From 8a8b4773734e5e466297feace2c7531f3dcc998d Mon Sep 17 00:00:00 2001
From: Gyorgy Szombathelyi <gyurco@freemail.hu>
Date: Thu, 26 Dec 2019 14:08:03 +0100
Subject: [PATCH] Galaxian Hw: mass update

- All variants in one source tree (except ZigZag)
- King & Balloon speech works
- Eliminated some gated clocks and generated clocks. Use T80se.
- Use common CPU and MiST components
---
 .../Z80 Based/AzurianAttack_MiST/Azurian.qpf  |   30 -
 .../Z80 Based/AzurianAttack_MiST/Azurian.qsf  |  186 --
 .../Z80 Based/AzurianAttack_MiST/Azurian.srf  |   54 -
 .../Z80 Based/AzurianAttack_MiST/README.txt   |   24 -
 .../AzurianAttack_MiST/Release/Azurian.rbf    |  Bin 306194 -> 0 bytes
 .../Z80 Based/AzurianAttack_MiST/clean.bat    |   37 -
 .../AzurianAttack_MiST/rtl/Azurian.sv         |  192 --
 .../AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd    |  534 -----
 .../AzurianAttack_MiST/rtl/ROM/GAL_HIT.vhd    |  534 -----
 .../AzurianAttack_MiST/rtl/build_id.tcl       |   35 -
 .../AzurianAttack_MiST/rtl/cpu/T80.vhd        | 1093 ---------
 .../AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd    |  371 ---
 .../AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd  | 2026 -----------------
 .../AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd   |  220 --
 .../AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd    |  105 -
 .../AzurianAttack_MiST/rtl/cpu/T80as.vhd      |  283 ---
 .../AzurianAttack_MiST/rtl/cpu/T80sed.vhd     |  179 --
 .../Z80 Based/AzurianAttack_MiST/rtl/dac.vhd  |   71 -
 .../AzurianAttack_MiST/rtl/dpram.vhd          |   75 -
 .../AzurianAttack_MiST/rtl/galaxian.vhd       |  446 ----
 .../Z80 Based/AzurianAttack_MiST/rtl/hq2x.sv  |  454 ----
 .../AzurianAttack_MiST/rtl/mc_adec.vhd        |  251 --
 .../AzurianAttack_MiST/rtl/mc_bram.vhd        |  182 --
 .../AzurianAttack_MiST/rtl/mc_clocks.vhd      |   85 -
 .../AzurianAttack_MiST/rtl/mc_col_pal.vhd     |   78 -
 .../AzurianAttack_MiST/rtl/mc_hv_count.vhd    |  145 --
 .../AzurianAttack_MiST/rtl/mc_inport.vhd      |   74 -
 .../AzurianAttack_MiST/rtl/mc_ld_pls.vhd      |  115 -
 .../AzurianAttack_MiST/rtl/mc_logic.vhd       |   92 -
 .../AzurianAttack_MiST/rtl/mc_missile.vhd     |  107 -
 .../AzurianAttack_MiST/rtl/mc_sound_a.vhd     |  117 -
 .../AzurianAttack_MiST/rtl/mc_sound_b.vhd     |  253 --
 .../AzurianAttack_MiST/rtl/mc_sound_vco.vhd   |   49 -
 .../AzurianAttack_MiST/rtl/mc_stars.vhd       |   90 -
 .../AzurianAttack_MiST/rtl/mc_video.vhd       |  433 ----
 .../AzurianAttack_MiST/rtl/mist_io.v          |  530 -----
 .../Z80 Based/AzurianAttack_MiST/rtl/osd.v    |  194 --
 .../Z80 Based/AzurianAttack_MiST/rtl/pll.qip  |    4 -
 .../Z80 Based/AzurianAttack_MiST/rtl/pll.vhd  |  451 ----
 .../AzurianAttack_MiST/rtl/scandoubler.v      |  194 --
 .../AzurianAttack_MiST/rtl/sine_package.vhd   |  152 --
 .../AzurianAttack_MiST/rtl/spram.vhd          |   55 -
 .../AzurianAttack_MiST/rtl/video_mixer.sv     |  243 --
 .../Z80 Based/BlackHole_MiST/BlackHole.qpf    |   30 -
 .../Z80 Based/BlackHole_MiST/BlackHole.qsf    |  190 --
 .../Z80 Based/BlackHole_MiST/BlackHole.srf    |   52 -
 .../Z80 Based/BlackHole_MiST/README.txt       |   24 -
 .../BlackHole_MiST/Release/BlackHole.rbf      |  Bin 302464 -> 0 bytes
 .../Z80 Based/BlackHole_MiST/clean.bat        |   37 -
 .../Z80 Based/BlackHole_MiST/rtl/BlackHole.sv |  192 --
 .../BlackHole_MiST/rtl/ROM/GAL_FIR.vhd        |  534 -----
 .../BlackHole_MiST/rtl/ROM/GAL_HIT.vhd        |  534 -----
 .../Z80 Based/BlackHole_MiST/rtl/build_id.tcl |   35 -
 .../Z80 Based/BlackHole_MiST/rtl/cpu/T80.vhd  | 1093 ---------
 .../BlackHole_MiST/rtl/cpu/T80_ALU.vhd        |  371 ---
 .../BlackHole_MiST/rtl/cpu/T80_MCode.vhd      | 2026 -----------------
 .../BlackHole_MiST/rtl/cpu/T80_Pack.vhd       |  220 --
 .../BlackHole_MiST/rtl/cpu/T80_Reg.vhd        |  105 -
 .../BlackHole_MiST/rtl/cpu/T80as.vhd          |  283 ---
 .../BlackHole_MiST/rtl/cpu/T80sed.vhd         |  179 --
 .../Z80 Based/BlackHole_MiST/rtl/dac.vhd      |   71 -
 .../Z80 Based/BlackHole_MiST/rtl/dpram.vhd    |   75 -
 .../Z80 Based/BlackHole_MiST/rtl/galaxian.vhd |  446 ----
 .../Z80 Based/BlackHole_MiST/rtl/hq2x.sv      |  454 ----
 .../Z80 Based/BlackHole_MiST/rtl/mc_adec.vhd  |  251 --
 .../Z80 Based/BlackHole_MiST/rtl/mc_bram.vhd  |  182 --
 .../BlackHole_MiST/rtl/mc_clocks.vhd          |   88 -
 .../BlackHole_MiST/rtl/mc_col_pal.vhd         |   78 -
 .../BlackHole_MiST/rtl/mc_hv_count.vhd        |  145 --
 .../BlackHole_MiST/rtl/mc_inport.vhd          |   72 -
 .../BlackHole_MiST/rtl/mc_ld_pls.vhd          |  115 -
 .../Z80 Based/BlackHole_MiST/rtl/mc_logic.vhd |   92 -
 .../BlackHole_MiST/rtl/mc_missile.vhd         |  107 -
 .../BlackHole_MiST/rtl/mc_sound_a.vhd         |  117 -
 .../BlackHole_MiST/rtl/mc_sound_b.vhd         |  253 --
 .../BlackHole_MiST/rtl/mc_sound_vco.vhd       |   49 -
 .../Z80 Based/BlackHole_MiST/rtl/mc_stars.vhd |   90 -
 .../Z80 Based/BlackHole_MiST/rtl/mc_video.vhd |  433 ----
 .../Z80 Based/BlackHole_MiST/rtl/mist_io.v    |  530 -----
 .../Z80 Based/BlackHole_MiST/rtl/osd.v        |  194 --
 .../Z80 Based/BlackHole_MiST/rtl/pll.qip      |    4 -
 .../Z80 Based/BlackHole_MiST/rtl/pll.vhd      |  451 ----
 .../BlackHole_MiST/rtl/scandoubler.v          |  194 --
 .../BlackHole_MiST/rtl/sine_package.vhd       |  152 --
 .../Z80 Based/BlackHole_MiST/rtl/spram.vhd    |   55 -
 .../BlackHole_MiST/rtl/video_mixer.sv         |  243 --
 .../Z80 Based/Catacomb_MiST/Catacomb.qpf      |   30 -
 .../Z80 Based/Catacomb_MiST/Catacomb.qsf      |  190 --
 .../Z80 Based/Catacomb_MiST/Catacomb.srf      |   54 -
 .../Z80 Based/Catacomb_MiST/README.txt        |   24 -
 .../Catacomb_MiST/Release/Catacomb.rbf        |  Bin 323153 -> 0 bytes
 .../Z80 Based/Catacomb_MiST/clean.bat         |   37 -
 .../Z80 Based/Catacomb_MiST/rtl/Catacomb.sv   |  192 --
 .../Catacomb_MiST/rtl/ROM/GAL_FIR.vhd         |  534 -----
 .../Catacomb_MiST/rtl/ROM/GAL_HIT.vhd         |  534 -----
 .../Z80 Based/Catacomb_MiST/rtl/build_id.tcl  |   35 -
 .../Z80 Based/Catacomb_MiST/rtl/cpu/T80.vhd   | 1093 ---------
 .../Catacomb_MiST/rtl/cpu/T80_ALU.vhd         |  371 ---
 .../Catacomb_MiST/rtl/cpu/T80_MCode.vhd       | 2026 -----------------
 .../Catacomb_MiST/rtl/cpu/T80_Pack.vhd        |  220 --
 .../Catacomb_MiST/rtl/cpu/T80_Reg.vhd         |  105 -
 .../Z80 Based/Catacomb_MiST/rtl/cpu/T80as.vhd |  283 ---
 .../Catacomb_MiST/rtl/cpu/T80sed.vhd          |  179 --
 .../Z80 Based/Catacomb_MiST/rtl/dac.vhd       |   71 -
 .../Z80 Based/Catacomb_MiST/rtl/dpram.vhd     |   75 -
 .../Z80 Based/Catacomb_MiST/rtl/galaxian.vhd  |  446 ----
 .../Z80 Based/Catacomb_MiST/rtl/hq2x.sv       |  454 ----
 .../Z80 Based/Catacomb_MiST/rtl/mc_adec.vhd   |  251 --
 .../Z80 Based/Catacomb_MiST/rtl/mc_bram.vhd   |  182 --
 .../Z80 Based/Catacomb_MiST/rtl/mc_clocks.vhd |   85 -
 .../Catacomb_MiST/rtl/mc_col_pal.vhd          |   78 -
 .../Catacomb_MiST/rtl/mc_hv_count.vhd         |  145 --
 .../Z80 Based/Catacomb_MiST/rtl/mc_inport.vhd |   74 -
 .../Z80 Based/Catacomb_MiST/rtl/mc_ld_pls.vhd |  115 -
 .../Z80 Based/Catacomb_MiST/rtl/mc_logic.vhd  |   92 -
 .../Catacomb_MiST/rtl/mc_missile.vhd          |  107 -
 .../Catacomb_MiST/rtl/mc_sound_a.vhd          |  117 -
 .../Catacomb_MiST/rtl/mc_sound_b.vhd          |  253 --
 .../Catacomb_MiST/rtl/mc_sound_vco.vhd        |   49 -
 .../Z80 Based/Catacomb_MiST/rtl/mc_stars.vhd  |   90 -
 .../Z80 Based/Catacomb_MiST/rtl/mc_video.vhd  |  433 ----
 .../Z80 Based/Catacomb_MiST/rtl/mist_io.v     |  530 -----
 .../Z80 Based/Catacomb_MiST/rtl/osd.v         |  194 --
 .../Z80 Based/Catacomb_MiST/rtl/pll.vhd       |  451 ----
 .../Z80 Based/Catacomb_MiST/rtl/scandoubler.v |  194 --
 .../Catacomb_MiST/rtl/sine_package.vhd        |  152 --
 .../Z80 Based/Catacomb_MiST/rtl/spram.vhd     |   55 -
 .../Catacomb_MiST/rtl/video_mixer.sv          |  243 --
 .../Z80 Based/ChewingGum_MiST/ChewingGum.qpf  |   30 -
 .../Z80 Based/ChewingGum_MiST/ChewingGum.qsf  |  187 --
 .../Z80 Based/ChewingGum_MiST/ChewingGum.srf  |   57 -
 .../Z80 Based/ChewingGum_MiST/README.txt      |   24 -
 .../ChewingGum_MiST/Release/ChewingGum.rbf    |  Bin 271799 -> 0 bytes
 .../Z80 Based/ChewingGum_MiST/clean.bat       |   37 -
 .../ChewingGum_MiST/rtl/ChewingGum_MiST.sv    |  192 --
 .../Z80 Based/ChewingGum_MiST/rtl/Pisces.sv   |  193 --
 .../rtl/TripleDrawPoker_MiST.sv               |  192 --
 .../ChewingGum_MiST/rtl/build_id.tcl          |   35 -
 .../Z80 Based/ChewingGum_MiST/rtl/cpu/T80.vhd | 1093 ---------
 .../ChewingGum_MiST/rtl/cpu/T80_ALU.vhd       |  371 ---
 .../ChewingGum_MiST/rtl/cpu/T80_MCode.vhd     | 2026 -----------------
 .../ChewingGum_MiST/rtl/cpu/T80_Pack.vhd      |  220 --
 .../ChewingGum_MiST/rtl/cpu/T80_Reg.vhd       |  105 -
 .../ChewingGum_MiST/rtl/cpu/T80as.vhd         |  283 ---
 .../ChewingGum_MiST/rtl/cpu/T80sed.vhd        |  179 --
 .../Z80 Based/ChewingGum_MiST/rtl/dac.vhd     |   71 -
 .../Z80 Based/ChewingGum_MiST/rtl/dpram.vhd   |   75 -
 .../ChewingGum_MiST/rtl/galaxian.vhd          |  442 ----
 .../Z80 Based/ChewingGum_MiST/rtl/hq2x.sv     |  454 ----
 .../Z80 Based/ChewingGum_MiST/rtl/mc_adec.vhd |  251 --
 .../Z80 Based/ChewingGum_MiST/rtl/mc_bram.vhd |  182 --
 .../ChewingGum_MiST/rtl/mc_clocks.vhd         |   85 -
 .../ChewingGum_MiST/rtl/mc_col_pal.vhd        |   75 -
 .../ChewingGum_MiST/rtl/mc_hv_count.vhd       |  145 --
 .../ChewingGum_MiST/rtl/mc_inport.vhd         |   86 -
 .../ChewingGum_MiST/rtl/mc_ld_pls.vhd         |  115 -
 .../ChewingGum_MiST/rtl/mc_logic.vhd          |   92 -
 .../ChewingGum_MiST/rtl/mc_missile.vhd        |  107 -
 .../ChewingGum_MiST/rtl/mc_sound_a.vhd        |  117 -
 .../ChewingGum_MiST/rtl/mc_sound_b.vhd        |  253 --
 .../ChewingGum_MiST/rtl/mc_sound_vco.vhd      |   49 -
 .../ChewingGum_MiST/rtl/mc_stars.vhd          |   90 -
 .../ChewingGum_MiST/rtl/mc_video.vhd          |  430 ----
 .../Z80 Based/ChewingGum_MiST/rtl/mist_io.v   |  530 -----
 .../Z80 Based/ChewingGum_MiST/rtl/osd.v       |  194 --
 .../Z80 Based/ChewingGum_MiST/rtl/pll.vhd     |  451 ----
 .../ChewingGum_MiST/rtl/scandoubler.v         |  194 --
 .../ChewingGum_MiST/rtl/sine_package.vhd      |  152 --
 .../Z80 Based/ChewingGum_MiST/rtl/spram.vhd   |   55 -
 .../ChewingGum_MiST/rtl/tripledrawpoker.vhd   |  443 ----
 .../ChewingGum_MiST/rtl/video_mixer.sv        |  243 --
 .../Z80 Based/DevilFish_MiST/DevilFish.qpf    |   29 -
 .../Z80 Based/DevilFish_MiST/DevilFish.qsf    |  185 --
 .../Z80 Based/DevilFish_MiST/DevilFish.srf    |   51 -
 .../Z80 Based/DevilFish_MiST/README.txt       |   24 -
 .../DevilFish_MiST/Release/DevilFish.rbf      |  Bin 310161 -> 0 bytes
 .../Z80 Based/DevilFish_MiST/clean.bat        |   37 -
 .../Z80 Based/DevilFish_MiST/rtl/DevilFish.sv |  187 --
 .../DevilFish_MiST/rtl/ROM/GAL_FIR.vhd        |  534 -----
 .../DevilFish_MiST/rtl/ROM/GAL_HIT.vhd        |  534 -----
 .../Z80 Based/DevilFish_MiST/rtl/build_id.tcl |   35 -
 .../Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd  | 1093 ---------
 .../DevilFish_MiST/rtl/cpu/T80_ALU.vhd        |  371 ---
 .../DevilFish_MiST/rtl/cpu/T80_MCode.vhd      | 2026 -----------------
 .../DevilFish_MiST/rtl/cpu/T80_Pack.vhd       |  220 --
 .../DevilFish_MiST/rtl/cpu/T80_Reg.vhd        |  105 -
 .../DevilFish_MiST/rtl/cpu/T80as.vhd          |  283 ---
 .../DevilFish_MiST/rtl/cpu/T80sed.vhd         |  179 --
 .../Z80 Based/DevilFish_MiST/rtl/dpram.vhd    |   75 -
 .../Z80 Based/DevilFish_MiST/rtl/galaxian.vhd |  452 ----
 .../Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd  |  251 --
 .../Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd  |  182 --
 .../DevilFish_MiST/rtl/mc_clocks.vhd          |   88 -
 .../DevilFish_MiST/rtl/mc_col_pal.vhd         |   78 -
 .../DevilFish_MiST/rtl/mc_hv_count.vhd        |  145 --
 .../DevilFish_MiST/rtl/mc_inport.vhd          |   78 -
 .../DevilFish_MiST/rtl/mc_ld_pls.vhd          |  115 -
 .../Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd |   92 -
 .../DevilFish_MiST/rtl/mc_missile.vhd         |  107 -
 .../DevilFish_MiST/rtl/mc_sound_a.vhd         |  117 -
 .../DevilFish_MiST/rtl/mc_sound_b.vhd         |  253 --
 .../DevilFish_MiST/rtl/mc_sound_vco.vhd       |   49 -
 .../Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd |   90 -
 .../Z80 Based/DevilFish_MiST/rtl/mc_video.vhd |  434 ----
 .../Z80 Based/DevilFish_MiST/rtl/pll.qip      |    4 -
 .../Z80 Based/DevilFish_MiST/rtl/pll.vhd      |  451 ----
 .../DevilFish_MiST/rtl/sine_package.vhd       |  152 --
 .../Z80 Based/DevilFish_MiST/rtl/spram.vhd    |   55 -
 .../Z80 Based/Galaxian_MiST/Galaxian.qsf      |  141 +-
 .../Z80 Based/Galaxian_MiST/Galaxian.sdc      |  126 +
 .../Z80 Based/Galaxian_MiST/Galaxian.srf      |   54 -
 .../Galaxian_MiST/Release/Galaxian.rbf        |  Bin 298354 -> 0 bytes
 .../Z80 Based/Galaxian_MiST/buildall.sh       |   25 +
 .../Galaxian_MiST/rtl/Galaxian_MiST.sv        |  163 +-
 .../Z80 Based/Galaxian_MiST/rtl/ROM/ROMS.vhd  |  292 +++
 .../rtl/ROM/azurian/AZURIAN_1H.vhd}           |    4 +-
 .../rtl/ROM/azurian/AZURIAN_1K.vhd}           |    4 +-
 .../rtl/ROM/azurian/AZURIAN_6L.vhd}           |    4 +-
 .../rtl/ROM/azurian}/ROM_PGM_0.vhd            |    4 +-
 .../rtl/ROM/blackhole/BLACKHOLE_1H.vhd}       |    4 +-
 .../rtl/ROM/blackhole/BLACKHOLE_1K.vhd}       |    4 +-
 .../BLACKHOLE_6L.vhd}                         |    4 +-
 .../rtl/ROM/blackhole}/ROM_PGM_0.vhd          |    4 +-
 .../rtl/ROM/catacomb/CATACOMB_1H.vhd}         |    4 +-
 .../rtl/ROM/catacomb/CATACOMB_1K.vhd}         |    4 +-
 .../rtl/ROM/catacomb/CATACOMB_6L.vhd}         |    4 +-
 .../rtl/ROM/catacomb}/ROM_PGM_0.vhd           |    4 +-
 .../rtl/ROM/chewinggum}/col.vhd               |    4 +-
 .../rtl/ROM/chewinggum}/h.vhd                 |    4 +-
 .../rtl/ROM/chewinggum}/k.vhd                 |    4 +-
 .../rtl/ROM/chewinggum}/prog.vhd              |    4 +-
 .../rtl/ROM/devilfish/DEVILFISH_1H.vhd}       |    4 +-
 .../rtl/ROM/devilfish/DEVILFISH_1K.vhd}       |    4 +-
 .../rtl/ROM/devilfish/DEVILFISH_6L.vhd}       |    4 +-
 .../rtl/ROM/devilfish}/ROM_PGM_0.vhd          |    4 +-
 .../rtl/ROM/{ => galaxian}/GALAXIAN_1H.vhd    |    0
 .../rtl/ROM/{ => galaxian}/GALAXIAN_1K.vhd    |    0
 .../rtl/ROM/galaxian}/GALAXIAN_6L.vhd         |    0
 .../rtl/ROM/{ => galaxian}/ROM_PGM_0.vhd      |    4 +-
 .../rtl/ROM/kingbaloon}/col.vhd               |    4 +-
 .../rtl/ROM/kingbaloon}/kbe1-4.vhd            |    0
 .../rtl/ROM/kingbaloon}/kbe2-5.vhd            |    0
 .../rtl/ROM/kingbaloon}/kbe3-6.vhd            |    0
 .../rtl/ROM/kingbaloon}/prog.vhd              |    4 +-
 .../rtl/ROM/kingbaloon}/rom_h.vhd             |    4 +-
 .../rtl/ROM/kingbaloon}/rom_k.vhd             |    4 +-
 .../rtl/ROM/mooncresta/MOONCR_1H.vhd}         |    4 +-
 .../rtl/ROM/mooncresta/MOONCR_1K.vhd}         |    4 +-
 .../rtl/ROM/mooncresta/MOONCR_6L.vhd}         |    4 +-
 .../rtl/ROM/mooncresta}/ROM_PGM_0.vhd         |    4 +-
 .../ROM/mrdonightmare/MRDONIGHTMARE_1H.vhd}   |    4 +-
 .../ROM/mrdonightmare/MRDONIGHTMARE_1K.vhd}   |    4 +-
 .../ROM/mrdonightmare/MRDONIGHTMARE_6L.vhd}   |    4 +-
 .../rtl/ROM/mrdonightmare}/ROM_PGM_0.vhd      |    4 +-
 .../rtl/ROM/omega/OMEGA_1H.vhd}               |    4 +-
 .../rtl/ROM/omega/OMEGA_1K.vhd}               |    4 +-
 .../rtl/ROM/omega/OMEGA_6L.vhd}               |    4 +-
 .../rtl/ROM/omega}/ROM_PGM_0.vhd              |    4 +-
 .../rtl/ROM/orbitron/ORBITRON_1H.vhd}         |    4 +-
 .../rtl/ROM/orbitron/ORBITRON_1K.vhd}         |    4 +-
 .../rtl/ROM/orbitron/ORBITRON_6L.vhd}         |    4 +-
 .../rtl/ROM/orbitron}/ROM_PGM_0.vhd           |    4 +-
 .../rtl/ROM/pisces/PISCES_1H.vhd}             |    4 +-
 .../rtl/ROM/pisces/PISCES_1K.vhd}             |    4 +-
 .../rtl/ROM/pisces/PISCES_6L.vhd}             |    4 +-
 .../rtl/ROM/pisces}/ROM_PGM_0.vhd             |    4 +-
 .../tripledrawpoker/TRIPLEDRAWPOKER_1H.vhd    |  150 ++
 .../tripledrawpoker/TRIPLEDRAWPOKER_1K.vhd    |  150 ++
 .../tripledrawpoker/TRIPLEDRAWPOKER_6L.vhd    |   24 +
 .../TRIPLEDRAWPOKER_ROM_PGM_0.vhd             |  790 +++++++
 .../rtl/ROM/uniwars}/ROM_PGM_0.vhd            |    4 +-
 .../rtl/ROM/uniwars/UNIWARS_1H.vhd}           |    4 +-
 .../rtl/ROM/uniwars/UNIWARS_1K.vhd}           |    4 +-
 .../rtl/ROM/uniwars/UNIWARS_6L.vhd}           |    4 +-
 .../rtl/ROM/victory}/col.vhd                  |    4 +-
 .../rtl/ROM/victory}/h_rom.vhd                |    4 +-
 .../rtl/ROM/victory}/k_rom.vhd                |    4 +-
 .../rtl/ROM/victory}/prog.vhd                 |    4 +-
 .../rtl/ROM/warofbugs}/ROM_PGM_0.vhd          |   21 +-
 .../rtl/ROM/warofbugs/WAROFBUGS_1H.vhd}       |    4 +-
 .../rtl/ROM/warofbugs/WAROFBUGS_1K.vhd}       |    4 +-
 .../rtl/ROM/warofbugs/WAROFBUGS_6L.vhd}       |    4 +-
 .../Galaxian_MiST/rtl/ROM/zigzag/col.vhd      |   24 +
 .../Galaxian_MiST/rtl/ROM/zigzag/prog.vhd     | 1046 +++++++++
 .../Galaxian_MiST/rtl/ROM/zigzag/rom_h.vhd    |  278 +++
 .../Galaxian_MiST/rtl/ROM/zigzag/rom_k.vhd    |  278 +++
 .../Z80 Based/Galaxian_MiST/rtl/cpu/T80.vhd   | 1093 ---------
 .../Galaxian_MiST/rtl/cpu/T80_ALU.vhd         |  371 ---
 .../Galaxian_MiST/rtl/cpu/T80_MCode.vhd       | 2026 -----------------
 .../Galaxian_MiST/rtl/cpu/T80_Pack.vhd        |  220 --
 .../Galaxian_MiST/rtl/cpu/T80_Reg.vhd         |  105 -
 .../Z80 Based/Galaxian_MiST/rtl/cpu/T80as.vhd |  283 ---
 .../Galaxian_MiST/rtl/cpu/T80sed.vhd          |  179 --
 .../Z80 Based/Galaxian_MiST/rtl/dac.vhd       |   71 -
 .../Z80 Based/Galaxian_MiST/rtl/dpram.vhd     |    2 +-
 .../Z80 Based/Galaxian_MiST/rtl/galaxian.vhd  |  193 +-
 .../Z80 Based/Galaxian_MiST/rtl/hq2x.sv       |  454 ----
 .../Z80 Based/Galaxian_MiST/rtl/kb_synth.vhd  |  136 ++
 .../Z80 Based/Galaxian_MiST/rtl/mc_adec.vhd   |   14 +-
 .../Z80 Based/Galaxian_MiST/rtl/mc_bram.vhd   |   20 +-
 .../Galaxian_MiST/rtl/mc_col_pal.vhd          |   25 +-
 .../Galaxian_MiST/rtl/mc_hv_count.vhd         |   61 +-
 .../Z80 Based/Galaxian_MiST/rtl/mc_inport.vhd |   35 +-
 .../Galaxian_MiST/rtl/mc_missile.vhd          |    1 -
 .../Z80 Based/Galaxian_MiST/rtl/mc_stars.vhd  |    4 +-
 .../Z80 Based/Galaxian_MiST/rtl/mc_video.vhd  |   63 +-
 .../Z80 Based/Galaxian_MiST/rtl/mist_io.v     |  530 -----
 .../Z80 Based/Galaxian_MiST/rtl/osd.v         |  194 --
 .../Z80 Based/Galaxian_MiST/rtl/scandoubler.v |  194 --
 .../Galaxian_MiST/rtl/video_mixer.sv          |  243 --
 .../Z80 Based/Galaxian_MiST/rtl/ym2149.sv     |  331 +++
 .../Z80 Based/KingBaloon_MiST/KingBaloon.qpf  |   31 -
 .../Z80 Based/KingBaloon_MiST/KingBaloon.qsf  |  194 --
 .../Z80 Based/KingBaloon_MiST/KingBaloon.srf  |   56 -
 .../Z80 Based/KingBaloon_MiST/README.txt      |   26 -
 .../KingBaloon_MiST/Release/KingBaloon.rbf    |  Bin 333436 -> 0 bytes
 .../Z80 Based/KingBaloon_MiST/clean.bat       |   37 -
 .../KingBaloon_MiST/rtl/KingBalloon_MiST.sv   |  194 --
 .../KingBaloon_MiST/rtl/ROM/GAL_FIR.vhd       |  534 -----
 .../KingBaloon_MiST/rtl/ROM/GAL_HIT.vhd       |  534 -----
 .../KingBaloon_MiST/rtl/ROM/sound.vhd         |  534 -----
 .../KingBaloon_MiST/rtl/build_id.tcl          |   35 -
 .../Z80 Based/KingBaloon_MiST/rtl/cpu/T80.vhd | 1093 ---------
 .../KingBaloon_MiST/rtl/cpu/T80_ALU.vhd       |  371 ---
 .../KingBaloon_MiST/rtl/cpu/T80_MCode.vhd     | 2026 -----------------
 .../KingBaloon_MiST/rtl/cpu/T80_Pack.vhd      |  220 --
 .../KingBaloon_MiST/rtl/cpu/T80_Reg.vhd       |  105 -
 .../KingBaloon_MiST/rtl/cpu/T80as.vhd         |  283 ---
 .../KingBaloon_MiST/rtl/cpu/T80sed.vhd        |  179 --
 .../Z80 Based/KingBaloon_MiST/rtl/dac.vhd     |   71 -
 .../Z80 Based/KingBaloon_MiST/rtl/dpram.vhd   |   75 -
 .../Z80 Based/KingBaloon_MiST/rtl/hq2x.sv     |  454 ----
 .../KingBaloon_MiST/rtl/kb_synth.vhd          |  160 --
 .../KingBaloon_MiST/rtl/kingballon.vhd        |  455 ----
 .../Z80 Based/KingBaloon_MiST/rtl/mc_adec.vhd |  251 --
 .../Z80 Based/KingBaloon_MiST/rtl/mc_bram.vhd |  182 --
 .../KingBaloon_MiST/rtl/mc_clocks.vhd         |   85 -
 .../KingBaloon_MiST/rtl/mc_col_pal.vhd        |   78 -
 .../KingBaloon_MiST/rtl/mc_hv_count.vhd       |  145 --
 .../KingBaloon_MiST/rtl/mc_inport.vhd         |   74 -
 .../KingBaloon_MiST/rtl/mc_ld_pls.vhd         |  115 -
 .../KingBaloon_MiST/rtl/mc_logic.vhd          |   92 -
 .../KingBaloon_MiST/rtl/mc_missile.vhd        |  107 -
 .../KingBaloon_MiST/rtl/mc_sound_a.vhd        |  117 -
 .../KingBaloon_MiST/rtl/mc_sound_b.vhd        |  253 --
 .../KingBaloon_MiST/rtl/mc_sound_vco.vhd      |   49 -
 .../KingBaloon_MiST/rtl/mc_stars.vhd          |   90 -
 .../KingBaloon_MiST/rtl/mc_video.vhd          |  431 ----
 .../Z80 Based/KingBaloon_MiST/rtl/mist_io.v   |  530 -----
 .../Z80 Based/KingBaloon_MiST/rtl/osd.v       |  194 --
 .../Z80 Based/KingBaloon_MiST/rtl/pll.vhd     |  451 ----
 .../KingBaloon_MiST/rtl/scandoubler.v         |  194 --
 .../KingBaloon_MiST/rtl/sine_package.vhd      |  152 --
 .../Z80 Based/KingBaloon_MiST/rtl/spram.vhd   |   55 -
 .../KingBaloon_MiST/rtl/ttl_74138.vhd         |   48 -
 .../KingBaloon_MiST/rtl/ttl_74273.vhd         |  136 --
 .../KingBaloon_MiST/rtl/ttl_74367.vhd         |  122 -
 .../KingBaloon_MiST/rtl/video_mixer.sv        |  243 --
 .../Z80 Based/MoonCresta_MiST/MoonCresta.qpf  |   31 -
 .../Z80 Based/MoonCresta_MiST/MoonCresta.qsf  |  190 --
 .../Z80 Based/MoonCresta_MiST/MoonCresta.srf  |   51 -
 .../Z80 Based/MoonCresta_MiST/README.txt      |   24 -
 .../MoonCresta_MiST/Release/MoonCresta.rbf    |  Bin 308269 -> 0 bytes
 .../Z80 Based/MoonCresta_MiST/clean.bat       |   37 -
 .../MoonCresta_MiST/rtl/MoonCresta.sv         |  193 --
 .../MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd       |  534 -----
 .../MoonCresta_MiST/rtl/ROM/GAL_HIT.vhd       |  534 -----
 .../MoonCresta_MiST/rtl/build_id.tcl          |   35 -
 .../Z80 Based/MoonCresta_MiST/rtl/cpu/T80.vhd | 1093 ---------
 .../MoonCresta_MiST/rtl/cpu/T80_ALU.vhd       |  371 ---
 .../MoonCresta_MiST/rtl/cpu/T80_MCode.vhd     | 2026 -----------------
 .../MoonCresta_MiST/rtl/cpu/T80_Pack.vhd      |  220 --
 .../MoonCresta_MiST/rtl/cpu/T80_Reg.vhd       |  105 -
 .../MoonCresta_MiST/rtl/cpu/T80as.vhd         |  283 ---
 .../MoonCresta_MiST/rtl/cpu/T80sed.vhd        |  179 --
 .../Z80 Based/MoonCresta_MiST/rtl/dac.vhd     |   71 -
 .../Z80 Based/MoonCresta_MiST/rtl/dpram.vhd   |   75 -
 .../MoonCresta_MiST/rtl/galaxian.vhd          |  446 ----
 .../Z80 Based/MoonCresta_MiST/rtl/hq2x.sv     |  454 ----
 .../Z80 Based/MoonCresta_MiST/rtl/mc_adec.vhd |  251 --
 .../Z80 Based/MoonCresta_MiST/rtl/mc_bram.vhd |  182 --
 .../MoonCresta_MiST/rtl/mc_clocks.vhd         |   88 -
 .../MoonCresta_MiST/rtl/mc_col_pal.vhd        |   78 -
 .../MoonCresta_MiST/rtl/mc_hv_count.vhd       |  145 --
 .../MoonCresta_MiST/rtl/mc_inport.vhd         |   74 -
 .../MoonCresta_MiST/rtl/mc_ld_pls.vhd         |  115 -
 .../MoonCresta_MiST/rtl/mc_logic.vhd          |   92 -
 .../MoonCresta_MiST/rtl/mc_missile.vhd        |  107 -
 .../MoonCresta_MiST/rtl/mc_sound_a.vhd        |  117 -
 .../MoonCresta_MiST/rtl/mc_sound_b.vhd        |  253 --
 .../MoonCresta_MiST/rtl/mc_sound_vco.vhd      |   49 -
 .../MoonCresta_MiST/rtl/mc_stars.vhd          |   90 -
 .../MoonCresta_MiST/rtl/mc_video.vhd          |  447 ----
 .../Z80 Based/MoonCresta_MiST/rtl/mist_io.v   |  530 -----
 .../Z80 Based/MoonCresta_MiST/rtl/osd.v       |  194 --
 .../Z80 Based/MoonCresta_MiST/rtl/pll.vhd     |  451 ----
 .../MoonCresta_MiST/rtl/scandoubler.v         |  195 --
 .../MoonCresta_MiST/rtl/sine_package.vhd      |  152 --
 .../Z80 Based/MoonCresta_MiST/rtl/spram.vhd   |   55 -
 .../MoonCresta_MiST/rtl/video_mixer.sv        |  243 --
 .../MrDoNightmare_MiST/MrDoNightmare.qpf      |   30 -
 .../MrDoNightmare_MiST/MrDoNightmare.qsf      |  190 --
 .../MrDoNightmare_MiST/MrDoNightmare.srf      |   54 -
 .../Z80 Based/MrDoNightmare_MiST/README.txt   |   24 -
 .../Release/MrDoNightmare.rbf                 |  Bin 295678 -> 0 bytes
 .../Z80 Based/MrDoNightmare_MiST/clean.bat    |   37 -
 .../MrDoNightmare_MiST/rtl/MrDoNightmare.sv   |  192 --
 .../MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd    |  534 -----
 .../MrDoNightmare_MiST/rtl/ROM/GAL_HIT.vhd    |  534 -----
 .../MrDoNightmare_MiST/rtl/build_id.tcl       |   35 -
 .../MrDoNightmare_MiST/rtl/cpu/T80.vhd        | 1093 ---------
 .../MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd    |  371 ---
 .../MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd  | 2026 -----------------
 .../MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd   |  220 --
 .../MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd    |  105 -
 .../MrDoNightmare_MiST/rtl/cpu/T80as.vhd      |  283 ---
 .../MrDoNightmare_MiST/rtl/cpu/T80sed.vhd     |  179 --
 .../Z80 Based/MrDoNightmare_MiST/rtl/dac.vhd  |   71 -
 .../MrDoNightmare_MiST/rtl/dpram.vhd          |   75 -
 .../MrDoNightmare_MiST/rtl/galaxian.vhd       |  446 ----
 .../Z80 Based/MrDoNightmare_MiST/rtl/hq2x.sv  |  454 ----
 .../MrDoNightmare_MiST/rtl/mc_adec.vhd        |  251 --
 .../MrDoNightmare_MiST/rtl/mc_bram.vhd        |  182 --
 .../MrDoNightmare_MiST/rtl/mc_clocks.vhd      |   88 -
 .../MrDoNightmare_MiST/rtl/mc_col_pal.vhd     |   78 -
 .../MrDoNightmare_MiST/rtl/mc_hv_count.vhd    |  145 --
 .../MrDoNightmare_MiST/rtl/mc_inport.vhd      |   71 -
 .../MrDoNightmare_MiST/rtl/mc_ld_pls.vhd      |  115 -
 .../MrDoNightmare_MiST/rtl/mc_logic.vhd       |   92 -
 .../MrDoNightmare_MiST/rtl/mc_missile.vhd     |  107 -
 .../MrDoNightmare_MiST/rtl/mc_sound_a.vhd     |  117 -
 .../MrDoNightmare_MiST/rtl/mc_sound_b.vhd     |  253 --
 .../MrDoNightmare_MiST/rtl/mc_sound_vco.vhd   |   49 -
 .../MrDoNightmare_MiST/rtl/mc_stars.vhd       |   90 -
 .../MrDoNightmare_MiST/rtl/mc_video.vhd       |  433 ----
 .../MrDoNightmare_MiST/rtl/mist_io.v          |  530 -----
 .../Z80 Based/MrDoNightmare_MiST/rtl/osd.v    |  194 --
 .../Z80 Based/MrDoNightmare_MiST/rtl/pll.vhd  |  451 ----
 .../MrDoNightmare_MiST/rtl/scandoubler.v      |  194 --
 .../MrDoNightmare_MiST/rtl/sine_package.vhd   |  152 --
 .../MrDoNightmare_MiST/rtl/spram.vhd          |   55 -
 .../MrDoNightmare_MiST/rtl/video_mixer.sv     |  243 --
 .../Z80 Based/Omega_MiST/Omega.qpf            |   30 -
 .../Z80 Based/Omega_MiST/Omega.qsf            |  190 --
 .../Z80 Based/Omega_MiST/Omega.srf            |   54 -
 .../Z80 Based/Omega_MiST/README.txt           |   24 -
 .../Z80 Based/Omega_MiST/Release/Omega.rbf    |  Bin 301983 -> 0 bytes
 .../Z80 Based/Omega_MiST/clean.bat            |   37 -
 .../Z80 Based/Omega_MiST/rtl/Omega.sv         |  192 --
 .../Z80 Based/Omega_MiST/rtl/ROM/GAL_FIR.vhd  |  534 -----
 .../Z80 Based/Omega_MiST/rtl/ROM/GAL_HIT.vhd  |  534 -----
 .../Z80 Based/Omega_MiST/rtl/build_id.tcl     |   35 -
 .../Z80 Based/Omega_MiST/rtl/cpu/T80.vhd      | 1093 ---------
 .../Z80 Based/Omega_MiST/rtl/cpu/T80_ALU.vhd  |  371 ---
 .../Omega_MiST/rtl/cpu/T80_MCode.vhd          | 2026 -----------------
 .../Z80 Based/Omega_MiST/rtl/cpu/T80_Pack.vhd |  220 --
 .../Z80 Based/Omega_MiST/rtl/cpu/T80_Reg.vhd  |  105 -
 .../Z80 Based/Omega_MiST/rtl/cpu/T80as.vhd    |  283 ---
 .../Z80 Based/Omega_MiST/rtl/cpu/T80sed.vhd   |  179 --
 .../Z80 Based/Omega_MiST/rtl/dac.vhd          |   71 -
 .../Z80 Based/Omega_MiST/rtl/dpram.vhd        |   75 -
 .../Z80 Based/Omega_MiST/rtl/galaxian.vhd     |  446 ----
 .../Z80 Based/Omega_MiST/rtl/hq2x.sv          |  454 ----
 .../Z80 Based/Omega_MiST/rtl/mc_adec.vhd      |  251 --
 .../Z80 Based/Omega_MiST/rtl/mc_bram.vhd      |  182 --
 .../Z80 Based/Omega_MiST/rtl/mc_clocks.vhd    |   85 -
 .../Z80 Based/Omega_MiST/rtl/mc_col_pal.vhd   |   78 -
 .../Z80 Based/Omega_MiST/rtl/mc_hv_count.vhd  |  145 --
 .../Z80 Based/Omega_MiST/rtl/mc_inport.vhd    |   74 -
 .../Z80 Based/Omega_MiST/rtl/mc_ld_pls.vhd    |  115 -
 .../Z80 Based/Omega_MiST/rtl/mc_logic.vhd     |   92 -
 .../Z80 Based/Omega_MiST/rtl/mc_missile.vhd   |  107 -
 .../Z80 Based/Omega_MiST/rtl/mc_sound_a.vhd   |  117 -
 .../Z80 Based/Omega_MiST/rtl/mc_sound_b.vhd   |  253 --
 .../Z80 Based/Omega_MiST/rtl/mc_sound_vco.vhd |   49 -
 .../Z80 Based/Omega_MiST/rtl/mc_stars.vhd     |   90 -
 .../Z80 Based/Omega_MiST/rtl/mc_video.vhd     |  433 ----
 .../Z80 Based/Omega_MiST/rtl/mist_io.v        |  530 -----
 .../Z80 Based/Omega_MiST/rtl/osd.v            |  194 --
 .../Z80 Based/Omega_MiST/rtl/pll.vhd          |  451 ----
 .../Z80 Based/Omega_MiST/rtl/scandoubler.v    |  194 --
 .../Z80 Based/Omega_MiST/rtl/sine_package.vhd |  152 --
 .../Z80 Based/Omega_MiST/rtl/spram.vhd        |   55 -
 .../Z80 Based/Omega_MiST/rtl/video_mixer.sv   |  243 --
 .../Z80 Based/Orbitron_MiST/Orbitron.qpf      |   30 -
 .../Z80 Based/Orbitron_MiST/Orbitron.qsf      |  190 --
 .../Z80 Based/Orbitron_MiST/Orbitron.srf      |   51 -
 .../Z80 Based/Orbitron_MiST/README.txt        |   24 -
 .../Orbitron_MiST/Release/Orbitron.rbf        |  Bin 300739 -> 0 bytes
 .../Z80 Based/Orbitron_MiST/clean.bat         |   37 -
 .../Z80 Based/Orbitron_MiST/rtl/Orbitron.sv   |  193 --
 .../Orbitron_MiST/rtl/ROM/GAL_FIR.vhd         |  534 -----
 .../Orbitron_MiST/rtl/ROM/GAL_HIT.vhd         |  534 -----
 .../Z80 Based/Orbitron_MiST/rtl/build_id.tcl  |   35 -
 .../Z80 Based/Orbitron_MiST/rtl/cpu/T80.vhd   | 1093 ---------
 .../Orbitron_MiST/rtl/cpu/T80_ALU.vhd         |  371 ---
 .../Orbitron_MiST/rtl/cpu/T80_MCode.vhd       | 2026 -----------------
 .../Orbitron_MiST/rtl/cpu/T80_Pack.vhd        |  220 --
 .../Orbitron_MiST/rtl/cpu/T80_Reg.vhd         |  105 -
 .../Z80 Based/Orbitron_MiST/rtl/cpu/T80as.vhd |  283 ---
 .../Orbitron_MiST/rtl/cpu/T80sed.vhd          |  179 --
 .../Z80 Based/Orbitron_MiST/rtl/dac.vhd       |   71 -
 .../Z80 Based/Orbitron_MiST/rtl/dpram.vhd     |   75 -
 .../Z80 Based/Orbitron_MiST/rtl/galaxian.vhd  |  446 ----
 .../Z80 Based/Orbitron_MiST/rtl/hq2x.sv       |  454 ----
 .../Z80 Based/Orbitron_MiST/rtl/mc_adec.vhd   |  251 --
 .../Z80 Based/Orbitron_MiST/rtl/mc_bram.vhd   |  182 --
 .../Z80 Based/Orbitron_MiST/rtl/mc_clocks.vhd |   88 -
 .../Orbitron_MiST/rtl/mc_col_pal.vhd          |   78 -
 .../Orbitron_MiST/rtl/mc_hv_count.vhd         |  145 --
 .../Z80 Based/Orbitron_MiST/rtl/mc_inport.vhd |   74 -
 .../Z80 Based/Orbitron_MiST/rtl/mc_ld_pls.vhd |  115 -
 .../Z80 Based/Orbitron_MiST/rtl/mc_logic.vhd  |   92 -
 .../Orbitron_MiST/rtl/mc_missile.vhd          |  107 -
 .../Orbitron_MiST/rtl/mc_sound_a.vhd          |  117 -
 .../Orbitron_MiST/rtl/mc_sound_b.vhd          |  253 --
 .../Orbitron_MiST/rtl/mc_sound_vco.vhd        |   49 -
 .../Z80 Based/Orbitron_MiST/rtl/mc_stars.vhd  |   90 -
 .../Z80 Based/Orbitron_MiST/rtl/mc_video.vhd  |  433 ----
 .../Z80 Based/Orbitron_MiST/rtl/mist_io.v     |  530 -----
 .../Z80 Based/Orbitron_MiST/rtl/osd.v         |  194 --
 .../Z80 Based/Orbitron_MiST/rtl/pll.vhd       |  451 ----
 .../Z80 Based/Orbitron_MiST/rtl/scandoubler.v |  195 --
 .../Orbitron_MiST/rtl/sine_package.vhd        |  152 --
 .../Z80 Based/Orbitron_MiST/rtl/spram.vhd     |   55 -
 .../Orbitron_MiST/rtl/video_mixer.sv          |  243 --
 .../Z80 Based/Pisces_MiST/Pisces.qpf          |   31 -
 .../Z80 Based/Pisces_MiST/Pisces.qsf          |  190 --
 .../Z80 Based/Pisces_MiST/Pisces.srf          |   54 -
 .../Z80 Based/Pisces_MiST/README.txt          |   24 -
 .../Z80 Based/Pisces_MiST/Release/Pisces.rbf  |  Bin 316148 -> 0 bytes
 .../Z80 Based/Pisces_MiST/clean.bat           |   37 -
 .../Z80 Based/Pisces_MiST/rtl/Pisces.sv       |  193 --
 .../Z80 Based/Pisces_MiST/rtl/ROM/GAL_FIR.vhd |  534 -----
 .../Z80 Based/Pisces_MiST/rtl/ROM/GAL_HIT.vhd |  534 -----
 .../Z80 Based/Pisces_MiST/rtl/build_id.tcl    |   35 -
 .../Z80 Based/Pisces_MiST/rtl/cpu/T80.vhd     | 1093 ---------
 .../Z80 Based/Pisces_MiST/rtl/cpu/T80_ALU.vhd |  371 ---
 .../Pisces_MiST/rtl/cpu/T80_MCode.vhd         | 2026 -----------------
 .../Pisces_MiST/rtl/cpu/T80_Pack.vhd          |  220 --
 .../Z80 Based/Pisces_MiST/rtl/cpu/T80_Reg.vhd |  105 -
 .../Z80 Based/Pisces_MiST/rtl/cpu/T80as.vhd   |  283 ---
 .../Z80 Based/Pisces_MiST/rtl/cpu/T80sed.vhd  |  179 --
 .../Z80 Based/Pisces_MiST/rtl/dac.vhd         |   71 -
 .../Z80 Based/Pisces_MiST/rtl/dpram.vhd       |   75 -
 .../Z80 Based/Pisces_MiST/rtl/galaxian.vhd    |  448 ----
 .../Z80 Based/Pisces_MiST/rtl/hq2x.sv         |  454 ----
 .../Z80 Based/Pisces_MiST/rtl/mc_adec.vhd     |  251 --
 .../Z80 Based/Pisces_MiST/rtl/mc_bram.vhd     |  182 --
 .../Z80 Based/Pisces_MiST/rtl/mc_clocks.vhd   |   85 -
 .../Z80 Based/Pisces_MiST/rtl/mc_col_pal.vhd  |   78 -
 .../Z80 Based/Pisces_MiST/rtl/mc_hv_count.vhd |  145 --
 .../Z80 Based/Pisces_MiST/rtl/mc_inport.vhd   |   74 -
 .../Z80 Based/Pisces_MiST/rtl/mc_ld_pls.vhd   |  115 -
 .../Z80 Based/Pisces_MiST/rtl/mc_logic.vhd    |   92 -
 .../Z80 Based/Pisces_MiST/rtl/mc_missile.vhd  |  107 -
 .../Z80 Based/Pisces_MiST/rtl/mc_sound_a.vhd  |  117 -
 .../Z80 Based/Pisces_MiST/rtl/mc_sound_b.vhd  |  253 --
 .../Pisces_MiST/rtl/mc_sound_vco.vhd          |   49 -
 .../Z80 Based/Pisces_MiST/rtl/mc_stars.vhd    |   90 -
 .../Z80 Based/Pisces_MiST/rtl/mc_video.vhd    |  433 ----
 .../Z80 Based/Pisces_MiST/rtl/mist_io.v       |  530 -----
 .../Z80 Based/Pisces_MiST/rtl/osd.v           |  194 --
 .../Z80 Based/Pisces_MiST/rtl/pll.vhd         |  451 ----
 .../Z80 Based/Pisces_MiST/rtl/scandoubler.v   |  194 --
 .../Pisces_MiST/rtl/sine_package.vhd          |  152 --
 .../Z80 Based/Pisces_MiST/rtl/spram.vhd       |   55 -
 .../Z80 Based/Pisces_MiST/rtl/video_mixer.sv  |  243 --
 .../Z80 Based/TripleDrawPoker_MiST/README.txt |   24 -
 .../Release/TripleDrawPoker.rbf               |  Bin 270641 -> 0 bytes
 .../TripleDrawPoker_MiST/TripleDrawPoker.qpf  |   30 -
 .../TripleDrawPoker_MiST/TripleDrawPoker.qsf  |  184 --
 .../TripleDrawPoker_MiST/TripleDrawPoker.srf  |   54 -
 .../Z80 Based/TripleDrawPoker_MiST/clean.bat  |   37 -
 .../TripleDrawPoker_MiST/rtl/ROM/col.bin      |  Bin 32 -> 0 bytes
 .../TripleDrawPoker_MiST/rtl/ROM/col.hex      |    3 -
 .../TripleDrawPoker_MiST/rtl/ROM/h.bin        |  Bin 2048 -> 0 bytes
 .../TripleDrawPoker_MiST/rtl/ROM/h.hex        |  129 --
 .../TripleDrawPoker_MiST/rtl/ROM/k.bin        |  Bin 2048 -> 0 bytes
 .../TripleDrawPoker_MiST/rtl/ROM/k.hex        |  129 --
 .../TripleDrawPoker_MiST/rtl/ROM/prog.bin     |  Bin 12288 -> 0 bytes
 .../TripleDrawPoker_MiST/rtl/ROM/prog.hex     |  769 -------
 .../TripleDrawPoker_MiST/rtl/ROM/swap.exe     |  Bin 57344 -> 0 bytes
 .../rtl/TripleDrawPoker_MiST.sv               |  192 --
 .../TripleDrawPoker_MiST/rtl/build_id.tcl     |   35 -
 .../TripleDrawPoker_MiST/rtl/cpu/T80.vhd      | 1093 ---------
 .../TripleDrawPoker_MiST/rtl/cpu/T80_ALU.vhd  |  371 ---
 .../rtl/cpu/T80_MCode.vhd                     | 2026 -----------------
 .../TripleDrawPoker_MiST/rtl/cpu/T80_Pack.vhd |  220 --
 .../TripleDrawPoker_MiST/rtl/cpu/T80_Reg.vhd  |  105 -
 .../TripleDrawPoker_MiST/rtl/cpu/T80as.vhd    |  283 ---
 .../TripleDrawPoker_MiST/rtl/cpu/T80sed.vhd   |  179 --
 .../TripleDrawPoker_MiST/rtl/dac.vhd          |   71 -
 .../TripleDrawPoker_MiST/rtl/dpram.vhd        |   75 -
 .../TripleDrawPoker_MiST/rtl/hq2x.sv          |  454 ----
 .../TripleDrawPoker_MiST/rtl/mc_adec.vhd      |  251 --
 .../TripleDrawPoker_MiST/rtl/mc_bram.vhd      |  182 --
 .../TripleDrawPoker_MiST/rtl/mc_clocks.vhd    |   85 -
 .../TripleDrawPoker_MiST/rtl/mc_col_pal.vhd   |   83 -
 .../TripleDrawPoker_MiST/rtl/mc_hv_count.vhd  |  145 --
 .../TripleDrawPoker_MiST/rtl/mc_inport.vhd    |   86 -
 .../TripleDrawPoker_MiST/rtl/mc_ld_pls.vhd    |  115 -
 .../TripleDrawPoker_MiST/rtl/mc_logic.vhd     |   92 -
 .../TripleDrawPoker_MiST/rtl/mc_missile.vhd   |  107 -
 .../TripleDrawPoker_MiST/rtl/mc_sound_a.vhd   |  117 -
 .../TripleDrawPoker_MiST/rtl/mc_sound_b.vhd   |  253 --
 .../TripleDrawPoker_MiST/rtl/mc_sound_vco.vhd |   49 -
 .../TripleDrawPoker_MiST/rtl/mc_stars.vhd     |   90 -
 .../TripleDrawPoker_MiST/rtl/mc_video.vhd     |  440 ----
 .../TripleDrawPoker_MiST/rtl/mist_io.v        |  530 -----
 .../Z80 Based/TripleDrawPoker_MiST/rtl/osd.v  |  194 --
 .../TripleDrawPoker_MiST/rtl/pll.vhd          |  451 ----
 .../TripleDrawPoker_MiST/rtl/scandoubler.v    |  194 --
 .../TripleDrawPoker_MiST/rtl/sine_package.vhd |  152 --
 .../TripleDrawPoker_MiST/rtl/spram.vhd        |   55 -
 .../TripleDrawPoker_MiST/rtl/sprom.vhd        |   82 -
 .../rtl/tripledrawpoker.vhd                   |  447 ----
 .../TripleDrawPoker_MiST/rtl/video_mixer.sv   |  243 --
 .../Z80 Based/Uniwars_MiST/README.txt         |   24 -
 .../Uniwars_MiST/Release/Uniwars.rbf          |  Bin 310852 -> 0 bytes
 .../Z80 Based/Uniwars_MiST/Uniwars.qpf        |   30 -
 .../Z80 Based/Uniwars_MiST/Uniwars.qsf        |  190 --
 .../Z80 Based/Uniwars_MiST/Uniwars.srf        |   54 -
 .../Z80 Based/Uniwars_MiST/clean.bat          |   37 -
 .../Uniwars_MiST/rtl/ROM/GAL_FIR.vhd          |  534 -----
 .../Uniwars_MiST/rtl/ROM/GAL_HIT.vhd          |  534 -----
 .../Z80 Based/Uniwars_MiST/rtl/Uniwars.sv     |  193 --
 .../Z80 Based/Uniwars_MiST/rtl/build_id.tcl   |   35 -
 .../Z80 Based/Uniwars_MiST/rtl/cpu/T80.vhd    | 1093 ---------
 .../Uniwars_MiST/rtl/cpu/T80_ALU.vhd          |  371 ---
 .../Uniwars_MiST/rtl/cpu/T80_MCode.vhd        | 2026 -----------------
 .../Uniwars_MiST/rtl/cpu/T80_Pack.vhd         |  220 --
 .../Uniwars_MiST/rtl/cpu/T80_Reg.vhd          |  105 -
 .../Z80 Based/Uniwars_MiST/rtl/cpu/T80as.vhd  |  283 ---
 .../Z80 Based/Uniwars_MiST/rtl/cpu/T80sed.vhd |  179 --
 .../Z80 Based/Uniwars_MiST/rtl/dac.vhd        |   71 -
 .../Z80 Based/Uniwars_MiST/rtl/dpram.vhd      |   75 -
 .../Z80 Based/Uniwars_MiST/rtl/galaxian.vhd   |  448 ----
 .../Z80 Based/Uniwars_MiST/rtl/hq2x.sv        |  454 ----
 .../Z80 Based/Uniwars_MiST/rtl/mc_adec.vhd    |  251 --
 .../Z80 Based/Uniwars_MiST/rtl/mc_bram.vhd    |  182 --
 .../Z80 Based/Uniwars_MiST/rtl/mc_clocks.vhd  |   85 -
 .../Z80 Based/Uniwars_MiST/rtl/mc_col_pal.vhd |   78 -
 .../Uniwars_MiST/rtl/mc_hv_count.vhd          |  145 --
 .../Z80 Based/Uniwars_MiST/rtl/mc_inport.vhd  |   74 -
 .../Z80 Based/Uniwars_MiST/rtl/mc_ld_pls.vhd  |  115 -
 .../Z80 Based/Uniwars_MiST/rtl/mc_logic.vhd   |   92 -
 .../Z80 Based/Uniwars_MiST/rtl/mc_missile.vhd |  107 -
 .../Z80 Based/Uniwars_MiST/rtl/mc_sound_a.vhd |  117 -
 .../Z80 Based/Uniwars_MiST/rtl/mc_sound_b.vhd |  253 --
 .../Uniwars_MiST/rtl/mc_sound_vco.vhd         |   49 -
 .../Z80 Based/Uniwars_MiST/rtl/mc_stars.vhd   |   90 -
 .../Z80 Based/Uniwars_MiST/rtl/mc_video.vhd   |  433 ----
 .../Z80 Based/Uniwars_MiST/rtl/mist_io.v      |  530 -----
 .../Z80 Based/Uniwars_MiST/rtl/osd.v          |  194 --
 .../Z80 Based/Uniwars_MiST/rtl/pll.vhd        |  451 ----
 .../Z80 Based/Uniwars_MiST/rtl/scandoubler.v  |  194 --
 .../Uniwars_MiST/rtl/sine_package.vhd         |  152 --
 .../Z80 Based/Uniwars_MiST/rtl/spram.vhd      |   55 -
 .../Z80 Based/Uniwars_MiST/rtl/video_mixer.sv |  243 --
 .../Z80 Based/Victory_MiST/README.txt         |   23 -
 .../Victory_MiST/Release/Victory.rbf          |  Bin 305269 -> 0 bytes
 .../Z80 Based/Victory_MiST/Victory.qpf        |   30 -
 .../Z80 Based/Victory_MiST/Victory.qsf        |  188 --
 .../Z80 Based/Victory_MiST/Victory.srf        |   54 -
 .../Z80 Based/Victory_MiST/clean.bat          |   37 -
 .../Victory_MiST/rtl/ROM/GAL_FIR.vhd          |  534 -----
 .../Victory_MiST/rtl/ROM/GAL_HIT.vhd          |  534 -----
 .../Victory_MiST/rtl/Victory_MiST.sv          |  189 --
 .../Z80 Based/Victory_MiST/rtl/build_id.tcl   |   35 -
 .../Z80 Based/Victory_MiST/rtl/cpu/T80.vhd    | 1093 ---------
 .../Victory_MiST/rtl/cpu/T80_ALU.vhd          |  371 ---
 .../Victory_MiST/rtl/cpu/T80_MCode.vhd        | 2026 -----------------
 .../Victory_MiST/rtl/cpu/T80_Pack.vhd         |  220 --
 .../Victory_MiST/rtl/cpu/T80_Reg.vhd          |  105 -
 .../Z80 Based/Victory_MiST/rtl/cpu/T80as.vhd  |  283 ---
 .../Z80 Based/Victory_MiST/rtl/cpu/T80sed.vhd |  179 --
 .../Z80 Based/Victory_MiST/rtl/dac.vhd        |   71 -
 .../Z80 Based/Victory_MiST/rtl/dpram.vhd      |   75 -
 .../Z80 Based/Victory_MiST/rtl/galaxian.vhd   |  411 ----
 .../Z80 Based/Victory_MiST/rtl/hq2x.sv        |  454 ----
 .../Z80 Based/Victory_MiST/rtl/mc_adec.vhd    |  215 --
 .../Z80 Based/Victory_MiST/rtl/mc_bram.vhd    |  182 --
 .../Z80 Based/Victory_MiST/rtl/mc_clocks.vhd  |   85 -
 .../Z80 Based/Victory_MiST/rtl/mc_col_pal.vhd |   71 -
 .../Victory_MiST/rtl/mc_hv_count.vhd          |  145 --
 .../Z80 Based/Victory_MiST/rtl/mc_inport.vhd  |   78 -
 .../Z80 Based/Victory_MiST/rtl/mc_ld_pls.vhd  |  115 -
 .../Z80 Based/Victory_MiST/rtl/mc_logic.vhd   |   92 -
 .../Z80 Based/Victory_MiST/rtl/mc_missile.vhd |  107 -
 .../Z80 Based/Victory_MiST/rtl/mc_sound_a.vhd |  117 -
 .../Z80 Based/Victory_MiST/rtl/mc_sound_b.vhd |  253 --
 .../Victory_MiST/rtl/mc_sound_vco.vhd         |   49 -
 .../Z80 Based/Victory_MiST/rtl/mc_video.vhd   |  431 ----
 .../Z80 Based/Victory_MiST/rtl/mist_io.v      |  530 -----
 .../Z80 Based/Victory_MiST/rtl/osd.v          |  194 --
 .../Z80 Based/Victory_MiST/rtl/pll.qip        |    4 -
 .../Z80 Based/Victory_MiST/rtl/pll.vhd        |  451 ----
 .../Z80 Based/Victory_MiST/rtl/scandoubler.v  |  194 --
 .../Victory_MiST/rtl/sine_package.vhd         |  152 --
 .../Z80 Based/Victory_MiST/rtl/spram.vhd      |   55 -
 .../Z80 Based/Victory_MiST/rtl/sprom.vhd      |   82 -
 .../Z80 Based/Victory_MiST/rtl/video_mixer.sv |  243 --
 .../Z80 Based/WarOfBugs_MiST/README.txt       |   26 -
 .../WarOfBugs_MiST/Release/WarOfTheBugs.rbf   |  Bin 346666 -> 0 bytes
 .../Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qpf |   30 -
 .../Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qsf |  190 --
 .../Z80 Based/WarOfBugs_MiST/WarOfTheBugs.srf |   54 -
 .../Z80 Based/WarOfBugs_MiST/clean.bat        |   37 -
 .../WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd        |  534 -----
 .../WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd        |  534 -----
 .../rtl/ROM/Neuer/build_roms_galaxian.bat     |   20 -
 .../WarOfBugs_MiST/rtl/ROM/Neuer/gfx1.bin     |  Bin 4096 -> 0 bytes
 .../WarOfBugs_MiST/rtl/ROM/Neuer/main.bin     |  Bin 10240 -> 0 bytes
 .../WarOfBugs_MiST/rtl/ROM/Neuer/romgen.exe   |  Bin 578560 -> 0 bytes
 .../WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1j  |  Bin 2048 -> 0 bytes
 .../WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1k  |  Bin 2048 -> 0 bytes
 .../WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.cla |  Bin 32 -> 0 bytes
 .../WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.u   |  Bin 2048 -> 0 bytes
 .../WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.v   |  Bin 2048 -> 0 bytes
 .../WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.w   |  Bin 2048 -> 0 bytes
 .../WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.y   |  Bin 2048 -> 0 bytes
 .../WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.z   |  Bin 2048 -> 0 bytes
 .../Z80 Based/WarOfBugs_MiST/rtl/ROM/gfx1.vhd |  547 -----
 .../WarOfBugs_MiST/rtl/WarOfTheBugs.sv        |  192 --
 .../Z80 Based/WarOfBugs_MiST/rtl/build_id.tcl |   35 -
 .../Z80 Based/WarOfBugs_MiST/rtl/cpu/T80.vhd  | 1093 ---------
 .../WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd        |  371 ---
 .../WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd      | 2026 -----------------
 .../WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd       |  220 --
 .../WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd        |  105 -
 .../WarOfBugs_MiST/rtl/cpu/T80as.vhd          |  283 ---
 .../WarOfBugs_MiST/rtl/cpu/T80sed.vhd         |  179 --
 .../Z80 Based/WarOfBugs_MiST/rtl/dac.vhd      |   71 -
 .../Z80 Based/WarOfBugs_MiST/rtl/dpram.vhd    |   75 -
 .../Z80 Based/WarOfBugs_MiST/rtl/galaxian.vhd |  450 ----
 .../Z80 Based/WarOfBugs_MiST/rtl/hq2x.sv      |  454 ----
 .../Z80 Based/WarOfBugs_MiST/rtl/mc_adec.vhd  |  251 --
 .../Z80 Based/WarOfBugs_MiST/rtl/mc_bram.vhd  |  182 --
 .../WarOfBugs_MiST/rtl/mc_clocks.vhd          |   85 -
 .../WarOfBugs_MiST/rtl/mc_col_pal.vhd         |   78 -
 .../WarOfBugs_MiST/rtl/mc_hv_count.vhd        |  145 --
 .../WarOfBugs_MiST/rtl/mc_inport.vhd          |   85 -
 .../WarOfBugs_MiST/rtl/mc_ld_pls.vhd          |  115 -
 .../Z80 Based/WarOfBugs_MiST/rtl/mc_logic.vhd |   92 -
 .../WarOfBugs_MiST/rtl/mc_missile.vhd         |  107 -
 .../WarOfBugs_MiST/rtl/mc_sound_a.vhd         |  117 -
 .../WarOfBugs_MiST/rtl/mc_sound_b.vhd         |  253 --
 .../WarOfBugs_MiST/rtl/mc_sound_vco.vhd       |   49 -
 .../Z80 Based/WarOfBugs_MiST/rtl/mc_stars.vhd |   90 -
 .../Z80 Based/WarOfBugs_MiST/rtl/mc_video.vhd |  436 ----
 .../Z80 Based/WarOfBugs_MiST/rtl/mist_io.v    |  530 -----
 .../Z80 Based/WarOfBugs_MiST/rtl/osd.v        |  194 --
 .../Z80 Based/WarOfBugs_MiST/rtl/pll.vhd      |  451 ----
 .../WarOfBugs_MiST/rtl/scandoubler.v          |  194 --
 .../WarOfBugs_MiST/rtl/sine_package.vhd       |  152 --
 .../Z80 Based/WarOfBugs_MiST/rtl/spram.vhd    |   55 -
 .../WarOfBugs_MiST/rtl/video_mixer.sv         |  243 --
 758 files changed, 4303 insertions(+), 168667 deletions(-)
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Release/Azurian.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/Azurian.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.qip
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/Release/BlackHole.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/BlackHole.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.qip
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Release/Catacomb.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/Catacomb.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/Release/ChewingGum.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ChewingGum_MiST.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/Pisces.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/TripleDrawPoker_MiST.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/tripledrawpoker.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/Release/DevilFish.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/DevilFish.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.qip
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/spram.vhd
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.sdc
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Release/Galaxian.rbf
 create mode 100755 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/buildall.sh
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROMS.vhd
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{AzurianAttack_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{AzurianAttack_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{AzurianAttack_MiST/rtl/ROM/GALAXIAN_6L.vhd => Galaxian_MiST/rtl/ROM/azurian/AZURIAN_6L.vhd} (92%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{AzurianAttack_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/azurian}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{BlackHole_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{BlackHole_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/{GALAXIAN_6L.vhd => blackhole/BLACKHOLE_6L.vhd} (91%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{BlackHole_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/blackhole}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Catacomb_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Catacomb_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Omega_MiST/rtl/ROM/GALAXIAN_6L.vhd => Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_6L.vhd} (93%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Catacomb_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/catacomb}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{ChewingGum_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/chewinggum}/col.vhd (90%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{ChewingGum_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/chewinggum}/h.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{ChewingGum_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/chewinggum}/k.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{ChewingGum_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/chewinggum}/prog.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{DevilFish_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{DevilFish_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{DevilFish_MiST/rtl/ROM/GALAXIAN_6L.vhd => Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_6L.vhd} (91%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{DevilFish_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/devilfish}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/{ => galaxian}/GALAXIAN_1H.vhd (100%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/{ => galaxian}/GALAXIAN_1K.vhd (100%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{BlackHole_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/galaxian}/GALAXIAN_6L.vhd (100%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/{ => galaxian}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{KingBaloon_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/kingbaloon}/col.vhd (93%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{KingBaloon_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/kingbaloon}/kbe1-4.vhd (100%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{KingBaloon_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/kingbaloon}/kbe2-5.vhd (100%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{KingBaloon_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/kingbaloon}/kbe3-6.vhd (100%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{KingBaloon_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/kingbaloon}/prog.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{KingBaloon_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/kingbaloon}/rom_h.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{KingBaloon_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/kingbaloon}/rom_k.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{MoonCresta_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{MoonCresta_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{MoonCresta_MiST/rtl/ROM/GALAXIAN_6L.vhd => Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_6L.vhd} (91%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{MoonCresta_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/mooncresta}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{MrDoNightmare_MiST/rtl/ROM/GALAXIAN_6L.vhd => Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_6L.vhd} (90%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{MrDoNightmare_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/mrdonightmare}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Omega_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/omega/OMEGA_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Omega_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/omega/OMEGA_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Catacomb_MiST/rtl/ROM/GALAXIAN_6L.vhd => Galaxian_MiST/rtl/ROM/omega/OMEGA_6L.vhd} (93%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Omega_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/omega}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Orbitron_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Orbitron_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Orbitron_MiST/rtl/ROM/GALAXIAN_6L.vhd => Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_6L.vhd} (91%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Orbitron_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/orbitron}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Pisces_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/pisces/PISCES_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Pisces_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/pisces/PISCES_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Pisces_MiST/rtl/ROM/GALAXIAN_6L.vhd => Galaxian_MiST/rtl/ROM/pisces/PISCES_6L.vhd} (93%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Pisces_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/pisces}/ROM_PGM_0.vhd (99%)
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1H.vhd
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1K.vhd
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_6L.vhd
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_ROM_PGM_0.vhd
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Uniwars_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/uniwars}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Uniwars_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Uniwars_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Uniwars_MiST/rtl/ROM/GALAXIAN_6L.vhd => Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_6L.vhd} (91%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Victory_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/victory}/col.vhd (91%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Victory_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/victory}/h_rom.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Victory_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/victory}/k_rom.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{Victory_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/victory}/prog.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{WarOfBugs_MiST/rtl/ROM => Galaxian_MiST/rtl/ROM/warofbugs}/ROM_PGM_0.vhd (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{WarOfBugs_MiST/rtl/ROM/GALAXIAN_1H.vhd => Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1H.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{WarOfBugs_MiST/rtl/ROM/GALAXIAN_1K.vhd => Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1K.vhd} (99%)
 rename Arcade_MiST/Galaxian Hardware/Z80 Based/{WarOfBugs_MiST/rtl/ROM/galaxian_6l.vhd => Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_6L.vhd} (93%)
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/col.vhd
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/prog.vhd
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_h.vhd
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_k.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/hq2x.sv
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/kb_synth.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/video_mixer.sv
 create mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ym2149.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/Release/KingBaloon.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/KingBalloon_MiST.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/sound.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kb_synth.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/Release/MoonCresta.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/MoonCresta.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/Release/MrDoNightmare.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/MrDoNightmare.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Release/Omega.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/Omega.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Release/Orbitron.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/Orbitron.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Release/Pisces.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/Pisces.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/Release/TripleDrawPoker.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.bin
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.hex
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.bin
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.hex
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/k.bin
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/k.hex
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/prog.bin
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/prog.hex
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/swap.exe
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/TripleDrawPoker_MiST.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sprom.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/tripledrawpoker.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Release/Uniwars.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/Uniwars.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Release/Victory.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/Victory_MiST.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.qip
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sprom.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/video_mixer.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/README.txt
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/Release/WarOfTheBugs.rbf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qpf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qsf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.srf
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/clean.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/build_roms_galaxian.bat
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/gfx1.bin
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/main.bin
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/romgen.exe
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1j
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1k
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.cla
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.u
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.w
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.y
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.z
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/gfx1.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/WarOfTheBugs.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/build_id.tcl
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80as.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80sed.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dac.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dpram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/galaxian.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/hq2x.sv
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_adec.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_bram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_clocks.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_col_pal.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_hv_count.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_inport.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_ld_pls.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_logic.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_missile.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_a.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_b.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_vco.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_stars.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_video.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mist_io.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/osd.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/pll.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/scandoubler.v
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/sine_package.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/spram.vhd
 delete mode 100644 Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/video_mixer.sv

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qpf
deleted file mode 100644
index 43a9e280..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 14:59:16  November 16, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "14:59:16  November 16, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "Azurian"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qsf
deleted file mode 100644
index 3fc9a82a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.qsf	
+++ /dev/null
@@ -1,186 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 16:34:10  March 10, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Azurian_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Azurian.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY Azurian
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ---------------------
-# start ENTITY(Azurian)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(Azurian)
-# -------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.srf
deleted file mode 100644
index 14cddd5e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Azurian.srf	
+++ /dev/null
@@ -1,54 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/README.txt
deleted file mode 100644
index 49293e17..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Azurian Attack port to MiST by Gehstock
--- 18 December 2017
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Release/Azurian.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/Release/Azurian.rbf
deleted file mode 100644
index f46206f204722760454c12379a850d354224064b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 306194
zcmeFa4}2ZRb>F+YxK<#?iSO=RK#NP5+!<Uz3-FJKOICr{INn{t>@}=NB<$F1>Q@7>
zo*tvN)}OX{PWtKd?!|=+MwCTRR3g77F#sWolGv6+)BU7v8UwVFC`l7jj$fYJm&PRR
zrs=0m46;fiyGi}NXD?QQD1anLD4`=9l6QA!XJ^iwIWu$4Z_X~i{q0NBJ%66jfB&Bs
zzV)qdo&V-H|MD-s`OR;A>!rW^pIpB57k}~6U%vDgFTM1?xM=*_OBeJv{;mNf(DI|4
zZ_w3Aps+;CpU%^+<tXK~Ld%cK>$vzluPaXvp+P85m!n*-m86{Il$XESF|RMbFV9My
zdAc0e%7f%z&V!ui<*#<k>&x%UGg3~TeznKEyemEC_2l`5521Vv=INI^u9jcYbGo<;
zNtd*Xk9Ft<NRAdHd4wl93Q5|<)V%Y`uiVe`=BasFew`ner%Syell-0><-SmU{uCtV
zF_fpvbxx8dB-hQe=6QZUKQ6zw{5-!eM@i3l%JYOvl;4-5@G=DD_wu8p%efqL%J0>n
z{9KMwj@0pHNXE91q~#=Xc?%?YegcwbZigC>q|1G|7CpWc?Sth0JC{hx$ti+bmdLz_
zY)FzOmMFh1&-@1TF-UF+KhG`EuS3hvmtW`U`7!5VFC=9y*FTYg+?Qh!av*81kfi0*
zOlkfKA99u-rOk3KM@biwb4kld(sDlX`ttFSw>PgVKgu(rBf^&p<<HA~=|g#5(tZod
zbzmNnwB;meIpyh+KR?gwlcVTBPB~wB8{~f84k=ISpN1x(=b<k_c|EHg&p`RTynZ>3
zK>iX*Jwn2V93@$fpMs7+3KHJrnSTdK`o|%;C)a<lL~@=}o+igXgqC0Lzle@PB6A_p
zhvr$aC_D(sm=KcmTplv!^6@3|kZX~N9EIfk;1V@cnrZ(5`U)hsE@ET9l)t=wxfa=d
zKO}s}bxuFMM3OGLAu<*H&-?B{C?5}(8Y^F3qCBsZlk+tUNqsp_`7!4~jyWH4?m_oK
zQl#)P2gy;&mbAQ%D>+Kt4?x0?^t<Su)Ug_ME>V78+VBBrGbFc!Pq`NTkhx80`FS(t
z_S^q-iSm0=|JX9BE|G@hRBp+6PM=vKx$cAH_#`B9SWe4jBk5m<^7|s6<4}GrM;X6D
z!jJU1P(E(uD7;AjNPTjY@gc0pJ<(HnR`fu4$>~yhv05KV{mV(}6KZnQ{B5Q*e}8p}
z<SLh!h*)^bDVO>3qsV_b$-U**%XyG<>Gzd*$kQH%q`sUt(XIal<vhqyt}jQ+=Mg#2
z$4Y+8>s#%Z*O%WH-lc7Mx`<17khGjG$CKR8>(7s}#^z(;V%bRDGIt8exy&CQg8nlk
zx+d$d97QK{dU1*5T2Axy{3v5=9Fp?#G#R(cN$xEtY5Vf)CP%OEBzy}WIsN<+$+hq(
zIx6Ex>XYM1NO+U;oFq-=q?~rHKq51#E2mFFGGFA^vL5BUt#te%^av#SDfeZ4%F`tM
z^N^G&G8UUeXcttvh$Jm1xg|UZ2_Iq)2%oZcJibKvIxK6AklbsYHGlu>5?!1od<gyH
zCF)v6dHu_e!oN_SCVYtQXUy><IxE*XEgz>VoeTK!4M_SwC*fxq8!MhZy+p!?WDxeH
z97z`bME1+;%lVPx^7M<(a~|?(UgVnFATodEB=f3}*l0qMF4wYFy$@<%qMwE2TI>!v
zz84Z6<S6t*kQ^mVNca)^G3P_%E9d#x$b})-GJnZY>>-)cgk-FDKw|6uKTvL0%kkGP
zK^M>Qe*{Td&PRTf`j%79Th5or{nL=-$z>($kH|qt&U2D$k<0Sq#pk(Ri5zm0F_7D7
z(srpU=R@wvb<;|F%UeW7J&>fy8Z7ghko2oeA=@CiCuyI6#BO;PB=^Nu6In`{*l77!
zlYEkX09wwI)GZ|ARgQ8`j#9pm$VN!c#degV)bmSAB<H^X$x(bUvF+t3cH;jH$$6e8
z*ExyK<s>?olhiGg^C8onT<0>qm=9^6)SXk#m&_UBAItHfCHigXUo26cCUe<)mPlmq
zC?v<6<d&QZ4??m|2noN<lxAAqcOok}&yQl4$@#s|Es)&%K}gc_HFF0f>$#AOVX-qr
z2QEeVvmy`C1JNbXeOWhTeG!uD%aN>^LU}$ZN9MAeJ`3gZl^i8KA2)K8HVMi3R!ELF
zL!v7}!iOAXEXz^m2}zTqTnov$q~#=O(l0{7kF-(j=iDEcW8Ob`+FPM5P@XRR_CZL}
zgk=4aYniXajuw*hzYjI9n!n5ER_Qybe>vs#2~RoYX>yc$gydX!k~aJvBzl#TTwhG5
zFQONq<w?tVkaN+!ynZ=KeL`|BbC~Ft%&jul2+6qrkC3G0B-fWCk<oIJF)L#;C#i2G
z`U^<L-tv25O9-u$Ch1>YA~|0REiZ55d_w{o64;Qyl}bS7KbcQol|OkE-2AFrD_po2
zrG5UVGwW_y>fo~THJ*O)k+-bziPf_&zW=~QH^Wz9#uweZ^yT7TylQU0bmq(5{b<{p
zE|=ws@4vQ{SN!N}Gp;{l9{8|Gz2*k|7Bf{z_>B$j<P=(*MFvU5LSi{ara+;V=j363
zvcSWWMGIGIuwrQA>5p33Bl+{$anSHBp69&SC>Rt{lu}<sM~BIhldsHWEEr#WujM(0
zF(d_SkM~U}Dl^*PbTBgd>dM?dI6Y{P<DHF4VcI6OTZ*bEe%@Iy63Ji$x@?B-mvv=M
z8;&!gwhkI)Wg62zM8VEaOm;WAwCPONyRAOU2;W;#)70_K!ZRPbkwVB)<6y+LRNNe7
zzG)=Vl$S}GBuXqI^6RF^%rK6|@+%Kd`UM`YR}!*CDzVP|?sv<rb)jq1vt?}%ZWiN<
zhvqf#xc*9e4a_Wm^!j1!jU#@BOiqgr{%U@D?Z<2H%Vm9V?;pQD<1(8LuBEMuPtIP;
z<F9`9+C}zCdDk}kyi!hf_BVyG<;&MaP2}>C-)9xLa$2UID?If1c3Br+p-Wf&O1>4(
zo}Q2eZ++->RgCMZmG$)zm=T({{Os##WM2cDe^UnLB}IV7`mLADv4)%O7ys=IYsh}-
ztk*SXYjaXB)lmCSeuCRR)_+mOsby4Rv7q<1-rnpLCov6M<F4R<^cIYrjrm4a+L|9Q
zKL4NBt)Gqcp6Aw21;6iKTuRt$yLX*W0BDAh`LXDQv7{EpH6||pn{SDXSZYFavFXe$
zY2vjee*Tx<DvQSJQFQ68&i1{VDt+pO>d8oJ`R)2b<KEz8q`olm(csB;=L0WI=zG))
z5B$on%{t`$d)xZXMlU@m&s=oWn;Z8IT(^&FOL*6}zw}@{q)*Ypxk~fm#Qm9Y*QVdA
z<^JlkZ(i-zTGM^&i)}YfuJx%^^Z#Xe)mv-6u{64`$*Ov}((jvk`ShAkuJdW<3fm_W
z(WU6^$1invZTJ5ABz9>(#aMjwGiz(frE=5Cbz3Lh#dE)Tsk+v7@2^k(m*I1RvC9Z(
z`Rxo2KmGgbHusB_xIPM-;m=<@*|Kg6N%4ixh%vlw#`S8}xNSWB=hyG%%KCH;a(qM0
zCf8_TulV?e*}Y+Q8|!Fx%ha2!hr4exx<k``$A{OWFhfc+jE{b0-2hkDc)ESv3R`zn
zBWvw?{Hzsj2`^=PFP{HDuY{-O=J@4u-uLV4q8M2<e;uv7T>F~$*VFPg-arV|l}Yz<
zxz?%|mn@I2T(7MQW4&kWb+gBe#kc*^C8e;Yn}}?3O%GfubB5roW-hOvLH@=-yEp9a
z6|LzjPyCLwyTh3;_yTcfNcN_R7VLX>RWRXAZuJ8%eQfL=wJ`C)V7A@a{u=<@0*Zrr
zHx2BIkNR8&gI}+Y>(lW5DxiDmV$+|m-(<PoyO!%>cxQ8Hb8qlc)9D)SZD3(*5LT9T
zLt=m35?e1*Z6nHLtv!jGzP@4M*YA9N{c^V6E6I13-EABHU}EiRyV?_|^SX8PhTVPT
zCiaRsUthZ$6<D#>YfOac4ZHi#R~uhzPiI7~*ZQ78G3x?SWU#0G?f?C|*4~~~o>(vV
zDil!nbo(1RShl%=u!^8pPF{Te&sM&1HL0uGL|2BEzq-mtKJeC8CtSnTdMR1P!g?;1
z8*ukpdv(3La;^2Rn*VxcY~4&dfzH>@>^}XpOxmw|n2E9Y&py6tx2^fcs*~KBOXAf^
z-g;iIMgEQD#J?VK(u82shu3HZulV@uXV8b|e|*n|*}Z;dcX<9Mr><_cjAZ;@94@{1
z=?|?qU0#hrWE9WO{=*d~nM>Jy*-Q2-v1Xk9SL+(fxFTm)mAKwB>{T(b(nD9nSY@Sx
zB<;h$z1p3%r(X?YtJQKfc1&okQrek+xxNnB#$vgOpjS@5n!a4QBvRK|$*yjeU5UH(
z-l4pHIa_fpSxF?9P1|^{5_Mj`j(!70t*vO_USs0xXCE6I?^Ry=Tb<u=?^Rx5fcK^B
z=H)Z!pL~A#)wP{p(JFfJXWLe*^7C)IeqWzijpsF|U%e5tg6+Nd>0r$atopze_2sHh
zzxu}2xAL{0PBRu?{I9Pr{aUWBk5;bGf(^!25XvQ!HY9dQ@vLxj{U!D~N14ddvG}jA
zW4wC>AzxLJd-@IZZqo+bz4Rg#=KRLTOs?OJ@v9oiD?DTupMC$O-qKs)kxL|9y>0cH
zLPK-$o~hTQUUkCyFE3Zk%Bvr|0>-X<598^n@7%Xg!z)(9N4~ti&e#Ul{c4rG%+)#$
z@(rx}GO}Lj_Iji68(8;BQog!0X7hE!x;LV`--uxM##@zhmDlO5%9kTFu5N70Qy=^<
z>-QDGrH?;dJu}OneC?t<xcv6o&hLAjzQn#ZE>_5W1;+9UPpzEvT8XWk?}}147`q}d
zEz7iy5(~|LwBac(6YUk8Ubo8c-rI3~y08+jcm;yJ!Yu2k{f2#So5X&-!K1scQ1F+{
zwt;qEBLuz?-2EN<EtAU*jw{WuG+E03xV19Lf7f*d<To+F#cy_ALFOyVQat~@g)7T>
zCApZ#!{&yGUY>n9V!H;f<Mcnt{_ED|C0+ITb-TiEFt*k{y<R1@VRx^!C$Ha6dv4g>
zYwk<2yP5n~3^OUVHde97)2n>s{QvmlHFLP?1MBI2$n3OUJ7~szpS?c4zx946LyU&k
zqTA@qYyV%GHD+CGbJqC88u*~_k;!#na^)(&J@LKmU;crU(YgBl-j{DZ8I9FH7X2f>
zDR}EwYS~8xZ~e+a`KsV(`f&DH!S=8GxcoOd?O)lGeOK_vH~9Z@<hz1$JXb&OW&eTB
zSpAXamj%D`3gJK1k^dFw<MB|lHC*5M)c360P+RY>#wJZWc-1-Q%5OB^R=@K6m&$p)
z+D_N6C9ol}OX<@}_tslt{<@8%H_+QsD|O7;)7HBy*UrHzPh8K8t)ITG_eW2#gf`6c
z4fA}JF||rELk+#zFwYUs%m1UNcqSX>`K!E*4fA}J@w1lX>v>sQOFLG|yR>=1t^3}0
z%@*A&|H0$`vA!RpU5WFnO8cAKm9Gc{<ZS)SoelH+6~SK7*?Q~Pbql7fpN?JE{{_!_
zgXAmy@AXY6{@zEv_lh*^N;0jt7Oq=ozi}eQ*8?eE8HE0zGGEuiAAH?h3-=p`tquJA
zmF<An*+37^|G_`FlG)<Q@?cj?URln|=X#w3%P-HssyWts-*MH7)_P-uu?>l>Ac6H>
z=~t-Y>XJ4XTdUk&2Z_BVP<DM_!!7^x`uk5GGHL$}o+QN<T%vDxULPSS7k}Z{c&2oH
zFqRAI<>TLAy?D8e8~gRIh~f&*WX4@DfaQ(#&HXDB@MW^C^RQeul)_l=4;Wm(oF&(c
z`{#WupAp_b%OnhQ-FkZiExYzT?hUkTBib~dqAq#dK+7&Eo)vGd^8&tN9eHAqpIpgt
z@jw39m1MiJJb#s~yfTiKa=l>~+c47Cq!+IPlC-A!SIrD#>t-Bn80o8udG#9`MtUZj
z4I_PZ6<OsDB70qTonP0&H@39nP3~XG%W2o$miDE-<FGjK-`5xaSY_<2J^3muyVbwq
zu;q7K4ebZ@R%6o8*&oBVE@e(jQBhbZ@`n@oGcstzMjX`)!yhCyj{Jfh8+POt3xiw!
z@P;t3N8{}^qeI1GjoWW@x9P&2-a=sX?ryk;j}05Qd#$(F&&?SP$KKKStIfAHy8X>z
zU`n-%e-_W%hpWBLmfG36drXynq-)!u#$>p#dpNptAgTsO<GmjV(qr-d+Tq*0)A84%
z;FO(yLVYQEzUFPxyZWmmbB~8F#QMFJkK55NSU<9RZel9vt(doa!Bo7t(JcIJ$MsS5
z_Jem1jWr%GzA&oY7aR7@my32Lj!*jMop(OmXawVRd*MjK>pM}ptGg%u<H7Ilyi1Rr
z@un)qKdS9L=%u~7`&1(>ea?9<)jhT6?C9Ses(T;(nb+%+--(hfru;v`NzA3_V2SHp
zQWn|p@pxb5l@xvP9?<C@f3wky1YX*(dUb}ZboqY?eCw5}3`4#~BKajXqr{|2{)Qwj
zRu5-4mu`8^QU%#{Ui`8$ec`Y9L?GuBn)Cm1`Nl2pzhSAoJTGs<FE7||4cC+EIeCR#
zJD}ugWh6R<S1DeegLGEOJMLZ<#Fu1uUsWhAZGL$rl*eBtO(F2cVToQ2ruNVM1Y_`G
z%3FPL`peh8nN?1KdDf+}7w?*TInyd9o^Y5ymgRAml)^!dOO2BBAY=I3$Cfp@`Jm+S
zN3(}Ky0EBJWV%Jum99XV2|<t|R!yT#!%Hl#vLD0f<5t-Uf@YewjNiF)X@{mMkz6jY
z7*fg0T_Y#*klp0e&Dc-06)@5HR#La9)Yn>D+z2vJgyz#<et9J2J%7};i?(grMbmZ-
zJ4wxui=(#N5!tlBHrh=)>{mvICDquWX$Lf`gG6(wmzSjM_^>XGLST!(v4ztn(cFw+
z-!>fEXbRR&vSg}6jh0k3YlnyjCXA}#>!m025)9*!f8W|HOsbZgkk{-s9`-~w*;U9u
zX3$y&-O#LOIj_F5s9hU=-O|Fm2!8P|e@6<Fj>-<rLbKESM^wacUDpVsDB_&6>@P`>
z&*1Pfmiw|2n!QHLG<~#q{DHib{OE?Jk?9A==4o?EaGT<!IYoNU@|)}=S$|3+NC=u`
zOGzI*&{}VnC=G5>#%J?1E5(+n#`Vgvsi{c>P7_E8%}%+ZG|fPy`>0BbEJVwN+z<Z#
z@=v<IEa+k?1Ddj>WGN4+_n5*|(wsm;5xy|)WX0u-89`PqVqg3pA7Ao`oh+kIhZ{wt
zidK~vI3e<tOV?;0C5cPhc6Zo4QKYoR@2Kr|(gN2F7nJLEF4*l0w%bl}qU*Dc4uXJx
zz8<eL)O<Cov>vGX^}1$E1W8?6;rX`@z@AWZU^>FR6k-=627_x;woOMf7$SHp3P1hI
zaqLb8s^QFwU?VfIU6hdKQK+I=DmD7l6Ant)r?jcd^)5}a&qx$ad*lz^I+@ie)he^O
z_Bhnz+J0oqxHCL{LOWH>%g~;2xUU&};gk)FlDESm$&-IZ(5K8mJB<0Hi*Hmh=x3em
zijml3l3YB0`)8Lns1jS9vImS%7kYorHg-1V8%Em!I}H!ozTIyp2W+=UhQKx|H@R(7
zanan_IDMdXzip@G15<9FHQkli=b0*0oH~(7rcJtcj>~5o=Iwzwtsm+yN0YO<Z0?!W
z-t?}rt>PJF>^bGcdTVS<>%FZz=K3rn4JYfCfBpdkDC9MVuTvIn+0SgyX8H%1&}e8P
zlh6L_ul!7F&$VGg8}=rVzHRQecPPVlJqLZ9)_Z2`M5?EbJu_M~F%{YPv)bt6AJ6q6
zm2do1^FQP*E7Mn|QEo07=qeR?)Qd<^$Tr~y^=>nZ2kf969iZYfj<w(3jL>Di<xUx0
zoUz;JGu=09Qw>#9PnDL?`(0)qy4FXBXoDxGHEezK>6T3Cr|C)bZJOCItHz+wQa3F4
z3@kK&vPI`Z3b7*^Lp$9~S^pcx+tf5;!7JNvn#}HE<Tfj&`$eOuR+=o62(yPfa`RFZ
zG_gEGjoDa4eo|#N4LDTG6%wUD*B)plhtJxmy>y7Z#j(n8VZ)+h1mzZnuQZ4LkS2JB
zF1OH7bexrpHh=rSH6@&g93(^5wIPKg+XPV>F11msXaHwz3@r{al@wvnkO9DD+l=kl
zNL%lbS&-h7>8Wh`bu$PYsXwu#Pqj7{yH93q6tU8+R7qQ<Y^l;VDJ45i5N$Rya_zRM
zl<u=wrm0;7@4{?CUotR7eW`Aoi|JjCu}73ks^Txx*VCuu8$#qpnqm3`3?Ge=DWl0?
zp!udKNSHDh-P<ZNtf}+77dCA-WS;d5+rb2)ho{D1(fL3tSz9sJxZ|5{VE9kiM`O)&
zyi^)(`>DShk}E+?!xRDV>L=plHYP?ZKVr7H1IX)WO#N?z3I7xfAf<WQ1iL)IY&73M
zSL$D2!Z4DSX$LN{vL3|xnr~nl_;D-Z-16-AEMW#@Xo02P1~uN^idKZRY+4fSY&Kx8
zOhC9eGFe46TUm@jR~jMRH}xSN@fRjwn-9TcE$l-#Ef}KmqclD+Zl7c{(t5+V^PhhA
zMtuBVS$zDfzb`|tuSzn7Wc2b$p0Mor?cXd+W>ZQtO%#<g`RJ{X&!LzZ28PRYj@6Mk
zB=N&&c9_YXY~d$ofHFHCYq2)?>kC`_*uOiDsmv2pk%$>91<LQsRbqcI<|Gl4>D0IU
zI5SK`Op(kMZI&kYF>jWBzOnUtvg`bZ^1`fW!wF3fZ)=G}rJG!1fLWB3q!!iW_l0Ne
zq1lqWL?6BF&C+}<Lv-60R+@Gb&+wP=>KPqW#T_m@o5$r@zh5Q}46%f{Pus3v*JPl|
zmq{4lIxz10fr6izS!rTA#YvOdf#(%QJ9&{X%bHktB#Y?eCVWfbNlS6mN$RQTONE7D
ziuW!4_e{UUnvqg?D6=?Igtg`UZ%wG8XdY#D@{ZB~F=-4xmDy4z(xY(8bVh5a4xVl1
zPR}=`BCnKkYzf*I6t0u41DC|4FeFb}6@Hw$g~Yf}ntrFod#9R_wJ>ZPi4^>i_b{a(
zIchGN3Fl&u(Hqh*rYm&HR~A#HVbqX<C=RBpuGdqmY{fzE0&Y*>sR6^IIV?(O1vjk<
zH6|C{{a-Tq@T@T|1(^ntl;&Z5D$!4jijD{_D4t}V5rOfm3RxS;5lH9u)LD*V+LUCs
z$td|~(HEa9NPY@Uq%<g;Yz_=bl*^@LsoS@h{uAkwtn(#z(qfEI81-k>!-j8Z1KAnD
zw+G*Z#3d8YxJQ>Xe^N#qWl4UatbF+q0WH-T8#=4Xs0qLFS4pLu1isAvfpO>4H{f|u
zdM3^U?|^50W_*;m(~kNvj%8k_4{R=3S+PYUJ5?4+RhPV4hQDvQeF`HPTH;3gsfd>W
zOeaW1{E-g1@Z67OGIkBer8TTrK9z^2%NkOW;xP&kfh|&WI5&)WrQMLS=2gfNf@eh=
z`RgX4xRs(atSc3x%W)j*W(A-7bww+o?pVkQ%`LZ!L&G46;Fl+nkmvG;%pxn4I#Fq+
zf$gS`1t~@l_9a?@4hBX^9kWO5PK^(o@sl|dT94@vLE6?f^r7Dgan(fEf{Lcgw)_tq
zZd{m5aiy8Gkv32>{x-9hm?YVmZz~3tPwUFa#_Gt1Y_soV8cXDnR}=HWg+Kmv(!^G7
z=5%mJl2p+GMh-GZ@}lcaH89*BlP+=xSciiFN$U|-0!QR0Y*dBe(5iU8B@c5JpxpFX
zV0>ftEzF7{HiVU$;nHLyqp>}kZpm&^ox**~CQv!e*cF{%^^X*m8wxD{`lN3YObo?w
zL<bmgq{_d=Pk&)aY3X=mA>~tYDlQp{k#(6Uh_nia1%V+$yNEeMPP@-GDXL`Q#UNIh
zT8wPeR4RT~Hi<Mxs9}8Zw*kULp_n@o)9Az(%l=4$Xlj#lMi(8Hrr;tyQItk17TY|D
z7H~NozpCc#PCQg5dSq_tN{9-2+o%^IDz4<OjM^YP@BN@GZkc&0?a6AO86~L)JD-v0
zh;`2-$1gn+FjBNx>{nG^)KIeFNsE+3>5U@YC4MK~4Y%k#NA&+2rGn=;-iQp-c9s(^
z9Jhqz=#~ZBZnvlG(x}}rYIo8{tQKyk!lwkXYFFgO+Afg;SK9L=&#0q!*yS-h*kO-2
z^Q!Yhjz5kF7W%6lr&OuMtuk!F871IGFt2;8E{lItPOqMFPU{)f`>az}>HSW9Z{4XM
z(?J&#W$!Uv2@Ln|{}4mKb5R?^SG3##Ym%8xT4X!LQF!r6raey|dff8towiegQ}OcU
zW_zT>*QML~)vbz^YgTEebj)@WjUQ}HtHdg6U3#E8rhCSi5VnnWRVt2B+noU~@U}WP
zclE@v+^AHzuWv@_{R_AM5uGSrH*mi6hd9_ABuSj{{2#V09hEuXxf9+zcHnrs%^$q3
zj;<D-oKk(S{FrVB++}~efdsni%FO>^6E~A2x%uy?`q^(84Lq8*`&n4S8Qa#I?Q)A<
zKCAAJ%-#vpc(>QKFyR!VDX)AWHHw)Be-qNto#}gQ$v5h{TMvkr=)JqczP&Y^(GTq+
z>vV~Z282J~-|yJEJ$0T{v%4~Herx2p!Jf|^kIu%wsEnOnI62$D*-=}&SV;SxD7B60
zTkM(sN>8=AS$z6vn{D0Kux{_Ox{v9HbfvphFoOSy0>cshu{d?*6nCu5R4(4GJ8g$%
z*%X(o>71eOWo8oGdT!#;nr_u`+h+QUQwn#tRK>e_!A6>!w3OI0(^ZbrS&)JRPhZEw
zI_Qhz6V+L#c*2>nD>v({+|$?rhDfo}TelSc=(HaCuCj1pij#?!$%P{@XObRZF@qh?
zP6TSOWjMBpQ*Rs60#0avJ?c1R`@B-Pme@&ch^s1-k0wh;J+;+rsknfAz$cnN@TBW-
z=apN!>+rSh7|1{{@2F{1ZmSlaxeruiEdKMKMT<SW&rrb>(!jnV#Syk5{9h!-Y$Wco
zII?(J=w;^oi>h@w&!|}&{L5%NYtK|gz=1ADim9+onLAY#*rSVorLuj3fl=v7_c~Qt
zzg_pXB=u3)>9dsZGprGlh{`>)`+E(9OMUy17vfil2&Y?+5hpZx*e)x8B4b4Of))CL
zYa0R4-AKj;A5hU*XI2|qobeVT<h0+o$?2n<zFAeapH)rp01Tm<Rb|g?KSR^0Jmc_a
zb(^hcby(FwrP4L4_iLE5{OY?=D3Q@=oBl}5wv@RG6e9tbV}%jr3Qc2?J~O}=aLN%H
zum#cp;Xo2k*e>#KODWLKr0KV`*>tV1XVIcr={D-thB8#&xT!p^(q##fEi6=uRz)dU
zLV~Zp?=4261apBESsZ1N@LZpD2iyeo3`k8D6l5ozmccV950GII8Q9Kg6nVOe;y<G-
z1mbw;S4(k5foP!3v-W<SSlxQ2iz)#iP#9fNeVCSvE~lw2eHY&M=Od}89)`F0_IA_h
z|A5Dm71sDcIA}@AswZfG|H1)0cg9F<23?HI0j5kBthZ|5*1KQ`)AVO@HZ^_P-)D9o
zbNCr&yl7)<X3%VZ5M&?-53=kmKK+5PRT?a1U^yUWn=L@YnQtHhqdkKnurl1TMpt_q
z=&^S?YIPVH^CBw`1rJjU0PUT2dNd}71FT@o1GG3EU`6tTz27O<P2H86y*GFYc;Ina
zs~gPa#t-bE*-gB&gHl>p+6C0e@CAg?;2%SS5e#b4l}*)Cdl8Yp&|n+|eNio+hs~p^
z%JbxRT#<pToew<D94(nzeH0P_)OE}50YhmKQpLBnH%PDRxQ5-@c|lc2qCeTYsj|b%
zzJOcl`AGIb+z*XE+_*P58I6uVJn_-s$@X?Wh&!SAAnvDs<L_<j<FJ>**@c%r&ZF6<
zW3wWfAHc2jywv<6?ss4z@lf_%U!os&c+#49=tAQ^(A(=n`Ty+Gw0f?!%*EM%lZ{#_
zXQ!QDca)awswMY45sNBw24!s!w+IIlbw|C~vLgx0xr&P>&dWA2#hP9T#fe4B6p<WL
zpL|r7wk5*+!lYn07zsm1(kWlA84x~}g~b7<n`-eaq+%9HNZfCq<$-)8NPeM^+{uL#
zk4dc=lQ;>2B4G709Q<ZeB%@DaW@sj<R#wQB&!b{nyMZ)7?n}xNiS?G<)r;Tg=Sg{*
zVJ;PWRFx<;`e4fwoUsA!!8Q?-Kbv^mbXmG(kZL#vyR<Za+1F&u86c=mz|A0-R<g${
z!x&=CQx!cAtobKBw3qqQI4aYF0Tkp%!WlxycB_Puu*r<k>?nWG6uzsz%tC>iR8^n_
ziH18x2~<EIPyrO^q+csT|LNT{1G6mKPGrgO=)w_!z-boAOy?|HhowAbZpXtQ^;ug;
zXWMY8vK9@JF<@itv$cbt0@@RJ0cC?<1@sC{)l|-&Ygc@#s=F-XpZ~LD#_@^)Dx}f{
zFN`M5P^vSEHzJg5GNiV$#WuSuJ&16{E9{%WomlFCH+j=aCoO%dj%$q!{etWb`>Bmr
zh6IzCiIQ4@IC|J!V#BKv{LHYFB>tD8Ogf9!O8;dQ0J<)nP?5+OP{)V$><P{WGMyAP
zmXySlP8Fz_a|h=SB;_|cjH;2!UBgR77idTGGV3;@h?xZUkj<Q%SYgzxI2O@JcOfT#
z-0Gzvpxd6O5~`)Ylys>`k0(F*|K144tS^QUw#r_%3<p+xZ2cxVk{C7%_T?aMDjm#O
zn94P03FT!(p$5&6f3^E&-kSS~tP`?HoH=$j-eU(2xVYUeeIz>%T=C<9?3)5;BX+}n
z2DuxZ+L~vLcLMiTOjZ#N+MUU*LKRA?0%y_~3_<UOz2EXxtAhuQtOZ5m2d40}gtbh1
zKGktINu@9f@&e#OT^8<12yCnY+{$sTamq2qDOerV+95sIspU^#Y}Yi`UHrk#JS0Le
zoRT=NF7RRqmO$~6NU}Jn<lx5(9NQgnJb*cAXfUrrHHPKupnF<;Z6_Sl%s$(!ZBZPb
za_Ax>j4cJK!rveS3HX^$hHAk^dHHKl<~(L9nV8V1&f6&_*2@H-mMIk(G>O0>(m)AC
z5Ph&{i;U%gil24~uN7J+8Q*ah97+-r)S;c0uqO-{)hW}_P8>ptv!&M<y_AnUnWK12
zi^HGwJA1UKq$z<gr1zQaG0N5}7m8Y(5cgo4g-|P8|NLhJ#^f(9CsoSaCTd~epSm!S
z?GJHu6KopSN$^2av%Mb$E@>W-@|zqmyV`beRAnkiDuZ467w*}P4lS}BCAISY+ho_B
zeRmNb?pxOXSs5UXS)<a3XDHLhMQ2LNWCz@GR3(a1WZ;j`+az-V5MTu=P!7uBqwxV~
zt}>JYb_lg|?pNMYmuxaxp-lS_Nw%sq`w3`O<UEg0Ju17X*|s-;2K9~DA%3>2y%Dj7
zJ@k#~PRW2UDl&HEgcOv1@lS7|)FqOUh3hU2ppPQyA<Ct4muUkj3z}<DKIO@vmvM7c
zF-(>or*%G4m=idJD`+XT*D~fwz4N!e=i|2B*>8hvz$FL;I0c>5OaL2p+A;m26rr)<
zC->>abc##@5)s1UbkM8qq}ZPBYzaCR`a7(SSe@#peU?AwbYlJWEU0#s9<xhKt97f4
zwr<xw%zwH|UvRY7ZFSfCbuS=uTp!lkte`vARlQxmP3vviu~gTIp&Q%PXf`-#y5oh6
z_)f-|QNkYffU9hfCiJQZr-~USLS+o#jZRbwWW(v1LBRTy>WEXVtpS>?gHGLL>CLLg
z49d<7tAVUT3HrRP4v(j_Q*nA`RkiC0HL$~(#<s3IalKyE+p5aYz1nduZ2Q!7nwh+G
zO@?h`CUVoAY@Vh|0LK!z!8G_9Y$IH<p>;Ub-)HG0o&s~hG3O@-Js5fX?Vi<mZUfc(
zbY0<UX2!KT0K~WdRsT9J{Nulzw%gu?liN1Rt}q@f5QkeX;r4EJO7FFM3+%A>H{7>P
z816HkI*_`a*Oq}C?WqJZ1cZJ(5JgkNhTnf2Bm|G7?W}WRz-sFtF5p&Np6ODbgQz2O
zTYuDdEG7t3m7hI+z<ygp_IDqumZR3b*f~+PwjI!_?>(yf0S9!W??m;K6F=j89i~;^
z1K=C26};rb@$hVKJ$CeY=K)+xpUFUW<Yhrp(!t^{;}`<G;1A2@GCQ*39W%)BN*!@M
z`G<esulBUymEwb@_=B?byh-~ed+C|`45pB1Q|}>!;cGB}?=fpvLpJztMg`d>_LPin
zqZ{pb24A_-eL`RO!#l;{1w5gDw}_7{&KXW6o@m<vTaXiRSv@X8Y!YTvrjBWu^UF55
zJ%EN?M#n4#bk;3<OX&%;PF!dBu^dD?TP@o!*s~=z!ZWUHN5{ijg%;jpFAlALR@wOb
zl?u@nbben9^k38$e&*j#+Yd4X;OZIVg98dLvSkcUKp1o`a-w>`1YsQR@E$WUQn!Rw
znC=#5c2{vmBW|K!WDb!j%v)4y&#dj1X8Vb<ptV5-zfI&6S|CVWXq^U$H;@c#Nl-i?
zV%oh`-}}V(;A+!3P4EKU11wN51+tQwA}hgxz@td#Tp_1sVumH`w;lSBn=jZ_nW-`e
z?^iP-s4WgVADeWa#?#-^6#;J{CSp<c0;(XcC#n?%ys=&US{hPp$|;U@9U1n{YD0hV
z_umYn&U85?%4GW~VlhKm7U(E}6_^=CbL27uG*GjI#Wpodvo_M97iU-#HtnLi{WeI8
zj?OC;c=M_}ZX#f8Kf^z#>^fDeUgm9YC)q&-907%%(Uy$MiekY~AH1`biuX(X^cBo-
zA`2goN*0!5Gd5v`YOve|1tB_yu5F{McBnn(X}d1}uv>Vv53#htT^ro7j%b0m`et`+
zb}Gu4?hh^FG!rK9kKI&b$Es9R5YlI%bHVv4XhsHeNFW6RXlgI2K?sAx;?YhZ0$MCO
zGhm=eZBu(Cbn5g04`ybVF#0SYF^Ry-Y)(QLBns#D0Dh)Ro3p5mO3>F*G4^8vA+z2&
z9RfO?dJs@O1i`FyI~V?FAAp0bk}wTof*EkyDHyKf5nn;m8^B`B=Y;Ttsf8GN3pf}H
zjRX~LBpB?n@xq=bxLI$39`b-X2E3#mwTeMg1fH9A5I}DM5#JuLW`}PEsx<EX%y<1H
zZIhW-FlL|(lc2DvxY=|G3u{LzvPLg~AdY)mgNd5}6UnDEI7kz2&X8sa#85h#`jBse
zI|FlI)Q_bS9@b5OT(RC|b&t0kmHD~%L9^S^r^i~eDY{{B=)CZ!7p{M#W3Gw0JTlz;
z--kE?x|~hFbh-b2Xpj6CMwkBYhc*XKKk(}R#At<AJbpBfyhPzIL$Z=%^d?rGFSC8*
zLX6=ix!>2-JP8YV(n`nNQd;TWvb1}D#hS#OYI>OB`=Wa&98;XnZ0w_3O2(0dGGrxU
z=mqTeCW1?YcL+#=pC+SU+~rhTPEf|`NUWkx)s$1ss=|g-j2oll!aw|mIN1yaXo*8{
zDi{+&RE#a$JO@Kxswlffc92Y&ZW4kh#NzWALJE0tjkto{WLx~)?_~{;Co(?<(>lt$
zcEi~zMkVd@c{KZ>9^rsE2Ub!}gQSW(#e(dQo1Oz?;9=9z5T?R%UA0J=xY#lsDO&%?
z(};(Srx1P<n<3jkN(3daA(Ut({U>Fz%OGg)h&^yrF<F&apR!xRbAm&qJ)m9Vb~AMV
z4H6Uke`ib+g|Lw_S1b9FJ{3E)pZPVw(N^tK6@^Oaq8k3VLo3AK_q^sdrUaOR7O8qy
zi%+tsl1xTTkFnK0%w!(6BIPcvZ!m_en7dHy7m~`GhH0U(<-(0gYPSZ7eWMSsfV8N}
zH;)jb@B|jV0$;F<0jv)m!|&B8aBXKgtB|RNAq#&WC&2Mf(eC1n_TgDjglG~5pK(s<
zzCm3WOA2s60}Hj}R5YBt$**c7zE{1aI^ZO+-OALsS+jx%?LpM)`K8*7N)r>c3qXdI
z6%1%*K97D%S}@nWc4@p*;urUIR{8Xw<=4A#97b%7`VlY>a%SNad(&}Z*0leVF<5e1
zFN^^~Pe(v<Fn#A^CX9!myNT71mZV0p*6O4L1v>$=ZZ`acZC#yKET;4#=9tI}Z&E}d
z8Q@a9NUoeXtiOqtS%*NNr(K_sn!E|kHJm#yyi>8vNdp;KAtt|oJ`%OyvvlL-qBMlU
zfUGgWvp}L^2ACI*;J-3-C>#h1?Ucbn0^`gg9;9Hza);Pesv_=~LKgRYIjK{&3^rDi
z#H6Q_79Y-KKc4`8$^r<;97MY>qIMbqi;z!s90Eej8OW1yEBmAt4wk4KWm67*cql-g
z@x>qiJJD$Ucu$0{TC`btAOf;mvy#!0o*Sp}x#8V6=>;5NghUCfHo!@gM?*af4JbGo
z2+9YpSs3pR!m&nWTvZ0G9WgBnw#P<XIaKkAID0B)ALzy3c>hSfF3$nB7`AS!Nr<3!
ze6g|{bR!Dk*nyYCti4C=Th)i0d4(b?Q!_5u4rbt5G&v12WyD2hi4FC8^?mxy6{ix`
z@6scxuizhxM|7z7>E~j0>E|6U*k^9}sn#P->wM;zrj0PQLh6#MB;AYuLD<JBMfi6|
zy>!-w5A_8_PmZvgsu%1{PP=WVIGy}U;z(IU2GEmu`5jKwAJ~w)GYjHS^RZV;jT+M?
z=tpS91Y{$(N~2&b9{IJ<V~uYG!m+|yE8XPk;@K(7*1!RbM<(P%EDlkbtVfszkUPTC
zNS<j&cH>cTc2q=ylBXDSH_RFtLd!7bW5bzNU4_M;e@LX0R1q!l2dO2;CINTyoP%LU
z8ig4^PRvCmCS}|2S3m{YB?brK1DVC}F{2Kf{&TfyrxxnFRIN5YHV;E;M90oZPmOSh
zO0iyu&wTaW?AKdvc%$n!0FsdrIGX{2j9<rGEu8W%ix?V^aZN?WPStECqg_Zdj%9Q(
zgg+8!c7PC}v>g)hfm7A){Ab?_yp?9)N<z4iMgQnhJ;rM4Gwsrt)3<=<Bk@JVpi~W+
zsu_s}4){5-TpgoSN6)ki;sNBR;;0tY0v$6ykIC==0Qm*e=o<9mTFpCGcga*!Aagt8
zVL~v9x}fg-{??r;HSBQGnwL<QVk^BeRTX&|vi8Uv?_-NHKsXcm`c?-RBTV=Xt!BF5
zC(x;nz-1<gX>MG!7*5#?l(jcTI6FRW5VVUx8b%`}96*Gi(K*ls0Kbp`C7A(m8c<kM
z;7t0==~vSV{H2sy?ftfsm_~Txah-WrF^>s1$h1*w5QXPW77{ZKYJR~uqu&&JLrM`K
z{8USi{e16{_{N9ro<ra)J-x@g#>ABB_)_ZhjyWA;&XIFYe}8GT1OVgSx?tb>y#1)Q
zT>qGIJH|)BP@b_**kh%jbHTPt3pSx79p@Z{L)E#U^oY|r>zuL2SS}WnSGJhrG!bKC
z$AVyd%n5palgT)o95;=dE2rzK+SffWw6h$4IzDpzfgRq~(HLFaHW#bPzS&Awp|^V>
zJ{oV1x2ZqValGBW<G($VI`;=JqzvNYrPw~;m5v2RqS}u*_QT5U%$R=^=2dyDL|EHG
zf1e`Opw5pj+M}gg`}>JnB2Z<g-C>r-yUy9il;;e9-Dp+ir==6X#V&!#WE#{saw<4-
zEYLeqf`-1emDaSkru)Vk6JH9B)oyOg?W^50m;S=pxpV2)b>#+UzhL=;*4_H+>g&4u
zxZWJM*ZYUJ!+5;q{97lFcZ}7UfqEXtpYHKm+4JnsG5eZ&zt@Cc>PvwppJ;}h2u#EK
zE=!3-2MAWPEEwhGu#_w#leLt0(8E)ZC>8!`^O-;~i^2hw^4soxMOW@h)9qvTm}uhm
zc*t_{AFW@|l{v@V9+&>?`wlSV9;pvc61Z|c2qq5NZ5$p8&e<<a4&zZy{5bA&?+uT=
zYo_|{4tK}T`DRalK-h-hH%is*`}=1~V2^>@IorSOegK}h97$jSF)TYK$|f%(oET_1
zUeaVg4+?ug5Q}DTOvwx;?rFHag~wX&YaE>1GW?4~L$vOhu^V95PTCln8=N@!3m=Ye
zalfAK{nrGJ?A3*>2f`Ea4R`k1=i)bSc5Ws-;~~A-xnrnzZr7Pg;oe8zx__#}IXG$G
zWFH=$blduahA~k)VDFzK)MEc(-Pe+#B;dYTV2y;Bg#G<s0E7hWF+&9q^EM?dlNOZ4
zF^3(zcn93TBDST=%HmR#1>j)0iPP#|@VxXH51#i=PW%VG+X-g}hYBDZkEGG;Sh>Y0
zN7g-s%}&?JxZn+)1ls@viJj{3N4wuryk9*V@QR9X>Pinx+k{_ODG@E!V}IAi*FHla
zf@k+&>PaxfCT$=>y9x?D#b^Tx(JTcx`v41acTbBTW?5W|^^BS+0UFtfb==)QiBp@>
zTVI;ATleq+#6)YX(#lZ5Ta4qO7d@}B4^R#7H@@cv{Qa$CXVlrsN&TcQpRF|JO1o=|
zJ>N2J@>s^;w9V8Fa1k>UWj5?R66^y?Hl>iL?Pe?(ZO_`-8&x1yf*tKgrVfEb3UCAj
zM}(?Oup%vcG?XRp1+}T+$;Uji@z|v0G^R`R$i(xp@l0GON6v{D9?$3#EM8@EUsaz`
zb~T=NwhnIX>9d9k!5MdV{K=bnf66{cm!rIN=0n0Ix=hc9=KfDeC=%~RdW?6VsA*lc
z7Zf<i6D7e#wm4cqoYbP%b&K0G(=Y8J$ifjoX%w5mL4d(T?U2(qJbBu-8g2J0fFoZ1
zF!n!H**Zv{#}fyix}|b5{_<q>yx!W6q3G}~*Q`!v232ylay%}#F!)~l$x*{TLr(+7
zh;pV9OE`hqfPOk5_?;(uMTATCuF#?l^aywZ+T<c<fQ=AvqAjhbQN)RR6Dz#Dt0S7Q
zfATR@R!?~SDo9<uD2o-EKde#4t%F1Fot&syA4}66!dnu>vx7#ZHll8+%nia_q0g*z
zz4-or#YB)AM}z&m2+lg#GowT1c!cTUgnEwXp$kYhty#EQ5>tRcz#FvHY@=$UZAKRf
z7Gezp^=5B^(5rVL`hbD)BhLQGhTmdL9Gu)b*i=0Op5|`pA-|rFl>x3*QMF_tu7$(8
z_KlCesnKRf7!M)1QqUm4rU<YCmhu5!ev51sd6@)=Gs6|c8^M%1?Enm!5<}9*3p+%)
zSOA0cF2bWl#(wW_$9)V7YvOsP1doMy|767&C_2`NJ2X6*Zq>x#uyJeL@t`(pLxsj2
zaqJz9yI%bLUkPQ^##F}&w2I0)8goG~Oky1|`!xIQ)DFIAYK&frC`UFs!;NW$#z!9h
zIy`zh1hNNVj*B%<IbW#-R@z8nueFixtIs)@MPOfJF%VPIu;!nOeYHCtNsCs|y5$b*
zK^bYGeYT!qXhDOSjQ4f;$I7uV(ZQO*JBRI($pNS`I>4(2SRTlJTf<DWCJ!LeQAJz}
zKUwY&xRgvsDVLHcF?@c4;Y~AB6(6ymk7MU_b*|Fbug8quiq)+Pr^hDYCVU*B%*XLp
z)7DjA0Q$+-=^GxeMR->IZ>pcX;{WUVQ|t48UB4P@0_K{le09L88`yft6iYBgW$^l5
zMdIP+3I5Vqu{HGYpANH<FOk@hIq_EVNB(<$vBFWt{A#3|H<q%*&8s_q-RirMm)VP6
z6qo`nIAZCW<G2(8=isA}j}g=WzG3vGT;o-lRU80ZD@MA-fZ?58JfmsHn+Lc7n6dom
zsi+a-pwCkc71oTZQS+^uIA*(}Pqy>I2NEgDm`d^M39Jy0k#OnE?Pg+ej1-STwmp24
z$t>epLM{v+g|-3=Vd6bnvDh`6w!?lSZSiA^ys<%ra8%<b=&HQ<t^-*hg~r3CQ4B@H
zn1*W}OxTvj%k^~zJz;b+zcH2IW|Vbm`8e5$mHAp^n#Z{tXDf%-Q{bc#di7ZAmRj<l
zGGiZqss%s{$57CR?Y~MCE|{{}2m__k6mAXgFfY@9Ofe|}=87lpXHEsrAP@UZM%6aL
zl)SjemXpk}{Se!X<MePe;FWgY*3)q)4O_>Yku*IrsPC%KHrzd=W|Vco3*zZ^FPWp|
z(|euX7eDoTKJ52<4SC<NL6{%zrY3>{`91?8h5&*@I+b^hF?&G@4Nd4hH~@?$Cv6LV
zRQz~caNSvGBy&!jsC__C6{W439s=}1m4UGu<$Bss3)KX0E_qOYm)3WFx{$=JN6e#M
zV<e^AodD>>`Vcn5KcZz8`iq1D8#>bnqm0?DRSI~{%SL;N446@{Qm&BNg%?rnEF{ik
z><zr@$illGu}}3L-rL#;#+-TY@Yfru){O>`M;#m`brL&hsO}lpI~Zs*>`?hZJzM$A
zuEb0mW$o0W)YJpc5p&!+tRKZ8@bo+`751l3BxikGcd3@6%JB#d@J8y%DfKY+R#2*^
z=?ut0-NK*2??fv0khN1@Avxp(o8sUwh^X_p>M$Es(7~ZDRUdZ)x<%`QN1Y()DmdQQ
z^l;!*2|XIBTYKghKk?#`Urx-Cy2y80u|j&FHi_w5ghru;9&bJ)d^Fl9PAbqh=_^(R
z3Pnw0^pu|A^8+Y-s0u;Z!rW&s-yE4>sQRL4hR2u_*vdEv)~3rR-uYI6RB%+st&w!3
z9=6&*Vp;!+LIP*?+&Hf!CdaS#J3XnBb}_(7w^8N5i1}-T>Oq!t26u5%{OKBhj0TFE
z6k=E(FQBqxex(KO6A;0^M&Zt<5raLT(L7Wdj+raiJz?wteb(zT<;kof^}{zvp^ZlP
zFdrip!$>NY6JiEo84VZ%JJ6wmkti4AAk!O}ApH6bqD7~F_Dyc1)9N(aTXCLK=kNl3
z8Vd}}v{9}*scm*TCfoSvH}I3M0DDSBvs0(qu~Pt&qZFH1rHT_p5;inw8bCQ{$7W>|
z)eQ_Vqta(Kju4YlnygpQHyJh_?KhHG7iz=r7=CBeivC#>skNV(L6jbhkZ$BnDB@1^
zDWD3Z?W0A~37s^ukD9?Vc)#2P(5pYED9lO$!@lg@&<IjkySw%ja6r$b***DF@u#d_
z`<ETIvFdKU5VHO%PgVS>*y$Z)-0cpwyuEN_p*QHUS^N>DQ9S6`K4Bq5O?(0L!UMi>
zeZ`=a2qOdylJHrTVh0xiknnubD&r1b&>|4h2h*}^n_`=3Ddu$!uXEubC@zKax?X`z
z1C9fJy`s~(7+@=v7X*9ig~jh5L&eyJW97itmrjK+YB!-R*h)buPERqP)2AUig$)~$
z1<b^>hdXouKKzDALEA@bya`dWQLy01KFh0NT@`9Osk<hN4FkSfOB$GtW?w-EiywX*
zAcWUhrusXh+UPg{iWUedOk)#KGoONtXRIXSpw8%CBH*1SM98mby4nZ9yW4dA7=(l6
zOZT<44w;QKZU>~V%#ARNq#5+sp2pcqy&%C5Lv}rV@kK(XXs|5l{4ndw1_oQ5{TeKU
zT?p1NEMtj#1Ak)hg4B^j_=V+H*w<u4_Z|0G`gB}l)tlaH1hu&RC%zO|mHD7JIXZJ>
zA&w`=ClF_BsO){Tq<-PczdWs&dHc*1NiwY1Y!C+h6yX}|JW6;{kSr)aWj>LWGHGF{
zLeWGR$VP^3G4e*~PWMpSD7Ka>sQXyGLJ!yCN~01pzEoIWaKd^)zt5`p<~CJ$=-&c|
zrjgysyYN9Vh}4*)0soLQjjpnWXc(mj%}|-4>8o)D5&)r(Wk3`ltv~}};ANNC%Hyf;
z1}5{yJ<8fvxZ9ep82hA+1j1WA^+Bsrqw23$teRJRz`6gPw+8+~Fp_E`ZBWV~#+IjH
zUfyq{ZXiwy2cEMA@Jel}npPeCG6XsbrA8qzYH<<7IzaNF*J^KKwjCyFEv(gA{mNju
z6-!0Tn_8`0s2NVBX28uMXL0Nc?q-#`)sOKCl?O7GwhgGNGh&aQ3I=Xfd!s0g6(Cuu
zA1nG%=82M7)gUlfLIby^EMQK%I@aGY>J0R$Q>uMb;5x4pyv$ipJ18<LopVk`=g?F;
zEyQkZNA$KsJySu@SslGYJ*;}3@4u=3i2aj4wxjl=kJtJpZmy4YJHPOSp~H901h>@x
z$vx-P$=Z1@KBFto#UB|6f-d)*deYt2{hw6j`0&=a68F@<q${(-!S(~+{;fOCI_lh%
z_0#>q$DH(IHip0U#z&|0MEZq(wqrWgXvyo~Wil6V?6Y>Yf3xa{W}FUvOlgOxJ=5zO
zwM$PZuXGM@&#g{7G`c5!RJkRl6#EWk_w=iM&qk5bg?QhTDt-O<7(pMy>Ar>9ME{Rf
zJ3n;OqZ5jFtkL?B_XItY@#MMsi#2`Z#Y4_RmGOQry#w3JtQ?A`-689TPsKmXn<l#D
z4(<P~;eGW#`=$TnN1sqTyz%H+`+>l#P1(1CpnWU_w#*PQ(3mB!Cy!;qziGl?uYHS4
zfHR4C5|C`xnU6MAwAXpOUniA<+tG8k6sj8!zl%8k(RAY3h_4?!UK=_Qs8nL)#}DWs
za6CNsv2pp01XE+^oYs}bj19;}JPXMu`qc}1uF}Wv$paVm{tmcH&kK_a9uDZl^Z3q>
zj1M2?ZLo(29(zjnjj5aP+_xS8^O&*s9wfR6-+qTm`DTlJD8#)<-c2Dogbu`!Y#VjT
zU*iq3=-KMe1E48Y{;WhqO#~j1KF5OnDS<%Y`TIu!LS6*$bkrZYjhJk}I^~~gyiN7K
zcXG?|lhK_0+Z}CxJp7BLGmXaFu5uKd2+qxzKmIR+Q(pJ6vBSeNcVCF3hl5Jo`$tMO
zPUwBJgT1r6?hKxdzZ`EntL~4F#Sak+(x~lOaN@0lTgJd;UQ%kpt37KEPfoP9y)gM6
z;4A!lVn#d{49%3_DJ)LnN%*o1b~RiBxjYNL!Rt1pmiR!7P29?!mbNI>2Z)3*?qeP~
z&p0m4$!B8*LAmakvq9eU@MJvQPmQChytnnJS5^gH=F(g5?yDcrDs-x#FO$6$ZSo?_
z;MTZ2s$$+m`kGpZ&)BneO?&Mp;>w?W;z!w^IC5Z;UKx)M+U`Rv^tBtyEkFdth_E)d
z4UmYp)=WoU<pLT6&tMo4Q?lRg5e_B1Nl+K?K|ZiX);^2qnmsM?7N;;hxS23J!}xGS
zgi8v-^XPl+JzoP>+S2}DYTolC0;%2l$7ysz-^$BUy@iRfN^PQbYYz?dt;)U=W0mxL
z9B;k5yx`md=+;$vCZ4m)qhL38e(Zbq+Z|XQFW9F7B+V2b9rXCVjC_%W_l}AnfNd%G
z9`R{34ID<bh=f6tB<4v%*}(iphz3AB!tNbWvm<8oG*D$5I=_#$ln`>~p!C)Gh&H5s
z56;*_1<*uwPklJ3^bWS(ToEyEz59>@98>8%89!NVM=$ntrMu&@wLR`_oK>Ul;-~J<
zLbVP9(L^=xS$niT(FzcvW_i6$gSSffRtt>s?h{fLB#X^YfISqTECEov0G!|z(3KU8
zZde>04ek@r5EHSjUjZ9Q%+eNjx1w1#py&A97-E>#o6BnJ-46#T`q`+Uz-i^4`W%Zx
zW$3s*qm(<ls~u>G(Ztp>??d*!_~Z#V1?NR{2Hy#KsDGjru&BD9eg(u~nFUA^MUZ#Y
zSW7!Ixt?+AW;o-7=y8~8;hxAQdbzMOqHQd%dg9<=BI|z2b<2Be>Fh4!p1NuD{IbV8
zeK)Ynv7Z&+*s5a|F9OBqfv^c-s%?eCg}AE`eM#?*xBSEJ68!I>YKoW|I5|dm@Nh}X
zTX2jjraHRY27yFS0##!Q>=28JE~f7paxD7ObaflMyf}t8xrqdteK=xBiG#s-dum^K
zT+Q9>5DJ(c&^5-r0wzRcVKpAQf%og;bCtQf_k6*L?|Bj*N|j@4>mYkL>JLAChA~Y%
zB*0r}62XW^<b^Ld1->I>68Kpr=5>L0_-6V+xy>Tc$l}x*Zy)W$GMEPpnbCZgW=1m&
z4`$Hb&<*aUyL9o{t{$t=F<VXlVDg6Wsk=Se%+#AiPYn(o_ZoNX{b6l&&FyoZ(Ki%l
z?>4qK?zsW$sL_2QZkS5H<FW7A?4`kx6P{_OX<}jo^7_s*ILC$|uiDKkeFVb{$EuTi
z_)Mv}HBKUv59xH&Eqp6>Zw+H!%m>WV+T*d&S&)zHuz4LnUaK|cruE^LqhrRt@wgTg
z!03+R``jKh(zK!@adX@YKZ0$6Lh$Y$7+p`RJHRdv3(jp164_N(3yo=cd1cvaZEnB@
zV^<`P+%^YfXU$Jw9P`bdR9l@VS%l^zV?G+Pjz(hw&=r3<sz+ZrI1uUf$x0(?<s)Lz
zY=tjx7H;(pIzugKx2_Pn#=f+({nz=1LL9P86^gT!NB*cFINgDB_4~8;-p1<LYjC@7
z{Yved4>obSZ+>j-p3(H-$37U$@*3RbBC&wnE*FXQN+F;7HQqKm@{NJd(V)!@kT&=@
z-+Xs&c_H6g;-ncA_VC2(z{$xbCry~{Tc3%CgpmxUd*s2lV$2g^g3+8da5WgiuO+eM
zm~Z6<iX;S1o*{E2i$8#u2XxW=GpjT&hSXJRiW~9Ue7Xd%N}gGjvVx5epX4&M_}NEs
z`MuO3>;b5*!G|s;Q+X4qYILNGOrj3hu?@UQssu5R7c_~(0LKGpz(CHvwm^Ipu8#z|
z09_o8TOV~=tK&1^O*?Cb?wPF5Mg|+30e~PQg~kdZW#~<ndFCtv*=M7U3-^3(TH#~Z
z-XsvXKbndgH2#E2@Fx?iUCEBBS#HJgWndvM06f0XJ4gVtYiLsRgq0MSP#bBHxT3dt
z1NfE*P|Xe-e394SwUvX&At~@Wo(63PHmIA!oAvw048nkp;8KAtjn)yWZ;A^<yP3)0
zRt7l{H++Hyca#q)Xp<SSPmS5&H+<kk0?QVZ1kAu$;2%2#Gt+9kUL}*nMa8xGz-x4w
z<P&Jd_+i4^79#%!BL;W<)kExljWT<+ddb2-df4`Ahtd)D!LXHGpGf3tS<ey%2a4qo
zF2P%8(~7r|xlKqdD1~3ID%k8$vlXMQ)i0FewBXuvZUgk`h&4n%@vd5NO!@eNUT@{W
z8}_(QMM(i<h{?tnV+$%6o{l~L!bi><23&-#I7T!XpvM{MGIY|f9C5pX_Vkplrbe|L
z$Rsdsag<iS$2Kiyu(k!qv1`YIA)pVlX!TYAC}*899aPKg1|OUzoI;N@yjmtsZ6*aI
zgfs@cT2Sj#>XhTf&WPd*DZdG<^n5VWXf(Wrx5G;tX`_7-_^8fWg!4PF&75{N$uMYd
z3A$QzGREeEqOhBJ$IxrXTIVwr-KO^I$J9hLHtxhc8e47k#!NJ=eAS+w@E&mbYr&>&
zXEWx8($QpUsfvFr2xr}3EO90qR-!C@4`Qo%9|2@6&+&$~CRS$4_EylJL-negcE-0U
zko55d7Na!P%5(@U+@yGOrldDHRg5RA{VAoPo~eG;SA~0_*#RU7z&?CRO{-06B;E(_
zX4UIU3x|AU<%~zwD5*a?mg;kQW^dor!JzX=rTtxCj6+EHhC}J0Gr*VtNQIy;t)vmI
zt|l5vpNu12pH;!|Hf?=%&cv5*0ME@U-@I9%Bg5&K;o!IpOqR04x7O(3c_km(=v7vR
zXlTM0{Tbdjr#1D$ArRa-)$j`=s_LHuY5|~OAPRtzRLuF9-b2G<85kA)q)IGC%QWFc
zU;XHfi3rcNM^dH<<_{TcGiXM@*#Iwu>I|SyfDr3A^ZiF6rV?J3%H~GET%%it`Sk9i
zH7#!bVIY&F&Q3Te2g8{KAJt-*8(ZDlbUfgjdhz%FJqS<H)TvCeehRCsw0tvbS{+pq
zRwwT&g|t|)m{J+I3E+Ei&>F}l#-de55p|4+`l8ectRiaW`C0Q6^~8)-$S+g^cF(q1
zi{JlqhTR~D!1#n9-u7{0lgeUFdBFo|j@0qM_k%L_^Vt(q_1N*0Gg5NPco|OFv9|Xo
z$}x?3y~!<F{YPBpz}kL7_r|S~E+__#{B&7H&58S-tH#B8+t>tYGy;IGUN}kwU{|Bk
znBv1J?H8i|&7UFYvLEb5rw^&dH~>y!F#}?(8D44DDMhWi6j5KlPmlp0;^Ne<!c4?A
za1r(s^EO?#O7#ZV-@XN1v5kSl>V&?_4eoAj45_*{{g%{A6T8N@jJ6fp-;85x?gY~~
zsw;6UAGhJJyZC?o;yhnIWiQv8a#LnyyBtr}0RjQduqZnyhFy1rxm#;__fY%VuG^=W
z_)$zh8aw88MyB0SIP6BFE~&LzX)q$b-Smc{1@$qzvsyFaA9jMDQ$~{R4i2F#XX;ac
zI|fS+Z$(cJ_cgw28r;(CdU4BLZd)ygQj={=^SBcR(PY2fVU@?2vU%C`s6y9|*~~LZ
zT|4YwAcByXG<q1Iyxw9YPMsw{CvQ@Q>XCPd(KXMBQGPlmv_REdXFf2x3cju|gIk!}
z6&3`4x3l<gSJ-+u9q+POY-D9j^{GIXh!j)R^3gnA8E_N5fYxv&`>dw1ndWxdYHvSl
zgW(Tam9(;7&&PB`(QB<a`&z*0=AHRCsQ9Kr6)UxE@$*hFVeQk}oY!~gyLDk3lYm?C
z$24!C)%+K4dl;S@#nfp9R>Lwt%Lzzfh~T5)Z_?78%nG69ZO>xAM*!LwAg()aSN54b
z>0NFNaB0OOP7O@Ct6mtvT#N}^GKTedqmCBTcE&LwZjQ=ue%y>Pc9<2Dw=%q2e$(=q
zZ<rIah)bY7H%VEfnCWSI{4N2ik*Q{5gcmOOB&|7b6N*>FHD_c79ub+eaUdQ_%`rNq
zJ=)vSrlVQaqra|rP^q}PwbAIcd@Ds0=^0<mM#dNdWy~0hzx1mVvlEw#HJC_ddmiyh
zc%8gz1az4=QChb;oycTvF?@T{YVQKR_MKXqw)lu<h!qA=8L^?sK0xP!_RmE_aotp9
zHj^gn$`ZX}N1~?hNx=fAD>B{HTkiblH&&evrVpL+y(#pnfjPn%15%?x(|qto(H|my
z%^$B~+`?N)PL;UTF&5{2&I>_39wUOdo33%Ed=;N_qEpefIO=<@99l!OF;kM*3TNu0
zjeQo}o0XW=)AnLDwyz#ppWOVtg3FJ;kiL+Xep5{>1O(4HM@G{lFQj93=LvPzIcwLy
z=FF&_ikLdPI-pBm=r2w6&R2Kp(kb2`-mW@#If{1&^$C>pZ>wANiPD(8)#<&TZ#WGM
zlx7^K=adT7@9FXL`aSOUv7rlk?`FLtj%&Sh6@aQ?=g0#C3!84z9S@A1Qrq9HZ#h}N
zpob5210BwF4-pjhm{aTdh|_xWgI;fXeCY7~&Y^VMoST@#TPs`lmMc?ZTh+mX<*MGS
zJyP6fVzc-BXMc2LQ{PnZ=>48O(5rQabyM9rY(L&{YsVozT-3Fz-`k}678IZuFK<@E
zcP;b}c+9~!JLOrmjR~(?y~pXhUxT&G0F>@hfRpWNR&_iJ_IRu6@9n$aK36%WI_`2B
zrP;V`toz`$!LL>Cs@O++8_vybx7h!3^lV%GxO(5f==*{mrK`1Vjj^8i;J#|@aCPj^
z*7l))>;#|t;d2k3XZ?1(ZL0gE^Bnft3AS<icE9Hiojf}>6W!rB+s?bYr_<vd=j#2Q
zn+5Q7d}usP00u!GN7JPjC+W2OtW*Z5#2I^*Ez}wTe0<FoxN(nUJ)z~aPaW9PjQ0al
zJa9}-xAQF#efWjy$w*5`km<gCY^)g+D0jdRxg*(t6@w*MacU{1Z%CKEqUT(R?0d4^
z!L-d$$GM8<Y-<9LFT;@WCUC?Z>fxYa-}=JjDG#&-95U7IQ^8~3M2RN$M4Pn0kULc0
z2{6SEJk>96Ts~AK9&4Mx3lEpUx|}xlvC6~!e_K0`q`;8re^Li_b<FO1xA(bkb<OP=
z&rmTwFQu|~#qNmT(N>r!KQUN7pgtULkAk)fV|uHu?EAa+*84X*pFe&wp4;`s-WN{1
z_@TKyUz<5QcXI4WV8xr~hQ6MjotYUN?m76>zS+C>yytM&xwfgGaZAt12mZ5C1$h|2
zX>L~*`1dJ>)K)!yRz<%!2mk`)H}*S`;S!q#encD@Ej{cIayij4qbG2wLE$!Ofs|%;
z0YN=sA17jscQtoe69;$QHrusd-u1hQz^I2k;+Y5!dxtYy+U!jHe<iJLy6~K`yXt4v
z`MrB@Cd_J^fT<M%gxt69Rlt|dX6NVr&EC1L&ECFm>d`alf!VEtu(nWBKQPe#%W>to
z;9;UMw~oPG?_68>Tk)Qsw~ak#1z$b`6NhL(ZEK}$b{~t&>TKm?^}^jhOUDI`36G|L
z_Yu!F(Mmj*fU4(trPdsfFKd@=USHJmrE{C+dVlLemkRdp`aWLq>^_Em?)d*%d;j3L
zuI#?EyVawTvlB1g!vhGAAc1#r`=J5ihk(H_G`*w2ySV)Tk|06!fYdmisUe;kO-Z9)
z#9+AD+Kr8FwPZP?)Q~Xk#3}C%2{GD9vZ)~<S{vKtH3`%5Y^|LkF&NpK8rx!v(f;9e
z3~^|cH>q0h=Uh;+W0#ZN)Pf{L5wG7n_uTXId(OE}^>Xb>{pI*h>)KeyFM`!xqJLL<
z8n1=Qm><NkYK#QeC$D@;A2&!rxJR%+0Hrl=BzUk83wHUVN7hEa9*!Q_Up@4G82hUo
zudJIZ_Vw~NX}hc*`rJ1QYbSj=2=^}$K6*XUfO$o&EHGAj+2fv;LC4%@zm|Kc7W#h*
z`Nc-2mCj6hud)L)O$OfB?(8sBan4fByW{a8iVN+A{xy9*q-)ae&{&A?z80Uwr!btU
ze%*iN=R=yLyX3T`UH(D6*BrT`UhzLQnK_OgwSB0bq7^U8er5Zw^nN{@`w>9m;@34Y
z){F5AsXO#k>NIIySA6WBTC<N<CcwF#m{vrNU#saldm-JQ{TEG#U&wyvwZFNWr(fuJ
zrDMTIkJ`KoY(>W_pZ|H9!DO;>I6TOH?Cy2wWDB8wE5L6cGp?7st060D%W}e4Th1Sx
z1Di)zfH>oFD>Bw@q|ft_iTlR%=e<wAL8Jki`QJ}>2l|muzZI(1e_^htYau6URS~9Z
zMqe+Mzu9}GdXQfBY1sw355Wo>S3*>;mnPBUrdQqc!y`0n`OP#3pque|ymUamPUJ7s
zmmpGr!fT;F0mgcnW1Iw8&wl!I1S_8p{}wo>?qv_?5CjjGliR#rH8=K|Q29h>x<HCs
zh_l)|5}7)slm7e(uP6JDe<^M}()LT?tLWk{n=8zUKAUg<Ws?We9Ju1$R)lwDY)ppy
zB)pD`*8REDdcW=gbS&=k8QeVe&6TXG(FmKx4O0$q-F@KL@#RtZM^__}Gr_W-ev2M}
zw)L^gpW;Y1Z*07<uIe&)t3Q2Th5ld+^2Zc*RvKp8%id?<?sylc<b~6jy^~A}to62_
z2<nycLGQ#j|3_M12eay@YBf5HYoPFzgA;3Z;+IW>L}#K-8zG*dBS9f^g*8Ki<!Arp
z4-qHP4f?uc<nBjmGU7_JGWsI0r^8XPF$c8{J5G%4|J0#J3UAT>*|x57x5NCzTfHhb
z)L?3$h!U*Cy=%T?6yrx8@qQ#fajo}?I^j<j8~^<41G&a4-?XP|J@)U=&EHYenH!S_
zUyeI+G$LlSnb>%Ts<Fy9m|x9&{dXRF-76A9t$2@-fCmRV$fR6r;@$?q4Z$i!Zz>`k
z6Sa^$BAAv*jW2Z62y6WYvj$)?j};FR;!Wh9Wvckmj-gm(eyjMX+_Zts><BM$m<YX<
zAraSk({tGtcfWkIL9=OnExeN9Y@>_63g~&4HbeX+-+CVj4z_>3Lm<!}c~e}Z%FX;k
zilY1_#UCn0TSJCo1tp!R5gY$SaJ1#J&x~%)Il%1DWUJ2pS69X-?u5~!uK<7gudL${
z8$-XzxUB12ZwKCNc(3VODDV-y=;RTDOS}@$eu>^X6cj{d+TgPvdc}Le(zhS|Yg-oo
z8UXTp6a#<v&_nDH^l}Hq{KdGr_7KHfQvVh>^GB}7Um5#X(|;<Bk9}`&pjiK#?R_=D
zF`LoOiDDz_ZtecSf9{!LKdYYoPaaJ6Z(k*L_)i>6_E!gO|HHOLPDHz+e~M6;uZDc9
z@yBI=D+K>J&eF*BT|Pl41jlOhg|#q4BE+E)oc<>l|NAc=Jak2(Xf!%AAuyHuD@jg|
z``6%CR1Zmy{3Bxg|KV!~CH+eu*#5O^mukh1md9$*bdgeR15~mIDwOFVMa<Hl_Ob#X
z%^oCKc%11`lI+GyAuX9Jxx#DN^PK^&Skb#xuB?0f*TVY6GE{OL0y)R@*9tFZ{mhZD
zq3Snf%r8<RwLMfgR9|)=tVNeOym-GJxU7pEyT?-)bv~T^=^yIo$-W%6K3%W%_%ikZ
zA_E&}-Jm*0f+y;M6%blftrmL4GG}hdK;>f`YXv+DEda1BbvmGQc_rJE>v>9bzEaQq
z^g?a=WwIG+nM|{%_0wv1o?QX&I<QvmSb6y$69ASqP-)Kiy{`iF=x_YS-(-%8XJ&w1
zB+1V9?8>g>4sswv&sqrZQ+zoml#xE=0E2J9Ejo(bZcXdg^Y77x(r`%3rNR*|D`&VM
zU1?+ou7q?0DLx0%kW&X&ZiPPRt;%lqeQ_lhP3PKkr|TWH8Xe@>Os)O!V?QlG77{^5
znVqoT9>~;c8PaEcAwxe?%ioYg%2o`}(~ap&X5y3NOT~`E^&sne)IfZ7_!GRShD3T=
zO%x?%hm^yg=mGZhW1vqYuV?eOA0x?RX*}a`7`$@9*G0w`Cul~@G#cmIC7+WD4>cG6
zu@>M8^4uKT-10+o$OFh^ra27}3SrjDLd0Kk@d`O|J;-NT>Yfr7N+&kA>B()6kFV56
z0XfIOiXW$KkSISpxDcK{c)C`b_<REquf3j~WT`!mM4$ItI=~-vrzv+_&V*fK`@Kb;
zq%w4bW+whu)~hCUcE!A*I~1vWM=9IcxM@1n3~96Vi#Mjn)Z_Z#O18f~r>F(ZtDfvw
z+)=m!`w`Mi_v9nU){4ou{6mCpB?cJF4s#rD2tr4PRxLL%u0pkv>zDoQ&>dIy>Gtf(
z*w}eL3`W63hJw@Tblty6JLPG^OJ3r!X}!YH<^wf4oqBWO5uVY{DK_df|J(yN<altz
zbxhUp2lZYRZs<de{Pc^j!y7m%T3^G--0*7n82*L23Lg?1f&v`%e>&UIRnH=MkLd&X
zo-k(>{~l)cO@rdFuRUr*t>hJe24W9y_^h)&EO8A`CO2`B<S4KH`0wUXUVi*^P4*Pz
zL~ajQAWvE`ieP6Y+Y1jSa)aPHQufou%<BLF_+Gyyhf0On5M+^C(vAd~As=+RFF!Ki
zn4l&Q^k)PA1^;gO!!2y)Mwpo(RrS6Jl$+IKp+aT(DuVH|qa?R2CijxBb8-rPtwjc_
zsZRjT%SBL&aIr#`<kp2i(e#%y88iE{`OJjM(xJz*LO%JL*YVg1m4W<B%(Nd+Lq<<L
z)?(zNCuGT)FytnW!8vy;N1*&OYmjSV_gDAr>ZgC0prD5*<K+352`lUB0oCAt`FKa>
z76R1r$ta&`sIcXSw8*)vif_jtfiJ*Jphr#AnS%s7!G6k9Aiqbe+-Vi}@YBy2bX`E|
zjGFNIDF?BzgcW&Y+>*P_)qdu3ZN)eClPu|J)tLC9%!H92*W^*C5VXODdJaYcv1NG9
zG`GpKHprX?o{3DJ2<VqT$-Vj5{~upWyZrkv4nY%ZC0{&JzE=MHF;MoGzy88MAv@r{
zvR9ee{!efr8;%BsY%1N2DmMu~TOQ-5?%(|m080br+B4SRTI9sWvLX*Wu)!xl{u-H3
z^8?gv=S~?u06knE_T+0kx#vUgr!ucR1}D%jiav5j+C-4F$;Xbq#!YX(md#jc*au<9
z+qj=*g2x+I8`H+*YA0UHv}kJg887-g&z(@51fX_4+u}dQjjewPc7)}JKh(L*<n(&u
zvFVjSe%kZlQ{Q{Y57}WX0{?eHX}kriWUaMg=4FC$r&0WatW!1`MoE<~mocEn?%#I4
zO^fO15gx}j^9Q?f#N#k)cXlEtXXBvF+We?($rc}P%u=M4en2bdC1o`E!DZFROpL|*
zZEFt3ef;xG4?oU$yH*Df^d>V|4U~SWI6M8?ID-25*Dx&pp=_q*L+U*{SEM|C@=tFy
zCUO~hyxsoFr=j@cz09<1_-sLD>NURALS*CNUZRx`w+w0?3wN&XhbgjSa8$UF5s6)q
zUHT9IwfhJErEmu3budE(j=CzJkt24sFn}H4DCWAK%bZpc?cd<ymhx+|em*ksPZalE
zHxGZ{cr5>XnSZ7O>fw#VKy8ox)&w~>sC+gvac6Xm3(k|8%MBg78jTh#B*HMkiBW&$
zhgbNZ@Dk`jXavUKlhZSQ+Gy}FciX@6(~s{fi|GE{$AkeQAjlF&ALPj>5b%r(GkUTu
zKEqJlH#A)F>s-l?gk6#f{3UkrukIeABP;ojS^K}SGWmk_V*cep?h7IL_>1NJ`InUW
z|6^Y-9v~!m_(j!%LryT#8Nw8ZM<JoF)_Z~DG&vF?l7gGle34r=y5+G(jgM0E%sg&-
z=)MRrUwqnq;Z_xlf80#NIGg{oe<qfKPvs`u1s#8Z$`<B-YN8YFtAK5xg_TEhe~HIL
ziT;|e?N9&AOX2-AW-vIlm1N0oDQ%Y;(+3;B`P$6E#(4%+zveY+^tcvxd57wu_m;Xi
zxl4_-U!+ofyz$)AdUl4y>ObQn`Ki|$lYi&+Z#O0>uXz8WBkq_6$zJj<_cArO-~7n(
zL$aFo+pi|~Z#8I~eCe;Ji|(BMirSxW$`w@oX>$$jT2Kaw5ZP%7h~96%rle%k8p1#?
zLMCEeLntttfBr*6PG@$0_VRc`j4=B{MocA=kE#65kBrEY`~-80Z+!TJ@67zLPA;Uk
z)wu1?$3yl;<JZ64X!-W*9qk7@8a;O}+zdOzmpwXtgT1O+qbks!Y^CG3`ty^&Yd$%1
z@b#I;YQIJQ=gS<Z{R{tZu6?W_m%dKjYm9N<+IRh}-fDYMNU%f6<S&@V8$-7~reQ)z
zxY<$c>~$3MZ>i{2qb@$Y@>_kpnP-Aoj<IkrzoO8@wWTm#@OSyg3Ny;jm*(w+wSmn~
z#c|9K#6W%3>)iBI_P~OtS{e9`zgk!@lQ|pX4C7M3mFN~H2o_b8D$Sq44K<RQ2a)Pi
zXLMhsa4HIW^Y-H_Gb<b^H>Uc>jr*;Rd|-0%tmSK7C+&9L+6>RleD+s(of8SiaM*c2
z42vyZe8($$4E0B6!+&kcaSWZMe0+jXptNPZAm7n-fd<m9?|Se1XT3OF^XcV(JltiJ
zn#`er6VMs+0W^nq`YB#;p$DbkZCD>wPmM*3^JbwClnr-{OArAGs94XMDqgA_PZM)r
zsiDNqs&lriOUVa%UTdDsrQ9*|hw`3LY#<0v&<d-#|K6~5BYe;I=h{3g9L-N~(-!!e
z&z$z7a7{fCGQOYs%p_-bnc>1--C_eC+hT=NLMFXJ^}5<rORB6!_`a#kMs$o9TqMb<
zid=%7koEATlt^aplA5=yqcCqd`OuWrBrKJMWHNpKly5YNmT6I43NM7>I3ac~f9du&
z3d7+^;*2<+fce7Kc{>?~;Z3jG`x!*!;688IQ+vib4oah~7cG>dwnACf9#~$Lk{2;S
z09f@(-K46})Tw^K99PdSRkrN9t!N}5ecteqOlgN=PP|k-o9ezY3F}K&RqrizBhsb$
zq!j#|8L}`Iae(C6TVikbhO~83{-V*m7%@W*XInQ41FPYbDZw+5LO8r-=WN_DahH=F
zR43=TTpN9BwAp%rWe#k5OW|A`beoh9Ky#jD@*O|V24{-zse8(nRpGu$!~WdDndEu<
zBAlBXx2J83Yzj2UyN{5Yr*Er`wAkNNZ&vLwJ7r51F1={Z=)x(Xc}E<+^c!Nm88i<=
zkCy)R&|i?l8oJE2u<36GOM0B8BD@pm&b&RGJ$!-T!hK%n55jQISl7#Md7Iw)Xxh3r
z6d4%~yZxrQU(iDR2|g9K2oq1h9(Z0ym(*&yAIH1D(z~8=c%(_E4DymLCHVg%7j2L1
z5%R+Ii2F)YZLl{ZdS3N$h~fSug8HPerMHshWIWl=Vud!*>8~4JbA;Q^4TlQ7+vOwO
zT?Ww&h6`Qy5yU*)5eds2z8jAQ9Q?_}bY~AN_`}HAQ>|kRH5_XCO^RyKpRhI+K?m1c
zku~||gdAm2{nzPg-LHDzHtTBBH2J=)0)NRYTdgZxiA7=os07<Jl#ZweMh&rFMithT
zeGu7&h0?N}H(?>MC<P*s$&9>4b_PLZk$Od)S_LnKfc4&JVQ#YQq^qSd8nkPMaf0?a
zuj`ukKIM;r%dI`i(B%Eqa6F8}3}(a}z!AAChoAFq3Fswp=ABfzmnwQmv!qg44_cq4
zov`lC3aJ`O`yjFpQQxoo?_2$hziH;9<d!*RlALIoMgF#>Z#WZlmBH0fM(pur4u-0$
z^{^c8QJ$z6zj-u^@~yo6r)xp1+~nw}I%H~ZjgEy^!}V~f5G)#JT_*Ba5Cj$~2f(Rd
z>^z(OF8nM*OLR*gv&U_v@|@jBCgtAH%r>kk6hWO&DS`~~ZGRL-<Mz2G!=$$KkxfeG
z6q^7Ej^y933dzhN`21E~%GB0WBoz+t@RH`5Ql1Ti5jTSNN*wPFv-`YVt-Jgu5M=Z~
zDJEW`yO<&Th}VWTV)3wjPz~8IP7DKwq+s*L405eTY;s*4sP4DVj5BO+Od*13`1eqJ
z(17Bw8i@k5K=)r%eaYl%a>kzF@}#fQA1uK=*}Mq^X#3{h7t-Ofg!X=RkHWze+p?<d
z!$QGxD};Em%PU??%o`L%`QG=}db?Yn@^^>d^*-luwhh0^i2pI|ZkrcV!m9Btj_XBH
zNJA}>AyqSMhSiigrlL)~Y?Epwp1}{~MMMxJtoEjQpv-YISixZSZyA%Hsvb*@8-_9>
zLLe5200`Z`@DtE|!s}|%=u!7CgbJ(Hx*E3L4|N;=mqERufH?h*9i_R&+v~M1g<=3#
z!(ykpLy@v|jHPh-9`)lY5}6X4fB?W5*xr-Ffzwo|Ue#BU!S%|0t)dSq^WwfWwk_gX
zM~DbYUDY>KU(~;*G2cydu43QSTai6y&Y2}+sxZRc8>;{3vyN(vxATS`2unm=ZdgzG
zomgV`=$8EX;8<|fi#e>H@)s%H6JG26QH(`r>hsB6ev#k<0~l(B&lhzR+M!umP1VY3
z+8ZDz>GZSps+~0tw6(|K=&@v0S1L#>00RtUb=W?1_UF`oWx^wCsS-WVvvw=FXufRw
zY>N|I=>5iLh&wWz-yvQS9$(@#CA72Hm6o6M4>KslhM;7(0yZ(=GD$Ky!3ITa<-}>U
zZWHrO#4=l6Ef98yNx)!>fIzZ1$pJKR1g*q?p>xCf@VfR-sWX)`deL!E)LmqW;R3WF
zYATzmB9>bBj_D!9<E12MKY(b*a$m07erk}5TP`cLGDft7mBpArN}1|o=@UCH5~=3W
znakd>;BeOOxH`JdAle>Ag~B&Jr5+DiX0dZD{M?upk;`ZJ1HBN;8-(!HeOQhWy`|0(
zgJ5$<(tBn}EmcpY`1O&>a#B`_)5r{#gaxuK18YVdX<)9C;fg6;u_cY48<%_H+PN&#
zo!}xTyqoZtQ<ge;W0hiJF}fDQxhMT&T0N9}1avlz1Ew@S^uo?{F?FMK6nNrE?|8o+
zVoOA<xsCV;#2RsSg2gk0jvT*K<Iw^2>YABKX416uZe`vkfj#AR+!+x^vAi@)*0`J!
zm5gY%s8UUa%)(RiNnt5DrNWrdO!hu=^<^RbW(bc5asgv*(S=Z4J>j4CMeV`97O3FP
zhrN3-h&F^vpxupBLpbL%9|}W}0<%ySu_y`E;<dyA3eBW~s3X37RfSKRc*@QM<JQD8
z%VH|wGg~f^i0Ww)6tW$|>G3p5qY?Fiy|1FaXt9hiy@-DwGLu3FP8y>BFL@uQ$C2}$
zOCjb!wPm9_2&!rOP;0bG1j&|e1*Jv}<foPC+(XyGYaX=k>5V?5F@R4|O?_oEF2iTk
z$_a|)o|hmPa#C#Aup;uW9MiL@IaN7qw`_g}aT4R`!Vf3>vM1Gg6{-jC>5X()4@c3P
zR)>ohlOa0^9Xp1!`;W3PIeQ~)L$1$b?-+0rpD`B~6&w?nkw;}oQFhk|CT{XNxx3z7
zZ>@KjWBK@MyHyz2aYkYSoL`346@~FyOP{@E^xy|*R#V-A*tA+YXP0cV64+&yMvN-k
zoWT$0ZkTFaZz2>+X*pGkX@u{t61)L~il8~$`I-NLJL3*9T~yCknSA8%G@7}KyG&O(
zp7dFN25;CxlCm6J4{BkJs&FUQTnP7gt?DgeY_DZ5E-mY2&85hJc!(Vu5Qj_rdcnY0
zT*M2edVn0HS$$xWN~vkbtxfW<BfsMdMekIxux_>_3KS3eAVopfqS<t_!beIKdpt>+
zdYm;P7qTha|KMvvJwt@U*bZWlfOFKc*xlifcO!*lO^7oWAN5M(yv_~Eclpr;$p`(A
zq)`sT!Um4(lQ2!hf`!5r`4oPzj_$3RUXG={sKk>GS@mT#VjghKEjxuFkl@;h2GWe-
z==Tw4A)7#aB;xNg2uSi`Wj@lCk`YJF?ZtY0=j0<u$DD+9H$yp&RSZMUYujpD4c-3b
zF*C%b_Ig0`y|=r*G>V8E3hSUzPz=o{OA?}#<T|H;?DtBY;8N+Q2h<h)>^pkO9#v|l
zLR`0D&=6UjGvQ+4iW4f;MKgWm9Xo5uges+tM3>4qDDq*rMfCYC!Dq0+xC6qS1!>R>
zg2%&d1Lqcvh>l#DffdUE=52Q^6w}8w`=kLqJWK2CiMZ{nx?)%fWQqtonIHhI%PHSu
zio=;s!K_<pw5FqT8kIwSCUr%2fDI<PWMZIaO`TSHM6a7bY=k{f8CIAD$q%c2B<F<t
zm=%$P4;G;qQNXe-g}}yTk09RM3}I_&N$2IR!Yh2QU($3GwF7U^CuKfF2)sSLPe6A!
z(RR?a88^%8fd3NIVKF5-l1+Bb59&A4$e0ZzIvtMUW9e)(505u1TWUTPTY<DeMo;dN
z(i)2rZK&yiO<RAvGH++_)(y84u-Vc4opW3(XQXq~`)Q~-A9@4wu7$6LZ6t$yA&_#@
zk`;<O_Id3$z1=hu`+_Dcko)3K!iDlKzq9PFll+^@-7*O<#FbrD#6)U;v_I{A*W63i
zqx)6US9v~Je24uPOC-94N#^n!>4;i3G_)O8gH^hwj+ixb)RxBW^Y(c&<Q~AL0B!t)
zq$V+4qrre0!(;PGh+Hv<&gzSy67_NVKW~o(F+euQC*JhN2t2yzQlp>nGAUsf67+zG
z$ZZPd&Bf+IMn-Y&@rD`3g*{MdA3IK1T%9bZQ))_=(#r9qv`Q8UEo@C5<4shg2GCHt
z0(I2XA5{GZysGcInNJq4n_$C03wO<Y?ceduF*-~Ab&nEk9Is%O!^>0%*b9r&Ukr9%
z3#d8o8Qq=h_J4ryAnb1qKlDZgb&y!Dt+rY6#c+QNH6Yv6xlpN<x_)%vO;y~Vj@aCg
zUVLEeV$eQjA7@qgC*iOdx8eY)VM^G{n=6S%-Z9lTqgf^EI!0bqI%n=1Fa$K;nda?J
z{R(6g?{{r_b+r*H28i!SaE8tL-pSPho{=m(KhZcFj1z;Rgck@wy**=lM!Q>=MlXPS
z?DY=Nz>W}0R6*X28j46se%yn>SP}l(OUb3=v>n#dFWBUsC276loTLl=P(lek$x)7*
z!u=Gpj5Tjox9t7Myjb0;E+?m=zRHj(oMV-uxmeN6_LtsxNI1k2SO`$lYAz7#tcMs7
zT(P%<Ou)*PphB`DS(c{;E{}qjeZ{*l+78!G`x9C5?L-)EyCK}MrAG|&8b0t|v?;-8
z)U4Du(j={vPE`^zS-2uL9Qo)W1Rbbvn6&?+R3%MSjr#QD{U|*{h%r5>gZqYs^2Mc@
z|6@}~#*>gW5z_^V$}rtlD!Nz@bF^b=ktUxJmaEhf+HfDdm4!H)jSY&WlVAcO$|9V3
zvGSNMeh(O)obt-owWz3u_2jZ$wszcp*^bzX+X~qWDb+%#Pwa+K6I{dgY1|)K_jpx8
zxL_TpN+2LQa=R=MK8K<#z|$-k9QN*lV0WAZtXPZ$z(NL*GOq(B6jH(7(LKF;#)7sB
z;o~lM)uZU1>=vGG2hxy0h*-0p8#Ehg5Dc`bHdJY=vJ{m84hyG9tkG*?3%3Kv1J*^W
zl{celHB_z6t7A!DWpUhql@5^^$%cu{f9Y@k4d>`^%w0z8)oMuC=A(Q7Vev7txk>Z!
zX2Cl@=FRg>bWLE7eS(^Cwd7KJ)Gq&V-RdI-7H87JD%ml?gMg64MX#!UNsUJAhCXA$
z#RrL9SPWK;sHwAW^xmn=d$dD`VDGDDB)z2z=Zu8^^U*9|=y8duv7GF3Ci9W_KBTsD
z4TId3iy#S8HylRa!#~4-4A3Q8JQL?L?b*G8@HRaOH3!x(a>T`qo2(X`*@ju%k&lSu
z-?0D~IH=uEF1Ma;8uIWVC?2sv`zbR`lqI%aSWFb1Dc)ALsYzAR+`v7vrZb1<ljFAK
zoXMg1;;A#+-%uj7^f@+t16L&o@+9*dK(_}{)9GW}xsb=p*HKytiu=O7qr<oytjhXm
zZ|fbej*ep5K)AY%DoX?hMkf{slATZxtcSfq^M2J2jtsD&pN|$FMRpK2E)x%r`zWp`
zMW|%@m$7U_KV*Dcc1aO`ZrO_#ERv9k-H_nw>i;CTC_^4{W<qNnR2Byqw2cEJ^K^kz
z@?3f`;D2b)CeZZvj_zs|IUkKian!B#)c?X#;d?RkiVU+M4hn*8C?j)Yijk6feIuGO
zQ>v7pIvO#+?1^!LPLL&BokBH7v>@XM&b_1z?D9N06TT6|A2!HdAZ9=L_jhuST|Qh3
z=z~Bci@_JnNjM9!1ZwagE|KGf@ip%n_Sx$sSK2pv=o&AnfqL*>2aWw~A(AUI4?`CI
zBEhk`0lXpsuO!vDuxM46=E><7x6DNo;<X?dKkm}fraFZg)Ayogw4Q!sEUQ>j$pZ_B
zyOjijH#&88Qv7TG3%Zx_ya7M<2#0(C#EDXkXb<Cnfv_td1|S!po*i9xNMvcO+10vt
zG`fIrz+nkZ!8wlUN%slSBWQOG8B|J(p<siBC2Yj7nlY9nS?rU9A3MfW0^+8+VvaOk
zeOq0rR@3CDnkKVdw!tam)-OA8``=_S4<29SX0(LkrVzxl;oMvlOSM7dki)qllsIB{
zh$kikg}vS04<r}m+n&)U_zSv6ARXN-JX!AC!81jC5F(K^vBO2REztxvRfE9sABoOq
zlg;RUD%*W7`6w}jI1Y}-dOftr9CE;s$oAP+-?Y!(OI}^AOo@BkvK4C*?UYK=&aeNT
z$TFhgpmG8SKdf_>v)5%#26Nb95fYZt(#WomkvfFnpx=Ji&yJDuIrrG@m*;ks533yF
z4x=3aAZaqYzLFCdR)iGitBj#0(O|m;AKZ@*S#T0131TKAq0oTTBm`F;(Qg{nr=NTD
znQ?X8hKpM%>+Y?<Q;ATC@Aryfz7Pf^dw`jSES0Cd=Tn)en><1qPl))7mAT>x9@iG%
z1>{&8^#>MOcfWzqVwHbf%?PB=4V~kMZIB^I)r#SKg?o|G_0+zg<HL3yVE!30WXb5o
zzQHi!Hhz<!ZkUz4I$oK4r*g*h=a1WXp|H#)IQu+;nwi}%+9yfR9(5Y{mGf9HGlt4(
z#k2l~o&>ZO&y13k^1HnTQN$kEiZ$Y(J-vrsmjCYZ0A9w(nY>*_;3QNQ5EDEE;c&qX
zuO5PJVBH#4OF&V5*OD~r19r$Riaj&%0*4AUnI5Hb1DFg6KERiiPS$m*&X_Zmsmgg1
z_JMTpB`p5dce1cJE1^Vjpy`hZ&JtWDE!kx{#|lEYSZ18bb`TsM<we_Jco#r)wDSj}
z#7RFG9X;5-;Q0gKpyB3RIX<c)7X-mSxC2@XHPqaT;66j97ijq+36%-1tFb5yXRO{b
zXcO*In7txlQ0`KaY^W-^OR8qmN;;(n=hcgP*)%KTZo|dab$?&D{hnX;ih^8tU~z3(
z@hZE_myBdlawXEdGH3TWk}ne*ulZvGZ+SxK`>puHf%Q=3Y+IfLHt*s{u^L73z)Gjn
z(?>81!}^5QQ<cTd>ay94mQ4hi=qu}DQLIXZLx7-!oGMx}OQvf34CXMHuYfgULp}~K
zuKqn?F{zL|8}ZEH`8v@+b2hwNF3+P;Y?~;D7_Up7&&aw&pg%L(dW{fcee?}~FZo^y
zcF<Xll^A@q6+hwpHGdNgByJeN>JHvhO)b{0GMg;vcM{^vDLp+Iq#_tjG9)6RcZ{Ji
z>OhQOEUD|3u!K}ZB<Le!w6g^gmS(<l9Gfwby(*P83a*F<5k67m9yK4`#l5=-u4T(E
z#IsbUE_q~rOj=x%RAf(h@RA3d@0~6aPH8C4i)({*XbdKgus%m)fCTALMOTIBqtW29
zu4-$J+4wn4(8tA&(FA;i39F_c35gj|_oAd(0mfmYpQ}hrUpDw`=Lm)B7xznDP-Fts
zu*firgSLICPA>YhW=!J*$aeB2+sImgEo5Pz%*A!LzE3<?+)XKtf{U6dpDbyoQlhsz
z`@UnPS8_VSax}GRMsKG}RK|2+JPCWplP_cLM0IiD><T)#k{dQ!SJx{2*VB8TO2?9^
z^ciY`mBn`>OkIL8a+Wu<-T6BZO;;?BZmVsCJ!K;0ZUQ>6q8}S8z&PxHNVTL!lT6Tm
z*YmG=Z;gJJ**q$N2ls?{aF?KqOM$^+&$$$>QVP$qjZ~B857u)tYBd^Rw_miuY7%l<
ziQF2#6-jDUak^JG)>N`#3Xe{y>ZvF(^`IiVClMmM@vVRKD0FuDXG7vRbWeg`GPh2`
z$vs5%#GE`@%+`!lTTgSG&sewr$llSer|{PMJfQHU5V6OC6Uk{YpQ25&Jm--wDTOG%
zMC5ZMYS6uKpt4X1+V2~@MFJim*UQqxB9hPMRDq&|#ip!Ok|FiHK~t|M2r|+vH$(vm
z;)s9IK7rJVQlsRUMU0yt-HF$=Uoe6!Ot4*t=ZHJWnYt11;nA+Q!n32-Mt{cZBB~49
z?zmz@;Yq(0nG=eI8!iIIwPLm;#8=bPPa9R7DcfU}r~Gra!AU+5f+jf@Zf{$eVIx5i
zc6g99Z&(kRC;{`1h7z&Igw(QInQz>KTy_nFvvW061fD?2H^aSJ?J_(P<(Ie~oPR-T
zeu1}g&AULn(fX<I(1p=%Z#8TKtD9@Hvaiy>2^U0(*xcekst|z}$n(^2HLkp<Tw0v!
zQjXP32&u04&Re=4eNR`hYRJnyvst}QAW^MU!l#x^;%tv>86(7h3pyuUOH0vf^}%G%
zhnNO6_eBkZxFZ64LI$L2aTxa20V<vtMO>cn+G8gK@twKV0xnL1r@Z@wxQZS!CDprX
zs4}igoUWeT#M-=A*{aU#%4xhf-a?*_%_FI**K=k%9ROq2A4Fs+lS}#@QT*ZqYp3*)
zolBj$+5Ycn7R=msCU{IT{WhXa!I5`Sac`RoVzEvrBXRncJsUj0*@4g#?d=_H6LY3o
zX^fy(fFKCr;UgzG>s{ns43AJGF&11NP#cEm_ya|LIugyN@sLys=mV${t@jCI#7?0}
zqyU8XD~}#o(`0(n>ZqDE6?>FlapnjzDP9*Yf9V&07`h!8gavjsSb_}IiU!WlJ+4I<
z*=HVa58n*vKY!e7r3T5htD}@5x-kzEbdrn~CJl;{2Wj5%9%2{ZV2-%vc#4H8r=_jx
z5*~y`q9nK_iiVJhKynek2X)d^AHe1%upjkoSuHLl=U8_Yd|YnqaE$G9U*-cRyy9NU
z<#n-Os*SD2oCSeIUt9^#Ai4cwa5&6vd*SY}a17pF=9|1MvtBpxD<l@;Ab7S@2zHs%
zXVP>!BIExcx}_#hRbDWqGV4aVx!;5+j8NGxl{0-sv!;rQKB^?hG|WL)T^RD;zRq>Q
zZB#^{HHPU>Ea|qS=yGyS34bzf*#K-XisKc7fJ)hiqobXvG&gjS%y}or!zm-7Da(*e
zcbY&QiRP9!lR>l_`l_i`)ELXu?W)fwX9(uUt=u@zisZ2AORE1}HO{$bQht{NMG=%$
zh%=sBwrS;I=qaq<{=2^?6id|$rFNCZVt~z!E~^`bwyfA7;c7m<Ej>9T9@jjdf`@v;
z-_zRpMk@f36Pe99^9hkVNmF2~M1ArC$DU2KWY8@L5ERplRNmHQvODmIr>@hZQs7$G
z<gilDVU{yT8qr!ZJ#b4;QYO}@*Wj`}XR!^HDPe|-s&8LJS|_p*u^8k6T+RV*!*6<^
z3aw)Wi8#eQLBvae=1d1*G~Sfa^y15E><Oj=fwR<bVW7_D;-F#L4#|$*VsY3+sUD=L
zMbLFToifiY=`xKgvlYT%gcW``ffbzdDv=GXE)@YVmQACaQ1+iUi_2y_nGvUessj*j
zfS^ox%r_DoDqf>Nah96awQ!@Lob<CQxo-=F13AF2i^PtS3|9HjWmViqMo0ccAlWoa
zgzdtFJSZnS;-o^{f(oaBej2ybaAcoLtFuxbdTw4nZxCMV90(CbPAUz9tEQ)^Z<+T9
z=x>1rJf9SZI+M5Ud@2Gg3w!C0gj~V12_0h^fQTXqAq9By+VWEd&hBv6=G*6O2OY!v
z!UK2x?|L~JoW>3ji%A<AyRpl(fj&!)0T=j;Gf6^-q!}UYg2e%SMGZv>JuT^cMITF&
zR3`@>ioED%&l)jgJvWW>1)xar&%>2%ogOnIv;#bMuR@FAIcOH%!RPPrYA)m$T!fM+
z<A@pl#-W**-fpuB9c(k(O%f2;@nAAb$>Vab+D*#{HH3kzgh3mW`|g?4NKXpaif0jf
zyW$)`L3+wk)r&l<`zndHsvlK}3DsgbTD(t)B|wH;%<`}jnL&Le($SWlubjZxp0~*|
z&&?AKa?#Z%K4x*3<eKDjI5f6+xIi%q@8HtSc;;F_t{>AT#F?!=PzsoPYv+d7`CUR}
zK$TEG>9;upCY3rN6m3&vYy_~xevvDRR!!*?#jNOgGW)`2DvuYrdFU8=s5|Yq18b2K
z^unX+jCtmwu_X3j-m=TW*6n}x8OK(E{fJNmkmT)LD1A;?R<@I4T9i!!0Wnmwad?e!
zE{+Cl^)HVedTTW6x7H*!+#ANNz?-7%>;&itcg4G^VtUC=fUickEB7l2TGrIIte=yJ
zRdyCi3D)RnaZ$OXr6c(3x6@Om*o(f+BO3)?2qSSQH_Xgllwx9yq|3h<0$ETlknk45
z?}r3da!W)&HrA!egpWNnSW7`;ColH8ZhFWKvF30g!rZ|xViqwGa(5|v)!$Bo`W1WC
ztfy5oYtm$vdrsc7`O~7A5;?o@Jp;k_bVZVAP?l65PvRHVsVW^7W)t`!VI37M)ijA=
zXyfnW?tz42Pz<;#<s_2jHdeBv@7OUdApoQcOXT|23*iJnkF1T8cx3@3e(X(Qt_0C+
z1s=)iDO@2hh7&Jgg_oQyCSjjEr3&R}%4UwDKU^-+<4O)F5Ubaxk5D4#%B6G+h{BvP
zFC_+nND>|{5nLwo<bY7yCAziJ1X~2Mqzy}OGx|M#jBX&uWtfaC$EC()Z{>m@*cZej
zcJtD2!d>#Fu4Y-4MJ2f-pCB|9>mV}G(`YnlS0iatMmI>^NuAMK;g(1_;ZIH{lpNK-
z6<fTjX>dAjs4Ua!x%jZ_S3rNjN}GjHX*q5c3JDZAe?TPIJsd%H+~i7;_SyJu?BzLl
zfh&o;h{!oMtn;piH38`q?VR%4M1CHIlF-c~oD3tDQDMVS*J!3=n!aL<QCKqgIC_yF
zUKFV(huJF*;##(pr9jhESjS^z8@hyxrp`ZZCZ$lo{UQ7xh!}e{WopC&oN^%6c+*SG
zQLzwidtsM7d^Wfq)UrL-yr+Cl96s1(Y74DJQX$Gpqv4mz<&sk(i3y+<9*f?ia>er)
zV4kS@$I=l~F<(|+PNYl_AGH(YG-4@*3X*tYO^%IyGvUJCd%Vc1TBz89&@0KXbFpmN
z_E##x2$Z}Sfh2&g5=g*8fg<jiG9D;T=mxzQx5Lgl)WS8@v74aCtBGCX%GI#Doch?Y
zhbn<W%f2JMlJ;cM%n?LTO&P+7blEJC(txB#w-Q;KXawuZP{7Mi9{~)0ppq$b1LV3Y
zwon%y-jiL}{@Z^fqAON`P9<QdxJL9qoXc^$VPGR+63sI$R6nzarE8iFP5NKGnCSe#
zs0TQFZPZEofcdJ{CXc#{{)kzHSd4#0-Bw%tLdodk8EjV8h+y=lzNhEy)#Rcvl2>u1
zFiYx<eY(($HWg8?R*el>I*ys+G$TJVF5Mv5brItyq+yUikt9uFb%7e%?)rw`b0=vK
z6I4suuufomMS^!z_vGvy!ZRZH&R_T1M(OfKe9Cj(WwDDWk~3%`nT`&LWQI`t!7FIq
zJKAnX3C3Yj+PwQTinQajq$Ecu52e+ppAbFLZ`$X^D=((27RdPBXe+|$XfA#j2Y3HK
zK-HKEr)!$H>vJOaQb^DieJ>ygX3r*w6CvFvOb5{pP`kaO1U}haUdI?)L+u~qa=)Mv
zA8DF^)eb?B0Ae5~0mRcqbwnS~Pbcrt)Os#CXDE8&W#NZxh65T{SpOB>ALRB|hZNHl
zeKuU6ykUc7!!40?xpMn6Ul0a&*3Bp!78@)<gqO8nEPRo`L2RCsH3-mFLPp9@!%Vun
zCG_k%i#(L2FT7bUxBWQsnGu&ELM*txgF8@rJ$Q>em-C6~RMe%aO5Uw(Mav0|ye21F
zB$s0#B-30XxtLe`VWq&Y{QQhS56kABUbgSBAC6$I-u~vF><BV=16Zo^CbFIWWkv9H
zEc~Lz$qIj=U@{yHdT?h{@OF6zBgA-5ui87x$u~-UVY4KqIWEKQxV(uQ3*uPh(Gs=O
zWlZ_CFN)f?tU6#1&kM@lXVH8~#>7N`l;>Im9RV-Xi8`RB>`?W1GDSf#dD9-LR3?Q8
zBB{(v-xrgXrDIgoUBCvKlR}IIz91fl448nGVDqqSE%=OJAMl=(paDucCojm6Sv1Ll
z>l99w(0ZhT>oLYq(L;hx;GWX97Hwc6pqX;eY=U%6Ypum8^9eB$8Sr=tG2=!c)%Pk@
zJCZ&~l9<}=J!>V5V`ZWjnO{4I>zK&4u9C)yttj61=vkxp{ignLHEVLQ<$ji3Zrltw
z_6#@``K6q=hjwHy1d<dGbCdoEd^QTlZCzP_I}g;+BQiNW!G?JOnxiB2v4|N3v+%s_
zvkU#s2?!0+jVEwQbwiPiq`H?5uqiuCJh>Qb;xDK|qZK<AGn4uKUqv8ph}v{XO_>c3
zpq%N0F!kr3EDs3CC@8eZ+c>#r4~kaoT!YCJKY6o6w>JjD<Lb>Ddap)7C4k`evV&M5
z0iSRP2{?nI^??FX)K?XJX++aCN<e<mPA6^?p+i=gqaf$!=w69Vu_GKhR(()qMuebv
z%UY^)q9YbtnEB2rYWOr^5+gF-0drb&q(Inbi8;l|z-OT&KQm_mQad`N?iCJ<jnZoB
zandap%U}k@t~r>^wulr#Ivb9~;&+ZHbNa}e$^bS+lUR%UHW{4PGrA#EI585z?;%5C
zIZ@smspx0#sg(A-k96|ft%T^}0mz_5^4*3)^k+w<qPR13<Ij2Iz`|&bnC9S_2>!d^
zQD7&Y0NqD9^6nBm#?L`C2_0Y>B_zMwtDBmvCN-WDQ<18NIU5|u*hNjc!UjbZ3*;R~
zqaibumQu|cjI?}7YaHZ=Rip{Q?M||xbo6sN+QcL$rz*#if)agoy}IA|0>~;8V>BL|
z4a53s$YH+<l6!JIRCZbn*MlIKihHum4l=TW-GJ8cXS_pRjn-mMb(eEu6d_aQwRTJ>
zX&S;Iv5f==V2>Mk;OCe%o<0)H6Dpw7(mIV0ahid@YLNOtTx3Fzw=U(MBTu5jZ60@f
zAyj0xd;cZu4Z1+jBwUk{u@|(_zy??%toA?Q?5u2bY*+4BdX>nX+t2PK%iXQ(Nb`W8
zsvdgSECarj7yyy0CD?Nj8OpV?W8&EJD#f5?WlRs^M381F$0*TU7Y)%)DCop#x_#&b
zV;hK`(ZoJg%`brVH#8Tz(45HaxU(B{yi>uT6)h*@AVU4b_vY8sq?mh&A8r1qHydYr
zvfao6Z>K&4a_lJ_3o}KecYF2Bsz(1XMZ#xdC*<>z!Ug9F<ZRM_5QbC9m(xY&WJuu_
z%jsmE4P=+aCifuo>-1A4xo6iRV&ln=qAG2~l|V4UplO#;JA@5Y$$aVe`GnLy$v`<8
zjzgS#V6GVGJ16})woI5sjMKP)Ncg*JE?yH6uD$P#db_FGG+nY^27IBZpKt;Gipsi>
z4Cpb}qt|rLnzr%e0}x(m&ZS=vE1MU2aQ<c}6@Z-;DH~T31`rrl!0}+C5n7S4Oy;+@
zxby_F2QW&Ez&AR5#C0(0NGpHaxOQO&7lTRA{B<p$MqV2gG-cF#VssCN?Hcb$C6K!e
zG~ZQjV^QJ~$ScJ8IsJjZY^|Z2a@8DJGtoV|L1)HkO`_PwTS@UZ0&7BtY{N@LcxFf)
z*)YA=mDS_wdE5KI5@9eKhaVBsDYBN?{=VSXJcM2phv<&t)4~lDOEQWthOMcQx&VTY
zD0h&AkdfZRI_zqttfcl3eEMBfy099=r)|qLyP+!VheUCNLwt9Ej!ZG7ls+kDfM=(A
zGx5i$FoOo4(G@nD`|~j<K>@MFt10aY5_LAsMIA@w$~1F1c%VtPMRLKfe+_3XREs~@
z>18FB6a(k5>61?y2^Zw?$UQm8-B{Rtm)=HRE%UzjU7(eLm-#1zJHUD{Jpph8&Po)A
zDHp?BC+O@UlRp4_7WS@zq>k(7h>PYc35nEkOoo^vS>6inl1rsEj{|WYj*F$kc13VZ
zTDY5)ipw2E^uP6@Ou5yRWY4q+c2bn{vy7(<hw^0ph`k~Okr6jy&h~5cYe(0-A9!B-
zhX9ESbQjYg635pI%7{V}qKW|!2}Du{>cP5swehA^FX+Rol_B$@-m2mk&Qvf5++VyI
z%oBXRzNzX61zkdxGSL#V2#=0fq`ERvv4%Ds*$%;-ul^e;F}KNNtVBjZTUODx7DVw^
zbs>j70|lW=r{fu{+iqTC@3r3ac2ne{0m$p3=WZg7zc)XoqdeDwW$(Zs;`MSpCKV-u
zVIY*rh<#Ae)I0h>OIFQ79~8)Fx@6OrxR}0*2(NMEUbJRss<wE{mZVf$2z&w<$%!zw
zne7YzrxS`jD#PsPdRSL=>E!{fh%X|~s1p)4k&inLdxUQtbdGlWb?VAvoj5x61b(Dj
z0%d%9+x$Fn3#`Rh5T&}m5Oj)t!?p@!BE8VfhzgR5r)P}@RGm-4P-F-NhsUm1D@Yqj
z;qi1tNB5Fb_PMbtM;6QkR&h@_A~gTuFFKk59t4&If0dzA`HP~TUj}Rh5_E8Co{0(G
zUWkEP>vc_bt$X+}fM(aaM-omb6`PCFVj=+-IxAF5U<<eczxgw)s_IID8=QGlSyd7z
zGALOQhGu82J5CxuqKA!Yp)cMR-mPvW7n6l&Y@M6BC<mH<`=1NVJE4Wtlh1~+C){48
z-mz5pMH&hu?8SgdSFtn}Gb<Kfpzg(Fp2vYUKH(4{1%O34!f55uf1K~mChnwhJxe$~
zHl5y|50q(ElLtD|m4wD^Js%aIgb%nqmynMNl5|$pBi&xVr{AF}eM*a!j`GjJ17Id>
z#!GL|1)Vu9BJ5^+RfHDJd7boKoOGr~{O-<{^Kxg8e(hFV^c$Z#NN^Ff%gKM<oSnmJ
zB52M`NVq}<M_jQV#qZTu%t|xK_lwn{o0yS0&`ek+Jiw%2)<lfK+&)S<qEgG!=$Ec6
zYiq8Xt#n>326c(`cA}Nc?a3^5f~bvG*5yd51tJ=tYD-G;RV_OaI}EnOOex(coNCt%
z!2{PuuZ3Rif~Tn4g1b%pYdYhXG<W5CemSKUpN1ey29+wxoAtHycx7N!r;~b~21|(|
zwOH>R^%uXR3mX!crcc{wt3sy@Js<(uUa~}z!A(W;GUp`LWIRf+L2NP)kFq#yuXR1#
zwCf?w2JEhIf(T!@LgoUfyi4-ayMBltB$_77Q{|F!2);AhT(={@VzHQjT}AUGwxJgr
z1U6zW-IOt~5AO{fm~E+&t*onHlNw$>mc$-jr5OeE7o+X+Y0-%7?~jN8lkN-dkUNi)
z6Or^uLvhySACoB>iRUqICAzh5@yf#+9<klP8)^VoM}KbEH426?2U^GYT|tXkv&awp
zz=lgykJ4d%OyYpFTU6}SsvfRRrGpk1QpE?i%QN_eIhMR-MFgJA)|Kf1KTm1hr?Ekf
zZO*v;+NYqI&WM0lB{KdeO>3TLb?HtCgxdwLrTpReBH9-CC%h-Z;n73uAumnaCDXpt
zA|+-E#X3n(5WZ3NO%OCC8Hlc1vq2U#Qd!dC27pXXB~v!Wk3xd@+#S}gnH#C<pI6f-
z0D<hZtrU!T^r5SzaPS8d4#+uZtCRL|ndb;(vWK3^HctO7C<RvqX**%h6RtfT^kiGJ
zGPV5`H0~|0jvUB9#Z7H3b__>Mp-ilkSg{@$%CClCS9Hrk<E#;597%EUd6U#Ngd*eY
znkc6Hk~-OPT8|o4JF{x1NHj{THWbu|-Nkpqi%jOven%R#oi(FsfF14xKZ`)CWrnpp
z-)TgDTudIv9g~0+A(;1i*!0%D+F3f8F8fyr_kzw1%`A#9LWt?(_7aKh2ttl_Bnv6b
z`<YF(uJ1?D;yL>PrI#eQC6-zw0UDS9p%Zot^7fmjO))M`ncgk>IL_$8Dw+RIl1^*H
z|1KF)R%%$C07A4J7>|4|im!!Z1%|k}ozq|82C1Ewzd_(Y?-WN4kJ0oj0X;9ioLMhy
zmdsAZ!3N83OoI@NJsrl~5`fX>iUroRX_Oe40Wk*ETn8g8h^0a<P<}oliS$5yOsVOe
zPR$X$mDV>SMs#gzC&&UB199#S)?{WkrE!Ka*P;q|;VJYN+s=m8j%%knBAhWLrO9m1
z&2V@94RxqquZ2YN?8Qbnv0NbLL~Ak#u#oJMe!%vtiuiY(xRM|&8KLI!<@Bjd1Jr)p
z8m0nKd_IH-=dgUzLe+mUr6`&b`P^4}Hd&7XKdn4RABbt{yhJom`rf3-MG?_0if7JA
z{*NLt55qL0Ys*3@aLH4Qt4(GJ);gH#9}QQ%1LPiVntN|J-{w}%)e;Mf9}>Al-zJ)h
zYN#2kzgd0ycJg!5iWpCUU!~%^#Tm0k$EQIn*viu{m=WE6U+bBrO2tkw;zLQ#%t-j<
z0{%bxJ{Pa7x&~1yu^@!hn%fYF)SUbcz&4SHyhOHF15ek&YhKgKVWuySJu$i)C1vW8
zT$|xmv%xm(xGbnZLnK5&^CTGVe-x0gn#vxlv^bQWsrFT<eQ(+;h%gc?@*wU4Kc_aN
zUf@u-=mTvZWh8xrMyqkNIA(?*pJzCGwf(_0=*FN4az;8K=Q@F>4G_&l_sW~rcUt5I
z8Scd~q|l(&^f@7hjI>n+bW4!Cw#|DpKF^jgNjN8)E!Jwy9c{2=_?2QXBwHh7v-bgy
zMKs?513YdjxO_e%h?=-^QV(O0__x&<$@O$}#X>a%AGJwE1YS~)%pd%ygc7a=u#-7r
zkN0IsD6}`6GIJ492``9cAfi1_LK@$t^I3cwbN&8VqU0w4wKhUzpmi*K(o7jl96_lh
z(mP29Z}B73?8i`;sF~<7J*o4U+QZAHg2LfmoFG#yM^*PL_C(IrsB(aQa(J_HPm{y)
z3fdu)ly|}uR<^zHe~Wn3&0U|W3uDBB9%C^u(DQZx8z9>!beHlS#~yZ>cXZqsJ-DZ}
z+keCFtj&2o(J7~(6u+n^`3!dh1QOlPvDpw3_P%WtrJ6`=hKh;CqH?-u81NCh#oZ@R
zRY{U^IGS-oba~wLrBmj4GgY-OCG!d8M`to20wvl0P)?Q-bdU<8YxF28Imdxn4Zy>4
zi7{7^P3{{rcEEuqhil|^yxY&~X#Lcv-+qnrOxkhK^xgbPAru|4E-Xj0omHlc*t3C5
z5=ltBR#u@MF=Zoi6Yel#$BBrwI4}K{w^9zONc-PSU)_w_8Sp7b%+IG9Mu-jC-uERT
z7c>PgGI2KaV(+q2t+{T~H1rPBR_123CvFA%WbTVZ=`Kz1-hn%eXG;e(1LmXe(_YSL
zA^3ITQGp6jDu@-C<I6EwN%Fj@@OhFnZK~90#w8vVd2rFQT$srKF&`(ww1Q6{1AKc&
zJfEGsXpiH}#qGOr;vX$>@r|%JA*W=}%TIk&YGTpJwn+x_$<;*AX70w<0tZ#xh1PbM
zyz}b~Z#O`FJFTT>38C!gTpK?k?EH=>qKI;iNm(VcKC8&bI`L0G&CZ2W>EbCRl8n-E
zoe;qZ6!Zb{d)e5FhH*#3Xa}0t7^gj3j0#}pr=^)yMgl$8?#$^F_*^NP>Mv?=LxOj{
zAosH8IJ^(Wx<-{9R`VV9W`m$@{$yJorV4|Fx!6Ud2s4jMYVrL#QehC;Q}l0Cw60*c
z#heHQndu|9Fv1u4BN$>rpV&Qni;3LEJ=>^A@F%L7$^7w);^2@4g+1xXk;<9Sj2Arj
zI5^M!Y=_9e$6~MxFa`Rq!Qexer60bP<FVtmyz^K)!~IY|>3bzd_iCSufP3*E^A<$n
zgv=_Ju~l5{7?sJu$lh_2jPcl#WmpQlDDl^XJ)$mf{Ihr9<%HA|WsZk=9{-L<$kR3#
z&!gTxrpSe8$7H_J?Y&4TlSkL!Aq0X|$>z7tc`eM5XJv<+a}jPr1v}5OIYL5Oy5v`s
zo5?|K#ITt|A>h0tLs)v=tT6SNv{T)nv+=s!!kJ7bSQxBwp7q?Wx!F}_#Iwb=8ZU1q
z)`?Hf)7FV_3Z5}f9J!BQJKVer;<p!KyM@wL=)5f0@Ch$yIVq-FHk{vl(!pt&^Gb4x
z0h7`uP9{MkiY}C^i{%tP?RaZw<j^&=DZ$<LUZ<pioF-2#C(Bj`_gtfh+*54q-Z!}z
zWm3{(+hec*G*`y+rIX7VehQa_{grqso(w}q1=^vNsRyR7--p_>qeNvSnR6wvR-D($
zH)jfo3F|p(G3s&EOM8?*k6bR&)B`h3-pLg9lCPDE__x7Ze50VaWjBrce<~RjKqx#Y
zj~6O`@L$Wdew=NK-9#|$^g)m*L8I`T8}h}9xTu9?(CkM_6ih%px-I+bYIZw;3_Ys3
zqMJXgqvmDPaw=I2PSN795Q@DQJI>b)!OFIcxoR$|Df^5Ym4c7SQzXfgJQStjY1_Zg
zE4g^PH_yxnCe29<qv1r`mW;c@3iMl^j)9qo1wZ$KXeT50CPa~CyC5AFJHaA~UQ;JP
zz@43xys8kD5kF0Ql`Mo3thkO!o(MACd&Qa~_q2d?P<qC`NCV6jd*q69wHRTNntzpb
zxwy2O!Hs~q7Gfs@t?^085Um)?+qRaCJ2>CAEqh}$kk}TnV=P?aKW+l~1dH5^0GrTK
zt(i-Ly~!~=V^n`nnT3S~(GG`YLD&jYTbV&BXr}*wDOBt;!BVo7N=0@Y)HLC-PU<q>
z_<7+nFh<Ol)|8=Xzb$J|%5J(16;MSE{o*i|jt<^?eA5fAdY8k~s7R}D($0Hs-zO|z
zNC^byNS+4BnFvky16K`IE!k>0eLf*6JQW@1a>r~Gov@#mC|#;Ny<ZojI@5z#n<2;}
zUpZj=v}}qS+u8oi+p@d2sUO^=`WS{%Her9~7<1kcD{d-bLXX$T;)uFdL212Kf@wJv
z?tPDT4J?g3R)$%)RNyTFHUfVr=pR!wNv~B2O`p?*9J+KM;gqz55JltyGNo*t12u1I
zU<-OgQidArl$r)O*UQ9reIkVpY~23bFqCo%;Tl;WL&G&de1Vi*3n_Viw*lD_&bt`7
zgR&X93N3oO*Tc&S6u*}jWv8tNX_J!k%l4=*NqYc*2L6;Vk0l7%k^$6JQ;`%B+ouf4
zY(%pO(~oJTQc5<pHNq4=BCrQ=_<*iR!+N;CGL`h1r^=>M+DNccF0w)^kkGFH(oWD+
zDCg72bWPbi%{!tTgdgrLaN?hK8ssn|^y#R#4@jfu!su>Z@$_Af1ijmPix33qp}r|M
zAk{dEph7fq;S8pO**J8uscbWPCw)P^peo1pv1qDVn5WGRqiD2P2<O$2@=GL=O0vgy
z6=wtJ#F*u1JUN~W2JP+bIgw6&v&QY{4@EfSTrr=yFNU;91zbLhpp<Uu2);?Qhj_$-
zCQ1t`Z(ODvOj3)9Uk%4P*YRZ}1{*}+GBgIk83dmIO5}MBuuD2aMhNYj`UAH01taHV
z4XfzU$$2W(V}^_b&xH_3SvZ%ukqX_{RlTY>nq%@^`w>R*l<vn;6p%p@cD8Z5D7njo
zV>RQ>q~FrR(6bqrOJ6d0Fd<-v>ch3myjncypn;iaKn^DGTc2ue0T2a~DV#)_g%ucI
zc7_M#p~6j?o;UPmfXSpI>RmzTQwgdIRUCd(iw-!V2@E6vzoeo~b<ylkdh1t+rR`zP
z*|UsFr=>E}(%c^#D%}1K%cJS#Y<QP49^DGmsZ5;R4k1cC=`$cG2A&uNmp~1^V<kQd
zuDHu*wryCXo6!}VRuG(sca?XU2yuqh+#S&t14ro;M&A~TOY@VG^AVJU`K4y{US%1~
zjy@BU?6?xd)?rT&-%qBfi%$<U*7W2>C9{%4=p;c*AGwS;2=2VyCn-UT>++S{HdJ**
zOFfC=t%9eJQrSV4_)@UU=JX&*MP4JQdY__b$lI2JUFOO17d49$&4S*%=ofkjy?EE?
zh<Z~G<X)&0XHwhCX%rNR0cb0eJJ!acipW1O*_s+$GqnA!Mf~;Y84$^Y23Ex^Q=$5>
zdX#zTR|Ev}+CrZMoZcH%mx+HjxVAU6bl_kIU@~CchaA8X@P1etd>LHnCc1jUI}qMw
zk|mPxA)qUQ2F{%cT-1PFls%LzO67)KfYqmutK%x#U|{!H+NT!VH_cW8?g2w2B$cEK
zgEM3pFuO<G3UrndU{7vFO(Lx`l|Fr@^30YQ7xp>v-#-3NL>q5|XaU%PdeCW40X0_~
zE_jlxqEi8m0%jA(fQ2n!pznKlYb-X>!5;uD8NuJs7)mUqh=_DMz(T&H?DUZ`(*uo1
zpB}DEnSpnB@IwE^q@S8I7YU=0XE7Z|*n$xVuAqwGPzmQQzDWFa#!gu?xojSFII`IH
z?O%2S4M62xSTAHFXyb^i3ryiq@D<w&ubp-u!{(7fw8gc%zPTJ0SMCEQf$9!(BB>mA
zDcqf4X%bF|3^^!FF-ebf?nfLrHzxf^>k;(O2AVU4bj4MBkR*)Ej&zWb?<YfODq^Cy
zN&oH{;69z~Bx4-NC!T|a!iqn8gGykgNLuSjV;N8$p@WM6JvN$H0WM<@4g-61-1f5G
zOX99OfhEs+a#~NDoMp&$q!U;giJ>TE1H`?DQz7CfuPtNa7Rymzr9z7Zv?jt|1Rux!
zF|`Z~)dd2>nvYPJ;2U=T#dJLyw*@I(PBw^LU7k%L@Peyc<~S8FHymb^oRB5%2I0PI
zl#gF_Y%WO;%wd|>FO2TvAkUXyZZcXj#<2lRwJ2JgDYa@j)I>Zu-<{A&yjFDCEhjgn
z`&H2%jgD!?A7_@6;DEK0B5ylf?vW<d{yeAjU^7zHXBgq*#0&BHA)Q<-(K)L>J}N1W
z2Ovt30r1ZEP{gh}F6L~=yxrp({SblUKZmpJ7lWRgm^HD_@|^)Kfc3g$wm>wk{&*qE
zbD;yd9RHl1Q$`@X>PD)}v$kTQ>qIbsq^eH~quD|ieC(j>m*DKC_{}Rx(nOjoGc>AF
zlx2>6hDN`N&>@39+h1QtCO9<>ScS-gcj8J_kj9eka<i-muSBQ$l{priMz_KAiI&>p
z@R8dbPKUj@Gbf4%dhjrXaM2gLjclmFWP@!!ZU(NW<LRv3Ozx+4aoN1f^cyvw5e+v4
zXh-lx1y^z$CTWf<(~r6yH!nn!8=Mq5Sh4+EiIj+h2-%X%H)?!ipiFv5<orr(vH@R)
zW;BcAj$N#jXP=>YDwg--?XJP$&fMwN17}0}*kO5wIi6#hJ$88y<U0+)vE`J))>^6M
zkk_PzRlRsFI#pe4_kYgxVw#2I9V5pgd)AU61;#E%b4HU=8*Z1Pcaq;}+Jn2lGzqCv
zRI5{ZXNs8I2Wt^{^W6f|fP>Nb!rrx1VqdzUcxf3gck6v3JoJV?5Kew57&MUkW^7!j
z>#Q3@z%q$OomQ#3=KKVXINCHEuoh7j-bi8uS;W#IP-Mp<>y!d}@Ybp~H}iqrBy6^Y
zdFmJoz|}i)!_5DWiwH9_CO(=setI|r2}Jp?riW4(Yvm7iyL1Hr+Ml5AC#_xaUH^?R
zaL4=7jlzjfvrvr>hFhX^q9A-u%v+{-J`In&N-{ER2J^=v;!0BjHh+g3I~*0>y6AaL
zDTa<V)j7bYbc80#VM<BdXmK9dI1kA?5(m2feZUVmj71|BWu2g5gmGX?XTxPVZwmb(
z5@Fjo%VHsB_)U^^j!+)k^C>yyWDh6mb;&80u)f%~TyVKFw-+<v6kAEftH(6eJza@j
zkR}mMA)GZ#EU090GX-T}Kz0Z$F)v029U-3MMdp;I0ZCUj)8@{l3-l)@*NvpvTqW$-
ze(S$MI96oPSPr&OQO&;qRC?Pkg;JW3{d1Pq#vIHZuBm+_?oauxms^ovSFNY<lbNub
z*jQ(0T}bC(Xz4Vhd8prCS8F=MfraKHYmb@1c@QQosT?~91*9_AHqI&!`>&X3ImZrX
zGsGDuhi}QSRBXkr;GYoWpL`Np1s)Zx+oN9M+{bKZ&ijI)ztGVtF`4^=zZ(uCPOIb1
zw(QAj*tMaV(UQ>%;1CyuNVMtLS`;6EC3rhMfDz{O7_$W^3I&8?FWP0ZWDW=)90ty3
zR<5VlWl)~(O0}MXh3Rce`|a~k{Guk(H<NiHEepB7$~%vMM?Iud#)3k+Cus|(Hprnc
z7eXRmemhV4c+id_iSTT4t~$k56BB%FG7nkyB(D(B5pO5#f&vmixD|$diZFT5%<HLC
zpRi|aZ^iOv4N*+Nc`|*98l|8(dZuaXW76Z5Jm7d8%aoREKhg-1ZLWu1DiBlw+0xZe
zI7S@7oWO%Z*e0R~Qw1F3L%cA_O_K~rk#Ie99rw~4D$Zsp{4|12e9LY*M}QJ3Vj3cZ
z>8HU(IncpuDnTTw1uDI!9WJ?i@}UoB4wjRJ`zc}1o7<dt#9-8^NKigORRp=%{+6IP
z0@>0_I~=|ga<&wR1Rd!pNAN|haIEZZ-Z6{!DC4s6V+@jU)<f#I-|?ur?G0x(=jwDn
zAb-v>iO}w#wqPgGhC(zs0sg3ZF$Ha+&Bix*ktn%JLQs{1@jc_JH&2K~7jdRf9>@jk
zC27VtBv=qU8SY^KNJTk}H-L~P7;AWpxD3XN2NsJ2s|Yr!t#L6k^a>|^HgqSaksd9F
z6&}Eqs0opCp3Q=tGNK0@PMriyd{xEIjH!hMNz$})9ym#;1m6ikfglvB(Dce;*^uT#
zs9VLq`+Hn*9tOGw84@7zVj`bj^e18AFilXB!?7qhgxCkN5Q*}rzI&OrJ5>I2txE-D
zf{kVsT*?OGhy)c8Tx?jKHsFdhG@VK;d6;GyayLhryrL!pcsn1J5_2kD2n$jskkw^=
z?=DyHN?+-fA7-Nno^rT)D$^YD`MDf0m`l-I7$7)qokIs06Op-dsY5ZNyQ@4^<|=jz
ztLd^zD8sxA<W7@PCRlz7x&qfAo=Lb6!r6yvozZ%F!Z5UJfqeK4h5TJ~gbhIQMt=?3
zP7ogXwKX=CfhD96&qQsgjbvxXBT0%J5Dw+>1ahQ&CtFVIChis^3ATVk(DO_N3S+r9
zrj?sws6j^L@LzIAG3$!MUD9ZonY2ZIm!pLcwdZ1_g)ih&xA?h-l*Kf;5`yl49K_b2
z74Z{<yH${wF4Tgo;3lfdvxjx-CLI&5Rg!fHp-{@`mzeQZ<`_c|2-nIYvtUaFv8m3L
za4Fg%9&wHMNG!T^nlHHwA=*loqM)2C&L@)XNDPzT5kZ<6O)jGc#aoN%B2zqN5kVI-
zeElcnG@>FkPj;6#ZAe=nuv2!p@ME0Y32RuNge2^aoF~bNp8jPY^n>-t-&qakFVD?@
z1Vf<^34eGjj+cCu9wWhx1|B_vV`7?|w06FVJ{07&7ow?RAOZ0*0~_gJkkgkS3sEiE
zT+6&5k+L(~><>C%_yi5Ou8||xMs<riTuw#THRDNnZsexpu!-ypLv%7K#YI?}p0BXm
zOwhH&5}3<U<iVtmJoOUAz%eEGJ5kV>Dl)M^*Eo$^C6PIvD9e!U+^cFSm8K*4o-C=4
ztmZu*<}?lz166ei5G?%3P#TcvofCUa4;`w)@sIRze9v1dXrE1HIY_18?{d}&RSd;@
zyop4ahq&B&=q}yZ=+}w(h88;6th^L)Sw9MmwJ8qBVLU2oL~GTVrgHt)A0>nw5y#;;
zK*Na$E&5zOaK*kCHC2;Aq~pl|a&bSg7^aW#Jng~&kq=_#&wLV+C4P6U?zlsaFhq%R
zfSprD!GGi(VyJLhdQL!Y1sRn-8j#U7fA{;m?XOO!@f;NfxGQ!|e3QtP0F1eTIt0*o
zq^p`?@u3L!{%&=i*NLc$wioGyU>*RInd>1u3Z>WX0ky?+C>_@9$D6ovPJyBy`&Hx~
zQe;<ta}}Bc4>GZS9#8RB5W*sS#s`Q{3CtAF+_7{CXWLm>{d05(?~z`*Y$ti^cBnb3
z93DG|2ZzP3h(^mXLIY*B-yF#gF#n<tR0hx4YK5{eh;CA`vN%@|k#-Y~=6GP#h`z<^
zT+|1Zs+pc#mJ$5YyNT2fiK*ZocileuA>_6={*H$4`3gVXWiaEE<5RO&!ZqPBjIa$x
zEqRj`P-4@6D>N6VB;Uou?+aP%otVV+O91tbT1l$l9Xm)?#UD-@Hd5!pY`v>ClH&iv
z+Pg=`abNkJ)ulEUo^>`|g#uInDYEO=)y+ba1lcW!f$53eRVXwXe24@@$+X535ycin
z(UK^_9F4P?#9fVsM2@J4peV;q=ENijb3AVo;%H_c*(G4u<77Pv$>Au@$({{~;b^n7
zNlZ~1WhN(kvY%TGO4Lct?jO5+fFN1j{d?TU_kQpF-5(Ll4R^UpX$1Wj*bQs}0uKzu
zY`mz>1P-SV5M*}%+`1h4TjW5^lsJaASls;EZP)2ZRRJQI#TzE~O290R;n@*Mc|*Ef
zNcZgSMZ@UnyhN9a?{RX@fZ%ruPeXz-GnQ3sN1~r-xiE8-+Cn3{!cpWFB9gXmQ`IBw
zK&ke+P9#KPN3@x|4pZ9{Q75i8)r)g9y7-}6-<%$z?%k~}1?aKRSDN;fzs2%aIMfBX
zCGFI84P58P(ubPO0<0lq!>wy!iYp8$QZ1vKIJ6Q4nCfAio5I$8nNuY^nsA?@aA0r=
z`?yPDyK(|fe(zkOb~Y$8kE)9#B(@XJoZw~PvW}ujUUpoG{Fc>7_)M^|njfz}eYq-i
zY<NFG4Vt$8vPdon*aKY3i9ZfZfh^D9nWzKYKP<c)fK}x2ise(d!L6;r1<(iS499oK
z*3kebMtJhu@&&LRs41Puq@X5z7l%ub0Qor;q5F{<r-*j13+Y*9jd3^FKtTvnPGjna
zkp|ZR2yF}`(`|8g>%nBTWZek<o{}UoC5bEeB$#b<tf=Hv3Ezm<?ax02>f{_V(#s54
z=FlF#%t>3EM6a~-!198iFBv&{cF5i=x(|xH<DeNjbCg#l+K*5s$dm~1wmTOUsXF;E
zg8Tmp<C@q=L$xaCNn#4w8Zm~A1-0f1lC(WKLTfd*x_1)W9F9jYyY*^X92^hB3+#P>
z=euHfSYa?E%e>h3#$TRtE>jT7NO%r$z8cDbd~W|1Yb?)x9uOw0ExiI~9Ytm6LvCS~
zMdyuKbwp1b>1w>q@+>4}bsq{~C`WxOg*i0>&oOLD=Y6T>Y6k-3Qao?-eD!dxxZ>Vc
z3(-sU4^((0J^YR<+%!ibhD4|nm-jpWASrskM%Nf58}W!0(V&te9g(>ky}{1PNT{xx
zwYt;2DXKx&I>l?;=>lx!)Jg6-Nj8~FVKM*UxWHZPc)~6S_xp*_17iCYqLo5a;Otkl
z7ovZ%UJrL44=;xyX#`PW@j|-bql2Vh+{i_P!y{4MKUjTsf3&gwOdT7oc$CqLR&M-n
z+dI{dXbYy10ELmuH;51a#(g4=Q2mT4jT|66y~iv!=@f5u`95}!E|ZHS2q~BtHtGSA
zf@xs<vOEazJ((#aAom3|nG~fkbj6We4mC5Tr^j(%_jq5dB;p>PE8t-0f4@R_Q5bPY
z!`A+=MnVtKLgr6@pHW-DAcB-c&J)BarKHqa%E0-?z3aG1?+avD91@-ps*yA+saDui
z`N~z1j}J4Ygkxu=MP&Z7AtNYq3}sH`#;bW+5}CAfm30;b&Qc@i))}ZL_(gXze5oE>
zXEP|)R0+Y@wo+ezNz613PPDD;&<cSTzcddOyy-o*0-elWw5t?vgy#)v1hw_lCQydi
znPQl5OPwT;8T$S%KA86uX+n2~k#4bVt7=)i0R?_HLbRu_EW*^fN7a5nIgOoIHnuMD
zq|6WxBmE>J?kuIDLquu!a`liIRtG}gK?ekmYueFUXl2FcSQ1c^Dlmjvioy5;QGL^a
zB|@+XGZ{noWs9TQ6UMp}bw8XcrXTo&bcHeeVd~|P|3rBi!u_iYQy%uctrl3`P3~6c
z@2LVulb#4@?i-S=WXr_Wt9$3P=c@8BbR@5;SC2-*-)wZBhwb1GmP8W%n)a)s2*#C<
z<v{EoaR*Vl;B$#WV56`nm>w29v|1CsKZ+&nxsWTabn?@jgI!WR7uxbK0m)wK99fZy
z7>6VTO^gYqB(Ww7l=rBu_?370y%N0*fv-l~5k3HV&PB9DBSj~hN|4CA%57P6N!(r7
zA5Ky^L~_>6TbPJ8nfh%H9#2a~i$sedZ=X^U-CULP4dZhP(=36VXv1lX9wkm{UHq2A
zsgzQ2p+uiaX|RArPhQb}Av}^AXVQr;CV$UbVV-3Q{33j!ByS;lJHoc86`_*)3nL1D
z#GyOsZk0Fz)<E<bEUtSvue(7|;1KUZwCp|$qn4Z-dP0rPBb15D$1i<d63r<@Mr@;p
zv=>N9U?0m428I66$t=>c7t7X7&M-Bc_)l<RE1iELJ5|P&T{C1OR+5>JPX`KMs1ryf
zLjv}HJP8h8Mc76WD9AAS1_cX+G8?fc+)ahXGC?)V-1Y@}TVa~eufzo_?tFbD*!&Li
zL|YTiYPq}9yg8FVo_=Q(%_Z(H#Kd`o%Mk&U%trw<t_@GQ7*W<Ti41RqPRs>1gBYd6
zax#Ghj>JAx+R^^2{BxcQh9sqz2Gff%`^5McpvXuBA>?oKRRGvsReh#TLB;g~{!%0f
zn<`)iR4|8wIwH?YCdTC$iJIKwZgCI2R9&u)xWnHdSHNV$WSO)VS5nME%wt=mRtHqz
zkb?Y!;D)ELTO?+fj6ei(=QcNCa&KWtt(z(dJRs;P^~MT51M{^fPeNDT9)sDI@kBOO
z<q45mDI{tk#;EY2;tRQ=t?DHLAnV<5IUH&oN0$<8%53<B3<iCGdB7%JaE31{8YEGo
zM~6s<KHdyS>@AeSBfri>B<vM`B`VGMfsxWJMx;b+KX`;@*GYh%fTUI|0fyF%*d@sG
zJVFEwkyx_M>tWf&go*9Nv&a&EVoS<Eb%J6puZ!*q&^bzEIZ(x#RtLnKCb=omZ3#1=
z7^X-LYbvZpb^2O96Ot5mDH=$Y2wB?jFNonPv=WkYW<3gn;3?GMnm?6)&vBJ}dWKP;
z()Mm7$?TmfEz;@D*?!(Bcb|7UzYj2);&K3?k+A%f3Z-!dqROk;W?6oGRl<g>eu0w{
zZ}0^4Ou-!vbnG?8rafW>eNqUN{NT*pfbdJ)R+lWanBF^+Mb;W(Bmp&xAR2faJQsRQ
zRv`iHiOWI+GPLsUjXHbO`^J5v<^HwnkE0^8QgWdR@+iXlk&qC}H^tnve<C1zBQ8Ob
z^=h*s$<%~Cj8uOh#~gBRD|aPu)dGhhp0mz|6A5?E8n6U+_P4WP?RRfW2l2faP7w`M
zZ*S1V1Y-8n$=xavf?HSGK6qVwGm^sWeBn<6Q+!(DV==OyFqPu1<V<SvQ;q`!cMIwn
zy4F!aHkl9Bz^RBqVBxe1(4Yznp0~DF^Ax9!NTE|wdn=23{$KKlbXpd#gsm6XRESs6
z3}fan)+&BsoajATMkB&8Bf$>DZFuF>y2K_ulrOyLDzOcfw1ATTT!ud(5eyjz0)IH1
zkc=2bktP{1yi?t+1+^>H;r#;5-kA))L0UBlO2t-b|0y}-0B3_WM;a)+7d(JWe0j>f
z>?)}Z7i%t+ER--IG422LgkoXbyCZ4gjjI#QXHJPAwmnetH3=<P2rgc7i=?FCyruj%
z-;H{*Ycj&hQb6n}2V;`o;r_`Qp+}DPBVn_S*a+%`6LsWS>E0t3$qIU5020|ehSg3Z
zuPhY1WZk9!xEDwW)4W*fY(DJpOqcM`g5Aq`oD`o*M2J$}!&z<dBJUi4MlMeFV;%U(
zVXXpHz?>Lj{$kg~;Zt}aM+EXK?uz?iAg#%~y<zj6&`s|Rm#b2?0w`;n9DL=ib|C*T
zP7%M&kXK>A3Y*3ihB9uHo)x?zrT2ogq%gFH%xG7tC+37W@YX=lgff?qnkPk>SdI3`
zWqASB?n>d^RlVbqlIX4*)Sp|XaIdgYjDWDftRs*`;b*vWJ2)45JLhTFQ9Y{Ycu@ca
zb7b;1h8bmLc`(ewd6v9wm~nep<@WfA-ueEXsixToEhBNm;sDWwUW%PKgkOTKGCJRr
zHiAaV?gX5N1l1z->=gJ>6zb#gw~Hnc`}Sc(mYVLYz?Bz*YG7Rs2NI9RsKie;q|^!L
zqi9MpuZ|QhtNCbGVfSSKx{xk37^RQwh(x!-gK1y?oW#+b@58_)-hoc&5|)Xv2A#T$
zTO=V}p~DZwIOpU}QKBEZD3Jw75etFUC0oYgC0a!+!EW8>Pl#paU`W&p5i&E0)I^2r
z?elZe=9E57qPnE2ctkrb(c5jcq*U>3_40W2`RemDjdX{nLXrgR5Hbeax`zv(6NH5l
z68g$vH2#nXeh5)V#AWH&N-&~`IxVp?G3&h6pzgWCctb;ccpJh<jQWX%<^YVk?IzYa
zk(N2NH+rc+%`?z%xSJLNJTA5$_su#}r3g9?*qx9{P{k36kc@1|T3cdhfIF;(woB^w
z8sH-A-hE<nFLDzr_*8JFJ#++pA9B9S7<G^nTh1?IEFb>7oK#$(08uFV<UK^F-J~WU
zks4M}w7V@ciBVC(VX9Xm#o6jf{LDtUZu%aRvw#L<hzNklyT<!K-onx4D0G0^IHTyc
zMEWfZmU&BpY;v3^cajX?da@)2l`MM#p!fnjU8P-;Xd1XWr$9+;7B6S1)>}iyya9rI
zzm%v1YQZs|Iklb69^wN;Q$V?M3M?Q(k0d2^CvELbW>Q$9&I0LCMQ%mnz=%tk^jV;W
z+z*W#Oh{UE1=FK81&Z3K<%qtY0g1V(XgM5B6Kh9643QtY0$pa(h!4O>!aC`_L@O5u
zSSS(R2YFYup{jTvDaIfuT`L1G7yqPF##$<JoIFu=zOXp~9_y)~eY+N$%^cd&ubSBR
zNVy(@kH|}iO8n0^`y=|?DVRgtJ4+<u-&O!@XL2leAt1XP6>qyudfAS`blk@L$#a-l
z#{P>1F*;Y<W?m+M;cif_A+QRci1uOZMXg|7KqzslXGI2HyinfI$sVjN<09^jU!bJh
z?+9}%b~B0fq;OJ9Im2I_Lv^mseOoFA@kP1>Op=${Nod(;j|Yi0Oj1t5lIyB(0AwDn
zxRB~>Snyor4*yW<VmNfgY#Eu54R<cj%N&Hg6=@bMKmd`PFqZH62?yScAPAUDVqEN@
zF}ZDb-7P~kSAgXYmo{)0$$Ftx#RNpb9#`sG*)l!=BP-VEeq|`O2pb{^G|u7+C>d04
zbvYb%-IfdNL2=|^f;^2QaPDn)33`l1F<XNtz+0s2pQ&@Sfm59#oiYig@Mq7;6cPgR
z-V6lHh(ZV?=So^9PY^CznMR_SNH^E(#K7Cq_Dg_?bwn16rLtJsbrClxxT}r}Rb$Tg
ztv`tQ$ehA`QOB{X@Ju8Cn-Z!>evP2QVlWUOrKoz`C~~Ff>ZEdKqW-Yj;+_%?;Bb;4
z>H1Ygj>I5ozxbDYf%Q+K1LP;Mp+e#<Ighnj(?k_ffg}P++<{nH0wH!Sxg!*1nQh~D
zq!LAM+i~$&iO#n3R$S6{2CKN>CPb|74!2XK62!_6mmixs_v`wgo+Q~{o!}#Rt7J;Q
z^CiX#{FA^%#+by?^6~Qf%V@7lC3AuiW#8o`#H<NSL@CP7Ras@wgwTuhEoG^MOcmGq
zNezXcSSdtmv%n3)b5>MZQ1UE+Nis|)zeLDvnphDMt&H<&GA=H_3*?2|+*y%Z&8~>p
zVw~@()<<k~f&+q;;7q=NsY>KINso{u5+lSI0peUIkc=5z`{#L46cIE`G)sXf-)Gee
z!AjztWV}*~$oaPJaawC&*@HxI<Y|6fRr^)W(zU!?Py-w0=FKOfL{hLJce<sNC(%D~
zBPd^@exi?wCIZ9}V%al3o&w6Y8gg?ZPsq(h?S6Gs;}V>y>wZMB6+40E;qVwYW53UO
z3m?83LCmQ`*C#<z?w+c~8}nT9Xc9^$$5A%_FmT=aO^^p==QpbRBRH4jA>Nr`AO0-E
zMr_5}!I%SC=)dTw-DQW{L;zT*8tz<fO)XiZC%8hKCUqq>xS{jBQ@CYZLf$cwi}?b*
z@Q4a!z-_0QAgxue=@l<dQfSR}I&k;HpmBQqRn2#T<HVkchm}l~YJkRtZ=_hbz+pr8
zL!!#uRFqijx}1|?@scP*1f)l*Q7HB(NGM62hrtx2M-=-n-3co|LxdMQ)H2c>dy)p6
z=cx#Bid+vhhWjC?Y)<9hbcjFM5n>G<7e)TaMlVp=E~<BAIeH;FvJz3zI!QZb;2{A5
zdnjoYVVIS=sfZ)4Q(~+(!ec4@D2EQj#orDoat`v_A)3S-GHBz;dom(Y(T*v31Mz*l
zk+|@LK4GUwQUJU;GhxCto1BCrk$H);niJef4j*dxV`IZ^fEkp)9hv@wWd`wa&YPbv
zh?6hC72&*xLE5O;qX-pZB`}3rCQu=QbUCmVf^SgTN*Px04po{TQl<Gpl@!t0z}d=i
zK1L$Q_U4mGb)dw-tGs@j6qT=SEyXP1{S^KJT}KW=>nsFN7SfqPUm~5=$%S|&gTIaW
zV{p*2j65n*%lm({_AAsAM-+w$<`yQJq-8_{vVit!*y+9m7$>5cYyp6gpJ$_Db3XE3
za0B}Dyu|Wf4qEg`=Q9vWjLw~bmA0gd*%Q|;7`IKq(Vn*-ia&YBc7z=Ibns@7Mnw)E
za>yQU#$U&fC`6X`lzh4@;zvWis{$c2rBYEMdkEYqDygJ@A=h*bRQu$4h9W4SDbWxo
zu_78SXoV$qX;-0tlBDx>f{FTG_qK~(h=oA+w42`&XbyQUP%5GN5nlwpb16R(cv3%#
z5XhkI7v+*wvzzuuJ&x}iF)TU(k>n{@UZE4%MzJ~q**+Tfl<==x@q<W9v9*%86^?E!
z2g9HYTs0n`t<F$uO6aNDPL58rg`I-l;BKA5M_|h#s*s}*wi1;?(4P-P(50*?G1Uom
zB4MbQL+oP0qe!(Is1`v<RtA5Ql~g#;MY@O}PbG&oL*D0c0ILYb`4S<E=rqEcAk_PV
zxtv_?$Ipo0h2q^pJ--}ozEQtX2PQqoN&*-dSt2k&<hq53b$4H=Vq>0|<TCo;5Og6c
zE&_wFJiR`dK%4Sebwe@%QbqSX5(%yR&m}fe=n`=&xL|I50Ii6ABuE@tOV*(Mn*39+
zF;RfbuW~|(ulsls_wp^W7eGaRAwyK|z+M#c-D%`a#wI^tR|x#sIL-vqn4wVpA!`_n
zre%MHnZg~lcntdpNhtn1hGP*kIqQtj_#IX=ksCRGA(jBh#fPnqG@(Id{K9yFxOQP9
z0zqj)Z+<NG?EzxFlJQ?8a$>**j;RyWL%CE%of4}@oTf`7UHMHrw!X6g<p(seqqaL7
z8VG|C(F)$4@qYasVadgB3%MzSh9nXUb;kK(K#3twGEW&ZQU>kDZpbj(V;6KF14hJT
zDzx>@v(`iciFsk<0EI;G+ao8AqY<&f<BOHyOG5N>R-9_235TU#4Ve_~(WE%iYPMR(
z!yENwI*aTHo^iK^)@{IwEQpLn``>yQx|GMZjiW4JdqnNfQiS5V5dF*{Np)cisI(U6
zMbIR$5$r%1fy9XK=Wx4>80D6wVan|3$AUuOaHcKoiM$JWNKSv^=>YG<s`D9)g>_#F
zI6h8_eL0w13W7b=J%kOr&sGmfy$YHwhg68(HbXFKa93^2%`Qr!t33}{Ux}m{cOogW
zP4XMh*9MIVV343sz7bX~$rcDGl1)mUTovUxR(VQ&G;D@X*rN`aoI-V+JT8xgY|9HP
zt|fye#<}fsqZh@B9F(4P0RZ<t|K?Lt!`8sxv+IIlQ!sN0fk<aeH`y0J78KepgWBm{
z)%<D+fN&3Mx5qBgouDxZ(vs;3|9jse1GFQ|3D+Xy83TY}@k42YLL#Uh)@sa8d>7`N
zGM5$Z#i9uq<5er}?fODU`Ra!O%n)sKB{bbiNR)=-5Zn0bFEH|?^#Mjb0pZexJqZ9P
zO>T+IuEHo@(TK^6BNK0-1kG{@jz}f~z@2i==9P#jb3|AZ>we$hi-ngjDvnD=fB>!|
zn<H}B6^;O3MsP5=Me!LTUCHo^y4)+7M+e|s>N&2X`9MjVuwZ-jD`Ea}l~_l@Kt2g+
z`I01a<9ilaPz+I~WYAY3!3J8WfCRBbWEPXtX12{i#NI`&k3`6BQLeyL65J@suMZqo
zjF3oT+t=K`1?}TzXlE3W`9V+RDAZ9kRj}R(IR8nzUnb9|h|eLRh*VO=o`p|s)T<+b
z1arXR=fV{iV}v3x{5ya4hqC%@Sl$L;BK9a=5@9BG`zhILB{H07NN950R-@eMu0tOJ
z>=Lo2%85+{_qv4}K5?cvv1AMW3wla9kzld@NQk=r>Z4V6n3RLVHUlF>L%`|)f(oEV
zin-24xo-rJMOChXv65RShl2<qt%#AiLq=bg9{__XPcTeU2@49QRt%mQafYXp^#pin
zbSQ9&@-PMarG5i-!Nx4+A4?38*exDR;4g1|pWr9fMb2TvzionFJgVql^L%wn6=vFX
z5n}<Ithkb#IuR#YdfQzo)QRx@;pMP4dR#=taoPjnN$q#?($=U;sFj2w5^K>m?GirZ
zx%CtQ$Y8mA3OWZkGH3I@{Fe-PgE?E;p72SDm5~#b1yBr@krk9(y3eRDDE0E(WbtBD
zMEc!b(a?1_L=WYB#%5G}m6_yFC->R3TWTmN{*_v~k?Qj*|4v|C3~Rf>yo`h#44q*A
z7x34;l&1)c$cZ2UaqQxH5-;h(l?n_`vr!Dn4!JW`vo#u19y3ztFaTK7MpzxDDOMev
z!K&Q1<ZOByycEP2fp<v<9aZ6nVU_c=Zgq(Q*`!jB$?5>eCPxqG@Akvsh3N2U*V~Pt
zoDC)<7m$3ufb~01R2jJ7k;LD%EjdsiiAIxu;-+bnX$o6=H7r@XrKO)-vjbw38!@@i
z^O8YAK&o^6$1UDiybx=W!~!3Wy~vUmSZ`vyy#WrDLutpucVyJT8blmnVbFpd#ZAi<
ztAblZqY?J0h*QSp$)m1iei)E{fz)T4SV1xw>rzO1lIUL*g*K~*0(KG~j~9jBk=Y_P
z(wdp!oAd(hb{H|7mJj|-x(G`X#V$WBz9qpUsN5%fsYFR6XEBt?&&eYw|K1?|eARhI
zYSFM7SZ;ysKpoC51-Zi6fXv<5Xk+zJs)CPl-@@&%UKiV1m!XJ5(X=n@lF|EEiB;FQ
z%BVjm$DL`h#(Sb2EPY7RaW_R|-R%<>b&{^Nx<y>*Fg1*ZA}53!;3Gul6P7WecJ5*U
z4Mku`-2-?FBWe#6?W5sNYkR<p@K5p*7<H_R*C%%}ZGrPD%m)Sh*E7T>)_CD)Jq+6X
zzF49=|3><PGShpI8?%nD5s?>E0Hn>2mR<G~IVU{b>r?U4>xfK|tD*Tnw>Wmrai$6)
zkusQ7-p0+3nrR*fZ6xqI`G7VLO3;MuXlIa!Scz2k()t>+C@on=L!nIx<e9}e1tj4>
zeK~+M#4FcvRH_Q?QQ-1|I=yBnFt4&v42pWA0jY5o0ZoF^HX$mp2SZ8*g&K>AUk#ol
zC_;GrhL2YRIZEgOh~zT#@@g$)8)NQL5Heskc33PApCliVz~6#&kp56kv=+F3g>tD8
zH6o|Zsc?OXvtPV|7`Hu-_Dir++yfxp<IY5VQE)U^sNM*$nY+TFRvim25DqE&>92?s
zrP>ANFdINa>>@iN)rk+9L?4WWl}(V=UjG=Uc6*)pf+|8ve_rwcrM2bl2{p|Q;j-bS
zcPSVTR*J>tWmqA0`yMInJ{lcCk2##%u2HxV9Ip-p6VF<cq6Y0bCs`%7gOdoG>T(&w
z4F$J5srD)<XnZLQuGhmUnls)5YA^nt6f2N##$qND@W_S<?15~Ir(8CebrBK2=`WI^
zq2(oKyOXf-;SIvEQ;L+ED<wO}?v3Bg3j+*WBVY=bv8oj9U7*|HMRjD3yWpa^!ZYgW
z@yU&p$3|zXP7(t!W!5yQ1Jk`6Rhu6~!B#p3E?|S^+}a3t7Nx6l!g{k{?>0KV^Gkn*
zEUo4vSH&j@kmUPBTpYP$xPXaBT(n%EZrd6-?coye@;!=6J2{eUt@|n%UvP5anx!Zo
z5F3h|V=q?yKr#b$I+7R`+_@E|%*~Ald3s#zuMS~RQRu|FAa)7|CYKOXX3rst74^di
zuC7{@>t>}vdp$9Uyzh&hl89`_+~TI%dJNV{w4kjGF1i3*OJIX+gE^GagpQ=$DBVdr
zq0`9-aHjx->Jr5|k_#57BW8|p_aosct3W7qX0ZY<E1+Glrb}=qcZ4KJQ=0TCRgfbU
zQm#BDU)6$3{hiwAk`kc#f)w>8!hnT-@z13T6R<u33`B&;4em>RU2-MRKn4(fE4`Z|
zozzS9=DzQ!!R@z<T$6M_`$4WJmk|q@&XdgU;{juO;Pug1vHz^$hjmx-0F*0$7r5XZ
zAH}#O=tX9d&KT-k5P6&Ga68*oALmf6hs)?|)wNn;rPxg#eEl}DlpN9n;K)eXZz+x!
zou!=kO(+}TN95j?JxQgS-B@I;d*--RefxP<y!R6L9*>d0JBV|B5Wq5q#FXDNHyqPM
zXelO!yirMH@(k4rBjFH*fO`q{hR}|-Xf?$2dsjGrb-VDxNJY>6P)t*z7BpDSQB5M@
zoV@uR&lN#$1LMR3CMKhRO%#leBUo_cL~j!QVL4hcH(uJdCFlIa!f;pT_Vdn;7;G=5
z_KW5&Nt<DhE3C{XjpcQ0hE%4Zfgh^+t^)P26BEwUxTh)*Es-mP9LKdu)pkz0RpRtX
z7qdDHlg+`5>Rc!(3aBQIuD5StyO+IXjQ5~f8>-3Q@8$vXlDuZ+M{m(d9&APuQaa!X
zC%l7o?-X=QLp*_;5{#p$c_pkwn)N4)VSVnCbf+&tFH;d}3IXQs!Y%9y?}TCP#Y85>
z_5srr@Hkis+@13UioZkkL1B_!8PIK@Q6wy{kViNvS^KX_?ue^9SA*(AY!WGuOysx}
zJIHew4PFw`dfBvJl(OIE99rR(&k+cSX%$=n!W3sC3=?nsk%QV4U|A%T4XELf-lIzH
zOD4Fpt`}%|Q5Dd_u*K(qE_DxJvzd%<1h%h-d!oHuDOIJ&w7I-G26^!7uL>J13MvT$
zPn`zbCt0L2jhO^(rNxHQ^PGxla;B{A0!u4)aK$`NojtOKmULn~WB4T;Yg$Hq-=Im3
z(wYHWi9w%y7mpp(KsWyIq|4z<gjTjCIr~KGPfh};N83&~cRU)9))~>3D*Y0tpx{Aq
zcnpaYv<<&03=`q1ARIw70_az<K^ren-*v_r(#7M6AGW!h*fedk(-@=Hfs-%Y)Tcwh
z8)N?CsUcm2>Rw&meIi0_u^{0UwX9xfXFW#9E72oo_@!{A&NNvcMvst?Vqc-=cR6CV
zm(>CqjUsP~4v{W{IOe!MqK>7N*!8D>OI+!q=pvp+^b&9;bpvfq67tqr5X;Db<OR%^
z`^;~WGB|A*W+nEIF$GKO+Ak(tHc+fGkA5sA#g??f*jkvvG_OnwRk=4jF41)>OtK^i
z0ibBi+PtogD?$*#{nf3(T;X}eCBYc-r^h2Y!3o}BUC_@d5$uZacb#xAv=o>46Dm6o
zwTXRg7juLhkJAo9RZHuB@QuMArbHoZT7tbXA!4OIp@iT-F@e|+GSKxY#aW_=R>#TZ
z2hSx7EaqOz>RCN$PFdixK{D;t;P6OwPY8ROyA0&2W1nQS+MV9*j5L#gb;%y1SVBW4
zn2Uf@CCi!EKEDyCzGqNhl#wqMl0aiX7z|m<P`2s51<jqojerX!l>zwPIthJ2$w+m0
znJ0&rAe`m1878S1iY*90g2NmY(K$Q0$E`h`6ax~~3H63Yq><j==iS>`(e|z*0;(xS
zPDl*;bwH_0Yym7n1V(+rBF*l;W(YJl-!F0FYw;}}rMs#;->$FXWL#b(f)5bC)E<3X
zz!D^a(U@E%)fWom!J!*fdROgrSvg*nICdI^>Ykz^V+s0kiFKYlvJ`MaCw$ipDUA6F
zWG@fnl9<B33ZRcPjv0$nY5x?KRQ@iSD9A4%G9Xk4G{ek|Fx5y=3(egFJ1&$zFQ|3}
zD(0<Hd(ymu8gt5g+O|vjn74g=q9D|MNO6Kh)NBC?sX(_;b$6Qk9fu)>gl~`;C+#sB
zE2<jIMTbFO0h9-IF7H5!aj4`BHFg3xW%%El=1UURB{8W0x};y5P>*sAArS)Wh}rOc
zdMqWCBFTcIuH_wb53AmV)q#V++&nsfmf+qcIBHAxy>TPgQox;*aVs>NlIQ)^XU}rC
z#(n}9z>f@G!s<CN*A-P=iV*PrfC9GNcio7lZkuno^P$ssT;?cBuKlNV3?1RY+G4JW
zB(T3?u!RL(h6xZTDrkcaoCI~L#-9klE$`qs0R80>%qWmow#dca0IX0*+0(?^CGN33
zcA@DCl78G;csmkD8LU*PwYVH|@+NTdSWJ;+Y$cI|4j2!eP3p+Ig>-*ZrP){&re;eu
zFR9Ai3`llIyQ7k{DL^B^t(ZT=L^$fU03${8Qj(%Z(G%Gzn)i@2ZRDg9^DV;Dvbk1V
zjp+6G9)}8L%pXn?jFjfrC&w<S=S1AeBE3L3dbd!|Z4aD1!E?9WP!imUVaw8PbWUYk
zlWxDlu56U}=Xf~jy7b5<n<~{^vX<J_=M#4$>LjC=kOBL5kAhjq<9h^xCD_F7wkUt@
zUUUGj+X);taI9;gbjtva010uhd)Ot6RpNq$`DJN7W?{s3P<2841NnuSDXvt{hLVV(
z-OtuKFH5SMC3cW=+I^QJt1OBU1h6rR%cn6;oW0P7=fkWRP8s~2vBV~lg%L~0S1N_Y
z;UG0G_%~Vb<P`SRaKh&rK$_&0%Ik6~`1i$9aWTnKvg#ZG?35A^4HF||3i{TT6uyeE
z$iWw+1$X%_4s)S?*DV~4xUC?}5fHbnpUfJeVd$(nfIu#@DB>@JDOIn2MbQqo?vB(S
z4T#)?_YnPqg86$w16WCYG1DdnO9})yN!L;k60(nM=TJ&qD$=o*qb|fb4?FxR3l8*x
zpQinVz>LJ5$}8?$@F?O)91JN{{U1j4e)lWUE`U@JNQEW!`m*GSn}xQ}weKmKmVi-S
zfNgvs0tYNdoG5oWQH(blqGF1nFlO!bg*JDwYM<LwqX@eEMC_kx2b)4BfR(u5#HGP-
z_brxOQ0pQvmZRmfQs3Yys;Ph1;jj*Jj&s7heRBM86|6fMf{6MC3^1ixbo~$ethd7!
zgHH+&v}{wUrk-1f=v_~Cpzj+IH>%gS6rSV4Dk6P3!AmHXPQduTvzP!inTaoIlRt=i
z+}>>dIWMIFEFvQ!p1Bdm#$`*I6cY4s4+nA327(`?O-_eU0s~%vYihI9AeE2LU$);6
z(b-g$68Z?Ez7oAlz)S%>i%-JkxSanQ5xAUKr&VL)d1QS1)uT|58w-70VHK!%!pq@&
zSRbamUT}b{(4FSzm<AOwNs?tXXcr<cDd;X!*cVAM1P!UA!G_#N&2gPh3G_uZxJ!#}
z6UIts`xT@x11yuos)-9hYekOR?v<~2*yfz9K9sc-$4nM}7{DWr)QL@@e0iDdowVds
za<cw5krSF);6S6a+&yx=`UK5f5jsbJG4?ol`p)m36u}2cwPTsYRmoY>PGWd>s43;>
zN#=;FwXRr0F-&Ruc3<Jzu{n%iok4_>$43H=xk+k9q=>yke?L~=ITcabQ;>-ijw}?m
z7aTYj7&$kuK>w&1W6uiln`O7i00Yp8Hsl+6d;Kuzuev^`=w(qv-Vo8({!~WZuHr@7
zlQ>k6dLb5MaPRMYpB$q{!7zqI8m{4{fH}vES%cHlMi-<z6fkHP5J}a>m<ri3o^8Xl
z`w;>w-&%;+0`djW*Z9t%YV`)F_iPvjOc}AmU~#fYqeTH=PHrOL;_9u10l1@JYH}gC
z5#5keYfoQ~>d9C{(_Y=cG=zFj=FnE&1qZ+T5sxM1V3>a4CU8Z=R4Jjzos9Mxb1-_0
z6lK-KpIraL0K_(A@Xrk8<F%J_Y6#M5c5)>kt~(kX=g83T6B22FD8yCBqAJ1+4-ibu
zDU3(ZAG}bdoC@;d5Egb5Vc=GgP?iYUyz|F$TBj}kXh7TQC#B%dh*ZfiTwpuf#T%Ps
z2`tX+cKe(goG@g_g3}S(BvWuNm}^Tr=7Ts63s3U|q6@)o>X`x!&G#!AZ&jl0d(w`Z
z+8jc1kankT*Y&rO0n0Chb>WC;pv9Anl<wDGVW^r=Q}R=nvm`{5XQ>ll+Olx+n-W*8
z6R6(nGepbE5V&<&K5HW~9m;?ugLvP<ieV9kUwo4!9s6O|_C{0ncS+`k`Tg|bmM9ya
zfLtILMZJbyFX%_+gDpVOXD>%AY8`la+a)W2R*E|%c-x=iYdcTc&c%RWR*SyH%Fl^=
z*Y6FQKi!nAc{}FH#WvP`tHkkc!DMX|#2K<tjxb69A&?|7bOPbUv;d6e@TaSXc){;g
zITs62u`%Fu1J^k24QW{><Pr{0W+BE!SB*KgBzOTA6%4;UN#Pn<ylPOZ@(HVR*!xye
z|Ans*K~6L>p^n@0Nti!5SGg)50N^2*7Rr$1I4r-VRC+@vfD*dp-V#7b^An~^e711e
zy!gIZ0BVy`(z&YFUq8YbS$1F`i713f8DeO}q)dTB19Nyh2ag~JP^nLfur(`H{DRBn
zU3B!QalI|ZtNr-@d`!5-qzYD$fn0%;uvQO_OHPb6ZFllbhYh(vo{7pGOmk|-TrOGL
zWb!nXgjr(bEI$GyrbssU-ukPXQdG4Sic>hcNeNLg>Ce=key30m&xH&fdy1y;8saC?
z7v<m__cqT(RanKq-+d#*Qs&1M528oB_07L4Cwp)!2}vZ1$*75|r8I^+CPms4pJZ}@
zrUr^^^Z!ZMCy|vp^U<1<{K!jveIQzlTf(%o<zJ!+>g%gZ_$4;>qS{qBbf)_BS!#Nc
z)0B)iF+v*1y+I3XE-BpnQj`Q&*VXlKX|g{lFQ}u<?q>WJhK>3C^j8Ja5OIF|6N7#&
ziTT<QAeCS+qf#y)zoF+Ev4ax=z4HqgaG{ev4Tn0JGrxX5--$zI=ac5Kl8?DhUUJgZ
z7fTayD7?-sZWQ4UkGsR%7A4kP3@9;^4vyqn<jEz4HL4e0P}=j+Gl4VlEbSYof-(vv
z)<xU!c_}ezr+E`Qp2$7x&K9@Df3LX`P)Y^*$uL)X{AB%v@E87kg8>j`;JrDVuEXu#
zcu_I16|g>oPwY*y-l{oY$NTpOI7KYYNW|$Wj;gA<TOVS<1(gT@KuHx1UqmD%u)0|2
zvyLm*ybXMDoV=SXHq*QF$8tfe@EF$x4+2U=Or!unIN7~m7b!oI;o5Rs-Rw!y6xWPH
z5(!%E6&8g5^Z74IwJo|O3W@lAB-n(<a%4^Q2RpIl)hYK0YD$ME#a)UDV4Fo9n>r@^
zT}AcL2N8yUBg`Y$t%e(`&swk={4#k{S?140jQ3-#0?q;fqK;z8WAGn+&P25u*FvM^
z$PFgRR3tV+ATA_DZRqbFM<ECd7tGYA);=09?eB_na1%fd=^P?u43ZThwy$H@&_PyB
z=oe2*>HvUMTacc<4+A%F{N3(+Si2ewBvV7hv^#gdD&rNyEkDJK0nX9GRbQV7id1^B
z-BLc1meHGL7BeDsJnKuHZ<NYCb7oTUlY~<F5%Z~l=KdIjbQ___h{Vq);xX5b8jfs_
zh)dOxav{el^ntL_Omb9-vCPh4yD>GFNlJ^<F9*fjg}DMfMiLWJc*f--^7<+|!I12t
z7K0;a$xv4XJF!~rDXpR`l3WZ!WOZMdJ!ZAy6otn!-~^;!Fuig+9U~x<@(pwV<DIYp
z_c)})RH~hcbWdJaPyxG?Eb$1W@<4bc91`jP_ya&eUX+kDf=}?dQLt(9@XoaNXn5#y
zAXiFk2{yVT^6mf&{Qk**zbZ2lA|$`W`Fm<NjWorH3Jrv^2?Zmi$MDPx392Q$%S}sg
zfwA8Mlu5{2!AU6PeG9%5L@4M=ye54Z=<zv4%gO39NKJud#Hfk;Z|LwwoR=3o`$8aL
z)T6<37YqHNAM8#CyTDZ=$slCFgMWhoOYEKel%sY0k_>Kgj#UQhSC*}zMa}}6St;4c
zU63yi3kb)=U*}}^HJ`#TvDZn3>L=ECqe|8-0W1<s(?y~xSErM@<z|WSa!?oV8YcCx
z1fxn?9Ys4YPI|?8^{5*Z?$)dIYUJ*vv{9N<CQ8B9|MXw~400lDg%~`3wTbeN1zidQ
zn^5-{ZL)S097zQUy?`t#k4Ui4%1Y3;{4yR7U5eEKT0EJc6=drp4HYN<A-)o@CAvo>
zs;aFPm7#~|xGgC@v6o;iwut*k-VR(f9~J9zI~<v$=y))$o^gjG7DsfAC!eZH5-t(&
zdoV-(Y`bm=bfq+uoTmg!NQqAZ@q1Rv>}II5Mo&_uZg5Z#%hT2MDFKM0{mH1YE%%LE
z)jT0brR4<_-4rKUIb1PbczQd9tpuNmWnq@$ZuWsjjt9YtJ4uaHVY2G08Xv#k%`<E<
zZ&<=R|KzVBBUo-^<YVuCeQYX!DX)m)p<6}#hg&K5IhzQfL1m!a0H+y7*W+Dd5-794
zqOT136J8N>CNT@3h%dL@cMEUVMXF!oTD=?S*Jz7ZwSf^OT>wEKz+AmiSOCeoL*J;^
zIPDa|tw^y&G6aM}+xmZrcU%=^r1|4UG*YLY(1XAW?5o8^mgG-t0}xLAf61`BWr-Oy
zh3SMhd^QskEoAifTRs}~C8UE&e7U+<*cEI=rn$4X8dhn_B_(6*wis`=R;|$Zj+_;`
z_^3KUQO<|;DwN$akjv?F#VMe(+KUg4TvGw!p}E>_m>-CTY|vp>g6RuR!~Bew4{S5A
z1Cx_w%di>eTZIm-mC>Ds{)5!MTBbYgv|`_JNY=HMTZ-)(SK6dLnkIRbk$2?>xp|~d
z_jc;q!9Z)IGuKCkbVuXAvnjW7-qbv&w9e?zGSBABmNw72J5Fm~plS8*`{&Jqo${Rj
zabk|Q)~(pD=#`qDS#zFu9B?xpqU1DMX-ZDX8n~2!%V#NmWmP)ow%n#(N%L3j&fl5N
z209NoCOsVYIa<8U%LL7orJV}ufi^_ruQ<-=EgRv}D*K)IER%IHP`4^p$8d+1@2K%&
ztx~h4_^r|$P@B_yQ>*Z~$qzoHre!$`g#!w-{M~=IYxO^_m{(+Zq@=i|#qEDI<-L{0
zM^wz3ydkej{*>g*xq!b)$SCnt`-jpBD(z^l$gn_!J4fpBAK4TOsAYqc9CBm9wXns%
z#+eQ$>o@&W#>BA6bG&=|Lz3^4CF0@L9}OOH_=zEvf4lScm*hVhv7zE)raIOcnHyE%
z4Z1OVpelVPs99fb#ly9Z#a648sU42Hb=%&;d7`g6OU}kJk3Xm~K@gY+iZkK5^zx$L
zisM$sPS%Y!dQG(ukQI@{NV6@3i5SXfX7NLc%cZZY7MGBn4RXh^?`ezy|M#zI(hBVV
zpC5O=IQIYgMp95Ba`ed`zQ)eAWo-37Z2r7+Vz}X_SO^ts6))v#J!Z%D=bD?Rtd2h4
zL&&;kmAxJzaJ*kLzv<8;+A+S_>zF6?+<5#-P&hFbdxg!xfpRPE?>$AoJ8ejrpNXgS
zu#uilZ*hTQVM{Bfig9ZqJnh;;uCZ*YBdK%lX%!&PjqONGM!7+AIZ)b&+gLM-Yw>nY
z{pDv)J6dluMnDjZ#!^ovttw_p^D<@giqWfATr(^?^OeI!JblKd$tMH`=(d!J6yIcB
zlvK;61Gmu>Im%cmcA{557zA2?dTEV$mk%x)bEbw`FNO{RxihCenA*|s_1M+oMyg@d
z^op-;HA~*rm!0^Sb-1a1jc$p#SIy13m(een9hpzZ=024zt#!Sw=azn~cYRY82E793
zIS$9`J@<<0w_kKU>of7IZe~q()?>laPQ~)p44yLsv*zudGk3W`XgftG?b#QWmB$`A
zwhEX)<Yos{s9lLpyGT**-2?xF=9#Bbjno$J)RK4F+^pg;HKSKzRkHh>S^G6*p`wjx
z{fejTR!env>~Ebad9iZhN~=Wo#F=#Yd-fSy4Pqlt`Zc|3yJNMPI5^Ro4V5at=$T<F
zWoEeJ&bGrwN?}1fY@uTHg}hJ(rB3I@pKP|$88;RDtFr#8X~y2kiRr?R>`Lprvpb42
zf7VRB>e#=Tn)Rm7c-qN1$0(KtFO&zhJC;}J7;MDNxM{SEWn0U|K({llKUhqe2Ti{*
zYnQtRhEJ<7Yj$)xB}<(%uh@Ri!`9$Q<LvN3zc(8318wI6MK?DypZ6+fJ+t@a+j07E
zBL&#Ev#A}SiuJ}y^OD(|a{{Hl@Y{dooHKnZj@SwBHwivezd7`M(=I6U!~?C&HwQO4
z)6SSz@KV#hz2Kd9ycY-TA9)S)yXMKb<Zl0(^&{JV-O*!b=)7~1?m%a4ua~thq>9e$
z;CgT9SdH!WPu2sw)qP@dT`^tuUUh~Jb?!2s4br~3n{X{OgM)GH+=N#go}0*;XWfQ=
z@&N`r-Ark=(Ua<JHgnDBW&8AiR{UV<zt6_!O>=&@c0&I##UO*Wd)hqc*mn0|kGe8w
z(CjU)MAP<ql`Y$+&X`x5`sOqCD?z_~A(cN64EtlP*W5k!_FoxzJ&4~}x5x8N8R~tr
zuiX7jLlw*~w|b{M>jPg6pIGtr^2uv%>K{|%tp>S}sW3g!8jTn1Inz7&fC>@AQ;Swj
z)q-C2o?>maD}$Z$X78M7_ni0Dk$5^)-o3H)mOGKN&7E=jU;dJ2duql^H?G%GgCfHX
z#~3WhuCyA#py6tREp@PYuo)Lz^JFTM8b09fjn8<Vt?ZFz<wSGAOL3?}_h($=XRX?>
z7wdeE+nc@_uW2k6uv0|6u%5wTzZC}4DxGcVwq~Al8ct66PP*Tq0r8?cZtqkj(=%&#
z{^?P)SX={^5F?|R@g_&J=);O9&pIiUi_M^>$8j#;eJUMx=!K)Ymc<&J<`Ip%el)Y8
zkEY_v8cdH_4CmeH)WO)xwDhb>WrB1+|J_JsI=qI1EiqE(ctN(AGH?EdUOC~UknPxO
zWqsXt?9HUejcMIb%5FSROkroCAyPvnYo8bT>r!5&HCD4***Vk6q*|5v;3NxiMK#QH
zro$a=nav#bt7SIkP0U)won<ybul}kfj-@jlYo=We8Y%AMbM@?+JIl{rDcM$W)-+Cg
znyaSu#+b9su}+r@9sA5m*~yIAEl;a_llu&?UiuZ=idmzKy~aBjh5Sd_)4J4tXL@2_
z)G(T5^XbTPw}sB6I}x}hrqvFdOjtYa>Qys+zMwbEx<9kzb?e>w=2UUQyy@sJ25QLb
zEKE3|T6R@!bNbFJf4kD*#c>%l;!HDvWa&t=Y*W*-y)D}{8-CLtr0e1d-Sq~TActhZ
z7<Op3_W7zYai+!p*yjj0II!=x#zxKO^xb+`2$!v=J4~g0&(=e&X107MKkv61*3UTW
zRmIRvZIeZN@6)E^xu-&Xo2sO~{otosoyu^`AylHLY#Xj=JI1f%oN`}Af5<au2Mo(N
zrCUY+WRPm@L&mZXW2$Bm>DbZiqLJFH7nX2-?!0dfX41RA<Ffdc7mPN;_)~y@dCNPz
zJI=-5ryXmL3R70F?vRyPDiu@qK}(q#Cy1B16u?sJEN4wkYaOujN`0_*N259G#fEFd
zpPjXh*xuLdijb2YRT95M+lbU7x{>*`=XUCqTFtj?s_B(xt86Dy?jgDj{jhz-t(|sv
zrox`|?oR<nbZs=f*|bt;PtN*bcgd|jUfbh@e$<_+bXb}5u2rEQ^p&y3nzHHo``ke<
zo385L{>@Ko=S&<#%Lnx~bY*88y*zy${H9$sAF#Z2`bj<ikG)el_D}OinrK8N-H7#0
zKaAs4tjd~OY5ID@H<!(uuHQ<Bn%k>%*X&CfR(9O|o|)F1&2?COo-3LAOdJzB^75yg
zjYjtDK#oKxz^`xN2h|k1+h^!kie_wQ>@%jJIhESZKtFBckqUZ7kF|ViI!L)#hpeuY
z(iE4)n1%F&+ugw!9&j^8IJBsGLcL<9O;<a}>trbB{IH=eS}IVRo9UXS)}?_AL69x`
z>t3!?1)ysOvgz8lm;Y<<P&U@-;^P594ehjTXbNQGO+(wpjP9n<WQnq--LcI>0adD^
zXH!}xl^sfH))18)S=I=>hzUT#tzsz5bkR9$RMZVG@9UZGhYdG%&^=f%?Cerm(<&-m
zX@)dY*Z!G13L!eWSlZ?oon@yt(4Dy3ne`e=PHS6<gU)8k%P9Topfhe(7P%_a3BGH3
z%UWK4l?V0SAZ6^UnZ2fRmfS33eAM-x)Enj6{#xdQt1HCC^lAh<YP#ebS@V)}%qf$n
z3eB-xr`fbjBi0+U4pCjH^Q@_%)taLmEm*hme9DXwg`EBhP_Sjkt!!#KwJ~mKr+emm
zlyl4;^BSpB(|WhBYx`>U?v&|=rQMN18mX49bc7i_yc(o-`$1TCe^d9IR;9UUZX-C~
zobnH<ik?aJE(hy;J>N=eoVd{%Gb|f;24h!K4ZWfq_1^#FHD*5>&;DwuZ2h%h<C&g6
z8eHuA)tsHLjm^Do#`=TP1J=xYMzL!={+-epduG;rW3h9s`Pr{NY#u9>oqu4i>wF_u
zu)n4btHK}Jv;L3Okn{ag?|A&|V$R$g4Q+BN#qsW;B~{+yoO;7}W^RwOb?%XH<DpR+
znU7ynE8$pf=X;$ycV099JQz^Bn^W6K9)=~D$iV4aD$OiDed@->Tl=SiKL|z!PWsQ(
zf9dw|v4K<9Jl78v%e9~VJwKxC@QLZ=$7=bB?*5^5H<WWLx;=M$LSG*Q&Yd84bknEG
z-x`|j>o;<DJ!2-i^xDA8wPFy(ePg)uzIE#1zO`n4v2^mx=iWHvcsREQ;~wK*?l@Ko
zN~MC_qgMK@+=k|PXZk(Qn4b23^766b)47u>H|IE6Co*%_7R+VCeqL1^Q@vpnTg@?x
zZoxzQt@Y0jEsQ$1$F^Hv@Xwfy=_TvA3w}U9@}Q)Cj&qCl#Q~#dVE^WMe>z@NkByr{
zZ<y*;D;q<`{lP>J9YgcEIlt4Xcdb8E-WU|?b<ZizsG&LQ_qJ#KZ#n(;^ccMh3qPri
zz0`API?gvI;+ff8al)D5svN$5!zmt$zr)w|_s-Zt&q}jo5AYiM00rR(YELg2-3MyV
ztK!7@aCFWzzw-^3Z@;s|SO4i|+3Vi_vd6d22RrA~YZiYTntqdemaSXyc=)%YBaVL~
z<W+g@>ML1W0uZ=4bIIrHmR)Q4Cwt4#T36Z653L>8ZvRBJ$Qb1=cAH$K!4v#f(YaQ>
zERXZXD)RHcF8`t~k6jOG;mjprU$YOCwwepx`0YpTc9vdmKK5%Q4rT{u{)2LQFBsKZ
z=7M?S#MtlW&p$lUH~-gXw%Kp~&0NW&z~`>#y%KjB*G^pj?wESyy}`k*vg&=$9vpt6
z+&6xL7tTfN&F}oJ-1*WUoS6BE@#{wK*zqrzdgYR%F3`HmFOL8C=c}JHUY{QO@ksFG
z<0l@cQPZZ*?y2xbxKRF6XUsh`SNezM>A4-#W8d0oeb?x@99?{P{;v&u;lY>nFIbn$
z7mPQ#eBFp2Grq9BTwZT>T9?XIvT~aycf57hSp0$Mo|}AC?RAU=HTQ6@b6I_OcJZ9i
zTB~LboOt9y?ltcRe?#rK)g1qBzHGK;{=Ng1#SJ+6%z<w?z0+gGu2k#IpEI<4C-a;+
zU>N=0%#-w_92|6=t;Vf*>=*vJa%SvVr!xK<o79eD_JMDOJI))w@V3&;lH6(iNcmy)
zhwFYZTx-1E9QzSf{r>Cm*u>Y>+%vX6670BORH#@=oqO1{j;z^dzToV5?8Kvf=e%+^
zU-rLa>{FYJUM>Wkc=9_Kwc^l{FSk8grC!G<2d}F2-TB`S=8Rr{PCYcNbuBtG|61m`
z-~~^XH|1U}&jbtR*om3nP`qg7J@SW5f2_0D-#Koo8G8)W<I~*Wu@lA>&wa#MX?Awl
ztv~+fIrI7ngMWYE&5k>^{pQ+c>hbOBrbBMVTyN&DnQHvUNB7sw*QX!*@rb+0n5lj7
znN6MM@POMp;kZXbremB*KJdTu)9cN?+uaw9`3J48I2boRYjo_qY{vfkk?Kuxk;>3i
zaDI}pb$;OcrduVSL;{hXXuUpp?_U|!xT1`k$a2N&CrtZR=buam2UN~KP?9xx^Vi5s
zjD7c<IdkBbyW+3fwI?azd1MIrs~ESM!FcCG#;duR4j%tE8_UisF=uCtec$X#vHIVA
z#JOM$f3fqXGe%2(q&xprmHNToss6Ef*S2T=*J!@$HGAL}-Ay^$-#uq+_V0!vE2W<^
ztPS03)|-#|M=lyj@_s|@EA9N#*q;l}8CP=`L;6~KgI7x*M9xj;TIojT#nL`^r#oJE
z&#CpMMLO`e&mr(CekFF*>&@}y;SUYt)Q~-A#9a)amxg<<*>9q6JBG%8!&9%sm-CK4
z{_wfZnHm>~d0wlFLv6$3Rg)=%5TN__xXj=s>Yhtl_C30le@DT&{;4_FIZXA-L~%Sk
zTK|A+6YAln$9u=>Pd{8XeYztw$MA?-0#fI`@sIqAWg8`$xaiD$e#j{XPi)-UdBK>$
zpT9rhm>G@%KICtjEb1HF8?<_Jhc7F-=Qt^^7;r_`-6!AA8kd|Y4@G**kqKQi3LRPh
zfYH-LiIld_-0{Hg?n-68WN43!n+RHFPQ_iFE7L<yRPEle$F+UK+IsUB-Y(23vn!=N
zKCje>|9D!3zpy<jj@N%Nd@>(gcP|I?M%S9+D=EJiunC#6+L5yQCw4>=Prn~I#XoV5
z4UZYcV7yHI?>X)f-=cP=_sP+U&sr&WAeY`ZDRcGp-ju609RF`Ll)HPJ7Mk;UT6<Iu
zpkb}cR%6UYLTl)V*~&kl_BoHFGDCicWwlz|_+x(NW<2)ud-A=hu4C?}_8AZ5dHYAk
zj2+|Q<BubEUB{f1zjfe7r#}2ab>xxrD$LJ?z5c&1II7o}S657DSICz>9ZLMjoH2Yi
z7<R7KkNJ-q9%VA?j9S3xiVNfPU95~dpPSsFZ<T2)cS}_<Y0dqfy8HT>N{w44_LbLy
zD%LSHZ=c<j;vk+%#|KUOO3UyncB<t9`HGz#H{&3T=ZvmL9L79*Nb6!4SI0WE$5R!I
zm=|ua1{^#5qE*t?&ASM0kpc9j_o-_7YSfVlf7j86|6@3;jX1+y=S^R0Ri^c;PP66D
z20Ij=XkR__-LM!ege^CKWIU&S{wN=QN*Q{gqjIa68qh4Lu6V2ID!(UnYO&>UM#n4O
zihVU_*g)WOj`lq>wd_&iyH&NOQ;i2U+s)X}EA}tXnc1|h)p{w0+j-syM;FGM{^deC
zGZ6Nw#g~WXoXW|U{R3Wc&2;Kq+0Cp>2Q}cTr}ee;;D~-T@R}D4vSW6$nL4Mw@ZHa}
zxaP{Pyy2WO4wSuCoR1I1aUUdfUyFC~wBLHAM+G)3mp52coVL+Hygx7~<lpHaoAPXP
zOUqN4H4szURpqw)8-;l|yn(^W*~!2RpG}+jX4APAe8whBisCJPkAAg0;1^TtF8dBK
z<)CT(^<byt&mOYPd}o~crJwbA%OI%K)Vz6B-L~%j`No6(zkO`2+i$<(<G|g**X$eH
zFZ+k4UuzxpF8dSHug!ejyV%|RlLLP-qmE3(zx4+{w}rL5zT@%_=FIh{emW?QeSJ&*
zTxq^%&mZNRsQGRGFJ1->jJ)yM*`wYEzV+brYj1wtd-sWBUCH~r(Dg-mqs{$Y55~VW
z^mCi{n(rB>e!Anbf7dlO_<!+thc<+F-5%cLBHu-4zU}`9dAIHVqV^Xr2W#cc7}LAm
z6Y*;^PkD3Q>pgidz>mCD@zx@*2Xow#_mO$M?*E62GO@p~TSxhb|EHPp>W^n8Z6W1N
zf}JukR%70M>fOK65Nef-1>jnKG;~5f{s=l;LmN)H;UoIK17q>NuRY$eZ+y&Y{a`G{
zbHJhOKRerRhi8p$n@}{pujX?GWr%=ef32lKRaUqm>54lPq(goaoF#AW*;-bQ`9#}#
z>W5?^NyiDX&u9LB`=Rdq+gsZlC@jyg{odMbGgTP0yKBW}>9gld>mN9;84u>nuEEdF
zo|;gnR1?mzSyr0U7yOYIHD3wrZDtsH!|_|LV+=T7ZH}9{=JaFV@BaB{Z+UUxbf>fX
zPs6C{E#EPza;*L&IA(scW*=?Emj>LjTQ0_D-Qs!kh@*Q4{3EyaPrqOGAqTC#2i)3W
zv-hQPhv{}NIN#}}WWbTb1*Ta{^{%OTrnfl<*7d*r#%H!K8ks?RIu&OW6p4L)b8uop
z*|8T-r?l6|uGMt)stGw3HMR2Zsfyn*(ky3!&^wd&%J#vM@tQI;x2M#VA9Ixp6S4c^
z5IK}wxn};_cPuQz5DBr~W^0WdXpI5u%CPE-l}}LT>|XOw&`3ig&z1?Fd(#%gnQ?A>
zG)@nmsuK`DdH1vbl+bHXo6RrTLlb5kXJ>7-t>>KC{jHL<*6BOu{6v|bR;QYT;I7op
zxrHS!<1N~mbk;}@LGEg~X712R9DdH(?L^K&zv3>rH-ib+UCjIwbM)o&e(|j9h1;y6
zbEZ`OUf6s9X0bG}Gi9qvobH`>whx-7YjzgqEpwZdomsLP@T0KO=gb4WXZQE&|8P3%
zoTrf8{;qi{YMz{!osNt~D&80Gfv{<rr~9_qrw0eK@Vs#p$KCeM!_6!9?nUFI@yoG)
z*^2xTr{E6dA-o&o{;8C``;wc=oba2=HSa9^t@T{$$IJFiAqq^iWOvCouRu<zq4UA6
zfpBBf9ZDbc)y_-y8uP`#A<f`r^R6?%RTpm!rah%K+_IJZaIjPJ4<h(BQfgK@;^Jc8
z;5KjFq1fy?VA%(Qb^110yY2~-jF)$CRxT{_J6a8;pC;in)C~0OA@wc2kvjY!=F{=F
z_}l#2Xi8<$p4pglyt37mUhlkS1?o{-ndkB~<?U>`g-4u<9@vevR_;`k;E+(z8yC%;
z(@wsi|0j(3XzEon?(R5c{Do)q_nb;)jl<J3rPAWbrP68p?C^x~J=^rZ>nK%>&pT-P
z;NTWdUA1TJU1s^D@lR}farf-Np(VHc_ksqT-#Dh<U7zQmMz#~%-!e~?tjB)vL^#^&
zJg&~Vn!mdl`8#9Zz0`TV=CtPgT~2R(czu}nmcqvED)Kt$n$;!4E4Fm9)~)kqCxNCj
zF{61k^|hdP-p$_a`Tk8`A6>GGvmWtd5F0&%_Q{F(A^Syp)(8h*vwGfh?4DcPV^!|#
z>_`UA0SsFoJiqRGJZJXIdV{TzIJfBSa=O#~J?qpZ*U7zQs}&sPajzMppS=riYRIYn
ze%Ne2ydTc4l`}ea1sl6<duX<JYPxKDt=`CQ9q~^zo62meNImuqH8{L5*m9iIbjr)c
z4-EPZqQl%b=#!Ug&W+psW_Cv1-Ta7VZ?jv<tE7IV30yiHUonh^-nnRKl|d+e&6<u$
zy9m?b4Q_+7ZmC9KoQR$H(Dzj<8_mInsK)nQsds^AGe?}7w##ks|LTEZuX@6_zKf4V
zIHyZW^#*6lFqh7f%05soe5SEz?DRW&n<>SNVpIF4Up*LH8EEM7j9a!F!Qr^#=oxp`
z-i8UaA)j~`7sGtEGSM_MCsL#5{p>9>wOiNDIj8(Ip1id?1t&0+R<(7yW}iZ}Bb9N(
zlg(5^@d=t&*R(I~Z)Uz(J2{=&=9vzZb)yBBXgAaY0hvVY(O+t$T3Mq*X>e>qsmh7e
zK3^j}G0RfKSvBqGcEMAr7KDP6u6)yS5O;F-Y8ZEs%`F(hk!AdjAH$4OzNNXbjJm;E
zh$)lr9W9$e1NDO0!OArpooN02`UOd~t1POjwO~-YNn7(@!pmzh+560=jY_IBRhdbl
zsWuo&k54Pl83g5IZkdbbLBDZGJ)|sqe`sw87DKz%mEKKyt!_>?_3E;J(5ejoDC|u;
z-A>C09>@f?ZZ%p#toL2B&y=m)IJ;u^wZ=)Kk-HfFud<&uiAHSr-3k@&Sd4gjk(9|c
zZzeqig8dQILyj7UTk|TT9hr{U#EeKP&aXhd71CK^2jh%c8|AuXlX=P29C_QM%c)_i
zK(A$IRX(lu1cU2Vf;2hKnsQG&tk33F+N@>ggLAHiJzKZtpIu889DmT6HSs&PcG4FP
z^V9>q`pIC>!76Dj#GVD84*ct0DtpM#va@7SbkerDRMv5hnPy9+9u8+~FwItIn$>u~
znx24@sA;xO&VT5<dAhXCzf$UH=F{Q2uDW$#o!*$RcE*wAX-4qIfM*0&@A8B*P9ABe
z8dq1<2OEF;U~KiER+@H-w3I#E@y0YHx^FQa4dr^E;u)UVagcP@8B&Ydx0<@COq6b-
z8I$%HZ#LAdnO&q%X)RvS47`ftUaskYU&CqYwVYnlYWuvJHe-zF_SWfi-<-AO@aX`V
zv9uCQy{?r#N9EFF%#T+8DtT8F!mf4LGpUnC%}XJ1_Bkg;U>f?Vl*R^WTkO!%4*IP)
zkw%a-vZ*<)jb9GkhI_4MQO)sUs1^gQ&tLMjh-OO}=P~kY`jwhUF^@k%rOAq`BLz=3
zAx6!b^MzmRz-zR){7&bysdCXOC-jp@K^TXFvMXgYF3zN0H-ZlG-Z=_eOy3?#HJU~W
z!dchOZws>NzA&X73^emJ??^4mG{qvrC#*G|l|567H>d5O#)m6&-MDuJB09IM$T2lq
zEjPaV>%|Noma(0foOg#dtzvy9tx>#E>B!EKS3I%k(2~Ff$i<Zo3OEbtK0S+?A*i0V
zJ!rb;gVR=~>3=G3>6}k#6<Yeu=9rsZ@(zX>D=K(eUbXc60~7mH{GH&iMZHcri;85I
z1D8l(Nd<XjHDmqi-+!Q~&Q_e5eb$fxE~`qJS<~pSahpmjYf83Z$re3m_4jD1Wg`#M
zW{2l$8RPd=iuBpZ^ms$B4OClAMWRc6X-zSmoiuKmZjiEiti|x0Y4}EA**VzKtisBG
znX06WgH|TBE>+8>is|C8^537@su>lqoYBf0j<YFhO=>5iPIZdB2w8U<GaV}}JDnms
zOJ*Amdkjf9sh=|)vtb^nY3DQg&gq<<by{RXTIAd`4UD68xnmp6M+Sqe{)*9)&V19z
zKA;sr9NReT9b{6SdZ*GI78QTEA$;^w9GlM?uXJ`cuiMS?psILdGt(1suZo&8*IN4Y
zm|ZM+_?z<RqSG72>J_7PQjOVH`+}d4!R|hB#(pq9MKh4$OXR(~JIq%d$0IYhMS0IQ
z|Hy1UtS+2!`^~l1ru^s|hu1symO~E)yGN@3+&Vrn@Z9Jd1MA%@?#MLNhEE)t>z#8S
ztoHkpQ}y@Eo$D^|oN^b#;pnY(Z>oQuEBw1-t%>u~$L-)`P%4+W3A1<Hd9D0P=|F$y
z=B3Wfl(_bf)5kr&tHuY5Tq^YbmOr%mjn46SyB(kDAw06<!vE3qzg(N1m_7N1eaaZz
zY)$Lai=W+o*jVpv&reS;_L$y!Z!JXj)y=_w?9CNw&reS~i+17Dv3<}PWxB=L{*!UD
zxm30vG6$bG%gWw0w9%R_9Ugka2shC`b7sFYI`IcbX04&O?3IAyYsbA;gCSK`{k65$
z*|k>w9~o1@o2LJQ{h)g3J$LNk8(WS~{OH(KuikoX{EcN}fRidd>|!waH;-I0rlLP`
zg7X7~xnL{lz|DE}zvt3h-3!4_cmLJi8duNQ)BYs`w3-^+ZXXEOO~f&DbsR%wciSiC
z%n|wfF>Bq41<&zM2>0D!Q};uC+a2;SM0E08`%8zsR!DPaO!Wyx9XuH|ZMf;&V=&-V
zXRI~~d!6v)TX2EqezhS~`p;hW%idLZY-RqWe0fZr5x(11G0}9(dMJu25~}<b|MU^t
z&5M(FZ+~5z|Mvg+Gj><)nEfMq>B7OCxMRRPKXy{xu?J_q<~Vol-s)fG^P47S4t(=L
zv-tiAyY<jaFBIxuI?j%1AA0EZ_}U5MQfd6eAFk_K=)7c)oh-~7uMPh3mwiZY^Oe>}
zu<8Hi?QOu@xb8FGnIWtqsoRTlFn|srO2RoDLPO{i5Un7}7tUZn4JleCASz*6XG_40
z!)UjuDLcL1Zg-0_7+7EhRU}0v(l)tE(6p-Urj4a2O`50omZYSOa_d}6ioMm|ZJt`P
z()I4$-CDAeP50^U-WQV7Cf$!`?|trbA)5qA3@~%%eE$CL|2?G+WBjCb_X~{gbbfoc
zd+HOUzD8po>IF24JyJJ5B;Q{zyZfp<_xfK>P7Yt8-@FXdPkKj9k9^79Tm8o`om->y
zi~B!-?aFUlxMNz=?4Fc|mxbCqFp#CE(pA(TGI-(0(|kP?;9Dhq>`gG%{oNbfkCcCx
zKxLhdzs2P@fXS`l1@V#h{S?jLW$c8K83N|Lh_h7^TV<BI7kg()GuS^TixZx)(^+;(
z-&<;)YF^0omK50UQ3YIyLt?bR*d!*?<Ruy(f5m==jlWWp4z##s>-#?+wE^wk0k(X{
zj8{Ig{<eQ(a@u{G=0BPmwo2wNeDv(#=quQ)=%8IZo5~&K*n>5DR2?WB7W}T`?2O;f
z+3_D1oUIj5-f4M(0_s|c=a_e$SiNw7qX`t<-Ad&Rerw=42|X+>54dorwEzt0&_Dgv
zaO6A}t3Y9+%~(5{h<c%8<W&EX=v)(C8PRi~s_&t%D#C>#ZJ}YWb)^P&M&Ge>MOYQL
zN~eEbTx*tG8#j<$3E^wPTFey7>&4rqDf?6j9_!J@xZD34)r&tE1nj-?A1jsg3k0b9
z1fO=S;5)W1*l`xS&>N`I?*7-Bb1btnZk5k%wk}p1dY_Lf1EO6o5y7xoecX~|`k_i%
zKj3T?i{$0%3-$BPMdt_8|2kP=8^m$kDnw+;%~9mFHNx5^HcIx=4w_7NnXz_nT?djo
z-h*4;c{6G#To821J3C+=lb9>7OXH||+p?Yk6CY#^hK<5wpBG7K>Z8x{M)<Sq^~uMb
zMRI*Owa(oSjU4-)ZLPAG&SCsH^(#^-LSD>%NuK1R=RV-}*B_jHi44EcIj1GMjl5H-
zuodThbdmHfi{y1N;AEe1dhh?y^;(HM!)`VqUp{Xeu{J@43!_vNZo)BwyOm{)_oPp<
zhTQ@2iygJcn%xMSqvxzGQQWLo7Rga{<=;@h)C`g@l4VHs;FRjPkkXYhP|Mti4uF~)
zhdxiiOjA5jI*y7!#`cSBOMcB=rY-p<4ULpy>Cm=Sxz%0S6gwh#x%msG<;!1jjN^<T
z7Y9XIyIXKRAQEr#w)+^DM;sxHz6;f5w3X18KM;x#r9%-M8Anh?6%orQkwp=lI)_vn
zg{kfM89O^Vv$#8=&*(%%#yM|{k0dLK*xD7WYp;aT^1b$`)z<dO*h%=GnQ?$zF!Q3j
z1VkMdA#-^7=>&m`Jv&5~c%#gR#ldC_VUS+;Qv+Mwqe}gf^%@N|{?c*QlhNkz0Bv~J
z`M?omiBY=kIj2oF(GR$T3i8e+k+_9cz>?;@KRlzs+SJ#foq=^f35p?h>f;2(gG))5
zo2L+%7)4M^AWDGWPylSGielHB4{DX>PN?Gd%EsvB$5SGK&_Zyl6GZZlm>>Puy~aN2
z61Gon+}G=uCl7s1zLYJ(OoNZc7ORQU8B~dEWBfNiHP#7AoY_f(yFEQuw)=NYI*Dd*
z*X(&LB(8j8U(k+PXt8*aJ`0aQ)ZA^Q-t|-)EP<13vC=|cbn{uK|GDq|bYL!mlwfKY
z@s#Kk{wTqYDMsu)+QtUbK!_H^a936AJYT|fY!F(p&DraxEbYo2Ovj3!6Zsp}@aSa4
z9=$BhYi=nPL$oAzi@YRUv)edzot#bKyth`-TinGQ_h@_L(M9r2H5Ogoy>IoCTkbP<
zsq|68uKaJ#MF<KH$i%aZp-8Fu0Vly_qU&0@2f>Y+5%d`vcmDji(IOCpVKkW$x;<k+
zRv}P<KYf;C`oD^Gvt}o-HZoZ4f?Y5TC0%<oz;<QcP$(h)j+3tAHHjN7X)W!3oUNh{
zHV2m-R*=h;M8Q2Jm@J%qjJew<)0`});BgoXErICUdn;;|vjoWqR#(fFbYaT;xiw~r
ztyy6FWy1a-2=tL{(1<4GRkZblvhJN(m}ue{h52=uQDxfka8iKz2N<^bb+74jJqhg&
zhWU<w)bEXY0OcA+>Dg);YlZmL0NS|I(9<qLIr@gLZ+C2ZjV@cGo(2fM?wSaMvHb-{
z`{01owikw>h3PQxzNkJ5>ONa>@^ep#$UGO<j^r?WV_Y`kY{|kas^*FBb;V!%a0gyb
zKLFoV|MMLV{s1<A?#E#BG<is_35fL{gIssM12@An>mhH(lXro0hg$<zTdBY34mvda
zsgn;;`g8{GaJ2dv^5ZOh+fMP2TkjO_g6pk6M$;c0U-eHsr0IKZKIGqf9=y-tAK~x#
z&0qP0E12Ni{BI!n|95W!+MT{7|HF^d@4x+KGK|@~Mj{?0uX@mfP6=I>Nw6N&1AKe;
zKdglFI#xDDpYf72E=D1nlcYqU62rf4smn+)CixuGf<`FM>^bwY(vVHiSs{hM3jgYX
z<&oBN?-&1(rr|^X`hge!_aC(%fAvqk^zGJ$#d-qxrhc6P+}z}AEa9AH$qK2@*^8Z>
zGq6Ec?<EFissL^m=?rC_KH>LNj-^RRqPNXu>#Em~h1I>W=4~?1qI$g}yrk-7&!05y
zY<ji()6)(+U4kkyI_W%FksIRG#Nb<T-H~4Mx12OrS4^g)^bTh}IE>|(V|FitY`lSP
z?~&LN&yM$0{Dfb1x7E9Lj3t)JN7lcvwO-?royJVwHnv@2EYjrDB;4wPrwbW^l6OXA
zv4T1ZkswS9j&YI%2E|&uCE7F+PV4!A)U#xT1PDObJ!nr(t-j2c3)7B2Csm${HLJkq
zCq<BMU=r~dU38owHE-fpu)%Pa*Mh9fI@yV6|2n&-q{3RwS+YP!?fU(H*PHZxRDt}}
z9I36@EKmZ=Y&#GEa?U$SK*f947}!E2oI0IJG<Wx~BBto!9L>(MA-)Q|=X`fSYF#fg
zhrLw~ZLqwAvC#}#q>16JV#=t#K`xqkJs(<(yJ@}b*{#o6gVsfBVBnaQY+xXS{*vWi
zgbDhx*-}OU^nO1?xA8=9JN46X9h7B}ZnTqK(8HYu`NROEt|=uXYbwx4FT6-sYzF!0
zB}*z=h`OOhh$QuyD$TYGNMUS*7wW1m9AZ}dVIxY(+!WdO(xlw<c&eDm$l^JkP4Zs#
zl01eOBS<c<LUUU4FOKk4dZc{JQRX<X$*#<d<@o*}59TwqlNP8_O@I5=;}HvtI%3JU
ze7!iOhGb9<0y~S00Nl{j_)w(Trs?yxuC<J~*W-neMpWneOkv75v1lfHa*PBC8WsyP
zTtT!HL_>9Q&eAqnSRlKVG%p7$W@Khvo(y5*gKt{i8^tABH63IZI2uDyvRr(bI_m{%
z8T4i5Uva>EQq4ya)>-TAvmb$sw1c)jk&8_E>e3u*LCmi{FK6`ie*C6t(;WKe)>DqH
zCVU*M@4{`rbbGZNsF}Gw`HC)EhE3HmF47W_hVKL!JE-@n^ANl}Mb@vG8>}jw>xuKv
z@!^AU`R$TBHuR=+{?fE_BV5}0_{qom_qg_(>M|skTa=Mrb{_ZK@pRjqxxifB*QT}I
zGU%^}MM?gaJ>Iirsj#2#@Dl5`%AE7|a8b){p*vU>ir#D9yp3o3RPl8839^<sd5id$
z9*dqN@iXtYvr&|1#UFYK*D6v!gjADv@+dblyT9Zm?=mYfPh7RfeT#BlQ5wQzJJ_xP
z+x{Ih{(R<KU(8;xyTuaSlbDqJZ}DqGT)txM=Ubh4bJ{xNF-Gh4z-(iBB(L_iGCUd>
zIgQc{vM!b^&JZTB=q&f_oClTsi;#6H-qrid_l*^5H<oE6v<qonwgzcAA_QT;aPSYX
z5&=Ox5N&PVZd8P-alXWRj9E))vjc#5IwY?%$ZQ}s!W&SFTN9i{q1_J*56Mn5W*AC+
zz)ZvzHK!HI1xe6nd#WSFHfkY(ic#x?eqN;F#Oq<WryE)cy)vT>7yC2D#-Tjz&Oi=L
zdvrEKa%Mb~G$1*~Btrvj+=Z`d7D13mxTen-(x!bOC<7qxzU}L7Eff!)^4*AUw7|Nw
zmCO{~Wv4PM>gWQzr>~=f7G0i3Qnq6Y;|<VK?4x@B`O6a$9NUCmRH^)<h+ZIsGg02a
zBdZ+53S3K2Ek`ijsUaw(xiu1shohKMXe|nfyyJ$n`Xf*X;4h(wUb`iQ(9N3C5v9|#
zxG-w?$fOFP9FQwgLjl%$jVe(2-QzheYKSB#afF58b;tCq7FQ5IPZO-+V_`^&(fwoC
z!^?tz#`OuRmF)Z+R&Lq6z6-dHW$kT>Rs%q&qHoQKYrNM90oh1fYW>D0i}Rp=A!BV6
z?g9D?cj&5!8J1<$qC%fVE<ic9hTw-C@~myDv_!2bva=l8V{^kKLAMi*bIhGUzVqY2
zZ2^WwMv%>8L$52tE+&Hj*y#22JPUkZU$Lo(xM8jB^q78Gq>L{CC`OPUJIIw2>Ya0(
zJtBxDx&~u{T!4<AE>LM#w0;$u>2UH|Xjj#QcG|%W8uphhE&B_<@t&wrmlc(az6W`2
z!Q9KBoq@aF*Sa${L1bVRe2)rH=A;Z`WM?yafH*mn*dfgQR(c?_*k$J&r*@J@0!tyt
zttGhwBAV8{QXH0zY?tgoo$FpBtY(0pU*K1eHW)7`T$YwJXk$rQZ(s1td<EKTSC0yL
z+QMh)W;WR?!zoWrQqtXv4QnGAuFME>t`?NogS#AOx`_obi{g%6lXKmW{bn`0Gp(@e
zgYRvHxKp$0#-eFQau}|CVJZ&rU9grYRMa&q6jzhT^u^1Q`X=c-OrzrI`_H})bQggc
zTQecFms&xOkg$g2E{srd63SaX^>hspYSQ42I>L03S5J}b<%AInM*xajRMdkI;So6}
zBf%cwK?JfbgwmiheL>*sHupGu*!ri-sT-EwYa(mze7T%>aRJGKhSobKoGHkX#dD5<
zeq8&ALXR8-C@PmiG?4P_EYa#d(v9runjN4<BNBiiI;a`ij84JFYt9Gl%cCCb60!U#
zC?`yQ$Jr*2*v1z^9ri9}2~R8MwwN<hblK@Ptk|GasEQSf4;wWU5Z3TmHi@3Vpic{o
z5965Xv0)x+sVibUx$Zv~Q1oakv$=f#9Fk!>N(NL;G%SS6d?Uzny;d!0LtPj@Bk#fV
zfojEY&6i^U#5I2F1wC?=*t6x2B3kA=sYe3ha>~b;wn&3Pw^M!4hB4`h=-L}3gh&gz
zB+OCxiol7z{SSXJuY8{237_6%&|j4hJ6Pc>c5I3+(!8#AS$6k4Ur6eZj+rU7){jl;
zaO2{VxXlXEpHyMSSm7+dTmbryn%+qXq+XB=@C^K1F)tfXcK8+zZIZT_z*}yTSs{?5
z!P=adc`k9>XGk(+M^qOQ&zuu~?&!+gXfsT0!pP!y6k!J@S2O5th_;9oG6M8d=tcu1
zav>fhBsewgL9#Xtq7G~Nc$HamrhMBYD~DAJa~5=#$z{2V;zPP$aAYv)I7ryz=#jl7
z!X5_VrGx%D^J!hx^xnXM{JwVmPk+`vNzQbCLGfsXwz6cSSy=4}TGy4suA5{o)?JOJ
zY}hz2WKPaydP=fUQgHR^-oTHNg@up#3tzZRZm9EYt%rWRGS@gCb3RSKNk*QEZs1SM
z&-I_0qzjwXJahN?j}tKiZYs#l#AUDd={-B(LN<JqKTe&$ZQ0vF!qfUDYpb(^rtdzT
z*!E}fImiCU+Nr|dGk;V5J=y(EZ#jCwYR9|h<;VC&`U%>tf@0O&R5>n9Ge^4b_R@_`
z^mETbB|caBLTGr64&P4Q>bt#MUn?ihT7SCL$etvhp4&5RR%o<JpCDxgk%&bW`uF+B
z6j0G4_O1C_l+W{-3p~>g`>8K1!3?iE^ZtV*6I)QRn`T*kr|Mr)8OW%60+YT<<_WI!
zy1B+m(PwkhWXj*PZKHXV>}j-V>)C3C9bhwAIrvn3d!lE${J+O`5_e#FJ2n+;^Zopd
zl=}BB`#@n!?3w2;6z54|InI9W1{L2I)Y<Yr=fLjx5*1sl=dA-|%f+7Oysz+EIP)EJ
zM`7EY%yN7^$o2Q=MRv!k4~P#t8{%6FFW%`h4$#N{q$3wU0sLK@<467D_?Fo-epLdd
zHon-`f!+`G;`lmkj<bzWf2%8Vd~ZcAKz}gJ#?0=juO1xaK_}Lj>w_Mu#6FJ2<@l2i
zzP@`5oNH*@eV|N-vbzK@e|<M(U-daGt$AtuLr)#%I+*)I@%Js&`QyU{D!x6`j927#
zXG7mZ&3N`2=I)6y`%o2YT8PHW502a0Cfnr(Yws<!>I@^*kU+@RA^V-<UcL0wl%%dV
z0Zk7*mw`UDF+R2-OJ9H9a<4bb-~NTND4+X$K>9&cVsF7a?dU`GH#pIEVFbhux&WBR
z?QgCgnk1cKIy44>^g$&6rVpN3jGkyu%ew&a60gU5Es<B7rMVq#sC~b?gCB#+6ZFdY
z4~0VdwPyL;N30Ma{<$qr?~JMP7kB>h^8dVvI<fQFJG?~R7vFpL3yH_xsa)xR-Ns)C
zd5px5K!zB#D%dS#^0E8at+m9l4-0vTH2&zRt)JbNk?Sc40NrA4o!tA*0^NP*qrVFr
zxV59!{>XA*;eCb|<g0^5eyE~weurYWe51JByNS8QQ1JR^`$B;U3ysDtipb|%9iVxr
z*e3g=DUPad_dqb3A0K-=2NHwRBl+;5Mu$89$G$$cdg}Li=her3J@(H@xp|bo&+G+8
z-s<Azr*2OM`s@E<{qG%l5tpBSlb3dHl-Z;0$F4^aaXmh?;c03eC}h$`-y{(ucMC-m
zg4bSN`u*5aln#Obvd4}*)y~q#?sADx_q^EKJMGYWcCPX37t8mzK9MBydJ_Q(`QTO_
zBJ|3*+bM3u2hiZofUP&iRmTLc5#GoXfQmolT!Uuzd2_57o3_32u|!8AA4ZS^I{DEi
z!CmVe9mC<f6&RO(=o18<P@u!5=JICqenHNZn;Q#TT@>Ko`Q*}}(f@Vxo{QBN$=e9D
z+~RkoTpv%|;&bw`_U;qyyPmhxv?~0u^Mz$x%(6h>q3{0g48)_>02JagkDYgZfO>Ww
z>u3tZn%P9j0SVkFmj=_fk>{|CaKJk(aljeAIK6I{notQHO8(IzfiMJ`_pz~rDxHqC
z5$s@a!D^CJn~ow<Qgmg8J#H3@vJ>%YXElH`lE?G3Q9R_b;8b@zN?$)jSZAO5T`cyj
zl;h`OZFg_!PT`{S5_$cP#9`wZuACdYUn4^AJ0kgw=JkJQDtX(Q1plVejKHStBSg0j
zI4ob<EgD`Mx^_YpwCTeZ*SAil1#Z*Q?h}g8d%wOOBJ_^hok0oQ2yZ6(l}8iUroFuz
z_htuwnUzk%2&mi)AZy2M`1>5L=b;$!ScM+-1A+^@@?>Y{>r;Qhq5p$PVIK#UFaFz3
zx`VP2=PGW4cvgEGyBI7u$8GC<1AxYe$Mi#o``O=mHa`~ItM_G7i7Z2dlIibEm9R_6
zGI7^i(2mEkxvFvK-yf_XD`YF7)^H~`1D}~qkat8SZDiJ)iLS`fZmZuCw?N;$ojpH;
zlkbG2#Bn4M;y#WPLkPTqTL%qp#K#$;8%*Jfj6+CFi&fN&oa1($000*QG@fFcBhtb9
z^5Z={pqf!=i#u`YP9Uy#z&Yw)+kKxS=+l>K6YCd_AYmT`kYATZk_Pz*z;*oQz{P^4
z|B_|CD4uaH@+C1@I#AO3vXl<QUPM*};JGg^JcWD&(so2bb}|z(j(wa(?m3lL-~3qs
zXb7v@B662NKn=`FNPBmHa13%MWP7)2oD;T+ZPX(rRGMkdopF+$w~Ha%fj7!Vq%FYC
zPyd3mBt{it372DS4%4)k*?Cs6J|y!nH!qNJR}L?e$<L&=?q<d3`d*5%U$UN?3<N1h
z(+4MGCNI0OuR^gpcn2+0e)0#^O73mP;WWlB2*ZRvI##AyX0y4>wc%x9d0WvCF3|%H
z-}&iB1I(XmQ4bfO%v?f(a%&ybPV9udDeWZ@TtQNTr$@rwm|d9@eqI@KGFc+qC+$&_
zq`OAKViRkO5f&gum5@g;zv{bz2yt=j(C}IEc1l#K{7?~D8c(}o<%LeyAs;Vl#qmKc
z^0{7CG-06wzz!L^rOg)7PzhXf&bdMx4xA~=7Fg~7`SuVXRMw`YSv&5jH=*=K)E`=w
z7CPgsR(p}W!XAM~bX5^?4E>T2!6Ik*b|xYFm$(YHyNNj#)Sgnu)sQ&PWO(lyI6OPa
z7NO9X6>OAt*LC@GT<<?iCM-L>%0^n^5?iU@S<Odfsy!u(%UrC;aauFySwyr6Hel>s
z4Wegx{G2;1@P22b34Qop@$(Z+lQ69tK^VRV;(Uan(|TjBkRNB=enmZr2zh{^e?mnd
z1vOEkc~bE~;lUoX#@wewey&f@5yr7#e<(B$?O?OcFhc0B4J=#v*Th+>^)FM(o&3$}
zwg9?vEq)U+b9OCtQDTOkC0T&>QTBcVp#6dN+_+YLR0P`s0qukppc6FjW`7$(b71lR
zVWBxFJLV@prs>9P<gYc|4-xwhq00the|F#j8sF?r4?JY-CK&r)K(9V+{sbI<!0I=<
z7p%MFp<;dh?n6djo&OPI{|Sxx+4%Z*HRhoG9lbi(Jt+Ha`d<;5zk5RC51Iepkk4<L
zdMH)@FIfFU%>H8{b7<h7I+KKaDS&cn+zS-Ghh2$(Sao2EuVX0<vzV~d+<fT4@35+h
zgwUL@q#^-QZnXfs6hA}muR&eZS!!tx4h5E6hepS-Q4Dx9-Y6e_Vy0uVk`H(O`qz)n
zQsT!S_!+N$@PFsmShqcV$ala0)i?3>>rX7!BW{z<*=m&`hze$1%2B%)BGUp~Ag&Sy
zDOnD1sxO=a=G@9vE1PQxCujF8aaJdGMeb8ifE6)!q!$a=^?p6Wwm`yQi^6xLGUDMq
z-fxsYc;;)^?hI|lW3)i+zOR{nm#C{}$vG?$Dnq?LHS}0U?C0(gHggmk#Mq|S>MAEL
zdORcmYhUET%O#dfugC9#cqy&!1YhxdC2rjRX|z2x1CvICU&E?%_OF!SEKlpm`ZBUL
z-wAi<IeG^r>(Qpe##z0iNzv4CD<9frLGM-u{)!%>B7uD)kX9RKQ@tm6Xu(v0t;NHO
zCXk>T3FalZc6L~2=}<0Z3BwUX>t@=BN^SCRMLgNY9rDJhGlfD)`g&Ty`oj~izV==X
zL`|i_IYyH@{9I_b+W^#G$hNpdgd1A6x}NNs>4HoPi*ck~uMX_7ZYjaBPmRbAFo15X
zHlYMd#=T(P{3qr8fTly=QwyyB#_$DCPglU*M4eaEXPD?24E(vtsB#`1XFJskH-y`?
ze14vWShCt1eZ&=ji=rF#!X{dE=7poqt)^}x<i}=Np}LlZp2%p)Tu)BGB*X9JhOpzO
znU)IEL0ydKi&Wd>nFYO0!ZUM3qtVs($EA%t13Sv8*W|l1rgn_B^Wm4-5-;e<IR<5&
zTE!I@X3re&>EpX|DHXDJm@DIfZA)h;%Z9t0WX7YzLWhXVNw1o;rmT9(K&88(xc;XD
zKigq7JD81I)`Dy!sf;s<*pf{tpfgdQ=5~c>5&(OZEyTmMRU2oE@W6grKM3il(&9GJ
zRZ>u$j(T1+M7)_o#npn#8(=3gA&>LA;p`$xK&d|OCehB4>sGv^zY0wsTbat*t<^q+
zI5p^LYa(b%L@AtIlV1A%H~toaC>0;Y)0+R_KA+Lni*zQ#=qvT7<{$~TXVzG~3j<B7
zciNuIA<;Z}!>cHkB4MYy%>%R$7VJ^G?K9WSD5mzffhYUTI`!-~Dfji{z)=1@t&^Ey
zr3YwjENR`whm~gx)pL>`jrG*e@=bhLho@&y^z3<S{AgjOT}BAx=$5Z|Um=FrWHS$c
z)oaTG2@8Vn=W}tp@AnRb)4XKvV0&^r;+=*Lt%F8@(vQ)XdyFqE0hP^sg;hzk7pRLg
zU*r=7M2Fz0q0JP+Y;_}}`}rPkMo+BuWIz6tYOHocQD<l4ZAdR}%~k7l=bZJp{iUx=
zRqCxdb{Wt&-ux8!PfSF0WTo`<w#z4oILmFBdd=fj5Z~r6Sc~QeziiF|B21CThZuFM
zJ?H7dK#yAE<wf%_m=tAuY@qFrZ2TFmg!2^&f=5UoJ1{D(0~B?0T?4<4gd8+9t)?gS
zcvBc@R6NlLJ*g|aRujO`=)0nW?$z-$c|V{~jmM!etm}ws`>rmIM)L~;RWA~HLw2Z3
zvW*x>NE0Uflpvc9^rV8a&iJKo{4BJ}22sctSz(dzo+dp#U=rE`BAL={lT0X~(Ugrb
z*+8?=^7@D>pgz)w9YyYiUYDKA5r`1v?Ril%q!}dVz%23RT?3s2gc;sJLL%1uoEOwA
zLq&{DL$anjbZZ&C!&ud3X-jqOLXg7V`Om^>8D6nb%_y!x2g65$2<)VxYywfe4xElR
zL!(t%BSiBax)DUy!8dDw=~`S@0gh@w@{QIM(&8bUOI)w{fj+d%ae*kaS=TA7dNal-
zOLK@g<6%seae5)`&wn`R6Bk@KjHDO@4}pn0+a@TxWuU8L`6dUn#BkVgQ=0{{PlfDj
z$^gG?Oe)O7B!PAle@^%$G#Dn1+|}dZC0ej(2HiS*hp?etu!bv128};c%Z`H~aE^Eq
zrm&tfo(SNDq(bfpe2PTv-qLp=kPf3TMMs9J5OJvKY?epBb?Z{{r{-pi)+$G1kdX1|
z_?rgS-;xrl;XI<mf}(}#GlBaT$f;N*i;jmQ{ZK5V?RSu$A-bNR&zbs=x)EG<^UJiz
zF82&!4TzAM=XL{FYDi#-hbSF3oOEc#b+=pH_y2hN3IHMzqA^E~b8MMJQQQmN;5>0u
zR+FFx%{cEtCES7KJW^t~jykFkj?hvw8AwMkB~VFyBjUa&#FlItD1a$MZ?ql}(zG(E
zJsn@j5l7pAs^Os!kkr6y2GDKIp9h!3CEB&neo7y^_wNeYwq8C@FvCDKh#-m!jj(Rd
zDKZ0Rji7~^lObmSCba-gI>_s0-KZNPubd`vZwAh3o9wBOkNXQ|{#S`BugcEd*QiAN
z7Vl^}FhDTv?(?AhDU@}{Yv{?#rJ8dm=ByGAc8~{%=Oq<X&DORM{k7dA&S}8|jUvpr
zs}rZhNkL$bh>wOkLp)4_A&jc&ol>PCr8J535Y2_l$u{I)*ldLB0=v|)f?st#&DH7{
zWc*4!$wOKrSl8`i@&vIvSo8#vNz0K?lB2uOq&r22-21~{Op=?np;X<M7_5vyp(^{_
z2`6!`3PS5nsjFaAVeW=`Q#a~V{?X3JThnu>tHQ29Fn}OzK2%o0E(`Os6_hd}P<eL%
z`J*g3XL$^Lu$V%<k{XWlUr>+Wd={;pXS%dn28E2unY^wlzCgfgmA4QOMGLJNq)zlv
zj5xdclc*h$3^BD6RECwv!wAa_Fn<|8V7ZtexK5|OXm)bRN<I?Fxl!{GSwqKEahU5#
zgfbq{o>T@tQr3b_<Hu)9?QQEnn;$Hj#Z}m+NLeA+TuEa+*C85`Lvwb1mDIb?e-Uj3
zmQn=nGu;lPA~hYeA23^;(mkDtY2N0zErZQa(vW#wA#9MOR!HknRCVR2Xm^FiugDlW
zQrHb~R7%p*6{*nt9AP9y_<SXWL07Xc(ePgL2OBqODl77U@(>*)v0e<cAgQaD`+>Q!
zzt0Ls&u+%U6G#r%dJ0(2C54Z83#k=I(`iC<Pf%fS_aY3j8U+ulH%dlLf4Op=Tb&ah
zZaaYYlN4dl+3uRq;kpLLOtfbUGoOgT{xJ44JL%ocqUXYf>dE8$C_Mx3k(1v+;CYYd
zo$l_bL}Sm}narmCxs5D7ZQmvKrvCU<#1=5&RjZj)E<+Fiol8w&&e7e1v;&uT`u#me
z*!6`=thGBAmCutW)%rR?a@dR1j@?oIn`*6llfC2P-Oj=X&54D)_ru4$`fZs43Ac8P
z%iKZC9zQG(-X`}f+5OzWzoO*#V;A|D`SX>h$t!aBQYrmOq=uOX$a*J=g$(%tvCQbL
zIR7*Ayj&{{-!<h12{#kxrOJ-69qx(2Id`YLC)_Qc{m=iPi+#DWW^cDQ`-l*P?W44H
zd#;Kc!Er|Fm`|lJf|1Qi+)_8xB@+L7_YJnze}c9V=spi$EOKVvPObL$WRO}}*Uex9
z{e*pjR!FKsyD5&Y_^`{1Kc5>I*z<Ku&OxAlz~1a;+}05@XYai)EzdF4vBI(V0ful*
zDQ*3peX+vD`O0+V4xQW={ee~5K!4uaEUO>G60bNvUCc~>{FmiL-q&||?BqoPQ6XR8
z(P}yR%b8`lxp<*6m)Q{S7JXaJ%H-4kbnu^klpZjj=zo-c@;AZIr<n&?x_z3Nuv}?`
zI|%&@$9nXy5c*z_)4%!^T>Ux-9m3KMK{vanbBGuNp#SIyU>`<0@COU>Y1Y%afQ3!~
zS;7f5=R$mb+?2yl`Ewq`&CRL9ItEpBvA6`c44AA$<FA>(=lHhpfTH84l2|hzmm40-
z){x|h4>^nkZ@!nWc5wNFui$GQROj&p7s$M0>+*9K{@J66QhYP)HQoWMTm}6OKs%4o
zQ}%7xr<6~diG%i_eIXn7&WXKWX_aOkNY76VwFP^lV@(kdY(;AWKfSA2$Lqgnrpxxn
z768=gXW97cMg7&8Qgd_pw;{eQeHVL`A<420;&Z)uom>Pp8!dv;U;T`0o=^v`j=bPj
zFYmCnRsnJTU{ZW#0dh|FOS_+tcZ-jIMjq>ZLT2QK)ZR-y@RXSJi@)l=^s&7M8|gdb
zrOct<=S!d3mT^0udzO66J$$xzf48~$qdVqIdHDD2+w!jKd63xN9mKvcBma}t_xDAI
zl#@&bZVG$fR9!G&X+WT=H&!_$!i{O(j^gHa>jCcOvFxY<N`vVIJY|}Ia3|`9mMDGe
z&`V<UCTJOfo?CW+F0Pa=ktbG5-3STnj=KQT#~HB9hdFegW7u`O`TARKDDM3m95d?e
zuwG_z!D4{ZgYDf{o_un{WcoX9NyWgsU&RR*H+)Kc+bn){`j49>Z=XB-eN?UQTh{Y5
z216R$%<k9R<=v12A8^?w6IV?46TE6U`u5=9uiU%0T9dbMV`aD-^cAY?do}|KM`df`
zE_5|=JQ3}HO)*2xL1WvD;anF1M^VGaAz}r*ViNQ@3<f&>z-HoC`(XPz^b&G|fO6&d
zD?LlS`y^^h{W_HDpF!Iw2gUD`5_Sqolv?}6XmeHCN)`~CU~fyAxPJBSP;rpoLg|?Z
zI+*STM>U=+-k+8y>Lu@SH-W2r4SO#%<oElmgmJBSwl{&WM?A4=9&it*oM1uP?0}Pb
zVw(|>fZrtQgk$Qq0_1E-NN>gHjERywoq_=cgyS8u1p<g#OuPyOs-4b_H<N902$#9H
zxAX-d+=I<S=CY{kQP^LMjo=p$_on@d+H5Ys*JG@h(6JE=gvejFmJmM(hJ-VY>tdtL
z=&~rFI;CHjGmAvMWA;2@E<YU<n|I8k2LoqVU)@aoJ_6g5?6ooLY<5NBzRsKb-NP>s
zYk5+{v(5%_!s?3CHz_b?>@Md){w~kV90cDFVsi*bmu3+8YMy$FLL?p=YVVE=aii00
z5Q@RQu_NSs?qE}6htLp5Pj{*u5)8&;a6tN3)cCgfdSfXwgloC2-b5%UO~d4E+rIL3
zH*{1jpc0I;{bG^y+@I`2^yp>jUobNx2jt#4bMP^__au{>X^MVOZjS#}cGVk?JkQ%O
zzri`emB!go0bmBYC9JUgbozo>a)&Q6#C-<)|Ey|Q9D`N_IpZYpCfIj^j3ad*%@OX;
zXE>!X!X4O!ApZeh_zda+5W8un4UM{oLRzO8K>_^;LnMGts2E-t52Y{IC)pG3vIvS}
zW4MS$D>OPJJGJ#oxP()$Ozst>=6Z_i{~A!Wd#D6N{wH#b<R3k}BrX@1Wq#bX>1Z*n
zBd`G1MYT*Q80l?Ua^I-8$tN#X@9ng-7$yj2Ckdm~rQzfZ^kz_Boaa8OZqQ-qXE?;_
z8w3{5=lQ%Hk>_ng%YVYPBZtN!<HbXL1ksGQdrTx0MISd~`mtVi=&PKvF@n8zQ0Ry5
z^1ih3`rqw)ME&u?zOlXKX5%e0C^tX9@EN?y9BqD^%}O-5ad!hn*Yl+79cNcchZ4P|
zSTU%Vil1=z`lMo_4($V9k(%w!R=;+uBM`u(Rtf5<u0|Wvoc=&JHy{B5RQZ;Y%GiW)
zXALft3i9f-fkoh$tBw7dV;Q4|V9v6U=ff#pRWXEZvuL5IRpugQ6uDgNHVz$f_jbMh
zU1weJ-N)UuxPJBP($`M}cj#H%3EggtwB1&z3GeUmF`K?tv<&wbT|ser$<?5HSwOIF
zT!u<3eebQWO{m5?`xwzw9Bkgss|&28klZ3qJ9{1Wo?UEXD+MTs%{W<juh0S6Ypb~c
zVVTBPIcCvk23dT3NV1t#Or48i7Vilk%gn$Y$9}fQTV5|FOz;CcvClhQ#abhjt6%rt
zLaxH(Yu&+hn1QA*vv0{@9)}?oYOA7(dNv@$%c--ybk^D{6!^QT<u2FEDVe-?ra$k&
zlm!WlOHiW|#2{=6HXfMoUk4@*7Ty%d{OcA~4CPh7F0oF)%QQ2mNlXFU_rpn%8&96*
zNNyIG2(cQ((y%i{aVW=Ia7BJ$P;>WNVx_T2DPD3_MlGY~U0)VsMGgx|cnF`i()q)a
ze;|e74I6=HgS9VPk8ia8h9v!{{H4r)-??Nv&g*v${+0d7e;bwm_w7%9g17&Khssaz
z_Ww`b<XvdL!QA)I&t(v>{(;HN-+=ZonX&J<4@_q8{h`T>eP`@;RvOv^JPv%<q2v$z
z)RAAR;H=(Z-gvxAwgWtghXbfrAW`4N7NRiQK{Cg~Lm*THOv3>+tniZHgh>VV7zwSI
zGO0+YrfW$h10C+p#>l;Ye)GZmTKKB?gQtJ>MgHj7yT6B(?8Dz+#e+u@OQ_Cz7yJls
z`QWhv1R}JzfBnoNW$ZGfy$%c*$T>(n;RMlrQq;RzxBOK>E!852RmAoSc88S5!V9zP
zTF^UfGVkBa!Q<o;3|S3@D&kBB8Mr1X*=#~l)(Sr7jRq>e;MCm9BOBcr`9X7J9*WK9
z3hqqtFFf;!pd$A>IhNZ5EETG4ae@KpwR9M#T#$P1agO9paElG`-gyX91JU~;xA#DW
z^Y-E20<xOn($3oGb0IO+XdU#3=il;`(6{oLlHbB&8RTH1PGDsKO|h;ma?!f&D{9oL
zGJZI^$>zazmE=mP(4bAtCQ-iBg9A`70t3l_#m>ovxNWuJrrfv0hm_%fK6!Clgs>R%
zlD7!uYdn36&Vkk>MY}H{mUvCvJ^bdb0f0Z7#=|)!a2iNxULk+*BCiwZ-})i=&T1+N
zqv#bo5+->&v#oVKm}5ou9<#{FWr%ZTxbJvD1$F=(cV(rjuw<}BU&^XtS1QvDQeQOP
z%27EgKOL&Ay5Eu}stETS&4H$KoDO%@Zi9vlEyoLwxycZCmN#o_d8=*O-+U?Qmu(vo
zUFQ|{^0tnFLmvHgB+!#tmZSYq@6nnuM8dX^HC?%=F+hC=U^0hzAE9Smb8Bk|P8Q6z
zgN$wP6^sfr5<bQq(5hr_yD}vbsnC8@J8)R-8QN3=#cSBLUgH(zi#co7^rrd+82hh%
z_E8rIk)51s+DIpghg^ZA-+|~n7G1Ws0ga(fLoi||2;nqUSCWQhlJhwtCmgf}42fX{
z1u!BuQA8G2yqZrJ?4ziTH5id3jZ_oy`H<OImP3eNgcvf|lX_}Oux$of0KyOP=IubA
zXsB91!d}Zr_Py@&`{u`MOMF(~?kDHj%W$}$S4}ZQD^8D4^A;qaGs?jDFyiPl(~#x&
zLNZ8QTtk!_BV9l{bzkoxsFJ%7Ll%T9x-exAy63G)W!BcAtZG8SW@k3n6D-M1m{jxe
zVR&FYzsX&6@;J9+bc<hevkZ5lRu@?hvce!3_UGA<|5~7|i`mKE+~5y?W$#2ZVO8pq
zsfKj{-Z9WZE0p$VBbQvoz`^!h<=qz;4GAqNzrL*^<KZDE(2r6@B|<8zHnK|Aud#1Z
zxz9g|^RZ5p$rSl`^m1lDhk7ix5Bjv=PYkHchjniw>dFjqx@{+}mU#C%cFntVB-w@m
zNk9YSpra<N<?55bb!^<8sq1u;otUp;|BL`Zk41ir(@R_Cy;pzZr_5lsUkhZX3(~Gh
zusW#Rb(@$l%+t{uZQv^`AEHoBCJhAlCVaOr4<-#Edw^{Xwfs3cDo2O3031g}nkPFE
zj2EpWH?}<jF)PSU1L(5T#I-VTXGOj28rmBQLU)z8%<@0{axBR)m$5ofIjzSL;hOT%
zpP*tQL;~fuw%SoYqQA8Rn7#F^VwV&_LT;YPW+&JZHQSJA*2E+XEMWNW<P8U&Oc^bz
zYk$OrHU&<PkeDHIR&vgRgOrBS@a!aj>20TtcZYd#Vcpw3n-~4WfC+?bYjau+Z4YIE
ztTB*&A#lYj1K{^)?gEVx4dPm-GeS3QYErbKuGEWYMySbJkMH{!@HM;z5EN=3O0-~w
zlARC&0tncg7f5`W)&gtJu8I4<*{Gc+{ebx$0uIx1V!9a<i4xGN17@)qAKiKCvaQmR
zU9~hZ;oA)KPZM^*h#ICc#SSEH;Ikt|B=N*ULj!IkR5FJ`LnloMk$p&|LIq>L18=O>
zlDR^?+5+9>M8qkFS$W^|LdT(BNE)uky|_>P;B{}E{q_%kdjb%j6BZhxA;c|QlgJgW
zQIj4mWzBp)34?)~;au=7fig-GBq5lX?L4SFD==D0ick&ZJ%oFaa_1z5)IiiM{FKza
z*1B5EaTn;zX%6)(k5E5@9M=`r8?xA_*Vp9G)Cl-EnBEW1{zfuur@BMk&Z<?S@l^{a
z(lTHrW0(`@)HKQL2~b;rH_atOox6qA!!c^2^6B{yencwSn3)VEKkH>AMA=BI@RF&l
zTMH#X|1~Jp15__f0g=G(Ll?^1;VCh!I~{UrDX;wHfB7?T$BwbUQ2EeI)?~A=)G}6a
zYYj@Fw#tY1a|&uagm`rj37;{{gu{)_W-MqXNJVf&&6FEgF*V1B8J*6!)+HS{^*fQ~
zpa^+d4asba+|x$7;ElVLa$&PNwhC6Rksq_I6GtBT4XCeC#ag{a2Vc9X5UxvfK3LJz
zwkjm9UO1>366ZkU7V2AGhseWC8W`~qp-AE*R6Z==uU*yh853ELm|TlNWJltQYdkF+
zqhTxqj4BKD)7l244)h(gd+EL3`cGPfsw|TP@97r92yy7^RZTx=e9?^P;N}6YM#l$h
z+6b<dnHpM2En_3w0{!U2{ac`AhD6)hM?81M(vF$gpsLY)*7OjP!sX<JG=z(-dr%I7
zp|rL+PDncuUH3BA(bLqai9nHCQ+j?x8Cq7;W+6Ps;2?(#<T%A`uDG$wRIDaF3r!9k
z1S)dpbf(N*u9tK|cHIfBunp$0?_MREm$dw#%h7f@9(Q^}+`%+U8iS!;dRyq;E{843
zEy1|s)$aYLe-P2@b-{<4h8j^4ZC5a4?Quro+M{YtXh?L`1Y$YiRkWQ>0!2|T7y^G3
zTA?gEntnW-S*R^)sFpUSOrqCFUnY2pV4pxwQD!rb)Y>v<rytQU2H7FjjvJ^kTIw8S
zZv^*#_t{;Rf`gqkDq$er8OX?}DTo9IB@3{uCrGJ6QA9$R+7$447-!Jcz!4_Yse6%d
zZNW}Y`d;TeY)8xCH1aN#<smE}@F%2RXozVgLliyvu1UM)A}~+C)TQN(qPR>qcXt)u
zVf+NeqGql%a$}*Y_Pj1v?RX3MJ%5LGf5)8Lew@5PGrTAB*l_~4t@U-xiK@z0bmrtX
zl^WPK;ne3cc73&nKB1QA&?@U*;)0DBA78V3#G7*7dd5OJ_<E=3f^^t@3;D*y)$u_q
z2tg^fPzgr5Ht^PORjTDDRB&P7P8>1c54*#?3&3_zYgohHc5i2|`9p_3{k#x&9m;lE
z{NFo>ilyv(S+6&^U$(brTQ^?#s&h}!oKxOj9rjNhUOiz|gU$cQZPWO7?2O&rRw*yj
ze>^j!r>^!;N%!1wROW;0)z4GAu*Bmq0%UvGE4fR(FbG?-XTD;u+Qo72QnjEq+Lx+I
zV)=IqNAv~BlYJ^`OsM^Q!458qn)8->o4S*O9>R^?lfgzem>Oi*=mX^#+;QnuD;?ak
z#)ofR5m$0$1Q5zQ*oU2M^QN5$dVA~tlzFZ1@xiISz2*-s_D%6baKv6HAIQ?yd8b_-
zUfcW8r9w6J4SQ_I(A?qv@Bdxr4e9-6#{gwInB%E&@2}O_r}_|qAMePlJImM(gvT0C
z*+9`9vW$=c^jl^Czwlb;*J-YI{vU!e58+EFy^;7NjG<*qxcHJK-k@GfA?}R)R4isQ
zrq?ktnR7edB^{Iu>+YWuKE$j857gRJZHFs3Ic;^8or4|JJf0qg*7tWhQtgiB^?}R_
z#wz#z&popXv4iwD;ICXCJ>lPImB=Pgwr>?~lXj-TUW#s;_P$FlWVh&`mCv@uPj76%
zt+#;zI(-jHA(jLq{WdF3;+QKb_j>c-%^iJ-r`ktf8{2wt^k%Uw_B9*-%CX59q}}uO
z==CVXg8)~b+F^gY=VN1s|4fyx?i(Bq%HR5!Yi~*%y<EJQ{g(=&-i|o<e}P6CE-7!1
zc-}FRxD_lvo!!JBKiy#m!^^uroICZrxE*^bGh5vXRd)xEe;+og7sOKL3A^;$I|qLk
zT3`5RJPo>bVEAQrt6dVk_uSTm1efd>yqMh`e`4Ugqke-ecXY`>Ygck`bJ0`ac{7Wm
z0o>kMNrA8*RT_?Iy+I`NmSIQH__t-Km!S?WHOHQSei4i!aq#M)?{lsl>gc4eSobRx
zRlM)Io8y!P%Wh-bJRo6rAs2Tmu$-mrF*3aD>@B}CVp(lGorE98Cx6fRoP8W8-G4q;
zIO1F=Lm}VDRS&nxtOaI%9smxN>fFx3B?^Owi`AvwxbD49;?^yFYw-^;5z&ujo>3h-
z4jOwxAvXE8)tA;^H@Wc!UFz*{bVbLT*d!_oa}TU{T8AFXfbp{sD;>n;ls+z|5r23I
zR|6}PCrfF+?8+1Z5F^9)Imnn>7$e7aOJ{hjS*)0c<17TC^n@GWP)JA<_j-EvyB<w0
z51yz)XuH#09t2G*i><L^yS2pird*ml{33b75k_M#Tr+sdKfIJlw1LXug6;JWu>Is^
z@q+`Uq-=wXo6n%f=CD)Gha#&Myb<=5Z7l`$GX&>Qmug8JMtk;X>(D7&!j+ytFa5mO
z`;>Z}y|jDucq#3SpN1*K7a_-XO+8p|=Eqwbi_V90jX!a%(5YW7E)NEHiV|ceg6FKD
z0Ie})4ag_G;j@|6^x*Pj%lX$Zroa(l80j?LN-f6|x=hF$zZ*&`@(uBVyyrN*%bi;w
zE`xkp-V?{(3uI|GScaoAb?aApLZe?KS-P+h{w$rd`wAm^y3kQXb-bS=EOboBqJ`Sh
z2#+>TeW`Q$F+g2PiXg2dNr1&iU0kiUd2Csv*jQ;op|IRhSzBZ7BE+ES7j7xNXKD8Y
zyrVO)a#)IPqMiLT@A%G=o38j!T9>WTxdYCx{M3YlLVjtlNUYMAzJW#0@I`2B9q(AS
zh#NGxGZvb!m795Z2DGspkPP+Ogfa6W%ZO!o8V!J$X~zw}A$7#c-|%Uurwv2)Wi<OH
z8oA2DpxoWj2gZ%;h7s%niL(Yrb<z|Tao~g&YK+3t=#W0kK2fw^X48_3(knyDBC8F5
zv^o0pR#&Y!R6*>%b*vFS;G~f<`vylx;3P{;hc3E~$csC5XC42;TZRiy4aduH%(;pq
zp$M`;SpG>@jE<p-DBOYK_+@Q>rx1_&MHV11HcFxuzldGm53P6hM#sN<2sHThj~8)@
zGa9ZyXl}>N=<@op(dL5;1td6lNN_j=IQ;r2#&UT2i9Xi2d1lN^-*}~TRYOrDnDa}M
z*h<}oTll=w7(a&seGWk#T!5*$X+60_*rKSxjGtP(-yC0ty~}q$Jqja+U4T{ONtqUO
z9Ae;*c5N_}ACuaXOn*Yk(CB4ch?`u>!ioi+#SNoaI<yxa#UCodiD+zd8Ce!r1FaFp
ziZNAcUK#78yL5bM8s23D7#rh<dIav)p;HCgxOpfv+T7TXqpwKV2@aQ=Gl&zs)+9GY
zFxGs-T%PO{v^G0P^G4(*oE_<wKnwboto#QZ`_F&T2pS;hu>3&AEpdU4P#>V1MzXW7
zkA%|(CSzfHZxu!$FiTEJjD4!Bh@2!Yzq%!)#!4N$%B8G1Jr<^hY2sSGVRq)`vkqpU
zbR}5qrCP#iTA^9DCc`i(#A;$Zf7-D}*Bn}dmdZLTBxCbA)o=asr}RxNc$Cm0g0>~E
zNO*MI%+awSRMt}vHDkc6swbJMsG46vCU_VvBog#?b;xlDyccH`7%Kq;Gz%PyfACyi
zAF`}2Se$EKmCjZ>keJo}!1dAoF`m}&KT0AEFO%V}YuV)i*l~Ac)-TAbgHU1Lte&&P
z>@a5B{TQP2#+OUsO+iOKz0?1ZPsszn?t%YbO+g^F{&BPK|0m8OFzJR}%74wB`+tBe
ze+GK)zhQFn*TU(07A(GD3_g6}|9~a~i;T{rLw@at-yZzj`4#iPh$Hy&@E;Nz&AEji
z{cDT`DmFfTXdD4WJbmz`H4nOT83Boh2jSS$_yzu9k=79{1)W8oE^GSEOOHJK6nx~n
z5BEn;{)_Kej6HlLv3&T+NA2OsZ~oN~8_Js7Er{^cOtp}I9(!@>-vT>2>Wr+BOGa)7
zDG0I3f5)UVzHjW2He@$rER`FWQDU`cRl48?61gNPseIzCS$W%;EbTB0av^n`53OxW
z-82DXCyPU_^;K(CLTy+po7o<JmGoA&h~yI2CVJ^i8yU%1`Ruh$!Xp&&QS4=>dN0##
zLIjrnPq->H{1=QxYjE8DNB=Nnk1SCw3oJ=n(Wc6<U1rpW<&a*(f+%n+SUrKwv&TvP
zstu~BNK*!muBADbBk-<{7z#x(QdWiQFlV%q%Vx@5mTwRPi!7HV&r7mKvRY1~*$H)6
zRsEWJk?%q)0{hjybOqvKtg?1ZspFk;cf40W68d$0as+msu!S`uh$P!`YHiPy+UM7*
zq+sMybC9PyO=A<U8F^P9ffHqcJX%0l3RtD5szg4#-bq)8a5wcmdC8nybi|13-BN2X
zdxWl2EMvtidXO=yu`0Ygu`=sbMlED}Evq-=&|VP9Y|tNYZa7-6PVK62c1_Kc>{su+
zCs`hz(XpBw()U<OkADHd?2a1jip)WlMq8ArsI8|KtQlXYF19dmOcItUUZFv;qV~wE
z1E(elOMP0UuJ+RftyYz-sIQAm3n?#yo(R>ZJ#OH(CArdbbzd03*h{>IISFSFbLIL&
zz_}E`s=8{MKx@e==)*P7kV?Gz)$p$?Xrp<!;CWb|(+C@Q;FMrXl@EL!UK-Fr!5?eZ
z6d<j*XqrFW+289K9xBXPS(?C3Lb{B)&FD<X#Xg0a5+bhrRaoJ69-uYz-ZtW*+vC(W
z8bXJ_li6x2b#-bMAUe5bujKk4v9r{1g4((-CmzB4j3Q%UXw8&=L?MlASaT+PyM~A*
zj254^-P0texlq8O<u7DLXeO5*Gg0fkIqbiBlqAY9#%z_?7tP>b(9~<pZ}YmZ+T2V!
zr=#|Wc<KeTxC8y#G2Rk*)VX*w@D2M|pWWyBXUnO}p5WH_M131Ss^+mZ<ZU1J3-dON
zakW<4tn(KUW*9QrWFR&_WgxOSg`B#KJ##WQJD`r6BdQe4veiJO0>p7lq}3nKJ|;%g
zsx?9{oBJqM{9uqrCDgyoBin94Cn<=1!J5lGV>_2Kt*pJNFZG;7Cd-eLzVX~^!Q<E;
zlznOcX|~<la#B4*;QX9AS8i2(sLrUphc!t!n;lR6`k(n3JN1{22xb(Sx8YZ=+^PCj
zIpW+546)UEdH6imx+8woS3^(r4WG2(sdLHO`7hp^56|uI5U)D98PF-ov|UUp*pGn0
zTm`C#G$H(O(L}%{C^Le{RqLn&Ba(cM4H=?UaWn-{+=$Un*?YlymuuX-;Tan`j%wH;
zTIk60PwLAWHXe*j@s7zZu#uKT(t@b3S;^3lzs!|a6Zg(-U&Or2(@7u%`pR7<a2Gcc
z1`Nee#=u`VDb$q=oN{eF$%WF<Y?9Q`nYPiA!B{@?$ysX;Ll(#KET5Gsjh2&!^MyJ_
zTYkk)>Pc}qr`#lh5Ai9L3{1Ph=X1qy&>O-`#5eN7TH@(B_ROXCcH%1##X>Z%N4!9W
zCr*+Hpno@M#2|m)ZSFF)U70+@hX@4gBBJ92ci9?TqeRvkg1R89wAMPUiK4<tfv`+f
z&0&P7`Qj0~=G+#OK7Lu(F(VlQ39mU>4-)65!hQ$%^?klK@81*T?@j~I5^NC@hG;fF
z$Ag&ZGE>nx%nyhehm=04$2>4OS0h8ZhIR-wV~6e9N#InRI9|It*zIFWdg*z(Q#ZS!
z23hg?Pui;6r(D;#H*VpkH+!>FkZI5MwB6&lvo`vk3Cp7SvN!HR8vjg>(f5NlUtc+g
z+mK@Tw0t-+S+H9W84Ib6p(n9zQ@N0Og1tiHib`#0BYvCaEw#4I6`1fuNS~t<mD%oQ
zM(2A5dY!&C$@`*HR1E5|t9GMMF_G+Zt^bY%uj!a?MBZu}e5(n4_&oi`nKJ*!y1jLv
z*V3`g&kLyf&WomT%?GTF_x1RI{r}gTwT*c`7r^*e?am2`hyoSGR(X3YRFCX4NEal8
zta7bTFdJNt>M>JZCU8!|ZzoD37Lu-Z+yY_?X(H`{=c9W_T7ahgDkK*95i1ggofI6|
z4cVf>s;OqpkrYI!O@*ShZaI2k&aC~i={xStcYel<Od(?zD&$Srj}YJ4m?9gIdRJ29
zj9->ueQw~ms5V?woLP&IxE=}3@_2a8B?6?E<dM!7c@&~uOmCA*vbGL@H2)q8Q;uEe
zO0`<qwmn)SH0;1Fx^clZWVV*Esv<GzCsoECa=*S!*OD~&j&<k5T~O0^V5=L_0?=$Y
z-L%R<0g`Rhk%&~tG2)%t+lj{@1cCMjMyr_}33WkO#?!_i9k)?YgoPd}ZH@6=V!~Q1
z+qKJ1?Ij*q@PADCtAZBAfXP#xw(hvX4WwbQZK0HbT12mUPyBh8OLmxbBZVzsVeq9>
z>=0lUi~tiXc=RaU9nsxczKhqXE(N5+CL%W76^CF?N@D6W4wl&vENjuijeePxh)t1Q
zo@TX7SWAra^=%V7wrnf45$oDx1j7!nT3^`4$s`Tsc**Se0Xy#qH{}@HbW6+6TVHbD
zt9|)vKTRZ*Z0Lwg&(>w0u_lJ=)*QwaZ5DwsdK5fO%bQ9^5CX-kq57jk*MkWMxk!jo
z;CApC>Ql#<<Fi!<xkV{fMygAVe4PfNezY&o*|Myu?QD=4-0ll=E$L#T>X|Cq$V>?7
zUSz@5R$`Hh9J3ur<uC8zE|WtYRs9e$u1zFAk^HKqnNh>d>rcYF#?AAtJjDMK5U<p9
z)5Q~ln`c`RM(~%#D5|YWQp`)R?Z*T{J2h1nwSDxo=>NZYdmHdJuJg`!W(cdW<7_bp
zLwE$!GS0yO8i3RXz>gqu63-b7D3GEo03u~ZtJ)+4DzanOCM73Mx7lC@1B<k%ilnJT
z?oBo%O)1K^#VC%`kA$SC#!lUhB-@GF&Aqi`r#DTrH<F^JPPR?=KXlxryS?{5_u1#U
zv_*m-0nVH`=gc|3_y7K1AB4_+K`<Asyk)p_DUWrC-r=(hP0}aSj(e_=Z4-D?+jS%R
ziQy9jY=CQ!wPxWc1Ri2>#QRt0VT9^x9D?o$gWw;~9E+@_7DH_Ec|jcc6s^MDL>NGC
zGT$SGIOguEh@``DDPKL7uSP`|dAl|7S!Q3z+rGT5jY}{&Ijjllj;@BS$)|@Ie`x78
z#|>U=!uCF;tc3RD`%vBQarvQ_k0{5G`}e7~+iJH{7#@WlYa5h5fn=(5OZEVr*6wKI
zx0#RXOR2S~wjP>lYhu@^5}HoEI2C)1&=P0ClCt)IhFj;k_r{0JJ*BSoACf;nK2_O=
ztg<$~X*zg37#l7>zW;P~i65bHm|SeTV}Fc(mlT`V(YxBB>#u`IC!SNEct-i+2x_M$
z+sFo8+n5hMSsD7mxz6tF73;Ka55f>=pZcM{S!vy}$-b^5H2Vy&^-&D<a?drjGyX?S
z(#CA_N6&|blauTahvl8Dv#y;yn^JoQ?ZzM43o-utUY(J9?al2kr4n1oZCSQ+SfgiC
zYsKJHETgMSEUuiE7nCb}K|`RqBFleHv+1=N#^v5cv_l3OreLw_Q97OJnUeRtlK4SZ
z86Ih+n^-&lGPC+wqtmK?6a4o9=M(HsXL#_<Ec-M|>7Qa7```7M!=dO2-oJ_cKuhP>
z*J=mZ3;l<*bnS|J*{-<!?7^PZZ5M$~TshLVm1WPio&B!c7VdX{Jk_*e5A4pZ?C|5(
zFLmWJd$%bcQ{EBk{TT$(*HqV2RMo+sk@Tgw&{G3r|I6oBb8{riFJO}y>V?4VaC$4x
zL3KT>c)Z%gr)Q!Thx73Jv3bTb46<kD{XU@f+O(JU%+7Z}9qk!(b1ZK*n8@%yzG^E{
z$IranUGJ^?w}5SfTX(<Bs*j?FgH=O^jW6A=WBn7KhfKMYf7o**siR&|?81X*EWGs1
zZqtL^-{0tZhZu*t8m=kv+hccL^lznoePryKqDBtrmt3BMSoTP~B9E1x-p0=B!@0kO
z&GxjK+ao8RS$mb*;iuGNm&qK>^%fhiVd3AGk`J>n_<3B*=#yK`rpb()i(NQ1ynTo?
zmyg<>&Nz7;YV=W3_oLDV#I1)@SF`3OMR|eT-F7B*Ak%M`u?JbNCHhX?237WyxsH7L
z%#AF(!KX>=+TI_KqqC>Y`EvLQy=Hd9sC6BTtX*F{Jhu~XKbHNQ#ybBiHlI35X|ILK
zkHyYMIyJm>Lw>{jmY4NwR(EnCGpWR2POJV@3Fkh}zO(KYHP*%71iJGSoBgo)r~}x!
z$Nm({HU3XA&j%vc*Slp-hF1j;swWlK4=BBjw=<8`{(xLT-M*_dwI%BhU$#rfx%d0G
zLKzD&sdVgS5W?dVQ1)Ju%{SFB?5y`*ah7qeH}(!5bsF+b&}?e$s{|WvOXREnK8Tmc
zu1Dz>@N2EjRKvsOg6W+mOcl<L$_wVJqs3EQ(`K0O)0%UTp^%~ZO4z<;=96=+hxm4r
zhWGNp@|Md>r~se3|25j5OF=k(vlmckgrFM`yRPD_P{oknOQ4qS&7JVH?qlpV-2QC|
zhzw5OT)vF6LIt{_o5LShkM;KwPuUCQ^<+>A1A1oQ8KU6iWLRe(wU>Cem3MALDb7iQ
z*Tu6q=)O@!2Ab^7H(Tiz**hfww=cUmbo;V4ZxPh%(|})B&E7|cPV(_$rP*p849mS1
zQFAx;c~wB4WzOZnVw@$fp*rJ9D|v<U(Dml{;&hub4)={Em}cye<+_^p*^M8e^SE_i
zE;+pa{W5Y8V4Tr<Sg!NgAWV<%BqM6R7YBQo**O;na?TfqpTX(aoOkkjWKRsgw$X#J
zaCU}cv`j@PY8O;Kl4TwGfOh+bkJiX>6W#Xi^vNiM_##eiTmCjB2}LSQ_)DWlx}!kS
zpqrLoqprJ2o9~4<7D14(cu!|@Z^&<{WJp=lg0K>#nb&$u)PdP$&EVili5s8YXY}^A
z59>d)IlZpyE6?IeS;Aqt@lE)P)I2$}K3?3Dn{7qWSO}cEipMt6f>l()I1_+exA9eZ
zmbw=F$NlhOnVex{dK<c5-A}Az{n-9{qV2*D-=)AS{B9IkT*#Dklh*z3YHQ{Nq{1DY
zKVv?@OToM0f`4>&$!xa5gVansVdDA}Mw_kfb87t;oo2XRto&{n)gC$DvX^c!x0<8{
zgV7=_*YakR*~QKoxV~%ji_ZzUT`1~k0NLBhIvLBq{>D4aIf&7{s*;V3XcT^$GOnnz
zC=EXgQ8DHP;(uQ%plXyCy{L-fBgf_$3&{4YT*QS5!-pCJq;J7=%<E<rN1E1RUQP!J
zy!M90CT5mCM@eDsZX%JW<_o}{sNT==fj3R_YDTX=Z?&1m$<F2vkj>f_@q-o(WBx$U
z>rv&qoxVpEOJX5~T)*w_j1s*Y#_@HC@RO!mgf0RX;h$n!wP?d_JNK$G*NUr}m_uac
zRfyMxMtZGDMVCQQ+q@XwIc{MNz`(%h8tY{+0O|!dmsPm-TvE1Nhj%!p3;SBry7fx8
z)jxW*6|;s3;80B6rA3kGmNcI?(K|5MFT)h3e(A|JGeQx7z&x{H`ev*|adg6L=41Ry
z{5jLdbMvg_vUY~~j4->P7voX5YiL!of8W)fD+RZ0E#@yV8MKh@4S;^xl#Hj%K>m|4
zc+9_m!XGl6Z&tG{4lN<wVnIiKftTq53!7PLAN#rng5E#+uyqw<We;cdOMlt#%?!ow
z%P?hE`w;xXHyT!o&koMPvIX<OWGmurGQ2a)Kg=SKbkRIcBgIpKn-@YQmRFxOeRY55
z39VrLZu!9ubtT~=n_OstUKmG5?VT4~8Yy3<-8WuZ`<g8$$_`gpCZJ_u#|H-OWb>2d
zu!NBOqMH-BB7|<$1HBg9FSm$R4k8ad0MmB}JQiKp@X6>7{jeCtdJWP|H)c!I31<x;
zG@IZoNnUWHtYL<wLt%A67dzQ<CIk^3==f%+E&Iu4rfPZbo$`84id?bf`AWzSariH%
z2bN+4lq+Bt^U7LWuuP~QhBSyEXCWIu1|GCjN9b9GI}to#aC4X8XN8#r1l|j76D1MH
zvPL8bVPO3YInoB8a8x`x!==TnF5H12!(QVO!p^W0-<{zo4WMb}akE>hO`26vGu=W*
zcZ2n?S$6Bwos1mm%wp;BMX%=d(qEXmx&ji9RoGzX=`%Nd{9n6)|9_+Gs|$>E^KVzf
z{GR~%FTDDd9shs$cmG?c{)%(sEx(k#wWAh@`M(?rGWPo4e7n3STvzJ<!s@-{4yt>C
zwtIy%S1J4RqF}jIY!9Kc#s)zUc-@C|Q3-oz!@};uUet2n5gw7?0{#aVQ!ICobIW_6
z^yYIfAc=X5%Ao11i4Axwe7Hi@hiv?Aallq1ke04Kx%x@@%%5P_h2O$Iw<`Vm2i_y^
zd0};@@~@t+zV)Vf?q9ut;t5;GU;V%STIfoXt#EuMQ?VKwMg==$&0eU(`EMAi2Dnl%
z1KqIasTS5%<~>(Ras_!4N6dLAzM@!JX%Q|Ao3(f)7#NfE@G{KErnMlckRFGhYP0pu
z3_XkOSINu|$hA^pe0nX^+iBKq0+v*5CoWE)YMwe@GHVi?p0ktc0Np1+lLV&@mGxKC
za0VW9sa^%!wQEk%K6=b&w6r!=%eDBtz6crPgw8{!XbAOgP9tHx3VNj1oT$W`PB%Jm
zj6m}Dapk4KER?rEyCgpe(Rc(ePJt<GL|I!?gS~=_Vrg4l!NkWT9Ht>FV!pLCdF&=r
zAZo_W?~jkNL1t*8!D_GsNSuXhT-kwMG#@{s`>dJ`b@WgE*gp^z#-CECJieqfIg<)A
zCKF0gc^XNwx-lm9$Ufdf%ckKwrkV55i{pyP;)IrzT`ExyYKx7nj-p+Q48pOHgET2Y
zjbEB&2W5YRl~|ICk%l;fvk{x&VF?V94%%@Y+bf?NLBN3}bH4G@I$h3F;gnhxGx_)3
zw<vE<FR@6`4NE$+7BkZb*L+g$5s8IP77$sr0YSeB0J^4HgKf|>K((Gl*1L$TCh&KP
z2x61Sf<<HjP^mhF>Wwh*z1bk6$Rm%yVRQw>Qhl7YyumEJQCAjpThr{}wBv)mrcCo_
z@5oIY%dHBvdMY`hm+pUco8+q7!>S#yDt60cY5=Q@BWWxGnFF!#6tNLm2|e`Gdz)qj
zn?i|N$_M-b5E&SbP(I52`e)~;8<)J|lOYvbv~*xp&M;d)@7R!sRnrQ@r-6BBuu!N;
zXND^Q{?ppB6=ou817eRqK5s56?n{hoVpXbYooHLvx9NusL3@}yWK(yk%X|Z<?!B1D
zYy2`b#jYvZQK=<{Ap_4?YcI@lKeL;u0qOIA*#)TEL2a8rz^;!dd3wd3Bf%+kbEdwO
zsWy1w3>d>~X7=r5BCJ-I+FI;ojOUtTqHwVeA7Y)c0geDReQc!cbT3;YQ5w~5YMG^`
zzA>M?DQg~YDOveyUE)1wEF>%Cw+)81CvKQOnxU+Fmg-~j9%r##u1>1wrqn~h9IC#^
zlB!QAMR>^=6@JL<7?qH$pYB=K<7ZR{vH()>N=c5<vTd_ZLjGU3p`xxaiCFI^D>6I;
z4iT7pM}X-rbzhcok0qHjk87=M=O*8c*+^ffrMt=$b!#(Y*G;9XY`Q{p(C+3w_qEwM
zF0`<yJxi1Gv^E!;AP}HCv5G4kGXFaD?;ze3k%kfAB6Q6wsthv*L=USHMD~2e7SbGo
zR>r}adPF5+OJh?g#|I^Hm8g0{%d(cSRNR{}qFvPvy<#I=1~(8Nw#Pb9wMvqdIe1d+
z?9Hnh(gkqej)+kF<20R*D-bQ3V0qS0Dh<^J&?b?-wrtzBoR`L<vJU|}f(t=x8|p#^
zEwscR#R!F_+(ppchFE*FCe9l-6NR}EQGk5;1sLGH1AUJJ;IFZbQ<PW5K!O1_Lir4-
zjPAyLRfkdvpjMkxSOiQk!ZgLt=!6nsllg%s#;-@0stx(g0BOQ!G3mg~%}bCeZl(n#
z?Wt(JKp_U1Kj63VjfP{xTZpn@ivm)6ph^hjSJX^IWV#oAwG7J<$5`2_I=<=}cy<_)
zphZOQAVjpAniqskKe`!stfW=twXhTM^#)wHW?NO0=v0!m^RVT>p(FcI^+VZez~Tv*
z75Os&^0pKq2rOX<R9es#YWQeQCLGUfEt-ko6G53wF**p9FtQS+&4ima)xkVH&rH{u
zW}UwJ8lVFqCdH(LsO4#=uhy`g-MQmt-Kj6j9Wn=WB>QD!h1e5_U%0YQB?6>3g26Ma
z2e-NwNm-OJva58KqCpJ53qmZ5K~!F;i}e(fCkswaHe=>RY7P+^=qz$M6~L-Vx1!Q^
z#=Av5=UCV?XF44T?SiPu0GQwmeT@@y-h|p^mwh9dhut_?$B-rhh8=uC7ZzCrO5y+v
zd1FA|daNIvFCgJ8se))H?Cx<eswo8|!(VV*+_bPFtD;r7M{)Jdnx-0x4_@PEH0Z_L
zH9bhR^i^w2cBf!{)u2Xvuxl!~<I|yl@9O-^K$mdzkuIziF@6K?B)J0>IeSKAw}`7t
z(d(-<5jTyvV-i<_s(lGa+Fm5gkbpLI7}!N5IY5cHR%C(|SW*OI$P8ct!%(t%s1%h=
zDS{=#W+mUVWI;a9H){c0Tfb$*E2hdPaDjgIy&QA{Yp9;UY?;99A4r3oE)pAleovMN
z8{^iK&LnOU0G+0Uv}5!~@XM-*V+e@4Aqr>%x=0IVz!cF2Xe?FmqSH}|zLZUwXrDoz
zpCH7$vjQul!*`1<KJOIFt6w{$xd|zml9z<IXdvS(W85kT5snp=i~et{iO9Ed84~O&
z>d{IAj;CvgAgl}P86&}OR!9KagEV`$w3QT;05?U2Gj2FigyATwD8;G8oncbp0v_cd
z7uKyVU~491=+)4-gsLpYW!O%P5*PQ_764l&XfHYqRmA;a%cX3lhR7iB7qO6X#DX&>
zc`^z=f(8!SB4J9z2<IgifFB(|tAg}vOcNN5IhsT_XfP~idxOps8f#-wO)?}Bm?Byi
zH=Q}9#dp}GRd?j?erw8pTC%l>1LH5*uc2jaQ3#3}M-$J`EV^b|E6fGvsD@H9h*1cU
zy-b}|TO7o_l|wZ06&+R`(jv=%Asg<pVp#|^Pbq2$2ZuDi5ZEdTQ3D)?d;twX7v%D(
z77E0bG)!OPVr0-+RJ88N&P9HIi(jDue<&|Iwq&cei<p{SLkChRONdxXLI)x1v`p{<
zT%Le9DY!ZXb=#0c`!o<k!hDE(E3s6q<W?D8iPuCBnVcYk7Lc;8gm9`MWjzirMeH;w
zpi9td)<@~4^7awCJa>n>>B7bN1L}p#P*@|o=%tJ9Qd8e<_gfT*Dwv&YOCK^@U}R0x
zaWqK0=M@E8$Emg^)0t{JDvz*q;)`r!Xe%uw3sE%~9SkBDR}V1+h}X|mQ^^fvY!3BM
zszuUrHd>ha8a?xLi6r=v@)<JNu6&nYjGblt4(*{5Utjvj#n4mnO)@z^QlSmn1|>Ef
z-((JxGJjyfER}QQ74utKGa>7<Ef=&m%wcm`S#M?XLaaY&OcS@oS_wT=-q*7nx`%X6
zjtq9}EB)ykT5v=rZ-&?3$>ic^;zhf5mVFB~cA8#Lwl_mZp8iX*V~MC=BpdIH-%wf3
zq`@DWmrt`)CW@MHG-qb7Yr(OX)5|PW(#cb`G}26LmKX__DOM+6WFeAC>9>=5k!T(E
z#VNZ?5~Zn7nRN7Z^O&-vhf7*~l5VH*USd5gucPrv664cp6ayaQ?BO);SkT%>J`m6M
zRLl{z!#zW8m<sz~%<R;%*8WbqVI(;lQWK}O6zs%4AB$Ex!=3B^TaN#oJ7dS5f=c@k
zA9{+$Rez?VKc8Jjtwh`bfST(rZnY;Q&viT5!>|VNRNAp8=SYns3~voNdz}LNjY5@a
zasq1<XsWS6MGEp1RL83t@M7At7m0m^MtA0iOx}O#cUV&FeLt$meZmuir=bAnLv!q3
zK0j>!9y4EwL$r;(Z#U&P;!tf5qVisH*XS2Jx5bmu3y7H|_b%b5Fs=!`a`G+V_QUYl
zzWc+st|RTwM*-DZiXXl!x=~lJrc%kBUyPlECi8{ZSJMa7kseUC<^$p4H$1E4&ldma
zZt^(>xZ%~WysnVgfhff()7BIWpr30!p!d`00)g6h3{r2DyR7+|4-jpJZ9NscXnqc2
z=*z^Re1u(q5F$lTld;%(H*rcdDjm_!{Uc?~L2awmI9b+m{}9!-j7*bdw@}&44yU#b
z=Kh4SD}yLySoS@1SvxaQC&T5Rm5Sk=+V6smw(yFXD4qJr8#ne<^sV}r-5cdMQ2Fdy
zXXk?-mvbZL$IC}+*PFu76Yu+npU%jQKV`tNBWh{ACn>Mz7t$a)d$djPm?-|`aC58s
z>fb^<UdRs3v-<ACNys6aUcD8BwKy~rJfie<M8{FCE*-7=HBae|lTCX50&w6^V^Tq<
zz>BE8pf+Cc996<ail3KGHU2b8nMPw!T>g_53qx>Oj7pC|Yu?&YWHYU5%wvEoA!UoK
znFU^9XMnbIHyALtv=_Dz9PeKLMgE=#=c8A<^ADb6hc0ikni&exohe_0PkPhCrhYGb
zjmih2qShBeB5M0r($6r9Q@iipm}eI9v<3e8cSG~7hwQK3V(j^gnW)uw2Kg6iQ!WRK
z?NZzOQimKNfhK^@bNY}y!!ltRx^%aGi_nM*H%MdNl^a1G&0eRzJKAoWy%m%w{NLM}
zTVbD|Ywd5ql-t-z)GqM0Ie9A$fKbm`&8BfhJ5xGAb3X%C><bqw@iQeC7fc5@?cCHk
z4=;T)IY+-UJL`$s$p@{(&(zFT3Keqs`o+E(`Ca;ZsgS#ldQth^!P`)Pumr^4UpWZY
zUVl6$7XDNFEISge|2ImL3r(KWc4|A~A+Wgse{4g010$~ooz|kbNOhRYz?s2Kve!`@
zmIm@^CdiQ`LiMB06}uQk`Of-omS9p2sPo+K$L3oD!!gYyU!&|YqWn?3suOM`UR_z)
zyHb{*HCy0!F6E(<C{|Gzy{B`BrHR1x?5f(dT2Hj)vZX<WuWnMN*`4qA0b#!Eb&Omo
z>e&_-WE_vJK{os)wxw0&+r09T#p86#70ORDn7VMW%7fsDhTLDFn}U)-Bu|PT@NeNI
zbg$Q`JjalB0FEzdv~>=F39x*j9V{GYB23?p9#)Whp<=(zw6IyCsYjJkCFx{=Q^SKi
zHn*=}wX~6f_DID?wBOyQs;>b@*ZW_>Bm!`ZGbm}=gTAX4!Y9R-P-gYh2iD+Eu$tK$
zl2JSHD-7pS&!f4Z`fr99t8pVRvYdmT4H7-g{u~hJ2WD8Un4{w+nGFgtA_0I4Gf41m
zW(Z_x%?#ulH8e`WP3Y)h{yI)1X5*+)33B_6^jxceztaYT%2<(r9(Oh~u+%v=p*)Mr
zv|_^CWoS-TukPCiV{r5!4A~z(;tgL|+b2sET%WL5!Lk4N5o?-#<2EGZ6=<WUnBUFb
z1-l=havb_UvnbA`SPW-NjgOs(7E<kE7h-j^s6B>+j6m<fb}`pW-W4=V;&2XXz)bQy
zb4)2I8R%+4V+v!hm}-(V*mi5Qz?Cf$ikHXuEDeh@7z-7AgO{GPKu%w=;49C~lNDgv
zL{0V;^dSocd8AzLKG>6QlRa1N+`RSR_4IeZdnGLUP`==Rx|<;`(UyRl%-=_`T4_8T
zk4uex7CT?`8@+wPOE8F$LcK7IF9c;FHk&HQaLIWV`Sh4t80@c^x1#Kq5kiQyMpaa4
zGHP&|&uwX#Fbz_|HF?Ot1%J-_lVN_tw5nnbSK7+WR*dJY`Fr6rVEECN8(hH}LQzx1
zz9<gV>h^sX5*#)z_wSW;Edannsmf^r(SM(&Rq^|SSkV>d>%JthV1~FE6?3rM3_Q=)
z6dZW(UVxhe+#=x)vbq&OIXmoM#e#J(9RPRi?PTY{M=U|lg%zpdZ9xoMGJFCxZ6UJc
zR<R?{T`(nK-L-+S7=m-d$SHxq%0=-V+lD>IL?`?LxaavHVWo(hGt9Ut$L$v_P)KJ4
zd<VZ3JmZy^)EPi!j8KMqEiAlorZou-VSQvxfpj7B@{nxw#;d%^=SgAa$@#b&HDBp)
zqr4aUYwH1@8w>f)m;I4q92)QM$FVH%Zp_zjeB(F0vHv$M{`lG(9otrmP_7c=+iFKk
zZ+fL8-?F2=61pbqZ~0OGFIS-i`u!i2)&CYbUadiS5@j*h*WM~-Ik@WCaWWKo%d!J7
z9roB*tiXe0gD3L-(oV$KVb_hXF_7cjn|QGnfAcMO?AL3r<bUqr=lA80?t1eR<p(d@
zH}v}b`dsKf{mUbN^6FgazPHrkKRAa1l)L9jzar56ZxQJ0@s@~3o@J)yu*;K$-l9;y
zfU7Q}3MJHWd4z4I;np&VVn#L==>;e+)faTgwqaNa2^_QWV$>0L^neP_4R1q*9T|3s
zpd|==_^?wd3sA<um)ei&WvGng3yk{QtEW?V-M`|=0dWR9reA+pzkUep?Y%MH%j?bm
z=Et*@TSp<M;ngW-hYo7{vBMqbZ}2H4cU+xFHBADX1f{PNR2r92^ou*o0EUtVfm&Bo
zip-LTjhu!_V6AutBgVM^ni1t0%_!*zW(98jmZmh`I#!b=Qo1`sVd`PeQV1ncx8)%7
zR~~vLzmLH%xocj@?<!j#)FM%8mmMMO_>iSP7Gei^Tkn4St+m(xxdlH12%t4~!91%N
z$5kr}J+3evOeaxP72KOS)OJKQQAU>K%^1=c!Gxi;v5)I`L61l@!lfB%`0`YpZNg?>
z!!SyU`VlT*JL^GPO=T4!N-OS6NPvli;-h1y;dzf%8?Z|gde@W{jQfQB$s5{}$ml1&
zs${u(jY<)59*!VUaZ!eWuI4H=F(F3qtgzMTkqjFfVAYL?w!p`wXDP~bN{y1u;5?F$
zXux;Yk~ds-AWI_5j!@b_uxk`UzQftY&aJek%odqxl?G@_Tcs*hK?E|`J5N|tx3<yU
zQXzl!&|fUJ!9Q}kt;VvqJe1POQ97cSzVV{w)y6i9ShQc@HifQ7?5U+>Ev@JLY$8!`
zu$_bq?H0EwICeo7ZRps{w9O$RuQ-6UG$JLSE}OFK9>*zaAY7wmTUYH2Xqw#$zFu~8
z^cX&)DOne*q^fj}zSyKk%(12Z?J6_PxNnS%O62oT3tMXtsRfiC7n)|aS?!9lK?KSa
zVbQB8$QCty6F2id11kKK7IM*3@)%SR+tlExP>wPUsxZMs?<JW8kg~{MvrX*%s}jp{
zA9Bm~W59GtC@jVVhK;o1A7j#1C#1V31@UvY(HX5aZ|1+u*7QVKx@|%mn`+5PYJy#1
zJoFyL-cCY3Wd|uXVeTBPsdf*9b#3oyx@bCk%_VdVZTzgZ4SflH`gs|3&s2wJ8UyqU
zDL=y)wc{(gy2zk<6FQO>+zcEh!}-sT0-7wnl4g-*CA@6mD%ysYF0-muwvy8tt9BmO
z^`*dZwNWp-NI;g7D=jR3e1E?D>_6Pf3jK-8&fo>tb<?%e$y8g&Ur)u<juYgLw(x>J
z7?gKHbQrCf%i5yWBd0Z(6faWUMjb;`{v@O5PGOQ!VN_8@6Rzksn9>|%5c%VIHnCrL
z0D{;-=P7d~lNGHRC$FF~D)Oi8>wqTlwl<dYcLl9m?g1W0JvPx)cTJZTGhr58&^&MJ
z+8gF&dyXb*Y0WEhneUM=z56DJvE8VMc_$(oXabn`H~@EorUv<PTXjnF?uR~Gu*jku
zfJoj3D2W4d`!s{G1{W6)9}&rrkZz9Isv<x)%<^DF7!i#eFVNHhM^6u!u(_x$nL2}~
z8WO6=n=hvY<7uKF^9h*{8q^jTFn2s=KIE18McoT<4vjHy639RvBcUfvAd8(KB!HL=
zdh{~<cafWQJTE|%=>)|A?%tt9h>yE*^F36ZAt8`OKyWB>wHeLQFquq$D6GL!!O*3!
z;<weq3g0i37L}_#PorX;F1q%()Pmrb@H?tvMVL3|#;JrOK_aI#KtLDq40NwJW!NC#
zQPoAMIS}N{OqkHKtuV|Ns%5(-35#09u5o`FIGy2M5s(IOTObj~^39kLfHhmB!qxZu
z2SEVlQ-v%ODNF(c=+XrIdNW)vT#l$r4Tug*6b%y)t7r;Iu>}F#j7tF#i<o6E?zO16
zT0FmprO{r2yyZ%Qfl1s{h-zj?fmF2kaT52(-{iy%sYrD%INH8jo0Tjpn$47Kwyu6@
ztiYxQ7d2AF{DY+lpHR+sO9*pWOyC2^ik_iJ?GX`51gazwVxNYJseA$>7ES8inKUhD
zn<oCew1T5$!fo~n+RfqqfRw<0Lq$&|Y9T14O=w6+iZUWGoAN-f<0@DG_zoqY+2jG)
zY9dRqaZ%9QGa72@5idG%k%N21mSpd0s_J=?O2;NyEXC*s1?qZTZF-7?2?9d_3?Y0p
zN{mL)WGo>?B`rcmr!>uwI2<IXtO*5%>qZ4T&x|$&pju~Uq}L7HicT9)t$r8R*sYeW
zEjMLcjkCbbLcmE86${6#Y)eQ)$>Q!P;Nn?^56z_ORG_r01S_ekZ90;HD=H{4=@3ID
zMFT4WTqS|-k&=VU)-1Cvj3MZKt2Pb~Go&T#6BP^;TwFvLHGLwF$j8;Y|5!sJldvSK
zK@?|&cOapp0S#Og<v<-}K_#_mk}@c}1HOPXCg$)vo_7dNIqS7Pqg9MxOxC>!Yk2Lj
z8I=feuoc5`iSmXeC498dog0-l08ql_B0y9JvRb}9vmU+@Q~AIC-Wmh0Luy1sL!nhj
z6^LH+RL!}VXrN1qigA-3aT;*dxrwj_A_|SjBgQcdumD8FIGd%-dR_7wNHDC5Nh~|y
z%Y&s;shdk<5<E71Hs&ToQ%?~M<Iwl%!FPabhHl!dBe3ZY!1n^Tbz6WX_YB1q;Ub0w
zL)SLIK{>LHB1i#6#b+i3R>KEkV3`@X)S`>Yz6OJOzimwEcaiFpzMWchHYUTjFPiR&
zjY6$t=B+5^TZp6#rTaKxv640sq9lNak?SY#i}(XR1h(J;BLtox5`g&tWw06%<cX*i
zEmN*B+Ahhol}v?!Vzn0YBtfp|X4EEch|6%*|2BpM{(}Puu7=Mzs9UcLa$iL1L3?t+
zF!hRqpTf5X7qlh`Gw3j|l&-o@NNqp)<AxqnBCb-gpS>MsJg9>pAIvB>WtcEfM8`yY
zXk6mRrNML<P&$ZeV6}m)1h3bz2vIad?FjB$Uc39&%6k;tO}({`?fo-c%llZd0)9Se
z^@435GKGj(_pRqvXqq7z0hj7ypW4no$SYxD71ghgQ1vbibt}{p*2mT!r2C%QNoT3c
zLeuS`(K2bQ4C{ANM$fi|-Y8xt>(}Y)i5qK({f#}+QKpfXLF|IdYG{_OEjjvmQkrXI
zQ_=N|eVDOEvmrss3;H}0Hnh-~LdjI<TeAIwVQqKbKG=ne+`}uSmx%8@xZBec*W%_8
zZ9RLb#I`yc%%0xn+~els<?nYK)P5*`NE;oFZ&8Luv^SX<9%12w@y9zZB`bp)Np^V4
z9DmI!rSDwmIUOQTPO^JzjW6BNRF<DE+tDSGw1@9H*fvbQ-Z(-~wDK9s*k2B}(Wv?U
z($>j$ncri<GLq(I>H1V~XL@ZZeMif~tYeOjr-*wuTT(y3;78OVZD6$$iH*>*!`3_O
zqse$HRR-n)X{M;t=MhDBjsDP3zN!16<@Hl5k5D+?%8xUi7eB*XsK#q)_B%;?eNEqY
zQ@lMLZ;!utBb0yRsB&G)f7bk@_R>hplC{+t%4q9t7JFR35keTcX+$fV59<&2v+>^i
zCiBL==U?Of`)0@?o|6Y1JBRHkGP*&GJzo!A2Qa3d%z1(i@ElT-ff_uQkKQzlJBG00
zJjk3`dOnWdsLqiB(^-LeKbfMekd8<(>{erhnFr&NUhj>o^We}d)c;_Y<j(5Go{c*2
zjHbg*<YDtc$gzQlwbgIT@lyT~b~0Xn9BQ}ZLG{v)&Q#cldg*g6iYPAqS5GnR5oU;i
z?CoI0|7_nHDy=}Cs*v_p8I-LNbqrOxgxY=e50mEB`R}bH7t&k%pS%}5cv?O2?fO-P
zocoUy31}pDpS&@%<FfqI6eNI0!tGyUS86-|D~&+}c)#gfnH}zWo-VM?-G^^ykGi`*
zd#9O{&b^0?nWY8F=3~RD%ML7$OTmr$tM^r6Vr~~v2d3{YO@aL(TR)s~uhKfn7JF|a
zTe8+iDCMQzJ8zq35Ao{<hDqPg_F0=`Isf7ESD|j*J-q{7(iipOAAFGM-}x-$!+;^@
zc73jy>D!f|Z<v5{bsdTLxnqmUkT3cAWqDT+sln|F@YSbLs21~gVL6(cXIqGRu?WCq
zE<-Y!!x&mea{umd^jvT7-NcW)z*2=$2w>%QxOBi}c1utVHq=YeyTE@(D>~B}-*FUR
zHl^EYV}lLa69X#$r@rS1FXaMPsQfhz{e!gI&Qj<xSK0wR97toXInHvsT0t3ey_FaQ
z)IZk-o73aPOWR|~z4p0Z#<laOil2*&sC!N|vt(L<1BegW+RB$_-$`<7wv068izp7(
z&%likxvlsApznz(H7CNu0GwGpO2rgpjE_N|yrotwL+qION>h=nI;|AjPiMHV8H`NX
zl%9*$I3Tc`2Rcud^jIqeBdmb76=ZtI!AUm5Xj*FzF6gC7E>s%ryX`Y_pa>i%_klYC
zxr@NU=kWXB;Z%iMHNGadE9ITlhb$kSyT9{{d8k;=)nC?&U((NyUNcQ$>C5iCmBuA%
zGvB8USjjVYy~EmyJtlTwfqq?v*9FqoU_SB>u_(00^)E2up4d(B%n7w&opRz&*<6$i
zEzo6k-MaRdJu&(z`Mq>q<{W$q>Oa?FUMs>Eo%bJy#Ma#XNAJeT{Ln+PTC4%zr|({U
z32lVl`=z0fbnc!La-kRMP8BdvK<&aop6dgyv~~tbu6NgaIovFMwzEhoJG6N@aE)8d
zxlljf9wVXMFXenk!p&BsOh0cm@5_+f6KkM}-7)KjO~Yl>+7#?wgcgnduVWaQ{TAC|
z-m(McFd=mzDsAPtHqg4>;P@bKU&c@>^fj~h={fXhQQJBK!*db78oSwgV)U~ORPe5e
z){YY>k>s*&c;`?V@)dpz4w)M?5stV7-E#dD6u5g1g1i<j1tQ?wFFUuwTfMXbLkc4I
z|9D4bzOPW()cIT*6#VBg#A4K6+;h*iP84s9`I93};RWXWR0+kLGiq^krt_oksunw|
z!)lnk?wI{4V9EgLx9^}BG`{3lR2ct+u@SzVo&RyMPu{Xjtj+3n(mu@Od`YH=zI!nv
zc`^>!xh#fd^(hum#loo8C>GL%QMh?YjX~0nvw$~6?l~eBbr_Kh>j1{U!9N~OO1#gP
z%wEr#&2jhK&vH4)y@yU(h2Hzw0)x}gKce3sfk(^yzQU=xI>*3#lXF2e##}M?oVlwa
zR3NZwLqG^{yg6!=n9z9Ndc9Wsz8AKs@9qrmJayua;5gI&%T{K~3+&=(c6SPv*Y(|f
ztAc2M)Qg$4e}y0(@eyk896j;xgBbAj7b$Wkegrlw*7M<=p3h0+PAIQ`oWpti6Gn2O
z5miia1wPe>N!2TYDwDo@gAn=4NElJI`w#X853}4abGbWV5?*?#^W<ZN!QS1mVq@QY
zYv_7+z8jtDo;++yAgH&J7b?X#6=tj*lef5o5g_g0PxVY8-OPm8Q_MiDW1X5iX5zTC
z7%iRJ@C0Vt`#vOu!V7c+^`GRIN5!_r;wXUVA-fS-_5Jd@;|N;G(EVR3`dR&!MsdCk
z9jAm;3$YRPV+#alHw;Vd{>BfMQ5;n60=vIZ^hEYR$?Md<n?UtH)&^XXzyIJooZYQw
z9t#)S+n?!E<p<_v6)rTwJ%1*IFIVQRFp3JPa2oo$kn^dC8%ZIv4S^5yG_i}1TTzf?
z%#1WAsy({2J@ke$U|Ys<*vS<v1yxQXe3;_r%Da69NE-HJsK8|-k99C=KSHTu5Jloh
zBdpR3$VDcxTh*<0g^?D%M&(hcgsbjZ6m6=Dl#suLT}~a|D2w^1FQk6X8aH3C^8X<{
z@ZyjJ-YeU3zoHVu&iZ9UWfSwn07X7uK91-Vc6^@xxsb*^ya1LIt2Gp$)|)6NMNJnr
zJb^nlHXIR&dOQ(LXDE_epWeq@h&5m;V)&3!8!6?vsTKgwJnD?Qx?nx9rht_`u(Y8(
z!OT5c6}4RHmv`R!Yy0Tu&UAU~_F~7c?4uKB_#j~N&kuQ-O-GJ-%=Le=)_6<A?EVB_
zS2MP}3X7`%_z3`D_>KHOh?sxv^6@3`UI5@<`~kjhR6osE0r2`MJn-IS{ZmKgAJNb7
z;nuh6HNFkDJBDS?=;I2(*VRIc*W__eOnsfncmAsO<JwRE3MT*jt<sIJKlMs}Rm*&5
z4G{Tb`rmkP+^e>DB{XP*CZC%t?eg9WI_59@L_e|WjQu6Alr(bD9)Yg;CzjvgSZQPV
zU8S~YyTAFLx0ibR`!Vxv=aAq03ca&C>Dtry7ke6!hIUkw^Q^*u^*{6aoD%dIlN6A7
zf(vy(>bgz*aF27b<MFl}%Kcw|=jyH#f6OBW{|g_w0ATURUB5lbk<OVQZE^RgDaUQ;
ztXN;s-Hr$B?W&s@r*x7%b2fE^^)RG-hy!N_P@^JvQ8l4H4yhFz(oNO9oo-wkQreQ^
zwUQlQVn9~U%2I*G&uZ^sR}|u~UdPU#H^qH_sBkOZYi4`RKQFZmI<qs>vI$sli=D0{
zeS`V<kYh%CLU72bvW7C#dt5gQQbtK$12lHo?b`i!y;IF0=6@Vj?|nx!z|x3}k;leU
z84z(D!!j|FegTG7y3kCKC``pMGMSLa8elU}Ejy~axHf2${k9&z89F*i9+2g@s4P-o
zjtJ7=O$|A?ui41ok6=HVQLCD-imfslo>l>7T(fLN%u{qs+?XGm)dXT!e^&fPmDwWx
ztfEe-E!;(2E`Ju~6>g`Nj;d=wM2v&|=si+S?8P1q8+)Ig3ecq#<GDG)pqpavw#91D
zbuO?aEzZht0g9=r^Z<XMdpxD_u9C^un_VU&PdaG}Mh&I~&j4Ms*lniUE#-w7UPJM?
z2yAB|*>xn2L)YDPFGGFY5|v9PiM31-M#m?KIxD|OM1o0Wf*KHx*1%1K&01|zcNg_8
z)&T^_thEr47i<z)pr;X6ok}EW!{#=Kslao3O^dQBl_;mYMXpSaAz2G};TG48Vb+-=
zQ6F2(BU^YB5XT>-6gg8`b_F6lVLKT+Shl3FIcJV*H~!1cf=MDsh~8^1s(dlT-N>Lx
z$f2NYj}1d_7m|=XZ_Q#nbxTc5gr9`p=C?W6j;Jf#4U}C-nE5<;zw9}}l5T9gNyxFf
zEuz_n#3l(G&4MrOA``|WoS#{Bh#y*FPV$C+F%P)zAuio$N$crFHEy-317_k{U$S5t
z2T}RYO_Ve{?jW}EMdcY<bas}rYp=oV36&o0Kt;wr{Lz*X-3O>K2#MQ(8E?~UxY4xS
zp+mRWt47S!yMuN~jbG;MWqwVUb*)P(N1=GyPDrA2?V3S&fI@<Z3Iz#S>m)bF`<=lt
ziP81Z7GFl+r(3?7Gq_w6Bla`gwxKG3jxIkwr5%bUt#4~qX!PSf=8oy#W}&u3P1@?j
z)m{0fi#nv7m8V6vHJD(nnTo8`hcgTEGScH)4(M$%QrkiAH|sB&8Y`(?vZ;#S3L3`&
zzyeE6wF~NGDh?Bmgl8j?m3r7RRPB-;ZKx5yn#i7{HHT%T(D7uJ)c_k?Xc~$~=u|Yl
zd#(+-<Ah~RsROytej0AmGwUinrsez%qohq=Z->6Ey4ygzO!&R*FV}pZ{>iPZXD5PF
z=&m}U@J5Q*66x@DNhsJC&+B-e;TD#rnB@X_U++W`RD|14O#+<@V|GKpMdV4Zd2tWB
zO0hoyvvpk-F>ir--H_rwH#w|Jc@8LoQj`NGNVg;)bv~B&TaZ555#PtYb`OTDn_dd#
zt+uuHF#xvMFm;znM6y!G%`sWDo*C9L574S)sJ=AB876NMk1~;W90wVtwhiz~MdO$T
z{v%Ww_Rr|dOhi=1L7fn+6;L0Lnxk`?38X$I4)B_lAALsI23C-GgR(V&TZozcGYBr-
zvdQ@)zkn3B;OY>_0@ke9LZd6WU`KEmMlPHfC8pnoqlhi7-g!W#p&I0Q%ZW+^7!Wl|
zA|lb07`))|i1MiEH$C+s76<VR_WG3Ug3qoE&<lUsyvuI$SH(pZ5nnV%uU~it5l_N5
zt7>sYAXt0IH>Y&=iZzk28da$Ys28eI!DuSwm4M}l!k}yT<jo4Dw#<xW6m_*hp{zwf
zdTBFeIyvBwY0&sI4VRfw=Ac);q>>*^VFEQf;iu)Vu7FcUs7Cw<6?juu+4|;x*-p!l
zX{*8*yk4<<X|ZkMH01Ji$HoNhf$D&-67VlVQLN#X2g#=?+36VU7S(_X!@X&g4;4}V
z4QhdAYG)!yj*%~sIRZLUA5kfvgey9xdPk~D`LSg)Y?%^8NG1l&C*a;h$!;c^VftgH
zFDH$e^u`?@LBdWprD?3-x`C8pC~B{}jZ6l(U-r%)$Zyc)?$9klLgWEVFzR{-e13o%
z%ZQecRv0LNzgJ7<Vp>O9i0B1hv0ww;WKvXuqSLiWz#=|3;zN2Gaol1)?*_bhkjW56
zF#L<m625uoI|F%6GFThPX{F1yxmYc_5y@7NN!5ryDrh`XDhma8esif1Hz4;`#F)Hh
zfEGaC15yQc=)SD9RYvk2#YC!yO;n=vLs^QdFN5037a+~H3-PdHpF=RS)}|YNW6ffI
z0s%eEDBD8INfIfs_>Ix82v#FYX+0&RzND)-<H1^8lURh6olrue0sm&jz*QPYUZ5KD
zRryVj>l>D1w&BjFutgT&w{owOD0;{*D6pnsMCby>MX=I`+9>8N8&vd5vPZ8i#}Ry@
z<33w+wHIBvq%UcU7SzHBMcn;)fN<By`%pO&$`SMgR#(JOnd>RR;21v<$>o+H@G&Xi
zE9^IX^*F$~z%hde1CwKePC!HAiy%xeEl%?JiabNO(5U)x7z4D*C8lxc#YNk!`Znf0
z9rbs0Q3GkmKmT{``FC+!e7_{f+#nVcjSED!Vqy^j@wkYayW!_Kzh$}VqZ-Jw-|*p0
z1;NM@gxa$y-LlqWlpvC0LOA^bP`fYCIOw==Z3*0>R~z(d&5^3^UJlv7gq}};@6tv;
zZe#-Hy*zc@h;}2feV_|F7gg#(Sh~hVL16VZ)$k)V09Q?nU^-?Ky1l^@ha+B7H5F-4
z7dVmiK}(^*Nn~q8ITaD4fFR!R!CH{mo(s8`0|Jw9(+{H$V@=)14VU|>l3|VdF!3>W
zu}zOv91JK^HLvYHB`D)XguQbfs^=k}VK2*;8zjC|K}DBa@ucVlZ8KTXY{Xz_A<MiL
zM=%48*cR`Qutbp9fEUMD+aMUXY-R|rL7pyQOb1GN1kFStwrV)Sn7~|@z@DCIr5aiI
z!q(xhl3x4WX(en9UHs%oN>3?S{)#)Pe1bide$Ro6?!~SVeeg<0&xdJ0q`%5TL}{AV
z_;$AR5}A(YuFRI)&q6tDYVz5QTEH*!)5!}L2N_vkBXoSK={9rlfsy!|O)!thIMQaS
ze|E3^45g<jZC#rjPCbs>-MgF(dh3C3o7|M5UwGZ*nYN^i>d@?nX~*`nt??Jnb*dYb
zEi3ocr}Fb#HJ1-?&EAmTKC;d%waEL+Ul>tOl4ysyy`;PBVSeX5ztuDxe7x}&s`edr
zS|JaYzC~(#=hoUOg)|N8L*x@IcUm?xiO}Pz-&gmR6f9B)%kdYG`jOG?dPsw4JXxO2
zspgu$q^0Hchypf-d+qbDpVo_55KOkQqm2Jq==~Snl)gb3o7CcPT-#x@y>?Bc!LLB5
z8cjz(8O*G${Z!WfoTd{b#Wq8)=CIGommK*eQi_%BrOY9#2FZ^*YsQxIL&x)-&#UR)
zLcY{>%-n}s1n#iD&~z~A9AmX9{ddEM;@kBvm)7jy{cSSD%}axjA0KJ@m3Ifsr{9lF
zm0JH)3~1SVjDlk_TUnY=t)W{W5gx)Gc269B0{I~+TwMLubNo0F@;-&()7`rfI%wEv
zz^?ib=h)ZsOb6;FBB%x>QGJp&LjnzN@zu}F>>tGvVP21`mzWQ*ddPu}I_7YEJEw#)
zd3{T+Kbf5;p-V}34hIB3YC<-2caP{9xO&_k`%YclG01nzhoeU?%ViYJ-QBt=h%ESH
z50=--;hldUuN_c-&w4Qiw+*m%cuWtEmrmW`CQDy9*D@E(`J&Ko+@l@P^Y`_^1)%uZ
zc!}tJzaQ&h+V@uOHJf*?BaeM({d{n%-u`CPWjh9omi(+z{9e<=(b7w~52t6@_R!GZ
zrzw)+ABP$rU=XGaAm%2B;@}~>{iD&?X}6eqZylTF;ty%^b<TZ<+0i9=q2w-yAGVq;
za_k>9_<c<472Yf#ot4jM3#=jcht`(spCm`!Hz1&17y7{#c9^aUS;+-hN{1iO&X_m;
z+w7ytu8OiH8!E}HMK(d9c2`It^*bzG@6T;5y+--HIGWP)O0x9BbK^Kwi!pPT#SS^!
zmB-!{g`EbSkzf6N+Qtfh0drea*6WDj$**ofsA1WYWUdRv_K`#OxqhXIU9_OjMCGqj
zLO8p#GdZI6Tlbe1*fllW_zyHTK-*Ec&D{0v2;WtP=JJKuLP=XDTP+mo`@&vDI=9d{
z-**(Yd3;O5P`VR!?NGANQ<DDxUrsAU4SZ_H<<p(ojh@d0dYR&#YwTihj@ifn1Qa{B
z$ApE(xv#P*91m|if%+`%Fl&C2vUC0aSq}$$D+w@9_u{BoGMld0J5R+zC<*x2BU8*c
z7sFWj#&#M8pL;3_?DkRb)NmOqYr(94JS-<kZw#O^i(OeGVUP{K(kG#(wBHMFtDQ2*
zg-^0{4rSA}6vyu|sWD=mA+-2~&XAP5vhO*tKWn3wlwyC<IS-xCaQ7|x4qChtmGBt~
z)WhsMOP8&A>*%-M89G=akmlw)7(}giuiB1uKn;2$PNT)qzM)dmkv+BVSJj64o^P}8
zP9(mS_76=lDCBp=o90sI_GoC>rVTV9DfqVVS53~&(KZaCT<-yd9MFh6Tj!$Zc1Kez
z7rO1Io(lvG%X|T6^e7d>#oIncBx7d~PT4s?+^?X`5eE5=ecJRT&5M=!eWd=MJDaV-
z4>xMN`$ku+BwBJCjMdennh*Uic9OluFTmL1HT$xqEG(@-xytrgSv6+iq%jx_i%1?Q
z@Q;<|(zwdKy}J5?gW64Q<4!qQvg&_`Qs#<NdMLIAF{^jQY%fwUCu>7>KxUMmJ33qZ
zcI-q-10LHkD5k=v74AEdId|VyW{_uE>weE}Mix|0=!`eN%_H@|rl=XnBXeo4CFU3p
z%(2|XP9KWyebN*>ojFQTy3ix<9HsYIuhGl%${ah_`8mtj#gKhq{+{`9^PB(4mn-EU
zip8n{{w9_s)ce|@flXnNu#Ds}R9}=%v`AWxnf^*tDhwlZh}mu|4vPC?+=nCiV%DoF
z8I9su*XvW(5XRuS(4WD#qt|+0%D81l26ILG-(Qk&j&ftHbgKP=%y`Mvx1f31mTbwK
zVUMB&Xu*nV;<@L|=LkAGeBKN3>g8FEgpZO%yM4JiD+#f64z?FJ-Z%&uZ=;0V0VtEn
z^%ONQ;Edb8lHNJm`2OM|`RcW3ENPlSDYxrX6oCz|d2+i<Jt<LmiJPT;GqQ3=tQk2O
zuX+(JxG2RC03sVG+P+xCB}K<Y>57+MD7Lps+GAgBJqxAu0(fldqj6eSuW1_e&YgpL
zz4ZAgyQYMOkjdbUrZ{2>*OVr2W^#+#4r{&-rXYU=FZ4oX$G+!EjrkjzwnegHJ`57`
zNvU2s`QVyd=SfS?{m0JG_4jTxc83H5Lh0Qg*VrK?r1?G%;w#7^Fc$#fFP78>?Zgyg
z^E`<P^)oEV{ix>%eK<tvcQOX>eL5O1jehlyV_>txr`U|#jxv-8lgK66T~Zotj>vP6
z=P|p7`ObUcl>Lb5Y4R~4&Tpt!`L50x`Hdljr1Cg;%O%@TKk+KW6X*T}176HccRncP
zd|S%1K+%ObuF3b~^PL5h7j0($=V4>_emTi^;W5)Dm|@m1`HX1O%;gD98cNe76vkDv
z*J1ifoxuTJPo|pWI5kVikk4IEAR$8K!QMDct9$m7bRl0wZnPfiUx_{8aES8ldbf;@
zI7d|L&hnbN+4x)Mvze&TyRmBC_fUjbQbw}`D`!jS#AspL>eQCiBiN+6Ie*yPlSiPW
zOS^ta85mQH$5kITUv*2Ss1>1;x@?Q}$q&G*L-x6Qpqd3YSADKMB&pb^<gJ=iV8GG7
zLXsPo%FvrL6q(q=P>0E#BNlG$hTTxbT0C)*xLz%aC0EB;1O2$Dmk3^DgM!CURqGPN
zPAcKOje5R(s}P&h;OgNr;#qrqy5p8#b8YbKvhy2d5m&kP5#ZldN%GHs!^^_{7cYyq
zi1eFp5ou3Kyedh4+Y#gcMc4d)V_y9W?@iW&u&-k6j=y>fMX!J6twULFuY&0KTk_~l
z3}5j+n-~Pr-cjJeTTpw`DvSo_hC|2O66qUx;OR5`a_vUG{;|Z#(7L?$UUMNJ_FqY@
z-#(<@@aXuJLVCgZZ3k>X2xL5xfV~SILLrA`I=0?;?1#J%J6I%BL#+cSBSWzYOug2W
zVqi{f1%}+g7(8ALX#+tbAtM_I`65<RtN$lpQeo!38shkW9Q!)_HxD#n<NaZ=itR^L
z&in6lej8G$)xU@>K0d6s9^-RFs$#qI_J`qn`_cdS6?9x+Z$EkU;k&fwx5^)+J%dY2
zD|Mbx;L%8C-RyANC`Y-fN0kH@$5PR0Ye@yh*0QEX0UVaJ&yzSGom7kUKhs@~WXP*b
zonS9Y<FoJ~;4KmX^|+{k3{>fo++z>YBTDEM{W3QXDyrJ+e83re#3qRE_n4;QPHXG=
zpw%_x(5_CYbHBSG?sn=cX4TZCkQRsITHbc6;@C2(ZrPI$jj?mdzy5dwK|fd0;L5Kr
z$wV#e&4RS37VNJ@=DypMH8H2pQmsp}lcF_FFM7BM9<RrBgPu(c*wqqhq?S$Wtifuq
z5wxRB9N>b@8jmvzz6EV=-7!Vr6MkNEWZyP!Q$xyk=G&4zz7`+QG(?>DXzsY_U)0Si
zY93U@2OFYk`GHBLCinC=&09iT>BerFS}<sgEw9x8gACPdK_)U}qX9L~UEFQ7s$Di?
za^6R<-L4`xc6^QuK%n*vHI^HZeL(;}L(57QyB#?zuT{2agWJ{EaYk1l`-Wo6mzA=J
zc#wqThCzy4VP$_u*{wlaY%l7W0b3nw)A#=cyR-kdLcSx!xP_7rI960fD1Kbt#VOEV
zV3{a)5W|EuO9X*in=(naftCWA33Op2HV{FKMODT*rRiXgU2@|up!aa-F;#OvNMk^j
zVpBA3s${QeNc7SC8Y81=JYe~jsv6NHc%|5kGLq!SlccMGho_)ZR022br~t4qK#fV&
zLJqO%hee4jgj%>Jg2z=Q4)GRhCSqG05sRDgCTl%PuugwevzcR76k!ZwYH~tGtO5zy
zqEb+*COj=X9W}SDDw34_pgAhHc$T~eDOefZ$^wJ}zevCchM%e53^jDoL7Ubk<oYj_
z_GgRx5vr2OJ3;zd7DH<XQzVe}v(0)ooeqQZde!aps+g59b&ffp0>L@*tdgc<G_8zH
z2a#x7Kcku#Z4m1gQKc#!Um`)Ns3gpO79X6mW6P8=i$cFmjpI#1pwnk((-uFw+``y)
zRp)1^G{$H)t&d}$t7=jDl%iXo{@R)cE}OXih?eA33wzpvR{wa@0H0t&Jgq&IQi39s
z_VHFVFr8*rkKE&T<$}EgX{{d0{=pKp8-4ZD@*K7Gu?uyxlvf)SRzhT$R2;c0t!tSv
z(S?1^6zu1TMv6`@EgRhxhGM^tEalnZHrMU+bxQr+hyzP(g}K?9`~|H`L}|w!J35%v
zX?g6jv!ccKJ4bU87c69j_-!3ZNpCi)a%EH$nvf2{3<VR9i}{KM{xA&~bMs+}Vh`gD
zF6mVvx3(Cj(~xIhi%1aUx%duT8t<@X9O6eLs7LVTz<P%Cn$1L;u^AKC`^~=ZU^3%C
zBXu&$ckKr}3)RRm<x!@LPQs!&F6SLF#xNNSny&ExOjz9{_o?UmZBZx+pEONTSOm@9
ztWqIhJIe$|f&?=3`ap_kL2-VO8Tq(~KVexjX4NNf&g?4CLvGa4Z5ZAF${Tt-oo9FU
zG(?vWrzXN6$AP2OJ)k3Es)m|$)qulOHRCDYS_z_N7;)Sb^J$R=WFGjrQNex1o4^sN
z5jeP$UR?s(;oUGHjui81X)|sonuIW9RzyyUEmH7eSNf)NGv3Kg$yJD9Mf^?B*j}#6
zT!7DUu??*v#}!dlXcLoy5=L#%ltma`vqm3&e?9_76XG-SehmQzO`(m78UxfpD5$~k
zRi&C3&_o3D?Fcvhv?>kQ+E{}H9|DZ87MjuqD6CONe)L<3;xeUn;c*r2vjBY*DGc6i
z$v~?WNKOLR?-J1>0#gwQ5M0PMg^pYB*#cGUhXD&Jyy-Z5;$o&)z35Qyk`lxyg!n1O
z>Fj28b9giK%u#8UQUgk9t1jR8KRyk<47#|e;8X(sAU}?;*iDEEzUAg1u@oedsq{SL
z*<jY9!NpX8u=qP-B7h^XHX1WRN))10(b#W$*9LP9<fMk?h{7Ro*o25)LEHfw7r)?o
zVL~n7i}{UZ)%fv`8syEYG9dE^zd6K5ZP`L?6G(x%XvMfx!2HgAO_EaRK+#1BGEfOJ
zL9>DBiXD|sG&I>4pfwsmmjl#Rt^HgFUx(XU6`$pP*MR4$5BW3ragPM6WVBJ0cf0m~
zC++>C<G8Ln&+b->VLX`$s!#wMKS<&|R5uy`Nf0eaVK`^(u7}r!1_Tm7t4Y%u+hR8h
zkSyzm3B$BA=VXj-HY6&RjtLmDr8CZm0AY@2GqVwCSjlE)CnO9jo|)u?#K2nToZXEH
z!^|I>Nl2L1W`1TruK?Q0&hDPwvjqr*(DmchefQ`0-gjTjtJE<zm?%-JP|EPs*LE{%
zCO&L~a9U{AVZ{vTnd$KF{OfX0r-mq2>JqrVk|lbb0Gg=iG%GwJ(^1cy+Xj?ceW;T>
zj)(}jp~4-{$Ls}07fY@n4kGfIr1oyjM@1sy=<AIv(Gy%r>xW|2@uHFTf;TD-C+nh*
zlBc29N<_-~DC*p45zGoz>E<y<7)~W3fIdCiKSfvw7-1n2C_DTD*sjUDcojII1{WA7
z<<-i)zB_f`<|K+l-8?>*7sssVP^2`!W#f8OWglkl+N6abyEPd(ExqiActqu*^{Qo6
zt7x9K*elh-jI7|RnU}55hpc+TuA>F=ZnPEk-nD7l{*Y`F(N|*^ZLgMgUtMd#gnlPV
zmgk1^G3yza!rN^}tj74Lmt_i0uSl?SB^u+&zV?G|yB!l8V6=73Hhrh~o%LgND6))<
zv=u7eQl0YAF_8$rXlQCA!eyCUe1=!A)NyNg>_C(ksW6H0O7_-gHQg8MtY1Q0B9VsL
ztmRq+Xwjq_wS?8Mo76S4Mo(=1xg<<N0;S7riW-!Ao_^-W6=izIO7K7%Cnx%2x-ACB
z?Q*FtpP|Yg29k8Qkpy)I$%h?Gr>e5L_8<K*@rO5B&U-f!4X0+D?7wbpeARo;xpm;y
zsk4rHxV7Y2PEqf*8@-46zCI~dlLMK-vOPMfle;?3wob}FkcXw4-LMzLul8EbXuI{#
z>(hO9M=yn)2l?u#xb}GLj5_7A3-4U#_!rurk-6_7ma)Bw%6As+k5*sHWU|BZD_wPQ
z+L)jBR%GK!Iu{$a^XgQ!{Z`sKRXu3`>#sB;0`7OLwU<0umU5u|ZrVO%r#mOz>g>Ly
z)V)1VAGTf(1bfX}C%oKQ>*IZUv7fm)=il|V?kRZ<!PwZ;Sk8LXvfQzT)q?|>0sCT7
zH|RpC|7?3PnfksviMz<^p%r_Ne5_>4hEtuXPl-L}ADgq>rn8ODk~{2=9UzN8*V_n&
z?7o_5-zSIdvfOKrR#=VGoOv|UKUQVo9@XlHokXVYTzb*&I@=fPxN+SM62e{jXJcTl
zzw1(#>b~~am+XPc%u1R&9?M*pFUyNZmR?<3T1($Jdi=;~Z@j)j)uR<19&?(6XTaW>
zhM8z_ERk(^m<S_VY&C718=GQ!yk4l{V^l16&{yYXJ5a6D6svuMez2uVvL0;sRM(}j
zthth`mZ^?5KgMGbnm8xkFz0-u8l#T0N{^ej)543<y9<lJ8C2nz|0Ic-nCYLvvSFHN
zc>FjYOa2C>Y^PE!;xCIIqQ3A{{g<piavDBIL8H!nzW!=rESI`tu?ysrpKJCewf?r9
zEA*XsxIcfRHmbk->l7{9#qW0kn2h}j8-Sg(KVruk6i9Alf99HfTb#{(E;+Aep8V_2
z+ed%$^~9sMp7<sxutj^&wP5U}$RAh6++VTIudR-Wzbiq7{^`@@)`i{^jW3UVbC1^D
zpM7Oa4afRF_8W(4KLq(by5ekJlEK@V*gs>n^_ZX`G@B(pnd;7bdExBv@49mZ@YdgR
z<=IzHeRKGm*35_6JT_UAFIQ$_>9;=eaFDdVL#ydW8@wO<xwWhD)HlZ$txE3XI2$<^
zZMR_{ZaWRpT=BJZmnzQi+sX2yVoi^ImWB~w-KaxjRej9O7FrIv^oF26s~8);B<)r9
zUMrR!F{|TGiN9-AW(t0Lr7-@e3mnz3nr!~jf)^-&p9>LiKemt4PE|E7w%<%!rW%zd
zvwxUdY_Ht#?3WkDe=kMJ<bRizGtD6Wrm4l3t6*97R>zsUj?*h%9oziefOqQ8$M3T-
z0{=Mllx^&`>O87!PbR@%C>hR~Js-iXiaC1vy5lDeMk~S!UAH;vnqNXR5d82XR8oG4
zX8N>gT^I{Q*BOz#59%}ay@ow(SJ>BM%~GyewzE$Z>`D%3k1B0cXtgWGYWs+ni**%T
zx(U=SS))OcraeJ&Ib)y7A9CT-f1?wl-=w0k*_~dn1dx8>OP1TY_2JLobs8J2OyavI
z{ocyxqumyJqhY4@X6(8#&mP@#w$1aRqyLM{#t(_CWAPgPN3AUQV5CLje{{u`zJH$<
z#%$OZrA@)YrOdI$QbY9LTDd1|;J&^j{9u0-WcZ0jc3K1-TI}7|?0H%HoAPakVkFNK
z=^UU?-6<e0O2ZQdd(AX^f3B*%iB*G6UZ5TvwqRBa=bWD@WW*o;!`LzB1grYfpVLu5
z$ptG&E?JdZft@Yp?9oRX;>}Sf@_KhHS7^lRdvrm%Ng&f~EYcynAF)q-TQH~NluMUI
zLp1%zrLo@-Hv^1Q$eY#N@Rk(kmHiS7SLnKI(VYV*3)q(m^BE?q*#cvZ-@E{xAxDAc
z?Nfg~9bHPk^w7*RD)E}VWYAPAMlGq5X*XyuTv$r(`s+{s;%HzcmV^UujafErTCOJ=
zPVAvyG7I!o#7@%K^EaAeL9P;W$LsNUk_#|-%mwA7=L9{5kBF?T7V2v=cC67x)}DD3
zs1n4pM7QP{3av)ROGjg`e_f<&!5M&MkAd#P|MS`k`H~oYCbw*Rr~a_bIyLNOYB$pM
z=%LOkHQN+vjF`bXV}P?4%&+_JeCWVfXK!UDPruKZ=0}j8Cw+pRCz8}?JnZHQ{aM?J
z<@|rpUQvyEqEMLn<}-Wjv@0T6N}k7bWZb!8QGV-1|M<3N#|BCzSo{$>BtQBQn_fAZ
zbODXIZT4vdxI7B9Z#MSxPQ9w9O%~;v!yVY6aOTufFl`Ml+nigN05kvY$2C87ZV3)8
zgKTo^)$tV2)EGeJ%awimg1cY*!)&6(J9WVkwV5X$>*YtLQ{|iMV;32;y{mC;G7)nZ
zdgW3iTWp;6^m(94mP&Qob+-oMqa!-<aZ1_08^5_arf3xO-Qro(@<uoOj#>DUq|({?
z9N6}WzZaxObuNCrMv1!FsE}P2b>t7c99^c10Yx#*59Nv}>hU%8!J~dZtK5gVZD|@j
zc^pyyV=sF5KmX_K$5roj+npYBH97%+IQJo3G8K8Wpf6c_Ss0lsnSk4472Csj+mQp+
zsCO{P+Rv#(VtDuU))_~R)n)=aolEQ?5#=Oj)0L^TEasxMhWV!xGipASU3pa)r*4?S
z;Ruc3>WYo&$|{)ZK|)Gh^QaJxbX8R%O$s3&`{J9woQ)>v(ZSX)A_^Nin8Votn&i=t
z*`fehu3|AUhzqs`pOD$}vATAU-gvFg%Kl(75hbEbni7*&t=;Jw$qyXUiwbXvx?rAD
zszjvC=c6*hm7_A7c%vM_I^HZ_SY*8es|F;{iTL&3`e26%S}}YfvHqYY7?hEA4zKTE
zr+@YTgq@nI-t9)f{F3^s|2Nnv+2*6m-w&&A0XX^hzwM4}KvYv$9G3Au_E)Bg_y3}^
z!~?i<r?bTWKN$A|nCVVm<E`KN6)MJS`1KV#OYH=H{r16ZJ~*ZcPioV+vP3pGvC}d-
zEuxpqDpKPT^TQl?(iO4uwLpy_U%&}%RvyTJASruq{Q2;_pZ#Eh|8I}Bn8#;7AB>5B
z{^oJ_(cfyj?G;k;$je^jaN}^aQQ@nL8rtNlG$Tr<`^z?A0GqHyjBB6Bc=e?l^EWFQ
zDHD~1c!ln|U?8vA=cB@#$<Q#MFHu`<t5k)Iwne$%qWu{e$j1D0)&5v6z0#Midxl`>
zLX72{#G?`Vac1cGJbnJmN^RJ_x5v8Zq|UWURQpn-9XGr&9&v3}M<)o|2nA@XIY&&(
zLi9-Faht`i^f%S>KnlIo;Wc}3`tD6yquL8u?c`6TBaJ2)YKyXNxijXujYn|gTz!e2
z<8(>|3~>p=D72$sP#;RHy2DadZn%}{txtY0LJ6qt)y4I6v@{*f#wuBROk~U?$%vCC
zoIX&E8NwbZe!Nskk9JB~yGS|maFw}i^YSsXsa#`R*K9dm76t{-jB4hka(|s(bt#8+
z_?#^StI;&q5zW{<A~HOeepSr5YUKB$(}pV|?oBra2pRDrqAlaJMRnwStlvN!1nO9k
z>)=Y1&ge|*LlL$(OW6I3f?c1YbSAMW>dQM`;=1*kYs(+5fSz%IW=36#B|&Gs40p}O
zb3|p4$e?+d)Mnxr878f4B?VY%VYrfVBGA$7Zkru@q5x4B;#8ZNk?~oicBF;|qc=o^
z22}ikViX4~CE}Ucf#^1`S4pvX8jBt@O}?wv?(?b^qp68!v!5H!`rrSJfkINh0oIc|
zm1HBwc^kY+5Hz{kKJ7*1`5VOP5wm2U-MEAu2Wp<)#s0OWdQG<x<mBv;CHseVv_5(<
z;iM~V(qmzdtBzTzIK_IWJ=V3??Q=o6cOQt>DEKY&&_?C1nm(4f#1efm8DTs!6Cd0<
z_Mhmk=w56UmA0za*Lc`|)l;>#ny`uqm{LUShJ1ATd|AP>yDK6RVP}ccRK!P8U>R>W
z#VGUb(}{>~!vW-lY4vzPR3rs<b!qjXHY;|CrjL_H+$ai|W!4Cmxlfv1-OjV?<`t2a
zN918wzV(IObu|c`m5`9~H~{7*Lv6GI<#gQF9Q17g+}TaCBt6X^v+?ln=B99DmLkxH
z)m@kQVUT=gIJUwK&R6F2bd10J(dT(|*%Of)G%%0jz|c9Jd2HMjab}|Q<X~ik=QymV
zE7@PFMW$ogtc*^i0>m)uil}Fv1ImzQ4BXp1l>aJJ$1(yKqs^4pf>Q66nYKkNPWo3~
zH-BgBonYQ=NC@`?$_`%!Ow0@%IH1M~2f!`VkcK*vnV|qI3-*KfeTZ|iF*%I@u;mmS
zJ5327+RWf5hKzTwt}|%E$sC*y0B2I}zzqCkeCffcr{Fspl+eS6y5FB`!fCn<QxwR_
z;pMMr8IMfs-D3M*7geM-Eo0O1$ZtRYx3g@6T+4c^4g#xpUqlUYQf>RhG&c|buZ<er
zOQHr-nE!8!*ItdkQaO(>McO2jiYaCs)5!2NZ60<Gun}{vbnpN3-iTM^Ar_mLA)i!0
zbC_9;^Q7q&t~BI(B_5F^m@2gteVZ9ByaHR+Pyms<2WO!sq7}h&+G1T?$m{GpNI|q}
ztj(>)M-Kjixo3Fn&~4}c46}UTXybVwINT5X{()ad`oo)ng7Ua1d*-z<CXVnAW)i~x
zV?>b7KwBK<_mF~OI=nVK3k}Z=OiKgB8$}{7zG*(=Z#7FsB3b5!4XSJW$qbS|(_<Zt
z#;KCOwlRy_Y*4e#qtMLhkq3WAv4y9rY}zw_e<f3kxYKeDPK&hNd+A%|j{Q8HcEH?|
zv=GZj>CDo<`|%4rZS(??Z9eTyTV=+fuc?gS-f!1-N0j+AtX6FJrfld8FJ?sj`D?Xw
zT=41lwm$`s7K%X`4&%y~c0-n#-I2CiZ~g*v?M+8VYeplWIUS&4bMT^?w<g(xjo=*<
zX7vhFUE|Nw+w%f!I$a@y$O9>Z-6l7eg~xPUfGo2=-Q8;+t2@OQPkY?PqP=D;k}dOs
z@L2y})i}K_-x`m!EdahH?sZa0FfF_-k8-iN<v`exJcXR+6+etK!u4r{YQz1uif>=<
zMugeTL7N*?>ewg;lA4{;jk@9ft8MW}C6@rl{8t};FmEJIc^@-zk^bG`%=6lG=Z5st
zhCXK69!xSBW=_t#iidyT&*9wv&6Dr`mnV(gjWnZ0vSt*KPHuI*#?+cAG7LAG_>zQ6
z-Zo>uZl1vm&@K?#Sg*t)Kl{7<*#$MM{m;&?z?-k7Q3#R$bvA1#dL3Ob?cE{(hd2j$
zWpmdNv$cgG>of$3I0TE_Is9-sI{Y7M>{DUXH^XU;MzXi8>Vr=|a4C(${?FHb;M2(6
zFPt@$)Xh<5{DEYI#4*bFZwN-@J7zGv`6Y86V#L5s3)RNDASA%(mhk+a$=A>Ba<@Fj
zM;`x~V>-&Hw-5YV^9!~644h+{?%y(I68IrchNl5hKR681{qv(%`N+!O3E5hEjD%TF
zSZ|A75uO37n&+8L?X?;f;;?Y8r#Z)cxGs(_#xoPUQ5$U{+7_*(T|ahEwc*KV%~gEV
zrW1I{sK~i=q&<F`C_1e@j=SG7w<lPNa3!~UXu1O7w_n1{15ex@B7c)@RRI=gM#i}{
z!|}M7)aZsURIBhHFz6k9RzuBk0jK||{G~mzr*U3L*Vhy7fIg^HZQw$!{|m2vuhzet
zC0f5rXY%}Qt2${dv?pw<Tm9;k*eZKKnj89iFZo-mH7@x~Eq|o;2N#Bq)Dr*SFS&?C
z_>xs)=O>ZgV;!vuT=@C^2g5pEd+r%`WcUZtjsI+1R5om1(z@|rU~kKLmAY20Z4Ybz
zzK649*APh0$Z6%UQ(?wlkx>M-9$Bp`NrggJ=CeBT3^s1T&PVEp(p={L{IkOt?lyB7
zdO5u12R<`N3)vQabV#Zn{?^}e{n_%(RG;pQdk1xG_{ginyDNWqfnBa^ZMSD{h`otS
zf~AT5w?w%SMwl(@gMR<l)#2K~)tmVbo_wRJb*<8V-YVHgTJKwv6BSi<I{o|dzd5^9
zIZyIqUn0GI>xIlg@9&j&PG2wgt#-!yf1rNpwc2;SS7YlWwtwL4S1W7mlwt1Oxh_*L
zDLG%(J?7l||9uTMfl+D=W3vsjB2pi->TMdE9uf_Y3ayDwwAOIDeHgEPzcnXX<jz+H
zbmNxwzUS?4ye956t^`BXlX`Gjuj&DP33fK$hTl2dx0N%ed>BaAit1DMeey&DuD^>@
z>f+OtN`)2=3%$(?qDM^GTZM8reH6N7N9xdoH&Rw7Rg$ZpR~>GSu@tp8;I#=M?hXGL
z(pRa?{9tzNjg7g<&a<MD5%qFTq#N!D!7%qGhhvN(GO9hk%^P_4ERnixZ}2tADKa%B
z?v=c~ps5>;lfgYV7<S{{fL6nC9_6sNPdNO1yECaKRYn~Mf}D<xpLBKdq#S}WMV)i0
z=w~!Sv`dbRY_D#*fh$xp(4OC?pVvKl-cJ_FM!rvbc6jc+GfQ>(Qx^ayE3c*BoJ{{(
z=WRQ-$F@@5Rgn=*_5yX8S{5|wCl?Z5WANLo8`hrsLsq86rqBW7wx_Y-tSFr<KQS5T
z_yDxzap;a*k?Xb(r5H!S?~g0prgeN&HwNDJV57~^qvsbgiNv#VDJ6O))Mj~7D|?rJ
zGS$JX<qVnaOID(}a`wGAZbM~;){?STU$)sgORfkWpSmg*rRHhd-w>K1c#Uk%hyRgI
zWLhXNB=OYWwIH5dF5UM;i*C^$)x&ZbE{G4twKg!=0}eq)x}r`M)dA<^L~cE`&RScX
zd%9qmR~NC2%?67-l$6_UPcl<JF3aqG805ABe*hYt44#Kc926&KbBuiDZ;@b4oO;9B
zGq+dlu^W0tO2k^%D5a8n?BTWCT(UnF(U6xpHoYabS))mnEHu(y(d4Sz_7yc`&x-y2
ziXL+AYhAajYlem%7lnL520Wh6ch=luFrsVswNF9x0Sy7Tsdl5FjeOg1wslloF7$NJ
zpS&k^g+1jCsu69^vuh4eTJkYJS%h+<A=zyEMK@ll)n<^%Ulm_3Sgn(yM9~T>Gf|bw
zdLqWNy)1K??PG%`!b%vr^_sZc-jcCfuZowx?Jbu!?ZseE<No4%4KUG3eO%w={>sb_
z%(Ol9h}*7Xesx~ml<VbnHKk+66<=oJ&CJ6<ZLv)AVmsg6UbpxMS7djpM_yB#{#tpe
zd`;h1YJ8H5wC}`qmUrdr_aFI%aO5<2c&0kvgmY?LL|g0?(6dDr2b5>LK4zTrLl&{>
z;r8AZyJ^W8TJc(!Qc{lilcLW(riTLU_i5E{1{2v~k%LOKZ@TLeT|k*?()p@7rZ4)m
z!5$^|9C%)Tg$nHEZB25y_h7k4{8Y(q(LK=}bo&RD?Cg`?i<*i2lw+%S$hA{!BG?vv
z>yLJayFI*?PP2Jp#qMQ;Hp_5&cDx`B$q>O@+=I;rypZNsEn244H?>z5yl0c&^@hrg
zUF+VuW3Os|N;@?-B%$_j5{wwuWzbx1q|I4Z&Xk_?Un-W#6eur}bB)@77BMN`mM3J7
zTavC6JsKMki1D&JzOL8ZqVypG57&+CIyxQwi|;>B9S!M~biGuwLZ)sARKZzs+b-M1
zY!SioJhWa;PdRKZ-4<=06J3?L-WJ(ZS+%ULrE-0BF*xQ9yGC2<e18pw<u&8m+FEpL
zzB}Axtgfg=0vP+4er`&ibbUV#IYNa8V>gRRwE6sE?=#(FotaE`xkqlMVk4@Mdfd;Q
zWC@e+`ik5%!|4zC<EiQ|p{!AR&TE}5a^?-uG>JQ9-L%X<^>dUS1`2W$beZvM8-eh8
zt*$w%{#)X<wP^p)nR(YsKU2S$I_5T|Ff~l2UyB>Xr)eP_YP{<TT6e;o?enTfPie-_
zzK-Mfebw2gk`qR9b4<EXDY%Kv?F)}IFMYH}ypvfjza#tPv--ZPxo}=3C;e-_Ryq#h
z4?CXW?~xwE-yHL)KdF>$XOHc`B#zTmpwqZKmXs3B5Gn{S8+b+w+0ECi4f_^)yX*W{
z#$Fg}aaeUc(W3Qn7m=hvdZ4j2c_Ve^IXl$P6Yr=4^SJ1KQH})jx-`D!>zk?%vef;|
z+FZ8TrHStz`BPcw?mMvIZn$5S$IF9j6N~z=@17~9dfX{9t&UsT9?h3o8waLv(^8c+
zYfA|FVBZjFC*|=o#p9VNGz*M2=&fs0!&g6NS?Lx^N8}x6)jKXuH+D@1xg~$FsMX_o
za25LG;-eT?b7bdKXHn*rIuL(uJrxAc-PcguO{S2ZV@_@rh;O<QJCZn(NFV4`2VSlQ
zuIuXDT5#X@5AxL!JWX$K!|LnWns;#H@BT##x6Mbp%2g<w#_quDT`QtXX55b|Gv~}a
z++y@f)`FFY_gc@`U2<uPs(x(xn)Tk;Rx;?9aLRFgQLAlX-cf;~b6y?fs|Ry^(D#ye
z0_R=-X?G;pbmLjrFt?*CZ_0u^sN8(#V@l-ag9B6QWa^kgAj*cf&EZkl^x-#gwQDop
z1=XA0u{eyObxvS<>aQj3KG(2m+!znWtp}so$^uSS*EO+-Bh^yw+H`(oZ+R?B;Q!nf
zcSLQu+DAZ(`ZN>2%~&C!5i2E&GC8U2_0+ufl6`&;OrE4zox9IF%>o@L7GxUBBM!+!
zg##s*QVh9PF6++C^0Gp!U}v9(&5T>*9dnMMBBt;CtIwG?sIYx?*?vWx<qj=Cnbi%N
zqVG)>pP+z?kw?6&nQ;Ig@k6_+a1@(fTK3$3GSNEa-7Af!&L;bU{4pBT_6J7T!Y72I
zZmY%BP+VQq$3nsF*Ul=;!-Qy8M2TS97VDeE;^dPHxwfTLIX}Fi7JZ+4Ea{;da}jzO
z8Vn)vk&P%~h$e~Rv{efh2BvjUraVMa?zgvuOC1LTHM3_f^Kt>^EHN#rRVh$b<-BTh
z@2EREmecckFfeRPzK|<+<gZg_lz&a}6Nlofet%Kr)>5m=M?_JOy59t5lGI(|APW1I
z{Cs(<3=6SE#X&W+mO@gyb^DY$r{4EfI|>K_w?)Al?8IN5pbjcKOSzDtZI`?zWGIGv
z1%CG)g_B|!!%&2=<l@<QB<n?6sho@C4`ChUP&~Du{MA6_R`t-lzOMVtnM`3w-<xvP
zSa5YwopwFEp{Eh2@wH&xol?qFX<-n|kyKks`TTc~b320mqC4Qydu&p_j})q&z{R!T
z>4?bP|M*?_**K|hv=-iUep9qoSA?8iWAP}WwUXRl$hZS47Y8LXCfca$Xgypf+p6c6
z95r#<S@!0<7WbpY{Yo1D36=3UVrY`H#0KGLPP_TMzrheUf<Qm-cR;%lJ>@@!67SJ2
zlL*aG*UiSV8%L_Q`Lfu@cDR4mu_5oICgdU2U&d#c_YdkI=Whhzv_q3R68O!x|7T-w
zcmX#3aA-+o+|@1_`=Ko%{YGJf@q3{#n(24&0^2Io#_u<pvGrT%ZE^nmoyG-1nP->9
zmPnqs;g0xy#xu!<Khc*v3L=8C?sQ<8vU?nF^q6|l)rE-;cl@io2Ohcc8`}PcbJDq0
zD0FU3%C7gzL^&N3{gduw*=HJj8kc86Zr9qimW=;>Z}mSDp%E#}{K*CQ{X!SwnG))T
zzyJ}XmF(11GF055=Z})X0mZ(ZW`URz(W4voL(e{(?wa%Jm*f+Tn^+NFFSDcvonowP
zI1Q0bGjtfjO~M)d>p>9sfjj6d>5jlRQg5WG7KUk|`rdR`;r;iG3;upt9Z#iJCtmOe
z^_(6FaBz5phqoMf9vt!8|I;rs2^jtC?~1i;v$Mx;wJ|wZ{{;fD6Jy3PgqCqwU&s3`
z7pHbX)K|YF5?$5GhQrR`SAzWxb6~Wa7p_MdUgr&lri_wC8|`p5L+^0S*Kws><vq6^
z6n*unbr&-Q%fZqf$)5yBSM%lGqu1=o$t_#<v~Nk-11C*P>Z#QG+J9bqpF+zKQ-tqL
z2xQ#&dz1gAF3(HUW(H5aIscUmTAKbXV-{1umds#yNcpy2Wc*Q^vfrjh*!K5w=IB!K
z$=a1viyHFBom^jVQ`c5QDKNIy@OMamysgu2C+pefm0w#AbUEm7Uv%+eT*IF^XPcBZ
zLx&%3k@=e(T6BkAdg+Qg?DLkvG3Ab{M)Qg$NVgBa1*TW4)s^ff;$ft=i=i@7qOlFN
zl@$AFOG^NO@?Z!%Y~L6?vcG=KI&0nN&Aedk^Y%D<y+a~@JlQ{?y5@EMxbE*mc=5DD
z@iN1vo<_U4RUIxg*QNGl6$Jh3J`7MmmlDrVS!pDfVIOHe|L^3Q{H`2&R}O8ssGId*
z%0K7pbN)%$K_?mWmN<T9g8uUP-Idzth0zONUwd;UJ)7z^k-P&pqu*PkiR}9&=fg6g
z&ve?bnRnY#QM*;n_O^IK-?o4woOiv3TVrb{u8CFcJ+6mq#(Ua!;tf29BF>-!yLFH2
zz&9xBnzQRg-i?qW1zVv(9*mt$Wty+q_igp$`vut}s~f2$xBsi|A)Q;*XEwFQmB(u`
zafJPuzhoctFsh#!OS~rjk^G^3O`zs!;JR1TV@6$~BHOqh;2vi7@rck#V!{5fkj+=<
z?{T&?TWVUjwu0nSD%Q_iqUiGj=*%L%gBf-tFR(6)`nvM{Vvx`C;q%%(0Ds5B(EI13
z?qyG$ExXVowleZi`A~UcL-qx!4Hf8Nr>OG&NuG~#3g!B2-@_F`pi_WF1vaTm;Y_7&
zh*le$dWZ!O!i0qwB%?4;EyNRxvgup6<c*cfXIj7E4K0`C65hq*We@W{6vw0@t8tG>
z3dbzSXbr6@w?F>09(UqroU&`Yw_KkyumeYg*vU1yENeBlhOzaDFp1L&NX;D=dqH=j
zzHON0Uc<*oMxYO8Ze5rYGwDeYt*<JtWaA>XuDD&cqs>^kJJd4~*hL{PiM9oKG-zzB
z08^EYdoSpLf_wo}(?<lcthH-IXUC4#t*D_T?b~H{7(JHHZ7Dstr1ON&#_b6O7QbHJ
zW9NXM+N!7HoJ51XpeE$G)cYy*Vz4fYsS$U|FS|^ifl-h!qX<7T^zgPdI+Yl0>e}iQ
z^;<Lpuc*qLu-eKhRl|Kl2(bQ!tsx!>@pM=9Onu@pPh8edE>4u6z2cWg{590KyUEZQ
zW*D&l+;t(UU&R+$m#B`UTU5`jyX!hW7{};F7)GNTDiC2phfLSy%%RB_3I{Vi?j5<M
z%Be{eJ8)m&h`$&VC!WTGNbWLbx~>+&7+<`xYbUs`y<FX!e$&2ftEj}&eOs9DXGB${
zBGf?1a*@$mw8~f!?2Oy%B)VRz)TV?rW=(kC*D<5E2Q)#CF+jX$$RV9hHI5^&=@!c>
z_l_>6hSvR}I<usWZ2+es1rZ+I&Vk=iEAqg*vL{&6YpHYoIlW#k`t7wPV?K=L4ypa+
z*FLl@iS%mtTJ_6xjUZG5u)^c2LhvTs@>!})c|F(~dVA!uTW4``F1H_P!71;pE?ak;
zJB^Fwp%pz~AHp4<!sM8kji0cA8G1PK1Ix;Q5>x>c%IGsCi<}hT01p^%zY(s5erQ3N
zIJ(e#^m6ZqW%G{(rXMKFSf0n^vs)?E{#8}_v@Q*~eId)hjb13o|KjrxT(HX5sxRCB
z2w2dnX2kT0Aht*!a`zO5%ZkjqV_qGe*XA|GELwe_FV8~pX1CmM3GN+^pCGc$<GJ|w
z-5@3=qS%guMx|m`M%S2|h<i{S^FamtVk*x>>Nc>=aQd6Y`GtC8H@{_XP1@b#*v)de
zC&eptsK-+s<q@e1sUD4DSCb6Ic!dVmz4x8JzXMjx+<IeC&it;3waEG^5c8t6<Z!{;
zqxw}Gf<jU*JM5U4A4JPZ9A&HJtGH~{nd*H}YMu1P##-F5+<gr;Th#f(nu7s`Q!uU9
zq|xHZH94h<BsB1Ri{%pWzpp||!OQNrFWW9;^SQz`Hfb}E#rslqtJD;l$FcjgC_RTO
z2={vZIA52nyZ*mr0x<kHo306DmH=bTTEo83VEk5yTbSzG{e^;2caeyB?MB_ls-xDD
zm0GYLGl1=W`~16>)AiDX<2*Z=)JwiM?9^(;yEO`BoBh$|1vyldt~(s?S|i#-Xu*J+
zENl}7t@}58;O1ZGN&ZM~;DTX;Wv(wZ?m%`Q*mTug5JEXdUfvqPmYVU8zVVgG^c$V^
z*MOHTRQn;m8gAQbW0T1l6`pUBQ>R1q?lfAnR((axTGpw(o@yAghBkH4Ii|DohW{O-
zHSyQBxrc0F@|v1b1=-<>cD<@t8lHS_!gZ#UjV?g68vlm--oCHg(QW{jYs5{mTebUr
zsps`EKe?jYf)Ejg`gVx7ym%g!6Z-FoA0+0|U$dLgn0ssxFCxEKYuSDZ>l!0cM?nxM
zOo8P=_+G1l1+zp8O|@QcddjnIX!Qv^z*Q_$f7}n1C5CUC?({=Vmfd7V;j}-k4>(`d
z?M2yPSPSihCNaJrp<CC2)pfbI>ze&5Y%wRhCwk;$`C2*Np*{_>jju_dvD4rXI8_P6
z_TE2v<N-oglV2y^AZ&_s%^9Cj?uRPSB*N`s7(8|Oy<}ZSgC4P(7RtxR-u7U3`cIec
z=y$xe9J+o}JIi<^1BN&rBMVvH^;eW@fQzJE)`QMwP%QTZQ_2VcRQJe`gr4BEAY@wX
zB~leP<R@i!d1z8zQ+>Q~>NvIv8=IW+QT!f`K%aBTV0!nC3;+WVd0OcPd>7k;*!*)=
z%!<9qV=g?4c0$#75gV?wO$x8+vS|8|HP_p`YPEQ+C`kWCZa{lCQJ8SD;g)dV4;+|j
zcUi?5yG|}Ehj>{W)T87P;$ChCHDi^IIZ`qej|kPjic{XBop)59>aPVM>@%<pXxV@K
z_%A##sxzHyZx$@0TT-(ycfD=h6U3)%8fr4bo>6#Cs2rQttk1&W_S@Eqx8K@u?w3el
zZF!<$+<pqu3~w6KY6fkTQhZ0to0uYhNe``R{kHF}`_47L&li5E>Nv~D+IC>kyjZfI
zTzs0HDa+*nU#9wW|CBcNnj^0Dj#_zQ0idN;se6W1U7%~Yhy@d_T@`cUkUORa2v}fL
zSi3G%M#dGml-VbmjB0G&Y+Sb9FNu89vUo>4=B7+6)Q@7Hr;DU^_%_CuV^nsyfK_WU
z{zKQ*C*?7Jz(q)Va18p5s}UdY!WqZ?Yz7Bicx0ae6APIa)WNbmaK9YrL*?gv=us>m
z)X%Gf;0;VWz%0_4IJ~xPnG&p1nelGhFi5X(8m<c9&VtnhAmb`Dq6so^)Oi61&)s^A
z|1!?eJNBlvX<yOcHZP1nrRReF6@sD>y{h|R9_$iy-&QYKRR$z)H()L*aan=baKm;d
z21nsO;)#V4nlZ+eH|P=fCJWt<c6aoU88+@@>b?wyr~DdM`hG!$h)FhXu*F)#1Jn8n
z%|t41+GKj{SjuC;1-ZDruD91s;f<MDfTkn@@ztv<)`tZ>1db{K)H{vumr4!yykNhd
zNj~oTwfkBRFEbYm9-XwqI7ziZRM)NZL;9R9y7<3a_?*Sm8C(W#o?{Yrm^pLFw!1FZ
z_sAc~+wM=wWtJ^$r0%#^<nUJ6H%Lv2*)w9p9ORf~{IW#zy#q(X^lknJO>31*Cy6WY
zM0QA6!L_U|O6MuHDEkZA$SV?S)G-zZ-+>);>$^ndvgrD8!=}^cHT8kiyx^t>{9y-|
z(FiOA=KYyNG8l{61$C60K_6N)C#RUH!6~H>#?ZwHv2J!7XHhwg!E+l@Z^%^{jOape
zAaHf(I-+}Ag}OJ=Xd<PVU)oM7{@@M!3+XR((q6korc<niy(fs1#tgJ%Toj&+wF&cF
zH>^gI*ZV}*ZIGGv%C{}o=t*Z$PJCB<B1n-~aolB%=zd_>k$n4-P8MW);0`(KzL_7m
zNY?@vZyr)?2Ord%Ua~J`5?wz6&HHItCb3J$)d9PfA?56^U=<C?vrLqSdR(xc8hZ%7
zhD{daVPlRKWu(bQNvbK=2?Z995)T;CQ89y?141L~=e(|>wcpt)d3)>@ecWx4PXO=c
z`WS~B=STc!?pTDd^guk{i6ve2FX>=Fe_9X5`;AFQ-D1~l*2IfSNgOy^ARgUz_JuyE
z$xXZ7fq5Ut(^vqbZJ)aLp$g>=r>q9+7EnMcnjU38hO~v-jv*?kZ4Cn#8e`rzD-51w
zoZ#vem2XKslWu)iKkj})zrduQW{mvDTkTk&2$4Td3qIGnB+W9stgs}05Iha7jnaCc
zI@_TCBuWU3odSSexRtqc{-iE|J`Z3sAAlQQ{M0TS_Dc3+Z=7FbgzPI2yGajNt98S!
zUUS#9ien%=CL*V6w>@FO{p@vR?XM>fx0pHlBe*zIvRahMF*nQ$gYD{m0w1GEf2I+$
zWdsPpLmkwLdc1KJr8Zc@VL@YFbVeTBwu`OC7X&}|+56PcJLSppit5}*opYVXl$%@j
zr&J$d5+q*N48?%$(J$_cSBySkA=cbv`U`1eH)Zy=U5$|oP=hfu#fTr8%~>@7ed|5T
z+G7EMRc>34Sk};w8~%yt3hce!-f_~?1+4~%(&x1wH(~%bW~6W$oU}l%U01ccMP16P
zBrZEt9pL6#>v`vK+6EZ1Y>)pC(Z#)j-61+npaK1lxg*3JKt+%F$NjezQv_*>dXP)F
zY~c5J1bu;^cZLEAW08Pf+LUV&vc}(o{5T-|o23b%kQwT?>#Or#OD^BF=pJ{~Qwjm|
z(15NPx4HQP^%3dTL+ilP=mMPd)RbORSkO7Y)0_Zdc3heyF8p!T4m)irN)|e&)cQnG
zjf07qxH6<*<gc$m=j^FOYgPRq%)1c=$xG6ymy_aA_XHvciezM)q3B$Vl?c7f;MFPY
zPV-!;Yu;+fwWOxus4byKREVv3+lnbnP8%`<#+d{nX~cDD!inK2bOwR(a1gYwG79Ks
zv}uI$A}VOz4tY?WjCH;vivSj>clFb_gvksU88>d6Jk(Nj`s!E=d!O}wEnTu3yh@D1
z{0M^@GZ|t;H3Zf4F~E=r(rsVG;H`*L`@HM;G3Aztrs9cbjv1VSxTno<Gs=IPBO*hA
zdtlQw@#kjX==a<y0JVbqy#Hz9W`jHT-}WlRo;KCZ<T_>74g1MJ9JrI(G&G(V@Sm2<
zi2!*okx@4SHYlRgBKp*!C{=|syPem6Ej@UZU}ukgnjL!54bg`6v1%E-D{ibJR30pu
zF*}&d6|4TNAd%R(FjapgVEK&Kv{}p~2^|;*DAsUj6O9;{gHZ?gR0lBkYD()V9cbU#
z)q|-drsKBTJo$50{)dHq1%E>>PUHdMHvkxc^x_?Qa5FTb+L@<Jgtl%A*6;rbohLw>
zPhBtxi?W?|vg|Q#)yIYlC+ejECPN{FhU?nA>#Q&~XRlR{yC|A|+|cJCgI)_Qt@a8a
zxMTXb!QU=1Zu7kpt|jMC(#Z`{^R5s65Ugu6IsHqF3Rug#h$J?GAF{e}F|(~ny2qNA
zT>4>&p*wyV8*5G-;VPFY3)LliP)8X4-QRJk_Zv;@?QHNYbR`f=s$@@Z6edN(=U{Fe
z*$@&&Y^}H*Ia1FKClq$QR9ndTSH-5I&$>TNx_K~`Wo)$h*O2`IzfjSuKxbvL?5c62
zh2QlV1<CQGk7Am4_BkwIA*~N4iCe|b+ag(6DW}!|l;m@nAX%93*}dGK(sLw>j2lv$
zby(<v{u{#5AeYV|v8Vc*@a<mVbd_yNlrfZJ-V-ur>;Yl}R#Bu}Inwl#ULl#7)*o3_
zUHNhSOUq)z2}tU1GT`HS(16W5!5T`!u*`HHL~lnj3DJ_f4*EhT8{fmRIB4W?R40x(
zrZRb&O-Iw&NwoqF#&S$;^u4n_@xHIeixWaCVU!KePmKHzCL0HYPj{U|g8E`cj&R;`
zwvsL$6S5l##n(I>cNU-NkZ8NCCjHxuON8<tKc}xI&js-zGxr1xAJk-Z*Oas2l2S3r
zh<<~}6(xzr0rvp-2%Lvf-&T3~1961FSkbb64j60Vc|Un40RB7|<|~*t(s21#sB)`2
zm3VcnsgN*(Y}&A64&DbzIN^L;u4%a1gp*n5dsCl9HzXWWC?;AzYxVZFR-fLp-@4+q
zmYvqklV$r8?r_|s;rg9gV615o&?uxYr4tb##k?QK<qv`(?siafhS5;S7NG)N=8#Kc
zU6Pfh38_ZZHTN-{BWn`){)$hv7MThvg`4l$1EK!7d4Z*Y$d$><S0xRAO@7uS#6Lk~
z#<Pt{1lV3RrWZ51AY>X?xny-MKGD43Hf=WE_i#)11}*Yqc+Co0_l3Y(7|rdNjmS_R
z?sa=@9nIlx;(kA^+2P!PL^-3OM!c&m6GpP8@e)Wlb$!cz)Mi`yGO@6`Tz=nmlk0dc
z>v~g9DYTD4+NXD{`n~_{znJpg%1l%AYja<=Ly(!R8-$AP6)DfyB%@1^FY^M3WAhEG
zHPhR0wRhI)x@N_Wk9~6Nlimv=-?ianGy;E2E57qXA@YMDgk;Yy>JEG%vbGrXcQHF7
z0UW!m9fgtwO2XqyP=yugB1Eg+PJPbaNU|@PdZGN>gdPBbBkSwuCjDBmOmKs2jd-^-
z+oM*Z&!4B#IG?}Obgi>6+k`)YJUSG6P$N_rD4499IU-Og&P>plpmkA5Q~So=rS-S1
zP3If(cxfnhILIxj<2tuwywyDJRQ!RZoOWx}CdE2oYLkSbK9fY$h)dZAqHFl7twioy
zM5VNCaH_E<T?%ZB!78Hx!Ki&TzM}kh8Gjw)4l}U?5_g~ZXDAXp!T-?NSuuKqRC^jv
zDmFbSzHbrA@cb+mFg|z#gJ~z)Zd*@S*Ly!q@0n9i-nJ&3mhygQ-C7?jHtbh$&Ev=h
zwJMwDl2B0?T@s0?HdFG(sx^k2Q#c%*@dI%zkI~(@L%p_S(RefbQeChLhsw{csNr|r
z)FKWp^}9x{jl?A|fBnY)ySMOrEHoe|aYLj|y*X<NWa~3<GpuejqWw5MF_dw35q}6n
zEj|*JXf8o*YHapfpY5G3wSMDleQyc%a$h8myB;V5CJK2(Y5qLPIUP4hH^~$X{D@x1
zDF~2dBhLezg)K&VSHuENQI|n}RM*0Z?$Xd>vi+rbQ&Ez_ZG2q!<M&Xv2Q`Lo5JJOZ
zU#^cD_cgJ*;namUO$6B`73i@AR<c2=KjanE1nK}2__)=KHfW(tcp-Ddwwq?|Szb%W
ze#%7lHx|ZD%!(IKE}M`WM$Z|uxnuM5ZXRzVpFfVr`l<UGG39ggInV;$3O66V>V)3(
zj{UhN-zi@$TrFUGy36hFEC0CrV)>k$;AMxnoZxJi@t@3a@L&J*<G&ETLc%-s%4>x3
zi_8IOLrM_MGHX@H8I6OVzwK;!xn-VpsrM*7n91(}^M9jZ^4VQon|`V`=`JG@o7$~S
z!8A<QgIL~0Mw9l28~3Pv^z}(13?19{-mvxC_TEGeJ=7-LPJYfNtI{LOAZ;UhOHOp8
zdXVfXe+#}}EB9$qGU!xB{^B<t+75j#ylgjA4E5_{5$Zm}Uk7ZaAD@B@vo^oj&9iKe
zZW!l~Xvwtn9$l12T0Z*^sIDdU-)P+O#PQ@)C+*}e!w-)$&&J?DrI6_bT1F&o0Keop
zyxx;;ZdbC8@M8P6Z2$^zy`W_^T5^)%7uw$`UsH1g5@kPmju-aN(J~d!7?;JsM<ZUv
zsG57f^_w^?wd`5peUD)QzQrOYv_aRm$d4)n&^UFt3(#^fN~f~A1!=VcLX(u1{tfR1
zuccgmc2o5QBP#Im6@6l2(kDnus3KVhe!%Th?T#J8jXW8QzX#SmwCQp?m<w}fR!Pv0
zKCiOZz=$Xh)$20jV{$*W>{BM%&-3B+F+C_M(Ywcg)hq#;`Nf*^n&{dv21z<jSgCr*
zJ>+@=3KuRk{o0hQ(NT=t;t>k9K+dHcdPe}iiN#dYeeFK3;N<=#^!nqPvJl?T7=)10
z2k=n{XSPF{=NvLstANF*Nc}XmX2zx-!)BaymK_`|Kw1M}3E&*t?&-LZp|oqm-Arwi
zH!-U(_`_73l})e*3d(HOqAc{d`_>P5P{kr4WdDgNS!rR%-CGv!RysBBHn;^dlrR8^
zQ%DrCPE#{dwx<`>kPJ|fEvda;ZY+l+84cp25W=zVNNQHeB}#Gf6oKlxull*7EGgcz
zKW@a?FrztK*VI%JE#W1Ir<He1kI(r@6)@G|tVHhq`IJGDZ@~(;-ZUi>PCbe6G@(84
zlzd_`2@^5Ha0mD-nK%(+I;!x^Ci;8Md)8g_TNm9=xZC2ML+_F9G~%|y&2C$bI?Xk?
zO3jU%q$ux2w-}rWOw7d?ZG+dCqfN9gu%F~nccEXkhbfcXeOHbbQf6|-Po|P(7?ii-
zyDb_S`D-%atSV@DLp1Eh2N#Uh)Y(uvPR`H*DS_*dM##I0{qal$feU_{`h%9qyPo%9
zRL_Pp?>#e8*mB)Eco|h47EQp<A#Yq%?G)?9I$R=McfITs%1;x3eX396vV=Uu*dZ?+
zpj7)w8Kzg_&-Lj8MX-8RObt4#$cC3K5->K_VCckuJ<93MVF4>lQUeT$9Y<1!rM(fA
zaSiT3mNPNn4U>w!ZZ(6>w$E8DjC0l-`mRV_^=dE0``^=d^gNtQkvraBsOKTJndgY>
zlOlm3q4rI+sf&P4lx*%)s9+F6AJUx4QZ(tWC|42Pt!m^$<9?e`xc3O8cNyt7OB>rt
zzs}-4b^=MzkoYx-OF=#(1}4K8PKt561zTwVw78*0<g^!Qqi%?<!Dp=2%d({~Ig}Cm
z8{hFV-hO+zlo2Do!<_elP~pskezO@gb?xC7q^=ef6=FvE$gyI5It+g@-|lUX=!G>7
znXdEX!xu80_oUt3*Lh{4^Ga%XGFYED2XEoDpVMnH<PS6h<B#tD(_c3A;s$e_EhMn<
zY0Dt4O)+e}`8wwIQ!Ht|jJ0p0ABoLMFRT8xO@!RryyDr`v+p6ZC5l={RQx!6JxCOx
zw@Xxv88=5Az}Y%-NKIL8)%dh}#DoTA6LNA}65U4ql5Y~#%XXrx@)KD&Sm;b`x-06L
z;Fx<@f2xm!AmI<8HiXXwUe1()+dY5A5~y0FNhRI{5p<d)>t!$}>^xUkVL>=FM;s8%
zRp+oXUAbye3*sEIZ2XxQz+f9E7Igi6uk_Kv9yQ@QdKKM=f;9x)fvGMk!ehW2IA%)4
zkE#AC?HBxG{)?^|2f;BGEG*TxDesCNt=^J*w(QAnL6S<Ylsj~KM6&i{Vjw8x;5#GB
zSqg&95`)BV|C_(V!nYc%ZVJexC8@tkQ3%&$&$@^g4te;19Ou`f2`ZPv>}(iwRF?ex
z&O4=R-d9UR6z)JVPc&gX6ypJ-)pqo@Faf3l>@G+Iw+Bz4Pv@p^#$f>1hO-GVABv>&
zH{~7Ite&8BiRl4Q!?Pd4LL!%*J!~F-ckRE@R5G6*v)*F0ks?I`C1n!{aG=<RDM6*I
zi%SKPWSB8-M!+syY3iHn<>J78=gOHbx3=M*OU?_1$?c6(6@-$%%^;EKz<}}qDFZrJ
zD4$tZ>ts2S8v!a6CK~WSQQB|@?KX1vN1j~jd(vGDj>`_Wd@N-`q;5TaUun_d8pCW9
z3Msw2|Kc@R&uOi$HI;37QP8=J7T2nz2JF4AQF?JB@MgS-X4azi<C00$sb`Ltx&r68
zc=mlSxi@%R^>1RQ=3#7Xh6#6e42uw_3Ak*QY)te7#nb@2?4tm24dQr!A=~p(rh?D7
z*o<r(&)gJ-pIImIT!xLc$>#m`B2AYgWRKE&P#UJ%n$bEADdGJr>niFoUItZwmS)KO
zTW7MD_3(K;Z<Bv^!?qWKkE*@;S(wXUF&J;=mhWxCzO7ui;DDx%UI+e`R?jW_0D#wt
znCilLG6PM<0DxB2w04Vb?oJSY+C2t}_89N#nIjSz`4-ENvzA$skxok-h!_nhWokis
z9|MO1o<oQYpvw3n>Fa{QJI~0WRjS)JoXwN=Pm{q!+&K1>Az>oXvWDd5_zY+|<LdzW
zO_p6U*Ekeg+8;kDbJDzp@n6CNU3@S+t-}rU0phLPM35`EMEE8ZWS-me1cc0bw{3|B
zL2<x_Jx3Cc92fyE&cunFAqxU%RJZwsX{@6kJ^+NYo*7#9mc1+Lrgg3~pF9-E!6{tk
zKCSWGIDe<K^ri$PW5|l&aUjU8_&!U!WPE_z8P3>#BXd$duY}@l{DB})x%VcPRon!d
z#xsbFJWUZP9TneTVGf}n^FB((JjJ-zEHwsKn&~zMBZ7+4kJIL|wH>OrEn4XpEN6ei
zxl*raDi`+@nx^!94NVUdR()`kAU41?hM=l34qTJ!2%h)P6iwEbaSkt7rgRD)pB^}(
zy?QmX@Wg>1p;^}?23mT@U}-WML5I$P{P6C)zp46ezWOCtAkqp=TVtTr^~Ok`Zb!XO
zB*`wC={JRjkx=71qa;0IRznovbeGk%?A>8CKyt6{j}1Uk64Ia94n}s$)GjKY_SdFr
z*Y%Rc;6>1jj87p0Flz|0Z4*``rFkzmN#0H+@B5lFUJT*~eT5$tmK5Io;vz$Y{U!l#
zDN$swDbF|&u<Cu6cHPFhhbV!uX6PsjIXZ2(lB=%vc|%*md!aP6sdVi<Ls<o!$oeO)
zFdVxr&~*lJ6#0X&sTy2&aogp%dJoYtjvS|jtZFKd*lg2TlYKh339u04OwtI)7iu!I
zh6(;Lc{ef?f{=|2h0GEk$%5A+2c;c1RD|-z#hR{$-f$N`0T1rjo6h3I3#1C)5rH1s
za)S{cfe*O=v?~;=oq^tzaes~E5ES!R-LW<?<-g;zIxbaYsNDQ#l*ch!R+~mg<lCn-
zekrTUd_UihzVkz_GI}y{*V|d1dcjWH7w})8?5wF}eOr_Z02?ldox@}qVjVMFJ6&1m
z?V{gfZ)0z73!C-q_4e=CwC~^yujclsuE$^l^yxfArr6kA6;h7XWx!v{swjnv+>ly+
zp7A&<Dmi873oHuznzdTh#Y|WGc@|Krp7yKuPi@&DpAm=3kIRwrmefgncYF{49W$UG
zdS(R<iwlSTDZU!rqniqV8uhlp$SG)nw4tk$`mSqa*aWABO^C2?NpMNi`|yHT*SBWL
z#Y|!7cgC&+t(*4BID55U@$m``Vv!#X49JSQ3fbhQTsENTrh!e(Vx0AfDa{mwi<m;=
z>s=>c0%=Yp($ldcU9;t9zYUhnnx}I6s=DdFr&o;@gvnmyCPueLSaf7^<cUlFF+!=u
z?xvMAfX194Tf|DD0&Dp<)Lha8zaDIeJ|Y;K1^r26#Z_@ld<$i0zOMFOY24p%$9|`D
zr}4@J_0VhHCWJC>GWyPq8@-HOGRJj100k4R=sI%!<ugTjX3F0P%wUZ3J$TiLPFL79
zt-ZQfpxWN<yrvcd<*&HU6B{0<#>J!-C%M852~g1+#A8oP-}}eE3zC=Eo&GX}PrrqQ
zD`Dp{B4wRrq!}W=7Rl1k9erlpH$8aPsflP~)WPo5Q-o$89auQgc*B!JSAqfkQFYi<
zGA`@dsu5EJ+sGHk0Ue{pWz&t<t?K?|zfYCUte3F>aidlVN@$Clp|5LC`(_f9BLy(i
zBUiP&>zc9aI17=Ic1Vt#DaA^BdEu8MmC9)1%}MdAo%Pho8OEWO+nDTh!-8xmHsk`h
z86$|ThC;)Ff+7m*%xUCgQnzjEcEdNuTgDHSRO>nMx#XBP;Ine55B>pTgiKI>M|ufX
z-&VRhuiE>xiR>uM3Id!AnGcIKohjDAMcbmJ?2cY#wck$*<(~H16+byyR#T}BgqeGG
z5X*MpIcMWuF5YiA`K|n}NG-dY&bni>&~h8x2p3)$=W=aq%O#UO>B2;`1jPJkU8_Xf
zD)kid@RnBnY_DpWYJTaO_l~!k+kbKnKMs4Ioi|nzwt@4uDc>1)4<pAoWBu{*_mw^~
zuiH%!Wn^m~aVCrLSZayKTwS!gGfYu600ag%2BYs>_KOtiyy${phP*sTSYS8b`<K54
z&{4}?*q8%RvO%p=lyt9%x~MatQt%|sl&O9lo^{%8SVS?#k7~&@QbR9K*+WaI7Tr2m
zdSXonx<53V?2gNzcf5QYAc#!y>%2+Y20C|6-@y|lsUI9u3R<Ak`hnh!AAYo2H9+e5
z1s@|I!Rvccn+RONB|Q%|W|k<$5I=@=%o(J{;qGw<+<j(u#cGi++ppgcP~J*aaExIL
zJbrIJiGnp2pU1%MIJwbj@<})_UlG9Xi{<0qC%xwPMQNyZ$3NLHya9JE@kA0!Mmmhg
zZ`j?q9VXQ)L_WFeZNHDqtxKYH4dfjUu3wl8n`uVU{O{yK&h6>AQhr-5m+z2a{WK7_
zS?e-KXtQ0qMr25Ab@$PKAE`xV@>tNZ#Mf-{TgV@tNLRrkXeq0Hn-Rmap@ZH=92C87
z*%vMAa4**3xVOLITCe-kI@MjlfDdFHP}&!0To8kj?C^OuqkL%`|FU~it!gNqH#sf>
zY+g{azMlX!LR3rc?mOzqMZf$)`9L`(d(>kFehQv*-e-ZUi%^G=DJ3Os_x2^}DaDHO
zAG}$3r6CQ>wcoDds-RU!{I;%*6;8BBrU(B6y5J7o_B>W1;|@`P)N9?eu3F#7?Q!xd
zUtimVB&+~ff>Zeae&aDhc0+7HJp8M6<dcMcf%U{hEAgCP<8w^BDPGtv<+9U97weBM
zw0D2D`-$$U9x&i{fK%_3-wD>r@0$AhfJz2r74yM75~V)4@Gn_XNu!(j^!~XOkphc^
zZ%ok{?_r8a){4}*GM;U3);J3=TQ4<_iG9Y`E!%s0S<T=v3C?@grt{J!D@fS<*XVkZ
z)F#X|MS;xS4vfR*F|yss;I!&w5!;FPP0UEK;W0*pz!I2OD%H#KNLTd8sU8<F8(?y1
zB>>ttFyJx$G-{tn$M>PC$^B!drz_%K`Xq~YW&jsv?XjlU4gAz1M=c9`%NqJmh^|T3
zaJ`uhUWV82H#Wj<ywPj1Xsy?>_F64ZJUK;$M&KOs{M&^--C~%Pmmv8Rs!jYjuHBxL
z=^_XdFav2BSFh^ay18pCsdz-)D(#VHop4rq5#dGq=;cScKikv(?ZUV1&6JsyRrLZ{
zg?HQ~UT458jIH)DnI`Vs=L}MJz_ow<7rQC-A|qdUjdljFylmrOvI7r-+@y#z{=RIo
zx8Da2$8OzooI!!nhOc0~+qNm729N&aSpAP1mjZxdx5XdPlgTCBzlsS6kyjVSG~*3r
zx(?LGtr430rhJAsT63NEQh^Jr=$bItIgkluZwrrfE%veq;-lR;dNNErdu8GUtq!rg
zVlx0};d($W1s9{C*&}YmGd>hAboEdEcGfIr``GMnb~dRSfM|3JFkKEL#a?T<Op=H`
zVx}jab3L<KABUssTjG}W6T!Jx#b(3nqW-=By1Ft!?~(Z=u6=D=yAGL`Fg78Sme8$3
zU=()EV^Lb}q}y*YW=euq80^?kiuL!E%TluQV;AjDeyYmd?6tJvqLj;nh4O(Z|Gfa!
z;JjxP8YS)CvV&zv{QJwKdUn_5sm3o?B|<K{*v}dT)LK?gu!Do)4c>s~kXxbQ)L}**
zzCag#QSU=XTBk}^OXWs6yrxNjKMs*po)raX*6pE3#1BJ-WaEQ28vYueQ#uc%g22{p
zlaHM>Qg?*3%rpt4PJFoEk-LWG$_KUAxodngh#$j8r0OPaln04b7eTuB#D3a1(S+ol
z06@-k!X4y0$~I6+Q%pLCl6zD(9;U#Vv3(SSu&erlXp{0hUhmS$p*z+(5Muh{nV^3|
znMkD{KiYSpxbdVzieFT$2Oo0mMX>O}Wq(~#v#5PXne`0JXjm?YX0_$fsL@d0@Vax|
zXXq)>o$8*LSf_IM7~=dKIKc=GsPVmXC`s0TkmRxd^dR{)USqyRzEusO@M#Le%u;Wx
z1Cgv*`D+FeMve*k4S-v-3*RN$OE&@8Z#MjybH(kdnWClQTrQtm*6yY@xBwJ_L&Ndk
zWWXf0wO}FPW`Gz6_}J^gyf0ki)8mq{eMp-)A3Z8B*LRO~_xDg1#nNT^zjT*niXt8I
ziFj}-6*qc?k$cU8TA)uvSsJ#x^6DI5%j;(40M(9dcofRJk!)~~y&Zj$qXNw)A<MuU
zXGIg$Kw`FcXvxi3mTXClHJIc*_I^+s(x8Pyab;cD5(VH$8$^pAGp>YTs85@}4WMne
zwH&9)whB%31*?TqrnX{2<s?W#(SH$h;9_UsEe1^O(u?2vMLf2=cSKO-SWkt7<v27d
zT9mSNCD~-ca|-G>-;moLjJD0fO7xj4)wdXq`q7?E=XGzwSPi}Z<o%@hSXueYx@OD(
z;}6&2Z95Nj)pfb72xbq|2v^ZXtT#nKjc(`da`B4}%NfZ^#nLRWNnTUcRduoK7nL^%
zi;PpMMba6|j?-vxd>ppKTc3Z}RK<=aelz_#1K4i^SmBnXEU0P9!>@@#?u1cw#$o0s
z@hF8Xd#TG1d+I^QkKVDCie;)y-|;5BKug+itO82*Y2Q%XSnrTeMkSdW0c25}pay6y
zMd)fmCa_B#Aw(ggjh>^Fs+|mS=ICYX=ua}N5<4WHy<a8~I4Lvkv6LPv(uY2v(-f4f
z>vJ0CL6#H0{zo`JwV992lJPm4X8x;Hg&{H=&RhU7_ZOH@oek~qx~@dM=8AX2%8-9+
zJ!^r`CO%0i{=DbYk||W}SS)`DqXj-^C?5_#GF?NvtWpeurti~0g!D;?mt6c(qZUPP
zXt64nX<c@d^|vfps(hXz=+0~96}P`SSze!@cAu4#X6YQI9=A-vObu6m?BnPcRu=xM
zc$w@7Ar%TyqG9kig}QZOOSp{QxIgFuULxM;xT0j$i_eNuz05$d{T53%=KvbEJoh*`
z0IhOl*7|gt(I3oLIQs0IX(X}TcOr*sE|kR?mdcdf{y6j55AlUL+GTrt`;Vw!$6Z=f
z?OPI;xuCnwv8<db6cJ!wP%p0Ka_-gt^e|mL@+hsdf{HOON_^E?fU6t4@1I!HAs|JR
zjXqBpZHiH{qOFx#E8(2V4>k09b<vL&X^ZZ-_|t^5fG7_*Mfum1snYXTlsCT08X2%T
zmKt{&7NivkWUEvjGP#o@M>>C^V3Kb4z!mp+`FLt*EqKh#nptu{N#_(KfX%@;E@2Yi
z`eH0x;QK}c8!Xh@O+d4@2R7biSJuW>Toan$W@XVUrc!KJRK#r@8#{4{tMgC3?lmt_
z<D1{>omltcxp|W|^Gsa|is%86H^>%u(k4iBXrBy78EsCDk2B$tL<4ndq=^a&wpm`5
z8I<88?Hj3Yu>86_r@B)I^^pA@VfdQrqkj#}j*uO1xa2j%S2!m2U;K}7xLFDQTKZ7>
zE!GmItP&Y37MX^6<TEt&g)(u&t}GuKqwk^lN;J<}`|xTuogX(WgPP)>dG3^+B_J`2
zP={Cb;3`EEC|(E1(;NphT5bbB<TwRxMiT->`O7|fNG+>Aqc>P!P0J$=QC%SabN;sc
zkz4sm89=f-m3|>L4Ak|s3kCWeH*O3-cGI(#9W$JJzkMN6tJEs<vol}lyp;f+#Epqk
zB19@>uN%hXW(II%a_d@9A`&jEx@a|Cr8bLAq?a1(`dqKq<W70t&-Kyetmg6#27QCm
zcR*^hW<yc#(GD`D#f$E`PoPER@pa#iBMgQ-k!e{qUm1zn3Z7k7@06E<4*zktD+rGJ
zPrIfvQDYcf?y3|0;W!fZQ{Vk%+<fNXV{h)6`&yNZiDlIZfK?N54^Jjto`+^+Ah=1*
zHypEWu9Ym-Ey9#r7Oth8*yq)+;^wbgtPY!{>;!NW{mmw(W>EYHCm=G7JBy|vL%Uvf
z*Y%WMhw}HaV0fCjz%+6*KH=r|uFH?`eWZJ`yZD9f@-toU$vfru^oIJX|GXNWSEc8b
zHt{fnsa$m!OrrVfzkJB7wx*%ln_HrDHU)-L52{wM+F}$S<l^XeQnq1$f|nOA1Z^^l
zIT?EWtX0@MR{srMANR*-+;m@SG^8m|C5&LscBoJK4eR1p`#_|~PxywT-_`2OCbNnT
zbBu&<Q-4iPN>!bdbFzI)x$=3|a=POM{kE}oSh2xdni66}uyXHDdmpU3e#JiZ#&7-~
zti5k^RQH+Zd8=F@N+#2-dvzsB0z=)OZWSdV1S-=W4Lh6Ez53NvsSpCmf;i5OO_d9o
z5E}<Y@#)Enq^h{G%>;LV$Z<T~nIIvP-r1RLgB9nT+1Y8pipM$KJ&kF_?d;i^Hi|;`
zp6T8OLfkXEXQub_+!9W|+kLUZHrT#(>-XpR|9qe4amf4_NE+Xfs30K)BeF(BykiFt
ze{k-YCgowAQQ7ReX)c+U#&uoa;oEO>pOo>83fV{mhb>1(ULz<REMQHxQbeuBeDB%n
zGCiSm9#QK=r!7k9A^Gd3x^QTRb-a?1GE`u}`-8h~=D2LIO6P<b7#9)k71liGk{x~W
z&R0gjsN}EqNQQ`>8LSz*1Q5Px{fY4h)19Qsg#l$X2PA-&ApS{ul=;84kCi@FN|Ydh
zFcCFVqhVHL;PGJ7cI*QOs+N3x*`I+qpV7`2xf4p5-Ov?bIf~g`i;)Gw9O#Qw7q^2=
zV5=1pU_|}6!-61LCF3DHM-aqH9{-7ip2E(`xn2orW6b(ciU{_vI0vB-)+*&y7y;xP
zow|@X#g9Vdc(HbA&MQrtW8UP*q6GUecfrH(ddba1r`^gLDERith`T$hM1Dyx<N0s}
zp|IQmC>DGj@lea6&3dg-ziN$5^j-GDRX4m<g(;xDFD&^hh)6!bHi=kTBdjEL`@eQI
z8#8+UkVao;sWu|#8SiYwv*ZqjDn8|H68J{ev6g+dm8uJ#i9$j;nxAZ3@Jb5~tM^A|
zyg3h)n-mlbEpwnO{i84lsT$IA{w}`<l+R=ZRE-v7jU>g8miR7u2xB*vQchjHVJ%ti
zoTA7Yp)~YfFyU`=%THD1=^ha-2Xx9zB(2-y{}!=m%)NZ`+(akoZV)x#gYl1Sd-R64
z>Q``bz+a1>Dz>JVifwWf_+<i{bk?{){AQEW?`_hhi@}55BNz;4kShL=WI+)bvZ(0X
z`*g#OQ`zg|oeo#i{)8JmOxi#!U609BU9nVyQft)!dp&=o_o9naw=D=}GSiuARoeQD
z?gk0Ps?pe<lp3e*4E$dt@me;==g2R>j}?ntBB`8A><M3b3PCBt^?ZP?US2K6S#Jc(
zOO)rbBV97gD!o3o+H3x*ZlGBp@sTh=%>|^mE(_0y7fN|D=SFBCvm^MTMriJbeN#vh
zo{G4j7VBxa%awGFv^bMY5Z#l4!5YEll{JJho;v;o&VWSiIZ!f^yo)ItV^LCio7Kc*
zzl)$mc6(F|N}Ta^$D$tz!9Sd!wj~-pd&l1P#?qy8x*$Studc0eYT~RmkJbn<3=iOO
zK5bJ6wX=$)O~5EKL$QM&$T~;N$hM(V?+5M?;E2!5|0z)4NYepdzc+<=Pse3Htb-2J
zxBqafVbsCmWeGlRR-7u?JL!G|D3S!uJ}0x=mD<umf?sl0*UcPak>h{Zq%LW-W4YWW
z1qDM7yT^4fCy9?Cw+aOjMQtuw7E4VZ<bb@}fr-T<`~2boVncm4CXJ>GP_#D-atHYC
zrpcyNGRr}EWW}F!z0z`Yy9F-GO2z){kL6jy?Fcwi3~x!)U3CPDI_$Th7&$2N&A6F-
zy@2!Ym=1`8g(1qOJ^)e!u4B@t#pJTSt`mpZmX1`BkgZ!nRP6Ah)_NhgD-z{dy@sJB
zY&R^7G1OdX4)p!yiA8{je(^eba78csPp(WQp2SC%t@Dep>eyz(2oEHQk4j+6gbEjw
zjh8?#Oa9;yD;0`u3b+vup@JlinNamct61FpvbWI+t~z7o+YVp@I9{4dNk3NpTBk;%
z&m}tN<6h#R_!6w0bVb~4t8xgEdZa%AnDkowx(e6a=lpo-M&*$H!kWIPgVJQ?NM^Dk
zOyiA^vxz02IQTIRfoKEK66pajVbV!TnlZ#TPVDz@Xcd{+O<ejYxibRxCPl{WQvF~i
z5waw7?GxC2_7AicPk4x+B05B<W?hFkj^jG1L;;jXB7Ml!J23sk&ekJmZQ-x;z?4kM
zc#SJ;>J-sxWFGhkcC@XEfu$hACj8$peyanzB_cK5<NX-3$hLcZ=wa1@gdcP?A{ddt
z83>j0CnnQ&(vl%&Z1McVcDs4WL%wjPY(GL&vBrqO4FfjveSbq4=<N~w$_Y6lVQ!(2
zlsZ|)v#iC(bS8m>5>LKdMP@fmst+!1pu>C7JW3gV)}gda{yNLu_gYf@xmP{m;~mP1
z(Dw<d`T0{SmN)T?&wHiU3J-c*W#@{=e=gnAEU#p{A(zboeH4);Do(1|-LAEx%R7P|
z0$`bYzC19gwG_ms8bolYul&(OuaGnT>~p@79+!(6JR9<Y$iueCx#0tbar@hE39vN^
zS4vjA-iRxk<TKRjf5k1hA}Uxf+{f=DTzfKUcbc(IDIz}WZJu5Bios30Vh?MRJjZT$
zJ8%<CSDd%YPf21nX)6xGhdacICi4yd%MviXz{(og-uPg4@QT8~crE=peOkt<{=TVU
zE!fPV-TGNq3>~p`CG1L?_s(z3z*!7n#jK}7j{#NS{@aPwNS+D_AWO}|*k@4IG4O!U
z^j7Q3PW>U^#A?jTe)V}!#Evud%XIn?6-**zN8IITmx=q<4s9Nh1Yrme-7E6Ij$k`B
zkJJIMIYLK3;*G&<7TxRn@oh?AqR8myg7~&-x}yVVTtZ9>TJqInTTgycCS}gnt(I92
z3n_2b0iKT^Y;TuWC73G0eQ&XoHL(yLKI>%WonE51-`{xjt9PmY?YLMuUO4UmqT>Mf
z>x6V&;X2q}bh>A-aMs*4<ZC2lfmxD54}xz8&*DbS_+qr^FOeC917sG6+HN`IbAX{i
z8rTuOv%fM~W%bW!5Zj4JDe&gx?LR-o>*rpMeK-5tNCUxjMWPE_%2vN&5pcr5j@;2!
z-pvdZ^Wm$`r|D8izJPuS6sh`~GKYiDPCjxM?_&vhu&58~Kost}BFj^7I_LMe=wkoK
zY8637xfnz`7Dyp5rZeVg)a70sP-p0(!62HFFJiW$Z{RhF?qF}iOh)a_Umj}KCd4xT
zCEN2|Zky{xBQUv4dTM2U>8AH8%nwuo<V<>}Ztk|bVjq}4Gp`YKy5?*#w}3||KK7Lp
zcbsx@tlVFI<X&3$>tIP^QDFNuExG2AUniA7md|$p=2l%&PD9I*QJX;t1QWcStQ|>t
zODZg)a-y!gs?tBPGks?QJ@_GIB9wzLKd<ssX0HZ(vB(?J&xu%{v-1L$rnu<;_~*_2
z{FJEJ+$$EzooUC!10?QItN8zzp-VvP5h9#`Kp$$C%x<jxw#F~afvvQXt#)iRZ*E+u
zV5(I&RY&j`6T^{#d>$(21fcTfR@@I<8ymgiy1^t#hZVuiJXIxGvRm^c@r)+uzrKJ|
zVs))L7p>A)rWahACv2lsp=Ubt-jp5R5j=?%B7)S7rco!8&we#tml8!gJNy1A!jb|9
z1QQ~CtSS@uA()#9WO78t7{{dY1gqPapyFavTjx3Nu^%9y!TSeSy~+I)$`{ci%X*il
z)-O^g>#G-C_kk-4Px`WeXhO6BM|dtEXPIFAh#~qXP<~)Zt%%vR+I_3LUSC8ciW9S-
zc2=f?Lzy0X27sOzzMRY`;b1W8uk@3ls@KEzWaq2MZ~T#1YaLW^d~)**FV2$~84yw^
zp|z-hsmm{0{U&bU=7rqj;~U#w_Z|lG-+9Ou5?W&MBTJm92u7}KopEUyR;yOM^o?Le
z+Y0YwyNFqVVnqcv>m?#lp`x|jJ=%S_vgq!pW_Ht=H9(A`7wJvM>nP|MB_>FU%=!-(
zBf6=#pK#v)&bb~lGp~UCw?iAGXYGTR9P;>>>4}JP&Pa(){i?aeA-Yq017<i^F1<G1
zF#y$UrDsU_2_09QJjnSXwlE(<5jE*1eGMBF<XCrA4+AIwn#GFzp&5;J$xU$dI!WeH
z&c3UmsHU3-hSP6tKiGX1U-lvpmh65C(*p8v_fT|hchkmBjyO)8SlFKfs+cVn&t_jP
z76}S4MN2YJovZ$|a|zf#xtqKVH_Hv+`_cx}{1dX9YSTko&9-^(tFPJqrl9k(S0(6k
zqwrxBr6l=;C2m0IZha3}{F27uB!?(^-{yW%ch3MWbtxy2L;X9nzo$-XwaeDamfEiR
z;CUZ&NLdq^r!ZGZr{v^lL@7{Kb)H6wH-=>X1>HoyckUb>xPXdc;0cLsn|9_-Iz3{E
zd=n9lVblRD(DF5d2cLItqIKU!&c(HfS0SYUqD&#01Xfx^HK~MCauXbSVOk?SDTdY?
zMv+b&xnwh>6pgt7Kv=qGm((I&)B=n354lJDw*#+$od5||VIPXno<0}RxZVDn*+Edb
zyTI*PSWt1ueFDvj2OBLi&nM<=kSi2XbzH)P?Y)r8ZAAHxKTcH_Z8gq0M|-E!CtP<`
zOFlAzLXFI!=7L*^IBNJ)pcMMZ#8mnal9OU6P!yUkxUSElCwcXGrwi;yeZkoSLfzTU
zl!VJ_Hzc;R`nJ1GJsW^{Ipi0tIrx;Kw8(E4g5UbhPe!%S<FCGOE^`y7g=BKpCZ%9*
zKIgPgnxBh{oq_#=CAdPICnA=Zq(cbuVZvM@Tt-6K>CAZm^JiQdKO^s#p!t9+6;XcQ
zi6QudYw|FJp^vQT$%^!ysqkKUR!9VEy|QRP>gj%ASrgrBY9X`D4eqMU-i$k31wG{7
z)4|ir3@Z?=^}2o2qr{Au`rlAijIa@)eVqnSG@r$qp+QAlWkAXb!^%k#14&v}NPSxj
z=4z`idynEI*jQ0laAmoDXd7#S0HwG`Mn3MeUh^FSmivOjdlkXXq$lveprV3~x-<N$
z26`3#>>03n&Q-c6{E-`&Q19Uw0JU{p*f@_NL&bjm&dsl5CmQG@8Ytvwi5KU90m_25
z;TmB_5i6XtRPMBzSckVAv(>{r@J?Vq9|YPtqut$Hx~xF>tGQ64m4W4$+~86DZ5rcg
z5=U_Z4|y^jiRoE2E8d#(TjPa}33cQ-Kk+615P<|}l6;c!ui8myh@jrs=*LcJcJemS
z=&N|!c6*_U6TnxAk-+NitI7c?=Fl`9zzN8`6Ha1%2SKRv2!dUt7k`i+>d2^Dj{Z6j
zP)(!DUO6p61JdON<)>B-#-S_E4#mvef$m4t4%M%m+Zp#M-z`jLS|M13O<rUaV(rd<
z+K+Gsf?{6FKG?Gnd>g?5GnVb7gkN~BeK(LF$cfeF?K!)k@d#O<1)}e)*+D)d21LRv
zc<i11BZ@^DH+4zgvf{>pN`A7cJtCWBQSkgls!Oz4RP2r?cvo4(xbUq<Z)EU84rGpK
ze*=4^Q+M=W^0)q{))s&aMVzYaf9auF%?bQbOb#TNh^`rT#ghP0tDKP-*j<-wY^a+^
z=yvaB^m}rP*+F&&hY<P3Ls67L@P~X$^GLC(6KUV_$(lov1uIcbV-4uU6_K8is&2OS
z;Ga940gFh#>h|Z{ew7KV4s^UL+<f0KxpVYRL;&__P=oZv0v&bPA!!?>oip#U+Ko{p
zjs-*_K&T<Az}$S(JYjlw1WJOc#E-e-LD#^(?Gt*k;3F#R5PIM`*7=_%YC;PZg?EWU
zoV``FlkQ;MAK5%qDM}UdK);otm%8e!u)j)nhvF+e2gz5FfXH$rNFkl?{jVRZheXKV
z2PV?9m0%qBoEr#N)eb~?+L6k4>7^=(B1Atj52A}27sQesAlYQ;TQEnqwwLXV{35t9
zjC~DvNt8{TgLTS~OsJ8+rVmsLRGRn`Rmd5I!ZD2NLeto!2eevf>uRjh@Y4dvwW_Y^
z+iqr9xiA7;$H}p70ZK?s>=Wwa$bkc92D^?rj;zVTFFPcO%zpO?`nkKqK3^`NJ1+@p
zEe0&y%y!0l8)2-|uHW;#c5lU-W1W#8NbvG?d#DwiI)_aSHkOeW#Nc3|N|`f;jJzv=
z=7>>bvp{2aR37b1WY6pLoa?30pU5g-cmj6;woKmsZN_|sh8<>c0NUr3)HZU*(C9&(
zMX5>hN$y1J0&Po3Z?cbt9JLFLi`H2Ac$vItr5C7-ONrBpw89h=sh$x)+eeYvv?w*K
z{}mN3Yu|CU@z6c3OUwQ?cSwjG)zPGPsYIo+N=dO~ho(9GjDAli+*I^Xf)0|gKl`U2
zm(tj9?xmhrthr9Y7kJ-Bw%t4Hkl&I99Zk%KMpt6V(n7$rItR?bJ<eMLTL$(VX&)Qk
zG<@89usl_^_fK4Qo~u^%=v?H}M#RH8M?bFNI)q;i5Yx0*+$ypb?X<!01dl|K-+g^R
zMK!kafR*i6Q{p4;oI+OkPr2SUofb>G3K>fmji~fSeDP<>bmyY4?u#$K5B&HQs}0vn
zQ7&l3dI{3`pS6Y*YKJ>SN7&&Bu2ZUrJG;-Cd(_DbG&AlvJH9Es$=}$~R`s6%#HK@z
zl2BJz)k6^}bC}T%00FvoV}|e$K<L||OL55y{2PZ!-1DX<i6;zB665SZGUIow96)gY
zhn0sF-D_4e6@Oo*-+v~+0*RugAzl}sEMtIx1F65e;}b9?(6pZ>ktdmdLVh3189irH
zIxubmxGVeZKX5EaL9)$S;s64-a%hS`+UCpVyL1TL^w6Hgp!Co{FRjxy-}4HOgjGDN
zIi0e#ghk~Xn%kj?lr*<;wJ(t<niYfm+pV{ubX!+&EAH8n<;QX!$PMmUcnCGKXSMs6
z)^ztP>bN>qiJ(btV_6?TR!u0Vu2qUPn*oygr8i>rs6pfVq*h*N%wCn;VH=%cr8%rc
z(tJV>`#|g?bND)XO;XTx#Lj~##0M!BA0W;@zR}#e@vi4=#ud<yETz{1E+&eG6o*6u
z^LKPFJN*2F>T?r*ph3BAlgn_@Q}UZ`y+5j9-I>Ab-9E9!+SW}4B1&^~wQ@JZ91@>B
z;DSZXP<An@0XdYkzVXyLVZ8)Zg)g6_bA#0uZ;cT?z2;12L<I_G5Jhq*d*-ODL3HYg
z0eE98O+mWm#vgkati|)w-kmg91?lgFJp^I75xqoZDXjktJc~g}9yhoaP{8BvuTHu{
zYmy{7q>b85L7@p%(cv2`T|`!ISbvkFit=kT*f@Gz9iPgCx6}+G;v7(vWfo;XQ2_a6
zNy#VnM>JKReKmV};?<Kfp9xqy8Wz=>Z6DX!p|}WG2+`Japk%m(t2i+Vw9bS04pv+J
z2j0?&j@U7hEl=31{uDPLzC417ZxWf*yoA&miFBU?23$>OciNxP8-UW~kl~XAfaD$=
zR+MW(Po16JtKB!9FXyf)V1b!ceK(_?!hasFl2$!O3`PzYW(^%Sk+lB%UJwDvmbsU*
zFA2;gn}wRrIGdT9(O^4ildq6qE7Zgn?f0kykj;0Fv;HjuZI@`Xin;Z!Szql~(CT;r
zKlFJ>sj#RE5-yiGfJkM2cKE?681Jh4frc?90!Uzrjs(Ku5>y#7`N#d1Ns)<gB;9vQ
zRU|?r_^x411|B>-N*WQL+_KJ}^*jImo5But2C04Lau(*M&9Hc6mmT~CNfJp&Udm~<
zk^&=rfDHyt0fbmp1S5gDfwo^b16Yg?4s2@M)b_a7c_AH?tube#JxR}1cTKNoaT){&
zBjMoahai#Dw@4fFr)}FmMC?;qJWgh)b>*Ni!XYeSR|snlJ(MKHp4)=F`houoHnh{F
zGvZXv?YWDSaVXQbQjt&3$QhG^ywB*D{>{hPlStq1QZ=#KAnYu;1|rT%@~O={j`W6*
z)Lvv0LN0}nmdBu8A&4&z)PH7H+Iq>x{k(n6{^7tv#!nrhrQ$7`dI__9z=k}bv~`o1
z{V?H#bZP+fZbVO3X@0faFJjt+!Y55Etq9<VQ+j{qTzCW&WTtObeOPfb;lmkS2rAX5
z+~^Z0Ko71*bU)3|QrSi%dV9XtxSW+rJ+>geQ1k~hH2+FJ9!FV`i34Th$_!n#0drY^
ztIB3_&s~Rhc|U8rG;quMr8&NF<EE+74O8E%raxbyebEXxRB|~(Bo{_XbV*m(Op#&(
z%Iwu-<yo+V=_Ox390YFUrSN*riCc0`E_CnVm=>PgbJMvA<YR$A1}@&t%5#}->uR57
zbkwgtB3#pT=gn>`k-EJZ6YrZiByun8La_2ed(u?-vU@o#A#2Vr5k-}Vcy2D6?NTV-
z>kPp#Wpm8gYJW)Y);pfFQGd=_mT+o9P|oluwAS>aqKbO~k^p8R0{k>pWkeV0mm4fo
zFNY*9Xh@W0{T&mV`GeMWbEmTiqV|^3Z|c=b1x-(jfyyw_5VeH5x~`>#*q!ay48W<B
z8$)HRJ-U%iDpMCnOLj%~@QJ&0l_K&j$16?+Zl5%t!ntmrr%#O93V~e=I&XF8nR5GY
zR7Vqd(q0ix`$!`?rNj<~yO8=BTGnZqr!tiAt8h!COK2xUctg;s+x^EUx}6#6^jGw@
z`I$p5hHqa;b(B2H0usjczl@U}vS}51ISXg6^Lj%HbY#i2!N9UoY!SNlpl*0}h^|g}
zWKqG9X&2Sw<<8wsXIMQnMQ&b)65Em%r>s{pMiKGsAURLIc-mL=?bYPC3mRh&19m7{
zvYdeY?C@JJ3veQl&Jk0teqmDgCCY4DzFi*qua66z)QMX+Xu$p39B5M{38h4I!is71
z0|-=7a2}?$Y;w*XVjct{$;svb_^Y;?_75mV(?>V!nd-axqGm>sr-eWH8abBcn$s1x
zJK@j(a7F1kp9VEkbP%gbsvC`hHp%l|yhc0$ncCnGES>kP5{+gnKoZ^VyHf$hJ3c|y
z8=0zm{{uoI|MqXzS@_j#=KWVM_sBWZ2*a1c1G<X|jd0{5h7hd~iPk7Pft<-enpN|z
zBQh3^vFV{rPU#0;`offNA3w6s@dApWh~Rk=n2W?wbf`62rAQ4mb6rSG>Gyp5P|%k^
zR(Xdb$5)uPTbTAjTh|-84|5aSzd~1TiNE((dI19XZ@Tn`D^PzIWd_2se5%Q}{fpek
zZ1Jj-c|X~t80jf~U5qDMq$88=x@jfmj~uF8q4X4_?L>vdDKLrdHo|0+k1driW-3Sf
ztDo(7!q@JSFky<T_`AW6qC-KZ<LfU4q%;7KKjkuXs~W{OeieSi95=fzW4-=7eKWm=
zT6h@cunf<>N%iK8zvS-*j$QreQ!zMv>t7}6M(d+Va0l<dh)xg=<to5qXX?=op#F)9
z1o+4+LLL0l+I8x9@lVoJt)JHV=Fi#|{L*U&_t1lu{)}&y-*j*2Ae@WR_Yjr%?Cifu
zQ)e)s(tbl<(=-@=kNSd13{uzU!q{}47(84Hw#T_dNUv)xo#^*>D)t*x)l*8!da;~_
zU9gmp25}@|^h?8^0!`lfVy;J0sZFLOc@Eean6osoc?73I2uWC1_JJ*G*)rY*J9oe#
z==_?y)qJx|5&;<H6O-pC?<YShHPMmP+gx~FTr;OHOr#S;^(NIm{|F=zABw09$$%Yd
z5l(fUbhi6j{C*#RFfi4r#Itm+56%Sz91wQ?(c`Ju)<4()ah_7=dPG^FhRH!mIdrpy
zJ_7QyK7IoN3f^xnn?X7U%nndZotFnH)N#|QyA6P;_n>aOsD}MuP7?_p;=B`47@&FH
zR4{^&Sp<Hvga|uA_Ks$7m3^#*d^$vlG;2y8^2DH{NjpW!g_S^%W2FD#L3*>S?-B*F
z>jmTwzrO28XG2a{R^R3m=ZktU!N&YMzOxv3@;65w#`f7p-iw(A;fjF)dt-ZBuDnUN
zz3I$2_Aj+&;Uppfx&<tT3yOFaNr(Z_<A$1qAItCyq|N*rfZ51pME3lBbJlfB)?Hr}
z`|kPybsohbS_dk!#{vC;<jRv4wRd%l<vY&5gISHu*m0s?<)B&kH03BF_Wfwxtz;`X
zKS`7j)+Y#d!Zd+Jngo2z%_oRe24_9<L9f02C&(ly;R-|oB_e8@r&uhOLZqWCa!Avo
zT?^FWmb;tt-_2WFQQh*>8V}-rpT1EcB(cLU6M6l%@AYuqiILbSVbR-v;Iq{F6({qZ
z9<kD3G)F2$Ggl)MbOCrkF5OIu$%)bL5o6$l83X?=@pdoS_L{y<k%vBb&>LNrMu_)g
zRO`pvx}b3?SKSC1>65Y{zxZ5m%bnr4cZ-by%ThX*id$b&JY`*;uvcM#9ex%Qrf`ki
zary=}43y>pB`{KVdhUqUf6#fwBAF4HEUfrCzKg_sA_AxVjw6JOs!wotL*p8yWOvYW
z(oVf=#<rMk1E$$#$J)d;H>Auz??OEybfPmOK4lzs4@0!^VGTaeFDRiGAu=9-_qqqv
zHpj{x&V0##&UL3N6H`wSA<k)s*8vZUzAyD|*9NKK26F}4)QPmc@~;A9!Sv#g`_oTY
zIhSk;t~GpzQwjv_irMCI^~nx1_GsJejCa+uH&2d_kLb|mY)297&4ola+o%Gg3llO`
zXh%@yoG3XVi6IVHA*>Ucs$*Itv)S!x#{?<~>(IXvj7%%E(h9kP5zGRZ#wbt`ASG}}
z=>Po_1{^o{T_^KXl%ohWfDBm`<%w1&E~k|b{fRV$on^o&eZ5eW9bWweQHB!`uT@Il
zv?t9@l3X@{S$eZdy*6Hm(4=TsE>hMmBdow-CQ7cr80`?|-&WnLpK?oj3R%d@34`GZ
zs0P}ePQMe|(p&t}LeMQ`K6*Ms??%i?By{(3000-8?5w~Uojbp5NV(E=QoDo#o3<@G
z0Phlc9khmWHX`g;gvWYhA2ffVvSy*1|8M%2Od#$@It7r0klCo)?cdOa^~e=K2Xr7S
zTi-w+83G0120*4Cpe4)Oh%jVCx!jL)URM+(`Kv_amXy0&4Xyb!tnsDBsj|k#-TTj4
zsXK$)NVkOH90kum2D>SINNw90LF$Ou>vzRy5nhSn)<jC*B}XOG50avW-oTmNe0HGo
zru}n!_MB6?>y?XzAAuayqf*8(;#MQ_g(2ie5c=Kx%@t(kL~H<sEW91~Rq@KN5a}4H
z%g@QiN%?u<>~zobja%+}m5c5OV}JaK%n{gEcL>M)Y8k)v4(DF4&z{Y`V95k7=$&<=
z9ivceB=&MH?-$Ae44e28ElWj{Z8RwZ9WeJSbZ=~<`{iz2r3o`A+hghBj!|t_bpY5=
zzDf+@=GoV5mGFyzVTdV!Ii|vZ;DCq~2%o5ei*DqnS<2BpGktl&?Y<aPx~GC?)ly~#
z93|?8a7tAyX3~7o&$Dm-x-r`_+wxLR+l^PFrHi#o>r~9$NGPWFQ~9s++^%@y_=p9W
zQ)6!#_`q7A)k)hUX4lZA@mHKp)!<S&_)7IR+$#X|S9C&hgQEP_Q%g;)H^$*R#XRjh
zGi<^gc10m+>75p>W{+BUh!UE%J-?^`(fE1hmb<8W7Av<^<{ABks(w<ye>9Hf6J6r2
zT2fo^@+PXz*}{)|UO9JK!U;0sRQVKn5E0=QS|_bU+zPvpt-NhhA@_k9YrEr^?RN$S
zP^Ts(*DsgbVq;!!qdNKd3UrJ^hY7^Jv5WhAs4bx%{RN$FAd_}ziHmwWaYXzQ7l6%e
zQ@@Hd8MLHCg#w9RR;;mH-)iP!wf8*?+#BNc%Sg)TGcGx<=3361*AGh686)@oS1S$b
zJfb13O4abT*Cjgx3LK~)4*?0PHVRY_tJp#)M+W{}Fh4D5jfbejy<~o6oUDb!_J3mD
z@FKN?dxEVcbaY=1<<I%x1<;~C7@5^7M$K+L>dKrBX#4CsBS<ar$qTu`or+?c?KAzV
zMBu=$^ebuXeoc?s&*^IcVA5*zsY{eu%Jy-!pZ>6UCGYgS(s;1v8<D-sy|l$Kf$RJM
z)}0U{<7DaKD`zZ~RF`Zq`IB8zIB}USQhVN_$!hZWc<C38CvNwf<=x)C^g;UiND&K?
z60N{*>z-5}9!R%1d=<1l9fF_2aUEUu)5sbb)=kwi6!uXC&d%<8xrxVB?%1ljM{ek%
zDsGz^uI|S&+o7+Jn@@P7WpXSM%%HB|_g0(xdDVI4TxUdLV%bOy4)-IT)&7a;G@_Lo
zLex-Rx8^zW$rD(T(n1b8L+`GdKPqo+f6u&ECVWs%Khbg7K^<wL%^p1LCWOvJcSoX1
z%*jO28N-ra2_%kKe1@K1{Kiv8K}3jD2eF?V)d|TxCx4)Bx<B-nDi-91LB6lrFTp!<
z++=ajiEkmxYI02MGmD8Px&8DzkQ>%dr0_&!)nzltU6(j0pAmXtg_5PK^Os!C1=SC&
zZM9&W&P(RWUz!8tPVLKOqS9L@m+0MpkIW0gRWDPIKg4IFelyKIE%^z*MAsEn)m}Fq
zyw8)tv&d-KH&hpib+Cug&-Te3(_?B!WqY;fO@CFN%XHtPI7dfwaGD=jUlGgt`ai(X
z2Yq_qLKYp;)-*Xp09%(`<;(HH*XY<~k@V5G4Q4YmFWlUq_v515Mgxjq6JEu18eRx@
zV@oUw?~Al-Udj%Cn;XPkW@n+gF+abkk2Kp{H7_p-fO1`dH2Arpo`c7H|5_9&OhB{L
zB+dBmDd2KDtI>6T^ocwFW4Cl%Aptqvb2j^p$Z!^O6m`BHZ%g-Ljmq*9@>iq~Hd-AH
z(NOEqiSaw*m{*%Jo2J@6JVGcX0@;+7bXAXpGore=hjr^&!k|UhIm{8#7k0S1O%q{K
zfoo$JM_Ed&JTkr8y^huHYG%8?-Jh!Z+sF<)IfLo6-%V&A3xb@#Vf_B3c%4N*O1l*n
z9cjK*bVV&%vqVbvDrrB#Tl0_+;yU7{vf#4pj+<r$JG#sLidk+?g{)M<PjsIMBU2A`
z(^MOrbzJaduFmQFhgz3+Rxzp)O>^@^Q{~Nft38x2KH2?T#o4xvwPto^++39@Ymk2d
zmnFRvG(WLu4oiu#<J`GBdVfsZJ3TU9uqmTNCXu-o18VEUf_fy5jK)kYfV$Xg3KPHq
zF!R-c&GT)^t!91x;3oUAC2zM^w6QwQKrspYLuf|uzY)zFE-V`W{^-H)n9*<R>s3lY
zVQn-v&@vHvO<B$uKq(!)@X*fg3!mMY{>3ych>tU_*U$8xn|jLMp}Qd-jXaAtKPfAU
z@@seg^}oMA{Oh~flQ$&5AeNEb1Pm=RhGaWXj|eC1xJ2uU9zfbktOpsj5q$erOjr?6
zmrUoigB|mF^BM_L8Ox(#fG`vzBw~bUM<2M7jUirz!-x+2!m{q8;!$Jj1&Cg}4&=Yh
z;?Pc#En~nCo7(e6?uXMqcmBNlLq(wWuJZdcQ%jlWFcT+1LF>y}XHZU|s8EPRK6>Y$
z{dLnYd?}mx=_#Qm(dwc=#M==u)sM}IXOb`^?Sk|ejd%})Mg1l<99=i<*A60>ybrx{
zX~7+azUUiC(VZwnHiX2v&k_#J;uiF6-%rB{y4fl^jW6%AaUI@&anmY%E4O1}r~8%~
zQ~1JaXJvuN&o%kX47(@z7^$=*ox&qo_Uu=GE$Z9(YR|@V>>(1aT+8Mt1|fUu$B&1Z
zBgw=*ekEtO3|u#VF(3_>ozCug%PLYGZhyOcbRVed%WlNk6j;%-0KSb5LGDHZ4o(p7
z7T7Lxi2Y^RDu#@Y^&>(r8QHfN=&uNgXF>kyqsJEElb+`)&tJ|=GIw;D$M^9T{C{th
z%OHmzRRcb8>f`xnBJ``-7uZQpGeslrvJ$5bLoqGBXS5SE7#EW4Ag@6g=Oscwol?ZP
z#UVd_@sUkOHg1ICI<QZ+5*htiC7OxqjYJeCHhz<Bh&#hI#`R!w%1zsE2ix`2yOG2w
z`(_pA1t-^~=qfgyqaF{ukLtdd83tWKIs^DJ!RH}3jKp8E8J2kW%LW0JdPwH@eaL5>
zm{`5oTBy5z=aD!Pr@8W>x~yE<3UuPxZBofie(xnOqzl}0uzJ)i_5(emcT+qUDHW(G
zS~Oi8?Q0xf30(Rl==6J9Kbep)g(TI6oOJ`_q>{D2ky|{t(|Im;S2}ht`OI|H^cp9A
zL=1QdEpgeOtne{_e(O7U_EiajVkCYSexPG|Gwv_(T-B6Uki~SG;}azpr6TrwF)4q3
z-F$#F*#Ny-{=}Srh*`yDJ5!%?+NS&w+H3EYy2z15k?0X6$wq34o<#AmtGzT}N?dOM
z(jJDEAS%fZLD+-64Xnc6lW(YRP4s+U9i?XMxI1!Jx!rXBSP}hRl@I78yE#yN-u&kA
zc(VYtM?Hv_hrK~h4dheXdR|OybYh6&F>r4Pkuy>9wQP1WQNnp}pytg_+nujzdU+w-
zCf6p;xtL6111@t5>^f42tQ{~D#ctB0P*<6M;4?$#8Q+Z}1MYgQ`#h76qdVC4hINU_
ze;DYC)gj8jF_K4#;38z3kpyDUxcT)vfAJ^lqqs3=&pp`lJ!ETSmAA=ANXcmkBO{E2
z7+_+&eehyyQuzJ>sHOoV@L99#>Hy`~kB>h{EO&|+fuxYmItSN$B8qwqS}O9v=mile
z0mOeDUxR@j)j~*%j43!-DkY=BCt@71W^@&U*~mceJ^B4ZgW2tszKd#%{y66<Ukrj<
z=*dZvwKIa15l4gG2i)HN|LqfzNGe{<O4%6J1%|BfFlG|J!1Vsyw-U%ktXZ}b5m73(
z(FDHJ;oUS>t@$TQH_gl<)4*@Z<dS_Z)UywJk7Qm#Xs?+>VHc@{abD}1J`~W9(S|IL
zRFalN?TK(?&VkU-h3RD9TdMDx>bq49{cFLI4y&Svma!VN$D*6%>~}uwS-%3>;AAu3
z$!4yK&8ld~idGQ)_E{e^5iv_i;~XHeC^(u(6TFKFF0GN~%|}rQ>3MCIc6;qts~(9A
z7!)5*G=Us`bnr5|_H};=(K#&AFpwxtxLe{|8ogPsubYjLh1&DOiPv^_y;-?|LaXe^
z07K5KPOWheV~7$l8j-k?gOy|7`OqgK26*%=;gv?D#pKMTI!e53cCqT`+|Nx%h5=`v
zr*g8(bm^#P*=8HQEFq@O-xz<;^UX2cK35pl1Qco56|M>2{)z#Jq2r=ra-zz5h|tXV
z7Pi$8KI&mE=em9u*OAk>-$tSLt?B-W-`rl^QQ0Bw<15~dOwXKtdJWnkOzBpm&)n}R
z@a#M5Uh1RY`JL&WcW722j6kS2av&rs?PlK91Up!dSp8BRMlJV!vq?-RT!yRWrtz`y
zu8$GnHQybd@y>bz=@P{=BK9`K$`wX;!CvfD7gQJj?Fc$e?Com-m7uP?TcS08_cnGq
ze+p!7dS~W_T2%{f?|YyqrbvV=1#D<0pqvJJzOGqKb3t8qJ~x8X&_XBea}t{rD$1-o
zrxAxwr&o03qKb!_7tNCbc0`o=L38uFrdeOJ&yJ6IV_wnUIyqCA4WT9|25n1Jwdra^
zyC6L3OObFXT*KzaBE>CbO~GLVmqa9nVuqo52}skhlti|@P^B6Zpm3j_3%-CN6PiZF
zlWg6;g_6L066gM!U{-|i`Av)n@!#Cc%NP?Jj2t2NrY%T1Y1%ZOq(#T(tJDd%U!uO5
z$to{<U*dX-tyMjY<m9xQ?u~)oM}3iy+()c&Q5Pc^T~VH>jq_rG05cB0Zwk*k0Dc*#
z1)vUH9624hk^G9-D0zGNzoBg*cfr+2+*g#WP<pgb<cy**iVxSZNYoXT?+6AQnaw^z
z(#bevjl5F0RDRg$WZbAT=I(Q`+V=BR_8RM!-N9YaV!%)KVUGfKvPnqjmB?nB^D*1O
zPz_KN2_{Y{HO~oAg$G8E>C038svGPE`xoGV_N)Z7qXB`2<=P6A14xU*aH;CA<!NLX
zBLdvit{EKT$a=f%OuKVVM!XszOGq@3pq@;8@AYpYNwY_L!^XwTvFG1(o-4mwSkkO`
zSr09;XbI$@u%dNS>`>AR$VLi{{29s|P-ZLcnub6CuzPMDV0@f}uj7CcX2j@(pFUS1
zNz6!+eUK7OCMyi@mI9kJb~BVI35_rPMN2(TBy9XFW`B=(G3(-`8B;~!(uQ2&LPp3F
zDaj3;*mbiTd@epfzq2O}ZjqTew4z&`Jm>a8&r!~ZVZVrw=*-u(EXyyJq@8y+0VLAr
z+M29B%{A=i-6AC&r_SH=YA~7YvKFk;Yt_<*%F!{mpvf*xR;vNsXM~?1DZ#S;kqH~t
z=i1-NeoNq3A`w|Rarh`tCpsxTM~0W@aZ8ZHAs`cJV_1v#K13v<apBO`_P1%W&Y+iS
z<)}m+3L$5?Cb1zdic^mcJuhYf{mr@)!}<tob@o>!S4*)To5QD;;;LkXW*YoJU9<Xr
zqHd@;ReB!FEF!>Sv$9*HqCAiOt;MYGt$n=SOm;M0CAK93F$&tPhwTJOK2pJBX0LgX
z)9{ick~&We5Z{KPa-Vj3pR$8X<KHHL3i{aH2#{wIS?3SUiCT(itV!#o5Q)5~sS%ru
zQol!*b!$|-03T7ak~HW(Z2|4M>HOTmMN^qo*QTLzCbTD~7+&TSFtLRId35WK5_P&p
zCX?^hr?ap2NUUAfjV&V^kYAOFeJ;`j_T)o}R*f-lk(cOZ_zOeXv&R-s96k1?_oj2t
z(@gfj7{l*nP%A7dd@Z|-_!IZNfuDFlUBODrJiW{`AgadbmBB@(;Lm7$P`3b{-^y)c
zX7tST4fP&OicvhNpTWPH^vi^iR{ZD#XQfS9^7b!&|Gw|u`A+tQ#wivqyooG~ToI0y
z--ms=G!sh@5sNjs-y3K64Uq?_J)`qO?^^?wkozXuZXH`x8+{-%zEzc$g_O*r@%fY(
zqtPxT<Cy46_(P<ezzaXQ<iq&3rt8R-j~rcqy42!4wC88tw=zEml5~r1g#_P67&xrU
z&w}lEk{(RF6nH;jTN^J|+WURI?c;SsWqtN@Nx@aVO6VlogW@X0K8Tdk%dU#Du~Br8
z7YtGBU@2wo=?2>M*uXe}tD{+<^}*gs2HGd+L)s}KwghIJ{LpDmn%ws#q$)K5VrfQO
zmo?S{5|Fr1!PcMxNUqnN2NV@Q6GTwb(-XMq+zEcZ>YY|gQ!5!JXztYHuZ4;rO%~!f
z&WU3Wumy2VX5W2rI{VXPQ__>fVdkscL}c4cJ1?hcXC=xkA@;#OK+7GH`C}w7Bt;r$
zaMO5KxR@DpN(<HA75lEMN5z&xUxA~H4sJb>P;`pjQpDUd=?BX`(W?xt&_F`?PeWAN
z8>V`f;sxTP7rM{4?V(oejoebM{zLVqBJ(q~qk0^d9ZaS#sSs-SHpqwedl7IA!|2Xf
zg9AHYO8#SA$%>OGzer$DyFa0fAxgO?*bIjkh2j8UrdBOd4!wYl6Zk`w?0$Qi@}<&>
zCW9Fwg?JXLFuDzA7YVd@P^AiIGU#3k?#aa8C_%Aq_?!_CyXyvxDk2~_B7g$YticAM
z9t4SDd~+vwDw(RRaA?J5Sy!(J&UNDNoOVSwp$Pe6^m`3MO~Kx#Rc|a-OPR~woYP-@
zBtS?up#dY%eB^*|MbRp0bmGqW4)I!0k`i`H9JvfgBq8R7JfLc^quVFZ0dsz_MoZmE
zH;sCtHL$dXZ9Y~5AGZH<4`8&!qytFP-B`C6B}9uWN8J1;9&1H1N_Ha>d9)%LN3Ne6
zXloFetuSCWgKYee#_xsCc63frnLHv&l~av$!hKVqkwCgjiVx#SYIw;ShA=d@#M!#Q
z$>KEhO75`we(uiZ{GM+UDp`?kbi@ZA#=R<1mW!z4jBByme_COOc|gwMX>h6$F0~0h
z0=vmbLxEqgXt9krHH03YI=~pg+-(QDc*9ov766Q?oA#nRtozABis4dX@I&NTCYpp$
zTk;dBC4ZTyl<x(HpkT1Xep=?%L{^!cGEg;w0!sMSUDjuGFaxx)Z>0)5SH-5dt{L`X
z+}`^YgKm%Z?EA^-o}Ydc25(A4F%E@5M4$`n@p8l$DG?|sKaYi@x=+60+_LVC(>SDb
zQBU3MxU18JMgKOWGm=2Ti&M28J_gj#P1;ns^yT11E8>7uby<+Mk(o+DPLX@3g@D4~
z&3srvg!If*+(lnt(g}u3%;;-`m$+@vydI6ptUs+Ap+FO%W(mkh4tPDN6j6vZ?JTo$
zpiu}xBhRFj1k=>*L7Q4P;YoYVUbDhPzt^v)<_dcw0WL|=!+NMGHrA!MG(PzN{n;(a
z6mN&7_HQ4*nAJ|?hnzq}^|g33!yecshA?)G4uT1H*sUI!P&|ahr|iY}vp<v}3s=Mp
zZ(<tO9f!z~Baksf&!M>HoXMC%8B$iFQt_;D-pw9W{?-5rrtK?A+-B-x6*0mJxk|Zi
zqc*9ePt%M)4Ol$A>~BN0?%+wERtItmyFhQHVn&T(kO>?%U)(l6agLTK*thf<^tS=i
zPOm?WX_~x!sDODD9xz2u-j~f0E<jEi;uyAYJ0S?(PJ%%MhS5ckbwMTva2u~Xe{Ri<
z+Ygqp5zEJ``wwBHkl>Nija(S{+`9izB5*`{cYEYgW1H^wy&~@e0;s{Er0R`2ZMl<s
z8nc)Eht+ns2Oxo0fRn4RMkqd3L=)(tI}cM03r!>uZ|e>OM8RStH;uTH&Jr(6#D#B$
zj3Gl)CsN)CO5{9G>~O5vFpR5XZ<c4AOVw$|okry?vS?g-;n@2^&N%G)eT&Rn(F6km
z%7Tbv1h4ze?$@KVmq|6^ski|VV>lkI>cWjGr9;yJu|HfA;nFKO8OH7R2e~`jM8Y*m
zSOf-oPbBjy1Uwu0ksJka0c>8{V4R`J5EZgNqaVVVGQ;%Bn~oHZd%aVW!-w{{R0XkE
z@;4$iWPcwWF@d?DF$YzY62$^4;RX-5J}MR2Dddwn>z5V_V}3uxyXv}92r=clG*JwK
zhKn^Mk6E{$xGd4o{O3AP=d$;qTI*OBQP}<NXPLc&r$DD6q#V6vC`ihC^~TSzSNom8
zJ(-K;qrD4L$8H7B>BY)0@~c^JC6SL|aemQtvKoW=1flDO!cGUOw*#LT`;lcaL7;eV
z)U?I)q2Wk2%L8%^MVe>0D_}sMb+H<wsb7)gWB;uL)Nokpv9E9blptM*o@MG0tX|Gq
zv<bw_;y3zKiuq!pz=3jb{7vO5$xSJPQg1n5^Nw9q9Q5bi{wgtt-4Y>3`imaFzwA7W
zRjh@}#Lee)aH~3}3k?`m_zzmQQZY<uIB=Wl`;mX#@2e^o?~U0lL3N*Bh>w2sq+#sK
zaSHTTMNmXBpU6%H^x6C+A)nEY%n6SLH*HRWatyrbqTf#=3^yEWxRpR$$to*ly%FfS
zxh*+k$u8lK<Ey~>UJu@tOyyn`S&Kyeh|;%+Km)7A*1BgZHUN9H^;0gTDZBl&999%U
zz5Pf36urj;DLThRv4vhmJL#q;){hjHAe&I6+%d!v#`0H9mEswtDx0e3iO-@y7%}!X
zbU-kqRS1~qiMXh;R>P%7dy)Pol>X2^Vp%^aok%3X%0rxKtQMp3OrI8*4p9>XV-92&
zZthbEwe3hs8pe+6BrQh%*>6Dv2a@e|`ED^Z#eV^%zrNJ;Mr#D2ChEKy-t!QJwMLx(
z-)^4u{1RYb|Gc};9bMEzEAZJ8zp6SAR+DRv7E3%PB(_irXM9&W|BmUtrC?1<aDKO5
zmmxJJK&@QYxJp-?uR%6yr%pVp7$)K$QuJ_HQN+;i%bUk<qNR=NLJ7&7BWUsn!`ze;
z;`_;>ISBLyV~_X)onA;#+c{+&{pzII_J()a%UpKu6<BzM=!`^ObSY#p95L2jbJ_Wd
z%U!2*CY*#X-6cPq(`jBP_r|_bPQ2rq57A^QF4>YAuK<C-ojkdMmlZultm*U5a=ylF
z)TZ8Pi)f%30}&T-)e`qmMcb0wg_*^cVA#W5Q<^pRzU@60#*fAINF$2r3%Q7_lqaK;
zrF&r*hKm}Pu}IWLg)0Qa0LSu-fs2O*h$%~1hr8Xb*>F*vpVIsN#^e;yo+BOK29+p}
zp)2ov>vwsbR0>0{1n?vug+^|whzUmZVDJb7;M}8UY{)ffGX*r;>)a(OOh4(H9aXD$
z%032|f7n+CIEa8nMeZwv6RkDxQvy{qMiXw~Lqr7)47Fc&gG8$+OxlVW%D6&%tO*XZ
z@1n+%`x1Ry)?9tVT>`ct&qZHsbY1$(zejYY9@=v(7D|nBnRQWBXftQBz_n8XsCldO
zVIn}zh@?iH!5)q0-TA4~hTgaJ=QEosGSqok53OkzN<_?YsvjvcH-&kV&_LR{6Qh$<
zoTT6YiG-&Rvq_q^4`!47Id?3VE&6~e-gckK$b?uCwcxS72!}y<^6k=q?2k>tNy(N2
z_1UKJF2_qlZekR0+v-GRLN1ibV*V-m0g-4WAFf|BAHM2XgO7VhJLZEiZ}URM8+AK`
z!|w6iXcQjcfbU0Se78^RTK>zeDruK^w>`m2IWmf}1;*KMm<urxa0itPaYrUl@2l(!
zo|d$+?{v?wJ<roMhwhbMfB#bwU`Hm*o{|`nV7(*jK}5r4hZAO*V*W}nRcd#W_~Ce;
zVvxKsKw3i$el>ipax4?B1`q3z)nFO?EUt6{ksN`*noA}(hSlzts7IW{Eh~!@mBfrR
zZs)aiV*QqpwTwN=x!@g}v$h{Owx$*|(q;$fJCGmg_bM~G;*POr5INFe*s`ww(FQ|0
zh<h;%G&x`ehJvp1a2ljx9u$#;@xaMYv2LO?J*uc{Lv^*_`=y0S?}k$2!y`;B_vsm=
z!^B?foG1)~sE*jJSd3y{+jQ%Ue!l8HMTeNsmXHe5n3)?v8-jSU7S9%oeZi``>N42_
zJ$B2jx-!@aXuBM<JW7n|7jX=SmOAD6VwXusx5;!_(Y<s!bxkh;Zwg6j%p4hH-x)uz
zvgd;$CHW=E`W{+6G*Q?aj6x6$?pP9vm;Kr6VLC&i;K0xo9hGS_!r<bd6!Pr(C|;gq
z|B^o%tTh&LhO>QQ`y`%-k^uV-f3Fn(d>HsfWIiRJvLx%M#a{ZcbO)`^GHkl@RZ$aB
z@{!OkYnIgY#))x}6EaYzzzIr@%5>|ouFJ&Ozh!n^8elk+IX}@h@06Cys=r*g=|4Zi
zvhe|%A@oT8$x#<;#M^<&Yh5lNF*dlaIBA77&p8V=Fos{$tEeWO_x8NzY_A+6sEfW>
z^Ur0Nw&-G{`F<Q~i_#_p+`3}7kNh5{T5Iuhovp8O-dMn3=$JqdEqp7^vmKMr5VT3Y
zo?I~jOo>JF72OONef~A4q~c6SBsltyHOX;~afrBnAd80pqYtv`Rt6_vd68@(Agv()
z?N3yO$z(`*MAT0VTO^x$V7o^}Xk{Civ}@{kFs$8e?o)0s?Y{@ONAoQ8f0FC6jKAFr
zLDN@$?(EC&NUDP6wh<ixcp&m_*n*N-0PRd{I!$yWU|>-(^WB}_qRuWepDry{j!sqm
zkvCmdOtDeZe~vg&N*?5-iIE`0uo3`%r-MZexMmI8-65c59FE9drL3HVUhAd{>pj0R
zbfdC1RdoSjRjXC$UWm_=Feve5h|XVqRXPo~5QRH?hF%~9-`H=o+D+;akYkZ)=;iGd
z%{@vr?G|8t-O1hy-Lz8bx;R`~JW|Tg;EO%&_ZPL0wpVhioG&&vN>zS}uJpZ4U-NhA
zsQ*!-TDXR4f>Fs4dK>{~({;h5gGu>o{ub+NmE$;flohFmtK0lzE7&LQvV^OvyE!&K
z#Hb?|2}UE6KjrOkr1@Qkf*U#NI8F$Akl<n4L;<xcz}-ai%y~A|Xf)I-PVbWUZRgmE
zH&a-0EaZlyL%otLn!8yKRbiBG!!~Eta8`VuPA}?Vjqk(JMX#ech#6f*el;_$FxLSy
zxc7(}x}_V4M-WRZL@&bSNCQh4z83q;k7C4~Tk0=A+By5<NP^raY0?#952LHa3l+s?
zbddIn<(QY=ZR~k%xb(aWl^vT3WB`nW$RnqNTn}e_-(<TY6RK#KCcktC=v3EB*~_pX
z1`3`UvH;8COV(X_zd83R^tit#wY{9F+wb=W?nvZyEwe|lzM`-H+pP%+ls}q$xik6G
zq_}k|zF9TI3|df1Ol%^-QP@a}UuO;OY0N)F`7mg%gO6ptACxXmP2FQMv6@1$i-Y6~
zD$?Vq*FAo$%r!RFjiDy0@QXO3%d|Px%M!Pu)ziG`5h#xOe$P{vta3ZmFDE$SPgizk
zD7vip+liL@&t-Bb@fneR&+rFa5cw<vr3B>l#J^6U$@9t2ot5T`P)3e=@hEvtFl)j@
zF>>FyYz6A8(d0F?U;)G?EPJuzvBttwZ@5?)!bFN@`RwL!C^(bAMs%vs6TRalP{BX?
zIPpM}zqbR7PB^nUYl3-Su~b7nkUOk`yL4GdV{wq3xK#l?xu$KwyUa0=E}auEMAne1
z$3D~e1c=CD@^hUsWfhM|`E{wlL?@zUJTwvy%PmP{Ax39E7Tncv;*Tw4ilvK{pc?E|
zVk?cV&u(i{34|4KW0Ot@ZxTkPieyZ8+n7_hLQeEb2cf_aTYl@ksct$yn0Q!q6FgSi
z{k<x^Mm&yehd@z%p(|<gX&HZYP7VSoEwi7LPqku{R1vG*9~YYg<r2lwcq*&tFxGfJ
zqz&m*rI_8D$-sI;b7F{(xGu8!{)6yp)pcv(j4z@s4Iy9i-KvPA^?exD2brpaIi1+4
z^-@MUdQ;FY(!7ds7(JGX89RUQ_YEU#jbT+pmw(+9I*yX})a~70nEYOg8J#ENz0Sfz
zs@Ur;W-29j&3{gO$-<oGm_`y&=<cJh$HRA#57(=9X40o<uW^6zd@Dbxc*$9F*YGpk
z>(w`<uOAkL8{U6NW}WT);wN~}wyz)zB=^zOZ(_2M(czXwd~(QGK27u*cADCh>x~!j
zG%KY=zxSFublLsTMPzY^UJ%98ggWK>jT#Ac9OFnLRCRUCCxEk76=lT(BVGs;0Knh_
zf;rAI9C2=9JMv>^My8+#YZX0#P96)25~ljq3hq4de_~FEliVJY{^CTY)=5-ovog_+
zK;Z3s144JSE(O~cR4*lk%!yNkgn6oC**R8W?!d^cU`^xE3z$p?3DgC5(6reiM?Dlj
z2}yw92xiD3Ni$@YA{}^0#$&dn-UX2Fch?ieV=m9Z$OuKEg0Le}Ci;FF!QWhFq7MBQ
zW=BZU05K-I$4LWUM_<UA7u09{cD_9!K1d$>N_u_(TX8HU;FYcidS7dwCf@3e>8yv#
zCd5EUPZo>hZK{eh_`a^F0KOc<d^zZwp@uyXAn$l@l5!2S6@XP|PosN*?s5a&Z%kaW
zDhzcbCBGAKO`5fTs^1^37Vt~o_Jiifu*CqnQ{VK@|CYD}Ge^AQcbw*-QzKMIX~?KS
z7J;Ufzr~!TG23Q|oy7T{x_I=c1gA$AU@nYw@$-?aES&$i&P26v5yuWPrmATlHuRD&
zPp#>yTO8t*NOeqPs)8Ev?3D_nEP{?lpMjX2aycE@s+<QS@5Kq)x>K+N2a>jFa?<q(
zhuf68oH?!e#!2boX18+Kw9w_n4K~qepivfd=bT3ztFlRr>5cmHWb`C7Re-KX+!?Wx
z<+vldHk@s=1XvZFL69{qCO?T9cLsqZm4Bj^`AJVJns=k%I@E4|WWs-)O)Y9^kmN^?
zVbEXy`lsq)DD%?l?T?<4I2G=5B)+1&2dct77zNXSB(XmkL6L$Y8jT0KF0}n7wa`|!
z&8_%B2my1RyLGU>%==k)5fH>xopi%q!6tZeDR8UREAst}T!YM*+o0wxmFrqC=}GB7
zUiq|2U#2DlX*={`2Gi#Y_92yiPfe<i79d4GfAHJvPk?rjk0)M8(_Rx_+9Vik<Ri5#
z4Gr;H2G8ee^L}Z*e3XILm%Zl-D+QQpMbGFJq@>^oMVmz@ONT^<3<v*AyEX~rqLKd9
zn^F!Gm#xuJ%-_jjgHOsyya&h>dYyUF1mHZ>640brE%vwnh)W11I??`P;WR0QJsX)k
zQCd`5;U1(hINSlF+S)~lWIHX)_EjrZ{F?XZ^s$S6?=99CPGM{B*Ht}=s9>dh#eEO@
zfN~rsy^2VU?+f+`zy+jJW(n|U^v;BVC!gh(S*X7qg*;X%y3Fj2*3R5sIMttuo}^Kr
z@tLu|hm@dy$;hLp2(RL9;6$Ghk`SvMJI(S$dqRUvKw($RIzJFut=)U-Zw!2YyzNq1
zJ%6#1xmR@w!dBooaY*O1B;mvlYD%^qd}rw@zU0Gq{s-EA(@(H6AAu3QS>WSfF)(_v
zw8sGqj>Yqyy5kE#z<pCSm`m1J)w_uoHHVI*sbES-CQST7KDB?G<S3y*&b^MF6Z;Z_
z4JMP!9r7(9L3lJWL{eK&wxUtMp2kJJd7;pIajF!4h@m4>rKN@ikQ5iohPl@Ja#=Xa
zKd<|$RqBruy5vUaK!ZEcO{E8IsBzV|T#+2o(=MXKT}BG-CG&)Q<uR<#-|P681hM%!
zB};3HVv!HBMiZTfH_B3p`Fa=^sd;7fE;u>mPki;3wbtP-WF(n)Ov?X>-7&kasW|Sh
zF~z}>AQ&YsQJAU*4LnuEg%H|$T;A|YE&;eIwOs!GDJn@<#Vc~tmFPP;7~?-(Gw_&0
zd-l;}7%h=9?g(eWA_Z+p2h51n36fkDC@MWe0hPDyX`H+;G*MdIR%%@Ik835J>gObY
zg3lm4W@9)u`K$-Q<rmM>(p@`r`VX!vf+NE&B03?aE8`pyGu)_v1LjqB`@nXuXWO>t
zK^m)Jaf~vPm5AD>rOg4chD&tt1Z(Nk>sN~+8eaCy?})=GVIZ*^Az>FkA6r7~qKHpH
zRudKLjT4wiEqI&P%&J|w==-}|2$+-Q=7-!hy_-Yh@pbVaJqLq$Z8@M?rFBKGY5I%!
z&DTYGuoh!gKT&10N#80hEnKg-i+AY)ad(k38hjTQdh^gH4MwlECdXeSa*4qx?xv(L
zsPjvYOY{UE2qKVd5f~Xr1TTo_cIDV>Wifg#R*${yj=qO97dJ?P=+Q7C;mszK9d-@6
zp`=;-ZNA*6cD34kU(`VX^Hy1wd)$A_?RL*0wuYA64S;yvHAv=}b(FEF8an9y)hn2_
zEv@FOBEv*C07ey~rx|kRI1{W==sKdU-iD&;azRm8aO9Y}SdknNCS>Membt_-ha_Mk
zlyhH#)sO~+!_fCCapXo-zwK9_3C{SCJ`5`HRl~@ja)0h>IxxA5^vT>`)kFe8?GcG{
zp(kNv<MwxEUsuEoV@4~V3XQNms~T@{c&t4%PR5Ot-NJSZGh1gUK(eKne7$(G;qm{H
zqeL3dj`f5al7_x&w0<X>XF@~Tag}~iDPOyBjNGE0H>}n~uX(hQ&-yJ`-1)d)^WSm5
z;nMv(Xz{-}y*I9RB?)?jH6mcPVTYm7kC7IVMAM2Uh*xyT>S{4t)oJgWHHxh5s+JIP
z7>*`JL)t0UVks3jl0J)eb6M3|WX-POq+-lbG_qmqi-}aisGrH|+J;efv_h^aelo`Y
z7SH;W6Aul$qs6LuR~?fWU7bTVPVoVQ9<W|ZXZ%W*)Nxni?M}})?I-GW%W1vat7~yO
z2~QToFrR!eUO`_}X#Qlkq?FZ?S}qC=gvKeq#pqHGIEUS!CEv0uo8Mp*L-l_%nT*H-
zeP~m$&X@w_K_nn4{LKNkwg_A_*&4I?&#6Sni?|uqa+0T_A6mwgT0B0IptzFnMNb>G
zxLZpYSBhoq=Y+iFKkv&lALdh;n6jgP$)n!6O}^IR6ChDSzLQhq?FL9%#rI|nL$$_@
zyh^m{7HB|Ly8h!B2rv2f+tdHuVK3~+UQM3HY;3UrxRu-5P#H3`T{e*%-TXfkL(jX4
zB+M7Hb%cvEV0JNrjgH2h*Bn%S(LXg;91i7?;rhtg&DJTWTz|MYC_IZyw2~@|yN69o
z?k%W<>A{k>ygZxWdBkfyq_Gdrq`KouWx>Gv>1%%R`|eBrTa#g-W!clqJaoA6xBr3t
z{r~iH`?KT!Z*NL**8ksru4jII<m&Elux=X5$-S1|VH+F0?)pI2Nq=+Mvrk)p;a$sx
z9cQil7Z_?|y%=Z9Vdp?Hw2ZA`thE^19P3XGo~&Fwb~W33);|5Q->F})Rq`87s=e5v
zI^Id@p;*uorsCPP(~7i0((PTz#s)iz)|^{-KQyy*ZusNIM7Xn|lb`HZ?t96FTr(|G
zbICBQykymftndLZyR7Oz{_sEkBSVJ<>$FhhXKa`*Th}S;9XFdUnj6g4gspUjz|_fj
z>x;27MV(JNF)!7Yop&=W-dOTVaU?dF^0Kf^wth0^xu+5*6GpF>abjV8v7TvJJ`Jb6
z<z-!~_$eckOP)!dwpxn#m@S9r^VU0EbtZA?`m8Qy@4b3qmpxc(8-$n#ulupq0n6%k
zCPMq9>9trLEge~}_zr_S!)(fH`M^HQpolZbk29SgG-9goo#dH8D|OY(K3Y4QO<gTA
zraewZ6jwWcw2_J@RVC?ksaSc$N*INfZ1(ETdPj>ps+T#MRJ>p3i@%HVF1%wK*;IUA
z_V@1nTC!C+_1I_}X_Z6-iNb099RQ`0hVvWoT+K|R;tHZr#u+!|w<MV_(WPL8SSA5+
z!)g4~s8oQb__zTwF%|QSd^T?2V4SX-Em;`W$R<bP+15neIPd@U4?mG7bsRU`TD;eb
z>(&=hNO1HSCV0e7)nkgKF)c2R7(B-zAsFK!Fm5+{Ch1xAoQD;6QpK#!SY8x(60x4F
z$<fV`<Yk@7R@OBVQ^tseAk&D2dha;wd)Uv0wL9<syOfu(lEzS@ZpKrdqJ{5^^?Iy+
z5(!kVEjVt{>UH8?w$>0f&?z%Pr?q6tY_SI2<m<K{S}#82?y|3t<mrm%S$HnV##40`
zkdi<bXOK^1ft)7mt?#%Q<ROb{n7?big+$HfTYB&OlVa;NH+kN&3P`(He&Xn^Y;rK2
zt(WWn%C7f!3=d!wK6y1cTXhCi){6w3GhURj0&I7$BeU-0m+`tCuQ~s~&7Jm_-Nk*`
zQ|1QC@{_dz+YCEe@=B??S4<eHj|25`dEJu9#*;;hD>_XEGHzsxN}r0;ekME}s~7)c
zC+)orH;*4;%*K;pSKK;0KkB`B!fI<#VgAK=s|H2EUNS|+dBA9uSSMH{hnouKTw`=1
zi%*LbuF0|0m_BS7gWa(#3a*|F>2>WJr(-1exzsGw)KENj+yAT!p({i^7wmewvexy6
z58WWJA!$xnS+%$_G!otTLqFL<FQ=<X)mj}=XY5*hk&kBLUYirIqjSTgu}eWWXoQ-I
zL1~7im^0MW6h1F7>K&g_w@-b>&?vl+ug|-&B$SzKZ5i<sipZx%WAM(Jg_84hjZ%Qv
z5SPif^ZwJZr1E%2i{KOt8?D&-qOW3F)Qx;;^xH@*9F3p1QV--&-3nf)`=8ml!D3nL
zn#V$Rq*C>(xn1m<|Bz2;xRN-SBX7tKvLud}KWAQ)$1R2S+#Iuw!*x-eEUsQF`<AM~
zxqN3VMTHPn3;zQR2P|~|-`^GTJ3p+kwFUW+f^Ab~d`R8~a~Y%YA^0>E>j>KtoDayM
z?A5HLm3Jmdv<-6Rqq3sf5c-fmwiXlI1aIdKyy(sROY5in7alh<+|jOVJ<C@(eWqM$
zEW3+caq^Ig;`^X6wvvjey^fqul5M0OFs?X-SU$$5*uI$<#qyQ+a^eQVoCWz1>1RF~
z8Psa$zj%N*u>v=2g(dl%%M+;>Z$HI%#$}F9D()${@e~<04&@VsVoX_W&Ef-?MR~`I
zU9pXtY%ibSb4^=8_BDv1V5Dv)KdHKTb1go9G9F1&S$+-Bo|7F>@q8FZ9LQF(M*S2T
z;;dj*8nN7Y>k5B5BU`|@iemzqtxg>37qgDP>KrHknXPEKSERVxdhd;=5N!O%NOCf2
zfk2*@NX1Xamu1Nf{tvH1^2GBAteMtW*xF*Qf84NZ67E*J_*g22$kcp|&|~XSkBo53
z=@{P%uf#P*)F1a_II<X6T)u3V!s@ibtjd3q(+=f3<Zu2dycTA&tubTpFe^5eQ3Khm
zwJUjQ0_Lc<W@D!T1ITToozRi&%aZ@vDmcjIH5s?xJ$P6RB3!Ts2YG)TsxySd*&jc0
z2yBiMYEed=f3-U6{D0H266iMhUol2LR!kF}0}rsHR2^|=8E06W{HPpS0Ai`#{h$9^
z^p$y`?dFf8i~}x076B{CEy(V$FUQZfu(y12L?f}zII<E(5n~%SkA9b(Phg$PlR^ny
zIUBu`FY1=)Kkxrve$5^7!+3r$TR+V^QBWCVlZCyg)Z$^jGJ}+Nl{&2&49w#A7OfG;
zB**MZk8<==49U&b&e|`SBR7&iYus@V-TkKbI%7Y#xT(5Dhg5hQp?0$Iz!g)Sb{sDp
z*o~q&S|5sc#W6{X%V=8b8*oMHWK65j@FIS!zi!_<e&KL7GrH&)^^<;SFj+S`2GuFy
z!O(IKK#k$y`hn*&E$VQCBkzqNFp#rG?+Lf%v|pvYk*b@XbIF-^)JZRvF+Udmfz`<t
zf!tW9{g`DA<(SxE&TVl}11HIaoJpR-SMtL8Ne3Q0?X@iT#`qr|0?9i0KnnRX6t90~
z{?|tzeV%VW+^E+kUWD=L!b4VVp)KD~3#JSGWz}qgC%U@hM%M$#z!w+Vwj^ig+&yJ<
zFB0b)78Ke)Xwj!{qImEuH+F#LJRv}&c*mnjU>)W9%V1M2$nX?h9+TfNjj-+|JCez;
zT(6%u`S1J-xvmzqg=4|jYnj;j{lu{6q#Q42&A$JlcR8m_Z`zu7W{avk|3dh>Rh^&x
z7pm(-_}K6Ehgm8`{-u-E%e{?>V(Mfgw&wwJ$e%Yo;Dghn|59!La+k+olHAZI`WL$%
zIOtJjW}4r~>B)_zdTH}Pr`vQYW|u#1S{)Vpb;}($3yW%Rr`^AZ4&k-6Z&8TbILAL0
zl&Ln)JNZRtcDlHEt}^@RJEM*1(~rJ5nw@xOHmh(w)x<lxcj@;(#qzWG>&^>}MMr+O
ztl7s@?qn=$z2LZo#kN_W@YdaAve2=hv{tjlPn}oB9#mHsj{Sl%_WKJDS$dz_^|QL9
znQ04~-C`I1q4Uj?PkNIzf0D9f%RJ2A_8#SN-3Jevy^Zl#1rn${kJ`Dt?4Lg=qu|zK
z{cbLt{WmP`#o4EQ#b7Cp>YX2*zQ17g*QJl|vz_zUMYE4)on+GG@7b<%)~Q%+AbDgm
zNY>M;F`X>h3%oM>Qg$}MY6k)Lr9A4DjM@ME|Fm~5U~*j5fvzf*<+jn<-KF+WmWAC_
zsu@~?Y)e8o`jjkG^;F9vd%!(nBn0u|86gn}aby#RWCICZts1!%<drN0F}wL<NfyK(
zNkDd-ge)YUF{4E!PAt4m;v^8u4zFdyx@AmOhUN4A=T`STG_M}11vZ{L)AhXf+;h)8
z_uO;NeU#^|wL)@X8qHh7Fw-9tzhUiP8x&7Djyu>BW9CPE<$_P&vG~jB4KF*CN%IP?
zNvCUNkGP#*=?*-%ko64Nw6FM(=iZk&_U*#q#e-Y+bb<9j*FCo7(R`lF`Mu}a_kixQ
zROe2;RE@pmk<PETy3g9vTP+Vn-&pDfTRx3Tcktp)3y>pPr;%F#VeH@<&*ej|dU&H-
zr|b2>rcCr;wm0ZFwbt(H%|hxhcy$K7+UA3ZI|Goktx~we>8)O68U7JBABN?wFs>A`
zF|}mbY=Hr)-A7h|DRbwlTK?FUDmtJbT8y4sw|~geIxFBA<!FX?*@G!(56w|u<_0OJ
z-0RWrl4mi+*vG+TokmdB-A-fhes>AHaV&p$^=?$_G^)-)ckfOs%PbK_PHd)A2Eifs
zF8i{JPE>oVuW^=q&$cfE*G?+<e)nXcpQs+ngn24D%$KSvTWd*%{alu0Vxv?oug;b$
zmRa7o=V18Qe_Q06>kKVEg5-ct2e;hspt)Fs#+yBR&;YqRBQ_WG&Ak<ij-c!q5HRR8
zB3|Da4OZ!^HJCF^B^n{I`Q$jAdM2~Zh;qHvV;^!3E#4d9*gfPPThwWE@gWO7dg4-~
zQnhH_8J#Rt4)HluyvH48sme%w(KCF{80<c>en))al@RZ~jOW0W?GL)AV9fUY7U1sZ
z^pVV9%D&6~#&30)gIj*vDLr~@5&U$bx-o_~wLE?`8HHqGb^*@avL}R@L2lD!&i?GC
zuUm(mV)m16XU1g8PWe7Q4AUtje1Yn=i^9?jPj3td7a?1MBko;mLqx(|YX^Izlz8}#
zeZe~n_X7HG25zP9-29ufMH(*rpbpR7_j7d2>y`!9<5dL5D$8p>wCc{tYd@T6OD#W=
z8GOgPnKgd@)vW2;5^5twlPMPPiRKpj`tm-wN4IWcjK?<Po)lPb%H&6AQf{G7Xv~<E
zj{`TGS+^{6df5P<6>+tm>fvSZcxUg3wEm(rD%Q`ryY+0|k`i_5;kAVh1Dsu>=YH2^
z<)2%)IqXy*pIh<gLw38l+D=ynoRyYUT8(sWcO8AX7xiup?Gsy5G-;z0<F_UAoL<V7
zGc>K>>d><JRN0c@xI7R92dyiY4j)}RfF{n*vit{-`!XeVx#wiI73`td?U$DEW;@Jd
z--T{x5XO(>{iqTg@Z6o5hdL0JL084-QL?mBSh_+))cap;?n>nh4V5OZ!D^VD1r(DZ
z6eARdh{_fhQdo?PkpAhOt!NAC9WPw%pcOIlnx%irkW4h?o|G8OqC(Kjtx^_!Qd@3n
zq~U^JfA*=37qmTpP1hCPHTIpst(-ef+aBjN*FD*NdRO6!>~&9WIeq8WUwk@xE<bon
z{%~8{lfUtWV~4FP^MBO!^D8=^9zOkFNYwdsaQZU}$ll-wyAmkzj&%<O@7j4+yd(cm
zFtGEk!4Ky@Md~f52VH^I`6WpnJ-+Tw{tjq+o?ZJVy_{n?KT|nnAK9_)PlBzLy}{{E
zCCI!m0hz}Y7;I93!s)FOaS@!Zu}Qq^t*S)vj<sjtvV0VmF(8cs6>d<N<d4*06mEF#
zi>Gp*$c7LtosUrL`lH=CKZnjeCD)qk--E(Tr-Gc6-;%>tjF-)c*xx}m-nRMT-xW@$
zp1r%{BI+oEg9F_ecoNVjlR%B2zG|JrqI{R^58q+dU)0si`d$5`G)!Nqt`lEOy367H
z(X^+2bK!>NK_OfDXlLHRGzhFcQLlH~5~Hi){IR>rI+SmJB>!5s<i^Xat!}u?O6}Bl
zyROl8#0txId-zi@Vm7SKuZ>*y?LpPa1b1Y-#k%hpm%Dn7kCxlo?gy4T54K0EmhLVL
zv(DR2FFoP}T|0Gq=YCJygTE^Z`-3a<#cFT&HB84Fh%~gp)oz!OKH!z&eeGA@>W2lx
z$=~NbUU2l?nGVO%{VJ--H5T^l)~LfeZVidm9q+TP-L8?hG4S%*3Zo~JiaSg<w|~un
z$hNY<(kS37j7ByJ5YU#^c8{IESs#oGfvuNf*4}1g?4k{Y)R!$2MJ(KDExI%8IFJqL
zu&9nME5-J&q5b^&_wBRn{va3N9i(pj^;?}X+Ue@7lXfk`iIy8);6U#DkcX$<3VU3A
zkDkw2$Jg%8*r^^p(lE||SXrQ1ZDxPe&(_uvUVe8qK49yh*sz$cojT5EDg+xtU+H0i
zAQm(??^nI&zIjtQh;@5~Znc{>?g$dlUuzDw3p`S$cC?(8HL)mM7fI7qS?%Tb7`UC7
zG9_aTr7SZqJz-oN3o3P;+wcO3eeZ)*8qa5LKL!lqW{>f+QXWUF!5r3mJ>-nFTtRnn
zT_acICB_Mb(S1yCt1Xi?8OqL}hVh;<i)u}lZDzPH8<H-{N4#)pKPk-K+J--uVy(b7
z=PT(+Hnwln3x$n@Z-uzXG|T0qC#?3UI*zLcVSvZR)^5uN-UHsM?9zhDR12g`IRgud
zM0U`|WDB!wgjlA#^$3JrTz5vCbx-`w#e5g+?yQru%yeb7?YmCkW%g%pbcWW@^uW7v
z_nNX($sF(^(3M$<RK6RzjKDd${aIWRE+$Z{XR*2$>s@S%O5VYjUF)*Y)RyV?>LnF@
zn|<98E1;RgLSQ@JwcyUe9)nHBH^x|-RvB+p9Ori%KkCToSqlNr<Yq{T(BPU-h8(^L
zIzEk!kuWW{n(dV%he+~lD3g}uqOfeGFhH%V>a=<yBdHZ*pSK6UKuBE?9TXlrwjdn`
z3)2PD(~4Dnd0^NMOPfy?@C^aQ#qSBJR!i;p9tLHgbw&msD=wIjvWy3(4<9OB5g<o{
zYiVM0g5Wznd?<Pz9|jI{T#<oW`+uJhR|06u@P||j$?%mC)IBN__vu9xQzT^$I1+@@
zY+PJ%AcQ<<LCDb2f*w)1$`zbK3XrW8=;pMz_MH!CzH;~pwH%cibKW;_BS`MRb)k_8
zp*!S-9YNM9T;O7w2h0h{>1(w%8V6Hd%8}5L=XooDIVm(`fPew5aO9@X^%S-`0RVXi
z9=b*j1Xp~%(i+rF*?@$WDOx7uN%GY(T#X?h@W}CwL}uABAQtHbP>+GOriHr;;Zl=H
z-Q6P~73Z@<A5^&$iT162K+h%Ak$g0K52l8U<DoQVRUe=^<hi-X#n)5;Z3&=8z^Mt*
zz_nZ<nV+gHeJrP3`HoJ_kcBK{0jQ#uw!%f=Acyj9&Jhn$NX0NU%YXyLVGSDOm~pdq
z#%GroEwBzc0XRZ{vO!y;U}+h_M4;qDm$^ufc(pyNrLYJX;^zXv$rqQ4L+y*#30!mf
zYHoy2+RT+%n_<L0DP^Pw;>OiA<Te75Aer+oAW|#sA^Z$g%Zy{!#gUVb?tS~kP7Vx2
z5P=T}!x0`_gF}o5QVJoA6$)qM^kAt2k7<hs3T=0LQXzTJ?8xGQtGmHgX8RGH8p4J?
zK#kw_S42|cPI~H}4aQk}V08eFh1^yMp%7GJFQ;>20gWLFTo^&1kTC|A@+njT#b*0(
z@8lMQ3_JiQF5(Hufv2A;Klix~$-PnH(Q}zrK{;?4<t+SWM!;ySQ~(PZC`H=DgGlh%
zWFHz>+La!eB}{^jNWrBBs4f50o-9-9nK#C*3{E70cAPd`gsyA5uqU=TB3zZK-k^Ls
zR4u<jzdRG_^eS3zf#T<b4w<CQ4it<bPcn&;tnzz5ed%il_O&ge9yQj==ync=nNp6@
zM&5JF1$UYFM{};LYn`js;00m;#%5O;odtW@n+sphR9^4&47cZRHZrp1T@Zw?$@V;L
z4X?Q_*tWReqF2MqNSCelR&*WwqiW{b27GqWpy>u(R?i}BrPs9|1GNkP+@3=BhgO_=
z)6aRqvb(L<1{+q<FR|<)M~2aWgKPp*-zaZ&nd<;vj=Rj=THr0)u{j_0DA|pUy_)_l
zZ(qNdMY5|h_-Xp`OCQKSo;~D*E4{X3Yc78#*xD6dpUHRJo?Yc-MUV>9SqxHn#*JwE
zmKo4#*u{IY!G_-W%YnV9T<AWqVkF-YuF1!=o990GvHoEDLWaCUOz}XJclED0neNbM
z+*UOGwe(1AF@sO43;|g(CcjKv8DM_^ra}4H*a_r!!0S{8J^OazX7imAVSuJfts#Sg
zGV>VY!KEhFtz1;y!ctb<(#>|*_5o+dJqxb1idWLf<6$Ts$<V(qjTW>&Xbm`gddF_J
zjIQoSV!vSQE)+hEwRmuuR>p4>^10luuNNu>_aW~=*9>lCf6w@2;r`d-r^!avfet+=
zZePsa0DXMP>2~kyeB-_tJ>%RSZt7cpL3YyxU0X8O9I^Q5<Wc+m*|2)}^-QTd?Ak?h
z9gTJ=&Mpkpy^eFhTfVu9h4rQC;PDt&1O`zt%!^gN`r*a8wVe&Xm$3Z+#xc~hyt1yH
zq>8<E1BCs8dl-3VXzaj|7FWRm4|;E?7$CcDr+!eO3JQIEq&_Sj!`Tq_wH;c`#@<eE
z_8KP_^!BY=0IGZz7#sC^!Kjm!X)beuatlh~I$SVbR5;=;(fbSQo{oY$Ja1z)>U1|g
zDrPzccY&|Deem7BkwX@RMRN&K3t^;rbZhbvTZq|ynAS+|TG>dh6#7Ot&la4nf$IrN
z@AX&87rHUO`-&`L3Nmuov?fCxWJ&?cwl+QA?t$Sg8=+or#_fEZoftaZU%_KWBZVaE
zz|u-%D=*Op*Lv%MEnyeFC#`ei9<78>!u#{$HsiKkmcbqWSR<~J92i2`pP-i)C2gI~
z9GfLUNY@k#Zfqp5xQ<)6X^rD&-{AOt!4=DpD0=S|Zi3koJ$s9F`1PesS-$aD{+}W2
zYrr}ncJTH19F_!liZX)?e^Y~R_VR=F{rD&zRhSg@XaD^IZ#xrJbS+@Z48#zal@ouy
zg93o$qHgo~qIocb*=?Mpt~31w9L$GZ$^|JhI&KD2>!r%64*YUa=9Ew(Bc4dOg8G!t
zM&~LB@=^$w*rd~nYrL9mufzp-znd4|V-cCYCG33s_Eg*EcMERRBOIn!%{MfUUZ`w%
zv^5GRuW?8Tcjoh4&}u;^ILVsz9zEN+z(3?_d>4|8nZ{^aHLrc$f}@_WeuKa4>x1&)
z3{}JG8l7lq2s-2~>8(N_Z7>Bk2l=u0P}uq0TTZ1-M4G0-SLL9<2Y>yIt|LFK-Es{F
z_ZMiD4K^JrhB1B}=$?TVh?elO%k)z3VyO%H+-a~$=7sY<U+U%aqV}duMO@Al6hF+H
zv#=C($D%RZTDEZ2eF6$@#dAaBtJ0Xbz7aO*q!(l&P(BW8*Z!;j4tkcdelSA^sX4eR
ze9Q13-<kr!d}o23Q1E2HY+0#&s<?PyJqH$J#W<w;nAbj1#L4cKSWny86@Ddi$PJ2-
zTiCQIZ)N{uu!P<jmk7?6^1Fs<X@|kBbFsPZKG#3Aih5kPVDNJtpITKK!J~zL1SP51
z!(<-w-Uly?k!XSRhoIGN;3)CZhSy^ooQ`0dNDqPMMF(=`i2_r1JZCsYh`QFJ_|_1n
z13}ISLOeVnv(&@)!EzhiWy7(%I?TCSBUFOiVXG_f4qHJ{w}TGPN?pB8I2CmLzL?1i
zEWvee8Z<^U8`qO~z9M?ZQHM?5jb++FCu)QrNd+$NKo1}>)QrIzMNKR6!qwgzBTt4H
z12#o#DeHlFg*b=H%~E%uQR+Y&335hITk(bd;Jf%pl=nw`CBJSzab4Y2vb^rLNn9l_
z;I_e4@(+o>rQs^U&mz8`QGW~08u1`C{4GazC?I<`zMx!46TCL!`*}z_N%(#q3OFBm
z7Kc&Y_w$hQ{rsTr`}u+L{hZE^cOgx7+r0IP_Bt-@Gy8rLKhz5!n_QqDe5UUE=^W?#
zx$^T6*GEos8Vl0A_$jrIz6Ebizr~_WzR&GougY@54r(vs=5faHPr#WN!9w*Q9Xl4E
z*r$YR-*QQ%{zBDd<C?Qn?JVI8eN;R8_h!{Mixm{<>#QL5h8ULVcQk7yv$=F_Ct^*h
zUKJcDjICz_w<mg6VZ+wK7u~|zHKDzevB3^+F}Bi%;idT?y{!=XXmG3rMsW|y!=A6Z
z<ptPp9r3#Yx5LEHwXresPe*L5lMnL|vl@37ssPU!=@-6rJ!1fHVz-Ic0xXiSQ!ndi
zyI3xmQyQ(O4JESUKtA_Kwj9w+tRoJ#sg9bOzT0C$19k~x%LZp7%dmPGZ4y;gG<%6s
zbqvwA+?b)`4rU7G^M2mE?d_Lff4G6sj!x2Ttk9u@X5;de>T<x1jIk0#d3N2kjD34n
zzF_WwI)Row(H&W=A~X>OkPP%qgc1#{0}B;xx6HgfEw?pt8GuCypy$!N%7%aXOI;-w
z;jgK3qDk|(9Tead$D?CS3ZIkKOR1Uhg)L>JW8TxrnB*jIG%!?`VUP=$K$<qYc!3Rp
z&L%W_?#|y(a1!5Bpsp2%3QrO^<&Xmi`LJw=(Gc-KKqu_lMxoIEaGZ5(IT%v0F!>4+
z&wlX2cJagHbcZ`BzU}Q3utiXY?pzVyMW<Ds=zx!C`(C7vtd(4s7)rC`5@V#C6d?#S
z_8Si{@x<b2ltFVJegZ$AK#Pd!n^Ayy#Ns|j$6Jj}MD1v~!w$~DqgfXGxk0DC4?jIK
zb;t+K3rGpQ43_8W8sDF?yPU)L>O-p3#ooxorq-1)1MYm&uNG2em!7cl{E{0Lb(lj#
zeP}@((x`z4Fu<q)5X+Almx*}5LsepGS7;#laOG3|1`nVfCQ*`%E3NjSCzBgFTKL-p
zCiMkf-7*&80>5hDIC9HSCKAiL9636m>7vE8>PoWyU@g@qN#G0|K_NUrTD@%L4XMcd
z$?tU+)LSBeh~`OFcrEQE^aYYiDjx_;uBiwk@l3KH2sY|0fRekkIVfT+QqObG|J9w?
z=kR=*Nnz=@*Gp$fO^JOYT`=+vv6ycb*t8es?-0jT7BeiKG4Z)cL!_E*KlF4cC~Fy{
zal*Apb}$p5nUGDXp8wj2R^hQ~S7Jei1tQ~c!}~%-8KD#b{SH2+5JUiqjJ2iX3@uUC
zukaRMBwZe?07^Yf9?~tkWIeP)$xt#6eEm(|yEM6x#v`j)Bo7U5nC&RK1iY11nt51-
znlC%_;TTYWumk!{sU?A?iJnelVb3K1^B?9YEV5bo>}n(T%Z;BkAdO@z(gNhea>k1s
z$c?hb8}gzhQ<+5Q(nW$vYywU!oUdclfXWn4i+L3(<6YB+?#IJ|4#gu+d4JQu0mq!K
z^gK`syL4an2@`rt5ok}8z&8WP7l=zq(Gr{(pcb|!DdGwCbb85%T9<@D?L#+%htNos
zf(*eLe7Hv{h^T}$Ongg0I@Wmy9HPrgXsTY&!y70(Ly5&FNZyj!&{DEjA<$~a-zFrd
zrH7gWEJa@~fKEah7ob!SlvO}saik-lfD&7^{Wg{=fLLJCebHWJs$3{wg^1x*w_ebm
zrImzQ2(d_14?qMP)nsvzO2Lez{R-mp6CgxFypcjknZvIw?pWdqbV?ty6#b@qE|fY*
zFC>LRTi%M`X#_|sB0OTU0*);lZ2(11>fFI(JuK=hz~)vEAW;GwkAZZ{!f9zHgi0Y)
zX=-o$Kc%hGHnQvj=>(YWMdn6WSr!#Qd#z}BnXS&sHOq7j-*lI|iViFjXS}<!G)Bnc
z=62q_CLpl1ob9Y=xEnI0jj`2wGJGTsp6^+pZMfSbLZ~)qkhLTs8(*<i!UiY9@yo+D
zZ3;>Yv9v+6l>O^Z=Tcr#l;14A{h(ApGSJcyhq=rn*$tJuQ8a|(gwmGQU!c?rWLQJC
z73*=FRqS2CC`&HjbJ;PUp<sCqeZ_{rbD}Q_Y4Fvs@gBa}E}V2>+Zy@y^h(eVScA4D
zW_!6|>ZRBXr|~ST{o${aw{!?{<Nw>?pz=U~;ZX9}zeFlhJSia$RDT*fc+yxsZ`Xf*
z!&y>4>l<XMPu)`@N<H)b#zpDvR=}tu@w4!sJ@t>jQu5lFQLx?BSM<7C=Cy_Ph;MZk
zTo%Qa3fhgAdsoLxo*wAkcGT|Lc!bqHnOs!S^ZAU6r)0sKz0OCh>%-zh?x!;TkyTw6
z^)L^hXzsi{8!nR7W<^i$3B*Uy{!Hf3DlES%twQ)Z?3~cP@p5b;d>p$EWr~Yz*+mw2
z=b_AHcX%TirmPGBHdy|BhWSJDOVy#cbi8Or{-Wp@-leNP`KoQ(7y295BL^AYZ_gUV
zY@31onO=C($rxnZ=H*xjZ(xDCxallY%)0B@(BL7j{;aZ-{5Aw^V}j``?L<^s#HOPc
zy+avMKbV=LS>lATb0ii`$F#tOSq)5xV6sNB?@{QuWhAVv{(w(w5;0I*ztAr%q@Td!
zpfGtL+q?dCF2j;I4-UGn@3|ZCi0BHJuNRCZ0X7|O7pBo*mJ%6LmYEFVW`SmcwZ_i}
zqmu<bovt5Tjs5mO7PN090sV&<nQ|b0AhzqVr3q@sX^C-MG(Y>m1;H<{&v<BHpK8U;
z+cdsW2cb$^or4+AA;tEG+={WCWl+qoFp6=7C4WaU8ubcI@d5RQ817}EmgFG4N`qQ-
zV{DvWIJ^wBmNCyW(4iB{|70~XY=?g$7c4cI&0-Fwv|~19(wL-w!9NUW+uIBpou?Jo
zn<WpqT{Jx<HeTmy;c^%05a!d&tT+*(-jbb%gK)`CtW?bN@-PG0u#wc1bTrKPVbT;l
zr?Fr*EQ18(q0X3|WczW%`zYuOaec__4e%ITB#?_Yhqc##%@^N-lSZ>QRo#gUwG4k@
zr{U$WRK*r8qKO$ynbATFZXKt!G)PoXTr5N;fmUP2hIlrpErhVJ3&o+m=7eC_%2Id=
z6o?Nc3XlGEDlE1cUb|HZaA=gawJ+pn(C2~+PmO>#233L+sI#)*AmgYeFrl*Rf1QI&
zH*@d>t+KVFS$&ikFmE6(PIi~nL0O>z_exR0fIf#e=psvcj|UJT-B$(om^mvy{QXkw
z;Z>y6mJx3MsO$H2IGF4{C^F-PHs&62AOwvFN0Wh1L+9>&TQ$5p7Oj_th5Mh5M&wbf
z`-6t~VVI*)#EXH;$V35vN#TS{AJbcKR$BWCGLfcKy=xEWsusf&i)vq5OvI8)Z@yJ4
zt<G!P4eja>76FLA%k5&Vg(l8*%rjgB<%%0Tgujm3=*d?Kp=2T@)PgM3;=48`+`D=x
zrhm=h8qBd|Sq6;!Lk^=4;``9F6Wu9d##GELZ@6gJ%_4=%=tu%R)O<F%-=;B>29?O)
z(m|&yz6oHXSU?(a<<Pi%#=l5}45eh`AHEm3mU2$CEj9Z=NaQu|NRYm#V7G1Q4*cV>
z77ydR@VUwE-Mp~vi8qSV;CAJ<*jiC@SjNv?5y!(obl2$A6(*asJvq&s6TBAnIVT^l
z&pG*cG6Cj=-%&t5cFS@#|K%_6S^#8%^MZ*hiSt6aKGeh&=E01|L}t;9$E5W@n6RQ8
zAcY&mi^9B{Bi?7NMHT8uf+!(!MC71*${%B=Ik_0SPu5Q~o}iP+QV#i3@!)@qC=T^N
z-#Qxnuly@5d&=NV`E=aF@o?lZ-1w%Y3zm1It(&2wc4&m0(iP0ZAeY&{Ml?4}L@Veo
zAYE26bQk3D4unjn@E3*YeBn`)2HK5gg)GU)Q-DsLm6R2SLZhk4j&qEG(qqMuHiElC
zi*R9t-F?xw{!I{&;7IEcm$%r5wsWH+RvBYdFtccSLC&o#&^ltBd&VK(Z2PocC`@e3
z<b(8dInmG|806K_NaUJ8*|d9qNe8-=&f$p~^X4o%H4T6eX~B>uLo@HyF|kBN_078&
zFJy{&kP?~6s4;~XpgG5(V1f|Wl#Nx1{?b&0M}$pv*bC$I+HV4oY$T^d$rX7`PGS84
zsg=s9ZpkTBIPg}ni=sQPK%aaG$XU*{FFZ(t7h}!~wl&^}SQr<A#&x|^N&3b^Ia{Le
zYLPu?Qe?S|{cr!vA~4t%G7YG2YXUe(PNID$iNkt1xZ_f~69Ui^64x(sAe;*QJjM-6
zLQEC|#Qy2N|1ISX(b*Izx-1lFVj|}h4<<$Cs}GTMo7@S`WGnxkUQD%_Ia#wOS@Ot6
z`SD0el`{IxB1}5dn347ezQ^0K(&m`yk{~E}5)%D5xgI@Yi0M>xBZSm01c5FwkN7>d
zOQD?50K`qrQRSV0w~proWeWsDQt=bgDDP3&iQ1u_mUTf+3=S0}{bRp#krYUoeTf|=
zuNpB_G{p^N<zf)f1YeaZxt44cB4WQpDw|mQ(L0rQLK{fpj63?`29ST`KaYbDV#&22
z0A~goN;gI$#w-VUD1$s$cy_oUz<P*Am}r8n;^P|A!Z$wVd6jX%$6sPu0a&rLf)8lG
z(etSKCs&y>kTeBuLRbS@tMY{qzo_pRWNRXY<9Mj*S`Z)OLsewS3%X=s156p2&w$aR
zX<ZQqJN=&F{-8gg=-ndMgif{Ik7|ww5JP1NI7eXC14bw4D}=>5hb-XTV5=m74Ee(Z
z)ObjJ?v`0HjZoX0MLQhBoiWeGD>+kI0XhCrQkbL#sOMpb#VX=T1whx{`wR7(Gf&_;
zN((AeaX<PRxk%NDwuiK%t<lHV$sGz)M>Nfdb)Y<bxE=L>oHac@2ZbjYsLJF3WMP^_
zTyhP|)Jp?Y36UHI#X}qZ*<a>T@_v-GWBe_V#sxt%2}Bnkv8}b?l7z9#dM@Lk>FZx)
z%2z7gZQH^}uvK{K$<LPxn$wOZ?oXhv0;KRxz^Y3gf;1`FI)lt;h<LNeM^^l@WfBgq
zk(iaak<@_{VOTpcxNuk2GTUkFX`v5cd_Hgo;6vG2NC?bJ99N-WCLS!B2q>Bx97j)M
z&}aBCyw)R*Av&tSVn4WnC>|b(Mxr?2%RE`QG8{Cc&>#3H<6Ss`sj+&VCAybJ5U|pQ
zFu&yo^<}0c%Sb624|vBl7_ntc2J%@OoV&Ap-M9^dpD&W&3|^JpFc7qPcmTQvhV7kq
zXLo)jc9=#R$HVDG#gtTU@bEpCRw1gxDyDkAUL$|b)c@%Js1+_+<+%TtUUvXPum020
z<dIds0j4^z8fOrjO8QDlTtrRHKK&hITl*#c=Jm`k-EJAob;@hLYc4m_Mpp`*R5of5
zR?s$WD`as~_^a7xs=#3E%6KR)LG>+RQ6}YEC&Iu?Z<jclw;l%o7R1T}L$TEpm>=QO
zD%k0mV^lg*#jj^J!>TYB{6=U$WPLKjJdEqbN@p%Ufc!1Ti{2?`u;gLDF%G{CtP&!4
z&KNPsS$F_zRLlkfN32U2jUz9xU9_;Q=dko-M#aI*jTxGtCl(!sPRO!`VWzZ;IS$8R
z*@c{IcfYmdF$3PyO51{ZUKlrHnPS4Lk#osXauq?9V1R`Nhr^c2Y{H7w7)Qq`5auF$
zh#_W7ky-ZG+k>n;w&MUF07V4=n>v^ue%D3eYrC~@yD8Soq(DirUS+m~K$o^eZafsp
zBPEqgZ4BuQj{p7uZx3i{#aJg1`IdXDzF9ghIg%2~ez04A_UQ|^c}!6-G$nl`$1_MP
zk0b|5r6@{{Nxuawh^dKNLpI97I{*eUIDs?dHWt)~zeZW@R0HUxFqXfCjjU)og$Pmt
zft;j4sSt2XiYF3t35KW6Tj{;DvYNkEs)}EVEs3hJFhD@hd)q(i#r16rk%KDes4%hK
zhzF|4D`ie|O-{t8a&U$)X@#zfjBtF5Y{5fW)^oj8&<a#t#m7>mm^=qlwGDTaMh5U4
zX-v$~WIUR2e6pmeC>@uUBE#sRwr@QJ7>aon3rK_;1N&f1?652Y=xMWrp$miJD}<cI
zXhGV%GupR)CFWnL`e-VRjXNT_*S73oacJ7G@rq8JA;u?YtQY(h9ykica;?W+KM6h1
zh?a{S(C)&l)Jky#hA-ZF$*ykTjHWBllO_cK08d#0B$5UjSBfi_GRR)HW9x5VYSvze
zO}sR5G>QOHW^R8pcwoJ44Km*<No>Qt*}dPn6ifE`z`IGAvRqt0*_J*37GyFI|C6$1
zAIvkT-<VlYcuPJpW<OG2g>l12yr=%}qKXh$sc%rfsUY?n+(^X{u$de<la=FCI?4_D
z_28**{;7I5@u2kCiI1AOJNb!1r5lHR;HlVj*Q&WY6Ve9b?%=^u-6?s@WE9$;6)^+@
zlK3E{V^4o&%YyOJX(B*L7$&KwKFR=nE~4Z?)QE7)*Fr=3>kwWiB={y-;Bach8h2J$
zPs|0qMyx9^)FKX)<*6TCf@Pksq%;I=67r3UDbAvWiUKa329iMj*0YaLjv6lTC-)4J
zcV~P($UVR9;ggx(N@j7_L+%Cn*VvI)*jwlfhTV^3`|bR`?6t#p#HruiU+|CJW1T2G
zas0Oj7!Jww{J=tEyW9;5-!61MogHyE_OqwP>g?5F*Tr`^%e~-}k#=?Qt~j#Zm_L~5
z>9z-~*A1+HmwQz_d?ahTA1K@&54+`4R`>PQlD*s;c5bXh*41H8s%?1f;?<ezHCu+f
zH;lO6o=-;k>@VG!xg$OluC1*m`U%^r6o=!D(ejbF<2?~yMcdQ8;`ui|uf<m8Q%_XP
zqmlDSWqox+IP4aJo9yAdwtP*T-MxRK)?=rx&5Rt8h}XndcWakBg{^VVMcEaudG_(*
zi~U~;W`k!xV2yl|eIzcDd~2WEKSh<D<)aT@b^+}cqe2?5(uWm4H3MxtGh$#PrNuOc
z<8QfAo!LtgJ`}Kul@;)2;0nJI#Q&2puNLq4u0dan9!+1nP`&mNWM_w$)5qe--oR|y
z6w%oMIsN4Sc$I_NA2=gg;1J7GF=^DHAP|nFQ+oe&l1Jj<bRL%ZHC)CR?#nJF2af^^
z)Ih;O%TVXDIo!MBRmz%DX}tynCuxR_+nLUaV(d;78+F4m-tn84fRA55N{l6(B*3LW
zWqmBd<SRAOj;u*(wO{+Wl3P*+mv4Y1>pn~`6a&}M!cn9rLzwUc!6N#xD9^Ddcfdsq
zUHj{){%!}*9>c~0Thj*oLc!$9^ZbPpJDdP!nj5K!NCr$3Dun(;&wk><z=xp%I)>2m
z89?RF^DWbtLH(d8$MF=J1~AM5ni7=e3%R8a3kRRyc&EH#+)Nx-J~pH9wgbmep9Z{4
zkJ4O-VMkDhy#)6Y-+2|64s8Gv4}Rs3dxSL<p^5N6dyw);{%SuCG_#nVqL_N|8$d>{
zR9q`nD1e+ML5^lBtxJRfy&A`-HZ4dmEFuFy3&;-Lig-*!!B>6LXtLQZhNW>SG7Orv
zKlp`}u~a-Y7qkmgzy{dIG-B$)Pdd-p04DE!+4%w0Bc<44@YIh!sJNJ^1TY4`pcLW}
zh)@IEDMAxLssUW31C5m-1WjtapYV2V^tOfVeOtGsEo*b3z0lVYV%6bPPH!%3Hyo#Z
zqbJh|_=G9OYE}&Ptl30%(rm(R2IE6q2QdZ--wQ~gpAUwoE~{dzlEwPAur0f>gMA$f
z1v6-0m^RzjlUbp#(JQ$@xUE>&>_I~*?yLbxA+Ek494^{hx`)xyqbM96k?rqp?k=9*
z><-1-4TjvX8k1AeAW3O!ptTpwa6mn7R$(Ner0vGm5bd0ifnzDQV~Gdx4qSObaq}Y#
zHWpXoAMl(~(6QNK-TgLyYq+nF-W=W*Ta{EXyD;*OU=tN($lgpl1?&-zr4l#+C-@M?
zybGGR52!vkB8Ri7RO|?&jiKf-AK*Yi23*y+J?s5xkjIvKr~Y=8-}mmMO_#iF4pzR5
z*~0<gw5=V>c&ju@c{F<vb`$g4mvLRbO;bH)4zj&gH-o)bye-{VaMB?osvcvQ$R-4o
zviV)6^J6bs3&rz*%{Y5D!p&lA7R^}Ub?oLIIDE@U(Y*Itmjo36gdk3@wN1fu#AMx0
zN!B|gY=%b^3Q~FE7LctLki1)ZiWmH;?lUx;HpFw{FI1$`yzQasLAHh3w&Fs%Uy?Ob
z0x{w-k^z1*)-Q#TA?f%SW8gQe!sBIl1CGBwi<5@R$HE2?S}$`MHbWzZ>Xk{}Oh%GS
z>Vz?G{7EwKT{;eaq`&R+i^6T#_2h*&$a7d+AdF@*m5qrArEU0XWHy7yf+m8<ZTznM
zlNs0Xu`S_=RTqu$ysWpIT04yE_)n|{=b>FxOlgEF!ec|>rnbB>^~WZvE9r^SMpUHl
zI6GN7**AS{L5#>M8aVW2bsQ3u(QYxYJtP=Vl7yN#2qw7`Cg*`OfsF21&-Ux)&>p%&
zL@dkcYBzkf|2VS(vW6WZtGDkoKwYN4BN?vV1(p2zkTvx`9qyA+@WD5M6LZ365K2#h
zz4oS`NzFD8J!ZT=vwrg2^)u(uGj=?F9{p5%D7=(`OtFK)GcV?_YlYcVpl#1NFk&DB
z2I-{#tgX6ZA_O?;Yyye{;n^qjsuBjcw-eMtn30}Y`M{;U5TfKX=~&j)BNa<jf2_z<
z#NZ47PVGLRgjfR96HN%X9-X~lThB_Rp7x+f#jsKLmhKTcK-nRT!I%$zMD!d{8dSFR
z!qYxS39I5w1$Cl<p~??VweK$`vWSpSofF*TekvH#kpe)CP<!nU8wIQ*CHR8$nZei3
zd@||Y?<USw-@b&@z@qU<P)8^_C4%ECD~VnQ+8~RZYqzgcBvi%bJ>=BMK-J9{A?pc|
zGYBxLwlgzCrNjS0(HVY6m}*ab;eydLV;55ZOg9GD5@L_V9e;K5moKEK<T<VwRJXLH
zaZkplnBp20w!0hi3GoOCQ?);QO@sTSFqB*T^HZd&Kk}w}6+sb`g9_LF^M!)VSV7WZ
zXx6!LMl>goB~oTbq=5RThi}p<B5xJN6%ges5;b=$pL+h&pA;~u9Yi(a<9&CE7d;rw
zwoz&n{OMtw@dmAs2_w|Cf?fO0f0g$FQH>73<`iAD)-#gLeA{45Q3kag)k|gYv<^Y^
z39#cNRZeX+rM8fr!Y?ViSaffC1VvH+&@Y26Avw(n(O4yvL$u=*4v4YPsFXVFu@^I4
zMZl8=M5ulKH_>g?><k4$im7}gaz~%dv6&ze4HlxikaHBD{HlD#2js%h)FMXaR6UK#
z5eU~l#}KECdBQQ&1zM!|i@;8*oPWkec~cisqghV87(+!&8jy`KX{6hLukan6{^M`v
zx|N~N;I2Rxe8pKSRWD2+*+`L^3es)TFChS8f{3apj-KsX&|`Zkz@SEo`mE%tbbq1T
zsej?NrUH#&^k0gQs@=0Q-8WK|6&XFc#!#mk5XBb4Zpfv0Zbo5@PA)^C+O+o2Y$nwE
zyHm@NKw@1{E<c4CV}0#98P1aNNHrQNLXvw*Cnt(3r{)460hq*<nU>G)xKK2C05`yh
z2A;fEkDDhK&;%l139gbpx-3=u;fE-OnpvA<p|t)wuGI4c?wuKZSXE&Az>Z;iyIa5M
z?K%vE5d&x`fg(i%^QMtj%~Y%(z(N}FxZJYkVg*=CFJ(wD+}WT9t*u%9RJby$RwOFM
zTX*W{w=NPqmA$CUy0J<V?3)f$AU!ibLZsbxAXQ|vO{S`ArM|q_K4N;DkeMPfKr%<u
zqizXF4KfuMya7||{qG_v$^on<c15~w{g8n?*43csWGiNzQ6+f9K%3GGI=Oe@h_rnG
zi7kSKvK}%INqn9&Yy-ucH)mATm=RFaf+z7x(T3$v`_>*71!I7WZV5MTQSjuw++NCd
zNK4GBDU6x;pP+c7^W*{{+Dw?H$Ekhh$$Dz187P{vET)d>n_A6TRqi&+INa%r1TPLe
zRv~QO5v<yG{eT%W@-ZbR1Q6PTs5byq?K^A$PqJtnr$$n`=1`)bg06ipxK+8OD+7jK
zH{U?9X}KYgqR|7}JU=3!1-Uv_l2;SZCKo|jMcSWzK!B^Dux<iWBmTIv!Vo#*N(rSh
z=*v}(REIp6HK@GD#geX0ZlCQ`fT#}TM@t|njbxfaC#7mYDwBIo0phtDTah<U{Vygx
zlH-K3Hi2XVYI1JmRQs6^C6FYeI!INVxj;-xt3V!o(Ug>mu}5<}lRl#_;?XO)DDbO{
zK1tryzVWMK@WOObBa``HH2Mq|qFtd|CEf|~<vz9|rRYli0uhZ(6<i%q73Y#k)F{Ed
zhp-1|&vQw92FjvgBH<&3(jw|271#dg?}?&}j7DuFH8h7z6n<h33BdH}Z#)h}fT0Hi
zM6eA73ps$jTs9R%d6$+gN9~7KG+J|Ab~FWIVkC-Pe^7h&&+5gKlOV>S&X^O^G;<ee
zzx+ghH#9tJ2vSVpY<1)!e)v{pQ`M2IcP-76?hLGJfAw1{V@xWh>Wg6ot2bCk*^r2i
zruh;35!(Uw78@OcM$vy_K0QVdwvdb;VXPv_<sd8|_=}Nr20qi>qIbaSVy)4Z05AK#
zo&MY-L$Rnk^?#I0ph}e~YA25N=>SfAF1k(QAN?xQuKLlXYQkm_`-Bx|YF1|{^jFJp
zj;RJ^ima8CQ5lxb&Sr+lJkc{oa*`xR?u_>p&}VOpyN}cCXd)=jxl{kTL#-=IlyS<U
zj1|$JrECOc^Cp+G94QH`Q@2x?x_RYQVv@)YH5YJ7iymX|q;h6~nY`v>i*++X?&+@Y
ze?uv(07^Q4QTCJndR>Th(G*yPEtC*R1Q<+-z3;pf)m5gHHp;Io6LlbyW;tK*70p>0
zJ?P@Kt8Rb`W#CE8bQI_+G~hPw>yM{B$@D`AoT&G-&lmsJNO&ATG7D7bFs|d63s|5=
z%4(22J{(@ay;={a^|960sF480p;TEcxCjNJxnYrdRCvBVBa^L#YCmL;U2tXKrKF6L
z#=wg*IK-xytL?z5Jc@o?fXeULYZvWG>?^QWb1|{6Xt8QZpURoob1Q?7eGiYH7_&}J
z?lfi`YPo*mPSed<C)dkH)4RH^3a8nxx;ZH0Ha_|>4%kd#o;-S84wgv*RdH_N#lKuQ
zs+*r1BvSv)hO)wJ5?0MNbL5QxPzSB{^N!LsMB|tkCOw$=ddj=ncU~CxTsiv3-8Xfq
z(30kgC*a@S&e5mEwjk8nuWlO3teQw|^REgpNY_M|m5}#-*ld8AnDfNDMx2??C%&)z
z(=$hE^6mI<2~K3UiFeI`yDC50qMA!EL#*+b%@D1*SIny%YwXP>nKo9o_RN>3eL3eB
zU^eG8(<Nv%$)?L^&d*zo*qD7fXH+I8@K1g9eG{LY%N=$3(#5QLE+reEHvN^)h*~N$
zvCdlMZ+^blsek|W_{`7ky48)XRkiKw*Z$u5k?H3~FH*OdWYX=Qg$_MI37^{QU%O1!
zn4dr3{nCJ@9B(++^7yBIkDXZO#}dX?HBJ7sO#DwR>%X<^V}DU!vwP010}b|Vy=B<0
zH6ioe-);>cfigwQ#mqd*u=h(Bo@L6($y%)qOwQpfpUfjRSHjIxY@T9MQD6$$GgY*v
zo}C9CJ1^b1W?%KI^Fp$zDjkhf=Mz!f&OQ9gZ=E}g1_Tgm4N?N|;Zw3hPHVz>Xbtm-
zHBW(;xL|9(ATz}j9-B99XQI%gcdv+M>7V-e-IGdw)(=|Ql(IW6zo=Cl%jBL1E*4|I
zC1KuMrpP!iQs&G}kW5sNbM-Dw?Xx=H-m>$DdG@BO|HF)9+x2fTpWj_%f3kZ3jo(>!
ziv4VFy1#Y$=BQ+CZX`6}ay6}W$^pdMS3gj0iLx&l&B<Nn>j`et`oKQ_Y!X3^-q__?
zUDdwddsgYDOw`Jb@)e<{Oy&BVlCsS_d`VNRWjfDoe=MuNS`%K<6l+ZpfzskunQNI;
zti9$BT2@FYWy^R>^y-#j29vd}BRTO|9ff6nM7wonzxGNIDDch8R7F331KQe)gO|*!
z=wlzhm|8`DNy^o<x#O~h)s{)=A1yg|P>m^)Cx22i<r)Y~SCrbuuT1x9hUX1?<cugs
ze>jKvfTJeXG{8<2TW1K)YjtPT)U3Bcu~s$mSI!KvS;^XTgqN&_-s%ZRt+O3kjalnd
zbn*4X$;SoGdLxW!SD;Orj=E#-B~7#0Oc9k_-f{UHMEXq7csDOoW+Bkz*O2VxtE8V-
z%;zVavSe*^EB&b^olfSavwbp~BW3(f5Tk0{<jk14B%$`*7g{4)CEN6=Tc%gj8+grt
zlfp<Hl(?&X`)9_Uoa0sQ)H_~+BhGAp$KGR?w`RtEql?G@bMDLOrd0g*e)Q}*996C}
zYi!3`TWUiH!Yx|w_iOi`iR;<lw@_E~^;=(pJS(J`H{s^OAkrYUTmNV-NoJ1QLLO^b
zRVw*$qOCQejN)g~54`Qi=1cc=>)}1d%tW8V+m~wdc;yHb47{nQtCZ<A=D20s#3f_5
zIQq*M_`ENDHedQ2TKUXTC&~a}yY872O#hZ`4r*^{ohFbzwRu=F6PzTRHD0ox3cA4i
zFIQmB`5;Q;(YMXd9ypVb4a4co=gIxi^=GG|PX%ov&rTI%4$tPMq)cfsjODiDA6r|>
zd2jj{ZJW6I2{Oja*!}b)CdNbU<HNbs%!Fv}ty0n-`-}NW>5yw~@@Z!J3LCacq|8rv
zIcLrNe9uXrpYT$+BKu>R9se?#@Y2E!97N{-=$~g6InBNmk$-ekOFgg6W<7hnR?Fbo
zb8IrkPc34~7ug`f!++fptwMqO>DR=hm_N0A(O?NV&sXJmYBY2GlBO8$N(*1l%V@I8
zJQFs<bZ5qCH50yk-Q4FD^LZcoPsoRUCcig-A4t^Nr~a<_6tl%_i5{TPBByuu&X(OY
z?<Xj8Nt~mfo|~#4P6Jv!e(?(}8_u1xQZeIP`P!pDoC)u_y=zHb*0XH244zv_W{5qH
z*bKy(^3^=WrX<S@59cX1197H&B@~-i&*!b`DVbxYhxA$JRmpw%0-smUUv}!bV)S_}
zY^L@;)w_9$O+}TNp1ooy)~d1S`Ng6$vD4J=e(IS_c^z6joxLRtt7f;<dVaPw3!0>M
zU!H441@l(hVy&5f1Y)n8j~=~zb?Ebkxqs@3$LH6I{@B)v$~L<#Yq%QQfwfk$ikxam
zXi=A&Otk)>aDR(Jix5-Tv|6Iiv52a3ojT3EkNwnqtzd>}=np^Dnw=bkhOMm2?1{Gd
zH4{@a=5$YgikjurMO2No)w_jEoz+=9Z6*0LJ1$$~&+oV>0;MH36xI34G5TSg`7IZz
z@#Utb4T;*rZ~hyCU;6nKowKRvt<$Ps+8bq^g>;`fNvmYO($Q}no;nltbdFn})cU?S
z1F$*1nz@wD+@Rg`hDG9Pn`3#V$)on=@n2h?CQ`GHXD(*5P?C7`T%xVa@8r@v*;-8g
z<};ox<|_g*`HsbGglPJGD-FSy?njm8m2|}r^GbTt?V=G;dWU%>ebR<C^Gf>5MoDi>
z@@{Z+H{QSNKUr?s!n-+rx~PuC890?O|LWnUZ;xF!o}KNvm3`aXrwGn8fBe-~&#_G5
z^zm!^UtKoNcs(xqIGx`bjU@@rsDsgW4}ao9cl735FK+sOGJ!v0)b(5;k-qkhUpy1a
zI3jyv?{fO+HANX0XY{dL)OP+r(@NC|&(7*b(Y5xU>vc+D&pDjDZ>$983T(6$v>LH<
z=8|{*>}c7hSV%JZF1Z-T(r3I;x7Nvz&28PuR6rWfMoHFqFw=P!#I)M0H_nuNZtq%S
z;MCj4XE&Um)is&?Y=sJgnPb?sUt2nJjJdoOqB)Xaxe3oEhQ5+VN^a&1%{O^DDkdT#
z=K}gimo18O@=5}Il%-X3CJ%F|0wt9A*N$95s~UW;Fp_s|YcN%EvzNODQU!kYv*tmv
zE1EaNZpG0{VRu1WqVqI?=i4dI(IipPEW3v@2%_#nr@>?O{syz`=m)Fag}l2&AFSr9
z-Vs-8v%A-1wSyV06do*o_ivD^t|+I2srp{Zk}{M-kTc7Ag0kF>2Em!l+;WB_8w)%V
z*Q<>nd(-b5ia@>_Q;x*-qZ%h<(zJY?Oez!Z{S=XHl9vtAb~hmAB=<_UJgk<5<`Vzm
uXI`3C>)d<xMlq*2&q;Djk$%FX)-?76<jV%JxhbY+sud6a?x`1B7XCl~89QeH

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/Azurian.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/Azurian.sv
deleted file mode 100644
index 1579c63b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/Azurian.sv	
+++ /dev/null
@@ -1,192 +0,0 @@
-//============================================================================
-//  Arcade: Azurian
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module Azurian(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"Azurian Att.;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian azurian(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,  btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/galaxian.vhd
deleted file mode 100644
index 5f8a3a74..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,446 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
--- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(3),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(2),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 5a4d0094..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 677a03d1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,74 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else '0'  & I_2P_SH & I_1P_SH & I_COIN1 & I_1P_LE & I_1P_RI & I_2P_LE  & I_2P_RI;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "10" & I_1P_LE & I_1P_RI & I_2P_LE & I_2P_RI & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index e924e09e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 0) = "11111010") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 0) = "11111010") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_video.vhd
deleted file mode 100644
index dbe0d0d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,433 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1K VID-Rom
-	k_rom : entity work.GALAXIAN_1K 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
-	-- 1H VID-Rom
-	h_rom : entity work.GALAXIAN_1H
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.qip b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.qip
deleted file mode 100644
index 68624e41..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.qip	
+++ /dev/null
@@ -1,4 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "13.0"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.vhd
deleted file mode 100644
index 37a2b849..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qpf
deleted file mode 100644
index fd1b9b51..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 14:59:16  November 16, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "14:59:16  November 16, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "BlackHole"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qsf
deleted file mode 100644
index 4a93cae8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.qsf	
+++ /dev/null
@@ -1,190 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 16:33:56  March 10, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		BlackHole_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/BlackHole.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name TOP_LEVEL_ENTITY BlackHole
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# -----------------------
-# start ENTITY(BlackHole)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(BlackHole)
-# ---------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.srf
deleted file mode 100644
index 063fa14d..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/BlackHole.srf	
+++ /dev/null
@@ -1,52 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Design contains 1 input pin(s) that do not drive logic" {  } {  } 0 21074 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/README.txt
deleted file mode 100644
index 4767d316..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Black Hole port to MiST by Gehstock
--- 18 December 2017
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/Release/BlackHole.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/Release/BlackHole.rbf
deleted file mode 100644
index 403b25658c89e98707c11f5a528c1e5ff73f8ac3..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 302464
zcmeFa4V)asb?DnY8j%sf_Ec}r(7P<sbTg7$3&vVm_FeN5(>>~ekyy-**u_hXgI1RF
zuww^Ak{ADOeu<}dd#qWrGFp%vNO-X%%eM02@DY5Uf4?|E3(~Wk*cS<#gnaT5=h}&1
zE-Tsh1}AoS|I;&#W|x)FqUA=u?2)#syFN~xI(4e*oKw|3FTQws_|U(^@V$RK@vr~-
zug8Dz!ViD=gCD&3;*Wmx;=ljvi$D0$kAC#R3qO3}g?}gQ|NG?W5&dtUssS~iJ(T-J
zcy$~|x1har5_dMC;L8B*VS633?~}Tccn=7GBwj*!o-YWVc1ZA_DopB2(xt4_nZ!#t
zUm7HTI}LK5;6GKE)R&}78NrjpzuGXtccx)dPm*8g5J<*g68}o!sq#yF0<&>Qyu{58
zM}hMI2~&XN5t<|vkhs~<OgVX#^dxT*o5Us0N!T7Q^$JgtGzleLAh|yP$bAV&;^jF3
zi4&0L=3VnXNl(J|wD$WXT|$XZXiD;UElAQO6k0X{Nm>$0yxdEeK$2Dgl6wgSkJNEK
zAY)rV;t~+PTmVR(PXJP;ABX^nmvng+IX)d+1xR|i1%f95A6U`?eHJJ{qUtS3lBLX7
zfbD=J2|b5e@c#ns_wCO~d=e%!tOo>VyZi|cBwfNRU;xry0f|eX8PmK99deh1(q_4r
zP~rvTUg8pvxP*?RzGQqP?M>=RLMbCMB6OKRQeM)f52d`s{V9;hz(GLb+CkzHNa7`b
za-Y;Ep~yf230+AWBt2<|;FJ3I01e;>@C1<5bE@zeAW2K=mvA#sXo1utAaqD5(GvbX
zFag+r&?aTR21xuT0ZEhRziENoCy>NR_;*12^S~_F2?);xL>`)V*{skYAY(#6;uC(z
zm`lc&@I#)3ClU(C{csDKG0nKY0-gdSX%-m+g1^0fc^2ON6d-iSa{~9ZK;lI<gr_3^
zN#A`ONXEnI#>zKakmMCS30<22sV|`^2@@J5Oz4n%3%CssltRaTKtjPSaY-F#5=z~-
z1457VyU3o@aVqF;L6R<QxCvMeNRrSg&mtc(w+Xc0H)Hzy|9cCPG^u|}8?0@C1IVo;
z$$bKU&;ohx0VMn!Abe<tcHT(*w}2#F__GU0o+Xs=D<Jepp9>`8Rzjgg`bX-MP{xOl
zB55M0QdZ<ZXi4C7a&f9YlKR_0>Jw;E)Vwxhn%6&RfjlMr5*7<>2_!sk4~75jAZhK-
z?KH@}^!r>iByl?csV|{TWb5C7ga!%a`IVr39+CTGtR!Jl->Jf+z9d~}m$oJG!Y-jf
z;u3fznj}4`KM7@xO~%4(-bmdtcM8b8%pdOuz72@1$@(jy$YcWFZ-G3^Z4#e^GRDRL
z!I#9zxNQeXYX@n2`*V|`lQaq4LPr9hZ-G1ujUuBmj-);b9|nXrxlcgiWKK$8%^V;+
zle!Z4G$8Xu@+|97Lfc&7<G`JO$fu;s`jo^;{3C$i6dsFCBJeh#V-`qU0+J*&2nZdb
z4+x#IcHGl~WF3~ZMnKY<cg^c}TQECL=n(kD7F^N>N&W4i&@Yh02^}K)F>zc(X5~47
z_HjDby*NLf2c-WK5PI6knDh4j76=`ZLC6<85-s!z@7wE3=#j8Je)fGrLo&?^UlScf
z=FbFVUKJ1>O+e!1S=Oo>fP4#n8<1zwJ0u(gga!!(h5!jAPC)1p{V}0K_$&9x*hrWm
z&oX~WDEg4hX#z6VI|0#kp9B)UTEfGpf!TBXe*+{gp(6>UzII4xOXw25e*us@39n@R
z5k3gWeFE|<d}$A7-zRb<d`LjXK%%Ef+oi6A4oQ>erj~ZW1;V3MfW*lfEc2Uy^s7uE
zmjRL{arXkEw`>3;U34|!rNoJjmW(yYC-GIFohGSUK*p<tk|v?x7ZBbE$i3)}5=uS4
z*8;i!9Y8{{#YDH4Q1ry#1mr%6ljj6P<`NJYOhD=uNa&F1PM#B<&Za}!Cv_)~&?R$*
z*vAsy(Skn%eyasZoXlm{w?KGsHy~jGk|g&+gMh3P0zz*yrWu#?o$yNTlTh?BxxW>7
zD<Emt0uq<3nU@2yo(sqr7Cl2`;B=6b6@G{uh%AZh%eo=!i-0`863Ch<kmM6QGM6Rr
zhd?r4NhtBjxRFrWBp~;f0usI%5LporIwX{_ETPO35+|WN3&_31B_MIqF9Jf3v{Cfu
z#2%M0>7OL-O~48uiI;x68IU*uS-<32<}1;o1?2u`f#y^5+CH~R-%0)LkkltMC6L5P
zDD?=)z0f3W_y!<ym4H0YhNH9K7|<ToPJ`Tw>?QR}DD?@*z06@EUoyAKTq7Xk{%-+^
zOF*7q34}-OAY)d>W&%>*T<}9c#$J1x=n?{R#Yz0rEs*>9Ks&z0`$Y~ca$u1IXUYMY
z|71R$k-s*>-8>^{jt6sA+#~nJ+Fe_0&~`u1+sE&`V4fvToqhT})me$&44?6=#M3`c
z|8U0Ke)`O>l=`vU(pSoI#_2C_<rx=!dB%k&%)&n`T(6ie*K8~*HLfL%lmxsKcfLkc
zHeE{@S}Z`GBju!Up^>I=Bb&mM3W}Pe-T$#vTqG$Uhk;f|QJ(v3l-59!6|6I0=O(fw
zP_Xqj612w$Q<kA=8wJ5zN>@$VRHo&iH1M^aQClAf_5>O^%26@BM-jVHP!(-1<+N6l
z44Uh7>7Mybr?}tI3}dr>X`pr4y0&Ks#KtEYE2B#s-Dr%iO!cHRZ?I_Zp^kF;f%h*1
z30W!xT1iR8%|TYswVE{LC6FeG5DSY6qq^`+({`5RDuo+`G=)ctHM043E%nTQ{Ygn$
z5I8$IYiom0GhLcJG|z&@g%{ehAf~<OxkK3Nhy4th1g1a!C&}&EhiBiHZGCX-cV3%u
z8BYgi)7I(F?K_*|Gs~Vm%TD4uyV>U?p7?H&uvrXw#mCtkYhO5DvGD8+_t#~;TNrpv
z<>H)b<><mNO!M@&{`PCBW1j_?v!(1TP-(BJV4Njkh0NI?XfJC%{>SIFKcCe-EIW58
zo1cw(IzFg>{shSdl>e+<3R7CKBntHUOn<XijGC?~2WtiUV|7|v6CI3VZ1XOlJ@V}Z
z>*oa*=Y{L&|MXj@WA^;g&hZHV$<Sgm7P-(`VxgU7<n$l?tMG`W#zPjHwp>dR&o=Ur
z-+PlR8m|TFjyD-^S$|Qn$3C|9Vc&7&ddXwat?t9V{aF2D?&tExO)u1)5820V|MKB|
z26^9mS<kcn3m=y<vqEQibZg%^Tii(r?N0v-A1`fm9;Jo*i_M3Jw#CeypM0Mx_tOua
zf2yQ;$1{sB++2C|{*&g^yeXMg;9OpjXOa4<A3c5gLzAz%^sIslhD^nXk8b?mTJ7_i
zl6wDNE^I3o)$UnRdHToK!ywnRh0;@EFYiaDPS4W$q(az239P2EDmCU)`RVdzkNtrt
z!waTdpHds2{?$*Oj*j`HW%UPcSXd2yq59_aWy8M~3M{%YqHvbF`<%s5=*762Gwm!R
z*Bmd1rX4HP7Zn{*!Pl)7)$}5B?M*Li-|``Qs(!P(FK@i%E9l#zo1=U;)$7@z^IWWr
zpR2{4qtHG>-)=oz^e+o%xlUjFd-ItNPM?>VcR?mgPt+Lo;%65|?~XOUkHjZEPfz}t
zrY_XVC-wa}=?c;<Ug}J_G$Y@2cfVoA^VvMS)+`fwdHJ^anNU3aZRbp~omn2FY~hCa
z>&QWMX54+HTnjB^3#IkM8tE$$f5z#wa^Ym`oLov`R{W@o;FQ|(g6ZS04`;VI{oGg2
zSioK}<2k;To~5!nXYn6PZ@0Jiu|>Um0rl?Irsb>CGhQ~T?!5B61yQ^Oam!2bvN~Q>
z#EfOM_^MExEHwQ;swW@L_HMx@9?^=gd~!keF3z@XC(AEbD?vG<FHctS>h8{E!WK*=
zdR;A*uTBnTms)5cTQI%bJN`F6KbzQB|BU#byOb^TQnFwQ_9<2P1$1~X+{Omdp|qc`
zYYWxUiw^IzJ;w2xI=p2vc#XXDi|0&aqheuTp<Ny|_Bj>?nrHGB2G@e^&I&mTy(TYE
z6Bh}aKO@iSu3V^vQoHRBe@qV7&%XmtmN=)o@+6sOd3P?`i3=vL3wp{#Tl97>;Lh3W
z%7mZOU4533udTP6+2t(ho3pri|L2!1D%}gGbep$!E;~18%h%4^eU=N~q6R;22A<2h
z!n_-EssanG_ANTQPsQoE<IiOwTd*m1(b+wB=btY2$MJOcf;zinKhc7T;OohTe~sM6
zNb8*1?O8@H9`0U%qvfyP!`<;58v7_tH=E8Q?LTHkK7)zwws*X79?dv?)`eF4PG8$R
zQWpuE2eaa=iyT|z*jya=kD15jqGVRwIZoJXd%Pt6TI2oSU6@yqgt6!9@b~nOOwQ`~
zvv@qmW#%kZ;5m!`SbDlenO}UL@+<^>R?)fS{uJk)PoY7IY$b62;KKRf)vdXcUxk?a
zHNI2(0^5m#INsTx{_=YhD$hQgi)*hI>$y6=p0gAG>xZyY%lABm?RB*)JWt-7BKtxQ
z%Tvsrr>Olj(Tl$B(=g{0NsGR25$A;x!Nr5!XM1q^H9goZtHzuP|5-+wS6r}o#$@3>
zAlN>S`=^+<&OCa0_ixvJOip%te2DYa!uE6O>+mOAvC!JWNz7+?w@BE08Mu%fGmqvM
zPj=6*1I|^`+B^QKbJX1^hZX0?<J06`Na@cWzhR21PWcw(f;qy^=?|HlhS~E<TJ(3H
zrT+S3>F-`V*<ISmXS?S$QcjooT%RmYNBca|&ec_P@s#*HI<c8`u`B1vvPGqPo(x;~
zQ?>IZ;1mTGmF`n8=G4)#(jA@RtKFfOnOhytW?p5HTkkw~&kQcu_L=s2`5Y-i@N(BS
zGBbxid7fEsw)J_Ic-bNIQ_}(Rk1qs~b5=Qh^LIA;|IClzTyAamKSH?bqt-Xy@v#5?
zu^sV`=ZuW)h<`mN|J1Pje9lPt1^JLSLHzqUQ!jk7_4_#zUT)pl{6U>nFIe#}==>NW
zDQ%SRl0VOn>NHzZ+IS-RtA!hC=lEAyPd)L@D`iosn-{ytyvVWtXpSw^_VME9PUhQ_
zi^BhEIJRK&y5OHXd6l|0{?C{F$mJ_&^o#2Gd?n{xUT0oY4f-`jzNnr*?EkMZ6#k>s
z^SMuGpMLZ`@aatB^f~5{`oHiM&G~%={ps76%%d5n&$^J?vx{2A>3Kaz>bbl)ESw4c
zdhvG6(ZR1SYN1Evf@-d>u1Ry0qLm9LW9PJ+XHh?wwPC?J`}Ono$!n@Zzoy7vI|bc*
zems@`=DQyDpBvp4JI=R^#(wm5?|7;b{|x3kaGdiym?Pni_=hm_PyJ{4{rUV;SH!=B
zIq^I{G#`7M37;E1-t?Pq8Erb!e+-e}IPZDZf8mp*jm_5ZeBFUJEZCIaeyn_sNqnAB
zOalw1p}!73U0C2<*jxW`=5On;sr2gM{`$<LoePTW)suDZeih*L^K$6f^xllJ3$4A*
zKz=q4i-gUWdrgkL{G9B9s1C=gzcOEXPM!Z;wxmx@^*mF~MFBSAHr#q>={(yqXZ8g}
z7T0iEmW6W?aq7tF|8nW66X%<94oa-38!W|F-8A2}%$0vZku@tg2U+$KVT;!7TtaZ_
zxO2HL&t2o`+@)+m%{p(PkCmdr%)Qlp{C|Gu)G|8Xl!cb*h3f6s&j%I|oU=b$I`^^7
zobj3>-z)=Y&YI6w{q~Okw!3)ZwCw=xYrLi1`f2NVP9E`h7UwAQ^Z!^wrf0+ac8rtK
z+2cFv$^F@fbI*3gGeyid)Y@SBp=;Wnc-=sr7!HYpN(RA6Xxa%UpJ&`j*4l}0{??4h
z=0ia@czd`O>NQ*Nofgfk;?o~}&y1KBVc^p&u*LLof9CMWpPx57vlY)>*-TBBSD7I%
z#`+SKFWt;8*L<FCTr_urpoz(y4}H@o=IBX5kZl*om_VuZl~7;#FYU!*I+L!YXia~m
z@^OimF4J%S)0ggBH*~Gs#du&`+`qH)obvhU@4cZgo4y!bO@GCfy$q?RKmPxuX2lkS
z9-&QSPuGlB=*n58r-!~fBgTkX7mJ?6gK&QE^zYAZYzsxwCG*1g{5O7buIdw9bETa+
z?k~PKBaLxTpmnbfm!>`c)3d*?lQ3Se&TIUW-MnGuyGc!4U=s4?P2%*SyIwAHHKfDh
ze<9Q@OQWCXh1NU%YX>0ZBp8B$Kl&4F%^<!%ndO!4roVFa%mv6YKq;kYcoSZ_X+57d
zP}e>2M(<_neW5ox7<GmEPOHn$SY0xw?p4a^-rK8L%Z<{`O`5ho)1P7T!Sy)jcOG8h
z;OgTy{lpBiqy^9|fziAv>{T;zyu!n$J7#XnXc|<<s9NZn$X@}=$>iyG9hv<>wSo>4
zG~tF^TK5v1IhfNIePU+rn9AltQxmC>i_~z&F#Y@$GxJL6S*)B7KJCR7GiM_sMo2Te
z_$%mgZU38D`Dve4{9$Ugr`qV6ifFYJNq1Ss9;KOGOSs=zl3I~44dIMuRMQ3b>a?aE
z6dbehyp(l1dU|$=g5J*(e(EBmX=jT4qa$+}2FwaV5O9Wg=B&~?UaBt|2J<%zS~H+%
zeaZi3XPnX1{MpCPDBl@nLI-cOXOw<!t!tJQYZ>!fLbAu-e0e**cqGW;7B6vzRS^8~
z>^~#dX&yd3Jg0U5j(BNfm75P7q_u@i!_{WA`cxQvjelM`+xG7&26V}<WQ*xSx?u8<
zwbNPM%%+1E|Nf1ht42z1sc4;cX-m|<%)HD=UuR9Z+Uj+YIeynBt>4PLRUO)|McHRd
zFBlbLr*eu{9ogkgIi=}HO{8{~)>kIo)k_aX;k4oRpAWugOHYla7a-pQhSY03Bj_Ia
z-jY>%&iZKhu(4J3+&)=3GWu?-r?LK7|MtMxVr@uS*M-0IiA{s<cw|q0;<M&AjYCmk
zs?V`jln(eS$NVF1@gnoSFS-6y@w%egV)?b>`CG<5T3q@&AGhyn)YqBa-|{o|rS_^X
zS;y_DvMXFY;uJ58x+{a`WqZwMx{O2a_=E3&Cp$|=8;|blQTLRVN1-{<VL##DGS<E1
z|L}_&*Z=Nal}n4ibYbv}b$zhPx~H_SymWPXhuiZ(|JdqpRqt^(hs*7Q(dBOG`B~>1
zPSu%b65qbt6Uj_&X`zhPmO-U4CM>OB>xN-8%@|8EMFl;IA73WeiIhq>{k#9Jg)9$N
z21-IS5j2j1o^6O`A8H5VArcznp-!d}=maCeEhAD^*_NEosv;gwY`GkXr}Ne&YgICl
z7^)FNxTYGus|$Ke2g4e-^$7y26jDvd@@QqDf>z`+niPq-B$b@3sL(R53i{LkBp<$!
z7Dv*QFcfvlh$4gKkOhUygkTu6X+w-_G}gb#3I{3KY6Exe0CP3Xp^3NtC)os~-PDjk
z%vXsdPux5jQg9PGPZF8rpBY-yAG(kj@MSZC2}-nrZ#5t$uEWxz5H0y+eO^VXjw_mp
zsr3Y_3fN{>Ub!U61WGRhBlzdWDjU3MLEL64q&E4R)&7JT7@n=$r~h_IOx8;X)`+4^
zVk87YD4gOcZgdl2Qj>%;V-gForay~X7`HuUB|;ZzSyu@Qq(rUB%FSR8U)Db@2SR%-
zLMjA!`p^FycVYa;wfP@PV~&dXp=BGOhH`05s~5Rz7pz3aT9h{zhdaNWZe>TfXg5?f
zSC5)5jtyeOZWWNq1>~{C!Dd8UN3EGD5xnX5J}*7iWF*<3Xw3FS%>r5s4`VD%S`&oH
zkVr5S8Vsc7V?n>}H=8D%m+>;$cx1!T5UjO$(7>sPHJ*lsaS5?JX2J~oFD+&-UV3uT
zgAH_!w5dtvnCP8NBn57zzIK!?E3G|B?kO?-2Olpa11n_kYE6-eRrt7ud}cz(BOx}E
zT3nH$v!EFx<CgY#$B%qi(v$3RU*qEn5C^+s*%qtxWPg#8a98q5?paY3{aB>4dl7;m
zVoV|kUd76c+qT_nSxjlVHl`S=#!jAm$d*Z3vyhb#v1^hdJumgd0heY?achM(5qyST
z!9V`xFKCQkS}h>6zUNL_Rvz)CxRq_FhHZy>K`~DnTHaNekcwoqfTD>`uFdK|EYYz*
zO2zSg^M<~E{K-@!u7ifvhZ|ZHQlHo+VxH*{#srzVp2fvutBf>BYzhGp+fzZ)%F{G4
z>pG4fI3lfwFItpyOUD|U8e0AKN@jI1+$cO4>HTh~uaSmpS|L>S7BybVbUka^=}W8Q
zRQYF}VSnR6OJ&CQs>nN_3N*!PGovwbY7g$x`y0?KSulK{xTfq!Ro9Z5;KAVOigV~%
zUB0j}{o$Cg(tnwOMqSzw$?PEA(iEd?B?AlUnJ#5zj4&)npglttSYgX3GBg+yhg{%D
zdwiF^M<q;}{*?p5BL-q?60ggEq@E_!GptnPt~U0lC@T0Bc?RQh5t6xUqGE&Uo7GZH
ztET&pq+}p5<5Q6|X`s=ngP>+t=~$@<((;vzwcLto&xWyA0*;acmNu<%n$^0Kjuzzb
zvMCMm6ZHb-(feahK`7OT)U*O|7}Q!;BAg84rfE?q^G`gng;F}6Ad)~@DiBL8wa20-
zBZq!^@EARVJhF^83)U+cbd_g9B}*>}BCCjwltI8)_hn6<j;Ab0Pq@@_hJgH}L!;F=
z_{dy1efM91PKH^Qw!{KKKN;hGW~XQox1qZ<*-GV7mk5n<hseiq%Zl0hfF&gCQB7JT
z&s={m%Ya*;*(tGK?63bXFP6uHjODsj30c&4mf)<h!`d;?9Gu!1J-Nf8`iW}8bhk6;
zjru($sI%%vCibWhn*5A#pay2c+uKW>+Uos^;Ghg<<V^YzI&FQXmw;K(K<<R@_k1tb
z2x)s1nJ%+(mMStWrvW`7%ZC?sWD2$)*X<pd5cbJGdjA#dcgyHc6sIfy?!5R+y`onu
zVF?{>XGsfd_EZEKYL`|p?NmZXWne`?Kk2uiD_`y=Xp0miJj&nY#YKm}89D^wAqC5%
zgKNxlwO)~bne}B}WUay0X#dBAZJ+iZgK$Ox5i&3dJaQ?s)B*uEQVr>mb+RHh45~zg
z2_P|+s~g!$!)Jx8`He7?b-GREL2Ox1la+QBIW@bvvr(92V5=*86IVG)b6ZZ9HD)Wr
zb7jT>SQrT<3%lzgfG-0CIR;ZRj{etlbAgB6<~mWSxS>L^Xi+X0Fq)`B#)N3F&9XAs
zP60LBj@KwUN7o+ztMe!*0M!%`x<qLJT_`onL~DdQ;X$l%2+yPyAv}^Q(H2A_p#XLv
zcpTCMCX^mq9h!URKVQ(~pC|;Z@gQPK22cv)5!@VwaYYghB4H8ZH-3`Jh++2R3drIX
z2h*RJ(8hIXBy?vpo0)}JJE7SU{L}&~3^1Vth43C4Fm}XzB|`++D1s`4NVEaE5v(0;
zwZzFOsq*OysTQm#pK^^n%R;%u9uYY~j6{^gnvNF{Muc!yK$<A4jbUneUsthGRnV2E
zn`Eew$E*qGgwHko&JVLMD(IV?27Z}fh3ZHMmsrUgx4gxNI5VvTm1TOdXw?LLE0ZJ(
z?t*<{>wk;yVMSa+^MNZ!p*-$io(fH}B?L*0r&d5(++9@ewP@h^=!)j|WaFNSBJzT)
z9lv0ZKOoK{H#NO&16+#4P=Ltz{>A-EnlwULvkdKnps<zkl!52#{MXE^=+to7(><l<
zB}7UoHT~|pW5E^*Bf3tef>x^pr#zej3Nb&S8u@Dx9Ao6+k;i^Q)O;z}Mj&*zA}QKr
zTnn{m7ftXODT=|;jNz^$Y{giNBujhx8-i7O9m+&*+x{bk1wGmvQcE(@TUe9B6x2)q
zWZ73zT5U=pe*pKf_=p4*^pE{!@-g6e$TtzZ#04RIE<jL)$)3+uq)epFn^Fh)XEcq5
z!to#8@lt2EP{cJfyWyo8UXI;jPa=*5Z%x<odW&1|L;Ln`kOC8${UjlF2W=#uNbBja
zwuT`YMLvL7l7;vcFTO#ZW2{_G3tn6_&Vs$Kw7Ba`Gv+eW9K_O}ak9DM8r(r`OpRlO
zB{gMPEH&c<Giyt_jht{m`sZNMb}DGL5=Y!W{b9Uh$tn>4=Y~;N!OV=JgE)g?x5b2x
z(P<rweGkH&1k4sj;tZp+SDBktr>}Q2K&Dg&lOWDuPw(zk`6-pxyTd6J56GJBAOE{Y
zL=ah~Xp<~fG)3gkbA2pZymAvvPfWsG?6&%-H>r}A+mp%^1%YdRQh8M8v(sA$W5ob-
z6u`NM2!+Q#xa+0v3=`son;{M`(d;*eA#EtMRn=-4nITu{2KAa9x;Kdt1PvC?@`uvO
z#g3I}u{hs%BL!rrW$jX!()Mphv5e}O>0M~ak%hS>Ce0qk4^GJ4?xSjl8}3oX658j?
zEm^Z!{-qQ*^nG<e<%X4(tEyU6U8uSgRg~0TwcNPSRG0de%I#IxSh=aXXwr8m)N%Cf
ze}6V<uJ9Xyyn_K-m&NMN5RD#M#`MC2R-E@_&SXl8V@wl*wcH3xjhL5N*+f)1-9m|w
z&LEN4H)F^o5Z4pFR1L;&29p5OLB@mNN}x?d3st4|z)O-;T#LUK>y&B+l-U(3d4kEL
zPCxZ8NpU9Fdd3siL7i>xCU3<8!H&XEk<IU!)txLS?aL|AE2KX#&ZI@5PLzxjG1ko6
z{s&f2yg>4dbc%@9;u#S15tdj@Ot3ijOP98$c~zPtRrs`^JJhuShPS8%RF&P^GS>?F
z(fgMP@~p@p|6!0YuRzbV%t^#UoU}8CHq<9TN5UpkhB&nks8~KkMx;q*ESbXc>EoTW
zrjC_|%*$#O+ncaXq+pL~Ub|H0&X88c{S_Nz(mp!(CCJUVr-4<Ov}mLBnwCT1$mv<+
zGdAG6^y#Y}7Q-^q#%U1Ny6IxwdYRQ}Sa@eRg;^+)!Tt_)9&OOSVmHEroh9k&ll#Y6
z-D5Bj4I%MvaJ~X(;byLvQR&k1oh8G{>IWm7G;~f)e_-VsqL85rVWiLAdKT5nbn(Z{
z-jaroZMmryzGIR|w5N+9=rgTgMPiraMH(LYhc^m~m`~dYB!;>HPfW|%b<D_W8CgA&
zsYO{HN^{&6^PT8s`oTIZkowK*Zd$hZiuTDj&gXtb8+(f-OVryq2)T{_<*mv+78iDw
z!igD1W!ytEFR_0Xp(!9XEhsdtOff*^)<3@f&yplf8$EgZs_v$L{diJNlyL-!S(D27
z8x!TUjgB~9GTn$tfab#nfNprY)+yv#+Rk3?^R_&ol4ZB8)0<)_lUFRr%wD3E*Yw!B
zX+uurEU1A6Y)xQD$TMJRkMy5(#*2Ki4Z&>NhO4P+#JQzX0a9rZGiz2ZXpAvFv;>BN
z;1w6_r@uvWBy+4f#o7sFXs}7Zdg-T=Wa<Naxscja7zstQsHG%A>t;`Kvod2}o>NF^
zuI7I1#S6qqZ7S3lAqx$s&oU=5+o?3R8dW^k$5x9b6vsS?&CsS#P--*K{<SqKt~_2S
zq_ot^4;Wux6O-M{#`rM>5IePlxtob9R&9)f)C~=>xgH~HGPQupA~sxJP{l0TtS}g9
zp){qFR829pabHVO(_8=KjZAQ2e#&AxF34+BXl8Pnpy}cmXNMEi1>vVvOH)t)O0$8g
zhRyYjq`S15qBWfmFFhc0HdQ#G?r1mPAn&z%C(WZ89U(LVaX)g6vr9x10+#M3YLLVo
z<it7JB<qhJ6ZHe2Q^R=njEoSh%}9w&#7L(37(`EM-gTx5(j|r1M2MqeS<*C@x!7<X
z+5QG{CIrA6ipdj&%vP;D2{ARj5Vx3HY6NPnM=3(~1Zt`2Kl!%Vtupy>A0;;Qr_kwQ
zy;g;ts#1kxTHO~|hN#6F50(HX3>V$(PKb#+j;vCVLXOc#ne093a%Esaq3pAIX7z%T
z(rQNP`N|vF&xJn-ea#ogbyQQCF@0CW%pee3ZU`{4(MGI@jiiDf<6kTiFMe)bC8dyJ
z0egBht%*f}T_^)lWqmYY73W2}krL7uj2rSp6ZuR5R(3#TZQ>ZT;&h-o`C~UyWH+m?
z!BC@Nv?GORrdFjMdFVQ^=tTX8B5lCJat;~r&1p^!2$0W;N53F%0wYTk;|DsVt~fG&
zPUHYg@X<)!d{LV5BDhgPDYF@##v@;2<6f)3B)CRgK=P5xqp%R9da)~c-l?DoEh4Um
z45S&T4<xyLu3=|S^!=*0ti|Oznt)-_2y6`|3Uk2PtXQ$dDuRKsev9cXHE2c+_O}4l
zp%zNB8T^paWLXWXg`BjnAfoqx^(INgcgScBsXmO1XfndHq%yT?m__%E#hG@gWz0X&
zM~Ae`w`QZIHmTc`X2#GOcD0ntqqF^Mg>mMCFgp29J1IWGXfc8dO|r8p23-{hr7787
zZip4LKeqYlNY9@_=k#=Cnt5g@vt_$$j#C&t@#QB^k_9^wVWjVwdJDR6Q9$|tE=a(+
zj5yA0E@c#tdtWGu$23cwxXiBEZ+=qM_3d<AT|H&l$1K%nS(B5YX>@N>_o#c1h5nJw
zUAuDku%{)x9(o&=VO(0FrFPMK3}iO&7;*}(f?K$0;+*vrkN9{D6DiL7^bZ}{jRh<6
zpU2ZtP?L0b_lUyG>>MFkMn!Fjax~Yy)OMcFFR?%h+GWaMSX+^qeW!J?W!*P2nJ0SO
zulTNi3%<^pKh>#u4W!B3p+byFMvrtGEw#kmf$=P?P|P1Z*Ql1o0D8#Ot#@PHVn*k6
zL@ZQOVpSklG7duBWgpNPeZS+ZI`NiA_JpXDW4`jO%B0F$87rzQeS28%47XXs_r&s=
zRheD!jSTsEr?|D~mRJ!zc@+lnzh&x*xf`cp1w&&2u3;F<U;OOC3}?W($iDRx87sHJ
zKcLLKI%283KO8#wNjJCb=z(n;hA~tJFtv`~XDQh@_4L@t<I({qn!Bs@O8Bh3&G#ou
zT}rpE={)L_(Nwa<icMwak)SZ%WL>XwocSv9X*scc&5P>>W*3%kbuwq$m?9STfuWrI
zUfZ*$j1KcbBSMa^=~Vr=HOBX;$Z;>LI+vWd^F3P5SJ)>k-{R}tT~+L~b?RYm1Dim;
zt$TZwh5?E_XJMph#=t$w5W|#FLNx|zSQbN^hEe5%%4V=(83{31VOk9{7HW9VP3RKa
zT|-Lnn3%bk>&#s=z`)Wf>{Izt>dt?DBbr8r{|XB;Yx#QJs<PZzwr??UlXoDtkumJR
zLM?F|LWIsk3Jwve3A=MelN7y4D^ZL!iLWuKu=Jy_FhSWgLX1@p8(V15x<>5c(VNe|
zjZDLhoUBe^JhzxyxC?VR=Z8W7Jwawhuk7Gf?<E1p0Q~8~M4~$tH-eRtj9$3VdIldP
zGL4dCv2tXYA0fe{12E?xLCV&I5!yjxr8@D;Kh&skxWUD;(006G3#Q!&H#)IgCo$Rw
z#PEzlv@2FeYhav#E|$GTHT+?b!a8V`){`Q$u}}t9<}FxBVOB0#cjzZ39x^~0GpU0)
z?Mz?3r9keGMLGhpR8b#B6X--P;CmDz1F%5^r%MkD;)7R$G!}~iqyz5|HA+{AN+41L
zc9<<I2`MtgZH}`mMv{*x#e8hq&wk2&>+TC=(|1^@NTx(F6>~SzRK<?zZnl2!P?0H?
zJ{EjzxO05qm>AMsDwe$*Qb~u91D}I5o4WzI2vhK@NKWY`VY;BvU@j!)WK^1#AVK+L
zXFY^8iAL7wcN!Rb2k4~Bbo>6_!C7~k#csak*>F$H@%m(Gr&Wj9e^cQ!!>}AOFoo8f
zn#42H)oa1GCBo--?w2V*@24q*eg<xV20_FTAYy#fU<cW(O+|<%Cq+p>oE|`|DW6kR
z_ZDA_HYslu_Vq^m87rOVu6YxRQiy0~Gh)!^D^D@<hcWvvM(Jz1Qz(VaUKgvLsHu95
zbxO1!rrN~XN4D8ArVqV}3PntPW)<-S;5R7hv{$fk%8z<JHvXnhkx3>*-RvY+pUj<;
zCBy;Z=xk8L)1*|2rZBmlYH(LDp~fkqr=Cnv+D+(2W^F_Up6mc>W*?3M!+dAjKtTH~
zTm^2ApK*Kim5<t2-ni%=X!|1F-2Q=4dMbu2JDli2#`s9ce=C2F#St7k?6vT5hlV`o
z8zkApHUF{HwcWpLS2;$?42BT#*AC{#cH^^;!Ap7Kj1=%h=@W=G8@Y+giR{gS+4!^v
z{(5PHL#zm7)1Z%{0v>W#xjKTRnNf3hGRBP1053IKv~46&b|L}1ZK5d>#8t>-6yF)0
zC%*i7NsvsaO3{AI0G2~EUVN9CiK-jZEQR8mM$?9p;tX2BA6rue^h4oCtAVlB8|$ZU
z{q6+?nIX`-F+9lNSq8hPY)1OB#3Wub#JvfEKxl~(v7^w67F;dTCB`*evbdlA6I}o7
z$nFwOMq#KGI6H-YZfYv(aF~6woa7>V7=;Y<nr?`-(WBCa6@;G8eh1DH%%Z{)aLb(0
zTmfPNaJSej=?rvD>+{zZdW+M)ax-Q|P1YGvpxE<g?uQEO7WQvdBV@9VH%r3MT4Q+@
zRuO19)+^_^)^HLAkS>VTTn7GHM!0DeQiY~)pm-|D%_e$h+L$y#Bh0x~SR{uFXuyQJ
z1&uu<oq5sZ1fDU*#0uYWI{=wA7}bWXYF(*9sCJ?GX4Xh2;wW;c)zjsF!3Z6uB&HG^
zB*N!fFKWK7_2A;nra$((oH>ZbG4-gYmrbB-g;_hi!&muxI<4?N+dc-9?J3Lf(i+l}
ze+q5XDA+WhmIhheU=2B7M?BQm>ouJYWHBV&@D89ZNzSZXv~JP-92YAf)W<%<OIBk<
z-iJ74@zF$(UC^~j`XB@sm@O^f>^^~r29;4&eAjX$&}s&VBWY3@Aon#~BH`$03Uj2U
zPyf?f;v%u%M-D2>4iqOHw9UR2Fj6XXrM9c47e?Y<ZTd_g0>R`g2TBOolt~0)k<Um|
zAb{?K)YwvipV<Tc^w15kT0~Bm5t^J5SbC7<8`ZPsbJ7B~$*BbdSg4asG0~E_rspGF
z`iNI4V)`Xp+(=9gftv1W?|N%N#SSttSB$*!)i$e_vFxc4rFN<O2!|GZzZc^S?Zjfp
zc@^LHZ){r3B79AtI+hk}JDMOhBGgzGC4@pA#i%u7tFNZ7Os%~A#03S}t=J4ta2XuI
zZPjbVdv>5fM$m&Z+9XMW4Ru1Us8llg<nOD}e}$Nl!mrL0Ih4kN${>x4aH;9$^tY}R
z!7*9G;Wg$jdj`Tul&Xw(4-$#zf{|CF7qTd?dQ{LmvDzRP>psR6W~-qmmL?g97Kqu`
zx-%S&SrqxWjn1EhWMMjHSwW{q$s<Lw3}V{Ba*OcC<z%!*;H1-t5Dp6A(gLRt-+%@+
zMZ8!wW~iEu3+(2<koVF#d|+xEDFv^E)t0w?T^kR%NJO?d_mM3M<38sGd5IfMEmDIt
zf|kZRornttqxf1nbeWH9dkxKA@lbgL6PNKz9hj3Nlbcm&;s}X6RUsmZryROoq&Iwt
z8O`a33JUE0i!s`465AGHR5E(tGX#LLpm>ynEvd)H;{%wGNY6Akz#vs;&>$~)sh=&M
zkd7b%i0PNkGf<J`YztB$vH}C?L8&5PI8j1?HvPdT=&aZ`jLe4mK{~vE$_3-382qLy
z>oJexPF0<Fpzv(M5@bxNNlh`ei)6$r4}v9Cz(%Ug+ObPR)9i!xTYvpcv@917(71~P
zcPN4wZ}cI1zNBG=$yHFmM=N5MK;+_aL3}KQ81Yb!3l^17YKh0FJKZ&v^{Zi>A*bzP
z3qm)>*g{putSJj0f-#}12{qMeZCAT6@axL<w^<BVY}^pGGfd6xs*Y`~@*6V3M@xyM
zW2GUb+05Pcl*&&jgHay0QUo7uFsr*{g<Q$SJYzd4NVDA4`l|1J;^TX)ye={kMw6ym
zV@*t2ll9)tP=)zPYr<DmOBo#_N+t|rz%oN-tYwJd<X9D<ucOn#5HmZ%IK$mDj8<xn
zRas}Vy_V5UgK(Y1e5Qj7qak$FI#{x6DSU+8j8$3ryG9|)u-2~HXRkal`Ze)WM2L#G
zDR2(uhw-7bE)8YXE3xsSnx2Z->41wKPsRXz7Dv8Z`Om^6K@@6n*_OAWna0&2qUKNb
z%K2b)X`TwY7^iBl?BW?(&xl(2Q16M`57(-bDvWZRSe}r5=Se3YZn{_7VO+S&ywsPI
zuU)+pCP&7_c!Wbtnigiga+a$J11l%*m=79DvGli1WNtb@r;OQE98(-%veZRtd$`-(
zLdIoAu_M3@0gm;Vi|Zf?2PRDia|@?{`L5oq{hSI*KHiE8%^Z%6!h^fivFZT_H=!Qw
zah4k^M^A*$;<CaV8))pnz-27R(P1oPcG%fa9YzREtTe1&F@JH?iG^C7G^KqQZ_2t8
zLmOMGN(M6*J{wl?A!$llXwmJA5$tfWsu>FA9tTIOrB-zCT5q_Cu4OEVExq?`NZFoC
ziuNTZY$hZO+<^whAwwJjP(t+B=#xVgSb5mF79untrX=SNWSf{+B^&4(d&uY;{4JNN
z)v*TK`1)?9cV9<{TQ;YrR8LAw)@dl%g9TfFXxczK*lq4f5vTQ(I#M5dHeDDNN#MA4
z4zF`#_p;lp;d^NcS<z#m1f$W$2jp#IuHeW(u5&LQqCLt}^gDJZA<eh_VO#;`a=MLE
z3*l~9#rQI)QrJR@*^^?J#il<#A-OYQc5bgDl;B@ja`V-1g0c{AfdwV9@19$>hS_qU
zQBVw>a8i0eN56thjCDC#&NQ~WB8GQPr-y_=SmVA9U&J{wN#XJ8IQ|a!fCP*G0tVrB
za$++b+Uc++Uo^Z-$`5g&py4igz<FZ7818tj8~8-B(1I68Ne>C1m`s^B4dq$Gj48JM
z@c{5$V>7;!R#TrhOl`DB*ioq7%RP;TDwcFsrXHyX9>N*Mm&}PcIUJayAw4}O{(56g
zSVVQ%m=S0r!y#)~P7ilyjy6Eobo%T-Fmc6JGMx{isXt&ToD+5akkJP%T|~D=8)f7o
z9EeU-3#*;*Ax4EWjyXE3BPIwAjfD!s5|Lq1X%d41v(~wE<v|WLS`{4+1gCSuCmJ&A
zSw}mH6h8V?1%)=+qu_b2S0pkX6^3+2*Jo5#=)8v`?fB{TDsegB|H2P5pbUs2&qeV$
z3bSiV7#2d@k`SQFDF)UJ8Avr-7aN~RNAY5avJTc`!Xn&>j{E%g-xN(EQ)mh3ie0H)
zXalR$A;g6LHwG$GuABiu+h!l7B*x0gm+9j+dN_N-l!=dmdg+At@Ps7?>k@|sQ=hmG
z<d6h?E*mBGr@xx{6q*%^5)*JG+`?`H<=0zAsJtWMoQNGxGRq3#gmv*-w9;e-&f@bx
zy?`W~bJ{!8$cvm?XwJ^!N@H#ie^B!XeI0qkMVC#zczE%n^JnO>h>z>Yp$7aGxA6L{
zWsEbJ&H!rYR)r9ei$U}gZd_;j_qM(i)4Z8+CEqOY+n+%ysvMY;eAD?~-xH!0HKU{O
zpfxdql}d)tyCqyByVB&vtH#V=iG#&pp2O~`VNOd+#2l%i6`%&#Au58~)WK>gM2U(h
zYZPS2Kz<GLO>?x)C*G`!9UV%GI1)R?>8KDK+U9U`=m}jIVKzDv7P!;}uq>gkirQO4
zYwq@0fROr-P47}8B{q8tC`bX+H@D!Q`25-e3Lpb6J}^+@)gRi(`4XXsxdmH;A!LM6
zY%(+(L}fe0?3UpbY6X^(gSMEf0?bafUU29K+5-n=JD;DPav%An^H7|fP>wWk3AAh<
z_63`b;l-9X$2SOdUV5ru9RigV7*Rl`+N7nqftT^MRp~>1!8eb91SL^wa?1LuaI#1x
z@pP<urfjWa%ANEYy~+*Q50R6VSnBqbUwDHb*gmU4fQC&S*}*8gl!FH_3!>SrvKs2A
zWQPokHw-Yx0!(HveYpw$uu%Ox&J1fa-S3M(#;1*1;84<CqgJK;J@9G3-z+8}wt0ur
zOD4s$nN^ub)-TNsR<NeEeo95u>;>r@?ei`4Oe0(5V#!Nsfz_`+ruvJa9_9y;vEU%G
zV~+QlwN$o`3EaHkYkJ=8HLXKFYN>dFnT&$KwC$9m^_Qkl(+Vl`IyGwO_fERZj@$5+
zZ1DG%%z~~>gm=02)5iH(GZTaZK88`*8m#1sDl&qMmQP3du-7`snpPX}$9i*`Kj=-M
z!Ru6ZP>rcud}DLyuv5pn?04FJW69LDZcy_p_K08Z>+EML-7w-SzH4wXn~qA0{6Y7F
z`)n16#Wxn<XAiY5V_C$y5bm`xs8=Cv&K`66JAWhGAD~~L3C18zX@nbBfM-^C3In<}
z$VR>0g-ON{KD`=T3>`0xC6A4j_VhsW(9>BcKWe9Oa)rzV2obA0cWdOdNTjWCQA0u_
zntt@pN%3);g`E0LmpK3uL=kmj8XFH-j?TF!y>9CM&dy*BTR^za)7d_TsThYGV5}Hs
z2Fdn!piWvlI}vZy4^Oi8T}91jxrq#HPg7ef!fn)2GH7b4u0i+d{mD0kXe=PUvrx<_
zW(3#Q#&mowk&j+N0iQ879*#0lL6XlLL_j@1W5gqk_S&?(kQz%Pl^Qp-luR3r42IAD
zxo4)8myYOOJ)0I&i9%Uj2}^6(_YA}-&D^Dx)u8PCnHvUuaA4HLb~Ji+1qEj_Dh9^|
zR{5-F5LYN|m6~gc(+&~h)#R0?6|emK`RK5wFJ#D^6L$r}X|tTMFoSMg9c2s4w9-<C
zw-i?sdK1#eF`h#>yEu+0HfAlPLsOd5Wzg4sL={rn=Fu#>xmISo6j@^x&1l7c=d2TR
zN<}Zz`E`Al=5+>ajceGJw4M=4^YhCz!@rP^cI46>YMnY-(K~!IGssB6JjYjRhGkJV
zLi&e^E^WkTkPI0cuuog1rd-p>>W+5M7L`K7!ED$!-|<G;g^<N_s+iVHwn7R#tSlw$
z)(v`2x<E6-Fev+QTTq(X259odn-s`SoOFfbxJIy9EJ_$FLPP0Je_5Y)9}>&9yOo;$
z(XK4p?Uf*&2Zcd&6b?F1J{5tm(#ztGDd6So(1U_+tHFww#sL6B=`Xw>#voaE;{|^M
zM_V|<Z8)a4&PGlg2O(8%O)vOgvbKyuix#?0RyAOXm(sp+gvmr&F#s#e-0YMy5oniT
z7Qbkxu0j<RXoi;#0-1biW=%9=<c9(RH9u-@@o9=_P**!`j7ByAnYmb6#<t)S5epsS
ztnB&E|I1R}M3RLO0-!^NI9a2(SZb%r@okm(4EoYCLW#l)8#U#b47a?=Xw9zlsT=To
zdxZXSQ~+n`NMsZd-fqZ}hd~d&n9d)0^G_f)=Appz`>~C1AOxHOXMGz94|d`Yt>MRE
zAjsepO9VyIOIu!ASR$JVCbNQ^p2H!*e8Y5<rsbv+YkM^Z-s;BYQ4hy<$U;(J;I2I0
zbti3#ISLUntkq6&NJ&e%@_CNUz9wSBmP6LEVJHnT^+_3{w10y*%~;S)&PC|T71@C_
zJgs_<Zic&DL@shs5qQ^54~^;S_H5NRbEa7iaKf0AYy_&h%5ii{;mGFng{t?euXD}$
z{)oDFO5I&GCp$(|c~Y(E-f2}$8CKpgt6I+wTIJpxf{itx{Gp6l=jet1K}^CUiWtlp
zUu`o-RELez!^p3^d!?J5>g~I>*X>MQYj;1^%Mm-%bnjNZy~|fm9Ai!CELA4^y1x;o
z@Ml|NVbv`TJoJ?hY1L@br`l|e^Cg+E%D&)W$b@mX@8jH8p;b7>)WQ}A4wr(htij=H
zRkzap0AJ@6Zl-%LM#8f`)5M^qCZjRE&I%pU9y~mOZgt~j!bgL9r}J+6THA6D+CBQg
zUe&$D=)*svdM10v{qQqJU-k$JzI~?=K8m)9^M2C0#6NMzm%Kr=dj1&Z^aE}fMsUm5
zB2Ja$PoqL38`;(2s$~rFS655R?Ab>nKAAk_f7A+aatU3W0UQb0B(^c0PX0~WjwgQ)
zDkoLuhV^FB?jd7xbs}z^yw!LDAvtJ`RUP&8JC+O_GV8;KhJIQ3N35YTXHHfHQ*Iax
zxW8cz?JnJ+b`Sa1W5b-?zSFN(%(1;{=nZ$MFfhV#RaDjoOUu<Ay-yBRyZqbBgXX1G
z%<!^4y8ADcyI0<&7?{je8+T6OZ{J}J6^}L4w&J(cajP%quau)I)xk@vR&J<lT!T?(
z^jE7F8h7B+d2)p@`u8MWZoB=}p%unw-X@>TR?gZTUB3~nFdlOL0_%5`{ZLfB_wvv7
zY--dGIEE1&ZEUm7zvTE;#|MI;H+VNGGm4Pm;X}SRd~I2e4x9QNYHCQf{zLUZw|c`s
zVCK|tf7J-TZsy7;#t&H48>`w-fPLx@R|h6`-{?=9;u6A(_d+-B1WfU2eDZ#|HI!Sq
zSCxlUS6Iz42(9&1v(woW;Ku40<jjI&q%UO4fujMY+vDIe>bgYl-1oNa;VyMWRp><>
z9B$b5r@ycJxCjmpR+;jZ3J;s<@X1^{8oCz$MfpaP&p7y2c-*wg75zFNJW;uONG>@N
zhJ$Cq>W$_7N~2XU9zO*}{c;n33XXpG9xAQ_gBPoTK#nRrS=|$ptXDCwHQ#rxxIUP+
z?JgsD))+Mghu&rPq+%!0rpE5yajxhX4$Uiit=tQ?eZ`VJ4x94>jqM!oYkYVhC@-xK
zSE^ZSxXcEBKv>OIhRe@{{`-6(d00I&<#+1?fma#!(T)Z=S5{6(Q@N#hID}Lz;tl#W
z@rekWF|<s<6)UJV%7Xz2)G(yxszH}NSjOV_g8IIWu4*~Am(~p(vYj9|sjk2erRTzw
z)^&Y@!5|KaoZXZKtefGr)7SrzHneo0QVvkTb1WMXu7O;qK5z^Q{7!wjnXBk5E71UM
znrfFG!K3m`Rk|#efa*PXa_|Y#J5Y$5B$Bg4_2GaQF#KV0Woh^|a9ed%b1RH}9Rq6B
z-nE+ew^kT7L{-&A4o6C=ldJaj@|MWGD~!}Y!*Sv-0d(o!clP?J6~pJ12boE&!GJ9%
zj!yM!1AmK?XHW}$)rIdSr~eu5NaR$7<ureTxfOVI8CHRiIWS23hs&~X(w`!nu&gmq
zmhLX6aj*Ei&N8H_q0h3tAu?@JCg^nZq20DN^nGPRJbo<)7we=AzTF%4cGN2kaY~`#
za=y!c?{A{|30^a-SLpFW!9b(jzcf62)1Wu}^+7tSdarifRQ0P`d9ZxY`g(URn6eJv
z<THF4BAX!{=u>@{KE#GTJ&ER9W-i7VC=&VPO@T2`E~hPDlKr87Fq{*nIrIVJia#`~
zLuQXLsIJ)CA%o}vb_$~ljjoQ&<#yMkb(_7nqiGoDGxn#S=gbN&l^rZ(VSSjd9~^#P
z&Kthzo$31U`>OK2haHi2xVu{~_v5<j_Xiq>&HXUF5}v@1%i#Xz)oBP!AFXBvQ2#k@
z0<SH$v<C)V9OFYp{peL`D>oQuoLULWrXH1}eJUtNqyFH~3bn-B+l#JegsVRX<Ba~8
ze-M<K{?nXiEsH{L$`bc`P~X&;^0ULy2h-u9>Kf~78Dpx9@BStq7iM>QyjltPbcN|g
zp}hElwH)ne$f_@IH|?~>^v!65tSr8-`9B?Cc%~0RO)g+JS()~f>DPMAz%abMHmkk~
z0ydTVE2w&+QB6<m^)8S_sHTSFodY-C3c&58bAYGib}F!%uvBwm#>*}BcE{&z>NR4T
zCvZZYl?SI3CGmQd3hW<BQG63pCie5jt}aV^CswVHFJ3Eb4q0fXulhUrqQi>dxzX3`
z*AiC*Z9hf+gSztzX8fCr&y|{AQn<!gKI2ChPZX`@k1ZBgz0myi#rKcxh;DTsUdUfG
z|1Y=1zyEk(U%vhKA0Kj`o#K}g-|hCy`o+YXe|5(1;<c1v*a)Ccvd%OeI%sw?(ok7l
z`PZ}8j&J%n6d-E)DE|od**zi0<blU8LwlSJzC?I&y4*!_Ap%3CkZ#_e>iW!=Q^;e)
z|3S;En7or}X3QW8tqnR~petKT&HkyJv3`k{&f<deEkE!BV~1&=nV5#pq++XTCE_?`
zL9eSchMl(#8wDF_jV)HY*0I;9P4=$scP4G)dMAx(W)w;|3=Dg%tM#q=PH0s4N(9s$
zwSVcKmSF<m1j4cjvKf>+J!DAuW1*imy-Bmoxq<8jv4M^e#&=LS!hyAqC4eQ0-Gh3*
z)z`3tbTNS#$bI}rl^2tfy(n9`#%hDpgU$qBJromFD?V~PiR@_yp&w=~JRd0kc$QGm
zr~HsM9<T*Z-0bXDzu(qZ{u0MhRXWTy{7$Q{Gn=-uZ$Lc`@b*NQh7~80MprefGqoYr
znd;n<7i$1jU98FpBNLy{;YdsEn-8y7Mv%J97&p!j3p(}JS-v9N6NkLa<<{oU3|aTu
zQB_+#WqlySIXhZeWP))ws6*zI7K|8U+t5$~cgih{>iAwl&F{V>ECptIVr0tbX8H1O
zd~~Z?)63j~uBTP7p=&9~GkYr+*#p*2w|<Bz(kY=-JK4UR7MAaF-@FQMRXV%O@Us;&
zjk6`2hA(e7>7VywH)DDh{M3lIF})gZWEfs*ul7?R{+nvi$FuVbrT!&jPnadQw{IZY
zpc=hy;6mR9yeOk8Xrvx6OU3oYjy^MT?l7Dnyn3_{IWTj>Xvea`+DdJgS=hu`7$f9F
zM<$%U|6L|F(twpSGKV&Y{?`n%vcbBbT)C@zLJj+0<xKfAVQIA2w(#KD+igxKJZfnB
z*QZu)2@holD_?tX`C6m6wU{3s-L7sj%;m+@XP)y%OIt_pPCZka?A>9mT377%E5-M(
z58P|)n!bLma_hRg=I#F79pCaxuJ1m&&IzLJrCPdlx$<`ww|9)~a_d2FrS@=<7Zu>V
zk?FQ4E$^n$r#})n;a!(|);&)4!=-`Blvd^_QXQ8=uN6e$eN{W$Uh=k?x2UU?pT%oA
zI8gBhBg3Y@i&}JT-`CVGH?sK-RS<l|_CMecmR41sn)0nqR}Dwm3%nzJ;b3rWU)7n~
zxh}uDbc-KZ*ZYy<KUKNCXj!-1#pXD>vl)NGL)Kj`Yt`m4r~Cb*W4+eS%ANj}lC#Hl
zqqmOwFZ{+2ikp#XH@nVZb3gDHPHQlJzlkq~?XbdBj<M_Gg3>fN!rN7sX@@u)qIsno
z%-~thpNQ!iXuPpA?TT*(IWwjV<x33vCF1l+8-?@O1W$#$PPRdJ{2txuoBoB57VIaY
z6msM<@D9n~i)y+txl?5)EqqiCTR-g1$=6q?wy@1Y`l#s7ASA^3uNxBqyW*JwncV?D
znsWOvoOg0+j5iaCsl$5BIA9<*PBdn4K4+)(fUR>fr!k7lJ{3Lkvy5wBPLXD^hs=OE
zILE4)y~ho+Pn2$NdZda>99F;(sYV`tI;U3ZVgstojJl@C)R$pmVi6D4W1$b5VTA#u
zIn0@1=+c$~UlfVwUYsbUFeqtm6cr!8GewKSs5iP-$@c`NBD{=~w3>D^Jxmtm9jM6c
zjdE<}$FF1TLPuM}Xbse$rd%zT+IwFL=Ci9{q_b*Waf2~g^u^EHuivCw*N50Z^^R(I
zBme!w%E3vL-D`HFC(Fk$Uc<GvucAGCp|+MjXohb-pmk(4KSFn|fPp$aJc5c-^?+`U
zD-&-9E-YC);LS$X0DMR|RYM%>dG<4K2IAofc|)o;WpmhNX&rYJ9tfE$H|TJoqWN1K
z$ANbo3r;z;bfvb%Hj8)mpO11YuA*#&s*b)M<|>wSdP7IV*xEy_*H+59V|HaiSrx%(
zjjvTI-#;97jH;@S0-fVbaA5KVgXybIo~yiwMr^t>wQ3oSDd?3#DNJoP!%kgJRt@;#
z^rSHpx|b@hc=vfDSv+w#;83hQ6m499Q{C+FZ5~D3idlLb_g_AKeQ{t^)Ar{xAHe6M
z)3LmeUBnf{T8x1R#(@gnH5bNgCerXV?H0$gS)!TZaq#t<sgcM3Ro)UsKzJ3Cj%B}c
zOh<M+x0F#KG9c>=VH6?TZw84_bV$y4dzrDdcz3fG#HC4Kn99Ku-J#VrR>o2`TxVC*
z=Fv5F);9b`N(;PVDgEhRlY^ewA<G-)Wh9m^aiig2HNp-ZZ=4+6_fm{&Mkn5+0==Pc
zwhQqt5hUcTH2!>}Zl*g+Dh-REe8?I$v%Ti}LmZ@7Kf0@23yQ_kJ+`B=`a}wL2k`Px
zrI6N2-~EKV-zF}!3q*26l#!o-b%-&q2$twNUm;<ch=Vmll`1xuGIybm>R8X~5W{9u
znY*T9&$prN%;8gI10$fDYAK|&w)Nv0UR=f-7c2XvV@u*{NT$uW<JpGh-J=P83}t~h
z8&*e}%^HFqZB*CnNVe&1>#?wuhU;EB@-fr3K=MLqKjW79%#a@O4!g7+@nw@p{OkEt
zar#&PPn0MeO;kpHS}kY)#IGlt5J;|fiPWiOmliz}jU@g=o`GkIvFSW!BLI%cNnd0y
ztI}$7DX67(q9c?_g`#eCq}NAuioOv!i#HXvXw#p1&p;lxnmSySw}*0H$MrQ}O`6q7
znAXkV#?Gq6>s}UHIp64BYpoB}P&hJ)+aT<%hYalp&2j%{LUY$!cy0E5!_h}n_c3GA
z?Y^W}bsqav_{8uxc%R1fo}D^jy1Wn`=7z03_Ql2SyExO+J!R$n%5JmU|6@CxRFfAO
zJAduMC|CJX=dK&eM{XRSvNles>U&47DRzFY)M<Rw-R2(KFly8dc9OcBj~Aojq2inE
zfu1XWH?`i9mqZ6R%{9oHmk9^z17WmlAk6o5?(94Y@sn1!+M?JQGIntW$oi~4p_WCT
z@sCBmzH5W}K@YA)&S2G5U#D5^R_{>nlvlYrM<#=N9i{Gh`}kz{dNs8=$o1u}Q>hD?
zG<{se+1$wW6DifLPwXvq>%m2S$No*-MI&0bb-nqmVDvn9OK0icb&g+HD~k4GQ^D2Y
zhILz48H4+u-+q4oFk3ZYxx+{DUwUm!4qUa)WW}emx-N3=P{uAYuI%uKD=Sf{h8=k+
zC$+z>9&|>+b+{qAayS6{E^@~0>O<=CzA?X7trDc~a_eTq(Xku%Ir+*LSB{Q^=8Y-5
zgJRQN<aj}+9(0>}|1oo&pS>s8XjgB#@pE~@d|wft-xtfMddK{IPPC^O2G{nNdPe*Y
zto8rR_ih+9qj2aK4Zkv6#h;|anYY8;jirCP|Gw(#!N%?zgRX7S@Z`nyu90x}7wuG#
zD?ezBOyz#Xs5W*OZ$GZoSoI&??7Wo?k0<-r8ugEshjKkPG={Fv-!}0xpXffIuJfy_
zuQc|l>qe^Y$UWHiy>9yLa`#$usQh5x_2cpDZ9ga$d!EA=`2FI_OREFwI>WIuH@W(g
zH>x`>!9C)3U4Q7J;9`4X)1mhT7xgZ8C$BEOyV`aAU*2-XKiGD3*OvP5`1^`iT+(?=
zxtHi4!h5l2EvLO6+Vt>&^UIq$a;j3f(74AM;x)BHJ_nZ$U%YhSKEF`CmT!DiJNGDP
z+3REnbE<2y`<Jip7})xD-dHZ*@N+hKhknE0;7V}C^^M$nHVqv3Vr9QF4nN{JBlg>K
ze?Rt%*5J^z>xSlZUmt!UoF1Jw8~Yq<=)sly@V4xA<OQI;>|IzmgSww+oUqJy`|h}L
zi+Qm<zJ56Pnf+?_KbrgA)}<zGuX3!suY-5s?0svkJzMsuJ;4>v+10Bye*gEoImCo>
z3|ADD;Gz-_;b0C&OlP{Q8sJ;mJ*)<{j<`F`GWou44P9?|MhZXE&(H?H`hnFCT7I?4
z`JNlD_uvQb(S7)*ZNAo8eSgk=zdsZ_JG!YscevHB6{?K~Y-gXUjdDut8i!*=)q73r
z8Z~s>wh7Et+uSc%+x%^IuY34Vx#J;Tw6zB6*KTzN)caOyLpx~ufa)33H>T<KVB`L^
zSC8122Dk2BavK|=!wtNpP>pw$c{Eo^dxP|Xg?9+g7mlp0>|z9Jv%m5N`oLbUjN;0N
z41Fkgn-M+vzT6eRXbr!88(omGuJ&_RI0IWhphn-;ZNmS<7nnO-X6)lDSGv}1E7Qg^
zh6BIY_87ePV*3hwvd$INL*2zKqlc~w9_}3(i?Ep9y|O2zt}WsVf@%Yo-M&lmnT>c-
zHx`d=tr{D@zdP?4n;5J`yN+WMzZ%CF^`U+}9I`lNRvjwHDYzgvf_<k{cy-93ta4CQ
zV@&H$UQ28LR*C$`39yEV6M1*9ZCuT^%CW{bIKN6qnz`ea8~6s&TaKO(zj%?)gXY-1
z$?3svT&@E_Ayp2xaiT7`d2roGzH&eWCb;M-4pimn5YFg*Y2<Uzev#92yOr6PDo4fQ
zlwnVQ_r8IxEA=pfa*k_3>(_Aeb>hX$>DxnjvyP+mlePr~`VJOTj;&457GLLEGIgI*
zYeTqmIIq{)>DX1ggLzZYwA^0fa1cS^5H8lC-S|!rk#dB4TcfWByZ1SAE^>#voa5T5
z3(XbguD)>N{y}`BFjY>TMaX`QwWjBZhJMQ)RjTw{qEaiq_mhlpDhuQQX%!D=cRC!x
zNqo2r3(MlAF6VC$cc$KToE<5ph67GA!gz7JmJ7IQapet^s~)ad_#1MFlzmQIfrq<s
zr+y8TR!}bT7O1|%DlfHmaIkGqNN<=plBxQNhfKZaL?0*Co-uBBE8iLX{<hvb$9!0Q
z-q3fhic-_Xty=jDKX=7v6n^q6@E7jcDui4Y><^5hJ$?H<?4D=?LmWuP{HWAR!$F{x
zpIo2b9+rp7+QoH9C!!z6D=zNxl$_cu4-UFr)xjZnclev7^Z<TEUaG}^O1^acqvqhC
zLd0qNVKNSka|Uv_yc&dNxhSs89X0Ade4h=;_3(u2-l1w-xBD9(_Wx&JU-)i+qh5cQ
zoyF=^T6uqf>y+bmYdMFv@x0}hkj?jkzVyb3LvJ`0Lv2j;L$n->`C!^$2h6xBV{A|#
zcY4`Q+i8yAK+#xXT!&T!KYdlfH}N|9Ua;Htf~B};@h1jp*TcC~NIl@3hix#9HrKPy
zktp^<QnmBEaMdPj!)R*f7FX*ZP4&B}G2PKB93z<C?TAyL&2=cJ<iy#?K|7-5lpG7|
z1Rlr;&mzm|fQ4TZQQ{pxlqD-)F?fq6i+fd8-AcHA*kbQ*@@nx&dPne0X7ximZ7+)U
z8Ns!_at7i(R?hOVH1h&ZsCW^uHWC&h{R5@r_0jfE&aMcyjBfWog2QsAQ?TXFb7Ozr
z4-dO{$YHeaODN98@B2-U-umAvUOvOQ_@#&a7|(%+H#B{e37&`W4}Re*@4bv|x-YE1
zd1BuzALVnS$8k+kddq0jSGn%$*hl$&-+aeY!!K;#@}X@eVcq#qjOHzu<MO=Xi%&jO
z6#wG&D-MG%dcN<AH@5J6aYKyfQ`h{~x_3NP`L|DPyvTgV3%Ari=6)`}{FXa637%)e
z6Fp6O?qB<`l>hzb<+Z?n@bOn}Y@%@=uAKPmRW;FlZB$vT0RAG}2Ang~Ij3Z2Q~C3Y
zoZBB>)!&OrX4FTGlva%FEMc*bLNn)5NI8Z$D4o!jf0Nd77sGRGO8$pYnCET6d;0i#
z`j*1zs=JD-b`^1Hif>cfkOo10+b7Q-jVnLhrG|y@au9Q17X0n<S|i04cpX0kt?>pc
zYl_)Sx2kNo%gR+MMZLCuIC@sgc4Ia1?jz?bGLzX`Y$t1D{JE8b#e&h`b+}tf-qx#d
zoNDZ#hXJ-gZ4@>Am}%IhLziXs&~<#WhvSZua@>NmgzxBOv3PwxRJ#&(Vh_Va0@J*J
zcPJ{nHyCCobdGZkSF)KYk_^7-hcohmFrV@ZV_46AY;s%a;F_YLeRZjJkZmgH$0f41
z*uT!iRWaD@MWx25VFsD;l*?x(o(o4)R-uG*Au5Pt_P`dt#emCYD~3|W2pHWNr@&D%
zKV^W*_0F?3ck^gKFR#}<6Pv`?g=eBLn%<CdYeuEG&&K)@5%AK|WbFCc=vsSK+I4vi
zA`OaFxM0Ro3MWrNP8eZGx-S};EJtgw{xr)Uh_aW9?P&SosuW+GsHekPX$wr2ZT{lX
zNUv2Z1I4hWBHz&wu5w1R`$tCWL1mX)cr?J^O8a}TXltoHFSWLy2V*Jd*E~)(^hExC
zUb#s77n$x_FSF{K#kBi?nWD8NC;L<8`0dxT??j`l0VkSJj*cywhr+cqqo8|ROCCo|
zup5zU`0Q11@rs4VG=~Ed9~Wnh;E=2Bbc<GvEZ7TL_}N1oqp79sN-bsM5Yj>$dDZq5
zgPU)n!MvAN^GkPG@3Gx$t>V;}u3hFwD#-l2P0O+F8>##)KAxb7P`C4L%Bn}46}0>b
zKjn|W;jA?pZi=Gd4!hu_BggTz+M|YFpkuYQJNvTla3g%=+UjaFHaZerYq9y-T}l_<
z-Em8gUCQ+DGe_KmMY~XHIO%~(|J%B+yG1uHnKJVuVThtq*<o(>A^7TWXP2Sfn6h}!
zMH}<a@7Jx({?+zv#gw--{OXeJe%_fh^GB@6FxGDh*WYdRvnN^fh9fQT%Nci-l_`3~
zv^Fu-hcnT2Hl)_Lwic}7h1E1%Hlvhv$l30HHO*dF&Dc8HS6jlyX~^(4t||Isjyh0$
z>nFw24_4eNnpX2u+GeB1l+RFTEMZ0=Ze)s1!iR!u!YD}hFdfM+DbWvf8U5rLQk4C#
z?ADU>0B0aI7mr4fWe+JG4W+wRd}&#6D>boQbx4L^5Pw5hoR&qr^D@DCX*ZjWEBDO3
zMi@}fUiuJx@uvmXScpKu2tpg5`FN_}r};vYynT0dxIJJqpoTZX^<1V2zEf$gW1yY*
z<NwS_OAKj-z<T^fd}SoStLsxEdDw|4+B9a&R*!Oifpd+>8ihld6*3b}%5zG^G#?@h
zOBJ2^^lVBfp#6mu4t;nP@ZC0Zr<~1Vtil1_V;Wqi6(x^=%{WfMxG*cH<fzh>5h*AT
zI`|licTh7Tog&#SAp=1o<tP$@MG?)Yr5_^>R?_mc7Zg*s{n1jZU-xvcl=0Uqh{6fO
zJ6#1;No7+ux%5Jcc>#P88z7;$Foj@y2_305e?vIrjzh-MX9Apx-EV62=gxIP#{bXQ
z`+!Gs-uHcj@mg9@Cuw&N$D2EXB<98JasVEWM^s8^C#`noX2s=sX#y}<FHcZK!g?Iq
zbsmYZ6jOcT7_*r5?UA6#L&)g#*e-d<U43RBm*!PYE`Dl@i!4(3>A4~iH4p7JmWZk~
z{Wz`e*rd6-jnmKfon4S(p8gpu7Jp`T<~P6h_vicj^S<M*j@=KH-}-B`U@0>f>6p;@
zE8}C_N9?(ebD!m6IO)PrdLZk~0;`v56zSR0T-L<-g053yQ9<?F@=?@em8b1VK-!aq
zTVen4@rz^+U1wqShgK_v@4v&x@(lvsziA}@|82UveEY+OXkg2R|FA!F;?csi!($^I
zWv>8XFiq*9e0%ScP|fzn7e2wDVx{OI<+vcGY1ug`L!A1N29r#a;ampiWy~xeheJ-1
zC@ZN?tVX7QmYggGxdX2>$x_)5@b42GZo+3`43SfL^~Vc*#A;dDa7f)G|79GEaj_rk
zIgj}%G8CbLb<bbO_g;w$oZ+`KI%-8v<-6(oc5WtGu=U|)(MR63mjZmTYz|T2_kvRi
zL_rg~?PsIMqR)T!<76Hq*a1xlhCe>Zl(f#{kp@)%(3>-vj`7Z^?NRyv^nWY&`k-w^
z7hBlS>XNH}e*W19EA3vjppU0c`EX?h*$v{m6J|kwDf^ch$FSOGHAxCOf9Xm8g5gBV
z!QF7td7vpOH9H5TC9z)jv>!fbKN5EGCZC@iW8x2&rJo}IxD$M4BVIM`iR@Q?nH$ij
zo$KHJ?;JQG;)Y|%=PD;d*mmFp{}=BZ)f|7|=={Ho1F1&`J2?^vJB~WF_uN1Hkmz`s
zJS0#WvkDPo&Ko$iz`6AP9S9c@0{^ctjp=<K0C__mb7S~FdKJHXXfi9<Q(19*2v&t}
z^zcKa<mTx=P-_!ch0KXJ%U8&6JJa8YIl=3h<yqEky3Q)iGupk0(0TX3bdGL`XKIX+
zdEsvoCCpKCwAXp>!_YO{`LmqnP4hymoxd{r<d=St)$P^W0+SF(=R_q|mLA3hPM5Q3
ze$|N2`<%0Kq@y46V+L0WAjZL@{McjnCH$Ur9H*%Se)Rd72dQFe%iry<GA(TOJ^vM>
zW%sQ5c29oP2j5Fc24HZ0>EC?Vk8nG=KCX^Y&H3%}7IUnqP5I3INf6ZBHcXNmetCG^
zq?8m8E<|y7Mc?s#dj(2H`ISH@fm1@W@G{^3&p<rd&^F##IUtgS4jg}uo9Bk5NULM^
zuK2+iWcs(Gv-5{#h|^4)t3g3-7<I_(okgvn&}=%_=g)u1e|I@LV&diG3!hm@zHNfS
z1HJ6zQ|mj~$>Q0xe3g3mj(>+A9xnfA$0zam!pXzt-dkVrP4MH{&pi=5+<NQ(>m#%O
z?;q)%^SqQLbJB^ua%ZJ{VTx&Ecc1)`FAwS3OLl(wGw%+vd*b*@S@ZtvzwWi}&%A$!
zva!44=`WbOKNDKIuC5g7Zn*{zqo8_!hN7LsnpRi>f#s%Wk(<D=JL`5|l)^5mQIqaL
zsbc;yL<%#Sf5<T>_CHhK%RZ@H4cggtLdQ&2@$!X-jVXNd4?hun=G<~}&u31)5SP9k
zCp+0c-pNWk>t05psdC4WiH-8CSFWWeZ<J?$I*pgdr$6)U<xdW#3n$--Tl)v!%4!gk
zZ>Q<#;5Yr{Tf@<be=R<d-80Cp-M`){rq_!0#7ywW&-)XVf8XTi{m?z}$>E_tJ|v>9
z)Aqgah`&~TymJ5aw~hJb*nA`Y(7gr{zV}x@;`Fh8<%28!{nH0Ge3DKiy?p<0<<82A
z|7Mwz8`71{(G?Y?nVz5XL}$%xnpJhI7&D{Z6-gddU!V^lE9|((+}BNQ%S?65hM9`v
z1>;wb#?5w*MK;>K6l2|Gks7DIV5$p@Nj;9^imP8Gw_fE-yPp8Y)5?3~NUziB#L?rG
z+T)eu{=}9aO0{rhC=C-&!`gX5&6y6iiK^rb$L5rX8g}q?kEvA_%oMK;vsxjp4FJw*
z%Kc#6ikS7(saH6nT8U#ffFM5z&@+slr|*CLP2tDx{E-*uzy2awHfERJ=O3K)Z!;m<
zidUiJ*Yvm-J%lmkbCx5U(DWW5lR!(ypEjKpIJIF|Lau&G^)wgGWI!Q72E6W8D;4-u
zS};K%jYsEM*Zu8(b&G?|IQL??{B{4x2Dfh*CI;tr|Mu$bLDZn)wzxis`s96BhMID>
zIcs1C*Pk@d5<a*Q(5V@fcp%u^da0QxG#YW{E))31pW31hUSUe*!qe4?uyP8AEMqV?
zbEf3Zaah%*s}g3>OnjNX+-J((<c+8Q{#-M&<R5CEeQD#}Y5&lZJ`JjI^mb*h;;wE4
z^~I!~EN0zgqD5%D&7#<Iy_7avHzW??dv%L~8hN#p7_k@)QaXTH$G9^~m;0>o{ot5^
z8zE#$P)@aHFmWk!d(-SJEd7#!UC7K`kf@*ag-$n)SsdoA-hIrSO-ZReQ+{>rKxwhZ
zT8Z5!!~Qg#;I+3a8$RypaOH4?5eyrJB(gWLwBBeZ86>1#Zzrs=@)Y9TaaT7@LTxyr
zBZ{Ra7PD-7F+qIOFwHpP4YO>ju76DL_ejd-ke{vuog39!HX+lYUFR<SpSihJBI_z5
zcrk;=w7)#hiUK!(`WF~r5`FXDI6^)?Zfa2k2TeQ(jt8~HBxxjzFups!xYMumTgLBA
zvJtRR-`9iSfjDA}8-$9D)?!9K4_zr~`aC?o2k!VMPy*jK({4$Eeu*(g=J{qYjcblE
zzO{}Um}64YfV<&7i>u^$$iJrLo9C0#L{gkP-+k2UqK0Fn2Ug9jf9M7O&UiLRloe>N
zXN}^vH^H^JWoL~8bP&UAPP$Q&%r(1<y@a57d<nkL{>@&-7lzzpO7NIf=&J3_E)Wl0
zgLt$eTqE=11b3O~I9@hkHHL4cg{SFX?g1%CI%VlMf8mGbxY~Gk-g|NW2pMF}Q!k;R
zOx{k$7c~O7+oagVm}Aa|TdCco0!WR+({-=`yrG>w+K2fm$p~CTjNo6F;=Rs+R@dD+
zTylJ*jN>XtX%J>L9iH??W9@}93)B5VyPiy72Smp?=37vI&9_I&V~I2hp0=B)dxmt$
z^0CzmPND!w>rXKt!l;~IgjDj8@~fw3GPv7wGNfK%EXDy-$tX!5u$fwFK0SM(Jn8!v
z%Gqsym9AH8+N0-RV6et#Hn399`(>;~`B0L@zz;NWsTXw@cQ~WIoEbO79602M3Q2vO
z))!}xp#AmYjLWWR)X(>843)0u`u?S&D6!-?={gn;yO7JZkL(A&pZZ!d=XIv=lK=X}
zY3cz>>u{1OfP{mL41+XZrf$#xs&BWO4X-US$YpV2$k8U86h#OWz4J|qA4oi-fb}Vg
zJps4v>h>{`)l&<XtvP^qd>Si?C5Jn{@0Ti2>-!jaQf0{Uchk4i8-LLz$<G*!KRbQg
zKT}b^ztr25kL*U3Ls0<*%DPK~K`EJ7!kCtd&zQAJj{_WQvRW>}o<sz#i_J!}&~Fr=
z`E@MC%LX~F?qb@pRMjmbV-)y7aH)Ap<AZif7tf*%(|ASRrj4Z8t;a}n)}`@w5`*<O
zUZEu<vyS(rjol-a3ueZxzg>CP_Yb{U-ko2m&Nmv#_;_*v5|eJTRcv64=6Ydx-1<MP
z)h3^K9h)JifYoJDMF^cp+6ijHidt8~-QH}-!Hnguxni~qv>rF1Z%6m^)0lXy5)Jvi
z=fj#JgwRJzk8w19OM(e&FLo<T=wW+@b!fd?uX<x&e5XJ&cG{i)`qwI7tGxK6uP;!>
z?Y_XneA)i2&PQ0W0%}LMRqH^*YqcRSOV4y_-eqH0Qg_psmrYnJ=%}RGTv{Jwjq&E<
zKu4`F^w>G+f+sMvkC~9~AgIR+m-XlcM5o@XgxH(dz*!vqmN9|Jb;&{w+P!)-+4s^f
zPJBqR#ArNYY9Z{BiMq`ktfYIfsXUUD7L!4S479w(YY_s)=w!%%%kXm`Z=Jn(Ij$Az
zg$&7UF#x!XZlMpB@j`n9EIPJl;uW)N-Zkb+Om-2pIBlp+(yx-0Jg<2<7phXc0Ww)O
z)3fG;@k@M=wsR*1{$!=6yqo1$OPpQCiDzK1@aS!S!c_({43h*`<V17p&^m}3EzC)~
z_gu$RdeDbDhhYnw8{w+vb_QvLziJIorc$^Po+p>R3x|+TBw!cmM}@2H4*J6~9(aV>
z6CD7?J#e>L5rzwNB%^+@x&UZv(sXw#zO{Sv=s%ikCVkw{PB=5`mzh9uo1uKp8y+1g
zEjWXIcL}$O{EcJo;AHw7W9(3Iawa#;YFwZ?o<tngZbGUI05+%NA_GC)JuU(^tr{V8
zo7Lt~_@I$a(cb4eTPiSMCl|~#vtf)I5EAj{El&Ns=jmyYmGp~;KAH}Y%4WFYdu0$?
zWeg$@R?b0VZ9KvH;LVdp``RGuV}P6CawkQNEhg!>kHr#K??4G_*-x^F!K>e|nRmWF
zy<vhAsBm=|8iOFk#Bg&YNU%@qE*VuPn5u}!q^>7Ho25z&@6UTYSTd`ecxbMLfkv|K
z_YZf<WpJd0laM86j_zR(`^X7Wnspg4uLw=6jB5w66I;0!ZmCp|WH?#vsSvomz<?c#
zm(8)Qp<djA(-17>kd#izRd))!HMt=mV7ca3F-#)+s1~=YkRZPIrx^^oC*Q6tSGs-w
zxIbR+12w}|rBEL)K+K@q-buSl&4HeqbT!2BfNx(Gzd%MpMMwwk1OLwmg&DlWrB_e^
z2C{?W#x5>wrhz~|{tthbt^-4G@PX`$4%9Jzy=^XVsvR%Ix2pPkCQX0kC1eewdmc?i
z6)kWqo%4@Wu!jX;4?5WFF7+Bq*XXJxD0r*45<Z2ft5hP03A}*B2{2S2$CsfH9tv}I
zR-ps?t8RD<2RGee03deZm1;%aM5rH&iBg9ky6IiRc*ABuI`q1k5BIoJ`dL{E;ttQd
z{+EBtflc*3o~0(EcZ8vRUhk`&Sn#_L(ZR5|(_LyoE+jO)^Wj-^R+r_LTC;&LOVT)i
z-CIh!*a>f3NVc;Q7FUg1Cv5Qjdw2_EuEVO7KEqF^upF#}@pG$Nrsh5m<L?3+xc<dU
z=&WoQVa&Qe->ZD<Kl;cvGQ_~2eewMCNE>LiI&#II^$#z6j(Fk$Bp<+u=p@?$#H~gP
zNdXT(i^(*27>0btEXS?RY|!AI0Dg<DY`ZxzF)mm$v%yVuIt-`ydaqgGt0Uf7bd^;R
zT?I=XW_u<kR3TtnF_kUDp_?YS&f4BM@c6X3kRoPY4^0-*d${@GMxl?^9C<3dY$jqw
zg5mhY3XbN@@`it8ImYB9!19T9YnwQy0h7n!5BI)C$^ERHi`DF{fPsMQ?e@<0#1gZM
z>@#U!HqRj`D4<pD05y_1kvJj^=@5T`m6tnf9oaA+X#n_d8A3KI*q1MMi<pRK%CzOM
z+E4GB|LhYHz%;u(e5tZBox8y0N?o=GX75G|<p?*2SMGWTBopHvz`68R4{>`R+&CV9
z4x=Ok)GrO9LDB~ZX5F3eIl?2^QQyaqA`(IpzVBDtmr*`c3rLGk4JrIp++#6>;@Sjl
z{R<Zb15yw7@<f`gzxGdlxSvI73WB*BUcnn4NAG8rE5z6nd&F;@&Xr&}#@V3zpyj1O
zw?%w}<f7oUcRKn6V1m(xCo`ShWD~=RWnElP2YnP1EQR?6aG*sP{5_1=7KZ9xvxjjE
zk4s1`^Ex03ybo@<POEl)@D(H`eBIm)I$6D9X1PVbihr2v@j&qVJQgb|zmwiLxL5KD
z&I=PA&dj$R!SHxsU@a(ZyV>694-m}aw%GO-2m$O94rO@e-5^k0MTb_F_2F;QZzRQ1
z&s{UPpc>9NIBseSP>UDBhs%w31bm72rFjai!l}3tBk3IG&&*=zh|{@~?vBTTNj$;$
z40fS%&ll+GN0hIkVIbc-E7mOJx<~j_EhlqHePSG0J+R##*d$B$JdhHVS8VsPIq8bb
zMey@LP+Fmc-OYevyL5dBbp5#w?%S@RqaWdhJY-$=z`vVjZFGt|Ae_Mwz0rFO59wY1
zy?gNIh}7-jk%jc&6~8iOuQy}jesyM6in1;E)#S1*%uKr8iSG}AVWXqI5eN%u{$g61
zSnPGji-Ra*2xstGA#9sw2y0g?CgwxS#(~7PkxSN9yTx_d98-e`-DSe5J=3{@sX(Wu
zh-wt!z~~*1CHr=~^(VcXp7-kX$H<bV<*#+V);VV#=No09@!<;KcngyYA3+q2b`RYK
zQ!uCs@3`7iA*EWFHR-Od1Qfv}nXM?nFg8mqjaTS0!=n<rRvz_Mcl}H44$6r#A^PbX
zJXGDJ4yJbwf93-%@uG1%^brVW{WaQLX-j_XM?c<0@OnHj<w2&~6DN=7(R}U60E<&k
z+Uwnk#cSJ4P6kvE&T!&2QZ%lEZGxvjcDaaBduPz^qdIANLiJhp%prvsNeLsGqo@y9
zVf`!#Bv8lk@Jxp@5Huc#ynq2DK*E(l3wMyMjg_u?H~#p0gg%@<MZ3FS4d1S8`Q#Y@
zl^E07*h9h0GARVux1KhZvhAgv#$r?F27I1n*a2oxiL#rm;K$4ZjQSkexyAK_iLOmn
zRTD^EcMXS4EgPQ!y%z<Z!Y)i9npO9rbyRrNo@9ulYAYrtvOsw6;)|nK?44C&;$6jE
zv|;vGiR1G>Pr(XvCO|?!i&a`+X29*3QD_mtFnq8L#?+{{pvf91c`BeusM#s>Lp2J#
zxbtLgy}@L&ep&|~fQ&exs{BK>f{TKu$Q)xYoU5E3-@O?3fn!A=P^38SfD$Zxs-AwD
zJbsZ?kJ0s`H~!B)lLazv@zL{iIE<AK8uzidw%CB5i5Qx68T!Qm!2;)H*w^CXr0X#9
zlglvy2jD5{9_ThF<OnzhT=7IFLn?@Lm*EZ;{w{Q!K?NaIPcbIM$$URX=+wjPJ#WO#
zU1^W&gM>SBT6SA!#vRS2H~)1-V-F;J(*LUe=#fJf4Ts<qf{NqS+7Dwb3DbMsq>XqM
zAr-knch*d$$f&=Zn@s#Bw!Jsk0t7Zlb&R7NYd9iH8UtCYY+$WLv<n-F73Jeone|Bv
zV;$#i<4mi<1juq}Wdoa#6S-Wzwb?7*yzlN(tDqFvxkD^?$DDJpFdmXr0LLK$9<hXe
z&1G6y0;LH!qCs8>6v9+26iB!Z<QC$-{b|M%(SsZcCLM_~-{5P@K0tYg5#KTjyP)UP
zLI-C>{KLZpyJ*WNKQq^i6pM=<o3vnhzWvGjBlGiWpU|bcOY2MllRE3{sZFKOla#=$
z@x&{V6KgSXxd=v6jwh%NV=wt^F^P>I8cxe7%5oLLZr>Lqc3Ck4972dO7h<=I^(QQr
zBPVzK<3x9*COLuf?z!DEDna>88;y*Jy5g2-d!i-(D}=g1+=3zigTqxaiaH?i3Jpea
z5isu^013EjsH$@eeoS-uX&026D?<fs;2hS@^tMPe0Pgs*q2VzXG8yN%c?&5Fn8&hH
z&f1MX_)mbkOpx<$4{r~@4mjYtulwT@c$G(hXbC=wXrZ4(UFbxNXSPt+oI*EzJ`gU#
zqjV3<UF$XvMA*Sqr7eIOGaaO?x*>g7g-YU9F1@b}?7k9m7vYTbbb19(f?*L5mR_Hd
ziRvQLga_^3>)sb%JkYnIH5^?=wM=txB*Xo{f;ky0eUd`sL_3k<_QixrY@pHGq*)2Z
zzYsTo>qyOkq}xoEuz~`%VI`E21`?nNIKkJU0upi>a?vX~XF4e^gnc#a$`xbe`6LZN
zw;iG{l2u~ecJGVvN4E*|n$7uhhc__V5Xb5>@+zp?7b*|L23Iyn=UT8c+lHMue(WnG
zVqG>(B1_F73X$fn&0QNr978HR%?v)zF>i3$J-%V<6qb6{D5*whqsk?w+U)iWW5=x=
zTgLS)%ZJZ!c*P}1(}2(QWTv0@*8LmZ-v`AI1-J3H2s*3j<cxi!Jdc_#4iKViDQQRe
zB^At*vGsA_7YQ{w&D*WPcCy$i9YDclH9#z`^il>baO#vwIJ=_bVunwgbcukB60-at
zKk!Ob+4fS;e>)|OMhERT2Opuuo6(*>_aY@E><Otywxschf*TQ(fNDwhAcWFR=1*gh
zU79ZJZW1dP#GM3Fh>jyRS;oR;l&Lh7j3rq{A?kn-QAt^hHDiXdR>|2fn<_bVvQrBk
zSu2oEv!@90*0=a^^u~XDN4-GmsF&Uz{;C1V*wD*nP7VTK<MFc8bE4R20=kG|7*i0{
z9*Cb>15QslK4Nl#@_KRm0PdIUgo-}T7}7+@|0+3=O%oj3H4GjW#35dNpAPRagWxP7
zr%Vx)DiH~ngZk-Lx*W!+p7*p=gdV~0`M>zEECp-3dXJtx$B2$H+KY1<Q`DoexZam~
zXm}YkHWX9k93okT0W6WSw3GG|9BT0_s}O?deLt*jNQ?QEDqBDpYqbJ4=9RqXjlYT=
z@^!2d&a%pS&fwA1f3x>?`kHs+g}+xiATK#C4*uOdb21JzSgzRj1tpUr7>ALGBHGmX
z<t(vHC>v)nj7yL(vl7S{%?+GEL-l|t>obHLH=|&Mpk^6lKm@Qw401RBgjoze(&loQ
zB$RK=;hBy;V#Ld7RA@^_%05=yi<ewzM31E-6+mKo<8S@bxfYDdy7MWH(}d&4eUdET
zF%S)<yeey_6s*y)rWwmjxPuy-(56|)#)l8OLXuzwvK>i_F(4e-3D=f8Bu6XYDH4hs
zkb932_$Gs=RK<IMAvAfewK@ynUN+wanj117l(4-f6XUYgw^J5F<n88Xe+~zRIxE&3
zMx-#<h;auOs3el6SOQNGT_FYoo=^N12Ks{>CTAfy(_8{1E)D7^T9<SN;W+8)oN3T;
zH}+95@VJ@bU2#|LdEUom;t5m$K9DH2VdFGM64dBPT=k=;FUvXdJQJo3@Vt|ju8F()
zyHv7$MF|I86|xUK>7Qc)+z}Va!1a+A2jhY!xQ})DZUUP%7j#R!rA+jL%Q2BRlgqo9
zUpjmn;34lS@uM9N*!x|BjEe5pB^F9q97T>HS|;kaBpHGcWsyo|3ALnk!@uMz5=53s
zx~=;}HJ|?}gcW<-?N6WCs9AtZn&8bmu2EKIIfjhFfNW4g`Yne*Fq_oX{R(A?0F{zC
z9-MT!uK~^|S-O^HG73tU)rxB!V=4&bvhjtnt(Er?j1R~~iF(|e_-kvJhNLtR<HBWM
zca%}cd7UN8d*AuFTN(w%6MJyv$Pw!?c^kdvaohw;I|FO+maweK6YzPAIffO>8j(ok
zW&uXP;Wjy=BF-Jor)Dy?@LzAWm^YglAYCYIqy|l;eMxk39<oE+&xVz6_Bt04@21xq
z!@OSg%I~COFa7h63hFvp`Rf~`rSa-Hf#orR1#-R(#wSUM6P6ft9EA5)k5GA4saJ%W
z_z~kvV!yw=c&*Wr^&?A%@xt^1#K`{vCxgKEDMVg!Gtd)mP*NSkZRZV0_kBj)XS98s
zWc3#GU(Ydl9;fu0H}*@v@gd?5r+d~-Ep^ObE+6T*ZzP?HR4M^U6hV~P+&~^8qw1m6
z-a1^|NkWCU9OQvWO5^SIDC*CVg&<=QhQ|nAN%REJsFot`o=O-7iUM7i?g@9A@y0f&
z1|0eUWs^;0R-<#CW}5rFTc1eR$~S-WKSkup4>9f6ZeZVhbmtFIJS5Np>^76_#b(k?
z#_2y{Xl3yQ(@kl7aS$oKN}3ZbrHe`Ls#ICx!r%wW%UHx}eEPDixf00SoiG5F$ahZg
zZGC6uw1IGHby;=?^MBIxTmQpH`vaoO^DjP1_k}I+-lyd1A%)kESK!7XQ9n{QNExh&
z1XGVM=fuY0b<!-y9KcP@UE6M7Ly=o#DU^K2RT0h+@CSi00uZKp^r$VxDXy})_Y|@i
zXGN!Gig6{?!*)vE97ydyPS?`W`&ifR&3|zKUnBGIq<?k#%JdbVbmSG^*mpIF+#Y<6
z_meIK8=w*O?~H5?GFwz)@);uLPRC#$sJ3>tg3zEHpv?>|+L=R-m9JwZuMP(SZNqSC
zLw<&oP8g!CCAXwyvZ+0&9X*G?n1xVDHfA?YQ#7y$X<_psKD0?Tm5vB>`sV-m4rUU=
z*X@V2AG=4Wjc7ac2yvhUF&ST?U{6+;H7SMadh704MJD2Fy<muIBL`8)8U<1wk<B1l
ztSGFz0{WpdLr}8fb{A%pfL5f34dXm!13&D7%U?I#3$H3@o%H2JC0rOe2z)MmJoPHy
z`IC>4oaD1Fyl`gY3}%e%B$XR2)n#i<hvUzhJ7W?$Q8WNpW-#m80H=sfH=pR3H9oM3
zkC@?oa#q<5LMGICv6(`51Z3w4LRe2WQg;}~Su?Z1AHum9mf+$=L;(c{e6u~#nKXjQ
zcbUKf;fgWJO8UNE^%lqskp@Uv;Phzv<}1Zyz>4$8>!altWqU>jh=(6k4t=UheZBy#
z1cy{|3sMvM?p1)V4T4%BL2J9M*3$ZRQk1EJV;H^F1>DCm_c1&k3XZ$BV@@J)&Ba^6
z>1hDStbRqy>Y!odv6!yWmjLE`(kp)Y9^$Az^Ot{p`q%wmr*BAO&C^73^*;0nL+DT$
zxz_clqhJ`Z%IzL`pIz3~Ksr!ydg)*@nw50%<ji<^tGC-DeGgeNjxace3K6Q>KqtIJ
z7YBna^Us-NU(>ThcHlkAii$B;Il8p4d5M}DhrI)xcX(&tX4Ieg-$<ZJM^$aWa$&()
zT1W4w6EBx68r8%m8QnpG{VrzfTgvXcz)oJT2QZf;5Oo&vS4%xd#uAuzwzHwSDXyCD
zRq_G#)15#g3-V;+9GUjZe1;*+)_p8=F8CRlqA^NQ)S>#`7cYKnZXo5K^SWbcJsOkk
z!zLGmf?CaHt3a?|RU8AOeJm*QrGWURQGg50Lf30eaK9EO<4LOEvs!EbZOSe$Jbi&S
z1!O^a*36lVDdv#)skw&Z>aKGUBfzjQ163)#cfL19w-jUCZQ7PJH8LGsu7Gjw^Cy>y
z_`Vz@g}REbWb7x3{RU1-VU-;5q-!3FlSbgu?4eYBy+F$zjBrw%D;BXze1`^$JW>;#
zOPFNY?A&Cd#vGQLL$^l$3V#=rJePq;9okXPq~ARJanuVkGbIjpu}L7XD?SDh`(`l6
z567ES31qo5LY(Ft<8-Yb;r6T}URS-11NnBzG`CD#Kve-hSng<hG1=y(b=pn!3aB;g
z9;(GPnL5!7BjeNJ6Fxx6m=s$`8W2W?)4Hh{%wYifiCwY)vPpU%$I%;C|3Rra!D3kC
zdTtNT;gPY1@_mRrE6EWoCZrglvjtXcOtc4#l+_Osi1Zx7w#DQmz6e=Br<qksjgkI~
z0#sxn8p`!CD7<R%GW`H?j8F8dtS11h!BcY-mB>k~pc({mH2kIpF?L|1@HO{&IGSh5
zw_c{6@LPXQ<~q%If=L$_XuBa*uZiD=1w;q$R#m=>$ORxL&?{-7`=iHYuyuqHOl1=k
zeK^K5G6+$BFd&b$la|IO@W$-^E^yJE!oy6vAZ!)?X=1rW!iQvX8fr@JaqUn>08qgn
z`1ioCH`NdYt#oBM*Z=;{s>c%mBH1A~^&XP=q+h2*G!C#<bHcXQIzR-2u|j>N!*RBZ
zaI#;)ZK6A%@S6(Y8yO;*n+{`W>GCfTnp!Ynn>aI$uqYC$l+_JXopDM0ErbG)tVGCc
z#XDf+tDiykQJp{f`n%K9FID8S^DlgM?ptQ|NRH3Mg*jr|<|3KpYZydQ0{Ad`H;nbg
zibrf1gX`W39!8|Z&w<=G)+cEws67#`ag<_}sSVh5MIPjCe(CU&Ax6D2A4x)^6*}-{
z){uW=_6+x^#1MID(?KCETwmBMN$!sN7|J`m)f=z=i&Am`-rnc`DkR~?HjSCsRp_9G
z8~fu3^M*=fl_%Qka~V>M_37fv)Q2IwVLH4aI8r#$Fnxy}!ohYyvYTcU_&A}N5ivw*
z{M^IKY{FT(Ev-CP(R)%wM6?K%{H%?ViO}xNZxo=yo#Q_6R2=E0XQP|JP5ww<c-DVz
zV~_Jgvt?w?cT2T?HKd=AS_BAa!}-^NN|tC{WJooNZFFjFYPr>UYzVoFTpl;mdqP0R
zmeDHb(n6268`3nWys2H*y_0v_lGj(tdb*>wtzo?vA+sn69P)Dc-oN=#bQGrF9v*s%
zc#@6+L%!iiUU%Lt&-zfRtRH;EunTcx_R?BNCWqFVj>+qiIgx6*wb7b-GU*gW2(VrP
zm?U7Z2LuZiQ`3t=iA2^4C`BX5t^{I>yS<BhVWW}1a@41}uJY=uA0o-Mjw3{t{b|@Y
zosYcbp_NWa@<Tqc18FUyuJJalO(fE=qtJYuNZblDX(g~FZ9`i@izY!7usK0SlL{JT
zN0j)uE&g-Bv@9->1PBw_j{!GmvI-#^?h1uI!%QT})1GmULGpBGS2f?dYAct0^c>z|
z$12@-(l>i=dLNBwjI=Sj82Y5|BkmeS!RCV|CR%JD1^9*nLE{7#<wSUb5rC`qFqb~J
zlP+Of9TYm=zD5EOZ;sYYYX20<vw#5lz&as2i%njso&tG8Df2+pB~7-f6Jzb}Ho=UG
z4EUt8Phn1q>t*sFYJfdkzPa^hRA|&oQ$BPaT~iAYMt3|<IW1B#r&dZ3gqH-a?j-WG
zb#mqCq^jeH0{8T?`7v|SEz#FTTLN{!Lc=Shb$X}RM|#h|uRRQe)i4F>E|i?!M4UiK
zv`h%aFj5K>w3i@YmR}?m$S?MghSk%X5<!gwkSpr-y`vv<NW=H25tMh2s7e6tBhf@_
zKj=>c3xwi=acoJ7p;M$=Bbn5Jy)NE@uZIHSmSk=~Je>{_JO!dgu)7kHfM9=(z744u
z#K_4hF<L!(D#ntfnizz#+0#sM7zR*BN@c4|({j0Yk0#NxZ}y_*JHPo+m3Fws8E`wA
zZ1KX#7_(#srTT|sLlX^|FEAFynCc{cMm(_+3|qL8O@FpH_@Tg%10XD<g3ule2$$*P
zQSrha5!TeFiFh72#}G~eLAQFU9a@9~)nJ)t!*G3rV>`IwkVL9VYYSv^rmP`m*<#wO
z()F=A&D-lY9{!QJRs!58AMQ}_uubK6RyO<^EoZlxBbEEm$PIK>{16^3VAX&HAW{Uq
z<4!`kzH<{1(TGNrC81G!1ijD4(X*=ZHpi%=234;~CY;J-6Fm2Pm|3_K-iy!1*3Gz6
zoQO%+Ft`g0LL8pO-6@hr-=3u7<I~f{ZM-k2B0Wr}=GQ88qwq37Yia*PN46SAuPH8o
zkI=Qj6HdZKOtBFoJLXK<JyU3yEgsZnO${$$g1Q^{n0nHQ3}@Eu#aF`$4wC?Dij>k_
z9JOM20dNF?NI9Rj`SErSc=MF^6ej6R+I{Eyw^*ddUHsA4SEg_H(-uH}Kq&64?3RTp
zvA<|ElT&cc#kG|%gb}=KNNs-=H%ElacCf85qI>dD)=|;_3Wz}nDx^gS@R^f=0U+Uj
zf2bgG+0@)ANQSwL1|onnzSMpi?(#}mWBpketS@@Nx2^#KCnkz7+&=wldmCz@p_2x@
zYm>Z`Tl=_Xc{lk(i|FwfoP|6OBMC6$5~{IV2^i5F>c6Xd5Dm_vw}Kzspk}n>IUEfZ
zCQ=;FKZ@}{+fcSDYH^pTvt|{Xw&XtRosA?F`s?Q3z67yL>qwL4^4QHac3w;FjUls(
zZ&Qv8Y3mlB4N*2Y3pr?;_4iz0L?+Hn|DttfSq;OQb%VOWRau2V%F0O5H}tZh!DdDx
zfNR5aaOf1m;QNx-5tS)%>zhQbbbZ`<bNTn_gGK3yslT@IHA0=72COFh<!j;Hp!#FR
zw&W&*G{Ifj2}a$^rgl|rC>+iOk%hhZO2D5^o%AnrVCo5tZM03;BlfVs$^pozA{a;n
zjSIx6Rc>7vhq4nXVtZxWgg!*Vy2D3(N+*{UAf5NpbuHumn#a7k8-p*@iTH{ybbn^!
zuu@gLnAAb}?y%aT7dEP&HRMAJKwzr=B&e|SOz1eHfpF;tadqwoH%+NfpIF+7oJP?m
zs!=>ROp{zyc(Svno*7<n7<WNd4;5fMKsmJ{`pPMg9d0G8br6bxX7kf@vpLKb$hxo=
zJY0FT@sWs`RP<KV{*Taq)}Q19G%aGbl)0Ke9M=jFDa!#NB)vcsZIN73w$y=L$*LMe
zT~kwXa2u0BUaLuv#yB&QDGd(F|ILx!3zeC~wbJ4&U`*iLb8P<u*k{Wqdl1^1ebqa9
z)TW8XDrYfS5P2qj>D7<UWqo|=li}kX+yggewos(uSCyXu!B>*?alPAxj2;T46#@)H
zCR@NL$?_YQSe;e@_zu3&v?PYLUeqDV>0n0Xfu&!@Hx$lFr$fzBBPRt4&4^Bdyk6@X
z5|*ULZwUxXyp(n0&#5?dqxCiBLZ!%Q`>dwTfyEek1!kx{H6HcWP3(?e35-jGL*b5G
zOS4VURQRoU#)5LAO{N$qrq;Vs0ddChZnsFP(m2^{5+0Lh!N!Ya)8H@PzfeV%F@Y34
zGIVQ_8z9kwVpTz390oc79tcRC#~tX=Y7G3hzW0f3_*82CQF&$htJCvG)U8@ZT<9XG
zeI=Mz;{}mSw@9XiX)EX-5lWHLt4e%iHWGpaB3)WkmwJQ#5Cf}53f2?gbFGO-DqSDN
zN5GV8Q9F}b)`-wVSQScXqf%>{3vM~j1Dkl<L%nz7$+zYbcrw>JcZd(LL6>Y2)84+~
zf66yDNx9u*3c)&|Zb8Ngv9d8_KHTU}Tu35_PPlRWa~7#mrV@fNHBb}aANNX5stP*^
z#rEwJGZ)FJi7wZdZ9;fOFTnwDCgm|;Bn+PPu6oQRdF~HN%q;Tu&5~+O1O&>hDSZIC
z0!S;eJFuO!n*$_xD3f-S(NhEwZ`|$;D5FxmsV}a}24=K$%ha${QCm&ZK#|G(K?+t<
zoV3mQHBXefe!zTSW_3{kAQx<dZsy+5AIS`YXCE!K2mOp^B>&8YHDBC(q+*zwzbH8R
zkH(Nlw+}F1TC?qu6b7h(W?sh5$P5W%9}iTQY=}@MZBU|zO62^BPAU^aBqMJM<CPMC
zTH8hdPbH678_GW!bk<^ShJ<eirus@1;zvVb3sMHK^i5LJX?EMRGXTLh%Rk~Dx_=s5
z=RmON{a00A&st*`NgE)CUEA@6(68BfA&@GdnbeXm2L(j~H1^W4+M)`^u&3#n&SVZd
zd>s9rVf;z*Q9EouT}3Ksc3}7oVS_tGDpf2OrD{q9&II-prOV~)R&u;7t@vAy(-+C8
zKKS6zRJss13|b9Ie|^oW<NFBhA>?vt`--~MCCDxjZz<=mQOzCY>VoE)%t=0lU>E_K
zF?qh1OSxfL9duJG@RFI7+7M9m0ZUXbvL-Bq)=+DG`Sie8D1{Is7{YrcInADb<H*l*
zeg)4c(UH6ZLK3P->nr35<uAL%fi6!#B)M6mb7bT+WH#fAWD1=`GKqwEOFareh$rw>
zRpggVb(Y8(U@C^W<XezWQW~2WYFUXc)w+)9%$k7c02$dJ30Fn0Fj!qry<aRZql^}-
zlTy38xqZKkCu8r03q2+v=kPAJl~BuJ$s%B*p}-YqiP~UQ@b%U_SOuAk0}?w>2&)j1
z1ZBWzHEGCkjjy2fZZnO?1oERtLG^SGt;Y@NswB(B`NyzLgxrc7L$#h%V@*cTLz~tk
z1mF(u`m_HCvj{{?L7GnhMM&x2$4qIPNiQ=Ow?)uu$CQpBuQ|cIBrq+4i~{h!>b7Fm
z6#{)|79>}fEUN<gvRRE?M3^87@bO&(Y;vo*QxYHoU)+@>T|!RtlVlXuuE>UxiMbRX
zwMAumj@NF;VLt0!ul)qmOcW)YJvckfm?Ni$LHo5g%azxBUhYgKU<rA0u=3agSWtkO
zu%bzaW~T!!f;jXKMKvmalp6;WSt1%fAPHeP(~*66%p8;J+%z==Ab0RZ<qFYi;s@?`
z(&dKOhapuy4oiixJsom_H+s}+!AW#R0God=a<Yi9`N-kQi(h5JSk6_&Qkp;p?X??$
ze{z|UJT2OdB?N_jA#5weSP@Xo9x^Z%1#+=!O(AiSL_Djd*C-&f;8?{Wh%BON&FRZ9
zS)j?!f&lOay(${g6oqf62p86vDNdhaDL!=zBBb(iD!z)tU;Ft|Yl10Pk9sdKfe@cg
zpFAnp9E?K6NnVu#nKbf2^ra?Lx+AEBvyA4@nF*2@^FVB(C_)C<3f&1(7&5E6Cvn#w
zVwabdGse*e$`7Gh(l1Oe%q4P_cPBvX=%+K+x#VVu3iu9c=`qOu!H4D&(6IMtdhXm2
z#x=G`B&;X%5!Em?XHfcqS4}9SgeU@6Nn6R?w3y*RRuE{~Buh&hPt+)&F4>pp?Utq>
zs~CJG+z1RY=$d_nA(N*^aG&Uimy?iHi!l>O2fEKpsH3NBqW?b9m*7vnpDBOmZ-11|
zO}O<!oyF2EsymYFy><D^u^2@Q1bAs1R;FrfwCt3qic-rbU^A&8vMNd&XWOLnu|QdB
zQdzP+gFT<o(7VjMw1{+WMuY+zFsWLt0EJRF<1|4@++pPBIu|b80#7D+4i(Y!Smpcw
z*N5pAl0|vaf3*BH6<g-Z2XjI({Tpg7+3-OoP|8Se7a(*ZClmoB_m^)E(ag4pOpx?F
z&`<ge)W2BIhjXf<WF%>zEi)s#iLNlqN8%uZ$}_2@P*ci(4^6-<*3>DTHkwixMoh${
z@$LFk2gzC^`piSFJ;=(<Wmq)h4rQtKy~=E0@a7SM=8aF#BbDl_TYSG@o;0%otSpi_
zM$c$%23|?k=tS6%KFirFJ)x+$=K91xfd&LM!Z`>ZGFMwZbk}GaBsL%j<QM{uVk$fg
zMUU3U?)__@pm2_`M8frFDm7&Q^XmS*5Y(cIFX%@-FTG4O>9K^?F3Hg$mQn0!dpe?w
z31~gYWhOd@WEkfmf}%B=+|!m(NubWacLG9h5^CTQff7_}SS^@B0>n>wh6*_r)h(GC
z_c|-RUH{9UB2>UiK-8nQFf=wkfimGq{Fd9GfiV**p);BcB=;k4E|{Dj60p1gP>?!g
zccQhl(*;Or3Y6`7A<~#u8Y)CKH)Yjhm+GyrcvHs0`ca;mUEPxLR5!5iXO~XTpoW@a
zGMO^w<(pT|TI1QBKhKiCPs&>U03t#Bmtz(YU|}^`L}qm*DN~m<<{6mB21cln)C3wH
zV2&ZJdlR-w-fOgbM1BG;yzmRVN=IMeFojA=N=+fAf!dQ1XeBBYdScH=VcD5#cz%D1
z@mFeHwZx;Odn8B|o@Q&c|BYWPI@`tU1v^<?vyNn;6e!8=BM;S2R!=UFx{kWa`1J<c
zixkESvXL0I+)-J=5m?RXgm8Mh23Uw9lh!a+X^vD__&}uyiV;|V<1$sU{fL5)0>-}?
z##k$+>TXF~cm-N*fCkQ|5f%n+hetX+Q>NLUIY)o}JXsT=WbcLUkA%OC;*;guuN;x7
zs=QW>DFtCG2%cI?t!=LuaT;00A;qv8(TgGgVCM7*uwYswq&C;HD&`Z4Vy`F#x;6;`
zSY}m!aacZNatH(nMu7lWex}Rf2dd4sfhkC>EP*1ae`^kq=>QGQmtQ2pD~nT`GS?l5
zyx|9jZd8LrO;JjR(ABd|id~UAR~bV4ecQT_JV3pWh^jxx>Hw=|L_P<+iuB})o(qLB
zX4%x}%A)FaTF6RhjKO*gcg4AE&j&_f7o`IXC^yhuVCHd?3B{A-O;|Vhzp9j$1{9kg
zJqHH(s!tAe(k1O=k-$Rv&V_{tUqI+y%p#J}0|}edZNyscjr7T+rdu-IgW%7@5oFi|
ziUKbiBwStLLM(S{lwSw#DfnzZjmAmam<c4XD5G!>d(|%x0I=hurzmc+1TS-+X+-tD
z^W{&F<pa_`dR}QA<;)J63XiJ5ILsfSodQ-lG~yAOc9)us0uCPhw%ma|Y@~t<5zRnk
z+!>v1)Qxsd=2dsjbhLX4D=-vKhCN_vcGpEliBNLqYrDGxKsV;<*fMOzDiCOBoOwz(
zIg{q)@>!Z>f9@+JIwAzTd~m_5rFa3Y1aX_O#^Fw;(R{wL(0Cxm8ATbnB|hHX*(S+=
zT|kN7?+y%)&#_HbieGhDe;^aeA8UZBaArewtmAyy=+C_yRVOgH$h%6$3?|yje3msV
zEZzVqz<p8aRmd8je)<x-QI-4EU`RE<0@!<RbIAbrN#tpvooS`dd<rhgpJ^5WQ4>}d
z_FV&;V5(3@h><-@rC7Xp9uX@M6*B7fz3l_Y2)p$y<Z6#Oh7ej7h9q<``f^<G4{8}I
zoCEW_)KO!DL6~fj7LnE~mu$j1V}=M1QE2xnc!?Xgy+wk76o?iGvhD%*#ltGgV?4x{
zW-3NuK)gyZg6Mgje<;CD%&AQck@UrivUU1H6o%_Y^oB7d{y?!=$HIaqf3C+%7>#nc
zg%ov{G!zIR=CI963!Ac4il=TR0(_P@K-1>F^Opny<ArYVMebiyMC!Oywt1em;y_HP
zO)`qMhP=+MoQoxlH?`$=kxi__1X&<4PwK`b7A|TR*I?0gb3vrQdVLaY7vn?@ZlMl}
zx+rXGKe|T89DQd3ec!xXr?X6r^Ij2x;MI_AJVvmfpqSu6%8hj-IOhbGS5g{y#Uet$
z8xkrlE^JLE>7|$vw6O)3uDF+&y)B@oB%{>Ex*yyWjqnKFLgyl4$vmI2?h`4U*+1TJ
zM9laLtRcg!1=^y}V;*<Q$}H;G(?S%9#kG*14;ueQ0O=yl`f0z9Ednf1@X~c$Zk~h^
zzo5GWQ}3sPER7vZ9}Yo9H+JDB_fX6<Ug>kcD>#HjD6!%dbPOjfh@$brV4Dy<NojEt
zOTdgHQV{Ya!Mw4fG+}KRx5fxT1Zg2|8iD`}<mb>>Fpn^=UFk*+5YvY6SDW5Z_IYbm
z1|-wjo&U`zN>m2hy+a<oFqRUv!bA}dWy2S1IGfRSk%W<mQLRrKPZJYzD8iTqUN3<T
zF2>a$#=3tQDqO13O%rTEv<TwEzLsi%W9(;zFt0*->%79))S;c|f4v1$d!SCgvE@jK
zC-O#(F~?!GE9nZzU~v#}CeD>_4VEiFgs`o3=2}9cOc0{$Ahq)Ql&DCb`o3m6Km(am
z&>9~O0u79tr_yMSg$(wb_n6%8{MNln0`ml;BNqSFt-NZC9)bHPc-k$%S)MkkCQD&I
zHq;7s6e2n~z2rcnkP+ib?KR)b8c2dm#DzcTytkUG&x#l%2}xn-RPjTUcurBh=y~Lt
z*Q1+HOaSjwXMEq(9NHHY!DZIKY^Kq60ZD=*h~<zi>PI4#gTx(3wu^)Og2<<pT3gbB
z{cym)c+oBng@6$g!#ru1s`pBWI<)!FvLfrm>wa%tB^pNa?2Ui(5<r|;z4IK8RkQZx
zk@*NcfemPIivlbT8`Gw_ojHH<ofEXCKn?AB3BPhcF59vmm=eUeOH~7hM2(9prPxkL
zw(}Yw7Lv(?Gp!lJL~?GDo&r&H^OZF&47<f74O4kcCI+e+<h3<2O_uj*GGAHqNYIE}
zf*nSZjvA7jOFPWzQ*)vW8uyP;(Zx#A+e?)S!^B4*)XFy$xYB$E6UbO$E*wl)A7in-
zXUc#6rx-B;JSGw57qJg^$I1~YWt3I=-2(X?an$le`Hcc*>sq%MMWjzj`ALID>Z4U3
znaK!H0WjDu29dyinKe*=6drCc-G@t_Cs$o6-ulj^k1+xTdKRPTL76tp?HD0wW1dh|
z%AAsTAhM=kUtLx*WZK9Lh*2Jxz^=oy)Eq#h2$e+XDsTjq5=Snm-xH&RyMP)jzKQ^d
zE(S<*k2=+gVxlG<{wXi?%ihhqEA-nDDS6&}n%jQs0~n`6i;c1zW-epNfF_B761Zrp
zC5x!EP)FCii3vKXtu0bAT!dh8ky6FXj8k)A22>9<_z#4GR&*CLL+b$ob&(~tO2yUJ
z@Zi`Oro7zPc+D0VQ>~iy0*}?;Qamsi=V)I@2(#1%L~jC`i0DwkDIyi>HYBZ&AHc#`
zlmW}R2sQYU=)rSeI(iE@8L@?RxFbja^*|^_NXGYK)}`K6^wu6vF}=^&*5`lwYX`^;
zBJ%TRU-XWMnmVu&-T>AMY1&V*cl0^KY2;v}OyqOWemWhPa%v+?c35Uec({;!b#QSm
zWPlk#g*|e=)+gx*#tZHCDZgQWCeydUk%VY>cz@@=AlW5`Kbn@$;TCh%7R;T87@@+Y
zYyIt|78s`?XSXlOxC2aHqWX~<H*vAH+m>O(q*>>~PgrpjX_ceE1P^szd!ZPjT+E<f
zZ-?lC!f__q)5}a2{^*ULJ%fT{^;yT{+#%*OOV8D7ZMA$JMny=GaFl=zAf_+$$F=i~
zz)SO(*HNzniOfol7I4{^90Z$h#<Pktz$H84_QMRR1Y6Baar+g_B+ADMsZUY3;+elU
z{_J<=TBs`<mcuUoR_5V31poApHt<vp=KbRi;H7TXZuNpjjk}<^lwf;@b()Y`^h{=y
z;Xsb^K@^bU|0-9?sam@e*bQ3cRB5U)h&d*wa+Y=1U-RDn-2-sF&oj5Wj|v4@V1xP-
zJ4ueX|FloTJS#MDn9PU-8-ZY}Q}{#q2}za1bTCxfgJ4rJ0r+Vi2eRY`q#`iLjE&f5
ze{qyz!6u`Om<Vjc<|S9Rdo&7F8P~MJU+PfF2CsX?bLY_a_YGV=eDI16%0Yd+HO_1e
z4wbJ-B>|RW2`s~v0l|2#^?F}x0U`#lOW?r*4P?g3*TsvX3kWDHZg0(3EGI)jyzB-(
z8ivz=TQ@xfy^_83`ya03fijRFE9Y@FA;IX-cto3iW1POO6hYt7;s{!XL?groGwq^1
zAo87*BL=de)+h_tz%W?l*H1Bz$65hSFEJkuss<36tyejU(Pmh~zM%UWth(`wkC&E`
z{#@?`Ej!AB68q~3qIzs3yt-||N3a&{dNwO>O|OV5V7O4v2(e#ksR}f}E?Lj3d8;r$
zE`?zt8;d*^A;}s`EEi}^3{pm6v#VAkrn#(_n_4dB)|*SeTQ49BguUVr=2~ExC<i9s
zZMVJlpfQ0w*-!$=JhGGIWf)S_6*NuLT$3eRkQd0bVx;*>3?6onOuIOzyn^-e$iFl|
zq#{&I(Jy9i^!(Jf?U`rNe|WX7!iBVjH~I+QizCWBxF>N+EmlQsu;NA+QIZ<VM(6et
zH%kzy16X&Voe7%Y{jB`k6rhc~WfrNf;7U>j=r+)iPto!PmUOuk427>S<Amm)^}VhF
z*q8brM@CC+?_3!J4x40}G-enB<b}rPCT*Jo7AR7JSgXcbSxTG+!d<``(8d7%2H0Ce
z4XYGXxrBQHutBxC@HFwNvV->S;UzW+IkT`Iu6C*(VXE2yc_39!S@!3cV)1a-CC!88
zHUEI-+bve9qGq8s=RD&^YUs}Ril29oV?AwE09e5CFVgPyO~dQ`<w3GZwAvZn6xB<a
zF9x`PJkcPy$z0@Tbo8Dfr*8Y6hwabg;+LhM<b$iHln#WU+{x?t;krW1hxA2dk=HVo
z#?M%9!^ZDSSBubDmIgVKKKHni1X$1FI`c%n&g_s*$F*e`D9dZHD}h9hRkR3lnKP2u
z_Qmt+?K`XFtUJt#>ptk=Bz|E%lP;yM?!;1yn?We(du90qHi|5y<T!Iq+Kjyk|6%}}
zkqv^lu2%E1htd|SB-6WwH+$=RtY(47sR|H+5lQpbmP&fheTc%itPZsUZef&m$@`l2
z=pA_=R<}xl{-15!ZN!qB8~c5XFbjh0i$#x|C`*;`;%=L2L1hu4^*!1Qhc)`n6^PN-
zo`J#0FEYG&;S&6}4n=m9c@^(6n?{46<i|a>x^tXd85wFd`v-wvZ8n+bN*8<?UrgE#
zZ~W<h@*xr&_*##dMbp1NJ!;Gu7IB98rg#17!wXc#$mS9jFoke@u|>01qsSEFvs=1v
z+vQ<798+EhPR4~sfr&NXhNT`r0?pH;AUkq4fv7Yd4d=={Y7Vh<k`7p27*brN7)>K5
zjY?K*uV}t5XIGwz&MkE*RB=`uep%z(#gkJnyRNwN*0(Ym5LpD_kIwI&-}QFYKU?0?
za$|XoPs8$K=3%B#V8dEVpd7Rv8MgQEgSSEFnJUtD@&E&f#<RBZE)$}(-9v&=yd9FX
zXN*8kOs^hm9m=MqAOqf><+c$+)f-fOL9R51!2UoQxeuJ$>6uHnI20(;N@a~{^5?vV
z{zI19#Rk85?p>c*^1o_wIiVYDm|tgp07Fv^Y6ZGb04)HJ#er>Tk^1IG^S&=*THT8q
zrMB8FHVWNVyG1K05Gj0}k|C2yDX^$&N<tFz$l6FV7l?-QaNyZcP4P<k+5OYYw$SYc
zLDs!R`s0Ofr)3s-!wr9a^W(`t_O_3WdN;&K=}UB+P;*WGGGLfNgE4N(bZZS0EhWXI
zazud~uWPiCv@}GYYH?PCwbYCN#-(>yOz*M|QfFj!1zU6%DOZ??`~b!;D$~P&Wm$cA
zl$n{O*jZcVAdZ@1fOs7}g~Q3zY>`#YGOwh}gSk*-JCpp^;r5-K5eJP{R99h3O&4GB
z0~dmpWc3h=r4~(d`2au1(k1&JnS}b~m^Z*7Ic$(ccZu1)0E?Y)1_gb_j*jf;V^DAD
zCzpwTu;$b{xsl+!cit-;!W1aoM2&a(3l1VPMEL$14~Nzyyjz<$|K-!AB^E*`X1a~M
z4fG(Aa*)YocFpsHhUK#ZCOa|9jwBsxdoDGR10dELw1l%(z^0fx90H0-0jYT4Nvm04
zl~Ow1rJD4S4iB7#dOBTdD-gE~Rm8BQI%fpQ5gh>9^Pwim+Tmgdd=4BAM2&!k_zCy|
z|0`tjo?{yG9o{#O{!qe&irqKAzR5-QS!(APu)tw_kcC@_AXx@Vpa7(T?~?H3i$3sk
zNV++xZow!eyF_|4>C=KomI!-l`OjgNpAaL8YWgM@%foFP+MUw(ghz(y1mCus2i7BV
z(s6~S;El`W@1}w?*Pr~SR6VxQgg^3_lC*Cz$=1^>OmR6E{1yMp)i1<gcbuA*6jF+!
z#00y&ec@4~7+dYj!6(sckOr3L8a1e1mozi?c_oDWT(xP0>b%Rbh)+#|4Ote|2m~pj
z#%<)&i7A&&Z)%i+np=bCu}eq`=AQJ&)}#Bq^rfF;-eVRyv^=w@@-V}kV|jASKtqgU
zw?NFAq=;~~?yfV<3qG+{Js<-?Vn$t$W%?%C*BH8@oj>!eH7QCY14fm9A=%L7c|a<R
z?qG1#r4aZQq=AZf9$3|5S_i7@RnDYqW7*+DXd?sLjUF5mv>FGeK0<D%K#mkz1}P~K
zaApp>IIG34UFJg%k}jQ@Kp40SNSDKdF`z3t9GLIF{}Dn#avL_?pn&26cA6K3=L_Yt
zz^#-Jb^2}A!~@*5%P&59jyNYr%jNRp3qM);$r#-x30|MTcn$g)whXH}I(uzgU2KU`
z;0>BDmnZ~lIUprolzG8*2c{}qM10>4F$)YC_mYAGNo<m%i%o2x7{sh8?JTgRn!r_0
zZsDJQnw71IeS0sGdr9*!l`*s3$+#z#_F$YKfnBXbwo?pb0yVugie&qAjAZaB+b$9u
zW4)Ahl1+4xB&10*xdUZg;9pPqP9>!r$kk5L44Hb-QEiM)^cKmw=2eekmH$qOInN4K
zHOc?Tp=iv87WT3rc}it6;k_tTK?i7KGsvQg!Y_iJs3(!B>Yh-)WripM5v!dG+d|oi
zm?mQYGnlMz@tV<9o)yZ}Oz-;{89i=DW}O8QY_m^v^&cP5NN`0+^CU+$-Rjf=v@wuv
zBa&#4?k37q%@LbLJf+P5-KbTvf&}&(;l}&3JONCxf~9m!6|Ym9MeRs-Y+fK04nvha
zP&}Y0RvB?S@j%2;P-8#lPOHsVoa^V$@q|Ojy`8dN{$<UEZSl%oyZpP5%SKfyNJb><
zgVDFg3w@nP^YHQ2ERJhBEa?}qunh1Q)_4;|#@Hia%cBA8G4`Pbl=Agb_Y8SGA7&9C
zLn*8ju@K0b$S24{pbZz*{g<V*A+43K-v5axAxdKXAe3M~ffO}Ree{krgYpkZogfs>
zfzz^47b7uJT3j!AG@V1Pbq8EixnHh^@~fIa+!I>?6*VXa>gqD=(t;ALdn5ozgxaRa
zwdm$2zoQl194leN#DhkYW|)M!QUS?X#FY`7axI;Wibi5@WPrcW(k50JbXjE)$%K>Y
zu;u}q&*en{7J~#|tVB6Mq3TcsoaBU>;f<eq+=(Jb5K^7s!!V_mhhBm>AYNmX4|3oH
z*OdVlaFt6M`Z2R9nIb~OU@@_2shNVqlz)GQE+-u$P<u>hm`~B`wj#)`a8@_t*k;}t
zqrQzTTdzHa`446)2Kxmku|KjQ&hLMUq#kst!Je2T7cKc95dthZxXjXzj40MSsTYQA
zP4A=9&}d=|wzkO%R_F~=EU;agVsA+l0Ozg*+h_GFFIf-rT-t2snND`aK%@XZb$Wh>
z(kXIWzSfDAo&eX8lvn>J7E^IpEQh`kJI!X~F7r0r!<C<0ILORAh6SEM5o2p{w=OW`
zsWDn3go*H|68P=fHo>22;d6i#t*50J))E1GbErPGi5-I&QO#g$+aD?VOFD|LY|vNR
z%#|CI;!!bxyE<+9{n|&U=hbZ=-f&U?I-5cgqYLj2$G8Ru;O9j3LX<ZV<vVj(z~ITQ
z;5`O?Yz>LkMb-)FBWDDkiW2gJiMjQ)Y-Dzs2Mw{9VQsc8iG$#2jf2Hxb#eh^NNXxt
ze+z{N%v73YcfRro)-hDdR~rwz&fU7QVm8C1XH-!q9c{1?(T%c(7C8a1){#yueTF(C
zVi*QNHoPf?ByIBXhG;>h_*vs)JSgU%v6?=}?lk?+PpSm#46iz`$^}$lG$NKR(1H|J
z0PVSWBUK2`2q?1wVvL8d*>>y^CWFL@3lSKH{L=aiG+7Iab0=^NNO34d#^=)P(~lhB
zezl?^*R&>UjDiTx55S_i>k=pS?{5%9Zih08n!xDz?AsOZmB^L%Q>h$-02vsD(T4Q^
zK}b7gv>>2LiW_U8JS+nKZ(kgf8d@`fHCLbUXoUxb60iC1`oZnNXAL}Pke-AmByHiz
z%SKwt=IU*x@{J%as3)$=6Cjdp)_f$FpRO`}Q@fXG&RRyZHqCEi1YkxL9kZLpg;qls
zXpUU$8JFp?B$~5}mk?wIRVrA&`Ik*BfovMmG{UHci9=kNwV?4Su%&@OKq9<@UqcDz
z(k|ax?xs~ykyMSmJWiv%6R99f6ro_qZdJ)84ZEEU2?u81lDEnQ^8==0%o%dNp$W;p
z3JY_WFDi8Ar7#YL-ux?1N@T3*Rs2r;@;Fnm)MTtLeB?Z-qXkvF3Rnv62$B9Er5jKx
zMzU@cj|0fIn`DYgO=U}-u~Y9+pash-(b{ntUDaH2URrY_Zi9aWMNqiu4v{>^Fz$5<
zE^>Rs18J6if83QA=jMT_x+vV3R+u<gdC~{<i<#Cxa6i&xmtB*3v#qZHLGo}VFMk{a
zY{cfe>S|jcdKQ8|VQ3YRuO4wx`zP65tDu9n|B*j@{}S1@qBOx;T3Gm*|JjbT{n*F~
z%s=vo9agOcM~YdJFxsFFLNm}t3U=Bd`@tgdd4{<TkT$p*b!#ZyJlw1&WhyzIlO<1I
z(RG1%@*mQNJGXvV5JrY*Oc`g~wn{53IH`e^twdLb8;DHJcL01m<Bk9-C?)Sv@DUJ~
zZbiH{9%m%$e2(D)J3x?@TlFbt3T+ZZVzICP2R|W26z<bzFRf8wSopWBG*UC%u-6iJ
z&~alC=x%$@r7FN(Ap=<<1q%`mcjT1$sKpSvI^UGnyNYTx375-%=PP5J9%;}d7|AM<
zy5TcDPnklNFx)f`(A5b}(Rz&5zo~H?CufcPUc478L#w5l$+(dy;c+TV@ZsKA&YJlY
zNKo9_W$2N{chR?*Wf|w8FQ#8kr<!(|aImU*^m@TKVlavws@WCO>&O2dH^4()^HC9F
zWS%}%CG*0#unU`n{E}(4=DzlgU^&KliI#d{yU^c0K=xD1d9HB?Cl9%pAJ(kvv}J*u
zwa7T$qPnHY4^<?U{RUQ&=4Lf<5H&@Y^sWj*$CK!lBD$hAxHkMZY~~IG?BA(5q7TQQ
z0dXs;7X)1<b)pfol+t5{eq10XMe>-IbuC2^nM8P|gQ-Gc{pl?`8GMgV!3v)TwhZN0
z<UNnZcVf)cjL=HWWqskJNAr*_O+WwNx`>7vqo4QfEc~HQL!uN@*?uBgMPL|*@Dj6}
z2GcG8CV~y?)OA@qq4E}uwX1OqEunub?x3vX{)R*d$HT<Hhm?TNE3~l&1{bWkrOvm$
z{xOs&7v(Wkxamb$#Cs4G%WrcD4OYI1OC@@(7I#=+KT42b8`2@VsF1FSFB1qK9WT_&
zKPB1tGaO0h5}7@l|3iOim)o&OK?NgZWK^o<SK1{Dr2-Cu+ZSTkKcNgt!WTJ=fzyRD
z%}(Glt_9x;+;lai21XyTDke8o$K_KtVqHLmi7F9Z|K;DywU}!N$mE+s5Y@0{NnpYI
z?p{ib4$JsJ8pVTx%AER>AOjO&Ran=zFI0E5Arw*|s#bn>5e*?|fPmt6S6uGLS<Qi}
z^2d2z2R{b<RGMr7lLezu3{02E+Q(^|#$wRnfu9Vtn+cgbbAuHMlWm&_)p}X$EY{WG
zgaXzA*pk9oy!))U1Wzo9BmAp1B({*^9Q`Q)bQc0$_f!wW2g`x7=GpJc##vV=g72(c
z@t2vrtS^-7_TbUoMkNPBmTbhy(hUuxS57(W)$S%60dqVUP{MRDD-8pEO5V)%+~sRX
z_wuk(M8@?l1Lf9L4Ml83xTYPDj#5zqpR44Xg3k+G*V3I5h<*Qm|5$D_6%*vMZuimt
z!IkQ#s>&BMFaUxkQi##1_m3jBCx6B+L?GFwCzC~NlMFkf+6xs3aYS_FO|J}$FgE-{
z1%}G_evGX-9eiMFg<G=Jk`y7F1w`Q*uK(GZ^<hK*f?DF_sL{)hjBt~%?r1|P2xk~}
zIcF7}&@S#7uPP8}K-g?Crg8KE@Tc-r90AT<2#G+57_r>?<ime#L8f(Vyp<H5k1w(U
zp!KTgg#gF?i7*f-Y2!ebR`Gs1=oT!vS2{yFiEjntVsN<1d+H!BFQ<#oXXo5ySSVA%
zwfXIHN33^{SC>kvQH%ShD@;)^3=kEgO%Ysz00FSC(Ik;>7vNr=u94}Hsl)u(Ko*=h
z`V>YWM)Fl>hKAHfArWq}o86n{FKj%hBf0O~9FMCi3{4izDB^c4wqg=00IR~1YMQPY
zvDP-aM};tnkhxNrH;l)u<Mx>Gg|Y~=_PslwG}UDQ54-rD68x%DoW-w*eIy#2H*bGQ
zjK;}JZ48f9q?bI;wa@xL8I#LZ{T!Kv9kAeo*fft|*@tz?c!o(r<rq7)I?7Z_HfsyW
zo|4p7P92#q%c6Z8J!M#(1E|kNEGRpkU23}W8Z!IW*Jioz;X*xmD*8PN4->K0;2Yiw
zGYa^EZ90#(Nxqk3%_f3ym7XVx%yDKJK`R1wtpkoAIme|fc~eSRFlG#<C2${xQ{Kq+
z#~L++I;&D6vwaH!s^9vXKMZ~Q-R;A0X+$IinChp3n#9^JTrACk%Kek)!IG(gO%&K|
z7ilfgqjm-uLM^M!xM;h}Fp@SR(kdp)8fRJ7A0TuYhy<a$W^+~|d%cTVPz23$u8%)}
zY|+g%61Y(_b_2~*R-aNF&KTPAjlwUcfXJ>%`jGS@PY)UNrSkGbD*9vk)RSXpQb+?v
zAA~_w1tDt0VVRY%>dJcAl~UgM8C=nj1pAN$OwW8&c2GjHZb(^SU+d6A$~=I_uAT(4
zge^n?&|GEJ98KN;x(a5<7r*b?1iFF=5SO<t(7tMmnS^%G{x^P!7|V8u4)tC=*N@Ny
zF8$_u(lKl0hAfa*;UDx%H0h&7>G&<9#==*f8SnPe3Mni-qx+}*PJJ%<zrzdYJ=`b3
z)$ZN-dmmzq^9AW-Z+PBBJ{a?d1cI#5M~X512`7{KPFh5kJm^OD(mbVOiP;83)YK}_
z;WHhM3D7VQnLF(=%@u?9K8ENNh=g7Kl1FR;|6`t6KuDsZB&pt~R_r2JQWb4XDZ^>u
zVymC49-++EC`fbi9~znbC?J8hR%auS3!}44p%ROR(r1iGY4>VRbaZ6R5EviZFw?tw
z1Q+=og?BlV@(W6!S<g!eK~{|57|9IJ&(+$%NDQHiBIw__Axr(daP_R6nME{mFn>yv
z$gMu)KLjjc^dv9>_p%mw)lL?TFa!L|qD(D&LrKK4@bsTWlv<qh>?|6_QFzE@5u(so
z-(sSLS(e=Wlc_5qoCb*VgE?j#k@`45TeT|w#twO0fUV|>3|CySdA1y_Yz6YEB+e3<
zDS?p>uv5=TCZm-BQdlLn!CJ=+x!2NDVa`nmgz4fG7bi|pCVCVDjM!O&bTJ$X?c+zJ
zeK;J_CDfIhZ{7M~Sx6ZGN&g6m()1eHSXx*hvI;PgWM#sY@njgNl2K(CW{7Oi3X1{-
zue58ur~2SiX@wPjH={PD538nKZ(jZJk4VC;$JN!j2uzT>L;W%FvWmkEJ_wB#9fzey
zY<rom%%5D&CzHk%B;+Ie$EU0{!VX9oeJ8`&+MYtuEkS?lPd^OvEyt}G<!CE!)8V~3
z8-UQce<&gN$P-zc5)4<eF{6hLwM?Y|I^Z!m10L!{rWU)BuR&{<w<iAC(oCegpo@_S
z@;k8sm3`)FXpW%{5Lb6Ef}LcPS!?RKA41Vbf#R+W811v6^Tq@Fu4iG1MH(H&3&{3x
z%N;1|3T@hU5KTNM6N@G+?toAjGg^YI^lzBwL9C-M910VP$aPo}Em*X3D^-xSV37la
z&~b#c=-mRHwhOhGe)>;Et&;N)fK;<KZq7jfY4u^k3PaRLf=FhRbANzL*ti!{{+8s;
z4F>7<0ahx22P{>$ZdH_AY)*lV9v}i{QBEAXxcqEtTG33eJp~w+P6OUV5Mt6#AQ~J^
zcKzR5v$42^-@}SW$kGG0E+vA=UfyOtYfiG%Aj8en0Sh$qi~}?H6vpH)r7wV710qRk
zlSN9R@*(T)@h~NSQ5ha-n_*Nlz`*T~{Hn_le3|KG2%Zv0J6Eu8^4h1E;j3i4$~)ID
ze;RqKOBsMTHn($V42l?RC<E2l9eTqtp^c;m(yT!vC`<Zo%MYtuBufPgq<82A&QHJZ
ze^9w4`Dq~=cF@C!RY8}WPrvjrRALy8+OSw)oSDz~V+%l~gdBkn;U#zUK%AHe9biQs
zyjjNVek&ViI;oDRFPmVBW8X9LC>;Oy`E1oxxO<dCmI2}+9lIbbo@T%Cpu<&OW<ZTL
z<#311Hm0IxTbN+Ukt$kSZJ`~w?xY|SA$r#DZ=>kU8bH~LJO_ehOgU6StZR<GY&5D6
zWe6AS6*-Q=Ni0ZZ4>X`br0#UjrxDcAFwOP;@PDyz{Rk2?DtFpq&*U;GTx|UVJPM~~
zu?tB!iPR`;l^hN6ov8(i!nd0s86o&4k5T67SS%wpls84rCqyDIO9=r5qZ!z79ICn%
z%PE&50Lm-CTYf65$1>-cqEBU_y7xcIM}$Uivkz3%Y-WYdHZ?{6jEH68WdUTTfXiy?
zP~P{crF)5D5SbBLIEr+j^fDIk#-Pxe^<Gbp8hV7B*=7}INw_~i>>eZFDo}=2HaH)%
zL`TYUc>w$F)pu_}yzEmce~_*AV8+*mfby4^J@Oa!?yV450a%XBNdqnd6#_$;K@7k~
z3c|Hb!wbek6@v+<EJLS|y!X=Lxg6QY2|*lPN%=9TO|^2$1!2nOrOvPZiJXEh0!cS)
z23AV?$Rm#ci|h-;A%n+eZ(eV9kN!F6Qu1DEc9#YmJCL=reaSp{+j=k@CnhfN_dlrF
zS;VqFz*d%|N}vBJ(#Omt%A_iPCy*1c>CX3hCq88>ayD&av6>)kj)C&iJ{F%`3DhjW
ze=`EKrEAI!LtKQ#<fNz}?vs&Wj5JWvj`t`cyM#YyyNfW=uQGbW;E|Nv&BK2tG%W}X
zO(Q5<KD_Y2f<z1=Mu;}&m4dT;L%8;j;4!ET7A$Uq?^{ra7!QfcO&JWC;_@&`5;i&k
z6OjY~0s>wrgEptyY(I^Jf)a26oaI~p4AJ1m(8qnGLo}<eAvLhTk_aa_Fy9`tbXnR-
z665EWAWMtnsa1|K5D4MQ*47epO9|~rl6M=OLQ+OHGC(o36N67zD87kJV2J4dcfKkw
zt{#83a`|xllOt{*<|CRQEkA(w_vmJQf%O4H*o9-fl*bXbau>kGN;yq<_xGg*l_Ei$
zVAa$z2H2-X0(l}RB+<`9vB$vogd}g4XYJZiEHA4+v|g*8T%&b+@auN$kUeLZ=v9uG
zWgWg3FUNMLl}{m7J9v6R3{|{U_j$8gxneNJTDWp#ckOCfEQRmCp@o}#=54>r2;-hg
z?U@{END9*ITYvEpTV7O~g7xF-DA_cs_%ZF<Kgf&w6q^K7F%QF1xSRj1eLGnhjx}jY
zrfb7Dy=>{43`O3X9L{LA{fyF)xN4?ai;E*c8=kOpC0}`B*HB<vF&(4vr@x7TRh@?l
z0Jrbm{No>0ue6irC_x_rN<vG##us@u9z&|vP)qZ_Fl!c~QB4!VvDT(eh^M*)rJR0U
zxz#O;<AmaJ_z%J*?}TPp3E4+*E`b&iSHL7sAW{33swz+Dgh<S?Pmg~{Ry1!T9`)$Z
z+&aQLd(>+-jX_)XDHJpqW_*UWx0C;T-?6sV)FMXbLVB)FFV%A!Hgq$`VgkQT2dpVo
zMG*v0EXmr-rfN$#-C?J#j#m~gv*Z<NS&`f<UVrl~o3BVM2gS!uoHs7S(Ibz{i<e;f
zAwO+E^#iQ5(Zv9agzE0}nUTuxO}IHin^l4&7LZimPGE@|jl`Czc3>m53}p~-!Y+Di
zC*2^HeV_`-GQ<&9(EOyeH;@vu8?98o-B<~1ecmEqC7fmdz`^Q0(Lo*kG+Nq7I2gZ$
zsS~7RS`Xf)>%9dQer_n2$80=$uTgixG{cIchmoV|*yxli?B6we`$qxnfx<S;N$sIn
zzj^oVN?r=&L9CXJKEhHF_Sxmp=Yr1#xjcSAB4Gp>1J+9BJ8677S<r0^Xp+PtGBZJZ
zmzJxQw(Er*OdY^?0~L2!u)vP=$fbpjmN1-h?c3{g7**gUu0I3L_P+EJSRVKTJGH_F
z3q$i*)zyxhJoNue*rpb!b@k0rxdt&;OOB(}Z)hn7YlonVX$~Ft1U`%9v`Xl#{3;on
zTwz>Ff)u7Zv0FnV*^9aMHOnJU>=e6C{rAFZ;u`1<$*cLSw4^nx!KFtwst1>2DnmpD
z&@aIgO2<e7_4G|?^d$8&ob7-z11p75!@@vhnK&vtc*R(+A)_cml4~)RmHPr0P-Jw1
z8U7yxe$droKr$|jDVou}`PX@Jj!iNELa@$SNux|`v*Ax}n&i+ofZ3|V;?ck(GM<2U
z7CKcwMaV)ttBPT>Z5~6T9I)n_N!NJz7OT0qgjT?%)qDhVjR43xtB{1|9&<527)BoN
z>haK@O!+j$AAkOv96GXc`|CT5|1hQyLPUlPw6tB7MQvL6t1s^}=xV*kV#uRb+)xj%
zs*)wz;Jz8C`hF%KiQuDDUP*GT^59Q?v)Jh9DHij>Mk*udJo_g^3DQeDPWHJiwhT>>
z$~tqy3^s*&nOj8LmV=>(k&7Zo0hP1b{6tb*-R-%0o=d!CR(WhyCzs}Z`(Qt+0V2sl
zB~&@Six+bf3zp*Rv%A8qIq2Aj9g3+`;4BEqs$g!}z}sVSM0|-h@kzl96vNKcwcVis
zk&|6yEe89HJ~0^^0X3k<Bsp_sIjKTFP4keP5Rv+ww^>L%4<rMovZj@<@Z+&c?JL0{
ze*v+ekb%dPaI<j*8=%$c(<!mm21^0KPaz7;TFkW1pK@uucB`}Kj||X=5W6dm0nRQM
z%!2=}%iK9`fmXBYi{$JX5Gl=Wc~4z07pU*s_3Bh&urc__3M0dHNjsxMvc9+<ivId$
zg>P(7qWPw@k1wrb%&<5r))Cs-eI)BBY2ddpdGA3BS`XMQTeQW(Rm&XEQC9(;<r0%7
z6!(G->o-^aZ`R&EzK!EN7u{X0R9KZ$%y0k=VT#5s7u1rb6p^A_Mkh^nmb)S-QxO&d
z71&W6k|rG`&4=mQsc&v>g8>&7Sy8blQ>}8F-iR`lD*3r5wri*9X?sf0WGuIGBdPZ9
zr}ic%mg}^=w>>A4;<Reo-rQ$E*=c+F=Yc4KBo>SLc<23i-e=yatK|!)6~*Y)@keW{
z5+s9xc4P6Vx?Y&13iO0+V30=q9S)Qz+{!>n+?suYwq83oMR}%bL2qqT?)fRJq=KP$
zF?1+e)tE7qo&i9mveONVqQ(lsyL~5yRDC`eK`<wZ^JuSmUT}I~^DrhV0*0Ulm^@r-
z|Eq&kl*Uo+ZXJuMu%dh?tV-9e8hF8iN3(W}3NYWF&YXI;a&izIE5`@LoNXu_<+P$X
z2qBfKd4K<H4Zj}xPsJG;Q;=b|1q=$)r9#F)i2+ung17t?$G#QNq54J{5i?rUunVr0
z!z7`s9moO@R;;C;4i45b21UIL(x`e_`3F8WU-&TnYd!!H=fCmCO53S|&=6=<dqX{-
zR+MllIc|^!u$-Yf;RGrG7)`91G1whygTIQek72O`j=zlFVx9~bbQRF3_G5yphNc+B
zXs8+s<ub<$XH`(7>T&>1`cH2uM2n@AV$offD5S1P;2kgL!iMo`oGAz+29Z%(rJ>_0
z1~jh<E|en1PuQZa%v@zzUEtybDvUlnADD7XjB5C;_a28S!hiq}SATRIwUr~5`0*EC
z!hmBU@M9xWi^%{pQ0aNl0wEdr``Tj%TtBrV7^QS!2v_m4Iu-*T12xewIhb}xD;{sZ
zL(3{q2v{GkFq}5DXR%g1SHldz6e4AD^Nn8RgW-|I!H_6`1m+rK^@GLDz8Zb37nQGU
zylz09K%?0<CIQKH1#ram)xbp1q#Tm0asuCO1?c>k@pl@5cf#1Utu3NkuVKAI87bm5
zrlXdB?4ar<Y#7R~!v|F~B;Xs3T(~o&6dPV`c;C3jw$CVc%YdZgT9{*3;aDht1Ou8_
zMHN46$3zd+?mShZ8)~P)>+unVsFUlk(egyY#;6A05*4TwT&6ZALS~;)P@ekLLj10n
zQb-1YYjN{~fK(tYEo<jZ8*52rh%MGFFd+rEm>4Q0BR0;4H?($)oWKTmRAC2wUkf3z
z4W)t|O8AHMpa!JfhXQLPl-_O%;t%}u{mV97#Ksp~ey}IXUqkm|wF99r{k>y9gD%5?
zvEi{Oa0O3LD|gsTfkDq9k)mQws5ywPQY}j7K@$KKv6Xr~gP+EHpg<}Q4p1c)*lmTw
z1%#TFcDF|*L;(H3lfhRH6ph`6rYd6o+MGgX{?8Yv(~vC0Bn{Jome%q&ql3zYQW*)T
z8l?jp3>|n~VYh>gr@;L%MCv~t6+?aDghI#13n;vUB6urEJVR6)m9<^X!|HJ>3PrQv
z_u;YD7+Yy^<=j*;wQYvlYlMYYbYXRsoGbA{P`>N0m1qApFH<FOfSIlB`g?;uoO{+%
zMJeGxAWPX;a&{I&g|V_RR&e+ldy!GobO<o<q4V(jU`;{)nKIN=!lJdmfdSi&OJSN6
zO1##zwMZD50mE&FC0n*tp-8po91@R#QhPDrH_Gkz<MPJR*OgDI#%h?PpmfljMobCY
zaO;K``G*`6L^8k^IB`<Z1ZpT?q<|4s5fzSuWwj|=m9u>;!MDc<vyXRT;9#U0Rmbdx
zVMV|JgAOGGpZ(%LHTvCotD3JWk@zfzXbmG!QgtgRge<|Q0<;bVjaD^exiJI~i8p-v
zIcLnrK<BafeHEeECed&;j=57xsvDNFA>Q}}giNKC8Xaq(4!2%j6M3~C1oCD9U1?~D
zhRz0`A^*+B$09R<7+0wZe7#d27Yy9B;~H#Lr3qkdBRF~+S!`U~&?$IRgWqUFxgkoE
zINlQ;Gs1FcqnoZm7||Ie`5kX4?BdpLYrF}|wek4Ztv+Ex_*9~Et6C`P5+woWYS_u#
zC|ahV^!=Yvd-iVy=ZYt+{yk?w(KM=hH@-WHZwbH+rcWhVpbr}yg0(IxeRQk0XKW}I
z=sWDG)j|k2(#a~FdJLiEzutehjHcY$`>V1Ow?^}ACG*bRR4?6sb>()L5Up?yZUV3@
z32U#AkIv6RiM&0Gw@`AZn_F86-^sYx(1Zxf6=4_a`JIozX#TV(U_nwC4e4QniNF?5
z#q^x{>Go8G>0ib_jC#kJ#uwxSVz4G97z8D6kYFG3i-F&!zSNwc?i%nKq)Sw-3DhRo
zr9&y-8gDe@goUp)@2eU2=&YiGx{BX5Me=Q=VSXCL8|ov5uxkkkBwPb-!mK*wTcWN=
zjKMhHIN7POewH!iXbalW5LPA5Z?F8dWzmHt*rhH&wfDv~Fv1=n5Ue;Phxp(8<@#GI
z8=A4O#uQM8q!Q&1D$uK8_mn|_W(0W&lhD}zfK9QW=)nh3uDk?`1XtXOuZpNKtbin3
zzBXpJ7N}|<T%osLT*PQW{Qwz;LwWPp|Dge}HENBj9Yk9cuGN68E{iHfD`4HAa4@Ox
zaDEDQRIA32fs*40iLk>3E9pYbtZS$Xp->JrRgHcA7Dh-ZK0_VDp@!%k?YK5Zjg+by
zA>}Dz<{O?Q>Ni+tGq5Cx{Q%D7PyO$zg_@Rq*g{!k#S_HILa=#Q2LT$U?3{XPY@dKq
zg09mVp--^nfb#{Q4gcc0V%RtS;Y`#<zzH?^oUPnxLus0Kw2?AI9gr!NC^FP?Hjrmu
zY`jy&21qym_U#Q^5}F!bJRnPW^lJb@3NVKzunu7Q8`c+%K8;utx2(XE2HyqkMR6d|
z6QFU_e!TMZGdKy!K!ea4A4<Eu;WWO@Geh*!7&HJHJ^&9THX9L~BdA4$|AXlSteQIB
zeQhnO(_c2zX6VC)N*u!xjz}Fh5-k`YB~oe>VG6Phd4eXzNf_`#(WKQ<9y>Wy85t~n
zG#WMy5pd)2woK!%jgdv+(#C!bR1AmRK-lEn{EPO6tKNu8Ra+E}yQTnam|Df*f<6QH
z2+B>}1p>QP2HfpmZWN5J<*{2DssP*R)gpeZQ3c#;JAqc<AWr4LVQ?Da<EZyH+M%|P
zSa!BLrcP3T=a1Tds1&9YfRb$a|NSELzXrd$fhoEeq+9Ar?U>)?^dtO4Ya0Fu#t`}n
z0&g_*lnqwdm~RK#imaJ%MDnNxsBBOH2gIrNz;9ESoccEg6?+<!f)K0GEZhc6bF4r(
zBSt%X5#$Y!ylWK4QMG$+E*xt3`lGiBd?OdyXqXD3mo0a&s!pX->K_ejz)rUshPEv`
z*o=?_aXc0=QYp|&jX(yr+gD5Vgx!JmE62yaWmB;T@CAIVp?UyL!5e@aE0wPDXh<c#
zd-i9PP{5w62Wsu$p+z{a7uE&MfEo{O^$Jf)SqjJ;HmRt3dqJ(?=pi+s?yDYPO5#z3
z)qdwqXpZ{J+pow4i42MI$slF<E5A6XCykl8Owte)fvqWRRU@`5-Bjb1ISR24o^x=X
z4ANsX$clW7ttway6|1UObkF2C@G*v3Lj2=uJGfK9UpsWo$)0fOah|uFtj>eL&&E}!
zy37O7R<g6Ek4W2H(ERL;X9u%$4BRoGLsYADw<m@FFqt;EHlild8Z<Pn#oCaiLtyPn
zU45`YA-8i((pYQL;jg(;PbPY1^<-7NVdJn@+^1?RWEX`)wX9`g%^%0P>PhCL49$ka
zBz^zd|0|Pb?mTt8jXRi@4!G{oE8M88%g)hkn=rjt&UNDL5^aziDon$XH@u>&h#VnE
z(oX~$l?v5%G^)lq>)VzN?~P8I+zZA<z7pFk7PdJU$LrLR%$~qaj*S220UR^2HZ7cZ
zdcpDx&%m5&8b%v`ujp$pLXzPGX9Yf$XVu?u*deY{4|JPCgtaU>ioa`~flJl+$MV|V
zs=5NLUZPr3y#d+_?icQssOU4e53mw-1+H&M6h~Ej9iN-Mb#J_~*18J*AS~6rwZ|Xr
zxvgKE=X^$o<lrq`lf<61AE4W;om5OhBPs-6sQ4y5E>L82j^n_W9UMbOd8Y-S4=y}f
zqk?It&V=OHt4`xtczn{5vZ}mLC|<~?VX2Woc@va@!xza<TRJTkKQ7PsozA=yR(tkr
zbv`jZKJGuD0tDO-F8B0}r=Pvm(EkNbpHHp-H+NCG_3cMP;BNhDqoryj-+ry}tOoAi
zKein?&ieKESd-L(<CIk9xK&K`k|6EqOEeg;Mr=+3I@QB)LkMr3ag<%K^shqPx-4<x
zy<H?R6S;DVj9c7^3r<|A%H{X&;MvJ;gG07=Se)`^OP8E_aUI}@IPc1*<UAkGtgy5n
z$9ij*)?RknO*-YAVDXe~o3=}*XmIm4ez79;IAvSLcve^jx3Fa9QW{-CThfuA9;+q|
z-Y-n5jm$xYENP)pr>)~%s3Xg8E}}N5qd^ecIBjTYBYnn_*{Ti!;Zz=HUOZZ*6@vPC
zG&Yl1AwC6kGJ{P5+#!iVb;j6ZxLIpVTx<HV$JV0?zgDoA)<*hBb4jELY?YG^412*d
z9?F>Mgx0TTt73)O0oMw99Z0!n3!@@3i6HIg0lC8~(mUP|ejl$qX$|UG!#ic6xIaMy
zxsv^gfeK#j&gK<A@SJX*G~uB6_Ml!d?7;Ol$~$X6L$T~fgvgnJ^_18|sHFvUnbm9k
zC7gL2#XKI@WV+WUs(NiM0Jl*K6GPBIL-|dP76&m*!+E5fp~q490g@6|3@qS=LD#sK
z*Yn&fl}Ekl*q?OaMg}wqZ75u=ZXczsfosK|pW29ZvL{h%^DoOf@!qiOEfd@?<+G#K
z4i@$>?xfi=Q$~Qtx|}6AQH1qzM-E+b=TIG0lpoIpr)Xfs*6@`@-R_U71NIEvLl66~
zSkeV@af<Vm8Z@_RpC&1EVr4YWvPAQEjF6H;H^4(9BHhO`#t|`dDQ^*TYAl#F-hcUL
zX|Pp@g~I43Xiyf;G5QL9IZ79N;k~*jrbkByCyB9*bVy-p;~I5lUX_BILs7Lq>RMt`
zlc<bk4#=+(+Lu|e;#{#jM8^Dd$!{-Jtu#I5#6wZOE<zLvi+LemkEz{IND_@i(embc
z-p|LP{{Qqk^}Ix24uw;Xla8}si2=!vh<<6$<%bx(`KOl)c6x;_)<{BF!YN5B7aXQ>
z7{!60gVEl7RG{K-+f`{4+=^w);pB%S&K=atoM#i~nF#4L3O=&$h`MtzKEdT#fnes7
zHtLS_&-&;4+OOmdyFGDXj@K{Fce}4k`zj^9DLQkaqmSR+DcrGo9tRbmbhJz*py}YO
z&NEFMcQ`~bortH_x&7T;oL`IuHLtZiro4ZY{+bmgi(yJwy`|F40<n*4^t4rpB$T->
zwAqrV2n1;`g<c{}pzmYE7O;@s^g3wpu#d+N5jb3#B41(NH(`V|_c+m}2nsp_I-83z
z*;7C&M^Fw`b~`&<j{3FQwc5L#<4wS|0%9%%F!l-D-gH><adNnt%#YhFtK(o*BWcu3
zXGJ(L_xu>!(f+#Vu_5p^(;DfonKll6OW3E?ED6m$Z6zHjftkz8XfNDckysLyZphm>
zK+}Yv(18Y@k%l)eU=+-2Pi@gemrh`9crI^?#7UOe!QzVQ;&Hly^H-_sC3d)4#z;c&
z>taC}wVFZs$sivaJE+rHchfOL;h|V^k0de%$MJ_`k!F=u-pBnOxEH7cEJ;Jd2HABO
z3XgBZ_`1Oks_pN^LT{Ev$n^*lAbSW;vIvWX)Xe@%kYx#tEIuaKMXs|#UTzg!vsnBk
zU3-aW{X$PCn5RpP)?flvhcubBY-pc4To(=Jc#YND&4QdUX9GDNx8`3b=A35x6&y|p
z8*dv~BX&IF)4z1P7ohqLw{U(h>^dscCdCTZz|IQ9rWrjZNj*hdFso-x-hwTv@;Dh3
zoa<>;mQs0$=$=BM>pZK#ef;DaE|&$Nc{=)in#G~DY>7(U(MVpC;cZzxYie3vdivKd
z-LCCma06Euik#xZd3IDlfXJ-A0^KP)q>gpyO-IhG4n?oLgjhR<>gglhBi$>Z0Q4aZ
z3_eZkcyH{+QfPCXP<vAba%fyj>+m%2IT&@dl45A^5g*mA<BV~^aG%)>*9osFRVol$
zLx*;eA(Gffgha1qi5VusqSY^yCJo^f7_t|tHb~O*?g;ht8b+baG%OBNrd+HCSv9mc
zYmE3=!>;JI)Ux`Evf704oHkwD5e{9ph^e_Yd92s#X0~Ux=!{UBU9dh%3NiKWleDG_
zkzR-W;8bIAiHD@bmI$PanG(<1t7viH>2Xa8DRe9z0PihWBB~c48`%uVvn=K@yuLs4
zc%XkdFd!FssQTozp{>}Om^#6d#!o)IzRMy89q~1f5*s&2>#03b!L-B(=3(-@pJgaX
zPKt3dZRQe9dT&x+)sul9$2A@CQh*WibTp))%!8F3yduyPFK=qc%O1p)SBRshO!QV8
z3`{rAE4GR8_*06OIKDl{RDuM4ErT&g?nzXzTLLAE&8rTGQ;2kux=hZH;(QI>g_aC!
zu%jA@lV(;Ql19Uog>F&qDABxbSB_AMhPV`e=)`*T5_vQ%Z(>phjrZUCvw&Bcg-PbH
zuRES&0(`a#Y5+A0qxrgpKtiiTG1by}!wX<{x<*H}fMW<Gbf+d9`x#3|VK2+HMU(%D
zDo&wHI*<tIC5WAs`Vtp`24O`%=tE4^YHZdqA5HMQ+Fc}-WTook@k_t+bE?9xMrjh7
z17V0Jh&Cf2-)J-HnV5)`lq~WfNvNYcnkAIrCe0(XCg~;(-T=`G5)+(EU_?-w%R*RD
zv6YIcm{}999Mrkrm=`$dRrA{UOtPD$o^wY<K*VM%%@LzKMA#$5WX)E@NG*7jJ=r`(
z>TE{faLkVG6pv;uU5yq~bhszIOvADtbU#^ddGeBsG9q=V`6W`AqEC@Sl5C~X-DHwo
z8Z4H-SS;WBa90G4$-=~NpBvNpnFHLNqTiVZ@!PIL-};A(gLZZ7a>k%X$n3ZB{$BFU
zEh~@hmnViZuS)656N4jh@_bInDcRGzm*NZ(f5kmAHe$1{f8`#V>`HI8I>jE=oo<fW
z(pxXN*5rG8h-k4#=e7WP+AJqN%jKno9zO6SO(&8M^G9g@Tl^)fFjl+NI%<7ll08Nr
zv<h+`?I-+_E6%4TP{f!daxEu2nlI7I)}@xBY@x5QqCA$nG*i9Ya)Vn#QS8>_I`E(C
z4pyZ+z-NlQ)qU|fXO!Cg@`TmuZsFVWN9YImF>%!S(gZukqI+n|919;~Vy?@7*?5W6
z<_;fqvS<81vFw4V{5_Wa;$*PwINv^EW}>^hJ0B1eCoHej(`<=SJL=4(ev78>D@Pru
zWc*mf2W0Kf#2K1yNz7Q$H&jK;(%m>&w{$m-QOHkJt%yfFeV_VPE)y8nl)17xXC0+9
ze9~$MJ~*eoSH`AlY=y+KGK%Cc%qCCsMCYiiySPxe+fk76^wwDB_m0ZB!8aK`Ip4S;
zBK`aUrx?$yIQH=&ludm#UUb^?ueQ%yUq7<3EBc4-ba`>&8$JG&HzT{7pZsk5XQ=*K
z@j$0N8HzY4|K_gT^=a<Bn|^Jls3mw;^ng_>zq#wtCVd~@#f;Qv?LD&i#qf7&G`)GA
z+$E04RGB_A8+~mXa^^352vu!{{~PIX!$V=FIQ>dXfn=i90srE(pI@+^uqJV?>~r?P
z>F~S2nO;n6sbx?WZS}fk?S6`c|6*A<c!M;(QT6-89Z|;kRIpbTU-__;`617|^lJD#
z-njamz&Og|bDg-pt9pa6(4jY3dVk<tKe+QW>Fqvh*ACjd$Q76P(X^9GU!E?0|ItM|
z6I}||*UJAgyh!5IjketG0~cxunu*>-?+#BuiGSkJt$OV~NLzFG4XR7BlsS8VAap8u
zG$LN{;Lp=z?&_gZQxONpbUxR20D)wjde*Yfkdv-aE5B^xtWtHB($1qK^|ZZvis-u!
zOcP+%@{Zt+U$#&0X^jfu2mRgX?`!|;IQd%n!a%Xpj;8J1#_Fcs2LkO08IA7`%#U2U
zy(_YJJ?q|Rp%Z^^TXMBzy`P{j6X;9yo?Qz&Gto+TmeAprHr%ZCW82!@pHD2&T>6J7
zQ@YT-E1F)te@};{I~_9mVi@D1lg(!BzTZ!wgVWmT!I?X;CB&JS>OqI1EmkKj5fnIG
z9dh)Ozh~LSX>_RYik&Rabs9J?wsxke5Mr~^D6J&`n%bUYuKt3h`Z4@3j#HQpKZjC<
zQ)1d)7jDWN2*SnS=uYR;!SnVT6B`QM-P_&P)?AUsaq2pt@^ceuBfNhAvn??bg-?WP
zI)2z@?fzj)3(j7NCUOhprK^wbQC%3wM$=*1Cgm`*0Em6qOYG87$hEt0;p{(wKVq=9
zWj8DhHz9XYD-&RZuDd!EN664gr0M<~0_MF&&g{hD+o=WnC_#et%+5kd^*3L)fZ?+@
zS!|q+3Z>>V-57hc93?TfSi7e%ClIgIP1hJZ9UQeY*Y|{X*`NOMyISdRscE|#ns<W4
z>5v?@gP4VrDHCsgtu!Ks4-|PuWtF9tE*?zjtA|8)!P&*I({tRyF)hd@G414_E^{3H
zcoGaxBYf1J!%`_VJ?9qlXk}+H4o&1$PLtY<Azy{XIK8u$*DK<z{lrvL;saJ3zYcr5
zw={jRWT3vrH8HWf>1IA}^K1D$4giOXQw|(!|4)oe^dLEE3y+k8T@cRz+0=4~g8(rY
zdMyzZrU@&YkFhsf3x*-*=W=M0J3)<ke13Tbe|X_u;!&<Ub9dmx*WzbdAS{~zn1?0u
z3<us-CY?rxSVkP-xLk-mQNHAQ95hJwrujF;;xEUlmBiL+U&RH}A4x9~)P$v{gVQ_F
z%Gaf!#uGpMIplJlsG`q{_AwsbM{=0<O+Y!-QdngV@$xrwsA{L-08=ds+n+!tdfMs6
z+yzKkkGByNoOLV+1&~wqZI|v$>}s1S2Bmg{H4TA?1Gg}@-C7e6ti_Z6h}<JB&#4t4
zhbJv*s5I#lRhpk1z3#d(gakyh)6NlD`$s2-_jZ28_WtJJSL~UEz|K5HG>GC}NI2O)
zs$2W_C*q0qcyl?xxus<rYaxK>N!5J*9@8WGlJcVBq)7CVW86_=9Q1Y=Y?vD4lYv)k
zC*Ea0Q5erLeKGf>We1fiJPGF7DPk3;Q_tEPVhDwIB|2woDIMcnm<Ahj^oeTIO(E`h
z@JKaghavjl6tTN(FLBR<5ApM{o6)t5I2Y_)B-*v;8(xCVjN#xB9Ie^SW0rYfO2YTq
z<^!1{{P;AS?~0`pI;C4cXe=oLS%p8Se-hipaqjorv=*e?GnB&@N&qXV*!@Ag4#7bO
z_TrJ5y6PVfMyk9LkIKA%L>7WR_?L6O78A}t5cgNDxx7ocwEKAW#vMNfo&i4zpF;Ek
zb1_1+b`tBntfkM_2pq9E)Z?I+@L&Q-=Bafo^2)r~g!R*gxE>3DC`9B-jLb%Pq*5fJ
zpICON*Rz+fk&<u1Ewm+GS#)}2OKcMmC}qb6H1b$uBCu=7W}m<FUFlcf_aouJgo;o0
z-x-Wm)$<*_15?N1PrJ{H$=)mFn@7f;*fT1R)jr~$NvE%T_77Iy@NvX*|A)Hnp{=t&
z=zAXay){<PZ&a`I_|tuF4La>N)ep}PKA`S%?k&OYZrtbN|K>LE>KeD{yjs8ch5kF7
z&a0yFyq!NGZa$7bwBKx2cM%UfsqTW-bl-GqpFj6k>FdOOqIk1re~R2GZ*;!&p|0(X
zAJ8QHQ2+6N#(VLDSo@**%i`u&?!n#uv3c>GySdK~UhmEyt9{=6`@<xS#?|bj=~nma
z5C6gHb11cZdH3_H=+)CdaNmsay!Zq6`TSb%+(qYmf48Y39<i%NU;#jedmShQI!M~&
zaRWa%>UV@#fb_s1wtxBs=O1xF(yETp<}=i7pR+){dzRe#5nGIGkBn9kUxb30cL*%=
zSicx!+Tdmn(S&f}8hex9N~o-wn!{U<HPHF(-)=oSYtKp3LF!S%J^$V7>JM2JjB46e
zOY5JsRuGU1=jAy&{FrF(<^2*d3!T-cCi?<cOkc{+@j%X405gZgl`dh5EkIl1dO*`F
zY*uVavo4a~tJi{h`wrI{6)S_-tsWzl4xkUg7VE{{#2I5t*YUnWtjQxH#r2Y1sdwdL
zsR0~o|4uAo{fHP!CGMW&K_5~5<I>%0pRstduW#-ry|))6;~bQl6Wm?_SQ<D|Op87)
zvJnRcX_4R*^BCeHk8co7I^aoxIDDa=6@5&4w<SmYC7W5IE?yRZ=vGw!NtoDS?ZA~D
zN(FN^WL(Tkb{NAI$QLbJ51N?%q(u^*1a2z<{`q#sDCGO(o!?s@j*5LffoBpXEG7Wj
zYsoJ$ZK~b{L{Lg85bwzua#&Cl=S1e0x8&c;gq9xaWty}Q_t3;3pm_~v27m;E<EZ3{
zNGFcF$?bI~nE=)Y(^)fP>S~Ak<GP#gHv|q=93;G>m_JUye#Pjx9AxfM-^;)G3mbz%
zS8NT9!kYH6z^j8^?Umyh1vkerrJgAR%K;9Ru)>4{h~yzfnb3l}6a7&h>SVCTv7CMk
zNX2IffoXM<<NdOq_Bn$_1)*W!KEsN6H#t4$x;#jC`N7bpH1Bh2`d6>|mttEf4RUw>
zHfhTk+Kp$$O3R&Xw<pt0LH>_PfWy0nNPfr&sW}?p_Mu@}UW6<bMe2q5uiC^M4<B==
zDMm!!fQ$o#jX6X=n}9Gox!_BT26BopPC*qc<!3}<UIRjcVQS`CI_~p=DAn8bNA50L
z71|W==N*7gN$wQ$SuqV!94xx&Uf}k6<+;zSLsFZt^DK3OIYauOIK{?;AeVn%3o1Bh
z@gg14$3c%Xa;hTwa#|Ez{5_Xf#~w^uz$>}aFK`giiaS*Fk5l9q6KL9tr0fQDZMN#S
z{IkpCW?v41z|Mga2b-tpv0hc|lk;Eq_tPjoaDt1i%focj5wh|!GU)?y@NypI*5{qo
zIrmAz&si^ayGN{k`GB0#MgNTtHao{@M-j@tcCbrKiBk2=8uQDKhxrZRmAqc?!@YhV
zYLf5W)Y@6_KOy|ma{2>9sQ!S3ceviD2+Kv-*XQ+Rrq&&$TCKMWcyT&jc4mwq#X>$f
zRE{y^RFqao^0v@5<Sa`31G^T;BQ>4iGh@}%7mV!yE$fK7LVkEzCQr4*vhzA~`4m0H
z2Zd|vcR%l55BR`TEI;zO4Nlr;+}|KVEAk7Y(z0UEQvl&_;K)=aJ4r&b0)cTflZdie
zm=Das2zgx_=f#8YFk&a?nKxd=iOLe|<bs<tfjtH>5Fadcea6<c%A_+YlcjlEE&=A2
z>4bB!O9TK?W~2Bt3W?TYlIR!nG(GQ1`tI+n*X)3{5R{_88N30oKBV#xU<a<AvUL$F
zZB<A8J9Dvy`eBGJr|Q@c5=gD0PZ4vaKCVp}0o2ZVRszalk|Z3yge`5{TNzjp$Bs57
z#w9?G8Bko1V=>|wFcK&$@sNJ)`MnK<C}()Kjxz*|&`2`FODCv|krTCa3kZ_n-X7cv
z5Gce<bQ0483m3U81NK6ChnF?1V6QAS4e_xSixwSu6^z)3PlUFVm*BW=(x9r*W}9Y-
zYkEHp9|XmMF(e%oI0|q#rm>e8HXP_xr9G@HkSS<@02#Q7fkbtz4cbO9gvRM4n2WT{
z)ucX$MJD)d0KssvzQW{?zbX5olN97d(!P;J4)Y-9D{in2uw_NJhwA7)@IiU)^PzW`
zCoyaR^-6B9NUjgG(TjOKK+P}U>c|%)^QK5|ioIYOnXn`S<j9vCwBIua72Jv@9`7B5
zs7TL@!S^^ERmePt28C&Lg=Y@w-g#$4XdV5#dU*kFjnNONY3~E0^3!vB3<n*x#(7Xt
zMPndnKnXDo=zAA|+!cL}oiV`OB*e<-N3%8nT8CAz@BztKuPnftYt&9|!Wco{U}|7h
z9zii{;A13|$ZxD?7<)K(j<Et86gxp&A*Q_cz&~nMTzEr+y>)2KKS4r6SRD~h=8LhD
zM8*l2Io_sG<fSj-w}z(xLzL7J9T0%jIon8n(kF#F#xdy<PP%lOU8ltZ)k199(#7g?
zCEJ3VV6=vOC#s@Xm?!fKolEco(8(kQ>|Ic>tcNWzZ(5-0A6hE#AJU6e7LWK9qtOU2
z2t@>}w4WX(Exs6xkaF~e7>2KFV<MAyz71^+1W<Z&r0Su$*>wS|<(D{QMu7By8r$>#
z4cdAfjW`+j>&7v{1aumdrw!m20he`bo6467&e9It72He$oaT=p*MPxyaTZr_#8;p^
z{8Ry3P>KccYg<6_H7c;kG`qt$kQCG(>M~xYMXq(~Hmp5JQ!Kz|YTEmLRTGjWOU|n`
z6J1Q^OKt%+cLUP=jwXW<;b_7g60mrikgb%o%Xf5J(<;=opl2}hcn^1~P&^eh8o*~B
zvYtQXfV-BbycemzbCk&%+mJ@8&>W)Q>>^iUqYo)00Hw*taFW~`f2BXJ%I+h0#J-Jc
z(vFrxj>M(|?SQ-BJTujs@D#j4*n5Ev!YRz-YUHXCYF^-OxahoT;}y>Yo~mgxG{8Z<
zT7juPVyTQ&k=~(cWF<6_zBG#asY?HjlLerh)S2Tw%!+O>f@+JiB4Jtm#j57@!9D25
z@dKL*Fuk~Em;gZ=H_#vhHikeU`9o^xD-_MZ_Jc%nR>At(P%(~^bt;lHSg&PCVnAx*
zdyfWozW=^Oah8-nULPXWxy;3>OZjNqP(3w~zxQzR5z2>Jc5^H4ztp9-vlGrXN7U;{
z<W%D!IoC3K39-&S)D=K459CoV(XRIwx4U&x5XY?n8iOZ)>39bg`Xg3wNQ%^Xc#Cr^
z7Dq@rikq!TK7K&Z{<`Hp<Q7@#VEwCOC$@AA7Wb0mxEzp6?lF3Dp1%y*$=&7ZAbi#L
zZk00Ijf0SavVV-c`^f=V#xukz?5#b@^1sPg&2Uzio8yV{;-I*aiQ<=|ICt1uT&y1v
zPxwf4_D|Zcex*vD$N7G<^zib`Xcgt&zvK*(&pB7}_6c-lhW54yoV_7ruEc|V1gmH2
zgjE|QQ*Tg`kMd9~N2py(waj<S(msIGIKe%6d#%Lov9e=TB9T>o*#1UW)cWFyu0PY~
zu7;1%Z?+VxDfdbDPw3y$yHB<B{|+DP|H~&Cog$rt^1Utm%`59$AD_th08Vj6K&jm-
z9G(FBg5O}fQez8e(;HedXQ`1sv>khN+ugXv;<4)5w~_-aRCMaW;B&Sm*y2uY$OuN8
zjaC*CYfP{vs|qyT4g@chKLnJbJP6RXoFBvo%~{@|mS%fQgwwcN$#H?mj=JyTCwm>1
zE)VT<Iz>5;@1wFd?{rQwegy&HK)qfWg@XjZm$B>9e|wFkCqCHZ9X$B+<l=a=XP1l?
zwvKHhN4vuV2XUCdOY>pv5q{sFPMG_@3ivdB-HQIlUA7Dl{#Dy^Jh~7rwmne=;uq}x
zoj#n%J+_qq*$Ct4+>3AeXMX7@SuF*fJ+rcN<Lbd729E0`cGUh8MMafzn9aGbId2eB
z9@<|tYM%`@-8BZ#P`ihpJRkFYZ1}r`KE_G}BNjHv%PZ05rsw#93lr&T@x$S-QM}<$
za91=F&03l6>9hZ5wdWP~{Z{)@5RF??*IQb0J@nlj`hF38AIUWxUHkcrrHi!45BJd8
zeWmaPI?2nnc9hh((VG7Lf5nk0r3bC}+d|)s1HibzVKsf;uPIcgQ?I?{ICl|T8Z6pK
zN*0E$Vp{<rQ#ZKUb}&Pcp+iSAq<rWjMI&DQaL`$eF6{S>boo?32gGZSS_?b(F_f1D
zwo+oX@+T~IjIVA46jMB))y%sHFx~A=CR+631B;<q7@sg}e={na>-VQH-XFERbQ4-f
z?jm$CcQ>t-bGsZ;US*k4>-&fHTs%iI#uHZbr=3PC%^A<|C{PFOc#HPY9x>hl2o!t$
zd0}P0e}=U3mB5W-?ac|;{NeB_uxWtbaU76%<ur*eH35ZNJ-zdY3{3!A(~Q1UPvy>#
z0dWyPWe|osP%Rm~83KNL`t!vzfFcL{Oyo`&_*P5ozTQGtH&MrWhF|9y?R%#ZnaTKr
zBpF0R3lAdu96!sWmmdWd!B6IOI#CP&qgfC@fQ<VEp=U@OE&^Vh7Q27g=Y~U=DC~a)
zSQ<WUXRd;B;rRJ;c40BM=^>PQTypozh@kQKALaqk&NUnHYg-m~0;T%{$2i7M-b?r^
zEhlHr*!!5)S)3hC9{^x`0HT+}xt+sT?dNPGZ~^9rZ`n>pl)q+Wt~37qR>Pw=aH=B9
zHC=x2_V8ejmp@q28mRlZ@eV+h0k4(66kVK--prZl;yEiDokJ&Bjv2KU6HyXIF2D%!
zz|q5@c!6N}JB=7PYVlilU`s%B+TJg9=9Pz$oXqIqhe60(4~!jdC-C8FG+RTR6i7==
zLB@wh@3L!UXIMYlBqq%GweS09>{@;tgFd}_`)QIJTxi<Ia)}IpVH2~~VtnLR)`zT#
zmd778z2eVj^ws;@X&k1u0tN=SdEeIr1nO6{R<_y-X%X6=5X?c+<b~ig0bO^x5M-X^
zde8~eQ)6#gR#xb;6(@%z!VsJjNO%dzEC&XBc^bY$I)9bgqIAK|SkW+QyU;R&Zrk{}
zj2!IsIrnbW*m4T+x$^>!(WJMzjyz4mgL|~v#%n*hQ`JTB4x&i7Nd1ry9^S7$o4}G~
zqB)Y0Vx!t80Lhw$4F{qLhi_<+WQdu8oB(yNB_I>gh0_+OssL|OdO^Hiy*#Tka6lmv
zc)7nkAAt<IdnXSQ58<#D>kOF@&Y7JYeJ+qDqd#gQa&<2?Ui;9PRUjp=*aY<RzMb2w
zi%&<kMV%bAG0F7CuYATUH(|*SFY$DVWHH!Jbr;B^3nY1I&mxi7Ms$7_a3-1&X#0_L
zrQ$U47AP>z<SAbzkK}1uyP{-wS^^!^YkfRLE@1?9q-%l&tCo+1_DuU%cFvMS<<h<9
z?98aFoFVB1pk$e<TQS`wL}FsjDs%%#E|d2>?iYWbxV67HkSLt9v_%UL`9sgI_Y4^t
z@E!_*)nUXiMZq?|a1MFlW3$Ku&T1<b+zXDiEemW1oIIeCF$l1o{;6rLz5q2T=3JzN
z&<G|abEo_-A|tSR7dCor(vBSiMa8y5Q$>V!%~*0*5NL`adtGe>QCRyTr9-D2H_*Uu
z!Op&KAKv&lR|)S~QG$a7u_(ap`<RJSOuQ@k#0V-Otb{OO%$x<JR>(6Kuh`!F9#9b+
zV+f9q8mAGFT%ZM(^-HV|uF&y4BNARTVA43L$0A$IJFiy-0}vO=F+^a=Q)94o;3Hkc
zVM<Bl%E5pSu9sZ4S^W0{cLq0{=3f_|ya!n72|NQ!z5CDeHy_`72irWQ;Ksj7Pm%`Q
z_$k1Sz*1pmudIQM{}Gh>ycnylfuX&3U%_qsJN^SC^$!(P=_)|>-y*4Z2Dbp&|L86X
zNp-&hJXb-V9|z+3c3WO}4R=FZUWo7vSoej&|KKivvDTKYPpK|_<M1S1>k|6%*?(Sj
zzizJqyI;2zvRl0GhOO@8K3~3JXH;*BN1gp&%y&!h-6P=yIWlVTt%Pq~7@FK%outd8
zNm_M6w}EA_jRHa4VI!=^KP@XQ{OfM~j1U1-YCDV2F@W2OM<Z^?8rcO(2OHOs7BYyE
zKLVvQNiWxS`KjTul?*l%;<FpHvwl1(a>j_rZS=1H<*%w6Sn${ZEU6#=-2?H^I}d@6
zRAsl;9v%XncV1fip#p#V+Pk+_5{0f{!Y?gmNe@3;@+CjJA&pbXkm_FC!E)v5Eb=6;
z^l0N=0%vZ;&OQhy1&3vmb_7vEAmWN%0K|^y2fUfsOQf*T0ujdyDb;amttn;wxPt(}
zom$uK_<!umVD^MNPz~P`w9u9W8ODX;aM5i+EFt3y0)a@o*{`o~+I-{VJ2ez-U;zyf
zLHgjt4cR(kfn*smwS&;Y*$2`bGbDImVgr{iM~H=zroc(b2sV@DMMP47Oarz_CU1+S
zNFMf2vXYCKwY~&)DoAT`hl3MDJAwR^W1yO59Iq^~B-lmAIri$QARkG%MVh(sslP@X
zV&$A@FXE-#AwMfxjKx5L4wBqBL|T?zZ_kDpo~qO?#(rQTib?iy5ZJh*BYLR?sA;S4
z+aS+Y_zD<qV9Ox(LLC&*gRn6$cewp_u{=0VW0~x>>=|EA#mg3)bHwYohh34~Eq%eY
zzy3qd)JCm(%@~B|?~CToq>TX!!Pa9OXzBCRACn!V=+>PPD*!i!s9`eSinCxb0XYI1
z;TUAZcN`DAlmHxLFv`Ipt03tDQ~+h!z_N}GC!co&D<j<_pQP(|G{?<;dMH@6+qVFx
zt>q5HPYG~F4#a&0D3TeQFoSMq-`@TK0s0nZ-($K1GR=mmOTMnzg^ZMK`VJmk+-r-V
zN~nNlN+xpc-K^iQ%7}f;(g*dAO4=cI^ATaCF?Ins``VP=p6EA%im?Qs*rZtr!ER4T
zIznc2@lcm;4~p2TyRt<`gu?+t1%tL2^8Nec3_Zmv{Wyh0ez|3RoGiH^E$3(T6zc)W
zX8D20=iB&b1@A4KkatmwcZ|y9L7S!-D^^*JCZKZXTUNw&EZ)+>3^DuXSh|PJRz*GS
zruUdDX<?+%m%L*PBIH6qIxd8$kQkY|82yZC;9yfb7l%(o?YGap7zui|+X=4|dtXP(
z7`B+k_9rgo<%zzmzwC&6=w^|2WRr13y!n%{pWR_Edc{StP#3xToN#aXD*;Z0OD{L0
zHWg<`XKZw&SITc={p9Yp+@>jg!HR?0Thu|NW8|V+*f+O>e#3)VvKRchqcr^ZSbe}2
z(Nf2L@QYstM{4~@J@&e~SuHfbSnm=~FEe*vADA}$-qGkcC~B9ETQi7p{ZYTR=e<k@
z?o=;3d+Bk~Qmij+kt<Oy5#!>atM$wIIW|Pnk1&@^kNS5!t#yE42Ea7Av0H<ku`L~|
z$?=Slwyrtw;**=OB7-=d!B%^|cYU&tX=ou#>x^aj?{z*l=V&gZz>+gGF$2sMf`r`=
zw3JVS5newu#~GMSCwR*V7TATymw*Thhfvf<D0?sS6{MS83U2T$ailJ2R{zMky#Nt#
z^n;&A)quTa)OOv)=VD-f0;hrk_1V-LR&5<<nV%0R%V$jZ%)KByVBK!gtnguGXv{f6
zv4{X}KnIw-<XsVB(`r=*1f#nJR?$5p5cwd^p2!EJLw_LF0aGrh4Uz3b@j5F2hV<4G
z{}+^X&44imrd-21FZe++ljwr)E}+2;W=Yr%P1u^kiQ3H}LRrEZRfx+P4(1`x0mQCf
zk3Cb`ae8_gJ4y&3q#%Y#$JPYzRFKtes?`-wT!COqJQ?&@pFXpJA#VYwCJDc%7k3jH
zps*34IbhdX$mi-<SjXEX;x`98PafwsYA|sEDGl9S;+{V5!6{F~TFKi|n%9;vZx3;u
z2FUe^cHr99f|fgF6YT4$8Es9*klvw>-bHh#Xw9LS9%{uX;wH(bPeOrei(HJx1-}4h
ze4hIO#@qy9pGj-6xz05vXUBvC0xPJ};6w5nP+$Vw&V(jTSh4Ls!;Neen@6f`RSJly
zv61n#<*m4bH(b`|wIrbJmt3uIm5bvH-W6DXH8j^n)|vvHlJTJ41<dlT_P<mF$kbkt
zuw`u3uun;oj#jx8N6w`nXUOB&aRb&Sa3{X#L4G%8o6Mk1hpsMAx0KYIs($#0tIu=D
zg{F;AIY7O-6S*uqMwpw`UAr!lkJDF?$udQ*svoEO`c?{1zC#d`!(s%+0+S53NA=qs
zdvvWg2G?{^^N_2YR6rT%%Cmw~za_x*LU{Kml<WAN3ZdhPIxzQ5*i-3?z{9S1m{S?o
zUacDe<~2Eu3|&BnPQYTD$UMfZ;*Ux@6fpk|J>P{5TTshE;9{}?w3)whFA%#z#*=#T
zki7zDS&QpA9F@tvvKS%KhQR_qIAwT7MGuaHqwh*_RYKHEZZ*%fReT)W!}Kj~5?i>m
zc9i3h7YBV8L~T)fb?^jp>o&*)PHg2OTeGZDRw035A*1XhPf*LNPTE!4E?VdZ7`yR5
zUUaa~y^Y9x>Ro8Bh1Ph6w&+3AYcQrkMJE<x+b~tgXJm<=h_i+_?|_5=6r;T%q#=aV
z6M+uq^WbAJw@kLzNpe)6+aMs*lw+iKv35P@h;tMhwCr@<Ro=eB?!Cmt-`xas8Lj{v
zDoulez~2G~gDQ43S(bOZmIIVNs2{VFhQt8au{Un<+%(yn(AYgx!ZJ|_<W}V@v7rPd
zkaP+^BLRNya|9Keoh+6)JarK7r=t@9!WXD?v1;SAUlnh)_QQM8Q^up!XiO8?2vH*6
zV|r=A_u%wX%K;Dz=dnu<NpMu}Acp20mT6N2BN!OTP(YSarqvvyJ<-n10#Iptq#E0@
zB#-lU-Ge+rOxjHwIhT4Tdx4$k>zQ5dOKn<mJIIhpJh&pRM$#tr{^A#Z7R71I9DFqt
z0Ha{XGE%1a{2^TqfufALfI|VjI_hvFB&;aivYyP6Jq8rJDPud-VFHupApA-AC-8|B
zQ#eL`mO@QpZxAzZKrg~5kdC=o0h6R=G#goC2d4qD8`iZS+`~wTga<mp_mJ;*w@&2C
z%V$rff7hz#@_W~@5IVX$(<OTOUt3e;<CmOZt0)~2Q$4&F2d7!&x5Ov;=rMNv>}Oa{
zOO1T4x9rp>kY5hZvt)4J*_V34z4N(4JzH9HFWWw9)*(Z8yh|iUFN+t8`S_SK+d~eG
ziKEtUSVzcFP&)f3E%!NgB6UOrtqy!Wt2Uhe*e}ru@zJKOR*7G2o9lc+6kAG9_*bjZ
z{8N9H2N4#~@x$#`^4<0deR+~zXhlp=|0DJRY|;I2dDq_50h%gy)%<&Yg+G$^i!Cx1
zSHt{&;ul86Bk4W&cCxm~o^Q2;b98(L?!rUV7Y}y#PqtioZjysv%Zn{fb-U^E<4A6{
z&AFiOA8C8JyX(8O{oeU@^FYtGyCdHIImcQioul-KUk~b=m*?BNyN=Koi{*jp7aySg
zSH;8KkGPX9qf-MU)6)fRgkzoPc`<tTN!n{~wf@BVq&50cdFR-5kVyT>-Sh7`av*(^
z*<0Awrr%qje>6JQw4Lv-&b3ed(B}R6RCFf%V}3UM*s<G#iKaRSOIA^3+kxCpEH{3#
z0Q9mkc{UvbLP7v@wH|GE0T#3`@s~tsTYl+5#PoPe3owiPWarfdAkjGU`Ru&&5G%Vw
z2sRJBuh~YRi?X}8KfA+f=lQvAAiChnmhZKF^=(YnPUbovkhM#SxeM%9(XT^twW`Rw
zTP$2W@nrYi<-w2IinaTB8yA)D1zvnazVPe0PT-w)Yyp=CP3x?Vis6ll^ZQ`av%5Bi
z#ox*SrC7axqD|kInK;-~D^GlM>@MQ29z1B(9t(zt^R0B^BOkmropF9a(pOq*KWVd$
z0?B!6mlXxW>2>?k!*@6F*M6nlnd=)qIM8{54+P=!^tE%*p8^JbVp=?Bf6e~()#y8S
z*;B<}_!VnASe?Vbf@jH9`mkGmWx!`M#qaFPb^4zjIyBsIaC-Phx!mrDXUlWvb{`me
zO_6S|gGPIZ6yALFmnleaK)s&tIWQd_Y~MyQ2jWMMKyt#HfN6gTQ0UH&0889I6CJ&i
zevQ16nRwc!`&gKMLtbaC6X_pr?)45nysOdS&oq%MT{`Hi2glz{^x=<u)LMLPh`nJ&
z_k`yDg=l9kzTU!q^ff!9Kbl_Vg|NF2Jo=3$K!$V=CNlTvqTQNVEeCgzCl;bT+nr}x
z#0}foePA~CTfi}caNbhi7i?5ItXs3i3&3_~vc~Xms-QaPWUjaH+TRq<>|8w*rWVLO
zWF@s=i{bT0?eO3S?`o@+M|1W97zX&cm7jdUsp2!g3|3$dm3QJ@->yePokqH}qVU$%
zkly&GF9O0!p=06wp8-&G{|7CpfNS~MaA+lmgKIpKN*i6#?^&5ke;56rvwCS9#OcC?
zaF{CgWEx~p$C`;AA(%fAfK~m4?GDb%_%Ajp#E(Y*_xq_4gmab~q`psa#sY?YdL;xB
z{91d?FMoGS&MtguI7iAeEoa)KA}nT}WugRj^6&=<_>+G(erMB^f6xJY`tMRr5A*VO
z0Z6wUCA)5@x#j!?^^WN28d#dGth9q4YYojGJY_mR&l#ACL739x;bEdp0O*aw&3-<L
zKnI=xf|$9F6vn@gchiB<i33dl)dv>r0tN9kgYA=K!H!q3d+_{rM^io7xmtd&Rv;+r
zs92EfPBK-T)e0XDEm~GMUIKtWw%+gv03<YYrvZ!-WbN`V-`QjYYBE+2?c5FG?l;w3
zsG9Jde)&no*~MI(voduSVvwwBpB&YC)rzVWA5jAU$9+7E75mfjLX(EWdtOK4J9E{F
z{=%YRk$UA>2kkW=f)J+DL`<ATwjpGWy2T-&l{kU(>F<A-+9LHM%bLZeoz0*rs4;d|
zQQB^H_^chDe9T#}Yy4gU(0tAXKz;!uxnBqne<vC0JRY?R(fjFB*6I+nMS1um4_6n+
z@PfVj&(1|pf&hCHqd&(c9=9>nbeRt<j9Pbo?zXTr-klNm^{~Qt>Sq+Bs;6%EcnbRq
zMlGPc<TS9_vswVkXQ+1eJbH$pusmMa2F$mWujcXL1b&8h|Ht2rdYPqE3TI{`ak3rB
z0>GC*OJ5BUpbIVBBGIUsl%kE#-~ceDU+V*Yp1N8!cKxv1I>u`W3sNxmerf}nKlz8w
znI`=De{`Io&O*wvqYHQ0TA*Y`<gRa~sJbvr@cK$G<F$9~B4y_pO3LqH+Hgbwf0JD~
zJ#}xB_S(Hov=F8ASCGY7u)`8n(Dtv{g<gijI*u?f?y*+*BI`uMo2vb#C}sJH_hCiH
z6(eq6u#>%N48Amc)=DnebTtqD{<AEK9^y9{4ZmU+o=&|$>u#+T{Pd`Ma}mh5xx0<n
z7^C|D^q(QC)S#`*d5B{J+O-egEUbiVfq1$%1YGn`576tV+bfd}jA7Iyc>J43v_iKQ
z59`P;5VCvSFcIZ*;A-FIB|1#_@k0vkguR!5Ly6QY>u@XG_P#Xm3<uZt63}V3p5pB|
z8$6Bem*;o25uoN0<C(g5Gq6=)_~0Q=|3VF#2=N7XlHdwF@ej8nXb2Am)(nPG3r5|-
ztS03reeG&MYs)d1SV?0MiGzJSS=B`{--5(uj6G}fdy;ve#xV#wkeE?KDDdI4dM#hG
zeTn)fW=0p;dMrj{#R$#HPA;Btn*x)^&@h0`;+2oZ>vF-OwG@j!A+<rW2@c}5(Z3v-
zX3F5gWehA$_V&fVD!qAsMAi)Lw;u=LW(15c9mr$OptVv@A0TD}AiT%1(;C3DSGI}0
zf|wZe-0fVl=CP^*r)vx<to*-ih|zgUkJXxCA4O#p8Ugp|)N@l0Oa-~Awn%M^(K|Mz
z%ZJ?&`P;FJC=#18p;<}}`R?D2i2vSyXZQxz*Q<9cWLKfgzp;ig10MdLQ0C3@w;Kdm
zJokTSo8rgb1V1*X__1qjTkvCl++f@O<2!8I#Rm7c8=&ryu}_g!MYcU@gS@Ngv9R_x
zJ8>si_#c1az#40}LAd=XYq!Du6%Fn$IK-n3-1{A<8PG7=)A=^X7R~uW|DEw0^g2--
z;=wmgTwiO(SQWh8$M3m?pZ}|#t#OENDB3PC>l-ef-v-d#vuh+`|0o#E3TgK5aGp5i
z+X>9#8u?atO5HdC6JOZtiu@SSw$hXtux2ny2H=mYKgSXgnx+9RFi|YSR>Yyk13ylI
zv*;?`m*(lAFu@uEZzma+07OVF6pIwW6#|#wCox=gyv@UXlAw^U-JlT+t=;O@U(_!@
z<?jZK*F3oU?>w;LG$<YX{>1NZoYp3cmq`>08HjK<{5N0L#z(byMqFs+**c~1Q#v+o
zV;^#PZ)w#J4#5i#@cgO|PDALw<?!08adf$MgWxzUpKfBK<Nbm>h#(_QHupNH#?@ku
zNHH(Lv;t`3x@ne38SN|-Ev|l@Nipb~GeLfy+LBJ$#i}bV&{KEV>8@@d9N2U`Xbg$B
z&TQ3UXNTH}mphdA%wVB5pVm5b8AxkD2E5;z197fH7$_;|2TqKbfn%4h5r@@hIX!HV
zk?MGyOVo^BA=(Itnlgxkxnu$aj96{Pd>7CYO#&*9<-AB^8{{Ssz-p2t>T(YVe0IFU
z-R8o3(4K9dXEbTPF8oBscdmc<5s=RWfOhPT&4Z7j$1g^X^iHw*aayQ){1o+Ob>J(<
zC_`1F{7L~1f1G9)7{%5zupdkAAzfR<M4)~iH>n0*DHzkh9bh6?JfM^jhD6u!$usL@
zH&P2BA79qwkoXpJI1pmqbvf=o2ORn$0%uceMF{(&{+}R*YxRu*OVj4~c;VOXt#9#$
z2SXAeD_4?M(;T%zV{R)*LP;|a!fJ_}exSM|BI*ZClc%FH*lW_-hB6I1fX5Gw5v5HZ
zauTr=bO$UbDkPjr^<hkwc)U<Q#)d3iYZr%MR7lWI@?}@UF^j?!O){!$*&b~F3v3xA
zM@j!O|J427Mh_5@SJiU?gGNdg$719rcske!c?^;%!;%Bik+V??R5DJUu@I{l{2a|2
zd@h+zXLOHb7~{n_P6o>?$#CvCc6fr`2^x0nIm95rV4bCSi(p)zlTARAdP!>2=oFHJ
z!t4~EnDbEgc}(;h!BOjoKjMG=+4ZqC!5>b;`>~uttz(YCIU60An<#QpI!3nfeaO9%
zhslFh(oFTzVIxj{LOQ5^baoffYRfGvY0|^e(?}srN=I~&d%<38$sI=Bp!PqLXc|Lt
z8eq-cp!)Fgpx8lzcnd24Uj^0G%arnmEK4VYMLtN&;N&uXF9teI*5}TXN+e1=mA}Gu
zJM8Nc+kwNIM``<t^YRVy_fDZrB!}K*tsbba`b|UZzF*6Ud&}|sjx7_>)NqmK{+Mhf
z`zXR~8w{MFP(4Nm&eTz#VLOxkmp(3ny?rhBif=k(sF%NpWY+oSV^kbtD+5G`{<@PJ
z7q%2Hk6I<MGE3g$#K}YX7bkh{z!_{AxmcZRsm;@Y>UesL%nEC?zLHD?<4Y_~_w)tr
zeJK&~_|M7bcSqb?ZoWVe;r9Ua9h`HHG5gD3T6bKr&^*)!@sq82W1ImDTtb18N>ml7
z3t<Fm5n!2XF9W;xu>*TbM_CG`KQwCuYlUIvu?+M=9N?V*Yp3-99EPkoPeU6E8hf6P
zF<=@od)?PHA%G6d=rSIu&cmI?2|m-+IvWuKa^}Y0{9V#t7mHvj@=J3e?*~flliC5K
zJxFe|I7w={N)pCtb4VC5P!@25U4X@jv^nC(!1|bkC;u4ZL7i1bZIM0E35-OWiGbDs
zv%S~q?*sgO8x=B+QD~+XTRK)8YPoo2ccv*pJYl9v_q7r8IH6g*hF7lrmsQUY%;N?+
zkkwhvgtE}FlPsC;*X<?1!v$YHKogd8A=-PK<^Y>xJ3x}T$juax%z?9{jEkt$QzJ5I
zV$(n@W3YXzG?Asi&x@jtx&iu1n+~BEsRE3|hhV`P$spF@9tQhsrss;tPLlZy(ga}5
zSQM4R4D64lfJL!I`vgs5GCUxps#+1)>d3N;*8vJ^BX9zt%?ilDbFH4OH}hkl8?$sC
z5@6NVhuFOU+hw4xfmjbHw0RlKL=gmOS7qL&boYp`L%w1k5!(AN{alc&Mhvc*7n5L~
zgO(=*R%njpgE<f}Ezf+2nl(Lnk~Se>q>lsi#a)DvJkQdh8PCgkR6oWh;9TUoY#Tk!
zc2GoCIl(r-#|5Ra6tqND=<hBvpJL$ZCXxc4Ck!pr5LB?#vN{;%X7c*)O%?<s(mO>f
zx`mg!vH#+6uwYL$ksOQ;&Pbuiz<LZLKTS$8IJkp)h?GmNo3p`7l$cbK5fJM25#kJ3
zvXt68Mw>)&(RtHJ3wx9VeBMg?#!^$w??-V~qeAwuO{qhC1(t@ze2GMW<#Z-uFrWal
z!%V<hTo0~iQF0;(u!UtDV4VRIX65>4g^sKftK%>qa|b8$Z>Cu{C-G(pV<4KqZ&;5s
zYaanzZ#L;85|Reb8-!leb4cuf(=b2)<{oEBvB66;j}p&BmjV<b!Jw!l#txEH)l_38
zjz9j<@3L%^PnQ;wnIL#i%N7&>OX~F_1a5#181hxChJ*r0+_6U!!4kk%rvch8(JbNO
zU2tTynlAZ*XNCr()ZvSo)}=Rhw^+b6bqMhc-tNtFNN=(iAg!rs_v%@FiFcyB2bYu=
zW<4$_H^AGVhs6SLb2GMNw^olUx&(D3K%?O(RdjsI;WABY(H+fO55_nFahF@iGa!c7
z%z&?~oHaEod6{=Zmd0zSGN7cJt|Vh9lNMdh2ovcQS}{BaZHk}x#%)Z~=7r-3>^nea
zPkCE8Y@q^W715f=m8`||kN~=T8xo=hLy;0nq?074u;7u8$&Ok(2qkGEjBHfJR3tY}
zHVKk9un_>zymH+wWkcZ+u;Xk7ly#(km#{5D)iHwq2aB(LZ}$eig&jiVT9D5_gj9@$
z0x3Nn7Q_)`)BTzhme5<I(8smZrj()f{(*Qe^raRSGiL^yJ%fTzgOqQ=74ldfVj4*C
zDlWs|6YM<#crCILh&n74^7u7V!Nm%{=gHfUx(c!w`WyC1<{8qvH2VMZ_CC;UT=$*t
z3<N2VR%vlB?+h<tNZ|zs6eLTwK#?--*vVXQMg$cq#(;nfDU?mfq^<PG8&Q@VCv{t1
za$u4%RSPne(5bUAWinCH_#{r8)Tiy)3KH1RsoaRR)GAr`G;-x`wwvxsYTCMgUh=*}
z#d)vUwr|gS=RDen5=CGzbLY<e^Z9*$-=8ikIu=xT)-|VK<xD%HgQp-L(qSZsYMqH;
zYcnqW@`%omi=pFz8%z@r_~po0HN|Q)&`rNlg_T9<5TvP-I#XMb{e+9x5R#sRhzO%F
zGPJNE45?-z<cz?cY&4;N?4QHzGcvimHf$C7qj9gcVc6VKi+@p)^w6E8rV1UGd%TSo
z|Hk`dqpEB(lJ9Ry4wECSPp*q&ReE$Ur=<28fiCsRR-`@3O1kMtqugRFJqO!|v9w_<
zt}_mJ4NDJ_rJ6iPU%ois^{0Y9PCqhd9_D}2?j?V0oNa1U<|jzT+t4VC-K=AOdS7f@
zG+tR)F%){F$?$<zR#&H$eNfVSX}W3L>n%%)pPX}5&V4zVhRW(*6`GWbc-y4+^`Cry
ztKoXLzq}xeFE4?yt{=LSn|Ct<*p-%cMxSVyd0%(BYPYf47s-4f-%=x8RbwBPvPrLN
zW4h_3b!?*`chM^UM!718`8}GBndEUYSlw1_aw8AwkIL7Teori_e=)I{4yi{d-C|<M
zl9x*m91rt+sdkU4jV-mx%ikI%PtbgFuv;91R1eE#qmzw!S<*#Lax4bmu!Q}=IXP5A
zVEUOf3vA|okU@G>S>?XKuWjEuAl-mD-w)<|j14^#wDQm>^luMr;B$ezSj{)ilkVC1
zh8M{C_}dL*WjTb`kK;S$>7j3svQo)F`dRT>`1)9dR6&Jfgm<g?J}enacM)#p+X!-R
zlMUrj1%e!Wz>}cW#fS0hQefEd$>7^vhF`9|-Jo#%P=Jo1AwgrBSdGO4wCy0c5&Q@-
z^DyHj{FP4xd|HwZ;AE1C>(#&f8uKo7fT7*Ltpz#K#gF4Oi;uPL4onLkc<5Gg$m#d8
zbC(|Ii(Q|H&A;Atn%sNE`xs_`?()%H!~C82`s5L!?^>Vy`vznx7eCOto~-Y@)OQEy
zs~UDZmfh@qzNn9%{^s`^PDA(oVh7=c`40WN%Imm;Y<hjlBijJf$itc2A-?PT>!aK0
z=3%!85itnMe}!4Wy&JvHZc%`;?Cl2v{<ix%8COtZCduVq&%Fg&!A`__^9xQ)wmHtN
zauOB?;isA^6Q>DmCj;OM65H2niI2Uq2EyYbN#%XzXddH$@kQJ;2nj)cAKEDMi$w<N
z^0({#bi5<hGR$_r2)>r=@+Q7p_DqA6eguqJDV-i_qmy3y&^Ks}yPlyf>@lvz;rGxN
z8)o^hcIY1>#l8kGI~P&SBOfGJl-v>U!s3pXDKw`=hvKS!;s9gz1Tl%?dt$P1N5CXO
zDjnzw>+ahGKY=#J`ra&7W(jWI`am3LmL{B-UOAn3D$(Wn>@IIkh~M~!UxG=1?iRKg
zvQ#fLqBpsLdbhZ{O~42T@H=_5;+;<F^xNg5j*xkWsr9sDCCCxN2uR$wl-#|)1?Cf8
z0eteZF%Jm#d%)0(vhfAt80Lz)vAaQ4)?eQyz#9kg`MV!((GAauEuHrMJ~>ZtG!D*}
zG|-dHp#pu1^a3v1&f5f<;<}{%G>#cv7GX~{BR4cKx|m2H&ovD8d{B_RxPE7rSjCJk
zi#MPT^@qZ_!cn+rR0=Lg@;C1<<|aBQ1p6^P*Nyi1Zkg;RxgQ<v!}%UehI7LmzeDwc
z0p7i6REGK9w&W}szcRnOA%>Wi@COUPQoDz4-4>Ji3?Q;hev|6CVsPZ0vm`f}MC>7U
zR0m{x2#pu>@M(4L7Ia+9^0@`qhewOUamN<jz*+&<pBja(Km1f;E=jL{>yG0Pn&YUI
zy>3!QjK8D78wc?aReE4hfnJE_*;9yBd4-^TVwI0H<Q$BC6X=C5(TYDN;IfcNgT|J;
z0JfjR%F**QqeSR>I=>IrAy{}8KtU^eKmLBgD?3|tx72qlM7g~}d0#^NTOGHIz7+R9
z-J#zLtuHPMVG30X7`z*|K$82>XIwOYl`lZ<d>D&*2zQ}nz`q?&E$mHP`@J`EPJ0?j
zkBxec02>1{hm2dsVAB{FJ|xl*vqQ~H&^tfJG*_>@!o6WF=R%i#{`ug<3j`YAg*`-D
zAbQN>h5~DyG4vi17@#nb+e~8UcNWi;hxFVGqqKw06Fw_oVv~6uA%%_=xbV1U_oA!2
zVcY>e0>h4#+%K+#;@r@Y9h^!??KZxUp*MybFE{`Z3->$BmqueA@t#m6Vyw*74gD!{
z6!s4)38nDcfcAM{iPOYjRi4AS^+WCOJ-}~xt+<w6Ks*FO_sZ^WLY*Shogp(nF$g#f
zW+*gG6{V=fT)9%s;XtJm+J}fpKZSEObj?T;2#RU0ssT}>0}<RDYDmbS6G$z3Jf2Tn
z+q+<wT(}yCAhd%YgAYOP@h;pDEjMvKFz=Yq>abyYh07IzDGF54c#UhIznq5-w*aEt
z8-Z*csXlc8_=1_9@_Nyywf2;j*6MeLX>zwg{Vh+zBv+sT;}%<w0Rr(5?ie)^(^(TO
z5ku)lHN%ymZwh_xSThzHKGrDKwMQOoMnGLzSkjH^3n0E&R$fSiqa|sd^+mMM3KWGu
z1Z>%uU1(3)4B?TBtzip_;4>8oG4P0Y)zJW9B~~j=A%#VBwwl3$7C;!zyV_Okc}5^X
zw-H)*kh7P;%GU42LLkzdX4rLH`yFQYvk_Tn$JQFS*o2oFoHNo$O#K9gxWgLswJ>X_
z5LK=Xks8*Ei0@~0lV???1j$jh+QqTsQec`sTA)I7{8Zy(9%f2XYQuP*1r=5mZv%cg
zjn|eQ#~gY2lQ6C;ZNiLNvd&=EgTN)QM9M0>l7*?W(JzA#1~w2#BK4*HI4>lwy_E{U
zF^m!LhDQQBgva^CZ^2vPrqe^uGNnEJi<I`?GiU(&{h7_fy9fC<Q18EYkY$&L{~ccZ
z|NS5j90R%rD!!?2zKM$e@i#Mj19>xm_f>Y|{!cD%4)85nIt67JzN}mVX2;l&$TNWw
z8G2sW@P@FtjfUl*Os;~;2d@a>$1_$!0}saknuC{PuZ&eZk;G$$gFmFM5#|+wW2TnZ
z>VdLJ`|9IsvFG_0U;fRXe(|4||Mh3T3-&OnfAOZD{cvsYw=F5k7~^{BO2V4TvPB-D
zpaC$ZM%XRew8|G>l9_y<OLk0_e;E~1D#<MCJt$EPglF5CUx$%_iJXgwm>nve1@a{(
z8yw34puoJKCR>)WX;xFd`8dlGl(V(hjA5k)c`1sbynI_3^)!5SUiZy6Q(ks*m`&(d
zgT{ApWm<hoT}TlN&c<!M)%LL~qhzuD+NlFtGCY)_5n@R~qj_seLJOV)h(Ru<6SAyI
z$PFb|DLY(+>_iSoa0MS&malQ3#|z<(Bn#OxoaY?A29_sMTC!Jx%SRln7c3vEl3`?z
zr!Fx4LFmDJXeVnHHn2IKn?6r^r#qE)j6{*Z8#{r-JQ%iGiO+u_Qie{KNSX|@oIIy=
zHyBjmSk20GPL1hO4(75s%icGN)B=1a$R{@WVI{|O3^SE{R@sZD9gbx(Yvl!$hv4lT
z(rlScK@g{0s0n@0qcf~>nCa2>R6Q<;F$2{ezl}@vY7K;8Oh^A<*opgkA{mB)daAAc
z+Wg10+2orE89_2Dr@6E9;f*+CSpuE42;EoE*tq+Zo5{dJTOYKI$UxcW39Gq=tZ9WL
zn@BX1bvh}4ON)$8bEjgib;?eq9ZDgPAPJ#2M9MN^@+zCkOMxUzu1EPtJ#4sJoor!R
zN_HG~k^N9+7GaB;=5Vf<gLWwqedn$lTcJgR>%iEClv_IBjL1=W8?2DBeD@r(NP9!p
zR=)KX2%X#zb+NTA__mYJnk>FngFhV%s}*+9lA`BmjzT*J)Xa_4eIHI8N;nY9;oqW}
zcADtTk9I)_7fp<Ufrgr^o0DOm`Yq(c$bRiQOc{;Pd0&M7VB$UQnnANPTFKx270-vD
z>h(FYNR`P$3Ok6DY|)j{#)&#c7xWFXS;vNdD|B0nv}X6xI^?d{U`OLAF9m1`qUKHj
zK85|O72nG`vhpNhrEK(Wh=+l?{8>yyc)Al65|SvpXw7zIK4%R=HcfgP-W#oL?vb5w
z^RhL}v5ynUCsKcs(rcY&yV;iTpZ>}(CC^f$Khaa;$&X|eZ|_#-ge>edLUBUh#H|oU
z-gmZQoZp*$LGHC+Df5u@uS74R4@x;%W0eAiePn=|pw_ai#%fKu(Tb5Zra_?WBdJWh
zy_4771LgDbqqQ938b&FL6?Kgs=Vk^m4oR`Q<s(Y&JDYM~sTYN*$MLx4N!cgTOpU#i
zBH4@nHs-Xn%nG!;<^Ru_4`-a+*%6(TwE;W~82+Mbd-Z503^X*MZzhbbF&UEkCB%`P
zI6njv;xkCM4+D2b)G~5(e8{d*oxNr$vI`2tiZ4@oQV6-2*cx}{VB;N776*eIEM_Yq
z5RJg*0YNUvi-CuFGojzO2P+XFps{a}FcMLfu<J2_d75X!f+#aIJEs9b3Jl@T;EZs{
z5wc3!O-^>z0F-_<PEUf6MCZgoqBp}I)?<D&rQ;+KXo+B+AJJX-{vy4n61KUco4PEF
z=p$gY)U;-4&nU^hbL)mPqsT;n+S-R4l$aTvYDPAM=MkJhi-HFQ5C&fuZh|j{2M`9K
zz|RK~_|c35(lA}3Eg~bBts#tLZlG_BU>4E2--W|ESYUvqJukZClc5nk`f~ciRXiPb
zK}Pi+KoxHGt~hQ)cQ$4-*(C)~SEnjUwlN@1$B3Lmw?;a6%A6s`IbVW+I&4IcB^k!=
zak?yQDR54%5z#>>P&WZiZ7Xtev+nSNO6Ge^kUJoBCn^sp+KkiM8Ve-Qqal`XobBOF
z)y^^L)UD4WNt{n1K!mXve@y6jyiMH^&C+$^nN`V1V8LHgbzE_TIwN`C4kIoKJ6xw1
zif#u{*|{978tjmmRU65Bjr?>?5zDO7q_dOJvapD-9Lqi_gb(6)hC$bAJB3V?J2SB{
ziRdewjD@f#LZ8}MV^RIjsAaB31D2Cc<`NRmqdc>xCj3W;14lMSaxJi;l{QBANCTp9
zMkJ@|&BMTe2=qkJfM9<)N!>EI=nnZI^vYFH;$T>RnQ3<d{zi?k%W3#{Fokp+z(=)H
zJIs+b4JJfu>_SE#@itw(s+x&uA?k7MPi~233Zq*L;pc>rlDbsU9!Rg9b?Y_r9-=kN
z(5?nd9cQo<z`UkviD(Ko@>pR?=oJ!ORvFM3OM0%k$coHOa}H-{`v8Gryue}e%&0aQ
zY74L}!z~82Vo{g)NIKDB!y}_#5+fp^YsXV9GV{vyRikDRx0ry#6G5`pFb(Y@(V*92
zOLmnRB_Ey7*YP|C_}D=-M)CsUFA&rZAev*VKw^V@IM^$&l!R?W%JUJ=0l0PKK;RS4
zA!!X`)x$?JtE1Dr4u50eSX)!rNI-3iXvNr#^d(!;FxJ4D_!0@>!=pQE2>$sx_#?HU
zRZ0RG8Vu-LRB>nu3j=^{jTn4&V6cT#vqMoggb+k7n}nHB2rl{iv8zaUDGpC6J2a@y
zSPmd`4+-;DK8komSo#tdB-*s?5v&e!ncui)R|Z>|kfVkKVG&^N2;;$%s-l?*-Qane
zgL;?Ye~GDf0Dl|s&`YOntRHNw?P?3S7kED|ifCIQu#Wf$B83q8Mgiee>qKZXouUyV
zr9u`BN*axHg>tOZx-GaK3u@SFk1aN%I!J@=<2)^#8)Etz9DU_k`0l`diCgU?k(yQ&
z-PO0N(3DQj7@D0d%L{S6Rb{|?k*Vk*8(E;MIu0y|=p@1}2)bdIB4k|P0mJHp9#Gl{
z?tYIB$5^*y*&oG}2Rnu-Jq5g%vQieTg2NwsafPiXSB^J9wJlv;IOvE-{V_`!$fF(B
zBN1*w0Y@~9RA;cO4MVBK;Fwjzf@P8%;SNdZ&0bHS@GsF3*>u*7Hc^bo1e>o=iz0-N
zqC<oPylNaNv|f@yleZnSG-(T6>k8rD2S!KECg`<$r`ns+bREZ&|822=NN9Q=@9{P}
zljULaSIHkYeFJV2rEc;GdFk%*bz=>l^J?W%m+W?6$xy2G%Tm0t)(?$xmDlBGGR$=L
z$*D9mkAfaQ+jNZh&<d<$VIwdOhGf_>cI-Y-`IFjk?9%?4SvebP@>+{0)_rd&yHxhJ
z#FrAoP5Bg+>&$M^Enua**|QoGrst16nkb}<&Qu}!Se&q>vj`4YFSg$|ddx(A#!{wj
z{aE=_Puu2}ZM;_AIGkwf9G6^t^hWKE*hkZ*ahLHqIxc4`1-U_*zs~#oo?1Ldi{GzQ
zP17G{kFs>bhH?Sx+u83)_oEo~Uw?V2beMetBJ}uH{^~c_>yQ;ZbA?u|L!?x3%*#C8
z)L&NTYn{l|LarlPUCAmxN%!ro496c-TbTN5x{D`a<Qg}!Gw})#Cpn*vUFaNU{7Ly~
zG8Ea0h<NIm+bZnwc*FGj+Unz8YiF#hMpIqn?l^x~O{L?Nw)C;K?$HeoJ}nYoXY`bK
za4B_|J-)p&^}q|^_5Mu={K(kPsd4YnC^&6#12(7q9+JT38!N-?=Tvu?LDU><L6H*`
z*!z<0H|cI^Pw+0I61>&LTlqSRLwby*PvCF}41CiyxCy`SZ^iFRM`3&LE;PQ$n7eCl
ze_8+v!}$UqP#zkE;x{{VqHS5Jj1#HAo#J19pFh#E39R`9sz*RWy)lqf;mu!lR_uCm
z=z)gyNb4tefU!8mWfJB=th@mjbIAA>y&{I4LLqilc=sLkuTRi<mGZ83?4}9|*0+*N
z6R$g@OfH=FTzGnVE@a0~tG;5<DvSFry3?6SujsD)BdAu^#Jqjc39oK|E`G&043+R#
zyrDY)g`si&F(t=3i}&3p#%JFscpInrrG4(Tnb<c!JI2A={s#c=U~%2KfU^!k!+Y8B
z9(|rH<Of;sCg;{|R(BnrRN4ENu0K3gO5C3Lav&c4VWQ35U4MStcdy7Vh(G`Gf9Ni|
zD<@%NQH0odq0s(*ATaRNPs0pY9{nQmFRc~U+q*s5E#~*g*l>LJPdjG8NQcY^N4sk-
zk{nk))q=f4pIe**DhHOLIb4~9WYhwLUovJ1_#Gf_e;WGV;&eky_CI8o3LS7Q+2>ji
zrrtLMBjOVska4nd2P81XkI-?2^KAbh&1CmlunCbvFH@|KI$mn)$`l+?fyCAFCd6&l
zU4O&Yzx`Z*!-pUgJwMc*`1A9>3_){;S~@?hV7&lU>For1&%vSXG&cvXs=R4%TH!s~
z;miE9gu3^alX|!8D3Zz#r3ZN_BD51w#v;mOBymTS5uWtkbQKh+1SI%mfsCNA>`R>V
zlQa(aaR6|~3TX3DAn2mA(i+-bv`f#TiS8A0Rn8jP0R{>=`tHCZ*Ksd42=9FKbu92d
ze%Ci3x`DvbPtK9(sRSH<&G~r98v0h^MrW$BH*@WWd+dCgpe@=vyonsUg<ub<9T@_>
zDioh5Mn132H|e?EhEN`eaF<s!^yo^v-#NpXt7Aig*JL4<(yy_2u?g3x1vdfq7;Kv4
zvhFlR3XSlIYspeu5`y8clh~EAX9;_ED|*1vY4XK{T`0nP;=J1`ykQHb%HYOx^Xv;G
z_bK=~!)9hpVwX9zJ#j2$;rkza7<%tCE<D%Wp{tH>P&A4&*dn|^1Mlz(BVNZ*z}@*3
zc7DGAWbQ`8^biju-S`^pqh%08aD$WH!!AG{(k!nFp%vHZF#=KZLT|nych$pRN=_ip
zefDT$8~5CbEIri>7YTgov3NN+DYHYoHTuQ`wAjZ0gg<^Oe1iK1-BozTK9mSNwXeV^
zLb1eMub+l|9!AmmzibJ0mxs(7ot?Yr&~)OfH&&eJXc+ZUM=73$emo81>S`cUHi}T@
zv!ZV1cQ(uXGZ2sug5h_UJIG%sAw6^)X1<i74ye5Y^2v*E-#~;Ej{)H09?)Yz@LV!&
zXWAQbiy(HD{vE<!crV@TJ$6+83PC@5`U-g&s&S_{h7Mr%vrUIn+054yuTSU#b}W_1
zt%;n(CHe&QQkI>yyJZDAS1`vGcl9k=*It50O5o}36ye8#z_><p2HZH1!RZueZetR1
z6GN9B26=_ye5Z(0z#s!lbF(xF?_#fpp1oASM)-MHP@~lWfDt<&_TCo2h3F`>%nfav
zFgyR{4m3gon!K_G5gpkkro7V~NIb|9`t(=`ul$FP;WB`cS61@(J)FPmtyzx*=FSV7
zQFsg?62}t%vwx)zU>p%}?=#;=^g))gSMumgmxhW4Z=#r(Zf6@Zr?JCVIjq<xSZd0f
z(YOax3`BIsCt5Y=%`3s_i$v*PBUq@w*iZA1XQHJx$@vqJ0KpGI`n*2wo<)z5yBpzj
zjW|vtKDPaqG(Gu|kGH%)jFTB)e{yFiwuBfCz&kcD2{<Q(?)}JG%hI4q%to4Y>4MbO
z%RG896V7!ZN9-8X$o_&9OFjwv+zmqp?8BFO(wpoV6=Y^dGjMU`a+X_5S(3#Fp&di`
z3->%*pww|y0$I3bY3ie4s|ep3zBpAL(VqwGjz++uCnOCBGR4lO1=d+xG6Txe&P;6_
zg~e|U2D37B;m^bCp-rCBhZ+=sGwRaPPFm=|WXSIX^_`~yN*)JFhM92^s=llXoQy;t
zY$IH?LhT9pg-`f0Ybdc4fN2-PlI58guf^fG5B+ghw%DRoP6l9_uDp=PR-$klvHKGN
zX&wpA1X@xRQZnIJV5H$AphtV*#xKh$Os^sZu3WHEUv0zM06JyohK0Ai%bTHB25+7Y
z)W!e0D)`@~yf-Dv?*J9wxqOgiiSoa7kgv8a+xPzOIBLL{WBans`B!f0ihpKtd=nKz
z><lZ6yOte}=Yl_PvSP@T16z)N{6gUFaXI^s%eEZv8fxIrz$iKJ5{4DV&vni?PHOIF
z>g1ilVFG{U><x2su-^i3#(q&?bH2RC(X41-mFj>vfB=LLcfpr*nuATp%`d#;=2s0b
zlaA}5fF?<X7=dUe16OoAWcl-<0A6Pzc7}ztpH>6SCb$F+G$3xiSKT}?e)!ox-2CUC
zeQ(C@0bk2@7$6q^3va&m{mBbf)sQ^^R&zCN#LEt1+qu!3TNigrY`)&;U~q`Fcx^}|
z;i_w?Rmd!5aVOrJJs+=)BlyyDn172OCRb4z<T=zJniD6np*zH#u%r$ap3pf<vv-EO
zi`=m<W?|MkP^}|YJnor0J2~w8rgtIXZo0kqEbCU|vUTum>t%nx#NQvZFUD(~>v(Fi
zY8i{2<XG|twf$;+s(O2QzYH{^U|BNR&gtZh-v8QMZ4li`$}!o>-H>C(KR~(_?ZVT$
zwzph!#A~#+g>O{)Yjmz#NE?acPG!g1N*%TY*s^O9DqHML5xLQ*qY39#B?nbqL9hr$
z+C2&uWV6Rv$?qlY+-(C4LG>f26JjiiiFjr+KUYQBrs;KKwRO%hb_j+MMIJp+o$^vt
z^bT7yowz#Rr~GTX*KEi-btE|_^U6nw0SS_tPk~S;vt$e@<@X|6KD-$V`wY!GkzCeh
zgVLT8yJA!48YVN@-d8vG);hORe;0R4aRqUd9oGT8Y~RZWXCGJ3rlE!R3zOJ~o{2jb
zyUNn4cV$34yV^v8%B@yn<b;LNyGwp%Iz@X&tL-D1n$<-{WjJR!^)sobf3h+f6vD)Q
z(>}p-R=3C{{4!656lZ?Nr$m}ImxX;2ID^iOrBe_z@8ZvkiW6=H$5yB)gI3Bqin^z$
zd!SbFv8hdCOPtN39+R0OYgL2pz?>5PouPp-b)2nF;Mv+wQ*m_|^)1%bn~qt1i8PZV
za@DgGPIX&5V|mn1O0}poH{an_{Wg>Krm=B#K3{(CC>6<YvTfqY6U<Q?6f74#{~Y1$
zNhJt$rK#wuT*`8iXdf)n6d=#6-HyUV2$w)ix#}6f!HiR7h!#3d94dUrf&Z!o%mxzd
zbkB~}U@*@h!fg&Z1AIKQ(}=}35A)qVUC4ma0j=P<*^$le-5i*%W>+N=3IC_bwHC_L
z)nmC)o}8vuPa5eWnHhSFfz{J^jc*LfI-<H@*=~;wcEi&H{=5{jYd<<CcsZBFHrMBH
zf~cWVs3V>gT~EX*Ktb3HE3@QRc9d?z9*AK}>c@3QAt>Xa*AK&)1Mq+FRHE~@L|a37
z>@x}5%|5$jUHc@&L68m)3fVVW-P9VnxB9yEV0jm;hBk+;i1Ds5`Z7CVwm>7-_0Inh
zw=5L4J22;#N|pTPtM)2TceaoD(#*=ZbC|72(o(`QKW%^s^^zlyQU_(|(Tk<*ZgD@s
zji!h*F1ytx_`I5ne6q%?kd(bD*HnsgsKW?UTxYuw7tI>|KEfpY8R5a!8Ay`XHhO2D
zPUtk@X2mn{UfO#(`+7>w3!vFsyZE}#q+TO@d%@rC#8NM%YCJJU4u}K-55BwCmmmAh
zkZ>?$W}FOT5evZBsYyGe#Ua*1zVM)=5@Zg0Xh_?jx03;J54uB})D&Vrc<UM?63|T`
z?sz0R0SudEdq+ofnRrm|gShlK>`IkpouLD=5=KP%0!Jj+(MA+pX9uN-hJ7`#TZ`_*
zO=J-=3xjUzG|D96B*_0iS+Edx1TM9-%_IWhX&59G68&>9^XSV`oPx6!n#*1#^k!Wm
zAPysjak+~&K*#zj=nHr@=4X?#i5jGeuneyuYrlI``cDJy3HSnc+TY<Rr#aJUIjZ?A
zZ=0$G6=^X)+|EM5OwyZ04!<2j$0tDC*+ndg7O6ICXJlwZw~+?{vWM#uBpQZQPRK{#
zN=2dJTxB|iIRsB_WQ#c*{XaaS^E1#6d@Y4^djz_GgPpaGh2s(s;Sq`K3;6b=dPhmt
zVORftXQp5osJH>9v6{SqPcEFuF-2tVHmnh=qCp1)YyvjSu5?qGm0fzlACQw{h{I^p
z(Xe}`1^J}28X<qU7T|rbq97LJ$uMp89fqNL*8w?B#)QyENC;NY;fkfd)^>=k8Ic&I
zeFni_1Xm(`Se09L=%=5LOkmaojvrBEO)W|g?d5AUJEd>6sF2VMXm!lfDOWeLkzKrJ
z1*(yzM!c*)BBapmNX?BTGpjl>*-Snagp!W)<2Z@Teqm=;SytT|v^1@YL`>Fj`O|v0
zLS)0CL`uIoge(@Mm_c=PhF?7NS0S85E^F*Sl0uy}d)YLiF3E6Bm>!BpWT3NFHagXF
zaH_B^>65j<ni0R#z@rn!fK5?4j0C#tN}mrcgg~euO$8GgZB!J?2GXlrBdW?UrNPb_
zy*-S0+(2zg?-mWnt|^--8ImJ4cqzQ|W&tSyM|?zJa)^rhGKvnuEXO7X3H4o?m1}AA
zTmy^iMx-g@sb(2QT!(ZGW9z}DLSBN5>?f(M@n(rQYp5LEtZ!kMB`;%*YDq}<{gLH`
zhlZ~N<j5N_6Ngd#ldg6KX=+l3KpqjI&{to2Pcr0^?0bd1y4`}SltQlz+tSgKHHN#s
z(Gw(vRS6bG<MKF3_^<(iU`xrq%rv&XHF%Ta1H`1BOHfiD3MJRT0SGeIA_5r~zTin;
z4y{S9*^p?~p{Pef5Ff%vP#*~fjxAY#_6*WAeEA{>uG5oF&E_&+eR+)|p)BT5zal%y
z4qu?Khw2UCAzj0dQx+{i8jjB#7{fyuC^obaRA$+f?nL~xS!a?RGYMJ~s**G;Oz}Wh
zqXqQfITP`xPA0o_6oJqowUru@Y=o)`c%uj?$V+Iu37LWe1ikhMR+GSeh{{RGcVu`P
zoEmDG=psf5C!qCBA*T|?dXqxyuZ@V%NQfYx&C)px(}*4o&*676x>1)%jp#+_BjDUQ
z42yPn4i5&j#m%8sBu1ogi)b@`(nlKj<DdBDC}r}9D*2;uFp(!%&ax28Le1OUlTCV~
zi0XUNlnokzK?8Mlbh4o2fwnc7n<nmR)+CW);3?!}>RL@6Vmji(j*bl-O((-xJ*5z%
zXhtyH*_G->SOfA3D3LIGK&g(16M_+)bZ#I)%_A__Xh#-R`^VO=Ko6EUhZ@FhVN3MS
zfuPxth6Lp|W^gooGp^RD=y4I+%En-sfhAvPEQIkWDzl-Ea1<-dFl{2CE<~@)G=x2#
zZ+jbo=pBUnDUt$H82iw7gMo`!1{SRt2U>80&G7sFD!V@mVL35M^A&F|Ice_cu~1et
zd2g53Lk6vryVc|{`E1i2s!=s~u}Anlw_Ru<7inMi+oZpi@|SvR9P3=kKaZ#9jU`pv
zjJWVeN1yo{i+7?hOZ)c6t<KaN57w4Uf?e{Pqr+xtvrKMhjk06+9DR7U@yf2)I(AR&
zT$MS-{mQ)jAf%jk13#Nb*6+W9g~LTaZ@EGK5yht<kEdHy#}3EpF=-zp<}@)cRy=E6
z{1APj^9X&Mtx5ca+)Ucz8*1xY$IEl>KYi+=9dedlq@VMT?*E~4lKrQK%}WQ$!j-RY
zlq-y0dN=EMJ)3Sa2h$gLwPC~38^et!I)+~~YH##OCSMcdGT!h_9;)x-<D_qx?P2C1
zIk%s_vH$gk*LmBWtpe9MMud=cESQ@fCiR+o7c1ud<P6-M%*$=^^4YQ?m9GD&UZaO@
zftOg-tb9Fw!tA}0P$12lDuc2$ti<;1>`dIvvU@g}@$Xk=DM}7>e;|HPmAlONoajOx
z80}f|hxwCU>d*gM1e&>X*r*OQ$je!j1q`&wqY{*Pv^-le0?Un?6dOFc{{vW00!If>
znn8_OfXoK6D{Q`R;%iuE;IH_Oa{<K$U|t|fc)v)o3l9Ol^yBzYBm}_w*MnMl%Tnq7
z|2Psr>|ncHraqu5ev5hdXWtf={}#NslAVJ)$L198#@0JP>O=JU<RhB99;MGf9UlU^
z&gQoT1{B68EfDO~rTcaV_QK<JCkqPtKS1Q3PI-wfJ}|`n|FnTl%KYElK>_`WZ6Mc$
z52OKsyY`dGzCXJ!zsWm&pR>!lwF_R$`v@Q7-y@syy?*pGDfZw4K)u}-dAaV1_k)+e
z{V<%JL7^WL>to$c@td?x|F&5C!A5V}Jqi%Hzy37@5DHflPYEEzaOySFFlW=n!`2@n
z)3~^M=&r;3@UDV;>wa^u*k`4l%%7gP%lpwB%#N+(R{&_fi)6i8TeL737&^>=j%D){
z)v_#rVs8TF{OA=0q2vu7`)1#L5Hauly(9=>thm&0YTID(PlFO^PZ87)8qGV!OJIeV
z)KZt;bWZ^-lkN;SVcnP&xo2;)Hqn9uenu+q#Lc5Ca*n)(_zS&ef)oq<7|K~g-1%h#
z`e*~S&Va0cMbH>|@)R8$nuBxc-sCNbry2$a;Wg_eAJ`wF#otc?NKpg3scunuD|0Hn
zaR2E|i7RDT9#4ANWaxdL(07gIKtiv_V;zhlX}<A|3Az4dO8CBp;J%&ghqVUn_{eTr
z$u}_i^cC-W8&4&yj?bXNp1g>|1j5+ssZI@g?$`DuJE2`i&9|1^YwpVEOX5^wVJ&+e
z1IANmjH87Ht>bzFne--{TLY2%-p5*oIWM@>8roN+_6m?^*qLzno}}6alYiGDaPa)?
z^i+de*wF&!{4v^w7(qWAwQ2I`2CHvE+?oiSUrq&gNd(5w-<7Z%`0syo#<vJ=Q)~zd
z=zODqLMc=!eb2fT>SO~RyWU;t*cIiyzXJ$VdB2qaSuLi4>;T!12w8H-U0s38F-q{Y
zRXD6CT5@mRmv5GVp~QJYgie@0u3W4KcXzxW86iJPehYn|C`Xr2S7K#u#`PtoW9V|5
zHl1p*23tn^tf72EN)355*2TUK@alT`TNCykh9Y<KOWmXSiCGcL6mHuTI*0~+YTGf^
z4w=0Uj|hmM^N)4Nl9gn5zT6KZz;Nl_21xB44J!EHHjA{qdvOEhm<)7?YYknwD>aFm
z@n>Wcc=+e;%b<fGWEBM}0BE%lCMaW4FT#Hs203WeBOR!y2m@~F|Ls1n*;8rSJ$rT2
z=yk?`*b(B88VL9X!fVb(;Y}5QW?iU$FXuyOx(N~MJ0A_X;cJ~K$2D)Xyscq1jGPY;
z>AoO_1&$1@ZijB`cK$wegp*Rgw}x>(u#SNhPw+T+?6#Cc;6~#5dURH(OH-rJE<?O+
zW1-AMAoqtLx3~(+2;KfV)u)F7I}OM6N$IbO`eyI5gdd9~Urr>hNIVFnvKHL;ez_?j
zKO8uDYzk2V_i+S$Cc8r8;`ziTiK_SE3lmFU@pg!x{z1fbLeaGdYn?Y%#=NVVI$3In
zmI}D}g`y>4IHM0%-fTFPh)L_M(TsCM%qDV$pr<W_qa~ExfxP<CCxj5*3<6VnV7;ul
zaNUS?<Pm1LFR75-dzKgXG$6o05PJEoBs%0wQVhpS8L??a^6LpyQ?x#al6SOl_=9w`
zFAER!m^bsm!}twZ_y>5fB)s2+zsRHTbH6pwS>do?(V)q8*^R&d4#dqUX&8l3G>evc
z8B9ke0wApot$d!m=)<kqyFIb#28)m2eBFYvPTbZR#Ra&9LQ3m7wGA)-wK57FmfYt_
zFUN2NXPCg{dA!yRH6(=GaLTJh+|anfF)P2M9h-uBJ{zL-=M#77IB6J^bbLc3GWj+b
zjlcB4L@4*Y_wTp!zqjdBL*@JXPbU(C0t>qeSX%hk#&UCIk+a;81_BRsZtp2;?!||~
z(RI37=MU-d#zl<bp(v~*c@6c4bqKawb-(gTBCM9WMjI9<o<~+R<UIBaN2VJVdXT=v
zGMrgeUfbgG3hjqfu$PCCb)87bW<*uv*}51DvDWe!$Y3X5NGDU=_;I2;m0M^SrHiPH
z_e|Uk$4H?U?$GSU$0{hZ;w#LUz}MKY6t;u!myybh>UILO`NbzkkQ_v2so9IINfyRb
zP>GkvY_$S%a|*s)R#E&CRrGF#kP&V`5k0DOWFD#9_7p{m5)%G1&2k0zUmPa`DjBj%
zt=QjVv&DT|Wg;UIzXt$kz6ey*5Y9x9^eouZzxkd|U;Mz2-z}JTQ$>A~YWpAC`2S3`
z1EY*hD0BC&VMc(Etz{K8;PRvG%NEb?bKb?;>r*$2?!nwSu*`t}#!asM6&Pi}nk#T;
zUOttdm&*%;)IXL1lMbve{vELWGmqz&-}QK22HVTE_HO!32eupk%0W*5-|6^|1G)|O
zj?B*GQvux$JU0Ntci#BmdTgCVu!F-UA@~aR5v?K79D+*P(GpIuo5l)y1ltqrLA2l}
z>^R|+>p)}_mcft9e+24kXk3!0fQbI8?BGuY)o*l%6B?n;^)Dm&GT6uc>tBJ-AMPE#
zMgS#lz7BQW6*lw1|NrY(v;MWwY=%1f%Y|fk9_5;H{tMu<Yekax6!>7RQaAvu%WUpc
z`yo=uB-z>ZvQqG!TIHgz$e=pJIBH)itPI;(myQZlJmOdC5PxqjOQfidA@qYP7t^eE
z<pLi@4q)#i*ywE_$$FFJn==h9OH`1xAEHPq^Od=lFr+HNlul0ST{^U?PQg6SXHoU!
zX_+}pvdCpIPYZr4Jx(_fr@!a(&U^7#M|bMZIJ{Ri)bJ8W)u?H8sLo)6FoOlXm%t9i
zL4rSAS!bw2ojQ`&LE|AZ<P~hbu#0{aid-a#?_3L0yy)E)QXYKlh3!$DTgVg~(W5ZA
zjb5BaV9ED$TuP~W!3<zC><r<gqYzACznReZ_RD@--0!;H@|y#qKHKY+9si|hNV;oe
z-AR_7WYHefF>8fXQq(shVbFn<$Bw&WP+Vb~YI7i?#h`Hf0QBS>2dp1A9FJrB2Govc
zKN>4xxyxbRVHEs!AUUcoyr6Gs0^~|Ohg6Z24%Z3JCzU=R)SSZWT25HW>AO**a1DeY
zTR7jiLcovsl@n`n*;!=!8}WD+Ah5y;NhP1Hu`XGtG^g9d7|CP^T}<#Tpes{)P5M3(
zcF*BTmE&Whcu@#s%a6zjeJ~h1qy=86xhaM8BskuK7~)veM<ie?9jK+wv?Wqq$g6_-
zSv)0j(wq=^#`|IM>Zp;7F-kHee@pyKtnR)=GGXOk`RVCMa+QNkuw_C=6|#J&%`m8~
zrUKyyJPxv@hU#|?6;rw|az6I#_(6jXG8}Yvzb>UF5Z4ITW$wwS1zzn$l!q(G;+V>Y
z#XU-dVGlVdr&ie6={N@8=QvTmM7_F6V#%IG7%FUy0|0R3XX&^9_Z4ua7>Zz}D9wnp
z90})L$oCeZMXadd)-}0=Rq^)Isl?I-w8R1BW=o^?+T`T}x*L(oZfe5tY_FxNM_-`v
zu#}E0n_(1y!^EJv)qevyjrg^kIycO+rJYn!r!qLoH>Fz>=wNY3I$z=Y5doegPjG#D
zKtiGfVR1K^H7U;?taYm~QrO)3q(Ipp^1DCzC6Q~bpe#V#`9m(hLHhk<zcdRw&2W8s
zff(JTbEs~WOQ^X)Da*Al%9@Ya3SC~-tufilVP%Zcc1Y8iValB0xZPt=wb^SS9<Mn*
z?Wyv~;dtJc{$v$$<L8jictB0o2sDsmq?GlV3Ga+^=uD5$Kcrp5d^&#B?wyX)E=A(g
z{GdK1s_4HC+#*L?pkMoxxbeVu5VC{xxPYc5fo%?qYUQ3}!CnI+06UcdVsvpHaQh%(
zWuf>~4Kq?OehL2|NKzfd5*qonAaS-%6;i)_UxQrN(zSsr5Zj*M^Q=7ut6O`TY4+o6
zBMDC_6fsA2BdgqHLn`vs<O&h(Esa8IFQPj$nchCDG6<|2$ZaD@9jI*+Il;6R9V-H0
zU%zGt1`gjrVL7dWzJznBJJGdMO6as(fiWE;V=}uIvQM(|44ASD4r+%Tl&}m7RMUlF
z@gk5D0_dA{EF-io9jP^AD^mYu0W$^KZ4GE$6he@83{+uzXIW?%dcdJF5P>RRQ<y&B
z2n1NI+3`iRI>vW6)@N7AD5yVLLX&U@7BZpKiVHr9UFdL!fI4*qj|`wOP9K_Dw01D<
zaInN*ea#N}u&5>{8U<=OA+{4C$dG9#9nQ`JX$9b@u?E@J)Rl%^HEMq8X#6@kuT%5|
zHh|hDO4TZIC6&fR4W>K^jXBex-xybL%YdpQWtN1H*UJDdt${CteuhM?(W<3fDBp9^
zH^N?27n&nSs*qUEu+RU~YB`z=jUi|sF$)0qRuslGQF=Ke3ort;GyAIm+$fiYW*;Gl
z$WN&>&I66?q2ZvdhGt#jzS)a$I3egw`jpP$k&hc^`=ZuhuP}9hMg^2;huvBVZ&=9&
z(wvD_3B?GiAVU>^l$oDSewc<4djQ1LeCrT=<O1b!Yc3@%E!xJQS`BN^#^N4DpoCwB
zYvDaI8$tNAg2zy6mOIKy&EbPA#G^3-MYD2$)o!X|DGtYoT@=SrDO5O=KCRLe@4{G$
z!#Q2LOdW@&8jA)A&i%fVy`D-IB_Z(e@HMbTzR={PVO|l!Gb|d?O;GQ1X9e0dP9n$I
zfW)Fy;_RT<g%};s*F#4ku$q%h!#(MZWp|c1x{TB8C5%WV?AU|SroK$V10ukpp%IBX
zSuizX(aR~_J+S0El)5LZ)S*~DbxmQRIG`LW3MX)w|D(ZGav1evM|7oamaBu&5(7U(
zx#;y1@S~_PIZ1jCz+f6MQzrq5v>iOqYM_QSjt{{#uR|Lj9fhrf))SJf#$Yam2{-5C
z&Z~hgn5S5yI^Gr0KKPThNf|mrePmJ;Pz=Cs2uCR(?X03Bo~U6Ofg_&|M2fFy7%><8
zIU?W7F)8Ux8ktNnh1;UrGK;2?I<GNn0nq~_C5`ABexW+?nIk&9kA)KG92k}nu!cX0
z_>C#ZT(EkUR!un`9-QQRa5X-c7%zaxv94I_$mrUfls!5f5fIqpsX?1SFWjtKb_P-4
zoOMnnbc+jdoZFea^o0<ciL)!yl98G0grIzp*l8p_tqcmN)7Ck03uTEE!9kkIgsy!)
z+bv40zlMyCD3KfwL}Yp^XUJ4`aVb!wyFE~~KO!OiT@7hGf*&-xRuvG&FyTp|Yivx1
zvactN5>9?#U_r<5>_sO~<gj`?K=TmkAg6^&RGNrjMDpSA1N$r=9a&B4A~A-{zYs>J
zNxgEt{xG&vWke9-`XTC!VjLsE?S+~~G!wGIMi4@-4IWSd(yW2$2i+Q=fS{eBGZd0J
zo>)hbMV99+#Ipz|RG7XjZp;Z=5hX)u*?_)+VVp(@&q7H=bd1K0QuQD?0S_W#u$H`b
z{?0>BHhh9#8XJx^?1?4s{hsO7iZc|^<6Y#NyV*T_i}BK~Tc)=d2LB`s${J@`$K{>F
zv5qGC(P8X{A50VJOI7p6CFakmYMj4HF8XBzpX%eX&-1yqi+`J(OOw8|v8ODJ@AGOr
z>9tIklY0`F3e~z;qwvL4wW)vUfb1*pYI>w;i(x*#Uf<HtG)ynG)QGX8FT0Swvp@`F
zn<{|Qf8f@h@>%mBF%B+yyGWy|93_Rvfq}^q+m^PcM4D~r>a4Ugv$XxE@BdIJd4w<3
zhU0ye<U0N*dohnA7*X3u-22!T<~`@#y^nv+4AjE>?s9EuXqYt>*nOgZxM7gMaO-X?
zp2s}|1uzE}rW<Q+8H$ocqpN0^_4pwMf#udFNM|6BROVyxeA2z;Vv5}TJ~Q?>ZzE5r
zr3@s>x$Mcd_{)9xduObt3RfV48|PFWC5xmnLyUM?Hma^FKi2NA<LC5!sFa&y`%;ay
zrc6iYk%Vb3SzUKCF59La<&VV^<ey)hIs?u0GHY%Oj5C(qGeSND)ArtyC*C!|SO(4b
z_AY1+OfZ_jiWwfl3aj87Y%&7k48=!ag7L3Qr3-;WGw&G1D}x+kKx}*q>^S;AK%m$f
zS~l=-s{*T^fMPGOIuPuFv3&S>3W4>WQ*8jv%RbQYwKyA;bwN`;M82!SsLdz9-u8YR
z75%Pyi4GvHp$(ZWfmg;yNKg;1(J_=$x@zb!y!i4x{)HcTf1OMNDSlhPCb^i@&wI}L
zfcn9e8T=O&-JYHu-nH+hPlj^m$!GO->H-`w$fWWv5q|HihmWdUwm^$w-j?o6ayEVP
zfehS+@j)-s!i13r?)78m6f7vVFB?Pb4Gv#-UrJ{#Pe7$Pap_=&<CIGU{`73Q05ENN
zR>$17r@!Q#zU9=WuFR^*>+qx6e2RP*Hp}$$uf4}DbOY-QnW4ereGTKvfmen)x$iMr
ziMcOPh#*TY`~>FL9E$h<=VfPsJeh)ljGmjiM!;|a9t$%8rsFK&E&zL3fI@gNYoOAF
zez*>>fYSp~x&5AY)%`+nw$gxuMA5@(p46kg9z@q{x0ME!PI{<6SMVT;#Dy$8VGWX$
zQ?zEurG9VISz7r<^3*n{j&F#howqdbct>30%(<5R$6SE-DzC)7NAW@T55J#`c@EH4
zE}7g$b4^89WN;H!2O_A;_-F?bZ{VH0gnN^laNMf|cXi6e?hv9yPUb+NeIP*J5KB&Q
z;z*2zmxA(+0-Y7vISvN~^odLP){Wi-9M>zQwjm$#LyYHza#GI?!I<|QD3V_idFX44
z>xgpu9S~6171+u0?65o67V|y}oYht-?GSNYJRexIJap~%U(F5PSBm}+1TruOxgC<m
zK?(dmTznG!te6E}oGGGco0R&(?mN<y8V$gY{V;e4zc07~$3;U``rYHaDE%wYGs>85
zD_DxJq;3J10eTO$l4BeW<l;ZnU|~>%!3CU9P=c=|3B~JVv*(;7v)kO=M@8iw#tPAZ
zO8d$U+l6!s>}KZ@$N2p97VCME#_1>I74ZXXRWk2jdLlQTUT>R}{&3c7=+NhqZxe`%
z@6Vuxiub|_bLBPAWEY>&kVF-|&oJ6uPMU$GvgbhZi3VTjh29-c2bA?;Xjw}IIERqq
zs95<t^slhuC>=%c!`=OHNYY(|4L%1)ZY;Me`99p*+ynttdl(H-XqZeh<C`KAoH%f!
z8&*YEkw`HKrzteMeg_3WbwrR`FeoS<w*A+B?T(z&VXk<J486y<(7x~_5j3|i*{T=i
zEQG=yY%^fmY_BC8B_SnJkdUp6XWI8AR||1;dmZ$4rrDbS>qd1(iU*S*2oGEjCBL0_
zL{!2OPgeA#vC68fhLuOr5c&|y9FWB;G=xfc0d_AqS`nN(LN1(!!N^-eUnd|GXhy_w
zmH)Jq;Xn9o7)TSLQ1EkwW>>lEEQ9^-7jW&~vJVMCpj^O?o5pnXDCrg8yzFBqj5Dk7
zq)tZAi+t#wk@L(6dNm22M8p?zgGFP^^Tk%au)8rhyMlpybHmP0g2+CU#KKGY##KZD
z{2ZQc9~Wy33PoVt1K*apw%j&EOwg5E1uWh|W^eebudR0D9QtYp`y|BtV=EY*Cbn^o
z*kqRQgYb)kv^lEVI<{^y0#sUwpnFKz7|W8Rv6_$2wUEnjRA3}+!}A2mT&U9TG|P)S
z!Vm-M7rxJf0+BYvy*bt}ioQ}oo=pV~<Lyx2WnhxiM^e^3<F_OrKTl}p{RymJL-#)Q
z%hsSKp;fkwaIVfahTI*PlxDhYny1h_Pl*9h(P06@D58807`p2K_d<9r;p{b&p|*=y
zz~x15m6ZZel^WD=t~pKNj*&tkGE1*aXKZY#$7+5VF~H0U$eNCEIzS;SID;JJSz`CD
z;_l^4cn+xdJAU~P+q+roMoD87h~G6cun2~$AW|l{cxOmuO5D>59}UAv+1L96O_dC0
zOuPs)8MHT8X0c9~F|IVTCwB~B#tfT_P>wI?_$Z7X<1#o@DVXzeZJoL7@(fw+=5(F{
z`0hp9)yO~%F)M{^3dvyi!8*+dJ|Xbyz`8c@Zcgl%8aE>;h|&_*mLNd->#pCrX|4g)
z^I;3?op-tL{|mMAJIjX5@BIH`jIoTCf1!NfKmI1b^i2=tcL_C^^S@!~d_~>Z^z8?x
zfPsT5gn={kFH&LP=$$wI>CxtF$j3If8KJGftMljo1^X2n7<l>5<=u-DY+(McAMq2&
zaPY;NmS2}+js|VLrZw%)EU&KvhAgjrcx?Ga0sad1KKP14_l(~7?pLrB#~1b#_*Jld
zzIjya2A2Q*7r$LNxB8JWBb@v!&*iPkd+2P^iRW*>TKJNeeKpN%O{64XQCg*bwMXdP
zqQ@Hr?DK2xqFHH=Lu3eCgT<6m9L5hord%nStG()F1|-xaLs{fNTVtZe)%kSXY-d~J
zats@1H#7!+8IXigSXMlJI2~`?uPSe3C720#aMv&-l8T#mvhJ2KS<XO?NuC9uBd=`I
zAEB|ss5V`hqt!p3bTa13`EV`ijzT*LnJ^4-*ISkhiXrLkcoYSOs_`<nE}SJasNLmb
zJD1}QP8KL7Jf=@#h-#3Xd@DS$fx_(w3?PsSu0xI+hwjDQiCw=>EzLQ!8A*p><Ro++
zW0ml^vhrv70>q=VR7xaxl}gaff)(xLGBI}LLFAyX*#ddaNn|>VIu%s5&P$Xg^SwA^
zzLN7!4toMS+^wQW;FQWAgz-nkIVhtih|7CWP!EV~tx}qM*+Rm*jIva@1_B{Fn*}*g
zt98kCiPNgU$Qol4>7?8YtIe{W@Ilb)K18_TfEUvNVTQV@>n!S1T7N;`I7>IytjTKp
zTCLljrrMrhf8>_tnD&AW=D=gvgl)&T@j_X`I071A_yssv8nfO)7Q?yL)tBv(&#?mh
zBcqYAVYX(o9{p4`zLjl-0#lnL3CRqYa7@VFgQL{37kTsv7AfB?Gmud}$0swFdnDej
zj<Ip5QWPX)Ze%mP8<`cj*;Lw#taUA~IR3WOwG+SB3}Wj?b=cnn5Bc7v+$N-O<5`$a
zhGuJ!oMXhwKn#VkGgW0OU<?Y=<1r?8;Q}POy$Ly+1B|A@)x|;l&X1$K9bgiqSZM5B
zP~Qt3TPAqFVxMGbpt%E(XZ5B9azVO=({)B`J&LgSuPEtnPRCo>MD^|jMFz`nxc>oS
zRKl@~KksE<(vlpzM9UXG*sO2S1$toiIXnj7y3PhQ*sOH8BJsPK=Vm8D=WB7ZBp)O_
z7i(1{7q2xVD9P>&MhDf14i$LB-xVNXS&vsSSw{<~S!dLs=bmR15Y!%&RhsUSz4`3a
zaBG%tC+Fp5?A-lvdD5zO9K<7-+MpzI)A8ooxfAgZi4TcRs!fHyde2$`m7re<&E+if
z7N4-kNGUT#;s;b=>5FhC<CjNec4uMKfa^f7HwWR?`c8nmQe_<USC;%5MOY^=DqcG-
z8*66vJFpKy*TAejg=fd^?J*!<zKn+#X4YAd;>jA7wP%-<s`5rTrOJeHW12Z8Q2H9b
z&d!m}_+QlEm5NKN3|<*~W*x1eczkpQf}h^11)hk&j(_hfP|H$KG;J3V9PkCks2I8|
zU(G>@i5qHupXqptCkXB;&JP2f9kDo$qBVnxX?D}fB$H13@qmpg7<*>HR|e!dx|KOS
zV1*&P$x5dNxw%nb-w4MdiF%gQ@sG1aGy?psK7ZdYX||WOLkNi|37-h~Fu=%}wKoB7
zB+#j|A*~FKMH!UtK-lPUz+Msm5Jxs=F1uNW?@zQ2Kr|E#)pl6cL6U-;1<l7W<HLQz
z8-<F!FfdAUSWUoI+{LH$Zo;#X!nhR)(6&7|sy%$fg04}hy1hn1_h@4Pfvp6bxwAaN
zg@uSBsEt1x)N4hM#C8~-2Jq23EO_w%Gy`gZC+B?FsNg)1h2Zj;hNy>$$#nHZFh^t~
zQxwKB<AIxha~lf;h<N`5!YCG2V%ohQd9Q@96FT->><md_odL|Kq!AKZnOX-_nIuS{
zR|4@9c(0-W^9UMt9o$QYNs3rXZ_uNiWGj@-SU^OrGz5E4DZ@>Ho!8N>8b+38-FFmX
zc%ar8cyI!CIF&n#<<kiIbLNzQ6I-IwPyJvNPyLS%qSD8wP;T}(Q|+!UmAMAq2MGO8
z);k<St6>bsy@DGW@zLJRy27-H#<#<ogT{$qR?zI#PF>RqK&s*BL5Z;s9}EqW#*(Fk
z4cl8MM5i}rutY-4FRW=jz|ZF3etSn`tS@oM(r^FUHJmA-HDP=zVf34I99z$IK{Xu>
z*&YMv0(gfEfM6hU5ZHt3ZkQ;e&YcmVLmxj)h|G2nBQRB3i$Jhy_82ZT+(Y!Lrfp>u
z%JoAiWC=KhTvyHxpf^qFptmTG_Bdji*)WDzONM^>`|nBWz*`!r*YTWKw7^NSkbr3d
zx(Sr5Bl>_$gVu!=jJ(ItH6qa|JsR#J1dY-R-98S|1P*=(l1?Lx;J**B$|rD+=m@r@
z+hHGp$-wLxCN&N_AT)t1fgy7Oc1vGBd~Zm@yob<%v``Eo5bm}|+xUn;=nyGchyySw
zh@Mke#Z>S-GTmHVh1Uok)rRGX7oUJzgPAzoj8*|V43rq?`zhS0;O}8`5GxPdwymrM
z@uae%@H(fw-W+;C-1ycj14N)FLAjjq0)<ADmf$;$-Ux|91=aqbT^CqzM{HejYC9=R
zGH2idjwc|h<3?cUfE?V`r4!}7!3Ys8WNjZ^!`Edrlh2M+4QIMo3ha>4Za5!2!o9kd
z+R74%YbOn~93o1{XP_Wr(QHWel&e^SwbUpH)?7He7VVwTu>nH!BNJdI#YRZDpkd>a
zU5!h_F_%|w66*_e<S5MULX|4>a%gIB-6K5I4RLZk!0Z?^vY%3;AveJIfAG(%N97#?
z7cH?y#1xtNlzxb<j>|&ENj6PLU({gdsaruA&N@f*!;dQoH$H?;__U)jIsiFsRKT&#
zh5)43Nl8SfuqrYlo<dv<^M|CEvm{z6g&`S16~sz33_nr6Hc<X*EuKGr{pCh<>@Fwl
zGZ*9FBH}M~L><sQ5GE#`v<Z4GoW;PaQ42vzq$(hLOJ-M_dIMn_bxiC_!CDjxEzM~r
z2dm8(?V5FrYa_btlrU6>(Wm8B(hNSVRnVuvze6KIk&jR>gxPPswd%n|GVht^A)k>;
zza!5tF>me|k_yW1WmYu|AWq1ED;s1v`Kz29rYF}?;{Y7o3W+XHMd3r+$uJG{3Q>kR
zQ7LP%=hm4AYqE*(_Beu3$4CLR*6VSHfpm$}RF9uW$UKe*xB~CBLg^SQ&cxkxP-&uT
zn9anedsLOhhv7{8s_bIf$H_&wkU-1YBu<bA<%g!K+(*_L1nTA=r@G40d`q;&x1SOR
z&%y`3TPXK${<Lhx)2zia0cqKq;^DX#H}{Lmpip#t*nENvdbtDUud~M~JJDpyh9`^}
z!k!ssOS1$nw^_MI8Ksi@36h0}^T`5mwy}tiZ3ls)_e=4-nl{r-jk3Si6#Ub0(-9c%
zke*_NcB|L0+|059T(J?J=|wUilzWKl!({5m7U{(DC_jIG>445?KT>IjVdGY*HPotD
zWA#+ooN3j#Kc=oH;%J1n_^!mJbZ~X_FUUK8{JTGprJM5M)}NbZz^4MZ^#J6+vlZhc
z{`yHk+P!zB`FL%i3GEg5O9H(9g5G#tWf=hn-vV08gDr5JOqQjK0<hyZEjDl*?EmY5
zqIvnR?|#GdXvWt90=vsD%dOO3X3Hmmfbmi<c-PNf+O3om*kp_%C-$bdh8#K}{{AP=
zljL4{4Q|PY8$hnWW@Fxqt%vDL93so@6!rYPVqlQ*VR7iWy}!N1=j-DqQO!*{dr>(H
zso4H&fj$)gb2G9*ioL)~o1B;Er3ski&9`;!d3Igp5byspLm<st>fJTt2)Nm6%smnS
zy~)Ix)IzBU_S;=x8;cWe(QD3L_D++!yN@XQmc9vq)eULH#6UlO^l%39*>thc4b>^_
zcHHUAdOlRx5xYLa=O<2Y`?i|9HSts$JbU8}-WdSLmg{G?{6NS?eSIu>nCgQaZ!}y9
zB$ik?Q0R({aEtKffC)izy%`2`<o0y#ykii~hjBpwY`KD~UgAL-Jvi<j=dQkqoCi|(
zra>T>UU`UPD6hM7_$7pyOu>H`io4eUUNGOCTn(QC_xVK5O)K~Qmb6xcX+T|~{9uEJ
z3mDVE9p`cKR}{(2we)(YZw)Lx{!#>1$@|5v8?+9uA;5PDkxL!@y9VfN-TXr>`ry#l
z>2<JD9ZtMM=BmoxFAIF8Vl+3{0UTE}piMHsSJysIrorBU5W~m#MQA}Qt9cH-wPwK?
zk#P^dC>6nVp#k)bJq~~>gX;ido24eev`b+g^#TPmiw*Tr-%5HErXYhcNL!0vK=*KP
z&0mqbom@)03snmLQv%f%&7qeQC;m^~-Uhmj^UUuZK(H5fv?*pdpocI-ab67JA@m7Y
zb{RGGVuk|>q$!J_DVy<XHzGp0S~r_WiZ*rArr`??A~2#VQ<is~#yJrw$x+hu#G<uc
z-+S7#f=ngyiF_j}${uZxw`(eH*6rzOELqKUdbc<C_d>Fh?cIBB&%O6t$mRzK4BmM^
zo{#_Yf1bxJ4Yu$5tGkUaKdQf_h8_ma$0)PgkNtdvPpk0xBUu{|Y+CCyp99Jdw)X>b
zsw&CI?qQJ9?Np&x5Y*U?V~R~_QrdVRG6053QLM3x+qd7EYcM=-dxVy8r8|n$x(4$*
zKW0+$7QPk*aZ|e<SA%{H5b1ZbR`F3=^(q4`9sJ#3=UhFW`%zGFGEuN~k-LUNGji#%
zXz@|~(hQ$cFYn_1obClx`NBy$FkX!Ik-&b-u6zqXcE=&+)}zx(L)BqWHw0um<V2qP
zM2R6$>{iv0o+Xhu`3V5Q=Q_aSlV-g<M!q5ZUGUv{oZ>D+&Qilu=q(MH6_QyWx~mve
z40(92lI^Bowv*<nvB}EYCSeC&$N(mnZC<!#+{w&mN+Y6Y-iE;aZr?k_$GSn6wZyZ~
z=Yv|_n&^&T7%;M|My2M5Bkaud95w*Q=i>H&sb+`~R&V$(CMmh0hO2jgTB>Kyuk4}*
zNxhf$b~;`62u=)v$NvR<&dRi>!GMS)L2s?Q5~HQ!J9gz$0PT7v0+JY|n)4bs1gc?4
zDq<VOBf^;I20hm@H}+zT-~v<CWQiINOmDk{4z3%9Ls%pA9Choq2R6j$<Osm<cKR8n
zmk<v`6Q~S*R4sma4s!caDOS9T`Mirhg(b6?CecVq5e7K?<76FfbH(HkbR_S9T+gkj
z^U>N{+uMq43$Hv<ct9^dCMGMdc4q**HK+T|;)u`ypCf^tS}-eq?%J2`2sde(j)`SQ
zHo*#xY4uruxKRPf{rX|e*dC*r@uo`+q=By3!IP2F$-GAGj7sBUp*J>kOusZn9d6(Z
zA|Wz~NuiyG6g>Pp9@S80xA3JS7Opy^0Z7AV-th;Z{>dcu`R>mTH#YTv>I&O<#)nrv
zZ_}90#xxvrx}wgzpKCA1&5b5D;kZ%sB?;MV(l@g)iIsYxq0!)&z%t<picTyB8?ELj
zIqZ}b`#lG1^Q_gFT)Ln~tgTdBl?Q-1`FAXD1;-FSJt3hKMm%Hj0|00_dXSqD#a`uG
zFLsUBLR_lfr%ZP}R(!spZGpwHW!$rOO6`-Y?)bwU51s`>;DAvdN!CX<fxYgv3{#b^
z*gt76?c<Lz$hxH!s64>j;w%lVWECo~ReY`w99NfivyK%Rfzyi<1LtlhRYH0-54Yy`
zV(@hp&P#E{m6(u#zE&OcnVK88dG(_{tc^*#8BQYVa^6a+Rd~D3*{i<tYh{rY)cLmo
zx3BE}wc-$}s>7{16$e#y2ne@yv%B3(?^X}IuQ}QO4!YgDN!6Hm>R@|2-|MQC-iJ-_
zKA_Qp8sDPy-l{U8n7jjAhh})MDr)ebD@yM-g1xP#d{2Fb$hqPMUu)m1t1fug48Cvv
zW4>S4TU9S^IQnW25O;O(tA=_<R6{+U`P8$ARPhOK?*k0xkE)+ZGN@ntYEZvMGtRvo
z-s1M2Dc>$xal-lJ(ci3LpV~0BoJ7=?w(?M+<>F%lO0*uh1vr)vd|3rN7qV6p7^%3U
z6uj0WG#M}E)#@oeM8LOAkXZ^4eaU>)9BsJTRf~2-m8W3-u=<;=3-aX_8vMa;T>e*p
zt@FXN>U$!l{0km9xA26cT3I2(T<`Ydv-uSR<xTAadUV(?jylbO%9rIjoeFuhHS0B(
z7mID?SPfg~LA__m){mMO_4G<FY<?90tBLD845}!t*KF_O=1gR2TsHOkbCla00=DUk
zG_jY%PzG{nujK*u+#{P?q*YgR;IKU|>l1RTd&o>U%~gjCX(!C5Q-9{>&3gam)Bc+t
zT|T__kEc5-=K_0`)iXZ3&bp}o)R)g%!At4OVI*;V?DNpyJUe0CIs8;O5UCpjzG=X*
z3%pGo-rcxU?az0NLqOP7#*G~diChJBDkI0fIxZ)6dI!8IJ=hOgCWmY0123cpxH-*(
zSFlK7+=e~g#K$Rq)e1MRh0ZV;3G1{mhaq~_nTbdVPweSb)DX?4bf#24nlh3l4bw*)
zF};`QrXAZ-liPlJ*L~hIFrP?q@nS=fT@7MvlTsf_lXe*+n|=4d_#7^7piNOg!Rv-k
z41yBW`7%9DiY60>a~Qr3xj2BcgXJA>*M}C<R?zMsGXn7Mz}{nCFzGV&9EBwe`5ij~
zCO5R#s9p9Vn@ZL5)8o25KxZJm{rOb)BiwDo1%j8B`^#_M6^!%Q5;WEcx))t<{8E(;
zJ56}IVRuaHkt%$d44}Wrw`W6muRv{yIKU-7vxM_l9#Zs2Z?x8@$}NXYl>-B#E{%6J
zP#isK)VIrNDI=uJ!C@ZKC*)KRo35OA*any&$9&Oh4`<UF5Sl(cYld|(UNdr)!Lla~
z1YdmQn2{rUY!sJtE|A6mVW;>`+*2(h3s$e#Wtp)_FWOCmRS(Lo$#u`s{S7`P4B~O%
zd=1asqhzsVQvKbyM816hd|;Inf?tIB6ARt;m^BmSrJe>G8s_CD)2q*_WmE+}=wD!W
zwZ)rus&>Q*_pJNP2eZ#Q%^;K>-g_dr^X<SkE)tT6d}kySyoc&ic4@3>geReC_vsT&
zmGxbQaZOsUr8+!Xp<HyV0IqmxB<usuTx`mjacbX3NTwYN_4KUHjU1{RJ*wK!OnGqV
zVe^`aqh@E>fS=qqQXcS}afw%2f7ql71!CSBpY~o)6`$@E@|^i#RqihBuJ!-*<BvK6
zzEScWYCgW64i=rzt1qUKodHzll44HnuAK-cz-zNCKV6t?f->21uhldlh6cS>`}1kp
z<Q&V5R{IOCoZHz1b;N^fUj!&Fm4~dcdia{x$Xo5Zo9)Rrk9uPRTV|72WnO2SPuZ2S
zH0g=<Y1zh_F#~Si8q%L`kG#Iu`~vN24phExTL#VYbc!OCr|pOs3cU+yDL=X4&PhmM
zVVmU>7V&o091fz!dUWNjE<cKvRtY+$m6)h?d10ibgT1~8C@YfBksv>m(v~s-#S;py
zMUl>W%t!<Z#Dw-6(-;pTSVEv*Yey25LE7hN?G8Xr*_r^(eZ)*OjQED&qk&^4qBIR-
zs}K8=6@yItow6fB@$ucT8OLQYVsS%N&n~g|ngnCZyQM^zOHHhez~(h$fRNK3d(xwh
z6k-ma+3JO|7Z4vv##&g<P#(^4@N^!i2XZZ<F^pIQcIjmnNlyWbYT8aBV88YDM>5eC
z>{E;aS%K|vbMZvkEE}=F!x|h8o1i@_yNHQFKPP;XMjj|JPjOnJ7zCW@#t{rR7jf_{
zO8Z2J*m^Tf9cTkhq5%_5MVcm}EJ8~?4SWxL%J3+XuD$y?L$kXZfJV&gPXEME0a9?x
z=)3Ghx@r+yg87u9-SIR)4C#anBBr8r5VIM&s=Tcp3}H8u2<ik_O@lmSTm<(>+a4!;
z9!Q9Yi7~T%1tfh^SYp<wDma6(y3ngxn?s}5efO)nV;q4M>v*macG*(su|p;`-s$Pp
z9@W;)I!2-+0@a_ZQzP9VyDteqOZl0KoCOOCwJvz0=-Xl(ajs$}USdKI$kGCL4j2ln
z0X|9OBu2qoFN6+z7L)XlPQYq<j;#~d%I%T=^&e?8cYcPed&uqD3PM3SZh8Q;3s{{p
z6*iU>psST$%kDLq0P4e195xZBu#s-U88%Ja2%Vsx!81WxCxRF(>cdtC&L(Bf;f$I)
zD@6sn1u<%(P-+M5siz|>@S+CwwrqIrn)kc>*o1gPl;XnmnsU+r?yvb}S5*Ct!c80z
z-PVWz9PLtAoEGvyK-AjgtVxArvR)z`P&y*RCZmG}yiso!?}98mTGzU~h$?fddufH8
z(dUgR!1^?(vp_ZDVs-YC;l-tZE<4#Q|7qt(EMZH}VY#E;*^j&IFvKV-v#MfUZJ=>A
zuY-AG)g=hNfxK3n%^<|3i9t067NlAc#wsUHvN13~0<~$-(0YXuU*(vdq=rEV4|T8g
zDLN85wup*iJZDE&KlKqvo|+@59idI;T~88-aNx^>Cj*BnQwFxJ%9rrCK5cLH#9c<a
zX)4k%Tdafn&>;4nZ1Yy?-lM#plHXDfDMUAr=k8Q)U!bx@G_A@1pv;bx(So7%uU!3K
z?<~G;Q#L3@tp+RQ#{#XOwa2=Ytn7)ni(L_?2rHc`6}sgh9Qr)qL;?$;I#Qs=LtYHT
z)8kCW2z8ff87JXggg8$diC*wX;0NWwIniJHEoxX7BN+3%iZde&e>nWv!jOn(?+$^{
zH7Uc35iLO|wM?lXx{mvU(ST*<GHh_I&SHQO6ADuAZ&!j~i1G|<bM{6kjgS!$(2!a(
zSQja>D?>HRMEuIpA`;FVv5REK@I=f%=yfgHKl^NqX$?87E;oP(qRt58jTZm~5V6lg
z9)^-#j17!SC8xYDJHk0k%y!^O@nG*mPwOHfG0;0W1Rb79EJ3TVC#m5~2)0kZtGQ@8
zT2bWnL=5PpJRuVqUgC*nAT)2=c)xhM{ah;hq&y&G_XYRCiRJ)&T%<#j=-=zhHDa0-
zx4zhZ&{$_=uZnTIJ-1}+Z6m+_^}WW^R>f52T=O-e$A`?)g=E{TzGb#g5A%@44(R&y
zUh}GHd(S1e>V4yt;ei7cqD>9&W6;kpn5)dGr7>@}zDPmgNAt7-4bw~3l0_cWo8I3y
zgVAQPmts;Cul)~_gFx>m{=9PHfPQIE-##{K{Ntr@uL-DX>+$KPv$3}@^+#iey({S(
zH?KRX!lvoy5A1Jd-hO87&};3oy*KyTthHr+r~H9ET`(z=7TxNeKj&sHi-Pm|h?w5n
z77cbiZS-~=@Jg2T0!5#;pjnZH&8-%p)T73t)^5&PUxnv|PBm%xOAgSGR~aA`ENPDG
z@^PYg#wRLPv%ahOiM%=c=i^I@=NaA}{Y{x))u$iTlbg%{9QY_mc0PF~xtOjy`Q#QI
zl`r{F@1J(;H;MAzfmJZ%_4W!ely?pqBKPn6_PaNK@ozzITLp%_UA1eqk+RqOph8MJ
z-TJSW7yd&B7xAP*On0a@J*t|+6k&xAG1c1;t77in0$Z)gR-Fjo*cLshRg<wa`vGd(
zDs=p-FSmi-mXF+mg<DlC6r1T5Ke$EU{S`ReCdZpnxx3!r4d_a<0Zq{xcR<<upG6d$
zRAjEZ?$%BUC(LEG@1|=VKuSO@1^4?w&~wvDl|K5?3lvN}k*m&~9J^KF*rtep1%-EO
zTG3j!KkdA&&$`3VYAK7HJVP~xpmfI%rz1o0t?5w=tI=6lY;UA1)Ze@sfRF-ayuQWn
z)ZOIoR46`C@J82o#*YUg4|gP&Dsh0_<Z0`)S()X9fHZ*z24fEYhb>iFll=SAH}(1#
zS~TH9#`edP#+Gj-F9ZB;YkKj6VtDbXo35KW9XRi8-Bpa{=EV=CX9$0!A9mx!Kd4@6
zj7)UT7Yx7_*p4S(74rg!mjrJCv(kzHje_q2)Na?BrI><RVdoj(dmaD_Y|$17v(+q_
zP)HR=FmJZ-BC|y@y>N`uy4&lrGFt+w`ioK|g@i&5gK?Ub<WeJVR%lrIz(3L>is~zq
zkB?i_d1eBZsj#~}=4?vZm5a2PFMa39!<gX@2ZJ|1`?0rdeL;*gSgSLlmFm8EUV!t0
z9-aSPaZHyvp^v@D_qxUNJHDL<wT4U!^*9E`M8<dwNe)rABfxA(ktIQRhcqR9lB{>&
zNRrffDOH<Om7~cMj7jgdD|KqOS}f8V>EfKiESDO~UW=qWmb8awAZJ<?%81Y^%{vLi
z_Wf>HrWsRVXOr_{ICv^%JQBS7r6-P20YF#@^;GE<@srv}@Di07&ado&5d9sB8Jt>F
zaPBEPH?N1(W2|HuE^WrpwGm)Orn{sOk_#p)4XJJMDoJHd+OkqH;ejTlT9G-uS-L|5
zX!2lgRyu&qo>RTsl1csP^w=nI>SQ$BWg6v5pAAF^Xf^g|o`fF&&v-6691OmAzcqM5
ztopBe%zmh*sXM8FK<N%7GqVx!ii@C*P$}<b6V;z+bVGPF7f8)dMo8|F3QZf+6JsTy
zXOe>y!S*U9*)bZLB)2PgIznT|v4C~j{)z3z6lJ3s<JU(gE7TVnd(KQPd-|xp5u0pS
zf#mF~#e_drBFd#+Pj!)`z9OM;d@pkB{!(zFe~Mxefpg<uAHFo<9T7~Lw%&Ed0q=Lk
zh9~S?G-Sl*f9^QB5!YEGtn))-j78N8V4Y%k2jMUiB?%pr*cp`kj%ZuW=XU4`)0@+w
zo)7`3Byq!s&7_RzCEKq2IiRgZ0R=vn7FIOJVWbaGD0^%|JE(7eT(PgAh@VPsFHvul
z*a(FPR(MYZ*84#)`1Z|c`v`9KE|X0eFu4>9nW``@oB5z&+n0C6B;_9-y;!#*4nV48
zO3}g^J@V+VF+5Yc!${tBDey|fQp{w;V}VPkutSvgH;UW!E+&ym8g%N5aFg;p*6nj8
zDsC{xi%EJ_Ru*@)`|<8JPBMK30oDb<*Y3z0X)R~Op4w!+8wBtEm)u#a6hcXuS>b6D
z-N*Cby6m-{(DNS)tg~OvsB$S<*bOiZf{TAWmrtxzgwx>*nsum7RTw_ZRMSENE?Yth
zz9x?PTH>T`3}K;RY&-|UAVJVLT72yDE`_hPXZnUuJ<uL;*3E#D9~0tY#9!||6TI}=
zN8k4B(DQ7|38017eZ5wB2Yg)qUQFwfOW$rpozT7%M(}}y$w=3@r2cLn_~zKv9>R?E
z_+&E#MTwtHd&7-VntBZvG`R?2)gmvcxh_bINxH3vRF<d=VYmR_6vs|&7hGo7H}mad
z%cZDw$&Y;p8cXqV*`itlu?CJn*_e^B@BSqAhgNtF<s~R#JSy;Ic1`ugQCsDs)JGV5
zN(&EtS;3*)D6s<xmlxO-SEu)uUMnB%2ZycGu2$8WR^|N5K)AXRpe9VAQPbsh*x+@=
zt0l$zY+a$hI^h9b-qMBjnBE>Q$&6=8Y?m$8u+o{Tsh;NMymTm{p1bX@Kho*kYHfGe
zyOF)cS9LyH`1Lx$hezH&P<;xb>aVKvf|~lv^77_0=NBBsSmk~H9gcguG{gTj@%1*0
zdkYP2(O&;wUF6YE&Mdh9Lqj?BL8*yXZXwfuqcFqm+Q;tS2HyVFN52x)TyYx^<p)<3
zIR{w2|2GdH9p%BOhaywqueE+w2D0|<KUu#0%isJKs9)g@{`#}tul>ToLdbmhxCPRJ
zP(`)h+V+tRetDA<;Q928gw{q1B&;0ppLe^jhWA4N9WB$<#5&@>H6Hy`#Sd&Rq{CV;
z7RoEZcZj@0tMOoUfjfgQ%5bquk1cvs_YbFM@qsM-9||d!<9p1j;jB3%BhzwR&fq>y
z;@6Y4E=rZD<&D;-^?zzUHGZBhjQ);+r1?c7vMxC++c#U`p@9B%VbyLwlfFWG-Kp?K
z;omtpWLBCAlU{q-!YRf>awCw7q^(?vC@>%$tf(qSw3O<mu&V-X5)@fAt5KQAlinTm
z7)bfF*T9kA2oD!b!E$ElryWt4VH!>vPStb;a2nJ}w!iP1p*)^fG@hMuXDy@_BIH@q
z6+O~UK5t3)XS?Gf=rfQZM!YLpzhlU_kdp&_q|P)qwogVovsl*SD%aT~3m*h!*p~pF
zz>anTib;a3dNQSpW}4!Qp&E}TJ)qh>mY2q%g;k3{G^U#Aopxy{E8zo2+n@AG(Jgjy
z``Gp|qrNmk8^Bs*D7a8I-0{-$rZ*CP_cOnl8S%w{(I_}G(HHjRCOn#SZIO0;(H63A
zq?}s{t9^aIG>*Q-ZXXHHn!|p(rIMe=1|&#`6;M*(c?f0}I9C^X;~Bj@R;SdYw}^MY
zlC9=>UfL+*;2I$qxptOh1f%qh6Fm^v?N~#emG<0NCo2RtH6@#HNpbOwZ6Vc~2bvRK
z+N{zxRj>fjZU+fU#LD7tXtupB9fp#IKhQ0K6XjXM`!wVpGms9xsHZkHuy(*<z#H|7
zD~pyQPFr3OQceTz*ooHwC2)o<Y1WSpl35CZ0I6*Xmn`%GPmudBiZQMI&UXvfoNRE#
zDLA3XF1nX`_qn0oKS~X|$3m#?8=dAh{oLAzZG&1CR$o9M)cG9*b)?xHm(S{h{-<fO
z2*Y-xrFVIj8Ace_Sv0&!IRYzKNy%6MUrT>J?akI9=iuT?`MUQ+`I1Fi>GM`t=pL(|
z{Ihb2dnE-z`bPWOrZqG!pV1xC?5R3bj%AiY3NMU5?EmSGyR;c&)Zgm<zSwG){N3jk
z=NvDXS&~s(%U&th_O9LAc2(Ms)((lq;>EUsNTyQW6;GIo39ms{DH$(ViRURlnNQ<$
z>zk~prLryMNI1j?$RGfi^~&Xo5Na<ti;F>Xi!3ck8|bwiy6QK*zQ}+VYXVG_KP~Gq
z2Ko2d(Crsf+m7lKAqE>cTMngk%EqVc$P{^N)?bhON95i!j<-GDRrQLbd6TeYg(5Nm
zlmKJ^w+#S~DWdYNLNtTmJ_HG25sR=Chcym<hI9h%VaZwcP$Qs-Ri&iiPHz%0bY1!q
z_LdP^eu#MNjwRwSd}}}aUJNFumZ|yrAe{GN5bUlwf#%j@TPP`%izM!@PmCK~9yJKc
z@geX!lEni8MmwdZkeXuf6x*66uK1@~Vs{fkyw&Pr>>H_9!B(^;Ba>b@uF4dHgN6A1
z#G2?`prq?G;3<Sx%dJPcqKk?6XaDZqfSmnfF2yeywc5AE-Ls@O&ww`5S&qO<P@I4_
zPsgn=bU9Pp+@;XA?KXrH!hwcTQxVxVGDc)4ufrRUcgU#a@L6i!=n-Y)sS|9ai97Mm
z$p~<q!2q@3PySuPY#aHeNz_=f_w=Yt+%*gTaXalflfeoau>pQZY&-yLK&J%#6Y!Vw
zB7s?k&7E>GVg!VZ)F2q3F$`^A>x!r#2_LJ5PLhCS#3!^})Zk6XB{@MR`fDCRn)rZC
zR3u<cZ{EAk)E3G8F7`)><#`Ee_ymf75J$WjdcIh(KS8-oYe_5WLXW^ara-4%Ap@dA
zpVf6e9A+3LYB?6ua8JDQszB9mXmZZX#k%bc1iGTof&_g6jBz88O^_eXJOxgtWoVWo
zY;xVUo8`&z0P$q*SuXjyuSWy3nbpf}aT(MV6)=co2ZBmSN5&Naa|$*G#g=>*l0Fn0
zv?Q1b<a3Jx&CMI_q1W*EgPi1r5)kYzg8>!MbZ3D<&0@v128lm_+|rAJ<Z-i0F$*K8
zmz%w6U)H19=q_pv%Y^S6aW;Zy4n$-Ki}R@Nb;08dNDKi@Lzjjp64sczkqy<55lJ|g
zJp9OTUEO9m4s#h+YjBrN*$Zf~$<Z>!Up>Pd9$<!N3D#?pPv;!^)GTNVcFW1w7HRM?
zV%(OW{6~*ObbD5xDBdv&uf6EST5}PBz5}i{9O}tf*dcXrI|Qkw8)2L6RlGz5a@=GK
z%tc8JMUZyWky{{NanTx5#P@)MeaH+ckm47i=h}&+USov<vbYi`|1L^mct-I4fBu=H
z9q=`iQ}GPt3hpf8j*NFf7)5z<MwEpFCDe(8j@B*t9JROkv}a7f$X2!JMC^d)B^)X#
z6(ej-6>-o@y7}pFPRdEW>_$S;1>zxv2~5rBy`J{N{yRK^Dq*puZpMA>5}bK0n5I2T
zuii0h(laoy2F6m5{$_2M>qf;3ijF=o+DzPWNqR%$v+(8_2%CXXgSxU;tO)gbC=C*$
zBu4BdBb-Aum9=t5%<!l)(GMkLXeO3e47j5W|2v<yP7H^0CkS4Al=KHI74}s*)Efvf
zgoEKd19r*nz2=#&9vr1M31r}KGLnwy&*+Jgr|<A&^5gK_sEJ-OLDuMnu!^^&VfIEK
zpHvb6({5#uL*26^^{BRKi!@Q+mJZvU2^=df5604d5TR7J=X-aTqEf<)9i}Oz*&PQ>
zEzCqRUd+n_5z8%-$R++uGOpWD-|w_+_`(rh3?(*VS|${FXtb3w`-b#^qx23fMn;Q>
zM(n!bF;#|Q#v>?dnkJ6Xegl4UTpNgK6LKc<%dbGAN{$-IH*@}@A5Z$f-K;;_ETzU?
zd~W2#8J&9J$x`wi{m3dxtW*YG*DJrbRWB8idpeG$SD8>u|9m9haRASMUAo;Gl~!BD
zTG!$I$li<jcy%goWo9W)aF4f&x<qX7_Al!D(|U*5@q#`u+d*w8^N+lHi01x|Rlibi
zrnf(DuChwK$*<0KbW}VFf%VyPmOtvHt7ZKYUg=*Dv9#KA-fnrKEw9_j3)WHVtKLy-
z?2_E8zlzg2IzU>KscIr!|LwmR_9vR%PxS0B-JKmAoiBaCDfg!<4+VC1v@C}QWuJaV
z_jhMrpG`kQm8Tc`D7@6^jajl@K%Rw5gJcC66Y}4f+#C*k*!^*{JtmEfy4k)-S0L=A
zf$@q=n!T$InXA%U$S?|+k6v^8?&c~hY|E#=nzuUkS{3VAed`0s7iN<so$eOq*QxbT
zS{kVE1HS0!b0c2+Ke1-@ubafs>)%(z7XI(345W?*2TCai7N2uyl#I>ylY5JlL!ef{
zufAl9)abpF>Io%&P^49hx(2G??uW$<*qp6A&kvDN2)1>AQuSpHf0TDv#{VPGRgrhM
zdiR=mu*di^RvF~7dVQCy-@~;Jd0hO3A)Mr+!6ek(tp2Czm<Qx~xiRveO1t#j<%x>@
zz-f2nTb~*++~lJVtP%AuP#}FxwO)Sn@%j4?S`Ylla2KpfHK{i$KhMi;O+By6wUx?h
z9kA`k>#HOpZU5cJFE#cKsiFyoU@wlQt{=5dDjqELNAH+AZF=R?mOi@u9$gNQtUYU0
zD77%#``p-e@VeCZDNuRH`tgoZ>hud0=(aqU-VPOx;tao|Q=%ccOTj%8iLtrtIsIV%
z$DhorS_|g(<UZ?(Q>25xR(`#{(b^WA2oAz|T}gchvBvw$Pp+KUK4KiGh21BFws*Y^
zb??r^f5~L*`q=ZU{pj$2pbYAv)LSF9%ioCr0rua)C#jMKP$!pVWr*H$vNXEMJ^*cd
zJJ@iULJXbI2j}#M_2=$LohGK@z2njEOo7ynddDQQK31V@ad|Rw9vU%VTBD0wNdger
z6(lT#%d5`yQvYgmv{CZsgZ8m6CXWXyIlcb&T;*HayQLR_PP@#FfFBOVD7mo1$=rP9
zpKA{opQ?dMt_H$-j5b!XK4?ahzwEY$8!vT7>m%96M-+J5SZ#>+=*iut{lPtgCf{~m
z4rhK#(Ub#jinSX413KaS#rBgB^55vDvz9)h!x^p|W0e5YsKPpG4u>U&rHV0tA48kw
zy^DeRIs+G%MqL9oH}vCG@N)w*@`jmw98zqs>%SP>Y{c$44Leg6&8^Iusl4^Tqa|b7
z^CHF%7r7xY?BW0P4+H=AU(hzKp-<PoJUC}#dt^OjNUO!ML#2~qSdQlWkpo|JHb+n1
zTYI$eK-8L0ffdM=ZNsM+rFH&JZ4+7B*4S4W&H=l7WK<c?W<W1M@VW2@I{EkLjX7OQ
zMHY1n&NFDTAp>T$(oodJiV2`ZMTzgr<fAO+tNmyE(S~Q+?PGfPY5%5WnfhC@^2<`a
zX#qOVw3fn#xO!sSrts!J_);SFTZU17BB_AY<Va)Kr#T#@a&>d~)W84pQgkhVpj-DJ
z)6WtSFlc$_JfO#ul9@jbA(UZ{QVF+WS`4JS)V-HnPU?h@9!=VIr2@d|Rp@)u4yFta
zt^+>vvZKk!A*vytK%rIicTF=m2A_76stbInTV~!+2zyW7g4?a;T`zUB2G7}s9AqM1
zWg|gx*ACAuJLZj<_TdSNESCR@O*CqN()P!+4OMCe)K7`x$l=FFGz!a(H2&CHL4{>N
z>^w@?*+6s5ixaA1@96e65g8?X5<Fm|K{+h5$EXjPOfE|=C}Er_8gvTF;H>o=OHpCs
z;qDGlW586aLm^z%)9?usIXpITEC`eAj!vr>F3-Vxjm(_JUfJS35)8&(3Sw6KsbEj-
zZi+>p!|7CQ+e&{--RMMYxcS?ZyscZ;ySsDI=l*JBKI72zjbd2c_eP!32kfOqFCv}f
zjW+Tn`xgv8>JPf9z@fc0S9$RPd)baq7}(klDFSSqBaBgQ<rT!p1VeNNpghVl)W;5u
z9@9<pEW~H>2P0nT(YDZg;7{6E$I__iQL;b)<(sP3@|Ion=>da1#>ipJc7`|K|H&}b
za7FQS<_P8Z&e+Vh=?+_~tI^Q=l7HuL^Rs?!-2PVw)(GL8Y$GQ!iuGhsqJea?(Lztu
z+)f5YyeC#{UvbHg4>#(RK`2!So-laaUy#+4_OM4zTe*iILEK6;>n2V9h$%;kkFg)>
zPl(nWcTf4{k&Mx*6hLgL;#o7z&>Rki98v>gMPHoxc_b`_)mo4|D%M*iKNNoOoEWx6
zPjvAg`eJx|VBRnq6x!Vp*u{_H4+qeIf(Ry<484uk(ViIXdSYk8uJI;;b)xPVvJT7^
zSJqc*aF3x+0U9?g2|1~&nI^)s)p927N|k6-AyxAzJZ}v@Rx~Q@)>LywtM``6<Xj~d
zegBh-cPw^8WU{e9%WddQ!-WV*x4w_XINQamU$7#^NmMHZx6!Xaz0xFa60Fy#LrE@Q
z=?)_;wR(t%e-rIDL?{z57l>N1eWB?B{-PO!e;nGL4klcN<OZXcG{F|=t6qnFWR+!~
zQp#xNo)Fm{(^P#22r1)DjlKZ=d#`=8{mMg%B)hj&Vxd~2zuc`xY%pX$D0=%Dl5Q2#
zR(*#bOCa_tKrdw0|B;?>A716DU!(p0|96p+s{XL)q4F)3?()<XsKW}o=KHU)bn72h
zY)}Pwe>YU^<!%*hpwz<OJ)~Te)&s-e``~AAjA3#6Kk$jDW`FpX4}Xxie)2W8(Hx9H
z3;zLETX`BjzRvYOx_vd=L9KzK(-ryft$*7O321|V+w&hh_u1q}NjyC|>Log2V2rzP
z{G&p7x(B>48wUV}Tm>vSLpP%m;9X9q6B5K4b0wP|w}Wm_p6Askqz4}kh^tSB0aB!b
zW;{3_*+X_Hl((zRre(CpEW;^9nmg-g$4#a+C1?A=j37&G0*p1wLRFL-iVn?|5v9rZ
zuYM_Enkj78zKCAI`LgbGwXmSkt}Ku<elJ;xX)`8+a4STj(3AAi4k2$DO(q0R2ua9P
zGES@|50V&+f{sWa<tR{nVO)mOkpnuOBcj8IdR=!IepkdGom0bQJqlq(^|DFCtc>F|
z?Cbyh@8XCxJ#9;kOh+>wY!X`7w}MyJjG|%2@ca@MMBY_qF%=8(0XfPlZ4?#|PM{Ui
zS%49pH3MKwb2OA(ByQm3DYlwsy&fq6uu=3AMjhn&g4a#^qnSuCs)rj5d(PP@5~j5>
zl>f5MAONtt)P^ZW<?SsJ_C#oG1;`ON$q@%$3yxnAx?{A{O+*tq(3K1*{lJV#$tbko
zkWTwN@)8`aYelhFaZyjvUR@R0i}<oDT8t^YUMo-5BHp`y@MYdnL{&t28B1D=E^1u6
z7`Nd^g3iY4BBD94`gVGJ^vW#cJvBgA(Vigi;IGdOLtTaoq|u^@b^t@MzH??6a#4#q
zJNCv_zU$C92ok=iqF!oWS`(ETKK93S63Oi-_wJYPF2)E=hEB287Vn}#k?vjfBYAI~
z&^8(a%{JKT&xm*Fr!H~5n_WUT<1;`T9(QcHFuzD5lU`ViHH+R?BEeMD`%jQzwJsUN
zkM$Alv%JUr_->esLov|AL?bpNDq*nafB8F(R=Qe)9!9Vtw$nD6-G+JE^4%jYjgy2-
zz?7mbmo~RZ&DJzD$@)2CizF+5qqS2ejJVw$ohV-OBLN7s8<Ok`U}*sPn5L`Ya#^-D
zDQ#Os!u93E^X2d?C`kQ`84N9&p^&1T`ptXFp|>e8CS%Rv@ZG=qw8j>W0q{*mG;q$i
zG_@2^X(%1m$YBOUnjzYkY8-T?OR_+dph#MmA7`i7Kn9`K#cG{3$O-O(rbVe$H>xhC
zO-tjHt+`yL%-3RkThATZ1R*~=oTMdN4E4yRT&jUOnsZhtoC77OfGk!h8csz3KfNfF
z$6^3CP?gmf1`J^r!a6I$dzIQwAk#)fC^W#0h2?;Ql{n>jG~J7#Ikn>2h(Q9qXJ|kC
z<ZmQuk<;o1G&|Hx=`vDonZ+V?-2nUL)p3Pi#EXO6mu(k~fSXdGGpKwC-{co<@(33N
zkBzdOHINcNBm|(~$tZ`iD+ZCNi(*3FyZ_?vAts~-Ymg6hcx4pPJQsc_j{~yF+0c!M
zqfUffjM_|*#+(Ko-xy2lK=HfB&pbHn1dMEUs-=W<bVAd9nI(6^VG)3N)?z+D{3NL&
z!kgXUni{ntv2iS!e8D#WL7ps@qiR_gnwN;VT}BMfGIY>MN5JRi#`=(FLtK!zay1_B
zKL2BWk#<qmDq=Fy6{!c(kAat^033_4qC(HKfR&GtC~kEbYT0e_q1Ag87dGHR6l+bm
zD`+7{M>SLP%C4Vv*d=EJy5a^ghZnY9&Yl11?|+bD()xI0Z|lKmK74S^TXUtJY2Bup
zg<m};)t!Ivc=zjHK$NH(30rS!U68>eV0c-PKXj?t5X^^~d>-nD)@Zn>`a6$XE71CJ
z(s9(~_x#6|Jj<ri5;pUB*6=kwVHXsF3T#W?2vwal$q_J$A|{~KGD!)_XSY60=Ly5{
zNrK^dK7vogGhsQT`pemNpRSo*(Y|<wS-$nRPu?4`rOlfODuG)Uki@}4HKuJ0UkcSH
z@+y^0u8XA2HuIe|f%?dY8-Ss=|5mi@5w6br=BduVF?=@+xmAX{kre%SqUZJ>MT}C-
z@oj{EZ@qDw^HGjsz|C;elQNPp<T+c-2jU;O%h1(FW1mLFq?#-425Y4CG>4Ap9A~>2
zvzdK0dupe%mw0Y68l3gjQ=0de$5)ch$vVtIA(i?)cu)-Uj34WY?g?+IVLJSsi&9)J
zuBpGTxb=4gbf`vZQ^1ii@_w@PZoR$Qnt_esKUe4N*439KCwZ?u#|*ds>d&^L@oqNx
z?k_SM$eCL!%4e$4v1-T}e&AWmca6`DX?&{M*xU*;&XoV!v)s4hoTGQy6~DSh>%Lb%
zbVohTM6i>KP4%WDJ{R7qZf}@%;?RI7yB|D1#N~PV*2^W=dgg;yYjysFywQrSr$=sI
zL``t;ZvLMX)!j_0sW55$!W(;-NlhDiUrl5XsyE~CXvHO(->9pyQ=G)P);y9y_c#A~
zNv#6!eTPX#$hH2;@NZvu9q(mcT7PZ5wRm&eGGg>s^OE>rw*J;<6H&Xagx;^uc+uhQ
zYHHPaS5s?oOd?uP<5$Tl<vx%H{LX{(gy{SmhhIHijH<7<AKnK)aJq}!4Ubz-wdCxc
zua%+!l0Ami<ft_;5Oc<?tp<@WFnI!gl9FM<^oB{{^7h0CJ(r_gi|D<obuk&~5<=8k
zy_k`H*ioS9m<Ox_?~HV<aEno=wcCs4&40E*jX*uPCJ!uhjV_P3hn#4QT-_G>;MZ>B
z*1%f@(t@T3+e^()SHx>wLLInbaPw!WJ@$>N*CG6BFwws+xFVd`mPXk3^bGA+;?q)p
zl>l*hS+DKW=Q1#z*Z3dXfBOyBf(u{nzp+R+a(_=)?hU`+80rn5AskFGP-%AB?mhbE
znysG}NBiy(8`_WB!g(b8^loR{(AEF1KP0lo@0k#5`rXz?y#MC?Y|n84>ncDXazv?i
zWGLg$j<(s+Vsz*K`A<kUc8;TE*?peFt^ev>fAdfN-~3Y-*Ap?`^)nf9`e&=by8gbS
zK270+tLJ)WhT`%frQfH#xbZ^M?#N8(<3{hMRpLqMSIwUOE7eVlJ+Z#4{?LE-;u(1)
zU$FG7?E8^jZFfJo@C*LNaNS}!^udMG>cSts_EF>S-@fpjzwh_me(lBEuN^059tYuZ
zZx5p9ipYN17e}j?vW(&8ch`a*=??6~d-L_Ce%Lr}v^|@LPuM=*mZh7r=s04tzu0vl
zFaYcm{3N4Mqm<^nos+eih-OEF(tZc0j6jMty0{n&QStT#laD-WrE2zkfmg2GS2!oK
z=frxk){kcQi4oC#+km0oyO^dssyO2J&j)K4s~f}_Q4rOh1%J`+IqGjXvEP5+Cy6pd
zAZgk+uC62(s}Ia{PB$N1Hg4$oq|Dp*-k&<HSM_^E$2t2Rqpj9D7s@*@Qqq=^;cljl
z7o16Bvxw%Ze$Zu%Vj;ojER#-n*n>XWX|*@xYpy8d<_f9z3?ox8GHo}6fcWR`6y1!N
ztKGV;tBJ1KWfAW8&s8%oPOP2C<}Qo<)q<bd<aZw-^GpIjH*f$f>v{L^_21ayl}JIK
z(<fJm+|+S!w8DCQRlWeV7b>Z`D<y$B{M;1^$H>)WBqirFuIP%w#|i=uDqtyHrcf&&
zYIwGncTG<nhwZyo?kyY<J=a7P49mGSM*sF0UAL<yZV2Xc(XXx({g6bn-}5&J=ZqiT
z^!<L)))8V%Yq9+PFZT_XJE=9tgxw?W6{~tv*KIxZ6F9#Q>BcHMZ7|Wcom`@d<tQvn
z(_C4yR?3&GWgw*nciHLY=I>`zn~#gla^7}@$X*E+oROeJ885Qn(lJ@OI<yo-3}&I-
zU1~gQ@#>t&%-P0zk>wU@(V{;hoO%jjj=G#=U*#ZSuiaO@=G>_I8?ra6{@OED=ci)A
z>EFjoyT`urO{M7T<;JW9$bFFOF3b1+-fEht|FvnQ?B&@?BYnA%nQMC}f6Ul?TA#BM
z*KJ#LEZAZsz=0>vm1Z(Sl8t&0h<91e*$=tmpwVT|<qfFI!hOqMa0Er(gB>&VGHowL
zgHEbKykzNdH+MX<`FMWwWpP~??i!IfC)SA#2=$B+bxzcyAqjan?NVN9_!r!1b+IhB
zai24IS-e<X<FE03^kF{&w0l0VPe`f6XNnDAgfs7b@yk2C&NQ2qJbJm$KJDJGZ$6Um
z)Hhd+d-T<MtzZi_x)9Mo8@>>F=gaYfRL2jcdq7S_H;artucvCY=w#I&;x()R1#?T~
z9gF9!m4|>`4b8PS&*$0Z4;3;$61E@BvCVVmghM4KHu_h>kh|puD0BwH+;w5*MmLBn
zV!x<5xqW^$`;z!G;h2|2>|5p&4YdYW8<7wkW4IB1_Uo~rGd;krsPEN((Q8k?_c48S
zo8PqWwbv_=;^wMGkUZ~f@evsK-Sw5cSrUjHYp@E3*hfaMkt2<0bJRWSlo&X#3&;ko
zvtIQJ994<}Qf$CT%@?NT+i2p~YjuiFv6kVlXPns58Wkj!rsXy`e&I8WpQWMGPLFt{
z$~M~I)CyvaZ<hye`sMG2HwVk=7RKPnTQkdWJ=mh1?$5p$e=TqJfizq7X3qiRk7{47
z&5OcLy*Ibdp0(2jJDEo=7R!u^6z{tED(zr@0MdR?pPIAXmwM;(1(7;#Sh*;*LHuj}
z<)GkrKv%_J$Q&J#Q%gbK#6oS%We(J2O4P2|HhqTO91ADxgn#!*J{cLJifK*PaCn8g
zjxDp!UoX};x%r7TPY%wDp0}M%+|EsZ@DTqFgc5hRxSPCMIc;D6`ICtq;WjLaW=DFt
z?cB#Yv2{D<DN1fwZAWaktzdt`u%mbppzTCZLu+7JE;ZD@rZs(;@)YwKE0;OmW*Dr0
z?V4Zpvr5DV<sBggMc-0*ol`ca6GO>NO+`}23!AGVHJ@2q6|6&T1mGP(#Ey^}hR-{-
zeQqPl5^x9*k{g`Q`vvyDdyE9G;N0LNg9lE8EI|lA3A-b5F#m7pzWugG$&NYwl3Z@P
zJnLQ0=hq`Td(-?{HL^>(zt=f!a|QsiNEe51NId_XJF|klJ$W2HI0B>=9U4*l2b(?Q
z+t&0puW4;lrcK^*!P;}j?=OfA_Ho^LNR1j18SN3AV3M3$7Q5zVch>~sY@H}?aN2JO
zzeg<iVw1>)<_(|Q7;PK~`^&0#4F}gF6*l}*$KUBROK*ZxBU1Fa{LE!KismlsO*_|@
z*E_1ldV7`q7Bx-!6h4)vnay`N^i#`{owvEByS3v5*Rpb)?xD-UNRTi`A*n8wR3de0
z(Jb8rVBamLPFv5aLo7H5S+UnJ82L3(+sC_#K5_@^o;jJBr#EVjZF@-+80#x&iRyYW
zD1I));G$3W%M&O6ZO&BNj66W<P*O|g{hB{K1bP}zae7_*g=aeoxoDd}%eKwh_ll%`
z-R}NGluc~K&&TU!*sJYFO;AqR{(LX;8l!+Npfx_y6<cYSN}_=oD~&Cdb_|^#9olO4
zu^pEh@44<wW}ern_NQxqVhe^|6~{yd{n{PxCe*^@*HKM}Tq%%0V(o(1<ga=1sT2O%
z?^OrUcG*Y#{%g+L&i?Wj2JZ&WnbW5@sm%CwtM?nt-#9=Da*ChHaZ6t__QAV2ZC}<4
zD6_Wfd8|`|1JEW&`M~ntaiM6H$uc)nlz(od?4Q(*=TkOEoy`mmg&rG$GRx)}DpMmJ
z?e}^<J%CM-XXERqgv%Zh>x_qtPSIXaJ7^8I<Z#Pec;ef)<Vu~MZx{se>2q$EK&7#9
z?sJ?CBKvb+<eU@!<QXiTb>*2W^AiA;5ad$&1*^07XP574pYTX&dzu{b4osVS3+WO4
zo;JSCvVpD{=WMfd-F6h87jG-5k2YqISat+unA+>^t{pTmWw;lPol>QJM|dfs6jd-Z
zwiqrh9`Lp_*-JCFv}-I|PP{DU+EN9vHk$Q`@hMdxPSlMu`=btgjj0q557!FrR4sb8
zx<QPJ_0{fc+3-a5smrX0y(aK8HwXQH8KBJS7qAH|m@XJq@5mc{kG({Vb2R@cYF52d
zJKlCoOxp8#Ofi>b&ys%<56_P+78|qXVybD)EH&hDdx{;xF4?>She*rS1jmI3d#)Vk
zn&Yz5GU%Z3zT2B3@Hkg^aNck;Vubn6MjfGbkIWO5Zm72?XOkP?AfwdRi*kALr{cw6
zopA3HnIkx*8?cDZ_+)A*H?qsVe)aJ^=1mhqai^6gJwWeyx5su@V*<&av^DdF$zk4S
zpRvz5eNivK#^d6#gSyfk%ks1}+gq?0H`W0a9OlSo5@Nlxm48Z?@!t*(^U%=Hn~QtR
z{pN%`!2F-KYUeES2{%t+{8<HTOTj@_K!ftmA#SP_An|z;n^WBI#hNGY<385@RAiqN
zgC_!Z(}|N$eC319_6`yDPC)xg<GW|>`XQF>Hi`!y)xTzUysR%9$8CeIg8Jv|z4ns6
zVDGa>D{wH#>)|sfCP<&aPHQGlvOHxb4&IOHUPxtX$Js&AU|<B(uVwzlywVsYt@o#|
z1bfYQI0{Pb9kdU*({^<8g3v|2utxMKYp6hMsm2^}b|h+`WhyMV3$Bt7Jr7pbIBT52
z?3wD%t3K*2dl@5RRII&n>SlRx3c++0(=I$LDI?#gpq~F?8Y?xe5)CD3Lthiq(Y70Q
z{$BlF;~{;OZN6n(Mkm<kSr?YPrPAf%8(0-=DKhh{nbQ_~YV+~?F+%wd?d=NBMM9b8
zj>dUa^#sr2VVt2?Erdzv&P*ZCA`huU#4erW2yrHy6VAyLcf<81=1WMO=Ej1HeqJy7
zqmTHHa40s2pE}_=HrC*Nf1khL@AnN-+HnP-Hghtq3%&pBQA***Q{eMo&u5z-!ynK)
z7V`6LtM${m+FTWGC;I?+ujk2Ogl*jFG^bBn<I?Euq_6kEw#~<}e9+7s3*o=*qvHtu
zvosRZd~|VZy3?ez!$BAnk2bOmyOz0LC~U~+BVr>q_dG`g8Rc{X*mIoJ_AOf%+!_B>
zmqp1fh^%uHJ(tbCE#@7kC1y_q>->M^OJB_@lMfq_S(Q`Qzw*7rn<P6Nz=YN}+V|A%
z&EJc+uv%Zp+o$#W^_(#$MA`s7;?R;#po)^VEG!6Xo$kRxZbfQpDkJ7HXuH}G=V7tM
zS0@A;V=VL%EBi>3oI$Opq6Z5H3!CRNsVU`_<<UrPh7BZ&zCU&<#MEx73+)gcys=jg
zqQu`7)!Y^Fz3P3=I`N43OqDg6aQwAl@P+c#`Te(+?~sLUF-@(JIo<u?3wJfKqo219
z%&xM(ab#rnxzl+=zML0x`n{Q?yk<o8oDx8ql#7?jk@hQSoD_%sWoyALxGp*mJ4xAY
z{)B(~CPpchc>&cI)`#Nl$aDUM$gRtbSr^f8EdQW7DbZXlYG<NOw|{qigrm+<+#1~U
zKKGrPaY_hx0|tkZPiLyH_zTq=)#@cN-~R|_-ro>jnIDCXr1oN+Ty*7g9@M9=8&@`(
zr7KJ{)x0_m>rrOqV|x3XXh#~!`}K~NC&$^p(e0G*ZQ!+|oknM7mOW@r@OnepH4n>y
zqk>0-<gNOB0v)4f`TW=new=>BL_={fneD^1h2A-P^ISf&EXM7uV0&>?qK<ZwOv#o7
z%N}bDk%d8XC|AQS=U%Cv@n6ikgY$kr{HuO{#J$gv8rYbv_E!G0&AZR<H;>ZNTxs!d
z%w~SnaZb<bOZv<9a@(^06Fu5?&c+b0cw#sRn75%=v-u2%H#IKnr}70P(HtIseiCPt
z-Ll@<<`WuKK-l>m7wcm~=dTRyrOzgt8M~o(YNT<nEtiR`x!>;1qV^V0{-Q^L6gIgi
z%&Jt!M5!O;$xWk*gwh#rXJ7GO5v+{5=jxhZ4fk=`9sM@W6ND!CX$LXvaJYJZcF#v{
ztv_pWUC%#cf1PD{&(<GY(uI8u^KiZ0bq!Z@#M|N%&Y}M$)*fX;zwa4Sc0{Hkhij)T
z`}qBCVRD7iC&5s`;g}FRQmmA*3n2-PTV$((+(Rz6G+%Ig*JSK9w!kyZUK0Z7C5kqj
zKlwxsmlS&kRbIy}-RH(N;Z`>|3*t<bL!bGnIDuxlPdETC>-_qN%gfb;aZGWJu7AAe
ztXcYN3vthpZ@=#L96n-vt8Mek`hq^!)-fkE7(&M0?igNw(4<>Xy?k{DV$~*GTMk)0
zZsq2TWBMdccvNijZ#e8f9-}kzyxJ*;(k$9}jM3IvVMmM2=uxDvl37S=tSa9(p2&T$
zAQYZ#)Em&Il;BeS>wVd7EcD&E6WMju+_~y!{K42d|I)Yj4}O6>D8w(C;55s^SY~dF
z{r0<-IXt7Xl#g2E*qwIg@|zcszxHc(R?Z7ED=&LhzZeUf5(pzGyGyqu9hq7W#;4}*
z?@eVm9{5ILsEX+TT`#_f4OXu2w_-nNE&V}TsI={4m;ySC#r9gXhd2_UJtC3p5I75v
z7>>9uRtZw~j0j&5o2t2M*`GQuI-+d*mumQ@{h*Qvsk67ti>CGOenI*)w8gXf%*%Pd
z@t&O*9mnm0Yb24i+QXs<%iw(6^O`t2P3woK7<M7be5%l^>~h_5@fvb9f4?(vOW59$
zQ#+LUc!M2BMollZa%TM9wdtwMeA{{@+XQmR%@y!VjS<d6O-UO3Iz%sfJy!q@Q=3Me
ziTNkj&SyUZPVgjF?j!!%x5LH3?}jaj%MzT@F$v|=th?q1@0#WokJ>rM^luo5k=2IM
zd8>^`r=BY0@5Oys@2GhNy`aihddFftBqy(_Fp^rdH^(9ZHc2rR<vctrfFE&_JZ!75
zwBzFW9gA<IOIH?IFmAs7zJ=sDXrLC@B|XP+;0>|BKc*pyNph=7RfD(<_wtf5Oma~S
zLk!7k`Kec`FZK`Cf_*;lo<AZ^j(qz7pn~d1f%IEy(7VdQw7BtpN|jLGi1z60I4n^K
z7DkD<2i;-e@Zq$Y>$@Ko0YE7tXl00hLn=KUH``G^mD$Le%(aP}ZD(qXDtkh3egN5m
z(IKzC<KjjAlx|FU@2Jn~-Cdi)EiX8i#EP}GBdm%jVw2b>$7)K-QvDfoRIYcYQ5`O-
zgH!E`Ti6+p-v+L}L0rpT0TJBb1S9T-6BBqQz<v~4JHR(Y&0qevyNnqUa%Q~uJMx9E
z=kL8g_o$wJ*^VY>ZDs~206|(bL6e3Ni!nrjI;{vDyJ;Q7X9B^Z0JU0{zUVDYi2qtH
z1w*Q8n+3U58Dq6-ZL<x&d7qujquw2{7XJ_ACSeV>WD~_*INI;ja5lg_Sd9h0wjlOZ
z@d7sre=tP$h7%|1PpemzuQv4E5)G@AtovJIA3Z-BG#OC(I&_ouJ?rg`<+eh;H+NmP
zbv@@V8w=f+0{}pJ<9fj&+Cs-)lGAdw_mJD`<|5#iZK>n8v<BdT0=Jdb-XNtACw9o<
zyr`vMJr=C!!3+knwT{hiY{)1Gkg;O*vac{qIO25@t8r#`*RpY!{a5wZRjb|e*)@Jn
z{2}LsHF?B$oGIeXMQb-&m=}k?lX}V2_am;}l5_baIP63A>b4PZzxhIY1^+L7SwClI
zXYG!thZ`Qmo9AP+?d`O<6I`OyYwk>;*R@i|^P;z)od2EvR!2dXrC{treFsq0)eF}x
zbC1c^W!aj&hp|Z(toeLz;XbjZZB0I<)WtOgzxsyq0p}eO>agJXFD@yR#)@#GC<wCm
zGq|wp1eoR(?5m8rpDEzk79Jwo`2e-4>aSYw^=;efEux(x8}-%3k$gIz?<m-laz)Oc
z6CL~PybT!u5J~|B7wbnAN|T1`JdUWaW@=N%g@TRIAsJ0f;&uVumtrCJQs<VYm&$o_
z1~JYqUY4IjCmhrZo2OnjPK&&e*eCW0b=>hoY`cCpM~^5e=MTNPyQcI??wSCS>YslS
zEAgpU{1e%ptnvjj`~9oA(VRN%an3s*ujcl~-oJbXKF#F#>}vgUdGL|vQ0K}soSHK_
zKGl}qXX~;$@~Cpi>0S|@k9VDhb4vhq!98b90~gN$Zg$x~e99qI5Gd#-s}d{in31ga
zURFKjz2ECji^yj2vVpm~_9p^tQ25cc1>tlX{#e77EfGYvf4N~?aAhv~5-`7?QD@!H
z9I37o=)SUzW7z*r7(CVTgn*|MI*ufH_q8p1%qziZ0I+(a=^BS?p937Zp(A@SVOQ&!
z_iWqEE*m42fqf1KeKaiY06TlbJnZ48O7hBf*KqbGkLL}fFskb<u+8Z0{Z+0HjV_)a
zof*iRom9?|2I}oFfL1OumqGAkt`k8)VS==s!vpD#h9^|8l$vfhc-Lx2xEGMlOwD<W
zvvFC}vOiTf)*UT(f1&(uU9)9H*5g157g+2=O7On<mzT;-K8sT4jj#9KBfnAOPTJm6
zivp<U;;D0R0DzXZW5wbmX(X#HY8wIZXKZ%V47+?@XqzMIYp@j$#4E+rK`EEgV~gj5
zH_OUNf8Ls58yXj^>3JJ3WKCv`?qXgMx0n|%i7Lx7B8r39A?R~;+>3~$Y7K8d_*KWb
z&jGRRCkRumI@zjIe#ZZ1_)Q0?t1uGG!ztwyz4!V5Rt)}{HcD5iD~M{Fsx7zGmW?C!
zLwaZa!KR&U+Cx<+7lEfd!kJKdZ<vS7p=L|;Uc#j~T&vAxQ0*Y!yj^IXiW}i?2f<=J
z;N_@Z(%Ff$&EYuOYwllTtc`-@v$wFv;bs^q4mcBxIs{*F57gEpuM{fRU;AnH#p;G^
z%@@JE-*v`!&XDp@j9b$-NRyQBZGJ<+Zy_hOqtJ1<CZ@1Pj<uyl)krI>(*!sO5~Jvf
zAe}B#UbtOlG!SvI4^N2&i&elGM==N$Wx&P4r*5SZwlm_lsCB6VX8FxO68ns6_M?bb
zZM|}dT7n7L^p%rFYgb^5fbl$!qQ@9ir+P$u#$S64M|@uuL!>8M5Xzuk=XYP`hm1p9
zpW{rxE&uo*?qP{P%~ri`b^Ounvp>>tkJ{!4dx}SOLZA1j@Yg>3Bva~zAkDEwi2qau
z$FewP7kUo@+GOU1(VL2PiG9vZ$LRwl84fsg7n_Kvi}fpk*Aj$sW~8y+GC*x#Hlisx
zqM}}F#2$pK@B4$w6UWbhU?W49>DO}NoWJ&pn16DEI8j~ub5Zqo<MTbz5=>ti#S9_$
zjp*__(q5K)eQyI1yubp-T`d<rw$J{Bt9P<_9?H890zwmzd&}@oqLKscJox=^aQ>oc
z83!bwLc}np1u!8dzBY-vK;dn5T7n75#Hx*5IAl&Q1>VybJ=`~AJH#|wM(>)o`!ege
z1y(~r3LAlMqxSH(B~CIHE`~_C3_Ec;+KL7A;9WfR3W69-UUL8q0~<hr(11!N2~&~O
z^*`RS)4Qn55V9wpUoBt8P3<^fq*mk>^vno4P|uySlP$!bl~7lY)0hf)E5zkP@Hg4p
z$MHjL!diy18r&fo4WTCzqgbh!w`1iu=w!JUWDl(bT-W||uXRdnp1+?DpUc}BfsWWH
zZb7&8C)}2kp*|%nUT~k`j@g`R_X&c&Uw+WfWTV*yj3~eVhF_jO+QO=odx1#83c~oG
zxqe{v@X!|d{nq{LwSJ+@#F6Q*6;OMd4TZAi8RB}otp#hgloD~dJ=ktDlG0n&)bWhb
z%V|z!qIibae4%1T*o3g0N5lG}dB7tji4%g|CUejB3S&><vH;QQ0XKAA8$ZcUjiKsL
zbGV4;I|4f5h|=6^e4<`eaO&N7;y&jjw@KOQqrzEx3!`c|NvEyT3IjVVfAXL2{DHm=
zL{SOc>FZVx>vQBr2ijszv_&7%sf7l(Ohgh+iCT6^2HZ~hE*`{TDQ{TVQ#nHKQyg=n
zOVq^WRsdOnRH0O+{YrycSQb@sm*ul~7`5XDr{gsLh;6YRJ<%-Kh!H(GCRA(@@|fao
zH)=+lkM-9H`w`JIUtNorw}E5r+v^5T91H*s6-q@sSfRuQHujAT|C@3*C>p1%#NGq5
zUo*azAr9FKYe1K^1>2Vk&JhRcT8sq&I;_0aB2j5+hMdX+(nV0!@b!RmS4>7luFz85
z$|xM=m<QI5uo?c)L&RQaosX$L*PgSn2{T?*^emtsviy&VP+H=NQxX(GX^EDpry`TN
z+Je$@2q&P!^};7WgGhb~b80^!GW$OD`Y?Qp83GtbRebK=*!e3#q>j0m-sjF0zM<d9
z+exh3d+(<{f2Xa&OCq`Cv162Vfvf11hDIB~0WT!lsAN&<azm;RS>7=CcuqXz4dp$l
zRjDI?&X0z#FJVK=_E)WD@6>qhV1{UGz7x=D1LoAcK;U5<Qnj>PzFVEdmTg#m-mO3F
zHjp4Mi96R`%g$#vWG9>rd{;3)`;vG&#HRX+as{QFRtPiD1}gmZH-?9{dHHmwW$n?g
zc8q-W-uqp(ugs3jbxaYFu8t5#@&XU*IB0tH;9sY~1+A$_-NmXu;$jsZYs2DYBBKMw
zgwKt{K;E#a`0}==K&`RHwB2+MOaUThqA1BWr&IJ?=A_`#-X|ROXoZZG@00)v%`Lb_
zgZs?R_iu0vR%7r*5QS>)NvGe~=c7-)MIHe4Cufxdx7T_HjEbZ3-orocQc(%ynQ_oQ
zx+?z-<5PHmopwQV<_+X8J&r4@oUDq7#fck-@(rttP%A`3B(S2?+}~x}_}a(B7EE?_
zmvZ!#BEhkxFxJ~1*cMT8^vINo-s{#nV}rPEh|XJj1ht<bg53Q?&JLAVr-*0-(WY1t
zckO)teN@}ZE>xW}BDNm$>TL%-sMs|VEk>g>rj+ps((udg+=XQk*=WghX8FiM{$--w
zZJA}`v>si>=0d4wrSM}^&us*<6u9_(1|pL9-$4UER!<QHEN~B^bcKjF*@+w!w)>9q
z;`tpH>LGgMYU8xUK6LB7IPw{>u0XSZ%|2d-@&a3|eVF7*ZV~xtv@{6&?ekUq?+pa-
zp|E7bBh}33ePLb}i{-;%fW?CGTxp;=@CV=j%#}Ungoi4u|HA6XzTUIi_*}k;87SZ^
ziE9{DVwK%R;F}nx3`#?o+{;7<5Ln*x?$kAc9WXjH1(TpgwziN%KvHZ%DHrQkhOVd0
zp;ny70*;tIf?2PF#;5K#dT}-ugg>t~6c|ta31qKY1W>~RwU^u|Cv6RKYQMiAu8Fs^
zf5;hnMcj#fXm2=irhLWS#0N-FFN{qDt+H_4Klw#*5xJFOc%9aIH~DJ*2$J`-{jy3M
z$8VZ#nI}UCeGhLSmWW%gHOabWS8{qg-Hq;M+nzT>DvFS<EjaU{r9{|MDoQ{}dQ)8;
zd`K~1$T^&<9jC#`YlXGkI!A;563RG9QOR4K+K|r}YY4E_=;VBL&<TB(>}|lRwLi_`
zdb9*q8E27)iV3MheyI1mhd*L$lhV#xR@-dP>RP^|W8Sz|q?8ksofGD&?iQdhgx$>9
zM%^09xH4v51IX+>M)`3Y+eD~6O#G7J6R1-1<^o|L0{PhGc`H09vah<z49mSIh!2Q$
zY;?2-N)GigEb3z|$PlOp;fC4mPN5^UHT^w5hl}t%WhOe`6V*rjK^TyDuOh}R#E<Ey
zv7!H|b)s=%JM~o^N55e_%Qkw}?l_%4uHUP}P{~D^e6R#AJ6bNq$-GXJX<se_D!kY0
zPR;=jv>|UGor&5x2UEBh3zb90m#Zp-u#C(1s%3jm_ns05?ag+E0#cVng^li4`2qs1
z@M!#`lPLxdQ#?L-xe+}k+_UVYE8_p4>3yK1I?puEQlX^Pj+55CRhF+rS?K%jt>UUA
zBv--GWo_2cy<9;d%QmRlH1W_Urp$1>?wz#3?yP&x?6hvxRgi*ckYL(mlN_UxOc-}E
zL4t9+XL_bxxJdArY=CgOo!M+RDziSG**T{TWP04Qv)lW7FK!9rKgiPk^L_98ywCf*
z&v!64q#@cW8*`MgExGtOJgI(u3WK*mTovB=_1`^_fzykB*6Hq}dPDUFL^^7U)Iy=_
zI>q0DGGL$|0bcv<9vK{-|CsdzqoNE8&GQNocP(mmHdQb^4&ov!c^gYkQsCaXX-ORr
zZ<lX-QuPT=;Qh_Qr$XN@*+ZsVJg<{etkEnS^xik%sMy_BhcJva;15ytmeceH$$=yb
z+Tw@N(Sb;U!(|+!r6zd`nVHB^z^Ze1kF0c}vUrwNo4IH8zq)XYcGDV1Tol%)hJ+(g
zIkE;p>S>emi?r4R_=WJYGvT(i2E8N&QaoNYX5yal6l9Hdcla=f+>0bZ>CNuDioH-K
znrjGHn7UA+knGv7A2$cEpVGD|%%RfC*;QSXFiW5%%$`80a1?ko%C*x9U@-+Z;L;sC
zK+>?c`ns^a7BVf+6%X>Kr3dhFz#ai8I{j{c?mtvl`d5uR2CHjxp@?^=0XuS6IfhUP
zktgAYI_|c&dyc0o`=gjImhyJp7+GggHdTpO?Vv-hAN~^#CGg&1Y*t$P#ud6v%F4f^
zb<ayhp*>|Qxe6v%m~==TSVK{&<;}NT9)_akXjaBQr1ZY6&w@z4=4V&^1J3gB^387^
zh}SMSP#Geik(Te%e+t*UBZOqdMYbOYGPkF0XmUV`25X8R1!@nr`9VAMcn}8RlW7xA
zXsC$8NP?D%Xmp@6&#3!KNDYQ0G0x#}d@8*Y)3zzQwp1+A-`{9&T{Tz1xFlmx;l}$+
z^kViI>Pl8f++Ln0u`IZetEKuI&VimP0|!L)ate;hAMiVq6j1$Ce&!UNJ1)QQ`@jE%
zY3C5cTV&22MoG|pJoS!2&00J|w-0s2P&V&xaXQ<fI!UCLgHJMe57!P^AiZ9mJ8*)U
zn<`SVC6c+OGvv^V3PvX;+TTu3gyLAmBPxU-U?CKR{!v@uIg`-u$t>E6<z=cqLaM+)
z{&vib!lTsg1A6>ar95zO7^3#Jj&A6$69;H5`^(vXHy+7{NPq-r%pp(s?Sm&W&8OKQ
z<cztM?n9-YcY~ts6{S7II*KK=pn}||f;+Sydzv(uZeF=wCU_DP1R|Ge=+t@;a4vGX
z7t5&*0P$d|(-}HtypGH1E1Ap0sogVO=j`w(0~PcuUP92D^(EiA{UVI*d_a;Njdy^c
zTZ=pVJodqh{&w?H1*sPi>R@jBB`KNw<1n~H+4}&B>y|E`{C2PBMB4i)xq}-cCVsSV
z!I&>RuB`Pszk=nc+=`J}$Uf^c@YSGMy0;7zzCMB333L+*XVgwKlNVFGn3RQ}rRpzh
zmo7SLh0#6ii)ievH1)>Q+%!<S*X{bK3i;4eI|*z1fqjGO4$zmBIu;rt6w#Rc)+wM?
z3c%_DOu{dLSz9U_5!2q)l^6ZPehVyhz!|^4IYPPs@aQ$lr^hd!V0_+?TIi_CU2%_Y
zUT>P~i>W1ZJz_{<bg6R2E@opHQhDzL{i9<U;x2>euUO|)7bz_yI<b$yA$?qe3}CU1
zJaGNX=`Cq<$~X<`We1rS%&i)sUgB*aqoO0g@}gM*+jajIqHwNyW2VaO>HI05KOFo}
zN6}fG7<TYo(14J#4|=GzapAzx|L1qfXx3cY>^)26P|$8h&A(XK8gdO!=v>h5jdFHH
z1Mli+C!!wYXo~lz2~Fhnu)djfUIcI?-DmyLpdC=N=L$+p>ItF*@<@s0g%UmeR4j7d
zrQ>Y3NoO@^gB<Zpl|9X@geVip6V$DVDYNL0OBdWkfI-shf7$1`(;h=M#V7{(He$)N
zohkg~&(9cL2SQU2RO#Vr*nOdZ*5g89&1icZPCp~PZ$yK_oXf_unwdbT9N6=Y5D0X^
z1ur2JPa#f&{ql3v6H-O(i>UTw=k)@Zo~9O)&xYGoK4(v@8~i{wB*Q12(fdz6JDJZi
z=s4N|NyAS$QjI9|7@hG44hRP|!0H)xoQTv;_xm4@$88M31PBC(*=wxMP5;M>nO~;U
zKVe;ib2bny_s$L#Hl&av=$_{c00<>Faeq}I{YX$Il!<{8?Gsc+$Aqk|K|`SZiz8HC
zt3_o>BzCr~IwIhfu4^DfEuy?&hquFf&j8CpxNk0L*g?zfsV)}!WU-LZ5E6n3L@6!}
zpPA&4TjLKNB_KWTJg;6r=&cdB#EpU<_=|Bg=3VnZ_kzbID!IS&>mA4&3z=OrN9K=}
zj@RzG)&@fW`3I@Z#*p!_fo5N(406U62mX(OHA+P9$ngTbc+)PKvrC()+f3nfP}2Hb
zGB1VKQl=v_b9v8I3Jn^ArrEQ<S~_Z<fu=W2wTZHbHCWMaOX0msD|+9uoWhX1NrXqL
zNA)asn7;uSkIn|{1KqV+iNK9yiS0$-Ax4b{1ZLq9pqSXnK+T>z`)e;^ml-z%j8f_Y
z^M>_-Om^_oFEB8NFxA~=dOY8DawUxF)iDbpRs<Ce(|%)SU4BW)*V+PB0Y93xC8fn!
zrXy$`OJ9{ZNKodGNcwyR>ePJ8wj0tOE;4>lEy~^&9fFV{ym1gMa5h9H2_$5$BPjYl
z(hBW-s1N%KEVc4L@B{yc4y6S|8=;JJ^Zx(vnac+n_eE9v!&m1woII?)!ppc&FjkNt
zJz}f}3g!-}29-upfhk!3`=aSR6JvYks7{zFMrFRABP-lvB1O`O3>jC5tEGv<PWolm
z7f?i+IdfFtW52k%-y8cU7MKmC+e(SuwQfWU!?R+l%~}tFp-F~GM;4BB#Oa)o2y2%_
zX^~G3-Uj7<s38wG`Ognk+(9C*v&rvIPv#eSo0foQsas_SA1iJ6N5A@Gu;|RJJjU(<
zzBWIz^ctGIo>pqVp=I;yAjWzSJ>+yNJ%Pe3V+tQAqRFB=TU}&~A!Q2YAb_24Jb6FO
zX{ZFcAheYOxqT|dl6Btl*$D-A5Ey>}WW~#2Kyw$>AE#o+L=~Em&bQFIEwB!y@%oLZ
z9@xtV$BRDi^Q^y16AFSeflvGb5XrV@o%OoE{m6;*lNs8i(NSYQ%HOjJ8S?o0Vt3mH
zqgW6=+IV=<?E|YfM@57ipqHLCUIE5XP!E-8tg=;1w8Y7TheoP>j5HpI0QY7<?K+mG
zD^AmvodWs0gsjTw(rDEw_HqkaXAf&+PK(nqd&oXXgtLD69J!A@|H86Uc|jU#t(<dE
z_wONyQT7cx%fMYEUZ*WFY@Y!Ny2t<Nue@!|dNd@B>A!X9!OpYI&0f-8`l0<Pp%ET7
zNe-G}-T<3~ChMxfp(pUzZC%e-L2x5gl3L70-waxQ9JAUx_sxLi$t9d#{WhV2hh>(I
z7V_bejrOxN0HpOv-?C9ANp4wby}}o=<<Su%0_vl}*qGZypKqv=-&(PkbM(i7w$31V
z1TED!;fX-=XN(gf37fm~>wf@gIQE^4i7F*^sQ(kyPu5;lKJz3-sW+~?A2#K6pd?O!
zZ4-@aGuO)=runj-j+Kg{mCchl!NaOek6wggM5{{!C-fr7kY+4V@X8;NNVa}d)$%S<
z0|-SnnZ+TNk#y@HrT9aZ3fCg~guOHL(?WPu?xakw*~#ZFRR*29&-Cg*Ku0!C`Iux%
zZj;vQfBvjFq1w#MA;8lk5^!O0S}A*5qp)?ik%pL$Rc-tL!NiJg$P~*T1Qo`JmBka>
z4E**0D^2*P^e^V-GdsL(1%beOXWY39);c6sJ<q}5nCJC^c7#iWrC|s7a@BnBU#PTM
z=1=)>H|XZ=1*%ngGl(P8mFS02+9$CPkww-!bNAar=fP*lxGeK+BfY_7piA{^X4&YB
zP9lKTq(7PR<l_v@WQ%Dj;|!1ni4c&Z$ClzI7^4Xz&6>+Rgl3aEn^nJaCByzU018DK
z9fdO*moCC8y<s!i?<e7yKb`ENP6gz!S<i0&xS|i%5t{pK4Jo#R<WuEi<3C(}`BRA=
zg>uAj$)A0<jpfpybLaisx>M*s)_<%(>|sntr_@RH(4yYJ2~nEI$T%jq`lQuG3u4UO
z&mu8<7D{Amcr!+JcvhNh8X(P)N)*YFY}>iZO$(hi3=Lt2aV&Rs0oF|AD+&^`*w3!@
zll-of<GlWi4ka_lPzo`WUL4=i<=S7S>!KNadErAxf42We{`Pv{e4j<Xaajsj)E@jz
za<%cv?>=?{^QWgnrPhqK`41K*XJ>_N+6|96;uU1IWa>I4quiI7)0z#vi}bg<peBw~
zdr$)`rKXmkZ2Rh{cj$wS0yFl_gpCIB3ge3w*b=eb>;lb{kwsecmrQ8b7V!j~o$ws+
zW)7i;i)Y2lYKPbX!{{lR0TqW@F8AkT0;=mQKz%uI;GUc`1qDScCtSV4@8p5M_%X9n
z>AsK>uf<?)_j=T#>r?uX0!htlsG)4i#FcjxLVVQ9l!F5y9(b}}=j;_%*A&19ITNn}
zT+Ox~6J;>q3IO{{T9?0wlz`X$C~O#DK<rZJTT@F)^Ne}cgdWI^@dtRCaorFR{fpAm
zMyQjcO33AWnD9JRHCq=nyTw<>{7?H8b4Ca8Y>o(ccxByD915YqFj?$%ODFFZm=)|*
z=2l3KhfQ|C2Gjq~4#ODaF!=gi<<XlAP<f^Z=Qo#-!vnzEc<=E|Xbm`&PK8Irncx@2
zNpEHrIu731J69~4BkFEZzl~m7#62!HEh<}PA%#RwRB8fCXMw`p-lLWAReAmgQJ@d!
z9J9rq*rTsi_q?HeiTgxPP@gEG!r8l9o`cnIfb%Wd+{fq(Us5Mm3cyyox?;qWBus?q
zYhxNMhnEPNjm~JlCwU3-e0E8*oY>PS9(&rRsxW6yXu5fvB0&EuGqEq);a%O$*MUOj
z4!dua>dIw`@NsikwLo)8I>hjMyL2=?j$8tAM$T&FM)LkS{zUhuTMjko^X?0+9R5iD
zK`IHDvscDT<9;G!2>}J*y~60H`oXa+v`Kr^b?c>ma`0=2v(e+MFLW=Z5O;}kh5y=Z
zDpm>~C(_&6i1emO^;@tg2-v2SOa!Q@1)=lhEg-XRHZIdMdRIaHeMHu8xW%x>vg38}
zlVF!jmXTHos4^&IU=%ootCu%HEc0n}==>#L#xH0GS2poFD$)`Etnc(Oeer|w7#2}F
z#mQ{L<O4w;gcD*Yl{%>`c)s<Fz%CYuqp22p`J!^=(i6;|G9unb4q7KfK;3Xhs#S)*
z&}crP6LgI&1pnUj`%Epg_o$emW@iq;exO8e*&nDwCK({_6Yp~s(RMs@POkj^vWRbj
ze|&#NNG8f?Jp`LEocodAUnet2;DhiZIQq3X2g~;Vc=s#VIrS)S%~%q`^<Dv@Z^1|<
zdkL+K!I&F>!)T!5t7oJU@FBCad8RIwZ00WtaQH(Gtns8gcS?Vu`mLKywHpf@GWv1m
zYfsROZyPY}s!`>tswm6|MdYs6C-cNbKER0aW#5=VqR2L&^(FJD0X$R%^m9|6b+X0E
zuoLak+wYG1N1WQ8`2UDWd<z0G`r)5^?x!9-52+%K&l5ao#1>23&#Fr8Pcdby5ErcR
zB9h|0z{eSqLfAG{x7o+q6mbCw@0Kq-l#upt9#^57X{EsQOCh>@re>5V^ib0$P0L<W
z_k;$hXqy<Red_5f6@z?CRW;X7GCs%<=kfuOs*Ojh`pYb%O}^UxmY*IeC#F{5S^>{7
zA=As>?k&IjF`)6kWvpqriQdPK^?$efHFL>kMX`vAJ;E_DSI9ios=9v%Q%b3jk~7Z+
z(C&z?B4w&dE!}h|+?cxsNsn39FM{2{j>Zn2agC7~H1zp(U6;(kMf*{$hUv8@9i`$6
z$B%}#Yhn|V%uY~Utsss)QF)>13)%he-`Mj8ax=X5L~Sjf@s+>!{uh4iJ(>A&NMJv1
zTu1);nz{PeI&1yrZfzVYaLJ5|JUsc;Nwa;los|(Jrg)U0;+6YuRaM)V+=+ojEawk)
z5j`VJ^e8!9>R9Ib!0N|JwQ!MHZA1rcy+y7#cY_@OKP*o?5<QBH;6;5btvW^M!1h5{
zN$11d%MjdkM~XGj=gs=fH-0%jUTa6oC5e<X?SRi;DzuqR0=3oEc<h+UteI=6pBYQ3
zl;)XlJ)|U!IlpP{OpX#zSk~zW6Ob68dEQ!7wBg`t!X=Xj0{YaK=wICkD!vH)_eQ%|
zI}<^oHzORINT264%4dt)D7hn{om3k|00FzIz|i>!5-h=;kN}dhM-h|TZ~A|uedwZL
zsmUtHKY-3e&+PlCtYfJelc)4`XH|H2VDWrrC4DGE;e5!tWAq<Cd1I!~ojO@~q>y^f
z$eg50&5PJzPCjJh+Ht_Zr|E4O5R~#a;X+#jMd<**CCA)_l>Vf$pmX09nhh+UL+Mi>
zMN*D%(Njs96ZDBz%%4f?gdsf2%FfBEQgQf~W+JnEXoJ{iOsWm%xQzj4dyGam<_4Do
zbdJNzlr!<<5c;-7<55z<hVTDc!+XLot@GXXN%bvTuNq5sSGXT6jT&YDB<o&aodhhV
z-O?msp6k4u4@HL}*AJCa<<aSFhn=8ZSTj*!2FKEux1`@=j;V{fc!bAd0RvV4bE>Ol
z6CFiULl#rnq>5f=5>*Nr83rrQ04K<81G+rE>Mv9VD&zqjeaH(Sp3ZG4+Xo`~5G`pW
zb=X&br=vHGV9CO@9uC!3wN+(T!<q=Q=#lI&ck51U5FipDT_#r2ZPM_GkT&x*klNgb
z%>%0*b}l+5m{ce*DxK-_#DT`UbWEdO7cIexTL)CHn)bY@vvr-7{s<FB?B40UE&zoJ
zjLkD6qvS`b5MeH2laKvMKU2VZRXd-xqjvjd_2xIxm4V~1<r4OHEnNMB_R&w$Y=YUf
z`AQYoxgJ4TN`r#fyfkwu<{!!KewszW(oPE((%wW{)&`tCTF_M7N;A2}B!9w1NRE=%
zW4kn_;eaQ~d#)UzKsaN}&6hwX?nv7iV_3aZgg4r#&{_7QiUG1E)h?NsfcpZGk_coT
z^(fFpzPW}ib|QwnoWZj``|QiW3Taz8J}V7}L>cQ_G~D0bobYxbNX@K;3+}7cp#rzi
zYjoFB8Dy5Z5FPK!s_AI1EI<#AL*Gx*o)y((3(Qt(b9H-!J{A8$E=a)NaYh5&N_y`V
z>KX_c4%dA;1V)rN+6A?c4KirJg6Sa*nd$?Dpd_6rJ1KlBzwYZ^=PtQ57zq|7+qqfE
zf#&)@%;i2S38CL1r$x|tys|lIA`|ql$m@9Ndk?&4L}MfXYx*nm57#y<+_3DW&FeR>
zH!Oy}Y}jl!W$q3<(O6D*G{^Q%SQ89$Ft#UU`Ve(Gaj9-F8HxQ>QiviZQQ@(0LY)fl
zq%-dsRDeLoqiPC@XbCm-Aq0PSP0dcowsf+OMs9r?jU}&vKB%m6sc>%0m@`Qx2c<qc
zT)9C|B6;MNb8z((2hH*0%U~iOwIa0^%(Efr^sk3Ij(BwYr5dr07_S+J3qL=7qq}8N
z^PDV<tQi`m#)8^q<b`)gj6Jw3f^~n_*xTGSLzJCuRiUwH=`I!M!4VlRIq3Z$lryL;
zqsaRSUb9;==IBS^lAfKXg>8;hRJLWew11ZuM8)ZwG;|lK)PQP&?4$=LlK7)iIO+0$
zW24J}=C;qWpQx0x^cbRFmdn%reH;ivl>uRCwU&;5l4MYdf|43^_D*;IQ9HFzqQ8(@
zpX#o#Z0v{4QHipXOyLDh84q|6Pxc*QgMxo8EV@Uz4{1%&@v7^-q(@(uiSsBJrC8Y8
zyw<!<VKQ}zC!Lx>05xy2z#N^cUXt1wVBuuP*?4@)8<7SaWBx!qLWeA;=POU?=LgT`
zULYc4RdCS{CTE0<q|+dWM8>H)wEphrpMSy_E1}7yr9}qcFn?EJL$htaF;X-bL*H+5
zX$HU@>_7#OPIpXy-;l#kNy6dL!iaf}hC>0pd$G?Z(>fEE95jp!&C~0eyPVFXmkp4Z
zl+O^{?s<2qXj#uHlZwG5jft*0;Y3gn!q*}`l_3ynKkgyFrLw8gzlvo<#inrc`#;oy
z)C$YnuZ$lN#)6d1cP3!{-Pa#{&)Cs;2Zi(@>rd#xT{qq-<n|jqwN|Qumk+V3d(tpc
zMTiOJ4t8DbyB@IkNHVCGN<A8an*nTA6Yrm!6+sqU0c)L})yy=4ObCp$3^fpzB^94h
zBL%9R0?&AWPyUMtv*0jPwu8H1nMnD@pqDUrI=QJbD3%MWdU^Z7mXn0s@HaY-`sBOu
z@gMktIW2*FyJwCTzVz;A-yvzIU$KOj>VGx$kko1G4MW6;bt+xB`t@26C1QjbbUdhM
zxD%G7{TnkFFR&}**(okb6LtZ7xJ~mW?sF#5lQd9e=fQb|GOS5lpxdxuW~=CX^(CD<
ztoeN-x|7N3;xxk`@=BzhW_G@FhVPk^4PpOCzi>Nu0JgFMb}jq<HNB<GD@5`@FtMyJ
zy}}}gu0D?008Pu|c-NGARLiIlPuonFvTbd0K|OT9PmH!lQIH^IFqmSR({7TU)Dqj8
zey9|~TAYIDH45Oc+Mi5!y`269O-qx8-tmwbmL<EG_rTf(UV==1Xm+?(yO^3UPr@b2
ztBAKaeg}ly<Sm$(SeU$}V*iasCx-xKqvNAWE{^|EfF@#!P>%ryrV5`t_PDT*b3Ci-
zryJ^6fBw#61;ct=jrdAkAUxrJv7mk<8H}|fhNaQa3@?{5v<{@IXK#(Ps>V4JS+WXi
zJT?l5rW0$in$a}&Bk=RhAH$PC$*4oL8(%3gHX+7CA5cM{BGiMjy#W`KS{OYwI_dHf
zNanFAOwz6Cq<+!A0ig$v@u9BZD^clB%b3)G<&Dv%@$F<A)|7aWcpv@ouWZ{L{Z!<O
zYjRFOue)L4UZL=aF>*&0y4Mgp9Fih}Iyq%}?V|ziepgYJ?VUUBc^m)*RndcY2%1@T
zNeFo-D|!M!>=<9$j$~-xOk=i?NgN5OFR#y-uefhnHmT;8UK3`6q~^DDHK{@6yQ<_S
z3J&=dMo<SIRTtzXuj&Kv!U!*=*U)m7o$_!l5NCkwzaypl>_dKq^l_N34cq?8{=6(>
z4wgD?rF$RS`X8!yEY+*<-C38Z01T^i8677jLm<dQ(;Z`T*8?gd<9+c}xm2R(Y2@S4
zL4GvVvUC^&c`LX}?29gc5&hPWh5VA}&cv)7Fj^`NY!;euiaV#3l}$#kOU{sh1-UJ>
zz+t!C0p&9lZK;fFy3}WLXJE;0J1_g=SIYP2aabGs!w7szQTN3$h6tre7ab$q-g8y%
z_pCLuV)o1zMil%nO21roK`~;A;3~k_I9SH+TsWy7ns>;05Hu7i7!*q@2y$B-iV*yi
zpdM*qANN+$qzzH|sWs5m(P9ZKpEHRHj_niT81x!_;B^@|ke9(BcsI~(#QJ}~`lcU1
zZVzm)obc@=J3YFY--5ilgL|YnYcpxvKlUKwK^*8JT_1A#&#V?M07f_dZmZ0pnyQ60
zhCiRBS<dKSW?wK}rdJ(6^Mwe48}6J0vVtfCnD)|Ss$ANEgxbXx-#ZsJ*(6^~H$<2t
z>B*gb9wy4j*VgD+-7$-g>)a)6`=m-L>t%7P0^hR7;ag_FRZ{BZKh(=kKiYt&sQI3%
z=s__np;_{AdHj1~6(f!CPSH}#HQcBF<L7w^GMd9-$ww9*UYLD{)Xl>+OGWXjqBt_P
z6&*roz%Jj11I(U@cjKXTZl`Nz0k{N{Y6)j!yHhQ{=mbm<d-SWy1ciM;1L{M{j2KY2
zLNWD0t!TG&#okoxm#o3&mO6vYfn=c0Bc|oUE<ff@$)f=U4>7};6Is@W&c#Z#Lcs@h
z-=2Mo!#)8pRNhl<b4-E!<-{%IUq6w77Ad(ebeo03<Au`0MrzHxZZMSd&>`W<9&x@>
z%z~A~K#X(AJ)C2h+_^<&zQfx%3A4=zp=}F!kj&HR_0T$i+QSB{FsHqFLP>~Vhs9i}
z9<N@o7ES%E&2F+CbzW0WXrDWB$QaOm=wDf1QHY#3sr$r<q3OHZ>%rH2{cLW$>4U3A
z{9`_;yhG#(*m{*{EFFKQqsKUv5w8N4dyBs4iXrtks{QpwuQDL?hqA##w0P0+f-r<}
zuX!)0uONWpWrh~_zyj+@iX@rkkVLH#1Th7+@5&g(>pQ5*&08TeJGDwRU$qxC<2dkb
zG<QiK!o$X~N-O%*)N<^qPMPw8BFQJq{s|I!pqCH0s0f^4=eDy)$D>{yIE@Knr>V!4
z&)r?vv@3W5m{jB6zWZ3$Tm2sx&oM=@!MI>lATJUAwaltNuQp&F!6rxFFhRDuk`~qq
z*WG+ovS4atakIsXfeM@qNau`sHOD$4x)O9m3D0}QxIFCfpRX2C8Qd+J#laO&h;xS3
z<jb3w-uq1$tC{=y0s7QhbLu!1?o&Q}IQGYRU+3x-_BpwuMd7jcjr$B58rTR)0!<YX
z#?yb)0b!kyik6<J{YW>h_RXq$9y_QWvn_55Jv<p-9SqqF4_l_A#=gixe3WD(dIRR^
z>YGvY8hu32V1n?x!zVmIh|FPgwk6G>%5yP_F_FPB3Q0HnaT6)&2U=^<GSg#mMj=E{
z`Uxaq4^ztKnX$z#>dSiIz{Z?iufQo(h|bL2A!s~RKH^Ad7InPku2|u{t|$BUH^dJh
zGN_(T|IAuTQ44~-@pOBb5#h`wrGL}^s!uGUW-O0ExHef>2g0d&tLLPPRvKW^x2TF5
znzemrEP<dBoZffk^1kvh>)k`?n-Rn;XpF`@oQTcn{5`F$J{zU&D4$^Uahh%HZkB8~
z#oA+wpYd(Ie9(qV$jKlA1c+kpU;!RE`#i8GicEqgkA`{{bG?7_+f$N7I!o58VQMn`
z7SreX>jn}H_u*8|ThzHj&UNgPWW9IpZB9?@EkBu=g=!LKHO`meNm!bCR(M*i&5I5@
zoB<smF8cP2Bn$vG7+T1+<JA@kgPeb+Kndlzc9J&SM(wb$I$rk$@kl+pYlhNff!!g&
z3T3z>mP)(|XSJeRgoB$}<V|QA4>*F@N#u+)SYcnN?kt{rF%w8mma3z-yH`oFEdbn&
zXH8KGq@}sb5c*-|Bq{FpUEzM(A&%#i=R)rsb9p5_Fdx-0IVJtBU?NEozmI-{wQr&!
z?V>Re=`odCW1?pc;BF1uKr6F{$;Jh3^YG!?oM?LT4T)7yZDArO7HK+90bX79$Lj~j
zb3|OS$0<MBj`UA@d&oFs{P^Be#S?hRWL&Q-o&V$Je7}qSHFd$jWQ^sT^Vk@SGm<zG
zyXHu36F*6hS~q7{A&lP-AqTE+KEr5#Sk<une&jRinQjlJ)4|Ov9HJ2k)*;8h%2t<f
z#Dp0c^r*&%h))<6h@ggakxfD~iOz}N=8A5l`7@E|^SE=vPQ4;tV?V0oOxhKq6xda#
z5+@*GvjsnR@Aw7?7@CeKL*~2ww$T4w3kh!lc}R8M0DoYMu@BZ8wHZyd%$^{$ehRRV
z!r=_MQ@Yfq$jo$Kn}!+udxnbX9mF)ygqO*(aEBpTpQT$6UEoMd?I-QoZTSlKk(b6J
zyV|11LX5@hP*&5k6yXVxHjIBryBa5hip}2-I1q#{`k#!KH;qfuyTWp&abrac#CV^R
z`KUV?cF3%7x6*cJ%nRjnPi+mZ8EaB3a0=?H#98uQdlOJK8dvP(zFX{#e6<Y=vCY6j
zg~1aU9EOL)*J<tHUS{an?eM&?4-B$U3avBd<660@KS^e$#Lhuc>8yo5pCTzD*-=A~
zC|Hl@D<~}K*L_*rXLIFY9R+dz8()?V3*R@c6l9D+KJS$##aQV$TRX1Fzsv5sar%09
z_%o!{OSq<`#h}DY-ty79vtgkEr^~@9c!b6i(sjWp6w`hra8)*T8;yuF8l{<RZuHlY
za8*~}vTu9j3h_)cj<Qe~#UXby+t0fo+gIrwNWs*>FfeyBN0$VuFkjV`xWZsRZy{X(
z3RnG8J_PR300a+)=Pig3HnthNWB=>ExO;JgQUG$N`@8O|3nv#DjM|WzH*zc35>-uO
zzn`ZY2Lgfm2To1Vg^<Q0ZN3k}DzcN2dg=^p1ML`3CZIc^&8O2$uQVC5zZHh6tu&iF
zLx+rcs9w_<R>JD!7W4^VVbW2Hi^NvZYeb1T0@IXWlH4D%{@?WVCE`-9PTfTJalBb3
z!1{?3QaZ;>R2SK;=iXoJd@*yoah+O&XElHQTR#gYXO5WpcM9o|{e&eZz4p`j67A?}
z)@%pGw}&#`HMdiF(yFW}RlVRYZPtKRA_+n95~}1;Dhz}+!Ni`4>3z*7G2US8m_Q(I
zw?~;?QK;Z#THfs^{D8bhlMxe;;6M-*w}aA|??eM;V-B53CGG;85><p6W{8O2(v#=5
zlT`#VF`6wHjf^p@f8{-+>tb5C%wFre)~nTH{Rk^J821e3gG#8FQs(vDf?2V9?d%A4
zH778Wof8@2Vu8LlDolGyIDMK(OrtoE4)=HWgJU>cS$GWN0TzJ}R!XZbjpFK}*;_20
zFBY|f9^yqQU7@F#tR=d}>@CbW8^e9OGPsPGp#M#%oIms-w_{w0d7V@CvD&1@pw>79
zm9@I5-IN)Ko;4#x2WuTqt*CblF}L!NA{$y)%@qe;Rw&OVbFwoW(}@N(W*U#z4!bTt
zjIaZ-&(niQ0N1e}?$f-8J7(g3H}wqa1IayAzV7j&G_jEdYkaHREQL3JWvw_g5oX!n
zGU80Aozi9{H*jEZ8So**PA=M7L2T{Zj`n<WQ6Lm&x|}gcKPRl?|4aK%z3WZmqHr}w
z3nve`Z#~wE$3LK^dOm=;edxXsobegdSZT<qF^mKkjh&=A;6xjJU?jag>nzI4WMXF#
zJv?=4FqYZVyoQD8js}G!UtU`&A?%>v!7Nn89{fO6MKyCtyG{<iQ&F&zvE>%n-aHvr
znd^*4L4ErzeX(-ZvH5BU!k2w0gxknE_~N-XIX2j=6|8^o4fOO#QbGc1_wV(u^xt6s
z)!3{aDXhmU+eMZ#X?&%qgdhyaq<fe_g?xU`uvj5I&(%r-Iobf__8Eu}0#iJb29hmf
zIr!ihEFOIrDJn2-DV40^kU7kOy08MP!sjqd&`C+*EP~~Pief{syBUw?s8oLl5e=#C
z2GvnfY9r|Y^pol~E*~okXAp)p?~2vQ)}Fif@_Xm4M#dtPuUB1v+u!|a499J%g?Ymr
zQrC>ieJvR|8wV)KNBD@IO5?3Yj2Lpm9vp}3_$N?WX!k|uWye7RDBRT8zVg`fkU3P6
zJs#6dA23M>zG^VmCF@8}@ft|jj#A6WI^v#Qc#Ggfbk%0dY5HID^A)rNIg+)XZ8=-~
zO?VV=1ML4q-@HJWKfC$B6CAh5-hMXxwvo;(nZ(J0SxoD0y6}(CiP_+TtdR;si^@r8
z1Q$5hE_ZT<nl4ou(Lg3*>a+gNBndE}_`~l5qq;`d9yVC0!b>71HAo?ci|7}{jdhUa
zFHfKA#_JhNR>^Yweg#{HnN?Xsb^ScbGTpy?fKC$I`K<20h#0wuYtrHJGv{blouFcf
zOm<k|_>Uj#YG!5&R(P!Y*ki}%_2GV@lIkh;XCA_TRr$tskG@3vXh)M)`}@&KnjMP9
z#1vCvEq%z%6y~n5(Qi9&9y@%GAqi{)Npnpsr`ZZ{|8uHgX^@rM^N!ioQWaXNSyqu<
z1#IxK>_|6B#+dn=OD~2X{V0Kze()~^mJIo@vkoD)9ynQs%byzG7zsg3WQl`o*C+q{
zcktlKYynfxsY4~~FOS;7_v2`abrNnWJ~^0{>b9h}3lNTIBfKipG{hy$`K5VbaU<9(
zhwF%jS}-DH?sU5R;7)3dF>Ku!oSwO4l}P7{wByyFPdeBANq~mWxQ$R#{1TZiaT4Gw
z9Z5Y@8Ej&}&*cwQY$y8c_Eo=K9Ys}5OONBIDR_k?X4-fAzu??E1ZPoi_jgO*w!bZg
z)@FV4L+S$~q^+$ULJP5b(#Sc0>E`GJyvkLpwjbWgpgI7?E!iatquHt*(jj%8;PSWK
z#~I!<L@31O)pQ{KAoMWp52_(rW7@FSwXSIh1-urLm~+dcCn*Saji^bFSL<XqKw)m7
z@)Xi0<gI_M0ZrQ{^*CkeC*zF!#`ipZS{@F2fcyWmFMlTNrG?8gkkQf94ePoEzd<>$
zL^YRMB4?${(5K7Adh$9?XL{OxB2zmIKh*8H<Qbcu3o=VhW&rcCngAmmp~qoj;c;(1
z-Q|j@1JgaEJ_v%5m&}$OR@94N*25GI1CTZhaQWl1C)m;!>8eg?P4b4zB$6Wb%ihp$
z`t{tn7+yT;$8Gv$Y9InDH4r*u?gRY#Uxquc@=vuk*%hy)4)>!Suw~fKbzztx(%Sxk
z-p0GY!)cmxzuuKL#Bosd5$FbK9ASS!4YaPr0GIZ*$^D9Ep1>-8<2$^jY=`rB73-08
zEP<jPA|`FrD%a9Hb(LUI?agOnn^r1oUQ6dplKE0_7^|&%Hn0!MlJZ4$T)E_LbZ#x*
zj)Hjhy3Imu3l~3o=ZhQ9r`tr6VU+)Qp|+w@1(sCo3)(f0Z#pDe#oV(``daPq_>h6S
z=2+r`*AXUiD<3fN3(BCm1*^%C4pefv2$UPE=H{mHdtxCTOF!LUZis3{rrzSlMNQ)*
zCWcAFs?Dy--RMyQ)~>1ogA@08(u6Aw?@tOzj;Aqhe5&Fw_>s%~Va2iA5gq&AbH0Bd
zy3h57&|oH%W;pQQ?Fz0U>Y=)LExh-b%B`iUbXwm=b+&;F;htA|QVImA5qQq<1duk{
zVy{7&M%SUTwOzBTQeQsnV>-q}8aW~Y@qQ;W{W5XQ!?anNJ#$#W_EgvGC3C>ADM(RS
zLUu@romhSyI8Hr!f=Mn|jx%ik=WW6&lWDozc>R`bu3mi~GnjT9$4OA~DSe$4>&_qi
z&nK*)tHi^yD1ZL8pUeKhfS_G(uD8?O3O{>w$yu*|Lrk1Fm@o1g41$p>Oom3OTTc_2
zn3Ti4hborwTJvQxU3|Npq&X~P_C?GsbBs2v<=Mr88)1fu4}8f!sj*yGkly_i#FOg8
zw~Ag~CyR=$K8+A_mb6JHtci{&2gf|DZ)<*u40EvQZ-3^ES*9e=DM+*uEKWUl@0EXf
zt-L#k;VgUpyVemJ-$+*$Q6jHTr7af;9ZbPP{}+Q2JA47-V|%Y4w`cxR4)F!}&bIYj
zC?#PHFd0!~z$xkhr^+^Aqm(D;vBKc|B;AXWYtaaqSt=c=&gn3;*R*b_mvogo*`%*Y
zXD{oUd(TPoCgZ<N%oWN59pI49d8cQ&alaxKr${SE;OYNu9PTNcH6Wgt)TC4`VaxwE
zOSdL<#cT8T`iXkGyTRh<&*~I-k3c|C<e^kHoT7tLB8o7NA49IP1!wH{NGzOsP(^$=
zB70@?lnPnzCy2j^U@XY&Da#bjgUDLCPVwAg-;G+WR;K`Osg^xo>>>j?&S15recz<D
zm$j0tdvVmn>xURe80-W1VN5cR%iaY@9dw6v7iCfwaE?26IaULU(+hYx!j|IBogZBb
z6tQJ)|NOD;+-asxQ~9t6Blw8w@l{>#JDk1aK%8S>HMgq?C-V!=E2XqR+Nl-`6zMP^
zU=pO`sIPgHXV~}bmC<%cD=O9}Gv?TTVm*5uvl6=&6@yXss@SX(d+lV_g#OPyGxIvD
zOXMxG!esbV-U*Q)k2Y$f^FsBkZ~wV&??>+yKq-K##2O8B#5ZPeoqn$S!~eIV(VG@d
zd+*G5Rv5sUw7!Kz-vpL;Yi#!nqPpO#lU2=$Lu2U<+{)oMpZ0*W<hZR@;#Q11f)I@w
zBcDX;C>H&kRuKYC0;u5YP3Z^{PH2!zXMQm?Qdj*(MTyB91~9shh2;yABiyFcd(-%2
zp9fsQ{Z~-we2p7%2SA7wOd~X>n}}d@`tbPuggC>pWohuj!wcW}RS03EC^#<uoV`hq
zEYWo(Cywk-Wj?^v*juA5<D?i^1K|=LDZycP>7>mS<V+d8#_UZo(X+0{u2l(MFlt)*
z9-{={G0q`0yYL8*%AUMKidYhSvUwA+OAWTD^@Pl1jXAp{oj@goEHI0)Y(_#M7dEly
zn>vg0-u5YnTq0|Y%5@p=yS>awoFSq8`iwj)SkC{t?L5|*gn?OJR3#ju|E7yQwStjD
ziogVFE~*Ihla#oRp&--<y$I2|XqdO*L~zbT^lLLj1h8}yh!J$IJqV(ZIz7z@1quOi
z-os#@XzAXVx!~UKN1^E-P{>K*;bsz}D?}5kg5m74ILB*r(Dm(9t#yYM4EyAT1!9@s
zcROm9w?7b%K(aSNY&-tyk+vt(A7=yw(Z-rTa&o9YO$<&Q!Y-oMi1++M9`9wnP6rz5
zpS?AAIoNXrVqlKUemvwEtec|?NWGzxrrSqUz8O?}b~=^c91H>u=E3Q7*F{#bHMMHt
zo{Iuwb6)s=+~z4cveg^B5=kUkayo}0va)8yn;9<Qyr%PVmvEJ<e#nA)A*r5XSUx!%
z-Cn*wZr2yWBj5ph%-xXvwVL;*87h!ZETbD=%~fkZ6SNzQ0?u1$415fZs!<R7nyEo(
z8nhmJ=A=m(g*@EUTdpyqld*2W=0&VJmz++i{5&LYjD^e<G8_lN0;V>*G2@?u3td75
zzZI&pA1#7dJ=JAFu|NDcT47d2z<QKmb)vG-ab9RvoUi$~__qLz?Nanb-&+<>s|aBk
z5?*<b_rAB~(ae*?PZRuZ{QUG`_jx*~$~aTh>kCv(C}+i;?w5>d@9^noTci)L({%a2
z!5))B?{IC`XUHG6wnUPOx_m0>fwB02YK~`!f)!MjD?B8A1SU7gDllZ`=%8WrcoxD_
z$HjgD6Lxf*f=q<_hc)N4O})vtqvZqsCQvV)fpw}7kperIC=D;;sX}b)6Kw!n{j~eT
z*FJZv;dO|H22iSw;Vd?!%>1I>x?-@gZy1cC-q>w2j+z+5c<SnO$K~(ftt|A3c(R}_
zfEFZspmZD|57WV*c^`zKm@ZsCMQb+Q6yp<I#W4}ZXvyiSD~!cR1sbmQ2FRV9PTCM#
zn1nE$_+a=m8V=?#rQc^!>3j&;UtM5X5oycMM%+RN*hFOE28K*OfHjvu2=aSZZ8&*}
z+$Zfww!^BrWTZvSp9@=)6*DhFK}w0eS9Z;fWl&;Flt^iDSCjs!`0i|`ZWfTtP23D_
z1Y$BFhcn@^<iS(Jqf&43zx3Q?76a#`ynRV`U4jQ01k*zNQx6KGP=8(01{DZof<!5j
zpfq3(YqH*Oj;2!ZHSMy|$I}bGy{9_2rwVvSawHKqY>UNH`+o23w9FF0bZ;;Yx$~v4
zIP#8o*MYR$G_<p(YX_Z-ek}~}!}+NPs}oz+(l<U%1NEpq64tOdr!Z$#4>>zoCrBjI
zDA~$CNrwzgU7wL|tDt21{!9h*R9A}yv#X+<A<9-376DgBimFiR5TX^t2n>2+@EceG
zZ!f#_zyr~HigR7I68*qm!g_Dk_=q^et0tD;EwmoZFl09k=z13|UR@tC;cJcRW<}7t
zpv-wiyLCwRhZjr78)B*#;u@9~^}8TWX{0XTJF%!~bx9vQ=>|LEXqE81F^;fLryT`g
zQS^~|s`I>nO~nBPM=0iX!eR=CK3U~$u(W7UgmbOxBufjLfm!z!8W(A_($F8Tf<_KF
zWoLR7uN_J*dhn8x;Iy$g{fF~d3<wHVyJx=Jy&-kiee6}^p$7H^MXMW*p<*JP+A*18
z|DrXJV}nq8ykBPD(masjyo>IEoS}fKNEb(Rjawn~KB2`ZlpA4{K{R6cy2JBO^@Mgc
z=7aQrfyCty(Q1-A!<K-gZbKSkFR{xFNjq_8BcdlbmrMW{?J7LUfeKLznaf5;4ZiH_
zn|V|g<tUm$^v>#1<iMGuqrXh2-x1%pBgVIl*Q%2;9>0`YkCzBUI_aD#9_f&MCCM`*
zO<$IVfE4++SfM<T({#tE4&hkh+2F*BFe`}P$eS?kz3FXjh_x6FK+^*Owqo8xb<35j
zY_-B~?Db_1)g|=6da|tY)b2^{OvvT~jx$iP&mN$6aGz>(HZhjR=tX-XgiFWt#&n;w
z`}TVnh}8BYeqd^+`z3dOiile%rqk>VBQ9-Ml?i`_I)tvt-kEnvI>)(m=1Q;QMT#_S
zgmX$Lgt1TxlRDU$<Tyw=m3SU_(F9F{a7v2kxww9Wm@_Q9pa+-K5OkZ?6-~dm{(71D
zBak%Vk2W)Y>of$C`GYz8qW%!D?hk->ed;PYe9oTybiO^DY9sOW8Ryi~xi7o}ZSygt
ziLtx;JFNvqjS7YJ#+l8zhI$-V{v;g$4y2agli(Pk|KxeMLq$8Or-kMCQDRgwfz_%E
z06a+tKvs|Z1;fxz|C10cE<H@Wt-{c8@jZ;0Y*cPfva_yTp*zW_!gkVP4X6ALnUtq?
zs`O)nt?LKARvFf0_@s>f-im^~=Lk*QVqC$SQ}mP0KHmAK>D_Z(Zo_)Sf~~vr813zX
zSYL2T9|MG!B=z}*6b}<@IGRaw#>I@Zf2D-I=a$acEW~xVrpV!A2{{8v+GZ3@0jqKw
zZv^Y$bqu^bPM^NVUedI~1_(#-pnukS<_%Uor4of@a<&Tmqe_Azr0o8YpI_Gb1Gy}R
z4HkWL!$LKq{h0NnsfWDl?!Wk#*Cxo-ABkQI-E(O-z6<6M?n0@MP=tMB+GWy3Cjmnt
zM-NQz<-mk703Cv2gUKFfd|h<8B&^0j?Tn(LQ0KBadtl!L?IsQ$m`|SpbM!##SR<^k
z{VMNqjoPoW{snI&r(?q{QnhIQPm3EJ`U}jZeYk!xD;`|nx^t(v57PDcf#pr(^7#2R
z+m>MYuqg3-dYiiK$06<d#loxAQ@vP7Z&qeED!M8whcgoWbT{_uV%HL|0n)Dbr<NT2
zCABX0!;6$|f&dLdD%U1L=%AC`LTa2?qYc}}4J@fX8<ByCS9;zdm}XmW`p@c7Q_dL>
zPaBbGlj2U3-D*|M5`tP2+<kDBzn?w$LVHf8IPIoC{_?mmi=C$}j(;Go-ud6T{HyWk
zU@v63e$AYJi~-az)E@x-GH^61GwD%#vO34g9VaaOWkI{=nfPqct_D7c5gkeG7PBwp
zK#&#X6Ke=xo~xb=3vnPI1RM%By&sq{sUbgx^v7DlCZjJt+%Zp|UL;6~Y#{7TzM_X%
zFb5Co>T)oU(}REL3kkBxUp^8&H7>nN=3H2qYoYhazinY-0|j6n0a+mW|2BtiEU5K3
z(-`0k1~HhHGP8dB7+ObQ)?74w(JG{;OW<{ouJ|(+EzV=AYcMI~Yc60JY5J}VK(>39
zbP&w0GJb&u`9WI@jO#4r+(vy%^08XZ_Q(M>lyg$kT@mSNjr<NZ9uWIquGDjUXJ%)i
z3MMtOf*(eE7`PSr6Ru@!-aq>NYuFysO+0FxaJRnyttF)?8&Ve#(27TY-fSZsL-(63
z>%BOfAbB`uO<Zq^UJCt_xWLRUrl4`^#XJuEn$fSFGUe$d8q@L)#z++AHbQLzhNp)j
zZsa9R1WImVefU0?2HwUfQ^hhBsY*|{oSj9Z%|%0wo8+55$yis)zRb|3@0NWb2l$17
zsu*^P^Go#FD___dw}Scaz1@$vCl|WU7cLaob9oLBNv7Qme#M+fl2U^xyqpQzCyYU3
z3*J4}R&hJPeHDW`o2*lTLfZx-!WSkIqgOLK*8owZE@TnKktM@qOke5WVDZqe0N>H+
z8r>_)Uz$a10k+o_w+{oGYb^QY157z`uE0TZu>Lx*^|s^esSlC}5^*CNMt~;jogII`
z@hzw6#uuz>-Ph;IMBnCY8AdJ497Y6)>CmR+Ruo!UF24Z_i1^}=^>X^7P|>eb-poSD
zES1>6ELu&R7K{qvBx5pg2y$Xm02jh>b&4TuB%Fm!X11j+0I&xSbCq?rvgofhX9~o-
z0P;{`3lOWucT5gCr}RMO1tuRCD*2X3n74~N)tuNtIE0c8V&SZKa!j8t{m!5K>P|VD
zgryXA@2_z#LETKP6nNdFe$F5qQl6;%63qrfHeBKJUIXyl%gB!)I+v0M_b<&Bc+{c&
z3z!>i?>v=$GVO79s3xjOrfh2vOuA^(H0>+02cRuq?}^WJkm!R@Yq~_=mj`}PH?=>=
z<!0-Z%8=HZ{OuJ-{ScO+ojA)$wG?5eOT)it8@mZ<qC(>e{fXDAZKa1(k8`XMf;kEX
zlJARZy5eguNKpAt036PX9qCUjDzz005o3hIcF8SL{Ktc9=vrZA2tSg*06%n95qQto
zwJ<LGhxKN&zfI<K2H3+aYqsR5Y3{8{GVP$^j41s%y+Y9FB~8{E*gk-5#g8;LzW8bB
z@^+}DE#uOlh>)<0nX(j((;szzhSPz8G{>;u$W#{AV`{Wom^U=O^$Jl3R^scmr(t56
zjeyfv+7WVCJ6E6zDe#`F)mBSOdJ2jqydQsrRAMTm5j8LkYSIL_9?i?CPxO7GxWCu4
zqJM@$_K;rCeG7DpSU%hdR;0^9DT%Zx%;AF~f?FSJv&yhjq*KI#0rp8G8VHy{9SGPl
zVHlbaFBB!e`R=1a4hhQY`WE<g$oMvTxf7g7QOv~r<J%&#hC}8-UEV`qxt)b00~qHN
z>UUc&G0D#nA(RC~AicwfNP;ZS&=QNnZ4K*PiC0~?z0Tr$kB8RCJrm~*=}rv5Mz)~B
zm7IrKr)Wlp$$l=EUqLWlO%gr(E4k+xVa7^?VI83N-_Y@Ou1RjQo8#L%SWmG<9+Lt+
zhyKqm)EbyFnLWF$?iRb56C56qGbxrfa~1+%NI$gOgW>aO6txQ<+HS$-!>D1%6rXN)
zhB<h`(W1fLL+NA&2Vk06P`fZ3IYNU{VT%~zBY~!Z-uu>~xlthuqR@0T)J3ureG|<H
zN;3(Q(JchoU}^4=S|1ok)A5DB(F6(^?DsDLMTet3E?h=Lx9g}uM&c*e!aKis?HZu>
zJ<62nE2QLCQ+cZ9#|v9I2^F3)g(bnf$}>z(RUdhy7BrDms>n?EUGxpbqbNB@&22QV
zA>`ypsU-P>uo^?tn}H!t5>tvosR|b5T-}x~n5F<bC*IYn6D-Y2BIS?H2$jU{=QL66
zpZAv!*m&es>W&M`%9;um#y2kC7rnn7*X~TQm8gE(c3y9C`Wp9CyJJ0;>#xIiGtS>*
z!fDqjX4u?A&cnVdH8W4F%%DUd<E%;q0#`~y$VUqBToRIMRbJShASbw#x<&vhGdd~^
zA(t^1!N<DD5gB((z0uA=UbLhlNF=yBcC<8rM{ygBKc;R#TP!;=zxH9S<wTl)X!>@r
zP_8*a$5hDUBPYXJ-}yKH<wTmyAD^djxU^V2Rxq|M7G1Mf2KlQMJXJ9wNWzVbV#e9<
zdKzggF=j9!JSxU)#hxVtVKM`q><6~PHtZC@bjYiD3qfRT;rPoo9)nrJdnd)w6Kfi>
z+sT1TAq9}4#DES`s4PcX4}r=xOgFI<NzmXa{gjwii^_c?HsXi<|H_fN@r1&&Ap)I4
zK)T&CfA`0~_AaIkNCU#I-z(iw{oN;x;`+^{YsPcfb0`T&x%R|pdf%1Kj<NU4$e3l)
zTA1<>t1b~W;WWkL9ZBYs$TF++w*eFU6}0aR4TpEshhT^bqn_$7=>E-!I9h}wrCs`R
z&N9k&i7xRht+?ofY^MP~FIPNpkjbuAPP2IA+23}e_Cco|lj=77Tt%*5`m+xoxO`hg
zO)ts-;UnFzot!ivB5`5^(jnYMM8i<go-uaTSi9`u&Ic3V@LJnZL=ONQ&hFAhdcKlB
zcleJwLTY=QiV#eBzZAP0-Yey%Uc$m=sW_~zLjwUfMfU^+N$1C(%)c&H7OWnSrW|p{
zv229?frHONtZ+hrqYlQDHiTY~9cO_-t%!~`B0}TF@sIwJ!>)SM4MbnCgvn`CeTA*E
z^q(^`m6Va;Fk=)DAX3j0Q@_j99zAWO5*GB5jj7*aN>dNFO;H8r5l{EY+8=8dc0Rb}
zk^cHvrz%f2rX{>$whgWp4+BUCE1yE@MAjGk+E~v{UOOjUQ8eWhJ)EQEqrRqxDyZ3W
zuDw9~u_K&mrXLVjEb5UiqHotH&hI|UIDZ2rCnhu-!j=iaIkHkXscso7F&>ILzDgoI
zX=*f+-glMb)81K=;aG8HC;XB`H$z2mq7|4y-h(H-QPvQw3jd#o;wIWmt51bC13Dus
z+H8p#caE$pg$qlFkLk&CqV0o9g|!oVCq0$y-%@$rM!n9)rO`uj-dcgB;5C?^l<#}f
zB-p{%XS^$=u`hH*#w)mfNH<OBx03bHqJ7P%=^|`=cWbhk)d_GuyDa^FS$U_^a~?&3
z9MZzsrgoi^l?WQo`mP+TD=UcD*?BWi4G9cAZAIiubmX^EqP!$AhXh;|Qb>^po*^HL
zU|LL&SsQguCKCw_o!uNm5khdC-QM>N{f#EW{maug^63slCtxfX6-Kdp)&*A&;U_B|
z77h1t_uJ-iqY955pKx_X#V2BS7tsI-xfMjs2J~rzQii4d>6j<44i)tADhL%dnZ_^=
za>BppP@I8Exfd!MULKVJ&@R*=kDl|0>;bHiDmr_E4Ux=I-C#@b#-dE9z}t|J<={6M
zmFi)=;N#jSr`R3PFI@6DW(9CJy9Z(d5zrZ<Pw2*;L(hGVgYrC)3hX{@q>xptL;Pr`
zr4%1hZ_|_}r;=NxnuvmTS29X^{uuMDRjbVO*R|-S3E^n@au*#9`6956Yk!ja4CHaq
zWgb!0x?#VhSIx~hH2RR)GD1fpb|eP_CWK*xjAQW-L(vtx`h~LxNnmvcLykQf6tvM<
z92c4tdQlFRj!Iws5`#~$Sww&1NQkJlwp8e=7alh_3d#qS(z}K3&9$?6(W;hdk<)Pw
z==I(rX1O)Qk!ZCb>r*|79sH~>X$x6354?SpCoY+b@JYSEhy=_LeVh@YNfiZgzUsrh
z)3epDKOj1jxTFV+!E)6#{2^s<Wgx)ASr6!gEhnJ72^eKGI}+!`;~hRhBIxYBJ5Qa@
zh!KC>l6rW4`uew)P-<pQ7K)N~x%fk>>HL<nEg5(bT>)Bsm#?H}cSo0BA$c$zB%N`<
zU6oVcs#N#7N@cc#PXd-;Q}`7sGezfzY|W7|{AOY7ve~5G+QcW%8j_d3?RZj}AQbl&
zHnp?Kqw*&LM7Q|;)uvy0K`&JB7DcgMUfNRTjqyvk|Ja684jw8U@A}mrdspYJzWwvx
z`kB$HD$Z>!WbEg}I8k#xGk3GEsHoP1=4DBN(?L6>0i9}sz;o4-g_yq0G>e3G{}kL1
zV~l7*c^6&~Y`Y%JrwKq@dmdIEXAyG~b2T(Lq%w#DP!?6gG;$dd0e|JB=iHa<i~gM4
z^)(Hx7(r8Of@pbTbYyu}WJ?G^%|1DM`L%!jId2;aI;6ld@D#aJI6@Prw~$_s1=MxJ
z#0b2oyhj}EC7OxL6U6HVf<kM~n>lQu$Q@BoTf!4+HiF9*kgXz-lk49Je29}6EdsMB
ztw82TSLEP?LBKJzkZrR5vlhcZaEby)Sw`1pc$s30YU4nFAsjbAAFASFY9V%UYVLN#
zCP=(39t84v+Wqf$U!!<^IWx0AG&6Rsrdv!|r-YT*z{sDeT0X!)3x)6Px*CSGGj~V0
zPu1YFS6#9&D-NR>voHCv11XwFpv49INYL3<Ks(LJ%O#u#!)>d@c_Kcih7vyyYkyKJ
zI!}||BreFbBIULl)o>(OCFtPgIC${W?!ZE2qjsc_S^lB3$K^7ZAvQW;v;Nnc6s=EC
z_o?fr?-n?YU=bQ6M`k@^kak;$N4i(DNj=)$j1fxoZn!(5k82@a4QDy*u&&}(G6V2(
ziYaSdt{bT<r+B3mQUIu|&AgIA5#UViLW5~RzsNdpXw58UrHRa9;hCSH&lB?YU^Vdn
z&E>xFb?yz70^TQjlfQBKd>JmZLsS-0?jW*oYJKx*&N^2OqgSPh{YdC*+K1AwbDU6J
zGpoc1HANL3lpO(pxi^gzsK%+YC3kveQOODF<{6QF;(aLgU9!;MPMe&v%+nS>2;7Zr
zdVIZR+!V_e@dlw{N$wJ3azG4=T)Z2@xoVYY(~m5VBECYHx#W*m2vE*=yNaGF6XW4e
zyczIo!yUf)`QzSxPt=k7!$%5lm$t%ibgwD}2Pf+-*HrE{A2U7<-~iy4XIC<fOvD*T
z-Z@3@F^{Prah5OCF>8+4nG5$u+r6imZ<J@j_GD*5FtSFTQ^QK0wSS2(*A9sm?lUeK
z<Ejy28=)#F!4-omf5>NwGRJ{by5eHWR}p>TrSa{tZ4TzY7N?I}8?0YtL%mDQwR;9p
zPXF=hbEzIUAI3<`e8E^RKy5*33_!<7n4L%qp>L0+x2+LpagD}yGLi#FtHckArz8a<
zcntz8A$e+4F#nV3gpd$ZZQKQpiH+j0UQ-k_)Vs_9OX2SK?9B^UmNj#Y2$RtH>J7b>
zF^xAXIke6g*pY47qV~;tlhg(zmC+Z7$#8X`V|FbxIzDEWGWV5m<O7tD53Ll|%!Yah
z+F_LwP*TVVWcZ?t``+HU=6gn0JAvI3+HHX<c`=3PAm)4~q<abLOl<V9_yuN?$*n2C
zSy*kUpXqRw&{B!R`=c@2AcR9b3zN)xAi{$m#cD82=>EDt?0kbiZaEkAH*QFabs$jc
zsqszaWzj2layS}6^7qT1<KQ~4Cq#OqnMK{UA8DEGu|uo=e)G3zqijop&NAf(z3E@f
zHE?P{Ny!)mId+IL8AWv5wqwDAZT$e=hvKT8d*EY24of5Omk5!H7TY?G7nV;J4k?Na
z$Z_10F0hh>6G|9(+nqi~(09qJtQ)5VUC4pfl($q|e!iU>`2K<AEDv4U7i1{N41WF9
zSKBfC!B^-L%lgjlZ@tQac=m$oSt)S(^BOOpWhOsX>MKbN-V!!eqW3f<$k>ErS-9)x
zt9Vs!Ml?Z@yN)xo?ynws1MS3n7SGe(?jVK>U<FZ5aeS89lUike+7&L>8TFH)LxPnJ
zAo&yia|pb^Qe+Lmz75h;T|UV9yc!24t)OtFv;9Xw$Oi`!S}-57lCQY0{`gwi+c!gB
zB|Ky>JnWY8j1gP;P`_hvsOMoNgD`9bJ=zXae3kAchoofW*||{;CL8`1DUqTXoLi>c
z<z5L@<XX`}1D7p~nL;Wqq&<TtS^5wS(gtSr3s{!+QM?0Y{a0L9q7U}Hr=aN02Ae9|
z0SOxD6YZ&@_!y7xvZJpp(RIcBVd^tSJTa%G?7be|>vlOTt6-$vkwW22fy;(D=P>GL
zed0+c=wKo|mZ@EDQdpW{t*y2MMk7aA39hZG%`Jir_(k*q?T;Psrr5WZMSH0Raeko)
z#$3^CTVbqj$v+S;A)Kku1*J*UKT@3rA%o#6Iap7SrHq0t=W=WSM~%~SJTC1o0cdi<
z2A2^ZNb$*+{=d#I(q6~@hh_BI{2k@anZE~bUJHq(v@w#YB6qTzo8SzfhBx|)$Z+|e
zDHnRy4O!vTqTSa9@Fg2>yF~L^A{Fq459`JB#dIj=t;HyUj676yP@m2d_!qbb4Nm4L
z!uvXZ>@cJ|Ih&M5{2pyD9~kg~$RFm|!MrE#0W<Y-_Fs*o+vKiKi&TcIh}D|2cmMc<
zYZLn$?@~WOS-nztKYU58nRju}<P2Dvx-@^q;QFqk44PUUpw7|EGN&|if*uD^iLeE#
zs;ZU>oa@)}D@;4ZFC!+=J*F~tDxex9B^eH@GPN#u*Q8t#rT<2nr?EPlyNF>L=lKCM
zHFsR0+k2CB&*B-*aca0TbRRNoM3nwX8R9U(5naropxQ(W@bukvynNaiFreL(Q46a8
zG=`CWW~fT4dr7CCHS;&pS|{0?^0phh%Hib$u%$=B8k`{eMI~ub0R7I8&N$`dNk{fE
z>xmT=G%-jCBoXw;Ab@})*CaLx;ift%xqMD^U>Z+oPckuCI6BHgs_Gm1%X(^=bFo^v
zv%ZK8vh@H1#Nd_je}C@&T4Etf7rWQ}yT#;-X=+$?-MSv$DX6((KNH*ff?6{g*k$m|
zk`%I>YQT>G@Kd3!WQ1giP!DrzXbQ3z#%D<-&S(xi@B5T5OiZ<H69B=4!jzm>RJ~w&
zhXrfqDuAH6;N&a@8CXRL4MMpaA0kB_=+l=fxmCY<%Kw_)R2lLs2@coh{HWzUGe_c3
zwRfh*j0OD*_lMv9{PgX{N*akV<xA=Kf;iW$*C~7>hK%%j77l^*k!<dwN+QXig$kJH
zY-iS4JbI$I1)sOc2BBSTqrjNLMv$jHM$IK<yVoNPRM26O6NGy1nR>7R0bn!#U#;j|
zoDH%)C}c@u33AyqC#9ggWeFixVF2&IV09S>NA6*}>9Y&`ANbS%SnieABo(933(=SU
zrw5OFYo1I^K);>#-^b(+X9;(Gv6vo74l!|g<A0>3mheD&C|<pvWTfl;7Q@lzEa!{i
z|F+18Puo;7?>qjd0&Ese%odU_dP#nW(eiZ)URd4gezi$=wX~lcOb+T~f;kt-0D!m{
z@6Teu;38wDcm0&F`^f?WImMVWIjtS_#`f{&30zFZQ*7Xehw$>RpGhKs_s~({BVr*v
z;+*9rGqqIQy5Dg7s)!nBUW>53NxUO`{nTq%JJFe)77usHNec9NpX+S-ErMMVv@ahM
z3aXGylVrRlTvCGyj~I654RAz1e|4G!e>ohOU$6|MVNR8l_It8FcdDYclfiTaJzCx0
z-g25g6#Dq~=a&-+j&YM&wYi4-rQ=Cf=T50m<_io7wo+kr72n&o5_|&$14ZI*m{hA{
zd~eY`?48-x$OuQ$VA~!KF9<C}^N7|vMK@F@RQ-g{*L#Q$1Jl~6R2ZsSy}%g#J+qj*
zq1S9P$*3C1m8TCq@=Y)S^c_?Wg~~DaNEN0KKBS)uAE$Zxq0VurE>9#&`!U*6?`Oi5
zb41%hywOV5hRvU6=Io!~Wr41m!!3%vg`D`V;?>w|bgjT1oL6^M_8~xVJ6s04_6i&1
zRGRCD*J9<}m|02*d@wA~kmdueoJ^?+j^k((?f{5aNB9s{>nR(DA+ak>^qa|Hu+aUc
z(d+&LLb0)aWbF)r9^|{MN{{7Mj?<0(gB8a`3$Z=%l;2qod^U)1oo(R}K1soUz3^br
zg#XwzGe<jas8p-b=A`3jaV%m^82+(;=tGqR%}(pVh8K$W2xb!~mrB?ka{fnHwPX58
zrkG)B<wLS>5VcLw`HlOkMavw7BpF=N{me})aCx|gN3SD_=7=<MZ;1A|{Ct%T#mBmm
zThN<W_DXFMiT>9sPz!z*vsjUe0-TMG+3T?5z@EFm)xi8Uwpt)-p#u}tj32KHkVnG8
zl@sVk_syXm!@U}Zh?zEyVj`DaVtZ(g{HZcebcUf1@J@Ulvow9%xoCOl95D}OsM)A0
z)ge@|)g<}(Q9TMR)dRCk%^dfK=4h-yw9r~XS#r_8t9_9gOLv0OtCfp{E+1yzSIc83
zUg9@0Z%u{w%5U@`t`wc*942%d<`4J3)ql@W52qextQv<WIzvFf-GZRu*RVy}JF)Ak
z6=0S}KY(ZN*6yJ%wCVSfwG^O@L*Wjf;p4$`Qb~~TC`4)cS`a4|Gghm`#T4We5kJ=g
zn>mi7oL%RZX_`udhzny$9Cl^<!ZM=ssXXcr`2BBI^qbV|zW=d5emvUq246?vNU&t8
z3-tW)UwmCSJQlQj-FT_{=QDTunX3b9rMlWie2>!`jh(BGDN6@s+ME}jPwx-k**(L?
zJzC(j9wrc~OL%C(l@M8npcuyPABGX*&LHu$Fy)@`3=|4yAXHlFIol;_wzMV)X+;en
zb%5CLAejc2m8}^$l0qk)7j8Rm@^xo(1Bl;V5ET}Ccp$j7d|;VQS4W~p(IVokHa?#o
zd@vA$SMPmz5)KFLSI4?3!R*>XA+L}Pumu$JW>_$CC*J73pgHy+$0DsYLZ!T!MNYM{
z@FU=W-#)liBJCLOf#BnL0TkyGwCD)?OSA;gWzsJlRxo~Go@})WMXMC5w?%0*@+#yG
z_=ots7)i|32V}49SV&Z!(taK(BKN@IQ2s20TZ}>l0U+oE$Mbpo?1PP`1rEfP;+R&s
z?mx56VLACw+sKNsL<fXsXnPJ;A?~Jl!L`8qqKMwjxl8UD`dzS?@PH_xh2vuv$H<2=
zrc*kNiMXN4mVjqt2^j;%dA+JlSPdHSKCfYPZ(ho<2(F*~4EUMVtTb1y`31H#R{99Z
ze3?!O{FZb3Qyl&29mrkq`OlI+_QozEqBTC6ztfE!!G@~&7NwYJ<!~{5T!G4RuQPk-
zF`Oky7@FukBe<_?ZGeMFJ&-Ncx~WSESLaXx-PeK&>B$F&H}dU2#nW^h*Nv>|RME8Q
zT}WBnSCNh3NJW4Z@qHK<&B;x0cGZtKW6bAO9DK@uRO|5o#(eR64oBybO~dF&2<Zm)
zKUVsuS8sXVcjz)7vc3f@-rP?R*{r(4xReAeD!q+yYIICA9d|`f0=9!E@1HflXwL~#
zgz%uwc`C@8v0#li1Xm7_kdWF0M+7mavSg#uV76#b*VZXGtiEb8G5U=AI;DVQ;?a&d
z?RNn0P`)92+vMkS5}YdIEzl^L?4}m{IU{rLQV0Mg;!xBmeRb=vpjLnebQ$7*uKIC_
zr=D2{Fk4XFDApI$$I8*8?U6?+wkB>;Kcq2G4Jn7(YE>+7vG`<(*eszygO+3)c;3#H
zw9yW34(lu!Dh1A8HDodq<ScBzN~lP2A+iY=SSA?F+`t@+&<wWDF9%B57b|b-WsQo!
zFVk)zpn^{lP=2$<C;xGixF*vmjgU$fEvU_tNQkGlvEO1JNkD`M_gFE+Q1VRsELlLt
zT^H5JVYef1Gs(CF(GO<PVqn2@Zs(f^EEFzV9Mu6AOgt6=4N8X~PKQ&LNxjr65;$YP
zM)JMlQnf>K#;9%lP2vqZgXa1&W622Y?eryox>%O~1D@snTo!||pM(vLU&x3Ki}v9=
zZiEpjx`Y*4X{`2KTkbyl)|oETISGO*=+}k3Aarqh8(w!*Q)E13+SNL?d>oh}&s)F`
zODBEXgF%5iVb`vst2+3c+NdyKf*GXvmAc)h%}7j_G(c*d($e7~ifMcKK>iPfI@vx%
z#$X34j-@;0A90Qd7K{%;2h4VrKe_pTb9z{W@G8VQBs_-f2g<WvWKt$oC=4k!4(O*l
z$s@%hVOKM{%sAFgRY;qZp74k9B(bauFb*RpD7WJU|Myu8{2zaN)kZ5gtm#@C1gT=F
z_YvV8XL`JckjY+!vyX8P)czoldArycfg5yA-xks&3+Eh6p8MYN-&ZYgq;c7?Xng7L
zXS#w&Q9qtj=oT-yoWY2^T37d{nCER|g&rr^aOO^Dd1lSq--xAIL`m9#1VXe6oADOq
z0FPCNOqT{eBqY)t@B(04o2ji*aim%(P9X`jt3?p~VL<07i#HyE6Q;Qn(kjoQ0vZ$N
z@kYo+|37u_A0Nkk-gnL{m&{V3>-i35R|5#9b_N4z0Z|eGQ7WWM?D;Nc$t4X+yU@ac
zWa?!CrgXI9#3G~QY~SU&vzQe@8;l4Fbg7q}GeLn0?Zjt^vQuAs*Ag^n(-);CWhuur
z=~-fIpL0!WQr4@drgzP~pIK0GleB-ecdrbI{W<&n`Fx-6^L(Bk--9y<ry?x(VO%FP
zQJBnJ?8PGM&tD(<QMigL(X3fm8NRc`;kG!J%fSR^hrQV)+=SUUE;)q10m6z((d)vO
z94)!I@$>$ST|~OWSTc-^lv;#@LCScGmJ7PYACY5rF*Zj>MlhL?SC5UuXDm@tWQ&5_
z(Q&8dF3Iueko!;>O&}Q9J`-%&FnI6GZGrJX^$@ub-WluEA4#02$!YSBar69EJc|T*
zz#aTa>Av2pH2n=5*DsvKhT$-XJ@uQ}K8e6cY8S0n=S|7dAjjQfC?_NGy8HY5CBkT+
zc5!K#DbrrDN+4bXlIt-~?CQV}{_HGgtBj&4GPH=)83M#U4R;X*(I6!0C_5aG@>@8#
zu}*IrAZg$7Kq@92EVszUwERGIa35_DX=k1-Rs3=mN?-ZT20SvplkTylHx>?*-Y(r2
zySMZS?g3Ucu;P^l7K6!s<uHqm%UO_`NU^v_;JF-<=hazG6hz6z+=Dtrt1ydxAE-pu
zt5D6WShMu|k*L@LT1%3B{7(SPd)Afu4*D&&p_JjYaQp2b&21N~oR58f@U!CQ|HFaD
z{h43JQt@m4dE|swTKfd*XSqU(o$z%Dw)n~Whc2zf17DsqpH>G;&yMzf*hY44UG1uq
z^v6STzSYj8Ict$Si8k6(mDJSViQ^Yth9bWIm^(E4TvrJh8Fd^Z3o(>%Oc57khuWdX
zV%QFD9HewuhpD1e3SjaleFLNuJEw@8Lj5A=U^6=DS0C_i4~7;&c6Py;UiGuLM?vsF
zwV$0y&MBN1F&Vab#Qkxwo_$6f6c9Q8ttt&%L`AvT#;QAeO41^b)zSldIv8*yP!{op
zqjslO@i}jE!tj&GOYF}C=Csa}`CBY9c%ryHbRbF{R#QTvw@{LcSq90OE)X6wJT&cZ
z5x*oaKre)v2H=_#t<#TuN%G{g*`{(mz@boCb9vw6?6P<H-w)D7T*!!dtN#je1@U1Q
z<)k|KhqBvq{h2}QNg~Xlj@;7=Z?uk$&R$h=%*e?uxPL~`K!<}YM3PKi_Fi-r9Oz<m
zY4*j^OQZM$U<`^O5$sA35E1xk!)3SKsh-3>2X}_$%gK`F&{gk6d)?4gUk>}a)A#x_
zUO(Jkz@C^6v~$>tI6Tj9Wp1B2iHq9<GeB-v5!UXQK~RuvaLW(uA~=kV3sDDC51KDN
zQp4XnwISvlME0;NCkTQhd}lDfz$ARQ3$BMr0$)``9i&G9v7B~w0gofj$eewHkRx#=
zpT*Oy5AqQ`CnX(dsA;D34^qY64-$tKyCU=8m*I%$yI`I6uADSo5_6OB=9HhrO}^Xa
z53)=Ba(Unsks$#(%Pt~subg_7H6S}KBkyrWNc@w}KJY~EtE&sWxQ-VtKMUMEdv*}X
zjALqE@<2)mRKU}GW&*>PZ{e4eU5zhAONt~P@Bx7JH{xTYW>v^tC{;_oaV|AT%Z7{2
z3-@=PbYu}@lJ;g>>jY5gYT0;f9`k+A<Aj=A+ZG8QkG9lY=fnI<<iUDs5i4$*6^A%B
zNsC|oohNs>J!>MqO%4_r^1tj|R{(@`OR&%Ho;W!8qb><X$EoC&u6yHySfj7nKJmhG
z%uz@d5j5*75y!)wQ764av&sD?TW1dr*h2FDgXM|nulRmC{A^m|NNF5P${9k4AbsZj
znI_{<6vodKil76!hKH0GxJsDi&d+eJC@wrRgB$wK&ftl`;fcSMoL+<0V41peqNTp*
ze(wjFBD@1B6FvRCr6XPs$+<p^{ulSXLAHrrS+#4R8I8fv!pTc7^Zz@jfW4g%4ZVN%
z5DBD-K{z$y+r<{jRx4%yBCQo!%i@bf(n{ijgWGNQz5Y4h2loJPMZ)Z_PWc^@7m$jP
zksx|{;rZo{az<9!$0cuO=+t(PLl!);2X>qx$*>>>HuZ&kmPq~YlP}}zxQHEUJ?jgy
zgSgq(dP%&gBry2FiBxoC9db@6QK@pOG{+x`4x1i3gT(hne3dL$XFO4PyD&>&;$eJC
z!g6rtkx58!hZIc<iQ;~8rrp(7_XmeZJP*+mJkSW1`>Qtc8WKKyhixEbJFS+;m$wmH
zdlY@~wt-8&&#~Ja*%3Hbh*CqY8zx*_wp<C&`N^%HBvAqI6Nd*V4mBhn&BC3CYPYB&
z$~X%EBgBV(YBu)FOGo(6=`dQ3wISDOPki2udypfZ8)^C;B0#n%vQO%-ElZ)t6kOn>
z@1DH-PXDOw4RS~mNGBpQ$8$`5T1-wIQKIdZB#VE^5Pz|2*eCGj*|+PdV}8?NIVZuE
zY)9I}PajV_{(t<rcVBqR>BY%~&VO!L&fvzy6r5iXWOubIHBqz<_P<sUOK6l-a+<T4
z|CoTmG}n*-UhS{Dcb5*Ib-hy_ja<S>n7wr*wfI_soX9lr|1FRQTf!DH_j~5;eS@C&
zqVL<>>H}N}UM2sS2X?b3N@V&%7sjc7X3*a-0P2I3cb3##M2oyqda^oFHLTRwA|dng
z@A{ePqlD-4*|2--!pPwKGh|CZMfZSmUczQ^6d%k8uM)!S5@<;doLfcW!#Q0Hs8BAx
z!6M&?&phj3$j9hNTB7ty*-+{gmhNC|!W?jkV0gR7V(z1>s9QB(nlC3dOT?fUDv*)z
z{VbOs@G%k1kkC|U>P|Ae-4#4per4{-T_eyDg1;&GpqPidKC<BuGVWn^vLkNy*}=Qz
zm`%KTW+YyX>F_XG!`1;z<V58Pe@A)`A8=sYsW0&;jyTVVJrq0~2@@YZAEc;bF%ko?
z%)qPBG&P9d1F57?>4#!lT*R8K%t<s$IB1%K(y*|&XX0iCAvC*xkYlA=+5L}~#Yxz)
z|8ceBl5~+6OR?9<3b;J?=JOwXUF!fX@DQoF+V~Y8zRJ0@aRvy)$3%2Wa%&*Si+VTC
zSxyhGcqY9>bQ&!k!O@89G9#Qw%WVcp8&g6P=MoW|(avpLvWJH<WKiql3|f?cq4Olj
zypzS-Q5RFd4an^xup#O5jiDb7L?bg>&SPV_YhXjaO?U!6Vb8r)EyHw0WJno@$PDw}
z-7iO1a5#hhg!_lj;vIOT^vn`|<&rSsJzfbr^-%e>`c(u1^sPj$cJGzdY1Hptwq6nb
zFjSl!6&ny?MsP5~y~y9SEdXv789E(w$?hnI_tE01KEyY+0e=WWzEiY$Ku@?QV4DE`
zVC7_$z*obU^q=Kj%QODWVDO4RQobw5Vr;A)T83gU&<WWJR8MGZ=^uRVrYJ%R(wto~
zjBVwxLWtpr9a)E0!IB1EbuwebD4>m?E3Q_iUcRuccl<yv!7-!m;a|b9!{IqVZKE~{
zfg$6cG9FR8Rvk))dx}-=Ip5eqfDUGAU?9Ab%H_;*fJ;vzeK?14_6%xnxi9m;%md|;
zgd&yqZ$axhUw-bZ;?g6&Jfb+`fqK{5KeL-@6}zq+^YbhB5nGEx#dCf!zG|1nL15y1
zKSl?bO$=X+qItnAMN+`1)II~}cF`wI?idkfzm;{$c7=AH4)z<`OnD`KHn;^0jf{Bx
z0GkjC4L1<o;WVPLB-RPe89c*6FJDEp{3c-(9&V52;PoIqjC{5+L_8YuAzHOy<F`Jw
z?m`5sewuOqMEBeG0i(6dA?A~#1n;Iv2s!WR_Z2`C&KY=awi`)=C4jw-Y<Tt&9H>Ct
zNb8BL0B1P1##>NYkt{1w2MzQE)GQ8<+)hG~Qh3mxk<+d`&$A>q6^77Q5b~j!7T}p*
z?X%C8-zo!~^&wYoiOT-I;ES9yld=?55?@o`<il_N+Ls6=T>%+@?w^ilX7gmy{u8?o
zxrMabw(q0n>P&i`y5(>tQI*_O#Cwu5p)mIom#|N_6~{h4UGS43(gxW$&A?4$sMkgt
z8PHoIU_$PDX+&j8TQaaIhI$!VMLR^Z&BfP9K733{nBml@#j=M?fQSw6l+zoxpWW3M
z5{OgA8i|JWz-0f~yD^<(22T#fYT#n&bL4KqYX$yRQmIJUJ7d4!CxbS7B!{92nosEI
z`;nbzO;Wt!4a4Dq;82)o(IVJqWHaSLi9w(zE@2s8{TLPS?$KgjObE;%LM6frM^Ac4
zHOPAS_d+Vd%VJ1PPEIG*a)#U#zwGz7&La#|`)2~uvI%V?#G}cnQTEf(KZ=j`?v~?e
zJKih@OMhxFjP{IpWZM|fog=L={EM{1_7akw8m2TgM=H@va~|`A9|XJ6tdB5+B?YO4
zFzaYQq?xr**J$N*%VifDLL@%b)ofuj6jjy`%a1^nfH&<q`yxI-D1)iZ;rsscGutz0
zg0h2p50nGeZ7d!aqDZq4CCK5xA7tD6G*lzT|CALzy9DfXvm%?k*X1LW_4))X5{MXa
zn59da^Mp7@oC+&BGAA7Ff{Vby3FnIi_hbKIZeTj;<G9|}5n<Nh7;AzNKVx$nn?D*J
zZeFE!hVdp=7bZB*-o=FZg9TxGf51RIFoQ3<U#f12M#>11eOZWH%&daa$L$}*XCKea
zvh~br<gd{qgHIouvB@wqjE&)S8;l#xTcCfCFnp__lxi=gD<-y=EPYt(KEXuEZjOF8
zVuQ<&n|%f$Sm-+yUYu;v<ZMTh%HU&R-s!uA3^z4tH||o843V#)Ln+D7NIGq$Qn@rV
zfcA8DW`hTY5M&d)q}Vt_LX$;!c}{}NueDx2+B<f=*G*DBeyH{N%zKC5ONw2#%~O3A
z`YL2DI=9BaT*+0cqwq`;1HkAnj&248BwUrmt~jzF7PRDVrp%U^jSLIVkYT39ki^=M
z5un;BwMEZ(D6BBMRvEAHvOCcdgz|=kgl#9o7#UlZG3jh4_ajyk-^z%@E8$E@b~`3T
z@gP1aN74=d_!~D#hMQS^<-~QD+~Qv8bA->_KQi1+ejkZ0Cc12fVVGfkM%iSg!pR9B
z49*tuO*lFHnZB)}?2+21&%`4lz!y&_g)AYAdFm0uS<n(?Qv{j1b7aIQA|=98mQPQd
zfqSE;(i&c%W}~r)V_mlRyMAjq`Y7_4Jrmp(%<toSddJF?6n%topBUZo$P=k58P9Uw
z%ZZopVH$YD{u5Om_8dG}0QRrqQGwVhX|AeOoTI8F?7{>>PiGH|UL-GuxUPf6uPgcC
zYJf?cD-CLWM@dCxf_hOySdv@J(m*-WguH?HP>?8&#Yy-<`RgU02`kMo*n0!cdkMDT
zfVU4=yZ>LbB<IaVqLW|)O59(6aX|tQFL1=XJ~4VLKEyBHN1V?~!>786a9yADzg{bY
zV9TJuMQ{lu-cQ7m7YU=J-=jxHQL2Gu2+QmE%Wn<D4-M)L5yx;7(9k_j$1qphzI~XD
z0sRBST83L-Nf<bKHD^Ca2rIiKnB?<#O5ZlnPr~2d^#?Xou`35;z7Rie7Lq1g>j9m8
z9lYu@n7ctNo;`5ii{2}E&%H>ad!^Cz9iujb$EGH#JCXpAU-dbgp*}g%Gb?UD$a?Ea
zK)|m=H*`Q`5xKHL^0CQ%nIXv=GdhBxia-b+6z(D!B}2_t$$mK}hYPea1E>w3o#_X|
zzRMS8!p`HRF=9^#ubz2Q#*F_b#N{uQ3Ncq6+BB=@kOy<5f+2y*(_KV2NXF%tyi7OV
zuVTr25P{GzNI@L3WhQ`5Tj2dPIm6ikq&3A1;!~9f+-t2*v5c&X$E)4+NrYA;Zl2sJ
zMV1^KUW7l$8C-|f&oex;8PvC5n|TGB?2M$mz703ytNssz$X|wmU71^JH$JN|6_eoa
zC!gC^i_*hJkGP-5`hEY|!IfbM8k2|Xj1Uyr3wywL-_d~Pt?J7hbyoN}R%0gz2SEkk
zqr(K=p(r=~8T_;=H(dY3j=#3u4?E4+laoC`-+^LIc}<@o?sNc?hisb$nE?;A#OO`K
zeXuVd`D;cZlGs7-EPFV4V{ZELuG9CYhMOy7J{BBXBCbUuymS9KXBBe>?K=L6VHnFZ
z&kU3B;+DJJ?o-|Xq?{Rev0tPRaA&-|D<_;I#A37Si^Ri08}Tuh_-?ESIB9yb=ruc2
zRHn1_i^tixPBl5wjP#r$_d71LMY*k16eW~-pkOA0L@Dj`;IfRQ{=CD-Rk}Pgu;rV$
zQuv93=(V^j1!Y9svLSSs<C~AawO5Zr#yBKA``v|urB9aLATZ#=wtp{jZR$MXrJxKu
z`D$!!vaXQD!u*zOws;MVj?Ta2`b%9n^8vfi&8<PDL+_CUZi7-GuEbc><erjka0e}B
z$H(zm8ZO%l$^!?LBb#g|MtjEV`z#}VR2=<qQGc%SX}Jp-i@;uJmBa)e_zH(bt3RHL
zJ@tvw2?=TTd!M`eUae!Yqmc8clXMkzc2x{b5jxBpvh-GP0~1|2bCRXZ&MKl+Hq6r4
z&c>rfGyyUKYQzTRQJ8-e#vvw}gu$h`9Hxu40O2G(rl>TuJOkhM_wNd#)^a2gEHs2K
zQx2Ql!C!ngLSP|Bt4aOy3Nav@^LUIrq$7E=7u`lJ1SH<ZUP0C}<fw@KmCUuxI%h;m
z?gBF4Nv2+Q5kXIB1Zb}8GIFJi59WuZ5;*iv`qGv*X@~*G1`2@|7~eJ_I<shGY>sSa
z{;uZ-23Uv#KODdyaQpVYH0N4b7VfBvvrnp1UjL1|kERJS<}bT5_Q2bt9sw>llMic%
zy%A`U?UC{_xH4bJwHvD%C>0MNLQ?JIGaMp*KM*ds+jG7#uo_?o=m6-_Zbnu>xu(zn
zLTzl0h+30Uu9#ui0uWiD14&*B`@tjVRC#}&|JKaRU?EfdVGxyPlKE)A5X+T0(Gh^1
z*<$QJx)c$V+?%GYPy+vB5*)@q%5TkPNEy{jOrYn7%yL|-u3Wg-YirgThj<~bAH!6N
zZr%rJ0v^tk;doFb7hc-CNs@!cMswMFhWbnn{`Lbr^9J!Mv&%vW%rxo&y9;zXD+7EG
zhF2aO2%azRdMZ;~j+#%FANkUkt7u{f9?(_c?akf`1pe328%bAr;>hUU))(ww!MTTA
zyFL<j*RgbexwUNfXK?q5;uWJ3cw(wSV#a?0p!t+|ZQ5*x<>>q66ejNosSa+zYuh2(
z4EA=nbW(8}%)#)$_gQJ=5ik;wB_R{*?98HAx@P*EvwqTQ1=0EPGO&K?`Xk|5HV&|z
zf7ctItW|gD2V*uBoT>l_K^a~gJ~rHq;})D*HbfG#AbCcKjtRi2l8w%u1qdSWh<uq$
z1$^A_nd&t)1`RBw;U{Uci827NU=Mj`Nzp1d$qYaXqIt36!XL5FsKOtZ@wZ>ap!GO@
z7MJ{ynX<s*H;x&%k%KXXB3*uci6rID6NsvdN4#gx4!-E&^6uX`3?(44u?RSj=1vdW
z6yA4eF91^CLbNZ;nTNd=hx=m4Rd|avNvZK5Pza(%8gdf?g`2i(_@l+ymU$9eX_H8)
z)bf*Q@4{<M^cL||ID(Ujo5R5MxHw$j6&%CC&cA)eFE<;fPQSgYV+1|t64}J){P}%P
z^nzXP7CC-uP7bPw{~@?d?@Jz<%4XQDO~)D9W8RK3hzwB6c<tha-dC$j3a2Tw%lYXR
zAt>0@nurq2wFPp6Y$T1A3xoe#4t~~%NN@lTf9z5bJ-{f!%^(Ka3`D^o|ER@s1IHX7
zg?)L;ua!s2h)3BHZ3ZeIdM=HDLpXXP76y^bqvU?*ee2^@c8d0tOU~P;k8!xe&73^5
zHq5AffHxBv0#A%MbUqK*CP}aPDZc1SU<j-QtjHMJDmdh%RtI=s)@Yg$V_a&=wvPvY
zUtent+QYzxtwDHi_=!@^XtK=kmrBEcu%rwEwFUzTS+wT9lBBYQpk%s4rpGsb_>XG1
za(#pIat^6m7p~gpyKzbIi90{5PT8uHJMuEd9tr*zg*JyE%2CcQ$2M9hlhXcCiz8Xo
z2x|suK?DoN6>+G8&O;vGC#K2ZNC63Z8X3V2xztQG@sx=9eMdw@EWVOTbRt-hl<{o&
zchO|;^glW?P{PvO@Ym#uYCj?%QY#Bkpy?DQd+c2#4B5%Rw-3MRVctJ`A7_~3q06cm
zcAO!iSF!LYA0IBNlVio?@epX4K;k$d3BuZge->yEP7@i)79++U=!D^<H*^A-f(-e?
zScJgoVGt+%;C1l%lpTwpGPefM3v)iyl2kkgeL36m-^>uvB)3Z%p|fR3{4aK;!5o}v
z2eDx0nSXK6JlAVC^~2BJ`pn4SXE-n5EQod=$;VjJ<X7~|*|0Zi%%fzzS{>%RgA<r0
z7D`wrUMiW`o$kk|$??--!o30P87>iUO|wK`vsuDw;@*z`E7K$%q%wW*I@zfO`zRT>
zk0QsFNz5@rl3PDH6&cm}C#zRJogyFZoY^!-zwk){0AQc4f#y*Hzc}nYClRpE2t$T0
z{9ZZ1%4!G+*5)o$7dg4|JFy;RmOe8aA6~k9w7CR6M#vRPMv0jhSZC3ZG7<HM4c2IL
zX#@vS#2deb$r5+b4q_@u#6=vWTTpt{Ke=xxIpy!#Kq91lK_Dr$U-4N&oI(OK9wy`D
zcRu#+-&49hXF8wp4iVit!m=LWD2$lYeEywmedNdz(>wdVyXT_OKG6#cCRcg<-jYOp
zog^d)PFxz;R~|>0kj!_26EryGPB+csQXhW%O|NfO?tv2{N}z*^aV*7><h+ZxM2a}J
z4!^Yjr2n{t>Weo`C-!ms|5_~@O>sjKv0S9#_Sb)XJ!-SFXAZPiU4Hh!Xnc0?Ih<);
z^aPe`wPwn{V1JNmKnQ9t!-~lsby$XVm~%vkxv;^&h@j#a+*hKBNb+s4i_31hLu*8d
zQM_`9a_<|JI1}G*wZOnUq%;wKWNXgFhY1lc!rR2@95wqqEAH{DcyB)+l!lTZSS9Nr
zf;_W|5d&F@gF){4^oAXJhrV!z^_RrAcx-ofpYz^3eE&KFl+>;x|B&~pY(xqBT*Y;!
zqHnC=aVVLNFVE4XB?9wZ1Q2kqQ}7cO7!B4tiMe&a>EYAQu?_ixY9KGLHw)G%K%Jlh
z;!7h3K>IT-*-r1AdHhr`bSnDjS@@fuJik4>8j$E`h{W>AyeN@23e-=2@O!lgH1M#b
zncO@IbWxHt@grSWQ3cB&%t*kDiT5KIl2!oozK)6ndLoFO#NmWQ4Sfbg>ECb@LrxMf
zqXOPV{$0$zLoL9i`&(wSC2Wnx!Xn{jw3T&+)Fa>xfO)X}YVge&fb*G;CI|iU`7#uI
zTku6kOxA8`njscM_fY)3E0Nls@sef3Gi)PL!-;RrO}C6N19+JwSx^ZGGt3z}D4OA1
z#+%pWmT3%T47P``oLfaSi;To5W)kQi8q8>-gh{keC9j?_uA-76SmlJ<U&@XJrdu__
z<#M^*THV!*o?O~x#@-SeU&gR&PFTLlf3c@rW%wh*@Pf#LVrJr^X&ZeozO<uoCeE&c
zo5Z#OBxU%;%(>vOdDIC|aeM;-%`o<^hSk8dvVJ({mjj*C&15-<n&qrfq39pqkps35
zt0fZ)TXCJ?S*FKuXJ~C;EL)GX_8IP8ZFq&uAs^>OL?ON<p2xE`1a!1$!bv#K&e%B-
zSbQwa(o0q=+s+y`d(|wIkPKz}vSa3LjGi%eZ&aNR7I#&nfB$9a76Zj%DV9wq6#a!u
z%Y(s2+sqvG!&Zh_pnX}94LPW$3GBg_9Euef)9HxAOlbuFrPX1kR+dkN2L7v0VP`W8
zyuu7CQ*w$-kc_NML;6Kpi-;K+X^7lPXs%oV|K4c_AF<!Vh_+|BF}<v}{g*ALSB@Rn
zA0sCOZtr!!t8|CgYd_;T9)=rCHy$y&kZCoA(Fk1jSPUd^J&&K_F;2$tacIf(XRIiT
z*0GAQM1V9T=w=K&fY^ak=YZ`rW-63L0t%YU0<=y@^esifNHROm4~&m&A9p5Zwj*UC
ziBnKo*%#h?cc-2I86L0wLftZ11u`J%biGq1L-tcw)07F2&lu+a_yuwN(f<`rIL@Hy
zBu2CBR2S`N=P`S$3eBc{S!W24wkxe^Po48^60rtJDG8bf?8x!W0cZcIM40C#-!y_S
z$;7JzWU(jYHJZ~SE^98@8id=kVWuLAiT(4XByMI_nkwgQ-fo#A)gC*_msxw|>aMwd
zv+32VrP<cm-}%|vgx9CF%0)rRPAofMk9MM?B{2B%cxJ0j=aD@40Girh5Kw~sGhF1O
zbB+;5136u^-C*6IVkI_#eREKWmHpU42@X+mNfN}+owVI;d<fxLS=Qn~XYS3$%Z8=0
zMRSW8Ml-swE+3fPrd6)asIG}5VT;nneI`ERK_%CZd+~XD+$^s1_g>Wj?g+-9X?Rpt
zB9-0JUX98WW?5{&9zbSgH!)pH<rv*fuHlXKtJv$y>Nb#TDN}0|-2c-f$ORa&6#RJA
z#P(Ir<N<p^JF8&56_qob#4FaJ`#S6lmR8+2EwBc&TFJ4j9Ag!2JjWsnmBWET3vE5+
z7?zH5MZKUR$PhLG>{tz>RhMWc%XGsksN%fYRQx8&#^Jx&{<~zkWIU@TRT`F=)T)uJ
z+SNo+O&rC0V*{$AwwP5U*;Ih;_@yNDz~3jKpJWouHKDph8%>kOYG=$$!cEo+gtcn(
zdw7*ooL;d3y3P6P|7x?--zY;jS!-jhRG}A14a0!8DsINoP8I59sEtA{+Je`T5Hl5I
zlb9A5NhC55GN2hnD>^ijx|LI7I%n71ag&a?RG@l2b0v<feaJqXEr;)|wy;fhoA#<}
z1?H^je*CvE?49@Y6aFR<0PGLMI$Cj!-Gen3q<c=?)Yqp*QT&bQu$qY5nJ^oFQL`%<
z9JqlmLd#lppTH5TW!&Ky{hN|_btMrHTgS<Y9Wnemuifsf9XG$>?A30q99!5Dx73rP
zz1Azva3gv7fQm*($!!&V%FWuz&K1njGuquA&DooFzWEEw41Ac|#+2L6Mp6z~W<Cf1
zXJa!B)if8dW|9Bls9V&s!)Y5AiK@}ZIPKL@d~*x-8M~3;6zZ<Zk86Nf);B!Q%9d(X
zd){;dd(3QVHRqd^+>RK2Z8P|Z=~-_b!TBv5@e+WvaFkVM<-XlAOJjB}7|7bjZ+nFv
z$Sz~u6a;N2YkOgtv!+6uZPE5TwrBL5&@^02b_9Za83CIV0^Yb8!HZx72o%}2GaXsg
zV8MZx7tLt%mL{g<tX~<8F8%o?i?ecIv7T%J*mfXfUd0J(-c3SInq#j!>Oz;=8iyRK
zZiba@$>~HVO0I4Xt2lvJ+a^B<2?t{sgH>MBl$<rE_m^1<+3<vK%)>{UW?Z&P2Y+`1
z#2hM4SR;FV)^Hej7zLch(k`1-&Z^XR#tY%5rdj7BT{SJ`n&BqgQgWfWTZo<VEnS~-
zSeD5XDwmMhMU!aRh~Y4}07ZKhgudRuf&?4Qc}e{7%N4zEG*~o@nj7w9>({+%lR}`#
zI-xRQzbdvKhCi{Q97lzd`aMqKDoatZ(#Rq#RCU5JDAsVaLj&Tln|s4-GgjF)`%`5U
zeb}JJsA-;aZEMamV<x4!;JonsyYI;@Fu3__o$<|cc3;kN%!JZ&@UGBZFMJCLW<~a3
z&3K2L7^L_<o6jZ%ZbVL2)<y=zP*x055SmWx(D=)c=U!|e4&%@8$tcBe1IxK+U;ErG
z6jPR2;R?HTJ%LnArcOS=0?PzPm0ZlJ>~vz>bYU<#TA!~*lwxR&$Yz<U#z<3%6H~LP
ztg1F;EZ|HI6yd}$PJGhX!-ZM>dcapSg$GpDaJQ+oW0|Y^3D;!UWs;3h>nvkPQVD*|
zeGKa+ols<M#kI_s=t<aMV$?%;=|=c$$^)I89Tm-S*@g|s5Zj9}d%$UF_w9qf9@Or{
zC(2Zv-6e9wh#hLU<pmv?FfIeuQH^Mcw2WmUwW?JlMu(&#3<P%o3ei3IOi{C1Vfu9R
zFk=!Gr*(9h15dW~#>xT=5)K_%Z~gNB&RsMFc`O}THVh&Elr}25o9|rVm~_seUHpbi
zGltAwx+p}cH5M-*vO%|zhD0Nysq$usFduHzm^WCWoX1)!Uj8}_ri~1oY@8;<B3m8r
z7AaO~UhZ~X=*`$^j;m^xn^decbOu_zhaJzz=kkuTKF`gym_p4aP#$fOp4XhFxpK6Z
z?ZcWwUY6uWk#=FD51v@JO-3spsc1c8hBA?*oISBR#4=%xLAMYHEvQwuy2eo_cGFRG
zm>US<9Gjw(FuXK8PXJ6}gd0^<sG1eiSq;rPMK>XWeAY=+ew%XG1EYvBv#J^I<6q5A
z-&5Y)y|JeC@$6-kjmhd_MNO{c8&hrl=uY?MIL=q=D=bjmozFKG>-jy^#f78J>bF<A
z52?Ct?1uSPs_Px))a#*YI5k&0(PZuy;wV`Ovx}jw=BwS#RJ<7G@~&Ian{1art^~%I
zA9n_0-O#pMSIX|zzwR!m!g@LTAX%Md&Bg8Vr`*Q!U;fwcero$vDW;Q^dR3zp<6Pk6
z-EmcS8*G^u5qa2|m8H8M?$zx^^?0<?`8lWX`R>92x2-0%jv5KnlC%|zpqG5J?F*{9
z>a_3at;cb+n%G!J^rTyD?97X+#yq+G)sg&rTqo?m?5e1H%BfRv<vuhK8)M;4Q>m`{
zBGdEvy2Hp;_YorwOIkiWY>!|6mHW>nkKLl(s?w;!O0%Wcrt0BT=WlP^R%UWRnc>>k
z={-|bO{b^oZkTUR$L;+3nybP_uZp8ex0Euhl6J%4!O0$q8);!ZdTL5C=&|?lQ&$!1
zj+&>D%9J|`Il@63b=Pip3Y1b6Hlp55`0SHL<dA;Mzy9Y#wSD(E>)P%CRi7KzT2EDW
zl%3LrM^*SKJvBM#O#NYH{kIOcFY8=;s_w+Kg?xRk(rDNuY@N)jsoguun?ZUeC-Xh}
zU}e%7TviwML|c>m#l)!WHls;LO+}LtP8>YEwxvuUv@>b8Kec;LelVI+s^|Kmd;AaU
zxo_8h(}~}&@(**mL;dB-lgj-4UgglN;QK0`$XAwC@KB>Mn7#05qvyp%^@n<{zS`b2
zODx-J^YWk7AHTNzgId%-!SGb;3c#RZ3W#_7;fgiYTgkTFM=O`+>WA}YQi02=_SD76
zyjgMAC)|ZqeX;=rSZO%L`X5(VBPJlcsy0@g+RKyM6hCb6i#ZUmdV{u4{mV(SrW|mJ
zMfF54qS($l_n4JB3-L3`T2{45np>+(2Igz-X*sPzdk5S-FP~Ho!iE8T9vQgy(no61
zJri9COPaw%QZSCMr?uLc+=Cm&@hN3ZO~N?qb1RjKd7)8vl3IjIy~-zMWm5M5GhcYv
zF<AOe-qhTJyF%?^U2&*P_UTyHC&Q@|lc!bkT4R#Tz;o)F+k5;`^}1GSnq<aon((Y;
zWdXZb49?V~wqfQM#<MRt?3CYG()OEIUNLTVRU3Jg5t2HH4Ohlwp1WPgXm1RsBIIzh
zy=Rh1a**CD!5gd}W!EP2ZJKv{_xhTGej5nL2A`YlDumOXimthgHnZ}wjM2-L^|hG0
zs<aL6uN}vXqx_4miQOSzIjw3BR~YYS^K5p?JhT!S1o>m1ShwRX#KngQCv+&Wk|l!P
zs60xi)#Up4cy+x@7QHfP0r*_43hB`cF~_dtJ#(_c4ObdQo=sIbR)al2Ljbk8eBOk1
zYjcxPwsxH7N+qUt<;KVNsHTQQ>f@7)@ykq%3><%xdE){rmLXSW)ZRqq4V`_$+4K0d
z#&gC!4|M?%vZ_|;eJwH;CfVdd*P-%fmGRn6cBWiSS&armoGrK!_vF_fieGy;Z{#VB
zZKu*e>~U&yb*OrZ_T-_k_C{lp0OOweVQPMsDO_(<ObZ9hbUp)9=S_REo`+U6-J2(6
zx1*aYJ%M+mPz#V<Ah?=z*r-(uV=`N-FayuBhvsE0Kr|}`QA{db7Cq1{)Rt$)+7GkS
zn^AsJg^@;cga!1<NEq>?v%a>-OeM$p>2Z8n8o$pyld4vA*t9u@#Z&89DRuY_$vfxR
zccSc3$EYn=3U3Z<3HR8F<>o?3VVq%H7k3y9<I)w@sF6V371OPu6I9|;ig(dR5-6)}
z8sj<KiIlmD`j>UtZeyn;cQ1SrlA4>$Ub@Kl7hJQlhZ`L7g|X?D3_^mOJJ@xz?Tcu8
z2`U%T{TB)wlXfOCn(Qf7wc(&WTT|{}HfCo!lB7ZaelPQg$5s?)8b$L`IopPtUqYXE
zHin#88tJ2MqOGZjDk|Byeh05(05?<?2iZFW_EJu^kZbh#N(b_L+<y{t+>P~k&Mu&0
zMwfQ3e`-&GwXD_#qER=ZPZF1sEnIA?aH<yt*(4)_S|O(aw9s%y3scp)(YP=1bbkH0
zHc5t5xW{48D~i38O(Lqq<!XMtbz(c3N_b_;ji>dB3ddDkuTl+Ctj&N&>=;vNA!c%<
zZ4}&1VQ-dwp}&0n`oG(&|9tG0;7;ED63+vla9_RmtNO#UN0N`1zN)8ZkF@_m>G?w8
z%GBF!|D)6Km%sJFEkitw@$|;Z+rPn2hThQW^PO1k-+oHUc-u`rKKggEkn*lm_U7cr
zrDX<0dQ;x@X7VqJP!NWB5e)y<tMkR$*GV`hQe_cY@Ne8K3Tu&%o$qz6`x{^W)CUOS
zH!gkS#ov4`t|4K?uP#LATa|h%N-9;?;o$N*T2EB%%{kE`vR~L;N9J*mPf1W!tDaK`
z+HurW5e6dU$OI|2Vm5Sw=wyvoajE1ujzq^RVK=U0Ir}I%98}<$NmJ|IIWvip<Xmr;
zS#Z`T2&~`cDDTB_<woGUXd2$X+W|~_lQr&Um0mzw>;=*XtUzl)`me6<WtG{Sc70CC
zqGKb-0jX>nsBVG<XiE-rbgC|!7C*{a-MNaZa=6klqOL0vFH&sKl`HI5McvOh7Iii2
z8&;yCOuYLa!F5rsV~w=j%%J9oaH>5cv5?OV9RsAWNTusY`|NkfmAq68ji@S-oL$Wp
zLaX4|R_+kSZo?>4A6}uM@m43Ft)V#-x+@=vEx2FRDVbP1<M7SjdY+On1cY4(<A!k?
z!U6w{fWNjV0!fl;(=Z|kgt90NER{EC1|drrF+H|Z+Swa(1Pw({9*;#cKp~4kH4K#S
zuY491qMC6v=$}WSosw=88HA7mJEmdu3-Lu@S&Uz7%jCMC2DvzjMfPwF8@w#a8b@7@
zPs<vl6P!0mRYmopTVn)>uYL1*N?k&_v?e@h)-sKQzr#Zl0d43J9@accKbUjrT%yzV
zbA%BS*I0Dg<^r%-r!pYAFk$AY%+!z*<}IK_NU?zPK_+(Z+PuM7%1>1-x7R@tf`oH%
zkT|0J#YHt$%I5}6v36MNpUB&r;sw$}Br<Yd-Ht5?9Z<&F=0L77nnJAiDuSucIgVOr
zm+Ls;ptNsM%QhAUJ8DPeY@A?4ZX9unGb>3UOTs0MpS(&)G+<C(?%I!@7uw6g*o)Ft
zp%hV)7gA^*zzVXF=>`NAZFwKxg^U5sqmkS!ntRdo0qkT%Tp%?*Et+VeJfpT6|LRf0
zvg>8bW@$n5Ag?)JlupVl&rxGyWgP=}D^$7mqMH;Ud@l|Ir5S3VVb*4q>4~VOHpLR+
z24336ijC<zYwV4~Y-tt%Og6p3!&Qb*rgy9R^dGI~HbknlLxHVgp_p{m=pp0VpQa3e
za!}u)mv5K?bI@oZUew6~YG=Z{+fBVmH2Q?7&4OE{t!@<40?H-REcjB+_|POjLkW#!
zsQ9aS2s4b4hmj<$5zU`(_|9_Cb9vHL)|v!IFbV=$2$W&&P&O}dlaB=t0_D-XO^h0x
z%@h>EVgcUf+5hZ=<KT%Pb_^Wtk_u|>LYM)G0VdDzi7W@rdX$&?@Ji3D$wEdt5Q?WE
zpbi*4c^`qd>u}MDqlAK*x_8tGd#i(hV@a|qrMrf6ZMNUSy0)+e+yDm1%3!^RCXElM
zJ`-j=S^TU#`mT`s>D@*o1XTy8)(zMk|Fl}axS(oIw+Uor#TvLOKbpr)ki<To2};1s
zQZ%d7*y|<Xn;(2K%vI{=!)Omprz0{5RtC68YELh;dlrr?vp80)8;zuZL=XY2FwUZs
z0v&)`)HEy)v_e0jA_rV90c$4y1BpX%?bYxjyUSD9l0XZKX8cb-A9ma5_$Ea;G3#41
z`oK*BTcm4&&N4PKwb`PYUa$+M^MrEuY5QgkaEoMEx3>a!1DY1iE;KShfA}9oDdH6!
zHr3V?1PeFb9M|9v^d?BIJ-VO4WH@C`>9S=a^~vbU)bN}_OPygb5ZVAOWe)glEVC+i
zWO;BB0YcIh43vl`Oud?ZdF=<k5uzJ$rPcs}3AszDF`*bCc?bji5o|V-epPtC^e!|(
zoUJUo=q62%xu8OBW))gh<TD^SwyP;!h#FPcTvSW=WHr3#L?8Tt3>!-$5>kQ7v@`N3
zWyd`8`&{f{lt_gPDq%q>Bxkl}U>cBHvoX%7^MTQ&O`{0kR;!>;Qd|?jfF4WNX?D?U
zUw<Dy7b@y+xNT<Nv^Fv(j5n>7k(X98hY>hi=-8}#<`Ipu2!@lG#tM4`n|MCWI0^oq
zJD1KdA}621bYNG?dB{_nbkW@E6u_HzD!1(ZS~*%*Yd@B2udhHP9L3K1<!@Lm00KGA
zuvj=`gEVxlOazR}sO|~ka6!fSx%$et)FBR(t2?irQ=iwBo$tyw;K%!8tFhSr)m{*n
z9jc-(sNHOnU3$7c=EczMqEoBp$E)<6LrKS0oQQ}~+=%Nd4-a?m?ymJFAZCOfg^6~y
zx%2g*-Q8bV)MMB@RAEzvuotJd8^AY?7p(5Od(SSVatkV7eaKx-J^bS&uq3xw)ozsZ
zvV}mEA$z$O*LOa2*{!#}?DVcU-FhXjRb$rFht-v;1|GWHtFBC~ID7P}gUaH{;)tR`
z)>e(0J65mSy0A|JAslh+I*|SmRrpQ!AL_zJ3@qOsM%piASqkpQ)Z6xK*tj>9{dqvt
z7mrXuk>v06+H>2C!<!OW88~2Y_GBXnF&`zT5&r38JiXHH0#|D+s`&$M!|6gDN6t7D
z$AUXuspFTMZ;L*GDkTDl{E0%LuT+7R?6#A5b#&bnqLK$f71Kgjn%c?E4|hK{qCWH&
zH&q%x>{nHHTA}sS=kld;JfV!BtccU>$(v(SBR}7+&E1m;%NfYh4Ls{t{SVlsN@HK`
zOj(0A&E?H+%^kl|&s9*bB3+-mFpjo)1mg}c2FTQr(re?uN0mlpFq^MedJcTvT}kX6
zq@7`|8?WV;)VK7cV`>hjvVJv);)&Pt*{7F=cMEjXy?$(JZcmO#`4`+eyXKTvao*hW
z7XV=Bvg05rpgy83F67y3!ii^$0HouQyNw`VeFUDY{>ld)XU!*|3aG^4_#<6tub>T+
z^wki2gE)}(qm9~JZPHKxFh?LNcefKY!Kna=l6u1c3|mr^bYW7C->ghl?84OIN$$ix
zu?Kw}!%@<Iul<GpVFP&7Jt{}D+Eb0Z@S+s$3GR8s4$Cz7OkQPbz7g6Pnid%02L|vJ
z$_A&aW;+Lhb^IZ_7NOQx8d?y$2vjUr$=3cb4}t@r159JOvVTrS@sa`{*{RupL~)NI
zV{&|b?T8><^ONS`dhFEZS57L)FN)Ise}AkN{ryiE6-V<u1;I}hK#S4t%GB=er*1Mg
zWMs4gFZ_V-S<wbgI-K}4$Qw9^Xw7Dr1x-UMCDb_!zylsaF;*Sr8swjSrV^Pw(-_8U
z^OIi%uZ%SIP7t?wbo<JB(5!sbL=pl~2`475-SVvQtG{4_<!CqUsKJC-QzsZScZwf;
z4dCKyF0wH$i*Q4F)So4*u*ZC!o{}UL^*MUh81zo6Fg?2%5JZ{-8n`S-<YeA^(IqD}
z9zT3=*mTZ0`HI<7*Xq(dCj)SjM_!Zi0wbE!U^*{1tf|XjchtXfVN*|?v9#<rKmAfV
zVNnfS1)`mknM^P|OdNA+XMob|ObF+fnIy2-Xe0SXj9Ak=PB2-N-w5kXqbDb29v!OV
zbocsPO}Vv79>1x{3fVTmvc_ms7)2zS0&I&wkaV-IgvQ#BR*Y9C@oEBXRa5h_S*Z<Q
zm;imwfcezs(>>IPk3+k8XlvqbFP!)%p5ZZORfvnMpL6X;d@sZYIb`r088w86<6WSy
zjDfB5teQIB1~j&RNr8r&oIy(a7$(OB^URyyiR(a^l_`BvwKo;(uVLYQ4X`s0q?oW|
zS1|Es&)NNCQ2yt&WSdcID7QVHVnW#HkCu)0Lw5K|xoQUenUGUtt9DD%n2Cu}SjZTI
zS%lI(F3tz$DsrcD4$R20s&NJh#<?$R)39;ZqhZB2VhurU?gb^0dB=cIBHL4sdHh5f
zY0?;Xk=Df^noM8o{^z0F(>0YC=!$|bK|Ggm{<+<_G?O#>*M(C)ju<WiWy2oK1lpq&
ziRT#a;Ro$?HXyxeh}%KZD1oph`XgBzE&3w1KQ?7l2<46;gEUIK2NBxrf{XFxX5{8o
zZRLWazZvei*N6r20UD!vYypNtN0mWG(@i~Snyj-5AdZp5AIS>ar~Rvp0l=I5P?&oH
z$P?EMMj=$Ox6;N;z^8734de;7fO7yr-T0$8qu2;yj0yK8rr5fVaAUG!tODB2stxZu
zm@T~e-mmJbtph0rG}B5Up>6kGsRD%D;@k@cbZ7<)=t%oRrBgscpZcFKoU#j7?*A%J
zo9BNF;*)|WJYQ{H??6B^tqvyicd!sJpcL6E@9Ol1_Ya<VS1N0XX0&$2H(qp}c?)<V
zLZ`TtpgAM_a7oUTpL*bvBC{)+o4ky9{o6k-{#Bu(H~no_TGmg0p?~@fuOZg-x|V;S
znM;zm-&7t6YLWVo^&Ai3oUJa;*5^qT5sG_Ot01;xO!li=T|8C{+;xCjuzx4vxHE<5
zZbjxf2l~jVW?kFO6#-+Tqj}2gMP+d2%wBVL1$h(^IcMv5(OCH2K4ko<Y9OEs9tHIj
z-e7MHPy)HAS=R!Qs6Fa4BGxfOg+jeI7U@)A8gc6xb?k)x)n%ygphu-Cwon*n&Co;!
z1`!9ekk-8ZgPR!iis`U%!?$9rnmK1LLMuSAffEEGJ(5x)%|nvPQk4c_TBa(6mYo0t
zH${CgT$HsrlVh{9XfALX?6%lZvW&ni;x|4Y%xN@*68~d=6P;l$Xfvt|#fF(6w3P`A
z!xwZ3P1&<<qQ6Gpf=%%sGnr$&3iwHOs{-Y)U2<X==R~RDVipV+2QND^#>}1KwUsIt
zxM&$4dgkvL=WI({LS(z;bJ9Jr?OLWsN6OSkBcvGXqo@r*SjK;p-eKkeyvCIV6@kJG
zTT>=UIK;{iyhW8M?S<>puV46;cLg|S(r~;$Q!TybhvGb#@to6To>GTJ&#T#Viu>Z`
z0?F`{uk4wa0#VU%M@ZB~g~JWzh=el?O!`9EF5Y)KyH^)78ZH@)n`1hldfXbaTJCuI
z-~SB0B(d@0Fp5xQjY4^_ZrmECTKSx6XCM)Dq$T=lBteKjR$Ffer_4HTG;0duja{dW
z4@rY4A)ORgRJhRVF6zSiZm<+wbq2j*d?i+NVyrNyn&Bl;X!=7Ni-H|yUwCvK6`%$g
zUzA}%YmPc=5A|9cfzk_)7Fw;)EhDHy?gGP*86nA|e9qX?)i6q3Y;cZYSp#;ZKXv)$
zD-XTf(0gNC_xNSaU3L;tQ$tD9STD)sp#^5ZPhuV3#0$tc)me>jzlX#D$<t2MSM;T<
z-i@A13uuWHPahzuO>hzMQlQ4j`0wwK&)o_1$b`Cu8Vx)j<nD9@2vORMgoEzLk*D%G
zE&^_MM~5~R4Imd;EP-IFXng{ffUtr?$*of2wa<RiQgzT7nwBUwc629zK^7d~ZQjNU
z0y9<W&O-YFg^pcwjw;u%Mp$oU6IZf7j#-<O*EAKXu7Nv17waq?un4CpJ|FjVHcGuZ
za9ESUE@!U2@`zJ}r*^Kjl@l2Ki0~LlsoV$}JR=+#HM<*FR}1Tn41@DOm^9p!vW5Wy
zA)Q!ozzp#*V?LNWsW83M!1>I)>suK(M9wO2OzTPk3oqmbFRht10ZTGKAq|(>vuc(G
zY;^z;oSmZMt}YhUdfZLK-LlK%EKhTc+L;^|M>gp)9YUp~izXo)@Wg9<r<t#^xnz}1
zVI_bv${0ph2jb~$9%;*EvW>!AY$l;Mtq+^An4EA9f#jpCy~o2nl%HgUdoo!@xKFdr
z>2efCyiKp*FZcfpxS04liE~CSR&nQx&R}}HiD1!e0Td0;79^aZ1U6jBVZF*0z}97H
z2=_KL<4U9~kUa}SdS|c*aJ#W($%ixExo5Z&kTWfx8J2ftRuunJ_=nC|dV=cvht*Nl
z1nqN;Wtm3cHm1t*JZ-vl$F}zI1G{K~CNoQLW&vP$Tcp;l(i-OQ^;em&9NU$!N0}(O
zu=ffLYFnx^VtKhyz{5r08qm02SrLeYMTHj@WDaS_RxG_re-2k$d&PU(*nEg(Lnl0j
z9H~uSrnPZzAcVox#K{Uqk6he`L)NhEx(~&}&Q=vI9L+nk${BTf*-vN@ByY)RLH$B{
z$OTLiTY<pkj3ad6I^X*rvyQbf)T-J|qx+{^n1WC^LqYevw2xsXRuwQnE2<Y{FABBU
zpL6idLaK8Pn+Bjs9uc__0!K){?3DV_zDY0Hj@UfW1@Sq*_NQgXSc+>d81O`o_&+5J
z+wclx2n4(hkPj?)vW(=I9hE1&8X(N8_2bBwTK(ceefKR3$4Au9O~adR*1Nm&tNDcs
z2f7#4ccFgmJf`Y<7V<k(y^w!R59ggOjWJ3Rplo%>;X?L;kTc?eKMHWgX$@o(U`6F5
z1V`I==>;)d@%mTZTdYou#&G(ca@R&-m+nTyWVTz7V%o{{viT#UM@}7u0L#kcghPf^
zj!GNO7e0m&G=I=Jp!O@0y40)5j@a%#z%lLPW^cV(-=PYNPS*hkU9-|3dkfAOGdIo}
zqm^uBW4stwjAC(G@8rKX%*kV(@Z`V@vty<mT${YFS?$6Hh`%XYB?#z%HLT+s|5dIZ
z@5(NDkJ8^pLvDAkPulO1_*Wcy4k50S^5HQ=`9mueynk@V#WiZ`;+mUK>e_>QPmfmd
z8?Z8Q>S@v{Vm%TDI1#|ON8{qbLk!9}tqr$;(=ck*^<SShzS@rtIozkNoT;n4a=r59
zxrzI>g$K1>C<mUgqjc$^T&>G9Jg|b{KGV&sb?UYm!C$(&$_J~}g>v$PpMBx;_0}E9
zwO;q0dY4`MmU9Sz4hwYtI(zTr#{{jZ)F<s=M`QA9_Gwj_oP1%?9M8!iPg_w8>#GuL
ziXz`rulVRV(d*s;;;wG5_uy<{kLAX}b3dcTxNWoDKVpBy&(((e30KUsi^ccgIgf)(
zmnZHFVb{7^*FC1yB|=bs9h}~HYy*B4$R=|Yv-Uaf^;p@N3wxd!HXfT)81OaD46%8^
z0So~VsX3L?xKyC`+m71m=#y%PHl85X2bhEQp&{0yqHaXEm%?&-E=MK;W+e-Jb?rl&
zjr>D4h>P7-o#=uIc**g)?SVps03v?g3<4!%7(Ub$PO#HWL|%L9&jKT<hxU8cJ?-g-
z)U{qaV32PXR0LNMJ&E(vsyG{oad9$F%QS8@;6Pe-e0U0j*25~SfXC3fJbTGW<m_fW
zYQEvA%=<pNu~=1ZwT=V|Y(#^C{5n|ogpK6VMSC2>1CpaDKJwzk+-r{vOX0zjd2@45
zVC-Y~`YZK0jT$+5TqP^g5+!atJ&>s#nq#;K*#@)5z!<{ki)NE;xkw`-gIVRdN3Z+)
zvG~_ut(ZDf6X&VGYr`N@mm6k{%5e_L0M!71^A4wqsV}3CcjwLJ%DZc4LNJvc1ZU8g
z9B5tz)VTIC?jukW$O7m>y?zppke=&!17>ZZCvj7PG4a^M=_GAK1Fl+RMUpRvg<xO(
zqbwBzRneM$kWxEy-1LN%d4_^?>Rm8UR--X&R5sL3SeZ8Fk!OdAKUV!q>cW&7ZfXFZ
z{VS8EA*2IZA`n_5pJjST>uv%Xu?S^i41946;3C85(OH~dVDRi3U|NP91m3NuH&SQZ
zp7QR&j_J`uBYbFBC?@C!=9ut+9{Y@CAT>mnd)5KFOw3()#Aj=nc)Z^X?kO`i6L&La
z;9Shxg@)<^xPyixhDDOP<?$SI92!%s;~OPpBC`c3B2SPDLn4?6^y_-p&ipvU<+)vj
z)x@|1J0+vv&Zxm`Xs^3;&|Oy>k-aU<xWGV}+Q?w$_!LOc!gk}a!mM}spvz}+1I336
zDuG5atY#CS0>@!?c|2p70awPu=~>5K#y7^fgdy5Y5VKeJuf1|0tg@V`0jpfN;2TWG
z9XcI_SEh-XQJI8E@?7+r;K@=gKwADKZQQe=c=^LsbBoS|k5t)a$q<#8x-rU5ZoOIt
zSi%1W&H7v~ERPdX!CGv-We8kb-yx=M^IRe#`>JNgyY{(%y?4$5<WckDW+u)=!l)O@
zG!sY#budTsZ}{ebmI1`z)a~K}v{wrR&M)zj5zHlWx~F3>m$n0vzA$DqngY78`MQPP
zEET#)%zVx041!C!_BdEjb2>)eDPO<k!~Y+7+?@G4;kNU)c-;KNEp{YFCgyKksJ&Qw
z4|}nvN-+zL{hoV-)EMGafJz^E--Ka8m1w<9?n|$5=~yazt-bwEKJn8Vm&mVDgNRP)
zCBmXyf2lUjA%dt(jJBL}1z{Cc1bYl>5Ck>V^0>>x)1jYWzMQcIA~F!q2u3stn<O^L
zFuG0m5-A`cP-(E}rEK98W)~4c+{oqA=@{vdI&I|AqN%=fir=A_<WPx)=cH1o0GsSU
z{6nJTi-ZQ_J755G1fpV&sYra7aEswVq)kdTql8{c&)_NyCB=5LB5)Ie6<pgE1vrg_
zeHtjhAmqw~aU!8-68J4h2O(HA3C+yPA$;YGqUR}JI-N1bIzvYVbS}lckl5iJ&0*9|
z%<Xoe%}g<cu?fTEm+%hT_}3SWuq(GrSs_3<#bAylP8`9xoRMxVS()inrywp|uogjO
zGcpsb^KA|tK^uup)E>jyr*$)C8{?xW-AN6tX#!XdnlgR=%C2|uI|o%K1GdDt#4-rH
zWdwqbCc%412r-~ZfvLhF%v}aIor?5ps}-9xOmZx9Q+j8gY2W(WKWnI^RC!}}$;8V-
zqn_b;3n+RSFU%~Zz>Q7;fgmVkwwSI5o|5roS}@OUbEp$6MI&GGkw7Ta?GjFlpzKA6
z@~Dm+Kbba;+ghf*Ym>&Gq!xS20j5Dkqwp-DgR%4|F={Ou?x4vrjsczWis`Q*G1FS#
ztS4|TwhSlABXF}?>}anB<Pbp|2T9ar&Rj%QiAA8#qL1TF!-s}@>8+nNRw03nF}+G_
zO@~DuLX^K)#)<(gngLHms+9i86*?ZchAc&)>hz-s%p?^v_&`)UEBlpyD!0U`suhZq
zFB%kAr&QKrkiKeCE}s@iwLwpa<H(AIo3I^pN-jH!<Pm&7YBEcjcF247=xZPP9l4i)
z$_@{a*@qUW2WsZJp?-JTm#%DS7T>T|r5TJ7Z<;a49nYNkNWH1cK@*hZOT#G!Ld2Dp
zg+sU-K>~ym#L8M{c-)`xm%fl^c0P~Ynk#KyS_`E}2jKzoxlo@}$;AP`p65N?-mrJh
zko6sI#JW<3#Ef7$2#n>lWDr2u3)-CgLe`+LM_Fc!1x!YkL#n(>x&Oh%!XaNTQx%%G
zerMfcxRC&^)X^j~+v!@|28<)}cc*ChF)NkJ<0ER|0+A5%q3s6UNuN7)$Z}#0ro%@=
zp8iviX&M`|1YNhsB@R#K+e_UrWc(>=t?UkqlLCbYM*<d67m9OQBW0z}kR}t94&yD)
zi{~9zl2T2~((8-_tz0WVEfX3^e=4`$;O{ymROE_xE`f+7tjM*_ekqd{3$NuFO?bgc
zAj@<t(EI|n`05SZ@SU<5Qigr49@;4EWUcft%g4f(n3PN~!o~scX=#LF2+l&yMRHE~
zC~ZpOt+gl}7MV*f!4SA~I;y;g<V~k^E%e%X*)#{^>)Zd^B7+de^qjwUuCzk|ok>68
zg)~R58_!h0OB&uG|IX((zH}ZO*d!#P%ckQkGik_|W(-=rjm;vLg4XF&rfggYK1f%5
zr_oYo(_AY`_J|wf#2oN4y)%5X`XlElb1`X~klwC`k0ncSyFS{kmz;Rfu^v9_oL=V$
zhf84NLiJ&Jsw6W(RZVpsPbL>e?NJ_E4(1HWbp|NMxY#Zj1MnGcm(<L5#jLP2_}sO}
zK<tTzSN4Sczr>;1Nra!bn6Ew@Gk^;Vr|V0Lc~H|AmACk!a}PnA9-oI*BA3`e;<eh1
zy`E4Flq8i=D)3xUaZtQq{M1HB2|Bz9WfY`2d;;rZ9)(*;V+t)K=T8)x06`LBl>Tv`
zF!4hC)#grj;S+KTe;7b8PC($CzR{s_5jq3-9sgM)Km<mF@+M#bqhf)`L&{mfAJa?j
zrnYSQgSy{!{pbHBUJi<MfFD-vx%%D2|9B|w$ER$sJ=8#J_}ar=Ps~r;eMh@i3cQ#N
zyE<Z%kxXZ5g9GK5>;yp>YpyZ25#``05F(vp48*UaRLO=uy1(Yz+&DQnq8D5<0U2N|
zbBEu%G;Fw=?J;Mu4Cj6U2YOBzGKsZL2yw8D_kH!<62CAt=L{Re!%59Y@%PZQQ7CJt
z(5wIgq(#gH2Y>lSdspg#LMLef#8i~-r`j}I5Tw@w>CvEUr~Z?`(Y8?u2n)jAPU37v
zOH8%=wm<V|B8A>lp9_>Ibv~7P`E~87So}7=MAhOGavB!|BcM&~9vg+mGx)!Di7IxZ
zax`aL2AZP1(g0D{M0-oCC*Xnlsak>P$YSPK_Ga6=wt3uW5koO%qUA$g?dn6Gu^@HR
z?b;WO__T1#3EzuBZN*4r(~`BTQ*jy%Bq}|sE9$E#hJ0ViHq9oQCK@e73HBy{WHY8w
zBi^kKtw**6hXJG6mNyM+>OP!iaFvPCPrr5xvJJgMzmDPkIR;(&>J?3|X?h(@y(sZ8
z)DcPNcyVI{WICFNXRvVza1=fDb<ezZVt|Mko#H<DhK}XH5(pOLfsu_p<7?fSAfS{0
z83vI$wXeZU&e7rwqnI)j**KX_>7&3D%wDHjX$e!ykfyWRV@el$SY3<%9nnODyWw$1
zoR$!eDD3OPjiGdo8I=`<ZeA772xeW>X2=00nb+^kE}=;R0Mw$UX&A*N68Fj&1Jp3g
zD8P&_VM$9$(*U=UPOO%}IH_=jcym=Wa|1Vz5lVl?C$J5wb}{8=jF07vv;i!lw!k?3
zv-oL<CxkdiyfTxs8Hj`)LZPB=5;?>C;RcaQCm7uuyh7SwhfBjy*0Ks;-OdAzN!9k(
zWe^AgoB3}<?h)-DJ0N}z%JZx%ctP|z#vM<wTQUS~*KU~}!SM@z99SgNrdH8vf2w+I
zSS(tqcTvhy0?VDm%}KT=rzCPX8aq#D<jAuL1aR&D_$3r_m4s;2=+>z#hgl;kr&cnO
zI|weo`GV~`hx>vQL5&?)fkEEOC-mASjg5T%5vKecw`OT6HAa7RJBAiiDfVaFD9V?=
zvhi>6aQNJsbHe939u6P<Xvf3h?EasMcKOhJ$Hn0-UHVUlyPWyz|6egP53L2>+?NL4
zEPi}2ZOQR}Fqpys|Mqwqz4O0yqIVuzi{2?e(g}At{Z6>cE8qIr7UHlFReH%dBjR;-
zm3N-kzWnK@&Wd+ovCVYbkw+FodWF|N@*6*Wue?r0+`s<e-|`+3`|H=o|H-;JbZ0LW
z=|sYX`=BEtMoKedFJLufP)S(0tO+zlXwBoB1kQlrDOCtljgI$XF`=F4Qv8P%n$*W$
z$i{#D*s!Pr#sX|#F8FE)kRwtl`g~eP@{WlZ(oCyJg=va~I4L!~gvW`*m)0muiX1$q
zd+oh9GX}2RQ8&`z_Bvvcw3$m9EKLv6SKL6wi4;%iJjyfcD3Vw5zDUE7pJ=^d+@*PJ
zHFL($+O!o(c=#W`)`q0>)Op;VEmBL>DD%(C@<?dABYyYW-}+&}=;0jk==QPqxV`op
zt!Z!j907Hs6MIJ=^vb!NPad0aOMgCYjBm8>Qm<aTDJ-e@VpJ&|yZg3QP@Z!O-@db~
zALL;9ORa5ZDhs7SCp&&vohYAaKk3Bv_?b7#7pv}3`)1N<#Typ~emQ#G{ce=u=6R>|
z#l*WzV*D$1QVrgSXLQ$9ZZ`T>Y(M`aXV)Ki7yJht=c#y|{-vqbg;np1iQ@J{@wue$
zs<&^pd@i|b*1YSfchRKjU3XNCTU>w3{$zZkv&GLo=*H#T;I^bqi`Jh@;%l}Zm$tuA
zzS7DbRkY^fVz}a$uO(_8?l)HbFLa-}UGKRm+^=4jdOtLS|Mq{Ti%d(D)L9}T$;1X?
zjF2&8Rx8QM5zXkvCCVHW21#xZYKEBQ|Jt_^QAAM~Kz;IEU^MZu3Ez6}*V3<RxQ_4w
zohU7vm!5o{E=_sCyUx-_Oj#pOsabbaJ)PbiX5bzXYCO2l3qPU`;H=I<z_kava#{Q&
z_!PfDiU@9$BNcmED&bZ7%!+2&^@-XqUkWa?1uL?66gbEXeCmKVhi~<qrLl>}1DKL*
z@F**+%s^TIvcYx;-WADc?KGvJ^x_>GHYu6-fb=uPVX6v{Ad4u_aGWA8AtYcc6p*$(
z!Gz^U*S`GEI>Vg)I9>4R@KB))M%rk(PcGuUcm!FI*C_(VK#4G#vXjU&_F0*I@{a48
zvx}Q<YNu_ZM7n`eKqd0h6W^ZL!Y2tsTc>*Yf=lYAk!UDQ+6%{$2@N;UdH{4@yHN*W
zyY_qkkK8VWb)JRm3VEdO_aP7%{D!Y?lrA;PcUl-ydehnsd@dh#2IJ?YRA~bjzo3Qk
zD&a58Nc071b0S!@KnsHF$e)%w(pso*FgA}Cnp!5HzlE1M3YD;3H>fa+<?Vb-{<+}|
zMU*hN%KnhlP|x@WvSU>zcrEKe-te9Hlf|HJ;$x7u95R(5NH0Vqc7?4t&J;Z}Z9RJg
z5^N%IGWbGyiWDz~UC?ihe{XHr*=;iXNxCi`zywIMC99xTCCyK#)Kpccuh~cp_kbom
z5VGmm5|FXY@oYZdc{!*D0dYy3xPmGN{p}0rC?atB&v^Q~9Tt&p6K$4Mtrf6VQfPTe
zAP~+;m#9W7JvfC4p-)<_zqbEMm+3924`=n#MVig5+J-minb!Buqzg{&;jR=_5_mBr
zB`vc>{vRd_YUTHon~`qua&4K*FEZ%i8CimCp&1)~-658=ymXYWedDZzDN0#!LZd-a
zSn~Xr@ECcWR%1oGD3&Xof1cq#1lfcUJSsZpc*Pi&gzG?5D~H+e)v}N?^F(Fd&X_$H
zBu#waT=&|inR+P)(IEw$(sw*ik<f%tne4r57yaRqF3B1ZRas<OKA<p&0b{LvFW2|H
zjjhfrI-8`g5|4UVi>N_T__R?ActRhS8DKJi9%wy9$Wz)Ss|+zk9^Y|eL_ri#&K$+P
zFCb08ca}D=8g^xXl3`G3KV)T7o3Kb87)1HuU%xbcTDu@zm>wLBlEZRf25`yH$5Rp5
z=!vOKPh}YJfSCwyioG^k9(acQJ6*22q~@)bGyV9kO_f5<I;d89#)&lE)Q|5Mz)C+$
z2guzK5{o+jnVyLLF;Ck$OwlFT-oEMRV;<-C?3*rp6Zek~1p5k)dwabt@v!}b&4dLU
z2wypGAGP~m3G_jyWd>uQ`jzV|{prjDaASKwUrA^aB;v&qyhzF?Nyph)<3#VcdlJ15
zzeJ;AGa3;cMFAnaSlW_}0>ZV($^<yFMF%VRqPS6^{FL6%pZS<K?QuR#(Tf*=fYhRW
zn^zlPV7)QZ^Tvk3jsNoZZ<_PyJ8KQ`aP9xpkdd6uh`89FM&>}kI9SUc@}>OGtUbT;
z!P*NDndUUsifLWR;IutpM31#Rvw!W6B!d2b_-CrS{-;g2XPxQyu^L$JeSSX<9fE-j
zWl6O1Y43?-;?s8|asWaVG{DOBk#4RZ?CIABK42f7c)7A6*bcT5a2DVbN%?$&R+x=z
z3FK&BigdQ72co##c-#wiL`TcD#~;g%?L43K)c5Us!JYP&jonV=Ui)03|E!Ju`QX6z
zC2t==ESqg&dZLMe>7Ex8eLi`@v9k+3+Vw%Q-uF#d-dup@D3D3j#mLQZrF_;R`rwo>
zsDKd*GwrDon8x2DweSagaeN5&@fV~UqNt9HmUw9tWXWVI*)4V7*j?CnQUw9-5CAUG
zW03Jy+pX9eP`h=HrZK=sp7(;IHt^18i+u3IvOG{>ZF{N|gi~jNG-LVco8TvL8`KcP
zG%s$lruJ8|VWE&g0-4y(4liQ_P(mYEvRK#m(Gn*c)S|tf=h<NKJqMhIpT-Q;2KwUq
zzW!7HZ+mA0B*#(R@!8e*EZecXyIP&kHpVxrS#bi4I3q(Ss4z2{Ju3#H)ggom2;$70
zsQ`|^ahVEK%6DQV1QoCyzLFw*6o@26LJWiy5R%xqjH?J$AihHQiVX<~#YcIiD1?uq
zoZr8DW_Ryy_wIHzG7{Rpy`7o<c>VhI>(}qS>FzC-YNfy6iyu1)_eLDx_}=0xc1Om;
zb9t`$^4pz*{7yxl^`2m1|BtW<ml@CS5PnQvbkS@3cH(JZs|{7xqdB)uB`(7oUWT0@
zPHhjaf;hw<vBk@Ico^o&mG6WQ$DbR`hn&(kJGZ?wHd|#KNemTks2(joo&_?Bz)8W1
z<hwtz&Zlc|dm#6YN<zcZ7ve-abh&=d3BVjUSptE5f2{vnIUmMOh*}6ykS3@TpaOCB
zOd<N687)}xN;Ov$alQI%wVaP<IB|0-U#h{4bPel=XD;``{EI#De4)b3`T3s(d3u7D
z2Bm0>!{i(fwrCu}vE(@ogd7SU6WWErz8|sK?a?E&-VY_~c*&qIM-H^w2rLY1G`_>q
z7-$}of%?^VA1&eI^R$B`45HEZ6<Ol&zT&frc|2hG5+0&mFWVrO-BJ8oxX-Mg1<815
z`mda$&}D&d5Gd@MP=_3au!ml>g&EJSZ<%r6Ys8D#0oD+gOyPRNJ2O3{Z7!9Zs(Lna
zw@$99Z{dxl=`Pq}ES&Qh+}`EIJ+t#HZ<+N<EVyYt`b~k@aZJ=;83u=Bb8|-|Df4fU
z5jOav3I{`IwRdzPm_}Y)%_gE79RKPD6E5=?<|aMEMwYVi6M4=kexfmd4(aluh{<QZ
zxChGIIw23FQ~S!4JIZpCM(*mvw!3yM?2ff8Dt_?b24<4HC!dhNePZD#Y_QcuIo8G)
zR84r`V3;=!A#&lFfjN&wNJSyx%!lylp?q8&!6)R*%s5v!JZ5MwxPGKGIyEv@18^<+
z`%*rRH|JQYp;u=B9*bw@L%qnl?lAAR=zBar4Hjx3`2RG5P1*aB5P{vPN@Md2t2mGj
zZ=It5@kr4f_i1vS&+(o5hFG1^nAfYzQC>Ka!dC7HUbmF)h*%|;A1l2A7m@Fb?nBn*
zntOgZ;QEZzNAzpI4d$+gM-IaD9if5r=y>ew_EXR7mR(xU;vffd8mt1C+M{W#t_ME2
z;~*+M+b<9haHn`Rf<J=`1ra?7zMXC$w|%Q7#f3P|$3Yw+t|Bj(ilS&lYQ}g@&}t~}
z<(OHAA;kb!h3w_X1v#hiy?<rDIP(ecky}(FeVHS*sRk(;u{C6Rr|Khtpvnmh4%871
zO%zBzv!ui&cR@OdNsd|84Ey7@j^FbEAg%X&CP!OZD!wl$%<86QkDT?02uj24rV;)u
z=KM9W@{yX@BBO51fK()7o@$ZWl@Jxsb?*8H#7!wDRS?2}WRWl5lA2*Hvlog{fLA&K
zXG0w1nHz<&fa&cBG3ZGw+lo1+8xsmeEAPcVIjHj)QyW;R#+~rjf_mLSLoOmvLYq)o
zMQDZC_KtlJV*0o$=2{w%Qq5oWNhQ#~KH4k``hpzLEv4ytp<GoPM0au|z(g*jq@lRs
zpn3&fAagC+!}-q92#R@FW2JLGHpKM{Kl#V+l?(Z|k}DtNSXZfC2ej9(m#Eg%hfm(C
z=KYx7rHwHZ^B@BVQx*EYH;aAehTs-DUbwl49ke-D%cJ~HM?SP=1+rEdyXvlLIfenf
zaNCnE^1)bWd-_rf%@faDX%?_CeR#xRAZH9Fa9+|(PFb<-B^Rwj2iJ38Qp4MRzJd43
z0;sqsM_$`0+^9h^O-NLUP#+!*U72BB1SNHCg#dSyXc`Ujf(pBN(bEMDc%T$EpY;qo
zI9Q>}M*&_kR|87j5hsu4LWjiELL?B=1fi=D!SDbdc$^0K54`R?XFE5O8ePg^5KY_d
zRAEb@H4_6zolGg!6nd&t`N`^mifq;xW=|^PivHmEyB@mml?TZfawu+&y(vW!Sglgr
zUS?lL63B>T05F6x+)iJJYwA8Ki6S^9H59w3vOt4FjwBL&CP~op;72U-6JNg(Q_i%2
zjA1T;p2ldfCPWG%nJr*Q%X~V48h8}Ck^pc6gV+r{CuEFMoU@9lCph`)$Fm-|gu<uM
zW<H#xLDQ&|f(iNt6sQ^0sjyI{1BE5E6KDXsEf4n5G>Sw<mh+yy7a=Ne$bmWV%)2&H
zl7Qg_R6`+JDfUN3nL%Odwz&*Y@`Q$+O;4)F;OJ*O=OP13P=lOT1Z&E*!K*xEA%bWi
z>p6rp(4d`*B#oQE(3ml9dfR{CY3CEaZqg9iLTq&{nX#`0%mfh~E&^@zZSXXqP=<i@
zEogK!Pn`rY;0PI-UK5{|-{uqqsx6Zu4nP%1LD8G`fr|;I!orA{%c3o0f{(p$9lM;o
zY8XZlTuHBLvz1ds;4xwY+dNnTeizG|IPpP?yHZAiPf$=%(qKY^Qku*24t(aijjVR?
z$gzWcTChop(+-Ql#;_Qb!gbVQ>%l1%hqHAb`#ub3Y7uTxW9rZH2=h#_>m)*a?uj_;
z1GWtnj|kL<9w;!~aXd*RL?Vr9&?rn-{CEa2H*)DuU;LXvH0^EQ?iZ_Jj)NK4G(k%X
z;kt6L4qmSqA_1P|zMw&83xQw{2EG1BkRO8W4>NTk0SjVRlTSqAGgH3-Yoc5p-CL>i
z7c!1uQDlGYBcgF^?Dc<naDLx4MW?zkSLe(^?Z;|;TJ;04^<g&07#mq)-gDH6!4y@y
zg5r-=50YFk)$;o2vEmfx@>d-^-{15C?HSmd8)LKXB<n1S*A}CjwLgP>8Bc6XqS-U!
zH<)Z?Q{<m}t8bTB$U>KyeBFfqto5}imlLJx{@j+_<9FZa?0#ufU6_um<>+R1T5NS^
zYVMA)FGcHV{m$wCbY^Et$Nb&AZod_;z=S_nj#!hiHHJ5?o2ZhlK3mv1HI^^VY(D<g
zYn^Mqym7sMEe6RX%N%^KAc5jkSx8Uc876XkIBph04HF0|>VtSh4$mOzJZA=@$K$`|
z(kU*vlyM5JX#{-PS%0HPIVHnlSc$BEcS1(g^o`zaS6=LIud*0^x`fQ9Zctc<X!d#F
z1~jz(fPpXYwu-{uDex*_kZPv@h96#^{A?{>=U>&_fMx*w%Xw^P;W#^oJ&aN3*G7qg
z3CvLlJdV&q;1YYc{m%LqPfUWDqs;@f)Th>Hnw9x>M1TPwyXHc5R;e4x%t#E!G!`Qi
zhje|G8I1b3n2|^Q^&26AScka*JAD*WRlq$*2}r8ir6)dqOE5i2&6}&*^1{B^=jaqo
z_EfNSfUO;gT;m-Lbif&4enEtqk)TRLIzl0+%CE($pBQL)q!k?%WAjf>VKxUk>w%7)
zW$e)jqbIKT7U!9k;6|s;T3wJSdI8Iot2tAeY6u8Oc{^OE>KYuNEV2==j7LAHzY&Zv
zHN*R}LJ`ZK{-hSV15BU@iZ$*D(x*QBgY&81=L}UH!a}A^&#ADf0R&*RYuAbB^g4)$
z$kS6E5;qSO{n<I!NAZ9~5X_co=qy}EP@BO%JENA>Z-gsMPt(oSQM#F|v6xLTd3^+-
zsM4>wH*RQv&F1+W6XW)+`7+GTSqfU>arNsbg;v8LVRlC-gAX*>&i>3yaPMI_s+2!U
z%c`uAAmiLyDu#F7I>iVGFu%powMRpM5UZC7KzpE|5$1Fr!x-At8}PBa>kAti9$gI-
zda-(EMQp@c4=e(fVF0*6es2tk60#7a00~K)HC8ta(@<;52gB)Er~c%Lq^K5Yz#8|3
zUQi|tT46AYWZ(v+NMtBtaL+#Y_=_7=dYbJINWN<(B=p$W!2Hfa3_2h2Bl9OV2T`bW
z!M&#;d3GPHC)+xR7bIv|ff9_m=I{($S(0_aR{#-zcQ7!_!5TBXY=dpz^Nn>~)?-|8
z79JLn$=Me@PMk1<E`u-o2G|0c&zb8o3wl{Z_j;vNefTw(Y+cW*#UeHf3MMg#nEEs<
zDwV8WkyaXFP~~G%P{s4OH<89}%y5Q#B#B@h=1oST8>$dWpsF*vku0PtVkKAj-)o-&
z8<O<KP|4D#Ob)K9G6r(Y6_Jcw2QJn%3YroHPJm5*lSjE+l_HD*Dt_pPIZ!JZ-7;9G
z6rFOQdQ^OrCIopS#6koHl_|$~P6!LI6vG6Y05zoG21a#O;mx@jGK9@{-DEYuKrqpf
znKT%heu6`CF-gn5Ld*yT3F?zglG`BB=$f}Y9}Unn5RAbW@F^^FHP{lBR11I@M0qh|
zMzMjXEQpMlYPgf`NdD&SKS%ruFeOEYASaCJKY}s04EWCalwxf++6(<LNc2tM_&*sX
z^p7l5b{c=0t=D=6FvhbWc^n*2kflx(b*M&Dfyys{f(@2Sk_Tqhh#JedmN^?BM$u3a
zm1;ia?cxssNdh3-n5U6R6+F^mE};BeJ1NMA$%B#{=OyRqThKjy8SjM$VkxGIWZKhr
z8bnVEgzqpY!H>|RP^KE2&y@Ytt5ZZhCR!0i$>^wQbP8@Ey;*j}X9|%+`Yr+7eCMl_
zsRbjUgspX1@y-YtP6W`Tqx8X^G=vSqZGU)S^%}N-v-c+lj_d{BT_US7`&y(H8F(;C
zw)GeZTss6KF?f~q-eSts1apMWY&aYG%@5G}99gmS#CcNm<v&a5Kx<5pgb}MN0L%u1
zwqlKPqpV6&1eEk|f6pa2ZcI+fY9MasoJZ=iFniL)KxK^A0fIVXK8*Dd1QJ*o_B(k!
zFZwN|Ef{$VS~!bimO!@z7B0HeC_v!N2$7gtB*V}Hsk3?I%baSC=J4MNWHZAsWnD88
zNlhBp%BP!<s(m9|p+N+TU>*6sD!uEu>#)I)8z@*gCkQd`^rZ6{{6!#oK9G$uV=0<u
zdibW1jl3fQl!-xcKwl_CMXMYWw~Q3v7%Q(4JoXF2kUj*@IB+3{TIQkCI1hgJ0+@ou
zxdHGZk)#L@YQPYTAmQ3UC`A+EHiwvJ%hf7DUO*R4-2eVpE?`T`!rdNh4D&%T40CKX
zE>FtlWP=M5iM)oj3^$rqgPOq(ND`&#ICrq;=JGgqkkxbfS~QJ08k02)qG-<+JO#5D
z05kE-ws-H0LXJbCqD}C5o|`(q=o#cTMY}mxq3DB~X&K!FK`fJ4zSn?g)t59UEKKF0
zSrAW+#_>oM+c%E!VKREk)0M*1)Ks*m5>`)q{I`uos|~G;fR;6@8)J(a!1`(p74u-)
zm!@IDqQ-Stv7>HaEm~vP9=q&3zk0<wfAUh!gJgUBWCiQ9$UJu`KgH*w)9%=}@ybJp
z^!ocy+AA2cj>(fJOLRw6$Um`x4J+d`x{&#mT^L@pzyOKRkx}<`L_on^2y5#x7_TYK
zhxvN-r8iK;Y$3WKw&m|>1bc7v7W}ylSTm*lpLhLhH=?KOzyPV#`QoH3naOLdS#K-~
zEQE@&#yrCn*4QxS9nD5VhazTzM{mcq<b-pWniv`A@)GH?Ffe4WUa{UVC*#o**S*6U
zRO>hlfboj4N*5bbkuC5H1Plq7RVIgTtI;i$^Ff7DP^I=|A_&067%nyPkT0Bb>$B+B
z7%$!oT~*tQ(MF4DZL{`j=P^1sPC)r=Vl-hTPGTcdtC2PIbVr>;wX3Yr(WWllpavkL
z_sBlv&GIbvYFvc|vK9mE7tA(eP{pMazjz*7$1zRS9vG<(^TJ-*_`eZxV(qmGwQFhv
zF8>nId?f+;N+!`_>YR>9gN!4x827}goPxEzh%w@*_U5--=uZ}d(heGg4#W(^mUuW4
zV?~BHMyxSpZ5>p{6D>~bQfD$|l1r%Mq;1d@f<j*OKGTbPr}Q4*+yA6>m_Bt+beNQR
zw|%>(0}M*LH&PY-Yq}9Q+!?-6|Ji$!0#d3xX`#$sDzBME4D=~op*Q9%XQ1uMDf;`f
zcr9kV2flPsW3uRM=fx|+pn7LTP1|(m4$;KenmjhBOLibty`>_4x+4<Fjip&}jzZ&k
z=#;$ur0w@K#8mbB@DaqUWRojqAs^2=@lCNa$I0yLWt`O>g~uaqj^583==wEURTo59
zndbF#9v_TWtp(Q`i;hTHbjTzOP-9~H4mim`<fSiC@%LPG6KZAPP-)E4mLOliKx7id
zYNpSra>T1+&&J_{FFgP7PR?WK+<4FChg|CfL<1IS;HZ_xe8e0Ty;WTjZ;;UPE#95O
z4SSw!?aj!kj=J|879NcmC$8oXTzUS`;%pz;*xlkh*cvyddh@_X%*wY@1!Kx%zRtsf
zFgL?Ts)FN8YAUxMcu~_=z<=_c%w`B~g;>!pSFKt#kCHINgnD%1X6XrBkcxmo&qW2z
zDc;m)Aen4w3|FIk>k3d4Ox2+ga8%||5z)8r7XhR|Fr)j(NNE(w#~^IWs@C)_xdOw$
zj%DH`iiU7dJa~WYsa!e>0lH@hNdX-dHN|E2F(e>{UdtpQaIdQ5%)My|cLsd=kY;ON
zTP-(H_K8`t{dDXKmRocLPxmX~Y4aKsF)8&!=lJTiu22c8AaEagc4A^%P-ad^dfk?`
z-z~}*!^W7nh*}yeQ&Q%bUQxSritEe>Wuks4g?>@+S3=fwZ%1~p4xy(O0$84C{>hs<
zl6&16nwTO0(7PMcMaWD!>0DwwW?$FC##IvNpZt$c=*9&4reP_N#;kO;J!5htT_=#u
zw|#GUp%(cTCmH;Z;jW@%a|3BX5S^jTNbuN0f0i2`)5Ny6V9bFIf|?5SER<O}3ZCU-
zZ*Gec-+;B>J!$|1BcGDs#(xYq!AaaN4iCI@X$+!eah4@dg4Yhfw~q#8nCs*faXYnj
z*Mpvhgcd+-24ky$ZY-Idr?%R?GGeBzNR<WySae9nq|MNL^unU?(tCW99|R@n!esCX
zI3uOq;V~Tq2cS{8%}>8@Tr0QQVI_10nE#~hT<o1GtadBi3BL3GTpL^q>y_YA(sGT;
zfq5#W6WJGj;qOKcYUWrRkj;xDk|+2b@yi#DHk`y0Jj6d&EpkSR!ey4t#9$CRIR5ni
zF^eb!L$;d<s$p5RHVH`tO!?*jhQQ<HzSin%v9d$}Z#9WCY)oA|(UkD6$6az{Ik@F9
zrUoQl>jSQgiX|UIF=e4o!s1_UaT<;}tzgs5m1*7%vc7|*#d(g3yQhJ+y5J|tMP5}p
zN^_kjHtr!(n~P+;)kCw<n`N4^-%x&)EcF))jvu}8bF3of7wJqUl>KXB6gz9==||wu
zRo&7vY8#AV%zS}*Yi_wp<3;mc#ATL<`c@5Q%q&v3^&n=lCV<kpi^=|}TUtediFuo<
z^gRZveV-^z-oa+TOhXXJKGMCZ)<70?Ro8s;^PIz}1QdM305pVa*N_;Qj4f*{gn}gG
z1)mXYs}N|sWmi2jfg^yb#W(P!(sU031f$wvX2=9|A^>mXSuEt$8tQ3&_0|NA@FpZv
zjFh8pL9i)rhMv~B8gl3Y=BhI#&+XskN8nBCxfqfd<kKdYoJ+ohoFGZgFc7&n1W3LO
z!9kg0lH+`XiwuIdRE+hAVFJVWENeA}6Wj6IHW3W#+@t(S8CgS2V=Po{nGrR2K6DpZ
z7gS94_`x@rb784T8>O*8?}%_J1@|^QT@cmtxy15XS_`HMt>}nFHUTEy!%|&0jYrHh
z)Y7YdwBfL}f2l=FO`P6U*oL&%!ZM^EMO*oO5%c1X%BWteWcj)eB9?Fe)Wt({=n*rA
zg5%$MIV`re5F$)_1-OFn;VUja!q|dKJf8Hw$RN=3q5$`Ggw7{>U%dOXiK-!3`tJcx
z!-imoqP_3-ebxP}*a^&l@0Q#xPP(p%H_|Re(Y~A*|Ke*Gn-kpt^o~nJG#O%p`nUhx
z<~8l?U2IJ$%{OmcQ@$RV(smjdA3MiB)HZQ?l;{?nOc2NtLc4FmhhK9^x9kJOb-qIG
z2LL2*g?4LCe*Fur*uHNhG#7<!j~$3?i(sS=gSIm*zvz0~rt=m(pUT4!v3{v{hEr@M
zb-{Q%TPjKKX}^nxaD4Zx`z2KG{O1${Hw+!jTITK)@w-Qx*zwkEx9w@CGFdIILM&|2
z;uTN-p^cO&+uZie{$TX7hXkd0|82U6Cdov)Qf_7K3<2a~riyKx<}ClepEgh%Ed;D2
z+W`qK!O5@kyDfy|nY+Hwi}aEctZdN4b=50!_D$U)IBoE0-bL4>eP&X|=ON=h1<J$z
z$84~`R)Nw9GKHwP&U-q9gAW%4LG>5K^n9>b$%~ny2fP>lZc0=2)<B^}LM)!I9WvmA
z5yn#*EKSp=-dA~a;1|3i#uZ81>6F4PpS;jN=y~kGp{aT?z(?yPaJuLnRWG}Bc{TE5
zS>W6Va(v!hhuJE_TXqy#E{1(*fLVsM#{R;o(;|Qc`{3Iy5E0tT3RDBsU1K*HyjzHZ
zCQyT~Tz-+_@c<-%xU%_)he3i6{x<Gw)6_NqT5Ni+9n<>`yyO{_a}d2&ihaSo{a^Sg
zRRTZ;KuklY#hGxaoO{iio+W7gP_B(~YZRtY<%fQW1tipHX%cv9Kcta8uGVMYk@(OL
z+-jsX8rtH(TT|Vs=UMjvx3c&_y|tE*c(COSO#YHrBk~;XDc}8H>kqSv4#wAJHpBmF
z2kU>#2v|!EbQhgvd(3p2dB*j5@)JLq=O8vlYwIJ4(($kc@brIIFJ$rVcVFNig=;tG
zv@u;SMc$%oO$ctG9Xsz$9FCsxE2fJ=?ug9ckvjLQVLg?-T#@|5<t;ux4vK5bpVB^v
zIFv6EFI8cE?KjxWcHqSMiQ~^K0<ex-mLgQ-XXJa00oIJuc}(thp7!5-K7DOGUGiAc
zDqtCBlt8aB086eLIc?+ulaEk-yPCWI<L8g#A26=2^cxo!%P!<4T^n>DS^rur|DsvZ
zBoAQu!SW?wC^j;yIP!u<MUX>2uC>7iO@n8GI0J*)cuDZBeFo*KS)Sn~QUHWkasqa#
z5#SbSGXrSZ!iQd_rW;f(%LjS@+chF=e4-HB$^__Q9J_IIUolz5E{7kh>a_^L3BJTe
z_drM9^yi@iI2-d}l&u;L_cYYCxOqZn+s7_$Kyd9p=%UQ$dV3U?nFvsM0j$6>l#i1~
z*rfT*mn5w~`ml8Xf|J3nrJyVH8<+jrA=*Wt0sYow9{|JqQ8Xz&e&Q7aZk|sLB;0X@
z{n16PPZ+a59qDiRsr@a<m%Q#xjRO-O`&FH<2ugip(&fhu8sF%`&x1t;$KQUZq(C;I
zdF5ZvbMn5O;WbOyV8&7Uu=L6xv_T4k3FgMWaV&iCne4M%Is#XOXJK@F+u>-wn{T|e
zrGB*0>&Uz8wuO|$8zI3qiT>PYmK7Kv!eY`qi6=IzaAug>36)wstk(VFgITrFaRzUt
z?M%xV1|Lw}_FD+aj6&8PqwI$0Q{I_T69F?g{g>mAHN}?KFknp9h#eddkLATOUKy7i
zk1-7_$9B*dm@GTN_)C7AaAkGBwQO8Unih?(ZXxt4a^Ut2gEo3uxvaS`yUspW1PXl9
z=d1Koi(bwBzTeB8R^W%x@A}it?Yi%dbp}0}-rWEFp{~vm?>o}7(66^=p&xCXg?^&(
zjqHZn87)_riL5~*hFV3xlp9j)S52|3l)50d?cLeF^y`;0J@cO{OqQLvE`Q;lGF?t`
z=3+LVnFp!(<2ODs8oHKXmTr5U@h<h``F;}4SPi}0{O)J_X~@cX&tx%hTD9o27x-{_
z?rO_(S7!M>QV{|xOX<~I*NeQ;&EiY5m8`v6vKn5UB?J7VyMA_xz74+v;tT$-<6+=i
zyW6t)`gaWsVR1p4*?j(|7sn0uB!aQl`no}9Nv%KXq!*9P51fk1xroaEw)<5=Fq<&=
z1i{G?OT!=i&C-~`p9e>5S)D=draPBK4jhpoVougt$iR(STJVfS%q;A?DU&g7+j}N<
zrI9|zbZmV#p<H;?%X5L<rq};+nqJQGc}{QWx*72JPrjcG-VU4InlC#u$L+ZzP|jX8
z`m|y`)X^VF9et@lLHKkJ?G*y4%2Xm_hqBD=10T=MiBLSSsZTlWwGbC(i^H+cr5fkr
zHUG<Vc9csNZKN@6_^-SyFA<t1oZ5BQqb@!*0JgMk*K0L2yJ(Mt)X;p#(+4TmS*Al>
z-}SKDnKIyg!g~+>Gn*kZ3K^(lZJuiGPk!1l3*=CtRyLvgsN~#nef2?<m9u8R80`wO
zQiqLcf8eq{MPnO}Wp`P(@>GoRHgXbS&2K#|Tb~cIvD8z!?l>lKxZb7R5i8vd*Snws
zm~#PFUmqg9YI)Y-dY3o<I<HO7Z1#4B>s?k7MBUP|p4Yn7F;LtPv3|)mq}Y&R-6)Wi
zPA%9&9_vQomEy9d*jedEAMX5EiAB1nWjt)*o71(XdsFG`1wLGjzS?T^?%X*@Y{nct
z2nyZH3=!*2m)@~MiuI;V_mm;Uy3?h1?2ux;Y12JrNU`p8=^dLj#fHA~;U4ea+}0xn
zCe-`r{*GNfQ}&9UR?LTsTz-{{TzatU8ltlnt81uoZCQTZ5t|RS+~$?{vhe2A!@T)*
z$>zPkf9jx82nqe$D?!qPL9W}Log5uLNZ}=AvUbxg0YCVo5X)w<fYxFSH;eY$6KA5t
zFl*{ET%et~TR$s?bsUbYInr;J^~zuP;@_?xy3b8#XVpRHjzl?oUEHS+^YX5%hd<>~
zdc;)p@`1}P$ZFtbFIjs@-M-_`XjQE5*7PcHCh8Ri*CArPx~x}xh7>z@wsrL)X5aC@
z{^CN`a`WxG`=(6K0$DL^=Bw<rn`x+_4>k0joZB-2DRBDq+~#Rs;qqdcxTnSa9~^)8
z#BhnrYD-+k(_N1}*=wx{E1lq_HzoarZ4YO6lC7K{%WLl+Ckx}QhWX`}<pBGOv3_8)
z8?(QHJ#%L@wW)&Bsac%bw%EJAe0F%g?Fl<QJ8PAMyYA0~$xJO-_GS6l=mo2wzV_rS
z5gWdHUpw7xPW_rizh!#o&r<lv+0(nGK2x$}vcmDbpMGRcTr@wlbWWU!e(r2LKds9}
zPAl-!cPM)Kp*Q4*D_vG|qi5#%?&}xPR~59#{GKl;Ws&w3in|{7$Q)VFH)hQrU)EPk
zR?M8`JelRx*4Cfe2i`0>-KJZ+!ljWV8S~DB)4ca&J83-MzVGX9Jf~gp90&OanH&y1
zZh-CInlPF$wV{1<Q5v)Cx~!!pN5yGYpU2N+^~>$c!1IHPio5MQEmEy|M$f89e|Yq?
z7!j*mHr;8}(dL(br1h|>8NNa@Evq(5ds@)uTjXm+ExC!8JTHCxtv3HJP3rr(W3Zo^
z(W{zo`^wp2`1Vbu&H|kxZK2Yc((S%CYgn=2yz|m-#RiL0XL>5S)djJ@Fq(1V7@iyF
zCw5&DTPQ7%c|1feR1h=cN>Z42osx58+$C~+eKcY7Z@X{9g5w<eXw<0OJ61ZhzFsL`
zRsnt;5x}oLzL)B1?)8nzK`&R2cSg?TIbtomU~E0V9jZb#cfRtzV*QA-GkR>EXp?@u
zJMZP*dt_%cQMo*K=*Ywo|7gV-9oxCR?2HT8duzY=iL>BTm=hQ3M-rl`WYU&M(tKwk
zn{18x*7yeFifo~dK$L#|k^%I<S2hG9P*7=bu}5+lc{Z-tq}l2315$>}W603?JY{#L
z5XW5*I=EAjN9INIn3TJ}duE!3?fElB{}isBqu><4*rFXm=#*idHHghy{$FE*tuMBn
N`R+eI{%~gD{{bcDf<6EM

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/BlackHole.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/BlackHole.sv
deleted file mode 100644
index b9ff9f01..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/BlackHole.sv	
+++ /dev/null
@@ -1,192 +0,0 @@
-//============================================================================
-//  Arcade: BlackHole
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module BlackHole(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"BlackHole;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian blackhole(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,2'b00,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,btn_two_players,m_fire,2'b00,m_down,m_up}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-	
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/galaxian.vhd
deleted file mode 100644
index b881e738..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,446 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
-	-- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 014e6f7a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,88 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-library unisim;
-	use unisim.vcomponents.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 1d61cf9c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,72 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-signal W_TABLE : std_logic := '1';   --  UP TYPE = 1; 
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else "000"           &  I_1P_SH &  I_1P_RI &  I_1P_LE &    I_COIN2 &    I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000"           &  I_2P_SH &  I_2P_RI &  I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000110";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_video.vhd
deleted file mode 100644
index dbe0d0d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,433 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1K VID-Rom
-	k_rom : entity work.GALAXIAN_1K 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
-	-- 1H VID-Rom
-	h_rom : entity work.GALAXIAN_1H
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.qip b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.qip
deleted file mode 100644
index 48665362..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.qip	
+++ /dev/null
@@ -1,4 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/scandoubler.v
deleted file mode 100644
index eba1d598..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-	  
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qpf
deleted file mode 100644
index 3b0d4109..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 14:59:16  November 16, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "14:59:16  November 16, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "Catacomb"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qsf
deleted file mode 100644
index 3b0a5c72..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.qsf	
+++ /dev/null
@@ -1,190 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 17:57:46  March 10, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Catacomb_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Catacomb.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY Catacomb
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ----------------------
-# start ENTITY(Catacomb)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(Catacomb)
-# --------------------
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.srf
deleted file mode 100644
index 14cddd5e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Catacomb.srf	
+++ /dev/null
@@ -1,54 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/README.txt
deleted file mode 100644
index 43f4d04c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Catacomb port to MiST by Gehstock
--- 19 December 2017
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Release/Catacomb.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/Release/Catacomb.rbf
deleted file mode 100644
index 0406943881e2ed0791417b35a3656c8b3d9f279f..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 323153
zcmeFa4}28oc_%)*9w!r*B)jXiGTv}_b{LaEw)t0@sx*IgMk6t-76e4e>ErXAK~^1=
zCdGF7^=K|v&y3!c-W3Z1AIVQ~{7WQxgXPpoY?t<EFV`Tvwzm!rIHh-7FTEI!=E$$P
zMsQrJxbFGB&+HDYgd`+b8WQV~G=JW|&-1*``@GNd%sZpE-kKS<{k;$W>mSbl!y9jm
zjsNt`e|+=Jx8C~4@qhR~Z@lr3|M=!OZpX)Q{l<q5&fL&1e69d+0M%!@o`<XBfLMX*
z+Ckd2oT)ttP<^iMWAb&-SCF0pSb!j%&U8OlpmwSuXn(qM&|i>Gb*axFoz8Q`fy!6o
zK-WS0)18C<f_$n&?F8vpdk)&0?K$WtC{K701amM*ztVZS@{}IH<Tfas(k7ohz&ikR
z4g;tR;Y4QwN}CMjoJ&W_56T9qL0WJhoU7BRU*buSM`y|>2(Cu}bZr8Hbh;0K(g^6j
zd{w><@`H1AUiEd5PiIOGa0<$#DiGw;nQ%!1g1q2N>2yu!0D?Rl5M0xl+Mzyf0npqg
zptJypFAD%vrVl`MG5`jkbjqiDlH-}689@0>6`*zkFaS4IAT$Z007}YMAjqaVF9Ui3
zltuUyEASGa`nvi)NDs~d4vhe6vs(U$2b53e2p|R^dI=~kfO1OtNO;gya3-4Rn$DC?
zK-ZKO0Hp<Z1pNi`BcM0vD>zdfk`cly4hZT~K8+#Or?gi9feai5P+B!mS^z;hl@G3i
z{^(3H5I}%eKm+9mbWnTL{~&+^N`UVIf_|nuzYYlUg8u2e1)x-b`XL}Z=uF9Ueg=>S
zBmsmQ)j0~F^gRH|qx<hwfUW}w(&+r(0M+*!C&69-@tlC<p?npI5Do-1CkQA#;0MjQ
zV15xl=$?2&X9BuzuRuAaoc33MlK{$^gvLf{zq)_AC*FMsKzPu708dna(n&UmrzHQu
z*!2K{`7qO5IZ=V2EVUEhwHZMD1vmxg00%k;c+j;BcnCmE5*`HrovCd~3;LMNnfiVN
zK={zOlk8C+)4{?D1o=e6eSk#($|5}Jp5%jc8$tDTIVF?%y9xw()PF}6tg3(tpi9c4
z>j1u90lKdT(D?v>_)rbiyrJ|nfFPgvvmX%L)0yTk0pUYqP7usnIukB5KGYwbX?_qY
zlt*$(bx95gmjGsxi|NLQ`mYA+kD!cE`B+XVAOEZZbQkc8SWLJD5b(VEO#H6~%B#Mw
z#(}PB+^51JNZSpd{sP=cw*C(wz=6(me<i5aBXk|imEauoH{ChtFUTj{iMAk}*hM%{
zS^!tViSmQ~gEOtM!CaWk8|s^MCjniP{&)cJKL8|awEohWWHNvY6`*^%4AO%$&9QC(
zwHKt(ysZYxs|KRI`o4_OC7cLv!XtpEDnR#yBgrVuBkGUN2LXf|T?asEq>}<zF$ECM
zsILIN3?O|G+|zm#;5OCy7@!|O@=5u$J_Tu%{w)BtNjxT-gy5F}w@v~|3xKi+2Li%_
z>;b})){cP+1nV%ZH3XDbzA7L8wgQvW2oHkaslehY2>P!+6aEB28sR~*?<0o;$t>Lm
zP(4qlx~AaAj{!9P0T4b_XiRzejS3JRRDjT@b|{(fBi>i{7vMwZ>h#Ii0S<whC%y(Y
z2<guNNUsu*jYdG}bWdy5CjfO7_!5Bb$?l+Y8-Q@2Gr`9Jbfz={!iVg~01x6XT?ca`
zU<Tcj{-QJ4L!{FPXs+K5AY1n@0fAjj=ND&y$vXZA07?t+2+q`BH3YZ?coE;f2B0zl
zuW0=tJ`m7#0CZ1$sXkA>4&;jX5CF}Az)mCDsjmPJ%A@<Tm9}63@n{Kv(r67P{YF6J
zN-E@T0Oe8I7XW0ptOHO!*=oc~N+TOBm}^vy(l-IBaiYEnXui^!^5{(M6A*6*=$dRt
zI#WM?PyxDr8bD|A#mKg&Guerc1L!(Pqx%3z<^muY41oG32=E|vNB03wC*wi%QQrXs
zc#+N^|Cr9ZD)4Q<7b_5?kuLjK1&9a#4nXGsD2uKM2Lf6r2ngSDN;xeUJK_~x2WPU&
z=z2R~Ie_xk11K$6GnWBqJtv?!Om+szz)TR-C4P_`kSvkx)4D<H3jy6<324nE2+C1A
zq{{;MLqMRf=uGLsyrDDEL_pVf0qFbz0Lcmg;X!Ab%XB6^L1}cRdjh(qv;ZiL#)W|J
zAsWek4*YRC2jdf@y%%r?AV{ZiyB|Pl1hjt9J?Sg5qY3ExUjfQ@<zuyOrLm*_t0Cx*
za0(zuqcinGK-Yv5(eM`llB)pdeli@N1g`<Ald5r`Ym&X7e>zit1awV0jO2@SE9n{n
zn)iPVptJz!{z^bRss@^~G&cjF{-%OA0W|lj^T?JUm@19Zzh42mo(ojBH-A0Pfq4$h
zb6~a{ApJ-BbV7M&Lb!QC))Y7KNon7D!nf|KQmv}%IbI&?UogiS(-$B6=bI*FrY6LU
zCuPojJND)T-9B^SE9E|V+s#)hGVA=yshoAy%L~>XF&Xh;;<_Ezag6w);^1fs$O#}7
z#+4x;DIz-InBWUgN~L;KS>Ylo^GF!3l%)x(@Qp{qewCoUf3^fAjQY5aFi}7w5o&b;
z?A?qa0Vv5(6$-+!wy+!%gfum9kJ-F0iOz)EfT?8&^<FZx(HgV_lxSj_I2c9hoz#?;
z#Gy$P94a8_Y9f@1pHQ`eD#T)2l6P4`A{i0}KaPfDef&<gSPjLvcW1ahETr1B<RJQJ
z5}$qGU1$VFY@7r$N*$LcnGzBlBIP0wNhHL?BE<_4&jewwNk^*86%my^%|S6E>4abZ
z&M#3`P2dKXvzpK-2(_O8zi^0Ei6hZAW=__!*Ff<N!2U_(Rfu{0eeb>svPjWQ0bl;i
zd#6afx}@r9>1%_lYo=Ul?7;A~RG(P)>c;Y)m}L`Dp7E}FvA9%l?CHP1baSm&SI4rc
zd#x6XsY}cubsn)fFv~AmYmRwyMPQopsnGH-T~8Bxnr>&4Tx*uirq5ZGsWD=TG^<``
zQ7C@wKfYrY#b#Fo3ggDbY;G><Oaw>&XCJZ^*#42E>4pW(B>TBh%9KYXh6O09!dZd)
zu~ZaRu*1x6ZO#>hZ~c#&jk8c|WnR01{?#we#O%4{)p(xGt@D{mmk}e=#P?z$7eYlW
zglkM3`wwqW$FMC@kj1hqSCPbPP5jm$yq6Y@>(TVB?~UEl_<pTE`P!<3hN{wW@e6Fb
ze$Yt1kbP7?P#3#zJgaU?zV^sBUmT91?7z6X{**D^Lv<#d)kSQ3!wp+q4HNEaX1vEt
zt4Ba#K`Y-p|FF;8nS^HcdEbBTmf07+LP=<f+Ud&U-<aBgxdIMTX4hJUP1(s@6a9G9
z_S<V?5Jjo?Py3J6=ZeQ=<x>W6{?UcA!%Uk{KQ;BBjq%eHis5FOl9P)~asT@8&me-C
zoPfyWICLd*x%Qq3#jfRsWR`SjEnwd8o;w$BM1#PeGso*@H!){Ja;+6(tprvOurBf0
zP%w)!sZjKzPr_^xYGz+gYmkrqn?18YXqH84D1lMox3crvWR`rd6sydQ>tVyfJVqzi
zXueNb9X37rS5xL)W8#W)3K`qJP5pjNB`bXODzZ-BA76FfcyGtH<Y@MOeYh@m&&x2m
z$vlVsUAC|%pVia8L4KoFSC0et2_|>t=KX(PJLh%mpZ&qy<Z-6bP!+Y(mO|vUuiv=A
zgPE8xr@UIPd~@o2ro!`x&BUFl@@mbo+RgE|QGjZyfth<+t%tIv_UPQnnWhG)teuSA
zu<MBMj|tE}t*KlyWBlzA?2eC}{_|<X=_-<I=vvhL`2fhdMoV?d>OYs!?$po=^G0_K
zjqce$w7h%+-{sTn8>?>m#jv_3#&9PQI`(8?Qpz>l)=u#t1pAHKZrn)NHSlO+)mocG
z6I;KAyILbwGn43TwNzfi09IA4^;p)-?oOTi-fvamd5xFQJ~u9AwOUGkKEvIq(Ac(p
z*EqaY)iKiZ`lN~<v$!lT%~RUW*O+*HO>dBPjrdJjog(S;@$Om3%`A)5Quo&K>EL|4
zdzJ%ORjjNksuHf@veu@@HJ~!F>e~jfnk|&Ve7t+22wm~+Z6jk><iu<XfMd0jSH#Yp
znmy|*Z&<8ZSbN&Q`Hi~A#1915%DsAf?O6M{+hanr^*SJ(I`^41^G0{=Ug}Go`~1Ee
zR9lu`g_*6^ze2frd-Mtnx-5I1W0$ey3JJC5*!)U)1%^+|zL72E+Ns#tKcAe)ohk2X
zYAV+nv)b9+^Dk9GHPuc8-$p+ClyTo{OuW9aZdx?1gWWC6zf?K@QstCu$P9@$@`^kI
z+H=gRwb?hv?x!z4kJ$9QnL1~lV^i~G`qX)jP0yRDbAI7DR`u5U^$m5W=uPr({B6y`
z^Vega^3*ag$JA8l)3x3BGROX>FMb_X_-nMTr>uT`O>VGf%3iNAaejMAL3@AgBHeTP
zc;*%Nc5nY&c=}l}$DHW)n(b1a`<Ca_jC6c7UDI#B%#krO6#s=^MTz$7pj~HR=^V0Z
zjabcMQ}Y|U=P-)pqO~5&T0ON8<~MfFc`SpSir3ffCbZ_an9O-_YCX~BjKFjiDu`W=
zsPWI`XH4R27R-M@uy!91tk&bkbTT;W^s&!<sn!n$XWjSA1urv6Q}jittAyS^yUL1F
zRJ#nZDay<?=|)##v!!F^a`POUnLn51#*f$0e+j7#%*)tZ`B+Pi(T>2m_CJ03TF#{S
z_S<hvA&Z>*#3)!W?SAZ<nd3L~hfJmyg1P0)N4u{*a7-Nk`LgHZ-+1b#d8@m2|9R&|
zSC(_r3DcIY<@!>~Rdh~I8>XeMk};3il{hpx|82psd82#suwU{1MpYN{M)wtmZgK(N
z=w{P=vfE8bQ=8)v=_;#i@2~BL`zMog)%OtTnms;y+q|9)A-LQ=hRjT{kz<ZU?@xy2
zSmQD~eR@35cuy^moU+TY`_FDM{wMwk&N8{z_%zN-cFHF{c+hyDd$<43bGCNx_WyfM
z-N|<P_c>eLuhCb$aq|Cv&gl4_%Ky)y^D?=={10`OjLZIi(D^xR#7xsi$$yN0s#B)M
zOrK|eRlBKngMXFvs`b&tiZ|+lJ8z#)9H&{_y={iFW;+-j`okMDUO6xPvk>=*MQ&u_
zubI5o^rKnyaqp|NwGsck?4Mj-!J?lx&nL?3mG5q3iN3BD^mT1~-aJ2O{L?rJ^XB=L
z=lB&%+{jAcipbBlz}q4i{PwZwYG&@to9DBgK|#41tBV^qm{KztBa=Gd-Zh`0$efzJ
z?TC*NBG5SHo|UT(l22>6pZm$#Yo`8U12vYy`Tu%(k+ZY9fD}S-u02vdbrAZt*mZ4u
z3kQu;_I&xKo4Gj(sdHb_=i}#9j{~l=fj*nhO+_l&QoAJB>ZQvGSIZxJCy7Q)U{3!Z
zQwd+8&+o@)^Uus_)>L4omsgMfDZMmb8<@AN=gP-<j?HsyDh|}zqM53Xt4h1U5xXu6
zxgg*1|Ge|6xHVO!`6)jYS7u6^=h#f#nJRCdV^eWurnI*W$COKE;Y|Fva^C!x6|T&q
zNhNA6WHk#)Rlkut3FoW0g^h6IVpdb14nEd=ylm5aylifh1Zv>AhP1A0<MZ({{TJkc
z_H5#1f-v!OVEVL@KGyU}XI7@g#0IBsFLLhRpPxF%PpxXAd^tT@e)%zPXolA2n014D
zz;mQ#n&P##RHo@>?#XW(#FSZ0rdcp>-cFwdlO`6awUFJo*6@vs8J{>LSAR#(USJW;
z+v)Rm`W%I5-cFzL5%~Ob?Mbh>-2l(EXD!)~>Dig-vuW{${)c=@*mHRJBC$?*28s*;
zKPfTd|Daq%Y!($!i8E0U%E?016r!n+kvh?OQ%a9+HSe*7+mmJo%e*Uow<@;Eqq?wk
zHH+sS+bm>cX?e6*5Lhg_jQ!J=yUWPjlF~!e?b!b|l~H*`(pw~NF+bYXbL!46wv4HZ
zqCj`gZMyJj`vu#5%#_`JLzeC__+WIm_Cfh?%yv(Bzo9mtW}(!nt#_?v>)k|$`>eNv
zQR$65^XKyM*o%2*pU!T5f!(POskdt#TK<&bcE<0n*Giw$h3$Mb%Z}<xMKGs(Q;fT7
zK3R<XjqwF@F!nx=X&dBaaXo&wu9f~s&4qu<{<a=pp>E{MPUKb^ON;L7?gM7s?L{<w
z;m{w=FlKYins?jg$gsE1{^7YYX4>+QF=gIuo0dIOW!%Wq^2T+JZd}Z2<F-X1D$%!|
z`KQ^BoTcwG#2)Q_8+^{=?Gp={+g9DVYyh7Bp2z(6Jf>R7E=!y3_dKfhB45_VrN=KH
z{g>~qjc!FBbJ~u4IZjBqh;u3=JiGH9Q<j-FF*$9HAZ&m0;!ZmXKFkrAFwxC>>wRUf
zFEzbYMvCGxz&1hw5yMI8V}DsJr?^vOR>~raUUHuZ<(B+Lt22K5oA0i^y}aJ^-IVJE
zyV?D_kN&rbtq~?y4IlmRO;=r)Dk|09_BUR=Vq>uxd#h&XSjTKWMm$U6$J!sBvE#X9
z&VPKbid(be|3kklR@IsAvU>EVD}(e8|LF{wbIY3l_+FV`<x!kLc~-GCa<1tK(qL15
z+S)}M6Cc2A<U*sAkpxm<6LW+hW5&kL{mHhf&ZoG{POtJWFWvfYf9dkXsuW;5dl)<M
z?`JMN7u4co*?(QT)`Xu0p|g`8;q}tZG}EuNgC9e2n99wjtZ=F5_I2-_V~r~zQq}nN
zbO}=DPJH)g@)qI!`QcdI$u$RG#7FP)KW;c^_#eN+`LuVg{0YAful!BF)gL@*kN24G
zkADy!0_^R;hX8kH@7IUx>P~*<o2XsmM)3K)`cuaE9y47=1o!=kD|{xKhJKciI`^lS
zFC@xL%4Ej1?#Ex6>22?ss!lMW%E(6_{nd#<iW%{mK=2f;jXm*SClr}@Gr_j3&XR>G
zC-m62jEkjwOE;j+FHNm6##T(Qf&DI=5LHwBBW8cO0M${qAj<WD`iqU?f+|q6)d)By
zjSUTO3SV+%D8i_<Sj_fqN~|qP(r?@emAgVo;n@C*UWVVZUyCyQmg$g^CAr)vQqgKe
za`B6nm1HtREyrl3lgn31RntG-SvBCXGPV)f$C27&ARr~7+TKg7@X2!AkpBiX8YTc*
zPPm-l-yi>*D(hbMIpMRyr`+cXQP&N^{o?*1B3<euNTpI`7+ZEKxWt)o3%Ec?)BQxK
zN<kyk&84>dl4D={?t~gu75wzc_eex5Rrq4es~Q;l+pdduDdIi@g3KQqDP>FGDaMFc
zSH_#Jkbql4Ur=0(x~$-j?gZKK2hG36;iLI?D^&C%lyQUnP-Cv&grDTM<+tnigx1hx
zh42ZO3#riZVPstbs(|XgMER+}{n8E6%Psm@XbQqq7XIon8#}-MQiHw#5^huxf8~oy
z`IoK;M*y7^h!vo!(Jy<KyfMGYa$AI~-zXtH5tz@47*HgVopR&2iB&cG^*blksoeUF
z5?5UsGt3|WxKN%El`{VHA!LKLE9qnUw<}lGr+|7o12H;PpmIrw21(VINP8>$PAHYh
zP#%1wq5*27YLxt<KGm*EoTOPg0mdx*(mh6)xy%)Cpf*4;PG}vIK7z{tRqD^ZSj!(8
zqMrUP!5zzQx`?XZEam_;i{>M;P1nGPdUIi1L$!j(_C?Vpg=M1@nv2OX{0cb6NWK&o
z`U^q<aVz&lq4u#4|HGw@ff^dcQ~=Hb&aNAgWz0Vt4dM?7l&SLt#zt0UR3QxDyqm-i
z<V22Ps(@wav)mE>5wY;>Z{NZ%b_7B${?ZJa^t+L}LYC$;3_fBW6$UuT(8b@f0*3Tp
zs$ZOpk#jHqG4cGOAF@&JWqVDQl^$Yti3wRqB2-Dtl?C@U-F%Ik(nh^mTH1#G8ryjW
zT?O7sR!$;+GZ!>-uPF#Ew;yJ5BD6v-%SQ}fBuv~SEQ%pB5vq1tzD~4Oz{P~cFC#MO
zFV)V85*I!ISnH?Kf<UD)g2)6YLs0=8DZV_A#G!eie4uRMq2a0}CM!{sWtW1c7;dQX
ztbdiYrH!0uMlHWboO~TAU^PT9F~2Wr6J3;l=>{<N!(YAhS_d^+X$o@YBTZA9k|EVN
z`mL7_pas+tV1@LFprL^b#Du{p{Z=48w(0}H^(ESAkRiuV4}PB)JILaSIOvl?7k(Fm
zQBpxl(q|Qf8YB!xeP&f!9$Tef>Vp<>0dn9^abgU$NbEst;1OmE@hRw~JXsSoQ;1C%
z0qU(hCPAC8fB4de7^opM4#a3Q%WT2OmwQ2yKMG~W5bvl7zhyLDhHAXQ|07$e9TXAb
zIuLZRn*tLC9y5-pkc)yzwi^b&mWpsi^1=9m(<zs1A|ww+4>PpzIw>s-cqrwnxbn+W
z8}xVV^Y5XPUn>l&1aclJk!1RdRXG`iA)Q@vrep}6L}*c4PI8nw0k#Q$CZ^ml%s6UD
z0Jc6i#<riTer+Tr516!6?<Pi|o-5>|nEp1Q9YK~P9QRe(MZ_xP00DF)*GZ%SsIRzA
zBT`LI>fG1f{F!)5|KjdlWk=_E{nS)nK5xO-(|;ykKA&Q9+9&H249si+!{Gy1e+i)7
z1BieB)0bueB`VbggHi%^SOs7Sju>2Db{<O~aVBC1g*>4Y#G<_9M8dQlUd#i6G4x%Y
zPq^_>EN4es4?(!AAy~97rCq|$Pa_ol7SK`vbPrrez4tGyvd4pbn$`hhP_EpECRAf-
z_{!v>B9Z+WUa9~3zgeJHH&wYVPk3Kt_$yOVMB8Yb)_ejNL?Z<qW37M(Kz4_RyRx%Y
zRyALK^<4@GvVu{#M1DD+?iFVEoW^vgX7gbrmbICaG;H!EVvZMbfg)LN?%qqjnsff-
z69OhYZIz>{z^U9US|ahmAMs$Xosx)~P%mV%2wObDn`nX(+3FG<a;#4GP(<Jic21Yu
zO{xn3jK+TD99>y-peC_Qlx<4nf?}j~qjNOqh)l4dz;vog%mXe!URfy%1FoP7gD!&}
zkzE<faGk{JbXYfK9;ZO$N7qm&(5J(|1+Cr{@M*FsNf7Ad1hk?9PN^7G`n<Qt;CMuN
zNXW$`;K|DTq_$iCSC#ut9D-?uBNf8YcV21sL?mjufru`5P9j~oD)UtdMRcl2q@mvZ
z0~J&#sSM?E)CBcH%a31}PQ-79ZU8tENBl&p!GgsI<sbSl?-7h<QHaF-#=%ewy1#}-
zBpXB7V7n1rEOXoR8B!Ju6qBi~2zj|m2wmjR7sg+aVk<aH9pZ*=>$b!cS(iL?z5S0C
z4B9p+2#YWwQ3SF6h%llWRa3f1NleIzE^J%0i4jLSnY;kPP1))?#5#zOfDqw;V~n^C
zjSF*Rjx|4JjQ`iAPMH=|AtsbXj~Wn68}bYB6#UU51Z<1}ks%P10Ehj!htD5ZmYsJA
z9JU7yADO2>ZfxK-$bZV`6=6iEp+2GQh&fH%Yn!fZD`HL*6irkZ6UkcRH<vN-+hx=b
z%0qg5iR}vs9`(!62&D^O?pe?%Di->%{1hB2b;`G(Qr6?Nr26FH2>GTmDQ*xc<-%Z-
z@EA+!?-IHtPeHnZVQ_`9?H{660tzlMr`#5%HyWU^0F#=j2S_b&qhw64vOhsh(?CZ!
z^aasGUOQm>v6~g~V$&E$;;c`VD>T~}N<RUZh$x&FnXeOkBG5>T3Zs1`1g>IQ0jM8g
z3+Hsrj&Ha{up^>HH-4RfP#QvT+!k=AKO4A2xabmMK2f*_dr41L6f#dqTo$-5H*`X|
z*G4NX`^_^#8m<+Mt(zC~XcR3o#{xGT5sgEX_S$~YGJVvv52y&2gqKwWI`##9?6rNV
z{g%~iS(ccxP#Nk5+6e~&-<M3uCA+&wzs=<frtP<L`|WN^a&fYo`F=aU8eQ7CqHQwY
zR}<VEc!jY!jG34Z<;V?_V>uX2f}C^RA=w#_`!GN9r?}C@SvLm2k$NN#Mj6}Ry71kN
zdEjD{$BVo@)F!}kfSD%q)zo3P<|Eb3wAHqWdnPnD*m)87XqF_Hc3!(p!V1OeAmx|}
z3Vgy`68n+mSUw3foDiWHbD5Ilp<Hr6j&-}P0q1fB?}0ebj9&h$zr<}4JA=4Y?H+<O
z7qnLXBIptB<A81Ye?apvWugoj<YZ_H2<0V`7kvYaLkc3F)1_W_H}~Xz_cg9d<YI7-
zBsUU@-hR{TtY86agxZp(8y2!_?7b$8`4{98gKJ81J!mE3Jjvqnkh#Iovm=(Rk*7%&
zAIk59uL-%0+37Rx!?G0HD-TB9&*>e}+-B^w*5Gi)Z7K2G{!nHlDm*KPe2Jis+~-dd
zE^m~$cb7qkNe|`8EA91#J*u4h_;!JmWf=%(%qEbzk(2WR6()~Z5y?!8xW%uHivcPw
zr?vP=OrESX7|lv@ViOk<hLni50~_+1Dq2nu`Y>vJ#0;J|C(GR<yy9N=q4}|`mSFmd
zfVzh#NlqGhn=~t2I~{N5W;zZG1Q%x{o3_x)(jw-@kd?O3KUIL60M~O&ruA1y;1Zq>
zrXWFfghxO*)(9!aavb6S4X9Ah+EYRwqX|MlC=tVa^`Di}BFl0p4HK>djgg~?S<XaS
zC(;*Wxfg*1A`>KLB@pgnB+zk)TJnK<J<GY|_VAIY>p}F6;|^KzvF@EIrioT%X(Dfq
z{6rv5-49x}tB6RjQy6^YDFtgI2ZOSb;ub9E6&fFC8XB4eh8W~5k^^$LxLMAPan7CS
zS&+Lc+K*1r*dX^nG>W!H!x6|}MgD0m@kbi%5#ctJ4a@2Uj5c-cP}epJlPV@*0Fgpv
zl)*0F^^Uo4l~WD0pg5tdF2!8F#dSHjtrMqvd5(w{wm<MoO`TR+Y-+QFCZFYKAN=-J
zzfZM*akYtBjJoNcv(jNXU9f00eO^Ph;QS9p``xGnP7^|KkYS%bD~}@Z!jw~Ph$mj-
zukjI%ay*uJ4p$(}>%sCt#mBz$&5dlmWkxJfHlT|z2jQKf#BqNBuwrl#62!K^4^3lv
zHB(T&8;WTlTql_<5jxIE#-q0Tq%Uk)-{*{!@<KP#F$}$Kzv~wojLKW&#Pf1gip4xQ
zlOFt52LqQU#WnV(OAV8NR!{(kGT;+1aY?VhJ;&u<lXQRPZj{WsBD^E~#8U2J@=}+w
z5K}@KS`cF>PX<cFb~kfqId`eH74wI%0`D;f!q}aiTeu=(5GOkR@RgB`gQFE?2MVub
zq{DP3f7wixXa&Uu$^cV0u9GR?yV8fLOTSyJn6kbX(#7wxq3MVU4@9ER-nO5K&s=%J
zc;Q8T*EEk9*OebJwtTVji1CX*vqy~I_{ckZ;ubW4mBI-uy%Inu2x796#G?p=VCe!6
zb#S2Tt!^&qZiOB~nAMNeBK{#QH|DsL4jpKMp!+>dK8$_&C5PlxG^%pQlp<}7Uu4NJ
zWLyTr!1QhEMJhZOth^;y4Zw_KSWwgui6Tj}4);)w@B#TSJ%7ULhOQ&hZQ}>WsWFQV
z0r=gp%AM~w!E&cwdsW{XK|U&zZNyZBjmhnR%?q0}s#9lVWB^fU!N~Zpf0+^{Ht(mD
zX&~>wbz`|?h)9S4N1zLHm*UhHZ7-B}LWAfe1?=(QjdZDy#3LKwKYTx;X`oPvFGz{x
zfURQ6P~7hg_b~4<j9$4rSdy4(PLhSTxG?%*&?q6H8wg{H!=!YE&>zEkfN+}{qN(cD
z4ajniY#O!;ib77o&>b5<&{GNdMu}iV;?iC%vH;$ywb4#lItiFigk9}6L&-T@BEJ^u
zLUHww$vqGNo?;bHL4gwz*b0oi5^~%wH;+49Lr2mhR1De@JEZ2rPkkk#v5*48iah_6
zI12kvdk#*J$t+mR%(jfwLdhZ)GSnwmMlfSAxaE8@8}b%$jIbVx9R~XKAxJ<n3BMLk
zae)bbb6edluFPl|-{R(z;5jIU@v6!(l`&QL^$`eAlf-QDZ=3YEXdq}{flYASBn#TG
z7+C;8f_VwuC$m8&IPXZqG_&o&xa!e(#?Un=RKNz<ii+FC<-sJL?J|ssGRg(FJLJND
z=g}@6v2_fUE;C0B-M>dvq9LFKnv8bAK$ipzLkiCxG{R8CJxvdy7-NPK^!S1RbpUEP
zo9q&BM^;D>9PWh#;f@P<em079zj@!eC3(R(M5%c~6?H|&)snckg>DZuA!06ya43E1
z!OQayZs}$PoK-oZV}u##m-g!DPnTc!qYzuDfM6*hVH5}gQvl>W<>O1Tj(}GfD4IaN
z0>0;jWgY^lBTDLm)5t+>fZrO_{TG@Cjl*pazT7^WSy+Z5B7=-2Es+X2INC-IzD>zl
zke9frNSxE`<<0_yEtFia9R@IjncB>SX!0_;bYRA@7>{w>=lKZwWR6rXCBg|w9^1b-
zqTOufL_4B=#ej?r#&fO+tn+OULh2BlvW2n_1UZD%%bTHdN^*kxPkda=GSZ|5Eu%6l
z_$_F^?6u*-Q{cYT!J}0q_#5(|u1Grb;(EV@=lt}%CNf~h%$VV>h#!tCpoM`?DLD?u
z-P{7fbJNlW?${jCPcwLcrDa{@Ti9U?4)@0y0!ITV(8tIfa2G>`7=QvEU@E%rf?kI=
z%*S${6HMi12pKd&ip&HISHvn0f@xst3Vbg|e<g|;M08Af^n;)Pd=~Dx4mp<oP(t+m
z?$8^$b0p<m9tPBq`rMGf^v7f`ChML$cK=_4@6cL^U6?UNgQ+C!wQ--aMZ-`;qSQbM
z+s%oHXdv3uVCNVTK@82H5Y+|&SelY_O|n8$%Yih)iPuA}gTSAzEDkAu`pi2Uv5u{E
zZNrwklS76Q!uZ4zB4UGxX^?!_&7y-BJJALK+{tE{`(XzKiC`ieKC)4eM-z?0b0F2B
zeu)(&9#hsqPq<!vQZ;o|4}XNezJ}aTSuj&#H=Yons-lI6Aj}a|0)SQri0YEVM2tum
zV@L!Aem5Wxh5Tig5=ei7LKkUux{Jm<teihK--}}DC{Se0orcwnb)Z?aQq0hx?&IyY
z0;Sw+S**>@S)9?2l;&}XQ$PVT1D2GHStbmiUm8B@-!}{C?1YG!nESL7gP7_VP*U+n
z&%VRNVzR}8=1EC^E}EN(8Avh&#gfS7MIH($49vt_vz7f=cg1d&)F_JUR5<L<Y<~<%
zWDvwrB)1#!3x)V3d8*(gV){-NPG~P$>FB3i!(DIZPq0wGwKcnW!@^JG_sd31&JD%e
zt)k@`Sf(QTEl3X&jZ_<^E`Qdx2TCsuaKW<?EzMcFJ7DLR@*I=o!@Qewklk&7C=4V8
zgRvAGro{)d1G-wu>0Hm9<st6nMr3bb7lLJ7?ql^!ca1bGlj}#^zJJ%SC%OEN_q3-+
z+tT|M=8c5|w!B`>55@DN?YX}x?nA^OmrUX|+Gf-G)MQH(kL<PvC>ruY(K7qAGrW`S
zvb#I;rkfgJX@n-yqxQ4yBP@52YfS7zq)nG(4`z)*|0s7aBs~=CP7(lXiu|nLk8wxO
zb@3h^JtQ~q7%p=w<=6R2Ie%B*SC=OGPPt#z`-b(_Wn#=W<!+aZZYvGDeSg(4&amsv
zY7|+{5{si|>IBoQc6*)H#!<{<yic<R$_FnsP%`B@ge&CyAs{*ABCi26nt@|jL*=@5
z?qOI-&EeMtd%;sE4le~it?ne(N1}^lid*!$u5(W2p8myHLg&Lc3?yIPKN!t3ZB#bz
z72%QHwksM{7a6;fO{`$_4)wBUV}Hp{u?rSL6yvrHRW39YtTeD3u@Y@Ozsa(*huo3A
zxbCG#EUiC3!trFhKYzFO97~?D?mowPKYPaN9vawCva@`M3j=+6h~gUgTcy-Cgg^2|
z`9V8OoL$kB1lKn^07v*xPEWfk9NhCI{%q`j%QAVp$GA~qV*>-ce)yN=Jvgdf-^k)`
zon7FFQ1POpiGx<!-DIT;ZM*Tz5d<H%L||$O%-m?1HvDYyAqza_hz)q~KOuJ6@lwf_
z>(0V$-_3iuDaZIm-VH?aoWuW@T|_sahp|j-ahWp;d)I%c%!JqBfNn%f(irDn;*<+g
zy%=H~^5Y>r%KLbjdt)OdIMOlM6c9s5gwlnkjaFKtsDe9WwOZmBA~W!nn?yuiIBVk@
zEnCsKxQo9cW+}ixt<~+s0_CNjvE;``Y&+W^BiM45OY%kzO)BjLK2UWyDbK+nEpHi+
zgq{&D^l|vbC=3ChFahExy<D$XCB5F0>L2-6H#r4Mjv??Pq`|fJjh1sWsEws}SfV2$
z0s%~+`AuQHh5US4<lJ;!L|W`;teBiHSjYJxyMRjp9Uy?fp*xkRJVFrydf5Cdut}_x
zeY!znWp~C#K1e|`a4Q7WI`{=>MaelUOLu%xk_{Wt0K-fjv@~}U%M>;xHd*Vf1cn}g
z1z^9{T8ogyZd+)&?<j%|5J@}Ro(C7*^0o9zzK!>d0M$G~GrO3HcuTCGk07MgH*z#0
z^?@Cn0=O;)6w8aNVDbz`8RkkaR$r*xnA?XK0ER9(goY4{2w@o*;{y=A;gv`}q7QQQ
z{+v_?O@VO~9hNlW8iTxvy9r4-%YhYm=d+Kn&EAK(j2tto>k9@ktgq8xK&PALaXxO7
zt%O2c+Dj7)ORK*c07VMNkYr#L+JniRq@fg8Ki74{A|B$B5*E~5n8@E>`L1=ZS*#Fk
ziPAVV#kFj-XeF|ntfs<kGM?w7Zwm8(Wtad$gfYlJiN20GKq3xgn8-|r2)0t3AtL9c
z8W7g>#l26;qdy8t(R4!a6|pFa(f9!)3ilz(h@i|6j>!<X3ib-eF%3LP?{`mgNqy^H
zY3-<mt}QdSGM)y%+7SL&fbfSbG>V65my3y8Fq4JWX(A#fiY`9uVKzvqQc>t@;N}*N
zaGfIUhTalVZcLU|$ZV;Iskl-;N;4cni{Q*|c{jXI;3#M9p=83<^$=f5_0R|SrGnD#
z^D=kN%bx~M1$2+bOk6D$58DE<ABv44zwo~(2j(2IoCUP!plr|yIV@j5K;jhy1otS#
zGx5y~$dZu9(?Yk~Mn0ScsB2r7+>Eq$0GflE{nuKGYocpI`fLPU78W#?g~q|IhZR=p
zq`d%fv2p=Z-fNkd5(UlCbu0mQAwsL;!x(pq42x5Kglc<e#iRWXVG41P?VBMhmk4v9
z_<LNao)lG;_i_Xdb~7>~<UIZoy7aX_n=*FuJFERY*>_mw|GoHw=7;0{e`){i_}c1!
z)866-UM?8rE!B;8Sm(9!KWe|jdPKW!`xQnGU~l;K{GahtY<fsW6*q|=EUYpt+0nR@
ze9ewx)y}MpBO+kS8TiPlc-*$z$RnaP;xd>b$yYO&=P5m`>Z;<Y-giHLQ&5qdZnADK
z0sa%qWsPY5NM9=BUtQWlHul6G7?dg70%9`DhY*L+Zj&40`IYgAXyA#@N!wazix$g@
zS<A*BoVJLRgJS`Utl2KXua#kY%bp{{=_HY&xDOur&?6V{Bcd;LLkgw|oU!CeIH(YE
zcy%z2ToUzsSSjfvO7z^37h$gAxj1dClO0;B$m}E`_5B7*fvpPv4xB(Qv_AyP4nYi4
z5iG!yyF4sIJPSr$WJaakNbQ#3t5RSD1z{_X{d6DEDlw~xTX;Uw=|(Wi8be0Rh^)4l
zb=)VlNTkMzRPq-DrlD%y8bH*Fv0RiVCGHYx=o4E6Sdzs+i3E~djwfM$Moflzq8JTu
zyb;Dh<ms?3$V>PwvE2C&X|G$!VjLO;_PJy1us~LJe_Tkt0@8TMGSI9D`<U=mG<YB6
zw?crp2(C!vZA2w^FVBY=V~6eTMu~0lWP3!#<4cT+$-^eBPTChv{R+AeQ|m*DYDy1%
zDNJUbl62iDONI<w=iM^8DMY4hcycylczg)6AHD%xXh(WX7>tAYX$iJf2$6VzlD#wJ
z3bA^wc`-?aN6@fH2bVb_IJq$1=pf%j6;vcD>ZxCOcVh@GIQw8Z#4@8$4G~cuHB$OM
zm^c_PM28j#SxvM?@$A&2&KQVQM9{*`1fmaUZE$~VRl6MN%DWWD$+4(D+Aimh$acNn
z9UV!kuA7LJxa!K?|J{QLp3|d}a#KS-?2Lltx~?ZwHLQ*u_<#Zm1jZc1(jr8^9Al#p
zox!-9TF`w&1KV9@xURVc&o&`Go-qQ14AW6LZXsFVs8^4jrwEyO!sjJLM+5^gzeSv@
zi5La}tE)2vHwFyvbE93ZR|khOp(bVBg!L6;&+4JKKJ^Ztg|K`=O2{D>0p$7<7IH?u
z8p->hF0jplsge`x2c{e{E3oc?ABdbeD&kgKa^##jA;nGNsVnSXp&Pp0Q!(VZ(7)Y^
zv85?t%Mlhrr~qP>M~d<oQ7JTrNvHwTo$Yuyq9y;2QW6wrz#zE$WUiQ!!%N(8T`EMi
zTo_;t7=I_MkNw4~ezd~ZH)z1M5K%KEcv0oHRd5`!P{%{t03{4ALLL=vV&leO5=k8W
zI+6p-1zpF4753`z@DjLpXs`s`!j9^%yjR$bGh`Q<BaY{~Ld?Le55PBt83L?4juM*a
z!mC6uL)K{x6+B3dmtTPAy_oSd7*dZO#<L+Pr@g!myNz`W0|LW34rqo8W551MrLzPF
zoxvv;Vf)!;ldV%w2%84{$D$BhsYn#NCJ>Bp3F|-DK^lsJ5190XgH6~uXqL2;iQprc
zEq8gG<)IdV%VDk$*N2$S;$z?YEfhtuyeJPMZiSk*gRX?b7ETW4xR^oI15X?GmJ~FU
z7j3xk4&%(`ck8Q55xa|fJtMZ~(XIe@(C%}!5OCPV;20ptL4e2v;e&`5c$5rdo?@@@
zN1-2>xP|347NYPXAc9%%h!iUk(bO*6_DtajBKJUp!_C$1M&BB;JdB0O5UteEG!yzl
z&zBr2)kR_wa&)lPqaO^s-!q~jeKFv&^AF#NVMXLaq~3hp?srP!LjC&U2;QM<N{1Gp
zqwN&zXF2=|+}aRJxc^BvL^%w9kTAh>!h^Evgc9L@d5)f><$<D!T`UN@o6XR^CV`^G
zrDlD#)r?3MjbjhyupiKXMxYA;x~F_EkWmUw(@=s>u+<p40u$gcx=D_th_pmfA<p_Y
z^qYxuJ}EBv#NhlxQW#KWju??MG6W6QSXZ7zor6FR^B8hA$Ur8hcZyS32^&I8P%+$~
z3o3&z6pnq~mK3Zq-d^2v&Z0{yPDuSNSJ>z5OuQ5y&BX0EqC~Fkf~OG?GUJPlBObN{
z(}5vsJDldl-V#O>2i(We2<^h?6Fs5_F-=7CJR5_eCr4t4FM1xwqd}=pMNNzv;w(LU
zfG7A@yOr_tM+L*d(pp}g{YW(M7irO0VPoSx7mx5}>2Qf2@#cAQftj$RBZ{`PlbawK
z;)<{&=0!IK$YnW+#kO$Zt}wlm7~<0h3Mrf=c%Bkg!V&3LKdbD|G<7xEbz*bTwp_DL
zQY`+LY-<*Qo4N)|fdv9mF{JC5W!XGlwB7s@w#S&;XF&mY9_!oBbMY>gUyzfy4ID7;
zJ@EBlejsA`BQ|39u@T0BIL0N<^UvsB%p2&DZLVVER`3CrxiO}UxQxTZkujs5cfFAz
z)))5J*!YWsc0#nwqhhaRVvb^k*qkWh@dWG_*T5vrGs~7mliA(a%+ks7oyGiq`z4Ae
zu_Fw=u~Oo@>|G37TXx0sh}O^#Zj?@DGoFVE(=orh580U9d5&E)=^?pUzpaa>N0x5j
zgSKLK^(nuGP;C!SLPrn6O?8tco{)HM2vQ5;kL2o~cJtn8FC-6tzu{)St{gG)!$#Q9
zV%EvLa2suQb~Orx;1~MN-|RAAnJh=HL-{~+`Uq@1jg10jbC3c`h_6w^$-{D~>taw2
zA*KZ^Cmu$zZNn<xW1GwLU9J~frc>+*#o=anh?soU8;atP#EyD>MBP;mFQMSA=kycG
zR%Z9Qz3v7phEPFLdsuGItu+^6v&!atrVy`t#Ln#B%zBGW;#$Ot&RCLltcdBI!KREh
z>t0L_)7<NBI~y<RaOR6?t0UhxV8WLkiI&Sh6Wz^^L`H7^PRVp1A3`Ss1AS7zdoIVn
zS~B!r-j}yNQ{n^WvmE<p*e0IACW5Ve+w=O9GJjV8odI3y_s(NtY~=qRSL@v8;h`6L
z^Iv^@^CHBYMuuaphzVq*$6rGb;MP7^CTsq1AUC2OJ8?^_)zWsz`Vc(+5i3TXXe^ff
zrd7Btu_<pP5RMUH<ZaBGrrWfdLT00;U{s<h2$3OrB*3AE;V}~3$kT;rpDqpVgA<*2
z`Y3jnjBq&GTrv+6ZQQf7CEf=oI4uIH+eg&;CkOcJ-Y*Y$v3_qe0xF^1+<8tmFc}8x
z(X~4=46AWW9`Fz&Q>0#R4{Cqu{mxbdbzVFA8il|RbV8V5Fy8B0jfIcL3`2HXEG&a2
zFt#@$GMSa1K}f+slxz@++Cvzn2Pi9rDE7|4>8H5L;|P;Ijt3ctQ6NCGn_>uudEbJE
zfPG{qA33^0-fb(-4V>h6Yssb9Jk_70keMs=yQ2`B1R`cUqGLnHb21_vFw?RlVDHcu
z_*g^3t}h68{AEaP%`o<w6+)D%ogyshB*Gi_4n-{sA*6@x?^z<-4Lqz@Gh}^dDJGPn
z5KP}lNf_kmcnMlsFMz)`g#^UJ(-{-|<!K8Ui)0U>g+5(;2&2Gu(-2UsE%qgTWZQwo
zi4m@>9N>d$Uh?-faXo~f1ncGXs&Nuxf!#Qg0~*!(;b@;!f0}p6_2(ZcIS*S*TpwR+
z*#iFLCef6Q!H>(9a>~VCC}x@|jbSYli-T4QVIc?MDnw$^3&1vP<mr>JF=#JjLsCYH
zwlZ=Q(H}4jY_XjY1af*g7jh#-p`VF^?jFAFfch8$gS%8PtG)wLP~LzQImx+x${pfg
zy=9Ti>u+IT1=sb*bCOO2we2>F>1l}E(vCE-NsOgf;Wj+xY_ROe2!{McsS@Kg(&9#z
z7G2(VcN>B_w0YHgMZ}s!7{W4Oh@RTIM8j<=BN>F(JZ#!|<(X)&3pw?=M=aTUrC{ZO
z3S5f8D0Fqd>*|Q}3K((<7$I5&slUAs5}JeJ=skppl_)1hEhl8RCqhkyHo2+OO1PVj
zB9!Nz%Vf$SKy%~Kmy1GEreI~;i--Vjv=Eeb^aTnpShO2W;S1cnIL5KNO!P`NgDB99
zLr4Z3L^$&(Nv93b%Ov(;O3_{_1gT?>4;9lF8uVSjCkvVqA+Jv#!YtJF=VZvL9};|+
zLUCDa_}a;JZ}<z{(r#jE{rPjB-r_ci2!p}Xx)*Pn+<Q~ge(T<7`_bPNvnMU+vJyhj
zM-hozC}!I&ycgHB0ONF4&W8sxX^I0u(;j9vxSATV1qG}_EUHURhao6ZGQ~$Sue+zL
z1&L7^9K{jSGJ$mgd!?L`+W_g77U3P5@(^Tzo&@=JAHt#|{d&vmZdAnXDraTfh(+4s
z3D4MX9p}dWW?8lj0dKH%V&hi3ZAZYoP5BH30pogBr(H^dBeA2BLm?;_EH+fVkQ&mk
zncPJXj#Ywicr2_p!1w=%E(^=_n6pn#4JGRla}w_AkYirG7s^P2;&r%+s!HmAyq_Xn
z);bufcnFEsVnRBEp70!t_CuLu^dU|L8*2}?ER~lfY(UEC;^Cr+y=M?VEL9l4!*Wi-
z`a|I^!8zoK;N9UO79gFS0y~}s>G^%ITfs#grUI3SDIBPvoYMeJR!Tm);aznnK0;q8
zcvwF1!GlJJ*K2&b@%^-U=%=5re4pU|^}kQ>x%;1fz6<}F_&?vDe_p45QA}t5#hp7?
z<vR!K%AXfFM9o~6?;MQV*+=yQb&KrkuO)20>aQhyZpu$Cl)skn#@DO9mT-T(^0frS
z7!^c-{H;icox`L~kxk0{KUjKX@zJ}ZFym=gA<R?Q_83@X;7>uUE37=GGsT0|4QsPO
z*SEO4Vmh@Wa~0X9EX9}qFich>0okL9?;MbQI{~P5fJz3t4^#pX*vehyr1%{@IxHnP
z`EH6;r2WKlK7`%j0t4o-YT>fNlMRoi;8*J|!Vw_`-#cwcaLq-Bg@wK_BChld8Z#hF
z1gH1Ocy{jcRrvC;FyP5~Jk!Kp7neN8?l7V^IeP&9Z}*X?x5bMtJEkOWroAHO7IG}*
zEiOz;>f2;Kfr5*kfj#^*2`)tr7(vAfDi;R9GzuDE3MvS@)Zyu=C#93vJK%FY!f!%+
z5A~P~6Bl&E1$S)d4^Y=ZG!9!d>ZI5Upp#k_V~)kjgc8H>tpg?Gs&JB^t#Gdkj*0<A
zZ#s}rG4%}K`mCM}<q^-0!F#B~Gyko-2pux!;of63U8zC+vj>H`BG{3H(?ajS>_t$`
ze{PQrA8=3*)uR0k40}F$FhH1eQcQU|hEUKd>V|wzPuLYl7-X-Fp5ZX4c*|#<A$7mQ
za4k$%QGg1Qb>zex%?qoDqAVHzFAsnzc&`>aHQ@bXqkou@A8fAD9MKSD0|Sa?3D!vz
zuE3)p3qKBGCtx}WqiGJBPDrP1V!+z5fSUs26``&aJW2<Sv)WUNKQ!{rEe4{2V3r{m
zI=VWpC+lSF(#nV3$lbTfAGBR#g)SGJ#bUeAGXh4z&D{cHsc~s20Yg7!Yd2B9DG}Rr
zgca>ra>QIg!;@ncjzzjm>`h%2&xbnfCdqMCU6dVfCA5{gg~tqR+HB@bRo#a8u2}zP
z7R0bm$$;moZ#9@@jKW}pFfG!V>q3G`TBHf`Yr_rbH4vl`mdHE|T-LCgHe-|%S_r$e
zz!GfGMohKt?&oAR1c!oy7v>;X!ofe)5h+H6SdIsbAqKAU0QivLVg1qcdm+IoQ9$Gg
z4m38%fcXTV3V_0pG6z!<3joN)XrX27x)K<6&)h83m*5kF!5Cm2vXdgu^%5AU@YEUs
zgVsdp#uft|VJP6TV_XdEyJ<t50DYi@V{(RZYKLYCnT|_J0FQ)_=cAx1sOUfvfB<qF
zNk#|@(<&vRUReM3Uw|V>7aF4!y4ONZvJpEl(B(!$!OY&s4A>p?%pWZ{T6i->ppXCn
zUz~k9j)-m8bi}==qaQr53R4kXQK2<FVeHi-O2`pYVc`K0;id>)PAhXt3F$Ee^MMb6
zf71PCG1<`&&1BllRPIgz_qpFI!eJpiB63kDCKxIlisdI4Pz#0-QAGua3c{Tn`@T&f
zrs3MA=`M^SoAfTCU|i(bg2cf<ooL_e>i$L{FP7I3^*|BLgJG&jE3lc;$Bkx^peo^y
z?z<T}ONfN`T9{U(p+LT?V*bZs>cyU1!D0$XKonEv0s_~r0x3#i2b>EIN4aP4kOOJp
zC}1jKEb%OahjQ3xEx}?3sxio%6K3Yv$3KQfX95Lm4ghtk?vQE(IhAw&?*(7@iTL9~
zoPv!p0f-8?WR&KM51RBx*e~R(V^Z4!igh#at_1{IV=sLU8Y7}1HXm7vHZ@aG!+4j!
zIh^t!)=;$Ie-vCwj>b&zY6YV=id-lnY|%iQsN)!_2q8s|fFP5_6<Y%>ejVf>%(e<S
zXvLBASpV-Kd~eWeswp|S8D$Q~ObzX>V$U*?Y}c@WOHA14s<&a>G*eqF3M&}3O(O=a
z8IhvpthBYtq)(+a`t`tg1#g6-%~e85y_97_Z(E{rPF@Njtq4EL61SCj<ylnu9Ymi?
z5VsVUJPR7bzsDl$cwh@@6oi37AR_>!py7d+0PXnd$0F@{v<EX$iaeYgQU&4et=e6d
za+9!DZ^fGm0xWC@Im~kK<$baGu#oCNzL4;e&#`k10*6N|64b<I%$iCITJvKdZv{hr
z!GQs5Stvgg#W0n7(3+n&F^G-h47{PYN)&1N&`qQ&X^bOaUc^)xr~rTb>8aov3<q~m
zjTq|FQYlO0j(O>)qFY=$Q8a;MltT-c08qBy+Kw$10-nMP!j`CxrU*sY+x{*MGFR|C
z8I^pwET<xgN*|`uc>auAN+;>0<jJK`=8lgoVAKab|A1G|qQfd4z^ey|(u_|jz4;>0
z>oY?9pC!Ra;T{u=6b}1*5~!-p+GX3UWIL~^`+;L68~Z7)P+55E!|#Ng`EE$4!Yv?O
z;i3OVC$X0J0$FU-p|LB)g~$*(+LFYfQXE&8xO*{G5L&-q_2x9iyk~-{Y)Hu@(48<O
zaO~^>h&CLb2;z<s)I$<Bt+yEbQ$_e61|$c05+l(?b7}(_0HQ5KG`YwcB@-FQ0y*@d
zC>2+tV0lKye`gf3=lZLXE|^Mzb|tpJ94Tq9=Y6H^Q|Pxk2{XSv1vMS)>too+2R$HS
zbwMXo(qW=WjH&`9jEBczp|ucxpSrwme^S+&tp~NW);*?)@0K*MmwBdv;gPGmE6UvX
zqNM)5=o&8>eNNrq7*yE6KGmhQW=^UaB5$m5XTHQ5Id;+cRTiF(dXGeh7R#~dUFNUt
zNS^O7Zdc9IR;j1?e34Dr%QaPb7J|3r`3_d@<Bl)B2cxkBQ_s*$NRx}r$9S((4+-iD
zh?!<?QL!|Me%1=+Vl-U19pU#QPw}fYO6k=U=5M_HV!ch5@+Q~Ag63Cief2$B^S%!2
zp615=X5@rvmGUo?7~Zx)d|IY=kle>su9Blm+`ovOSo~m}9u$7UT*2-svZD?8jN~5W
z1{EHa_1lx((XFwDg%_e754vVYeCbQ<o|hUcg*OCEvu?cmwCGal6Uh#0`8l(?bkOvu
zOr`VgV^JTE?qWxWu9;|fdB;bJOE3IhdkRvoBj{J}dET&DuW7?ey1LRwwE7Mc;gaUg
z;(EJS%-)CHk-D)HdJ<vFo$wx9_$!5Y`annhfev+9!E8}q`6j!-to6n36wM7*k9N}P
zvU^TgCFVg^VTS`C-Kz6E<F_=*7Z7#93yixFMqA6*=hrXnw|~kO?vnGbaRj2GvD`j6
z@#M<HlMkoe10Sd#?&zpLq%~+QUW?t5Z^2HuhNHWSO((3KYzJ$z*4h>$`0<C|EsVPG
zH3YRj+=Zt;Y4!undr4dN;BTA1Wi_9%igrKSVeib`m(R8zeGyE5nTR2pdc9t+8z>S7
zm{zdt=GAOZv4yR*%p<LQz{>2jfb!82>)F9rJM2^#+GTK5Z&=OzsrFaawsfm~)`k`>
z_Q>O$WlwPX5c`uSp1yt8?G$K3%*fr^UH@Fe(5-9m`;}W0$(v1^w{T-!Ay3aC($<dB
z2{5G}t(4+D8oja?`|B6VbJ+0?G!L5fg$~4Vww>2BvxzYa8!WS*&D>Xdv7LjO;zeo@
zHeV^rYrLV3c6(cRTX@--wN}fvmeK|W-r3J&j_|d%k<smg4A>f2sJg@TpaSDVf}jqo
z!^^Z~tZ#%{>v^`llrQoAl3b8m_AT1~?b{b&`&7UCoV>E3zD&u`$JTsh(;5}1owj~r
zY3rdP#<9O*ztvJ)%UCNLV21H+L~bDnKmMbeEqXqTZH4G4tlmA`obFum0oAta&oqOo
zR;$hWjSJ1zZ@g*QcYcb*uBn~XwOQTK2HEXispnQU5Lt`U$***7D|FTutkw+!#kI|A
zGp&}~R_xLDvvmmYl|YsSbp{g|yJiRmRnT>$&~%X9Yw?~=+cU87^woSnAJ6Ce?H{iD
zVQF7{x12lWj$)Taa`Diuu{8x_^Qvvyfd}oD1M7>8A1p%fc;nsQv<G;EM2>zM$MM!P
zlmFp+Sfe5mgj@AIRmFB!{QjWxe5bbVF-y_TAev`2#jW_xc$@VC;sx0B*&r*6RS>UY
z0u?&!R_m{<Z(3*UgGKvHMzc>?cKi%<@^04G!0=EVsv9(f@mGI@Wy}JErtz#Tx3S&%
zm-#V%mbV{WzyI60J^5o8cgC{zNUVEk@fxuBsaq2V9@utZNqs?U{A2b;p}5{^&3xAC
zgzo7&x+lK}kH<MCvoQAi3k3l?8!&ft2!W;Fr7r%wTK|Zu)xBe_^}uS=NOu-3i=|e_
zt+jZwY@dwJXe7IzT-;FaWe=!$*0XJxeO+s{-_)#@{JN6W!dvWOW`Ol{mRfkG%l5TE
zeHdeo_C5882E(cVB1S+<Qya_d%zvu%=i@y8a%oqzMSfu<iv4;0?j}wj#2VamFDsbp
zwnFog&gLa&noI0Ec%?mlruf<X1(sjWu*>;rnPara9yURQjS%ZH{OqEq-(B_0dxvhP
zUxHk&D_V<BXz|C=_t<MKx402OjZHiT&$QbePBtKFpl=)Q+}3Heruo@)foINGZ(7CH
z{F&koUSxf`Z53HJ+&?G_e=(&QQ-7oYdAIxQB5Ufjdrp=P@dj+-EcN`z7-tLD=ITl^
z9`vBXlPl|olWX3Qc=Cbz;Rm;!wtlqXmEzZ-lQLb_9;@$y&6>~HcBf4b`mk|C_||XY
zy^;t=7XV#Pv*FJ4aPzhf%c_5*^Nh9HGB#w^ozUAdY_zE@^Ri(zj^h3Mt**OF?jDM*
zlGm`W7^<nJ&se`-yuh?|Amo*i%m&LYeTQ|Q%$&4$viNEkC$6wUA5@(%Bv%bD(|XRN
zA7N+g0fuJ>*lyERS|9JV*By$xr)VfXs6P+or6z_xmS95$9#>{M?9Bh4IRlx^pJC6~
z8*C_h=rh9*lyjNii^SvPod8tTV+We;`hsaMDVPuLu-FNZ&|-CWVp(akvOD7O)p3PZ
z!Ca_8Z_v|U(K@y*Ik04d_4UGfw#<6zf>m74GKGxkL5(y*p^(9dNj(Ug22u_#Wzt2A
z1N8HLmT%xkN4U|1H=mF3+uw}y7fZ6c8#_OjU|Oidt5&TU{^$341=Xy7$@)7jGhSd2
zTgKM2)}x2mex8>423Vs^+=1EOI(joHV8|>0R+XOiPMfFABbK_>+F%{FHrUNw*2auc
zj9J~GI;qYczy|)sL#qZir<V+OsOp0Ui(Te=Yfo{l{mPH51<i%L*8^EujfW1jE|zBm
zDc?c0=R%=CB(&OgG2cDFvv2bJZY(3k(*9QC_wpw>77?~vR#`XnlU!ej->W{=(Xs8c
z`6lY&fW>N0@ui~mx^=dA*6y;cJ!}ta`Ve;Z*(1LR8k}Ku7ZeG)g5FUJopwF6b^Vf9
z(OPd6@5VaXB#V}XcO?~Q+a<Eztv<Q(k$b<ARMYBd>y1v9Ie(_u_aQ5Ns3>LjGq2U=
zQY$TYG#1@ZQ3wb@icXuueao~~v&-&7-kv<;FWz@_on74DYxIQ@1}(PvReJ8pTXnT-
zTjAsP9x&5Oj&v?#nICNUROY2Zrlr(aC^pIm8AibHpf--3rSIinq{C2x5TE+8x;btB
zt`>)Za>CL&Evwj+Il)Hb>*F$ZZy_L-TkI|No;1@#o!i&}v#T{zDl``|uZ&nNnZ{?B
zvF;F);|JMEONN93Y5EDn+Rxl;t=nuFMhow0&*x8O8uD0wn&KDs^Hz>88L*uDh(4gN
zN-Xvc#LNU5?#L|Z`Ra!B2<u}{Sm_U0>vn>VK3CQgU&fNZQD%I-s*(WF($ImmuetFj
z8pJ1!1z|0Fv8&jevF-ct#w0%3fb#UZxow(Q6~<Yy@uYRIc(k~#VB4>7=+X7e>%qLL
zK!*BTk8xf{10lDSFy1fT$6MrM_78K<v3<~@c$Gs|@ye4La+sFX3Z0q1vyT)qXEO!X
zSI8?OhXHbkHTdYh@d&l60-&Xr9MDWG1?l0=b<b;$S&jS481om~OHB*gECXH-io$9N
z*E2S3>f2b)1xstS4;4>Zhpg35IM#-uK{gS$$$G+Amf<j?#j{D<$uP;}%=b!Cc4z)X
z=49rFqx%-t@u<}6s)LK`pH$Zjf5N;ME!Uqme{x1^O`ku5g|~&#%MJDh)<erMW-aM5
zQ5d`RyT0znGC=N6n!ygkB0)%RT?domPPrlDVnb(>6<^>x$l!)ofQgtWjCl4dSbePv
zMf)feK@apiOv*h0!cJIMhI!-jjJO1$=Ew1@??t&SpZmhXR(|M-sQwyoR(D0!Rf92X
zH^O@o8?2@su!e!#g<=s%7F&RCYo;Bdanjn!zGt-;5t<$Q@AMsa*EhO+Eml9=+*N;|
zGku_QS!c_V`X5;F9TuKWueV>dn>&iol*Wsnm90)!j_sCX$9d9yGTD&uhVD%FcwVvC
z!mzgg$of#R@d@~4a{LfK2^)fX#M3vjPXMHj!w)gcuKj+_PWD-5w`H;?N+tH{6Rqoh
z8po@|h{fesHn_WP)$6;Tgu4Hg`kvvAuF@;R_AA;m#lACn?F=h%OcDgCIHWxG)(_uF
zO5cHQ@s%;8z0h2*E%|{tykuEtYcuv;odAE^*wMC()r9AnHb%!qFadTG1l>%-;@)6o
zN=2(LkL3hoR&4w%)(Bswf$K$a2mgqN?H2K(2Rj_Fo1~X_pItY)A0J&{yYSu;wsgvP
zTPAAXTWGQ&1zP?`_8I$A_IIrB@V@v66Fjcyq}iA4AZb)d+UpC=X^6rB&Him`$wBP`
zOaKcgt%G`5D6;HA&DeogkJ}L#mGM}+dpNF>Np-;7cCc_rd#1T1(~^gQooUSPw8TAF
zNMH)A^Mj+bLP72N?$se}n78y1+hFe$n--q14zZI*$Dd&N=z@MATqlp~vP@P&_kmdA
zsZYY|sW1GXe&nky-nxUuZx$Esw|LVb2%*#miw|#L+T(}TZ?uZpcG&2Ax4v8N_n^my
z)#d7W)m*M!P&@8wUi`-$=he;)+NV3VYZscEw`*+=ZZGUGSEXOf#M@YQXB;nv!EAt&
z2tx(3)O{eHM!yG^bSz`1>(6c&FG6D#_mqzDHhzqq%<qKrbCkR;zf<aZr!H0d4p<u5
zGR?vgnknUv+w$ssle{B;D1Ua{)3--pF7Jx=db{QB;g$7ICf7W*sbSlJ2kQ?!n11G~
zUgMWwIU23`?;(oxDsMW;cEURuX!%0f-x!4!%Rl$McfQzGe6ig3PJO3-NcWk$T;0*}
zh)Gm0If2XXs-4Z-JO0yyZR+yQ6CEc`w=MaAw$^I8kBw$`z)N@`R0sPT&)-zHn`L_r
zEYUkQbT<B-{l}d<izlonifj4HZ1>TZ*)iS@17as1$Om0w@$y_+=ycyps(%IR+#1%{
zz%ZsV7{pKJ+w(oZy76h=-OlB@Lo(i`fI-mxWU?z=*nx?y4_ZfBO6#6r>kcyLo0nNX
zaTPz~dH(9at}lE^?$2SJ$KC}xJbdJqiv*WP_<5q32KWQ&a?PjsC#HE%$MVij>o-2J
z<j&u11|Q7kA7hNo`-;V)+ZgS{WX9X}q203EfC)YPiS&U7A-)~IU2L_x;HrP82+#QJ
zQLr7O+zzJ*$5IxCbuY<Pd5C4&wt{{kU3z^uv)Nj&Sq9d+xFr>POQY-A+S0dg@7oC*
z1>Yj-Lc9ykyWX|=-lrDRL^;#kX&yLZp3VHo{*iU&=nj6e^jZ5&&Uf?dI3L&rkFuKP
zbEif&W}3)F=kQ}6(c3v5l-vV>-eGQ5?*ZNPQ~$`4^BpGcIzMf0*G|;$NPhw^!)0Mc
zHtqDMY8~E7ptlc_?$FjQ@I8H`&}t2zJpyvg{7!n6DtnT6j^m;HILlXr>e2|q;v>Jl
z;0?plfd=U!R_x+EGKppUm@yt_FWfHg#KS!m%5pH47>c#0pZY*oJuLN}$F*1P#s-l+
z_HMhE^+SeyTXZ}xe|ukR?%cv)crnJ`{!A6I=XD)nh_L#Q`iS~n^+HF-@+H3uu~wHq
z_{W`(s6X*%b+fs=vu*gE^qs#Cy$v^e2TftQdz9Yl%$HY$;kJ80aL)mFx+g6CLJ_(Z
ztL2;A-c2n3EdL(7Uj9OR@#SEE+qrvjao`Hpi?dj?&z2hUR<8Z1#di<147C3FuMJ>Z
z4c=VUL9V_A6Zol3_deCpwax3WGTZD87CcJ}%T4~x3}`-<C#i179-2RqPq{z6DA1sI
z{pl)-zl#ALKr|qXDQrIC|6q_I+TwQgCmrS|we6j49iJ@R`Q6iE(|yIJc3v0nbXm+L
zZ6DKP4YBmlon6~{mh^nRFLPdFJ!jxMAGJXk{Cddo(cV&j=}^8M(M=L3{O*LC2V2!6
z%lnAdGQ6kI(nry2EH#LL9?GADcFVlU7q&$AJmDf5g^fH2aKi9=a&cn#fka`oKMxL=
zEqhwb#*aW_LG^>$3wG&c_9}moWJ*3}oZG+fSa}Bf)A-!i{{AA(;E9KE-i2icn)(7J
zvi5-`B;FS=kC$vj+KDA6mOyoBZT0u0dzmqsm0_C4;ls!-LeEbo@kT=-iLe_CG_y55
zUMRLUA1oGlsd$X<u*Z+WKI8rWm#z1Kj_S(Je1%%=A$fi?Ep@e1t<mzJ%T-a)7znf{
zOW}Dk)YYldRq0CA5Ve=WA~WquA#1e!r%f~-jfa;}m5#)fxJYe}rk~Qoa*!xwh3B>#
zhw;Mwn8e^KxW)yv87(g*i#2Hz#gY9;y7A+A;eI6Ze*2ctANL?38yl(W+<ng8-~RTu
z_X%Wc_v!K}3RhmXaOf_L#wDxAdQBJbT+LC{sm5&{*E>Rmv@ZCc*KuPr@o1#Ja%X&3
zVfyz5rk~^#_kLu(I&&(1QF7K>!9CkP>WuqcrE3Ad-P3g+kE}Ct-9K9Ax9Cf);Mj)i
z{M2G?*NqR1H`QL_N#j{u^c^d;#r#3~l|}2DenP#2JmR5f{E0#%6jS{Pn3%n_+N>g%
zU6h^a>&qM4ZF%JGVecpu4rewvs>AJ8ws1cwq&(g*AGu(@rsKxwl5NlX(Hm}{NBdn8
zt1&%XtR`t@pu|qYXe4KDJh|6qnp#m=%{PF8z%_zjMlA;OJk}dHcA;ACdXw*cJ@fA8
zlWUIf(~qtgcfrN9M=`FXq-<$U@n@Xk@JsBVF%x^zcrvyn*YJ3DyE#AI*(*`0<bS18
zlWdb-{2IeY_(=9nry7l!;Y>$ASOk5X(|Swa^B^w|Ir6kQSYAF8lsEM1o~{&9&1kGG
z8pzuwbi3CaUGNwDF6Z65UR|d3i9B|So@P9jreT^{?aXW6XKpc!nTt248;eeGRdqOr
z_0T<=ryAy-$Bumc<;mqpRNlwGGrzJ_@s#6*H{$Y|EYPqTJ~d>ee2IN##I~6NLsCz(
zvHPsY0Ue#$chrN)&eB}fd2+PsCeTX#2~u%mmoZ&0sJB-DIHYTfZ3Pz<hz9ds3pkJ7
zJ<q#BgkfKceff;K<$YYHD+_0fWD+KuIZ4!->$0zSFfd28KQ{5bLz4_#8v=J69z0yw
ziA&#HYn=Eu5)k4Y#SU{e{m5)7o%4>`IL7d2A0-AqynfOD>CT!(AB_*46;5%x@jS*A
z-)!8mSn>zPLDgw&F&jQh5s*4#f0KU2YzARPI!lQpv^j8>Rl6IaHsl5`-y@7vag3le
zug>UuN?}iL+&@$j1Iur`)~bWP@3ja?P)=qWUpEdvirZ@PhWflauB!%@?5P(YatQ<W
zQa%x#t*({Or)m#R=b-aXnQcqWhx{-#Re_ux`x5@{ip%fld)1jdhkn)2|LUjz>&ofH
zVG{Pj=+9ysWIuC!KeMu64%3)7=DRy%q3_yaK3UwF-d!cgTqj00c-1`xB1ID(Wb^R`
z&O`5X>=~U&-?V1OuKLayb*ps9?h3|r7#xT86I(MJ<z)*?M3Ml!44(O>#<s$#F6F>k
zgUI;H?-K58#NJ7Un?+-1<Mk&tOSY0OKKH_OwwKSdxgVM5%rj)qXUSHE`fXzHP(Lp*
z4v{kPa@{)2@zy_IvGIa?T~6^xxW(AS7F+oF>_KeJ_WmH7v$kjZj1Tb8nEB>Ui+8M!
z6cm=t@2VtyR*Cq9=pcBnar%jDE#POGM4`}oGktdP7H{P#+v^V&g05ihp6AZtq~CK(
z@}8ELE$Ky}aycQ4En3D-({&cegWROuS!zem+Z=e~iH}?NxB`nuPDh^@L_Oa)y|eMe
z&g{PF%^>&QnN*uWaC%dpRgbBR*H>C_`@BQmjnV=ix1*8uOF#X0RjbAh{TGp<k;O_(
z`hewQ=RPoHx3f3<WUS!>wtH&(V&}H49nGC3HP`7jC(J!GQ}suqi1j5SjduZpj9%j-
zt3S7xUQFMD<0Shn9di2ZL*Pu_28igGhZkF3Hrso44VTw=%H3v4YM)#rE_=zqYYAH1
zWRrJgV({H)%Lo-p!N@Xo0Vq<t`D8tNtC4K;R=UUfTN3vUJ*G<F9k7mYXddyQZoKv5
z^=|u5U;2lu3zq~6ZqR51c7=GFr31YzW2@!h#<r#o$e(y3^Nsxf7Dd@aABJ_!*T2vB
zAON=HPSc&~>26X()r%u*yU>hJZGOtfw|Ia+Y(9?V``!O(R0dUV(}fmmj8sA;T7rQ<
zAGU{V=S<x!ry0kwBMLH{GUB^<m*xwhm3#kIEm3m0<t(XN>Q-<!kdVv^gi9U|-im&_
zCX?WKJ^SllT3K*@8H8Z!>xQHZSov{$nIsmuB*$7}GQc|Kcf4XY^y<Wrs_S9B!qFbi
z(@Nh|JH0dBc+!;oZQ9xf^;7g637U(}Q~ot?-t8~RV#SRQ_6Q`w)D+uR4b6%hrwiCQ
z4S&^QkKv9qWYK~PJMBY5w0qZFx+ur<^&4W**>BWNZ|*m0C7&>iXVfz~w%E}Fr!wZZ
zJG@%Z=j|t7IV^Z{^5Zpl^K|t6W2<JC6pG-1Um;M5HCZ=)Opf*zqnRUaSq;}^<y*|B
z)7y&?&RkvqHUv+YBhS{<khYRT)%5hr4xhe|Dvt8jg@ih!`+4(+!eAwDB#7S71nM;>
z8{duJW{(-ug_bn6%uz@%xZp#YC&giCULZ~I4%->~Hzvq-2j8cUWLs2-u+6(>9_LKu
z8Xst!p~`Yq)8<#s9q&0faas7$D7oY0wY3(nT@BXZxn=|5P{oT21S4YI!Ikrmi{`WB
z8+*GCJkI~=uukq(a}R2Ecan2mLm$pSwL8eSM&jvdBRyjUc$T}S1|&UYXWTxARH~f#
zN}hAW4!}ukk2TAcw2^fi&i8fe&!H*%wesEOjdG~@PS$>JLO*n`E?WB>+0@bKPT>ct
zjp(j?@t^G~b~hGdKQv#^eMO1@8HmLN-RIyy?0)wUA3$|Z_W9du0om(+^-C)oJ&a$}
zgtuDqA!f(oTaB$*b>IV|FZFo#$=uWFt?8{6{X}(<jWz0>J?`L!!RO+$AVR?B&fcj+
z8uaP5dCl$_-J{w{9d5Y4J@H}-fqYem*yyro;Ut!^r-)*bl=R|4_~q;*vwE7mqpm($
zcVu$R`#yOxCCy*&kH=4Zb*Hhb_$$JJS$4|T?W_{gudUQNFDwg>H-xxhD)sT&q#_!<
zc3}-4!rujDV_Px``C5+3xfXRG{7>N@pSD<P`YX}>woZ2XAi-$<ZPH}PDW+Ae#LZam
zqV<^BcDXIxdPBj%`FC7<-0u&_8p}v*ZZRmYHC*m`zr9aoEDQ|yIS<3x++|-1+P&dJ
zZmDi;qP;G`SR~vKC5+lBc*_${q>DSso@|@Wr0$y3a_0pC^6h}#!~PWyE+QZ+xl(tn
z_4dTEbs1ILzh4R1%NZ4$+xVGbkT<cb$sO_4#;4g>o4Gv;{v^xjj2-xW>-r~scBlK5
zh!EIEW!k~e-FUR7ar2Z>TeND0f7Qio^F4F1%_FNa?<w36tsvnMC2$4(F6&<xx0Z`%
zjpR}<XwzM?dxAnfF$~9BYOl-K@2e;B%(cO5)(lqe+I(VXWAV54o!~rB1+=a+4r38>
zi{pg#v>`m$N&#6-aF>mp`0(9z!0dnDyt3%<M2{C<l4`0XQ+F)Dr(iM`Z5d#ckOz`K
z-m%gRdkwABTpbS0Wm-4j+pDLDWYie7GuhCi7Tes{au?62C2Dyka;i@JHUL}*8V@c=
z{_VciQGQgGVVMzwfwvrcLc7CFu7A`mj4r`B@9;A2=Pt8tF!oUVkK-sFb~1ly*XH3@
zr1;r5Gu<}RHr@QDPeJCEJI`w!*1T4@>dz-553f(15BY1>d~libs{nOp$v6ag3khaE
zZ@dW`*1e_sS-{E%vH9-4^uDZ`vk^z+H4G~fn|PG6s4=}+)+{io@N=`6vEL}_r_@#5
z5sdRr?vy-;0~S8_m^*gg$a1d8H;7lE^PV<hXNph_&5ck7iP0w41<HAI6s+z>BFV=l
z2495ZJW{<AR5tb1osCn!wX<vAObXYzlyQEpO(``h=mw=*N|)TjzQAxXwzrH>)-ol(
zQ@3X6*SRN36e<#-V+{uZq{0z>V0@si8-3jeQ_ox1vwf-m9=nt7IKMmE=_DgEYQ&C8
z%&MQNsVzRf&#Y|J7Zf$HphI6S2L2@%n$rcH5JRrP_Oz1@th(-yCNT;)??Qa0k5Y{k
zTBM9KRPyrQ(G%?L&vkULbuyZ-iS-nA?wVr7zqQLeX<3a$6ToMGs{N}9KL3__sx+?W
zgS)l|BHNEAJ01P_U3SN6%JHXvxXzPFVkv=A7AyPO5C{(8*U+t==D$3h!keX1Thm*L
z+s&N*rkAuIi}>%Lb$T(1>z))#hboaNio6B=562eU{ZS5C!RuovS?N;gQgD=~E+Dk!
z{))@YUzkE4HzY<+pSoKt8m<e?NsZ)?yWmH=yy)n=lh^Wzv(f4x3h)*oPyN(aYm15a
zaWh?bQ%^6Ay56h)nEX^BgvuW5*tOQrzrYCH+_z%e`<ZkYB$t5+vB|*3*}d6JYHw^S
zfMl!nG#^l5HFh25O$Zq#wJs#wHvI=+>=rxYob#LfHhtBd>xZ%cPk7$YjnZ8g&VD&U
z$!-p7j03YSBA`TT6G-bFmyoPVRBPKN6Gy7O=b{9s!T%U-oZ7J~f1<{2dZB3c>W@-)
z{Gt>i)ERY7-}UWluH=#4CCMVmBO!9@RxQfEZTs5F8dr!Bo-8{zyBCXg8WNDPYB!~d
zhR>{28GF4_+)_+Zb;UuSr*^$j2A&R7ZIbZVp)ZV{<+bezU($(%;EpX6f!puyr&2z=
zf7O<v#Y9sKw5({RTC{Pb-)+(``=cKxKA$)?j%pD)9PJnL(&(G0*Se^VtJX=s&2Ll9
zEKZVScppMuzenB}(wHObeDR<D{f4z5qaPZRssQVX!3S*3!s;2aZQoGWyP<9^>&aZh
zr>XRl#UFGGp=#Q1=ZDNaUTrnhgoe2l-pANynj6wFeI^$W3YQ>L(@Uj!-iDMR;6cI&
zye9fejx6G7oPtZH1U0sx>^@z`Uk{=<C+z=XG?VyPNC8^V4(A7vZx|SKZ~A1XVQ16k
znZ>jEH;Zkm^_)NN_i;W;lBPhOj0d+TC$Q#PIQeh>+ln<;I7~^=h31mtOICa`Uk+MX
z>uIB5Z+2@6^45686e2{O&(A$t_mD{%lczEB=HSf&kx)EFP4CG_MY?D<{)u_h`uQRa
zmD*1)1$P4IE<}2=gGp$H=Dz@@Ns~9R@X7)OVHeFwi#_}xBw&+=DvSD5-JOZa?@_QD
zoT?wszZ4%arm8_5)lK^fGdX*kYJRhLcJWcwta~&7i>zrObiv-yV<gw_t^<>QadtIp
z0xLjUk@pnvOwgI-h#S&CTVv_#S$Ny*vqI!<$sPDKZBg2fcB#bfNF6Pp?8pJLirTQ9
zb|8ExF{4?FFZg%h^?c|maE73Z$2{*Bj_Pio{J*NjR!+aR&rpw=JLKg8=k7%0N>rc)
zwN#)Llx?l1@GYg(X1(z;Wjmb`(%(5;k`x$6@cFTc%=z2L*7)6P{wh&>e|6OU1xT=s
z*~Df@0vNG2<7pBER@^|Aus18jr9D)4!``Fvd9?L>q3VuoAzh^|&MT_ug=S*KRg5?v
z9OB{P330mKd2|)!5F?pb=!irOP*6z45a)FvAa$D;N?lG%AmOIYM0J6HYEykZ72Ulx
z`(%0PS<k)vs+aa|=|lEio1ZEHlrwr)ib-GKvi|U`2iG1`ib-J%&B8_Vo5PyTk{B4z
z5M$t?rN$I{+B$I1dLW^aeuU&tS4X3hO(QRH)HYDVi&P*coAK<+ulmhr{eIQ&P%?8b
z1@il-_ioQ}2wfmrhv-Z?p5kw7h6zzFmuh^M9zs=eLocAwX>!|LapOaiB&H*U6ZMP>
zsy~_Nsj$<JOlq{QZW|gy9b5yO^p*CP<QZOb-#T_XvYw&*<TutF&1ETTWdk`Ku~Q6b
zu~EAf-Zl$GncI@vYQ17oG4zx6{t`NlA-HGh381~(PMf-lym~mNGU`>tI4$~;H?HqG
z<Tf}$Z*J0srCWtYWk0J5qs({FBAb{)TIM>(LQq5sd8Y1sRGbLj$D@P0rZ%5vlh|+T
ztJ=8*aS_1Oqz>75atE|Ox8J)m`QD4vK-cCui=~y-$z$bV4OCM3BO<aJC6JJ?w<xH|
zK0pxk>ytUL<3SaPC~6xxR}Kj9n;p6nK(u#LF_ncV)@><@H@Zb-N(2uZ($y0b)K$8o
z$yn}#UFyA}5x~caWF?dCBBEf(=#2ns-RW|!U{PExMC=5I0HAm}il>Rzp4?MgKb5kN
z7pM~jypGf6W$Zq6uf$>R6OQ1LFo2TRMAqjueX*6r3N9Fm3Jwy8D`7=Q=g`s4XBSh~
zW6#G}Z5iTQe`B3|oHDgf*gT&A@@l;s!AG>q!lnae(Q9+9<}*Inv)#J{$4^q_iA6p4
zUEs~ia>FBu26Vthebwg55uDJ8@A8-7GjLCn{;~I}Ma&$HKO9H)Kd`}$B2?l<euy@P
z2Xju{^-F>aO4q{T5V^e<J@VrE3h(LO|7G<|;!+P6LV`I??8pkFmkb7uISW2ePiHY~
zXE&?-2)xii`;vOBE?HHf^WVla1NEq(@d#A`vZ##O*bI<4MBI~TN#u~MVjM<dZT7OM
zl8rvFS4q=To9i`cJtwhp)};s*)nn07Is-&32&z3^({()3i&t|t2H(|!l+ZxT^MhU4
zE#vNjdwLR%Z7uciA4b<Ktqdu}e1=r(?~t4>*GIBe^YgLiyRVnY^Hi$g&rem&?N>vc
zUP9Vk5T!6W$d+Q1?L2Z<Lk1+$XM8HpB`V6-2!;DgN99f6Cd=M*ndT7C<6PE>VP6lU
zElZS`cN%~T+@;{OcY9*;yhv&v63n4DO;sDmzjZuCw^{SXR>ay)8^zl@4jYs-2#1Ez
zNxUg#9$UvM6~D1&gYx2xWT145jSL))K-So2vDC9!iay4H=TraP=xjW!v`XZ$`1w4V
zALP050V)$rP-M1<?{gIWc3)Ac?kQ2vbFN@5;xW$LJqkDWg{@gpF`Gy<M~iL&I#}~J
zZPX<<oZFs$**iS)aC9iTls9O%uBn}_?y4Qio4`i2`$&lt#7etrk^K)Ne9dQP0xLrL
z=)?69Kl7v2@`o^n;+iXeEaaesMfN5;lEWB3@Im(-@istL>j%&($u2cl)gD#tb#nej
z3>1iboan3tT&DG+_26r2)RrO_ICKt=Cr*Hpv1})zLOJyk!NY>P6QNcmva^Bdf|E@T
zn+St-;V3mruO}Glap48rKVWqAhUgHgooHizs=1=qG%I_L!8#|}{AO}d-@RfV1;p~x
z1)WROkQ8Jsp!?msYc0t+97JLch%>B^D1$+X@$cJXkil$KQP$vHJO0Lc-R$&rVs3ws
zq;82xwSb!e7KxS%=&_(40o~B2(cz415(GIbU>mQi^v?Q|D4Vqce+uh6sYlV&9j4ad
z@P>&Z_goUW$T8%c;%&4?OGr($%icGIrpr`SLB;5UEnZm15>--{N8$bRW0B0-un~>^
z>1(SH9k|iuj#O?ESIS<+l2j>;?Xf=NdGk)pda_$|Bz-9$`cI4Vr_4@g&Q=TRiG&Bi
z|6CL;3DO5qlN1xo`M2Iy!$m;4S|Wtq@q@!u?jS;4j?7%YH|Zt60O7=x2={N|PW2MD
zE*#bGxgwfrciTfr$ZxxzD6B{7sSpw)PbT)AOcIHq50~uOQXw6`Rq87N&pDEqa=}~h
zPS*hf)|vDFPOLR22Xj*;S^{>eC452XT4TMR#=2R4wqb9KU7OyrIOIegOgz*VG3AyZ
zbe3hNR-|W|xC2o#EMig7bdvSy9;vv8CA<A4Fc%dpsG$`Hw1)cJJ)sMu8{4R6C255r
zh4yaPXZ4GdM0RqLhc+IK@1n$p*FW)%T_>`;^eZrr@L^#KNcv!rKBCmT0vkK_(Eie#
z0G}(z%BqSr8~C|9tLIeS1h}9e3LyamxLZ+^aAp%*tpglTpu%UOf9tb;U8$t1QeUYG
zljlvGO|y#3vO^b~r_`9fd<z#p50QT(Twqseye$1$UgmQ09F0V1HHprvCT|E5!Opn-
z-hzH>;`YSEwUH_KpN9pROUeNb*t2hHPfdmGbSeHKaKUe$lu$wyHV{RD3!J}Ex?L9m
zo3Aay{*&KcjV1T}5IhvPmDP!?fEpzDr^9?U%MLzp9fXkDD!bUqDxh7YuC6R@u7n|g
zx9@4J>JWK2NkpH&2q}GtdYs_qpo>5$!6alYSm#k9GUc!W<WHsaY$2a$MCQf`ZFeiK
zxTEMUmt1m*T2cw&y12Kxyws^`MlIRLRmJ65o9>~@=X~*NN8t!KpWrL79q@c@{_*cW
zTiLYY`j!=aPy}*L&9az4RtoCLSf9pXELB`C)i^P4ETZ-+)%+Z?FK(ZwL_`&|5tlU8
z*)>p=zL`1|Ys-Gpq!sV@s9gp<hXV+MQol5gEL&6<k+AG4`D8&*j6giFOuxps^TAR8
zKJdr9?=7CEm5b#b&L7!vq~81E=!t4Ude!@0X+S!<sXP6eI^}vx&MiMY{{7$sDK^7(
zt=Go<;ZqN+z#p-zkX?lWEbhT9zr%xyj{-Eb#hx`jV8N0{bA;1-vk44)L$Rq&NBAQ9
ztY#aV?5pADZ`Gbm_UfYX%wpTAw#F=M4Jg|mXPY@k33-G8?EDT))*5gtVn%7CXndpi
zMzJw1ifX6HE3qkC7aUo6<l%`-a61zAe0@mQ*XF-0ocQXl@UwTSkJ?Nx6`GmYw#AG^
zo!XZjURvNKO90#(9w>~QjKi>&N%-)6rYZ32IEiL_V8+-~G}G7Bh1`!-PC2F-cDKw?
zPLC+&If!5xrxf2cY}T8a|Jmb!OO;!+9Yo-1A`N2OX8JxrJMu#boFcldXzsDajH765
zRg*j9i<%Qmb2u1Y#D6{qfSsz2Mb9=#V5v1ZpMsNJws>2K5BHrjc98*28=0|2EZ6$=
z$1B6uLg5D~XidX$Wa)RK#(lxe7?0;RKdO@WjZXKHpHxasM7|s00?NUcs0KyjT{g3l
z_$7e)QI&B3bghf<Q9maAp$KL>O9Tck__W<hk>Rm~c*U}_5d4j>1#r-b#NYE&#{SS=
zO1yQfdNS(Km2=(A50dzI;b8<Vl1n@7s`)Y1d{zrdr_V|%ZC|2BIW{q-3!506cKc15
zyCtKMm+G<8(<a}@VR^}nY3feNGs=|dbIx36prcHcqH&qtf5JTdN7Jcn_oKyAuU=4v
zpu;b8s0;3xrixi~`H5T>A^ly<g5VVKR`_2|kLyHx+zi>$S$%o}1agJk?!!C?4aK5(
zNBR8LzLSZxF6KIXLS&Bj+M&jjx@vbg7h#V#j?B8FO*re8|FXMN^G}2M58I61s%_cr
z2KB0G&Pm34GZ&diHFOTA77BezG1DND?BV97`g*Q-s;N1i#9Pq!l07wh;U~^L-_NjA
zJAH`4T)RgBc7kMpW<jQCgk2^^VYc9&ayO24={Xni1t{%?nw+>sJ!XegS~+(QNvfC6
z<J?)oKDfzrQGeo^Gya7Om*e+reGM`$q|13aXUL7HV<+6(d*72z!LXXZKB}~hO*3XZ
z-ECMjQzTkM=`TfpQaA;+VrV-RDi+(nH@Z*D-v4xwO!H52kNVAl&rO7K+Hh1Lt}dH)
zQOU*GI~5ggn=!w*t*o8^di%*^p1u@ZvX4~zFO#}4tbzORz^C;msvA!xk6W9%1sD4n
z#g_5UNt)r?9d5>5&<nit;Xs#UobI*l+%2uq((!B4v}OM=8+pT;?%vL$|1@Sc?^VD0
zD0gz6vCXQ)?k=SgBT(d?0b91IFxA{uleG=ok)~RXrE}RkLqWlFg)<m_%66m^gm*6+
zpEVe5v&|QDfu*$s=Z6k?o#?sjYc_5;lfWf!WSHO{m;4N*G<33hlc{s)-Tc;BWsN>~
zA=U5BvjqJ6m5Ge~XBYwg_@BJLfw!)I>|UTRaD-Q};*G=RjP;B%8b8aa*1pudId7dw
z-?3B*U3^8}&*#65&Q$u*q)mxl=J?wxRh41ys1As=i;LR#-sw_5p|^!jO#pB>BBIh@
z32$pGf;PHOYmRk5&}?m@oHX1NefU^2y)6&%TQ<=qI{){bJkY3(n`()EsZY#D9(m9@
zqAycRI*Z8IOV0E7X$JhqvvRtm`oyWFd8?`?9V^lZXg+GTE~*KYderIYKqtDtl>esE
zn-V?we01PT@KoBEF|+CJRO|Gp!vl(+RW#}O7dxHz-1pq$Zt_u@OPNi;rf1(!5I`j<
z@0@grP9kY<)n4Lo@NguPcwavkJqxw5Dd7Tw^9>EfWQCPJ=fhH!nqMvLo>goZk3YE(
z5FsTZJ%D3lVGkgDsnpMm=`5!N*~Cn@)xBuV0KC|7k#k6=<|1{GPWz!Q?;!>RZXA3m
zY6vS|Y)BV#R_absxBHDxk)gV+uR1A{_CMS@S}<`662D~M?9S1B-DGkg$S9DKv`ayt
z-`)7Vz6gopAly^!h3JtTQRIKm^){SLX6<Z;kUtRS#7Ro9+Rs1+jA(}b4J#UiE07I-
z^)GqwVOz_<v;`vO9mgual1o|5(!Ka&JI6NvrgtfkJVfKxP!J!QY#P{HFg6z@4qIto
zk1i+@KCML?y~z7@9#y!qMC+0rr>W)sd#{N3y7?1gK+Yar3c9p^h16HlrWRpfB8Mi(
zTsBB;i}8J68yZ^%AO@sbp_)abDksC*JuC4F&=ReZcvUM+b24{AdU3jYXyS5a%yzSR
zIHKuiWr83Hxij}*OX57tn5M=u0NOjD_EjBM&a0yds<W?_T2%8aAy(;TM7Kl_39yV#
z2%mUUaWuYDw^RA;^!zJSx)gHDOoF6D5AMLnzZe~2Fk<ztdfDS&i>LLlev=sR2JK0$
zXVqCBmfBaq?J=zoZPP6C<H>LU&vC<GpVM2zc1OyV<%u~LR7wO9O3&GKyy^YwD|Os>
zW;exujgm{#P9)$oGC(Id>|eTvcvr;0Kwp4bU_<gEGUFxuCFlS-fBYp49Sd+M9QEeT
z=t=LAeJ!{>5gD7j1W{QV_AoGktOgEduT6_sTy{r@ZXDdC(*%b0`*gWQk;wO*4m=}n
zOI+gsAY~?HAalH9nyu5RvMye|sw(Ja57b;PLDgv^_oT&__xJ%jZgr@?)j><D87*r3
zF=e&!uB9iBr(Rgy;S~mkHnBo0RCyHcPP;9jwBW^KFN?m4L7ET8y{R3w`OVYyFMOGP
zCOgYm%TW!Bt6NQChBQ=yXDTXQZ}}y88sUTHS(^{^#$rb7*UeV5Pesg}-`Z)<MX0^N
zUnOY0-<Urd&&$T1ZnkT({9r3B{?(_$v5&}!Cdc<x8;!aACL+-gwz9E}<fBFY8v7GD
zpLhN{o<_b1JNHMEFTGQL8}z&b{$g;$Cc-H5x{K<Es!2K-+0p<z;*nld<XO^EEI)(&
z_dlF}AddWP+_*uoE2eCo`Ed|{oUp1beCbU6pUNkc4k<FnzDU(W8<}7RugOl?RqWhH
zfrMM8zOP%XHYa00_#M5ZXFXv8-2#@Bry>NQibceqkfz~8ye_xZj?%Ak$^HK46BBv3
z<e$j^YPL6bRz|sn=zyIr=->2Z@&Q=Fhbe4R@O7{n8^_$yo&aF+)0QtuLwDsS9yp(|
z2jYzn0G+LjbsY~b#8d}8-5n`=zpImV&VI<P{16&=Jy=;$W9@q&Zly2!9mNDZvU7v1
zr^RVg)Yysq?@-?5*u&F`GnZq`0ybHF#R%IU^g)V#$t9XM>30G>*GUHYmOd}yQObfa
zm{F-4<@L#L)oKiYPjv9$lpcK0DuO4~uf(e-T7~(>r=Pz5OJS=YufmgWoK{xv@Gy-s
z2XlU|n*p^M<+Bbuv708n??y)I6ZGLcBpn`wsrsI5dMc3~Cfw=oFE+;)rR%!6=%}ka
zX32~tl(IbsB<&RQ#tr=6g4(GQu4wGequyO839e5xFS)<%a^=R0bSl2lWEAoz4mLK>
z+8Y11$~YH_SAiK$&SBgKMQx>q0U11tu%G*N9iCN@&F~_OJ28jNkA!z<GqOp={?}EP
zR1ys4oiFW(>_*(l->lE0e49!ROm|z(WYM7;Pt!e1k_+Ns!!9E|wkNt6`~VT7@`t*X
zmrN8?#*GHh%p_nuMJZO!#a~3aTH~Ps%1`ZRe4zHr=|W|Yo{lpyxoD^3ZcZ0kIjgM#
zzINO8()E9oROQn4vNV~FeF!WeI_8Zt)=SxcYBf|HAYncrEbP<Nc3#(tx?{2`k%S+t
zfG9M$F_q?0xCqr7n`YZgf09Y>SIuyd?WHSHlL*iwx4Zr@CRy&i3bVvbWK)cNq{7@h
zJ3Z5hFU4;@rhi5za@2({$hEedA7_4}h6zLfQn51&+iCX3E?@_wO)VUvSG@}zq`^|g
z9uB<WTfxV`=upT;d(HXiwTo+6j!>40^xB9+S;5|vYXSUQc1zCM+WlmASoldjZM|NE
z*m_6p_kp)Q_loRBd|YkEF_kg>5NO$$vFL^EwO&(gK}H?IUEd%p^)8jD1>ArYMQ7RW
z;o*kLpUmDb+s(PF%@*{m2^Xbx{-}1L3)E6zpF4J2dyJ*1<(7&gUp0<bHzF6CQfYc{
z=&mwfTg;$G9V6imt6BE~QM!oY`Zguk_3HYc?pQ4-!%8l=FQFSC`<K2&(Q#QqN|OC=
zGq+@)g<)o~XkJXjF1hn_PA6f6RI@%2CmFXUqXU~a9PivWY?}I(10JE_7;R+>933e*
z<wEFX*Q2WCBoE=nmKQrIhf8*;wP-KdyNJP5PYMMu-lVU{Oro}EyO+T&<cDT=#E0Vf
z!k418#ecRhR+aXPoTaP&Rc(*L1?t0Ex+E7oxGxCF&nJ+^;MDII?;4#IZikl^YDZ}F
zzN}PtjAhL+hTUd9E1dI|91LtO?0xD@QCr^cB%{Y7m+~4N>~qnLN1Nz+jt?|6kO=wu
z!V)kx=cI21LSjK<(L5;?%1O7hvPz-R?;CZ}Y`tkyzmdq&@7dapE(UiQgIc5~2DmJE
zoFf_K&b@r`Yc)OaWh9<6L2$Y1s*ScbI1F`gEr7+OgdWMfyRL-()7TmsGOT6|0(Zlj
z9TFF61s@3CY;=e^FFS9bLVP@n4l{KgzSd79C!}#t#)Qz6Gf+QR72QXG9k{c|K}*4d
z(x-n{J4dOb-#{H8MG-iR!?wS+q_u3#3w%p!)*1~o0`epRa^Cjap8v3R&PF#NyO63D
z8sH6xmb&&K(=yPt?lh%4U22;h>f#|}5M}Y9Xw^lEckI3`L#y69uwqd0MAu!qe=6fr
zwL=1t<*bHvk?pzfnNMaLp0^&4ZHKqQP33ZU2f~6=zu_T-?A$%r$X&Y)U$(Qh^OW6I
zxE!Zu(C>?Y-KEwnLtv-?iH2oaI4=7ZSuJiAgAPn`Ku4o`Qn$E6_I?MW4*PZQ^w_(b
zphV~k9IUTo`i5zqB*V`sBH%n_V0v!vDHm6#?*yC!Uf`~KY`hhL<=XPy_Wq4)s5xGC
zu#zHy@wg$H;ZQCvWrJ8Vvf=J$>7@>fuW9yf(%G0SMbz7jGi=`2G*G!oS6MblBM_j;
z19q(TV4SjOc^AP9iqZobGTg1pwTZaE50^W;2^>HO?E_Am+;MxsIXy9(fA@Vi;ZD`(
z$uZ*bny#+BL<?94;zZF4MvG1g-j+hdVICPo>ot)%tviilXIG5Ji!O-m3I&3Ogc0#K
zqNc>nSkGoZ%ci!b%4IG7=i;OG`Q2Ui+jXt=B=lTd>ix$i<M@t#(jn76Zgk|(u@IyM
zw2>U^l2j1&y+9PBI0iSmf3<m<LRuKvDKL`}(&xZw>{8!$x$6~Ek8_H(^KtO6M-JzY
zL$VJ1aeVWM>ZaP6mj2p8Rgd#?r9)T<K^3{<hx9p3Ojp8s2yJ;H5neA?`hQ<sS#i0K
zn4Zgl>ll+xH941}u(R&OLQ~S=l1gpQ^`)+V!ZZZAu(m>C8cYC_Lrrr?9(DY(XckCW
zm;8HdRh+9RlPLK_m)vDb%0^vLwWNn7kDql5Ex{$yBX<}Gdj*Bv_n)ilkH&G7=-k1N
zAmB6!>87G|HTbGfIIga83_`gim4Q&=E;@mA#k<r0Zk0n0Rp;DRgAJuJAc_bUxE-eo
z2OKl-uBjB>Rl0TzYIjsWXdnDagqtY1S%X3QsN9W;+J-H|!;9oNx~;L%J%={8U9{&^
z5GgjJ=5S#QRxODv!Qe0wrgwL$*UVD@UbnT!<v<3YeV6K1bliTzekspHtpwR?{q$Fj
zowY*^#g;}gS8}?xn{C6bS}#h0kSe_vweiug$n*IZ1QEY`ZH*Ph>AWP+jfGO~kVR&Z
z@$jeaK1D}Xj_Sbn9CZ*e<=#`xk^Ro@dHch}9<FV(7hIHJjE3&9y5gLj<AB{UcAz5_
z*_5aWQNWc;`&V3qJaggM<fL48Yurky$5uGgk~A()c^mTv34OF}ApC|l{(5w%C;y#j
z{5+jw^|b{m+`t2TKn{58lzhSJLNxdkTd3eK5HaQB^s(C$(RF3KH~-7ZdY8{BQn!YK
zR@t{MyV%%gIg>WD?DG^XIjT>mzz3;hr!7+@C?q9X6H#}A^cz;j?Jg@_5E|uCSQO`w
zUzIM48)=zYkoD5*xgQw;n>l<r%5q^L4Rnl@fEiuGW?Yn_(rW0)azWBGpF*rf>(CMK
zcw`gh;ko0rQ~ze)jG3;4nb3${benFzqwTr7(rbuQqJ1_9qvtvq<+VL)YqU}fc?o#?
zGpavSx5PIIATsY{Q*BuJ$sER&bK2Q`U~e`hTmT)Gk8wpEdR2yj(!Ogpz|s^8&Guqy
zHfS|*6ryq#$wa6NanHIv!Lnt;vr4wNsq))aVYI)Pv(;#{515*C76V%{s<CKuKY{|T
zZAN96uia47#dYMkf^4rl>xr(X#c4sojhuj*QdbED*e?`2ZhyXgy*)vD6|ydrSRB;y
z+zO+W1N$sXO+Ah4eLD3wcx6e|RN_*CdDi%#!3~TBo>Js1u}?K!l;@bQlTiU>Ddbsx
zr>Hg1y6`rfmHLh}ZVFq&3V&$QrYpk$&<9OQsn0_<@sxdJBzgq2R?Wl)%G-k*qBXTz
zpKR_mjp^Z=)4dcY9GrVeG}F$tk~~2WEkN(XHAPt5SmxMT1TPh>BTykLePuB@q8!(G
zgH0=Po)~hGEL{n&m_J}nPUOM4W6_5mq${Mts{sO4MlD;8=fF}JQ|t#*#USJLJ2Wwt
z!p=4kO`y@b-`Y;_#N&eWNWMr@13ZzNjCdfW#1(J&oLB!uYX<dy^k<OX_0jzC9W{2e
z)@-O^0w>ftQeO#Nef}ZJ>kjTVRDnqo*~mIz@YDZPwE_%A_PU~2qNfN0&WA|WkS6{u
zxn>S&=zyfs>|?~&b11cw8;2qj5w5!ce`%ggw6-v9rRz6Pll_TebQd&gos9n5uLYj;
z*<@mu0tqeeP<{xV5CjbM*f1#u1F5!n42S^Tx8%mr<6-orAkgj+H<SN&$1o-~y;-O{
zQe8W3AOPDp^8_5$Oi?OB86~YbqzK7y+y{FW6&f<1^{Q899{k}y{o<~rSX9nALszsM
zUl53-IH*~kLpN5P?z4W=M#ZG*6s)ew4_0%J*#_3DP4fXexLN4%-OEc(u7uY(WQ$w^
zj8Ho3_1sTPLcx^C?J5j+o2Dr1{sf@JjUA6tCmTNGy6>wUI?9+IGER!l1I0*`x`GvB
z*hS89s2&FN8FYr&j(l5Y1N?#^|KcxK1E)MysdJNVZUq$3{8yF_kd$;tQqrAz(i8`j
zdb;D;;(Yc|JK0q_|CLFSk_s{9$WA(k;w%p?9)lM3=#TKTqf!J_h>PsQ{&<OPI3&Pb
ziV~qI%U-senMi8gxYKkP=>sF&C3+@b8g8!WmnT|+@1c~a(T4{c;b-cN!qCYl4mMV$
zXD+slf@Py;)U0=rpBQ%Qhx%73DbPE!_H6#U>>4XdRX<PBiG~Umn`L*he`Bnbbn~+q
z7*=AY=wHnFECkc}WLU*~Xp*IRQ}r=-^I-kpE6wStdb&H9y*b_bNyidZg``517Ai!M
zzOZSpxlA2cS*pn5jX0ZD*wNXxQKvBre*?=+QFM4hlgl27KGdi0QqJM}nQyw^g%c$6
zBxtc`7nM0<w^>k8bT*I$;c4+h<nB0t^01uAwRPp&f4x>HDmtn+;+31OmqRA2wL(F`
zmY9qtcs`4C5@%~Y3n<!>Yf&n%+9U5(M_cl;-qTUyVAD>_i_4D{O*{QjYBt{deZP&4
zmPETZjw=6<w?DvIF3QNB0JO`Rm%AJW3n2*?%C}C94x56Gl3n_3?`I6<K=$?SpZWjV
z4Ku5XBlSeiTE;F__wS=qAD7TUb|Vy@jGnab`i_Vxy>Qjyx9QgZqQd!4Z?5Tf4Bx?^
zG+eSqT$6NKVC*bF3Fj-pg;moKn0m6f#XOAnt(w#I@ZE0x`RI|*$eRa^S2}ASNHd)D
zZz<^;f8u*}IYhvs`{^RRkWjbatbs=|zy;$H*7!{U7XqcNkbt?PdNkM-6yBqlQ5Xag
zR9_pZpQ`>&bdnJYXeR{urcbI(RjEF`2oJGDDW>RN><6da4S<6@P{b3HAD&<Dh!?-S
z;)vyu%WK0GS%P}Q;RK@5<KG|>@JKY3Y{@lT@9ne`u$t`=ZZu*{=IQ88F)mF)B>O;y
zY4-E<si&L{Mbo8C8j1wc7BTWQ0FsAhG2G5_e#8q`gkwbt(}h!w7qr{luNOi8MAcvk
z^#I>Are6kgAc~iy0}f&nYJr_;ijBRdl}pFWUK`N4to!dQ!O;Xr04Lx3gG_!MtuX$7
ztyw6v0?88rKy)E;axK}y;)$;-Y0H0_cthlYKQZQSs!qorDn+8I^+T=-=6YT)U)hAd
zA-Xp$LZ_c;zwKg+8eLLL`cQz&CC?m}%%6(c*fJ$1evwB@qDEYO+f0n<X<%-lBqM3Z
z?S8LGA8`l!kKNIc@1dip&3_sdO=mq0*#aMl(xEjRq9()Ih^?sf9U2h&!B*muzhKgT
z_1r3fA}=g@7@2`2IjIPO`N}?iK6fV;Yj`|{7A6Z0G&`pg%&SCgNfU$z)~y`LR}SQ>
z_DK&y4xTc}^j6<5sEjX@Q-IxaRyjiMI|1e?pVm-J9;V%I!wt>!=_<uZ?PIR_m`o=i
z4VZM>WExI2o3@5sTd1#x!JbOi08r2XF4|8KQt$e{q`uA^EnmEXq=Kw63QAf>E&P|&
zP75Ax*e^s#1vv<ekRFmOTQ`@pwr4+MZc2y*(fquCUM-QBb2j?nNO4iFoQ+n3)Xb^K
zKC@t&H`DH`DJe*+C7Pibc>sP0gWn}+q73#e@80kQ39Xxq%AYW*(WY8PKZ(2GGmwBB
z^G508#IOE_$0#^%?FOKrEv-HIwSDG{`blajMW;Q=F(2X&CW^2IOC*e#$b&zRtV>_s
zzqd-Dgn22{|FrRAA^61qhKt-voK>=i872W6_NhhpwUyk@G6%W24>FDu$K$Rzp0M|s
zU$(7mA$iC2+k(r!ZZ8Rm;=<x0pNA)MFWK$)6E)GTQSW4p-?p4t7qa@>w#cJ{l6VuQ
z(Y3vpJf{(#$b3nrgw`VF?1X%0zdqxSQ88$wQdT0=AdHiog-Awv6rRoM%*eX4d2P@7
znF73UJpN<p@)CMlz%F}td+q`Z?pA!RB;Q*We_)+_K=>*~IYk)9CUNF|Sp<YMgAY<P
zh!zW%wWs=n1&m1-Uzq;8BmLwr_bqv!MUnc5(+`}xuG}SCh=#+iPF$mC<&GrG=OR6M
z?}>aK_VmOzjN|pYrhlcjDqV;PMf~ULpcK7rx^MgNw)bq=BSNHzM)=q|1kv@MR}h3G
z!h4a>4um`d{K<7(5H8m;oKIs!(k(fTCasxUimw-yqMV<6uvEW6%bO6;TN7`b>8v$r
z^m>45t~sVCo1E3fQbtqTU}_cgstX)F=TQN_FU<=hIN(88zo3X5#BR2$THJRQ+%A7^
z!QnttQyGg4<HYh0E#)_O@UAp@HE#JbIWKI+J>P6EN|7H~3uD0$uYy$g%hG#+p7ite
zoXYJxf4ye00078R0x7UpKwx%zj26_gl0T>D#LR6mpG9l=JpGvs2Bnrx$lOx2<|~s?
z#tQ-qYZ_zI->R)bGo`K;+p;&Qg!n)6X{MPEn2v#ap%5B?g4Pi8j3!$yw;%~SYyKPs
zFnw*{2eADWQ3UV=XmX2kDJhIK0fyFUE}LLb!AZqlx`@OWpz>;o^ze}CC!>*pWc_@|
za>G`WwdnBomR6Q4z?;}+@ca-UT4CXZb_GPUU<X9Qu~0J&bbw*OA9pLYTh(FNp^eNN
z>f*LsaBweDBD2w))*a?Hb;@JnCTzzIByopJv^cwxAPdchmt6Kpt2LL|+1GU2D5{xg
z&OYoiWuKZc5>3}-uttCc2Dy)yu+PRB%YMAZ*w-*LZS_{QnQe{mWodKCyX)9T-EjWe
zjS{o2Pzqz&wWWx;E$f!b<&ms(+Sr-}_2YdR3L)e!M|M%MuVc)Gh#?#P?@$m>7ggV6
zB1?ktYZbLO3qZTU!e%DD#9)y8(aD@j-w>I$Ps5_*Y?OWEYaNsz=8~04&r+UjQM6g{
z<Lp?eMKTi|f2B(coIjcPf7V@+k^0dgF1&n6irckDzA$6$jWa6BPXEY%Lr+qarMk3O
z;zu4L$>&uL2hy+j;rTT+muU2-|7~5vo0MGy1VizLbeYAXS!*_xLIwT-D+LFKsn5T(
zlS*J<-Fwxz;Am6KJz*HT1`EZAsErKj1G8f$(QdYMnO;#S0e2h%i4)sTRYH6BtttUr
zPK^u|hp4-tAwhqnQA431@$`4JG(WkSz;!=tePV<}6+U^Y-up(=t`j?sAMEOh_gIXy
z`Fo{hsyYKG{CPF+i$8WavN&Ub+n@hJYwCX;TQTplmnw*!mX>%~H47%q!70B%{OOiG
zygafB4k?jj6w`iY5pSsB4xxDc&UlT1!1I;PU4nqO`OLGRLc9opr>;6wg1qrkS0Lqy
zuHc%@-2MBW3aW+C+F(Np-8=OubQ+tu#KF@;YM#59=Wf|uPIP#Q%tpkp<Y7@`=dP)p
z>0)x<be5f%Z7YsWUt|EA9u^M)2jGIqXlo8F{Dt1}=RRNMB8aiV@+_z3xF@146^iWk
zZgz4O_`4NHg|D99)@MDVlTK$q8*U;o6yGpdEpnC3Q_YQNxlr(?XR^)T*WHVb@27!m
zuEYfzP4US`@jfuSWedye(I>)MMFm(8r7^KnkDk@C-DMy@JN!Mjg)#olpLyKkA)?{>
zuSVlv+BN;VUGZJqr(iUWow|9-^A$syq@k$<?INYpyJaV}PAh!-Z&rt|h0T95iL_EA
z@UqZ(%1&8naqLs`vAyNO+LO80@yZW%dMa5bQt2eKnWJ>VasI6I&;x0c^>M%IIbGsu
zXG)#Ia&wZTNd|<-CS6|WI^K7AD1Iml?_n2Qv++?>Ej;hNYCS4rYfuX^xxRMu)SmPZ
z5Y*y_k11!?2>=vK9e}-Z#1+#{Ap7?V9ghEGbtEPaQTix0RnjU(j?UJVv7Z7hsI%qn
z7~+Yu;)UrMo9?`s*j+VJ|HS!Ze8b3wfeoVQO%I_{L;LreYLt1y>hdG|eWD%}3wYiV
z@0`%nxlAibMgw^UwGG=l@P;0(ExHQbQNL?H=4M=+HSj9>?&sRea4U<nZgYKL6PL$A
za8F0lujJB&0vZK|wTni?qkD|8E&3X1VhEiWHz=K|>+r<y46iw<lA=S0;)ta$&LYZ6
zGj2GDs{2vJ%q?890IG(A9S76TtE#!G<bLNNL|Gf5+M#=4E6s*sGnYc`yqLO+?8m0a
z7j}`6J_6pL(QW{d?t5aMEoBlRe2*7e-KL^AV(P&<yhp<xa}y(XJuWz@h0>N=VHm#)
zi_ZNMD3mR5W!o_J*KIb<axKuV6u(^*^~+xP3nPfG{o7w&O;gF<#tYOC$ixYrBGL$X
z7xpjFMso2S6h7-b`Dr?pqS(?!5oM1)PXX$1{womMw8tk%-O`Iz{7jMBiJNAwn|sJv
zaOXYfqPc|<vjIrS%Or%va-l@Y$GHp3o-H_C3Mbqnut~50o4nvGwJznU??M^XGBtzG
zscLEAP_@ORZCN58KkL);quoAm1g-$z%g=R*H<V1*#hWKrK~uSNB+oQg*|+nd{}tfR
zA9hNXLw`I;s?-*l_GulKi8MBEA~KNJI3i8@ByfmA^D}A_05Ztf<|4E2o`QQ2Ekz)!
zT%h?~T5Za{Xx$M#1>+!PNQ&Q>GPz*OVqM(PHT$_^eUW~q(|w3^wR%B@S#6$5q-nA$
zQYui+gQHvpAewL{gi1LIwnZ8&LH^R4wLUBVi=(T)S3;c-!Tge4OF0UHl(l}EWvM8N
zo&_#~iVuX9MMeYk4odAUh%{GsLMqU^7x!Kiv41+R@ffI8L;#vWwNIOPSVr|RZkV+a
zX7lZEFXEcYrA%Bt9~D5`3xK6z<x?^C)EvwA{n58{|HQdS^+qnVxj;2)2i2(QL|5&}
zgk^mjvRiV7yNXbL$iJgXVM*K}b7j4dYS2sTbDd28s$7NF2NTOQW(g@&QUy9$TMP%t
zl$F#R`au}*AEfl|{r>s$Er~n|ruc?U8_4B0)emcvYjgq#OwF+L1)nU7a=c4+MlwfW
zkJ@Xo@conO{+h{YjrX`NO7Uy%#-ow8k<7abdc%N>(30C$2TmsURoS-H%it<|;E`g9
zgy3i(&A;+-RFFQck8AMY`|(w7MQm6G`bajYC58o5i7W)s*!Rq*yPwRF!?9}*JihG*
zsl!?&7*G`f>?8QD(cI{UAENa!UA)jXmPwm$>LsVH&%XyEwU3h20P}@gArt+D(}~is
z`3>`IQB>rCH@JW&vUwWGKCqq6oPUei;b?wqX$#D6K$%kP#0_vY#Ai93L0qbv&#80j
z4#NT9BFoh$nw^8sqhFlc@!7XlT<$W=uZ&B5jS3X3Ah?K5ImXPWgHjnkn4+l_!aKdS
zBgypA{f<+8FA@#ghADqFZrH_r0MpsyxwI~ri)z|y&rwvc``Jj^V<s^3jL6Uz0z8e|
zwUU|(r6XbyKpBAsRES>iu4%#$7Ing*!=O(uaI`mKE!P1FkJLla?V$UC?>ilx{ssf^
z8fQ}Ek6a4#ku*WHHg0phMd8>v4&vQ~0RP1~aDQ=XjT4s9Y#~`FXEkh#6bemvm+oh<
z@&UR78^X0Sg{EpK;!H+H<Vq-nlC<)DBih8Q$(mi2J9}Q3F&hgP{kB(|<Gz1c2416h
zpmYrxafP_o<(?noFqKbgxm+#W=m4pe!CYRss)Jz{fy*3mmqFWIO5VEm&)1Nsp9lWe
zZZLLDHSesQd4jR67tJx#xu`FmQB5jSBFj1KUn_|p9(Q5Pk9={Kc*b8(OE9UHSC#hj
zuviXIf`<_omE+=<XNC0VNeEAxf`d8P7>O`wI-&CLT-6jk$sD58?T>$zF>NSS4I{m6
z(e9A&gA7B3WIP!_2}q9SM8fQSFg#w^>mDHi01H>LXr?$ZN2zUe6iFgmMUn>RlAS2Y
zO-Y%=Z|D(<bDE@KddDsX9iG^Eu=bVTl{s`8bUE90m9A~-kmYed`%5zaV!@NT`4`n@
zAN|eBHWwEu$U>(62|5flbwUnXTe{Qu<R@bX4yF#Kt}_visyRhA2d*zd1u{B9@1QYq
zy6MD@T~nKP?yNO8&sfGY{^j^5PT*g->T4kon7K$znci^^etY@)1+n+?@K&t-ZL9gF
z70=r4PwY6S`WV%#(FON?2lp(~?&T)95A%QA^hW%Tn>M42Xgq1jRb$gB2i4i4vQ^O;
z3q*V&a-J~h2#0xozACMYMql6dWmRrX5IHgV7X6*E;i3tqc*C5w+LS}%fwG&=Fm;0d
ziYjNSx~-bo4IfGlvSZiu&Lec*^7(taPVRU?X4Im?YuncLN!vwGv5oMIyBN47%Rv)}
zAX_8qM%!9`DZbLp5&mggF-(wJ(x}LYL;f)J^?tA9y^FZ+-4FBqS}s7)P10AqIsA^z
z*?lJ%0w=H6Hr>|S{3nVFg=S0n!J<pE9TjIAw<Ev)`QKK2r4A4ydgcNp{o$GJ#uWF<
z<;+KJB6=11hLutbw9{9jnZ$>Qa9w0q(waFUt(nqU#uSdJWV&kLQNJy)Y`O!MN>yB4
zgqGaP*m4KqaL%pJp138^UJbZiYK+y>z2r5yo-`*VAH3%Nwo{_0dc6AKrrHZlP1GH0
zi`CGtf*pPcg(V+yd(4s@&#A-kGY$wFTAEj=k{kSf^HurTl=^Ud#!QZZsl5+$m`<VQ
zjG9ns8XNLt3(1K75Y{46dzx|iGDC#A8`z9B$mbqdZ7cmM2ao0&bxUxLQkQ*|v9T0f
zLQ<LN`tM(}`%Tq~=tv2=&6i+<_3kD2EjKtOm&QQXEV%s04YeB}R~t~Np)`}825E!g
z9|$%&O353vzSAY_E|TUHXuO-*jZt_$IPbT!^yEC!mo3bg&*ZFaIXm^J^{bt!)-#sL
zK10nYJs=d)SV-8OdcVo<<eq)?LnzFx8A4av@a3ZI^prBLuREAlaVy}WINB+=zFXSB
z_|-@TJ(EkjPCQ_Awh-BjUt^TWyFrwx(u{f7$gQY0cf2SX2UTx;+w|4ZM<@VqJgUZ>
z9=kQFHx>}-b2;DZPyI5iaDEd+9)xM!pnoB2q%T;_MPeR}j+_$5^X*h!r%qP2ZfM;Q
zh3KiMpo>{<Vd_wqxsHYw2f}($CDMYOmN2Ze?-yiLNBGNOAO+3th&6*AcWA=9WP`-K
z(LaccMcPrQ?_s(QN{kJblnv~(?~m!=@~mrL$aww!lD?xzwrDoi?VcKzPP?b4D=Naf
z_~@sku&m!S-n8B@X3VXo^{+pp-#Joq)9-XUaKVUy^_9A$ADs(i7Q_(7-4Gps*QPnE
ziatVowKM5=sL@&Hf+qlz{S(k3Q%Hz0`Q+`(?FV*MfkqixA?>FEh{iy|(jR@j^{t8X
zP&5LZ!iKf5G~2cBB(kP~$NV-s(WdAYpa<Sh-E(;N$Vg#D{!D$2h8!XP>*HUNUJYrw
z(^9+Qi5646Tz*AYh)ELF(5D{1_)~o+O;}_8_YjlE?q{Z<JLRH8nsO}*HEw*-_Wgh&
ze~0ho{6Q(Gx|`f4uiSPQ+F%rjXgh9?eaR(0EI3{M@LBgQM9IW&ako<tFEzC0FQ2KC
zd-e{1m9LVe(<@*WOP60&BM-VHKK-Gxw3!U^XMdODN6R2`5DTiLMm>|IlRn#_j2;>$
zRSO?U!f}yzKL-=mW%DO_>)|KbK2UE>+SEFyE{InF+xzB%npNprb~Jj<rNgI6uHXyz
z5oi$Xw`lj+E^JGS`%NCD)E^e?)01?agw6mY@&v{BWv5Vk@>@KhZ-XgX?2LU&mHZSV
zn|y9{1Z3dI!~xK;ar;02Ubzd;pc4}q(r6Y_Krlt`V_VixiSMWzUY{-3h|2rkPwnvj
z3c_mwYPzgwnywjNIe0o{inC)Hq#tmR(XcwB#b--&C~qe@VYAb%pBA}?leggEpj-;y
z*8-W9b2~D@3fN5{3C1-|E7quQV8{-Api9n@%@7lv(T}PliZsD(b?FG^uDtxv(mxg_
zy-7eM_E2%Fk&y6_MRm0$m9SfLS~TzQ5AybJATy>^wm>Go;L`32yWKQ6xOwmd`h_QY
zsX-KT1j@$7BIXB_Jf_nn!k2Vs$nT^yqhb#}Wj)6W!)MGTF%18!juvlQ#@e2zy_DfN
z6U#C6;ijEOn|3iTQ9k$7Za!fe>B8*n=xpEyqwX1>XzX)9s6tDcx=`-Ydt6%H25L5v
z1;#`~k|Rb|wC7r^-DlLIKR?S{YbWFb=IVN6S|NL_{EvLiCS;qPHR8>jCHSo3RffG4
z*#=FVc3xsqGm^`eb^ID!5)0u=Jho`>GBKO`6~v{kp6hezm5Y3z2|se*hoBN{BWjP8
z4Mv<ZiGmE2iA?zDFf`H=#@DdrhLxgyuA<^+|M_)U1KUat31F{i#w~7zSyUIy4%I3R
z<?4`)wvv`6A)um%6Q%oxfo1`xaYw*Ts__g-jboW@`YM=$Z<EJVWCPG+!&VOa564)J
z7zD?~YZ^%!L)qxU;HX1h-~zrCFx+P9u9PJ+9CkVSQ`Ns7M2{?wNZ7|swe0_%XB0gf
z`l{jwUsYoYWzulYb~gT+<{Gn#E4TRZ(mGH<+JPhk7yMBwtC|ny&d}YYQsk{H1%D+{
z>xfS!=KhJ1IXEUh9s;8|@Hf3$aw)VULS%D=Q*MUm331E6q~zRUkGdNR8Mn(Dk=jls
z=<<(n&2HP*zdwaF!T>7MlFRn^*1m=f6~RE*bZfWSqqFq7@@T3?q2Qzy_Fq_GTVI%8
zEj!y{x5PIyma`b`@Erw0FQ4;(_e{`Ops-SY_e34r8mO`?E@qf@=_>U*fCUT)1$86|
zO`~UZ)Z7@BFhmK<e1d*mMZ<|bOt*>qO)W+^rrRmKNN<lom=DXF>AuI^v+rc}UgWU)
zF}k-N^$Vj#HLA^cJkUxxfR~?bdySZ9Z`3geUIr`}w1D>X3PEG07S&DbQ<VJbiRQl4
zp$-Umi5KE=)qNEp7U0>N8vq0}PxyNDk%)fPYrdg<Tkvdr0fv$^bM3{6W@IsaR>$S8
zP395>)DxRPh1_JrbcOq9vfQX08ek7-vZf-<j5~H58anNhm4L%^EC0zB{7a{um-IcF
z{r<<V{4&jc8%criSHKgXJ(0hWYc3Uv$M9@>owJvGW+=%UPu|}?{2`1Qj4K#0@faEy
zuIXO_%QNsIy`(^v_7z@^2C=H;xPeL+^wDB}R};IU{EY=0+USyfWs*}M+Tzd<ECEEh
zvXg+tmgt{l{|Kb)Q;WePz5~G`v4iTl^oiEI-m;;5tzRY0LNT+LBYw*@tJbF`#$czg
z5>56ijX<G6+@q33v5NAiSj2>*HFc5AG;E&Za<z+9qKDqtV$;$`@pknv6e$0>aWFR-
z4~OBBD-K{bIxe+5q08kkAE|~AS%Jl%`zre<R5}?|$8#!-F6sC=J1%QrcLKr5S|DkD
zr;8WCK}pIY8BA{#ZpKDEtQte_#07u-c9+~z%22L7cn>&*FB}Vur&=WfFkn|zWt_)o
zsqyVdkskU{`nUy1g)WI^XkL|*PGsNjs-amo6GUH~Y~!tqH{$Vg1^7zbJIQ}Y;9F3i
z<5fCPAYAp+fCa(~PX=*n7Yoo@|I_?8)taEZkyS`aFEp}w#(Fb*#`?@M+n^f}e5Hhw
z<4Tf~KTkV?s@Pwp`vN90N)%8fn4})N!0s+Ow7B{gTBt=6J5lj@UQ6ID_&xU8Ccw~0
z16;rE8nV+{x!BL`vFC^}2(-BQ>8;6-5e_#RNyhRnV|gbNmc0pb71$H^mUPJX^*hY=
zJ*4kxt|UTj0NWUqTi?$||M0oBq+GcXkVr43%W$eLtSYq-sMR-e2V;=v-A^*o$?Ev)
z;_JmeTY?Lf8}5x;-g_(-$ek}HkE?+qM-^ms2(-fZhSUx2ix4UqlGmebYy-ZbZI*Yf
zBo?4=AE#k6j}&uC=j;%F<rrnK(c5)llY59@*obnw-~B^{hfCW03j6Z81N)fH1Zd7>
zvgL9)1VWini0fx0?|gZMw%|QbDL4X5V{T_mY6aVcPNg=T^UbZ<XTv{G&U?D!^<w8K
z(bN-wg7e9h_by9jbf_qx7S&@KM}r?PG}8u4>tngT1xIz*JrBQK{w67@jYu#puQ<+7
z1(`hICO5uw*6Xt29=L$<<+_jq!%nRC{_$hAUjrP_F^v0Q)DxigRsSkySIQ!g$^Bkg
z)V6-~(f_yhnjL915QeHk%6SbTO9knQ*o%?o-H&%8v0%LCO>Wppr{^&1e)me<kYBfK
zC*D7%BHFUpqGa@{mF}Z9$1e2;>@yk0N;Q(Y#k){W;bIY8Ex0x1@Y_l>pdt-|jm`s3
zdV+DAVJGxi$^5QWEVO1b??H7yG|F*K3EQ|oHU{#{08MHj(itJo<t`<m&({v|`WJuy
zMR8lrtWmLry)4%m%8h9JyO~q;%fU%m+`{qu>7S?5td^6@_+Wo-#k>-uYpXcCCeUm2
zod00EZbkdxa&9|8*qmKpHl4=F)d^2wo(z=bPENw^8&a&>m<+_doTrw~Y^U!7l$JRM
z2HmX!Ke8i}Gob86K6)G~(@xluL_q>SDbva(xCL$PLjU3$Ysp99)TJ^~R(`>xiw0FD
zU~bK}Sg39x*r^jVeDKlyYn`7kkhFY$)yi7KK)5MyHfWfh!bQk+J-n!jTv>lj%iRRy
zKqiq}<bUDt3fjG(n|EO*M1V?4uTYap7*lWLL#_%r9l0M7*Fs&E4vW7{fu@U2FdARf
zeSt8oGK><66U+X=7c6`2->xkMg+&Czz+F9VY@uR_aYfbl>$$B4b0TFjEgb7#{rM-%
zvcawk-X15D-{Z+R&hh;FF8ayw!hekKsyFJv3+bxkIp;_ErQ8pF%2M3wjeC}x{g9-x
z$;QJ;{pD@(KVjC7Pme;YC##^JI=xa@iq#bS$h}@>cS`mp+3^1pjW-I(`Hfvuzqf1Z
zYrA3quEO8viW&RwiPc~f|Bzb1YXsMb32bj*g~!!VUub>((>EXdLY0$pZk*6mZt^wd
z@=9#aJu{8hvs_O=-^V;(|NK;6`d^mj_EWhe;FcuV9!6v-c^aJmVBVNA>};GIEgQF6
zKe2B)ChW^Sjs5~@gcEjei+^EILK*&v7ZVAd07uDn+~F!YouTL?!Cnb);EQg+yt;|W
za#kR@4v#=)xb3KAW(H7V%PZZzW&yVIjC!>+s{E2T&C+;DL>S|ga6aeatYhPA^i!v&
zS38%MWf-hnMlOq}6W%#S?K6|2tP%=stm_~3b-a-Nm!dDgj<{`Vdo)n-J3K63H6Z1N
ziaXMUncVSgOUJ1nnX?eEQm(_FQA+YC@?r&!`4CmjWw$`Uz=u}KSTgh{eBDNI=moQ{
z7}8Ypz(IRImy$!3Flh1*9<F<j33jpvYEQ#H!*hS5md{tdy6?mjjmV9jDL%uuKhHPg
zOH~KXO&+-D79?IW>^8qn()x#gRk><@j&76Oks<C(VwP0&DYY2f)6tR=xyG~f706wl
zgzNP06R-vR9;@@O&;}VIE~ycnZkpb)v)1@hZ84QaN_HXR+y#0$Pa(|A1fo^E;}Kk_
z7xFCZp5T5-4c9&?mDF;TB^Ehj&bo|MBYM-L*X1Lhyr-G%{xXA%{s_yL&;Jfy7~3N}
z;vV9CCtJ9+LTyvAMQf>J)@k!eUD@}X0MV6&0ya@DuW#l558qnd|56PWX=Xu&7oyyd
zrSlkoEZObZM{^7p@9ylTwlqI;rz8D?6$igQuMbCzHVlEANR^6(!fUF-Z`aF$s}d4w
ztdAxKPS;;uJ8CwAx*9>;=`Z5686`C=`SNaNZhBqJAd-m-t#S{mB$N+Jx&J<9`P#mz
z1k28HI~@v+i!yCo`I(>}!4(xP!byo2l+l}C>?WT3i#4!?$Il*&BONT?-O9d~@OIF8
zK1XpWc98N?idg>l9qE(5Z+DS6bJ@u|Oq8ly1GL@BrsI(wrqL-z=eR#A7MWU;X!oy%
zYK}|3l-4+jB^tl(mzg+6d7OP%Ajn$WHew3wmsIGRnzyYB%qkyu|LE&&l*z(dT*Hx^
z(j`+~{l2Mh)tb|)w`ev0iFqy;_JQ59b3V<eh;-!G%M%c>*}7x@e*NmPm)f!D@=+vl
z^yQX37S0!p-(57HPJ!XjaU*wN(+i4`wU-b*tX)Dy1q7#+u40lbZ-FK)-MWaHJRm8d
z&?KIh>9*(G1-&LV0`vH#TGDRDA~&ZhFpQ|(K3{@$9=AWQi@Y3Z3+qe*+}7oNCzIBu
zq6}NUr!;Iol)v!bY;XS%v4Y^@-jyNxBwTAe-R-|Sv(DP+*9Hi5p=9R+%4)2g+S+!5
z`K__kvpfehvE5InPvY&uEIkCN;`jJOn}Y5$q}O5BDQ)UN{e%PF?uihgKOm;h;o%v!
zWAlc}-y@bTuh`kxM&3Ap7+~lI7n`=B@M$MS{J3=rzgA{>rDR^lF_auY<O4pCO_A1;
zW%(B=86S0|b{DEA>yF5*`86wj|F74#GD<h9q>W-+88{kZa)O)Dow3;MAoH;6qA&FV
zuKo9&@a_y)(}xxyA49V4Zd6<o;}i3`flRpQLqf<cOHyFd$-8tW;N1}_Nbz_aFTIS*
zMM=Z=3DHtf@m)IM941^Yy4*3|0=w<>d-IfwJ{~zec{)7RBBQ)dv{XZJA&jbWeC@EI
znEiClCth5!L%kBd6HreY^71;_{_X$zzpYr9_MGx0UphF&k>SHa5v5$3mgHzNf|dSi
zDI71(zc$ZxTH%Sl5|tCZ%($*4_PT0FarLymeA7PW3lCm$2`eZ_F@Y4#aWZz-vNxLy
z&(mN5Ct4X2eQGvQ7}MeH9t$>YW%ebv-J?(I>urBfW(2^lzndQ^SNpI!jJVvR<{(E<
z@Os*DDQJlo2R8v37WlX=13XrdE1uzxn^x9dR*&W>UbCf9wh+Wa;40Vg>{SSuWFE^F
z^GU7;e5LsMV#v<IMBT6xH$u)p_#zpyLBo5Ely#$7+>4Pi|CY&Je!IF@EVV;41&2x`
zh9x06xKMm$m-i!5T&8N>Mmv}0?Qd*Gi#P92qNg0UC*hhid1efkA>34T*^$c~L??f%
zw!XfoexjBXoZM9(F%kEydvd)h@Ru`9B8Tf=r^S1J$0~l6#50_*K^8`=CR&4DvdBR!
zxg7Ab?i5OQX*ECaLdU*S!dsC8xI5~+=jv7{>7k}5_i@+isbp^zGs}ywCTQFhp&AJ=
z`Un#3fV`pKjV=Yav@qQcwWPA*(AJIa8^u{SnX{S74{TwNySTH%5LqNCbux2P4)}-p
z=bETsLg$8VoHJg<#5(HcOEiGO{B&@PI)h6k@!kF2jS?*lbf^dy8M52s`SbtBinY;=
zAXUhtNRi|dQAl{aMHKQu7S<H~mIZ2I^zH{YiP<Ojk%N}_yb=k|_d-})kaJGd-kd*?
zOgGePn64HJV%kqX=4b3hUkHHy0N762J#>x*g$rl-<;**zjovm9NAy}ktVmn)0M;6w
z^u{Kjjq0uux@6I4Xjjs+@Psq@j6%*B_fA4DlY-MO*izz<6DcKlamD*D4&Ht4d%vKE
ziPLHyik@)h09VdBc%}DxH@1G-;=-cTfu9Rn!Q=!ksj9TsQG!_Z<jk)q$c4uF2N-{r
zO?4DcE#jxz9NHIsbWe=$=Dk2tka@jFxgq?na>!gg;y<zCXHE93%is&IU*j4H-B+S*
z)!z?UCBZ9P3mMj|LyJQ@>@{p)?njH(W4Y!f6{w5%q+{<;08S5gIuV|0tJiq-+arIs
zV)IZ$Oa$V9m(@R68SjGZD{IVmb00Zp`@r>?zK%aX)ft5J85b-^_TR6&u=bEa<EC&+
zNWpactRHZ&6IaEeH#lk>Hkbg`dw--txM~Ss*xD_$Yel7XO#hne55hPEUEUG7E<SSX
zy)rC^re!4C^4?}HF6xD}rZ5&LsqulzlZQ$aQ%a(jE?>MZ3fnc?`*!BPu378Bc$rZW
ze}*rY3|zj*zmb`>Sj(J}j7C53Li*3enUkD=Qk<}i7QS~5HY0$Khme#!jF{39&ge@m
z;!QhU5=4SEapj8p&XT+0%*x=5Wg9;MqOk5U$wHglIh1ZN4``R<&Q7pcxVKkX-F>)l
zYVS@?xrJsK6xpvtBksxw@z9eAg|;qc-~PKd*R1$D+8;!|Wwj65AA#Q?BLDwMd;jRD
z&NI*RR;A*uPJ4Ewa#?euX6dS{i?|ZvmrOirPR^w2>PlP{g#d-5wTw3n6&b79*p3}K
zqr-ZVx>r}?N)!UqIvKT(+l`6>s%h-l4yT9odOAoh?6M;pn`V5}S?`X`s69C2?zY`N
z8IsL*@8`KCKyrHKpA|v~LH&5&_j#Wm-{<>0kKhiuRbSo5P>M%Q5SFJi;G?qI!pxSL
zOGAs6ix^bwwGkW2cp*+$=`8uL-uX`U1Dp|LEQ=_U9S2;xY_nChi@;Z>W~sAh{cMck
z3!Z0r!_;)BHs4;h>B#XEv(#&GmkO!))(P)yT=iKP>1+-Qro0XxB`dK$)FO^SFdZ@~
zM6H*XO7r9YxNN<^XoocePNq<9;hs{&F4OYvwI0?U%}D_)vFL-D8jOaiMi;3s&S0g)
zQXN4n5<7Pc!;GD#urZA%>NQtNokNvUg{+v63#;>->Se^5w*<5HCbvx}R_y_!BJjXx
z3Aksy9)qd}QDPW$uD*|lGkIAs7ZK?|2Y=n^;LtJHCrPMKeQT0Y8Ld>ZPzXKnrpLU;
zC>Ets3xEeW)UVaWF2$Mt`0%g5#MC1gs4nnPLN8djrbM0HJ<?L`t2xg5t!ul^p88IZ
zfGk{^TG6!_cEHFI__N7L4xj4Igjzkl`G9`a`XJNRHdQG+R%Kc>v}4wNNaWiq49Q#K
z^S0`y)AgTw*X?i?CLb8XybmNkQuSUTP^8*QY9Hj+ZOzS+>!kx_sWNW(o^O0W;vKbt
zp;{bqAU%wh-R8sp$C9%SZu2lm4dI5=Pl6pb*P_gUdvz%rWpEW^fp!(ol+Kg{RKwz8
zq^?#Z(h?;q(mn4(W+dS%hn*<t)$%x`<Lm{CalS#U1;37UvfzSL9oCloX{Bvw6C`T0
z<d@x^{zA5YPN)X2`4cOMux0pi%~*c~Y0?qbOmeR@DBm2(?J-9e%sKBwmN*la^r-h(
zcBl|QrxXiFbbZTAi?DoYNnyKq#30qdT{dg#OCSbqb&iAQw8cST<XlDqtzI!!XtB4m
zkHl*Wm&Gqy>ZGG5OI-v(*@aBC()lyWK~{X?WiN9SZ~Hj#!FfBk4x96)cW99Fq_6X%
z-uV*7idL0mY&!~v@m`toI>iLyS9rscph7n}$y*@^On_5eS_WKcfR>sQq^XEmwpD|b
z%eqNfOL+Y&(;-(btyc?DAu?u1IM*y$9P#zdkLFmk^r(P!4Ze8g+JWBPKNa?a1Whle
zD{{FxY`91BK2t^1{3+cWq`1obAX}Wx8gk%dVHmK1AI{qVT;OXKIJFQ+`OPCI0ukzf
zR_@$SinCMrPedugUYV~5A~eIgk#qUF*SQ&k>};IIN+;gy229Ba7WEj(rcaouNEgV*
zvZ77q`4!+vOAq|-dT(RpylWKOaDb=^t32?~fENh4{>&0Dl}0kTUHeuq2%Pk_s@%)_
z3eFaKgyN9N-y~+tCmjM_+w@<RcKDMRpkG!B(vS$vvgjXPz|&m3*F0!3`?IT-?StaA
z!3#*-c4Z8sbvZpv*iqx>37P1Y8vlwk*2G$vo!+^**(!-UA!P?e6M-Wtvptr?9BkHq
z`uH}Az)~Nj<VV2rKy{nAoj}MRoBJ%lv|2dbyn5kp2&iqYG?@X?0<16Kf&@PFXT&^9
zHB3p*mP&+}`UMNpDU^NyTr?Qp2*3V<e`~F`U2o}#yv3&5N{_+edIA{waEP4jbLw-G
zKdiYTw7aj~imHjS#7tBwox;@V5hB<&1o?nHlogZ305v=s`syt`+3!5GM2&H-l*0g8
zN|7`+i#}{D8I87@F?_4Fhba>YT0bpZJsW@~VxyN5V1k&sBgQYr@qwL~)nlYE?X4hX
zfP`~QKAjU|#StI!Uzztlb-Y;W{PW%g?}|kZQ`Fay!svaK9}~oZ6+Oir4w#FeWViio
z!pc6R$Q(Dy9?g2_yi{3iCQ4Bva0Nkzbn#m1h5htDE?=;eO$1JuxY=T!X>5Sz%H1KW
zmiiy^KR6|4N~o?8ws6JE>22!Ei#D2rh9)D8;s~#jcBa{zwYJ+owc9?hXkI*#mCe7A
zWyMnXf2jK6O{}QKgI;2!-Fd4|GJJz}dYkt~6=a!sM4zwxP=zTV%;caTXqkzw55o5^
zT8x#V)4Ne2q9mFQtb0&fvAlB-lKrDUSu)92OeM~VK{JP%Ov{NMkjorQb7App1`x^v
z3xB=)?4eq&Ywk$ALCjXoN(&Cskxzy<m#i4Q@3U>0^9vu44Diy_$N=VupClO?nP#_e
zQ+Wk9O340_l_$J%CrX`Rwyf%<KCp=|y6&rN_kS3_85xS!UP2B;XMZIIDksznCghUl
zlPVcn&xkJ&xMe>l`?Y*l&udE+wgACmrd{d%c@?$&7R%3}y7X(-m1fxJQauhXxbR;}
z0HSiGs{o=ix6b>hBhJ-59U|lXeQ+R+hrCxmmKF$I10dns=CJLL1)&ZVmr@Z`{qNf8
zp8c7wlGK!Vn<zGBB)QDhoVQ@O5Of4~n#Fev&ve|3r|WmGT3s^D{pYO<r3DI`s}-7|
z$uQOmkT9=?wFrv9MDH&~)S}M5wG;?H>elob%8O&i9~F;GYOFP>z!lX^V95?-{!8i1
z0&59iv)5?i`x-9kO`6*j;vVbY?M(|s!a6W;-g~Sx>17t6D3fC*xGV%7rkJlW9JQND
zzh<pD_0lt*(JC!@djwrN0#z1$44-iN^G`v@2;RE5DK!j5R!;|PvDGEB`qQelt}?oi
zrE4E;AV4KCSvNyV9({Y+eD~ZpmR$7OjBcnVHNnPKOG1crP)@s_ouK5Vnd-L^<c!`!
zK|Fk)|KiSyTyrG$mZi4)VefkTy0;q7R3OQC_Jp;K_~!_b0boJ_hlw+wq@d=BFG8v!
z>RQ4DJ3lDtVd~2Vt6fsZ`C5Td2yvN<`hLKn5d(&^k6XrPV5o%<y8oQps%z)`9vtv2
z09Cfu>rDzRJ{4fj^xaypytJfwK}bcH2lxTCx03&0;Y>bmu2q+i^eEzii}ezpR2_;3
z#;bN@!8xma(nZU(t584f3l&Q;`7hna)?-n8ZXMer>Asu5QDCWYO9(HaR7!*RP9N~J
zvb~C7{3RuSRdSV21db@$9Qh=Xe;f9%@55Bv)=Sm`RQkbe_IibuKZumbkl0B$Ei&|Q
zsXBlC-`-kuO{vOwa)QinBj7|^$adhA4MZO1M<VYi^n)3oGESLpXLB1@%-!_C#SINY
z>c&W)@M;5^*EVkts9jIR79{?cbND9GO^`ZspwXH$BVWZkVbv$x^l2_88j$ePpTS&I
zBtbdv|2!Ul;)j#9pd$!7mN+QW>3qrZ({RLIpqL0wS>bJ*F{yqA8<e_EG1*f~uJm{N
zZhPON&?LLZIS0utX_mkx7G+M*kwcyFTZkLQ1HB^K@}61vE04tA{uB^SU=3bGF+=2~
zN=2duLOytIq(T`Kh}p&rqh<YDa1jT8lc9341O@B3XVG=X9)u#sNGH3a&=UmLwZt|@
zoD7O5g6j<W4`xBEMIXvwRK|tM4a;6k>0Lr?P#Q?%J7K>rjjoN`_=(_yH7B%)JO{BQ
z*2@fz{4EVmqPFj0I@pLdTQB(?XgT;QvIIHrMMOc)8=y=O!n7*grb+{-uoC409Q~8l
z7N4#p;x-9gMa}}Z?Y|ph_w-pkAPTTXtA+HA3Ob4YoqplD$#>H?-7Wl=Cg%q#Ic-U6
z0~NwaGOJ4VdiJ`#z-Th|S^7l=UZD_Hu=>jtTJo-CqAu75b}RsoM9f8rX{)78@F)9B
z213)QC{W{pl+KaR1-#?XWc2}-g6(!!72^U{Vo@iydBq7UBf-8Mj8d&iI>M)Sr4N$>
z5f46VxetvbfQ)d57g+UNaDUgTY$N}%#ozYiQ<II;pFhf3KL<K0uXRh(;pv3%2+eWN
zr}(~?-6bL-&%kApK<iUw+P}4S2_hPVn22~0jUCjt!cjrQK~cUf1%u7q_g|5LpKE*n
z8gP(sL(ck8+IzWXvH~DQ$P1jbVBoF9))OUQopI*4e*^o$rVGCgH8aP0ZI&yM8hiCA
zBqe7GeSWK-?;!DUgm<2%DZzx=2nddt%aVhf2WMQrSw0Cq#9}{Wb(hA+3trjY?nyrs
z%)_M`Zd0pbUV675{x3`KHg7@HnXEfUEG>3=(OtQcD{2pF04q5{FeD!=I6%S0S+4)!
zpXRTSz!gfCp8bh+d|<2pIzz3z36O=68`T204)r=zc+$Ul*oz(W#7887?_xSz!_ROz
zG};h!csuZCE20Z8(K3PYh;rtbt#_T1$#or6u?c<Up3SGevYCD`MQw2FGYpRUUPZ<&
zcS#DHMAKz<8Mcj#%wC@GdjEf4BIZ)32{TND`zp@bTexh}*r+*uKdBG8OOW~dcK1(~
zB)e9;7B9RBYw@-dgr7@&Xw&qgeM61K=E2sN^zy{O>t2S5%kYH##|TU2c`uUZd%5~b
z_0}C<ED;ses?}&5<<nQK%{tit8S_#pbY3VB!+7{?kke{GMh$1UndrQ$@zlR)Jahlx
zpmBYx(epKcV(Pib2V^gcr!F1I=J6S7^HBw*xb43D=+z~zdLaF7nDh^J+^lVd=(>H~
zyP75C7r3mF_5xZ$zf<kv&xoF{QJ5Z)(TyF+BC{aP#zQ6Dv|ImT;6_RRTdT*vo?T#s
z7Xn#XL=pX?_K+t8H~IXPYSHIQWb(J0231_xbPq|fN2FUnJ<TC89TkirSjD@;*W8;7
zmXlxJeKINa6ALEOL-mF2-R%2zTAB1BdH9M#TdPW#5cJDgX6Jr%e3=TMiZiT<`xeyl
z>k^yxY5T59yU3c?x}Nc{2QmkVb-7-b=CgZeWTagn3P(B)4Ig!X&_P13>EzcB>d7-^
ztG>@_KJT4-i9Sx}t+xrUX=U@WXl@_Viwk=jMi#_nOfG<{aSsp(k{r)?&6`TNa`qM<
zToG@8d5-oxWUjbmID)GHgXLqRgKAD*b^5M@r@r#2<Q#h|LBUZl_3InHl%gLku-&{O
zOg7q?EgQnQ?!ToXxKi+k_$XSfr5sz?Yjszw9^I-~UB;x{DK(@!EFMcq9Yu{m&eE5(
zn3J!ifmUtS+Int#=Aqsmi1Dve%*W$^i%?;Z@Fe&MDA*b_Y^j6P+$nvl)_UEBxqx2J
z4uUoUw#<FxPp&Lnx(-KLislN%CLYkFG4yw^Rl8<=U|locGkFm1;qWi*%1fTlEG=C6
zeosEW`(ABCqd{Xd**%84xD_*Vz^a&A2KJiUt+>ZpXzh-L>Uku-;DqQSyHOqf0adtC
zV}8%j?$Q?q?Of}CxwUy+>2Iy=cEx+?lgeB=YcRKtHweKWq`oVfs&Yt>K7uRDQMtw9
z)-nKun>D5aVh%3ow!+8&q1OMB?K<EOI?v*S(l#Y_xc$UEjm6G`r&et)<&4&sX#RVn
zG(dTwMaOl|b~B$;J*HkCDDX<#;?yAp0~_D^mz<8miUJR;*)8TWUa7mAQf$Tt=|I*M
z>lIy(N33n}#$>$|ybU|oXrhQw<Wj^MlOw0KoISYzr`?10)+(fn0s8p~?v9P53;%@I
z8C5vY;V>r?mLuYK=c`^q4DaZs0=UXB6iOuT=LL@ljZMR00>j~{8DLYq%Qj{7D!pm<
z6|0FdwT%OXUb_Gb$@+x*Yg6~FC_ifdb;j!OI-==#2~EdFJcMm=o8fgb!14KkUDjIb
z{!L~NL-?qxi@cG2H$5#S%VOJulI5UanVRL_*?oqF0L}Z0*S0pd{)|C9=dC&K^=!9I
z;YZi5%7lLm^O^P(`e@Z&ttJk^3$N49{&{J$j<k`J65pc>-BR#o82ttHzf(LH+zGLV
zwYY{UJ*8DtEAQvg&oBIW=`RM(Lyki>KCvoWvq!u`mQ+meWz^E4@^L%9^faXz3}WIc
z8wxd#q!mVIb6r<093YsLl$vslyDWP$o^>9NQ(nji!%)R+n!PeH4w~y08Fgoy+ihw!
zsa~P=dIzKWYX1{au%7kGKC?b;3Uoj~J`i<kzw*lDgxW*5h){v9A8t4i%IK#oOtIBH
z!25gM>xE1<VU2#k<ihR`;5?@pOgQ94sdIdDF9dK7hhvcq^PbPOn=Se-vw4%Y&FZxt
zw3;9Z9kIKIvLsQu=Bv(|6=CcjQ89rp5*q{`vI2g8U{e?|_j*Oyn(eJp^KVTMbu+(<
zqhI_GVIIegr4~*q9VDGB6%)8=>JvZo{-j=#QqJ^7f{u>H;gcKrGW`|Mw@d}Gp!a_E
z8$kEj59~6WWDEoP;B982zR#w5%7>-5Scn}x!qKloq-8-ROPZ)<Mn_L;>-4Q=uXVrm
z*66N@r?X;z?&C#Yi_eKIul@Q<T!BC6=;)vknZaZ5X4vZV>(=;?<sI;@S1wee<5OOz
zq`78j!ZLQncjY52Ys(u^j<4UMFSnZAHAggRiPzcq+$6+u;auXZo(!tfH#WjMB{gzp
zRb~|V|Ar74svOYk6;i{tIUaQj(NSa2QJ%fQ96uQtD(AxM1Z^;od_6-82ddb*COMzV
zWjcl(%nFPGvyQo5!l?{?b;u@;4fAnkR|gFxih7m?8s5U_CMq5)qnj+77_uOhfKtfW
zX+&}MkJpYVFUy)O;lds#tw$O5%golPbU{6&ZC!v05M>3FD;b6?%i;5p-9#NleK0e6
z_S_(CioC6Oqs*MFdMEr~rWMsPv4@`w2W3Tg_r#=Ttu=1DzRqfmFIbzbxn0ElQZ9Ij
zJgXS1S|DCKp1&9D_y@+xc8;h&bI4^QURoG;uMyu=EAVTwS;@f#r@+0rrEcVKg7x5)
zk+vs<ta{!EIlEW-ajl>D6Vyz=G<Z(^d%|4liy(_>JoU(Kw}|Nc%qnfScUu@TVa!!7
zSXb$4OT8eeAnv}5{`|+&cOccY`jvxH>^y<}d)<!?Y|^<vW)FRZvLw4?j%jrSOhu(<
z-;$hW$I)Ri;q5ZL`egh5QwNL;FWXz%ZXMStP8Ke1&z($WvpcKaga?11=l04(E;L!1
z>pt)OxwqTuR2OV1f*$ebLHl?4uTeVu1m14|?IM3ohuatR=$S8z{Bg(wua_nkG9^1B
zgKD?hA6g77_0qmIdM9`3M&>cOuo|ftK8g}iTiBBK%;S3ZB*o}xhLMBzP=M`#TLb+s
zg9aDZR%<rVE+eB)Ys`ATo*ge{$$GzFmF&)Qfn{}}{>TeUtyWF<21^Tev~^Y=FP8np
zb+AkIzA73Xh@=XkckAb+Ttkv>wT2pUbbNm6;Pmew3|^>LpU@{3dO<M>f3I6@1E>(G
z>R}TphCm!Y+<aWtC;PbgX=dm?;*LhTuY#6y|E(qU(fE34vR%J=c(vEP=isR?Y_1uL
zUkvD5uWiqeEVRH}sGd9^8E)*3=sX#v$1-oeBBp)uTUw=T&pfZAVfqobLO^<}93mE=
zr2^#p$(j<u=ab$ci;Kk^1}!zNnWvvQTO6&<+NPU1$3$a1mR(j*8v46mzwO|;CCfDF
zG%iE8j}K%-fqZCXF9FF>F9y;kr3o`TCA%ac0l{IcoHRDOO@~hIWs0bg`HA%lZvk$T
zHDsOlKCon{X+@fUU{A4v5h}r3`DHL(3`bV;T`AV@(p8^O-#%2`<{g%NA>73vc7IMi
zS(~IDPy*^3Pu|aK*xlSM(TcBoOlFw0vW)Ns!{NB--9f47fA~5FwsiaUdnkhatY}v6
zxucU5<t|vfa13ocbo9uD73p8Dkg`P9MDhs8l6JVXnrUjC-fQj;?{{A){lc^MmpwE)
zjj5zDAW4$4k3L5*xYOi6<(GVG$-u^;(gErVrRFm|NB?A>VdV?e_j}%*`QcOmMBwb9
z6Kll<_eglQ`c(6Y?u2Kw-RV~IU#xUSrM!;?v6vq`5Lhg1cA%l|z>8`vcE8g-(7n~{
zq}xN1k(Q%pyhE&rJOSwkNsoZ4)i9PvI)tm)PB+O@jH7GLQ8l~oz{2^`FA1TLyYr+y
zuX`03S+a$r%!uTGY6)FK>IDF?erlHKN@5Ga^c#LwTJvo43pWaJlG5?1t<Y*~S)rgQ
zzQ7Gc8UKR1MGc^Q|Am1Yy0tY!Co0*vty$l6d7;7Tgg0m4PJH*Re<sEY)x;}>@ePW)
zF}P0O(oH?`HfyWJ$|@uC*8>Kr7~&V-444X-N^t=`lG28b&uku^&NYq{AJ~r%`_RDY
zh0H@{&v{g^zp0YpLcKU8JO#RaNV%;et))N^PH4f^I$K<)KO?Rn<08q}!`c}=;9s4S
zK$;YQC`4J^VxsS!#%Ye~D+ghOYm^(gozIs(z}1idptCZ!MJ94}k};GT^w@WsKPMI}
z@Msj;Q<S>tMX-PLV@q%SnJ$H~R>g)!ZcCs{3qn!&{{x+|`P3H<5=f!0&bGGxgI;lk
zx!P0CTBGMZrqJ{LQTof|{g%4m_%hlPa?uBD?+DZTyb0fWExsL`OW6JaT5{8(iH1Tw
z9YpP%)*c#=_B&fMlEAf?^Jz``6tgNcTELjCUM=^FGvnl3x1?u8Q!&Z5t1=*CN>M7?
zux3}uIugW_yTXIohR-4XRDkD51NT6=Z7z21KD|2do==};iHwaUrhFU0L=97A9Q3F`
zDi?QB^l)>@J!||V=s&Z`>zc=rqB)HJN>IM^#G=DdfA0lqS8j4Z2@h@4Ft%Z$zf)m?
zInTbS(&ODHp&=VX4GcBsV#v<Ed8>{Vw@BPpl&)4w)yN>tO<L2pbNbJknKCIYV#(Aj
zJe_&k=E@1E`^6PoW@I|>VutF7>U3xwts~QM9LyYZT>L6QFF^qTB7`-`PZcil-a+UY
z4=u5G@Oj8ZHl-aH;AZ)Rf#W-9f5?<=f<98oNAX<MC*FTWid4j5oURu@Aqeanr@suT
z;!%?@Yvp<GdzJCFszqHG&7?7hg^5CCj@q`d_vK;uvQ*RRx7*FjOH1EW0r)`a0~&jf
zl>@hbU>}3QWT?{GUKR_{lLLjJEVW+C?Kpgrj>Q~G8oC3-M0=gJz4v-%Q10UwE2EN6
z_$5jn4+o$H;;uAbmt`+2QmZMQgF4fZ<!W*~)q=Z&I1Jk{2OR(N_@tCB2(~-DvEjN4
z%z0PfDSxH0X}Aci1e3<xI{vCbnHnxB4d<jbq$*TjY7&>1YJBvqUoHXpK=R4LBh^9P
zB4~aWWTQ#Mn-2+nN}xXQ-3QIJAlhL0B;tAdRfY)POjiZTh|e$z*&B(NCM0X<ZY3XU
zL2(*|pdfpah#B&Sd>P5Jn3UyC)KVBQ4^lEPxu+k~L3vV#UzsC9uwV0pL3Fc)m8jcc
zK{<oZ-P83kvPAYQ?k!Qzf?W|P^=&AKWG~3XO49x|pvQOr=jmHZUQA!qd@142kc*a-
zWHZbI>Qx3v&}kp<lf2EhO$w=nNJENFZuD#FrCZ%00vF&OB3q_)Os7eUW5PQxRLH<%
zBO#f~g0sRQlJ!=P0F+z`PF*$+EX@$!D_J^jVtkW_m2tQs>6yZH*cL0}munanLOXmb
zaYIsaRmilv^};#Jp3TgO6b0bbJZ4GyQ!Xz;yL{hr{Ek8}8LPlil6nr3u2;2PS|=dp
z0Cfuw>$`Ff_Wm`wInZ&eDIE(I$p$rxN{>M1g0v@^N;1>A;{DVwcaL7RAaj#ngS=#m
zWV7=}S?$20eDnUOh#?sncs$|pYqoDxJ<D~DRtZf9tJ#m#$wn|o+#c}`5NiGqP8@f7
z_o}2;GMf)r2TJEF@M-LxdGEj+7~y5;y#f{2W-L6pi~#zltxL|BR|hqOI~1^b<x6u=
zk@Icy+t#jT+K)0Ngtn{PZEiO%gpWRZG5y$0|Do1`#Xy&B_D-$Z?`g$>?(-f6wC5o<
zUZ)F<FxV+X3OE)xAV2nDcgop{R0l<u^hqJ{>{d(CI%fx_YqZ~UUS<ZDWa#bp)6d0!
zIE5^8#xUbvtaV}u+=wq61ZV`R^wxQ!3%$00Dnk`cBzs71o+P)XB>GzhRjz;WHg5{a
zBs;~0h9i}e76A-X%LVz#X7V<2_A*7|!QNBCi@PLLU*C~GZxUY_T*I=tl^HKgF76*Z
zZ)=(NfMoYt0u9ZPssN{zMt{_4+)T@{bScyj-!?2xVK&Un8=Un38&pR8sATB@Xr<JU
zWL%)elk3z*>MSKGN5vgANkwa$E|18<u=t>g=B(~QsD#TPDM{v|ED12wA1x_L;<d%$
zQ$7^c6%0U>!)}(_z3<N;S2VA0mP2Rp0TVJq78W^wO`X}cq}vN>a9V5c(9}$GQP<uf
z3ogCzGUp0_95*OQs@#~X<zWkOx*-!So_8%zB}Q7&(%UoigL&3dcU8O27l;-~xyL8B
z_XI!(X5u*&Helcj*VI_DNk6Uk4y+><TSr2qi-sd}^u)I1oJCKPbXVVBJ}~9`jnUiH
zrO?=yDQ~8&@r#4ka^3g8#ZGi%uJwl{3wvfk0vT*}0nL4zxj#&eVo23abeg-1CX>hy
zmb_<RjRinnZ$T(jkIey(6F9#;*HM7(jd1Z9pz@rxoHnAe-MrwnL#T0GZ)}RT_ZRr}
zT>Sm9cTr?DtF^f9&EhNXWHfv(Xc*SI-+snIhmQ_akH`kYr6JKRP2N!spQ@_<56w%i
zcTiUzI8(LhYp84ycsccb-_zIbTLrzjdDp%Nd(V`f?hQD<62$FdJVua%l}apX>4!CG
zeU)@*5NT$;a&>mpd$KZ$bdwGCWYwfcNeTOaB8#i$eoL<ek?<34XNTSsbOZ!Cbc9&)
zWZ{*0Z@NBUwF}>XL#BB5W-+y-;UgKaBRxA?@!j#Oh!E)?VQ~b!Pv{lP80~L<XGtZJ
z2so3XrSV6gy_qi}+FbH+`?h1TVDM8(-hJggtd-a+VYH7-;hfd3wa{LLKQ$#B=b`=H
zw61a3cWf<FM*9NBm->kt_8d7y92HS91$^dOzWvi@T?Qg})Fan0y1@UoMz|u|e3Cs|
zKfk@FRz=LJpHr{+a;?clK5}rn{-6Yly(B=a*&b*q+3f{UmPprpLEug44zcWNf2rek
zb7gUp0^XGL!yx@6dORm(8#MDTY7f)f<*l4dv@%zHN2*hZZ1J?_>gVKQ*Nm5_HkkY&
zX+LErDyZTfqm&)@uLo9|f{`i-IO;1U{krI!)B^k(ujC>&i#12xx#$Sxd0xSCCWrvH
z29;Me4Svfpfg`uG&ooVc4-rvsg@zbe+%ZBPn1NhpSS3`Eu3XNEym#lP<r>}1xRKly
zjm`iVX-+wJT7NKi|5x_~88~E`8ar`Gct-WHC70O=TGO@n*V=|@@AQ_dt@N2GvoLBj
zs2}h}ngc66pS5o~Vl_JrgGLPXtk-NUWI&JUT1h`2N^x-1uUb&|@uCBzbt^QK#M)*W
zhZVb9wfDOBcN10O#DGvNR1To*-^Ns<ZEC%<mmlx<m-r?k*f4l%3<_~iINacbuXR&z
zCB|w!)QbDR_RJ}uTzSF~W+&IKqkIjjaO~X?K=w-K3MLC%V38A~n}ngvmJ6fhGGss|
zf(H8)++!(_4m#QOTqs4y1$Ed$FG`reo_ZB(SM5-PC~;#DZiv%K`KYj&b!&lQtheP=
z2>7<+VdF1h3FUZUQ;8e4)JUy={*K$)x@M#}U7`%hCQBV9nN;m`^V)q6P?5oDALynW
z{7eZ|4MxL^iFjA7f)X78_Cx`t8?tGtZ7KV~b~CS97E}VSHyGdp^--Af^M!eTs9@cW
zt!mUiwDd*6y@VX)S>N<Jyf?Uei3<h7gQq69%h3w-bgOd@UfA#KP9D;mD_%F&7=akD
zMtKQ4i$T5*H~VPyIq0!d%e?Ggp1UQ=DA>Rv<8wk9k$xA8PIk~&8e1&M^i|)sc0WT%
z0YZ<{S-51$9!l#6%nNaqgBN1s=I2YL&O*+fs7zEw7lf)K<Z}rphz%)VU64bN!yW4*
zZ5}gRylcG93*MBcWJ$O6SG%T&F1#Pp>VcD#NP@LeZxo0#KM6{M=`V843V?mQmPwCM
z20nPZEt)y7!&5hDvB8QD*Z=PH?Sh*{_k)uaW;!>v8HW=~tgYVHt3TK*t<otrGFO-I
zHhWP}mpEM24&HN3lAV|qqtHh5lQodZUhkGdXdl)ewwKjj5?U)u6@ttJq@db^7Hh@>
zW8{O(Tqw~rkLI>`TAsS8uvJ|-xiTK4B2ZOu)n&aTS5C6t`h&V22KNQHsboQbE%CLW
z18}y&WnB?8_+Ki=m*<yUSuqJ?VR(M{lNh1E>ISE)4G=ot&%_bxtM32W*)t0xfm2*7
z?Z4I4W2B=a5z2cEkSUoNLd8lYL&~AI$_15)YZxD~LqEQ)joDs|wKy8w+k|_aP7W?$
ze?QdS?2vC|Unu-AeiO<UEMzH<bLZ~UrqSB{iB;-(p+cg<s-Tv!5FBfu{}#Cq%P#HT
z{m!z*22;Ij9a~^)bHp5S^OfA_mFB*ERFMrZI%nZPX7^7KVs7oo+xE^|-QKVx%%xXb
zhffhDS`f8+u|C-<x9|neApIeQ?jp!SKp=oRM4Kk0?dI`1!qk?yEgyBqRTTO4YSej+
zjM0I@+cd8LSq*#)(7KL>sasU#yBk-n(sdf-n7DBnP+N<OgDf*&tBN|W9+GhepYD<V
zTi>`X%{3Hg49qYn0B)8l6U;6_1PY1)Bn)p5@()#^kX}v^F>=VLCwp6su1ki^;P1Fe
ziIHM@f4H?+DN`bV^+zoqrRW^{gYS*TgzPa4iKljXWzj)kjAAwiY>S&4s4G&26&Q{5
z%bkAw2|3-secn4fCV?W(Wc@)(Um*sA3Ldw%RyqxDp%9ox@t~<6BlYsBF$a%4zQnKM
zRcR>TUV+d8yDJEfSsW|wmKGh&GGK-hs-KyJiKoP^lH1F)mHP_fQL)TN3|MvsV?x?#
zB3kNFGLg>lLGx7_6j`qmDbZ21D$oHEJtuXbi)UMNpQXlI$-CvE`;3=bu<b0A9(oM+
z7q(8(?6Q6<v@VI0_<gU8Gz+i~%+Pe#{)m>nG2jtdPIS?3(1XBvNlaaEbI{DcI_;q4
zKi|^KQp_JXRCJ&xT*Ao+c*!tU#jEPxVhI-3jpe2O0xJHQ5+{Sg8u{W1=C1I4En7f0
z{BZjTGZRVN0n$foT=ua<vq9xv;9_vY=7tym`YC-CSY8z6I;5d929`-CAA1$;+Li4b
z^4=~4L9sMs2{7nkIb`u88>JmP2yJfv1#iDeM$-aG3PzGjup|=_js&CJmX`_s!*4HJ
z^%a`m2Pg=&{5dFntXS-C?)d>C#MS%oGn((GDDs)_F9?q@h;#;SS5D3QkE<lW4bvVx
zp=Z2jM#tMr<L5{nkX;U9;`u^gfJq$Ro@yZqfR}{4REvspcJ@_>ES_XqU$pN7KKE%*
zO>CR~A^o=k(I)d#%YvWWiK5=!?471xz0?#5OPTB9582f6R1t27y6n<&6MX7>x0Z~s
z1sy8@IM+ko3uanK&wqh{){;aCW>oKcF!(|5-<5X#6d7XKudNuCCNzO57Oz7fU1Dn~
zXK(i0bEl<Z?+wTv7$=6<RS1-POwtj5<U-+QP%IuL#AuWkpGsm%FlQL))X4dBsPZv`
z&g(=w(s)Z2EhM1h9fvt*z<_UwK`xSP+=mg=rDH?ZxD(?5sQcKQ)PqV$CS9jiEaNBt
z*4s<geaO9qwTn!%LSZjTF;#B8eup5tP&fDO%B=>^q*X^&){TtUt~DYqQZCSyOyUhv
zIs`r223}eq%__O>f|UOTdJGpt+I7rOQx-gG@qr@bO1@p+ZZoS;01bipu2u)D7R1eo
z_!I9tBIbb`@-4O6A^0(o(#FlF?mpOjI;ZU$FwdTwJyFO2n3GQ!nj=V}R;{2)@@YBd
z^{8=c*~@bbft`}+>r%u|i>df7ZI#Rw#qFZ#nO0K)lVFZ(EJ?tdL82U6$B8C&^XYiZ
z)=aJWlL2pg=9dfNHd-FzT<NeSGrPoI1sr*4)Dh^kn|xh4aMap5l+zZIWlKh|tD}H1
z$0Zpj7^a#P%ufzoZM=<pefc0QD}>;eIk(Q<U(nkuTGGJz2WFDKP6(yY9G9>Cqkr@1
zwYLZPVzE}pxE2)iF9wYJA*DZ{5oB=kyH3jne61=VHfddZrFyH*{aY%CO3<ZbbF#QI
z6K29|iDp~gKo9Vj%<TQd!q*;otcsHojCw7+Y;UhF14YQRL0n=BvVGRJ68UOL0&lV1
zxq0BQIa+R!LzEGl+XH9>J-6}Ra{J-C0%`?n?(Rm{Bh{O6Kd>X2bCs8d3J`Xg9mal3
z3<(^x9Opgc-r58a+M3)86e7Nv=r?S()EEs=V?`0hTg_JkR4DT|0q!Xv!Tj7KY9%PL
z!kp1_uSO+d!b!bNf-#-Zywlp&w(XgNm8(=w(gV3l)faCm00G66<C89e+c!N23HR9n
z&G376vwj#FkapozZJ|EFu1ri)9hZLY$p9Zg4E~j&9;V@1KrNZxxVto98oj07(qP7*
z3S}<Kw2zAHH8zM*tSfNCmtFiPZhUG3YC0YfxVmW5rEF5$3MjOCV6`qtw^YZ%Rt?hN
zsJ9tNm2z=~u)YX%tGOYYp55kk>I!s9o~~QpU?M5*6S@v&8DGh0*tc^Tfxc)(^n(mm
z=TEHbCM1{u*2gg^*i}lvSIQI%k$O7RoQx4W^GzdI7}Zra4cp(#K$m<eji%o&xDZKF
z0ua2003KN$RQ~bcvIcX40EXYV>A;AdGv)ZZn{i-rwAx}uQ(sZKPR)sudVB7<6*9iy
z&0FY*s5*_I-#hynfdKbwMPuvit8H!m2ZhI~JYZh@G<@@4G36&Trdi5Sw-()UXXB*j
zlNlh>;f-de#D%HF!YH?(4!XAH05bS;<Mh`vC9;G6FyKuLtb<noF&ms)n(9e;Fcf`3
z0cEJ#vSgdO<|j+enj>=(feV9&`Ux3J$=*oKQI4TS$i9rGIt?#-LAtcax*w-utDs<u
zq-0?i8L)oblT963<_tOb%<0nj69WLgom0G-$L8>R<bB{?j67Mm>Bors!~@5;=R!$F
zWdR1BD7!+g>{MyaQ-Jd*54)YPL(?B+u1!%GMgn-B`4_uSu7Z3w*gLS@f_BE35m1E>
zvLDP5Z;Hdn28c63`s>pZTOZhbYX{_w)I1v8^qjPc#n6HL3fP~M#;G4uKq>{apkil(
z6vxOs1c};Jui=5LgY0D!1(kV5Ko+gRY}s&O=QH+XVU7-}(4)~jpkt!$hi|&Cw~G^k
z`v1IHDb*-nsQX>a#JK>l&~?F^e!P*{27$aE-nbGX7Z*IZ<EI|!%iz;IYfV);H+fs<
zs-UaYLvx}^fcnK>kJI3XN8ZF1uHC<6(Y$AZd;yFo1}6j+henj#dnQiY1I-Vk`AKgC
zp>_rYMU=ccC|+C*4*aOYfar2hJ5=<05cz`|F6DxGu=Ghu-(Rk{_Uq!yRPkoy+_~$Q
zA(7rJqYTh?*pmVGMaUFV?4(1=Z*7G!oU%K}hX6ZGkmLaM|8c-G5IRNsI#uNU<XxN3
ze0le&)%#1i{m^vJUSmFx^h)<C+p?EreClPn?kKsyNZww)s{Z4|(!vzcvJOt2L}wUy
zj67;SSM%lRWYf*x0KX|sxh7cf?y5-teg5!HdLJxSk&2zz*s(cz@~-xSr}nn*Z-xU}
zS*M>ay($fSL0JUosftra5G7vikNvKjVcKGeJPN+X{Apgu{M0l)mhvkcy#9jMGgMIN
zd9M<{{NeV%rNz-n{=E_GfgpyzvwPJ^bAL(GC`@s;o29Dzjz<=e@HFsgYq_4~h4K$y
zzTJRsDcB;Yp+qkf-l5~y=8T86Z#U!WBKi92g;TrFO5lQPw*+hn&_*grBWAAk1@D4R
z)t@w_-a=Kpj4L}L0C=G2y#U-3%WyNE6^2lPm_?{FbVL<6_#5^S50X<br0B;%%z~1i
zPD1}DG8Io24<4pSN$(!$p3wic(mjwJrPl&JRCTB@&qd+1R|NX;rm(B(_TRsa84CI>
zY6=}oE;EQx3C{!-UYqN=l9TSpl#vp{Q6*2&w0I&_<{Rz|RG##FkVvzZ>JHO%ykzF5
z@MG{ux5NJ^L6N|zU`BK8q*3(9`y#L`CM~Gf#+8LyO{%(tGsmC?%bAM~+kO>;_SBP4
zNXR1R`zBJm7@^+18?4<<6r$ra81ACzO8S{RRtS2z{A!iOzrE+y<(8Mkm?7CNqAh2;
znB}0GqL$lA3xsdy#DT$;4Z1<s1RDsr>t=V0nsBy;Ta%?-cFxSdpsN83uQCzDWYYF6
zxYwj@iIr)ccN1=r2Z9O<aQLi89|WB_Po8zvQv0i;_i@ISOwage61pMQOxBr{6g_Af
z4$G;p>~21-<F$kNudBFjx;Jo=Ib6JUslj`9sWMa5e|@{D;8LI6l^)5mWNa4z@v1x4
z=70=?DaFMD(u682vRsue7cWa3Ui*ZZ>_ift7q+OG@G9H8rHBxqbn#?uPB!S)?9=5U
zfJJ!NP2eygknjOrI*~v~uUzzo2YufsAy20s-nD>B8)G$k3yQmbH-Dp#x)GVp6eg{0
z_RAjN)!bu+x98^hCCxmR*Uzk38hwkYfqt)PK;IfVOCvDDO>O2&>y>@dxgJeUld;{j
zBnsFTg-b(>Z9sx+rYd0cb+isUPE+xK38AeS&pdP8e2JrFcBa>hnPLWw4=^0OA=)1B
zU2T_!q}|srr72WSA{(>%7IUIBYC*hk>4W@=xacq2^rK=9&k8}pYZSN!Ux=ifFd3|`
z?ACOKhKxS%{e=e`djbCC+k#|)m(Bw--3X=*3RrXd7Jt9xHq&V7E#ATEIbKQKNh(jY
zcy9H+#X5Le6p`kTPGfV3^|lq_t_030FGFxMooqbWuF_gg@-&2Guwr{bG?`{QC+-P#
z;XW2LNSI%yL>i}!4OnC(pu6zbWC)++*mY6Y5#=4;x@Q4NN@l(%NYX6Q<H+BU-$BHK
zn8XWfw%J;I>D5Tk7?lPpSu#n|Kt(F2g2r-7SO32rx^<@)CA?jxYU7>cYDq28SbaHj
zE$G84+J)-7ihqYkUZWP>SAAuMVE{60Sd2FPsL6XUU$e<see#jrMVw{xlZ6u4*Go8D
z7ieKzCBaq|do76HkU!;PzLp+*I3TnM|28WGtAH<??&|Qo!+y$_?!{6ijIJgz06!H@
z0<QT<yz{$upGha&;zGvVpS7|8saZ?}>m~~&BL8zbW-jl0y#8O_R@}1lq_yx+1Ya|Q
zFr2JFH=6*XYHc_Fu<JdN)0tX(kNc`Kb3)~RgcZ~K9M@DGD{^3+yqo)N#C_lR+3{BW
zoIgHC7ci+}eGP#hDuA#RZniwAh2V6M5w{$;sdc=ljr-Ae{OB8nArF%9YvPm344}X#
zf7iK3mBrq}(m@^?&ve>$>oxPBB}pRs;4;C~`ox=)vzGQLB<AV%&0ONC+cM5~?cZ5)
z)Qbh9tMEmFynq~e04~ai?!}YVq%its{u18|971k5zdMdPSNtCsp~mFN*#6Hpx)H6{
z>t4t_Q+3D7)m}-XW?!BYu@nAJ;T3AH7ImQ5ICcx=%``HAR2oY~6GH`Nk<-$I%YE4n
z3NxOn9dgjzLIxk9(>4M-#9DO*(NG-=`F2~S>l4e`5;Qrlito$q;c`nLvW#!@ch>Eb
zUcB5wp?egaCd4tZ&m{K-2CRp*pXHbeEFPJ3qB@HL$0a$!#0K>e36WZr=%XD{T17B%
z65>z1{e-@sU?_`ciDE;wby5{BA-9aZq$dFveV7iQmujm=vmFul03pYE8LhJ(jL%FA
z-3DakZ}A;4_94GIMQ1_m7pboRS?y@>;mL25J-{WMPMSimK36*Xp1EKRWM8K~RG@1b
zRSMk3Za;ZB{VCjGyLo#D0*{P==>nn$dK~?(ODOVZ10Odd0?;UhZdKg%%$bEtVua={
zJ*hUZ{Mx~f+~~l|xyRT%+*It#B)y`QGoBr|pr4z|UneFCtX7aL5CnkqW#Oh?lfELH
zJ0Ln_tMXQ3tD%h>w)I7Stjy(;0hIK74m#2x;v%&j?X7aR>o=d=d2sp*yNmlWMeU)=
zdkdLQ29Wt16$|pUM|nY&UK5vU4RoFq9D1q5Kk~c(?4QW!O88}pf)fc?-^@JO)+^2A
z>&g2;Mfuv<Q@ioO<>;x5msO)4cv1twJ)AtD5gKTjll!R5EG=w3yS3Q)ym#LFVr7dL
zBoHJZmix|GfV3Q1RO)iqgip*}CkBO&A3I-qz68`tiFkBmS0Sikqfz2^u$Dl#$;og0
zSHXOPns%H1{oN%>Cg1CR&&*|>37X?tAI!}I;R`2R?!4el%hH~_=bt>e!&IE)>f|1e
zfsm@D7+&3=8*2+~FxAz`o^T@E8mXJI^Km<BrBy#40u38>XKW=OIxz_<s@c9CNk#MZ
zRwQQUBaYV^G8Nl^Ws!{<8H%4wXNMijJJFO5+a(5HK0mFWNY?4mgco*{&KqC+f*w<q
zy3e%;W#0)Y1uf?5PAESbQtB4WNID;ZINiWMDha|wn_o(gs)v*fY6CJ#9n>-3j^z?w
z1ZT!Pq30vV^!&O(p8}hx$}~z=q-c(9+j%G4xFVwTgsBZUR{p;6Kh<qg>oO+q#|c@?
zkK3T?YD$Z!=3r{TR18OP%$`Vt9Z8fONmM3g48@EkHpML~Zx~OgdFZN&s-znuTvMkI
zG8A54RW6dtR}zte9Z_7~@-dai;?HT(lvmhf@SN%OE2Hc)|5p1*+NrR@WB3eyoCu-z
z<okS7Nhj+0zw9(mDP1DuBV|QAW^eJ|xF_;IZN*AN{W^BZ`|#+WQ;``;gd8=-zwwU=
zEfPGc_NDf!9FLOV$yJLdu8Z<T(Q5zh^5fc=#ys=B7eCU9&v(6Vr8cc_hM|3JRFA2#
zSPZIcql;C_AJ>}nNmDmlCQU09XM31#=A;Iln8N>QhhOhXIh8aPvjNaZ19lFkdwy@G
zu-9pj|EVUN<S9_el4<0q)u1|*z7|v=j8?oJHJ-&giaN|ICJ7vpCktyCH^N~K*o189
ztUqXbUP_%Z{`iSsyZMIyfB*U6@9g}Q=a5}m{_(3nS^n?A-_nc@{Ny>=O-@U#i^kN>
z>3G|8TqPHgY$L5e9b`J4ck8`L9r12p9N8*8WY$INbSKIoZa{ovJuP~qbF$TJb&|T5
zj>cNkM)-SPGL%BVZ8cvX@f}-H632ZzpEM(;p>>8DJCG;U7~N!yYi7hXddwTs4G6jt
zBYzVb2`e$P!R5wmX_8CjS%rvlB9_oGIf2BOzJq+Ed4O#njyFVN>Uc=8j6{>8>mi20
zGmOm$)%js1!?xtLsA6iVs1;KjJEcbaG{TsOS$;STaQ@+@e;)|2QWrLdowOGkONLIQ
zl{%OAu!p6G(;KJ`z9{QltFuFO5#%i&LgrGst|#MX<I0QSlpi%b4T<BQ*}_nsYwfun
ztIoTABoT|mwD!iRYKt`ct;rTQ?Hk8;4S(|A-cLnR>=b9gajE$b%SuHUM4E`ysbM9_
zi$qZrvIt)f@zQ7YP)0a8`HhC66gH`zJn*7tI+~}nPEX6VlL}(|F-=n(IpTzy45^JW
z*{@5kj`PiU)XLXGuSwVOAM2v65f4?8ikfn33u(E<jxrn_j=G5|b<~QlUgTO1hdM)b
z_N=;AO~ertE{|GBhE}1Sl(C9-Z&>jZBNg4_di{CF4aH=3FX}px%xP&x>8+VjQmDkS
z(2SC=SEHRF2NjUAy*rpK?WKI(vUw|>&MWht-tj|Yy!fE#h)zG`T~iYqJL>d^H~eVq
zY%DQp^V&SO+F&G6ZF%=|dPh@egId>Nr2Md#aEeKT@^5(u4#E_RwbpM^6CZu8^+ddJ
zcEtu2{iI~ll@%|B951`zR5-0vzpeIrjd9~$H|e;0(@KMW+`=?CRzo?>(mnOwXo4-d
z<Al?2-2sD5N4%9r`$*i3jGs)l7iO%MP}WUqX`{m|q@yR&iEvYW*-kjqF(+^M(L9@4
zM39UIKfEE<j?VYMaPy%;?2}jS&g=D7RaH!7Pgk8D@~lKC9q3s!n9><i>=||v0Z{8y
z|1*hD;y3c2_dmnm9Yaq=Vw=5iXGM)QM^3CtsI$;&4Kt54B|f7%=w}n@QBo15fIN1@
zkS>jIjAQ@g>uJ%b{7YW9qDnS`8lM@7DBajeUfV+1*YTFUd_)9D=|hh8IPGkxFHdfw
zdCgQb@ra>^Z4WW5eXR4`eAtpniy@Io)VufZAI@{;N}8ui52q39u}wS)&lmIZVJ(Jw
z(E3^<N?m+#L{SoHBdWQ3JgM4s!#t)!38U}mD1YuiqC@2>A8R*e6;-=v6y0Omo>^We
z%o7?Z-fYXPVT$tjaO8<Z(&6P557JL0p-1>8q6|m!EM_i}-|J;U<_6m_3x;QSNp701
zMH-|0$Vj>MQS4|q>BZU_)UcVHby`<>;X2drFzW1ZA(HPmu>46bn9~wX=A(|Ae|LJ&
zFp~Ln)J?jHqU&z(Km4P&C{6Q_ntXDk-q@%rbM?{TdObPdBqB~C9(62*tCmm4EhEA{
zrJ^Yok+=O&w;Il;-AJ9waW(xjX`7dBaV;OW<yidUq^%k%w<yQX@S&!nb*_)PRARa>
zIZ)4NwnP7|Jry0RSgeq3F%ur@gl!G62`OWjXTIajsAgi5Wd=_mcUR7nk9WL~nW!(?
z`2(?HyuB{$DQZ$_2yd`3{w(y@-RV?VkLBxQVg0aCZZbODHly5P_--SHJr+*pRo5sx
z4u5<2j~ITMh;;jrbRrokRB(r6ta94SN9;s|ub#)=UzG0?@eUh%;*2G|jkcqXg;euI
z+K;t(+FngjE}Ajb(@-X#9n&61cKJP?+-TaomZrA*EumBnZzYeu;`E)E>Yy*{Vpp_q
zqTTq>zy9Znn)ocsOn6Bz#H+-zNhj$=OiMW&-%xuays20|q$6MA95Rp5Gxxac<Fl<y
zv-GX9XEr&Hn+g5yNdB{{wDuh1zSVHkXPTqQIyV+^+Cp_4obCnNmz-t4buAHYafZVm
z{^GAhldE1naw6?GqCUIO$iYT4EHoneSxFhuJwDgU&!gWF+f3TmwPYx%G`r3ndTVGe
z?<z4BAG5=4$(&x|80xGkHDyPViKtu$JF3^sa!7T4G89X6qIuQt{_xi=#c@34**Lzi
z++?)7r{t|DBEyTCsR&Q%`J-l7Y3n!Sjkj6hl&Nv+Tev~PQ6=Ml7QD?91LSD5n@2!G
z`JF~gOE5^4rRKwHV{K#6ycR;P%HK^zHsDb+T2jZ=G*?;|)sz}_lw&p*Aj^+Z5sR_G
z{0}~3Je#fYFYHOe{S0q{9nsB;Ci0_r4WDb%kd<TpF~e+&@D>l0!|8N#gFEI&r;oWY
z<*@2EMo;>-8jFr~6#dnP??3B1#w*Tmt@t(dn4RV#<m1>71=l2Po1SN}<_MOo8<#xo
zId)$6SNRca0&gavO55*<5~~aM$u_8(!*=9Dmts*o)jfJX>hsg&SlBP&!0Ha$cp{0u
z7Bl$a-0nnjrhlc~Jvd^TcK>ii?K8i6-E(x$i=-<3htp&FfYn{K$Mj7UP+OU#&V}1%
zXJ+iq&t@yOsrI=q`5o1Us;?x6ldH752mRO+`of4&^x978g~}D9<qx!`Q>zkx**e$P
zU0$`;U$v=k&ECS39bbL4zi76_Hrd0Ec>A?s^Sbkt+3SwD^SPdR!&dD(O0IkI)hC>D
zhX485@`O67{XFK5b`%@j<a4gG*&Wq7TzAdzcu^hSs~)XJxC@0zd$?i`>kH}lllDqn
zsX|5dUim_Q;S1_3p+Zux*x3Qk^j6x|O1sk=7%4=$r?TdYw1>z}s%X-eT;u;T2ECYC
zu%B1$3xobf8<;CT+`ZrH+kLH6?wf9TQ?qBw4dqhP`M%?QN0S$fz53U*3CniIroEN9
z&0p;MzBM@Ql(ZwWg&$=6O~<Ewe|2@8zuHe{cWMnoe$g3=HchEdyNRi(<9=g*>tS_l
zaQNxiq2yD>N#jprYg*R1jZ^BMw!{vrhll^z4zG-RCV9t#ZuR>;rFettm*R&UN51X1
z(`v(%ZKme^0c(%*iax0}a3tQyq-A=S_!9hQZ|sI^X5Mw`qW}ieW-Bp8M224&3@lI1
zWHMl7!*6Qx^lQybvVLBZ7nyG^#beHiSi`(_-g4h{-lWqWe`zi0W1;niu3xc-T-UUB
zX{jlHb?ZfAY{(7A#>$2od)jqd-*tAjo`|hPt^r*gzOGXbJMQN{KKNh18INQljY<9P
z=yt2LvvKEGtL2!6cR)Ru%}$yl*O9uH{UdhfPN1E+6ZMG*k-oV*-apq>viQ+hZe<$4
zsC;3zT(2L6G`D8wk;de!cfRarDo`A+>o1rQ|Ml4x8Rj@%PBQ$h{E<7mrhfBZ{>hDN
zv#aCAk@1JK=X7~!c};p{W6Sx{+4{?VdfqH=JUabX<5T84$-i==AQs7v*hn>|0Hlr`
zcUQnX@clMFeXUSF+fs?GdfqK-FPBfvo5s7zmM8%3@wMY?w1()3rY}7dZVV-yWW-Z;
zheiy2x_-njSztEl*jRnp+EF;<DO506UWs~^lI7(i-fJtiStsh9eCWvdn!;|XbNv(b
zN2i~2`QH?n#}4@u=9*l>j(yzGaj3kiT?4BfZz|o>_=rEKui5Dw^4DwHXAb#V>sO8S
z#@kl0er4mSs@M3YKW~%=SdXS^ANixnrk%dh2p`Sg5c5V}b(^N^-PSM$!_$-RwEUra
zqW-B^Q&}tIe82VMAN_Vdl!=$??F?0_oK(7zwm%Wi+<m`u$?`(OUW7qn(RZAWvR0;4
zuk7%<&RKQ+Af6@buq?QKr0TAz0vqwP4Q!UR`R`TLRGxUZEnd9G?S9^j9P%^gbG!Tr
zx8?k!hxQsRrMnyV8V}`~iuJ=rxHRGBID>TAQV+GPW;@(ARohu;i8`rb{WpErsPFLo
zrqHl~6eyd&Tpno*H%|Ml#d|mhw<+f;AFlre!s9ui3}Q_`Z)YT$>FW2D9aegeGp0vI
zV8Pob>bF^TW60d$Un*I))O70$qzlZ((1|KdE)gKyoLA4?bJUsUd>UVI*X-Loe7$W&
z@tz~&>)T#1e`Xl(w3X{Ozv!+htl8P<+;H7YvA$3)x5lDp&w_i6l&!|Se{!-s(3q^c
zNp)phPkPFU`Xl43jh1(vbmQ?Dhg5ED43&}`jPg$MaW~1HP2jdq_!G{D)z09$ba~z`
ze~*<}#d|YTLzWkZ3bliDMMOF3mH6&RHWT4~n2PNGj=4_c4IiN2A2&+%M|_1FVz!1&
z<%qAZ+1Kj6uTSO<YyKK5bH@k*^p(ap%T;sD&NuviEqT#5TKmeq<^$b(rq_EB4%jw1
zlC}%83>v?yt*m+aDm?iPw`He4!7`Yl<CnF@w0Yd!QC_9G*OKoWYO%g?#$BU1<1J<F
ze?F%u-;7fnU`2aMY1t8FWFAPx>56>F5wL*B4*$niCbB)9)M*8$T#72nZmYk%-Z*cT
zxC+Y3*c#uKx9^_gCz`A8XMXn@YkvgMDgB$;CAj;W{tZpD6JYmq+XhlFc#`=WENY-J
zv|cY+o3GgY+8QmjOIuU#wN1G(FJW*u%k?`n<y`&ewDGd9AoZqE_P=@Nj-HU>(aWFW
zEL%;m*Ja+kYDY$*w$d$E@-<7zN0bxnaZkj-17=Jy`|OTK4^6LOs!Kldq3`$3uGx3O
zf8AX(a9Epg*Z56E?WkWatob*a|Fdz!oo)QJ@$%VBc)~yXj5c!JxNyx#^D?og8rM{s
z!cVlwby;y-E@Qe+6aMlM*ClVdx9qM#Y538$5Vxw2!0;*6Pd2{W^0-^aTW`JgK&X<y
zy}qc9sF7I82|K28tQ+_B4Z9Fw*SWy9spP$Si!do}c&?sYsroIEcYGsqaZVW@^i7f-
znl~ObxJ_-P2l%==zPqU?3MM>$fo2>2VCqV)Y#HM>s<W9po>E7O*5*#DsHt3#cMN-a
z;|ZVln7`mgzBwLMp7s*6zN-|XsjBaO_`R7uj$;mQTmcq?FHiWY0$Ck1nH*^=Z}?GS
zW%0Lg)??{ZG~O6?TPT`7X6ARgCzA34>JiguFVsg{L$;ZC+-ypQHZ{JiDlH?S7X4DA
zoe6U+idwRhCx~Ry1WIug&)aQ52P<{eLSoo<HM3tc3R+0}((nF8MM-(O7wU<47t=ge
zx6~=wtcw*>d8M{hwprk%>Z)mAOLh*#luJ~}hY}I5t)wff2y|3sZMuVhshctr>2PX3
z$NrttK#jP6yi$6XrZ)IP?q@tPkag_K8?8*Yc{3MHb+9o;R2?(yk7n=Rlm45|-_+Ns
zhtd!7XY-JH_1^R8uMZ#b9yZRW_YNN!`L6L^H)BWoZ;WXB_c~9%{IA=v<4<?;$GbB(
zCV0%&*h=s3I?ks*)}ce+814Km>rpz#c@OiW<<E1v;d`~G`Mt5=X?{<hX6@P9)0ED>
zo0g|L^^82r>CWFQoxagudU*5s^nX2k)&9k(`J0n}VIS?gaVYoD<WmOU@OIuGyK?Y_
z|9H*hiN3t}L|^{R+7t2TcK4&&yU4l0`})mI_s-ilc%t~d^Zh^ncR5ybwD0Ht<f<Ss
z%cAg8)&*-aGarBLukgEvXMh6;wLHfog21)KqXkfi5VR1B^7lPXVk|v{<oOC-R2{;n
zjFr_rR0?FSx!zeqf=t=gjCI~P*uOg-j%A}`$z-(EF`{|ZBX-~ew1(%4X^mltDsh%m
zAN|$86d(NdhjshgrQh+e+aJR`8*f=Y5@EuHr5|7Vhu_FJ)9F~>jE9@A#++DoW88>!
ztA;b90@2%1(f|Z6UaYdmOx;;G8zXLNj2R)XKND&!5k=nZJ0bI8EFT`5)bzx3I<e7A
zH{20xS57*!h7&W*zSVl2riPQfzL6btN8^1qD~ZKg3|Wz)wz<ie_PjQoToYSkG@CJ_
zJ^B3?f5U#(4ykG0X+ty>F^<{J9!FxYgsk0B(;M0p0rSQ}hUe4~X!Z*f)0zymMbu|w
zZmdI7V)SL+7}JR8+EcMXQY^_k%sMlgij}>5htU>Y72Uz`%A{k25}~G0D%=*<6=l_|
zam;m$!7r`;bug?Lj<;+I0pZ4YjI#g)H;-8Wgr+Tr49u|0Q!d6DBZS5v0-sHUV>WLy
z6=n}ov8dV<veQ}C3I<sM<5`ntA53GwF|3sLN*p*%H|j_gxO<WuwaV}gZMp>k2q$A7
z{=qMm)C=**Fgp|=c$TBg@NUv53_p~%>eP5Nor;UHYO@J@hW%(mkwaI9>!Z5v+GC+0
zSoLC@oSKL#$BEV-M+@-d7z0m~qMioa<gM*--XY!}4i(H@t~VTZto9ADOw_f#-`aUc
zGn?I+j(Z{1(afHZcSK9aDv8f<Dkox|=gE1Dh4fSys3Kyq8;JquqOE6qwF8(f+N|w0
z-q1s9+(b*Lj+auLhFHJrI7v203;CdnQ*3Ed+Hlh9H<EeaMm68$@c+O#a~$fo{@^#V
z1hkG?#~bkS2UN?h8WpuGI@W3M##%#O#R7Tu(oT9LT=%)ekZFKJ`(E2L=d{6&{Yl05
z)K%fFUd%|2seSqe7YKK!%bf*YMa~<1MvD%EsJDYL`+J>><FUOLV=;bmQEf2&nN2B*
zMbt5Or#s`-bzll&x#5u6{*Qf8L@gD+)2fi6s;g|WF4{-*!kgZVF}4Y51T^V4hWDmp
zvHVP5`VBMIXVmo>dz@racajaNI_M0)Yp46Q)PC1Hm2*rVLE&L0n-?QLl1<;K4YrT{
zXSY1r?#-Q#x%Gbdgao$UmNCzBdM@Z8ZHygjw2^vkvmd6wvfi*GURgE9LTOd|?zc&b
zfQYa~ieV)z;EMJxX|KO0od{iwrDBmCS}Gh%ChNigAilrRO~q_m{T$d7N2EB3dc?z6
zt2X9_ot|U}Q)pa7f&{)$R_aPNR7yp)y6AYgZpaAdNhDBtC9nIRUJlv3uB9l6BtNb5
z+tu`86Q}^x-r<ir--*bL;hpHI=rQ%;3dcEy#0vDO<hxyP+SDei&WPmC+6H>mQj&xD
zsPf{k8wr+>2yKYRl#UJD>%>m7kH}EeR~|n3*%(H)F1o`55w*B#Jt38g>Dh|j5Cz(c
z4>($q2YbQiC?^L-;%+k4{O3URa*hL#83Omqvv$v3(`Pzh^Cnn)oj{6)$3Ho8efifU
z3635TAkn%Te>@MYn;~l{o2wXm+_Wa}ZbaE&aE=kHZpbtz<FVvLH}$!;DDYd<e<umR
znLOp%VLxxq7T?fJQ*-?pH>HI=YmX-QRh<udIDDnZVv_lYr%c3B5ijBYo{=8)_xdMP
z-SypuaGeod!;a|r$neLfzoWQyR$L$%>!QI%u(>K{J;FwF5IS34-w;Jla^;k|+^Ta?
z$8U%Z_q!SypFua}C*A4T@0tCcuBcnp&Tt{D^)S0=Ca&pfKALo$hFr2PruHEKEot?0
zYgPVVOjm*F`p6lD^^30Ic<~SatVy}Zk>dJWhEnIb^>!q^gFC_7N-KxbJyzASltUH?
z<x61>I}t$w%tA!<FAAdmSrQKkGm3rVlzlboPPxA7fn)oLsFDwX{(6M>$9x3PR~0`M
zttfshpA1_dN+16I=8NPxY$IV=Rw+rEC#BNAA||O~$VyJ98L5lZ4GerU8$M=sf(@H{
z^w?@0wVu#JvF@<xnk~<p+ULW)t$8=xHcQ!u|9snEOWWWYtKgn(Q4M2dYukRK%`GMi
zPw0y8>MKouRP7tg`-8?FBjzUkmRH;ae5I~ge_#~!@}lo=bym8mOf>z?Kl)5dxGo+c
zmmb|_Ah8xJH#k%$&3W)wB(x=T(bfG}RdGo<`Mxr0SjSbp(RZpOQhnFwc7+s|Yf|Ue
z<D8l#b!gp}3fDD6N5jev`IoVD)KaXxU1o1xe?qUj@Tb347n#n7c$KtAUXJv4kbuxq
zUc}}xb;oykX~k{3)8+vQHCK+c#H$(4c1_pT0re1~wq(^~f9vAoQ9#R!zU3+9e6%r|
z@)5;++K*xb^V|i+b#@p!N>7}U^hJC0ll60?Mp#{^K;gj63aT?@07vqF6f#aqT8xGQ
zkZFWWPPi^S9Ci)OE9$4sv$3S6>jOK?y3w!aQj?{G5i7=8reli!%~*H?oi}DS_--9G
zp}~)O1t;W?tK`n-e?6Jxf*$|yFYZ2JzhOk2R3R2YrSkSjlAz?cTp&|yRT=<)mua>n
zBc_}He*-eN%B%Rp^Z4(vExz^QAI4oJyVqwok7N5?B@xZm8_`iWv|&7@Mb%?|Q!+Xh
zRn|C(&`Brc4?7((KQYZk_)m?$W+Ycdw6wuxNTe&I#TCo)EN*4poyvyn21`-8V;y7*
z#xqgVZ7bU?Mgf8MO?6E?VTIjHG-LeG{B3**P+Fi&Wot62?@7aHs0$~zI9|T~K224}
z<1u{xRM>3`CF?BQhR}5CbCp!sQ<8f6Pt}VSO(pO8=i^^B?Us#t{w+J6Ej+4M<LSai
zz4h@G%_}N~;vF^XS6G8?I%Un-eYR=oZ<tpzUolrtzmdC2Vc%D@Hm}27Gqc*Lj{4EH
z$DguS8{XPJ@338R)|A$dmy%%CKRx@`{`1<K?xR}KSlv`^dV+R%JvZDH{BG#{N#_4)
zrbW^Zd|KYk{i5~wgt1<m>3DIrc(}39pIPgUdT*Zoe{J`;>kn7Q$A${Wr^bG+x}(vy
zsj1S~pkMeywe5X>X4LD7*+pmkUCnng+V!$FZ&wR%|Kjo=AKQ1-dego)bI9!Z$kwwB
z-*9{GTG7wNQqxXn&K=q1^*p{J-CPKdJ!(w0RnlYeNh@vrjp^)tpmd~RIR1aT_1c|H
z`hl3X2?wv~Ke_|cUk#s(U-up{=iLG4r!(!{+DE3_U|um|*OS#)+avm;db|3-boSlc
zBa?lD!yDr-ju)NdM`GEX#xeD9>>Go)l=@-y-0!RAf$@($^^9?7Fm-Th)?eLn$T-w8
z{8yvzm#5Xy3+e^`5jW>wPTueu52aTPPLEFc>y97)-<<EYd#jBPrv_G5=We+7T=X6^
z!BFERogo6%bSrC$dwZRc7xW^)*`(f@bL6W@?>ntBW2)9RTN%0941j9$KpL3?x0*43
zy-~XRnC}9J&dxH#@M$yS&-mXbnAtq-@NdL4haHg7W}-v4=`Zb}QE)podt+1sJ$=(I
z1Dw_$amS0X29+->{WC^>`tj9<N!Q0AS0lQ40LO-)(gn^P8kMgGj?~j`CtpvQ-n-6_
zPbc-2-UC>W%jpj9u8;a#c32PguGx2J_|l5fDo^byZQR`VT5|<zSGc*PjU3G0(DfE?
zC&boHwd!eIyQ=2!POB%9`o!vPvF1x@J$_@%f5=>$ZtQ%1_IzL0qjt0<a_Ag5*_QIi
z$EMZzI2_W#y{f*xd_jx#m!FNr%2T85?VG>6ca6KgetM(329)$@a=JigZtZma#OTAB
z;$1J7-!aSgH2h+GBIz`|cfG@ml^z`3;ZHo#6Fs8-JAZZSDrpN}9yHd}ADZrtw#0|V
zcU%7-V{ZfB#&w?g4&ae?tg<OE9%GMDM#c<>^zcKrs4%&R*PF!*4#7hR6iJy)8P}~z
z8g^*Ki7iK)tN7-(!5JJt2NXzAEbU8sU6-U0mvNOuc9pD}b#F-uQYf2_Emuj^-t1OV
z)vVGc8(CFzm8@^O&ro)^?WTJ#Y=K|EU_Q<{bKd{^yw8chGpm2;SzmwF)n7@zaQH~l
z(%(FNfgbUG{BFZmy@$5bws%P5e4eLj)}2Y3w$4cJd(_`8ORxw$&!a=M&C~9*+jiHx
zJH#N(sga?)C+H_BgS-sjrnLq*6c2&wTw&Q(5&BBDwV{lnjy;PX>e#>f%2-W5R5|X;
zF@NF_r^$Mo&Ivt!!I`t#{z$s-+IC{lZha{VhSXBK<&D@U9W#D-_LB}9c=Rqu0}E~j
zfRs|U!<4+b-+x6v1JSA?s^>D=&S+^1vJc_5i{^rCUEBesy%6L7=4Us>2On;yur3dc
z-{}lct1`G=Fr%#23G`aC;)9HC_>-0Z02N%Z?`8l3FJ*Rkd}<;y;{h7gTwp0hKXl}{
zUkx3owW?*5e_MB7bk12-W7tWAQ!|#+P3<!>I1GoJSekJ3erL{i?1KMCmp(tGhkMLE
zznxxbY@8tBewHjpE-x|t2{OE7Zzpm>E4|{QCL(HoX^TF=CKjX1e(Tkw^Je7&Te1&*
zOtt&jG3!NB$-V+g7uBh&r-ta=q0;@d?II7kh^E?h({AiGU|{OLj6y$|Z&fSTS6AC9
zIMi#wo$b)ltA4{<OS4{Kcw*0@1+bQD5+1N?O6xcdX?*@cEud+BICaFa&X2>u)gP43
z-S5oFZDlh)%I+A?8pr28@vw<gK^5M#g!2#3>YG(W{x$iKI^dW@9&()Ud05v~_sVyv
zJ9gKXHl5EO^VDwDy3;v{c4G}vs_T#2wGRzcaj!vpY6~llTLJ+;hH1tw>J8Xg`x+rr
zpu~Wo6HDvubOaE4zyhpW7+gZzDqr=1pQrR~tF6ItOkgNcET@BgLpMjq+hw~Ie;LUQ
zNG*SOd~xxXTEZGLzb3W#=;$3zle%?on;#ipni8q~a))o~Q?iG}P0Uk)#?gfA1qEcU
z?d?2Tj`etTU0iwUg&>pC?}ogCRyVDI))hj+iQfcF7}?nUd24`{fM$bkkU=+Kt!L#K
zw2ZEx<!IZn<tqT#D9zc+p7lnYuSoCi2c0`QTESr3Vebm|7#^@U$aS;+3K>Q1=VG+S
zSp?KBNi>y@`sPvb35#86eA-st5Dy~j*+h0@{lH`TpycylvMB%ZNLVUuD1>@QELv}f
zZgDOC^cBPCI5zg884tCo0fLXJIwUCJlGYZ+qz9{IP!IE()QrbcdAps?%Z(FW5NeS9
ziJtG6^OOTMGxf9Aye75doaGon>u~&#Yzj}XSh(Z(qIR^pAKW?rNfy_MruW54ABYdq
zuL$!k6qX64`zOAL9G657*N|_R&~$D;#<Y^YrNEFoY4$JrPhj!#j_>~ZFZ8c)6}{6V
z-RgXl8c9sjOLG~t3}q6V8KPcFs;R3P97Sr8rdHF)6v%m6m_xRqqb4Kg)*Q8Ce5u`9
zmd!gn>!>dm^(kM8>@V}Me9#Hw#*kOKTb8W1)|_zvX|j2s{w+u86DBeTbX2hoNAZ=T
zzFJ-JyVYf(Y?n@opt$rT^w`;-JoW;*m*S2E`YOX|3t2maXjKJ5FzF)rBKWQ}WC5{c
z!o+Sah6k)+FwKH`eqp8Bs@lbdW$Bx!Pn{;1E2p@}3=mG>&_YNm9XFf0?I*aaLaIoQ
zk`NG<ujtbr_y^FNTX5$r$OEd;B)#(Cua2zsd0t9|TtpSLn}<t=I=~)LQwAWlw7f=J
zt@i?^QV)gYqu#V^tl5PnreLg9ky-Q-E2j!BTeMTiQrc~uU<_@cJDjAB8)4B~!_BTO
zgqMoYWO>3G<6jX@Dk+t9h+WPgUl}GyNG1-;JCezmc85bmuvH{DlS0{6R<_EbMykUw
z$Vm$0uRdYN&VKBed(p>2*Fdpj{sx)-dv@8gfn;Bd#r_vWw(SN=eGgs+SofddvB5^3
zdJpSvYx_r7xA~vl$Y;BNQJ?m1r=Y`6ebIR_*25>Cdce7u!TbOC*E;SrV(0EYcJdW_
zgX`W-H%MyoZ`}W}H$DH5$3A_7$6i0M=QDWYaKK|ho1c93B<3H%cJTIU0Ae>NvvY~Q
zN0~unUwqrf{6vSOQiF;vsYmuXb*RBC<*4Hl1~Vzl_3_|nd5~KLj48npyCAX;ql+Le
zaCADaD{fl|5iC`7%;3>F1cDX3i$quecrkfb(AF%PsCmYrpELwNzW<;?vETb1QHFw`
z2X6o!!{>yY_h0nhR}p+T_TV2s3Zc86_$5rvNa}vurQKRpm~Ij{S*I;ji$Dp=AiHaU
zt_uol#59m)U|(_}q`{a6omH?glJX&Givjv;VqUM9L?iPYctl>7rUmp&%0XBxQn|Cj
zJZ$(b<Q-rig^-hQZG_XQq%pw1c<QEJ`y@#jc9??9K-s6JFu<kMoGrqNl@1LcoC)((
zz&%VQh-1r+O_BXq=CB9Th?#(aK_EpC!Q%%Pax_0-x@;pRg!)cdM!p4vPdEj0(JX`@
z7~;P@j<Y2OJSvtMfJ;$z^%4z^aAg->Oc6Vka1N-Bqt~YO!a^VoHdSTWz()#TSy4Dl
zilIapTngbD(dRJ21pTPu1lH-gRW;c?jVsf$7zRT4d&<J;=TulJ3K*Ao$L$}1ahDlf
zDC))p78J*YON3H{;7sGITF+>10l6%2mJyzYEX~F7Dy!21YtoP<cM4icIR6*IF%`#y
z*jDiLVY0%jH$zm<167$)SY_Dv0`ETJ3PN~_u(e}thF1NoK1@pXs(3xltJJ>wnfi3h
zi>S*+#E@K<VZ0@T*gc|ls5qpKGa`&n5vM}~fXg<!WY0+?Buh21u#$2p#?}!hwK<`t
z8p=%F$ts~@hy$G#d>+DC%7xG~%7ARsBo%<BOc4F+q>b0o2?%}_sCpA)B6j`%{5K<G
zyOX^kpk7xbEI#V%JR(DBgq+=ET$mMC9Wf~w+%9K(BP3`c+x6YdYcig93v1O~<;pC?
zY2uWYPRdE)H~qzemYS9Ndbp?JZWk3q?w}PhEoYkOs)?uwA^8?iHW9?%iK_<N4F#EL
zmKMz7tW!|Wm%^#M{~O{PjpJgHTL1pjM=3wtScuy6IlG?PthgUBx{Ne{6H9VF&Z_3y
z%=Cmw@lffC>zXIJWF30`>S2K;l%vmyLXGrrUMWSf^aE7aPUvw-_pEXb;#>^?xf7jh
ztcI%AEl%rt7g}^hnRAW`n)eHfXiIGs02QQ3Whbd>mfnZa+to_8wJI2`NGwk!{_ypi
zJPN5A+N!E}D4rm|-cFb}3}{}r!DJ#@w`TDYaQ3XBq*TA23keyKB^PHVp#?o#B*ZNm
zbk#0FW@ARi#w8m1JaHl_*U{swNCSr|7fqD<N~(sYC>4I?+QaiYSq}}l$P6?jFe}&4
zUI8-Es5y&Bb-PV5&Y4~ckev7)dZJ#S;GW1HqP=QO;mAFXNJO<vLlJ}1GHX%MZc}!6
zUZgD#3{#ol7%Z%ijs~tTGhR};(u+D`z1N9exBp8DlIt*aEsTRH`=&?^yn#U%HccGt
zaZ2SWm2$-oQmYZ7$%5L0+di~w%__!19%~Fp-*j-U5;IO&!{IJh@T5R@7!0Di4%vCx
zF?Dp;P$6vL>?R{;E^Wg2G)?t%xQz<*UJO3Smqo~PD9AtuWdfZRS0PPoCzp3HjAJ-(
zWkK`(x*TEK<?E!R#vQgq(6e!#fK*hBh6Ql8LTJPzb*}U!MPUVUc8qf1-2ma!QV3=h
z{IDqOcE9*ca1V&61<S=gVxYhXiPxenvk0ytu8Z3n0s+Dxg+l5aF=~V&_(>!Kl$mB2
z8boAnPD!yws#O_5LI>Zg7^8BY=34?217?O@jsr=p3G5s`jPw8Wazu5hfcPyX2Ss7l
zSf^@+jtlA*21PDY^Ki_}rPDNm4nP6GJrAtT=PQL!+2PUf3sDtg0#mxRU|h<<!D{(A
zv{DJm1eQf8EsVPHa4rfZCBh1PrlpJ{|D+Zd;~2V&wp=v|90fhk{{)Eyyf&hF3<qyF
zsc7X6zKha2Ri>$e`LBY$s8g?)UuP+sEHQI{jc_(^K)xrso{oeutboeV1PjJ#mY2AG
zN`k1Ci|LwL&{bmLveP!IEhVJC*%fF&j^!yWNICrLrb4LWFu^M+dP-dFwbd*}%%~j-
zREeuJj#N6(FK$$d%h1*%VQ9`fX(EJiRiQeqryBDv^y~>2;wEs0w?wF_^>Pz~_l87M
z!3tPqP2!RZPD&VC(Ta7J5Fy11Cb3`qe?E{>6R3#L?G^}|L&^%e8E!<uC#eBQ%-K;Q
zY;856mFo-_TVe)VI83p@f>?6VUnfF7B=IWth+=%C%aWtH;A{h`+8fgq?56--UBfeS
z9+uLgvP1cXWk;!~L6-_%jp;#(P$#5#+YRgtMwo=^&okolCW6&}lmb~}!XLnRsBEt$
zG<>8G5;scI1+S(8cU7SgN+Nc+r3>knf;GB=JG!qF&=Aq0g9o;F<!^sqL7<#aF{%YQ
zZyX_Z+A0M1CA^}b(t>JJn=rIFXOJ;-x{)n=q(jIOS0OD9p{7EkKAi}a)igk=;1q)<
z8b2iol7ys4C~1rV-Js5%!pV$vN>i3a3W8ZR5q|7fHqjKaiJsRhhJ**Q1wG*<ultg(
zR>I0|&qG_P+auJY)bm^{D`IzLXjQDSg1Ro|vM$iP%Fu-h#@y;rzr=C>1J*9wj3y8q
zX7DIpV4>WWjs6wP4;6%Vf-9)dsjA#Zi{{JD-~IK!ST+Rj=a=02c>0>na`?Bq`V(eU
z^R)Mpx5AQ@Gh)>sCGnBm!O`qOIs<{~B+ZCf#xh;Gj4(2@Uhh6By1u(}ICHFeY2}=A
ztZ|s}9^5x&?s)DpZ(L)3JipfWTKf8|M~nBY7n9X$D|5#A)9a$VUpV{4c<+h8ksEHP
zjn%_OmAjbJmGW-x%X;t5Yl8HyR7JfwmhN+64R=aQpiNb7>RYP3BE!Ww=b(KsxxFf?
zOWvJgj5NM2c-Tq5vg4O>hwVwdhaWUp+UsKJzbGxbl~qzQj7!woyKg@M#ZHR#dsz&r
ztxMfj-aQZSs+R1tOfBZSz3pD6Yv|+GkSRZ5e8HoQ#8{f$-TQSiJ6!yII@)`%R2-%H
zF5|xA_dAa;E|744rh1@vE6_0i0ehK@uk9q|HJKh?DXu)H3%%fU8o5QYCGWZ`ZZ7E@
zTxhw>ohUNg5n-)4z9=u5S#q4pG;_q4ZGWtdhj}Ho<lVlqDK=y~(5MEoQ)o}Kqc`NK
zY~x$NQ!G{ux$P)to)yDuDx)q24f@_ctoH!H={a^>*z_EXDxqk7Eqx>!n`7Cf=+^4%
zSOyY-6dGU^p5|#yR9ZneC$VZyfJuXw2X7kT8;q7q5^HQ|8+F~bAaXP8hi<T2G<jZd
zi8it^+u(A97nf{HFI+^5_t@ao7s^Ks_lWg)V@EB0z<+~a5uyWrbZqP3WU@P-v9`ux
zMD4ZT8;{m9cfTy&VeHPj)xUC~UIT_SjBah<@~6GsZ~f3z#qDdyAAZ+!<2OB)JMIlF
z;e8Csz`+TKB-7VfHe>IVf7yXLr}FoYh&;zyoOV=#^9;)0miz5|v~tsgbH;gRz3R6j
z+kQ+)lpLo7yjd&S!5#6_5N0~bH>y+OyuV5&w1b_$CBG_+N#_mGpId4v?aB4CSFG>z
zy=&L&wzc!NB1FOL!1~xh2=tCvci$^_(O;&2_gm^#=vS@qn>=J$lO*vuXG4m6fOp$3
z{^}tf>hbPgh@SUqx4b258S71VZ_cho``uA7Anm(omtJCLEz}NNKSf)?xUQ6`$xmJr
z0>{uQtAk5l$*#o*mkuo*p`_36kZS*mrb84K0q=zFwNLajExxyEql84&1F5L<^4ueG
zzNx?0T(S-}m65VroKp@J&7@rzlY1;R?QA(1{nq+L>tNK|h1JKtRrQ>HH>w^g-n+h&
zX0J7^T`~0Ln$@-#%?Mu?wY+nM()%`b*Yfe-iJm-57dsE}Xw8n_<Yld^jRr=s;G%g0
zayxArl2<Zb6Yyu>srhL4#YdND>A1MemZFcp_DxT<zb1}(cBi;&-LRm9>wrj+L4tZn
zYWgJc{kJ5ST4k?jn1_OxhzlGM*P%+Q*7m|}WqWZ)`F=WYP04xd;4R;Rf^0|@m&W3B
zuG*%>&(x2sTGNajHGW^zS_bH#auO@n<=^~|VQ666gF|7CbClL>l)w(qaU6%}4GzOy
zvg2tftcxq7_4(*l19^wFj8b|D0!8+u*o+r^ri0A~G;ksMwWZlr@|NuKQpa|^>Iv+>
zgE7yQDJ(!{9+th@d6a?+&^SMW1D3cJh{urkoNwAXD~~4MmMDWhXw9R^k&PyY19$`2
z{>a#}=&QB8LiqRSongkVkl87^C!A7)1($c>dR%*S+Q^##cUg7PakE0)G(Sk(`G2b*
z-4G8kXFz7fZWcgN{4ecocyf1Ak9RDI`-Wu4bt<x|i$=0lKU5V*U<t&UAg)})Q{g%9
zDB;>XXk<wa1Ej&60d}_Fq>!mrtKGN)p~B0?;M%+%{{%%z{9iZD(X72&Qta-ToHii)
z#JrmlTdJYUPKii$s}TrGm4lX0zV_!g#bROj@YrExOc%RoyxFZ~;>{ror*b}{91wfd
zZh}DzZ2A=sG??10bV=@HttwW9?DF^(oXbOUAFV}eFQ{?%>KgE_-6tZ~jYc2qU&TWd
zyB(|xp@||<<L^|Zdxapfd|sT?+OEzT-8Ji=^}OL`k2zOyEHw+lbJ37;mRgjw6V`ij
z)`0Ysows@O7L>D&)2$j`d}vF*IcS+1Eq~D}U_sgNPI_O+%`SdO>9g;?O2~Y^EsUmA
z`U0!bh;0wa0o$A;cDD|vZ|B@tbx8L4+g7vcPAOAkPOAoSZ}?4l2CG)7vYiG%bwaBw
zNTnpDR@#q|D%fXCp?1m?#MICJ3Dw#bWln>~5|%!L&Ke@u%S@{*$|;fE92l%zdU7+m
zeD)=aVD<1_Q?Mgf`$X=@*Z>XW;`B=2ljj$rVGK}*Y1^WXD*SL`?ZXNd|5ZLU);5UF
zV=dR)!X-phRcN3~EQSOQWXh#A`Oxoq;VH4rGw0=FOofJ-Y_>u14lNB^%F}m)kFyC4
z#)MFO1C6G&5&;Vq3T_-Y<$lmH{iDv}GxPM|jzf&tqyEIOk+rW1v8M&S{P^N#y+3#4
zPGwi!!<F5M<Vts=dZ*KEsLwWthr%%?RLp=q!T~!|s-Tak5F6l5goL-6n!_C5H~dl4
zGx_8GQ`P`AO+i~#{v`-uF)Kt3WZp;QSQ&*dF$D%nR4%cFfOC*ZL*Pz@QsHF?ucE`O
zn{TE$p`JYFsoQBrU1q&%?u<Z7q)Oej`u{9cZYYGXC(y>}Zy{%y!c8~CTUDrepkz(W
zGB4E#X)Ceom|58Bq-d;liAk{&y4K@mRZM#62K_6iyb+Gv<p>9y1$cGAu@WGrh)%J;
zWPp7Nb;e}l_!KuWwxS?As<r{)LS*cLb%7Pb8z2ak1W$O7R4LI<z4HG<()x4x>9!3;
z>%G5x1AX2bsA6vjM}Hnaed>#?8yorQ4SxE^zxEzKy|Iz>dmGu1)&?8F*4~4#z5hTI
zyMa&NC%OMX6x;DnM6tC%6#KLChA8%iru9<?ZzyyhIT$E(zcKzuWwP{uv-tGW8|ZZA
z20D!g==2hO=^txZf7$-(PZKg!K&uBVb#w*O5z7hzVB-ttexNxG)Dw6V%t~v;4EY2q
zB*X}K3b=!gcmRJ3VIvYk2}n~c=@&Tabp5u8u=FkGpnpT(8i-tx9@uW@u(@pb%0qt>
zyb}Zp;qk^sHh%mEPaDxi@N*DBfSTO+(|ezXAKV+iQ1F{V5Qr$Zf9K|He(%fi@N^Q)
z=tM}gsBYzDBfQ<Ic;Y5qnRcq7Y2#MVRGy-Z0U7{VB+3CMN;=D9Gd78-#N6p728Gg6
zCn5$EPz+H$rp2f*qhN46CjBKd5o$S$bcK`mT?qCnD@O0An_i`nWJmR;NyEhsw{#5^
zHmB2FL)Pp^8g3uG>2ZT-^mMR(`3ge(2vMg=qyu^$wF0GFG(ZG6S`ncXM~R-C2;xxX
zL@44n^FdfWq?iL*289%A=amGHG69b1K5mc8gfj~d3qkY>4|z%ji({iq5w&-w4$%;b
zp?T9g5A;0lg+Ha2RDcXz;Oz!UGEf$fA4J<B3-HVU>Y*#x1xV<y^Sr`XjL|@6)r#wn
z&@ZZ0$2h)QHd1P3MJ7y+GZZ0Cc&oikkVUaw1hOtO@-*#LJz|@f`?82uZ`ns3vpi$h
zd&R0*FTInL%X+fMq(O~iNqtKkHVS~wf(C%$M2MrzJEg*c;04_Xx8{Wj&DW`_D|{E_
z?CuuW1hndn4z*Sg!s&%Pn?r>fbWPK!pJ%#Kjp}nua$X%0Vmk_N)r4C795Wh}qHxLO
zI#@Xtz5)a|%N)DY>LUY<UOKdFK-YThU;b-5WlYqK!Uf@pF4l|!A8kc(Ipsmy8WP>u
zEll1|P(!66V=&8&QwOZh&le%sBf4b{+e&2+;*xGu45BG@v#<h*u3^}N9!*$-*8D2A
z)Z#D9tjK0-_n2R{2JMvE=Z$#EHmlDuAtBl3Y^BZKAL!w7xDUE3c|G%CJ9g1>?*T+y
zc23u6hTyVG;=*r3i!@Y2yciu8NCl`OHs-rc?kSql4J@VpIsJaojG&TeWvv{yHD&Qa
zLL_64Xa`Yxub&l9iMi_M4Fp3eHFh7%pb(?pXs`5$2%F2&mxdgK`TF7s{b0F|HS1lz
zzil`j^^O_)=nli8S9JS=S)}8&kBpC<7~J|-ChK?5LL9HWZ|Vc>qk2DAPkhK0)B>aG
z)`W5%+P`90(A+~S1v}gw9p*e8YC-@>A*FIl;wj(NvreZhKj+n*N&Qq3HcfTt-HrWj
zL*<zvnNALs_rQ+yZE?+(zOH0QGKVI<w!=mIc7jLuBk=q%;dk)dxc9rd+tFlp+GE-M
zwQ+X9I=W^(m!xP~*JWkKC~Qt`{uo2+B?k>Yl2)c0i@U{F4i~&j!llDPp)}}!RHJF*
zIcIq;VdL(jrdSe52C8H=@Yh5q)vKfdax8dQv^ySDqpHF)hPIBrn*wV=su8_U2nBg%
zC!v{uB$Y5<4_Ct(^lOlnlxiv4ecYMAx3KE8OWxh}(S%B;4SYl-Fg<ZG6pF$QV}*K7
z$&0FxaB7O}4hS?fDI;~CiI(w|FSBz38f7uDX^!OPe2gA%u{Mn2nhy_(%{on2Le&uR
zpv#T4MKnn>J?>WhO|H$IX&bY>f{HvpjZk?KCqgJ6qaLPZ;s0aR20e8w;14$u!r0Dk
zXnCW?nv1a_7jS8X9<oE!4hCDVfCi=yaWuf1;V<+iJAz-P@<Q1W+!V|@@F(M`u#y%q
zYe+1ys*64p-y(F(ezlY)17&r%5K_+n^(K6fD9jj6M9$fg%9w3Q&0V%>u#JF4A!lu%
zm2oI?Be<uemWV9*HVHH0VV7V4;;><+<h1I3^bC&@jAPIPSKv0l+jTb)#uVnb;|>9M
z8Ct=Xoid^dDA;9i?;#PYU2(saLW5Lu;xHZYa-wl<4Wd5DELm-X+!41ml@%H$>^YjE
zNx2<^jJ{0rF6H^uoG8;rY413wCMI14im^LXjjE?WNK_=wi9mZusR3z9gr_Z>NJ_Q`
zIjVzxN(#>jE5UrF;-KLzdU|1$NB{7Wil%}b0Z92G1<e~^2^r36vX1$VIv^k!$*DO_
z1~-h>q)ead!2JYK0Vcehhf->X8DgR+)ZvUFRWj@^KR2<ddRmmFiV|`*Y8U1(ky{~5
z@kelDDY)T+I?pXmOt)HZJUB~uqDBfF?fTZ^|9J~C5wkQQc2JLTZ#xyes;AVggz8mP
zZv^07&EOWA!my~wG7b?BT3}vXG&l5`lF~YL=MBoeg3*zr8AqK^#em3&I?Za^*=irl
zs06;z<vucP^IQ{3O1QGp!QB}Ka~RA;Oyssu2#>b-wNq+j^Qaf(RV)}bIhs;dl_@qn
z0Sksu1kE0~TvYF;aO%XgfjWdCJGCfeBE)lQLi0vsZwQs_Xcl%bso=H{l&02<lpPiT
zu5XE9;X)>hHXvf!F2gN^3a-E{n7WYEJ-G#}Jmug%?P9d8yiE5>d(9Eca$2B>TH&Ig
z$>|&)fN>F8?SMdHgyIT{lBanno1b?Bh>DF#>bp1rxUEE}AZ*U($Wq{lKzEBX4)zN0
zk*3r_*eBJS6I>NgcA_KdSB^b~<AP%l3?Ni5p(b`P%)1m;RdGdp7(R%gV|Fv0g;R`x
z%wsGW;i)9U#c(mfshTRE2Py7bQ)ZL_JGe+3q7!QjlORHIIuhEn(}omzZofV5TLs73
z;j|Es4B3g0P~O~yS4^{!`s2*Nc<6DZsJbJr9x)ulp$;7fcMX6zCQmr_l*(O!@3%|k
zA!a~3u2wY<5yY%fZ8ZhEB%Ce^W&r~T*hWD8PaQjAH)k8wzyS!G(Yc_?1ocBarKSg+
zTY#L2^2N_-X0Y2lm?cnLMobqnOjU4uRh0rbH|~fUa`t!yfi7BGhJDA3p6Fg9Zmwji
zF7_H7V$P@{^`xaK<^`T>Cd3f~Z6T!v;(kjA%uFl3xrp{|x7N&r<~rzL{cIDZg07^`
ziYFNUH_oz0u_A7Hsr22;UdK||Kj2j^i{Eum&oNOo#%cF>ZmY~{JH<|sxgX)pTgdTr
zv#!Rs7^#cx6W#YQk#mxBFdL4o`MU_Tqx1>tBtPEKIYd4_d;cUoNb2d?wLT_$f5={z
zqpbJUwKHOT{dEp6c9+660D;h#_T_fu9zAAUY&vdVC?2D~=ZyP1Chd55WhM6vsjf6u
zCQ1uk)o00+U42D<e{`%gX;iMxT4c&8on;@Txe$rvIWN8Q7n#)N?(peZbkN?;oR>{5
z?Gz`D)BR`1S?_fw{0aSX`ntgm0(us^h{sQnBZ98>R3W9UcCX>4nTN{O_0yelWqsV`
zdfh!hOHWW4U7Jb2EJjz-okRKFy<(1?I1A957pK3&WY^jL(s6mL@e6C0=;gJ)ne%=_
zzRu-ofYlz6yGA7|o^|%IOEk&0u6?{~XlK`v|48o@2fQ|Is-tilMif~(=8UfPJ2TGC
zWXtTU)mJ`q+Frv+$9gMQjim$b(_a{JAMSQ(5#06N|5Qy4wZMm{H&DgmX#?-(5q%@>
z#N|mlV|=onZV(k)xUW`i6%aUhWm>}@UA)f?fUde>a1g|r&l6r4U0FfZtI<+Nkz}xy
z(lKFQ0s;>3@kT(KeGdpDTb))#r6xvJPTRFxVrT6@Y+Eu!Ammkp%>^o6YvT!@(CY(N
z=U&od_f!j`?js`L#_9vjp>Eoc`U16KGS~;HY{t5M?eea5H|}50i?Pzr*2GJ5-oa@4
z-8$WlrByD`rD*9<ku_LdvXYi_LX+`_04sjm8MlnB$v4M`^H+#|V7+`y?|yRq&W3(-
zw6;rJF=A=^7<t*)OC7M(Ln{k(cj+8msIvH8ereYaqqELV`Pie!y=z2Y1(nb@^<~=S
zc5$GVQQy4qPIV%CEO}w{2bYgnhl;;h-S9h@A&@gx&iv^5qJNk1HzYYJzdF|b#39ps
zw`RAG9RR#Mw%7uy%-TKZBFUR;vmWnvSD@J2i$UPe9{xZc2nhRNf6kF-sBJw_JtEn`
zsC>!B+_*n0FQOux?Zo{YHU3ws)vOx015o}J%5h5fWd>xwbJ>9(Lg{Zs8LS8<ia0M<
zb5mLE(3eMR9u7DInw-Ev?*(k99Hj3E)v;6?9WGrL<=&23^bH(HwDu!LQO2DO-uF|M
zWq1F1>pL{l_LF4NckhN5@*&y#iayG}HEseLmVfqQKCXUitsmg)z`~C&*BIHVZ}aY~
zll~vPGqnpR(>M#&W1J7tE5)u<fY0hcIzUNU_Pg?J3g$Q;b$4CL;x}h0oCNCMt}By_
z#Ru1?*1W_Lt|+@SPQ3kc2-GUqE>Sjp@>Tyh>eJr<Q;df`UH^1lfgc~Fv7cs4$N8k*
z0Upy(M4p3fg5RI(h@Q(IN4@~aX9}p?c?^d=u=F)C>&-v&V+y={+qTS}TIaXcr~{%l
zAB81~s+S;ne(}k$?Dt-Z#;$t)9(W4Gf2THf_XYFwr&<Ci&nXte2t^P5VQ|@STKF#N
zOgh5L&Ny$b9TzA|?_m>D;eIJ6F7mwr(!IivPZ_ME7#(nrp{e%cz_2nw-W1)2z8J+i
zj2;BHqpXbUTc)34!Ewd0yj!bKdmz54gc1fhONAZUMemDhci8Pzydh-Vy}mxxzNUEQ
zQS#2Ib<>Lf^pu~ymLzXfcgl!1B?@QgWoHhQS@!3TdkfKERhJRoPmhmH!0<vemCvky
ze*GSA<5H=?m5Sbe44L17dOx)(1HN>+f0$E2^4G+83g8+@*W4#meh_{FKNM9}N`{%q
zv~&j~teXK#v3TXfN>NMgpPB%V_0@RvIgi9$0bwgHcpbhLG!gVUb~)$VdR@o|YqV&N
z!w%v#M?H`0a;1^<h^CqzXS2wXoYs_+Ob@?N?f!<h>5b|xzg>s;vh8hYUTYCh_j|32
z(b9EVH8*k#Aib{gXY0R2mDDh`ptX1l{!0wGm6x!GJ)T9lHvsXcQmIj8r}W^qCrX&M
z;;^v$rABpGDpyz)1)A#o+#Px7g#EON7O@X=TsJ4M*V{$5do559_f_Yk_NSy`!>r-T
z+_Osj&s#@n8(skq5eq73yFL1Nb%@@l_N>jPx6AHYbj0b)g9eVbU8oG^gRZd|nGf~K
zE5D7hPOo7PJS{{4EvZj@yN(XrBXcjdoR@MD9K8No1MGZjG<8{YsIU}fsmtTUKjT1)
znh(ahH!s6v0j<hUT`j-Xo?F&CfRUe{fl-F~yqKypP-7S#bqjS~Qk{2yj=r*clTVQ>
zy30Pc+F&=w!_WS7b;_K7<}UW?SgjLHR2E(cbiAa0{5qU|qVbpI<vahcCl=6#vM+TK
zcq~-mV{_R)HikZO35_Sn>&!=$^A9!DVN^bE!6;x4mY1gI3;`HkUAkyN*<sxY<*h#e
zY^`t)XIk(c#}tzj&AK<7?;oDCO0ZX%I1Vqoxz*Iwdc9p>AgVVtJU??+N0)a+Ozp%(
zX$e`RLCTa7k_|^JbxJ_fZ8ziGygjDjIy77A^UpTHcml35iuEj0^{J`m-_viwmf>sh
z#HNYk<=QQ^yPQ{7#Rc=s*sESmpPKn}(D5!@fVYG4_`mz5y8AfRbp;MgSl$o<G)NQp
zr#wewG-!o2r3X9iE3|B^l5d&ROl1yRk>N2mAc2`dawFHhGD|&6*?{nvfWm<Hs=O~y
z(++e*bT;dyc3*Y}oV;RJz+tvDSz*^A0|<GWi<=+!eD$cM+N`}L^)?bnddCWDQo9kx
zDE$w7K!8;B1~55D_Es*FnvHXcn>X(8zPc>Z4FPq2j(W>g-1cD@%TXsi46_NUY*2C(
z4NnT(%Td4&F;uXTs%t|*7qDiGPc>s&0yb}W8nF(w?jmE1jp6pK!b1qR?g55vamNz;
zk(K~GgSkt~!=_>yY>YxjKb0HXuu{0|pAqhU1X|kzV|$Q64nQsRyMM27{mzEQHF<3C
zhE(>Ld-3Nv7yR@+rR+~{Y~-m2S~oWG2PZd#vR}s+(BA*gjl5@n@ZO$4wz~*ZhG0+r
z0Wwa0-F+#3!_(m}C*Jc=*fVhhg&+IIhKIuK^z+9yj^{J8J@1j{o(+C|=j;vjZ!J*&
zdf6N3`G2T(cQt?UQZ|ezZ{vYbJa|Bo$`SAd-_6aCLaSD2y;+|_z#RN(<539yOacOp
z$Yq}6Yw&-915U5Zrr&$wADt!3(4Pyu3aakZwOH$ocjGw`4!$h}&zSzd_t540-=#MG
zjGuzfdvC9TzXdPYcq;-r#3IVy{pT%o+B8vcmg>+Of)G)&JmgLi_V|GXrHa@jr8QYb
z7-iPA=_;d<I7Hy77Y)knYG=GzQ(E0qTWQ&1I?+EyQZq&jf+wgWAy+m-Zj9|<(@d<C
z?Wp>qI%#C`3?CnLRD3#$Z_{~qtmKCw;6ap{b20b)v*r*@grUIk)@_BOly?koK-imc
zmP`|^UeSfXxm9te@&OUBn+Oz5>T$gpEw~(Zi_ux1oCx92Tq;m2PPvk5Ksf@jpla;Z
z+<9NPUIyK-&6Ob<)F1LY>eLku5j3K0r`1lw6JPvQwXnNOi6Pw;UJp}%rLc2=_TJ<M
zf*QzhP_D1M<*h>fiL{i$FF~uAWlU)E#)!1VR#^zSNDPL%-^K*yeydL4&=AuNyOVGp
zd6x8sTruqlPAMXL>fjUo0(J-o8Yr2oFE3Ib0b+<L?!0;B(BBLgnIRA5&cJAd4gjPm
zJQWJuR})1ZUMZ_enGD-*J1HS^YRYZIZE~XE^pPBqmmPN;P&Z`|!y05$dUaE5wGlDB
zp}BT!9fZND9=3~aQlJ(u+~Rm^D}F_be{<GfAj#7xOZ8L{w|R32^0Fv0X56cEdWwU%
z_jRKwWZv~#zi2C|hfo{wFyduS3b*O<uu)tgqO8Jz0~Ixf6Lnm8YZp~itwy$pfr}iM
zfJclj@(_p=*Gm?xIuLzZs82TwNC4in05K$*B{XfYEy$+z@l`b59CdUYLMWz=NZt#b
zq7K1o7vb?RON7!P8!ftc^}qeA)OS21JXF%@FwR$Mu5o%+(POl-f}(JaEF7^`DxHGV
zsU+1QZ=0OdQ`xs2tk{zD9~|_m5P>32a>mE`6g(B8TSUR+4?73F$FYYWsB`9$AL-qW
zD-S!BkP<L^UK#b%{yo(=S@Pq~g>L5wcu9#uh>GE|yyS*CtGG$S-JYv9<vCL<W_u)7
z)1kw<`(KR4jIB@*(}hdR<K-#0E=`+8&IwnGk&8ClfuUGvUJj-C?yP7X5<N0?))5!*
z;Rr5sb7C9uY5D0{HnGp}14AzLM3T`5HQ-11`Un^Tj4T!p``zpuI@dK6sqjA$D{^Ar
z;yKYfR<t>3cdO%ehqKpzbfVnF{L(Dj+CiMs4piN*#+A6>u5-Y#^y8#_SVB|f?d10@
z>hPx!(Q9YE42^6^ahr#Q*|txF>s8d{Qwl-ws;_XlVed=j0COW^mf%Frid4OfA{OFd
z=s^X%GNI~;aMcLIAlg8`8vz3M!Rxx((q<<vI*05&8X;Y1=%^Lgt|QV%GAA)6r=5AU
zSPs8*Xo{Oc{YQQwG3YICjHt*ODG|!ZoCNs-mDZSxp5y{3DSk?27_jW9E~(MB3GkV@
zE<7W7CDfe+!oI^&2K*GWIh&PJM3z|?t;s=KlRTmEnEK@~MhMeFCgwOKo$$U16&DSp
z2?tn&T>5ve&kQ7~0VU%YPVt$T2H917G6<fid9a%p_S_Wi_B^p7`XH5p>kMhoQ{e#h
zD2df%kt5g3{BR<K(G7<SA-rAg@V6v15yOxg<b(BKc<0qHjzYDHyvvw&9+>)oY^5PV
zZq=enN@!64)dD1TRW``KZA78LEi44L6nCqf$YU5JX>kDp!i4CgDYaTRa*hU%B^p=T
z(|v8dHLvMmcUKauDB+GXrN_U6b24cw0EWu6+|e2glP3b{sNnEHMi0>1Zk7dT7kt2U
zh^a`b#g5J`HE+3n;iia9)kfp2Va&O_&n?(<ESie4=w7Za8_`MqR;?A|o&y9e*ogbI
zN9zU!XVy(N!L^u;g`AX(hCaRAf#MaSOcSd+Nm842f>SKg-r5odhtw7~5lX3rsK6}_
zw9Tr9fcw)sh!vN`@bE`)pso0)Cq}Jr+?0<G`5ub~!bz7i)Z(49p;j4Rp%K!MHD`6!
z3#5PZG=(ukre-A27luXlLLI%49b+&k7JlVs(_Y)9r|nB((Ma3P*n71@-Su2TeR%WK
zQ0qALb6q0WDN=TA*!0Ah%N}&pUR$cY&Sig;wcI06$RoW<pj&O3oo(@xcC`cYxu?<K
zVj?UAj{L{})!X5w)M(ByT!UIk^5r4cOXpngR#ikct#akoi=3j4E2qY7w56ivB~);F
z)1Juzlrp-TkI1>)WengQl^rp+MCo&M-dsj(0tK@imrljmrRLN&u=HuMHtkiU2un1X
zEfL4mszkEnoG8w*NSGCHIhC!#Uwl+cT|e-DCp2ZYrWj^IlLKVAv{qe{w=wr4Ja!u!
z71NxIFd4~%>@(zWr9>!YE3doY#k7h-buNg6kV0QZ{x#7^B^O1X+o7DS!ht~||AYad
zSKfBqhxALCD-a1ykO#>;m}S0rpjQaEc!yfO9fFuPyd=og-+fdm%-*IHa41Z=8BBi%
z-3Z1P*#+r`ZI26*g#<e#iF(4_A?yK2=Yg>KG&U-TyMQ8w!VVPDIU}??PS@6uBIF7c
zJP{%(4?igpWQ!9j+m11%koPgSLP`q(2@57rIhULxyFB+-bQ5{(96_2`EzI%MYp$V`
zLy;&MB+5!kgbK6q2;jR3eC;Z3dXqwzQ6;mH_pcJiEP0OZ+@>i5P8FFs3^C3$m~8>~
zd)L5xL=n(6qtqqr1%w~BH6#v|?Zc69$Mw%XSWv}+SHDH|<_%F)(@2!JszOZry~Nt|
zaZO+^GsDPCD1HV54iz3IXCe`bfJV&lX)A)H9Z%$GZQgFHne3Ex#~RJ-V|Hko7Q1Ni
z2!OGj%gaojwyI{<Y@nDA<=yQhvF3}^m=F>ORJgErh-@KHPng}>l|LCx8PR<-Fs_M&
zd}R7HWT!FbQWC0=BS=NK+i3#++FC}M>dHV3nE^YanSyvDn1op#ZHL~|X}dXX=Gg+S
zmLT(FL|UNtSyd>z#nZBLw)bTb&S`$NQ{Y^|Zldsu5?=b##=K8Z5Q(a(f|kPqJKHuz
zKWW^%k4CS%;?`u}VUO=B(SxFN&8-&CiR*{G)B8*3jQz%_>^c0w@3pgMIDMjC`9XdE
zInl5as=MAVi0h<Yd`R|-bK(!^+>o35m0FH289jF9o<=0briOB}^(nebukMqp=T5w1
z<zCmf=6hEk=698L3>_SO-Ff(jUs@f1+ev>{oc6!_?hheGj_n`1Za6EwPps91=$U*t
ze4ypT{#oZzty9FE!_F=^thoKYYalzjyLz!S&c%yZ;Ya_BoN}%R$32u=C2MWbB>R{w
ze(*1AYsSaRm&6a;<8yCYolC#{M(^8(@o&9n`p!(228>!=lwT#<%I~oFaPPMoKaszU
zm){U4uG5)w!@I}<^N@QSbF=gh=mJT1)=ykwn5eDE*NxSwcxJs(KroM@qqEFqbGg2A
zyY$SywM7?mkatAf>eJJI&hG7az4;FMy3zYx=b_B5dk%SDm;Zr|zPOW3u?PR4dW>9J
ztHn-y)b5cxJEqu9Z}nh0v*hg(J3G?X<}&Fo%<dTKmtPXc(|e^lWoNF}NcMuyTNgyr
zE6H)bM=s9vUQ8b!+R?G=NQ@+h4=#LsiN9%f&Gz{d@35J<1MW=a`hyo>CXv1cWV_FO
z|M@+o^YHN!g6835X#}C@y%4iZrf(4!R*qL~%$b6K8pWbJ*={j8yOU+%)(f16SOWnw
z)YXWC5%(gY^E5=#a&+Z1YGFs+PkY%_u<_nnbIUNpn;tBdj@52RtIHc-k|K4E-BaJN
z47Rpb-^9EhA5}&$e+ctw{4EKTRpdTOt6)Fj&dHrlTOhUG_)>xY?^gLb^T<{)<ppAF
z0nd!$=dKvD57hRh-E;IEH`Cr-l6&31_6E0-KbHM_u6xl#{EzOx-n}|}XkqUg-y53S
zePE&d?8(QgPr4^c@e6XlI0C=eot0A^L-Ng)-=~eBNDwcdYKLL&>Hq3)9jsmz6W{i-
zL(U;A!3BTdtLsz!tQLI}9FQKJ`zg(}%{l}1J@%P($Tcf(FOBA(T<HAHyQjom###B<
z>bu{!pS)=9UB6Zn?H>4Cu0QKseJ*a_DXe}5PT5Y2Shen<>NlLLv$K6dhmcV|_u7%c
zy9X;T{V;mcIUpxq)qi#A03?jB?D#MIjPq_;wC$)~@#^PWe{cl*{-K`nZ@-omPgK|a
z_|<n82JBz&X*xzajaxsGE)C~9Z;4))Q=eLo56SQRZ8{CM|GnXEeKI~-E{oBH+q-J?
zC_G8DIRAWIsE6F%aB29+V@yIWU%RX0$gjY=q2tI<Y#5Ar#5`2HM(cqWDD(7gERqX4
zP5Y_9I#}PckL@0kuta?l=DhE=)Z5(y{KWN^e0E6I+Z^vY^B>FD;9qyyU6v*Ps@?>-
zCrpsN(lG5|+1UQ-7ewu|2a5A7e(O1Tx$Ub@@apC4OCRcZXJQSA^UonMg?jyY|IJH~
zyPvTyV<Eqm{qn1_>FUWZM9y|!bKR|^$9>@bWA2db{+##Dpeqh7oy#n_rTx`kgYRDH
z+%wlpB|UcCm+kAyA09J8SZi+$o7~B1*0@geyE-(yV=j|bYfW9dMfdkI_jtUtCX^r7
zk9kL;93+03e7g?IPnvx(x>dg;->Q>i-mG``;HCcj5elVj^<B&ioA*`&hmWPZI<B3%
z<ZLBPvzGPd_ys7@@4hN#KSkS6zOjq$`8YgEmgJL*x0IX?wfwWO#ry7+r6o9Fn0qtF
z?3Z-A`6b#mGxyl~t7CzLb=BYVlO%cbGE7&l-cvhjoXOk9T%&QTJ4|o4&))KNGAO_8
zwc@(KHDo3DS{fcCl{49-uYCAtt~)JXJ3{B@&>hvSPv4O<dFk?_0HRkYZX}#P#taX_
z_#UP_20sl*jhT1lIhhtO-qL-Rs#s7j{s?5Rwr$4PPecX;IeI*^^w~*Lepl3-(kq^v
zxJu$h(Q?&@*-+oc&v;9DEMYE|>eeCu33M*cO4w@om9cM*Mdze{p6^}X;m2<}>eY74
zJeGsAf(4tJBQ*XBW<pm_zdS(y?Ou0Kx)0DARr<OcU91AhWE5PwPqcOqvk#WA0JLar
z7%?En784CeXMX_O+S2ver`zlB#hrSLHUOSZ!E$#<^vmmBhH)(SN0m2!h*ckowtDcH
z9t!YmV%>xInJTYgy0y#K2bQvs(O18jhvQ9YoH?Z>417*$&GVcd=Ud2yy<^Pemh6L3
zWWcaA7tR-Q6HW=q4FUU!7lXCH5?GO2T!x1?ehWL1%JsFi_J>J-??SyD(zDajIdYT#
zsPTKm9U6?5*zU|Pck|LW%N?8EIPkCPyLlDnEwMkP$5+%^6zy_;jm04=*UmeK{nT+N
z%{~66Od|4_&^#!slrIH~CnJ?bKA8t{o}FRi!9MNs+HFYFjf1zG{2m11vE$Y2c0L<q
z7}lIErM1<^Jkax{uCaMEKk(it<kCT>?1t_?FbBW;j*w)$JmbfMnp68rbNRammlm?M
zrssWlJU@KiT*{&4KL2#PwC?)x%{!z2`%v~0=X>dY@YIvP0bAqvJ947=6&>yGUoLGs
z08{6|XL3u?>KW_$s;hi$_FCHA;MLDQ!W8(_G>DG5)yU=X{oaf>;M_G1u3fE`Rr}2&
zudb@GMNFrrCc0-m^8C!F*4P#K>|My&7?&N`tMAxU+qUZAa=lc2ax+R%YOssG%Q=4P
z#T});w2yf{M%S;rhTZPINNX(zKXhR2+cd~29FX6pPcC+fti4IT2IvEwcy_VL{@SHi
zAATuXyF-}BRs6-)MXPVN>6mpDc0ZS)ir;rC#bWRrA;Zm`RaalUm6z_*<M+zR;$8RD
z2B855bdSCLAPL#q#4SjNF)7sQZ7K=_j(Gyk$xZ5%|7o|~PWdFf0rMxSt(v{<R8zy0
z|Cn>nnDhLzC%dfkOV@p`sk{K+4GSw3f5HDfZ;WG2CHC%%d8_oN*71whz49wl?bel9
z1MVv|OZZUSmzL<B@5;e-chBbYq_$51WmP8u-|Zi*y$1L5Ki#99H}_9{U}T}SW?^+j
zwrD-pwK;|Yq)G^GLJzG*V{&+RyGbBQ{4jA_!P%N`3)gm)6Qj&SoeV{8=b^Bm&G1z*
zTEiz-GYUe2J1#+jq{UrT(c#AUX|E6t{@syucG%Vk7p>~{>?2MHDtKX<h3IA!1`*eC
zU<(*-l(1uRn!?j#@g1bun()tzNn79VE!y#WA)+6%av|%-|L+IZ&wZo|tPQd73c<6j
zmM#T=zw~uTM#=F5;QRMByfvJ3N&SSQZmmwJ0+Tdhi^HgdfcrS9b%~UP+0G-X_>vXO
zQ99JvTrRt)*EdoIYSxFiJliyg=}^|&m<Vmo9WS>8-@>6nOxCm3#bARqeSL}HZIi;s
zw8Q~nV*Dm}X(83H@oG}Tiv@te35{%({_=*E)|G3YIPaeOUzm3M9QF_B4^sX<w*UG+
z!~UO6Z@3o!^nGl<;aVKHZQNl0H#YK~Ne29u|49Pj>%H$;AOHIe`;hmoHg0U>pJXB4
z-;-;u^YfiQKKeh~Ilr%5|DRl;J)FUR;-7r#uMwjCoCkEqDb1JoZ!Y*Z1HvyM9t^NM
zpe?vpA-o||#~NoF=-yK>4Z&0dUjTs-FunJ<Qp>#m?fY4SzyJA$j{JsX>F<B}-Z%Ih
zJP;2CF(keO4|n62fA?*z5jPAz(EE7z9Q)vI(#^J>%X0Trt6d54daF73ksjWhBp>R6
zm7-xC_Imevd45zU`ynlDKI=ep*o}t%#O(1b+*K=~xBTSPfWJMyjiq*rM^45_dS&Q^
zQ7%SkiyY^muEo(6n^eYLDDulZ9CL~*GpyRl>R^XsWtulzgj2M>-lkTv#+)-us<|+S
zslyuSfWV43@e?`+g)CbiJ!@4uhqt2K;QRkAMZ1{Ev0(|HBCQ)$BGZn`B{Wg78G~GL
zV0WGm#Iho?CDJhEE&Bs^dJjUB<qX<(_x|_{R-JRFXPRq7A7Hr^Vy3>}2(7H02z8S-
z>y{b0W0^P!OPIGBUKdT%AyHD1`D|0i>5dVB$O7)NBfcYiGh=*jk&l^d(w`^hYp!(X
z$dx}>7`ZJL<^%5I?kxFrozP3$byCg@I=N8lIX$;GGb)?M`A7478;k5PT196@?_T07
zC)81~?t*=7mA?x&<%y7}f@8$@!PH&y_1WQ*;n)$Q85sa)b15G<>mG37NGWj1P<K$h
z%_D21NZb4^F>7YFd(9rm^50>Cx5&_I;S|YgE2w@}4!DuVn$F{Z(DEs}$A91>zZ6p;
zStQf<E6rWT;bO=g@x`)HGKUTQH}?@0CG9W~c5QgG2)Bp#A!}G&(I*XZausmC7#$Kt
z9Api-gc?EpfLj^m$}Ss1G9Tpu)o^6dbcDiNu(|}X603%+sL-kM;tcZ(`{TRWq>(~R
zu1`wWbSd}(ub^I|Xs#L^p#x@o%tS%KoqF%8mpsrKN!~*qc>Ndr!RT)pZ`~cL>;;C{
zvMqz1XgX}*;}5u%5QMB?b<YfeS=0?Tl1E0=+l<VQ-i6i0oTwd)@~u#`dRt)BqHi<m
z+?8dj@{Ud$jR1r-#l}}eQJ+DErfM|eFWYn%z|(1-bM9D)gbUmZ2^#qPLiJ0_7kL;<
z$BDW_wp)+Q{$g&>{UABHLhdm8nCLY=XABq9o%#wvQNlTajzUS}ui$JYvFPU`D>(2j
zqiEu%;-I*chkP#02WtZ!jB7{NVzkR3yhP<;UH<Se;U-bqO5+|BYGTT9aZYWk*L0m3
z4Bnm2bXV>$Fff}V3@<os4LNUl!(zl0E!p+PPx91Pc@aL*!s3`3wj>RES#RTetvUI^
zf_ayFv3W;VEZL^_ys+aBpV^Xwqes5(?%hthhkNY`y+8hft2MK6H<pD3A1RBf88zmx
zw4X`z-hAn_`x}Dyx*umJ#L0Ntz97$xtGUDEgh|xi&<Mvw@2SQamxxq@a9i5kQ}L3q
zU%y+T+5d0+0#8npm8P+$GW)IZ1uTwZoe`&JAADJ#xNgYm9+{qTdi;`Yb|wjPMP-dN
z&%u|nv`WY$3nsy`n@9Wwb7H|n1Olnqy`uk@x45V!_@FA9)KVstR!gIt^98^>t=~l5
ziz1c-l>G5=ZgT+w#bXVi$u3-4LdgD&qm?J%yE5QYyBOjNkzv2)p#uq8L^rd&fWCua
zg62Wv2B({#9q=mtMc~{Twy~CAqA20~fi(g}|0h&WKOKU*?Isav&>ur;GC`dMm@`1n
z%~VjuX$o~IB<s5wXXmL_X;pO|gQl~x<TBD0a@V@q=G1050$8cARSe-?98|8@+bvzG
zVFfyiylq><EW+aBUg0otkQlIeB0Z<u^GKY8TC5OhUF3yuT)+14cK}lLNCQYYw6tbQ
zjnFMF(r|?k_v(s+b`03BqF7H!#gST7yvUFrkvA(6UQDp77h)O2^l@E;Q<ac|jx>mc
z9$ey}JYO%j$OZnQOxn1uh|CUS8u<mKuwpDj<mxNRnBpj3{JyFfTbVmVKH6+jjv~n3
z89D8rKMW|o!i6-TtcUB*Tvo#T+hgt|&C2d^(_@~k6R#Rl5YK^fCT5LYT?+Nc*d5-d
z9UHi|#m3lZ4SPNkd0Ry)Jgn48;eqiM&zTr&0{wTW<G!dB!_st|s<c9~080|<7Uozh
zzB5PU`6lhl*T3<jf~F|NS#s;T!MK=bBg`v8ACi`~=0gJOQlrl3w0^*e93xuBarep1
z;J<;k7s~a>6C@l9i%4y^9<#&B3MpC^2FvLgF-=E`k$kVftriJT*wiX+No`TB#EjwF
z3dfyz#D`v=@MNOXNpK{Z8pF5mRd379GS}0Wsi(NxFe*}Mt8OW(E=LVRiOt>5bQtvH
z)Jcl_-Mr!Uo^eh#igu%<*J-bbN-(+=tx4|~63onFHCB3d+zdtP6zdMK)Fp@0a0+E1
z&0%v{ceeSCJz?*VO~NvfTQtMgTp}bf0LQg>5|ckuiHup&mh+q}+49P<zb%B)oecI!
zn@}n;4DX7SLGS)h&Nc^0FYlrUU7h`Ajg9bSR$KN`bF`rG0l@5n8e~gFrj3ZYUu}Q_
zAP!_N*m$L8^!P||of-#IW7&&*ttzDzXW?>Q-ic1Z*~F#wu<vry@rzDU%G`KSj-X&h
zpFk;?)7yq5iaAe|mqHW1rTwmx_~ws(F?tJEZ#6pIC<bvy`!#ZJ=iyt!K6LaBVQDio
zW4aHmkqNYQ6mKMm#1f&2QBhD8h2gYSu{g9^X)$NLjC8e@nS4?Bp)qu7F!HPpOB1wh
z6lW30%;eY(5|J~`OWX`2ud7?fvG!ct3iCMHTLP0jSzs3}O^Ppm{THD-C(B+TlsU|7
zW>2A(9tXj1wPhX)sXZvw+k|#hsy;_KOu<!s3M-p5r=D6?Q%qI-9Cz(;Z!s69J{A&G
zQ&^2Q5pprD#BP(79A=PiH8?z!h}epW4-PxQ<PxhQ;5F#n#S1+AwFf9y4ODYzL%MN*
z$Q4C_QIj4U9*u<xJY;$>jX{!Zd!q+Ni830PEx8!pLg>g`5p_r`bf*xcP)~=eA@b#D
z1Dx2xkvTG-<^q>_9>LIgHiXnjM9NS~GZVgs2Ch##7*<n0OjWMFdM08UDsmBSDr!F^
zb{9<=x<y5Pw`v+4>Mfgk{ySlB1K-AVUy07ZumibniWv>zE0m@&!yz^NibR@r8P`oP
z!wYgifg-`sF74;8Nt&`?MXo-grgGYCaR(RRfC4Fzf&F8=ZX(i@1G{o#If|c>b+-fs
zDU_{5q9X58()?OWQL{>)yOFd`o}7BycZU9G(rtGk8~g$W^KtK;d(S!lbF%rAO_!qn
zj4CpU>Ku_D=79m0L)KuxG1HjYO`xMj7I>}hU+h|TTlhmMO3Pk_oa^o*Qz7WPXGX24
zw!jlMq#!4FDY495Q<#D2yvN~){RS^MzJ`<$H8jbG)Da0;2NKCjioR@Tb?Ih&c<esK
zd{7kDnj^Ti3$`BQV`f}&-2mg3MIl!4*TTVroKgewY+8&s;rXyC&pVscXv%!RJ!g07
zR7Zz${3!Ln+|N)uawm0l0P88C7sD)%n1-v`zDZej<~Po&7z6<G8$JPPJf!~m@Be?w
z#6>zC>taXPWxdt>-igG6*DC8;LYw*ehRwxC3e(Siu_He&o!Xl}pZ!TSdvZnTi05~`
ze$>9!<&GQwflm#@-&>Z)W2Y|0N_?Mv>b%`>YVi0)dac?jjOd9sn=e*ctMk&8u_NSy
zKBr_Z@}$vKtp03!P37Lo&mS9O#@DoesALZ5`^|eu&nx5?+<yGsV$bpKbj6>fvp)#8
zHTSvYn(@as75BGXa<=gGbNf?YtnBZ;G2gYRBYr9VO6b45cDd)G`30A6Th9OIYVGe!
z&f^VyzwzAMD~%T&_r;F<<L-X7)UaQhCXFC3oEJLWzmUT(c7%;nuk0tg-;Rw`RTpX3
z%FxedW9yaNAH<d)>|^gFrW+1tTYCDQI<~HIB3rxt`*~x!(p5gu$IB+V)sO!2*`vyN
zV~lQ6;=Mnx7tE7a+_AzWFMN`Y({TIHaac_*RA}Ndl?uR(mGQ(I<*v8Y!%F^-hxp$W
zuJ6rFyff(hz7l@EdjF%x>}L#Xl0I<RdFo1E{?(ylTz%@sriJg`vw7iZFb7V})a1;j
z;&}78+VeSb$(Z5$cwgzqiMfU;{qR@bt68X7=yprFBHy37#Fk#EadTJPi<wg9=@&a@
z^S?b?_(>k_+3t94$7I{ShMM`thKW=|W5d2ba@>1M`yUfS=aqI7hA-#a+mn1!={0{-
zfo(FviaeeH%*N`Mjw~c0L-(D)Gif);s+CLrqIrY&czK3U?_(w8ks9N$*2Wj01>R5i
z;+eYKa4VgKkv!@HM#^t2V<G!x{`hJRP#oDoJ)_Q~5?}C^)5jJ*c&AqejtxM}|5C2=
zFjn=Ad{v7F)5?8V1$UPa{R7UT6PC@MdCa4kRljVH=on$Y{LHZMW*x4VTbP4^w&&5k
z?t1<0Z<)KyZ<>Jf`r_AOT`kb*_6;6QeuG?_oZ4Z%ExkiJ-rQyV-vj53UElfjCeR;`
zTz;pkBELZ<djP}rz3}dGPmg}lfQH?J1Z&{!&(ADBNskU3lAgNpd=5m%bM9wPH&yMQ
zyI26+3SetT^9^2+L3Et60{LrQmD*Q3UMaq7*^M5=_T8nXM<<QgcHQ2e`Ci=(z7$$<
zKgZvBOs_S6Ve`&!$=O{~-?A23&%BV-Hdrs-^<^Y4G>x|P*%wpCMi*+&oLaX~+j#D9
zvMc=DU4Q1*{z8@zs^}hbX0_(ILgO<Q|8uwL#c<oRb;w1$Ydrsw+c;xPEW3^HDwbQE
zdw2gAF}{)n@;}ZNyMLRWE$lKcR(a<pb;CLte$!p~*|8Juob=SYoXeB)j-mHxWq9t;
zi<ESyy5H_8lCj>`tx582h77g6!0cZe5VJROCwug3oNus?SxJus;v7oyiPJk0g}HSq
z&c`_WEN#%|*Qt%pZgOntS*!lSvWOGL#2vr?+Q1>zT~C|-5I}7}-p^KEH{8#-7GS!m
z85}sQWBNdFHI3c7l33HIjT&`rGVoFtKFi>zuHze{Ne+t>KIS<uV<Fw7ops-xK%k=I
z8uM*V<kG~)Yq))f2_vFwF{|32y`mg7tM-C*SZb=0A2F^xTuM%ougsR*@W|XB+K<?J
z(s(J}MBj4X?MbKy*R40e#qie=9(Q<0s+lEAuirONL-v=h7|lg8<xT{e)%TVv^8UH9
z1zB<GyGuRK*E$Ug^;c(SH^9S~#UAQvz{zo&3ZCW8xY3t79OJalo|iTvdJwkECJZ*t
z{N$UKGOuo$#WC#9fX|BQzWuH(&uinQDJ)v;ON|o_j=BWIb_x)tmhExowaJM|wDoz(
zH8j{z&uX{-_(1VD>7B}DHYZW2eydxh(9qk!*{kv+c8k+=e|G3geK5$$U*oyYy3q^J
z2NSueqNXosC7Ry_t2rEM_7}Mv(h7}<*DUeOl`GAzdab}G0-@`+HBm5^pwZ6$;`Hl1
zx>rJ>U7dAzpqz9lRabxBEjv#5=H@HL;Xlk?D8QAbhO}@v9GAYPAJw!Kce=~E_mXLp
zG;Na<<6yJgd88@kG{D}uOE3?aD7mmbfpPMSx9Ylaw#1BiZN|~=ea_9*Ua$Y+LFsno
z4m8?6Q*1ykWb8=tkkpKfMx4}5ZWDi~NdBJ-69zW+$iwf&VrWQ77eq(yhD)K$W*6zR
zRyHtEpg{Y3N}!#RdY^4j`%(f`D^Q_cY6de|BS-w%U+_xL0<tK3bl704$hjPFW6Kt<
z%1wR7;aCm&$+3m!tNOwFpnJrAUZGbpT{~DiC8Mpjb=%-;UhSAJ#NibGcHOJ8a~vd1
zAgrbgc<~Uo5w2J$@^Ouz22UV&d7{y&_0kQ|fq|Jf{JwBU>~;m5NHa%j>hBJ2Hutj;
zdxH*!wa+NoUSQ*wcz@~B<VM-_Do_^au+d$y-ZGBy=JPJ5;jnor)DF6DrEU}Y60e~%
z#%>d)3aT7tkn>-~*ff9FGi!SM-%;uoMx#)~f2w0*XsqFo6u;6_;~RJT?1>T9o$7-t
z%-pUX*@1O?v$H}2YE4H1-Z1_8<AH3+6;KG$R5JEM{rMtv{Z2rOY8Y&1=OQ9}#u;je
z{_3@xXw@!Le3^1T!1ijtvt;vbW3$sxB!3G64~NjPcl_oW`K$V;6~6-`7`VhYxk!HH
zz0@8y)~Dc9^~w@-{Q3?96C*+2I##D&LmUJ87|4NxwR$)0Iq$y0XD!u;J@go^bg$Ew
zs`hQ)o74OSBy1YFdr%8L;HZsD@N#T3y^Y5&P_!wYds=JkJg33kU2mS%`rQ{xNNk07
zlZ(!U;Uj#mbfrXmxdBb>cPGdz%1yBgQaf%MG@U#h6nFADodtcvv$&6x>UJ>@7$<L6
zqSu!!VWG*}saDc$r#%DqqRg*4nFilgC)Xf?k&$<H!KP?Ks(M~J`xxll!Y;Z%CyhS)
zLKh5K9?+1TBW~T>;4{~!RC&_fVfi`QXaN8_N(Pp#vlYXjffyDH-G(~ufLfTBa<c5v
z0vA=O&517M)W(&P6!t9y=Ov_d|I@`FjY(u|@VAs;BFljVX5=C1?vM39`#UuHgX%$f
zc<v6a5`CPiWFe!R19v^kq5W6!JEg%IT5f2U$=NP0)`9<&CmmtzgackvJwRf<T0h;Q
z9U;<Cn-Lw*M?GcGq1P!PExGi{^12BJWpQp1Gj`FKBr)r#Hf@X>N>gipsnlTZb!SHj
zIpi}kE0+Rq%|Ua>g|MjwcKqp0yw|kg%OgRCO4sU1dq>AY`&s)K(<w$qoA70nD4ba9
zKW!NP(;eL6H101*-pqq%D<-NrygJ0kJ?;Wi4-_dv|2k_M!{zvbUf)6D{!b8Q_h@Af
zvO~v<N_L})8pK>qOc>CzRRr2+==vo_^vjOa!69P>dlAU7M;S&~nKjwobi*jgi};i1
zcp1rf+Q)RI@6Uey>GPlZ2C5D`$MJ8Np5yqA)}z1bQ}cn@4cxg`UA|kev5zt!;cc@@
z8T`ABISuca%B%49M&-hXJ~i)`KYUPh@b6VFY;%4oxbZ{wVtjNTCR`uJQNnP1byprK
zd{F=JuQ?FULEYQRreBGF{C6rb-Y=p+)U<aze__2paod5P|G64oM?h}8C8G!6h>+`j
zL>J&2wuto{^t0X*>Jy++^S+BfXuJCQh=niSBkHaDyoZMWu?p3Mh;=RgciuMt<v~}!
zW&iREeCK)_`_+f}!H={J-(WTN(c|j>^{MDsa^1!Fpkc;*&$i}bv(lK^oO-Y-Tn?2h
zu{C!Gx{D9oXNSjFs5nIPH$#18WhBz>md%YyK6YD19Je{&Pl3{3o=7&!JUXw-EI!wn
zP^I(M*WGi@baQ=xm19G^Qujk%mP4n3C~rh2+Il8)f^Nxo5<TChOyVCCVzXm;_+-{-
z%!$eYb&+rxi4$hvx#MBkY11MN?-~Par+WQsUsr~cg*l$~>}+Z!f4)OW?~=eOgw_p$
zmz<=;UgzULZy7v$C{L67Xc_0ea~IaLlT=9C+wtjo!Iv(}G0+<!|9a+_z$8%688`&p
z*iZy0Qi1sEZWH!X6sixRPe#mUIb}97`Dx?{hyZM}j%XBA6ADK?qG@?U_FbL218UO{
z-4^dw`#X*kAUt%5y*a=ZG9uk5FT@(2qz1SSe)AA|bZ0v;bJSQx+GDrL=~*K*f%6!f
zm61a!+j6E%_n~B@9tNG0dVSzjYxQaSbYtjQ1#aX_q?oqqfF=N{z|+q)WI2~uP=(`q
zn*kAjz~F#t1H94n&*|ha`;pt)krC00O~&%q<tK$jNzO>Fq;lpj_`$zCSgw-E_oa2k
z>TX7aX(ID(7BfaHy57nT@a(9i?<C4Cb<YAecI&tl$So`B$KCa1xa8_-3Cg0eN5|_9
z$f`lQ{6M`!9X9W`>x<exnII)A`}AO_aYU0rTabx1#fdqsN_x;@YJRq@(jbN=$P%Y{
z_-i|(y8M8Zn%n4Njw>Hj&uY{9Unm=1`n6=jRBnNCEOzVnE7j!|CFG+)cn%ObtsI7>
z&|)IwmvLX=Fc>B_C^6BDOa82n#3lHYMOt0paT^sHHKeg}v{?$!jHr<^#O)o57m3M&
z<ci}Lnzz`1RTon{YOL6*V%TmcYKB326?Vx1roH8qm2U87@<qoyYN+Roo2zb)jhLTd
zlA%gZS%0QHV82%5p9}GoBEnIt?t|V&iBpbNmZ15OGCAET`{Smp*t@G|NC-akbrokL
znUlxuQzl=Y9Wmh&FFDeEe0{9`c@q&@Nn0x?{HBQ*N*Nv|nvv;rRhaBv9zsb$J()4c
zPU~FCVWhdWodKx~g}0aZ8wl+i%aGkJJ#UY&g?r8!{?M(gg(NPHXj<Dk5~|4ev?-sR
z`>P|rVIs>fn^en{6C;$eLaWO{HEWb!5<=QLk!$y?Ylq}LKPM-^^t3B>XwYUg2~Qf#
zV?VG{?(u0%NJAZD{)Js`#XUUhg7=xtqX;H(geH0CE6SJ&6?(Cn_j>eP^cdpNZ9#8F
z$XI*zxXB;?zA+F7y~X;Bq(LU{>1uDgs_~g_R=7V`uxIVU$a5h%P?&zECEP5d$|$r)
zOR@D6-Jp_^#?u%}<is~M@j!L_rtI}Qw?%Y`2EvLWQFM65g8{Z;hV)L@co@0}un$Nn
zj3xwuZFJ?F?oW4sM!^uvgig~J<s(q!!UcH_^(`n45Z2Gpv^iu1ZCIKGZ`CY=G^FC(
zZuVIbQ3p(@)>()gxK-u-PBS3i+9RC#(yDlN&!(hBNfa`4sHfEcG|a#p1G+uU$Q=YP
zfSWZpw_~Dbny}>Xa~;lAvfp)7#KsMK!=I;aUWDfr1}jbOY_J0x;cQ1DFF0vxTrvT7
zL9Q!IAZdD#=V?hLtRGk_>5w70;Lk6IP*=cl%L$HI!dHGA7<QstRI}f<qJxeek!t9g
z2=)xf8#h2xh~5X;k$_n+OvN>%l(mtw1MWuBz;1?9ddyw2kTd`*AryMS`3I4GKCmo0
zWl>ZVl;vKB40lE=WG;^yRaF3^5_Kh4)kGu_!cbq-QF7(u{PsUVy_Zi=x@<DYWnmIE
zCJ9In{peJJU_!Qp8<HQxWOR(vbn8+)MMDc5@a%fi*~cR^TygW(i%N%;Q5WQ>pPaQj
z{Ra#cBbzWoVGxdVP0DD{8XVoItNnIbwNP&)5LMPXMXw%((M3HmV3PywW<<OGM}Hwq
zn1;BBQk5!i2%vO03EOd{zkzL}f+9>Rc7s3aOM_SPt7N21QBh*Loel1+lEy$QL^P<=
zE1nxkjcfFX8j=XnCAeG&bfPfK&(e~g?K2@uSuzBe#=#T@moaGjxC$)RJL635mudGl
zC8X}M2IcCztAnO!Dl}9uO+W27qsv1A_#S(m$wl0zxjf9%gSK_hp0y5grxtO({)m6G
zdq58PEOjFprjG5x`BoV#wA+s^7&VEd&E#aGZm7Nqy&dGs7@*dO`<Of8*i@+G+I2wU
zejb-~Ah{m#;^WPt;2OhL%<8By)t~MXQ4cGDC}BmaR>RfEpZ8~HOd+~tcEvc@2P;Y|
z7EYf{Ez<^RlJ{GYn;)QlQ@Ch>XNkhx%(f%`gpxz)0Ir6sKg6BTLI-uzuW8e~L2MLf
z50d->v0l$Cz*@zLxbTq-1tLDQ%9u|sAa6jQ5vZQ_2~U2!Ao<c_h8jtZzJVxnoDq|T
z{6h35zG%UX%Sc)gKMGrD9SR&G3R)Byh~S8{i0WTTiwPfkJ8t{I4)`gh{q?Ak+UQcG
zF>%X>7As`^+@-iEu-imdNY=+_B^qdZ)Nw@N&WCRi)Gk~;e9UMJY~$UMDNKVj7)8!T
z5rmPYTR7ZXbokgQA$SNX@Fc=cx<T;F8+FrwOFZe+T!bkYgpFYP=uiO@oTmftHVPGn
z8tc$Oeo_MmyC~xxBk+B&amS4dle4g9zEf2%NHuYpnMzO+ZHxjzNmWE?qv@4B3BgqC
z0Qf}99I;Tl2@V3iiE;g`Awo~UG~5Hb8De0Fjr)bNEFT6ZOOVA9Fa=?l+d8@)yme;4
zK+4=vqXAPhqM-8A;z8q{$1pa?#Q#J{?<PToLVkco;7cgZAY8uunDz{!U!}Q3P^E+x
zg7>XH7;;@$)KbW;QD<&Rh|G}nyk|u3+)guSiaPIUJ^hgJp3Q3u0rNTea=n3eo2efg
zb$Xo~FOdRrXmz)P#{+Wow9(B}4!TM}4X3~a^OUKH4XWvjUi<2nMe7cFz-}m-{Z^WD
zRNf?LhBE9+{2NL|O7kL$Hcc`%bYL(o;qbW_L6625L!*#ffbkNvgShrC)6L+hJ>djs
z2cdG>TF}#$<7-l#yx8cs1l=<s6U<qGf`DN{P?s&#&_lx(42Krf{I%_W+x|#HyZPU$
z9=O2vm=&p^7&~4u*T?MjbkZ89cUb$B?bFFnRpR^cyX~$cRam-Jw-08QXzY?%u?7lb
zvBFWXp~rcJ)+D;#zPMobsrqI0C@q<r3&(BchdkwOe`2!6Ue6a;;Yo6o)PMCM`}E~X
z+1{*7jPb;l%BSc)J~g_}F1%fN-R>KAk5b!xx82SEW%FVCb#|E_w>RaQ-)7GyK2_<~
z!x#9%NZl8V0scfOw(N#Td-WvGoi<EWYbiZnG(tl<?Pi<gW(;Iz_);n}pf{i6ZK1j;
z>u2#Nc3PiTc9F5MjbvPz?vwUd*`gBOL$9#*u6+A{=&o8TRmJ|Nl$ge3XF=h&o1N$R
z7P{Z$W4yPgYm6dMXpHt+_@e7Y+T6Tgb{;LXcM0-kv)AhUJ9mudW=KI@GJ3REl~>7Q
z^o+_Y+xFW>jRn?g^|?PAa!#)pN1I<O6sNvS<6kHqb7xAMpRP$Y|M$FelsNAcjmb*Q
z^2xu?{Bh+{Y+IpE9a~zj)}OQSI^LI;pKS&Yn%$%Pz_w-!o92wliQURx(%xubB{Np8
z-*fau)vO=T%bVoR<JEt*;i|%)=w9nt_@E#H`2PxcgwW7(9EX;DD%OM2hN_##*-Np{
z_z&1?{gv<77NfmAF#CZ~z%M<)fdH#?6DC3L7eT=G{o!T=3&L1_LH`wU!6OA07L*!e
zlJ~8$6W|Cu&7b{RWnSa?1zkIhk_&wa?1;C?Ej|u*0CpS@GU5ZY?1kl79UlW75*%(x
zP4#j2l00H=nedkBgZ1mKD^vaY=ER)}AjJK1$;a+g2Hg`6jY38I=6m&Yy=26`FCQIv
zvoun?f7&{``TYHQYcczaPRQZ^=54NzjP!QxBzvp>n7%qdFDzdiTZn~jOiuMZb{S~8
zk+bTz%zgW`(`3rs_NGL5TH#baQx=VIW*2RqU%N@_dVZ9hx^~jJ7e*_8o4V5cwlpUJ
zdVB0}5@1xJ^O*d+)OYyp%|>hSC3}N)SnZDQK+!_xS~0g7aO3z0aPY?Kh3Z6yyss8C
z1P{%rvB9p|&yinL3NXAk<-Z%U!e1|ff+$HRp3ODB(y?0^9Ba}V2gbJC)Aq*KcPi)q
z04zXuFZo3my&GYF_t6Ib*{<S1|2m-Yv2j+Fj2)DIYw&g~181x|OgVHt0Ul&T#e!!q
zc^K{#hqug|nQMiqzElY>Z$|0IKxXB%i-lagR0*p`AVE2CTcb}-^WDnNySgk`FmHbT
z?)|KDn-<Pqcc*%v-}ZSVSs=*sqI#{zN;HqChk5<y$QPF9VIFJYse1%w_wo>p&DY8&
z{${L09%r$4>h&hoBdlUN#Ko_V5IFR!utFKMfP|CSJxK8!OV&53fAuL}Y>EDkxeqkK
zF7sNanH{PmkcpUldvn)A_q+H1BV0h{r2Flg$xrq3zl&M(p$if(6R&Q8vz5pEq&Kvc
z!qMe#tfEY=I=pF+xEt(Qxv+A27OE824Wn{c?ycsH^^kHeSo>Pf%uQRh?-<63S1PZ`
zKPMe;0P_bhIdLQR<1fs^?PU|3c7Aa(vB55^7$fjG>PtOdXrhhJp}1qAev&jN0R;Ec
zvBobFfY7-HK-8bm8remN*hy&MGVDb#()YieaF^6X5@2)VfF65QyVUn_`M2)7U4fa(
z4YL!bMWz3Uixo~D?$i08d;gEd^h4795<Ip?2fJkyYu9on)i~4223_YXV=MK_fO~@A
z2u)n{LE^N~hNsB4myvwi3G54bAh2aQSWjfz`V{$gId)X@@w%gJyNoL?fdfqT#=M1o
z{~i7b9fZ&6N-a)cEzaM{>1k{A$XcvzuNueYx?A>XXOK5L*Oq-YhcbjQy`zv!#Q2Ch
z25wQ#`f&Z~0nK(M$7+4C!Ou5dKl~rzLf=RCn5ua}U7(EL(cQywP!t{gXPeE3&bwx^
zs=t(fCx$A^Nfc<1UNm3QQ?$-rIbtnPeh{GMe)k4SH7NZ4yV@apcLQnIC|PhQQszM_
zt!b(c&rPGKMElHG6Svq#3mLVJ)6+hXmoC%S<Xt4?zBqqZjl9DxUAlLPyks{%uT3fI
zPeT<x(SS428-m@|{^fw0mk{i&r_Z@7r->hn=(kk(!1RrPuR(Cb7@B03435=aw-Y#~
z--}hPxJSr{a<`Zrs%p^1KB~w=(Bz<P_YZ<g=y}JC$$G<iEG-9U#GI!+dh*Iv+T+(p
z<g0}#^Pxd^JJHSALd5(5jGz`}E4_=~g0|lsx6(gq_>$%IvwHu&)@IjTKuT}C^jnjp
zJW;w!pGzFB&F;2KqbR9yoP)Kw(1Iq%fIDj}YtPpP_wajUcH*#ByA~!ja{n@NZ%LN;
z!VE}x|5(GkMq@J?h>99n`YnaU{={1A%l_bV3T!7vp_(81gS&6)k4a}syUg$1u3uDl
z^?b|Xa}xZ4EPl~!wHgqGp>#og^<PJeAnd%~&q)&(Mvqz`VqNIN$p)iiNha%cmGs%)
z?>aW>d!|&_mYa7sFKxq#cf1m)M)|#yxuzJIxN(U#)gLIlc<XSf$GteW%OcLj$KPF=
zP!Zrz+itB^K7l*bVsyUk-ka)X<Zx2opgGS;E}*TtE-yyI*FW~sgcg2uBo@+=hjsPq
zYxv#hU%!JrmF&-~&64wNN9E7Bv6a#G)ymiA!A=qap&K4i>%0d045%<9qNL61T}WCr
zuP<f7wHJ*Wju#k>iUs5dI1WmTTXN1@#@-ybGG4GF^R9ldZOW<3&1?FOJ%@E|()ny^
zn-3*A{zc0|;Uw(bvF&r3|K3M0wt$I}WED<TD|VpiE?IAHY8}sH-_x|FwaDlUi*=z}
z&W;ivU5||7GKt;Nf4a{1(?9eD*A$ZU?ps*QS_=kfXm@zPm2haMT4;31?qVt=EvWkH
za?o3|{(M=E!-!~1t(^w!-=xZ88|8xd1U!2IN}vKeZC3M~7qYyscD$@M%ow0pWh3{{
zV3Qg>r_am5;$zVzD>9;P50LSThrJtP&{^T8kHiACBP@2It)$A?hsKEPG@!#{ZS_(?
zC6_tWJ{r@7zQ&I~eW9%#FhezT2CQ1wMbGHS#;hVZ+d0hkB!!lfu)+U$^oR92wfz>s
z{J~FAgWx+rttiZpNC(Ep3-)ahsi2Lrh@W8^L9&o2=+-;j?15P!pR%mbEWC*bPaLaY
zmVmXI+ZkB&3LkjzmIB+$eZ2o3_#BN0^zmCD$N?`f8W4^L8b``8ALb;3`qf<*{tZ+7
zcg&AcMeq5@oan>a0$2ih1q%OeZNZ1Q`uhb6kVgEb@-G|7K2rJ>hokp#_5Za%;iHYL
z7ASmF<?yREN&oYNr<C}JZRq@fZNS(6oj*TZ@&8Se|K>)|nP}iw3KV|vJfQvuKeme5
zNBs;7vB3L)`l=1Sw`PyP7r?7g_~_sJ%cFmJj>1e8KSdnvqklm64Gjp3_we9-LpalT
z^XgA{9q^YAmRKMBX7xkyJ(e-vOaIj)=))$kWBgZt|CP_KX^2<I?Z>;F+f8#1<Ft~k
zPx4TrI#p)l=Gqb9jgy02BRtr#E`Gj@Rb$YXFsU!A3@ucIv4U8`LxUFIr$kKMJj&H0
z^4K9}vk03mep#<;uWmlVt=Up};_GnVR`M{sH&3_o%*axGitU5MjiF<kg^O&kxpPUc
z(MbeBPQjFuX8@#{#Yr79nvi>(#J>nD7}?mREs@f5t<7wcF%ued+IYTA{mKi!CWJaZ
z3I7T;ND_d2CB-HI1Tv1oo{Nh`z+UR20#t+VOq}C$rrc}?HnE;HtcQs$yi?*S7Us(G
zP<p#LQ_Fmj>G}iBmBKt>r=*k_g!DTzZD@5J(Dld%m4@>UEYN$(nr9MaMz=Gd+>4%F
zf+NUr$q{1%hJi^0sXyk*m}rz3Ycqb@Xv3vRvET+PJ<KJZm#Eb&k?KIFcw90o$_pm^
ziR9zwt5r!C1>q2d`8?L7(J%8L<hnxK^a1Z+!mvG6V}8|4!^U_v7I;|`<K~ztP)G=6
z1Z4UN8Hj7nk}?}{Rn=^s(FMTQ2bx)CnuKAtAXhRoge<Uq>PG&S;q>S;deFY{=F*~s
zH2GN4jEm7Cl$WMSgEtEyfSZ8{a0$>!E-IBe`G=$87T?8}YtHecR%n$&ev<>;s*qmP
zOE9xgR)n+m5xor6dPT7v3JVH)kTfPaBL#6|A#_=5H9&T)rjEsY+}TJ^n+g!ju;c5_
z(=yU34=SPUo?XOUI@I3Cv;3klUONuww6FZNXzB%N!ZJk8sR@*jlSTXsB?6&lQ|U0U
z8$2&Y;Zqb%mC?<Dv|Z14kOKG*fo_}?1c0kNXcdWZJjs#BcZ{@=_%vmNav^g|5H%o-
zpXC^cXDD7d>`dT-2$?x}0h11`!kNHyrswC#yk_RrPJjm2{?XYeNn7I2)~!Ic$%YvW
z(Z%nHgew5`kw2S47o)IB9$c7oVnf?P)?j0FUS?ZnsvF=lQb;jI2&DjaY`P5aXQwi&
zJZjGlnc;TVJT<}^ui1)h<+UWwFdQ;U6>?0Dx@D#Fh@vRI8QCnK^1(%Ui5Q6hSu_lL
z;}HCwr5@+&#3pu;bTrP%_xymjb(}G5%NktDR*ji>bSd(~Hp1rM548+NEn6g^`v_#U
z)pB7ZmuL+q3{`VS7}saa3Z;ifSi)SM$n8~Jf_f#1w!65`f%}2wtV}~=D#3hhGSrDH
zJVzVu@0kR(cR_DOklm8vus-HhF8sMt=nRb4hMSYTMd?}hj!|qwL&d7Jjr2LLG|-H}
zpm0-KO0mr7J`$WE`CW=JP2N!3w2noiK=v9xR};ET>!?V*D~k~jtPF>bOoWMGwZKLR
zY-|=_SssQMDaJA4f=G|R>%&G16>0&t1)_Uw9}wD3QJ4^^@UqTYVXAGz|DmU&2z)vd
z_j@oBTQvcZuDETe05O7oa!|D*Qp#nO4L=kGR1oM<e+@lrTiY2r6=3cFl7v_}W3WMe
zQ31|Y0lVY}yc}GB154a?#H=4s3WdW6fh&g$6r7lRZX=2h00%o_3uMBxgzMwY8DIUf
z@#iM#)gnw&*Ag8<_e&OL3A5lIVMSEHfB?*$@ZJtHQn#Sib9Vi6AX@N;h{$OFk^qrB
zTE_w8Ss)d5nQS!Njm=J4gr|3a2A@%Q&@qv&NTL+46B&A>kS<dmlW!APl=?bhrep`w
zYhGUU;wHkd1!&t3Y=JG?xQC!%!_}aSC!8AsTvA*?|J+SFkNTr1q=0`66)3`H{hY}-
zLNFFW*}Dt)q5)!}a7m~{?OPBS#p2{Xc`j`$L)y4$MsH!Jz=E>ul8JT42q=Mon_nY1
zjPa2~e3q;3#v)&j07y4poT#&}F!`LLin!f1kT!WFEy=Q<F>Rx!QsJNOiL|m}R+OU2
zB4ozIU&hTyO=cI@0kMp!B79$9DIp?=c*vos4iMJ6{nmjg+zCy5zQ5VFG#k4bF?}Ef
zeNn?SOjM>AXh;i_oFk85k#jNvo%u2*vfhOZa@%J*onkZqI8w-q5axt6=BrL>fAyr;
z73e9$<5`LOv*Pg)CIc`RFlM27FzEXQfZz~x2%Vluc@%+OHWQ+X4~{`D1}!w6s1N57
z0J`qd@UrX%{cq6}_(5$}Cg~v^mOpf?ByY0Q^nxBp)CI<Ec2-x1oX#?tpl;dFs48^c
zsJ7hN)`ie+uwobZoXkEwW?JQL-LA5M%9`uMNQp#K<mqo@)lV`fDVP#`WKcAOedu>^
zrT}PSPXsRt7~hr%G~xK(mJP)bdk9iJbVrYpc4eazQAJg4MkIo)?~;AyqOuT^-9X3<
zxUm_xvpkaygacrH<P_80&d=z&yXe;4k~5Zzkr7h>F->I!NehM;4j=%{wmkw4i3+%(
z3MT2-B7v}diz%RIM*V3Q#bi;6(Nai=f@-R4>s(>l$yQ`u7w9%{DRt>K@VD}Sj=#>a
zmwN)nTqd9f2kg1L3@=0)oyhM++e6IwPWx$i`qyi!mNM#Z+|}4Wu8*5MDB%XSSQQHd
zRY{DBN_AW<=O@f0LD%kw8#^vH6mpoGVXScky<fu>Ycw_7buiarsvtW&=V!r+n^_k?
zb~q+jGx{dObs_<MBNrSU{Wz@xYKEaG4!|K1AF5ic>w}L+eG;4v74QcR9d@e&2PBl-
z@R%yCi3X6+j)AKVF(GxJn0sY?+{ns-7ANSRbjm?{_pId%>Df^RXQPFTnYfKbxo2!|
z=KR92iV~{;VvCKeALnc{IS2xT$s3hL2Op1aoesz(!nILNKsA=|#1|ulyJ@^4fi5ts
z1L+5C1|*mj$TSbe;Ls$%Jb}qU|4xoppQW>?`v<2LMY}Kp@Iu2C!yAL`azv-dxN%jC
z09FdK0REP4E9kn2{+_^Gbw*M9Q@p>YL0xv8hBXnF6b;8sOPXm7Id7nPXb;!iPjYug
zXUb1^-Ad6PFg6QrUQC1DDq|=T8Iwo^JAs*XbSdObu|fD@fYb$V*f(o2SP~E-x{e_!
z5}@fd7;AB>CBv#A>;w~l%N0dv1BMvch+sA@2+b<Pb!~9xGdp7OyQV+QSK4=(gJrrh
z9s1<DN#%RrRE%#bd%yIK#6R;THgQd1Gf2Zpf(SoB){eLe4^`Ys;z{BW>h6h4bA+B>
zLS^PO8XawM>yTK@7P9B~kj>}nwi%cA8@rTa=n_%-aL*Qdi5#MXmkP8p!z!m*3C$Lr
zgll{=H^&aO&&r`?vXz;k4%FBWSsCM6&VJ&V#Iw1l!^lik_mR`PXF6t{9;!dyk;|;f
zbv)C=UTAfi#k!&TXWnTm^v)a3qt_hr=#%c!Z0_1!|2^^t@;eE6Jo%us?qRz;F5S-h
z+-djeLMq<v&h)zD4;G#*A~N9n@*PS|eyu2(`BeG1gdD7O%Qa>lc~5aduaIS#$1d=p
z=9u-zZr6S8S=|n`hx%08>KV|t2Od|Y!G*Um_arBQHOZ+%@k6Y4BKAy?I{D?o@ge(+
zeuI;fiK6Gu`Gm_pQNteX;Ga<B&Ld%jx-Io;FkJtB?n-IJXq}zQ{n)(*V~hG@#8^gw
z{KW28Q>l&N7j~7F?Cz$0;iiTr^~=VhF*~I-zx&;DD4l<`-JJAfAgvP5KCG<stbaN&
zp@BWoN6*=+EHHXd?xBYZ2S{j;FX9bbupCylKzW~C_58<=Feu`OLVP5D$O(l0cnZZw
zgA1##oR4`go%dA!dvkclB;RU8Z$Pq+Px#u{eGvW+HKs3?_f9$UYisZ~13p8=9fm&U
zc&`L1lE>RFvUB#0oQCD-B%hccfYcwle>K?%H64=H_$$Um6SWena(_>}-`0hM&^zfn
zo>5JonH;PVN!8CJDRhjbtQu)w>sQ>N`{m}=G9<t_{->_-Z1_kanIDAjNOb}5Y!RW2
z``I<+>0Yh^0N#-5ki*lgug6|-&%J#t7toiS2D&@9hwDi_J7itup|2XMjL^S+3f|n%
zp_$&xMn^YDbFIBo(5<eD+nXTE-Id!7CzCS`$%z&Y>-b3r0K0ajbW8)%TkOr%UUaUz
zp(kK`4XJTM?cYl<IVs)H^rpKe!}|-R7n`(kHs$=qLih-l6fOMT(Ye02jrq0BN$UOO
z%TKpB>W1StUG1XqjS=s^UlQ(5LbhGthzAutoh}smxuisZ(mxoJ<?JkjCVn;p^ZvfL
z8NdcY-6<97Q9#GTDK)sauo<b5-L?~L%hkfvf2h<D$nAE+^HLPH@iEVBBTG<W0l$+Q
zxEh%wyo2|<QyyZSEP2VH?udHm)~oKbmjOFJYHu|f<s0N#e8fJjcV?^IBu$ch$9z~y
z8GYKf+CJl%^t{-3iA_5%z9<R6uSz#^IU_$$^u_^q%Bd}B-zi5CLcLGw#iU-Sx+Xyt
zowIeZ+f~9VZt}z<1d?2KZIa!eg{_P&ez}kf$eT#aKhDnl1n&BLlM8M2G>p<Ij;+Se
z+;~9$2j_9a9GFngjy>syeKh8WJFvyF@+&}cOE_hoqYAy^sny*$bmHMYz1@*(!iU1X
zzU2p<ChcC(o+T}OjTd+5uUSWp-7WyUhBD;ZO<2r!Bcb41ZU2Li&eD9NFSo>H9e$*c
z3RfU*ch<nN$NCc}@%sMrEiW(m_d|d$fk(enI)d=hy_}1a{GhbcT}hTu3vuVH=cxpf
z7wIepAt1$O$=yk=jGW4;g14LDGCon5EKKE8-pk$Kh5A`1EDgCre6M%O&^R+meMHCx
zfTY6*s!7VUg7#uL18-f)8LkM>wz&gG1STZVsI34?qaX{mrl7VU4ldG;##i9eLJq#z
zXf3;+g?Bh|NC!#)5hE*OF8t%0huRvi|IN?R>X=eP&XkiBj;}*W&;OsMuK}7s(L(YR
z!XYNfon$Bp7A0%X!PYBTfv0`Zi$?98qH2^b;7Cv%_nj%|sJR;*c+B-E41|=9tY}0N
zDg5?Hctohg{QIQwD_$~mOui+1#Va2{B<K+w3830r$(fM{agv-324Lu^nJF~P95+^6
zM(Ra)RcU0vMF6UEY~H7<LNDL{Hm>2yn0ibbaC?hWj{3;`K6$gL3NbNj4^>r5_IVnR
zfA_-eBzi##;Iw1r&#LAmWG5tqi6j`G@stT;|CoPgLH6zBn`IxS@Omxrfg;q@tFv-l
z2snoihXQXczX_9mP)b|vTIot^sH@*)&anDYt_iB8tgKz*h4GSifpOF|u&oJXXT6co
zL=l2Rm_8B68YLXtOHKncC&&Uu>nrl!T$7gF%NN|nOPwF9k)bKa8d*S5fF!|i6(?1y
z!;qHz{zPDsNE1lLtrGXUu<w1Dzkp_RqcGLNvHw#%4Obzwqcd0FzaMmQQlsZSff27p
zMvMQ>L>zM%p+?@~aVr9h@e#NR@EUUijyRC)F?!gQ`(0e2;<H>GHgF#0zEnQIvMFN`
z0FNU_ys8G&0-z|hUlS&$)>nk)FQLt4munntN9|2D$jTDVx(IO<atvdPBJ%9D3|L=5
zn9NFW4C=OpDHq}n*GbQzmF#od8+=pFShNJ8cN9IZHn3k^c|CCOOLcy%e#5|%`yUfd
z?BQ5H@8tf-F~@(ff|EGORhb5Tv4pQbQHR&ih^TZxDIzvuq-=50<`Nf97{piO#-7&>
zaQ*5PDFSU13)v#Cm_n5KoQMP+ksLN{5evF3S_fxBWkh8{gLq;9j`e!bB1J1`+kQ4C
zR8)bEf$<5bS%SW24!gNIHCpXY&n^LYTtqi_bYP79Ah**2A=`tI09T)#n6)gP2O~O}
z6Iic(a4n^vY$}oKEs5df7PtqBK_<qgCGXzKAvn+8osFUxZyZ4)@ML|Mh{4;2%VruS
zxk-Cun6Y*vs`!JmT|(V00<O0l^F?i66iQG!5-|twG17Y-+{usTxOpMvmE>L678ox7
zDDYN!Z_Y<1`4(RR5wSTRQ1NcK66f)1IdRP4Xw!}W4L@$e6F%4s;wFw-y7h+gh<sb<
z{HKn_uj`mIJkfb4^(5|3{F{pKj~wyeeBTlO&3P|G^?!B5|AzUm9Pxj%2!*>REB{d8
z?%C?UzmcDvFkbXP=gvE`tA6;v!B?jUJFwYbG3d!z|H%W<KXCZ}(4gl7hyPze;uqlb
z|F1UkfmP5iBk`E7e4vy6+HUO2FX8zgNZjEa_5PlqR`I8I-0TQgD*4gKy$6;cGMcz^
zfWT}YE2H#>|6z#~38VvrJ5Z&+4{fi$;r*wy516e0rVKyg`-p~l{pv&6@FtdA?>~b6
zv^RBMo&Uf88&B=@;a~Cnzx$wgPehF1&3Jt6FFziKJMd{GSY6$`i$Igw%{HQegktn5
zz?-K>rm?z_3ljV{07+vhZ|bK=AnUJmn#;2cj^;KhGgxlBS&)G4iNuX^LMx<mg~uN<
z4uns4DESW5Nf9`^%z~6r=1D$j$TK`^EzM4bV#b(dHj;wzl$($hf4&tMV)sIR9i5eV
zuK`~lrXRkE3x{TmOsO;B)B>2~Z?NPeza6lumXP5LDRVC|^QNtv{CgZ#GAuev7Ui@F
zdkmox!NS=Lz0S*6Gb%GIIE%GWH0AP2@LB9C01kl;n{-kEXsu_|fTMDV*GZI1$dtbf
zg!0}Qrm{pQ4+n;X7-B$zB{^j4(=sOQ97?cu<7w!qlKi<*2V!2mLv9Qt*!8VDg6BC?
zPLbe{Eg?z`DbT^dXUxI)aJds=MhN$}i&=Wx2v)c!EC|D>9jNo?*93hbf7JP;BAbf@
z1#QHMPjlJi#9@>Ke`vR2$B4^-op<O@PXN%vJ7<*`tP|vR04Artpa+6jF@-9L76%6@
z2Y5tmkq;=k9&O_(4Zch83vy#u*4>(DrGiPZuEl<FD==&_4kr*?-GfHHY#>6Op$@^#
zo4m}M%dQZG7d*q<42?SI&r)gwFcLy3bC%Wc=0N_ubMtUzj)s>k0rwYDV!Ss@1hfNZ
zh{VDHI@%QHi-VD6;ttPc)D;~cB$JS#jWF2a3^Rm-TJ8f@XjwCjedN=B^s$Kf)DVCo
zYC_^I0IWlaJE$Wl74INhd_sAc0c0%0`CsH_5DQuscY#ETg<ZVE#S24ZmdGYhazN=>
zZ7)uU8Gjr~YO`}%-z-Nvl#sn-@Q^*^0EQ|I8H+=D#@~f%g=mV)7F4o>HjKL+>MB;s
z;UtoQgHGV8@m(QITZbs6750=;frW4|RgN$ffE%(V3ucP_H9K41pkj{4$IV2U>-lvE
z9)_wnKVoyBZhVnbfb>@tH)BKP<eue6T(R@KL*?_ScEqSS>$m33qKj2Ed6;jS*-To(
z!zOHL8#CqENx5JuZPknRpAXG#CVgrVhT-ABC&F^(nhpaiG=Dk&2YSim0Hke}@#j-c
z#+Prqr^el<jtuAfzV&OszN^;_atP0Fub3hG*3+$!LbKCfQo323&EWtU$?k!U4&?xy
z>VtMxNze`_v>UY0805E0fV2q;0}5!zy#yUpkI%}@BS=f|A41brQ2_v3Y_rTbORU(Y
zp&seMO%4}jO4$hKYBP<h4!>4cy=)iCHtRRK5YceK_9T(!w^i1p0#7Cn>@^T8P}Yx^
zjhMYhfAJdP*wYNC6R_1K0L_A8W+@kWdX(kGgvijZqqjlnY~o^j10DF22-M`jJ_rQj
z0Ljp|Fa~pIz(F=-JUwOvh7qO?GRN~%VnD(oA_m^5%;kV7Xo6gZ5K8}g<>TpH)==D}
zAPh2oGZp|~6inr19+_hZXXT5onLyJXHwAN}L*^Ketro&AW=u3RpyX!6v~pq{N@>Pe
zu$of04KAUW1aVL>)D}nwM=R(NX|1@C1ZNG-dNjCR@MxeQ1vpf$<|$E?*|54#!AMK;
zH}&&>{`MxIY&a4rdNW@g-MwQ+0*QyG0&Ql3;UGFQBBmu^UmoV2VKDSai<Ap<m@HsG
z#0v$?Ex9aH&gWb!Ek;B&4K^@Xp~3-x)De-xl?PCDQBL?4ksCRED}E=%h^Z_~_^hfx
zm0yr}6;4zTI|F^Rw+Gm$AG@)URD#4+k*JJYmF)-49-s~8GB1>D44dvEY;A0oHZ>0S
zmw<r419Dc^{S9I_J6IIR1{M%z1>I#);utKjoDR6nGj8bm|2PtCW2(ReDN0pu5D#Mh
zBj%HAT=E77j6j&PRxoDa)(N-{r-FNjg<xiS8;=he7|;cF8Rwwi!nh5G8?6<$;WXMD
z-KxTdV~mH<ob0)%0>`O}kn<1Mp-Kj^A0oFxkjXRUYUQ<Io*9Et4(_lffNC@$+`xpW
zA9rT&M~}@D9NEG5dZ3R500<LTbmUCRbl}s&M$DOwxw;aIU}jlstN}Oh77MJ8_gk>L
zS6Quk!BPV=b#Bs%<Guq~zYa9cWf>EOiH7LP(SVyK#aCX&eavNv8!!EJKU%0cJ%~yj
ziuT2ml0svq9fN=W%~45eF|m^XiT%_(Pz`0Kq@y?ETAc-c9e^De2BDx2`K~mOP=>f1
zTq>ZxCaRknIFuez@5j6$+C}}ca}oIW7THj#KdarQbD6+@Q?!Kxpt_uY&fdBZ8kBM2
z&3=%J81RE4gy&Ti!U^1=aB>vrR6v>nAx#q=n1$mV%ybsf(Rj?YU0mVlt(YO#n&cK3
zn>o=j)5SHyo5h0aMVP0N0Opss$o}JE@b&6pl*9-?L8E?Zqpiu*_~)M6g#Ljj5gEfL
zOF=+wM2w)7-_G#SVwy>QOl=r&XOyTJYeE$z=baY(><DyG#^7t1v$+GV01AA}5Te#R
z<5;_365*x;r{WHo2Yfr{lJ%~@B1OffalbRRsMMOHfK9=R9<U~9i_G+$?|n>C1c?OA
zq~dkPPO-|S=rN+KNIZHQMu#Y>qtI4@fddMfofjyC*2Pfs!_A|v#H-t_n9r1*UW+vE
z;j%w%8fDnSEnAcg=&V6swq}NEm#uD>_lPJ&Sq^H`U9-_yc^RXkS8bt6R);01R3D!E
z>F-c2kXHuK2?S0zDp8Q<*+K7w;qyHKeAI8E#7DyQhy=<Y=dcUQUZ;-*A_nrXL6Z3$
zObAdG#1m_fuMkezJOoB+2=~8$FylDG?ptWsZr#KhXT8BPDv%>?BUc*0>=&M?Po?6n
zma^T!9Y4R#w#_1>^?nJrW}Fuc5rMRX?n2XIP~oOO-Kro3`T#G>%wf(!<~kU;!G5JX
zNMsG-oI9MTbxB{AEggJGkOR!owW!r7jj8%}@qqyyCrucs2;^l2k-?o}oREi8^1-Zb
z>uGe&+Pd@lmx$m#@edo9ss}fOelMFHRHT*S?~y7>b@O3%B56LQJV>e@uCBUZN_WJ?
zsvp`CO<*`MV;$8rORI-$*nDj)I=Ob<oj;yhKHgF6&QB@jT>C8CUtP?)X3Wgvc5KPr
zpE9>y;Xk@k8e4ApZa3dBVjN~8&8g*Ca})cj-MQD<W{{Slm*mW`>g}gqT6+4ihX4A*
z`gfO=A3YK4Za#UB+Z12#?zdYfn)ej9nHktePbqH<h2H+jSb1y1)uL5cnMdVS?c?nK
zt&WZMHnj8D-dDQbnOfWT;K%+@&#Z*Tlya7ms^8-$lEqk{pZ_i^e=ivik-_Zws{5o2
zJi?^C(rE<}fp(>H#oh%~_a1~1fU?-mPBlyyHewci{8)8~u~Vmtn;4(K{eaiFW#j|I
z2`v`3fAZOIYT<4By@DJk_TN)`26b<p%Z1F|V#jRm^Vrm0#fMv8c4?|_!MFy#`Mf64
zZRYyQ<9E}B!RF8&W%m!43Kz%YU#8nH*n>-N4CR#NnyJu*_2zy<RT1RX?$jT(%7dRj
zN!Pa=-$j0G-YA83{5X*CfNT_~q9?uo1TY%1^6b!sBoLKV0DB!nnrwQ+#7ub{bSg$W
z{t?<;SjD{GN4{5|835^y0@kw~K)bynW(%(Tz+ecTcdTm4m$3}?<iwrsmJi%#ZuD4q
z7qZtpyL{l+p2a@iXlav0yz!UOZ&=-U@b?zhlJh?JCA`nvJEd`yKIdSR1IwDN#@cJi
z0Ys<%>ENIYEKO3yUQ$(-3du>Wdaku!x=O-b4<;M@ZvunbwC<@>S-@#00EqQsp6O*G
z0+5OgLQ(RFeZ{&06#C5aUe4i!aHep99+MHp>J|cht_Y)={rQV9kutlNh5c8OqfIos
zJhLH1<h|MV=J|T116bK(WT5n2IHpLG;cs7oi+pXLd&I7As7n8v-P2BbXLek9)`B6t
zx?y|AK;xw=dr!V9&q;sl-ng7w4?OmB{1;s(7v%&{q6T*DB<*Z&EwosGzl%@*blE*>
zKvfEJld+C7`MAGt>u<z9-~E6jpP(WTs#YnJEJQ>K^AIcyfMJ1&2?EjNvD@}ZVNp1d
z@MrBo{CSFZmXLb+F!kK>C%FTJI|FAH{2+v{JzIUkzsOGq*qJ%<sx|2HM~}%#_YHTX
zfuAew&E1kc2Iq(2x#nXh7qmrqN<f>wHPz$qwzrPe>SgEg!?bbKXj$?Mwy)sg(;6dj
zK|eNd^S5Er4?OQ$j!!H|p7X`6S9$Iw7gEE%?MFxV7*|G~%)Q!nef;wPt?N|8oA$fW
z5lJ>9N%u{9NQwdj74PpAg(|Thhk){<6Skkz$Sy+0Y{X5vWS>;=E)Z+Q2gzCJF0Q!1
zv-49tf*4;Iidb|nf5*u+Nx%mIHivhC`tbq22cWyF@bj)pqqW=e?JWG$$u6Ncx54K6
z3QaXbV7=t*uongq!P}SeY{`3bJFqQ(Y`Y!3pdHIKCk@*}@Nzq#`2{9=gPz=W)WBKX
z0{GYbHpIw}{ILSmzq-myy4+mHusp3H*@PHQl9(7ae^0^~9`k#xP(Um6L$?sV2!kiV
zIf!G~<u(V#8JH7je**`BJVTE&Rh$TrGYr;2P4p^vM?831Z%De$7a*I3m#=5B;%-Vb
z%FC7jT4B4tpKdBxBvypbRrB0%*tFZ-tVS>Eimw;u3etD2+QZ1rU9ZDeguGaP?-%)Z
zyPC%GuP6<H4dmBj@5EwvgD*HO3H+>Nf?fvdUbPPUU#ariSRQ>UEctPu=0V`oVsMCJ
z+1Y0!DHaW?)8jZ|$9M??CU?)e&}_qBB@jMRJjHQ<S8gm-RN$gH#Ru<tWEtdl@e5<*
z6;G_}lI&jhpK=`b>$?AJVP!0EfbY<OPxm#vyM$wh;CE>TYJ1mAd!VYLz6^i2o&41$
z5Hz)lbJ4gkRT@33A6w$qP$3c6u(W1p41*B*N^nS8>s4k)l?91S<0ud&I424CpW;?t
zgAiOluTcC59|~NAX#h*(wgb{ce7}<%bjR(3(la=gGwQo1mjJQW9+Tmaai#efy7FYM
z8-JZZxbQ`Fm1JnKgu*gb!xtX&%Qf;7PLJPdIDEgHg|J+n7^-g?1U?G}twx4Td=Bi(
zq#eNlO}ULunfJ77HRQ{oEw5_3KQ97F9+W(*CMXE(BVfDC)gBDi3j6xz!`?H-bK$8W
z$(x#B!huP<4D%#-@)%;SIdIVR{DR<;8Ne%HlfL2-ACCjK1scx5Hy{u_cYtJJLKC^r
z70}n~>16X(Lx{D%E}UU=D5FT<aF&_|!MJWk$5_nuA-Pr=DtK(cCfajY%4%rGJh#cU
z@BO;+LIP$y9lh>Y<L=+RnaAd74T%jZSTBWDQ3-brEgzKln@CPZog5m_$}+(-rn<0p
z4~uD>TH-1O;vB%VlpFl$&QM8Xg^7tS5OZKppa*Ei2YNFgALtTZ<^kSvQaFvIv)F3|
zKiCm3wShRbhwne&PIdO&(y#SU7lo`6-9&ei<&(n3T&=%m_VuIM{91QCe1raRVW(20
zN=B9Z2or?#N$JSI+CYY-)-<^v1i&4L^u7(VE$j*l4bf;|(7>#dx6p_fS#iq+sFW}f
zTvlwj!V1~#B$bB|2i;&VC<U?8I70A>8uAleA5m$8vUe8FSOO$gSV<`z2umAAeMbw$
zyjLZx1%r6H{<<Pl&4`z|@fC7Q?%_6zXQ{+QMT#QqwtpxoWS{De29nWbE@9;ns`ewD
z4|!95IRR|jM>}1t5Ld<67)vIxV()OhyEIQvyIYObCuF@n(b;oT0=MQx{<#0_Hl#M>
z(q#_px~709D8F%YcodS>9MBH1%Bs}iL{>&Scw{9NcnkMnybzX2ejXmut~Px2mzCT9
zNw41vla>#x*h@#vk<28N&ab9Cviw8Q_4`Qg&)$Te93}#vxih<J#@_Lb2Y(fH{tz&J
zx@T3o{qFd-ZP?0(`tSEXR9&~g#BLP<e}5|<!OkCPxBr!~%C-;eSsJmmm%jahJqx~g
z`|^L#ZWniabVUCf?Y8xycDwF<{dZ5#rLDi=coTNC6NpH$7{C$%*o^>t57BFE_z@j|
zaP(a~*!y1u3(F43dhlvHy`bZl5wCOiI6BH5k%i>_^W#O{ztwj{1AlkxYXAS>{U2=Z
z{hxqZV7>Cuwm*1@hmLz|ZalmXSbb>T^9S4c{TnYU7tAt=dngOOE<nacm+Ov;5Y(ns
zKvM9%77HQ<{!XuIx}STiWVHV>+|8!}E}b^YBoq#m5$Twajw)oi1|qIp2!CTpgoM`!
z@#^xAmqXk{7GP+J(Bl`)-LMirm`Sv?*B|Q&yu>qp+Q*z-azZyzLW)?#Yl;!MDFg5<
zqpM<kEpL2*5v@>m7ykK6cAG*o=Yf$4(Q}3b2+>TVQo>fan6Zc*@T5h6xJa-aAP^86
zK<;K4XjgU04KCyK^AKdFSjEADy%$)@ED74k^2X#QBZmC@)UX{`REE_cHvvM!IxOh#
z@;_%#WtN1tS!&b|w9ri0fsD8nurDAXda9I}n8pV=>`(v16hl~FW>FkHXh(g(sL0*b
z5mk(gn0N-Rir>JP9QYfAF$E~3L+&nY7zVCTcQ%-0N(x}Hcvcr(A;Lu14g+EUzG9jU
zlE26g5K;;I5`m7+nYPS~lR;!GsptpDWf`O<3ACw=&^X>KgnbPV{mU7#<<o+>6Q`+1
z)uG(mY(NJN8CLyi#q(_dW*^9yB{Scul#lx&y7<s5`psnq$uLDLt?+CSjvYtg#I@E8
zSP(wP0tX0C{H|H0f{aL!*=4wK0E`ph?P0UyoI@yJr?pm!dLBl2y>q$j&tK+c+hWUT
zY6a$~8dlSxWA+>xRk;HZ95J7DfB+++cEWBaQDu9DSrIh=e4D3RAw@p0z=15-lvcwv
z#}P9A48q;y%$soD^_vN`s6#F5y82q6Io`QkHf8#>A8b*9u_11q47}_K#L@FkiJot3
ziD@;>&L+EnIS!cz8NlFJL-OoC*izsN7$O6rP(l0Y9|dd*`5GE7Tt7J7Y?$Np^fbI@
z%SH%i+})!XBc3Ln)Ra1tz}X`_$!m-ZvTa%BBJ)3%C@Fk13Hf98vxUN(+3m{J04Gn8
zW6h#z&hW689T&%qBR;JhRA`q?Jd=5y-zL9N%`<xjQ>;O`VBehgood%NE1CbFv-bgS
z<38^^2N0|<shSW&gqh%61@ps@8bP)sfZ80wwhl2IP@qIbGOKFUT-rzsW$Q`YwI%0C
zeeL!s1{lgii?%GSE>*MH4MD0sZP#rq+uO(6r@crteXFEOY-_z&x7YM6$=Ap2(_Ssf
z+jD!jm;1cG0ciP8B+3*-*(5OY`}6+!zTfx#y)({(1-`K`eA||b;l<!2&kY{p=v%58
zeDl;$my8-YubrZ~LFw23?a){Kv$c)nj%F6es@DFqeG9kG*e7j&^l2+x$TUgO?(aRZ
zyEkfl(mL;F-E$dAGQwu%8OL&ungLncGwy0vrn$|^ZMuE&(6er^HylQ%PllssGhS^g
z)!U=~V);?jZ}0Qr^tS!cdF;Z*nz!dHD{PuG`|Y|H-nQ+bdgjFb!9};(yXqU8Zts1)
zvUuXvNENNa-fC9$_Hy=&)%<RB*!;XZcWlNPa6R`&3m?Vq4c*>FACI#^&a63D!ReLb
zxugO0=H)mS;*eGL_6&E=s1@DVOT(uYJY%SbeNIidJS+D0%wz+C)}R<S5kRq7P9m3}
z0d=BcJzmQtaw(T2wYwM5;*s<o{aLVFk^4x(s4M5ne|cio`*@}+ScHM20=8bH5zFKB
zk3z)vK&_s#f=W0Vowum1JWDxd_v@8Z4wsyD7Baa-F*1Q?Or?z6$F0er-qkCD7aXpI
z&E0TM;k1(q<=(}pjyqlCw^Ng0DGWzb$Hq7y(p-_-i|7Q6mE*Ihm@!+P{%t$h=zQym
zMCEbcrw!4|A<JRYaJ-f^!%~JSY*-)L+7*#d8cNkI$Hsr0r3xF9o{4xc!ZF{fL?bC9
zf;;BqLe1pA4PaF&NB<5o^p@?`Q)<?$CtbK@T0S>&$sF9}R6`}ZPu#wR@2=JLiSHPd
z&@lG!*Iz`3pG#6*{9VV7*s1Vr#t-&X@M7KN*B(iCo$c;=gEX5{V_k4Jbj+807gY9Q
zWt2t>Mg`Y&xMCRnugi)jXe4LBf~#C&cRg`}AD~au$Z`O!KAo7J3z}E{=3BJ;u7yOc
zW2rGZm$B~OO)?D2qgMth=N&V1zK^P;9;u{+4Kp@kA){)o79}1z=I4GUvpV{E3R7h?
ztZY<qBMi%ESNQp7{jLbl5fKKfSN)`$i$=qUb}D8#6Ho(Gn^B~7&3cf+FWYY&xth~Y
zI2|fmjYop6YGm(^3~Y3;WxsFaqN6j%8l$NyTnO|vhcZ%Q$sB!!!bCs9K;w|q7ArNC
z*<UfkvAsNJ*~oUy*zyR>L+AaC*0JyM9M%NQfsAg7n0hm-yngEINtIZ&Q;lO;KU%@B
za;e51_{u)}t^YQ|avF=%Jn)p)TDO++8|)`l<UC)ScH>bOO`f0}dE!ewYPs}>vS@l?
zM2*9t>29&@^vU4i+B95YEp^C=x~4*F(~0g>NEZB)UEGz9H?zT(<gsDX`3Sv6q6flL
zrZLMMa3%m6G$_Kgxy?lFjc`9dFv4y(<@Gy=o19VL$tmDaW24(Faf+aZWRe63lna&H
z;2vjA6i6@Ss2VnbJ3DbFM)-Bo8O%L}!g|u2B!^^daz-7=KGof%swWEM@U40nBn+cw
z-1~naYoMqwW$?(<hOziCU8@kwkuEyDH<KQD87>!8W-Y@VNzJ6j7TsCgGe<UT2d8F`
z1~5!&2G;VRl!(4J$8x7K^)ONY$g$xdX*8lkU5(mwBLUW-_9eBOj%}pHJXmPM`0W4s
zA;EQgh185l>viAV8)3|HKAk@->qHP>{KBEGn$c`|fq5oFasPAzzB89lXLbS$EuNu0
zw8&^4w`vX2*;Jb&-7J8=B{`!Wvy&i34;@8zlEzGu^E!-zTf1K=B8ObJdw+BY-F|=v
z9@L}gT$uZ?dFI@<=!{GLHWh6R&eC~5`fixp9oF|^bc}|PJLP!B98C65s$q;doR65r
zvE^zn*V3EL8GGbSRxSvNAr9XUYKKmFkB~)3)S0Mayhc3;yEt=2I{!+ud4{$xL3dYe
z$UQ!Z&_tZ0iMqS?gxy`cYECH=861USzbktp_B&^-8auUn&z9-LxKVq=u~Xj0kd_ku
z8GppRuXf(~c&c_jIGH)u%s3p>N}<p}kV{(Qvo)@V33fwz%kX3iV*>H7cZIcF>hb7}
zYme^ndsAM}JiFTqh8Jr;aH=O}!iQ_k{n6B9txygRowPPjkG{1t8vmSCd(7QxJzIFa
zX1`^HGymg>$!PWY%|YYPn_-Q<UCrn_nXcik&5=LzGnxPGkM7uC8T+lTHuJw-8UBOg
z_naU7<DJoGZhy}D=FV*=8jYC~nPcZkxRM9GFUZ#XbJ6PPb7X$UHr+n$^Aw+p;c55O
zp(mZQ&Q`CyJ{tS8+VQc?Q)6Fun|mAefXAwwIP4b6k=0x*yQD8eGpx-Zio-Sc;*|IL
ziPOKiqIPBs#N(eJYw%XhIcyzzGZP)!WSxDk%Njj+!vB}yv(YoP{lUn&-6Id3I35nt
zJNz}+t`ipgI_=XP6#fYRUv?g@jsEe>!fTtO!@I{$9Dn546VrXs>tP~$JZx+Yo;!^l
zS{)wp>8^HU^yON4G5hSy@yzB&zg~Xj(c?3d(c!a^cZ>(fa$aVCuxH9^?hSt5I<Y?U
zH^H&Y=g+<39<H6;9&IWg9&IjI_1|s;k6E*g!xcF!_P7P2t64KsUk+vh8uUf2@Qr_A
z8F7;mYPOF0Uca<8hiKN{o(*;B^Y9bt-V-&Cn5;bG!V_=hIhXAxv3^GCt!m|ymNYKe
zT8K&FQzd@(>>?FJk;B7S!#~jvV;$}aAFjwLWc{RAp|N?`<kCM!IPbMvF12XMy)3HX
z-NNO{34hC_=4tCchIBRMnjyW^ty3N!lisAgr)W;v7o2pYXM<%vlCn%9F}qdkxwy4!
z>|%J*r+w?mszLwUlLMcsz2$_N?1RxNXz0!7w|gf%h`sQMMe79~d-S@0$JN`v`TeNy
zlokB-Oo~UoPCrr2(b;^9zx&b07JupP;Q9M%Tl}kG=&!pwTX}8l)W8eVE&p?i*{3uA
zc>esBXRIqUvR*Z1z2%2IKGlB<;>v#M`=@^JOLv!_za!e|MpSL5r>xifC(?iN$t|z>
zGp+Q@DGu##AALPMIdY`gI`O?H?hUrrrceFKqviCL*FOGVtum#>kva8GQS@YK_^n#)
z%l!wA^UvoNbyM(qa?43SdpT&Gf8)FVWn-r5ylGLCPVa<ZoB#RWR@;PJ)+BM3Hs!Ul
zBQ)UiPt3?aM?&YMqCtx^QmD+VdUbT|swZb2T1*8~KQn1g?LN2leE0s^=qdY2|IN@J
z{JCgL>ebpqV>3?c==O76Q%LoysdM4h#m~3W-w(H({CQI@o50maQ#_*cVsLlFQU0lC
zqf^R#EVG3I;raAd|I0k1H1VtVHfQ}U|JAaDD4u$ScMSHN^0yp1YB85L_;Ht-mB%nz
z&DQzBtG{vg#*EC-PI$(alOGT1vz<*GI!T>&v^{#oPny+dc+6%QuIY8I^lI(j&A_RH
zrs~fwO6%$GzCH%ub0B(sY}EriI@W2WxBTtcsr->3fi!&MAJ3g<l$$G?YdfOp1B(vL
zz~5S2%qFHzo&Wr8&%aiSXcXOLiG)C!9_DeIn&UeXMKGj1Qt{B~6Q|C9dF5ka^sE23
zRi5=f&!irU8j2@t4m4Z-mz^~8I!V<qW!CLE9ZvJ#8-Af{>~7zKfyKAf4i7Y4>RXGH
zbi=W|;?vaS5tjwKC>!(**`MsGbH=|t{>VvxV|4EG|G_#NJ#w-NVR&ker#Q}R3rn-n
zHtL<(p~3m|^PB<T7}NIP=;DqD>Y4rF;hj*N!!DD5BytZ}<WuMwL??0f%2jhmxB80C
z0BlYp`trRE_68<4a_gs5VF4*QIcbG_X9w<v1)bB2FhRk<fpH=j2-+P~dTjSk-pwOi
zqvIia!%~I+DcZb63fmW9BIO$X;7c>V6%|zLlaDPvV7=nM<gc2IMpuQKqsJEEKda|M
zzSB$mBvj-2$-*(qtI?|Dh4Ya^b^4(cogv3oO+6d#h73%<PL^N?eMS>#6I0k4eUFsN
zVZYu=N5=Nb=*h{#JWb!DlWOz1(USv@T49}eM(%hts|JU=R2C=3^X3|fS(UY0e&OnO
ztKBClIqs@*B!KoQWN8`(#}W-5G2nEWXJ^yh<fWpBeS6Ul*q19jYJ7}><1Jk;*2<(m
z9*wr1XY~FsOs>EEb8`dP#Fo?}51pS0gA<g9J+qh+MTrPXq{MnvHgP!etp}o+=wfh%
z9(k26cK90~rsGF8&4yP`&J+|W{%L4Vsm|}Ap#8L!Fs9rmlx4ga1$Ngbt~`)o=@Cn-
z3jxaBCe(N?I+gCGgF6X`@7)21!zPZlB4v&OS-007T0H58k0B2HxUmK4xfmhhzs-_Y
zouIY&yT5O<;sy0kZ6-BZNlisk7T$mdM?H7@WG)^dF%wYy{4k5nn!^aw7G;NTl<Tas
z-^gCG$_D#gA<Hv`K0j#f=GN3~M>#CbRF^Ue2VFF#aJBs3y||b_$seVjWJ;*-M>zp;
zIY?lqs9@d?W`he4x(dmeC{@Su!j66~l}-Gh;${=yBgGM%@VZ~0`P&f%vr=f3BbvQ)
zWb6#}raPj_wkbMn)B6)iSi6db;tjGpk75tZDYrpkzN?~&SLjKp{;rH`PItLGqIDBk
zwtDhNaFz_n6cyg{>45Gdrh7_#yZjNrEL4!+<?YTUGg+0$9kmWUOKH#9(Uf`qj&P!4
zSR2PE!XvE9rn@pc`|zw0OuanfBq~wXJhzBD8s(e~Xm&J84V}CjwmAEoRq?WZ?G?{S
z`MIJMY2j3NhlZLy5!QmK)SgC=!S=b4&0M!6>&Y{rQIAwI*JuPYSLeW*DFLW^8p17m
z+DGrMeWga^Ak^{<&iU1|Zr9Ak3g2GBgG=Ifv*n&4TA~!ioy6r<3ijDBw-7$p^=g2N
zf5^(DX3mCmlqDHO3(*KCEw$0&U%U7;fdJ%k#qH-jBkwPF*FfOPSi6!#z-PibAXIqM
zI#0y;S>c_(<?F8Ce;{P<btTg=WBk@T`*i$qyTX`%gfM>h(@39vCt<wQ?Bkt}G+l1n
zk*)C~P2bseq{ChR(eszQ_w5+cW{hc6-VZpvpD})^DXH`hkKSgT3qoQ4Dh&8xDVe5x
zTT|ffYxHlEr<y)fi;478&(yB|pQA$=pG}moOup(mnBqTz8HW%!#gj^Na}@%ldc)yu
z@fXER1oE(9L{vVXaR5WP#FmDga*dkT9SQZEsagBOpz~*h<j72>w%huFu*`%A@A;}M
z{Uk69cj<rP{|Nb+d=cj?ed(~udgFiohuqXrp2igJ2_N4*eY9qRDgCc^ZEn!!Vexjg
zXc?Pldfk8K8~y~c7erH;RoUYi=?ggpST?5bu7!IlVRP%MT;FZpF@N0T_$tR<7jJJ+
zxl_!T({7^IwTqTj8gdh7EqB}^b}Kr=rCQxQv8nkSadQw@3}B{Z28F=Bt)AEt*<Ii8
zsCO#c|Hr@k@NU=bjyAc$Osbji;PVrW2i!%=A~YXO<TCD?nOX$(QqFYybS554m|>-2
z>^U1ipiF-^gT@elhty6I^>^>44{eHqt;!^|nAE^Q6~aZn7$#2DA}GsIo>k_+5ju3-
zJIAO@*D|JU`lRKOW^R4U+B*Emmx4!v#2epxnp$$p56sb2ebepLQ<*(Zqq3P>RxSS-
zx3X$axGl0qiK%;UcOl6=MZ?nI(c|?lKdcAp>%^uX&$#EJQM-DM?gj*bVYDMuzDXJp
zUU#Ug3H^{G9JV3UCq0AT^h?B;98K24WU1cQvI*FcxZYFt{lEU9A;0FBJ{<!@kT%t*
z-1XtppxJ1pZH328191JSe*j|7qa>@ltLj1#R1ULDQhw(8L#bJ3ETlv&W!0zL1XPXz
z1@6+P^EPG)R~5m-9mg(DSKO4@|2mvQJyF|Yc1=?ODt|X_nn{L3Zyo)uJurrKI~8P;
zh6yKUAhmq;Cub6hf9pw%PcG4$n#~Y}m!YPNpx!v@c6UvuhK}za>7pvuG*09ukyc6*
zyC{U^Egnx^+ZeGNkJk(usq(XWBN4)5z43$dkB{{-_XSS!Le(3&fia#^XFlu<>*;gO
zngV0T4RRmv8h@@YRSU9CSF>?<ICk3}zx!mR60m5PV{fLEnMuwp`a(JvHtnuoY`BT(
z1np~2R+=<GF`6PIVZ8zMIehdSPkhdVUXWd2XRZ2ebuuQ+LU3EZ8-$4?UIn*VdFB3(
z4Q<Mt{hT$$LJv=RBsAO%l!I>tKF`)wi9#hwDPg!Vtab1A4$<N}G=e69ZkRsqo~h+R
zg7?rL&iIRduzP5-5%Qo^YkE~}Iw<aDcPi#|!?y8cLs*Dxsy=0(b;mO2&Y?zT{hvj{
zd#7`aqhWcRheMjPPTfCcyJr2<&QRC4W|B02uHQ!aBhTopjI+81gsx%O2F-9MSzjSA
z67|G5^(uY}A{DbBrSry6L=CB7?#4-QaAP+aGYA@f!WS!JC$g*D=`_R-*R}8_M#XsJ
z=)Zx4^sQCK<Nhe+f;A|bA!@Dpz{X96&{6eN*#A%zra}WcI3NYkOnC-bt8OQi`}ip{
zsJP*XADul{5BWK7GRA{$2>U}_<A&7?itcD?x?Gz{7<7XTLPkgfXcBoDx8+*(ek!v+
z^~6WHq2c#gQL>)W>L9|CP|zL$<p>y*Zu)9;jif?vDCLKGG6o5@I+9y6a(g2VO?CN0
zr;sd&u^KYZX)rfcr@PP);#POv6+EOjbmLs!8-JaFAZ2EJTE23}dAqSb%c4NEwcjMa
zkRQhex-PeZ3xeov;6YNN9sIw%A*_S5x+4g-8Mo^pE?fVnuVw3OMb39TpSO(AU74E{
zsRehW&~%2=5~&(Zc_Be_dI}1i@eH3^82;mTbng$1jaFkA-fMB(tJG0kHc;ViB4Z4D
z+aUAElOKhHVi|Lh4-1$>Hh%eMSuO@db7bv3Ku}P)$6)B3jpW5cl@h(Jr*hl|W?SB~
zg@JKLYNvClrhP7qjA#lb3hj<)ysH?2aR@36<}=8Bm<Y?Lfl3}Z7rEIm)d-AJKl~fy
zC;pPb-|S0_#PwhAa&>R~^>ebe@{U}B^^L#U7jC97vz;I2Iyb|(@MdNqo7El42E|`>
z{WAlu@Y@e|vD18Vs9ceSzQayo--e~pL^EX!%Wt|Zo3}e2Ki?Sg`M|5NeF-Dzj(?s@
z)+b~?a;czJ@nvvsO+J!4+wi#iMhLljD#)=T=H~M_y3`Par_pVXr<F0J{5e0DRKs0c
zqoE`uo>3v=691C6CZ4m-SCH~lZy0cg=X|=KaObr8IM;v2Z*|!P87Wu)wgp41{HMGW
zpM4`_(1ABaRwVdE89ymMR)Whs?kPi7)XU3u`*qfIh|^#OzR6JXbF|eXTN~S!+=oS;
zBe_71lM(nI5q`9vIr7t-Ec(5FNUKu(SB~I_DC>aT;trI_tmTRig#Qp8LWOqER3L|`
zCNhqG!Ym}~31{ROuF)8#pih1+*W!^rT}Jv7<{%IK)W2pP+lVQ;Yc9$qAMUoU*mgm2
zK4ZdJ=eY(pc$<8@7C9;7H@^H)nW7}}O%|E8U~sZ`IkA2@{CPUwI)==~VFLLOKW1UC
zdo%lnfN+iOwJY`h>o*T|p$+vbzu@d(pd9ctjEu{NWUUR(tQz%H$WqKQy`dm!7*BS7
zZpaQ?|8o(?#~4%e$j-=szs*9{W(xWvBm^SoHQ~06DNIBo+P;bUQ~r<2pNf(BDf`R3
z?M`nkTeNnO0=+J*oxGV}8#}C@vI{Fi<3)Ac14qQaHssSooYv<S*L~U;du5D|jdVVH
zCe3Hb<LJ-g*jUkAO8@ppf0yW%5Jy%+mhKMzTb2$h!hi779f1no{&B4$>)%<?Gam1W
zFtmDUXw)JLJ=CQyQnykBNi0M7#_v2_Pl;u`zBGdm)>B;g`meg&JH9&qgf+Q3UtBdZ
z<gH5oZ!D0%ccGrDlWqvawFuls*Km`L<JD@O?+x=Saw%5LrBnd@7KtWVHAFuEK12SE
z@-RN6++0!yLLtL&*cC;&6A|+>>*Tw^w3y9YN^EUc^zAv`CttZlP5&!<WYk8m=z3_K
z$$0YH5xF<Z#1HvEm*Lg;KM&U_Z;f!KwNTHTK%&c7hz#RQ^oI9KJYHv_@=4|0<4=wp
z^j}s^YI770KQwcWP;xp*KWkO2+QoF^V7isJ%=9|%Ghc0g;F5pt(8$%r@J`QrAS49+
zPtjO8q#hzToaUt9YTNxpdXNgH)9U!}C)9@C<F;}>7v8tu**^Bl``+XV8PFSj1Umga
zcRA7-*po<S|5Fp8@?=;W{>4WPZ;$e5KBP8r&aSHxu!4cfZuQtnw6|ZSj7sjkziNLf
zwMGAm=IDk=TGvn;?^f);d}_EW{vH0PeZ}$iukK&}A!p?1#EWW^zcy95(+|)83`LN^
z`G~spN|!kk94nTrbbs)3=4YLWURU1h-#Ie;O>bj(=OWEJpF0<JzjE%~?;gHVQTGJi
zL}u;C%M+Ux*QSPF@y2Mp!kf>{STmoYl8M;qllf+PuUXFgROh{KHab^66Tbg@&!`F4
z@z$=~;BwVB|LR|&(z_#GkGhW{gnZd{-?-8*ulm*guc=-4^zFK5U#idF=~KGBEkpC~
zY|u&*zm>D|#cZo*FbG<<>z;A^{z=bA7P+1UFrx|o^ik_D&ju>kit4{XtT@klRPGMB
zP=#|)naoa~Cy;KhoX*G<v-5U&aK0$7Jb&lp-38Gzk!^0mJNWj(?|fvs!Yy8jpde-B
zfl`I5O07|S2UX|K*Bpl4&$#8)-?vNdSbf>2_E&C30i?WaCNKc2I@s#T+D)Z+2BoTC
z3CP@Mj%O;>F4EAK8w;#SS^SHPW=?H$#yqZ-s^Gl2sI`?U(f0Kia%oVm$g3wipN~Jl
z_jn4HzNx<Tm1n_{dfDT}2kqXe`mUPlPX6>=P!}eyI?nwQ2X8V1o8{0KEoNKAL2WV^
z6~<s|dMM&~)QN{1ZlT$<>Efc-a*iBu|4!fE;a7a0Ql`=N$GONYjQ!MS2m&~pI{mbJ
z(0$gO=h>uQNjd!oRl~e6am=~1zdAm#&l|tT>FY&kD%&!ntULFztgM|^`Bt8#=VcZe
zvgBLU4!@gcakJ=|%r`S+Wl4YM7%KL%pp;5h7%kCB)z74;+?qwy+(JIzN}F;uzLwTk
zN2y=@e^&-%Kf|g0!8E_K&3yiD)tBsBP<J}+{oaJP&)eBQ>GYXgu9|`%WfATAT-vl;
zxWp3oOv-*$x^K5`|7IqjlytTAa4>VZIcJvLSw@tk&*dI(_@JZpL55b9D{=11;=z<G
zHLXYnB<OMF&02W*mc8-^`FesT3sEq&ztP@}^~%0e-EmAgg~kQ{!o+xgb=Sncl|$o9
zxKa&IXA<>9u2rJPWg%FRoy#+_T*+bI_+ksIoZclEv#e8!LJ3t@c{|@o7A|>DIY_84
z>&3D?o*AZ-qiNRXl*zi;_FURkEN{I%G~%})arg;C+TgqPQMd4v`&3y=`g--MJ#V{?
z<Bl%$Z}#^2yPS&Cr)8gJ^%+XKneZHKFbC)J*}39iz?%)XQZR9Piy>A3KE~(7W)5yv
zu~T#DdL!AL>gU(c4Ge#$KUx98nieWjQd!<3a++k-+6z~=0~@iKO@Hb@GT0GuxOcUC
z1d%zcl*ulvZ7e8PVO#E1j$_--4v}o%7;dHOjHRp!h&LCo%~{3!3MB{piU$uLC5d<z
zSxofqZ%lQ$iV;|Ks!tl@TCZ7rUY6e*2DTkE)LbdYi=v>U2yACd@#p3j|MSOiwc&K*
zDVI?d8cD~_mz2sKbiV3LdOMt|Il}n`=DM1Wv7v3ZimodwHP@3(WDzsoxXBr2y#zi`
z9WdpK2UoV8&nI0(Q80|p@jESPzCV^Aq*AlY-EJgc-IpZapaVIbFt0qfMyv{W^9Un4
zCdT}Zq*xSp?FF^azg2DP-<PWH($b&t<?MH6QwEt0?B=|3N&nbZx!zzVuG{bPm7zrl
zcqcGnM$9ZCRvHYFmRm>s{fd$uMDS5?ZAU0bF$No=*rif-MK-^p(BLaxE%q@;WbNR}
z=YGMUG%B2a%AII5MRV^+uCdv`LSuoa0}PLQ&c38$bYoU4l;k0`ZoM^-YpHCbRV*>A
zLK3SWUsyTnTNraPH)rFBJwM~KOk&r>Ql!S<twE9rceZF2@J_j;s2qCD7aK<<#RGr$
z69K^v^*x9aoRnuCWIX+s)K$ew;Rx(XA1ZPtGlZOH$tU3~<gqfQ*d#7>oo*Zagd4DQ
zNw>O)7*>5h<@-avKUoo@&q<6#Ion)Om>Zb2Wf<fO+hZ~63HI&l1K8|v>V!MpIL7kY
z2JTm_y)e;O=&$Vc`^NpfeV$Bj^d-OTe9H(DhBuGmluM#Asw0=UO8y7^ZV-IASOWx8
znT!WpFqEQBk4cmmQP5}&)a`r{&lX#PoM_@~`m<mA5NI*X$p$spAag<Wm$VEmIPS2Q
z+Uq;EZ&YcAw3-b<>gLSB7Iq-dV2UNyptI?+)Yt<ShOsb+2~R2XQv^nA6aQc`Wh-0@
z?R3e1bxacR2Ua=p#{cs3KsZ)LfHqLu?(<T8z2hT17{uS9P^-r?Tj?Llo2mOj14NC9
zAo#-i&;}Jk7vSe&_!xtMVRIT2JR{A=_!!`r>Li4xSg=y5Oamv_RBV9$I7Bd{b&&Y1
z{jq>zvmMc4`$*#|(l)0C=kn{+8s)BMMb;iuJnZ9YzvEPQ-80mi6tiIs(|nRGr+o&v
zV#Q!nq4RawA2Y>dAdp_+QB4-50rZQIU`hr}gt<fiL1a??i$15{DSAuNw{|e!QiBOr
zhb^9qrMHev!tGNa@Z7&AOhw(NUYEh4PKd7RKc)(o)Ft&4f58yjCk{HhCi={bmt^Mt
z=*7z2m^QXQKaXCRE<;sTjI`8dZ>xHjF+zy4b2iDb`W)SW98`X%kM8kZwsH6+A3mS8
zLhrd+vE-tt>@<IKZE?iABpB-N{3T=$A$bt?Lw72yy~8Tn8`OdtyD(w;c)W@&#<!Xh
zD`%Rs?57&c^N54IY@k~}{@-Pgc#IZrs*^`i6JGzDjw8rsC}nVoDyHpZI)@O=m9iqA
zN@at&Jl<POcr5Nj)_8!=x+^JXXp#P(IZE2{;l_~$P6GgUtyH?p++cr+6$MnLHhaG9
zRQB>DI3H+O)y5pulrNWQVWvujgcxI#jV0gaZ1yk!{uiRDFPwk=3yamiSQOZK_6k)Q
z!ApSFm!fMfZVZIm0=EhF0_kk`E_rxu;O9{4@r*ylE;D-D9h@`yTQc!q4Y>tcEnm5S
zUnjCxfAe2GY03DR1lP|#U2Z&G7Wg@^ZeU%{2HSp6DGvo4_A(hrzP^>LF;E(l1o~?A
zlm=S^g*lVWQi6`#kf!>D89nmz&;P~wE4RzYZ)fCs`1;#bw|uxgaE6ab>`y77Nttui
zf7w6FL()*jvf-8o@nTubo?xoBYT*iS&)2qJe3D~GhpFLcUwPhsw0t;*&WwDuSz52w
zBO)ySK}_?ws*ZRbHsegj++3;P?N}65m@lCnN+8?VxX-F<vApr{9}bQ*PFwATXQyr4
zsG{qPd{%r2_b|rTF94I>$`{a*xpYb409*{d{ME~Ek|Q@~i~s&5G>OGOZJlNp_BLlu
zmt{XW7ASx6X{9D6`k(3NabldbOxdJ^{Kd@XiWsai*@D4&&H>J+vv|NcOv!dnaKp{#
zP}XxO6SU}?A;mc_yx_CN$dA}o{;}jx9d>kuB038i^V|<5LNViQs0*$#%<^|{lP#dY
zBCU&t0{e1fet<Oj;M1imB{RD>-?zXvZ15Ofzv|mHX;*tkdU5*4GqkT{9~0$5L%j1`
z4-ropNT%2bna46_aU{4v`Fu<EoIA1;$cg*7!xZpS+P+kL6KIVo=K9&WfkFVBA4DVs
zqUdcPw<NIQ!f!H-wgzYk-P>Gm9qu8l8@$Lo*QN6nZ(NO0fa;Bm-%~Y{KDKa_-;l7e
zELJ5?bDBAvB9>Zi+?J%p=XalbUR3z}_iulpLI=(lu2X_*mW#l$*+q$fTgV9hLF>N)
zJYpp<M&Ow36<b1<`g{-3g~Ax+c^fl`<%r?qz7pAMzw(1wy$_-eB1~7xZUIHsQ(z;Q
z!SJ|p?l|UbU?O&Pm+ugyQ~DYn$Z&uL0*NiK2knGFUWK8qesx)rL}2qMyDxIY4xr02
zwoBfE)1OJP58Wb3+cMz0L^hFYHs;fXxl%oWnU_dJYl0y3gk`zE_ur!l7X$fo8daFL
zXV_Y~<Xu?bboPR3Tu{f9yU!V)sHSX3Hh{K-=?b4$g0dNQNgg0@2J^|_Z!SLZ&}HTI
z&`EnFeFMqih&f7}8oOBGuz`td!gdO;fN>NTim_;m4mO09zuNjc1}<Y2HK0~yt`u7#
zR-J2q8c&s<nAlE8rPu(+uM&;=^vB+s-kQ!O+#Kaw1Zda?J5kWGvn(6b?5w&hQ8Alz
z-7!+Rgu!A%D;R&)1G&a!6=*hCpHCAUp&YZIq<HjlKYZV{zxxEEN90*(Mqezihd&uW
z?$`C)#jNvULkpKCB*xzCb$h$KZge08Wif{C$}L*T9Gq9gZ@_z7Eq4MKAUy%m+9J0m
zNkEh%@f^OFZbvz>3@mhkcFdT$QVdArkz-YH%)#X!uH=K-_OtpIgJStn@U@or`JQ#c
z{p82hi~a&wbFzCSvJO7tDQd)=651IShJUUn2SQyCfr-Us=M5G1K>3yEY0Pum>9Sw4
zq%PKmkddX|>5l~*hGkTsnV!;Y5xR>11TgTnc<itbxu8}2RVva%T0~W4?Jo!75o0^X
z;ulw|wF~m9RL#t;$;nDJDa(=?C7!qHE#Q`Fwn|ymXyp~$L3`}}4c%7x;bv@Y7{0tp
zE)NtP^->~?j9s%;$AMy2HXr2k^8@9<JjfB;3Gz&8Q^~w|nTXrpuSp^+3_Si$ZDP5j
ztn9$*QfUJVa|g3tr#7qVPPN0S*i}keDq3vxMe@yN6PJR<G6y9(yDaBhKGMAET8E3E
z4l(+SC`tYPq$g7#HH_!2I#@)KIe^YVMp5GWgpvH0<TLn^z<_Nr-7g;dh<sj_Uo4LO
z9OPk9UN|nZv<{F?Q&_=;yGAOG-{&V;=kAOn-h#ia(x61)CGd$joq`C_W^Y+$zuY$a
z>;lr7hFWmfJL?_dMFgK$#bBQWn{i={tBYU=iH>9vjZTy%F?WK!_>Eur7}MY&HWQ&H
zG{|3WoEH41H*2-I#&+&hwlmr&K_!^53&dS1v$`o`5O(2l)S#WrCF<T+9pLY>hTryD
zLb9>}n4UVM$ME=4T!u8F#@4pXFv~of9^{Dzr~~9oz&qa-CN{}%H~eLi!3%g0T@a%`
z{j?Q>Pn-S|`LinTB`bZPH*h&m6)<uK5L8s4$l8>Nq}YVI-9*wr?n@$cof2E`^16qM
zM^H8G*|A+vtSt@crJO*%u$_YZw}G(8sm$kbx>z>qKoi2-B-^GF4aNYq?1!hs<;ucq
z093roEr8xcFz+g@ORp~JNQOwtn^TTIxx;f<qwbffZ3Q+EgC#5?yq*HgS0JMh9oX){
zABj3&H-+~ChX>1VVJ#TDHZ`a+05s_<Z9Vb2JNzMmh;Ud&wu!$2BND#UK}VtnI)9|~
z08?d_@6W8zJHR(>N(V1tx<oL=EEfk$s*m{UnB!KHv<~wLFARLk-9D5LlfXQ~AP`^X
zK`8CmWqDH&?1LKPc)1rhG8G%Dauc3`DFx(a!lTeiiCjySODJ432^A+?0^egb#xI-o
zmi-%lCr&_&ss88Tru-}J{GzbC4vd~VIzEDB=IQ1bx)%v8a4ql@Vuh{jT#uWDZCG%Y
z8M>4;;*4FuAUDc4fg58<Z9sk87lJ<w@|S}+icCclxfj@v<S@M$?ihs5yxjYH6EbX#
z8Fb`jPPg&SI?#k^Cv3<cKiSPQqmhUm{%Anh4bBJVP|>DCAV_EJyq4V8jiRo$<wQC~
za0c01mJ_&n$!iGKCYJ(iKm`z+QFb$(#rPmHM0W}P(*-sx1>^)Df_uL5a}t2HL368k
zm{3QXoq0hHPn$rJ`vf)&_4d-ql)xOp(Gn{>a-mhisF^wNph76uFJJbpR|N8l1CVXb
z&oeCLr6Ai=EE5xWGK18lvuYlyajs`jt#D1ub6aX;@r9|q`m2|ip+HUT#EwYR(hj^>
z95$d~CMVrH`+b`*+#J~@OnI1I%!~$10a<Mg5VYInEP@FS#Nf5k-oycm<-y5kW3!3n
zgzKx99Cn$j3r-elWGh4;h7ohg`dKA+kh<O_te=ozCAfO{pJd@hcBHNPYCJoExajQZ
zQj55EurZ<XjSGHb+^Ov7$10E=slZlk<ykZ*AtGT}^aSu?EI)C?Sch`BspUDKS6?GG
zz4|sXB%TW<S9lk(U4FO2N$7M;EfZg>*<vZznE^=*0#|Fc_@iGF=PPDEHlWRb<(E0E
zlRxQFzq+KwVl#%_n`9mnT)+EddLu`+>ndoOyp=#@Fad?b2HXmE(B?r4Vz$A^4?1zs
z3vjNc>a+*LIEYx4X6;$CG%FdnxUvdXRJ2cGt-rjiC0`qUwxGD0VqRJQmgY>d*Gx$1
zJsxB<4MZx{m3@#>zKmXIJ=b!@<g@hId_se_Tk^V$9>bh22@y5cP_SMM9Q#wvyzCRn
z$p9gJ)S!ac;0%L6PY8dFeCndrOzvQ2g)DoF-Nf(i4TOym<YQj8Tg44_V?nuh;*3fV
zV)r=Jaj)vFM1*`oB9VWrPynmJ#LYs290LJ+TmEnCx2}PF#P!MySgf=LH{!WBdkPax
zOU6uU8?=eGa>O1G)GAR{Xqqt0ZRacKU*2H<$-XBwZzZ@vv_PvDzE=wo7N}Sn5+Z)R
z^A+VA&c2<FEu6qJ8L(B5$OR4IMd#tJdR&u$+It)R+*pk*aI^qW%qUwZ*1&L?Jpia8
zK|rND#7<XmPV;#SwS<5bC6Rr=2*n#AJ}QSIKlNwgyksY0KL8+R@Op#Mf&68{UCBxl
zejV&j?aTP%{kEnZ&Sr?FL4TrMSmzb9HpzgYm;DQnpn4;2h#n4z4g*s_>fD{c79}9-
zu4D_Cfb6sOP$V<eV6!!#kXkG#a`ZNWCh)a`YmMhb4LaCOA{ke^-&W6ErNJwv`RPk)
zLiJC0*ab7Qv%jww1cxJg$*-gc9gQ;NTNymkvJH3a;Ii>&8RC;DY(U_NU<W?E-q{NK
znIs2Hx{@a{kSewVTqKA`RAJ7<3zI@nb4*pM0+?T-gz~o@{Ylm!CQP(1I1)VNf<Vy*
z+yjrUe7dAJK#{n(Z`_;QyN~<<ag5Kw4XFVz8T_nGB-!dA{3Tx{VZiddfeyzQzPtue
zXzW-u)t_R4K<GLEuD~n_E-Ja%q(zi1qn9r|1LQ|g<h9>?1*K*iWgm_N17*l(F2_qK
z(9)W`mZ0^dqsEd@CgV<@<aM<(5N<=V=ndi+T+;l20CENOwxrEBf)ltN&AqWw>;%OR
zc_65t<FgWkktiYnfF+QjCF<JQBS8@SGX9P?mKJtF5FA`19lbPz!oQ_yK_@bYbv@a<
z<U$LLV~%3*UeX{0KAIurV$7O@_I#c<<z!QZ_*~woHSNH~8Ca1Qn!m^Ee@$p}20cUs
zDQQ&Ku<*SdtIu*nMbxi;^O#7xcwAZOR+?toGHix=F%Mp=jFZnX?wy!)CM!;*&(~hX
ztcG}V=G{X^({6GZ?`0ov+cuXsS>Tu@mk>mcRplBJ-ZrNnj(I0p3IUxj`(&ud@4K>-
zIiey~g9K+RB2pDbYV2EoB36c%3>vi+^n`fF1amJjAz721l(;z5=wRvvi)3D_yyOEl
zKz@1XAYv5RkF337xnu)IQj}C1W3iO@Q#Sn#5-cf3E}>#3mA%^^#u8KSpyu+q7O|GL
zkexVPh)r|W{`>Dpd?FeuXze0-W^5Ou!P5?&HZSL4dAtQGcP92CA3S{=AVT6-bd$_t
zX|_kCZmy>g5XC74Qdl0d3^k}Ze$1n+9LB;W%Y=cQ@Id8aWQ^XI$y`YgO%NvuEYJwa
za)5H%N(u;-2<+<D?-M^IJ_-@P!g*Z?!a@0E&xX9fwfvV90j`-L!M3yC-a+NrVrEPr
zl;kxb$I<^no+MU%E*`?NY`l&T(^{{KTF!F|6de(spr67d!O6nF4-1h|G-mVGV31D?
zs-z~gw0*%qqn@U_A^Vd61sOPS6U0p5RuJ<zFnBqCIe*dKo6pAuQzd7!+C0&h8QFD@
z4Phm<0b_Rhq-3s%ux$1i-kq2TGa)?5azKypZKt6F+M7TQzApB4OeIMb8SuZ`GQE=$
zuo$E!F!AJJ4Xh-ouy_iwiEI_W^K-YwQA#IRH#=<AI@DlY+H6;S-Q(S>R3DDY%m~Mf
zGk-v;8w8N7060mRLjsPNSaCUf5J%~HskE(uDRRev<@iJ4!m##|%2}-`w>Swx0vkqV
zFj*%}6we^Qi-{lm=U<FHtq#!z_FoQ;L3VQS;_4E;2<>^P0up|FbbOLra{pxCE+xtO
zY8V{NkRd0NMzjJ?p3qCUEV!nDf+fm^2npuGneqi*1L|XnxybfPF;gM`oNMF*_IA!T
z%bGH5TOe?RX4{It*NT%9ZNT5kYw}l2r;QreMF>N|`|H&3f^+XgckiwVhj_G_+L|5?
z5?lqYN3jyrgfIlk0G7E02rFu=lOXsMl$pY>q2mr9hp&oQA|V9W-T)dKCScx#%4ov|
z$ua9qK({H!N|!er7pxGYX2EOCmqa+lcW%J`<G9wTJaFfr;~Z4p$jZIUpi+S)#|fhQ
z9AZI6%LKe7Op@w<JG*id%&dtL(PSndJCSrH@d4GqITJk(aus1>wpeHc#OjLD84^FN
zWrybxJ7lBG*{h{z#1QF#7lp=wQG|^ZVp3SrVkw_=oQf769`8fMULn(eHp6d)X+-kX
ztO*fDffeqStzV7;0|;>gvA<#X_$cx|^7-wa5-LgTD89e}1mKH-%eGJs^N^kFa);=o
zP(4R}sQhofB{HOqkih-bZdt|_Lp3%Q$RR4b7uyE@ew-pr1b;S7SzgYz2|9U0N9u0|
z@B^JkMmlBDp{A5OcF9Y!<WglNu{4MCbBP@MEG8kJ56H~Hf(l8Z1;)Vb8t%9MHLXoC
zJKA(2_ppP9OLE1|h$*O&lB()rzeqYJ!GpUaZ;!#m)(~Cws9eh|*I}5pOHsgb7W@Eq
zp9o79Mx-Sz47hkea!>52ERn#HF_C#4$F0yMTezd5loK(5j^#w>%<R?6|DQ;V{1JH(
zcu7)}8Q^+La1D}Ufg`^JhxC+l(DD71lm=9Wj_aBl*gLC~n=2NQrL4fd92<TMX*rod
z{GuL5rx7L2CD_eT)J4hA3Sb3$OJLFvVegEbQ{$#lzW-+uvBB4J4#&%|MN!3P;qcHQ
zjN=0i8sv>D3>mbD&?6cT<M?oJ1qL3>vm$%&RLcYON17KTI}|TI-{I>UkZYH`gHDQZ
z3%sX*6@vikZ7GGcE0e4rH-Uxk)HZNxf-2I#|EpC)bj<78)8Lm<$<;?O&Qn<T`vilS
z{?3toJQG}Vv3GMk(yS*5l8bIx*HS4p=J}JJ;MsRnQS-R>LO|YoK-7?p7AuYwlu|il
znv<oHx}EDOW5q2gh-f5Lo3X?LN+`174?j!?#8)Ct?W^V-Bg2f1s}0n)OsG4A<lfd_
z9g)gSN0?|XyP6^n#7G>26k1Ti9Rm!B%7&9tm4$^I<+(6J=dAL~f?KB~v7TTxd?mFY
zGQLXpaczRc2|#%O5&0|zo7>MW5t1S&iF$D5zRxgcdZ$qe?Ygrz{%}05u-d9b_X!Vy
zwkbkGD&PbkQj|f!I#(1LPs28B2X$*Oh#c`fW2vdA(F|6=WwAe7mAe^iEG(T+6*Pf{
zC*{6)3zD}mpJLU?<Ol+cmB=te$t?3z;~%AB@q{&#n2HkhMoHOyS}8Y7On8JX)I^Nz
z#ikH;#|4W3Un#C@&gY@&phtN#e+BKoqr!QkL@2Wgv!fX>R7=nuDGUNgDJicQb@C#1
zK@1eNSCaaTw^NWEG0ykr4GLKwr)@8lU)&=9VCkTl+yekQMq%8(UKC^HB$um<1*bDO
zkX%6a9zK|46yI%Ok7KC&?lR}SO(_9Qs@c5grg<FlPQ(o0N!T)cH&qjfoY4B<A(gYG
zW;Pj{O`I%gkt@ISNA*NVQ6(KB*1K@dfHM}&B^^g7E|I?K<4Tj=$Umlr#`+Ga6!sEZ
z2PIg<V(R6^=9L`e>m7B@C)`)zJC#gVe31^KL^1?V)>)=Rwn=feq@0mjcC%9~S{LAy
z$X@vl)v@$<q+{fxP)5&MFt~31s#&^=QcJY}jz6vlq4pAFJCjn6H%h7myCPCTt`I3H
z4+c#gb1S#|q_Cz#V^nSORE!~>*I}6Jsm-O*6raVmB6F08vuGrA_zr4(*{?h!>=hCQ
zm}}XJ%BZBod$GjjWCm|c{+wYvO!d0dIa7#DSut5M42*k6W1NewQ~e{RzpI}xwL(7R
zXr`Ld$s7qa6h(N{3L3mk6!g8thAugne6|s+U~vjUH!-LblfZNNV|!r~q?i-F!fxdA
zEh?4KoDOM(nF2^$Irmum)WYNL%rTepdc~;Rywn{Qzy!`3&)LD=j*AfYo=gk4r{1}Q
zpD&>F*nKW2#H4I2%DSUQ%`>JhrxcY?%4U2Rx7<?>7Dg&oF}%7A9y6&6uCRa<V-s0X
zeuBn!KoXWeVZ5>Kf}G9`!Y~M?8w%sme*w)~qm2H{oBf10JDl$1B%lSnh`FI61oo3e
z21W78s3-ferthqGHrYj!;t1hkWl7aBr<>@p0)S(=(#Lg~C&mMVo1N=16=WEzkZhX|
z0zeVDU8f8=i1>i}5NgVB)>2NA(Dm3JAsyy}rlY$QF?`A&y_;l(7;A%Qos#sDlx1QH
zJMv+$U`8N(FbXK~(`JuB3#gHEG?}kTJ$}7qBYw2Lna4Pyz^J*T2t-4HH8~7H_TnG@
zq?|`X1=hRWr(_w|tNem|drJEPe~qf_8`(9nSDQ5=O*mblN@neBk`)<jtdPn(X4+_9
zSS~I_>2i;xJLb`u2lpl0ORXOIV=!C_{7cXXJuv?02cOkLqRdu?WWDiA_r`UsUDH^z
zCS}W5jpQ20N4z1}X@i2;=o@!zp}!1<Wa#)do6G|FORSh44wgZNqQ8(vrT@RKJPLO-
zcFf2QixEqR<tN^!n;}DKN`efXiOs82{^F63{uGtrRMrLowc&Ct@sfQ{X?f~DsGh+%
zIeR76%urb1LwoP3AnO`|6iD?$5zMiLgv{K4fpmt&3K2~w;igE+!rBUF1*PI7Mv+LV
zN9if#VgBo?kt`(J1ELU^&IX4+P5tatt;=<#rxOFR9mhtvUnHr^IfFi|sUWlzMg++t
z-r^($oTg$>yjf?^#8%0ndFU_(McsT7^Zcqui3AV|*Q$*a@bV=e*+zJUyO^c+6n+Fr
zN{WY!7Z^hiC~u{I^p&3o=z0+}54igqKnfE2g$b-da_xdz%c6Iiq#k;GPp|-V1(B3^
z+<6=9gkBAZ|K_5+a_>EuvD%#(k6bB^CLWSIk3Qv0cw*?Kvetju--~=9;dA*C5m^ta
zEH-UPBt?x(>(!ADQ{f-hy|M_E-G5ANVC^<wWiZZ@d-pnfIc*@IU}&-;0S7P%e+G1?
zo?RDP6&gsNn5yfIRXxc>O=|94GGl51m)4I}z>;FF!Xl9i^>}cxI6rJ!1Mg;ZWUEfp
zVVOVMgPo!^_O$2$(qKD%s-*faNxDObaD-hdZk(Z%u`NR?+Q$6=>q-<bmq^#>)!>$V
zz2kU>?6a8#G*Ae~c46Cf2_nFR6{GJUrkLd0oXH6eb``h%wuBMp^L6Ei&j4I51}LO8
zeYtU|0rLk>|1`nzy5b!R%2|79;wk5nr=Yt$)58#Ee3FHAbcAxI5=L3fJCj<7BOdY0
z{vxgBsGqEUVR75-+ogn3b0CjWY0a~qUx_HUAk2Xy!rh>Z06mK20o&anL~+heU@JJC
z!%@OAZmnZA>M}&5e(mA`p;bDp5UdI%oN=IVF;D(tgT0q{*Q1KeGj~$B>PdmVU#AF5
zD*q_0hEr+I59FGXA89N&RdPs-Szb3}b~`1L&^HK*L{VaCQF1Bzlrsr9hZKfb&i6o`
z%@e#Qfg*1U0e0uX-;)i|(J%{Mq_q^$Cf6d!xoFex7~A(%P6loE`jS3!igy@#ts>|F
zy(9Inw1{%v0u(f>1M=lYm;?YMNEkOuE~F3$h!P7Q0Y`wvvw;I}+@M&zkj<GFY`;p@
zlMsJm#Oi_AYr^?IJ=ta>+U2TNxfEA~6tkB}j;<@NA^*2dt=IEVRd1()RYzusk9(hy
z)C<hg3OP1nx3~lA)41ea@Nc#JS%PtdG!JZl+}S9aDx3t78jnshI6^=oUKFUAWQ#iX
zUBYuSd+m>O7Cz41iA<I$fRI&9vjOtQPB*Anz2F~HJ0{2ho4W*V8mlvyd0;L!QD~t-
z8)OMDC~@7gN}iFOGCR$nwak;iFotyLIY>;@RV>Xgv@69id4p30%C>C@)^M=0{1Da{
z5X=3IJ0yV762#SXQUEQ2jb4}DU|%VbzczMw_;Cs#fEY=%3R;~Nhp$g&5uP$hQ{=Xg
zjBCzgp}z@}6({Zxop{mnb|X3Vl!M$2n<=rOqBuII0m4O2^6af@g0vK_CLX*<54P-E
zFRx_KVrSxPjM=W|nlIjEt}EW9){%)>yPzKE-=+5LqH3vkmy+unl>PJEIZmH(YK7BJ
zg&;ulbfxoh#(%&PZUt5a0z|eMORBL&97c=eOL$0ob<~x+pxB%n0asFGz@PRE5GF}^
zTz&9l+fwSxZ&9kQM19FQQZ-D~UOrC^2N-tT`w}_3U2N`%$o^<$Q4U7H_JLwa`q+6W
z5Ty!~?{zAkm$3<PePB_ibP~CSn(#=x6JrQArRv{ifD)hy2IM~WAl^VNIYz*N2yXWB
zPO1o&swZ2;Bh5>kiqL%MU8N0q$qZofMS;hXd-wI4KDil*7RFcrz%wB;)%rHjS(H~u
z<)swfO|sXz_KmT#3$kK(q3&lKpo@<;!Gl5#SKy5qCWP*snw4o#(4miz@c&u~3~I(X
zKe3%Cz9U6(@!Om!<XKM^<G<R>o-WBDs0rn7RU0M_D#D#UbEg#X!I!+jBb0>Opnygw
z9|WR@4VhK9K-N7NC*t)Dxds_3W4%6sgc#v^{nQTVKo&b;5a!t{P`ISb76%FJl6epw
z2w2NrwY;_;i)SMTVZ<fQQ_3N(Hw!|r!PNc4Yfd#uw1yelTwxJfoZ*=pz>PI9xl}6e
z@#Nm|>n1KN&X1u7dLQyePJ94dT51R@BuQYZ{)IJyc9=tvIc_TOs;vf$oSUO4*IxKb
zaRYG`1Z>^q=2Nb=OJbUEz;<Gt+Q4BiXFC8o!}*k64<QvF^JGS@AV*SQz9^-^Q6|X@
zEcXPA&R>(E#A6n@7pu?U#u}`UpdA3G7$nNY9n2*KYi1crz{ZUcOR2Uc1y$!-_IG|)
zAApIgIM9e9RncrF+Jz-;rSs{eU10ocgc#@>5kRYJy?T8oVEnUkWQAkP=rJ9eU>e&j
z?~M@zImC7qG;%i}dw_m6U<Snq7*Y--Y?8m3)C}^Y6we8tD?vG$K!^^CKzL;nuCA?!
z?8p+FW+U{m7rCPR04*@rK=NJi@U28IW@;bCNYb}HXB07|CSE{UvqivsBDZ|^8)t`g
zmBoPEC*Kqc;BRsmG^1yM5TDUB?PwXXDpThRGHf<cW>puMBwynG6SKt^Dx@bh3L>w8
zIgqLZsUYUE8z|o(FCQF(z8BQ#C4Fb#N=MelGD$2kX5^k$0)vS%Mem8&nlCpq`L-`$
zwTjeQ%>g|HaUnkvP*;pGDOE-VSRxVyx_Y(5R1_M#WQTGh!?=U*{jz8QQ_y~mB5s;q
zpjZPOqPkk5n6gw-Yt)c)kjT;Z@n*zqvcVh*r=(si@`_mkM$))!v{bC=*uE`F*O}Az
zR70oZb70(vycD}G6!3xreg;L;0flLR_!HJ3p&WcRrKc2cFoTZyA-6<|{!>kPWZ`K`
zXFAw})$X)-czIz&FWVR3xiO?fylW<W`Z`qhC4B}sDn}VG0S)*7B5AYEstieL^}XYM
zpAu-Xoo%^g1#LXJdfY*D#P|S&*aA-9bH<X`+;*XQ5wbufb2wrxK6O+R1%PTFl-#gb
zAVlVH`r-DmFFC$Osvw=`p|lH5p`<v#FoF|H8IsZ)<~QI@%8TZ)J;+dxVZ7=IAGVya
zb22MVe<GzlBL9r3|2Qa!J(YBroIhHWP?FlQhK=c`DFbXJ0YDqW>1C7Dz5V;^M0uqG
z4%yLAB7eA~mmb3an)@_@Nhm$1?i=r?2rKE>9ATg<gwSCG=(Ft6z#!F>xja>%%f+Bp
zC)1&00Lns8otzT%icAtzV|!@QX%LOMgS5OT8HB<}y<T^Nu`}gdB75O$AL(G{Sa1f)
zQUHx479}g6JwO35qfHr;6?>9+E(I-b)=9Pv;7wr5h>$yR%d#9+T#$mH*T8|QHy3Xq
zi81_^=n|#}i6PxDW`sr<c?CwN08uM!n}HFxWuvmi@7(`U**LK|Vl^MMPMMMy>l}Kt
z2ULG@?SiveeaZ93Rb>b|v+6&?vYVPgn={#+a+b*=x1vyzBzhad-O%&O;)~>Sw=6I0
z7V{X^1eLb?5{RK(#mp%F3G7U2h@7pQm%w(m@lPGojq=%BzX5vC8xlJ%E;txF^n9MU
z4w&H>Rd`^*g=`<bPuix~O|C;J&9bt2xT;Q_7_PRhsY1z7B7(1?;0kYB{VFMJLK9ki
zTKK2j64;b>UhWIuzOB93T42chN<9*Sd)a=vblS`}IYdu#fZ`%L4f*>rBOH^3QZrXm
zLxYcl$Tu<ca|23>X_U*zmuKW3EK8xJh6k()L82h-32zh>B8(}+=PYq`Q-)A?78cPh
z;82ismm{EB)@P;mg@EPic0%1)OJhm5FAHV_BIqNs8|?gma+F<7eaY+vc<3_5)fsTI
zgvx|*WV?Fse=AgO!rLq<qZpxGXV>3rAKRrfvYjF&wyl!={%i2&=%^T9eF^_%9~{ge
zlM1dF9u&*2lA4EQ0?2m2{r~e%OW8wv1F$sBPT>jHrS=5bRSObDO;Tao4Vejr)six8
z4nNN+qAai(BE`D9`hfLv45VK8>x}z~oCmWKHx>}vo}w-%C5*CkaA6(G^!Ol%mS9E2
zR)%I9obtQY{1lUu<h3Y_)Hy%OfoX6t6&shyPprw)!^c~>*Y4&ttU(q5mqeO^U2f6t
zk3&mo`U^F@TPmy-&1@BAxiB%}DP8gq3>twENc<|?9=RKv+;6#DSV7YWVScaxZI=qD
zkyUq(d_f;h6PJW)K5gM>Fc-3wK$^SJLnJ=Aw+~t&<E`vYao_}5A$7!AN%G1Z;Un{h
zurIq(BbIfTA;zxdMWVt=f%KC`t8A?A)3ku561+h*nqcn1xgOn*u3f6cVgVJhSKs_A
zjVCphk?`D{p#VgLP%8Vg_GOq#$MNlZRo}SU0l@$%V)^(~u!LpMMT2vPjeN2Wo3^}&
zR?4iTC?V#fxRa2xF)Ja9&fg($*tSf!Lmb7HLi7&i=WT5a+en@U5Q$uH^{&U_0u$im
zX^i@1k#y~kU@$M*Pt(O@?KmKB=g8i^<UYW>w+ny$fN(Axg9kVfDq~hP;V9Oz9Z20o
zO(mKI2cTehY;b&1)xiN3+_aEsF!xe8WR|76(BeCMFtuUraigG=f0lpvl#E+PvSJ_)
zOY|q<G3e2371vQ2mM3R~gQhOY-`T%|Dsp6zI5`lWnQNd*JtbgX77(SV#J(j@r0t`~
zOrFkB0PP0Q6c8XmRHeG8g<TjrJSk*_%`IYqkM$Hb8<ex{PuprL%aH!`v#waj9(@|&
zv`J~tT6na^g~{=eA&&q`Q3xW*JPZs4VRQLe;%@AWvD{M#2Q+jP@<6Y<%^?i2h8^6_
ze^xd_=BHDD6j4l_S!~%vPW4zxIm7}LUcWZ=gsgj~q>a#Hp^UETt>pNDeGM%wATU5)
z<yUAH*2_&Qe(xfw5q49WisYL%Wf8hMhMKmvz}z_W)3K8-X%inPRtB>E7-!H(`-75@
zMmfC5IVJ1}qsI(Ld?_AV)8p~7OIS{h=ZpU+jy0YDBez?S-+&(${%MmVu=)`4dbN&B
z@5IE!-oEkvzLZUfPdaaFnmYix^Kw2L3k*==W<-g2;pJ7>avV(}HSVT29T1uGhyVoy
zgJ6Jt(h*9cyhM4{#D`~-9JF9AU=o=F*p+0NS^nvJWDj&@v&^LT1hOobltV<+6`C6q
zPxe;e12r}=flks-ZiF?Go@OHOHW)9<aUwELKn3<%mt=@I$m@nUEItN;;17xhNaLCz
zoK!z$7y=I<Owj;GQU&6}6?`LPEKEKSo>|1(AZZBMhwoRBf1yCM7GEpt(?q~Yy*4&9
zsq$UlhC%M{8~21_p~*Nn(ykL0z_Ax}(3c!qvX?g<xvtHYTMBn0%m<rCl1)%BETF6p
z1thZm28=ciB~9YJ3Bv%zqDQXdeGXrK_Cs7l%RD2OP*&{D)26WZ*#%`2t)9db=Mnvp
z6x@9k7t%}CThf0GTSSw{fG|PB-?z`-+}L7j78YBHpAw5nfRh|sa5Up2)Q6Nezgm&>
z4C~WO%oag5?Xo<P8W`l@>V5yylX0}IBfr!9H<k8cFEx#~j??#jB}9fK`+dpk&dD7k
zRSqE=6-&ZC;@v?Kl}HR{<mF(n-uC4IN&>%5Rk@6wkhG!HB~Ml!P7ZcdeC(J67yu8_
zuLaed*DNe16a8&Z1Di><?dm`OGx4)>6k#d!lYSrUDsdku;eZKcvkubc<q4X9?elkf
z6<hY#sR-28MIpt(6=rUQE0HUDyBuVuVWk{#ZY%8yK-V#+I_aUbF@Y>S*DB&wgs>sU
zNe&QD4CjFbip5?>KsfvIw>f}+k-6$!U=oAv^9~}Ix}?@#%g1m>D%FQba)6rg`+oL7
zCX^M*HL05bq_Qah*gXK_Wlo|EFOeQ}jGNh5t_5e*oAh+(G=!XHQoSL>Up<&JX9p-O
zvS}?Qd(ch+p{`<o+#|pBVaBR=K>vIBZ5O~HQj|b<EV)C9)*XKz3Xr653{IuO!3P?A
zQLtCYlPW-p;J>7KQb&bvVtJ&fSq87iFX6Wuru^Q6J0PTjyLo^@4#r39pyX&0Jbp=#
zEIU95r!^Q4B>C;~hM!8JzZ$H`cQA5uMzlchfi37^2sA~WqhICCafb=eNCVp(ROlce
z=XVmAHB{Lku9EcUvV^FUNWlejpQ4-x#%{93q5&xpCE_ZbM&Zyp^!)(12L@0YIS`e$
zCxC~eDzW^<U;L;BJpf}+{>5OR+&P0!bcI<yBLNEhN7AMl-*~@+YoY6y^jAo@GIGFR
zi`H1=(XPun-`x017A_vXtQ6Hmdpw-HSWx~D0;Nemvjf&_$(-e63se)Egc`^8li$ES
zaTMgwC5IxzX6<GDn*l0}cCoQNFlX3XyRN)me`KXW>STwoHkyGT^*p!&4vXFNmu%0C
z&3;*q<PZlT4f^VNs@$j{5#5FC1BC+!_f~uj2XQC_%gKU7ZesJ_UUN~r?6p7kW7{Ju
zkMAY>EQk{vARD^Zrri^sR4IQSDW4sVLn)6BWDu*sds*_NRC7|;rMqS<;rts3eLQ;B
z2J<G;nb#$a6v%n#6E!d*Jmh1j{*{~q){~wG5?2XbA3IxWa)N8W___?d4Hzy4_H!J3
zmDRqS7h&0uAE)?)f$!_}dNbpbd&Me4Wvv#jyS^efPq#Cw_>d|<zNX8T6N=-{wXle(
z(ZWI=#0wkLR{+=uPTtJOQ5*)Ya{*;lMmi*z0D88?g@92&g#DeLm$Oi@o{HgIE%`|K
zi6nY7V7n7th3&z0^<^;leifU;(saW;VR11u^CkFD>Cu?Y&ns6$hGnTNR7mGoqz0WV
zt6x1yNUq_UWCV;#HZEJyRk~cfPCh0{T~xgMf)9W!-}!F|s*-8_>+--aFcAysP&(O=
z^5%nTrE6DBe?(VBi7(_4>nsL71{2W06_S)RXyZ5OQ7=QGt~72Anzo&I+?qb>PB*zJ
zEiHRUImy{*%91pUL-^!aYwv3n4T>T5I1mcpLz7rw1saQoNT)|TVI8TivchnR*2IZ^
zsvR4It83H)ioqR|?!Oe0DP!NR5vOlNf=fwJ5Qf0$&)a4REGCV{a3@lZ6dDxOb$USW
zZG>!ROZHTjMu;3V4|B)*NpWXAQIUL1umT!}>4I5=Noo^Gz!nKPwtwMchCEtj8mbA&
zUYp!t6Bscpl}~bl%#-d?TGuS(iB1R9BTFv8l|TR<MkofVA+IlRKEf8wV_Cr(N;^TC
z88PY<;h}Ea#n$B#r5xQojHQ@U+pgTjAASTl6(j;8ukNI+@(sZMoDv)}l*F3k5;S&m
zVa6czup|_MzF&{#W&?YU^@o-(Iir-0vtcO!F8G-iaXDh&dXiAZZfh`{6iea$X!EL}
zE*9d`r)2X;d*lxg3M7GRd%RzEjJ}b~xDw69g^VWPf!J>wOJ9_#aDm_0;CI(7U#68Q
zd@}MF@NP<|Aj*&%mJ9WfGeUH;35dlp;InyJ4oPj7>YxD(4rPc}{^m<{dWutG_e$i|
zqDJyXcJfXT*ap2tcY*=>c6s_W0*n`5C#S!l`H-RP3LUp_f(L&n#XyY)4Fw5=-ch}5
zMVA^Pv5KM&{7HWZdo5@B7-prLI(gk#1}&fGxRg$84mL@&%dFej5wEXFJ$%iVd6dyZ
z^lO$suS6I4Q?lxa69xVDH4~ZdlVg2fbL3=b{Q5C1&~35l+OYAx1ZiA?27Gt-<|xS-
z1;!<ZaN-C_SUkT1K_I=`+aISAs-!`Uc2GBLe*U#zlX}mG155xFG4!3M77j`1qgX}G
z;mV&46X3yp%j)0`GtCPJru79KH7O!{N2k?Sg9-XP8{9%43&HwTs5_8#XCl&@T)MgG
zWw?b&ocl_<7MeOX%2pq4G%+}O1~L!ARti6Ux&PjY_6~3+Q5&>vteC!Ie7_Q+gA3@9
z2}rjz^?prQlhip<x5Jr~B=$v#{prVLri2Sd&^a)B-4&O;4X39+8eG@=pItz3W!!Qs
zgn#w7H4~e?W%QwMieDihl~t4@a=a95JA?EC9zV}<7&o19aUoP4N+MFCI+uhW<EQ2T
ze*gpa0R-tE?&|D8{QQFHWL=bCjm;cT0@nQHd&WCD@cuhM1TWAh_V2`W*t3pLk&5da
zN&%K44})bvwZU8%d}K##)HdXwV=}P<Abx_)^h=io#>*gvn=h2N{k~TEvp@Z@cP{*4
z%=bG)X9H1RM|1Dl_x=MHET+*QcSQK9QxJQ+WNdRJ1C+QSaW{P5szlh4co2nt<if41
z?Vta7XSH964pPyMH(SFp-^pM3Bl6O}&AF+}gG%Go7Q&kP<T?Xi8n)!El+46n(3?GJ
z&LJ3x0DkB=nsb^4Ah){Q_g_qQmV4?UJ#3NfgX+TDLavr4<}9+vc@J_9g+Y<EV#Q<p
zAzO^>i0z*vSH}c|#rDV@w7s!dOC;cy?aam9oN0(35}`*gNtqp@qw(ubR{Z{no5?sf
zL5qr(b9)6V-asrDm%3z&)6z<d5Q&%*(mA*=puYs|@|*$2ed{Z~=7l9YuMa9=Ba>2;
zBB~j`CS>$Cd&)(A-b7GXJoyd}&AKzf;rBV>!V^rGNFH`py1D`+H+v#LXsnzr#nyxv
z%C{c?vV4`j|A(pTcHu484RT55AfAeUn9p)-J-r47ur-7%-~`HQmAl<L25Bmk<5K&7
zfOp9(@x&UEev%gDv0X8o6O7Q=0<ka4b+%t9zOA(v#8Y8ySi&U@kgX7`aP#M-%;zzc
z+S;%Wa%k6h9}{l}DoLoA1dpH|1Qy!B%MR$Luds{ybqf<%_vt6&82d=Od-mOtRA3OZ
z4pMHpfm-j9-iH|S+<Y2#Q>ar>1>}jMDydhG$s7NM_3G{3;4=5306p}CGd$7~ph5sH
zQ3|B%>h?K@TiBs%e>l7}LCxamHWP9jRXY=zAhmP{OgVAP9}SG!sP4!41~~#Ez^*8P
zy}bhdT#8#_Ww>#PX`3UAHwltc;!#zhJ&*WmDdc#O{)Zm`^Ibdi2k)MwZqvaeg%V(r
zY$cNvWx|zAP|kAC&Fli1DN!f9pUjd9MY3PZYhvE1YY<`P?yxdR_Hw;5Oo|P2k&(zw
zTA9mKJ36;)V^RF|Q}3Q?Cts3gKQ`pA$$mb_RQqH*Wu`Z=-#kC6Jy6jeieH8#tG%3x
z^SDbg)5PR(bF>Z@HK(eRp28eTd?ID49|*-?JKKEkG=+<gGoo5(`L-snt-Uzddnay&
zhB4gYUWFxMM{T8aY4q}VRcT2q`<aCi0)&F%W(ft6TZu^F4QYt*0U+kJ-|h5W&_uER
zrn$I|a_Y?_<`NXNL2u{P{+pqGs6`ExJ7G&w3UZdGpKbbEKB?CzkBwCYSY5od2rc>e
zCGEseEf<p(x3AWPuy0TD2z61NDm@6Qx2LJ&GkF})O>B_#DHP2V{ld<=b@p<3y;r0U
zf)KQAN#Ma&?ofD%gHhs5C};AS;s*eN#V?-viJ0?jTUpr8_8gHL5{|K*m7Za;mCN&q
z1ZCQf=!w#80@sR5SY9rm)6`QYDs$COPr2kZX!d|^4oPfBtS`|i3n<2Xxjz5ew*URz
zs!8TKE?Z3FG)tOrY)47UgTCT48HLCkn`!6@GQ>?@H_iA-Vm)S;HSFO8r=zWpxXc(8
z>-pV^xc=yCI&pBlxVF1zh-a6L6tB64>ItX>iA%^Y_4ju~_Q#PSEpt$22}ncu$X7I^
zaw(2LZZgf7CYH}~|Jcr|S3U1#A3g=OBrhvrmuTj#Z|2kc-@BRZ{_6uB1k^FJ;Ly$_
ze;hWTbEyoGv5IQq5Tt?i5{-Z3-MkjJgwfsv{3IX{ftUW*FcK+(1<3r2VC*HNdJ7il
zFW#e_2e3d8*D_SRrUnQlL3wyi!K*hjK;-6RBV(bp<;e8XG;frxz$}OtLnjAfx#Vbt
za-VcM<y1^k%7{M*(wq2y-o2HiMzmhCB{D&c_3|2#FNeG+mO6->MY8AR2+Fc+49Vk3
z{zMxdnWw_r((b_+l4zvrQwR7#W?1~&ch68P4>uAEaLtS@&xZWl^paN0o8bZ}zK{!O
z-I9YrF4=)LoLxrZOxLgp9tO~^pyB6nN0*u-uLeyNmUNO^EZbkc@KxOa`n?8-i;(0I
zgr^OVCSt{vym?de!!cj>K}(&$S$!t81AT6ymO4o_Kwyb|MyX528OL=21gUCD;A{$U
zZQGq&nd654;XQMVdqQc<KCr>QD$@k}EYXF_fCa+0NnFBipx0p8GaC84H#T|Caff1j
zdJ+SRs0%zy4*4fle~Jl8hiYlCAu_A4dn?mCvhbmI!vZlpQgzC5w!^P0B@GF%JsQY%
zjO>r`By6QtEH1z#^W+<rEwAk}Fsu-62&Ja3i3)KOL=bZr-7otWg+RXLX>R|A_v~id
zzG4KZsnzyX16eJz{{a1d69bF$C=JHwhmlH47WjZA7<*&AY#Z6Oz%m)BnE|m&QW#e$
zoQEzFzIAtb`pA<Vx?m}qZdcu7Ki)>Nge9Hu>!yLGWJ$yV;Sg}2s<Hf&YVo5|*h=)0
zmjqxCo{BTGI)y^6?gN6^`=5OeV2=?HBZU}QGC(>iS!P@!kUiE*u_BuB?gs%auV@`?
zfF~1psO^xZN2&jjQ|tge(s697<XV=(ljY;tr+<wj!;<&E4!9E|#CLnAv4xX^5xuG8
z0u4knv9_Y0Ji$z2lVt_eOOG%Sd=PIaWePk85E@A8g9xarNbU#G(9h=I7t~5X-3GPS
z`IK>})0<N5#rPz%pwgHjVV=vY57vx@Hi1Gy@!=KZ<vB|w<?uvcI`<9T^#KxR*UtXy
zcPr@I!AZ8m=xwky*@d~S;yG`Q58~aF@3c>#nrWGivyEp(=tUHyynrxMJ0nOvU6MtX
z2P1UrEYSUboqD&>Uf1AH6jYeYHWU(6yA0^w<_$!0CF27S(uFL`5nKV98t?H*QBr!)
zbExAIxpFXqu40f_?1M2uTmSTZc2vsT+61O{Ef1F3xm`fQ(tiH9M{`3pYt__)wS$J@
zIF`4xsW(FJ<=BCW$fKS(Q0gc2Nq=?~Y@6bM8%$7VJ8vbZj!wLLmhAvuECJYd3GxBo
z$0xRX%b@iH)=ET;{9!L|Wjlq~6OM$>>1eK`b0V9)VU+~d%0XO8$t62^>kjm<-;dXe
zkF6m$ZJOko;319Tm&cRPZ%d4ryf7v$)C^O!gyEM#Ar$eSe0GqvO2(lzC%J&O(sYGq
z(ti+p`|W~$l)`)6iq@}pY^YGuBx7!#t7_S?XVLQ%4uQ64F->warbG^w>Vh`zE{;Xg
z=(HSOaL`Wa7!JWlOeUHyujM<>YiEDuJ#yQ5fFug?HXstpYq>cT68Qp#a7;2Bup5wQ
znaEEoD7_|7ZFE%ITv2bj(8xNG==HnB4t)^G{hi?5GX*o~BjqA_?U`!gU0_1>=BXmV
z@mlO;&GQL4rLxSZQ#z2x=1=Bm=aVjd`<?%vy7v!{>pJf{?;VbuD~Gmct|oYnCJ23J
zIA$&(Ss_5xov_|`?%+bapumunl>~L28l<^?U^R(FIc?c&`{<rK2jCfCz+a)&v7%jr
zH0_R6XG6(Kmd$3@7zwIChpr??Y4~ijwJ5tSlTFv8<hDvTUGL}I0YFNWM2Ow}V+Y^>
z9L(H%e!S=X@qNGVIc0W8LE8p3a=|wvvA?zH%^mEiJMNTrFm?M(62&C-{^gAm3#8)d
zn3+QsRz5w&U~Ld>Z+mPcz${Di(X<Y3R~=nT4^3g{OX1D2QeOM{?br1YUDxAEuE1TG
z&0ZggQr560$y*u~+jC@0{+MWNZBA{E^j}R^oEfK$6oZ(6Y?N(bQ*p(s-JNRMn~1Of
z%NMWfX)3O!YBj~9hcGDzFq>vJ*Ww)@tY$Wizn1brdSS|1VA|#41{2Jsqr}I_6unaK
z?eIe#h1oKk-9&E=6ngdcx9O;n9TQ>qI@(h|Yqck-o@J!W+?3)>in_0*tG(DBqiOsD
z45(p^r4Z&sov;%<TSLv>#B3h<`_~0zpu$ECEcfzi3MI9iCQkX)8$r@o5YxuqH=$>e
zL2y^xy>|wMR{EKWehQZuu@AP_aSaTugIXJSK<V%?g73nf9An#pl=Hr7I8#4}Fy%Tw
z2>5+1y-brR#+sP9WJd*%08?bXCRMwf;Y^hn!e9byD3<AgG-z9<)AZH2LO0>U55HwR
zM%ZbT-fE<>3TB$D^=c;f?L1pkvu3n4JvEb(U^rJY4DXDX7$jjCM>VF`Z1`g~>tR`@
zM$?cFZelXO^;6eRX1YBMeKbxjn)YgxVlrbX{I%-8zcn>2Z}`~^QEznu)b;k^UY^f)
zcJ|WTpV5Ckd0>x4*x<ll;3e?!41jPG6ZtzIx(?z?*JdxdaE%X?LSJdRXifA3Ge*l^
zjNOYeR`&pU=U%4ZyIC*j>TPLuls@9-F_*Bg0flZV<UI1R^kmxAb&2=W>*k6IT2{0x
zf!La`cS9vX|DZ21f9uSSYin~6diuu*WjdQ!&a_OCJx2I4o?dE9mPK~$!26NPbx!+o
zAI)H1gJT+_iFn@F$=mqlA+r{HEAq>|JkeSV30OF8NpA)jAZps6&EfZy*=QyQND@Hg
zzZq8RYhV1{o7W@&$?}Oj^zaS2_z(36BsWGd(=-^OW~KxE>ZcCST2^GQM4$0t8VBiS
zO7DH8j>~Qcr6x3C!xF=+c-N8UH~#QC{c1qOm1NO!ntBBZS`$+S<6%5Kv!+a6GcnQE
z+B`k8K_CG&vflgbkY#N$*rgFyD9UWRa}_mMyR?4uyVon8w2REcYMN;1Y8RpX-iY(g
z>3!*k(?w|xP-ZQyWgdIXF5?>BW|lG~!I>0m#~UzHXdS&dnCrQJ{$^oa4)Bbq-JEZi
zE=XpPDeU<zsn4^5=)EKO(_1G!Pa@S<DM^o17+4;GWfq9*-kaid?fU$6YG+x&u`E`!
z&H=+6fdsTxxZR-8e4P0}e~><*qHB#+n7u?idAMcmYLJH1VP7UPLajG`fhogZ_3_p&
zwLkN)lh%0&KP~ezV2%3_O5+YT%HNkHl#&MfLpIUCvtpC{Jg0$`YzXdD6q%~V_~}Z>
zAr^10@p^*Y?Af~06nVi0vMdgQ;^T(6L`&UW!CLCOe(+l#SgG$)X8Y$S0W6Y-fNVLI
zA&bJd-dx<p4jZOq4o8b3D9WSWSl9KvWM5)-#FiNka?(>35{g-NlA**mxM4ll*7c^G
zizd)5)M>Av>mjO!e!5)RU9PaJbG=^Au=R@K&;;tKOq9{9jL4_OTofaljS_0kz4@9B
zoYuN2%|3G{-7;nA47F#F22-HN>SlEs+2!5roae0@V)HBux5#kj&7M|fr-dK<+>h}e
z**H#Fo>j`x3=_R&-cZrSChX?y`7)a_Fm~kua!}boq2G9PIYFdpH`qM7TqeJj0qifo
zQa9)@i8v!lRIu(3s3&{tqORZhPw(p$bvbl$h{Gsc8t~HwVE)cMoB{Esnl7`4Lh%%}
z@wVA`J*`>DWxKN59nCv0vm4q0u_QQ+o6R+lX|iQ#sxy@*E0kYjR84+`+AAv6P2CpZ
zIAuL0O5!tk{S+*wgTl5=lzaWokKQjR=t`@)B2!9gX6Hj@f;O5+lRQZI?Mu4YHqR(9
zH&vAkwHYKHXc5DPuVr)W75+3;k_nqJb94diEC*wZmhn@KM6(>m%vq&m4k<6(ijLr$
zJz)3%k96)3O}Sjsb=O~Bt>>a9DuF0ZCc?Dx)zuWitEiT>VUR3zV;qc6f_flMu+jt4
zuRW|HK2>T_slX1;W)^r1Qw(c}N;E#q#;Zih{MsoI`7eDbBh}PF!MQcBo4m?0)x1O<
z{X^(P(|+@`#+Z<kyiyZxo(EAImUmrQ*M!_OuA!Nm*|usG=79P~l2c}r@0)N(4*d7G
z(0*EPYKeG~R<F*&OoRDa3q{_vI`xzodAQ|ej{}N(rGQsYyO`&c5K7U^p;H@4Rqd>#
zj2i@}K+)_?QN*r%u(QJP?@3Qe@%O1s=q1t2GeON77`S<u#wq%2WM`voj-7d{DlW?u
zais?oqr`hh>KM-A?y$$EdDouc#aHZ=p<ga?K_m?kJmn~wUhG=~O&VG)QlG9{{02MD
zELY&-!CBsuKE*neF(zEu>=XlVS0j~as#bgTbLnb%H}d}QpI@yBp(5l6=e1yhPa);2
z;%<u3($bKXg!J3+MN&|}cxGnRnyr{tPgzYBntAfdLzQ82%nUb;4h!Z$g?De-^S|?Z
zt3`iTM>-9a%)(sj;-qZU2zWZw#+YAIcgC2<4D=}mxmLkDO`S`W;@DNZ`(1!dPwZbE
z<GHIUB|S{Y6rP!{6@Tl-={916t;VG!P-Jn=mucwg@b-o{Q`=uh#Y44$ok2FAF#IOQ
z_;df)`W0z5#jR6qQ^K1r##9Fy{^HtTlr)%GiMtGQ#LH0be$7E1hy^w;&eT*rWtg%8
z@fVJ!$%S{l2(SF{*fr%^rl|Nh+a3)W;aE{4Yg8h=AZ%4Ukd7@C%aWW}rRId&>Y6=M
z`X;e*oDO6*iD%c76P47>A#-q(%)={Bf99$VOlyj<vu6GE2*5qtvql4&GVyTC(FR5#
z_~jThGI&#=7Aukss7hsaxg_bay^fa#-Ux&fEZn3P?{b1sYJR9FzE4jHz0!f6pc^#f
zh6UXl)8ZzajX|?M(MK6Gr0BVbg~XQ|NY_ni>O<Su_|jvU!Z=UCR`WK9048;lGR)q+
z0ByXA48N$&*B>E7U~C2>SwZ=ijp;Ha@<u=+l4N|Co-;$O7U6t~u+h{{>ZwnjfA*7$
zBY(PxYT4CIxk0_#?$JkjC8l_9EOl~INy7PzWTmp{EZt-p<MWT5xeoYV-m!YyDlW5<
zef!1m#^o-i^cY>lY#E}TMb}up>GwOLhdtn_=ibpj19@8}QOqZCk$Ytz3pWQn{nqbZ
z-^GU6tsJwu3VEkw^VB-Sa=3A|3+;2w1e%l!)~#f$?<!3C&X{+P<-i(bF(L#cKsZm6
zZkE|-!uZ*RR90_>%yHj`-`r7Qm|eXj22|`f;NC0##~M&JV_nio9W+Vt`dW9yz6zEi
z?x`?%bu*E45fU#!<jvvUKeO{XKzKDRw3-mVDzPhG%G;F=7zfK}L}tUZG2Ik)Z4wK&
zAuZWNT#dx`_COg?#-A|~%a<WH+)U2@pFDBhME2^lQcn=JN-wv#8hxxKABB6f96!-q
zlqFc_8bR-stU@|My;Z&G`*pwt6I-QQv!rygo9XDkW^2|rrQLdY@wZ-?Yam(mLM)nU
zR0*a4<+^<(8TC#m+ck{-RKK$CsUMDl`k3usD2^CWH_1@$UN5cJ&^(#QH|C<&Xw6H#
z(j`<7vpGcBF6Az3huKo*ff0JMFkMqbLXsHZ+rXwh-qE|Zldlc`hc{1Us(jv7%ig%y
zu9tB$O{9-3&D0}V)6!hl2dUaIeWa}W1*(?Ju1l6d5L0?`>g}U{*It44*v9L+xV$WJ
z2Cm6rTrC|~LpGd(UnA^B!xEjQhGeCWH?SkiG@!JXJ^ji=nv!O-<0N?uGBwM6WTw|#
z1oH47U&l-CQ9NnjHPtSqW%qeaG3?Mayar-e*5pbT-_a-Nv9DJI06C{bkDcMnKk^qh
zM;v>l{^mJcB|I`%CM^sf8AG|ETbI}4Y6|?VlfwW~%aP-tktm=>{GPSuXjUpx@tRDC
zZ~6zQZ}3sG!Nbk%Yx3GpU+)WCH6g2xt6^2GI0855B80eW4T#|*uQ6v@UEZl}Sr`o+
z83@S)6_&vs)6-C|2GVPn)c@nrH&11nQZxi_1b>;+X|@<xo=fT_Zx~OTUal-CR3ngb
zN=61qG&1{+(rP@|l#FatGExAbox+bKhpCkWV7-}rbq4>=n&vUBAT)R$+_4)H=*f1P
znOyEB$I11!7+yA$@7Tv)D${%tw-=wskax^3*Tf(u3c>B^ZHTery{>&Spa0mc@4zfK
z^;mDQE^kOR>N!2jhK}PcO<mSosGjS}ve-d2-3ywY-saL<GnZse%^@@(C=0+;H&Z0=
z{hxSifqfH`VFjCA3)j(T)}Fj!A(x|&)rjkz{T;)+VPpnVF90+;PRQ{yIG9M25ikMs
zDrEjHjN}hKd3`5)Bp-z4O%(zx%pPd8;-tSFlqgN4l;38)*&>Sk=bD+hJt~!%#}#h}
z>;QKTUngCi;G`?U`fgl-fAa8K^)d|yOh}nVTFW6NSl*h9WD4|}*~AZkUPNKa8Wrs7
zqBLWa3TurGDa$x>MqGEBqYQ3l$B$iiId5K(y*nW>Ti+N>{&dPpxgm~2mOuThnM@?A
zjDB481m0OzO+E2dmE~HdrjCtK2tbUl!&Nv|b{FEhGL>uBI}d;6Ei1HpT<$l}tJj(?
zLFbtM^@4kFv`r=gS&MS*9p`9P^R}K_Z}~A>v!&Pv!6d!_loSl*yZ6oSo_@2m!e>}U
zK(?-s{)j}(dQ74IH4t+_v1sbnp86RgHM>^MpNX`3%;!~cC2}d7ys$YN1Ao9|jIJ)r
zwa?|}{?8A*t;F_RR}*WQ&0F3D(37HdMs5euJwsM)?Pss76!S5g%d3(chY?vbnHGNC
zyNBTi|LL#4c_vYC%Y59Fvf)CnUakg6_Y=4w^X4S>4V{x35#xNW%IZ5uAJ-6KjLu2@
z)?U_(#FRyjVOdJ^?;`a0$N%v9&RxS1yQZ4Am(;m2a$IVpL=>VcR@E}EXj$jHv%*;+
z=l4X^5H`tEkxx!ZeiS^IBg<|^L?8b0bp>>9Wcpo08&A`0E0*zX;VZTg=qXh*gRDd2
zhAn@;qbqkkI!E>pn@HS|ZXue6Y&|D&?JMx%U%QS`v_jTQL*(8zQE7F3&n;hT@}CTD
zs#HybN|xFB>n1x%OhxvNATm8RuQ$D^H5xKPV!m+{41K=$-6LOIGZwFvt|J#;B{E*a
z4O^k3uA!h6f7~p;-gkZ|&X~w*g%AI3#1t<TCP(^UFHZ_~Z^j^gcl0eC@f8B&a)4}h
zp~32}&9mu==!!+;TpV+*-&#Vdw~<lA6i$aVc5@Eu^y}AanPnA<I9$s_O^MTMVMv%T
zgVkrOKHo`74PVuxYg~nVGzGZ~Ee8*kK5`<=&BYmC`S0GMhdrBnHQ(_w8&?n<L~Ug|
z*|#P5r@8TE31#c5w~3?rpT|GxfBu@1_TH&)JvEZ{kCK~|cVx;KAQP?rW$ilVfBr{r
z?p<n&dYi#tWi75mQ8#vF;Md}E_q1rLLXFGzuGC99_o)puGiNwQMupxa0Qb%5x30PA
zZTNB(*T6iOioZ2xtA>nt^}ez4Yp$@q8a}07j0yM?1K*LVG7LH%=_*{A$hFVn2k*Py
z5cWvKMhP$Hs;)`Ot%2vm#sEcA>BTp5VK$MYxOy!N+tp4kj}QmHK3xGTHZnj*F^hyy
zs~*j}h=sp*U3#O3P^||1##^K6xR(p>ZF_s;eB5$;V4TXK-uC5dvG-TO)Segs`$OqR
zO5ycqVfNjGzxJc2)1!{xqBJ9&gE!Zvt^o|EM9*kaq6(u)UAFvLV+{NTO96@s$Oy-a
zGiZo`0aA%7$Wh(gzH`5H=bQD-$|NFaoX~N#1TJOntj(i=97Q+z{5IAkJC41JgD+Nh
zFifSjWP23H8@Dv&IfTYBU7gIei|Y6O#&sL%T;rF%Ar4O6(i<Xgz1ny>XkZtrjMt17
zzqxw=Z{~Cj<D25P!GgT02>9uree)y&`}eA-QEb;`R8!RdhCnK)zv-Vb{d_OikU%?G
zB?8>Q^sfYnDKdq$_gr^k3|v$*qsTs;y_vk~4}aq=y1T*zxMp*i6~(hABLXzOHC>xV
z@PNkOZj-CG@B*%#RI@rWCZmdCg)Yv--YlN_o7a`br@5TvikIbDMm9`Lseo(PHa}f1
zsf{$oF3rTOF~yPg4?#C-i|3VkE0}`#;c%jF21xzw``<i=*Vw7my^vPHj5Qr;(4#n}
zZ8WhW>9m`SG}zJGunUcGG>N#Ik<tJ3cFd!629}rP)h#)eX?iR1@Y^88oW^aWlkaVY
zVQuo_tB&|P0~*&1Zu)taBQZwGy*5elRr8O!UUM$>2TxuPNSX5KZ>%~1DUriu;Zm)7
z<FbFVUHNkIW?4elnDu{yflN(~$xdYrxty{-?ElR`#2=f!&WY>giqkn*-WjpC072Z=
zM66m(z@b@9-le=L?cmz*)0IqWdVAI{X=0ole%$1FD6c*H)`-+<`FpwyKfj!PTQ0F(
zOCA;dVpI%(B8$+7=$dmj%gAXe<;45Ofg{?0ykTf#rk*bqUaq`mTEpkZ*I7|3TN97g
zhl8xu3JXp-&TevIdqdsbEHhR#n&t1!3W}^RJ7$Yk*7w56#ERxC6QNbM{NcLeEk@F_
z6U}k*WknH-KBekzaes?Kq$J5c<21ANiB>MG$R*Ldb+*1EV`)!w()WFW3q(>{(RBM0
zmK7-#e7N2!WMlc)L@+UZ)c0NG-F+V?Om3-!<t_W9idAKCtWHYxS7cPKTQv^sNGZ>p
zDWKx4H7}A4;k34`qmdtZ{(8^$C`}SsX*HE2kOya6%~$H>nv=LmdA8K&<n*MDvocn%
z|Kvw=g~uX`0;GVUZDi_^sN7S|RxCFd&g3fDD5}exBk5DN=2%{)Zr$f)1FxPf)BaYd
zR2JUsCdX<`pA&5kezV5H^<gqxalC>fX9`Z>`FCq&DZk!0H922MJWh?8srxEhw^a0l
z+4mWZ$|LPg#j5j_K0E}u?px6$^&$wfc}O5uenj;+TTU$HIWiW`h-3cbA@{u7(hO!j
z=fu3IdH=4D{J8n6`PevJ<P8-@D=pXJ)tF;QGjxkzVRVJ&jgr?Q^FAI?(+MSAHV<A-
zA9d^L1#OwjU;Ynw<w8f+BBvoKcpHx%iUumlrcFcj&4qgT{&F-1-i=4oHN|CpeyLQF
zUkN6egn`rbay_autWf571iO_|HAgjU*R#hDPVOkHub%FFD>L0uGwQME=UdzL;`E<J
z(PT8@<Q%0qSkIG{53L(eD!KDi63wcmnY)+dj;d}%Z7p>(5+ZUw^=Pl>y=MQ{JzxH%
zJ-rLm7%Hzf5;<cDJ^s(6Tz#wzlcjjg%+=~69p%+OfA>Xu;r`J_#+XYc?1e-vhMWGS
z3X{Eob^Z(chx7Z@QTLuC>+KJ%;YygT*Xw2P3z7TuedD3-TkqE0gZKCa|8yZ?{jGDi
zE6ck(+E8(mpYO<I=JbhT<h1lbp~6mKpC`k%_P=$~-{CuF{OEL~?$P<lR&lzjXA4p!
z5x+FgYV}maNsx*I!>snHC}~BV`gg}~E#Gr@SQqm_L_>3ly1x<~bw%#@C!axDKIB(!
z8E;gwo(i)p&rGx-vIZ(snQ)?Bmwr9B#01w{PBHV~{myn(>(s-S)g}3!`0G2UN79S+
z5od=Z>fU5y>D1Gq^p+NL?Z_?9s(4AOwu^kL9sY?Zsau{{ijw0xN@nC|r$2SriRFC}
z<63iC*|0p~Fe&9>d%KED`3wMW*R%Pn>z#~T87}oX#jJZ@ql~R%Iv9U9>dtaHUeuAE
zwCmGO(MiTfT}QSe$CaM5;J@6=`Z;G{DqB3^N22w8<?Be7>}Dyi3)+DopNsq#|H*r6
z9QJp#U|CxbM@va5!klBdZlFBdyS*UVcdD_jwp=tv-}+Xdoj_S_sVouFa#6p>&xQ?|
zceWIcOS9fXS>F;F4Kq_(FJ}vJ$&Vt(bW(BE*yb&9CP24bKKIhmLeR=Ps46L>sb~}w
zGR_s;?KHu1DJf0H%!tV0K-;bx+YLJiTor_ke3o`L#KCs9tQMuHMgDu|D)a78GuxJa
zpI-Nga>Z`seOvjp4l=#P9AY`nQnQ6r?tGAA1y@Qk+xk$6!PpuN<n^W}el9CQq51@8
zuqt;!OyKthOCncj9TOHNgL{}2+m(yYj5<e!>jipHj5uz0G3>h(1#Mw1wA3?>&xh}c
zqUve6E3wP&&lif5Qu(r&c|aBl?eU2z%g_1t4#(RoU2PRB@)lZ^bH;PpzAu)TD9&F$
z5<DGE$Q|V?{eM!c<o!asut)_19Sw71g(WQ(`z}QJ$zUpM3$cmGP$E92bDf}>jH_SF
zw(Q(`FW-Mc%f817fpVL9A(lAxam?<^4(Vz*h83_{%}H&w?3Nr9V%oPwS+z#}sU(vV
z9VIYfJND{&{bhMVjFv_mMG0!>LtDlhnPT=K*Q<OwD26JjR{r+is41H&*{qj$tQwUJ
zx$sUq+#)!n5uMs(UV~b-k{BWJ0teA@ck;JUOw&TYIp;REL$_}|N+af2;DyL)1p01G
zd6*r=GQ=oGmh^5xoGkArSSLSbA)?Lf<$v(!%x5DTDz+q>%5pD^up3GY;{t=PL}KKm
z6=pX?%C!!e0(wgY9tKK?1+hg5Z*P*6y-MNEY~oe*4&IF3(^gr?i778z&gqdz`;M25
zZ)w^}Nlw+KG8ZAL);Y}bxE_1xGt~6voY0E%ONCnKXru!BRg(6Y9XoDLBeqetrn5Px
z7OAKp3X3AK<W!bbj#P&IX1LHASUem9ABk^U^#Nq7;gqf6|F+r8<ouxEc#+>-8lZnh
zG>8I<_ea*{q5m62Y!t7sYU??hC_5p!b>0CV8s^mnUd|rxhU%zJl;E^wj_2ARxo5Z<
z%HrO7*p*h|M=tYk$F^s;vMSEFsuehm3R5W2G&ZUzRrpw8Y5SJ7bHqw`$+I~oQn9$v
z3#e6P*0QcmN@G5gT&2VC3(u)dYT4KmS-Hx-s86UJ1;J2G->)pKb>cZzy`AWW<DHhr
zb#h$slD1nN!AnOmgMs6zuBiERgd4W@q5~dWT#w|q2r6gAE)|CT4!)7*G;jZ(sZyId
zUTceLRQ0_A2VtSLP-yzqmggkWqkB4xWi%PMeU1zlTCsLQ-lN<Z+uNr_LsWIKVjq_Y
zwZLVX=IzxJOiJP{8B5nRo_9^4Dgp2qe9L<N;U8zA8q=PODt?evA*Kcq<fA!fOxj5j
z%#?&PEws^1R?>2;snBOxWa+!58+PBKmULIE*qP@;P2ot(nvmuuPF>H7rh~Xj3(dmh
zSWGfg8?Uph@`I<|LyH8SM~G6k+DyD)@N4T6;|g+-5Fbb@bMoD+2;v~i3S>5zCNo)9
zOPBV`y3mY1t`x&qm{iJ&aCIz!;;<zPD9<18HktQ(v>iYB%@0ts&ItB7^w%0o6*NuY
zJr=4uK<ind4swp>iZv(Pt+W|4RUht#$%v@>Ni&1P<;jZAMQE#QaUIVQIqqrQW9~(}
z<`I}^fd<6uK6UEHbCWWV#5(9{saRSz%OlkymQ1{oBWg~K!NglrF@ib~S@W(N#u;lz
z*$8D%U?VHea$kkhiIqWmxM_)3Sl&oBJ^9>!xg`}XYsTKL^|1DJpf)=Rn#vk>5*<uL
z4f{cz4Rz9NYa$Z=_DV_PeK_f?^kv;)5k`NZZRugo`W$_q%dNEX<X{v#Z6=o&Ev31W
z#V42}?{1!Re#W<C?e+ih5hIn<<1-Xvr2r|Fu@1%@RN@#r4OmGsV<&MwQqmD2a)!ie
zU8LWGDp4&2MvW@GgfabDIUXOfr`ffk`NeADU7X^661~=;U9r{`NuQZN?q6?|Z0{Ij
zT*fL1|6~8o;Z)T|AcWI6CX{x^4zw2w4L#~#LTZQip2O)BP8bdks&H%x-Pgi<ITR(`
zL(%YOqp>fZ=&OoZIV;+&$zb{~bZJREav>@W_Un7)xz5QjXue+X`~Fm25o&IKjtigD
zSeZvp%T~7WwapE=@wcVwtF|L=vE6q`Ix_@Phoi>#byu_^|DTDdE&7&(U<4-RY@nKf
zFn+d8b0?)QTHlj(XXx_ngWl+*9JYC9-~|T@)z)@-C~E9o8XZ)RJf?$3)MwAl3XKqT
zAGy1Kx-uDshecyaPd%l(t%f~a>8i2uDA}%MZGSTub()_ITK=FI-W!d6c4@k>_*Ae{
zyR(n<Ew-kAxKwGL{K_Mj<}&UBdv)>2r6=^o)?m9mp?BQg7D}pb1(#ZZ|AlrdywuDl
zt#;HXZMIuzO^M-X>{Zf}$HryU;%PSUi<#y>7LAho`Y+3u17|@TqWu?eQ?cb$boDjQ
z?wm?QpK!#6)-yb*VW;(ks47>@ofy`^68~3oD^I=8;V(h5?!9}vUJyruv#Jtah|a3h
zg}%0a{B*%>cA^~z#M!9hkMqjYqOTpzyBqXuRBxV?hoichJvLLpxt`$@LW74*X?4*E
z_K5J+UfHaqPfz(Jd&hV5AjfJyzkU5k=rllgt=;FXL-J3ScGWNC<wNSFu#=zq&x@_(
zjy>*kk>1i$W6rMVb&ZFjN7m1Y>DQIot)E}I5IRTX6H~9BR{iqxt-r!@A31qoaZzpl
ziPu}L?NPBbuC@F8xdW{`hs3>K+!gt+3c+>4#oxGJfBUgr;pxBMywcR)`ir0V%HSdW
zz*m3iP-#kUbC1Xax)Yvx?4nv!)kFG7>vT9TzxDM{9@0EdUD7Adf8rPP7drR!%X%j)
zUObt1?#S=fJ5J~Cz5R&#e)#pg+HpGEb}B#rnc|Du9(eK-?_-;x*Zcdesqypk`Kb%%
z$HSuipgNu3AZE4oV5{P&Dd$1;l6Gn@h0Y<_JgBm}&rfHI7o+jeb!X_UJH^xX$lV~m
zt#+#76a7JSI{*B+zihSqf$xnTP_0uN4{JKK|48ys>+6f3_+hm=r@wW2q<BT^9bf<T
zLvmK10^6I_-&#+iDvG?<v_7IvhmDi%pO1FjuNz+*<5}+b`Y*6O!j7yf=?!X~-%nEy
z5Jmi$>V)P$_5<%ZBJF`!#@B5REcxtuYh?X{0KZQ0qCAOJpVOW_a;LLf&*$Z#rTP4$
zC1*~|@c%=4SLCQ*%q*3Is*-1h4l9=yaU3+=FP{A3kw|lX*$<WSXE#1S+F6{u%Rj7t
ze(@8(>u>BVe&Q?nCeQzqcv0)eIm}+~prYs=N6a2G-H1D3G<B)@wevd)NC~~Db;5Zw
z4S9t<Sm}eZnU{gG{lHiAbHaP|(BI!3Cbfh8bRoN2f4emg-<jbWQT8Ft7@y4V)Yg<U
zpP$o5=-x@>hq<A>S^4arhIj<`YB48vwy24cd(Ll<#0DYx*dWTd82A~sd(dTf*SV8p
z`((0f?CYOl{fxOZeBkkWxXR<5ygRFRuq?ZgcTs*V+>w3sYm4<WZGH<c=+601+#+{m
zi}_9{m<MO23(M0`7V{x;8raYO!mUO7vf$p<ZXNH@hjrl2>!f%<9Mm0MEWNm>J9H~R
zycV@J<2#CXBEkoeJ|j{y+J263KqWgBJKL*P!ts;`TK`bd{!z{1%0ovKzpg4T>Oq~j
zqNV*IF`pFoXgR~-rE#Ji@1(BF2Cj-`bgZInrZR7d-2{8)aC8g4Sy9^M5C84?JWCuy
zGv#oI<aj79<IgSN@V&6;n<nnj*1gBLj`p5t-)c3M6gRmSVVdK<*k1MQY0cU1ET8d+
zV|$Y`etrGR$wPX*JMau**L13?(eW7xZ7~ntm$CWsqz3zP=JiY`k9VQw4S{{i5k;<2
za|ZCwT<f2H*fZC}=FaDfUGv#_BsUqUoXkHL@j3I}SwTl`pFxgi^Oko3-BipQ4b{Y|
z(!*IyY)|&BGwPC&VfU~q&u&b{I`x6?EMAH_8;>L#olj(EI={AUtI%bu<va2o=ZyFV
z+L>=M8}e&<x1P}ujm_9#$9X(R@WP{v;r*`s03vlj;Puc*yWqc|9l;v>RYbgNS}^92
zrkO{ZBp#*Gc%J`&*)5hLuz$L>Ti+3x3DeeGizu`_@HBqQlYS=HacU^B29E1#nbGs*
zEqe3&@%iWTW9!i}iPsf4AjTozAZjwP<C47@r=ZwXw5reX`+WQI&wLf!5$}-z>i&Yi
zI|{92b9O>&Pda##6J1LcO(%l;eY}fi`yM`y?TH5!K}R>V=1v6M!OcwyKc{sd&L)*x
zKrOmzzSO!Mp9X2t&KBb`7kqpm(XQ8=_(jd%^Rsys2WCLdZ2s{_u!IepxW%F;pO#Hr
zGI4fV*<p-vWY;0z5$AoUmFJ(tOe)@0zd$6e&LmmIyGt)dIC+j>R$4X^X$)hZj%4W=
zBCI#7lH`h9Nw`UTk*m?JmibYW8yS^+yUv0aE>0LQJp<D!*@fSE^p?Jte(tH@mE?eU
z=_5}C`;tS!=LVk&KHZo*@j3sgU~gk?>S6z@ecR>S7e3{m>g&7k8~@9*r`)~^+n)O4
zQ|^Y=52{ZE{8T@v{xGQAg)M%4diaBo;a(T&bNng2%;xkmUwC-)SNZt(Uw)zdz+U;=
zfAY8P9N@<=KQ4A(KRo=Cm4S;v`g8dzKUvvy^&;xpws4Wxr_zf&cY}+3{0$db>ChKU
zhfGV}@*?#eX@C6Fz3zOqzT=_4d252VPE?4eZsn9se8NLnHE4-J&2jNF`5G%p^JTM3
zu@jdwak-r3TxNfulC|O?Ur8VNv+Ake&Xsu4CYF`p*#ru}KVFvClvViVPpwA=x%BD-
z&mT`dV}j4s2l&-HKRojx9>L}6WPB;K7p)OT5`m03t-+|zY1sOVaFie_50nPnik;w|
zD0`Q7Yr1sH1|8=oBRL%^yXGGgZl8F{m-2~%GkSORUfEESD(rLWJM#W9g3A(i1oP+%
zh2*|hZ}Fr1q-dO$TOxIzBE}|6Zm3WYFl>n8uqvV*9EXt9ts(dJ|NK*-HJY_{tEteT
zO&_w08Db?F6L%7b$OQ74ej#!~T4>!b5>X5zzAC6gsTK+PX7XplW4f;}8RoK^mLdWZ
zfU7}3gX9)#+DW{1GaqtV6-jJj57>kaX6bDaBYqg^EKvfR_`AgmuYVx64+TU`2Ix?&
z&}rIo0zDo}HhUss%T6e3)@|6Tby3-UtU%|dO)M<qQYrtGe@xY~@o(z7zK0&fd4I2F
zYl{X+2e67pUatcu%}NnR?MN0w0?3+fR<b7I2CEnGlq^3^XgE>-_kSMePo!waQL$YT
zDofRpb{8zl=(Coi2nTg-@q`RU{n7oB{WBzi-c(_|AcG@Mx_SfY{ksbOrkA2bZmq~T
zkr{9@HP9*Hr2s)4^@~YqUog=`c->sMW0FZHW<*6;X&f%3U=l@nLT(Y4TXTrFJ6Gt7
z3elJo?+sL7F%%73GEBM2AkJ3;osaxH5tJWLpF84r3uCgBACFA<`_aNgSLRND5~_)(
znJ98ox1p7k4*)};1%Sl6q#*J~$xTSUW81T>hKb^e?Aue4Ww}rO%-?#yOK8}a4b&oU
za!2z~6aiR_5kkoTc{-{I>GR*0kssWx-KqVN3T9o)Z3TDkiMk*vyA?p2xGXC7%1z^H
zth}{y*uSga`}EUtr{6l>?@uI%?AA_MdC9tGur^>LcJp?ee%iKO=IR1TXn+>wF>rvv
zEF9q~x3N)X8YS7dC^NtI6>C)Gqp;8)Mq|~&0=Fx)M73WwOM$409F3hTh>#>)UVKzd
zizxbNp?QGZR^NKYw#|+Txyk`i8C19n(z{O)tL~2e?V{*T-R&Q#{~MV>3>tZ4l6x(H
zS~5qi{hDY?MhgY&TQ=F3x(k@ib~ZM%$4vJ5du7Ak0H8`v?*Vo?RF}Vd-s;;ggFbdQ
zVE+}hr4U+Hm(iw6*i4XS71p9j%}4>whQ#~3`82B}%sE}J1pW}zOacnkBz*8b*Q`yM
z1OGM`U}5otU-(X^5l6-P+$-ylEbxe6sgQGy7MhNWf=~?QP9bvD{@rNKh`_&Q)XQT8
z?2OP<HmCAgRG}X`;g<fx_cv@3lSG!RW^@$yL1%tJ1N3LD`SDyN{JVvZP|#6gDFX%~
zytE>g72En>|BBUR(FW5zv#z-S|0VOm!nGvBo;9Nt+iGSn3td>DB^G?Ti8-%3#?;dn
z+Fy67R@?<q<rSki5LXtB$Ko{#oOS6p64&|Q-vuqqw+p#~W8S93Bf2SVR#|{wQ3G)S
zFygjajXGnbD){Wt7XAk;z71OD)a{N61FH-~g*f}ob%1A)8Bs=3l7HihK<GSspz>g&
zT&mjVT>h7T&8oEvv_}C;3ap5^0Ym8pS$Y=WSF&_N-v)_2S|Hcxj?#}|TZS#0@>bPX
z0g?&HH8kv^Q}kUwlf(%NU4k38l`y)~2j#=vX80H&D+aFw&auj_i1!`8{O~9(Vje>=
zjDM0?%tIm*aa>IVYTB8O+G?!iEa)VbrAVwtxdtqF)2Sv&4U`FTq%&#(oM4mF@tfdq
zzJJVbBaQ;y)>b-putb6(;hqdUc(F}OWV|lM`d<FM|G@3Byw<{r)=3%r;L{q^sOT(u
z_Pn&>$cb^!+i|4Ccr+2Y`l#ZcnZJ%ZE5l-RTKeH8<A+Pxp@W_z7m8wMwgCEKAQhqo
zbS{Z1GuNj7dGvyh5wR{mbryFM?Q1}PZK=>JwRIdV74QWZ2scR;t2XKCEk^8Ge&h={
zjl;wxp2Nt}@+3H3G(h1Qos@4igHqGC0)ZP@F}<~zQ~GJ5DRvm;dBOKy`RD7<ZCDZ;
zjuL<LP~aXqGcd9OOn9__&mhK*>7!=sa_9TUNL_7U5S;|HwZ%xDKZnzx<r$rMB=S3n
z)ygF0*zuJ`B*pBoG>B=uo=<PN4T+fhbUd@G`GKQ?Et#BL82NSzYfhxy_n1#c3F$@P
zkdUy#lFk~zMO9$_M*X^@Km)l5o#Dr$8N>@0oMB60Uj<yp2yqpLxSDf*^eL_gk7r4^
z$d(yhJnGo##t;>972As21^&z?q-_-t(pYNvSOKfyMHLx@+2M_+8mCC#XQcEP$qha~
zW@OdOdrN?)vXCO=+HM*%V;*3WWz>pWyK?wRbKCWysAbLQHAx~FF=!LiNk*n^X&_r&
z3s2~n4<pwTI+l(bq68Q8aAx5|E-OtefjYr$=(epb{!m=XFh5|{l0o8*Mixv*&FGk4
zUH@|rf56&OSZw6SmIOPI`{&xzP#b2k0Zl#GY*yQ|vhg>g-Kr_uy!yyfg^rwdn(fwf
z6sn)qb85TR+jV>TSE5Fnq`+vkaL#WYJRzKJ>#XXYJ}kz*CeClZ6kO7Sr=OXOrvISu
z`|VTiS0`oPBxYr)Q!Kktr{p#^cSY`!)SL5@5~o5nj_GObD2%}*t^mqsP#7iL41Bv>
zEZgpuYO{XjU;P646e0#y%8UMw78>$^avHj-$G)hKH}X}zh2}N<d|NcW2rSy1UM#pt
zqfHxe9MxbOF9w{wc}~w<Dd=_|hIMqXFjlgUk5>C%4$23_i9%mx$aL+T9;%#b>`j`b
zjN5Ein@@^;4dEZpwf#o73Lv=`8bcJF)iz*mTgVnO=a&L)qq5Ogqzs#-WF63dai6?P
zT>j2o9^uy^lUJQ8fbkjZQ8jyrq^|+~_;tI17h6@${-cCWv(f;Ng<<~4fJZ==W4*Wc
zo)0Q@pg;=oN}=@(k?O_Zpwh1-V8X+CUqX1MKVNMFXKnDCe#ZrhoH^wJnsxkvy;AxE
z7gOmhP7+gt9n{)7*{!8zz)&&+eD{rORC0WZy><r%#hLu8C%3XbXY*ntJ9Qxp)E@n*
zsFM`@IRgUi>FheM&$=(^i~2(74{A^j0O_Nkh?lf;x!v9#?bZge%8h?}Q+P#GpI<V-
zh5!6{u$4RZOpUifkxT)>Jb$j+n%}td#7;HvYSkYBsvMdv?|f{`|Au%?>X}RVCq&>B
zUlZ<*PIAYADL|}&$G1M$e7XMk)>&x~i3Dili0t5zEeUT>e8JzB_bo9sklp-4A>=&J
z;}mx${3j{`LKyhCv_ALxdKPKPriF!yJ*Iv82)GZ}x_B;100RwLwMVJYJxunjc<cnZ
zWLmvj2Rl`5{QNNJ&qZ)$10^YX2(t4B%D++&QwDil8gI>S9lM}9oKQcuJ-Y1s&wf+^
zhe-oH2>_i90$7AwsmCAR3aG-qj-m}@luR4MwvEH?`v=%h7FA$iH^3hnoxYzK+b)9@
z4Os)P9{wxTI3ok%c7OPS-V=hzs3XioCoer<n63d2=LDDzFfAC}i=lQN6qh1rcWWmd
zIot|s2U~y2yXVAnfJqGDv%eCdHg^RtE_TY>{wU;1<s->=Slaqk-`}N|)V3#lFu)n7
zu@^+<<KQ8Ka;kG`;5c2__L^=p6~&SxkLb+~)27k1xGp`+3s|C-Vqe=bR@r*6`hL$b
zyEp~A^|PN09~6_3!LBsYj_Wc<gLg%p{2{5l7xh7!&eS5Wpm<AkX{y}{a+j7EMu7bA
zWrimJ<^c~m(E56L+oz*o;FV-w6wa5K5@0E<U(k8q-=pJBzGVQ$p>)Jg9h-6H^E2e$
zPwE<w5i|*rOIrvmooBSP4IDN<#Hork`v?DxW1SJl3L(;Re>fqhD`;eml<bPMFT3=c
zrQ<nU)QoeceR~$kw%lj`p~0CLu3eGSyrNsCM{@!)E$s#dywVoWEzRe{1nD>=w@0}P
z>CB}d>x_?V%;^~#4dkSzH7&R2^G$Q3ViU}17SLEFGforHz;$EO?)f}vKr`7!Oc?a}
zA<O^L=}Zyb<6<m}Pl!D&YYUfrQ6Ffn7cR;H$+8(=R+BZV9e}n;mg|(mzrUcVhzkjX
zLozXgJ94){e67p6MGHm&;0NvlCc97T(N4aMfC1Ker}D-g`Tj{z<>Jq3>(N{1^DRVK
z`*{$gyyF_w+f{LiHk%oUZ7<`!`q%#p(tH%pe|(I;!mvRDA_^TXS|<%O$+*(b+-Z|q
z&IyKHksUasbsRjUoT5G410i)Xa4HXe>+b}fx~y<}K_%@b3IR7mX?*kpdP&D8@tq#s
z4Ca{_u#(8iN*5P`XQn!D_UF#=$$?kT{p*)aelLg_*J3_8IY_S1OywO>ZVCMOWPYwi
zSCIjWmL>}#Osv|;LDZiI;$;BB^gYU&&eATGyqshpIXH0wm}fCiU~926A;+9~EVaUe
z12Y4qG&jN=(wxm%5MnXru!+Gy*(8q#UVUW--!mA=68l>P_E2`FoXuGlNU%gxX#58H
zrh;6w-tCLVPL@zqTg2$=N$8TQmSf^{UQA`hPLyG(*~L;#k5%#_I$7F;(+INKe!93$
zdie`Wj!WVk7krC|ohBHcRq&^H!7}jX0v4LZ%cB0+_uiu{Oei`wTe}cVl0CysX`W3~
zN&4D`R8-a0Vp4-(MvUhi)!RvOjrowKHfQ^E&yG2Q7qEJ&wggn3_jS3!@L;gKjNUxG
zSL(#;VUI5}(f~(zWF+k(xen<DcLb2(HV($h8pu1BcYI_b`1fFMcVTLO6=ZMILGi=B
z;h((wBNw8-oUZ?5;UfTehxR>yNnODd|DcB{{w_bR#S{%Li7_=u;=Uxs7SoHozI>6t
z{Kx4<rj~)p<%>M^?k=+2lK<+9%o<4X^{D~#^EdwLS${SKNqcP>INd`x>pOb=;s2kS
z?Kz>w6*M07vR9b?7qBrjzl=m#3-nn6Bf<bJH|zN4Y$KZ4;<pUGn2B8iZy*=~hV++6
zEPpwvvuRmJKJ=c%T*y3@U+Vqm>NAUy$FfIkNTth<TJJXm+<IBAzIr)&G9E3E#12^h
zdlV*H2|`Nn7_br`2NQ$?O&snY5hAOm)TCS}OoiFN6;o_je}6RMAnuK0{e592DIYKF
ztj@Y4<B?jtM;I)LT=>svAQmNkxA;KPa)}b_A%PN39`TuO7;n7A8?|xq=1WIKQ<h3F
z17xNe*X4KQtB?F!Ytgvq3J{JUrLSUdQFOc|ON28lm_reS3)1Dn>TBgIwii?h+Xyqd
zxP7Cx+sFiG3K=DF0ds@^%~MHE2bfM#CH9;)gcJfLA_cUlY7VjD7`JL1!1nSRWmKs0
zFMoFzu)<L@KH08n$ngk_DFYs0;1w_hL(oDASRUZmR5rkAuVrN*7tJLZ(sC)eQW3Hn
z<j71<5&+`h;t5JW(3_TgRgLe9ltr|M^-zRuigjLh#8KV>1P6;n9`k*MqBQ9LVIv+a
zgtestx`6=!`VCbR&%73nsek}LjfhF2ww7?fEw<oxdZ17J&h7}VA7CwbhTE4d7c+g>
z>&&KX8vGZNeO;VzLY&g6Qe&??R30WME9LJ`EVTs(iTK(a3t@rqS^f}#UP0|kKKO6m
z2lplyg;62f=Pbf|gw8{<g!hFt=!XX5sHuGa-Th(U1^Z>ZCt3_pe@-$&P%Y4-o2r$Z
zGgr8)Ap0&QAZy0Ymyq}FG+2}}2o-^y36)#Njla(eAP0v3Mj(lPDzZwxd-#1Y#PZJK
zNF+{(I6&qWkWsFra)mMQ!oCQkfDAU52BwP$b|)cH^>h0Xa7ws+p#s#l$By+AJ(P#k
zGZzzNVA%Da5e)(-pk=?YFKO!ILKcUF-*OKYmbMYA5@d{wGd$K&A95ndWl7q!&ZTMG
zp*+MmC~wIB*k~pf{!PVdA30cXfJzoMi$55d44%njoZt%XU252k!NQgT3^v~hY9G}A
zb<AeFf2t7rVywTaWy^jc3W!F^cF@=-gQ=|QDz{a-6<OBZDni(Vxj7K{n?dY>L}*7>
z$#V!V5)8sB$dn=CplWqd7GhX})KvX%etA8+p%GCT6(ZHBT?-EydcFdoCb3n^_El1l
zkSP$^QP3r+cPps_YfHZsgQhJa#pZ2Z#=r?Yu=M0mxLhEuTD1oNSnyX%S)ySwcAZ}Y
z%>%6q#y|~14M7T|C-Cx^X|n)Fke4tCa}^RNRl(j6%9bbvqfKi%2}10nA!@;)YZ!P$
z%RC;iN|*p^vBjc}ZPP_zcKkN?X5;u66yfshhpbvY+pt6Qg#i>T&@ym~TE*^L55o<E
z&KHP5kOj~%zBD?5Hqk;WK-<iiH5Tua%|K^Jh4A+Ya&pRw4P0uPoj&4HDR6vOmVamD
zmYT?-IcnJ?nXW(^toS^fFiA#fGM<~(jyrXKBs_6R@6`~(888q1e`_!iG#p~-goWbA
zmy*fEyH&FGz&u!k3{G6u#v~}-4WMI8!}1u%W_Ew{@%O2O1!@#K|Ij|FhPcC=Gg!=d
z){#X`h8PwhSXh`1LjvHw^`2jL4hvq_e&|gmj}RHVt#u59^udL>SGff3x#7&%Rzi>m
zzY*?TI>OwZhg-A1^jAh!$aV1unR>&nb3@M#S#`$T(ZA_zG7Py;700995kx}+>%}|v
zCkYg0dpgYOk6;6|fIhXaNq5V_%aoIvkJQS9H8u@5)|fK1S`WpFv0LH?zfYY8lM|Su
zYla;bg_Q)LXdx<TJ?@anr16B~O#tjIG0-ApJmcf)BiTfCF$CEy8pD`O%&268-_Uv^
zSg3}*#uQCxa>&Fglr0#sqw92v%$Aw)kNxU8GC&ySEOTQ9CTI|(YAa#yd@C^%;}K<o
z-6T2*6Fths;1g0LalW)Sni!SCc5-iW-15MLU=-`pBo-*~nk9srkH<?I>kv6=2Jnz>
zTMW5E3>Zk{-gQ6qNAE)~GTH{#&q|lMP8i|<2++F~(};`%85$h3ww~$9hBZH9j5pn}
z!sEUMxC2@vf37X*CCCucLl3z=w<qVxe3`qs)(^J+m>F5bnf2$?1hawjYsogmdNywb
z>Sb8?<Wv?9os1q)h#foL-nv<?q!(>v0t1{3@~9rz9SbXAy3E>xC~I!QYDyQ7ur9y!
z*Lf?CgjP<k=egT72{)YXB))YRzrcpoirDfQ_-`}`nO3L*{N)oV?k~#lA#12quaq%8
z0z1akm~~<)Nz2U0@KHV{;&o-W|JDC=oIja<*RosMmI{JJPjG#Mhw=w{44mliQPYOP
z4R&ZoW#09N-TsJK3BodR>Uu+B!1j?TM>2RV8$Tu;Mn(@6VJ?I8q?7l}`+j_Pv}m#=
z0TUL4(@#NL;QXfj`uJP{g(#-KAHW1ov~EU5Iq0hJAP4^$^hA!*nFd}1Gux^4ABr(t
z8$I3b%ofk;BhlyECq(Pdf(vTs>&b?%pGv0B>SOwB>v7>8uBw^i{;X)dA|IE`z<ZPA
zFs4cKJncx{$4W-DQi9^35PeGmgKq@REtX3ggDXGzi{3#|=*J6{BUBS46OkIepsK2G
zGV1fI{nLfJTZaNAgY%cV9WhtXdO`-RJcQ)rc;kuw3(>`(-4DH@>BtSOkv81|M4Rlo
z=Y!T~pPrT5XV|WSH|gX0ktKajKU4r@oH@1m_{=fPU4X;rHj|Ttr==};U~W}E;>-k>
zWVJ0>EHdtb>R@7U6K%XHQq?x)Ot$xF1Ea_C%Hyxa<Hib-`3WrjmQ2I=A~0jzC6Wd1
z%o>Q!uon-i6g)&TURWY#O6iQ-4Q_aZcZ2I081QLvBv|<yfz&BTh~~prpWxR#4V)$Q
zw4pqrQDJ!Ol``)A1O3B^>0yDSi%B-!cIAJYwZbz3dW}1ELEA+;zv=sVb}`)^891Zz
zT(~Pb>;ADGRL}=OG*Xo9vHs_mKn%A>hg)Duvw06>tz^)gKmMzV>OVPnFVNv-QT!JG
zBklSNp|8ycfjGW>;@LZ&6tA5yFyN4Q{@jb9f7^w{KZ`oI&57UCm+~)aXnCi~M@k1k
zAn(}I2s$&xD=l+Rf3Dqf#LP)RqG=lXx)uqT=NJ5^^PEBg{B^Q^#{IkCY4iE#oA#K2
z3<%3X8p>bJd$0b-*XHxY2%t*_2Pn$60!tg)6*<KN3INGqJdxVdN|BZJVXk2?2GBnV
zbf~le09!2$=yGIf9C+xEPOP2E8s4MB;+4nxN3!53OZsJbrN4iB<lp5#dscNyKUX~r
zZ>xBK?hI}ahxN?kThH+ORv2KN@(cO^D_o8`QwOz==Hgy^w6{mo00M4!ZF^_~t%a#|
zrrNOmDqPVc!3T<axchP+PU`K^3)(!-=l>A6ZcaR}CnJLlO*xkzYcoASwBsQm11^IG
z>H?nH9=YOPgH>%1(*Qra&l{`~F!;r>1Fcs1=>l_B^`Bb;@Jg{jNSfd9w;F`Tpmj5k
z56+1ry5n!#_@eG~fHMIaZadOk(q5?qw1fp=aCvhJ7>;I;F}FPeI0Gt~f7|FsF|qxh
z`|B2PsQ_4m^9mp{kJLPy!mHCyDI-G9768|@b>!Ti;j2JaRb)*^*5?fJI47R<NgOPW
zWF;N9=6a*#?kqgJo|AK>bENS{q3>tr)EEx58UGedO`xM0wxLK)Jt!Qc!jSM>h*?LP
zO=k+o2;5A2po<VTEgF{kVTcbP=0GVZz50t!S|iyMMA{ACjF~UO7&I8A!&75Wja1S>
zcc1S<AM|X7_Ymd=a-V7MP7TM?9m$>%jQ@1@3;-+BYcM$^z`gg2W1aHs))~~)$X`%J
z#(a9Rr2UU;<(1&z>Y@xfWe;+xYmm$%7==sbReUO-Htz`mc7>QA%-XUBG6LL*BhPky
z%-E3KnqAHlT0=`LIjSANwh)1eube1+8;H(FWQvAG!<50oWpQ^!!v~@gSq3FR8skz)
zmy@=7IeDn<J9mK&pH=!|qwebxP|nBspdQG8I&TBMDz|5xxJerUE#(Z6Ji!@Li@CLc
zczK4P=Y!2Z`L8~}%dW+)I;Zm<8o@QNH3205bpt-YM9k29Tqn=xuLO;7RCD8+b^jb4
zVO-mXwRfy=SmipmPghQrr<dRw4#{NRO&;%Tg<kr2XCpJ0k!JmK?UN8SXY+VA1}Vhs
zbB~mxX+j0d;PUo-`J2Cg3#?FBn(-dfuA+=ivJR2jU^Aea1Qm-*w?h5FvI>Spf>7aU
z-2s*gqi{hHHkW;fr<M-<fpzgKNgb4{tYK;DJ0^LWfe|_8u)PP_A4$|e0vk(Ls49v6
z?V)Zltr*xR=gU6O<fpITFQnNq%!ys7LZg!QheNPmv)Wr-6@!O+0Wk-T2&|i_jrr^r
z{`O(i0}kmD0h9@pr?R9Y@THl`q)<$d5vewl-J$=qCSzhPLZ}5U(Xb1?2`)Ahsd)U6
zYU}|!F0b=m{qT+n`emjuKBy!sE5R(CO|m&WO8Nw|zL5faF=lK*G=0Z~T}ZsbFY=D4
zXTs9=VUk|%`k1d`RV@gzT@%<++ZZQkhId2;tp?my@k!Yu8J@v(nd`wa{4~p{&)G~s
zW|?=`(3qIW!pFY!o;Pp|AF3RLYxu*!;DIYp-v3)DoB<X8tD(IAk1qnXFy%U~pn?4V
zN58!uIVI4Iviu17hd*lKGs!PGXE#aqutun6UMFD7=CWk~LGw+xN5ILijZB>3GscfK
z@8Xeq>*;S3`7br!%WqtmSwW)HS8x95yZ?M$yOtais@tW)G0ah{W{V~s=QBp1K-}ne
zrV0gc0m575hGFyeNC$=Jpgt{XlX3(WMDAdrjm~ZD4cfzlm8rY?XXU2FN~@ey!BZU0
z5Uqmo<U8&r{o@v}m0vy;6G<)M^hH%)4j9OV5=L3`gUErp)CX4@e_q7T_~oB?edoW(
zWp~$!B)}vm^zH(7&sI|}DJWwFxE7JPpDH9fq<$;|nPMg%Rcx`)cCALRe!Aeu;jTf$
zUA*ls?zxW+kXBitSvGFW5F$+br;>U6bpn;fxRMmLv4mo@6cP`cppgMw^h<jaUw(Ux
zS7b1*0%kTWOa@`DiZ?`B0Roh9?@e`-rXw|0Pa%pbQM4Zam~cQf2TzPTqwpu2)yk&*
zNvNm{f(Z7g@WEJNiy#F)VUUTg;N-N{5ik%zNRsqq>d`ln<c4ou{?Q{_Dj+HJ6HLt_
zfocQ*J`Ylm%f=?!Lc&yhOh5}80Rd}J<Oyj=9Q8dn+v-+GTxZIgs($MUooRGMqRP2W
zsl3IHZ!I@Zxz&bSFzBozs&V1G5z8?XR-d-1Sq0lL!9J7n@NkCOSl<p7k;$xr+L0@W
zC7+Qa%&U6&{Q*FLfe~_IJ#VRH4+WI(5}CvPEE5M2M8=dUz<FfQ4Q!e-v6Up;Hl!6k
zpqW!5PvT06$4|e3?PTBU{r_U2kPD$LzzzwlF>1mn)-+5nGlJy7>XkiFF{3z*jH_;P
z`c4QroTn`NlhG*HX23wlT|e;reckdigMKi)FPV@VItnhRoRmiGW}54c2mVB36R}^@
zpt~$RQ_?7#5+|MzTT+kd<(E+IXm=p4E64wyB^JpNMq~F!us5Tu2}<&dddh%)Fjgc>
ziFXHj(Hr!wP1N`AiO$K}f4u;8?ipJ)?CwIxQs<puDy-BO3v-3-L_y%@UBc(1Ak9QX
z$tI^IFET*X1!o$2qT{hWY75;o#0Z9`X@f!9iZWY8Q)zXM<8oh!O391r)z1WsrqLQm
zGlq<i-UOv4x;Fp_7_-%v9dQ;4%%GA90$0mgi=%rPDb9?Gz}=YwZ(UzjG>}g=sJAuh
zU+5bB%JU}^#Iq<t9JqxwUy$Fu@Ls_19Ki5YHV8od0xN-7Obco_Ceoq;+!sy~M=Z1H
zsFF9UZ31K<<5Cl!yVK9)CZ9$pvc{!n6TVLZ0s$Scz_TIJlxj~Bu4G-&ItT`Nv~`~C
zZOpjkiTaUWTNelG13@pPQr~Aes}S@ieo?s;=g~l*$c)v>&}SnbI65hu*Hg~u-Oy-g
zT2n^J#FLtK@FpUB3p~N}(BOrzuMEHo!t%kFZUG{38uu9|IS15CmPF;&(=N{lP8_H}
z9RvTcNJMx$!gR1k?Ifpy!usO?3o<Ez?-d}f&;c7s^Xh(L^8p4+vjkX%l#QBB@&dyY
zgF?`V%Rlv*-2TW95pjcP0E=yb<HUP-<A7aL=uG}H)-H&NNQY`chplmy0)k<AG#~mI
zHFjJii!l?XEMTBc8#e|H=)Cl9ZCgiyIFS`IR21doM>4r8wkHagM_Vjgt7~Klc+|YX
zDoa$9c`#DkQ;;9Uj9GFZ$i{nv1s|ab%7N@!*6~L(<(aa<Lm?)Ty!QBo6h#6U1Z-gJ
zBwghjatT=#gZGyK;4l9VzsIGGup$D=+5{q@;*6OHQ^iYa3NQ(Vqyu?u-W56=aZsi1
zglU~NKuw6=;Nqwe28Ef-Ku(NrwLDxK?#N3yz+=-#%NusAc%Ay#^!w>ZFapX%1A3Ts
z3^Y<+s2IylN8vIe5w(gFGBvfRk~vqu+c%e(%8q5^8DHkvL7|+|u*(8d=EO{6N)|KY
zgIE|Cin%qCWL^H&-{YDl`IPZ<_j3`xJth=|>xTR#=dbh66srAzP?la$bTsQOsL{zF
zK7J<x<b&ZMi=ylw6^TT<2)CSCgV<E305Bj3X3hKbooSOe@L&0NUfEt`1?=<#Zot35
zOr8~ZwwD>Ut41eGqXA$LlOX3EjFM(dJ)8c=?~T6<GZSDVQ|u%b?9w(Uy5cu};X%L9
zQ7N~S1>@QO=n*e6)YTd}Of%r{?@I`GEt__Z#YE=A%oVpcCe4!I`2$8djeSSi-Xu#D
z#~A*)pK}a{*7Sw<(v)TJ5N${I8yLR{DP9n-USuS*=_)pz@-jZ}W__4$Fl(lj9Sb0>
zJO+10Z$61p&JJkmaJ!>rqG({>Hmucz*}~V=#qtvOZRip=b&p#r@#v9jP-|w6s~IJL
z#+7}}H~%b~gspvn8fmjCy}%Es(0wK!wf#O`*dm(4?2$lOaY+sp*vf$Pn{*>B<(~zY
z0=(vEve{lZt;cpyXZ(ctmKd{xk!qnm>yo-ZxAA*HxvQoZRY1w|@s|FYn0L?4d^wT2
zC7<w@^ds$Rqwx(vYN4wMtB*4s&8lws%mX$79|?{h8=H^@+DlYJMz<^Clfl%*k@x!}
zBK(!Q3`Vfp{(|3CO0sbS;2IgYs@mXp&uuIPC+?;QrtzE5-u>pu(lbk^@0Eu}r(cTB
z7Pg%j_O*Yu@aIw9zYt~4xhJZfBhlU^eLneKeebYL20H$^&DHkNvopv1Gd}dV%~02X
z`HFw8%ir(^tIcg4J#!Kx_Om*fDJ^Me9~~10_4xtDHMfM<;Wo^#sx??u-rk1W*ec`)
zpIkR)ve1RzKN%PzJ5VI@)&tkpqj-Xt0FwA_uO!p~+cVD#YJ22?`RTzzt+Eg1?s3AW
z5eQ_TFZ{Yvr^<j%dSk<%Ia!jAL(Xf`V5+$~13ag!KHq7c1b=K1BBh8Sx*1;rm*Coe
zSYKtz!EU?qOCy&Hg^|`P$!q=nBd1HS?Fu96<WPPX$gC>k?{rEpg-@0b?a}_W*B&zv
z+qUm4+5YTS-qtcW6_8W%9q_;_)#@)rcd5b=DvaSf4Nko}rgm2D*e9QlE`+CsW^b4J
zazBs)@izT?QvA`_6_DoH^79c@cpGQ8{$@vS09;A7eb1nJ<vR{|ouv4UmVFmR54U<J
zZzr;U^lRFchv8}G%Z1`PxIw=WId|+aI1PlaXvv^;dY%EDEl=sw`@i&~9}B%90VA$F
zCGHQm?E@lpH~2K*wnK7Dh0=p^ii35^FdEAMLwmw9K$lYnR+`@mk`s<(X9wq6yXueM
zrj7tK<_@-gcv>Cpmv>bL9_qh;46@r!HR9l`LBBe#M@|pT4mEv0Z$AFA?wm4LpEqPW
z%hLw+m^1vPDU3*wb!upQFKV88?7kjbYrZ^tTdh-`a_Z$@{u8i|%0Ag0sko-~WqX8b
z4RER3+$kTQ(l;2+0Q?k#=8V#GeyKb2<zi_`oe_J^-}`u3ZC~2Hqc*9x@1QEBQ=X7!
z?C;g_D^!yAgRH)iyh<VKw(m8D!HNP0_@Q`_W?RY3dz&@@i?-SpZH9#aCQ>x7fELkE
zNvrqZ`$9PzC{w*%Zoa5Xl~@1w-+nnbpwyH8YoZW8>EB1e?-jpVQ@|z11)?ypF%PiG
zC+9al-?ja1zlofk+So#t%9fEH!v#CE6c%q=0>rLg(yy!21NF$EG_<Q}_!uRM7rT;z
z88yH4F26<04^&(}qdSj_qSO#vNleW+?8UKL<B4fg0%{bnq7NiGrpUTTOvaJMYcLH?
z@BgWa75Y<Dd;l5}$)WtWh!?_)JEb!KZ(yC^P&*5O51JBZ=rn*GWVb_-3<otIJ2~8`
zRfgZj(K7j6OMq{Vcd@%C^uDtgRpdpOZeX)BovjaQ(5b1j4B!AB3b0p)c0CFJ_C=io
zL}Nrj6Ad2{Vj_&p2#^Gj5ocFL4?g~$T|vHbp9VIk7zkm*%1nK|%*Hwu6Ob_b<-jRp
z@Bs8UEqz^*92Ms}<=m3GmlW3HWK=0uHSD@uVFLxhQGX0v?ieIUSI&2~tvjr>5l|4@
zQ~9Pne;deL@gz^K;cXgJ5-ctiPm#`eY<pC*C)~*Ov(HECxcw`QSJ51&%d_QRe&dnG
z$2AfHY7Kyepl#%I@omEb_UKRn%<4E#$S|}zz^l8e!@#vxa@Xmidyx4XsE@ZEM--4J
z3fnI*oG(zUHV&1q4kd9UYv5V!@@GA;juG_D#sgr2P1`c0NI=LEg~A37EaKB(#c`F*
z^6DDcj>Gk4heZ8>?{`07sD`FCc^;={;LG``Nb=MvmuK^5%F}c%BhRA?cvH<8$n+t2
zEYE?hVr-J=eunp{IrVq;JxHAT_{<&{<^!22(aN;!@|-V+J6w5ASyOFrt^2fB&K#|?
z@aF*h7S#N0%(B9Bj3wS&!KZmZXjFY)lwD+kO~cH>jn%8OOXT#;W-B%>(TLngH4T7P
z1s@ZmfcwJ-i9(5=2UWpu28GHVy;FY{_)ekP&x`EHxGp0=5s1WNX!maD61d2HiJC7J
zVI!UqUG3TDku{q%pjVO<`!ctHdVs_M970wQJadGv>?>LR2&(XdA6qxQ-WV>fik&JL
z;6Q#hYjHmyHVn1s>(5e?AdGQ&P|1?%;T@5cA{e;HD(<$3RDnYi&z_bW?HP#lXOq*e
znl~);F@1_1j^Zv0wn*`m8J#LVsHqhuNTAR3)_9n;1OM@jAf71{hTHc>4DW#l{(k_!
ztyV1GfL-|3kmT?7%AVf>!`t=M_s^7}=cQjyR{)3&S?`^`GS;R=zdX9H&bQxq+CNkW
z04qODOaQVM4%Z7WMMe=>5+B?%gg^d(d&<An2SE)Fsp`=^SFZfl>dWu+OZthodP5qm
zt^DDe2kdsBLN<!D$`6Wc!^Q~!T#>l3ffd7j!p+BXw$xOG?5SrW>8>DDRwMAy3g?d(
zTI;+L(Jm)Pj;lVBXc<z%3E0$tojdE7>bl+*Pc{<vyCQ-Cw?KlM1R)TCoCaPo7{*>x
z7+RJ?-nwF4jLWBE;!!&UHQG-g%+?)#DUZ7<Nikqzuq)CGOjk?GUCd=ih`HEGhh+k#
zB;YVdoQ6QoRT{_rQ#Ht42`!WMM8nIp2yh`onAm^;AmM6xC5#rY5HPrLy;F*9VkY%m
zvzDo4(E%oygW+JboC)zZ+SKQ{oH-0`VVDO1OeP99S|pfAX-D&=-2Ncl2@h-vN>sTe
zGcPBl40i=U;A);dVSppaW^zRKOeuQRh5Z;fm+$&zW<DXL8*nf&=251rZ~q90-iW+|
z<uCqoPu9zN1!bPYY~B1JXU7E_aIO9`^&dljemt{5yj;Js@t%Q^eX3pSZW_+^AFIgZ
zvyZh3&ExfC;e@L`yr(G^g+Dr!zpGX1)5n4q?;Yr}uiOJ+(%-C)hj&EVb-~}9ozr7a
z2<O9la;n=I9Xd8}p?>%O)7}{X$#GnVwRbS2mNY2sE|;hw0-1Zm_0`}Ak>HUfUl3Pu
zW^RsHQYYg8(Gp_OCV)~Ya%2V;LtBdD6n7SV;+}al0UA=lRhD>!P!40!CM?U5%9O-A
z=wO2-NC0J~!X!!wR9r5VN--9ZZ81(_=KbEi!|vVg-R|9h2FPpRW@oy4x_|%v{rmsl
zzk3|#hQm%Vyw&mYKm2_i?7%FR-u!Siig$%h{P^td_+2}zkA}{HaMR4O+v2Od8&mz^
zsXNc*Pn@{-+U+>=d}{DL-uO&uv!3y8#iq9Tq@JkYW;Ob!x!|?`{UtSdv@iR6FIVj2
zao>r`-KP%wGj3SZ*-0jV;nIw^`6@l?q;JdWl0EsoAopr`B-979{iS_+^qTw@*9M#r
zaCGSqS*LYe%LUbF+WX03_Ex<)O5eD*Qe0RlIoYM+WnantWw4PGQnRmyuT<=VS+^;t
zR-6B$4#}xgqeq<VEy4ZQ>OF_fg}W=Y4}Q3F|Mi;k$PHITUNmWWfn4vgFr+~+{mc(g
ziC4f`*u#<$-6Q8~Mn1NkgARrktX7Wp+;YzL8JK0Ozm$$WJmd<w^hC-P`-WmD=7b^0
zu5gu`!kd<5Vn!I|O(!nJr8Dt0j0S9ZdD{@C52GO9ohBw2j6S(RcEGBQyGnazu!`i4
zU<|=c${sv`1k)dtif#(aM!%@fj65|ERM!dB<D-fX4T6>wExs>U{iR@M!)twa`5y{{
z{<M40i(bsl7KP5SLs+J%ZsgvY=Yk?1U|Y!zAbG}Y`O-R=&29DY5JUoIx2_(%lQJg<
zi;Ckf;2DyX!R-PATAX<%hqW3@qGH<Ph%qeK=?S#Ti9=$@ky$^>uH%Wnx$_S>`Cmul
zIu`+cJeqQul!MrnmItG$dj|6^QiSH&@z(K44D#u*Qar;ytz%fKw&Li36$kx?^Keou
zvfy|q7AH?}Fk?MOjoW(y&NvYNNI?Z#hT%`huW039EjI}F(NF!%PY7<rSBgAhZzE*v
z0GBJe1UuF`-yX*I749f4QZue#s*vJ+O2oEOfZ>5-(_iu~fk$KF!dM1#d*tV@mPHC3
z(xXvOwlwxN&k`q1<%v^}pAO7hdxG*#%|juGc9&vKB*vl8-xAue$#~<FnCP(PLq&on
zfCL(`b#eNrurvf1nbO!50>M7<Yu7?L(qb{4at)vk)<}WYLCBH#>AcTW!OTO80(o~P
zvtA5Y3P}ofe**kLM(|ZRsM@?zmT3iZn!KHZW?%m^3n*qXHtP_kNEsR`H{2)I8yYHr
zD9tGY_>c>a4+f|Dd<Q36=DXaayBGS|DmHZA%b_k{#WGH6QaUyt6n%`yz+MpFISh`q
zXZ{M0G)%5$oQPw;7#btsplCo;5q|{c)yMOUTUksghu{hEK>#5kPPq(6O()VRQU~D4
z{(8X>9j58h)Q+6Vtj0=I&SZo=UADDD&(ySm%J9YIikL{c$F70s)D|84Sa<{GHl<zG
zi@>H}l8WkqcCe9}{jn@O(bv>T;v@gz?W78g@jsF~#nA#34Zw5=0k=P@=B<g;FbLff
zY|T&PY(^6Y72sE*CfymbO6wSEv_*m#{WT^~*5Mdt0VY85@BhkGP&M$g5MT?Is1p%`
zYH;7=nJZ1d6Jpq!k0XbLm8m{Y6Aj!|&H;iDq)(VJan(0=IC;Wwj9ej|LnsGu8~?Re
zk4P;h_%>XmY!y<GJR0!iZmSnP8p;TuzaSQd8*{m#V=T9hS3!>Pt9_QCwF11SOx^Ob
z9PJ>YeoFq-BY$(1m^9UJu4pk29~L~6aUy1MQ0n*ZED9Q7<#bZS`KwOsGVtVd#XXh4
zomE;yLv(5Kii;`CLvH9IX|z;HfbXd@!*8!pT(llKpoh#~l!GG3D0ITw9}6h9h-_jT
zSCb+6d>eWwZ3#aV@+y}1zK~e~X5m5b)M!v)>WFD&Rs=Rm@=F&EZ0AS7mq&j6qBWe;
z*1N$_J&H)7I#hgyt%vV7SZC9L^1MQdqb&hhHrLBB67_~jFL72iiy|yj9DwpBQxN_W
zzxK9I+8}B@pIRyLVa_y5;xsLS&^H`oq~?bA4(Eob(~W2^!xkRxyvX4+j|P|p59Qze
ziK1f<PPoC#CH5K*<~Q7@M?=<~`zH5sV6np@>hRFeyQ|o!Ch!uBE7l~dWtebb3OJJR
zuaB~@kRq2(Fkd(&FGf2@SiIet3@(&@q-MZ#A;&Qra9=hpM0V646;TmWTl1rP1E!V;
zqJk%Jw)%$XLo)|Xu$4f6{REq*gUKHivHX5<%kAEKsgeal-?^`(*xYi6t&m<&o$=Ve
z?BE8NWAe*!Fl8Yn{_C({haO@7O$zr$|06LL+XH=ZjF*4RqBxrwYG2wktphc}_rCcL
zd0`BdyS&D<X>Z8e4u2*>u2`hmbIhL2y{t{j#^zJSfpF7g?jr%G27S!Q+x;XC)%_By
zmAx1{8%~NSk;YR|Qz;aUQ3XCYm96J&7+an6?|?7%scp@k-*#OvvVMH`>_{<qWp*bA
z-R(L#61`N-@#zTvp@{2dd*nmmwx>D3&D{|M#V-tD3VhZTGih<1nA!%iA1g+w5ptgO
zJ~sM)i^W@ZK9*(kYVHX!iKV~kkUPf)J$7*BH;ssv?nHx+Wk2P84~NO2aZGpP50$(x
z<o*PYvZ?IXcUKWCv5RfR(F&u145vc2FT{>e-s#<)z9qmlN`1rZTYd=(=eaB`e1dPY
zsPhgVEwjg+`=jGt?*8a(l`Y1h8eczPWsbS(p2}c;y6EKsZzEq%v<J9gJ&s0>-M-P<
z9`elx_OEXH*Us+K0wMR#jE=Vb#i^aA2VC0A@rN&+-WjR!O~=@yih0y|U)9|hi034>
zG`YbhM~Z``1zV9&1J=O;3#XX0iLN^*ZeY9K(^-ACiVs@tpWl?ZFH$oYWZaqHY&Ex=
z0W@;V<@4bK*2v4z(c7JJMS!e4l((nu7_q$pKJv@wuErv9u?nz&jo%-EAg=gyYH#Dm
zHr+ovPyt9Po5W{x78D3Z&G~RRHOY?Yl-W&O?&DXy_TUMOZ`QUj@)l&#klmlyVdX83
z%W>4X9oI$MF?CFF*tt-~Eco5cahujyG{B$hD%ZtY>~0S*wQ?Y5fgUIx&5cFsTu8S%
z(8N?W7|~e=bKdUL0~K7_0-J5(Fduxf@Rm#I23Tf`F3EHx6^rqT1trXH3@Nf<nq#`b
z_9pw%<NVeiP{laD-?w^vhlLffvC{xF5*>5F>Be=++YY^Lv_|Z0>r7WqF>tXfM#t`m
zG0r`PTWb#5oVsIsFz#8<Fq;%;7(+lh3x7u?G$!XCj#U-?U&WNiBD!!;0=N=mZvmJ9
zUM#q{<{=2|c=eh<jkACr2kKE+e!#3^``Fu=UP01W#G!h^|6S}~K+G0d+7pzp0*}~;
zWg@`&#?kDMoXRL-7+Yf9ab|s`O~u?u-Czgg;d%$_?@QG_`5mU>k=@Y%?x#9p)AUGM
zoy274L-gJ@t9+E70SuLL7fjv0&61tFU}7R`gEH7WU5AA?3ha$LPmkELG%6A$=3HFf
zG~@w^D<Kp5gt<VBzvBBQ4Um2+r;fkx?HXBUiY@Wirv-|bt+8orm+GVY1}vH|tuZ|E
zTi;%uEgT(G+nyfupS~TdDY<Uhr{Xdy9KJdm_p&gASN^(!73a$-ER&lNHI3;D`IY);
z^3z%W={~ZG6CkI2;dqBBo5Vt@_D?>KyydJv=)hSgcVQLO%yox9tO9Y*!>dM2baWI`
zFH?gD^PkB6ZkUT_FauWIAbQ4Svy@^MoI$3Gk6y3X;d~@4U~klToZ|I|)<uh%J^a{0
zs*N`bVLS1tkO|TpB0%l@EqhKW9S75F09IsU{yP||jOKhoUX?%m5>t^F_MFU-a8FD*
z7#Vreyz^+lC8Jro%46wcS@_^SWAPiUR{BJS6_zd%F0X^KgCV_w8J0}|$e*%y_QJ_7
z41<@^KHW|x%4aVgW!S+mIKOv!scpw?41<sCw<~@=vgrsBm+L|7d0}3=@?(3x&8mUt
z`Zi7|G6-FcVV8eMGyGu<Zp4TPZi0-BvQUNz;_*;>=jZApW-fAGD4UOHx#??pTKG_V
z{+_AISP2n}Z@eI6={OQPr5VMnM)GixP59VF%0<ew(eo#7_hx31XE@bN>v(VjyHgIh
zVX<;^uJj2H<yf=7WM2i{$lJ;Y8R$dc!k`!qc^>wD;6~cRjRr2{$c|eSfGVuG#5N%+
z%|7=7L=)NghenOs0S=G@@8sk=rBJj-4H^Ql5%;sp6nFh~v*qDx_7!dAyndV@yv(eJ
z3Dt{{<APGjb1nD4prZ@>4nWxGZ!x8K@WKKmP`V~CWc(OI<-bX(*%{x~6M-GkH4XGL
zBt4dWun=OYG`bK%ceEi&kFX!B97J}12_Goji1HLPIZT}86~)6NRXF6ug^GpkG-J~;
zSxmr&i0MxQz9?cSH0j#kohPZ_4i>%PiiNu*1i(%=@kLUFeJ5O{gMx*WJxl4He$nC(
zv31DxQTgTr7>{!kXpcEm6_K0W7}oEpX_QH@1ZOJM2}s9M84*+)tAE%gv=ULN%bzwF
z=B8jVO;bz|%osC)Pyj1<DI`U}p2cV+Imxm;-Xo2HA6U#`-qVypR-=#;Edi{S&VNSg
zc3s-!!7*u+M$sypMul$7L{iSBBR3u|hB#rmdLqo@s44D+UdDb;AICfO9dP$nGKaUs
zWs4OeU9jTv3DyP$G1MIUoHqp!NZ(opglI=XD_EVL310uW=tAhsk+aE;vHuDvW2Hfg
zLKK-U;uzwuC+BGCFlSwrez_7K+>+r-A`t9k1;;ZL;Y66JvJ41HC*s?&4$;>RVB?75
zp(a>T7oG?i7Wi@=c;+0p>hKUA5h=|<k12G9J#p>c_lhnHez<^t0wm>v@x0*1UtdlI
z%;bWT_+XI;8;QIuT?vI4bDU`Y<Ycf=9o@G#h8QWyP_LACe23*p$9nRPAsOXA(?>!f
zg{nt4%lUU8FXnheIb4xVw0Q=%OAq-Ra#0Q$h!ZiVn9?S<&yrn%IiU)p0D@&^1hF4x
zJmf0T+MoNab&^=O`av@E6~2@}NV;ZLLLMP@)Z#WCLi@3SqY*~fXiZMPN^|Q(ho&iM
zg{Rp(if+a5#Id*b@=TpDjkB9Hm7R$pRfF*u(C8bX-my}|NdvGf6&C_LWm2=CMN~B$
zf^aZ`7<iW4rU07I2!Oap9{&4DRpCSRR=|B73>g6Y_oN<?tRi{C=<gtsnbL#va7ZWp
z11&S1QZTSlf#jz_jj<+W5UKUQdqFlyn!p?6B38;XZDvv}V!ZX&(+GukAKJ57W2l2t
zPECv8Q|}0g5=O<KB+fKMdQ^S)j;o|_WDNNs-oQa_Qe}05k?@far#o%o?jPKlhe$AF
zXqavs06i3im?4D=TnuCa$T2}il?-aCsr}RERHkUjykr77biJu?2Vx?rDw5k^!xqac
zWI3~w;*n1S7D}Xe3DW7*P_NBkp#Ef<`Ba}J-pNo-8PbqcK=o)vy|r)+Q$|ERLNVfS
zma*|Cfy?!+W2{L={^X}IUQA=8Vek`G+w}MHzFDjRqj=^?Mg^(U*9-t@x>zIlVO@*v
z;~*Cf3pJq2l8?cUWNDb-1hw_R8@hbqbDx(<v0z1}eF6pXbztfYcqX0=AcYw?6}^fb
zMvr*e{CdeJ6Ck(-ED2f))bg&WLc{V*NwrUX)1+sR9|R{dB8AKd<Ym=PBP&+m`V<He
zNHJ1)#9mm4Re4MVR6+}-Sm`vLg@O!_24y>5Vf%1_9a)hbNERdRf<9M@VAkOr4mfT+
zJ5tTbM>HNUMx(h>{#0=*XHn+U<C=+ac4*vobj;~#@kI8B7f;CXsm{dAP!8S>*OgXb
zy@c(^lnam<!w#s7(@j_ci0Sb6ZZ4!FuUxSrUt<Htr5sOA0=(BXR2RqnxMkv#Hh#D`
zBOdINx%BK<$(z;jj+mA0IP@OMSFbPqay-H|)yO^<=f3Q~P=|&%>%kbAWct83Md5Ug
z2{1=N2upGvNWqX9moL2jm1#YacB8;!_G2~%S3o2G#VtYd*B{a4ZH>bdEB11ex3|l-
z(AgP0&E#_se~yk=KY9*E+SuR8+d38p6B%7{zu><~%4vVMqaOI3tI<8hElI2(<s6O!
zYV4Uu^}%qQuevzj5An?z=Nvi<?;mTb5C4hOac|ei_Avjr2T&gFTHnEy?EO_f3vkqZ
zOm=$Saq|At$A{jB(*LBlV<sqG@Vswsik!!8{*)KK#HmtKxARi<$$e;n-oQhXyQ`zu
zib9AgrVIFB$R@`Lm*VH(APsX0x{Ku6h~_+=&Yk&%cVOLMn;WVgR;B`k3cRKm4rQxC
zRE1qt<>Cu8klTGKI$I5~=%9se$CUCLMSCQDYmpt5C!fVnWaPeC_fd`l${wSF(^G>S
zk*C;Kijxaxgt=0wOO+lv?Cz@2w}YO<a*Bh?1q{a=s6`B_;w~;RmJ`5N&;6<GgVnM{
z@5neY!$6>6tyYE=MNYY~VE*)u&<%H=>PK@wEfwKwvvU+>c4rj12X<kvz@!pw`!=pb
zSUT{*$)T#d13RlRnF|&wn_`C?pT{yVF!+cOG!Wqd90n5ba^_#XqmV{x_ko3Uc|o$_
zpdw0j8D&@TN!pN40`58$sab@kduVP+n>J&$S<hcyS9X<xbCq3D0S_>lYh*_!-d60{
zr7j$2ge#4kDMZ+Zpk(e32}~f#lu~DYd=34^7C<F<5okaq9mlE%)S#$Y9J9vorMAaQ
zND@binbOOVMLI{bt>2gmJS;at@Nya&d<TNTxeL}m1})L!b-M;=5Edj5nO4SV|I*^y
z{`y*~9g9S1CaK;pl1us|hGI0Q$~iWNYrV$>9@lpsF4`ICk?P4~E=HY#^^I&WfV29|
zNJ2Oj0lvICR&}K~>I5Xi#pMxm6IZQjqYs<bV$>-MLzP$+BW_|(s5>(OIXAnijPWY&
zSo%Gr(A9kCf*Ya4bpZqKNhcsqPYrU$9@a3x5<fl9$BR_TG3#=|)nTlr<x-6awSRd*
z1nEKrCBtWFT0E7=hpj?nI;t|xQy@9Eju&0)xO+8iRtz|rfN{tj#O=$8IV;bPPXLme
z`Lf$jjgmv=2I`nh!Qx{Yhm`>5e`<gkJL%f}=UJdb)5PRq<vnCI9Fl1JC?f}iD^=#b
zXhiG_ne;E&I^s|?+-nhkW)9*YTs$#EW*Cw?h>>AXK;}i^Whgc#g?SZDMQx{W)2f4V
z*XUIO5yzimxS*}PDU9?L+0MfR!9`ZAAVrE9D+wYbjX4by1=?ph>u7B8DOhO%(~MHn
zR8emY(!ZYu8bP0lm#(Cgr|z;^HY2w6V_KED;@;*1&aS|{h&P4TA(IIAnF~UV{GWGa
z`gUoTj`kR@rT)Xke!VaB`n9B5(Sgcf@$sT&ZAJ~B5FaS0sA0Xpgi)6-AO`95IyFK*
z2tBIy>^tXb>-5_UQ6o>E6a$eh47LCCv(q|q8Np@8E+C;uWdtOOm|NM9GplET5y=j_
z9iJ-3)at5RWxLqTxzYP{{CIwXWf&t@Auk~ba4|tv<!KaqCM=YIcoRCZV^5c|XMQmq
zL~el8S7Gf|sGjqg%o{SurOtF9&Jrk>cBH0@GX1kcU<LY~o2{7{gw`XV0lR=G-7-=o
zh!RDpOPm@Tzi*fAn|_G{ZJI+}k)Y3{O5V&kEW;y$rps7O;o2n?&u}hLO2r2(*j_ng
z@0T=3rUj8(C`;=;c2$YwX&!3PaB~Io_pS;M>mxs3%2N#<9|9+uG40C~Q(6We8lb1B
z$Ca1Nh2QdAAAy$V{ykrm>>MJ>04~a+5Gg<kHDOQ1^Z^q8d~sx`-`BqOdfOsdX$RmS
z6R{&q5QK)0QOQCDrbi>BQ`j#cmo1D$X;>cBxw-+iDH%~uKv3sDfk5AH?+NkXvdR>c
zt{OR6M0H@m=OjQlhm9R9VwrItFYXC2ZyZ1vEn~)r?2(}&M;fu9%G=g)$J*Lw;4Lr@
z&@QP#G!tZDkNPA$HDhxHdI72_&<HtrUBU>+m%fk0{Y0SIiY6zgiDyz$BJjHxF+X3>
z*$=)=^l?TsBp?MS(~E)xcsEod(f8z>hw*iBS?w0{hJ$$$8+~TIWG9#TleZ0yh~yUp
z#&dL=Q{VkDo*X8GTr1K*(~@#vOD_gIW{?C^+TTQj02dP|KMlG!F^nL7X&~c*)<M4#
zYFl13zl$&ETw<TZ0vND8QV291P^~|ThdBl7xL_4PZVOIKDdJcu;a7$^2-n=Ty|B^@
zcmk8gu?A^UxB!oWFK9^q3kokjnOmj)bFp#L{zumvjY5_~1Ee44drFF~m)CqpDQ7m5
zvr{m5tPksPJM#Krb@g6u6xBpe=C)jK{Q2k|9ZIZs4Et48q^0!`rEep%g9?F_8_aQ1
z_#9@r7ev<!KKp@s`E3iAr70n3!@(lI$am=_x4D=Xn0cCBua~H5|FF4jX+ly8Y)UTy
z88@~nAXI1`=7JR0C`NuSmVeVrsmffY#lI9BOW`QYQ6yz-ElQz`e6F5EP!x>sVyNHO
z{@dp+MlHT$?1E8v5EByo2W$wXQj{y@xdlU*rgQ^!1F;N(&z$c>sjwi>fF`Vin5~Ji
zhR0#R2gq-096Gi$6bWXm1CPfV18mRiwWLmJVG`$2T$iO$>fAA7Q<B>SAyVQ6Cnpmy
zg9^irGq9n+{rZ!|2~Gk9VN@KWB~VVmGHV$gBhAzzkq{35O}K04+o}snpL?Vh*|t^x
ztE<@e=>ob9Q>^?U(!sd|Rxa{OW9p@HBh@sXYVqF-wPN5>Y+dq{@7l<PTlF-N%w9~q
z`0V~v7+a_^zdpJ<+I(O2<f#4URd!pUfMs^0;&>-Vi`TzW4T`zC#*6mk7N6WFhsq)8
z7M>L8rf{IrsK6_R$hz)UeNMz$u_fgm??kqYDD0Qj@ln*u(E!y)6fM3tId+<MSD8qV
zmib?xl`Wy((0bJIqgS`2U3@@&lhRL?Y@hXhL~mw%)`rpS<m4IVBvJe>W^ZCY^N~Bg
zd|fAc8-eMH_6Oz4R6@z<ezb#&sFlPtLpfh!<7US_sfAIEXMvisqR7X&LLd}CBUa$$
zU?+1i^)13lQ*pH~jx;?jx<!o<BMmSLMgmh3sxQ6R6c(3X`<Y!$=?iXs+aCpJkO89W
zyv>Cd31uwRdFO5r0uecQp<V`EgCWslGDq$fve4*jF)W=0G4XJe@6CDYmXHk7!jnA>
z*}Fsaf+T@rnE(YGrEa?Ws->#&qZlC1hBov4Su`;DFKhFaEGM6#Zq6%=3@yRZ9Au(l
zp<fasv9&+@@}BB4jS1BF;ZO=cCGgB*`mtp#J49jAjOT;<XvwtppdC%g=CdoHKoZD4
zT4k7<nm+zj&Y9+X>85k0<r{W<bZ&*;i<7geUz`7O-IZ2I*!tzVPlosYFa2K&bV-L`
z#%qVPcG1thbWOYH1#!|dO`%gIwHptW$r;UO<<7U~o+R40xw85>4IN;c4-na9BMd_e
zbxfwn0u(89ZDe%w<^iNK?Ei3v*L91CBy;zIFmB6w7m;O(kwOV`5{#LjB;EulvVe=F
z(&s+>6GQ}!X!A4wAh4qe0<vQLi&YkOJmhh%2PEF-Whrh#q{e0hks?()>RUIO;+DLC
zhq)kybq==;(0Exv>71oC1u!}Xwq!`6+c^g*O|Th+cFcVK=goRy!7^wt=&O@Rggn4o
z^<_4SlUP<^N^lA8Oqghq1{;y)=c)G_o%kXFnOIRA7KCPUY`$;FcKmB~Sr~>yyy;SD
zzpGe;C|GU`X#${Wr{-59K{SBmv94vbl-GE8;Kyc)Zt9j62%@dUi*L20T#RnMtKI$M
z=Ev3DvyY@OhvwCl#B5djUMC%`ebG%AS)8GE<mBSWrDHmmS9|_{Ed6RPso<=a?1o;1
zZrX<0U-Y+)?-VI*>{yuE@$t7+I=$Izyno?4AMNcO;3@!K`|#iwdLy*Xja16NaD98b
zPy4FtL$-5)V6EEe&9?CrB|NKb$Xxij7iD%@TIImW*iuGS5H(^>Q(y{fXeq@fL!)3U
zPFbM8Tp0SjwqUF%vRBGps*>6VcB-CevGeGKwT%7xQgtm(>)hE$sxLgX_=T0mB#bhd
z^PmDF`8Tg%ETbeCfu9ZUv_k&cDipP!{_B;NzWHjH*qor>9=w}gy_(}UR|I?0LQMzI
z^XDfn_3BN_=V`9M)tep9T-VcRTZ-OWIR8>3X{kcy(`vu*+hr)DQ)o!ih{Fw*$`rB`
zE67~<`d`hJ)fu*i97U-FO6(kN`voJIcE}LT#m|A%0CFz6@hgMQgj#m~jk%}=zcL29
z47C%lw#zwRS-ZrJac5szuza*AXB}CKqT5A0^1Y5oYi@t@{i0$nBH~Xv%2PqpTg~@P
z(F<<R?z0!f^!#{H2H*d;ORib<RI<#6iG_q`oy6c$Yk>8N%gY>NZAFRpB0w)$Z~E1>
zk<}ZeH0WfGYx+ygY4at|&06yjbJN$^$GWlU8Dq@+yB%+S_H`q5n)K!2!Wh;X3at^f
zPye8izVt*lhY6+p6fbm|y<YF@I90WR(Z$mh$HOm9WeZxjBx>LJfd#pje(YF@yjI)S
zUI@6@drKGIl3M%W!!6INdPth_R#pYg#h3lmZJ%v1VqZ*J!QB-{vMXq#x@^S`|H7va
zt*Ak5UrLf<^ZReSCMk+l>brk*ZM7}PD~Qaz^oOz-YgXo$Gm|YahRI@nkFQ+#yYH_6
z#tyF}*+D(q&pN;)(Qh4=BGbz1rBg75dA8Y4nu+WNc7$A!h39v?>$*$q`}`)bo-Hwa
zdP};zIcsliSt9qEV6g;p+9s`GtSwrWh)fz|1sHfT;itPhbG56=l9n2}s<fL-mos3A
z%C6lYqpLg+Y;rVKd*|o7s<f+2^kucHjNN4Ve;Zf7!ris#zW)h1c`%u<#!!02W6~HC
z!&5JY;&!5VdjbCe`Rd9gEd0_fZ`U69{+dJU-uMrOKe%P!)tT3Rt5=8C9%=fr=Bqun
zrE~UVChvxA_iN90uBg|PZU9@-Jl$O3#PZ7+ofZa~i!t~6KV$qf7san6B5Ag{5*XUP
zb6EqHlu-B9v3IrY;}u1AGc3C;7$Qqf49=hVYNF%v@`bFNh<Ylkp_vP3e)9?x(al2c
z{u?{G19eM(^ZA6^tud8(baZnA%KR(S&V8vZ^lLKuax!{1^wnJ+W}_93TOr;Bp{8G5
zj<vRVYe6CM$VnVr-t|-R({pHBMeSFAd%1$Tl3(TM2c;f(Z?dd&IncUH=lt(af2Pa4
z%VwJ|%uE*Tvr9j5ph{Pv_VJOf@^zIdVIfNDtoLl&+NGJrwkeAv&;IUm?!SxQ=@gTs
z4v{~*VR;p<6CexYlLYLt^(lGt1129DQV-57?A?_=Cp9b$|9|igRt`w(n|><$r43i0
zm`*FQ>Z9YWjaki8QvCxAe(J$Ps{y6;-2?$sNi(NQYV5vp3t#he+3?D?FP=P_`^m}k
zZ9YoCKCxC3U&T|>6uk;iT3^lXzabG1TEp+vBd@GUD6RNi?rF7bvqi8y_bq$5`npbE
zEycD7<F)4}yRNuX#(DAm?51RiY=zqMA~@Gf>5EXZY{Y8Gzqx|dQfzZsm#5|+(thpJ
z2`w0y0ea@E>k{*IS@T9W6eMJr6iZRR^2f>Yx)vH=%|pTiS1f+*eN|TL0dvVs-7<bw
z3uODIzdru<H4%L|5k0Y?COdOhGa_2vg$XQYM{mi$!~;zKUB9_RdXGuT4O~Re2M_mH
z`x4oc1B^-X4Lw1?7~z&^S##1|!<`NhZqC)+{TtiLx`x*sWOqF$#{ec1-q=?50P`AP
zJs`_uUBlQvHpY;%)^>~T?6ns<=f83%t<G&)l)|vRa^>?&3i+C!%Ny$FvWPNQ8nHGJ
z^@_PQjICj;9R}Vi6JWcxuPkm2W4+?-ErT&!308L&@|$9(Xs_haG5=d;&bo44P%bIt
zYsT~CjOQJPPOk|o7;1%%UdOe+{7$d+ch29-<k1<VM)}{(UzT3uO{cnb<pSRsTPB5%
zQP*=MTG%p`c9XmUD(hTqFND##lzPf#4OmhuWNZE{%aOt2^fx_`nN^|W{Jae(ON3y}
zo|oF_KTB#E7Dw*?c_nTX6`D+%Jrx#j99vBK-Nf|#9i$}-y_^TzB^7k9%)<Q(FMoT@
zfc}OV(B**L#0IY7WSC?*>yjh8m&Am)K;7LTIfr)KE%*PIH>oq9;3_kBc6{ym|I<r%
zEuD9@omub2MjbDFW7YGPpJVs1Z#35(+Y{M1VPH#gf?nGux-?0(NnI_KH5Zv=S0?6#
zZhXD>-*_1kY{R9!8H203&s=!_%$2!MbWKX{z2lP}Y*(frtvJu|(jB?D_C>+3utjt^
zOL`(U3mE_{Uli<pL@aoNnN9X5BobtQPa*|LAxV$iO9L36G+$Myy|3vomqZI&6<ECd
zrWbhxL6<9$y>(7rSS^{(zkj)QrIK%0%tN`_n<QI#`F>DI&K&U99MPq-lM)-=I%{(f
z&e~2<_)PPs!2JuK_0}xu%URNsGkzz1&hDGrl5Qr&Bxklc;dRNcX?8soKXJ#L<+|%v
zI%b@2C7v_v2`6CRiaKVmC-f;b(m}DRef(R?yu2XUw--b-J=Vs5RDZ(CF%Mi*dT+P2
zul|dLFJzXeT=EuKCFo#+Ja<0{<6uG9`)Wb~`@E`saMNnaXn8lRg@;-qR`rme+EuV`
z%U_f{-Q~cFmdS7~W*BrkqLv~vsi*erzn!nHWeH|JwuhVA?>8yYJ-pX8Yl0n+sCwzt
z-k<bd`bK9ii+?}A^tdgjUiigiKS6E|oIMy8SVw~=Fz98_Do-xZv7yvJ9tfE<nR8mH
zLWN9WJyNL>+gQu#P$DY@O*!PRg+C;D{0rf%=Q_DKv)j$z=#n%B2593HMUU9`YPZst
z8jDJy+L)Sex$mTleagv=r$_9vdo(*%Ri$viBHC1VuU+m-O;t;w=Wa}mSG{WSn5#B8
zr91O#Dyzn#sh`{bw^!*{xx&4489*DsjFXHV3cnSQ=i=+Xz%1Y5c4fVyDG&u4q()U6
z9jGIy7z%RwB$HXn5j3fCz1eDhFlsWFQ@rj`Q`wf>5~TJ*)h4o>E)^`3zjn)K>xoHR
iFV`_OCnqG)#zY7El>=C{7u@-&*4(vk-1vH8;r|0yj0x=k

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/Catacomb.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/Catacomb.sv
deleted file mode 100644
index 2ce725e5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/Catacomb.sv	
+++ /dev/null
@@ -1,192 +0,0 @@
-//============================================================================
-//  Arcade: Catacomb
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module Catacomb(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"Catacomb;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian catacomb(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,  btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/galaxian.vhd
deleted file mode 100644
index 08fc21b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,446 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
--- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 5a4d0094..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 87a5b3b1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,74 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000000";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_video.vhd
deleted file mode 100644
index d06e75ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,433 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1H VID-Rom
-	k_rom : entity work.GALAXIAN_1H 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
-	-- 1K VID-Rom
-	h_rom : entity work.GALAXIAN_1K
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qpf
deleted file mode 100644
index 48fab33d..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 21:51:58  January 08, 2018
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "21:51:58  January 08, 2018"
-
-# Revisions
-
-PROJECT_REVISION = "ChewingGum"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qsf
deleted file mode 100644
index 8543d295..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.qsf	
+++ /dev/null
@@ -1,187 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 09:12:33  May 10, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		ChewingGum_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY ChewingGum_MiST
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# -----------------------------
-# start ENTITY(ChewingGum_MiST)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(ChewingGum_MiST)
-# ---------------------------
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/ChewingGum_MiST.sv
-set_global_assignment -name VHDL_FILE rtl/tripledrawpoker.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/prog.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/k.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/h.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/col.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.srf
deleted file mode 100644
index 4ecca971..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/ChewingGum.srf	
+++ /dev/null
@@ -1,57 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 113015 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 113007 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/README.txt
deleted file mode 100644
index 233da2d4..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: ChewingGum port to MiST by Gehstock
--- 16 Mar 2019
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        	: add 1 Coin
---   Up        		: add 10 Coin
---   Left		: increase Bet
---   Right		: decrease Bet
---   SPACE/Fire 	: Start
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/Release/ChewingGum.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/Release/ChewingGum.rbf
deleted file mode 100644
index ce29a3966e8e24d84b232b65b35589ee6333d1b4..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 271799
zcmeFa3w#{cb>Ba`Sjj7!ws%KsWDL{v?r_TvVLeEQbr3eGcNPN)l;8-I)s$^qi=^Fr
zR5y+uN!!$Es+q;WT1H?9%5tJKP7G3vtJF#Ku$;L6*cBmDvC=3J<v5Mnrm>`^P5z(!
zQ-MrU(~fQZzrQ;>z%E`Q$W=m>dr0ie+~>LHo_p>&XYQT*^2=+(hrVXu&;RPr|LPmx
zICbXCx4!lDZ~fJ`&wT6K-+1}kU;oybuYdCl@a=DW;~T&Azt=A4|N2-92!Zyi?t5@<
z6v(xpJ$D**K3A2O2imXgbu7J4>q^6GKmerSy6SnopmN$FEq}FZT3;Hkys9$|*LA%(
zD1AE)x=+hr?V8q?#w(A?NyE?enwEFA*R-BAz3>pEV=xVWrR!?x6`sP<G8C?`rPl^<
zDWGc>P#WQ+t3Y8(A&FW1ReYK@4Nb$+=k(ehu6jk2G)`B=3)1@s0o~VuG+fUqC`_Q|
z<Sw~S<I`(<T>E_*udBjSoYFM47NqgI3YY7FG%md=T=%-Bkj9Mx>AkKhM|Hd&(AX9z
zECtbJ1E4fN0VvNn5CaNVyq?9!Yr(aE;zwJca#HYtz7}MbKoL;TR14B*<@pkDH=rot
zbD{;m0kq$@Kd0g8HN{~BP?_!gCmJYT*8*SzYOg?HDI_7uukg@adR3csudBiZx>r~V
z3QO@w>r2N++TOIT^r}4K5#dz=()@~7A1c4X{u7Y$z;Qrf?Vzv}(r~3u@6-Bp6%VA4
z;+3{R@o76$p6Z_kn!r=Qmw~jN)vnJ2X<S;ru6u!U3sjFlc<8ENU4IFf1}cDXQ=X>*
zh5sa=I6ePC3v{1C8m8+X0`1QeOJD{N%?09z<gQQ<4g!q{fx=UIXw0SKOZ3pQXrik?
z_j_89gd}1A6?hI%)Dko%RDOH?dKT@z8xS6PPT><RP`G$QG!_4+efLoy9S>`bm9MlQ
zO{;QJylw(iUy4(DO>xjQ#Y6WFa66zPg~u^KSCy@>w2rg6s_r`h;iG;R@2QT}U}Fo?
zc(vhuz$QRZ!c))U56Lz``+X8JKK{R3kjAP0{cSMR0vFJ&qI93aue3nVgMhA|0z`*)
zXs3<B{|HFqMW6eC^jTMpUxDyZp9|7)tE+HP|ENA)H9mxj;>4%QD?Sh|DXhg8tM!rU
zZwJ*UNH9u%laS>1Kej+mDZNBu;g&*5^Y*Lg-wujve{RP?_v-hRa7e=r0;(^?O}zDO
zAjLsfJ--sP%MsnDV<o+&^{sYI>r3N>yV{n9i(JA%VJW;4PKr<KPp_I|)3LCWHmX~)
zQ=ogvj}HKU42ah>|LQ89OyMtDpl98t;ptUlY!Xm;X_&@sJ1DLl)b{r01fxZqgtzcW
z;or4D&%#kWs&S<HbbSmEZn{rFVUkHHY+C_DGu4&CCjrTe^jY&!irY%pXMjV1_*3zk
zpVBaeKMtr&(O5c(;2PlaC7`er6eS!4!bAFi@YLLKe+$xiSaXd)amiis`=>2f8YVmh
zKiq=NZIIUAeii<LG)#Di_YHFVh-dYjLi;#f>0Zu{mjLyD3c{xijTLVnYJu=j0->*R
z6fFEi`}X=$d~|IOUwWV7kcxTHHPt~RKU0ug6-Y-DC|u8)tG*BDZ^6$4dY0ay>&<|0
z&{gpF0bLa)5I)i$Q#?dp-KS$CC5E0QzjT#8B$+1ASbr-ZUHA8ZRIk?c$u(f9jQ?MN
z!csiatLkfq6t@&F(fyYJrAcX}`A2jR=spEKi!SZgrS~aci4G}f45WIR+OE1%JQSzr
zL`&PSK{VO|C`@y(<eNbKDiLx8pg4v73?RK_7od3QYNDmWq@$%{P3aWA8)(N#bqh3J
zbyb|MDqkSl2y`#qQCHRT=@#hz7Xe*mi%GZFReIvT1$3W=={W`QTnggB6jZk$#Y5sw
z&nZop;-U7b?i5nIBr{|m>v~TMehc{77NlX4W$$f)Xz(#W*Ax_`d*L9^JRuOiNk|fw
z_MK>@`}8WkO!v0|R|ATB51_Dg&b$iHd@j%!mYyLVSPRm;qKEiEyd>V&yrKC;pyyWt
z&6$EUoyw6cOW`v>Dz9`^csg!$RhtC5e<z^p-v-1h0^y;n#<H%G6AIH+&jQ^mECq$B
zUj)KOZIu3;+T*&W{gZ~h8F&YfhO6Ih0Td?C{H15fE9ub!-M=45o|4~o*{Z%%{q2y}
zC!A79!*o?W0^JKIwc&RG@l^_XUJ56dz_UPmP&*E~7w@I@>#F($x|a+Se@V7V)(AB2
z|2v?t6!iQ`AR4uU#;nF>3aW1<_$HvS*B&QbLa<Vp!oS)A-LD7Q%j@0uDA1!oj{;{)
z0m(nf(~k6Ehr78WYK4c=lCZ}=VYIup(4g&powv^%+OW<Xt0$lT2fLR<);fH~OCr~P
zod0HrY+pO^E5+XRmP=kK$yvuQZ{=BMU7oP}h&lL&MfI_g$8W)~O2}{BA|{1emOI}f
zsE`Y@wq+Qo<|>~umzy~<Hw#%zsi11P)<bt?O_nsjxdv7_OMdPPan7QUf=caxnVU$G
zLb;L|Xye@Z;QtFN8EaN`pL9Q1daFy)iK1oIO1W9rv8~bE^*K^Z1Y>n;AX6*d3^rEH
zRx0wC1fhGhXa)Y2_4;6z;`<-1=VptxW&NYSm9ff4ntSTQ?m#B=_PDd;4My$kU{;xL
z`?Lli>BfXxy{LkdQC7}aq1v(lYLmEFG%7bTBAR8*)b*>(&2o;+jcQ0TzY=Dj|D87|
zsw;4TGg?>LXj$DK0X@Xdo&r4{J9}CsDcdP#gu!|XXiq=?siW<W=Xc*5N$aIwk77NF
ztv~?{@x}__=Mq%QT>bN}riOhkIJNRzEZkp~vey+TJ@bW2yHbz}fy*vj%+_b2u0@mL
zpZx^U<qW1qr5<IiYF*m%NPax&6+6sWMHgEI>tk!q+7=&=O=;`SU_JiFUF&D{&01|*
zUmWACdma6qKfAul*GheX3jjF7GDa+XVYS%8I?urQU;l<Ef+<{s7ZXFS#fj$|`1q&a
ztV!e5DEjg@+gFaftvXnFcIYwRb@jXXi}7vVV}9j}Q+Iiv>bKu_X3G6g<=Hzw|Kw4d
zwBLWl;0yklk1EfStGg+_ZTN!C?q-F%JAUS)_3PayXyLJH^6=;#hPZ2S^V!FJ^^w<~
zed1S0iKOVBtUUQpn}6gLDt@KtZi}#2s_$&$i`GAzI@`3boUV%^tYkgZf7vV7xHJV0
zs}<q4_x<1G30mrdPMds}-CgCjr*@~5J*(@5I>@`OK%EseUMZ0osvkDXa9%0t*~KG$
zy27wEiT(NUzuUc;<h7`EpQ8X?rK>bFy3#q6e{mV{uZ9MTats~MQ+Z!8I~u*Ls}<wU
zGjQ9fvQ%xOQNOL~N(bLDB;E9FrJ?toxqJVIDsxk}ct`u~E5C%oE#(~TJJGL~Ufmas
zI)0&McTa+Qhr-=@c-z;yXS&Y6{nM+A)pH0&^fu2S+tMsGqi`2rdgOw8Kb*X|oxl6%
zmZE&_&s|iOFU$#Eq&at$D4}=<c~5?+tCnI%+2{4p?XK+BOljTznRBqARw2c?cjXEN
zcAH`=RB>)WT}JG}mDgS4G3x?%;B?KWy{Z#@{>Ogu+?Z{pTwP|sp4Pn*kyj6ENx7cZ
zoxJ$5N;^07yxraNcGph*!9QD_`PLhQtmuZ?ZK^Fi`zsgj8@u%qX4UjPC1zF9tP*k2
zP^@dJT50~p-&}>5=Mda&ec&8WSUJmuj9Ax{+pf#&3m3C)&m^z9-d(gF`q~BOC`!f(
zW1}ZdRu&tpg(l+UJblC~W`A{8nb4jUYdz0EInsOX?$wxO{o$}z*F>*89^ICf>u=FY
zIl8E<)iU!RI=oUH=N5J$YYXdd(O=gBjP+x-N{(|P|6kW)nywAZp1XUM?q4<docLmu
z(z+;oF6@nHUE|lTP9)a12I!boozz`Z$1jeh-4~S+f1bMPirHV2T6gK8f7jP@cWZG_
zcc66JTQ55wX&H2&G5>2%hF$YfCu{OL%0Ksq^O!~#*EyKY``|GD;h#TuOqS+656qSp
zbsmd3mKAkjPw*?Cdu~A&v`Tb71GAkR7uR~s_LiUfeV2!2*PM-3Z&T&^JN31=yu0hd
zyn8Iz+f;d8J1t*b#aolctFbtyx2dwXsdBxN_kz~0*4vns(i_|0<bUqYs%PV~{_xz=
zdTQsq$@Tf87w+5FrLA1eVZSup^5?7m(eki!4e7GhcdlqG&(}k2IZf6M=}~NL`Yey_
zKE*CpU$@@N&HvOgNxq!qXBkpDc`jS+S1J5LpOjw><@HtFPboUTN=Wxy-Q9C_U$A^%
zyzMRB{VK#N1AqO&-JcQGkHd;NdWfw^mNfz|WQujoGj&nD6JDdU*Adliso1S|7FKUz
z_d0s9m9(`*sB0@pR@L8o8!Fe`Io%#;>qcO;3@yZ7B@LEZS6qE^o`G6@%}RswEM>*)
zy$zMuchl3|F30`Vc<`*l=Rf}Q;os~Elf~sAok-9B#%DVNl2am<gq`K%?SJxr)7S7;
zY4n9I5m!NboxvBf;=RtMteU)*`EYM1!m89+G2(({eys>x5#w_S>}D%#r+(@JWwMq7
z=OS0T&xJo$%F}appQkGRT6A{TPJLu&Z#(7JRvHiI6n4Q2%X4bgvP|8aUwTJtEhFzM
z1zZfeZP(Xfz7kQ-Hom8HpDm>p(p|9PqNj8(^wHVgNa?QSSKdxp$n$Zu71i<R9J8GI
zKYwzzh`n;UZi~&Xy>q!(wr9fxE4YsJLA_<F_d1i#zr|i>j^#e+Rq>$kz0EElxpI{+
zPra%CD}V1X|HZ}~&R5>`n7_YqxBp>2;r*`X#>_Xo-}T%ceZ+fTbkKaoyZ^b5==7Za
z=XRRUcu&8?F**8-x2`WXPC4e>oc)bM$%njOdxdb8jt&F*$@=w4Yk0o#!8dkos9oqE
zWqoBSb~Y(4*a^3X*x7Vndzy=eV&$&AU%H6)Nwsszx!+$jJa+CRT9Olrb&p>;aU$#*
z^K&>Gn$U_XNP6n|l3qN^$DVrLQ_p+qxeg7QeyOLPpQX@PD_L*8U5h#^#q}t*5>?g;
z>o&!@r|$IB^R@bIg}82a<pt|Z=^l?=h=;f(J<G=kyX_=j>CpN_*T3!1n^xeba|`M=
z7j~_)FP_~et9qzc_AIYMYrmzEc~uMl=&R=WFTHdi+w-3<z7BYm74-IH<>w|x+H>(n
zPA^uv0=;v3)=kE4zYtwF0;^@{A+{Q2RtxV@Y&FWP7T%-SYLr<mJfYY+w2Jj4eaAn4
z-D>r&JG|Sf>benFEkh5n)hM%Cc#mSMQD(L99>rFp%xdA?rdZFiU5(N!hhNAuao2oh
zT{oOAT+F&^($#t|vn8Lp)!P@(H_2g~-eOY(?$(@T9hY;DzuKvv_xAdKHuARWRgPI@
zTHW%aX3^;fCJ)B9d5`(~CJ#>C<$bEZpGBurE{jfo`Agq_#UPgvE-%cT`AM>x<(a04
zWRYog%b8@=>1(i%`t@e*EKakl9JQu?{pt9>c5VLd{Ahe3yYlq6EVQ=DmuKfc^`jw7
z4b;xIsAXj@1QbsF$aL$Wx)8Yf%`1H;_TBs5xRCk0vAg9RubmI*F0^{RH{I4c*IWOp
z=`R|@x;D-)o;OgdGR=A;y3J(W(vN!IKU;54l3uS~P`7%EPJ4R#I=Kfi0OR!Zbja4z
z)7LON{yO#al!ebmEl$&RT(ABY*{-@k77D-c6zj6rXl7>{mdiiD4c9VEe2Wj!1^OxE
zl7H9cxQ}ywog@D0ez}yZ7b>~2A_h?K?*EmkdBuJ8E61$2R_goX@ykkAxVamhInUa<
zBQ71d_a<xH$zNSOam<SC;#KiqZ@PE-<FBuI8C5&~m-X3VJX8GD`|7pNMf)08+#26s
zo7-|NxJKENjUS1}qAxe@bB@R5X9rHi(ZK%5D{hLfymhEhd9ku@F>O7+b;mUAs$1jV
z<(#xn+-FZ`2kg1&ty>zqBln<vZS%6y5AF}<<DzF>IX1G#At|LsHZ+K9P50j7CemiV
zBbt1|zV@m3c=3v(rQ737_`8kI#y2_M*1&n{z5~U>_4jR!>Q7ak_n&K2PwgIE;H~q%
zxiG!B*sb&L{pIs++(H2tW-CGOqCu=%n*PP(30+{`^S<dalXcAi?{u`CZ!=L!FI>#R
z!~=M~Z6v==XT&Gm)$et@#+D+>t2zHuJ*#b<+|;w$R$g%3`;<q=mq}jbrN|fVr#vo{
zBh;4->u!5pmsN1C0X@XlOSy}JVi(mnY1hjEE2r<WioS9s=MZ|~ei`+G{Rm*;)c4I@
z>>9c_t&1#u@qD}!%kI3ts<*P1`)cnMeAO_oo%+g`d#j(?7IUrmR^=RI`^s6mBk^l3
zf5-ekxMk&P&LPwY)^o_Wa+Yq1r-EAg{-0jCl5+{|7Gh@Y*YX3>&jqC<Pqz?LX%~ea
z+|4P_P^{-fUl;dY$V}E9SG74_>zOa~t&1#cC5B|(!AzB0u%Gkjt$Z>(pz+ZYDQgXf
zWpR*9s?EwO_IftXT2?J$)x}JmD#j^MrM`AQhuzzuuw=u<iaL7tBx~uJFI>9Fo6+L!
zIo-YE<E`&`ob_IZHL58-GxRE)LSJpKQKsg(z`Nh}`c<>la;ruyjbNP<@bG<qO@~ef
zOY2|#Ioa-U!+#(}afMXtXyZcemp&x>raRDmeJtsUCD^f2ZM`u6AHTTXEUTx-PU_l7
z@9j}oozAPobf3#ssc5~y7p%uxE}yP(thD~HTQZ|mICahSJ!g6?GykE(Jym^u1Fom4
zuWY6Cmb>(pyJ#f!mb<J&o+O&}kDaUK(NU9e+FA2=|6E7tst>BVx@v4I;yeG_E2TL5
z_`eZ9zwDJ)G(Z2t;%@b`Z_dgoyQwAi*1N1s<26G6MtE!ueA1}yy!}i|>t-u2OzT0z
zws_ZDFR5MJ`-qK5zwNCX(vCmhYj45J`McO(vkP7<Fz<aE`<1?peZE6%A%B-NfyB8w
zZ~xvx!RLF^rS&c?ukXovcfZtXOBeQQr99h$EuTL&3EK+MT`kC!*$r%7YXyXu&BKNs
zk+QL7M(->N&5Uj7jA4t60;6T$wSCb`zpGfHIGgN&iUE|`k5qC_e%=})*Q~%%98jjj
z*tWJgl<1hmmhCL0xbgR2Cz}|=z`_p#pF2~yiUOiSDYs2X6mp|^D=6ena8FV}9O>5y
zGqq;M>K}G2hZd^BFv_Sk#^L_e-_g4dhyjAhFO90@YPqU1mubytK2VGmLn1#QJ5`bx
zP|JX@qGA_-N@DZyj*lulp{2PlBmt`+DT0O;a=z(;7P&~oTS@--4SC;a=x%aG+=BLP
zFE9A&w7J_vi7X4y3QNja2sOx(eHqM`u2~XR6W*01a4zY@r2K?wh-kH(rY?X7wOWrS
zhugvz5||rbnAUQI01|>HPp$GztQy|0v#rC90?Zj3x4*5gocB9R>v&RJ(o^lh&U8{#
zTB5lY^c9t;H2+`rnND9!zd*%BtSGkC+9X-oH;Pl3fw5x8;g|mlB`E19KlBQ#J4^>H
z*07LSH)YBa84`dL)))R1&QAlDUTb6Uj}-&_(3lOa78sJ5#PLG6wDPLy)}eb_I13m0
zK%Wd~WhEJR21hZkfN^E6=BEbn_ySFfkPD-YxaZwPIlyDh43h<(Atb567m-YhVpE{n
z>$JMOoz%LYZ~k$TCdr!In_m;KSa@fAtKhcepraPgzw@rNZH&8CJl8@lVMGdyK-@3n
zBgvpv``hJ}!O%Xw&`0Jun*Ro`@L=v0fO_~AL(M7WYNgzX+E|c_8T^ZwD~mmyDbG1}
zY?m`}xstIR{t;Xj%5)_{f=@8~VPC^^i|EQ<`ky31Q(?Y^uqJ#ijz;r^@iFR@hyX1J
zq9#dfPi8D9ru+02p;|s|2hAYO{N`Ij#Hfli=qA62r-G1A{)<!m+MYm{i8u;sr46;4
zV{6L98>y?|6=p<0riwUH*G5*q1J^LRO^bw0@$u&_qgJ6YF?wCS<c;1O)b0#!4z}h-
zbLD)~8qGzcH=nQwwoeAT1FL8f1-a^V!RUSUiC{F>h?-nBkSwsCd|#T(Egkfx^0hn1
z@>_3iS_6;Vx4SvsJW`y>I|G@C<{^Z?74AOZZhW?RQ`4%}XX*nPYa~COpJ*nB`5dZB
z>;fvb{g05Gs!jjQqex**1hi1WHL^_QO)hJq$=wviS_7)xo@hdVL(%T0Wz80C0+M@+
z>Mar*G4s%!dH~w%9i@AhR_!mO@JDm-2ZR!4Pbb(}*3_P+$^-*dOJ&x)<M3n+RCYJZ
zyM@{UknSDd2gzv#h_p3O_X=64OIX!R`(xb_&1m6<B+!3pv#H$~*xd||6s@T<jyMer
zoK~yT+NZ`cUp>?!cpA2NRdt1=Cb2m6BsjHF%ofF5DG$@XgqsdF@v(K=6-XqtYB?a%
zB=RKL`0GeRsq~ahFOiKhjjpp;Y-Ihw*(hcmMN-Ucaq*90BNIRct)7V0T`&FkrCbBG
zX!&9zT56R%a<qTJs3YlYaXb&c1Abnp+i+R!$aa%~N{+|esk-?;yPt8_QAsUlVwIv*
zbs?`>qNkml<UJ#1dF7EQPk5FyEtJf}YR!M^|6Q8JUsy7=LP3kQcCM~UliD3?u1a4$
zed%l6*!t}6nL|E@KfBv}7M1IZjZ^x#>u3G_4Ze^1QzLKN@vi5_zW!77x0T-Y+@7!B
zy`N9S9-O+xJIWVhKl1rCUxz$+tol7nasuD{BB=r92#IV0k=VKPDV6JS62}}+bI=d^
zoBJZi{MgQ9RGD+4xExg?0@2MEp*HsHwU;#(pU>hhVZ!AJ%Mt;9dPCSImJ<F-k}|a>
z$b<MYNR%D8C5l>k!VKd?JSbn+4eiT*Itn$TpV>_W>O_pE*yP6)aiE9+I|NA;5N77z
zuO&NXRG6r?pFkvTdrogv0g6PsE|Er2>O0>5dMif1M;2jU_`<B<1o<eS<;>^=2#Fv_
zvfJo=zIB3Bl3zl!Fvd)4heak--^-BnK-9=M?t*M2)mZ+kS1hbS3w?*2mfz3l4kD6;
z8MFsAS|th%i}D4Mej16wz_DV{YC+@m%94)Wbk?&xXXxsCl}ikQ&f!F&0&R(F8-r55
z>|<Z521=!fLf$WPes&OBmNDPRW2+5?TO*3(i%+)db=<*L8&r{#R1{BEPJR7OQ?!Vo
z-V4ZyhJ^}4A*ds{sU4*VUT0Q@!K;2gA{_N4UqhS)(s_)=JYDqsW>Ff7>Fqd1mq*ts
zXKP+!(uFeR=6@U&l%@cYNJ4T5PSv6WkLI_QOD;xvDrX{Lw#`w&?VwPR)7ZJ+Gi2Hz
zl8~GKV3-%BC&nncUt_e8i`5hAUzw!j^i7d5l{&{A_?@5wS+uOkDHn|{XRG`K-aRJo
zra?skrc1f{%;>aIK^E0PYuzB_4V$At>OsG1o2eR#B&C8J@c8#$W>6MwQIScD{xOy>
zX99Z{2`E1x6?BFj9b(B9kc@Bx<%~k4helouzqu9~FLj~fI-#Thv0r%Fpe7at!(3!C
zQd!xTIp@^I?oaGGDpEgN)?Pp6w?A*tCrnHTDQwy)YlXjT*cWD8+bU-#kJywt|L@H=
zxeBGEFKGZI5((`7+#JLTGgBqBCM$>wIY&ek(oPI2dl@D|XfjhK2xmfEc*>(<Y7O^A
zmM1j&^RDgjnKr6I^ZNCw(zn1*Z<b$8u_l;mMEVus<&wVI92nL!(zw-`Ne3^Mkz}U2
zw6hmVgI^Zzxtag?ck!#n6kY0dbMUT;Q6eZ17q{dKd8b;Zq~SDtB!leP*NB}$UJ)qJ
zP{(8_XA4dxYuPn7$a`*E#LJs=s5rhHJ`>TFJ%<PFyj`tV-x(<PjnKc4M@=bb&|r%0
zTaLJe{1uhp(RvPK=40xO$ZcUE)tt&r#lfuAij7vtO#Mm8;ZTxy${0UeUnlfMGe)}F
zt6_)9#m#uaW(l8zk?CRy3eqQmZD9(8k;+-Z1oL-%!SD}yJ~aFedoUYW)oX>iHS#B7
zEU~3;JAqZWqjJRM?eLOF-?{<qFo{Jt>^DT&7K<n*ZyBSdaH>+F;Lu+dd;3@W)WtL?
zEN-pC@vR=j%hKw?!d6f<{q#i=E+mFbNvL`+4ZSG>LDSo&?-cxxpAqTNVHw8<vM{F9
zy_12){6d7&e;~_PKU|l0?LD+tify5E42qD)TGZ?&n$T1FX-!>hJ#6P7GoKhtNd9xz
zGEY%I)QC%Or@@wWWnC<CJpM@vtvy9zY6z_5k%a(^lB~67-+I)g?P*pB8D>;)9LWx8
z%L~!Q&xpHBwO9X(H*s4iRpE_=u@E$frQjL-j8UON-x>m^!G$VLLWQ?cm_o#6lTon(
zQPTb}wzu`^>xhIQTJqTE$w1+K$|bOa<O(KgP|`JNkgmc8$r-D64Ltu@bQ}~Jk~&`T
zeyUDE^G0A=Zn(IWgQ=0Zg;6j`Ll?m{QW!NN6Ne4jlfb`xge%zMgH0<;6bAGhpD2k#
z8zHF<gyrb?U}KIZq=`ual>soOL9r9>)x_0`zUA9}-{D@}e_zF|UK{*C^}687dj0lz
zY&iZ>b9^|Sah&L$VjPt=RlM&g?rc<wj||;6l4khc_y=#T-Z=i8Tg_e9j7NTS`l)!N
zd3bpickL|s15xpFj_-`UP;A^;JhIubi|-uyt{<tK-tWKFt-lyN_0eljpNKo~a+YOz
z*uAg5<<b3dlHs-^%)O(GLtld^ng}9jfEHqH6I)F%6bm_IY#~2d%0oQO!Iz7J7PCN~
zwj6uiIs{ZvCVYwvZdn<&xVdNSeD&JH`yt%Oef7duuFV~czxWh$(zG+Z-HGulos24z
z#eMd0>Fw?hMD_ipt(TJY6ZLKJl_yS)4Ns5fqo?!nq@TwN^>$~-DQ<~Io~`Wf_f+ah
zcgKmXxsm7U8_vDd=-%%#rS@I1`J;9BzNE~*xaLno^mXKL6dfrtBUcQMh)<RSW(Tqr
znP6i#w{f>p&br>L8@dht9d*N_F7$1|SAYCX_CSTgjZ4kcmPReVIs>4=59Qm=Y%#2K
z;1jx8*Bi`wTs>}FDBpq`Z`Fh)f89WZtZO#IcJPJR1LzHoW4CE)6ctjwW)#Y9(1!9t
z1-JjqWdj*zJ(Y~qT$qc}`WLSu4S-52nFi}F8Fpz3&q6n`Jk$~{Etq!#ro!2xFcN9Q
zH9A2K1=)X0ebkheV6KR1{(JgqqmB2__g*r9*@!<gtf-gG)Z3A<?ZFn=#SKv2Or&jb
z>Fr|YhNt%rLrghU4Bc&ITpfApKT;%pnM4B>Rgo5HuJ8;r2^WaYl>Te~*eH;WSPslP
zd#fX}CDNHBPT648iAcgS6y7FMsqW>YZxTHrICI_Fd=r9lMI9SvnEK$hHh^zjmp;`n
zSY#T@`{c_x`V-PnINb|=YjBR~S-eGfrRc3r7G^|&IE07&`GHa`IOM#Z(E?fywS*bl
zrqkA_12%&VVEtrBrlpwcAR~8{fBX-*UF>DcyYY%QQGrHHMP0}p|BWxPqlC5x$qIUa
z@e)C_4u6FOgAO*bG(_@3buQ%dZu`LN81qKR&?97Av&Yd=)pnb4?3iJ(P!Kn23S@&=
z9(~g`mc3g(dzl4~ltB$GShck0>%2GJ2E8;akr^E+%XElG;Y<SAw({q{{jU)a`p~3<
z1n9`oS+?Oh5FstYVo6HT-(xJa_d|F(_!q50)Ay)LN?dqUkrF5j%nYpEfrV$4k5YQr
zXk^Q6GW63s;cPfas4vB4p<La}QZmJZ2}Fb}?UAB**`-vEE?yi8^S}PPa5l^UM<9sS
z5<!yr%o2zy^{pAxZ52>HjH6LDm}M|8$cpgv{oo=i0m+LjSc`8+qS3|Q62eeVGOLI*
zX{F(dA9$mg7?npF@#;VdaiS?dT9OdN#pm8&ay5m7r(e1YE);WNwL+UElWKcS5S(Nr
zV%SO4fy^R=u8VZ=;Cah4ecOr(Pk*UMC)pv%xl(}8TNQ*l3{Mv^&O0j5nDxSj=3S<i
zwh<ei-uhkyDA<#M!s)#w8QW_UTak!~G~u1LI0Q79^NR@W9IkgA?W3PGuWE9CMWI0X
zM)F7^a7WAAYC#&fNK&Zfl|`~NDm;DUMg}c&wW$aGNn@5@neEg@TB7N$qjU?VH#5MX
znz4{|{s*oOr8dAk!fLJQop;&lUAmcu@?R!e8>oXJPiVM*0ej}Lx4?O@A47mvv}IU&
zD;)r~H*Z3OPaAlt*3%I3vy8Ka$gBVS5+Nm0nxV50vFyg7Z?U?Tv6*HR+>?^X(oxz_
z|2O{>);5jKlts-oC{HSehz)-l5_P2XB#AvE7c5ET6tnR3FMUuwrkPtAq`RhZ%dd%U
zMM5(qJ1Q^}qcEol(o<UCJ@cX0LvT&M%tKm<kj5;(O7R4Lk|=q5yaYYCgEw7E`6<kQ
z=cwTTI#v8YE7F)1uA)8CK|;TiiemLLED!dK-o?@%`bgfgBp(>Qu$+2sHIQDRW}0!{
zkqAu|uD8k!rt~(<t*h_F{lr+Lp@~wzM(M}}GnC2@k-zrxnM^2{KN!-bjx;Vj{S$MV
zmesMS!fN>HfFwxx7t(ihDwCkf_mFK=qIoNY`5XQ-#aG~YWo24qbft02t`ZudItR%~
zj!skt!5RV0khMAp^b9kY2Do^EKiaWmuy<C|!bKcxBtu6m)TbSwFWImVGyl!+h4n$6
zKXW4{U5H(F!&GFZToRcf*3n>Efb^H};U<KaQkeh7AVX5*5$i4Ky)==zl0*Xl43Otb
zG&_x6hOP88?5?(sn1AHA#Tsg~vMsTuI?A`y1)BP8gsf54JEB3FqQ#=Lp<^0;^z+Ox
zAg?Z7OY)=n&`x!*x@@V86KzZf>)O@=>!+`$Xb6v4rCK_WYJV^sB!x|;0y#S3n6r+G
z^3s?Wr5g&x)!$5P3uwda-JWOZJ#<8U2YpmR;nNP9S40zvmIkp9H9vZNOWl)f!8%+6
zf9WNr1JnZ3hR!;~{)X<N)S_-^-S*!uQJ+cYprfgSzXb%A-6+<K1%nPf(vemY&eVcH
z!i;aU^~3FVY$zk+w4%UJqJzGj)tE`rV59C>GEE|g7|<}2+5*om66>Y=Uk82kA4$0;
zp+q04=PgUSy><#@eCfaXWU=r=mm^!C56y<qng~}1MT2)FCQbUJJ*}C8rRaiuVpXQG
z-bXJrY|Z?)wm=1gq{GA%OEHm)2K5SwEj1!7n>CY;*@vXJoQr|W@6<x%PfDWp1ZB*3
zx>vFYMXOCg`RdcWS29ekLDs<$?fJP!KuON3SC=v~Gnq!N>Y((6eDm-BA!G6|bD)K;
ziFz3p))0$e<c0jY35`C8Y?F?qnIMIiK9*zJ*0e6pTmxi%(kY04O{pEsr9PaM0V=w;
z8=}Ae3x>l~@S5z%tYyf-d~HbIjs_Y@iyV~QhWMdp-(YMO=>(nVwCCntdZVZjLY5`!
ziy=428<*9hK$w5Kh6RN}a53VN0y`feIT9`8Uwe4D!DNN1CYz!SY47(x44Y6Y93Vxq
zJxk~Pf{EHmX&e`(WK=2S<U%)kkKcC*m<m}*K=~Fsi)(+9kPgvxMUBq3$$Eg=5X1%R
z#VK~;ADU?+8PaQEoj5a+(X-5iV=Pjx1|^K5+XbYa*^vvSNQsK6p1%;e<OZKcr6L8v
zs0!$g9Ykc@HxRkhf{;;t3%OtVyKi95k$Nooz7V{^jfMkSk?Ek$gcJy$Gdro8qiqeC
z@Bcjb7&e2^J6WN#2E?JdCat3_GE|93mh3_;X{7hgzbjKxZIxyr9dC{9Ma3~nuY~kc
zWkNFs&MzuK%*a?ws|ZiO{U6f>a?4fV3mUUV4U{Y?1}&v`cCrvE6y2*v7-6u;L*8xw
zT(v<~1mrTrQasF6_PIC|LDqqVgqUOuoZqG>KmUPCHKL@{tt}myDAY4(`lh26s}#|h
zGh|z}bLD)g1lvm|hNO$BSG<#hpwfXXxg=POxhA*5LN@P~e}73*BEm6*mltA|-Kejb
z-AE^!tqq_<GE>Muw@BmppWRBwz~9i%B3oOIWw*p4;1J~<F=lj1Zgq?u@2)@2LSBi(
z@|vP0(X1U~a4o4{)+IP;^31l4oOgWu%}^NjHZM*ja#sf^46}9e8%1W#ykHy#?P{I(
z(&;>epq&i&wF@SVuw9Y}CPTs|zY9pc<MVG65A&Zc2|J0mkVrSil9wz%7)KrH@H!*J
zHP|uCz`cDGZrp|CV9YCi8HENqa(7gcSmjB222}#>DUgDR(#tQ^8CYP&@bm|-Y^x5H
zEv<PeTXYn;kVuC6Dp}g=g;N)>SR4o5T|bs<%Zwmdcv^!8+Ur|2OM86?)rH#Kv>D;)
zU%Rf?@HM(GB~)@n{4MrPdk?fTX0ONLvmUE6+<If&>IpX^F{DZ^N{&vU(*D#gQ&!E=
zlj;nu-gG7@oAOR?9#2Nss%ltDsN~w4$066MwCX7^Jq0E)7J3RyPk~7km!1M6{jFz@
zcg~}F>Zz=};qK|`OGih~Na-0ViNCRDr1Y$_o^`h1|5@^$seMB2nWe97vsACCdK<VB
zj@CQh-UhDT2CjDbmfrI!xKd%ggkBt*HSlQ!SFN^VH5{*v+h1Y#HgNSeaILu_g2hDI
z$ilinEuQMM(_yII1}^jujMTP)rri_04P4sd)1i^E1d6qPy$xJ&iWVUEHgL5MnU4G3
z2Cg+%U-mX|b#Tk#LvI7uvIU}x#9?td6FABt%U*jMxZ3E_c?$(mbb1@OI;pbw)Z4(t
z%5K)kv%tSo7hWV0cZ%(8;99<Is+~wI&`)-IaMi1>&W(LWhwg3Q>TTdkSw^eewV$oG
zfh(nmHVGv6+FY;z?5^)^;OcGQTGNC;#p!L}S{N~HH_S!aanswtWoVLYSX#PMr?-J?
zkzslpxE5*Ac87dPUQEBXUpw|TaILYJxvjgo?e%z%)msZ%JCxD(y^-xJ*A{k&_VzLL
z_AxEa6`ew*{i(MawznEK;gb%(Tf0o@?Of~aT$3u&+j?(i;#IeywTsoB=C(GidRz8-
zTlRWe_F597r>pmL^`5TYp?`MHr9C61XQcFul*KX8v(9>Z6?=OXlksp-o28H-@;R)v
zKj+kPI#SNxRw{GA;)ZQ{w*8nGdz&+Npg1<>a7<W*wc{M&HaeE)e7Cq(y4B}k)jVg&
z68#jfXp_T0+2+DIeXUO<PG`4ps3XVV)y5vQ!@elm8@*%WB^(}Uj!KPdIU+bF&9)<p
zBV2P9=a~BCVocQ>U&@)J(;43mMsQy1Y-tX@^PRGvSLK`p$U2Lfm(|IIwXr7azjTgT
z!E@PUQz<^>aR8ueO;;j6|Iqj9B-E)~SPXLhB+K7x&Ny{C&U?Tz_RU8#r#P~%Ob|_r
zW=fo`YMroXB<HjReEgCVPC3c6oP5yH<_OSOYdrQ+1FstG7<0V=ihMNEo{xV~ge2|4
zhmScskN^Fg<=1)Ko*x$i+DO6XE2b2v6ZG=&@ni)FzippXCUWM>g<M3Bk-h~woRL#l
zImEUV;HxHI4@sg_DQcba+DgSmIZdt4Ty<Fx#}TI-->>Cy$tQ9HzZR5&pyX`4zce@c
zRB3$s#^^w0yK{iEg-N9~VTGV12plJP-`MEb*x1cual}cq2l&P+|66+u2=V;<G$%+;
z?u+;zM|y|PW~hq!TCWG51$bwyS*a9njV2E}@pt_9MI_Jn?yk4!q|{E}<@ve6L%-8!
zjnWw3s-7s^>PI6m6Gu+wd`ff}L_sY-n)eIw?s(4cFXer|5R3)4M!|6hzI|UD_Xiy5
zTVfPVh<9jpJ`OVn^kGvc=1ALS6n)H#4cD-kYO<2G1MnmzpZ1KblON27#Vgq7Q?ob3
z_T0EXp4Lqd`?g<e`d%?tE{<*dL7)CVQOntdCW9e2QyR(Cc9eq1DpYAX>{HHwFbCt>
zWuFvrB+hj#crJl*)CUv))__=qQ`<8d1am}jP;N9%lex=T?{R#FBqP=uMHq}RhV!*O
zam-=4j95<06>~+p9LO+QIV09#tPD+NL#m1`&fzUzPC-0rxLe=z+ms1XmLFy`%qW8a
z)Sr)o8e)QTf}_zqt%>xJ-?)V)7fzj22^tQJz?wP!Sf^N1ZXCheaUAaFY)YbGv+(r4
z`g)qR!jYJfIB#4c1w;as;)&S8$p>#b(~SNkOX1cA&t^<PVtUR}7tU}txI&R{ly=vz
zaVoNbLfzp|$H<BzA7RHB&skAzLqy+u4H`kOKzCmi@W+5v8RqEWX!3H?a`Kid{zfEj
zSY&9IAwXOkMkK}7WY#5<cgq&OXFtmMsv8Ppv}G!1bD(ulhPuIlVz9wKzVSqSLW2EZ
z$>Ow4G23*p8O?13ondeC-W|ztr-2bjwOc8;*385;Mqwt*JdJ$J+jGdO7|AFJvKOrN
zt$oM3?eB1cxKJ0$Ihs8Kb0Wb5I6ugjvwkdEkTg~>bQ(uIbMCgz0|khP%FGfJI%_Az
zgy~n-;d+=fZ@uIrtVcD$XgU!15~dbEs`hRl!g2yMWYK}cF)}wf<N7#k76~`Q+@u#K
z&|0&FCZiZ!L-D?4y*zN4Ril=uR_8o$&Yh0pX+K9ApMNxlnFl5(KczYSOiwc&`H;;C
zKH^altJn%B(OPln)8R1zNw5W~^WXnNdiMF#Tt~|^fr__tI#3?ODZW)=)JjS5h8Z|*
zx^>_*O){-;;%#b>fU}#ysxbURV%!#(T;>O+Htdw(-ikKm#|A$-G~rr?hfam1SqoDG
z*o<Xv`Au^~d{Q_(Oogp_MA_B@oCT(kCr3xAA%;>k$J8E2)^tWyC%?KQZ#4g7cZ<3y
z)&?EloVu$N3Hfv*Yz@YGFkog#=r|^^0JLIN!b3mz#(<0Xiz}27HY6lTVFTn&=&VdB
zD2C`L(v(L}AYb7|<b~mwg41N?63>&a#-wk3^@ZFb(ki5uYf%CfB{?xXDcXbzwN?)p
zbP|M<1g1=LJOBTDFb&cbu1FZpR7d~=*HAR!4_^Uk`ZytK1gA0NlY{E%L_y5o%m0>p
z=Ar;<2oR+$zDS-q_qUXkMFRfUm`4m*p`3_UK#hXEb#8h{NwJa7Tu21T;^@AspIw|%
zH9>I9I~rudb36p&N$IL>3QfeH3Uc7EK$OU^ahW<2d_?I4=ACbw!-IXA3!l(O2KPCB
z&6B94UIt@`8Y@%4M0X-EB8Tx}y7PV~I*{q-4B*LP-sUXiNQx`N&5oP{hs|kC${1^I
zf_zhV48EQsHFq1d3591)P!s3{F$W$SCJ1r?6v)Htg<xYoo*<&&+&l(NG?Ya*&X=Ea
zoS5kuU5A5o5oHB$U&P^k+u<&qdQ5g|jcd<co&oLTzj`%}(0ZNRsKX>WM{Rq?eEnHd
zHwS3rM$U4sGom&a%}<OI_mn@;gsWTsIdDFjE%rNk6bYsX6xjUUC{k$1RKscXB7S7}
zp!nbZ=LGGr?Bk`;T;Yyt5M`~YkBsdJw%*)~M{{>Kr<(bxJx@cJiRP2<3+$=qPV5e>
zk9+mQ-b7IQ$k>Lh!Jek|(LK#3Cwou8U{QH@)8Qz0w{*}W<iWe+nR;vuJo1SQCkn?b
z((?1s-QYQupDljed$IUzQ>U`e+{7^mBl&S1_s;k%pZcvoQkP5wqX?561ew|s)b=z-
zbM(TVr-^y;=D;ANTAL6)2Pq?Kf)o=0v^YUHw;+|U*=+F;YQof>CJ1mkIS-Ivwm6j^
z*xlqOqXRf}G`X02DnEbAjizR+c5?s@;L+q4a!fHQ_MCuk_kh^co)fBKG>2?a<@`{B
zg661}i9}sOh^&O9YC=>2)xk<4fZ7NY^7H@WKbdx_GPReVI5G`Ls)zK}D1Q?HWyMc|
zMN=fSp4>ou4H6JVW7Poq6-b%{L(o7|714wV0bpt@^S!&tsaDohooP3tc?#yG5C|m{
znN*qhS|bazpaE1@1rP$Xo&3Nlw0;<wrcimL9)POkHq_J&_=+#D-glY05_<ZoO+m(R
zi(?)P?KG}PoYJuXeaGoZ6(n|5Ed!4@#r*9KrK%H^Peep_T&PV$6x<&E-)~S=s?oG=
zf=-@j(zOgZVNNAnMjdq>r3ugE57webH%v5rwMVTqnW#)6ii?_)^qwA-M%p6z-~H%i
zVu!$TsItZ=O3$_jB_W7}o*28?qvbPo%9&`6i*eO;5&9X=B~QFMQzz{~lvq__h3LVi
ztf~76pJ*PO<|nCm{$snCA8I-BS|t@5ZB=WYihY`<ywbsHK~zU)^0z{T<HACd6Inp9
z<k1vU+j#ysB#bRSLxE@@LWbtnDpiw3okTxB{9~6YyMu^I+lKieQj!3TGy_4~+DuYP
zIu6aEl1D~xqr>CzJaW%;J28|)nyqohvKaQJxurw*=K8<#_a5_KY~0~|<z0{Y`x|%r
zA0Bzzj(0sbcIKn?x0T-Y+@3Rc@Bh%g=-|{X-qHU4=RWfJCy(0w&+UAS%ckj<h9C2}
z#=5@PIOW8*akIa1$UpPZ*H$5a@uWBS!rYmktY2@M;~lGB<){_)>mR);H7Ei<fNC0)
z%#ch~Sp3N(j!xO}Zv!Smq~1$<MS2V?=XETn8CU$Y4x|v*0Ht?dh43=a3TZv9bTQ*0
zi73;PE5M<@ylgzfq!yqb)^Z?yVkG0A5U$(AP7`A&3^E#+F#S1Wfxs4U=@h<(QZDeZ
ziI~Tw-lEnse{Yiq1*0IY-P(Y&91LkP*oCpD^t}`qx%kW#uN(1YDgY1&tL%h^1Kz8o
zfwaFcb~C&^hBiPDvj?*&TE1_xkcs&lm6%O~SaY@fHp-34nXpdU8VWm442c`J^l7S2
znq`Qu89Y`<m^r~TUCUuCsV&l{4V`4VVuMT1pgoFe#V}+Ia$yD(WnFQE7Nb8CJyX5J
z+LiIG{(xFhAh1=yDm`|E+<3M!IvtKN3pU#37-lTjw`Qu_M2<o;TN}eW<5>qdkSy$*
z&Pt@%({+aRK$UZDWCKN*!mbrhHco%={m@4AWd<K}CNqI;1z0n_&I)w3m(mc3EFx+d
z6lYP8U3toQY{(q5Z9ZG$xsYL)a_zlz5$QbY&dA_~4lapK?tX)XcM;x&#2X7<G0xOt
z%J*qTxlzebpm0}#lpNY5#hSNWd$xjr4ZxOy9DCYzBe&1m<dr|>SVJ|O0-Ot+iQQT=
z%6Z~*G%(xCVyMk;|6$A8R+6x^g9FiA$@1ypy-}@N$)E;eS>wVi<#_h<aai1g(uR|w
zQt>gc!;G`ncPFFl^u1S1XHX%rjpBj*5jy1z4HHw+xX{ke!7N0{JhMFe0PN!G454_-
zna}=_n&IanSOec9!+{}Zi+#X{F7S0j4{jhC?#IHdk*gvrIwFVCB1is9RTpC)gDw!=
z?jSnh%8X>UT!Q@Pg!<pTpE$}x*Q9vn0J=(SMUPOVQOX@M2uYq}eo!fD!&gv`de@X~
zl7<v#nxfiFleoV7H(qDes28YFe62*&G0|HBB=ngzC?R1Jh$;lj*?yJ0H*)OAps0A;
zis(a)O7J2;zkG9~Vn5~m;jeM8j@NICMBJlV$`fS5soUqKKQB*|kfq$cjX1*lJ6&(W
zhcm+lb;t5%E6S0yje~Zwu!MKRuUiemV5&mS4$`f`Wf}TZVnD^WVByw|h6n<MFcPH!
z9c)In1iaGx{lAmk8V?k=q5r`&H`g>JOqeu}6!dR7<6^gE3u8?oM-RlVrc6U}F10-0
z?I~wJ`Qw+-jSKk<i4)>rr;sd(spYs$ADl2jQxiQyo^h|EwoD65Jz^{fciWfW<Re5i
zg*bMBzNIJ_MkST~q&!ooW*KucQ$?d7jYJesc0~?otMNkdRNrcUIUBn5vF7P3|FWFf
zR@zpw>=B<=3e`x-60~U_K1qb4^3f;>F@5|BydaGL(TKE!FC(3(1tS^1wp@bD3gTDE
zF1-4Ot}%x>s!L%O!<`9z0&q2;gR@$<ix-%e2duFc>xU6Ns-SXKM4JDvKV8=JsG>}9
z#49uOQX<i6u~5?oW~f>W({kNI0wk^s9Gwj%rxrmiPZO=$9p8L|GK29#&q9b6VSGPH
z%Wr6^Oddl{`b_TNX-H&h7a;_Zey;xQH#V5w9j6e)QIy%W&$s&#uQ{k!%h9%=CJ%kC
zfR|ovPytDm3{z8DNXS5T#_J#UyaTS?%*N3@6_mN@eT|r@(ThGnJ=72ta0^i3G#?5=
z%GFNYhd<2ezpvDv3&yE6aCT|)y>B5@bNx)^G;Ui7wM8>+kYH|?=Lm6pGZOatfrlQ0
z!?2v4%;0n>dX319Z1AcSy&**7;C4^a&*{(iV@NyGR3GnccsM}ev>!e3=1mB;{!$fV
z+OhSg{^2!^7#D>j`7auY5Wf1eoQ*v<@I4oIoX3gs*@7%(`pJ!_nhn0cag}p7T6KQ#
z1C!KiENHA~N{A!c4BO3AZrSpBY+8u+o)X5^=ymndfSnughXVBcV7Ax@y*nWHq#tas
zgVAc{Jtf|172QomCa7xtVfz<~q<ZV|nC<m5*iz1oKHoUYI8O06mg?-#CcEx!{b?um
zcK&djAAhhoS!~)57USEUGn%KTGXtj`2WvdahA$kc<led4v9`s>nGv>mwFlk7o0_wm
zAODYU7|oUMD9IkWIj{#X-!TB<jEsQMoDRujP~K4V!&4<(09d?WfjO6)OXx#B#CUnP
zQtKvT?aapRkX=4nyr-y>XEQFFS7k|K2@U>k6Km75Ce0~%+=y4h)3^Q~%7Z|oIn_RT
ztVksTs(&D}fWW3wkRX6b8pBrLb)-0&n}s@<tqBqt`pckT*F5)QPULbVt9!DU8O%D?
z<g>WXEzHqjb+7FF)C%PwKi+CvgQpw6IuSIi>wH;hAc3hiP|Qi-2nox+&gTtdDQC-Y
zoY1VGK=mNhFxa3OB~(eS;1@PFXLL~D&L74m9XwjJp4Z34u+R=of{b-f>R*t>#zBR$
zt^VHkoeZGPdmyz%Coq@#q)aM95cmP4#`>>{0tB1dNid7*LwABVUn_%-kbBm(rkcEE
zL<kJJyPF<MS*$~m>~U-M8i}HL$7%UDR6kw8_q?9})}?Tj{0^ppqJwEZ*q{iYp@gRT
zSm;xR(t-yU*P;H?a7cmxC5!k_*~?D*UUn1FVTNbRHJq@sj{=OPzN{O@?(CqzMBohg
zkeqHYq_+mds<TC(Kd_?vD?(U|AiOy}k9O`nO6BGUYE+LvXHKIXJi2+nf6yHma;6@1
zcRrvLe+~%<@$(ORUxq*IvYE3MJTKm0Jr7al|Mk%t%|TiO@K<Tzfg;G%zH+Vj^H_0U
zF2=_IkGwEf%ndL|EC-|_lTPQGj^0-n>1T^rw`RnOQmTEhZ!`wAvFL%zO~}LUr)(#J
zO(=0NdnhVC=$h9=w_|{1Wx`M8Q#)M@%j5Gu@wyY1JznIk9^9g7RtCG{P!sc3f1b%G
z%!ER@q081P&(U1Wbk2OAnWc*dGinhxyh&HIO!_!PqRW_x(U~(Avi1Htvn*CP^GHm;
z-8KBWpUP7ndTBYMYH<f3D??@(UR2a_yx5TcfT#QF2v-wM9Dai~=K#ij&0+4aFe9)z
z9FqZae_xc^`$*5@l~4ZbH!idIZ`=Nu|AEPa@oifl^Y=|2{P<nor!e*RoSAa5{D1lP
zzyFFsE+brIB9FYSI{1Qbu8ECIz?L(K>2C`0Od(U9g?wqHLcZ}U<XxkXLpRC!@IrLj
zGv0?y-a~hO{`WA@y@!TAtLrblH2jylG2Gj+xuJ#4&c}9jV)LuFuIj}Y{G*uCj=j`o
z_MiS|H<lr>fLH7b|8f?ysc{4(ar%`!NiV1{yiwP`qm{uUt^Ws@Inkf!aTHI=Yn4k{
z1k{c9YvclDL_m#RUk%D|<8n}e3ng;*x#`z6VP0Nc1h~}8MdX^jtt8Vb%AmUkrUaCd
zL^tE@I0$D0+bu_K)|#zYQP>yuxy<+Ftiz*Ct+N$`ImS8GF^W`-)9}^?s^DY>wYipm
z%b9!LXF0xK-d=)GXacIk!A^lW<@+)fO3$$+`TK*MFb-%f3R_gkM#PjG45O@c*hy)E
zO!E<<0rF71v>lmxWSD>OMI$50!Az``G3Xm3v@6v!6(MPC0G+0i4Tq`>lQ83X&MYct
zTxJk@)^KQ=8ftRYG>Q5_d!iYqyuU$}@#DYnW;-lad4oVn_5o_(t-VG*y~xmHn0rpd
zEku+d#vM@@K4q6^&l|}){mn)tsx+|Rxw?JW=f`zu?hB2~mi#Qr4|<I!T#*wV4Mvbh
zE_FFy-Lhd@Nfgc_Y<TmIje<)+u7C`rr){)OYH)<G;I%Nf5EVnW;${ZWq@1{H=X}s2
z2L?bH=~J@8$s-j@f~!*Di=>=*8dI0+aM14LTqVp>cHg^qzHX)z&*9R^+mo2R5yDKC
ziQ}Qwh8gr!8IY<NT0!)flFMi@cn2s6)!N$<7rn|*X{IzZ2ycZA^uwbS%esM%A3O}}
zR2zMJBinI@2O91JcCFb!e~cP^2d?oBV0hTx{D1i{+)#1(&QacuQFY^}|9+?6!6Sk3
zjGi_rxvDV|gE}3~aw2>z;l2i(((fIy-Qi(lr|`&Y_$YKMn;V<^Sh{2T^x);yXcBjf
z<sNWh3wowfX~4gzO*lE|b(n*fc3-=UvA`NCF`E;|_^*Z}*uw}B3gM~TQWqN+mUR!B
zHkQ7J=3a(TFtuT%as?zUnq;{{^lTYX?t-mOjn{7mD<!O;JXzK=kG;w6r**Lv7WJ-E
zzFUzMXwlhdKRRri(oNl(Dl{N$Sj9DtDJoF6_CbhAn>X<|Mr?P;DL;XN&cqA7Y0&)V
z?`+vY1!s&maboI7ZVCf*vALp&Ys7)+QFNn5R-q>}b~qr{vWA?IObjnsKK6pJVFYR9
zFb-X?vaRBwzmILhts=|&L<~TVtv2AP72q&}TBFvK)WF_@6_HPd&FDmUIvZIL^=}#T
z+>w0o(BqfI(6CipNWuC8%%GrPGw`{PF$qSH0E3w!YlIN0^J9%q!jw~f@rZ20A&rS1
z|HPY3J4~7CZBQr+UDE{QWvenZ04E15tC0?U+^|y5h4k})n+-K!EN`3})o0CCNCGoB
z_`{55e)W!As|Dp~PQs+s1~Mu=K=BDMCJ;0(bjSvUYL*(XB8cW6{8Njw<5{Pi9aag9
zcLOow`a6D4Lp`b?Jj@#q^24ySmM%*ul++~A0SE<oEr#JFv95`9CBe%XNUv6hR7gsG
zG;h892^n4sP=-WNlmuWiQbG$<sPb50JtwXq*bV2ZR7<l5$)QrhC{h(9E8BUDS`yuI
z7qcPlA=KbaPy(hQWrZ35eUfuZwrK|?$bN7<pU!thYFFV(4EZ%?LT0!5O=C%B-q)LA
zBu^n9$<!D8H(f&YhFY36U{gj>O_p>}t7gi5B6WDAQtqRYS~ZIRhXF8SDX*NtiBg1%
zPmTWZ@lpiqn3kB9s$Q5#Na1Rx73HKI^r-8K0B*US3!I>KtTOIqh6!#Mt$>!;0XP6~
zRx1-ey!p5Puf6^xf|+9dd|B_hDHHmulc`ytRzO`G6I99*w;p8Ryz3*(D3cG^$E(t0
z_Ks}%ppVe7?Jd>K;4)Vl9?V=-f^)s0@%?oQjlg!`XvLlxc5$x6<-P&;3D3p-H~;iM
zp=jI4LmNSAW=iTJh^BG{ZPiX031?_9%~lYYM=P}3-B%Ap*iF^`>f{l7_=bu@HN)O;
zf4sS}&mXb}_K(bzTyIm=b2*XzfeM~(&6)3dkgjHx)c%I+9+1BK_|Ii<*Q>gaKIAPt
zx9~gENdFr;Xyy_vk~qo?p}oiawYk2d>UhDfqc+4ItYBeoFNHiT{JBq*{NbT;<49#8
z2%cpM!-{aN;@f|AuWxO_LbI`r?f5OcWIwW<r+zoL6?1Q3I}U<!rhpegrW7VsvGQUu
z%FY&f4PVFFyTMWX!=CGVM=|?04`yet@pcEBiiP0V=ITiGQTtQH(bBPNej;<#vH4QT
ze|Y$JgWd691M9Gy2{4U{nN8S3*Hr6+kK*2#bsy&4e-rzB@KJBl_fC7xfz0Kn?!S#W
z{$VGBnG+VBJjQB_sKCCHe9+<VP|FAaagZn}PR09ml-CVWBeT=Z`uGrLuc>_{I67nn
z9`+xLBQaNfEYzczjx#0SBJ1pCENAG<+wviM%5yjS8GQHFJ2t*yQ;CU(>a8f6E%G|V
z5JMa!tIoopR0m@E2`B2u!ov;VYOWc?3FntH&)1JuWD7n}tR34fr%5n7<OH1GKALlb
z+3lFBcuV?b-Eg;@10Y~yx9@Z_?oJSR|8LKf8hUZ8H|8-Wrg@c3(_t0JkhGsixCDY2
zmy7~Y6^jV`A)$sF22|(@s=}|~&u-`59U9Hey8i4niO*u^W}0Bj2!6yty*P-Bal$V*
zd0+B)@pU8O0w^$Bj4b?IQ_R^^rfM>xoH^(XCN&sPg&Kq<i;gDq+p~5?^%BmUQnlh&
zk6z<ET*UyF6<#<d+uV2MHsGboV4o;A*uX!6RX)|^s&aNx&gJ>}@BRZO@=eCugq<!$
zN*_a$d^PlDwDTzCgAM^Lbpx@3*#YDsr6Ne(+OZ;P=RgroprWg)5DT0C7~Tljq7RQn
zEy%&dLV|3wLoA5^x2e1{(R2qhVPhm;dgkz@yD}%6^t;>_j#(@K(-=;WRWFoz)Nr*H
zm_bbv9V~0-5tm8o2A9sgv7U8C|DsyOEuHvlw8moKy#Z*reh90|Zvy7>8?p9awg}z5
zqu2E3-9yn2GY-D<7i$}gch5S=5N6RriNw4o#~DEj=3o@v#8e7?wFqLSZ}HJ>jUR^A
zivl%<G$eS~z0?Ay<1rP2gBOqHcH-7>od6=LZ18wzouB8UXP<)hc#?L`IgvNOfSrHl
zn@m}U9c$WW-NaagTS=|}D%Kl&x(h5|4{Az~2<O1dlinsG)ieWHR|W$}CKmq;WP|dv
zai;u&U(D5LP0ft&t>|gCJ)Ym$fFg6e{EIU4zyHC#2Tc1Cr-9vCrC{+6DG{2g5@i}x
zsK_iTK<#r;P#78bCAbn3_^v(P%=YKXbti`yC3Kir@$<}nDNW;f*TMoTXA7tP$q()I
z|I8TwX1zgm%a5An2OSpsgY8a;FMa=&azeb9i<}VeJv%4F5>G~_6GF}hd<Wn76$&#>
zh);ETGLGHW?#VdgeOxObHhI6SQeKF@oGyXbxpWBx0qsj5{>rSQIODZDM9BV;Z$9bW
zqm>jaJ-A0pDZD?D6C!@edu%LOO7Y-hyH1bXw|7i^E)WZ<_r-@TSh(|Cs7>cf_mR#E
zp>-oA2~aXdO%$j9c*(<(g)^W0X(Ey&O13scD@B{?l8E`A*)<z6!=qR`PnD)4mbJ@c
z4!+v5z!Vf>pP+#=q)|nfY@`rj5Al-R9?y7J@m?EqV|$6H?am}~dlcc5aCs9_o8Ipu
zl!k|DxnU^)@UJ@*Rw_p-7OAYTa)bbz7ZsoU9tH?9OO&EqbfJg^hhT&(fd(P^P{b=O
z1{K8-R?bZNIj>)q<N#VVik^$Yg4Lv2d2x=BRlyt*(b4wHS&~9lRHG8QH&*)R9_q6l
zUv^J_@KmY4={GSlX|n8kX4iZ1T#l=r6!u0m+xBp#ke@)_kC!X>)dx`_El)33g5myL
z*yo@P4n~ueY*>jf?8~&zalAqka-datw0_H}%AcX1W6|OCb7IWP<IXrF-HeUHJLKs3
zI$K0=Qo1N6-guPVl^xA*$@P1gLKR)io<;Y;XJAFa4YoT|vd8OjpY2cg1>RMqVOdZi
z<?PDfG#PJfr-lAirIF|X-Ul9G!$_mAT<xQk?&aAny!-XSsPV|JUvePBZVZ`_+JP`t
z&D2WI#hF4L>SOrZGo><4Yuh?eXdbZ#VU5`Ke23R$Tk;NqFnfS`+_MKG7EW4hzi4Cz
zGrZd>AJsdpBNey2|B2`Q?51j29N}UuOlDwm3n62{=u$Xcd`52h^ymK0Yz6J+yQKwM
z{`BFE@xhYg%#@;juTdlyHoa}{+V4XFi?>E6wm8*_+c%ksoZ<dzw7q2C19zdK!hU}2
zLihNK+2f_c#$z_>vJ|v&Tqr{&dlymRHCOcC_ubB}$-_JBca2qts^fE2*TLoOZf>}Z
z$*7v;l`RTOgs)|~ftCK#yTb@KiO;%d92Yar({Oln80XyFbd)&=h4K;XJzJr__crj6
zRPHSuzzy|*D2$HS78_Q|(Gxp{p08)@A=|-D@O@NfIHEuHH}C@Ra(l#`tV9);{XGY=
z*G+D!GEhc7He9GaQFVroGj4{b=|E=?p1#R-4rGVJ=z&VP;vTIG&42ipLcClM4T&GZ
zJ4lONtenso5v83;UP6U-DQ|77GET<wlTl@VLmKl9sEJyv?D<C5cO6C~I~Xucv9i2!
zWp3DV#~Tbrd|JlGa3IUd4s3CH@<7&|AN`k>&8h-d)+H9pamaxapfzHtmQ@EieCf|K
zPs!Y25aTmp7MZEqUhP;V%+_+h*%t&GQ7f>(i`v5!Wy3xe<uUbPUs^-xoSr+-xWsX1
z;Ur8(C!Eau@eppzi1P3z7xs)<c+7dx83!Sqz{})jX2gh$TAYarF($s*DT7utgnzJ*
zV_q~8r2I&!QHhG!obF83$5M>Jm%f9kMGXeIR_jRo&i}y&wD`;TeldFND8PU-Yo=iK
z@TS<-yU2&D8O{EM{P7Zk6&qUfYa!>>;_anfS!*H&OAv%2W!KgMCETn-)|S9HkdRB5
zt5Vwe0}bcpcU&Tof}b@L(YcTrC}(Q9*qSL79>g&gjgPSK%oP<RQ*C#I9bycxV-?gi
z`40<hEetbzeYO^&Li7hs+3D6uW-#$t(XcX}4~$f1daK-b`RU28Q5a;6%JSvV<%Sdy
z&lL)z6qv<kF}&!cZpN2KZ)SXlsX;D5<RGS=?^NeXwY<kGncVYHgS3&lN|gbKN@R8M
z-BVeX4B<m#5eicYbTNHL|1efWVgxo;W)@wvkQ-!|Ku(!0FL3;@!Ga{ae7HobN=-i)
z%S92EP9@{pBTsDfagI%uK3I>-#-)RSh~;cCk61$pB$(Lse*X7Z3qv(xQ@@NB?dOq}
z+R_n2@Mh!knC3e{#9QuirII1Atm=7mcNK&93FO3a_94;0+Hh%a9VbcPZVAR>m{}TM
z+EU?5o9F-GHG89Sv8lmGH4q4=V3Q#wc^l7GT&HlX!V)*!kum(@**RV$I3c4<F15%S
z4*SGKECP61Y!F!e@f{^f16()cDkm?-u#0aHH#TD|`|W*VRit?wQvj=&a)Fl5A1{%f
zUbVJ(+no`AxC;4W&4A#UDI+QIDuX{b+kTiuAv}<Y18W!-*Br`n17>&;f+5KKQ^B_o
zWg(kp9D6V`zv)U*k2eD}i;DHHpAD^2eH@>t5@XW}s4R^9Dwfk;pPsfc!7Vp*VIXU$
zpJ34se2&_~c0ZIjQKjd|l5wR2DF%l6Hoi=}WO^k4g<=y9J<Hh{oYmRE%;aSDfRGMc
z_EWLrz;iWBc@2R&YuGS^$Tn!<%~I*Gu}$|f?oF?XLs4!t_s{>#Z?eBoyDBq?<$Y1V
z<5k#SS=Qc&VJh3r8wVWkOg_#RqwPB;KjUTW;r?4EznHP3Xew?XVUF0f_;3kl^w7xW
z>_FqNH`2Iw$3V6gf2M@!_I>A`%E8jW(2nS7w5Q2^k#7$<6Y(b882Insb*mo_v67_!
z{wh-f=!<<K-WM=Uv62^QNk{OH8L$5AZ(Qmeh}gBua!ls{-BWBn8%Ln~n}?mCf8&Ph
zSQj_8XKeD`Vb>?V{yFdP#%)e~;BfWn$svcy3{LV38@`xvU1s-zx;L49xLWy4b$itf
zMn1M<W`{pgxzjtbW8};6vvKi9ogL2fcAP(b&diSK!=;hpjvXh);mp31v0ZhMbIz~>
zS0W=^k8xL-+<$p^w1TGVe(9ZzxM^GfaTM-j?Cy)Ea!mOSFFPZ%4@0jGj$UquFQUH8
zR<=CXEFRnbu03NTjTaC<$Ls+=K6<$vMg952;e*r1oh%-!xZ}lm^9b&sP2SWes)Lo?
zW4`S4(lL7^Gv3(e``(~_oJ}R)b6Ht3JQN`bW*2=$((qK|MkK{-<*Sds$$Hqquwxqs
z)}7<LWw^Sjc+d7H^8<7Cm*U`^yAMUX@u56(Aj47<mM=W$-gAu;51t+#9>}<d8Z0Nd
zX7IfSpD!LMMzhzjG-dG7p|5F`!Tcwj=j%U#eiv!2#i0l<fQxUY@RmO+-r+c(t7fmb
zWBh%=JAI0OdiI)sn;9HDRoeLEFHt%RA+B&wIU9KybyIWn*yUGwhuJwYZ0-D_U3cG!
zAU=A{$Ymg74L<5TP>ctU;@22F{crBJ;^$#end;6IJ7p+%y3Fo?@ngkJiLZn=?<|0E
z{Rcs(k{NiyJLt@A?`NZob4Wgh2a4FhgIXWJh60w@F=b%S4&LeHcjEN&Sw6(8e_7x=
zH}7ta#w@FNa>LF^+Ex55?Du=FVRg;agT>M6BVJ>7Fz}gSTdVnZ_JvssmxFN|@Rkze
zeE#KMwOE#cC}SQU9go5BW?rG42yF1g&x98OcZ5gL^CI$bFP`0esPW#X@HqGblUi_K
zR&m_n<W-t$;eP=~%=N(s@Us*rnm8RYQ)9>IE%t~|O!<zDx$tPQd|H;tJua(Rc7BFk
z6Lhu~uO#%7E5;%b&XNkn&QxyuS8|MqbZmJz+1x!I*x-C~u+5nYSi^wN0_T<7CWCHf
z7Ftc)`Qf`GhC0ayHj@yd?#7pKkp807u+OZ^nRWfy%?{p~3H)E%2X;U0I}=a)_>UT=
zN>COb43(R`EdIa?llX$b5t87%c>q@t)$&k2DmrerE`Rh3uh)tecuPArXzhjqJ8{4X
zB=!Wz{4zUvJXhHddj0spU{^-V!0u@lm=yN}u!5GZ;3cEXAysX&QY?!T(87b~;)Z+j
zM3r?LbG{u%ppbD-#u@d?pnJF!*7KvshOS~=CJr=Q6@#u=d^6IE#U41d;8L;W=N>{u
z_#8gX2*jSIrl}kYS;}+pj`255ZOjeKmHa_mpwsfZuzG5=`a+c9CH0N<qt`%YoV=SE
z%!5ZOQn!518a-z3%my?ZC(&kF8_-$^jsIw%n5R7!TnIn9_}nl;a9#m;AdQy^#LV@#
ze;saOf?*B~AjQ+8>;UoE$23~S2{thuxb`kzYog*OyeCWXk)f##EW7c{Y8<T?vt}>%
z16M0wMswb1uAIfU>5K9K^?{hf3_3>(pJiuQYsn8)Xq4f94jY--3bPOWZ4^&1eyMaB
zjK&PivZR{_`f!igtf7JPawnh4Pmp!u1Q?EvRU1V-nG-m4MswDOp;3TiI%Ex$R^d27
z*)GM6K7aP|058^V{HRai^nn25UN)X}u}_)-j?N5Qh-%SIO@@xvu-NRN(fn;$-}3>8
zqCvq=aPxrbDhBLEnF})q<B-{0Qzlvh9!V@&6quQ7nQM>7D3@m21VxmrQ7`M9tfM5^
z$KzeuK-<_YBr#6#qYGZKa`q&zaKlEO5sYH~_*Lj%EXF;KS{Kted#a>q;-AJ$F!4cj
zj0gwX-bTdALrhN+#1Rw+_pmY-Gmm3y=v~24{9D6@IR0Q}>b`3oHZkBv+lw;k=e=5P
z7Tn!h1dnBA_9HgrV?!XIeP^v(9=v4Pnwy1PHrM~`S?;nq_7a|@#5J_wV!FX>)%ixp
zRvlK&uy98%ruMx$zeMic#=$iF*_HR|e7#l5*I9G3!crM6xM|z)^V!|44L_gl@OGW~
zXx+4@RmjJ0*=lwTec{RWT|?fnzhxHf-1Lu<GQ9s;I=%VRbnpV8aw9PH1Nl%gd4HP0
z;=(k=h>~3-eild1z_&RoV%vM1wdYPmamb8s{9FgCT-Xx;Ytau$dX@R^>tRdAW+$|s
zYl^eV{NjS?OtH$-$<Zv^r`a|-(XiQ*YR^S}jrq|TsbnY<)w5QuH~knnh@h**KFetL
z`g}`bSA=Pw>CcT+SbUBB7mU{*w4*J}!_`UuKBu3!>n3X+>QT<wydMurFoZ2#y4&CD
zvkW*3EoLi|eOs!P3i~Zw4C`{Gk;TaJ>`y;LV^0WM)+9tIr?RuG2&YNlVY+h9J2&R4
zx?{(FjRiX_8pfp**1b&aitK^Rt_EH@Mk31-cU7Y3UI*(u%=pGvmt}8EG>r~ccG>5K
zUFq3-S!o(YnewUMoGavFhEo+Q#2Iy*5}W;E9}HrUVF4@#2W#cLLhvIVE0#Bu4>Rn>
z8TQ75hMxzquqzXcXKT}LUo_*5T%LE{GhFj<jTN#Or@UY1ZBDMgnw`{pxIVP+Z98~t
zp~hS8u*XUz7VZBD@5MvL`wXtP!VmhsPw&gfq?VB*_IQPrw{R2-Od$UWRxO48{roy7
z<4VSIoo!VVO$SBrsjC0{6aEI4&(v~Z<pYgP)oBby`ye(l4uzpDIj?L7Iq&!|(+bXs
zu+QVvXzUiJ+*fY=kH#F2?z{iu5?Tc^HhmV*`4L{QVAt;0iCC47<;hCOp>aDmS!bp8
zwyIW4A<f)~Ehk>=Oje3xpYZTj@t%Lyrt^jmR!5?!GBg}VR_Ny^vv@eXA>>o!@y@oK
zMSO-MPkE3DLu0Ra<Q^M8&4JChb@Er&-!xE<>87Y~qU0Yh`PW5LJ4(L4YpxV)`_w*s
z7bl)aEWF_3D+=q?Y~b8bDf~z^ZwE0;T}E%Mm!a1P{P4s^cMA&im&dY0e8OkE-n`TK
z;1lCfX5<m)rZ^6dR3^W;qyN@9$M3(j(f?q@eZEl{$$9owe8+}%WTWHG0hcu<5sJMP
z+GC#I%uXJ$2O53eWMgQWucOdc0Ul&$8Z#t-i>_erHiJovkg&JxT@5$m)f^_PObn5l
zELO6oha8-Y{bN_W5Dhu@aXPm`hChh$SBW?Wt|^^xtdZSgZvS_)L}_5CRNmLv^1(VD
z)5$MZ?Oil^OYV4S5QBNnnYNpm0XJhm?BU_WD2=A0EX-GFZ29sZ_W8IOVuo}nUnsFo
zh|Oy9oWwqy?P}G9kGzNIGbQ?9hCzN^V{gOl$N#_%e>8>oxHrCgjKPSQ!J|;i;jHA<
zDwbm{=gG*GX@&`k3rBqy<_5B3@omL7!@|)C)_XBxaU@hT_6R+>OJmy({(s)y2S|?V
zzVqwu9nqr`Eba7;SMBiz>VDhWJdR)pJ3vr<Te5C?rdOCHhQS|FDJYgpyGx!8%TkG?
zbalE!75D4z6=n_t;|~!Vb>^KGOPr0m$R`k_9p;j=b{2~Wh@p~5$rr|UMF6O?nR8MC
zAzH^fyOMl<vw$qxvU7KJm6f==*qP~m{r>)bpZER!-be(3g~)g{g^U5-g<}h_PExzs
z36;3YDO_5oV=;V9>xUyk1gx1scBsQX5k6ZV-fLQjs8WZ4hcnA!mpWg6<bfWO#VKLB
zR=jBVU7T}VcZV4S7AJKMa-dwif+sta)!Uk>hPH^An0K&dk!7&&Wm&6%mTFLm)!=`o
z;7{VTGgc|M`t-LR=uLK*iuhw}#mRVKB*jf?<4jTIXEaYGF$)p-18!8nB;@Xyfkc62
zn3))*tj||a!b!Cx&Ci5dP@rM7WEEPfqzTB;L*Q9Y@UcZ@IG6$=m(vi>JBR))Pslwh
zr3EyMC4nI{qdY-c>B5G%GqWoNwdiWr_~SXZjTN{p4VXQcxbiWmQbM&@jAN~1qX*No
zp|o!@gqmVM(Da4CJ9s$)G`YNW=T|?;w7|W1F0V-Nof8Sl<Qn{kEWP`3F_xazyl&VM
zuz~azjD-fHSkCxaYMQqjo-Cc{RLj>ZC5mSirfoy520;c`7A9dlRH!5F!ElpWKdIhD
z6_1w)4wBB>rTyb#rCNediTsf=GESg2d{kQr1P~Mq2}*Ovjr_nZv9**=(*dCCDSY~r
z&W+1tMlWbUDCx#No);zArJ0x@gS3#dXijdFvaUT4uPmX-gsHGfmMB6Z!f9+)+IpGp
zY3Sj6Rw$rOW<V^y4NGBR8CA=Op0aE}oZzbT9xMV&h%C%iibMy+@_Wy3Qx^$Up0K>|
zd9FxQrO03{xH&x<4}?O9#52aYHcZjfS+f|UNAkGXa+WvqVl{IPcB~r?Wl1zM9jhr~
zBG?zU=YUpFg_SO6y3hVh^OZ02S&?EOz};lYNG3~62C{@wBNXZ^-HLyx*n*C!{Vx2`
zX*-R=NM)p|O*xu{do%+XS_YJL8lWjmaO;bX#S$PH)>5`h#2{kPGj|%_p>?=APsF3U
zF?}aRlSvviwz7C)(Aemet-7EC`%2mLM7EMF-wiWoXH^C@7IK4K2a?4E&L+2EZ^CAa
zg~wt#p}lyWsp`&+_efD`9|i@@LJh{`p(@EQBS9o3ndI*bAI2;%%AT8n)bb(6AH#+Q
zlMLdc%r->VF18d%nTaM&9oYdC*DH0b!G@NZfuPGffB3pJ1V&dE7OH!y-OAZ&vwEa}
zL2XvA#8Z!UhC;d|xXoRF(3}YSkF|DsH(*MSo334S*Mhb^-xEe{*yv%<ne5CII?vW>
z;2w+nmqUX(dnrpXv}Qh|H^c7o#tpUHzF}IQXw7`WM1)lB4^|#;%~a1;56GU&%4c-)
z&CXKWi~7M*W|{sK&#RjtcT}MZ14~bpv&-|o^xwaIJfXa^z3~!nj3vILkKu4EE()e2
zDh0#N7S6tuEwJ0PQhHe8#wO2I2bHsWzPA+T4m(kbb-$}_#V%7axT(RcqTHG~9X7i0
z9>T${D7SdhD;;a)PkXyCK@N8s$J+H__4<{m{XyQ?qZV4<ES~a;0AOSKYr(+Lxq<+`
zsLgUVgCa+%<;-^m%6Ve;ZIh1{>66txg$4Nvhzs$=KZ1LWNKe~NKxC^ZL10>yQ7jcq
zBRwA&(W=Y^w(J10T1=L<FxpZa*A({S^dm{i+N@eoI9E`dyU&>J=-11dH?iA$jPEm~
zSc&#Rl(uUFSYtXHeN(t(qyI$Xg>vZqZ?Am>NcPpK#4WCNL;H6>7k;~P%S<Gt?Lf4c
z#3_W`od5CkqU0R86pg6Wv;@f158p^?x6C6aX1)zUTS+bi+udWEJ3}znCK%`Wvxj;+
zFU++++N+<@3xKQ1*PwAYjm7G$JG#mF*;Uo7Ur-PJp#+cAUhN|+y109U+jiFuZPsra
zfY$s40Mg4h;tRV^=8yCVG(!qTJj{2!+OYyb)}LV3sru!C+^ha_kLw&48gf~0c>e4A
zj;;RqeEFDZKUtIvJkdMhK>%vAo{)<}*GT>$j|P~5A#Od{-N-Ym(<`qehmyJ7Q6k*v
zP-kZdy-5-Yi|WL4-{{$^yRVk&AkIgV`sHY%Ja?DKLVJ`ug!ezvtFr*Y_ju$6(6P6+
zn^3ZB+O9XWJR5HwztA|DBO^K<0OXbpUOsK}6hT+3yN?-&8PQ!)G+Dl*zl<P_tTm<<
zmkeGw=#Ju__E^~t4(3aIQ07Y*4&ceB=*Q9f97&S;^HGeF>4Z1juNucp98;>w)P)Af
zP|ZC}jiUOi@;#sRk~><P)!CEzVY&dNLr^2N`|7Ac+C+f?GrdAIMoIm4PCQ()OJ9Xb
zN-~@pT$pCN0#RM#vpjB1=;~T!5;QPv>Ejc}jP;8>6kR26Wn1&eKnT({`P8WP0V6$`
z&3Kat&<d*#F%5_MDx1cYsp93{p}~HL(7YE;!{R0m3=iF)&i8|dKIjc9C1RacXQ==x
zWmQQ*#yixv{8ATa7Fl)o$c<Gsa2d*U^PIk=rs*D*S)D)=ke#727;PdT|Kq>?L{Tl#
z5wMIUly9CLNXbxhwKPH_^cri9jkt~Ks>0nPRT{Q(OrN2Wch};_TRgIihE1vz;^yBr
z&s7g4iiAS^e;z2c4MTBlwlLJnsPoo0s`KUAV{vjbZ*_Rk!vj7k#8G697ZpJQJSec1
z3O$5T#e?*aKmla${Il=)@LfP{$v{g-y;*XmiLi=Fg&AIp)1^4R!`4SE)mf@HaKJ!E
zb%#zy`*Ncb1Q56%1$t4w{#qq{N&^F3`ptZCsCOyE30>RWtQKP;pYv6vB)pX>OpyJ_
zo$#V~NS+1VUM)TX>!oUV>Ez}%Mi}Mjkm+V1zfdS@u@-<1t*ani^mZ?ifv$F_NECUO
zY`Pw#clx9`JV@MQX8z4EtmTJp%wO2Oa%5A+=0&ByI<-=c=8y0%K*S1pobGrLMdiw$
zXz7DDFn|fN1+((80UHR3Kb%Umxq2j-qdHlY(=(8|uajR;<_6?opmN6hNrMRN|9SSE
zlR~+ndOTKD(+{D4ue3_S?A8nGE5rHH6V*q%de>CUdsY>7Fuy{je!GQO^Zl&{Ry>~W
zP!CZSbqmG=+)M2msYhXSF+F_nNnikj)*lwWn}kjgTf=zWOW>lS`BIbR2QRS7L$lz{
z<y!19_>iT2?Lc{clu552mv?!a^TzFT3p@FFnpgtjFuMj2)6CXUyArOs@uM{-?y?^I
znM#xycAd#<1Ak*`v+hiOw4)^LAB4^;HXn^x1e)as3)$$tR<OJj#NBzN!E7~Ik6`1r
zsWOvkB;*gyV7hTHf|WX&Mb5?ru)gxqn}!ez!c3D`#B45hAGvTa9HDXIH)D^k5!y11
z5|1B249IiGF97R$*s672uiI?zpnX1AjWD%9c~BJf5_t|~IU~D88J$kLoKrVO7O4k6
z4|7p)L<~u+9Dp@aiktB(|6w_GF6)242)p097t?l`pTF^yj}2H{|C&I(`=N2<=(#7f
zTOitR<rn{g(C$Bev|sBlW!1U+#ZTbpVLMvlmlx>Jo7G1<O(NvQV%{EN))mL%hrN|Y
z3;u5=&#}uGdmVmQ@)Oz9$nun!y5^&NoHw0d%8C>In;}?|P&6Xo+AWFPD<$#hMqA%T
zZo-|V?f3sAJ_WsX^kv5H{c_K6zW<)l&--usf!DC6?|r?0VVkRVMeeC0DSoMHh`N6m
z3up3`P7F06dK2>0vvac)!-YLO5rCGzQSIhSvGL}kY8P7DiN9II;q279hoGVUQgOJ0
z-G$QLtv%&cJJ0MGI47!IX0m0|2Y}ze6__dS^o-gy<t~5;3$wAq-Rw3n4+9mj&-@yc
z<+wYTjrxye{iR&oP}UrPUDnS?%lv=+5k5vx(Qii_WhLuXT*U!Sjwtu7wv9Vl#3KKJ
zX>T$@N}2?n+vdy0$7*Ta2>tAKwqzPBj~h1N4|c@MD;R1tkHM9ISyD`EUxppfcjoo7
zX})F{{O2MpW=miIDl$YBbtuin;HMt)iD`D&qBA`-8RmM$i)hR4u!=`qKz9tfHWS!j
z68~@q2xiY8DjMyfw~q|bX<!U<W_@YsUD8k=T#&~zLWU}(G&t?e7~8$l0)+*OnHP=g
zcC~sId7n}1Ud@5!t$R`AKd0l@vSH-6I%Nu!Dit5iqVYF>^MAF{^7Xh=T5wiM$x3J!
zq!~`0sU|s1=^>KAMQzW9H*o7z+fDZDNpSoYTZ^q`_@qWo=bI~`*BwjSOn>XBY83Za
zudaLkFdSrdE<qzm`&zHXj_)GcD>P8Sw0KB_2Y@9izI+Nl7+36gK&GHa{^n}U1t+J$
zIrd7?o_Np*VHJpekhBbJpJrzl%UHk=h?+-prsru)w2q)%KN!RNP>?I+Aa<mIh*Yyz
z#08>2tE-%dkD=##)<rx}tVh(1_WU!N2*g&TFLicvJ8ek(Q+e}~f9#vt-V=1n!nC5P
zWb)AtqqB0Yx=`7i@+MIk($BqxrvRGAgZ(Z$GqtSU+o-mekrD29Nse*4TEqwgTBQ>q
zx=RlUR)n0Z(O@oj30%uTy{c=LjHhOv(Ox=nj?@@l+;_|BW@{L#0tuU4ATHQhMLB6M
zdFtti(z?5}rweUxBlCBcQFrz2fx7#rf7jX@N?*Y$GLzv_)*pKC4zuZ-${%!W1e#=3
z-|WFAO{{0DC_eVH6^NKedB_Ldzi;QKr+7S5>77A>kzT2GaU5OJlNU2Dc+0U@44(IH
z4-Xd*-~Q9cU)1D_Uh7<RDU6E^Jh7Njs!w(R2qaz)A_7MT(`x!kq>cxOh;O6qI39rC
zp)`#_L-!AV(Zb`37?LLOp$$+B9DHaXzAS^xIL5-4vv<+-yps4RW$iR4vX|Kjf{6R9
zYL0u!12Cv!F~{;Mns8=+8qJ-E$pm33tFOj9x90S3XF(QUqZ0*C`r^)S{WJIlskJS)
z$b&dZ$~S@_I8-oV5qHA-#t}I+OR<rA;U<PH*qZdWG;q?>B%6Vh!2d~-u~9XtvzYm_
zVVWr*ZHX5s20k<Wmw}JxKfsJjg}6|v?R!yHIZYT;nc3OUWl?h^)_6fOZVAtl|H;#W
z7ymxIiv0xxb@d->jY}M<-9&p!%ExO}a2Zq%Dp>%hCQ8(Wb*xiZ4H%h&z#evj{1a!G
zA?`>+z4<r)@05Jq;3HAu#w<L-?2s*TPs)fT;{fL%85CoLJp3_{E>jraX{$zcp%Et6
zm0PBBT?uAG@|l3vc7@}mA$$_^141QaNiyY|UF;8}HoP|vE`R481JUqV2;z8`1w0py
z!%Z32?C7ZT0skhihD#eU<wDWYVA=4X<hmM7oIqDggS?mqz*Cmk9Xb0XMz4bhM7}f_
zV>*FX;eiB90aR|;OgVq+e|(@Pu&isN0kUPGP51%86d0BT3_3teI$8p$Uzs^<mIV3o
zcoZ*!a9PqDKsC}cxd6KiG^yuL1H>fCQAB6T(qG*n6^Wdbtk~-!0_QfEy6ggt^ixRi
zcy;u}GgFk2)DN7R(LK(DFn8cAGt}rN7*^B`O(Ys^I5_<tpM<KWRO9;f=rP}p<E@Ly
zI!-iNiASKgl#^Rp(g6H{vBSTJ8p~{-*W6eJgS0yDQ$C%qAR$edQ%=HMuwCVt1Fkw?
zO67^IpZQ(79|kYKHp5wzksvOCmsaCcNENe%#uI7jF>E!Lq$~M0)j`a+TrNV{Oj5KR
zrm4@Mz~W(eZ|YF}4sYN$xR>m|f#{pPS!OZo=0AL!h4b4i9W0XZZEZUSS~j<hGI05=
z65X3V(bz+3Cz}pRt@;j~ouN2-R97{V5lml2A-5R&OD!yp!Y$g;!ID_VG83@E%NJ$A
z!q!FZ-1*4Akf{dLOzg8f8YN=^rYlO<#s6imir+wydR;c__;6~Nl&BG%QKgF+<_4&i
zPtv2t5;_&Hjp|VX%jJD#3~a!1;Wb~MuG6aN+hdDu3>j@rl>L_Q#xC{Ig1Jj8iL|bu
zcc%Q5^2l=6pjfgy>0&8@ky*|8k~_(5rT*m)e1M8K&pdF(xbfr;JN9k%yAqC25Df}i
z>&YYuISC;^@!e+Vu2&nbiuHb0^bAvDI^b)AwTPm*sPTG%$tt~P0~REz4$WACXEV9E
z<79ls`yF@XZ1u#Rldb2xjc~j-re=<EH?;OUmWS~sTUk19kxR}pXd&4WGyNr_^i9+1
zWdZa3?aW-MJp3nC`=!p4-ez^^B}F`cZYpkrJfV<2D=9Nhn+n1*QozGgd)WMGR8gx_
z!{=Gj*V)(%tae~GnB4k6e}*!l6Kt05trolK;Qf~OfogIrKGs^uI6tB>b0Hw4a#vLy
zi<R4Mup%e!=443~xjm>5z#QpfMh7jT?~i8elerN>#a<)Im$MHGEL<0IXPp35O?E^`
zf$K=PK0|G_vd=UNmMIoz`48K*8rP=BSkqH%Mf~zfraRZHvSG@9xM4NkbB6Fs^meuL
z!OGbX`X^F57{l4{;2_0`Wpk4MlPfu<0@s-n3arafa%F!RPmv(}k;Ly*@GC76>5Sw`
zhZ6SAE`WPRsi9720aCYuCp(=Nh>av+(K!!LC;)B?6z-NhKTa~YHd~p863#BRM(_S?
zc(!#C7N(vr?5;-Fb6f;RBh}HGBCKxrhpWOAW04V^3}%z~eV^_h5>Zhl|A;`vWpi~$
zBO>?Fj^&)Kt>p~R(AewQlR>Q2r@jBGqc1nYidL7;#;>)?f>yY=S6qrvV14)JKgp7D
z!aF%6H_+9QBF#eQlOT|DS3JQKDa>n2xrNES+8{lTB3*-I$vH%Afx@(~6&@U>mrdKy
zF#$I6Ho{A-Hj=RkSjOBVWLcg=>1KV!ti0AzyS-G3>^GvX#Qtu~zunOa0<XZQz-8fd
zg;IsTrdHrsB6a#;1Q-6+fBTLRo&6;;_Aq5~Q`*&Xfp5ewa&3ABw-#BUwN=l%nLFlR
zAbyc7*Sda}f0Sx#q8$Wbn$-%>iwo38(#N?+Mo&}J)h#M$zI4L7`nizrwAg8HzQ_oJ
zg%CYW=tv)xQt@<TLBi5Zl49w|C7;+@rO+bfx`^#z9iMRhmw#hh4@p@*s#wqpg+#_C
z@~)J*hrCYoWAs-@;CMdPJ1O52VTqn_prt4!5X2rm5rLrUaL+%#d%g<xNTJIp-T<UG
z9u9@ouDbAE6+K){H=;oWofnX3@JKJ^B^^l_C4rTesYLDoQ1z^x+N;*@{@59Ss%7A$
z2X9z8yP$Lpxa#Qo)QeoeH>3a~+!MQhRk86nmyh}Mnzd;_5(&ZVc?nO2U{gX{bag&z
zk+IZ{=L@MAX!VHUF^5AkNQ`3PjjU@6y0Rr7gMkpM1w5-~@hD1Aq^s({OFw!b7O5&V
zMwc}Bw8spq!x7f<YAEfz#I(TVjV?|RWMrq5dv*F?V!_Qy)Td(c9!=C~Fh+}4UP<Ux
zBpAPdQVonqNgKvjw%?#XC}W|krLQw_8a6v*b(3IAhAPwg$qVnCFG;A%RjkjL?nVV6
z4e6A|6Ut=aZ-)wnB=bR{n(R=`7xsJ-Qk;jwtx+*I#vNIQss7d77)QQCPAp;s_%TYY
z1~QWYc6G;EV>{jKu8y{QDNvjt9D(?Iv^H_2wYay|=<^MOr;ee=T6i*dtoNUI$2?@#
z;`X#kGH)D4ruli1`;`nSsQGblGm-3DRL8+b0kE9j@`Adcqyw#~uV1^U6zZ{p-p9h{
zG>x-TIHJb0e8NR#wCcGfv#L&F9`HQ_^&iWd=Vz&#xuEi*`n3r#u2PcmN?>Se`**MY
zUK90OOrmV5BjZqK*3WZ$G<30rX1*+-j?L@~Zq!`KE1RKmhd=pvLvo`51&!^u8UE;X
z`Ts#OUlFAqG|#m#1xbw6Q-&&-9@r}C+U#r~dY*Htwae%_)=0kfzE;Hc53~FYsqq53
zX2xG5;<WvXi(=pLgi8j}CcA|{Pg8L}MpqiktdX+l1L-jO2}fnMST9H#NU}h&E)X<O
zF_sU$V_!<(o+>aeBxV2B$FKoJeYjp&n5Z(!?DgPN?=AoG|F5~OFK%JEAC~#*-z9z4
zTjAbM@3<c=`qyXSdhuS~tBZeK7OsyCMq)nlUDYLdR_mdAI=mM;cR#y<T~ETX1n(dQ
ze8hwuf#*c(LcMR9(wHNu2weD1t>ZZZqxgocCf`>|mXX*PjK30l$C&q{<8*3gyj>bX
zdCO!N_&7we*^6P=eEru0i+Az<(bvfCzW)z?%7x@hlnC<03?M&Jr%4C@p<j1?O8G&|
zp=j~=M?0rH^iGpSaC(Zwoc@rlZX{CxxB+nu1T_-Omn0Z$cq!(*JNePV9gIzS_`mpm
zu$YKIzosU^4g#|UryDHA#{nbz1GUiDGk-DIXI#@CYtZ*a!t``lYn2NOl3QqcT<d1W
zE%bn^M%c|pbK;LfR3~{hU;hVx;?r#jK1IVpAXt~MH*Ye*6~+8Eg0$FK#V0uxiVx=c
zONJ6kkSy%bw-*@>&Sa>}h9({(JYB7+CG&MX?dYV?lf9*^Zu@I8ZYWei=$n|x6aYue
zb^F<QP?%DPtyIPX`_8vMzRhy4<G<V(C97r3&I15kOmRG^&GB<pPc7t74;({rez}J?
zqn9#&8gGS3K6tvi7m*oGwVB3LAW@dHtJ;W<2eH?NUo@=AB3GFM(|2cx(+V)DPU{An
z*bG?10A{3TPP2FS*%z$@Gk22KDC2{72C{(w)TGT-->`G<?uxeSL^ItC_qzkwQKDBi
zwHUF$L0efU1()K<-m-C1cuL`5=8{F)(|Lu-tE(tarw7Ej9O9v3<R30(h}g^<WaUTi
zCHQfsM>z+%t%VRc9?<!k9=v|^Q|nW>M^^J_YvpmXXpHC4hYWjKMMU^K?N7{CBCaYc
zEU`0{jy86R1l8(4X7ckCWr%)>fMObC(RjtUo~11km)ToHINoB*Et=ubBeg35_E_&&
z`qHvK9_S1mLYZ0?$l7`5Pj{jtY0B<7kR@jH?K6lE@uiBP2lO#6iCJe#`-AmpZ%3<E
z2O>EcF2_vzQFTUdR2zK;9%RSlEh?g_K~MeZRvAb%tV<XwZtSq=-=eM&1r3qYZF+R{
zw&TuhM*4thgsQ!vyV>*-T6=10?>XIIFE;8srtfGkH!KR}!Ni+yJeHabZ}LcIg>%=+
zX0m+cG<<1T?FPdsBqMf=-r?Gmr$2F}y0@^m@1Pk=n3^_}7p=y^l3BRo)lV}%b7S(?
zX&&5SqY^#H++Oy0E6>>&JGEn{m(PaDK%I`ZhXTjOkd^t56ymaEttevoz?a??t-AGL
zwD(+u*u%}ITfJPJ2Q${=H}`kw&Kw74VgnIjaczc&IxaOCOVV>!EjY2z2bCI{h2Tz%
zC3J9wk8^Ih3$$v<&`G+d>1lAPfWR29ffJ59LXTxj4;iuph{GAhPhsuku1t--bIDr^
zJbmXHt~xV;ha(>_^`!RBDMJV1z@MY|<=#Rtwi<M^7Q_<L6ziZu9ykX7FwJZQHpZQ#
zK)dL=NT4#iFwIi#m{{W604GWhah?+{M4lf5>hfV2+AL<$#~RGz=H&1JnK<dgl3)%Y
zR1YN$|77tDQhOz=L}b===&Km=Yz-8$C`-m_W_AFIvd2T--YnOaTZO((-%NiDxJT%`
zOyWLI$u~T5a##>+*XmIrnf<l*j<Jx8h)xPqXA<V-3F(BaWF1o03~k^Lvt2-Sv#!9S
zQ#H{uLEy+D<Bo5`W`;p%7AFI-if_z@{x>@AS#1B5p3H!y+d(y`lBPZ%@H7<W<omYy
zOlDl5Z;M84-NP0eFEhmKXwaxy{>0g;)vsI(xTQ-k27YR{Y~T-=PGP0oXVzX1bCWH#
z@+DJXLpA8|Y)xX1GC^?_MjcZuHxTm0Ae5yEp`DqszxA)))h0=ywhwm1E@tYSFE0el
zYRv7HG4vE=7gj_|QBaONU}_-fj&CNlcd;}!drOAiF#gP*MXqY7E~e(hA7k!M_!lK!
z4M_c=ZI)O7ZDu!^K57kZ-gEM8&8g9;4IH{uVs@d?2vy)sXo+Kli1bxInB75NDX{_@
zZ6uc?F&S+~S;=shh>n?JHWT9q6J_64aRVC}@}@|zw}TdDWP$pa&<c%EnWA}$zINxi
zFQPO{xV(|Gt)RY0bGb!~EdU%#kkVR0byzfnX3(q-^B8^952!e<y1+J$;7s=vT5djy
zl9~5_b;pY_xn-S?(Rcgg`r~y?t7`q<?WFR!iN(x3;KEc4<9VxksFsF2wPL7ozrsgC
z9CKCz->q~5QDMOv;>SJ1>clfqFv4r#mDO~jpvTEbBC#@izA^*RzQo~v^IKawJGvRM
zBTc#%&A?;~T-Td^u-xKt`>oB8xg}w&h=@+>C?!ur2_I%b5IvZTrIp8>$0#_hE!b^R
zux*3~#vZ{anpCdK-K1j`_&W!FecR_Zt2`Ff3px?-$W+p`dGZAF*y;y_rCJeBN>Nx<
zu{`>QA*L{P5-TMxleTNJ)+p(x1{a0A39fh4q&PkdT1GTeFZGUXp&->f>uO+51p9xE
zvBpkb0bfiKx~PCv={)qNnUdP{#TaOoqyeO1q+bYhWu<4tDj%B(nLYC<{oFE&zcC9$
zH<`es@rfe0lwToVEmc5A_}Kq$w~xl)rG16~c&5hWdJw--kUA2hW#|VsdpV4UYXpgI
z?on;btP`QvMiR$DqcC;0hlMirn2|ilZW}d>*j!l)w(pQ!6B{GDs65FDBnv>a1DSa?
zF#A!`yZzmo6>T|F3nt65*&X|`;Z9;*tNXIOJ@#<Y=^$tD2NTyKE6M?3JJ|?YHltNK
z58R{f`+x377AjrD35*_&SbK)LDkyv0ECUs*144X<*a}0<de*q|syP#(_kX-aj*a}v
zjs_0~?dy-}!r=Ov94&uiZxpgT9?kPJJK%(7a9VF?+v2*4F9fnOXPk(j`mGnkp(b9|
zsC*)H+PkYaUM^1WI8oi4zqTje&<&O^gZ+9wU<3`8b7m}1X8(L(l-C#pxs%_0?zx*W
znhG?8Zt>M>yl7S=dKN&(f3Un;1}(<+DawtpfmH8)VC-Xg!a@M}BOa2{ZHe{xZOCLm
zZU8w$sCpro0kA!mBO<(I4tMUo2eLEztviwcs^!sTk0BO(O25)Mltg=3KM)+_%i%Q^
ze|}~8lca{p?Vkv~wf&v7c-u%ALquM3(;T|qZjpZcDn#r=tzCV=y-<<gzlKPU_|=nf
z<$^js4Yb$<^}T9hq)(%C-XDxU94=RCW4iV#R8ULCG?9e0-ww5V-a{7U9*EJvNpL7G
zv^qZfyN|af!2vOVZt|(_i{WMW7?+;AjC!#CPj>IG_?PwVIQ}Avzv@)NN952fds3u>
zbGL)wf_mSlB^-12@BDay0B{0!c6_#3KCZTV{@q`{NKBl_@_<lZokAK{NMI*QxJs=;
zU?9&U{0BaDVhSx7G;v$)vS-gZ1o4WH2a@I!=Lrsi4{bpd5~!0T4=`W|AB2--w*FuQ
zD5;H6goD=-um!oY>bt7|zqQ@nk=$`X3O~(dyLKe;q?&8-?^ShB1WF@{v@>9uV4LYD
zA7Z?NfFv^XYPSSQ>XLdtA>#C!D5R{~t@zLY-gh9TzKPphRfzr2{Xu+;y{|P=8#=iN
z@i39=>btNn>YhaYC$l#EgVYcNlV0Wd^Y{;v%vt$%3#^swYt1=^_nnxU57*T8Di00L
z5V!#^w79a!(4+!x8}0~s(_p%r+1RQ&@R1+!nH@(*)Xj6*l_MSSa6;9tbPM5hm9A9p
zzBnFnQpHbXePFH;pXNf$$bi#&COn89^l7rIUG~WHWu<G1hl<PlTI%3nLHO$$>F%hw
zPftnQ;R2zoEc5`w^8pFo<R)Aa=GoIMUqsFNYe2EJ*`~Ssg+^+Rg2cy<NC@kE7a1Ai
zNEC^{-I%Adz6#kxeMOBfBSmzpr4!MpLcz^0+3cuF){ENH-qkPO>%5*8SjXM#&msgB
zAPGB`bZH}mIlB1>IcI08DXMVl9Qq`>GY}(r;-H3yr9Md{N5)=2=G++euYY&vH+=i1
zp(^BPKA)L@Xz<kvHWi{t+j?ROA+0l?l;DS~7<0scT6e+_Bbb_i{{eQv!u6cAZ*sZ;
z+R8O`mHhv3Icq)iK#2|3BpB~D#dd@Stis$V7q?p_ucl-bBy-+0IhbCBwZTG}57WDY
z*Thw_*k7>br%J%aN7<-L3c}OpOOyl7=G#6-r34bER0Fh5mZ*_X5M`ZY*rzB$(jK|S
zdOqif$`7Vk0DRAr_ATbbzk;pjRkGFaDcVe7d-F?*&e)=40~q+>ADJf)Qwix#$!)G6
z<U^$#!|WI$AgK8gWF+G5G>8x_ZM|<<RzX67sE-!d74vEZuID_e$BV4e`R0c{Z?Eti
zU9Xf}-NsRy#!dLNRpq{J0oW3OxK_`5f?STHX1#OnMJyi{dW&2(9EX7gvGUDU2&F9u
zVinu%>qX4a>BpsLlF{lB!t0$1w{pt~<O?d>G+lP`S~bRbU7giN1bc1Vh+k+~n{l18
zD)xM=ho@3?xFZ|%sDz`Y7}}AAK#*Ibfn!^z09K@H*dXsew(XavN{cZ!XMvHp+k}<l
zNJp?7@wv^Z5}SdT11bL}k7h)DoLa^jl^k;S*8ot8jop``A2QPOm&~c<dJq@ck^wv_
zLN&Znkyi?#9g|co8M0L6+_FWV9u^1zQmi-Nlm6PiZ9f=)yYNF#x%>FXe@M{l)wc${
z-jBcit53N*zLhw?E<cIC-4f*8!)<(OD**TYWngtbm?`ef?}zc;E6c?nJaO;-5p`Qx
z>;7E;;#>3Qy+zj7`pb&E-+Q;rl-SbpMQ_6;vczYl-_f_=5?I6_G2doZl0RWskG>Li
z=-Luej~HZ=rkBAHkGd-_k473lwe^+%fq!xF=4cdcebmRw-TLi^eCNgcr5Rb6m>xg)
zt~;kcb*e~;$v3Jxk2~F0I>V`ho#qZsxF34aLPbC6JwEK7_8NHw{=tD~n<3_6HM!ze
zzddyEHa)X*YO*&ZRXbX_YhJ|1<TxuYSBfM^IB1D6#@|hTuK*2SfhLClPQp;nM1A|l
za(gE_pkzJ7asgrHX9%hr3`OWMn0}01;yP%pUOAd0nCjn#BsLaJ^r3V5$M5!kn<`Nx
zMw;xQ@WqGW=kDsbmxNFbI6%$0X_ySq3?(#zKpE<u%TD$rG!GwX7+HiELvc(_RijTJ
zkqb`cbD*N4ZJrBFfmOellfH%BWw1o^BDTJzP)r5(ain4vPH<y2Oz-~0KRpE&9ae9|
z9ZuR#1}*_M_)s{6)2F>b{J5cpia25aJXy$2e*gqLJWk3e^5bx2lG7hGZht8r3^{kr
zMwJ0VGK9eNZACY^ZZDY1Gu~p>wz-V>9ecx#uvx<V8;BRT9;yN5DMYEoRBn_4Um$<l
z>jmfWN3MAJ*zZ3g&c2n*$l01B@0~>sNHpuE=iP$jH4<{W&W0s?6W$qcs5<+W8qd|A
z#X#rmVQuY|jR%7(o7&LL$w7>@+zKCSwPA0)SfAceL(;VnWYoG9Q!=_VanSgK_?;ue
z)AGmq&YgFk1%^-#gMf(OCleI~iS6l|;{3Qp1J7Jm6ilUr<)Vp5)jb~IkXl2E61$U<
zS%zMcTnw5HGJonx#t!bQQfW2@=TNQUX%gIc1ET^Ek_4eeBuHv&95bDUZ~XN8@u6mz
z$({j!bT+*dajfTEAHx$gz9F+*t^y=YeTOQfHfV`T2z1-f1Gn=DlkfJ3{0TV8zRYV&
znWCc-s6Jk*9qyc(lFdo4-7Z>tsxT|gx!*Axp4vmJQLC!GCJdQoz-@LtvciL{(4-PQ
zB<^|Ubbj&YY@92!Y$<p5Hn|@gF?8vPYG{Inm!A)?>(REMe_=#m_cVf2)&4Y&&qh@2
z+JiUADOWZJ$go*?x*9FCj$Yw%D@pG%p-=1Bw>Purbg;Wh|HkFbGsxm4&6OH#@9u-s
zOueXYWx+5iCePtCKE{p|8^eeKpaYJa3ec#LFA2B%<cGK6gJLDIaMB^9t=yzYHzWv>
zY^e}i`Yo9i)3_Xr15J_?ADv}htrW&lpm?;5=rb{ngX4nZ_rgU;aMyDn5tHSb+aVnm
zp>uuXMjZw$8X2Z6zy=*j{p9ypw3S83a<x>L@vgV6fsf8qqtbwjqyYp^6n4$xG$A46
zeJwA>tFGY^u1XGePIZXWLcK~<uvF7{$%i>P1njfN;V3#`afXpl4`z{nuvD5QqkM+~
zF<Kbzh#bq`y77RHRT^svHPvm~hs!7QKR@88F)qSHt0$Z|B}R`aNFKZx&GP)D447o3
z&%lMh<S|>Pjvs3o>Qb>XlT(?Za|2?X(!LFgVv2d{&Od)C<)Wi-WyeRL7h>3>%;Ind
zSxy=Sh#P_<bVffBc9Lz_9SCKZbPB6kh|UedXBZfyG{{<vGYY|05fF*(gdrBCPIIn+
zC70SlXHpxmWVxM_UmNqu#i21Ngo!8~BPOD}`9hV9v<uS&_yS?}Lt~iIY`E<h@K!hA
z79={6?r$flOaj_^*oz@k1KM7Jtu$R>JVdcfzhUswEf;h8h7a5UN^+FY9rb@mmqKg9
z$9Y*2+%qx-J5mU$I_9d)FfbIFDWk~@Vf8VuOpDYh*W<D`lq7wLkV%*CQZLL6e4cC7
z;NAkrxDM2dvht#J@W)t7aqoHTfz6#-M>AT2aw=;9j$o;kQcC;UOc$k?ZE-P>Wqsjf
zw}YL;THmwEKJ9p-4|jaG)HV)xOaWj%qZoUu0NAp)$Q?&_OX)Dy$NtZ47PA~$q=X)>
zJk~s((D-(tq|!LAgq2`6TtwnCKGjW1yCl0O8l=!xXck)~#-!JcFESF;&Z%`R5ydHg
zjx8U~$BlG4ByyIdoRVSCidF+FqFLDqXEDv}FI;~Y(-6&t;*(W@`b?Ug1hnj?&$=SK
zjC=y;8P4kv#2EBMp#Y}*CB}>)HND*(hRt*Q6Pjf)8`*}3Ss<NW66uE6C-iLivKTqi
zrLB|yP!=kT^@wK^V9XDa(YF!OXEyhO>;bS^B}+9+YKDAi)~QJPYydVdC(?GHMF+wm
z9g(S+4TiYHK;bE*T~gyPIWpa-W;s>#EKA*qlwX#(F^WK$Nuoi=;nldz7^OO55z&Dz
z4Qbg*^bEX4KYqM5*a$Z#rL`TV41=86H)jZRmNro|kdh9$PCf#Q24KRXZzzkaaqbH9
zTl3b*cO=Z|@_dSdTLs;oBJyNMiuI6>3W`L2ML-nKL`zUZH>MpHMtq`p(|B>b1p(u6
z1n^xZJezrhOrfysEmb1-y7%R0w&}dT`}SW7)8H1z+1FWu2}w{nmXLSjxhcA{A%-VC
zt$)YWd-Y45v2JihleZ!tYX8{)6?b)*M6nnVFLfl1#>xw!iS^Ur%pVlf&j#Jo(Q$W}
zOb(V>Bt3Pz%lUEldIjc}ZG0eozPh|&X(EA{Q?gky;@)lr6PtSBif&`xMG-T0)Ig_}
zZ!j&x&=8wK1Qi~}(dxVZGZvGQB9NCv16^iJW1imug)aQcW;DP!^ztQ>DDu=1hD(&?
z##Fy`A?Ui4m)(hl;Rp5-#PWuulvCUFb@y5{crF}<#UOY-JnzP65-~l;pJ4}Wb}Cvp
zJ*BRj+3L*W!<dzFsZ~?$@<0-?A_+koyQ?}lQ`L>_SU6>-C-5N2fXRHjm^JlsHgFVS
z;;oPUzEhK&bgMy1DDGIwd1E1(5tH(tX4~*SUke1S@vfPkB)tPUOm@)VA+_o(tW9hu
zMa@?1?!@HO0KcU=-`ntx5vn=!O2>{QnciB3EO}?cx#^g1gi?_&&mP%L;_s7vZ#AeB
z3;gVapPio-pAi1Re~PJ7<Un|Rm*TsxAG-;myA-|d3DPoTxjR04ni$&Sv!oAr^?Xoz
zkoZ|3fP0c5te^7^b%f^e5j}TBJ|Sl%%uOt{<P-6XkiaVtw<k|{1u?O&KSKhm+S60X
zCGYtvjD;*#h{(`l&E55)4|hbsN7&!&_S#oAXI^msCCq>ieYfydt`(Af3!HKszBdol
z`7T1r`t9uSASUwkk-jA4Tj9^Q&kI3p{1J=}@N@QvDE|~#@Uka)@M_Cu^|9~Fj_pT1
zID5sOb6<hC%{?Dg*zGZhkp!fOI;}iXjLi~1T3m`QS4B@l5b5-B5)2Y*$bkkR7KvY_
zQfIf6f@r2RjRWMzl<OU@fDb(mAgCN|0s2;_^O*OW7~+>hxV|>zgIsYQN#XBQV)r;X
zNH1`8NZ$!keUQj5Rh(5&cXHO`V+J9aTRcH*$m-7?IPiALKA_st){)KC3i;S1XPtpN
zO;8*pUN`CrxTG3aA04bt$9#0bUR5N#XO-M4FVqFS8<3BZ+p7fl^0b*W1<yW8tj4|^
zfzAr9St)TkMO=ewi~@aErv)8)(Mdsx{T7j|$7k<db^3S(xVjs23{h<zy&vCl8*=xw
zx4QhXKeo45_jMM{<VO=#6x5)kk(>0uI#MRfz4~WiSYzg`wU1m|RfI^ZIvoo5Sf)R*
zK)__yh({(4luE2;FGC3x^@!C`6jElO4G0vxumVsl=uC_lh$DT814olpcRLh#Ipf9Y
znbBzzdhWLL500MDHDXVo8&m=qtey=~{C)33uQyBnV?*C5=0o&~qFia!iK^vRgcB1&
zo8E7A64lXWT^nR1J%0?PC$g&=)zgs5CU=t-JiLnA$F_7+dO5$1(@&R8ykFHeB-OT^
z9!}tUNYg})NkN<8Ei=YSu^JSZw*y-t3k0=EpaF|$XXhtS`JJn#?vVu4WD(nqW)!qX
zyz3VgnH;sc`ccvpPL$Lf*+CrI{@H2ab&89iY3s3m$<)Pk0D)seu#D<7N$pLhhRy}G
z3l)Sx>IkX6TpdyO*fMeYoadzU5dK;Li*cgW+HOOOBe+y{N;*dWji33SL`k<-a_bf7
z@;E)V>=rOPbfesz3FGTMvIxI?<IuI$X^@~MxPHF0Q^de1eI+72PAOnR+PXpw)1wkr
zyO9&fMxfiI(i+~?i;8z%Eh8Ibv=h=hI#Kp;Z*x9;N*}q#Jr0YclQ>>Ug}4@sPL>!A
zQ7Qe3&JdBF@DLBaajS7~lLqbb&#T}@Q)Lo*I8<@~CCTSZ*9)JT`shH_pR8^}5r|T+
zq*eT=K4xOyiGPx4WGwbBc5UK6Rb}_woiAa_6IC0ncwb}=NC@`jy~#m#J}9SkaFg)n
ztJOkSwsj18Hfpd_Ena%UyT%|ERKH{hGp4V+=Z}6Aib%_!Vo_nF$*~g!5n+bpe5o=o
z5p03k6{FNa8#9epLG0_PFts22JRhzH!-1bk=sMMjZB?HJydUn&vsqQNGZVj{er=lk
z2il`xI!@4NB-mM55Qo87mC!INDlVyTnkhuMUx16qVaLo6cmDOlVh_s+(?~UqSf!_0
zSj|>17Qvsw+MFr#B3|;Nf)+_!a`tC2ex0IAQKw33a;k91<_W08F*EH>p`24cYb6WL
z`pCRPI~%WxDF{;4_s{ddPGM16to~DkL;qigQ@rJb%(tE^@gI6Zrcgr8gLvUDGRK8`
ziT2)lti+$g!sY)c;PS7&$X`+kUI;(+@;g3%|4>ZgD#X~t)$y8-Vn2>|s!16Oo$v)Q
z)cw<9MEVBYgX<&uCU+Op5?{<Yq!xpaElE&>H#(A{6KS&jdF)skc2#H2=@~YviTFhp
zBay!^YGhmlC>Z(Q0Qb<yTaI`K{?0qaIl+Ma0cJS52lgs%0}ajBIJ_JKb@V&2YNMZj
z#kcfs^||!zad+0+J6RgClrH60;B^SaX1yoKTMV}_hA~sQCb(h0+t}q%(%g89!<5|O
z{_-$48y{c?7|94BxGtiR`J)I|+WAWbQo#+~Kco91!D9eUp2Jgi_2dNz&@l9uO&%=K
zIg#sO_&==mYLHNENUWAJ#^32t4Z#WM|9P+$kRwo64*cN*;IY%*2{-wAK_C$)Jz+^V
z%Y-0PC3z5+UFMUb9*iEI$c>9GQLK$Bv7hbC#WAgv4V%4Qyo-!Z>$>P;rCKnRn<fiv
zfntxfHEmKLa*`U<<eVd84-nPzpYw2EQe3AaY2Yw^UjN=J7P8CruwgZyiSh{o7uO@&
zn?T7*`9w&HL%iRp!5N|jNp1DRutOa2xTa>cBywLeR~(bh?kP0#$<t&HSjtiOkkqUS
zP)iLtYAWbAST)$bCxln6hn7nn!5<1SQjswjl$gjE{53pCNuzf$JW%}+-$@#{pS?3-
zq5G9{Y+#Wnz3f9Q;W>`+b7wpx&XpX~xJ-*}`b>AXh}+Z{baOwd0@ZpgZs;UUjvCGj
zF?|!5u|ZI|1`O;AS@GP#vZ1D|Vwo*{27$&SV?Ri@Q6tqW8ia!@ru!FK54}G7`b~Va
zo2Jz*FT@?Ml-eepwq=oRe>T*DQQ=q>9he67mb;wV_?T&Owmo2wmNe$3p^AVp-e9Z`
z_hV#?Mu%f1EVjEacE)?4B%Iy{bnSL#?7j*r`gFt;Yb+kss4>E6;fzEx6<_|sy9UZ`
z=pt!G;R-Ae%OOXzehv|cHtya8^n3>41KzvZv~oxF+eD`ic`&y;{@IX_{77G^kc4Oq
z$6gitOn!NXy^NZvFh=lt9Y^~$L-V0A+C_6X`jXcwn_@4dkQ47A9)%n2?J>42Lc#NZ
z12eSr5DxU5x!7)f>)8jAU0&RFViL<8-Ds?w^}H*)tEzuGx-#@U(kFrA7Y&Mvr>g{N
z6;JND#yK$g%N+qsZ5vN3uzmV@ud<CE=5Y(J|7oJ#a5|UsJ|{>oT=q7jJ_x2zksGN3
zB?Ap+JaGgKu5cZ`hp(Iy4hHZxL9uZJ${m<|7*T%>t+A?VnNiCOiMxOA)~>2WpxMEK
z?!NMZcerDk<+`aLglyZoKekBHK2$!Fr7oKS)^+G1T!aa!Ya<X+AfI5V1#)mnX?7|s
zjt6r5MLI2n&L^1_q8FJxQ%9uJh92j-$79uD(<@*I`t(9zKTVW2^p_578zGD9iu*8s
zGzp|=QptGs#$u-A7lv^`{JF_C*n{sI#r8m;1}z<AE#2x>_Aru?l&wJ4TvU}L{*w!)
z@C)!^i7sbZ{xtfwo(Y)7=wu!Sv2~}l)7phpN@Pkv&N!E1G0ijg?g>+Zj;*3Eu*r%Q
z_AZZQ7mx`a3K<#3W=n8~Fv*OGb6pEb5a6{=afKThi(62&gj)MdIRb2T=gv1dG(bPB
zU5yP8+9J(j4~wxTUs$1hbQRnoQw9<%%zqvO6)|!qp&j%=Im`f{!Q{nMMC?z%o%j&)
zugF&@Tg8%gF@U&IE4uS*pGy@1!t7;Us%B*FL6bFe4aWdhO6V=v3@ikIgZmbP)=@KD
zXJ1s@rydjOO+z||LbH!U{(oremV^(~<9hx4w#jS}nOTGLL^m>dL}*EAe+!SE8CNPT
z4FVMhZ+!WGws=CGAO}$u1v1TvGM$FDrQB?WgWjki`Ui70e~2Y1i4bwyx^A;<rX+u0
zy5R&0rer&{dBM*Sk)~q<YLCKjH(|2?1Zs_|qI=a}_(a+5x<@)b9RRq428xbI-(n5m
zXrCZ3%K%d*RIEd^fjiNq@U#v!*Ou9=i8za{<`jISNF5{P;`$ckOR62oEhU#G5UD!7
z2T3;4f#1$7ZJJf4j-;C*0Fw`SXkTM0nnP~^l&P)aW{C%*YAT-B<Lc7Eq<=Gk@seWe
zm`EW72i1b!<as!*ETDxb79Y#TI95%1lAN(zy7ZBE?vkOw+eb=#G%tv`&eEjR_NY|>
z@lqXPi4vw84_bRd>P&Ga0gD+9qVPi&4|+GtiUgc<Qx-{<M=J6Z|MHhJzOmf}i%YZO
z1^1owa5GcLo(dythpiHH!&u)~Q<?|Uja3l?8XQv*N#rh>Sm_UR6PwKdh@dbz_Sgn%
zflz1qff!dTmA3R^Om+mPJR_BbeFUxMsqfT(f3f4wh88U)GTD5L8lVs|STvC`j8%yu
zmj!Y((O5hUwKiTp1(lZ%At#VZ64OEuEf2^p5A6q0<R2-cI%P&ww1cIl?*91aeB^rp
z+l;8qcmsYkl~T8<&ruUeH`P9eBFP+6EHc6iL2!tJX;~wCs%cw~hC5i7R-z^)#GTrr
zSX|C$0>Qpy*02{de(l`(m$Qoxb(yaZWKZf%fo>#S?JqMFT|(^#pVp7(H_44sK%s)^
z;ITFmas~`bNS={{aqrRmSgT=BDm0F}Go26UMt()&Ob4XS>#5df^@U)vlp|&*iwgNO
z24_6Bzl`K>h$6+Wqy;?BXhVb*xh$JhjA(q>1v||#7LlK0^G&NUHxJGS0Q6W-=Rt73
zI`jH({7K3JmA4AFTVlQJbBFvnY`Y<67j9G)GWYFaUu}3%H%Ef#)>_}jKcA^~b}V1P
zP$Sb!FdI$27}{|8P4`4Ke@b6)bM}B+&j1M{t+(%JmQPfl@QNjXDiWsL#oAgnHSExd
zYZTA04-y!IKpvS+#DP__JQy|tAOLxlQxDX%QTzy|XIb!U4v~uc;TwPNJ*zx}Wb>OZ
zU>?=tvD~DB8S76n9!JbixZe-_M?X(r&0U?{GA?hB<baJ)hQL4n<`yH#Uu`+-S1vS;
zVX$l^2z=}wxnyQanNC5CpfbUnguR0~&j)Y0k=*pM9=*-HaOm#8_^C_PxO_Z#xaxme
zzmiC{zU-0f`v8XkLDFR14wjMwt;=eXKwANaH(URNM1OJVI0~^%qV2vbfRa0LWJZ4I
zI-$Z)pKA|?FqYbfP}DtGJ<{9Ps_{XDb&?|R&^18iZQ)95ySGoxkB&zmN!;87(!dcr
zyi&_W8+g1@tWLMfJ1@w2p?pMf?nmAjh4z6qPi7MjZoq)hVVyib+u{8HFVPZGJT;<V
zd0al3IS*Y}K5*u3oUL#&dva<Uyn@GE+kI8e>VOX%7lv7X)g0PfojBMNFbdq%YpP8!
z>OALQW`{RdXIH#!p5d=()CL^ed8q57hU|6MX1_KRC8fKcSlYSgr)<e3_%IJN>yD&?
zWl!XM_vC`Wlu1(Zttt2kE{X=p+4b|Puxf|-t1BUs(_3#C#h`-F<iHbGG=M7?lh)V%
zo3Soz5KWd(&bh=#Vsy0(GaCxq4A)ThfsI7MHuq9;Xs}v=l8(?U`aY^EKMdILu5yd*
zBGyzyU_+=Sy0m^cxmuo^DAm=WfmJ`;U7Y}-q4AQEf-{-TDBlV(l3dyG*Cq<UlN`Om
z+K)7By2b-aP`VU_tIf5@c89RC?i@3nkAKs=ZGR=J-__oMp)En2$UzTZn=dLIP6rvI
zORcf}4|^1i89aw`9gs*SRLmnC60!mEX6c8Wd4h=dwNQtOIMXrn;brPxlNQe>C1-l*
z+C13=QRuyzv#Tet@i~vG6coD(uEeZK?Nx;sPos%^U6T6<*CKBnS>*tNb;h!VwiQX@
zv`vt5&wl88-)mT-KIxVa|B=lRT(ym(Dz2rl$`1YnABVb4SY%H`Mq2wu$A((1PHfj;
zU@xgFLWw)1iPY+mp1(FrCq}o$i2SaHP!;OOwdcnCt&aY@M^3xjlm)G#LIOx-qM{2h
z1Xju_qHjn$1X9WO;=nnxwk#)1jE*Ha*lT_KjbHfZ7EOY?sDOJhJbarR^Ra9|kdil$
z{B-~*0y^r4XgUQvBUHww56se+S1SiM$wUlyokbMc8y)U^I~Uq0=?5tbRI<*o0{kYp
ziO*x27=Mi@e;X7<?kUO1$bD0#Y%OP4tS0(P|EQGkj4Z1d2gg;6yi$~hN}%L`RDa<J
z2u^%$c<7qXV3X51ByXVf4`z`XnHUL3CRW@%*kvQYng2|9VH#`WaCei67wsk#5M5$2
zAF{6vwKEKnY3hKgCDxcGw`giwS@8qhiO!R6H9DrWU(YA&Aq4~P+3J)1gVYJaM8+d(
z+$!humbmzXB@!9>&WQmy_$o*0Y>pr-+;O#WH8Eop)tY~%6)~^~NiL6ql(!*d<hX?r
z8{QnE!CL5@Yhi(Wy+>R!N5o*!KA{2Lg7_uLqLDsT_F$sCjl`ku@ydyT<~PJL2YVDv
zpM2lnz?ei8QCL9XDwLq<om*xxUsLOaNO(t^4L-e_#DjKG-4z)QPCnJ54O|LkrSL+7
z8A0wtY*L|#R7C8(sESbl){qt6QiVw!Od%K2M+lL9Nui!(R|v~N;-sDQo4@_G&jS+~
zJ39dpa-w%(=w@gd$IJD=ltl$nu&{`|$_b=q+SZDcg1;s!mvgGei{g`TWFKbUM8}Zv
z)*)aSOK80i>q}Gx@_)IoY^ifye(-oB7L(eYJHLG%+W5#%yjK>{PjVFP%xAqfCflQP
zJ-*NQe&yeX@qPbrkgbcn^>C0AD}R29t-!b6Xv=A~oT&SKS>dm49ftdP{xI{VSA6Pz
zK(T%y9%T#s3*_@B>u*Up_};n%6yHBl_w({Ra*?f+gJ(bW;19pZTeXS*<wzx||M9(o
z9DeBX_v|bte>_S3TqyU}|JXQ<SAdX@cC2EU#GCw;e|{z;2Atpag!kUYKW0Yn(tahm
z$1FF)g}AyI?lWDyFk;kXkDgXEbm7rYejWW^+yyJe*rp4m_7}eU4ms6l%fui3GWvF(
zE^hsWNkoj~zxqoqxApb=U%J^^2;=gxRx<zDkX?YiddWz<3ET_))k;xe!<F;c;2iiT
z<aVjfFwV5j1G8k(vHq2)=7vkd!89Vq&e6P>NnZ5UTtzCse5EBPxZ&F&e2_3aR^aW-
zfv2LnQJ8oE#_u@i(9Mn_-puU`T}J;|*w>keFpW$sTQ=tLDy;s@8(;n}cD<J#9uL8C
z65v8m3hsIhrc}~;FF`x-T8P_4)E2l42bo`SAuC7Q*uca<iz)*nQgdcp6g3Ay;gAJ4
zz`fQE5Q<s_H!`$9A7&WhlObYb)J&EO_S0EYKrRg&W}X2DjA_6-9@jo|_W@1=uug<C
zW#oJ=Gz%~>WL6=(mSM+1xrJ>eOZeP)28Fe*2WF$nt~|R+Ee~Iv&-#k2Z{E?2v;Z(D
zk$~bjGj%E(U<K32aFkp;9pw|O><2?&gh$x3gQv=gbg(&<oezB0BmK$ai!J}<f|FXa
z);6<_rq7K{f<?ZtJEWSTyoH<IcZ)Hy6M|)%k#3geN&RfZBP9V9g>%*;Lt$aUHhsEC
zuD=>P?!ZYa4^k%@Ii0;q@_!EV^ZfG|pq$)#zNI?81a<-9s3oKXw@m{#L)<49S79;B
zm$T@=Z$7}G8D7!cHWO}yR<TmdR^cq;Q`hj}amd}q;szo=2*QayX>gi!jCP{BvtexN
zWJof|N5e@BX3oT{?3n@vVQmu+=x|TmOLSnRf&*t8G&1i`XKC)q(kV@pzxHk45mhFB
zA!Kc`+<zOH9+u+fXFv0<_E;o4O;31_w^XX!Xiq{)cXX<?<<^xYqto`e5Y+-w!Ces~
zvKj3#{hYt&_U6pd__|X>&1x@reyS0jiWYVgb=75`$t+5G_05^kA%9V?@^<ACq%~me
zrqR+f-d-xcpXY8d)97G^Ea#*BrBOeZ<a_xT1ceS71Zx2Y6|^c*bn@?(qjU)L+}tew
z)2x==0!IyEy%eLoMHq&HVv?O^E5DTm8P48<30}?YmFm%KWfKSeNN17?Z+G;Q)fctB
z!;r6&5y7a5ab(VfoE^BMk6Sm$oE)3aG|xp(RP~drIsl~8T0{NFIH2Uhd&xEHTpvSD
z7T7Fw!lXF5_IX^~i^O(KJA`@-O5gdf-)1$BW~K=-U`_LcKPdJga<4cg9v%KN%6bAy
z#a+izyaYSUY#w}c+^kR`+H2-<nv~v=Kqy%2`lyTHa1vG`oM$b-lZP%846$a1sCaM@
z5<KT2b@$cla6FGhbG?^4CPouX#Glz`*mfvJLK6TVk+FvEm)k>}bJ=r?qfN4Km7A!_
zYI2eV;0gVjQK&b0KtDbwI(|n^azIO5Lfm_WUi(B?26@QS(ffpJut+m&z>+@pkAHL|
zHA|9auT?k&=WGyuf-*L!po$Z+<ev`V3r9K#%VOp<qb51~1$4<?QrW*8+UTP?Ma&dO
zoN6jF4dPpg(X_0F1@TIM89+%Fga$HGksk}l!C0h$%%zXe$<d;56V#wK5=EJGsZ*8O
zaJyXue{#kENRkAhToth9j{zT1M#Flj%+MYkV!~#ZO)Dwxz`}zHhS6^eQV|fwOqm9-
z4p^U{w|9S(#mKjtB_c)a&Gm5pNa3Rm52-Azz|SP$5t>TPC=Jq2c%@nL5$47ifXq|@
zYg~KT;QBR7R!j$RSXrb1Uc<K)E;YLwEP~kO)HKL7cc~Eev@~EjvA^@m7-N6P<LXfZ
zCBjibG(}9tP8P{liKT{aII5KK@+K54@gY<M#<IJl6nM?gsK<h7y2cI-je|D&oaArp
zQRQU*6euMS&KIm@+&dq*%H<GSDIS`)^GcsLVcq%=r0a^QAJRnWQ?@l&=elFSbEH~8
zt4gxTCb{$#mVQn?=P6j|7XralEIJe&uxruaaw%vvjhL#j&U@YsFKg}rmlWI)d8tdD
zf|)X8lyo4Jiy>jn6ueSqe>rIqh{?U}gfYXhg=35hLzzSzV}N{Y+mmx+Iiv4VIS^;*
zClrR3l`iZD4mixDcfb34&7KQBrGe=!;{}23?4y=BSix#2_f+UJT@S_pip^5AQfg;T
z!I?xhL&<l<bfIShpKY$r29yh#Zk32c5)4g$myTo^XdxCe-UMSzEgJahzxrPo-n1}l
zA149XLe80Fka}CzCQ&oe25kBD8<IMZM7vJ2-~qZ6P@00;LP3oxK1S|X7-kMBJS!wc
zVE%^7$wVa8MehV8(sF+3&OiDVSxCm2<`N!-DFHainw#dbgEo-&q3q^E1#vyJC6*O*
zua>pQ+=07bkqWUCC-Mdf7Nvc1JI|1;_Z%)0;Exg_VaUi~A+zocBN~fIj|~X=O@p2O
zj~#hC^B7goOsdswn=xVPY`j$E5HSRmj4@QdY%Va^ecF>X!F!Y<h<Gz5`-qn=ZAh|x
zED9<Q&TK)qLCjE0%pLxYpUCOxGy}DCGvl6$EwkG9zV~<NfPJUmN<I);-QW!82A+#1
zKNB7`3merz@br{SisRS9U3&nANrM!G`C2e@G`s$CXW4jr&w2SbNCmy_b%#@f*L4*R
zI56h}PW~9MfH(Gju6l0A4b+xQ=)5$kTglOEC;MW)IUV(f_%tqY(*u4X!Aw{o;o2?J
zVkV5Sz1V_fD~oLC<v!d~^)V<A#^!-)fI|mwo4Wh@AF*M%oJ~eM=qBv9FXe`f#+gp<
zu^|TsH;COZ(__(2uTi)6UT_<^nO<(0Q_<d6if?rAz`8^2=H{iMwMn|g*9@6|T5&Yh
zxBIhGJF5g11gd{#PxCW-j>bEuW;pxqM72Ron&<(tW27YxZ?#@3)HjNZz4WC_#Dsy0
zF9yv`CPLy=$e%E67rvslWXFyGmz;pO%)D9z=O<5|e3zR(r9X>x1eGj_RI7+_3<yBG
z#$LWzIk%-%B!M4>K+KZo@{3yrupGM9&UnKp8R6A$CJ@Ra9bEJ$;d@;nl@N!eSdiye
zaQcIpBVEoZ-Ro&SV^#%Z$}iB*>b;XsvaL7gcCCeM(kqP6(N!+m^AGoU<LgXvs}t-o
zawY`DfGGXMdq4JDY)5j?a#91eA@^FF_^`fRd8v1Jv#nb7@UnY#B*Cj(@vdE%LlW8L
zFcFwp!Jdb|8!K||)qLV-k|}feMm=jax;w)MlOvpZ;{F4>u7Q9_y+L9+(8&k&SG`1?
zni5UoBPSLsdWi7u{F5kkw$3H4tLM&*PDnvUHGnpD4;8yaLPwk`S|&N^1V!H5%NL*Q
zl;5{3#A)}}&_Z=DidHK(B#(QfxB9bR@csson{bN+C%aTfHwBStKHh2+E1wO+CEhxB
zg^ss2!3nb^sM<Kkxz=5_pDPd`5qFgo)3ll2<md(TZPXWRqV`>w3Q!W=TU@NEV%434
zlhsTM<~AKeb8nf-XTy>l^U-Jy2=3;50irL-^aJSOMc`h8BGCjz-4RLU>a>-fhr}YZ
zQlI*bl66Th8@6h!)!F$n<zNG<MYcjdDXgke6lx9w&p8m=dZ!*7;_!At;*p0^VAA%1
z3cpQoburHr?5istRqcxW?1K@N$5|Pj_>z9)8p!BiX9S8yhcpl=3)K_0C){M)&A3v^
zc~}W-1ptYPh7)DzD?F^KZwQPepf;sO#vZ!xv!8km18t2gdaPk5bPO0;Seq?UMKu6)
z1s?5YDy!L)ahXf()M)Oca-}Neu`4FgD7f?piHS%~b1cj@-rXuk2L~i>S#7vfM0}*H
zYL6K?PPjT>Caz$+S7V}+N<}&*LFaK9>!q$Z55!+K7OTme{h!Cnf9qG?31ZZ8xQsGf
zcWqWqXfZ_iHaO5Y6xPWoqE>6161}ZXU*?*fP{|3d)12}_t$=u;x5?<lV?{j|qtkm&
zO!-K|oY<F|0x%I$E={BuN5$$y|4`vSSLJ9BtQ(E~j+Kw&lQ|xTeDSVanh&h*raobN
zYtzL;7m|}taWI>dGY*Lu5h_hWfg(ZaJYZf>Kuiv`<T^gGIx~(e)$z~MWzs{vST)If
zNwz>|g^@2Bz+`k;>O?Fp(q*#AfLwCEXqRdEnsiT(@!#$g*{ztv*Kz@@tSS;C&A@?0
zkSPFZDf#_)LRz*yaWT2`?$2AJ;!?r<HL2Oj0(?2%3>ls@ES-fji4NUR@a@HH#S2m4
zaf-lUk!xb6Qi^$cW(A*->;cr_EMd@{66<L)DicG9wkYPqp$Cx+AL$k8OYDBYTH`xR
zr7U<X76>cltP<O&{}Gli%XOOFHg@YjfmaJA-H;8>`SY_9ZyuL_VHw1Zyx~NlsSB3K
zlzA_vim}#!gjj~-XIpea1~_6%dMX<crJGb5QP-@?HS$)jAcah*sc(MhLWL-C{q;@{
zv23Zy$sx6gGK()hE@lL7PRlCvoZZDHW%(U1-}&Emb0t5cEim3x^SyQ)Bj_xCp@n)2
zv3P&T0X|UgL3(>wDa$;7(vs}5Su?nmSIF2Izo_J(?@h~`7@#ej2M=KbC^FG=<g2|G
zb6`uANOUyKAtMZn$8MevNRQM3ds4VpB!Cf%gjlk&{?cpjDlkCSF|muJ8XfFt)jZqs
zL5dJTg-yLpxFDoaAMB77kqB*GM%K9I^2}^mTC82EI^2nGW^uKM33&z#1Sl~Bp^`mV
zD9Z~5F{W{X#S`JLSPzB{W*sHut#|;+JYN0s&L8=~c<A`4@J%oL{(;0>2l&2uZ27N^
zW&X{-5X*coB>La}a{E{J?0u#4Z$AImoooCjSJ_hC&XL65zsg@YP59Tg*yW%8a_cAV
zpN@RXynN)%74>mB>Ex&1LLGsOBkBmT-07W+-~2wh+@g-fr{0P#|IPi2yp=lMkBA1u
z$~9UK-Tl(%80r{#dgLT*=@U8ghCzyL%<P8`Cnu7StsHARv0^B__$drD35j;rLw>|L
z=GMH|A^8j@6qtf=uVi#7L{LV4DT_fVm<l^xSp>9|s~`Ii{pjA;$a<$Yr+@yZ`!C)5
zDF!iSs=OX-{g5*Jz?W~|dGJ+?T(<RRys2)rXRmvw_6$%NPVNBaxP6YXoI%&tIj48+
zX|qI$3*N#0eWkEtWBmB>_QTj$B$UAz)Ga;zbl5!|#-e+4^?0f4%;3y)%~E#75O{+x
z1`fEaC1Ex%;0w5%s(J>!E{SByKEx`wjflWF{x+5HOiUlw>gb8P?|-+o9s&E5y|5Jf
zW7xRsVQvE4rNvwnqR1&HJ3V!~g*TA1SzZ_hV!qS@4XVYs;Wh}6*&htBj!pJRN3!$t
zXg5d`<QAvHU2s!7y@l{@vX@sJ^pFG~l{xb}9UDh<%~Vcgvz^-h66D}jQi@3<H`xNf
ze1>dfpZeQx!<z%c9xkA4Mnb0a=7P}Glqf!*9k#?*fI-=;=-Y`wcs%}SK~Nj>CK4IM
zJ^osN*NUP@&FI-`jtf_;M=72;Q}iivBI1HzJjz~z+tT@Ymv}6e(7mX2#%kb31t4gt
zC-S%Ns`eoQt<YhM=14KVtqGK)8LY|VXso+|V-4jdr_d(E%+d-%v1zRaX8cHD5{M&7
z=0dk5ehwjJrEqkXrqwLslF%KU&>azK(vOUim5vZle0|b7-2Kcv^^sJ|26hRWaT6}U
zwn~8?hxfzeHR^HH%LZsg4u|&L9(@w0aI8S>f&`VhQ6UZy#l}d-;S<iwjRYLCdh_wo
zz_RZA*(+8XA!C(%k28oK&xP~leHou(t#8{gfnQzoR4;VWLmhvNy&R7-7$L1zdWM5N
zv{Q3+rBfb`p47!#<S^7gkzlh~N>7J~s%*mk60-|liEl5drZ_D|@Bu;&gSjQD8)Q+6
zJ<GfQdjF~F<D_PXrnC1DW<0}uxj+b;^zk^{+F5wGd#nv&@n0%9U)vbs89G|{JYyXQ
zMrXod><5i1N&e`2KtmV(GTo@4L!-3diLV&xYk2x@IvaAjZmUF<3T%+Ro*T22gYggr
zJFXWtOZv|9zs1Y647D|k`Aq`uEnEtgoCIlX>@~^h$AbU@;`Dp~5|jp{$;L0z|6FUD
zF}=%cn49>hOfGa|aFkpK(if}+#UMk1|Nrv#E>LpZcb#ul&BUHKeoU8|p=gBMRoy#V
z9y^Mr<?HR83-MG>D<0WnBso4{Sh$uHFYC(<#C8n$!h*ZHYoZ=BiXQlY?%v$vd1yi0
zg;-Jy>)nNoMwV|x9&20c-Sq)NEG2NVTu9_`Hs~xYxu5U9s(WUn89j0#rFm$&x~qQm
z`~Tjrze1-r<)$_Y2AaFos^gv`;ZUkpT-?=+0Gusi7yxYZF+wP&Z4#mrJ?v~!Q<c0W
zHa+GARQ4psaG;I}iCN~Z5bJ0!l|<tRR%nC>m*F<bry3EFuL~ppa#KFKV}V$>HJVRw
z#=WGRP{kS?1dYA16-2;GAdkoe6voA&MH3!#gc<6!aLW&Prvni$UoZ#@%6%y5({mCH
zAt=Sf90Ez!>DYSpTig^%m7cV?B>p%Iplg9SzJ+VPiTCTphOPCP27CIQ9s)y$E@R@X
z>7U`Ze*RtQ|03Spa##ccY78Vz1h^V@u@JxqMau#2;~wS*Z`0#h0g*_n0we|&DT3HC
zPb{DS?SlI;!!`l6WLzzfwvXvyF+iFJAP&O%&<(^Vh@V)Xf{O<NT-QX>z&C)RzhnJ^
zJJVDAx4C%gyF`fTVSr1YxbsqW=30O4zr6?5Xx^RPGQAp9B}f3ATVLTYND!`sn)JBv
z_0RDiUF={0<gJAQ#o~y?F%T$tbtV@SV|z4U9A4n8d>#7n$~7*q?B%522QPXx+$8W~
zzTH3iX~aTr(XLqi{zJLI8V%|vh%^@~$+1L~Z%z_l+tvIo--+WRt@^*M^;(;f3kjEq
z;RzL~^?T;DHJ}eKofTby^X$TN`SP80iwmb8)ycR2>m)GL8$3#Sn8jxm6?%ev96hCZ
zjm7P}158p*-1$WMo3|}3-2b(YM7)KyUa;f1|83uAZrSK=-5j{L5qig#Nl#nmEP>PV
z2Lv~0>7Fh!Fv`l^erS$6nX^LiMLo2+xK1Z=?z`R2wRwhRr!V~8x)i<O8l-~NUT!`O
zum<V;y6jbAj9O4YOW(|$I&WTfiR{%2zds;^P%L1L&T{?u!2PP1)IRKThH!e#3EqR-
zz%D%5>&AwE4v?2#)@6X*%Ino*E?}P2J@oy<FVfb>Sz#joeZr#k-kPv@GDVXq)sT}s
z`g)ETVSNb`)b6Y&arZnI$v%7sA8wotUIfY3gu!BZY53B7*s@-`?Bs=~$2tgbm$1b(
z^@JjfV(tz=>Qeb6WP>mi5<3Xz&ALQ`__Uq93iWhY;v)}b0*rSpJ35rM^wQ<8Wao;u
z?w1~K{o0L?Z5`C%LK7mlA(-rg^-&(1QeBtKK%B%Yi5Cl*HVhI~JWF~s9CQl*EfQyM
zc3$0f_{Pq89+M!ln6vu|FEu*v<dMyDORTRrK!c7hqg;sopC|mq-O=|1wV$Xz_JODB
zZv^G~Gs$>0`AmDFnj9b^Ll7a(Z}7wK&W$wv-0|SKvF{GvH}ISvJobahhaWF*n|L!Q
z_ukh|#-5ozgY!QX=U!shq49IM=2N-ZlIP~`to`GsvwNJcpZVAa7EdSdt<|3B-h>i>
zYx_uY*<H@~9l-26Yj->r-1&hpC<E5Tzy7DF>7Yh_4Kdf>7fF-G7z55a$-hBZF%k`!
z<bXXH+E%bh#G#K^{Z)Mg%#p-jaboEc=2A+i@PP}z-x}SWzvBaM1b0()L^ESDQJtRX
zi$70yNDGT<IzBs9YUOsh)%^DbKM~im_ny9^ckIm?bDhka_f30rUL|-B;s0^Tn{Rk;
zZR``ZP04#tXBXzZNqXT!!xb+#7>~W~?;Z%tA2_)CwczgTx@VG?&m{e4rrB(b%bttl
zLpk%_p1XpN)q>~JcYfpkKiwG(T=Z1L^peM9nNm!X#E>>y$RX8=4mku4m6ebQBKH^1
zm4@bnLTi4QeeEhl<T?~f4uCX4Fy|6wt1>%c$YGBLG!+Mg45Jf`jQ54%o@PTvi8Z5B
zXcp;3l5bx1OJD43#j`m?NtGnsd}(AhH$v39Fc(nk{{a6YbByNe57+DWMfEY#kaHyA
z@f)gz)~sJ_@=ofVxGc<Wpqb-B!5pUv<PcNjPi5wm_s{`j0EAdBAXBf;2^dU59kc$o
zzIx;Sh=7R#vIAd@KNJrh9i}Fjo|KuO$fcYp*dkEak@MmDmi)u@F?OaQnG=AXxpftR
z!c9ZI^`vlIBi7@2fZ;LnW4;s=fvo|Obat{&HD&ro<O%G}(HFw0Wmsa!zLs(zeDaIE
z8}ft#TL)RSm{Qu13F@uDcPb%}ohUm7PZYFm(axag9zjy2%9-1xSjdo6uz8kTmEMGr
zR$%j&PB#S*cn~O-{P|;S;X@^@rGGq&Fq|$Mlh#SHB<}u?-GHe-`Hc5wn`S{ad^!;}
z=g4vuO1?0Ds66EM3M44$;rd$<@<$L6)(xx*WP+EPt{DhIVB#zLG`_`t?At@kpE1bO
zl8v*MN<2vs3F$k~8nOmOgFLfp1kedC&*lnmzwjS-M)YvEjzi8<C#omH<KesyrEVU9
zc7<5J9#9G87E*2XEs(a5#3jkc1~a~bep(O~j02=p3-r8<a0zNR3;w*o6}5nagw2rK
zDP>Q#p9(4TCAG+-fhEDnWlZ=3V;D3h7Y;wVGn!T}HIqvz$Jozh_m-;6uN(?yhd~sO
z1t$m*_A<{#gtet!ua~iW7`ws3fcr+kz>XAGf)CtOiJAtiI_Fagrqm@F1u88YMPI2t
z5q`5J+vHIyJv}?T?aWOR$Md)^C&LjscjktP1dqh?DUVP#?Q8)lkao1a{si0qG-B%F
zo6Zom{XAWID<Cj>58s{D%+`ZDsT~EWDoa2~Td<I-wG<aB0OKoq$y@y2-cP0rsi2<n
z*W1m5R2I=##KUj{@bFN5d%Yh#z+KUU`Rz=GMs>MVWEbtgDrR_S*w_{{B3MH`Ov1uS
z6g}ydL@)8mxca1bIBi93g5U=5X?d3j7)^CF_uc>aWIkyzkzgOek2baG6*as$P*_0N
zA*B@YI=koWs5fjLTVYTO`r~>WOtphr`KF$o4U-TNX2o<W+1@751m(t4P0eA-#DX}f
zBX7h+ttfo^-*3L)<p<tuKj~d0f&__7kx+o7st{knhnGaWd`$2dnInL-(JnHwM16X*
zM2)fU>lSdjZcgF?ju0nRps^A%i{dKefMJ`JD59xiZ-6jIq)L#Aa8e{8(PEUx+u!^+
zn~VrJeYY1WqdNg#RY&GFS0vJw_-chrR2#nq-2xEld|DsHxj~o$hvizFWpY}RqT`@Q
zb`uJ71o(=@L%!|Ri-_u>reoGl{DkybFtnVz_eXE4Gpujm3>h_nQHqhR1t}`%a;Q=c
z2m(RL646^8i%40`<Y3cTKOE{|b5$dtjb7j$h-i#a0Q5#$vn5jXNFec-;FT6LoRzeQ
zmH>;m5s?9=QpG`m2US$@+rM__&S(Q!#3!}vi0NMmWA4<VB_?16h74&Nm0_41wOVF{
zW^+gm;T~LpCzeRp1tJ!3Hiz9JA%t3PXn}=80}>L*1170f7>>0YGM`P)c7)GKHp-3P
z`NKaQeIt3&`)d4pn<}QkGagecU|o2==zulhs3UeBuG86$-%P|mm_r~6JCbX<rH+Qp
z^v7Z7s;A&PMW?fxl0C^Z8MUKODu@ZCOtfMtdcu^>tKKjE8FW6zHj6ptLA7SrVMwq&
zEIKM$rsMPV=koQ4nq;o!10<Dn=v^MnJUAfWa?;5#k4cIE&=Lt@%T&AMI8cBS<cgpM
zK`8fB{P6SK`CdBJ&nb{Ky$}wZsSeo{Z=@76rVCI=bxH1|s=ars9a(M_aX<lKm7uP4
zPl{u-gjnA)0Jspg`42aXW62)YCD9tSGfENs2mzo`?Tw&_4|*u8k8Hec;41<JLt`Nv
z{3-&O=}e`b0&CQC!Uuw-)j6Ht7M&w?imf#dORz36<TBKhc++DFA_%52>#H4wWumDG
zzTzq!h{avhxNT%uRJx`{uB4xZ$Z_C4f56)&9ff2@r$5r(OLI(Neq8|)Za5;o0M%4a
zakM4>MtzvQ5+MgTjw<p(TmqC3*_aYW1FMIVvewoyT9E>%21_HJVnGacQVO0tjBU6#
zm;zc*l!;290wkF}8(?-c{M-L)h}KA%i>j`@{@$R~1T@K)m>)p*06hvzs$)y?WS#*$
z8Fb)fxDp}_GtI>HUCu#5ta`Q5!0Z6-l=no=ncX^df^AJzy465*N>6oE$f$?KL%@H-
zBn6+b@@sqIsn^?c!JcLnGjN!0iV=`6!>fa{I(COUW*3M&!go+qSO`EJ(`b+<A`Knt
zAHhr{FfRE75$nZFEP^iTcH<&=QcYCAQ+K7}&N$xSO(Cz}`O;^%k5hw@?C0V3d4;p>
z`Qe$(L)eHgB?KM<j%=Tl&Sjp7WN0v;Xbtn$#rOvTU0H`n3V>M_j|8?D7D2;hU^xp*
z@mj>t0HWu(cMfP?c<`o)T?od>mpo|9-P2MR9vPBwBo@&^%gYS3%(mWMhpzk>X)77$
zm@kl*f~P)l#e;xSgg~pG^hkQrETR$HVaz{14$6TYz?WG8GGlL_?3sKqZ)g=ciw3|V
zVh_By<ik2!50!-@MP(bl!39&#VJgB)##0g4z#~a%5Qb^w$#6t?uXBg!Nz%zwEiaQ%
zP!e<@dxu9hM3)&RnW_Jhcm6kRSn)~knbd?Z#w;_Dm>nSF<3M=@rDGRZ)(8*RECCKC
z8!H4^8-Vc57&Og-73_)@H<dzauI|t{sV4TZ0}g0BrMFb)iNYzh`udOD;5|U5SUMMj
zpgE63C?Q`)W_=!w#|u*xB3}{Fy_IN-sGjxEgQIQ5^Vxz)so|h8<FYl2qrl9^)HF+F
zG%Agu3&^LI!DgTf>4OG07)q48?e(93(rHnb$n5wHRjN4V*;`XKeh`kBmC$+w4j!v)
zSd#4I{IH@MB?paO@VT4eNQ0RSn1X|yHC&ig4-$xyd@{GRFg7OH`5~hjj1W-7DG6|!
z!1L7Nwx6S6Ofr|&?K$>dN=e92a)AGw`p$q+C+8P=x?P~!XEBvf*P$4=jNAyfDfK|k
zsG00cM~%nSryXM8EzN#f9?1*V*E|A0!f(yqgu8<IQkV~Dg`XY9Qc#t@Sd;@_2KNf)
zuCQj9A-qSn&C*#)@1bSC>cQQ-mFHb?eWPih8kVAyIM8LoXTNgutIVqVOgxFvx*y}>
z$q=RIjSz~JlpTD!Y$Qy_-qG)e>)WCy^LOV9bXAmMzsF)-wEmeLQG~yUCM#z;)Rah{
zks&8XB6GDey_)LR$!ECV6zl_IvS@ne(%ar_OX478jK^huyfF2iSKc`N_If!U(jph-
zh<(ZnZ2HTnX0&$J9xSIo@-x-{57!?==i=O3#aSH03Z2Bw*yol-hr8-P&%)?AWM?yO
z^)Q9Rt(fgVmw_TnAcc4zYHrdyDoZ9KY#JBLGx2jD>?PZA8O*;PURa;s^2hA?um}GH
zn0eq<Fkh;Q(nuB1fXS{ODV8&N&R_RM_eBrnRHuSG#R?$J1qXH@h8mQY1jPZ7frbtD
z3j0fNOlD>!`u{Bd4sqJ7d*f>8{odZzx#)PFHc}5;3x)2B;AfQ?YdWL(UcT@vwVMpi
zNia7&g0(PD5gC%*aJ%HI%@>u(#?}QzkcK68i(y5Jkmo4nM`A&-sjzQOpyA2!7vA~J
zA9`(^+O4g2g1InTVyrU8K|Eg}?gF_76Sb$yM6$L32+PZ0Mr=&<o{UH&6%sq1<<h#k
z4iiOUYYZk2Xjlbz%>uL?SlR*283<w^G*Jwoq`F4m)M2*c>Z8qDH$XdVU}z&QVO;iz
zg0v+R*_P)rShm_2ORQJV2$BVp&f$hBDEPUc1%oaii7#G6Clz`6&h4Q2_^swsp{CUV
zcq%*OuEaWH-u96PZ<EV^E~XbHrad&oI`KmIU60jho+_)BgKT8)$$TUw=VRx}G*J`=
zVbob2>^Ll!5HE}PAL2?r+a=4Bh8=`1Krsu}N2^Qhxi9>Uy|5uaCUsWz!ac41O}FjO
zudCwNpd*@&i8ufR!m|G~YbY7wFda%}CA`fu>xu|7tqiM)OF&UODh{EP!ho+$DwEQ(
zlty?@x|oE@rB>Q-j0ofSi_R-g=by`;WG1P<s~Kz3hg|1y^s(A~HG&=)f$WU7JeP-n
z5tehM8E(iejrEXHo{aw(i-tZj9>_z4sH2RPK?>=?5!r;{=`*7933(wS+-OR<N4%lK
z^l`(uir&vXIr?<|#k}MnagJd&6=6#de<rX-B}F3%B<()UhKB?jZ9+(lsCGsILVxIb
z1bvDes|feNY@$_EuH?*0ItfKIoHPq0`v4mN(Ibb&P|D%(7ytHTe(NlPXbM>F@#w{w
zU00l6hX$o0j{vNq!K_t3iXO2?q*%(`uM$H-&JZ5s;dCg+AY(4%jMhQVZ-4<ODJyGE
zks~$+OhLlZ>0d*YFN8pj|4jdfqp=12kf~V)`t4~>VQ<V;2n$Pf0{_PH(C(U4tiYiX
zWegh;!=uz90st3?Gz19T!#c$%6DHV-H*^NTGGJIK(T%Y<r1kiW2uDjOO9ZtFJV5aE
z@4aR6jr#Gt&p5Yu&fmzQVt353IV#Vmg{4=8-90<YG%CkvCZ`pw&XlUKE(n0t3`oKb
z1_Li4%29L#yNx9;h?mK_c+ex=D`&{?JP2Z~JdDAPi1Gf_kME4OMY$s~L54Aba>N>B
zoDu6p#+<L6uRT>JfG?m#)$Fi@JA~q$4`e1cgTRM{8$pIBXt}_e<Fx?SW_M_wX&<xF
z&FR8r!c8&-Z0*CK){{FjtJ6!QG%W%%<TQ2mU%p2|2T#|Z9iBcBvftP&>j%pljPdD>
z<*}ORNsB03%@9B2jM!&^kbj0(%pzhR0bFUw8EMV0!>E>L6-W)^Bc{y8ubs_UACY4u
zJ62*@_|yU$AyjxOu-Q=N?!2_W*M3JCiM{K{X^<r_R3(BPG>Qt4lHoi83z!P_NHE7u
zA@QbfJfTb$iMlX4QO1P)n>~`yvXWBLf}V{42nMUL2(N)h4ntbfW3#!IwAS%2-tubn
zdYwfi1yuZU^HWt!YeMJ<;FPk4%qkkaCE1ijA}y4At2A3euiy>{PeKNl1|pV`J~fyx
znD?=Xz`a;k|2Uf}FWAg%R?Ny{O0s^^Hjq3^tM3DH{^{fR^k2Vc;2Y>ujL8^cnA=R^
zVq`w3h~#z2t`0NeY3mLQ53~mh!>tLUF;36iIE4#IK@9|IAGzcKT#xKfmT#qe8hs`t
zU;;D}lZwhOK}FV`;^W0T|NF`OnDo8N^tVbl0!_?r#+VUR<75nFx=iG>fEvM`ZBp)r
zHR<DsU{H!=%z>Q62<5o~zcjm<7$gEZrFAGN6AO|@;71}sRH-L17)*uKUjNg7@oqv0
zB3oQWQD_q%g7Gb44855HOV^qy1v4mIBkP2d^pp%S;*lt~rf=L@?Wfp1%SRz46b>wk
zh!k06Mlxr@dk@{PM>d}9MN%Kb_go}goEw70$c8QBuls6|j2*-N1N?_*HTE{8S<ImV
zSt#C&`?)Bv(C<3pj1X?bd`f+`K#_-xE@VpJ4L#JJf=z@*$t6CRqGUElf5`0c^WU`N
z4fzLh0~ZNo&kiU1o6JybA(Tlm5F?VT+*saNUJjUK6Uq)t16g+&=UW;vg!U!3XoQww
z`W42H5lNV+!jujck2HJ7Dtza2>`=xU=|_byLk@Jeu-U|3=IvS|#qKI$A#U1Ay>*!h
ziWQOgv%yG!u~MA#jW{$<oqe`TA7C;_@2@leFX3%8qU$l72zgAXd<2^bP1s1^Lx&~S
zl+z&lf{?{&5EFL9O2aP3*gk}{01-2YD=%AnW3Crr-DS56fA~*c8>j4Y!P}?o7m^Ln
zrkZiA;f*2{yIWFapv+2ye}m>sv5ow4*+LJx%x;4dTCit^XNZb6p%<}o(eQ>ba*gd`
z%!M|4O%b;fA@NuMEUGZ%fSNfc%FGqs`QkIjJffE0pz#B)WggLC5Zxm6rA-9k@!c}J
z<i%uUDm#dFA)7QB4gCQ|rj|U&@Qn$K>STD_9NQHIv(QXa_m*l*;i9#u9V>mZ2W<f2
zL>9$#X@G1xCp*vt6yJXRFL2%oMT322WzD)Hc+eHrCtC(iDt^hWi-=?#Xx6?XJq%Sq
z7Nnqa+=G`{u54)mwBZ<92A@XgXQ0C{&kx_o+|xM5-t@>xR)%^Ar#Z+>9)UxJen@UU
zE#lPbcTENhgt(ZQ%pIr}{gPHA=->qVi3gPbYb1I1W$VHxr(YY-_3jf@#An-#@tMM(
znRWHhOmItTAiX0W@~88n2;%AM5b&hnU2Iu#LUtR4IV7^^4#wKx!H0Q)N9XZbb@?0Q
zu|d7Te>i=XB5An2*+hcP1>hm|OGF%0yD*+vKHBitzj^~sZ~o<lRE}X+?Qb4ZdIGsl
zv`Qhr`UFNyZ-+dR2#pkxn6j(T02QROr6nX8@HCn%Y|JuQZbtbfM=^bj1Ryh(u4bGQ
zpnp?-El5@b3JJ_pf_@49!%*&QPL9HV{Nyd74gON<Hvn3Umyy|FVB*WH7ok41TCt}(
zQ(>cxDi@+)%}Gy5+hOs@0mfLtk1*OSJIA}Aef(Z?baBkt#`&M^LlPHAy_Fo)6Cuq?
zLCf9ok$F!s#=ODaE3s45oX<w(OD8=-KdAf)sYpv1Vq;);ZVI=vAS?+OL7uX<oikSW
z>is?Y5ZhBG14$vs`!VravztdS2-o54!DRJJW*hObbphX&+8}IxbG>3uAS~*S^!YJD
zESFWsNrT!vf+CPPC<gobHribDG9@TdRPb@V!)RYo2qOHQt)G?f7+x=nt?Ie^o6zvy
z%Fz7q2;+gNL*X$LXiEKh<GXE(hyh@>F=&*)AWS(Fx10dclmgZuWkalu+K|m7<V6cH
zv0Mjx#2}@sR#FR=?dvFLn1jL%hiBP91E8b`e!=hy|LA6gphYB@5>ha86<YaF<)Zl%
zzmTQHin3Oq)2DM+!jwlg$Zz-ngp9(qA=fpGsFlF#XaeZLa3CnMWZo>jPWWy97Btrk
z4r)kk*6e2dQS$VNjwV>-D3T{Lp+sNulf^L<m!30yz2x<KLQG%6DaZ};8U2utr29H4
z$7ZjG&;Igzrp^)0cq^v&f#8Zq%4arLtuPl*j6?%uC&FV5;AXI<T%y>5&O3zP$l?dg
zK+=FajGFYWk_oZaJ;YyLe&>u7h#yq<yFG+!Kr`*jO&`}QVEHRnFxWd$DdPYtcrnUM
zZrGVIgh(82u15$A_-W9f0hXu=Lb0T3IK8~?P0Jv>fgs^qVl-1?g6YEPzhLo@*#V-a
zK*%5_hT2&?U7V@kk|0e7a~CT`)WVH*hCl^h)Fq&$P+I~?FQ<oq)2&i$cVDd>Z%|<X
zTg~{C=FI2NFklesO+N}JNoO~DxRK9)5DJ}(7P2r==+00MF_S(__qwp9xt(Hp-J@~-
zU)=f!3wd^jV>%yWyY~(Qs^Vc{+#sBA<mVgzS{UZWC5oVe3ZUs)9Rfy2A~VsQFsR`G
zpa+rWKB@DC1BNzGAcTc6apX+)irW>N(U?82{r1RSHnZaHXhBG;5tB8CjNYobou~s~
zpdd|tM#W*+&!C>K?h_%*6+hPc=ygskE%LOw?*%k?<8>UvPADS&(qG*mQI5odr0@hF
z5Z=O3goh|NLAY7Gz&e;$^@BPTAG2LAEWN0!b8}JQ(u)^9{eGM>BK$=}L$gWVUByUJ
zJn4HB`bVF!<;74;@feX7OoFZ-Af3i1;u6x4n7+`Cki}qFx&Z=1LLJ_Rd7UnVfAvX;
z&f_4|m^<^q#;PQzzGRh}gD^LYBWIU)A^s)D2*{ya%=?B~am!r1nO>I0dq1{K$O9D(
zL@i<=>6KE9ri|RKD4xPn^OUH#RM9N=#H)Lseak?W-cNCz`OW5Q9hoKRk@GbZ9&qsE
z#M)jLI3?Yvo66oVoow_DKT}3%AQ6$s$_3%8%8<dE>3AOE&SfOgINv;kES_O;Ig>7L
zMv#gbOfCL&3%M<n2rH{VY3|JxIb=0tUsnSVk<kFOc^;a02%K{1Gw6CnSS66R3af#^
zE}KJJ&z`>Rns3$x>T2-A7B-O?v+z7tX>Q4l%rGmcjJc=38!KUIJoRYr=TZtXX8-WW
zc||f-uBpM+Qg~%K#a#`z7|ci&7HLF<21x&Th;;eFr);iOYaz!#7yNJh`J%`oJ!^!_
zJO1xoh4i@Y`C6(}puPhHfik|h8tLI@+C@LjV{;LfIA|GgQ&5*vo|Uv58J@6u6OJ~*
zGBIipq10IXuj~Hq=`QnS#R|q9oyVl@qHs=p(K$LUEhbaSQ##RD{GGqK8c>8}F%#7W
zgTU*M=vDXzvMa{R;kc9=Mpf01u#`SwF}1X)XT7GE-}gUyJ2zT=d4P$BQ<dj+0L3a|
zfzPCZP({x}bM8{uQuLqbf?N`CoUZpP8ORyMzQg@rBc#|t!c`<f_kCAqQW8K*(qauJ
z1xtqNQ-NmS1fW+ZZ~eOm2n~!W*^wKfEmvHceJxQ>8XQ2RWdW@WC@cK*XZyO`wZ_wL
zEI$wg=m6Ou1eCkTx-wF!=cCN5BgD{FBpg>j)-ep|O@_8uN7+?C2xytO;Md9U-hDTl
zNQPn==+WW5t7soV2#kuT$eSkkf6ZVj!ocDPGN}YYtVVS$Aux$)%9l%Ia*J(g(~c>J
z{m^lzJf>H)NmEdzx%j}#nk>rj3IV)9Yje4BT`UW!8NgP3qKniu)&O`?0f9AAq|RVT
ztd&eScp1D)c>;nmSopvTW@V>wg(Y~Y8pnqkI1@hqy|;m20{}3uwx~kyP*4*ESfdy!
z9WuU(WDx?4Gq3C`=8PdrBF4+fGnKjGTC{~M9i9`5rKzw}hYZ|A!vW6@FbTO6(>fOu
zT)PadvRJ+yQiW0p3T2ol!oC^pyV9=d(5f_qo<sZ%UQ?eoeFl?coj!Y%{rJ*i_*v%H
ztVOIDHVL?q>bpjC;=SQ}b&&@`y8&H89V=i2fvmae27t1INr2b<yA91_F!5ggap(PO
zU{a;BG&5L?v3l*=xe0+xt<Tz44CU#3S+v#?+%S@RnI%KdPptXVu}hHh(H}|K9`wkd
zS&b|KaW0@bQ*!A#@Q5{k6=Oz#q{K%v1^8QT%9wMkwGjF2OE((XX%M+8=ZIDU2N3&v
z8`mt7GBc(lE#+$yH0&-s%gGU&FM05p4O48I*MX0|+wk6zn^@dzjrXq2s0K9a+KJFa
z&BZA)1XE7A6trxCV@y<pd1kOK0bTSDhA;e=n>$3my3vs0P0#sl8ZrR5x>?_~V^R&R
zTOj^FO=Vh_5m%)(vygi4wF4w0hLT(({KOJmVkO7wavZQIfdsK>CxV~89&S6)_jeDK
zrKkvx2sDz(6^u~xhoLVtM0%hx1QND!s+&8nTj8VM^R5&qDLA<qtNMbwYqVls7qSQn
zlIMY#@PIa(^@n`)y9-!mb1IIjDi6Hwz#vVqHEgT;{0o0CZW&1kFeG=})ElghE<uvI
zWe)#c!qyirUd?9b`O^1ay8{cQ5|AJ#EQ19fRzDRq=%6cQHUYuv>18mrA_<^V#IY9t
z^uyNx-5~3DJu8WUf~GPqf9mHzVkx~XTS;9~W!5IRCK-{c(#)(6zxESp=;RzFQy6}0
zc(WVJ+iJU&x*|qK80B=H%?~<K_R36*FQyTzDYd2K?`DN00ty6@b;aOAwNok3JVki2
zX=sgzfH9(oT(LD9t&;?y7ph<TCS4U9*30OFE6&AVZmq%=I6~*C2YFbv`$T=}z`KEe
z8HZm5Ug_12l@EZIIv%EuSl|Lxax!GVqlpkAf`wY1rcc>9ax3w)j8f&J3h!Jz{Z_P0
z=<Qv_o&p(TjJ36_2(f2$oxr^^th`eN5J(W?=;~)hLQsF}tHT{MX&)lCg0CdnG>QzG
z&{P<{!XNx5q`9=1dn<d>ScWKlg$2oHBC$>e-P)>76h|c4R6%6mD221S{EMw1zBE2y
zF3{gz{4ZyYttZ8yf@~%Kk9(i0vX#hc@IAm5I*gFVBhils`N+0wCs3t0#W#kDjGSJH
zLueCIpF9qdfVzN8*^)~!gsMmkFZXTm)LXZq`tLpoiE{U}CYPLF_5CJAok{O?T^7aE
z?-VVWMAL)N=(Y}>Tm`!;OjHwETj{i$@_R^;;ylsg;4|7f2nC~PHgrma!6Yv^8~RVO
zE9V{>D)tWlgwy2`t^I0bdcGDo=$p~r>(kD7&Jd(AW;TzMRASRXF+9@=F__pSFalo#
zC}Dra82AeR{dZr3_)N+DdW1X7gN@n+1zKIzY#@t;BdT(VfVEF=BNA;au3J2Yv)nOF
z=S#$$*I*u*e{$%S7|m!D^X|*}3_pqON#xRF{F(3?HF#Z|2?Aps!^1;_bs<C6R_Cn_
za0E}j^|h<Si*!9<|JzhKn^oyCf4R!h1!Z3e9AY3KtfO+wiN@lFy`9CxoS!ePAq~?f
zp=zuX23dn3I}3tMLq%vBl93T{IhC2)qo|dKm8ZcSAhq;WE#?uT37L*qgZevBzw3yB
zTgtXT`|uLtg`ewIMvWkG9SxJiGXTjTTo(5G`fuETo-<(s{aQ^U0M?1}?izi>z4iL_
zggA-{8(={|2uLRx&X>hFViX<YRuTp!Pdo5sQ!<aG<p9Wj+K=OeA`=ETM`yw>9eU5z
zU>zbJv$0I?8h~CGtfU`{vcppI9spK`H`u9$$pSzrKy_Bq4z?}we~nRL$9MJu>;U=;
ze|zPnR!)Y<fw9M~S)f=&;&4V83rcwR(s)ryYUp3(*Gyg!7`sBw3b*|x5keU^@P*cT
z^~j4^Yl_D;x$ruIgc`V%>IfrH=w4jzjErVBnC!5GYUM!en?efI1UzKUxCb!0-0+j%
zXKb)-K=`(rPGp6xs+P~!SZpTd)3t%w$Pd|J*Q%E@{SuReHlB*oHE_>LHD^k?C)2V$
z6+=y*r)q+v2*4w+73Jc9U=@r**B$l<9LjQ}1O9EV`s{`qUZsS>Sd*q1Wert*zNYxc
zeKpFSjX}xtB<ECnac!0mT}dWzY^VbMz09Q4fQ9rSQtOh6BDYU@b~FxjXec<L0TFes
z&Y5L~<*)w6Taj4><dzB~SCbCVi<EXsFxM5mQN4y5Co;=u9_w-?(J(SegOT`#LXctN
zJL7AJd!TaV#8p0Gh-Yf?y}wVmcKxgJGYqt=({~zK?CtNZTalu*9R;xJvt>6zfN~qu
zc{dD>F&A8-GgC88rrh>+%iz_Z7A*zbsmx`X&|a!tW^%1~@zl$7B*~65M6O@e{j1aY
zT(C{$=caNCmqT=JN^>%0a%I3x@szDxg8bf8*RQ}b!V8d1y%}VJF-K$7VP*W#7FbN8
zZexG)4r;JAP|>_6Mtr>U)9)3V=0At&oISxi)wK*!Q>CgpNy-m+famyJHy3yny-Q6g
zA?-9#E?Sk!UoKgw45yS|%&9^se(h<RLP{{+poC271kp^eowu~)gYJq4E;7Gk_#;1X
z8`46s8*vEwuMp!+$)$ch<^rSzc}t7P#!6K)f9MhP6ePYBgErr!B-D&$%327tfqJ&f
z7-t_<myNGme!MtUQlR%*);qH3FTJvrA#yaTLSZc-_X@O;sT9rJNQ<FT#xwRIqY}>k
zh|Rq|rvP+nJgny3ohWA!Xxfi)o%p~t%C&}V0ybdFSPz%_ci@gM=Ic;`*bH1#U6zKD
z%%Ypqib5BMy?x>PfBsnhcwRo9k<itV6X7aZb(4G|P(IpARWFF_qVg&{h7qPnoT)=#
zsV}h|(pWiMgsl^|94)_s<xUaOOwX~-af|(ne(M@dYOMWhkMzpGFoiF&ZWQXps-}Mj
zDAF%+NP19J)I_tHM7kkEy=>ys2f}B6$59z3#gr7Z`^$%0WgpgPCJ23gwXs$>8v>z3
zt)*3^X^k>Y)+nVyeH?3EmONb1z}4sys7{67(@Q)NDs7bJTs6H=P_G%od?1h+rS4?j
zh80Y;5*<J^Ml>n@qn;59s6**g7#ULcN8qx#3L9%v43<8=%yi9bNDXC9%W%RyG~{kx
z$M$3&`@Zn`{cP;HJ^`D|mtZQ>@;O!;%k?df)v`%eOm(Q&2blZ3_82Qdw<>l71nRRG
zT{M@Y??vSc07L8tTap1p=6JkW1X&JHfiTQ?)n_BhlF2j3EvB_hpNrXd>=*vxt%ye)
zV8HVGnRVb-Lzk%_&X7YQjhsrP7%phSdL${=vT;s2&z~*=%^hG^6}c4p(wd`UZGbZX
zb<$DR&Za;V42pC!Cq$8nByQMA!+zk88oL$};DHFh9XRext~x~~Pwj3nRekhG4k(Oi
zdfDJA(>9^rAz&vtLH(5}>*8_o4ot*2VRew`B2i1clNK1svIL4`+h5%LnP|iMFQA~*
zLH)X>>(DZB$=E7I8nGHNw$MYew$k7FNmdlEt=M$HpDAS$`2m$>(a{>rl?r6!8$LIu
z{#NUNvdO-d+I+DN_ctkDREeVOtLBO~UfP$u!MpwY-}Ra3L4cn8sx;9)K7GD<yxNo`
z3FtP^-4ttl5&uizrY53+R^5v@m=w7Y$(+&sbhGr(YQjgeK6Re1=?>scDbNO1l?tLN
z6C|hmRp2EkBFQPl%BnKu-AM|qLSsh1AFST~(Hm6Q?9oKsINy4xO+N<QKC2>k$&!gV
z1<9BdU@A!Orn8C)czR=Iz=uXkiPOxX<u#2Wlw?y@Tbwf?V-{ItADet#Rke+feKCC`
zb*8DFJga4X`Dgk+uhMnqOF*HNgwF8OjJwj<FCgeYosXF5)Ua{tR*t&DSSIZr(*YAu
z;>%WQ00x<70T04jeUsI23bvFUhFf$1ba#A!W=g#IM$Z@WTmJca*8ffD>>(_smOt+U
zi|nOS<>e%0<|V0DpB`zsNSY=J@tTVY8APv<&Z_CAl?xUO;8{^NtCJF!Sq%Ow(tx^J
zd=zxT1qdlD8{Vk*b$j$>o$23~+*|iEAK;H^g-aXs4Q(+~jw}x&*ccT88_6uYuVz>v
zHO!1FRlobn)37L&CKlq;B(_<_!+|dZ>VYuCpelZJiHm9O#07;%o*9|LYT_yx&KVcT
z>Rm{OJTb-Oo5O0n0ln>EhIWa0SDB4PqoW$&`$-f;rZ`$W#`Tf<bG|TRNLZMKJZK~E
zn0Q2iyHDOk(om@FwxqFaY%LB{h*z9ZK`H9zt3h+BT4z7Q;AC0-IZ^n^iC7YVI*3Bg
ztT_pbQdJ~9G!7tC1H&oYi9gIIvme~rkh)l?`}&3ZPeT`|+hg8vb;><jfr%<bO6}oe
zVUbWd!;Bztn)eX6NOSY-QeGXs+OX+7VqPJIuoPS4zEp}JA%j{J-PdyB03re&qYTX5
z84tp#_Tnf1TmKuUpIrZvXNK{#kV*4PgRV}LUCp!1<B}*Gz9p|N@U=!=HDcVnB9qs0
zsD!|#ELeowo!`R9EsaJ>=ahgPgM}jRU;-WuD4siM`rId9I>ZnF`n6-s2==~OHt=dD
zptu3`Mokj~oe+hq&bs1aR9H#x)6T+{E8S^VX{Zyjpwf2Ak?|w`<O?J#hmlYtkhrhz
zxlL(J40@t%Hr-sM*im)5L7H-KYmT;pUFb|`(&3~H8k;>>(vF@lJqRN~4*Zi0P6<#E
z8_Rm(-Wy*&7x_#XE5y5-8xggBSgp(qkDwMC=WEpP)OljQDd=TC_q7LEVYRXP%0Qsk
z!bYh{XLG7rA@o>*8NS=Qo6}+=sb;aOmWa%m7}+A8u_tcK`d|9PcQF$QLQ1^Rud1_g
zzB9{e@VPQ2P?6@ukPS<AMW~;&_=*x@HBO*Y(@SDG*j$-SNEqy-{YMada(7gc#i&?C
z(Uhdq0$_`3CCs^mtpup7r<;g&qW}3zlnApDX66D@4=@FxE!l&xaEevft^)yYER>k^
z0dA!L%^_nH<uT&(SwHsaNPsPu)&vR?6;Z!VK;H1VF+bP}Z~ahl7tNw55O8$qXsT}4
z2JeXgP^7%-U@GExNELiR^`tQl451*QZ$y)7F+(WP3Z&5#UNlgrQi}x(zjer&e46gV
zi}G8&4dK4(-sK~y#!eyA)0RZ}+iG?$E673zy5?`tw88WhBl1#Im_`tSl>wt09FxD%
z6AKqea~1{aKow1$Z$3qaCmXejeazBe8>4x2mVgm+I!Hvm{geMnBK(0I^RkY6{;n3D
z_+>+>F6~(DRh79`Ty%#b=ZhwybfwfZ3JrM720(;y3K7N`-BjNOMsiPw!5`}j4S;c(
zFe$n+YvJwJ|JpK+91L875t+Ayo1%%W*gU7osd-Fc{DA4002f?@k&nbB@HGULnZ6Jh
ze5w5if6Ax(z^=@cid+ez17bl1uC#pA!h=FR1gGF9W8HKTDviZ|^KgSUEW{;)NQUN@
z#!xk2>8v&r#$ICr70F|1Uz^TbMq*iJN>|p{nC4sC0nH&GL)1P8KWinIi09G&aML~$
zAyt>)K?bggd|>32BdBB$q^WJJ;v{;b&bEhOm_8Zvux>%Bw7W*em8mk|wKPk6T|A47
zfoQp{=@jfN69PsXUI7t^Of4(KYbSIgSB9!f+HJr8ub%Lp%bO5tT=+5;Pj&C*L#Z$V
zTv4{E5oJ#*Y|REdT$LuB$*~xMHYFj+0aGAA%MB2g8a{pH*<h;W6b{SDa2Mafb1XVC
zSv(+PA)}*@KKbqq%*xUQX}-U7L={Vyu3iJ~zruVf=^-N&D-}pUB%&Loss<tn>8%m;
z&^b0<#)%M>=xXsJUv9)^-Yj<abx)@P6Byl?V>83d>O+yCZ23;_4glZ|%t_pUf@S~-
z8@N!_?Ztcl_L#S$J{F}yXAsuw&ZeSnFW<|UWHw%lW^(sM^b6ugx|p;@7KEh`Dd_Ss
zx<DQNn1QoeC?kfjJ_G=<8YGRr2QQ{JE*}I9l7gJ>C!!js1%;3P)oqi{Ny1FN<oV}f
z(TA@#EyOtQ4uPdkts~#4MYxFR9PEHRi=*Hni($nSnB_SaAJsUF7en`WE*m%{fQZRy
z?G0U+{#)^~7}|Up*A(*r4O+xhjNN~I54)e?S<uK^TsBr}M&NTO{;>8KDV&l9El?#A
z*U&1XM4Bm>=A#HHb4!w)aI_I`=Jo!*WB=)9iErEr8n_)j6JroTLfuqs3FAaod}?;q
zF>!}|nR$A{etaC`5Yfsqvnu3rVHV^0nG0tf0uTp00Q^SzL4o0;|NT~P!}@9aEmAVG
zB|50rEzN`)Ox(w6sYPPdXL5DbJj|6ODw(6=WBQ1mv!_xV34EYp5w*0-lOQZ*l1hS|
zn1Y7Hp209C6^LdQ6$lQpfoAv+8{WiG`^3*Mz?+2IY;Gr25n7g6Z1IMKRI_=uUMtg*
z%~m%Uh8yw?B8iCd<|-qhVyshQ7WmpFC^yy^P_$cMbc}L(#9P=X$H8iw0}!qaZ}J?#
z_(&U;5-fJI|DW7sVpKB5iS;fU33aj@hNA=)gmMevv-&(J=tH%9fIbUz`pnQYW}$GO
z9WV^M+CZnIB7^nd9A6ji+1&q?_{lt$^1zv}H6JvV&w?VrVg4!pQjaE}h_!}6;pU)=
z)Pl<Pj~KXWspdIl1A=vBXyfE0eTT?aP%XO%i1;rHWAsbb#>*&{i$C={{f{wZElypz
z08(IpC)$<;VPjGp1~WuMVq5Ag4(OCbTsIlLJj?Bo3+9<Yt`b{(u9S|It3a5dq2*$G
z^i4YC^dZESw7+^XJJx~3HYqv%d}jQXXaM0w0%PDA`tFyFg_5G{l<%wGKr>-6@BA5m
zro<2rwMAkGf(eeIIEvoES+pI2M!!c??R0OLK~_b=HF+KS7Qjmot4hDyTkt<64aHRo
z@h-wueh)tRh)vIP%tJ_(^qPpB3~A~67=>FP-2{t62%W}LGzn|wL)qa_3%Z}9;j+Z4
zfQyW43638yiv%QK7}`!HY9h&HsWE&eH_-R!@4PDlEr;0y7>HUvM5s~%c!Fpg_cIwY
z$VibD{?V|$#)K%12gwX`G#j-WKq8k8c%Ttvcz+)vp8X5<24Ree&AJ&SBpm>G5zjk{
zcM&s$?&9g+>(_wVVPJZ_eZu3ZU~zJrS<a0h%X4KdT}DdzL?NXDyxB8?yn%*Haj97~
zyfc=xhfenj{DrBrY)I4!T9QSHufm!dfoo)K_J*aUd!&8)FWxYA4!2n5Hy~~Xu$AMY
zR<wj@Dg=Q#R=Pw)&uDfcPl^p{l{kn9VJ?6OCNj~8jf1Kx2rwpDD3A;Ys<H<Ocnql)
zFi5=&IC@r2{UIBOv10}ij1ASPId;24P<Kbhq^V|=+OroS0Z&ua0=D2Qt_WA_9_E0s
zaIs8ifDnQ#CU7bPLB@#oLm~ZBF`)zeQO?S#WEn+RY4l_#qeC8^I+mBHcj?kJW*loH
zXG6+e&qx@<@~{}V8Tz24w?N}Qp>YKy%^L&^Vs##w!;timCR20K3+C|+oU%^<3Y$d;
z4FEy*g1$D+9?NS-6gX_MS~WQ&e~3XBaDhbFvb0oWJ;>~3`mc(uHAX?jK1$x!v?Za4
zNl5$@Mz~kn2mxIu`%>}P#BB|vLcm7MSGN=5`On_uYEK2?^_bo8>m_5L7~CymYLvK2
zeQU0azJQ)rn*aqtvot<U!?Oh83Z<SAC)J->rpa_T9cDQI5L!lU36&`@@O<nJ91ef{
zy_g&%AyC1f{gTm7Jc5?yKpw+HJ?M0!6TU!KgJY3^IWYXw(3ca;FpsB#q*%6Q7C}@f
zO4Q17an8UX0^#dGxb3I@f6RO0`I+{V!-Hlrg*#G`>zdML3Yk28S$nV&IwMt5*_rU(
z-+i|$GaeHrCzdSC!Xi}}D<TT>B}ZQJw;1&{)|~Pr!E3V<Bluw74}PYs4dOD@+z1%q
zjxYuWE}IHvq@c{QgxZi#-!jSezPk{1jCR_HN3n9UlZpEGvP*#}W2zHm^bwT}$5_r{
zM6*OZl&rsMk=SAZF6~+3QpJW9R8hs!v?G&-Pr)Ai07SL!$a?9U8UDq>w?Ea%=<gUz
z8aaVJob}0(h&eKJWA^au@<O#F{OTN!2Dh>d1;Sf&&`+yHn#?5LSqa6dO)AY+W&`Cl
zCp%$KAfPZFVu#+~c~K_|&NF5=7#;6pf|=Yo^d6E4gc*z>7tl40#V`NSYva2#6_I&9
zv%_-!s1`~25mRs;jo)wyGlPD)nMg{WgR5UQ-wC^t;YPrK^NZb&a;fl`nR|d&1O8Rg
zOT|ry{*}~+#8OC%;9%F!!r7mD_kOC0*+L_p^4W8IYA#o0jIstvv1}6o9n_@G>!{y>
zvg`rwN1l#nGU69d(`S~J!+ym?m}jmAvF}WTBCI8^QNLmTVSrQ58&H^4!Pp*Ut0{W`
zD|X=GCn$rRj<Gk0?z>Fron1$=qzC(zIp^v{9_?kG2AWKs1onX*d?^Nsq|h;2npvlL
zxB-S6w=(O2naUTAOcNY}9LN_e1Ww8-o|iOa&rjdz?u-#^d~lX3#`%g;iB?#DAW&>~
zwAY%jv7wD-=hF@YO&u|pIgA3qm?DdUiI9`KCt)O&AnVk0I8W==+?LmhdVIqMoF%vG
zjlT4Aj+acf(G}EpX?#2Li9v)NXp}Kg&0gtoc#%MFBX*d;MpXwcqr)Pkmjnzrn|zL2
zaEPdA0G!75ah~;2pjG}PRUPA`U__755=J8H5J=NQB__;ZIyu`<wcbsk9#L0QPPRXm
z|9QzMr>y}aMU-e`&TPRhV*FHBnc`&8!9i#*z~q_F5$eR$mOz3#mpty*%s>%{0#F3g
za-+V_WrGmZ^Yr3(J;ZkPB)?3Z$8Z&8tlHWU#7+-uG5BIxSsASpvt^3FQ)#eS2g<gG
zl_srf771wq?G$@RqB5u-+?mDexY}Od0ojF02SPTooE<)vTB<wA#>k%V{>>(4fnw;z
zn?u4F0hwxOUBV4~7^6mckzx#etJw7Np-v{;NoE>BNtD7;-Yo^rm<$c_W0F)&BAh@W
z$Wd12R2+WfPi~~<VhTegVZVeD^ZoFD?GbEus46NtX^UljtHu<gHs^Sh0IjGcmi!me
zIgnd~e`W|E2Kae+V?fYw%zCgS=<mdgcF`yJG`KJhzkn$EIks>(9DaK5yOA;wyzkHA
z^HSBde1a1nN^c{JYK_57*i&49dke4`CK&3cO!4%yd|povo5;<RO{M5&dNj^{i~*oH
z@W`QWZ%UJFJLx>e`eT*G<X~ApaYXkP246ye@&u4VN51jrM^3!^m4{Eiit#;(H^&Tc
z`4T0MrNCE&(@v4yKU?n%^6n=0pH`NNfwoNy2Cm4{rV+OEo>?#mg9^EYnk7l45kpV{
zjF~23`MH#bRe_m|NSS9)%ksB%)3902oT9ROkCH6jw(vShb8T#~k0QUbWIi!Bx+9;?
zGkW~N@_m<=B-|H84T3a64)qiOo=H2ah|-xM%0LAP%S<lCfV(EVSOVxXVHvb)VV7zb
zE-gveAHVapKi@t<b{hmMbF7`EFl>DUUXTrnVwC%8&|*VN#`l;2CLkN9+^nihCD4nT
zP^!Ruwn+i5j@*3=OWTWv1ife}eo0Jsm*H~!dLLg0w12}S`e(=!zS(|?@8i|EVblm7
z7xYWKp_`BI5`?Nf%GmUd$gIegNhRTBi3;IT_Cofsi$f?~lf*z8!l+9P-O28qa!E8I
zGD|EEQ7ygia`b*``ZkIOer(zhut(zlp*DL3E)A$Mv;J411<gMfUpA1pmkg|G#8~2N
z?8O7jY(_*A;WoUygtz77o0bu9At}O+b$lg=Uq15M#OtSbOs9kMMaE1d^yVpEBECmv
zvq{OrD&zizbyR|;Y`}Cuk23VosX?Tu0&ffBn(~ynb<6~7ve=+_363s?g&~tVV67l8
zBOUa3OHa27RXqQJ8(#TFo?2iLFi1vVyc8<FX9i(SJXBvA_rIJd%-Ayz%SLVyB!q#b
z_>T^w++A{D?A(GPH6znFw;YZoEVG}2#v($&841G<SA_RlPu+lEdqo?RsColBYxzAz
zWTS=Ip(2fxhP$w)5)H+QesK_x+(`r~IN>fC#{`4@o(eB4zw;7=X8#0|0q9wwRA3s*
zXlVg1C*8My>4#sNpq~8|CHnyKned{*?_rgk7=!bg4szjg$?#zQKB_(=v>sEtW|Vbp
zv6m9DD!w`}qfIoHYh>0Z7C(f^0$YMy&M(2!B?!ZEFNG<@{KU-VI#)#RPyHj+S}(9+
z#gbqaA6zoVYvOGEa_ymQE0)#bn>uPW3y_gqG0_VmwvjoMfuh(HKBKrv_~lrYt_@wv
zLX@FHJj0;lN>5S!`u||SHTZuuEyyBPhqPX`=Gt^dsAxPDew__1-l+2+*V-VV*bwW2
zsy3ZF6r`0#u&tNe<kblas!&1}6&pCxv#I5?w2YUN)jMApS!H!rErnmBdhe1Y687h*
za^-8CSr6Gce5H&Gb12qLqX#CUsfoXqry?z-{GgTzAtp_+a#>e-te<`6JNZ}`*I9c4
z3#Eu(aLHh=r6uTcl0>V?dP<NXTP0mV($YIGf2t3;-^quvh%sqaqWKzOW1^MIxx_6i
z1>2rx4CTrBM}8}fxb()$bw%~rFTUqH$W|)LqPmv6m~l}M6BGel(sgvXnSo)0Mqw*b
zg-!9`Qp@~G3-!)Nzwn)0DZDZq5`+bOrdW<x@am7%5#^4gh1uo8u;~?->zD31mcQzB
zfCqv=1#+alXqLg3=36dHn%G!dHYiP7)bKu@0f~WhSVe$H$s*b$+Z17CDdZ)oppGxn
z81eMtGk<<n7!`@%&Bz1(T`!a#=D*nrN7eQq8$jue$b?*1&IwF`22W#z8Ot9iSJX^T
zpLp{|CM^gtYvM-9AIf_9NBMRy4O86~Zi$&x%5Gkzm7lPraZ$4-V-ZBj<fs5pUqV@W
z6u~3L0G5hi=l2qfRDGR4Pt$m3B7>%Iy+7PYaBOw)KB~(5>zc+uh(|l)=+<V*FQHjM
zm=)rm(Oi5npF)`ia&zKLc<+aA*_&c;O(d$XWX#k|Vi0Hkrf_~`6k>AnCLAY2iL1ib
zEu+*D7cs#^jSjw-@SB~i%3)_U79ShA>b%AW0=9b17>9jnx_on0P!*BjfqWy^&_G52
zT+&UMF1M-v!I4oeg`XW+mhRbSmi}<K|D*O*ZY{FxY<iMrC6{EvRk_>{Jn*K%YV#Ff
zh0TeJh%Ob!>AKG_x&CF)KKr9oA{Z80g8;<q8iZ+>9X3k3Ja<*RlA|F`Z*D9`hwRhB
zN<*>Bm<W4>*d5?vP#S<&vQZLl``>$!fhOw#56k+woQX{TxmM{qMqH_qgzTOnQC3|e
z4ur4t3ueZgFbTQ9IQ6hMK&No?IxZli&0qc1Tf2Z61Nt(t0$?nGE@oX%-xCHodMU-5
z@(Teo#a9AHWLOy~W2h2pXlRk;@O5B25Weu-ZEO`w#Y^Yksv}|axRMHzKlO=oQFnn&
zCVdTQ#nTY7R?J-ejaZ}PA2uT;`Ai4Om6B#7)kxe)9tBZD-IDW)Z}UZ^?&z8D>vQie
zoLlICy2kvPZy#90I9C^3smMG7v<6;tKk<6!E69Mx(xk3rU-%{8`P|=+1T`W_u`+{F
zoHC7tTxmoS3QrH|OAe%`L9GM0>g<o{j3#BO-E&=cL-<Q)HIgIa_EqJ#63dlxq=QR#
z-+MKwWYhwrK&~6b3N;u{OP}f>j>TRs@5yNCNbM#u2U!Mzx=C?*;AM0855Mu9v;p-5
zgaS0)2xWz+B4oI7Z10j`w`8zm>=Iw(A!SBMcoDI<q6_k=U-(YC!7QLDCNFfBfrsmC
zRhBW*k{RChtc-K7Zkr|%AUVR4UQ18EiWl<e2XE}Ckkyrf_WIda9+ZH=h`1iQQXWeU
z;LwrrcP}%{X}!_`2`Ly9q@oO%<vFEYh-Xx5#8LhDFEP(+!Gs?8q2{pFXC?{OZ8Z$s
zt`&YYLlgK!#2iFXVq=7h4fw)NFuY(^0NH`4OM4)V0)CVH)uM_<Wu5U}lgLWnL?g>V
z19oAd`s(-fEyZzEx3hZWM4KkdRs+Qr)nL~VFTq+XLMvIrx44!Ps1ECzXOo!G^NC*4
z?JyKCCj4W<-6$fRrxMV&k%`a$yB;-mh$bY?SJgT)g0^8-AZJiL*P(U@zRsAQdgH1I
zQiEGVBCLXGKTAPPlEFU3;h+k`nb|2LtblX+{CzhpS!x=Sx=IJQDB(Q8sMLv&%d_>`
zjkShNWFsYBJmregyUURZPeBXX_#idOl9tj|Pytav$;Qt4!=5*Nko^#osl^kYHLc)j
zL;V^cXPgaM58yg>8^N!l&E?yh>2Ag=1I|nEs%7Gk5btX^AhhV<{G=~(r|{JsATyN$
zYk4|dQ*x9VmFux2)uxtBolWCjOr2fHR_fcM14qr!JDWIUfRDE$lSpzPJxj4Oz3NH$
zzJH3zn++3N8&nG6%;XAs^~lTC->93ZCYhL9Rd<SOoD?CdEzwc~E!h!z>Qm~>R>sI&
z&`5z*Kdpo{;&a$<T6BkZNRo8kK@OcUzJ88(o&WLM7~B@Wt^NZ2TT2L>hg^Yu@ZtJ)
zsxFXV*E#TwNL(7VGA1^hvl4V8ytcPh&OF|ybl09HRR=0-GeN~=va3KF4SgC@?|kBy
zFLWcf8pyK7sE}@aG?fU~6&EdH$Wt0C!Ijd*rDN1mgkmsfimWAlO{NJlX3bLN7N_2=
zkzoJueaG_Mz`17YtvYgnI=sN8IN2h)a9wC70z#6`fNRE@5M9Xr$cPBSfSfIB>QFeP
zq8vPABJtS)k-yen{BP4}vu-pUFMc(m#Q8X1V`w%xWMmgRzg_#_Y$ds5&M6?KpO?lj
z>GCJz!(0dk{CSeIMdfIl(60jt17qj30<nPi&cRQM4i+*BUMrquym*Fbnl>I~j-E47
z|7)9c!@LzVkQt(B%;n3a7>JeBrMgVNW3^4DTuIquQ-Djtr8!$Q5Nbvx|Egbl{8qYs
z^Lh~TFstD@y^c)he%ec~3(;miFIJ~;eYvA&l&b_UJxGe(6Yn-;V&tz>hdQZcKJSTJ
zw3S@^p=0YIj4WUD_dpmbq!I*3IC}jrpXJ5cizdbmc__$;RFq6sID1vf_~4UoksHbc
z+cgme1ach_o~%Uy;UM{dZ6B-*S`)u9^pGmt!{PKHa7<JR4dS3bB&IW>IRiCJAFS@5
zy~<4FZ`a_(3d7*-AeRZmm(F8Jt=-h#m4-%qsZNvt8u`ZbVCIK8-ubi75<%dC`dUr<
zOI4i5&NX7?nj?E@p?r5Vq_J)<(Z<pZx@eb7iRuL6GmvT!O-4GV;4FM~yyw~s+igUl
z7$cR+T9om1*|s3mSMWp@xxl?-^<f-*A7eeR%zMmkZ*qJ@uR<|En^^@E`G-`dyYl+?
z|B)gq=@`{DO<c|Mdmy;a_z@Ocij#j{ib}4wAR<q5yEM=$S0XdX#b~Q0#jqm!X+EAj
zL+uG<t1zkwupouy|EpyI@e2vGY~J(g^S3M|6xL8{9RnhZo1-?Eq_<@At}Xct8DX1e
z5etR)A>hn;GrR{(8k8Zq0ANOHQQBZ8x+yLlAR-JI8>9G)r^&`hx9P>NeC_Yc>RpxU
z*~xij<RX1CYwAR(e`b}Ina2p^><yT~`?fI0?aH1H8aYj$7&G{!=0#tDNte-trWD17
zlMN{o1SP{`5Zif^8L1)e%Ot^h<HHlIhKv<*G1O(8jf|8}hTDGi8Yp?mHp8I2UQ&i6
zu&hKkS<<DlQu=1L*%BSI4<F(}QDKOJqw|JkgnVznrUxC@<_d(Ii8nm?txVA3UyA7t
zB(iZ=S!;YD_U2L~i%>J6%}OC%^9;?3D;W89AZ%4amD6FqWBowC0L#%&Su&<CzZQ=k
z|NA$7eO&iqCg2E-3mkqJWoMM{3gb5$F^4s&b1BHm+2Yk1+_<!*oqzMDSCMVU*K6ij
zI$L^G`!}`KQg80M%rxcKOjsw4=>Y2`nSsn9R_$mUx7@=r9Z<*;5sJtois@>ieRA5@
zSiIdYuQY|%a*Q=|Yp~bM{h;HQUDPwaTSGr)%bhZ}22q$!&6ML%3`X;H-h=1avBE%Q
zD<FObtjOXNWK5z|8c!a^b7LCB@a?6Wr25utRH(^ptV)w<Ja%OP)pdDBX|RK2oU!2z
zSun?T1$kJQj*`kKKL~+>Nm`D?dUEjP+O1&{Kl+Wn{Rplrn#A2qSI7T&xK3~Lm28p@
zK0&&f>t*)HOU+``x5;`f5q1`ikhOym6v)?C>l_fLY1qs?sZ#J&SX}qbV;)9kRz#&G
zSSydTyJn~(B@}Wt52Pm4>K>M$NyQYwKMwiJoygQBUfmKANCTqj0Mw8NznAET>8o;>
zhVT6`>FTS{heCcqXLK7o5L{ou0D^-$!A@kA=eUHZu`6WwGWrklph36h^_f-_tYX<0
zFk<JttYUBao&U7WiU<MpHfS1*26`2a;n}DJq}spUo6zoNTcdn49|s9~AT0V0p*rFq
zD*aPpB@kMQw#845IBwYLNNPCRPK~SJvRlR8<e&WuCBE>FU0MOd(Y_Y%cEfs-&=8`&
z3|&l@nBw(f)W-*P6Rumd2m5HblO)mQ2pH+T{BStW3_jl1aJ{}-a^XMx&}eUe-)Q|X
zO%o^cAuXT$rx?5Ayr%eSGJ3OTwW4;5x3>;e`CN_r04WzbN$c-u+t&*m%wRKj2LP+F
zt4WzWCBy=dM{yXc`sjUvK+y3+P=QzO5bHtAlW<KA)T3oy(jOUq%zt?g;U+$*NJi(l
zaPPm?^6;m?Zt4UV>@^JmyuhvWtldNCrEa|Yx0ZrGcyZZl^lSg-FONPvZk&rmT{k2b
zTna^Ha$2~2c)ja?Y`lNH`mIO%s8geh1dGl{L3**Z<c!_JB5lR7?_<i)7Dn74g9MV0
z-9i_UPWmkeH704VLs}qy?UT2pfBhZ&yzs+2(&b)pt)gR4rq@8*T1N(xkk~yg{C3=*
zuqCp{HJr*-nL?HngB)YE`}1h4c&p=Cl`USI0VlyJk8Y&C>81uVde&WW(~euYzF5<I
zA}=o<=)XCp5hZNcaWS^(N*(Nj^m44o&Y1LAQuKGn8^Xa5Xc-eX*heX+J>$=~m2mv_
zyZh>_Z_Uiy@DK46aTL<W58`{{hO=NX2QiL%t3`V{u%R3XR!fzzEv+;8oF|S6-~?cT
zLO{l}115;Bamn#B>|Q)bF}~=Md*Hwo{b2D=K8{h!gIiNJb3Iz8@<qFGC?EHS5uOQ+
zYzc!Udg4k8V5u;ga!&HpRwLJBGqoHSt9U%01p;n1cd_H3LT46pge<mO1DD|@+6(PQ
ztF)`t>LJP5<8BJQeZkOzhkO1Ho$=f6xzTDdWNLQs=KARYTB+lR$Ee2rkBpbC{xFXE
znAZgD5B7$C;PzQw9H^Pe^9I^c+m26`N6XxWop%p}4W36hAL6m>fj)&<03GT)2`p~A
z1-0jTi&QF3Iq>>mUs!dSt<`w@xBl%D)$*xwyj5$T=xO?s+;jPG;PHi|m?O6DZci%i
z6W-m`e#UoAy<CQ?!ZG_~esnzF8_bZFbqB`#T0KvMy@LsRyo~LNM{kDz>WLeB2g0}F
zpw{*eB2tPpl+!4pVIT*+%4pvvCKS@9<t2$r75=o{3VhJl$o18}b$ic{A1pAyDUKs6
zCNw%(@7q-NM(@7s$jeb5BjxP48b(9*_VLyS%hsM+Yu?}LjJBNzy*Osj!oWnm?QHa>
zex=-sZr<x!W5L04(2Cw1w_i)_O`a9S;H1?;;`fA%w{HSop#r-X*R`2s*E-j<r+eIK
zXRBSQvTfc1vlgAW<wr+-h@|nA_uVwKP#)Wn1XD==d-{^rS*C7nD!cWTy(u4i@jq)a
z+sB=JEN(^5<pUn@zUC&VeRrG;9KOpvos1^KUOcs~8Y*3!#BQ~^k=U=BL^Q|@CJ&8I
z`I|$}I~E>fS!4GBcd7~EXo{QeZMB@x4P7+AgW>c-wKYbrIUWe(Aoh7rtL5H2@OZ10
zJF0g>b=J>@i$l+=nb^9onIt=FC-ZT=PE$0I3*QT@DLA+{3{QqTn^0BN1BK2+T!HBl
z%Wc`T@ddE)hH``XK6N*QZ==w*7EpSwOWP<mtR0Gtf`;4Iiux$<Ct-mJG40nF+Tpfg
z4zy+O`~KYKLP;eF<6_J1@7;vrSSTl8Dmm!|b*LQLWL2h}VlB+w+;DqayW;`1k+*DW
zP!SPZd#s?pJ?q1?4m4!N9v|u*vKw}2)riHwZ~bA(K`JE!y;Jjk3<to*&h+BvezcgY
z_d-+sy)F7(6RWk5cf$jD>txxQ-W6LDzO6YWLWvc_JYIO9>Q4U(DA3eds5p-5h>@0E
zba`|z6eRF@%p(y0W@1{hI~EluqYQ(Mss0Cb=piYrz3zqA7p<~{&5YaMw`IJy@hPuT
zzGtF0bhqwqhM`M(Ya$9;Ij>yng&cbrZ-JnihU1gsX4tt&jXQ}|Vh*eoqE70wzbgLG
z=HBd_f<O%7q++#dZ5tqIJN0A49s|b^dcS|C)#Rcr2N$pCyli`0#{23#@RMFX-_Et8
z!}*3Y_;~GfG}dF)$LxuoiPy*N(fr|R(e2w*l^6(7xX}VBZ@O{&Jc$CYxT_UN{vk%N
zIb_@<4bT!o0F7LTC<ib-Z_T~1f45QcU`wi?5|8!{U={R_-yI&{3Y)xoSjQS7!=o84
zQ%&Cq5MXGCTDU!7mJp*wCj1`HN*Gm#|L?#Hbj=~j=*-~hq{FzbWG$T<EwqybP`6Lr
z#8Lq`(i3E{a*Y53&1=*iJJoPDm4nbqu(bk+Ru^g5#Y0tS!=<-YR~RkV$YttMRxyC4
zP%em2I}CTW8i73(*cgKd4o*xvOf_mWp)%)dk65Ek<ZW^QVA;2!ji!hACYnl-xG}MA
zI!U%VRsqBm{oPFjpJm-cBOi(d5kA@%4PsXmZHv!M^&pet{=?e)i$445Lsj(IkZm2P
zHZTV5cpB_7m!-%Jnn?C9{obtyygNV|PrQA+ZpC$|C1x&b9By?Qm3*BCi>ytI^o4i=
z&1!(BxKfymHDmWh&xwk55K}_tgfl*G2>27S^BIw07o*T|M?-tG?YDYRjiWS+gE~G9
z$36O&JVQv<)ay@d$q>^e%(=Sd*4_Tl*`CM*WK5P#LyQldvPdu(>?gdVTp=2UYC-CH
z(Hse8Fw98Ix)rl#mFW`ng~|5EzXrk?(QQpQJEJ-yWnC))0R<PWk5G03n&}~&Xeigq
zCAieiW`oZsLTO>Qu{u$oMco&Xz!g!vMeJ6sj&7~x4iZDnmB!*@w>Rv-gF?N&V;;6}
z%N}#QsMv(VtfC855fq`x6~(ia7|X=&8pd*=Y12yDs6fmE<N2E-Yfmi-&59NmFz%BE
zLlrGnkf%;!D3E`G*%=ID*3*Ky1C8-`;UB!qns=rh62O(gGiCSmmhrp4e`9{@N2_ln
z=TG^~m+#(F8~ku<`c!r6q4MXMgEMw8tl#sA{LpZDE1kkR{rTvO7jDdNxN9$_E3MSi
zn;EQ+zMtCNEHoF&-oEn2{N#(}DF4Rz?%IU=31UBld8R5J`eyJ<cu%<CB}36yn|8I;
zv>9s!^!<<Hn@%r;tpzXG>oR~h+|`VUC%J>1xTlZ*1XY~I!Vy1w_D|mR%l0hD!>4#A
ze6Bh*ynbuW8-Ki3IsJL}E4AUfx1Orr*Q%0!U}ojy-Qj)BtqbJ`+=0`1p7NpbvEW4h
z(B1LY=&;A+;_2aPJmnxaru^otPn-INa#TFA{)BgEebRrXye)PHph$3kFpQ@@6%L1m
zLtg7(HEeB0vJPrsi`(K#Q%!JA+I;-5m$=2&0!X=s$i}&NcWc_AUb57~jFyJqv#oY(
zVccP0uQkZMKGd3Il4d;lTzM${>F*fdI_D0Mz;XxHPxB+6oNppY6DI5BlhOyrBX6Lu
z`wsIq{n+5e+;HWaKh%mFyTB<|PJhg#*LC^Jx5JHI%MJ$*dyPxqH+eKjKk_7l(ezI2
z?IZs4@AMX;kzjudr@Q#U_VkYW$Va_LCI`QgI~Z=MA93$`a^f51@|`=pEvL&Pi_du{
zj|6n^j)!}PAIw|(n`i5MfC8Q`tlx4Z7<%Xnd~SC5ty*yQ=#%5&iQq+VM>`x^{De1o
z=E%?@k|%sHzvZqI;n~yCk&^k)x_x0T$QM4?o(U#@G70bekos(A*1bIb)!P5PZhQM!
z=#c7V3N$@{ebmzIh=cro#sSUc_7y&GG`RCadviQjfjh(-lW<Qw6YSkwh}tx`&jj0k
z_m<HLPlkQb|45yok+0;F9qm`v9|_n`r97L9iQXN8UV}w%{VU;IsSx$;Z_$3tgE(7y
ztCQ=?$32_(xR11loDJS&+vx{|O?xJwHL~A35^SH|a%6Z<bF%LO_T|yQnhd#=XBFOo
z0%+sorK)Qw`D?w_wnun14#=ePvik4Z%@ZJJX7dI<z>4rhh^Ap{Xz>r9p2?N(I3ItR
z+y}jc^$}{FUU{V6@70e~ye%w7A>Kh(As;9<ANu@c(p*<h&bH4^+ri``XK0z(GI1p5
zZLf3N$<W!4XEHY|oH7BxdX3e3B7EfY^>Ff$&-0uy*2YY*4~J?l$G#>8mm@uly<lHp
zSM$@}YJIScfGs}MPKfI4k8QeF3%S0LCjS{G;8d8c|Ky+j<!wb;N<Y|c(CYa}J=ov;
zV0%mN<Rhn%VG~Ya$2buad#L$PI|>SC>$xKoOibR)OblL{VEVxm<s(4>DglQ{I0F9S
zAxx9Pj{25fz&;%X1aIqwFY5^smX`os5P-5T<Je&D_%<Ge9T2jc2}S?`XHi3F=W^Bv
z_?sEt#}Fi<ZN<R;!RY>PdjE@M?FAe5YxGW8tsTjh<n^|_CHa&GSfI5%*voi~>MK8X
zIt&RphBSNcsM9+3(Dat_d<lr?a^a<RAYehr-W;t;PZ7%siE&3ke7fkcQX>nRK$_z@
zOy?_D?W2Yzca*#~5Eb~IvWbO~nq>WRtlLa3X`JWo;B=oi+2`)_poD_Wc=-E!zjgo3
z5b?B)Jz-7nn7|;|Qr^+-Pv&xyFO?mT1r5A%mx>g@3`#0w>Di+u=%*kd*LIR*X0umx
zxERwZEuP4k$xTJjY7x=^5}tslHzWzb)(Gm;5aSH5;*>MJ9>vHQGK?e!M6=jKi$DLi
z)tIYn@EV8EP>dF}aK#V}B<i++yJBtpXb?tQlBYyvkb+}Xle)qe0mCE0s@145c<*eT
zH%{~>Lh;Z;EE;Rn%86+Wrl75LEE~oh%gRS9BR$X{v89;+F68?Aq=_-b*qEZe?XUWH
zox*g~dc)2WARirnu7+LhoJ_)CvM(6z;}(-%FKRm85~D5;)Tr~qzUsq%*m1hS=!XWd
z^QL^E2O_eM1-+1XSa^NBuL#{@<6}Tka#tF~jSsB@yN6DJkCS*f*cFy_|DS#RCa<iX
za}RQK>qHLfK@z{W9(bqg!N8m2eIw@<a?{Rqu6&+`X1wOf`Vrpua2WTOOS!|fiY&DW
zjFBX)jFuf{M>QWhQ+F$)Xf2@K9ZuWu?nGY&TM$Vfo<hV-``9nz<0Lid%J&ZJE(CB8
z<hXA-2p9{5VZ-Wt<In%|&Z$N~-`O<Jb5Gxvc<hmJq<-|=ZqGeX9<nFeEbCBo^G<XS
z&Jd`JOEw189lws#8r0q#M*~^bz|C*r8(O-CI~tFnJ5W4#B!p(1eM!ht>?XLNS(^kh
ztbB+X3i=P%P-hK)A!*nRgF!z&?SK5KozY*8{h#HH-k#{E#=f^a_>A|)JugNdYVAut
za`eS$S8Lzov*E7~47~Zs#mV3&cg4T`nSXK@_xkNIew|ym_;EfmbS^T#H+uV{iyzZ9
zE_%sFs@X-t&P9Ir@m=x0$w$LEF81?(^NJwuUgd*pUuEkGP>%kcfU@i&FFf^oub|Sy
zE-1D8`7`-?cm$N_d207BKJ`0AXiDRHE;~eQ=^-Q39Etgfol2Z3d#P%op0GahBK<^u
z+kd{rgkZCGq`&kE_Vy)5gr#ea)lSRM)p6j3lS%PqH|cl1{24E5<PH%Rvnq_<a8A4N
zR22HP!+Ec|$(#DnDY$lL+=BSqmAhNbVAkImwR$Q{B0uFN69);p`OOc-#i)8$t2Una
zxX6sbWTe*srN6ZB4@GSsFBU8PTocRG3Ia0x?$EBN@E9i9QNI`vOZ13-xUm%v4Qp?R
zp1A+quk;P{BB1fhLmQ2-)$aF>GR43?StekG>5u*(z=FI+Cc>(Cbc|1TG5e+o?+}ui
zUht~1yY&>qjNAbsGD#GSz_mdE+VCSmVWJ~@T_`@lpQ>zn1edAd2Q8k836l#RKB-Uq
zBgSSNdL#E9d?L5GqZwEG&*ba<zZ~@y*Y%Db^$!5Bob`dE*%KcNZMKZUN=^c||HZQH
zMbmaYEcUc^#e_=<7GUl5ulL5wC9Xde=Z^XVN0A5#gO+SUIvOL!Xfix8+3UpC@C|zE
z$Vr?bi@-_4u3E*nf8cE6pj$3)@=hnX6OZ{`{IXr&SpyYb?DjkCSR75bc!pbZ?Sn(%
zPJhC7`+MV^&7H9|Jw}|%^$u0<^sUj*2}XO1Zm&1xdgE=I=!WA>+jyCF5CvncSvT;;
z2oaoN$Vva<y!#-S+*v!lJ&EgMvCRsgrWpA$K7Q<{iIuL$*$A!sg5QdF`2v_wkMBGY
zU<J(n0}_e6dp?M6K0R6|35sRlws$oxXePAfojpu!qf%sK@pQB1wRgqIRw4^=^cG0k
zs@SDRLIqbOf<h3`u*zuC^gmVh{mn#=f^hU=m_M*SCQvbTzJ9j#9?v^67%qfS@&vY<
z7u{uJlrT4HEU29!QZice#@`(0)3INBD2WH|4kw7}R^n)9j6Q^_SaCi#xx1#{!Lh)9
zecXW-7Q8=jT7)<1R_j;tcxsJVzfma{7QHg@ONwfu!vtBqG4Qyx+1yooz@J#~>WKvh
zY#`WSxjSp)(*sZcz-^_m`ZL~FnlVX~uQdH#&8cRty51XGs7@U$x1Qq6uJ{4}H(zhY
z!{NY9@6G>~eV6kg*lS1l+IVy9wCBG3dXn4Fi=d7NJnyCOTw>pGE<ObAUd{*QsJ_se
z^&hOB4j&A?KZrcS-N)|QMKsj6Tf{es=i$>$GcKeN!|;UP`=)|J-t=bh<QAKLd@hoc
zc*+Y;hZR<>)f_HYm_@sFc3^5T_mSedGLf*yn-QE^ag%!STr<}<;5|(^a-HKQ+u@_I
zKOndlj3&puQ{IE#K<`QB9ur*I<n;#!-D0im)cfy>UtW(XKpcm~jC~)`*B4t=B1Q!I
zSYgrzJI2X7B)P{TmuT1mU9@)SPEgogDcX;Y_xV<I4}-jp_;}6z?T9TW2ueN{dts&j
zv4{=Zysd8E=uL@a>f>XW9sPY|02)o$4H~}7t~U;qar;|QnCrW*MX0FXgTAf6^(K3F
zM#acG>Ie1Wsj%9JU_hH#0{*Wh`>hAnYsYWZ;{3&b{uKfSs7CzwI3b2Xc=;5upZ=SO
zVU{f)chas$g_`Hp>JESm^u}Hd{MU#q-Q`39$&dqgF#&X(kzE>e6Z0Nx=s53nh&r^~
zzLTLv%B!bxAXGXdMtC6UgWy~D-aHYIzdK1KZJCq+A&iK;Ohlw*6QP-8Ah5UJHCl6%
zhst4j5Z&M(fE5S&CT!oj10fTXb~j%euOLVvO>|3<wXwK3mYD2G;`23L812R0+{DaC
z!n=t=SdCL<hFV*<-*p>t52KZs>CPpJHanzyi39FNdoeI$_Xv@u_+)SdDOR+@14G5!
zOMzY9G}!O8V}zJYLFCDqvT~l#LobXy#s!TcBS0Jh3_<sXuh4O={>V5&v$2pHTfFl(
zpcP`87PdCwlqhcGCOp*1l%KobNrKpS5k@D&vSn?DiG8o+BuK}gHqP4LLlEZ<htN%U
zFeLi~CQ)`_C9L*`1n5Y%$D|EpA6iV>LoawcBPLD{hwSb`n0@T=Wa0VpEuM8GDVOW<
zUBQlUVB9J8OgZjbwFq@ss%dB$$lK&v+iNg@Rf=x9%SO{2_a4Fr<9a^PD<`g4Tb(+g
zE+`!9AfO^Yv@zCsS};JI3^Wi@j>wKoIYsyXWA6Qf<2cVd&+f*E8PkeA^Kv}tOnA(^
zFB-$f5R`}^iaW>JI!`xx$N>de7>LoLv??zEfeNK4iAa0*T&dK$-<}>35Wx_H7$3`V
z-2xCO(>^(tXvOQx?XC$BEYprsCK>InYHM#-l<Ab}He03`t>ew!p6~O5{vofO>}_iQ
zxRD5gKu^!x@9*dHe4pn%SMcGbB5hTd!!H)HG&j(Tvd00Ph>D<7u;E^oOQNE}WU%fp
z_$k;Hlt-ho&gyDD)oPen0rx?sCXYQl1^^u`g;7yQ?qout!C)j8m5yRWl<jz}zTg>d
z=3<bUF6mphBQF-y+V>t}3QqZDZi_W6O!X{yn{U@}_zk~&X26nPw-pUUWoT(#VufB%
zkwr7$lVRz@g+sHN^^)y18BJrde6ho|W1AshT(q@Z#14py(=tob+uypkm?{Ts2+z!M
z0tF0}hxXI>x(8z{JAGR$Df*N{lhdG$t(Nq1i)sN5ZJT{=N=LLHwTvU4!opWZI!RM&
zbIj(O&85M~N^3ru&ajcov_AQ*taV8=4rTqghrNmEzyc2^_rVdt?%z@UM6gsMb9_wk
zP}cJrDxbBknNDV@hU2<SD;C41hb3-FM5G}!o(*2~ED_sfJ{8o91FoBi*!{bu@Eld2
zBwFS_adgNp{I4Ig<Up9gQE(!7#$_$ca?XyF4m&{>P^;HAEz-!o>``ZvNhRyzEWy-W
zWns_5mf1!vN$R=F#$$f7JL3;94ohpY!)M1ykHs`kaj0H~uEQEjAI*I2|GZSIq|eu1
zctJ`%f6=|D&bYf>@mVSEbLYQBV)kL(t3Ouor-yyL?`?KQ^$l^K5GR7-_f+A2HMKHO
z^W0rx_x>)Oz5kecBiSo@>7xC6OZO*(rQLqtIdQ)}UUC1hdWLLi$4iB2j(s}k>-jT7
z^Lt5b7Pv!x(PJZ0SMG=!Cd1S7o(Ur<WBKBZt>G%6%U~y0W>;kM?d0a#G?~q37YCT|
zM&3$*<@Y@{{=_?PoyA2A-IOPWD@k}kh}upqcDuJdcVFw!M2fRnk0^XDpR3{3oVw;O
z%Y(husZMompm)8Z)84(_3*-Kr?N*X0$*x44ke%o2mD={XS4!)``rPyjqB`ggB!qu|
zeL7iiOXS2BbL>|K{kpO$5RF#~E3)EVt&5FOHcxd@f#X7|^T_OeWip=bDJas+F8=M>
zYn-|zS-~H|<vZ8=yazw^kDeS~`{H6xF-i<mJX~Q~o$%`W+zI90C61ds(b#@JM25x+
z<l;fMFPTpCkpx!Qm&p7ZY=iH<W1?y<KA-S!^X(6=j=4DC#@V~~#dzd~P)mazr}P@v
z8U84^Y!g2Q?92WAKmN=geaD86b5;i3)-QSAoN@w#Qm%aTiCrAW(w^x*<A3P5x+C(X
zhhKa8Vr~4wfm`9l+KJ$iaQ~OiwlCZtUdZndx2oc*XntPp|5Bmt^}e9~xYSJc`XBm)
zd7t0S%2VQN8_ie6Kflm^wqM;jE6%?W`t5;kR&$hFs=9APwt<!pZimjDQN?#$KdP)M
z@4(@x|6k6wuNqZf+66!wrc%8Kf&}tpmwHdJ&;f(y4u(5S=^${Ym!~!=uc~)lcjG>9
z|Cc@!yd6Gwqt(8;v^UzQ@(I7N)*8S68}GBK96i0g(EOCDh7&Wp@+Y@>M?NL2QFT)X
zx5AaZ1MM)_|1H^m&L5k(vZ9_TJmM|XuZSXdxZ-}9EXi3h=F7$=vpcPWcPk!L?DML=
z@og_r!Ix<@7#ZQ(R_SACOx&&ucgF7nOuGUkf?68hM<q8dQ2x95eq-*<o4`I-{%_BN
zXKetw*rBcN<)UZYD6>C^Jg$ktr|!J*UCZF5TSq>n=AGtQK^@#Wa#qX*waR{{dCuFv
zCi)6c)$v3LD)?DhZyugr+P0%OBgd`=G^p2C6Q!U9!GLacTmR+&6tVqzx&Ps#SMIGQ
zfv4;yZ_ipFsU~@q^PlmoV5xS>y;Aq~o8t1}uaQIF-fRX#l_1q!Qm(dV4~B-T2El&t
zb+hh?lU(gTkiU|xUM%EI`J36+-}xOYsfOR%UOeI{r}?5hxwjc5vOV*wYS%Uq46h98
znZDKDu?zjq*db~4ZK-!3o9=hIAFYsrxa){g+wXT$NYW{HD!${EAW-`sPM4Qz2ZQFK
z8jIp^B3jCy?({TMNu4=REe>Vgo}qMxdUCn4V2IK-9m0GEdgOOL591axUH(872RRY(
z3<&W=5)@kB|BDY;yHs^ptngO$LIAq`YHaq3pLFt2_@0>Ly<}XYN((E4^qqM8Lf@D1
zVZJQvZtJ43oAc@&w{+yw${)MHeQpf2pR<~o-jzI<Yu$&_y#jeI54vn4BJLFtBjr#`
ztC_Bl6NlxO6STH9I2Y!ja3xP>*i!JSr?k!O(zqvpltm-yyVw8J>bs~`6j;w#Spa7$
zYG)`!_o}Bn$rv)_ADfAj@fpi)X3OI*ag3GY$%bQH@mACh(U<YlZYc@3Z}qKSM=w#D
z(lI|9+W~8?D1l@#>Xi)~<PWn7nx2v!l-txczt^lqVIf<K7{lfCyU*6%l=dz<k%tRg
zj?Ek?IL&|U3Fpf8%s~6TscJaBB7HjNbZ_$Kg~E|S5*(hn<VQ0cg|kOAc+Roe2R(5@
zGe!+eRLw_bt>$5Gv(g$95e~b^70p{A*?4JSoC(c{9RZly^h?%Olb6|vtY^H;*hbT%
zst@Bl^%L>fhI+Zsj_AQr(|h-wqi-&^Reyq@$M%$H9{#wWdm~c4?W?~YHO7-s72f#9
ztaIg&ia&O1%4!z3RNGPRtxmqBokrqxzgGb*9(g2Emr|S%ho6YYH@Y-aGvhX+G@osD
z9Xu0bQ9pezvf!WOs#W`gEISK4FIH1K*CITtyCZ8YvR=EO#zwoV>ULp!)NpS_tKJto
zJt;e2&!5}YVrw+yyIqIHcvo20=hwYS`DfXB_oJ)6e=F!;te+}GtVm6`svh!1su~mX
zAWt2QCQv^RMPbGlQPiIdZVwdxPuWxOa}iFL=t<AU3k&dMF9UF)Y}jnlZt55ELFDIN
z4`1Bo29;Ggx0Z4w;C!;aeeIGvA~U~yc5Crov$|MSwy66iTHwsqS&t(I&pts6B2KWY
zsgE6w4IDdT>dnONV_6#$b*s-TYUie1Rx()S7gCtdvJWPmOgi?G&~fNa6zau^7FmcF
zLK5mKb$ye3a$T&P7zPTM)ehhP7<*RXHe|kLW<GT1A18)u{?gCnnm<C4@8N)dbFTT{
zbd%rnel{Ha|8$eS{|aH<yvcw3nV9xxP|e<o6|i^Q+|Tm&U-L?T@H=BiV5Fo-Oxd@Z
z@7TP?_U1QyF+aKg$_J94eJ9M6pZG;=Hvhax!D?>yvtKX&`UlR9POTSb+pTMd*43!k
zii~2+?*xwU$C8tBw_BIFb>UUcl2Eo+1xJ(5VXM@K)v>~K5T&DPu+XdziG#8_I5ek{
z%U<X4>5*m8>zoe6xq8Qj-(lXnok56H^%XClsmfkw&Y71hbbl>@{q8~CpjXWYnK(%0
z^X{p_+G|LTtPZ^I;WQ>Ydj9P8`Kk2sujs${Kgv4)Mv7zeP-Yn=0u}*NVxw++)K1Yk
zsM0zHIwNqw5UED3P-)GI*}w~1D#2MF*W9_OP(kvHbOeX-4qsi$v#l={fO#krePx5s
zdQm8#-NPcOQz%3}D^iTuML(ET*lAYmIiu}XYgE2<=>0N6=FrTJuB#m|t#mop`m{UX
zxRtE*`?YYEm4|zot*V%t(l21ki1}lMY~b==IxNo=++nR=@vpZAy~-2X4X&jiL=4pN
z)Mz@wx;wX4M;<yI_*K|f>}Zx8te04#l3_ED<cAO-5Tcll3O|2TBTMW2Nov<Q0b_@k
zx@YI2@AW=!jRt3ZUp?r)7G|2+21<lA9wCSZ>@@A<4@IB$2$5M-^E%&Z9aY2joYM(?
zyX;(YML)pHSaDMwBL^Kz-IO1ewX*@>P>oNxX^=_dWShUYFd1B`i(Gof^VLEjmyMu8
zrwS~aC&Ka+;+srmMyCNb*f3%|+x_OQ<{EShEv6r`o43;qBt7K3nBR8J=+m&<>PTvO
ztkp?{QYN<J8>yqUTNX$4f<z;cEhikF0km3T<AM7K<=3Q+Ak=P*PsU0|gG``n5$V-2
z|5l|s)Z@By35vzIPxb&z+|H2@rB<A1FBAN`kM41I2F)xw##7#(4d2@Zpmc>lWh9s|
zNDEa?aCK;PBoW@a*Bc&{dQSN31zqvsu7d-xChdL>O!$0))G?pMVnq64r-7bBPAJmL
zh#~9B@2qWCrx=IM*9QwD_G|K6i5$KasHxCz!C=zbNbtRa|MGye*IrBPlQNxfOJ8=w
zuMF5D_UQ8XBU$hJLm!AP6)LZ<I(~D46=JczN2IIe4fmv|xM%Bf-}lt^H0?#Zw8xc?
zKOSoT>t|dKov=J9Qg2~1k;Je#=Z@N)T1j?vkZ*a@LGO()Kfmo(lFuAW(#|@Zxja}$
z&&;?K;<DCQvSoQ0d(1APjZAO`po<C8XjI?R+2(bh_p5^i{fvtuYA){$)+fV5T5ZFV
zp+5Yvt;0?LO)6#5hU*)daEii7Z|aWN!EBo4E?bsZY8#h{i?;+*+D?TULpmm*Rw*Nx
zA&Bld4(`2cgp)bgN=pe)%!nCd+Z7W?w$R#S<LBMVELIpsy87k+*c02s<KAS_@O$Fk
zyt8WQpyRycRFEg9hV6ToNbRfEgtu|oDa-NJm2f6$%x;UaQCWy}cv7@6EJem2MaMnj
zK%d|>0r=j(WR8}IfwK^QE9W_WXGRC?8zX)>BJBXDOk@OHoP_(&-;YuY<)BskxCgQH
z%V!HU%fvu*oM4a3K+$EGB%FgMu{2PSzve@xv)pzkis&hPq5>aThzZd3;5ne$pmuy6
zEQEYr36xdzQEa*RH183Y{NuNO`+tb1Lw|R{S94Bx5iOf*(28SqF1q6_t)Q|H4Vop$
z&Wrol{{fpOgILN%Si9SB%5O<$ep$T4JY%Kxv@+{7F2IS+Oyd|J)X0+1U5C1yh@prN
zw5rJeLNL|bvb6jiOm*szcKq9Oe`+Q81b`?8o|J7<a(f{3dx|TP?@@zWUKja!5^P3^
zsMR%ye@by^?JOG;7*Jyt4^hVsjDnr*dQ6iyvYPLp!XmQvc=P!*qvG|^*g?S5vV7iH
zTF=kldFcXu%K;XPnSgUIkT6-&Dl5CZEpZf3c0B0^^oHprpTi#$YqwAxXAE_uEu`ol
zc3aK@0!33^tD6}HNifw>?W%D!+%p8@jh(0TGF!J!dJhcRiqAmg4@s4o4Am%2QGRFf
z*BaTKLD^~GMCU#VCz9J>n$t^?2aoMyM$)z~i$n&F1v+F}?Y+!6Ro3Gw#MLJJ>BMMu
z&AR3`SOv|qGxeoT+0JDT)R`bZQ;4V7f+d_6f#$y9XJXt3-Bf?~m8TjUCkPYua_rwE
zLryV-T+px2r<au@UGYNTNDHo)-Ba+;MMRdh!<W5wz>X9+MnC8Mv<ub3IwL%E%5)zJ
zqxKXyTg0LPG+r<|IOc+R!ZI+|AAR@BA1()5<A5^<P5Ux!BPFFi*f^9aN!#};PGcU=
zh#9mj(JG}~C|AztQ>iQNhZLT_)ujSgD5igTlg=M!2q3pVkxMgicvRC%(2K>H*0mOx
z3m;L-vUcwRe#)2<rrd;PyTt5c%`tF|tQc_NgB(M(R)Fz2s(96P`$N}hOe<?Z>cHs(
z^d$@u`d%Z0wZLG3_AvwGQZ%0%L;MKn8?uKf#37DXn+LFN|HH3Zl30z%iWt0&*+G|h
zrXXva1*<$1JBXg%AhW?<%?$T#PRCA1?J4Z#L^m=U_!})IS|cPOU;tug)$j|r_qiKx
zfMPbFdt32f3ltodsG2!DwCbT1FnR3ptq1deZ~2}GPXjg>3!w>Xpm(ybC>(|E&m@%$
zTbrYa3;5kPdbOIHFzui`RSvfjP2xMAqIFW<&hX6OQovE*rpz`9Y(jWQ8V?zZiC#4m
zQk&k|P}%00%eAN#gpt1e|2%l9GO#Rn7b=Afk1jF1#wt#SfW%aMrJnb|=4x(gW#7?d
zUBvZWI)0zZ?{mN4sov?{hgNPTuau69iR4<MZmwOdp7G}bZ@qe-xO~|^A&bu)FJ1JH
zaVvk%{{Any$z^|DCF|%g?{kYswYa?3{UcEyN%n4^?^O=*6LW8^IS<I%h*K*ONRTkn
z@QCktdfz{Zra11;6Vp$TlYMn~WVJZF!D3xLKlFf9!;dHPuet}`);G@nhZj%3>EC4f
z?;UoJCUat_vd=@J&aPxS*#(9!ugH2@>tFX%WSg?wTiY>krl39V>rVQTs=3{1{l7_3
zsk^n>@M5W>&g^^PvOtDB_0pLk)u$HyT?8Poqf}bg+|KnDK2Zer%m^vlV-9}OgYHK4
zm4Y(S6uS5Puz%7ktshkn1S7|ytI>n*@Ds^gn62uYox^EvwOGBCzA$yLQ`<-nopB$)
z$tTr296PD|HsNR1uS~S2>L;|0r{1fP{1N(G{t?XVOMZ+#xpwyt)R8};o>-I<WI&W{
zwW+BrarJvOmDq*E$Qa@Y`s5!R#DY+hU6vd74xfz<^|f1vUVP*(O`To!IO-!h^r8^0
zLtpmMUGi`Hm%LB@)Ax@AV8ko#YH#(1A9(if`s;afa@1Q=uB!fM{HgoA+8_O*+`Wo2
zu5cdp!;V4|zp;N%H*4ZP|LbiJ8uzgL)#<+Lv%}-zuEEpG$6D^$aqkFN?qlir%I?&^
zGX6XLi!Qw7^J)&o88e|Z*Pg4)<b8JZgFD25=<N8(d=vmZ-wd~&4uVxR_f`<hJH?lx
z>Xz<>=(lcm#{c-CkT*1=)%IyQ6}_y!>$(SSg_Xhi)_tqD-R-03=iUmYHlDiZ{<&Ky
zpT`Z>EUu^%Yms3oJ67PSStE0-TvW=2H2q-(+zi+ZzK!(EK-}BDd*#uJtd6fv83-gx
zQ@VM$Qbi;A+5<{>->z36f#-!9ANaP*=|u+hpm!5l_SM~12FwV_j3SU&<T<fZjMA08
z>>f@PmLBhBmp*i|)_gs>EB^djC-cLvM=KvItwq1#)zj1I>da(tV#6dY7)@{Kn``#b
zuYNW=+Mbc6hp$Gef!nh^8|&bXQo9D>b}Bb9|7)r?fL-`Neribt(QVhi)mL=7k5u6L
z?U~%V+x#*F2n8ghYNKxzUfq}VyT$nx^WCD-b2hv!>!uuIa(y-*q2~(%4xI`{9afVO
zxYx^te1?-Gg63)k*tzs@ryV^Q9fC49UyU-k!zgZD_nRqDF8D<2!V{p*_WYsMd@xM;
zuc!9y7mmJMnDS*6rxkI$Am`aKc+~4(862BcfVcCbtF>a7fWX$5dZQVM>Lc>ittoVv
zQL`d#c;KRoSmv~BAF2@4w^g0mJ_QLw8`%l6rtEN5Lz>cvXySaqOZbDUtyZ8j?+t>n
zS)z8M)rz9;Ox#!R{_AM<aH;*;Z_KDtkg4{*GunDUAy1_z(($8G{%jPU%>Plo@aCDH
z+aWx88qsM`b*>aWBdtUx8O*K>A_%l*)c&_5PUoj-kT3#9Ps_ec)tTu%<6n71$+`9g
z*^6X1ss`azuM`{-D|y|WPrfDd7f~v7DLJcF*$()0ik;!i=YX?^%BohNC;@6_aoFsv
z?(>@;k0@9BwU0zCS{y|B%{2AwL#t0L6k2}im4e+W<?p@ys9UC&&<$aLMDm!TqSy9-
z%9aHgt~z_@-*o%E1yAX<_#)=`N?tX$xapPAi)vb58Ca3t5qD)9Y+tQ)@lpnf2{2|+
zLfn_y+O!&xB|H#ax{<;cZ~OjObQDs4Qbf(w!w6)f2coA;U!$v?PH!D>Znv0r^1^gz
z5j~}XR_3eq%tOl*^t9&jV2X~QOv`z1r|KV{EwALgZ~vCU`O&umk32w!X|Adr{>+i0
z6V2?exnl?9SQIIs=BjEucAyl5&e&08n~;!xQghLhE!b}WB8A*jjG$zLKDmEcJsbtr
zW-mG9{R{NAhtk8dSAIJ}8T?w1o4DHaZ2JEhn#I5JnCZR`1^JhzPv!x(-wd}h&28x(
z4VsxbL^ItMM~ejGN_MmTtNC>1$rW{N`W(eAq)rn#x4Ke*fbLi!vZw=o_mFR&Jy3Oy
zK(5!G<#bTFWJHmi9G{?OjhbBmc2uHnqu&h8A@mkHNW)M!u4Hl-7-r0mtrJPq)DO=_
zY-X>#aUiuh9EI#mr{=Bb%1cpcYVFEu1ug1h(d|!Noz$LBxSrJsCm<CK&2ZbTAjz7t
zo{+)Lu-;vt?_H5I&8)itABc`Pb3q}KMoqkz98Y-mfC2d#_vvhXq#Y6|m|NMlgPlz`
zyHF1f$N4Dj33f+rZYFd~YpD`OAUd@cF!L}ZtlZ%OD#A;2clY&hwE$y9*13`|7BYTu
zd-`mc@qgj@GW$xinMdB4&sGCiC`%S$K0sKw1}L=Uz<`W^voDd`CUBbmU^VRDV!VGU
z{X%M`U1w5D-vl_|A+M*pP|q28X#bWJ+3Q-mL@W%o42H=NR;PLjbrA*AB6_kits$$*
zToGY$AvBftfn&i3i?9DruLj0nX*8hI$)+T9Xx|&H?>&3ymkRsPfS#Cs>OCq>Bb_Y1
zvHw;6+A;qf6rY>Y$^GUQ@7$GuPA6z6UmX6WyEh4c>Lv&;zxH=`^W;C$U;Y(>($)6}
zN=M$KN;SCiroQo8|MX`Tg(Cf+D1X4?P?S&o)kQ&-`jgL7WkX=3t>K}&_dpW*)g75<
znPOY8stnf8k6&ibYwQp6ip}?TUuG9gJOAiM$Qn0XJwMdiM>?;e7XNDLG;CqF#F3kw
zOgm0FgIuWaZ@=@wAKt=j^8f2EK4sHT`7f^AEQ+>1{0*o2If?Dm_D84JALLj@^ptj`
zbToL-Ev*;aV$09_iG82D?8V_wp}$x7JyY^@D3x@A<{Msu8+k;&Q}9bSJULhp3+`yI
z94D{+Gh*wWp#?APaE#MD+6h!pL>D9pF@A4q_52V97{96St7G-6CCSG0k?c{w%Er7g
zp!KrEu<!}?Da5aM86Ej2gTI%&JNwD<S`C}Pn+_k`??#+a?;ce;wgY_sR$2x?QJn`R
z7PYH#nH@+3YS@a5rQ+;c$+EoUq7THbobB=Fv;@^O&bjl#jqa9>RiK<eS=kq2JaV3s
zB0RV3jHD|e{&bdA?5sMCxyK#dl1mp`!*@=7p^Q=?byux!bQL`mCdEQ=gSaHP3!)_J
zb8AYuqmCbxZP^E$<g!m-jSd=MYByPgvw9Tw_D(gakWcEsA6+LerDoQnC@Mjc2i#pN
zSZhXBI7B4`IZrFzZ<YCsR1`hwoD@rfkl|bg2b-9C_vUX{h!j%~q1r|)(dTx;)@=Tq
zTV$Tm1P<qqE(c6wk3*s}!JbN><>xQ}IU@HGfYdI_HO}}|WhM2L#=@^fVxy56MNN1R
zh0(@#w>U(Yv6eQmTcnZngYk(t?U~nDgX@LHP+?T+MRZht`SK8M$l({{u+z9u_|CuR
z0b~eZxd0E_laQYc6FK)4*M|ZOugVeI+CYM%B?hM;wQhg}rs2-ou?@l!u9ShLq~Aou
zsu51lZ!!f&)GsE)qV<vmb`jg#d_q}kdkz;-#otnPj>b;e#Hv9-%6C@(qA}Y$hzH!k
z+H`%OwCG@Yr4PDeDNKBcMiia3dUvR@Gr*9Im<+w3GZm(~Pt*r+UT*4lKtg~M(J!Zz
zr$(fl>Me&y!(7^K>C4Uo!kt^(ULRiD-bfucUrIW!7S&>5H19d%Ej11s^mGqJT^Ksp
z89kwqC6d-{REI-e{Q+TgsTabBzVbfT?+~dbbdb`Sw4P^w7`(B*?JCCZygVbi86>B)
z%}E(a@n(|uf^*(#86k3dnM&gU^T^(a9T&4UQc!<DUk`hyIuD4kmJAdsoSIj3Hwt1n
z?_m*Mz8Rh=!4;^rl9E`*L$Q>y$FF#cg^$qU<3IxU6Z|Uh)(XW}TkzpLVSb1&6s(|E
z-TBjHs5iY;(}CzcInOTBnXELn$Gn(cl6rw>$vAMg7(_<nnkmn7@goPh?1E>dBlPaR
zOoTYDbs!6sTVe<m&k7YF<W^yY-{dl26|slNR`M#q9E+cEVGpsRzW7BW1yy-BLzDvv
z640L_<}M<2nbf#8E*17L_8aHeCK@oW&5TTBtI{|1cv7Y&@i!80yUf6W)upfkIvO3Q
zSJnzK0LB7|LNY8RK7!u?e{4v%g&WvJ*jhEe;SUxn+3)=O_bH|*l<O9&DPRbS6qS#u
zXqIYdWa-uf{W8y6mvB7}7MWnI*svY=n={3|q1-OiWG>(#`)$f#1Z*l`tq|i}?2{aT
z+O2vdcZ8qvR_pYC-nuW7%l5NPWE>;tUld|Nl$8!<^zvM=6}Lk_ISI(vAOq?4Ik;-i
zK>aQW4{KdNBSM7PpXL6Zdx;S4bpcjnQglYu<6&w^D&101?-~$BNcuI4)i}eS{R@Ni
zG62}>tb5Fj0kYI=bo(!U&w4hx7a?5Psp00`Y+deB3TFx9w)$8%@>^xvhsMnTSGnjt
z`<N~p?zCnLFM7d|QkzPkt}Ubiq#&VZ_&g?xM}^Z%*+?`u1$Ck2AJQ7P4dTUedQ$}7
zJJq(zfn#}-%kzQ5iOq^2+EhrSrYc_w9qJOEoic7?WZXFvu$OI`N88v7yUdxvur;T)
zY{@?8U6QQ1mr6eNyX_4G83kk`ixeIQt1J=3n&Zv`kuFKgNEj2D+Ei2c%exMOcEOr!
z5&hq+9d^0L<g!4HH()nX8f&3o{4kS}S%aalc{8di-Awp&zjWL&)o_siDKPFBh_^B=
zD^4ym%p*!=BDJi*vJPbDQP7?BTcjgl`6t=RcmBou@mev(kF88f?YTwbhb30Eb&1<8
z$=tZYec~+h?#=B5UG7YwXoATpW5fBJlhV579_wW$dIoH74<igkWi)NN9es>PoC^6~
z74PjN4j6ALsANSHc2*da(L*!L;dBc#ka<=<L$Hiivhxxnh!rT+_+a>4O?B{jDIdJ*
z7g_l>-_c<3GZ=;%={gH*nZAvaj4qFZi$o<KO1n0@XAc*db)euoqxOQ=_}-&W<qoUi
ze2W`B<6U&atuL(+>4-x|r(<UC?O0u>;dn2x!s19BLjWZEuP1qDjka|jWK24uSI{3O
z;aOgJ&6D1+HmOYfFpDEjSq+s)>39IwGI+CfDPmI<J>z93uRzVk4lh!yWW~&fcm7;2
zgw)bEX=_#?cWarZM(By=+FiDSUfE6}W^MWbYm9C(4K}mPJuO5qoSE3upl~>|R^v{R
zPkLPCk((u4X9jbK&^AiwB^gmiZsem0X5NkEuzwGAND__%H~o9*J=FGaVyeEu0ooz1
z)_Uv&W_+-aAas^^zZp0tuqelLXid_iP)N&EGjE!PH5<)XCe9QyPT4LKYM~-Lb3CQ8
z_Cy`q^p~Z+cs$L$`=9^EJ!$mXlzhf@`abf8|GZ~((3eW-XSo~ULWAPht8;&{`aF>(
z{%57Tn`L#euv1>nA9o9fn1DwlyNnKyt)0kXwzzet9%!!?!*7&MNCJr#MehyuEp}f6
z$uU*)cPf8iD(T(ppAx!%tybQ4BV85`?w>nW^xt6>h>xlDLTw=F>09&`=m?3ytUJ7y
z3z^s%9rjorr-Mhuxu>hka!&p)-i~PB+u^dPtcsK4)a%)Q=3i6!jZ#M*qvxbwzwCFA
zlWOmT%=u8vRd;7nn(pitqI0bFf3Y~Q{c*otV|Ub?U=3O;qK;kGT6%8t9NEE+7w|#9
zK!E!j>&vpcB6s1I5Ig0-aesOxE!N!8%k{o`iP#puw>DJYH?4-BukB_cdq#!cTS|-X
zDmG7xL#$eOPKXc~`F5~)_|33eE1U>Aiyt2uETjkgGtqs8j}FW~KT}x^t7|j&ZGS+X
zh`#@ie||@L#6+w2p=>)``Jq<yu3$9z5dz)RfFgMByL&0J(hADY&8s%QU_MS%V=i~x
z;$uc83M(ZHtIv>CqrTzGl)gq4-xY`&IjQLT$u9xfIqZ5Z3Rt;}lGJ=LS{%M^s#fm?
z%bN(f6G8Ax-oO3j_caf1yzJ_rCa!I?r+4MY^iH)Sf68wdy4HC;S`3Th>-UH1So&!7
z{_yjAcNEX>fPNO6V8e%G-h0RQNAg=vxxaf<-Jb`VihW{-IJgn)Y6Hfi%s2bnFw;`|
zZNzPh2p9LOD$MC(?Z)i7`?6Ts`@6qYc|@G@qhC|IdIye0?yI$5n5g`k+J7t+Z-rG*
zle$<($+-g6HOOjdTPZL9w6HoDG*|!54iVnx?F!PbMGtuD@{{Rrr2Zef2RBsbPoiVd
zz(4ROu14cuedhxYO|=i)#%vL2MUjc-TybMIfMo$3KH(X8<n|Zyr-bZZ+53=e|GvCk
z5KZSKIr;+VP*bEv+y^wvx1N>uQocAIMy0jV`H~ZPyVU;2r3BG|Aq6-pOFBW_cTo_*
zd$E!LAOk4N??1jWXkZY}zNnzaa+k8oy_`*4>Iq{TtcUonLve}D9&8;_$G3lcbakfM
zb1<6j*0;y+wjX6zp>-gf)xJ+5TJ*+dX&C})-<0haA5i;m%J%2UxA&m<c1gWc5RueR
zw?hgZO_fL{M5Q$!p;1KxnDnSORpRnQitYz?QJylY(V#}GcS_vyVDo?&pAB|~RTcbM
zxYFARzN@@a$STA~<eeIi=s=-N6a3Frr)32nF;MEw&^e(Wj7Bn@wN~re{Pm61C-yrJ
zM&W$>YE-@RpOzc@o~7ntkd5&tb_uHw2-62lF=+4fa{JKzVbYu5S_&SSrX&Y4AlkJ^
zR>R_IzGJ^E*4!rFaiBGz`G|NipE4{q==0lh4!uFX?2Fc-An18UHvV)P!C`BZI{F7{
zb(=?DgUu>wApHvA;4B@#b;4;K%2<!ygMIj5)LP27j@G^w{IS95*COxB?lE_CSv~Z}
zTbqXu>>&(s?ADQswTEX@k6K*yfR-@6n=<$Sef#|9mFSMT2?aJsf``ShH4zeH-hEW{
zgP+~iJhIzhDc^KT=y*{~mT3G2VLsqg5T8}TKk<PQYSG;ukUEV@+uZ4J6Y#x|k5q}y
zK5aTXkkZ<}ta7V)7kFDT5ZP&NM9&Z(n2N_<JG8180%0S{d||Nx$|Hu`^7^n+`yBpB
zW(WFe3F$CV_|HlAo4S305`_e*Uteu2sjqB}k*vz#(eN1-BdTdUq_p(vO{^_8ga18=
z0-A%_n}y9T&9RCv<kzgUnHVPrr3n}SXfc(q%=$REzbCYoo*-yDaSlen%hF)W-+!#|
z@hD?@vo&nr{`KEyrSq)jBjK+6=>%O{{uH}YJqBxS{zgb8pC=y#88FtRAgx8F+j`^)
zaPZqRage<>+aARMVq~C=@mut5A*HxdGVMHIZwA}rTLqQAn1}6?MM7*m=#|d6Xhdz<
zi<h>!<;|(~OnI%qD*jvNRWn_UtV632Q%bewJ~;XjB*ycrk^jx$`fH3nx^Rm$1DTgE
zY`JwrB!Ls#ea?OX$)gJwv%hY%xzPg(2h1Da$hytKmS+mv;jn*p#Br}|7mi_;8%HwY
z+JTJQ_Xv#l#&p*87(Y{5`VewVt}xLA*SpOjuO!=}PiDvy5>)M{zk;B8lea$R0jAmN
z9Qv$k-U7=mVTASL$Y?>*^QCuM8_X1i)rek@9?I-+1M46C^80gJ(X=4R(E;hNY>0d|
z4$d7AxdZ9&dK%w&JIIKQpz)PL9<gqL$*j<?g2SOqqbD<IUm?{5=r0t`y9&?`=XR=)
z`Y9b9_8Xt_tc~3fd$%ZK0_&~b72??)_K#M*L8joqx2}bi4L6GRhgawQ#^IK#zs85*
zy;G;t4}R(~cKwbUv5K*Pb$Za@qzjm9-NY%radbAZyR3E-DjswJK-%MwhZ;DPk47De
zGs<z(-Ot8>JFBL3426Q3+IJVk&f^5PK|cwv7wBHDO~X&epidLTPXUS8=^ZA20o5Ay
zuZpyrIussU8CYq|dU{EI|5xta;r+DG^lsGpdxfUo^M4ro{*#pPht%}PsM3(vyOH#N
z6*c`SRQccMCVz03-_~Dk8{oM~T>lz=`@25~<^RdY0h0cg(Da)xzW=#Rb3&)IHXGR=
zzl`1dldt#wg#B#UMn_S0TA^kBM|H6I_ua2n;gf&#{-1oeCC$H0r~2{h?!Pua8qUhi
z%&*LL`KMq1_=)&^l~23gsNKj`>V=Nf2>+xmpYg$JwhK-mpwK}-xJ$m!Zbg8>-P^C+
zNRNqV)}FU>S@wz^ThGeuT8-dOyMJA=L!TF)@W%Z>230nmBl4937K<2xz=@H)*!4n!
zU_DYEVJkV9nj|<>E7H}qI#9+|sy4@OYi^|L@!-_yKmR%K8YT)1CPhgZ2TpmhgpA8E
z)rvUiWwpk_157DN9f2zt$OCrS)}r%@>kK%s<t2%6Kc6SJl2y4Nz2YoDP|N34EIYRQ
zv>k6tfxZnd0Y%GY1a_TX8~d%S<aAKq%m}v}e*eO~@tT^qkDzTM&`SaxofJ#4h{$cS
zW5qpQ+&*eaywzIF=3j3e6GIqLv_RSRD5Z%3$A%4^0V$n>DpwSlI`Yh+F)x>?H44e1
ziW#LH4H__^l=ftz{YoZP^^yac^^55IYC$}lefd`~yUKnt>ntTd=vBtz`Kw=uN-~&2
ze8IFef0Z-k3<fw~qRnq}GSkX8Z0o?Q|L%hiCC->GzMgo?wfrUV#MQH^FrYFIx#;zi
zq1l4}>(N+izP~-YyE)pw=3nyjJJS9kx4P|p1CKv@uCZ1*z_qru`{?DP!tamVt7pZv
z(#BZ=|NY;6J2*GpdEVu=VfFoIpFZBo{7yc1&f6V5;CJ<6xZu7vYwr$Dea6IN<*&ES
z9am#I^`5%9R`<7)<L!95?6oF#y9Z|rNBc8f?yTkL|L$f!;;T1<bE?z1CoQ-2i?1h{
zm$h6^4$O{3Ybp#((Yxou;T9jENu=Ut@6T_faX2e(4!@Cj_AlB4)6b5+@9t9u*@fu`
z{KDK~xI|d4xpI|Q=$pgmLU9eS>K(Xxw!uwrrzBBX;GSpv{(CN^))%>>u9ENZW_T`4
z7xJpBHqKt^Uk&}c75DM<2UqHR|HdDP+|e^{hHoU92N*8@y<VUE&^_<~C<S!fpg9vz
z9^Jre?RXwb0U1#tswA>l%gx-x%2&l{31u(aQb5On;BccHXn}r|j!bJ_y*CqSu%{6V
zs*YZk)^JV19Ve4AS;?3K8mXZR79`M`?<qU%rs8)7|MHR$bM3^+h2d;o*(MFk9O2Sw
z87VZmc<I#=#9%~HwT}I!b{N$f`@BdtSb>7VHCZEY4IqchFk%oCJ8Y5QZ?SYz%Zf~G
zbv>I^b9l|OgfjalB^C;BAM2|xez3STh0w@VKwK6gVewa#`;6$%Pq1SbSKX0hD!{4H
zjSMJ`aUE3knHm?R8kv~8$Gt?}P~k7b83oVT3HHIM=kuxuwgO9*L>T)-N}{<NNbvPg
z*U--61yV((S}qnwoMNgI=US_SnLvU7>-HaZ2*V{f7JAgU_j1r09jzCJ^W*7!5T^OV
zEnRHY3&nGV+P;h4vIugu?L6b0LHSov{neqpmei@V7D`Nx_8yjIcEG|t?qy>zj~=l*
zK}O;BDbBv)E*5BsV&N8R8Pe=z*?Tk8B)$dq`y*Q33{*av?U@Wzag}5ug@r<CI`q}o
z{vQ?%T0^tcr-2m>*nzdf8*9N~^o;U?S~nBhWrfV1$<Ux+D_upLXlfg>MF%1(*J)%b
z&>$beNYFjgO8{QBE+c?r@?+TvxHOl+;c7AEeDZC3z|OURW}=C^gq+@dz;Zbs9n}rk
zBWqUfUR)_O95KT#ZZcu0nnia|YLGj^PLWYsF|Fm!PlYhHyuVhmmPD+j1M4eg9uSQv
zl>veOYeOQcc!`62j{$){&iB9n`n{|fn=4~uBE%nq`?zeUhEMm~M#n5oB7+<bsJjy@
z2v5^?X7L1W4ns_-tqcWXB{ij?AM!%n8H?1m@Ep)3{j$gmJJ#(lzuHLbcuJ<0HDI%E
z>l?_EgR)SniN45@vhM;Z8<E0OlV!#k?joz<v!uAXKcCgHa0G%p9<}jCOSN0MY*{BF
z4UJ~mlwXK|cM5AsHjw_|ZLuc9%@vM<FL?g#fB!qyv!S{5ls43?QNR&M7(2r;$KP?X
zCZbK6mbF%OY_G<;oiq%_rbCNKwR%ciQpNDlwA`V}HfD!6!(eMntMc%1D%5HWc@VXX
z$);e@7ZkNYnfy!n=r{lTeI^l2!{I*#x7B9tYdqSrJd!g9&b6Zf=`_~Z((aVdO}Jmf
zZ>xqw1Cvr0E)97#kH^EZ0#1cc9CWre>12Y`JZ6j^%oZl#f<k0W(S*qd>i?r}|Gdd%
z*)X#RAD)WTB(}~0TRo3N5BLuH(A+qPoqF4f4`z-uOkedmV)=ZSg=srorW&uYuIO9N
zq%_4(Li$dHVNA{e)6R6dvQpY+c?zXSdG^@3{lL?d-sFJo4@|GI0!_27Q8Kn6eVI)i
zx!H6{%{0qVP-{F~oF7+dypE!NO<6?u`vh{h_+s&|psVKLaSfQ~h^)F5+hy(GO)@Z*
zUtIF4cH`YAM=YxWG{zh>V`T%DYrHV%T73^4cdkXCJ-N<3*gNAX6eQWdsch19Sbftt
zK!a?cgQ713Co<#7^yEDSQ+7Y*o>UFA7|EPk!WBSqNw{zQ<}dub+n6@(ns)5Qgu0fX
zGNusZqp<t|o5CU6X8*-dp@T`&A3W9=Mgu>sX{v)}GY>;^=79ZXDu@XU;iJ*b+U9e)
zUko$9ef$gM7R%TwvvPwJI+p$%b;%|RjWr3e8yQ(WQ=kR=+rAf*dLZQkkIK{olZ!g3
zQL>iR>+E2~c){*V4Zn}|pi&ZO<jYu!BvGMBCQdo$dk7XVJ*aB4zw-iQ)rG(FPazzX
z7QXJ|%cVy!;Kf<=l=-bsOZwblKbKvGN3$3e-Nf`pWWmf5mh`ONDe31NZ_?bHNs0t3
z{M@Tco)3==F*p|dM^Y2)x=i;S#xt2PYkc@>c5xu@;)--da;Ee-7AwsvBcIHFqTo)X
zFAQ$qsc)s7c9QOPEAEzGm16i6_pM|~b{%i-I<$iY1_z<Y9r9&<LQTrKDM<k1x?fD3
zU9g5%#G=}{;`dE=mTP^Va(CVoU#N)PM2<MaJ!+>Md6-qSbVJE^l&Dqp9YF3yj}7?9
zbU@M}Qm^jwd-dKSHLMb~EmQ7!z{FkE)Ns%63$pUgoePt4!IfelC`}~Kh&R-A=3{ij
zZ}22Xa9r+j2LR^yJ(pM0z6<i8+M)J{UnOZk<tUB>MrBd>?J68y>b^v39XusZiQ=KU
zyHk6`bG7@`nqS+gcghpJJJh~)zwhWu>G=K?@kKeUyW!hX{dqy*rkomPr?4Wtn)0fH
zqLRGgt+@xKJG>%?l}fg)lCVQ-q(n^4`bz~Bq-KlXGhz=*`i32R@~up1LS1q@frC>#
znbPn1f-Ma?11(!deq^Zfn<NW3@-r?x=KhdBpU~%%i$37hh;?B+B$=F0ce(b7O>wV8
zsEYvKFlM=VPZDKehGUQWl@=*jdtynd%uN}uvBpd0@*n;A#XG<Kub1+xvim&(U)r;$
zO0pOI*qMXjZs6I&FU<(Dkw$030Wf0emCv-F+ntWRJtI%5;(>clcVMm<N1jYSG!1fI
zLx|sd6P0duSD-!XkAAW5Uy;(F`{)IENyMa0ywF#xkymv#&nYSo-=y*Qgz>kJysAQV
z*4y>5QXBPYX_Gd8ez54sD$&f%=NtrWM3;|}jP(Wep&9ZM)KRRxiBfm?qRJq6EPd&$
zJ^J}UAn}-M^pwilfAKf(DH*KH?BIce-C)9q8IShSRxlgy{6{h%&ngl8eMO?R3w^~q
zb!^7QAxBfQyFg)$L~bINK8K*@s&r|BEb3CZnG#d=Q=V>?^s5g?&5PptZ2P7AO|*DB
z8Ya`Kc?c37@Qe`WC(1p|S5<N|2;eVCn5o)9P|n{=?k9juDgUasvKN;$@%%_3;a|4(
z;qSs=1+|tVyndXrbdWcK=ydQ{g~S4B&=~gu!Jhoe#EZng-zkWx+x2?!QN=8ILVF}5
zK&<KQ$`jM4yV=|XTp8B6OCjg+t06a}7~>Z_KzXzEWkDY^JRB7ysZswKh4G{+9p^w%
zS#^wiE$|T_?_U`V0*eWpAZC6Xm3m?@dx0dU%7%^-_Wy5wt~AA22Bg_!zP}rTKhUK5
z*C_4p1aIng)w)u8X|uFV@|FxhJsZO5PWU8}Wyfc+1Q7mC`C}u*?OjnIT9Zql?;;+D
zZLLp{SK+%A2<N6;wEIsg#vLM;wvnY*G$Y3i0u#62OqaJs2rALJHX<rFAo~OpH%Agh
zRb_JKqD+!^>aV{ksoz;9Wwg)QB!=~lI64Yw=L_+5pH!?}fin|MenR7eFqpp&w4Ec1
zY_~+A37`Qa@8HJWi3<`33Ni1_30=N{40MmE-`Z?}w_mRHG*;QQS7<E5>aA)|(=nT@
zph*@A8auE|5&*wJ4;W-TGK(W?WDWbU|2~8FEqn`9ChL*3mhgz2-=10ZtQ`eer7z*)
zsYek9mEk4uBzMm_W3y&!#w6YcS25*s$_gR1>}S-?O1Cl*@em}PIH&4kQMo7R$0nlf
zb_iO_X|9sNl&$|}3Ig2z%8i2kJtj9n*%`&V9>XXz|Mu^0ErvWx;J~zd2i+?uVb8cT
z&B7)KHb6Ubiq#DdfOtp-#c55;G(vIQZG{&F%>Gf<F;_EPbjg9kzv#RnD@kcsC`Qxj
zQg7*DkHOTQZ9X!ye^Y1c%uss{36Plu(v=#xS(e75KpBy^gH@oK89tV#M)!*TqKe9@
zx|!lw1d;!HRT@-n_DQx8T=CgK(Hx(S^RI_w5co(lv-))QnF4PnM*vFPHvV0=q1v-v
zq0~#?=+9VCsHe#;wX`=~QniLt&AW_f`v|!(GG?ehiJX{Gbd7_6NWBo1nPTGLa1_J(
z8_{{G5akm!{Q7~_y}1p~LXArK%f|~X>YDG=>F)b1NqXPdhCstcJNZItcV7>Y;|4T%
zY6aabqIlRVYaIPqvgj82&tMMdh0r(&R=I#g!Na%_jdW!`K-|(9ZynLonjsK9nXcsV
zI=bdl!y#2#-@dk_9>_<29kMOAMfbRjWZMXdm-9g-LpBAUUnD`6jsNXu|Ka4El{SD|
ztt2o2IL9V{&)xKg+Pj}+r?Qou8V*yII1G_uwoe;Zhu{)%9*^qNnB9E|h?s)0%pkpu
zl|58XH=U&m)9mE{#35>ZHm0ovDqw`QXufrCyTw50-@?vqbk_VFLd@1LzH@r*zdZ{9
zsl|UJsYOb=DXIPc0UZ9DmjsRP!#~It8~${1)iW=a*{lBerOmfy!@l{#I7=}Cu(!=u
z14(}P{oUXH@ayKg$_d-Z&DZHin48&5|8=jvA6)y_U32$$Uz~W~=&aPlTv#CCV}+U<
z=x8}Nk%|#yp2hlht8+}G2*^F%PIpSgLCXj=D6G(Z?%V8=^h;AoSxQVDAqHx75W*a`
zEeV73pCGXALAQIhP;6b0H32b2YD?NL&Og&O3MCA{b#F4XP7stYBGKtg5660X*cctd
z4gsKt(_dWo@}E4irEH5;_V7f!Vb2+HPFiNz^|Duw34SJ^j<J@t3b{8J8nZh89N-}y
zENOToVZm@@FvBGz=8btxQZc0hw`}0=imb;gvaGa&HBCf2$?TQ{Vb!q`X~5LA$772>
zBTfqS-JXabD<hLbvop}iXPTISO&>vAz$r?k>d!2=aD&x|delDp%q#}tk|1AajYxJj
zq|0RvASgTJ>2u1VFR!P`v4WqES{Fnuch(h?3C5MQFda|^JLTYM9kC%yv69O@pa4wp
zf+A~OBlFO^A9TefV{mfXo@Z-%Ol(^qe9W^P5tbym!)DXU)y1duKJ3fXiot#aRc2$Y
z1_@iHsh#*ntB1EuBG<LK!tFq^*Exv=i*Qff*OPkWW~isvpK-k;zrku=@vy-N^j(%C
z7<iFT?nBR;gq5>tn#R)Bw+wSgHBqw$a1?=N3k57%kQ2B`HP8~GOO#u18thQY;2&O0
zK6PMV0x|SEHub3K(Q40jdKLqOu945UuMw5Y2U<#$9p*s3`_31C4xOubjwi?VZV<-J
z=MrveqISzRq;t(9p<vKz%`PIJ?5A^@q=oSb&Lz_JJOW#_P-Ti1R;`P<pegL1C6ZII
z+*I!+Sa^{>c@u+gQY+uucXmjeDvaDn^;=<Z7CSV^SZJ@6UkiMWmdRMBmQ5lHp>yJD
zp<_pl!nB@WYt0W9T-d*y(js3Qwfh7AhU(#vCm~+Tq$q6dc};DilUFp1n^Gt?_=9!V
zq$<at@2`<P<7hB12|MyT!!yY>PMlu^5{kK33hSss)v(-F;530nQd#8Os|5~@&{7X_
zAO*QwJ-2EP57r6&!{*_6ylem911wb7=K;%Y3-+Xgtf#3f%yY!$Dc!&?uaTrd+hq)M
z5;2kk*=A3`FSG`Eset#`mZ}k{tL6nKtfUcd2f7640~uSmj%ZW!Gb@cXtr$DMeDmi4
z)BKy<nNe1XJ*~2|W7*0sNi&3vsF>M~A!2C`0x--NWZZFBRG)Ff6@r>6i=o_`tZdG<
z8s@Aev*rTbqJW_i+f5S?A3G#2&JbVbF(6{6?A+dQKhqEBd2@D5p?HF<3;1zaI8&d`
zbPr_i_CCsK=G<7CD{=I&Y`cYQnp$Z9AEsn3l7FQ8u<f+GXa;vV$QWvXLmWLN^<?-7
zQ%ZW{FSbCW(0(_<Y?<ty9#d3`WjZNcPcM|HYZc7e=3>Rhf<eLz1is3?WX~lI^?Zh#
zYW!ZKJg2Wi(xK3>ew;{J(D^!#+Vv82gt4Q8+^XCxJ?F-hl|zSncLO^+@p6d`9zhc3
z$W7t{_1XlOxg<eL2mx3p^LrMGM3M<R1?`jA#kM5#EV{lJdjZwws<6<IdJEv8OGGXg
zjs}dow2^6Kq6T$V$&@gn9inMGQXfWTW&2-jZKZ)tfpS@c;z`tyvg<(?U1D&vV;Dq|
z-9N4%imB{d7akzXsjMsh_sSx4_D#zLAuWwGn9gQKRO|p;&e6{daY43<!aSw|7~ddy
zzBR3)%m<e3fApoFXC3ew07QlpjAR2mM>bi%vF_$PKFlN^NUd6+QeeBH!I--B{Gi#=
z`<C!EZLc8H!^+_&7PACH{|A3!hlICm`pY(s@i<wQ^f>q(ZGKzsx5!<<hB^yVHjP0y
zPovl_uc<PahuCtQe=@c~<|N%gYX~;#vF4IN?r7?&0hTgDF=F1P>v7+J={=&yP#n`0
zT@sBtTxd`rDoT#n+5ey;A#shZ9x7zI=73#<I0x7w+M^;o)kxaDu7sKShm{#LzE#%B
z(YZR%!5G?%eIF@4AZ$+ow}Y1sJ8QX2Y{w#Fa-WvOSrgqcV*2-JPb4Bzf4gLUZDf>C
zu`_)0?{5VPlcAW@5z8KlH73#&VJNvGv`uVRu*V}4H1f|BWkRewG?&PU#5Vkz$6$4^
zP#n`=`Bjwj&iFhdjshLqjf@pE2;#I9|Biw<u}3w9;0W}BcSrwT%o|D3oO2z9uFhp>
z>X&q2GSE0~|CDZ^lxuADec+u}d`pIOV&5x{n=Hb<w}3j;1MN~9oOfz3Y&RQemcx@$
z&G$kN$z0AX(a0bmC6O4FZMv4KZFVgJX0-jAe`|{;`mQp4@#!3^+PJruEFlrIm~~04
zX-~+p(3C%I;>@BSnnjrZ8{>YBr#6CcnmR+60rKfRoRep<8JNV^1MQ_v2RRgwq)vrs
zBrIeA!j`*dNHMR`x9@)=RC%$#v{SNY@B4-*-XI;$T>B|^=gpU<mglE}H2s1|$z=2i
z;q*-}UtV+XUy*;#fa!f+4NND^=WeX7*Z)X-?xLFn|H?mBpY9z1FliK$_si*(%3CXP
zI_W<y&Z+quYF)U+6(WtCG_BWbWDh3$`@VDa>h)CWp84x(hlEIWy&iNPA1;Xta+o|T
z#1wTtR=A2|=|RqH8ooR<Of(1~xUf|_8tqZTjytNR!ssD?WV*lj4fp)CmVMdfZq3~(
z=dY_Nz1(Z}{Wf)0{7mVfUVZIMNi27Qb>;VNQ^%D1>A&6Qo~_Ow7jNl1oNGDUdV{1I
zUG;*Q{ZESBYHq#MS+916)peDS&&b*(_kG267W{cVSO<%o2!dL0I?TW8dh?6h{n|;n
z?`WsyRy^JNe8D;?N0V*Ha};MAj@rZM4u%y;u_8{bDlEzRp27nJArUqhrfWld?C_nZ
zdzW-y^{QceC~mN*-t*-rWvHA4g2?o(Wbb>Do9;AkAiF8#CtC&Re122eiV_uO^_;oh
zp;2O!gQ>ocv{Wbbk7cOl2&O8!o=r9gVGL&P5D^mq4Kwvxw~)%slbwDnUN!KL1Dn(|
zV5mCP4oY_h3X{?RHi>ig)Fw0em48?X^?3TSAWh?e(O1Qh<?ctr(mV5R-+EfQezc9@
zf3mkYzDkD7m!?GZM%u3I+SYkkUxTBCS;S-~c<<kLAAPRhd8j|Q5oS+ol1(nMfr;(%
z^;v{?+m3nBJFXv$tn584kBySzbJxQbanE0ydy}-LXu_*sf~R%Q6@vYo#zZ>Q7xsSW
zx4me2@X7@xipQf{;bI7KDb><TY3-rF_D^Dx51=^3jIZA5%%V{Qzc~#zf$Yr~qBMhW
zGK#G8kAx-km+tAC<|#1y^BK;T+FqLKSL0rDrFWi~W2oUpL5WRL(a)FHNdn}bSU&%0
zwLf&EIIZnHfW!TdC)TyuU}iJF=M_#pLOEI3lqxPsbJGqyFhu|wSR73A@F<9e`_;yX
zOkT+ccv#}8z(RnSu56NrH_zSUAxjM$nQPIX12QG#IUj8wp9W;ir{6BUi26`jr-~+w
z_}~-}^x?Prwy0>T^gM-G$|Kxb&Zh)qiv@E86sHvlDVOr}8_s>@2%D9?Of3=lG8GZb
z6OpT%w?a6Wbr6WKQY%JOLdZ-?<i}EPb$kQ4Az72g$h>JaGlmboTmTaSX_Ws^yB+!8
z*~pe;7RZVJ$N(23@LeM^p3-J=h)j2gRJyOVp8$0QTY%Er`wGs?5wau9O3SO(@cXFz
z)~e(AlgqNa#>5FZwB97UY9{Bc@X+m6AaJ{$&{jzYnKy#~@nXSLXRM(^cswbJ2{mWt
zjOfM=g*1feo^Sr=4-$}LOF*&jJ>yQyG=-CThSaSF<z=d)bY{CW3^nA0r3-xp)&;b|
zkSu&>WKUqSPtX6MS|Qq;7-jU#f2eSadhC5r09#Aank0cF`B<BrUI#v^a*|XEQl(Zv
zZ{2LPK!T~2LC}z8y6I;1LEs$N6BsT$9C79s{nP(&y~m(O*Xg#lBE*dPwv74II95Ta
z?aPQCDL86Q@kp^+-0n>#fw!L^`bSl-eOoDW0v528(bv-l&KktfY&fE1n=<ZyfsZx!
z9A4SBnf}w?Jjsa>QodNQea;!OqS(1Y3Asm4lbC(-hFVKC%L;zj7jLVCciNsL)#ljj
z*v!~$b7ICM@C_Q{GgCY_Pdw5-fR_7_17owdjub>Ig1~oMLIut)^Q1vYW>wEBP05tq
z4ebH9Wmxf1BKL7`Rn7&RJ!mu9H#=aH_HC1Zv=wD^GZP#7muGQh#Lyi~<?(11jc$~z
zk^jZNeXlu@tbGBliuAdgZT^8E4xaZgd?0oCv9Ouq``AsY(5QT4Bmb<k8GWCT4Cb0|
z1gfZXst)?op54z@9aPP<J(z*WN!KcvlNx|vY%&lxmaa$n3~VvDs~wF4<{#C7?)ATz
zhepEO=zmQDP%;m_vc-fd&|hhcV(T#?PlF(CUwtyQX996)J|^}R<E7@F;Dp`$y}df$
zVjG=w?EbVzE)8D#9eRo9V`FeUU)^2G1NN3>BT5%t{bZWt$%i3cBhV!8t@IYR54=Sf
zVX#mSFl;6YB%;m4_HLsdk4W~Fa=;S#971Ev1nG@WZ%Gj}pa!-35?c?|5p){0D67rZ
zN&N*l-~{=AijR?!yLH$D^W~nMPR43=vwE>7&w%;d;u~bQVajBYxw{Opp$xMeq!h8v
zL{Gj5c~A~9{S4}Wjc`DkzYM1XN4nQG&MYd68ugR_2ZEp{*I0k7+kbiey)=+ipzk?r
z>4#F$zvh6W-~TT{<NxxnK5Oa4;tu~uXD$7tK=W@X75%Tp*Z-tw^)H|O=}`Zl60QCW
zspw}<(7EouOgA$xHlAfRfaX<ZX=9g-X<-c0&6l=}d;^Qo{ACOnzM!MTin#mx&9Be=
zNzZ%!rOo&3H~)sO+rM^y?Av-QNp)(}Ik`gQx|tMkCkZ;u|10cTy_=wR<sk2IblM?I
zS7Wn$$)8Fz2#phBadKyk@!?hcUQPxnC(rwxp2k^JKFFI0TYtynoS}7&@x<xtchmKu
z+URgZ-*eOTI>%H<+njff=L0&2NYoxlB!&=)HLGXjS5MuuBr%w^k(Q-wrWssX3~&Yr
z_Ey|WMzeH|GaE|mMp4+5C6Q|&4%gd5Xmk&XB!##S9fqWYjRHGIJpzf@h%i9Qa*>E$
zWSY6{z7t>|=CX6NOS~-SZDaXi71sb)e{Yz|H^PO+IX<}ohRJB7F}1zPDObPXOlkue
z7;~fqvtun`Ihyk={5;tM(lI}lQypJ5vSp=k{%Ve3RWZp3bjry#>4H!CG;~!QMSGG1
z*Reu69Y>WRFr8)T`jr%um~_?Z&VTyWq=YqC<ec`2`nE92XaXW}=^mK5#$?HjV~Ikh
zNKnYWMCYfarAQytuP{>xPGqTKEyiF6#()URw!&yJohvdj5Roz=!hd4B45vX#n!Gco
zi0d;-6p|ERPa0m${rk0@c3>MZM>kO&i26`dG^n;l-CV})F@#KqG@=j=o1-JASiJlQ
zTZtt~Vu5q8%^G2V=BQyKOo7CpC%ZlKr;V!Jhkc*Bkpvtxp3idhH5$cK(=fTZIWJ<&
zpVa6v-0q@LhXqb-<F(N;&!Ja9Iw>h6Lkc&AmO)l`_?;cYCMZ-9r3`h+F~HZ5OhS45
zhNq!$J~(8Ab;**qKNrM#93^$Gm71$HnF@R;GNdjrW`7w?2yPjV9oW2`V!g+54OcGX
zZr&E6p|njUFnoZSWXk1y3z?6u(u-1@{gT=?$1qU9AZnf~+~*Dlvy0m~^k!Rzs0p>V
zpp``?Ts1f}D({5fq$8l<$x#Q$!)!hPo<%*GDy4qs_#|qRo6(H?725z%{zgsX&<FY7
zv@yTpB7v-hT>%WCx>n#fnB2&j&2NQY%>2u*Sd+_IYs1b!$p%T7iH4EIkGO|4M*wQz
zf<(xM8%UbF{&1?HPg8T8>kY!9?@*l>)TRqW2)RXSfLVZvn6e_r&WL^c`~LxQgAKk}
z_D;ar+DvoE#mz0PSYmV2pEX4=0Ko*_o1RU_p%ZC1N?F>x1DvP$Y1y<pg*GO%<p(Lz
zuCb<%Ta4qfy79%IH*5~g7-co@p~f1tp+VL3%Qb!kMBbcY4Hq_(EbC-PC%T6_cerod
zQM!jur1m-zT7(eYOi&AEUJxT3b_KvOrC1VCadtY1d%pVBd*rj3oYNg|eS5r>OWF!P
zWi7{c&gl)3U?Lf?r6u)e**FtaJB>dYlp&=>NVnrn%2mXRUL(PSN$nT`8&5T-8MZ)U
zx-{xgmIDPO4FamSfk8D&2y}U>qc$)St#baX_x+E4!1RABx3yn#3rV_Bu}2W|%j3ZP
z($7k-%fVudhu!cb%I+1bK^QWr5FO$$F1e0Q%GefugZL8xBy<?QirQfIvrK-7h%3!v
zWd4}R;~~#XP|JN`Hsv|YfApPJjr_9G#D>fA|J&Z#K*@DfcmDOLvB$=So@Q3tjE&XZ
z8kv@{ktI7s@shZE++z>6ypq5PUWcq?#~}um$Y#Utk`2fGX5QctmLl00aDZS*Rt{Pc
zup#7R&n6s8#vEWzz%pTj7ef4zoWsWk^yHH)J_lIu?|<vP?)SQ1&rFX-ISQzzr@LOg
zs#~{iecgNOR#lGrE3MAS?o#z!VJ(wt-OKLT+=Eu_d=<z{rEG9!%kXyUf_7MDo>^&~
zOWO_@GeCkuZJ&7Hukw_3N@em}zKS7r9JaVHT|R+WKJ!morb|v&{9L724E9y%N<*|9
z0ihvy)fV=e%s6Zj=X^%rXThZeAXGvsAnmX=O(;F(g>SClx+-kK>Sr?&2L66js=@v`
z8^QzZ^1Ms2g~MrqmSF<GL_%}5eOfJ^8ib$}r(A_eyqDeLLxFXjR^t%E_V&ic#wMif
zq560wrx6mx9Lk_8KlNfr2ADI(!H8K5Ev0M_SO6+)K*HKjxhv#DV^T@T8~dS($IW~?
zD4?QIh@<5xEUD@FGq+3&oM^<{wu$~)Y^sD!_D1=w+zYp!y}C5s08XJa#lj>pY3my5
z>t~}w<3!!Fy@GTWxd#=A@z(bn(>|I}n1A)o8oh|=>PV>yk;~Km{)!acMV&xX^IkVH
z+@#e&491*^IbJe$mi?ipR;fo>UgN<y)yA36rD5z0sRWFI>k~uX#SQjsc|L{UmNbYT
z)S-b*LCiw*=k=Q8<Z5hG00C>fjcNmv$JV`<b1!34b&RqxkNUW|_v(G6m818U)|76l
zHrL!Rv1WMf6Sa{iYd2T?HTT0b+%x81Qd)V-{s1N8D=RaN(uN}U3;8RrC<VbmthQOd
zt~M?@Qrxw5S~C*oSX3*yKfc*79j&f@rdqjU!?iUAjtacZ%He=x!7sdRdIL6Rl?N;3
z&u!#ZpSvsU*QUr^2G8`qap#fo&vClJeWT@HpT6pIuf6c{(Z*|np(@8da_{)qEsfVb
z>sS5N&onlSAN$L5Y0ztKlrnv+IsF8RL57gh{@F)MJ_k?x=t0MBt6<?lV5Pi%4D;UN
zK_6MZhWZUFh2nmWk6{Seg3fgH&HE3IuN=ChdUx@HDvA#5;j8LG>{dti+&QzM#%^>D
zA1`e{Ot@{@zq>Ls?N?9&`dq<Ryv?6^-^HI}T`YIuIUBF5?7sZM@#3u$8?*{jy0G>q
z7k_Hpzh|`kchf#H&4;V|{F_k?BTBLBn=NgTB5k|xw_=++=RqUpc8B|GrYTzID;3Wy
z?%eU1wEz(AX7cDha@)V{Hh#~}p*WM3!wklDTmWp>qoaniZQk~6`ZE+x2tm4HePy1=
zjGxE8man7SYFvxvY;3%8_ei{J`}I{cFcW)UFWt=JwT4XSQ00}1->Gb!uH5BIl&2Xr
z4vZAd=uU@YVkfqzQpvw+>-cyjystQZNpQG0yRmx35p*e6<jO0!cCT2O@K@|xKl=`D
zG3LtiS+;k68oRkeNYb?f>+9T}GsCUhmoX;2?8e50Ty<Xg{F|DbNmv>EO!dr3lvG?%
zgqhuH_M=|(M3aTqV)^)!uhWL;+#2kV{K{d3>QAHfE6q*}Nnte-_~osK>}X630G~z*
z+=GRf&L5G1-IglXGv-jQc!-r~n^2Tst%R1ia9};X6orfKnf9RBY)!U!=t4&3*m4-u
zW)SQ5u%ny7ZfwOQTYOP69OPswY}14$HagW73a9mxd8GKGcf4pzlPhb+ip3i*o;(9%
z;tQ}=<n)G-*`a+ScU9I5-Cnwh>xZ}%t7PU~+%ZFzH*uLcyF|GV#k3h{C9(P9s+r0a
zLlvwK7y>j9Y}~@N)|YMJx|<=tJl&|-DU!Ouhk>CudxH*;-1?W?;<KUjd7UAO(nlAI
zbJ@)wS2>g!&C=8FIjeZh6zC13bej5&Gl~b-KqO3&D_b1>8aMH)d$Y@1tJ{4n{yj+i
z#2mUasS;sNASjc~nz3orf3@+J5N1rsv8c_pO5DIMD>8;&4q1GTWnY%I4ip>cJ9JJV
zM>U>*uv$d1hjkqH9n%h~#r(eYh5V|=Uc{*DZ8-#Nx)BWZI0N6<R(6XtCQ4PZqBgPY
zy73Sq0C)0?uele!TLYV}5%e|an&!N_(7tUwbg5knzIt|8MdVb>fTLCRUFKEU$i1(M
zA`@EdTdxhyEA~}qq~&RXdzD?ed&g0CHfv){!l-w!>e7bd@Rg52^zp)twMwN_Ksn2d
z%!$&R4v4YyNQv`JuuQ`~Kr`2?M(m7%L*q0@QKHhyRgTV$6xF!UX+jhRf7_Y8!Gp5s
zS(y&e%;w4mE}LcPj6`fQ8NnX0gd($6|5}qeZLw@OnMZ{+IsV+mm$TZ(W#zA*o19=3
zY8=yyYlkQu{V-S7d5*<{e~1Mn{c$D-(iIqt*(q_SbPXsAC5PaD)XeR0O=dPojMX03
zgY(1esoT`68_~3(`1I;1S$!yR#bq*;n#|Xj<R`Tyh(1z&_DwIjV2ncy**7^mI#lFZ
znB5`*swfIL!aS*?*x_;3zzCZzr|wUbN<&-bxJ#!o<bC2j+&R>OBZJzxG6Ujh4J}#C
z;~H#_wB;3Ix~?!Do;}?Da|q$nM@mO0@?N8Qm|{VZ$#ZIVZ=ijL-}q~|Eoq_(!=q!c
zGMJ4$jU52yZ~M@w2WY6l0f}mq0t7z!=e(nAEs!Rn2AvSqigh23g~Kp|Tl^LSI~jNz
z*cdeiW56CN5E#0Y^~w9#++N#&#tM0I!!_6d<(kzyAI*KB1Xm=xGzyDd+6>p<RLk5$
zu46t>M!gk9+I~j)aVDQ}Mbh|xxoNCWe!E!3OWxzzK_2XbhKZ^n$D!KeW**zz49|X4
z7wFj0k}T%?>@Cc-R=;7&&V*#^*wyr?2IXZslfJ529mzlS+e6E8AmqPj>ott={`B*9
zzGa5KYTcL4n5Jvv#0)ON(Z&>$A9_mc#Yf{Zcjuo*9{0HD?>PH%GI{v1FSkm!vT^T=
zqcEzN-Ev1QOe1Z)sP2Md<l$=NQ8Naq-v(cwLkGa#HB8gSX*HbRh+Q`lOap!sZnxN4
z;a7{cH>oOwxl5Tl7vQBm4sbwXsa0G4fnpgeeWZaZY_C^6@1uxcI}u{bx?=;28g}V0
z1NrLCMa(G>Jura+EqGoDJatS1ki!`GRSxD!mZ`le>ypd_t?B9M73Hg-A32uSk9(|4
zV`##jjVcT@`lz!1-1q(ny!<A4Q0QTXO1dXwB-UnV!w@RysjGztk=Wklqm_~254S?I
z(U?k^!z!wVway0R>nK^|PVpgcBM&Vd#|j>j*|pJ)@`clPsDcW4efvmEqMb^qSym<0
z7yx-e0hNsol4?;bv<13Ai93853khN;w`f9Seu<7N=k&75SXK*P`7Yg&gcCp#&marv
z)+OkL>ckQtC{dSssXHH(hYM%MKsA7pfU=Q-xYQ+E&9FtO@uURQWcd7NJdfG8LAF8}
zYdmNJMo2-RFR`h`DG)i{GLiwlEL$V-5*Qv2m+vXn(Pg1FIt=HmqO<9Y#tj)nN|D86
zS<_ur!z<T%+bazujj8jISv~Z*<s2q5Emm+5rM=Y*xdE+Z7&(sf4kc8PH)GbWo584z
z;7bY#lhQ5HEWxl`sZ{*^@Dkj&RLOZD!`YvR<GGzs>S_N#C1B{oPWaNA=dJtiRI{84
z<w0X8E|lfan$@7FRT{knGYTX#O6iO4Ds7Re4h-x;Bvl_Maiat4V=Az@9UmV?Z%BLi
z`+yqdj$n`#0EyY<3K~w4SJ^|a7J3I-f~!~02Ljp`wG|vD5F#^gxBENQpo9tY7c-3K
zmzg0pc$<IWT<>BCmA3>YD;H6oLHN=*)xyS40ix36ActBOsiCRmRQ7p8CsqsfX=o~?
zido)|4|%jj^ZwfgC1ibt2441wuhMurf()n-25^X%)H%0fsXb{IwJ*5vT{u%r<ftCX
zL2IC<@e0o})g+vXQDMPj$XoUCTv;_CN=q9td{`>X!`POg%289N1SF(2KmnBn)q+YT
z*OID>P)M!P0RcRL&-BbMU;bWtQhoTs+lt}rEhHvJRDQA}E@U&KS(=>JLa`zQMN26O
zl!d6OAKHlZBOAvkp%?6;ny5quA4O1yr9)ltLHX%WK%fg!BXpF&!60Y4JVk2I`c@A6
z7SqacSQQrkTWbfY?L^Q(?HtxPt)cKOKVQ#B`9W7yuhLgQgqGUBuQ7;>RURlu&w^;6
zK+C4;iA6E!J-d8DAnFkf7ryLINkKAliaNw+UuIY-W3@xdss;=Q5rIO`Tc~-fOT2L;
zu)UPRsvr5RW)L1=z(}@)v{d~#yg;aiBj4rrvXSPk=;&7Ffk+Z!D<^6mC!0B<qOU?j
zPgg?=DS{GB2D>c^rFwu8K=nyZQohm6tJCpKiLk6i+4f66C_^B|X+}+wLsJ_oTC`f8
z8Fz^b>03D@ZY!cIFC7jKp_EVE(@<pa#22Vjt3B||TrlK~Ub%HhM6nyGl}L4_n1Hty
zDKFSr4b$k<xZJpCIWR|(fNj{s(C}5}&%l!%vJa!yj)%^CFKX_qDvf5o!Dzq$Twc$Z
zJEJegcvNRP{gXF=uRr=A!Fx*tveXjzyDEMKpv>|WW+Kd%{4xRfID~-)RP!rL^BV!+
zb7G=Da|FG<&ut?mwy1L;>-{1Q+O^?&sq{r!A(o#*)zKaQ>x@lDMvE((pv0|PfCsIe
z+!%sU@ygmr37%pnwpm9QxGLlvtmKs9DJEo$k+ACJi&32qvodw9UV`?q&IAQ^3@>y*
z-prs~A!jC~(#{IU0n9WwxS}Yl!CjTc{S+|(f<m?5_qJ&kmuk06SA)&fGcE`k*qhL}
z8qixGog16{r<3?)V6ZPF{eq*#;I(OGXzgZlvfJ#5;ljXZn8E_b;ww$`PY@qOe(aaH
z7w*{aosD93q)8!>a4Qr0*Ly{-DaK&vpO`hvckH@xZqpnx53@U~37oAz?7hD>alC{W
zb$ASoN_}|j_(w{I1Ei+eVISdxv*<^jWST>`+G)EH-!Rw0ZfOQh%H1PA8yJI4hq$AG
z(F&u3a&9-v>zsM_=*R^dy?QmzA^6^<!C|uEoUH&Yz`oUcUU8O0U>3MqIgei^1w?SH
zNs!}#Lp#Q9fw=;;2!)2HXh~%B`I1}+MmuwL$R;hyu&|OOO^M+JWVt{MW7Lu>+^DG9
zx@I~OW#@VO;6XSd?AgtESzy>djh{V$V2+XoNCBCNDx{WbiBrl{vI>9{L_hL$ae%#-
z%0b7dA(Z+m@-QFEgshO{5tfe_Ix?>?N8!B}{`|#d#S%WSGQcc)50@Il7*A=yVy7RO
zGpJG?S8fc}#u!%pT<eLsoKysutWlxhT820x5cd*j*klkWiH`VYL@KI6xvI$CX!!N-
z%b)^l0rWlK1L1d<$OGdxsT<Ip`HCz}2>Iz!24k0`xN4bxM@n_*#O=O9hs4}b!LSk2
zmLbOBDI+NzK1X?ghK<M^g|6*JR}en*1r@ph0?Nw9EQUv_N>!okX?a%Pl2on2%gUPE
z=oo4nRyY-3VTi#<<c1yLu9l@k@m$VoQsj&k(ww*Bf4)>ELzobe36#_*NqI@5xR8P?
zu~a9N+GF5!4eMzi9GIc0kTR+@h)F~%vQ-|94FpV2!8>$Mu!Dj@^9o;>!dnniRQDN9
z_fGI~?8q(=llBFQI{U8fS83{dCt5j5xqBDQ7keH?N0<?^sk6qx=xM?~JJc{$SK9_#
z2UPjdvB+k(T8;iUKY1oRQohAT4UhGEWvdD62)q#^kD<nFxxYda#{9<j4r}5fr4hhV
z94_shp!M;>%_NkUa7`6!^Dy9=TvWvH(T}qCO@kb?!k$ON(Aqqs7N=%tGG3{s12g3X
zC`kgJ!F+9?E_5WI8xdI)hJUc64OAF}pmkvV+Xg;T&S(<mY06(gMM>je*dp`=tR@_;
z{N&9^)0XoxO<QW2m)u@*(KAP$|Gh5LmgoDJw!Ht&6p*j8t!&||BZ9=$5sk#v5zljV
z1gXDp5`bjvb9?#6%2wf2WUr%&wVtc0q!pTxOF(6%BBq~+cKq>OsR%sOIss+1^<;p1
zRi^Q0yKv;%7R)5AlyeQ}9bT~Ahkf*!)WJjyA65deDabsGi(spTd@&llgA?DiA^>q(
zw>lj&J|nhDrOv@_lev-FRmM5VE=BI;@A%-0C<DAX88T}V%vv)ni3Xj0Y!@wYDFtow
z7R*$b?sEVh+U|oEL-GuwBmD$J@~Td3qECPYSD}J4e&8`eXc{GBBO2xspZt*VRj35=
zDw?;`S69Zv&_h$E2quA*TDSVGktr6wF^ur`RRD)m5n#&1oQczxL;CPGnon{%!+Gnu
z^S%{5_xTxbhdZe4$Bw7-BJ_W=6Wrx9K$J4e)v^M;qmM!B`CO&_vJc$$d&Zh?ZSxvB
zJ}rP~EjTr3Y(A0698dU7bD-s17tX}0I;OTP3j$R)Ek{lV!t=v_cUuI5AFIL6qkKR%
zC$Tl*1Tlitd0_!}PUY+QCio(Xx1+ckjWZyzW8@8>A*Zph!kO}fz^a3(S~VV(IO>&!
z;T<e$M9$FS%d&J~3H%~27Amq)qpifw@`@iI>_5D%^Kha*9fP)9E_~zG<pSk-rx6>J
zmZvzyXx<S^MZq@F!ZnMjCuprCW>Z|Z86@hecb+*Yq58)E8EU{9t@_fT&kM5$aqki%
z*qt9_d=pFEael`uUztiaM~%CLPLrarMAViWCtE{zKFFDNE=BYm4e|ASDm3#!ObAYJ
zYYupM=*stD#06K&+G1uJ0;4h36i^OdaEy>s?yU-@H_o}xhd-4VI5Vc8ei=pK=@j9v
zUtJ)6VxCCGj4({sWw_=Ci8!g6NrY#3V`%ZOMF~H7SvqPzfDT2z+qkwX9smlo=WuOI
z$OvpdcyX?6aB)ELch4IZ)%~OD?V3pq5J<Ih5y<cjmn4Dr^;<zwZ-r#C(Hhcs&YY2o
zwAhDCifsG&v&!jSu~=}u@kYaEztkJLaEKJGI4Sf~kykx`R_b|y2emICsF)~W`H4lE
zINj052Z9$T%cPt4__lN72#ftS<W$D4a+3b&&z-YaC~-XBWCosGxl>q%!Joy^7WE6g
zzzKPUPkl=3tpb<ou=V5L_%Dlsm5e0qMe@1he;iBw0h~~QfkllAKveTWm7i3h>(5+!
z?(_gKg_{phq&bxP$OjVZD0Pr3cle4owfdAHGcU={d{E;_XBkL87X?MKr%P2he!<OZ
zs#--Fslu#CF`75MC@4@FC~Lg}#%EaNOrW0et{R5Bk>J-!vgOcSY%G!%@+vgA(sZFp
zLL+xnYC$x(KANtc#OwZFVur~qK`KxH^-p6^RnAg~D8LkC?YP?>7_2*_ph9sW@4ng~
zAHL_z@*tE4gwx162!>w@$<gr8zi&fdjK@*~R>(;)OZn|Pkv4qh>crE+-Xut)t5sP#
z-M7Dzeje<Jwv%w-hu^ILTG^5~;$V~XDC!nkP3z^U|IM3D1iJ5_)87s=v(<fV0*Ew=
zj*)!eHD@Sqd&zjAez0sze*O5@zPePk;l+cf4QJD8!;_)$TciSWeoQjdhQT)yO=&@|
z##1+oYyH>Sp@!E)y84lI<y7-byj#edgyZ6Fe$7kf7D|<PA85t^s|b*-6SpT(7jI<M
zzaC_CEKF&xjOKH|s?aoMJ{|XpS2%wvu=Cn{<y;~_3&;uA#TEVPZ=1P{wt|^!%O04u
zBvPfl8o9IGU9)jGsnM&MIT4ol{b5BDL6ppolgGc?*1Xs&<am;fj@1W&wI`^gkSu5I
zrUz0SGkoZuVsHD`K-aUOrP(X0yj>sGB0cYsgWbHA;o1h?*JEVtre*l;7qSwl&?%QC
zBqSNZ2<}slcJ5wIrtg6lzic-aSGxA2y$_#BlNB3Fxu&ZW^Y?tg3-yG>0S|oOrLO<7
zuuYhhn?Q5bDsQF>EVPYCR0~nmA0F?dX|$V2!`flzO~U7xv_wGK`_Lm1A3{mB{LWif
zyFB-4eyW8eQj8G}<p}btpKNE*>0~s%e&7^4ZY4gDQ^0ul!X1eX!AT%}8+6=)lUT+$
zh2Q$I^Qx$>52JB*g;j^naDcJp9S1H(wG%P?>iTl04LG>=mgWQG3>UAfv|pux{-{Gi
z09Y}FSs(NSMCtuDG(17_;U{l(_;Ft;V@jjZXg1Zd9pKT?W-~H`Nv6RMmNMwFA-fIS
z)Z*=k55L3R=~HM@zZjO#!j%OyXf!!=t2s(|hAYU#GbuQLzZR7`E`07QE%(f#`xdZu
zAC|t=*4YxtrxQEji-d;+tTbTn&h;;)A|)<tnY;>lVKOhCALJ!5G?69FVNU>;b2Jx}
zGiLH@Z<s>_nf)Tmz!Ei_EFoi%EHPxqccZQb-Bl(|v29WZliEN+fDVvIlq2D_MR^k=
zs0GJfM@)7i(vLnGJpc>1ZbYEf)Gep%YOoX#LsE(s@ZBc?lx2<&&3H~oEEpgGR0M~z
za>{gSE~-=Dwh=Z~z8yRK<pYtQmIzR_Ag}4bHTqFPjU0G_)CP+u>GpgCEu&maWm#=-
z21cLe;^NwO5<el{aW8x+=N^ohsyS*)UE5V7;QPBYZIgLG-2Y(9ZW1=waG)lzHqRc6
z!vWwhb7*=c^5_*Jy4ZUeiO}|tv}8(ykTgZ>OY{B@fA1W@B;jP!US17($cCOYOwU?K
z+L0_rY~Sh=qdT@;NUNI?FTyuJwp}$5Bd4O|o$yi0vst=91@tXSy>vgKip(Euqzz=h
zg8srEBA1kav+lq-{Wm#GtZLqI`I9$3f7dNo3iKYR@#*maY!~Kd{g*|4SQa3?Lddh9
zUEw+`mErm-o~63*Sie<HZL808#?2<*&>|vcZamy|N6YoB2DteVOVF?}-DBpkWSYx5
zjut>?Ko&vYB<7TJVr438Iw)QwI_j}+=i13El`DUv9hmeKoIwxC<LulDcrwnWvmEq7
zelpi|90K1qkVLqS)A70;jn}7S9aQ0Hh?V4P!Xy95rD8I6V;<lkMibT$5g?lj5r|G+
zQ2{#vk8d7!%!bNq5Jcj(+|!BZe2S&QLrkDb>=bnHjLCssGv|5R?y$oE07C*BorN7}
zHZ=v)ue;$g@f&0qCgYiy<wXj^9q7)<bL{V!Y?Y&Mh4Une234MneQ*(bzM*X-GzwFV
zd;GCiMiZD+ow)Fp^R4)J1vT<3FOj2<6OK_^A_Gk`fn%s5n5*CH5(36C9&UaGy7I_&
zlv+@nv$``*B&x+=$Co5JM^ACId4H2}1-t{DQvZ)HxS}?gKq#|KPpY;i)izJT6BRBs
zD)?%<LmRJkAJ1){;wj%IWZU1bnSxon)TV=WBy=UiKN|klW9?!VnoVm&>Q&m%zJQAm
zOvO@W+wS5F1EEPna(JoW&dn>FTNEidaAL~EJ&Fi&;n&}%A60M+OV5ST(S>;l*Lc)A
zV*<+;KJpt;dyHEsMK<qzZJvY?hSHV@PSg<e6CQi5Vdpsd2-k>>B4(!3Y5;KJ<|JS2
zck#owJy|xAxSBT_P&;4>ahsViJAuG<HJ*f7f8xPh9Hk&}!$e^Qzo_)_yFR}F6if#<
ziW80<ESG=;MiOZFhY$iQv4f$M7maz_sPGd+L>y!srW6|t2{ok@Z|cXNU1x(H7z46F
zBQ>a&jmc0ZOxfVoi#T(ZS^>>T<PA)i@|nggFQy3IMm2f&%UZBV8d#Da$x^Y{qtQ3Z
zL2Glgj{=+@tt0tS4f847@e4y+9@9F=)~2_WwG$4X<+|qkCd3&}w}$!lc@HmNJlb4%
zbwz6^EY;i|#A_%X8}R2?d|4~0XZCkE@;lG#T}V@o+b!;Bo@v$G1Xq|^@{4$K<RBZY
z_>KzF^<&1|(P9UTG=+iNue${nlZqnd|DmZ|lmqbTuEv)~zp5>XSJ{qgPQh0!&~|X^
zYO~v3^^!8JM1X-}AIro&%m+JO)DjuurYpd0Az<|OA8>8}dDxc(EP$%2C-Zfa;p~Cu
zUKgll<s@~=t{ktvfFIFh+oxY*U=@kpAW=<OSvQ6z{YWlMV~UtWsAW09CO>@k;DsOi
zBY};{3f90i>>cG5kmcMeR=h^0iVS+A?R~k5)`Ip3MJ)AR4Y0$MH%~Ak5ryh+!Gsi~
z*5^qi=f}RVK@I9!+e2Uh1fbju_4w}Lph-sT(Md`s(7&$k7z;8fDMwiKN-^v;q$J2h
zWSOu4_cc6U<qFgAwv5))z3-b4FSUsS+w%4E)#2yOhrR~3v7MG|!jXz5n5a_W;WwL^
zD>MJ`@+YUB?>XG>*{c_4M}3XE*Lqd+*JpMIJK`e`QzqRfx;Ass-77h0@W-Fmc_mL?
z@sIkwVArvY|Hy%<&or<z|M2*$OS)Y9I&9RRFAZiI-YXeB_q*$@wY6CTo=ojvp_yNu
z@sxg{n#AEj29Y>yF5K}qW%t58_kP#=iAuduy?1YD889YBo4kzA)U3-a!&pP(%y14d
zlR9|o)4<hEIJQu%oMRch!ttAFX>vC8QViNS^SLy1f^Tnn5Cs$oqH>GLwh6^n=%X^P
zTkEWAz)TPwzJf-8!&ZGJ!+~N1f=q<7oG<dSspK8*k#D1dgRNQ6fo#7`c$fmEsuWOa
zjjkU#{O0ytmoA-Q>xdA===o{GNWDS8t>-wA=6~l?!NRR+{4Dj<&rumt$b*w)frzke
z3VXNjGIeTG$$?_OO%2sHY7@xz9}Yy+>yG0}3a#0QeG#K5vB)-F1D#J){G+exU8rkx
zVD$RhY_MtsAaP~6nBlL@L`jT-@;4K8BQ(36<z~AMoS?<G0S@Ab;dN$h-~cjN8E<H`
zOsLVv<Jg_wG-eha!F>99r=4!cWe&-!p8D4ibacI&76kQ}cA`ca!3gjDUgT>6NGKY<
zP7Wj}+gT+DDgCEiJ$L;-#32g|MlPBm1YYWmLQf<W$}tfAZhNcALuxk0AzLq(U?|ze
zWUXZEj^9rex2x#hPa@L|qoHF>DZNH25usmeYD2Ml>LNh6<1gB|JL=hY|N7Cn7*vce
z3nU2zj3SJ4#u~N(dEtXGR3YUWl<Q3M02TqQo;q-1-^U`XVWSKjV==8=aOv;}264Q_
z{aWX^Zc`MQDiIv}%$HuP@zf3&S|zzrM1y=HQTVQF+!M2fL=yym>1oicX(dJrJ<KC2
zLxw{j(Fme%%fx>1+EXX~vFoGJrw%;Y67??i0@4r}LKN!~o#-7OfCK&!e5@T%4t6JF
zLS|2Kw6GX0&WSsUKXljFtHNYC>jIJ87`-AP1a)GM7LH$3R0os^*;cLmH0$qZa^<M!
zO&<<eS1NGZbYXOyt3wuC`MDYyC-A;7cUYEijJcfc!ATLbrL_~fI-tjfY|mxU3MRZO
z3lZY&apITtug9p3cCd|nw%O4bS!<m5y2g<3KS#^yqES;HYv{&?Z?X2;15*KXN&^i!
zw13(9sP-|pT|F1xbjUqvnF@xUkJ?WB)Tbr{uWikz2h-MCsDozTqv8I?-J?Vljr9&|
z$tVo=eFtbwaX7UZx9Xvl2_uSw#&`I;|0ni4!n%beBZ#OoZ)X)KiP5xEk%vawapA|V
zcMl>fpGatBt%@>GfAdx$O;W&^`UCr<AbWexf2k@0{!9l?0ekP&(Bo)xSS5H&BP~rf
zL+*%02X>FrEOze#hSjRGJp*J~O8D%1RnG!-16QwkjkgQ$!^+umrvSa8O`HXy6GP4J
z0NPvILEfM0U1th^ygJIF&N>qS-=YZ@VJE+cVnmBTNN$?efTL4^bck5Dv~%T!nbOY5
z6H`vw&eM~$1oYfsc4#z!dE80a(B$}~h!1l;r;&|=%@1myYFKomv@0Bc-zQv%6Ja7j
z#`W@kJu(d<eo`I`AHVduIH1ir0EY(L?1ZO%!YRhmxU$siqnn)(y<rxKUO+R~r^u=F
zT@T@}y*(WQjQNm@BD=y#9iL9^ee@C+ph-N|z?+}oz9r@z0IkeUjhO%%{?1pUr!KVm
z)rKwOh=u}1B^%fTK=0u%c1*mCV)m7ck@iOb)Lu-8=?1v@>c~PMQ9y8=$EXcZ@R?4w
zw7k+FpFTgA#$dsxs5(T$wl_}n_>U5j8dX6pxKA9R`xormKvZaPY>=|!zH-o;wkNHR
zI2MZX0$KAIu=_f3*(y0mw$&YR<a+LbUvZK@vnqh}C!dK}0y-aH2gI-z#vOOw$76pq
zLQvOmmHfdMWIJ(S0V08Lbrmj|NIY!EJ*BlwIkockObv$p7)pz*FD(jb)JgNH92W5{
zSNL{BpbEG#tDV4(&#}^IWMYn8Z779g_`oYW(TxRaN>uCM+j*Px0Vg4=C*OoS9*G{s
z__zuYj!i<15Xs1qAIkAD#DZwDPsIw~_;1~_8jb;qK-0bZ^>CLU-DfPUu39;EovRyU
z6b#WMrASB-8)&i>J~LR$1`f87lXyWEs8_VSMWECRE@%4=@43J1p2-GgUwP%FWDwsh
z6F73Fdn8gMyjo$Nik#UW@QCoDtv`gvHR=p`A9%~zbCy&bdHh+_Vop+QkwgP;OVdlw
zc_Zt7?riGEcDvj>0l$U}a|5<Ellk)S9K1O~%sKVuc<%bqh3(h0lH+5)#-@cWbEY;b
z>*U9NJ7G3&i|l|kZb)(Jcz3l_DyI+Sj1ny4sB>zGO5#D6)<0YuPvLO8u+x$-)Uwe3
zD-Yz3Z0D8{cqc;Hst4?QS{U%WS8a~QKEQytL{x)j)@<2u0p)P?9b;@;Sp>RW&z5e_
z9nmym9bd~UhN<Pz2Qa9L1nOT7PZ@2AV^3rK<#)RDPC&%(1UY(y5xx&Sr2lk-pwNy4
zqi8KC!Y6$9h0aI2l+Xgs>Q>Rx%{(=zo+O9?$-y-yOa#^ofA|*4<h62Mojc|UMILE*
z*DLm<t=W)=kKQ09ju1OT-q@AXVoi74@LgKDQ3jTzAfdgzDiVjLEyW_i#R(M!gbE2R
zP$)b0wrkFKPp1T$6_8v;B^*(^ZkeW;g>IaS^Z~vO83s)iTg9-$d%En`?rfetkNw(t
zqp#_2zGkP|F7ZC7Ww}&pu|Tdn@AB7VtvemiT2C5C#v#4GcwU)`$Z-8;tVC3`k(7J*
z!E;m3C-T6t1g$pwm{~M?Ejmy?<Y*M?Ee<j9P&_#2ROEZcI?P@KLvu!6j6^@@8@Rxx
z@C3kU8_DphAm&T}5z9kB6u>?}jdhB%(<B=E?KiyQN`CEB+f?|H9>T|-SW>#oL?)W{
z*c)a>T{!U0FD14aSoB1t)^k|^VmkR<oSfqR;`v!AmKHX+2p(g`FUY0co<HbX6|t5S
z#pzE?1DRr}EJ^r7cYbO*k0m}0UeNv-{R|x=(w_(ey*W*>fyhPVQ<`FQ*b~_;UtjzN
z`yG2?jmn?|?2Ug)le8DzC5D{J1Dyu?j@qAx*!(D)bsiw<Hg~4<04WBDda{B4)bs6E
zoe<x?`Ovbm+Dq(L8OcuNu9kuB(t-vWHM3P|os7fRFE@|gfjz&kIsa?#ftyY@vIR)g
z_4;({?;^;8kEbcNAc?vnoTgY8K^A<3VyJ``ab(p1OgP+G_Q6=k|L=DeL}<|wPS^FK
zNfkw0W{OFbc*2Z$CR-i;D=zZ+mkRu}MNr~s{fw;-r@Tebpxr7f{xWy9?kpDKPP^lG
zp2Ob5|2r=S^(|W|wFL2B-#=*f+3}?}e)x^;^FmFHT*;2QxX|1GYEehZE(%yuI&$kS
zi%OOqDg5{!Bwy57t6aJ}`r2+?{L*2ml+#O3o=REIt@~)S+Mfzv+C!55OM{R|wQS8F
zm_PN1SwB4b*KRjRf{07@E;q%NrNLS$!%c5&wby5tT)rsb$oJo?RnXJ=^B0wui>6CG
z?K-<EPvueIv;sXg0%~uzK7Dv>*H-D1%c9qhf8d@)ciaRA6EE+_zj5E&GuX+oak9+c
z!V{ld(vZ?)$6(OceRsg6$A~GFq}$`dzyEAc*pdU5YlJexo3|fXG9Jl<r#w3#WKWnw
zw-R4@VQ1Gsk_1cfFE`V(6dbbB)N^mYCo6nuVawHEmHVkmu~QQ<>y|rSep=ufsNoil
z|H_fmOuF6Cw&=NjAp)Of(obBuezFZwB182I<M~Xr{s4;wqsMj*oi=mfB%;rJ-mL92
z%+oP*Sr(OrI%56!-@I+14!QXEOy6^hk3E0PrSj;RP=9K9fpRWU-rHww4}T(LFt564
z+l80^X4`+lo}Wg(u3JF$yd8HBC<x9&*X3-nqeoY^S4HN@a&fPg6S1G2yIrM^TNXF^
z&`*-R^u%B;XI)C)b7I&eQ!nFyQ7jz4Ve3B|lRlO!Zu^sETTmOz-G1K*E$$_0YQUC@
zP2V>%8dg4(1b-s_eIwpAYfl6~GOYp2RIVjsE!IDld-|5MPnJ3zRCl~0f3l!+2wNq0
znpL0pXWG-+!>a$`__pVB%f_mgMxXlri7le0_`4V0b(Z7R2k9w(pI%cq{+(~SSA#%{
zfThr~u*d&fXG?0I9D9O0sCA+6^lJwJ)&bL#g985c&ohJj1vdJ<P<Z$k7tHs%>m8?y
z<hz1WkB@x0d+(^7V9?8@rcyQ9j7hTKB{UGL?jOYXWr1v7cxMlCDKr-SfV@)-@BOXr
z__m#(U6k&(_RJBbQFvGT2ut79xe%F&1_^Y{c-1qIZFx2-w<`H>zj_c1=8tPE)$(9g
zuH>I8wtH2fcA_jw_^FS8yQ{x?ZvJARvzWIZ(63(o_Ju$!{{0|~=scTRP>bQh`#-Vx
zoEM5Y2xbexT24X033X8?OO7g;Na&o4d0lwx`gz|E^injdD8<@*m4;;P*1AMX-tv%Z
zTkU%EiCoq#Jyq(j93$GwbD7XwIZt4Dc%r5g4m@w&V=tksv!9*_s*je6e&NRI=*z1B
z-NI5LW!y)0llg0d>U1Tyr8za>jpf=U=bWAKidQPm4o~J=)dM3Om@+kS(NKJj+qL;t
zCAV*GYNA#h%gxT!=Ee_Jy_Kb@%SXMkfbE-H_xtA-hRZ`bUnFp&kP*fDNg+R>os?5p
z`deW8tAP)Ut5LU$!wJ&a4n?#XAIaB6m3lSc$DR00VT??k7Zp1?B}Zw9Tw)k)4Uu+A
z@#M;R5SpG+;9N^IZxZ;(v!~S&BF^I7somEXUygZWb`L@=I^N=4_ssUlM~=U+Z0`R9
DGZQQa

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ChewingGum_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ChewingGum_MiST.sv
deleted file mode 100644
index ba86b690..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ChewingGum_MiST.sv	
+++ /dev/null
@@ -1,192 +0,0 @@
-//============================================================================
-//  Arcade: Catacomb
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module ChewingGum_MiST(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"ChewingGum;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-tripledrawpoker tripledrawpoker(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,1'b0,m_left,m_right,m_fire,m_down,1'b0,m_up}),
-	.P2_CSJUDLR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,btn_two_players,btn_one_player}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/Pisces.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/Pisces.sv
deleted file mode 100644
index 13aa31aa..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/Pisces.sv	
+++ /dev/null
@@ -1,193 +0,0 @@
-//============================================================================
-//  Arcade: Catacomb
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module Pisces
-(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"Pisces;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian catacomb(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,  btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/TripleDrawPoker_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/TripleDrawPoker_MiST.sv
deleted file mode 100644
index 214a4eff..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/TripleDrawPoker_MiST.sv	
+++ /dev/null
@@ -1,192 +0,0 @@
-//============================================================================
-//  Arcade: Catacomb
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module TripleDrawPoker_MiST(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"TriDraPo;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-tripledrawpoker tripledrawpoker(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,1'b0,m_left,m_right,m_fire,m_down,1'b0,m_up}),
-	.P2_CSJUDLR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,btn_two_players,btn_one_player}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/galaxian.vhd
deleted file mode 100644
index a44c4a1e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,442 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-	signal gfx_bank           : std_logic;
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		I_BANK        => gfx_bank,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
--- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.sprom
-	generic map (
-		init_file  => "./ROM/prog.hex",
-		widthad_a  => 14,
-		width_a  => 8)
-	port map (
-		address => W_A(13 downto 0),
-		clock  => W_CLK_12M,
-		q => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
-					when "010" => gfx_bank  <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 5a4d0094..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index 49d7d7a8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
-	crom : entity work.col
-	port map (
-		clk  => I_CLK_12M,
-		addr => W_6M_DO(6 downto 2),
-		data => W_COL_ROM_DO
-);
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 841b2407..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,86 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_UP    : in  std_logic;   --  active high
-	I_1P_DW    : in  std_logic;   --  active high
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & "0" & I_1P_DW &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010000" & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-	
-
-
---	W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_1P_DW & W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_1P_UP & I_COIN1;
---	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01"              & "0" &  "0" &  "0" & "0" & I_2P_START & I_1P_START;
---	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
---	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-	
---	W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
---	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
---	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
---	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_video.vhd
deleted file mode 100644
index 555d96c4..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,430 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-		I_BANK        : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	k_rom : entity work.k_rom
-	port map (
-		clk  => I_CLK_12M,
-		addr => W_O_OBJ_ROM_A,
-		data => W_1K_D
-	);
-
-	h_rom : entity work.h_rom
-	port map (
-		clk  => I_CLK_12M,
-		addr => W_O_OBJ_ROM_A,
-		data => W_1H_D
-	);
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-	-----------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/tripledrawpoker.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/tripledrawpoker.vhd
deleted file mode 100644
index 0b95e2fc..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/tripledrawpoker.vhd	
+++ /dev/null
@@ -1,443 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA TripleDrawPoker
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity tripledrawpoker is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(7 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(7 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of tripledrawpoker is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-	signal gfx_bank           : std_logic;
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		I_BANK        => gfx_bank,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
--- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(7),
-		I_COIN2       => P1_CSJUDLR(6),
-		I_1P_START    => P2_CSJUDLR(0),
-		I_2P_START    => P2_CSJUDLR(1),
-		I_1P_SH       => P1_CSJUDLR(3),
---		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_UP	   => P1_CSJUDLR(0),
---		I_2P_UP	   => P2_CSJUDLR(3),
-		I_1P_DW       => P1_CSJUDLR(2),
---		I_2P_DW       => P2_CSJUDLR(2),
-		I_1P_LE       => P1_CSJUDLR(5),
---		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(4),
---		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.prog
-	port map (
-		clk  => W_CLK_12M,
-		addr => W_A(13 downto 0),
-		data => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
-					when "010" => gfx_bank  <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qpf
deleted file mode 100644
index 7fbf41ef..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qpf	
+++ /dev/null
@@ -1,29 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 11:56:24  October 19, 2019
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "11:56:24  October 19, 2019"
-
-# Revisions
-PROJECT_REVISION = "DevilFish"
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qsf
deleted file mode 100644
index 9a670612..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.qsf	
+++ /dev/null
@@ -1,185 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 01:03:05  October 23, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		DevilFish_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/DevilFish.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name TOP_LEVEL_ENTITY DevilFish
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# -----------------------
-# start ENTITY(DevilFish)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(DevilFish)
-# ---------------------
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.srf
deleted file mode 100644
index a455f0f5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/DevilFish.srf	
+++ /dev/null
@@ -1,51 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/README.txt
deleted file mode 100644
index c7b5b73f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Devil Fish port to MiST by Gehstock
--- 18 December 2017
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/Release/DevilFish.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/Release/DevilFish.rbf
deleted file mode 100644
index ae2be57753415b5289cadc8411524f71139bfde4..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 310161
zcmeFa4}2Wgb>BO?gx#Sc%h(ZuH(EK;>=06hD_bHd+lBdQtz8I`A(^&B*-6wUtw`CQ
zR#DT)a*{sVd97v!1M)5iiX^PKu-rrdq}VIQw*ExVQ5q*A{U>H@Cz4&KPf62QlGD~s
zng~?ghW?Z4eSdd$zy$=500}pY%|mc!=FXjS&pr3td(ZjZJG(Ewcw)N!uPyzL@4WDx
z?|f(OTgUze`rj{p_gmlo_KPom_t<y8`!~nFd+gZ%{`R-Oef~u!X7qi3*MVZF`>6A?
zbZQ#t=}`C6McU~c#m|MhkKJV~J}=5D(i_k)RHW;u>(!F@bW_29xnogYabM4>%pzUK
z)ykm!-7@IB;J@6lD6hD$XT+ySKh<NwZ>7hgoFc#E5EXr}NI%(ex%^5mXfY3^D{b*H
zg<cNnSca5GGU+H%+G5J@9RJk)B5#peq!ri2u{&MmN+-oV9d%z+oVOvJ4?#t`t_xC{
zNZ0vUeqP)!j@|dV&x`vyD!q`Y$kXUhabHKtay?YsD~?LnxsC-D_eP-NTu1Ry8RtOi
z+ajeEB)yyqDbF~hXSP8Zq;%cawe0vrbS<R&*K|mH3Ti^@I#gOj6-Y^A9V%|?na@GH
zA>EQZpXt!=Lfz-x*F}19EM&ME63=e?lMZxW$6m;TR9}(O3d&RRPsyRP;;1_7Tt}sg
zbgs05lvc=5lvnhRqP|60#Zk}5MkH4sR6MWyYC}D*w9i9@4IF}$)=f$)s7P1-;=CwN
zN7+C@g<M4)bib&F_^JG9$UsM+FGEE+%N?JAihD)*I_`ji4yhcG<j_&cI(`(IfNGFr
z(=%U$lzum)d%FIU4(Yt0B2C9Xg}SeATtxdJ>0Bgx$j^FvC4)$PLZtLUAL?^O|B^m*
zEuH8n()rCD%2V>RKZc%$bZe0qH;R9E`MQ?w{sAO8bY0ND>yXlA8`7!lzi7K%P|+Vw
z)K|XJp(3yN6ms1Jsk}m_;#kO_V<Csmedt|~SW1ouARWb9X+;?;IjZb;Ly|}BF56QX
z%h9VkRNPk`ehRt>(k;oUYuSg!Hc|I^p0aJ*Uv;Rsr}A&@qAeW?A)V@$&I|f@hjd+s
zbo?+RJ#<sIZj}CKP;p=Sxd$q)byWWqNglPisOYykN*1+`%F|K(L!#)O>{QRn4kSxK
zC$fv>+DPShlgbn266K$HO8)sf9nw{yFR56v6;$ZF`zZZ)lkRn2cgvu2wfj;s6lr@Q
zl~>3n+xp*7A%l*(J{fh7BRVhoN^va8TkcqtSKOEEs#}pRbx8)L6?8J0biXLSIBJe9
z`odz}sBDd$BAsjecn9>~AlaJcUmazW1%0zay4GotUL4iOMj`Pl($sIeN%y)*b??5;
zB|0vX<dz%-eWXLWmW;Ad^&^$1<71Fy(|JKk)0kAyrX@%^Q&|Pw2Wh-0t~DPOvMqId
z650pJK6PL7Q<0|hCm`{Zj^&exu7u8CL`o}2w<Lo|a>yT$oSHkPI#kTVnrlS5m!IXI
zf6<}EX_7<qa~;~yMMe4DN69ZL(j<p$-wMZvY*yC=b@$Vy&INuv52^hNl002vEP47+
zha`tGNPO{8vgDKQyUQ!&(Xl&y@p&ObG0aP^g%6_fvmlMDBKc?{rR!RA)sI8{9r_hW
z*YZ1bd^;o=bQJv<q@&VAl1KhyA&2y<^P+DQ%FwmOFCFC%X-pHTuU`Pk*Zo7N@T+zF
z><MV`82?`(r4@1%N0rx2g=~df()-6C<tcQf`A2#X>AWCaOE2BW#pi`xNe>074-|fy
z>aMa1Ido6gxtDhCxzf?4kkT{<YkU)_T{VQf8qz(beGro0avh}m^3|kErO8Jt`kL}7
zeLK`GlgbvUzv`%aI*PwYx)JGIzN3yR=hr%<^9Lav6^qHY*HM1ry^zj}G+h@Yn=42*
zSdhvV6>?~}({-WK#d4^AD!ZUUE{z$Ak9FMBp)Wum>QIrUvFvRfk`CSv=~$3%>0C01
zG*5^mZ=RB;6>TS7>AX0~FVp!Q&=rvGy#-QQF=t*5X+9UJ56jPx4V;LIXQdC>fow^(
zuX#iBi%8ceBh8tjBA@tZEGy{Op<=w!QRzj$(NT30>HIQC#~+1cD<a9Eqx!Or8Yh&d
zqpn3dS6V?zQ@e;HkLoD@xroPgEZV0?dnI%+RHUojZh@30()^`sjaTxcMLPedP=1wv
zc8{%UJC)x}MR}5`pdw92l_S!*WKtde10=gDNY{($sYUc9s5_}!2A#|Hit=?-c_N)_
z43m9nY}HsJQosMtkkSg$^~p#&>L&GB_057*-cs~kNPVySo_q<>QfW&6YKL^b8tUeE
z_WY~{&T8PS23D#8jei<X7vzrxH#ZjGsSEBeyl7Zw?s(eVL;vdd#p#~i^}{baT^94t
z&;7*q`Sbac;rX-Goy=YN#??J=qTJu}TArxz6Wv>T!F=#xS=LBj#AmOyotV!dhdTu|
z%A7SFl6rgMvgg=FYJ_@D4+o})hfQypP-=L<37v=TD%(ej=k0OW3CcXrd2iO^z@%4P
z7tsEj$Wl;HD|LzBJo)yr?>Wx(V(^-wYY)^Y%=uv?9d0`Hv{t%tczW0&$2HkN&vb><
zOT=oR#>X{1POJ=06jn=(zORG>4}^~A?WkQg>{M$dXZpur?2VgCvJGL$GwCJedf92b
zeV{f?8Q1hY{Eqc7A<GB{XQ-lr`*i9AB_~!@=1EmjN0o|#v?QH5&i)~N>R}V~@Nha1
zldV~c%g_A559!vL(2~7r#hkn9pl9ZWmgt%*X0|Bf+8gbn0#5bvv;>PWy>7Y-D_bi%
zy|!E=#c9=Y5wEj?EmFuyFPGHV@JSzAI>YzVB)7Q#9Ix@aYVPri(>z;J{in+FY)@LP
z=6+x_mabMa%j9pAuK1O6m$|q4<g?blTAiV>V9iFKz9)bC<*OB7+5Bg;WHv%wR`k`}
zsQl$P*#lhv-r7)7b_RyzK40x_%Ui``+NgxYDnuU}dz?+#q0Dk$^#jfm|833M*;(s;
zwst1?_dm26<)1k389tcHp|C+LcHwl)!a2>vx!?M>bV3~3z!vjJu49R(oA|`9y;76L
z_k#8Luk>DX^@RiV+LyLG)(k^^ZuoR|NAy^;_UW;^q7V0bKXq&@yuJ3NcYpG;vmSYW
z^40Zco5yzPnMKF&qU?^rGxqVYEZM_t$94@}AAX7&J}{79JbI^9?uqSrrFXyj$T=&`
zdeVH16l*tDKK0O|81$sYFP~wphp^>KTIHR!6Rc5k=Kk^FRTjToc962Ct`#n{HneuN
zM4rFZff_9@OLNct(X#heeS=!A**w`d_uTKTT7YFA_*>QgvQly5tY9b7&Z2u33xDcA
zuIbpnHU?|K=O-UqXBJ6(s+WyY<*NIIUapyUy{tPv_ltL*s+5bLYn0}0Kd?CQ)UVGD
zC#%+7KAfDUi@oIIXZ`N8ez$Wb`rQ?ElHQ|#dhMz^%MuUdtF3dpe|d>}r<inhhF?N)
zCvr)hxugI05|5l>(%+`~|Bu#kZ5$bC`3DH0Iz^*e^w?U5ifgrW;jHz5y>>P>_ancy
zNQtL$NgrP;$J=rKrivuXddq9(kN;qx-9J!K{E~k2X(s-ibh{ffpAH0ZTO|9!fl%1@
zYqtm!zOZl0PaWHR>+Q9}W4A=J{oZRn2hc509Mn7auNNP~=PV3<ram4%h3pG}?#{)9
zf4z2t<yx;=#%s3Dmah$-#?amU=-;NR)-A_N&d&<=5|x}J;Ri-zYvrn)-DPqTi(2CL
z8XMV}J6@l;lCAYj@;&#vfvB&2>k_tfib-p1g3j6DWK|8(3B11-J2u!1f+(lyy)XIr
z_tvF9yU#@Jwl;)$t=-TI;<47F<*I7g{pQZX2jBI`8ol$<V57lRf4HX0vkN6XovXDT
zs!u9Q{zB48vpI8Du3*h{O_`lsraZ_0ah0t?u(j)$XW{OZs=bqMt>Nxf7QcM<Gg+{;
zv)479Nb(JfYldns>%XtzE|az2G<DYNUcOH)ap$bpy<ppU<LLXgo`t*rdI>{0wWP+;
z4;(l{N6WKt_iCH;OrDZgTbJeYpUIB$@=~wzj+*l9Ot~thoypd}c0=r1FHfGilErJh
zaJsC!yk-vh55_i=AEYg7OJd5WnfSehq%~=LFChA}FIAp>sd81*F`3WM8JT_Ocl^;A
z`R-z$Gxw$y;M0rRK`Q}E(%f4<xn%k&CH`%@-9H$$T()Wcw$*=Duw^x{+8f{ZO=-L8
z9T(`UGS|$vUe<eGGq79lHqCuttzM9a*&4QUqx3IVKQAn6muo24_hODeP5*ky$G^8u
zH=16u)YD8v=(AY&+F{+N(;=HL=}ea;FG)Jpgx;e+zWQP3r4n_DpL^E+Jj6+a$zQ%a
zNhSuwU;CYt=2>xuGkn}xaXn6$@eB=m&e&)y7wjz7eL|yJeDh2;vNIP^K652Ii*+xy
z@Ke8LmRYlgKKn}L>ASFM$?pXs{k{7J!LzSaJ}_|hmC99*Kxf_C)vD~Q#=c)P*7sEZ
z8M&gerYPL^0_<9?0W6(=E#m=g30%6AQ%PORF5Y*?1!ty_bpV`YG3qr#!O!R&CZ}Q^
zOFeTI>^`HNZkp^g<y-RczK1@t?(F-NYxh3onLb!9)$>mwZ7t`Q)0;(Q)m=2#4!f>S
z^YqNA<)Vt56>O10PI|e98vB8oC{L=`6=gWRF21OUHEc@fj2*7e+;E_B#}A*|aF_o2
zz+RUh##z$sPEPTWqyOvci<<v5F4xj>WYTN3eCE9C*U!ud>vY!cU(!x!3?o>=i`9=Q
zy#%UWW!AYL_E!1COWomR<$(DPvj##gUF3^n=k<T(jgK{-OYii*^7_Y`x2C(B|B`PL
zeEriS_Ui;+|MboJKEa*IUi*cD{ZGG7KcLh9^j7<gf)mg4OF8;RK^>n<kNWnfb8b!d
z<=-jzcaI4_r=#Bkx_jvQyf$3l(0;|5b+r|LU#vE!b&>rI;jZiabZ*=K6R+6|GpF#&
zI>)72{M{$d?9*>6tdLIj)f*rBk9`05$SG8Gu~d?0?)v|=La`QP3rhUJF~1n>=N`X)
zJJ?=3&V^TSuFktU^6XGl@ROwZ?-9?v_s3Vqh}^kM_A!L&x^ld^PyOkt*)4dW`&W{m
zdGBfcPGh%Vj`MGiEGTCs7s2spt6MBoH}}X#EQ74!W~*w84$HVCwdG9X5{>LTa~mE%
z-6_`B#3JHw!zb4lR+3~%o_wmG2>rxQ(jSt9KhdfgQD18)KDOhDf|{tr50L-EA6_jt
z#K|?MPt_Pz<|iC(d3>EitJu10j$8#<OO8u%B6eyL+cKm+^RbfCYkB3LE8wZek<ChG
z1q_ms?;&s}<-Qqywi5Yz-NeaO%(YW+het<BCB~&Y-pVh(udcowZVL{%V&}f|4aOM6
zOOOxqS&fMoCg}M-_UQYnI6n;^l+@-We{TEbftzF*l^64sHj$o%McyQqS5iwbA3hTb
z;6%NMwwn8sFU4-dM|3B%e+#O&>_wr{poFiFxL6oJbl?5=PyW=&ZZu=Ax8HXXejl^7
z;D<9;6$?yP-h9EKY`WsKW-6IeEnz5LC43b>fB5QJ&&CHTj(_#~ZS6|6wBPr#pcEYa
znY$e4Mnn73!ecj^WoxnMMzus4)QA$C>5Au6XEe=|#t5c{CjFr|tb=nV?))W-7%Y3q
zll*x(uWHR|O#JB2d6DqH{7X)HqY+Ch_p-be->8;i<jkdXJjpJ`Nhu%|lOkpAuiwL9
zG={ayL>E7QqU+o^Y3vSLX`b?^O11RxYg|W$lR0qCR?fCt$5yBIBd-M`08&5kh4Um-
z;*5=`1y@LFz2pC3%D7Z$BUg~8#=WI>UWSIL13%3Pcm0;DqaV;z*UD2#nE$~}b!D_L
z|67~Wm2ECut4)`B@K-H0l36Td{}9dUcw*%1nfw0z%Q94Rs>OJR#3U~~F7;K*h`zB0
zLAJSkDE%X!B<i3Z6?*STGDNw{%Dj^5h3I2rM%SVW^yr<5I`c!n^UAZq$MIO|ObI?{
z{gV>$bnG%ys{gFK56RT&;^NNP0-D?KuVJLFvl@4r4hM->K2siNITu~83z_n2C}3J!
zBLCc9{z^W$F;m)}yhNUtBr*D`%ln@16-@J5=bv*|KCeM&m2|wGnifS$5&z%#O{X#9
z=0osG=ka`M^<pM&96@oDm!PBdzDRlMD=KAmV%plm$a0aJVB6gKV5H5x`vZKgR6?>Y
zAh^OWuX{(2-x*nuV<i_wdvuv$N3nCi`p%Uwcu5{+M5RfvT&z6D+)w;786j~ARbFur
z+i6k{P8~_HATFfB81MhD&kdNm#16JAZyO%%u<MAQN1-sj?-T3P^Kb!I&M%gGp{DJs
zuNqp`t_sZkv#;2|T`jG-YGs6su{;16*%lFVYd(IQkUn=8sn&K@G3tn!NNjT|)G+sR
zi5+qDxpF;r*ugYrxUkiiCe_Pnp?BS9-HW2Al^p4M)_LG)>#ApR5%u}-*M4ZV2$W<(
zl$fV;K6a4IwGfmZ`tIN3zUsU3b`d+vDrZut6dqK2Zt|A{W&?i&Gsj&Zpdft(6x0}a
z^iO|$B-W&OP{B!}(A1Wy?*7DoB|_`OCz5<6WJ6mGzXU(}?<g*@3c+$Ip@ddwHs^*P
z=l6{=8=myqU}YuDc~-XW__&tp2Ql2B?ihvh-+oRy4z`<C$vF`AP26Ohfg$;XSG)Lf
zs|r)%N3zm3lazQ!o~XS2-r7)7o~|fN8NfZYVT#k+CW>*qhu**5h7vfridN*FuaImD
z%eD0>f}>1R-oE@&b@;hY9>#Jq;SVbxEwG>I3N64V{0mpQWA+Ztt&-5;4R3x0rZnbu
zBwn%D>O#5I<C-IE?x52=cEpt9?)A-m?zP7Sr@dE3K}n9djUqZ9Op$hUQg7w%lUvTy
zAVR>l3U#P#86;}9L6y{kqH{guzW>7?InT}+HXIxy6j~{%{<huhNUA7;1ne|_Ud`~M
zZ(<BhoQVoC)~Pu6c=5DVzZ(;4@~<(o*)}Ow==g`QzWCWhc60HMtk+0DyUYhTD+w0L
zig$Q!J{UpWRic#pZ7mds*g$AUf>F)=Zk0fV##CLBzKF9`Mk;abaE7dYQJY$+Z;(rG
z|4=~Hkb#SgI`lp9tKWCw%Kv*Bt2Rr7D_8yZ(rRZaYm?nBL~f*fHjcjcee)NmeZumq
z;#naIr$h`|)-z_Jm(AnZ9Q~K}r`=cOhjbN9r_lJppSVFc>|!SvlTcTllbv>+v<D4-
zIR&La9N&){B22H7y8K~L4dlk;)H$)7gVJZ|mTN@$mW<Vh0J#SuA#9cH$l@>rKiPLW
zOW1M&3a>`I@0(qx!)gf@-CR14KT|oa{e2pO#Hmx?-}vlmr6T{lWdudT=1ji&wzY22
zQxI;cN7j0)#8PFPQrcO;R;#wP*O+=jUxXZ|g-2rf3z6BQ+rLkK6#0ZLwD!$$!s1qb
z^V9_EjEakkx$k|aHRdj0mrqp-l2&ptKjtpTJoljeY7;HxojNg!+j)jS?9Crj2rsgc
z<RYGEXBh?IZ{d67bBhAk9I%10;{-?F@lLrRR>Y;(1D9bcKe^-65VbSyz)!(}q`Kka
zb8<mf<K1|1qQIJ%2tJk}3zoL(Fy;E;a6N*qlJcs;1qN2y<8!w6Q>XSjJ%v7wbE4+X
zRrkmUsqbn;l#7Yp#L05CLUv@GYwosd)2my)gW++xXm`u8!+Wm!(~U?Fey=Zla-{@6
zT&CP->R^2^v;YVne&18Sc%F?eSIVzDUtVD=pVNU<y(>Od7Th2Vbye=WxE!xLT7-E(
z8Xe~bejPjSgsbX`wq-0bZe_NZozCK;|Na;AT7Zh=CoB4tG%qFJdFU(Wt||_IN2j8>
z&eUB9Q}V{v=UjT3-9-4(!cLT;)|ApLOsorOG)NLLM)bzf%V&AKG2*jvV8z%rPw?zK
zaUOH2!Gixm>8{tlEM;E{|FQ(LoX>ZX6G=+U9s?TMR`w9n;)xbfj1>_DJ1buuI2UO#
zc6KSif5kgzcp9OR5B?gCfE4Lg9-AqWT1~~!83Z#r_g#OE$uQFSzmtev+_udn2uR?$
z;7<PXOF>P=-=@m*Pap}K9<o;HMgyL>H*y+b51!Db?2v{UteNK>iwm9%XsmAL8S0VP
z1!ZAGY@>)A4>a+z?N0E>J)n&xCt)cXfOlXEV-H&$P#J)tg}MsaPk0nyXe&T23nt1g
zExcvpUT~eH^vs3l2|Sa|R$)Z~xGWFa8-_GcBE~dT2k5%NKPPatJp-9xzhWd2CV2y>
zVwM**P(2)N9>7!^rMuoJxDSqF5_#p?fFCTZv^i^?TGo8TH0|6M*{=s*08o{_VzOc?
zw*@+LsqL7cIeBjKMa#6|Hdek_C1)nsx1hWXD?F-x_{kp<Nb4N(SvwhFugoHUn#!!e
zOSh&+19roMjAX!Vp7YD^)YvSo^hKO4bk|qHJ}w2=Zlb>AG-hgy556!xM?EEO!h7zE
z|J81CP#rR1ho@2rnRoxZpvWsh0YO!&>d`p*=6|@O`IlE;IB>ad_f`*F`X0O0`W>Tt
zvpb^4nmb4Lj@=b~xWAvR)?*=Ctv{w8ZRc<`hi4BTyPHStrew<^-&#Fz>9KsT_1{4z
zL)Y6K<G_cP`>M^*^)F<99IVdX9rgBr5nlhW1(62+++H-}^?ht@<2fVd9iPFTp7ev+
zNS#`6nkMJmS<qBUf)iJs-6d}`5l`%Hg=GC{J)e`#G;@l7T)N>OpPTb5Zm;BMnaQuw
zNr26YD8`;W|3|OTrTSrqj_>&{Qi@|-NX4ofQmN)J6jK@qAv@!}<Gh8@C}DE9OuMT-
zT(DZ^Xgyg~)w1nmimClWuX`n9P{)Vu2-|EbL!+mYZK*?0qmuMq>(#+0R&>F!m{o$K
z7v9@hv`>nq$DHLN#1!V;DH>=jQ~6F}NaM$9buMik=Kk^*q|?MUKX)C+3Tw}n`;c5b
z-*Gv`7%jjvCx7k_zkHlqCy_(9dh=8YohR$X<pR#9sR(H9feSlHYz*z3oveKj(K0Kf
z(zOy|<P4p;U%o|6(-`TR<4?vhe_qAIM$KgFor}onRgb<h$W61;=*qbgqNO#%z{q~c
zp6rR=H}}UoQ5wzN+b!oxc+Tgs`qQkSo(Vm1xs0$-;(WFhomgJ;Il1!vyFSNUdkXwI
zsw-4zTMB+xeABXn<0^G%dre2QJQlR8>vR9+4QgbqZ7*Sco%|<0sG32?wmoO=rw7%@
ztJ7am+4+Jr8ev1UO5^CA{W-T)Noa>gMhrVH77MqX&f@rUf4L7KHA*lH%?GK?`Qn#7
z(cnmR5e@N(AT)`wSpii-#2N_&zUt_&{)u+du)BgbdTEzlj=8lzyR~0su*u6#m3F|R
z0*aJ8@AqGfVJr8i^LL!t@<Tm&a09hF0A@1L-0NiAw1La~XXW{KVETkBhkPd^xL6`u
zxn^Lc;ff+0FUPqwnpSF`s<3T!VCZ4*S1XRE9o&ebXoZNvyYHxeB{|<iP`Kv}bwlUI
zVSO%3Y6wX4tbAY9kw1IjmKPko{?&HxH#=Mwx#%ZmEaw?kv6>s!Dn+3HOaF4H_31lT
z+<smlms&B4VgT~Y(=}H3`OAeTVj-X3dgwF>SK@~vY{*4pH%m{v77mu{0=|xOa?X~$
zOkEOFP$KzJc8q<N=KTLj8nkM4<l@35j|*)n`mo#B_g%LxOJww2(bcdm=frv@i`c=3
z=E_F_$tz9Rryu??%NK*Z(R2qLcKEw-n1@ypwp5?B49V?vm{5o|CC~zNQO|kthI2KG
z<m|AO)h|}?Xv0;&NhKOdiaqWhBJGe`Pyc`9b%D^430{Rc#qHU)1X*KOm8n8tcV`Es
zzHgLYx;gvJA3BXUL%-SlKODBaZ9agy<U|3~J$Gze7=`^(CklH_9)-QeMq%?|%O&$+
z%l3ZFOmb$eZ5{u}E%o^IOU`o3%#$(BfHuHt8b=Rw-{^X(p$w~}xnF-nY)26+a;3yH
zsqtKNToU>2a*_PXU4I2DHc`NK<xz{B+;X1BKXdML_sUto!CXSb<-e`mYU?;F&TNWY
z<A=V{<2Y$(BB$P|bWn~KWL<dC+oONO_}@(`W-qSo33`IQjL&9+gdwN5uhuhCX_T7I
zufMzzRdx=&X2iLmHgs#YZGGRX!=4-b!;!P`wOL<l@+N1S?_N>KuJ6gb?U!dK%lDZF
zoXo47Am0!$LgHOfIi4}D)P|nR4&T!_91hK8m5K8Hp{qv@M7&wC&5s`OY{qAXo=$t7
zzvh+o-}P^*?CQxzU%3CK@U7{!rup{1SJwxQ9B4c}Jay}?pO2C+r^9_m?&(M5&twzf
zP*i!A_dNdL^_TlU9)8A8`hI5XaQc=5hoU{{#=ha?(KP#(Z-%p{ye~eGRh!B@;y$(E
zl3NF^bv@;se9M6-YfT|g={2|2D@U^6OWs#T2BT_eQ|<DJ(aru-8y@g>UvjNG+4s&j
zzk16Jelp}McQQG2quKV;NoC__$0ov0`F)25el+o}+Fbah3tQ||u8K9hgopKio-{Hq
zOEOVwSbW$npe`Ec9r2mSZu!ffmGP?AbYj5VmTkr**uxCmSgu5=VAd$xv$^Y!S@FaM
z9z07H2#LAOna4^YVF5`{q2CCh|BNR}Kpv~XxsShYLGA??i&=GUQXAa++{?AD;=Dg@
zGt7<fO7?QJM4dZX6?0ixxu%4!_rCXCq92Y~jyif>eB0{6esE{O4xX?6uT`)As{I1=
zCi(DRyUX(Ce!fz)ZFl;K&c(`#Ccc)qB2mynP<rOKdjbYg>&>rx997fe26Xs!q!h-4
z%wD5(%bh*NtyLV6$w~?vvDT%kuXcLkJ@TQK!Vs2kVlfaO5vMZB;@p{g^!M@$^^~MI
zwa2{6EJ&KaAS{BD492q5K}?nS%zJvoioc9kkvfQyGMt3O?>JfZl9nQZ(tYDBz0J4H
z@mzMTXc<c+7ww=B^Em0eXdK_U_;=T(_TIvJAJ2Y*vsls!`>`iBW8V`mur*i)WS2#)
z4Rtlj{BZG7u5li~awD)xpm%e`nYaA^8XQ*094l|E>2X}ZVENiJ#S=`52i(Mvjr$a2
z$0B0dfb+Q4Jo@eb-VwSJ%fi0H(;7h5RfPow!#GG_C*MTeX)z5>@>Lj77@KwKJNFH*
zGfq|nvO4LEl@wwZRF>CECuGgtZJC!i>yI8+#I%*WE?X~6dl}K}FGWKKB36IuEWVAo
z`RbcqNVaXRbu{jscwvsWj+x#SQtheW=?kB*D{xgd^k3u=){d1NHuOhi7^^j12Dp9M
zIhqLwwAc);*p_+~!EJF|6onOPB>GXXF7;uQim>u%j(CMz7#Heeq3EBy5siUjpgQCS
z$>=UXth-7qSRX%j*0$6_3rZkCDy6J_kN&;Da_PL|i~$q^=kHN-Rn+7--{MSfz`{h9
zic$g_H!7^NX;gqM;&UJTi_U<Bb`~#ob!@F*x8T?b#w~LVVVxkdD2ggv{4<(PC7o5x
zf~V(eu`o5i>WH1&F0!g94wy0jv97sWo>WFS^A2_AwFf0Y%j+V)Z`o*4$i+nk@OIRs
zwmpGy@4J>&KbN8!F6&#Uw|g0F472MB{^ny#1nZ8C=?0dCG~AfkESZbFcPyh(*xcA3
zl0kdqdnttm=q^OVR?^MRx-&|hkF*2rz*oCj<Xy=yRS|@vj<W+RajyE4^LD8sr@YIb
z$XPvE%YL1rRgDajDsHGL{^Ga4-<Im$rgcXxvvFb<4d3uslSRWK=KZA;t~}1iyvLX7
zF1j{Ah4Vy{h}1+PHRG~`-t%F#JICB_{6Y8SOU~6vR!no=HL(O*EJl~B`4V1%=Bd0h
za>(6hS%{^+-lO~8)H$E8q^^lhmzQk*aoL(hMGF>`GxxIxErV_?9>2ZxSqC33Zo<DP
zytg!W<l9BMj-3XXpIN)_73cX-6eNkQrWLWMu(Djy)JV5jha`1cd5JrYCKgG_Si$%J
zV=g*x>53&C_+GtpIREJUSX`VGN1HkSfStJVU+?Z=Is(Q4cbUM{VmZy-@cW$Pl6B;h
zaysm!ra;>2EyXq(>O93kbG!9(xf=+9;SaK(-rOI&h4Xo7=Wpo5>ORghFXAb#+|h{a
z@Y#_vP+o6t_+tC?!jA<-EWA}**~jfgqh?FB=P$l?{w>p_$hq*ysC_(pe(N}^u1eTj
z(UY&{{Yp!#*@P2Y=&FmYIM`AA`J0a~9j~C0wq#TWE4jKIqHlK28l^9c6{)K^D$G`s
zz?1R4>&c71L&%x$dz|kwUALD#?KsTbXNsL~Vr9STzr2jzXSKKTuPd83WLs%iS|U}7
zn0xXs^Xsl|T_l|7hz6}>syohdq60dB?)WVm)7jo3fO=Kb5pF)H!@aovh&ZgceU%wO
zY@=|BkXA$`Tk88a{W^9UWQidm&$jfZSj9FDp@<IM_n2PgVKJA{mIbw9SSW5Udt}qG
z$Of};!w!8$Gpk6R;a$L6sxOBbn-1U%fVpxFhzpX!RA)p@F*{fYZZvd=p85h~ij85=
z>xu==gB2UEFg$XUBiMN}*|K$<%2hWLzKpp+g<XAir(a{sh#a-mzlofGVG>IooBW3S
zKisuyrS@D!?;_8?-Q2D?x=q~jpWZv~$tEi`mfWFb%$Iv_SA=ZHk~b_xs%}*AzVCLu
zss-~EkT}B@ZOeO>o?<nK^_q_}{`k-0=XU}K_^zydE$fcVmVMA!cCrgn6aq~1<mdSk
zy&~vYAz!QD4lB9F`HGgUD|N7cbDtkB>W;Ylt%%fimN>DpT1DhZx4gH<3MyVye`OjV
zuj<+v)wBp{Ppyb{F^g}Ddf(?7TGWe63IOOiy;B(B>Rt=Zhlrem_Ga!M!XvO>okVkb
z7g1`p^sWz-B{T2c+c=}K`ci^Yuv4|CJ9&+nntaz{4bDbHp7Rr5Wx)6KB}oKKL#)Rw
z4t#9UCt3XK-UG?EFl7ukhcoJ?7m`bjqmO*&`z<6nt$mD3ge2J?(@3i#HD#ckgUpR~
zuC$J&y(swf-EzAy=~ej##j`IxKK~hBVNmkQ`C$RfkNKR-G-(}6btj$jKUn8g?)%m&
z3x2ZGl@eVtpjY4zSx=23Iy1X7_vB+830K_R^=zk?>lCRicTMd4ua>=se||pFk&vCC
zK_0pskZ!q6Q2`PWj+}l7c$kzDo{BYX6@tdhk?#u6(Ym1owS}%gw*ivayeesv@uxU+
zs-8M=xz6|ReS$*rx1M~tAJn2l$h1u3#V+oFg(fwh!*SHq)>BM}vlFM{eBa0I%S9S0
zVAZS2APhxxk>s1Fpp>fgyxmd4CiulD#S7NsImlrU#qHYMpZrB$R{rH#l>8D(7Nq!r
zzT{2M%r^#H1rj*{igkcrYIEPrzlZjC4%SuYxh!KHHl!jGw<Sd&3+_}hcISS3+x+uE
zX-N*p3z*Nzi5%F}I-Q<4+xa!Wf9L{^cy&nrlK0<IhbhK2{E>%4YA;BHj_X<SX)v&<
zoLiNo{@mMNLv1Z%XB2lT&OHR(KTejFy)2qBa6J-Zy(OZa#iiq!`3+doxfAxy{nl@C
zR8<nIrM&HQPn05DihQVoLl6}g2pzdra76a7|1?-HhIv-y)zc5v%0m+a_l$5lfyfQo
zxw`?$ZS&<yv8R-0BKyw`jCiC|X_bU_k_HbZ%7W^QlN!HsyPcXeFvp&>D}cR&l0ik-
z%5k)0P=1<{5v4mZ++2M`I@k)4jKGGGSI0Cyn56M~0~3`*Pvm8OD`M(|H~gH!$lO|J
zj}=jD8xlRiMW4BZGA^!ul}VLw0AAT9AKQtKchsCYavUcqJtq@bu#}Ecwzcg<F4S91
zjd|Cv3C<lNZ<g56I=88LP8eg(%8HRQ&1)|ukZm$>`HO6$kVJ0VrZ$h0dVh1XGZefG
zlkqcNRzPS>Yo2*`*X&B<6ic)Tag>xMZ5tH^7K{HlcJ#3qgQ({wR?t{OJL2z1T04{0
zW+KQ1=#68FE~FN;9ZFrx{;3HOJ0;6{XWIA2>8<I#X=}!xPP{2V8-FtO(#a`ryw+yu
zamJG<nyRD$CQ&<f$G>o{b+7dY{Ul5Jqs@NeO;G;Mgdw%NCdQb+V4r-VJC!Sekjlui
z^pBL3TDD5Qp#anN&18@~=*R99i&6AK*&LHeWP9bTpZX?v{AbH%WGEXg;lla-o&UvX
z&?%jEnE#_-8TL#6K=|VsY<T8CI_*_A@`S!E7B|?WzW!GewSDpA`9}{NnXY6*wBRAX
z6FEKNU+q?(t?A7xeC34^*@dP)l7z+`7#g1%nl|IEZpUsie#AKAt{1o5{fTn4O(XoM
z+1O(oZHBDQv`nu#Vx~8bM^S0KZM1bnnGSiMH&a9C5jN3`G4)3W%UM+2&~pFkamU%K
zuL&AcP{#?M^AUp8$2cmNvC&DLSS=x=HZ%i*<e%iP)*_81^!3vCMutEKk-c%!$Q#dG
zVCv~iB@IJAt-tUKyPc6C%u-*z%P6l10n<KC<3^nHAT&)WZ3?4!C*Z_deX0UWeEO+s
z>c+Y;U6E~Q#IjN1xa;3ri^AEd>F|yZzoI%ba{bTyM5mhH<=P)FPG_-8IXtOzs!6@L
zCIuPB(K@wMiAkG-NrRMXk#)Kv$uO>I-6a&+kdB+#&69m|uRH2oKk#;Am0C^MoT>nY
z@6YY7CG06FRY8sl)CDD@Le9rk0H54JC^KF2tr}1hrqCw9$|ahnA<N^&lqa44^cN`A
zM%-S4G^l5RPALc#=Ed+ZkLNXv4K=ry9Wm%nB~Ak#r*_ra4E5zdET=CRZ->(dOc-x$
zhj;attEHz5^&;4B+4Z1BDy1^gDm76<syckA1yvk{o4kGj%8_=-Fdm_w*o}=TF(sg|
z#N9f3U^=Ycf5CM4);BavkC$mFD5xy?=2=WC7JAu;YO22CWU6$WxQ^MClo?$K2F<wP
z%bnuLtsa&>BKbrtQz6;o=>Vg|p)8*HpyOZUPlsW3ef`Uy`yr;(gztcM7_0gQ9X!-x
z70k|0`Q!EtGGyLHO%EZuLvtwzq)9jS#IC*^%jcarr^=4bTFdp>+F6VEQn!s+QgiiG
z8b+BDnKZiZ^F8UvP_L_()7WKtD{~d$r=}J0Zt$OGjc@ZKst`Y(_E27?`sP*Tdze&J
z3P%g7jBZVkQ}qPD8su?3l<Ox7Cn6J;8%O`q51$P-yWYH8GT7AC9gPkvCKg6Cn-LrE
z7Z7$5c=9mDMBifSuz!7be1Rs+w`{G9^MYQs;DYC$|4-|VST=MN2;*Ex%!YIeJA~S!
z?sAf9IJ6&rh_rgaSua*QhmyD~b5mccJo)E6BgeTdE*WdfSsUf?;FeP=A?!y`Vx-K+
z-3C0xwvWvJ{Fn2L*t_El<mbibyo^e)j5{aA4T&3QBgm+9o5tllTWntV``>aJM*4OF
zVy}R+q!E^!i{LWMxs4yhlpQN24`Fddop{og5rj?r3V%On@FV_^8<Z38-g3V?okUxs
zsA-aoH5G%B&`p#^@oW+WL&tvhb|*M6(r}$&p`T1{L^~?h3D%9e9Pk$f7!!oWq$25{
z!Y-@<{csfqrDUQUANI$IczfL%1CEpVeCdB;wHY}<7$u;duP;6IQMQ`5uo`MXL5HY)
za>#F_C1)zA+-7Uga1GO3>{cU1sA*6R%!U%h1vQlxc#%8n`=gb|{c`Ito@MAcpKxb(
zBtg0!H*8|_)F={qI9(-Y(9~zDQ5@E8J>PlaljqpL!oEF@aNcMsWBRfy4Fo+YQ>#}0
znr?42q~RuB5AaFV1~y?!VKmN6Um7$q+S?yZ`iN{wkw4g~ZD^GO!${}x{0xu`<85eW
zY8%R$XB~esGQViU4s@$c$l&fN7&F^(EGgWA!b~a-Ft9L>v%{EvW~0V9M9FlBI7w$}
z<gnIYJ%H5j56ejqm1Q|!y<olG-O9hjUEU*H+1SI!j>H~eM<GhVUh;TZEvFvD!IMq)
zY9Iajgy0`VW0=Z^Jbu+B9(3m}`}fK+Y)w+^0~v;%vjaQz6MqV5Af!{{|D?4InF2ZD
zQb?2Ir4U9_1hbm&MP%ZCMBR@4$Uk#NRAqW_nxsUaQ4Ne@y^LTJUQx+U$4d#{vcQbU
zPy|y<pT{BNw4Hc^s|h;w8j-svNw#DY3{h==6Fzi*G%_+0xvj&4xYQH18J`kU6C#3{
zPUCa%wr@H1ifMl+XD0hLoc2acycA-~h$R;klp^D7Rl05vh-6NvF^0NZbJl}S7UA(@
zzdXrPrf=>|#~jOiznNCW4IWC29rPNCm{@No_@Kn2%(T*r4JGsOA{8I8Iu!N0)i#aV
z8%4?0rcBTfmFgSAS~)I9aVrhebUcMKcaFXO`M5`=XLKDOM-087%3fSj*Po_c@&1@n
zYepWg3q~QQcsi0A(<r5m+MyNOxXTNX3Vek1!N|=}6dtf@h~2~hJ>`qHoih>-<gI|D
z(-<1A1lBf{@eqR3yJ!-9s5erCXHRSlN8hJV45K#+vAYNbDoCVk6OEg?t73SDeerW&
z+bi`pNQ&u%q|zS!uGZJ_P?Rifb+i|_Moi2skK)n<f3A9_yKXaS=4D>*ZRu$3c4B;!
zrD-EV4~c$!N39!|{QzyE&$+8FiAzBbY4k~vCoNF~yL!AVLq{S;Bgzr!4w(Y2>THTq
z#v}LzB`0CX<Rm56beby;(V}0noXH!nCsWlb24SrUIMpbsfjSUDC_JQmBOeIunOQtp
zwIxmA5UWZRW#ZA9jR@45i4K`8prF8%$HQ_w8%f6)sCRkt&|B9zaSwenZY8*;Esd*I
z@|ZT2vS@$Rlv8W^vZ#<0bxjkb<!s`}ltTER9AX*p!Tt4}(LtX{q!yKFud;&MI*NC`
z@cY37eM8kAhTu5aI5m}~RaImoWv-v}`2vtBGdVd<*jY8Ljgg_IHG<!9#!W^_f4pYY
z1?ZgZjkHnV&Q5PMRqWcB#3T><=A4OiFd98D==o7=+$C}JQ)YChX_=ART6Yg7`=>^y
z%+_{PH{p1c*6V3Ho2GSOq1kp?Utb?N`uY}<w_Zl`#I>mQL84p%Mka__>-&B5J$~3s
zNs3mDxE&SOO6bbE6S<z~cQR}Krf2H6C415=ZMD;E>k(7EmAP(oOMCqO8Q)y)C;d|<
zOFnEan3@`ON29}2t-85?G@3QDaTKQE{b^W_W>e49&3Jn3;}fwNkWtvU+iOLpmURAa
zH}O&5r2G9UF7Uo2a>tOeh|ob1$Vf}!c!&I#aFNRyVL~`GWm0gF$m~p#X|I3KL@m^Q
z$lsHsd=bk=vvbtmYoV=L(vHHI|BhuNR{X!<xufTLZ&lbi<?~h0K2i38@Ks+jUjt{W
z41B(A6!niskKEHdl6iYBAilbrIOqdWRB3}=Txh~q&1{}F{=nzW<Gk#crVs0jpl3cf
z?j}>a+-ZM2+A!;zda^m0<vVhXd8+;FM7w_3P5Y8B8CvVkiJQ&knZKv9&$L7D-f!@^
zFFi`*w8LaKG34gm>BXi!eo<v_G}b=2^=q}-M-N_hYtXK5z4D%Ch7Mjy@CQZ^ex2vG
zh8x=(p7`>4elT!YZ_qj3E@Cj=xU5kTfES{`1TFh%Z~MTwTa~_V#Nr5BD{&iJCk`fx
zrBf?To+JlBWf+dTTRg(bX%lYUP-)L@xzWsSsctvnQ>N+q)tXzqiP-V-Xw0<FZ#`<-
z=0>yI96T60{GT=lO<I}`?_Ce@vc8@^>py717hhfWukT^`%n^_=!RU6kVMs`;3E?XN
zIB3J34}#WQV1j4OgP<gcriI{?czRmdD6&>!ny$}YIXR6`>mvfPYB*z%f4W`W>`xF6
zzu@~>6tPAeJ?tN)`)$3yGVbn;?)Jysed(+*Tkjk^25NPfmI>jFumKwM<Js`u7RP%N
zw|+lO_uPkG=A}b>{ZYQq$C>l}#JtOYTzyx8Fpdx-QT0I+&rC6{5ikdUGLmtol1Kmk
zz3c0<!cu0#saVAh(yk~sI2cZBra|6jTJ3h^MCfyZ0za76!$+r*b~qMMg<tpIM%K|8
zb8z<jX#)!<t!^kyUpcO(E~nEQyj{r)Z@P*Shxg{qy_X4SUs5qNv@t%@3$E>*^do}!
z_^6q3#v;v)LP$yh7+8%$a4lp(vmsp+bRtT@Fa*>@2gBXTUUP8V8$`}``|h;2mxjW|
zBGd>JFc(F;+9ukwIWxJ+x30rvVK%;XT`()er9Qg>L)tLz)?c{d!_$=!MqUOQHPei3
zcEXJD$dr=!OAO0kC=?)j1jiAukm3rd!7YkH9mD!8dMuA)l2mNgBVV;<&e`klMQ~t%
z@#>dM3Eax5kG9PmdUl<biEd3>k$aIp+79dG>AEHjIRS%Aq1f{sRd;&$`fuW5t98Ax
zDMZ_Dl5vZ)q^YO3m1izs<^>x`<V(;1MDFwz8KI!0d$Glt17`ZldlNHDPpQssw$&Rq
z2d_j&(;N0<d0$JKX7+qPi>dnbmHW&_xBhO7x;|UOd)-Heqj6Kvp(vzr(Z685d#S^d
zPlKfFPFOGB>yNqq*b&oLeH(V-Je)Fy9?F=WcHm+&p)h8HG%#8^=CTpATxEqC6L2m9
zb_?$X1*(_Q`u*qc@FRM7xtdH3)wx}tJ%3MSZ^j{Z4;gyWXhhCYmjrWn5&?@w<%iQt
z%T9IlFr5<QloxBMF#o^$SkFXhB;#wno9+(bEg7>Vcne#FCxQfzEC~`VvI)sxK;1Y{
zicNAjBat5GRA>DlT^Ee<o#AOI^8EeJ)ss>?%(iKcEyv92;6p-*;xH_2ytK^Rno^_D
zQs_^VrZ-GEw>(|iWqLG~G9~OvLOY2(o@SaP*pzJNkc&W+O1RLPMU=&rZfHh};&c!d
zdpiedq9HSNYh%hd+1||QXFw6`#1!&OT8Yf9=?;HzzZsv!ufA+Vv&W%KGe__#W)Pgo
zj~xEHh|AP(w_j#tU!#57Pv)=DUVU-a`N7zKwB!%QerwnDAL`>*XTNo#U!7gztH&QY
zOvmY_&f6<s``xKaoXd)=+q&T174Iva!vt1NL0Kj<y!e5+*WN&!;=4_}SOJLmwAv_$
zV~3xJ8JSqFLCI+lqA?j^<_V5IrZuUMQWD0WBAg;V24Jn>1pB*gOYjUQ@C2QPVL3RC
zfG?OVLMN=d?Rb6f(W~ELLxL%uQ?!m)bRhr|d8WGPcU7YNbx4qn4Ux(*y$h0m+89_z
z5Nuc(A;@<^FCjNdj@^)IS|@exSFU%Mr0iEk7*?o}ltSY5ps21h1y6~fK7odbe!}FO
z=^CkV86Tb+?MF5OZGF{B++_7<M-qEln;S$b;_fQ%?vkNA?Xf)gRQvDw{xH{i#Pe7|
zXIWNgY^!N%n<GJ0t%}<uT5^I>H$&09UF(G`KgG4QHR(s`L|AL5`YsBAstzGa7}VO)
zr6?#WO*+mNKQ1RUO$)EG%rGB0TcTj57MFwa+&}-SjhVFGnKXQ+6m2Z3bI4eRWr&1j
zzdJ6)@#YkB3#;}%>mU3$p@QE;d-6tWNqO)YfQP7BCLawFyIz?2o7m%^+cTb@O!JK#
zNj2QKGa2k{N3+vu(2jiP9p?#x^B9X&an`G7#a3;mwj&vBQbtfA08q^pk`ivP+tH7R
zDQijid+=jz?NYNjV#LD%@5iMYE&KgbgM(o`Av#IS?Mb5g`@N=_CNt=@c?8k3X&yxG
zS~7Zm6ecsovjk)Jz1F?Si#PkNO5gC)BZvK~ccQMHhp|MzzfA~30Fn_Mo1m7F33ce(
z1+j@%!XQ3Hl$kc#HAcY1r#V7rg6!VwT^xLm5xZV%9cafx(Y?`VEltZwKUjmAit6h_
zpE_^xBHF1|yT67bRzq=NXzI0cIN1u1ec<zeE{HOG<A_f*o9t*Za*x*5d#w0@2aVIZ
zskVSp8k%>UDU5F?^BN7|O_Z%kTT}uVWfKS<1G<o+s7}aF^cND0hTu5ZJ*)POcIrf4
zd$j!Gzb@ZAoDfXYCB;<TR>qGgV%AHip(_RaN=CG?r0|uNte5CHbQ7oLfx`G8d0|Q4
zaS@ck_w0bR$)B#_xdKYmW{^FoVT*$)rKeAfuEz%bW|ldharXOJmY`VM11NKZb6`EY
zt;GI*sX7+Gh>|f$fTEU5`?2U*s$$%BqXxrHf=M;qcpZ-p3dXb;)!g}y!~@M9q;vvP
zbJNkL4JB(bH8)LSlDK8@2<)7&ujM-YM0qglI|nyMP9tiA0FFkG>kuA92W5M)3;KW-
z#zTXD$Md0PamTq7n57(rAyIvJ#p5qmp?uL~#L^CZ8-#_e005g-qf{3A=NbiSW}c?6
zI`QGhv9h?t7?{?QjT;iUg0Pk7B3hxJU`r0+#&~Hk0FwyS@hG}c+V}L!oAI!l4C{Kb
zH*zQ3UF~E_{28yP&n{370^9YBi9&6N77)hO!i*Ewwh(weleWshn{C!j0)t!Ogu6^y
zW6JhfgsbDcrIGQ>4g%8<|Jz9hBZJ@JpoH~zO};WNsl~it;~-#4Y$~o{WKDaCZy#h6
zL=Z(A84(eLh}VtR2kWKr@mjbp2+wH%17%2IfUP2i`%6u<ZVR$e>#$~q+z8MX^Erp%
z_lVi5Mf2F;cc%F3Y5eW~_>)+renW^22a#HmO7X#2;O=q(b`&~O#l&|pXwXWmIVeTi
z$>jta!VOqUGKu5Q*a<2#T?-KbY(r{voVqCoql}(unQlMrVP?)V|NZ504<?ANZ5A*W
zwM~MiX*KmIU;P17lQpQxK%&qWGBK0J>kMN*1E>0GTwBK=7~}RO>oFz%g0cZt<20Ob
zpZJ>}0@9->nj0i42gwk_@}+^vb;u;~1#Zi2txxD{CJ9GrB{YGzufox#v7%ty5eRtX
z2=k*VRybJ!d9HfkJZIBLgW5Fph>Ei%@SxE^qV8X#R`#Kkr^7bN>W#`lX@X4&acc_W
z%?L2Y57Q`dnZnJ6*%~`MK&>Jm?sS63gPDl2E2!OuhIbwP#D9qg2B?_|N}OF$La&s~
zYuaEz<&eLN+R-~4V>||3W*){u6V%;c9b-Tg(h*_qI8l@``<4S@o1mQp)GdwMX|UM@
zAsp#6cp9{F#H>5_p??sJWdl8oC0^4T-|VNO#*9o&Rn2vb?#xe~H@-8u8wf;_f4~qR
zZ>-hUe;}&0lS$yF_2ZT34NSbXjc<6oJ`+t>TgjFwv&#%dljF5LWPWh6I^Ozv`ru5p
zod7F&)1Il0e?6I<nW~#T<~L1vFl|@s{Fw)R;H`}_qh9;o*~x=5DGQ{dY19@-+fFaX
zu6G^1y1Bov+H-v+YxcQ}`%&$2Q^TK{1XX)5@y3%{4X8SsWH)c>jkf(AgwaXVijGX7
zJ$eQ}VVl7^as_yqbW2n{n40?I>{2mX{b<miok}O`rd=IR&KXZqU@*7dipJB&&1^az
z{#MkkM&p|!de?Nc$E&uhk28VazcJW2>qXIcSgVhlkS;s^=*2xAn;qyA%uWmw0;kyO
z()p-WT>m1o+W=49X5vSD3r`7?GI#pGPx%u%vV;&Bg3}bRsn*tjGq}a1!GSz>umOZV
z;#tq;>wJ)L%4Ve44osC}RXI*|DdmJ|G*x^4b?4pCJUTq`u)lp<P<eV=<$+4_eqlp<
zYNL_6Z|3L`16Z{?A*l4<Ou(pZCVama$OU*(wA~Oq`}*zVqyC_vrONJ^(N{n2z0OZK
z|FjRf)q318dzuNeCE7!P_-OQ~+1S3a_3N$Z`U8WAR^3_q12g_;_@-mV%vSHrZZ_Kv
zZmvFSqDQ0AZ;%vTG{w$}Ff&_cuDs7ge_nYu*#Itdk@xxb!OMome1MCe`*;4=hw48!
z)iw|N;dSQG!P&%kSN+phG<uTc8vYOW`oz}<Kw73NyJ`LHW-n*n7;)!&*)dXEkAvfk
zfny{>uzZk`ir?aiM|?03K3vXN4VxwW-Q(>6^l44P<w~Tdz(-7bc5BLKy}rdavzx$s
z&fnL11j#o{f?n(!eRS$U6OH-C{0A^sv)PxL=uGX|dac=R*TZHz+%mb(m|H9Nn&`RF
zcTb`Ace6)f`1(Ifnl}&g{c;afGJ@rd_84P~9&0mbu~T6;Hf>x0B;YZS4!}5WqxEM1
z0vfbhb!U<V&$fi(fyx~koG8_wOFw1Cqr-!D8*|7XjSgN3K7qvP!FDAHW;gF++6e2Z
ziEc7`E-+w*USwXN<|$AjJ5AP6a)gJ`bO-%0la8)GG`M%lL>K(f4b9ENjbnYUa<Xf-
zAuHU8dcomJU>gD>oM2`Oo4J>r7mw&YcHo#&ir@|{aW_}}BavY-GJe+V#8yC2E*k7d
z>MR>?Z+ZO@BPh0AztQXhtNb+BOxm~^&?vc02pqdpFpyw2WUM`Z>)TAqy8wHs;|vYm
z_IK0U+LgV2QcwSfnM&D*1cuW}4kzJdzvR4ic;uO6`>>M@S7`|2+-)Qi4biSp(IDAw
z07>?8!g|k)blf(cpf;dnRcr#z9&nZ3cxh;JOZ<)m(B)P$y=CjCaV45jxZO;T4`!g$
z&nBgCu<C+0;WS<8GoWEV_lJTXvwc9qS61)Dis~Dl<uhWkh{nGKt`m;qk$%}E?eGiV
za^5^Vl2n<+n?z8w7QQT&474R30>l}Nnf+e@UnhkTxRR3_pd83xs+BeqMdEmSk~mFi
z#67jZO&CyGHFrN6*$T1=csE)aKW9%R2m!sKdJ4qm`z%1b8{BZ(qj&g8+}`4$-1Y_(
zI(ucWTLobPBLy~O$JwX;Jl;M$lI=sKw9jzkJ%EJSuH0lbk&YiR!HjxfiY~#ng|?yR
zyf+5Tr;ST%fX^nNi?blJ(R1mYz5xZMp8mw!$UVWJ(B4pO8jO-&bZ}gKl}%S;UpMa7
zQT2ph@#$%|(fnUF?=~3Pm<vQ_z-d8}H=~NMu5J_6@2{9>;wURD5C3B6hQr&3Z!}Lf
zw+}yMwr^|lgXw&ggZ7cJ_YM!h-{$%zaW0y2dTHVk9S!KG%vrLr2lG;?pga2#5W5Py
zZFY|)=~L!_adxNT<3=FQ=Ca!~tY8Poy$#%s!C?0M3EE*_@`%4a!ah@q1a2F1!!Ve-
zbt}2|!Xnu_F@65-WUL+1ms3Dz`tiHI`SQ<P*E9O1k!DYJ%}7SK;gy<Qu9vV=2!COl
z`!E3?-4FQt5bmFT+OB`ZxEbQI`qq17f-f(Nq6s&g@Jz%DEM(PB=&>@IZQSLJnDl`E
zMN=jMNS{ke^+{hjS<)ZfOty)pIfr+5dPhvS+5ch`ewuZyPy0^)*G*~ek&AaEL63YA
zz^_4&g@nyU%&;E%LyK&_c-SWh4_skm#3r;qxT1$5rC_^>$#d#SWHzi5v_=%nZl#yU
znz{~W_zEeDbnLZcS0{Nw@@xQ3uTjXQWy7M~HUcORM;2cK^Fs8klVN9zUV{Js*6{1M
zi?5)2+l9qf&~?5(j+bCAUH&_~zm<Ol-Ag1Xm~`I9KQWVIOELNQ5__7yGXGWCG#DtA
zFeNQrLmB@Y_DokNCLWd(4b6SFvzJHyF%;;IrQ^J8?jqS?pJF^z&MztX_yc*;+-0*)
z|FGNJcP?*y5YJXXIKV^pXv+!P6I?&O&K<?ljY6L$n~r0PIgNq^Z;FWKLr|m)c!$uS
z90j$c6gmCv8e#Py@k5fF!+clUG?=xRB$F+pwRP1YQ;ssgqeB-EnPq-|G+EpIUT0g=
zO*XyC{s4=Y5G&#9ulHkuRX5!MtU>G))EF6kfGo-FO#pqQC2gw-4@Ki8UP2!&hXZs&
zFuPLdM9Rfx{%}W<OyH0Z>6D@@Vp~qx(N`7(<@+9E`+K8j7@W&XEYCz>lE-Yx{u)!m
z(Z}Q0UKPR*RIPBH$LPLn2nj(G!S5(7iqpi44qL7Gtw$n4z0k`-hmt&i7&xTB4Tt=C
zl$0{B-yDd(^PS$|Y-e&Edw9;}8*e=LGGiFzE`!PAckoTOBWfq6b)q#KJHo+azrWv9
ztESv4w}x&@C-+3X=1SA+`-9Xp34<nK<8&?KwH`lc0#Xe{>#F>YwYgyAwojn~hZgV;
zZO*FZ{eVFrKL?`mqu;$GsEqVrgA)lWj3oi2J4~W!HnDh)hJaG9pOpwI8%Hv%s>ujP
z91oO711bI+ZPQK!mizrA*zAvn$pK={AobkF5i}C+G|brGbO$0dS3iJ@Ektw5;8nZM
zT{G*h-p<J6C%yg=R{Z>aQvy_I0r5>XTsDozO-yJsaoGcv^bUYFGz{~UZ!*7C1DzWs
z>u7t%4>t{ZqwL{)COyKM_LjR@=*uz>j0;=7ZIr!Elm4cNO#wJR2f%hl>+BWwdPkyj
zlHsVeb9AEgOiINoSvouQc#2byUh$Q4@#Tm8FIKL(d4x9^0MTZ$*7lM95%+4Wcw%Ss
zP06H_{kzKRLA|ED{w;m2^;x#b_rnC22Ls)cw5UmQ(4RPrI$8%ztJ#jc!HYuAud_dG
z|7(K~U3gm>{*h>6i(x-le^lQ*ILem(X+qO=6KQGGxKZ?pBZG7^AeLz_+2hq~GlM&l
zaIo>I!Dr0<Nj&Ih)h*H7Uv0&VO=;LkK8>1gCV)l(G-_j{OuMrMf*-C2sHY(uG?tW<
z#`&QE;_3u|Xpq1cuoaWdDe<bnbgcP?o{Qx%^CYzqH}+f>=-FyRuc*E7C(ki0XN{3Q
z7yc2O=>Q|0kCx&Rao{j;3kX)iqdN!!9lyRF#4bTUK$sH;+D?BN+%(%C(WiigaXHF{
z`m<m(H06&bHIot~rx~+bvI$)_qB8470J5PojhD;-b0CTu?|I#M`};;3eNE<D?d;5)
z;l%0xd4Irl`m$h#KK#$A6WxlhA@J=h>U_b4HvPmiHBb$wk(F@oK(Laa3^1AcuSZ3U
zNkSL)`}p44v=fBs5N`tc(E#HCC_t@z)yK+yv$rQ3Zr+%U-6N1}oX+9teYOCrqW&AN
zb35ZYV~OGSspG@Et3g*t)5)mUkL-d&#Oxi{!cRxp=mtVr?m6_N$nj>i|EXjLc5op&
z&bly0yI1`pTM_oYeUwd>8LbBFrZE^{X?Z}S5{ZpS_gGBGQa_$ym;|vwX2v!~XMvRy
zY3+PB1TD$DF#qu%58ja*#W)hRb@3LvuP7+viCr3P_vdaux`T>fD6!jX_{uVqvgV-L
z#43@JP0}!!6G)t3Rx}V#G5CZjpk3m!=%R{XJq=S4Lc=&0KW9pV;V8?4kw^DoQ(Ky`
zar#y~s2v7a2()ZEO7>m0J{ay99%hSYPq02og$D(!)-Z^X!(`dRd@lf7rVtLSjsXS3
z&QJh;Hv<^EwW{Sdg)%xv%7cL?i~tdDZ6zQ=WhZ(jDIaXINhcgH$LSWsycEdJ(;JTU
z1Po=p=MK|t)LV7{z|b%fK*SXQ4)72m2g5UaL)KyGOes+~65VF%*F_8~9>vfNc=}Q|
z3rdVSsx_O$fgaN^-bwcfLb`K+-rdo2{3q)#!`>P_tfxHeM>Oi){)8#9l8Nd}EL<&K
z-vWY~;Om)O<7Z3|xV-ERa#08G{q#QW`%_cX>F8_?9k(_|R@PQ|R0{*O5{Ab<MoV#d
zTK9rfU3z~sx8Y*!c%+}6h`G^vBE;8Mgy4Jw?+SWI)FEQ2XG*%EWj%6|N{0^0L6Ve%
z^G%KF24#{rMId6Ir(3DhOn|Ll3aYEYJM#8N5%b)!OFq%KXL#hg9?IcurZk9l8hQTA
zGY7Q&jy0OJF(UUet{q@bk(u{L;B4wsQDE1G9H-6JP6mZC241d~t7%fIjsx?tq65^A
zTNPD7hJ7}^#OHW%YJM*P$oVkq4uAYVUwIP~e(%jRi~+Y`nqgJT^fKeJt;#nbpX-_G
z>7+;K{Q)mLxf$*6u&)Wc&unP2WH?=Ac18u+Xic-WtRgN&UT;+LTg0=8X@N7l?Wtf8
ztB%H-xGzArb@$@KuY7a!>c_S{vTb|T@B2M(@vlDY_do8Bn3<&Y)5!<gpnjML>o}ve
z+F=tXGl^%W_9R)7w#<5rg4|K7w(%Ru*U|T$Wc0d0rpv?r<lTe!vX9qGCuV7V6S#Lr
zEw*~$XKeWN;Grm}@!D6|@3x*z9*tP2`nAC*zBR4iHXeFg+k^_!{>1MY@V5IWKkn~I
zy*(SVR-1>OP3rd=rq*<}-k!wsfBwtozS+O}&yss?&YH<^;*HKEqaU1Ncg7Sb<&MOR
zmq6Bx*Ut{J$%#QTHEAYWQ&X*<HbkWpNJ%(@kwhC0n5x-mTvkWD>cPQqil)L+Tj6s_
zIN8R@0_2+rOFNQa!>yyONBr=SXvVAWOfQNat!^RudEAt<J(Fx(b0#15(?|S+-ra+(
z$tan4GrPj**IOR1-d6Eu>r-a*O5fY#zxYx2qU<drLlbxUeLdM&A5K?+3EH#TmrP`G
zba2$}JD3nSnB{qRZH>F#PbBfP$si&9`2c^<rQo(Z(13ZzC?OX1GkZQC>CS`=?Dpf?
zq+%Y8W{3gb2&j{4Ei|ouZS(+f__M^Y<K&+zKJlTWdd^(&*X7#&cEO`poO|7!!w(Ga
zPM$p69N2Dt|5euv5U&1T=HS;WV1Qr~7gay6{cRvAAS4ztWOXRH_xH?GMw_p^Wc)$n
z@AW?z-CC*gc3R_wBSIMWC4d;??x%tO-0>sqzu^J45M|EjtZ%&0N0W$e8@U=NYwY%{
z{;2n3hD|1w&$Y5`<KE4J=BAu|qvwNUL{Z$na$ox8Ry2e->^3^Md0!0>^WdZ2FZfTJ
z_Q8m+SZrUJ+|5H*Hq4{`bEekbu<yT>ZUDp@;`f?B06r4~M<Bcq6m}A|4QsS)1Y^TY
z^^btF?p-gWV%!CuVj1%Q2oci_0Xt~U#GQsIVa%OQM%&>aJ8l?(!qj;q%WyLwE9?Yv
zGG1z8><QUN7Pe*#VqeY1otr?Dw{AC}Pi!rc)Rl`+V7o2=EuwnP*5=K^PSWs=gJ5&@
z7ryatd$R|I+2RM@0?={uupkC)BJ@X*s#S}CzytyzwKsmu<ZsdmY#SSCOZ`9w{cZ{>
zVL-{!6i^GiYag3j!Cu(EHUzX8rJw?3#^rk2908M=0IBp6&<J1wVG?YYL*06-k6m%V
zZ`uSm?!L>I2vO3uH+IC}J;d)es67NA3-={oHZAk+ftTOVyz?^yf0o?&s<#h2*SzWh
zTUR%DR?yo-f_N4^zL7m}2Y?T!P5Mj%zH0E$gBt1vpAx_auEiOMZUPoP#imdy9!1VH
z3vQ#S%PV&X8?y$;@XNlau@OKq_g&P;9dpyIN3j#P|7HvM0jWODPAN7x(0b@PP3NM)
zedZf}^ulvvPYoX(9v<3<tiwGwe&(77DpZ{fd+(8~bRZN=GchqT_e@{l_`8go2=W}m
z@0kW2-l-PZh3sx{r=c0@pcU?(D^dAVtlW9~lCJ?Z9RPAB$g0u=aS8M<8H>XEjZ<ei
z0o7t=7__!`(MUCbkv)}N?K+szIC0$c=6x-C3xEkWF$k1o!i(89ab5Oy^O<Jj<`F<7
zUQC2>%K8wtz)ZT2SN7ska2RJrBf3ydz{ZLo@l4<<@nehjnlZuuu-Gy;H*2%xm<bs@
zFahAZ&Al$IDL`!llWdHXbP!>9AUv~`ejiA@$xc)(JqT}RnJfrr5))naE6$MhA_KLm
ztQ2SwINf3D+pWd4Lo^YUXIUX5{ABOjPR6CuuE<cjOKU$3s$K!!3v1Y37)3|5Cog7;
z8;z}ZEyG58UVBb3bTfN0j}8v9*UmXu=5g!;7&o1*1T0N!j~qSssasw#QPPTYZx7qU
z){TQG09@e&fJ-@QN#^(zZ`U;ak>n;q#OaFJ_|Zzt@Nh`DpUdt6Qx4pE$=O=!!~8Z>
zOB+ATTdn22nZR<?95UZmT<?v8Kxi3WBe>#py$)nm$Fs`tWZ(5WFC)2h2)CGThNa5^
zpt8Ts;agz{g&9x`PIKH;$Y4DkzQhuT5BV5fB6;4d{jiabwLHFu^APy)Gi;0tBjSDU
zZr~7XVh=Au-|y}4S<|IWE*p}gzKw-=+(woMUwG3ycO1TMpl5f}@rRq*{`L+{N%S>s
zZ{y@kBY?A!>rc2b6U-rI6sDmOAUN&`=X25>$==LPMAII-<bo|e%jMi{x_yyHgw{KC
zE89&%bP_jxH_Q-tw8V_UcMhZ@ypzE=(c&e{GP?!B!`ZYq;j*31jad0QQhVrMy<9&_
zah>qsue@GADZ#JleZqdHWp+n<;qN${=CA2};<la1-mzQSk8=Fj=Wf|M>-9gq^|8;g
zeQo0T!N<0Dwy`0}(fqggZcX()n{U1_|A~xz8{4sed+Y6R`K4Q;S$^Q}eV^p%ZYIqR
zljb5OS9h2UU8ucq$9CVkr}OiGIxgZ8{g*MzC3<Wm=hA*);5Yt-b(ir1bI)4t;6hU1
zgIic6vXrb-zK@KB<sbowvge>3vPGNAKGAo_M~ICq5fC^p0qXKwIR6Vsk6J-;X)LEs
zhPhWAj-%#n&E#-z9{?W_T8Xb^0PZOhu#p}2)Z4|EQAfn-pf?SsL?WLwVV@H3WITGv
zPpT<)&#+SpwnUqJM)^`wuS7%j1W3!j4pe9=3ixFL_64<Shk4rppExMhn{F%BewiKV
z#E~d`|8v`39#;nYHu+aK`}*_~PQV3>zI5C~(hvzGQ()!J4u%3yK_90v%bY1E+d)JD
z(C3Y`dEbn9Za=SLv9q8|w8xTu#ZCH;48~W}IcJFRxJh{AB@tT@fU5lXQ@kmV5D>Qp
zc^Tum-+UQrYO;%g0*UYN4p`yIb;)LKCksK090ibq{}@f0VcCyn1EPCiMFrX@Z}f1@
z0csm6^VZ^>eoqz=ckW=9L$EpWb|eln@DOnT4VRP~?(=_toekEBl1o{mr!ggvAW~4-
zBx;x<K0GwyMAuc?yZ{BbXGSj>9BEU`tq2ti^u$D>?)8LNI}@IxReSxizbS<it<9ia
zjuZC62{UA(nb!M-{@n2G4*QpesXdLW7YO@%64`3DBOQX@wbVUpxEo6&dA)-y&3fV<
zCk9rqCd44e7zIP#gQgz6JqepWhyaHLksi7^F0m;j=xOwP^}`79MF|MbMR{xttKS23
z>+Bv;^^%DmK!U4Z>-QcR$%3It|HzO-2LEAyV8m^vaheTWtEEcWKJ9-SKQuLg#GAB1
zCb@+7w)@;|rQTtpd=MFL;CjCYkY#(;+6`=D%ui?WmOk&Rzr%)=pfW_R##i+7gbe?g
zliZCVWD})B*YEAiuI=%rlV%owW+Vuc+V*UR0S0Rf-<CMwDiu?qt#8aWwR?N^`#yK@
zf04(>tb&(a+S3e%-1Jh<ANl#dw%>SsxH1B0-KqiG#WQ`4vOoIHusYjxzRnkWzyEnD
zj8^4KltJHyVKpHH)u|l<3L7sa>>vwe7OfJEfa*a+Q221nJBn8CSRBUHaO*wW>^>3R
zzy!Im<c&Djmq(%vCElfSo~hs>#-%0}j7<gb3c(J5>~G^WM6Q~OMGx!k&EDZbcmh7b
zq=mnOG0-}?6r7FI7dlO^RSrXNF0c3N&3m*e5rsR+IS_0%VD~}lMssht)o~hSo@_SR
zAyt~-`#!{`dQTsQyuZ&G(pA8J5ttM*c(9Z#{iGs-U_q=9>|o$Cy~91Eu=_`txx|lm
z4MaV??iYSRr8vX<7!30<$Vv^SeT+HraF6AjPB85W$ZD2hpnXWaCUb`XCUl?NmTI7Y
zy{fA%JEpr^y5W!XU9O2UfR1|-We$3T_UPs?|A(xS8bdwEkWG#_15FYWDs^MViN8re
zQ2H~a-k!8oY7R`ejnwoZV^F$|8p3pwm>j<0KlgBOhDmU4j50ps9&e~d{YQp@9CUdt
zTM;q2-kzH0)RM_-dz?#p8fL(q=rOjFqCUnQX(9l;>)EIcelVIS#bCEE4B*oH&CmWJ
z%Hj-PhL5}&#Ra)@@?etJu1Lv`6Z1`VJpElCqz6m+oqOD&$q^zt0zVDUYDXpNqsQo+
z6q|<jkctIC`z%nLy=fmuzAKK>AU#2eug45|G(_r6S#SEz0lqV|M<ZIpuhGhfydfUD
z+8yDWHP~9k%a^o>p7{SMdmG@kuIx;ZRM-hS@obYAwDQE#DgyW*0!?6HDatH8rI`^f
zE*~#|M?%7|J7|}y+oB;0j;N)rVqEAc?KJUp30*=@kflO<VVBkswQ!p5D6yr2yXYzI
ztO-9u&onLB8m0sHs5X`s?x3q!X-kWC!85F6zY95=&32}CmXv6VB=Fw-JLfy!`ObM?
z{(zBfSUAkTe0x0U4hH(~-fJ7%?d(11<h_okv90lzXa&;m{`#UDSEIPzqx@NpdjKQD
za35f~T#5c~$miOrxMa9DtQgpSt6d=}-0oBUUq6&}(5K-daI~^tzR>UbyLUBuy0V8D
zw)^-0H7r+WLFCx`wqc-Z4<_YcPw3$s&2@KnD4pwZb#d`F@0^l@_&pd5%pYz<t`w#-
zEC0{c`PZY^l!kGT_MCtD*Rt<oav`;VI7NBRg`st+L+UU^k2c=o9J?Yrk6%F0fNB11
z$2Weh>)=UponWrRZO+v$S093cgFW~;x_HT7FhImi{rwxLhu|dVdv_~62;;i?e&q@l
z29*?8;NSUU%oTRwKU_}SuDoxoOrHy9@5_bx`|m1pAzgC1>7)Gbzx}Jf{MnvAM-@+J
zuSr<mrTQ?04=JuFcOa^2x(;6O;>$(6RoA$DD>>}W_x}sOo|X3_f4%Rve4Ea@|NFlI
z-p4J=Mmz^U>c8T~HQW_BTRLV7Z;z8LoAdm`AF6NjIDXJa|7%}+;aA=`#BsZQ?dAXR
z|1n({B<{{7=Y`4vVQR4nw>|tewkPf!e}84d<$TBq-~Ow=d+WcKKl_!Bhi@+5?7#f+
zkNotrAH38>LoodZ!8QNiuk`o0SQm|yxGrF<FfFJhn8T*PNSMEeb%i2nhKzx%41ure
zn2ATppz3sNJD6f&>GCiDK()>rK1-^ki*@Dpb0b9GcnV|x$3Gr=vVZ(%fA`(aqtoyY
z*O%Y;Yw@h>!Bl96n@rJ^c9L$m)t)iI!x_`&VMvqEm;r(2-G1X_|KcEob;IPb*)Lyk
zkJ>ryfyD!a@c;iWd6u&genaRZ9Ka%bwjWPF-{tcDcK<&&T>aPF#qe*tgWHQPw>rV6
z(`sC=yH%R`FTVsKq%Y+j*1Vk;wEyjY#;%daETj@_k?f-!O9S?~tLvY-w&DBOQjhY#
z{}F5#w#uV8g%4j9X72qQ`zkCGg8yGH+x_J`em3>e!6~Ot+nCx<eLbN7<?AD+-kV+T
z<);xrnB6;Er~8jMMgpOKG4*to;8$xrPzzrokMe-U_0I2}GZk|$Qi-d|3;p|){yo|M
z;Mf>^db?NEE==k5sRNd;CtN4GZN6ipRoZ{$FLU|JbsGfpKe!LyhI>zrxQk!DaqIN&
z9dtUM5c5n)f*tBoJ@?dx+9HH>#rV;EwVCN<x=b$d7z?IOSr(6ph(Lxn65E0L$^ln)
zu^;|8K!To6)lWSeZf=nYV~ifXUR|!W3=*j2@0cw@&*(RV$Ysom@|H8baJFCeTARa5
z=kB_SiQ&V$NPzf@B#;~Dp>gAw_qce$c&eGoP>YYTF?LxQ=vQ6YEJ!w-C;$C~Bj{>5
z@R}#pAv(^F-qtSFA{*|yaZ3EBs2R8FcE;3C3AEZ8TR4+FjimD*{qApMM<-!svhr`&
z!RrJ!8pJ?*CX6`E7_-%rxzDXyR6kj}mrAkG3imeI$28+CLwn|Ob%r^R{m4CE?ssSp
z2vPME3#RLPlI{QvvP$mGl@?n+T^8fm*uogU^nwDqGkXp%UhIF{;n?NyxYaV9sIK)6
zwyM1LW4f%3(4o|ruG_GlO}5m3G3>)!VnUI19awej>dZ>#4oRHWwG6p#RIm_s^iSv+
z>lVWRE4(e7@Ar=(J<`AM95e#wSGz&MVuVTL0ddqlC&@)JOnuG=q;`|fusc(msivMz
z4bhNimKS+snJ@E2CDuQX&Encv4>Y`XxdM*Ce#dS1#?%2i#De~1tw}39y)=V$Tz@Bt
z8p3z#`eG?oTDTzdE~p<~g-<}R;n?R;Ro@1o8&9`#wSwlcXuuk#6WRpVm7Z8>;OC*&
z(2#BsYq%T3yzg-MF5q&wpoTfz(zF7n)Vh1lESTf`jF@k-?A_2?rH_zhI16U>f7|{W
zSqf*2KkycZ+^UD{BmP-pOw#dOq-EuT(_6V(EwRU+r1^{-UfapXLLs#9a=E&9yB7N~
zr{DaJ<2#rV%*^enie=}*v(=h$^l9~$zeS?!I4kGHvUqD}c4^1i{!g+YW`pE(U=0Tv
zo<B_7^HfMfEfUXlY8&DG)nIzdFlM}Rn_H3I(CB_X7KyXHT;dG}ib`?W!Ln0x+*4_l
zia6Uc_|00O7N2hCsyE5R8m>1cZiu+JwzFL<eSkDc8yn{Sr}q!BQABR@EGaP3Ic%IL
z{_H1A1iedkP`}CxMqEvKCwN@Xa4wd)@a-*1KO;-d77q`p+pC25ED{yUexqOnNPMZR
z|LMd6OVYFAv|WrZ_?DHAKxU$ez+N0*Oit)q?jnxUWpP}Du(6-!8+$6mzsZ(FxWok#
zQu6HK?J=~ZGJLqtQ6(auG5(q5`E~7Q<tGg7Kk4GU4c+>C*UT@9rGkQr=XqO+Yrhp5
zg>}hhc@~e3!eDrX6mjw_8cn(je7eo)O+G9JPm%prUqhY*F@O*ZeqFXSmzJULBJo$q
z0Uoo1v{f_g8MRUyx#_u0MTTc^1WFO#TP3(FaQ%=dvJo^kR9wSO5`_(mRtWG5vjf&p
z`ZzrSi{bM(8NBmS=|#SPt%&d)=eyfA<oZs+HKcm>5nXS1E41N1#b?R$xwJZAoD*i!
zq>*PL=Jzhuh2+TZf3I<fanwU$SXd!o%58qsNqj=v+^Ef3<@L3u>MvHsI2Uj5<zhP2
zd5Uw_?$w0cd{K+|V143xsal|MZ=GzAI^PmeU&>xs!j3q%Gm?cM%yn2+urFYdK5_jr
zK_34l!L*fW5VpArBfROwG<w-RZ^hu#G|y5@#Ii3hN~<g%T7r{2@Jo^y@GR0{%KR<L
z^IKf=?@W2k$se7i=S5O1K;FL!%{{cnS=7vZB<}y{-yEW&lSo5gp@C3bpQsf=r&Qc(
zlg*Nr#tZZ~4-K;bJw!!;kMk0ZVW~Ph&&OY-glJWm{P40-w8m@0<{BN?q?=|&;IW@L
z(W|c@$A?k%XHatA85UOP)ln_sW`5PK4zmIowx6<$A-}dq?Y&%*4hBtv92gAjM)`2i
zl~M<LK6Hx`Ef^<qYqQnc#;LV-R9j1~-w=6Nv(gt%^SlV*7|Gi5?|$%Gs}z0>j!m*e
zcwQ*5_FMyaVk2c@jnz&67OxhFjp_6P;l@PlLOir6g)itLfKr%H&}CuIFfx=XaGSs*
zE%BoV>@(___4jOX#*T|Dl;Wpd{UcxpkqGLC7i*|*IvSWaKIt~}cFmaaFPZ*!)fikM
zOZ>8kpjgrCleJ;eKrHs7|3;DEPjr?z44e9wt0Qz+jG5J;@;kI4ns(iM>k_tk5hIda
zH4ckg^{;{g0=UEyG2ecIZ7cVAT0h2SrnjnA_&_yClY1_Un8-`#k`9$#mgB*(0OAa~
zqy@v6-hiO&0k7s8Y>Qa0tCMTz*E3?;{y@y9BCm+k5Ck8|qQlkh#r`)O_Y;ZX(SSTX
zoUd@P!tam<TQT73iLEaQgXZ5VDyp~RKkx#F@`<{dh;kf2pH&qntkIu&FIA^oWNl$%
zsX>)3Qy3o<x3`>P!F5dmJh}gb=<9hG@q_eSU0riHdIpk;fm*blY8lnI_Z0n{5Pg<c
zHTnXEw9MPiVhm*<_>gEB{_D*I&WMZPjsm$DpRQD!=@JbXar4eM06$_pw`|r?!0^(`
zZvkkXgH_KW>w}LAi6AVy`=~ltAr`PiYKCR1?oEFySB;dd>KnW_zt|ssO&%ziR@s~M
zs7v_{Ie3Kz;IF3llQIAFmQkIsKmDl}5$BkFL(s^3#WDE))7KQa6aUp;_q;o4VPpud
z0PYXDCkXRg!8ztuEzatDHrcFko37WG-{O%GjIK_-@L(fF*d|;NfJYss{=LMrjSRt7
z`ZHRkT3(OQoBFVRo}Z%Tl6Y5dMv#;0KHI+l-Ik2saDm4s-7XI~NhYa3Q~NR5RGa<=
z-Guev1mOF!C=?@0uon1$9fXg(>$*nXbo_v5+dSLGsK2S7s-7f`RMVU;N4J<b2M1Oc
z8FN{Ai+?O&G#uH}_uGGUNFSxW^EhELg7i^<0OEtU`-~eWs-%#M*{&h4FGFW}SpaUl
z=Zs-@3;;L6JVB}kYdDek);{bk>_`z$r@b(7>k~XYYiF>^bvh!>h=nhT&WpRS|GUm)
z&t!2p9m9wHzjWX_2EFa}mSBg*(m}P!TD%4j`8KkNua#g4vEgwYe0@P;sRWzA=FqN_
zS*v2KXl+6V+tu3G)uF5Bd3`;}vg77?`$8$QxMLnOIdFgB<32iR!l6jO(KR>e{?Oes
zj8!Ys>h#t1ac$VVNsmp3w+Ij0oQB0>X?wYUE}I3if!`0h_9CqNL*OqKP0^rtD`!L>
z38ouOv%>Uc-o#WU_3SJB#zK~#$(kX!EoJwr<8jw4R;()hBN>A^9Gvz)bCm^ZETF|H
zw6n!xYyp+U@bs|pk2=0}J>mL2;s-dupm<6LsiD~?qUXI<^o)KETPb61VNXU7kT?L<
z&SZaQ?5o)jJTYuX7WSRYISm{$9>&fMw{kpHux6&qIxM)qHzvl|xHBGtC{~_m=vc8!
zK61NO9S%>z?YU@-wz!c?>?!0tj@eu_e;)2wsWU**bIt;cFjA-TG%xgvY`15d$3eEa
zJik8JHjE)}5D}m-M4n+!G}$5~k<u1oOt_L~%C+5n*sZDoLkxLyKS`z8khfrZ$bLcL
zhR-?QUsxY0BKhBc`u?B)yF-kw!UIdB)YTOrm#ODEnREx$4YJP1wSx9kGrhBA)t*vk
z`7C$Na;s>>8LITK{cuUR|A9)POovA&FyjriY)x=~rDkp!T7d-lmc?G@PuQV+U0)X0
zO7C4l$O8+UMJfjdXA#Ce`l&~P3~BD+l;KHkYQrqDWso4&WY~%*7$8#@ys!03L?fXu
zIxYXe5%e5&0fRn(N%NPq$N_%bJ}z$3ANq&rLR+8^CxZ;}``Jic+|72Q^hf#bQ12*J
zCIRi`DVv)mZd`Vl_9e&!KVbw@Eej|+IDM+7Hd5+U0WD&zKOR{GYLojB%Quj{=J-^-
zpCE%k5kQjI#(X@dU9Yya9QZQ*yxL-GwOO+cEZOGH)7SXN5c?o*IwN)K-HI#PN+bqT
z;MN8ksg!QV{jFMct)VykE44<dLKPhF4f<ODE6&&s2@wHArSpE(IjDLp1WR5kH#5Cb
z#U!n5X=e3xzO`<yw^1xq*RLs&mJ?$H(3x-l#l}JU1kWOf!MW?2lMaSOi+BSB%B5V4
zj&4va=W&Fh(~K5)NW9o8@|Zm5o$v+6@2=;rOP;-ys!4o*OfAs-&Zn>b@apU345Jlc
zi^vfsaO}?Z&qLgY2+h&8-FPl>(&1KT$pd0U+dLOk)2V_nybfz(hu}uBQO9wb-g08!
z05EnrhFtz5>X7SMynqA&3i6dIVh<N$L35+fB5(rl(vrBraKB&R3P`+tcd+-}NeT$u
zITcyBfhdCI3YjI_e9Ekmpfk+kshbG116qjU?DLosk9>i1iOe<z2cv>DY&jCcbYMTM
zB|QECOAN0+1;DXotrf_*s3|elXx;Wc#y^0A>r5#Q$DAwcDm&+7=+a27SWB#`T`|Yh
zo4F@xq*oYl-I#iKH&_&Gmu@9malA{|?gm}rxdzsm59@LNrrF>dKWdn^d4}D9*6RI*
z?OQv68;@i!_y5j2-S0Y`k8pfQOWC8kU?9LU=oMqryJc8G{f@RpE#{fEU}q?N+%6uE
zphpFA7`QU@NJrt}FrYFWqSa$w#N*X!Zh{Xjoo-l9K#G(!ZwW*e%4ahDiAc9D<cwT%
zyh(TiAsLPuKCAh*#)H(G@){(%42+jzdGS{9=gftY#7@N79Y_o;IunC9tvKtvfaobr
zr`seKFmDL60Y7Tou*WaG_gX2w(C@vAYkdFG*XAcVfQfW)GJNTBVPie?0(ygrVimDm
zO&hJ{@(n737irNxrV=pp@5WTl;S3bX;|*yghA9csB~#x|Zq__Mac_E)SLg5HK_EEp
zY}t7iVJCbl&YOu7kBQ;)<xxa^m={%D;y10het_2072+*J1|weXuN0-@b^#c}iVYtg
z{$}Tw2WLsuh&H_$<8#V`I^7_r#0Wbl&WaECdr2!Ed9Ik*nNiZ&`DXUHt>2*5DwifD
z3!b+JfJB9No5;n?VLLv(vFECOoTp-J_XrP5qTs&M3AqJ;q&zZ+EgY_d$AQgTF*2Y7
zt32FDEw4AYcf)E6bM(&o&*ASs77$oIs=%Y}#Tf;E@?63=qN=V#B$6aJR-Dw_m^t8)
z7~%;dhPnapq7q5Zac9CE<<5&_H+x?DnTlz?Np6)}%+#D)T)<h2#T{b{t9YF6!2Q>E
z_JMGdCktM!Ye@CsC?h5dRKqqsuCJZa_G$6-&d-SzeuC1N2rnt|kPm<z>w`5~B@+pt
z9*x{nGjI?yYFQseY;d);&R%aUv!s2-#wPs2bZ&27f}w)zS?EuSv(oCUIshMErG9#y
zU`OTlkx-y|T)$~ekZ9QyIcK@#0QG?-0%`70E{9<CuTWnRFtt{*YU4D3lRm-C$*aTG
z`}~$j+UIbkw@Tl(`ZAIWfEMww$NMIcx#gYRH&>=lstj<}jLcRm)}?A>$;9ni#yI8=
zp3VF7kPjU{urFW_2ktu(ED>~-sT|odPip>5Zl5u3c@Buzt(GNjvEDPHV4fA*H=*)&
zpddt9R<OFm{f~oT8~i<@O{r=g#))1xnqC2vItAf6nmzVPSPGW?ZO8EFaA<<~u)PD=
z;2<<<uEncjNQ~ZIOY^fLKOz=BqM4#Mq%^ax`~TBV4?271AyAhU7cUUzQ+s@~M4i;e
z=rD_|*DBVj+I7;@y-Q*g#2Ww=ya*C!Sf}q`qG2CYc~dbnCWh2wtYC-$`{9!7mYL-9
z2rACoC1<#9c7u0VKqVHC--qtIYAZpa>V7g<=Fw(4o$_q27)v&+CWm+agss99!9aj;
zcL0Aewu@-QafOdjk2{qPC)I#9pCKoiH)ASovGY7zTDSrCWcIiJ;P-(KC6q!!8DlvJ
zo*KA~W-M@Da$#W^jGV7Xsm7C3P)a4Afrj|N9=pi!Vc?uYZV$%7hte_TLkKaw;jV}c
zBeTA4o(G<ZvkM~fMM>enygUn<#<BZC!rwC(LSYOEKN7R!-W6kmRCtl3V*E*#M*#cs
zVhQMQw>+T`fAy%2zHJ&9ng^W5Y<RE}gax>kv<u+h$NA|mAU8qm%GwA1DF`QwMIIiY
zDA!=mCn~+CvX+4m%zvud;-pX;y$y}*7z>LMf2A1Sp<;(A08wa_bl3H%`f6x+R6?lz
zWWu<KZ7`GCs@32)RN&+D{uVKBSfeXqgr9Rp?(-62^K%Nc_1o*v8D!ztDvpMygQbQk
z;;<1bcalu`F*P~>06uvH0g=s({8uqJxI%n>(=G3^XCfEMo#eOOZLKz~OnT4pTMP)s
z1hUxA3(i%Pd3R_3=&v3L@pmEc>4Ydwxa>FJcJDppQD)MuoH3)ftGO}nIR9`8J1@oJ
z43qf^JcNW6@QI)}Fv{l=_taOh1!2jD5r`oSwOSgTr~wR7I>TGh^)on3ADCk-RyxNE
zJ6FMVfPIFH`kI1UKI|rs!=_`3g6atMZ;@(nx>d8HEeZF_7U>F&^FndpwSLLt$w$jM
zg6cQj(%Im6O<0k-dn1*xp4Vz%^v0I{)W{VDut`juXIRM72)?_5`?^;TaSq)HRuWcL
zbEj0qRbg-18=u~J()zJxk!hs}>&YVvOG+e*HIzKWT(=MK(6tETqCFrqPMhg1N{`V(
zHQF+2ul|%|L{c(F`YrpdVsmvb-;UN0NPG5sB_=td`Wh~2Z%>kYDSv}q)o+r)O0L9%
z-VM@YfE|d3vR{??`#B8B^=b&z?U1V7Q_E)Pm}-Z&a@uj0r~3e2#`z6a5Mz;7ib$#r
z+<#`N?+GY!WC#Y&%K%C^FPp}i+O~MqyWg6i(OznlASs1;1uE;i^7YFPo#uo!#_Y8%
zZjEb^P4<L%^+kThzGWx%&@I-q6^8RA(|(|9Ft<Sf0z^Roa#y*HZ<X!5sS{Ml_Zp>(
zcsPpWw{W5^Q~x!h_6$>9?OF5d+a48*bG`XxRQC_;HPMzh`yc<}U{5EulFZB;bz6i0
z=8I^Of>52p&BRky&X}N*I71o`ylOmjttgGP3s?b8VmLJLsb{{!_D)!%6@JwmOU2gX
zx|JI<CxkY+ev2h}p>!U^b}^R}=!Q80zyLLPmon^xFLrsVl$;=B?W%<n=q>9Lq?+T1
zkDU%9jG!kg@fM!sFzg)o0Sq=_LC|s{dcX>&SimZ<iM#|`6eQ&PS*3uik@uQ%|JeW8
z=X9drGTR|$oZE)fCy|>Q=K&+eC-AkFN)I;GWjeyaMK@TaQhaTP<m+%XxV!-%TnB<+
zIK-U|R^fnyq3Nc$0}}Gax><rBA7k%lW7+IE)UzC9@IT-#+_Mg21Jeh-X$xsa?WPu=
z#&NkxVtjB~H40pZ5O*Q}7~c&Wgk^NNq?M3f2q5wjpWd=?XfDAR-=SNAoG)h(YMAHD
zTQ(ahMj|W?B5kq%*78?YL%^$tI!Q0YMA1pNq}hS_<0=BG*!qmRM4xKXS?b)+!zE{a
zv2+m#Z8u&kBe||XV$cH|DFKBY(1NVUkF%pc;T6W3LRm5G;`_>&Z2XI&J(-+=H+mae
zP3Ep793(CwhSDdDLe7pXiTnn^#)gT@H$$jI#ct~m;EwM&U~K#{?jmBk?rwUOBF^vx
zyD4}mN0*gl=g(1Nrtt4R{|J@AMHXrVoE1N!ib1$MjDw%3o}j*#Va@nA$QEFzRp7Y|
z+GG&wukwqM`^R8pxVA{YgDjrp1~Hch_)L18h?u^n?6Gq<*h0pf6bsAd5q2gEW#&AT
z(V!rFpgLV#&O6*G2-3K>ouh!CNp~(W1qBKGcz!7h|J}VCe%$x!=!9fpVC^V;5L}<W
z$;x_=C%v1qG-ZFl&q@E#cA95*0OhmZKN|TpI=U18BOwDKrn#P=3Ln!@SLiYj$tGJS
zjWlv8!z`*g%Mt*6Q7jJlu*W;Oin;Cqi)?qV5}$m{BQxxhR<I^4;EaDu?lne0_t^ZM
zCi{8lz7qk)DjHiOR|h2ENDhB<*qP|q-DrarVaQs!s@|$0yq_R38ceNobhP*kgmDQJ
zr1XLK0yE*y9>Gq;^i2@sC|tvlnB}V*tsI+(W<M}*F=dOJFT+?Pakf2!BG126wyn|-
zz@4<$eZ&Cb^=%M+(jBSOc9qZQTQ#mmmq9_M;ZhuhBD%0kQV<IU2tgkQv~&3?<O!PJ
z(rROD*jj6GdXBxG+632`L<o6{U2`Ix|4bGb8OioH6ui>mxt>sePX@?A5W$gU1O8{2
z`^CBzAT~9|SWaDfNne!4T0YqH6W3nMgi8jh*I^~~bo#Og>YKE|TWis117VA@v!ui>
zAiW2wZF~Da>_5aptC0VIsQ3_P80_>L$RS`?ut_bhw-BDRYt_Ncl<q_@7zPzj+r?r?
zvP;r9VdVx>E<hu{h2<RK!BmCcdAee(ul?21xxyLS%$Rp{@jbKRT-@;q&J{2O+AT@0
z;XZLVTrUuWo)i3;<kPNT8lEmv#2ywjR~Ea9VIT+DnGKaP4#ne0xC6vvG-%tfP9XTc
z10EKh$W#AOgD-P9JbQjazwhLR1FJP~|D6yrBfT<Ml8Yq=hVHs4_3hjkjWgsPPgud!
zvW28B32>5|q@jWga@lK=SjDhl3Hu&&(!c~4o>m&^j8TN~9AigEL;$erv`E80eXL(A
z`tG8f0m-xNCFqM`YQTko#&v9)7RuA?=mUd~o-}52#3=FnGPj)t=gU5Xfn8m@vy#At
zdFdnMBIYj5#<fvP^Ed1b|He{J_6)+naV7TBD<z~>aeU8Y|J8qf<X}>ch|BCq7XxA-
zg5)Hhv#ue7m2?w5NezT?-^L*KI;BbPtkYiL{>P7cFn-W&$UDXTr?lt!k9mv2i3F`8
z&hZ)cf%%@dUA**xOb_o;`cMi7yyzGXMPEfwi<FNql_CMl*YGaqq^*xOQhu0F1ZQ3p
ze8?%2$;<)ZEzj^Mk|PPX?!7~n)@S@}!e{)I>Ky|a_w}UpZbqa;c)7R?#u3#qiqbBA
z6B4;B{31M-B*2l9A_y~(1g~wlH}zAJJp=Ya_Q>62C@%sVyNvC05#z&kkxl>)8TwA*
z@jrJ<)5Zc-nQ%yX$1Njfultv1#OApt%mRM{*Mw*T;tJpc$CDnAV@?OD8p2m6EraC#
zSmXfCDZb(|$}VRIEJO2y_dlYN;ZY{DfHZQ6MA)x;HiQ+OFLHg^%!o(UACt<M?Dlrs
z31t3+2@xycYnQ(VzPCd_gzIjQ-Eluac7Pm3GTSXFcI2N~oQ3umCEEy?-2FlVQJf@4
zJPt5h6a1-mj?B<gT8mrA9h)ttudywYpA%TGxaj3s$Fs1sbFPov9?yOmX~9-6na8|q
zTRBjg@bX5P`Fr4iB_s9<-;J#;UA>IgndW{o!Ra=icbyMgLDnLMk>6tMPuC{I4Y5!%
z*GG14U)dR2R`x2&FMhW>Yju<g02We=p#p-<l6^?v92bFF&_7A(5Q~(#0i0wg<9q-?
zG<F~M#qRr3_YrUmd2o9}_>9w}JE*rcW5^#&-*LBc1jow!07!BiLIPu)8^9KTkm$(T
z<=LhZP$W}o6tPpLI+a>mCM#92EIh_{1MR(>1!#d^8^Bq5*WufnkQYGotS8+=-Wfj_
zx}d#mG}N?sSIL-76cH8_<R|*mS$^veeq$c`65vXtd9d+Z0n&F*l>th`uHDQ{x2sxE
zKcGpZA7`M-B^MoWN&A3nc6_k^up7uAfhotXLzICSbXc6I2EC2xOzm5H{%R?ZyJ6-o
ziMYLlPCsK}6}x;lUd#e;^l<i))lv~h4%@a6LH`KVwxN)5Nxb~p4scPD-2>YZbY(Z(
zi=ikk;klO*P4A?ZSANEl_g+ml-vMbh%kPL0v8!}LY=`WE|IyTM!0gFZ1`=1iAo10t
z`%#%%H*!w;JhF29Gh!W@0-2w|_Iq)b!!U!a#Ch1=y$b=%T~8TtA+9FB)IvcSZ3U5!
z`kWZSW_yBo>eL2LK*vi34rhvzF3bl6zcO(G0fQfDqd;w39$<_N{5rw;GKBK-Vt+(#
zK6xRu;Kt0kW)u6!oCWeKhYaK7)R11#f9RbbFwr)wP&(aQMFtgOGqiL6%N48?Ml~<{
zG6AVymiFiY5Sg!NgpRS{^)c1oq)D6`FuSH9^B{Tfu&+2nSSx8D;1z>1BM&)=j8^x<
zeL@OS--CGH^SM?HUd_PPOnkuO!p6A@iGp(s4IE?>3zQroWsBLEz`J8-og`Pd2&!z#
zyS8KnWh`Rg)SztgWk3<wA$f-Tpu}+>?I2tUETE-<TU)2ctrPhPru|Fg$714r@lG@H
zkp&+=(9ggez4|wYXrEK6M_>iJ-X=aE3+!a15xuy{ppFDbc!RFw{JrBq@`8%IZ%GF8
zz&?1Oo*S+-sD6aY$|!kqDq7bN1_p4zup8~77O=IJDbAT^#0Q|b3j+M8?2yuXy1Ppq
zJnHGB^N`^*^O@>Bbz@4>{v-|w$5j)xEO|VkSgx6b?v8I=k+K#X70*6is7>V5xc><)
z_j#V2yZM0$r@eq6CuA!xqRm@6tNh|$_s&zWEpkj<0L4+~ZFkS$#?%w^7y~_@-k6$n
z(_wugC-TaEt`v&#$hBg}{mucJ!0QiBf}#Ls-+%+ah8&@R+>HMec~Gs*q)r+Crux$<
zUBSqpuIk+-VrVstT`v`>a{8nr!6pf}kihcGXdwfaq~^tvK(D%s1|Y6<0-qqtm-u-Y
z;Uw|#46jn%HsW4$mLjk|y@G?!HW4wJFF8>a(pHq<=5LNZq>->%u!V2qrI?Q=)z63~
zLN^KWP`bCiNBP#&nxfjgq(8=EJ0wu*B=iG_B_Q$`@&qv^>EWuHJYQ*;>*=i;PR;qH
z4R_L7Xq)CjhL4E#49B+5!r>$2zmS-anma#rY_q{<ATkL0@3<>QksxNDTPitl$fP5N
z+v;Sl=2vk>u-8KYt7a@$H%PHM<F!~WBiM>S+Hby`9TU5hd5LUi-u>Drh;xQWTapo=
z`ueWJJZ-oUCnTqQNiEJ!Ss;|KA$!70B65xIKtU_8Eqp#K)#Go%8%#k<hCP^K<JCeg
zcY6xNV*F~0kw2~F5YCMYK#bD)(B9(dk3@e)QIJuEF;x7oI;GKu0Ud0pS55y)721m^
zqQ_wi(txToi1H5#vT&B6^vFt9`p?}^6GBobcZC!u`In7lBV+K2reMv_<!;$BVOt0I
zEM3amGHWDjPG7J7+We#y!h~i!%<~+)J+?V8ujePUoy+B3w4M>7%%XCWNOrp<`+>?U
z;wvOastR8OqDzf7bWy3csc{oHtDb9=fuwM<aJhBt|E74(%yfo_YJ1S=xbGp?;};x*
zM^prO#Ha?Uwd>Wif5?9m&H_5#N08L<3IY3wrIRl6IR~(35d4+oXfU85b%J}IxAxV7
z>TLCAAfZ^GuzEvC?pZA1kv#L*m>5yur+qtnvU0Z|Izf<tJ?)c(lEmbQ^Nx!NV{o|&
zQQP1qRfTt%FDb9^T}5O7J0TJLC<v41$Vprlp50S{%<@|#AVEm(1p6!TT9YR&qkv@6
zIUZX840Ry1M0ai%RC7ll$m(R*jF<`0n{D9Br2ARy%-%U1AAA6Gz(Ar5+wm=l0{{k8
zxLU<BQvQ-P`jh{z6|J3vZPX#4L5z}JLVY^Sqlv%Y|MqW&Mw2Gsp-g>rsjgwl=A2am
zGk-^IS832cTO-?l3_@Q}d`}{`heJa36GV#%96A?3i08I@((U;c4SJJL&v@%oN%u@T
z`J?iATe)LFkx>U_%t4X?xxt;?c4zlOB<t@Hd1Sx~^3R|$<=u^x(`Dtway9~F-7P5s
zg++gmh$3878+6&~9Yo^MFpi5eON;023_oRB{9NfgORv6nO}UHoZ1#6*-63lf&bgC&
z>jJG^rhW_tIR=_S;@k?R{Sc+WjHsuqp1i^@6vra+87>c<3vvW7A@~9&`b*rg);3@c
zXSL6(wV~-i;W+iTZ1bELoffxj^wDhzWdYp-kaLGG^E^mE#vwQH6)Hn>@8)!QJt}z$
z|E4N>^Ik8Qs>@g{uzxTjuEnoITPh`a5^_bC*iCCpA5zCu*Xv7w<nNm~Ft<3J??CYJ
z2F4ds+JCm=AbhnVuZC^-0sw&=V1;Z<?cAVHUyh{$#xWTEHGncYs`loa?0eAcK4hOR
z_kZZVMrIS(@}0rSt-FbnNoG_D6tx)@R^RyP)Fm_AHu-xa{8nVyIbuo<MMmU)3wwUB
z=UH-3^0gx{eei)^D3fuEc=(GjE=rFHtnE7D^3Q+j;bjU&twoW;jjPV<xh+Bq_A?t-
zPH{`jLjxz4`Caib8iZj2U%&8G1e6k0b@(SH4_7B`iijY<0fKYm+KeAr)412F)hZk|
zQbs9n;nRhKjeru@KDaO8kVC7GQ&!3w#IMsJZTP4CH%zSzj^7fok}_t$p`aVsA^BXF
z?xYlIzv+;9br}}adSE7Js}G>#*AZ95b?7ogq`$&_C_u#1lot{Hf9h(u)V(nLcyD#n
z3srZuRvm2_T+6UOpto%3s<1Qn7k4S+3bKle{h$5C|B5w(?eE|ZxoB@lvGoKQw5nrl
zdUN`K5l^*p)-Ve~77%A84%=AT<qVHFk>}}Xo}iuqMDRE+N|I&Vc(w+4+tun1kt4%G
z0o#Km`<T0A!t|U1xGitgp<-)=wt)iWAz#S|7}`lv(bE12BRYa`MfEnJhmguX8Nm)5
zaeXV{-kxwDa_fl2+c`tekbCK-NdD*?pu~reIqlpk6<@hj04sS;aojrpm4k@Fu<5a2
zFc}?d7*wG?+SxL4M;~ZFQ3%E~nF=7eF@20-24Kpme4q@BJua!dosgRK#Bj*h^FozE
zNNJy-M?Z(R_7-*PmYoqBW)jHbEl3!5-Vz}+WQB!V0B(oa36Utr6#DMa`jlCeK{I$%
zpA0KSPR7jn*OZHhTV&P%3K~R%7GZBw8Q6l7^_FVS6es5YrJ2Xv@toOw?=iF*1H<tB
zg|8e`khYhFG;9#;r}SSIiJ8;0{Bxr^ioY}7HZF_q7~v$wQ!2(o%T5etx3pEb6p|v>
z66#TPcZ!bb{&tPd_|sGdW9-v9YphG5-+Fz0?<M_vMOzt=Vz_MIQojQ2gL9h;3$%?u
zgz|tA=oZ0R@2|2LkMzzh?SL)BSi0s8yAvP{RrSeK=!7+-2lf3ldeuBF8puVQ#%SJK
zE@n8?Bb@J29N*peC-Zbt$XFTi7kI`Y6}fW>A$n)PJVVMcy<Wp{vf|L(>oS)G0bw{R
zwP-TtSA3q2+#k8A13(Hw1;YpcW5@jn+14}b-dUs#>blajFI<Xe7Zt1x3K%dAZ#eo9
zsyu{z+8>Joz;(Mu;;Bq+YPyD)JH`cAT|K*a0Wv}<2$%jiM4+C=d1H`<=6;5GBgggH
z^VQ7F5i;7eGv)@fcb+Znx^x~E{xledTiS0OL_c(SqOkc`v<GIMZUfzZ#rCy$Zjk-B
zR<>lEB0xJq&|Bov!lU|2l9TXLhuyB-^g0>g0lqfEAtKDh*!%j#%?a@il7Z&?rTK<k
z=hqZGsOvCve0Z(H5pcM+Z<83sHAZt&`k;Q1A5mQgdm_SjBx1mvgLnS~-q-OY_`M8m
zc)ev#ZXyl#gg20%0G7BR=3BxU%f=S~ojw9la{B&bF{pdYj;viG>n;R%h-(H_Wb6N#
z1-35->!mK)f!cBEiiuGbI_>*KsTf2r#fRJs*f7QA$GPJcN0~*<4<y2K{6lxfG?&ff
zx&j%&&UZUZ&|?3=5*$w;0h8zYrW>Fd@CC<}%y?IFr;Lp~C1bFJ=q`qbk0@O+`P?wr
z)Goy}2p>Oq*xlvIO}b;^gy!LGL*#B_U4U}U4}>!CJ?GXXW#Boaw2>eAgQpJZK)MpX
zOM}-1RUOi3ID@^@4S$<rFQnDzrWb*%fjm{eiW4o9+Sm&+=T;64hp<)s8}0+vIGL!9
z`H!Xj8Gd`uEGvVQP67am%+AKbf(ynD+05qvCveIeh-2O)U*gpO0jPj-ItZ0vbtZl1
z>Dk<EH{@<b9)dqx%Hm;PGW^HR>yolWk9$9~q{xL&vjREB{B;c~ABNn@LPnS);+<y}
zV*Ly9Y8RAXp;L1PljkD4d4=>$NGK7<0p~PY;;NnoLc$zEQ};22U=_(2gyas8ZSFFa
zE(U6`G}X)NLAY$_I;+F<EIn(2lgW$McEm81K*QaVV8t=?%#tfIdxsD|4-|3LTDxl9
zgxdh<+bxz}k{b@|<09MlA#tVl$U#?c=3o`P&1prueJ@SHLO?sa^pern`{6GUfLOBR
zprf348&q$F(0v3zk@=h6x>l)LMtIU~>+s5=37-6#6RJ;H(A4cvJ_E-D#q;AGp?+<x
z$@bHy;PKYB=)~*(3ftgyD{YU9b5I0^&WHivFrGD$<b^V|Kd3?>6q31cX!R-G*mK9d
zZp0aw8RKZxKs@MeviF?3(Qr*B$-3W8py~H@!Vwrrc@&AkJT3E6{CRRp&rjRqT$aO}
z7w<X8cb-ST&TQ7aU;PF|w>ns+PUA+9GCeYkOQmut1_2o=OpLVyz*nG$M|enI%t8tH
z_c~uZF6SQbii%(epZYY*uV_z@AvSKUZ}?G#V2+*=YU$E>wu%^Mu^$1)cId74Vmow0
zgZv$b1`++i+qAAOYs=P(1^s*sIaAP%HvG^V{584Fu$-`|67L-jI0%z>=e#1s8&Dfs
z6UGVlZYeM8!3rV{F~R%F=<Fpg!l^UaU;M?_P*6D!b%=DcbI>m{KSUM76jqHDE$wIC
z5i+J8-IkO2I35~@7&ZnoCnH9=gLWaH4SKFY&<WQfRU*gI;l}iGu0ku-717{DJ}ypU
z-HNeNp(Bz$ryLS+Gy{8)XM22c6b@ss3?%ef4K`_uqgpGb+cEJhh%JcZmR`CjafT!=
zx*U&72#cI1pqG@IRjdPa4LP=GQ9n!HHwyxZEVOwa%btNuX!l_e_{)Rf1`!KO;cZu!
zwk-(44qF|U8=abt(=BQYTONmGuVP}H=jeWTTB*vDa0Pp^->v>Re7c{5pDWw;(OF}|
zy`pUyjEte6K%7=8B`9Ce@nb>yGT3hg3dO+?LV26!TLxm3ogi)@8>a@%OP0O#vJb5|
za9pL@2kD)!uoqCbVb~|Me4AH?b<au8{yl1Ic!b@tvNraBOwImn;-7><s~r>sAOs%^
z^|r)y*t=yOGXvzA<?2;2`V$Rcl%{pSx^SJowqx8G!|r*wN*EKIx-!@uAlQOhS;VXf
z0NqV}Gu6_g!SX2^ilN@zhW?)NA`05FAt*$kjdp<cb+|m+RF53Fm2`V5WD7e3%EW1Z
z6pB{_YTglNY$5!RI77M-+wUmyK@40?HQ&_L6|12hs7)|>p4sNRJ6UFDi#u;D$Y$oq
z?;QVkeTs7uY>!0#2SI!j*F#RF$8SRu4bb3Sv1Tpg5TXp(oyc9}rcnBV6Aud3bped1
z1N&5dcEy1$w9gSABd0#W5ANgV_*oII^JV3^BBCc5f-a!Byn^aPJlq`#)Hf55kb!Nd
zA5O7*Nc<W3C1{@gfc&s#Uhx)MY{2-*bM=X9!(9$R|0y{{pV~;5t%7!w#_Z^+T+$5?
zdd|!@#VUWfZK5r&0w(Ye|Fkbju~?nWC)r1pNZqka!A|4sW0%h`XkEs<ImaXkH(4)*
z%$0vN57a96Iq(AnWM6+ADsx}~Bzaogn1Li4<$4qsejTdN73}{zdPcPHoY!prxl1-c
z-a@z8j|v}!3{O6(5|t9)RXz=sbQMK@$90I+VVMd%(u}}4LAudFuE0Z&<5VCggta_n
zpfn{;D;lz>$WuhM@T8tgve7N5{n85xEbe^!`<s0|sJ@m53d;rcBIe{W)$7{26<6Ws
z<Ea%2Xk}|XGR6qKQiQLU+QQvgi6vf0Bw^k?h7*r9YrqT!Q<(VLNwQ21*r9Apm~F)g
z{cTa1lZ7x2v{dfE-3sw6hWt*$!rd*gpx)v*U^%TzzX~lGCNlrkhz}7S)=P1~=d}oI
z5`?}g*EjYw*rvBttrj%#>J<xo+$`TY$sHnu1~cdHJ_3>*{Z}Me08$j8B$4b66l5v&
z1eXa)6UkZ$T3>KRz-Gv14xk(XRifp|?G6ZisMcVLW%&;vhg5Ab<Aynk`;p>OVLM+A
zv1axH+Tfs?Q2|Fb8ifx0;qkTBN=O+LNdA#yRJ&rWfvlRli@+k>jjRDyri-yCS0~-t
z({v`i#EcWXI$>6kozQa<4~;t`i?G5D*+u;Kf4?i#Cv7(Zii2QBU{5i{Rc)=V!Aj;n
zrv_w5Qm!b%Bk0l-+W{owddR6KAAc1-6J=0HOVbwTV#1nH_hXVT@gJH&x*vP{U6eAQ
zdhu>HQv|R>`BMqOw{$LS2<z{Mykxdkv6^bbzg05^d!w?B-Po?8-U{NN-JrE)IFIlv
zrIKioi?P&EwL(wj9@tF#8_Cawy~|>?IIbY7&(60ie<9oUqE`&I7qAcTCaQ2z-&c$4
zSjY6bH3kw*mjM=?1PIDGdr+u@o!sSMi4H(->UD~dAVG|DTkedoG?`Z33A~EjO%`1x
z(phvb7<7fMbZ$wFiWQ>z!4Abt%mm0Mto94VJghXr3?zCu_w>lb0m)UX#K`UAS9z0{
z5arL0Ak2@8r5z5(+5TsLf%`@HBehLmavoq&_md%tQhF^@Yvq9dXJ|&-uLa?DxU8<0
zYPZf_2hY_>M}e^Ed~|go+6u*B5?1&+zBUBkw7_5&u?{)sB(zSQ=~1<PDE!-pd-FlW
zA_~L?6ou=N58qWlMZ(j7*p>az6%fdCP%y8RX`WklfknMN5Q(CO6Xi(KDk6>l&)@CS
z74$9XBs`161r0EqIpz@DOKK=Rl#ZvL*fYIiVID^(Db92@9>RlZBmjVmf$!VC&$0c=
zC`J#GiN?4M4NKWNZh1z8eu}du_P2f?oP$8UEm}{3y~Qq?NGM2U1F&IthRb#o4ymFw
zr+cGbpf#qVgboKm@_*d}Z#q0K2rr@=#9ybVZlq9Y=@a_v0$OXkX*U^O&_s=anRWG}
z{&nlOMteqOVLfUpQC#n%4k<juTtU1BCMtht&pJ}LYp1HW$r5tPpD?lPd@YM(0U!zu
zhLRlqI#R1C_23@^7!0MrzHqy?MUnJ7Fa7gq-D=vl6SIf*?U1m@R#Zv2Wk=VuWLx!w
zp{bjYq*kjl@}j^^G>lL<&7?A2lI>l-uOkwL*$se*8R1V=U@?u@`iZsE^m%=Ql}x>E
zwJ+iD?NX4$SNJc2Uz5E;<O5BRs({cMi{rRW{7KZk9GPCp0g@kbS3%m0s%@updxdwX
z56M-@h|=ShxqleM3h}P+COx2y>2ca7#_64?1sR6`FkfH)wmxPXcza|5Wt|1UMR^q4
z3&b_$Pc2!furZ}>e+?E7j+Rm*UqWX6VQj!4gO|lP6(R|VW8MkKG>80g+DIL!z7947
z6=JA7+=)ve%7q_(R{P34ygqzB=u<2YSX2L`Tc+j)Ih1Gca)gXmLF!b&tZ!*#aK9z;
zy@ld9e;Ju2X@c=Z>h`2^YOmu%*gSp2(nqv0f6%XdPW4;<jq0*ULVQ@jMROIW(j!4<
z-v|x^OL{uwKlGp}Z&ICM8RG#gBv|r`#M8h&fNmIcCe9|p1gW8NfI?C|N3s3b5H&!}
z@Z1nYR8nZX{wH*zaLcYE^*avWFWMY@oC626J>o=o+F?(nRR+yFh;kaRJb@f?_|`Q1
zWTfG3;2R$z5gRTQMLe=xM0hIcb*WeOH(dRlqyZ)t9BqtyS~<+f9qMga6N?iNZH3;E
zMXJ7+is4XQND_h1Ls}1#N4rk;N|Xy!p7LL!8jQGwY2?~dkH{j<-UzxYT!>^bg>V9}
zbGyjEe#an=t>gsY1LEnGTFXMk5M95q1QnkS*5@-*+=#?i-;$j~WftcC@3#9UtyN@T
zIwH}x$spfw_h=7@+*+)iLo|i*fk}D{Ze<e|8D-LA>_v`>ETkvqx_4i5%(oKYFyKOh
zsUr8cEr{iE)#3H4v$fkls(|wuL3E3!gvLrzks<r-^0QzG*l@pw)%I+oHOT5ZHwgm?
z9WZc+V04yq9}HCZtCIDW5v3!!{dxk*Ml3d6GN;!Ora@3vn_j6+5|jx!lX|SQy~THi
zFF=wFR$>12LpohWQbZbakHK+z8QhnCzzS6L6==*MS~}{`D%c}qEQC7*(-M+qzl#MD
zvSbRhk5!Gb9~(H(NACgLRDWSM%KKRX-5YpGyn}wnXz&a3cN$>mZPcYle}G7>$H!**
zlwZSbPD9Oe6J^O1X~&Qe4=r8DW4pV$fuOpQ49n`d2)^PbpyOwds$p_Z)%H!CDc@R$
zq>I(z>P{6aK(1(Q%azxU^sJ65JCV7?zhvzbgV?f<+(V-N=^!hSU>eD<V`=RkUFK{*
zhrlN6{i+Q3=en8i&BTTqYV=uBwcf~~s#gmDP&AV6`BNw~fq)eLufRt;eCc+EC+b3n
zS4mWeRO<RB-8n#ahUtnU^9{#$RmWbGXd=9X+Vz(rGG2mtg6~dFI0iswQgWT7=@8Re
zHMkH7Kbvyn>)Bgy^(Z_!r`%vMJlA4=S;^jyzS-4<(hRteu7eH-+2(OuJdEV}F?Gh9
zAun=h!nkFHb*IXl=+Y+#<jOYGS5Zq1M;;*4ZOV`Su|AXDBGuz8oZNHH9@Ed*Az9t>
znlfI>LJx5Wm&E?L9Kw`?_rSo^9-RGLF1&&o=Va<gz>0|{S)><gbrfTDI7VPqsm(-8
zf{?LHecp|y+m>|#1Hx?B&W5!ga@e??;dbejVq`?1<#sneaSqD8QJ^=Ni;k~)6gLS}
zKG>it??qYY^i{@um#`U76XI+{9&^fGP;yK7M?uIT9}nxfWS*dCy+v|ybqVt0^NnSM
z2CM~qRa7E-QTo3OG|f>$gP1+JiyU&ljhiZ4WBPb*#*62|*NiGm{XUu(UWGR!FFEBg
zm9|J34h?^EAm!@Z5EN>43hE)~hq7JA`miV}q1Ts@qLqJt&VK%09e7mM44>`){vUoN
zI|?h$rIp7@5!8_EBU*ywZR$f2h&9g1CpxqmfGgX}=%XydI%)p~kh9aSQ0AIT>*L5D
z8#8IXDYmpI(JH1bLT8nMWv7JIC?!PCLWxEb!~IM`Qu__wvWx(-Z#cMX>J~9-Na5s=
zAuTw8FQr@^oSf7w4!Hi1Y=gU5Vn+Zv%Jy-+5S<Vc*l1w>yxwL0oItk(*`VPU*Lp&s
zgV1NmtR>(bCa$4!DTcM_jNZ0t;R-qoV8wKxqE7%revU{^YS(uoQb6AcXQBi6NrBHW
zfPjssWf}6uH#YK{9DR8ND*IsjLuv+bDUt(cvb!+_FC-pUvEMLR&l)`KMWITW#l6Mq
z95P@fV*qDVs$m=luY7%QbQ{EJVlL^9v$E}5F^kpODbaf#roe~fIoL7qV^9LV*~ch|
z(hhe8YYh%0rK)mUUp1!@(I2OypHn){tI<gc?N>zHjl9Rv>KGm#bqWY~{N=-t>uf_Q
z`!vc>r<-~)SI}m>Wdv}t*#Y*@xCz!6IQ}&5e*qm`=dvNkbw_9$Ks7zd={<@%n_QjL
zpH`e#%#d`k%f-79pErw%!dO5CAe2Ygi;$;EY!q|Y6SWCcbw!%f4eV?K>A`aX1^3w<
z>RtG)TjzRLWrU4y<7-!!%Li~c=|(lb7PXBTc6B|*5SLUa-*4p+hkgR?;4xWKjqnYQ
z0Rc&OhmxJJ#Bml+-_bVVMv$TO-$8u|W}r@+%q2!p*3rzOxF3(%a}T+E&n3Xa0okW?
z2$m)+6i`@11&;9czEB)kdZ|MK0dLQB`+FdjgM0T|wJ}{^HZ~Ey=o{)JpFrw8JG#P4
z#ap3;!{(VR0Q6t}?tg=PBr<AQ2^LU;O*&Z`ADA;bUd?Z)2Y3z7Qds5+ZLnuTmv><M
zb`Iz6?ttU+;pi*@<wSDu-3T$NWfAu#>D}{mb3JW`#F#x=bdDni{ZQbU<C0(SRT2$P
zND6UXvS|Z&%M6*t*$htmAJK4LME)&~2O&!z3bZ<qeU$<Ya+DyX!VRzN#WCYwvQlR-
z6ndIHqJLW-KoGPGx}EmtpZBpO;17FP=&re81)1u<YDO#rNv613vCN(|nZ`xkTqq29
z)rCX9i%3$6%vqK(o{LjI`!Q|P!aHqd-&m)zYGYjaz!@u@7kFgDUAWED7hou*R`5-N
za!A?3N(LQKK*(eM0{#`PSnE(Dirtbc$|G$gw-+QQU=luZOO#rKOP7Nu(UIJ7d$0s-
zdz=rpL0FZ*rJ}L>zy+sleZ=3;e~nslJXjiF<2gAT_=6~d!2BbZb%P8l+YCcMM3?J<
zaR3^2M!UO6w5cycU@bOvbxT_hy-v4mkz-HrTlN<v9(Fyac<~g_>~=ht1s^Ej^6X6j
zA$qob=*B%r{vI819zfmiM_O2jW~f(=02x}eH@FWO2`C{zSowK{2fee#1H%YPo;$EM
zL0(rYHrzA1$~NA+yU?j5QIz=IUYO#Y;6ddULwE_>LM~gzWqWN2k%1f%$qQ&p=e)9C
zW!D@mwjAnih#^3-wh0X*{uzUV%9t&aqf8DwE9!}5#(rKts$~vh|Bku~Z-!;a+g1O%
z;X<7tXzQqejfViuwUEuafT#yBif_8%<E1C=d>U(zlKN4;A3**%sAlqyUpWm@fEC5r
z3%k%!qCYDU=l=kT26EEQVV~=Xc5aXvIEHI}ewEFom;pzUhZ+WTNf-gVJ_r=v<3c4)
z?IwNOid!q|YHA&^j#U?{&bWOa1s}4?{~*wd6o8EmQio%k$FPlI;cLQqkU>yMDcXfM
zR`Nc{?#h4~lqmG60mK9{$GHJCny<U>xMlYNFW_GAYMVq~FSn(51D>QQmPK<xI+G@f
zwlR##?;eza>BIV$HwY{+stH^Sha&2?EFH>A>#{)3DxdA>ZLp_6rea#(AkKRTDPf)g
za6^~PTV|P~=FLV`I5dIpzcjWGmr5I%Jit=|kRiivN4)}CpbfYriA_=>U=;YU2tuMR
zci4onCVCA#+5-KpC2jTz)HT4PL63z1a|pfx<s^_-x}jVQ<S?o{_EsI#6Y>YSx_C@L
z9f%#gz5UY-Xr<xjJ9#(>U|gs#<s4+G0Q3v$&1wH8+d#4l(lT(<VXuI*kbE&f42&2c
z#^B;%-+pp1;g&8kL!UR0*pDpNHbo^mX^nH}vC5_QP`_~oEbem(YTy_wnc}(PoIq1C
z;&S=CX)iVom0GM}_{kR0Zpsn|$n>|T&{bM8Ac(0J54(Iv)h^#8$x%GyCBMXjS6A|>
z)EVo2%%O>7R4E<7v24p(L|3N&{TxEL5YOThRvB{^#foz&JRQ?VKd%}f{^|tMY|JIn
z%_u&||C}8OA@;!aFzKM$kz<7R6Sm3LA>6`Q8%o8@g7td2$Y87m(js*WWu3|x;L?Cx
zy{!BnY_x&-Upf*4Wr|W&_c8#$OnQYkSeZd(iL=N!c6llG(nZYQ!%4h+IO$8dq-w_3
zU`xz1#lkJZA&QVYk@2`l+w&j|A@`M~pOWCe@BVKOp>&C1!8#`jkR4V9+DdHeDYoC3
z&g6dL&OpOIxWw1IfRd=X$?kGqly`?U!>YmXA~Pks-GCGkGv2ErGHd+IpUfTO)+jD^
z2Av|ri&TLav5w3zI_D-l+hk`e*w0he#?wI5rzlUV$J8MjGwEoBD;B?a5rhwhr68y;
zN*$YwN?k#UEG-?@hY?od0;6qGh$G%P#V6OtArQXE@yMd??0@{m!AXnDj<gVT_JO;B
zPXUyksI9fR6xE}%C1}2JGOhLi;^bzXs?_R9(CO-yDfL~6T|{c1i&ZQR83*Hfvs$~S
z&yuE^<^@xXT9?kEND`=1GCuN=gLA71<SP#Yc>17oK>MvSI{}_wGmcw;@D&RwPS6QU
zFXbOYjus&ZE+;#Ja4Rtf!xX8fMA4d|82Cos5@Y-WV5nT1?~Gk2C~?TZvDxe5{@?C{
zVrl0S2uNfY*99Sh#L<X%=@sbB^%b(IFW1odOVigm@=T>XdLRHxgF|pQn6Ki1-T}E7
zA6VSnq&uGW)>W$(V?+GB-W19P4z%+$h%YoE+pEBq<5{$Dt*gk)q49|1WRQ)6ydsj^
zBl4RJ=1>JZ0KW*c0Vgb*t00vceHRmevq7&@JZxhm=XudsTgh#R3`>E4In9d7i*5PL
z8QB~I>Bi3?ZpVPYj&$;J9tUJ>QRr->^xnWmFaRsZ2~dNfr&$Q4DU0YSB=?02h5!Ej
z!~vdxVAq82>}gJ;-lmH9iv1s3M4YEdegn#im^c%Pq;Zze00B>^>II~J0eZWJIxkCJ
zP@xx2d7lELoY9dyjAK+t?}$7U#l=GLl_DOwj*CgX=OMQO1KP=DQ5^9xeFngU4>s)v
z3dYe5P@J*P3iFGSb1ZuvT8mH<!jbRSw}s^BWPy)_49+R_G95%{GQoZP04W%`7Pw|q
zx5Q-NGk2}n9nMOe1s5-atsxI&30>O7DgZF^Avi*LLAhOJ(F3-XjZ5?E2#=IFT5=o|
zF2LaA;D%d*0!#s+^yob=G+0$!<ay(w0f@aMAV*p)b_fKSnp+HEwVVcuOf2s5j~Fq5
z77}ad??Behi~2gN13Z+BT|38+7M4{#N%3b3Fz=}ImkdIOOJx9q@ZC6E>aYa?{waF0
zI)(6F8hCfbO4869{IMdWQIb8EeV_oF-%R{o0ym125AHh^-ejem%wL)o4Db8_xMUkh
zTXr>ps2Dy0-C=;&IKs3ju7t*@YDXD#GdFmu`mk`Rp)Om3^@P(*7&4tN)n%ALf2XAw
zQ$aw(&H|t7(B|q$H&oM&Tf7N<SyJ4BF_VpNWT(0_+3fjncXqVXaOz9RGzJz$c-J!x
zG*Px8KBR>jG`A#3ugd&MXHp$6e`z_ol_y;;Fla-P+w<I};06n1oUX0co~^QV!QX|h
z{g&8~ajqyKCQvt=1#(?PlylgvFc0LpQT38GcmTZua#i0fKS|t0Zom}&JmQmh3Gphl
zE96T5fQt1UresuI$!(^Vtbq7{LCBjH=dob8!dnRM&xq|dV(-%*#eO|I`ULXca>+nr
zx%_x7sJ#t0nzW2f=daQkuuTtg1VxrfH2IcvOedPau6Lk09dKC!AP%w}l#W2y&OuVA
z8q;;nwr&Y$hTT~Q@rWK_7X+}mEFF=2)(DnN231(E!8ZZ1@n5!9r|O1^nhE`;7Ngpf
z{v;bMqXE@LU`)w`yP|Yo0^CM}mQDYbrN!)FJ>TNyI5_qt{=QhK!*eK0I9u1yHB<h*
z|0jQq{^K}WSqWnqV+4QwW#KPd{;TV2SM_`u#IzUT7~%_rd8md#NLH2{&TbS##!*)n
zSAn0#7{cBBJ6mjR6xH3(QYKAVw-lB^_!$Xl@dqXcl4DsotjSUk3}{FN9gVsL)X)Iw
z8OOXRdaUMUPq$EhFEW-AM!{oCAKFR6!NRP8nfGO?*NtV;uAzCxpHOIL@yzxn3VWr2
zLfG^tH}L2`q+Mi;(KUw~MdV-RQBg*dz$G)kM0b0IP#%UCU9uD(Niix#j(2E_!yy(y
zEsfX{`VFWV>vkP}5zXxEj8m3q%Jy&w`MQT(e}`6KrO_Z$>eV}Kp}-3plCvyB>(g7p
zbK2031IEa6Qi^xKgy&MeFLC*nWaIC+?_8PuMzB0$=SD=nq&P~u6wp|AC3^Yp-+XP=
zLInGe)OU3as$3FZ$ksJMa<47Zvh_k0i72u7k|7^Z3T*3wF_wXQ&!g5TDr2B)p^>`f
zm5qd@cL(`rPDgf`@3yhK&=c!S*6hbK`+_bh8N8o>5t5AFuyqr0(54C^U$!|57+3-s
z3|tmavPwErDhohwb@+4{SQWS@F%?WfjBJphB{|IbB?;Cu0`25bO3?)Evv7CdYaxsT
zA%|=mj=C2Y^087+yH?`bKCpT$n1&&wB7zW&xta{X51(_ec*)_=F5+Skgj2n<+iDM}
zrTwJV5G|IA+err4ZpYcjtZDD%xLUug-7xn;ZgD}DLqO{eQUT}Hd5<OCo!)IAHo?-!
z@0EBT_#>c-g|N?srIlFou8aR5(S=*HBR0ws;`ENXQrjXokJgPe&0=Km^y?f39X`#x
z|Ly;|Pk%(JeK4#K-3_o=C@4KCp&$BONaqAb0NgD$xO$v=8gvQ4x-Oe0Apb4v%R08!
zUvYfX%{<#+^k->``PQpr{$bm^^JlZ{XD~^~yv$wW(oXclF?MtGR?2qo&Z;4UUg6<O
z##4|6)k?;ZA+H+k4I}a#=Z=@N*m=Ny&;oic!tFvOP=?!`NuSbggEXsC(8>IN;gT@J
zminHvfnGCjpp7N}+kf$uK8jr@Z9?BRsDmu>EOGZhhEIb2O)tv4(6y{AauxnXk-z*_
z(Ip+H)T%=Ug3Oqc_{$U+4&6vwRoOp=R<)lo<?$)B#jqi!G{;NtJjYSO(~+J6aIYd(
z+||)@fO-vBpBb8O(|c#nC4+`VZ^uV?7w~v6m{Y0tmt9sW@P80vCEVhvHX3`;7>j0%
z>xG^}`VA)2z~bx<oM_X9VzrVIto~+*VkFWYyg&fL5JW(v4g`L}h|>+t`oG9}AK*By
z`_6N~z&SWp5^`>&8ev&92k0RN!Qf!3XcwGP-En#z20cInBjG47mZx=0Xh@Eh;K5=c
zKKPDxi)lT!nxhe9^2WLmm!*(g&<kC0*P;q`K?%1)j@zRV3_-REQNee-3&}t(*g-ZF
z3(+wt-sL{O2IWn1AVtY#4$!aPd%r*5-}m?ZWjd^72X@0wI@G<nGd9sB2TvjhQLv^f
z3ED^p-7T1rRNtp{ci87u(2O&TuHIy0oJfa=g`fMlSRn9Pq9h!^wA`r*A8g0eiQi4l
zWTb|zI>vKJX{~emRkmdaNM#pIR8n6da^}yy;b_oNV~&jVtre<B(9m>M*E5ZN{i?ce
z1KPpF8S;MA8!0!1?w<eiApO<F5WlB`kN_qDgf71q69d`jimG3-2cGnu5@6|9b(Rqj
zL3w|-5twn}-fOy{vMcmT=L)07_dQ>I;I;I7xkl7p^ZxccoWN668c(AH5>K_YQ)SAW
zWl=QQW3`uf^E0(>WOa_4$!3Ra)C<Pl@Dsu#VGPj))md&}UFUU@l&AhKqmb7dqq=Xw
z`&%8EsZuHzZN6L2b9<UOZ*t<kVOSw}k)9o0$<Mp%Hht2Aiub1mtTijqs6=fl@uEW&
z4t2!Lfvct(Y0H>2z`H8*k@>)>=d3&%^vVnYm}TuesTa!kBh`25p4}DY58M$YkEW;)
zYCE41?}7z$2Szi?u7Ez731h_^HR2hL2le05de+)k31rvEHDX1WfFr|U7+;7N4f_LC
zv{0t%YlU9FL+e*uF;3g9<{VH%`3BMX=}$)Hk#;23+xpG&*dojWc(HWG4&yk@T%qdD
zxJOm`5%}B+9(>L!WV20J*>LzRavQ{)ENdLfJfVZiQNFD`zv&MQqM3TFJgQ!@UTuu3
z4`BG5@589SBq~ejMgbbb{uGBBr+Om6RMOXw#wpKq28Itb203ji&y?M0os>Bgd|6!w
z+SP|`5l82(hN!1qtK%EhW{rxCP}+t_1t_)bie|ADII2%Zmk^L9jztnyD1pS<og$t@
zLdEsZ6;LoiyB5EyI-hhiQnBx=u;!si8eojtfrLrzx8pB_p9qKG4)4>?!>l@55GJ9j
zP0aa=?|XeG%Qi|<*<Zf*G!gB^9h5CkSqZ|BUEw5`6VNdpzLQ5B#+`xE1sYjHQLx_a
zr%9~lsxy&nO!%<;uxa|tv<hER1Lala&8dlTdd<yWl~;bx!oI%mWy!J6zBYNjP<%0k
zs`$;{4sjeMI>4)1aNI?$(AEpi6>ErBvQV3Mo^*zFhBIl=0==HX&|=GZ?{wXF?MUto
z6C@cB#!}B+)7Ml58NiRL1KiswT`hC|7b;n}h_?Zjc$F`*p01~9W83nn!XPrdj>K`d
zBiUU$nt1M{a~40}0wD6H2*u#Mu^7#}%rNf4;c6f~Zc#u=p4T1LgoRR`^OEOQHS`vi
zrb}m{r^T$dw?KOY7?<25XbS?c6^qf?jHy29<5RQah3rX)Iay%UIj>4LNJ?Y}F}(av
z?j0F1GT}?U*+bF1mfoz_()X41l77{Au;itFj7#(0L0&J)KJAT`al(v%3)8B-SDN<1
z595W-ajFC0e0y&0A?Bmm9aO~}Xd%2n&TjCG97OSLPqhUEX=)^I`wgGM+%<nA|3D4=
zh$bNn$my0o3-uRl5-WS`{^dQ}mD+-1Sy|lC&D4O$XLV`HcQzD)J<dMgW|cy~T}S&2
z-z(-8f6@xww(HTPM(|6Fw34QmoN?ZzI;3+HltvJM_%Si`yVm<V(dTV^09*zi5e^9#
zjpj=_>1c@SG1kb2(drZ-GzscXIwvysGV-E8VNHihurpMl`c6=b6(OX7?tHmVNOgof
zwe(FjrMGpcL&mbzrC%<mW^{1|c{0%!gZ=Q={l9bSfG+`U0Gx;RKLPWLZwr&rIjQIM
z282B52z@8i5yS3PcCRM(d-HJ{p9wKd;Fxa^uU=Nu%^k*gbW$J4Oj!4okBEu3UO`_M
z3u3)Ogz-M>8^nZ=4lopuZ5K6p1nY>tW9^X>dfr)ZdY!IvmpXjH`LJz+QCHOp2oqld
z5aS)bOHKv0I&5C>Zc*=<YqYQD^`^O;Q!Os?mxSsi3_dLse>{(Z9s*wgfj@2AM|oF-
z?bNVu&snkMIs(H+uY;+Q(jMJMLlNXXBV2y`qa+})9d}}J!RJiC8x9mGVD^D&|Jx<2
z-VhMidgc5FDQxj;ys?C|g1jgJ3JgR1FAXP&eVSMkfWONoT<$SIxciz*H*{-E2#Ks)
zu!_!$k>n4;jPKf~uh%*X{mIVt<bpjvu;y3GG)Eq2^k+T7C20nl_~%Wjr=$r}D(D<s
zR&t9d5JRZdj1%9?)Q>xd-&Ve($dm9Z7^S&rnnM8mEk8;`pfmRX*Tk>7_IhH?g0@r3
z*_(bQ&|@RdT6z^LRbF~w=Vs)*+Y8``xC#fb2^p+T{isQ_8Na7>4>#+)Xbh<1HL+Hb
zw^jSCHxPXymWgrZrJn|b?c-SA9V4=>ThGv>7yr;$7x9;Yb#K$0$p}}66SRa<Bx7`1
zPPM!e{nOmG{gPD4eq9$X46wQaqtn^VjN6~jSu$)O<7+#r2n=&s1ZO1e!Gn=7_85oa
zh7pTT(!+J%tv%1Egnp~XU!6IyxQyNHyH@7sy&vhrFp~I2vF)K~`(7z;kF>>-EyutB
zlcRe$72{YQ1HdDlAPlIw28#id6H~~-VzC`<Vm{wi3%cUCZ~Il#f7hcEMfFK%Ue3CW
zVqck_xTn2S_y5yaaGP4BD}K6J^7&4Ku0Femnx$@su6h(t+v|7h`U*FbCj8R<O3>9e
z4H8%+_Wasec?(bveLZ8Uu5w9u#P+|pUQt8k4=nnt8eaMZeZLwl!VxH9-ghI<nGw2o
z0QL;bYI>g%Fjm!aZPBlJ%1O^vTTfqnTx_5CMI;|-NRvAuy+uyxn%k(^vwn~FV99#f
z2gP?s%QIlsZ;*`ugHSEJy5qNRs2jQn{gyC;CKLr)X)4p<?atKt*k2e(nVy7xB;^QQ
za<KY_hL*|Cq9h%P9i%Ou_L37O2efa`TH%_jSJ$fci~E3T-}9!tCwI0!zJvx?3IN&z
z-z^qNGY$TkEoZM-B@GQ-w|n!bdsE#Re7%)k4Yo%d{MNtu6J0oQH`kp(5BV91uyTo2
zcWU{*C9)e;(xUgPA7pRCuON53Rs7_}e*h{ADpdOepmsOVD;UqP12=4~Fq*NUwUhwz
zMQ5H23*=u5c17&Io5yP!*gMk7CnWH(dNoyLHmkI@1V8_ky64_p;=Slss9Pm|4i<6-
zi(cfz(N>UWtb%1RV98rH2Yqv}Y%1xln$acZxKt1j`fOp`U8*2Gv5(`I`$UO}S`L5f
znD_hxzuvuc-0GZCD|*U{&g-kuy_GC@3k~Vs&p!U$A2<IvSXY48cB*ZJ(^ecN#{!#W
zw%a(@2X%8;nQlcpT&G^01$zPFVR6atj)X}?ps8${erA*Y#!1GB)JseD5O(*2rJ$rl
zh_&;5{o3YETE(R!<)xx7@(o%qKH92-JtGe+U0Ld^`t2KtT7z?g*51y(Q$fh(v&D(U
z2;>xZpoD>42e>ZxSo{3G6aJe0Ko6H0i4AKvabMHPeFkPFpCt3Sed4!%3~XHFOUxmD
zE`os{z&GwwL-o%4N<9zTT&ExDw~0M5PiLL8)G!I0c2nUQK(GcjjYUG*>rNE#QZqDT
z_NpQ4`)VB=Lr1USl-G(s(=_5i!l94s#ird&qj;cBpUly0kbBms4B00MVIlD%M9EnU
z4kGK94Z~qecg^KgviZ7`viH>%XRVIHP`SQpO)X7%B#-2%(U+@_NfR(2{>wXhe*d@V
z$fV&9d|jg4PIXq404ZRR%<Im4fj(!wSn*4GiS6=krLIQ43YSxy)$U>w7_@Ov?lHS|
zz^vsG8$`EmhegDetg2V_q`C>OfI$+kS_SL<D8YLaPBpaKCUkZWnC<XtAe89^J!>^c
zgf{FJ-kJy(c><cUHp#q${{XkR{OG~I8R5w&LF>UXxTN}ulU;xwZuAZ;<F^ovylF*y
zE3e8?EK@nZ|E-lE@+bBWO33`F0cGknuXAN=Q`IOscO)nzSY99Vi6pRiyqOnC**R7`
z6gzk|d@&`q6N{d+ZXVgpWaxo)b#8rLN#a0PE0-J>PA_LLYD+HXG-nxY-ir|~8KECx
zLV2-QAyzr7=(F(>-qT#S;Gy=@S}U<|Qr*eJLq8IUkeqF1s6*og$Rym^=!|A;cjyl$
z9}bnfZpMsu5<<hQGmS<;6jzxc-D4mRXV%RUJuf!w_ll;>0wIg{w|mDWCL3+z)HD|7
ztYd26%2LvscYIZ90hw;O5OqS>{33B;sFe_E0GlyKlUZrj8f?_unx3Zm8hwLP_K(aR
z-}vi<m0Q)hhBv<Hs~K~`s!+ZiH-bTfy_&Zv%e*`BC&8>!R$<UWDjJC#ECNE;IPXB-
zpjF-R>n4f?T9;mkG^crRuCkPGZV>+y={m@rB(9(nnoo53b_-W|LEonTn8z*?WXNu{
zQn>e=xBNM<U~9NGpqL9*)ziO3xAQ7OM{+@e*ns~S#hekXZ;M?Qd;*U_;Vxs$xTRT@
zLfDmG><(x!a}KY38B~Sm4k3yHtx>`kF0LxT6N2Aex91>*a7Cyo$S2T*+Z(}IQ^eqB
z6|b5Xl~Bww&YBJRGtVB?hzt&gzvsJRu`R-OFOiV>y@5f$thhw@Tw?g-9Cmg{m1ez~
zd~4TeR30-3cA>n1f{QrY*DgJ}%WTK^lTVw{6#}_#JrP|qfSu4&hdsL+wC<b#?HBO>
z@?{wkNeUcDJ&LTyDA+xP0@&5)o-QV}l%lglQ8}VENrbr9B3+WaoQice)1IAA<qB7p
z<W-ffSp5lRX!S}2f2vYO2nw5n)uv!J{W(Nr3?rGmBJ_|FGg|yov*$T!@~oUC4<7`#
z63zJJ?T^*WxOvB5INH3v=FFS?{d!g>&XcN>JC>tH3nypC*6SxE!#opSi1e7btdHv+
z8ZgXZ4Of^VcaK`)q}f1Cu=a$4#u6~@;0l0(h$?Ao(%sDHF2DU`{d@Ww##S%IDz%Jv
zv#kqc&wGQ00e0<jYBYpDt(DdjvyF6Qp7UhdE#w>G@{24*RzZNin{v!8YGXz$RO;17
zZRu7&=5>`jk})ujl=4m&tRLYVUTr4=3$_3Xoiev|7`O6lz^!C2RVLa#{Xx6KsHr|5
zzfK2UV8uB;`~+*@&)SHZNrU2Vn+EBRX#&D;*32wO{1q>iBA*=GL7|ffnN1)VMT0K|
z1AupLWD5yE7vE-f(!AfiC`m?i&3dPD@pVSXaTPe77*yJn!)Hc-o*}IeV?3#t%?4xq
zT5Th-0eYR(EomN6drqnty8Gq-BlK`3A|Q@8r=y@ol$Kl@pHzs1f!oyF`aMt)tt1)=
z09To_!r|aR75~tzjeOJmuuYuvf|HoFOFN&arLURPV$vMG*171})*VRr243aj(*u_u
z9l?5fPV&BXW?XOJk!f6!2m3Q}?soPwCmw(iB&Z_?@p)l6;H;vf5bGRINbX1OP18r#
zYR>Y>Xmc_2zQt9>zlCVJxTG?dz^Dd%-8b8y_mW%DpK$tWD&1m7wFfg%pk)b|q!$e(
z-peUgEzm#L$2u_9L-AoVV@}vl)_W9tY8P-2^Z>k}xvG%EdB@_l!mX$DDQxPj&xS46
zhr!dX`Qs{mMJ-aQ=2e|;Ab7{6qmJ@)+t==e&BvVPft9hA!*`IPqxiH&9BpixDjk7X
zmJ)mP=l}c*lBUQPO8|r1-3-lc&gvge_i{_D&TH(P<T#bmFH`SC#AXCXDt?Jb?r8{*
z%{0LoT}!2FCg+LL?}uQv(#|R_?&tPbBk*NoG0EX~vjEF#ZN6^W%p+6TInA4#ChM}A
z2OmH8nPKJR6`N2+<+uWIF<EGnsd*0XsXmdcIF!w6i*UuglI%d}i~rXn!IP6l(tIy{
z6`2~2e8}msr_6aD><Plfz<I5(d)cdz*NNZ>p6IGLGcxc4^Ky#iW-j><sPw#3FtQs-
z)V9Z(OH7?8buLsAV!4F(Hcj{C$DFmKR?W1xLg=*@;m4=pX+||#1-m51m4FUTx!j1W
zVfZrx(%L40Oplt?<2R{asbz<*X$PKFsbIagP{zb$TexdIN4DO7Xg^8jB@h8T8UkuQ
zg|xzysjGyy8O&8=&1!*>e^vL=8p6-RSW0@DJTuZ2VFY7rSTS6n-*E3aI{AS1xVg+9
zHv;C2{cThS1q0(~h=WVcM!rr2ctNLqe{o%bdNWwcYREXCe(Nn=$fBz$XN`Y?MSY1n
zco^OvFS#+Oot{L&PF8D~o8McR!?fzef@Ut{8R(R^KK*UN9*z}|SrIcUEs*?PGb+wN
zHIq|Ma-WZ3$)9WJ0Wa`#xojsLqa;*PK==-|Qb9wKkq^~^J5|4jPK<G0yZ!)5jpgqU
zzp#z+0_4E}UIMa6Q}kf08Fb!<q%dm_+O-bV{=if<YUN%OItn*VZUk29Dg#c2M`Ccj
zsN2zVecT`P5d=WYppf(YI^|-EJ5k*Y#`4DR?r-L90FFUSGTW(~n8R+3P|csIEoW-S
zGqqS<qc-Q93r4l@Ja{@h#bYN%E*&^1eg(rhSk75bX8JzNi{`?6YjA-Vbi$*&nCNWU
zO|^}jpEf|cY>75(&h#w;TCYJ8I&L}45URG`(DF?Q_PIE%!6=0JFa{5BdWk+0U!#xq
zLl?b>gx^@EQZcD9;-|A;McHNbgU_)GlCBeL02s<a#4ht+eJgpyyIh6KtC?gB{C{HA
zr28|KScnJ%Ubs8RK!6y3eWblP9;Q0mcQ2!tK_9zuHkHNUva57rO3$8wA3*ZlBu2$(
z4h?H_h7*JcPN_<=Kj}-YJ7;<CR1jzuZIXw`gN)=PY<u);G*6r`e=~buxm|j~KI#9^
zL|fm=<d)_<udkVDvly~Joox9m;NxTvtHvE^n8$n7u?W!<>O|%Vr%T&&-gRBN7=0rG
zZCrL-l9#ubFR-Hx6%Z0euajKyXrT+`#e(pNV9r24EU|x><fiSEb)(5c2ILoWItl=9
zWm#VtUu`ErU@h_-hGJbjb1rBR2(AU|>3X{LHc%!Jx3Q+KX=xKJTr;Qik#Vpnvs=CB
zm;3f<;=mN~=iUGNyP=0GF_O*Fd&Ds$w+9QN5}ZNBSt&v)6OWHSZfN2-OcfbXH=|@?
z^zP;jNjXRp)(ZuDqVVjI_BC%x|D8F5db`)RpriAZcPfu_IpmH@a^AWY`<Tnek>Pq|
z^t|E;32gw*()8g;H$cJaPn{K`6?n?x&)R-qewRWItTj^%sdrq7z6i}9heyBH<4-Cu
zH2?tby$YTN3l!@4e$$ry6>2j2AKNUCBM@IpEMzLcJQTxgux<FMgrTT1q9Rnpf#5%&
zHnpbcN|UFf^R-m1<qS#LatRvw_%Zq=3**>JpYdR@n>?fZqP`f;v~k#G8#Ah8%;|w%
zHBeAWx$|O!s&ul7AtoRpP>2rf*arU*$^ow{Ar)odnh*C7`=CMw@TrM9w>R%@dh7rB
z?X5*@Z<{w2p8SsC>$^@}ElxR4xWlS_PH`A~PImSNl6CN<2%0fibc6MM9S14cax(Gk
z9`3s#jcc1`2Bx`{@OrT(XU`D@<Iw~<kGA@zwH20UFivY$dC4DaEFLgDa;J5Ri2`r#
zz)T0Q3d?}}1zgg8iVD-b+3UAYQ5K%^?-<qkONp2A0|_?2xwKHhcl^Kq26Gi+APJll
zi7H5)E46_}=9sm(HjetfU%P8kebaC0YNXXNq)$(N2=DWSuye5wGmVuSFWB+A?inv6
ztXPSt5MGJrD8%o1_nIR$-E`r=0N30cfSDw~-!YxDuaWwtlUTwTeQrJ58xg1R>-_p^
z_;yT$?_(T}b{apeZ@JqpES1I?)bk_(QW_UP19eDG?ETG<G`t}#1hg0<%OM!g5M|T6
z<Stfp`exf&9_N%If?T&ml8Oc)%({SoXyUA(T*`qBb&lH|iQ)QkeObj<#)#<0Cv{c#
zfmaWnNu?p=fvzH;mKr!^G?7RHzdoD!j$7KW&MW&o?UTBp8I&~pxF`?tH7!wX*V6+x
zq<%SO#A{$?b6(CGPa;Za*b6R<p>itQBKbO=#%j6yUf0$th(=;viW&lnJNM+mR-MD&
zGAG@&!pYhS$-hlP1(@>~_f=4Ot~p19p|@SBgSda=8!G)kqyC4+DYPB!q(@C9iDZek
zt;nvOX-V-2BE!>~B(Hh<hh|mBYKw_P!kE>|I<>vITH<n2BInRaYc$_?B*~qDk*e`C
zwSHr9!R^gtzNaDQ(bv5h)HClcWkNdG1e%QE)cuT~0zT$o4*NNE1z>*J=}(A#vT!r0
zEC|J5Q6jnkpa3NrVOXdlhm3U=?BlgAzstVsbGm7*;L$_KX2TX^rMsH|8=D3$Mz-!j
z50$<ytIM*ll!ui)YYnS@8E2?V9+Mt|kdQ@iSUFXDS<&q{QqyasAq{gGr?$@-#=k5$
zYsQqnqDaxx?6+zO-8%HShij4ET)6Aa@isoAyMTC}ZA+>j;tAb4S-n^$k!$BpV=%Uu
zC6w%kF)~zHeBY(ZUw(k-Zu{w_01?S9=;yQ9YGfDL?RMISrZ3|$r@^uq=ZCnPRXVRs
zNUG~rf_^!pvxOTGlx`t7{Nc!@M>7(nhEHg8@ZBEts8?xIt>I&Ck>)tWg=yHsxxp_m
z=v9J3BqU*Qg6wzZ73DGUFh+iSSRdXNK>La+An7o2i|HU(mE0d#>tbKmfmW_k`=q(1
z)~yZefHCOz&^0yh`zpnXM-?x*qQas|68%O|?oxP^-63k3PFOUQEwxip9!Ok)d<`7y
zC2nUEr-N4{kw_Fp-MI0BX@<v?Im8|9&y$I$GFlgku%yI7fQ@K++TU{bSO4e3JF!2Y
zKgD1;ci{TCG-IP<<Rgg(b#>f73Tw(qx6shJhA8ab3VAX1iE_x*Fgk=g!rQptY4rNC
zPimv9Ea7lZew}a$A8}uM_U-qo5ssDYV6o{SJ4p|tZ&%H9gNI=mYighJK=Gp`CXr%b
zIkf@~N72`f#bUVP{2&ywA()2!g$|B78ZK^nRI&9i6({wRIyC*sga1(s6kqTl=vOh&
zxEQWGLzzwyNjGjD;mYO=wPy`$Fz2bk$KTKo6F!0-?8uJxy`p;@v#_2$IJsHv;*e^*
zj8dZEU5M^t^H~5E3OvC0vZU&v4AxFMNe5>A#Wl6FLhh=wZ$6IJYLI1c$7Lz}7G+YQ
zOpB-~BSY<mIj9Eh<8_MR0F=Ii`=W;x5>>xNL_>Ob{F$w_08fCGpj-wWWyp7*(8ueU
zd1u{dt_^9$WukQ*#VUDKxUbGrP{Zi05HNkp*|Ss|xK_&>wPCMz!P`A|x-~|^Eq#H}
zaC>oYc$$|qtO=^;bd5MGiYX@60li^p#6yVr*Ny@c^)wkV9RS;gb(&$w*Xk#gUmLWK
zdYS5$m0D3ZBA|b-zxMFKLnPapYCd&CwR+^F>o8lP{;Bqv+{M&iA#`1c4xWBkunBfN
zJjw`+=Aihj05#o!I5DL@I&$CD{mFd4l1y9%Q&5eQxd&7m<v3wRTXpm9Syi(aRN_k6
zjj(qxcUtVgOrdBZUslK>3b>^fd^r9+g-QLI3rOy?H{5<T=qW;nL_+@R#A}~BbwJ->
zvI)Ng8#fG6Ty)#aS?E>nKFCs{gySSZ|24;#S=-oqK^ytiMCrUM(m9)=#1-pAfyaHq
z9rO?7P-~od{y^LNuua~ji#YNVlBAz&DZImMVGh*}4;hp{963SBMGyz!O?<_tsRkX?
zPaUTtAE!J$c2X-0JCuow(NeL9S(Esnb1g2@C%JtzpO}x7!1&ZgV$PdT#^!+iuJx+N
zcr;?WS0a9i)|lH+sQ>(p<~~KQS0K@IfioahNcy<n#uDAk7ZPdAE+hG-Ofzo{(#Z`M
z>@}k(sdi|$$eynmscjH&NC)O!IHn>K`DA^<rvaDVEPuXi-E6Ek3fZM<v=wD!iYQS`
zAB~6|ah8TsQt)d`ukJy<VS+@M^`5MMTH{}{LQ!(;i)Rpk^u)ZdLZ)+=BL^qh0%9|$
z+UQ`FR*qb;C#;ix>-~XJ>ZJyBe(&@`<&(<J*Vf4*qlb$B%^4cnngfP&P?AbUSRufB
z{1P=4v4kgmw7N_i(waM|#lu$8zqE)Nw-Vj!=BO}72S~>_#l+y)F-qp+AU_#0*d7Io
z7XGQPKWJd$%I_AjB#{4tS}!f2sP77oCk7WQyE-=Ie6)vQmL16nMnvB;P0-+MftsUG
zPlbpT6Wh>(;vl-GJqEYk87#*kyG%&)!NlC8`zvEgSIX~uc4OyLs{b@3*QdNL8?8B7
zB;Zg8^*%6q&7{KMK^=JpN-Si?W$L(cClvDmagMqV<ZGX{7b-iN0hM=STRZoONfKi}
zP@z^l<4@#onww6hr%-;jt;2Y6!&_}YAopI!EFqN3bV_u;1UF!Hok3NGgTsQlGv1In
zk(gbY$X`**8In*ZO92yjmVk@^iWo$4ofrqGBi2R47O#PlE2bM{N*nprBa`~h+{wki
zGo5$+S1m61gL1S#OZ#0US{7FKndpD~`cukJX%4+q;I514$Tll;7GRQw>ikBb;?_US
zs6lJk=lDq76u*Ft5cfnfLy7U@*r^nsK`J+&w`d|Wz_yP;EJ82w<9k-Q-|KI@;-x<D
zJ~^+`TuK^=sh)~rUU)yb81DU!;f)$S<7>Q8C-W`$M19P_Si5VM_j7eM@}FxZL3Dj6
z)<Z`f>L?vXtbJau8tdcq#NQg9tUvOqLBR@3e~Nc&|FZabCSXt=`-5XGslMi|{vD0X
z8PuXSy+(LIMy$u51X_9iq<bgPVi$tY3)d}ScF?QO71`Z%9UA(k<Xx)9ZH7A%x#v4w
z{^1k)?C{I}AiLLhlPcrp&PdMsb{T!97nzf(3D9wRXGD@(0Ie>+Uma@@8##*$SV@()
z@Z8$T{?d}Eu0(hNycxoQ^~C2#XgzQ1Tw=cWjDO6MqkYmp;h(V9Jf5rp{5*MnGE$%+
ziFf(M`tRK6i|`-(FCwPxKs9eko6xdGDUEjFg_`<dMyh*GmZrPZW~GwmP86}G<e^s?
zQ${5wxQlS_GCdX@u=Tecf?MnRBq^z-#HjW1>*r{Ml4cb7dE(WJYgp}(wxkx;?u`FD
zq9Fzo-3t}I#h}DL_FOeeAVUKMU)xW}C^XP8GGPa~&s-wUNCgJ2+Ak^dG|XZfP1~2f
z)Jvydqyyzp@r$#hL%|0*{q6H+B)pBLknURFyt!^{I?xao6geir0QK%D3@t!NteH3~
zIE+v{!z56=NE)62NpK;ssr~wdx|Z?nAuy>?)rUdKS^q+j>2QAKqZfCy&pt}OplR9(
zucbcg(=Sdm?x!Cq(OM6{`33_Bwt|h%f)4VPM;TO>iifvljwqav_UTaK0c-VHdw`^Z
z^Gl{c%LORT7vsONwI+(yfHB-`MogHs<Vk(U*sveCR87;o`XB_XL|WHnLSAqp<d(GF
z7zrC4@%>|lK&gxasSP|rhv=0@x@(v^2T@VaIY%Xn*n<Px^|Uz<`&@`X$5UxK7*^G+
zwY#dlTc~|rJhQciUq>F;Mrrz|fQL2h@>4VJaOP;D-#R*ebfd<xsA@^@eunGfZ2dWH
z5UF4pn3!0G@&h1GU7_d#7x?DbMsm_WlIT(EHi<a}$VkLBK99+l0E)5UBLi1QFl*iB
zT@wYBMd2Ga=+3}PVQ`!|8dCrZAo247s>QJ;0AyuZ`y;*<PW&=fC!v#%u;7_U>pPLF
zAhfa;c}enb5-{L`L%dspgJCk$^l01RkB-bO)lVpqHo=ymy#p_U1$^=SW?4oNO{X?-
zLgE(onb&JXhv08DbI|WlJ+@I!P)<XPh~j9V<cO68tnR#=%A5$B+uHq%48bBJnaG1&
zP1yHqe#Q}63sJKVPJ(d^he<6kkpo-=iH#bH?+902sV6i<m_DYrv6!neIxtwpXGg2^
zGAFBpYij0av~?VcNSD`T#lv|eWp&QIL3Twg>_6_|c1fD_R2z9k=8~e7M0&>I87F8L
z$ysn99d(QnuCqOOuxf=P5oiDrZS=&x3tbNcXa9&v@y}YbSH?#3Gnp>^+`6%$@Y*Z|
zfz8|2+~dU}h!5<k=~&$OT!>aYl<pt+=HeBY8H$^jx&Y7j;n@n}a@iI}RfB-sjz>(h
zMkuW-{xLrbp~*FmSxIBV@&J9|6H`OF`-8s(8Vr`gp{uYX%`9mRZd;TQ;mK8Fvc|>F
ztO!Ew+0UnPSWR(x5~GQ8KXC95O)<~iW_o4MwfcgdbRl+`umjU&s3DRUXTMqrpC%G4
z0)|JUBM1m8elr)ZOb>FhQ5&>!7CPHi?Wim&y{N|q=jvgSA@Uf!EJ(NU=KVD;df$g*
ztK>Y8T%LbYVQk$M)yuvVEb4l<-f3cA#2RzHCP@>KcEOD=T0hi{%uyqUiex>zGIpg5
zMqi>RSQ(0>gfSp+0^!)e#RHiDwZ6_s;Y9m-5~;Axjf8Z>FIE|Oo2^z#u#_JY>KnF;
z;i@rV8Z;9wXGab9TiTgZjXsVDxknVM^;vyy>vW;p@NxX&GmpVYzg{Qus-a8ysgvol
zpT~Ne>GQ-eTF$R<yo)a{3SuiY*Psg?5kaByXTImTU#XQg>(E};^Y~7K=Hmpu$)gQx
zH?cFoTCu59lrF;H=XdgJ_UhQ`7(FNEMm}$MBr}(^>RSWydm*xdOiwY^^diAMNv}4V
zLenj!HJeDs%#Cjt$ZHci=^6bUIzxY5Bm3;qpBZ7WD)5f9|902S_($9^UX$)nM~&o^
zzh*6HLAA(Muv~Zl(i7_?`vP%Iddl{hET&7jE1B`cgoW}Eyi*GDZpjj0Bzrsc?O?8x
zoG}TOL&N6Rk&xd1Aq9#da0r^Ej{8tw(u8Tg&NW1nYDOck#1*@+V|!I%qt^K4N5dgY
zN%oyh6q2M5G|SQ3p}p+I*BP<#4-c8#pBpUcg|KOU*oJS#3s2Y&>a~f&leOcT%Ays?
zTLC!ELcaLjhg-ub+ae<brfkxDj3y$%t<-Ve-2|hjxE6~rim&Uwc^#u|6?Q?4JiB%F
zKu28SQ>)u4A<72~n)I$T$e0b<aUqd0p)f7Qrk8h6e{BM6w4x&fY||0FQ9xHV-|Hin
z0SIbEQ21$u5B6(r2n*q-^q_<+{G#|J6#xo*P|#Kr20eLXGQ{d`wxthN4t2dK<ldLx
zh2R@_7eXdRWZ@yz9k2wH=xFM2hnyKI3LS}_{G@J9@v2Fr1sdbpP_OAkiKP9ok=fP>
z<=#j%9PDLmm{4DsPo-aGqx;V94!WE8%f;E0Wm!o*E^QJXX=yf@FyNu4=&V65_2G_4
zoWt*{VVabl9?8_qcAuErRx53!omy!29fp@B7E=c}pf~W2-+x$(4RtBwJ75a&A8L}}
zZaq|oCt7os>-cQ-K<N}}rj<7$gPu6X7?*|7jOadWj*P%oyk%^fx}U8(I_|ER=iU0>
z)vOMG*qiZ?N#KTqlL!_e$S>FBa*E89#7zaU5H8=zdMIx(;u~b_`K%;dzxI%VMUS*1
z+Pi-&pHoqKggWe}#*UYC_i%qhze>yBY&ClWnN^I?-CfTHJ0awFY2+8i2y&#Vhr$Lo
zUVmz4y8MX*kBVi5TpIB!sWf^jK@=7%LUlFvju?CpFUMzG=Bg;?*wQllckw40`5i7L
z(eiDiRjvagLh`v`?g|^B-Lo3Pk<Z~vW#=%?a`(Tf^_ypy_ZSN{<TDr9dhwZ_So{o4
z&^%c3K*n5la!Fn;1doA9Z%s&)0#+BYXQ@2>(f{&U<te$3m1NAoyv85%oqpkvJ;*qX
zKIefLJ;wu!;=;4_l)VFUEKM=mry~#pAL{{Y;BqlG;|g<z>!%J_GvyMMjN6zR`A7%?
zN!TJIS~Ik6zM!cGs*tb&_OD4WNE9-7My`frGM_DF7gzpj7~UQUW|vwdj_jPzOq$%=
z+|oK78x`+GGIRa9Ml2*6`qMx8HFu3VF;)VS&;bUP$KQ6#tIU+|NMz1xcT$Vm8-&TC
zG!^r)Q1XUp(HcC<RV2`Pej~AD;_?dRo0nAEoOjxy__=O%wrtS@E<TM)S!T@Owh#2u
zv|`U`g3}GKtS{+Owes5Rj^LU|J#*`t;8bEi2*2<UVTqsBM-$`w+!;Stm}^YTfj09B
ze&Q`bt&Wf;?=Cjw{x__bd`)Au#N`uC&YSmrJ%MT)vCB*?-&cpot)%FHpG@B;<HQO}
zp&Zq^u4ghQn0&`04n#J=uM$a815IjxlN=scq!<|4Ktj4V!eDrWhPm}j|AQedYeG0X
zOJA%-(cjO`TJ|Gvaa0hCKgT#s*?8Wv+<d9h9)vg(%WUf~oag=eIAATL<@*4iGtPJP
zdkwEdRW#kgc%=KIpP{^OoAYM#EhFMAX`}?5`dVU%Qb11v20)7k0Jy4RX9Bi_l$F2>
zsZq{{_l}SPS74=pzOaOhpPx~5iuohvj8`r+UTUC=cV>pl2WA*huE`=arp6^XtY^3E
zmgdYWmeokP+ViefK8etQCSSoZ7C8Kwu4kCzZ6sUV*D~Gexd+NGLAL4AeFe`ik2d(R
zaL@Q^{n<bJoh=g_;-V0QiAa-`zB#sv#9EF)qz~$j%R_<wk=!sIHQQUk7y+~}2sHLJ
z>Ln6Ytr=B)tnu8aF{l@3?QF%t+u^_&;N3vLL<-1co<*+n!HaYvWZJ+`tpVD{8Rp@a
zu)_%GiZ}VkVT)+#9K1S0uN2C3U-COF#&a$>E9#_)9OVjtrUzhvS~jQZi;E8p@%9>4
zI3T+@F2U@KOCJ{Q;lA%uo$6O2e&_YgRtLEqa;&Dw@<(|318wb;zPm|(N}IYiWF7`V
zfg@0g0u>-c#P*5J<`Yp1R!j^u7>t^~OS#7%m|a>-7)EmmvxqBU2<6sM`s_%xVuQOL
zeM|&I$er9TIr--fv`tu3nI}xEzK<*z7ft%yt9Liu{g>Ur1qm_yA-=6s>U=Ba72<T5
zs+p6ud%o(+C+%LJWEQjE)Q|KH0S5>h9KAjyXIV);Utd8lUy;?h18d2|f!|w%=rC73
z$3fzR6F%b<8NNQ-XN9i&**Pow2-22=YOzwwzyk6}7+*iPb-_Qo==`tS=w;z_Fz(G=
z)<l7l&6+`X@S^!j9lz4-loC*f;2VDb%zkzwsLD<o(iAk%68|2eE{hxEtA>4+V?^+~
zs-pU8Bt}UVrxw6ix8uzA6J$`BLu)pWLHo09<2T1P9dmKs+^{WW$j2}Vr<=ZkzyhDU
z{LFw6Cu-4V3ix5&ns>|B%r#|*&E?PyQZm@uhF{w&5ceIehvNdXV5wJ)Cw=EQ31&m3
zx)qWq6pA&@7M=C=al&{l8)3E2su(I7l%o^A8eeh+t^~%2JDgd^tuSBVoHzlw5P<=~
zsLwtcZf~L;bGCfEmP<_PkMcbBXdBo^nQw0+h8~&MkK60S%u+arj>^T}x<$!ZR41Jd
z3&WXC>{F2X(+x&D5@Y?-BX#-Fo_KsOL7oxI(1@Ye66Ds2UN`Mo&5|iiX@oc_&;F3B
zy;W7~#Bp%S_nD@;>!S1j?2+U(^P2K}x6aHXh#%1^=~_^k#Rn2^NE8G)A}lJyP@hSo
z55EmTX;b;_$wz`)Mb1z;i}ua*Z6bN$yvC%&*(Zz9YPONH&YQ>m_J(iS$!96Mu3JD6
z|1^h}pF*0&?Pxb70=Kz-^?UVNmv!73w0BpCt-WcetovL3KK5G=*Fx-z?L@xngn0>}
zoPmwPdSX5CEPB5+fcBPD6~2@ph;p=oQ0q3};ceVAB`5_7UC;QLWxwQ`;~Rx5w!LOc
zytr=N;25zfG|B`maZp)XHD8c5yuk+D&(~b8RkzCOM@mQ!p1Ym;r@PXH_rUZ<q>ZuW
zr1MbaMvvqY>MPiu6jsMer7h}e`|tnt7v+{{IbvpVR+(1D5lsmLFuCgX8&G8MW~++N
zzf*aEos^tU62)6FqQB67lU8q4I$xVnGel=e&X!iLPH?z-E4!N>qvtLNcw6I5AusKf
zXRSu(d3DIEk$^b%JC)o2IL+O<CA&rdW-saVTw|sd>Za_?+~tIj?*v03XAgy5{a=6U
z;ZX`%7nB(q*ylF@1>7}MF_KqcwCtZJ^IA`x?gU1a`yd6@=!K`LB$)#qN11#abwDfS
zu}SRokJTDkdMbDea5#7sX3b;1Z2J{GkVwv!aS7E{*hl}w7Cn9N;xl0@G%!c;FoC{$
zVosThEiZcxY8upD|LXWduZ$GkEEp_+D0Vz1LsbSjSrL6rTZ*Q%Pa+Xq8iI>N<H30+
ziETDRrE*dT)HS;q4DbS+4?$Yw%d#LS@{MW(SA3ZLI4>R$3-<rF_Ln96)|@o>HYJ=&
zsYN2<QX*0CN)1Ty)3^Wohq$0r&|m>Sa=o_rh}CdpxCg=LIWG_d425>b3<wNr8An<h
zHka$AWXm+)#4EKhUWu<TZ%hQuO{C=q=9UJuzQT8rto-8Z{{#Sd_zpP_`~)av9_oF@
zx`#$ZbEzc_u5$Ok{B@7VfYCh7EP2+?(+;%M%o3V)r9_iM(iI9#YXjrPtEF~Gs4i-@
zkX{?3dP!1Y;e|-}#`dP<5kuR<+vIQii*uIjn76wn_-^9o|EWpi8HsYNVB8=DVyn@B
zQ;*CGwYkrSLjR#{yFy?mXp<LJ*tf7rnYPU>ATMuqZsaF@>3Qo&IvmA*E1h5*v`5Ur
zwIOlBI`186*BT@WDwIEf#$xSeTOm>FcJ5kUt=#Zl_D-!@7rmEGBdxP5x<AO|cbUWV
z;9||R&RdP-K7ZI5px4id`@lXes1O7ANzk>MobFJJDN6A#<K*R`)VMXs%*PHDJLVmq
zd9mQDm%QuxRjW7hC3>xX>ZMlA&)+~X2*s*mQA<mxR4Fq+tbj%`8t3^H^Q1HBe442p
zO*XLT(uL2T(XgniNF4=T%^!?>9RHYuhEY$p44H#V06I(V(Yc=4Sw@MB+I<+2rK^#3
zZ(%2bATQo7?(lYSH!nPGq0eI(`|oL8N^E9yJGwNPx|3{??&k|$e>UaF)s>Fjr`u%g
zE<9K%pqe#Tl}>76@8=)5wWG6LcDM5~A33#?VV3Xfq3FA)1s*C!|0*5odss!&=y8Ez
zcNj8SQYcsHO}AFMPY+Q3ft#5qkZ4M%NYg8pLmKA@NF`9ja$gPK;APIHKzC_*1;Rhl
z2eRKke!PCX-jU#1^Z~$tC*3Bc>_u{irG=)+kOyMHy~z`6<dTU^MO%tR?BB0oG5=J_
zs0_I};oXM-jeFt(I}j1XFO_?&(R@c<+9GPtA28xatU-1xhtJv-IVY07^6P~!HW#-`
z)XY~)C;-N!*aP4v(~5eM&yIDg9`-8k&~YbFYRfHa?)9_;Ql!cFB14cK@pZu=*|1kR
z#w8Gg*r9&rH{xUa=9%uc5ZS?Gd#)RiGr?Mnc$1i!WC!4dxPZx5+RPAvl<0s#!=9ds
zz;6eS)lFwe=OI`H9KxGwG{3l-UvNjqpqXqd5f<dFS1QrLDz9MI?*}&&iO((3`#^8$
zr)}f((k|D#>xb`H>x^SQ(Ds&=am<g+0xObJVk?6dxnO$x<-T?V$o5HJMVZu<KYg<Y
zcEy!)u|(5Twe_p)CpDU2{kM#Zk*~E$#8!iobHyK4gG-Col<-taIGAdy48VJsh5b5o
zzWhv2{193v&GBu=>q777DKzNZ)hlLnr*y>cgCVB55_eCphkQILa%pS~WUg&7R9uWs
zTEfO|9%<BitV!pivEEuTf!C>O`(iZ5+)2sDWLHQO!Fi>72qNJ)&-0*`p){$MYN$5-
zo}VFtR+3FX`2MQqwiC4?p*upXBOjryih7Gr+ua&o=9tyM5qd3v$!Dm#1y+si5eWbW
z4Sva_=8~uXMvXIkw&c6V-G5t9u216b*x!y284`iq{jdL>#GhClX^sS0vPczT#*prj
z$qbnjwNKr8kHNsb_*eY27oClkPIJJ3U&WCL#1D-*ynkD=SI0M9mnwyF`i-M@ZP<BP
z+t@|>J$xU7e#2Uem%gyWnr;g1UjcVZna_cwo4v}cPio!5>90PvFS2DnSqcIalqlkk
z*6J&|TOUe4K+8TcVNBJx<!q`_)TsNjw660vX^s5k^tt^q#GKCDA}#!rR1c}_1@-OB
zCGS|n<fF+=m%fF4Zswkn=-@jQa`Lpq(?Y+I!w~(tOe~YI4I{Aqo~w_$6NS}12zWq;
zN+fZy2#qsB?5o0`5-tWk7g%G`8+;T!=NO2aY`M?1yjI^=%gpiyqIzz}8xc9mk}k`-
zdg3YQ>ywm4$Dt}&5zth$6B4whxM-+(UTQFUT}vbqOWm(s4JmdBI*T-V#`z2sTPk~P
z78J(%^C#64b!Y+^ebhjpkHVuZQSG-Y`K+7*`A5LNfWI`t(!M6aqFg`{)zP+&M2^Kl
z<EV3wDm5ZcC|T(_=DsXcSXHd)RDzx6y+jViNPhCF-=@h!JnvxRxc_{`EJejAHZZ7w
zjW|BBrJN|5#qKfrSeiwQJk@K0>!bWb!M+gvs7+F7*g;~iAg#k9;<SeU^;h8Iv3o>*
z!RKH)e@NPnbA^U(l3X6M+Ve*J!?v3UH|S_3!Vi=!1DoY1!cIMi<HXA0{3TTANzU4x
z*Bne;F=?#RwzqD*dD@$1n=x|Hu(ZGOTT+KL8&Wj4i8%u8)tW8F$KD%p<n7A_uzq=c
zc%*nt=u;F{6{Ey-ttYvVSsjbi-5*iO0&{`O29@ib$X-_Puj^kR3))Xc1Sr<Le+2N{
za>mz;2X(Wn9KTb5anlKwkhkC#?ywW0%@hI=WTfb&M@^R5VVHEK9rOAV4Xdj$e$894
z_`4qWmV_1?O$IJi<;<lBz?S(XeH{@=eO{HYQ)OWWCZe;!R8*c_#+0`bEl|Qb6vIl#
z@xuLyzF$}s_wX;s<PQ8RBDhfnRGNMBH2o#fKM4QMspcYIr{wXcK_wBjXqS4Kv0_fu
zzJ>2rM-wn-&1AxAo&l&kL$`E{O$e-yu;G8epg<{jvS44MnNhyx-`sOe&$|rT5{epU
z=tjlWEJQOXXd0|(D~n?{4Du4H;)80!(&sbwxaBA{Satmh`+=?HgcZSYTjRIm$a4fP
zWKeflsiO(>3k$H!Qb}9*A<{4ikykrh&QGTP_+j!Bq9j9Fx&opJ%NF|eVbs7TD3&lf
zeLMk&NhWe&8FSfRaslMzi?tH7&;#<Qf5s=ZP@ez?9%O0=$v^4z7>Rx6qK7f^cAt)=
zXmOA;Mk04HMFF6Zt*S12Ssl|}eV;#&fRW)LLR>kGbml)iU6hsoMw&z=C_@lLT5a#q
zI%1#9yzNZYB6RDe#f?aA<job+&jU&P(SO<|um|<br`lv7uN6OQ(%IV33jA0o5Ont@
zM)x%6m?aki%cz`#`OXg|7Qx9QsZOPld3PN~#>`ti=p6f*8NWf?RXbsRk6}}u(>m%4
zBF;<TwbO>%dg_!x{BKwFq0*JckYbjoNoRn3|AsybP{+hKIS5-fN3hM#iz%p|NeV3P
zac9OSfvimw(3$O5;znn7Lh{jIW9;iEo41+5+p@hyYG*7(6keoB!WhnE*U|PtBtMrY
zyR`rnyY--yndqE;qmus5+6PpdJ_(0AgJNB?(ajkc7ae<;0~7Ymj8I7P`+Vu+_=)#&
zwK#bCCsYMMM7T?>`nwWVS=8n=kUPczP>93$KxtKq68JnePg5RoFt0DD(vBi=(hPK<
zJJ*s+409i^s$)tmjyB#ezlYlH2dNv89|ciT>nC6S@3wOgAnOETZ_|-G5{gMf!?^S+
zttVF0%?va=f5i~Pg$0K8JVfax-6`i!`1jN}_l@+#Ul<8y&nKmSE<*%eBj8#!8E9*6
zdYFa2@kXh)oZA}MwYAF>Np?he(u!$QcW4Y+4I~JR7H_+pC4`M~S=433^$}qpjocO4
zE{$>BCQ=I8JGL}|S=%V|x}no8L**eag)*{r4rn0y{r7(tMUSA84wGx!w4OIx+)8b^
z)?qOa3ih}Cq#_s=UvyQ|*$xFprT{d(75=j}<axzN=M7`f^V%71B|T61jwI1pxd>+C
zC5n5iLbJiIlAV#v32&lHr}ycBxpK{1Ow9U3+NBoz6D=n?z@LM@Pm0cz(RPG6Ja<j!
zuImnZ%dUG*I6Q|ajMMLuqo=kpRRIQI6v^}_|7?<wrzjMS5HmV^uv^l#W+zw12p5+Q
zf0S8OCw0y2V*#F%YURLkT7vNHM%V!BmImkU3|zEAi!o6E5R2b|m(r_?-eA?4iH4aN
zDvgaGxS%Lo;J_m>(%fn3YE-89>2%9rF+2Bo09Z>3#QEy{7&74qEf+!HVk!E^9GB~v
zzptI~YK9j}>ccdtYVN(qBcvej_JfkhEMAFvra83DT$-3!8`9huW3oP3n>VlNNmGjl
zp?QZ0jM7M8*hJud_E9VV?k4DneU8=_se?}BrF*%@7^gJG3>$a{_bcc7PtzjXL=eME
zkhx)ewHxIHcrW!ye-;>C4eFF*V+w6N0SOfcS5^d?4(WKzpyg!PM4)@a>NTG`S^o;9
zq0A-9Rj2&Q;OnnVM!YjP^S@f#5=j*^AKGr7H8W@Vlr?PDy8Xkn^w&Q$&+9Jrmfw=%
zEi+VQUd%KBguFU_Q{@^VRXE5QqiDyKl1Xq~OFc<ux|08a+S0zsC1don7d>AdJpJC)
zD9O4UAWXd?h5&ZKaVfy2LB*l88`-k2a<<4cENDPJ0TiYAH?Rftg$57U$rv;!YWiMA
z<>(z6a-LW71O)G`F7=jw;-y}UCV09}{;QrK10uko2bHDO%mF`>Sz{b^c074Z=h3S1
zM-`Y^@#pFt&AKEi#eL(tF>G-<jRWuC*Gg3<egrx{mFh&a=8#oGyGtZwIwqw!J_X?l
zoj$&RS|uE${@miAVT-8-iK?{HSpMtiMqb?Qn7q2%v1SYJBXoRn?rxn+Fo4Ucxg$>B
zNe$N4!kN-6{m*ILBvNBB*LfnOFW}GBeEe_$NH~+rZ~Dksnf5+^KNhld`f7wH<CT$V
zb4L%wI%4c6#7YGiLW|<ka&0)%J>%BgEFuaz#I#vCp^{pMV}jC~({tGJWj!#jr2c_T
za1W>pxI*RyKy(*ehxl<TvIY|6ZM`r;;2Ezmk{!2`<|x;H;YDiFz_vv=3N$CDi=X^S
z7pJXE76;73av1z04wyElj5=TrHu_FbmE0&aI7+D@&CUB##Fiogfw63k;G>^wXJ(8c
zz>o`s+N*NO1)mvp2H7<b0z5Lk#RH^Sp7a_x>vMv#<rQO*Fad+*W!-NC&5#7aS=6A3
zonaIs8PY|>DVE#x@`n$Q9HRfOtvh)My;G$|L{W<A<T*b1i+=@s1|!CGk<^WBk7V?$
zB>ax<S6x;=2y)j_ss}PT=7!}*fZf@BsiV`VwIkYo`BBMS0bJ(F)*_?9H=tdu5fd%8
zupia*LWI7LB6>~~;6ej2m|13Kwn5Ykw57=02Z`Bcv5%zEZ$5tR9~>)Q5wyQ}aR+Ee
z_#V=t_HkOvVFBqOE>`>w0NN}bh04ARjzhd-{onis%(<-yz!3b0V2xt$un9wHBH`D2
z(6v0_NMDi8l2Uo7lnUc3#?LHD%*B6nhYzmdC~11cl)Lp6Q&`*M^)&-}Q$5@^$8&lP
z<F$yLnWPIh;-X?nvLW<b*Kx?IFkU~Q9HJ-|PdMLOIU7vA+_EnmUn)l<VX}R4l-G2Z
zca#Q%oIzCVJfXTZF*`aq6m02|tl}s`-G3i?>LG|2#5ImU#MF53vURtT>DG``u+W>P
z6YJJ)v&Z#<Y?=^-2(d_rjuGWbL49DwT%li^7@DWVmerBBlFUm+-9j`id1oSGlTKsV
z5g?860ZJ$?ZE$QT5ltP13}@PFL@rdN@t_#vh2hM)9v$If24Jb!WkhRhiwIc9Y-#!N
z@J^A|H&3(raQKUb&jnhpqG6C+Gw9T&WQ*@(v4@Y0_aTX1&-4_S937tZJeA!GjVcxN
z2D1ik36}EFVNzb{;lzNcO^2o#hDksY=(cimm@~;aJxHXVKZmY|1kfB#hH4!Y3wFf=
z*&I@h88z5Q`q)=um+K^d=YUiA=2G6?x{VQ0b&MsY<VomZ<O+pCH$$R8B;xcT5^Y?M
zl!zHpfHzl4;`xIwd_RpI5NR$!1<A~7noGx{YvVqVok5r%ZN|%3l+!6t$sr4eXdwIn
zeF4oea{X#;5Z8cFLLJms^baj*3VVYTSR?of{<7u`Ff~*vht1dh3v$1>Id~<$`5Z-P
zh9$CX)LKYtM!F6p4+SU^G-R~v{G0jJu?59^InBkUEwd5Wk`hpzto!1QFaB!VcF-Wv
zw8vM{O^DJdbhFNaiqVr%)9HDo_SJ^#St}Buoo<kzhgT&p3xC;p@zD{CFfbprg6K#a
zpkS@5fx&UttaW}Ryw|0Ti|2ol`D^^^pxhH<O(mKsT}6G<LcwN9(+K$ngr=<rlJ71y
zi5qh}{(>1ELsrOiKh^BQ=-80Tj<zL12$f3pNmmMh{ojxLW+;%}#wFHRq@1b@GSw!~
zleP1nMg*WE&v<Yh>^qKZJ7mt3z&%@_ZJ6HLwtb9;G2&+(C;qn60LFMwtAnEZHCzdo
z@y%kXv$N@REQV#pp&;=T4(+e#lJyH1lIEaV_7^E~18t5fnx}*J8Xz?6H~)jB(CzSO
zds8ePKC4+qzNc`rZ8CGu^<j#coLWgW6}?a?xOjK};w6b*<kV_F083I}L7|M!iqp5k
z*u(ln^1PW@8z**;QN~t=v_idE<+Sr?Qg90cKOKC*6olppGmgdPBxeqP3JKC)&)>&A
zQ34U7gWagiFauT^>V?`A4F$UcOQ4|oE{Ri7{i;4|TQX6dX*|3+PFYYkh#iW5?ZgNs
z**xo9cYDU~*WEstQ+2l|$?&0oEL(af3M})JAV4U-U_F9*Z%_u2KP5SnHXh1xv{X+d
z){O;IoppN(`J|clp*nD9PV?e;-EtU^8bgRha+i^|X(|ki#@htyv=O7DHzu?E*Rv~)
z2Pl~~-ff_4@5A<Z@4k*Q0gO2tDI|4ijet*MnhwSeq7TeAg}=FCvu8i0Ay_i~l;ERy
z)>zzZi)=$7tf6}fAdu*qe>6t$*PqOL*;UcgCE28aPVg4&?4`ei3i$9#<V%y0dnU(^
zt%43<P88Nb1MZLnN;*KLKIIy7#UZqcFgJqW7GtTmM{XN?xkJcl8%DX8t{K35<<O$e
z7{43og>tq0-d8ED{3KdroSFRdB1bT49z3)~5xTE5e_6V)eM4i#wFp$;MjtjTW6I?#
z$%qW*`vy>&m%Z<BGthGA&-dG6OgAWi_39rLEQMX82k8%gQ_>l}xDlomlZaqVRqHcq
zSurwEC1tdM>p6r^yCOr7OmKm$Cfu63$4P&>hsk_jGCR3&$gDv=CEc1=Q#6G<;hn}n
zM;E*|Pm65lLqLFA2+Co6!+1+I{AGRwwaPkpyMTx(>hv~dQ^5NzH$Z`(>m)!*vsgJg
zCoI^lUG@a(a~tCY3NwVM>J-DrQsFe}9Y6c`zwxmC%bXxHsh$w))|1~!l+C2=ys-?F
zu=5vcjdL)`@yMdy&F*l{*`eFa`VqVf_sK`r@XH<QSov5vmtXnCrek$4x>FumvyAVG
zold;R&`}Asq30ZmwWg$IKq~IemeYB)D6Q+3CtHJ{av_@n_6}~U5EfX^E&ys`*~~q&
zraG)+-gCI=IzjWH&YSkCZ5h?d5LY!DKx0?AOFp5R{6?A97d9-33N#%Ug2+?UdXfjm
z`YtUE(&7R_LWjeJGjCw8<k^HU*b}Ra>|&aRq^f9Ppi!}5qaoLmTu+SF|6;Ya?gbdp
ztKL_uLu7g~?uUthd->$`k<rnhiV6{1&oinu(>&<Ko+6}mQmNKoZap65A4zS3WWz$z
zfkz`9=G|t7VIm(Gi+@W$HrjTJn1cyrG-tV5vh?rwH(?-fLR+Pf7@3|#_nopZb%px-
zggt8Z-5EcrKH@v7jOfcyffMFZ8t(_&PK;mIj#%dn30w&gGOm6WzS4c|X6|fE)qf@Z
z&ZnN`V?#TC^tTo7$Bih{V?@uH5H7fn#b%H;8%mCj9zbgh-EzZ_%%cUoECu22aamYs
zw@e7?ES}loWlQZAkrHQg&*4vf_b59kpstwK1^u_WLfK+RYs$LcJ;fOmA1k?zU{ai@
z0d>dVk@~)3_S+Qj^4IG3X#>xzZxV~?bsAZ&0u})<a8WQ6A5%=jLd+_YX+~0g7~ddR
za3+$I=Cg@6@1xpLenr2cXLh1}>XaFOcq1Av%Zs%vj5;3!_CT+f2`eTX0Ou){ava1)
zf2PEx@efh2^j9+3O0fM)${2PRM~!|(ca1^XTPq~uj~!5ahDa89#aQu$9ly1|MI02^
z2aJ0bM9f5K64rb-1?R(02-+}4(9vzC2+o_;-H2v~<Pge5{#l#;GgvwZ<Pd2=#+tM0
zq9LSu&5rV`vzw;BI7QRpx&;GFMqk`QT$w6Hl@}5gxwBLJWR828f<^nj8n#j`_$-n{
zK!tKCW=FGCyf%KEsF;2^9C#ZHov~EU<t-_a9(O5{nKqIYql&I6>IW$bF->>7O96C1
zHpgX=njA=da|emUKD6I;=jhl(V#;lXK9KBzA=Re~)?if_nHVUF2wakIY!?NR_QQMx
z1R#GN<a)-9f3ydgB>g|zC#+9ZIp_6yujn6NJHM*`MVaA3`cyA7F+pL->f%JwYs#ql
zeN49+&3I5*6ORZ#w&Y2>J-7=2I+pgswu=!?MDSckD2g1u=Q!=7N4lLlNfL1aRmL@|
zb8m&{EBx5pjz8*Zk^4nlAvGY}?+H+mc5YX@jJYJuqsQ33hyOOLpsbUohy5*m@w8A5
z`6WsB&)Q-?Fn?eQ8wt$H&)KVO^UkJ5wBI!+=1!K$>tD4nh-LjAosB!+Eka0OVQ4?S
zNLV7BFF`&b<m?$*r>&f|<Xh92Cz4_p4)mFG;zygLNZC!?-YE#Dblwt#Ad2V%BmiHH
z=KDTu6Vu_T90>U9x*w`>IQ-Y|e&Hd@YX25t5#9^GboyBXKtZML5u<&zjog>O0$>z@
zpm!jR$sysLH|@f~^%xKaNO!1D%z}bEs5!$xelt$YxZrs{nkmd?h(b~#OoB}b!gEmg
zWxzaBKF*_8)woeqwsE~4McRM>6qL<^Fd?=#eDHSs<CxD6;@#<5K9}#!q@Pva1g{w6
z)VdoDOZfnK(deyXM6(D(u}MhGsxbqub+?)S=^o+<B%$!yGntOWIK8cC1>~(=I(1e+
zjsU^L>asltzV<e|#M^_O&WF0|iyI;!I83_DSWApG`S?5dAqi!Rz>Cr8d6SxWusg#l
zmAwM~syEa%pXR^~NRLvlrY8QMy9$F`7QK~I5Y%X8%ByaI+5=-WJ96KjTdg(9oIglY
zQIH<O|4=CR`@efi(WK1j3(Be?h;U-hGHq-51vPr4OS>E*#_@c`=~i`&VlxVMXhsVf
zLmDS21F0V>r3Cg*m>ondxx!TaHH{v4CfB$*v$FWWF2Bo(!VsPUIfvO(mVp?joAjwF
zrF^7N<?zYY4vb2YPA=%%^IA{(6}^96pAM9EWB?FvkQODfhbPPord*MUX_OfXD|<%W
z7gw!)OYd2VOt}@%=p1jZ^^?wufInO*EqN_&OJrTeYVZqxyyvE|dSstFUadVZELf`)
zJ)mCmBPm%KdnSeKu1CB2KsABP{2D<cP#aw*`6(**!@0SY+Jmx2otEDHR~ywbgXAQ7
zehek-C?k<(RV#*28x7yf=4~%~)9^F9@jrdd=MJSL#0-Tnw(Z1z2N}F41*`E%y^>i%
z`1EKYyIMyVt}SvBLm@VBhI^4_Nla*Z=~qu#atN{QM8x#z5^3Se&vOM=##YAYLU?Y<
z{8r{|bFS<FY}4FbNf{EUb9<Yjoq$<!_K6Q#j*QrTpiMAF@_VO0*)f}0mBcW*%7;1|
z#7z6?4hx542&0n^kPObKY{i!jXW|n9!f_uZy4+H*Y$UP}hqzTrWo&~?qWo}d2`YXC
z8PRUtkvN*~H-^hOySLouYl5GOs6&KbefqyBs-hHA#rBOE2G7Rvd%`qxh5NNks@o?C
zNla#Htc55zyTDvEex6V&ivoudouR20%Sc}<j`W^cXVjaBLN2Cvj_5LJf!lm~-C8I&
zVe~@fGty8Mi?ugF8lR-_v$&%4l}64od_seCRQ}uo9A!n*lCcrG><YI(-4>HXfY0FK
zbIAkTU4VO?p<e9H5D(jQD?>U8*3|Pqd|vL-)_vN4)=W~$m$TQCpI58Kl!9+jb0+cy
z1CWUwjw(nR^bupp2~qil4*TrWyO0nAdlmK<)2BNUi-L5i{^WA$-+A5cP`Pj2V{Pzy
zf9ZXDXS4;$?c#Q?2`X0SDGFUUs(IxlCaF8k=}bfcM)WlkRzN*sNpk*Vv#t|uKIY)*
zG3CQL*_%0PqwbTR$~^Y$7_hQOur7*ipJz;D_?w-dEBe8jWTU#pAX9~CpEN&G-Zgg~
z*d19$(@O61At_-uFBAjUBuB4ExV~uuf1sWai@^o8K-DzeNeQE;@nG3{b?t%eoqFKm
zN{76cPtWZ9Nt7vg;+%AmOayqWkKRGn$|pq*n51o3r8g|;u#4Em7Fi15bF3+O`I&<%
zyzQwrFPoTh5b4va=1O@5+wc?b6gK>RM7n<Y+tZ)?{78s6LLhGH_rauQiU}AoJXu>W
zHT-3{lp?V(kZAFQ+*ztdsBy_pq4+!d^aTOn29jW^nN6h!%k>krd!~lHNXEfXwK)dr
zy?R;(_=+V7%0E`?sb=}itXlM@)GVd0fnJsQo^Z&(oGH%pSX&F((!_(;MZy|*C3&i`
zDewi@YOx{r@ClQjDbbOBO7XVkp<d1Ywsa*+v8z)<lMiY>nF!z^`Z@|Xw$c{;3gL%H
zx~Ru=6J>LWi@3GB!c>X&N*9d8EbCUIK0(k?>pWkdNHFZoYz%k|a;{cO3%c|3q?2bP
zIcx%hj2lLtG!S&mqQ?OZqaheCK2}UwYe>HY_)4+(@W=3z1Z-(1HEuJSUD`gAj7roW
z?%}Ci`AiFY8?gl(|Ca+K?ph2SZkCjgGscUEe>i3^<HXD-IiLz;I(|nzsl>*mqUWUA
z&fS^j$I&l5B1Ing6|X@6CTBbDw6Aknu?yBu2=9P&*rj)>EvF9=;)$Ex&0UwR>0@`M
z^H#%fR}4#6R71InsD!BD^^({E5loZ3@Ndw!h5k8js#=D^=pnbRW5>-yHq-=o*#{If
zo6a4C#GkbP?+l3+TqTI_gc;XHj!XFIlR`0(q9B?_Dp#1ytYoI34ffkV1wb1Td*32>
zq*$QoGib-iCdsFSgSUEQQ)g@%X>@(r`u>&8fyM_u-8T%1AuPWyQ{H4ori|;@3Se2?
zg~*89*yLK?SWley=?t<YP2?WcFvfk6=6;K4OYps>Q2Prb!9&g}t3%=aYsY~Xa+a!T
zZ2F{63zhyP3Y+BW&LU5D%l^D9QPwB-Ns<PB$$%Z|%r>*g=!K1&=2uwtlRnMytEv%6
zor8Q4<Lp7zL2Dp2uof2#9B_t89Fc;kVG)`G^JoUeG2z0KDcSA=gcFhJirhGLAMFnv
zXqRFyrIATu2<_LeoBajvDHUqCFyCptxJ8FMu$XM!?u#k>Bsc?421UAa(ycf~-`9-8
zAHq;{ffrEq13r5B@s|Za`lS1Rk~#%NaMpyHC?6t=XU`->G`kx8$pKQfp7D8K=n8cT
zqg37qdn3{Lh@jhG?=mI$@_|w5sc)+|i_~`3lN(6sp!noh%vy;`9hQPd-xh$Q-JBL^
zG6zr1ihP7JXPo*kut$UTvKmzOHPw<WSS4YO{^QP4Vxo`Z-yM;kA*gD4-a*{QoX1ko
z_{@_r3QF<GG>UGK=3?j%Ui?Bx=%$#xpSICez_sEGQyel6zilqmDjBA-OsW&+rvj(5
z6ZDx~Jk7P@P_&|cH2ciJRwN!11LvNtm98{;5?AbjCxM&5#Y-NQeX@4`@-&@tTWLkJ
zN?mtz3E#9ed&D4mjYcc&G!Web0FtfYePbPd)^?d{(kCNkhR2HKQ$IBqsG#JB%;%6j
z^4BelN((qH^`nWuCBY?U3Wh{;Z^cKN28kqn-UPfo36KbyjGtRYbTvi13lVEG0!bm@
znS!*0L%XDNzk|+1Jo=`up|7!dGC07UXrL^!bPE14&8*(ZGR=lN&&m|%C^}Hmlfok6
zSiV`ECc*5hIr)?WNEynms!rraAwh6$No|KAbWDzjAjYs`9;XGT&lxojJ=ZV+G*j6I
z6R$sOCwh6u7f&KI8-SI-<R<P*BBxPxn6$emzd)wC3HD8yocN@I7tAsFA|=*U0xpXE
zJ8I$ZQ*9w({hDdABYMX;Wi{{=r*uZAI{}EkgPaWc5$S0tWLqMlt~1|KcajMS6A~cf
zB36Jfb>I=O0{okQAT1RSNs#%|vFL$4%g!-SIb^M)ADZ*z5Pg8AX$B>QLf`)*@jY7$
z_zv|6+z%g$bBc~<;<Y+#J+o(g(kJ`1iLqq?duc%?%);O_?Z$2g4fs#TjL>*uEpcUO
zaSd2wLysG#!#PW%8>Mk4+grj#2?zA4&xQ8S``(%oh-@vtmdq!IDSxxk^o&vbKKBn+
z!3&~==4$v+Uh5c|)|q(SKdO#rmXU{~b)3hMIv8FN68GIxD@<|y@fH*=={T1}Om3Wb
zdE5AcVm`M7>16XZ>@71h@c*&)KG1O-_nl{Vb0jxuI>9u@NNI#)x{EEiID%<l$Y@81
z5>Gc8WCMiw&y3Bd&5HqumLbNwHW|mO^?5H{-8Ep%Op^d%SQ#@qXE2;_TR5&GQj8v)
z^KJkVv_Of9EXT=mv$=~%DZ8{USyQx<Fp1yueH)}~CF{NS_PrZQ17I-dsjk1j-{<$O
zU&++{8d|vnx>n~-#I@&~)m_-=S?FKeKer5N1<t1MuRd{L`;HrbaeMg6i&tKRis+U2
z)s@5Y&C7SZq1DVyIDiJLYq~#RU+P|`hZ;De;2}K|EY(${yZ;+F84#Te52WdO;7#kZ
zMtbJwbcj<g!u{JnaU_Is`oZ{<3;@wfMJWEGP_m{`^t*c_{@@qhdujjj-CMj%`w_+I
zaKq(gFpBO^PdqjG(DqN-*le0YIq#;xM37gZH^-y~!`bLLyzhvcMm+paLFBm|gZUGG
z0`Eb5`Y&&f_*2WD9r;0w8#{32m9AGYkH;@cWKX)2_6K>Uu|%gV^+WbvivEFR;zDW(
zK5%Pt@&hcbE=alDZ@lCqp-GyP>YZHX=>(C^53AY_WA6QiW%r0Lh;89PL;%?*y-$i)
z<F|+7sVfKMCFB5lb>(Ya@RPa#5Z@wqo__cre(ImzH5A~WMmV|2-R2Iy9U`i<;KIOi
z!w>a50`D+D<t1c<ty(XsL=YnZso?3hG^F+cdso_^+rNO;{hM#3M-9CB_8<DkuDpuf
z?_Y@j><SW(J@dAB=EZ8dOr>l8RgAzuO>g~O{|?@SUhPu|TjRbD-u}jgRIlh^9}(vH
zRKRhk5C8byafUe}tZD714lvGtz{dFtt5ojO2XFl47e=n$*uV0Md_|_)e9w0MU5>o^
zquWPC%xvp$HGjKa&Nxmv6F}M}0uNijJ92{Qu29@|hYQ6mG5riQx{Hq~wyQuY>g;i&
z5|WX?C<}N=V$wy=>vgR_RXpjNx+rU-6~hbk<v879WGl8ZoE12d(Z+tF=PuprdBVps
zs^c?PGugqOvx1B)dzlBueS|O&N`_IL=GExX0|d4e*BH{}U0l>qB4~w0pjt{GtV<~t
z4RZU(p<^HQ7IRGmtic3u7Z!>nCNsWebzpzu))(xu#*sc7kxNCvwFGv)26ooX;9b6A
zdRi=WPca=RUsdj!nc?hAX!^FVd9In$1b&4LCdlq#xQe|!ts)y!T;)PK>WrlsJS#|K
z&};ZgIVV7k1^*gmz_cuP9zO07S5PFX7?;6^;B^}tvrtUML$$2F$kSKxp?F5!guoMm
z<E^W2HZwRO8to7|c=<Db@!s?g?mldMwNdYiclQI$^g11y5@b9D*G|p<05fX(ol>Su
zPb=U@4^%Hog7-OSoS$2_M+ltTMN;yeJ~n}KWUw4wa93oysd;i%Tt<GyG{vICFtEV?
z@Zo7n*YX9dn<Ef)z<v=U6Dx>zaNe25^5Bl+N}HkV2s7A8dfW>qb4WIV6x6F9wMrAx
zfB<$Jj@y2!IsSlMgXx8>Y>@n*Jc@XACbL?c|398?er)eQz6?I#U60g{edmD=diRlb
zn>!Eo&Nr)H)7Sst`|sIqBTblMfdV#$J+IR!kv;yXH2DzoXlACzQb$=W%hJ4*a{Z|D
ztWf1<uFA4p79BY^bab1TCE?R)vB)@}rOd9|=*!I(cY8F`@|e4>BKq)~ULlmKp-+dS
z;b+{0Z(7P#ZR<~bhAT`MafaQ;SLXAx?Qlp#b^dSP3q(es<DsD5VyNs%yNH?b&1+0G
zFNMN0v%0AJP*rTo1SN!ANls?U+c6Am#bmZNpg(}75ya{g59qPgmo}oX7jqqiS=pR!
z65Ym;51X+O)(<=+S#hVmvcD!`=W|kr*KqTn{V(MVCOCAyY54(BwxK1$q#=z)tlHdM
zXYew+kEJKXDP=Z?&Sxl#!qja8>Fu~2L?f_ZmMGPXIGER{M+2LqBK(|uoGKwcxT-}Z
zsdVcRJ%L<U28$(CgK&uip|wH{)@uvJx%pSp6d6)=bYXH;@I5~1)SZ!~9s|>u986CI
zRk*{rGNd{DQIG`yNJW^|1>9?u=u1YcX+&IeObwsHdNF!UL#GO%L@60@$hClGpCMti
zNuyC#N|$X?F*+5ByT<0ZO(E0J_5VYA8pb7Z&Vy!g!!gxqlJ<M#4+V9av+@VT4laT*
zZW!I^R*wx9=C_y+u(g~pQC+JP#&|eQiky<yLx-?6!YCFM(kb~SC?`V~lzSr!P{tyu
zjn!skoGO;{T2WNpR2Yc+Mx;$6c}hV9v=Y)P-}>P%m_K&_=}T1%bX`pM1U$>K6H80t
zGO~WEPSdI$@Q1Q`xn~?h_@e8JJ`rV+MDii%`Fcqy?@m;e=g2reCVGicH%dxTG_7u*
zowBOPfhA}Zo+we;shcO5L50VZDpQ+;mx2MkpPgg;L`fJtwHuUxuL+_xq&UNHFphQW
zMqiL^=Z@u&R$~_<1J0Ygmc^i9UWswufs-n&vn=aps=61lnRsmJVpiYDh>XUasybLA
zW&atnG>KbMM2v$*kGe|UmG)lI?HkL?c%9Fn%DW;}*^;Xple*C}9#+S~ZrzB+dDGZP
zMWoh^NLzM{xRqNZ#=Oe6kdZl~IHCq#V$dRwH$|DI!5^#98!xK_8Zy+ia6Iqn3>sAD
z$4OZi4TRfVZLy(bOR|z#QesWebeR)^lV}3H-B1eZ2s(zT5o#Kq9ve7)*VUDQ@e7j(
zArQ8O^yau?uIXgXM2N#l<2MF1rLa~!gblPqs+rS=TUO9A2n&@Wz4@n~!?;ARLjZAg
z@x%2MVRQ&pID2fvpk-{+4pdaPGU8+q8Zy!4(Vx?CX(H7ZUID&PdJA}6k<?Z&zm0Mw
zEoq=q%oqXH(kYRoE%v*Q{FJRMBLvfpp{9mPKEu+$N2ZJ!MV(PbmxwZ%J41wXS@o2T
z46?#!A-1UMi)d+Wdr}(I_qeeJtHH^j`IW$0)1l{O%jndJBb1WDse(@pG>4Y3BBo_s
zQE1cm!r%NhB$P_zmRR6sA{7+Xwg}!3gi;fjo4V3&&b<)k0`3co*{B3*MBT5}4XS{z
zr5y|?gRn8KP}9*9q=a5mP-%e;=rPkpUeD_=Wy}!4Wmq<(LGg2t{^1Y5@Y9&0bOoC)
zIs_kEBC?#pP!7`d7PAn+g1!e6mx5f3P<voDQMp7*#9D!es?jMmg$G<}Xd<pK{!m(K
zO<`$uD?B#z2t`JE#TkZs$NgZ3ocgOfQL}i1i5r!eJ^6qkhr0Bg7B6sl0w*b&+|n?-
zbPp+xIEh2dI<XE39RvoZO4CuTU?3OiH0zLctpl?xX0^~*A*YE>X{dx76H%5LYKn(c
zN@i|Wn->0*D74fHw10EWyeG&Q9ZXv!a#=cNh<dqfD<0|x`%Zk!gJ@k;imw~J=@cKv
zGbOWz`Ou^qgAu|4wY(y?5Hpf3F7gt+Baor~9Kr1=jUd#kI&vXF><D!-H&s@^FHzZ{
zvG76kUeph&vQzJ{RmXJ5gfn2NO2LOQ(`y?TVOS@WcpQZ{P@{&zj2M%1J?$-=pb}3S
zIx{83+#6yE&SO4~)~4U7HBB@b{1wtGO%3z{&44aWC_eJ$_kRYTi$*Rk+S6SEcjjee
zht%O-c95K%MQb=686>5}q>11tp&|@6t7#vGRt|$p%Tu+HmS>s;Sr%$&JhZE!B&;lT
zO0a5}=vFMfIlK!)uEw>SpZ;(YXDtYHE8S7B{s*eWy{BuC5a?RzThl-+`XIrMd=={=
z?$<;|qUhN84i*^3Ajd^f0L=NgQy~@BsT-?Z2^}vT%=kRzx2>OU<_`F16<x^gHdpwN
zPoBypa~|vyXHw^Z>h<P2M%Y?qIURVtMC4%trc@>3;gTearKW{NMx-64L1Y!Ri=Ge)
zg-3eGYZ^K*Q_S!1FyT_lcr9gt)SFx~1wSSYw5=h#{{C_na}A0^FqL~VWF)b|oq1fP
z)6c+_z!DK)x<L;S=^~2eK(`G84H9A8s9|c<yuczBvhd-OY=)5*luEQnFv>7WT4Yob
z3G)IIs1mFV)4xY=4rrv6B)j>SzlHnH3pF~yMnj|fDeMBj;qzz7l*1ac_02}K5?3$e
zN+Mq*M$|{h$bAX#KF`#R5;lQ}wYg!8^1Pq$*Et)LWQGJ!^2r;#NaE+&T0*<!7_VCx
zQjhccTz#%azY|(ZvU;HrC%hP6W_4b~j<+RNyT(rvnQyVDlevYeR+Trx8zFy~G$LNT
zCg)~OwxWhHlN4CXGK_^%zQC)k&@Av3>(xisyT17ePP&QDcyadSxr^UfD$T}UduC?#
z=+0W-!jyAk<%{H~GbC$sn>%OaU?~S3R^7PVz&Ml6(!kj+Fwa;n5po<8j(nZ#lCxe`
z)$3M7`FO~UB8gnRldU94v?53AbtA4lUag)WqqS~!onwqu6J|a*SIV>DWUjk}onobG
zF%eI*zQ$z2&dGwcnXNsE&Tkc{UfZ<k!TPgS>(f72XT-L^>8OU_uyT%x0aVtzpDQ^r
z#(6?IyVh67oI!a3c3Am<?+^q{VcMjBgylK?p_9mYqZ92}Hw?jk5$|K&M9;qwok06<
zETMR?mEQf#S>YNyR92YdA(quC&ZOHwu^++{>BLjP;t3;$oNvJxDV)N)R^OUF-FNG=
zZ(xsD{~KIo>=+4JeIN68xLy2@uB_Pki^jke`@zG2>Ed`h|NU9QM_Sn_{@N8if6aMT
zGK6{fv(l(sz4ENgza~%c`5W1@<Tc6I*xb=LeDHC86#MMX#_ATEP07PDp#`easR-57
ze~U4N)#;ZIEXsltB>mqf`Kg#K6hDSuUpNAWzolJxO|E5iD?Bc5mP*LrB@HONlfJ@{
zY9hPP&k{*D8i;Z@q$cOH18YZ;4K;j7ee1~~J#Wcm(;xiO`|?YEbL$lDF4k~!2wB^E
z<%@ojUjr#r?OQndl;t<*$?MgpV!fUX&09DY4CjhJ6?bKh@=)nysZ{E)WJyt^_ku<$
z%+sTCGNFt#X$eu)DRhPF(Gkh!v&UE%mg-qvOSV=L*(w|%enRuVhFGO!v>|V@Qbq4z
zGTG37L53Ynr};UFZC5oYbo$rGLaVQa>~T7M_3(PbZDuzT^9b{G+J88W5Rn&Gy4xG7
zhsBv%|6zi2z*-w{v@x0kC12kpgKa8Ks>+KiO*GJ9spr*6iETN@r0oBQ#53%TZ^;RK
z22~2-IB(K|21>tG))+uhl(76qWR$e>`|v`G?va#CNz^VwdX)a>aramWYI@;Y5+;NU
zTG<ebYi%CqSZ@HNq{WkJFn6L!r~VbzQ{>he4;9+K*W2M6l>=Ai6GL2Pg$rc2pVa!1
zY#(JlMkGEQ2WJ&f-S~)at|V#y;ds8rxkQb>hWV6!6SJzN7FwHNxuD}TA*Exe?dFDJ
z%p{5}X^9_~g~C2*&Tmp!z9j{1-Y1)eY*I|nMqyk^RJYue)^aVuY}vmlLAuI(Rc}^v
zH^*N<>YcP}P^>k)@`y-*SuA(Bd0hKdIkEb6r=%!TmQlPmm@)Ee*%V)DDEv`jz9yHX
znRa&+xZ<a!R%ITM=q3&Hl3}(sD5$V~vT0Q&BwU;0veqi%6J**5^=z}iDnzz61WXH2
z8^@($CTUyYUZMU&I6({arVO#5uJ-BvQ;^z+$}8=(%ttwv#%7kqx{+Q`1gEmH*;l#Y
z>u~bOS7ZeS46Q6Q)bfNM93~|hSeCvA8V#_#Fzr|s9eo-ru389NS;T_z%es_h1~VX;
zFSN3CSy(3o&GUw&%?ADi-B}5eY_%xmHzjT%(3%AlxKC;Jg<&C7(Vtpe`Qe}4+w{<~
zYJqBa#bWX`jQShH^BazlS7c#+Lq(r2gjuGg(G}gOeFq0T-@vf$07|Xtt6dK5B=@9Q
zd8Y9{2{eiNhrE%&T0+l`Hl=rr`R#dPC9)&IxI(ZAg<}k6x~lY|a@T~I_3>NUlu`)`
z>y%~@Bh`S>p}g{6%2H&E;Ci?wXi=F%cdv+6QSi;Dslp1{hz{l(D#sxgs4Pf*5r-Ws
zqAqg`4Y5bo7Q&1%g~5<DMpz3ihJg^PCRH(SDn>>6{31*qfC!VRBM4wJsl~90F#W=|
zKvs=Oer~n1V3&ojp!!Diw9ZJJnh?rwyP9zE*Jzq)Qm(iR`|BGnYy-St?)57=>4>lM
z)Q=&&JZHfo?9?~gsxZ|`W)UU;fz^Op80TOGIYuKrAF2<!6lT5^zviPfI?K~O8LSCh
z9Tr&5pcR?)8R3I&fN=N{{B|XE-VNm|`$xH%fq?=XFDLncKA<l`D+n=Qx_}+SdmN>6
z{bCwV@tjf4bIjmMCuz8Ff=2lW+#CZIR1jL~>tR+eb;=1+>eOo#E7F5Lwv8r?8pi~K
z8>*97XClvJctVD-=O+2%9P`w3p-^RwqA{opkqnJV8nP8@>TmSUZ~x+X=X!XUeEXsE
z&Ukp#`4<ECZ`%<agUsf<b9md;1GkTkA3_-`A7`!3r>}ng>z7(HomczMUuxwy#@{QQ
zcjogOMf&x-wYP})^uqa}L$xXA_T<3*=U;$^e$u^v_Junad9s>b<lMxQ)qnTmKkq3#
z$^YHJKku2pwsiaWz|U6Zjn%8{y&m4V3W|cOJdLtEbk+a6$>IBR4_!U*cfa}LqI9kn
z#kf-xBQ47BIjuVv!R@^JA}C6Fk=u7K^6vZTyj@6(GPYWj!nLKpKkg2%UWB!6togVN
zclg%Fz5~;mg4bvcQyePrO_R|8b#B78)`JOIhB=`8=s&auD5<G0;tAvkPZn2KpI{%G
zVd^<x*uWlE-~p!(Sm3K>x1!`eeEpu)msX$3tETKbKf^D$`?&L0@BH+muc^Vl`dD=p
z6bg%9`S8#E)DWN%^j+NzB9@Q3Lk|;D4YRP3z*l?8<qL!@J`(NqjnM(}au^LA@T+;C
zB-sb22dP)$z6Ed@-h|OK$~*P6=Zh-iD@^kEGHm_MB-g>Ng=(x)?7?K+2e3-z!#N(n
z6f+o?v}yr@bOK)L*iaK%o4D3A3Tgnpg+5*2YupXDvVRGCTVSBTb#X?d>LEf7?%Uyy
zq<`dKeV~1b;Jm(>i>1KPQK5Y#f`1IJ2i~@*ssV6S73ox$@Pk&?13nfi-Ko%QlLnk+
zm<+C0CzCU9DvNNMFbBgSQ1P3R0v|xbc|-~cZ~jGgF^7Pl(y;(y<n%KFWp$_yWph4s
zL7Z}9#TLAijATaUIKmzZH{pP%{H&HTLW?^3oFE-KVO7aXwiH!8=p*}Vd}LM2Giwbq
zU~;Z7#zq}Uu|xhOiVCePb*PqR?4ha>tU=G&Y=zM&%d~HO@E-s>mYFh=CF_ZU&M-{?
zw+7T|AIz>^GQc-r(XeSa%8Qf!ghaclsGZ}Cl8{xiOph$BZt<#SW*3CUBd*uOhf1=O
zWpyKuvRtbzl@>8WFq85Pi3Ktmg<;Dos16D<2I*Jo?~n*(LyQ!@Y8+-d7-gGwCdMyZ
zEzdHAY=ISxLYXQ08si9%pqF6oB|I>s6}~32>lMYMA!aQw-P7nZ;EVuzT7VA2j1KwW
z3d?IDMa@QPRVym5%T3^HMz0Utg7ZoUGXO&tOD%YgFeXr{O?`}XOdO3O%;ePQhk+49
zx9#rUTy?<Ks+%xtkMc#<n+oEUsw4YyNZ*Y!H#<vqoMn#>Ik7HSjDt`Tqi}+uOgK_$
zrV(pZxF_fz+D6=Pj5>ph&cYU*Ov37SLk@Kk`3f72NVN7ie2N%-Z5K;{Af*OxS~Zt(
zZA%V*EQwXY&Cu#A<u3r!j`HCXtQb2|6iJJ=BKk79d8r4sTouZUiZ{{)%fIugNQLgv
zO76L?bU&s;t9oan1czl1n`mddGdno0MF)M>#|A)D1vo(L`VBiIqx_^Mnz>3&hAoiN
zE&j%Y$1W?{#xzT{Eb)m_2@9!~FE$KOu<oDWah0m%T!I>kAs?qpzEXvQm(Q1=L@-j?
zT7Mvq_V0r&M>lip|76+Q1Ctn<W!-Tq+proF;(=d{I)($JkarvYXUIXPyk1nP<z_Ik
zU7R5(A4i<86P_jpDwwyEVQ{LAOn@OMjEBH7Rz-!z>V8$IkpYq=hBB65ka&3brlpzT
z8imZO#%L7Zx_nFtvcRJpbDo3oPIyf%>&zR)+y*1BoDm9Lod+<*p-o|p_980m^;p21
zYk<ZLKfy<p{T0xiV2!CU!OL>kUy<mw3Fhc&rW_Exk_gy6hFD}B`V%1Ers{8GO-uRk
zXWxT0+6)0dG5etyf_vp2V16(<BT!%WEwnn|Uf_5Pqc>$7Ms;1F2U?)<VV(zsNauMG
z3}9m#Ol#7un`<!JcP5PY0@^XaPuvYc0^nychdF^Er~&(Yv-_UTj8ok&$_()!-0X8X
zl0mPIW%w{|0mEv{9nlSEP^Y3}zZhJ>HVqnLgv|tUqDt$AG}mBamjZ6zA_z*;fcb2M
z0ZlfW67-X%HV_8l>T4FtE2m{Z*C{+NF&`obs<BZHqXwqS)PDwCQAj0I&Uj!e_)UuM
zP-LdiZe8gt<=Am%qE3KUal0mUSt|@e%nZt;&S3Fqqdc-49rIT=TU$`MA_a<r$$k+m
z5-T4oBM3z?7ozD5%3*vJ^f0=R?Y_EWjTmU-)Lq;!Mz*6kGbC)Lt6ZR(QbjibilewN
zLs%)~bey9c22koW8XL?93m4Snn9xJfjo=8&ACe7V9RwnzFrq92hmsaw8)CSSs3D<e
zDam*YQw|!SMc}2LHj-C9FzS`%JqidOI9FK@osc|z&{3K|=$E-RX#<U?MGsk%R9i#_
z2s7!Sj3gkQURx99SxttUAsK7Q1ZxaMe@FR2!6~W|wrn%Cu_dg?up~_`uZ2tx!T2ZB
z`B*+j;KqEjU+>Td5p5EnwJP+8{9#xjSk}@?_Y|d^K?JH|yBP)J7}YBA5<|_PF0rI4
zH4Q)OXe>Nn@2k^NF?|VZ2IGvU@E47Zg|Zt^m62LV*Cxu%2R;>K(Z-HZ!L!oALac8J
zn5v(SHU+bs@H#T_M0HeFHN{*PMo>Sqw3%58pCi$ixisf^lcnngU3*d^CRSJuj#|~Q
z%rrO<tICj$Djg=6+$rh`a8`2hul`msmKEyY#c~E?z5|PuhhGtnRR~79H?T>KLoyMe
z4}^fIJiQ*qFm7y-f%TmuxFqHUbR`&9fcR9V{thZU)*={QOgB}`3E)Zib(rE!qWt!-
z9=g7Pdc+TlVzCkK<kO;z>>`@N$h0sy55a0WG88a~CvyRC0#h5ZqXZz#*H&4$wy+sN
zQ_Km3F^TBb1n*Cgv_xeE7y=1NA@~ZS3g~;Z$?`f!Cq0L%Eui*08m#lJ-~H7fgNb%T
z$Js0bO&Fk;q-*JA6)}K|oN7Z_7!nUPix^LlVLb#h5a_w!><Xqag2h{MUBRa|NYjFw
zX0WEAgq#O@HI2tpxhSQA9%@RdgON(1NUW|hlpmkE_jqpm@-O>4xFZ}y!tmc>&O16Z
zcq81rz#eW4J-E{4V6X<pjSJUY?6sxrsJqmCzUOc$_vXqiTUIA{HI(bR^?JTon1~wn
zd=#FO^eoZB{0gbh74u=#GEOr!UK@=?w02$2G>pQE%uj?1Rjz*(w%kN5empEzTRh%e
zjb4&Z%af$Q&dTr{VOZ4?QnS_?wR5Ca_!{|rLiMOYVA-5rkf#v3t(|MovFb1Sb!+mi
zzsL3#|AZg?dalt`$#nYL2sb?A^6eY~3X|-J^h)wkQfV8Q$U9fMc87fcnxvRN$6gc0
z!3&o!*t^4(+*eri^Nrp{)Y@Fn2SwQ_$D$Y5cjZ>rJrS{bzI#D(`m7a6rpekkPeK`g
zS&A^4Sty)nkd3l*j#hbXO($~GCh=L>+FW|NgpY?e-JQ%C3pFd@jp(AReKA3NgKk7M
z)L_v8&#?u<Hq!|{e=Tg3;{TMqXQO!3cOewawXHjjA_v&K>a!m~&`O3J<rTd!w)7(U
zrj-?`AD0v3VaiA!kE$s&o>>Ky@JR}f^YnR)^Q7>`yU1pqC02K%5tfR0|2quyF5WCy
z2(Zj?gkp^Rgaihy19NU+)y;C#7r{;QGr%tfVCbFaFunLc#-@1x{niiv_xJ2}Uh~>s
zJ$vbwy}~|utjl?hWDnck33gQ0l1<0**yJ<3P^|1-ru}E1*(<k*^0F+P0}v4OSjlmU
zg<Fz%g<B=^+miW*aqb(a=eRW`l0r&SugPS-A0+j4x7AlaQ30&%%Ma<5<jX0M12^pN
z<7IvhZvuQhDxNF8m{O7X!Vv);Dhe&&Pg>suz|x|tJno3p`%i7%kV4eFl@$6f8h<F~
z7m9zAVzp%JtJSo8tS)g4{8?=Y1udPDA^q)-t<RsuU4qX!1?`fbsp!f^@HBdqL&#;f
zHyD@f)&_7Q7Vh(^3B~!{Y%2N)hzE@mfa$)Yavq?6O3D@`yimBliX2n8H@|fc_|_&;
z)2G4~%0R)u=49a%&?Z@w^T`IlxlQ$KEh!W>=&W$0v06W;K<o-FDPIqZtA7&$rZS+t
zd0Ih>&2O!MpyGaTydyp^Zr~I8z=;aiqf__Eo7V65=5YQ6;<0Eiq10)GWPo7N58jHQ
znQmEoMp*t-Hqe|9#HNW>8r0EX`&K|KG5S;9l-3Ue5<|6vz@gBt&Pt0wPp$hxusVWB
zT1}p!Q6g_*t8%Lla+dT})%j#AH(L~780~R#Z6O5h!<3WW40te8<@`J)lgWIM2Oz=+
z(qh-Yd>j=}n*-5iosxZP?5Cd-_I~-QlWn8iIO;hqz1S&}lET;?v0892I?vqX*mOWI
zxHnK>%mU-^;g880SX~%`*W&Z{NY>xNoyb<Prn3G`7GPjlEVvRp@fzqfHI9Ob0@=%i
z^*bnxCXeFj<mME#>cNZ*Q8g0N{rozNKAO*>&YN2+enLTQVG7msEi6Aq*v~%uzNY6R
zCg2Tb_@xZaX=-O-3W1NNY|PptnpU(|HjB$?r53`yURvQ9G|iOM(TN;zyR<cNt1|2d
z|BaJc9?=JMnv<)a2sTX7!9k*Rd@zW39o=SY9?;QzgIg@2;Nq=pZLc(~6qUZ!KzEoy
zrH9~zVGX-U!Z5Ff^YeWGg$WE32TfZ=rv;@%tIx?AyEXGC&FoIky_w4?V$f@6VWfnu
zJ#vRn5s{%O{sp~tPzk8sL2-+eULo-K(u);kSVk!eT3(&6X<@Bkz@SPk2o(Ax`nguq
zO9c&pt)|7Wk<)gsXVL2rO9(hxBKm%VU{G}98fgQpwxM3RDka+o!Lr;d6((gm6!50b
z<UZwxe}1pA!}AF`MaO!y2731Ld<z3;N?!F^o6te}uk*cV`3>7*g$&x?k{^kcW2|yU
zvPiAz9BqKUk;V0atzovQ%qU|xqph<kURDUOFY2u+A=F5$%2SfHFv`$;h%3B?D8ibW
zzOe*E9vqP=;083tUK5#LgSn8MBQVDuJ^wse+oUAYqifYUNk6o0t#I7ua%$jY(%yU^
z$9hG9y845MsNjXxhWu+Q=u&%q1;LcT46dzgAx=#<C!hnu<bsW0;H&|@F<@haia=4r
zuvx52Fjk+pvaqL*$<3ItSlUo2iJjt`_5N%8Y}(WDl7a|M+8I{g&BOk^GHzVJxRpw@
zghW)p#2aN@mT!|rc#}jh)*+z~<#v{q=d8M67B)Gv<CJ@hrI^>cq&KtW404!@kQ1?K
zAE@y;wpRkmJb0m?iiCV~1@9ujz;N%BiVg=QS4tCzZO)|Hmk}5|u%H8U@FVOgnD$Dp
zM8SE-5p+NnT*MD1&~?xdMsVxGuZ+qeJ5$MJ;KL|;a!icq;B_f{1@9dJULAlF70@Fj
z^Ln_~4~ZB}!2^ibw3`OtJ6E6>fN_4E!(4~m&#_SQN$z66W4V(L`Y8#-hcbXw)az(i
zWjgS*QbpBIV^zTF2t*5LrsGQR`OI-1ro1rs>f`T8*(-?WyV>h+y_<L5K6>cTJLna>
z^WR@O$5K@J@feH}!1HYfi>(8EdjDNmiEp}Z1HyvFK7N<rjzz~Rzrjv-c7nlH3b@)T
zd;JmcT>axa7x}FR?hwzPe337`bCE9<>bThFe{czrRKVB2{$qSi3-i}|?-b@E_uswF
zNA4Ep;nl*-etPqH2Zj04Z){#I%-?;9riJ;Bcj@chTPn04SS^e@d<WqI!~Xfl)*)Vl
z2tLen_%nEbMuDTkOHF@3$Av2ZYnTSGnJHWWn8vX4(fW9FOr*?2aD;+I6`-Y44^n9b
zg_@$2eg|&=!WH}yraJs1Klh>koVq-4O5XkO-t_}MW%YB@mr#bE@Gw!1cOEz2|M}oS
z&;xGHkc;EafQBf#7E{Y|6JwCkO`3?*P4Kn0tR`>}%VeJOwMNH83iI^SdgQK@NPe8h
z>O+h|fmBMM4Jv@E_5mU>u-J!ygHBmg6!9iu03;Zud{Cp8HG~3?s?EX($x{o?uQ}(!
z3BLhjgj?1)H^%R~wfm9a0TfkmoEB!ly;FiEh|2Z}s9N}Pq&^ORNr>rOd8NyE`XC%S
zxYivvLUw{If__m8YRSHm8R2eD=DCPN4J37mbfhqcE<xp@;O<O{huTCz>K44P08?9t
zsYzhqJ!KfZjV4d^l5ii-{?+?fhc^qM82FjH%`P95Y>_!iWFgCy4dwvl7&RkcJ#>UX
zg|Y{-4$*=`9%!*D<2Ber=j(8MAlT;R#8OHKOo#B%!6iW@O-q$0HLIKn3?egWla~;>
zGSv>^N)%jChUu-p&IK2+eYk{1HKuceQt#|Sv`9bd2(Jp9nI$)H(_8(W)@Qb1)+_da
zBQ3F|kc%*=@*-R|058+Bw8*A#vIhxU!u(@eCrDXR4(TB#nRur@6U|vhN?gHxHZqEi
z*vV4y9ixnm^QsmGP*W7pOlz8aJktJQWIE?!PBR>@Fy<)*Ys_(jOVABb+6OE-DohO-
z2Dg*UOu@-G%z%Rz#?C?KWvjQRdO#SZ=zsMZB{o`tSmRGcqhyS3uU?!TqM>1jz`Go^
zmwMtw;bN{ebTr3lhl{8sD10?F=D_C{4lv<B28wpAx*)C`6EIV5_B=VgZQvdt!J^}p
z6px1^j>mGkV3)(}Bc+IE^={_KHyrz(9g%^xXeXfIoV7*nsKrCxr|Ky`jmN9(c**O8
zwkyNy`HKr|E=LE#>;7Re5p~#f2`mu`aNfzV6qFD@6H4Suz~<rB1JJk1Zh4tiqarCr
zsO7jwpdAe<5O<_bGa9>y&lr@YYUDronu-~kc*;_5*GL~TF7EZQGe#_f)?+?>NX|L=
zbHrH5RhQDmrE`VwB_2QFRQZOL)Ekbq_`MG`$c`$iKiV0R>Jod|LR`be8EYpF6r-&N
zrRcm-9p}*|G$o>TrD%rLqr#E|UZ1Fdl55d9)?h9vBJqcje~H0i&xhFwPVl+ZI>%PG
z>5w{k2wGK0h>ZFS1&YEz4Xd{vz8{l`*yDqMmvbwK037h~b5#ScO=qIOqFK-027L>t
z1{7AJSpHN9xKULf1=ot~%{An}r=SZVP)~#@aFNM8h*c<{EM=C)!R@pVDT7t;7&;yr
zWnd&2rb1vI1GDA)djsz=Ay|ciE@wpc7!NK$V`@5n%B!JlDlLyJVTpviEelm6#uj#l
zX^~b=AUQA1m>@EOQkVngS!RU|P*sTLNE1sXKtB*a(kK}cSf43r4+ELN$BL#4l@9&{
z#5nF_n91O3VgX?EhbP}Vpka(dl@1jl28QTB`hJ-)ofPw6Uf~!+rp7B7jA6i4QyrA5
z1m-c-?F{O41fn2@!zw_vZXLGnSzl9L57!UF&fp6o(0ZY2y2GKdmW0&AV1-AU0^RH<
z|8G+*X9h_wV{S_086H*%02>YttgsQ)PbnLB&?KH$E-?Xj6;X7yk(Cd+fd(NU(Z@rK
z9MmfU2v1|0A|NnOI|3RT0OeqoO^Ykhb!o_Tpf;!o3(HGvkhlKZ<BGEg3(OBP{^EZ2
zx|4Aus?lA!Aj<egVK(P?lZ?~3&4yMx);cmnn7dYNGrV8}kJDJMmf*!fzi0C`TYRr$
zy~D_J=yodREHo5j64j$A<rQEh?D;dKCLzJ&m{-Aw(DzJN_m%Ilj6)oSy)IPOyJ%C}
z(>vCuOmw?FXZQNOp5n)2E?I`4SpaJR`8x|e`Uqso-4ni%D9+`zPy~vMn@rDMw8um~
zu_ZO!D%LkNt=oJAv2WKHR+*UrvIJU71-MKx*P>cOR2pgoKWR6A^B=&*+#r+pM8*fD
zWEcy|<z-UMHT(g-%=Wn+6$mpay^nNU75+9kLZoKE3>(lwbQ&2zfGF1$qYMtS!udj6
zB<{+J$cvT46gJNwv8#P~g8P23;$v=OFfAOZnGRx!94k**Ct)`Vvd9AC_IE#t1tbGZ
zivHZ`A9TE4pLQJZ5yRw|5S1;y<6_YEGJ!I7mb#pg>_`R{XlkVJ@-O?r8d1rVlwqU6
zupCN*!M`l~K5R@yLHY3r1L%~P61!*_g_XLQhMz<M-OW^YKdj@keUcWybq#;fr%n^f
z?@?}I6$9z@K{!2lGO>mzK%<-i{~H*{h}gk8?<7#5X0Et8j(QC>4u=Zz1<Zs6ENm)Q
z0^49Hg#nz7cf%Y<699TD-KYs{`{=m6@2ha5^KNE)&dxE<Mmf-dS#a8BE*s94d@oq@
zobL!r^F$EgZ>@EPWS^0_jO6D`u1g|4V}QGmKy=v9U}I)i%*{FtEN<n}W`?~4^IqlV
zlVIaY9AdnSJjMz7D++PTT7qHsrUwA-WDq6s7i}yJ4!-7qfQgTe!9FUDS$o<>T`2)a
zV4y6*tOuniilcbdY^LA{kt;D|IE#PB_d~J8N8q|psmvnO%iX+K_6s;+%0G@6pAw{#
z0|N%uP#BJALK$TwuJXIiPkUrYb(LuwJ<HU#`x&JSvjml2z@413Oc(wJ;$XCrF(K2}
zXCSQBS-0MD3}f<!Lx(daCZd7`n*<wC3m@b<K8<1q;gKczW|10a_=iBLg>TUsS_`OG
zp<JQ=;-hBP+eY>|L!Q`<+*oIGIs1VR{IUNze|CaaKFenPkIqgw^?}k;bm;xhcmto<
z{?RulRV>akj2lN?8TH4V6V;*T?Xz8f>Ob5wB+rSra&q!bpVFe7a-YgAkON}l8T#@Z
z8EQ>leq#CZ$%DJYuU|Pqc9p`%CS?3|`KDNqXGuafCNY}ac<CZJDGrMKbx{vvJCk3)
z45M`;<ld+jNgYu!3VCa(8|p4zqZ45ZYUeGOXL8->4CMA7<;vT(4Q$=!4ur4y^flkf
zCDuj0JTh?5y$B9JbY%ZR&p`-6E?`3CJFOj@Ka^}6`8hV_o+slGugtRU<wqXsdgRRU
zu8WsN_cO6Uchq)<mv7~gfejNYqWDeGB16zLe0lct8GdA7aQ%+>U&<(?r&y!5v=SZr
z8t$c5Eqqs4tMK)#KUQfJqcy{PS#pGjlSRp@rF1jOco;q3Xjur@=pg^=%B513;1@u7
zev$v|3tDHcO$(1ZL+u9^b3^T%;iXTNS#MnMp%(4D>YqQD5>p>Clg?*GhT+iRy>Q=-
zIu6tmzEkSH>X$@{c^3rUl72z|JtlTCx+-Da7+*w8d!yKq(%2~nhY#5J3w+u35J~*u
zl=s%)VBJNss~>|8li<2-8{IPfs7PgyFqIx6@bXcet4R3H6BRsxhA0gW!3-Tf@BGcb
z-2P3^(KnKfT`oY}ivRh!;+GceH{ajx<HK|xbGO(Jj)M;%QDAG+i_#sL&%V-iR2(|J
zbz^SVNa5{LDX;dQV;7*L1a3SQ?;gI9eGB9#Zb77I?2d2StABr3+(zkE<*9bz9JUHJ
zDYBS)pjSXPk57fSMAxu=n!Z2T{wq$3T)z9&$BzNz7Jk3@w@{Xf`LFi9Dy=ucoa)(K
z^3b_b1fKT<80oXJzeOv6HMdHo`=D;!E02L5_DxxbSJ>~<k4ga77Jd1?Q8&fQlh|IA
z^5&@!;OzcQfAF8y?{Eg&0F|#gPWy?YVbK1Wqx|MUZ}^X;n;bmkrR0%{S4Ikx+OVzd
zaNNQqP7G~7F~!g3oXi#o5yd{_dWAw0+Q6eLBlBQvI1j<?xavb0SV>xiZz0=^P`)xd
zm^nsH&aE7}_fjnXYiJ}_TvlPNBR4@Ep<Ue0x{n}YnE)OoKB^=fMh`pJNNF|TU;fml
zNfeuf1$qS3qlWu^N`eC;@ZIYFwFbVY{cD0-=%R&NMGJ7QN$W-KeunwmyvM#zNU!%8
z=uV}*{m_1iLrdqp0bD_+#;Z$v#YADiZo8=d^sm6b^!{IC$PpxvuH%(>9@qju*fv^{
z>`1Ay070xbCNurtPxpAEq_4!t!2UL4N99Uk(oII(dNxi@fBroc(0WV?F}evz)v$e5
zCL;xECElU*mQ;othl8V&dKT1oE4XP3;OQ7XVk>Xb{!@GsAa#v$G^!*>pZB-xc4ouZ
zBezG0eR1<JDr~5o&F>ZTP=+hmE56_f&7DA+w%1nLZYgMYBbiAmr3BDB7Mto(D54?I
zNovoL6VPWO)5MZQqLjI+2Vrq~X3-(d*||JHxj(!gcrMwi%<HemXRbh5O<W%UY#4j_
zk}HMNwEC<BE{2jikKhi5OcmT4Rf}S0aZQ=WsR5|P#w5^}0zLC^`-xZg>rRtyVH<PX
zMaFD99p}CFUPEjbAC(mymwwdWy}f0j76eT{?ikLz*_yxRwK3vA?DomQ177|VK>1*%
zdN@8ak6V8c{i{$U5UsA`&;(mY<#KZ?4##ZM{Nu8Arn^objbG}adr_QkV=De`&pj9r
z0B=)q;-(tVwg<E;+ne&6MLT<}0Su46Q11h|<dXKEBPyC1Lef0E**!9bs9E`@REIMk
z{`x%|a}Gc-dW!E>AU8lz!Lz?DvkP7Zh+Ywodb{1z8_-}A{R3w_#T4!0i#&i*RL_5(
zF>kl8cOp?3B)?bDzuJWh=#e!D3<`TOg3K_*tq?h`_}%Dyh<XZB%t?CaJt0Gd_q2+T
ztDa;cbCPHBeGPQ<wEsMgLIZOakManB|0#?mNQc3UC2;9h<ul}f9QNKCxZ07y`Gzh!
zIid`oNS_A~I9T4{PAJMEjwzTyt&b}L8q45qQc{|5LJ-Dyj_kcsgJN~S&pan5d<-_Y
zsNrNLe^_{#&&V4iXFT-bn!t4OQu0e&d^g#<M>Z|9UE70A?q}r<k&NeCUk0v!OEzju
zOM!B#(S42}l2z-#Pw4Q#w$Gu<WE(NMV^*nyu?~Ok13x7k^b9_1zs*WY;UjX<!9-KC
zp^$}L3=!y+VNLjj@B)E<1ka@G&GkWL4tc~vxE_R>K_=S7zM#Sq=mcuC38hGzzE0ZM
zXW!0YqqXKMi&uOcD~bvET6L|v5kaQ_5EyFR9JVF^7(XW$!ZxO~8XW9Jpx=||&_e0o
zpdWhs-+mm7)`!Gbm=4Z%<ZpxyjG_;E3_HRW1^ic-iZJHAKy^xp$Z1>#>Vp$B&e|HV
zaA8gA141Jw?Qk3bR>`G5Lhr9XIE?+ztYlPrgabOxGD4w9-obDQ1am;a-INMeY+w}z
z5@teuLVtGiy-#;#h&N;lXBOKnon>cO^L)3X;f``|z{aAw>|!IwNV*bt*>6JR!vImt
zZ}|su_@r68;NUndA3j~WYU_n-PDv<NN`gV5JA5I%uD#&~>P=u)9>$(*F~+%DURhSs
z#T{hc#qPFH4IWR$ys+4_sqR=(cSSIKg)u9*znC9&{%RH8uBvYB?x$8oxc?a4zA*7F
z0u1U}_(|;cM*#S@>{S4~@FM^`^#28b?~vR74kN!qZcFEf{&89EVq}op|6am-e|tV<
z(I2`0cfPtRoE^Boeflno{?$6v#K6B#)`5T7>8GCtiw6FM4micX@6rLg!>cmjAB%7A
zw|D(IOkVT_kn_|5gyRk;Xw?(I6PSgffVC^|v|*f^avhum#DsLE3O7efUDwoufSC;@
z4^1>;Lk!;n%M*MtWG#dfY~p2jxgzuFoiMZiryk`LL;vJQ?l*GxJSH8H-NtCg^8S%I
z&Q0zdZ1Y{Rx+LSUpB-xte95nVi)E^v%iFy2o6bI8<i}<A`bSA|%DTQ3?ghDw*hRvN
zL&k(ldrLGv!rDYc7jk*B48`nMdN}uvLHw9wz_ErXio#iPog4arIIMs&L`M!%7QW$M
zEb(a@kh^*@7yZ1%p7SRLy4hGbu)=6}Ll%SQ$pr{8jdQ{6YyzF5_~GYt*Mdh^_HEBr
zm5%)r%SgvC5njYj_We<A<v`Wi?>e2f>y1FJyW|{ou4Dn`;H8(pEyf(S$E8Cp3uXdb
zP^5-iPhKXp{AYqgmJ1h}gETe>U-aV{U)lVAJ+>Jv{t`eRKs+&$U<_n{D!ohzu>-b`
znP2pwhYfDbu<M~Z`)@u3^>2FBD-1b1j1gZRbRu<F9md}Z|Ihq&O{1g8ra|{hWZFIr
zjaT?b?wUb4XMhZrMnex!v&`rbh66$5TnN_9n5fuVY+#cOGD#Gx5G-SbfwaeEa8$Z;
zHH$`uK2l_2G+aX4@li1Zg1(WBtff_W%0TegqS*t%m5iLXX4@S$oJ-5`OP)hQWjY?p
zg6}OkBbH^^b6iYIcl&zJ=*>~SMGCrHW>0WYo(O^NnxQvHZg_nFF`aVTry#HHJ_wM+
z3i?K9cU*+37%*+h?}yjbmKl%dmT-n8oABTdgd{Y_L*V^7cn%bxF?A)UEe2MAjsrc}
z$s()K2U|vXbJv%Z0nDQu6!HDSLL5POlR6}$gK0K_(6q%p6z=u_rPlkxcr6{Vn7gfu
zOxlO|&Vd0vDb-X`&sC4L+({`*tlPF;V%sx@aL5a~W6T69uzM=jeE>J?vB^vcr5XsW
zwD>sP!icRC0Fwm>Z#(tgQny|-s|e*}BiSJA*oTz?;4H|9MZCPf3FbB8cYU3Zr^s?{
zi1&55GsHEm+(=>==wKwjesV!NdZlgGR{{CTWWq21GtnCOt~1jZdSLFrE;8+lfit{1
zK2ZFszeVnJC}gXmIn!Z7;f%<L6`sP@#T&zOU7hTjII&W<t33_7(MXDUJ%aFdBdcPS
z0uqM)*C?Q4#8!y?^mEoi6h2Q1bnJd{l5W05&X(;tr*lGJ9CXR0+)nEvJ0Yt$Lm*2&
z<@13PN%bKK#7bh}jm*A(;B4cdbMbjX*28rRpJ%W6SH*$V_|(Wb(z3cUg##jZ#gDJ?
z{i1I91EKi0$c)h4V2eF<7Cjz`T`YopBFhR7vzVXr-y2^@aHq8wN#Rk6Ca-TMTV$OD
zi9O|DaRXwTCSgAOnG(4&2NoY8suFI6dK=;FQ;=$|IoC~YfBlr1af2LIXrokvjvit^
z<PV)Dc_`VN{vwEnn9h<J<5&)E0yEbP>M<mD1+GfSbmy?-?ib|1AZuGt^`Su(J`Pdl
zm@MTHj47yOf?%VW)~QRxJ}iXyfk2R6!jhKZH_%yCF+=hG_nPZW9zD!%ihtc99M6}|
z0iR!Xy!|48XdS-NXt*8y7WRc0P|F^XGhOA_eG?;<IT-|snFpBL(WS>0{2dQy6+pOl
zp#+V-rTTPHI*{kC?`G1&5?zA+#7eB=UDz$NZgdi$7VxWF>M=|s!y?W#pQXnm1Oh5p
zvHO?T!N70?Ruo?!^&1^b9R=(i#BLik5E;)4JR3QQklZhx;AKK`IwcTu`#y4ln40TU
zRi^A@Lcu!}rQ9H08o-Xybj7fyaH&jU9qDCQO)>^aOc)8IXs~G(rE4AYZ=V0SX=g^n
z11j<bFg+DOH=?UT9bz&oSq6-S^CooB`I+3jieE4bYU2npGpuUrQMZbnYGDS1YO@yc
z47ST-$8`{CO&&ptt;ZQK&J!}w9=jj`pOEl%v=+u1q#LJ`yhu7zl$*uj>T@9;RsG}7
zu2Yod02J7~$90B?XA4#FVNYdb-pja8+nIrH_#rw#d4jVM&BdD;l;P!BEU}OTk61<y
zp#+jqctG_I9nA!EScRY-i?M~B;R#r~6+)Q^(`gPXf<hr?g|JjDB6A9)hadj0Ye4qh
zGIpe6*EvUu7u>wbQ5#MTQyO-|V`qa>u|@Xa_GXWH&%iy4IXAX1$LB^?;%{UIgp~<*
zb8IWITe<EGrQ;5DTnILvGB}i^G}6O-Q5qb<Qozo8U9gf#gi69#ZCZ@hxloFxrFY6A
z1oNnJ%~YYb{~7u7N0eQ;Y6kgH>^D6w#H{BS?qj;s+cgb;$lRRq-9w4k*)w1Zo^hhg
zK(1{&+jVDWE;=8d5V)NrXKc^7RdpcrY@C-<cgCF#q&e<L9KSZ%a{ZH{JrP-J`>*(s
z4n!H6?IGU?F5fUE^%Ew-JbZBqUAL)Eu1F!li81SvCc+u!+T4G9xi<&(G<J-DP6n`y
zGBAmdA)y0D3F14}SORVZ*@Y2}T`?`I1G#sQzcYd@WmLV4SJq+6(zSrU933Aqb=S;v
zCLBu!R&%V{fyRP$FECA1!!?n{If8Y8YND&t@BPv}@Iyw0;<&w7dHFU8F|QJdy}~yw
z8&M0#oO>X2%nOW_x8>4R(c~F%QH4!a!*&xGA4>0t$yGCirEjL~%OQX@#{|Uq0d}s0
zDwOCYQw<637#bB*OYJ~}ZUhkdx9`C|Ks9C4kfQrJn|nF0ltZ!;zn6?;(d%Fy#$l$6
z(+b%{h<yVBH-dRD6^nz4*{Gm)PK;vANhn4a8E+B+lanYeOi_#>Ta^?;3~-t&2(=@v
z5W?F!YDgK4WbWtxA2^VF_^|ICTpr4Z9RS$}F|UsLqcBvq+Zi6K?$AMA$c%WR==pWF
z%ieBp^IX@xm=W$pPheS&Y&_2U;X36468H`J%eLZ%4)B1bNA`VC8$%9PvwAYhw@}+Y
zYo0gdcumZR(K@Dx7+QyBC}fSRsG}{i8e;oL9Kp5v(8FuDXFNptI#!6+L3(&w!1VNR
zBZw?}NZX(lEM)$W9ypLmb>CH@Yo2Rkio!C`>tji(Y7`~eu4B;=_fGg1g7#znM4;aA
zOTkg0g}z@9Qs$(pgr*NIJqaR)yb5sVFw5&f34JD1Zr;cT2fdB{cKZ_ok)YYG5y6F3
znVU7glpA_YoFD^l`MLbTCG1bBU0Xik)$>!s%l1T`zH#N8_Z|03pBnf9^QH!G@SYd_
zecMY{<43%UZ(h<iih=7F9`TO7`HdU$FGOqdLiKax+hUuaKkwZl-pdc{oVaq@uiHDJ
zto=kK->$g37V@7ue%ycT2IR+`^53tV^`8{+Cq&)Zl^mLTq<&y{zVoGP^7mG*!(5DN
zkO4GG=b}?{(bq}~1aV2(FE=JHtSlTSSO%wAVQE3e^PBsbemdc&*#!CC=ifJUaB$<u
zl@s2SccN?i+XT+%HBZ0z>-(?zNhN<!?3Vk*^1zbVQJHdPbHj5v@^bD#bo_ViiSfeN
zuHoAgx$X(in;O|P-`V}PpSy@D#`?XH@xhx6QsvQC28tumTrO(6JD=WNnd#d1oOf-6
zf7W}-n^=zD76*1=ufv<+HE}4eohPWJulelDjmgqNeK!A9Ke{Fm{C?!>ugE&NH7x%d
zZ;6dkM&AvgMNUe{N5S%i6=<aUZ-mtepow#2BCPW|uOgeqb^a1ERNPl6tTYNw)}klF
z=YP6$)=TxucoxS}`n`&;-~Htd*?wdhem9`>wWWnP#SE(y`=8S6tA4{99s}C<4yDg_
z0dBCj(;lr>+iiMu>9Q@X*Mz-H@P>T?eB8&I`FuMElMN0zcsG-H>WT4Ww+)EXQWl=a
zudat@p(;;3pVedz$o_!8NZo2EKVdE1A?E}##cRAI-%0<F>Yjhs`KkOhVV@^UIrlN|
z!17>wZ$8^+@7h}haKZ`H9=I}2%bj(RE5PeHligjlmc2YE=}OXF-`d#ar-1C4*}?YX
z$Ji^+>>fGuc;U#g_8;b^_!s5wk;JoiEFTvS{#reI%wKt~%L31)m);)n3+GF7*&W`Y
zZEWxhUVD24>2G}KuS+B=e`T)`&Y!_4F2n3x@z=?XIQhf=!*SwmSuWP^n-c9O>Q??c
zanIk7(o}U$rpY1FbPxT2;lC+sDTs%ruK?+%;T9I?>1<d?HoYpdH(V&{4?vH+wKgFO
z*P)YzLi^7@xdv=_xSieM_>bkTifnr?#N6xim22|0Cmy@T_g;AvEa+A5yq9EoB@qxL
zLR<=E;$+)P8Sq!+F0b%k!WID#n+h+)FD2d-ACr%I{>@mV2?O4eD_=cWmSEer;`mXI
z6^+66_J<Dmk9vn}?WLY0CH;_IYQ9w122kJHP`SM#zng6MrnD#DsD5qbOm|_f@lv}R
zteP}x5_cM=pAGHox)?MT(&>-^qNTXMQ)k7mKvk<3TKA<&>Wfm|{D--YoNZs@W1cSr
znw8fUmgV~sIc(={NWF~zk*;9Qa}AshbOmBg^3s{^{JF-nR}LW;!3e5{yojTBkYHd~
z{0_FT(>##))JQVY%=$pub$RK`LAJ*met`_!_B_TaNQ63kku_Hyv#sRKr(lQYH_gQ_
z&G+%9P3zSPYj3U1t&C5Fr@o95ZehUATkBgPG){RkSmC^x1>r}#pePl+5T0v5LJH+C
zVEM^s<^A-B*WQQ5QU-;c!TGcfQkcG!?1j`81Ens5v*fI7c-V63lc|-zTUi;lRme`+
zwQ6$Z(De`-JVfEwN-Hr^mseKMFC}E(kboZclgTne>+D+|JhPp3v=449aU2~osqOa9
z9Gv27hI<5;r|k$@VB82wc?JUHKA*ALv!b~v&)9y6!XY^c@>`_0qSjy|hw}&-WT7k0
zqFLz122d@O^ym&%HT%QgLgM2LPKF!G>{-S!yIC>N_V{rT4u6&)XYC$&iLFn|#qPk!
z?fEax?)KW<d}`%iW0)X9@zNP&Mfu1T3@y;gOFt0Hhcbu-^`j17@rIC>#2vnO@a-!j
z!;>w<hV%R4KlFSy@RTP2dMk;)j~|yWwGX14NH=jD$1wI)5N;3<gNrlc{h@VcJg?Ps
zXtd9kED4SA@l=<dx8P)_ig)ZuY;CRIS4A&Nb?n8XRY`wkr!p)K@>iEszf3TVU}q?1
zK8bC8fnM<&qFnMJq@9y){}_6G`9>An)Sileuq^yvEG_T$<91f;@K}DY4{rX-$nk?F
z!fxaA#id7aW5#YE=xk+Hj4Qi68_0Ax6OYNlnY}!mN9)abH0_Jnf`Fb&<chx~9UvOV
z=gmOBPQ?5=Am5fTD#4^xD8*ylOk@)oCgjcMhZP*Af-nstUQq2akxQhB?-gU0zuU`*
zDIqeu`CC`yI5IpVA9v{ux%QB~&#TFHc5wY;&ei24E}SQO)6fXg+>ErZD6lAAUFm7j
z@HqBSY@NK}V*^6iw2_9SW<P-HYxlngy{MSCusUd%xBIFGq-)eTS~qW@&YK&m*6OYS
zp&;Qxiy^a#p5G^x{^uJ&)y-6_dss?#>+5b=qS#mb0A?Tp{?h_A3{uYbd#F5!-ZthS
zgcknzMv~WqfwzVCI#&lP_oi{5G!G9*H@etc@s*kmKE1w{j$4|h!N%NDO=RJ;p&UBG
z^scr|j-{`e3#~1uuo;5pU-Qq<ehY2+I@ewB$21v(0b#LX?vv9lRZzku%$KmymL!zy
z7{%vyWjf&(`N0^+jyG=(%A-d;mx~X2d370ni<2Ujz|sBwIpR)}0p!>*_T)-c$7@>^
z|9to9EPPFl;kq+h>4EC9Al!yWt6CG_Dpglw%0SF!GjejEJLZ?L?FCZ+EZ{WR;v#|M
zq&#O8IDB2cxoyGF?Sl#&L6oong$P`?n{UmHF5TIUghki$hvAw(>I{$b5rVSKf~lj1
zLDWZ`)rGe68IQ$#A%Q7mS6Aa>0+nP`M7tCExF@I>Iqzx4G5Chu&WNE5-fFHc<*vbx
zJHwPq`(UcAhHknicCPw88LZ!EE?L8e1LVSE4M(F?Vl5yipa^bEuBNw0Gih+-V?=Go
zoXJ~%@_+qg!kz+Yq_=qTjyQT1NLN;Y^gm5ZalgGvwE?r=5l8=sYX6VWI26{Ynt3%b
z1*X+By~X`^RLws@r~Qus`yFZYZ4~8Q(r6&^I~PeUrT-bR_o`0&>zD2pWmPf`vc7te
zAL*;#%-#C40=z9#U8OO6ZHm*=|5CpuGy)wt8X%^Iy)J+JZ&KoS3H~Ic=|2q)Rsh%z
zGKLGSKBq3B0*^>hpe9XUVHBP|9<M%i@9NhdKb39Zzq>#3AHS?1-`m~C>UGlZox3lj
zvd8q=>EmbJ^@c;L4hXt0$3%5ZE*bLJtn*O>!#i<=_KqqUs6uLaWg#bCX2X5<77_g)
zv&LmIE8~|0H7&kEb|5+Db>yZSN|lYhWSnB3_Qn1KMld$)I*upUkbay*10~XlP4xdS
zZSNi($9bN4RyB)qQRX`6Vi~D)5V)#Pgg-W6nrLB|HjiR=RTscQqbZOu<6tyCHUQBK
zL~CqOk|$hGGO4fX1Mqcsfh1s9ZYxR#fZ9rnVH}ZSyhx%sW`oV7MZvmR$ue1QmXsI=
z_U0rc?M#?#=6Ih1CD|G0^2eS9C0zSbm+$(#&-;7lvK1@SF2}0c;`UCWDc&;XE>a10
zRh5ci!g*>0t6nHpAw(b{HyRJq+n<94cmYxv%wzg#FJod<<;y<0bUU`BP^&C4$Fm*o
z2>iE86q{hCtR=0ar)knjPsEP-qGlzi!XvvwrXfI3$onHg=xFyobQ<w8RSK0RKcU$V
zD+KAWBEX~L@bltvr_>A#nYySi6X<^ae2mAyeSXG3vLLm=bBm_ojq45^K2Q8|6Zgnj
zdsogHr>tTj=*eg_>g5fisxfW4N&;+Rm1zjBrL6m5Hl(E3>UlEz`YY@~8|;}XT{Lps
zTrwhauZqpuB1RGqXhR=CHE`<=F<T%Za(wAb@`5%Ne2h#`rj@8TNwr10zDG8*(})WA
z3B+W~(3NQbn|``MaDnlgXo)@n9Zn}n4&>d*h0Qq_)xae{)kB|DwS1LF;w#>cDhGm3
zDv4G6VQB$!&SXeC`CtR*XqiYqE$tX2^k|7?V=6BEmPltzEi3yWW8SL4D;{Qm{*B&n
z<_Ju%FoRm9u0$p>L{oPr12{0#d=sFs4^$3-4v>No-nX;yjyMbA1af(4fYt3{a1{>t
zQsM_cB{qeNRCJ+{#3&1mD+pJxwypgHK}yOf($MUDL$!6K?oi+_4ma#}nYp-SNLsh;
zDnO2Hnq|m-EYfK@@}m(7@kJgbrB{epFvQ)&H|<&qmiSTvJWdD_rU{KqH|aH+IE5q!
zLC>h#jqH&F3<63Utba+5P^8lqKg4qG74Jic-!Cc71&#8lK7zXFGhRMCuF4goe|`Ev
z-fo@qUS$w0lnUk}QbHoHLg#G-;W{(K&WL38T&HHHh6dk_{QY^WlxT->I!m6lsHyNx
z+6=-5X`3su^2D-I-w)9yF!yU_1*T*%wov;)B9q;%5zT+f7z>oLSl3BLtr$1{<NtOF
z8lmml{aW!`9-Q6oD5JnIPf3En=uihpgpY8m(G=3$-uekbX)}7wOVATqX|SrfLBO5`
zYa!;A(wKZ>lQGJQ!4|g^1U8wkLUy6ZtYdj9nJ2UnQd&Zy%<ig9Vrl=ofjn3s*McP)
z<$=IKHULWb#IIMH$ARvt8=a(`cLk=g91{B3&r2FcKHOjAKf91(4I?S}d5N)t=qEHN
zTet^869b?)P2yrKkd@4UozeyY1e5dzGvVxm)3Y1a<t5t8QmWd!H5aP2gXo-jQ7+po
zNMJC)TX5pYDd3u6+J+FXVT}OCwt=oqmD^w13HzZ9eQ!|22+814g~Ut{AAqgU1<`6f
z4_~6hGSghN85c0dLiRz31<5Z+cZVE@|1fRhSOIkaBOF21MZ-+VZjKwc1o7aUlS_dG
zM2H+h{>IQwgx~(;DW+k_&8m&qDH_|h@iM0v2DPmplNY@~dn=<9v4waZ!R&$*c#PNx
zBaBgj6BmY46VhV>w-ugpo8y4=Ejby`?%f<(A}|m*jvNmWrNMXwW4NElBJ>OG^~T>`
z_6ZU|B)`|Y;0mq>GO;(M$`>2ZTzyNjb4}IF)f{-MyQQj7N|Jg|Zh$YD=$5+|v|K%?
zcWdf-6$-Z&jt6d=HAt4J(kA7Xh@v9_0NFZw0BjDo_!Y632tq85aG~G@HiaAq*jk47
zby>g(2%qiv30zo@jXHwjfR*H{8iV7a<>3;;TU?Uhxt8p1+;p%4ELYe|)}0-QR$*m_
zOG3q1kb}e9K)fVhR?xc9(W%fx;erXOn_`H!&>&94_nfA23808;v1LCex63zv`=`d3
zQ!oxU^``o;hVw3d%GLWcFOrILnnOoztjHEsG{t=^bHBqgeUWTubUVJ=SnvrYqs4q~
z_o*Zwha#GQ_vnW?;JzFoXG@b~tv|#)D%JbYf(oLJS~jwda9_yfa?s1^d}&ELLFSRo
zu9cBX(Jhx8peuqvuanTb9aJx<?T0+=f|v8Q#zUEhtOY>1Jt@aoQU+5=C7W!DMq8RE
z!i;0P2s4a(d@zx7E%;%Hh`U!rX4GyTC0yNw^#VzF?wE(0v4sLBa|GhB9AlUvs1_0N
z=7b}TBEY8`M{QCvJTqpn1M!pp>$eg?10GsvQm{+=e6#1etgSj)6mg>j-(|RggR0Bm
zH$xA|C)_r0S45YTGsMTCJ!?TTZ9Lf~VaFS!lhr=cJ>Zocj#knyL)zYLf#YmofpdW?
zB*0P!adbF!VbzY;C;_sN%-es`@I}GVC1F7F4HqsO^eCoqNAL4S8qQ+-SW$rLtN_;o
zZUsCn2*U_km9a4gIw|@}QnN7Wa^OR3-|$o!i5g=5-F6UwNM{C#X*o<_auR$R=S3`n
zEh3s5t1bWRrA>Gz@K9XeP_r5$0O*Vk4#tL3jRjgfdZE``v>Ez2@)0gr1d*GRB1ITm
z>?teZk~*?1kk|y5vMuWdA7L0jO2kZX-<C=|fImIWomlDD4N$C3adRvX0(9(1Y`eX8
zR&Xx%9&+37?Vt$Bc%H;K8{8}eb^yl$#%PRGfJwa2WhN-1+h`0nJ-}uh1z|M|N2gY>
z5(;vXo}fAsb)Qs&5Fsu%FS}zL41R)%E3!mL@kmp!^9fD^jkn9uIgUkGSB#8>6B$#g
z7Wj1~{4&4s^`F`8;wA_UEeEGROw~9cWP%CQ5wOfLZES}y|Kb=x;=|aexB|nyh>0n2
zAF+J^F1(afHjg9Z=8-Xu7z5;YVKk^KS`bvUX$gy!@->cZdZH&5p*RI&7|b|=BUk_|
zqvjQ8F2B;@pLOYY|KRt%1uuWS(R63r;$P6~cHg0j{o?4pso|(`sI96E{FQgzZjKgc
z->5t5I)m5U=hW-{<`<6-&h_lJy05Tv(W@-qTA1<p<14i}9({pm`v5MvSZP@4hL+t=
zI-?;YGRD1PFMHu2+jG3$XRS@xVINP!U|fAMH53lbU;M?vu=V5#WFDo~?G=v5eEW)a
zYhC?tRC>TWO?N&KO<$)^An$j5b;p*VlC5aVsiWoa3j|M5Dmzl3e5?o07z{Dx!FB#7
zCFU~(;_#a#lds!b29qFy&8kCezc%m~LawE2Zew&v9X#f#lT%LVizxdRe#IWLpEyjz
znp*s#x{uu$wKDl%@QxgAbRS|5!`e}tzjt475fHXMja}?jQ}aFj)jp+|0RTkXrS>D;
zKWhy>r)J0t*SsZTh~&>9{IPbvbymBrS>cK`XMH$&aq=ZAYN;2qJk$=C;*6sH`tiS3
z)5-HS@i&M)%$I3*mM@=ldY?QOR?cw{fgdM3db1kRxM=uW+8!iDgO3qbo-*oR)j%Gp
zkd=>U?|z%kaXv;3+>yIc`T%P8+n+aJ9er-Bbvs(DSl5*H*WuTO*}Jh}_Kq1H8vw{V
z^7fB>F41~=ym1NGjdqpA3BrAhz$=hth4HYIt-&7Nf;}90xEo&aDjy;-;5gpmz37qj
zn>OJa`Lh9m%KalG5U^6;c814lPkXF#zxhv9?$oU>b>2`H?sIhrZ}on5DT2y<@Ed>K
z>^#_+oj%h{U5CicSCrq?Zo2R`_w+Ip2HiSUZ$6t{WhdCt*Etl}6D*T{&Fy7-;qCmS
zH(7wh{YVsByjPW>=&RPwM`vh0b`C2a=ew-bN25!1;Dv{6`;56OyI*x<rF!rtWA~rU
zZoB4r*XZ|voG6?=GWGd2?Y#1Oj7t5grMz6S*PZmuC!;@V!lF9tJ-A`>?yN$Nt(c&o
zlIOCImUwGJU%Vr7KQRFoGk+wKchzEM?FP0Zir<<+W_|u$shh6r={7{hZ*)LOd@m|3
zxgPk?FS)Vq`Z72SN$^}AbD4dGOHi!?FTM0r`@QtC`5Rh)&Abss#d<F}!T13_8^!nz
zd!dFr`TcCD4&?<8>sMjMepHpxI6r_;;P-doB2B-+v$Y#q_T|>?TJ0#TzaMuIiySW8
z9U}wM!K-VxBZmFj7UARz2Ar(WXR}b7VD%*Md<P<AQy4i<rw?+Fn346qH<TAMQwVUp
zbhr)X+bYO`qias;D}WnJx`l(hNb3DJ0OXCm%h2W(z2@Rv@^Tt%pg-Y{vZ58-!t%J@
zwRh8grp(Z9@M677nOb*ZYzTwK2`6i>4Ri55g9lxN2ksC*6qnU{%g5mw-T;2!G=^J9
z%7(kz!uzmvLVF445^!9AHyWae8??ge=1KY}yslbk*8_Y%&QC+WkCDFdU&O`UFm}bt
z@RtLkRX2Yvf^F##Z<joJ>07P@bq<#T2N-hf1^ET-MK)ZFY}k4sJECw~O{rdv-_6F2
zHkGKJ%vti(aoz*BZ7a*nhZ(XQAiIsY`tm*d?3h|I67@^CN36CDR$N32`oCYRIa8y>
zeO@Z*t<(}JyKZWi?u9J6&kJx?CmTzgAim0P!oeaR0BQm$2Xipri&Vhz6CbE~Gd_N}
zw&aiOO6*q$Fj6RX0ph9c%xW*U*4^6Ar^dOLswFSUO6jKCELaCQ+h8O|HP;-r@rViV
zEwm~c*vUXyV5u*Vms_4RLudG~lfXr|;+ilmBi|24w|743x0W+JzAwl$KSz{9nEFSt
zgt%TfeK>V2BIMP$_e@)8&`<!A05V6gLqj|!%e~)#r8mAaqb^c59^g2Kg8<S5;-Xo?
zbKv~O<y!7t<mTSxFY91w${&2>UGw+32e7p*sH4UG?)^W{E4&{~;8nyLQit#ZHY&qK
zIIK%(7$;xY;*ojSs8PoDpo<HR;>!pTJcr~b$igi-qfC9v4HCtyg#!~FUg(haKFT)w
z$_do!!M$E|6<FO7v{<p0yWyOU`k5h4vxBjtd)sWaf-V*#?k4OY?qGgBvv;0D`#>^F
z@CL;pndw*}MjuK%Are@_%^&>qyK-0%Fj(FWx-TK3P;RmNt(y_LY$}PU9pvs=PbhOP
zp_Xn0*fa(_`B_A^mwR<$oJDZZz=bI%rdC*N(bf|~=v~YA4B=u0w<3H_fOBCAie6tX
zd<?A`MjtGI(TMVhD4G3?EE~h#mNqg6xEVAxw68#mDCY@;DbUNzl(_{|kqzk2Pw{7e
zWpk(IIiT|R_Uo=CT~%44!UIpM@SR?6Wlg>sU&Pck)F(w3@|<?O9sU-8@7=+H^Jw9q
zaLxW>Gd7yzXp41n6|=|Uwz#8q-{xFM<IjSiB2u;A8WBG0)j%-u#Uh^E$zc}sCjwW1
z5Myhx72L<>fbY2L05+6svRVFL0d@xAy`Bti{CfVB+PF#$#BO?3{g_5tQ%G|*h&;t_
zW50F9`zy}^;M<dTFYM<+XSGOHNtw!F1_KT19MO+*x@gi<6Db44lx?L(q$lFdV>k!v
zhUkBaLZ{a7P&EZhHBQdI1|{7;woqs0RZ5BJNHJ(gQA!>)v9)>Dv@j-|Mp1+{Zr*~z
zr02nJqx{x?*>?d~iA|{%oK!V62Ya}AaAW@V76vpF!5OE;9%j&Z)<zM6aodgsZK2yc
z1cV5tYWU3;2F#7`Fb(ryykYATnAg+2&>Xa>KBi&r-KUXUjX>^RnU*l~=DG2zhjFK|
zsH|aM2_^_kczHe%i~;Ao5qM^$l>l1+4l#uZIyc{div0%EZvR&KwX61(AEKHEH&D$(
z|1#P5$MDGK?G3Uq*dTY<8u(^|vHTVu`R_q$R%6EU%mmcuJGkc`XDt7iSNz9mA$J_-
z^&fi0|7GOJJGS+Im0R-ncl7XgK+PZ6(8Ha=#_9afD_*#@{5fplVg&>NEqsHm`VT*J
zz5{#2`2Rcq@V7gEC-J`formh!GMY#}-uM8i3T86sA}O?__~Re8ZhXP^J(f#ia-v{t
z{06&_|M?@%%zgVKKAMdWJmKy4jeovzZdU)4GeY{Wc(g_OtKNPMUg`%aB2)XQTQR0E
zz=3twKgnRHtJowTEGgL+QxTtMZR`(u6g<f3+A(<H+N*>$FV>Z4PF+0DN}IY{weSh;
zK6SVI8$A^*yx3=!6D8iYs?m^M3y|v=OgP}j!ts2+Lkv6HQ<|nrL9|Ri?46?(u<W$%
z$p9i!i{O>hbRr;`P68h?=(s2gl{OF-n&%mEANli7pE`t0bV2VWTFE_(@J#^Ix`8TP
z_IB4}F$h+ZFId_9yb2~Eg*sv>iUymrOjzC+?9=jMc913-kk5H$P;~cLo4Qetst)J3
zVNfV&4-@N}Bbv~AQAcdj$;|r+MJuLSM9bp%$T&R3!X9lsfVUhsJ`AaWm>1saS?$(8
z_UbKlx7DBR2=b#bNdReTTGMNDE%h)}v}sVXB)>7bpX3<LJQ-<E;vJfk0WD&q0E1ut
zED#<*SM8Ol-Z4p;iLIfNUQ(lMw5O$p^JlQRcc9Tv^3r%{wh<3{`upv)OGHxY^{A3+
zWs8&3ir<1!dp-jbWfVJ4CPHiuONnxVFh78Ea}kiB-NgIB@@D9iLJn!SC9&jHs}~jo
z+NNrK8iE^h*uy5FEzRqhzKlJkB9EjOf^Bh}r?OcxYte8?IlW{&-r^oM>+1m-_iA`-
zHq3PNYpyhCZPF->8dbU*%vYhCe=5MyIV(sNm<X3MfHxzOGZE-vo={v*GYV{uVmBI+
zL_tBq2SX%CPkj9~dHP;gy9jAuNP}(+=&j~)nq-E7=O;YD{RHVgV|4eaGlR4VcU_-)
zpJkeXa&f_(M%wX0L<i+eg8`T<0$jf~Z$VYz=`5$jx4B3N^tbT<!zX<F1xL=pcM2me
z{A_XALc+kQ5WBezmmx!nDwI%jIo2rwHW5GgU*!I*8=>+iYs|XQoECcP4WyGLWzB9^
zwFS-1lzNe|-ONt}8up0Sg7x59<2BDl_P|s5igNlay9Tv)$f}T&wv+WvFOd(k(u3Rq
zC6Z8CADxDX9A^5aTPzP-e@1}Ju$&DO;DwZei`uDC*6o4j0?y@lfUrp76kPW~AfgfB
zdMl)2XyGPy3a6lC!g%t6_F4{-WYhbePuK*^O>OJcAyzu*l~fG}dvT*pJASX)3H$JV
zTn@dr58G-ywUB(WxXX(srU2%MKGfR7SGY-)Z+T1iH^Vn6vMNIR3fp9-(!sdBODmlt
z;*0|~<3ctPwF^C%aEy%B#^*<&)y*UJ(Z0^DC8#B-i5D<k0$P!!EQ^um#H4?bloQY%
zBQsxz?yJB6A3MR}>hC4yi8o@Um;%FLdjk3_GO+-Mh4zlgRrCa*3V&u(a3jp}2^VP`
zkc6^L|86r9+k0eGJ;b&XO$s^^)JQ)`6ipsu49-%zIe=*uf~Ud|%S#{*(zeb-g8Upf
zGojkZR8XK33g+)T`X1eO-K~OegL+be&r8cmK9z(3<G6CFmVumostH~K()Bs;2f$}=
zKLNej6pLGY3@T9e6t^UrRO{aWcpwpc+3~vqt;Gdl%*GgorG^lx@FI(vZve2ZD;!kY
z(iVt|S>ffsmD*JmO&`6}oq|o2_jxc*3k^lcgiP#59Aq~j3?Pc<xLe2lGk(tly(uk5
z;|&iWX*m*cOqeoEdH}L0!ZtKjPCzL~0t&wO*^;4)f!T(YLbwT|jBz)BHVkUAj6UKg
z0<=b<l=#LnDsMxUyD-|%rM#`m@miK*6ee;jcR23~zVxsa2lf(^_6QR20NOCo&q_(Q
z6cV@J11fyQm(ntxR5tELMGLtKSS(*+CN7o&lyOMU@^BfOFNK%r-Ov#shGC+E6BdV#
z59P+^KH`H1VHwagA%r`Qvl?1bd!M@M*t@*~VgmnZvfpu1dr1f;*D6$S4yUp_px*W@
z``MZ}@1{l0>6n8}YL?GhjSL}7aD+PbabG9`9f*A}wj1iN2}rbvSQ=U*)}p46LI4Wx
ze1Q?f9t1*P(VW}2I<Gd7C=yA7$(D-I6kGt=g-bcIB|1h+Mv}{ehddvNBZFwMxL#_H
zCgn60)FQ-Bp!$Y~ITDZrHwRwIx@({JlpbktbJ_YdQsTRbwIv|s1-_alQUUgN!z09!
zgYG(9*3h2)3C@;7a}rZ?x<vwvWpf;=QhOak0RpD{*^kLOlLq7qo|2Pju4emEQI+lX
zNYd%-oaRwqGTA<+H+q_A|5`e^^#XB*3~yuU5Rgt6@x7enOO9LoO;WKcMr4&NQX^ix
z=Sh@misS!;_Y!f+%$Q_B$slHoK=aYz(Wi7G(f~>@5<lm;65xox{+I7^P-`Tr*|z5@
zW3C&mu~bLP_3f>m-iuP@2N+T{GyYb{x%!kN4{ko;L0TSj2!c_8?bWRS-C8>byERl#
z%)IDaHuf{bF%hpYD+IL)&{*QA8nQh~0VVKgUm$_s(#mnvqbvfLugl9f{%%j)X9YpG
zHe*30pq0}$Ntcu&w0{e2!DL)F<T9e*p0pdw_afX$QsV%WSQw#|64@jW2TweuQ8Py7
zPzn~*B5=swBpRu1LdZr+_uUv|d?aZl1X32ERR@k-y7>qH0oW?R6)=eDQk*Q?#^Jva
zgh>sh8Yy3{Q3R`|RZHVEApih)+5-YQl_+(a>ukbxJl#Pep<sH*J3zGD7u%r-W0`28
zec+wt_{L!b5a3hM7O|EJ0{qcO_+30Xx7DSCR-fnDp(Yg%GKQVnRI>wicZBdb^S4Vm
zsY(fO{qC3pDcZFMe@cRJdLK4m%wt|TKuDd~XsUKw74c%<kWUa2wlo36@e)>R0?{)F
zcHq>7@&w(*=MjJ;7<KUDT-NUrAIFkrNrC5AxM2Lvo_FcYmf)-(WlkIN3LC+JxZ~La
z*I_womnp{hgl;8O2?s+$)U2f81ndQybSab&pu&Ce9k$?>8GFf1^DQODEYVBd1&R+x
z=lzP~wY;iMo`h3ekptWmTnQ}hNMa0Xz3zEjT-N4w7)tcpyN2~*%^rB{5czeFb$ZR>
zr<&m(vnRb-^+o#xvf=5)h8mt-kY2Rc&T3mL9sAgj-TnQn+i4Bui@((<;XRwQv#z{2
zenKk%%z2Dlr<u`Vno;-HhY{4BRY#)w_D<f|H`NTuoYj69YwU|J^;N9A+4)%Zyk<S~
zU;%)x@>iID8gXw3-i>ds2X!?Q&ivNnsqAF={q@Q4-uly|T91}#c{xZ=mdi$Ry|j$t
zf6#`r+T-h`d6Fqz)S|QGJ6KbcyOx6a5Q}&1$#Z}HZqJENA;qq<<8Iv^sCqBjLtb>I
z!y9Hxb^(s7Ic>-ux%fGCMeAX6?u&N*yt>ETQ`>QWeR5|18d4tFNv}~K+L7AJEA+mF
zS?fi`4v%H~7KZ8Z>UF9;6jTgUzdhMMF&iB_-kkh|RqX!B+jSMDhzuF(yZC`Rt4syq
zS1f9Ntd8=#o#be85=Ig;e6F<=yhKVr$5*|ltK<YJErCUbrmHX05SL)7Y_5kq{Rcc#
zuU545cn~hlr!H56`spR)#RbSWJE48{7w>ZK0IN4F*&7D%QEv!R#0H=w7REOuaV#Ps
ziGxYfcma~|I4(f}JJKo}^6qHd**&*88{%4f{3SMKPn~C|-G`rS{6LW-9FtQZUvG%%
zS=22A10{Z=0xVfbT;H&OAH^oNRF9usIujT8DdDZ&q$?a>mgtGMT;SMw17-aVC_9$K
z-vXz+Bag=>aHOuqyKvaXSCY51**3{hUVdT8^$tY)VwvlYzh7empqlgp-;nH720rfY
zJQ%&|HeCfol>1!eWjgL2{aO}mgy_tX)c2~@Avbd}cq6uA{{{WtEc*=m1Zb<zMfI<K
z{-f|rteAkBggv#cyxd(ghX-#q<7Yq0t`}<qm98OepSPEt<JY{}FP#jZqxF|Mp>Ur7
z62<CNE|YW0m$c~2uD$m_mUm9y6U_4T*9dsaM}cC&wW)W-9!n@=kHWs#F2eqO8b>@6
zfu!=6uuMWm&P0%U%gY*nmMp{53UR!G8hgKVR`8+VH4LU+;d8Dw<-v*$1NT7}LOEy~
z(B)Fcijc;QEiEXc@N7Swu`kyr_HLXlr0)v9eCB7N@p~&x0tN5{|LfXOXwGK-IQ+XP
zCAOS;pftQzJF?gKdz|jK!(-KdY`W?0N7yg3+IwdJp5`goa=AB=5|LsNo1mYD%v$JP
z<}nWCiKXV`hqItGLpTlssIsYVLRVH4obl;xPzqtqRUk@|)8MER(}YJf9n?8U*Kd}d
z;WxHl^4DFf267Dy#s@gg=pdATIG<JT`_1M^Zq(Hv))w)YgWM@d!}c*mYlm&bKPFS(
z1JrTt=;2_v1?a<1c4qf^Cz@yyFZ254wA36br@x>LL-0C-{b6vcBYN3A<EG}=ea)li
zv#+f^(>w}i{45{#YTHhRVVx;ZV3&^`i8<S;<>Vj2&i_%!+2&qzou8QiBF0VsCqkaV
zt%-&7)FYUBlUJZd#*}hm&cvqc(`jXt$Ef2#Uz)?+Gx0la{^0l)D9%$^t;i(5_Fjn7
z_qiVH$Jv34FzUj$-})BrohS^`S21Rbi0eGPZE>xDU`~Xdh~Pp00-k`^TAysIgY*K=
zcS}H}#%P_LIlPzFn@7JL+*DaBorpW&Ju_jTe-0kx+7WFEPIWrhy1cAR)m=ylw_D!P
zyHd{-$t;NlQ3Newg0`kC24EDUm&HPD8C#`zrj@gJ2&C*)KD}gq{ngD6qs=Lo>X-zb
z!g(!OiyRyX9Q9EA8D!^9EzfGnsjBDQP__He1dW(Ff5tgU-z?Q#X!9d+oae*wi>9W|
zvK4lEJSFb3fSGxjb0#iMq+g597S9|>Z>u%I;^93{o3vQ}rF2()?f&gc{OFk@xIO8;
zn_g<ILO(57p!UqRj>fGo!c)<v6d82wE|?c$TYC!2p{|qEs0RdkCV4_!G$HA}f?j`P
z`b)w-7u{r5bDTC_JJ_kYuy?~E?e<&X1Zq>qi#@d@?A6}0+PLea&#K3oY`HhUegUu?
zZHZq7gSrJ*wJk4pv6E}Ef(6sQ7lxY>3K6=y$m2EFOHV+Fe=oLL9Fc~_iNa>Ve3qYC
zODE!tgc%-?^i#=J;Ya}21R@x4Sj#vbjC!bLSO$ba<Mo`Zzkx#b03{&lbok@gUL1&E
zfkE@Q%&nU&g7-V;v4gzuI);ELa8=`uQ5)DhuNL@u4IKlwAGc*K{p~Q{bPG~Y{;CV<
zxb2FIc9(Xp@Cc#W7vuIlSYH#q5tYvjOkHv7O;bllSmbHKdU;@uMc@5uQt^b~4<WJR
z`dj9Fnarcp0EhzT`XU7GSuH3hW+>-~vjlIHcF0&wOcAhXzL&e=BI2Uyu$(yU^2ckI
zhR9Iuy&yYlQ&%D>*NTL8EM>=Nxktj4(=MG^b3%-1NYC^^VG?$>a%f(|Mfs|`^(vp_
z<Z4{2^8_nfY>6)(%3SS;5K?f29nvW;&>Kz1kBR?*<JS=zcooo;6!oCE$r_Gs2khNo
zP86}y@sVnqlW%<bKOb;iJ!wg(fvFvcR00=B?Dxj9E=6I8UP=z|M5nf&LE9U&V5R!7
zb_u%Dajseu^wNqcr9_10=qz&oOVy@l4rbS!(tNbf!yq`$^SDaW9yJ|O-!`SeAPvfq
zL}u`CqJ>Fvm)2^VEP?7>^1nbJKgR}4IIbP&FBl@b8qCyi^U==zj8+!OmtKXF9%)-@
zZ2lg!EO8j<69s;55YBLBS3K<dVAEz$!QuLgfKwT_1?c5@-j$4bD!4bXUJe@xFbg;Y
z6LIZe90oDq&n#xguLB58Upuc)77SVin1$DSG*;}fu+EYYUc-E^#C3SFNsg6$O5h)*
z2z<mhq$sBigmtdLsjSgJ{p8PVdi<TDhF^QDsNv8CSR3{Heog(_TjdD<Nln8$e(epD
zG=%YYl=AY;J2>sPYZ~@_?X8-IP|9yZDSvR|Mefuze8=^D=T-hqsl2`c#Qq_j+r*OP
zU!-&YTT=NytGB;J)rLl%j;-TPyw1Y;;OF6owrmK|*gOky#%zEu8y`NmB-rQ{v3>Vp
z{gIf5Ut=#5%i^(8j&JTf@a?ZYgbNBK2Ya5tT;2GipHPRpu-p0PKQ^TEJAaCGcCv8@
zcYfAI?4y3<XZ#kwiXSBW&41fcg#TmRcKcM?kKBXNcGr8}`|?8cU?cZX!?&9q#RuWx
zX=;|%>GrpdkL5Gneb$U~5$OYm1MQRw3-@_`ttsBOzzS#i*`6Is`RVJy7wg1n`QKN)
z%1F@&-k|etrqL~j^VvG|#Zy}8ELlpq1R@PpJ_BSz)Cd0uU4$1HUKxm%uXqzBtcEKF
z!v++d@T}QgMfx++LSs!h3qS5t6tEYqzU>^p+qH}1t{Wa?O<3P(K3-bBpvf#}8A%J(
z@|xI8eaqW^)}md8UA)&y_hpL{L7rmMGw6*n>I%vpg19&~xr`|TYPJV87&2<O%0p;G
zTVliHs+Ls*?wE0A$7Ct4tAtW|f&4IOa=3v^u^rT20?%pG^+2HPsxoX)cS9E96b@jp
z@|_R(<8)OU^Av~PrvilQ6pe9kUq7}rhqOCM@#t>l6}IZxuu}(0w&Q{)JWD*w`i^BR
zFVLgoW%R_uUS)imn^V$$Z%;k1*^8Q^<&EUwVAevAIYTx0Y_nFzp9o_tc)p!j^Vkj$
zEp2o`W2+cGwQ-Elcr-}7AzG0}r~_4qlx@WL>Noa3@7tCbDR7g~rWU<-lwofOGV~m-
zp47=BkZ^F_W86Q=?kZ!>jAOzBUTQ(aMjlHqHzV6yutE{4MPR2z_;ed;Gn!|`474Oz
zU!m73=N6T$Pybz(W>#^<t!@Lsz%b$YWdl-V2xN4X_~z6ms+n-OQ`3aW*_;n|hzc3L
z_P_X#d3_ylDMSs+w`F@&$S1QM0u0BZ4GFVoB!~+Q-<o4C%S{4FT-Eph|7j~>S2Vq5
zU>!8D!kcRTF3(L%(VoaG2iWU#QBQIduJRK(8S;42lP}gOE+C3V0lsO5U+F<d(K$@;
z<~A9^j1S>M4=g~jZ~Wh17VNdTjy0v~mX2Adgr`LPhp8J4c8q!y@1B!TULN+LR!6wa
zQx{akX5i19T;1)K=TI$4<Ka3_m~_UAf`*r$w<=4!C;1x1_-{|R-IKKYF)K^>-~(Qk
z`g16LIS0YpG;w+Tvt*o^6&60H*4e1OJvkZZDp^)4Y5}+(3iZ4j8J*krV^n9Rr@%*#
zYE25+I~ge@YTo+v_$m0nk#M02jj+){b9I$9qu0G{#p9}1%`(NzY2HEyUWVii=U#P4
zX_Ln;vS~=d;R`E@Ie4DTb-49@p6!E@ZI*5k6^?hBCPtRL@M%8vI-BG!xCsF=33w*E
zFJvXtL|~|NEx3jvj$qs%7?%p(4><QY?Uo~FGB{E<Mipcfx65IY&uM#FTFRNk(;z8E
ztyo`0n0Z<F)tBBCOFvLw6dPKaz^7bGq>#KJVJ|v}3${abl=nywq_0!c5ZhFVL8?l;
zV2aSv{BzX+jGCMT%d(%KX=59Z)i8P+34O_Fm&hp(!!hQ+LJ)wAs)L!KJ1qi96yqxT
zzP_@)6~n4cJw_R&a5h8MfcA^f9h}|Zf&;B*ty<VTnK>7gO}UKmqio1z%|gX?VUOI-
zmy}cdswY0n(NVaq!!5{kh+_^+l8ZqZ`6}upDCJowQwikA?4Suu50F{gTVSjsX#o^>
zn3@$CDFdLVm_{hR586@Qc41x3Sq%%X<;f^G;7Weg$`QM%`l6QG+Af)~i&mhRZXhaI
z1%~&;iDPEjO_+c@1?pisNC=rlM?gVGWMFJ=(>P4hh|<J04SkG^DJG&nY!t_XPv7?B
z8^4Yj$!&LC39$e{a46aoz9_NH9iMGe7r{Xmbf-D#&a!abyTqt)QL@vNiKeSLF0@Rv
zD`2jGy-2Zf?vxiuuy+zMtEH5Hm<2JVg3KX_qqt$fLIggcJjcL{Q(6H$y9CqPu{_^Y
z3gqAUb^_8X4kBkwiJ>Ky3|D4@hzZb#Ju9xGib?ikhXVwoT@`l$_*{gtYcxocEgC9p
zieVym*ufQ0B!F&&3U0TFvVFMJv0*?Yi0f_QZ~-SciNqA1juRlc$)Fwg_*y_PSNSHA
zK7RE-i@r2!YimiDi2k^(i<s3l32(k8UQmTWN5X824w*{0rBya9w@b0|JV+BQQVxjY
z)>4pn2ZM(k&m72-G((bsH{Ie)Z?&|jqi!qAiTcPY)&fqJV|AABB1F(k8>M`=fITDg
zlw|~)^jbSdZWNVoJoo7ft`bR92lYg;2V}=>gFKGQ?e?Js?;f>t*5+_3_Vfc9R1!(#
z;96nHYikEQ;J4zURLfSJ&CG>Ra%{|n-CDgTFf{~JR`snD9x<K8p4YsRWtnw^zY%Wa
z7$_wld*~&4p>Co@3Ea%_IJx7%IY`2AHXraXKj$QEK$QoP!y}|%y2eP&Z3v#Y<QNYa
zfF)U^SBd~n*|hMKhR3kGgf=E(ZHojL%vz4e3kDXcA+iThrq4Gv`GKf!f?xUm#5CW8
zLLfq^Nj!v*S*UQOzJPnX)#NAs2YM4s$+|S+I(fqycZEi-ssg_5C^<{Q@7u6s*xJp|
z^gTdHaK}s7h!KkPhy)gB_62O7<GZR$L`P9wte~LC>*92EayNPt<_qZK0g|5t9}mhP
zN)&F6#2d>0E(rMEYm+_Z<>Y>t+dVnOkdUf*2oaQi(t_yhCvY$b!FiF0P!|m8{W4PG
z>|8AynGFj*2~LIp+EZ5I5lg%fk4g~8F&9ZC(HG<Bw1M<ogAs&oa&-r1i4O1RiNO5L
z9#rg#J^B}l_ArGf2OFSSq<7?4eEr*7o_`F36)vr0<|OPMG}y%#72USBF~blYA#hNa
z8Ll1Kr>5i__m`McVaUru`0o@SDV??y$03UhaT<@`jeKi-j{t-~O7-mYBo9hJT9c9?
zDTvC~HH>5WLG1?%TNJ;6^c!Re9P)%5u6q;G1MW^vWv-Q=Hbd0N&fsVyWzli*7t*Ad
zpb>8(X;9NAoBagO3~M#Szc5nQPzGr`0TRv8hzgFAR1Pexr|~pyF8ksrfoz}fMZaca
z`h+>e{kdlsEM^_1AosZI%xFS^iK9}z#fyi)*Jv*yupJraUE1rFj;U8zQ!8A9mEX<Z
z^HBa`hilsOMT71OBISIxYTeh-I9Y5|0Z!}nUJU=dCtKQ+?X1oAtzFcH4Aaii>`8kb
zgp&EgL+!&;Z&Vgqg=IT^me&@d=e_6Z&_0(&Dt%t~+x9@qE7kIqnzLSbhDFm)lGN#W
z`Zy<NR>SXxE0|A9&y(M)u4)y}oaWzwQ{+RFlMxIHmE)`RWxuiVc(yvdG;~TWsw*7`
z)jj4RC1M|&vX<0-vi)<ecEvl$TzAG+Mh3T!GrEs9X55PE6_>1i!Gt!L|7GhqIS)U*
zouTZJaIZ(;48wo<-o6mB^xnzvLstF|yyqgPW(<CzXOUbDJokK0_Tw*Q%X7plo##*Y
z6fPe>0T%fi6#s(pa%K-=6eTk=c{zB>I^H?Cn@_;u9`gD~CqI#$ucU&f`FH5)i<S9^
ze>;3=rV@tNg5J1z$GPfxOqWNW$(PP*&m%rizGXdr)vmf5RU0k$iZ|yLHW(&%K3_$v
zh6IkJN-QXWu7Zy3Kmdn+y$dq-TLADqFm+=OL*Ow>-yxqE@TDy)k82#tcgLAnGPlXD
zY?#E;$Sm8?y-W2%;ST$I&)X6<G&i`tkv*Sje@pfT)Ahp$`v(Qc-lT5rsiK7A+whYT
zbh=M%Xyqsq8I#9XS{qXNTS|G=_?u7OJ#1fNQtGUF&`n8~e%ZAk<Zd9jE4`QQb+0ZR
zbBpJdzeVo>-G7}m*^LhEQqOrZ;@;=MV>)Qpy2$>H#jd>{ogFSdq-xF2)Q-Nnbh8+J
zwYKwt*u6V&`W`zxJg^r+`HTyS_cvX;=Z$cayEk~vy$O25e<#^(q-j6Q>z_&gcP(`?
z0>gXX@m77;-g67D^6So5?@>x;21?8Pr54E2mAP`ge;3g>)Z}lL_+(One7U^$oAsM5
ze){*#b6T=q-uq~@;$3&(4%bdXo1Zlx+Qp#=4Um*QyRO<|!M&}j{Y;uV?$!>Wt|PQz
zl})X=ukeFK8?v{~u*&-*8=7Q#lQWrmRFffBjx=rfWT&p**HbfI_UgNi#?;|qXF2om
z+Am+P-804tvE%l*YdziDf5?RpI;GV>`M~!mZ64Kw0s~LxXzj2P)t4b;oyjb^B<4St
zYe&q*C>^^P7hRpet9uVU&FLm^zBS-b>L3=p<ki7Jh_5%Q+0A-KyO*^>?QjL$1uB1_
zz6jB>mb6{x08Yeuo!ihJD@ml^r$ne}bU@0<$~U0cy6F*jzYBRhv}@)p>E8<U`x>w)
zknPJ)!$Y56cb2<uMD8$z*IBJpn@BBvxm4@kJL1MFYofpAmYnZ1mi`{eRuFS==`26}
z)x$B(dzomh^m|UyYk<@26$?GfrheuK^kZK5c3^_p{$ad3bo*FlJ*Ocakxs)oT2E)8
zw0bE2h|~1Iz~+m%VKXK8{h#?6;j+bG)rN52!Y35hoODMzaeZKV7htG$g_88Jb_mai
z6>OYjf6YuQ(qi(`AvcAp%4a6p`AY3{#(&;AbB|whV9#IhCbIo-&dav5i`Z~A|56sV
zkXNvj8RL2aSRFUM86bi5E*8^w1%<i`5walRz>h8)Q*tWFNw5UBJuk0n@trWHCgFbv
ziM;Oa-2_b(@rbILzSaAw1MUFy>XUF#Ntgc7jRj#_rw5}vbY-*!WcK<NBtZE<#GIT}
zvr^x554tx9=?8xLdlASi5wri%Vxu_cb(kX>=@Xl1nkgN1C%bVU<~8@|dGZMRJ_Pc=
z#nuWob4pJ92?t^tc=+31>y4Dz@Fr2jvxIx_6u-=_14I-Tq~yHN%my5$e_jV4qXZpu
zj(_**dz6ZsPDE#0kjTN8fO8C8%)BRoqNg~6qNRFUa~@(q+Yh#iI0sh<MQ1VT2$zr_
zR$x!}?z06p)xmCMwUgd@5o!CE6IfOKQFEVn06X9W8(xz$&mt>eCWr$*huIXg*U70C
z$BTeeZ7P(f<IBH{i(hl0OirUpYmz%B!|{?3nnbQ_D?>ZS?iVqK#pHB-t?jmly}-4o
zb_9-q@KG#PhyM&xZq3C)C%)o^*ZD!_j0nJK9B>tCyMia!tRQu&=;w!1iGHxlQTnuZ
zh%dUr&^jLeDqHvDSNNHiunjxPwmr|!H~_YsV6X6HL~-gz=ss^ynh6kYC~W4Z&m4~P
zFaXvrV;@j>x);R~%cSQuJXXNc7o7(cBI#lo^&qkOMBDVwfs*2n@Cv{|plaWvl;sDu
zpnGDAu1yss3_L(s>k@N!Fwu3|AZg&Zh8qW6Pot2KsZI9Y<V-Cf!nfuqA>bv?w$3-@
zsr6>h))Qd7Z$*dT4`by)z}n!<Y4Hx`$oeK|(-%BAy@7u5yfNtLGXdg9n}9#EJvzdn
z!oLC%3d%JCw{oQ=o3q+#fi<dF0Ur3!Si?rqN6kjY`Qm$pkF!<Hw#O(m;RBH`0>{y=
zB3D}j;$$BcvN<W000*R^ur&5SJEYy<?wHqHZjG?8<|s@DwAjyk)@qikla*~KgeI{a
zccE6_D<0Yh)5odMorTDcF4mXLEg2c$oW-u?KF|r5lSOPQVcQxDLXcm6^SQX{BZG>L
z{|6;ZxoRPg7)4ukU}OH3+FMN@6SY6y7_<%tu6+TL5zCKy{qzCq+8TV_FoDy-1XOK!
zyQ#g1saJ}<-G!J<58^jHVP}1S0Wp3AHH9I{JO;zKWiDaH#mMay5(u)u-YuNs(-bQ{
zc;4XcmKeBXP$XkONR~Tk&|k2U5N03$=Q$<+ToK3rPcre_l_39rc##im*s|dV-_V-z
z^=)E`waYtc-+s$x4h0@I^V{A(k-eujWbaR*v}FuCxfCna%gQI%-$1C|H5xzHDct&R
z&&N{0osW2Xv+;o)23E?DuX+3r8&u4K_y!w18NbKhOze7t1ioxM4!$uH+r9V$%WjMU
z;F1&)i%$I5jUR`<16dq9bUcVrG^g0a-KNFw_Kuw!o8&tmZFt={mG_4q@rLS0KCmIc
zu0go*e_r&nDk~YNA@60gwB4d}2!=GZF4VS1A*c}>R>5YG<Rt8j7Pog#x?wQDALZ72
z@4XV-myL|gSLqw!np!e8m7J;-Jz{0A7mbO*ZrIFbExi_)MKj?lsVfu|Yiiy@j#N?7
z946cHn{@gbga)McMrS7*B<v#yG6ru3;@DtCf$KBwJ!xh>wSA10H$}#>Aw<D5mbvYb
zU)y9e22-2@mhGe+iqvWJ-z^lAql`U*DsVXo^3<v9AX0c)-j#Q8%?5EN+U7~6xhHmU
zSh{tQhsr}m#q6}GR;8w2dczLP1m&>1i7*gJ$e5>3jCjhPvJw2Wd@9@TarFI)s+>aL
z2?gPkRifXOIz6Jf@vg`e70B+&uco$KP<6uwUl+bFMJtIKwx8{i(dL4<+s=B64=S<^
z32Mci2nx!IXVSdo?&#B;@--&<%NV5E76>aQh&e3<X31Hz^ggQ}B@~g((GA_*;bxZ!
zXRMNqu2WPt-s}-UzZMu)mrMFc1~CA1cQX;Y$!J0tsM9fQ@85lagw^q};C<hf>;p{M
zPM{w!T(o}E1K@OE#G{m9O^(q-f$9=1sTzD_LX?2ZY8vA>$|47&9(HnKiBW6SD=r(X
zn^2{u#>fF^dSg_1wgdBRd{vQ{9n_5ONe)pA#xDV6W944pH65>x^lm@l<UpGWWPJuE
z7|Xs9J)<Wj+s!GXUe0q&I}slAW{7}mQaY|MNgLz-IZL+uW2Of!(H8978I`6jTyD}v
z`n17$1ZVKN`vRu~m2Wq>2s}0Hz|_a4S2s7=)VY96prmY>gQi$c%Bh4dhd`A)iNpfb
zCq!B>yjP3(UdOH<`Gr*?@RuLBJCDR*03vLo-`je?^tE}lc`4Df*p6QQ{?>@Fo4?SD
z)GC%7v1qqMs4ckDxQA1<yy-8)YY0Vnm)A`eNO;{gH+5eRmYhZw3Y;0eLCsBCC~9FM
zZwAIDQ@5?a=(6l`!4f&k!;kDEMF<7bW^5$fw6rG@;YHOXSjFQ25iLjse?=`ZIPsY_
z6=5cLWHt8+vky0NPStz({=<}&X%g$h+Qmb`mmBc@zCtE;aAC&TV;!@!Dp^B_ptr-f
zTbj*Gx4WgyswotDRn~g7NmKEP4K11@b^EaYNM8%04_WA7aAIdj8grUG$+c5iZEObN
z&$}Qbhxsp%fKlMt!me?uU!&%daiL0&ikb<-a5qH%`9c>I%B;rT_o(b)fP&o?J>AHy
zs>nxg_aw(++hdu;4z?+YMU+-t4-j9D`MYBdA|c3_uy>O-1e+3LHlu3+<RcS)j0Dsz
z2uYCsh=wZkl75$2&xQ!_U1f3`Poyc0N4X0GQEBRfSly=GzIjCe6@g-~81=%W#Q1>6
z)glq0a(f>1&j!ZQ6r9HpS^>2-+E<9pEF1D86|u5GTR{X-(uyL-`aqExEmIpUg;I!U
zzC`_AZA9T345{XFq!5%oM3-PfH}+bRj-#OjZp7{c-9yCBJ}SAn*s6#ogENH$k6{~A
zyPE@oqG`5aoV1Z9kK@<zCyyA8#Jc19dkk@U=r9L7n=Vnf@bo!vO3IPId=S5e&W&dv
z5Hg6b3hHy>>4_>REC{<H=wje{EbhVs8V(pcrYiLq=h5>WZ9p<?tUcNgazO;(5zXpT
z24JGJcSB5SsWSuZ3zm?@#8PUg5bOp)0I|ubJ{#j53RDv0fK|D_Mdw?_D7uZ}F9$T@
zRd{;M)7yzK3Jo~6KDR^R#gf;HWx&KoGI#IBlFJk|#n2~#ay^Cg8$ZikmiMZV*#!>6
zt1n`q1tyU%`oVi+@jaR+E>6i1neDc*gwicF2@nWKO~Eu8!hCCri<lw(KFq5yj>dxz
zH%lnFiy}=49rj)m$6-R;vyEG~cL>gXTBA$7*BLbW)KjBv5(T}gBpG?&iY>Gk&+X#d
zxrP7DNoUasJ&sdvX-;G`i3YR<;vsO>ONt(d0(HZt6~G5?V)#KeN)RSS1ph;vF4kaW
zRZt;H;}rw@t$+p7v6~^7Mmi44`Q9Cv^CSoj*s;Sazw;h+4{RF7Dcfn=#_oA;@Mk2O
zA28h=lT%%izNT_-u+08+m3h%*;DBs1sFFFbplF+`vL%EG5JSL7Bw*$X@z3+4B~L4}
z#-yHF;bKrQ`BZ|9XsbS38tmrc382Aj5T=~PAWHZJ&}{(KK%f^SUK7&_+TJT&?}^1$
z-;f+$<Ooi%9)zvp(c57Ny4qa9+u*83ww2@zEd$!LHwAo+%wix9a&s7n)36&ycoC^A
zr6fe~seeh+V_{pZPr}o0BOq}B#Wj6q5>(BRuP71i!eUnDS_w<#udm{%BE~RJL|{3f
zj#UyrC2vo_2&{|MPL6A4HFObjJerIY`=fOU<wy}nK+G8-ETQQX0x=sR0|DbAq7xS|
zMMEA%XEJf~Y>q#$TnpA_U-W#uA$k%%u&Da%ku7+-U>#tEB*rS)V4e%VwBM)N3~jU>
zn}jYAj|V47h2?~7f@?ZfwspwwU~*yo000amc1*))wh1AGw<*8|#(<)}u^__<uoC)@
zj}noIl!<bxFnymQe>3tEd9BaGU>9zNcf8X>jf#%Ld_dJ6;|U<ZqoN3y4xM*SsLnZe
z=U^kCK{JSqyKv(vo3Qnyx7B4(-=VtF03t7xZ)s1Db&bgd{s3Eq9Ua9CP9dM&7~oHV
zzcdmQxFMxwQ(#$L<}|>dzojxCbb_rRjtZ!{Qr<Mb*h9<to3+0boH3S?;_<WwM2%Z^
zEg;%G$y!yOl7tdqH;x4aTel^1Z(0&^+KQ^GYgs*5wq_Bj7bv*sg1g&#Rt+#KSPQ%$
z10%)m@dP*m5M{vCcXX+c7}azO*9otL!Xg;r;k$-EpDL3jT@I9G{q~>!-BoYF9X<TQ
z=bQy+YGL%vFOEbv9sXJNdjl_g>;3M~!Uw$7=_;G*D@5O#{uQOKu)R8ZqGMpC@5%dz
z*pPF7>pmVfs=FUrtJn6SDK~ni9-Cy!>+GA}YYf_&N_MHui`Sf9<VGD+vmF<EdpfPb
zId#u@tJiAoDz05$ZNl6U{;qcK=o8ncmmaK4?;3@1<DP8!ERx+S`QN`zttOeSH=^sj
zRx5YcMqeW3<RlND<f$h}`a1zntp~qeuSOU7uIlpRRX&>j5TG4>pna7}ckh)857Np)
zIA5K*`G27JokM5bkFB`9T36F8{e^M3SmMu*R_}Yb(5Jn>7L8gLq8-1iU1#(<?bH77
z$#1PKXa(hP|1(elBj*ZhA*CYU*KwcLzfxRP2d>)+c_fPxI8<w35<z4yZ_wU*$t!IB
z-e$Xeq*_Gbj;0&F$@{XUsk7SG>euK)R0|O!JvW;1qTeOG+SA!9;nY`p_V&CPo+rH=
zWsl2C?UDIwD-~lJ4mA23WM#U()Jei|-bwx}=tZ#oGu7zJBuFh2pqt+0Sm*!4_dor%
z2>nAR_FEq8J73r=%WKXR?_Tt;Y5`!)DBf$u8#ipVHcUcsRx%zG6H5C2sTz&sU>9=q
z3<U!Mo8l-gVF^7NYbqPU@)T-q!B7o3`X=hR{Aevo4i6~wXtMVjY}m-Eeuu^VLl-v8
z$cV_0^ffxSVZeTi#T|o9c!<xS2w#tF*j3{{{2fXe4mWG=tk!cZHu?3Rs2yZqst>*N
ziGwHUM-P9{t=UuX8uLT-5B8jCrOqxKb6PBh1`Pkz%EZ?+`;pbtM?j0_e9^9$!-!}+
zP%;1bTW-^)SDmLPPA(lQK5w1Nd?mTx+hy(DFh!rf=jF!1C>^|MA8eXwtZRRfyl@jr
zTdnKYc+d$Q56)H8Ypl<(^tsG0@ELyet6eYiV_u8xHIKJs8bkmzJoV*Z@7D<4ws6Kt
z&(ok2M;rT-mw)l3u@s&D{mfmh@7C^lxdc6X;HyABN6`X#Vx9L~j~Ng=^Me-?vGLe-
z+R4p<ft~ggf+gn8Bw)v%edzg-uOzSboL7FHa|l<r*;-eRy$as#$<id*X^!pq>_g`#
zZlR_j=b--%dyqa+qw;yHW=A8%^wW=2lKs~m2$#k4AV^HbWSB=fyvRJOq9o?3y6AMv
zE+oHly?OuNYFQY^Yd?FEF7eZ3gzL*D>c53oz%<~Od#(q|(0tzy)&eh}d|-WG1ceqk
z{NT|N=V=FeJ%Ok@jxgy-9-F^S@S!2hg7}<%<LtYJk}y!hNIK9y!r2F{^NL;PA3VG=
z@?Jhkx_+LY;2fe}Yv)?ZKJL^JI9_S?)V9F_j(fSv3q6N80L~V;>G&+^7J?BCq_E-^
zB9SF+9&{<mcB-)iJYn1E?-Qcqws(c~=>Dl*esq_lFK-jTH-Xl?7fNF+>=tSR>08xm
zq1GK&7381qdIYs9M`ks4xz>xco^)c>On;M)GaxH;3)LBSKvsVPk?vcCZ!adxafGB(
z0pomXl;kCLA_xxf6Twc7$ic%*s=dEH6y<`Ni-<<#!%zy}W&)UHUT02vq?NZe_gnEP
zESjJ~oVNm+1V_eg5@jf9n<kVfXzc|QQe>BVHZK<LzoeB>IlRo@!yH(RXFbn^44A$v
zwG<bpgbJUYehpr55B(NOwdCWbm1>7^+$9Lwz_7Hu*k8*~R<QEr6ZFPs|6SXL8Ggxt
zuFK)O#w*0me)#xZ%F8mFEqEzAAxy0wUYS@<4o}{82B2tmKDp1k8jL{MN+3cMhX)qB
z;YY~B58dl7c1-~xok7|_lui^6x@IO6(*TIOR(G<#HVSjrchCGR3MV331X4@=2-;92
zA+~UN>*ALIclVcENV{$t4eV_adO9Za1nIjq=<G;?nDrLBenX44k^m=?%_4KbeBUoY
zd`3mb4>&trMhB35zHX_@$>6@#od+4u%df1R59Cu$L7L?!R(F~graxO;aom+B|J1Ed
zq?Ji8-JL|0&CQ7DjD+H1QgQ9{M}f+?)uByojc)`&J=zZ4Oe{_yIs#^TB(8t{H<RUh
zU`|!}>AHzh<&;?POyj`KXPUw+7V!18_^^?(0n0i+ooLS@YI8R366u>-wGzel{mXHd
z1gIGQ_21uZFCwhb|JcADhguJvS87QMO~|I!2d2AJ!0G?t#O0l>l#OO|0KV`PU3YP_
zq9xaX*}Vww_YKz_K|JL1=%=QE2sh%_Q#?^jLg&%g>pbDyzd5Y073Q=GZ#fWu_X3k2
zM>AX;>PxZqe)-Hmj>8{ch-$q-AyPfmY5f?laBMCLXRfE_pvE5=<Aq4V`+2jZ5>xe0
ze)n$Xq1@}#{fBp;3g~g?aix+xklESiPg*;ZLXUKy{)<K7gUE(>h1WgjDixhJXy#1x
z3eqcT?J>o#{rr@?qm~pFlUh+e(42~Mj9=llj587(4Mb~{_R|>Oi7GgCPbhB1X9qrY
z9T}t)=RL*OAv7=Y%aX7YDYunokTR~hTk&o#o_!e;MvBNk_<!DwIy6AYVoRr7a%ln~
z-=yC{;6i0k!w-1zdUlL@N9Q$r0Qaz?w%vRM5kO(5V`>h#+(p?JNyc^|m{WHmeUSNP
zgR9UO>%y~U%@E3n{LwX@DD7a(;c^DoM5E3`cZ(0uBZ1Cbd1payc#cr)ky3MrJF%97
ztv30{FZ{%G2f*dt;D+5AtBvAqW*72Un1NVwK9Cq_<WQ!2*b;rwb7J9@IZo7Ic^Oa<
z4m5W^ouE^a3ElfaW_yy}V7}cEi_S8HYzaMbu+|qlt}TU6Vq*kl8cKGR7ZMkm0t;o3
zwvmGmZ*@co(yPZbENcVv6yJfh4JPQgJT<1{h`^r?HcuU<>z5ySSNn$PdimH!5z9x+
z&u@HvH1lWPhUWYJr)D=a-}i4grr+qk<8}U^`LC9<{8zakx8LG|d@^2wKs$cR?fj$m
z?G3y04?!nC^nh>Jx8oeK9|N8I@sD}H|ECwZgIsz14lU*O9a_p4KS^R5+vooc+IG$Q
zdhfdf?0n20{?oPx$wV%(9si7t9TLH3A3GUn(%9k?=ruaDnOJO&z0$c@*pB~xNBX{_
zKc{02g1q%CAbj5Ua~sdUvm5Hd-~QQ;x3ueblx-n*=aIe`N@H~6$t-@N9{>8rFEsou
zFC26<m${n0ggvUm#8Mw}Gv}4SaA7RA2|XCJKjzK5gGMTPp=U5bUbM_T96FP2vln63
zQ1-!&k_ygdCs*6*dCbLGGNeF(50Ll$Lf|}UF)Y<{a%DTp%a}@PBHY`;W|L6H!&T^s
zg66<XrcMTF)PnctypOd!Cv}|x)$uIZzF9H5Wm<wUdHJ<@r8G!J=-02kM*}OFGUbAn
zV|_3c<yI_d%G%N<F^Y;-NqN>8l*%I>N2M~hHVsuCDpMoZL99(6W1PjVnWa?{Y%)`U
z**wgnK-n5~DfJzp4KJ<?9~7*Udx!x_;1ijwg2YdlQgiU8ut0<}aGZrUNA*k;Tr1PS
z#8MrbwGg&9J@H@vM<VAf^u*T^dFRw=scy<uTi(YKTCikej`EW#Hrd6$M79L#d&;q5
z&BknDE!dJ4XY6h!LW_cr5)M}tdkzYWexMwRZ`ScWt@zTJOZnY|<{)9AWjN`kmaCGZ
zRnHXkniF5MH)%j0A05G_It)-N4Vjg#YH3NM?>qV~fqIrEK+m9&C-bQw%Pk>S<!(uA
zGZibV>~7cRvPxYeZf+}XR(8grdQ#q{DZ8OMlJOAReH~-i1vRH~!|1Y+KF!6^l2{Jv
znhyxXQ%We>!YDSSx<gdX0s#G`5KYb>pVE-KI<lxn5Dy@X6sW!R>)(5iEkL`J-C7aK
z5JVKWO>sTxalSR@a3i?OEWG9^i9!-FW=i{s?Q$91VMX;Uz6Ao}L}~Sq4in!5V`j!B
zZZxl=5+OvZ(4ZTwT@%J|-4tXxI7M-cK@EdSD?$9AI=u_Jf$))kzX^vsm59WCEj6#f
z>F6EBx*^v-$^xaZ#X4mUE(He7IE}8ZrB0T$(Yjn}XS-cbMiv`5zA^-BXcejUDgY(I
zfIEqz2sLHT0@MI%Y$5Fg!a0yA`g~l<I4}AQ4Jqmhq#&>O|C07T&~Y61ooCNzWVd9l
z1599MgmC4VQIl>$uuL*MFQV11XBq{dFc<<9O(lrW`%EEN1!i=%mDAqi?)hD&8wIdt
z&;%(i;)At1dBBX6kpkPYmYZYtv>Os`Q*8vHB!`#dz0;m42b)8(%!O8T?=e~J=04Q}
z%Cc|Y-MhOc{&A+Ky6RWI`u+L-e)X&G<R)j8PxRwnN!IjRD(%&VY_^`?3E=b5|I8-U
zMu`?6@~#uPqrss`=M<TcPf_LlBh=>bPi2Q}MkAd1QD^9!%Dt|-GkXL|z^_jER1oPS
z$#R)=g0lO`97|E>NzA0;QQsTt2e715k6l)jNq44{$eNqwD7lqFiLK1peaj^A)2YE?
zciXKEyJy?8j(SSU?D#--QiTUVU8osSU&$U*vn#uUd<yjWw|Cbvptkv}xaOv$RiJ<f
z?5eDiJ<Kx5?As-d1w(GyFPc2q(sY0t_rVtrkS>W_%coVDBw&iRQe!(;N!M+n1f)Cz
zh5;CAi}HWNI)hy7jt6GbRt-$bs`+jqNab$s{pDH;8K;1zMtl|3DUs5xVWF<&+?lMh
zoUBu;lPhmq#Qp&Z@^`Q(QeA555|xYsHrJ<)`2(sxxa7{;>LS2f4QP>05z^0fZTUG;
zFKUl^T{^praH8squS~7|tj7o4nq6BdlxH1sw^LTL*SaW*0L;P?)=OT>BxX{ZebQsX
zg=H0>29po+l?dd)BmvXxsR;_{Y6{dBxU-95N>*QzTgm2s%j!?(?L6OE3d7}<4GK)H
za>6s|dQoMpEc-Nn{im!sMSj2shOVhh!7G=hMadRCOE`wb3wKP9?#}@*AC|TD-i6>|
ztD2s@>nwScV%DzZoK!xwM>ssayT_r@0<{(zshI)jOqd6#jUS|$a#$<qT@IMr@^#kg
zMS1j6OQhYCQ#ajz05Dm~Fr~!a(PRT8!$TuJRu-89#XUWC7ZwRn-Ym#=u|{%lvG&{9
zeGWF2*^AMo%4WY@y3gL(F8Gr0et5^SRZEfQykCN_HcgcSS5y6XvJnAp*KN2bPoa>S
z?7lTVc}7TYn5rAZx(0jfm0?n=MaC-lW&fmOd4pxg5mVyWTyf)oLvac=^Bj?`b+1Fd
zI5n11V3j3RNR9ZVgU;xI+$@_u(qPj;3f0J1e7H<m8vX3mG8EPbtN?m6fqr?z3e44*
z+pAN5_rJG<KsZTjcRXxRUqg>t;SvY>*$-ro6^Ek(vl(Gv(sGu7N6NLT>3p%Af%}QS
zWomb;GDFIHwp;U^V#-JVhpD_S*fJYaQfHYS)JJV(FzbWU8C^GXtd3x|@;&x-@57d5
zMlG=i&d9Q5%?+o!4#GMml7k7~YAA_Sk;(hTr<@_qn<&x^YcQ4Ltoso^_w-q3lqoLO
zvcwClSwVe1{1$4q6LFU;hFMZ>ede6NB#S`jsnTaS!nduD?J?}dX4aBjHvDewP9uz<
zi&bVX)t(*xAmbE+seP)?u4}TWYv+2K1-1`lF1q<g19+Q4IJ2O@y+zp13u-PSQ2ETP
zV+Y3q4~Z@Fym2;+r5ObQMyQhU{hNRC4@^3{DdL^ky(VSU#pj4C!K|c_7|N5mZP?^u
z`waYYuP!MnUfVeneWCsajif<DQ}w-0nqe9J?OS=25j=O6!7(%_Yk3~A*IA=MFvxE8
zKf6x>B#IGdcnbOcBpV$D#E5b{znsqvXL~Z9SCG^Bo)2)&O@<i1Ti)3UYESp%YH6Z#
zB{fwx(Nue(phVf4&w%c~luL){JTVWLtj7-1KIE9xFUh+qcGry3l+y4IauklAsrh<S
zr-pN`^Qdm9mdrLXs#bpDqd#SU_IyvK#OMVir-F+mFHuqo_A^{;7fVr3Km`%Ak%GNW
ztnic{)a*U>87H4M<$n_Sg2;vStgqNi?J-3l%qGh|tth*l&jhs$PsrJZG%x*!I~qNi
zZy%I%)9S5oTK$TeyQ;2Mrj`GACMt`eBdwv{rF+H6-DkYvxM%On!*6(R7sa^qb@AA)
z883Xwt)F#1xhelxpFMx}8$BC;w)VUF*K)0ukznV$Zcp_o=UFG)+*@67M}mdfJ(0TD
zBQ{WLQ?vIv)Y@1kfUc+JKDoS{9e3;gos`C5v5vX}Ikx*OWiPvXm#C~oHRsl7aIfAu
zQ-6M@Uf-`(??L@X?Hmc9E3&Q%`zdRILT{v=#c$1JdtUqV50=Y^<VjI^V<z%WidpAs
zFs<%es%}hA4=)Q*E*;%7cXZFGo}ml9PEYY*Pp!54lb;l7WPWh}z|H|q?-kXrE`4`>
zY4G1Wdcmzy-fP4k^Ro}=>`v#~1Ma=f;QpTaFZ+Wa;uC&+u=x9hL%JTc3ln@7n?9SN
z7WQUmXD{j5xrcJ~e-{+664(i(ulu?7<iaJ(TPOz$erO6)zaZ-a%h??F)=v%Sdt)*U
z&ep+BReO{nvaf7s?$$p!dQpu!;zaH$LXYi}9**SFaPp&6IjBmL$4N|n+VhTGDw~Yq
zt4?cA0_jpgI#=$y?+@ibt9PY9wy`OxG4~8f$i7KXF5F{4;GP5o9@0Mup2+PYKfx{!
zd@@HCWTAHMXOg<q;J(eDzL(NgZ}|+Pup+&CNkndtdF3}+A29`tWhDW9$y><z!Q{^6
zcnxG4ci9}==;gqQz3^K(yL;ll{P57xNY35bl^Z?CxsUAg_tYcjhIgqW)4w9D5iz<<
z$=+}5Zgo%Webo7c*wOp&@cqSw`zFedwvPXf`<FdE&HL&{w1EH*_=nWJ-JFDV?!m#g
zt7@Y1FN>EsCeBe0{_~!P^#iTGw|kbVK(>D<sGx9q_Ma*e{6Oe}w`BY0P6yxf+q$Pl
zse;ohKa?aCo5bg)?tObHHy5kgSM|Q!GAA)o+4hAfyFkX=djA{xTYh`(7v9i+skQV@
z^?HqgtiKSi@0h4lmAMUoe2do?x`BIv*iI9pn+QHUv}wTYds(+lQ8-)$<M^ZD%waK4
zX5!XA%-oy(n8WVtUjWAY>3etXU7~mz7_~UCXHt_gd{*yKEBi-4+y_snH$~bM!dP?w
z%I0+6lpF!%{L7^t>s0RacONFl`rPtRYrjvrryICaoU3OlOgz_3L4zl9Y!d7JD#dVh
zY|<*L)B|3rl7HE7LuzuI)ax3oiY+x)^g86`zJ=~t4y$YIZ3&JJwf^FXJIl<HPnu}v
zFe9Xjb7qK9%-LhQG|5y@frRsfk4!i3n|SmI@7!bVYvq)ILMedzl%f=Gfeheg_lRun
zzn7ZH7h30jI;o~TcF(*+TA>s-2L@i%2`p%x4vMJW;!M6>d?`nn57G&m-HW-C*tTu8
zkHW(*Y`g?wU2)#v#6IcO8D)H=o(imbE4uE3?}2^BUacKhGS4nsueEm^lNF$%l%*U%
zrj{rj8Ky8V#d#?Z(u)wx{lgwI4=YQ>0~420E`27^aZW1#3H6TS7`PO+dhx*FjRy#K
zJWR3MrSIzW*i#MrR1QE#^>KFGA}8P#!BaW^`o*0lQTlF99CW8BT2&a(RuFelnYWSw
zsc&!aR979<+LPE+!{&5Ji&<Cz!fGp^*Lv#aQ@_!5RCseaHXx8voA%369&T4MrSr<3
zn+%)X&R&%PeI15f#<~a3doR0xxeIvtbl^#K?m$r0egTG0|3OH_mRxzl!<@Coo)Y|T
z)CN<w`qJeGfAc<rU>5s+C+FMb4$J1xk$`Lp1yEJj-9aT1Qw$oE_>t3o!L`jHdYZEq
zn}#hw<4&2}-Ru5cHP{D08LQ&^AH8F!1wu{^%bdn)wdP(K&X~&Olguo643*5u6_%?z
z{V`|CowJLFbv})zuDb05C;j<l2bi4zt9xKx5Vv@?$9nJyy`y%Hot-IoIj@U<;ulQs
zU}P{?#es)EPgg)?Qx#U3zfJ*ecA=S*P#dJbTBWw&tD?S@dqL+{fHFnzTM%~PXxAo|
zW5qCV!5VA{AATsMA*yu|U>UYx>%dw5^5@u(So6;j_BNA4tNM;HtvQOj*!ME=LTilY
zP=39^DTQPD!8;mla)R6KKD9#7q#I(bYDQ=UA@8r1+;$ZkSD1>;?5o7F4J?)$`LuI(
zj>9yq0M>XqweJfh`>?K&?HXDZsHei_>4$#Wx;S4b9obXKw05Uyluu=gCv}hedi8|i
z1OM7^=B84CMSTmIRE@TZi%Qg1G*6WN9Sz%~q|CC{TR?DFug7$0ffCj_<JXwS8i_4F
zAgp!9vqCq+d9RT9DRyuMUaz0J`Ot95?#jjDOzsjM2YJSlJ~m}3o6f4LZO%Jk4_E!|
zTu*H(z|OwbgVsa2?907W%&2_2)MA638$7K1zO;2L$cny8ZfT`p;hmk^&#|CX9mDdp
zl$CGGT8af(!glk|1T5m3e+fEZBeO~-zL=VSMtG&8j+eXWd57iDievO1=*w_va;BWS
z7<tFad1va<Xp0=ca;-b3?)$dtal!d>rKDa(Pb*8&j-0sUq8gjoljZVtR>c9oXTYKk
zqrcbSrZS%<)tODdHoNPruv=$L((fQA3|szQRd|Z2L@B(*e*fAf=o5lB|J~#N-!gtb
z{h#-Lq6ps0p@I&7bPfdk#D5Z^+%D*xK$P_a=j5P615ut$&L%w9OVoGZUzA_$y;uDO
z80nuiexlaJ`QO>DbwR<5zxr>dj{j->>ZHM3KVK(Z_v3w^_rFeOUNn9A^v^!`;#)(e
zPtSGobxrm!Nxy&nmBF7q`1j>$@mHoV{BiWJz)RoquTK7z!EQTgzx*<3zyG$A_IqSI
z?Kiib_WMu2j%i<Ga<{Kix<9o${aZ!#F)&oOz^mY%sl44tD?M-5q@5>sN~d+;7x}JH
zchc1b{{>m(&#bPcg4&87cul;qnko`*NY%jerIpWEo`r7W%d-B9=eHmB-Y?^9n+X=?
zl^PyEa^X#EUwBc;<!=AR`o4YTQ`SxQS8DhTZ#gUpof-lcn#<Z3ch%#aF9|=h+vXg+
zr<}cOj=Qse#s7A1%MHr|%WmVTT<=T}eyDEO%hUQ2+ivUU3gJ{R+n^Lm@uD73!kwhZ
zDVvJFK}t}Q^HEm{2VQciF&y+h4G84a@60aTt6a~j6W!^-LoBfuc&|;VLc6Y<M_H4-
z{d)^5ZoYi$)8D5oa>fkEx4LAHtYF-imwP;K?#b-S@>@=7;J)v*g0)<3EH@;bfMie2
z*4u@k#>&9VI9KSJ@yM}WbUBeFlj~h}y3|UcNC~+v_l|r}w!@WzTe5wvDC-Gv+};f7
z3n$Cotl9XCT&t5AMlFJ0u>Ej%rlRdU{`aT;I9(~*L-vXzRLN$)FLRJPcBwu&a}fZE
z&k2&}R3qK!#zHAlYtJwG6t>kx1VaE6i+~aMSQHJmi{8AQFSw8DtZN-;q-v?Y{R3`q
zP|!}hT>HUEc7_;%(N~t34_U)*`T0~{6;?RF(enS|H&R}|U;;^^%}Jm`gI`$eNI&aM
zDqQY7yMyt!N_OuK?S}wBo+`m?R4#DCg6;04ylqY?gQ+WaNhlJwEOy5l7RjqrGsr$>
z_t6M{?lNaLku00)b+9CSQa!Dk2Z0W7G7&3<U{;mWI&U9a!I4%lYCglGM{&+Fyh;}U
zC3wIxe}Uy%YPso~p^z6u<`+Zp^LLOXWd6Ylyb)L$Zx?qRdIaQP0#Wg+nZ5Z-|2*&X
zq=6MOa~|+-&S6m6I+f)C09#0XKkMZke8F5$OR45$UM@30QYfk0KyqQWcxL%5;9Q7?
z0DiAs8sKO&y#glDhZ8ef*l&7Ja8kMUzL}typ9#FI^|Vtcq;NVLfLn93>HG>O)D`po
z58r(npPk&m^pKSHT*fa@P<$ECfd#}4*e#Ws%}%;fk@V)LyX1^6Q?Qc07A;jz`)-$g
zCf6%CpU)x_Imoh_yaAHmx@LUb@N8+BqhzP&atfk{yUAk&MJGj38ITFI<GxhAm^!mG
z5M&SZX1pSW$1ABd>vOF;Bv^{8{1V{1#e7>DzHF9DlE)Ya8HmH2qepIaHYSZ43bPT)
zP}eW*@R@br+6Sddc1Y^$KH1CrWGq`GtAd#_8^sg|AD|{DN)|Zy&id$I|1C1lU^=P+
zFgA1yD>S{cXFyY{ISq2@Ica5N6M_%ulfME|R2RxbI4F->57Nat*tO-eRbBCbn!_6J
zwM&NM;SP*q%e^>Y@T{}EU?K$C3GACc{f`aZ`R1u)*a5pzLV__^A$Um^JH($QpAksF
zFBvpw8`;UH@<2R!&LPWlS2lpPK<doki{Y$hv$MI1R;`=~D4haU201)y;uRLZxzAuV
zmP0R&DI;W+8aAIOB_GSP{(w^{H$0F)6QK_@$Bulv%jW221@ctbP4{YdkQ-Se;u-`L
znIP4bNiC*b1BW1^vo{}kg65S|OPN;JcnV{1YIdPyms|*AsK<*8YM%Eo&3vCmJ)f{`
zSG&g}bmL*y0j=_+6!&E%XpM<Xan6ISF+^&6xxWdP&i`cUe_gI+D5^R$S3fB6HlFnK
zw5sp2y|^pQ6Kk&Gk$J#xy*)^zFQ_+T1PrC)G!;U02x!=cAE29L=@Gx!OY=6_x%s;S
zjsCm+=a-)O5U!MG6$+S!fzBRtb=SbM&Z>eZyV3!2LBXJ^^E9KgYAFk)$rFgM)KsQs
ze`Q8%pDb`!>6C>$qwV@##H=oAm*OHuv*rRA4V1abW(ezCUi*bxzx0pu87N1T?QZT*
z<WQcG`8<IBhP+}33(ZK}Ht)i0rV4g1A~|Jv-dy?p_&LDjHDG4FQ?oZ81kmM2EeN!R
zF+P3}-Z0H338fH3BlY>;`z}QpAlElxpE_cXJONcpAzK<idNMHmh61qdMN&psXLJjQ
z4Wx_zqz2e1gd0eK^OW`P7xR7w1AzgQ(s_GdpdDVQ#UA|WY(EYz!7C2oeVxB68Crz`
z|B*BYKhj4|0R$;VgyuXme^hnx?OHw1EN=RcPcgSh<vjnp`OZlmbjFh}u$-dFP(@PK
zROG>?SSTt(?G{VYm(HB|ux%~H|7t0p!}BUBpv<NpG*UVUYVd@MG{QkNKYFztEH9Vr
z03rntgEDw2O)_XLl~472>hIlUc|;TLE_p?FMh8j;_mMlHGc`I75V*q(e*3C%mL8}u
zv!1e!NNYCJl(DaTV0b`&H<S18&cbcP98mLCJ_rhDHEN{8CC!3)dULN8{NB?f>C`bg
zPGM6_seRtZ+={!U+PO+w-mmTht-91$=vj3l&+B(~r7vn#p%NLRh8qo2)k*ADSWkJD
zKSvo*R3(?+?Wk!bDdy#T{Vfs%IfgZC`?VKTuWtJ>dbaITkfQA`%=T*i-FDxf>f-F5
z1$%#c!0&AbyhYSb`*-!eSSVV{Ik%5HFHnagyX(SzJ3Q&1bUgWS&tE9dos}Qci}LKE
zZ1`>Y3D<E4^v84{>n&ArRZox`=*>H7M{toPY1R(%k64J#g##RWY&RbDd*uMls@%oN
z-bi{!>d*B&%ZX3w$m}JOP<*wZ{Xg|vK6^j>t<ayQDs%3^{<ngafnuZ3_pAQPFV}zI
zH{AR778q6bY`(A1w^GReru+1{!ddEt7K(NM){771eKJM-k9(ft$9>a&{Z`;r9`*I2
zM_#u{;rP1eSs(W*_F?#ZuOX~~=9%G>Mx{*Z8bDsVd*=z`t7i?e?}HMO1M&ogAS<Rw
zfN6sbb_Jh}j9IG>BO2985drfT#g+E9_kZ%5#?*d_f)D1VZU7DJ)EY^fdv#!LGIw@=
z@&8C)Bp>G`&$-hn;C6q_JyCr7$ir@9tG_Lpp_V{et@}5=q+a%LxL<GQ4&?eTtgYgZ
zy4{oxxBYwCjUE^Gd2T8U_V&QKBw>NLd~5kp<8q(&-|~HjJFPlc*7(Ew7{Vj%^>!br
zM01*Ix|+mFvHEk%{HOcrvYVObSlu?q44w90_S?bEmHi+w_h#2#%0AZ}G}=Emmb<93
zc-mwvu6#ALADms$*}qx+sU{J%);{lI_I@GB|7wt^c;wE84l@QtaK7#pN-ukAN8<#w
z)*p3uGcbhi!ZNau)$a#EiEaZ9%yE>eIp7&G^rk$_Mz$_BRv)>jD+Ubo+b{Os$#&<k
z?*JPKiYM#qPUh(s%=5bK1NFCcu30!m&Q{Rt2Vh)GV2bV0R^NT8zVtF+$8Xm4&F=yE
zcygz`H<?T7pswig;QmLzXf}vX^>$x~LxX8FX52z{{$;Oa`gtA00D)+l)LmM;bkoMC
zx2)GSHBVK>sukST?tN66Yl2lZqcyWbKSQ0`bxI2~Uf4K(M9<o1+&~}TI4wR+R$~tM
z0(|h?eOar?9*y2Q=uzO?U;Ll%>h+Z>-(9f00$>qYs$el~lOhKcq82vRcht^%h6jR6
z!TlSROjDOAXG*zJyT+8!zmkS$4Xy^J!{ndz7rIdp`9eGHEnK1w?GVkK<AkVH$_1Q~
z6b@(rreStW^-a}HUD@veP0^G=huRzx2V4b&^<vR#9zfXbrI+XY`PBD=RB!5--xOUk
z8}vY`CSVo<uebbm&;a^5>sbIB>_f+8qGS&1A8AzsOVZ|Wsugz68=Q`+twN%@*b$Iw
zXoqdypeYT~s{o<`>uf+FfoAam7qE<Kon~|ftR<odC3*`~@U+0-o?c;wkwHaLBK6Jb
zFEqPljSbuMz&qyNA7A%V>tHN=!ue)@F74b0!Te@-fG^juEs&dp{gNM?VgWFVt=|pf
zp{<Z>bYoou-fFAjV54Wql-sZxFI1UNbNJpuk*@5YlhFS(96|@PFo)^YS<?MbLBPs6
z>(w#KBO$LPEUyAk*>K1SgjNl^s~uZbQ}Z!i@XW}slZ$F_E%W_S&No92+lFN5F7#q9
zTTwj{^F3H^KSITl)({hAoeo>^VQoq<@H1osV`X*fbnpX&JQ(Ju;kWdh?b2egmpVgM
zUmp-Mb686o^f9MzzV#+iXn-p$AH7(1vHwnyK-lb_&5%IY)Zm4SnqHb?)A-fn^5;T#
zgH7Al$%G?NkpGsJHk;r}HZZ-)_q6q{)<0qa<+<giq$=>kdOWh`NIwKaJpQ(e)HEHt
z16u)Ou`dl$M!M%k1=X0_5XdcW|Ld5_X4c%1Vy$c!tR9z>RMO$KqC@R6OBB$;s*Xy=
zKd^gT3@G1}k+qxM!ooi{humU_bNq%+1=lP-bm~6squ;CiCDBK%{VZ1`jQJ=<YAwnV
znYUaDSp+HT_kQaxB~cjtMs@T%Vi}^4^ta_YnU{jhPSh{xm@z!~fd@h7u;Um5lT)>U
zzUVPh2Nv|Qx@SO{Sp2e=_g$T;nsm%sp<rwip2<GrncM&wgt;vA<_=Q^H>ZQzqc{@1
zuKeMzJ@Eeu3^VvszrmltjS~E6@Ml{ucA&7<Hxl587oNY>soeUj3#X`fdcOSmg(UwF
z2<%57)^;Nw-)`i&Was*)lb!2BX2W^{Vs&<|-;zlyZ_R>%ZDUxse&an1YkTYZzwO|1
zePChVc>f0YJ*F=|f4)q8`j+X-qqCh{$er}XH1ZQ=U;jGU{|+kWvj6=y5O(qtn9j2A
z;bIBbs*6&PU1WIM$QnpEfGhw0FPs<3Ai}KKpsVd0<1JI`u_;|?el^P^()qQ>trz^r
z^)0VxYylEW+>U7pt27JzFjZXNWZM6KTs1$v{b_7R>r<bDlU1v0GEfDjO8RJ!#Yy!^
z1t^znYcFBGpsF*Zi-7$okRF8{U&ig^9GHE%aL)L5-+t5|b1lDOgDa)7J5LaQt^xSs
zr5ykb!kx@sTD~4IZ0y&Z*(#TJ@1h4Vs9R*OfA`;$T^UTu-ML))IXd&3Dun~@m$^mV
z2c)uA%is@Fea@J_b$|*sojE=>g<?w&HvCg;zAXic0;TMVp6xb;7TMQI+F*&skgxN`
zNMf;&)QbNSoaMC?>~36*?|<Y&gf=pkuS&VQ{W`tCIZ)+e3jewAF~=gG$zn`umKZO7
zH)bzUTUXe54r`D0g%o&0tB~hVX8qD?EnwKR-QAxm@@Otz=3~|oGKJD@xA*Pe`WpPA
zA9YIUQZ_TJ@4@9yk)l^%i>0kG%fUmHg|ErC@g~^zN0(;{X%v{SiujD2vdsY<_(R0}
z3n`N#<?ETC!8Uy!V;-2!moqhr*xkn@7qi7cf9-1@05QP3^L;q5*p(?*8kJbERLDdb
z^wjU-OeG*av!&9b4Q_+fU>>-iW}=WYv{*Bc0+VN4Rs6J41{VYjEMuKDTeZm_`P?UV
zSfw6&^-hOeE!(3epU8`J7zd>|5H%Ucg*rM)mwn^Y)o{~t<U#;jU8FXFWx?}-wZ}=h
z_<}j=!KSPVl(dUqnJFLhb?xUk&3g~diJ$TrXi>8qNJ~-fpncsh2An=$NV{iW{Ndsn
z5}2dUyKH8aWEJMMXE`7P(JiOt?0zhM?S$;lCQWT0=W-<^%lV;SwsFRgn*ce&Qe=Oc
zt;rmN2SmkrWs0rG<hK>^*IY{)ytEG=ufT>_2#%~y=kK(vWy^I>|HmE1?Sw*xRHdA-
zl>=1c`M7xwd6I6)WTx>ZS1px8YZ?55Pl%lw=0bM!2E27fGCnlW?F(>eN6|E#XY7CR
zd0JReG&gISVpa9aOg>dA`le|Z2Vjba^Se9%yvHpDBjgv)f_GB2ZX0jihhU~fFK;U<
z1o(wi*{lm({M-?^mbXs7{Xx?T%me6%oU%%s;K@BD8~A`g4<A-$pk^q^FY64vM2oq(
z3~ix@OePNRxb=)#QRb6$;r3OmrN8Na$WmQ*TLtr4*`Q4DeBRCE;n9oIvZCZ(GVhq2
z+n+Qj9*C#d*JIV7x_KRN#`5?$LrXDsKA1O;?RsY^2PjuUGMnKrl)T7!=AGm}mjL1t
z>ahV6way7+R!#)@56Cj(=o0Q7JO)t7Qid(gI4?37CuJRztRPb>q6RF|r0Ph?^)g@j
zy&a{rLxitJ4-7nKb>)B=Y8gh<r2(c4Gtx<D!=mLESR3)u47rU0cs$=NVhW&2%g-BV
zu3GH2H8m@RS@g7bK)JG(V(&5|EoE*V`Xe&{9-Qv{PVhOJ<Pltc=fxlW%$w(#8RE;p
z7oDq|{3<1%`TiRpL<lfYD3si^eNX3I2AH&9d6K5|_Iv!|e~ibgrAy3q!YDwjCQ;2~
z-eJp?t(#$sTLio)vxu-<smSYWh3^U!;C!A$M$7639ewW&&<~TCmPhcYr;5z2<C)UW
z)}Spt7Bkfe?XuybE?Uc%iy3-72vrS}<$w71ht1#(eDhTCBP&I#R1^n1bHgCU8<LdW
z`g}H5IMPj>tYZZaQ#|kQU&;;cpaIq%s>|x)-J*3dYu==%^wr?}bO;OhsXp^wr&V{K
z`jT?c8%Rj$JbDH0g$Bu$>oW6_=S>v^$tw&d`Q4$XFdA|D$`{k3GbPZK&YO$=LqRyW
zr0lQxKjqIcIAef!JyBp#VYhrx-p{!Ak@&L1DqwCLR92oizt#OSSzOK1lym!SlFPc-
z{ucyg*vj92|6+FdWiJC+ZYg?Y-q%6C;3w_-OofxYT|1x_6)eTm1I|PJ8_VC#s8~c@
z`-{wVF;hwx3~_$+`rfo}UQgz?GZs+o6a+J`GGOM3swk9cG3c+A<BhWAcyLFj8O!=o
z_+ir^x0dLKMFx#!T{L|>+<4#1#?ZA6nH$YFWJ&Db+Eed;IiW_<$eAPWySwzxFa0-!
znIR{Ry;XXn`&^Nb0oeiOIUFHvb$R9o4mFMb?E<s}n)%VY)=z%)^&);Shy5jlBxT03
z(EX;}Ao=94ihL@+X2@tIZ{BqOJelIGRj?R+$)@Ni>emeaa5DRbx&`7LhKjk`el{^%
z!f>`3q+xigzu@pEge+x1Qc<{_*J~^U=ol3Fzt5JC+5eqE|0gfg+U=`G3tT+($FI)o
zFkuZ|qFw9y&mtYlqHLkM(x}Kpev!W#Of!9f9*mV)f;>65GfDIHVWyf=cb-u?U@fz>
z=oHQg3%N)ar9>Z$0k<Fylm4KIs4L;t(w@g#`iv5T_BX%&!2)DreCgyDe{mHGUD<Tf
znh!8;UP0O<VF&ZKA%17^B=49XMw%HRi_$8lF*VKg{rm6wnc^pQE)|N-uz1WF5ukI<
z2xVwagk~glzxx7*yUMq^gJ0`jxi6R9f4}$hPZr*uD&JG|ejwuc;kP5jN4}&urTbM~
z9Z+Wo;o*1sJ@*#epXq*(jKFUdmj-V?V_ZEx<4ja>9W(zo59$7Ye8{e!cu4AgZ|`*R
z{$aN`%_HI^)>3H?Lv@A+jCvfycF3pZjO705LK=>m_TaRAlBx1vQs{rSR&?I8ykkZ4
z-Z2Jm`TLal91%9FxDO`HXCC;!yg6&$%)^i7gEwD&tTffLclc`YpxB!!e_W{QKv=ce
zU5DwR@|SXF?m3X_-s69}{I{nb^F408tUkUr_>8wteLUK}_f*K13$mBP)IEjS?ngPm
z;GOPYd++AUKYsHDw!FFd-kf{;?yH4g;kbg~r>3g6ia&X`&EXHG8{0Sc%|=sGuH)^U
zzgB!G+WX|cyL;B(pQ{(xV`O3sL}}PAEUNA`aYOcOiVIOofYWF|mfYFiy(`_ME)hz#
zn!+<zWv05QDyz|0<Q)<xwf~yF7GD$B^j3UAy`z-LC~%8?#dAgA4zK9tpBKl~c@;-;
z{=7J^Zpe3qtZ(R3Y9y|ca5n!Cl7K7kn5z|mz*kyTnqS{kOH$R_dbXX@9Fs8PtKPR~
z+Gb&K5H2oIwzuG~lq)Mkl6}V_wi?ROGs3&50xg0?WkLkm9NAUe^ITa<S&7u>jHFa$
zYhx_BA`Z#$@p!(U#D!7$Wn}`o{IiO3YG&&Ap5Wa4SnGjk{d}|<H^TE#W}+&?NwpX@
z+!Ly!*XVEtN4L?Ejc`@Qp}L{Bw7UgnrUN!-a75g%|Motrhe6~z(gR8(A2PK~5vxOy
z7}O6%q%1lc3MlDpp5kE%iLo|-H7i?US&dZ3#Teh?(W0#05_<lY(x<{jJtCtrZWUWG
ziorSWI5hLT<HE^-B!`X9it6L)wAhT6!$su>)mYCnaw9aLsxV(pORd|LwyLzl^%)Zx
zq%wXZ&dqn|yZ<!#7P;Js+%|z%x_etkk5n?GYE)c%y}!K?H&lPWJ1K$@8DKfm>)sSO
zwB3vkt_h5OZM4J6yHU6{u1WRmpA<tq(=icqYRV}5wBs%3c<Zs_tv$zAixZWB=?T%U
zj#aM+8IOe<Tar;u#23_nQdk*ghY8IlYzH(KG!5Uu7_CrU*T8?rj5qkh&;F|)r?anA
z2B|u(hNEa)t-I}L-3d2^-jc5Crp_Wg3D=}*v@2y(R5r=plcO6-kE>V1$}OrK%)~=C
zv>la|x=0<bgw*GTp`7RSsU33t74>+v(SKE`nGHHMbXBz}w>hIRBe_@~387_EHsGCA
z!wfnPU+n!Znu0?zzBu!@E_LmK!~?mLex1V25U;oOk<U1D8E-sVzb00r(amZ*9v6YP
z*3?7Jq-f+a9bUGwl~&oyXR0kyQHQ6iheQB7i^`jV9J)hF=%LRlrTn?vr1q_1)2lo`
ze7rdS*zgtS#Z`Gljm3-6h>+n!YW~d#LeK9Qba5GtsRx%N*E+lF*INSbiW)RpHC!fb
zw(!O;re;^VXTOyz@Rjhg&r{)w3iQy;c#N^i$|{y0P&7y*JYh&|sNs3T2jPHCX_o$g
z`p%?09Zkj?VBceUQB7!gf>a&;AuNt(WKs6DqT%x@++bO5%6F8E8z+?5b%J!oVBT;L
z>Wwj)E7U4fYE>&=*E#o`^Dnmi&(}>6zINgJzkBB;ap}h-#bhrG$~HDF6|tdJ{$6LT
zj<$h@aSRhi&SPpwuNJFOyKz)NE;Sfl6&KWuTvQExjWaraL|sWy<U~?<i_S=;(c-AS
zXT&&Ld`^g?syttvk)xCF@O%BufcqjYT(^H(UEb0(wWzfwNL={gffE$NPvwn;$k^zm
z^hn5*+FPr()!MKVDPsTa?f|ON9O?<#b6&OO;Hn;+sWzx69G+0`DlMv}t4N1*U%HqN
zT3*GpR*Bg4u&59maQNUWvK`Lt+GH_IiZJ0=GxyuVp{2mrsrWEXAzS4>q;=@F>%m!0
zUBCH<rvOuO=CaWlerw1GT^R>KBZ?ZEvK7fnzXM(EAhC-Oyz(=tBP>I~;;5?6it^=y
z>blUf#k3DigO2c6<9|4`)5q7En2;~SBl?00ThUt8ZfLozMz7%oCf(fbqm;4Pa?&!~
z$`jj~F3%7%=K5E^^dmB65;+QUjFJ5tt-~piYRt%>q4&0z(P!``+-Yt)Rvn9nGxI&u
z)gW3752^V9HQ#ep<T4oUY4pKy`j^jmi)!?|aBoEsoX{2vtfRSSl&a>YwP|UaCo|qU
zb;VZ0%9e6Bw3>@`X!pjTFA(t5vxfy(l)0Gc-qz5O3JOoTP8*%4)++sv3qA}>wDoNY
z5->Z$Y9CWU<6RZSht%jps_GzN2QMgo&QD7ceGC~XGNzQ1?)!nbFrA(n5yP!;r0TIC
zN8(a0GZ7mSCaavD=KGECH;a6|6;YRAMr(qAwz^pa|IBZ5AzWh?i_sRNt72`vMHo=z
zTbi<_sfJnIX2?cgi&`Yc^x&kZY{~P{rg%4!r&WK145uJbIC@QBm(|j4BKHODsZHV9
zhg4%ZYHU?|BH_)WAKbPciIYKh=!jlLu<HC~=-yCmbRIFv>{n*$JKaL+o6mk|C{s?z
z==<6HO8GObq0eL>Wh+D#YvlQARj!kl0w?oqx|!<rTjW@KO*N*<hoVuV{>RjsHz>_&
z2`11ZWy|mnYn4%>Qd@iUn7b&3-(hT6Es9P@ihT~q1tWnHw>hCu#lcFVyhm$ey|uw-
zD-d%LaiR=8|Mk~MdNOL?5Q`P-a9oD#w$v4*>a_5xZC$GqPTXG9fCsW7-Vti_gt&_O
z=TJ*Ap{~Z$BD}@1o-{ilV`bL1n`d!<z{=CPP)<}=k-m%3MD-bgxSGoeZ7%}9o9n$*
z4Na6}8B|uI@%Rc8)KbLFLLyw*vxYU-|0mA=+ombq%~qV<%&ehBgLNIpkhFp#BlN~-
zP0Orq;)tN02i2G!f;fj%@RHg>zR!PFh#?L#w+%TvYa4P7pO4Pz;U(3$CLXV@w?sM8
z;Wgx{P8id)XqkYVUdJfWE(K`vTl~)~>yrJ=2Y;$VLJN&;Xv~*`$~C<~bfX1q>{No=
ziEOMXw35822Di{1hBJ*lvZI=d!ckivqPK?4$ec1dBm?iVT_jR8IU%Oi;JZ?<#|py+
z<EFE$AtDz+L+!fKjT2GB{Pxnw#NXc`@UjduWb=0(!Geywc)j0Pu!M&_!@>A^=ITv-
z25}?iQGyrL5+=!5=v7{cE+}_EH3n1^BoGuVg4J?-Qw#`}#xttAS*0pCyQF#|h4jW#
zhp35-VR#8EuFaYZ*XWITR5Cg9Fz3z3rV}uT=bEnPjhbwQ>uv52JsDs_k%E;^#Gm00
z>B*XVK}AMAjL6{&EMa7-QO!^*zfG$Ql((8Hzsa$)TOy9f#OcT$k>&ga=ApxD9s9k7
zY{cN|UsY>xmsttuJD~K}J`bvgvrGgdg%&ne0ex>U+iqsvWd@l@*G1$e)ards06@l7
zr2h%k<GdTGVB82hJvu2mezze5JvXM-RAolQm!FKBb|^e-oT`m*bg{%)sR^~r!@P=%
z)Po3X6_+r3gYO`KRvX`Yk5&mSXb@SeTk%?Db;Cp6L0S@5JFI2pGtz>k8n2*M<~OS_
zj(0O+F%Ove8R{{;$I(X;o9m#EgP94~Jye@2GjC%DZkn(Om*G8g?P$<YvZxdp5KQ7(
zV2tmqm1rp8DtW|+^$euZ_Bu?3#Ga9SK;Nbmat#Gxm6p^fY(A#fUQ$tH*bK5A6(bUc
zF^^;Nh|cNfd(?%9qa*a1H;$@-0*6#+$YgLB2FFGkqM+>b_b`lDgjy32QP=;)hqsp>
z(vh_lSK6_ztjfIG608cl@q#}4-qJ(*!cvV}Dr&55RM1(q%!nL=okk?KsUc844TUm>
zMxPb)2!vKVA-BSTXuLWh?D8SSy<@k<7wk)ObjQdAOyNKomSS1C1>3s$tG}E8u!g66
zXU@5kds%u3PvD}2{fPF2s0n{!jr7iCYMEi@A!XKI+;~Ss6?pxq7&TJ;s3=?3HnF5U
zp7{du_d@g#f-@e28EzS;9a!|H(q*{HfN5qCnq{~atgS(?Hn)aB!-jyCy7~O0+a3uD
z0G-OoW5y#HSKc9UCE^I?>iMW0HCo~_3aFu9(7k)x9Vfe^4CFC+MjeXAqQQ5Csw~Cp
z7xbh!q=q((2`ufzBT2i>;mY%3D!&$usb)CXza^)`@EutlQ5<Lx58(ebmKB{f9FQ@x
zASMX~BYk5X1C*_rI?Qe97rK|9CE*7T<n0G$y5x?z9Od)pW_&7Tb=Q2gJ5^Iq6*IMs
zD}&iJQw?Yr4z#(U<FO*Pq^>SUhY*~e(Npu7Z9}+Fao9MarZuoNBC-!_)Rlc7aJ}{3
z%ve08MJ#pYf;yo#<reEgmFS@%Ye&GtMM1o_wpL-uj!RSnYrtjosFAOkH0sW?^C>S;
z*yCb&Q?_xHD+i-1(R!u=>%u0%Z3MvFXO)hM#tn?mLt+9~#L<p%H8J-l;#e()BXpDL
zui>3eSDf^e_Vx*yJukMf`N!oU9m;FfnK&pXF+xbnBHjTquo^eOHRKGud0p3E=ze;o
zdneguA6>g+PVAc0bB3BHa&gYbNlsN(3^N;+ZmdRhCft;mv21c;!Kk1LUcvMys#Ovd
zK{=Ic#tzuRKncRhXe172^w5qkDKn*ppu;njR<Svy7h8k2@t`Z`qgO;rj4R8WSdZ^5
z<)kh_Rg@wSqplg-(o%+)G<l4-<cZ(^AO*d1$%Elj!VNVv|2p0g31n@fE&?)G_yC<V
zU4xXSxC3H;kXN@b_tcme1>VuuqPA8;o7%u5hUr`kXOJJKh2u;W##=&+RM!!igR9~)
zcMi@F5oOJpE1?OJ7lCWE)bLDrQeB2Q+d8-W^vXTGBrQJbKl_Qp)#wuY1-1D;>4)8I
z7|<y=q%uhlNz_*JSRjtRA>gM;aab(&lnvFB1xPIglDqRyDozAxq3GsiEJxxAT)Kn}
z26Im)RP9SAWNmtKDjr;qUbMA@kZq`0wW~7MLlu=dXsY~<XX|+e0D{|sMik@SHQ)oS
zN?ZP;{ukf)AR#Zd8YZhG@3a1q!`|AM92XN}MvjGzQ1#mlm$~gFKdUqIdEDxbTB~5`
zUr=INj@pA5)+p1Et;WI7B$Bga7n}Uc2YXr|5}6?t(d4SC80o$&qd(B|PwK16nBK`u
z-0mwvO0ToLR-?*>tXG%u?kPI{!dIV7Ac&j)<HKFmU7yt~eK_`-HsmcBWevZ|iW9b~
z=+4#1x}uES)}wa$wgfOvl$pb2C7RVSIl+nA5(j8T&p)mw;sG<&i4;mmEBlN!{Yn%Y
zY)e(n<Htn9AkYt~p@RStJx{{4l!-RL4+6nlv2KuPWu(uBl;~0DT{H6H*4)<-vY4-l
zH3N_%4dpTzeygmh#%jFQL?FXMjrLQ9abYxCL!OBWDCGp^VKlVK;<}+9*QcYzf7bK;
znzgJHCwKtb=hL8TnY`-fkZ`3IBUxp+E<_U%O0yOlZNZiF5s*T!#xe3WK7**3K?*MF
zUKBdLbHDgs+vS}Pv6US3mc&~M(DTn=5l}Yvw70$k2x=Aaby+yEsja4#6UMC-h$*a;
zdw1{NojHbUA+JP>P)t;N)J8aTBL=_;#&r2r_8T77{>i{Mm}{S+jG}sec;*4|g;sH7
zyt<^gY2F@wS21bVB7IFHEA;&ot~je0u6QzvHBZOk=j>Mi0D&-HdE$LEHu!JC4L1<?
zaFY@-$9*|Fv|bJxXs`~Aaq=>j7!i7;%9O(G$oNS;j^x^yRD-bwA2#S^F%3SIxG30m
zs=YB$Wohc^a6w)EteWS9V9iV>4qQTHjFT|nku_WSSMd4qaeBA3TPPI#w>M9-hsF?>
zFAm>Ks8%UFhr0=s>TZFHR@xH6MR;_0%}*+N#F@4om7749y~;5wblADZiW}ra_z7_X
zmY9i#AJ>PpI;3aaN!F4&7BoS%i^b=GF!vm9O?^R)wfeTIGu1(W*Hu}a4ueHKI-_5c
zIbkSleC}<HW~_y_hDG8qR2kY@Afu&2<bU=@d7puRtD#ol3j<23ei(S&ja8$^7>URj
zY6}?>n|tVLUO5L<m30*1dmpMU%IHuS1$Yw;jv!Vra6;kyo(zkEqSBjHSKm@%M9OM}
zvI{3w6Nxft@?Z=LGpojfMm6XL#<;o&$IO%A9lCoBfrrXnGnZ!Bv7CHUbk7hC-16vW
z67hiHwXRzm>#Wl7JgfUg^%@dxC{t}G%8bZLwpp$?&+&}Rb>3@5i>!VOA=Fj0F(E)n
zSmocHkpvSAbjhJW2`f7-XQ~45`ut^g!b4r+j#u6l)rl|?^XM6n<ptf<V{qk!Ze|e4
z*E+LJcUCv9NU-9~&^4+=*V{f(5%YEHbI)<k^lge8(UqyGa6sWcMC-HwlCI}lkm9c1
zyE+D04Fd{pdQ)5zn_%$~K-xq!6Q0r|{F|UJGqEO5;kMYA!a;R1<Ix&UO9LAM)|k*s
za`+*2C@dkBJ9;mnI*%hS)o!$*T}v*?`r}At%6k2&pOF50|KY>$$&T5FHE?kvJ0AH=
ztBkG=;;M}?b};gShOrW=I_?2aAaaUK>{T6%?xGNY9ygeHF{0&oI1-P<qg(N$s>`Ec
z2P(cTI~?`AS2^d+^r>HSt_r&f%g8Y~92qZKH`q8pxTd4sA(~Nsm<LGbP2G~AvuY&A
zqDE?TsJwOJgD1;X!b~R8M8A!B0pyjb0B4FrYW<a{{~>G@LvXyY#h&IpN!L481{QOs
zc9f3eakk|ZF(yu`*>|epDK&p0e8>2vhhSrLp}VKeiUjY(aPt6<#lco}tLj{c>?_gy
zay)cPtLV~1Y>Po09hPtc@oaO-YAA6&S7RA2#q$?55VEF15+%mMxBTyY;SOK0&7ECc
z&@*R(NEk+NI*3ERZlera#tz<+?v}KJjw<9nS=o(~ST!EBJS4`{2qW}Fm7A7T+0=<K
zCK>)#vnY#HUi*MseMOv;gE!DdYVbxC46u^R%x4-nFJ@&X@=<cd0mipd+KvNA4$&FN
zNAF4bRXS%_6sb@_31b4s(M!T{Lt77nm~-29-?EAF%b-E2$q<-v$aoyVHebCK<=(T}
zTw_%{FN&3nUPm#r5;j!z1`IYlBkMMm8?>=MOvm!ZqQnOb0lvoNI@ky1ppKV=XK^SD
z1TSx0e&n!JK05?DMzFCcYAK^bj22PXSrm&=++fJsKyac#cYovtLCK7f-@}_=VPgcr
zFm4Zu03hjvdORMS(a170o%9%5_F=WR_IQ;wMYn|~DzB*X;)af*5slS^N`-sz+LHN4
zW0}jCn!4gT{h-zn_O*_6fUSIQ?&cG(cD1{SZ5yKjl}1O52)6@WX~!6vtq5tHz>DM-
zcg#yNe_Fzm)k#sFe==%mAj5<BWJ4U~J`tZ#SJ5{T_QSpC3!I?n%sZRnaS>xGO-o6Y
z81=a1EC98r3_vxa4Sl!$OUK!<4rEBm_p<gHwqAt5xqEZHZ~2A74}Wpva8+Rv8v^?$
zDcz0+X%5LO1{oq&VV<jY6<lRY?3j?OWhx9C?7K5ABn0$zGWgrFIt?E1uFz}a;o#%(
zkO|}Jsyqt06r2iA%!AK6PVmrlV?a%?B%cvisuLJ;v5g5W<gTlcYuMUkCv5x00*MyG
zvWaXEZS)Bmn+1Cl0ruJj6HPMR=rFFC4Z&8m3j&bC1nXMJmAsAk-KH<pHLDNTBphK`
z4Yla=gm||qPh*(r({UWmo8cMCf!P~rFvTpN6SZj>pk}HU#HK+5M>j#Q2K4+v#Uj9^
zF=Vb8UI4{yO1g^#4wqz?-qO18!aa%c_K8<Nd?~uL(}m#Zy^i=*yH|!VH)TbKE_&t$
z24`hjm|7b1Dqh-_Vys=`DrLqA<mQQ~D|)E$iPuK-yxc&5HKd8sC80Xg<31A>oj$I9
z0LQ<$#whuY)~?5_IJC&<3`>bjM0`1{tD17!(oh#yZByM)(kQrjoQa?B=(oS~yZdt0
z0(KBKMH1-b1I9001Ab70o0tu&Rpc&_QIy=?7rsiK)ixtbV+`QasX=#Bv_m0Y)%6pS
z-EQC6irXg2WMq-c-jF1~-`66-D2nhAc86F}XlK#*vdG;M;YoQ&`y;Y}-DJpYF5sm`
zTM{T^`;nqb7;Z6T+Bm7N@VUQ9QwJJ7j`fCRfpOfEg^yZdjWs8{%4!S+?W#ngfem#+
zb;gQD1y!+Y$7F3uP^5a*tjuWsgmNb%csGgXQ|1(_c&hS);S1tiaJhxK(XK8=gW}1E
z_*cw&15q3@zCV`{O<u(f+f|GQf=m5|aV6RbfOhMf=}yvwAu6e>5{Zkgvndcb)g|mz
zlmh{&ep?4;brNHyK?4Rd3^}GjbM#vEgovWcu^0iIAwUw(fQ!v{{0)Nn{6qHwK6ylT
z$Ml47-Hm9Z3b8KtT%$_Xq9(7%T%bwGl|k-;=B%n=gx4`Wi}Xc45M}Ot`;AtY1b@Jp
zGZyiWS!*7cio`yutkUCZg;4g41im*og8^WTDk~J88^W}M7OM&-oDf8IsspM#F2=$D
z{(V=4<xvD0X~sqZ4_Ed)zh~<BpA2t~A87sA32|Orh*qO9QGHWsc@1~`f&!8?xAX5d
zl?n01@L*!7RV$myodIP)um&9R=6~&XKlGyv6@0wpLlwiq!_)FI5;%i5Mxd4t7%$62
z^r1^WQ_GlcHUN&zihD;(d2(X}!W{~S9)e`I(<aizN_xsey8*9_wyG1=R}=`O8c~(V
zm@pz7V5$BXPmo%%8lg2I$h?+`leD<ptI0w!)OP<)SG6Z`ooAn*HX*{zSjUfK2@06_
zURZftUKB(W#83tpAM4K`J^4ZlDFTB$iMT~vn`ra!QZy=_R2d>F<%k}1#DgKRd%RVg
za*uC{DenqyHqppelsYOFRfyoj@It7OsMhi7Ix={b@bNmxv98&TSl5`Y*+>1;N9~^s
z<SPftz@+Ph2`U>Trm*nPmyq^pLt5Cuhq_?jXk$=GRb7oInAPx2y%fK;F&Qt0uWGul
z39P&q$S<N}KQL9fASOY5$OREY)66t(mE4N2Rb9gAgxt(UU^TfKFe71FW3n%Z%Rmzg
z2&T7uypO_4;hTT)!5@$17gl<REL$*gZA&^V)mBvoT60#XbZmHmPFuZBYY189fQ`sD
zVX{rQ@J;bdWXztS%sw?DaYxl{3KQl<__n4nBp!$kIeo2ax$$My!-}4kizb?nb!+rX
z!tq8OZGXYU{E1ML1fpQ^d2P>|go#U!zZXkQ3@@eZ(N-LQWXh^NA>CYy?YJFlCuQj1
zd6MEsqsXHWco^q%MxDm}9J-+|C`s_jxO9nP!){D43?lhxwDnfiyZj{8h!^-^9UTGA
zPP7!fHEA;;?YegR`-wW5kp8A3?;?O-2uc%7Eu>EW`G?;Zl!jb*&6xEK#6x>yJ=2W5
znjIijncPG)$ll$pA&*e19*gDZQiPAbjHfSA%Zk5Q7)VkIlYriMmCW(X@nEUd49Cr|
zQ0{B-s8Q20FOy&i@{v}VMWlSV4$`~cQcPpe(7==>`}ZEXn{g!Q4iXRb4_l7K1VXrt
ztdbU~F{qs+oNsIiT9X!&;pxgXu_0LY;`PYhn2hFU;t7;5rh`GF6okY`z-BZYt)_(@
z1(jSBq=d2M<}~75)m?1jtNayqD9O{&xr9)G_`UTR<&En#wuR0hDp*-xA%Xhlryn7>
zZ=(D3*LUv3AY@c}ZGBa)kzsA?hFSIOaOB^^6$h+g90?N%w1NV<LskMd;{pKZd`Y29
zI{`t1RZV%vy-lz0R!b2xctuTDD-QP|<w#Umf|NwD-WQJM14yXGY85)b8<^!4o4{&-
zA$Rki{8#iKq2{)U7Ojo;LoRIKP2nslYUCJ?*H{AFXbf7+bg{M=HQa|pV^eR2M`Jyr
z34u)LSYgT;TMPBt@(g{jeQz2^vvPtMcGSq2Xh6dh`g6BplVe1aC>^tIV9H8cuQA!x
zD=~t<e^a|K&eJpXvnIa(Zyq}=x;mLA5H?Q=iRF>^)zsFyax++MwFDGONcj<j0EAvt
z;}Pr?8C`-SGUT{9$F)nCDz{<8<Jhmyi}eRhrwFkl5!4vHHSuWXyTSL6WAbv7b(4p^
z8Ze}bVF;?q<iU^VB`I%3-GuZpTMf76oz7TXV2@V34y-JzI}XuNs>XDTY{txGtok!5
zkA6GF(o@Pv;*OchS_a3-81K-?zPOTDWg5{3JxDP&xCS!;^GTU>qTvD!%;{te2WP)x
z5Q5ai^oNH;4>@~WCNrmyM8bqzYY>D@8pSHfH0%H#G_9Fzh({!ZyDr#NJBB@^&qpLK
ziOZP9WavoDRC=kl7qQob3#R0vL(~%h0o-O3s{{>eT$KPmG_gwB-JV<n6vKHT8PXVg
zx`ar?M)+So^CM~KA!IUMWyfgfwBia-7^zMTU1)!`vxbdEVBRVl3giU)3bM^l>iJlY
z#_%1+1pZXw_2tbHW(q9Hj)ZnJwy_wkYurAGMW*%ZxLnhiU50?>GLn$JzrnnHN-O3e
zbY0?>ptCn0{NwlKHR0t0nk1|bFo1`+!MJ3#zuz!{{Uaeb=lB_9Ao98r!+OhVP|e6e
z9fwibq`z`?fIkn$J05HaPQ_W3FezH7MV7}BEPIUJg>Gkx4e?A5iBh|U2e578JjY#V
z=^7@!_22z(@26iaBW2@)0;;Xts3MWf^lHuGy$!*ltI-j9QZPe{5wY<Lz-(x}YK(Xm
zxNs(kgyI;^2WpvGe=N#XO+!&|N{LrvEDHEBS!0IxI#+1yc6@b^{I)usWSE?781Oaq
z&0BX2y)Q3}SFEP;n&CP&bpL9#+HaN)ml1!)>iG=8&`f1hZpqE+lac5#LQmclbc;oZ
zJT*>Ihk|C>P|JTpO4GU;yAor3ZW!!nEUf016h{{ILp%epnyZ0ZUNHg>=2Po7Q*CIg
zZXW;Kdz3R{K~>`$tFbr%AX?QyZ4$&9uA$zx;6rpnzUn~K+#vrVYCIV|uIuF1fh0sm
z;OieHh9#3GtC@I0>=+Bz32{mJx{^;~>xzU|j1=umZN<$HCSI3YI+98q(@noOA>Zfj
z`LS%KLSgrF>_tR|vr1NFynY@BqyN0ZjC+rS1pUnl@+vn(4ig~uMz0Cm1fSyYP$;l@
z68_sxzL{zky(_I+yNbDZLo)s~YH}L5C1E{7Js#wcZ>5{i1h*%GgxJ+v$sC)>f9==r
zq~H=RPoiOsN<gt!G6=|uU3GGiSRYWqAPe}tOeP>6YQ`{6AUb1eTzF$@{YkkRCQ3NM
zc`*2=QNc!cBo?rGNX2X8Vjg5og%s}C(ym?I_Ro#(wF0F4T4gI-6&!>G?22@Gx?MNx
z_e-Zf{9Za3f*I`#$$>xCFk!q3U`%WxZpPEKKtc?&bcC}5EsXD2bxuT2n*1##t_t$2
zu4CH5iGv9dm7!urPI-OjRO3aGXD38|zp}^08aXDDagbPpMrWACi=J%&)fmRdm~~Ve
zOD1TTc3%J7U3AT`snO_=&lnN`62aVnvM~lvu4&rgq9rM>3)dvfo>!zAODt%Zn?(uR
zV>&X1d^+K*4ETbxC3mcish99-WktIKYG_*KlQr=^D^;x_|APjLSP@GgXTx2olWKBq
zSJw`*zGl0rxaFprWezZ5fz(K(0~y66!}q46O<gvdb--^Et=92cT4J8iT@;O(sH5x9
zEV&yEa!*H*9Lb`TMW$i6(wdgzs`1XI3f5R6I#bbYoo{P4T%c`@kVMJ01Oqf2?6Sex
z>35l|noIB``-y*K<47gkXDGwMz~#LF4cAH1Uafk3ARzzbX{?rncKHm`)u3C41)81H
zHP;$jl3W<<J7&~ig+&r$snre&-BJ)l48AEgq6wLq1zIgP?9q-iF`eSdAoGlFj~h#p
znnIm$Ue@~5gC8zuzfC$cTQX9963(maE@VJKl*aOM@kh=_ky>M}t_k;qQtWBMAu*eF
z05+P~iNQR)7D2&Hxr@OQIDK8@ss}apqwm+V38IbYpP3@`vHmZSdFz|ieq4-J)P$+#
z4~CSU>5$K2JtkjKMJI|EYkJMN#oUqa<^;#=YxjJ>1YpeSH8(S~R#;vKRackEQPSQh
z6GC$FJwfM|JPhi2*98Ib^MsJ?F?l5%B$ykP4Kj&=FrtlUV~<R-cs)yajSIqk9M^mz
z(pR-(j1xVyq%dW-IhyCXp^Ktg8`oWU2%4{Eowb`!{ml>Ww#uEPSpN4JIKc=Q=B8N<
z8k>^&kyxf3kDzR(IAK9wsVKtw-;$x*mbm%@A~-BC?`3S#9l#{mszN)2Vg5uM6vQYY
z$Qs$R*tsFY)flF`L<bEv^hhY!AGX3Z4<T(ZoFLE^X*|1MKznp2f;yk7DI+tC@XNJA
zy{1iMv89DB=f?EY@40e@e$pByvuO+1(S{l05p_}wy#g`iF7YH`@se%OGvc3^e--C>
zQ93A$F@U#>4UxM>cD$I-CZ}v7-d1ol%5V_*?NB3V)ciGlLr<dIp<{k8Y*_f=JOA;p
z>@qgsK+cD>95ZOBX^3g;W701SKdx3AGy`vF7GOsoV+}ssgtWm}Ty0_9jfEAnz}Cow
z)?)q@%$j*D5Q@N|DS&{@ihk@1qVjTUQ?%m2aI?y0A+>IRtWzPYZU(w>N%LS<P)n^D
zYkD1Pniq7e=M%+Z^7wBa|HUtnX1%|M1)c~;KH_<7j{%c0{^UgUO*{$UgTd;P>MDUZ
zaCGqovU#c8S?!n+uyZR45bz9<T?SXeQ*18yvOK|tq)B~JpO%x+s}#r9bJz3{eaf9R
zL48&~^0!6s#+a8T6@k4-@>KPt{sTU8O3x+nCG(-qmvLoT+2(3#BMc;gNKFpympjkU
z*YrSck%ScUkIzi}52>MddU`nCz3@bi!*sU6ppP8+49~>~yP9AkhcKllfXSx$O%4)D
z=LBfZp`}3+QZVZ^d&E0}#o{mnLXhMuBL;CRG#&hM_+|Y}7@fS`!)uyD+W|SHH{%^Y
z=ke!@W8OE^zR0_>aaz42<JS}vVaG-I9kRl1e~Qs{qQ9iD1VP1poTMB6g$#j~L10eS
z$pbO}u6;8zbW{vt*>Pc85;fQaKE**6h)xVR#`Frb{466$W=_5#PV{Vh_!RIl^R%c;
zqEq9BnBI7mF&HxIcf;^hSl`ko!i3VNTt=96Ned9HUc<Z(5gu|jtL=E>oec>7PORtN
zjG@8YfL5J(O+JW{=4QS!HM6*bI1aBOiLSCjcn;IE{4CScna<D6-u<1U;!>Vs8hA_D
zUXwm9dNHTqwj|4Aq6%7dh;cm>jRU?ia5JO?-bj!o=7tH9a@a8&*&-}i@b`B)$Wk$?
z@N|4aPlkVBf|MQZF;u1^QPG(3$Ipr5&tD$AB98B<(s~TDs&}j5>11vUK?uXq=T1k>
z<nWn<^D-tdA=ht&@5FrMM0}0=uJP}JhIo8}!JWw6diGO90TU~O&*5cd#OMiR_=$+*
zX4!ub3WZ3uv!)J+xwyxxWSSadP|dgGq4@XZDe<cOZd=dw!05)xB>|?GbfU$K;BlC=
z#Vz36^U?VjwmMlQIB;!aK%JD;PU>#rE@W!1Ho3N;H#`7Y)=>y`YEPTw)_tG;(ykt-
z+hu#Io2ogEVwSPaDnRJ3qmT|o>wrn9!$uBpM<r-9O4I0Tv-;FLYBe%9mlvd7AjEJ|
zF6i%`(9`nUxlSx)z_n@_(~Dr$5e;`$4Ke6bvOc*XPR9dkHV(fHD9(jAt6^ByTvxZS
z*Q)EU$X2wVW|#GXCQ(4m{*npJ+=?&U)}5xe*jwY#I?s;}8T%q!67oH(5^0(tgoWi<
zGx*G^L<P>~PQ*+4((JXWzJSxpRb)9JU76P#(yq2N*puRz$~ZWwFHu=}8KG>hjuI4v
zcr@wTp*pYCGrEp&CnW<2=ZAxj9<G)LlkKcYehCF|HwjftNP}fR1M|LuYOkuCT2{fR
z0q=}%XTx#ps1dRi9C>WAo&*Rnl6BR1|3~F11rNSMynMDpBY!qsbo*4xshtx|hz{nw
z34ppNza$5$r^2~|d?EL{I;2nJWU>yiA4t}%trAa*s9dNyL)B-QvuF)T|IKHU!XJzh
zPapkf;=2=a3Ewywz{a3*jgAhohGEP_R-mX%i_1%D@JZZ?^?~TSo8oBo56sr(NR7@&
zT7plRPD8fqf@3Lh6_GfjTk*jvi%g&?7j*eGiFu#2hz77~Y|29`&8UUyf|z}UN`sgM
z#<u=vpMtjKd@7G=$0|8uR2f}6q+Z9&0I$QGhyzT;ps`I@>^cLfn1{3K+G@zCE9sn9
z4@JY`s=O7dZ(pn4(h8j(Zo|!fo^W3xvYr<eGRf^S#2pj|qtkHttLQC++-XS#EFBnT
zodcKJ7I8+UR@xe*0BdEv1rVc|EqK<@H;E;Fvv{Z3(rX54BsCc~q7}j!aXA><Sa-nC
zzys-iLJ8QB7KJx@0ZDNcgm!R1U0M*|y%0{yS$h8aNscCRz{m?EMhwPlS|cmEdYK2F
zkW1nG`DDI2q~#{^0*sqeAuZ&*JTD)L7xe4}W^}g0yB7uyi}K*Zl=Mk<+!5!Wa|$f3
zHugBG-+XH#(*4W8D;SF;T^mEiFfV5sXFM@X6rp-BA`Y=tJsA6QSF0D$i^?DRG3jY{
zD4cdZcQ|q&@r8&DbI~A&gb4L&{QLT~I5!Z^_Zy38(!{NihFDfQZwEDeVAJsnQ1ld}
zoqY=hpQw*(a~WcjD`YV!Wz~GOauf=)nj7{yqGsJ}F@UtVFWtR+sZ>BknOZ7~*V2q|
zGe8Frp`acEij56J;yf_#AZ8w}u*)|6ntEQa)*h4V>&B9$zwPh}yAMqWC75?u5bqKA
z|77j`gX1{QJii9il3QN-7MP5g7Q&MU;}+e*V!f2Zy2Uz77BkZXUksY0#n35~;)`V#
z&o#^FB70AF;cj%b(~TG4i$)WaSj-02Dc%8g#2xYwS#oi6^oF-4p%L90V`*zw$+8k(
zEcsYlu!<K;UgyHS_}2M6J)oqmbE@)3njk3=jh?rk_xbsKe!OT8VV*R`9RySG#|hZ*
z;kkt~lNoIF>W3H`V-bc?wel#1LgEaAwXsH)OGww&7<|)OiJ88NLrs}s`_aebJwhY8
z9r$)xViRNy17b@9&0)2TdI0x&=Z^y!#A|wHdHMJT;eo~}f)i(S5GS;%zAt337FUWP
zV4>((9BbCNl0@j<PkE(?qVwSucZd^{h&^dK(%P;Yr>@ttxaaNI5VwSKY9`L&dk-|*
zm8$HKRL{zaLSS&#c`#78h%mzhu17#}xKGWJUhv9x^)D{9_jPXsHBKC<nZ5W?l<IJ2
zADcmK!1@HZMB|%ep7LN4Ix^2LVerkv;)GpgY?mu^96mzEmnfC+Rrie7RxzA{7?CEU
z4~h;SlF^SzmwCOb_n#xnKD`gBJw^0kZm<?MT*^Dx!ZPQVQLBWjdqQ6iW)>RQ)bZ~H
zw}UptlqN_V5NhY{0&}77_9U{yL`gu}F<cDO#le3k{)cxpDWHL>z8Q>DU4629DF79!
z6*YC4!i$UOe$fUZJi<5LW|s<p&gP+D|6a4Cm-MT9^=Ta+P(r-E#pkxB4On$4NY^vG
zpzgPW)7erw|9narWZ3TjdoOSgHWJ8(Iyz*qp3x$ODi9?CUide^g(j7G3%Rj}!7SRc
z*t?nTVf;n5FBT52m>Kg@(W%{!^CBT~b5xi+Xz2r?Y}l3HX$dqks5z?^QKQjo<YmM{
z<=PGt)dEAR*5kHUt?g=OL{S)?eQ44<nf?>R7Z>v~#p(Wgl8!XwpTM6`HtgkJnA*$u
zQ{t<bEz`GXcmC*i?pl9IRFQYsuK|?0zy%b8rM|QB9QJ~%X<O2Rb5N4#ghhJ#a(YyK
z+r0Wz`V*8tsLfr<@)(r?*G*`NS>8<dWvA1*lQ_V8NlryF=!i=cEmuacp)!@FF6(kH
z8x+0qAI6fud*pZVqV^UsPn?X1eazig67@Ph*nLS~0nD%OsKhnjwQDjGQHa_)iV`T<
zVD_29nAIl2>|4RBm-ys!c&i68@rv%!vou&$KDdo_FvyZDm|mA)2V1}Erx1q?Sa_e5
zIA$=VmC%KaXwR7|*#s2lloqqJm`<$Z_WonNyIfkrfvVdffiSxtKmy6T6Ks-fHopA2
zU)&VX0?kv~RE0sOimB0Ju&n32r#2zxL4B=-%Yl4g^07)lWw<k2DAby_&c@u{oJeJ{
zrzvdoT*B#mgPJxA71jsmtB-rPQ`d!>Vv+b{?s)O$2TVSP@!*#n(lzP(7IYfUTkqCr
zh`=v(l1>y0s|rnrTOWmonmqZCIDDufEYr9+Q!^M&N`OBXo>62H!@IsIHi<_ItJYJB
zBD&IuFk?ddboknAO0bGqI;{_;@7a9OICq(~lhv_HfIFD}D-c*LQ?#&c^Pl|Uefby<
zsFx#*NW`I_!n)0YfIjxPhJAGyKG<h45U3W*20fV#u2btglfH6Py>dCdiG;mEWwhwW
zZQs96p|RcbS9BGFbUVC~9nI!`N)W1FnLufXX%>c+AO%985UnIb3uO5Fi?FQU=huJv
z#FvWO{3`KDtAaxp`jEDV$H6Y|4W{jC1qfP#4r~&XRU`M}#or3(3eeOcau1t(CDbR=
zOGv}4n!lu_#VKdmd6$@xDK`?(gqQV7kWtgpYj4J<#gQ`5Y5r)qgfCUwW^%Fi+l>HZ
ztLSVEQA2ZWRN>+T%sXM`IOgur-2Xq*%ZDmS-ZaAh2cKYS2kYvj2k}yZLtT<7-wphU
zbIIL)DAs<Y6)3BkI5&dcNm=-&2aWl38A`&RLfssQ^npkLR9eSMYa;7>9o8Ksn)Vd6
z?_jxU97lJH>h3av$ubNh^Q$~uDw-3Si|j=2TuO(EMQ>myIE}%WV)P%&gOv^Bod7RA
z5Y*jUtW#q^W>$jQa9hgnq^_e-A6>1K>~PmD<<lFeXUugQyu4%RpUIu;NmKQS%Ey5F
z>I?1T<+1bK6BpGFte*0pH@y|}U8?`hf`hC(xu2TzLe96k1m=ekx1z-L!Qb&nzV^Vq
zHJLLdeV_$ZAWNk+>allQwKoq2y-ONjwPvKNbmYAbGboRKHKi?@crgn5udvD+0&`;&
zLYV^A>;tAg?F4vGRkH>q>v}Udq)=SXL(F)AB|=LmB?8jFJkv(W*4H<e0&)r(v&y7J
zx#!gn5n8=Z%Mp*HAc||<<fJqQy9s5>T~M-)jIdY`Kkjb%Tqy#}q7GE7)jFE#a(8dH
zavJr3f6d}4k-*>6lQ})9LBjbjuN|wm*OJa5L|tvn1apK#2H`e~;J@gNeEZ>6EIgrw
z+29ZI^_Pg*BNK7LA4#sElmC|xH3$EMtV|Zj)skH^{w)TDP$MuM&@8}WjSR!@Z@f?y
zrvXRX)my~$?evDBz6*UpJ0!KJ2X%$WV;hTxv~{~&T8rZ*!0~2s8^2ZRu~TDGXc~c~
zK-fNu+Ti50-l3`Heu6uMUhgnElUweb+`FgvK4nX*6(BKOK7U6~tSS}Z6WtI`2^O7h
zDDnt*sY>qv^=PaB>6YY-IDFmut?*KI2@<Jky#K@WTX@c-v)hRTY&oHKGn-@V2f<eL
zZPhq*BiIkpN3@VtBLuu7ic`PGu>EC=hO`jFzVE-Tu?>+q`y34#rQtij`qz7k0y^f^
z9XO)7*S`mUcPsEn9tG2crNR&7ThGRl<;;7|P;=B|*QMhYCn~6Ih3YceH72MbM!cjY
z+V}IOohHInZB3Qdx-&^;YJ0o!vYJ5?d>cc?&HMCgWHT6<E9M?%fE&<QiFp5%JS>F_
zTo}i*P6kROP2TythlloZ4*TN~#VZ^S0{b4RV*2caCIm$1aJWOJ3RR~i34=?z-3F7Z
zf`?Ws6tAP1Vetc@=!8q%a~a;XE4lO#ws?<w$Mk*vSo>Ig{bF*tJ)U-go_86pT=Y*u
zU!u|XxwqtLZCe{j2OKzeWS3Az2qgPlpn4_R{Ltd+uv?gC7zj-na-6i32xu%MG+H-U
z)|z8N(OuE#Dqft-(UrTHkrGf`K}*6d<s|B+Q2>gei+M`a=M1_C7r~c=Pd)b5fY!^&
zZG<ve&(iQFnfgD$(jGK;eaaSaTO4F~K$@~ibaUTrbH(U$QhWfg$MK-0=?;e)e*QoF
zTfubnW!F_SIjqRoN2baYX=?zdF&*^6#taqL8AU~YCN1^J{e@=4OG(>Cl~Gmf#I0c5
z&>6jOJRpKiyW##P)G}PTlD>L8*Q5027JO8ZCmPpVE1y^&zX)@oAi%6iARL!P-_*0g
zLc>5bEj5+fvL~$Et-{0`WIVD&+i8O*tBx7EL+=jlBkzv?*Bq3<f^cA@rcWAQ+J+LJ
zbNbBy*U@HE;^wM3E8m93JXbaCNr_#io%k@lJG1&!_dxeMCezpO$cZ6fViLJ!N>?S<
zHwFd04j}oBV7a@w9?U-xEE4<xD%ySLqr@lTEuwrg)bz4i6xfZfku%u!U*i)wt?$8~
zO`a=$=>sHokJMqz5<0rwy`k$9__yJ@o@Ncy%&p|iz<Nve2->8JB3TX&hgtXfEoCkT
z07sWJ0D+lvv-Dd=Y9up1DmMp@G0Ul49s9x5ZFQoa5dL*G59-H*g<J6Nw@uA`Lo-$f
zLxsr@q08#B161kog}-1@f7YPq=I#>q-5-8{u$UhYCzcJ%x;>g-8;Z_k5}dd=_m9vu
zkkb|+CM0?j4<T7cohfi<)CBR$feihR{t3iYKt+^dyMEs>bm?9gfGkyy#_BiBI+02P
zm&wU*%FUWxYU`?zSgd!;tSd`1Hs4)Zj0>${_nl`yJ;`~IFbix8v)_B93BSW6zz1Ck
ztE)9<f$nIqfqdgxBclbtxi59iL?GpR-Q1{sCXfdG8rJNv!kFbY)i2#wvd7kf<hd^L
z6=c0mIOVMy0&2Xjm}YrVTzRYjNqS88z=}~_MNuL-U&mPDIsEOvM-ZK(RsepeRA|$~
zDg_m!e4_;As4vL55{i&gfQhbvT#jF1o<<FyJM;-GgXt~R0Fvz!4Qb{v9+~BA!P_F@
zT@LF%Q33^Gp(MX27l;BE>p`2=*E6+@)a;OOWK@a;-r4=NNqdq+p+WgSW=nRQ(iYR>
zcF$;gBXL5>@5(Oa3@GhQEfe0M!AXD-!3xbrB@v%GHWm52W{eYAZS9`A74~%9cvrfV
zEOoVLw+THBTTvS(JSUq&XjSbwn0p+(6fuoy`~kbulg^okJ~IDC@N$t;k2y7rKV7DG
z7L@zg3;TItO5rI=BEINkH#DJk(AF~O6F_ZQhcBN)8=+=_H0TrI58ht--44k3HGGid
z`5?Wc(pMU4^Q3v&1hys<p-=lu<#KbaJZ9JR+OZQ|J+pqe{vzJxAqJ4CiQrIrri;6}
zY`$e)aTxm<$!|;Iu3RN0k{5@`W%Sh<jq1<HG0m9^4{+8C%Kw|c{c~TZ{sOR+)@@yv
z8Y>Bx$OP`~qCpj#U8CKNWZ=vL1$h-_n~u_7|Is7x4PP-f>!kK1%G9+d^tXt|Chw%_
zl3Dm0??bt7pz74F*W2TVt1oVFs&BVGzQwV&;Kln<8vH;J_;~wu@<-<%(Czu+h>eeX
z@<J2lO+%ouXjZph=tocg;?LP1L6J(fNw&!Lo$I0$NHPU=KpTkyC*KIZQG9=EnyVjW
zXRhLgQQk)Q(A}tQreyvu>DlhQpsAI=u`kEi#kJkX4t2we<=Sr&prjoYZ$6#vW6Qhq
zSGfPZO@Za{rkm(e>30bZWv9}J{g8NaMOX=jdiT$#KBEp6XNLRR!=Jfj&dF<|x3|cA
z>1q20Om>Nc$K$-nWes+C6PEnoD?EBcrY^9A!$E*kLI26-$@FvKjAZY=ZTd^PX}<24
z2gzTa4_e;X?(@NnH+C_RBG+yPNRoZaTuao`>1Afb<Zmo_v6gJHh%JaK$QUq1+RaWu
ze-ec5dtCLgvjab86IA_$&*FAcv62Q<1az_mLCc&t{~v>a``{}eAZ&v|K=uVQSppbB
zB{}chHQ&**szya;`W=PresC|2m4!pjfANG~@h-l2qdD$()FE?5yHqj?k>mKi_rT4u
zsb8hog?m)OLE^5Ti7W8_P8|8h&)ta^K09J7WrROwy5>grU@)!6j{_&v{4Io|_yMVi
z+Qr9K_Y=rZ9feS|<?7p#t<_I$-b6%>cE#|{2044&-HYA3?Z#MnciS8LKMp-X@ey$c
ziQz@wQ*Qo%d?TG2GY3MszKP%9Z|ReY8&ZTJy30&o{v-S6Y(wkl$mqSIt2RQis59Zl
za(90bm7fVv$|?_@n;Cvju*qAEJTz}l;^!R}(Z`JqmUYt2=ASn9!Sp-X$&?`MgPTw;
zV=mWrpWulXk6q;K7>xEIL&)N6vNnJ;byujdOWR_dCV~ZMJnIeFugeB@I>m;$&uvS^
zr(XCudjWYz9*XQ{ia66I(_vxk31ZDinHgh(!|EF!(73JQh=9abgJ60yxPB{;*r2x6
zeQNXhR9b9by%_?|<!gIyF9ubE$%xIhwPPEZ>Wy<V`~f_G=ERJ>&r5^_fEqrw!Z(<8
zPZl4=3pWiCu`S4d@Q*CLlR2M-h@qs55tBO^oz{PQ?eSAVg0A(ozYde;8KQ!WAQ-^b
zq9zqCS7m_~Y{nci3J<k>82;&slN*GR#;_Pk67N3m)iDr^oxG@he89lquJziQMH$?I
zZ67eVZKxohU-J3*HL~u0fz>;!7l$}ili8SGCIDtUE*)aSt<U0p1q#z0h_B|iLnT(c
z1WG^wRz4|#rVxN&kgx7xJOk<BS5zdhT*AteR4d@DqJ;M6ll`oc40!O5RsFGe?bs)8
zjdiMT;{dRhPMF~vh*y$dXqhTrP=ZUFr0W91%W6CLa`;IcJM<&-3z6$CzU;nkWVIZ&
zOtaMp@&?r~!~_yOO-hN_5Ld@^RzSCy2`#^>bz72eo~C{daIp<AyCZP|o-Lk2bI_O0
zRtg3vT%TedEia9*^iu7Rpx{yBb4bk6-#)$tS$b5Swc&!6F+8T3mxuqX_L0exbX3hT
z?3eRa30NM}?Ml;@TQc!x{c-VkD66OS`7R}+h>%TXgu|hsc59qcYCbV01jtuLP_<UA
zx4m-fSOyjZ*Wk-*Ro!^+rhIW=-8tRbdL!R{-#BdY!*uivf9=Qja;n?Ac~F9R(NQxZ
zRW*=Tycpb9vT3QW$9F*Gn4c9c%&EpaGrOdpK&ns!i6{1bb0(~cB17<&bs!8z7t&Zc
z-VMyksM)de@rgCVzNtDjV0BIB4L)a|51YiLn8QR+)s6bP%2^QNkx1hc-yM0-3MNej
z-%qlSg6ZWk*m~A$cZoCNdLuwnO?nNr{kZl~Ma)mLi`h@wtgEZ_mEcfNdtM(l>Q;t-
z2U;V7LR3|ih@6EefXcew7nIVRrwl+E{-$hfj#%fawae%A&}96{1E~2jq(5ApzPqdX
z{`h@lU-UFnE|AWNZk-l5vJAop+nh}9p?M1vO_-4Yqkt}+;V-Jq)VDIJKa#pM{P~FG
zvG=gN87Ha92AFT_MJI+wXpj(`hwp(vz=Oyi*~h&K=+u;edjZt>{*(XkUceqHLt{K+
zKAuHp6<CLKeM=d#BWX3kiDX$d^Rm7$JWcFRKpOEiy87r5yf~~o<<C9Z8tYUR*KLV6
zto#phdt+y%$E+dP*$Hp=+VwGitryo#BTeioZ!4m~5+&XceUVqsFw`Vn7x5)5=5>aA
z-0Q;ct=<!a*IYM68!M*2x~>doqQk98YA?AJNRe+G^4cgR0wT%eHf^4$Sl##z0s!)_
zXtpWzus+BF@$dDd5JosQ)}E)!p!}aq*U~zU7QcfVGDc+Cl<;GyQDlqdZpmm8s;9z)
znM(NwCpO6{%hBnxKOLexZWo8OiRki1QmiC#Fz@Be0G0-Hi3a#4mneB4_UXXB_uo~9
zf>~N60sjtmK}e(=^I%Zvek(gg%IVcNLUk*jPQp<t=)tl0{8Y0XpWl7r#ZQi*6=1Xu
z#Mmo7)ohw_%$<((Je5hZ{amdSwv|vAf{^w5oH=b48}I|enm8Zs%kG^&HbX}>(^zOz
zXX(-u1u9wLU7H=PrYR%BL%ke$Tfr_O39}$=y=ULk;{)|kRA(y)s>yg8ZQoVXntFuv
zTiKta`=8c7(ZZ-al$CRIS!1jn2oP01vAey+o~OpjzMWFY0v<F05|rm&a&n6%7izC(
zfM!B_5dK+n#%vi3(S>2?{H*&=+ZGcm9(0$6ciuE|=vi|$sL!(;veK!cj{Q;>?}_ed
z!eS<+6H^5<OjEq8o&eJyBED1AB>#{aWm|_f&tR%gBO1oto6}J#Kd1QuPXz(KuRfT(
zXcX-=3?;iFX8oj5c^6@>2xOsh#fc_3LvA*vE@xB%;$i8yPjI?A|M)|d{U>)ds6Z?L
z+CB^aND^Q_5D&EhApg=vp#58cub_1$bUnmv09({tt;`Z<RI8bpQ8UI6wrABWnj_8k
zDl?>l1}va~(x7&3Fslt8yYv@how1o4_3?Jt1Cf!tK~xQmI<Rk^l7UC$p`s$N44H{H
zs+8EQ;EyD@A54cR%)NE_BUjxty5?HVh)RHdR~+tSCk-}kpaIf41Db2J0bFLq)Avi)
zRY@$z2(=3B{Sbr!S<~mb2LmeciC;s#pISI3&gwTak*+3EI5_6nR8aHv7e5$Vi|d}B
z`cG)RY!;03CO6?RIx@*mmfF{6tQR$*(qPLVh*#ZZHx(W6?$ST{jM}{BrmMpb%4`c<
zl4kV6(R$>Gkqp!00pbWh(=kM@!OJvBY{4=p5qW|5l6`J>Yv%$?RVLHA$t`ZC2h#mg
z#&^=3Gn<WEcVv(jhAyA5Tf1B3`X3#S*LpnyoI3GCb{%~4B&n%I<4aON&*z<O`J;Kd
zXiSVb4nRmco5CBALAiU5(eBqo3Sp7zJ-9wE?|RvN+5Iv_ok;Tp=rC4yb@(xO7NlV&
zT@IK$4w^FM;g_N`;%Wabqc92#F#y=28|8ABsP9IQ_`yj-L8eLPRtx|wg>|AN@^Vz+
z@blbWZXa)qT`bQe7u(=M?ajya-1mfe=WZf&m>eZq1+^k9F7E*Yh^7XC&8{LfB0Ed`
zGVam?6y8XQ?Z3G3jJy9f#}_>4&b@AiIV^Ud^{D&UYGBm^VU<QO(<K9I5-EH1XM;UD
z8SOk!Vn5K0?ufpZjHZce3>DEE@uAHdO2PsFRcICk3&4X!2J^mfJBetUuzDj|J29P(
zcS4ig(o{6E92!up1z;^1oJkM|P$MB6-X7}?NaZ};mr&6y7i3@u)f)46{`Wr^`d)XH
zvs7gRWD{AFsPq?5wVvLgrWp#iNvg=-)HMb^NH)P3S##eD&u8-y<}{xVXryo|fk39H
z#Tj#LKRh9%|E^)#;`(TP{&*ea_>(VIPpkyJ4!O6vpBSjgP(9~y1LN}psAW8Rx$MMA
zu=Uiw6ZoXLo-g_NtoKLF$Nu;uK}fXltUJ#ZQ3{W}u8XHFYYxp5;S6cuDr?<C7)?@J
zj~d~9(TOx^^9j3{<-WIzcIjr*)WWCT&65mAnZ|$1i#EZ{adn$zo7n%0V{2_caZs|9
zYQgjyI)z6}a?%L9D%7#~MTE>wPYQ}Q;q^n=6w;I6JgqGC7kTHY-y=+O(cie2Fyoh*
zWk)^+PM>{Di@OX4xs25bpV!79m_6U*=JVmjyug{GK1WAwtEFeM+NCZ~^KF8gL+Z3y
zxS0Y7VG(75kMKEKT|CV}NI|1ZRTRx1wRa>Uu%>rhFG{$d_=euszO?3g1_Lxs6#|X<
zo|mabbyE7Q=3tWt7T=0k@R{h{-?=%|{{&_?5czN<IHF;LD1)7XI$Z}fXZf{MMlUB@
z%2%F)cam$Hdu3ZBub>)gN|UI&qHxcM$QN!Zsocn^h;eYups&P(2hH=E7tKbKdwuQQ
z=FSy!2C>1q;D`!$+YlXkYvN*%WoWhp5e%bFoKwv98GSeT?V*VxJw!QBUZ@^Xm_JkR
zWRyutvv#;q_r__hnZQRB0*fGupi`D;ZiiBUe_P!S?L#TElFVV$Y4i$#@U?k#cwXQk
z7y&(~W~>vctT(=o!e1Sq!9dQD)gU8=?vO}J9?6$)<H-BoJ|$tS^Aawp^y|L+&u)HK
zz21GD<Cb4HsPRfBG;n8U>!ZkSS0B=0Bb>SwG{Ug0P|pDwr7iVC^;*BH76X-ExB@cN
ziy`8*wz=L8_cMS7^PbIS^I^k;GExi4x@k82^enpEZ%{@PuN|+)Nm6bLvraYiq0MDc
z-Y1Qb2tJoSaRvL1Dj2U=c`V<J?1nm|PNfS{-c9z&U0yj8$?D&V-irS6H~-aLzrQI_
z0zbVksLT)wRi>E)Od4l}CCU*R+XFV46ee1VJ{i5iHtsL(&6c_gsQ5&+b68ruewh?)
zLpL9MUcof5kT}!gPD@mPszC6J5jD4?KB1Nb$OlH0Q0nu~f4EW_U@9CwJbPS#3vK*T
zpY)+1908i2U?_B!sZi25sXWmtjiUE(e<3??Vz;}Wm#1*9{zL#=s7^|{Jnu9r#dPb(
zUfXLC%^g?fV&_KP?qzE3lH&P<91b40#c6umupnGeg#*Yg(7TPo-m6kk%}qIw#rfDi
zdZlflIvR>?wS{MZ0`+u9(XP0Qfe(_%1rH0+PgHBj%lE@IQ5}c$^)7$p6O+JX1Im{$
zFoLYVdMm?xSd+?uX^$~%xpl1m$q(bj^pIM$gpz^M1a7g`7MbVV=O8?eagJ!o<F^Jx
zHj6$%7T@0U4RXkRZA7RjYvj|rR54xxhcxv@xRFi4-b_8`D@PRY$%7^V<@8E`rqzja
z5Qz13FeTV>&Hbqnh!ac!+km=id2EoxY$^2_^(*En<!SL2TFj7<_r(~?XTn$|q2oH%
zn$bMe#+YQ(X9`l`yT5<Wq;27z^5L`9`T+Wma$gMAX3Q{y%@A0b%;%PZSt7QZ;z%j$
znXPNlPa1k}_HG4EecX&|wg&&7qrLnp3tZ#d3+-do`hA@qX0VzqsZ1cP)HgD|OZEav
z<=#pM9i!`p=&S{L<PfOk0qp1hYA}BV*|c1$y1@c@gLNuKNK~|yI;_~;L=m)8)Fa~%
zaBDa~$ZkHN!gO8Y8aj>D)Rx{dYRhC01^JW<Ei=`+zVXQ})u~L^;-<8V07=RwpDl)$
z3|FI1U=+fTtj=4mcV*oEAw}$$kJiM`bKd#>!eoF_<q|TBYPS!Bc!mt=3Z>3GuAl5u
z^d!I<ZGt%m_F1qUOiF3_-L4y|AcAXWf}d{cZz&==(i`7W2T5^4AubVU2nD$fAdj4l
z5G)0YcQU~a%o*e3O*;7~Tkd4l!efX(7*~d(T2hO<`lV3w9rGoFInw%@yY8pac6;46
znou2*CWy}Ffl%SqW{AT${j>=ymonf!B1o<d-l$eX92$Iu!{J2GP2K<sc{S5#GJ0r3
zgj{@~?K&6XJ5PJ8nb`&YE$!VQpw0&#B<@KRnmFt^p|?3y?(Zlnn^UuF;?vS<fOU$c
z+Do4K&O+fcoIR6M8}XnqFO+das2eHB5TLN5!lME3kq8Rk+iqil999$4v=ZDv3si7c
z!i6k6X!hSWOu~9z=W4m{14vA)uz9%=a_|6=tc9&qPQk$BO8J1{ZlR#uzwPPbNo7PD
z>nck&)k0>{2CLSmkw4iIZv4*hVDum!ZvPiUh59p`29AiM92};fBru&W9|ht|#f+;(
z4@ihKkn=t3uTCN1wNy?sSSBiZDm|x9>r?dSHq;#PT)zZOlJ>jL<9>cI5X=;W>ZgHb
zNI`Z|si#br9Gann0eq{U2IsTI*=^%EZ}g0xF{Tn5f(V{{P9O^sN8kGz_I*g)4E%Bd
zLh;N8ROwdmhLAm=CV(N(>)nlN;xt$CkwKhE2>wF=Sm9To9!J0KKdyQRX>G#Puc+DJ
z6m^PO4Re{Y{Us6a#)<fR`Na7$mEc}*0|iV9fp)s^QhG~&Z*!LV{)6V#{46r~6~iDj
z;UX4h>_{Cah6<D`NH_bF-jpe)Cs#P&^~ry8pExI6`K&~RgR;Uzaou}9z%#BU=o+&3
z{TZxM8X-~!p~Foa;ALHxikXdInvR<p6FLTc>r0Jlj7_Dg|4qbJ14hfC0f*_7qpfjP
zL33CSP?};Z<X%2n_E#=ECly0lV=a<w#wg1<Je=b98s|1kf|$K7R4JMFY;@pe3z$Un
zhcoHXvRk8qo!UMrP<@nf7Q}W&kZ<Y$1Bz+8VJD;-0YfZfzwS=RD3vv%#CIbSQ$MEO
zvQD>xtd-kp8H<$`Md`mpxN~t5d~N$`3KA678AOC@A#hnqT!O#;D<Pu=a>kS{xKV}e
zblPBAnenGKvMR5JZ!BC(SOzg|_MU~#q%xWzoPi<<j;yRN7E=tK3O&(OgA|#N%i=(}
z?q&Tv!GAz!g$^pGxc58nEs<`;zTOl=*Z)dY4|y{*)bP<3A3k7Nzx5t5BX6`_QB9lm
zht2h%3Q$;y^O^!tWKz#1Bt?T*`0ty<m#`6*QPbxnnB(@=joE5!cl(R=^-pH#Mm<hN
zpZUNYxfA7iu+4ZU!{)QQ<nysG{J|5xx%d91eB?H0Qi;Y4%r9z5yrJ9b4zdX6gbXs|
z7w!p-83&a7l&nnBBjQWpbB#-qqMh}8DURE_d0H>ZoISA#R@rY3(sEp)Xsf+D?D*1#
z-`mnpWtY|Qbdl649!#1mDtzyp5p&vgH&lHcRTEa{_NlqO5O8Jbfd|b_Nh*v)|6uGF
zq@R-TQ2bLSy&}p4>Xh!mnHm@KunIxxrKT+8<OR-#ku2qM5dfba*}L<M+nkl#SN;At
z>|6&n%N9_PalGivNrTR5AHQ0vQ0bdGE{&9pa&^q7-zI5r(nuqn$F4QZqSKGxQJ_L=
zTdcA4#^_$h#OA6=J2F>H&!NN@UpJ59SpVZ95D3HC1}KgaJftvNVB9w9BFwcDXGdKM
z04`#9W<me3^6-Uxup61lQQmWQ<b|V@9JRU$4Iu<a$Mr%(FN5(V6KO?y$w)&84#FSD
zDERfq^ouVxjwS1xD!r81j4sA|B^xn^_XD?Xi&K_h&xGE@0Cm9|hWyKBb!Frm2DTXa
z@qhO}KC^3P_}UUM!s`;?o?^n^5{rW5FYF(A=-xa{w;WvU);cNRu-*|f4X>EIeC~oY
zE-_4jJPM=f0NP&wA;#S|9m;Q0My2AWTo)xfk5*)DsPh$n@#{XV#qtho^sDS%J60YW
zd+`TjnA`eoOq`y(ZQLD8h=7y<iK2zi`tr7p8fck?Mmpu+#?>GeURhfC>dI+}(Lq}O
zvi!e(S3Rl^x(u7Y><&-l|D3Z<al|9n($dpT&tOi|t3h4a6efMOI1}Y5AmU-M7ZCqZ
z4#PvZQIAemA797a<6ZW@p^eXoAW$XuGOJ%K$7^MV=K({-Yr8wi#S>$Cy&G>Va+`Ay
z!CL^2cXR~D<Kr1e;oRZ6)kzlU$HAR+Jnx)#qr>0-@Y3*uyY5=#90ZhQ5JY1AOUIe7
z5&+DEz<kqf;;zJ5E{^<gy3a6@+Tb*eD0&ErYcK6+CiC6WPb<8e9DG_auS`guCjCMD
z1BO5f&#>(3iSyoxh4cPa-HA6cy`&>T`Tng@r2CWTAUJG}sR!5Ay)D3-#T66Ht(e7^
zS5_Z*?q&Ba;HI~tKU@9Cw}%f$@9q+SAx9bRvW{?$fPkMpf^oNrgttQHMwh5tq7%wY
zroU0Vurib9Xz~=CoK{Fer&@(~0Hk+pBwISnvV|?PWz<dDIr8q173zgx9wGgh*1OLi
zFP~VueqybD(RiKB6v@u-cYuwk4$rSX42ub<3KUiMZ!x!<(WdDZyrWk*rC>=AdinL2
z-}(J7xla|J-qr6;zmuapFS~3;{w^P-N~_BDRcro4@FoM7oG_#wE8J3@=s{h3SR@zM
zBxfQjjL=gU32YLby}UD??~aIgBAJD<MDr*8lm3L9O;{dVpz_H-v3C5#`S!*0^?D~v
z2o{M#i(7z)!~y$r2^LmD400(zBO9O1iP2*ngv!ii=Il<6G0QRVClB5CZSdsNx#nb3
z9z>Wym~-ZS?1iFihv_+WBE&0N`tq<BHTdzZ=?l;DqWz><{`dTRBu+-qTu(Q6lPVFV
ziLSjiVW_+3qQFMBLH43tU-M3o@UEZtI_Q}?b{lRq)@wdFp1zOAlof1TN0+>HQ02`Y
z#Ec9TM=!4cQN8T04zmw``PwJGtKRA>AX)x<dMH;htLULo8@a4zCS%&`^mrqvWjZ$Q
z$b|=<%Xdj2&7AK>RzJF3fPmg-*E`rWb%3%!@OaDe7q=JQD69Hz>YGlCy|{J)s~cx?
z&b60}6TNAOOp#yIr?8G(Ne2%zBm!IFm{~yS79T6evVelGKJx4T&3&(tl3J4S&IOr!
zgCBL|2)z;|)W|xruV=!zQj%KkT4!ZNGI1Dw%yD7FV<aj)6=XbFDE-xF2~vT(E^|hS
znai2p<fu=pTq@fq@<AEP7u(nClqhOkPAq-Ief=74R1HGgrECUc9rB<JQpM&Ov$V2!
zVI`;X-0J9)9x7)i?EP~^cK9)BfIQ7pj3nOEPB*SDYXVzy;VXS2%Vy-t9=Z7JW1}?G
zfH8yf!J59_m&veV<L6dN7$j%$^HbEC91~`LarfBQj{{%etFU%SThfn$Rh0`OlQ1!;
z2L*mX+Hyx6w>U^d5PJFg%kam0+}b0s^W9&k`y)}&GZ7}LuG3B?3=6qy$hu3-<VdGK
zwL~g8<SCye(^=|kcho9cepASeF~_RF8CE&J#ykp6j&T%2{ruX+7pG<d0@zN_x_cKE
zNmdJ~^B?6;QSAIT6cGOtG@ELK(Rcs(AC___;6WFW&vU`i3#1e9rf#YA@J0Xz3}nlw
zwWcwhubfR-BgR-{i%ZFyRC!>~yTT8ow}1r>fwc;F0Nf*vmv{gK0y*AFea!iGa$mBd
z71r@kma2wX2H=2=g|;kL)JSGj#=G2RBt$pk+YN&v9Q|SR7AP_L%RgP%;~t2<Ba$Zq
zc+K6ZICTi(&yLIwV324`GV7V@iA*6_&<vz#=7B`?g|LNaar^*I7a?%%q)nejyr7{8
zMW-CJJ~<PT{VV?5*<5c>fl^=lB79M;UrZV&*!Gof>SdY5tvHe3gF@*%AhLT7N)JDa
z_fC8o7O{YQ;?nSw|Ms5RBgI!n<>(%XgncT#B|4nf9z5nD_+*D>vX-vI6;nAo6P+b#
zQtDTIaOZwyK@+^t-ny<y#d4h6Ig@X}gg^Hw8rEWO0eL7lPF!p^TJr8Q?9I5hV#qs6
zx+A}Y#wCn<BJ2b*fk1aeGAG>UCRXN#UH8rd&o&1n!#9xUN5LaJk269Q-CVa7+}c(x
z32_9*?B8-P9snQYIra4{Hq#TLy>LkcIK|^8wE?@udbi%4u8~&{jhRs-+Xxy&#c}0y
zgI;Jr3Ywe^a(Q^GE3TVRq2=EGFe{-2nZ=8)Qk+!6^Ezp(3wW@jZs&k4UV+?&Rs{s$
z@H}x!OP$oz5E$x|*?yA;DfxQXOufbdN9I`4zEQst08InfS&6~wp$_B{vS7S;OOR7!
zHAC9ngo8g_>qr0nM<Po!Cy+m<BXFbxzmyUN>jI3WyrHV+9JHdJo6r)cN+4K&LCB3!
zpdQ!Y1Y}C8tb8E@`ysuY_zCT)I$!H?t#h4Lk&Gy;D&PN`tE!@aQ_}H7Q0;Ehp(a|s
z|IB*drVj{nQExDN<gthNNITpYkS*CXGm^{XEJ47M%X;-I&)s$8$*<(HKvxM+BPo-O
z-X_fZrV;Vgf=o6soP9t3{8W|yICiW~y~OoiNA=)HMw}#<aT6QL<U#=Pgd0>#CF|iv
zuOV$A3Xxh#E__9Jb>d_Hi@o@A@%6Nyg%uZO*39K9FFyoYlNU+1RC+w9jb91Yl~lf%
z88>;kh}h>V70W4kLn$&7OdkrEjrwioN~KQ)48niHNR{cAkPK(>EN<A6Xm;L!LbA2$
z*xJ;IvGZeNzzLFD)5J}ulsG4Q@?=VX_laqtFsd?FW~d(>Ev}GWdoE7{x=W9I|6kkR
zsXVI5jcX1cz<C$HKs5ggoML@%$(~6S6`cm#A0G<pQgGmJ;YXsOat~fq&`89+qw}!6
zEgyz0M5eRYT4qL#jyaJqS}M;`8Qk|E&!c;Gi&<KG`|VDErqGLRJ-6e{%$Fh$TwyBU
zCHes91MI+i>F0oqVjGRQMly>qDf-$QzaT#R2hAxS7u{N{XSO~7$G=I-FXpC;AI}VP
zoH)|N@eCE9s}G#bi7y6~A8<t}cy_O2s+bXVGI!*=G~~{|!Fu+HvN`Rax$Dd0$a9d*
z7|oL^x!A$$GI2e)tf-iB-JAXUEeq{0;i`wbSm&{5uZ^jbO7biyy2af85(ijR>6z$X
zK5@^f%7JU&p%Lj0?yvm5Y2I^zU-&G22s~$FdOc<Sq86mH%H;Gw(1d0ETw}V{XSny=
zU|jm#m52?_V@gTaB0(okI$y^{mG}MN%aRqxKWLuE4?chV#KrNku`(JFykxPFE}8VC
z{7nA`^duY7H@rxFw}%lzp-||!6fDD@a<({!b>j+ek<cRZ`H4?lEpA36=K85=3WknQ
z=F#+Q1h+;X*k-pz{-rx(!VX_6%f;vNrm?;wNz5+qY&Qirj(P1aZu})fUXGS^lHM?R
zp0UmRbc0;;pf9laePdqv#rVWHzG8aWFz~}*l}M7ai@b>7AY4duuC|DzwPygwQ92SM
zoa3<*2pUoC1Iz9iDpdszdC-6Izr1%ShnvB@FvCrKJOB{yCdWh2-p!eyWjM|)D^A}G
zm<cH61ExhS0;XpPvk2<xl`enYqQBVc<4Vu?^kAAn?(zg7L-A8kO65eVAVmKjcwY&k
z3(S^Vw5E@jVoH+#>Y>p)1{fupcNTwqYARRmBt2wCu)G*r%G?fY`oHwkfo(A%1`CvD
z?*|H;0W1{Q(Y&pcjV$B9=Wtb@ELMx{Yy%4D_C|G#4Q>QYC^?=QU-60kCYHV`6m6K1
zNC6>{z|KLw&4NP{%Rjkqaz%8<vw{JOv9E&t+tmyv4Gw8~8Gz}<_uHpQbn{ZH%qir;
z#>p%W&$h0@%?t1=(aJh(C9c#N!}N9ZEZ_@@yLycBuqmYub;0oi6a&H+^oT4)w<CTC
zU+&W0C7oqu+>zs%Po!T$dCY<ke+5vBCBFN`KeIUQS1$4h%uwn|GB5}m!HsUR9x!p%
zh-op?1DJFsgyj**6m4HqPjwlj!4YAN0OLmiK7(jXP{BK3(;!h5fSvpZ1IYSw?npKq
zNH>2Hqzg~$0Njj0ii}9yj?OH>F5$!8Ey@|i_8alxhn(Lz@R3)dVa*Xc6kQ5BRdLxM
zyA_~oQYK}-)Mbw(teL*7zj1D*SX&$w7gi>2)JMHh&+7()y$a$Q(jLm6hmbh4tY4+S
z*#M_T&-91;`z5^=_|*o8UR!{75(iY2lBn`;lk256NV}IbFX_qQXR;5X)pE|nVkTOz
zV;Gf69DK4x{GB2HS^x9Tk`ZPhmW&3tH{XjixfQ0j!}V-qMwPCxZ2Xs&gkrM!9Qqwd
z)QIF%TUpO&S}cP4j>LDnRFz5!2N7>o%kU>Xwf9}@Y~qoGaW$Ljm;>e+{Thk!d>_S7
z%awFQu8}U{G&bBx#SL<Qr}JSLsV}8CFe0W>76p8Mona?BuELWYP8YneB8XH@Osk}A
zd0>lC$!#HM+Vq5o;wZD<x$bG|-L|r-{0lE&I0?GSvX+r$xrIyKUt~;c(}rLW3sHpt
zak6+pT*4^&@gM&>RShJCCbmN?kjuV9k7vL-Esmj<c!>ebXk9_53unPSxFoj9eTNq+
zBUoN4SrcY=;<Wkrh&aiV(?{E(Rk`dR8{571#j(yO$Id69acCZ(1-y;YM1P^OFs>|d
zSbBo@*yIgNA)jkJ`tCpb>Sq*v1_QJd6;eLdZO-e5JiF=RYhvq@6!pZAu+GZJg|CP|
zz#TcV7Y#`1ylrNvE%5!!T)(5TDRqZ!VT#wLd?57|0%nLiK<aAY{BFOoHM8!E+_qKy
zvT5t6WvE#0uM&zP2)MCOe?2`#(K9(vtmS2+F0c5%u}Gh^|1)i$s_cB4LLoU^l$a{F
zrrRzJUQI<_(@b-Ad)fmvtXfG!J-5|IgCS_{&&b`M#Vv#W3YU2%D0MQUqB-BVCrz6I
zEUw*+ILCo^1Hp{p)9`ii?Q%6vI-G8$fYvFalv^kHJg3icFauwlKGNQV7c!+5QyHwm
zM5@H!idKj5!G89lO;q?g_8)`;Kq;>oYL2#x@GDxXPObNrlFg>D172u8yxPZ6CA_(p
z;Y#g*{UfY_pHa?c!Oe7lQ%*5rekKiGFG}<{?KCENG1ySaxIeC$(d?wklU2g8u#ynj
z!SNFBT&ZWw0>=wq!0FB1!qrE<zx)2V${m-Z_XKwwkwa3zkzk9F_HeGv$JgN_#?=e2
zr!YHi%3G9%!xs4G6hq{HW8|B*ijx%Emg3^I;UDg01fBC4Q`UVieXZImQxAM%t^D>{
za$-FI-QGdG1&8_#MXRYs>D~>wG)_EzE{2kFtkj7)lJV@>e%<n;wY*e`*K6e=Al?Vb
z;N*6&9wg#hkpc>Rs35^dUwK*9OWGH8+&?t{{#)?)9>ERD!>jA_M4KF+BYbL4HBvH=
z&YV=^#dsMkNlXitI<CVEl5DY;j4&-tsGt7IkX^~MX#`TD)vW|PkT$M;n)k2yZ1BzC
z*NS~|<p@716X}O!9w8ab@%6OiYupu3;W?MH!<`8In9I-!cni0*9-sf@%rSIiZ%0p`
z6K`qmCih3=dh(-1b3{`Z7#jk`fIaDaWClgLNa#!lvP{kRy<h!XRz7n;M)Z<)%=wl-
z$J5)2bWV_@ZKbHxVargdC4S|hq1B}S1h-QlG)Jtt--q+SAnj7w+b#CO^Na&!MCvdY
zXsG^`IN)CS(I#^e<Co|j`jYF+-}&1|t%A;Db8D6ZapXFnrkQFsgGMHH2w~GW4wlb-
z_1uHS=j0qRs(C4g77Il1;KXspr)8y#<7i>81zd@oSmJX)D>;)gG3P_bkZsTv_c`hg
z2-sn-ejW#TB9ahWg0LlU3u6TKnM8`{<@f<>;`{&Vu3eEr$)?6W+BkE|K_Zj_uxM)}
zk%%#(B(ZN-a*qukP-6yB!OQw;7uH}-Is(|F&{^sbsrjr{k5$Jyy0r;AcQ&tLL1GDy
zb0HNwEISxflW{o?rbWYusO>1afRS_kZ<g<0`~p#uB$RR;IEOM3#XK-F@5x9meM`wf
zj7<*u1i<6Nfx`N+v#^{*MI)o$fE54np`q{XSkguyTKRaI3kV$uLSqa{e4bTaR2SPi
z+_5pIzb6%t5qIXh+JqWhc@UIfUK2-h8Pp`w#^zs$*e=nw-~TbG((ajl_;U&@mu4}E
zjaq$uBHYJAI%!5%2rWMy6HhnP$X3Pg>yccaw1$t+E)9^0aoDJDQT*3~zcH7>_pvoO
z;qR6?+_LUg`9yo_1flcAx8K%=T?z@y08DbOv?f{k_9wFLcmqTUopMQyuVW6M>qO5z
zBDyYm_rmn!6*}+ba`7MS`V#?OPCLvngDKDAll$Mz=QEiqnj+g!%iX5f*KH4??Bg-w
zS>ihA`Wn6}R^is>Nwoz`3$27Z@=y{rLCs%=s$9=h!XQS|6-L0q@EQJ-5ACQ7X?6_l
zM6!)wNdCA2*pYEJm1cWoP|Z8V;@O$LsSuQ80G&cTuTS-AZ-)ujRcI5Iq9qn{mC`E1
zh%t>Mk^<jd-NHmuD41nS>P%o$2ur!qqTC(zCmO+xwuOwKO*Vyi>*1nDDF*utmWAFK
za(=YRtTVB^GSdd92$9N{YFNObuEa>V0^)ZdcT#UJ3MKL)c$`2j^?b9>yrXnUzTdZ}
z&B2ChQA&y!r|VtRis^(ZbQVnZzE<JmF!f+&(2YoM4mUxB1lBW*dbd9IoJ>+J@EM|D
z>a+leP@U7^^8ucINV`(ViM+bDMM>b!qIW+^8>J$f9#1=utI+s12Dl?IAEY0|wD4Bi
z(`|Bmx*dk*dCr$khxk-qfon_(Cfqj+qTZ^Mp&<RZ3yWtl(BJ=`?kl+5!f*mqm)o?P
z-5}gjSrE1<WoxT|{cidfR?e2#XYQ!qTVk45TiwtZ4p@5J097kF(FdP5Mnq+Xs_i$=
z2X!2LbPN>=n`&9nO~73Xj@%@d#Eo#5;HFs}UZBQJ^=sUg4N%ca$qZQU9Q)~)I1}>a
zU6C05kzqys5~4Q?Iz&;xQv^DB8H^MgN%h7wQ?M1?2^<!t4pbO|y(s06pc4fw$qSNK
zyPC6aOT0lfe=;Ld$0PheWH0l*PsPkA@SD3AcJD?NhU@2(^UF&0Zd2cQ(>(R>{tOS9
zCH!m3ZlV`~WfC^sr<d%MjKc2s5Zy5=i(AnhgI<(l=TEzT{{};h9x3khD<`onu9KVE
zd43$fkF7CI3#tS_*k-yDO-~eI7xs|R1j5Rc<n_kwWZj^A9XP?Ykq5BrIhkUJb)kqn
zXf)&VrrFMVPPK|oAmEcYia-iKgwKFIV+o-W-Of~2g*W98?E9mkJO9zLWHInY83P7)
zwU1V<$AhU`>K1)s*N=xcL}qRW4OQ}~HZP&w;S2G~aTD<VOU|3DN^O}2q4A1d;4e+R
zh>!AXpl@uy<yDhUqWM4t8=6XH+Gte6OgH$8kCQ+a-wisDe8lL)^0Y0(9eR1?xh-fY
zO(=ztclUmCPq9*wx@|d_rS(~kcd~d*m|7DHJwvgbTf9`9I9JOLe?p`Mom1=*ekFn$
zt2(MOnJ@%#66d=UKCMZRZ_29EC%e#YC*F&?j+Y{3y@=YJ*}gHSA=wVO*Z|@^pf2n!
z*4Fr!MdWhr6n*S31~F@bM1kGrNgmoAa^2HKz6kldoX$99qdA(+Nc8aixk`tOwiWs!
zB(Vt90>4w~)jVKCvN&|2d7ni&_(nU4W9m_)aUt#Ay)BU=jksiSXhqzUs+_>m(1*-a
zgXd%`XGgZcy9(AfAG`k=+*gq3ufddR#D4UJkLK~BjMPCLwbP9{C^x4yfE(19W5#pc
zCh?v)H_N)T!)#z9X0QW<8rNVy7*K|;mq=5Tyz{qi=*HVNC9dm1sm)C>wH^ISR%iF+
z-fUDiaML#^w`Z@<o;^GFh|AZ$L3s&z4eqltIaH_}E(dYRvn8}hR-;@PkOo(n86O3&
z%{XYbZHT`tTm(O4twt{$=XFB=xDl%s_a7`gCM@Qs;uzq0m%x7H5tjAj5AT1avbUJG
zw`<KOFw3xiHyt(K1D61s=rRI~NhlR5D5I>Za!uC+O<;5g+g!(T*iEM;zLUKHlUarm
zdY)XCtF(rnu;%&oj^`&G!q7L<b0(EpLS{}5=<EM_zbGyi70U@edSi)`PPvJ%3yZ(o
zKN$PYp`z$(*%|CKlB(+t&R^IFs~aKq#(JjsOp$UC$RtD;bxTBvD&UQ=@UAW7@WqEO
zwLLK)8i1slbOP1$Q-Y#oR+n;_%#|DTk}n`wlr>M6Gn=6viESSLqv?-K%B@n*2c*Im
znea4bX9;#gRkJJcP`^b07c`<oPU^ID6$O-$;;1=THM3y0O#X4Qdt=(;6raJ19dM1f
zN5Q&-x*<x)Q?Y&FgU$kLBq@WUG^klD%+ZYA{oi`92iw6*4**{Auo)9x3ATdEUBI*P
zpvbSidMAe=ZQIpZWtD8Kvr{27_dP9D;37w*@}LFuD%VBBL1UK~6O_>iU??W*NVcGF
zSNS%C!B4b>4S4`gSX_7xZ8|#eo%6qd5|IDe>9Cqsu|8^B!LsJ-I(3QFq#Lju&WL%q
zuil9uY}gHdq;0awj7kHPUxp@aAVX*X@gh<2AboYlYSh=;M5TsPwKIht72NVJS|Lm;
z7YYhvq;HwyDY0UT7U;O-$kBz6=(BchcrTVEvLeCEK$8rR4|C!L^JSVY>`*CGU~V*g
z-!}qKK{J7liH2g~baLmKQxb1#%r4pWWW6pdyH8i^cuX+cU9*!b71VmWi#K7MOe8dM
zN??xB@BL>^f%8w9Hk~U$ltV}reIvIv0i(@=FhjXI&s}(y{$J@gZ4S(;Sqs}2qnug>
zcVTKv3z;&5F2vOnb5n}fj`80FTCH34H9v8^_9i9FU6sCnr)+cXiR7veZNLOtZ%gNf
z37V%{=3$k&X~l65|Hr?G!mOOa?VMK(ZDZawML+Yh^#D;4&4xX*qMP8Bbfw9k%+7-m
zX$%-}kBqSGG`2xA6rvy`PPFKY*~!TV@yY<<WBTvt#@ITep-c(!i-&NCw=YM+E<D}D
zfz63L1tP~j?lE%@KO!mJ=+FNy)ulT#^7jo=QT?C7NKvJm!D}$w)bU`Wdfi6dG2*F2
zI4A<rDpJ*e+8`5ZB_Z{M!IlW&?Mw_V=qF~Ik!-eV9fu8*^G4hteH@0*U9{ztLUSQt
z-<J~+@YYRlojfqb2HOv#Dq&^Be+#Qqir)RhD|>e3X6IBi_XROK7UzII<mFDe(}R?q
z?gn%cq<UtN-n6{K$9jwwmL}>f=8vAo_-!~a4svTUSD>g$BmyxXi#wfGHL*dtVk^IA
zyCe+euEGdSopw}gvKBfu*br?&RY7iW=3f8w;8oG3yo$&>3(*`>AyxaeO;!_jl)7#Q
zSBq~>kD7?ZAP#&YnhA;Th$Ms!Tnk5HXo;eIil3@fCz}%R(pJj&N=@J24&77&O5lsj
zW^&mk%LLC52M8X%y5c6U(Iy;SoA~Ch4pu4^@z?O!;GrY^sAb1ACK;ZOYhWit36*6%
z<9?OjvZ8`TZ#=t-9fQBn1aY&W#Lv%_ysWr2Mf@3$jj!=7|BCW=QBm0juO&>9;@C(q
zV+ds#7y^e}d~!4_aV({oH2)!~(XapbzQqB_H*n?7OwRxHj<}MUO6<@m4~iuBOO9VC
znw#pDsRR7#lC;J(9jXr{f`h+&dB_5Y7BW;#Qu=i>yjOkQ7P6*(-x{zWOTtzRJpfxL
zV1MtDz4Y$q{{`PH4V2&{p0WJ}^0&d;LV_gI@q(Zt+{Gn|jCXh9;Bf=RA2;~Uz9Zkk
zZRUi<{uBHiCwwoo`DqM+>i}cP9db2o+&x@ApguIdc8qjp3XJ{t|C2uV+!clVL9ori
zpq|RzNGvFI!UU2|uHy2iUDXSy(}jjHDccqIbLajuSY&yZZR*lbge%<bNuK5qow>j@
z&bAxVv@O%~abk3`Wq68apUmPaCwE)TAOE?2Y1ixe%f-ty2{(v2m_2kEWJAgo^HMp%
zMrt<AYL_)B8#SY{+Ab8=3WLz3NC0=4<WIj+K<4RP)dC{YE$L2}MJi&6uJ_P}LT&F-
zS<d$W<E2%YX;o{x|0{iBY;7UNE9Q8kbZ^F#?EdY!#KJpGoKuBkn<dZ%_wQ6%pEZm5
zEP};vxIc`(vC=Qle0Jhj{@Z(^pkE|{nv>%LqfyG$5K*lS&UZc28T;YHdo;&<2&=Kf
zC9JI#EQlG$Xg<z9>v>6SNgrtLo^sl}e0{OLHD)l@skUPbk;tYZUCS0KkxwKHmBbNt
zRPopSari&R!AFlt;{4s;IBvaH+cUuJb~814JtN_sCnvEaot1b+m;%`p@oZ|-P|Xfo
zjusP5#wH>FA_H~)ip>c{qGHGU-xL;M>$jZ?^s3+9%y?T?fu+n7IMI*S|AUv@(Y%0r
zDPNZ~DQ_21NEKHBJEAuj7|Q_EY<fLIn-L>OCMnsP9$kF^A3y><_L;qAh#wybc8V{A
z{^<W!4t`w@UZG|w`=kVV4d8O^;*CHVWS&?6;935__d~PY6+`wnF*^WeQfy=WQfBba
z?^bO-=>E>3docEL_1!DPg<_?R9<}Bgr5eAa4G7OD2ta<7>?RGxZFaLHW?<2IMX*$8
z*R;X$p^<zyC5qtNLn0r!mx#jSYC3p`=vdW5>GMv>v!o0VkU#yxFD?xqKrl$tNa?$P
zfH!G85MoeY_`+v_TyQv{HhYQ1-N*EE?E8qEGX`P774kcCXmgaBkEt#|N1L|}ozj*<
zo|{fI*{2*37PW=P^SYDr*bk}~*VfQ2hL=WFJ|lOcS@R_$_VP83tc&`+r6s6AsFT%a
zM}8>c2=_hmD^GmrTICfvlW#81Viu4GkDg*7Vw%ut&LF70l>J-^7?@f_rcI6>$dSHW
zkhCRP(1escpB*it_w({zEX@R+Mo5Mdm~u?FlQ9P)+1AzSl8z%bB;nrvCDw%eL8*f>
z#J$92ykh(uV4d?%@*oN04j=vyb*EQcsnjE$qOef7Oq%}ljhQjim%8g>H)eQ9(DNCA
zq~EG^`lY7*<kS2-%cY7IBgQ9_17m9g%<QpPxN)rPfe<pDtsbv6dOL*ri<i{#G(OE3
zAs`VFVBCuY$<@|zys=TGWR*HwDY{soXgALstq%X_-+o8{HaHT1kfGOn1<ie$iTB?P
zOco?M(8_KtKG%65|A~BUC>m_-24EU?$>ul5GvwhXN(Ky*GN}{ir|P?7FBvZzM=b?e
z2`~>Mu#k(1@HGz8x~Ypd7a%BlBTmucC^O6Y$G_hsYRj#<a52llA{cOeA(n75!IRZO
z`-*l!xyS{lA`@EXxFRRHFEWUBx%=Z{m19s3KI^H}S#+$v5fSo;+YWXO5T~*ArwsX`
zRX35jZWF)$pOV?*%3Xs#VU$|Xfi1>B9tm$^(pZA5qJ(uN5VLS8Yx@x4oF1a#@GE$S
zI@!Oh=_QV(GlU6<OO#;$Vq@9{e<QyQKTyYLLjnlvov{~&M0rc~pL&duW0X#tjTyc|
zAYZ^J;F;XA`VW9n<OYD@0f5`d6Ut)FxN!*TRsg?<z)OR<gEQuN_Z>_87g-R`2o~3M
zbWrT?-KA9V7VE^8cFECIEs8K=Ahz}7e?hScDo#kg{XPNS#54ex#*j%(F<y#9Jlhv!
z^>^U9P#^*({-)uFCF}J54_hLI;%#2aI_9NRavUr(zgj2<GTa;0>IO%c3VK{p_(Rb<
zN8jG#rjHt`&?{R}1);*C%M2OuC-IG`2Oa{Y@XcP%3OD3USNOJsATk@P5AK3y5jjy@
zMuidudFdSWD-Ph2jNQW%JHJ~bYHgt&V+5>I1}lyMWvnzJD9h){Woq1rSJQ=nOJSWV
zv{{V6;_6o(Tp>yEENb+TUq3q-?Quz}@RgUyQ*a^r2e*v<MPj5gprH&)F3?6NmRk%s
zkvs5-fvjyn%UGL((yjmt<mP*@gy65m<<>F}Xs3vVaLR->7JI|ukdr>E@ux;N<@zbr
zaOyloIDky8;W>uvUA|{z^exJrM}QN7=;Ttfv#7>2JCv7cQ;f55NSn}E*6~-*QKXB|
zOPO1Ki3$}?7ykmrfqBG8N(@YM$N4g1*jjG@m9Ul`J}WmZ`1tKC5#r_IEUUzQwBi=n
zD|s9LZn6D??mypeNkyc54WzlYrT+9GHuqK_-UAKsz)mKn;8v_tXJy*tXNF3-d9E<<
z)ZnUI+?yGzJIx%xn(H8jE$QBn9rl2r>OTlBvLw+OxYQhLAabuUthpiTYfY2uCS1?;
zFzv8N8W~_FcX8lrKN_TNkYJeZJ#_t-@$g&$=0{eGkKu`DL_uOXQjmbdp>tTtiERG6
zMSWKM4N;$x=0kmkC-qZI+>@TrqcQ?q5VigC|NX!B=f!io8{67`cN?9*R{dlbbiXd0
zsQewsN%C}?hBB2g)rT|wK1$iA{DK=0WGD^ssG94w!%W4^jufaA&hBI)KdZlU_VP1D
zXid~58W$3diXeI3aRrhl9e=t<#EzPy=*gA$=eFFZLkt2r)KO;M%?8rgI;*?;-{{H-
zoKMr@I!kF*^Q^xJE#g>)xba(Nr*hJzwC<h^XlLY*$Uqv$59<Djmj|UQHs1hNo?q2C
z!>33c>=wQYy54R6*>C<rU_D$M9DQil;7$UFho3E2`ZMv)V|u7Opw*<aKqG{*=5#R&
zG?NF{-4KoYjB8ch5|+#<S2{!9u(`LIDrcw-_ERoTI_X-4(efqlnulR1SdVLKb9~h=
zOy)D~M+Q@NHK^jK*yY-w(vv^=KS#YGz%}JmK0eU=f^Sf5$|<z1!st+;tEq2m299;D
zV6GM??StDYvE=OW<ZPyA)t&$~ipgkJQ7EN>=BkQo;A7Te#38vj>Q)pt2cvLc@!p}p
zekRzX*Gk2`J|FQ^_TkS|JvA8@t4_cVj9Q~eebxGS5eT{D4*o{qs40bga+|}(AF!gw
zqgJIfZ#RcM-|;z>`KsF_g0I9oIZ@T}3oZI_Mz!56*g*xZ0PgDrbLIQrtPHwA1pen+
zGex&#`xO#zrtB!|ozY*j5cWx@)X&FRr6Bg~J@JrDJ-UcDi^?r#mH)PQ%|+!{oZ*)L
zTXT?qQ<gPpPrFX3A`7reqg9)KY}(Krb0TwSepLOC{4g(PSr5sNSh**|!#;Q^4w5Qv
z|3gXcD)AgtXAmJ+<$NKQRjC!^U-K*a*#A8^8IWt@YK#K7l^-dLK2#liXt3F>s!w=R
z<u~G|sJFSMPfOYsouPFU!Eqw9JVDA(ImWH47c@uDy;Yfbez9VPC)`pbVObP?95zQc
z<8Z*a)#*SyqUmSPol(!aB`Ur@zE&6;Eq{Ct3EJ=gZNg*K>Ei-RP1zeJT+w_@8)<`4
zcmC=8_LBd9`0IB*dhh?|r{wzi|K)D>o1@77?5t&d#-DWBLuXyfdwkS-IB;ah>>l+{
zr|6DWRuQ6KHeE___W03Ir&2g#HI<zVm}iR7P6zh3TW;KVZNT-1j5mv{;!#^Wb!YBD
zRUoS`T=JW>`=|ds$4Uo%<aU3jSgu-T(vJNxr&TLN&1)JyaVz@!e>gBXc(pJ&n0sEb
zj^kETDt=0xy{aQq82Yfh2h;gWl$pg%H!DUZZ=h0&DxGT05m;u5L6Ek#cG_bNU7574
z+90-fr8zj_T=nVojw!q2pRAzdudOO;$lzD<xrF0?`d1&BbSeZl?V*A*xmG#wFrSp3
zbKUqM*9?pfeX3ZBW(gRqXMCpV6s#dl;0yJ3IuW1Saj&}3<MCBr#lcmD6|I&`l*chV
zr4c}<l6)!>ac>g=9<ocH7-$Zl4hrr&A6vl_jaIGIXmn_VydOWo$z|Tq;Cy+&s%n^D
z>pi@?UkPmN*rYA)L=INrW?j=%)V>tpBL-;25+{F*I;DI3;8PJRyhrpA26v2g7OWO$
z1)88#@ZvlF;3rn3t?^N`1-Cg-#abNR%R%->hbG)nD+<>A$kFtB!#cGA1ly|cnv^4J
z-h}XMVt-cT$qQ~6*g9|v6^naV_v2KB4O$a?YN4>m`&rG=(NS@(nm+jUHP?Fb_#i@m
zGaf$TN71OKqktcL#;v5o#g(Er|C>c8`uMOq-WfSg#7o*X(vkbjE;k4!?IG1=pIp5-
zu+t{GFCEd-!_H2G{&T8QdGlJ}MFY^L=;4bMteMdQ9@Rai!C(TCxSuKw%n1<~cO_Ja
z-ML}g-MQoJ^4FU82JS<yJE)_{c;FKph2^^uxqn?)jYcNSg#mp!o?k2O9Gnf(F9*(i
zvFO?hW+0l0<|>Vf^>~C;ad}k$YCTFH(w^dc;B<%1xoq{-B4emZ1J`uHFX&+Mc=hp0
zQz0H4)H2{(m1m09Yw<v3XNL^i?57H?$ls|~3;x#&@BH;2H0{#BmkNXH!)kEUnjD<W
zOw-w~ss(DvMn}C;5Ky^w4K^9dw2M(fjWq}GGD|SlQ58+@*lAmQTbG7+SQU05py)nu
zQTU|+;X>5t^cSL%%_ujlKANyh-_qrKt%Aq*tOXmKft+3Q5mREvV4OX%YI-n=7(5L}
z3^~-3U|@wo9>=;^a|0MsWKUPXWUVpbD!(+$NGTFW1J+fK8(9uLL>7Y4#QJ>y`2ly*
z))D{Ueg;RAHAX{&w7|lC(X2H+;95h0+R@~tbb)|3E?}Hojv5mF=ZA0u2Ih-Sz-t#c
zvV?!a;+%y@*RWub4M{NidXSGQ4fvFLH#?*6be^&-Z_-iCz>kdXRE(u+CL*(Tj-ZOy
zi%Z6){*KowIT91t3r<ktWpUDXI&)6xe*PIc^PzFj#K$eUwrRSIRGjn%R|=2@0<e`B
z_*`{C=pX&hzgTjx>2c*4ZiPKMx%;>TYy!<rRyQ~ZX|%+n<%K4xb>J<ckZH=xE{e>B
zWPF$zt>|c!HcZ*3>489mb=dYT>+0Sz+~imtYc6(tRK)0jl?=o{q^4kg_LNgC1y1#~
z;AR{+8;RFZ_-ZP)<|blK4VCpr3xm82+Rr1k$mc+>iq<896*k3+*jB3~(_LvZjw)~_
zA7lkk*C6vNI2umebk4fXva>c)zQ6hVg=7HjXEj&xKo9@cM+&N|h*X=NJ*uu&tDaHB
z!=|}oC@y-AS2taKVFzyv*!>&VVn`XxISii=PcHcawPj5w^#@`+uLav!)ACWKdB1^k
znkIHSys-&jBI?0n4rp~uxx=^09p8@)(f^avs62*geZk`_+M&Vf(4gg6%}0v(O&hW7
zOFZe?fpwPGZ_0MEj*`PpPV$cxydiM~(N#(g*OnLdjfL^x#bvq*f0pHMTpDcVZ$BtM
zK3ITpoCT4pdAu$D(j|Vh<m2!R6$y>?B8Sd-O2hD^JT(0yR;+n3vnrAYp^+S}NxL~V
z7+{(VpORm$RgNYd;i{kg9ULdcdzA)8D}`nlIEBF4`C;#IHpb-cl=Y06Q<yh#J9)EV
z!eA?8D$7~QEzlVyK3<s9LO$8;V%Mt-?e!`ZOy7_<*o+4)H!0vuyOxIOV07z0|Egqc
zzc3UJSW~>4@aQM}c=Y4;XgoJy!OaEy`8`l*NCkpk(aylD0;kU@{ws9gpK;&SPNnI)
z9zxcC$#QehDn*0vsIXRCW)Jy)pA&x&hWJY_?g;JFwoX@Ha&7hIs67sz{&8~7rfKh~
zj_ZLTFWX5B=tQa0WI@(sz?$O%B835V^d46ZT$~$V2m9Zb?J5J@6jr#oQ*uTSawt|B
zbQxJa>A(}t$Nq<V9t^5#>IYvqr%qR^zx-JJ^|iM9E7N;7e#Q50H}q!qOL}21&3)qy
zf82XQt6x4+zd2@Z9?RnE3%7mm36*B<9JvD@_zmn~VUq}-c1II!`V%ghz~8+|gWB_F
zN9Y2q_&&T~cCMUb^CMuZ(5XG#iOdL)krh{_%{M&rcGY}ZCtug)to`ZB#mmLSA=GVl
z{4`$jd!4m0zc(?_B8o5(GV*5ReEy$&BpE%bsvoz1dFPi3X+=K_@A|j=y(#Ih<Kqpr
z_=U>DAN|w#<-*OX-=OR1?==>TpQW5%ZBD5LdbG}+QYkn?R|`s)PNWoy@<s!5v<2#P
z@&09w_Bu6<*Wmlvx!NP=Rz@a@XKSOz+@I?_6NKUppVhTvYWmZcroTb~!rqnQn(<?w
zruX>Ms^gcxzF0Qpx1#u%c{3X8_~z^aG5MW8+-yavs^?xWdq?RwD7T9{&7HVfEf`22
z5WWw8x9q2*d|R(ZpYW}bzv7!fyOSL6;OIrZ&mZz1^4oj?m;SA2BIT4RO7CBGC$!wh
zKZi0N|NY;XBO;o$0>y}anRyqT(XowlHS=*$p@K=)$iuVX{J#oK{_kOK<$+_UHvh?=
z{$g;r+YToGdMfy(VE$(3-KnXM+y8#!$*J!ZboF0f*AE}<Ofll^mnz;Lm?y*a;RBsB
z?Ki3^%?EEg(N}->$*ptM|A)Qz0h8mX4t=}FZ8J7&m}#25&9aeaMlCa1%UBYQqwo@#
zo~@Ba_8RR9g)D)@l9BVt#9Ye`<obr>dU{kN^~x(t@)KbJ2TMXpHV}eM44+>Dc-O38
z9YidH$#oKPEpd4-PVNUDISw)8-uV4a_00Z}R)5xB66Zs;v;C*K`qZgYr>f35b*j3_
zF6Y{9;O&{YW2pEKS$fQL<2zU(mU^RnxOm0znD(()<POB!dBwY%wDEw#j(<b-q2TFk
z^nasFY|8h3L64M|>t1A6vE*E@@ArS5eX@p&M^Vz99zJkW9bJ5XG`iF4T09yT5AgxV
zc&U0ajz76#-OvEmpRUJoH$4#D9oLS>_M1QZDJLxV$A{M!uH6tH{%>VB6<%4c9t{Qy
z)y!}_Fk0C@nr*Bvl)Fyc+ZpDgbxR*FJXqd<0jplRWB9kU6EQ24WmFquZhw@I14MT2
zgg;W}JJFM|wfoV(XK%vM5iBJKvTD1NxmtHc53mlZ7-g@fy&l8PknXw-LrLvfF@5YW
z_`RcV+8<k8QM#~=HEr={eVZ+k@5);Kj-j2Sg`Q80SZtUOjTWBzQpa`KDmbq@5bZ1X
ztHpv9s9&MFR_HebOPw#r#evbA9()A!zZ2{$`;V>tp|0nT2Ju5A{924H<uJWTyrya~
z86k7A%*SWhf^cLc-k;?o1^T+|-56c!>#FHR{@uDSwzp64*+mY_Cn>=_y}w|rIz6e%
zp}2Ot-dydu01y9qPwK90{gZ4^QR9Dqp=%(Hdk(I=XJ>kM{ZHa_&$DlO>R5OJ5W7Q|
zh!Qk@q*hmVL~7lZRpqYmFE{^Oxl#SLio^Az>yWS;JDo*-V^M06w{A<|On}Z9*fCaG
z!!mxe1te2kyQ7QuXZhfp_1KW1IK`p{m}Dry4cTM()|lyhtHh>>J@w*fp}18$1vU~J
zE#!*0>W%i4@G$P_DdRf&$%6%qv9$w3JK|dOhw=WEi~R1<!a9BNBF}0(J$|BGUJA~C
zUM@E#x0mzBwu~OhHztR77Q^yAj~qL|<J@uP39Uu@uEH2PHVmPMVa%w$rrH&<#!ejU
zEOlMXY?F0YmVB_IrMot*<;V_&+nugW)jpY4VP49PSzqkd#Xs+U&31|f5RHqqgw6Hn
zYkHW4s1@TfBLP^myvKU;Cq9BqZn-=2qlNqSUYu~qWBIV)RQ8n@Z-{$g>pl9aWku&}
zacv-e-}bmGTfDm5b=&ag>*=Gx=w!8lQP}!A;~BFSV;V1rw5<L|;$5__H*H<7OHzb>
z9?A}VU7-U<1h_B9;0XPx?Gv&in^Z+lfzNb)q9DwbE(}HK`+dmV14Hj$xqB!UUXI}9
zd*YsF|LZ6F)f!dqpSXTCoV-SL*_GeGgieE2PGhj|df4!*Pp?zy-3JDCmfgpmW>@k2
zR{a}lJMD0|;xuIUIn3x9imi)jQB5s0jqn;4j=tZ!*c#bMBzVa*URUTH!kkUd(Pgu>
z9@SAf1Pg_ACiCFb6lTtPVKgpqRm_d{(Ese9B}cc#qX(NT{{r!6<9HV=y?Ez=xVftM
z@e#P_&L=Oe3<u6(r`$E5s=s7co^W-lqC1XGjL^GO0;ln`O7|bRDRp#Wv}&53UvWz5
zHG{?eK4n$DU3QqSQ2tSvz}r`Wz*fX$TH24{k+DXx>v1&+x|QeZiaOYSC_ARDN&qU4
z#5A`Ndh1+#uu%6b?sUBLP@y5*{H%|;q30ic<jUi4PP4db8+8AhKiDXa_MNFce&=9e
zFbc53E%w~>(jfFx)OS~y%5RK@92&;(Ced^%2l5(KV5E#Z_V{EPodlt=f1={}bl4lK
zUJ;ScUOJ2kjtGRgQlC@oTcHc9!f>VK@%3dtH*zCt7EZAB1KE1v&6|cSxWD<mk8X@{
z7+V(LW}J(j_74TjKsoUhRcl$X<7i=-BW?T+e3h(PR7}^l_(euQE4re}=vFU1N&gdV
zOK*&N)58&4pGUr<x9aGEKHnMBH}l^M|BByjVVIZG`(56Rw@0bCUa-hQ#yg(JBGATl
z?_d9XWB9$^*9UL(cZBcbeEA*z6W2T#zGvGmeQWW-aMQM3AG)*n`<<On4nE%~ymwRd
z>94+PSr4aPPRGZeznfQjj)&&_Mt^ts{C0uyysvLvH48{%o<KhKVuAeVk4<5wF*$Tb
zOg?k_7Y-kEJD+^>gPax(KU3u6I8vPQwcn|q@DJU}{WComY!^36Pi@eR<RUq~-<$L*
z)%SaY)mrHHd8&JJ7?NOvRv~|)cMx(MlPil|bd1U-(FFLz${~dpc^+x`+xAE?(nBFG
zE|_UDRewvpar~-RAnCSbc+R3AGJZ~n7VPN=u0qRd8&gG>m>G_~%N_~!8xAOaC|WY&
z*1~HiuhmS2S=Q!lj=y|;v{((6Q7FHXUW98*dRyor>{p%6Ro?Y74;@6Y?JmMMQAc*~
zUf*gsyL41xUluGO7uP#|3_fcyq+*kabLmiBmyf&f_`>tfu0>Ivy;9s&(W-*z9-~a4
zUE&sM{)ub;w-pA_5=To>s@T9$JPt**ytd16XvOze?V(L^ZH2Eek40<KSh~azH|F1i
zI^b>_M|DMY-tKP+`^Dslx}>bG6ndU-T|a7-d|ik|PYY4|^V{-;)Nra`t#o^`@g@Gw
zRPMyr-dV%iP^!9v2mRW>L48OIxihG-K@~%AekitURgIogB3t%&>F(%FhZ|#*rU(-l
zI&{N{qVfBKu)2Be^0?C<&N|yQ6ev|4tQkR`^$vNv4-0z@U}E8jv5BRaZbRSlYw5>6
z=B%|t8g`IjW8MDk87DG(CDc?Jl}j!6juq|96IEstYz?1agT&-!Y${{k*uENsj%dlX
z2;>SS2lETvkSclmJok;72?`0mE~WKKj0^5H%x}5O8zVMvz3IXT8fMnlt-Li(0t}B<
zNk`F!pbCR!P-=aZdB09$m4U*Y&T?PoMBE`1*a1>7PUhq*zQwGUE~TM?k0u`t+qpDn
zXeH(l#^XfMrKqlpa@zbq|GeBQ=?OpR?DW-*DhMk+udjA6G*or@Q5$0V8`qYUN49Gp
zXOlYA*GTX3EIsDKf~>nj&AlZ=1-7H8uIYW<P|NDa!kD+*7hM~~#RS>+QJ>Z&E1+s2
zgp9fhQ5YYu?~S)n4|XT^ren{(dUe6>*Y2TG(O#N$uJ@G=_jFa#Yw~?pyIZxt^T2xj
zj(T=O&=>31RXbEKO}qo8vxW&UGuo9|#sZ%7F75hz_JyjFR-x`2q=iTDDabnR&c`(s
z&Sb;(2_GYFkhkmMwz?mb^`;2_V5F6yEZ=FP|IVg!z467OVmE_Zs4!{+)=5Q3ilI@&
ztF?xWeL_sC@CU4ro5a8?90q|Cw^9tjD8cB}d3&W_68SJ^(+$ubU=PeR><NNNJZIB^
z)ZOMM?yY&LeqBn{Y%83om#QgU@^(gBFv&$tT3tyyG~ZaO2zFw=BNY1y&94OWT5bg%
z3@acB4wxa8WV4M%RHLN?kLa)%TA?p(6a#n6lbTz!V{C=ZC%-8&8eFm5&BUQoTEz`k
zO7D_YnX0oHMm6Rb15ej3v2ZTYNMUrQR=C{XPJ4j>V{id#5<DN$z@UJjfk8M8!||Bf
z6_ZWPE<JS5MV*5>s$DqdX*U$Ni@J66#yGusC-%}H>p-0x?2=0}am~zDx-=O_c&v-v
zB*34qR-M$td8D__INAjE{x-%^dM2RrCPanL-Do(%KxsNI$(w1gV*VaaEU~hdhuSMS
z5tCk-RJb#{9om;`OmAY|5{lvRLQTt0D8k5qnUf2tVk~i12x(2A@$AQFgjGnxePrSe
z)zhB7Y!?N!YR=7SG<+odN_xk#YB{W1<vP7LUM0Owz4{d~O=S-GlArh?Fp$(s&X_+=
z-*XQZR42@(cScnw6pN<dbSxr`8iG(_DM<(lk)Uye0o{s6@BgD$m+=luZwzwYmI_vy
z{ne6#OtD;FsrHo1R(}7WUuR91ku8KuC6!)|u_hDSR>^a~KcskKw*ffDBC;z5Y0Sm7
zG&^b4UEF)?_l)^6$-EsCU9^#1w6|mPsQ1{l=U+d-WaT4OtDnBO>ToncafBUXPGcU&
zjnx{AB3&ynE>@)UIA$iuKm{2}Q+t2_5p5D;zKW?<_?4>2RG<Hww_y@=YZvD1OotH6
z+C=r`rB;}87NsDE*@i!wG=<_V;L%E$g%YkCi`}pmR+H+d37QIxw}p^2qEfLv$@@BI
zzx7``=&0mXt5<s+)gfvl=<`!0olPZ^pYT1|NHL%suZl6a6F5rvyi3fnfRa&!BM8C8
zetl!?vfSLtum@Q!kAH{IfM-SP*4r**5i*NpRiDy0EU`Z4i8AXJdRf&_tyfjmDjn2)
ztLi(Q5JMWPzBFKK7h{vC7Sr|6<W$7|GvaMe*U{&hm<eDUX%mp7PTBddVYB7q27V4_
zD4%U<M!<&IciaskY<;mc7Txz<Y??V02az{fb;~uiS+TYzUHfi6c3|4IPR`RhptKgQ
zPFBtLh5<Q3x4++y`nbe6J%*Fv9-nVq`gjodxzQ*b7J`mOwLBDwL$MPJIx<|x;BQNB
z%E+`T-n#A8)zuT#^4t9KkoS;3;SKBOV|Ux;TaK)neA~{ibOu|h+iz6cpDVM^-pxUN
zvkHD`%Pr-v{A$<>mT_NPtX{3-dR)7B<eu#l!^71rlhN?cGOF&6hW8HF`zZOgEpgW*
z3t#W>o*rMN@AA904Apn8h=;eVjn@oeu9}SFwHNC#EL0!SL$A|C49z3^Kyr9w1Rs;V
z@!kINc=+$J!EJvi-h>GdF>tszIkIgus`oq;-#Em4_TBks{wj4$+1K7yj=xp(V(*@J
zuPyfNtMVP!WozPPd^2%Nby@IW{R6A(PPw|jab2}~JuQ|^-X>YOukq%Y)OF@9QRKLP
zNRP)O+mPBo@=-kR`$m1xe8_*2jnn#84fkz%blWHs6FbL;>#DvEUBvCprpNr~Zr_rn
zoK#DlKA9=LI`-C``KP1m7WRJ0KMI+U8n?uqt70D#KOG;a-xY0t`pp-qwSn?uG5zgR
z<<2Mj9@2s0D?HoF<=}c<x2}BT5x;kDc{QVF;B<}9qtww=u+%^@JFcT87So+iR*QVU
zi22*y#`3pF*T>|N3C8Lw?RTOgF*k?pZ*OuTDkX|g)VC!@-ziaizf<gtizw=7)+Cn$
zvcp&mKVw+@SX9q`b;bSOCS67Ey*3D+3?3-!_xpG3`oVWsdqba%`Pf9hiNi~Eq#RsT
z6id^`-KB>nj^&RBPSo}HXz(-#Us<n@*Ic_OTdc=j;j=g^kCYer>n4loFQ;RFJ71<i
z0l!=JyT(X1z;<@q(dVN(4sFgBhl_D|<8XbcvpXJ*T|NbYU1UdOxpfRw>~bNg(d)ai
z2X=No9{)ONjutlw_`9;=!oLCzEFKuTn`zH`hU3q!y743X^Y`77Vs9zd>aM=0%mUxH
zm9NMSpU}fMd#PPJ-_x-b$0a9t!?G$axvN)}a}PZ7g|hR}14`C3@kIh_CvMi+{n+^I
z>xb+2`vZM+ux|YIVeDa+_+UF&`gUS}jk%Q13nAKITRH(}vx?B#9ba5KuowH7*fp_C
ziKQ?cjj=I7|DpUSmLAK!XE^P4#l-?Ml+W(`S*vy^8(_=Z5Ub#dU)T|SUEf;mPJK0A
zx7kbKGnO8!FAX;3-w<4(au1ZRF7F>=<E#C+$5*YbV44F1oUYS%WijV8@K}k(27=)R
zdx;Yb<Bru2;p^7WDE&li?ZOn5WsI%Y4t%6;ty}xEJPu=OJ_n&8C_@vTklCF@k=zeR
zvXQvpe>7eA`9H<xS8hC=-&?*Gj_x|BcKLtw{6yVqd~|z$KeoDKK@g9-i=9&WpsGdE
zud&?4s*C-FF|V(PeG#-Q>!?_6bWDd;S|yw~sI0qVu^#Qu4i$@bBaLe>ABqwz_&RsG
zF{0Vi0m&93=7fk{JT<sM)1mm_O4lnscH$BXYvO0i($?bOiTHT@G*-F(Ke|GLTD|m*
z@<Up1JESm4Dz+GO*;CBnV*3V|m%K53RZx5Id|TmL$A<puNV@9*J(S-65$jkysWV%k
z3kEx|5_8?I;n1a-eH_yRb+8}YK^2GD@QygfsZ(z7hOuhA@7Ig_{hjf%KXYBHlJkw~
z=HQ9}_wa+dJGBGb8l<4b-(4@e?lLds(hNSXanBAd@fEay&6H&&NQ?Au-9Pe9fPY-a
z)<@HrbL*vtga^Cm4aA;fH;VCrtcC**U|C+8-k(*>&|@*Ob8Nd<7vdF>XXCnD6!OL5
zvtNAsvB)m(#<d&XVjK2fDqJzJ%RjViq}&|dc~wBOs6)He&reL0zJWR1S+i-~maEHK
z^*2=DRK8nHV;i=_;j?bxK!u@ge-_UXsY>L;U0B1@5!GBBjjhTAcC10wWj{9gqykB+
z>x8$D=kCWn3bZc7Qvp-D&J{yCUAc^MSkhUQ`}ZuE=vrDlxbp5142V1a0-v%jJIL?y
zd&gH_k#(b+{-m7Rh52-`6JJ@juCIT^8Jn=eD_1XdDt%4{dpk-31|>$=hw2V=8>0!=
zt<GY4D-(&sStctZuSh!UtJNz(@6jz)w+l^--mr=-EpM!JjyU1fw?`K+;Rlq67PNvW
zc4FKD@}22o7o%6tvzu=eg>151vzMfFW5YE?tKz2Al@q0ub+kO9N(C>aa}H87I(*$L
z=F(Q<3qVr_nD49Fcz2YGLI=A)=7T{GB@TsYPg%6wBWRsgCyr-nB>qy`D{iynQgNh=
zkTo`(LkZ|i=b|Y6!k=_ZFyy53<>7(q+Q5nL4zDdw>ML;n!m2m<h;>VcRWFalRp^26
zyAi@5L@b3cVgRneM#I?9APmc*V|$~&N*-TPg<sNc9~Dtd`y?n`t!v`Sgq5v~cXmc7
zYi6fNg5Uw&fUq~VzW-C$+TQ-LCC1kFE=*i^_|J7-_xh`^d9wP$?bm+Hy9OiMjvFzu
z?P}amJc!NhH^1;LW1RY2Vw_s_xez0jeulGHr;Ls5#(HAv5+IDDuQxzGJR1maPg}UK
z%OyY_JPVLHF=?5}rhyE!F!@|)F!`O{q&UBmVDiHR$cI|R`QohNv}|pE+_ts#U~Btx
z`B?Ap3en|}O1xcOSV~u_iM<W~mW=X(y`Bo;dM=fd3xfzLn(+uD1^=ijB2&wSnfi{B
zE9CB+DE`0}6-wS<nwSlO3dI-l7ozT*IndFZTWDVP*EN}vMlFc^3HPRSI8o!jFMQ*;
zUoDl@W{s*+#b6PJDpz$dG>g`Px9-Jze5?jot@nCIt1G+`(>67GD6CF+ta}fU{mGxE
zi%S&FSvo`&81r{#;k+WnzdR28^qykZ%Dt<sM&SPNiOVn^PKpK>Ev0RMgReYX5psb_
zu~^-&#mb3c__Q@*S-5Z7?no)dHs$+kvreyVtzCuxL&nFPX>CLm5*Gp}oU_?|A~Ix+
z>M%Q&51isK3hXHsyGQfrsF!?w2?<fGtjsOAETA`)s_Iq4*;MJG>*JCR#l<KL`)p`H
z-r_@N`BWPX-j3E{M?z;a8WRd|!2kl5)%Rx6w;A4uq3$Bws%j`s4M)F=ujz<6#L5h6
z%8C^TsRXqRhZf=`Il7&%HAY)e0SFnqL#loUIKv|p%y5T>FN{G=Vlu^Y8Z!nEYB-iT
zc*f+SXW#P6=51hPu#*Vpr9o~Im>ffhNPW}UQ5rFW@gY49;-b{A!4ItR`FsIwk(p_{
z$1I%p#0~;4O1)wUwrVNg+Wpfht_3Pg%`s=g!sBSNQgo?<j5AC{k83@I^@}p>@iX2C
zc0CMawQRLY?v+VWi<Q9lBi;}nHSAwZcLe!DC|{GV<?{)&%N=WNDwqGqU;iS$AWFzb
zhpW=TK&Xz`rG5UAecgH)s|mVkGO-%+oZbtt2Gv$nL%L)>cgF-t=ZMF6LC)!ME5vJM
z3pNinm>5d+SCt>Kkh|2uT5}N1ZK~($kzFWx>6LmLR^y@Z5x>i!bhT^K5%p<Xg`90Y
z_Ghn_;aQYvs;{IYyR`X$5E533Lp)3I@S@bv5{sD-j*&|Xr%<P&yi;UIo8dE_SOMxh
zpe7<p=38R{^uxfA*rf2{`P;9_V`>N`(JHMEGoDK0h^m*nd&FiqrYhzM4=ok>dXFa~
zjZG;9H{OU-@VG<MB9ii9amJS8)a-54uYV6aLUC`oMRFy9Zho;7YzY~M+J#TCKWvP6
zQsNZ>>6c+q8e}MZ3C6IKIKY)~$5rIQn~^X?4J&#IR-vvCGsvQ-&3z4bq~@JJ5~C~B
z0)QkYV2Xs3je8GwIr*$KaOFvjvQQ3i(5m6k60umQ(u5}tT}8a?>2|QlDNK!qT|&cu
z9IecA<v+Es7aGd~_azyI=`sj(+nkfGiehW2mvmIZKul?PteNeD$Wm>-)x-WYY*5n|
zrHZRojRhrVS1@#e>-W`DMSp+3Rxe~RF@&zF*t>UJnhz)oIbh79*kp(mT#TL4o{7#u
zHX&+)Otc)sC{`Jgh5dRsOTR~!Azj8wtN2ELzpL(Y!^{036^4ERPfc9PS>&dywb{TX
zD)Zb&zGmq_Fg6h7gy*9j5&=D=KBWpx3zvBA2yA?m4&iL9O0E@d3zfW4Tx(BsrNSN?
z=quMmy*8hJFBY$pJ$)5RcV#jlTpQ)V@P$u`5mzdN9A<^E<Y*HIEx~}IDCv?+w#v}K
zq7!gf&0o5j&Lq;7mYyL8qvTRx7YbbGh6kJ=5ZVdx2_=Y2Ym)9tSV00aK{AvO;Fmof
zLyTO@RD|hDaZA&MTFNSfVE#a0Ta{wU4-2)ZZm-PM;r~$5U3Gbfyd@k9CY&}#;GY95
zjf#wzFUY28bVAaIRx4Z#Mlzzw8>N7Lmwd&I*0siE0CaM^7^Rkb8^g=RVk<t-yz}sH
zGXkV2shC;ml1-^3A2vC3GoaTBw9+=G(zgSEZ=6yx@nZ%Z6<Oidpi0xHxtE*>J6lMD
z=~RKuRx@-19tejgKK9{$8IGWp{91v!ZQaspO{XCBN03?+YE~V(2}Wu1sTfnZJk*RT
z(o=-sS_q}AR`ZI_1ex_khN*~uZEB2KwDgfp5yqC%1oINZ(Wa2bB||ZFUrOT)O`fFg
zjBU*jGcjx%YWjWA<JHi+moN18K3*NDhL4VWLs5Q(r+N#Y^}bV%zEeJ4zU}Jgy<*Sa
z;PUTAD_0Gz3?3ctZhFOQRt4^L`Rm-id%PmPovV7Hl<JH2dYIdLL-kMJ`*hB~L<kMj
zL^{GSMJdDO%ysyB<M_r1vt!6SILxX1jgjwm7VT}}D(QgXM`oR9e!0-w=etoU&N9w~
zN3z}T)@*`HakPzzJ^TJu`@GBFUwklF;jbLpR6bT-(R~fysv7t9_{*<exzc~5S6KU=
zGUyfj!W+HLeO?Ws)DRJyfB9Fn!2(=me$0iNN~%5J*(ztVpxoZiVsge*v<AK=6v^Zl
z)3uU%V}v*%lNnTl3QL1kCYBnW#$hRBZ0_0=hQ+&H)9Go%WiKpV{$w?)-?NPb>^`tB
z=potKgRW~1xFK|U_?DZ0@5H;FDV4j{#|=CNb}>gfIJBnh@v*ja>Go=RsTz!NySUqL
z#Obbq$=va9U?N9lDQb6rHe2X^JbpV$)b0bfk@mtydO4qQ)5oyfSol|D9_qH;Xvp5<
ze=B$-yJ%Iz*SGn%tG)-_-vjCUwcUr`Sgn4-^K{R_H@THViwooX-9@V&UsGO`-G%=?
zt2|aKNnQDFx$wX~yKi*yby++uIyX$@^4Z{l?>fN}mx(~epg|@5XoK-il-Oo>cW9Bc
zf#k#2L(w^{e$a%VaD0D^McOt94)*1;BkU)$ZJ@6bgo9P(?ueogyHbeP1XD*FRPoKv
zdR|4>w}ELYx3Z`!Iy*SrcW|X&d4F(drCWJ0sM}W0jl6KbhZ;<=o9}v0shq-YWkuk_
zNiJ!Apn)oQxSND_e>@Ii#5TZJEM4Fy$&b;i0peIhGZlBE2(8=Ihu^K-Z39QBh++B|
zy9UK_2Uk{{o`bJ(*(rDZk^L*X28Q=%8@_VfjpaAj!|#?4=DVn&bs?@lo9O3D&Q<TU
zHx~1z2Qxbh(DMxnNR7>@(QzysP}W4nvG|=tD}!E_eJnZ-`{UN-S2|!#=04>sFp8Z4
z$<$(5VQxTGbm1Pa5~L>f=kF>sI+pv54XP{3Zcsgo?Qj)FHI$+-#DKM-dHowoZi<H4
zpxSiBp)UcoN+LfftJERnX^1tn)k!U9RYcZW#F7G<41;n5ld4})u=hmRm8Z2_hYwrN
zKSG)BM2qdhu-j2w<cCr|_^78~7hJh}6CU9!yo$qW5MFY2f7WIOUzj4P4TN(M>H3c_
zK1@{+I3!6T+>3;>p{r1-%Ran8xwOH6;S_5E#pL_c)}rnRuTAnOM3vxR!4mf#MUIV*
zo>UEMm#P)$%q{SxXutNoDJn2#CM?V@M}vw(8ZK^h^sB=-S53f=aN{hBVA?dztUrD%
zvX90CF!(MX8_w>?rr3Uk1{*gzSP(3bJY6VUmkqHK>e?f#4m&-Y>J9v>h6j}DN%hk)
zDw?2=2BmT=l%msX{%tp%4h5&p=u(7~+7K5hc%x4c3$03b8mBKqH?K(DMN1i@tzGh|
zO{xiY@5pS4q-jl7es4w8aJoW&1h1=jT;bU{KAg~!Dk{SEJt@Uvpb4+oU&V`VPniy_
zr!X#Uw-$CV0^L`?RKvP88&?tXvX(;rF*pWcN`~CLZAD&JT}EqcDvWP99Wj)a{En!C
zK0)svRT?giA(<!2P89O0*w)-mpVb@mu&OJ>Bm;YO*)6~@V4A`1HIHtLgOjqA8EOgO
z;u^A0Zm6UwxNF|xL1}|mL~0qVF4ea5&V6Z!T9^oHp>)qGTvcdn@K$vWR@bIV`+n6Y
zrZA?945kwyUAwpLPcH0y;w@tExXpMs-B>ryPP1$#bDBFohrt4`pjDq6Xc=DSHg~iQ
zFF#BSFH`1@xeYI8v)-J9Nef5|lLuRvOj&PQh8O&<<|s}ZlQTIv;pcTIxa_e@>LNp!
zKdhAUN4u>IR(r$E(NKP`H}UAEaBaBH>wJPSXCF2g)jN)t5&EI{ETua~e0fP4er_B`
zU7OLJ$rx17O}x&IJ;;^FJ19K-th?YnuHlKU6pl~;VTblSN4#Wg-`oAK%oCa*Tr(YJ
z-%ZD#@v8Zi+xH;1NSeq9rzM2iw5w2h0#@%KqOfEGVJ(Z}Bo<JW=1YXcrCISNvZ5%~
z?od9vIT}W;cO&)a3U7J0-^;o$HK7sfSLsg03@U#k{_tMb@Jt{M!LtRcmW|7F&j>}?
zXa4#X>JTbjQXCqZqM0G>xs}vb79JuKqa0ZiG&PiOCFUDYE!s3kL14UuLZKSY#wf%Y
z1~Q@Bg_gCdhjvO8@ZkeramJnOf*jsCp;5{1`za%h%lMQ8`grm;bKOD?q~~!E5_Kuc
z*$~A-N6ZgsjcVm$c5=rvDz+6ihY_rBRovR-FT%+O#hJN~M9wadF$HY8Z%Q%&Eo(<v
zC7DK$0Ry<mxr9hJ6nn$cE#pa|9L?%NUFtwCLy!d@*0j+#vgYt=r1OZ9;pc+N&XP1K
zoKZ$-%$9Z8;R}@DFOkX$<cY&Ua|0q=nMazAi1(>+6BL>SDgduhMmx8nTht85gb>a+
z*g{ZJUiFq&D^p8Ckg=du5R)Q<Z<i#=bo+gjgH))2B&Hbt1XMU;+<Fi$9eOU;>fFqJ
zgX9(=u8pyB9MRn$HWk*w_?g#UY~=-Bx|E`)T1#_?Lg5jdm@*wykH$=(VFBF>BXrQ?
zM;0HoOG9{y1z%LXZk8sh&5=7XB=UZRSGL((eaG@If4>(O&;TN(pg%%_TidkFvM$G@
z02GV*etz`5Qkal`($KjYbughN#vnjZGb~p$D!zC>2x%c;sQT=XveWEYX>Vhpu&kO*
zv^*4|$vLV1MIVzV((G_9YXn>h3@N=Nf#?`HP@dbn+ZgkR)}-%;hdVcDG;=V`<;Mf$
zEqSpQ&aCAxpk7Q)nEFc3|F`1;eL7UqH8BWKO36%EgMx4rRB|*qqLmiDceQAIU;+{-
zA}L%q(?ybylvKoF<`KrY;TOYHm`Q~#(qO~jF_k3tXStBHNq~#x^$bK#E8PCZDJU8=
zL<ajX#LsREoxyU?Rnp@`A;@7xk_3$>e%anwOrW5rVku}yG^7v;CAB1H*QF7MK*tM^
zTWwizFFi@9YIY9KIPgJqWcbebsI{oFjP($sPufN4!iT*J0*Y^PGzS4GftDfJX@$v&
zOr#WmCka)eDTF*E7Yo!Su_>j$HdN3*ExZ68q0-h14YN>NAQHwC-5Z=FV00x_5)$yj
zC~!Img)CO47U<$~*sDsS=!<uk<Ybr$(AL*~2fBoqt>h_!H53#kl7Bg9lx+iC>LZdX
zh99vHO0CjeXsAZB2&oS@RBKK7C<Z9HVm34|N>0@5*<hfULxzS#D2cC;;4V}m^L8f#
zi~1~26VgWgT4RkE*CCx7Hi(VVkr6NdXv1nFuj!J*l3Ymo+~-~!l)O|(9ZC`bpbf^{
znET``^?*;<nA9^pgs17xkS3*aO$AZVlG+m1=)z!ihL4J`WPVYQpw{ru`|ba|oXR6l
zDY|Ls2C`{ph6#8gEkR;A(ydT2GV*axXC)mdeFtQ;gv)Asy_%hivW$~N2*Q!~cW*Hr
z7}rVDHpNH)nm96+A|@fE&zDgvqJxT%WFeR(EwiK))+jPmdptER1}+szAIMp&@Yti*
z-dNlmD3y?_<aryaijmh~fWI{*llCr1iborS$L75$w0wFgS|YnjV4m0!>TzF<FK2?I
z8)w>We7dUlalI+@!#&+dF?cUKSml;?uYFvv@Hk}e@T$MX+VnM1IF6ZRe0)NwFoeWa
z^|$}eY8OVNWI|QYQHnm;n6faL3ZWsjm`x#r=9;0}Rg67ZoyR=lZ_u6hb}QwNN70w}
zc5l1Qo8%IK!|g@Fz@8EM7@@*1@1>!IeVf8HQPkP}bAE4jl{YSCmkd6rVHj1a5aERr
zukIVX9Pw6u(BD`vkR${FP?5YtDpUfjN1%3?8Sx#&<d9Fwc^dsZ6vb0a8W={xkdeZe
zFao<z@I}y0%pJz&;W;|8Ca55jQFiwmUKt$9mlSD3CzCHzOsDai)#|=7>c?`8zZRb#
zq$_M7s;3odQnr8*M5+GbYDF3}+XwE=PHKPm_&{F`D+pc}?981-)*$V-ZV`h8CKFOu
zA9O$G4@{teeeHD`PndP%MoXJO7at!`iORjmf9)N?ceCTGD(X;nQP-M@%7gBO73F+2
z#)Fi~Vk4an(fNWCfB$o(a%ZaINPkQat+0eOp;cSS4eM5%{z*Waf9x2{%ZH32p3`+(
zw~s#%f&hx^B=&*9BeWRNRZ-QQZFcVQJ`5x3Xnb4u2BbJoqr{@ouka67HKL*D_I=a^
z>`QW#Qgy7mqf(Z6c?)}oAcScHbTM&=7Ek{ny0Vxwuvl1!ku2oD(cx;)K^hI!{_Ku%
zEH$1W6f03s@nWnV$__!XfVr8j6Wt!G>ITq%AH#Hkp$3$yfgsGh^uUqOy(?RpGOB=t
zMh9<R^U=~ZT1bS=K$^A~TtGt%J=CfgSy;L+1>n|mA}CySST7XSPWau29e<HWcAd(J
z8r=pjLnw+Rl_)jO9FTit;0Wem$6YfnkeS7TCl7<TKaT67sS_M9sfQz8^O_HrTrb7I
zr63XAv6OLUoq>cy$*un3<X6$Qt|6>5qs2liaI7ZO@hJu-kBZKVbqZUwdwsWsktKJV
zhxk()_xrIE4Gi<n;cm<v<5CG3uS3KY)%@X~_6M6GMp8}SAQd6P1D&&}x&2v)#U*tn
zzS1r;Wuo|t+yF=8#4`{d?&z}n71l6lKo@b?F}#AED58h$hhbDO5LcLtnGgzVxWv+-
z^}@1CLzNdntDUzPwuB0js>LCeVUTXBPyW+<uZbKnYmp^KEM<>R4yZA|(Kl5g!<6Mv
zwjWABZ};mS=1L4@u&&q9AMc1*C8wp?HpD)~ngeZ^Q;SGI(f=>@7fmsk%0?9Ui#XQ!
zl~g(0@#Lgn*1?b|Jj1$Eq7T1&L$NV9S%DwEy_y44b-OUG9ey{pQ865HB+T65Ime=G
z^}q@ZSt?JgK9ohq8Pj4y>(`;c-h~lkM}&I{rS8W`gIxPWb)w%#V7&9uOLRcz#GoZ6
z4MYWFMgW4ywjdAdL@9=qeXEHfnqG54`c7;JPDwS&i~-io4k97X#<4$OaH%>&1Da~7
zMlQ_}&lAQ+Twkaa>P0nw^j|klZn7AE5b}(D!XH^pR=l4KhY%+*T<|I{nRp(7Ax<`{
z=!r`#Pvurh;rJ7H*>j34x8EyDAC0-=X46ND4QPVCH^g1~#P9yx*%oZgcdgZ|1zY=C
ztG@pIfwb43of#9h%ye;y!Gw`4KPzAR>}P)?m(;h^Il-_9F`7!{H)JOf;$hOVO<<tl
zuVuDKUZPqMg7OjEglHn`76{2PN#K2HaVw>f!>6ua)J5}eSJcv_OJEWs|IoRj6bGn)
z%uJyXR;x@finwH}2_lg;nIG2Zhh&B_j>*E=5hBe*NKPUIMJ{tQSpE<^X)}~W<Rj(>
zkwUl@0gsHbPrd#X(l9o+Fcv|cW+Tsg;d3j>*^)9O7c@QMqYSHc6l$muCFCtp+mT1*
z(nw%HHPAWT`N2z(HAFE(0HuQi?NTbj#3Wwnz@z=ivygb^QL(*Xpq4C{O?R=1RDFl`
z5o+uld;Aib7A_3bf@wUG<1q7RCV+6Wd@Y({y%wkT*ON$bsW^S0-$=@7&U6$xCx<*x
zCAQ2s%!^qoV|y8A^@Cep-DT^&Z}BqzN5eO|>&v_L1y?UyS*3yQf8CXnk5;34w>vTt
z?1--Xg|(L)t&V%yBM%h{;mF#aO-oj%@97-B{3}i+O6@%1PU^d(;cu+g2k6_ce0<j*
zF(JOU@A;Lhtk;Ky)sGCSv4Lfu^y=5|wc;zceEHgN<i?d_apYcExnAcE<lpG;?dvKu
z-X5)<bl+AiC~w&nEA$$6pAC=JuNl6a)CDzsv3sT3rK7H>ysEfJUpct-*DhrCebcp9
zR;}0jg=JfG-^Jdtg0s$#Qb+6W*VVnnrGdRjM@QYmhoI+cj+dXT2X?k+Q-1ZNE{(5T
z-_+Tnb!Bx;><!(s-ooT@Rd(VKHjnHZH85Y7FW)!?a=d6Qy;_rwB@!R;n{L>533&@d
zXHT{ete)Ig8ZVRqIGoy3?v<>av3*0?z2$db(iLvW9+QL*KQU8{KYjI`%ai6W4wPm>
zW5G!4UW`gP;aDt92pH5klDu3acJogJwhjynvKJ9*3HLS9%e*VCPjf4w*}aTyg_7&m
z5twjip8x4!pc!tbIkkeqL&C?G#U(RQsRh1iU0h|-H~h?{0BNVCaRY)SaM;095ezTT
zb9TuYr&FVuhb1OTFcr}vOM)q|Yc}ZPB?fqYIh*x<vIfn#1sSlV^b3!X2XG-sU<4LQ
zoZx2~dZ`1YYTS=PjlWKxiy|gsh*(OToGT`ekfv)~Un05*`UuD5Eo2H4ZPoMv#||eZ
z+-chk-~<EH;H?G|#V7{=mPoKs<RFg~H0EbQtBEJ&ZpG~$=LOOm{7ud>R3`xhlzEa4
zAxJy6^$@T=1G4WT4mc9GKQFrTux*}``0uW0r!?SA|3r*{0ZGv2qQEsTOAnHBm2%_(
z6rl=<nZkq1c4%JqS(XpwxfMbLocjx^k&<3MQ+9bN!A0>v;3uG4q#%zxixmTan@tOu
zVxxPKwQIahQYD5v>)6T*a*!l}Lx-&mm}%~8M;X&j0^ig=5L)!58ilbiHYBeC%zk(=
zOhRgJeSthAgaJiODAVSboGtNWO&2fdBqgX3tIVLo%2pDH#|HAgz>v`F>NV%7LUM<Q
zp5kp63zT`59Jr2nq|IGO0kNu!tu~`WZCf?WsUXBB`y}&L!9MeYj(}^@CZSa3io5(q
z!320?Qs#twCPLy23ks7_5Qzj;=?bJ`<<=Pfn(=YD2Aye!Zog<AV9>WgqHW|dfZ913
z12d1sw=7A_QDE<0+c6VfOA8HxsYF&JolXluV#(e~9@4BWL*$SaPE@PNl5g`@|1j8|
z%5xQzT1+=17a7xA0Tciytk{b4739eT5$0Thm)Yk*g<iW4vJ*mvN^1K=@RZyMD|&z@
zpMdI?rbovB0a}<qL372pZm7~i+#qYYm_!W!$t^eS@WJx(dcaK>hM36MF%*6dD(izo
zk{SC*6jUi@ZrBh+hnWepgfcYUq*fXoIx*RSeh}sJp<{(P++S*TFM^ybAjhYSB1nGp
zpP*MdvH03jiX2&Uyt*toQiy;J|5EUns-)RbbfOoHUg|)@J4ja|wu{dZ<}3she6T##
zL1JMU44H0j6Io_4XXWkXELA1+qUDCmJ<>UVmlJe<>(?%dSsBX2W?-qj^u<<*-L=@M
z6`i}l_<-?-)Iz1HmLog^1DLu(tZV=1<jFUq^Qa-N;!=v2ahRb)ka_E&i~A1(<ER?g
zobO+<xE!UdLp$`IvTj`KtQq}1HrE(XhdZKRNmpv!xb13mW&NRIIa)7XDu=$R)za@`
z=}=oWtB}&F(IKX{3FT@WTl9yPkxqrB+m*A_VbHnmbz{2gI97(cvP#S3FH`ylvf0bO
zn>~<6wa%|l>WYx9Q<m#7=+)2sy9Tx04_{!~l*;!9c`!$(4sLQ9ZVLC9&<cWl;~^if
zmy#2q^`SkBdjuK4Y8KjT39A!sCh``FBA+u7ExDvLlh}d@xtT`CLL>$p21H!^q#Ecu
zIX?V%X}kr{gO!)s3?G}kH}x0s7&*e!Qr={Z@-JBpD*RxOSH<3enL*kD4h_h!WV`_-
z7jCMExxdRs=QqAGl$}u~>t_ySG4P=3%JwVpq^U<Lr}=@+?5`%3WpdAyjgf_2DSwZp
zD~Hp#yfnRTj3bGm0YyF>91g`mfo2$6;bCkOq8iJMIJAf(3>FBnaKk(X16YJU!eE9k
zrEK;hoFP50*L?5Yrc(%Ei-1_!O9$0H4=q@)lmZY9S(Bc&wg?*vEkH1*w&8!wY0z2>
z9fpkbZ*-n$(XzZGbQxi-inc3BNh>n0-+8>lIMMM+(55q%Kq{2p)rHp_T*HORP?M<}
ze&&&a#JG_vCn2$^IT)M;-<~suUp(DuNs9+rg_>0^=t%jbYi-{66s6#fnw8kZU^0lm
z1(uUxF`Ho9;l_u1Vk-BDnBykJR?%l-4!?VnDGdyP@0K_WBJwZxF7kjvRH4Ehifb%)
zYeMWJNEYUim@UXJ>15uz6N<vq(yA3k35$l;A7eP1#5^KHHO91~u}vvU(%^)R!uQDm
zY)EpL{0su)3U3rlr!hc40^+OpDX|#JA{0SEETL?8X#Ra;{>a&~d<XyeG`MIevi0p3
zYuXtdwG|2~;_|V?p&=@&I1kbg4kHG&h)V~pN}k}8f=wH<Jr$1{BVFgs!s9%n{OcGe
z%n;-i;j^RVfP0=;)&&25cKgPdlGp4?%32bo=-|kYM1qbqcR(6vk3D4)gQN*bq}XV%
zmxx`&vNlFMAs&@WaFYj;32CIO|IDvnI$y_*xqULG+$kPR*0Id(PSIYL^TmY#GTSF(
zdPU9rmgUUCq_v`^wR??m?0BI!RZoaZV`w{gw9Yg(j0mUxu?5X(QwXeF#Bka^ooX3r
zzO&lS(UO7F+(_FErlRM#p!LrRrWu)-8$RsBav^pESO<`){z7Le<9g+b%*eqUi->Vp
zCzy04zmUPfk^W2izHueJ7VrAGFhEL?QF)Jt>X&iWMl3<Fkstvs*?IkX?+Y6)WX2l?
z4dq}mtGG@c82M@Rk)?sCr5BKLg{}9MCCve5g(gEb4HWf=i0Ki$l78$DQHx4xK$)`0
zi*=ilun}jDl%^yI7kSY)rA0C}VQ&=uRM?$NI~@_VP|9jH!xFPZ;)dbMpvI3v<U%|1
z{Qnx~MZ#utq-z8(W2PRmTeG<lPa>%t=^C)Q2<#4X<^j%!(xZcrB%^JcIs`bO`Nm&k
zwlR=PgC4dSw5<SgDWMnRfJjA3YfQ36RzXX}%uSgLiAf^4%Il29_%^hwopb3zS25lG
zr|grT&XWMl2zzjy0Bn@$c0i|>8b$D<_50}wN+6;bD;3Z!Bk(8l)><DtFe31$5KLn+
z0VSj|`7)Xt!0!95vGSmj3MdDIIeVKT5{7vo1Q01|xZ0K?Dki<@Kh>UY*>z$<78MAu
zvF3$-PJ?yMeyuF|vI5`T7-6Z~P^}Fx0gSN>yMk-9E|lcJb*!TgB?L7!rBYByMq+Sm
zu>$3#<bWpw8I0*D@jZgdP{l-2SkCxdzzZQ1@nLYtNnjBVt}9m<K`PIE@&@#%D$fa^
zQ>930BxA{qs-b0w@q-ZY4<*etG(x??w;UcOATOIU?`{3`E9KHOH{J=M8aYxktq_u@
zg5X+m7P3fYkzs(Gjhk3#EfoY9iZ+s!f$K|S;cDwIwk-vDE6kHfiHu;mi_u46Cu9jG
zSOA@H$^?(Jl)lA9+$I6s4MKu|B;n?{u3N3eyi6^VPhKk13do*z&vP0P?TW&f`G0xA
z5Cf_^$xXX>m@IjO&uKy>1q8_{m%r^-FFj=Smoo?&ft43|qm<f%3s)ZEuwKrR7No&D
z!Cb&`)n65}Q!7dUQx(jq<Mt&bVw!uOFuV!5>~nwj+nLp6^nyGQfe;Q}adHENpj0js
z3CqIZinFP)q+y}C2m!Qi6$8Z{l*Q12)<vnu0a24X@?jyO8#X@x)KuR5GOiQ`fDMWw
zl`J`%0Ph3F0(*IJMu-fxDJyTaYJr5NzoC8pmtV0A41n@84bJdRAU<-)8H&!?i*e6p
z>luNclwk_IAWC3CXxbX@lp2(vMOCK(S#SOGs&qS&1HDivH7)mHrVjTI8nhl6p$x|v
zq8mewPGUkyD#-+O6D23<UL0Q7eKj@^ROmpk7MufmQ4uNw5u_wgwK5wT(vR>S7$&3;
zXn@UyawOo3L5CsNIa{7_5#~-@dpBMV0!K<>q9K`d3lgAY1e1sI0@=Vt#>k@O&P?%3
zBI!Hipg2&ap#T=b)a>Tx3syd$3}7GTD_EeyJej&T{ZbJsEglGl?MA`aPprQ2?r{|^
z@9twRgh4`bML<O!k3vlk!|<aeSK+&wXw-}hHJculbs@gz<A=a#t8j+|3DvLZwKAK-
zzQ?PtUR+IKY2(8#WhWmHDygtP2*Nky`|GuEL!neI*9R`gFTx2~;i_2UyP>)k@3wnc
z&m>bG($&!$T9I_JQ)U(BRYQvBLXY&L;nm315}|t8rVd_GiiN_C>dO{SjQ`Kt;K6!n
zLqW9Z<cBrEWjZanJ!nXVdjnI4q4@2YU>L+GT#O{GIHNC$85M7e5HB2Fq1$#9^&|qR
z=WHAZn}7AsrS+@HXR*C(ppft1^qz85?z|}I_4bv6n_TCsqd{N#mVwLjL&rA_thQKA
zf(R1k2EN{l0)3<sJU)6`Ux!R+%GSOiqY*Rm3`4Sb#Lt)aGT~V&;50#IvKdG*yI~lL
z7{7GUdhg19Xmi;c!j1Iy>Y!Ts1di)1eLbAWFiN6ExG((Z(n@DN9Rz5#EW<~LzX&-#
z*o0i+rh2oTh3tlc(Obh1X92V!=7mv&jH*FNNt^u8$3$`AAH9yKes)tu7q*Vd9tI6|
zu3&`%3bLqg6=z3;O&z7KyMvUC>IQZH2QRE#gu<6XtM3m`Zq_5ttJ3-#!>)nRB`Ll~
zxH*qUEQly%wywNEL{zi1s622O{YCOiTo6Fe;GrC*@h1%$k=-Bb3Onac;BCXiFePC6
z8Y~X;Wo)o|C(B7b`?J=XEvCYOsg?-H{u?)S4HWbHvwZ{QyuYaPri+eYJ%He{;KDk*
zK}okX6M;4%zyLM}0ZSbw3CmsJ-D6RRw(he_6>QSz5DmSb?$g@p4|>fXTw_%_rC-gY
zIG5g020*Z+d??$X;1%W8>5@|*MxT!ICwU9WrPt6BsUsXyWLBNR5Kq3KC8!a!^g-It
zUet4`C3<UF7@(R<AEN5TVh8Cr^Tmh)_+&2XvMF=La|>DJ9yGoRP`xVD=0CRdVI(bh
zky!vqE>Q-m+*y_s81<DHd|!+ggHc&YYxVc>yk9jR_+u$-kTE~h$qlQ;^Ceiq^nPU3
z1_GRTHVyR2vKro3ENw}6k79R-yNDB^Bfonh@s^paI9iloDY#TTwU%JnKv{>jPsY@}
zxGT_Hm_L+<;-4eTdYB;>UxteF*u<rkcW;IcZr!G1-dm6ws^AhJOPX%MRq3Lxfr&^+
z;`nPqKJLZ3f+B^*AwhtlsqY%5N`_gifl;DccuRJlz`-bi;yFigfH*=u9A!!UQ3iJE
zybrCNg+zEBh#etgTqF*6loI>HQ@?T{yCA0M)iSBg8;Uecqkz*maSK@Or6%a#+CB;?
z+LM3pYVaA;QtuND!=jORJkV=rC<n1eSa!|>S^UCM4Y*}O)@ncyeKR<lwH*D`3ET;A
zFtBd;l}i|emZW@+S2H+>s{)3}Td3L+eI;lKaH|Gaw4EcMn5K3`UZLdT7r~wA>iE!*
z+N|Or&7RdT40tk{$}GvPKS=$1sOmokE&Io%s;?V0b1qOY33y<mXt)1F%VV{rXl>N@
zRER{-g7#Cv=;KCgm=V?d{1?n!ki^OUFE1(>dBd{4@QS6?ROym@CcT)dg?(u8QK$Ea
zo7qrDLNbPJc)_p4AwH>C<+bd$h%Y*lqe6KSF9n(?D;uP*2pM0@kUwl|r9;iad>Q>o
zhbSU?T}E{rv0wYpU=`s`!;y>ALFvhY$+on<xLFEo<T9Z{Bm|nGkm8bl3%6L)c{}i-
zl$*A~6C*H*+$_=_BUEVp{5Rn2AP{4y33&vzj7ynBsuXm@j}yU?ZGKxN3QdXns|l{;
zY+69OJh<rT60RE*2(ise%7d4NXhEgtZ*Q1PKpkWRGo%~7z0qg)+S1pC39d;RhkT%v
z90-O1jKoilR!NIkCTg8T(IBxB6z$!2JA$&*g;6CbBT17<2!UZ(#I#KTk-(LB2?EuC
zH+R#A=694l%(zIwQgW(J)$GVpeat<`mufbGG)W|g$(W-+rh+Aa89{I_;pG8Vqy(u(
zK>bOiVExp+uSEV9)f6d+BO9ApR++0!b-C9(M8Xr@O<tLhftS*SQGzp35rzx6RF<hw
z#%u?3SBgy?LUuC|p>^D)X9U$X(OP@=^#B2U5^`k&vVALOG9-YFFo?M(c~T0)WmGoP
zaJ7iCcw0zpNS1m2{oTByOnP(FhQ5K4!crsPtP;>AXM$7!hcj9MZ4RSIf|jIZ9!O*U
zi72XAtgdG%$DQwQbrS|XMsx&o$CB+_T0|3)o6tr&N^X;rsdwQmm`z@@d5Z%Z0t<4I
zbE&#I!KVc8kf}jjDzp_yHdV{e*cRbfz{oW#9CG7$8!!lnZG!@E{g;l~j=&Qb9ZC*B
zl|wtAwzW_;7__4~yVMy9#~3pV5EoE}pOTuH81tKdvlfK&0xd6Rf*dj_CBGKTP_Te;
zWC`q482~M*bEX1qs4gE`W9JwQ4s=EEE{|*WWBV>b+e3J<v^nxdz<=o?YqJoBO9JrC
zQOcmqb?X3#oGs~SwlwH;1*+Dvn1wJfWSqbFnKl3e!q_}!ye`n%VLD+eCK4`0tIXL_
zb%uJOwcM-O<ITYlp+<n>SE`m%Ixtv4d0MQ5MDvGLO;)qXZ74z-YB60yGk{wIlsgbn
zv^e40rhcC#W{!;5^QWMZU#mK$xN`?hv?%=arwKU{T5&@*;hiTs>QZggo;gq=&Jb2g
zZZH+7as%Vdq>LcjLR)GWjnPp#I%ozER`wH<dG5L|iT2J0-_=wQN&Nw4iGoB_iYY~c
zv{X?WC&?@cU@X2fa<fNfe*^q6Xb)yWA2pN=?z=kO3!(G*%wQo3q9txR%I75$Wlo-Z
zk#xb767W(~Aj#qe84V33l6-_wD9I2YeHJj#gxHQh<i`#UYHc{-b&6_>Od7HLYCv~-
zoB57YsJ!R?$0r!CbiTh3Sj<)T7Y<oBQ8R%bE}@EokZq)=$i<onGk#>4w}$0}nytV{
zZCSY$%vNK!&fERfjbZPm$Ymj(3j4B~$CWkajq_<K_TR*TaNXt$`l=~CrB_Fk4-$(2
z$yESM*_VZG7?_4~reB#tL!M0i$k|nxNf}R>zLtNmQj99{YyQ!#%(0iNsm0-B*Amwq
zTzdI>cWC{VidQb6Soa5;_<~G|?@GE30tMS!*KBrBkgX27dJ&&R`R>AJKhddW-WGf?
zZ{}qVJSdCQDvwyIyv;_LUWCOi%HbEkRv-+$y)Sf^<pI&~S#f{cy*@MLw|RXXL*pJD
z&-LB86Q3`Xlv_^c*^LLnRa4RUl9bUV+~3b;QvK-t&_xCXK3~DaFPJcN$qC{c6<?lC
z2evZs(WcmKkx4;u((gOO#uY53K45(R8+fE6{aw#0bheop^N-m5mzA76)A(eb&TE}1
z4=zKaM9p|dnTfyBJ8sM;z`LMISJo)bU17U5tLcoTE6m-7J)K>Ie4O}YW|Z{>wQ;|p
z0$Cv-7|5c!qkRL_944S`;P?msxwN^69=ar@56OQXUE-#TXser-$TYLsoHv}n^tZSG
zNdKW^4Lpou5SfvCjTsYG*~<wt3>Bd#a>t`A#TCSNN3aA=-}|#)mdppRFYLhc`j+qU
zWxYtc<sdJ!m#@l82jv9xPL8?az;rBhhLe(h0|rEYohmn@c8y(R6E6jp2p-5zRCF{j
z5wfd+&^%;vHL|wJ9t<JY{pM#o>6%cW(}Da31F377xR=h`v}+E;2z+66lN$$V?<UB=
z{&*}^fmTQxixCKAvjfp$S+{W@+vpGys{zecL=FSq4FeZ4DKR*T6GD~xMW-D+bd#5o
z+1||+a@c&6%(shXEJ6@@CrZ04B|*D4>ajWTED2Cp`g=3)y(5CgSWL!zO@R+rMYn}X
zWethhJ)?@|E6)Gh?B<dUyww;ipvw*xaKm51Otr#>Bs#O_jA?XwED95-$aGI2#;h)7
zl6?WhV$+wFV@1^CWc62j>e*uI8nH&>)xQmj7`CqhTI%RZOcx!H1XX*He^|C{0Z}$#
zXm<ZfKiUt*bqE}#q>~_NXmSY@j9?jYW@@Gy5d{2rUJ=_5<rhtMYOez=xkuV!@p`5@
zhytyx%*g5tD;?N?QRg;A5&zb<ao_s-_hi?CC}8Jfcs*LOt?Z*3(}4tLLYu(_Hb`({
zoS<K6X~VPgtmVgb4Yw44O6pvwq6?%5OX>E^N(QWn-J;Lmdie$CHRb6IE9aQhMpLdQ
zOr0Ftk_&f2VJaE|%TmlaLN1cYYtfR;t^=IgVe7w6wUu_%i$3Fkyhp2&DtpXMn&F?L
z>4_MF5n-gaf{A4?FtG>&iaYa6qGT^YM1N*6k@Q^CaM25Lwg`TSnFSH2^!z_v29Qgl
zb~nQiJR?XBCUDWZrjr6LK`iRfDY*d#R`gbAe)RivC<aA?x9DNggSPSJTF@7?c_+bH
zVoVOk76GEB3IwcGldU&NP3I<&2J3^jo4j}f_BW!4KypN>Fi;X%tcA~vQwu6FtqLbX
z8oh+au6eaNgC4*HVG|;AZE&87YdxCdWWcr*yshGBOu)J;8fQy{BO;R08hXeuZqm#?
zOrvSy%|v>8(x#~jNf|}fG#JV3hDis^<SZJ9p@U_Ox8f*9yUcQFm{w@bmj#ILOuL!q
z|KF}wS_2kf+T16lZo_WTAbDh-&p;Na{OA*9*Brwl5C7dOS|x0`4M?ncEh%@q2#&<H
zP&SWGI*={yf}$n**29Y~o_ab9Eh(4@Vl9~!X51&3Pe*Wn-;Z7aHm#DiA-1VI1xK(;
zke-T~eIW%ClM^QGhxmdoXObIm0=fl$<}1Rkb3T}vi0hL5y$`mdjL2_*N{pJiYCoSV
zpQ&f<i{{Yp&89YpO6zPtpK(4ziKVFU8OKuktxw79{way)tkF|a&B!jfyx|Wnl#7!R
zo^+ceoij3d)IQ$uc*_&rH0;?0Ptqh(S3CV#&dm>ApTh;D&8<^v&>R&kY33qol7nFt
zF1@SDuWA=|ieOV0GqIT~i<!^O_15oSSeKp^T|t;(x`lD2oY~2ZR(U3<k?H3t?1|TX
znpd&*0RmP@dUS!`x|$95Ody46Ot|Wum&RNqL)eV>)m(KtSKQP)rc243*nDSZgQiWm
zd_q05sq7V1Sh`UuJd2H<hEG>jbuceZkHu2*qE#y3b=<F(>oHBS#4ni-w=k_b<EbSN
zlV&|z^(&<lhi1+2N&@%u4sB6>2(TO(mXd38=5h*GxsYzZ{hRe*`UVw_Qbj^4_6mDT
z9|%&RBCjJQQ;*yvg1S)(CB7X%pf%gdJEsu0ohn(1P4&twwRo^T^)Hu%z2XoI=S^oZ
z4Qpl&axK7<pAkXYaA%yEHPbS8W+uWLX|MT)ufQ$viveYZKH-yuhh~B&GHE!i(R>EX
z8J9F4t>ymye-sZLP)eGl(c7fsm4W~&2}W--ygDbtwo-vIB!MDA^#AVzM*T?$4M`FO
z2{lD<HF`RarZN!SjeqI~s*r-KIRkoI;yBFYo#qYZ8=JrNr4sYBunwbVWy6M|5SHme
z0mBp?#|bG24`({O8Vtl?JFGGDIZH7~hVFKHvq>Bat0$QWl`4_i{@17awL-C}iCQmP
zqe+fssZrQn3L!gD$jIK(cajIx84tKd!<~f-m_f7|>0w+{AgLguAwBltS8bo2z)Bo_
zp+Gp}wdvTCOFKJ<%t%?dDw#3_$@^Aaa$ez?m%=kAZ=Pdh>BP5x?HrSyL$W(xdtuy4
zX4)*gY?au-OG47T7<FL(<an}B&=O@0@5zhC=_ZrTzV*3_TW?EGfc!0B6$~svz)6s}
zB-Lq$7t<MN>4usA|J;q{JmVm|E5RT-4GzdBLrfHoc6xb-FGm0I({iye0Xn`&Ky(x*
zhZ|PQ4BCqc=L9UFr|C4>d9<aW_Wi6g56yG)Ui16EKkMPt%^5*VrJ8-wy!|hy*kSgQ
z8Fyy{42PKKT3$H%hSW(Ff5vxb<S~;o+R?w<*}i(|=NHc&r{;}q;?&3&8*?79`BLs>
zPO-M!aaud()X;zCL4ImWS!4*h`O7}g-qLfv^g1>Dc?Ld}CavLct_KqL!WT{%5!%D3
zd1ZzqJOhMu*k%Zw5hs_;FMR!^nAx|}&}Me0(~yAMvf!Ebj=uI3<OG5lkY@v)zDu&0
zt9x$#;k!*Tgxppz>mKFWykyj0#90%j(zNcUPEp%pM@;i~{$eVA>V>Hb9vQf%s8d-@
zy>RM9v-npgG7)OzGGk9mHA#9XWI|HR*3Hb*G%;C5e&Pao1V#w=Q@C(3%aE!`5(Y9{
z8cb&bORi^*Va*@hC6Vpyr{8E_wZ=`uMD0}aMjLUto*C}^Fs>9P7%?%im>3jirjqNK
z(AqP|Nt$T{;huHB+wM?iF|r|~iD^|(ViTW>QD$Y_4C(m9xd{6R+LSmcAO%udF8D+-
zF=7>Hp(jM(x=o8&faHcrB#g5WK^)tR7uz!*fAz+yd5`ib{>{q<$Hb6mfJ{N0+ni_8
zNKs62O7?wUx-@~)qM5wT{}e!>16d>lnu2Yh%sxcz+y6X1T>;p9g%SeN;F)BVTw|NT
zigX4N=r%;Fxf04I05~QW@?v7{PjEAdjh!7TL;tClXI+?5YZKKhT$Z2%5>qxjVz`~=
zA9E#^>r*UeQ(%p~fQi5;sijY0dozWSvQ5t&bA5&inF7|jFg7Krc-jc3=C_Um)Zk*E
zCaIEgn^+UU1_U5FBf&{fWwMgSrKRebMDbo&nphoAdZPtUwJY5~na<@TpwqX<f=ifx
z62g;MW}>Jau|6rWF><Y>{KgoWL`d!70f^IN#&`%#Lz=#l&lG9e0=tq5bqD>czHz~J
zz>*7YMbfy~48fS6N{Xc$WP*lA5D3B^TnGb#mC1@mI1PLHDxn9&;l~Tlmw#zY!>|GX
z^rn8MHi>QhlK07BDghVMKxbT`lTQ7}B+5Mgzb<8c2Iiyy*FtN6Z+l>iyj`(A17nUc
zI98k})GXo%?6uf-UK_9&WP`$%$&PfPNkKxfJ7S8$V9Dx)lU!2Z8VWOI=<F}ztP*KU
z)_$Z}$S$)Kxf7LpsShz`$&9%em=Xh*f(By0VrPluaZ+i<UMU>`Ddi<&1)EXIsY|gj
ziT}L$bON#Wl`q5<0(cn6<U(37)-<tnwIW~`9>|ewlRBe(ButV|L7u)ab~-WAi2==O
z{?o0cK<FvCBtaU7RFvdLzVfVPluH0p5MvRX207zOY;rI|;ug)ydVBZ53$W^u0?ffO
z@s5xp0D}lq8ghhWq*4j}#A!gtB(Kd8K${<gGLy{OYQE>qGISX5@?L^-QZEVlgr&(u
z*pdU}GrTDmb7vtnkZxrn2;BOVSs2tR1YKIY5|e5d=MU5SwU%xO#iY#A`?bm`Q054-
z3;}ar#G}Z1>o+f+0Q<I44+5~@9x^3%Oby~<t;}HLG}UsmRKu7Slj8*MpHX!XqaUVA
zQcE93*>->WQUlN?LtHi>5Y8OpIsuv3$At>7+0d+!qAuhSCu1=bcU)PNHPe@4w#gLL
zMN39W>}USrk_l<%33gD4#~gtbk_-bT-WO(bhPKASLlBd-l2ZoMQ!ShFVGIhP#Y`&Q
zvW`l}^()VtG0$ekq*4|pc(=ap;=~C=n$ygX+~@3>aWk*;GjFD@AKv}SSX#d{R1;tW
zGm44;Xv9BZK@kHbo_|KbB;j1gNCs*1Aamja*ntd8)A)I@HRw5^XhCLV6~N?^<OgrJ
z!fbyIA|sJ061c3Ce|qM2>paC(0hpWwg5<~;DnRAhoVlDkz{wJhZj<?b-d1wg5=VI1
z$N;84k@y7E)U8CF6p(rZVuEP%9~RGeY#?)=6wPFDX4K@}naYm!p$iRq$y<mFlE4%Y
z8iG_Jmr5bzMRSy^xk5Ar`I-L?DO=Sel8$ud$q+<Gpp1wE;`}7&1S(xha(~hhWKA^@
z9a*1g%rxsJU}vOnL2N-j1GY&8Y3t!Us&ebCr0CQ~GL#^RfsrAH<j|_plVDD@3LaDZ
zB-~)uO1H{0qc&z-wv(R2x%tfx(7%evO@+)#f70!&XD8iAmkNSRKgomN{^v{}llBq}
zP&x2RGN4_WQX6`hQnV<Nyl~Qyx{(i%h{P|#`OTk$Lh`z_8sPwgxePf%IXO&Y-MVTa
zatd5i>w+&1-sw9xh`wuJ03OujQs_b^#6ulZk8)!IInEtsuoL)Re+#cApk^_*pk_*8
z0M89+uGq`GO9h(r9AJeEZV)mV%z~f1dwM;}JV%HSdFV2}&>>Q%RK@I4$=&Rjxp0y=
z9clS~Zp6trBjM}z$l@G*3OIryKh<hXLQ-BZ!jEJsH|9VU3ZyfK`!<Vr2{@hHo1coN
z0XiqN>F%ld{W!<gFlaNLS&ZH~b26F^V~0_3r2gd+%!Nn>PdP{no*QYQ2g~IQJvbw;
zL6L8M1vmhdJ>{@bh%zQW5Cy6LPuQ4y(n&^?RLaFGr>O?~=vgZ#w3p9IihDt%@9TO+
zAL7^yT`IX2I0<97@5xBOx9THdCGJlOA}+OmGUM0$)UUC?4>1;XDRhkIM+Wcx4S0Se
z3*r@iSsiR%P_wPqZf<E?xPBzg9q3wgW#^_xjmpM%xMpk}p4Ozq+5O?{t3Vbx9cfnd
z409!#0TdHPrT|9Uk*XnXMj3fw&X6bvqKSyiD`Ncp?|T)sfmqHfrWqxE6e3&`jQ4b+
zF0?>GOM+lCXFv@U{RsucjNHxY_i&PF=^r4@YX)tpZ=+xURU)U<4a05XhB7Dg1T;qw
zH+tF&dr{C5S{UNUsAzH!MJJR(wCcXq3klfMU{2dMh>QP(ltK>8JC~6h`WReW+MW;s
zsGO$!_9;^vsyv-LK#{~fMu0PZtn0ZDFjC+a^%I&3Ttg-<PA0Pyb?%V(U(mrzuM}zP
zsyDn^ld`S(7@kd37)_3FY)00PTT}a%8KJ1HUQM~8o7gEJQS$ve6d|!9Qi8|6dZEb#
zZAdjxlth7<(r<7AfhtCUB6mvKa;q>~!p!tI0Sj;jrBgH~KJWQCwUPZ3MDZh&#I=6L
za_<Q#i>%F=sdLfM2)vV{XO+chNtEJAwAof+UKqLPyq0t}Eh$lK=4Qe9#Xj}GNlJp1
z_-4!xN-OnKzn+S@l(y6k$u(>@Bh0>=@jx!82TSYdVr-bE8!5q+rwd6(cABTcg00ZJ
z`RVp$>&%;i-WdU$^vcxju~~xqRP>9wn0vl5dQq^f=1<Qx_x6&338BtdZ|8vRm&D0*
zfkJDRT+kx4PRY&ukIfH$qxI71`t^ChY<}XG=aKp>NhxM-nuX7j_$-gT=64=FOOkm!
zewn)|%%db{NIG}RJi`lTdIZH5tlwU6C%u<1W-_8INXR_?$09Gy_Vi8``7-JtK~2r5
zl*D!Xw9esYePyrYa^h$1SP-lYkcDn+3su`C`>Kzh;+yfJi@ngT?L{MU@{1rQg2Y_1
z@w9CJVjZHIuVqWf|ER!!tlyeCw=X>PzCP$V9zK6J=j0PlTwMOVuWw}^ruS^y^=}Ad
zj&Durzdo6lUi|%8$B$qhu$zB=Z*8Fj3oHA*ooC3plsd!1lOBnnzwU=3_Ag9Ws4m6$
zZQcLg1*4d?P>30At@+-Cm#oi${^y`6zO|7oyFCYJXHBwDBr_Q;^oV*^?9VZQceHbQ
z{p&ftbJ}D-5frmtu2uQ6M9f%Hj&{B*g|>{H{ore5VsD`YapMU!$DTedasSrcFTa6?
zwp_BC@7;UaHa*`5KQSH3e_SE@$BOxR34K%a>E3rO>p4FDJRd$e<!i7DETPYCp7W8&
zXTQmkjB97QhMfF#e)rj1XDp$Zk34>AHVA#q6aOya=Bc>Mh>;}{mi4LaGooJN<pPNn
z$<)PX{_^B$7O)e0x+oU&=8_j~m_wy{vDW#2IrD1YdCiX8|9XlvM=%Rm=D>N5q|;H&
z|8x!t#&q&CUs0R6h0@;68`95A>p7mjEHx3+XWaU_m!&MsH}Mu~x<Fb{^V^?VSaXm5
zNte=11ua;YV*Sj==4dr9GHQWFE|dF0H(dB;%8}*8TFmFR!{3m%f2_byyT!>%E>H7@
zr_W32XOq$wuBkPD>QnP*Si)>)2+fcF?!tAfM?Z7s%%<_cq3mqo|BRn4#koJ9t4BFy
z@xi%*`+jh)DbJp6F2r6m_^W<nz9Q=B5nSkg^Yl5*^T~O{=1H&xo2oJS&c(3vMW~(r
zd{wq7ajxf|7>bqtE&N=Pg~mU4`dq1h_H^f4$JuE#JH-N148A$<=3+ePr#ETGLFc@9
zem3!ZHdnrsy9MUxmx9Xdcjt-N%pHto1CqOkJDpP_Uu4XWe^i^{ls_*VZ}{dM#<c|n
zHZOFh6aV;0Hl5eJuFfMiFLIIiJjKpaY%U7Sv%8)P#8liu^VoUu{Cu;WVy<(&fC<lw
z=cle%JujZ)+;Uz#e_484nx_479*EAh?>TF_g&rZ#n&G)7_=!O*ciz3_TzSHzJKrql
zMJ^IA6vfP9n)iKrVHno<h&}e;1@U}KbGr2ZX3Ioh{^s-g>1Z_1`18v|U%J!Ff81rF
z-nuI<J-?;P*|v0<XOlX8^68B)r_-E^%lB#ACLaC=_Pt!7AYJPesF#3~z@Xp%`qfjw
zUh>7<W7~`LsebIgoU0$tS@16L!T09+19PQPb48vtuK8R4>8xqaIl<gCJLlJDCH#pI
z(`S|XCES$k_buEau>}+Dq(JAZaz52+)`#5sx`kWo^Akb-%!zl5pI<4uus-NNIm=o!
z4Ya)_<9R1^7NQ}QdCv@`&P(ZMlhPMTBj%IK^Z3f<S$xnLa(`!EZCbLP&+s!x+B5Iw
zGV_JA;>DKnm(Ae;G84u;uBS$}8Q<QT$Llka3gXRwxnf4lOT1i2QP{urTPJS;A`SFK
zhIPL`$I8?B!^+w6F@olXpP&D$r+ed6nn^L|@D4hs(*O38t$d=><#+D!&9_~aB-RT6
z%xm7f-awn9Wao}jJ7x3d-_gE&>E}~x;KjpiH_mgatg~g){N+D8Tat5sK2^#EsLaxd
zpZe)@&-rXA+nBMV`U2qQJ+=CkNsc1lywtG!i%BQMzRWKb6sz1nytpN;_s1V9mZOvv
z@Xe~TZlrjY{afh8vjzFO*2&v7p1AFklAUa<ZZ`RTi3Moh`@0DQ`L_B?5C7vemJuTs
z1i6xZ!{?I<G9R3O$=E&ofrN+TqfakAyzrq*4Uo)&5N=)XD-y|_P4j2&G(KxfaoPQR
z+IJfknYAhT8Im^t>Gjfg&Et)EBo!wW;hi6g)=@g~@#1+8^|QIa<V-V>Z^pdj;63vT
z?T?GTWLRP@t0gV?%&^XBV9lKP$hQrce^X)OoVto*&$YG!TnN;jd5(s?K%p(UBz?n6
z1loMKiaISkHZ&g$PczXFSx<eiHKxBryySH$s3HDIH88I&UfOs>)-z=qfmHpOS30y`
zXq{E-oI8m;&2Rpud2$kNC%t_Rw+5U0-h}jGTm$IQQ)heY{~wOfhil8Pr~DL4xPSkP
zlHxSD8&Dabss{|zf59aP7i^Ajwb&W`vcSX!EoY#Chg~5^6i=#wB#004J-Bs~Dg$dO
zld2D!dPIiDCQG6i6&=>VnD2_{`74p=5DevU)<7Xp{saOI2!)%3WlKyIkc2Dr!6^?@
zj$9E?pecehYq9{n=>X24-~<QGs|rkzt0v$ntP!YK!4X(VDgoP13M^1t8(4rPPlo~v
zP*8!x3Ft$Rdi^7OKrgp$ayp`+Bq0R6Rai+xQVD2&0C3R}@E)oKK<ivtyjql+6d40t
zJe(M$7=fY?1A#pq6-5RKp;iu8mIkFog22m-Je;(cU>zVYmIg(}1sxtv8cI@(tsNR2
zDod0Y#3VdSL>Lr6hAnVC+YJnEB~bopf#*-4tsvtCSe!s@KM&Lk%OUmxOFRW8)Y=_f
z2)2L}e^~4VIUh^~<U>fHLC!h@`UG6GIRa_09Y7k`xKRPNV1Xf^0n`f&ASeJ?uF$~(
s6l~z|fClde?RhY1%4sU*g3<XylB0vB1zHCw&T(KwRsG?#<bSFG0Km&-D*ylh

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/DevilFish.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/DevilFish.sv
deleted file mode 100644
index ded58af1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/DevilFish.sv	
+++ /dev/null
@@ -1,187 +0,0 @@
-//============================================================================
-//  Arcade: Devil Fish
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module DevilFish(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"DevilFish;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian devilfish(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-	
-mist_video #(.COLOR_DEPTH(3)) mist_video(
-	.clk_sys(clk_24),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : 0),
-	.G(blankn ? g : 0),
-	.B(blankn ? b : 0),
-	.HSync(~hs),
-	.VSync(~vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
-//	.ce_devide(1),
-	.scandoubler_disable(scandoublerD),
-	.scanlines(status[4:3]),
-	.ypbpr(ypbpr)
-	);
-
-user_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-user_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_CLK        (SPI_SCK        ),
-	.SPI_SS_IO      (CONF_DATA0     ),
-	.SPI_MISO       (SPI_DO         ),
-	.SPI_MOSI       (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches       (switches       ),
-	.scandoubler_disable (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.key_strobe     (key_strobe     ),
-	.key_pressed    (key_pressed    ),
-	.key_code       (key_code       ),
-	.joystick_0     (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-
-dac #(
-	.C_bits(11))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i(audio),
-	.dac_o(AUDIO_L)
-	);
-
-//											Normal														Rotated
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-//wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-//reg btn_fire2 = 0;
-//reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       key_pressed;
-wire [7:0] key_code;
-wire       key_strobe;
-
-always @(posedge clk_24) begin
-	if(key_strobe) begin
-		case(key_code)
-			'h75: btn_up          <= key_pressed; // up
-			'h72: btn_down        <= key_pressed; // down
-			'h6B: btn_left        <= key_pressed; // left
-			'h74: btn_right       <= key_pressed; // right
-			'h76: btn_coin        <= key_pressed; // ESC
-			'h05: btn_one_player  <= key_pressed; // F1
-			'h06: btn_two_players <= key_pressed; // F2
-//			'h14: btn_fire3       <= key_pressed; // ctrl
-//			'h11: btn_fire2       <= key_pressed; // alt
-			'h29: btn_fire1       <= key_pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/galaxian.vhd
deleted file mode 100644
index 05956ffa..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,452 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => W_CPU_NMIn,
-		NMI_n         => '1',
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(10 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
-	-- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		
-		I_1P_UP       => P1_CSJUDLR(3),
-		I_2P_UP       => P2_CSJUDLR(3),
-		I_1P_DN       => P1_CSJUDLR(2),
-		I_2P_DN       => P2_CSJUDLR(2),
-		
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 51676803..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index ca6808bf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(10 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(11,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 014e6f7a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,88 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-library unisim;
-	use unisim.vcomponents.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 4c47368c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_UP    : in  std_logic;
-	I_2P_UP    : in  std_logic;
-	I_1P_DN    : in  std_logic;
-	I_2P_DN    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_2P_UP &  I_1P_DN &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01"              &  I_2P_DN &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_video.vhd
deleted file mode 100644
index 27a8432b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,434 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_BANK : std_logic;
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1K VID-Rom
-	k_rom : entity work.GALAXIAN_1K 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_OBJ_ROM_BANK & W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
-	-- 1H VID-Rom
-	h_rom : entity work.GALAXIAN_1H
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => W_OBJ_ROM_BANK & W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-	W_OBJ_ROM_BANK<= not I_H_CNT(8);
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.qip b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.qip
deleted file mode 100644
index 48665362..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.qip	
+++ /dev/null
@@ -1,4 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.qsf
index 8af2e72b..379b72eb 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.qsf	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.qsf	
@@ -40,50 +40,12 @@
 # Project-Wide Assignments
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaxian_MiST.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
 
 # Pin & Location Assignments
 # ==========================
@@ -186,4 +148,105 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 
 # end ENTITY(Galaxian_MiST)
 # -------------------------
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/kb.stp
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaxian_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/galaxian.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VHDL_FILE rtl/kb_synth.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/ym2149.sv
+set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
+set_global_assignment -name QIP_FILE ../../../../common/CPU/T80/T80.qip
+set_global_assignment -name VHDL_FILE rtl/ROM/ROMS.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/zigzag/rom_k.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/zigzag/rom_h.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/zigzag/prog.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/zigzag/col.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/warofbugs/WAROFBUGS_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/warofbugs/WAROFBUGS_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/warofbugs/WAROFBUGS_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/warofbugs/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/victory/prog.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/victory/k_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/victory/h_rom.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/victory/col.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/uniwars/UNIWARS_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/uniwars/UNIWARS_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/uniwars/UNIWARS_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/uniwars/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/pisces/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/pisces/PISCES_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/pisces/PISCES_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/pisces/PISCES_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/orbitron/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/orbitron/ORBITRON_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/orbitron/ORBITRON_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/orbitron/ORBITRON_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/omega/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/omega/OMEGA_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/omega/OMEGA_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/omega/OMEGA_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/mrdonightmare/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/mrdonightmare/MRDONIGHTMARE_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/mrdonightmare/MRDONIGHTMARE_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/mrdonightmare/MRDONIGHTMARE_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/kingbaloon/rom_k.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/kingbaloon/rom_h.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/kingbaloon/prog.vhd
+set_global_assignment -name VHDL_FILE "rtl/ROM/kingbaloon/kbe3-6.vhd"
+set_global_assignment -name VHDL_FILE "rtl/ROM/kingbaloon/kbe2-5.vhd"
+set_global_assignment -name VHDL_FILE "rtl/ROM/kingbaloon/kbe1-4.vhd"
+set_global_assignment -name VHDL_FILE rtl/ROM/kingbaloon/col.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/devilfish/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/devilfish/DEVILFISH_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/devilfish/DEVILFISH_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/devilfish/DEVILFISH_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/chewinggum/prog.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/chewinggum/k.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/chewinggum/h.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/chewinggum/col.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/catacomb/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/catacomb/CATACOMB_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/catacomb/CATACOMB_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/catacomb/CATACOMB_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/blackhole/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/blackhole/BLACKHOLE_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/blackhole/BLACKHOLE_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/blackhole/BLACKHOLE_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/azurian/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/azurian/AZURIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/azurian/AZURIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/azurian/AZURIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/mooncresta/ROM_PGM_0.vhd -hdl_version VHDL_2008
+set_global_assignment -name VHDL_FILE rtl/ROM/mooncresta/MOONCR_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/mooncresta/MOONCR_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/mooncresta/MOONCR_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/galaxian/ROM_PGM_0.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/galaxian/GALAXIAN_6L.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/galaxian/GALAXIAN_1K.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/galaxian/GALAXIAN_1H.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
+set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.sdc b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.sdc
new file mode 100644
index 00000000..81d47ca9
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.sdc	
@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.srf
deleted file mode 100644
index 14cddd5e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Galaxian.srf	
+++ /dev/null
@@ -1,54 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Release/Galaxian.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/Release/Galaxian.rbf
deleted file mode 100644
index 5f2094c1551bacf99cd2d607b33910c374e0ea2b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 298354
zcmeFa4R{>ab>BTRpp}*E+I#OVpurNN=H6X^0}!N$C8@0F56vuP2U64;fSeX_k{Y1$
zzOS7xiE{hYO`FF%i-iP)R76lxD!o=?0Fqs$jw6wF@+3_Y0d$(EX`fhB(mqPREKzBj
zzWp#rC#~#!=>45pj091n1d?DMrs5&7Gjr$8z2}~L?!D*y@0s0KUwv!(k^hy_xBm27
z-}%mWR$h7K&;I<+zWtp){q~=~`WN5%i*Nt=pMRT_S6=xG?tSrww=U@a_`43&fYu)6
z{0d!|1U9YG+NZO$i#bYpIcV*1Z5?NxXLV)i5p)ZbrOQ#S&zGc}wUm{Au47hTc3+;A
zI<s^+o-YrQe=QGko|S*DV^&{wU!IY2vh)i*X63E-nAMZz7e0itF_@*l-SJ%cB|W1v
z%aC+QJM-9tu7c#~L6S#!lB1BMok{IGuYbz@EN_;YrDfOIac#QPD>BLM$x-eLW#>;q
za$bkBbh*w*(uCx?ebzqD?q|of_tu_g_vI+*8BbZBXqB@2aui-}gR*<sQPSmHju~b5
zhN0|Sj#7@)aSbG6TS(F}61ltwk~}{R$uqY@ElASkzFdnQzZHE1lKUTCB`GJP80uIh
z_Y6{yBu%eUc3YnLZRkEoZV5lXxk|qUtvz3Rouy~TjE8-Yl(|;_L<VwSj(JE!(q17+
z%cz~w{uDmsEIUe@<y?-EE+prYmXV}od}Q@y<0ETtR#$eEXGBMYuOgH^FZZPn<#|c_
z9VpX*B}mfNlB8vnrAz+oJgZNRq5~Oad}VEr`&m1rJgI*knt`5$o`<q}&UJhd%I;<L
z%W(n<R!Qm+5<cW8$#VP!=n!Ne;Z2_Tmyo3Y3?%pD`roaRoM)7!$?-oxYp+Mnpu>>J
zTuAhxeU{G)4?;2~gd{zahm5&we2F~dT4W+eAvqskrFKd??cYEzKyvF0Hb$iUwe`!j
z$nFD>@FCY3J+?}cF1jHy75&fp?p`Px4{tSAet(s+yi!ia*BB)AWjtlaj0ZVpe8{;E
z-3>{R!p9Sk9HneY%j#IqQR==25`LuLMfaqRb5YMKW%s2GKL~As<d*O$*P<UXw+XF1
zZ>QXT`~O&_?4H!We+^Yv$wG1}x8yvdUtA@*9)RTdMM&hZme$Hf(*F?3?u&dLg0gEl
z%J>x$ex%QZvT-X%;YIpK>XW044`D^_iJr={q6flDMsKAT=jtP=e=SLULT!%PpY4?P
z=Wnc%TxIeS5esh_WinrT6#1_uxwrOuEe~=o{eCtcvb6glsW0PAbn7pmj0ZW&_1n?f
zc|^{$v63CL`p$LC>dWp6@6xs`UBo3kNLog3$CKR8>d%g{#%5#TOxZ}?GIt8exy&DT
zLjM^OU6b`!j-rzp{qZWvwVY<@*-^&W6eQ(kX)<otlH6NM()P92ZH`{&N%$5%GWtiW
zB-g^D=%|b%sZWkyg@iXb&q&f_PReNKSx96ib!GH<Nal;|TGpeCx3e9;4m|*ge#(7W
zpRzPbe+H5=MaE*22<?IjXON_2B)5bIA>l*p0pU~Djz?B0TZd(>5t4iDv-anIU8OVA
zgb$%luTpspW%aK;3jab`n(!gIpEAdX=&W34w04}H?Oec*Z$i@l83{jY*f{IyQ>!F=
zNCshF%8_K@Ph`KgzKkC^u1!DlJmVpo=0&cV4I=YrMl!DoiH#;C>2fV=)nA9YR_W&;
zxfZ)ajvs@B2RRCTA0$Uf6B2&Je$4m~`O0}VHZozzwai~~6njYKG$9%5-H_P2{|d_N
zYB~P1x1clU`2Pe+TE<6ql={|E##_dh$o<QZ<jG_u>yOAmNX|2oYmv*^<C*7~UWpts
zk};6kY0`G7E8|1%$#vUGd(V4BMtzW^$r>#4n~?OYOd*4i+>^9NA+cL-h2*~2Y9dQX
z6B{iXYm!gWN1?SmN!>y+UgaqF<S69}iEM=ATx>@<N<Cj%B{~0jNRHx*iES@Ou@nDa
zNY1k~xz0#*E+f&wjHGU%j1QUa<T{h-nS4n5r0$F|zGTi2|5%O(SLt6spIfCYP3E#Y
zR!L;=ASB0(<d&QZ4??m|2noOKly+LycOok}&yHf3$@yK-4UpXXtB|B+Yvv9})^i~l
z!(wNM4!jj*&x$-m4@8$l_hsFX^+iao-;QL>6w2~RIWm`J^c5(ZujDA{*|?FTv`I+L
zw?T5;3W=@=2_JHlu`EZKCnQadaxEn1l9rLANxujQKhj3ApEG}4j#>X?Y43xshq83(
zw@*NlCM4^ZT+4hVcC?V3|4pcU)&5*Nw@Tkh{c9<!Pk72GOOvD2BP8d-leFRYAknLg
z<oZl{?hHBstxa0XgPe=*W%bKZ>JyT4nZrcCWNwwYMo7l}zlS6(Be{M%5*e)}8M87r
zGm`qwMt=s$*jsx~Yzd*WrAhiXR!Pp!ht`&N<@|~Su1MgD1lB77ng3)yeMA1n8{p<Q
z+&are@r<-*9!sseHL16(IX}<SuRrjf^L*mm*;oF?=ovSoH(<tR+<fcHl|OsK-2T>?
z-|p^bJKyzoS=N33&8=Mbqi@c*@r?Q4!y@(JV#sGcRh0&xb%#3{MIL9dLsEWI!_!Wx
zK#`T_<l$gu6A#biJzS|<DvouY`mC2el0BauZ*c;T=Q+=}HaQfMmr~zAhsVg0QDEHC
z8qHm~<-awI>&#2t&)FX?c3ZNJD94G4o93;roeyuiZ4)_0ZW*pSB{wR53~roAOD>*C
zGc@d?a&C#Y*Xsiw#djU6Z<<%yaX#MbI>Exsc)eyzZX+DG^E`XYhqX80$-{SjNd_SK
zhK0Afl7ic#EO4EMwB<FDHi;ICjDn^sLUWwMb@`NsXM#;U+^jUn7Mq6m;_tp&Zfyu%
z=8Co<ZFHQC9|2bwTfYRZ=-B#Y)y}zAV(DaXz6Gq!zw*V!wU-xneq|(`ul%k^?25$B
zA^{oV&9kImNK)k9@N<{a!oComR-bvNXn!Ea-iA=|>%V^0h7=@)pk<dYXXodkzLiYW
zfB$K22QIFLsVAOOsf+czFL!&pS9HU5l*L!U`{>`~>})Ny($dcR0q2?jykY$;ee+gr
zI=_32vyJQM@BZBRRsL4FFY^fi&2UmD7QJv*)xx>R#FbzBjz|PoI6@cOj@+syUToqs
zUwWS`8keHz!u$00eVZ!-=0x?Yv9<D9{#xs<@T;-;+Vp3`FLvo4d}Z4Hh&gf3KmBKm
zn!G<SIPg;Z%DwW;8ArRNbyw}OecXD&yS@FDd+WE^<FxRJO8es2fmFC}rOoTV_l=|1
ztUvSH<YcDUxViGVr`F&jZ&UHx-QMUa?Ct7X_x%lHOc0xupWUE|`rL(qNL>i6{F`GJ
z^4Qs*x%4yjWzxzGTPTYwC;$1`WqBc~mtOuC!WGY4VeEVbw^0&H2h5Lud1DkdE$r)m
z>s>SF+nRIak6d;0<5*43hMCvrw8vNe-p`zai3>>HsLr8k<^1UM6)*n$`e1cwz7!@b
z)-k+Xr1gH*$1&+;5T5nkMJDb%6^N~!n$(*sR*dl7RWVLC7pp(`%6<EP#4JyLB3$g!
z+kYF2TdZ@;@3w(`=Fy%^?eWX?ar+#+zro^Oz1aM}HfDwsMO?Y=OXsJLZ<U*=VxwkD
z<)~MGOlHfq6kWI}e*K*rg%ZKUXNy;_W$U8OH_Y@FE;ewkK0DrWfhMW5a{s@$C@H<+
z;de|cH*T1}gCMFmsLBOjZ1k|)sJ#ov*<hq(<8<tDT}mA1&r9gRIj!Xlv&Y{VaQ8dP
zi@!)?^{kKorNq0Vg|A()yEoA8-so-1#)fUQwKoSZc;S5GgO}V?dt-I$zq-QM`eoJ5
z`Hqp;Mwx0?!c5Lr#Wvi5-8kcRqvz|(m$MC9NmTyCGZNyzVfOX8Ecl{x*B_n<6`jB8
zWlwCh=eJ=!eZ}xTt2w>?#7k><qd)6sW&Jq?O1}blXM^+NkC-tVwZNxX%*FuT@=lQY
z@85gz&C5#IFl$YMFn-`)WyN0nal;scm5rXNFTQoFC7hkH_UlaNUCGM!A3E=6&iTOQ
zEdC8!DV-~D_c;~d>^IJ?uxHQvwyBr1j=e4O>&<|~HcnrG&Ns~LcG?k(m)z=hF4riN
zbXnM_HU6FD#Q&v>GLg}G37C#f{p8*&R`>r}?_Bt{`Jz)lJ9nARmRI2Jx9z<%GF-70
z&Jf7kUS8G`yRuTgZU3#!a5?wo#!azT;O@13zP|G-Z&l*>ZJY|egM9e)qrvOXd1=9J
zSu`$z-R)d?tMXF4RhfP%)cPi}bL6^f;F>ps-4}>yI(Pr;3y<YKlfO4F$+u+RvUO(G
zbzI+2c&7$;uR}Oz&GJsc`_9_<3rf5qvGWz%6^UJu*jXgdp8C%f7_vd3C+U0W|K##~
zrE){}K#R|Hy>r&SOJTlV(l;ta{Vx&ISH8+b-h|y4db2fp5#?^+vZwM#|Hh@Xxzko&
z(EEW!=cyk_zr_9`1oir(m#h5OHB+x!ek-L%UvKioo^7C(t*e#mb{bcPH#YQT!_cXB
zR4nGjs#p8@jUJa9wQu1>r~ciKZcG!U6voo!%h{Xpn+t4s{=_fJ3rAOiOfFD<Z+z@Z
zkjcdwwwKiKmQ`c@!29}h7WcmAis8L+-yyhm9*^HRz%Jlw<>8-e$P~9BbZLW3qKkO>
z<-Xt8kOroO{O>j+*UkAA#?~#W)r^;`#NJT|)%kYX+4EnnT`4hvXXp4rQa7@d#k;yM
zPZ%_R>aQ;&oJ$OMi})|+FYdk&^*Gxzk^AG9sRC}at4!<HZ<Ve;=cNrXxkOACpZZ4~
zSFG-hgS#*H$?|L?{{qrBa(!9H@MfQ9owTwi{SE7N=6;)OZ{Nyb{aXl6HQ)U<)vf>b
zIz+bq!rs1>>o4ma!Pph6d;JQrn)7niu`5>hd3R-Mb+^s|b|+Ep?Dlv*cY%-G^}u`2
zo5gcIu+g*AhV7rdW8Tn43EqrtqcdkQ$j>wDCyaZZPrNC3<lKBv_`Ms!<XNj+`NSVh
z#Q&Wi!r9^97ymfNzR&o-f8$r<JE!hXe?Vt)>i+Z>bh=&`m!Hs?Ouj5%<;@}e4V~pz
zerEMIbmX|hf1v%NI(@JB>96SgB`l<Vn|w3*H~C?mc5CXloo@Y`jT>s0{(D*9yq~}3
z*Lu%2H%a<+>p`E_X>z{!M{k}t+dsAZRvet;-Zy?_V}2meO8H;^rSpfA&glUBf9KEG
zIXmO7&v@r(|2mS>rme~MK=J>m7@nXl8u=0FwY2iN-(7ooapxF`8#m0~LGMdloYb?Y
zH`+ML%Dw30<;>W|>FY*+=LyElS%L8jHpBr!-}Eb(skwjZfBw-$_wj25Y_y};e68e*
zJh}TT=f7&5tIEq+qtTm-H^$Fy=XUB#TKL2a@;+<LZ^rP?(^YtN`n_Gh|DmtOCz}US
z(|mt3wbXat_`-1dQ#&_en)6#blga(*kL`55@RRZ@mt8OHO@D3Y&^P%x%haajc(Qq_
zZJF<HwoUcFgoR+5%a3;cO#QZYYq<XClYeEyhT7SG)8Rsm*Qd6>TNGnsDE;Y#jVbD_
zew`+I3s`y85<7#5yAPhz5I)o1eWNXXrbU;Q`%|CEihpC~EcJYj&;6c!>+Si|S=;%*
z@1J89mLYz=^oh^?Wi!!(3uxu52QT2EbBIzFt_>UJ@01nw9J0KC<PA2CHq>~%faaXz
z5n8!nI(GJ@<Qx^hT{7C=z&hF(;%f=9hOU_C8#kf6bHc_isTqAq3%_(WdUWdN!YeTP
znq7fQ45M%KS7L44%z9~~%g;Xhug^?==GjfFk7tHlc3e$vo9dcn;q29rYO_0>{M5&@
zi}rE#vDcUhowJwJF5^v>|K~q>)@sl6AKqAJc12wP2VQpRIRDQ#Uq3&~S;N(5v~u;~
zw4gUI&J7Z;|ATXSIA<w7OA6L-)J`KM44svqe<90qj$`AE!dT@_G9$h-ZaRPR*1XA!
zVP{hC=A_juH~h7Yi$}Yhp{6q>a^cq-Y#3iSBWFJO4q{AHyeNaWpGj^>0Jif4*_gJX
zgyDL)&a=1YxZ<yIYV_}%Dbx$Ueg}2Og$wBoPrkz>wzIu<YMJ1Zyvvo$``HQ@t(mg<
zMeeqs0y2o&%U{V$*JtZk{_}e%4{u66ycCw^cH}mUo6h@Ejn5KD**n$Y*T3dq^{mYW
zB~W`vS=1rJt6hm4KDzaNqzGTDOH1HtKYfaPp`(LDvinP~m)s6Y$XX!G2Da%5^L~{J
zCv12P%T;jtuYSYPZ3alDibk8|R0@8dF|OZ8sI3tvZr7?nB3JRm8>^5)A?s8dR6|=r
zk;>P<@7=G7Q%(XYT-wq8kb0F*Qk%4t`6l33m=3)8^eOT+yp_%I>I1JIxGRMPP1ivf
zfg7#1LUO#;I=K*0Am&xe%7#+9T)$Ymx{>km+KD{i1hFVa%5Wy%>=-F`m0g==UHw=s
zf8|epe)YN4^uTp|RZvOns=Sdy0r4WtVlnUXKUJ~FP5Yjbvl201gh>vROSd)Y$g~E>
zd9LUMIZ73RM=df+C81H2SQMsxGoO}54UN}IUG2WMKtjYKMbZjsNaTJZ{p~U-wk<s=
zoW9Y;B^4!!%c&o^P8S+cbW|~t1ZMMg;asK<w&lvmXoxyU$;duE`{s{kvC(bz<YBj{
z9G>iPHIFNphe6ILSfwf<BIhsfwlCWS@)=U>YklfCPyJz5bOSB|;Up3n7hyZ$2;)Vk
z*e)7*_>_ihIHMgZPj9N#k&gNXjK(&@Qk&4q)^E2@)_h7m>0n4tD2WS7ja~F6&6Y}s
zn&GnHr73BDwk6N?%1_Bx%}dv<l9suG#>=pjQ6D8nN}`C@Dbqlw(M-z}5wukVu2XvM
z3ukW8G+e)%CX1}oG1r(}E#<Ys+E1>2rbWv6YbQ?eng7CS{~D`!E@__!OcLos?bfHK
zMFd%-LsQjLO8OVdt5v-YR;M4B6^5BApzH0snhtZOocp53NP<6})m?L{Cs|gy$1TjM
zB6(C{nbIcJPNmY(6US0Rk+BqrDn)UuNQqRe6sJfZ9p}Goq|+cuW5Y(XX_*7l<`qBx
zAG6(ov`y)f;1|2yLOiL8-OEyRS6Wa(#dGPYl&h$VuJ);x6B)sg4DR&5=o8bd=)Zi@
z$gn|uw%t~mxbk~X;s&>+DWATyy<uXtpmb6Bx>#`GU_l{=^iq-#s{9XV5>tdP0?*Rq
zMCNp9oBVHh?c?ev735F-(7(h?E4do|Vt2pP;Z*8R>vuV&qYt^aKdDM;R81|YR<V>I
zF?AgY=A=sY#S3bSzP8wTRDS_6>}+)|x17#cJ*gflI-PV^F>mULj@?SVbFMz3B*%%-
zoHKAN^jZyXz8w1Vc0ilD%b{+cu-o=KcA(mNvHp*(GoaH@;hPt~i}f_^d3bZ?75_^v
zf3ZUQizTDbF&a3pbSLbTMwQ%GPG>5IlH1A9ZOAk<qBtEzM(LR|uxOomYT+;-eGLbm
z{Lv$68oKAK%swjvjWelN^gCdY@>Qo<pxftBTc^{7H+V@?xT2$_BG_nGBacb0^cIH!
zMrD|Oieg*3KCLbkUZ8*UAJ|uEcf1T7I-YT<i=8wzt!aev=2hpY@=LKR1E2PA109#)
z#7%ULJbX%p(lBY2lnl||(zNzvapfm|q@66)2+fN=Q8Y3eRazt$(Kw_@=lf2vv_Kcr
zyNE-IZ%?`+PsF-9cBzT~G>PTbqaGR?P@&Mu^^c`TKHANrHm4XM$IgUx&dD2Ul2sEO
zm!`EPmQEWy(yl{#57t)8Nv)Jro2e-r@Y3XOei@g!tu1mbeIo*t292m<$)%ul0nN*l
zk3z}>PgU89lGY%Xa)Rh6LgYt-<}J->*O4~p8-Mq`XLD=vZcB=zO*9BEh&AJ;O?1=k
zzSPqa0jdPy6+_sF=ISyu<=(1~6nJm&oI>$@R`h@5z=Y>8-&?ZcS2f(*bC`Mhkj&b?
zo>zX9G{qX}-$a9ckf)*?jaaS8ZM#zKWYKRXy;Tp3wk)+|Mv%tb@Qd$xV{~(i+Hk;%
zDjJ4srW#>7@$zuK56LaHWX6exX>fy4_S&7*HU)L~Xt)iJ8+6v;{SKd*KUe(3|8>ok
zP>R<hL)IBe!E_*`Wf6qh19vqsO_7g4^fcAdEQwBsir;)RTgtK<WNw%Edcu0op8DO6
znbo{0Gk#!HE^?#Tw5^f`&H-8*$+X0>(vW$2P1)h<x!A29b`8FPByquLW{NowX5j*j
z)ix(+HB-4fhZPIsG80g>FFwZ`DJ{I+=(Zdfz3FoP&EHy$8)%o4x=ygC1cMAIhA|}{
z3?dTb4<mfF=yq{jq%&N@#R6<6$!EiR`j<Uvu4Z8n6QMu}YR2`&RPzrj+HX?M8Ll>E
zKA(uiqc>}D77I;=NjrzERf;0h!mXu9MAIR41YX-BTG`Sm%YslkD{u#i2gYI-hTI6S
z<`Wky6$`PdgK|8?Ld5`uft@r4FVgLyk32o0aLSNO!%j6V3tz=?Y7EiTDhb0dz$6LW
zr@p&G9Mn8^1uf~K50Q|@$;7uD8sgxSN$P|N<5{uHobF_9sGx?#JThA5K&N12*%Q9P
zCH&lO&+4@J$Bo6_s)|IWrkd@(#}=~KVmM%*{gtali(oo1GzP72NL9=>aDhT$#|3j3
zKlsjgAbu^ttfG~{K7&b*d2c%$4546|)?@v7RsL*XX}Qmoo~nc%fHB*s3wL4IkA&+d
zhp(c6*rjwP)$yOpg6Og=d2pdpGl1cg-mA$V)I3i2q<Nh%?LOqdA}Ecd{4(9=kVCrB
z+Pn2t7;`iz)mtPcMMD@VsV~)bQgxr}&vQ=-4e&$~m_s)#tydIDGez&v8=ef@KwNku
zr(6#n8~d*GgzJ<<3j-Wq4hU0pH&6AV*%V0~(xsBIfz+g%(dPh_SWRjqo=%m*8T5u(
zkp9OE)_3aN1!OKxAQhfQEJ9R5DIzKQOe|k4eOJ5+`XDe~kJlp#e%Pc#)CyDrQ&vRP
zmR}`p5bOG9fAXqen9TvqgH%p|auvQSg3B|yuvIXEDPGr#j!wNZ>NqSNq<leA(2-Eg
zZS)7Ox@k+J%<M-kq4c?&@L!ZNN=_gAi3U8U-1A_nLrhzO`>>Yvpi2mZnM_FqP>;Jr
zMMZHKQ>TfnX2{UehQ+iFqqeTo+l(zHH;z`^3NV##e~77#uA{^@x`7}Oj4l>?#9mGC
zDVU3zwAtwv&tDqm??f3JI4x4OC<{+V>BSN=4Rz264mt&$7{f4Yy&J~fM<397`Xi8H
z_)p8E5L`WkBMKg-4iovL50yiQrG}704PxTiym(5Km-Z;g5Cb%o7**N^r_OKG1A|8(
zhFgPH$$%73y}?|;HLRuwITeRcI)`c)tWqYoB5oiJa%oCKMluDH8}&>@=-8Eq{)DUu
ziL9apZ9u9BgMmD^Q<N_6TIM69=vd^45Tz9&E@6c#aq30G=<h{?py+YU#VT=ix8Brr
zdSV`<YQz;uGtz;07^%?~`ILfEDbj!fO_niA5$zd*I#7(XS(I#6OBX3YVP1xP;6<k%
z+rbmE<TTpc%ZP_VD1g}{p(_<<X+t?O^*Pc@LJdwiP-LpXaxEm<MU$MB@9UcPbx$%R
z&hLckPW?C_m<bgb;}*LoRTrbEFsTZ$dsy|jT`HNxg|J7BO6F8y2v;>uIO{_9&5-Ju
zQ+ejqJPXGX5*}c+faAuLMyjw8h6C|&%dEic#)RuJg=-z+(N>s2Lp*8pJuJTeOZ1lC
z9Vd9&GAC#mz`hJfK5-1W(v3OBakp~k&4fOz{2rC?&u{}*Lj_69BuRrDMmqYFxIHXo
znpRlxs?l;534NnwaTK(!iZB{Ulcl2xBLNOItk~f67mv;-`2^<~H_<Q2;7;9TyecMP
zB{x?8h5(o5Wb`eV)T{1puHIYFYuxNKkK>o>*<*8tNkYcAOe_iv&J9tvQtD$5$c#{t
zTj~Gq)1!|y;+%L=1vf7)quruP9rLd{(VedTUcYmBnk@J%Qwf<9+%KniEkc{XGs2M(
zk9&vN7UN?U_4jtG>!$ZkktZpQCY=jp>vHq>P~xCdkCa{bnA$e#t84Yn7MaDNne|!&
zi@Uby`7%DufX0n>+YWgDRrtWwR^^7&0~a@4e7JA@&0n6UqoM<;46#@emzu=KEh)Ez
zK!sg#zGJRN)wKvRSx~{ED&3(P+&X0pIYuN~aemiG>KY4_QEbF7F;$e34wO-f)RGnV
zX#r<zQT}MhB2KvsUp#b4DT`NI*(Qmr4*TiOKW0g6jN*1j@Zbhg74xN`WGWQ*Se(if
z7?4c)mzW~vRRqH$YO@vI8Izq0Fh*XK5uX&_@OmC{@U`2|${o1EQx$hG6`m0m=lQP$
zH-H=Qb-CtTK2N_i*f8UwYm9B+8}uGg6<J2+VG8*${M%B*V+2ug1uzg1yrew<4DnTk
zB^+1*JDAR{XJj}&YT?rsd6G0{PvO9pTxxY-#j!G($f@w;6zv0j*Z86jXimCB%f$#7
zi7(DKtzu&H<ystTv@8`L=SW37Sn`R-U-YG3G6}js)pS`ZNtbNsm3ZZ;1e|b-HcSx0
zgs@fPG^%oiWW?n9#vfm;VUkwKP;~Ig@rOkdU>qs5u?A+k5te)|Xb74K&JHdBODLL5
z=E5mxj|fjtodHi+l9@5I6`6ZkbX|00-tLtNszKGPkMj8&1Lz5QCXJBtsS-ic-6Ah1
zqFCya2{}st=q8G%K9&TulvRXuGGovn6587!8?~iGO;4u=6Y2JW<hxolO^i?33dL-|
z(Z|tdjlx})dRWV%gjGQS0nl(<b82a^#!#l_j=0!$dUr|u@>auAp9n*&Ov-YcAInhy
ze=9ru2%Mj(4C7x))G0iWEVp3S@A3r+MDfT`@;EtMr{bknF<@dPhhIb>$dpCU>2D>j
zb*`g68@8Ot!&qp7MpznlxK1PCo|d(c<;n;8CT6i8DNj_pO!4vDKGE}~X=&j^0;dhu
z848X7yTJ-%KBbL$w=0L_`42;(OsW70B3wZd8n&JbX(e+eh=FAmb^4#cu(nJ0ihU#1
z_Z&OjaRoG3A863Fl<3&hcnCyQA+e!QF&w4z5_OR~q)58Q$Glj}0h+mL{>u#~I{JBh
zqPL}XF>jmg)k9a8LPM2kNMJw(8hps|4|Az?l)&H|%fGu5P0<qywMk-eUMG~(W!%6f
zM~2|Lh#%|j5JMdNv1akBF$4m!Q7g{8Vd-c1V+CMJ8d-kT*S~R9dv6rqT=0|CjZ)4;
zDqQogkYMQGPVnCe5e<b}9i~zuDa|LzZ8BI!$c%ciJko88mH+wcQjU<cgpY#QP7cFU
za5^V43`j|406I8cv}vabH0{s3;-WD5_)CUy88JY`WW}zr%%9RXvINRjt+Yo5>F4ix
zFKJ<O#+z@ZT_zu^-I{W6=0|>${Bu?hPV6`z*%WLFiY@uvB-i!4*))vF8ApHog`aX-
zTJ`;YbJJmED<65brHg}$#g&#i#B{K4crNU(xVJyzuju&pYobuSRDVHohU9$676<L7
zkNV4@)4#h_oIO(4ORZV=2KAdQ8$D^%j@I^Jr`y!`w{E}sf^&|6n&!5pb-PmF%I7}e
zJT$Maz3tE~$x!pg=4aw(ldk%2+wU#D=qFzM<HPsfzFhh8uygCDlBJLJ`@=82RP8OD
zGOa@&1J2)OCR&g59WURqKmKUV?YGZ2|5od@79Jj(iIzWbZM}3N{+;3CidB^z_9HLE
zSNGKIRo?^Na-#XSU(fuUZskhLgMD9B%TFBI^mI91v>*AMhek94`5ASqcgyzSdnx!+
zyNicgv+6|s4@a+F3U8zVzp&}^#r2G^GrRQc*Tj0^#xQJIwVWgh#oJ(zp-oPo@jz_m
zBDP#asa2yx2gW^Ae^RS_Xc#*dxT)}b(t)}*hQb=Nzr()$VZ-$71<TqRXHdWy88To5
z;;P{aS~u{X`N{V>`C)%}#!c|AD19j%Er-Mv!S5$`BN3c$m){CBi<}dMUIPEdWIEfG
zl&O}jFlHYrgLiRnK^|l(!@H32<W*Mw{S7Re!?{*o<(x*GOZ=tOhxWr(kThLYwSk+2
z#jqPZEO4vW`AMk>GUl|BTEal3g_VlaeT*3gwzZ%>g#}ZCM=W>zmS9m2!e<}n)aD0X
zjcRcuU?*^w?8;M*iwnyLR(U_i8p-GeAMg(|QBAp_9$3&N)-kL7V%3@30cWKneq{%X
zY`=-aL^a(ikl9Y#3MiW|D#1|h@CD(UlF7>bjL&St<Ru7zc0Loh);fpWstDPckHg04
zfBUi3$x0S~fn5$sM<4bZO>?AHqF-d%N&2|iaG56j3Z8z$9Yg}sf`nR`i<qo<C~#{H
zZ^GchdR$EN0oZ6c^%_?>*FV%Dwq-_<oFWL{Auxtqd@!4}$PuU<t9cXXMY@q<^QJ@A
z4=b8M)sjfn)F}NbRY|V!flrFMGvh`sqVp3nqL0fwpYDW&m`kh<PSvm2Vv2Q95cTKX
zDJ$BX)&#Fi_Z5$MzFGIuRBD!@r0&qU;hXPrqR9kPGs2J32wNUSaLlgpq;_`Kwiq&N
zeQ3WL@w;*(e#o>NP8=!e&?_uxr)$wv^mOw?zsiM!?x6dC9a3mQ^Mr{{7*s#h6UH{c
zZl${z1~O=b4SL<z5p%JA?#JHc-<!A*7Njs8xzmCzIC<aod)%ow_q5@<$E~U!yww)i
z#f%HiXQ$&_(T*gkaIN3tF|Kku(UL}@Xsf$TI~4&QLhALR=DwzP*c#LDN=+HJ4&CmQ
z><O(;-@AuOlO>UAqWvj!DoJ23k9r`?X{LfF!l3R|7%@piv)sy(wbM;K^Pn|hBlf0`
z*9J|!sl7_WQ@HgFFXGg7D*3vtdxLHTi~?2CjeTB)JAppV$ggN^ok0OjRQ_uEa1}Sf
zNTgaG?xqo8|7h9St}9`_?(6-m{E1!2Ut?y6bg{R?@7s5xblens_ARRxJ<{@vyNeY(
z{$i)sWtUA~Y!p~^WL>&DaOX{)u^P|;Xty6uz-NV@Te(?+P)uyxi202{f)2R%vx6-_
zRAdZe)#-D4lot)W)J&T7tEX9mXWYJAtGHwi#Wwbqu*ZFWCnzF(qtAs79&38cgs!us
z{fe&mPFK@gLJcdC_56wx_KNA@Z`Uio`$LDpAjR^=ZDt4xki>rm3yiYl_c0+0%QgN~
zu`4!S;iRVXX|IaMj8%00PQ^r}ri>M^vygc5yay*xW6ti>dCxGA9QxxhQn!9s3A`IV
zDiOnC*ca3H`?)~>6(7!SzwA0aUcrt0+!DPngmDpgd3(g#$Lp$|%X|IW_na<oC-Z#6
ztyD^0zt_Kyp7v0Tigid`FizBrz0eGL!ExK?_18UT@bvHgR*-WN6q@c%7{U46M1q`s
z5TuA+a9gUPdUIV`dCtwoyGhku-D&U9d(AI-TdnH7rgzSme23D#Zf~sgBjuf1_s2sz
zUr+WWRa-Q6m)q~r&;4%0rQIR3meEYkzGF03CG9ozq6w6@WS)BUeX{z%NRj!DGtOBi
zNJv6PU?G|E41=eVzq%>|lJp6B&<SOpm-#GJ@`j{iXc63&iac-w=`p&@I+g1`a_gjD
zh-1JgrMeXHCv*OknM`ySQ73afY<nnwcFs=}UbEjB&UJ6reUIw?WHjuW)71}nW@<S+
zG~{nxcr;e0jPG9;K9^L(zJ3cvv*)DQU+BK4`uA=+ZaSa$PxM!B`h^4GQ2*@nq5FZO
z>iKPE3~cOLvsrJi7EW2+b71JCK46>oXm6_-aBIEIQEMwKVaGLd!i~qZ-^(ax@=BI%
zb+F^c`f**Y42;^6{j@$_?K}0oUy97K($nst_*PlT)FXbY>sh6{hWz5}0j8;`*q@0L
z@+_%Rvp%QG_f+f03*Dct9`7HV3#S+LRx>!~e?iR*sjc?DLNA=u|6pKp>Zze4;f?WR
zwbIvpTvdDA$6nHtb2nb|IH5Y#xf^4^sr}{d$-)lR6UQg@DQ*4!D&3+hR-3#X0);E=
zH%@<&m}E%%{joJex>7a$<+-ZfrmJQ^o$hPSCy06~R`HAgcS&P1NpLi$RWg}?D0DHc
zfd5FS#G_`wj8-?B1|LIv)n{z;rQ{BO&!XxY_toCX<O>fP+cmzon|JloPu=^V+2QNn
zuc-aa+0knEol{9~(~SBbv;&~2i(2kWiRmc<79saq*C&&^)%qn*P8w#^%HKTMn<q7A
z0EDBq``F*Vsx&$`uMVO;qcZ{n&e^ULGaW^cy?@YpTK}<F4W|zI(=UuZsUAp1A1NLb
z^lG#HQ20O+f6JQI^myUs!tc$D8nZ<*%=X&RC;!1i#ciWow7OX@+K={+7C`WJJ+LtP
z=(YMFK;NEUD=+RUjp`ldf#%pu=gaC;t=3t!T?<1G*UEeM-4mN*`ahY`0#8@Jw|md=
z*4~$4b(=j{D8&Pdg)Ov>8Gr9Wp>xb`Rk~7^w7T7P2f(4-clD0eyfWouJ`XK|ja4e;
zZ~gYQ0r;eUP~}Hwe6_jVJ$X9h;o;<z&(_Hnf7)MA)4(DANYZmGw4=JLp4EF!8?$%p
zNxKwI`%N`IqoT3u^&n!S=KZ$xQZhPoo!NWR#9t{Nt39sFhs?n9PmZd>$*GRsW7>WA
zr;k-TI_DS(#UW6#UGp?OFRYrfT~xhncKV!oeMfYuZb=Ci3ngW(44Q%C+HA8Q8XBRO
z>iUR%N?#)=+$6(zItMVOY2qQ5xR}w|qVNH3biY3>SgrzyqJOS4Q!km(A;OmSoK`~v
z`}CsP;y-+wjmIA?mT2*w19rh~(VeBo%UkrrKdSfc8!Hc$PMXnju{B+i9`Q#kxZ2OZ
z-#T}j1vu~hR@szb`;NliNmDVk5*k!`*|_~p?`i$`P^DKl<K{8_xN0m8RZK`(s_6+}
zO6R%#bVKhkd%E`b12dc~ONdl)vx=}ISe734-Gd-oTT(D^rbtr#GyZsWvu#a(+^*EZ
z>1)i$&lmgE_@ioMX8I2bi!hGT!NI}JR*zJNrs`t_fHyq=8x>O;UAW#Jv#y}Gd+#*G
z_uDGmkEzlW%t#BGiz3$$hV+z|Z?b!^ZK&jirF~w1^J}{I2;lRWWlpzI{ir>?_h$p#
z<Si^>PUivk#Bw4&U`vS&njUsbCuZDE_W{Ahf#|N+C!2P3SD`+vzfxT&Oy~4L)j7OK
zUv(~+`~5vwQy(v@fql14YF$zX?5WVN>?t1!Tf4WY`@`umTc*%IEtj_yMnE!4bfGFN
zmIp_7U1v&P(*V~^*Od0vb+cYyRAE$Q<u|3rK|o)|3JLxEq8)VU7Ih4D>hcCoH~(ux
zDOQ6KHJt-j7OfebL2cl+q?k}!&fR{l=mUKov=!F9B$|4h&h@*-Z|XJ5j~8~`m-MP+
z?8)6|eP#CtjgKgoO{qS%YmXV5>8%=@^m-$q>Gz5~i`Ln0_S(_H_1f+?Pg`c4vX`&g
zNLQ_<WBds_FE~6Nhf^tgey>LQi{%k(u7CKwxQA1$bL=c6*n~!u0vHaZ9#@Y16~pPz
z__y7mrWu4c+0mK6?YyI0UiOIsJg$cZyy@}ere<9K0UhR#n*E92J481Q7x0%CL5+Vv
znaGXm9e$<vLF+tiVYOe>=rFi69gg<fK=c6UI^5fVhFBSS7`Jw>NH^BrXa57nn92{w
z2}XKS3`b_*secp9E(ucVcMZGKxn7Mn?Cu$ziC7qloqB9$u78uRIIZpX6`I}`K3z8T
z+mx#fu9_Q7c_U?}hWFPe3}%yrBH32&qP2A5fXhj>0xJ0;fQx?Geo;r<scdfzSeN1q
z=D;@&xvdDN?S3Di28OUP4%hR!MzVZJ9cC`jT{+vjAD`@iuh~l*9$qkA_=qiF%qf+4
z&tZkMm`C!D8@Nw)4u#Y8q$6@2pp;HeKQ}qkY|3uOzG1p(&>d)Y%<BPxVCQYs>F+Cp
zi2ApO^s}R%0OoS<{^EOnc9;m0BDxM1R;<Z_=T3vDV&%5(Z#hUW8lE$U)bNAGj{x*~
zr@Z1GuWNX2pYsKxE?@YON6bJxUS&IPT!%aSk!ttJrrTSXY(`V%QGdHEb~k-dYtwDL
z?Jb2yHDccjVvmUm1+Lb#9KoYm{+`>PqYBo~VYwUr=hl^XaL?-<Tu>Qc4z{rk7SDn~
zwYcUYo)JUB6{kaX%o}2k*7y@zy-b5GxnzSyK4e=|?%w^`zaod%2*+2<;#Cr>IL($N
zU<@-JQrG$Qq%{vX-xD@w#0;L8ONv1p;!=t4--u_}dDt1&hzA030YpmTP~%D*S^!yV
z1<mrJ@fF`v`twP$to0JHF}8Fh)U#ae#6z}DH-@`yc9gt6dt3ufP=&O_cWg~O>9CAL
zY<B}rSlppkZBFA_#6IpuF;K!q+sbEmlHtRpe798Mg!vR{i7*9BhqK+kPyE?M#M<zZ
zphIsnt-}V_2f?!6fPrR+APC3_-ik{*Xp<&WDIR9S*5~k%tmFLbU%`({bY4BuO<&|e
zJrGV5g8u|SI!?pl3HJ>7K0-NU@i<#Ogg++Lsd(A!L^ec>_<gx~ZFP$_b%V-G+8S8G
z@v5_A^SMAUuVXsx5h?@iLIij(kr$l)*Y9_h*mcTHy9oo_Z}}}XtK3!>82T(>!837)
zXYcQ{QyqD0m7mi|SB}`r(vccan`aN#mb8xKE!z?NA>%U_p-z(u41sA-^(WSzwC0GO
zK*D{Nt@N_jXn~W3fSXf`reTk2fw#lR(v#Qz0`r+}wEz`;N)s0IZqm~E&~4~PjMb8u
z_yN9o|B(>1FI0IXNn}E)lGt!3U{j@3&uzh}j+ifJtfwer5c3(277g-%zwTz!4q>Ja
za>FelSaIyN4fRg_>dWuecdMCr7}v_h-)!Y`32_d<H!##y^P~RBrhj8nj)xb`lv_!B
zy+n^ZOUH#<LKLqS&6wk=w%xz6^vQCGSR@_U`gl_FpJ0#`6E>TOcc^HTZm6)$gyr(%
z+TUhgG}aJ`XRV#`h?;16AZKjwmlh4kV2JuuIh4F-{@c5Kzg6&@$WKQ7sY$>VbcQa2
zjUK><>wpPoZL*+eO;V4CXO4x*WPx+_$s@DN+ti^&-B{Kk2-l+^F?eA$iXLFrCxj$a
z!;k1BtQE0daEDHsrm(cj256`2*BZ@5W4CFR{KkT*!L)5O6I<0aTWS`7jGCsLZ2Cm9
zDKG{VE4I)O8RQeHE0kRpbR&>)#~=f(8IFB7Y~h%BE!`Dg9X09Z#Ov}<`WA>!hh4&l
zT%rbVFfr(97%W@qR!W9BCoKu>4Qrt@tUvo9^a01NK^WgeDi944$0+r4?BgWI*$wQ=
z*~IC}B@<2GA8G+9frSaW*qCAyQgB4y3Wg=KAPzYV0AmT52|?K^c@)*ba%9F3Ka25g
zy_JJM+i+!_ZZVSD#6T}bH69=@8rtJked8SR{AzoG+ldlVjARE?5X=fFlvyaC`i3Xl
z*)lVin;i|*dI4z}GBRC1wfCyKvFV7O@zpRBwR31RVbbellan{%<|O>ajs9rvxWBvA
zQ#Q{xCsoT<!rc*@pG611RlB=eg?%}zBEK5qoF=_-&i2lXHFuW5i~5fYm3JB4?Gk?j
z6k(Y6*#L4Is_yNyVU0c7opgeh{h^9e3IE}(Q4XjIxCz_}j8R6Y12o|Skb|)@Pd4Vl
zgduU*PS-;#-O1>sAx_kPRC(cSOh>o2q%zwbp<j%8*Eh@{rmtRa0uwqrH71Dc4R=f+
z7`M*@1?q7>`YTtlqej&cy-c$Fm$<kzfNhVbMhG7D{6o8jcIfML3tX&%oo1E`l|#!4
z)XY?X?xUn*$)Ad6==-G6L1$11fEuEP!+D*TNx(&^=FL0_qFqk7^2H-km8@G0fi^+;
z&@6$!h$ONq(MHiE#aiGJ`&2$+sv!656@nnDITPhZ!b+!(kC&Z6J!uPycvT#7uXD_(
z>vVB<bkeY+9|L|GfF(@odNTnEb86)i#Gg2(cfY9&dgUSHwNm^T0bn9x=JtdGs(}J0
z=uXhlYM5m`JA~18IE-?MfQbQ2JBD%VIJ2OpQ)nEg4UhFsMl}n|fEyfPOi7V|`tzn@
zjc6#1ZY0NM_PLE%Ua$kk&LNHB67coizRQ&A4uCL59-9q%nB5IJrR?ddV1<6(Dh;!T
zG4xdT9meveLd!oycBiqQ3Cujl42O)d(q*+{*^Pk#C9c&_9vGYShh4d^lU^o*vjw)L
zSeCkhv!km?fXLlYZs@o2{%~yFXqa`I`JRzam(Z9&uT`A(L;!}dRS`Kvj9%<Xrv`$O
zuY0~lD*YW!#7fQL#F$@ZpQ!GckN$M35p2CANq#tV>2k_J3O!S9cYJl<vfdqe#gQh^
z{+#_X*p=Tqr+Y{3bjMcJ%k$;9V+hCSlbWTOLe%|+vCRfU<mKsR)QJX@fH0A=%vQ!L
zSvO#SE!pV655=sOUGB6*1(JnVGIfzLEGTObW8e<}*m@!Rq~!Mf{yFK)I`wEUZ>)$r
zOlRFwm9DzmTOYoyUe~SyPzBEIkKM@I!hRHm(&-|jfJ)`cajNLmp&d>_7><f-im_5)
z<-IoPdQ?r}T=<_#y4_Cy1bEt`bLye%{IEL#VoUyEb@s&69O26+nuP=US@5?b=1cm6
zVX|4*Hk+fxh0Y^>*9qK{a&n?HXTts?o4dYU7`RXWx_ziT+WfNKY<eH5ZZ(DH_kxPB
z2yZX@TdgfWZf;QbnB#V*Edx8&w(CK|pct{Xf6`*`>smj_p;H248JskOMmK-Yx;I#(
z_m}&ap|)3hPX2OE7w=Z#iNu{d+^q_6F6mhY3qP#%gD&lwB$}<|cO{Dw^4FD|R`#G)
z_v_B@sPKj%@BQGsU)FukC*>2{Ec=scdjaTC^~R&sXqVZ(D=ZG}8S@`IVz!j~ey?_9
zX!rD3m`oq*U*0x7WY~WzGN?Cm^Lp^rp%2g+v)^jQ@PsMdW9^-`(q~T^?9Wj<2oyHP
zHmLoY^~*rq_D+LE(!0oRMfr&BZPrigUk&0k`VS|tn^hj%F~uC)z@y-e02RPna}xDd
z#HTvyk5=)jR*^&i!Y$$Si89{=%3FK_CKeK~M375h$P`sP*&Omg82cXKbLd7tg)7Gd
zd?X;z*j3mu&D(|)Q(Q5mH)>TpvXY1A#s-Igjc0z4r~C9{fD)a#g91Pn)XXT6Zs03(
zgd%RKJuFyD=_Bs8QSg;p&C$n3=dMeG5&w%m23q&f4zu@VfS1Ap&HBfOb{z}HW-B+y
z)1BV|L9q`k9AIN@+ovBeqc;JH{dUOPeorEaUpi`!)j+zYZqTR08mOeYxp1;sFCD9X
z3m9^o_YFtqq-0|@ZQBo6Sq8!k<8PIpASpg(1y_uJ#oCvQyB8m!cX8Li9j1I*6Vz5e
zRy}FV6Sn^eMNHt{(+}y&jwc2>I6r7d76pvzJyt#T0`TG7VSkDpo_G{~T7epWWFF|0
zuqc>s35Yx{&|Y`Qdv85sGqa=R?^X{qkN88~FN2r%Et2<+CvUd;`I%TSu6^T28u7<}
z&7q-ldy>c1N*P@BwC{7=5gr1=cwp*|89^EM-D$TeM-j-_d)k<R$5rpq@*?=389?1|
z@e`WoMOC}E?rAWOMXDdL@ffhki-uxKOkK@-o%`icYd(6a1MvUQO9^{oBWeqiKn{Ge
z^ZW7gU4MG`R$kDYBd+lkKr5qO()Q(Kv`~!3c2Og+o|zsW>U^Bow9%Oz=Ea54qsD(?
z`Uhxq_)G9K1W&!AGp)`$^i=(t8wwqj%Dj4rFv~@@v5xD`PuqoEgYlTwgRy`&7{AMm
zNLw-0y@GW5l|i6X7pT}5s3(Pa9#<91zNwLyJfC`Elb?@2ndD<YG33woh%?e%)YCq%
zu>!&eGEi*7uzJwnb4Ou%JgjUV5>Rkt=4o@R3f4Uv+~be!-IIW=s73We@3*ZHuuhN6
z98|r!FkCvlYp4aVwZ*TL1&bR|!Kg(;#+b9aK=~GTfnhJI!C01Z0Zk+8!fMJiSZih8
zI#z&X@C_?UcGN!qC!P<2*Oe>gQ4W}97(ePDzl0cE<ej3voo0?mO5ot|;I8{io%>FO
z;S*0=Jv=60b^QINzd1T9h*s}7{X6!g(Z4V{H2_>&xt^gAmf~aP2q0u(t9oE+-^Z=<
z@ZR#?so1q$V?*x;Zz&R<3Q#t0U@+~YiitGpzmFCW-P*y{BSEO?O_VA?Rho;1K_=#J
z?CH?XET(s&I(aP%F!f>7V|u*XNv3nr_*^6QUr<f<GLF?g4e&eU>^WvYP_-U6d&*#a
zV7mjx0bm~TA1)XVWPEyfth_T!ire9|qt}}r29qS3DIBR11bhd6JfM5SqXV3stJ>_9
zSxb@Yi@?%N#x7>GEp_xBu^-*)@#<yQXM8`7{c+-zTSTd_XG6#rDCyJK((WuL4KOn>
z?s9!hfv?XXWb*+pQ6Okv__*?)c=+n)o*bR(O}t{~iJAJiD(r7g*Y7Aqb&Wk0xnWoR
zXu0W$;+8Q+>)sMpkW+S9ZBbV30sRlgo`9r#>vc<y^m_BkdG+S2Tlo_+D)-!sqJ#6p
zNj(QwkL&|q8=1NP5JN4&jB!S)szwAU(U0+@jdC}E@Qr>><zM)t+}-|oP1#m)qM4`=
z`zp%yPU+!MEH7{}ZBClyR=20;?L^`@y^Gebu#=r2H|rm+vs@UbjieDog78-SzXlYJ
zw}$^CVGN!GdTx*LVUp$PhEa(H*q6;j=a5kcs!2SYXy$@hX3I^pDyQ{-^D&GIUdt4>
z02D6ODoZM<6ifSt6M_cn0X=qm4M@P4TC1^Gb>^`;qNM2t42`QIeBA9V;94gdZrUk#
zW$X7(v?J-6H+>M<8qu85xZmHJWFIbiVHgt>2sv-OUZN)w6L!(`JCo#t7IA<hj_f7V
zSk7<tb_~SB9Rq6Ib~n{<M=RMK=EuttC~AQqo94tl1kg0Ru5mmtS;E}jX4&nX>Ua(Z
z+yzY4Ch&f2Mix#0$ChzMY|r!8oh>l*bAJiHQ+q?cB0PJWbnNvn=6>qmVv!1Aou+P5
z0B*<IRd}ruUqy5Y#&5EkM>0V*2X#x&Ui(OGWwDYaN5gfZQ;&XnwZPZ%aDsK-He=T&
zzIGl+p_FkJTKS$&J4O6XBF-j~Sricruxkdscn1SVZ~(9aPpe@UjK7l_G`qAC!PfVz
zU($dl(~CMBSYXMq;bChNG|%x5u{Z3~78?@XY3*S`C4h2pOgtbRdHvE7E<;2E?lm|L
zgecTqhrA`4IB|q2RALAkNDC>6S9cKfUOQ@{DeRMuzW}Rs9S+%Kc0q>$I1X=r0K&P>
z>;Y3FTAk<Xb3;yKK`7;(BTkxaxIx(%JRs}xpDEP&J6(<nKsA9O@XWX$r#NGeaWRG+
z9m=Gki72xKLRfdUqesIQHcMT(eNCV#4@}bw?48Z@g(yML#DoVNp{@8e%?<=Z+?&|G
zPC8>-L5sop=VAHl-~ZmcyA$Z(kOz7JYJkk?rY0|@(O=q`D!7TNfY}mQIGke=BM<Md
zwi+F#f3m<nnIj%M$RG;=0RzNC5l;)Isr{-CMj`G23PzC#8e<w0)$u3Lz}T}dK6w><
z0!#@+B$}1%^rI(5vI<}o=YNXKc0yu;oz|4V48?}dC2B`^Fl4|I2i%rD9KsHhT|LMA
zi{DBxhoCp}8ZdQ`04;E&ae9_S1cFF-!_{w`KKKAWE7c^k%~8SMBerwgDL1jab(hE3
zM)A6Gv)Z+)3#ct|qi4HO2)3?xkySsS>NkOi>^f$L)E2tIn-DIDxv2R))mo#fsx(C{
znSR29Y;^#^;LTSkC1BXWLJ$*PNKB$VV&)A!<Gi|s)y9}1LbN~)r{-i^PUnZ8#r*^;
zOr~AiGgk{b4joX#!^B!X68blqj-BEhUKe&vCR28<w39HvN!1ye1wCR0=JeF03R_e4
zIJZqd=K7WH6G?|CLcdAAX1mN(M^NTf2}9uH5qlc|FTGpx@Zu!!|8Y=p3mV)kF90eU
z_cn8SikG@jYk_$AbXquX(Tq!!biob0Xu*If8TtsArw>e8fnKKXPVnL=QQDuJa?r?%
zbV9&D;JsfdgneOZX;yfQXP4omNi?^NHns&8(GPE>`G?fSaF94SfCv0)Bq(ox+NB!2
zv=W`bf$d0`IoNmmlyUqiYZTK4`v7cJfcy00cCrjH2o_Dl1#D&#Suny19N3`4k-%38
zXXDZ_pd>-ZtKUOlpCXcn$&4Dwm_)84Fe3SunF5^F>=6U3cARZ>0uL3_YSioi`eJ}D
z$xednKSrw}FGzp`DwuK7?Dlp|Kt)Uo;4EH+Z5}|gAGZJgmx_^@Q&dtcu%tU6D<i(s
zV#84-EY-%dQH~d|gCY4|BlcVvdWqNRyR&7CLB7E!ajJvO_z~Np(8oLzxgpRRtt?YI
z>{Fs2;l={pGAL~y%R9X-9b!OHSGNDtyvgN3MZiCu&RjQkZUS;vn8Q~D-wOr&xKGy}
zV#ag)*=GIOq1KJ=bfR<R$t0T53W(Ybj(2w-ABqw+JBorFH2!8iZCoPU)ty*hD09Pf
z&<>~aBAcp9Rp1gqZX+)Q5D~0p$wtR@Ww-tO_DwKBJxDaiN!PR8T+gEQVbz4nAJPV7
zVA$W!ONvLz_iJU|ubJwL#%SN<o5!{7RhS93E}$$3yB%vXXemg7Ynh80Ojg8^<re|U
zMFl1Rxp;0-=bN@EbJfZ(pL9l&DEE*+TEd1(=x*#tv!8btWA+mYk5nC8S9W87a&E1u
zo_Zl3Pb#g4@?NjUrpTeu#bWRCAnBDYggRQs-&*xUA{w^qp8BNTL#AFkW-Z}UfQo2?
zW(vl<8Ax2&^RVtt35VhZ@W$zve-ot7A0GGfSBt3}OrjwTV6R+pVvgNsurgZKqsG}!
zYZ1F_D-8hr5xeA@#{MQVmA5l2*VQMHOy4Jo3ut)7Vi@e#>~a)sUt(!rfHlYpW$Vql
z*VUY~7|OiFT#^t^KjK5S9NfEp<-H)Qyzzr7MealLjZs02E9wAD$$H-stu%ow*{vX9
z#zb>lfl;1g@K0Ow#&ivXlQ|QZZ!yyL3|)mvQ&%HFL#>yFLxL{D40oTIdp9<(W(4py
z2p{=e5n!Fo>|9UGio^<+<Z~6K41=jWb(~o~Z;#_NTm$T$H<T8*c`x$xi%sJRi}KPi
zAfH3f<|MTezd6BSNvwy4%b);7kBBdIot0ntFZ0xgl~fdY%OWTmz=9H)`hxB?RUM5b
zy$tNpW{-zV9%=>k4zr^B^>(9sysnN`zZWUb(C!Y|9pX_hGNuD%gD)CQ&!UUKje+*c
zZo><jh!NgyzTw?8lPal=leq>)0G0-D5h-{3&A4!@n{?7k1A@l$H9Sq!U|)RPJW;57
zgf>mbw_V+d1JJ^!=y3Xsozunsc+y7nYh}VnsR)y*mZXM8JyksW+`zl;C5n+~fr9#!
z>YgN=AX)0}jv4=RbJr#hE~_5({eGu^Yy8sOenkZIA^nOTNPeB!plf`p_omv`X8+jY
z)IFuDf5XC&+EhGhx_(tZUrkQzo$LOf?i<~^qRX502dlgPp?&nU^^bm8ci*F4&=1<~
z2dlGp*uLh`@I?8fo*N3)jdNx5!D_Ahbir1)0#=1v%T<Bus?4nW87<Z)%<+Uh2~OTo
zBM`9Cco|c0hwiiGm#ul8Ey}*8d~UUO-LlCa@$bWh>(2RyyO&tmlUBF-13xzE*3Ymd
zxTGGMyYZ81v+3ET?pJE-SGw;hHFfiV{ukQzdpp!Wu*L4<=Gtc8xGBz7)&1p%zPs6b
zy#LFE;_mMKy6c!<9V*)+er5W^-fFmgVBn}tPK00Uo_$=~9$T-P_nZEg%pzOOdIt_U
zD`{A=0HGkLmC}A&>+>prvvwCg_n;lMU3SvizT=>e$E#|G4heMTk-MIMUujq^15d5S
zIAVFe4mGYhlYQ=Zj+n(M(7|@h;!9KQIL8z?Bw)?&#-oxD$1T3#jA_v0>uBSeNXM-L
zUC2|w7JxF~jhn#})6eo75Jmc@R=wLc7tC`OZ>+KEk)>|g+K(gVuI}$D#lu5H15T(`
z{(w5_tNxQ}uI7|p0x}#vs{aHC@%z=zL#^9$rO`*P*T-rdo#0qI!Yw7RLXeV**{t^7
z(Z8Zq(g_v`>UZGQQ^xfFu$lf-0J(2HR(kkP?H9oN9+HQNL!7%=pY{ou9If80!6~0C
zZsTp_*<L{nM~6t#FPj5^fr2;k#%=RJYpi^8{T~xYH*h2z#D88a6Vp`{2c3XMWwxv6
zw6)uIRq6xB>~HB_Af{d4)8Bit{-hlwXy+gx%oF9ssy5ZX`YCy7c-aR)RfIkkuVc?*
zUa{#uuO0^Mf}>f2>K;}^unCqpfY~&3U($KBdXjaEK*?FROypqgtF!~zC(8N4ui3>a
z@B(n)9Z&w!sj|U(7WAk_4ZGC9aevQAs+-<x!7^(^jV<nq;-o%S-C=y+5FYljAc?di
zjU^<$NYI>U%$ktylkZ>K4-?H~)b=;oA_D0K-<veO&C@@j07MP~mllf&@nC{y<@g{d
zk{5@E%>jR$?+8fbZCqz>$J5|g5}j%QLcQHLsF$YpX^9ZKu8bBDySn0+7WOPya9G01
z#(uhQfoN2<RhRCV;buY@-q8JiYp2BS-KmKfEGjyI!gQB@+}41}=#N37G)wg{AW6*o
zS{@7H28)Q0D?!enW`r7kO#|!jT07g`T;BD!-do}g>=q(d62(?5WKE!1o!tpI&();^
zeopaDFfUy@MCygT3$~SX9xJHvC(VlQ?`ALz`7J{6DC9wrZI?zb!|Cxyx)IkA^P$@G
zc=-nHwf5{|jXr`&h6SkDS}2s0cxus<ko~~2gg90u%FHuC2N>RwRPwA0dkuW<1*q>|
zEL0BLy>8L`;;r(AGqDYwD#xqzC3cubXLt>|^Hz5@mWbK$8L)NTdB7|vXNNfmHrP3)
zf#<Y3xGSmb^pmZGX!6oc{4&7o^vA<%CDe4PA6}Gtd>2Y{r#@((=scx|h`?<U)Te7c
z-%7TK)*5#Yfu&9ZtR4uOKs`bb&A<W!UF#L%5HQvUr7vh7Y=dg1GOv^^p|}J0eC>U_
zLrokUVVemn*A!CsTj0EN2$)D&cFaodb!GqrceJo0oc{RG(1-kKt&jT;kL_a2%z7h4
zNR~#A%&W>5hKLL7EYx4|OPy1M2JQmw9)Gfz@V=Ikh`|?$DOoflW#W|!k+=6H!x#)B
z`cS?Ij*!De)>dZK0dG)wr7|~D8G9w9{p#o5ohSO0H@gWa)UD~<i^=GtEE8xr_!*cV
zftqg6e4HG}*6-a%PwdjPLr?!*voJ)6<UzHkBl51*VRCfO0#f}-*#lo6A{fy-6yJ74
z`<-7YH<_}NdOc2zDkS@u%IW!d3>%};@A1bw_?GwCt!%Q1aZv$8J;Dm%u5{lN<>VC&
z0A{8Sq70|mVSG++0&QGsF(8X}i{CieG%=9>Sk?6TKzXACv8!DFrY-)0Q`vqWfqzcR
zm{yX<Zepv07g%wIZ>o6UB1`x2-3FLutp8LyqN$QEUFqKx0fyY33zTPD29w3C{KS0`
z))v+?5QHF)jv#%T*z}z`aqF;gRS2dWEwDl7?5Jtp)gR@ZyXa~h@b}l}mFe-Omha~a
zj2g}T$zirJ8cmsmYEKkPi@Ip5ezCvL#()z)7Gi$403pO6s!BDyHF}j}2=NTVyaffN
z$@ZDwx%%E=yg$CTp{QEOq)Sc@6X=*I|G8maHc1qaVzR#(6_)*^9l>~K@?6>0hv(|i
zc&*`Xzc<*Qe4&sK=|~B^X|_2;v^#7idpzf+O>B%U>gUG%1z<&w)sYXExJFD6Cxsqa
z+z!_VFlVjaelJdbr9qx1Gqf#!bI(=pu(#5`{Z>D6n1PRLeiiVkznyF1aMQ`DZ7bIF
zYlJ;Ysw7DS5kW!iTsZgvFH>To;tqh<;Nv*B)MQDG@jy<5qEr9lSo`d)J_D2Gf2&;7
zv2yZ5jaeXrVv-+HEu2_t!_~*lOXQ`6>uUN&w`wB-*LsqUP&btCwTSOKWXcPC8)KL8
z>><}ip%`N!6F;yI5n+?boDS?VL0A@Fl)rk@7WnR(5XW%dlq@h4-=$4Bl252lvuT!X
z1MS<wqV3cQrx(6~d>SqgOP31{kctooG(VXfR`a-xHt&aC5wEpHG)=1k7@G5mh2iZ$
zFe<-6Xu=d{NV4@<!T>Y4w=}eNqjjygNL8Q@+;AjMWRn*xgNAr?1z&RF-t{-%$L=Vw
z9Ph8?L=+PV(nxSU8*XD)n0_&v*Eiz^M0=0~Xa^eU5J8tXm4+Ig>u(U?)e7QAKr@2o
zkkL4LfhjW;0(XXu<HXK^I5`btVQdG_!jJ)?;H^*Q@6-QoDj+^D$Cpp`BOf&gzyT$^
z4;bhlZU!f{IZ<z_8NRzxCpxIJ@xfeLo$}N)k#*L6QLE;%jdG#0wMhUG@dkVi9YHRI
zcy4II07r)Sy<l=>+tI)clh<$oZI})D;<mcW*=_N0+c@>BpL7J{0*;Yy0I3yQ``oTv
z^_EuGCI?J&%8grr-jo0*I)Def-neLzU_p%j$c<d0RCf^mGS}md3^aKE4v_Y+ep=)9
z8ZW3b>uDedUfb+<9q<R24q%jMP(q-2J!8N1o3{tX#6V6h;+cwQfu4w4w@f7SCe9Q4
zvs9@P0JE&;%`zCT-8bWgeLi2@(R|P^H5YU@4oR(>7$|G}zTs2Y1ocrf6?=y@t}|ag
zB%X)qJ_0(nh_+6cz^(Dlt97cSIz8g{qo#(PUN3NM*s}oYnLJ($XPeE_Q@1zF3IC|l
zkMLqE!pU<C6A;R|KC|raBPfN))I*7JyA3ZNPc{iq>R<M&`_yL&f0Q(rOYwwyqQ|_{
zjA!O}@wTg_pQYCBNrQ6o26bOp7=A<{<idif&g<^vI4@O04{BxvV1MvJr}kq>VvJku
zn>mU!tN0!_Hj^n2JO!VTP{7(mYvrH(-@HUwIL@$zZULy{b&SB>mk_&w;H@9vKcf;{
zB>}txu}!g6ng)^aYA0|NgAhl#v0u?C0e$KWfM2l9>h*bi!4J>P1HEH!1Wi+5e!)wT
zk#wkX>Y0`!Z`#OA#YQ*vf~3g|*Rruh7$&2RX@$2esnEG4QvSY0rVhTcIwprEe#$hw
z?Tp-{2y$frrGPITG#l(J<Y5PR2HcD}hF*a?hNWp(+XN+lKrvne5Se`3Ub(@oYG9M`
z)yxW*0PGF`D2z0d$YWd4afpWEef&bRBSPI7(sZ=E;LXse$g9PaPSKQqBdQLRP751}
z_3(}>TvwjC|LQ15)HG`{88H%uF<e5%QNE^@eCHPZG3QoS#pc7^mT&CZZ;BFfX`O|9
zjJvyxZ?Y3`H#yGhkw70|7n{9PMu2j@;!vhsW_(tK$jk4y6J=h_CK?XJMv%I}W*G>P
z3G?Y!KN5e+f2hb_WRDx+*pClKACBWu|Dg}Z?hnR_E#-V}7Mydc9v5%By`^Vp0~-hM
zjGz&vd^KmW(m3v``wcG&n$3LDN~fU!jkt@-HwjE@dJ}eus+nJdWu0P261WJeT|Quk
z>^Fzs-9Wzbj`ou1+F}0|-}!Lv!+fdFvxFkLJ;zo4fR4KhW2N3|u>#68%5KWO*)hL2
z{#tkOdUlGn=l74<sBWv}A`^L~6}D=vg%*$?6E>lr-5uE807sNg1THL!ZqWc@vqVtN
zUB7&d2C$^+DA(GjJ{JGxAve~)c^FAbV~K{<M2kesx{t~m1w;z-ijKUnQi)I_+nJ->
z-n#yzY3<Nc$@7br7e$)xPQ|NcPO-OcJGL6EMo>AYY}o$*r<fGwLll-*fstm#H-5k8
zJhgm#9J3wVlemw`&j2J$4{q`9BGBj$#x4Pa`Az$n6d7ZJ>w-lEhJI}{=jcL&%Zdup
z*wFuc=uq7gg=0Ap5+IKigvC+jN7_p=vS9hLr$77~4#2WNlYX>G^Q9#+BogPA&KUxz
zaj^(5?zQ!>>gV@20rn~F|0nHjz~j2k`_6kWAQ^TPXU>@!@B#$MIp@v{2O#({7bFEy
zRyFrxKtVQLV+No?r)on$qN{e3S^)htX*Ox*4hAM@Q4s-A8@cP$1Vp9U^uq$}<Z+X>
zCLk%6Q>PIir&XG6EmG+w&1N5yP_|XlCf?sWAY&)ZrrT#n6bJ%$?wtFc_q-qf^MBt{
z`M`KH1xbLObNoJawFFzutt<w<O<51_w`&}jwJvh^^==EKz78jxX&ZI`jQxD28DRiu
z>*pI_L$0`){zX2rHO@vsX3dW-X0mM7s01)yIzIEm#5o;RI;)jVl*<VoQ^+j`6bkp8
zRma1D^%+ABfY#^Jp2>$SK%OFxMe?k{{WLoQWSnFEK^S=S9GfElXh9^y{^s}?N0d~@
zTI%tnQXQ-MsxuWO^q=?BYRx7`eAs}&x^I*jZ|*?VK(9OgQKG!8SLkBSo8G)fd05NI
zx12!{t)_sz5wBV2w1t~HEFa=H1PQVw!!F@z)4;O;{ob1S_xyqb1Bk(;y8=Z3ofla?
zniv6^tvgTqD8N>jn$e8%sQUknQdwQl5$3|SJKQ>{FKb+2s}Yx|j%XxH+?|S|TyqiO
zqvpmeF`UaXV-2xIq!D6wzWrGQI-it#GV^Ztl$wt|l$k60-JkRO*5pt3Pxyy-eN{cW
z(VAMk^!>?sQ})BmNXN&PqJ6VFUbopNrhBGl&#7l@^n}s+pq|km9(xJ3DZEvRe#IB+
zZ!k1G&t9_MSPS0J>Az!tGug5|Ju~`LbAM08|3#aSN!wRI@TQFqd2k)Q*&n`alRzzn
z{cJl-qh&#JNDs`|6>WSp&xEFz8pkqQx8j}hx_>Af-e>&6tzY?()0C2z)qJ_9Pfaam
zx<9`5bf)@H@>TWh)JFELOX{OD>e0T5nZCtc>BXMzzp=QOnID~s=57tD!w<cX?2TJ5
z9`=v^h(Bd@x1G`J>6Xo%C60uZd0|F3S8X(+e$0Lxj&+dKZO_v1Ir|jgsDD5|T{b(C
zeBK|XEK)D)G(6{>#vYK^L$)9Cyh`~4ns}faT<R!5rVatyN1E&k1k;9%_<(gWyxRiD
zCNp;H6TdCh*icb2>F9ZQjqFxtAco9m=kI(uIqE-@fLQ_@Jx_cP39bq4v6Y;87Ao5*
zd>S@~ixs~3#kA1ELN#D&0$JWh6G3;OL^dCrTWoVElRv|A>{&^F2X>@bmR)_ABOO3E
ze*r=XC^MxBSIyRcc-P7LumORF-0_9XZs?I4#mCj~+USd9x&Nj$Ne{(ef4E>i-t%Z_
zCNudOu*zztc4>!xX0Dv6?M<I+epFBWB^738t$>UZ<-K9B<?C}?v2S9xUf!$2U+b@#
z11->s+WjDqZItqUDb}qG-4BA8&t4t+;_$@6+ptHU6R;6V7ieSn+ki2kE3LXc&>9#K
zZs1eaFZ?2i7?q&{#%x0}*?3dCG$-0e?XA4+6GpgUBV7mMm%<7p%Hg?Mv&|zscH?L6
z?u|aK&Lz|Ur=z!EfbL`h?g7?&t~Lp7S?iIy=N2f_!(8TnG?ReZtY*}wh}dfRGiJ7Q
zDj)6CPqA40P0b8}{(we7`$6CRBcVAK)t|lnTwst)#9yMeAv~CVw^Vv=z^?iuz@Gcc
zpmZU`JOCRRCot1WC<H=)RB2t9r+yhD?Cs@wfG7l{1dxL73GNDfhS0!E2B3E~H?tqa
z!mvN4fK^j!%)f$bdvw%4UsKgyD0|R~D=wwnR2x@YE9LILR^MeP{N4TgN(wL`3YK>f
z(LDDXN;r@|znNYEP`haCU~S+slHIa~u@#o7BGyM&{V2A}>hOc%3c(=t)-X10ULKn-
z-XJxr?Y5OXQX>KGIJQD($YblIesOF`GFFEC0#r^aANJW_`}p@fnW!26C4r&l$D->X
zW)#ei-nHA$PQt1h8(juUgR^&`Hn~F&S0{Iw;itO`^XsMR=w^B@24+fau+dT3P|X#U
zzmGC%LuEX`?Joub&s{Z?T$gE%cx0)(dl*_C1@s4ruAH!&F@x-Z+<`~+d+3liK&8Wq
ztz6X|sjJ#VjL~bLR!G=)K%F~eGP-qh1y=Ih*8g$eWd$LRl|nlk|CVB%;4|iXAVOv{
zZg1`NQ9~Y((O+GA?mX|PzU)6{vfXbk#PxU|4Z;dnHE?Y9S?fOs;s$5-IS<&Dvl(7c
zS3vVrKC7ftfeM=O4;U)1KM=Utc%|GM84yw&XCZk(UEGEtu}cC_=5596ck{(iT1yVP
z28fb}YYL1GyiLK>&A)b?Av@<1r$q#mL=@S7tr4B-siB+a8;kxW<^O7C(fT8<y`ZX7
zRJ!MH2C5P-X+c?uEz(VODjaIM`5_QQ+5#MLg~_{Q?Kpd`R9RP`{=>zaHb<y1R)z(b
zgUJi(C}czjh^=7Vi&nV349VoCO~Dfo6H34}S;1T8ZwcgkE}8FwE6jcYNdkbo77}FT
z6a>y0-v^kSKlM>y^WB+~ubN{MzjN|ZFi?Mea$k9XqHyaTz7Lf2JnNKp2m|}gz$-fY
ziYf8#w~bqd1H98#PNjFI{VP;)yZg$tH`VZrhYD_<>jvEX<soPbgxf5L-VvBYZXPe*
z9n(w~<3lWTjTQ<`2CldM@b@X5S!jd16(Ewe$x`wfLq3)HJ1w_XePdzmY1Se8M)g-m
zSB<S#`Ff*Sdo{a4YoSx&aOFBFcx&IZ<#B(>*m%9g&|<GL7Sok8<ByjG*A08pJa^!6
zYK+xKlu0(umhefJRjc4tG|}4S@-esY0u0rrD>TNE)j!llvny(wy<Fsd{wF}2RYF?>
z7^<ygvR9wV<V<wwxb~xJuUVUCaaC(+$jS*pMIqmu7>jnMdpk0Mh6b_!{B-FlwJhb<
z6iB=9H7~e1*EFE8LP1FMm<O2?mQT~W)@lSo*zRgf8KP0+P!!HyEjTHm%!!2+I+%D@
z2<sY~f9HFs)n@bBy#T|ad#uX7J6uVMwSiSBx^Fe4jv#sz4?5#lK_|yU663;L5UDxB
z>HAtH0=s-`78?;d2*FmGH&9ASNGZckjR`n8Z3&q+rWZUysOd!D%Y1{yAQwnf<@SHt
z<$Zvc4M5D(2?Q+ueNf%=KMY-7Ep1meKc#nH_}1|6N2P)5(R)8NvNM0ce<phG(|l8W
z&u@JaBI9FoPq#k#(wCyCxu@rUvh=gv-EW<GZ{Ge*-u~6UG6=@{k4O0H`da(VfALL9
zf8kB`|M@qWxIL2l+9SF2$^Jk8Ci}m8B=LvYAZ>jM40HQw;tyZ_srNMrJ4qYJf^%z`
z$Vp|o93Xmr6ggE1!R3_$4j_1LOp}1n-MK=0Yv)><OT#ZE_a|X#kZ-qf0Lfo?iwkMN
zDSi8AKPdl_SNpo{Z~uE=b6$?mBX{^SubaR3<ChayB#iKNKYIzv+#*}um4yWROwyRq
zJ?@D`sV!g6?=BTvUgNQvO<Jj!%wd&VyDz=2{i6@4URyV%^g4wz!yyI2keANea!Fs&
zZ}@E(Z%E~V_UG)9rS(#2u){C)>!y`{P>iPWg0a@gk+GN@v1Es)G_=(7pR#`!{X|HO
zvcCbFrj>JHGy)S{q*}|Vo`=_@zvNHHIeb*n?@BI=(9diQZkVBDcBBiIm>=>MgiV_+
z`eH@>9TZVg)9dX3?jbqAS>>6eHmJs_0F(>okoBN<h>T*+y=)pc@>^f{I0zEhSJEPH
zf>okZ?@xRkF=khYRW3jpQ)3@ey&j*GQOPxx_4K34g-;Z#vQdL0WT5tqCh)*H>$7A%
zcqpa4W#^jFMb9v&PzVqNeQevaJBU(*Ij_=mbFQTZuk+?F@8Gkloz6I=^Ih|;s5AAo
z4B6r27*$X-$+=b<i58NkJ2yv8@@nZs!uC_KivuhC;ocC_GGL}`PIpNcwPexI4=?o7
z>m-!1aY>KzsSX+&>u?~k{MSrkt4Kix(S`=<LiU)DYC3k1DYd0H&U7+c2@(acZMc=b
z=RuX7b2uNzp$NHE85`?zBLC%*+x>cfg@cWe+r#u$%*DX29{SZ$Y9*Df{S*ZVmcrxQ
zQN^63YdH%%Ar-42Mv0`4xh?z88AQZKB5Y^ArS5Saj(*(Fj9qX~ufd_4Tgn_Ng{cJ_
zU(lCI)e}~I8LrpZ`$w9|3J9-L>V7Y;ua)LJoB6nxp<`uFdSS@uQtOQYw3=)+6-*_d
zB4GoZga6Dm&_j?_hQr!Rpa~ThyoSid%Mk-NR4MIKLZ0|!?XNCoTFGfP-~9{G6S1GV
zF9Wu&GQ*XzjDIR)GmHLktNTNKFs%k>)T^bZGu?@q2}|C9Y1YQ<*Jy%P_D5Dri?B*d
z=cndi!Ok_|0ozwtX-S#nNjs(ym?kwa5R9)F2sAF~e|Iym$zpF~IzV4_gS|sG$OhbN
zrP5c{?_zQk`~O-+K7ot#tP$G*jMu7w33nw)#Q6;uRnD!r)f`>&oRM<Lrt+#2P?<?%
z&m^JI0L;;*2dK(8%%biGcyG8C2$DlrDs4Q8wL_tZ!FycQHo>)(Zmtgt*dR8p;*U*|
z;k(q9j>&G@6A{O(h|$CBop+Pgd71;5a{5Ai%J>%tO4LHCE=ouv?`Y?FNQOB#N#t4<
z21<4rsy0eu<D7A4d3csOK!Rzv*ranNKu75ZGw-8ZoU3_TBSQbUh1kk#YJmBBn7-Kj
zTNbPX#6|$><d%?$^t<HF@?fses?obcSRfBcIxKvQ(lsfLf#fas;>A+=2fr$0wiNp1
zn<$ex<+sj9(k(mF6OFm7foiQpSuP7a7srrJuShX@rD?r+np<>50}&OqZetcPlU;}z
z2gTxZa{Lc}mPcc{S&RIbnHLN$XUvKT*7VJ>Z{Y(lfJ&OdIH}Q0ms*Udhex=qf9v$E
zmDpaQ7q(NXW-497-Cy#(xn$W`>fj%?iB6IZetd2OfW};@)K;`Qq_KiT#?<{01G$Fq
zxPUDxc%Zm3|FQ5LGsto@d0G4X;F`&Q^WS`*(082*d&G<od>Q~NgJ>(KG7s0r8gXZF
z*$9BM;C)Qf4*+lvEHuYa47M@nHrN@!WZD*p6=d-Ws)^Ve*hU^-7}xkZ>WiF<mPZGv
z<aZ&cJ>UHH&$5rgeg^1Rlr2TomZF10bWiJaB7HH{%rHRL<Y|@Gf1_FKWUJ*cL+gH`
zSv)c3q7sQ$dE7Y3({`>_f-(9eEiY;17fcx^SF@*yQlDg_{TlFD#k;0)H*SszX}2a|
zYnzFO;m>K3a0Ds(t3<$)QK$1Y+S*sSc^_`2VLZ5vReA1CXDXE$X3P&K)6qpeOdY#(
zz;_<@_;IE)YG|A}y8&!rao@Z&Ipy}iJq|OSh{*HEHRo2moSUO;W$V8jXU&jj3$MRh
zT$ocik-5h?f#5Y_;M4}HX)q8lC)lf#ssvrCbmAvtFDe!DUNJruJRGYC=v(fZr*icM
zqg@A&KI$C>q732~yIkNaF7$NL?G-(+_*i%8D}&Rfp}lX<eJ>M5cSd1nfY<r{X%tUA
z4qE7Bs{U?*MR5<(Ahc4YlK{`fj$UL_DsQ3)t6NPjvaM(gi=LO^$+(0yW<|<=I~L(#
zy*$w9Wy3$UbMuD~L}N{G&({3pm_u0u2i~z~rYTV_mnwOXr=}$0QP+vZe80t*=v3ES
z;-!@Cyr4LAr>omrK1AcH&Xku);rQgmq%_=IVgeWI9wah~BG3cT5PJ$z&Xn?&$tg15
z{J-w;D{I`tVWl;qB&yyc+hxi*4{oT&GSxAON8Dk|q0>E`%y(9GkBwNW5&ki6Q3kyF
z-TU)SxjK9<#-0G9(ZdpNmy^eI_Q^wHYD$CFJ#F|z6dW~^=eMSUwYm9&_vh4xUsmVT
zg~)&SEn+csE_!$-^Oir;^C`c!=I`>~tYs!@^G~WD_oL7D%<-#-!|X@PqZ`RpbIUjB
z8!9wpDPjKMjUQXe{7lCG`mB9oV{YWL&<WQ`>95Cd(f3Z5K(YK{am^gOK5f4~acX~Y
ze0`wy#52aaM;110uon1iW(|5~pbXE@>tD5zU88z?j;}rhuv?Y}Fpw+5f`?vU@|SdX
z)1_P9ve5zc4gTK1-=~B4-QWGIhZJ2Uc%tr_UjcaSFZ+iwQFb_!>7D|&JUPa5T^j8=
zCuQp2pL}k%{QD~ZF}-GX%pIjrJ-yVQ)?Ej(dtZ6_@Z84OOlDC(W#%@=hK3&v9*cs<
zwB6mmcP?}E@wr!~!;hG~@elhy9sh&)o%kE|>G<I0#`OBWz9qffy>9lwZ5tjib9Ko4
zy|}J7ZA_~g0M>pp6qW|pNV=?<4vtz4`E~F*hk;c-VD@tHeth9xb9BMf?X{3i_TX9j
zpZ_)$-P<%ve~jw-Q)3Yg*-q8?;>#DlYeSb)Yp*Sur*wB!sFvr}GEgm(XgHkD{4(_)
z^Ot}UlZ3*S2-iPS<Cq+yC{yd6EYe)-Ty&;s>tkm?FR53Xf}BFq)(~iu7y?=)_Uk*v
z+P9I*LesbfE}_>MwQ$>QCSPn`1$5iKwrA_(f0rs<l>i!nA;0b`{j`7biMVgopV)Qs
zMYX&4c&#P}#q1irqW&H&3g>%gGN%@3bN9teZP6Z^SjgTg1BUt4Y*PP^dt<1fqkmX5
zz3=+HU;PHK<=Niar+!2qd!eWGVEyOHAI)6Ku9m#Q9|h)I^4brK3<aB4YEwJIr>xpb
zR{(!FyJUvjT_Mk=ywXGc=0ukulUGZW>w?{_3$6#600sg?8ZVbqSM3dBI{Qz)ls7j4
z;5Xx!RCj$LxIr7?0_ENyTF16N^J_4}ph^NaWwNyeAOi5o*Q<>5xl<>pwM>)%mY+R&
zSCp+qy=(q+e_#wu<z+iSsrH6~IogVR`&!>|(5Z<Lu#)HAs?sCzdc0zz=YAvhdTXPX
zhejs@E?-thmSFbve$i|$#B?P-m#A{+gW9E_{Q*6JRUV^ednM5MeSwn~T(SUK(ot9m
zIHY7Aw?Ad_&S34O(!dSlf?v@M@W1}O%L4FqgJwis9B06u;A^#$msLu5W}_gkJly=`
zZ(I(*x0)S%-<5sQ4!`!nHx_Ey9We~g+WFBdWj{L|!?w%*LksS7vU4D=kL<JKgM}Gu
z>aD_m&;YCX9JnOgb&PLl++MbD19V}<mbzIH15F6X1F>MIs@*ga40%Y7l{uH>&D(}=
z@-P0PZARXJm5a81_m7b|EI2yrWfG@nS-qMwwT;nEP&p1^sht|Vi|qD-&~&LFmLp50
zr|8KU<Gyy!_yQ-7&!756)_9{QvjZJTb~zZWa<5voaLbqr46?6TFC9K0;YlU^#n8%t
zA?|@t0#Vq<jAOgW9xgM!Jmh~%_dRK}nKum#>pY;hm5cSj)?fN{M=209x^q(A*J`M-
zsMW?KK_Ig)3Jnnq`x4+K5ZZ~#Vrg7CqmNe6kkMbrH>sKh1I;`}QTP=|ahcMSnaRIR
z(SE&Jm_??)HTqk6b-1HoO%yMNfQUe1m&<trT=z0KFGGfwdDT+O#jI4kUKeayutxx3
zNUCfr0rTEg^?ZKd#t(K@B9UcVe?ip~!Qk{cwo8Ob>$l79leIqCHG8kGkHZnA`{L;2
zaX`Tsja8$asarPRs4bQ*tCLqi4zo0esRaYxl_RvX1XA_1D%cL#l?5%j$Y3xmG^3;=
zCG%-xnQx~MQh^??gfy20CHDO8*kkUgQ><HnLhsvGzYokza7ZWX`lDlvd07zxv`!Z2
zjevL+QSk+UDdkjm=<%vSJ!&T>0V+?PEF`s)-(N>*KCZ^ACx2bp*~}w9f=Q_sCe-+=
zqbJos$01#bfLNt%CZIWoQXN8=g{CYLc5RR!Y~+2S2q2I{$dX+H0ucV~pv4u>eBlr7
zY4KxvmpYZ|yoczFdtYZNd)NG1V_oB<N26mzPPE6G_dCa{R5+h1&x|i*H;#9Xmq%Of
zu6bwt<UsQkKig64%9af{qjC<H#>*0#<(HK#pZ#n~d$!wWKCx78zL#!^CC3~CVWiVQ
zWW8&jHjcS06~`&>CqLP>n<(~tM087gwZt1mPm}!-?Y<lsiHCe8`&p-()kEfd2REPZ
zq>L|blUM&nz9Wj9uRos;qxpYi$6Mx_4?+mcet=pv-Ngn7Ji`WC<?P6^NuF~JK}8e`
z2qQ=P$j`Z0cFza4e)Drg%}kP1#XxpQMia`dYm^8q9zUH-D!=>ndF59lRk?=_d{O2a
z>3C&Q59`#Yje7pLuOELHuGyyvb%`F5e9qPY1(na1+2LU=lzwL$GkgP3Q3^JN6bZTt
zCvrHf%u$k!YvM$qadA!iKMkyi+Y?9C_Gf=I_Wz*+<S#ril{`KFgQXRq!5{l)ukrS`
zj(v&0z5^`&;XnBkVDTdY=k>Hc`DNg|XP>_ENie~gGKk{2>A$6RB+t}=7Udhk77xhZ
zfQtvzo^5oIZ*F6hJ)gggQT_q95{&X$Fv{<~)pvuGZD?@f{})L4Z~ipW8UHu<;#Rpp
z{K|_-Z@=2vHK91|yj&EEFUp|sPNpWU+(&DX#r(=2$sx#8O51NEDE^a|gzoLvlb<2J
zz4H%Z``n-Wqy0nqCpp#jJy5Lw?(6MucL;I^VCaI#p#7OfGUJa<qU$aCY_!~AAIg`l
zrk)>!j8G~MUvR6L0`N_yJ2Rzso6KDDm<}65{j^s~tz{tlTnsOGIrxFj0aXey{YA5E
zPD|lvu45PooFhwYf@{o8nVdjexeoY_E821jNk^%#xn{@Bw+eT+@vAPNkU7}OnM?37
zA-p6GjT3n0$^s1jj~IufW6ryl&)%>}<X?}L=)mMtA(e|40K1S<W5v+*2hgFitaGmb
zivU+79XZ=E42zO{faYf;Gl2QcxsC>#L5+@!8WLI4HKngie;7&XIhUhw{4RgqO?0K2
zt*R=`L3C~^2?wY_Z<Pf4qU;&q(dmY^-Qlp;(FY$V1pL{_n8~zgn@K`fd?IP_@eb3U
zOJcWFaj%8k-<Irj1JDH1NS`(mFAXolfjvEKaw9J3#;ISumT9=K*fe+@kCe*0aAc}r
zT#e8=M4>RS<YYpM%<O#LdrJ4{QxO%@6wJwIQdZGWv!$rik(dNs=sxew8F?1ZF^JP@
zfFd~^;KPZAxJMoa#nlaI0jhonHcJCQtJ%EuKYtb!+^vk2B2+I*MyLT$U0-uYL_oBT
zbab`Y)fl1W!xPDXD_CY~0geHkQBHIe1^Fa8SAI`OUB4=nyqufcXs-1;=M!*V>hwDR
zd+9RSNFdf0$C|ptZLa|%2{{D<EMTt<!5l~U`1gM7<TaX-Q4j$I$I;h>xfxaci+%pX
zj4NtUTzLWbdk*;MVM?$|tuW^m2fevx&H1go+BF>Nk11~vfG;E=@^_kR0cqnkW6p{7
z)veE3vyT39_-xZ-%*kcr)Aqll`#o(wOf^g+D!I9)Z6?NR`F`PblPgPWfL4n-xo^IE
zmrgAtGrfv_A+G;>YS>?_el1CmwUnS=SnRoA$_m(sw#wuF*F0-a&-Ekb+9}AEfW~Dt
z%-J$?uNXaNFv2%&hSLZ9=Sz_05BM+4*+fz5f4*s_IXz-+So%*^E(vzrF|CK`LTdb@
zuWNkyAw)nE%SIVgDA3sbq~BQEe6zHy!~XcauY854!=F*J<;=N<GTrxJKS<A027Ch$
zYZ&9<Q2@Y2RI$l=c}nNl?soa(+tW=_<KCV?CbZH;Hq0t7<)S>O39<qvqwEh2rdMdv
z0mI34iu~`C=FFUXe(MMSDH3*|iM5<pTpB$$pexb=A@wR}+DSDs#Kw;$Ud8X^=9!Z;
zSs7i3dJ^wE#S963R;d$uo$8I#&B8)+9ng>FmDbt;V`BKMVrgla=~03w7}`ZYMH5Vr
zD(J`58J=GZizPefI;H#rzswSf$|>-~lr()2AR*zS6DJ2e$7;#Z3kDXYCqEVZYR>cX
zZR<_%old|ZZ0i~@rEsvFTyht-h`zWC9=;=NNsqgO=dN4lnV}C>D^b-=)Fo%J<)_BR
z-0q%E7FY!2D!5eYb+#%NxV)7(tSnZSUushP={cu$L%&{1itoRaz%gd;smKnat-PNS
z3&Wi7qBh$v8JRb#tQ}?$i<KMcg1|#q_09J>Gij6${M;di?$qPacru=}uJxRgPStLU
z56rpP7{kCRHm1!b#5r73!_Ayl9Pq-&>;6TZiaGp1sU`a3%owkn>aeEJR9@gZi80Vl
z(G4nYF(J@Cb7UHbn@1m8v%hqPAu>*kH6JDTkSt{fR4r|`3|;GKAe*F<j)qR2<$HU6
z-Si|7u(T<ghCquLT`qSh1V@|bipldq)GIMn@F?XUkX$V%oMQ-4CvM%sY?bU^d5%_o
zU_epi?xMhr_Bs?PcSn>7SBR7{k(0TmQ2eCSx->5Dn|Cu6Bu2P5?-tp@Wv4gg4b|<@
zy1&CR9X<^XY^ql3oz@9=GS^C|)-@jTw3V;@USQmcccpa&5P2#YShMyhG;Gt_^Sd3X
z=>3-v0$Qmu*LqUqw9q)S)y|fHlR2*fWZp*6iJoopa*3XgAk&;IcY}?A_fsL~qaS7!
zbDMIPZ4b+fhm;rEnTw_oDn~z-67q25!$=V2*1z0BD<!}<Odp^2#p9XrsG8~$3(p%l
z0I9@Z9pHcLPCIF@Qj*0f`jmIZZ3>K;FmfPCya3RdrjnfF1N!xb#k<he*E1Gmtl>IP
zC`$>5Tw!e3Havav)T096&sSYKMkY>_ajKj-%I-#5jky`;WgpkX&ILku<S?s4{>y&c
zl{mfe^K_E-kblm^U4<XDz;(>F43(m8i3%t(z{sXP1Nup`j-`^|a#WY2ubw0ShlH|=
z+WF>x{$A{j+p2W3YLzq(mS+c^X4_`Bd3({jROJY$w-`pLlB^r{2Q(d4{LD2YigO6U
zJP2<I`{dGYSj3S^yapZ`wAWU^0~<-LiP)^iBuAF{KJ4dVB$S-b@A`mzPUU%UNYQmp
z)8l+A8gRC9`jV=+v`ST!##YX|t<t5-`kG35WPhQ3!g$3@v1Qp|FO@QdX<*Gb9%<^Y
znfx_f9Qkm%i*n+@7?9T(7L;cyHgOqdVzf!jAqyYT_hj^~e|7MU%#^ycA#I5Hu+P=}
z#aGW$Hd>1^*(cO<pYmt?4S%htdn2ixTAWuL1e5)o>NaQn)&8l)RL_h*mGqTq80x>}
zTP{t`mR8|&(iNrr>_+lfI_XO&tSH0aIC_0Gr0%+yKBfDouFlmgof?LF?={^uTU;&8
z3~%&L<0tkG^_{hIfD;rj7GN%hzUiL@*eIR0yGwgb@1{*^E3N*=_;tS<zG0`5z2?FM
zfaSB`cSm0jZDH2;C_8^+WviM#w3v?iYrsD0)t-+}ErM)+JyH*=Z}^e_8+`Mc`ggTc
z&(<!rzP>ixvsTvWMgQoczw7Yg=k#z-_w(h}+z@Vsy|z`u2|j*0<SCvtt12wx*!=X+
zu)XhDTZ}{h*&+R;{!H}u$hK#8Hly<dA?bgtd+P%~191{wr77*_K!It~>W594G*)}P
z7nY3~EW`N>-%h+Fa9@~e9&B!u?3(Z~HGNhFt$7wk{xg5vxf`zV1^8-E@?d{Si%(i*
z%_|oOk`4gA5GUECl5f{wL~cWnPpQ#GDFIxhOC&HG7$k+@?OJc50{I>~WxF(-k_Rf1
z+U4OpdBZ7=v`Lb}I!qLBgxeRjnU?3|ESzIxdd(&9#t#&!Y2<P{d{hXUyGw1#rCPv*
zz3B127n|~369#o{rJeTew7>S_?|Znmcse<kjCQ_Jt(|P2P!l~AcPH`5>iA1PT|N0+
z+=jL8I=3+Ydh6|^b|I@yRkOd-?uS=9*$tv`p$3I0+a+(MA`?2*j!PW;kbTdXV_*Cn
zC&08oHmJ^2{v{5@0dhPt6wJS_sp@X3Df%t;j!fudwU>^6*+{9jfJWx43qSvd!Thmz
zecBVk;7ipP@+O!mz4a1c$<zLG12?3J<^0dteKvotHE@-B^xhY{j-9>m1264w>2u44
z-eyyQ0*+h#;4>erj;r&vg_EQ1YmZhrzq{6Q#y<yicd8}L0l%Jg*PeU$uGgw9Td&f;
zZ@@eGe=CZjH=$Yf+4{m|cwFcER)X=*V$l-jN?lfz&9+g_CalI=Rw}47oR3mlptmM{
z5%c?o=1=*6ZOckdgc+zU%>P@p5<Iia_6RV^O%Na>xTOdX)QexA;yK0_5YoBCfTYzv
z)7XF&W?)s)y3*TcKmYFgJ{CbPdqzHg6j*9>@+4GAMaP6JXysbg1x6MY;zHIP?aR2M
zojZXic(^JZcpxo~bx|5kL&0*=0>}e0f-aQ-C4*}z2SXn)vgX|j^-@6~$19hWfB4AC
z5OV%F<?4FAXPGMG+CR-Mhdcv#2M@tB$DVxoF!&>nF-BD|6GsVom*(2fn1T9BJll-_
z126FyCMTy8-Te0tj#qd1*;SuaQ_akuI>D4wM_cavU#+4(k4`@6kJYLi%rWLBRcEx5
z!$m;SPN_E*Kx;W@B|V-H17wcX7Fh3KUm&#{j|7Br1cv1N2YNb?qZv0x`1`y9czw}-
zA?&Sv8AKDcT%pe@!#>wcf!49zdag+c@F9QxJ$Sn!dn$q%^sLWU+7x~!Crr`de1X$#
z@~f#y#gRX_ZJK!cuL2uQW?uGdr?ODhvr*z+0wUz+*<@MK`;v<9Oosh+jv+dQ@;s&3
zHKvN5igdvxnY1a*gSF+}*QONPpuR9)4+@JwpbS3)i|&*X&hgI`Ozov7gXJNdaz%Ej
z>I(@>R2oVudVj+r1>*iWbFBVS-c;%<RDM9egd%G8oV>f5lI78rb(2h{SE9sS>g`0`
z<)bE@&OGq$4E>+o-e}dx!pxRSEe`Gh%%*fNflfT&>FhG*gF}3b92=cw%&5Ac^Ydd@
z%b?N#ei2<AIu>_Ii%8Z0MCX8Vdz&}bfg2n%j>-=pS|<N=a)^iu{Fp5h>0~ef;T8C}
z5{LFL|7$k&WgkS`YihFUkDokw*Z3s6ALFAZ@2apks;??vzabP;SDlY(Kq*3<g9hqJ
zkw5kHsV;^J$SDV&TcW(gVcY0@%^XR4*$w4EO|-QIQTY`72FJneUS<qf9dIyWD=(jC
zf7a{9>E?~*AgryP-=L6s9-c4F5+H_EGsCUXjLS~TH+1LxsYwpazAe7pGNG_dIdvsP
zvx44^l%a*PzPqwY2Ki{$fTv(YxDG}2^B>@-dzwL(9nP|0Ti*R~OrxbprYi>vfbw?>
zU<BvIdD#-_=>2ToQ`ypT20Gw}{s#!Gl_w+yA;rq{#y-I18=50%pqT1iEi$WKC`Zdm
zLM$>j7jQG~+83jANzv_HyMX9h8QVH%_)-Zp%v3{$^m5R0bCz?*2@h#Zm2g#R#puc+
zaCJWo$vcTyIdCUWd0Qe)cJ0Bx|NeFrH%^aAQ4T&#Vvcmc+4XlyrPA{YHRvZKRWvW7
zoigP?J@i*d;!{8|^NWvhm|q*+1Wf^7a0beLUIAS$DGlARyX%M*Sl8CVoZXmR;2+R^
zt;hygm%kFPf`7a?&6FV>spe+uyH#jfOEvdT{=|1vB7Z)bZk~&Ncx2~a&`R>3zxLh0
z<*}cKld=2Cx4;%}G;jG=K6y;;0W<Pvw{P-?|4Y0xbM(E^9Y*9Iz=*t_Y_{Rg-K8&t
zcks_IMQtYH@Xxnz)5a>>w}D{!r^fQr(|_~N0a1T_8$`WxlkKtmzu)BCpSsDPexN(`
z+;^Hu4qVB9<@bqayF059JRCTX@+TK%(6#DEw0<~Y=ijfQ0ffa&JDH6KQYpdu_KTbr
z3Nfi$CN)MP$roq`r%{;%?GubzxRrF$Z}r{yC!NjPZ~F88qTuVl`7yWnuGj5PZ~r9c
zIY0TEcP-cp?i}aGB#`%rE*9L=$<vuv5|Edw)HmC?WfD1>33Qeck{|w1(pmD)yPR60
zOBbvfqt@DiY*c)Gm=lK$ESLqu*Yj>pH<KVBExlG6E<%1uNIAn&zBN211ghNBT&ZD_
zrsZ0DbfM|mFdTMv4ea^o`<zykkg9-_=%jU;1`FlBhQdctK6l<sE1zNjFv@7bkimid
zmHcNE5zPS>!UftRu!-#PMq4p@Y=HaUbvj`;%=HJ|aF`Fay0jkZz$F21=-;tXsoC-X
zZnR}NkO#B1oHSheGY;FgTbtkf%gHi;3XsnQU{JE&ISy4B>ja1FBx|xz_^$c_cECZ(
zDIW+BVb8fGkRhmoeI6-N>1dbaj3o#zpoLLajtVzRzkCi#D>a2{!Ga@gCu!@3)Ce}x
zpfa6&34?w!lTML;SH~k5DxKpPl~iXX%JeYB)uLOB4ws@=0Bj1cQg!c22e-sB!j|N;
zr5>;H;U4c*IVPmyfg$v{EtD>o?#gvA^%XBku4wWlL4zaSkXXm?_!?B;UsX>>k$?i3
zoGL|~;Dew%fZJ6{8ub-qgB|O1F6d5JD>+iy0YE(HFfP2yR3}%x+Td_t&K}}dNy9*!
zZ2=O16|+7X2!vZBHLsMApSE&T=5^(H(w}*qwNS}N*)ey#rK*Rk5q)mpflX%pYNzu?
zZ1fYFappRz&P535&cmiTWn0knbobbT%Dc`S*=eqJ<x4(Dwv%1~pl!_f9K|t5fn;I9
zO-I9VUT_hHUm5$d6dyEd>?n+Ol}br9sdSp80!5{}>xX{^R0J@;Goo0F*5Xsi1;KTb
z)|^?*uSw_B(@}LtbYd|xf=g*pt}JurSD8=0v5~Bns5{rWskl|Fw>ZGb8w~w9CiA=p
zOqrBy;@qT9hz4W7-ZWqeI#(WU?JpfFId*QzPx)^(&DqjnKgnIqyC(H~skD5}N?G-w
zt3O(@-~2CbHRsAs7t<r=q4K(a`jrHn9M6W?fSib0B4Qwn;@9M^rD(KkFW3MdgzQ;B
zytnl^<4PAlPfBJjM?^?#yM$TO&S_@n8k(0!{i-*A_qr2dimItj=80315FejHT9~R%
z!izfrk^raxz66|x)VLcLRI3dp7iU^J56A+UnRp@RB`h4^epUycW9MigJ(W05>tp~I
z29r6@l^#OJchW$j>mSaDmO0~NYfcpfrECGNEq6!E42<WO&KcYbquNj<mUxp|BCA+6
zjf6J}`BBEgIv~v#lAV76FvK|>b6XH~J=R51J?uCpXJ`Mq+&W)FZ0NP$S@ARgWs8SO
z9q(k7M=WlJU*Y@1bf<vrR?bv`4|sA0&`Nky7kH!$rafjsg!rMnT3o|xF#K!s7q3*O
zU_HR56h`L+CsEbYI-lxHQW>Pc4K%o_u1rTVWM`^E8dY+}>GuF!$kfVHaqpzUiiuc)
zL?e}#jA`XO>dd8*+)2Lhx8!LmZJ?B;rYol~a+r43p_^y>rPHRmGu5uDOk5QY1Rz>j
z%3RD;A9pIcGZXPF<8w?Nl6xbG+8+qu48CnuC%=?WT<GBOBwA)2A8g~!Vh;X-m-(*W
zaew6VofrRZ3vl}<PyQA*LJY+AOC03wH@80l1*7LCwkzNM{q}WCIOdce@WVT|W~$|N
z`?Bcee=Wb)cx3i;AaX^v6Js;dW%A4&?-{|wCY-s1s*l=En)c+v7Vnm^p>H6GB7Hj#
z7dCT&-x!&3^n;e5B@eeGw{wyaL9!G1oc+trd>5+B6%_doc+RM;-XIb<)VkT?zRCE4
z6R~8tuQrgRO?9Qp7`i^z_WAQ&vYe{b?O*2O{D(Vxz3+Obuzxup>eOQBRII$Sbg1=m
z%ZFgtHP5u_J?+W~irjf|rTkrGU}7>vhN6)by8C(+6deV|pYYR*CAplH<#6Im+q&?G
za%p=Babbm9JD;Dr8*+(LB{2bBoiWSS0Zh&B1F&>Peuq6mPr{aJjyTy-dzMzXUH<sh
zxU=FOYW>uwxwoh|ac-rHRBeR~x5{jEHEzYO^H511z8&jq-~1NzJ0d1|d(q2zBk#3Z
z@_uytlmA->(x<9D!pM=0AO#-a5WkjH2a?HWbL&R@T|ef7x2Mr*FjwftLkr(^`Qo3w
z$<1H=KSc(Yc?>cNq!V-XM_b&UnFBiJBQ6b)Iyn7RKKi5b(TIiB&!{pCd;1M?l%`zY
zN<>;?%a(h#?{w!E&d2`u4q9zFQ9}flp-zpr?vD{CgodBut}JRN8HIxtIg~VtINz{e
ziuuSBzw<hBj*v;JQ`W@xdvlw&f7=$8yxAdz|FduXlV2vS2M2K&Z7o4$w*^^k@{Pzh
zLO;9y?2qwvVs=PgP}@9mK<UK_il(J}!;kYZ|GM+j2Y>f__?IY{yta)*MMC2C59NK|
zdGT9@+*XnA{7}AQUxoX&mmGiH?E5NTBgPk@OXOnh{sH+4iMgzPB-M$P>S8-H!%_BL
z2?LVn4f5kof*5*pM9RdAEMaf^7yPc(N^qmRo8ZsMk6YeQC4PVMTXJx`b9=z@?d^ZG
z=Bu4m{=oytGa*B+mhV}$K6x6(mQ9%3uU5i0No#viiD>2Z#_xac4tucslCk;Y)lcLf
zs_u{DCtG8~t*<Ve7;ar8+62=`GO&+#sAEl|R_&#cJ8$^Qtsi<K|FIKq*?i|i3$2kK
zz3_T#gs}5}^etWI6ZK`l;IZqfIjfcfU#orbeV;O0(@~F&Z&Y9Z^zp4%TYvGm+<kHX
z<96S1&OBjM@11x6n<>UH%FB9`k}!@Ukyb5f<5fIWZ2w9OCI0Tt?<`vgylu+HPO7Sh
zQE7=t<?uwzZu@<w`IRGgOm#)LVzLtaagH1Ei<^ZXtxRY7@BZO<<WijaM%;N~_`-><
z<m(G-eRFIIeU3BGLthn>3H^ZmL=xY=^mFl{*8W$owO)C>m3sYx|7!cvHPaK!fgBAN
zHiGHyQvUej^c%&)ul9G2ycOSb=eG0{=eE0h`Z#py&t7crT>SK%8&mn;%B}e&_RVDw
z=}l`t9otLO)&0juJ{N!U*M(KZ76$-!dP7k)yj$r4mC#3OoYOUwp&PR75auO@fycdQ
zc7{9CJ$gf3O~0cz%Ckdnmh0+);9lK#!%l<t0AAU)c7Zz;r*x*6tk|Fl+0=RgeGaY$
zY!Ki%xnIMWW#u<s2nJ|5Y3AMy!@`yh_u2ldcGkwfkl%cKdb%(f8*`>^N2}H9WHlP?
zbQ)V9dRjF5G^O#G9)=53uV*p6KfR}1D<3Y@bhabw<qNTfT#PZ4t~)Bdq}WX7!UKAD
zdOz&s1Li>Rp-p{*rptL_3bAL}LvBD~>{&89^bXw<+WR)mRdY313h0Bm$I=6a2V>X{
z_hDC^8q|U1vQKka(!~RI5Ypjhyq+JKj-xY^@l>Hc9r2RDt+Dl~KWdQFCiH?=s^>b#
z*=3WO-B0=KL})S)It?;o5Zv4MFDu=>p*H!CCYyWoQhBGjpSt%wW-%ydXM<_WR^GUb
z<@S(QFc$;V1DaBCLLZhVGoWExfkoOCt`zeNUfIj%&jEA}_r73yJBA0mi*|qU#Et3M
ze5~(&{7gMYxFTVuW$Pm^Ht2L^%nT#l#TisH^dRP#_1<!NhdDAaL_bY6QnxA8LIzCx
zP(@4r9qDvfPG2=k=4hx*_f=C*@6da~Eo0K5HIQ4uctpq`>gicSoq6Q;)a{YYU^A@S
zgW;A9ie(vd9@EF8U8dl}WhWDwDF*}{4BicC=dw50XNxFDnE#la%|B8dtv(_{N6u{%
z_><4yC8|snNlht^RA=*eZ~4eXST3YTI*u@6geK-TCyFO(gBIU1<vr?Mr4E$!ezjK}
z2#RUZV_O1gMVq(BOt`nx?z9>HFVyYeimhDNb)8)_{3`_j%2f@wtroqmhRcu`18aYn
z?by2gSgbSXZd~YoBp$71I#FTA`N|H?Bh|cvgRwV|at~+7Evo&hJ3SE|K2oO@k(1}%
zcoPw@pPN$MYw(e->vh$4D;*x4Nbd+AFu}T|!vXvGajX%XNSCZsIzGsMHD!t;(VKSG
zM6aL}yZ~lpq=}0|X4Xt;m@bzun0>0>EA?;M(4N?wuG^?kFOGV+o=V%jJh=WnGQ+)S
z?;ax0-YA+;tEv|6Pj{mPthbEZTIQFrI=x6X(-&XY*C~&<q4*lSscYfxU@!Z%o7Q7;
z8N#+yi6-hC?7l;T*}_{5_XmA?-S(}U%r4oa7X1c<0GdgfD?_DYb6Yf?=5)AcftJ~k
zv`rQ-ORYL(Otmsu9pw+AJ^1MN;(;@O+$aG}g5a&&KKIB-EuGbh{+cpY(JrKKqBYZf
zUEfe6%i+L;9b7JRSHxh_OXgmNX|Pk<LM5_6mvv~~)^XVu)_9t|Vb(jMXN-<z{t>^7
zmWC}f#Aq(t#xg|^g;{;W##q04d>~&qY|q5?<D-+9CNX4_7&I2!!Owgj?J5!xYP818
zsi<Ztj2yQ|>VY~Uvx@Z<L$*vC9tNzi4ey%vn!Ht3J4~>o^B05i4y$%qQG`3;L?)BH
zu33A#z=8)ttM0Y;+riCX%UFz=-1N4=@qx8-C`2Q9!5m}HH~1ok?tm?gP8OrlNAl6=
z@i@**ihLPt>05u_CBN>SVs&MwFk)+}5Wk}Ln!?D0qLo2g4$_SZlVil@VDQSj%&zjD
z^t38oPd{eRf_NgtQ0-@AdsxXb;JnN<QL5Tyifd>pU$}6;IgFHbaVDS#G-jIlNQsJp
zO<h*Gxqyz&jV9fBuUbZJr{j<2$76%)PUWlBaZ~}D;C$itfU=yoF<=qOpg4@6uwiC&
zJ?&&CC;*ogCT15$gxc!v>*_I-_lE2?FQ)r%DSc##NeBZwz&wbK-|=kORm@x(>oLvY
zUtU(<3If>~$=))S9zu>RTMPmmMf!Qr;C4j~AH=flEAO_&X=?`c<R@(ExPGKqsG|hp
zBrv+4{s_*>(Yq8>mxh{2hx!4H%BIsbRmPibyC3nvTK6T(W+3r~2Q~~|ct*{diFEd?
znNasJd8X2~%Zxyjb^zYrlF4lb^`SIAWoRof+b)<Jw(YD~S$cV~XJ+jUtK*fRRE(!>
z^`mz5kxvvJnJzF&y{)h!(I>z5eS-0^V(|<;unJC_eicvHBT=kIWR&vgI2_u#WcnUc
zeIsVMe3{yw{kl}t=?M<6G+cxg*j`wb2%F~7d+~rR(o}oa+z9Joab%V4MU3aR0~hs#
zA+~HUQ&S~w^Jr6}sSm|bp23aAkK{!?<t486e|oW<ZtTKgiMORS!?b!pABiUH;ltUQ
z+*8y|0tjmF#kp-^Fc;MTc67HsSU#&~f?FoYp5?147kM7>13VLf<RVipeZh-SJYja&
z53Qr62ZFv?gVYOH0a1JrCzZk!Ah2OHjo+re&+`0*<C(Y{*8OCBM(fVe3~NfP)#rcd
z9!-m02WD<VMXTwlG9%T8kBp4eY+gPXG38iE8e6%gWF_f0)r`5N%J-`e)rOei@CYNy
zzNt2Y+1qhJd$0}?v+am$uqg|=c$Ml1>!BR-G(O3(BpRIBv|@5AWiaQGtrk10GN{|O
zw94@Q*9Tbc4jrTL*2Dnner2-LtONGkYAR2<gXa;4!V6#BfMe8Qg6n1}cu=|&6ukSb
zd|n<yDucrFv*`6Ko@tlK)`DV96&?!<XM>6I4lRyVf;QX;`o#tqLsKE;V63S9?O$#p
z=7G)PY%!zjqLv05Dk|wX|Kj%~<L<kzpp4<4%Ics}6Xk5Jd_=37k&nm7FgIwWaWC7<
z0rYYi!pf?i3Ic3&6Q)$rV*parATK<qv=r#UfR>B3p?kw!=HBpLeQ&r&*8@7Ocw&jL
zLd-RBAf9x%_g#){*|Z~@IFNOFa9U61A7TaNWf9e<D`aZbQBuy*_hZHrJX#seEGyKH
z*KAtF#6uII!r@>(ML}^;Y!M`8NSsl6NbRvpdgzw2yKE4zGjxlnVsBfnaGmrb%|gxn
zwy<etgV65K#dmaEvtaV=p^DLVdspn`^5vjJU7bF<PMnpG@}rqY;>WS^gi@lCg65UJ
z{V-H4&Fa8GZYT_+PxmEUjVd2LLidcA32hrfxv9hj%QD2CtK~1MnIZ3i@IiynQ2?)m
z$#b@&S_w;fJiI6t(hSwZ?55cYEYU2-D;;PDeQn7T65;UMBtTkh9kh!fZN#>$J!tFG
zBeVHgd;F0+%cmQA)b^h;+Hd~LdjzXFEqo`|{2qd-w0b4YlCRscDQB{=1fJ~yOLPJb
z%<lG1v(xsxtHJ|1eJgEMnRD=Pl10t4$;|S~WFv{7Xy(uADzku(=(N%ddZ*2bq7odm
z%|e68bm3Z?rhP0ZPGg}Ygg^(12l77@chhO}@zFW~Dmgi^pHuqdgECsmeKy43)5>f&
zjlMRJm_3q?YGF3Q;^1m3ZI6$s*WGK7HZpzJ^~jVuXzIFq%9<x}d8Z*jVC&n1V7PrZ
zbiKX07%#^YAo?S9^<aozJRlyQAc8=p{b;>zV<lkOU$&)vp{%XFW<L@pQrWC-euAj_
zcr-Oip-x*Ns)*v(?A;PC%5ez}zR53aQAMR|L5kCpSzUQNvsgYcyPPT}y%qf7eQNL)
zrSI!R9f|=EGcgO>&Ovk`Wh85%G7f87H|e?>LZ8tq7HQjr=H`}z-WLL>W`_6)wD3T_
zI{L`tqjA0Xcr=ckXW1Y6N=}S;1vbMD)rTzin$xCxf}^!q`4j;%M=TGbM@bbkN2zip
z80lG68$q&~rnfHEBroZJ1f=cHby6rND<`R|o_dh#_|UA`U})KL@SVZqDs|2s=<o-a
z=PgT0Qfbn0b1R>JX!^_}#~(lQh!`={Gb6EcW9uh>6H|s@kR1&Xcd2oL?Oo|?Jzc1U
zWyMiLvY6WA#2};ny^D%mb!R%gsu<`O!$oxjhq)STmS>6RXYtRdsJT7dRnrbtciIL{
zEl=z^*Ie3On_?G4&uCIzA^;&lT-7tSc}osCsd&*xESXd0copTrYa;TS*`LcHs2o<P
zrtn35Wln$IfuWx;)QPc@^4p(@S-z(Hl7E17=_rx2+0yBQs$R~%nbv0wk`RTwJv>L&
zy2Q+49dw7vAF$U<k)JWmVni@<7<ud*=kQ#%Ivm`v8+OKG-HJD?u1?4J^Frt2EOhb^
z?0jSP$2o-CBrKas1W#-uh_31>g)L&U+HJ>%Sa__J|FSx(Nb3ka%h~Jcpcd{itEL{@
zch%GxP&@AVE|7w~sY7^k!UKvnXKX}KHKW_sXp*l+vSMiqvTTB@p*zs@^2J}y7s>C<
znaSgXnxJhgluqa7Z@%f|h>K<vReDO7yF+!P7G&#KkJ@*c3wA+R{42p_Gw_bSu5cQA
zRbO2)pSnJ133FvZ-;Ref88Rc}l~s#oXxe5ux5f^I0Y-Etn6(J7?bMJVbuR?4wrRYB
zrYtEEx;aY@TePg_VjTxm9IY3L<%yDR=lI|LLMJ%GWz{zWt#X%Qh4gONTUzhd_mVIV
zWyzLm0ry8gQGO;0xS2J^*%$;0<l&@YwuxnyldX%ga&NnM)^^)u?qbTzSb8mvQy${M
za4TTw4-kOKEyWa}Omr$*K^(R>Amlt~Fd4;727b_Dj>N}*;tYT4({0l!!Ch%Xbfyp6
ziKeOzWSyNZ@6y@yL|O5J4#dzN2yrxG@fB(1E*>wvX!h&-ReHmOL3Sx%byvjH-&se5
zpdn6yYe{Ft<OdLUZ-m751O;5TJs&wdVK`vKcG_cM2t8}?h9v?2Px<^`w|{+lbaMJk
z#v5lniSfif?RXYX?_MKv5|!<VqRlXh<GMB+O2#%x+i){R@u6t|fFaehSf=6}>uQCp
zT3BmG0<xaODAMA5kKQC$m5gqeQJD|bLo(&Qbrv@d!aU(J$PP5^9XLF3u48a+%@($O
zk@kMr26&S0yWw4l=WM(AuRL=P{)Jqsq8Q$k>Rr?a)mj>@#W2N@mRW5_;AEcI*`4Jy
zdWiiTDwm5}>7jeou0Z0U%`jdhp=1cWp*>Q#Q8@qNB1!Unv%y(274~foZK|+sMsK5X
zPL7$Hn_JPxf{^@ipTfnr1HHZR$d)ZWWb?o}dF;ImSFFABg-?G_qSn)D2e1xKF_Q)J
zQxB-}k(xc6^~y*tmPzGOnJJPFeL(Fteea~FRR46iJH5ADm?CTEOVP^1K@w{Zx5qnR
z`lfYp%?!<2390V|kr=86>9$s*smLF*V+h);OHgf^vt%EjXQ=6tJyDO1i6S%gxFm9z
z0&(&W{t7r08T%WGpxM_5w;v@Knb3u3LaB;aYjI7)%o0GY8BFObWsr*NYEAFusXl}=
z5BogkmH+NUP#FTe?1ox0jV7PZ)MA)2eHa+_yX3L4RDw&w-?B6+VxSWile-_VWV||c
zCR4ATnXI0XT%Lhqww#+Qzn)86hxj8Ki4ExEi#9_M5lG6z<V$uaenhl*8_Ml_hvef{
zS|5EEg(YHMvU%=r#r<!4qzZrvrPQpX3<~TPZUtl>hXhxLbS?KHVD5G4RWp2974e??
zZLrF`_v;(+Qt`~>;{`V9s-2>sr0;-akG_w`()17CP%}y?;ts4+dZZo_*Sk1)v4QP5
z>^0ZbI)^Bgdz18Iw!BAjOhz^yY}=-`F>mir5%%HHWrX=6m<tY`gm?$xJ&(~g3EU1h
zEa?%cGt<4K`<KflBBZ^xf5q;NAFJClb^G|JSA`KEDbk)Z-%HG@HTGwb=yOe}p=41F
z)q+AjEJR{N@8~6KU4z2%C_p%v8?`g+Sp^f>SKc3F3h!WV`etn?i+NjE3}u%%&vqJ;
zu>ejRhR_nwI(|n_x9xJ<Hapu+)P|SUv9sZ(oiayt6VZ^1=;K&_Qck9n3<M|Yls@^R
zc+mt^*{Re;qR$?qHtZtFTme5dqP%w8)HeC(W{v~q&MNZFvPqYXIvC(0h6$4;j@X`h
zrgeMnFG@g}8EER7C8VcgdSTrZ-MwfBv_pi7uHmLAMO+C7gO1)NYv*FV_{i}>rkjMg
zie+Nb8Q-^Gc|TUH!gMbpqFq?^>GE#ErSy@B^pQx#o@A8FI-VIqCLW$iRCTo{O-@`s
zd~bON7HkMp-gY*EGq8l(IwE_><4j|zfpfv9=UCZdH`~9IreuOJ3=O=HmgK!OUM(T7
zQOVn?)k?MP;{V+*@R86$W|WGc{3|sA&yzEn3Xx)5+fJ=L$z}>om{3`UlwDOXq>Gk)
z4Z)TVX9VL^OvfFsBAceH>Z=ATl&%N-e!tys3a<nYVCYSNrP#I=m>-f?W16NJc!Oud
zI$pSdt1SFhe8bKbk5?zzDk&D)N!<4GKJzZP0x6t|=(aCu1}!B`Sv!T1G&8;J|Cl<7
z+Iy**N-vgomIpv<NHTyz&A~7Rr3*4Wh`a4A+j6=H1mfayoI<o}J+>XFwPLD0$(mT)
zm>|vr&}>nh4VS`TL(~~aEG|wSPoayF2aUEt<zFh`p{dDXdR>gUpVwJ1BvP1)ig~ql
zN_H&3(N&o+NWv<RVs*dXpWbEDo0`EL4AHQV2_{b2o??zkWF4ZY_u4non<4RDaJX<?
zU&Y33Z&omWvRW>)xUru5DPPEAgPQA@DGNmV$aHiDqf&^OZ$XqK<oL+(1{MF{^oTGQ
zmDS;)T9~Spl?3mxx9vm-r80X6I@fSGfD7HGrav?j*1{soG$UsvN{%7+k5`G~*jUn`
z$%bT-gh=Y%@PQz`8CdZOs0G(FNK@s|5CM^ccgzhlZS%$T;zRN1Cv3iI3Yj)0iv{9#
zKk@x|XXcO|EN<4l$V$OA7Z8t9;*r}foT(v3TvgH?qjY(wf7+BEG@Io*>jWJ10fFQG
zWPF*vs|;|bMclg>U6?r#^vA%UX%D}(eHHK?nb+mO3gVLo<t7l^D^YuxAJ7DvESTdY
zyP&WVwWmJ-=)w`<-Jm|K>YZvl=vHo)eLA)d<dbE-(L+{r?{!RL$QGFlVCT^N;11bY
zEVSg1{c#eC&HIxuqk+%Hm*a6TG9#d`jPyXTCk#OvByw#F9O3~HPT27Du^Tqpw7`c9
zb+0w}?P7dfSM}ZEvuPSe67=~5+uxWXeivYq_@euraxFcs%bAQ!jQE>vCx*B+@zARI
zqWYp*Ew8Gx>1jKJx4W;&_JJ+6C4YO9gVbF1^6DhvX`)P;R0$fd@739eS-msiIAYx!
zydcda2R4CvFamb4Zj15H+CzDOcmnvm8SNAp9-%s)|M&-Gal6DeyU<Ibq6baXPWdxL
z?=<6TXWO#6CEqxtb`p+*UT&%Ka3MOYH&{9Q17HOSFHqw<kq}7Jk^xDuY!l?~+f1)x
zg|Yx?icrEB2?m)YtVJX6I1XtJM`Ks9L?AeX>+Hki1x}hObR$kICldW<f1Go37#DPt
zy`#Re&hJw9nk<o0ntK{SI2j}gtbI~W1gcgQy~fM-=q(aUS>$`e!+oJ`Tk+doyh4B@
znL6=V&!*Dv2DCpd9YB<*qQq+L+qJPSa+UnSU`EescAnU3AeiLy&U7EYTcATEDTrL-
z#;3fT014epIreB7)2(Xya5t&%i0Z(7q+}V1c@yM)QPEi7n(1D(YebZL%b9~A0R_7s
z=q8ul8KYF%WblSpZCoRp8rq}dTNa6vQ83E(RT6p=tCx;-^d{@<Z0-k4Fohd-b9yOX
zGKEPT_i=*{iYjc&ve19&mw7e-BL>-vHM|VS=>|ZY46<Ay^p!~z&o1V?bc`aHW7Ed&
zAKF`f8}l~+UL&zkdk*D3ZA-Z*>2Sb)W57+1AkzcwKu2<@c4R>q#2<3i4q6roRMfpf
zI2p)x)>LKkILbR!fY8zwCX}duAbXm+0gVV4gV#Yr2COD9NhZZ?i>|kgAjQx6Wu=*G
zRaQG}@U9B**?YpJfbh%{dnxXbQG&TAo@~6zF_rAx%mR4qv76=Tu&5s6GPxx)&Qibv
z`<KJg@Uh@VV8ny0+rq!DVvF*odZzmkva_nR21F%4!!`?%x1<nRw};Q?CdM3zCrD3f
zl5(*eBq%_V9C=PuENMh}H;8dkBTj7Rv%qVn)OI@(B+IMO^adEIx?eUf_ZtrN+$k}T
z3{i9v<Pjsy{=4=mxFK&`v)wn?nUQ64Vm6<tb`~-~g@Ve6F>*?O^d66d>~VaH5~&eN
zsBC;SEs#Q)$;#l8F-HOux?JY_>9X3X`Le6LL#3y}2Z&1ugvv6hSuvX8tlA@`e@?sx
z$LpZg&3K79#RCq+tPW3bZJtEZJ&LjkhJpc_2q#x<bBQY+XVN2y(i}0E0?ObV|NWw%
zOcE%T*<MS_Ak}qMEAJ>5&?!+XVh7Y+CKKHN>`6bX(&h3_9;{psA5cVi!IAW$tq>?M
zS9b<UIk`&9-f+1vQGPI7GS|#5OUltU!EN1Wu+PsYCokB6m9k{y?^xS>%yRCiV6Pt`
zKPn!71ei-dV%uR{#0b9mU#YJ_S$2?^xoLurA@|;LP*djc;S5<68EhMt06JiY%`NqW
zs)v2Ppm0@{hj!T~?K-(kTRX&RiZCl{=tH_G6HlKtd^#i$WC}q;V8wP&LWWP!AIw>^
zVoC?}K{ExGjQ^1@AF*ftHj&Yp?zq#)_|VSZ-klTQni*F;%I#r=u!QbaM<Okl47!PG
z8iPV%j2zw5TvF+0O;5S}pj}VzN=wL?eRHTzz{GMv>}Gor(c(&xG_=EHc3-CLky#=m
zl??+0d?sd#kIu<7vU+W^gAEOvFLlQP#MCVukviDsCkn@9n*g5<#=&Sm|A!2rvBnIF
zI`&aPIm3>_P$9+-$wr&3&D$PBgf2Vi={;I_3Af4&@V=??gK8$23X3y#<Q*;Mx&3V0
zBW|o%$lJDm8vP7_yzIU9K8XofpSTQ!Paww*GkUtBj=2LK-$T8I5`t#3oxw<tcRB={
zn9X1N&(s;v>LnvmQ04T8Hqtdf0|W}n;eoXwP23M5RPQPo#Lh5%RjrzG`M!6|jJi6+
zh-ZT~BZ!YBUudgHd*(q61b;EbWSTuJ`%Vagr`OGCnI*{v&=8P0j)Vf;BHPiys!m_E
zo(%wtB`3oJ5y%P9F5K6~*3K1}MM;Edf0C(ZFH3Kl8d!FH=t!)*d<CuKmLf~SB%0mX
zIlEe(Q7ighvm?0QX7vO{QnDS<y|y-uD{F<$G@zMoeAEto1aEl&urr87+S|sM0O2y-
z8kb=Rvja+6k5!7}<DbeuV)N`>93P)Xkb)hOo;9|9@bj1(E&BjKhf%aj=5toXNEDGW
z=`!mAL}8CL&_dt!G%aVZVYF`y-NHKEYlmi$=T)PpxOO`>WvGpqxseD-Rt394XR-8K
z#zJc7!N{fJ_LIxbH;c&*c*pFj<uCwu5Qy`a^C!SUi)R>dd^amy(nt*G&CFSziwq))
zY7%qeF84BfHJCue?rqhS3`hnFpwFkzkmc4?H`=Mpy+)!aY&`%MJF82<UeP)v+m>p>
z%Z0`s3i9B|OE!NIrcfXc-JWrtg%oIbc;JPQlSYCm`?kFSDeQo)96wHmhDSh*Z8-Dh
zugqbJ*k$7ovM4gxg+a)6VD0IGD?x{tBK#EAgC`IelT7l9O0A|z!FQ_r>g6M6F<rPL
z%Q|Ox?Xd{}W8X##i8M0MCmeCwtYQWS0wZe+J*QQVR~imUcj;Y9WI(_gjee?_L3|M`
zQ$#3x0ykg!BZMRH5Xd9qk<}AKb*&6X><UOAADDCTlW-h5{GGwh^1XOH5{o(u^<JAM
z`x1}BVi3J$$;cFwaNv=M+e>=^y^HUJH}tHH)(s9HgUJAi1=|=VwI(l=U)IlRs2~;r
zPZz)OiTboKJI=&+rwA}HK{uZvymTO$=r)o;OTxpuaC#&bd{y`p8Kx-tHUSP$kmlxe
zy6RKj;H}V#&mnfj>4*v3p4^Ngrkq6+Bte_C6GIP%v*t}<O<?8j6M7?;w}ssRWNe7{
z8M2q*By_I>V@hr@xNb*3W!VOL1fZx0c+Ef&XJae+7igr@t>94YAtCRJ;u@GhwvIqy
zP_@$<8G}H={%K4liioVrd)V23H%!aU=BxqHiJKnkhP-5%@d67zKp3|v&~SFj9`4&@
zUyAKl=9pd0c7)WvQsQ>H>4uFZeK6RtL(<r9AKFp;#&rF0cyyMnD}x4L-UWyG_Dk=}
zp?z#xkzuesp!0<8xOKv$2?PwfWkFMzu=b+F{=N{<D2uH|{h*n~MZuBl_rwF;F-GhR
zh?}&zX=}<tUfZil&2JEy#|RXMD)$mvK0u6JNe}B`cvMDuWCok@biCJ2Mb)XPDZ@_c
z?M;lv)*oMJlQAV6Mm$WKo1H}xXuw1o0#rm|iN`>ykn>zg(Ki8FzNp9$SJjLmf0!sg
zKq+&4){eLcm7#9?b$XB26sZullR&0i&Q6B{3TFmqEmnA2^wJ6^#}e|7*;#aWo$U+x
zT8!BqYOnQ2;zB*fbTavl^VGk^WBV048xmP`C$}`G;RvSX@{#QuGRPcBJbbm?rhBc-
z3OP{D?6w@&PG<WdPhv@95&9j50s$wMJX5497B(xO(LwOTJ>jOhVP%kQK&B025_qz$
zxE!+SG#E8Q){{AiMe45~$5<Apz&a$WY^Um5|MAOCI~9^O_5ZN;w!v{_=bhi}3upvM
zBOB-3?q&l6l6}tYZd`(Ib1w*z!x_%>y=ZVa_Gkxa(kyNKBBDu-9Y>A^pw?@rYFB-m
z7_X*wWDPJ{N2;wv1gXS!l@kp(cFMKcL<Bi5E4!5y0jjd`x)Kja)n<3IyCykG;v|(Q
zzvpz5Qsqm&r1`2*v-{k0o|pgge_qZmMcIr&^YN5u6UA;E6FY=3bqh$c_Kq`VrdKF`
z6vW5W-efss0K#t0_$62=te3Mk?7TnaM>Oy6wfys43Gd@dEmhhiA%XMd%%yUpOZV0Z
zvq`nbI06ovF!#fnXb;bOiSnaNY|>)~^rL@`1M<$h^HyW4LTu^cNvu1ja~d3HXq6Ya
z6jbc;Tj&v$N&q?h%Puo19@VJ*_OK?uBRe{Zl*kb^rL+fj7%2^Sgg3%%a}QM_o926>
zMou`e$Y7*`y_$Ga50fP9GYT}pms`s<YCNf$b77?{mxF(B<(p#U`vr3wOpJI|&D>&2
ziYQWY1gadT;#`Y|t%WAJ$+icp>I6&xb1ggJVfE2;zZNOnjiBl?VkMp0vEX;u?q^Nl
zKL~B(ZkV}>B>><V6`)Ifh{|cQr=bBN_h9zyj@h)e4|%#nwO8+vWIc<S!Yg&q`BrOK
ztkhTciwVMWV*|;wkd(-`H2enTU2s7L6v8<=07k_Ud99;)NIkJ&$J$Haq#3e&r5L9q
zz^WhZ^*cYvu-wEeJ#QNeG1TH^d)<Z%ipF4aRwDd4oR_Y$(yQ@!fI$d-^C1!Y7dq|i
zVoiXEbrO(@af*I)xBvpIOh9SD8xU3Go8+OF6qKxPLwt#amJbE0NbNJ_9tdWDjpC{T
z{jMP`bysZzMHWJb)*gepK0?MN8AO57Ytx`s@jlwkgHa3+I{PmgDE366cke1p;<jB*
zv|Y3{`}yq_9N6NbEAm9KK+3M@=X<q}6Y`?lc<}<1dqI^S(dVE9GQ}m51ahPfv<Z<1
zuoB0<mwG*H`ZJXNBz7M~$vuP-pSftUs^VDtQY!_M6OcQq7?E#VW7)D&swPNgq6h;Z
zLC8y7F|{6W|Cl7)M4)T+;nxH@ox8X=m$jw-d$`Ytv};0|Rf-krDntrORIJPPaxBDj
zalL?1<bXLiky;psF_#$pNXk+l8dblM<o6B!wH@L`9o;c7tH64yJLw>>&$6{@8abq}
zo~4@S5`@a}pQ4IVMoX&I2S@q!dsvEtyfOU(;&AaIX!)EgN0o+{JF8DisUe=7T<<fg
zLaH}SND>j$rwe)%qFpcmzl(2iQabj2j3Edh8deSI4CV>#2|@3h;R_;-5;P6g>On(l
z9*6CX8{3x2*U&fcBVj|*ooql~yh&#vw!NNz;!3z49Iy8HHv3wqeacWEkm1(*wIB|Y
z?)l@Y5q_qqCl*z(C0^?V&|GODF2QsWGjXb@4T9@JW!=3TZ{f0tmmC@xTee%%%PNS&
z=K#lo>Lk)&A+lwXN4QGeSHHaOm~CtYNeFleIRVbCzhJhZOVmWK)>JRQW)dwm^*{hL
zdfVzBHpCiS(&t*E;uIiuygPS4B}xR^FU6pK7@dbo$2df6f!hLBJJ2)CBJBm*zNhY*
z8_6o20wsMJQaf@O@UgVwqbWz3N|?VAidu~=hui$+A^6Jpe3sx;33AZgYf|%>jNi3G
z^^UFC^Vw9JBAbizjXC%nDFTw0=e_oO(yJ-npCxksC{I}2Wjr#Nb#Yr@X-|%y2oH<#
zO#F;Nq9t3TKrt_@2GeaRh$TLvl$(7LR>$q96fy{0fU^yjO(wb+9)s0UGw*{O<nV?2
z@3LlLc9`eJrH|wH!yU6k3QjPXz1Sj&jli~RP3Yx5Bl?%${1`<K$g2((5LigjH-cro
zrsrWxfbqVd<-WK|A-$%QWjRKr$Q1_9#ABDI{pZ@Iv1Xec%{%3-{c^P?y%c(j)e={6
zn)_i!LsoE*8cYXR<gC~O*2(clWH!TfbK;`}))D)q{YLivi_5iBPtBcs-FU*>va#Jq
z|LfPCxZ(n0HMXThUV#JTUMSmKAkW*5nKJ00sHlwO1e#0O;3b0RvG<Ku)41E0;7{V+
z$mK3Q{gVs!unbhv^$l)fj-131G(NIneJSiE7&x4w*hBmmK@d2Q!jt_$<-mQmzRrUQ
zcQSX@nz{DH`q`S1y_MWMao=yh-=){k^ieix%@-Du8H%IHV6zh$u3pxPPecoMn-{r7
z>qYfq{GvHppx``s(KIgGGt~5=M|L0$>>ID*vqmAeJ#rDiwqwc6rcjns9qU2F@rjsA
z*#M@98m<YNHj`mfqUh~Rf3emk*0<);Q}w4v%)vuSbb6|b|F}sRy`ngPStoncz6BS;
zmylULu?CIEI{8f8*SHC<B`5MiNOweCPvc!*vQ*b_&}{$Xzy;4wcL@17CYseDEU3IY
z8P41#Xm}_^>GIA2?Mxbx4du>>aaak1JJ@HD1p7+6Rht(-3m%aDbXmkZ|KZ1k(5(=E
z&cp4A1gP8U2nIk?80Kn(<dfMU+9_aFad2CREGa_sA~<KiX>5kHh+sKwL-t>^Teg$O
z9J9-YIFN>(+0F1n4Xuf>4X|futbCy8E9zCC4sfclKfq^&x7~xZyh~?aA1$^{aptZm
z3|Y-NcIZW9RcdXP6zaWKQ6Y9&Nys`wVWpG=dJeq8O+egHTty^EpNd-L{?qh+ysg{Q
z0-m;U^BxK_&@9el2TVatr8I+CyKR$D*?O;|$r<uCi3qU+9F!P>^)R|h26Qr<G#n_*
z>Kf1e#oDjivry%&;#unu0k+HY-u<{_04g7<G-b82zm?)kN}*XZ?5ql8v*d6^R%OBE
zG|hc9cHah1XVr7tAu>SOi(rAi$tp7F%T7ocs3dJ+OSg>%7?9s{;U(|GUJ3b4$UlDN
zIuBys2i)AkUhvEh8nu_H1#U}GeNFPT{Xp=w+n*50K93B51}7-A*fQLftjIc;BIZ&|
zi!8H`1a1<(Ts3<9%C_|ns$=nPR0%O$GON4^R-=FZO_gU7`;o!Rml=a=CJ7A4Mq*y$
zkfje&f{u_RemQ~kU(@zPp58NY0-1Kpw!UDK2K*UeE2LzKAUNLqLH5hoj6B~`F*zsL
z`z5u(jEnMRWRGsfG-XG{6*?opUR1^;*54akRy+E>2AR_w$OQ-hg4<@|h80<aLKy5W
zxK;)Jm_MZ<#OV|JNZ=UBN2ob@BPT_=9d)G|*sf1cnVs;i-7(iq-(Vf8!BW4R)r(O5
zaMBcy^wT<@`?DcfEz(b$LQ?IP+zy|s%aE#=ELEuc?3_p#>ZRdO#AKGF33F_TTQY@n
zDAs3ZXID`Th>XW%ix)-RZKVs)`!icC4@!D;h%m<QpOh?9Ljhe2PF&~yV7sBW?BxU^
z2P_L=wcY60dQrj|OMPSCW_?)yl$=MU3Hit(5ZTJux|&ok#X|aK6fesOH_=}}1`?|)
zV=Bke1n=njJ)_!^+aWlRgws!0BlH|F@QjVfIxdGDWaT6&d-4-&&^{rjCGZ00jk%1k
z>f>~YZX{+F%i6K#m1TPbt)fB@cC=V*Nqx2V+8^Lx`F8eCsz>C9z*n`8jhxAFU9qSO
zo)(prO@K=UG4QTk8h;#oL>JJF;I8yZ9ka2d!0XG>R>2~8HSyUnK7iOLBI6rB&zq*(
zfXV22Y~ZN#E#Ofi`Kc>(tWAZC1zeWqrAY#=R-;{G)*by{J}{fZcbM>>9YYMU$azW;
zR(S(rs7`30fUg008vz9(ukPEsyoHDxNHuB7TU04h;zIC$k}L~h40}I#AC8TgfM!An
zp)KmgCJ6<kRzhO*t)vIiLrO#ug~Af_nqOCBg&roFPl(>b88p6ML%XE?3-pY~a@?=?
z;MOioC+3KtKvg$Xu3{pI=P7V(#|*Qhga}t4n#BvhMl!k31=I5Qhi!J*ECjnWZ6O2>
zVu<8*2PP))1H=xg+m72ziNvUF1Gk*ZG5|MGJ^4zH>s1Uz*Z0FkZqc|2tbfBE0bX^8
zT_8ndfqe?&cjm+st*fTAtO$!Su@!Er15(roT1lOPxHVSkPl7F#07s)wBmrYpS_^@N
zh_K;F+!C?7ZXbCkk-;WC2|db5mP5T|#6DyGWFN_qDp3yZ@}u8s!^U>sqr`?cY<8=W
zPIf54ojcWT2^9oLacuy5e`$n&rJIOek<Qu*39)R8&a_}wTowO=MTnhp%YbQ;ScLM+
zVB6TWU}lX97gPoM0Plm&x$ShqNkQ(Ey~hd5hC-x=HxOk5T;Q|hBY7*X3d5%>35_fH
zdOTH_G@&FW4%HgPFE-j4tk5MY+$a)dSA`V#-aq@4>pH`?t}7S}!2fegfl`|4C$WzX
zQwd0Lo+{#5;82(1CDeJhf~Cf-*CyeaF_J$PkgiP(B$t9vN&q$O>0?$+y9e&m8^VG@
z3iXHp{P7JU>@_Mt62ib*i-uYVp^NAdJL)KF?~UHag+|&!m&upz#&kaSPzN+fk=IqF
z*_1~Y+C<E#OLH+br_xx$jG_6-;rL--_Qr(G`2OY4mx?CTsc-d#2^=H5!^m%i`b+}q
zQT(5>nIf8!%9a9V%83+BAZs+NRC~8-Q@1R>G@X-eCnMo-A8gS7a-a+B^RP{&JS_wZ
z=1xqd!3;^=R1vG9eqxsfJIRs9zz*U+N(!m7-%EkS7Kt3lCI|c<OK2)}j9dd-_mAK)
z_-H-}RNw%li+T))d`%xeVb=p1XAhe-%u(Y8GV(*)s1g0o3p5!f$HPyc)cUW9WC~~X
zhEf|+(D)2}U$s3_xIx8EiAn<JlVpRi2UKy%Mm}<3m3kzx>V{fQ?vn43+L4oHA}g>q
z*?W04Nn8n<62A*ms7vpfnQbV5fF4Q_&%x<CM@nB+5}gp%=G~-rAWkBhlrw$A+Domc
z=E_)5^j<1rJnu{Yxs<aDS}sf!r03Tav+JT_Hsp}-)a<JWJ_OsIxSZ}tUotrMaCjk}
zSfG#$#=OzPP=QhXzRt1IO~5NfMFjnam~kp>HH}sF7(RhCKd2A6@2itkT+l%&4BomP
z-+;0<`w-V#wS%=;;8aHW0n`QRB<U48mVWi)k`spMVJ52}Y6C_+98>&_c#%pI(Q_tJ
z9tj7yfen8~kG-#KNU2p46kiPM;Wai3X^@O)t&db8ETF9KKp0r$_n?i0tT>hgYr=u}
zVkFpr9Ochx{62Bzx{*l>54A=b(9VPa8~*1K*yJKs3TMhv-`F<-sOI6u72XNG($k9&
zQq;TXk}rG(9#7(H_zHgRQO79{Ok(GEb@8S6auBHZNjGDoSOV74NdR$#<E+H(b3Tcg
z*-AP|>4KJ;QITxX0Spu^2VuyKt8@ZM|9_rl#1Et;{nn-SsY|D%%f{JLcJvEJKTfyY
zI_Q*0mGR80Y-+6cq28M9KVypyrHTyDbWjDtex!)*MGUvq8TC@QGfhQqV6dwJoYgk0
zg)l1vv$|@kj)*Jr98vvVa>I6*fx2uH*?XQ}5W3@_s_W2;*BM94YOm>o$$oOdQ3#r1
z007Ma=fsf<FYF?0?{M$aL^z`B#Ztbi##hxF!9BA<4N6T2p#t6?dmw7lEr6%UW>8%S
zw8zhcF-HnpWoyNdWlBcE?JUE}MXm0@1CV-K3*jucsXs~_A=*zI5O9!^?p+I<?LSC8
z!hOb8;C>0Jf7X7c(V7>FV31YnWyDjx@xxD5sZFc$?JB@kOvdHQ)NWCREsDaiB7$rI
zn@_kVbn!YJYA#!~3eUR)pfaWRLwy-OK*_H5t$<hUXmDRdq=FQ06Ia0jSsrOjU$)|>
zTu6iULSzY3eZ0RtVXs`a=qP$M+asnf>vI>I6r#95MOM1<iNStWN~@}5a8~;k%?r{_
zTgqnncF%>%XcQMNV6j97pja=*s}>ecg|o7cMKn)xmTsBNbU}d*L`raFc2duDNLo@^
z9L~gW$XHN$ujrNdQ!MN?tBC+%?gdfb&~{CDwe41Kxz;9NElZ>#RsaUz!~gk{VmoiD
z@{&rIRL(c;G6yO8XxkZBR$o8}ZBlZuL<dzPCW}QtQsGTuVd6vw7|fYo56HI9iL0zc
zUXr?mZI{j~h8Vm{Dv<KcNn*SyKy3q|=Ey{5G4jHVkK1+2RcWMxlf!n)3eTK%I#8HN
ztw}8f3h8!Otn7o|iEs^`{!mF}6xS@T>iVLZnLPu=LOCNjAE)6sM8uj{k%IP3+QeA-
z?6Tg{OiiGGip+YT!C~@zj}3w}IJ$r^fnA}?cIK{bYcd7Ah4=6-#0!%Evtq&2ab<sa
z^qMjIkcCIK_FkiXicH%gvIujD<r-$GKl-a7EC>*yw1p3&9($KM2p=)Cq={D4LZD*G
zGqDY#T^s~icqZ;>lGt4KvzMTS79p$wbv1e^Bmm@%{k3*|kq5~TY^iP2)?=J8vtN4t
zdBJLc1kS*<evrk)=N^y7cfwm-*wwaJ?2CtLpP_%XO;(V;JFG1(7l*q+$2uTf0ucz0
zb#*``y3}U4_$V0b@jkg8FC>NICsql%*coj1VY6fWX<>U1Qn3YMKT$_s#KR5BD0Z|T
zY8)5J*e2bG(ZFaqQ!J)H@WC~6oIy5f{C$C~Iev@6=vo?Gym(1kMwm<~JKEy(ukWoQ
zFYMK>zJ;ZRYKfRRJ|;QR8Aas^pNvMZQy3Xd4v}<#B;R%gkUgejjuU>6O%K`u#Xz!O
zKMn;x)IQTyh_34T3{@gj9NS1p4Dc=9jZlq!5oskWOp0in5g@_%jf6<ZUVNFtv<vM<
z%Pd}^eMIbmFl@hn-Gw(3n<@aG<oqg3FlgJ9FfOUobqa#(YXZKjQiL}GV2rKBd&5NU
zPIgI-XaV#>SSUWOPf4+>yUoNkHk;!)Wabk_2;B<rSj5O#LMPDu63C=WY;Axci7xk+
z?G1h`+m%O+M*S4sc!IWAsPL9lNdE^<3D_OS#a1d4Sb`euP=u`WaVgOBwDIjO%#g~B
z0?I9IP1a7SD-Tsd(J>{@?ck)a)e@43Kj_<mi7dvQ;W2jU^T|QefVV+JrVXi<L3kq!
zo9OEJl^#k3+B$F@hX1}Z!2aA9Yp>fyp|Dvp62MYLSpV>wZc6NUtR@P`0X|7jf}xTl
z>?(K&AKhopNac4ocnCFy73fHN7xa;t)GxH5SBtce2)i|~SUeLo3}ack!Mlze3ds*H
zCj7Qz-J9fruset<OI@c24>35gu3pqH_NN0(k}RYJf(n*%r?~vEKFm_Z&2npc_-WVS
zR?exnKmu?K!F~ne4uY&O>Q*XC0Bj;&<%cTXD;pN?3QB<fGf63?qy?<JNqY{PMv?7f
zzW{GJ1zwcBjA!l>R}W2DLN5Mqp$Z&&xk@|$8oU-H2X5;<$^P&|+v{{*+3rZ8G?vQi
zhgVnt@0<VNladpV0tL$Gu&nq|R0TeO+F2~?kV5_ji75eED)~^)0!{a|nP%0vES{6u
z7PteX6uMw={tt}db`-&{Fho%6crF9QN)`)`fQ!R%vs4}&h}Rv$u96A}^feQ%g4gyX
zwO^}EW_3;7A9W!lGUr>;hW8hLYZ$4)Co2L2PM;KE`H>bb*p!CqIz^{Z7c7vFYm#rU
z{+_t8quNOANmYW5MypEGczVq0;E^y^k!=_zZxNKNSwtCuruxb@l=I0FVG0OhrIqMJ
zkA;qhv)5FG6A-2P0Zrk*oMEkAZyAG_4q*0swWoy$x~VFqLg1LdLY*k8OnRtBVK;~G
z_1#r9NAV^yV^`x~4e{8GtB-fn|I*P_jH!qT8zmMM;13+Y0{FzU2ii#UK>~vC77U9V
z53=7kRecgLI<cOdSdaIE2^Oi(*ykT6H~g7K<E*^|vO1ed@Y=Uk|HXey>{`%)p(xdW
z2Z%K;2xqNk0u`_X^q(EY2O`X)Alw^Fg}_zW=Yyj_r?Aa|x>}WEEYz7aw_K@5rksJP
zY%X>I;7zYN5eRv5C#NzR4S3HjW0v7)g#(LbykpNp9KW0$Y)slY0L$xh*kEC*99tFr
z{Bu>vDpJ^FE<{)*cv(p57C?BU6cFb*n=0Fdcj*==vysq+<a-!^YsZ$S7ZTXjtt876
zi}v?}J?2abQ3X#SoY8hjZi`9+ni7-7mgRi|kro(~7phmTGglzLOo<S|3m?LB!LYQ-
z<+ItG9+oW?c5N64aM8zaNSqBNpa~0RZZT1Zd0^P?QUUCaq&fp6g^B{2RM6WnN$?`A
z9lOGP8m!0cB(#aQaj^30!!Lp*kbUSMg#CLd0WNJ=P9EKpL&BmW_LeH9@oVakCA*@{
zfnIOBm3^_+LYqd<Ws<w(2Of3eH`#u%J=CWXTop@ZBiKsP^vv`;$spov42~cmw23F#
z1Y*Cd#<sw&m+6|?n!c>Ipu<V8!I)X}8Qx-GQDw|ZmYSYVUpwvP4Msu0_QSN12=HtD
z)RJTZa+r1QV=heHwPrD_6NghZzXtX96zVkJag;#HgManhPf1Atn9lK40Y|^rY^oPx
zJrAfTDS=4+&2(zAOVk&)kHJwNS-l$xm}!T*K=(_46w#;tItj74q=a@d>6P4+t~X}$
zg+<A1NnFc*N&o=%TQ@@gp147vt|`Kz?z3mt2(PKPAzMYlqV7Kq1HA7Yr^?&y>KMAR
zs)CrnwGyslp@M9v7<2mr`~`c;&?|$^Gv(amGO0)U&n3TqTZY>(fy~JrYv46n2oiiQ
zqL$F3dCSghDMHo_0!1X=oe)+rcQoMjP~re<Ph1FVQ@v~UX00)7(t4|0JoOa9*-xr`
z^Y)O$Dr9yb{)qneK<$vOS~PlQfzkzB&jQe=kN;hPlpOhz*)XfHF(DBGgMdhwKu9*y
zoXx^SII5K0m%e-CRDLWN>Vot(VC5y=Tx3fLD4c<ij00w0N5|=zwUxuLst3#x##GWq
zQ*eM!)oC21nFm>wSkUu6{F5PK=RJ}I1cYJ-m3J8C-y9)O4uDg<9)GgeT*C2B`B!Z-
zu{UiUea1r-*(PAjfUAfctGZ#f75#4l`WXu*rB)eU3`s(moi>Td$K_WGC-R{a_t~+7
zHkl#|+M0S)Ys?kfAn8lgD!^R1>~HkdUza3Bw@}_t;JsYV9}gN&FF@MO_%l9haPD!S
zPZP7mRnwr((!(H`jCU)^o!+t}*BtU>x7_IyoG3-BSpkOPAS#a!3!l?h5{{_pBOrJt
z%r~ta*94m|_9?85U)DXre7zoef37j#sh7)|c)E{E?tNFhXkMtMX)HE$NiCRz0qrue
zH*<#nf;SoX#;SPHX}kbj#Y3sDxdCN$5_2h4>ERe`flwO*b@E18<f=3QJQU8C^3~WL
z*=3o(LL-!9W&}!${pRqe{3&Y8;2WlGS)S?;Bt6I93K;-%QEFEj^`}xH*Cg=!!dpL$
z?FB^9#y3HrQqb=NF<c|SU)I_ufl*fac6VTk0DREP2Q^!XYXl?rFyrVPdgu1jD^dt_
zo}~)3YFsvVDY7`0G#)}|VC)@;mZWoaoh<cuP9kN}R>F-0z(oo^y9iwgn|>){KL`9@
z_mTc<1RRB%iq{@wbC(*6p&u{Ah7zl3h1}um(Rmr&sjJuo3YOIRbaJ#K9hQv#>m;aj
zB1Y#4C@Gex8HA$}>$+v>$G=DLvJ@_b6nUoT5rK}gP<*dg@!mBZMdR0}*-Ek^hs`$I
zN%Hs953T)W(tUL-YRB<v_$YAnFUM79_@5;{p(2#5s!b6^8N7k2ih*(jE^_5jse~LG
zP*lg3@9HeQ9NwK4fsoXW5LGCP+t*P5|2>^4slPKgv}f2~H*qBtQDtM<0U{0d6xiRp
zPOq~$u|shnIYe8x+gZklLMlM!JGAgg@mh13`Gh~m9TSMm8+aXO`**8a@tB&7DFz7Y
z5}bH_m8#~2uHr2c8;OZPkMAPbOCj-|KGN94NQv+1uhe6lCSsbVs}haP-ZrH*W{Jqw
z6Y$|hF{RkX@$kwJ)Wp<<@J0T94Jgi#N`De6tzl9o8f0Kn6siS&{NJ{LN7SH5pfBah
zd&u)$hy!xIwDDn|27JBLfEh8o>&82ApJdx1CKbeV*55E};(J!Y68<8R!Ye}Y3j|Ai
z3{{KAlB=SXvfaor@(GEHG?9|LVy;b#8{N>?g_OX4wiaKuEpbjQEi@&~_bD|>|MkbA
zMqsFkHP|TDIC|GE33Q5$Ditt$V#(!;nN7aKHDX;KMq;-P-&Kz50n1^Z*&xX`%iCN9
zsIXHa4A<-dAJ!Kt<)DqF@m_REC{GA_o>+@hLOi1vlRY|&#n$$g?Qda5U+&ELb;4$y
zIrBvD+<mlj+lBfSG8L+{$^~L7RLf{m=}d4W9xe1`PPADHG{9D1r$<EkhWG9XPEOOY
zv_<ww#=2oiAw>p?PjL!4pXj`%4D>E<xGxm|3*3<lwJIkhPcO6tB~n&wDUC?##QVuA
zT%mM!buudJ6AFV*nL0j|02+mY`Fn8S--=?p`o8j}5*xJ1ER!Wt&8U9HY!G23WM{?g
zRfw*N6SI^RysHmDrXr~&y%AzcMMKbkx3#b*>z3VY>~P@8k=@LaU{tM7*B|mOIG;Ur
zxunP@<LkkD$+V6_LjdEymUTLe+qrl#oy&wep)^6Z^cVjp5}BUVRH7YJ0`Fo=Z;`);
zkeJDaN<R87ft!>I%ka`Il`UdyGf=2HDg=44zD4jPK{LPH5+y;gph_~5-87diA>JfJ
z9IbOaNFR;yu(B`wBtX5cg^zewLoS4bSq-MCeV?!yYMK(Nln`$KPP#Y#cPdjn@;_yz
zz$U7+5l|msVkQVk^}pit#YMAN;U+6grG=S9p~n=p>Wq9*%SPX0#a3{ftBvUIXbJOl
z!|>K;1->oYWs|lo<2`w!V_ik3WUY|tfG9>0Bqv}`w0RMkKOkMPhZv}r8QQz31qS60
zr!6q_zxZ8ODFiTu&0^;7UZof_8t;lFtroC9{wQZJMujj+TAeHta^5pri9jmY6H3$Q
zzkkL)CyL*X;aF}{a_wyY0+r%-VhV${;v0A=vAN{=<;hv8j5|;m(j?I*vTMP9Vm-d&
zFg0KHEb%CI3MB-aG>7Mg37!A^r)Bm40=i38F!<}h(lN@GV@v==>kCW@5eS8V$*ZW8
zAXloE9|d-j>7D_W|2B!AUf)9X4F!=Cg%hx%((ywzT78X>&%PtnsYr7FqpAfEDHSwH
z<+u&k&6MC0KlESg@WhwSWuDNcBB!kJ|NbkG5f28?2a~XuTMEcYngDKZQXP@FnY1rw
zk4I$>kX9ZCZ@)(!O;g^Y8A}A)nS`!!3u~G6$%rPqDUmb&DB|YRZJW7v0cX>t-?uOO
zeTFBO84~b(;Ui{d*nKg;g!j{ex=gQRZSHJ?5Q^hZrKqy|=s){goNHcqmI`1`gPIR&
zT7Ym(GaQ{K7SJsK6G$U*BB5wtcS5_Q7vn=ALxc^eiY*7h;Bg20Zo57SzWQD0GH{7z
zuz9u+h6I6*|LGR+bXO&#isJVQb=o=sC68>Q@%_eftu>5ws$B##)8vKTN1wa*Q&PY6
zAuM!(gQtCai5{*ET{xyjhZtkS8L&-a&$~F#Jm=WCQ?4q$Kw6V%j@-mO%eNyMeZ3!5
zxz!tRyIUa@!NGR09TV8wlKcmBNyMGA!5=#Rbb@5h33{ncti$ceW@4l6Wl4=L6>cg$
z+o(x2$`y?4<$v_wf=PIxO79__#3nP>l%Rb0T}4l)p;dxqxTA-#me~VXpN|ZGO8w04
zq)w$JfqY025BCU)J9oBH_H`7*MGduy-r=c8iV#E{sZ$gpn~zCz4y|g~*b}7ut|!sd
zqAfonHyNV!f=nC4`7dXn{0y&J=J<s^Va;#-8%a=hrG&0boL>^X^6F=%j{u};3E_kL
z!6u(wU8LCCG`5sDOaMupoek@^p>YnOGLDVtM<>k%a__m!%?*HXw2DY}>`nqTi2Elk
zhv;Lf@KTkEow{<J+Ehpr5S4%6UPi9x*K0DK<07y~xG0vH5<vfrrvV;Vwj72Jqxy{E
z&fSB-3riYk-z1^d4|q8^qB2k8cb}1|^BCB$ZC}W?D3EYL9p{T)_l>XTQD@=Xz~?`l
zNf`gv78B5j5$KwL-L7OdXy_#wNs@>0a^a>O_o=A=T5WdO5|EOV%=-RG81rBJm$H*W
z+Xrd7g}fpM$B;lp0VPK+akJPaR0(;eFRYCFVMn`5GF%~sSSB})^$CF|BCB%fBq2oW
zOAErAQTxMGo=M5_NsCQ_7jcvY@02=7>}ln=v?T&cmo=YxS9To+g$}v{9n3ye|GqdW
z$C*W6{TIHJCF*yeO`Z{ps=^(!sxkWo2C0^W<dd@(!!Oli9`!TOAyGL=DDsgBK}qSZ
z(vre<rc4$aU1eby+%@1c6RKZGq@z1_C5hVEF%BKwCk<h)#$EKkQfUwipb$@ehIS?G
z>g5KqDYad9evuqhw{QnTN-TjXP1XH)Ro7<Dn0eTJ^xmcUQF`)+%tzH5G<dElVo}aN
zp5CU`W6a)Sc}_I@5NhD_AIem~EqD-^{gBatFC{(RB^fO-cYG^Gykar?)0L?u{fK+u
zm8(Z$x!=E-$wWW_(M_pB6DR8Z<=-43j2X|VokjN1rAk2dl!?Q%{V|v)hBaX;`#q^h
zzNCPn?lm=KmbsxcSO{ls7`=pl1pSIB9bhO=$~<uT5arJc-%J0MM9+3n?`7$-0b<aA
z5T4e_R7h{)1#>Xro1z0$oxMz1*C}Fri)WJfewcw^XFh?bz$&w)@L(J0dXZz_ikGyj
z@Ky7DYvN7|tZhKrJ8D@ik*(u*Sc#MR=nWX)8JFn?8(@6+Cvy7KB=6u!Bap1b)D-g6
zI~L2I6dQ>h#q`V0qVpIVA8MCs)Q1`@b>Jh0@%BVirBA+5hdU_}nY3KKL|p1${w_SU
z%%|O>-VwT7>34Jt2qcBB7Zh76=_Pi7;DyL~3!b4!3IJvzyPGT}3+kkqxjVgV6j(_l
z+7&VMd({~34ZlP)g_VAgn`qzjR;dsnke@^m_$fhC5vxu>eP%T&YyUuY>RT2!S|bO^
z`UFLL-k<(zmE@9HRHJDMvj`EU_r)Y3lRCKv+;g-4^c<BG*X*bstuB?yVbh}m&`xxq
z7~%kB>Z`un&Cw0h&pn9@?4bHb8Vh8i4uVnLfJH0f>Wl=IIr5T-YoTrVmaX5j{&^|y
zWiR_Sv@E0vksjz|3q@|mGPewW!-m$($>11fz9`d}`U;PM;z{xXuF2)f>71AjKBC-V
zL*eO9vPC=<CP}7JJn{Jy&GmeM6xNdxzhoO3Wn3&pvldH+dlLE=ae^=m3$Xg*X4|G6
zL?;T#{!%p!az4fL$U-UcK~f*g{m`Y!xPoFLXIo2!+R0#gAy#pb%I>~1mm@-|a3Ttm
zGtQ-;W`Z8Q_@NFO>5{z*f}XHGq1FIHc|{BqD`zO3Po?CVIf+(*x|i_~tPsEL5jb<?
zU72HMkK;cr1^AOj_B1<+UII$9c85RR42OQb<i4M+7OL1NqY8rd)FQJOStR{13*;Z*
zb$Lwmqbj)Eh+m*MGd8=(*PUQL55&PSGu9z8k8FL}VoUp$lEWIa2<H@5K@K0gz<dm(
z^dwYUXe};6k~(7e0i0nz#9tb;B!$fk&-5+wjxv+F;o&<WAc0YPPkmg_j0gRgN*#=t
z{Q5Pl6;p_ldRpM=`WuCfW>00{Z@L~z-{06r)An!(s9Fx)I-`=T6DP`3@p{J);G~5+
z25yO(ZW@thNK#R+j3INTm-mPr@ra-4q`a~of5;Q9N&6LS`QgrTqugStjG&i^VPZ^a
znQ+m8%$FxgA~0VjJ5$vY9GRg4UA|k0xEwc1wHOsr7|&JV_b`<oS>|}KMO5`tXaM9m
z=JrYt5)ceRCdw8sHPfN0m%I-~^ngzbkJEUeiaqL3d@8&3I9dPw5T<vi2kmrbvr|&n
z*<oL?t^ItS7kz1#m_%2~>!MRo(NKGnlx#vr!kW$$m?I_$WdUbc5)uX*P*f;Zyoj)d
z%L&zUAW#8(_4|E=dTjZl21uVGZX9uaJ8YX^*;*+9H)MVhe|elP?wjEORLn|nVyM*#
zL(C|JYqPX`&QUL0qtovR2l>69|1?Q*T~3z}Q!(Y`4OO5!I?%fe^E_sCfo;V=^1=8%
z&!Z1wuijGlGKaXA^<|Zq>3bGXKm{VY-*h&OP;b?ce%!%K!S{uYHsKaxN@&uMiZkAh
z$raXA2ua0+A)mBvy|<y?$A_7S8K5;PXUpeWwb4_OCIk5k?*Gew_3>%}M_DFOzOE*O
zmy)r2;-;83G^_Y*c2-mXvr^qrn{gSYVTa2|b~GsyxuvLhgk4>;up=@Q{;{!or(cp-
zWP{(Z;u*I1B?aqP*J(K`Vfw_Y%8G^S>lNr7%CQB<U2XS4`>JlgPH0Mm%BVK1K;L40
zrqu<0D@`CRVhfg@7F$p!iXMvjOv!^fmFa>KCbBK{etaXo!P{O!A7sjS!w<8bKGSDV
zon=S4piilnU_b&P%szVkh^g90FdYEwzVl`Hl&ZPH{k&wJx9w^&iNM$luBU~_o}(I#
z(UmYL4n@DTNic=Mz@n<+15gS)B<#69!}O8#4DP_WQ@5vBYYMB6E^?`d?!B)r2OaZ#
zEPhhD5|>DgU@_zfI00UaXk+O24Z|)r771gIoFwq0<2q@FQHT`utrZ6<_8Ni3#!Mv%
z?&?K0Tbh_#2koNtdoIo~c_x*d33&25f9kFy8cz*&li?yzD7$r?zsg)BRU4f}xaf%y
zA#m`Q=!7y9GUbQj@)G3Geg)Ue$BWr)2vq4~Kzi!0QZK6(trSzmrCWIYgO&%vVzKWc
zP#_M8qOXQmgZ<Nn+o=H3i~^}O7>UI)Yw4Viv7%0b7|Q$H^Pd!2l8gj7eT*y+kUS|-
zKWra*Mer*i39v4Q%DVtvGWq7dx=&>nlWTb|zLxiH#fg#B3F(N(OFa*oVN-<^hGsod
zzfG7LE}J1{+sOyk`nn}KQ|8Y&I{@qVq7FBuyXubJ?!Zt{>b*!>pKC}QTot?${bET7
zI96RERi|`-nipp%F)1@XCBtsH$U<U&&^7+8QWBf-kikP31vUFn1(S-k&=n(Kwb_3(
zfq?6_o8jdwxf5Li4lLOvdqD>n47UL&Kvk5aYB2tECueJvBv6C~G<#I5U1E3XNjhtd
zq@WQ22~cNVa5)@s6}%%`yBFA+J`9NebSVplq|i@POAb!*@nsqg^oF`0kVVNK+Th6H
zU>ie2J#ly0_SrutvG^@YI|!t@9h7UP&2Ujtmv<Es?x+Iy?9^ZgYB@ouL=p9ET|2&?
zN`#wS{54BNtz{rhW3k@PN(sP@zW4hdCoh#_uuNfWlbxj<rnhAY(`N`k+k&!;yUCEe
zETJN1%S^EKBwVP9+lW8X!LFFj1WXY%6j1PB7Y9yc$=F$fzG}|`5wbRu@GcPLqfq#R
z{yD*a80ab3KmDE^qNc7^o9v|ZU$+!`&T$E|7B;mhM8#+R$dltIVZNzYWSQG~#+Ouv
z@hP><Jmu+}DVpuxQ{h4obA=Qd`~E0M>N*bUJ`)SCacE9T1by>*2VbQys?y$ru1G9+
zjGZkOrv+I$42I=loMd;15t{XTaH$)K_y>Rh?v>siOw}A5I+n^omcu{Kj7;$v@Wh(3
zu5e;0$j;E&a|UxN0LU31j9-C^OSm2h&3`dIYVO5b(@UY?tjjV{BM_G)<UoIw0;_t+
z9zlxm7cxYre%(g9h;ET$XCcI|x=5ZrUsKpWJ!vZXL;eYweSZ?d?{yxBY0wmTL!Sdx
z|M6eL@O#Zzm57!ol%v6S3Fe$ZL^E8P=8JL|<i3j<u~1Sb)So_*xik+=JieUVGwbLv
z7D`bJCGqED)feuv$K?$YOcTW%V>%2&Kya(LO>CL$IiJaBG;=*U;d5Kowtbf>nVT}a
z?bj`6s$OojCHU*7%%i<u{iN76lP@4|BA@vpC<Pe^+UAI`=L6^|IhH*1Pf(2=8hGBN
z;3MwyS%T-6>KC6wuTdx=U(cCS0E`D!V*atQs|H4BGC8ahph_K_hyV|KH0LM;&NX`?
zEF2CWCAyxmr{S_a*ZMU(4_?v5O#Hv|QxBq|fDoJoCWVdNROL1>#mt+!63#)~w6o=6
zr*UR`*wl%28^KQAn8s7@B_+BR#>Xfuy=6n>1YhMG70gtiU8ziQ9?q(f-D45NtsRSf
zf|%_iH9&P?JY=mEn;fS6^dJQw>?}21El9uOxlXN4DFXat3sd^d!^71)H=t@sO6g!r
zZJ8xK+lgy4fq)4C!A?>I0p^AGK!Du!vY|F&y#PLV?k+R+V=kY9O^L;l4sy{D6&6*J
zpEoRMVS9Qz#t}%wB8nxfiI@iQecb{-{3$bZ!uD2a@9bsmj%79;y`AmXFV-%mV5)wb
z$AiwF2y9Fjfhh%6x}Zvw7RFR{&Z;vpY@e7Cx3P|%ml^O9elF2{`b_weAxM2G1Z;0x
z+au0!Dmah?$|l%<X!NVLehalfh(PmC!@DX8fj#&?7E1Ih`J*Z8^YMv<S3pUhV>pWy
z1zi&cT$JK|@lX#sU&cgY`o->`SX)Z%u&-_KA6Ya4Wxm*HK^1F@aE%!shMqAs%k=ud
zymF(ajGAOjEPkGI<sh8O5Csw~1~-fk^v*V&T1jmWlRu^t=Xu>qtHM*|eq_m`NP3@<
zlfK|y?kG5glWa%<qC|l#^q-7*e7`Ouhgbl5Ai*c$!t^wpWKsOHYua@r)p#1K;C=Hh
z>F5p8A=Hbg%Q2T!o}}1dTit@Eo@A9QcCb_#_=1xnu)bx&wvOJwk&&68LWRTkormI!
z@q1N!Elj2?UiX%M(Ke8oN4EB}4zDoKFPo!Ou;sbMetwe(r&5JJ6T>f+6WhsFAap-0
zl@deMPdNZ5aC{6z_s3&GKzz{zoF5!2Pgc^a5-mF8@614vMN+UNtF0#X0PdVfTW0w+
zFlK$rFWL`8Vmxm&Rk&k8=;5NJ1`uEInc8P;qgCYW>ls{y*nf8QZ~u8!PGCoHAC)ME
zt*gz%m{c4AbShfq*fbVNTtxzPEQn2_4{X~l@J3?`4kEkY(w?IF94W7&Czq5F@!tsP
z1V~vXci$}=%pty9EDDxQ0yPhp5;10U9CMGK;<8Gp;SNPsxKZ9Uj6wlXWtrVaKl&x!
zJf5e_9b9BPS#6UFgxLjcW(t%Uu~2uG1Ag|ISVc03f(tXHzy#7gc!}f~z>n_zjnJ})
zCn&X<?x1=EG}_8I;Ys@(Toq#2wp9!(!IwCF0JS`S#AS97{R#}g4HMh2x2ThEWEsO9
zs69pd`yDe6{{Fj^AkkQWPC%)m|EsDDpK9s_poxS%{lHp~0ayw+e@pE#jL|y!Q0@##
zwp{}4A>-*y-v>!hB^!&aV)*(EiNmGj1E!*FN{>R!6q;q?P&^=z77HMi5Ey{om35rz
zRBR`WNDGYizI&N2(}z&h<$kd=p4EGB=65A<6vbk}WBe)Y!0#(6CV{F=C1-|z5rsuw
zs{pSH0aYG50P8Co@%?ZsOh`W-$S5O{on_AkUSLbPg^DTVz9Ou^VYd3C5b6rfhy}So
z*tra8%!04fR~fhm_kN&b4s?*&`VVO?Ia|Br5Mcc&@vsO5&fs5tT5Lh3j5JKBoCU{q
zdYI2JXJGb>iUo#<ETV(ef+Q5_mH<(kjO=9ah#4+Iod<1{ox}JEpCv|EDnqgyU*O}m
zwvu}Y29HBV$ys3RDs9ME;B}^ohk*;M7<WNvjT>enP5oSre4neNKx+T)iU6EyfqhL=
zf|gxoKA<Cs?F?Wpe7?I6LbQemf>!Gw2W%`P6oon0c#1<@muX@_D}CR_Ga)WSFN&+5
z7)=!KN?uBU2H_%C6Pdy33qTieQMjsY1Tii*T#3o6Ljf3~l(}}NUVKXMO5d>l$=}6l
zvYRp#BTpAqkZ*<DuR@@7W_pJ3q5xzOy%iDkMq_FyFih0!XnoJ#f+<;)T3P3&oDJel
z#fdfE1=cskX`rN(elV5hIgwldwR>tLx+`v{GT!US)UW&_CT4EgB`rIDurZZL{6~3L
ziyeXmlK9{A{``nkU6A~d=^0WzB?-N7!R}Ji3)4rS$%S3T6UagxV}=o8ttB5iPg-@3
z95kg(vFT#_-J6<QASy1QrwK7?%-*FwSz#sa={3?rJhFTm%Fj0vqk>b{X+});2W4UC
zWJ??WJX>o_X0^HY>$Mc0T9i#Ci*|dsn;VIyRc<!LSFOTFQ;1Ai0@v~hZ6&%oSg1FZ
z5kz6dQ=&OI-$36r9s7m_qW)Mo9hd^Dl6_$p6Wl)K@|3KJz>WdY@zWBZ%SusFqoeAT
z-u-adE>nfbOcQ)-W2#MCAH4?{tGbW1l59F_{mL*~%K1ObepZU(50S0sauaJZB1Qp}
zuvV<r?G`1lRevg@g@@zBN8OE=O-ebO^Am&kq*#(IElDb4o2u#~^$WHxNTngy{sB;&
zfg;{8IfN?diC*uzo}?iW7znY_L5WC8v|9L5EWhYGdi2LDXgjMUqA$Wyk@FcZ964r=
zDb$JGgpDOQ8`zw5-Bz#J(TAZmI2_>q3|3w7>~idn1++g-Lj&|mE{LX*^@TRGs8IJc
z$eDf>P8Xk7=rSo~Dqpt{mC3%lcz(<lwx8LVwHD0p#b#NK+yzpvof|<>C^X^NrBt^3
zP^mK5zpZD^u!X^>;)6&1zAg7SOGS|^rtvx3#vIAtsN4|^36VTOvwfpaNrJ;B(kiF3
zS@xSbiW7_$U&o@OOF$p7bXOIfT*--WT?72hT`OoxQo`FUnt9;TPb~suJAf0{*B5<h
z+86A>&rL-M%|rqAF;>%sZ~+Zi2o%vNBK4Skmen$T02~Xjr|(ZL&V(Z~ax(*qz@H5y
zgl?{@)_cG$Wy~f)s@usS%FsjnKF=gBT0$evlJy2tL(%@}Fn~6)S@DZjW@Mo9&9dXC
z@%mhJ@Vf|frSgs<GI>U-J%~68QZI8x$$fAAnS@A`2qz(jU?a)nVt%-3;R0ihsfa2z
zDBt9}kz^;sI8kO&qDC11(hWGC<q#LDg!C6{>}W2Om#^jGzo;_q+kMk|zg$uDY^`xI
zLniCRmV~8%eVpfqCx<=GyvS7%M0=7je+l@!5VIkrtiTzLI+N62pcq0TU;su95PFCc
zk7oeM9b{9s$F0xn(rw;&C|nfyb4H>9nKza4UtBL5X%6?qfHngpD#$I)<786w@zIQ+
z^^3KlK6R>iwl<%Mg%^{=7(xZgDpZ;q;82%3h2nWmsNQ2HZUQu^>ESb_W<Zu8!+DF1
zl;3MyLlsg*z8&fqi;s%2(7v8|^gtjKVEnO!T!afw^|HN>yX;^#v0d)8r72V<&0IAn
za-RD`bDJy6vQ8)BN}bn@L30G*Vc_A)_J01S*vamWz$G#7Oh$beFzP0R3E^_T1=2kz
z06NsS?_y}SRbr^%_Nd6;#h?jz&;WeLdw#s1G!fgzrepTlKj|&IW@(EN=<d{q?exUP
zOT-Ste>K2*GI5qdPU0_q&<Ay?({U;;t!4eJ{&)V~kchFQON)v;qojKFfZg<>86|Ye
zFz`g=PmUCn>rMFpwga@dTp+XxcIjiHGf$+Fo*k!O(!<|ave_*0i%29DuaWDr=b5|s
zOTe<z@<O8%jwfQ6UC{^aT8T|Bw$eFDItJC--rk*$0Rt=DRV7UuOzMUeL2ZIvw8C;F
zxSGYvutsM;z!jWlAjgPNj2r3QBwMlz2{luc_YeX-u|~)Sz7n)i<Iv%#&jbh9CV3P#
z9r+RLAs&c`lLX+wM4-%F-f_#?JFVpgzNc7j(FpMr3WVj9ijLo_@nG0ZTp89~Xi}O>
zUH|KJO)<NJ805#w3#O0^D6t2|I9*I8ld-jMhLQFO)=DJQ$*{-xJ{35qL_;(I^|ILp
zSj#^%NDvOo*&=r(6(I;CaC~aG-nAi-OT?w(7i+D>#U^*I2vdS3`u0DCd;)w>PXbV?
z%$wR_vlOIhJB%rV7jb{QK@L9>Q@}j4znfeRPTp^mZZ@KR_r|`KyJ<q=&f}0w!!#!7
zxovu+5-d6o!S9?m3QqARX^C*0;;72_rahWv+dOuUeLRH)x>yr4<bE-(;h%Hy9A-;v
zBDoSZR*0p>!L>0SD&=fk7|*vC<xr6`{wOjZV9f%x_Y?E<mTf``N74<0JxnCpNYHSB
zdt1}6Pt&lbs2OG~^bv7fgfr>vOgFq@uLW0wgA~-uncrimjBQY3K(N6a1cy0>ag<_@
zzI6MOgmcWeP$l9`T`ZoYLV;pj0de&}VLSTi1{N#*i#I?#5D5*5Vwqq>^-dzTP;3G4
z#O)`gsE965uCb$;DL_R~GBb;(gli^~$#IL6O9m$|=&3^0Y}=(obZ5<mYj(2pat44s
z*I9&QKG%^bE^Tq>|K6_%>EV?NBnK!ST~w8W!9JB{Fpdi{MM!Ls`*yhz-l?zT4`%4W
z59=S%QXoB|jo5}Pk_Q^NsoeTrbROHYOD?;YF~m~ZH)-YL<kK{vF|hr35`}&gRjuEW
z7_(iYoHWxgVOSt?xBuX$nLAM_FDXSmqhh`+*EPh)2r#%Ev~85=i%2*x{9S_@F<|g>
zxNLFUH;{D%fUgvVaYxAeBnQ@yf4HpAPA0`8FbiSnqtK!|zJ%92Kv&2Gu&^QfapGE#
zG&-idjB;y#Y8$6GI!v_=CP?yND7N?VWe4<tZB$rch4dc%5;c#M>S&`VZ4ij@<5i|9
zP^U<J*aG9&UV_`CR`3QZc3yd40A!V%zC%uR|Dc^um>!Qk!hfM{E>_1YN?{QU=oQLy
zYe#QM4Pn-ixq;-nUayy#6aY=<=#S_}e~)@MY$UJ-0)*{cWe+KKhN&4+MC-8#Vy(Z%
zVuTT&>LsLO7|=D1gu#MgO?ZaKu9GR}{W%OWL4KEJ66#%4+c4jfSdJZM2vXnjNJRm&
zq6$$&mP0zaB%$m~IYorE?>AhCHhMM_jP6wCtIt#HjFG&93umQU3ZGNDrN;2yK|3xo
zIYdm~lcI3^_m0k%AO)x~1ZM2A^oi>w4iY~<*h>L*fKawmDsp?b!UhWSg81+r&m`dw
zMu_heG{l2LzjVUJJ(Ho=HcHQDi<e*#q=X13?gqwu^?e9OV{$2bqGgTV7Bu`|P!3Q*
zL6RKgz&hhUJWpaq$U7Px#lpCdXs~{;oNS{DBZL&K-!?~f%hDKtizGsJ_3b>H2n-?~
zuOufZZ-lhiwhyI*qb?rlft7xHgHE@BZ6G06ga6ylxL86<J}3~1p4L0XNQ+(ZuGnRf
zGli-Av0jXB0omZ@L`zX)>J5s_=fm}iL4B-YuC5u2nr+a4Q=*YeN{z&}V@}ydHeGg7
z>U}604H#pP?2D84><#RXnPe^i`7Qdx&ei5JW^dxf-Aez*A4t_np-f0#1Xn8koYV~h
z*=nW0Z76%n3Gt$6mAnj=j~UEaFwK>1+=Vtvr0Y!IKzi|-*#_1;z=0%;Ts@pD+Y8CD
zBo>~|^27pI@H+689#uIYr0FDFLn!Y-hf+TDY7aABWT9MO;m%wP(cZuKDVE4N05Pbr
zUlkKs4i+?pOQ|9%#gzB=2<DKlmYtj-!7c<VXt4)W#4rk2>%U8cR>0?`ozx{Ja!J|y
z$$pz)B6vw6X5w4iB37u2re6*AZRj|G!|!Eh3B&1M<0hT@Dfms{VZHBVpGG2u+@dpR
zLCJAbw{$X?r{N|pl8nM+aFXuZaUp<gq=G5hzCtRIz(DAgZNnK#&Z_?`#i+_6IqgS8
zzFWy7dQ{lTHl;<88I@;|Mand|+%Un&8^12zFx)XcW>#ppqF<|Bl65j*ku?%T;1S>Z
z!=L7H3T1L^q+wFB76Btcfk3kh%z+oACP;B`*h&gPaNZ38lM-SbWbl6DC(#8_GO3JZ
zG$)X=ompmF*bR{HjZlafD<X*w$)+>AjAa@lrMG@%zcwLdm|}};V>lJA2y&Aw%#TsV
zcYfdJu&aH1j)J4%EG;o~*(Id{4&@0}LnxoIgyM89a)T0^xopl%OR3NydV2V7R>4N`
z5(f4j|F5igQ8%~oC&(vS6KtCV!9<Ahv*LP$-o>z2bdpr_d!cN)sju{8@=KpFc#PM6
z^!cZ$Xa$_#Bw>(lLAc21eRZTZ&!uys-u)BzqK3E}Gy`G0-Jg`nVfs|dIE{E>DyfD;
z#gq_VVLO~gAn;#s%X{&B@*t=UxykCfxvJ@2sDOa%fyJ-}u&TXsualj^eM1&-L4asC
zZ+`SMza{nnf_PPxHlYd9dul6KRLmw=AXC_{QR?qbk!Y2hCO|3DTBHGryU9-`#3+)%
zaFw~Ti3CFccZtw}L1A&X%!y`Vn3ii;6BF{t*#Mr)2nTLn)9`Jm86!NMvE;X;cDN%>
zlnWuKW@Uak^>+f#zxX+_G=#X`d9eA|0w9<>L=>W_j})ciheji}omg$@J8=^gS!R6;
z$K*&ND*u(ffM`59azJPUJul*z*Kj?KRY8LR1RxFA43`xmw1t;6$#~&e<dO;_3a;2b
zkcDfja5nPQ|BiP{#K<7WO}PeOn#<2vU6JBye)C0Ze!?ljNQj(um^87-hSI(dnB?Xx
z-u0Lt@Dwj5Wn#b~*te(I)m=$r7KL}Vs!y}wipB9TM49_op)m6$Jm!?&IQ9J+$pG3_
zio>HQx2%)H{!?yLspg2G0;|cLDwXD@4r!kcktt!D`sMt92Z0YTfy96`sSr2Z#jq?&
zNopv^$Kmu%RWtVm2n9stIHoPbZc9<^GnV3I46fK8%n3%4t5lNl>%oZ)Yp=&I0-qbV
z>;eCfeYsPs&7C8BAO!PTfWJSN^kx}JB>K|hsP&O)iMO#n65jYA#ep<pcLw)Ff)dRE
z9PTpOT4S%+XVFy=Mq!D^e9zsnp=XxJxdMVnYP)(S!~j==#8fHN!}Qo*VQPngnLGSX
zpv62z-;^gyTD9(@&wvXw=1^2ER15QRCz|{yjxFhr#4lsTi4gf}`P9A?78*Daw3`0H
zVtom<E^>p*WoQ)k4-DI1;JgYXsNpvv91twmU0x0`jnsklp(JnSor1We+@*ItkZs(t
z4=H&|Nd0vrXnOTg%~D5&+onoMv_+QMeY7CtCX+o2UfC#0QYsa$s*jmTD5~;A&alxP
zjmzNs+sGPKY1rKo&{mY>aWp9;Huh5@8@ck39>kL&cRkTqODJ2n8mW^<mu#A3e4>Q<
z;OdUKAEqKKH|%z{#tkYmc;HeyGj)k(`;5?+5{bC6k*Y*aH|E&;v{jSo-e-c*6u0Pz
z5zZ1{l8aUo2X+8!;z{&na0Io7f*2$+kQYZz-xQ<~`QEmE;gQ@T$u!rnF7<zpKMt?$
zCMAU3JY1hXN|t8>!e3y}WH$FTyT}sHoudALWv0N3Zt@*DgCb55c}`U)-W}8x86HFU
z^<*b0i<5v>5Ti_(;!dBAr9`hoRqwPw^PjNdIK(w$Z^E!rHcItMfOd<A7dRsNB~c=4
z)VeALavZgOq;+kN^~mwgH!jH?B&4LRVR4S=_n!Z!lIqiCxtO@X_{p1^DO21+Fl1zO
z$pHL7ii*2tZyMqWS!mKG4ogBI9f@i=ahGIe7qLC0b`mh27<+jvCL+a%B13)ffpl48
zy}S0hsxW5Y9vfCB$j-9gaz2m@UL8sw{K(cl`r<$7qB0fn(E%aij)Iq53u-gz0=G!2
zR7{>z7#ATr=!2YL9YYy*88(ncLt*SpV#S8CL^)(G94gqVB*5vM+$Jz&PR}tq&e?3<
z(O)BS2tpVi>Ru^CM>`xn?3aDD-4eyNm&#>HJ;;b2Z}0!X<*-0U_(rm%5?`B24S1_+
zlu0P$4};>qR2+2HhlZpCMf6|TPAJwE&2<v!atgA#ekVL3;tjYIe+IkwybanEDHj9S
z0twYbsa*pu%<@%+$>;-%miVw^qn5S8sMO>tMiwZ!2PO*aVPGd)u7kn^;VIpF_3a?W
zMMFZ*s)7U~{WS`R$;1I_TFGsev3>O(ojKwN`Qj%KSM0Wm2+BiZ!vM1=xM(S)^rx{-
z35}R|Ar;&Osi4*?Oz1vwT{LA67qvZ0woR@VV<S=NMZ+cZa@O91KPyX6Q)#AYDm4Bx
z=<{>9q!=c|$Q_(Kygyhc3M#24R=Z;}Cf<j{`Rzm!$j=EH2PX`US}M-b7B*AH^35dS
z^B@nVWMNlBF;Q|fuuUK`(j#O<eOvB?2QG-8q;~@_PX8-484`870-oq4H6)x?&MxY4
zt`6MNKt>^Ut%A<?rOrZLq~yqPNdQe#mH@F)(Pga4ED;#i&iTQ?TX(b{DWtT1m$DtH
zM0*(8X}yX`<kMIo(gi1`lPYtAdg0K%_pQx*y0n}@#4Ofog2!YFyEj^XHFu*SizIMX
z6$#^bk3JA<T41DdpQC=lLW(^m&CsBBTtN5^RS=k-lIHGOM+XcLhfvQh#zrb;+oZo>
zrKp43q2Rq=EF}lsEr?bpps_23W`-f61mZOd>L%-rDU>XoARX@u|JBnXvQ$loy3{5X
zVaf_M&ItEBsAUoxjC56dpxJHa+M}A(<p5Kq;0TfN2RIEwMD!xc3t;4ejD-NUv=(`o
zB8--t0pSbCoy3=kbx3QW6ut2Q36QgMsbAzmTTY7PMgOTNd%+9LrkbbVmPVVnR!<ig
zv{w+rfkZh;k*QRrRcxO)-jbDO(B<%qCOxR@m>2|faQsr-BvaNiif?XPbH|aQkkdRs
z|Cel<t5@V6>cp!|g+uRI%ZSBg`$6sBU9Jrycu2crmxY9S@PCnncUcIA*Azaa#tFIw
z4K5F%!)%C{8F^%^$09a5&r-uZnWzLqUWA6Ax<ul4zTUm5C=KK{;O6m&=r%rYcPMwm
zE?YmMmQ!{Zb3txEvX$e8dhvA){94lY%!N=2Hn|`DHDC@Ej+qSF81}F<Y^3+nEs{C>
z8y<}*s|7l8_L?1~G$kIIOH~W9%DxIqw9iY%4#M_r>1=48k3%!Wc<}wG5K1nE3vO2B
zHm&T>CE;GXEbL!G`#{K9deX(uN&ybCTth!2f7tOG`h87AO~%XYYuog2KX^Gs@Zz(~
zCW82#ml?8Bs1_(|@2B8v6C30`AfH0&ZpG>KZG&r6lU1MvQOtdr(sVn`&=5)jfnf-S
z+fYy<JGw2NM`hWn1Uc6%aF$6>7EC9W3%}<!hLU#ws=+Pq;P{T-vUQB?eoGmq6o?Y4
zmVw(OjM>d^UU|w<Lq_5G0NunzW9ePJq|-BcMv*a=nl_f~HY;7X(9CE|VoNw=5I+Hy
zn_AChxvap&O}ul|eNLYv9YaQzK!YK()y!0n(-$^aWQ4t8#0wU2+zi2Y9))E#@Tml}
zbqEw9D}J$+O)R&IVE*Kfs%)l=Qg9z%QcHo)P#8iNq9M_W$KvT(uVLtPo4st87?{p(
zLQbMxk0q1vi^qh9mibGF<~v+pXsa2%TCDY8lob`>g{seV0SUqDkF+eSZ9mW0>g<#r
z9;FyuS^`8Mzw>)fBS?JaU|oe`9eN##9+NGA8@}3Y9{|zwP!e!!=(tkOw(rB-Ki{Q6
z2}}IgQa#FPo_xe}j&~W@1~#`VfrJqJ(nP%sAe_%Gk+1F>Y9UE*bxe8rhacm;@|-16
zfq){_BhYcPw0slz3_h(`gi=V;jP_b}CM@Ydnxy)B$v@_w3pLBS1p9}$XcGSy^rYsu
zz1BD4EC&zfMcrHcOQekJDQch3TIANwWq>R#Q)irU+5K%k5WxWA5zWHFE*Pk#v>@=b
z|0&HBP2m;SiH4;V!1)O|H*xm;_W&D2QMeVSu|xLPOzK_MPRg2ck$}Dd^|~a~dQxp}
zppkgN4oj;+#*Oy_MD=ff&OIM1LJ}dd95wM+KF~*Y#T_WM=QEJT^)m@`gn8?ex3Er+
zhnP*_5cs=THBnai)c%X?vp3J!7*mI>l<V#YDa43*AO7~I#eM2ZAf=?S8e632v0UIQ
zsCW}%dhjVCQ6dcB2$#VtoD^LTXk~=05?TE5VyZo&ArMHTJq>)Op5R^XiAR$jzXP03
zS+=3*!Drgym37Q(jrewI`(ok>9xloK6@%qH`1}8u2PhYsXd2z4y2B|1LjqWz$gv!f
zsydqrv(dojDi=N=JjOk|J7Y;SVU^_+r@5&|Xt#kP&?6=kpgnQJ!c~OtvQm-dTeZgP
zmiwPB${<Zo*bDE0`T-w^-&Op9viSA3)K+k?=z9OVq=Ar~TA;O25E3bRtd$52?|mGK
z|G)oziKlroxQrZ<T(KZ96ygNIxn>(bkOUI->c}0_exU4IoZIzJN`zaHah_aDw_EWS
zXH_)nr50GvV_c>%(!MvE%~H$Gv7&cwEhv_gk0wmol+>q-f!s2hA}0F6^(t~CiyG`9
z<{MbSVobOure1PzXnyU3MuXd3vkccQ%L0*gAFYrIs}c@~I0gJPi%|3-W0)4$EzsCw
zHDv@2o?9}mGBT9C-_0f5;Yt38_Mv0g`6r4d)l+K{1F9+J;t@$CFLW^A(gxDNCAnk9
z7G1NTpPK|$64)SBQ~nn$!+aJgP+{x(rpSBn-H&igePcv9YMQCc2TY~>!Q(zwny!zf
zqTfTR>Bw|&o4Kfc<^mDE4zLT9K&HTAws@eU_jPQvpIlKRrEKLVKB$W~jGXub#W+>k
z)Di{@S_DeBvr*YI)bPQd?Pp0If{bv;#j^7J0`N*HpEa;Z!VVWk3yj|*{Q|Lsz2;r~
z8aPCmLEshy{)RES3!1!5Fb@=Bk(kIQA4ECWRF1c%#IVCT3UO>+VZf~|mLYHWsaclf
z0l%jQzQl<%$tq?>`(9DL+BC&!_FpO>b-NwV!6Su-(-IYAKi(+`u4J!Rgxj1HCqa_p
z7OspK0X-aSIiw1!>MgVEWx{vV5G=z^Nm~I)Cp?K*Z=A_%|HCJo=u`J7t?cB1DwG}2
z^CnI2oMQm|7(`9Py^3}#90|~t=aNSq6W<`dZtwsY7MO|~Fe6+Vxg83gk(lI+YQ&-Q
zm#9e<QqJQF2GVIh1t>aP1!zen&`mpk@ntc8m)h8_QvjKi#WL#T&jtWZdL5V4mU^gQ
z5CvJnFin#86Dv~U=<qiK0PSHr$XrO`k0eGovu!P#BmQQfsO}KlUgA->-x{dsCbnZ@
zo@8u@GnfuaS&^+uN=*w?kdZ7FG8*geR7z-f;Xz2!f9`L541|VHDziRvEF>`cKd9t5
zY)rv4vlN=MPoBzQyUx5@EDGy}rRBVpnia*6J(oA27~2Xx6`VU%@A><B=%U8lKK>An
z4i;Mo1ctAW`MYOeLhjk@sfHMk)WBc2B<}1!y8Snauz0a&@=|t5CD;?Wh+a(7<3-__
z`ng*YKKwuw&wvS%$%F)R7?EoJiPe#!_t=||jJkf8n-~nA6(9#<q&a0_UirnqopqHk
zbSYnt$NlJhb{^tY7=}|+Vy2Im_l3)ztWGAC6o6+-YFRIF)adL&jD`vTd>o<>-^p?F
zQz3PANEeD)i_)4Wg6Q^*M0*1Z0MfvyEQP%Fj8O*k*N;s!(J(+VsRl`6taqL|M$5lO
zSDE%Lw`rmt*pc^s>r)(oe2;sbA@L?=)M=!+Avq!50G<G6EugGaM8u4S6I&vP#r?nk
zU;mspA@IDP7cEJ+$JQJhBckuTWaS&Y1Hy?%;)9W2#dlDuhQ(l$<uwq0*0=z$V#AVp
z;LHEbufcWzXt*B1jVM*@h4kL=N&T&ok053PEs-CFt;g87h7%#E2yOoj-Pxk}@+uqw
zF9bYkT0mgLddaJg2#Q6<_h>?~p&AOu|0&kA|AziQR!s`iY5O@76rH;ttey{`a8+JD
zmxWT^Ar)~*g=0$|{O$kJOTk*T^MnfW%UelRi(~<ZJC|p}qm_}m|A8k>(IdIK;?IrL
zZkAbab7aMv%RcGlt=4Qh-28Hy`&~UU>UYz~FRr{3MJ9Krr<)`BO0-hF74a-hzqQi!
zYX|&%rFQ3!eu~5PMxW}YD`{&bE%3!2{nsm_BV>a{N60R$R83kOo=Q(wK3lP)Sr6X6
zBGXM<UaeUfnTyiaaAkC)Ir8ReG&a=qwNd-BPgu4&@^UjeQt?(iZ>2dBvPYvMqff8g
z;S9d@;9q}VuurR5Q!9mPI$SKi$zJ>ODJj)rWuG2l6?t=bbhy$y9rZGk{dLw=F%>T#
z9d3-&nj_)^z4GaTvTOq2;AZ4`_A8dJ@>a;Tb<<zzUGc4#JF+DA{!Zrc<SXC)g`rfA
zk{5AI(@*)Y>59iU@xdeAf;UP>tT$?KWohp5ulW)_pN_dIKD5}C&EqNLTX>PulRuh1
zS2zxPe2(|VZ{YgeOTeD|S3bqPcqgC28Zp?7rZ`AGMP3o<9X@pMk^TS78+o5MI(~YX
z&)}VRe&<syS&HN*Xy2bGC}NNW7%fKlp8eI8`q|STwDJ$q5Au~fU%3gR4c$K$#|@(w
z_1Vwh4^uE;?FTFWN$cr+Wiy={S!tdgS&<Ku+p4*l1G+zpDOo|9oBvL<!tr}6EBVUk
z=`ZKG6q$4FafJURGD3@^Z?!f*c(e5jr(1KCk-Yg=e|v$Y{r~j(Qb}UI$1i~sPhQ<&
zL15lh!+(+O8SE|F{$wwoy!Xd{d2s(Pppc5ibaTGa>MA`<2Ky7uk<!<q`QFMw)mmv)
z#yiZgRIRT^-^k*~9DRCpWMVP>*4sPU6!NzVZ)HEovoCK(cGmyvc}!2m*OAZ9=A&_C
zPZZ|rR>e%NHBpL@@g%DID^cF;g}JtC74J>!kL%N?N4#g{<eUDtR?hc~H(Ip%>$T|r
z?0K!5#nHmt2>R}00!Is@r$^q({6A1>F`@ux;q7cBUp;6JjXzuS@|$tGS}7OQiq>xx
z@)fT5&i~9TeCyfhTXuBpbm6Ty@_xVY4gYIi;&pYeU~`-AD;y}GhZc2nTT~uKo9iQ^
zU#oZ*wXOP}yO8<bys4zc=BL$cVYC7xQyEU@U-9zuX=U_C<ymDbt-N7;?@GaIMxmOr
zADc}_qF3^v@^3^ddL@GeTT#U?_wr88oJrMl;OJXd%}UA7K|XKw%&ki0?Lzb>70J5t
zhY>610Y*n!74Lkn@*&$qh-*hHE05lP%PSX0y6Tn6h;6;8zFt{*rGRk|Ezc`gI-7a4
z@=D&xyp=b<Wm25g%1XVKemz>i4pb_0CNDHfZ~D#Q{H-fSpB`UPQ95!ZQE%+ajHM^D
z;!kZFTh7<iTec7#x8uDm^2=FtOOii+b0m6}tY4u!<awv5wup|uQ;QD&%R=RRdWX-!
zG<>~Sd8b$_AE{LGZ>a3_XIH9)d`$T*;-wcVmC^4;Z!bmPU)g%oPxB~ke)(4A_?6YD
zu`={lQY?R2{hlt*#P1oUep3zau1#!4!D<w2Mika{(|tX^TId#D$$Pm~BPe(?^1Gd0
z)0)+Udu?>24-_J}pq?EXUpp=q;K8^5QFXPLR+kV$yu)`VuBfk1yt0)o=INEK6@~d6
zX?{6x|IE$W=!8F4`IS6BRJpxYx!u|PN^SGa^4smxc^>7*U(JI*RQ{f5cJpL;?#ma_
z3IEVo`8U;f>*enrE)9Q0*&zLHMb95syQ3shZ~3-iW><^j$#Gq|((7H*mA4Fso=0yp
zHo+G5r6Y+xjy>txp;|QV|NHvNkjI|c!@oG(diD1BXDXFf)bN`>_Zv5(o5c@qFC2MQ
z9hsOrU8#IFozpc{`9|@TJUx9R(O2Tif0GqYKmGO<li#X*rC9umdJD%Ce4|)xN3WXA
z<GC2OC@OtWc{TmRNc}>3v-tbH=}I{=h2+~{$hYk+;MKZWIlAv%bv?hPtyi{rVLqxZ
z7f;{Imyb6JE0MNW7V~la->=Mm`4;s($B*aumM9!LSZVxm#sButePTYF|Cx#&{cNRF
z{6|Ro`JBuGlAvBK=w?*#y4K`s<ZXXtio&<%NU=QPz2%o{{<GGrZdUH#L&yQFRaS~O
zHU7x6`8U!y3Ru_#GoYecF=y;aH}f@q*j_12ZB`6<#i%(le_EgKdEH>7S~wp4o%C7z
z;U9dWWf6*DZ?slOM?WZ<(bL7&)9Fg9iQcBe44<i`8Z()DY;mO1R|_juRrziaC3}Yg
z*sRd<qLxQrL*=~bS|3;ItsF2z`&ePuU`<Dd^A<TWF;i3N@0k@02A;ud;4F1?`0OxG
zor4C>_L{@<pY=W<^F8vG8o>m=ns2S7PmP}5M?5<6fp=VcDu3JbRN+~3+&enrRo4JB
zU<Yo$89r1gS5^w=4Nkf_VzoDgU1AUY(TeYxh^2Zu5eI0!?y8QuEzIV~YyWVlSXoic
z)9P%mTWEC)`5frs+2UIZy;lpR%E;(xtV6kt1zm{JmHEwy^kZK7Hl}JZ_s-{@D!x_d
z`Z-@1D<BcOlk-3~qm{<#N^blW{Xw-*&9YxHRlmkc4)|VF2CH~p?JYghz-D^;eDkGW
zdYW@tB?PYcm6sKVTFI+yn)cpKfo5mrY}5Sc*-A5C1Vi9cTdkFfy?MNgD#N)yl^gT5
z($}ewuGMO!^C0!WWH5fpJD%_J!&r~%3Lcl{rCx!*_J(qAw6|(&T8AmOU)25|*4_ua
zjpM%a-d)lTtU4)Xuz-dTO=AWNXbDj=0Z|IfCiM;o#86DvScr6B$7u*kN>#sUW65^o
z%e4(=v9Q31tO$x~<kWqSpeVme(_AFkxl8)C_mY&=ICs7$mh80Z+ul=4ar-oPy^AF0
z`Z{TQdA~~~Y18L@`#$gcytGB)@9yl(?96XIzwhriX~W^?Uw%(mx~L_l&tt}J^`M1J
zT+z!>7%Wu6un3nsHiNCgiuWt6V$uXHhBC1HwLN<=995J#t79w@8dMU*TqF=z1o{fq
zlkg0zQ9Xkt46Tu+Q)pFt70Vh$t#DfwSX<$)zxk&h*J3aXj}UD>?wFxr6Kh)MDI~H9
zV}61~=Sw4S^XpB7oP>%km1WutX?vtsYO~zH_<YtTYst<85|iPbHM5~tl!J<QL?I-w
zuwqGi(q?EQ_}*2FmV>%S1t9hzFtjk2XyJFhdqzuSP1u8lz#y1`ESXKImj|Imbaa2-
z3>T|qIERK|)3pe!1a$0#!sMMWVk>-HmxDSll|xBgTS*sh?>Zrslr=Bx(TCX+tXN#;
zGzBxphQy;2cy(~~qw$8pl+7(A@|;5~uMY@YX%F3aH*5*#gJs>3lLhFd%-aL7CY4k6
z^x_xIse;qn>aF-iQZ&a4x1p=x=4$AEgB16ip|)mgT?+A{zTMU^rG^cv@nKp)>OF=A
zfs?|4g9;C@lpMAjI=HWGSV%5qI0j^4U-%>}Pt$@W8tZMW(W2&~_L*bp=(U6mqCLuG
z9qj-M{$&^lxUo@Hff=f(A1<=cR>}iQ)~AlXgq9AL4wzVCw$3$N9Hv2>4#Np*PU&bD
z?B5nM`1QZ&t`eAnj=tiAQXz@DOSolC;|av$;s!=%Z4%^SH&LvL4^s>?I|dL2Q%m}V
z(A0Wk!P3}_fq;4&)1A?WE{6{VrgOpostAYFaJ<0{thZ?n7CLTSs2CD1{omerPgvIw
zsD|lxn2~UA^kvhWl1gHvo5y-Xdlhy%tWOyWB?zZVN6BCYVhN;cJIsvEKn%-9B1?Uq
z;JRRzvy6(&+2|JqgAIApSQ}UZSBrDvYUARX&>LeIj<CwGe&z*}#X5beZ*7ZT8mndK
z6J|Rbol@g2J0kxV@@l7l>`*`EdKSa%ntFeKY|(rw_E>?o^kVuIcE9)AX6%4`ox3XI
zn!X<^|5=%gFnXb`GFjFcu+?~Ef1&R@Tgb<1`KF-d(fm=){aChtjx_mIcoF3SxBeA}
z;zMB`JtFr!$)>RjPBVW*1Z$k6SkKJ~s<0ooxU^hvCe|`=h+@;T0WtHU-C<jkGcX*W
zAQ}p&S^v%7ddG~^iNAU6xkJotrnZpJ$OEdb9ay8joF%`?^lvV((^+ixeI?#uAD>o_
z$!R`A_Nggl%Ex4R(jO;v87(hHXFH6(oT;m$G?r(v5KZ69kJ8)&bbQ^OBdId`6dyR5
z`vRY%o0nNCXMOqhuddm5D^LIYx}Cg=E#b1eXZAJM(jP~T;=`1kj1Sn`?Kv@%8%gqP
z4i}TlWjL<BnWgu1Me{tx*Ypfb><mjHEBZ9N*6;u2gd}Tdg#!`EYH1d$9Xzm3Xlo*P
zSeAqJ?&;VHiPdb*Vvp`<)awU~*+Z<?xl$&6U7avr#(QNK(^0L6FN{k(DzDJkWBq-|
zbZAO@M{sCw+M6>|-o9oBX(a2aH6d`#%FbL>ZpO~Qld{0^!kV4o?lQj7bcLP1GVZ4H
zyID=(h*t#q8f!08dK!jOtcEXfeC8;nsn0A^e7x`S_8uCokvaB_tL}$3lUCc^ze}I|
z_4IBUuMQn}FP&pwTa31zVzpN%Q#YPxtv}s+hFGUR6giqKJ^V*~H*NbOL{c-=S0@+w
z=-yY;RyW(Z%ZiVEs$45>d-5o`_*gOi;`92M(VPAKlmDIbqsfP)+qs_4f1~b3=rOPQ
zSBQmN##$!c$)9-OJe8t%+o5C1{fr&oXQwU~&g_iq;%F{bFpf1}Zv$#&s%H+w4(Ds1
zhnItNv#sC56%NFY_-Aupqo+5GzC9c7ZuhYtE07_aMRYmas)=pMWA*niI27AB>jz9#
z*}si2gifcF`}a@(CZ*q;D6#=|;*nyU)IQJSvib{%27NE57yHj;MfFt@IYo+cfcWG?
z1);8678qLz2?9oM1PZ+y{r#oyay~jX0s48Zc@y#UQMWzEQg7$711x-=cFDyWxgKm_
zca^(sWCW+kWCAVKRW9jrWPn;WuBr4a4u+!Q(5?S0=wViCFYS!GZI1U^o8mw<d8m>`
z_nrX>fAL*`*Jh5PCQDHgn!GLC8|Ut>UFWHC=Zf(|?9o3jQq-YJpqqSqn~1x`=zgkv
z#LqRWe(5j3MrFy;TmOPv%jC_1p>WflXSzTeA&53}P09%}fChq3WzKFrigZ8cnKV$C
zR*fX}R)`(ruBXLal;;%8hXI;e5ThQ+iA?p?(qitI0#F^)(K0!KQnZ)E06mS(o{n|h
z&u}(C!^?=QK|+((2hWR}%hO9FsyA<#W~o=3e46O8v_cq8$}1C-tu=bO7G)I{1$2Ju
zK4hPbO+b_7jRA=iidV_0WD%dPocsthBugSLd-KPXZlhjEC@#$vk$dQ>8_87Ltw*sb
zFWQ0{Cms=lXoLi=BECj3?G=~cE4LEYg1e&fYAJn_F%%AsP^Ng;3XLY+-$BSGi=Pf5
zl%}C;I9!U{{DuEjLlY=#m+t$~h*5fYI?3JflC{Q4A1Q`wFUwWd+OkZn)@ebl15z*D
zX$rq+4zMCBeywym;`?$Q?Oh!0Fn@_0MID?qU2-;mgVA034%>=uoF4t5!=fLB#I=o9
zY>%KVxvat<aq)bbTU;>cv5$ELD0`^2L~!{~G0-DQ!_`?C#O|GD%jj_DVaYUvixlza
zemYEKxtipvvXQWwow$S1P6HjqT_TDk^h23tQ8I7K7^GoL_8#2{?azsjt(8^;trX+?
zlv)x@dlT+lG3&V><KY?{2}e{bw2f#e3OzBiOyX`5+GIB}DBQM|QRq78_@LI7#n6cd
zFSVtyjkH48(DA(R#;WZE%4%cU<(YNLuc!YtJd~sj{8}M?salBZlcki~Ms+*Y$fRC5
zw+mI^M!RAth-MwVrsNF_E21?1H1F=b7}8q5NHc{Hu0q4V86Amj8H5%Hgbhl8l=sod
z+i2sn6k5rk4J++kb=q(tbHz<58{gu@$c0g^YH=7n%3vahmO)p5UvmIy*Oo=)Gq}tF
z2*ZPJY$W8e_?Pd8l~0j%Ugt22>`I?oX-7K+HsoU8g5PdwmB^Ba)uQ(<=LT?P-CTu0
z_S72h^2&2iugw=SLSGX8cpKRRbmz{y0p33uRisADRw#8mTOqr2io<EUj&t_flc9vZ
zL}y`f7_9WLSfW-63ri;`;rulEh(MIC^~G5mhBfoGj3>RD_TQp-O*8|uU=EwU=fWiW
zvuVq1TT&YjL1yR~`-P36j28X#P`&z|{CFY0&dv(IM~Zy>QaNvBblGtI#xiW+*_~!1
zYgcj!VtTpYtjbSJ^YON!O19xE;VY~_6N;8~A59z@#2qTM)ma;s=86hxF>&)-C$X5)
zl}TnvD46$DPZ)FJd?7ICVpm|a#n_!JcIPUlKn=?YUzvFyYF9Pbi-Y@fSnMd`uwK8C
z#%d$wC23hrD`jQ4KDa{t6s9`*@erOh>Uh`FQ^u^0PwA;9{s|z07Z6;A&uo9zW;FP8
ztZXo9nRow-J7aJB>`U^RcZj{Q`z1N;eOCU`*p`vqe^P$u*}@icb91isY5Ol@hsc%M
zJ1z0cWV8C>*FL;`NAP#-!$UjB-D~gs#@H4M59F-}eg8_n^X%AfS?TZf`JcG=CAshT
zoc{^?C3z@|BOICjWfI#s(&KgY#XtV=5T^3rIGL+!@BC{VCUaGOf8%iMSa6grR{9<0
ze<F{gG;bZHzEPeRV*hZEul>Y9f-mDBw~B&;eE)^L{~r!g_#kFj|2y`IwPT|og%95R
zwLcEx?yPWCI>jC>i_JK+5ePW2u|Pzx<Y4KCLxeg6pxQxCeHqIoaH57Dmc%v5gCtrc
zh}begH6)QRm$BehFxVSL0&QVy6<GC&0>Cf}*8eJ8#$OE|FhB8KV6h+ns0P+2KYq6H
zporf%&`<oxpLm8R=!aM$1g~B%u<)WeTZfe!3ZKM^b`4gv=7$fG*ZTDs=*;4b{8du^
z6QN6Mk1^Bb!k^J&ZO#vw?4X?G^}+?!VQ1~Nk^hOuLa{yjy~kk5geMpqSH^?3+BL#*
zc~v|M-JU$y*}-PWS4`M)Tab5fokaI5flRqF$6iG`aU0HmK6}kugQoj~3-%YVJ)+=;
zZLvn@?c{NL_g8GbfTd~SWDfT3-QH6V-X^J{Tw4VPWSB}+s~8Hu`>uX%Q0aX-rlBS^
zSgY61=>D1}eBi5D@|f>Tl+W5qE?V17t?!&^xDpGYB4ipJP=g%PhB0U??#5aeFJZNo
zU!qcLHanx(X8|shdE3hGZhJzH7jRQ;N2s0_6v;^Nw~pNA3<aPQD?H~Q8YUszy7P+Z
z6w7&50q&s1QXWIha9*>Uilf~S#{$&Q+dST9gBJO#HWST`6`Npm&ZO3!1*?B2_3c>s
zdDeGH84MQ~vkuXNB%i6furH0AmZL?qB!=Rl9c)moQCo2gdMzAv!44l(N4Zc-SYzUz
zYEFCib>3qEQ-)?-;TXeggv}w0xupYHIKuUqIwfDRe|MQLaqB@W4x881f|%tU>+1`q
zY64a18P2)BW(!L9^z7A5av`GRniVg+0mi_9hv7W5I!r|EHN-GByk?RvjwFN!;!7LT
z1<LmD9%x$i?IQ^cG&r@e(b;n&ja=UT!SCOhAfYC1gCpFx`hW*xg|^OzF?`P$zQ!5X
zcy1U={&@>706$GjuMDwLNUGTdYrM&IP^1}sO8_b2^bC)XP`IeiW|@CiKHY|fNsoJC
z8ah;pQt}A;t`fY^76y`DY0_T8+BXOC@t_Sxa}?+=p<loIYZ~)YHiphZ*>kZ7%F>mV
z(e*0@`0lJ&*_MTxXAdr5X6*7`@YL>;Y&Iumk~b_?Iw<|rZF5%GTrgv2==jw_){F}}
z!rmB;MtTPL?0KGLk$Oa}lI9v=$2)B8ksMF&k2I6H!3?~1D4ps-Xo{5`!VWiz^Q00`
zGUb2?#!pd}FWN{j*U;0jNbH#=64|fY_OX$7kLxe{NubMa%e1rf0M<UGgKJ%rtv$aU
zXI;Oa7)||%EamO&ZpE|c<hVPWKeA8pSke5d?fN_Db<Wa7zr*^k3chAz;~FkWZ$uoA
z?kTYG;xl}a;r4$OcYeQjj$N)T*srcJ_8~Pz{WrO>`z0ol9doFee3HGCQJ2d(<Q2>{
z^@e^#6xmT;++oht<u)F>Vqa56GixW-NAj3aseOH5W!`jH8&lNUR+S*}5G!^YYs^=%
zLWm{+u%<kRD`oh=yswp!V@LK9ZOkAd_H315NZo*I#EzwU62^d~ZQ&SHduQYd7M<-w
z@M7pDzo102xdw0_R2ueT!4S!Z5SmJv<tg}vfIFx*RnV@#@W*iRO@UoBbg8u#*%-M)
z0uct}=2cQIbg5Hr8=6FSp`b}%G{t!+;d<f)->AR~pmgcm;6OgeOD@SN2JHlVFPdLS
zcr8><QZJnh#$MdH7`KNh{6(5-f+zJfRL__G-KJF}Ve5j(gf~@k_>>8H10u2~fJ%Tf
zP~U}o>BISJ%-|*ic%fw*0rWZss#3X^D28dncV6bNl?%P*6iuAs*nmWnGGU}cqMU#+
z0(VdG6}wo3Vc-W~cGbe|-+TSLpVh`mTkj}KwG2L`Fnp~tKbVn{T*Aq0Z^Mx&oAs8t
zu$}VBk)fVat>CBiCX5cubYVev$PjI;+rC=Vp5XQZiTZj2gJDtRanc3_^pUGDwt#?p
z^Y?Qt!Id%Y<!Bu4^pH&Ga!d)%;n)1ZuieR>)%^f{>9Z2#2*wY*)?mI)VUvnZa|kS6
zAsZ-do~A|BclKwSqKYOVGt;=z2F7+%Iw#?9XBzQM$2VjnYibGu9kNQz_6V(s``*S4
zZijn0X5P4wU$yoK1&5W@Z~T`R0K*`*YjC;YTn-Bzl@E`U-jCS^{zqs_){#E|GJS`k
z!16(|%42wqOEE-yX)#ZQIj%Qy7EYH~;4~q*Cz?X^;E+1TKA?LaqjWJ`?k#5YhKJW|
z&6?%1Xc^k45A*;+a)mJ}T(g@xu3P7tlLS9jG~s&4h|#fQS)yS^(PTrdSsEOMWg|k$
z-U8uTEQDa0Y8kT<E{>M^YQB9x8dDVaOiQO%+hfRi8(ll_<f77tEnL36AI2|88*GoS
zbN%|2qhW(v0CnL_Jd9Ziep%wHCoovBLb(v)Q<V4DJ!Qkl___gVr^sT_cj}(SoFU!k
z&VJEw3$kCyI~E;TCoQtS0JgX`jI@}VmVT>%CUzEsR%sO{%0W4B;(!wC%pUJ?gdoov
z;?tkIJ)n==BF-49pT7?`0Hy&HsvE#YbPYpu%Cq3%KA{jh_*mHa!@Nlrc@e(WK2rX=
z)yE-W0Acds*1h979Ic3GETnV5JrM4<X(+E`r936XaO@}#S^y40L#+-WZHjG-asBS;
zJ2k(gOGgif=rESYI=n&+UE$=mKxNId;F#fpY4mr{r#~(e(}lpZY(gmm-HYw)FJSJ{
zpwS2}5xR*`1E0rjsKpByT#_)%vGQi}Wo$&DaP|0@^Eb%@3Fhel?)U;ZsNk<cB_wrA
z1@X#ZBivTHCc=4Eq-yK}Rv>1g2i-K3AqNZlm#8^T4318H$%p>Jk-fvF+=A}~6K!xx
zN&VrG1m<bnluTm05Kgbgq&6k31YHEI-(i}^{;g5e(EBWmIbn1q71kGr2~ajF-8V%t
z3;DCuE7*z}Y?t8GExZT|c58jj(dnK7oX17DD-5mGD{xUBBH(&7GR&1`51YQgz=%p1
z$8dt7N1$5L%Y2?DJcY5ywxxRWfbr}^jB`Krh?gpSicPDE$DY$I7HdM)9b*fum4ilt
zeV!bSclcl@*<9$`{U_=wb=l%`vaMeC_*Hq>%#j)XdW#=t_h&o1J4yfZ7b1^{onq)5
znRdnRLtyc~ezlNFAKY7veSN#%ddgh0(+3MMAEw53Th|Kw6m4GiZ<=rosE$o%5otX?
zB90W~tJU&&WP}cz59Vi&+v(nzcge38=Edxb)D!2dPCC89AK)<ccYl}K=2mQ`Y|WC*
zwe?D_b=h?7n9I1Dbr+BiROXQFui@IQb(Xp!<m2id&!vf-JCiqvz5Cmq%j_d`Mz#+P
zQJZ|qI^6fNy`6oS{|Bnr=Wh&=^p%719Xt9Zd2@)qdYD}*ERba6*Wxb?9<nbo)j8%K
z=KHCC!L2n9+2&u%Lh7<#A4|Vtk=P<pebZ!zxu@`w&FiwYe=N3NiF7EPH%qUW*r32X
zO1FCBx%3g4>5Q=LRx_!L*_~qcYOo$ejL*L5vF$_SdU5W?o3fS;)}{xr+&$m{%T~c!
zYjz3`6&b9n(-h|PX#=li0CQ>TI0u@Q*rE0$Guh9wi%(ft?Ot3=!8X14&0=tXZ<dzn
z{Yv4}_pe>-fa%K8XYr-4$w@RE5b)$Bvafl<#MfFUu*`L@JQ6HgPo#i=TiD-{#`^v9
zHonxp=G|a`$49)D>F;Z{`u(e_THX_&-{3bb;@23`$=0O=1ddJk8xQ+#e&X_!EPW($
z-5e-=lIX1TT>^^J4G`-MmTx^ks`dwDR}RpXUFy*Dq4Bn?EuXbL_r-gsy<<vd$x#6|
zc-F3-E`5yTOAkLC-+ShW|4?C}aHRXqk4}jHnOb*Oe}@bVM85@=I97cNDo`L`<q|-*
z$+sd;+GXonaH`UZKpOu0iw_mfi+7d2n@VMP`5k^5Nq!{Wxm<LMHb`p8l5ISXN1jgq
z5p~<D^l#|iGhg%XFKpYV<aUc4?F-1U_?k*V)d9#<ZGYYUSn|e$&(E9KtvA4?TIFeW
zL|LiJ^bo6kC8Z+=zEZME;3KcJ-=t!h?An=}vz@C{6l%n&9W33>N`JI}nYPMn)@x_n
zb9<Jv_j4<<EWXx_CYK{t>E9q8U;sJUQ~^-$^|m{=LF0gSCjUFG!gGtjv^6pc)RRL2
zisE`eJi+PS&NC|k6vG3)8rmjSPJhmVy&W385W8rLI_H_?oh#ZykKTrZYZrgM#9N`s
zcU8`$a&*S!B-tg=GE}(|SsrU`4Q)~2JyE)Vr2YZgibfXf5~Dc#)6v6>$=)MsSKqr7
z2TCQyrzh#?-r}x5Cg<~{CNqYNg3o8FMI6N)$5yzc^^CQWt4w~hDhxl}6%S&V+<3DX
z4lN1VdbIcitJw!InbnH+%IU`oY#`nWWp0`jh}hybT|sLe`=vYg)LB%&_}D~LUn#u-
z3Gqs5fl^Ep000Bbit2zbXj4b^SXn>pBCFmAN>S!~)_vvIQd}WPDq#8}uuJGEa=+R|
zma`Qk&Ic|pt?^2E67-LidS7e1#SFOZiSMDd4M<RR4JwOX(91?37Y2#K_0$AM4V9_U
z3JEozwy_#aF6WM{p_|BJPR!+1>bUsC3qO57FWu%lU=49ey$-Hr327dvhQ7}rLtN!J
z0g+eQIxwCe)ic%E(o1mr*@L9^*h2+C&(=FzQ%rj=9hHx@Q{C(XMDnBLKble9UJG0W
z0xAgi<t4$QD7%f?1{5};-@_Xh?`#+)zuKmF!CwMB@8K-mMsb(KQD8c-$-p{Wf=tQy
zPO^90ErGKDlY(8r?jOl6!BVeaOFB%^5p?{k^t?@3oeJO7_7@Wp%~*P)=&jM~snqBg
z&2#(Wrf4^^e{vUA3lk)I!?ug^E}maQ4+!XM2FxFISLutYY8ysh$*Q&=G|{M-(vCHy
zL7kik{2G~SAo~H2ZrRI`AuwMw{^;1I>sRj!m^LB^p&V{kvQfPiH)h-!Gp>Vz5^a}`
zg3_~CBcJ8x?E>oxr<UDDj`EAOX;2L4`e|)Kt1RCG?vFr23J(i@$KQtRm7Hg85pgZ9
zP^I1_GFe*5qB2vdN_%p$2!}#fY*ZzXA^aJIkR5l=Sc6?etS$)D-pc8`2z(g7!|fy8
z({UqsxmCk0CGP%I&#Pd>71Ge7O2?3vrzajkP$U`b)uQ^UuOVoV`Dghu*n(irixgu<
z&SutqIipe=?6p$o@s_pyS(1S?I;!N)N4AJzq|UnBcFU6x5nY^!+Bmpz;;ZS~ky9dm
z$qiLdv%tBiL~jh2(yCFoN=iAgL;!}X_UX@vdiRU7LRhCm&ZC7T(TaOFKlc?U^jaIP
z0=~+y(o-ubHC7H`(XzeZ&`n_g)QYXR0{}~5njp<8=#XA1oAL9EEEcc}aKF)9gMkNK
z0i-5rUCJkH%z`U~R?IC~O=!h!g`AJtd$lb*;(J&~&gYRe%t-VUO$sj4(92MmOE9W6
zzo9plld+J9FPM#+=YMr-CKa&MRi-Q~C6$0}j#+UKGnduimmUY&4H3+HoG@j+=>h)=
zNA1I!i@R*_Sy?OF+MI8*m)9EdPQ1+)IS{d(u9ZzY#@Gr)p0-{;V7KEN>K({|(HmLI
z?4>xD?9FhwIGvEaV%4`3q?aMtk<iR9{kP&FvH^A%4)tw--G%=Lup7Jbso%edS@X*1
zOZYP|`<>C3<OT)B-(ZSe`2-$d?%Uw9BfGDZzZdY~-S61o!#~Mmx5HO^dE+Q|uic`#
z{{V-BuLnf-dq0VFe+-8=tGU)k?P~#V{?s2_yhibN^rdfZlm`^}AD0JM_{;yOJpX(7
z`$2iOo(g#N3$d-Yj*|vn1|Ysi+``QFh^r_OXs-An-o0n}1_}bs`^6b^a~U|71K~P7
zJltcMV7#zdHOIi%f}bboy6H>^NKOj9`!$-n9XkJB2q!9%M}49PxeGNcQ%xB6TEY$1
zvseyjSTW5MARpJb)+(@aErUh&>EHoCKq_9Yv3u_OsSQF9=$de{V72oPKluJX{rS;L
zIQkENg74uxKYVuG66WAZG8DM!Q?-?5)l$P`#UCV_=&N-V4#i$!{uB&tI<rruib8zL
zlQ(Vp{9!)rr9=OPRu0a}-(*nF4P<ub8NHvBphHaevK>%h4NezM<wod3v|~O9#Pe9s
zgM)i%m!CBSna!Gr?#!iFiJi1)q9E5fh3ZMm)YsYgbRj*oU=4WyWL1BD#82c{{Jf=K
zs29c*)^wI3WTLrGLNtBzzMb>5pQ}!P_d?y1pdOGr@qnzVA?)ND?S*b9Z+9I}(U58g
zPjBkS3LQ4i<(;C57x#M)DX+`5Ez}J^RvuHt-zPJ`M<1qlnE<-brXv~3GR$%vYb5BG
zuqJ~ZHF4g&T=oh@V;r-Mt#G<7(%suwx8SZHwg7RVpZRw?%<u$|WVmWWfA;vY-z01u
z`V!4o0GS00K8Hj<mWn;wbI(<|-!!&czU5GRfgR!W<=HHePI<_a?W{m9Ss@0v^wsXV
z_aMLo8|xX<$Gm0%o&sq;z>z3yc;^%lD%=A3qL%Q4FfMfLF})!a?UgapGAyiKZS8(#
z7Xd-P0SgbT!fMKpl^`|Sf<CTn#M&M9S}+j#N{i687-OpNQ@CJrNXJ@3hwTk`lC|Ki
z%wa_APhtoYgA#Cc!EPSMB?CXRGPIj9wT6TaT-NFHp5Eu_mYvuqAYRMO2=7~hkM&X^
z!b)c(2kv7u#4@;xrzdVcG@vykl!7&nf-gX$NdZtgaV-v8q^jUMDBDWtLs{FOjpXr=
zYvF?wY8#vmq8;`g%!e`d87yhAE(MPn=emZToPhIq+~WehpR*@S&b?*HGI}xBr?{Tb
zWdf}Vou?r%Mtju9=W@X!;4IhQeChUvJjqsY?Amh7u;%Cy4j);YqhrP7K^1!@Z{WW8
zEv|MS^r*`D)|3}!&oMFUDmu^ZURyWEg<OC@_EA5F88DX5<kNSudD^D{#AEGgkIg9Z
ziwZKGB=@dTz2Ebc9CI0S2YB8Q+`DWoBi$|_VnU6*K*zc2LKWSC^c8j2@N$-b`fJTX
zGMq@y^_SioHdN4qq^%FGQ}%hz$t!UZ#<E!+W(Hw1ZoYX5cJ2a!?(;AYwdgM@au05X
z;r@P{<GH$w-5cm~v*h(=vj9OWjVW~N^jC?|l9OHxdTFQz*G%V?Eqx0nLV1o`JLnwA
zsH+lL;>SJu0=M&VZy$WhP=(rq{1DoicNiT%4u3{A*GGjhCXBNd#7_3^vSEGtx8IFH
zXbwI_jC|<3c$Cm-0(wKN>PKee9n?94kyM2{c|^6SY!=hvaUHy?f+4LB!Z{7um+i-Z
zB@x>ahzYlk40+1Sn%H550^&6>ywdcv&;|*FbU9c~JWSBv3<p!6ZL#a0`~pr`@xXE=
z$Q8u&5T$7my|qrkwWdVF2w)`F_hUuhFkUV;bZo}?04E8kb6e;vSy&aseF9ps1cacg
zeGoSWQDPX!>7vEaIPeGA93TX0(T?-7h3)=uL&{!Ac`>}dHuxamS)jgy1Q}*TL+Ws=
zp)3)G(hg(lA0Biz`Bu2CM|2z`l+YEnH=0M|TM%%r0l&fT7dVOhdA=0*dBQW0o+tFN
zE;y8DaEMxgLO`wrTqn2^4c@bW_K+W_&@fOirHdNDT*YWG6Im?qLo($UAV487Y3C%F
zr$wzPPYQfB=Ib%t_Y;6pn&o68Nkr4`l%WcIats1!&qdrQwFCzmM0g*822-~x7Thw<
zvlt|yIW|zTG|Ga#6K|5gT_uRZ)hsAo0kUv?;Z3BaTeuuhy?~pB!nV;w=>@nR0;uqN
z9=`W=Hb26O;X^|Ar7$BNfHI7D+}PSY*rAPHWP=ugF?qzxiU#+*f{slM0|yuy0x<68
z@BN`hO!X49&%uep<xSx=0yU^K2;`V;U7N*vrozIvrN-$9k-&gs9Sk%<HCI%67dM~J
zB3#rJ<F99W{1mHI!#P_+<+EX|uk2K>V1usEI2ojv-TUc=<AF$x*fb3ZtdPN!4UdBM
zo!uYM8#=ebo6N-+3;C-AUAmz#mNE^A>3y_{KTjO=U*}~Ou=XjyY3Xa>S=#F?TA0x)
z3~DPl)nL`tC~nHUHslE<6*nBD7m*lyom8FLX@aDcpqxtYFTfXvoO{G<V3RHYHkt+r
z*Z=kx9i4|Mn!W{!KSdgx>*2LN1Xcxhg~?2%C3LH0!eQp2q6324aD$e`yJ^G6oD|mS
z9%A;cnn+!h#zYfd$T>bHo$$v0_*h^nTS&@X)biTAsfj_u9v1hFBc=+-5E$QK(1oV#
z4)sCui3Pg{o!U<X%?j`vYV}S)Jx}t;%fy~xMcY6#`#D=-8_M)r#2n5e=KxGDh_H(S
zbl%)uHHX%@c;7Oe7%Uj?6ULyPB@nS;fJtz*E}S0t7=rNh>vO*kY#*88FyhUA9kU5U
z^qLb$Q_WefqZjFZnC7X18{g@T^~~t1pHxkS5C=2J3=|ibaE&5HkTRMEKg=nZsifXO
z+9M5wwh!16S73-ehBSk)Y+=VeOf%9LH}3myV}`Tm5fuiuWLb0z#DkabfbzBu?)N;J
zu_y2{#zKw}TfoFhooL|%i>bPt+Bg-GWD_&Q)Qo|Fa}N%UHKOfU9buw7VvtdW;}L<N
zQaX{AC8OkBvW&WhY{mQGhq+x=tZ?r>gBS1Ka~tLOFAAwJv;#rZA)FDR0H7;X!PsXo
zqEft|JH5UFB@dF<8<>@~A_h?nVHuj3sy7k+nYilJMa)9@5XKr*twkuY$bM`G9PY7c
zgd232Qv`6Eju_idSbmrQ>UO|t#<;rq-hVkoz-}*h>)DnYN7&9IEOnAP@|ixbey*jH
zITGkt`{j(R@tF?ByO^<6QL-{6@MMQMerZK@$f>&8&gP=3Sy%q7gs3*MPqh{ya~;Pl
z`5*XfmEQYg=1}I1_bu@8Oa8YCWWSm@7pD~akO^yE44xDE?#q_Akln(!(!O<$yeJcL
z=Zj<^`D9M?--uX!E^-l2wtX}9QZz}rsGg*+TUW{D!kUPkOLjS;Ztj_u9$APb$>03v
zKb@zQ!8vkVy4X8Ky?80d$+Vi4uk^LDa74qoy;=2Ng5Y>FZ*}_eO??No(kJ_N+j`;<
zlb-`?Wv#>JGkuHZk^0v!N%Cs{>zDeo**VgI%=zWwoVB${=x&Riq+bFRaJT>N1#9cI
zJ%=K(iO1*6&B@(Q<^Iqds}}~W^c!3E6}FFHk97|z_K&B`=)~dZQ{wgddh#x7dusD^
zdf&eE>sTd?ubI)J{9`FkME6v!=pTxY(1GO8ns_j>Sq@kO)(#Uv1<UlF0x_=t-2(|X
z2Lqm^0#R?S4;CZXNR1))=%Xw^yDg%yQpM965(Bzol{Izhs|McKfU~!LwLpKP_|+m^
z2zqzi!mS(X+;{+U4?qKQVj>;rdEZFG9t)r>P5ov7b5kgAgdRA~Gjd{gpO}_-D8}90
zeaSKCis{6!39N8Wqy$ZUcH`rhQSg}Q<JUwwIL(0te(dpg4^ZDcrmiZolPIX<qB=?6
zq-1t4iM~j&6k0UPvD$MfeXRD?_qViNUlsHW@e#S-j<GDZEGI7}Z`kac&!i{lK>ozv
zC9Q3d)~CjycO867xhL+fE|UlPPJEBIM#moB$&c=olV21^ch1G5^cvK>Pt!nMmxgb1
z?_YmndKsC_?k|>J%KZW_J^TSEdUw4ox*5In6hD_ozS6%#nyvlrul!6B8y~n^c2-jN
z7XnRh>Fv~3+xpPNX1c8qtG+kjKc02(nLs&Q6i2x%y(c^|z4J!ww;FC_iOj&|<hN)Q
zlO4_~_hP40h-YDOoqm)s>&uUjCs_5XkOB_ST{?12k$XKO`!jsNzW7)HPP4oIEscbV
znd$C{k3{kAi9aFB<aZHn-9=8m;%0iRnPui?kkk>gDGQKNmJf?%Ovw0X%JX`nK=p;{
zfoL~pJ?+x#X3P}$UOL`Ww4gBF9|cE_b|EaC-UfKW@v*pWI}h*YtFZ$M;ya)JsR3Gn
z_VXx#PcusN7POjkEDE(TnBa5KE;+)#{9&jb<0km-IUFeNX3yG%M|0ab(Da4uF}3%t
z{Y&KHN1uut7bk!}-O0(*xw!k>T|Beb`ioylcC&k2T*OhR@ApP_*sbwH;!?ZtnBW8K
z;?I9<TQ<OZD?C>H*e43hypjbAt$dQx(!);%Qd{;kP^D8H8|)^LMFyaGa__`8Q7L6S
zh-G)9G?s;03fd&$TBVmzEf0`X?EKcBexm6T=7)PU-a<Q2P%<>gb5SUPD-o>)x<$Y2
zM&9H>YF4M3OCPe!g?$n5#DWo*Z(B*xVt-XIR!;nVDh2U5NG`wharZBiV1Se2XBo{7
zp0}&7K1~nVaJU#pN$XKa9<f<PB-oJ#)D9Zq>W4V1Y|f&^Q#r0Z9qI1e&j<DWCO!w+
zXcW<AlnO|f<8orZfR;6V{R1C?#Re5<RJV4y0Dj=9QRsK)5UuMxdQ=;rUxpW;+DTmH
zWI51iPtg_&?Y_a-#Z6A_%#IY`z1)HF#&>;>r|>?C-6h4SJ{p;r%$(1URg=iAVqbi8
zD?6HPAp+GsvjfJ0xwI2PQgieIeGN+RirCfVR*D!b^`h_!)t%cS_J(|X<h^to4{~b=
z;gYS?K`v%K+LKsD;+`dFEBU7n--#s2402f%TRBun)+J5%B-EZ|J?@^2>T~SN*i*_S
z$mu~kqE%*{+yHAaQ@BcQBQpd>SXUyg#a(>#Tj+XALFa$7xsRK0>HKv{@v#tQ(yIb<
zW>Df?Jq@{#9387hvJP^l=y(P0=9>i1L|nPqEcp024m15OfOGtUO1xoMfW6#2w)tI}
zso)RL;9%0V85awUBg%|&S^XW<{pm+g%ga!}V$`}DK8hhXcOMm1JN0&!H}~#O3H{;^
zwkAjQ(qB}uZr+Oz;-WG}QQ0{eO#vcTNoLxUlaX_I*Dl=-P5-y)dAJRr^9BEpzAZSi
z)pC$$NQt*nQ01&cp<gLr;BX0?IS|Yis`QgI)ANMrLg#{(ToP|$oaf*8N)OCIjlil$
zyqQfcsO<szFGYOU<{;T${Ed`8M82Oy->PAw?w!`I7n5EOeqG2{b`Rp*H<D=Z6X(PW
z!iP&oKva7MIb@i>8F+ruB|pn5kzMEPo?ZLMfbEa;<yiEqJh-~S6@&pG+}T_6Z7tOU
zCRTw1wIc8@7w-w9%=Z-1MpPMWyFUoMKpexqfpYUFzW(l69V;cB`Ht?VRF17!49oZJ
z1x-s_Du*D4mTEZyL7ss2JzXv!*RV`Ace2vI7YMfAzCSnXRv#0|wN}3<6n$f$zo^aV
z2^td4gqaT`%<Qb_jTr(GV&NFT#hRmASYW9h6T#^EFFq?=TI%vuAIM01Q|SqqZ8sOK
zsdk|Ht$~v1BUto~<YDe>^JAD$M+u|bk6`GqG#?CEX}83|H5h)<VJAPJDT&~j4Q+5n
z-ic@zg}ozK5O0&lRBik7LeTkX%#RR}LfYGB&{T&zn8byVYC<D@oaZVz1TQ9q?2HM=
zGw>mTwN*yekWWar$d^8K$3Kz(9=Rp|y>d(byL&^k`*?kWrY=Ku`%f5g{<{*9Igs0e
z>E4pc{@-bK2Y-?g|6}3rKh^C1Q{nGoARqo`gumd;w?xPrB|!mhmE`{y;qMl3jZGeO
zzgXbn$1#H6SX!hCH7vAY^9KKG!D2gj1E#V`Qbhj4f5D>Rhd)j))(`*i^wz6IP5bEB
z?f(~VBycAAqp#ljoA}|E1)ko5z8kOqqlX*M|Htx@g4mNO&av*ZEG_AJku@wlkB}i<
z`Gh17#S4e%J51cgax{H7U#!^zEc)bNlCH%n8FOp5e_f<?6FBJ9dTQ}~`um#6*9VAQ
zD6Wr+=GClWHw$ff#U6{d$ukj~PZzdugl6|+k<dO)c|OVa3Yr%b_#nX%C7mGpjwpQa
zGX0h`a>#2ShMH1vIbw}j>(-xtpqC9}0T$GOBZxsk`R1U08<Ex!%<Fn`7Qn#PlC%(V
z{2WtVyb39lSf|R4^-^R$aN}wRgpyB)MRpfkwVSzqHp{cZcmC>};Cwv`K8ONx9nb(O
zJ>oSLpAME-IV|#kMi)o4Vjlb_t2H=9<m?B0`qcBcHKcIuBiW`t;ydx0r!_nGDr8(S
z!w=L{l9UmE$wggUkmb;db44MYW%+h%j$8ffqiKDSE+Y1@RVO^AV9;tZdQBO{F}f+x
zHa3ai)dKvEQ-vkoFjo37zjBnU0mgGp=<u(>znIp?l`i(ELN9_-fm8>LyuE6LU*>-v
z>2ZuBJfONxnca!MF|!u;`!T$i5etu%6q4_HUE05HV(A1z(^3G0oW5l10+c1QmZK8%
zcAAbCc%2qa(chu{M!HT&UK<ngIfk`eK%tm}fptm%EHGh~(ebfF+?~A(z$3xy5{we0
zNUU-c^`6&z0Yia0hLbGjiYDh0(b-CURwm>+vF1%5!bgN2bIMW|Y~P1gsa^OSc}=WA
ztVk<tR!plteFlp3j@?g<T!I$M4EbXUw(fHQpE>|rL3oBEgfgH%2K%(Z;bzx`nEfos
zyqxDU;u+yyGhuA!wmqbj^u5T<AAAlq>YoCFCJ0LbWK;8ziZ>ron`PyLVR9#Q?FiY#
zr9R)~Gi&k9-b~I8e?4Dn>sYK^6<B4YeLa4;yVKqSZ8Q<hn<OLC$X!Mkk-MJLBXpJb
zcLryaGG0>#q}>M9mbe420TpSF8uKJ?9t20S1*&f#^&z!|Yud0$(@Hg`smKo@rG&YJ
z*tXx$DW6rBM2D;>GyI6hnc8LS@?E5NJh6x><wGjlH|XM)E`_#|oH=`lK4azC%cl(S
z2xvHVKellR5xvQ?X*ytU<}ALRea%zGkf+mmo+@W~I@FXiiq{F<b3U?6^JYWG#_}1!
zVHRJeQzD#WF_8Z%(xr`M$weVgMnF`%W1jr39cA@#ssy?c8{_&IHj=DfPybiP>p|76
z_z3w9Y0hQF*Z5`?){CaaIsk0&oAiZ2g2LcJexsl#F5#cv(7QIku49;XGhiJMrYYfI
z{zT>BhO)zLbUF$r3&{RwBydS2XF<F=Y}$=es635IP5bmk1G>Bv7#G)vxN?UqZHjAf
z3n<#S#7UXf1pHBa3IZ!5oh7p}G^^(zvc|GhpJ$kO(;<)%I;EEQj0`oVRRnv%yh2v3
zB)TxV6G9>q2D5h=Q<x~Z0HaJyb5pY#JgB~;5e%_*!+2Bn{@m*jB_bOG0<1Kx69jp~
z`vv&u&u2^~!Bu7nGCoaIH4U}_1~g4g0aVXJ0?UJT0oIkejSLDtE^MAN0q%*5#6Sq`
zB&cJ97J-m#5F8ZQDIyGyFPmdHl0d-t^?TkzIUEd$w(ij0HQyT3!=EE6q5BFj&nb^s
zVbE_UGz`&jNDb1jV|jw!qo5e&T2ts@qiG=LO#z8JK;>|u9JjC~&az;bH8isUw61{H
zkfX+G=&~54UEpIYZy|tQ{@|@13<Iu!)dHSx&=xc+;A}p#R>4P=trd%^sV5Mju5&F3
z4@P*CFga4utdf?Xc0_cjN@RmRpl87Q`wW7l6nWdxwMGxR3n$<b96*_(wnSjh4Z<-e
zu+lWb$V!Jw+Im3?WAB$B%LXlNQVK7b#e`l|&MR~zK-gX0m=@YB;>;lO9E8P#SPRd9
zn~sDUIy`<*`dN(yX3ymy%Tozs6-|oP$!J5yP@Pn|GZYRjVrwMUPyMQV0`MK-@|@h(
zr#p}Y<WbJPn*)=u1S%dH0`5=lxRBr`33Ql{q*%D^8?YP=G)@!bPaDp~Y{K*gE)jDa
zO1NO7AHfrwP%?1qgVE762WLj?vRcTtltGrzD>Tl?FaRYD>q7?81T~C3x>h`E77h&|
zIR<_Lx`$x}xiNm^7!FQh%;QaTE$$qIn88oz7W$QH=y3lApHIj<K8+7Lbw1?@+)p;Q
zlW?{eK40Pq0Kx=DG04&l4GCU~*Z=a{VXPj3?JRtGkYk#zE9yIsn$GRPrbe{w>8}A2
zClGKbbj)vc57<)JXNeIma2^aWX#+V;;P$~U*vuMQ{0Uo!XR{!=uALq;?691MUOZ8q
zE^ZYQj_FQUreUq5s<Kjm(|z0(4MRROvnhd-8@Q1De%M4*#%*A<NS?yjhWn`4>eYC{
z!0~4gfRAJ1S{)|su@D9oc#93KPgK1I<b{fg9Yh2^h8|oK>Ie2zgB!Rf@eLUa1X_Z3
zd66>>5eDWrp1wnaD-KF1*fVe}U_~;kqbLcNH{b)}SZE5vF`3;11;A`I7)3BDIBnWC
z;Io9u!cp0bbDR)v3h+WNS<n-g5roihEa4wdt@Fe>JZEE7R&;s;u(}tr>n<WL^?MEU
z4k5nu=<Nwzp=koYMsQ030O_V>h2if-(7-7)I@zS0QRu+gD{%91<S0q#O@oCEp1=j+
zXI4i+5L$-sIy$^+2(O`it_YrlL#Zr>cwTdgcc9w@$@Wl-81f9871{Ma-<{CA&1^hY
zgHcsJ*`IoRZEJVWnyI!z;93~J1h*hj$7M}P0{cdYoH_3L_bW}Sr@z9p_KdtDI(=Ka
zv9|2HqQp-21sZ*Yo#NTPqx>F^yhFt*oz3R`=7o$xcB4asUe&XjS!kQt=H_hD+sQ3|
z4%^Dp-Pj{znrv;}MQ5^E`}fabw}e4(+?|_~R{FBV&!yJVn^h?n+%X@ajO@P2P3*4T
zuP&v7P?Vule0OeSz<Pk+Pe1Y0ok@N05G2R3LL4K>?ApLevtFm2*fZuq6>;t8ud}M$
zs*n{ce3(vS0)-5it!*7k?i2RPSkC@D$;Yo#yLpJ6?<<_)Ez0ZNbdAU2C*!|GlZWUs
zA4E!~B+1*&H8F!&^L6;X>0u^#Giiv~ooMe|-(@?CM4tU`qpfemdF=ck(0B4GK`!RI
z#1`89?ex%eo!0-rnj6`<7A4UUvfb>f*YD<nzD}>YIdf}r?65dN$FpM3H8AkPcRu=V
zioj2xT*Ft5x>BjY{|`MiVr(GHMZSd^a$wv_i9nDS=tv!#D!@B4-Bf9OvUM48zxV>E
zYWK8<7f#btH1_BZ6DS0FUT@k{jeX5q$3<QR5~Nu`Fh2sP6dt9HBO?V(J;!ktJQkH)
z-;??BQ)v&1+$%rixQIU8d>S9xD+6|mbt^D#{|3>$`9Hc##Mf33j4;OnMJB($Fo1CU
z6OSF>t!Ly!X>j7qmq9ijIz#?chT?8!FlRe=9!*Lssn1a`MC3&;oMU?jw}?^q%w~U!
z*ftHC_IpV$JNxA;@(h`E1(GoUk=e^he<|5|g}sR{ofs9{$y~nmZMuy2K#B)@u}#Oa
z_{JG|wQvR-Xv%JGfMUn*!>s&vglE=i^a79X<vhjRr?)3Z_wmSEbfGYSOwHZo*dxjJ
ztI>6O;C6-cAW=g$poOD1zx`@LUxJr3z=KB#7*?w`7d=lUg+lPr?>ya$L;<I=tMv3J
zEN*0q7y@!bKs>hQKmr2sCh{8G>$ztL;q=7$Bv{uLbrsXEow<h8MYIjMZ-Ird&8*#`
z&>FkU9PNR?-wdwe2wFzyDRRyRm$jF3ty%;eGXS4EEySjmKEyL#5KaCj(tmGU=dRPh
zT?cw`XhhvZ8e3WscQ3yi;HvdOTBx-v0jS-Ngb}sp%}To@b(H+qQ@U>gv_b0#$p_NL
z);?fn_MWlAwUZ;;B5E<+-8tkg?BEcr{$4iot*(rFU7|GsQ;^IJ8>k?S=K{m#9W>n6
zja0C$M&*pTM6Bx~NS$EXaWF@6ui;=x0J5b|{t>8ESV94e&2_pEI8v-6N=Va_6Y-l+
z7{A1C{yj<P3D}4<DDP2HdiZ18h<c-x(kDu{#ogaKaGM&*YC#$efiV)0?!dzoVn|C{
z+>zw1@>Ni{7zp%~N(GB8AXGr0VG%}A#VBP9n4!N4<#R=mcn@C6AUlFiD>;;ZfIa~R
z+A6;dCT8q<5<CrcTsd%e?z}J{g&jiHUnQ%e(Ip3ZM+;RnU{K&ie&0I=dJBa??1Yfk
z;w_$Z+eMro0rNyvCgPXcIw~9a8<ak8Lk$^#;eHqpe8#nRB$N7^XlT_cE7v|<rK4+c
z=n*WGzydS(AqZ;Y0XuO9&b*m`&VzH$v1|j<?<M#ukRf9fxgJtClek}jY~$|!(hKB>
z`sV+^t%MtW2>!sy4?R3O%`LQPvGjs?t>}JiX=l)_uOHZ*fLb`{ipbUg(CY5Dc#GY}
zjuJN^AN`Mk9Ngu23nkYz$T(5q)?^9^R5YhHvt4Y<VQU)UcM`HT$TQ!<VKfMNk+#5B
zjzkg}q`~<sw1x9m*w%trCh~iL4gg?|>Trf<_O?-_VZ2kC_!tr_xTQ&*O=OJ9{sS$*
zXnHDXp|F|5rfEE3!c%Z_*8@|Sfm=we8T4UU{a73!!;_N`bpP4pX%L6M_{bz{mC>&%
zZNN(SI}9txGeK(~yN`N>O~~%?2)OIwW{TVN5XWsBH%DPt!C)|2=*IY()o`ENBD53d
zxG<tGa?iE1nzbu(3O5u<cae=F`!hmV*@5h_W=}8zym9wogO=RMxXuYuid2Y=THU`*
zfWCh0mRSCy69|U|-iB!OuAtC`Q&~EB7ufdXi80)Q|A~aJxD3e#f)e|%I)eg_RX?x=
zyt|-`6MbEwq5yx^E>OWMZYa|eSnQg$3UD6P74kMP@MPzE$-3>l4ddsSx`Yr+ma0Zj
zHyq#`j0^TkmpIM6?FqLb7YmvN2><bruu6vQb9+ik`#(JiduRwoEx-*8l&u7JZ|f4a
zxERypmugI1I)kxqAV@!ke`94LL+IPl59%y>C1-IWRh{28YXVRq2j5xyavOOZ9NA4e
zx<i0kZU_msYZ4^(v%PO|z<hgF7s#rmdJ?=RrF4l@hXvTCOMG4}B?F!fagBE0zB^*j
z2R9`WA!x`r1Pr<{B?huw)sO*I-Iycg5^eRq>FHVy85bbCKu(5f%#>|B7!M_6FbzTq
zU;w>tOsGu=cM%tkoC}!ukh7@}(!xrjo`zYfiL?vHxi(@`^Zh^@=Dj`!UOhmrf*vq}
zNzxP3sIdD!J~l1?D>&sn-j9+l{J*2Fx0Jan-+>}FQ0DqSR_4ACWN!FLbPFkNkhtOT
zTS8bA;)m%LHiWqVrr!_JF8n0A#o_<?bPGR{_d+E6BT?=Ti?R~rYWT58`2LNg4d0dK
zEsXrj=0obH9msn>aL5cu^0mUP;ye(@jUmFtUnE_4t9a|8?6=IDoyV<!wrZLz{=|PN
zSo*i#z*x8Oe=1lP;zit#o(LW%g0F4-!0NvB6NV-Xc>)(Lttb)K5$@H3KiaX2y&LbN
z8*i+NZhiPi>#1AM@H?U73;*0t<JK9kU-<W0?hmm3=h}9byyRv3V|j#k9YoY9@^+1w
z$XCD#bIb3~?e^={?a7Hjg%r4ZJv&809a_oEWC3vO^!JH9>-F?6Scw0$8Bb#!mFVzJ
zy30XW00Zj0A!o2EH$g+VTIP*<gkza&BSxJo0%dYSWKH^}yzJG*UDh65KEU_rV@7VA
zFQmu$dJNHDJl#9KX8qt--o47AqOP0}xSv0x^u5wnq|G_hERfEG4<cjh8n=+YN$;*`
zjxthZ8<Bj>&I4Mqy*h#;8$#v!Y*0`{TC$vvJa@4>`gIh|w1<{C%ijgiW{X_oJOr|+
zajgjYY7Z596JtKu8R(gzWrzvS%JnTrG;vDTxPyrMBq?5jEX+chYi1&GE@BcNyF_KH
zFp?~8<>7h+@p3*Cb;FRCHbt(_7gJ<h7_*02&vV`~4x#t!Sc?HwhK+`iNBRSV<3b)N
zJS?QaFC7CKN5JG$dOB-{SD?KaGcx*cdOTSefySWVubX3s-}|2J81j*pP|vmm(xD+S
z1N~jyM@+!1JV{eX)7Zp+v4didZZ|LF1x8pJM00B39k^n(fb_P)kDn)=(dfxQnL_QD
zt)M;vc`<0dq4Xu*SmPR-N+x=s{KX{bOn7t*DJ%AHX%_uyfnDH{(a;jt3fU3xDC6vB
zdmsX23Zbf+HlzbvrC8n^rmB*r2=PUbrHv2)g>i0LO)1E7(G0uGAwU->z_ETr4p2Z;
z7!bDIk0?_N%c9XVpaK&O4kxDFI3B@zdkJ?~uSjqTObEH2VGkL3bUX}+y8YYBh!Ade
z=n$AjHuf1rkI%;)^zv*RgZwIm_H#HlpHVZEp3H4GArL*ok+0Pkvq~XbGV(`~Sl)(!
zSfN)#HVgSQlt?)&F~kA{j$oH`h6B}LIhfQrg5)DY>2{9CmpQfRFmeDfCpMcMk>lr0
zDo4z;CBYuvC}8o4I<j&f$7)17_H*yzbS3aCK%R@y-nXI!1Db}A4{a37_tB&}1oWOi
zi$$42#Eg%2%*Lk_Lzp!fE`TER!*+rz_z)1+8w>e;Nfg7U={sm5hbZudKDbOtqe~+S
zcOwvkk(j310~CnFpa{DZjSh*^-W(F~j_XqebVMdT`raOlO`x{eb`a}q3|(M2!LTxD
zOnET>0Nk-e$CZyEbQn+v$5dPb9~znn#-2nMTbmosGWdJ2O|TWb7HBMSTXGx=J!<0>
z@#)`zp@Tc70leg+_an47q#?_K)9z3K)Q3KSaOIc{k6=)chNsh}0i~$IMCi{LQfQC@
zcL-=`2P0XG%Pff-jXEATFg*)_OtpH#lMuk^V?qzU=2+7b<x|G>M-DZR?<yz<!r9A)
zMw&r(0jl{C5ZDG98$2SoO|(^zt&MmIm|MYB1pbR#lnA$HLT}&<5LyN>23ePG4ZaNt
zp9nt0hSN}+v+KV!IIrMm;_y8+3CDQ`6_E_!36nm3ME))+4|SR_AjZXIK)8efAP}Us
z;kXG(7}oprARC2*HvlIJkPyy_W?rShn-*|3h7pWQl=cOCdMr^cw<c|5g~5((+V!t?
z&4vt3Da!$90S7k%@$bwbrcX)Dxg!B;2`8Z@Aa~O>P)5L7Gy}*b;1EUt1p<wc&45@H
zXvuD%5`luzWIaP&SQn^ctx@MJsg&pOf<)7%kt-LKhq#2p$L`cf7`6#Ec35CB1EMU=
z<l0o0OmT{V&zyoNPwL87%14vIy@EQ!Xc@4eh7N6JxE8=Dz|ypVTLj4+EwmjHc^70s
z;p^eCg5K!F;8Ov7Y)nU3N>x$q!-C~C>$UH^hnmhhvy|zZpLa3SkrgKk74?vkdRI#!
z$K#Y50ar2;1ypO?2y_Hc{Odky7twt^nwS#((y$bd8B^FHtHLpLuVR?Bw0<Mflt{oy
zun&Mvtv*AWiojzSw9`BfbGWvGz5)>c=U@8iXOTH3T#z+pnI#)WbQjbrTqj!<_k#_u
zWBb&gyuH{$R}=}5GgR-C8V+WItGGlTHHIiHJ<pOlUqQA5V;C}XWB|^h;Q>#Lq$1*0
zQuT@m8!@7<atBo0P2w}In2*ipGURV!&zTtQ5$?k|n$GvNn4vZ+^yJMd6>OsbWf+cG
z-q7uqLFDlSiH@h5fxwwLn-U99h~9#@xQEyjZab%rp~X)3V4UAdVwR327UJsl;!xHc
zd5!AOyjvo;??3&)pK9nDypte(=*Gdm3kW|#cZ7r*;~RS1EjFxhtKlt3t8v$xNGYWO
z#&%%Xqxs{W&e7k3E`>YJ)`qhJs5Y!ugeD*w;OOzgsC&y`#l%f-zlL}hWSd<j)?x~N
z2Q;=R;qo&Xunp1x>m#cKQ;m;q!f+!XIXQrHpPpDim!pWONqAgvaP%`2apzn)cxJ$l
z)CiJ(^c%1%&`u75aukP4V2`(e%s}AS2#7#_Tpi<G*!aQQxGEhkBn78M41Nu`E;P-l
zV&Q<a1*+Oa#0gNa(iD8oCI)bfG8<N%f;(g-43FXv`l!n>U_vuIg!{Tr=(x#EbZ0$L
zI3x_Xq_AZY3UWWOV=x~aE10IWW3OX%O|6$^4t<V%P~YCiz8GO3hmsxa%((P9Jyq!R
zwR*O1xv;i{#CDSRog;@S6rpSjH9L!bv+gmZ)21`<a4LyH&k^k?rm*%UR#z+|Vc#{M
zWc$2sI`jp|QU&d_4zp|q<`dn9SqkkVXkVS|&SFDGQ4s67L^atj)J~ej7ScBn=zoE8
znXc#hZ-_{yW8K4z<Y8fK6-;d9@f_u1(75mUpTpGEs&^MvtMCl<*7}cdD^_^C^F?YQ
z53}sq%I6|2T8q!9EO~ItW<EkD?xJQN$?_Hf-#tQ_7g%RT-phPs<4PYS&B#G7h%n)}
zhUN^?RKYIVtde^Nhg`O``96M#{-2D!4R{>adEYxTSjj8ZNq5c;R)ZBp?KwLO4!{p_
z7a#-EaXm8_P@n{byC7skiV|TV(2-lG7HQ|k?!Aq77PBH?K@|W~wcI)h06~uI%85kD
zj+3Wp0E%?wTeT7y`&P}9-imab>-HuoNvUm`o2S0N14@eR*nPSrm%x6^obPkq|NDRc
z@9|+}M`!Xvx}{L%Pb;%*35lmU|A4*I&R-DE%Psq6(MRG7(c45DOp0dDbFx|fY4yC_
z9`q{J+FrZofoczdW$UoPL=h#_=R{j6`@eqo(bZ(gPUnud-{!0$6AQ38ydQLC%5C&F
z<x}}N0L*;S-1-hrDAsN<`t5C#FWI!A=_9!J&cB1&Ce*vf9Aa75WMuDAkX4iYZMq*|
zLjPMO5|ff>lyg8fwmCMRsn+V+(tDrgs6vd?FTe8%;2pko?dh>E{lxtKpT*{%e_tX1
z9>M-VwZ63*j_ShE_f*A0;ndy5@5sjRe)E;58;^`<U)gH>L-~kC55Mm37_Qql*--s%
zwXgcakAvhr>L<PJ=)~AP_O6)}T%!2KDYx?)2q72&LDi4si{U5bTK=&$dvI{>!qW|T
zbN-RMw^IQKJ$^#gYF?yvO%zbjR7d*F+dw&s_C<jp^2A!dW{vKvDR+MZDDD?#3UE^&
zI013$czE~SyJmKf>PT(Wj`(CV-Z=O`bGCeXST(-hzg~t|Sw8<qHxwr9{q}25Ls0Ex
zsibV2^#CfWl>`aWy8++62xRv!lTP-b-uwQ2>8ew>yP_;;e&Ck_S`1(ZAnoV!stdGg
z$z3L=p6fpTMJ-0^KAx@RBqF%;-Kb~1<~QWv8^dlu`*o()eoEDFk?gkBdcF`T1@%k|
zMC@*;(j{pFrPc@G*yceB*X_yskzp;`nE~tAf9;bRK!qo_>@?AkysLox<<Zz1IPsS^
z>a^H@LDX=4KK0(KA;fq0H|BLN<*+dc8u54*L4-%Tk-5F^&mfNGM?dg^{G~ZbBU)*<
z`~!~IovEI@TDPf(v5Y9G0Cd$fHM3~he(~E$cwVgd-q3ACbw@YKU|DjwYFm{R1r8+p
zi9jZjp!+kb2q-2i(t>U`njxAy{$OnvFk5#YyWrhJeSTf`t>ur%1~H1G86Rl_Pkwa$
zM$)d1d{^2W2zDVSI!<)H0cmoSax+xGyPkkRd*2`3to+-X$Ii-P8Qp}venOieP=OW%
zyH5brb#%Vdzyu9ZaCp)_b*pH1kyaRS+zGh2eq9jLhOnvW^qdxRB=zvfI{`@+^V8@7
zva89O=sqpmktGE9T&dyQdO}hDBN4*K`;RMcos`N?R(Cj+hZShKV|m98s3ZS(SCQ0S
z^Qoj$p9V?<xdgZ!k|OQyNhtl#ieTb%4(g_jr?&-3t2k(NtUbb=z+@d%1IA3y#v4$g
z%^u8;-B9d;U~zJdu%_S=B<l?+S^S<8dZ%jvze*qY-RNdIN6`r>qlqfb`~k4cZcW5=
zyT55e${g%l)0|A8-v^p<7Z|DlP8S#6$o!h<?n)jl<|gKY2{bZ9+q7+>pM=}Fp+5f=
zx6N?=U8Qkd34jbD=T6yxwAo<lbNXy;bqM~?O?_^_N*N=fXiMA+uC#Jx{+}SKc&)6=
z68fbqnoJQc%w2#aAt}u@;+8q-!76ST-m$Ms1H^nlAd{_!u)zqH16SYpRX#2^nZ<T+
zFOnwq*w_jfx71Sr+I6w<wF>YXoY~IQ=WKs>Logb00N*OTT$KY|4ByY~m44cN1$hkX
zah`ow|9tR8x103^vg>*K(p+?}cppCxz29Cha{wONBX^bI7S2e<F-7(H4&p&#k7mPG
z9Z<-LJed>M?Ym>NBN~%OCb0eP{?J6R3sDilN*9$;75<PhI(g{wN52!?TSF(ql5Vh)
zPrXXQDW_=mXW;f4h1Xt#HjX-gD%>k}se>kYq9INW2$X0MFt}N%`tq(Bq(Ih`diCEi
z10TNu(F!!pt^LoH*TGr&L@;ORw~bvh3Y}Z^D%vUf5G8@?WUC8OU*$<?;dcXpPrhF~
zY>gJY=)%m`R2zo~@cZa}ikeur$AK#_EnLqlOVjDMY#E?G&Q*#G_C2YbmP@Lp*V(?T
z4RNCN8Q&N#hV$!^sywXtLBJIq<~)y>0M__|Lc2Gz_zB+0jQ)?9{#t-k%l0wH%1t_c
z?v&SW#h=X7Bb032_6a9?xP4(GbgVG;|Mw?ePk>i_9nS$pjc^Vz4D?ynSY!q;HGJ(8
zE@0(B8;U5*(;TEgj*41~0EG032rIb-(~~o--WfG`%Ekw8Rm;`Rjp%Jr0JPTG4A0L1
z6)j0<r0?u^W@VYpkOVbOmD_2#*&)3Z?&<XCEfgbcdo#SP_!B!)4Si~<cXVdGzE5n+
z&i>Ew#&<x=ZCO`9%Xj2m-=d15Gz;#ytu*`e3*nCx698>|OHAOBxMFVum->fv8$?~X
za_tH;E8F6=KOlemxR$^DJ_79Tox@xCj!42g_~%#Nf?~fP|NJ2+_WLgKgGviPpWBs+
z?syCN-0*(>3<q1C`;L5sbro1rvoT~~h5Xf+We#vWL<!|B2C7}!LSE+WU-+tCiuiB)
zp$(?L@wn|@Z-?yt(Ca0>w0&UKueY|Zpp4}059t>$kuayXU)i=Q-g)oBZ{N6NKRj=<
z7+RH2<Y%P#GOmQ{3sI<~joyL#Q&?j+pD)@L6r|nZ1n9ZzS)D{{W$GxZJLN4Xc)CRp
zxMB_PL1FUCww$ZVebt3#8^}t*4Yi4$ACO6sOn9|Dc5x;zF<<&WqueS1;EDA)YX^FI
zIjhp%60O?qo)vE}X$l3srPZEMwQ^gq=G>;jtABJeD$8yql3C*^t87-hFy69_S6$oR
z$`>a3ous<Y^`_NE2TaKGlRh93v;&%m&6xzi!7{ZCmB1oO)O4HjocA%&mx*vDKhu_K
zJqcxlXj!P6=Bn5!F(4GLfMS<TuT}GwJV=0+-w!fHjA@tgtTONa<lk=F^P7aj-T0KA
zn;T+dS_WA5v&pN<T#JoCfDC}Xl4*pbYr&L<k&t%cCp244)CQoS@W1Qc;_Q>yXrw(g
zb1y+Fv|2KpiE8h8&b}b^?Fi*<Na%1##_qz70~qyLy6m*KOzHWwMfMX_;w&gU@0Fj=
zmQDIR81YRE&XP12sN?V=Xp}H(rLF<ng5%;oEt7nds;!<n*~Y3~FYNmokd0k+L6xvU
zG|B{b4J&RT%=B6@_F@d+1K$R#uB8D$qr#SYRvDqHm}<DU-3)<ZTqDL7eN}~O<juRr
zRuM<sL<(Yf9*itmlv@Im&Puw+T<i6A*tYM0qFWNfu&&y|Hy@E8(#lTT$yEmh+f<R-
zV&rRn(hf7|$_i4WiFsIAB3Y7sJ|z%nLK=P^wCNE!&}>sNoC~~T`G=d~NZTAR^PocQ
zBub@KBbKw=Zd;c>^ob>Kp$((HmKdrsmMsYAp3+^Y<{uK-c!O?(8&+sXFA;7KL1;yn
zXv843SHUd!m+ZFMA~TEI8gvs>0*P~3mBCA_`+%U3oCiYqQ+G;$_vbvROdCZ_o!5-!
zYS+X={)|ob-!o2O$U7XKh8kBRHJHa>Yb6TNiW=wlvUNX5EszOfGNQ-D@~yYmro-MX
zaH?VH&L!q=DRZgU1u1q^-BmBw<jtb6`%;@$E_@ggvH6%?>p9Rrw<R%R3(NMx+@PB$
zjuouQW>X+p4KNZe0H}0qck5D#;R7mJlg3_=pH($gT4(etvy>U`M|U-CFV})K35%?s
zqbp+2U7_*Wf5Qrc=I<#M91uzXi%peG16RR;L!W}dW7xIe36v+1v^Q#WXj_54CWKyV
zoX#n2?}`w=TT+H=5GX-V0&7}1@CFqQ36%gAq*9KYB_$fe3G4wR842uP{b%fYH{`5T
zAd~@X(I|yLlKi&?YHkesr0@E0JIRF^P=XNS+sQY;L2c-4s}gJ)w6iIh4=KeUa#nbo
zlIhK0U!!`)SSce}C6k<T&em8QcZq;AAr)n;factNqzxF)Cs=1iHguP%JOJz$r8x>d
z3-{9_z>>yId2x{teGMxDJ>iepC&o=~XzhbPrrD&FlxD~Y3Al^bLAAki-dgD?7`QBV
z|IhEcP7(|M1UM_HJUpWlW_#dj@!J-GxH8w20SGWfP(k(pm-H3CgPG`AsUU$Z_1MW=
z*j(v7!`T%EY50=e+ZC{ORYHJ)d|4?AI8|dQEW@Hr*(hMG0QJsl*;aW?)(n5tl8>Fc
z@#Z91WPuGp=~`wBFb`q_u+jFOwJ6RAg+zcdT4lNn$rR?A%+Ff~vWZI5WI@t>Lx4Vz
z2Ca>t9nILH*p5udnuZ5|{V^Mo0*4bc2k<%V7M@90flk>`*B(hGqGQc?mK3d)F>1at
z`M2g7U}<mzPAi%a^<5->oq1-Csi9xmu(hn)d=9f8SJp5VhEX~rH|1W@UGt6IDj5NS
z9fB4DP-SgGDt5X>RoVyGUJOjW6H+`^uG*f+nVa&a(9Y{Oa}8M!?LMp_`7GxmM_oR#
z$EX@4A~SAEmLTPpLiYwcH-lTSDvi(CH`0@^z};jMzI=*@i-X!C%K-7*l#rnhDpmq$
zbCT}%jC{z|Eka$~pi94AfL7Ebypjzkute_!^3g#i^lhrKJw80oxa~{^kAWUe%rSkl
z+%WzTJV$uQXcg^%uvCd=r=<uSAOV8qE;6BP7te&5-qgkiX3W`H^%<bzQWw|3><(`T
z%$9|}Hsi7Th2i0eNRQVr7e|wT%h8*kJ_^Bb&eZocf-Yj{f$Hjj)$N&e6=?0`Z4{Ex
z$jY${NrXIfIm+PsC5V)}!<htCRSrHl5;=irxYK|DS>LWD-cD1lvg*swqUK16_+BBi
zTV6SFUmZV*TNl8y1)Iq$gK+GIoi>197|HMkfPHC{VOc<A=EgZj90wr1sT!_bl0f<O
zHbtSK6o;z7!~@i3@t52}wV)}tYHG=0kMa0K<>B(6$f+vi(^lJ#+m`xh&vi?JoywTk
zU~KL^TGloxnSu}iFg;_MoO}zgZcElM%PIa=k)|bpYTsOXkJDPII#?3UL$1br<*9OW
zxoj~+_mD76hGsvza7~tN>{d7i9-W`D>vGdU;@PN&!-ti~gx>Uw5%&F;qe!wC`{n__
zS>qB`MT7Cfl@?7#3toZTgKfQ-<9k7tjg2{<h1_d$Vu86X7~|Bu&(whG>mszY(<bPm
zjhVVEd@fqK1#=W27!)}0n3Q}P&&Y4wKJ<@|CZ9jwzm;DM?@4TV>ZXJ-J-z(-<JvMI
z6+-t*JztraA_^Xv#uIMM2dYF)&q8&I1%Jz(yO=1#f2wXRIWWcqnB(x3E?!K?>v*$R
zylAT#QCqB5e-GB|9^W}|wMP{%V2`Z7y6fBGcx?v9TT?i<s3EZjDkWRk`_!$fA@j$D
zXq0;<)Q++}I8pA&587yg&B*0^57=p5{C0P(`xftgg?r5ROqBC0dHbWv{3wgz-xIN%
z9ce^;|K)=_J?FVz&QOhV&JGWM#-1jwWO=9knd8EKz`n)pt={~o{gnw$yL;@<%4E-g
zTTxB9P^~4kWUl5HS8$#|39ijG=hB50w>Fok^7H;0%BRZiJ3hQDdzxS?&Ml&FTvf|`
z$NN|Me<Odg3<0*#tWu%;AHWvq`HX$5oT=t#26xEbt?KUcGFchCrPh1ZCO81huiSG+
z<)0I{QH0E2A?i~+uq^!#mhY<FQs`T$cDLJu_Ff!ZiUZ3Lb>6$A!VAM)qJksy9v#-!
zgUQxR2>jPi$RkY+>+t`B`%@rQ9coyC4+HAc=Vr;e<+q#LoY5bC>S#a|R8*?~fS>fa
zW1p#B%h5IEYQVJdgf<Yd5(h<vkFMF*fYsA)A*g*i6HKk%=N6;$SnXo+9)07_!Yy_5
z2N4JGReY?iqRGCS<wyTd2%*pKf6l!^GNBr0g#G!`u6<lhh{dDJUiqSII^AoH&eRvX
z%~!r?Ka%ZCwdErqofUV*FPgQ-+OUoeK0ll{A)F55^?huunLeu?Za}OWd}Y2dKmKXq
zhPK~W-d1r14|;ETV8y*W2$k#Tg4zM@dh~1iyS$qm0{9zs5bc9+oD$BhQI<eq*np1!
zIbJDCAj!c&Bqw*<5{&Xh-w9xl>i*|y56BP3w??OHhbBlxG}xB6P7HJ%E1VvVK5%Ju
zFof0hA3lx1!TzHn-BBEpY3C06V$yh86G^MDCn4^WiiId8k;K9ypk7ifQirjjrNCfa
z1~jgDUlII_&E9!h70pBehx|v;h9>u%1oH!_Qy1o=u}k@@!_W)CFne?uuEz09pqp+x
zA@m<&=|veL|5-=iv6HQKOEW}va$-<|M>?fOnHXam!sBQGQCM*dD{bAD{t<QE?t5gV
zne3Q%h#K$SE;zoS#{uC0GM`4U;Ib>aN!*c^+fUlwHvMY=h9D(h8#G`Nrcm2Jwf%L#
zGk<*$o*}xR`(!Dk=&rll7U$=!*KHISAj;O~U)aUL$3AEdy;lv4Sa!{;OxVGMs8F!|
z`7RGEZZOag*dOGDYD~tWK1+M-Kh5|8cl8Gl+SEd&N`4gT+C76H**>u-SqO0nU?+L0
z8WJG^xM+{qkKbvgUnyFh;=Gy*Y3`%CU^GneN%BVlMuDTFH94T5NDq>gXeN0U9MGlD
z1fk#7zQL0TTW$CMD^~C-td@gIz>3DOx8J4_h;Y_Qq+aC;=34#Gs{J}a-zN2#tp*d-
z_Y3QYG)cuYdOacW$KLf@PtsXzItzA}QMqChV=kA7Hm7euwj1;5{xwEtqhA{7F0}lu
zM;Y(xQIdyM4Na^q>2jhN3S7B5*dajsV3(~`12nO<-N@(LV(coC7u6(3-0?)7{7qWR
zG~&c<>TFbd!A>Wtz@@4#_cO9RLdt7(Pr@&J9{4*1?}hys->hDj;feAZGcJb8rSoF#
zQm;Ia)tv%{2e)`jj|Kxp>FO${#B2Hwzf&;-AXF-(*lmg3Gzhhy_eGKpSUD)A303J1
z8JykdD7$r92Ewn${+L!Q;}*?Hr7;|Pz=T;@FEg|1q`VriDyJm_%&Ro=2Q3d^TyWKH
z@ZBfTq<CF6%3zw$I}Mxz$of_^{kM`ia`(I3$B*Xc8c*-f3uIG|qD1_31<m2^i8AAV
zfi{ME-31q#V-+Z27l1pk36dEpJ#Gku8ms_>aaHBU?1T(-0w(qZ0gPA_ZYL6&YAOv3
zvFgo==r~*%6Qmc?qgF!D^!6)=v!fZ-5Lw<uY<zb&Y*Nwv0VE|%J2%+}7+!45z_BEk
z*q3$&Q^TwgV@Jhe<7w%poqL6!Zb%l0r6^$9?IEr2lq$W5W185(1ln#mmT<u4ZQQCR
zNv$}Q6W$Vz;X^se&aH8Q+?ooOM~dz6Nu@SBG-r+GOxJXCl5?%5*`qY<9BLD4o%Dt8
zoq^743+SI8%!(W|T-Ga;@Ehu(Wweh?Z2>qOV98`vT0`{JpcG<H8WK}0VOK+R;9QEM
z+8_o#!ino{rX>groD37rBnjt6pZNKKwhif&P<%s@E0d^4J8#m$0b?`apocas^M-Gl
ztE_i9yerl#H<^Mnc3nHa+2Wkxz{V%KOe8+N623O&qBuCOqA@F-Ghc^u%jPzw(NR2q
zOEZu}*yvDdg+r;gwr1k=Txv_OR=A-<Jt{v{8^-szpIyr7e;CW#(AXyoP&QG?AcQVT
zJcKll&2_z6Zkv;zOl9~kveBOGvEpNvI@=`XzxV2Qo}WJa{rKq4^=s5nbWN{i(W?ES
z&Z6~qkBe*hxPT%dQtGe`&FkEyiInd^lGoUwe?zzRFMfn>D~!(V$o?Jv+u6AOMo>Q7
zQm^kXAe-u(UjLJ9Tz{?psx@T460)>zXf4@m(B@n4=wJRwrs_61biF_!ejurrR&3=e
zKbVi}g)0~*iBTzL>+Ae?qaiudhLsEh<VQV9*7lfU^rW18InWQVd~j6N3kwhI_?E^0
zj5Yl?c<z5-Aie$I)Bm#vXXv*dfBl{9SKj&Jr~c`fCE!3kO2q8qgJo}D;nlW%0gRH!
z0w?K*Xt`ik2r*oRBOxAa=f)mPUbKwBdC6N9Y3mI6e@32`HI??xBseG*utB7S#spc#
z$r7ba#my>m4*k>tAgQDxG9c*>fF|X<E!jgz(UWp`hwp+Y2^Wvj?k=OSA+ZYW&;Bx|
zL&;3wp5n=_WGY{hlGM^J?3quS9uNgeecSAiGyr5kI5d&06`Lp>!rue2u~iO4XH}Mz
zOhOmSWrspPb(v{wBGm_{shwEh6WGc=wR7WPMFg}2K|PGG3&Y2V2?od<`I#F6>r^T>
zHlHY3+CEy8QZnNgO(P*<5j;~Mzd^b^(QzzHnqkKuz@^ZFItsX(^wx&`Rq1>CFkY-u
z+m6PvIqY}bW>_v+tVsgWxjWZE0}pEUczbymoMJ%I5<0Hd42{e8A1EcVidsn94SZWn
zuGiPYJuLI<5YP5F{1`-2D&E)YD&P%YAbB{vdpsiXPA6qq@M|YSOu%y442kS-skXUj
zKPZgx5%;W5w}6<m&PPxyY3p^2!*vOz?xHO+bXYF6T4y{_TL3>AH^sQh3}ZeUHPBq&
z|F>nm<mu-2<+78@gt1J&5!T2E5<?#``)(*(FA^4r%V;Fb6fz?rcx?9exgZmG%5*ME
zcYN6fFH9NRbc{JCO^Od1MmrH7EnpKeUQ805n?#U~0Mu*#jEnsWE5|P@lNjF1|LPYF
zLaPCs7f3{OZf5PF;`PU(sV|J!(Q9e7P`R&9%qFsuy*=5{ulCgHV+!l}z$g6KsE`Ro
zJYI9rQ&o%0z6@J0l88B%oatSvmcm(z{j6uka{??yG3gG|NQnvLqVOET2<~|xTowJ0
z6jNFCiZfweu0XO3g(@qrYyyP<los2Gy70pF#;IJp(UvKa%1?;G#75n}o#biFM2yzl
zeqzx+FZLC^lQI^22-4&xn-zt|)!e?`v!&=hXTg?gP2S~xo>iY|(>e}t+!eB1N1H=6
zcAc64juqo`CKxB#-y{==;SSaT1zK}FKa{M=a@85IXWMxdWd<nQnkGAGg^SC7^84iO
zA(sr@=*A1k4vZtanwTZ5*^-pDZ|X&7sRBJ2Kq^Q<l{C-~{=gO(WDHaye7;KWpuKQ7
zvFE#>GwZLEXfwU?*zU6szQ~*u@+<SnFrIzj2Hx<zB(1OS6M^LgoR+?fhEi%uK<U0=
z#2fTNg+ypv$oiX=!uYaVQrO!7l@eMS{)MM?aJ*`RM6y`6z+f0Jss+FaGlb382)AL3
z!Z&n`Z%p@<2#PkuVUvQ6N15;Syo(xW@F<(JaxXzF4vkIC#R^5J%iglUyh0X4J{80!
z5TcRmTnd@49z#vyQPrP%YcU00w5TfBZz}_3E~8>YUmSR%W&PVLEc^H{0+!OS6K4*a
zA;P$0L7V~lg6VDLoGkYa=Y-?3*tw(zvW>iz5GYUaz&mnV9?Wf28918>B^h~!L1mU|
zMjt+R4Q5$*{B`|6)~ubfRO=HUPAYiwrqAV6HpmuuBN!8}d2|KI4ztOKnJ(HN3FE}0
zt^_G(;({kx#*ET&vfU3mbJgCYW%in<TITKfuoKE?Ohb>s4JU<BN6yuOm1pgqvq!>9
zntmq@qI7dYSgcMk(9r+lrIINr!gas@tMJ7Q18;*Hva!)DNeGTtz_I6sIfdqB${?NQ
zb^vo{ba-zX`wlc?8)v_oNR~YR?yMg#;;OIh(8oLzS~EDIUN((>s~?QX&9#x-w88y>
z$uuQ$%V}9<OB$E|uivB~63|+Y?A&Y<YbM;}be}sTLi`@Aebh>XEdZs0+3k#(_)rP^
za?@mK2&7dHR0_{Q%TPYV3GmWf*FK5HBrH#C9mNDIaJV&5UIi>Ndhp07i#YE1{!=&7
zxqO>#Py2vU1`Q)9XMGVTc+N8uvR)aT%-MkOf*@<qvNQ(Rx<!C?wJ)WiSUI>N{m&-S
zw$Ie`sM95C*=hu0q+T4EWP#V#cln;UgY6Klh79-W5bnQ^?DTPlv0KQ*IhRnQ7DWhy
z*(3}yFdp4~-P{7_RX`{Eb|C~RfwGuO5*cEvOJh~mdhs^d5cib^{eb^8=*9t*jTMWV
z*5m+OwDt|X{>x}4XA>O13`H<v)*BSTS@;s8WrigdYH9=A>P&}$Nx$F{nZV4nGr2}s
z-2=yEr5I%TkISr$o)pPPXmH1PRkWM9B#>5>j^YPnQwFA5;@BLTL8iqK!vEA~Gi_FZ
zl*3dhj4}qbB(J8n7b-C{40dtEE_!tg{30a%ju(cDxBz`kpr#!50n^>99VczO$x4$<
z+tYbeKfKa$1ytFnQN5vQ$$G7F7OOk`h~HJ1L-@LPqS6|*Yf6Z|D=Tj@qL(1U3o9hP
z;S3|uG$eB`#b`aR@~1@QkRGTl8jKZPaiOI96jE9)Eo?X`D;vG4ANwSO(CKd{VQ4d^
z9H%clu0s8Q?OHagtvRzdtO`#ByuKyNCYs)S?WevujXr}+_Y`x{gK~Fre#V~k7SG?&
zn28GyCY_lu`La{_6=&?-e<qT6kNAlBk(tnVIh;(BP>d&>By5!S7pnG6BR_|%@9+7?
zyWI!3PKr~7*OKtVE1jn3naOY7^r&6=r2K@xCHsz7zq=wQqT7*a>idS>w_MGikTc?D
z0EhB{=j_w@)3RABo)9ZYAoooW*j`oT8I@asE;a*QNc=SFxfKq2X7^P|th_CG*R6X;
zlx(VfY?*V%y(?$`TOIF`2Xt4Nk)GRJXr!G9pOB=T$gPHfI!>0*lVSSIvb%GQDxC~v
zSgGM7{tMqpRpG2RQgsd=cc#+2T>d*BQo%wJqAY@ctaj2q+(<@F%Zoxn(5rR-)cPN(
zmC9`s;Z50b(24w@x>>$g^hR6qz_LA1t>#~p2bvPLYtQk)nd&VncU6g+=U2|CC9ziw
z?;E^Db<fz<g88bv0uTE=M9c0KaCiHLcga3Q5bcZJ;Y<I-D!Mw}{g?{p8+d@up^R3T
zijO@EBH1E{-EwbVdn(eXCH{hnXjiG_OOB3%AKQLvfQWT#kkfQ;Pdbh8Ez?e;mO6x;
z^i^Y%PR|2#x%6T(;c8&g=}}6*E5o-~puDEx$ZhnJ12mB3L#n+de}EFI)HW})*y!_7
zF{o$+HN08=*1x!+-hRma?i!pmW0&pT{VU$2cm&nZ*<FOA-hTF3(P@0Cb>#_nsl8d;
zc-9@6Xs-?$f{@gVTRb{?d*nP)9i5y6HUGEY4Ez5iX)K1t!6)qb;+5WB=h<PftWmgH
z#fg`@KPG@?-0t5VJnf6)N^>T&x2Ro!F*iBza{C(j_o{=>pK1)=8hr^K=b-Zl7{hbU
z!8!XPq1K*V9XN_eBWPhnpgF38&#B+AyRRzwEMM8%0XaK1q;y<8P+gUbIamMv9~;Da
z%SIm|u^zeSNvPw7$G!>~bo^P-lnHN!fN&jaHSeu*o*1y=)xiNf`+8y$jJ#&sdn;sB
z|4yV{baiy{llHg%wS>Ib{geXWpG8*`9n~umVNz?;MJQ4g!}IoOMO^+-8(m3fzlNDA
zfM0;CvN!_F0!RV<3@%|Yw4XynW=-uj^A;akQvu`Zz(q+2J?PwMdNuhwfyPpIxTDU*
zywPulaWLhD&vGi>p>sTGbaVp{bsNCa_!-%0#wO!~Pv-F>0-iw)y*QyjBOm{>2m;IF
zQ0ich60%!tG>|AIyN`Xc?d|{L{Aqv0a=|q((86^)-=2{}Ku}vG4MT=NYzq(o!8*k`
zxVw}eb%Q)%z^HYu)m*kq^3C72tpvGKh<YTcaElyKvAXSnu6>LtzcEYOS84*WYk?H2
zU5~+eNCEO_kuY;&tk)$lXzj5Cm_uY%8Ah>NA0K^+OWeJt0o@QvC24>TzR}y8IK?Xt
zsRd!-I=z>re5^eY54~5U_3g}3&05(4tZdu)Cu^>xZ`z@z5$=WnTpWo8HMMeNt?ISt
zK57~?>{WY6fwI-|R$%$Xkf42YG`YI#tFKEP+#Rz&(n}e-d-Tu&@ra%CK=hybNdQ+*
zzP@IH#?2n1O=F|uW(cs;V324uHeEY}B-g!Grb$7e-O(#jYAzrW1(VLrWuuazuFk=A
z8-N~6wu||?pG+KxlvaS_K;Jav*=OdS8zgRAf}Or0%Yc~RTQG3TeNZ(eGhy_r0C54(
zwiOPnJP*W2Kg=4QbVaBGoWt<-q!An5T9fF6SI6uPJ-T)&H@Cs*a*&fw(bV#t_QeTH
zJbp1!P-`{OwAlD2Do+&^O&#hcQ`c35SUj%R{joBfVK!y!CIMBrhm1oL!akTVRNEJ&
zjTYMet5ss*r7+%$A4dbW>vokv7DeYZ9vk&5-P7=Gj(n7{E=wloWNsG_FYaNF)DMaJ
z*-FZ#tjmswTNh><hd`}g2~CZ^lQQ;F(p8eCCWa#L>Obm!>%T+tO%m=iG5)Q)VAeRJ
z9YlCPUXc^CzjUI!JnU6ggoc{;qvaaPb|jAG2ez1r4ACm1)qP#G&j@?JsZmbDYnkA+
zZ6HnE+!0V`_l(eB>kBNf76cpHyZYouUQcY?_7+EcV|1-L#}VmOlJ4vt&Fm&poqTe~
zGPTjM4duR)(Av78=aAxbw<T}?-poN6zUg@?9fx3Bzfbqj=vOfL@BVCgV1%Yjy-IQ#
zp{}yE6wy)kKy={&*AxzvT+sJzxluuX)v-Y@D`hzE1!3(TSyQi0WNB4I3ou%ZTl=n0
z6Qkaz>l04;f#W5Ov;7=AgO}0}4Sc0GT5XZl4NB++Kr7US#^SEX5B#<|zcuU?&p28_
zbIZ;IaA2_gCpC+s<+Z~u<0FI$m1YubvKG>#NS>LB<O5JcHJNNYI}nmTfD`WJkJYB<
zWvlASmg$jJXl^FqSRCs}cMq=SgV~aOqvm#!5P>kPYmg@Vz~$S)J-hkPxT{f64Wjn6
zkGqovU`=4l=3J0OQ|^28ruUxfb1Uq5TOGaoaZ)ATeZa(9XjYc(ZPI7GY(O!^foQ&Z
z;t9!7m6e*<Njqg`PltcDtq%IbgwInS?SJ8iWIg}>H8}H<`q7Nf+qQ$<e<1DC4+gvc
zScc`_z(jfBgwkjxKYXnAhu73jcg}r(@~F4uPTwxf-nVjMomTKqb<q4<rMVXG{=Wif
z0<ylHTWjD47@r$D1J$qmx01%UbJ==2ZssP(!koqC<7iWsj0OBXg>Nd1VSj1@Xvhh5
z`?2X^hsE1wA(KQ~Mi{D44;c##68&gl*(8`w`ZwSB-mkrD`_*et+6>YUYy-@5ZIS)Z
zWBY|xM!%|m)Whwq$6MyP@n@G>*uh(N9eTzSjyrnB`D4W5zhRGkGqqjFL~)Se)E*{r
z5~{PtRy{o*18ud=47&?aW|35bgpIpSOm0qcF~Q17<8;FXaW7g*30pi1Q?6^5=!bb>
zb6jth!D{6;sCbJ*YH2~KOJ_)pvEsGn6l|7X|MuUesGST<js)gMoNn6i>bBxjhIA@p
z*yD)i(afCpl61~WVklMxX|=X|%&Me3*X0HqQjLHewh|e6k&@UKOJjzAi%(!Oco?bD
z1>v_X1s<W2#O%fbbo*$QQWM%)p`Bo*UjD1k5$>2Ixf>j9IF5cA`N<Z+_&V>FZaqbh
zCGjFAhqdI?oo?5ouNJxj=PWH_sL(MWZbB%FhEYaMjJ>W~tVuOooDsvNP=>08wcBrj
z?w0r-{eb<KsZDb%FzEW+^;9J_eqZysRLhh(7MS?3xjSr!jx!(5YiMY|^hYj6Qk_vH
z@q(9#RKzj=QghQGZ{E6u?Nub+yXNfka`7on<Sk)m;O&j)V{;hjygxZ3J+fI?Dkshg
zMcAe>ZfzD?E6ygt!K+wz>q3oNAq8M8?(<4lqyGdrOYE!25~0pG-N%=5Cmd@W+qY!h
zF5OT;@v4;)I@c`0Xf#@9oZaE|FkY>szrEu8Gij7?tc_T$;}E=dm)RG^CQA&mq)^rb
zCf=s<ro(tO8ZpB(25f^kl(>l|pth{&@@-#enSj9zMR}J9XAcwOm>cpI61xWKS^(`=
z;lM@NZg{PHV)c2EbIRF=r2sax*cf|ORpo(9#c50114@bu-}D&@r=9j(6M?+L7bCOg
zi`u5(fZCo=B|<b8A{s=OYNT!L)E}DJ;qCL1acfnKFt(yB!S83ZiS8M{_2y4V;ua6P
znNh#Vv<*k>`Kp6dC`XyYi7DdI8D$(;mtsyv*@xsT_BS-2k^B`;JnC%jKHL-|=3NXN
zb-PZearoO|Z3x-OGsANeV|^GqeJ(x63#{X!&r2-wkJ$`hQBbFa6+?zyQj`O}<sb!w
z!3dT<khG<2wkaH_xiUW0{Vqln&1V3t#TtA-zyUu=3~oZ8Z;4+)(&&39nVxu^kz%w&
z{1Vt9LlZr^Y{)nj#&lWtNy+Llcbg@A6`_9D7-{oX5M^{?`fwXKfexAZ)blrJ^e_`H
zHf0G+uM}puBr}aaUDD(FSrSK~rs0{2<j&O0Ey<aXu+ElVHB^a!pwJ%&C<(boi>L~O
z?0}S8%G8BYp=2}ym#ui@O$xFgwkX<?m+LeVlkkNv|HnoyB1MuthV!2#$>Sf$rWmnJ
zX|OIc5E)D6T|~vi)ID&*u}mw>x-{z&lg;NP*j|o~b6=G$i!n+W_Tdfzcje8N*^(xU
ziHff|pSZ-YzkFSq1FFa3ke%q=hs|;LpiQPZdAZvxL7*TzJU<s__`7`#mI<TccxD+c
zy63*C*<K+NjaS{4oyrx~k$uA&(`0&?#t5+VH9?2iif>b9XlzYKtw@jprezu5lbN*b
z8Vo%^KK{r!mzf1`k*1V~6F%)3q`C=#c}LJ%@WYXsGg2K^;XV>eZ&1IG^%OMMTd<5+
zw7Qtw{)n*p=4a?oM#}49+oBP|j1kiQxkcMr1n~?qGMAyafqCSqzfEW49$tnApiFd3
zXC%l?41^ZrkfMi_!LZ>Yh^oURmK@<!NUyShnPIXjjliQv2-W7QIE%*_QQ9{qV;Qh8
z=xys+*V<Ht3_k(g#&icIHH_ci|C2_{dH_6*%Xc5&*v6b&;A()%y6Aio?b$8vABqws
zqw`ccJ%=xewgQsItpg{NmNb21lZE(ERVSI!WmVKSmYyo*t(+w{`vTTUi_~A%<+TlC
zvB7i%RLPvB()VqUdA$`XQZC`Y43`SrLAz&Y9s>LQC{t1<_--L1Q!)ZYNLLs+T@M~%
zOSef7YXw)%@O(X&S%A}A5|*J<kSPgI*Yfh%)fQ_dXs4?W78T$;5m{)^un)8nODaIf
zGmb_g*Kjzo`snEZeb-WHSV*^cZY6|hI0*yS@MArA8PMEl#EeniA+>zWB7diZA<a6g
zx%{wyv!lL>a7taiv>SY{WJ(HZc`aKH-tCnerl!TxibIPQE>XHvgf-<E!(v*JUMs^(
zBa#`fh?SSL{XSM|%|k_hGKw)-sl15MTh&I5@7Mh>9%WlkDPqZLwXYs_OIa5z*zf{o
zymsm49yX085cawlv6k4c7*te<Swuh;aqpf{X6Bc=C=(-AF>DGn0T&ygom#f_3vzp=
z8y*V*{MKh3DyKJ}Y3k0W{7w1F`>&6+nF3e~@GrxXNtF$tX{%(SH)QxB%NWfyU}Ce<
zg@l_qB15Eng0@KJTC<uQH5}w0JQ~gLUSt=Kb&Yu0kh2t5X?AvU`Mr-!AKqub=RD(I
z?jyXUV|`>x6r!1}@#7-)WMY3Dxf*=Rp~g)MMKMGSS`2zu-f~2Zb}o1iy!eP5iRRVF
ztYk7vL-n2d>2V@7o@u^#Bst-p^$tfKiT6r1+*s=}Jv<|aU!GH2Lj`|bxc$wjaw%FC
z<Lwuf`wQ#iXZ(1th&QH3rU_pAx_6gfZg`vS4o}IxUI<uL--jYU-c2{9&ZiFkq(}=x
zLP(Oz7ox9o3X6A!g>ODwMM!`|LQ>ogg_Vf$S7+9wa36R;;<0Ao^ZRgUmM?}@t*AaW
zRC7;`P#pX0(8v}J!NP{zd1hfvjEv0A&7Dt|{qQb-<g|C(_1c!l0_cv^yu~$HQ;$f(
zZFZ2PJAS6wUMhrXxmGBLXT4)j^tt|BZhZTbn?-Ra&b}MN2ka+QvpmxdhP|_8wv<$<
z%lCbFHSzFNRIFA*!;E9c9+r)<W9_DlTarjQc!^QU4{wKk+Z$5F;c#tq$b-Xp%G2QD
z=RJ_aZ^n#5`z2loFLLa?JsfRc!tip^nKqw4koAgdvc(P^b0t)Oz$(b~Qtu;R%DKMO
z=o6dHF=X`nifh&Q7uCUw+n+%)4tu|H##4My#U49L&(+_X*mOpJo?!3~e5h=Ca?}0R
zKj@3ss+}EQu!}OYD<lp3#eTc}H1WFE06Y!0l{jpLknikxhwX+ydYykT_NURx3~<>2
zZ$P=H)zgD_+PKO_<6a=L8cEW1+HN7i6`__5ME_v?8I(5*Q!gKh)Roljd^Z~CI`{5J
z2J2@LtXykEK3QSLG9)UQiVI2OPn!qNxF^$rl?gKR?67Ws`l&Cqjm|SFiBlt8mG|GD
z4L7>YQ8-d}6^>;(Q-6Al2-42a0~^JyFapo;$RjU9(Uu`hu~ijhidK$)yK5xM{^y<*
zTvgt|E<#to9onBJQhU-P@keiZVSXZBh4%?P()0)HsaWk2$!MHOTJ4GXV-|^?&Z^E|
zxT48b3SS`GQ#}St`atw5boerm)Uhup{~S49QGXl-J5*s>pHEiR_x>Pzrwz@p;eoRu
zO8KZ8R-os-l!FTwk}FUWNl&g4U2w1+z^^BfzD6R5e?VTdd;0p<ZP<8LJvw-XRjNox
z`(QB?;%iR00qzoyZdA#TURtA<1h_{rKNauw2#rF-?%r67H^!xjdBW8R#R)-5LCub(
zq#~NVO|8_DQP7Zq=iLVMJRe}Fb8lqO@nrS!zxVw0JDl4ewB498*AIam;_JF^8#jb!
zz}W+b)EWpJSQjIN0!Eo(8k(2NNZU5XA@s?;Ua={?RaK;!k%t7PBB<Yg6yW3F6%0F4
z?ci>kS|k`gJ@@WlN=p{j{~W+)G~>gLto&n=1$FN2lYeKpbMGPJ-2cGVi>6*y2QMX!
zmj<>m*MVr_9~l%Tbp|e6c-MG{6fFCqF?xMx$^%`7f;V=WXF9*(HN|cXF~`R=t{aCE
zEZb|-eBO5BF{;rC1gxGNp=!Xn2SNEL8O1gShzvtTaUu>^Yleilw_b$|7rC^ZpROuE
zK*pcp17Svf8jfc6vMzf~GOo8SCJnD_ZB*8ks>dKi;M%RLR}bdm3BtQ$h6A~W7(xns
z^<|IY3nc5wQiI=3z86@<Cc7F#@SxQ)H&y?Lo32CX{jgP^FRONA>{@1?zE2<|0zL<%
z&X&Ha4l;CG_Shds3Xo~IGxecWyYPWnb%_7(6JySXO6swDGVv-KwFKV*%LG`b$VxqK
z@vIpq+lKn}z8lGLU$9t+3KmdseLfsL0Hbi+gSbeOHD-@(01%MQY<q-_4yl}z@$0cD
z=HpE80fq_SD#MT!Vj|Ki0ACt_qS~0(C61BJ{cad~6q&{{m~AacnyrcXbK@!EwprD=
z_hmx3yI4Znml6g!O~0srVQC@$e}Ea(`GmItRNZ){%#i&w<NF+OKd;WC*mdNe|K#X6
z3xnge8X&^ip?*zcB@5Xv#>Q+Vv-$9<eJ3SgjE#MPK4H6e$$#be0kEuH$bLA()FM#%
z%l~MXQahY;8LiN;p|tA|8BHK@1Myj=RvIGr*qPE(Ydm|9<pDzD159?kKFEO!^C8XL
z$vVZW<Z^|I`6vM0!4vLOELG>Flv>1okbTH^v+Bsj8`6N?+%s}<=Se%a0n~l!5UQ?*
zJMN~Y0hmFr#=L6=7h<GLvi%ux>`+R)HGcC(dsV)SoTVh|S2^4$7cGaA&B3m4pii=k
z4V1Uik`=bXVrE)4Tg_%HjS7~7wK=2Dr}IXA#z;9?T>hS%MygcrSSE+-&LrxDF+VIt
z`uMWvVf_w3#+dd}wZIHg)rBx-Nrk5(*Ep=K@p;bLi`MoBNJ78YjaycbD6?e6{T>FT
zB4&L68q{<c8b*uSjwVQLbFrmJaa7u)3(4-p-`=bL&)q)`9NZ>5{-~Tkd)P*QEJyL-
zYaGRmAL1wy!cF!eGS%Pj|4nw`kBce4h7G>WbUa@B5sB{KPGYnT4FV);Xz(39O^pb8
zJJ%lz--ZUa^V1`VNq+i2(E^xSmh<lyZr@H&ze^PUV&H88=Q~Q68*d47Mt5BOcaKkx
z9S)s%`_JT<LEC=cBjlVIFuOP(Gk7uq)@Q7L#V~`?qjF<UFn;u(!V_qg`psk^99Crh
zc!c1Lg_-uk%=*HK+7rWlPYml1=+BJl&rFT+owc|AVde2t=gOb|={q<6!9u+KvhMRA
z_uxo;?V+s+eX_lr9J)-nM!L}0=xuOL7D2liA|)iDS<E6a&ruPBWmvr`qV^f~P_n}I
z#lPfw%PzT!oTu?)+$m!!>8*-zU`-x<QocX5`pykQqETw(jIF~|kD!uStG%9_a7c0w
zW9)e>rkQ8}<84)Vai66ml6Vh?Y6}yN<MExuZ;`;WjS;=1#GWA#_*PB+`X_&etEF{K
zWuUSDvFoL+B%FNE9ifoqRe=7&CO6x%yjaB|7r)@iOR_!k-N??6hDXD(94+?>LZQyO
zZL#DhhecwRz>R9kFFa@~487hiLk(jeK!L=lU{jZ>)sABCQmD-_iMbNOO<b3kfA_oC
zON&U}O^P5jN0l^zoVaNwA@V(w8&(BjmRDpDdzPA9FbnflT9hGzw3hA5L2n?5Zct0r
zamBR7QYMYBXwXi6C>{l<>?)O`44E9LiMOdr=3NLtaF7N7DVsQ&JR~h^`_w)Ha?RF-
z=YP^bgqlozE3GhXL}@9UO-g2viHlY^y>1*10b4~H>vZ*Zig3X?Y+r!mSF&!Fb?NQ~
zLG*`&UypXmgj8<pggcBWI3uK}-|`i8G*8vjd^9%GP8Zjus$74U%GLbln)Fe;I}Da4
zD{lOZ*qH<msztR$D^H|%sc<^-jB$1Kso$=9WVR=s(_$?OtnPPvfqSD^DheZUWN17d
z$C-NQ<=h7oR^4Pe`mk9Cdj++_{6hJ(3r2R(R(57wN~;@cp1%*qx=|50RHoXi0u)b?
zX>Q0XnQFStsPM%XrG4XqB9k?ws?zy({>EK}U`V9I#d;h8LR__{+}Sj7OSXd&YU-WD
zkHf6aU`-1QDWMKHnWbUbvs`dX(Q{Csy3qTpw5|T+MKK~)R00gC{F5PqmvNS;GRDJa
z+&*UaR?ozGx`_0tuPg`>UsuV(3H1R#Q6#{G7S}r3e##p4t4MvFIrs<-wm8uiX~#Qy
zhFE{(I=|7rdf&m)7JxaZ_{6=N&g?>%F1rwYNdguxBvnBis38Uzb1O=1%0foPeH-%d
zR&U>!6VHygd)?;f6OQ*7DV2wb2_KnlCL>VCM(l^%2)UIY+MWR$7@zPM34Q6h43~%(
ze=r<aR(-K^{Wq39_MCdOFtMBPd~Zv2@N7NURL|Iek!$i%Y(O}wo`~jWr0Tmmx!cif
zq?WjG_N)e#NqEd*Imwaj#?Y;mDwv2NvV(~cw-W2cJRHU?$53HOt_$Kd-O$HIr<*|$
zj38C!J|KpcvY4bA++Z|l_=Z(wA3&1oFuzctGlq@Z{?5Bwrp@ZAyaX|9Cv^oxMvbr)
zaNJ?i>o2;2lf9FmToA8Q#jvEdT;nc|5XNY>!gM5>otX_W_~W%Snz#Ho@E>Tmu=P%P
z^%R>qnDCZ-Nxlhpi-NYSSmuB|H}$2}K9StNlbk?+1`U>zutfZ<2$Mnv?g2DMmQ+M3
zVwH>25f`sfrZ3~zYzQ1Fz*qRbZ$LZ;bixI|SK*-og$6)VnGqSLCO4vNXP^~ZYMjD*
zR>~&*sj2I7OrYMr^KEk@=mG{!1Jf{0#VKulDp-d6IF>Q&n92j-R$_D1jO%zt6)Sbn
z=1@?B_G=zaLicPjCPEPKV_44=O1EeY$M_8*3;Vfk1y)=pqPyAND~dCbA@`A_nA857
zzxI*fcjoPUw|TtB+-b+tvOXrI{kYYz8$q@zZb9>e`5o9670XUX%yZKSu45Htt+V1Z
z9HGoC27qCq0T^#*Qg~r7tNkU7(Zd6RuswqFHO?+kYH6$)9&Hr>BkTs_ol$qm%blNM
z_0t&eVbcMifsB`?!Mh2P&T$wQjTJgwjE>na`L2I9PPRt-!|{wA+PT;v3OiIPCif4%
z9@tF-;VI#P@3|_-q^a5mRotR$^=8-)SP}Y%Ev85*%CPI{ExxbjsW8R)XMDLq=el-!
z*uL`=ij$VTAUQVHai$0|lARCDx~Q@wGj@qer6UQEgHh>*nI+qhpyI$%IDw417Xohy
zpxY9pD)ubk&&;+rkqIGM;aTvo_C&-ea{D<Qwh{#^w<h9S<GU=kY-cLzvLgXj9bs)z
zATR9}X5txZ6)Pv~E<JG!W0E&0JB|3w)C#UQa^A9|;&7Z(ZZ0YkQC~~X*60-9@M-Ci
z6*CPF(|xSD^kF8<eT3CP#m0aB_D>uoq`-X%i0tubY|KwW5!zE@ft~G+#-f`{W+-QA
z#-5!dr|`HVg%DF08y3A?$J(YpORV7lYJN)q3z{X9S)gA===O}aU@n;W7?=SPFfP+-
z%Pxiu4mALTv8%uKzTighCOMgN$h|=D95Otzj)ZVFgyL#%!MM%+;TRt$5CAmNX2OBu
z33d;|i(So$g)^<1;YjFpwQ5?aBLS*nje2(&<A#Z{^aKr1j|}bPJ(SMO97cDU>=M08
z4tkrTV`sd}-rY`{aCfIl{J^r-$=yE_8vC;y+RAfI<q)n6%+1}W9Og+jux}t7dkNW7
z!|996pv{EReZaz%?Cteh_7iN}C^WF~WVVMEqmW@&N|d$FpN{w-Uui{cbEmlfKfTKs
z1w==2D9pA@&KwpI<&d0RF9hyp?HJXYI@4{0`h)8l{mV8%`u4Eb@wRZqFr)OR=++<u
zW)Eju_jQiA`S5yU1depz;)e|bj{ykdI@G;>`7gJgg*x)jk9VJN?m6&R_P<MxyZdjN
zGfPRe`1#|v2z%5HNA6jB{DghSJwt`6`xH7ueYY>$H<6;}6a9`k-dqlot+e~&J(In6
zM{zQNEW>OxIba``wd#mcbG4ywl*?uH28f`)gOoT!UU2=w^IkI&kA)NIW1&Ed3mKE5
zV!IljiS8nEVtf|2^bT))U4BFi_1#IH0AGgWOrMI*t#EGqxH?tCWvI5i56`WL{@M_X
z=U-6a=<(-%rYXBGkPrSB^WA?K+P~U+i$j9=<3yaMw}_+5J>64Dvs>J9hkZ2di1Wqc
z_8;~(o2PQ(|Lb@1&FE|nagNVKZf5J}+(9#R0z0;U$ys)6J5S~+`C|EFLsR518uiN$
zjD#aIO5I)_KRz@Q7G}a{n$e5qox<IE1}H+;WO$s)oWaBXsHes+M5le*vy#IYixu|q
zA?ZtM<9HXMB=l<P(V9O}Qz0Zyp(gsgljV5FM^+OpoOv=lHfX10asMn<bEOTA*(kdk
z9fIec%3rsg#kO$YK?FUJ9RtS1YdW?}dMYQg!|!xo7wEqo9WAG`{4DYW1h*HE+*jjv
zS{?x%Elj<1nAfMqwx4~Tp|goN^yi|<6f`r0I)fb=4S6kaR27^8cGAG81X60Ufb%r^
zX?@|oo~!@r8S<+?4@!1^u`z>$VBGztO;YQ-KQvRh;tqEo`HE=FpZw-z|K$ARw_f)z
zzxdpJ*?$>6HI?^AC!W^<tnkNPumLMbgMAA!o8S6ByqMe~|GxVL6`hE`)mWLSfAAkx
zif?@0t?qfMwxe+FH-QF^G#j&;GgXgwl{H59)!N!%_vEY&B|mrQ3koi0I{Jcm(-j`!
zu(dmTUMFGHx%<Y|z-f)@J=TV)>6Q6DerdUI^sdnlz<W!M%$$ZtC|)FWNw@n~eV%x6
z?5au!uJ-nxgKb#_tKqBA&6?#a|KTN=*~i^a^o|XR&TDZaw&%hqZOnI%b{g}OvGJ7i
zE;sGY>?n5b&8yjCZ%WzunrnX?gvLef?_~R23_Gszb4O}0`N+-eb^r3Vc4$MY;v0@Q
zx0iG{(Qk6IuF<~o#H<87^N#5hF&jr_))hP72C0Nby(jGsQ)o2K&Rq(_3@{0Z%zZP(
z=G^Fxb$c=TU8TZ1#$OO1z?W9b8&A!vOU=gmv%^=M!m%CJD{Eojm7D)J2v+vTT!c3(
zRz2<}n3?VX8EyRPXaaOLg&gO%e%8skf6IO4V&l(m6U6=>dp}9FrshXIK@Jwug#&Bx
z`QLj#b-DY46V&Bnm8bGMP}9}|ga4*~eGoNDb+Qdq^>90yICM}^Aq~h?P9Y%(ibkaS
zOhlrh`2iJ9rV#yrk7VcPBhboo_kHN#1Ig&UhX|OxH!4O`>8Lky@1NY|kt6HV1J;hh
zu`j8EG}y5X{_E|ntf*gn<FZrO={qMAuPN)Zc5W&T`^|H1#XQ$@U1#dHyUjFbQk6pk
z?FrB6zA`+VjGood9O=vba~XK3kKgoFW!?R)M%y~}t=reDMSD;cpK}_YF0U)<gHAy*
zBVpevL;`Bae?ANTd9L>~zk>~1m8+fy5S3l6opZ^&9mRUET?F3IX<{a3WANcxXL43P
zVxODzb}{HWnPGnZc;7}j0mx#kxmzH9us`|ju{Pn*p1S{*uH6kil_0M+Dl!ebYowv~
z$S4#O82<RrIdy;k2S*=r@3o!Fy*rM*sU#umyHo-Wmq(s+O)(>5D(2lbK@Z(DVf@mu
zi2O$O3Au*%fC%*+4&@rq`1m&5oiC2WLz-3i@?8`H9MxOXF~&6_+d;|C>JNnq$AM~3
zJYx(*_r=EOUx9LWjs7W9t=Kq=52C9Bz{?y<75q=H-_o<DeD!k&jnRex!gGgY>V5pZ
znjJXVr|*QCcgNL%!S^x{!l^uJssBP*^$*$UBX)R;?2wLp9_+SL?5f*6mN$9WI=M!A
zun31jzHkT{q6a8FaR{fx1W0;^k+Wz!=|yRl0FDPDC(DAyd9Z>B1+5uVXWg#*$2Q8j
z??&s=TO*v>ldJh1h3{n0BM?#zTxy2xtN(Clv$%g0EPpW<j=5DBy)o_9c)9z!`nkI^
z^<O@Ao#Cu<{txed0mwUCRY?k2SAo)_y-NI0_Z3-D9$le4Ik>Ju{1aHCC6oTqeWc1J
z;4%1V3XV`iNr6VoO}?yN*K?WCJgdRiXxHFk<GYp90;v1xonWZAY-s1|j^cNE)yTbH
zlAGc?KaI{UD6{lmS!>Ly#}2#;0<K+OoFwNER?6s8)y~u+<*mGro{Fy9d>BHo-HLvG
z67)TJ9ZoX&dn{nr@H;qFg6Gu3(L{}mJ{M-@*A>3RfMd%js;GD(Dsz;G5i$1pL%{?t
zqt{-_GIKhx$Zfrx%^M)c_o{<~JOfluJ&k82>3mIn!R}1_d8^@ndC@qz_SB8Vi)*%Z
zvJHUkzrSgMkA|_G#xVoC(y>M{i^4sz(Tq36JOKmFDdmUVv*JKDRKrHkoQO^F=Fyr8
zz8Upt-`hcRPg({8Y$)UGQ`ZNU49FuA9I~y>p%;X?bVw~U28`ksZrvDD%Ze-456{jT
z^_oFX<jzLMv6)DxargB%@6{%2>#F@<r{@VFhcJ!k+5y7H$u5+;u0Hk2Oxnp`mp*zD
zOsc|QtzfNb(a*%}Xn;GT>6k%xV&3N_(#|L#ZFbz2Msr6<We<IACh44-0nlAXf)u>g
zP-nxEg)vZy^!HO`#UF-00GL~foD6S5i#cZf`Nw`dUi%K2^Q#a3cpB!LY}U{xb#VE$
zoI`iM6;wX_=Ha(87yZ+>vIYI!A9Iyw2qtfAhl7K->Y(y>0^I)+`1gm?AN`n%5Sji$
z`282z&Y^UT5z0G%%?N$+ZAR#06B@3)#!n?wMJs@Qi~osnhs%kE5S0R^RqkUU@%49H
z{e#y^nAzJWZJz)70e#>aGHZa%Vk1mruw}2konQ@Zzgn_DBV<!^M%<l*JZ(QM0KvTG
zvv{W+t1^>3W$jdSdPTTan*8eT>Ti1b=?5QJ57%B0#u%2?55CE7Z{Pa+-@vB&{V!Pa
zun9L3FR82P1bgi3!dvQ*sTf~&!irTk7sIiq<ta?dR%0rCTnPsiIPx7gaSWij=^tB{
zu|urOaLFvKNg?J`TPZ8`Umg@CnIv2ONLO64Qj+#<`McYeKQ60kr}U=DK5$00Mxr~A
zT-@?SIxNTY?UjMP;bQF(v5CaDY64sBQR>#d8{KXJE(1`L5@Y)Car+68oAT1oYnc^n
z#_}oZv|K;P(o4}?XCz;>=PWfaD_&j~2ORmFlosa8a7kL5m@9!5wzk{@P#Fwky1jr#
zbYFFN30twSL4cK6Zm+1ig4by6OjhNpOy|17QrmLXfawKR61=9`SMNCm$g(jP3eXQR
zA{(CYYytuMtI!ye?FdQ?^2oEDu@pXgc9OOaofr*%6LJ&8o8gw3)D)9GEndYP)9NA_
z@(45&I3e`xK947SCUstzvkY02xqsrXk<mvf1&V9@{=C_ZnMPPfnu{`(n7GsWnA07{
zPG(eq6HzY*i^oewZ(!W5O*7b>dfQ7N4IxW}@4O(~Grp`<5Hyy%WWTHy5|X7XxwTD&
zl!Z~^9)Uljf=^p@HH@fU28$WQg6dbS&Wcmv0+SDm^i%)+C+b_Wo6tzonuOVA?glT&
z<U%X30y7CRP<De55@rw!C&p+FkvS<XJHU(#JNSWEjoXhL*1V?a=88mI>Q@pY9pM#f
zk$|_s%5y<XOPTwB!z64=P6pS>t)W~z6;*mClQ1_v>P&{vle)+wIF^gYY&eO**ew(7
z(2L^=b}QEVNHpb@aK`TgI(!OJ=NWo9u*%D#wlhr04>P|ey^SRavi2Luq6OJ>S_Q7P
zu_QM7CfgwhhjKPT&j7iW$uBZR5msoN5$SK;|E?ZLNeR&7#*&kS2J_Vj!%c#_37~(W
zhp<|bU7-1S&N{0`>^mkAIN0Mi!)aO4j%t}KyClygmimmB1Isn~NI3b$FjKOvx*vd{
z5}e<$`es#2Dg3v6mR~2w2z>9{iZ~mr_=Vxg1QzGCf;J*Yp|D%I52^p~#?P2J-Lg56
zi4$TfSqT!u!B+%8#TydWHa0k`e`~w_>017e2?gCFV4rDxi_S3^{)VR{*V%sHtsJ)k
zorbz3HbR!4kN%EXP%~@1Nuz1V5hN597n#JWWwv33)l)JvJMP#*IKhAiMu`)9f#z$5
za}l6z$>MVWG(jqx(g@rLy#!@!dWsIWVns2S10Ewbx6(WQE>tLRLQG3FZ^W0^zRKjv
zGN^I#CfloS$fa_A*FtC^7zFWGM<*MST{on7jAcp~_GMB~-|fP-0ObJu7<U%sFuax(
zN}-obMN0uqfoDw9%IdLy$`^I}*<6Qr0)EU{lHnlrZ`p)<!0gHz^g4_~Vw`x9qLjKA
z5qgaCC5^`EpSUX5Woi)NjmIt{n54#UyrEx}WT6-%;j}G737nR*h=iVWX4%)NC8vkD
z9>xwxUnX|OWf+H1213<FEWm=H;c>gRnHa&1T#042rSC@5aT#9B@;(9i#3>mFMEs6^
z*$K0Hcn~xa*pUvpmZx%Az$M-riYZzp6Y~oJ!vR{edeb-=@|J4V7>z(kQh!jtAoVqL
ztGx5zu9u(rwh>GY({FCXpF5)H4paeBgUu_lWGaVpNGv8KGXl2cu14K8><&u9p-F5G
zd@oZk3MErhJ2j}pqXcxNyCvW%CE8NMO$-kGMA`oHpTivvtlVTdriHJybij%kSE8(L
zU<iJ7H^?%vJJdHDm!SU7v`es0uU$f4h6iZ*_Cr@l)9&7SK*TjZ_2qZ-o0q$BBNt7z
z>qTx0n&nu5naYI3MO{=TV{hL%XWMCmRRa3N_U}P<l~J^PBY?9UOYYk@VaC373%sEe
zrDZ<$k?Z*uH4a%p;~VRT_4@&kF27&<s5B;R<E+koLxnv(j`^lf!?Z&rAB<G$-@os%
z-TNtHwZ&C`<s4Ucwi}d>B-hHP`@uA9+s@q}4QH8QP6-Gu^YmAM{dm^03fsxc7{>;y
z5FNlDt-nK?(C+LXMnD4v7g0fW^zLX@O!|4d{tO{3jwlN<UP0H=y*BW?;BPT~*`{oK
z2x-jvlu~?_oJER<W0D_Bq+s=k9-u<Owa(ymeM^e&{rWe5CWJCEx#HP+-fX2waL0`@
zNo~mxGjey_Gr}futkHbIPE!Z;ZF2OUPVUgX&d1M%;pknqd1?q4@usk9yKp0C9!Ls0
z3~DUMqH9wl&0nI*&7@^g80`^JeeD^XRa7FC9-9+&_E}yk(7*qG!rlfruIsw<>~6v|
z?Z^r4eceDe2oQbmd);V21fcgom>(j|?uQ0MJF*2dAdaj!5zz!_XE!?*z&PckW-90=
z7{Rd=36PxFlekQP(!`t1Bm$UBZFXm30<ve6O=dzg?UXXR*$9v)<*8(1ek2p`R%Nrl
z^BRzBC#h*r5DC0~ec!p~<A46=+<Sk%RF9VzR5?r(&)seNBbsyHqjFQ}Zzgk7rK@4*
zp_dn9sdG>8hKW|CpIqJkT;++JDo@nW$<YrU@D@2zc=2l?yGnknmimKCZmOmp@!`zQ
zRj>4^Pn23eQCrN$7irk7wY?tL*o7LqCLHpLOVzatb(;-ofGx^lB8T!E(~jA*BSPGz
zYou5Z8ke0t@08jR7nwqBHnGToImIX7SrGIqx`owl#V3AO6{p@W6F#0))EwBKmn)+G
zI-u`Ti>7(p_W~SW3uUGEvn{}pLQUHIrKvt<5e_6W^PD4W(FIKO;;+&$iOQ8dl<DvO
zAYOj_fvZoP8~wPtDJuiV|I5d#x$UKJqH4Tn79W2p9RG~}(Bg2Tbm;1n{~<+hQ|?C`
zHrXg~qRgaP{Kh}aPwB!pCLDA1)Q44X%j}eXdMSNd7q-h2ztG3x=JKK9$I6(_H8(YH
zD=->x2Kwb^7GDV4o?MF2Tlo57!F%P`Y|UF_m7n3Dan{3zPkhEpj(?ejlRtCrP;Z$N
zx*z+@#IHSCh=1*YD--3HO-JcTtN-rQdrO=*Jo=##h^QYs4}<gM4D909X`=c@SKRyS
z9~;GL#=rcH2Wq3||7dt(sfJq4PSR31HO6Hh{Zxw7^ha?>pK58H)Uj879g1V>tFf;=
zQI5r~`7{f%C!Ad&Q0dQ1Skrn=C$1iX21(=!ypM7OIXaPrQ%3OM%-A!muz`Z13GA^_
zsiU&=Je#fEdu+G0JfX%Hl@Ha#!7o3?4tP_K$H)I9S*-luIVlj0FFpP-_KUleV|?TA
zwLj_CJa2sIbN}QgIV@vp6sBf$amSQ2%*E^Uy&Xx8w&)}H%WLeY$g<q{0OzNpA5ZL$
zus6}VM*m<sL4TRnhq#qza6b(2vx<p_ylY7xNqRyz#?8<EZle4+4V<5NJUOxS@~7HL
zPn7x1xyj3PNKF+h|6=rA<AFc^Wj_@!&!*ywttD8!WJ!+Y{>CI*`F$-D_eS6SrYVJ-
z(eiBUhgEF+Ss7W!0a-8{SeD){#a`xol_!5b=Dos-?`+~_u-B8;EM7fiqUmL3`TK>{
zt7#km+96${8?$uoz*DIQ%CYftDNba0Vl;O3BTyx{d}OvHlu9xE!*P%OA91bTaN7ub
z3ml{h6kBFx@#ji>B*x-Vrc9JZTWYa8vVErTOJ9DF5>xEu7<2_xmbG{x@F$aq`(jNl
zmin?xc^jo&@<CQ)=Ms-iy{9zJ?2WSsn*V;i**`k|C$aJW%FdeT!;}Auip@UmKtG{b
z3ey-xn5Eg4@h?E9{MslcoQ&mOwlNOVx%#m(A1~ve4lPY|%t;zcr)3T24gD+kkQs|L
zHEO&dqp8K1G1j@ugwZ~z@BQUZvmAViBVzvI@%G83ubuxC1EAS*cKBW6fAaXdys!P}
zKZ&suB5koP<BP*`2F{@*EqkdpP7XrsSI<55DUQ-%lutfByI4w~mFx|wMzNb$lYliD
zANnGrbQ86!hsMABO7x$-`sA+(0SJ{V&2wzCD69^IR0lnQ(O(Y9LoJ~HS0CU&CVfwq
z>wD(xiG!n$qW^zzECs=bt&UH@$cz4;Y#IL(KX&FB){G~LQymoHwwL0g&g7Dp?1e9`
zjG6H_{&~4r`QK(+y#D%hkslP#^TXF=y{wG#STCOusnQGKI0H&t{ZG|2n%@CS`Lf|2
zHOQuMNV8(CvP9=BZF`8A=D#e1EYTQRN?-zv^w+N9QJJO@)(wWGC%$^DQ2RRA5sC@?
z{OGxOF&Y1AE=gF8e=3=fg~whii<4WQpb<3PU(eQ90ZBUnjTDP)lN8S_)1PTf^H3Jv
zpO(vC20VhT6U76#WcEO8wVRsX(EjsPBB$x@eHS_iNH(!?7Mnbt7*8XfU?TR<IGHHm
zfL-jnMzT<>CHSk5Nb&UI$I|gw7Ntc)fMCgjuu0q-r!TuN0y(%LZl7IdjOFJPMddSy
z)5W_#l7cac*q-lS{`-%0_&p^hqQ8H>N|Wn}*6Y4~zV!b2D$S<4|MrRGBemzQKK12Y
z>8|^kfAfvqFlrU-kB*l<@mHmz(fQK+#e1x|khr;YSI&?T+9>MJYo1j7k8w}?w9$7R
zy$uQV_r~+zyU9Or-pg<P&U?zGtI6^db+f5+p!0WL<P+y8gYSPmLFncpt}K_zG@sFt
zP%eFy9Dpz0w1BIrEq?FULgIV>{XPF;LAW$PrLUBzv|qjZ&7YP}ZX&C9#=zf7-}A5U
z`$v{f{k|8h2H@ZRYfh!%2@ch;_*MQ->w+5+Fi1AZK*$N}f?MV0s%<&lN$XV4H06N>
zZEJCelyqN>WZ%ZJLHZ$suH6)UD<(deh>%7$1erfW!j`Qi7W?6O*tw@L5?5dOjrSn5
z4|3G%p&HkN(vI;N@>f2S&nu><Z0n(EkAG+4{YsA)+FFWu>4=5EC!^2|H%4}WW=jtD
zkVPbUwxP!cVs5<nc`Z;l9eZl!2b0(dJP)J7pK`|^)mNZzRf6Z^HC~rTyBg<)>eI<X
zwS^MP)XJDomIcPE=0Z)D_7?&jJzP;lCW48{G!|HO3xu-GLqxN>MgPqRQlb_=UTTHV
zU_Y-CiHE!+`Dja93*ho#>${4H5_f2Q0wTzasKm|WXX5#(u-H<T`z{L5mqw{rjp17x
zTi|qH<PkB_asjOqRQ78<B^ulG%Oj=#w{wl!B6$;dM&3ehPQ*G?c6lI<tV@&;ZR;Y<
z?{OK2DW1bAc+58$5j`_3q|<UGFUSJAlp-xzEJa($k*a6q-!uc3v-f^P@j2(>*$EzQ
zyf(o?a8>+8Ssw<;z$bpIl=!{)BERX4tE|oh+`JrH-E2KFpG+T2x6RZZ@^TN9i!_fM
zqoZq88+|=4sRxh7y0ol~GwX{NAdyDDEbB}?Vc<uWJzAk!Kdl$-bUpoY+sxXZ&i<fG
zE79^$bR=(@zsgfFA-(nZ)%bW=i<M|wq>m=Kz{2OYmTUSaHj_n5gOig-1SP1L1xS#1
z));!`7UGOE8_-sIC2mCuvDk$YonUbWBzxV#t32erd6zU#UXma!#A|$HBq#3$>Lrje
zQPL~MwD2NOOpg2JeUgR67vkASxF`+MjVxc5*tW9smFN*y-Ff+A@;_-+LJ~X|x8nij
ze>SENP^{IK5*gh>$Bq|^z0k%d7g)yDQk3Nd^t3LxCH(qBK`cw&8@+gM>1}7Q5YHyM
zcitnvK$P$mV#|9kK8F`g^vrt;&&@xwaaxdgvB6n%p)O0_fG`%~E+5Q;%gu{oSPOhE
z@AjTL`EJR189n^b-tf^Ix^N?b@)K6<p_xS!-8puX;K;Kg%UTu<Cz)B$H4ON>Ukr(d
z<@M%Yd>A0|vaO{Kd96vT(=sxM6%nPW@stJ0zxfP{i6gjTB8%-GOP5Cy#jqsZhP>nv
z7NQToNuL$}D9cYtSou57#>Qi3S4QIK)5!u|N}sooVsaT;O-xNBVeVR*Z))?%fMvG5
z*a-+<4*3{gk+ayMM~QCD`}Us%Ny&#8KE?305RW~!y{AX=i|=|hhr<u{{?dHscU|xg
z{`GHu>brg{PtO@IeBZwrH+jgg$!slpaF&C-eRUS{?CpO<k0a77%9~qT2LI+={2z(6
zk~(n4oNXznOx*^H{IteTJ#MEgGVsEML~DEmZ4y76ZT^^Z_C5qO$s|S&@ey1f-N}fY
zL)a*Hodtw@Z@7E(zsLo&b#lLD%QTcXN{o5&&f;Q`k8b|1HQh_k81H`hLl7Y&haTg6
zk?|!yF-!Lo=TAq!Yuim?49#D*9s<`je_2r$^A5ca$z5MvJj6bTteb(vJNw5E$m1|T
zIw_;SeAhQbk&PD#FvXT)Bv4dcNJCx=zClcTKb3zc<nj0}FQI(?!+*q%d8Q6j@~&Y4
z*Ohq58@m^>yd?h6;xGIhN)L=Kwq#dnQEgtq2*+-Oi!5Va9OMW##<a+dH0nj8M<3HN
zU)l&;VzH6$EHdU+5~LXK=C`t=J7OK%sP6sN7%#@%Ia28N-}}y#@Ha#sD?cPp%u}>_
z2)T7{Mz}54?_IorFl$W1V*Go4EVIo|`H=lv-1({BU^_Iz0zY3b@SX@z-YRn|@fpO9
za*Qo{a8_YC7Hj^zz)dAjy{SIS?cPD4GAg;x>fifm_wzqQDi|v+$<w~Xrb&s|Lc{)6
z$Uq+bmPlECD{IzbMUIlSd}e?6V41l)viLlWh%iCiyDU5Pa40HoW=BHatO35FL*M`I
z*sZ-=M`C8}8^Gvye^nlngdY(_0vqGA%S2OlE@2jUqPIoEPoZOw#5GlHStt=y8M)>1
zeVOgwBpdQmb{e5CnJN*tI6Q>}ny<*q?Ej<r|HZ;0F8l4DHLs9Q{zqS5Is607-z|a%
zo;4=^v}wuI>k;F_b1)=96AOsPNnA50SbH)qqA!;Djl?M8mRVMvHo=c!h4x>(fo91o
zhK^mp6`r`<a%W|K=&c}>7A9c-wTF$%3kmrd5ln8*w_=OFLT_O#TO*w8U;MrQ&+_x1
zJ^nzu9c+8aSZ}O+$$O;SABImao;$Jl@0T7uv6%k7nj%w6pJOM*d9}*Pnd-st<WHJ=
z)l$ZWe^!3|=f>`Rb&<C$KC-kp^66(^UmRIl?o8J>r=pfTVhZi*6nliM+m}Z6K4j)2
zi$C!R@3BYUuwKjCZ#l%aBl0P)n}6sn-aqt~rRDVZeM<bnuy@8jIL6sSyy1<1_5&d6
zJo8_~J;rKMg3ugzj&3=I5<~Q>l845y9|uB;UyXiu7$x&sr)?-S#0mK&98?xuvH!jc
z{ED`5<}SJ;Ge|E#?}_nIU;5npys_o#Eqkoo+d>k%_}t=auP?T~@%mEfM0zp1ndw~d
z*{v>Lo8<JJOSQ0?>^;~Yj{Hja&|?2r7au+G?4yTjfAG$=C-<&BYpQL9y&JQY*2o*-
zqpyF@jdzyW)7)HPd(jiQZTI^xe&Bm=oGxVC=u$Ii+@A~WOVx7!7-RU#%psx!3~#rt
zs4kPSb#<Rp*6$g6*q$-{HkneUVx>e;Yh`bPy*}hrX1lhoZm1i+uex35p5u214Vsr4
zfll-WHkUA-P|osFNj5LE8~~=nIs2O1Th+N0b5e>PUi5qJd7_UqSXfZYUM#ET1NP_^
zomu5l?pWSqlRMa=Vsffn5`Dk(*MG=Zv+;JtJ-c;7C7g=ub=d)XRyXM8IeE{R9-E`z
z&EzV5SE&+mbIy`vhm=pJ{~y)+%<@3*)lEZlpK%+u;oo!Jv%x*r9Lw+6z_y0bgGQrD
zcJ6Zf3fll5w=5ybUv}9sa>7wZ6WrMvkFjS>^A%r^ebMqOmc_-kpP~1Ag@;&*I0L#a
zm0PFE_=7vYcrqGz$BOB^@0$VtR72f%?^)Fuxc*t&aOZ7(i`>e<Inf^W#1fe+9MbbO
zPTxN9g~sRaW&F-Hwu|dF?uObPstg^M1IXEw&XvKmR>Zr=%fi%6_=C1i+t`Zj<DuB#
z5E1T=cGaA!ulaDACr+e$Z`i~w8-6pKx1OG=vgmcn(u9qu8Sv9Len8YBTU*o4j`r1n
zI%50vpsy!XkA9d(wN>jTylA{NURUDJ)M^a(TeW!p%i6imNpQY>|B4OH+Ie%CGQBg;
zU=W@BX)4AGCbMDIY`eZ``sOXlb1^t>dxG|$n*~0G0%s&-nQoo6u6y0-v4ifWrMHx0
z9jn#+F)v>kgSE;f&sR&O67I4k790HWgYt&tVZ*U6?M}*9oeA&QaqgUBvOPzuFl3rZ
z{bbawXvZ_l?Q~CfPOFYNpH54^uQVCtLhY=h_K<^#w+CFT?LuL$*-nI;ueiOtoTJ*#
z>A%OhtYW1ghGU0>rGd}X__nHaudjQjsgBruzEaJfFOOELvwF&w%cBfd)Z*XWWw2?T
zZd03nx7zZ%oh?7Lq6<g2%waojG69<A6&dgN()bc*M7F)Lv_oaQd-*lfb)sY4=jd>i
z+BMtmylMn!v?Df*X)&OE1SQ>XnM5WuRo!KVCoJn7*gDrUqQ|YxnOLY>ch%KBrtKb^
zSoLo4K<CT3^I@)1o^7jmUTGX19!0ue3g08rWwZ07<E)y#Ww%$YyA=*A9~!E%A-&wu
zypj;<E-pToes+6l^Tc9zeci09bu*+Mwrwl6M|G~ScrkIt_TWFqEtbS9nJUGZvCb`X
z#^xph>9jm{w80`PRIHVWK!Fid2XZa+T_5VW?swd`cF-v6(6V>WdJoxr%WU%e*leYW
zt0<NE7K?q-eHR+cWEk6}x>eoxGnZ9E&#8N^#iGM4lk}jRk;N*U<)I6;8lK`#rf_R%
z*U_sk8|`{WUvo{rX)TeBz#2A(itjmW*#Qs}NanU|m+N;n5Q54lAi%kV9g;X<(_oA*
zXw%OhYu%6?qi|_$Jj!T!3I*UB{_JZh9xEGn;wPLs&b-#p6T$GdQ*rvup!iGNZVq+D
zCxEzd32!WI69J!P-9^U+?sr2uyUv7hk%j7Q*m{Fr2+`U7f#yrox?QVcxQ&b9p&zuz
z?XXr(h)am{Lq^(R(A4xbRp?L~!Gv`c?qc+%{ESzcnHdd17dSCg^)LRF47D^(L)2lD
znN!Qke^7V1sX2}#P=(eoj7;V2k;0*UOHF)6fAPd&b6CCKOq*karlIdy+Z!0%$BLV$
z8xt*Tsvuj8rgrqa*)++1+rwdXgL*fp1gX-d@$u;LR1!}jXAn;_W}?NQnPVT9e%q@X
zp?=A`SP7?RD=2N16-VV3QGo7;QGmF<ppq)tdC%Z`jqP_jx7<|4$xYbKKwK`CE7k=Z
zeUA3s=h7!W_bq)tqmHPK>!#i9aSoe7mpK?-vBG{e^FI_eJ8$q_-5R~`(Ove8JssZm
zH|&-?T*zR>dx<|lY27Q=aR>gXjlkU1`a$vXxvBDp^RwrxY_A&{aR=xGwUb!vHy?dp
zq_cBs)AZd{M7bTcrM%OnWj=;D6(n5CXs{c60>>Mr2^KQy&!8CQOZ9cNst)^l$XrxM
zOnwu8+7~X1$Hj?6+IvgwGGunDt?T%(qb{SkL-WRW$1PVxv%$x&%BbtBK0fT!w!If<
zZ_rffI@_%#aABxLr8*i`Bqob1LpeV3<B@V0P*%xoD*9#mU3zSj`HC$JbKhdZyV`UM
zwdc~c=Q5xBjwyVpzO7b$9B+T1)5p<w9Q5#IGohR+j$t1^6tQNqyp(V7UR8Z^-o0+m
zxZUUvN*Ae|$T=pF-paRei(kVQh-zW@^=ieA>hm)*_+TN1(c{>+FQLXY2C4hD{5!^{
zAy^G>IjM`9L)=o_mI8*wh7d0i_^QYkKemI(o!ZKDh<u&PLt#}NL-!|5M#p(L(=@o4
zatL%)%`Hv4%}*LHKM~|7wD^l2ONUr<4i<<!@e@&;xUA>-LcX~Wc}`E42_@BO{4V}h
zGy)a=r|%XOen=Gtl<vIioAl7K?xvTpqKDa{8uv$TVa8#FYOUu4I9z?B)>ztISw1m9
z_FB7ZbniCZlDY7*JLz;*Tmyr#rwTDPFd?2@vk1G2j^q;kfC+R!o<=@2%W2xH`qZjU
zAKlc%Axn8L3<+anxP?)1XbkWXni~mWolIQcWwjc#tIlcDuX<GOo^^Zd@PsQ5@8TbD
zI<idi9J_ZtyUA1)PVlWStXfkT1RM<F?dZ(f(?YVPco&I;?rW$moZxFNF|o(C2W$Yp
zBEyuh`c70>xGpMNq7#*X*)KXUp6>}Uvuf^q9%Czs!<FIQIr|-+j#Wf5N$kSMv2AC}
z@NIyNNo^CrxT|S~#bT)zPP3Bj=)B!@%{7#nHd8L}s4j7fSdsP+-y~zH1aC)oy8}S;
zS$oeI<x+tP_wa9lOQQkx0}gWyoWoS){mbR)T)EsbDz1vi`qU4K#L1ny40|&t-_+Qh
z)#iARtLiguZcgTq50|J7H}hTYDl@s%w|+wKGyRJ1N1cKR-EM~hJO^BZj98|VS8FW+
ztVb37+@#Z^^YeDnA#3kt>a_#}xvc50u5*aks?*`_xb9nK)#TC5>Uec_4AY-&lc}F7
zlZwXf{Kv0GQ=bNocg_*v-CBImDyAKEI&236pgw3%qi^5mte#U}%ygOOSJu^AxBxm0
z9sPceR5=M0Z`ZwHqR3nJ0t4dU{AH72hw6sEVE~ivw%>3<&ODRI7!A7Vu;k!G_7RdO
zrZ#kyKr?T@$t9!MKmWCA=>e4_`OY6dD9T;JTb;7I&Mu<fa*{p4ahz7W&bceDi?TB8
zrctHeSW<5+O?<w6<+%)dQ1!j#tPpkd2Ut|24;&`<a5Vw~Gc~oM#tGs!qs0a2RMq-^
zZ^ML%{JJX+2{AYGqR0pIVOf1{0;Q;0gdF~q_w|{|%;-T5k3=(?D3ORT1*8SVkWYi8
zw-qSKcTaBul!jkKrTSeqXD-SJSdcFs>xm_R!s~>Dj?J{QQx^#nE?rcsFLB0&XXNx+
z!pHu2fyp|xtpb8L2xho4<c6<V6&V;|R}=>;O<xPph*Rzy-fDyYw(QZ0Wl<gB>k`3W
z_8|T>QVR(NZ(M4MR|e{5=KN*<xaoILlHqk@L%Jt0Gpvl^)*_%tzVrEKE1&5~f1!5e
z3dv_W-D7*Pr5-x~Kw}VZCpgJYSq{U&jG+lw#Bmt!;)8FxxKuE>IE1$ySM9nw(a)*q
zz>F0uSxwm+J%5R-usB?+_|`XnyCsq=Ny3T()U29Lv!myn+e7o@e8)I5lM`}zhXnma
zUd3~-r#Zd5GoJ3&+iF|Ah0f+jCWcbC18`050NN<_xu*ydirgld%zzAYubEB&@97or
z0uRRXgA`F+F(1LS7QH&rafMa+G>-IYFzm;}nOyQ9+kI6S>9_y{1Uvgl5p29|o4j{~
zF0JF{G+5TSN!x`aK=tG;Aw6i3SZ^)GpUeD8<?{pS&jv?0X+mW#>xS!dI>zMC@T58u
zjRNc|GaMUN0*?kzS%A0>uWY&Ek-dl9R-!_r1Pg)*;(aK=b)QUuKY@hWYIzpTGt;@Y
zsgOurD&ZTDY<J;3u?3dwCI^(Ws@r_?u=s9HgKz<$>qajd7Xu@FH|4qqVU|zSJ{x>i
zo!U{?-3N`kW9IdwpQ_*z^XuRbL@V7Ik(tE+;Yr6P#GB~@Z{jQ6Uafpd7f`KtB+Ibb
z!|jw=*S>a3VOXt>+mDB{=kx4gHd`UzjRJ!V`T4FNLbf`oZRUnwpLT$_TWZh`ZyVdt
zmB2=zIhS~)QjpBCcEwEBt~CE_*H(H9Nlwy?dw@i?6pO5UUk`|5SxcBDdAEsUx!Zip
zlMfRRxq|-~Ym-M<B^(K)S>Wyc`EouPPL0hb+s4|!hNIHJ4r%vuKS<oEu?M-`CXZVO
z$qoAVEGg(<5Kh~^Dv1)2u?e-<hz+du#S`qz#ELog*WU=L&JlBJSMTb1d)L}di!k5j
zVUmSR0);K8TnH7B;`dUr!w;ZTO_4_fod$Z4#mLC<ta;{Sv~p?Mi$WSu5J7(XLsC8L
ztj(L+oWE}F`hYi`TQv{chjCX7eGS_e3&5zvUq$51cVr>m-L&c$O84DPUmxn6cDSbC
zd4;1JHc`N^_5opxg!XA8kZ{f{+oTz;m<MsfQJY;;J0zzO2&+%@)mC-iYx?N69SK8B
zw8vWd>_n`(t*ufPyNUwB|M3T61TQGCMQPLTUDM-gkc_F~9J5Cy^+@FQVnGD3o~S*u
z(v|+KJ{)w4Ca8wrFcn|IotGyRh+*?8Zkj@&Pl7?W-f*jSIJ{wYgLyk=uk&2Es=eep
zmX5-}ZF{8_?`znwVJqdqYG6mF!tylwNu8AWXZBzHNJ4C?bHi*Yotakob(J{lhZUD2
zy4!7+@evUgLer=aNP6)Zrk~}%pI^`1E%bh7{ls;3SasZWSjgx|5-wr66Vu&8JK_Um
zq-eXUYTpcVU^S3z15T@mCjh)g`4^%UM{po5k@mWejhbnL$Fk!8Lw03qo2o{mMG@Zo
zU*n<(amXVFT<AQl<}Cz6XH_59yhZgU&@LIXfWkuQ(*)Y>rMv0O7yVzVJ?H<j>UQob
z7!elXwi!<OA-S!u0CwMw21SO*R~`_?dCWGoZC2a|amX(+@;sP)Kf@KIO^S=}65hbq
z?0L3k3Oy1uJ~&T?0xeUXB@e^TmYNFjvx^*U7oo9*8=U^?EGzQ(lMRCkok7=nSAh3K
z8x-S}@6OD()7xJd*`}6q>V_Ip$BjE}I)EzoUCz>V=FtJ9*z~5cSZab}&Q0`X=k0{w
z<@TGifmr5?CKcu9dk#d9g4^UrJ1hYh31US(eEVR<&Q?5<v9L(OKu8m8^FN+p;4n(<
zN_F|1+W@IWegm&CM7oe_DCF)(z9+K52#rTzp>sQ3T26mJK~Iu5@FB^z%N9?u<=RXj
zA+1SpMK!Sifo~YW;Ze$vi`WGW673_ZN7+R--ZVjgq<G(e#q<;Qmfa$jPK`~|4LaLa
zCV@n?Q5;m|k0OCz-~<>T1F`C^v8N}3+_X+j1fUb~sFFX77X<sZ?&oBp-1mCZzwGcS
zj;~C+Ur0?10Zo#yp1k%Fog}VelPDrzAPBbsPaV#=FS<v=3A6-5Fk-X&$$C>=G$GEN
z5LxFA&cHOHsF!Am7zi5pfTUmAL%*Dqaak?<?W#)+1KCdpcDOcgh0NGCfoMqrJz11g
zo#V3bb6BNXKKV<|7jEF^I#%7|#vW%rZAy*Q;b<fSX~qTdB3U8VqB3NUO*svJ3rr-T
z`aucb!VC)7K-kSOpFrroWl{I8De+K*=f}c%d&!QDwdAJqISr;16$eVJjiDy|DRjpB
zHqC%4uuo)#6lR4mT7xa1DUv?Wr5aFDta3ZOdD8yMYpP>eIYW4l+&#ypZY$>0X_yGs
z?g5EdX2nRB0S%doLyi?luC^V1kWv6#u8h2he0HtwuBzbF1jB`00C0y}-iK}O{7e}s
zlY|0!h<Uh?Pu^$-<|F0>)zMJb&Eeo-5=?hu=wa)pmfbG%v?brtPxgs7CNT4wRvhG~
zS~ra{$y6gq^w?v`7{{vN%=dJHexs^Jm?Wn<w`q>`n`G~<UO|5uqy)TXR9<EEOW~R*
zpWd}Hu3z+K&wF@@<iQ+nSu{b&vA_K~F!`oR-cqOnCylCkdqZuxK=cOMmgwfK0$sFz
z?{^V-;x5$o7w&V&IF#}FP*t7v?`Z?Cu<ca*{5IJeG*UB~#4xx7Yl2s-Iaa)H&47D)
z%Rq$lI8emVH3HLtJK%KPMj9wK%x@zdz;DgAL5?OXd6-?$jsTulFFzphgf5{Veb@z^
zK_X8M!P|6MFGK!>1C899^j>@mW?!kojlxAILqJasLe_Vi2_JIDO~Ho~bv#j5GV9c`
zQ12?H#+`19K6e2s@pKbZIwRN{sjI;s<B-KKckH-3c83LMt@HM)-e{s}X6&HJ+BITI
zi<p}Gza!oS2_)~|RL-P&*yJv&8>Zq?2DxqOkp*L9Qgv;{J?u<9XWG@5V9)L<b!wXR
z^E--jBYSj@%{y^1Fyz)m>LS~UP|x`tQU%muhkVTAx*ctqII&<JjLB<SSpaq8oLW_b
z5t*l4kdmc$)ytDzPT5g7k_fMf>OQs6ghDooA=D)1f{Jdt?B0g0*E%khg9NHhoqR81
zi+^~AD(W*=o>R{&0@jY&v2QuscFx~&Np{XyCvZJ#I(y<ys>2rEG!dh6VpEer7aBV0
z6A|;#1By(VbhPfUrf$fI`UB7qV7lMl^lbk8CA66;8$qy4_X=PmcJ`dqw!4hV+*d}R
z@O_8fqOmgQ&p{pFsq)kp@M%$+(S}p2wf%8sUZvT*?^NB{g)BKe&(yRNDtQacUxXZl
z&jAf77&1EymJbNhE_#{FVEGBbL+^}K%8@4)CWH~1X99Y{@<pOEqvTeSx`}3p)&2VK
z;Yg%<LY1mraim<v*Qb5uopDnRiGxCykVjbQqobn+&U`v8dum(-Vmz<s3*R~6zv-0j
zS~TLMfq6Kt2W>S-w&Nvme=_B0b0JCeSp)osld$JTM%)W6Bk_noTokzp+GI{x%<t&3
zUf7~IWN9_@%&0E6%oK&_m%*O;gxn9)h$&1YH*fU{GV)R^%tHx83*=QKYjoyK35<W1
zM<;Oc<=!w{zU|Uqzyn3s#R|#8q!ct-8^f8`up=W0C<G7{zivuJTSTMN!O=Nf8Va2Y
z%ayU|*(tIgk9>Gk)K&bzSAI_>T+p<ztaR};e0{(lu*U;OUlew6Z~o{3>m(x%jRq5{
ze0_^u23@ZhaT?9RcZRiwlB#JJZZ)SW`g8>#>1+yThF{&2DIbPS5qDt_tS*mDT^cWo
zxic65x#T%_{=A=y*uu%eO%zc9r{7hb)nEXw65$f{_ONrIbz6nXkcErt`zI^#v2*;B
z9B99<f;+TphpJs7KW}flYxpAwdgd8U651q+M|>DUOL(p(Q1mjzgOIVKZ6P}dmq1q_
z6owVmYq~xs10$s`#xq-NPgj@J@IhvA9q%lmqe=SFEF&?H!LP$uRqbh}kD|kEM1wwZ
z(Z1(-6FAncf%LoDvcp3*oX}CQ45Elb(1?b%fOzGpy`vJE%xHN2(hRgFa1};diUxo9
zZI(Flp*A!th9r*4sLI_iEV`gZ*@W2pP>5lpVOC29K4iRWI0Bo(1jVMK54&k@V*5mK
z8>+W#MGfMz@)z|0b0$yNyoj^JS#Icxq^Z<Bh>A>w`7r<zz)o_3(H1Ge#bW=yGg~u4
zwztJWq}}>0)I%UF*s5(e&{rzzA-4$JXx{azN`I#iu@HUpPSrhZ9OV#)Ucflsan{g*
zdEu;}E_*DswOm8%7im>^6>|}rd|NrP+;q^z&w}E-+-`NltJp`Xgl}LRc`H*Z`j7Y)
z?)~szN&gwOClnl-{gx&2-nP1-s{uQkusBQ>l`TFiFl(_U-!d<nbUF_~kP9buu3-ZF
zqZg4s`&k_^g<3hZ<+z)I9Oe|y%g~B)<K_S<48=NXwYnvpx&!A04BfR2yW-8va7j2@
z4ntO(Mrr?@`_C;PL=j`V1EX>nyw<Kdz&N_yNLjmeQuRhN$i1UE98Z64BK@2wVDkM{
z|3P!ycq->?nqi(~-wGA`<@x3z01uyP&0t_dd=G}R?}}K)wop&F1_<OqrOvbWR9gjF
zN+Z3tWDCkCGyFCBYhnxY@McuS;{zC1I1#a2hUkwap+We9kdfhlWDPZLo<MlF7k)bM
z5A(fZ^7j=D92GUZVL{F7sFiq~rhi4RCnyeL!yw@eLsD*s=ZVifB+-SV+?FiQV7(?D
z(*U(TOHt12F+B`~$U(9;!$B`3O6RNGaJEvF3{MCZtmd&VCz?qL<n<g6;BKl981^T-
zXQ|QUO6v^9-Zy554*^Qob5t%OE;P0f7<RKElPJ*ZLbu8wJtQ`N7gPrI&&A{W{)x2o
za0GzFA!fqKp>{Zsp@yvl&2+u#uL&G9&~e8se<-ts+>s&A^i{k^EG!_fjn2EKx}vQA
z=N~qeHLoB+21sf0)ApE20Z&oFvq0FB7GFzhD*bizBg7X-PBgSBr9=&Ad`p+Au>Yo_
zdpN=o`$8~yrKSlc*(7Jnq$FE9N#Vgzj34Tpx6=ek@!*I8mqf9c?d&+<ir&e-U4kQ_
zCy_t+n4R~|hox2>B3u#ho!|d$0I3A%Z8h!KzUwG1EcCS7>u&1`EM(AGfm>yw&plCJ
zj76MyOcnAxS27z=GkOc%ta4axNsUBf+*96SsT8L*qMh^>a80JMZR!<ENe9!47Lo1U
z>YB|axKFOGxep&RI)wwsCF#KMye5i}po2(%=A)=(a$M!*xjB)Sn#(X;`%Vy!T;cr*
zDttV4>_Tm^cGbrS^LGn=xAsw&-naCea!a=%e@;{QlX&uWit&QsaFm$KdA`=~vm~Wh
z5f?OrL^d9~W;!^kp<~TGTB@41Izp5aLO?mQ=k2r+2in?#g+2Av_kw+6=>l#K6viHD
z729t6=FP;=8R-yVW)dDb&mwL8tUz6i_3hRrI}cYawVk6C(^-KjPX%Te)B+sCTI6*>
z=cjd11u$|OR%-3JIF)zqC59Ji1KsB^P8M)tS_4~#)*LGtjwU5#mn>KU^_AbI%`n!f
zi2FM_ENv>khkge)cMpwf_|$(apXr%b*q8`tj*tDIuz^INOoD3mpl$>k2&RX9l%uC;
zjx0uu>M{!nPS^|;F_R3^(5u1JMkq15i2V`;n9N(cF3ZU55|ycgUhZJAMc_A5`}P@H
ztZ^NOQIkx-39`)Nrs?tf;q`Yk^DEB@DnVsrL09pKH1?c-gV0VHK;<^w9DWSShWLoQ
zp~3h3=E9b=Ep3@X3S8oXG$%lD?ZT1ZN#7Y^Hes_hvI*XntA^!|SE)VBhGSuZ$cPIP
zF!AcSgS4l<Nkm)=B&9!9_ib)okHkH%I{+w{SW(<LeV?=|cQ({Yn$+Jqrea}cwhhJV
zNd;=-38Z2z`pL`Un_8ERmzqZdfMQO84n{0;&%D_p06zoZ)HiKxAYXnoJnzj;<xA37
z8~MaH|MCI6OR_Ug0zgGXfm9o?Q>iU?z#U!{fuL-;%9<zIR=ddt0_kM?3ZTAQ--qS5
z`5N>Rw9OfJLBtz{yJ%p@tw4h?al9wMccZm5&Gp#Gu3|Cto8@z9P=@Epf3!<|uu>&r
zATpG;ML1CWN%;-bjX#I&L+Wr~)8-iUsv#iXrkh^|&&hPY624dZ!x<PL<}e=M780XU
zPoNn(u7~H0nuuK9+gPR*tPMaMH@Vl)M4<(#w$g_{B$R4&G<wh>+7u=(SUW;s9&Pca
zXJQa3h%I*Kxp`?k&REU)%P4Ij_o92;?YF}Tw+=yqym-kxX5+O&pVcfs<>+z}^oAAX
zXX_Mktul+zN43VIT1<gVsv4vSdoKF-g3058qRIyGQ?`A$CgeDk?xVPqgZ~rFFPEla
zVsmVFBibK(^V@9coTY-z`Og6jU{yDkzwK*X+JZU~hhK!zlZ_@ojUfdYQ?EBn*chT%
zMfSFh{tXL##su=<yujjJQLq^>nQ+26SqX3~Lsh~;jIf^A(>@9qbZ*23CGrE!O0$=$
zH0aGrsijIpC`Bsv8#lNgA6pNnb$;2z=m%;Kj?M%2mYbTq4~~hR8S(xT%HwGE;0$7W
zkjR)o3{t-|&4CpZ@nKr?fl?8@Oorx~TVfU9-saem)iul6P6@zbB98{Q^po9>Um_BO
zi3qDouyWsrV!f$q1okZ>xI7n*+&1Bg@%s`k_Jb}IScrS>5a(3fR7XyBCI(cWtCwjw
zpfBZ&_1e)jCNkXDnQ=w3C)r0vPq?@I0AeSPS_SQTSb_k;jg*T5AZ-@-_r3#=x`0Vg
z;Fk4fO1ZJ~GqY1sZB2|bY7^-Cmpt?f<`(7JZlIEHPU3|Ood>QRe$DpP^_-1j^qz2t
zK*=O^9*&78Q)##wDmwYF$WCBrB)=GY_mSl$-Ed??c<2kZkS9uscia~ri*3Bty0*Bu
z4|}uaDRPfXqcj7=7*o^PrV?59Md5LU{3(G;g50V(BQ*S$@iOynfCKf$`yv~N=~Q8(
zuu}MdA$$k6AJQur!mrRRRG=s+Jz-)lyjtToVeix&Z%?Va(qKU-V15Oy;1r?<;B(mu
zFAGTRGj!|~!-IK12vor(`hG$@t-P4sZ$HY40M<o<I8~t=Ui${@_06I7AbISplw=tS
zEvGSK7FlKm)@RvWJV{B6+_OigF54R}KqM=E6vN>K1S!F?%$aGe^4rdq0n7}KBuFZm
z{<kX>3x)s+sO4u5inAk4x+H0Me!7&4*h48f;Ma!#4Nmta1^5W1U52c7NuD<>DS`CG
zQ1nLWJ#)3PCSmm1I6dVYmY%@vcKPiVLfF!SE$+0hPVW?w*~jq85hW3(AaCdc8$@U3
z%%nr)Xvfx2gGgD$sm3|Qt*}s)PD%@`raK(3L}%?RdT>yxBEk*bx&0AwKg!uw(oK3t
znS51s-gOB1T@)eD5?9a2XA7ikYESE-)I{yGmTIj%Zf!20PkaNig&dVQ5k-hSw?{e$
z(?V@uB~4Fox*Bu`yMeWg7ZC`g!sbQryt0Wt7#3iI<eqF~NpnY;9i1elBO#6|<)>K%
zLqV%shuexKV<aFw0zHbd-n_jSfCPAaQ6nmgH5LdQ!ly20xLBG&=Iv#zC#ff?hPELh
z*$YxaNr)3vt=p(%Zqj-ud5Q>D8Id_7i$?>br{fkjM~v&wONHqYI3r4oqri_&won^u
z>Z9tQjAHV&(zY9}I9@m83l0F%09G-AM8*@9JhTu;B{P~7HBGz2G4RO%Ww(hT(OZ!t
zxGwtWWD@M&Nn+Qo0Rg*KUp6#{4&N|!W}1uSD#<ot*)<(y%v_Sl&0AVeJlG*5I2#@$
z)xhI0-T&?^dbzNQ_@M3vRA*feS(>SHBlN239UJoE-S1@+$4#)^k~k#+9aKV|wiW+4
zxTuScs10|Q<d9Kf*n6T(;$vw_Uf~TIo~Rv_Lw|GejCjxHOh;>wVd<gL>lMrjfqvNg
zc=eGm7t+uJtqp<IA`N|azVbiwJj{$_F0}2_f~QIq<IcI*^~r{dEDin#72>ie3cp$i
zOsy|u@13eWLu0$`1>yO?+-6q>m&L53mnF#~rRXwe+|GucXO}W{KzJ;ik6Z$3NnEox
z*@p&NhTE4v$q=d9(sMRT^&$eIqm1vVG4=+_mP$zGEnT-S`X{yBw0R7hdsek%$2_yF
zb^^cGUQ+gp#>NW3&NY*RfYJGphT6bEqOKxt`QTzH-WqWrZZ$Z=@Vc#@b1z#Ge6Ao=
zMHex?dct}x8Hoo~MK5HYTH&Rf9%}<3Gt<IK{@F*sUg?{@?gN3g>n;$b3v7QY5bmSP
z42dpUnG-Ju4sGh8kErW<-P9G~k)T}2FT1XuFqq^!I5`>BR)p<6n($LABEuDm0g<Lg
zu7P#CHG*x7UeA6_fW^=r36EB0W{7-=h&GimLQj6}eG7(&3w@D~_ZbGarca|RNiToh
z-f_8Mn21b7R$SGA(p8=8tW|-RZeHX&sOiPBtvo_g0}!A1nmK79V7-gvPhfZ{RY)~~
z)(V2SNKE9+4eN1xO%Jdl03*X7A<FY?MRb0~l)R!42@#}u>LUj+eTb>rJs9p4^8v`)
z%XY$P<1?W58U+7gycpVVt|o9eu~@B(*2YXFU3k^E62WmOF6awOlNyyMMD+QLlo7@t
z^ywe1xXy-4*Pc=w>K8%ANRWJTf$d^x0k7Dn0S_Uyn>@wUnbJ&ol>VV&i}X1#*GBBV
zl|;?%>M9nRpjC6;mLzb+qp-D)m|()}b10!Lj@&ga&ZA+3v4D3$)Ofn)(Aam4fKPa~
z;hcddIUCHo7l|}9(3;jnbNtLMIWThDLQirHTctT*4E?)Ar?xa@u_CTSTg#b)690Tb
zd+v%)KU&3}RzucFw8MbAk^V+*a4AlHOPoyov{~hox`h7QHgVSIkaq&La3KkCGR*->
z!y^?3I&mlLFg3F-m)%e(oJzH!i4AdXSFEjHZ$=nTlD*ueaD)teimCRRS#C7LpZwN)
z7r<x&MyVMh43O(!u<52C3r5JO=(~xTmnA1+uZHvsroEmykjGmSol^lz1lUaGAqE%W
z!=`oO0R<ddFof@VN26@b=SeV`JP(1w%2VL07wBOj@er_|CGIVTWg#$TW~C8R{4@gm
z!z*#FO{TD?Yu3SIuGk(QstIWAB$x~!`g<kLEyk{tmMY-vZrHSboy@r-AVQy`AaP(q
zT{H!ksgnluB_wE$3+fsgzNm+9D=y$hdoD<_kZUl5Z2V}L-Q0@z6ZGGYMs;T421~?`
z*tcs3`M!XB`T|t|gbX=(y-8u{*nk<fxC>xH^Ep|pU$~N>nPV9o0g`l*{iN1fq3@CR
z*~9Whkbb^Io@I5ZGSm}vxjpa}scp;HFs|mr$AB_~cfmGq5<9}OA^D!pO<fv={)@@b
z5ZT{-=zwh3bpk=agia!O+k4lN(1Q(VTjSlleS8h4vba!-vwMQHnqb;p{+kTEU(<mO
z??+p5eom|c#-#b-^v{WE$``5|PLQ@d$o%7@NhuBs<VrNtIEliRbUZ;>DTmq8#Q9qu
z-Jcq`0N%kv%TSryUwAhjdO;Zh3Wo!Qj^;<E;dO@cIMkteC}j<QPY@=4+*Gg1RTdeo
zyM*AuV8!&1RrkA$M@+X_XcKIm(I%nHF|Xe+yWPQ-n`yWSW<ye|NDUYrC!iY~N*yrb
z;eq;X`C?+GObOY{h~sM(Xa9#~nd4oj+49P|JO_N2TQ=>^!}cV(IfP_jX*+L*uBX$r
zU7dJFA9mr|p*eM-?KV6~9vwMr0k1;yL?2JNIrgf7lS%Z8x}1g#<ayCji87#2&7T6t
zgVka8Te-&Tseag-?g<Scm{88P+7a--vns<&I(Xv4IFxP$Z-!a=XMrSV1H^utL^R=n
zIhuf#4c@r)i^jR9nD7A_7vEpnaJK+iByOZPtrAX~@=4kx+$X#j#2=pUMS3tDP6EY$
zBj@JbAT<JAut#hgPPs4u%$ee>+F2H@fd>-?|0m6;%<`Z9&HF?hVWRo;3%YZfMRvD9
z>lax-*KqC`7g7|`K;TjCy%LBy3x26~!-StFh;{jyz<q)Jw8-xWyD765YxXoUi$^Jy
zq#?zIla$i(On@u_i%C%AQN+jKITjLcS{u?}VzK9Z`6X!;7@f+`9-M)SB!I{;pZdG^
zQi_nK0SgOuWmm)CP3ZhxYrNx@2K^j?31LDIF+~1|FiE$-7Ka1rwZI*++~6buBkJTr
zP;W<NLLI-?`8d#Pl2uAC;vSFAyF@=RWU!B@MK&I@SweDOqCY6`ZrZ)RUJhGk#;dfT
z(%v0`E)i$)09UglYtCSfA25FM0>(EyXD;enE*d0L)I>?y8V+FD!3mpOH8_@QU{N4E
zCA0<~+tfu#ZDC)@ll|gIs3xSHMTfi+s6tjs5BMBg-?j>CS;Ol91X+wW4wIWN9z+wP
zdiD5oj49d1tt8RucB*=)8gy(~<_o$=7~&{E>_NQvL%oM>aM)VsB21r~r>%%qR6H;;
zgZbfBvDhuehN$?jl45e>0&CO(be~uBYn@HNF5{tHMJBmri<iO=RxXui$I3}^V=1IJ
z>*#|&kB8xAYTa0}C7s%_^L9(Ibkh|QyfFl(mwA#u39ktQ@gSB!Jb_{OM}cEK0Db=V
zDxR3v9!4n2nm!WnaRY~olhRJ2Rh(5cnYh)3cy`S)nI^wta~pgpp5VhCecE)jwN1g%
zO9CG$UiaVrzyd@wJTq+?+%vyJooQ%T;j()IRw;wzF}d7(bNFi%dU0V>y@WDBZV9U$
zq$d5-ppPJTfcPJVjAT#BsuT?{#+pM4)(&_B$}?JhBo{D53Nx0{ZeR_0F%Jm;^vUYH
z#~CYzB*aFME=uD6^mpEk&{LEL$czgY6o8L%48SQDaZ>HVZSn?T8F<w$u=LmD)$jNk
zWdJ%4b=l-GT($eE!GHvz$YsJ{)3X-2e$J~EZm5BtWWr^j4@3!IF;YNuumBO#Y60Xf
zuBKc*swpB)d9%9Ax`!qQa>tn#18UpE(4>1hPDZSqZNK6kLr@zeoeXbJdurKuYe6xz
z^al(jp~TbHSEngq46R5a?;=6|M8;99QBmgLcQO_ME#0K-ues9fj2(d%<r;C-3yFX&
zk#I7C1FO5?7Rd;kPqnp>u}c#mM*Hm)dl;q{cKF!KhUITZq*OqQ#2EmC0n2X>>1857
z6r}2ltk)wlvpu!S_=Yw#HHoC!;geWqIy~vPbs8oDiDu*nktE5B>ts@<PW1~-2<cqf
z4FsAKE{VyJaz|6XP^%}d1u@H_Czx`m=$qbX#WS;9RFZ`RrO}pH?3rK9;s^B+T5;Ec
zAWdNgP!4xJfRD>xSpmgF*@B_=@$+oPx>VCg(pRK6^hmnnzEDt?S#9k1ZAfz3w@EHY
z2g-0m))CyYK@)ud6{3OTn`Ny#7M{9Gosm#8$?=uac}Jo`;1U(!Z1iRepv0TLNt;Gv
z*`xJQ{a0SThnm;<u@Y?qvbww2f~Y_F=kG!jS`|$nJ|&OTx_ddG2<!N=xEd{lN(D|K
z>Za`2)1h!hNV`6}Y99>T%eqPuc(Muts$*6l2Eo7bA_p>IDSpA`!;7F>?$&P#UCrm&
zlQ36x*y}dCW+(%6Sc?ZJe-Le<yC+ErN0#YCko%7Lea0A*J{RrWR=YIfcD$yKV_#I&
z2VB6{9HtPJa8_TDy=*j#{106zeJ9g9z;W^&x7C_^IOw?U98rTqEQUw44-48(6r*_3
zl&x4lsB=f->u^7s#~~4ft#afdFd3H#)X3J>G$*C@vEW*F+z%w}&;41r8wOskW%m3S
z{VNe#L$uw0Or9W^SGr9pu@NV6y}cV`c?0zL0wQJ5A*Pm-EmG2yP`Z3!Y@|_Ks4=l$
zfl&Pz8gnc*w2wGQ%%T?U4SGtXx4`RnX<3lMlZ-ZUx)RLYdfiH4HqncK*giF|`M<K>
zY)CMlD$j->4$1$;<Q`jvS)y?f@IZN;ZeODS)ax!wC=pj)SSh)+@m|K<uAVD2)ohu`
zXKr`&hM81DwABO+16$xeO#Ei?z7h8zZ)<8qLAGjG!{ZQv*`xzWG~5czt7LE32s#|$
zxn^@61$lddRe@J1hNUTAdPl36-}ES5Lb>yvk(LeGaRe8CX*iC16u2aVap*Jfk9Aon
zrPQPY=VUfqi8RQ%shG8tLD9O*n@(5>Ue%gS6x`!dLy4e!^O~Dd+T$cidU9<3HoGje
zvm3$jK(SZ`ZYWIbp#kRB_SF-He0JB=cagEXW<MELW?B!964?Z|3$>E|pxA@BFzg9&
z)py-+2Y1ttdNH?1YD01x!qy(1Eq?U#S2PVUZ9Dp&@(0}^-El7<t-ePuG)f8S*%ViE
zqPaQaC5Ft=XADgv0NxMm0R7sG2&iwwFW}Cln~qFPpJJsQYhWOfX6$2CJqC}TkZT0V
z<9sb!s{ufV{3Q9%byt~_llpjYtdDMh3EBX}8Y*>Ys^aIlZt?1}AEZ8-E~K3U`Nq&?
z!x+1e?itJSZLpe%y(!ai1$Bs5kVZD@3&1Gn7*zp!ge|Uluj-ZNoChX83)|9fUkJQ>
z0_Jo?|CGgLl?k(91V2kM&W}75;biha*n$BT9wr9$wqFhCAEAeSfHaHQA%J>Da0)_V
z;Vjl%-=)^jV@b1Dj5oAvL8OE+DK_i_^;@d0mx2AjY*O&tyjyW`HKbw^j+@US#qb4Y
z8`&1HU`mu@q?R*Y*^{8qY$}O8^)J~bizVk>lJKIAnIY9}FX}Gq#OeHKICYpF(aaBh
zNR}8sTZ`+qb9AeA*QV=i-CU<#zG2_86Q*MgcU4HOqsa3XwGusz42n_ZdHiJO3bUfl
zxXIk@fI?%024p_dY0v<D_olDTqMtYiVy){sPv5&@%a2&9y^tHz)6&Dth^2}j`{YwU
zl+MN%c*lxiw-1(8s3D)ATVS>IoV#i}u_fHllXaHtG5w?-=_RvS_)H@67QK<Tg6%-W
z+U3%fz|00s5YZGFw5lY{tk~H`D_PEZtlzzbn>kuVp9DovAOU0%a?wAIhweoIWaVG(
z>*Y#FDpw|L_i|%0QX;R=ScO0RNjZMCxU2$Me6KnIDX!aa6*b^F7Eb`aByc5ihrUZ!
zJMNjn^BNA@A0UslX?8Gyt-{H&%tv8EOh{9>1hC`+6$%5BY%BU$YLYz;&IUFy6j15h
zbFz}U(`${7tu+W-4eL|%wRL(KD|s{lShnY4@lxIcT-+H|#$GjX^0Yp+N;(d>ZlG|N
zEp$rmLzJ*!81NRjNMZEx77*s#8OOSX_nbGk{S^wgR#**@S@i1Eu%Ydmv|0O*L%BIS
zZ5>Ryh;}u_%I<r0YwL*~%h5cbY);n<=ko;G^7)yPp&Z+c1oUrxHX&U|;)8u)l(XZ|
zzdrBG2lIMfGGu0}PC&pK!jM4lWVAH?iKQ#XPhXKgnO|}~=bs4Z?82%V&Wd|f>}WSw
zV=Bd5XwQ!ZT?B69vyugRPD08T{bq>9$cK0?F*GqnW+HlJjeA`-^AV~OOdHlWAV+eE
zQJziGQW8>0?-%a<r(bPuxl-Fy8JLA_^`c7my+)I>LsFW*Zc~k+s_sL5$w^;%;>*ni
zvR7Gi_KBMO`Ht#6QW)s%tm7bV+q>2|L&6;{+hgrPeqDeVIG0&(N?ck}*dVDMhCIbQ
z9ybD{ATXJZy>WL?MOzDcS6LxU8O>UAC-2SD%r#5ZF9&1Sf)^_>?*II6V`S2F%yc`l
z>je!U%6V}p-!MSD;roWzbjBsD&0C^_xf-TfHUF7f&6EzEurFnBU#uCu2$BYT^;ppi
zSR{NIqHgMjcs*ddl&k2-o1{63g#*1-uo_;UYarj_u@l$q0?z|J8Rs?ydf0y}PnQo2
z%5({80trhX`?(ohF59WWeD;B$jZ4$pjzS%rhTHIoO!SH%C>?f$?0lI%^em%%mO}7%
zjE|f5n>_95?SQ;xEh1t&Lx~V?*LjmbJV0F{gDJXHTUXdNKshS}S?-DOMVslBG=}Fl
zrhaAB_K|0A2Kffq(d54B<<GNj1dxzShVUuPR^7sHuD&N*<K*y7-*J|y1g`kbZI`|o
zcM^;aduLw7bmjg~Q*5omdCcj>tJ~^s+ALl*b@#Qv>t$btlmuzt$Y7hfjAUdPEbb<f
zecFy}4>h|b&S0}CQ4~@jnSpFPy9(8DYR%Q&n}*bfPC-^ZU4*=4gNKNaZ<c;v{8O&g
zNvL>o6S9*b<mGM$bIMe(4(Uh9G(-=%ai7N)59vZ&FV>#*GmFpbi;5jW=oZm-aOkcg
z%{_xZ3+x%7WS103QHNMlA6_s_o|S@VggN92YDU{bYZi>fkO^`!X1HdBO0a;fYL2e@
zuCrzBfHy$iT7|Z!6S@j%AOH;PaXGd?LXLZqJa&is!gcmQi&ln!xz^b*(x`#5Eh3G@
zg?Lv%3Ut=irJ*YiL}Py!3Lb3g6m9-MbOQ*A<YJuPYm-za%sR<)O2(KA8{AC>DNhu=
zaBPNSdBnK@lxZ~Js9LW-f02xQv|>v#Mr=(W?tlF~;5fiJ+2sR5rda|)Pa|t7XkB58
zov;=#NZbR1!~qwV2-wTeW#CF{e3DqgABfo9#d74s-yT4w&SP&AJC569H(5I%`-r)z
zhSCa^B2<gZKtKx#zNT%F{vw-ClxBa@W4%RAnwseCBl=2R=0^h_NhkC1<OfWllbBF(
z2Nmo#WPtc~q7!(IQnges*_={2YxW97uDqfR%-tPgeIeY-yfIj$@c8@8Rzw|$@nKuU
zGwO`+2OF>pU9LmhC6`5pCDU#T*#mTfGD_YJDT}J+i6aP-KEKEhK$w4>CyEJ=D)veb
zvhjNK5kngvyRX?5R~q8vv9In;(L>69ft;dVzi3>2!-khlV`$5L+KoIA8H?NvbjCcB
zgONVd^Tnd`Ew{G<(EuIqMr9hghUO}IdkYtgdq5tcz6D1#^GLNkUBW7Hr-WP-^3Ff~
zXhco6QQ+F8s?3rj7Q5sq=Nlry5ZncQJXpKT4QG}tF5XP1uf&rXcMWHQn_}mOdsg?e
z8{51)4G~zA;LJQVl`_U!vV2YURfBR2OCSeyyrGcmFfO_n0ck)1U7BPD^x=d83@Rw5
z8~zbUX7qe{_B?$vRx)tWOce8HHzfC3ST-sJt#uiEED$N}&buRtZe2%|C?-x75KD*k
zy7CPUQu;S2K?O8yTS~ASf?+7RG4F5NMzORhYXBBRV-vl*EbDU`U<ySA5k(Rx%P=JX
z8~|kW>t5O%xm~VWeU$w@rl$>D2XR)=mOw5-)$+%g0GM3gP+OIpRv`m*gN3cw9(aq7
z@rXTpQ`-8i+J>L_!i%)~Z6JgA2gv*|4?>oe<;`N|*qh8Na2g|$l<Q(}&7RzHbHdNK
zsF9%E<|WieYzIIqakPdndNZ8&rphKamK0QYkRi4dTPP9#^1BgHQr1zt1wWYC)t86D
z8~7R6<9>URppzhQG*^UN;SiWcdZV{~-GzIAvK0$Ix`L%4{2~rv?=gz-fJEjAMV)qB
z-wI^WGCASAiHP3_VTod9MJI+9c5G?O(v3pboA*fg@oL$4>_(Q)VdKpAC}X_yJO4sv
z8<fJf7!(X@s{w&+PQ=23ztUSeA+;HkOMeL6yb8!ZlD?VlTviJ9qwOxPNUu2g+x9-G
z2h7J?AS>2;^N#(jph!l*>V2DU^2DV44W2&Q)rtH?rki*lyQUXFpSs87=82skuK&ii
zKIN&g(ljY611-x)J3k%8``QL2r;*x=<V4V(YQpw50)Z-nfmWaiKKf8Df+g`I?8#YN
zHirQMaM=W~0$HH6E#>D3Wl{fy=*a%GM_X~V>)17WR9txSj5*!lv=L;#mk!Fur>|M|
z3&()at2+AmXd*vT1-Fi&X$MQZgc*(%x^KKI%C^!Sc2{3??5T^k$DAHwy*7^dY#^Ik
zSuJXhJHwEkmNmE&EUklgqxB~kun#(3k1H);bgShqY8r~f$L}{KEl@zE$qE<h%-cz~
zcY`8*H4qkuxQWv5Jrg_bFRU55GA~$j)L{FVUf>N@qwW62@T1bbCrwmX(>Fi9z;dy+
zyUMis%<6`O5cgOQ4HA-?^booG=G}yBGGt<lVkInwmrW}Nd_CZkUb8$?!Myd`)V3@T
zjU2vQ7Go_G_47obPlwL7a5+{Agfu2bdKH-*Y4)ngGBE|J|LinER0_)<#_7+%tN@}o
z>`1~p&gq9AM`cR2*LYI;pymy;8}z8&%ep@AzD3&ASx2rB!gv{PDj$Ed_j$d$Qpreb
z&&eTu^s+yRpXfKIX-&aJV$l0SCBYCrQ+x@zA>=&sOO9h#Snh=YKw6RUqXc}N;MiLm
zKgCBiq`tu1fTT*Ld>h>?GezlS!3i+n7ru#KyD2S~M3iY57dqqck#ic{=@7noFFof1
zCdH*M7MBd*P%pl?Q@_`1oK-5~P2aQa-(xG0U8pTQE9>g4DMsi(1Wb2_VT~KUl;*E~
z(sQcVw~=%OtiU3HJ+CHbV-+|gflnltb+^1?n=Fi)@urQi$I&L?U-@B*1;v`xupTE=
zN~V+M)gdNd2qOeQph8>#(;}x)Tv=AX<lO1Suvm9QMd(Zv?{{dBqdREbHeKr8r>AIJ
z61OGDe;oJ}ux!qi%8{1&61ppLtoW@1=~HW3qx}W_kc^Z)XFhJHSy;(_bS?XC>o@<o
z>}n4h_hn5!R1g#7gAmm4uB`;gA)IwWT!HYf#X}sf^`_qP+g1Y>()ht(a96o~QH-LH
z%6eMt0-K?PDhg99;X4xr5CMyLnIDsFX#5NJk|L{IL4mxF7OR5i>J`foOL+p)$E&mK
zns?r#bCRiNSxhYU|7B#;pK+EZuA3K4=as;;t+>bi6jdxU0nI22DY1X3_(UxRccmBM
zP70Zo6NSu0Jydmb^T7>V-Mo8yi0W6<Q|%2PsR$<c0G7?n6U-)peo0Wa5Es4{ZQ|i2
zpo(WVHP_fRlciRUf=N2|K@h;q?AZCSnel3=NH!(mH1=<o!TT&Mb?PH*j$+Im2XwOS
zCWcq=K!6b7lV`40Y>m4<8-LcYD~gy)+TJkpzK=>n>`Rg1VdB0ty|AlHq}2P?wSb&V
zohPSFV3W>jNZf!FhOveyfZ3BPrF{u_#uU6;JeX`XL%3=Ksf2WUwnSZ&Z~o`^F;qIW
zrEvj}!FK?$Zn*Or7zme5VTjR0KoPB~fljg5&*H~wAPb7;G+Yi}q{hJq$cA9OL`@k(
za|jE&x^C-Ymo#8iFxUZ#zSnIpK27{DQk7X<NEFx|INs;h50K^Fvb$lmI*KzWm(P0u
zsfcxxpf&hqF(^uRkZv!qa-r9EAb4fJ%i|jQR%WV*PGw7lP4=o=&m=w@P$prEjFS!M
z!+CcF{UlMwz`?-;s_zO`Ky7-s_zhOiUUA2D4(sCaB*BWjNmHf^ApIDPGzg>s(Ng|!
z)GjvDI;N@l%hFaJ=u3ZnP$UWqO2$8}`$mlHaP+Wo!b$fepWsJ3qF#MlP4Dy)d!E;;
zwhPAnxP?S~*ga00)5#Urse+LCe92sRB~`)l`0e^Q&)NtAn^P~MHV~Qc5=fnAXAu$8
z6BM$m_=0HZ0FiZ#{_@hSCM{*LG9fBb(LekR*+f^?DNBG74AjOFFrU-0ME8hNtPx~Y
zHEbX*moMEpm#J+O>;YDcFx70y3EL#wc=j>x63F&CvcS+6Gzp0XeN<c#rDRQ}3$-VA
zM(qJ<(F+~63wY}n2&YU(ID?MN5=D_X30|>92%r+UZ!ICVq*Bw6>2xH-&jjypP*@94
zHrY4sLGH=(M;gZi-D01nf!;4c5VKePhN%vnocA{wM!#$d0-TPFd2a;LMVKtWnW#?L
zXwjaeynttD))J`(5j_s1DYU4Dy=e1m_GZ3Jhj(>)He|!x90P=h5N`F(H~uwR7w=dx
zD5iX|g>$$;-T>;O`HomamxI`4F%kJtZXHj5Va5D%P&gd088DSvCwCtixx++s*lp~E
zc~9*7P+71>8rtBCJ_g9uE|&^Ue#^~AZ82g+@}jq!@--jh@_v%2D(!*!^Lbn;X76!u
znS_0y-~aXFVsy6@4qmo6Yp9XCuI+Jq=UI({94e555$y5U4V)7oN`=z7l3#FEGMN=0
zarX=z4QO0xx5pl~(9?PN8_XHq<CP*SiCqv!6p-gt14^|Je;5()=p7$Q9lN7$FXJ)D
zfG#j(?5JsIW1PQUX6_l~N6V25W#fYl@aSQjV1bQVgX3(EfV~H~9Sgl9DG>(<zN4aP
z7G?KJab=h1!sV6b?2Zki#zju9l&pEbaWI)OA-#=k*(8=uPe9@{F-o$MW)4ADPhSEC
zf<Y!oZddF;{xQHSJRgy%YD`JW#6ptX`Qnzy6KAh$W`!s^)T8>HK`KkfDb%Fur~$Yb
z2%adiu{uL-+f-ko2c2<7O*8HKWL2du2bW!jNlr}M2Sx4o21X6;f}$kW4-i-tEHB`T
z)?M203A0V$!T^NiGxZ4h+jO)$xJz3ctK2PF;|$H|@H#+hMjZRn2M!1^8TBDa%Nph8
zc9v_~vp(SukjlEI3FSwQk580gLrBG5D0DW`lPm=QAPu=kw};rs$ZQX7S-RyC*eq;=
zCrW^yV#m}4w1BPB@K!3-kR*#BN_9z$JGw~1zH~rK)Mm|lrA)EnJWF_CpINUXrAt=N
z{do&YkOlKP^r_`n?U^8d+n;oEz&0OSBe#ie_zH`T(bXbbm`r^B$jO01SDM|KuB!kY
zG_MYE^#J|9Lj@qUU?T|<F_4*<Q?z%VIhMqyRSfH3^Am1_pPG?Y`0_qV(z3ha4P7-y
ztZQ~rh(|-p098sCdD9G};sw4qEqb6k*Vw~`G|4};rF)#y_X7-io*tV?Me4`#SkZ>{
zvSYoxju@wwV3o1X)i?1`DTex>%~~c6f4VnLBFRqF8nA4zCF$|96$_(54+>K&(Mc|h
zZl^oe49PU~1cDLDESKmBc@sS%W97E;!Dcl;l=l5U#$apH%qF|%91e8ns>%4l(feeU
zm+fT;96Gu45+N%@1ooxAdZ_J*r6cV3T-&bQgLqD#s_jrl+R)R%pt?`-67R%X`dyHN
zXs@8fXqr{Fp+dZZ@^TF+Xy>*atqv5ir05Fd#p_fe&_Qq{@H%#QG@8wO!ke`Ejj{+Y
zV$<1QzeFhb(i86zbx?CE-X+UZ%(6}%z0FvA`HXwOoCu{{1y=2Co_h7uG-bRvv9x?;
z6?!%^uU~ZA-63!-4iff7AV`xa7j;;N<}AQ-W@te?N;5*xuv$%szBaFE3Rrg}u9@s|
zkXzBYUEAO*6jl;8Jt|^WB>^l)D+d2|k-N5))-iRufHAPPZ4+*~vOLiOLLmj{36`7Z
z^oLMi+0=+C%X)e)y`zkwILvM*Lx)v*5XxxCFW~ZSJGvBk+kF$l1e!ZVv37$b3(1k~
z4NHeBKc}e%LXkiaO@wR!9-N>&O!<ehzwSki>Ho4nf%CO9rRmWrDHaiO(Pu<`=P&<N
zq|B*l^`?G{%)nW8ZmHJ@swTx8s|_qZQLOZtTC}ZAw68XsNX4I{=|z_PD|d|;rH1b-
zQcIePSv$*O+kKRRw3Xypq}?p%cPsj^WqA|vAF_7c74^pLh%addVcIeRcE0T>?V8#>
zEnIRU|7T%ijKyCNZnMN<ElI6-j5}@p(YT-X!BfhqUG}#PjWX>t%}-F2&zErUMHU1_
z8p0Ww?D@KM;&~{k`@QP0(|6ZbCpWa3rpDba`KolU1`%Gva(N{?SzZs9rPj@gYdDnR
zIB|no*Kx7zNYZ<IqMfQ=$7|>S;_c`NUdPTn%FeH0*p}2|As7rfx3GBWXJoMKE?i6C
zf=^E9GpyROLy5B*y%NB{hF66e+f%0xMcXsIp7~;7@%j2i>dua{t{|46qKCn2?NM%R
zneKfUMl6nlK^@rjNqGp@9?LXL7+n#Wrp|)I$d0o@FbHCI8&&ine}1erOcLWFq{tZW
z{A?(LY^znBJBB4BNa&)??7&SOqk6?Tz>;qQmBi#O)b8LgpRX<ZzqFjWd_oQn34GP#
zpJAuZ&MoUoH#`RbqrQ89p{QUyfocCgYi|SP#&z9!Ruw@SVq_cjP=Jc9mV{R*G|?0(
z5@=GQWZAAl7br-kBB0q++Oj5Qx7q%Rcdc&8iO+0ijRFf+Gomb#l4g{39J48EqIfp3
zNXa|dNwQ&6<V2oz#w2C$XwR;XB|6U6Bx90__b9tNp8eedNJ~!k%sF$W*z5*Sg;%fM
zyYGJd@5fV`V0OrNlYYH^*dsNZEP7cQsVc^h@^4T?mGWOJsGfQZ*}jHcYmkxRjx_>j
z2;mwp{94K(LQSo<lbAB^SN@#@zf+fQ3O75^p8`=}A<8Z%t+eLvGl;(44J7$r&*lMj
zir5y9+t66$W$kPum7G5K(BhDp6&AF_eS0rZqM{LB#)&6se4ENdRWEv1FTC2{XKQz8
z94v3>hf|h~V`b;!7-a}En$Sm-2NVeD^u?e2-C!<YX}ve{FSG2|El=Q@xvqZaqJC3Q
zV89%-5(-qpCgNOmHhwgQ9Vd@hZy0~v9evq$x8GdfWZy{=2g0dB;2^UC&N*bkT`Yig
zhc%drkA<uDEqcoytZ#UQ@HGqvIW~K5f{x4hO4j`sab~XBOR)O%91Lw}HvH&(1{1>_
zU8xn0>*f0Olv26Q{(xFv+iWk?FO_i>RL)OW>(UhrYP2@t2wJZ#t+<b``^vgU4^zbc
zO&j|CfW3~AR}*jM%ecZ2#GWJD#XyD<C&N)ig`g_<1$CH-cy)rBIn{0Z6ht8cJY9^^
zVQ<4S)%EO=ORD|>HA0cfMGwMh?7Zv~0O41N*_!rJt~R8P>W?;EBiHjo(JlK;(C+2@
z^|kBsAE@1;Hs=qi&4hs8UPr%tNGmHR-sE2!dXt}V+3W&=!X7j3_*b8tdgiOx^gpl{
zskge>zD#WxfYEIz@j%__D!j4~fdp`+klg)2R&*YahBVSVlfgx)*}}7=F8M*P(oIF4
z&GSH1u-uH}oKV)fSC%Bry?~)o&=g`9c&U4N<A;Y!7*y*G2>wRY`4@Qwz10`6z3yyW
zP-?Ovh&Np19dtAPmGQ4^{|eLKZYR|3Qogo+0?*7X`r^RVA!2br@<H5d*t1G(Ew2q>
zph6oP&a;{XKxHOi(L?gtu<uz$Z`g0NW%L+7od0EyBqe+dq&o9QHoL;f^p$sAorB|c
z&E9?_?_8fJRb?Zyr+0Ce^`0a!Lxhb7zD9);nSs}qj=OKf$6YoVe$0L%Ube40gopzK
z$j|0CdgpO~U@-$olqCc(?OZBAL>WbULe@yk+E{4aj)O|{h4Y%^?^JE&E(B5xhF^Zy
zMl6&ORlxzyV`4Hc`lrX{**9l)zDRC~u<k)DYxnZ(m(m%~3$~!VFWSdzmuj`^C*Ftl
ze_Xw(Jlrw2sf~3FcOYR;R_}nA5SnSh#b?g#Ul{+p>h}H5s?mKf>Q~h{5FM(P);G?n
z920kyO&&u155(ogjCR!4^+ZBZ+p>YdDZGiLEK5cf1l3xY=_l(qtBo<<hMnXhWB=id
zbcz;hfOv2?`oH+sT#ez2OCN`^>?QLmmFH^AZjFhi#xbn7(YOc5SDF;Sb(W+-xYLBa
zZlX56khjX`G49qY#}^tH-X5%v3N3cQv>}h`wsRnt!pgm?m!ws&VIJZ?TeZ=2U+@%B
zkasmc(}*bC({QAN19$EVzbQaZxa>I)<S?b+{bkAr)X=3dd{XEXAHmFqB+kihVeWo?
z&Ry31_|4miYoZuJK7T<kYK3`vAyu>lki=AyVKS<t1b@&h_?0G_aI;*+CJ*&;`3g9Y
z_LNeg+NgUYsQo2;A;hRe^S6qD!hkj{oKmUnZ+zi*A?W~xz+#y@g>$f|8_HWn;@+k}
zsSk+)i8?GI1oupA;-yYwQN`onXua_iBm&%j1CbDLKZMN?<0CCzk|pvM06XFLY|BmE
ze2O;q-f<PKGwLB(rNdbL#0AQPds_BOn(~{}ApuKG^JgzU`gii=NJJtK8nM@iMPjY;
z)1q>6S3kxsp~@3S(E9M9n+{8Y5nAPogsGkLUd4W!s!8%6W?ae~hC_Kag(SQ@aO81d
zpvtSPG#<aUt*$pR5Te@-#vJ3+>RO(E5@zpN8|NCIq1dX%C?R*zU_-l*nuK@0+f9*?
zdj4o#LOHw}6q~N7@$+StFHvPS_z}kWRF4P=0%gpk8-~xLQH<hU#kq?Me;bHp{;*e>
z&?MOp?w+m;N@bvfdkm;w*`>DH6#$RxP&#GPinNbhB{8*Tm10TA+BV=mXP^&qw8Ue!
zgYqe4$cwyAgX!+8tigVka%b?~RW5?6Q@+z)6hT%;+bO(()`$Q&rYm@MUH3p7W}VTw
zo_&OyvI7MnOw!?XC(7rw{5@axSnV2+L}m$=#kw>IseC^?w?LZ;cw!gXJX|oiNR}nQ
zdAC;vciRG<TJB8|_xCXi@3YS`XLFo^Zc%;W-uH;j6fWyA+&j4L9xl(>+dr5;pKtW$
zyn+drtXRtc`v$p#H|Q^Wzj0#xL@o6|my74}59`TY<@YhA5}#(F2@PXS$oP~nAuOmo
zr7=iA2hY$f^{W>!*}%G9@o;_ol$V=pG{3Whyf;c`iVLcdNxO*Z^DqAggYNCIH>fud
zih|qd%U=FAoAN@tCe|Hhh9-Ds=(Fv`cuMFeQ8b=dZ;Q1Ke$#F67ZL%sUI%(1+>-mJ
zBWUCa2%~?t4V;Yn^ufA%RpX=*W_8u^aK!VJ$G#nbLWRDs0Yyd{L#~PB7aU*0qB<K>
zK=rKsDwIw@mc8L)ihzUjwN9S8OjEUqo=T0`UPYp}4yL7YB+jRy5oP$DJwg<w$`b<n
z6K7M#pq3x$BC4<HkzFIj3e1h?y~`fq5wJ^{V19-K$uO3BqS9gHss>R|C}LpvYN{cE
zNXkdS&wqEnVDepp7Y@}5%XMenE|^;QuntMtB|#b;RphqcJ}PTRHmwY@qxS4!B4w8A
zqtrqmutN%qs>&qLj$nV>AGJg}X_B}Ep0MblfNlE$UN$KUK;ZP-z;l<ZC{nzUmz5qA
zvYwcYcB3hX(^Nw$7Xmor!~LUYtaPGp(6@4vBjpVrvu`J*V(c)e$F}o=VWU9jEMRfw
zSg{M*qxMsesss3yZGA&p(xKj)#XY}`7!$KLK&J<+g=9=%JYty8u+YNC7Q9Y*E3E4T
z91fv7#H5Hrz;T0cyW^1ZDu+Ek0&t25>yO%AWY9;^Ouq1=YcX}yLxcsChztnX*Q2H+
zy>e6eHpJa68r4t)$pCHwJ>P%fu=;JU$P*PW)x0hF_jv`<_zL!fzMYG>_duHsZ1&CZ
zlsP)*je&nm?qV}B7*fp_9cQ4;8q74zcf_;nh&PKO^XzIf?af<Ufo&_nrcCuOeFk#u
z5>R+uo;Zj@vO5CR4anGGb<V=lL~=vol@Tk=;_u=xBNsu<!geM|V}+5T)Z}G*Mws<a
zy~+Wh#$*qMD|(_K@`wr**tfU$NItlFm9R%Ly*)ylrda6UPL0!JcQufPUQUXzNS=3E
zzv;=lgc?uU1TRnM?eN@cg?J4KVa2*cD6AKSptANDl(>ZJYX#pzVfHZBZZJhh+g$G;
z8Hpj5f+wTOYXBMyg$T;%QBNxNp3pezYlQ{xVJ)CO0dAI9X+pEzbVt;#woWPucSM(&
z^X{I))M26<;#5ebcJ&KS{Tvfr0$45=An1JIxQ)`cZt__VAn?^XA;%u`43Y#jva{&E
z@bm7hy)V4ITI`@@Tg7wbhjAw%XzpwfTEmcEaSWpY*l0mx%OXW?tIG~KbzP7U6~UF$
zE=n#TNv)RXxh}??>H!TP2zShrxIxH1%UY`Lkl^?$>9$a8>T;d(0Ko4!tko^~ZBsPn
zj6DetWHkN2TJ~eWe+tXA4pncc{xfwGZ11}Kb&7#ew@ZN2v)o8*5bi!iza_9Se}c&3
zyhW*BTO1CA*LA#gjPI4Jh5$j;2vE6jAyyh=;K^he5w1<}v*27IB>BYC1V0n{S2HLu
zzOHv(B;VFs%InfRyF&<WP|wN;!B|Gh9PwG>m|1}+FM*36*64{-Jl-}+HI!u#Sq~}a
zY1`ck%JUezDQs5|=`k8+D}%RPg6?BfPl^M=8izlQAz{XF%@i}hg<`Fy-MeWUIfX2l
z8U{ezV4(^MFa^dvM(q++u>q-p$sX`vi>MSrj@<>8|MjXnxnh@3*$<U>)%i-z*(S)F
zEZ4Mq<m*{urep!uWOGQ$=wi}|JVaCtc#f3mcDr%87x&_F<GgnWyXGOUAwxJv(X8nH
z21+DCX0Wh{_jzy1AF-yd_b$qoaNex9Uaxyrudm-ervktp$dSdJ?pFjwn)|Ri){Xso
zmGYYQWt%vr`m0J3FwlX>Q3k4ji8FOWCW%WA3K%5ELE%7n$fWYbV!4J+1UJ{Rc+mea
zXv{8|fYv5eqJau=L&8*~tVm-ACEC&r2)@2A<&#b^Zp;#n(>P8g5pxp_(Mj3(56*|2
z4dmAG7I%w#OSS(7SXu!C2@}sI8<FB-WO8^Da1ky}hm@#%@?#r#OeLUv6#qNU;H_hM
z`|33e5Sf}xI>!D*rOKwP?z10f)``KH`glk#GfFw@2eSOpi|-O&D5a&C^IJrrB15CY
z&Nm(A0S4%m7|ynL%xB`sFwD9^m7O9tG~%hUuHNSPwTU^e3ULUZ8;l`n8dC#U)l&pW
zP*-7cg1Qec>N-p2r&kFdFChl2Ib`Nk1FeD#O=|P+aH1U<(Z^x4I5ofaF4l}oAj<~9
zLHDp$8&8($BrqU;O39^TCA6lFLY44GE*(KpWKX13Y-fmTntBZsLIyg4{>Hf5P|nDP
z6J1gcdWSvjkS0T#8>PZ+TMV1@8fgf%m0k2C>tCHx<N1`CulbNS3y`{linN(9$e=-j
zFZ?p~l~B!OQ_Z@*V@?$p2(9+soFIo)vMI5@_#dPK+t_D5YG2&0ok#I#j3Kgb@#@#1
z#1Z&gmI4i;E<j`HJm)B>MKmZCiLEvcy)jA&aw<rdHW!r4(sFqNCOA<mECBRVKZN||
zr$4?|6H_e_wdfPZXMdk+$c96xKD%F%ZlE@Xi{%rZMTE_=S7T-a%O_ev7D{|@Tw*Kc
zlyQ?HW@*7@6EgH}&#TNTj}@YzgtTXE+s@H57{4NctW1*B+t0F<yxPEa2F2cSI>&^a
z_fDlQ!G<Q$pLNgFig=-OoBzNPh0I(>Rv^Ftxu}<@mi97K0}?qQ4!#;nEz~DLs^VUU
z0zZ!no<I*AvUS1~q;jGjYwS{EM?LgH!P<wb#I{A>DPU;ireKb$FewF#2Iny_&8|tH
zuPoq-RTj%Odc^-_5C0F^cahLk(Z>cX=lh?;A~gxbz8>x12#$5&Z1Bui85!au0G?z{
zDi06=m<no|J`iK-Shv)mLFX*2<9w~|=`N#pl>h@1+l7Uq9lJ7B_bYaTHOc^6Og#??
zM<k^t?kyvm{Y?bsp@@+L=G{9sAF)8z=#(466*1C3`W6vqus!l==Iqj|niQ3Ky)L01
zIB6H4sFclKF$(tWvY)m=VaDh57PalXE#8J2qK84gViE{4;TW~8j?gVSIINsyD?AFV
z!P>w!apwARv98KJ)+|6R^;aZH*4csj#nf`u=KbkTqYjFomp`uSwx^ui>@wqp_-dH%
zLlNL%iD#qdu$89{-B3OB0Zl0F7|Pjgl<mcQp14lc#x8lD$KYNuL;}-hFNLiYHa)1U
z+GcK($sC>ogYdjNEOp1CYAmXwkirIBrIp1oGH6MWAy5Km6QT}Z>8IZ-eBxw{hz{GZ
zZ?3Z~V@Nt&owAZ5h7ny;J=jS~ZtP``2Lo4EjA4%}70(N)O>Fbqkm{x><7RP5zuHJk
zW~;KQZHt1%QWYIbc*u5;z_^E;cpV*dqjd}L$Ri$%xIqf4hJ!$9GHU<n@t;$KBCkXC
z)&NNCQStkC^5bZ2+rY07?_f<0_X?{cRrZ<MSrlk$P~yu6IL%WSMA!1YMQ+2qU6H_4
zt28Lz*ik-dN9{72^x%}3#wn5YI7E_AK9goB%W+}uu!L(;d`g1z*9iKaD%I6L{s@yx
z83PP5v=gsLQWPHBm&@A*d&5C3K!gKI>)Q*Y4tzydU&ov)+7F|=5Zb!F4(G1RltOYs
zPnhrp{5p2QqFR?C&fhK!ET)0&#|70YX@~3e&61tQgN;4nTY7$a4vE%~^_eO#hH>^2
zYsDbhlX3=pY19QT-(cTX-msuLl-WZ)@@0D`bTgzVGXwVw2qlxs+j&jZzRL=pa~+<<
z^%QF@ylPXV5}iPpv2-$!a#l8lvG9M_Xre<s&;cu!vj*^&fj=4ViSkU4^&WBAJ3fK#
zLhZ96*itGfz-|7qG&Z`=Vhm=98Es5qrj;+$DT**9P$1=CWl$hIs!ymizMQ}t9k7Ov
zl2=&A$-+{G)24lr8|SR{1d%;V?mN!lDl`lVEOdERO89%I^p&DT2=*LbNoVrkzsXIA
zWg||=b=ZIXs0wNWLvRXjq!&Qlsh$&L&${Oh)$I+v_*s-PoDZN<htUm@#iR)~xK0LB
zjvzGAf9N1mA$;2@*t@l%x2n3KaSDZk5GHFqZs1RNdn-84L}OxAicu-T>a1hZQUOJT
z06RqVbqWjy7zl?sF#Rpw7MPWYQ(;CWZD)(|lU1?=Q&dZ-+dC+OxYg%8)DNx^buH~0
zwMT6XOB(c@Z5>S?eeuQ#70P)+rbmRW9mQL(+;LdYIC}nAh$XU@+E*Xfn7u<XySShH
z8RCX1;eSXM^$GhzezCUbU8v1b96@UQQ7frz$vjr>$p$TVNff4am`u-z@L;JH0B!U`
z1Ucl{e+n*=(&TUq>832LV2Vif`c`|}D#%qtu5g*uS|iAY#y67dg)|VDwYlg?c|By-
z94l0o1H1(5{J(oQkA>f}_hb#!FBX~lB&v7eV`{WswuQ%~t1piC#3~(bk*A_~=B=?^
z#B@3p>aZZ3Ab$oc9YfKW&=JjC2phC3ldDqLUBm+i85x$hy$i0Ys@+BJJdEo+8Gb_l
z(;p9KeKC5)8v{=CR!EkBc~G;*WU9oiGb^3in3T@lK+HOpqO4Du;Y1qF%^n7j1SMLg
z%HxZmhKo29xsA4Ea<5LX0UrmUlSRqLGOxqA#o&s8TuPR(9Ei;~2%uuS!>PRyMup`3
zO2u0Q)@{I)X18Wb_<`gK>QGeI!mfJdghy#B!mrjtEV|u`i9sgccQ%e6w{NT!zsW8M
z%b3Ntc^g8N-vtm!nsOj={EAlv(le!gPN#;DrxWH+&l1^!?NhIMN3<fW6EzOh!CEgW
zdWCQ_d_ifYXAurRnpnjW<5|3Q!mPJVDbnp;_IydyD2wHYhQyFjd6FqTs7HG2u}S$q
zdT(mXsI%oojrQ|4^@Aa6mn#f@9b&b`{z-KYcxZ`Ga5fI;E$2y<@n*{<>oaw_hH8oS
z23*dNNkA9F*1i1U2UEX%0bd<Ep_9?V{$#I~6@e8KQ$Upy9u%bg=Par67gRg;9#vSV
zh2}#5<r<J9f0-vvx2FT(k@+5QT89V$)zN;f)_$8iLKzC@uHqYP?JGXo&Fqmyzzzj+
zP&<4B*LIq~eest6>4*(<0NP!}h$gCa-Lh9XZco5%sT1a7&ZF`nt&eK(y&#)wjjvQ6
z-~O0a#c}hpw@H1_{ulxnovY!Afd*SnyJm>aYdf+$eaGK6scfv+;YnOIK%?Ddf?XSP
zn$@#KO6Nu4EKA6V=pSAXS()2pbD2HL%P(pfvI+&~Jff~JjBl4<Z&9el$tDMcD4CU1
zcHCMyK7hY#HDswwcFF(;SJ?(-_W4p?!FAE92GWgl6gT&}!T=HM6wTZrabwgprCumN
zJ*I)!24DY@RHR#1uK{}8sO>F!eGSeo5lwWb5qq>e&=r`zE;)xsJfVaa;Kql^(>jdT
z6`~ndlrb0^{-Flt?Ok=lFWC9Fos@dIgr80ULSPOodN}v*pVRZ~pUsK|A`!Pa++ovc
z5zLSu<^Uxw(YETB>^%PB^J#2i8wU?U9BOqzxJ$Efzop;kO)Z_YN5FJXVSqiHpVHvy
z_*rC-1ma7FiC=bLwd+0tT-ZM!r<@Ci{)koT#jEg-+r?8-KeyVBW~tFVsBI$%6Ua>g
zXrvT|#KB2E51ygRwg+K(H`Ot1JX?Z05lg;k3kd=|HmZ+#43=kXJFl&cN4?v7=TTjF
zetIPRK~};Ruuen_vFDLSgbUlc(%Y&eO-MzrN;+0(W|dq0P5#HG#`HX!brQq_KnFQ}
z^v^Qz-jlM6>70$}M3JD|=SV7+2-)%TD6EVe6a{%S2&N-l(j}mWP;X-FYcG^fcq_`k
zMKh#h#E~#rsd6O!V;PD!9<N(rSItf}v&pNcSz2HpT3hah_^?;D%7-PE{V<a|hZ6|n
zcx-PJ65*YSqRn;5m=OP*<4FevhTTkg6cnJFy^T`#mZ!WLNGhQWjW?9S=o3|xDfPys
zM0;wUT;&j`i#g<Cy%J6;tM>MDRHuSD!tKXpynS!OT;s0BY?^zv18tjb!SjXA3OCZL
zlfY@-t#pc{Hli8cU*4>yFvLmXE5A^#50Hf!57vcvLt<^PsIignO?exU2osCCM`;(v
z)*AK;4UuVe$TFFP@^{&}{M*hEB5M-5uSi2;0gWH_L<5=)fUQX~fXKw3i+|$h57RA&
zI$~0Xr^e1o-koF=V|h$eQ1Q#2*cHN&QXP>DC%mRM1(#mX4}0f9St;*3Rg>x}@AJ46
zM&Z+(sMx9ScG@_AY@)YuO^FhjGLe$W(|LF3qiXxjc*GIz60UyA^O_h>&JIWi^-TK5
zI=Fbpc3L}Gv#XTkn_zJkQDDIxe^5W=Ik$<c1GcJJ036jq-1E-cQnkYee%@7fDBx|S
z`VMri(`y2>>YUxMwoMWAsGZt7M0(d^8a)z+)CG@tE0hU>*xEqT*m1x^jMfv;we;QD
z1Kyi@7cb=N6L)rM1#}p)Jyt+1xDjbCigHs4o3!j(w$=X5GiUdoaF2R-JX@X!7wlIj
z4pXe6QzsjitFLVKBh+6&VRTY8A~#hx(C4mbLK3u8g7z6H{10=G35G~wwHxTOgaL&}
zYkrJhU5y<dp0f#NwKtg52EdK6ZGp-h=g}AQ3&H~FU4<$Eh#=&UOU*C}!^|pn;Z*CD
z&)TSXCv+Xph)lQ~qJBXb6rgc*tuTf7$eSsMDkt%Ba>z5ohDZxjYAd=wOqO_oVp`-#
z7>4nM&F_YojZp>jfsYX*LA`tkOi`kud=b$~{54R9FX@3?=WQ@YdhEju&~eH;$Yhca
zA|QTh-O3GN`6<fM07@_LOSLsLI?!2Ru9C81P|yoLM#ns$lATkH^_~w!2?!|?J0n`*
zhrUZ&;PLupO^N{-&<ZdYyOLCC0&Ev`I$AklVs17D26{a<Z^8)uvU1mziBQN>&s;&=
zn}`z7r1C?ES4S;nWf(N%XH`NLD?B#UT9v3e0N!zrL=ZM7)@2D#)lxZ8ts%NX&;my6
zzCT>uh4;T<Hzc8uSXjbI$O=adT`Utt1|Og#kR=Mg%RJ$zDdEAs2_NWU6&uf+tg)Oz
zg==-OJjE91X$}V6ld(f4<;>hJAXKKbvdRI#6Esu6CI+86{vOPx(!1cHTKH$B;0NF+
zPNWQqv~=z3-_J;*Rd}cdQN%q;e0cS(oAnfagN=B?VX&+o7CKyj^aKOaad5ZRY_Bkp
zuWqeK46-HCbm*yej9eIEeu(OY{$(=U)-c8l^R{Q*EQV8M5$31EyYcoL^Y^1?XV50#
z4QKNVlR@<v%N>g+DO*cc17?B*aTQQ@7BrfI(4}U}h$JRA&VFUx<Mx5WRr371a2bp0
z7Co+zk)*#IIR?SD{n}P2EI-AotLG#-BsN9AfmYE<Na-AtFb+}<aGCEQEEn>EU0qIS
z2B^~UO7y_1*YCVAF{Sa9Ustzf*`l2CU+%Tv+-C;bd)B)ZN;^euZgjs3s-D_OKLt`)
ze)I~qSwpCr!e58yN-)vVKGQQc!d%gl_Q0sZCL2~5@Tx#Gt+T)SUTy;+pTnCV&X8LV
z0XS7{vKR^!V>>MV&nwD-LCR>~rUEe0yUZahhSi5O^nh<f!;mAF+OyawPHtDZplrVU
zwzDO+qw6ARij8#LR5HZSRd!6l_alRUjLlcyT7zi>50C;Ld*B-7;5^#wdJnWfIwCPm
zj9wxhRKnzQ@sx)Oifnzqw^8+aq8DD#*qJ9vT0%!g1#v8bWq1aRjoL!pn2wMOF8{`-
z8lj$N%%!HK4u`gv@moLOiO4ds))5NOVMrVz>(%)hXajL5&_jyI8(nR?OUvZ60hrqp
zA$@4z5uD>R5+xlK8ZmQbU^jNv&|Fpl|I?MLCt)y@fnqbWo9&J0*p&$Dl#S1$G>d{j
zkPP<Blm9Ob9Z7@GoxC}6UQ=fAgngKpMRw!3L5rdSI>_DPnE&~X>-5bddfcKU>Fv~T
z72?teiz_MtFu9onbXK6dC{u4cQ?j~VUe#siZ()v&@4%n{8&na-BUXF_{r+T@&IGbq
z^K}Y1Ys2NbR|%ykBK~_e#5g5Lnm`;R@WN=-KD_3tf2k(Um+DBTelyi~k9uQJ4%iDT
zFBmc%Sy;^1)`}hOs$<R!&xl70w^6+mUjPA7-bpN=y-~IOapnqsohm4Fs^v4U1HoqB
zv1-%|C>CAc3d~SgHIXjf3Z&C#cOS!r-*i_Mj%zg;k}2Wo#w6@U3dap$85=AYlbS6f
z;5da<7@@;+IIrYj`xgeME;6b4h`;EgiunF4D}YVlGbq2`lqyYBA;)Q7?*f`uRc@ht
z9OcE?c7m8TbP*t)9znIQxW@kQFX9z<^aqE*I-jh$+o|+`azfp*6Xd$el~<+=yI9Q6
zU3sIjOB?8!a6tpef?9uZOnP$n+4>O$1Y_h5d(G)NqJG%`nJWn35XJI;{uj_`j9OM)
z_6nB-hg2ID)r$Hcbwvy3Y8P;rOS~6*RP~mPBz9x=I&_ylW+#u^Y}T+`9^X~p_^?+K
zy$=^O-5PRW=m_kErBkaFR2YU3KMFfy0)QDu6$V2W0AcKu^137iwedkVtXY;jlq96|
z<-Y)E7y*lBpTt}A_Ur599URK9SECF09}sLyNZ&foLpUaWKTCjm9FK(A<T1Nn)hD)-
zL|opNzpSX+ESq=`eYfbb&WF^5&YLrBRH(vaC%<iA6Q^S-vAQ5@MhT<1zM))GK=Q#C
zfxV|2l&k<oXl7FX1*`7g{-prrCv9f3YCG2>Wtn%_FN~Vf0^)#`to@3Wq@|uo1BNR(
z8+vTANG+>I<FMzAEqW)=mQsz}8iG<#kXY<|x7Myz@(nolP?t){#znuR#+tFQ0fVi)
z<ewV53#AwOa#X4=;mcs)o>-t6S1@_XWUE3LE(-Yj1Fu1D%wz}OI9REL3nP{i744-X
z)akyyUaeN$jc7^LDy7cx@Cer)GH!S!3Y_iu{GMQj#U@P8F+X&RxYT;paK~-M5McF9
zL1SZBRN^gTzy@YQ_wv8mW-z)X9pkfwGaz;er@cvEs9nm-n%Q=U9ig?2GB2)-WeSuT
zasPSy1=ntU-u*rI((ToChiW4v9n_AOU-i!Ex_Z5S0<1wGX;BE^<>`^CPE_=laulmX
z0%PtVsu>V9qGR-6Hr}%9?nqtb08IUzvLYfB$Yw)jm|fOr_r!0%8@yC1d7HqXm$ek|
zn2>u?ycS>3`H2(gD~NFdn4eE%!vM<Agl_i9+1~!6Udi0-9abX^t6Ets=WPv54~G$|
z!@Xz9wp<;Mhz_1n$`q&Ob612h@rflUf|zqn6<U(pJR&JExj;YWLczcVSQFRn?<cHR
z(;0oSc0!+GX;6vQK5oz1x3fJEn$E@sH6MhX>tlre8L^_|)N4y8YEyCig09=X8n5A;
z^HJ50vZmo?>A101FVpOx59eVYD4sII=|V2SdjaRQ*2K??{!hgbat@hSyi{HY8xbb*
zlYBSUaV&xNXlvK!Zz5>6W|tS$oL*0W$7Y@k6qMkWvc+syMzC=D(yv2e<(ykuAOh#n
zefth?7kO7aYTsNdPI)Ed06oOSXB5+3vTOx}umt68mu<mHkhDxaTd~5u>uw2yY2*z(
zt3{7E?=5<n@w$&<0~g*a_|YKIp?lf?GVSFE93lLpu%ORrD6pmqhjry}S(0v2?#k-r
zs<>qC>zN~#8=%=QYJQ#25^N~I*HDP(LM$)A>Y+DV6b*V!w+1@9SQM1xvNnVbu_$<Y
z7D?l&u}?HowViFdQ)H5X{OG;ch)@L3Wg=K5`I`1`(s0iP9rCI<xCGo(=9INTu0r;S
z-U)Z#QLWaO)fVNKPBB_?+batfXEN#%R$)13BN(8yD`z1%ez@6sYA2{g;aya?Yn~o!
z4)Qb8x>hV+f*Jn(S~#NY|A~OO(ROdNM;6p&avSqXZv)S;P$?NK;u*-sYcD-!6T!c4
z!F@*lyjiV2R=(pXRZ#Vt3WK1GqUs$KH1JB8CYoFh0K#b3jap^WO6`Afj&@C|#iddE
zO13IhbP`xs9-s9L)k*Lina^x;l@?+X<Mp#g-wo$>^GpKur1{Ac%Z@rGL*~>FLsaG=
z<SQ}uqcSA>!s=}AF{-=O2}miQ@X)nkspShER*xl6!;s*F+~mlsj<=N=#}k9d5oQD5
zlbL0{_GoBTZsYF_$cJ!>s>q7X5sSvc=w6OK$~DFoCSz92ne}=TyW#N|;Ut>3Q17y&
z;m5{4Q^kAs?W<SG=9?Hhn!j0>e}Hx5mA#$_bZ#jJ(m~cK%vfU@RtS0#$CsSsE~rCz
z1Q@s?!5>I34&u2YHY`JcX?XF#2>YW?N_Yj93WcWBR)VGrO6Bt%;i85g%PB+g$JwG#
z(RX<%k|44yJtN;UxcOv=^3BMAgoyDxJSQU(%4)4dj_iRfals9WJ*D2*$S@xAsjb>I
z?b6X&{;&<iKuT)7=!LSgH^fm+RdL_w3%sCmrnlWI^*)9{$-*Jrgq0(az(2iPjt+!V
z69Ji=c~d?goGU@wltkmZWfH>?mUsj1^*%PW13^At#DgNv9dsYa=BwXZjlLhpNN3l%
z!A4*L;Irfa%maWD%TFq;MyrKBCVuBQHW8Pu$Ivo$Ws6JDQHQbz2G7JmFlv`(+s9Su
z#H7@WoD^9pG*dd9PD=$VXD-@{_+~3C;_Xs+NSOOyy##OX&I&W>3Kio852<XA)>{dg
zAu$1yifc(x8A9$3@Su5|HRv*1ol4%4TQX<qOtH2KoE8O)$%7LxzrvS<bY-?m=0h~b
zTl8cmh#5j^&*hvn$b|%?6?iGDaMm8tgzV=RNPi(Z@(ullM)RGTa4P6H?`MRN2oF>x
z^#um7pAfsp?ESOx<1YDBuTV<lj%U3)exPe=d=i=BjHjG&sE7roV0`@e0u7Z7ZNt!I
zdC|AQ+UNGBB0sQ3zEpXz{Kady7hb-DY<(YfCq?<HpS|Hd#N@clfKUX?yny1K6C0DK
zPeev{QKdx-`{wQJcpQ_kFb1_<V9{60EUzn5$goHQrcdk*daMeEXGGUy@;Dtd(!*-P
zfvCwoJ3EiQBMV(b^M$_@q-r!I#t<*gh6`#@H*m1owHpA0B~hH_M4E|QN!m-4BnPZA
zT+&0R9fEC@H>EHXQ0I`sao{6XOj+!3Oq1WkbC^B!r79~kWj(sx2xpl{1YbZLU#cf8
zemx806)sBX42558LJUTqtc|>>@|z}{I}b}Otls%D^GD9?b1t*TB&w0l(xdT>Zc%b)
z4;(Guu{=?|v0gl(9tP7qp^th5<9a!3XqPcoOkik-#4?F{byb1+lXEhEFrRo?^Qttf
zZ)7xubTt(;=N&?o7&Stljga0NAN)s@19k%ns+=Npnr#C{U#y?XSAghyJ=LL9ft8y&
znusuFmrY9Q#8&BO*~@tin4>{OrN#1`_fsSx2swmFYDWwa@lwbW!l0PH!MF{^Orm*|
zV=-}|2GbLE%`{dYJD$1+rD9lNMN&^h{kxS?EWD%`51&fFwTyd^h3&c+vcWTYT~E&`
zFL;$gcf@;GFVHoSa_K_E#HUN*QuViiICg4<UAB|PFAdHMUAbc3vXUCs-n(I$K*v;^
zA|ox8Z)sM_z1tCljHWZfm|Slc7~uuGcieunMrxn8RZ5)ml=@h|Ws$Yb(zBEOE2Qgo
zmR{d?q4%O2>-doEu6uZ*M+t0{qqn&M9E3{BD=L!`;#Hs-@mC>+(`AU-js`%I?#Mas
zoCm8Ft`UWi^p|u6M4nhhQhlVl`LA%!5u*VxW0%5OZJW2No;xoB%tlDjsuqxz%^Is!
z%<x!wQ}yl%^iZE&?wDmL3$hk`M{p|}KMC~Sz(+VdRT8Q<x@i~C+0mZi0N_@dTDP(<
z0(&j_8RVe+&^zy8HKmC}y`hY_B@jl#j8iE_+;_Yme;g9OJd0<R`Y|w0!s@PeLGF{o
zgvjSZMI{mX0i%--uN(m(pB!)@z-n%uKL6{#_g?(tB+%**An6WGu_s$EC_oG9qUDt*
z-1(jdzQ#IBh)3QNA2{T)*5dv%=o0D{nB0iYTksv|8cG-lTnrkp4_z^xn!_f@wnn{6
z&vltmF~CNU7ihi6`<rcLpn+7-k7Qmx-o){cYP@3RSHJDP3;pOM>lN{9<~yo5X*V#Q
zBt%H|pOzS?n8zdO&g|O4tr2mu_MqdTI>f{{KryUH1P$L5Z}QcXOpMu0>7yZsV49Ex
zVQh1$d|`!2FFyNk*r^lE38gL|BE^E3d>aP{V=O$*LiER_&Qh)_|4l_Cu*AHix~q`)
zaQJQ9k!VkR0=edSfGg+Hc}Hj{(aJDjrW!0g(f*r^2w4K6he!d3>gL~BO<Th3p?$K(
zYA7=Kn!`v8cpEgD%O0@<lP6`?SPZf_hxeDSv7WaIeRQa|fA!oD1=@%T#6h)Kq&uMM
z$I-(E8c>LRZhzN^#R3PE+G$4Jo;uLz#Gz5~Lu(y+xrOFoC6RG=m@yJOy;d<3q7%3q
z?J%)QhhSvmCMK8Ub(gH|F5I;gvuvteWNXgqn&^0jC(RhfNo7Qn7R;r);GBBJXSa@Y
z{FH6%OE1)sk0&F7g(cXD5zz|$Fqu1LxW3;t+n)NSxnJ#U^t{>S1gqn2!N+Ji@Vr#~
z4Ccahd8YJ+OsjIElBIG!;&SJA;?R`6q=Tv%PTCm-7&O+xn|;s;9<i+u{Y?9@4=_fD
z6E{a8R|`MEMsqTBZ8x)0jf|77j>D$xaa}Z%0QQA);IdJlY!9b7gyME$nPFV9CcMxJ
z5-XSV<jMc#A3(?nAP0j4E0K6YKIKk4FUSWyW@@+S5<W2TGZ1*pFF^najMOT&xD)po
z9$oZzk+y@tiI7W;%}b)Pr$<0FoFwI2kr8C%jza}&+L#rVBq}lO(%HDD(iigP?;TxE
zUA*PT^g51{9NHaREdK^N)>tz>Rk_YXRm3Y+1Zz!mGvuoHAR7h5=DL+yzK)opp!vre
zZG6X5t$2Q>wG#HXIy+~>L@K3oKtqb~MjXO;?5GOlUEzk(m9CCsMs$_9FM9&yunG`~
zch?;8UzINXFMs~`I{aV!!50d$^xkolWSoXas+=+z(A3pq@Y&V3?|AVazi;H0?5s!L
zXy4vC8anZE61a#bt4dmY=3J0b)hG@(WOF;R?N;c7U8P#zZLPS$bjxkKEAi9LTFMXx
z;m+(iWKSm1<J#I{tCHRGR$SlM<FT~`lQYsY$7T8gtGnWqpl|_|`BVM&Q!@KwS%eov
z?pnHmkN6a8;GokEQ8`p5S~}<!surDch&5AomgVgm&H>ZbM!207uw<_;nP)5E-0?PA
zgq1@Hl%tx`9aE9MJ?Utabx2AXFMKp}&_3YVE%RVCi4TP<A#@YCc81knGJ|Z0erZ!x
z!og7+WZc|zIC;nocXnDN-$n6CoQtwXv6Do(tYdV07WA2iI!fMb>>DSk+UhEgj+4y|
zE25`@0PrCXeA3zCef@@2tXffgXs31U=_HqN3=va_A!|ddV*ae~ju>OSi>v@`8v8VQ
z8%;vzF<*x3z(_bJM={F6tV^84e&u}$o)urb<yhMZ?ryoQYeUTTVpboL$Ir^p87{)1
zYdXjgE{6lL>`<|2*Uu$@X}Rn{)iuxdR^XDH;`w-lji%AAKBUBG3RE`dvQ`tis}UB4
z+NsSg>WLfPYwVWF(m5=??EY{hx|>3ZnIv$+jOOOyKDnuDICQ?r-akRs&aqK-mj&K6
z_nD#*LJ^^*Dp?+rdzN_3v&Md`_M0c2IIu8ljS^<f9*vTcR1eac`;(tgC8iiUSv!hz
z>zr)AnQbz0D@Hd2=ZllbB@in*=m(j0VmNo3-gJ8=a`QU23Dq<XI)3CvI*B6&&DdYC
z#vG40(=Leq_Jgowtv)%fFZ5Piye-g{Tl7qx#Ypz((_Q+yZ%(rbjGGw2Tc2GAo6LoT
zDJ7v{A7Co*dK#45jJq~$jZVOCJB*n)fguQaMniK!%-=o7a%^d6XTz?fS?RbY4-WGv
z!AnE;SgP4EE~QR2?wTGHeQ@cfH{WBh`1)2ZBQ0<^K?bh@%|=dW2$7ZSnp0}Potv=^
zO|DWwb}u8#jSxDrA1*(JQ4+>Q$8uTC`jk(Y>}uEilnE7HJp4CUB`W}&aWHG=W|DrU
z-7;XKT*gwlTey2()&OHbnXybaJ(1aqPVUnS2s+|-uIgC{1k@Ne_uCTxAo!28&=T1Z
zP^XR-j31p_%Tj<!bM7^9#B>GMuwY>-bS@PfJXDw)wKFlHH(bwmIFEu?#YmOrk}a46
zzBGkN1c|Z8<YOpluvl_#c5|31;qizg8|al#z>p=8uBTjP3+kCIPX=knG~CZTo!Fs}
z987`vN*S1&Xd}1XMZZmArq5@(WgxgGx8kz&;0tfvd01Y;D_GhxDR|p6(=7Tz1li?Q
z^8k<u_ebThUEAJi+u4|wAtG7}nFg3RO_of5(5eiAt9|)6xYdozCaM89a4&x1pCFcL
zoHzJ-b2d5&jWA*eX}F`~m|-r%zZT2{8c!!bmWSE{y1i5ziQzJG3&~|sPyp>ibvzxn
zie;Zo&4Q2yzkP4IXywW*lVs<FQx0Z;I~O8ixw#V`><eG9VVnj!NLR*1cZK+1vi!L1
z9-J^|v1T^1Sge?l<0%-%QrHsWE160BAOAO*&!{h_nr_5QGV>fcGm>BO%7)g_Jrk9?
z=GSAJXc~uQ$L<^HQsEBVxNBR?+LbwBvUv6k?Z?v8<_~4K1tV^rW~v!DC@)oH27~7W
z5n1a7q|W1VvJ}Gfg|#aqk+BmTj$ROA$HCg=Lq?AGK7Zv?p8n$RRpe|K6%ZpaYo_H)
zhe093^&#ZPzZ?QprpLKEn-h)IR`x+#S`X28OlI0I!b<74S%NReeZ~jMqxpc3S(aJd
zch&};S!|{2=MVqebok|_GC*`&R5zmMU=6m+2O=dAE|qlLz@)!Ceny@pK47YoE_?7W
zB=Wp6SLsW6+YMQ;MV2g&n79}J-7oOjIU;%DxR42U&h(Q`Y)74_X>y+!uc+P3IAIj*
z4yQXwc)Hmdy&<wYPJdx^7IULjHJNd@-GYDw8CO7Y#a9UMQQewbbeC#K#*OwXE*2i;
zD+wLpW-e7Nu*;3O-TLjY@ydvD4}{P@IJEiSf2+h|+UZ;?I$F*hb=_<F^nid6IAOMF
zc6PV0H6pWcx?nduNz!Z)YP9o)nU!WIF4~1p*?T&KWY4asmsdtZ_wE(AR@G&@nP=Qb
zb)4+eHJ4vdSD-$*oFpgl2EpT6Bg{!|#BEukMkbFJn^k)|g;rpf!p<-L(yJ$V6~aG)
znODO0QXe76e=MgU%$yGGIBMEvn-scfXPudzEUZrYh1JEGnT~r`+_!<C-R#I4VJAB2
zJ`vg(0JvFHQ2uM2j&b)52!4cajmV25xY2*lH6c2;$eV;Y<rPyo3%$6H#zO6}@zHbF
zwhuW>*;YH=59~X0_he(G`dw%Bv43~E@KmGSY-T32OTi3u*?f@j!AETKUZ?qE;u&hb
zQ|<4zgT>~wJ)YUUd-oBb-WV733+^SyNsicDH)d|Mt^Uk1$<!memh|g-HaXaM%=VAi
z_l<XYJD;~7vn#H8-mYY^*!{A-6rNDawmo)P+4~zU%YQU^LH*cOelzpO<HvSZP58J<
zO0#k4(ob$OFqB;wB>%&iBx)}mDrDlPM_1=|M-cQ(>ewro?P*r*4{fsvfOl<s>CC<6
zzRvfWtJxI+q;SEBvLkf1=}axTetXH#c)DFSd~@AgZ`tl!fHYb&kj4mbiLZIfFVn|E
zhJzRQO)N3un50wMd}!yjhMgolJ7Op~9p+{pY??{4xw<Xcc}8TnqiHJ4Ic9S@ydDj!
zy+rrES74g}r^!5j*j7YKEI1kCPi~xdtbVJm9<#6Z=%kX4NDxakbsz?cP0Z+2;^W?t
z&bWF$gJ*$NA>H@&SAQj2YK5&<7`pO*XQn^%;B>ClaSWCL3pS)XAux~8?p)7Hqy1pP
z?9Y79+2ZzRqTI}q1AS)Y^S_>7)1P@>kB6-(k6Lw%k6|3ESniGV2&Z6Z$@tJy!v|?G
zeJ$OSahuO1(j62QcYm0_eBh6nm8>1K?9S4e2cuvn*_|Q4#b^?GBxsYJn<f#V1MyF%
zqK^4=j@aKFHQUdC$^q^iq4oCCNC-VGaWe%J&aI8t(Y8iRgPxeijp*<$>=(1bB%XxJ
zv`TW;<1!+~LD%^Dqwi%AIPlN*w~Y3T5foMjFjrzDxGh*++eSo6cb<Wq`tIs|9s1I5
zaeEd}dUumneXxQ{!V=}Srgj688noOLaE~8m1h^$w+syb(ajLi*_x(R>lLBPA1WweN
z0j*pj2WBSTy}BJXx$ACBH_)V9wAv^*W(1`y!PNNuv>D7iLu<CQn59n-c=~Y{(3kix
zb(zVq;JxYF=j0=cuF!+Q`4b941z{nE1>IDiT|#34=@k<G=)!wLf;E@oLU?Y;c0xcy
z>*<h=yg!umnX{prks%q)7!F<~Xf|%N82kRO@7Tgn_Fw7qusI0o`3h7hPyM9#1eTlK
zdZy8?Rxs)Q+O^t8HJqHmK;gGyzY;6x$2ce#tZi2}B@jc(mx?WQ{x7Wr9+Y&P{h=G$
zGp{tc_`{*$+@3)i?L^K6*CMRC%y2kemH4dpM+ebZ;>VK^_9j1;j*lHwLF2f3nL%-l
z@l4z6nw!3O#4g@r?O8@pYPZ+`U^}iXwC012pwUS5xrW=*W_LC=fcx|ZKe6_U*V5+$
z2wVmP!T;0_tP?sAxDE^1WT%608v1C)Rv$*~ekv2#rh3pt)kVP-$xl;3Jelo=?lTP+
zj(Zk?ASx&?4~Tl}R1<?SkRHD_JOw>|edJxm?|k5;@Ir6F{m!i~g>$_}!~bUT%Uf@K
zt@YLy@44Q&^|hI|9{u#E@&EKcT0L4UzV?s*;LK4~eC>{x_;cfdA8mgr<ZmK>FZ3?C
z$!B>n*Lxy->x+}u4;pC<8<~5IZ_m8d_h{^Q{`eysH}GfjBbzq7vGUfJCU5EwTKUG6
zR=)8wtz7BKoOI>sVORd}zqBjwc%JX3&+`rb@I2M$DjVJi-}+MHp26c(kNKbd;=6mY
z#E80(uu;a7ffQLP{6#22{xj4evz95DxlhL7K`|k@MlO`OLGzPhSr8FxCbhc_V-H4i
zx}C;;Eho^4zW%S@4Q2A`XO3!mv#TGL<l?Kx)psS9+dGbn|ESW<?lY4^x-Gp%N3h+d
zW5c9^6fic5tC97|Qw2;>XdhfI3SJq_MZa#x`|PD{f|pd$$M?h$x;1*){zGoEK0fK5
zO-xt2dY@Ue{NNe6O2RaAODiKr&<m|Sv0IL9OCPK!<7OqR-DPrqFTMIr<2!W0+#8BU
z>V&O|xu1??Z1EVK#TvgZWVG5?#*vtEt!s1J?U<31$73i<=rP#ztVVVnT5-=-O~38S
z)6y?DMH&pWV2pMP%@9jxZSuVhj^VE4T#N?kz1W|2D7c0lr%GpTr@cBfVlQMORS@x@
z@jabT8JsPG<|HS%iXy+^NOr&ZIIM_!36Ab2+hcSYSb4W$`Be8PYo65|UvYoi)H!Qe
z85cKyE-;-+i*TB2ceg~d#*`W*`z`=FkRD3`bXnUur-eEU6~NC3Vc4ROURp7-xl_bm
zJtNk(JTJc#zj^0l9MTJ^736m94IQy7cdmAGm;dZ{5i22<X_5q1ZcPxj+>DqBP%LcA
zC}DGOlsXN5kIu$wqtIJPbnH;tAJCizBsR2MsQH&ef<W?1Xsp;k)QpML-Y@*p&Q6@`
z^a>fL9T%b-uFY8s3BUo|$?oHKOB}&+IOs|yEP|3j{~^{Iv&C*io>>kXr+JpR%+oRZ
za=;wrk3w+g9G9E&cw1O5$E2!MGpj1V%$I+A8%BZ?1&!##Ek6#N&)+CdG?v+|T4+qo
zaLqBixKG)vLzT+_03^-r`5?20iS441hB>RB(d}wfvenv+ShSH_6f<?1-UU|4izT#6
zeu~x}P49xLrCtvkYeC6MG1tXk{WF9S)yyV|`wudOEY?eG=p+_Gq6KFQV3~~YT^h7w
zi&L@_;mTGn!Wc5N?$SmHTDM}Z(Iu|byhwQi7=0`ldpF}l8p&s$c$b|{h94V*1jtz0
zD0)dGh6!er-4$DN?_jcfCcO~)7gIJdmIF5tBYwa?xL;MM30?zLip3v-3UoCT2!(o|
zhueTmMQCGj3PQ$rTOq?iF%7z>1WDtJk#tSE5WIq#!IaWWhPPTCW{WxrSK=t~g_5QB
z@{;8NHil;>k`+tv)6%<)6>TKb>DMYPi{)2nWFw!H<ZSX(ggbR`A;=~iNr$<eQTU;$
zR@(>oRGF1@oW%b@7X-7^az6+P%wNY)SVA8+xnVAug>{s|za9M)%PK)EM>ck`j^yHi
zfKIW#nKXM`rk?LbQ9mQbJtGlhu=kCSmV*tm%O$OAj1M>Deg+O`X(2rVmCy@601C#J
zS^a)zEvJ=B7aEx;j{GRdoDL!&MP5X-#zMgHL!K`5#5X=Xnf#6on8^YU6U{&i;mC8z
zUk;g~D@RP{cA5uZCc<-r?8O(~Cz2)75FIoK?}!5vc55=KEWVklpBTsB9Sl#7br{Te
zPfwGs$s;g}Yyy^~4X0Y@m0R#P<cV1W$SOd~Elyx5aF@S5@vA^GuG7edhazr~#f5_x
zyUmiNhqKA76Xu>$CHgJjH#(>94z17FnUhexOK*4>V%FrmJeC%qnPc#X?dl%+iZ2UY
z?}<SHzWU|&<kXDL*;73ucG^7_m8RV!(mDiEN_-;?;IxF==n89DhKvD`MuUtnEgzg2
zR7gI!dh8GJ1oxd88ijrt1=qOgk<|fgOum&9qJeg}CZO3QW~z)_BeI%8U<`wAtKgeT
zAzK)~?~KJYCs@Np`fB@EZx;?eN{}~TbaU~=yMB`g4y9i*<je)m>76FuWZpSqqSbJ^
z>KbHZ<Hd&Ax>|m7NLz8&l$Sp}N=#3N@dI<_3>~`kLpmRTN1@9BB-(+AJcZ<Unnu%N
zuvpFEQ$a?j-Q{^x9VF+$CW32eHXS)mUO5=U^adpppd(_{BY(2r|BZL;jiO3x`kwh#
zW~DzJ#{H-<-Ky~G?$e#<8;#M))>K$|uy;CIZrW4*id~%gt*1cpH@OvfvDR;}lsj{W
zJ`q1v`L}Lm(ms6SY^c}Am62(14q2AI1Zk)u6?YJD3^*OTI)f|iM1}0Qu@M;szbIyX
z_ZSdR^Y4CRIp;K-k8Fth#n$MDThX!jPup?Z&)w~YQ+HQdJDo$<1sU#9?{s!Q;5SDc
z>rdN_N@Hfu5A|~mdv#l%+oYOv_O`}@Uh$sk3;tbtUpSQn(|$M^W;Ft-8dk%ej!jtI
zz(bM_lW?+jHTh;Z(@IV!-&}Fy1D#WGuvYC08_zh&3x9A;U?nkuEPZ$Z^cD;Mea>nh
zcy3qdw#STUK5tSa&Lq!YaT#Hp$+W#Ee(t*dGI?`2`{%7aA*R!`Z#?caGbu=dMUP@Q
zm?be{<$z~naAh%%mqOqZUMZp;!?kYSwC{7T@sDBEVV_NyU=sZq{fRl}@#@plcWM98
z)6sb5xd(PUwDiE&#-F#3{cuFJ?*FlF|3!{Hqnl1+=3dXKN*+vqkr<~&`#*gybKm~X
z@88hJrtSPy?zO!bP^U}bOcd!H0hM+&rUtIgj32}9o^;PQU`Q%k$wH!_RN-VJmTEFj
zEHCVIUsAi5emF9=aA4;7o!R~``rVacb4|(Ks_uLF-F{&e2Hdv%DgyHoY`EQS-a6xE
z+W!Fyx1Sy9e5SG{ZcZI<FCjDC=9>7-{gDwA8#B8xlRvjR^GyP7%tx1VR<o$4mR6c|
z6=T&CMbR@8t=YuT#`c7L%TGFhczgi<8NxH}F}wf3fza(g@U>EhlnK>rSQi0dtS@X>
z)t(6G6sD<EofRO$YEG_d9|(;fj#~YxuN|?^0G8dqjpVUtDj&D^>Nsv@g2tLQR;vHw
zo6N^mp_3n3010jGpkHSqrDpb4*0i6`onPuyeei;l$|w2-OAtyJNEbLe+h&Y}QHGf2
zfVhMY*%imSyW@dUEp+BC{$E97J(;)w0u3x``qsREhw(`BUF}yQ<2i7q{s^=;YBi^7
zU?wDSGpR*(d?sLQOt%>>f9w3}<QpH!kAzdd#sDb`H`L5ugCRYiTXb9Z2zmi$c}JHb
zgiWP5wG@FvJa^-oHqcqvY3M!S{2C#ODNXifQ~+ALzlMym<1>*J6iu{Ezn@=q>>JtO
zfjJ}m9N=8Tnauk7M)w%Fz#8eyNaxpgAG2>9AxBaPg2TdZMyfIMt!AeEya7d&h)ddo
zycA|kltwyt&CC%ys$?YWDI%2Zxz;h81>p8BjgICl`0L0ef{8Of`hM0A(ICzK^j4iP
z^i~tN<Tq^N%(d<3zj6Ih`^+>$KRv-vLQ{g&0CV|~mbn`V*?Z<On_jt3EQeN`PnTpZ
zHU$V1#OENZ5mZaSC7dfM3k94S>G;No&D^QX9<7aUzhP$|a;(?mOHNTgG`Xrdy-UZ<
z>4l2foGNd#TT>s`?fK8WtNka_!PNHvU-o~_JahlQ!8F^pn<e{vWe1ZC%F_JB9R{T&
zbh3Ll7|eHXFyn80xWK9yv5o-}Hg_s$iTM*!VZp;0$o5Nv;RXndFpFGfq(k*Es}IsO
zHCGXeCqjE^e#E-hnRnD%qod6=_x<?Y%?Ey=V20erZQg%dCCqLew|4KQ=*##1Noag`
zr+M~&pDDCY<3@i@b(W06xh0bsist)Pdq*yNI{=L91i$9KixCRkwf&i$#sC{?*T)$$
zPaETj3Avq}1C61BNZ&59su>@(o6eec^r?(Lp9#*-WrL~THST(Y?%hYc?&ZCwgPHf)
z20?XhpRC~iOm%Cuy&YaNo<UG-`XVJvtl%DJ6)=^{`UELKfZv{JuXIMtB_5s7k}&F$
zO%U93sJ<^;%NKnUCc5d1f|e!&=@)|IOwZvp+!VE|XJ#5_t1AaUXnx-D!W&0>p;Np(
zCi*sxB4krcS@qmA4Wn-vOCj$Ow&0J3(I!I%Ztjd{1Zmv#sBO$+`SQ~5hN#X0wg?hL
zD+&EVn~@`kk;d|A3hdypM+dD~zqNBu_&1Z+`?t6Py<G2)eLh8EKDO`i<g?Y6!r6U~
z_rFm6=l=kB^3enTc?jmNw3WXN9bVAPpY2$1-VVY%CQ#0g&r}~vv78@=)fD`g{4$*p
z4Cg~%_Q&1=)cL)a!vB1CfOJwU=X!t8h&<5%2pTj3GV~8L@^??a6A&6S(zqwZgFs&f
zZ8Yw=e9s#=D?lo8)2$}Hs(1YBXG-?YQ84g08UAa|w3;o-ED&15ifFONtei+O9JUf^
zVR>^59A@%rc%Tmx>U^aUpfdSFHvaZ^R`;%4a_q{BpZPnK*h1xlqnom?EAQU^_olDh
zw}PhNw61ACdOAdD=r`_F8JuJ77)8<*7KnQ`8|9jb*~g_AH|<X1ga_>8kX^{CnA0jA
zH<7@aU#zSe?)em28nF(l1pS4jvBnR2p?bxQquK6)QlE^IyW)~L$z?is>F!62r+^+}
zV+A!C!?4{z8$|sDzKB3m&=td+rP>JwAs!Au#%>Ldm3T-2D^Nf)IcuEDL`|vE0Z){3
zzLh}_D4CJrPMV34`gDzpH~tEVNa9jXD&d2?%6<bxB+sJ`z9U9Pt|`W*7<OSC@~Vio
z-$f&{@BoVWAWlVIluURC4!D7WCVCpd2-!-;_ha|Kxx`Gv*|fg+zc$-N7N|q4i4%@G
zky#OUCT)VmSRsf9uVCaHkVe-mgJu~T%MIJO-M~EAGJ-k9&5%&3D!9i(9Ldv(ao27U
z1kj4z(}-CHH=$8Cy7s15sdWX<h-KvX%g3S#%C{IT$d)&;X!E|2TZ8j5!~NYz_=^yU
zunG=6Zerw$g~vg<MyP|HNrUdr&^MzWZC!PV>&<4EwNI1ofci>YK$b>vYgl0f(nVuF
zPyx4z45Jjzp=&fin8+hCwO>4~!lFg64209gMALz1BGM!;S|(2e!!ZFXfiu&JC+&@$
zqx)8*SCjT>r|<mfKU-77Y8jn$*R5IpPEL)6(W*k!BEWjuc@XpCloOq<aI2_27A5$C
zOJ*?L)3|k$ToRiR@s7T+(M}-JNFMp1r`<iwK*AdannP5OD3kaJGzq|yjf>R<m#0=M
zQ1RzqWJq{gin!#i4KVP;Y8wo2pfYh=NHB_)Wzl2^o?&c<V~|oMP6(E<$50Lqc)J+?
zG?L&)=}O4LAASAZ&YoJZ#;9bLZNC(Dk{ot@;6#rQJ`jB@L_IGtXR}NO-CfSLOeg0M
ze-mWNOqnk>)*!CRFU7!t;qXrUad{1D7eoLsF|oSz`!1ILTi@8qGIDdUp+3{a<1k}F
z1zaw#h6h6>CYoE~E>*g!4e!eNp<+wCdxl#J$>5aenqd_Z`{19y_a#z+?9M2KqIl96
z1hUg|4uSWq4zj0ZbYh;KwHCOe%8Cpv8V<w|Svu;Pbix-rP7Ysw4PQf$yr#?GLpb6z
z08SizVSIH-h%jO@!!{E@kOfUAgsUKonb@fW#SGvirm1#=F1lxZjD_xs3YF1~2~v|=
za94R)Jw!s<U`X6G$bQR=V@$&FaBs{8-R5V1;XRn^aK=nJRMI}L7^BFi*Q}jsFYPS1
z)bN*_VzHUBmgRsgHsFluYu*vp-e;1tT~n3JFyWJ|@uT0&`p38+mN)$8F>)p^nU-Ms
zsJv&DtxeKK+Mc1oHZ5-88X@->U}tIb=>?i@rEN)jC3t9Tmh82g|Muq?D!~Mx0|)$j
zTE4*z7;6aC&~eHM;oc@K^C4|rF$d+!!Ia1gc^;7WfZgbLhv5qS-1J&Dl(>q7bP1*y
zejzL6>Jg<k;w|@^q;(D-fDz1@S3JT`4+%MnrH?{aE{YZWA^NI*4_ta(Hcpb$F@ZQq
zOhYmQ172s$5;{Y{4n7Ehf@HpF7l7^%GyS&4WyuVt0rQ9NhH7#Jv9)hyr2R?wd>Nwn
z()+RJ(ZLhxQ9!^d2N5QN_kcI8wS9GMa$07I9%^PE0}leogf4?BH{;F$H<A4^(l#3O
zipSxGJPv)vYv%mXAAzFSKZgWbm!T=#Yc?asU*6D^5Tmq_K4T<vT@tClgAH1y?}NwS
zuUra6$)pMc$5&~b^-SY~`88x7Ikl(asNn8q+~f#8yy7IzX~PNOm7SKXnlJzyn(@F%
zoT*+@&Gaf$KFzNQ3182#nNia+X15So7?r}_tQbydAAI4PGM22}9i(|h2>omX54}6K
zx4Z7+>cBZ4=zZsk`zhUVe(A!N`00kT>#5wk+cEk@Khuw#bsxU_5ImPC8Ah39?4MEY
z&$rY}wLjHLd;&{-)|&PoQeI6J>&|S^3nMSg6n(Sk&4#W&2q-OS6M4*N2aN`O)8xOg
zg^@D_kBL#VRnk99oI>-{fQ;auq$2<PKkd%ci3@S~-!v1TlRj=vJex_5ceZF=I51GK
z<9Q6+X)kc8fdwbG+!3*jZ*=CZky(%veuYNv7-<p=c<Opj2WB|u*z1J5EE&micLDmr
z=S%pck552dI$kph*8tlr*aY?%@zbAd0GXVb=>&JQ(CGv7<(Z|Om}5eL5)ILR?Jux_
zlczuLPpSP=$L3X|9);r(-1oj}$J>;sot<cld*5t_++D1!TU9so;*K5zG4cI?oaMwc
zCbPJcb5se(Yt9}b9naYP$k?>1l0gOh(sG|_#Fd@L>~HVyJWqrDpU2#u4d0{omM%T_
zXAl-3=~9eM7)OEoU;!a35e@QieOUzaMK$vm6`+#oMs8-~JX@k<a>dMzO1$JZ7UwgB
zniLr>48sgYA+Zu^{0LBq3>z~>b`bWqZb#U~O-JC1otgGM5oYfZo2~>q=uK!|{PR2D
zDt)(O$4SAA&x~RR9v~+XF(bjkgrhM0Q#{Vhu?pbQ^A)Vn9T|8@aDPLhNYu_SlbZgj
zspv<eYz|<WE9?Qn7HXz)#G3YAKR5F&>idlRbNh+q&aah@k9NMK)rWx0)V<31{$EMR
zB!LPfDKaQPGs%hskvu~;WD!b7X1ts`J;%xW0Yh4qHPR1$EEKXM*pyO^7Gs}hm!IK*
zu?o+?n3g^S_wR)SGVNPt3AVy=b&EZFdhCcj8JeHHIqP?TKMFRG9Cr(*cVneX_z1$$
z>|YC`X@61!&(9Ozb0%_BwkeX9sE9Qq<`Mftb_l{Vi|sxVPB#qWW+Fdj8B0*d;1z2d
zbxyDV`45u}rVe0ZC#7=-I!pSXK+b2Zhjy(&@N!!qctZ$dW;fAbI2R!d2fjt$m*z9=
zSLS)pSr#`R1ew=SQ6%yxBCf=i$6_iZmO^f4NF2-Hl^|5o7xHU#fd6a>w5gRWxFgn{
z<;W<)Pos<f<44<mGZPa{XwMwjjiJJdo9-BAh^>LOC&c!g2I9%ITaeVuF-R+B6e#MJ
ze(2BpCe14W;4tecy%b755cicy!10j2hCrAxPRRfE-gyY4V#RHsjlHucA#d-}sPn@S
z?_6XT7v0ysWoN$q#M<VAtx7nvli)Cy|8!@%n#7&J{f_L-(#)J~waoAgq1VlfaFjF7
z8siZPE>_m$zOy4k^O=)hG@2RxI$mr8@)u-fs$S*(5<bCiU*H67B=nT|?3scr-8ybX
z^ORYph2Z`jZV_lS_{IOwoqc0I6Bi$hUcV!gY$e>nCM|~AdPdXCokLDKg9sC1f*RTd
zV{J!HHL$b<e^i{z$wae^+oy?ICVPchXdLo5`%_rqn9nG6Ls;(oK8yax&DR<kzuC&f
z#Epzz8$8&;Z*)=r-+PwOVo<t_i0~01m_rRD+*$Dsvs}baBrG;Nzpv3^0-tIaKJhCF
z3&dg#8EUp`R<H)^+aZsiLK?i07I_$=3ZL2$%zQEoUi);Ga)QR`c`L{`U;UfxKM-2-
zvr!?R{;v^Q@((mJjOW<?jm{vl<fYC#<5T|W--}Oqdn5mKB1_J^JyHfN<7XpFzWPL_
zheQxS;>tha<*9W78yj%3fi=lsr*44~QzrlA=nnr5-ibz!-RKsVaAOcpAh9Lg@Y2#5
z=I3V*{j(qZ1MlGiKRt#Dp7EoX-nE1#Sjgl;{L?5KeN*h>)a~z!T8>hRg&?6M8NN-Z
zHo|tTib8UO34;?C6MT-V$|wx*8#>})!|^JYiJ>@gcjXd0I~l`FvWb1)#%pw#7-7<O
zkyJ7!Fzh((S17-UB5di17qg58<S3yyKy(9j07cDDFJ;IqY!9&-qzNv|BuSrl#uxtN
zS^;9ruzifS0_Pf0#jcGwgE}c+U!hNd#glP1tGaf5q)Q&%3Qc%%NX|+6F!UKc47Dd6
zGT;g{*W8+}HtAF;Ch87t>-+!bwZq={JV0t%Aa<8&oN0_1h}iIBKkYI02n*ijzi59J
z%?|V#IwV7v{y~Km1J%itxQq18&=<e*bvlp`a)Uz0A-{07ujQF}Ip~{w&OmaXVP}Q|
zBA;J9!n8etY0&dBDo9M@;{1pF#L&kQV(_^Wy+<*^i`rLNK8NZ6)#+Gb_=z-4<Ba`5
zm;6dh6d9Ujtfi|5T}eqd6bw&*ye<?Q9dslJi8=h}|8Wg!Y>rUo9HJ4TVBVm)!DGO%
zW8_<sU@S%42R>FJboUhpyozVcHF_}Z^kM0UfIcO2FzF>TM9bWp050T`5ECKV;)EAJ
z^jiT>B<en_p8KS)<vl}}HSp~M!|@Ww<&}X464F<n<m!u%=H-4oHYCa&FaE3afqmql
zs0W<OghNv-{dz1H%A63%gWjFOY77b^IQ-lgE^~%8?MoPULuSHYoQyv{LvH{t!oeJ8
zq^$&VHZ@nE3f!#n5eK##4Kk=#4uL)r29qQ00>1-7cM$pv3BUfZ%=K4^L+;Ex4@QvP
zPxO!wAxnJO3<WeQmk&orRHv)APCpLicL^SW2a|nFzsS{t+tS~5HTGkT)~H&5>`CGa
z-;4RV(x!Zu8wThD!<U1{8vGtu*FmOa3L5}hzx4crTqa+ZhUB*Zhw@F{`SdJpH=s3C
za>#P9dNm5u+ixhB3!_NKXfSZO%*E&SUZIK9Cglc_n8dg+1nGdu;HSsWwng_b9Mew+
zJ*IKYVPb^jKH=-@R<S&3kAptbA`6KYX%)>!W);g&RP(nT!8_h@LZ~jKywr)Gj!1Oz
zBflyQp*Xz#n={qHJ4r+uz8W^Bd7NRx@(t>wr01g)mW=?gppTF@lJot-Z|xX<i&05f
zR$MxG1m5WMXVAFlkCm(#sXnA3)I+Nki$YtxVpe(AWgHl5QB2`COeJU+X)3=tU809#
z9Sl3_lW>vVwBKM>uXgt8aMRTP?;)arsqBUeHR6AVSH@gU<J#x3Q_c;w0Bgy|SI0qG
z=T?T6U+JU_c|7Y7*2Vng5NnVhi=2T8zwis0a+ZrV(F>A!mfAxz)#R8j<emTx_{U<Z
z7FFdP;q-|#EO#6HO*#Gl*WT3t$x&SA+11)!P6lq5mAn!V?Jjd<b^OSZNu1ySv&$Sh
z358n;1r#|p6eTACObMsTNs6Sx&M_xeAXyTnPzjEOPChD^5ReQCp%PpmBgzo$AQ8X>
zV-QXiR+a5AS0yKuf1-R}_sss>&g{<I&f!&VTe{uZp6=JLU%!6y-s{&rxWpcPj5r#H
zK+CPo@gacL@gPDQ7zsUfIEAxo61!8GLx_soohn>;G&S`@OvlnFn4XgfT*`-xp{>R-
zPJI(ls^gez<E6pUAPBi3Z;S&Z#)U3o%;RDj!>!7L0icPqVGJE^A%=zG4$K7>K-)M_
zqkwhoWV!&KZgL@bp<pc<EJI5~FZc{Yv;02>&2f-l2D-2zNAn&21(@>`ASjBjy8oq$
z`~hvY_MZgT3z-7C%>O2Xr3;0!_?<d>!D%WY<i_IX6<(iAM9oAlwG}4~491qG((&83
zZ5%|*0eD><z;guF`}0_48{4q-yyDTyx;&1KfI%MXkFLxQKuw2wZ=jrpNOi8ImbT^w
z3>>16Rf{`|@RALSBG_QOZZr!?20{G=RUcmtGkS%N*b03}UB3GnQ^78Ts}qOIMnavs
zE)63=#4hwl5voBO9VWWg2l|W+FNVnw2Ss2aBZ7ThWderP1iK200ycP*|7|NstnUiO
zlliJ-!V>JZAsAoSLAhRsQrI7(KctY!7SyS!XJN*#t6&bQS@1SmXFvsHQ)zOn50?aw
z34jm=v;hL4aRXKi<-HJNFlTIQt27BdWQ%s&_?AM*ZXRo`>ve`&AcCNvbL)t;{xjN&
zQFIXw8;mqMj)u{95q(R~KvrRAxfo3{j13Eq4%kq1y9mT`obR$d@(6K-+2=Gngk^0V
zbb<wEB2EC?JTURfNA*JF?60zrn#IGL{t)hbfCH&Csj_<lKsGxTSE&}E&ytKnAko%j
z-%FFQbVzmf7_eyZRl7?{7hti1*f^68b~9Y9G5o*i4U`mMG0dW6!PzP(AmdKP(!)t?
zB%+WLNyE$%{lk+Q0*n(-pv|TvQs^5WWul7)yad0JLZ_k4>ILh8Z)>0#S;_u$#un`{
z4j>DHsepoBqW^3X8TiXmrg3z$>?H9JO|kpzd^v)Fgy=;+#}kbW#TbRL_$YSI?LE$Y
zAIgzR1cVeT;iU@gzax+^pfEUvhM`$X+O{!(z{AD1xd8&=)Iftfix_zIB9mh~!Fy;)
zH=;vWsVOQtwjX1o&rs|bySuV56g&CCd=uyR3?ptFZ5U9_#^RW(aqamnFjT31s?f@~
zz>Wz82y7BPH8IZ7EPUYFhGd@7R0IqF8!#Qp(1E@_PdNh18p_C;c=AegHBR|?ARFBR
z8Y$Z%7<&UlY3?jC%I*;ptb|^o)ope+@w5kEe82&~rogaKEQ<CI-$mvHHlQ$W;o3w`
zL0b(y#q%C@XwCB>2VGB_S~bzU;{U|KRbq8~^581(75|wnu}|M~;d7mSvQ_Ls6%)B#
zLWD1PFZTcC^Z<s72F30Vd$E6`T<m|Sw%EV@+kE_U8Vgr2L`kbepO=%wim~_s22zAt
zlmU|~sf$*NT>0T>6?Iv-#K?-Wjk#I-r#4JDPP$-q8I7tm6HMx`*yX#JB2P6i&Z~=k
zIPn*X4-hjjIl&6xL{0%Y1Gvzm@Il?wWEv6d<p}>JuAf37phPu=D<33+#ya>7_b<Bu
zXcA#Qv(W%%-Y9NE-9(ETR1okzl5Kc^Amzx71!z|<NLmng2%)$#PE80}Xx1E8%`7vk
zR*^s)FxUkoz;K~mCZfxmZ@=~-C6~#MR-$`>h)B6IyWo|8ja0R%bE7x03{;9?rHG$J
z+$;8HW5Wq8qFi-i?O9snthL6N85_Lzu3zuFYIKqQ9~b9hUqVb`;pR=1A>-wLjqTj6
zCzl>f|7JclwmbW~?;LtE_u-OZsMn+~y`_-4a9^r`(k1n`hgVig$qR}L(=SYHjVw!;
zaXo+6W2r;ty*DLNm!;2Nm%r+HQ#-U`on<EQ-rwP?^Ts*%6_dNRn_DC2oJj80zLC!@
zdZ%!F^uy`p=NG?k8u8TU&s(r5Jv5m-QhX>6Op3946WdLr{A%$ubz3gF=J;J(mXBit
zhH>}mr7_D$pa1-5am{JFFI+K<Ci2=}6<1bLTkl(^tif3TiNh1v&Yif}yl7Zilr7$5
zt~o7rVJ<e3K9pCMUSiHtx%95$@7<Fv{9)o)@%7Qzj(;Ybg_Er7*U}KtsL3192np3@
zAzFO=#XL=NiMVEFW6}h72sti3a7NKjKWfrsf>MQ=P&0+*-dGF22+xIKWjVpLxD=8?
zvGQjF$tXm(i8Wr6)4{Gv0B8&;%MU!+h^)cu=47LaaB4^&Ku#+!ZJ*D{KA~WqDdKr#
zU^44~WfBHvvqNpbMSn&km<XJ|5_mbH$_x3aV-XMqFhL5+$ihBK1(EPPbgq~sV4?{o
z`%C_4{&dKIw?FQ&)fJ<mlyCvm=RngZO!Uq{4UgXX0>DkAg0lY$F`CJJQdANx$VZ;|
zAyXB7{$#)0lAX_CqJzl#**73bv$nlct3aenqZ-sKj9eB7q7<^SjW%$tJUvUWYUqPP
z>`)R<>sY3M1Emgb>oZ3QeylhQ-$W6^P5#xA2t9%(g(YP!@fuFos{>UB*}1ftfo{pP
zj_nFiwNlnE{v5X<W1+a11Pv<UNkKacL@ebXgN5G%`P?EyX+FT4ZV4+rF-p#7Qlt@m
zL;bP$F8c`GXE3}`1HB+vewmymakhc0+Q_+qWu7knlZ(p{{`l0R00X-a+Kucn9~=NP
zMxqFatc8?S<+s}>aV<cf#y$8I@dcmAh&;)Ilqg~K19SnlcnV?8;Av;DHTWJ0*bQPe
z4=Bn6lzDyUWoMAas6URHlF#ti1Q0k9U>$L;lPSfQ?E-K>G=3NOlOK9gQzPKgmp;8R
z2MrObA|P|30c%jApEJ<lh+$a8%pfJ?2;*XU60{%zFltznPMHyeU?mHwU;IFd7GTeJ
z)0(V@UVz+eM#OuJ3o!}EU`FpG@V12;Uexm5ywUM~oW!0T*syN`Qv>@^$W}1%)5Y}a
z==gXxo1HKqqKjDmM?q6H$u^}NlnWK}2~5gvx+EPw$CwVmB)Wn_^iww$7BVOG*4^Zo
zeFhFmM7(UexQ?C&>PAUy7BL231L9UOYD|np5mvPU&WV9^pFs`+%fmyY;xIxl-UqdC
z(x=`J*AycTl`EI0)?^W`wkn|`gy2Me6WtO941YQw;*2HWpJF}~RUYc2djeaVa6+p5
zfaNGlaMIQOyL1*KVY?*gm4L03h8u)`H{!gi{U19M(|YxaB$p=FRTkWo8`uSlvov`(
ztO}U?%F28eu8EDKu+ZVZFh368#A4XvJf;FA$NGfZ0i()b0dzh-&<B2l(;-_lz*5pB
zA>s%a3d5~xYgZPrgCnN>ksgDc6uWxSGbZHNt|2&qhtzjII}h##up%s4nyMNsR@#pn
z{~njT&XNDqz!YXArrm}L7=oe`h73Mc{&Gn$Q?aUxW_XN)g5_J3Ie<O9C&%W~21N(}
z>~{XuHy6cD0wI=x4QyoGHpVbvP>$H~3(V%4V3{f~4S8aNMtfK<zypGXQJBSVjwqw3
zBLUR6N7J6&lMexUV?>+;ngD{T?4fI8x}5546McdaOlQmDwJGa&-k|^zkYK<s2CnEH
z2a(WVc58S{h+dmw`5G)N$nH65*g6}_P`WPu8k)jMAF-2vb2{OHKpYi>LQLWZz@sgR
zIiw5N1FSL3*$7@0QcN^Sh|P&T;ef@^&=7n@3-KG&yZl~wQQ?q)gfRe+L%{|x@o<a;
z{xm#Bg;NAx%P5A14hDD`*r;3LE3^Pu2muC_48_Wc*nw0c_TUqznSfl5zzoSFnj*Th
z$gzF~(hWUQ_;68hKto)m{j4fSZX&yy;6Dm3$Acgo3qppoI2N&mUqRQC&zKoJMG!|{
z(yeFTgpg;j8mg_sfJ-01=jj75;U0)%Cz;Yu_W)P1(Xw<L;Fo7ZSleb<P!H%T8O9hV
zm63PnZ;^r}4S}Kz+(m6e;=Y=$Hn<GH0rZS0mvD~&t^YcYf#|Re7|(6MRrm)S#Ns?$
z$v0E3z%N3X0)GLd&C{Ql@3N9^AJQ=We1$=tvv9}H8Pkv0{u54YfAyS(RdOBt$%Cup
zISp4khdq2b%)=gTnXP60=fs`|m&Nq&eI-MEgh{#$;C{zH<W*PLMZ_Yh9VGqj%7)Sy
z%bBMGe>|@OHpcmQe5jcQ{Nq3mybrBPm0;_A8Jyc931z<eOXfjqQ2JE{pJEafQd3VX
zBd7^&HR^x>1V{A*Ggp>3Wyc%wcOga@6Do(;bj&pELyGd<vqg2f5#hrIx=7Hd#kcdp
zNvUYXnDd*z8cXPyJ}d;^salA=w+9DZK&WtVW|lPJ0B2p=S=RVxc&S$SDU#}31piJe
zBi}qztR1eX$nFwGHZUN}Th_^BBbkV`<Ws<i2Blg9Y2#>0$hMD02sTAL)MUOKdR#-(
z=cB2BOC7W<Lt9*OGqM^}06YmvBr2jfYCmSZ{XPa(EUr1X1kXv`nOP9*G6@E#qUPiR
zGo24Ld>{c|E%qYW6G<2&@=|`9^*?Z3#NTK&uht~91g7N(FMlv%vzANayzeK$?32Z`
z6VEQxa)Jp7PSOsKxGeN))ej_=!6G0uQM)wO1F=4~|H5k;*&n>=7aRa$jSWz3Dk6Lu
zr!*|P?F`yoNTiHJw0RzSw}CN{S}SP@wOQxz=ogEygZf&wYok7^^|ek+nJ~^v7Jt~m
ztaT-~yFf>yN(lsk9EgxgZ31DJEIqwSJ4fo^I{-NW4UnBCAAIa1^3rs20)IPW4Tik;
z?pkf9>q1egWw*F;*pSnP69=!nxjaUb3&}L9!whLFjBaMPO|XXqKWeawFgDx(S3ux6
zd>kj=o%gGG8LvUX>#!5wUqSoMUlJiZ1%Ap8*g|N+{&(W|bL9>D1R!AVfTWHzeKvSC
zR%cnoKozipSnxgft9**l4#MgzR(|9HuJUmcwhrwGbwb|twvw<uoL4k1`-)mHs4<U(
zVKo55YAB{&sqZdAfh9-;Ic(5};y4*koqCZzcqA-?ISER#93m&9#diryTa*yc?eHz^
z7$phi`^W#OC9zg2lg-xbiIR1=s0C1QOYjZ>3PVNMVdcbn-Fj<@2(qcK4uqYtsLyu2
zE`bjTnzoim{p;6T|32lchK>nYDQ*y|Uu2;`!yq8+0_sBe0BOvg2XBCW!Bhk5o3f}y
zsQeI92QYE^&rr<z>mS<U(IjM<Kv(Co-8Uo!F@?1m!@$AF#cz;x({Z5yLC7_jB(N+1
zaC&alP;piB0f3ARPNeovJDQtK?!JtI9YkStu&{-sfdadwn%x|I+klMIEEgSZH3AEu
z$jwA_>svQ*xsna^57*yrXKT53p@cao*HY0Fm{GVs2b8iN8)#nF#F=s~yMAZ5B-wI1
zbahEG(Ej6D#KdJ2v-w6l2K0G9gP_do4%Z6%X7E~-hAZo}<7K!snS5wgWJ;IB*$uq{
z8hN^Z>hYWqJ3(f2Ge}OaGWW0@`!1%2NXSy{ORq1F9_TDj=>~=T$$#>y94sGwRjiF)
z5pp0{P507C<-sXn7*fL88+t5<l^``Y&=fjt5+ocCuT~!Z{Wb;t-loxZ|Dz2f>55wh
zu^#Oc2O+unW}b31<0P0v2uOmkKKHW2<09a5#$ZLo<Q0#`%`JX<;;WsfFR6{FuL>;+
z2@VnWL+GcnEP<sb8=BFg)z-HhhCFsw%xqmUz}+i8%a@;v<RKoM+djTG-+Jb#k7E9c
zy#2N6%B{Z&ElOcHGd7<gj=EEh%S^5RGe@#<v8%&mJ^r0CQ6guI&D{56hdL|Dzbq$C
zNyMiq(C@c<DEOW$C*C%JYZdGD!|cDX1ZoN^vu2b=zB8Zo2&v<7!doi-aX!agAlLCY
zDb~lZ&C`a)i<u>7Z>e&_HeqvjNHi?`h-5wYr~DROwS|qm5$w|ecVOQ<B352o5vsRO
z9h+Kui=ulIQuD@x<h(V)%_(dI25;GVf7R>ns=~Jc&oE1&?H@b)3_eyUFjIN35tbnu
zmr7crS%o73Oz+Vj^wfEVDPC(E7B1@i9be3d&_hf)BZO)9)~41xoNax(?k=?M%U%+~
zwk~sKm++EgBFdc)+0)M*NS%)9UZ9o>UOV;|XA1TO6Sss~tK@NovpWFp!CNo~MDjBR
zTFe8O%s%kbs-DnP&OiO_sv~cBW2QENmwxW%Y$s>)@=z582W;oxF7JPvG0>VqDnPhU
zDFA5eNBIDy+Z07F`HT%ErL6D25DFjxWESb)8Is+MSZE5oHudJMosp@&Hb~aJm{saA
z?c}=u=%a{fmmYXmZJTmEpn~pQW$M3=cY<tV-LQE&tkKpY%l35S0cq&wG%?(8FYu3$
zNk*+7?BQ2Q4p7uufVUCOBJdkIfdVfVG&u7;u+ygY;E44Z9V6OxesgRl3UY#|y9eJz
zTQ}bb?fI>wUivzZ`>Ibk*`=Bq^<lACM<-=d(wsUkeeZPgMktBG)gPc5PW75|6)6ei
zlarpn;F$MN&~%SFw|@&gZlsP!NgvsFKH{^V?O~N8n}>M5WVC%zA0^V(Ya>32`79E$
z`1IMTk77N<d=ROjNRMI-<nZyM%PBT14|65G<coHgk`D^CE7HxXTsz$T-|tdBDMzgP
z@AKb_b|pjXWm36e!Q8MH+7Z?N{Se8o%$aE!n$q2Kn)&BcyJXigS!(klsM{f>Fng&@
z-M=d|j#aF4A1;Sxqa=QOk67@ALnAcTnD^eo%{$HrX?U;-$~dI35`=JQ12lI;3Jv_(
zQC4rrMovxO+SDsA_k3pc2k|t&btkldRjl=Pw`2`VJSjaTF(@f}6#HdUEUZN+<@U$B
zQ>~jbvobW*h`MV~w)8HKDIOY+DIrJ9hNqz)*&oq*tJ>7|LmTY5B2d6Ly+v)vkB0cz
zlVfMN9DMOXy+Y!kJZl2)t+ZbuQD}UH#Fmz?ka!BUaR5h{KwM6}7@0ghw5itBa@G6M
z67bH9d=XwD`qryIk<D}ZcABi$zuYMZQC|ci9C^(S7BxD9DS`p4?VqcUZs-i6weMtS
z0P1UpY&wYEX6qZ6@%7V}hU-5IYnsoUII$TIT~o!7xhxZcu#h;qgdsH{?>hsMv3oHq
zheorW8(o~^W8Hr!G%bDZ$P_;3vHo%j#-7e9<~=w12j)hnC(BJ2m|5te_3r<MD_MO%
zZQ2!V{mk_UJM{v(=Pa)~!Sh=q762ZV%`0A=dwaS9kjSNIXyga%8QFp^IEkzf5z`{K
z?ec0Scz%e8buGnuhy~({1WVucNT51ig@w(0WMO!*go(`yJ_>E6^|{xfMZk3H=CFiv
z>zEhG1LvoXESwwba<i)Cp1Qz$`uPW{p9h$qZPfM~w#NbhYh9FbwRH*Kcd_wne=uM;
zk)lPqVs%dqZb2TGTRo-Dg(xkvK(S0%PQ<wrH`<b<L2h=dtrec-z$4tP`@@ZNcJuTE
zp?a+>f@UhUU!7g`j&Bh3BTI)iK)pbhPQ%kr-P0SCUZ6`uv`jD1r8D_ll}>J8T5IAi
zHH5Qh$5r0vqPf&*nbqy8fQWVJJPPE$exoH70^OVib)UTq%nQv(@3`DP#lQJh;GAw}
zjKCdotuPB?>Do@<%pPJvN!HC2>$%XwGwsM1-8|Mo`PQ>MB=D*0<(^f{doJ{Db)kDQ
zv$!$mbP8_9?krutsI&U@wd<s&QJ+7fYaDYwqk3+Y<{V$R5g|}sk79wyg~C0G^(f{>
z0SLvOcHWyEZmiKV5AtMIb=*@Icuzb3ptbY1+MMPqa^={$Va25QdffU$ijy$8|9W2?
zXgOh>n>|Iqp@iS>9>x4p$|*;Rg|!+zcQ$l6)a(4a&eH7|SXXj?m_g%$LZDbE3@g^_
ztToq{!wT<GdV55j0m_6$)43BeM+aP|u`KR;OnXNyehDuJxj4O}@IDS-QO|!rZEnW#
zET`ZL#$8`e((z-%0nnXCEebK+KlO=EJ7{+P9nv#bV5U60rE`QF2q7T`aKS_E9UNS~
zXAVs4@?wN*Lpt`!|6lJZ5R4%7oceBBzjk%~&(5yH;|#n#v$st&;9zv6V$D8;h8Ve*
zXM2Q}!eUr4w>B>d&)w78Co0CcXZHtYb&%{7c6D<b$E?^Fy_X1n6E8z-=SUCDB6fR;
zperkj_XpPBDZ6>5E&Wfzb%4~j*nB-5so~}#)to!O?uKyncA$&U9+YfVJlpbt+V?Je
z^4|~%9V#&IwgTM=pJaiW_bxmq5Sue+FL;l0&^uwNoNPBt9;06+XkWa`huO=neV<bQ
z)OCk?Z!Ho}n$Q%7o-4icGZ<&vmA)lDTL(p^-rE}Oor+#NT78x`i)vGE-s&yGgWiG6
zuLP~*Ro?%5zP%vS<%jv0oTaTYTvzKbSx*n!5W)dgj!r{JpZ2@?=XATtDPf)STh3+Y
z-(a&`=TK}2BR_BQ*%jIX_w44S58yTH5RRQD@$UL1+pFsjZ3ol~BL@*x+40Jmp`a!t
zzxA`H6e>PUo#K|%qPGuJ4{+<xPUkw=O6{{<SC#*{qgJ@xRlATm>+fD|2g3LLq;+j5
z3btSl#d_ed@0QyZtkc%%JM1jIeeS$)W&zPy_LJ(?{QgQi)==6_-TldM_t=O7&UO|v
zKujgJVj)qwNg$$hW;rPJ$5A+m$&wk3C`ysHn1*o_WI0}B=4i$Q9F(_;KY|b`<uA~;
z<wmoKxG_-Nl?6Oy0cz?6WiYCg^u2mMmrg1}rW)IuV6IH2p(Uf`?Al66SMs^Vk+FDL
zoyaMsA#U&071X(>qMEsViBhF9I$Ru#-e?&5l@TQgV6ly_JQeScXQIGUi^C7=B-xcr
ztQ=9`pOYNu+*3Fsfp8|;$U8z1n&_Wm{lhhqK58+KT3OZ<D<%qiRhGS0s&mmq;c^5R
z=TR5U*{KM}aHbMNW;s5biHh>p1$&&^oqyNOf{uZm0xCzxeLRJ>4OfD6R*N*2wq9Ix
HGPLx6u)XXk

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/buildall.sh b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/buildall.sh
new file mode 100755
index 00000000..e195513a
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/buildall.sh	
@@ -0,0 +1,25 @@
+#!/bin/sh
+
+PROJECTS=" \
+GALAXIAN \
+MOONCR \
+AZURIAN \
+BLACKHOLE \
+CATACOMB \
+CHEWINGG \
+DEVILFSH \
+KINGBAL \
+MRDONIGH \
+OMEGA \
+ORBITRON \
+PISCES \
+UNIWARS \
+VICTORY \
+WAROFBUG \
+TRIPLEDR"
+
+for PROJECT in $PROJECTS; do
+    echo "Compiling $PROJECT"
+    sed -i "s/^.define NAME.*/\`define NAME \"$PROJECT\"/" rtl/Galaxian_MiST.sv
+    quartus_sh --flow compile Galaxian.qsf && cp output_files/Galaxian.rbf Releases/$PROJECT.rbf
+done
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/Galaxian_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/Galaxian_MiST.sv
index 4fd067af..263dacc0 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/Galaxian_MiST.sv	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/Galaxian_MiST.sv	
@@ -1,8 +1,7 @@
 //============================================================================
 //  Arcade: Galaxian
 //
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
+//  Port to MiST
 //
 //  This program is free software; you can redistribute it and/or modify it
 //  under the terms of the GNU General Public License as published by the Free
@@ -39,24 +38,59 @@ module Galaxian_MiST(
 
 `include "rtl\build_id.v" 
 
+// Choose one for name/built-in ROMset/features
+`define NAME "GALAXIAN"
+//`define NAME "MOONCR"
+//`define NAME "AZURIAN"
+//`define NAME "BLACKHOLE"
+//`define NAME "CATACOMB"
+//`define NAME "CHEWINGG"
+//`define NAME "DEVILFSH"
+//`define NAME "KINGBAL"
+//`define NAME "MRDONIGH"
+//`define NAME "OMEGA"
+//`define NAME "ORBITRON"
+//`define NAME "PISCES"
+//`define NAME "UNIWARS"
+//`define NAME "VICTORY"
+//`define NAME "WAROFBUG"
+//`define NAME "ZIGZAG" -- doesn't work, video gen issues
+//`define NAME "TRIPLEDR"
+
+reg rotate_dir;
+
+always @(*) begin
+	if (`NAME == "MOONCR" ||
+	    `NAME == "DEVILFSH" ||
+			`NAME == "KINGBAL" ||
+			`NAME == "OMEGA" ||
+			`NAME == "ORBITRON" ||
+			`NAME == "VICTORY")
+	begin
+		rotate_dir = 1'b0;
+	end else begin
+		rotate_dir = 1'b1;
+	end
+end
+
 localparam CONF_STR = {
-	"Galaxian;;",
+	`NAME,";;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.55.",`BUILD_DATE
+	"O5,Blend,Off,On;",
+	"T0,Reset;",
+	"V,v2.00.",`BUILD_DATE
 };
 
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
 
-wire clk_24, clk_18, clk_12, clk_6;
+wire clk_24, clk_12, clk_6;
 wire pll_locked;
 pll pll(
 	.inclk0(CLOCK_27),
 	.areset(0),
 	.c0(clk_24),
-	.c1(clk_18),
 	.c2(clk_12),
 	.c3(clk_6)
 	);
@@ -68,20 +102,18 @@ wire  [7:0] joystick_0;
 wire  [7:0] joystick_1;
 wire        scandoublerD;
 wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
+wire  [7:0] audio_a, audio_b, audio_c;
+wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a} + {2'b00, audio_c, 1'b0};
 wire 			hs, vs;
 wire 			hb, vb;
 wire        blankn = ~(hb | vb);
 wire  [2:0] r,g,b;
 
-galaxian galaxian
+galaxian #(.name(`NAME)) galaxian
 (
-	.W_CLK_18M(clk_18),
 	.W_CLK_12M(clk_12),
 	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
+	.I_RESET(status[0] | buttons[1]),
 	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
 	.P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
 	.W_R(r),
@@ -92,19 +124,18 @@ galaxian galaxian
 	.HBLANK(hb),
 	.VBLANK(vb),
 	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
+	.W_SDAT_B(audio_b),
+	.W_SDAT_C(audio_c)
 );
 
-video_mixer video_mixer(
+mist_video #(.COLOR_DEPTH(3),.SD_HCNT_WIDTH(10)) mist_video(
 	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
+	.R(blankn ? r : 0),
+	.G(blankn ? g : 0),
+	.B(blankn ? b : 0),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -112,49 +143,48 @@ video_mixer video_mixer(
 	.VGA_B(VGA_B),
 	.VGA_VS(VGA_VS),
 	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
+	.ce_divider(1'b1),
+	.rotate({rotate_dir,status[2]}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(status[4:3]),
+	.blend(status[5]),
+	.ypbpr(ypbpr)
 	);
-
-mist_io #(
+	
+user_io #(
 	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
+user_io(
+	.clk_sys        (clk_12         ),
 	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
 	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
 	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
 	.joystick_1     (joystick_1     ),
 	.status         (status         )
 	);
-	
-dac #(
-	.msbi_g(15))
+
+dac #(11)
 dac(
-	.clk_i(clk_24),
+	.clk_i(clk_12),
 	.res_n_i(1),
-	.dac_i({audio,5'd0}),
+	.dac_i(audio),
 	.dac_o(AUDIO_L)
 	);
 	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
+//                                                         Rotated                                                                                        Normal
+wire m_up     = ~status[2] ? (rotate_dir ? btn_left  | joystick_0[1] | joystick_1[1] : btn_right | joystick_0[0] | joystick_1[0] ) : btn_up    | joystick_0[3] | joystick_1[3];
+wire m_down   = ~status[2] ? (rotate_dir ? btn_right | joystick_0[0] | joystick_1[0] : btn_left  | joystick_0[1] | joystick_1[1] ) : btn_down  | joystick_0[2] | joystick_1[2];
+wire m_left   = ~status[2] ? (rotate_dir ? btn_down  | joystick_0[2] | joystick_1[2] : btn_up    | joystick_0[3] | joystick_1[3] ) : btn_left  | joystick_0[1] | joystick_1[1];
+wire m_right  = ~status[2] ? (rotate_dir ? btn_up    | joystick_0[3] | joystick_1[3] : btn_down  | joystick_0[2] | joystick_1[2] ) : btn_right | joystick_0[0] | joystick_1[0];
 wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
 wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
 
@@ -168,24 +198,23 @@ reg btn_fire1 = 0;
 reg btn_fire2 = 0;
 reg btn_fire3 = 0;
 reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
+wire       key_strobe;
+wire       key_pressed;
+wire [7:0] key_code;	
 
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
+always @(posedge clk_12) begin
+	if(key_strobe) begin
+		case(key_code)
+			'h75: btn_up         	<= key_pressed; // up
+			'h72: btn_down        	<= key_pressed; // down
+			'h6B: btn_left      		<= key_pressed; // left
+			'h74: btn_right       	<= key_pressed; // right
+			'h76: btn_coin				<= key_pressed; // ESC
+			'h05: btn_one_player   	<= key_pressed; // F1
+			'h06: btn_two_players  	<= key_pressed; // F2
+			'h14: btn_fire3 			<= key_pressed; // ctrl
+			'h11: btn_fire2 			<= key_pressed; // alt
+			'h29: btn_fire1   		<= key_pressed; // Space
 		endcase
 	end
 end
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROMS.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROMS.vhd
new file mode 100644
index 00000000..6ee75692
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROMS.vhd	
@@ -0,0 +1,292 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_PGM_0 is
+generic (
+	name : string := "GALAXIAN"
+);
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(13 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_PGM_0 is
+begin
+
+rom_pgm: if name="GALAXIAN" generate
+		mc_roms : entity work.GALAXIAN_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="MOONCR" generate
+		mc_roms : entity work.MOONCR_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="AZURIAN" generate
+		mc_roms : entity work.AZURIAN_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="BLACKHOLE" generate
+		mc_roms : entity work.BLACKHOLE_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="CATACOMB" generate
+		mc_roms : entity work.CATACOMB_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="CHEWINGG" generate
+		mc_roms : entity work.CHEWINGGUM_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="DEVILFSH" generate
+		mc_roms : entity work.DEVILFISH_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="KINGBAL" generate
+		mc_roms : entity work.kb_prog
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="MRDONIGH" generate
+		mc_roms : entity work.MRDONIGHTMARE_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="OMEGA" generate
+		mc_roms : entity work.OMEGA_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="ORBITRON" generate
+		mc_roms : entity work.ORBITRON_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="PISCES" generate
+		mc_roms : entity work.PISCES_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="UNIWARS" generate
+		mc_roms : entity work.UNIWARS_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="VICTORY" generate
+		mc_roms : entity work.VICTORY_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="WAROFBUG" generate
+		mc_roms : entity work.WAROFBUGS_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="ZIGZAG" generate
+		mc_roms : entity work.ZIGZAG_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="TRIPLEDR" generate
+		mc_roms : entity work.TRIPLEDRAWPOKER_ROM_PGM_0
+		port map (clk => clk, addr => addr, data => data );
+end generate;
+
+end architecture;
+
+-------------------------
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_1K is
+generic (
+	name : string := "GALAXIAN"
+);
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(11 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_1K is
+begin
+
+rom_pgm: if name="GALAXIAN" generate
+		mc_roms : entity work.GALAXIAN_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="MOONCR" generate
+		mc_roms : entity work.MOONCR_1K
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="AZURIAN" generate
+		mc_roms : entity work.AZURIAN_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="BLACKHOLE" generate
+		mc_roms : entity work.BLACKHOLE_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="CATACOMB" generate
+		mc_roms : entity work.CATACOMB_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="CHEWINGG" generate
+		mc_roms : entity work.CHEWINGGUM_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="DEVILFSH" generate
+		mc_roms : entity work.DEVILFISH_1K
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="KINGBAL" generate
+		mc_roms : entity work.KB_1K
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="MRDONIGH" generate
+		mc_roms : entity work.MRDONIGHTMARE_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="OMEGA" generate
+		mc_roms : entity work.OMEGA_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="ORBITRON" generate
+		mc_roms : entity work.ORBITRON_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="PISCES" generate
+		mc_roms : entity work.PISCES_1K
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="UNIWARS" generate
+		mc_roms : entity work.UNIWARS_1K
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="VICTORY" generate
+		mc_roms : entity work.VICTORY_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="WAROFBUG" generate
+		mc_roms : entity work.WAROFBUGS_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="ZIGZAG" generate
+		mc_roms : entity work.ZIGZAG_1K
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="TRIPLEDR" generate
+		mc_roms : entity work.TRIPLEDRAWPOKER_1K
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+end generate;
+
+end architecture;
+
+-------------------------
+
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_1H is
+generic (
+	name : string := "GALAXIAN"
+);
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(11 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_1H is
+begin
+
+rom_pgm: if name="GALAXIAN" generate
+		mc_roms : entity work.GALAXIAN_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="MOONCR" generate
+		mc_roms : entity work.MOONCR_1H
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="AZURIAN" generate
+		mc_roms : entity work.AZURIAN_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="BLACKHOLE" generate
+		mc_roms : entity work.BLACKHOLE_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="CATACOMB" generate
+		mc_roms : entity work.CATACOMB_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="CHEWINGG" generate
+		mc_roms : entity work.CHEWINGGUM_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="DEVILFSH" generate
+		mc_roms : entity work.DEVILFISH_1H
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="KINGBAL" generate
+		mc_roms : entity work.KB_1H
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="MRDONIGH" generate
+		mc_roms : entity work.MRDONIGHTMARE_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="OMEGA" generate
+		mc_roms : entity work.OMEGA_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="ORBITRON" generate
+		mc_roms : entity work.ORBITRON_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="PISCES" generate
+		mc_roms : entity work.PISCES_1H
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="UNIWARS" generate
+		mc_roms : entity work.UNIWARS_1H
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="VICTORY" generate
+		mc_roms : entity work.VICTORY_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="WAROFBUG" generate
+		mc_roms : entity work.WAROFBUGS_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+	elsif name="ZIGZAG" generate
+		mc_roms : entity work.ZIGZAG_1H
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="TRIPLEDR" generate
+		mc_roms : entity work.TRIPLEDRAWPOKER_1H
+		port map (clk => clk, addr => addr(10 downto 0), data => data );
+end generate;
+
+end architecture;
+
+-------------------------
+
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ROM_6L is
+generic (
+	name : string := "GALAXIAN"
+);
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(4 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ROM_6L is
+begin
+
+rom_pgm: if name="GALAXIAN" generate
+		mc_roms : entity work.GALAXIAN_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="MOONCR" generate
+		mc_roms : entity work.MOONCR_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="AZURIAN" generate
+		mc_roms : entity work.AZURIAN_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="BLACKHOLE" generate
+		mc_roms : entity work.BLACKHOLE_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="CATACOMB" generate
+		mc_roms : entity work.CATACOMB_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="CHEWINGG" generate
+		mc_roms : entity work.CHEWINGGUM_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="DEVILFSH" generate
+		mc_roms : entity work.DEVILFISH_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="KINGBAL" generate
+		mc_roms : entity work.KB_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="MRDONIGH" generate
+		mc_roms : entity work.MRDONIGHTMARE_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="OMEGA" generate
+		mc_roms : entity work.OMEGA_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="ORBITRON" generate
+		mc_roms : entity work.ORBITRON_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="PISCES" generate
+		mc_roms : entity work.PISCES_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="UNIWARS" generate
+		mc_roms : entity work.UNIWARS_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="VICTORY" generate
+		mc_roms : entity work.VICTORY_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="WAROFBUG" generate
+		mc_roms : entity work.WAROFBUGS_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="ZIGZAG" generate
+		mc_roms : entity work.ZIGZAG_6L
+		port map (clk => clk, addr => addr, data => data );
+	elsif name="TRIPLEDR" generate
+		mc_roms : entity work.TRIPLEDRAWPOKER_6L
+		port map (clk => clk, addr => addr, data => data );
+end generate;
+
+end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1H.vhd
index 6f39d31b..6f23af28 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1H.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity AZURIAN_1H is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ entity GALAXIAN_1H is
     );
 end entity;
 
-architecture prom of GALAXIAN_1H is
+architecture prom of AZURIAN_1H is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
     x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1K.vhd
index 942316be..3e2ac497 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_1K.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity AZURIAN_1K is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1K is
+architecture prom of AZURIAN_1K is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
     x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_6L.vhd
similarity index 92%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_6L.vhd
index 69425a6e..55ee53d7 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/GALAXIAN_6L.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/AZURIAN_6L.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity AZURIAN_6L is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_6L is
+architecture prom of AZURIAN_6L is
 	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
     x"00",x"7A",x"36",x"07",x"00",x"F0",x"38",x"1F", -- 0x0000
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/ROM_PGM_0.vhd
index 5a0cf5cd..fbbad63c 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/AzurianAttack_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/azurian/ROM_PGM_0.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity AZURIAN_ROM_PGM_0 is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of ROM_PGM_0 is
+architecture prom of AZURIAN_ROM_PGM_0 is
 	type rom is array(0 to  12287) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
     x"00",x"AF",x"32",x"01",x"70",x"C3",x"C8",x"00", -- 0x0000
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1H.vhd
index 73af8474..e9fb62b7 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1H.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity BLACKHOLE_1H is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1H is
+architecture prom of BLACKHOLE_1H is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"22",X"3E",X"00",X"3E",X"2A",X"2A",X"2A",X"00",X"00",X"3E",X"22",X"22",X"3E",X"00",X"3E",X"22",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1K.vhd
index b5bcbc4e..dd80c0ea 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_1K.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity BLACKHOLE_1K is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1K is
+architecture prom of BLACKHOLE_1K is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"22",X"3E",X"00",X"3E",X"2A",X"2A",X"2A",X"00",X"00",X"3E",X"22",X"22",X"3E",X"00",X"3E",X"22",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_6L.vhd
similarity index 91%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_6L.vhd
index 2f811f7d..0b62b833 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_6L.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/BLACKHOLE_6L.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity BLACKHOLE_6L is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_6L is
+architecture prom of BLACKHOLE_6L is
 	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"00",X"00",X"F6",X"00",X"16",X"C0",X"3F",X"00",X"D8",X"07",X"3F",X"00",X"C0",X"C4",X"07",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/ROM_PGM_0.vhd
index 3ca80bee..63a5f7a1 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/blackhole/ROM_PGM_0.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity BLACKHOLE_ROM_PGM_0 is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of ROM_PGM_0 is
+architecture prom of BLACKHOLE_ROM_PGM_0 is
 	type rom is array(0 to  12287) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"AF",X"32",X"01",X"70",X"C3",X"50",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1H.vhd
index dec55c15..d4d2f2b6 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1H.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity CATACOMB_1H is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(10 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_1H is
     );
 end;
 
-architecture RTL of GALAXIAN_1H is
+architecture RTL of CATACOMB_1H is
 
 
   type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1K.vhd
index 4ed5bb4c..4b3dbb2d 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_1K.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity CATACOMB_1K is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(10 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_1K is
     );
 end;
 
-architecture RTL of GALAXIAN_1K is
+architecture RTL of CATACOMB_1K is
 
 
   type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_6L.vhd
similarity index 93%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_6L.vhd
index e989225e..b160e0df 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_6L.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/CATACOMB_6L.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity CATACOMB_6L is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(4 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_6L is
     );
 end;
 
-architecture RTL of GALAXIAN_6L is
+architecture RTL of CATACOMB_6L is
 
 
   type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/ROM_PGM_0.vhd
index 8b3669d9..8e4a78c4 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/catacomb/ROM_PGM_0.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity CATACOMB_ROM_PGM_0 is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(13 downto 0);
@@ -12,7 +12,7 @@ entity ROM_PGM_0 is
     );
 end;
 
-architecture RTL of ROM_PGM_0 is
+architecture RTL of CATACOMB_ROM_PGM_0 is
 
 
   type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/col.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/col.vhd
similarity index 90%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/col.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/col.vhd
index e4323869..635b1893 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/col.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/col.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity col is
+entity CHEWINGGUM_6L is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of col is
+architecture prom of CHEWINGGUM_6L is
 	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"00",X"00",X"F6",X"00",X"16",X"C0",X"3F",X"00",X"D8",X"07",X"3F",X"00",X"C0",X"C4",X"07",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/h.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/h.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/h.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/h.vhd
index a14e3a66..96927b51 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/h.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/h.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity h_rom is
+entity CHEWINGGUM_1H is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of h_rom is
+architecture prom of CHEWINGGUM_1H is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/k.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/k.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/k.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/k.vhd
index 794537b6..1107bf5d 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/k.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/k.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity k_rom is
+entity CHEWINGGUM_1K is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of k_rom is
+architecture prom of CHEWINGGUM_1K is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/prog.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/prog.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/prog.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/prog.vhd
index b4dc5a23..8c2b8807 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/ChewingGum_MiST/rtl/ROM/prog.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/chewinggum/prog.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity prog is
+entity CHEWINGGUM_ROM_PGM_0 is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of prog is
+architecture prom of CHEWINGGUM_ROM_PGM_0 is
 	type rom is array(0 to  10239) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"C3",X"4A",X"00",X"BA",X"CA",X"69",X"B5",X"6E",X"C3",X"00",X"06",X"54",X"16",X"2A",X"6E",X"3A",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1H.vhd
index 9a0ffdb7..9fad8ef9 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1H.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity DEVILFISH_1H is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(11 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1H is
+architecture prom of DEVILFISH_1H is
 	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"00",X"00",X"00",X"00",X"0F",X"1F",X"1F",X"00",X"30",X"34",X"6C",X"18",X"13",X"8F",X"8E",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1K.vhd
index 50436b22..7e5eb71f 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_1K.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity DEVILFISH_1K is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(11 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1K is
+architecture prom of DEVILFISH_1K is
 	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"00",X"0E",X"3F",X"7F",X"73",X"E3",X"E3",X"00",X"00",X"00",X"80",X"E0",X"E0",X"F0",X"F0",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_6L.vhd
similarity index 91%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_6L.vhd
index 7432acf2..71db70e1 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/GALAXIAN_6L.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/DEVILFISH_6L.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity DEVILFISH_6L is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_6L is
+architecture prom of DEVILFISH_6L is
 	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"17",X"C7",X"F6",X"00",X"17",X"C0",X"3F",X"00",X"07",X"C0",X"3F",X"00",X"C0",X"C4",X"07",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/ROM_PGM_0.vhd
index 84f3475d..bd8eb669 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/DevilFish_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/devilfish/ROM_PGM_0.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity DEVILFISH_ROM_PGM_0 is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of ROM_PGM_0 is
+architecture prom of DEVILFISH_ROM_PGM_0 is
 	type rom is array(0 to  16383) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"AF",X"32",X"01",X"70",X"C3",X"8E",X"00",X"FF",X"C3",X"73",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_1H.vhd
similarity index 100%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_1H.vhd
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_1K.vhd
similarity index 100%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_1K.vhd
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_6L.vhd
similarity index 100%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/BlackHole_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/GALAXIAN_6L.vhd
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/ROM_PGM_0.vhd
index ee7591a2..6bb49253 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/galaxian/ROM_PGM_0.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity GALAXIAN_ROM_PGM_0 is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of ROM_PGM_0 is
+architecture prom of GALAXIAN_ROM_PGM_0 is
 	type rom is array(0 to  10239) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"AF",X"32",X"01",X"70",X"C3",X"55",X"1A",X"FF",X"3A",X"07",X"40",X"0F",X"D0",X"33",X"33",X"C9",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/col.vhd
similarity index 93%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/col.vhd
index be83394e..f305ab52 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/col.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/col.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity col is
+entity kb_6l is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of col is
+architecture prom of kb_6l is
 	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"D8",X"F0",X"07",X"00",X"3F",X"F6",X"07",X"00",X"F6",X"38",X"07",X"00",X"3F",X"38",X"2F",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe1-4.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe1-4.vhd
similarity index 100%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe1-4.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe1-4.vhd
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe2-5.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe2-5.vhd
similarity index 100%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe2-5.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe2-5.vhd
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe3-6.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe3-6.vhd
similarity index 100%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/kbe3-6.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/kbe3-6.vhd
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/prog.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/prog.vhd
index 8f7b15f4..e6c4325d 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/prog.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/prog.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity prog is
+entity kb_prog is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of prog is
+architecture prom of kb_prog is
 	type rom is array(0 to  12287) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"AF",X"32",X"01",X"70",X"C3",X"22",X"13",X"00",X"3A",X"2F",X"43",X"11",X"30",X"43",X"18",X"3B",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_h.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_h.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_h.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_h.vhd
index a9b2202b..c4f0a4d9 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_h.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_h.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity rom_h is
+entity kb_1h is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(11 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of rom_h is
+architecture prom of kb_1h is
 	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_k.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_k.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_k.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_k.vhd
index b6a9c509..751080e9 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/rom_k.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/kingbaloon/rom_k.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity rom_k is
+entity kb_1k is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(11 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of rom_k is
+architecture prom of kb_1k is
 	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1H.vhd
index b9ce0580..7cbd2290 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1H.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity MOONCR_1H is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(11 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1H is
+architecture prom of MOONCR_1H is
 	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1K.vhd
index 75eca2cc..0e9f18d7 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_1K.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity MOONCR_1K is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(11 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1K is
+architecture prom of MOONCR_1K is
 	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_6L.vhd
similarity index 91%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_6L.vhd
index 9cf7380a..eb484000 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GALAXIAN_6L.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/MOONCR_6L.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity MOONCR_6L is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_6L is
+architecture prom of MOONCR_6L is
 	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"7A",X"36",X"07",X"00",X"F0",X"38",X"1F",X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/ROM_PGM_0.vhd
index 742f9975..510c6a3d 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mooncresta/ROM_PGM_0.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity MOONCR_ROM_PGM_0 is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of ROM_PGM_0 is
+architecture prom of MOONCR_ROM_PGM_0 is
 	type rom is array(0 to  16383) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"AF",X"32",X"01",X"70",X"C3",X"AD",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1H.vhd
index df224504..8948e31d 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1H.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity MRDONIGHTMARE_1H is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1H is
+architecture prom of MRDONIGHTMARE_1H is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1K.vhd
index 25afe613..20c69ec9 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_1K.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity MRDONIGHTMARE_1K is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1K is
+architecture prom of MRDONIGHTMARE_1K is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_6L.vhd
similarity index 90%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_6L.vhd
index 9d5c2fdc..9b3f5843 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GALAXIAN_6L.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/MRDONIGHTMARE_6L.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity MRDONIGHTMARE_6L is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_6L is
+architecture prom of MRDONIGHTMARE_6L is
 	type rom is array(31 downto 0) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"C6",X"07",X"76",X"00",X"C0",X"80",X"1E",X"00",X"80",X"C0",X"1E",X"00",X"76",X"C0",X"F6",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/ROM_PGM_0.vhd
index 1b828ed1..bc8150b0 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/mrdonightmare/ROM_PGM_0.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity MRDONIGHTMARE_ROM_PGM_0 is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of ROM_PGM_0 is
+architecture prom of MRDONIGHTMARE_ROM_PGM_0 is
 	type rom is array(0 to  10239) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"AF",X"32",X"01",X"70",X"C3",X"D0",X"00",X"3A",X"36",X"40",X"3C",X"E6",X"07",X"32",X"36",X"40",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1H.vhd
index f7d8d13f..21a028d8 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1H.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity OMEGA_1H is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(10 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_1H is
     );
 end;
 
-architecture RTL of GALAXIAN_1H is
+architecture RTL of OMEGA_1H is
 
 
   type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1K.vhd
index cb6701eb..957bead1 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_1K.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity OMEGA_1K is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(10 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_1K is
     );
 end;
 
-architecture RTL of GALAXIAN_1K is
+architecture RTL of OMEGA_1K is
 
 
   type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_6L.vhd
similarity index 93%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_6L.vhd
index e989225e..0f72c46c 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Catacomb_MiST/rtl/ROM/GALAXIAN_6L.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/OMEGA_6L.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity OMEGA_6L is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(4 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_6L is
     );
 end;
 
-architecture RTL of GALAXIAN_6L is
+architecture RTL of OMEGA_6L is
 
 
   type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/ROM_PGM_0.vhd
index 33721787..19fe3086 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/omega/ROM_PGM_0.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity OMEGA_ROM_PGM_0 is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(13 downto 0);
@@ -12,7 +12,7 @@ entity ROM_PGM_0 is
     );
 end;
 
-architecture RTL of ROM_PGM_0 is
+architecture RTL of OMEGA_ROM_PGM_0 is
 
 
   type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1H.vhd
index dacb0a04..a813db5b 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1H.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity ORBITRON_1H is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1H is
+architecture prom of ORBITRON_1H is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"7C",X"82",X"82",X"82",X"82",X"7C",X"00",X"00",X"02",X"02",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1K.vhd
index fd77d08e..ae3bd9dc 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_1K.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity ORBITRON_1K is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1K is
+architecture prom of ORBITRON_1K is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"7C",X"82",X"82",X"82",X"82",X"7C",X"00",X"00",X"02",X"02",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_6L.vhd
similarity index 91%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_6L.vhd
index 9cf7380a..ac18266d 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GALAXIAN_6L.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ORBITRON_6L.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity ORBITRON_6L is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_6L is
+architecture prom of ORBITRON_6L is
 	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"7A",X"36",X"07",X"00",X"F0",X"38",X"1F",X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ROM_PGM_0.vhd
index 401c50ae..c13d7bde 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/orbitron/ROM_PGM_0.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity ORBITRON_ROM_PGM_0 is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of ROM_PGM_0 is
+architecture prom of ORBITRON_ROM_PGM_0 is
 	type rom is array(0 to  10239) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"31",X"00",X"44",X"C3",X"41",X"02",X"00",X"FF",X"FF",X"FF",X"FF",X"20",X"20",X"20",X"20",X"20",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1H.vhd
index 787ca26f..25d7b89c 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1H.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity PISCES_1H is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(11 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_1H is
     );
 end;
 
-architecture RTL of GALAXIAN_1H is
+architecture RTL of PISCES_1H is
 
 
   type ROM_ARRAY is array(0 to 4095) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1K.vhd
index 693ba290..c6553365 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_1K.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity PISCES_1K is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(11 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_1K is
     );
 end;
 
-architecture RTL of GALAXIAN_1K is
+architecture RTL of PISCES_1K is
 
 
   type ROM_ARRAY is array(0 to 4095) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_6L.vhd
similarity index 93%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_6L.vhd
index 222709ac..19e98de8 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GALAXIAN_6L.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/PISCES_6L.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity PISCES_6L is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(4 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_6L is
     );
 end;
 
-architecture RTL of GALAXIAN_6L is
+architecture RTL of PISCES_6L is
 
 
   type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/ROM_PGM_0.vhd
index f49d198b..55a5db3b 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/pisces/ROM_PGM_0.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity PISCES_ROM_PGM_0 is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(13 downto 0);
@@ -12,7 +12,7 @@ entity ROM_PGM_0 is
     );
 end;
 
-architecture RTL of ROM_PGM_0 is
+architecture RTL of PISCES_ROM_PGM_0 is
 
 
   type ROM_ARRAY is array(0 to 16383) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1H.vhd
new file mode 100644
index 00000000..a74a2d51
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1H.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity TRIPLEDRAWPOKER_1H is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of TRIPLEDRAWPOKER_1H is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FE",X"FC",X"F8",X"F0",X"E0",X"C0",X"80",X"00",
+		X"00",X"80",X"C0",X"E0",X"F0",X"F8",X"FC",X"FE",X"0F",X"07",X"03",X"03",X"03",X"07",X"0F",X"1F",
+		X"1F",X"0F",X"07",X"03",X"03",X"03",X"07",X"0F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"9F",X"8F",X"87",X"83",X"91",X"98",
+		X"FF",X"FF",X"9F",X"8F",X"87",X"83",X"81",X"80",X"FF",X"FF",X"E3",X"E1",X"E0",X"F0",X"F8",X"F8",
+		X"80",X"88",X"8C",X"8E",X"8F",X"8F",X"8F",X"FF",X"78",X"38",X"18",X"00",X"00",X"81",X"C3",X"FF",
+		X"FF",X"FF",X"9F",X"8F",X"87",X"83",X"81",X"80",X"FF",X"FF",X"E3",X"E1",X"E0",X"F0",X"F8",X"F8",
+		X"80",X"88",X"8C",X"8E",X"8F",X"8F",X"8F",X"FF",X"78",X"38",X"18",X"00",X"00",X"81",X"C3",X"FF",
+		X"FF",X"FF",X"E7",X"C7",X"87",X"8F",X"8F",X"8E",X"FF",X"FF",X"F3",X"F1",X"F0",X"F8",X"F8",X"38",
+		X"C0",X"9F",X"1F",X"01",X"01",X"01",X"1F",X"1F",X"03",X"F9",X"F8",X"80",X"80",X"80",X"F8",X"F8",
+		X"FF",X"FF",X"E7",X"C7",X"87",X"8F",X"8F",X"8E",X"FF",X"FF",X"F3",X"F1",X"F0",X"F8",X"F8",X"38",
+		X"00",X"1F",X"1F",X"19",X"19",X"19",X"18",X"18",X"00",X"F8",X"F8",X"98",X"98",X"98",X"18",X"18",
+		X"FF",X"F1",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1",X"FF",X"FF",X"FF",X"7F",X"3F",X"1F",X"0F",X"87",
+		X"91",X"91",X"80",X"80",X"80",X"91",X"91",X"FF",X"C3",X"E1",X"00",X"00",X"00",X"FF",X"FF",X"FF",
+		X"FF",X"F1",X"F0",X"F0",X"F0",X"F0",X"F1",X"F1",X"FF",X"FF",X"FF",X"7F",X"3F",X"1F",X"0F",X"87",
+		X"91",X"91",X"80",X"80",X"80",X"91",X"91",X"FF",X"C3",X"E1",X"00",X"00",X"00",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"E7",X"C6",X"86",X"86",X"8E",X"8E",X"FF",X"FF",X"00",X"00",X"00",X"38",X"38",X"38",
+		X"00",X"1F",X"1F",X"18",X"18",X"18",X"18",X"00",X"38",X"38",X"38",X"38",X"38",X"78",X"FF",X"FF",
+		X"FF",X"FF",X"E7",X"C6",X"86",X"86",X"8E",X"8E",X"FF",X"FF",X"00",X"00",X"00",X"38",X"38",X"38",
+		X"00",X"F8",X"F8",X"00",X"00",X"00",X"00",X"00",X"38",X"38",X"38",X"38",X"38",X"78",X"FF",X"FF",
+		X"FF",X"FF",X"E0",X"C0",X"80",X"84",X"8E",X"8E",X"FF",X"FF",X"03",X"01",X"00",X"10",X"38",X"38",
+		X"F8",X"F8",X"18",X"18",X"38",X"F0",X"E1",X"03",X"38",X"38",X"38",X"38",X"30",X"71",X"F3",X"FF",
+		X"FF",X"FF",X"E0",X"C0",X"80",X"84",X"8E",X"8E",X"FF",X"FF",X"03",X"01",X"00",X"10",X"38",X"38",
+		X"1F",X"1F",X"18",X"18",X"1C",X"0F",X"87",X"C0",X"38",X"38",X"38",X"38",X"30",X"71",X"F3",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"9F",X"87",X"81",X"FF",X"FF",X"E0",X"E0",X"E0",X"F8",X"F8",X"F8",
+		X"80",X"E0",X"F8",X"FE",X"FF",X"FF",X"FF",X"FF",X"78",X"18",X"00",X"00",X"80",X"E0",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"9F",X"87",X"81",X"FF",X"FF",X"E0",X"E0",X"E0",X"F8",X"F8",X"F8",
+		X"80",X"E0",X"F8",X"FE",X"FF",X"FF",X"FF",X"FF",X"78",X"18",X"00",X"00",X"80",X"E0",X"FF",X"FF",
+		X"FF",X"FF",X"E1",X"C0",X"80",X"84",X"8E",X"8E",X"FF",X"FF",X"C3",X"01",X"00",X"10",X"38",X"38",
+		X"8E",X"8E",X"8E",X"84",X"80",X"C0",X"E1",X"FF",X"38",X"38",X"38",X"10",X"00",X"01",X"C3",X"FF",
+		X"FF",X"FF",X"E1",X"C0",X"80",X"84",X"8E",X"8E",X"FF",X"FF",X"C3",X"01",X"00",X"10",X"38",X"38",
+		X"8E",X"8E",X"8E",X"84",X"80",X"C0",X"E1",X"FF",X"38",X"38",X"38",X"10",X"00",X"01",X"C3",X"FF",
+		X"FF",X"FF",X"E7",X"C7",X"86",X"8E",X"8E",X"8E",X"FF",X"FF",X"83",X"01",X"00",X"10",X"38",X"38",
+		X"8E",X"8E",X"8E",X"87",X"80",X"C0",X"E0",X"FF",X"38",X"38",X"38",X"10",X"00",X"01",X"03",X"FF",
+		X"FF",X"FF",X"E7",X"C7",X"86",X"8E",X"8E",X"8E",X"FF",X"FF",X"83",X"01",X"00",X"10",X"38",X"38",
+		X"8E",X"8E",X"8E",X"87",X"80",X"C0",X"E0",X"FF",X"38",X"38",X"38",X"10",X"00",X"01",X"03",X"FF",
+		X"FF",X"C0",X"C0",X"C0",X"FF",X"FF",X"E0",X"C0",X"FF",X"00",X"00",X"00",X"FF",X"FF",X"01",X"00",
+		X"C0",X"C7",X"C7",X"C7",X"C0",X"C0",X"E0",X"FF",X"00",X"F8",X"F8",X"F8",X"00",X"00",X"01",X"FF",
+		X"FF",X"C0",X"C0",X"C0",X"FF",X"FF",X"E0",X"C0",X"FF",X"00",X"00",X"00",X"FF",X"FF",X"01",X"00",
+		X"C0",X"C7",X"C7",X"C7",X"C0",X"C0",X"E0",X"FF",X"00",X"F8",X"F8",X"F8",X"00",X"00",X"01",X"FF",
+		X"FF",X"F3",X"E3",X"C3",X"C7",X"C7",X"C7",X"C7",X"FF",X"FF",X"FF",X"F8",X"F8",X"F8",X"F8",X"F8",
+		X"C3",X"C0",X"E0",X"F0",X"FF",X"FF",X"FF",X"FF",X"F8",X"00",X"00",X"00",X"F8",X"F8",X"FF",X"FF",
+		X"FF",X"F3",X"E3",X"C3",X"C7",X"C7",X"C7",X"C7",X"FF",X"FF",X"FF",X"F8",X"F8",X"F8",X"F8",X"F8",
+		X"C3",X"C0",X"E0",X"F0",X"FF",X"FF",X"FF",X"FF",X"F8",X"00",X"00",X"00",X"F8",X"F8",X"FF",X"FF",
+		X"FF",X"FF",X"C0",X"80",X"80",X"87",X"8F",X"8F",X"FF",X"FF",X"01",X"00",X"00",X"F0",X"F8",X"18",
+		X"8E",X"84",X"80",X"80",X"C0",X"E1",X"C3",X"C7",X"18",X"30",X"00",X"00",X"01",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"C0",X"80",X"80",X"87",X"8F",X"8F",X"FF",X"FF",X"01",X"00",X"00",X"F0",X"F8",X"18",
+		X"8E",X"84",X"80",X"80",X"C0",X"E1",X"C3",X"C7",X"18",X"30",X"00",X"00",X"01",X"FF",X"FF",X"FF",
+		X"FF",X"9F",X"80",X"80",X"80",X"9C",X"FE",X"FC",X"FF",X"FC",X"00",X"00",X"00",X"3C",X"1F",X"0F",
+		X"F8",X"90",X"81",X"83",X"87",X"8F",X"9F",X"FF",X"04",X"C0",X"E0",X"F0",X"F8",X"FC",X"FF",X"FF",
+		X"FF",X"9F",X"80",X"80",X"80",X"9C",X"FE",X"FC",X"FF",X"FC",X"00",X"00",X"00",X"3C",X"1F",X"0F",
+		X"F8",X"90",X"81",X"83",X"87",X"8F",X"9F",X"FF",X"04",X"C0",X"E0",X"F0",X"F8",X"FC",X"FF",X"FF",
+		X"9F",X"83",X"80",X"80",X"98",X"F8",X"F9",X"F9",X"FF",X"FF",X"FF",X"3F",X"0F",X"03",X"C0",X"E0",
+		X"F9",X"F9",X"F8",X"98",X"80",X"80",X"83",X"9F",X"E0",X"C0",X"03",X"0F",X"3F",X"FF",X"FF",X"FF",
+		X"9F",X"83",X"80",X"80",X"98",X"F8",X"F9",X"F9",X"FF",X"FF",X"FF",X"3F",X"0F",X"03",X"C0",X"E0",
+		X"F9",X"F9",X"F8",X"98",X"80",X"80",X"83",X"9F",X"E0",X"C0",X"03",X"0F",X"3F",X"FF",X"FF",X"FF",
+		X"F0",X"E0",X"C0",X"C0",X"C0",X"60",X"38",X"00",X"FF",X"7F",X"3F",X"1F",X"0F",X"07",X"03",X"01",
+		X"00",X"38",X"60",X"C0",X"C0",X"C0",X"E0",X"F0",X"01",X"03",X"07",X"0F",X"1F",X"3F",X"7F",X"FF",
+		X"F8",X"F0",X"E0",X"E0",X"60",X"30",X"38",X"00",X"FF",X"7F",X"3F",X"3F",X"4F",X"87",X"03",X"01",
+		X"00",X"38",X"30",X"60",X"E0",X"E0",X"F0",X"F8",X"01",X"03",X"87",X"4F",X"3F",X"3F",X"7F",X"FF",
+		X"FE",X"FC",X"F8",X"F0",X"E0",X"C0",X"80",X"00",X"FF",X"7F",X"3F",X"1F",X"0F",X"07",X"03",X"01",
+		X"00",X"80",X"C0",X"E0",X"F0",X"F8",X"FC",X"FE",X"01",X"03",X"07",X"0F",X"1F",X"3F",X"7F",X"FF",
+		X"67",X"BD",X"DB",X"66",X"66",X"DB",X"BD",X"66",X"66",X"BD",X"DB",X"66",X"66",X"DB",X"BD",X"67",
+		X"E6",X"BD",X"DB",X"66",X"66",X"DB",X"BD",X"66",X"66",X"BD",X"DB",X"66",X"66",X"DB",X"BD",X"E6",
+		X"66",X"BD",X"DB",X"66",X"66",X"DB",X"BD",X"66",X"66",X"BD",X"DB",X"66",X"00",X"7E",X"7A",X"7A",
+		X"42",X"7A",X"5A",X"7E",X"7E",X"4E",X"66",X"6A",X"6A",X"66",X"4E",X"7E",X"5E",X"7E",X"7E",X"42",
+		X"7E",X"5E",X"7E",X"00",X"66",X"DB",X"BD",X"66",X"FF",X"E0",X"E0",X"FE",X"FE",X"FE",X"E0",X"E0",
+		X"FF",X"07",X"07",X"7F",X"7F",X"7F",X"07",X"07",X"FF",X"F0",X"E0",X"E7",X"E7",X"E7",X"E0",X"F0",
+		X"FF",X"0F",X"07",X"E7",X"E7",X"E7",X"07",X"0F",X"FF",X"E0",X"E0",X"E7",X"E7",X"E7",X"E7",X"FF",
+		X"FF",X"07",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"E0",X"E0",X"E7",X"E7",X"E3",X"F0",X"F8",X"FF",
+		X"07",X"07",X"E7",X"E7",X"C7",X"0F",X"1F",X"FF",X"FF",X"F0",X"E0",X"E7",X"E7",X"E7",X"E3",X"F3",
+		X"FF",X"0F",X"07",X"E7",X"E7",X"E7",X"C7",X"CF",X"FF",X"E0",X"E0",X"FE",X"FE",X"FE",X"E0",X"E0",
+		X"FF",X"0F",X"07",X"67",X"67",X"67",X"07",X"0F",X"FF",X"E0",X"E0",X"FF",X"FC",X"F8",X"E0",X"E0",
+		X"FF",X"07",X"07",X"1F",X"3F",X"FF",X"07",X"07",X"FF",X"F0",X"E0",X"E7",X"E7",X"E7",X"E3",X"F3",
+		X"FF",X"0F",X"07",X"E7",X"E7",X"E7",X"C7",X"CF",X"FF",X"E0",X"E0",X"E6",X"E6",X"E6",X"E7",X"E7",
+		X"FF",X"07",X"07",X"67",X"67",X"67",X"E7",X"E7",X"FF",X"E0",X"E0",X"E7",X"E7",X"E7",X"E7",X"FF",
+		X"FF",X"07",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"E3",X"E3",X"E6",X"E6",X"E6",X"E0",X"F0",
+		X"FF",X"0F",X"07",X"67",X"67",X"67",X"C7",X"CF",X"FF",X"FF",X"FF",X"E0",X"E0",X"FF",X"FF",X"FF",
+		X"FF",X"E7",X"E7",X"07",X"07",X"E7",X"E7",X"FF",X"E0",X"E0",X"FE",X"FE",X"FE",X"E0",X"E0",X"FF",
+		X"0F",X"07",X"67",X"67",X"67",X"07",X"0F",X"FF",X"E0",X"E0",X"FF",X"FC",X"F8",X"E0",X"E0",X"FF",
+		X"07",X"07",X"1F",X"3F",X"FF",X"07",X"07",X"FF",X"FF",X"E0",X"E0",X"E7",X"E7",X"E3",X"F0",X"F8",
+		X"FF",X"07",X"07",X"E7",X"E7",X"C7",X"0F",X"1F",X"FF",X"E0",X"E0",X"E6",X"E6",X"E6",X"E0",X"F1",
+		X"FF",X"07",X"07",X"67",X"67",X"67",X"07",X"8F",X"FF",X"FF",X"FF",X"E0",X"E0",X"FF",X"FF",X"FF",
+		X"FF",X"E7",X"E7",X"07",X"07",X"E7",X"E7",X"FF",X"FF",X"E0",X"E0",X"E7",X"E7",X"E7",X"E7",X"E7",
+		X"FF",X"07",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"F0",X"E0",X"E7",X"E7",X"E7",X"E3",X"F3",X"FF",
+		X"0F",X"07",X"E7",X"E7",X"E7",X"C7",X"CF",X"FF",X"FF",X"FF",X"F0",X"E0",X"E7",X"E7",X"E7",X"E4",
+		X"FF",X"FF",X"0F",X"07",X"E7",X"E7",X"E7",X"E7",X"E0",X"F0",X"FF",X"E0",X"E0",X"FE",X"FE",X"FE",
+		X"C7",X"CF",X"FF",X"0F",X"07",X"67",X"67",X"67",X"E0",X"E0",X"FF",X"E0",X"E0",X"FF",X"FF",X"FE",
+		X"07",X"0F",X"FF",X"07",X"07",X"8F",X"1F",X"3F",X"FF",X"FF",X"E0",X"E0",X"FF",X"E0",X"E0",X"E6",
+		X"1F",X"8F",X"07",X"07",X"FF",X"07",X"07",X"67",X"E6",X"E6",X"E0",X"F1",X"FF",X"E0",X"E0",X"E7",
+		X"67",X"67",X"07",X"8F",X"FF",X"07",X"07",X"FF",X"E7",X"E7",X"E7",X"FF",X"E0",X"E0",X"E6",X"E6",
+		X"FF",X"FF",X"FF",X"FF",X"07",X"07",X"67",X"67",X"E6",X"E7",X"E7",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"67",X"E7",X"E7",X"FF",X"FF",X"FF",X"FF",X"FF",X"E0",X"E0",X"FC",X"F9",X"F1",X"E3",X"E7",X"FF",
+		X"07",X"07",X"3F",X"1F",X"8F",X"C7",X"E7",X"FF",X"E0",X"E0",X"FC",X"F8",X"F0",X"E2",X"E7",X"FF",
+		X"07",X"07",X"E7",X"E7",X"E7",X"07",X"0F",X"FF",X"FF",X"E0",X"E0",X"E6",X"E6",X"E6",X"E7",X"E7",
+		X"FF",X"07",X"07",X"67",X"67",X"67",X"E7",X"E7",X"FF",X"E0",X"E0",X"E7",X"E7",X"E3",X"F0",X"F8",
+		X"FF",X"07",X"07",X"E7",X"E7",X"C7",X"0F",X"1F",X"FF",X"C3",X"99",X"BD",X"BD",X"BD",X"99",X"C3",
+		X"FF",X"FF",X"FF",X"BB",X"81",X"BF",X"FF",X"FF",X"FF",X"9B",X"89",X"AD",X"AD",X"AD",X"A1",X"B3",
+		X"FF",X"DD",X"9D",X"B5",X"B5",X"B5",X"81",X"C9",X"FF",X"CF",X"C7",X"D3",X"D9",X"DD",X"81",X"DF",
+		X"FF",X"D1",X"95",X"B5",X"B5",X"B5",X"85",X"CF",X"FF",X"C3",X"91",X"B5",X"B5",X"B5",X"85",X"CF",
+		X"FF",X"FD",X"BD",X"9D",X"CD",X"E5",X"F1",X"F9",X"FF",X"CB",X"81",X"B5",X"B5",X"B5",X"81",X"CB",
+		X"FF",X"F3",X"A1",X"AD",X"AD",X"AD",X"89",X"C3",X"FF",X"87",X"D3",X"D9",X"DD",X"D9",X"D3",X"87",
+		X"FF",X"81",X"B5",X"B5",X"B5",X"B5",X"81",X"CB",X"FF",X"C3",X"99",X"BD",X"BD",X"BD",X"99",X"DB",
+		X"FF",X"81",X"BD",X"BD",X"BD",X"BD",X"99",X"C3",X"FF",X"81",X"B5",X"B5",X"B5",X"B5",X"BD",X"BD",
+		X"FF",X"81",X"F5",X"F5",X"F5",X"F5",X"FD",X"FD",X"FF",X"C3",X"99",X"BD",X"BD",X"AD",X"A9",X"8B",
+		X"FF",X"81",X"F7",X"F7",X"F7",X"F7",X"F7",X"81",X"FF",X"FF",X"FF",X"BD",X"81",X"BD",X"FF",X"FF",
+		X"FF",X"CF",X"9F",X"BF",X"BF",X"BF",X"9F",X"C1",X"FF",X"81",X"9F",X"CF",X"E7",X"D3",X"99",X"BD",
+		X"FF",X"81",X"BF",X"BF",X"BF",X"BF",X"BF",X"BF",X"FF",X"81",X"F3",X"E7",X"CF",X"E7",X"F3",X"81",
+		X"FF",X"81",X"F9",X"F3",X"E7",X"CF",X"9F",X"81",X"FF",X"C3",X"99",X"BD",X"BD",X"BD",X"99",X"C3",
+		X"FF",X"81",X"ED",X"ED",X"ED",X"ED",X"E1",X"F3",X"FF",X"C3",X"99",X"BD",X"AD",X"CD",X"99",X"A3",
+		X"FF",X"81",X"ED",X"ED",X"ED",X"8D",X"A1",X"B3",X"FF",X"DB",X"91",X"B5",X"A5",X"AD",X"89",X"DB",
+		X"FF",X"FD",X"FD",X"FD",X"81",X"FD",X"FD",X"FD",X"FF",X"C1",X"9F",X"BF",X"BF",X"BF",X"9F",X"C1",
+		X"FF",X"F1",X"C7",X"9F",X"BF",X"9F",X"C7",X"F1",X"FF",X"C1",X"9F",X"CF",X"E7",X"CF",X"9F",X"C1",
+		X"FF",X"BD",X"99",X"CB",X"E7",X"D3",X"99",X"BD",X"FF",X"F9",X"F3",X"E7",X"8F",X"E7",X"F3",X"F9",
+		X"FF",X"BD",X"9D",X"8D",X"A5",X"B1",X"B9",X"BD",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C3",X"BD",X"7E",X"7E",X"7E",X"7E",X"BD",X"C3",
+		X"C0",X"9F",X"1F",X"19",X"19",X"19",X"1F",X"0E",X"03",X"F9",X"F8",X"98",X"98",X"98",X"F8",X"70",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"1F",X"1F",X"19",X"19",X"19",X"18",X"18",
+		X"00",X"F8",X"F8",X"98",X"98",X"98",X"18",X"18",X"00",X"00",X"00",X"1F",X"1F",X"00",X"80",X"C0",
+		X"00",X"18",X"18",X"F8",X"F8",X"18",X"19",X"03",X"C0",X"9F",X"1F",X"18",X"18",X"1C",X"0F",X"07",
+		X"03",X"F9",X"F8",X"18",X"18",X"38",X"F0",X"E0",X"00",X"1F",X"1F",X"01",X"01",X"01",X"1F",X"1F",
+		X"00",X"F0",X"F8",X"98",X"98",X"98",X"F8",X"F0",X"00",X"1F",X"1F",X"18",X"18",X"18",X"98",X"C0",
+		X"00",X"F8",X"F8",X"00",X"00",X"00",X"01",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1K.vhd
new file mode 100644
index 00000000..bbfbe2d1
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_1K.vhd	
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity TRIPLEDRAWPOKER_1K is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(10 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of TRIPLEDRAWPOKER_1K is
+	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"07",X"0F",X"1F",X"3F",X"7F",X"FF",
+		X"FF",X"7F",X"3F",X"1F",X"0F",X"07",X"03",X"01",X"F0",X"F8",X"FC",X"FC",X"FC",X"F8",X"F0",X"E0",
+		X"E0",X"F0",X"F8",X"FC",X"FC",X"FC",X"F8",X"F0",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"00",X"00",X"60",X"70",X"78",X"7C",X"6E",X"67",
+		X"00",X"00",X"60",X"70",X"78",X"7C",X"7E",X"7F",X"00",X"00",X"1C",X"1E",X"1F",X"0F",X"07",X"07",
+		X"7F",X"77",X"73",X"71",X"70",X"70",X"70",X"00",X"87",X"C7",X"E7",X"FF",X"FF",X"7E",X"3C",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"18",X"38",X"78",X"70",X"70",X"71",X"00",X"00",X"0C",X"0E",X"0F",X"07",X"07",X"C7",
+		X"FF",X"E0",X"E0",X"FE",X"FE",X"FE",X"E0",X"E0",X"FF",X"07",X"07",X"7F",X"7F",X"7F",X"07",X"07",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"E0",X"E0",X"E6",X"E6",X"E6",X"E7",X"E7",X"FF",X"07",X"07",X"67",X"67",X"67",X"E7",X"E7",
+		X"00",X"0E",X"0F",X"0F",X"0F",X"0F",X"0E",X"0E",X"00",X"00",X"00",X"80",X"C0",X"E0",X"F0",X"78",
+		X"6E",X"6E",X"7F",X"7F",X"7F",X"6E",X"6E",X"00",X"3C",X"1E",X"FF",X"FF",X"FF",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"18",X"39",X"79",X"79",X"71",X"71",X"00",X"00",X"FF",X"FF",X"FF",X"C7",X"C7",X"C7",
+		X"FF",X"E0",X"E0",X"E7",X"E7",X"E7",X"E7",X"FF",X"C7",X"C7",X"C7",X"C7",X"C7",X"87",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"07",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"1F",X"3F",X"7F",X"7B",X"71",X"71",X"00",X"00",X"FC",X"FE",X"FF",X"EF",X"C7",X"C7",
+		X"07",X"07",X"E7",X"E7",X"C7",X"0F",X"1F",X"FF",X"C7",X"C7",X"C7",X"C7",X"CF",X"8E",X"0C",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"E0",X"E0",X"E7",X"E7",X"E3",X"F0",X"F8",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"60",X"78",X"7E",X"00",X"00",X"1F",X"1F",X"1F",X"07",X"07",X"07",
+		X"7F",X"1F",X"07",X"01",X"00",X"00",X"00",X"00",X"87",X"E7",X"FF",X"FF",X"7F",X"1F",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"1E",X"3F",X"7F",X"7B",X"71",X"71",X"00",X"00",X"3C",X"FE",X"FF",X"EF",X"C7",X"C7",
+		X"71",X"71",X"71",X"7B",X"7F",X"3F",X"1E",X"00",X"C7",X"C7",X"C7",X"EF",X"FF",X"FE",X"3C",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"18",X"38",X"79",X"71",X"71",X"71",X"00",X"00",X"7C",X"FE",X"FF",X"EF",X"C7",X"C7",
+		X"71",X"71",X"71",X"78",X"7F",X"3F",X"1F",X"00",X"C7",X"C7",X"C7",X"EF",X"FF",X"FE",X"FC",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"3F",X"3F",X"3F",X"00",X"00",X"1F",X"3F",X"00",X"FF",X"FF",X"FF",X"00",X"00",X"FE",X"FF",
+		X"3F",X"38",X"38",X"38",X"3F",X"3F",X"1F",X"00",X"FF",X"07",X"07",X"07",X"FF",X"FF",X"FE",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"0C",X"1C",X"3C",X"38",X"38",X"38",X"38",X"00",X"00",X"00",X"07",X"07",X"07",X"07",X"07",
+		X"3C",X"3F",X"1F",X"0F",X"00",X"00",X"00",X"00",X"07",X"FF",X"FF",X"FF",X"07",X"07",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"3F",X"7F",X"7F",X"78",X"70",X"70",X"00",X"00",X"FE",X"FF",X"FF",X"0F",X"07",X"E7",
+		X"71",X"7B",X"7F",X"7F",X"3F",X"1E",X"3C",X"38",X"E7",X"CF",X"FF",X"FF",X"FE",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"60",X"7F",X"7F",X"7F",X"63",X"01",X"03",X"00",X"03",X"FF",X"FF",X"FF",X"C3",X"E0",X"F0",
+		X"07",X"6F",X"7E",X"7C",X"78",X"70",X"60",X"00",X"FB",X"3F",X"1F",X"0F",X"07",X"03",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"60",X"7C",X"7F",X"7F",X"67",X"07",X"06",X"06",X"00",X"00",X"00",X"C0",X"F0",X"FC",X"3F",X"1F",
+		X"06",X"06",X"07",X"67",X"7F",X"7F",X"7C",X"60",X"1F",X"3F",X"FC",X"F0",X"C0",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"01",X"03",X"07",X"0F",X"1F",X"3F",X"7F",X"FF",X"00",X"80",X"C0",X"E0",X"F0",X"F8",X"FC",X"FE",
+		X"FF",X"7F",X"3F",X"1F",X"0F",X"07",X"03",X"01",X"FE",X"FC",X"F8",X"F0",X"E0",X"C0",X"80",X"00",
+		X"83",X"43",X"24",X"18",X"18",X"24",X"42",X"81",X"81",X"42",X"24",X"18",X"18",X"24",X"43",X"83",
+		X"C1",X"C2",X"24",X"18",X"18",X"24",X"42",X"81",X"81",X"42",X"24",X"18",X"18",X"24",X"C2",X"C1",
+		X"81",X"42",X"24",X"18",X"18",X"24",X"42",X"81",X"81",X"42",X"24",X"18",X"18",X"00",X"00",X"81",
+		X"81",X"00",X"00",X"00",X"00",X"00",X"00",X"81",X"81",X"00",X"00",X"00",X"00",X"00",X"00",X"81",
+		X"80",X"00",X"00",X"18",X"18",X"24",X"42",X"81",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"03",X"1F",X"1F",X"03",X"07",X"0F",X"1D",X"18",X"00",
+		X"F8",X"F8",X"18",X"18",X"18",X"F8",X"F0",X"00",X"00",X"1F",X"1F",X"19",X"19",X"19",X"18",X"18",
+		X"00",X"F8",X"F8",X"98",X"98",X"98",X"18",X"18",X"00",X"1F",X"1F",X"18",X"18",X"1C",X"0F",X"07",
+		X"00",X"F8",X"F8",X"18",X"18",X"38",X"F0",X"E0",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"E7",X"DB",X"DB",X"DB",X"FF",X"FF",
+		X"FF",X"E0",X"E0",X"E6",X"E6",X"E6",X"E0",X"F1",X"FF",X"07",X"07",X"67",X"67",X"67",X"07",X"8F",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"E0",X"E0",X"E6",X"E6",X"E6",X"E7",X"E7",
+		X"FF",X"07",X"07",X"67",X"67",X"67",X"E7",X"E7",X"FF",X"FF",X"FF",X"E0",X"E0",X"FF",X"FF",X"FF",
+		X"FF",X"E7",X"E7",X"07",X"07",X"E7",X"E7",X"FF",X"FF",X"E0",X"E0",X"E7",X"E7",X"E3",X"F0",X"F8",
+		X"FF",X"07",X"07",X"E7",X"E7",X"C7",X"0F",X"1F",X"FF",X"E0",X"E0",X"FE",X"FE",X"FE",X"E0",X"E0",
+		X"FF",X"0F",X"07",X"67",X"67",X"67",X"07",X"0F",X"FF",X"E0",X"E0",X"E7",X"E7",X"E7",X"E7",X"FF",
+		X"FF",X"07",X"07",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_6L.vhd
new file mode 100644
index 00000000..bf710e68
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_6L.vhd	
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity TRIPLEDRAWPOKER_6L is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(4 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of TRIPLEDRAWPOKER_6L is
+	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"C0",X"07",X"FF",X"00",X"00",X"07",X"FF",X"C0",X"00",X"3F",X"07",X"C0",X"00",X"17",X"3F",X"C0",
+		X"00",X"C7",X"3F",X"C0",X"00",X"38",X"3F",X"C0",X"00",X"3F",X"17",X"C0",X"00",X"07",X"F8",X"C0");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_ROM_PGM_0.vhd
new file mode 100644
index 00000000..a9eb6f48
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/tripledrawpoker/TRIPLEDRAWPOKER_ROM_PGM_0.vhd	
@@ -0,0 +1,790 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity TRIPLEDRAWPOKER_ROM_PGM_0 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(13 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of TRIPLEDRAWPOKER_ROM_PGM_0 is
+	type rom is array(0 to  12287) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"ED",X"56",X"31",X"00",X"44",X"C3",X"7B",X"00",X"E5",X"C5",X"F5",X"04",X"0C",X"C3",X"71",X"00",
+		X"85",X"6F",X"30",X"01",X"24",X"7E",X"C9",X"FF",X"E5",X"B7",X"ED",X"52",X"E1",X"C9",X"28",X"28",
+		X"E5",X"77",X"23",X"10",X"FC",X"E1",X"C9",X"AD",X"E1",X"87",X"85",X"6F",X"30",X"3C",X"18",X"39",
+		X"47",X"00",X"FD",X"36",X"41",X"00",X"28",X"E1",X"C3",X"29",X"0B",X"D5",X"F5",X"BE",X"30",X"05",
+		X"16",X"00",X"5F",X"19",X"19",X"23",X"5E",X"23",X"56",X"EB",X"F1",X"D1",X"E9",X"A7",X"C8",X"E5",
+		X"D5",X"C5",X"06",X"00",X"4F",X"09",X"EB",X"09",X"41",X"1B",X"2B",X"1A",X"BE",X"20",X"02",X"10",
+		X"F8",X"79",X"C1",X"D1",X"E1",X"C9",X"C3",X"27",X"08",X"24",X"7E",X"23",X"66",X"6F",X"E9",X"77",
+		X"23",X"0D",X"C2",X"6F",X"00",X"10",X"F8",X"F1",X"C1",X"E1",X"C9",X"FD",X"21",X"8E",X"40",X"21",
+		X"84",X"00",X"18",X"04",X"CD",X"BC",X"00",X"E9",X"F3",X"CD",X"6C",X"0A",X"01",X"00",X"04",X"11",
+		X"00",X"40",X"AF",X"CD",X"7B",X"0A",X"12",X"13",X"0D",X"20",X"FB",X"10",X"F6",X"CD",X"35",X"07",
+		X"CD",X"DD",X"02",X"CD",X"8E",X"04",X"CD",X"2E",X"06",X"CD",X"FC",X"15",X"CD",X"C2",X"02",X"28",
+		X"07",X"38",X"05",X"CD",X"C1",X"08",X"18",X"03",X"CD",X"BA",X"08",X"E9",X"F5",X"18",X"1C",X"D5",
+		X"E5",X"FD",X"E5",X"D1",X"21",X"02",X"00",X"7D",X"21",X"00",X"00",X"19",X"36",X"00",X"21",X"48",
+		X"00",X"19",X"EB",X"3D",X"20",X"F2",X"CD",X"AE",X"0E",X"E1",X"D1",X"3A",X"45",X"40",X"E6",X"08",
+		X"20",X"06",X"CD",X"AE",X"02",X"28",X"D8",X"AF",X"CD",X"A9",X"01",X"CD",X"F0",X"00",X"F1",X"C9",
+		X"FD",X"E5",X"E5",X"D5",X"C5",X"F5",X"01",X"02",X"00",X"41",X"4F",X"FD",X"E5",X"D1",X"AF",X"C5",
+		X"21",X"02",X"00",X"19",X"01",X"07",X"04",X"48",X"06",X"00",X"CF",X"21",X"02",X"00",X"19",X"CF",
+		X"21",X"48",X"00",X"19",X"EB",X"C1",X"10",X"E7",X"FD",X"E5",X"D1",X"41",X"3A",X"4A",X"40",X"21",
+		X"01",X"00",X"19",X"77",X"79",X"90",X"3C",X"21",X"00",X"00",X"19",X"77",X"21",X"48",X"00",X"19",
+		X"EB",X"05",X"20",X"E8",X"CD",X"DF",X"18",X"41",X"FD",X"E5",X"D1",X"FD",X"E5",X"AF",X"21",X"01",
+		X"00",X"19",X"BE",X"28",X"2E",X"21",X"01",X"00",X"19",X"35",X"79",X"90",X"3C",X"21",X"00",X"00",
+		X"19",X"77",X"D5",X"FD",X"E1",X"C5",X"CD",X"2A",X"03",X"CD",X"96",X"28",X"C1",X"21",X"01",X"00",
+		X"19",X"7E",X"A7",X"20",X"0E",X"79",X"90",X"3C",X"D5",X"FD",X"E1",X"C5",X"CD",X"2A",X"03",X"CD",
+		X"D0",X"11",X"C1",X"21",X"48",X"00",X"19",X"EB",X"10",X"C3",X"D1",X"D5",X"AF",X"41",X"21",X"01",
+		X"00",X"19",X"BE",X"20",X"C0",X"21",X"48",X"00",X"19",X"EB",X"10",X"F2",X"FD",X"E1",X"41",X"11",
+		X"48",X"00",X"79",X"90",X"3C",X"CD",X"15",X"06",X"FD",X"19",X"10",X"F6",X"CD",X"35",X"0B",X"CD",
+		X"D3",X"10",X"F1",X"C1",X"D1",X"E1",X"FD",X"E1",X"C9",X"E5",X"C5",X"F5",X"4F",X"06",X"FF",X"18",
+		X"0B",X"CD",X"15",X"08",X"CD",X"AE",X"02",X"CD",X"58",X"12",X"06",X"00",X"CD",X"81",X"0A",X"28",
+		X"F0",X"0C",X"0D",X"20",X"16",X"6F",X"CD",X"AE",X"02",X"BD",X"38",X"E5",X"CD",X"15",X"08",X"45",
+		X"CD",X"8F",X"02",X"10",X"FB",X"7D",X"21",X"45",X"40",X"CB",X"E6",X"6F",X"F1",X"7D",X"C1",X"E1",
+		X"C9",X"E5",X"F5",X"21",X"45",X"40",X"3A",X"3D",X"40",X"E6",X"03",X"FE",X"03",X"20",X"0F",X"7E",
+		X"E6",X"40",X"28",X"3C",X"D5",X"11",X"8E",X"40",X"CD",X"47",X"03",X"D1",X"18",X"32",X"FE",X"01",
+		X"20",X"2E",X"7E",X"E6",X"30",X"FE",X"30",X"20",X"27",X"CB",X"A6",X"D5",X"C5",X"21",X"44",X"40",
+		X"ED",X"5B",X"CA",X"12",X"01",X"02",X"01",X"CD",X"FC",X"08",X"7A",X"C6",X"10",X"57",X"3A",X"45",
+		X"40",X"E6",X"02",X"3E",X"20",X"28",X"04",X"01",X"20",X"00",X"79",X"CD",X"CC",X"0B",X"C1",X"D1",
+		X"CD",X"65",X"04",X"F1",X"E1",X"C9",X"F5",X"CD",X"7A",X"08",X"28",X"14",X"E5",X"21",X"45",X"40",
+		X"CB",X"5E",X"20",X"0B",X"CD",X"52",X"02",X"3D",X"20",X"FA",X"CB",X"E6",X"CD",X"3F",X"1C",X"E1",
+		X"F1",X"C9",X"E5",X"D5",X"C5",X"F5",X"11",X"44",X"40",X"21",X"45",X"40",X"CB",X"56",X"28",X"13",
+		X"1A",X"FE",X"99",X"38",X"04",X"CB",X"CE",X"18",X"21",X"CB",X"4E",X"20",X"04",X"CB",X"CE",X"18",
+		X"19",X"CB",X"8E",X"7E",X"E6",X"01",X"3C",X"47",X"1A",X"80",X"27",X"30",X"02",X"3E",X"99",X"12",
+		X"4F",X"AF",X"90",X"27",X"47",X"79",X"B8",X"D4",X"C1",X"08",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",
+		X"F5",X"21",X"44",X"40",X"3A",X"45",X"40",X"E6",X"01",X"28",X"05",X"7E",X"FE",X"99",X"30",X"03",
+		X"CD",X"BA",X"08",X"7E",X"A7",X"28",X"03",X"D6",X"01",X"27",X"77",X"F1",X"E1",X"C9",X"3A",X"44",
+		X"40",X"A7",X"C0",X"3A",X"45",X"40",X"E6",X"04",X"C8",X"3A",X"45",X"40",X"E6",X"02",X"C8",X"AF",
+		X"37",X"C9",X"C5",X"4F",X"3A",X"45",X"40",X"47",X"E6",X"08",X"20",X"0E",X"78",X"E6",X"01",X"20",
+		X"05",X"78",X"E6",X"04",X"20",X"03",X"37",X"18",X"01",X"AF",X"79",X"C1",X"C9",X"F5",X"AF",X"32",
+		X"44",X"40",X"3E",X"01",X"CD",X"F0",X"0A",X"3E",X"02",X"20",X"0C",X"CD",X"F0",X"0A",X"20",X"03",
+		X"AF",X"18",X"0F",X"3E",X"01",X"18",X"0B",X"CD",X"F0",X"0A",X"20",X"04",X"3E",X"04",X"18",X"02",
+		X"3E",X"08",X"32",X"45",X"40",X"3E",X"06",X"CD",X"F0",X"0A",X"28",X"08",X"3A",X"45",X"40",X"F6",
+		X"80",X"32",X"45",X"40",X"F1",X"C9",X"E5",X"21",X"45",X"40",X"CB",X"E6",X"CB",X"EE",X"E1",X"C9",
+		X"E5",X"21",X"45",X"40",X"CB",X"A6",X"CB",X"AE",X"E1",X"C9",X"E5",X"F5",X"21",X"45",X"40",X"CB",
+		X"7E",X"28",X"0C",X"3D",X"E6",X"01",X"28",X"07",X"06",X"02",X"CD",X"2B",X"0B",X"18",X"05",X"06",
+		X"01",X"CD",X"35",X"0B",X"F1",X"E1",X"C9",X"C5",X"01",X"02",X"00",X"41",X"21",X"00",X"00",X"19",
+		X"7E",X"A7",X"28",X"2F",X"3D",X"4F",X"D5",X"C5",X"21",X"02",X"00",X"19",X"EB",X"01",X"02",X"00",
+		X"09",X"01",X"07",X"04",X"78",X"CD",X"DC",X"03",X"C1",X"28",X"17",X"C5",X"06",X"00",X"21",X"CE",
+		X"12",X"09",X"09",X"7E",X"23",X"66",X"6F",X"01",X"07",X"04",X"EB",X"CD",X"FC",X"08",X"C1",X"CD",
+		X"A8",X"1D",X"D1",X"21",X"48",X"00",X"19",X"EB",X"10",X"C2",X"C1",X"C9",X"F5",X"BE",X"30",X"2F",
+		X"C5",X"D5",X"E5",X"EB",X"21",X"00",X"00",X"FD",X"E5",X"C1",X"09",X"4F",X"7E",X"A7",X"28",X"1C",
+		X"EB",X"06",X"00",X"09",X"09",X"23",X"4E",X"23",X"46",X"11",X"02",X"00",X"FD",X"E5",X"E1",X"19",
+		X"11",X"07",X"04",X"7A",X"54",X"5D",X"CD",X"C1",X"03",X"CD",X"D2",X"10",X"E1",X"D1",X"C1",X"F1",
+		X"C9",X"A7",X"C8",X"E5",X"D5",X"C5",X"F5",X"F5",X"0A",X"8E",X"27",X"12",X"03",X"13",X"23",X"E3",
+		X"25",X"E3",X"C2",X"C8",X"03",X"E1",X"E1",X"7C",X"C1",X"D1",X"E1",X"C9",X"A7",X"C8",X"E5",X"D5",
+		X"C5",X"F5",X"0E",X"00",X"47",X"1A",X"BE",X"28",X"2E",X"0C",X"C5",X"4F",X"46",X"C5",X"E6",X"F0",
+		X"4F",X"78",X"E6",X"F0",X"B9",X"C1",X"79",X"28",X"10",X"C6",X"10",X"27",X"4F",X"C5",X"E6",X"0F",
+		X"4F",X"78",X"E6",X"0F",X"B9",X"C1",X"79",X"28",X"0C",X"E6",X"F0",X"47",X"79",X"E6",X"0F",X"C6",
+		X"01",X"27",X"E6",X"0F",X"B0",X"12",X"C1",X"13",X"23",X"10",X"CA",X"79",X"C1",X"A7",X"78",X"C1",
+		X"D1",X"E1",X"C9",X"E5",X"21",X"45",X"40",X"CB",X"F6",X"E1",X"C9",X"E5",X"21",X"45",X"40",X"CB",
+		X"B6",X"E1",X"C9",X"F5",X"A7",X"28",X"2C",X"E5",X"D5",X"C5",X"47",X"0E",X"00",X"21",X"8E",X"40",
+		X"11",X"02",X"00",X"19",X"C5",X"EB",X"06",X"00",X"21",X"CE",X"12",X"09",X"09",X"7E",X"23",X"66",
+		X"6F",X"01",X"07",X"04",X"EB",X"CD",X"FC",X"08",X"11",X"48",X"00",X"19",X"C1",X"0C",X"10",X"E4",
+		X"C1",X"D1",X"E1",X"F1",X"C9",X"21",X"3D",X"40",X"34",X"23",X"7E",X"3C",X"FE",X"3C",X"38",X"1C",
+		X"36",X"00",X"23",X"7E",X"3C",X"FE",X"3C",X"38",X"13",X"36",X"00",X"23",X"7E",X"3C",X"FE",X"3C",
+		X"38",X"0A",X"36",X"00",X"23",X"7E",X"3C",X"FE",X"18",X"38",X"01",X"AF",X"77",X"C9",X"E5",X"F5",
+		X"21",X"3D",X"40",X"AF",X"77",X"23",X"77",X"23",X"77",X"23",X"77",X"23",X"77",X"F1",X"E1",X"C9",
+		X"21",X"3D",X"40",X"23",X"5E",X"23",X"56",X"23",X"7E",X"23",X"66",X"6F",X"3A",X"3D",X"40",X"C9",
+		X"F5",X"C5",X"4F",X"7E",X"A7",X"28",X"38",X"D5",X"E5",X"47",X"23",X"7E",X"23",X"A1",X"BE",X"23",
+		X"20",X"08",X"23",X"5E",X"23",X"56",X"23",X"23",X"18",X"09",X"BE",X"20",X"1A",X"23",X"23",X"23",
+		X"5E",X"23",X"56",X"23",X"C5",X"4E",X"23",X"46",X"23",X"7E",X"23",X"E5",X"66",X"6F",X"EB",X"CD",
+		X"E2",X"0B",X"E1",X"23",X"C1",X"18",X"04",X"11",X"09",X"00",X"19",X"10",X"CE",X"E1",X"D1",X"C1",
+		X"F1",X"C9",X"F5",X"7E",X"A7",X"28",X"23",X"C5",X"D5",X"E5",X"47",X"23",X"23",X"23",X"23",X"5E",
+		X"23",X"56",X"23",X"23",X"23",X"C5",X"4E",X"23",X"46",X"23",X"7E",X"23",X"E5",X"66",X"6F",X"EB",
+		X"CD",X"E2",X"0B",X"E1",X"C1",X"10",X"E4",X"E1",X"D1",X"C1",X"F1",X"C9",X"E5",X"C5",X"4F",X"B7",
+		X"CD",X"2C",X"05",X"1F",X"FE",X"64",X"30",X"F8",X"B9",X"C1",X"E1",X"C9",X"E5",X"D5",X"2A",X"48",
+		X"40",X"5E",X"23",X"56",X"3E",X"F1",X"CD",X"93",X"05",X"7B",X"C6",X"19",X"5F",X"7A",X"CE",X"36",
+		X"77",X"2B",X"73",X"D1",X"E1",X"C9",X"E5",X"2A",X"48",X"40",X"36",X"36",X"23",X"36",X"23",X"E1",
+		X"C9",X"E5",X"C5",X"F5",X"42",X"4B",X"11",X"00",X"00",X"CB",X"38",X"79",X"1F",X"4F",X"30",X"03",
+		X"EB",X"19",X"EB",X"29",X"B0",X"C2",X"59",X"05",X"F1",X"C1",X"E1",X"C9",X"F5",X"C5",X"7C",X"2F",
+		X"47",X"7D",X"2F",X"4F",X"03",X"21",X"00",X"00",X"3E",X"11",X"E5",X"09",X"30",X"01",X"E3",X"E1",
+		X"CB",X"13",X"CB",X"12",X"CB",X"15",X"CB",X"14",X"3D",X"C2",X"7A",X"05",X"CB",X"1C",X"CB",X"1D",
+		X"C1",X"F1",X"C9",X"E5",X"F5",X"EB",X"11",X"00",X"00",X"B7",X"1F",X"30",X"03",X"EB",X"19",X"EB",
+		X"29",X"B7",X"C2",X"9A",X"05",X"F1",X"E1",X"C9",X"E5",X"C5",X"F5",X"FD",X"E5",X"C1",X"21",X"02",
+		X"00",X"09",X"EB",X"01",X"07",X"04",X"78",X"01",X"0A",X"00",X"04",X"CD",X"4D",X"00",X"38",X"0E",
+		X"D5",X"11",X"09",X"00",X"19",X"D1",X"0D",X"20",X"F2",X"10",X"F0",X"04",X"18",X"2E",X"05",X"0B",
+		X"78",X"B1",X"28",X"1B",X"D5",X"E5",X"E5",X"60",X"69",X"11",X"09",X"00",X"CD",X"51",X"05",X"42",
+		X"4B",X"D1",X"21",X"09",X"00",X"19",X"09",X"2B",X"EB",X"09",X"2B",X"ED",X"B8",X"E1",X"D1",X"EB",
+		X"01",X"07",X"04",X"48",X"06",X"00",X"ED",X"B0",X"CD",X"0B",X"07",X"BF",X"C1",X"78",X"C1",X"E1",
+		X"C9",X"E5",X"D5",X"C5",X"2A",X"CC",X"12",X"EB",X"2A",X"46",X"40",X"01",X"07",X"04",X"CD",X"FC",
+		X"08",X"C1",X"D1",X"E1",X"C9",X"D5",X"C5",X"F5",X"ED",X"5B",X"46",X"40",X"CD",X"A8",X"05",X"20",
+		X"09",X"CD",X"2A",X"03",X"CD",X"1B",X"19",X"CD",X"0B",X"07",X"F1",X"C1",X"D1",X"C9",X"E5",X"D5",
+		X"C5",X"F5",X"21",X"04",X"48",X"01",X"FC",X"03",X"CD",X"F9",X"06",X"21",X"00",X"48",X"BE",X"20",
+		X"2E",X"01",X"02",X"00",X"21",X"04",X"48",X"06",X"0A",X"11",X"66",X"00",X"79",X"4E",X"B9",X"28",
+		X"11",X"0C",X"0D",X"28",X"4B",X"19",X"10",X"F5",X"01",X"00",X"04",X"21",X"00",X"48",X"AF",X"CF",
+		X"18",X"28",X"23",X"22",X"46",X"40",X"21",X"02",X"48",X"22",X"48",X"40",X"C3",X"F4",X"06",X"AF",
+		X"CD",X"7B",X"0A",X"C6",X"08",X"21",X"00",X"48",X"01",X"05",X"01",X"18",X"05",X"77",X"BE",X"20",
+		X"32",X"23",X"10",X"F9",X"0D",X"20",X"F6",X"A7",X"20",X"E6",X"21",X"04",X"48",X"01",X"02",X"00",
+		X"71",X"23",X"22",X"46",X"40",X"21",X"02",X"48",X"22",X"48",X"40",X"CD",X"46",X"05",X"18",X"4E",
+		X"77",X"23",X"22",X"46",X"40",X"21",X"02",X"48",X"22",X"48",X"40",X"CD",X"36",X"16",X"CD",X"0B",
+		X"07",X"18",X"41",X"21",X"84",X"58",X"01",X"66",X"00",X"CD",X"F9",X"06",X"01",X"02",X"00",X"21",
+		X"80",X"58",X"BE",X"20",X"14",X"3A",X"84",X"58",X"B9",X"20",X"0E",X"21",X"85",X"58",X"22",X"46",
+		X"40",X"21",X"42",X"40",X"22",X"48",X"40",X"18",X"1B",X"21",X"80",X"58",X"06",X"6A",X"AF",X"E7",
+		X"21",X"84",X"58",X"71",X"23",X"22",X"46",X"40",X"21",X"42",X"40",X"22",X"48",X"40",X"CD",X"36",
+		X"16",X"CD",X"0B",X"07",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"C5",X"3E",X"A5",X"04",X"0C",X"18",
+		X"02",X"86",X"23",X"0D",X"20",X"FB",X"10",X"F9",X"C1",X"E1",X"C9",X"E5",X"C5",X"F5",X"2A",X"46",
+		X"40",X"01",X"00",X"4C",X"B7",X"ED",X"42",X"21",X"04",X"48",X"01",X"FC",X"03",X"38",X"06",X"21",
+		X"84",X"58",X"01",X"66",X"00",X"CD",X"F9",X"06",X"01",X"FC",X"FF",X"09",X"77",X"F1",X"C1",X"E1",
+		X"C9",X"2A",X"46",X"40",X"C9",X"E5",X"C5",X"F5",X"01",X"04",X"80",X"21",X"00",X"58",X"AF",X"E7",
+		X"06",X"08",X"7C",X"80",X"67",X"0D",X"20",X"F6",X"3E",X"FF",X"ED",X"47",X"77",X"3E",X"20",X"CD",
+		X"BD",X"09",X"CD",X"35",X"0B",X"CD",X"73",X"0A",X"CD",X"E1",X"1A",X"CD",X"15",X"08",X"CD",X"13",
+		X"0C",X"20",X"D5",X"F1",X"C1",X"E1",X"C9",X"E5",X"C5",X"F5",X"21",X"00",X"40",X"06",X"20",X"AF",
+		X"E7",X"3E",X"FC",X"32",X"21",X"40",X"3E",X"1C",X"32",X"20",X"40",X"21",X"22",X"40",X"06",X"10",
+		X"AF",X"E7",X"32",X"32",X"40",X"3E",X"FE",X"32",X"34",X"40",X"3E",X"0C",X"32",X"33",X"40",X"F1",
+		X"C1",X"E1",X"C9",X"21",X"00",X"40",X"11",X"40",X"58",X"01",X"20",X"00",X"ED",X"B0",X"21",X"22",
+		X"40",X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",
+		X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",
+		X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",X"ED",X"A0",X"1C",X"7E",
+		X"12",X"C9",X"E5",X"C5",X"F5",X"21",X"20",X"40",X"06",X"00",X"4E",X"3E",X"1C",X"91",X"28",X"11",
+		X"CB",X"3F",X"CB",X"3F",X"36",X"1C",X"21",X"04",X"40",X"09",X"0E",X"04",X"70",X"09",X"3D",X"20",
+		X"FB",X"3A",X"32",X"40",X"A7",X"20",X"03",X"32",X"30",X"40",X"21",X"33",X"40",X"4E",X"3E",X"0C",
+		X"91",X"28",X"0E",X"CB",X"3F",X"36",X"0C",X"21",X"24",X"40",X"09",X"70",X"23",X"23",X"3D",X"20",
+		X"FA",X"F1",X"C1",X"E1",X"C9",X"F5",X"3A",X"00",X"78",X"ED",X"57",X"A7",X"20",X"01",X"76",X"CD",
+		X"D2",X"07",X"CD",X"E1",X"01",X"F1",X"C9",X"E5",X"D5",X"C5",X"F5",X"CD",X"6C",X"0A",X"CD",X"93",
+		X"07",X"CD",X"36",X"02",X"CD",X"C9",X"08",X"CD",X"EC",X"1A",X"CD",X"51",X"08",X"CD",X"73",X"0A",
+		X"F1",X"C1",X"D1",X"E1",X"ED",X"45",X"C5",X"4F",X"7B",X"B2",X"A1",X"4F",X"7B",X"A2",X"B1",X"C1",
+		X"C9",X"3A",X"3A",X"40",X"5F",X"3A",X"00",X"60",X"57",X"32",X"3A",X"40",X"3A",X"3C",X"40",X"CD",
+		X"46",X"08",X"32",X"3C",X"40",X"3A",X"39",X"40",X"5F",X"3A",X"00",X"68",X"57",X"32",X"39",X"40",
+		X"3A",X"3B",X"40",X"CD",X"46",X"08",X"32",X"3B",X"40",X"C9",X"E5",X"C5",X"21",X"35",X"40",X"01",
+		X"00",X"02",X"78",X"CD",X"16",X"0B",X"28",X"0C",X"7E",X"F6",X"80",X"77",X"FE",X"A1",X"30",X"22",
+		X"3C",X"77",X"18",X"1E",X"7E",X"A7",X"28",X"1A",X"CB",X"BE",X"CB",X"7F",X"20",X"14",X"FE",X"02",
+		X"38",X"0E",X"FE",X"21",X"30",X"0A",X"0C",X"3A",X"37",X"40",X"3C",X"28",X"03",X"32",X"37",X"40",
+		X"36",X"00",X"23",X"10",X"CD",X"79",X"A7",X"C1",X"E1",X"C9",X"F5",X"AF",X"32",X"05",X"70",X"F1",
+		X"C9",X"F5",X"3E",X"FF",X"32",X"05",X"70",X"F1",X"C9",X"3A",X"38",X"40",X"A7",X"28",X"19",X"FE",
+		X"10",X"38",X"10",X"D6",X"10",X"32",X"38",X"40",X"C0",X"3E",X"04",X"32",X"38",X"40",X"AF",X"32",
+		X"03",X"60",X"C9",X"3D",X"32",X"38",X"40",X"C9",X"3A",X"37",X"40",X"A7",X"C8",X"3D",X"32",X"37",
+		X"40",X"3E",X"40",X"32",X"38",X"40",X"3E",X"FF",X"32",X"03",X"60",X"C9",X"E5",X"D5",X"C5",X"F5",
+		X"79",X"87",X"87",X"87",X"82",X"57",X"78",X"A7",X"79",X"20",X"11",X"A7",X"28",X"61",X"7A",X"C6",
+		X"F8",X"57",X"3E",X"30",X"CD",X"CC",X"0B",X"0D",X"28",X"55",X"18",X"3E",X"A7",X"28",X"49",X"7A",
+		X"C6",X"F8",X"57",X"7E",X"E6",X"0F",X"C6",X"30",X"CD",X"CC",X"0B",X"0D",X"28",X"3A",X"7A",X"C6",
+		X"F8",X"57",X"7E",X"E6",X"F0",X"0F",X"0F",X"0F",X"0F",X"28",X"0F",X"C6",X"30",X"CD",X"CC",X"0B",
+		X"0D",X"28",X"29",X"CD",X"75",X"09",X"28",X"12",X"18",X"0D",X"CD",X"75",X"09",X"28",X"0F",X"C6",
+		X"30",X"CD",X"CC",X"0B",X"0D",X"28",X"15",X"23",X"10",X"C5",X"7A",X"C6",X"F8",X"57",X"3E",X"20",
+		X"CD",X"CC",X"0B",X"0D",X"20",X"F4",X"18",X"07",X"AF",X"BE",X"20",X"03",X"23",X"10",X"F9",X"C1",
+		X"78",X"C1",X"D1",X"E1",X"C9",X"E5",X"C5",X"4F",X"AF",X"18",X"04",X"23",X"BE",X"20",X"02",X"10",
+		X"FA",X"79",X"C1",X"E1",X"C9",X"E5",X"D5",X"C5",X"4F",X"47",X"87",X"87",X"87",X"82",X"57",X"7A",
+		X"D6",X"08",X"57",X"D5",X"EB",X"21",X"0A",X"00",X"CD",X"6C",X"05",X"7D",X"C6",X"30",X"EB",X"D1",
+		X"CD",X"CC",X"0B",X"7D",X"B4",X"28",X"04",X"10",X"E6",X"18",X"0D",X"05",X"28",X"0A",X"7A",X"D6",
+		X"08",X"57",X"3E",X"20",X"CD",X"CC",X"0B",X"BF",X"79",X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",
+		X"F5",X"21",X"B2",X"12",X"4F",X"06",X"00",X"09",X"4E",X"21",X"00",X"50",X"71",X"11",X"01",X"50",
+		X"01",X"FF",X"03",X"ED",X"B0",X"CD",X"67",X"07",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"F5",
+		X"C5",X"CB",X"38",X"CB",X"38",X"CB",X"38",X"28",X"7E",X"CB",X"39",X"CB",X"39",X"CB",X"39",X"28",
+		X"76",X"D5",X"21",X"B2",X"12",X"85",X"6F",X"30",X"01",X"24",X"7E",X"F5",X"CD",X"AE",X"0B",X"F1",
+		X"16",X"00",X"E5",X"59",X"77",X"23",X"1D",X"20",X"FB",X"E1",X"1E",X"20",X"19",X"10",X"F3",X"D1",
+		X"3A",X"21",X"40",X"C6",X"04",X"E6",X"3C",X"28",X"4E",X"0F",X"0F",X"C1",X"C5",X"F5",X"78",X"B7",
+		X"1F",X"82",X"C6",X"16",X"2F",X"57",X"79",X"B7",X"1F",X"83",X"C6",X"F8",X"5F",X"78",X"C6",X"10",
+		X"47",X"79",X"C6",X"10",X"4F",X"21",X"00",X"40",X"F1",X"F5",X"7A",X"96",X"E5",X"6F",X"78",X"CB",
+		X"3F",X"85",X"E1",X"23",X"23",X"23",X"B8",X"30",X"19",X"7B",X"96",X"E5",X"6F",X"79",X"CB",X"3F",
+		X"85",X"E1",X"B9",X"30",X"0D",X"E5",X"D5",X"C5",X"CD",X"96",X"0E",X"C1",X"D1",X"E1",X"2B",X"2B",
+		X"2B",X"2B",X"23",X"F1",X"3D",X"20",X"D2",X"C1",X"F1",X"D1",X"E1",X"C9",X"F5",X"AF",X"32",X"01",
+		X"70",X"F1",X"C9",X"F5",X"3E",X"FF",X"32",X"01",X"70",X"F1",X"C9",X"F5",X"3A",X"00",X"78",X"F1",
+		X"C9",X"3A",X"3B",X"40",X"E6",X"01",X"20",X"09",X"3A",X"3B",X"40",X"E6",X"02",X"C8",X"3E",X"02",
+		X"C9",X"3E",X"01",X"C9",X"F5",X"E5",X"3D",X"20",X"30",X"21",X"D5",X"0A",X"3A",X"3C",X"40",X"57",
+		X"A6",X"23",X"20",X"15",X"7A",X"A6",X"20",X"15",X"1E",X"00",X"23",X"7A",X"A6",X"20",X"12",X"23",
+		X"7A",X"A6",X"20",X"11",X"16",X"00",X"E1",X"F1",X"C9",X"1E",X"01",X"18",X"ED",X"1E",X"FF",X"18",
+		X"E9",X"16",X"01",X"18",X"F1",X"16",X"FF",X"18",X"ED",X"21",X"D9",X"0A",X"3A",X"3B",X"40",X"57",
+		X"3A",X"3C",X"40",X"18",X"CB",X"80",X"20",X"08",X"04",X"40",X"20",X"08",X"04",X"3D",X"28",X"08",
+		X"3A",X"3B",X"40",X"E6",X"10",X"3E",X"02",X"C9",X"3A",X"3C",X"40",X"E6",X"10",X"3E",X"01",X"C9",
+		X"E5",X"C5",X"F5",X"E6",X"07",X"4F",X"FE",X"03",X"30",X"05",X"3A",X"00",X"68",X"18",X"03",X"3A",
+		X"00",X"70",X"47",X"79",X"21",X"0E",X"0B",X"D7",X"A0",X"C1",X"78",X"C1",X"E1",X"C9",X"00",X"40",
+		X"80",X"01",X"02",X"04",X"08",X"00",X"3D",X"28",X"08",X"3A",X"00",X"60",X"E6",X"02",X"3E",X"02",
+		X"C9",X"3A",X"00",X"60",X"E6",X"01",X"3E",X"01",X"C9",X"ED",X"4D",X"F5",X"AF",X"32",X"07",X"70",
+		X"32",X"06",X"70",X"F1",X"C9",X"F5",X"3E",X"FF",X"32",X"07",X"70",X"32",X"06",X"70",X"F1",X"C9",
+		X"04",X"05",X"C8",X"E5",X"C5",X"67",X"79",X"E6",X"F8",X"0F",X"0F",X"6F",X"7C",X"26",X"58",X"77",
+		X"2C",X"2C",X"10",X"FB",X"C1",X"E1",X"C9",X"E5",X"E6",X"F8",X"0F",X"0F",X"6F",X"26",X"58",X"7E",
+		X"E1",X"C9",X"E5",X"C5",X"4C",X"21",X"00",X"58",X"06",X"20",X"71",X"23",X"23",X"10",X"FB",X"C1",
+		X"E1",X"C9",X"E5",X"C5",X"F5",X"6F",X"26",X"00",X"29",X"01",X"DB",X"15",X"09",X"7E",X"23",X"66",
+		X"6F",X"7E",X"CB",X"6F",X"20",X"18",X"D5",X"E6",X"1F",X"3C",X"47",X"16",X"58",X"23",X"7E",X"E6",
+		X"F8",X"0F",X"0F",X"3C",X"5F",X"7E",X"E6",X"07",X"12",X"10",X"F2",X"D1",X"18",X"0C",X"E6",X"07",
+		X"06",X"20",X"21",X"01",X"58",X"77",X"2C",X"2C",X"10",X"FB",X"F1",X"C1",X"E1",X"C9",X"7A",X"E6",
+		X"F8",X"6F",X"26",X"00",X"54",X"29",X"29",X"CB",X"3B",X"CB",X"3B",X"CB",X"3B",X"19",X"11",X"40",
+		X"50",X"19",X"C9",X"E5",X"D5",X"CD",X"AE",X"0B",X"7E",X"D1",X"E1",X"C9",X"E5",X"D5",X"F5",X"21",
+		X"B2",X"12",X"85",X"6F",X"30",X"01",X"24",X"7E",X"F5",X"CD",X"AE",X"0B",X"F1",X"77",X"F1",X"D1",
+		X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"AF",X"B9",X"28",X"24",X"B8",X"28",X"21",X"E5",X"CD",X"AE",
+		X"0B",X"D1",X"C5",X"E5",X"D5",X"1A",X"11",X"B2",X"12",X"83",X"5F",X"30",X"01",X"14",X"1A",X"77",
+		X"11",X"20",X"00",X"19",X"D1",X"13",X"10",X"EC",X"E1",X"23",X"C1",X"0D",X"20",X"E4",X"F1",X"C1",
+		X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"4F",X"21",X"BC",X"1A",X"46",X"04",X"05",X"28",X"0E",X"23",
+		X"5E",X"23",X"56",X"23",X"DD",X"1A",X"A6",X"23",X"BE",X"00",X"00",X"00",X"00",X"AF",X"ED",X"47",
+		X"79",X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"29",X"01",X"0D",X"13",X"09",X"4E",X"23",
+		X"46",X"0A",X"E6",X"03",X"21",X"4F",X"0C",X"CD",X"3B",X"00",X"F1",X"C1",X"D1",X"E1",X"C9",X"04",
+		X"3D",X"0D",X"58",X"0C",X"0F",X"0D",X"F4",X"0C",X"69",X"60",X"23",X"46",X"2B",X"CB",X"7E",X"28",
+		X"19",X"78",X"E6",X"07",X"3C",X"4F",X"1F",X"2F",X"3C",X"83",X"5F",X"78",X"E6",X"F8",X"0F",X"0F",
+		X"0F",X"3C",X"47",X"1F",X"2F",X"3C",X"82",X"57",X"18",X"0C",X"78",X"CB",X"38",X"CB",X"38",X"CB",
+		X"38",X"04",X"E6",X"07",X"3C",X"4F",X"7E",X"23",X"E5",X"E6",X"18",X"0F",X"0F",X"0F",X"EF",X"97",
+		X"0C",X"AD",X"0C",X"C4",X"0C",X"DD",X"0C",X"CD",X"AE",X"0B",X"D1",X"13",X"1A",X"16",X"00",X"59",
+		X"E5",X"77",X"23",X"1D",X"20",X"FB",X"E1",X"1E",X"20",X"19",X"10",X"F3",X"C9",X"CD",X"AE",X"0B",
+		X"D1",X"13",X"1A",X"11",X"20",X"00",X"E5",X"C5",X"77",X"3C",X"19",X"10",X"FB",X"C1",X"E1",X"23",
+		X"0D",X"20",X"F3",X"C9",X"CD",X"AE",X"0B",X"D1",X"E5",X"C5",X"13",X"1A",X"77",X"7D",X"C6",X"20",
+		X"6F",X"30",X"01",X"24",X"10",X"F4",X"C1",X"E1",X"23",X"0D",X"20",X"EC",X"C9",X"CD",X"AE",X"0B",
+		X"D1",X"13",X"1A",X"11",X"E0",X"FF",X"E5",X"C5",X"77",X"3D",X"19",X"10",X"FB",X"C1",X"E1",X"23",
+		X"0D",X"20",X"F3",X"C9",X"0A",X"CB",X"7F",X"20",X"02",X"1D",X"1D",X"CB",X"77",X"20",X"01",X"AF",
+		X"21",X"32",X"40",X"77",X"2B",X"3E",X"FC",X"93",X"77",X"2B",X"3E",X"F0",X"92",X"77",X"C9",X"21",
+		X"33",X"40",X"7E",X"23",X"BE",X"C8",X"0A",X"CB",X"7F",X"28",X"02",X"1D",X"1D",X"CB",X"77",X"28",
+		X"06",X"7E",X"C6",X"02",X"77",X"18",X"04",X"2B",X"7E",X"35",X"35",X"21",X"22",X"40",X"85",X"6F",
+		X"30",X"01",X"24",X"3E",X"F0",X"92",X"77",X"23",X"3E",X"FC",X"93",X"77",X"C9",X"21",X"20",X"40",
+		X"7E",X"23",X"BE",X"C8",X"0A",X"CB",X"7F",X"28",X"09",X"7A",X"D6",X"08",X"57",X"7B",X"D6",X"08",
+		X"5F",X"0A",X"CB",X"77",X"28",X"06",X"7E",X"C6",X"04",X"77",X"18",X"07",X"2B",X"7E",X"C6",X"FC",
+		X"77",X"C6",X"04",X"21",X"00",X"40",X"85",X"6F",X"30",X"01",X"24",X"7A",X"C6",X"1E",X"2F",X"77",
+		X"23",X"03",X"0A",X"77",X"23",X"0B",X"0A",X"E6",X"38",X"0F",X"0F",X"0F",X"77",X"23",X"73",X"C9",
+		X"E5",X"D5",X"C5",X"F5",X"29",X"01",X"0D",X"13",X"09",X"4E",X"23",X"46",X"0A",X"E6",X"03",X"21",
+		X"9A",X"0D",X"CD",X"3B",X"00",X"F1",X"C1",X"D1",X"E1",X"C9",X"04",X"4B",X"0E",X"A3",X"0D",X"0C",
+		X"0E",X"F1",X"0D",X"69",X"60",X"23",X"46",X"2B",X"CB",X"7E",X"28",X"19",X"78",X"E6",X"07",X"3C",
+		X"4F",X"1F",X"2F",X"3C",X"83",X"5F",X"78",X"E6",X"F8",X"0F",X"0F",X"0F",X"3C",X"47",X"1F",X"2F",
+		X"3C",X"82",X"57",X"18",X"0C",X"78",X"CB",X"38",X"CB",X"38",X"CB",X"38",X"04",X"E6",X"07",X"3C",
+		X"4F",X"21",X"B2",X"12",X"7D",X"C6",X"20",X"6F",X"30",X"01",X"24",X"7E",X"F5",X"CD",X"AE",X"0B",
+		X"F1",X"16",X"00",X"59",X"E5",X"77",X"23",X"1D",X"20",X"FB",X"E1",X"1E",X"20",X"19",X"10",X"F3",
+		X"C9",X"0A",X"E6",X"80",X"28",X"02",X"1D",X"1D",X"21",X"31",X"40",X"3E",X"FC",X"93",X"BE",X"C0",
+		X"2B",X"3E",X"F0",X"92",X"96",X"C0",X"77",X"23",X"77",X"23",X"77",X"C9",X"0A",X"E6",X"80",X"28",
+		X"02",X"1D",X"1D",X"3A",X"34",X"40",X"4F",X"C6",X"02",X"CB",X"3F",X"C8",X"47",X"3E",X"FC",X"93",
+		X"5F",X"3E",X"F0",X"92",X"57",X"21",X"22",X"40",X"BE",X"23",X"28",X"04",X"23",X"10",X"F9",X"C9",
+		X"7B",X"BE",X"7A",X"20",X"F7",X"79",X"D6",X"02",X"32",X"34",X"40",X"06",X"00",X"EB",X"21",X"22",
+		X"40",X"09",X"7E",X"12",X"70",X"23",X"13",X"7E",X"12",X"70",X"C9",X"69",X"60",X"7A",X"C6",X"1E",
+		X"2F",X"57",X"CB",X"7E",X"28",X"07",X"C6",X"08",X"57",X"7B",X"C6",X"F8",X"5F",X"23",X"4E",X"3A",
+		X"21",X"40",X"C6",X"04",X"E6",X"FC",X"C8",X"0F",X"0F",X"47",X"2B",X"7E",X"E6",X"38",X"0F",X"0F",
+		X"0F",X"F5",X"21",X"00",X"40",X"7A",X"BE",X"23",X"20",X"15",X"79",X"BE",X"20",X"11",X"23",X"7E",
+		X"E3",X"BC",X"E3",X"23",X"20",X"0B",X"7B",X"BE",X"20",X"07",X"CD",X"96",X"0E",X"18",X"05",X"23",
+		X"23",X"23",X"10",X"E1",X"F1",X"C9",X"EB",X"21",X"21",X"40",X"7E",X"D6",X"04",X"77",X"C6",X"07",
+		X"4F",X"06",X"00",X"21",X"00",X"40",X"09",X"0E",X"04",X"ED",X"B8",X"23",X"71",X"C9",X"E5",X"C5",
+		X"F5",X"21",X"00",X"00",X"22",X"5F",X"40",X"CD",X"B5",X"12",X"3E",X"01",X"CD",X"37",X"29",X"3E",
+		X"00",X"CD",X"58",X"11",X"FD",X"34",X"02",X"CD",X"73",X"2C",X"CD",X"2C",X"05",X"CD",X"AE",X"02",
+		X"20",X"33",X"CD",X"24",X"2E",X"CD",X"15",X"08",X"CD",X"AE",X"02",X"20",X"28",X"CD",X"BA",X"21",
+		X"3E",X"01",X"CD",X"27",X"17",X"CD",X"09",X"0F",X"21",X"4E",X"10",X"CD",X"F2",X"04",X"0E",X"01",
+		X"CD",X"D3",X"10",X"CD",X"AE",X"02",X"20",X"0D",X"CD",X"19",X"10",X"CD",X"AE",X"02",X"20",X"05",
+		X"0E",X"01",X"CD",X"D0",X"11",X"F1",X"C1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"21",X"53",X"0F",
+		X"11",X"10",X"18",X"01",X"09",X"16",X"CD",X"E2",X"0B",X"21",X"15",X"58",X"11",X"43",X"0F",X"01",
+		X"2C",X"01",X"CD",X"15",X"08",X"79",X"E6",X"1F",X"FE",X"1F",X"20",X"03",X"1A",X"13",X"77",X"CD",
+		X"AE",X"02",X"20",X"05",X"0B",X"78",X"B1",X"20",X"E9",X"CD",X"B5",X"12",X"36",X"01",X"F1",X"C1",
+		X"D1",X"E1",X"C9",X"02",X"04",X"05",X"01",X"02",X"04",X"05",X"01",X"02",X"04",X"05",X"01",X"02",
+		X"04",X"05",X"01",X"44",X"45",X"53",X"49",X"47",X"4E",X"20",X"4C",X"41",X"42",X"53",X"20",X"49",
+		X"4E",X"43",X"20",X"21",X"20",X"31",X"39",X"38",X"33",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"50",
+		X"48",X"4F",X"4E",X"45",X"20",X"20",X"34",X"30",X"38",X"20",X"20",X"37",X"34",X"38",X"20",X"37",
+		X"36",X"30",X"32",X"20",X"20",X"53",X"41",X"4E",X"54",X"41",X"20",X"43",X"4C",X"41",X"52",X"41",
+		X"20",X"43",X"41",X"4C",X"49",X"46",X"20",X"20",X"20",X"20",X"20",X"54",X"48",X"4F",X"4D",X"41",
+		X"53",X"20",X"41",X"55",X"54",X"4F",X"4D",X"41",X"54",X"49",X"43",X"53",X"20",X"49",X"4E",X"43",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"46",X"4F",X"52",X"20",X"41",X"4D",X"55",X"53",
+		X"45",X"4D",X"45",X"4E",X"54",X"20",X"4F",X"4E",X"4C",X"59",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"54",X"52",X"49",X"50",X"4C",X"45",X"20",X"44",X"52",X"41",X"57",
+		X"20",X"50",X"4F",X"4B",X"45",X"52",X"20",X"20",X"20",X"E5",X"C5",X"F5",X"06",X"78",X"3E",X"00",
+		X"21",X"4E",X"10",X"CD",X"F2",X"04",X"CD",X"15",X"08",X"4F",X"CD",X"AE",X"02",X"20",X"1B",X"79",
+		X"3C",X"10",X"F3",X"06",X"78",X"3E",X"00",X"21",X"4E",X"10",X"CD",X"B0",X"04",X"CD",X"15",X"08",
+		X"4F",X"CD",X"AE",X"02",X"20",X"04",X"79",X"3C",X"10",X"F0",X"F1",X"C1",X"E1",X"C9",X"01",X"1F",
+		X"00",X"0F",X"5A",X"10",X"96",X"10",X"03",X"14",X"40",X"20",X"20",X"20",X"42",X"45",X"20",X"41",
+		X"20",X"42",X"49",X"47",X"20",X"57",X"49",X"4E",X"4E",X"45",X"52",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"54",X"52",X"49",X"50",X"4C",X"45",X"20",X"44",X"52",X"41",X"57",X"20",X"50",
+		X"4F",X"4B",X"45",X"52",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"C9",X"E5",X"D5",X"C5",X"F5",X"0D",X"28",X"08",X"3E",X"01",X"CD",X"33",X"04",X"CD",
+		X"58",X"11",X"3E",X"04",X"CD",X"72",X"0B",X"21",X"44",X"11",X"11",X"40",X"20",X"01",X"01",X"14",
+		X"CD",X"E2",X"0B",X"06",X"05",X"11",X"30",X"00",X"CD",X"31",X"07",X"C5",X"01",X"07",X"04",X"CD",
+		X"FC",X"08",X"CD",X"B9",X"11",X"01",X"09",X"00",X"09",X"7A",X"C6",X"78",X"57",X"01",X"07",X"04",
+		X"CD",X"FC",X"08",X"CD",X"B9",X"11",X"7A",X"D6",X"78",X"57",X"CD",X"81",X"0A",X"20",X"22",X"3E",
+		X"2D",X"CD",X"FA",X"26",X"7B",X"D6",X"08",X"5F",X"01",X"09",X"00",X"09",X"C1",X"10",X"CC",X"CD",
+		X"81",X"0A",X"20",X"05",X"3E",X"78",X"CD",X"FA",X"26",X"CD",X"E8",X"1A",X"F1",X"C1",X"D1",X"E1",
+		X"C9",X"C1",X"18",X"F5",X"41",X"4C",X"4C",X"20",X"54",X"49",X"4D",X"45",X"20",X"48",X"49",X"47",
+		X"48",X"20",X"53",X"43",X"4F",X"52",X"45",X"53",X"E5",X"D5",X"C5",X"F5",X"3D",X"28",X"0E",X"3A",
+		X"8C",X"40",X"FE",X"02",X"20",X"2C",X"FD",X"E5",X"E1",X"11",X"48",X"00",X"19",X"11",X"02",X"00",
+		X"19",X"01",X"07",X"04",X"11",X"E8",X"A0",X"CD",X"FC",X"08",X"21",X"97",X"11",X"11",X"F0",X"A8",
+		X"01",X"01",X"06",X"CD",X"E2",X"0B",X"21",X"9D",X"11",X"11",X"F8",X"00",X"01",X"01",X"1C",X"CD",
+		X"E2",X"0B",X"F1",X"C1",X"D1",X"E1",X"C9",X"50",X"4F",X"49",X"4E",X"54",X"53",X"50",X"4C",X"41",
+		X"59",X"45",X"52",X"20",X"4F",X"4E",X"45",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"50",
+		X"4C",X"41",X"59",X"45",X"52",X"20",X"54",X"57",X"4F",X"E5",X"D5",X"C5",X"F5",X"01",X"04",X"00",
+		X"09",X"7A",X"C6",X"40",X"57",X"01",X"01",X"05",X"CD",X"E2",X"0B",X"F1",X"C1",X"D1",X"E1",X"C9",
+		X"E5",X"C5",X"F5",X"CD",X"B5",X"12",X"CD",X"EA",X"11",X"06",X"78",X"3E",X"00",X"CD",X"B0",X"04",
+		X"CD",X"15",X"08",X"3C",X"10",X"F7",X"F1",X"C1",X"E1",X"C9",X"0D",X"21",X"F8",X"11",X"C8",X"3D",
+		X"21",X"04",X"12",X"C8",X"21",X"38",X"12",X"C9",X"01",X"1F",X"00",X"0F",X"1B",X"12",X"24",X"12",
+		X"01",X"09",X"48",X"40",X"01",X"1F",X"00",X"0F",X"10",X"12",X"24",X"12",X"01",X"14",X"48",X"20",
+		X"50",X"4C",X"41",X"59",X"45",X"52",X"20",X"4F",X"4E",X"45",X"20",X"47",X"41",X"4D",X"45",X"20",
+		X"4F",X"56",X"45",X"52",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"01",X"1F",X"00",X"0F",X"44",X"12",X"24",X"12",
+		X"01",X"14",X"48",X"20",X"50",X"4C",X"41",X"59",X"45",X"52",X"20",X"54",X"57",X"4F",X"20",X"47",
+		X"41",X"4D",X"45",X"20",X"4F",X"56",X"45",X"52",X"E5",X"D5",X"C5",X"F5",X"04",X"05",X"28",X"03",
+		X"CD",X"B5",X"12",X"0C",X"0D",X"20",X"15",X"FE",X"01",X"20",X"11",X"21",X"8A",X"12",X"11",X"48",
+		X"28",X"01",X"01",X"12",X"CD",X"E2",X"0B",X"F1",X"C1",X"D1",X"E1",X"C9",X"21",X"9C",X"12",X"11",
+		X"48",X"08",X"01",X"01",X"19",X"CD",X"E2",X"0B",X"18",X"ED",X"50",X"52",X"45",X"53",X"53",X"20",
+		X"50",X"4C",X"41",X"59",X"45",X"52",X"20",X"53",X"54",X"41",X"52",X"54",X"50",X"52",X"45",X"53",
+		X"53",X"20",X"31",X"20",X"4F",X"52",X"20",X"32",X"20",X"50",X"4C",X"41",X"59",X"45",X"52",X"20",
+		X"53",X"54",X"41",X"52",X"54",X"D5",X"C5",X"F5",X"01",X"50",X"E0",X"11",X"08",X"00",X"3E",X"20",
+		X"CD",X"DD",X"09",X"CD",X"15",X"08",X"F1",X"C1",X"D1",X"C9",X"00",X"C8",X"E8",X"58",X"E8",X"00",
+		X"E8",X"00",X"E7",X"ED",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"C3",X"C4",X"C5",X"C6",X"C7",X"C8",X"C9",X"CA",X"CB",X"CC",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"CD",X"CE",X"CF",X"D0",X"D1",X"D2",X"D3",X"D4",X"D5",X"D6",X"D7",X"D8",X"D9",
+		X"DA",X"DB",X"DC",X"DD",X"DE",X"DF",X"E0",X"E1",X"E2",X"E3",X"E4",X"E5",X"E6",X"7B",X"13",X"A7",
+		X"13",X"BB",X"13",X"CF",X"13",X"E3",X"13",X"F7",X"13",X"0B",X"14",X"1F",X"14",X"33",X"14",X"47",
+		X"14",X"5B",X"14",X"6F",X"14",X"83",X"14",X"97",X"14",X"91",X"13",X"00",X"00",X"7B",X"13",X"B1",
+		X"13",X"C5",X"13",X"D9",X"13",X"ED",X"13",X"01",X"14",X"15",X"14",X"29",X"14",X"3D",X"14",X"51",
+		X"14",X"65",X"14",X"79",X"14",X"8D",X"14",X"A1",X"14",X"E3",X"14",X"F7",X"14",X"01",X"15",X"0F",
+		X"15",X"1D",X"15",X"29",X"15",X"35",X"15",X"3F",X"15",X"53",X"15",X"5B",X"15",X"6B",X"15",X"7B",
+		X"15",X"8B",X"15",X"9B",X"15",X"AB",X"15",X"B7",X"15",X"C3",X"15",X"CF",X"15",X"C7",X"14",X"D5",
+		X"14",X"B9",X"14",X"AB",X"14",X"ED",X"14",X"49",X"15",X"63",X"15",X"51",X"1C",X"E7",X"E7",X"E7",
+		X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",X"E7",
+		X"E7",X"51",X"1C",X"80",X"82",X"82",X"81",X"82",X"82",X"82",X"82",X"83",X"84",X"85",X"86",X"82",
+		X"82",X"82",X"82",X"7E",X"82",X"82",X"7F",X"51",X"19",X"05",X"6A",X"6C",X"07",X"00",X"6B",X"6D",
+		X"00",X"51",X"19",X"05",X"6E",X"70",X"07",X"00",X"6F",X"71",X"00",X"51",X"19",X"05",X"0A",X"0C",
+		X"07",X"00",X"0B",X"0D",X"00",X"51",X"19",X"05",X"0E",X"10",X"07",X"00",X"0F",X"11",X"00",X"51",
+		X"19",X"05",X"12",X"3C",X"07",X"00",X"13",X"3D",X"00",X"51",X"19",X"05",X"16",X"40",X"07",X"00",
+		X"17",X"41",X"00",X"51",X"19",X"05",X"1A",X"1C",X"07",X"00",X"1B",X"1D",X"00",X"51",X"19",X"05",
+		X"1E",X"20",X"07",X"00",X"1F",X"21",X"00",X"51",X"19",X"05",X"22",X"3C",X"07",X"00",X"23",X"25",
+		X"00",X"51",X"19",X"05",X"26",X"40",X"07",X"00",X"27",X"29",X"00",X"51",X"19",X"05",X"2A",X"3C",
+		X"07",X"00",X"2B",X"2D",X"00",X"51",X"19",X"05",X"2E",X"40",X"07",X"00",X"2F",X"31",X"00",X"51",
+		X"19",X"05",X"32",X"34",X"07",X"00",X"33",X"35",X"00",X"51",X"19",X"05",X"36",X"38",X"07",X"00",
+		X"37",X"39",X"00",X"51",X"19",X"05",X"3A",X"3C",X"07",X"00",X"3B",X"3D",X"00",X"51",X"19",X"05",
+		X"3E",X"40",X"07",X"00",X"3F",X"41",X"00",X"51",X"19",X"05",X"42",X"44",X"07",X"00",X"43",X"45",
+		X"00",X"51",X"19",X"05",X"46",X"48",X"07",X"00",X"47",X"49",X"00",X"51",X"19",X"05",X"4A",X"4C",
+		X"07",X"00",X"4B",X"4D",X"00",X"51",X"19",X"05",X"4E",X"50",X"07",X"00",X"4F",X"51",X"00",X"51",
+		X"19",X"05",X"52",X"54",X"07",X"00",X"53",X"55",X"00",X"51",X"19",X"05",X"56",X"58",X"07",X"00",
+		X"57",X"59",X"00",X"51",X"19",X"05",X"5A",X"5C",X"07",X"00",X"5B",X"5D",X"00",X"51",X"19",X"05",
+		X"5E",X"60",X"07",X"00",X"5F",X"61",X"00",X"51",X"19",X"05",X"62",X"64",X"07",X"00",X"63",X"65",
+		X"00",X"51",X"19",X"05",X"66",X"68",X"07",X"00",X"67",X"69",X"00",X"51",X"1A",X"00",X"00",X"00",
+		X"00",X"00",X"72",X"74",X"00",X"06",X"73",X"75",X"08",X"51",X"1A",X"00",X"00",X"00",X"00",X"00",
+		X"76",X"78",X"00",X"06",X"77",X"79",X"08",X"51",X"1A",X"00",X"00",X"00",X"00",X"00",X"01",X"02",
+		X"00",X"06",X"03",X"04",X"08",X"51",X"1A",X"00",X"00",X"00",X"00",X"00",X"7A",X"7C",X"00",X"06",
+		X"7B",X"7D",X"08",X"51",X"19",X"87",X"89",X"8B",X"8D",X"88",X"8A",X"8C",X"8E",X"51",X"19",X"14",
+		X"18",X"24",X"30",X"15",X"19",X"28",X"2C",X"51",X"19",X"E8",X"EC",X"EC",X"EA",X"E9",X"EC",X"EC",
+		X"EB",X"51",X"29",X"8F",X"91",X"93",X"95",X"97",X"99",X"90",X"92",X"94",X"96",X"98",X"9A",X"51",
+		X"29",X"E8",X"EC",X"EC",X"EC",X"EC",X"EA",X"E9",X"EC",X"EC",X"EC",X"EC",X"EB",X"51",X"21",X"9B",
+		X"9D",X"9F",X"A1",X"8D",X"9C",X"9E",X"A0",X"A2",X"8E",X"51",X"21",X"E8",X"EC",X"EC",X"EC",X"EA",
+		X"E9",X"EC",X"EC",X"EC",X"EB",X"51",X"19",X"A3",X"97",X"91",X"99",X"A4",X"98",X"92",X"9A",X"51",
+		X"19",X"E8",X"EC",X"EC",X"EA",X"E9",X"EC",X"EC",X"EB",X"51",X"19",X"F5",X"F1",X"F7",X"F9",X"F6",
+		X"F2",X"F8",X"FA",X"51",X"11",X"A5",X"97",X"A7",X"A6",X"98",X"A8",X"51",X"11",X"E8",X"EC",X"EA",
+		X"E9",X"EC",X"EB",X"51",X"11",X"EE",X"F1",X"F3",X"EF",X"F2",X"F4",X"51",X"31",X"AD",X"AF",X"B1",
+		X"B3",X"B5",X"B7",X"B9",X"AE",X"B0",X"B2",X"B4",X"B6",X"B8",X"BA",X"51",X"31",X"E8",X"EC",X"EC",
+		X"EC",X"EC",X"EC",X"EA",X"E9",X"EC",X"EC",X"EC",X"EC",X"EC",X"EB",X"51",X"31",X"8F",X"89",X"A9",
+		X"A9",X"97",X"95",X"A7",X"90",X"8A",X"AA",X"AA",X"98",X"96",X"A8",X"51",X"31",X"E8",X"EC",X"EC",
+		X"EC",X"EC",X"EC",X"EA",X"E9",X"EC",X"EC",X"EC",X"EC",X"EC",X"EB",X"51",X"21",X"A5",X"8B",X"9F",
+		X"AB",X"BB",X"A6",X"8C",X"A0",X"AC",X"BC",X"51",X"21",X"E8",X"EC",X"EC",X"EC",X"EA",X"E9",X"EC",
+		X"EC",X"EC",X"EB",X"51",X"21",X"05",X"BD",X"BF",X"C1",X"07",X"06",X"BE",X"C0",X"C2",X"08",X"51",
+		X"21",X"E8",X"EC",X"EC",X"EC",X"EA",X"E9",X"EC",X"EC",X"EC",X"EB",X"E5",X"15",X"E6",X"15",X"E9",
+		X"15",X"F3",X"15",X"F6",X"15",X"21",X"01",X"EA",X"F2",X"08",X"91",X"99",X"A1",X"A9",X"B1",X"B9",
+		X"C1",X"C9",X"D1",X"01",X"15",X"1D",X"04",X"11",X"19",X"21",X"29",X"35",X"E5",X"D5",X"C5",X"F5",
+		X"3E",X"20",X"CD",X"BD",X"09",X"CD",X"25",X"16",X"CD",X"61",X"16",X"CD",X"16",X"03",X"21",X"1F",
+		X"16",X"01",X"01",X"06",X"11",X"00",X"90",X"CD",X"E2",X"0B",X"F1",X"C1",X"D1",X"E1",X"C9",X"43",
+		X"52",X"45",X"44",X"49",X"54",X"F5",X"3E",X"05",X"CD",X"F0",X"0A",X"3E",X"05",X"28",X"02",X"3E",
+		X"0A",X"32",X"4A",X"40",X"F1",X"C9",X"E5",X"D5",X"C5",X"F5",X"3E",X"0A",X"CD",X"31",X"07",X"EB",
+		X"21",X"58",X"16",X"01",X"04",X"00",X"ED",X"B0",X"21",X"5C",X"16",X"01",X"05",X"00",X"ED",X"B0",
+		X"3D",X"20",X"ED",X"F1",X"C1",X"D1",X"E1",X"C9",X"00",X"50",X"00",X"00",X"50",X"4F",X"4B",X"45",
+		X"52",X"F5",X"3E",X"00",X"CD",X"72",X"0B",X"CD",X"77",X"16",X"CD",X"EB",X"16",X"3E",X"00",X"CD",
+		X"27",X"17",X"CD",X"58",X"18",X"F1",X"C9",X"E5",X"D5",X"C5",X"F5",X"3E",X"01",X"CD",X"72",X"0B",
+		X"11",X"F0",X"08",X"21",X"9D",X"16",X"01",X"01",X"1A",X"CD",X"E2",X"0B",X"CD",X"D1",X"16",X"FD",
+		X"7E",X"37",X"CD",X"33",X"04",X"CD",X"B7",X"16",X"F1",X"C1",X"D1",X"E1",X"C9",X"50",X"4F",X"49",
+		X"4E",X"54",X"53",X"20",X"20",X"20",X"42",X"45",X"53",X"54",X"20",X"47",X"41",X"4D",X"45",X"20",
+		X"20",X"20",X"48",X"41",X"4E",X"44",X"53",X"E5",X"D5",X"C5",X"CD",X"01",X"06",X"CD",X"31",X"07",
+		X"01",X"04",X"00",X"09",X"11",X"E0",X"60",X"01",X"01",X"05",X"CD",X"E2",X"0B",X"C1",X"D1",X"E1",
+		X"C9",X"E5",X"D5",X"F5",X"FD",X"E5",X"E1",X"11",X"01",X"00",X"19",X"6E",X"26",X"00",X"23",X"11",
+		X"E8",X"B8",X"3E",X"02",X"CD",X"85",X"09",X"F1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"FD",
+		X"E5",X"E1",X"11",X"06",X"00",X"19",X"06",X"24",X"3E",X"00",X"77",X"23",X"10",X"FC",X"F1",X"C1",
+		X"D1",X"E1",X"C9",X"01",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"07",
+		X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"20",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"70",
+		X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"E5",X"D5",X"C5",X"F5",X"CD",X"31",X"18",X"4F",X"3E",
+		X"02",X"CD",X"72",X"0B",X"FD",X"7E",X"2A",X"FE",X"09",X"20",X"02",X"0E",X"00",X"79",X"FD",X"E5",
+		X"E1",X"01",X"2A",X"00",X"09",X"4E",X"06",X"00",X"11",X"90",X"08",X"21",X"51",X"17",X"C3",X"3B",
+		X"00",X"02",X"56",X"17",X"E2",X"17",X"01",X"09",X"0E",X"21",X"64",X"17",X"CD",X"E2",X"0B",X"F1",
+		X"C1",X"D1",X"E1",X"C9",X"50",X"41",X"49",X"52",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"32",X"20",X"50",X"41",X"49",X"52",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"33",X"20",X"4F",X"46",X"20",X"41",X"20",X"4B",X"49",X"4E",X"44",X"20",X"20",X"20",X"53",X"54",
+		X"52",X"41",X"49",X"47",X"48",X"54",X"20",X"20",X"20",X"20",X"20",X"20",X"46",X"4C",X"55",X"53",
+		X"48",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"46",X"55",X"4C",X"4C",X"20",X"48",
+		X"4F",X"55",X"53",X"45",X"20",X"20",X"20",X"20",X"34",X"20",X"4F",X"46",X"20",X"41",X"20",X"4B",
+		X"49",X"4E",X"44",X"20",X"20",X"20",X"53",X"54",X"52",X"41",X"49",X"47",X"48",X"54",X"20",X"46",
+		X"4C",X"55",X"53",X"48",X"52",X"4F",X"59",X"41",X"4C",X"20",X"46",X"4C",X"55",X"53",X"48",X"20",
+		X"20",X"20",X"21",X"64",X"17",X"78",X"B9",X"C5",X"CC",X"23",X"18",X"01",X"01",X"0E",X"CD",X"E2",
+		X"0B",X"01",X"0E",X"00",X"09",X"47",X"3E",X"08",X"83",X"5F",X"78",X"C1",X"3C",X"FE",X"09",X"20",
+		X"E5",X"79",X"FE",X"09",X"CA",X"5F",X"17",X"21",X"10",X"18",X"CD",X"3B",X"00",X"C3",X"5F",X"17",
+		X"09",X"DB",X"1D",X"0D",X"1E",X"55",X"1E",X"AA",X"1E",X"06",X"1F",X"68",X"1F",X"D2",X"1F",X"44",
+		X"20",X"BD",X"20",X"E5",X"F5",X"79",X"87",X"21",X"25",X"58",X"85",X"6F",X"36",X"00",X"F1",X"E1",
+		X"C9",X"E5",X"D5",X"C5",X"F5",X"3E",X"09",X"11",X"90",X"A0",X"FD",X"E5",X"E1",X"01",X"06",X"00",
+		X"09",X"01",X"07",X"04",X"CD",X"FC",X"08",X"47",X"3E",X"08",X"83",X"5F",X"78",X"01",X"04",X"00",
+		X"3D",X"20",X"ED",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"FD",X"E5",X"E1",X"01",
+		X"2B",X"00",X"09",X"11",X"60",X"10",X"06",X"05",X"CD",X"77",X"18",X"3E",X"28",X"82",X"57",X"23",
+		X"10",X"F6",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"7E",X"47",X"E6",X"0F",X"4F",
+		X"78",X"E6",X"20",X"0F",X"B1",X"6F",X"26",X"00",X"CD",X"35",X"0C",X"3E",X"00",X"B1",X"28",X"17",
+		X"FE",X"0E",X"28",X"13",X"21",X"30",X"00",X"78",X"E6",X"30",X"0F",X"0F",X"0F",X"0F",X"85",X"6F",
+		X"3E",X"10",X"83",X"5F",X"CD",X"35",X"0C",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",
+		X"CD",X"A0",X"04",X"3E",X"05",X"85",X"5F",X"D6",X"3C",X"38",X"03",X"24",X"18",X"01",X"7B",X"6F",
+		X"22",X"8A",X"40",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"CD",X"A0",X"04",X"ED",
+		X"5B",X"8A",X"40",X"97",X"ED",X"52",X"38",X"01",X"AF",X"C1",X"78",X"C1",X"D1",X"E1",X"C9",X"FD",
+		X"E5",X"E5",X"D5",X"C5",X"F5",X"CD",X"FC",X"15",X"CD",X"15",X"08",X"79",X"32",X"8C",X"40",X"CD",
+		X"EB",X"16",X"FD",X"E5",X"E1",X"11",X"02",X"00",X"19",X"EB",X"21",X"17",X"19",X"01",X"04",X"00",
+		X"ED",X"B0",X"11",X"48",X"00",X"FD",X"19",X"3D",X"CD",X"15",X"08",X"20",X"E2",X"CD",X"23",X"04",
+		X"F1",X"C1",X"D1",X"E1",X"FD",X"E1",X"C9",X"10",X"00",X"00",X"00",X"E5",X"D5",X"C5",X"F5",X"CD",
+		X"39",X"21",X"CD",X"AC",X"18",X"FD",X"70",X"32",X"CD",X"B5",X"12",X"CD",X"63",X"19",X"EB",X"CD",
+		X"11",X"1A",X"11",X"18",X"50",X"3E",X"05",X"01",X"75",X"1A",X"CD",X"C8",X"18",X"28",X"1C",X"CD",
+		X"39",X"21",X"CD",X"20",X"1A",X"CD",X"2D",X"1A",X"CD",X"90",X"1A",X"CD",X"15",X"08",X"28",X"EA",
+		X"3D",X"20",X"E4",X"3E",X"3C",X"CD",X"FA",X"26",X"CD",X"B5",X"12",X"CD",X"0B",X"07",X"F1",X"C1",
+		X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"0D",X"28",X"12",X"21",X"FD",X"19",X"3D",X"28",X"03",
+		X"21",X"07",X"1A",X"11",X"50",X"48",X"01",X"01",X"0A",X"CD",X"E2",X"0B",X"21",X"8D",X"19",X"11",
+		X"28",X"00",X"01",X"04",X"1C",X"CD",X"E2",X"0B",X"F1",X"C1",X"D1",X"E1",X"C9",X"54",X"48",X"45",
+		X"20",X"4A",X"4F",X"59",X"53",X"54",X"49",X"43",X"4B",X"20",X"41",X"4E",X"44",X"20",X"46",X"49",
+		X"52",X"45",X"20",X"42",X"55",X"54",X"54",X"4F",X"4E",X"45",X"4E",X"54",X"45",X"52",X"20",X"59",
+		X"4F",X"55",X"52",X"20",X"4E",X"41",X"4D",X"45",X"20",X"55",X"53",X"49",X"4E",X"47",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"41",X"20",X"4E",X"45",X"57",X"20",X"48",X"49",X"47",X"48",X"20",
+		X"53",X"43",X"4F",X"52",X"45",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"43",X"4F",X"4E",X"47",X"52",X"41",X"54",X"55",X"4C",X"41",X"54",X"49",X"4F",X"4E",X"53",
+		X"20",X"59",X"4F",X"55",X"52",X"53",X"20",X"49",X"53",X"20",X"20",X"20",X"20",X"50",X"4C",X"41",
+		X"59",X"45",X"52",X"20",X"4F",X"4E",X"45",X"50",X"4C",X"41",X"59",X"45",X"52",X"20",X"54",X"57",
+		X"4F",X"E5",X"C5",X"06",X"04",X"0E",X"20",X"71",X"10",X"FD",X"CD",X"0B",X"07",X"C1",X"E1",X"C9",
+		X"C5",X"F5",X"0A",X"77",X"01",X"01",X"01",X"CD",X"E2",X"0B",X"F1",X"C1",X"C9",X"E5",X"D5",X"F5",
+		X"3E",X"00",X"FD",X"B6",X"34",X"28",X"05",X"FD",X"35",X"34",X"18",X"27",X"FD",X"7E",X"32",X"CD",
+		X"94",X"0A",X"3E",X"00",X"B2",X"28",X"1C",X"CD",X"53",X"1D",X"CD",X"AC",X"18",X"CD",X"0B",X"07",
+		X"FD",X"36",X"34",X"14",X"15",X"28",X"10",X"0B",X"C5",X"E1",X"11",X"75",X"1A",X"DF",X"30",X"03",
+		X"01",X"8F",X"1A",X"F1",X"D1",X"E1",X"C9",X"03",X"C5",X"E1",X"11",X"8F",X"1A",X"DF",X"38",X"F3",
+		X"01",X"75",X"1A",X"18",X"EE",X"41",X"42",X"43",X"44",X"45",X"46",X"47",X"48",X"49",X"4A",X"4B",
+		X"4C",X"4D",X"4E",X"4F",X"50",X"51",X"52",X"53",X"54",X"55",X"56",X"57",X"58",X"59",X"5A",X"20",
+		X"C5",X"F5",X"3E",X"00",X"FD",X"B6",X"35",X"28",X"06",X"FD",X"35",X"35",X"AF",X"18",X"19",X"FD",
+		X"7E",X"32",X"CD",X"DD",X"0A",X"28",X"11",X"CD",X"36",X"1D",X"CD",X"AC",X"18",X"FD",X"36",X"35",
+		X"14",X"23",X"F5",X"3E",X"08",X"82",X"57",X"F1",X"C1",X"78",X"C1",X"C9",X"09",X"00",X"2F",X"00",
+		X"00",X"40",X"2F",X"3F",X"3F",X"C0",X"2F",X"3F",X"3E",X"80",X"2F",X"3F",X"3D",X"C0",X"2F",X"3F",
+		X"3B",X"40",X"2F",X"3F",X"37",X"40",X"2F",X"3F",X"2F",X"80",X"2F",X"3F",X"1F",X"40",X"2F",X"3F",
+		X"00",X"F5",X"AF",X"32",X"4B",X"40",X"F1",X"C9",X"CD",X"E1",X"1A",X"C9",X"F5",X"C5",X"01",X"FF",
+		X"00",X"3A",X"4B",X"40",X"A7",X"28",X"38",X"D5",X"E5",X"11",X"1E",X"41",X"F5",X"1A",X"13",X"21",
+		X"3E",X"1B",X"CD",X"3B",X"00",X"20",X"1F",X"21",X"4B",X"40",X"35",X"F1",X"FE",X"01",X"28",X"17",
+		X"1B",X"C5",X"D5",X"6F",X"26",X"00",X"29",X"29",X"4D",X"44",X"6B",X"62",X"23",X"23",X"23",X"23",
+		X"ED",X"B0",X"D1",X"C1",X"18",X"04",X"F1",X"13",X"13",X"13",X"3D",X"20",X"CF",X"E1",X"D1",X"79",
+		X"32",X"00",X"78",X"78",X"32",X"06",X"68",X"0F",X"32",X"07",X"68",X"C1",X"F1",X"C9",X"0C",X"1F",
+		X"1C",X"1F",X"1C",X"1F",X"1C",X"1F",X"1C",X"1F",X"1C",X"1F",X"1C",X"1F",X"1C",X"1F",X"1C",X"1F",
+		X"1C",X"1F",X"1C",X"2F",X"1C",X"2F",X"1C",X"D5",X"C5",X"F5",X"4F",X"A7",X"28",X"0B",X"FD",X"7E",
+		X"00",X"A7",X"20",X"05",X"21",X"23",X"41",X"18",X"35",X"21",X"1E",X"41",X"3A",X"4B",X"40",X"A7",
+		X"28",X"0B",X"47",X"79",X"11",X"04",X"00",X"BE",X"30",X"07",X"19",X"10",X"FA",X"71",X"EB",X"18",
+		X"17",X"28",X"1A",X"79",X"EB",X"68",X"26",X"00",X"29",X"29",X"4D",X"44",X"19",X"5D",X"54",X"2B",
+		X"13",X"13",X"13",X"ED",X"B8",X"23",X"77",X"EB",X"21",X"4B",X"40",X"34",X"EB",X"23",X"F1",X"C1",
+		X"D1",X"C9",X"E5",X"A7",X"28",X"04",X"4F",X"1A",X"18",X"0E",X"13",X"1A",X"FE",X"FF",X"28",X"19",
+		X"07",X"07",X"07",X"E6",X"07",X"3C",X"4F",X"1A",X"E6",X"1F",X"21",X"00",X"1C",X"85",X"6F",X"30",
+		X"01",X"24",X"0D",X"AF",X"3C",X"79",X"4E",X"06",X"03",X"E1",X"C9",X"E5",X"A7",X"28",X"07",X"3D",
+		X"28",X"21",X"4F",X"1A",X"18",X"11",X"13",X"1A",X"FE",X"FF",X"28",X"1A",X"07",X"07",X"07",X"E6",
+		X"07",X"21",X"F8",X"1B",X"D7",X"4F",X"1A",X"E6",X"1F",X"21",X"00",X"1C",X"85",X"6F",X"30",X"01",
+		X"24",X"79",X"4E",X"06",X"02",X"04",X"E1",X"C9",X"57",X"4C",X"41",X"36",X"2B",X"20",X"15",X"0A",
+		X"0C",X"1A",X"27",X"33",X"3E",X"49",X"53",X"5D",X"66",X"6F",X"77",X"7F",X"86",X"8D",X"93",X"99",
+		X"9F",X"A5",X"AA",X"AF",X"B3",X"B7",X"BC",X"BF",X"C3",X"C6",X"CA",X"CD",X"D0",X"D2",X"FF",X"EB",
+		X"7E",X"23",X"5E",X"23",X"56",X"CD",X"A2",X"1B",X"72",X"2B",X"73",X"2B",X"77",X"EB",X"C9",X"EB",
+		X"7E",X"23",X"5E",X"23",X"56",X"CD",X"CB",X"1B",X"72",X"2B",X"73",X"2B",X"77",X"EB",X"C9",X"E5",
+		X"D5",X"F5",X"3E",X"00",X"CD",X"57",X"1B",X"11",X"53",X"1C",X"36",X"00",X"23",X"73",X"23",X"72",
+		X"F1",X"D1",X"E1",X"C9",X"2C",X"70",X"73",X"B5",X"FF",X"E5",X"D5",X"F5",X"3E",X"03",X"CD",X"57",
+		X"1B",X"11",X"6D",X"1C",X"36",X"00",X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",X"C9",X"60",X"61",
+		X"62",X"63",X"7E",X"FF",X"E5",X"D5",X"F5",X"3E",X"03",X"CD",X"57",X"1B",X"11",X"88",X"1C",X"36",
+		X"00",X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",X"C9",X"62",X"63",X"64",X"65",X"7E",X"FF",X"E5",
+		X"D5",X"F5",X"3E",X"03",X"CD",X"57",X"1B",X"11",X"A3",X"1C",X"36",X"00",X"23",X"73",X"23",X"72",
+		X"F1",X"D1",X"E1",X"C9",X"64",X"65",X"66",X"67",X"7E",X"FF",X"E5",X"D5",X"F5",X"3E",X"03",X"CD",
+		X"57",X"1B",X"11",X"BE",X"1C",X"36",X"00",X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",X"C9",X"66",
+		X"67",X"68",X"69",X"7E",X"FF",X"E5",X"D5",X"F5",X"3A",X"4B",X"40",X"B7",X"20",X"0E",X"3E",X"07",
+		X"CD",X"57",X"1B",X"11",X"DF",X"1C",X"36",X"00",X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",X"C9",
+		X"FE",X"80",X"82",X"83",X"FF",X"E5",X"D5",X"F5",X"3E",X"02",X"CD",X"57",X"1B",X"11",X"F9",X"1C",
+		X"36",X"00",X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",X"C9",X"40",X"3E",X"40",X"FF",X"E5",X"D5",
+		X"F5",X"3E",X"01",X"CD",X"57",X"1B",X"11",X"12",X"1D",X"36",X"00",X"23",X"73",X"23",X"72",X"F1",
+		X"D1",X"E1",X"C9",X"9E",X"85",X"86",X"87",X"BE",X"FF",X"E5",X"D5",X"F5",X"3E",X"06",X"CD",X"57",
+		X"1B",X"11",X"2D",X"1D",X"36",X"00",X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",X"C9",X"9E",X"6D",
+		X"6C",X"6B",X"6A",X"69",X"68",X"FF",X"E5",X"D5",X"F5",X"3E",X"04",X"CD",X"57",X"1B",X"11",X"4A",
+		X"1D",X"36",X"00",X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",X"C9",X"BE",X"68",X"69",X"6A",X"6B",
+		X"6C",X"5E",X"FF",X"E5",X"D5",X"F5",X"3E",X"05",X"CD",X"57",X"1B",X"11",X"67",X"1D",X"36",X"00",
+		X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",X"C9",X"BE",X"8C",X"BE",X"FF",X"E5",X"D5",X"F5",X"3E",
+		X"09",X"CD",X"57",X"1B",X"11",X"80",X"1D",X"36",X"00",X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",
+		X"C9",X"A0",X"A1",X"A2",X"A3",X"A4",X"A5",X"A6",X"A7",X"FF",X"E5",X"D5",X"F5",X"3E",X"08",X"CD",
+		X"57",X"1B",X"11",X"9E",X"1D",X"36",X"00",X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",X"C9",X"A7",
+		X"A6",X"A5",X"A4",X"A3",X"A2",X"A1",X"A0",X"FF",X"C9",X"E5",X"D5",X"F5",X"CD",X"E8",X"1A",X"3E",
+		X"0A",X"CD",X"57",X"1B",X"11",X"C0",X"1D",X"36",X"00",X"23",X"73",X"23",X"72",X"F1",X"D1",X"E1",
+		X"C9",X"F4",X"F5",X"F1",X"EE",X"EE",X"F0",X"CC",X"E8",X"E9",X"E5",X"E2",X"E2",X"E4",X"C0",X"E8",
+		X"E9",X"E5",X"E2",X"E2",X"E4",X"E2",X"E2",X"C0",X"DE",X"CC",X"FF",X"E5",X"D5",X"F5",X"3E",X"0B",
+		X"CD",X"57",X"1B",X"11",X"F2",X"1D",X"36",X"00",X"23",X"73",X"23",X"72",X"01",X"1E",X"00",X"F1",
+		X"D1",X"E1",X"C9",X"CC",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",
+		X"F4",X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",X"D3",X"D1",X"F5",X"EC",X"D1",X"FF",X"E5",X"D5",X"F5",
+		X"3E",X"0B",X"CD",X"57",X"1B",X"11",X"24",X"1E",X"36",X"00",X"23",X"73",X"23",X"72",X"01",X"3C",
+		X"00",X"F1",X"D1",X"E1",X"C9",X"CC",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",
+		X"F1",X"F3",X"F4",X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",X"D3",X"D1",X"F5",X"EC",X"D1",X"E7",X"E8",
+		X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"C5",X"EE",X"EC",X"EB",X"EE",X"F1",X"F5",X"F5",X"F3",
+		X"F1",X"EE",X"93",X"D3",X"FF",X"E5",X"D5",X"F5",X"3E",X"0B",X"CD",X"57",X"1B",X"11",X"6C",X"1E",
+		X"36",X"00",X"23",X"73",X"23",X"72",X"01",X"2D",X"00",X"F1",X"D1",X"E1",X"C9",X"CC",X"E7",X"E8",
+		X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"F5",X"F1",X"F3",X"F5",X"F5",
+		X"F0",X"D3",X"D1",X"F5",X"EC",X"D1",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"C5",
+		X"EE",X"EC",X"EB",X"EE",X"F1",X"F5",X"F5",X"F3",X"F1",X"EE",X"93",X"D3",X"E7",X"E8",X"E9",X"C5",
+		X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"FF",X"E5",X"D5",X"F5",X"3E",X"0B",X"CD",
+		X"57",X"1B",X"11",X"C1",X"1E",X"36",X"00",X"23",X"73",X"23",X"72",X"01",X"64",X"00",X"F1",X"D1",
+		X"E1",X"C9",X"CC",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",
+		X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",X"D3",X"D1",X"F5",X"EC",X"D1",X"E7",X"E8",X"E9",X"C5",X"E9",
+		X"C5",X"E9",X"E5",X"85",X"C5",X"EE",X"EC",X"EB",X"EE",X"F1",X"F5",X"F5",X"F3",X"F1",X"EE",X"93",
+		X"D3",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"F5",X"F1",
+		X"F3",X"F5",X"F5",X"F0",X"D3",X"FF",X"E5",X"D5",X"F5",X"3E",X"0B",X"CD",X"57",X"1B",X"11",X"1D",
+		X"1F",X"36",X"00",X"23",X"73",X"23",X"72",X"01",X"78",X"00",X"F1",X"D1",X"E1",X"C9",X"CC",X"E7",
+		X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"F5",X"F1",X"F3",X"F5",
+		X"F5",X"F0",X"D3",X"D1",X"F5",X"EC",X"D1",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",
+		X"C5",X"EE",X"EC",X"EB",X"EE",X"F1",X"F5",X"F5",X"F3",X"F1",X"EE",X"93",X"D3",X"E7",X"E8",X"E9",
+		X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",
+		X"D3",X"D1",X"E9",X"E0",X"D1",X"F1",X"F3",X"FF",X"E5",X"D5",X"F5",X"3E",X"0B",X"CD",X"57",X"1B",
+		X"11",X"7F",X"1F",X"36",X"00",X"23",X"73",X"23",X"72",X"01",X"8C",X"00",X"F1",X"D1",X"E1",X"C9",
+		X"CC",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"F5",X"F1",
+		X"F3",X"F5",X"F5",X"F0",X"D3",X"D1",X"F5",X"EC",X"D1",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",
+		X"E5",X"85",X"C5",X"EE",X"EC",X"EB",X"EE",X"F1",X"F5",X"F5",X"F3",X"F1",X"EE",X"93",X"D3",X"E7",
+		X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"F5",X"F1",X"F3",X"F5",
+		X"F5",X"F0",X"D3",X"D1",X"E9",X"E0",X"D1",X"F1",X"F3",X"F5",X"F1",X"F3",X"F5",X"F5",X"F1",X"F3",
+		X"F1",X"FF",X"E5",X"D5",X"F5",X"3E",X"0B",X"CD",X"57",X"1B",X"11",X"E9",X"1F",X"36",X"00",X"23",
+		X"73",X"23",X"72",X"01",X"A0",X"00",X"F1",X"D1",X"E1",X"C9",X"CC",X"E7",X"E8",X"E9",X"C5",X"E9",
+		X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",X"D3",X"D1",
+		X"F5",X"EC",X"D1",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"C5",X"EE",X"EC",X"EB",
+		X"EE",X"F1",X"F5",X"F5",X"F3",X"F1",X"EE",X"93",X"D3",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",
+		X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",X"D3",X"D1",X"E9",X"E0",
+		X"D1",X"F1",X"F3",X"F5",X"F1",X"F3",X"F5",X"F5",X"F1",X"F3",X"F1",X"F5",X"F1",X"F3",X"F5",X"F5",
+		X"F1",X"F3",X"F1",X"FF",X"E5",X"D5",X"F5",X"3E",X"0B",X"CD",X"57",X"1B",X"11",X"5B",X"20",X"36",
+		X"00",X"23",X"73",X"23",X"72",X"01",X"B4",X"00",X"F1",X"D1",X"E1",X"C9",X"CC",X"E7",X"E8",X"E9",
+		X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",
+		X"D3",X"D1",X"F5",X"EC",X"D1",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"C5",X"EE",
+		X"EC",X"EB",X"EE",X"F1",X"F5",X"F5",X"F3",X"F1",X"EE",X"93",X"D3",X"E7",X"E8",X"E9",X"C5",X"E9",
+		X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",X"F4",X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",X"D3",X"D1",
+		X"E9",X"E0",X"D1",X"F1",X"F3",X"F5",X"F1",X"F3",X"F5",X"F5",X"F1",X"F3",X"F1",X"F5",X"F1",X"F3",
+		X"F5",X"F5",X"F1",X"F3",X"F1",X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",X"D3",X"FF",X"E5",X"D5",X"F5",
+		X"3E",X"0B",X"CD",X"57",X"1B",X"11",X"D4",X"20",X"36",X"00",X"23",X"73",X"23",X"72",X"01",X"C8",
+		X"00",X"F1",X"D1",X"E1",X"C9",X"CC",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",
+		X"F1",X"F3",X"F4",X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",X"D3",X"D1",X"F5",X"EC",X"D1",X"E7",X"E8",
+		X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"C5",X"EE",X"EC",X"EB",X"EE",X"F1",X"F5",X"F5",X"F3",
+		X"F1",X"EE",X"93",X"D3",X"E7",X"E8",X"E9",X"C5",X"E9",X"C5",X"E9",X"E5",X"85",X"E5",X"F1",X"F3",
+		X"F4",X"F5",X"F1",X"F3",X"F5",X"F5",X"F0",X"D3",X"D1",X"E9",X"E0",X"D1",X"F1",X"F3",X"F5",X"F1",
+		X"F3",X"F5",X"F5",X"F1",X"F3",X"F1",X"F5",X"F1",X"F3",X"F5",X"F5",X"F1",X"F3",X"F1",X"F5",X"F1",
+		X"F3",X"F5",X"F5",X"F0",X"D3",X"91",X"D1",X"E7",X"FF",X"E5",X"D5",X"F5",X"3A",X"4B",X"40",X"B7",
+		X"20",X"0E",X"3E",X"0B",X"CD",X"57",X"1B",X"11",X"53",X"21",X"36",X"00",X"23",X"73",X"23",X"72",
+		X"F1",X"D1",X"E1",X"C9",X"D0",X"CC",X"EC",X"F7",X"F5",X"F4",X"F2",X"D0",X"EE",X"EE",X"EB",X"E9",
+		X"E7",X"E9",X"EB",X"EE",X"EE",X"F0",X"F2",X"F4",X"D5",X"8E",X"DE",X"CE",X"8E",X"D0",X"F2",X"D0",
+		X"F2",X"F0",X"F2",X"D0",X"F7",X"D5",X"F7",X"F5",X"F7",X"F5",X"F0",X"10",X"CE",X"8E",X"D0",X"F2",
+		X"D0",X"F2",X"F0",X"D0",X"F0",X"F0",X"CB",X"F0",X"EF",X"F0",X"D2",X"90",X"F0",X"DE",X"EE",X"CE",
+		X"8E",X"D0",X"F2",X"D0",X"F2",X"F0",X"F2",X"D0",X"F7",X"D5",X"F7",X"F5",X"F5",X"F7",X"EC",X"8C",
+		X"CC",X"F4",X"EC",X"F7",X"D5",X"F7",X"F5",X"F7",X"F5",X"F0",X"F0",X"F2",X"F0",X"EE",X"EE",X"D0",
+		X"F0",X"F0",X"CE",X"F0",X"EE",X"EE",X"D0",X"89",X"9E",X"FF",X"CD",X"DC",X"21",X"CD",X"1E",X"22",
+		X"CD",X"43",X"22",X"CD",X"A6",X"22",X"CD",X"C0",X"22",X"CD",X"DE",X"22",X"CD",X"EB",X"22",X"CD",
+		X"F8",X"22",X"CD",X"CF",X"22",X"CD",X"10",X"23",X"CD",X"23",X"23",X"C9",X"E5",X"D5",X"C5",X"F5",
+		X"FD",X"36",X"39",X"00",X"FD",X"36",X"3A",X"00",X"FD",X"36",X"3B",X"00",X"FD",X"36",X"3C",X"00",
+		X"FD",X"E5",X"E1",X"01",X"39",X"00",X"09",X"EB",X"FD",X"E5",X"E1",X"01",X"2B",X"00",X"09",X"06",
+		X"04",X"7E",X"E6",X"0F",X"4F",X"C5",X"23",X"E5",X"7E",X"E6",X"0F",X"B9",X"20",X"03",X"1A",X"3C",
+		X"12",X"23",X"10",X"F4",X"E1",X"C1",X"13",X"10",X"E8",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"C5",
+		X"F5",X"FD",X"36",X"3D",X"00",X"FD",X"E5",X"E1",X"01",X"2B",X"00",X"09",X"7E",X"E6",X"F0",X"4F",
+		X"06",X"04",X"23",X"7E",X"E6",X"F0",X"B9",X"20",X"06",X"10",X"F7",X"FD",X"36",X"3D",X"FF",X"F1",
+		X"C1",X"E1",X"C9",X"E5",X"C5",X"F5",X"FD",X"36",X"3E",X"00",X"FD",X"E5",X"E1",X"01",X"2B",X"00",
+		X"09",X"CD",X"79",X"22",X"FE",X"01",X"20",X"0B",X"3E",X"02",X"CD",X"8F",X"22",X"3E",X"01",X"28",
+		X"02",X"3E",X"09",X"06",X"04",X"3C",X"FE",X"0E",X"30",X"0B",X"CD",X"8F",X"22",X"20",X"06",X"10",
+		X"F4",X"FD",X"36",X"3E",X"FF",X"F1",X"C1",X"E1",X"C9",X"E5",X"C5",X"7E",X"E6",X"0F",X"4F",X"06",
+		X"04",X"23",X"7E",X"E6",X"0F",X"B9",X"30",X"01",X"4F",X"10",X"F6",X"79",X"C1",X"E1",X"C9",X"E5",
+		X"C5",X"F5",X"06",X"05",X"4F",X"7E",X"E6",X"0F",X"B9",X"28",X"06",X"23",X"10",X"F7",X"3E",X"01",
+		X"B7",X"C1",X"78",X"C1",X"E1",X"C9",X"F5",X"FD",X"36",X"2A",X"09",X"3E",X"01",X"CD",X"4A",X"23",
+		X"B7",X"28",X"0B",X"FE",X"02",X"3E",X"00",X"20",X"02",X"3E",X"01",X"FD",X"77",X"2A",X"F1",X"C9",
+		X"F5",X"3E",X"02",X"CD",X"4A",X"23",X"B7",X"28",X"04",X"FD",X"36",X"2A",X"02",X"F1",X"C9",X"F5",
+		X"3E",X"03",X"CD",X"4A",X"23",X"B7",X"28",X"04",X"FD",X"36",X"2A",X"06",X"F1",X"C9",X"F5",X"FD",
+		X"7E",X"3E",X"3C",X"20",X"04",X"FD",X"36",X"2A",X"03",X"F1",X"C9",X"F5",X"FD",X"7E",X"3D",X"3C",
+		X"20",X"04",X"FD",X"36",X"2A",X"04",X"F1",X"C9",X"F5",X"3E",X"02",X"CD",X"4A",X"23",X"B7",X"28",
+		X"0D",X"3E",X"01",X"CD",X"4A",X"23",X"FE",X"02",X"20",X"04",X"FD",X"36",X"2A",X"05",X"F1",X"C9",
+		X"F5",X"FD",X"7E",X"3E",X"3C",X"20",X"0A",X"FD",X"7E",X"3D",X"3C",X"20",X"04",X"FD",X"36",X"2A",
+		X"07",X"F1",X"C9",X"E5",X"C5",X"F5",X"FD",X"7E",X"2A",X"FE",X"07",X"20",X"19",X"FD",X"E5",X"E1",
+		X"01",X"2B",X"00",X"09",X"3E",X"01",X"CD",X"8F",X"22",X"20",X"0B",X"3E",X"0D",X"CD",X"8F",X"22",
+		X"20",X"04",X"FD",X"36",X"2A",X"08",X"F1",X"C1",X"E1",X"C9",X"E5",X"C5",X"FD",X"E5",X"E1",X"01",
+		X"39",X"00",X"09",X"01",X"00",X"04",X"BE",X"20",X"01",X"0C",X"23",X"10",X"F9",X"79",X"C1",X"E1",
+		X"C9",X"E5",X"D5",X"C5",X"F5",X"CD",X"AC",X"18",X"21",X"D0",X"23",X"11",X"E4",X"23",X"01",X"14",
+		X"00",X"CD",X"28",X"2A",X"CD",X"4F",X"2A",X"3E",X"08",X"32",X"8D",X"40",X"FD",X"36",X"36",X"00",
+		X"FD",X"36",X"40",X"00",X"FD",X"36",X"33",X"00",X"FD",X"36",X"46",X"00",X"3E",X"00",X"CD",X"C8",
+		X"18",X"28",X"23",X"CD",X"88",X"2A",X"CD",X"F0",X"2A",X"CD",X"7B",X"28",X"20",X"06",X"21",X"BB",
+		X"23",X"CD",X"EF",X"2B",X"CD",X"15",X"08",X"3C",X"67",X"CD",X"2C",X"05",X"7C",X"FD",X"6E",X"36",
+		X"2C",X"20",X"DB",X"CD",X"25",X"2C",X"F1",X"C1",X"D1",X"E1",X"C9",X"0A",X"4A",X"24",X"77",X"24",
+		X"A4",X"24",X"D1",X"24",X"FE",X"24",X"2B",X"25",X"49",X"24",X"70",X"25",X"49",X"24",X"24",X"2E",
+		X"F8",X"A8",X"1E",X"00",X"1E",X"00",X"1E",X"00",X"1E",X"00",X"1E",X"00",X"20",X"00",X"22",X"00",
+		X"24",X"00",X"00",X"00",X"F9",X"23",X"03",X"24",X"0D",X"24",X"17",X"24",X"21",X"24",X"2B",X"24",
+		X"F8",X"23",X"35",X"24",X"F8",X"23",X"3F",X"24",X"00",X"01",X"0F",X"00",X"09",X"1E",X"00",X"1F",
+		X"00",X"40",X"10",X"01",X"0F",X"00",X"09",X"1E",X"00",X"1F",X"00",X"40",X"38",X"01",X"0F",X"00",
+		X"09",X"1E",X"00",X"1F",X"00",X"40",X"60",X"01",X"0F",X"00",X"09",X"1E",X"00",X"1F",X"00",X"40",
+		X"88",X"01",X"0F",X"00",X"09",X"1E",X"00",X"1F",X"00",X"40",X"B0",X"01",X"0F",X"00",X"09",X"20",
+		X"00",X"21",X"00",X"28",X"10",X"01",X"0F",X"00",X"09",X"22",X"00",X"23",X"00",X"28",X"60",X"01",
+		X"0F",X"00",X"09",X"24",X"00",X"25",X"00",X"28",X"B0",X"C9",X"E5",X"F5",X"3E",X"01",X"FD",X"B6",
+		X"3F",X"FD",X"77",X"3F",X"FD",X"36",X"41",X"00",X"21",X"34",X"00",X"22",X"61",X"40",X"21",X"6D",
+		X"24",X"22",X"75",X"40",X"CD",X"4F",X"2A",X"CD",X"36",X"1D",X"F1",X"E1",X"C9",X"01",X"0F",X"00",
+		X"09",X"34",X"00",X"1F",X"00",X"40",X"10",X"E5",X"F5",X"3E",X"02",X"FD",X"B6",X"3F",X"FD",X"77",
+		X"3F",X"FD",X"36",X"41",X"00",X"21",X"34",X"00",X"22",X"63",X"40",X"21",X"9A",X"24",X"22",X"77",
+		X"40",X"CD",X"4F",X"2A",X"CD",X"36",X"1D",X"F1",X"E1",X"C9",X"01",X"0F",X"00",X"09",X"34",X"00",
+		X"1F",X"00",X"40",X"38",X"E5",X"F5",X"3E",X"04",X"FD",X"B6",X"3F",X"FD",X"77",X"3F",X"FD",X"36",
+		X"41",X"00",X"21",X"34",X"00",X"22",X"65",X"40",X"21",X"C7",X"24",X"22",X"79",X"40",X"CD",X"4F",
+		X"2A",X"CD",X"36",X"1D",X"F1",X"E1",X"C9",X"01",X"0F",X"00",X"09",X"34",X"00",X"1F",X"00",X"40",
+		X"60",X"E5",X"F5",X"3E",X"08",X"FD",X"B6",X"3F",X"FD",X"77",X"3F",X"FD",X"36",X"41",X"00",X"21",
+		X"34",X"00",X"22",X"67",X"40",X"21",X"F4",X"24",X"22",X"7B",X"40",X"CD",X"4F",X"2A",X"CD",X"36",
+		X"1D",X"F1",X"E1",X"C9",X"01",X"0F",X"00",X"09",X"34",X"00",X"1F",X"00",X"40",X"88",X"E5",X"F5",
+		X"3E",X"10",X"FD",X"B6",X"3F",X"FD",X"77",X"3F",X"FD",X"36",X"41",X"00",X"21",X"34",X"00",X"22",
+		X"69",X"40",X"21",X"21",X"25",X"22",X"7D",X"40",X"CD",X"4F",X"2A",X"CD",X"36",X"1D",X"F1",X"E1",
+		X"C9",X"01",X"0F",X"00",X"09",X"34",X"00",X"1F",X"00",X"40",X"B0",X"E5",X"D5",X"C5",X"21",X"5C",
+		X"25",X"11",X"61",X"40",X"01",X"0A",X"00",X"ED",X"B0",X"21",X"66",X"25",X"11",X"75",X"40",X"01",
+		X"0A",X"00",X"ED",X"B0",X"FD",X"36",X"3F",X"00",X"FD",X"7E",X"47",X"3C",X"20",X"04",X"FD",X"36",
+		X"41",X"FF",X"CD",X"4F",X"2A",X"CD",X"53",X"1D",X"C1",X"D1",X"E1",X"C9",X"1E",X"00",X"1E",X"00",
+		X"1E",X"00",X"1E",X"00",X"1E",X"00",X"F9",X"23",X"03",X"24",X"0D",X"24",X"17",X"24",X"21",X"24",
+		X"FD",X"36",X"3F",X"1F",X"FD",X"36",X"36",X"FF",X"FD",X"36",X"41",X"00",X"C9",X"F5",X"FD",X"7E",
+		X"2A",X"FE",X"09",X"C4",X"88",X"25",X"F1",X"C9",X"E5",X"D5",X"C5",X"F5",X"CD",X"AC",X"18",X"CD",
+		X"BB",X"27",X"FD",X"36",X"36",X"00",X"FD",X"36",X"33",X"01",X"FD",X"36",X"46",X"00",X"21",X"E5",
+		X"25",X"11",X"ED",X"25",X"01",X"08",X"00",X"CD",X"28",X"2A",X"CD",X"4F",X"2A",X"3E",X"00",X"CD",
+		X"C8",X"18",X"28",X"23",X"CD",X"88",X"2A",X"CD",X"F0",X"2A",X"CD",X"7B",X"28",X"20",X"06",X"21",
+		X"DC",X"25",X"CD",X"EF",X"2B",X"CD",X"15",X"08",X"3C",X"67",X"CD",X"2C",X"05",X"7C",X"FD",X"6E",
+		X"36",X"2C",X"20",X"DB",X"CD",X"25",X"2C",X"F1",X"C1",X"D1",X"E1",X"C9",X"04",X"0A",X"26",X"10",
+		X"26",X"0A",X"26",X"0B",X"26",X"50",X"00",X"28",X"00",X"2A",X"00",X"00",X"00",X"F5",X"25",X"F6",
+		X"25",X"F5",X"25",X"00",X"26",X"00",X"01",X"0F",X"00",X"09",X"28",X"00",X"29",X"00",X"40",X"38",
+		X"01",X"0F",X"00",X"09",X"2A",X"00",X"2B",X"00",X"40",X"88",X"C9",X"FD",X"36",X"36",X"FF",X"C9",
+		X"E5",X"D5",X"C5",X"F5",X"CD",X"AC",X"18",X"CD",X"9D",X"26",X"CD",X"25",X"2C",X"CD",X"CA",X"26",
+		X"21",X"79",X"26",X"11",X"81",X"26",X"01",X"08",X"00",X"CD",X"28",X"2A",X"CD",X"4F",X"2A",X"FD",
+		X"36",X"33",X"01",X"FD",X"36",X"36",X"00",X"FD",X"36",X"46",X"00",X"3E",X"00",X"CD",X"C8",X"18",
+		X"28",X"29",X"CD",X"88",X"2A",X"CD",X"F0",X"2A",X"CD",X"7B",X"28",X"20",X"06",X"21",X"70",X"26",
+		X"CD",X"EF",X"2B",X"CD",X"15",X"08",X"3C",X"67",X"CD",X"2C",X"05",X"7C",X"FD",X"6E",X"36",X"2C",
+		X"20",X"DB",X"CD",X"25",X"2C",X"CD",X"B3",X"26",X"CD",X"58",X"18",X"F1",X"C1",X"D1",X"E1",X"C9",
+		X"04",X"0A",X"26",X"03",X"27",X"0A",X"26",X"0B",X"27",X"50",X"00",X"2E",X"00",X"2C",X"00",X"00",
+		X"00",X"F5",X"25",X"89",X"26",X"F5",X"25",X"93",X"26",X"01",X"0F",X"00",X"09",X"2E",X"00",X"2F",
+		X"00",X"40",X"38",X"01",X"0F",X"00",X"09",X"2C",X"00",X"2D",X"00",X"40",X"88",X"E5",X"D5",X"C5",
+		X"FD",X"E5",X"E1",X"11",X"2B",X"00",X"19",X"11",X"4D",X"40",X"01",X"05",X"00",X"ED",X"B0",X"C1",
+		X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"FD",X"E5",X"E1",X"11",X"2B",X"00",X"19",X"EB",X"21",X"4D",
+		X"40",X"01",X"05",X"00",X"ED",X"B0",X"C1",X"D1",X"E1",X"C9",X"C5",X"F5",X"FD",X"7E",X"3F",X"FD",
+		X"36",X"3F",X"00",X"CD",X"59",X"2E",X"FD",X"77",X"3F",X"FD",X"36",X"2D",X"0E",X"CD",X"58",X"18",
+		X"CD",X"2C",X"05",X"4F",X"E6",X"0F",X"28",X"F8",X"FE",X"0E",X"30",X"F4",X"79",X"E6",X"3F",X"CD",
+		X"D4",X"2E",X"28",X"EC",X"FD",X"77",X"2D",X"F1",X"C1",X"C9",X"F5",X"CD",X"15",X"08",X"3D",X"20",
+		X"FA",X"F1",X"C9",X"F5",X"3E",X"00",X"CD",X"13",X"27",X"F1",X"C9",X"F5",X"3E",X"20",X"CD",X"13",
+		X"27",X"F1",X"C9",X"F5",X"CD",X"58",X"18",X"CD",X"2B",X"27",X"3E",X"78",X"CD",X"88",X"2A",X"CD",
+		X"15",X"08",X"3D",X"20",X"F7",X"FD",X"36",X"36",X"FF",X"F1",X"C9",X"E5",X"D5",X"C5",X"F5",X"4F",
+		X"FD",X"7E",X"2D",X"E6",X"20",X"B9",X"FD",X"E5",X"E1",X"11",X"42",X"00",X"19",X"28",X"1B",X"06",
+		X"04",X"36",X"00",X"23",X"10",X"FB",X"21",X"74",X"27",X"11",X"28",X"50",X"01",X"01",X"08",X"CD",
+		X"E2",X"0B",X"CD",X"8A",X"1D",X"F1",X"C1",X"D1",X"E1",X"C9",X"44",X"4D",X"54",X"5D",X"3E",X"04",
+		X"CD",X"C1",X"03",X"21",X"7C",X"27",X"11",X"28",X"40",X"01",X"01",X"0B",X"CD",X"E2",X"0B",X"CD",
+		X"6C",X"1D",X"18",X"E1",X"57",X"49",X"4E",X"20",X"4C",X"4F",X"53",X"54",X"57",X"49",X"4E",X"20",
+		X"44",X"4F",X"55",X"42",X"4C",X"45",X"44",X"E5",X"D5",X"C5",X"F5",X"FD",X"7E",X"2A",X"FE",X"09",
+		X"28",X"13",X"FD",X"E5",X"E1",X"11",X"42",X"00",X"19",X"E5",X"3E",X"00",X"06",X"04",X"BE",X"23",
+		X"20",X"08",X"10",X"FA",X"E1",X"F1",X"C1",X"D1",X"E1",X"C9",X"FD",X"E5",X"E1",X"01",X"02",X"00",
+		X"09",X"C1",X"54",X"5D",X"3E",X"04",X"CD",X"C1",X"03",X"18",X"EA",X"E5",X"D5",X"C5",X"F5",X"FD",
+		X"E5",X"E1",X"11",X"42",X"00",X"19",X"EB",X"FD",X"E5",X"E1",X"01",X"06",X"00",X"09",X"FD",X"7E",
+		X"2A",X"07",X"07",X"4F",X"06",X"00",X"09",X"01",X"04",X"00",X"ED",X"B0",X"F1",X"C1",X"D1",X"E1",
+		X"C9",X"E5",X"C5",X"F5",X"CD",X"A9",X"1D",X"CD",X"B5",X"12",X"CD",X"01",X"28",X"06",X"78",X"3E",
+		X"00",X"CD",X"B0",X"04",X"CD",X"15",X"08",X"3C",X"10",X"F7",X"CD",X"B5",X"12",X"F1",X"C1",X"E1",
+		X"C9",X"0D",X"21",X"0F",X"28",X"C8",X"3D",X"21",X"33",X"28",X"C8",X"21",X"5F",X"28",X"C9",X"01",
+		X"1F",X"00",X"0F",X"1B",X"28",X"27",X"28",X"01",X"0C",X"48",X"40",X"50",X"4C",X"41",X"59",X"45",
+		X"52",X"20",X"52",X"45",X"41",X"44",X"59",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"01",X"1F",X"00",X"0F",X"3F",X"28",X"4F",X"28",X"01",X"10",X"48",X"30",X"50",
+		X"4C",X"41",X"59",X"45",X"52",X"20",X"4F",X"4E",X"45",X"20",X"52",X"45",X"41",X"44",X"59",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"01",
+		X"1F",X"00",X"0F",X"6B",X"28",X"4F",X"28",X"01",X"10",X"48",X"30",X"50",X"4C",X"41",X"59",X"45",
+		X"52",X"20",X"54",X"57",X"4F",X"20",X"52",X"45",X"41",X"44",X"59",X"C5",X"F5",X"FD",X"7E",X"46",
+		X"3C",X"28",X"0F",X"06",X"FF",X"FD",X"7E",X"32",X"CD",X"DD",X"0A",X"28",X"02",X"06",X"00",X"FD",
+		X"70",X"46",X"C1",X"78",X"C1",X"C9",X"D5",X"C5",X"F5",X"CD",X"F8",X"28",X"CD",X"37",X"29",X"CD",
+		X"95",X"29",X"CD",X"C8",X"18",X"28",X"42",X"CD",X"BA",X"21",X"3E",X"01",X"CD",X"27",X"17",X"CD",
+		X"61",X"23",X"CD",X"C8",X"18",X"28",X"32",X"CD",X"BA",X"21",X"3E",X"01",X"CD",X"27",X"17",X"7A",
+		X"FD",X"46",X"41",X"04",X"FD",X"36",X"47",X"00",X"FD",X"36",X"41",X"00",X"28",X"E1",X"3E",X"01",
+		X"CD",X"27",X"17",X"CD",X"7D",X"25",X"CD",X"C8",X"18",X"28",X"0E",X"CD",X"87",X"27",X"FD",X"7E",
+		X"37",X"CD",X"33",X"04",X"3E",X"64",X"CD",X"FA",X"26",X"CD",X"78",X"29",X"28",X"04",X"F1",X"C1",
+		X"D1",X"C9",X"FD",X"36",X"01",X"00",X"18",X"F6",X"E5",X"D5",X"C5",X"F5",X"21",X"19",X"29",X"0D",
+		X"28",X"09",X"21",X"23",X"29",X"3D",X"28",X"03",X"21",X"2D",X"29",X"11",X"F8",X"48",X"01",X"01",
+		X"0A",X"CD",X"E2",X"0B",X"F1",X"C1",X"D1",X"E1",X"C9",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"50",X"4C",X"41",X"59",X"45",X"52",X"20",X"4F",X"4E",X"45",X"50",X"4C",X"41",
+		X"59",X"45",X"52",X"20",X"54",X"57",X"4F",X"E5",X"D5",X"C5",X"FD",X"36",X"35",X"00",X"FD",X"36",
+		X"34",X"00",X"FD",X"36",X"38",X"00",X"FD",X"36",X"41",X"FF",X"FD",X"36",X"47",X"FF",X"FD",X"36",
+		X"3F",X"00",X"FD",X"70",X"32",X"FD",X"77",X"37",X"21",X"4D",X"40",X"22",X"5D",X"40",X"21",X"4D",
+		X"40",X"11",X"4E",X"40",X"01",X"0A",X"00",X"36",X"00",X"ED",X"B0",X"CD",X"59",X"2E",X"CD",X"33",
+		X"04",X"CD",X"61",X"16",X"C1",X"D1",X"E1",X"C9",X"E5",X"C5",X"F5",X"FD",X"E5",X"E1",X"01",X"02",
+		X"00",X"09",X"3E",X"00",X"06",X"04",X"BE",X"20",X"07",X"23",X"10",X"FA",X"FD",X"36",X"33",X"02",
+		X"C1",X"78",X"C1",X"E1",X"C9",X"E5",X"F5",X"CD",X"AC",X"18",X"CD",X"73",X"2C",X"CD",X"E1",X"27",
+		X"3E",X"02",X"32",X"8D",X"40",X"21",X"FD",X"29",X"11",X"03",X"2A",X"01",X"06",X"00",X"CD",X"28",
+		X"2A",X"CD",X"4F",X"2A",X"3E",X"00",X"32",X"89",X"40",X"FD",X"36",X"33",X"01",X"FD",X"36",X"36",
+		X"00",X"FD",X"36",X"46",X"00",X"CD",X"C8",X"18",X"28",X"29",X"CD",X"88",X"2A",X"CD",X"F0",X"2A",
+		X"CD",X"3D",X"2A",X"CD",X"7B",X"28",X"20",X"06",X"21",X"F6",X"29",X"CD",X"EF",X"2B",X"67",X"CD",
+		X"2C",X"05",X"7C",X"CD",X"15",X"08",X"3C",X"CD",X"78",X"29",X"FD",X"6E",X"36",X"2C",X"20",X"D5",
+		X"CD",X"25",X"2C",X"F1",X"E1",X"C9",X"03",X"F3",X"2C",X"73",X"2C",X"24",X"2E",X"60",X"00",X"26",
+		X"00",X"24",X"00",X"09",X"2A",X"0A",X"2A",X"14",X"2A",X"00",X"01",X"0F",X"00",X"09",X"26",X"00",
+		X"27",X"00",X"40",X"38",X"01",X"0F",X"00",X"09",X"24",X"00",X"25",X"00",X"40",X"60",X"01",X"0F",
+		X"00",X"09",X"36",X"00",X"36",X"00",X"40",X"38",X"E5",X"D5",X"C5",X"D5",X"11",X"5F",X"40",X"C5",
+		X"ED",X"B0",X"C1",X"E1",X"11",X"75",X"40",X"ED",X"B0",X"C1",X"D1",X"E1",X"C9",X"E5",X"F5",X"3E",
+		X"00",X"FD",X"B6",X"35",X"20",X"06",X"21",X"0A",X"2A",X"22",X"77",X"40",X"F1",X"E1",X"C9",X"E5",
+		X"D5",X"C5",X"F5",X"21",X"5F",X"40",X"11",X"40",X"10",X"7E",X"23",X"06",X"02",X"E5",X"23",X"0E",
+		X"05",X"07",X"DC",X"7C",X"2A",X"F5",X"3E",X"28",X"82",X"57",X"F1",X"0D",X"20",X"F3",X"D1",X"1A",
+		X"11",X"28",X"10",X"E5",X"10",X"E9",X"E1",X"F1",X"C1",X"D1",X"E1",X"C9",X"D5",X"5E",X"23",X"56",
+		X"23",X"E3",X"EB",X"CD",X"35",X"0C",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"21",X"75",X"40",X"CD",
+		X"C5",X"1C",X"FD",X"7E",X"33",X"87",X"5F",X"16",X"00",X"19",X"7E",X"23",X"66",X"6F",X"F1",X"CD",
+		X"37",X"2C",X"F5",X"3E",X"03",X"CD",X"72",X"0B",X"21",X"C5",X"2A",X"11",X"18",X"20",X"01",X"01",
+		X"13",X"CD",X"E2",X"0B",X"21",X"D8",X"2A",X"11",X"10",X"10",X"01",X"01",X"18",X"CD",X"E2",X"0B",
+		X"F1",X"C1",X"D1",X"E1",X"C9",X"53",X"45",X"4C",X"45",X"43",X"54",X"20",X"43",X"48",X"4F",X"49",
+		X"43",X"45",X"20",X"55",X"53",X"49",X"4E",X"47",X"4A",X"4F",X"59",X"53",X"54",X"49",X"43",X"4B",
+		X"20",X"41",X"4E",X"44",X"20",X"46",X"49",X"52",X"45",X"20",X"42",X"55",X"54",X"54",X"4F",X"4E",
+		X"D5",X"F5",X"3E",X"00",X"FD",X"B6",X"34",X"28",X"05",X"FD",X"35",X"34",X"18",X"1B",X"21",X"5F",
+		X"40",X"FD",X"7E",X"32",X"CD",X"94",X"0A",X"3E",X"00",X"B2",X"20",X"10",X"B3",X"20",X"1F",X"18",
+		X"08",X"CD",X"4F",X"2A",X"3E",X"14",X"FD",X"77",X"34",X"F1",X"D1",X"C9",X"7A",X"07",X"38",X"07",
+		X"3E",X"00",X"CD",X"40",X"2B",X"18",X"EA",X"3E",X"01",X"CD",X"40",X"2B",X"18",X"E3",X"7B",X"07",
+		X"38",X"07",X"3E",X"01",X"CD",X"96",X"2B",X"18",X"D8",X"3E",X"00",X"CD",X"96",X"2B",X"18",X"D1",
+		X"E5",X"D5",X"C5",X"F5",X"0F",X"FD",X"7E",X"33",X"38",X"26",X"FE",X"05",X"01",X"00",X"05",X"38",
+		X"03",X"01",X"05",X"0A",X"3C",X"B8",X"20",X"01",X"79",X"CD",X"D3",X"2B",X"20",X"F6",X"CD",X"E8",
+		X"1A",X"CD",X"19",X"1D",X"FD",X"36",X"46",X"00",X"CD",X"AC",X"18",X"FD",X"77",X"33",X"18",X"21",
+		X"FE",X"05",X"01",X"FF",X"04",X"38",X"03",X"01",X"04",X"09",X"3D",X"B9",X"20",X"01",X"78",X"CD",
+		X"D3",X"2B",X"20",X"F6",X"CD",X"E8",X"1A",X"CD",X"19",X"1D",X"FD",X"36",X"46",X"00",X"FD",X"77",
+		X"33",X"F1",X"C1",X"D1",X"E1",X"C9",X"C5",X"F5",X"0F",X"38",X"1D",X"FD",X"7E",X"33",X"3E",X"09",
+		X"FE",X"0A",X"30",X"2C",X"CD",X"D3",X"2B",X"20",X"27",X"CD",X"E8",X"1A",X"CD",X"19",X"1D",X"FD",
+		X"36",X"46",X"00",X"FD",X"77",X"33",X"18",X"18",X"FD",X"7E",X"33",X"D6",X"05",X"38",X"11",X"CD",
+		X"D3",X"2B",X"20",X"0C",X"CD",X"E8",X"1A",X"CD",X"19",X"1D",X"CD",X"AC",X"18",X"FD",X"77",X"33",
+		X"F1",X"C1",X"C9",X"E5",X"C5",X"F5",X"FE",X"05",X"38",X"03",X"23",X"D6",X"05",X"3C",X"47",X"7E",
+		X"07",X"10",X"FD",X"3E",X"00",X"38",X"02",X"3E",X"01",X"B7",X"C1",X"78",X"C1",X"E1",X"C9",X"E5",
+		X"F5",X"3E",X"00",X"FD",X"B6",X"35",X"28",X"05",X"FD",X"35",X"35",X"18",X"25",X"FD",X"7E",X"32",
+		X"CD",X"DD",X"0A",X"3E",X"00",X"28",X"18",X"CD",X"E8",X"1A",X"CD",X"AC",X"18",X"3E",X"00",X"CD",
+		X"88",X"2A",X"FD",X"7E",X"33",X"CD",X"3B",X"00",X"3E",X"0A",X"FD",X"77",X"35",X"3E",X"FF",X"FD",
+		X"77",X"38",X"F1",X"E1",X"C9",X"D5",X"C5",X"F5",X"01",X"50",X"C0",X"11",X"10",X"10",X"3E",X"20",
+		X"CD",X"DD",X"09",X"F1",X"C1",X"D1",X"C9",X"E5",X"D5",X"C5",X"F5",X"4F",X"7E",X"A7",X"28",X"2E",
+		X"47",X"23",X"7E",X"23",X"A1",X"BE",X"23",X"20",X"08",X"23",X"5E",X"23",X"56",X"23",X"23",X"18",
+		X"09",X"BE",X"20",X"14",X"23",X"23",X"23",X"5E",X"23",X"56",X"23",X"7E",X"23",X"E5",X"66",X"6F",
+		X"EB",X"CD",X"35",X"0C",X"E1",X"23",X"18",X"04",X"11",X"07",X"00",X"19",X"10",X"D4",X"F1",X"C1",
+		X"D1",X"E1",X"C9",X"E5",X"D5",X"F5",X"21",X"1E",X"2A",X"22",X"77",X"40",X"CD",X"93",X"2C",X"CD",
+		X"31",X"18",X"3E",X"00",X"FD",X"BE",X"08",X"38",X"04",X"F1",X"D1",X"E1",X"C9",X"F1",X"D1",X"E1",
+		X"C3",X"24",X"2E",X"F5",X"FD",X"7E",X"38",X"3C",X"CA",X"A3",X"2C",X"3E",X"00",X"32",X"89",X"40",
+		X"C3",X"D6",X"2C",X"FD",X"7E",X"02",X"E6",X"0F",X"C2",X"D6",X"2C",X"3A",X"89",X"40",X"E6",X"01",
+		X"CA",X"D6",X"2C",X"FD",X"7E",X"02",X"E6",X"F0",X"C2",X"F4",X"2C",X"3A",X"89",X"40",X"E6",X"02",
+		X"CA",X"F4",X"2C",X"FD",X"7E",X"03",X"E6",X"0F",X"C2",X"3A",X"2D",X"3A",X"89",X"40",X"E6",X"04",
+		X"CA",X"3A",X"2D",X"C3",X"80",X"2D",X"3A",X"89",X"40",X"F6",X"01",X"32",X"89",X"40",X"21",X"EF",
+		X"2C",X"CD",X"E9",X"2D",X"21",X"03",X"17",X"CD",X"BE",X"2D",X"CD",X"59",X"1C",X"F1",X"C9",X"01",
+		X"00",X"00",X"00",X"C9",X"3A",X"89",X"40",X"F6",X"02",X"32",X"89",X"40",X"3E",X"0A",X"CD",X"FA",
+		X"26",X"21",X"12",X"2D",X"CD",X"E9",X"2D",X"21",X"16",X"2D",X"CD",X"BE",X"2D",X"CD",X"74",X"1C",
+		X"F1",X"C9",X"10",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"20",X"00",X"00",X"00",X"40",X"00",
+		X"00",X"00",X"70",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"04",
+		X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"20",X"00",X"00",X"3A",X"89",X"40",X"F6",X"04",X"32",
+		X"89",X"40",X"3E",X"0A",X"CD",X"FA",X"26",X"21",X"58",X"2D",X"CD",X"E9",X"2D",X"21",X"5C",X"2D",
+		X"CD",X"BE",X"2D",X"CD",X"8F",X"1C",X"F1",X"C9",X"00",X"01",X"00",X"00",X"00",X"01",X"00",X"00",
+		X"00",X"02",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"10",X"00",X"00",
+		X"00",X"20",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"70",X"00",X"00",X"00",X"00",X"02",X"00",
+		X"3E",X"0A",X"CD",X"FA",X"26",X"21",X"96",X"2D",X"CD",X"E9",X"2D",X"21",X"9A",X"2D",X"CD",X"BE",
+		X"2D",X"CD",X"AA",X"1C",X"F1",X"C9",X"00",X"10",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"20",
+		X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"70",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",
+		X"02",X"00",X"00",X"00",X"04",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"20",X"00",X"E5",X"D5",
+		X"C5",X"F5",X"E5",X"FD",X"E5",X"E1",X"11",X"06",X"00",X"19",X"EB",X"6B",X"62",X"C1",X"3E",X"09",
+		X"F5",X"3E",X"04",X"CD",X"C1",X"03",X"03",X"03",X"03",X"03",X"23",X"23",X"23",X"23",X"5D",X"54",
+		X"F1",X"3D",X"20",X"EC",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"E5",X"FD",X"E5",
+		X"E1",X"01",X"02",X"00",X"09",X"EB",X"42",X"4B",X"E1",X"3E",X"04",X"CD",X"09",X"2E",X"FD",X"7E",
+		X"37",X"CD",X"33",X"04",X"F1",X"C1",X"D1",X"E1",X"C9",X"A7",X"C8",X"E5",X"D5",X"C5",X"F5",X"F5",
+		X"97",X"0A",X"9E",X"27",X"12",X"03",X"13",X"23",X"E3",X"25",X"E3",X"20",X"F4",X"E1",X"E1",X"7C",
+		X"C1",X"D1",X"E1",X"C9",X"E5",X"D5",X"C5",X"F5",X"21",X"5F",X"40",X"3A",X"8D",X"40",X"87",X"4F",
+		X"06",X"00",X"09",X"11",X"35",X"00",X"73",X"23",X"72",X"CD",X"4F",X"2A",X"3E",X"00",X"CD",X"27",
+		X"17",X"FD",X"36",X"36",X"FF",X"CD",X"59",X"2E",X"CD",X"77",X"2E",X"CD",X"A0",X"2E",X"CD",X"FE",
+		X"1C",X"CD",X"58",X"18",X"F1",X"C1",X"D1",X"E1",X"C9",X"E5",X"C5",X"F5",X"FD",X"7E",X"3F",X"FD",
+		X"E5",X"E1",X"01",X"2B",X"00",X"09",X"06",X"05",X"0F",X"38",X"02",X"36",X"00",X"23",X"10",X"F8",
+		X"CD",X"58",X"18",X"F1",X"C1",X"E1",X"C9",X"E5",X"C5",X"F5",X"FD",X"7E",X"3F",X"FD",X"E5",X"E1",
+		X"01",X"2B",X"00",X"09",X"06",X"05",X"0F",X"38",X"10",X"36",X"0E",X"CD",X"58",X"18",X"CD",X"E5",
+		X"1C",X"0E",X"1E",X"CD",X"15",X"08",X"0D",X"20",X"FA",X"23",X"10",X"EA",X"F1",X"C1",X"E1",X"C9",
+		X"E5",X"D5",X"C5",X"F5",X"FD",X"7E",X"3F",X"FD",X"E5",X"E1",X"01",X"2B",X"00",X"09",X"5D",X"54",
+		X"06",X"05",X"0F",X"F5",X"38",X"15",X"CD",X"2C",X"05",X"4F",X"E6",X"0F",X"28",X"F8",X"FE",X"0E",
+		X"30",X"F4",X"79",X"E6",X"3F",X"CD",X"D4",X"2E",X"28",X"EC",X"12",X"13",X"F1",X"10",X"E3",X"F1",
+		X"C1",X"D1",X"E1",X"C9",X"E5",X"C5",X"F5",X"21",X"4D",X"40",X"06",X"0E",X"BE",X"23",X"28",X"0D",
+		X"10",X"FA",X"2A",X"5D",X"40",X"77",X"23",X"22",X"5D",X"40",X"3E",X"01",X"B7",X"C1",X"78",X"C1",
+		X"E1",X"C9",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"FF",X"FF",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",
+		X"3F",X"7F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",X"3F",
+		X"7F",X"FF",X"FF",X"3F",X"FF",X"FF",X"FF",X"3F",X"3F",X"3F",X"FF",X"FF",X"FF",X"7F",X"3F",X"3F",
+		X"FF",X"3F",X"BF",X"FF",X"BF",X"3F",X"3F",X"3F",X"3F",X"3F",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/ROM_PGM_0.vhd
index 8cbdb31c..a560a391 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/ROM_PGM_0.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity UNIWARS_ROM_PGM_0 is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of ROM_PGM_0 is
+architecture prom of UNIWARS_ROM_PGM_0 is
 	type rom is array(0 to  16383) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"AF",X"32",X"01",X"70",X"C3",X"59",X"1A",X"FF",X"3A",X"07",X"40",X"0F",X"D0",X"33",X"33",X"C9",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1H.vhd
index 68faa089..f5dcbba9 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1H.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity UNIWARS_1H is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(11 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1H is
+architecture prom of UNIWARS_1H is
 	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1K.vhd
index 479fc3d9..40a985b7 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_1K.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity UNIWARS_1K is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(11 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_1K is
+architecture prom of UNIWARS_1K is
 	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_6L.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_6L.vhd
similarity index 91%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_6L.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_6L.vhd
index 3c34489f..f8909bd7 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GALAXIAN_6L.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/uniwars/UNIWARS_6L.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity UNIWARS_6L is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of GALAXIAN_6L is
+architecture prom of UNIWARS_6L is
 	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"E8",X"17",X"3F",X"00",X"2F",X"87",X"20",X"00",X"FF",X"3F",X"38",X"00",X"83",X"3F",X"06",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/col.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/col.vhd
similarity index 91%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/col.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/col.vhd
index fa425023..386b59eb 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/col.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/col.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity col is
+entity VICTORY_6L is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(4 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of col is
+architecture prom of VICTORY_6L is
 	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"07",X"15",X"E4",X"00",X"BC",X"6C",X"6C",X"00",X"38",X"00",X"A7",X"00",X"00",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/h_rom.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/h_rom.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/h_rom.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/h_rom.vhd
index f4d82a16..343a0b65 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/h_rom.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/h_rom.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity h_rom is
+entity VICTORY_1H is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of h_rom is
+architecture prom of VICTORY_1H is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"7C",X"82",X"82",X"82",X"82",X"7C",X"00",X"00",X"02",X"02",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/k_rom.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/k_rom.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/k_rom.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/k_rom.vhd
index cd100cb3..59fcdb19 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/k_rom.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/k_rom.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity k_rom is
+entity VICTORY_1K is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(10 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of k_rom is
+architecture prom of VICTORY_1K is
 	type rom is array(0 to  2047) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"00",X"7C",X"82",X"82",X"82",X"82",X"7C",X"00",X"00",X"02",X"02",X"FE",X"42",X"02",X"00",X"00",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/prog.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/prog.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/prog.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/prog.vhd
index c8fdb367..ef448913 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/prog.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/victory/prog.vhd	
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all,ieee.numeric_std.all;
 
-entity prog is
+entity VICTORY_ROM_PGM_0 is
 port (
 	clk  : in  std_logic;
 	addr : in  std_logic_vector(13 downto 0);
@@ -9,7 +9,7 @@ port (
 );
 end entity;
 
-architecture prom of prog is
+architecture prom of VICTORY_ROM_PGM_0 is
 	type rom is array(0 to  10239) of std_logic_vector(7 downto 0);
 	signal rom_data: rom := (
 		X"31",X"00",X"44",X"C3",X"40",X"02",X"00",X"FF",X"FF",X"FF",X"FF",X"20",X"20",X"20",X"20",X"20",
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/ROM_PGM_0.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/ROM_PGM_0.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/ROM_PGM_0.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/ROM_PGM_0.vhd
index c5c2e037..6e7dde14 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/ROM_PGM_0.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/ROM_PGM_0.vhd	
@@ -1,10 +1,9 @@
 -- generated with romgen v3.0 by MikeJ
 library ieee;
   use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity ROM_PGM_0 is
+entity WAROFBUGS_ROM_PGM_0 is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(13 downto 0);
@@ -12,11 +11,11 @@ entity ROM_PGM_0 is
     );
 end;
 
-architecture RTL of ROM_PGM_0 is
+architecture prom of WAROFBUGS_ROM_PGM_0 is
 
 
   type ROM_ARRAY is array(0 to 10087) of std_logic_vector(7 downto 0);
-  constant ROM : ROM_ARRAY := (
+  signal ROM : ROM_ARRAY := (
     x"31",x"00",x"44",x"AF",x"C3",x"00",x"03",x"C3", -- 0x0000
     x"46",x"0B",x"55",x"50",x"4F",x"00",x"84",x"54", -- 0x0008
     x"77",x"23",x"10",x"FC",x"C9",x"06",x"C2",x"4C", -- 0x0010
@@ -1281,10 +1280,12 @@ architecture RTL of ROM_PGM_0 is
   );
 
 begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= ROM(to_integer(unsigned(addr)));
+	end if;
 
-  p_rom : process
-  begin
-    wait until rising_edge(CLK);
-       DATA <= ROM(to_integer(unsigned(ADDR)));
-  end process;
-end RTL;
+end process;
+
+end prom;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1H.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1H.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1H.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1H.vhd
index a6558456..1fea1ba6 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1H.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1H.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_1H is
+entity WAROFBUGS_1H is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(10 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_1H is
     );
 end;
 
-architecture RTL of GALAXIAN_1H is
+architecture RTL of WAROFBUGS_1H is
 
 
   type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1K.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1K.vhd
similarity index 99%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1K.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1K.vhd
index 25f4acf1..3daf8157 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GALAXIAN_1K.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_1K.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_1K is
+entity WAROFBUGS_1K is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(10 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_1K is
     );
 end;
 
-architecture RTL of GALAXIAN_1K is
+architecture RTL of WAROFBUGS_1K is
 
 
   type ROM_ARRAY is array(0 to 2047) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/galaxian_6l.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_6L.vhd
similarity index 93%
rename from Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/galaxian_6l.vhd
rename to Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_6L.vhd
index 7eb01da4..64471aa9 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/galaxian_6l.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/warofbugs/WAROFBUGS_6L.vhd	
@@ -4,7 +4,7 @@ library ieee;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
 
-entity GALAXIAN_6L is
+entity WAROFBUGS_6L is
   port (
     CLK         : in    std_logic;
     ADDR        : in    std_logic_vector(4 downto 0);
@@ -12,7 +12,7 @@ entity GALAXIAN_6L is
     );
 end;
 
-architecture RTL of GALAXIAN_6L is
+architecture RTL of WAROFBUGS_6L is
 
 
   type ROM_ARRAY is array(0 to 31) of std_logic_vector(7 downto 0);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/col.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/col.vhd
new file mode 100644
index 00000000..c491b15e
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/col.vhd	
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ZIGZAG_6L is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(4 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ZIGZAG_6L is
+	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38",X"00",X"F0",X"15",X"1F",X"00",X"F6",X"06",X"07",
+		X"00",X"91",X"07",X"F6",X"00",X"F0",X"FE",X"07",X"00",X"38",X"07",X"FE",X"00",X"07",X"3F",X"FE");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/prog.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/prog.vhd
new file mode 100644
index 00000000..57565562
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/prog.vhd	
@@ -0,0 +1,1046 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ZIGZAG_ROM_PGM_0 is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(13 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ZIGZAG_ROM_PGM_0 is
+	type rom is array(0 to  16383) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"32",X"01",X"70",X"C3",X"82",X"01",X"84",X"AF",X"21",X"06",X"70",X"77",X"23",X"77",X"C9",
+		X"F5",X"C5",X"D5",X"E5",X"5E",X"23",X"56",X"23",X"E5",X"C1",X"EB",X"11",X"20",X"00",X"0A",X"FE",
+		X"FF",X"28",X"07",X"D6",X"30",X"77",X"03",X"19",X"18",X"F4",X"E1",X"D1",X"C1",X"F1",X"C9",X"67",
+		X"21",X"07",X"42",X"06",X"1B",X"71",X"23",X"23",X"10",X"FB",X"3A",X"00",X"78",X"21",X"00",X"42",
+		X"11",X"40",X"42",X"06",X"20",X"AF",X"77",X"12",X"13",X"23",X"23",X"10",X"F9",X"06",X"20",X"12",
+		X"13",X"10",X"FC",X"C9",X"DB",X"28",X"0C",X"D9",X"CD",X"12",X"DA",X"D9",X"28",X"0A",X"CD",X"3A",
+		X"84",X"18",X"DF",X"CD",X"35",X"84",X"F5",X"C5",X"D5",X"E5",X"DD",X"E5",X"FD",X"E5",X"AF",X"32",
+		X"01",X"70",X"3A",X"00",X"78",X"21",X"00",X"42",X"01",X"60",X"00",X"11",X"00",X"58",X"ED",X"B0",
+		X"21",X"BB",X"42",X"34",X"21",X"84",X"42",X"CD",X"E2",X"00",X"CD",X"2F",X"31",X"21",X"60",X"42",
+		X"01",X"20",X"00",X"11",X"60",X"58",X"ED",X"B0",X"CD",X"1F",X"34",X"3A",X"CE",X"42",X"B7",X"C4",
+		X"F4",X"00",X"CD",X"0B",X"01",X"CD",X"67",X"01",X"CD",X"8A",X"36",X"21",X"02",X"70",X"3E",X"FF",
+		X"77",X"00",X"00",X"C3",X"97",X"20",X"AF",X"21",X"02",X"70",X"77",X"7A",X"B7",X"28",X"0E",X"31",
+		X"00",X"48",X"21",X"22",X"04",X"E5",X"3E",X"01",X"32",X"01",X"70",X"ED",X"45",X"FD",X"E1",X"DD",
+		X"E1",X"E1",X"D1",X"C1",X"3E",X"01",X"32",X"01",X"70",X"F1",X"ED",X"45",X"3A",X"00",X"60",X"CB",
+		X"47",X"C9",X"34",X"7E",X"FE",X"3C",X"C0",X"36",X"00",X"23",X"34",X"C9",X"3A",X"86",X"42",X"E6",
+		X"03",X"FE",X"03",X"C9",X"3A",X"BB",X"42",X"CB",X"5F",X"20",X"08",X"FD",X"66",X"0B",X"FD",X"6E",
+		X"0A",X"D7",X"C9",X"FD",X"66",X"0D",X"FD",X"6E",X"0C",X"D7",X"C9",X"3A",X"84",X"42",X"B7",X"C0",
+		X"3A",X"BD",X"42",X"CB",X"47",X"28",X"0D",X"21",X"BC",X"42",X"35",X"20",X"07",X"21",X"8F",X"42",
+		X"CB",X"9E",X"CB",X"87",X"CB",X"4F",X"28",X"08",X"21",X"A5",X"42",X"35",X"20",X"02",X"CB",X"8F",
+		X"CB",X"57",X"28",X"08",X"21",X"A4",X"42",X"35",X"20",X"02",X"CB",X"97",X"CB",X"5F",X"28",X"23",
+		X"21",X"A6",X"42",X"35",X"20",X"1D",X"4F",X"21",X"9E",X"42",X"CB",X"3E",X"7E",X"CB",X"3E",X"86",
+		X"77",X"21",X"9F",X"42",X"CB",X"3E",X"7E",X"CB",X"3E",X"86",X"77",X"21",X"CA",X"42",X"CB",X"D6",
+		X"79",X"CB",X"9F",X"32",X"BD",X"42",X"C9",X"3A",X"8B",X"42",X"B7",X"C8",X"21",X"CA",X"42",X"CB",
+		X"46",X"C0",X"21",X"CC",X"42",X"CB",X"46",X"C0",X"21",X"CA",X"42",X"CB",X"C6",X"21",X"8B",X"42",
+		X"35",X"C9",X"31",X"00",X"48",X"CD",X"97",X"37",X"21",X"00",X"40",X"36",X"00",X"3A",X"00",X"78",
+		X"23",X"7C",X"FE",X"71",X"20",X"F5",X"32",X"00",X"78",X"32",X"1F",X"49",X"3A",X"AB",X"C0",X"FE",
+		X"CF",X"00",X"00",X"00",X"21",X"00",X"50",X"06",X"10",X"0E",X"54",X"CD",X"FD",X"04",X"21",X"03",
+		X"42",X"3E",X"07",X"77",X"23",X"23",X"77",X"21",X"07",X"05",X"D7",X"21",X"21",X"05",X"D7",X"21",
+		X"3D",X"42",X"3E",X"05",X"77",X"23",X"23",X"77",X"21",X"52",X"05",X"D7",X"3A",X"00",X"78",X"21",
+		X"D2",X"05",X"01",X"07",X"00",X"11",X"87",X"40",X"ED",X"B0",X"21",X"DA",X"05",X"01",X"07",X"00",
+		X"11",X"87",X"41",X"ED",X"B0",X"3A",X"00",X"78",X"21",X"35",X"38",X"01",X"E0",X"00",X"11",X"D2",
+		X"42",X"ED",X"B0",X"CD",X"DF",X"0C",X"3A",X"00",X"70",X"47",X"3A",X"00",X"68",X"17",X"CB",X"10",
+		X"17",X"CB",X"10",X"78",X"32",X"86",X"42",X"21",X"86",X"42",X"ED",X"6F",X"47",X"ED",X"67",X"78",
+		X"E6",X"03",X"3C",X"32",X"87",X"42",X"3A",X"86",X"42",X"CB",X"5F",X"28",X"05",X"21",X"87",X"41",
+		X"36",X"00",X"3E",X"EA",X"32",X"A7",X"42",X"3E",X"01",X"32",X"01",X"70",X"CD",X"EC",X"00",X"CA",
+		X"22",X"04",X"31",X"00",X"48",X"CF",X"0E",X"1B",X"CD",X"DC",X"04",X"0E",X"01",X"F7",X"CD",X"D7",
+		X"0B",X"21",X"88",X"0B",X"D7",X"21",X"C4",X"05",X"D7",X"06",X"05",X"CD",X"C8",X"0C",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",X"20",X"00",X"21",
+		X"46",X"50",X"06",X"1C",X"C5",X"E5",X"06",X"08",X"36",X"50",X"23",X"10",X"FB",X"E1",X"19",X"C1",
+		X"10",X"F2",X"21",X"68",X"53",X"11",X"C2",X"03",X"06",X"18",X"C5",X"E5",X"06",X"04",X"1A",X"77",
+		X"23",X"13",X"10",X"FA",X"E1",X"01",X"20",X"00",X"A7",X"ED",X"42",X"C1",X"10",X"EC",X"06",X"03",
+		X"CD",X"C8",X"0C",X"21",X"E4",X"53",X"22",X"91",X"42",X"21",X"8E",X"42",X"36",X"00",X"21",X"5C",
+		X"42",X"36",X"00",X"23",X"36",X"3A",X"23",X"36",X"05",X"23",X"36",X"20",X"3E",X"11",X"CD",X"97",
+		X"03",X"CD",X"F3",X"22",X"CD",X"A9",X"07",X"06",X"28",X"CD",X"C0",X"0C",X"3A",X"8F",X"42",X"CB",
+		X"47",X"20",X"EE",X"3E",X"43",X"CD",X"97",X"03",X"CD",X"A8",X"22",X"CD",X"A9",X"07",X"06",X"28",
+		X"CD",X"C0",X"0C",X"3A",X"8F",X"42",X"CB",X"47",X"20",X"EE",X"3A",X"5F",X"42",X"FE",X"60",X"20",
+		X"E2",X"3E",X"13",X"CD",X"97",X"03",X"CD",X"F3",X"22",X"CD",X"A9",X"07",X"06",X"28",X"CD",X"C0",
+		X"0C",X"3A",X"8F",X"42",X"CB",X"47",X"20",X"EE",X"3A",X"5C",X"42",X"DD",X"21",X"08",X"53",X"FE",
+		X"40",X"CC",X"A1",X"03",X"DD",X"21",X"88",X"52",X"FE",X"60",X"CC",X"A1",X"03",X"DD",X"21",X"08",
+		X"52",X"FE",X"80",X"CC",X"A1",X"03",X"DD",X"21",X"88",X"51",X"FE",X"A0",X"CC",X"A1",X"03",X"DD",
+		X"21",X"08",X"51",X"FE",X"C0",X"CC",X"A1",X"03",X"DD",X"21",X"88",X"50",X"FE",X"E0",X"CC",X"A1",
+		X"03",X"FE",X"E0",X"20",X"AC",X"3E",X"83",X"CD",X"97",X"03",X"CD",X"5D",X"22",X"CD",X"A9",X"07",
+		X"06",X"28",X"CD",X"C0",X"0C",X"3A",X"8F",X"42",X"CB",X"47",X"20",X"EE",X"3A",X"5F",X"42",X"FE",
+		X"30",X"20",X"E2",X"3E",X"87",X"CD",X"97",X"03",X"CD",X"5D",X"22",X"CD",X"A9",X"07",X"06",X"28",
+		X"CD",X"C0",X"0C",X"3A",X"8F",X"42",X"CB",X"47",X"20",X"EE",X"3E",X"11",X"CD",X"97",X"03",X"CD",
+		X"F3",X"22",X"CD",X"A9",X"07",X"06",X"28",X"CD",X"C0",X"0C",X"3A",X"8F",X"42",X"CB",X"47",X"20",
+		X"EE",X"06",X"08",X"CD",X"C8",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"C3",X"32",X"02",X"21",X"8F",X"42",X"77",X"3E",X"08",X"32",X"9B",X"42",
+		X"C9",X"F5",X"06",X"06",X"DD",X"7E",X"03",X"DD",X"77",X"05",X"DD",X"7E",X"23",X"DD",X"77",X"25",
+		X"DD",X"7E",X"43",X"DD",X"77",X"45",X"DD",X"7E",X"63",X"DD",X"77",X"65",X"DD",X"2B",X"10",X"E4",
+		X"F1",X"C9",X"F2",X"F7",X"F7",X"F3",X"F4",X"E6",X"E7",X"F5",X"F4",X"E4",X"E5",X"F5",X"F0",X"F6",
+		X"F6",X"F1",X"F2",X"F7",X"F7",X"F3",X"F4",X"E2",X"E3",X"F5",X"F4",X"E0",X"E1",X"F5",X"F0",X"F6",
+		X"F6",X"F1",X"F2",X"F7",X"F7",X"F3",X"F4",X"EA",X"EB",X"F5",X"F4",X"E8",X"E9",X"F5",X"F0",X"F6",
+		X"F6",X"F1",X"F2",X"F7",X"F7",X"F3",X"F4",X"E6",X"E7",X"F5",X"F4",X"E4",X"E5",X"F5",X"F0",X"F6",
+		X"F6",X"F1",X"F2",X"F7",X"F7",X"F3",X"F4",X"EE",X"EF",X"F5",X"F4",X"EC",X"ED",X"F5",X"F0",X"F6",
+		X"F6",X"F1",X"F2",X"F7",X"F7",X"F3",X"F4",X"EA",X"EB",X"F5",X"F4",X"E8",X"E9",X"F5",X"F0",X"F6",
+		X"F6",X"F1",X"31",X"00",X"48",X"CF",X"0E",X"1B",X"CD",X"DC",X"04",X"0E",X"02",X"F7",X"21",X"5A",
+		X"05",X"D7",X"21",X"90",X"05",X"D7",X"21",X"AA",X"05",X"D7",X"21",X"C4",X"05",X"D7",X"21",X"95",
+		X"51",X"3A",X"87",X"42",X"77",X"CD",X"EC",X"00",X"28",X"3C",X"21",X"3A",X"05",X"D7",X"3A",X"88",
+		X"42",X"FE",X"02",X"38",X"05",X"21",X"7F",X"05",X"18",X"03",X"21",X"6E",X"05",X"D7",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3A",X"88",X"42",X"47",
+		X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",X"32",X"BE",X"52",X"78",X"E6",X"0F",X"32",X"9E",
+		X"52",X"CD",X"93",X"04",X"18",X"C8",X"21",X"46",X"05",X"D7",X"21",X"7F",X"05",X"D7",X"CD",X"93",
+		X"04",X"18",X"FB",X"21",X"00",X"68",X"CB",X"46",X"20",X"1F",X"CB",X"4E",X"20",X"01",X"C9",X"CD",
+		X"EC",X"00",X"28",X"06",X"3A",X"88",X"42",X"FE",X"02",X"D8",X"21",X"E8",X"05",X"D7",X"21",X"03",
+		X"06",X"D7",X"3E",X"02",X"32",X"8D",X"42",X"18",X"0D",X"21",X"F4",X"05",X"D7",X"21",X"15",X"06",
+		X"D7",X"3E",X"01",X"32",X"8D",X"42",X"21",X"FA",X"05",X"D7",X"47",X"CD",X"EC",X"00",X"CA",X"A5",
+		X"08",X"3A",X"88",X"42",X"90",X"27",X"32",X"88",X"42",X"C3",X"A5",X"08",X"E5",X"C5",X"21",X"00",
+		X"50",X"23",X"23",X"23",X"41",X"3E",X"10",X"77",X"23",X"10",X"FC",X"3A",X"00",X"78",X"79",X"FE",
+		X"1D",X"28",X"02",X"23",X"23",X"7C",X"FE",X"54",X"20",X"E7",X"C1",X"E1",X"C9",X"70",X"3A",X"00",
+		X"78",X"23",X"7C",X"B9",X"20",X"F7",X"C9",X"81",X"50",X"50",X"55",X"32",X"40",X"40",X"40",X"40",
+		X"45",X"52",X"4F",X"43",X"53",X"40",X"48",X"47",X"49",X"48",X"40",X"40",X"40",X"50",X"55",X"31",
+		X"FF",X"62",X"50",X"30",X"30",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"30",X"30",X"40",
+		X"40",X"40",X"40",X"40",X"40",X"40",X"40",X"30",X"30",X"FF",X"9E",X"52",X"40",X"40",X"40",X"54",
+		X"49",X"44",X"45",X"52",X"43",X"FF",X"9E",X"52",X"59",X"41",X"4C",X"50",X"40",X"45",X"45",X"52",
+		X"46",X"FF",X"DE",X"50",X"44",X"4E",X"55",X"4F",X"52",X"FF",X"0E",X"51",X"4E",X"4F",X"54",X"54",
+		X"55",X"42",X"40",X"54",X"52",X"41",X"54",X"53",X"40",X"48",X"53",X"55",X"50",X"FF",X"31",X"51",
+		X"40",X"59",X"4C",X"4E",X"4F",X"40",X"52",X"45",X"59",X"41",X"4C",X"50",X"40",X"31",X"FF",X"31",
+		X"51",X"53",X"52",X"45",X"59",X"41",X"4C",X"50",X"40",X"32",X"40",X"52",X"4F",X"40",X"31",X"FF",
+		X"95",X"50",X"53",X"54",X"50",X"40",X"30",X"30",X"30",X"30",X"40",X"40",X"52",X"4F",X"46",X"40",
+		X"53",X"55",X"4E",X"4F",X"42",X"40",X"54",X"53",X"31",X"FF",X"97",X"50",X"53",X"54",X"50",X"40",
+		X"30",X"30",X"30",X"30",X"36",X"40",X"52",X"4F",X"46",X"40",X"53",X"55",X"4E",X"4F",X"42",X"40",
+		X"44",X"4E",X"32",X"FF",X"1B",X"51",X"32",X"38",X"39",X"31",X"40",X"40",X"58",X"41",X"4C",X"40",
+		X"B0",X"FF",X"00",X"82",X"53",X"E2",X"05",X"EE",X"05",X"00",X"01",X"02",X"51",X"E8",X"05",X"F4",
+		X"05",X"00",X"01",X"53",X"50",X"55",X"31",X"FF",X"81",X"50",X"50",X"55",X"32",X"FF",X"01",X"53",
+		X"40",X"40",X"40",X"FF",X"81",X"50",X"40",X"40",X"40",X"FF",X"E2",X"52",X"30",X"30",X"40",X"40",
+		X"40",X"40",X"FF",X"62",X"50",X"30",X"30",X"40",X"40",X"40",X"40",X"FF",X"E2",X"52",X"40",X"40",
+		X"40",X"40",X"40",X"40",X"FF",X"62",X"50",X"40",X"40",X"40",X"40",X"40",X"40",X"FF",X"FD",X"7E",
+		X"03",X"F5",X"0E",X"00",X"11",X"20",X"00",X"21",X"9E",X"50",X"CD",X"89",X"07",X"F1",X"11",X"40",
+		X"00",X"4F",X"A7",X"28",X"3B",X"E6",X"F0",X"0F",X"0F",X"0F",X"0F",X"47",X"79",X"E6",X"0F",X"FE",
+		X"05",X"F5",X"38",X"02",X"D6",X"05",X"4F",X"DD",X"21",X"44",X"50",X"78",X"A7",X"28",X"09",X"3E",
+		X"BC",X"CD",X"AF",X"06",X"DD",X"19",X"10",X"F7",X"F1",X"38",X"07",X"3E",X"B8",X"CD",X"AF",X"06",
+		X"DD",X"19",X"79",X"41",X"A7",X"28",X"09",X"3E",X"B4",X"CD",X"AF",X"06",X"DD",X"19",X"10",X"F7",
+		X"DD",X"E5",X"E1",X"7C",X"FE",X"54",X"D0",X"3E",X"10",X"CD",X"BF",X"06",X"DD",X"19",X"18",X"F0",
+		X"C5",X"D5",X"E5",X"DD",X"E5",X"FD",X"7E",X"05",X"11",X"C0",X"FF",X"DD",X"21",X"9E",X"53",X"0E",
+		X"09",X"47",X"A7",X"28",X"0A",X"3E",X"F8",X"CD",X"AF",X"06",X"DD",X"19",X"0D",X"10",X"F6",X"3E",
+		X"10",X"CD",X"BF",X"06",X"DD",X"19",X"0D",X"20",X"F6",X"DD",X"E1",X"E1",X"D1",X"C1",X"C9",X"DD",
+		X"77",X"00",X"3C",X"DD",X"77",X"01",X"3C",X"DD",X"77",X"20",X"3C",X"DD",X"77",X"21",X"C9",X"DD",
+		X"77",X"00",X"DD",X"77",X"01",X"DD",X"77",X"20",X"DD",X"77",X"21",X"C9",X"F5",X"C5",X"D5",X"E5",
+		X"DD",X"E5",X"FD",X"E5",X"E1",X"7A",X"86",X"27",X"77",X"79",X"23",X"8E",X"27",X"77",X"78",X"23",
+		X"8E",X"27",X"77",X"47",X"FD",X"7E",X"04",X"E6",X"03",X"FE",X"03",X"28",X"3C",X"4F",X"78",X"FE",
+		X"06",X"38",X"1C",X"FD",X"CB",X"04",X"CE",X"FD",X"34",X"05",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E5",X"21",X"CA",X"42",X"CB",X"CE",X"E1",X"CB",
+		X"41",X"20",X"16",X"3A",X"87",X"42",X"4F",X"78",X"B9",X"38",X"0E",X"FD",X"CB",X"04",X"C6",X"FD",
+		X"34",X"05",X"E5",X"21",X"CA",X"42",X"CB",X"CE",X"E1",X"CD",X"80",X"06",X"DD",X"21",X"80",X"42",
+		X"11",X"82",X"42",X"EB",X"CD",X"3F",X"07",X"CD",X"3F",X"07",X"CD",X"3F",X"07",X"18",X"1B",X"46",
+		X"1A",X"B8",X"1B",X"2B",X"C8",X"C1",X"38",X"12",X"FD",X"7E",X"00",X"DD",X"77",X"00",X"FD",X"7E",
+		X"01",X"DD",X"77",X"01",X"FD",X"7E",X"02",X"DD",X"77",X"02",X"21",X"42",X"52",X"CD",X"74",X"07",
+		X"FD",X"E5",X"DD",X"E1",X"FD",X"66",X"09",X"FD",X"6E",X"08",X"CD",X"74",X"07",X"DD",X"E1",X"E1",
+		X"D1",X"C1",X"F1",X"C9",X"C5",X"D5",X"11",X"20",X"00",X"01",X"00",X"03",X"DD",X"7E",X"02",X"CD",
+		X"89",X"07",X"DD",X"2B",X"10",X"F6",X"D1",X"C1",X"C9",X"F5",X"CB",X"3F",X"CB",X"3F",X"CB",X"3F",
+		X"CB",X"3F",X"CD",X"98",X"07",X"F1",X"E6",X"0F",X"20",X"08",X"CB",X"41",X"20",X"04",X"3E",X"10",
+		X"18",X"02",X"CB",X"C1",X"77",X"A7",X"ED",X"52",X"C9",X"21",X"8E",X"42",X"7E",X"E6",X"C3",X"20",
+		X"2F",X"3A",X"9B",X"42",X"E6",X"01",X"47",X"CD",X"DE",X"33",X"4F",X"28",X"11",X"3E",X"36",X"CB",
+		X"59",X"20",X"02",X"3E",X"3A",X"80",X"CB",X"61",X"20",X"13",X"CB",X"FF",X"18",X"0F",X"3E",X"34",
+		X"CB",X"59",X"20",X"02",X"3E",X"38",X"80",X"CB",X"79",X"20",X"02",X"F6",X"C0",X"32",X"5D",X"42",
+		X"CD",X"10",X"2B",X"CD",X"1F",X"2B",X"D8",X"79",X"E6",X"0B",X"20",X"F7",X"CB",X"51",X"20",X"3A",
+		X"CB",X"58",X"28",X"0F",X"CB",X"48",X"28",X"04",X"3E",X"19",X"18",X"02",X"3E",X"19",X"CD",X"44",
+		X"08",X"18",X"24",X"CB",X"48",X"28",X"04",X"3E",X"15",X"18",X"02",X"3E",X"17",X"CD",X"44",X"08",
+		X"57",X"78",X"E6",X"30",X"28",X"09",X"7A",X"CB",X"60",X"20",X"0C",X"CB",X"FF",X"18",X"08",X"23",
+		X"7E",X"E6",X"C0",X"B2",X"77",X"18",X"BC",X"23",X"18",X"FA",X"DD",X"7E",X"08",X"E5",X"CB",X"48",
+		X"28",X"05",X"21",X"4B",X"08",X"18",X"03",X"21",X"50",X"08",X"3D",X"28",X"03",X"23",X"18",X"FA",
+		X"7E",X"E1",X"18",X"CC",X"DD",X"CB",X"03",X"56",X"C8",X"3C",X"C9",X"15",X"0D",X"0E",X"0F",X"10",
+		X"17",X"11",X"12",X"13",X"14",X"3A",X"8E",X"42",X"CB",X"47",X"C0",X"CB",X"77",X"C8",X"3A",X"AB",
+		X"42",X"B7",X"C0",X"21",X"9D",X"42",X"7E",X"B7",X"CC",X"93",X"08",X"35",X"C0",X"36",X"C0",X"21",
+		X"9B",X"42",X"35",X"46",X"20",X"0B",X"21",X"8E",X"42",X"CB",X"C6",X"3E",X"00",X"32",X"5D",X"42",
+		X"C9",X"21",X"8F",X"08",X"05",X"28",X"03",X"23",X"18",X"FA",X"7E",X"32",X"5D",X"42",X"C9",X"3F",
+		X"3E",X"3D",X"3C",X"E5",X"21",X"40",X"42",X"06",X"18",X"AF",X"77",X"23",X"10",X"FC",X"21",X"CB",
+		X"42",X"CB",X"DE",X"E1",X"C9",X"31",X"00",X"48",X"08",X"3E",X"60",X"08",X"0E",X"1B",X"CD",X"DC",
+		X"04",X"0E",X"07",X"F7",X"CD",X"D7",X"0B",X"FD",X"21",X"80",X"40",X"CD",X"0B",X"0C",X"3A",X"8D",
+		X"42",X"FE",X"01",X"28",X"07",X"FD",X"21",X"80",X"41",X"CD",X"0B",X"0C",X"FD",X"21",X"80",X"40",
+		X"31",X"00",X"48",X"FD",X"7E",X"07",X"CD",X"09",X"00",X"CD",X"DF",X"0C",X"CD",X"97",X"0B",X"CD",
+		X"1E",X"06",X"CD",X"80",X"06",X"CD",X"81",X"0D",X"CD",X"F0",X"0C",X"FD",X"CB",X"04",X"76",X"C2",
+		X"8F",X"09",X"FD",X"CB",X"04",X"F6",X"06",X"03",X"CD",X"C8",X"0C",X"FD",X"35",X"05",X"CD",X"80",
+		X"06",X"21",X"CB",X"42",X"CB",X"F6",X"21",X"E4",X"53",X"22",X"91",X"42",X"21",X"8E",X"42",X"36",
+		X"00",X"21",X"5C",X"42",X"36",X"00",X"23",X"36",X"3A",X"23",X"36",X"05",X"23",X"36",X"20",X"21",
+		X"8F",X"42",X"36",X"11",X"3E",X"01",X"32",X"9D",X"42",X"3E",X"08",X"32",X"9B",X"42",X"CD",X"F3",
+		X"22",X"CD",X"A9",X"07",X"06",X"1C",X"CD",X"C0",X"0C",X"3A",X"8F",X"42",X"CB",X"47",X"20",X"EE",
+		X"3A",X"5C",X"42",X"FE",X"70",X"20",X"D8",X"21",X"8F",X"42",X"36",X"43",X"3E",X"08",X"32",X"9B",
+		X"42",X"CD",X"A8",X"22",X"CD",X"A9",X"07",X"06",X"1C",X"CD",X"C0",X"0C",X"3A",X"8F",X"42",X"CB",
+		X"47",X"20",X"EE",X"3A",X"5F",X"42",X"FE",X"80",X"20",X"DD",X"21",X"8F",X"42",X"36",X"47",X"3E",
+		X"08",X"32",X"9B",X"42",X"CD",X"A8",X"22",X"CD",X"A9",X"07",X"06",X"1C",X"CD",X"C0",X"0C",X"3A",
+		X"8F",X"42",X"CB",X"47",X"20",X"EE",X"3A",X"CD",X"42",X"CB",X"77",X"20",X"F9",X"18",X"0B",X"06",
+		X"02",X"CD",X"C8",X"0C",X"FD",X"35",X"05",X"CD",X"80",X"06",X"CD",X"2B",X"0C",X"CD",X"DF",X"0C",
+		X"21",X"5C",X"42",X"36",X"70",X"23",X"36",X"3A",X"23",X"36",X"05",X"23",X"36",X"90",X"06",X"01",
+		X"CD",X"C8",X"0C",X"21",X"00",X"19",X"22",X"7C",X"43",X"3E",X"46",X"32",X"7F",X"43",X"3E",X"03",
+		X"32",X"B7",X"42",X"3E",X"08",X"32",X"B9",X"42",X"08",X"32",X"BA",X"42",X"08",X"3E",X"02",X"32",
+		X"B8",X"42",X"32",X"CE",X"42",X"32",X"BE",X"42",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"AF",X"32",X"AB",X"42",X"32",X"BF",X"42",
+		X"3E",X"0E",X"32",X"BD",X"42",X"21",X"CB",X"42",X"CB",X"EE",X"CB",X"E6",X"CD",X"97",X"20",X"CD",
+		X"A9",X"07",X"CD",X"97",X"25",X"CD",X"DD",X"28",X"CD",X"B3",X"31",X"CD",X"97",X"35",X"CD",X"44",
+		X"0C",X"06",X"40",X"10",X"FE",X"3A",X"AB",X"42",X"A7",X"20",X"E1",X"3A",X"8E",X"42",X"CB",X"77",
+		X"20",X"4D",X"FD",X"7E",X"06",X"A7",X"20",X"D4",X"AF",X"32",X"BD",X"42",X"32",X"BE",X"42",X"CD",
+		X"64",X"0A",X"FD",X"CB",X"04",X"BE",X"FD",X"34",X"05",X"CD",X"D5",X"0C",X"CD",X"DF",X"0C",X"06",
+		X"01",X"CD",X"C8",X"0C",X"21",X"CB",X"42",X"CB",X"CE",X"CB",X"4E",X"20",X"FC",X"21",X"CD",X"42",
+		X"CB",X"4E",X"20",X"FC",X"06",X"02",X"CD",X"C8",X"0C",X"06",X"04",X"21",X"5F",X"42",X"CD",X"69",
+		X"0A",X"C3",X"D0",X"08",X"06",X"18",X"21",X"77",X"42",X"AF",X"77",X"2B",X"10",X"FC",X"C9",X"AF",
+		X"32",X"BE",X"42",X"32",X"BD",X"42",X"06",X"0C",X"CD",X"66",X"0A",X"CD",X"FD",X"20",X"06",X"01",
+		X"CD",X"C8",X"0C",X"CD",X"64",X"0A",X"CD",X"DF",X"0C",X"06",X"03",X"CD",X"C8",X"0C",X"CD",X"55",
+		X"08",X"06",X"01",X"CD",X"C0",X"0C",X"3A",X"8E",X"42",X"CB",X"47",X"28",X"F1",X"CD",X"10",X"2B",
+		X"CD",X"1F",X"2B",X"38",X"0D",X"CB",X"59",X"28",X"F7",X"DD",X"CB",X"00",X"C6",X"FD",X"35",X"06",
+		X"18",X"EE",X"AF",X"32",X"CE",X"42",X"FD",X"66",X"0B",X"FD",X"6E",X"0A",X"D7",X"CD",X"DF",X"0C",
+		X"06",X"06",X"CD",X"C8",X"0C",X"FD",X"7E",X"06",X"B7",X"CC",X"D5",X"0C",X"FD",X"7E",X"05",X"B7",
+		X"20",X"3D",X"21",X"CB",X"42",X"CB",X"FE",X"CB",X"7E",X"20",X"FC",X"21",X"CD",X"42",X"CB",X"7E",
+		X"20",X"FC",X"21",X"88",X"0B",X"D7",X"06",X"05",X"CD",X"C8",X"0C",X"3A",X"8D",X"42",X"FE",X"01",
+		X"28",X"09",X"CD",X"A6",X"0C",X"FD",X"7E",X"05",X"B7",X"20",X"3D",X"AF",X"32",X"8D",X"42",X"CD",
+		X"EC",X"00",X"CA",X"22",X"04",X"3A",X"88",X"42",X"B7",X"C2",X"22",X"04",X"C3",X"32",X"02",X"3A",
+		X"8D",X"42",X"FE",X"01",X"20",X"14",X"FD",X"7E",X"06",X"B7",X"20",X"07",X"FD",X"CB",X"04",X"BE",
+		X"C3",X"D0",X"08",X"FD",X"CB",X"04",X"FE",X"C3",X"D0",X"08",X"CD",X"A6",X"0C",X"FD",X"7E",X"05",
+		X"B7",X"20",X"05",X"CD",X"A6",X"0C",X"18",X"DE",X"CD",X"A6",X"0C",X"FD",X"7E",X"06",X"B7",X"20",
+		X"08",X"FD",X"CB",X"04",X"BE",X"0E",X"00",X"18",X"06",X"FD",X"CB",X"04",X"FE",X"0E",X"01",X"CD",
+		X"A6",X"0C",X"FD",X"7E",X"04",X"FD",X"CB",X"04",X"7E",X"28",X"02",X"CB",X"C9",X"06",X"1C",X"21",
+		X"46",X"50",X"DD",X"21",X"B2",X"43",X"C5",X"06",X"18",X"56",X"DD",X"5E",X"00",X"CB",X"41",X"28",
+		X"03",X"DD",X"72",X"00",X"CB",X"49",X"28",X"01",X"73",X"23",X"DD",X"23",X"10",X"EB",X"11",X"08",
+		X"00",X"19",X"C1",X"10",X"E1",X"C3",X"D0",X"08",X"51",X"51",X"40",X"52",X"45",X"56",X"4F",X"40",
+		X"40",X"45",X"4D",X"41",X"47",X"40",X"FF",X"FD",X"CB",X"04",X"7E",X"C0",X"21",X"3E",X"50",X"11",
+		X"08",X"00",X"06",X"1C",X"19",X"C5",X"06",X"18",X"36",X"50",X"23",X"10",X"FB",X"C1",X"10",X"F4",
+		X"DD",X"21",X"32",X"52",X"CD",X"3B",X"0E",X"FD",X"CB",X"04",X"76",X"C8",X"DD",X"21",X"06",X"52",
+		X"06",X"0C",X"DD",X"36",X"00",X"4B",X"DD",X"36",X"20",X"4A",X"DD",X"23",X"10",X"F4",X"DD",X"36",
+		X"00",X"10",X"DD",X"36",X"20",X"10",X"C9",X"21",X"07",X"42",X"01",X"02",X"03",X"CD",X"F5",X"0B",
+		X"01",X"00",X"08",X"CD",X"F5",X"0B",X"06",X"06",X"0C",X"CD",X"F5",X"0B",X"06",X"06",X"0C",X"CD",
+		X"F5",X"0B",X"06",X"04",X"0C",X"71",X"23",X"23",X"10",X"FB",X"C9",X"77",X"F5",X"23",X"3C",X"77",
+		X"11",X"1F",X"00",X"19",X"3C",X"77",X"23",X"3C",X"77",X"F1",X"C9",X"AF",X"FD",X"77",X"00",X"FD",
+		X"77",X"01",X"FD",X"77",X"02",X"FD",X"77",X"04",X"3C",X"FD",X"77",X"03",X"3A",X"86",X"42",X"CB",
+		X"3F",X"CB",X"3F",X"E6",X"01",X"C6",X"03",X"FD",X"77",X"05",X"C9",X"21",X"8F",X"42",X"36",X"10",
+		X"3E",X"01",X"32",X"9B",X"42",X"32",X"9D",X"42",X"21",X"32",X"52",X"22",X"91",X"42",X"21",X"8E",
+		X"42",X"36",X"00",X"C9",X"21",X"8E",X"42",X"CB",X"46",X"C0",X"CB",X"4E",X"C0",X"CB",X"76",X"C0",
+		X"21",X"B9",X"42",X"35",X"C0",X"36",X"08",X"DD",X"21",X"5C",X"42",X"DD",X"56",X"00",X"DD",X"5E",
+		X"03",X"CD",X"10",X"2B",X"CD",X"1F",X"2B",X"D8",X"CB",X"41",X"20",X"F8",X"CB",X"59",X"20",X"F4",
+		X"CB",X"51",X"20",X"F0",X"CD",X"B3",X"2B",X"7A",X"CD",X"9C",X"0C",X"30",X"E7",X"7B",X"41",X"CD",
+		X"9C",X"0C",X"30",X"E0",X"CD",X"5B",X"33",X"CD",X"8A",X"2B",X"3A",X"8E",X"42",X"CB",X"F7",X"32",
+		X"8E",X"42",X"3E",X"05",X"32",X"9B",X"42",X"AF",X"32",X"9D",X"42",X"C9",X"B8",X"30",X"03",X"67",
+		X"78",X"44",X"90",X"FE",X"05",X"C9",X"C5",X"FD",X"E5",X"C1",X"78",X"2F",X"C6",X"82",X"47",X"C5",
+		X"FD",X"E1",X"3A",X"86",X"42",X"CB",X"5F",X"20",X"05",X"08",X"2F",X"C6",X"C9",X"08",X"C1",X"C9",
+		X"0E",X"00",X"0D",X"20",X"FD",X"10",X"F9",X"C9",X"16",X"00",X"1E",X"00",X"1D",X"20",X"FD",X"15",
+		X"20",X"F8",X"10",X"F4",X"C9",X"FD",X"7E",X"03",X"C6",X"01",X"27",X"FD",X"77",X"03",X"C9",X"21",
+		X"CA",X"42",X"7E",X"E6",X"01",X"77",X"23",X"36",X"00",X"21",X"00",X"00",X"22",X"CC",X"42",X"C9",
+		X"FD",X"E5",X"E1",X"01",X"80",X"00",X"A7",X"ED",X"42",X"22",X"A9",X"42",X"E5",X"DD",X"E1",X"21",
+		X"1D",X"39",X"FD",X"CB",X"03",X"46",X"20",X"03",X"21",X"2F",X"39",X"06",X"03",X"FD",X"4E",X"04",
+		X"CB",X"79",X"28",X"19",X"DD",X"CB",X"00",X"46",X"28",X"13",X"E5",X"5E",X"23",X"56",X"AF",X"12",
+		X"13",X"12",X"13",X"12",X"13",X"12",X"E1",X"11",X"06",X"00",X"19",X"18",X"1B",X"DD",X"36",X"00",
+		X"00",X"5E",X"DD",X"73",X"01",X"23",X"56",X"DD",X"72",X"02",X"23",X"CD",X"66",X"0D",X"7E",X"DD",
+		X"77",X"05",X"23",X"7E",X"DD",X"77",X"06",X"23",X"11",X"07",X"00",X"DD",X"19",X"10",X"C1",X"FD",
+		X"CB",X"04",X"7E",X"C0",X"01",X"15",X"39",X"FD",X"CB",X"03",X"46",X"20",X"04",X"03",X"03",X"03",
+		X"03",X"CD",X"76",X"0D",X"18",X"10",X"7E",X"23",X"12",X"13",X"3E",X"2C",X"12",X"13",X"3E",X"04",
+		X"12",X"13",X"7E",X"23",X"12",X"C9",X"0A",X"6F",X"03",X"0A",X"67",X"03",X"3E",X"4C",X"C3",X"FB",
+		X"0B",X"FD",X"E5",X"E1",X"01",X"50",X"00",X"A7",X"ED",X"42",X"22",X"A0",X"42",X"22",X"A2",X"42",
+		X"E5",X"DD",X"E1",X"11",X"40",X"00",X"21",X"41",X"39",X"FD",X"7E",X"03",X"FE",X"09",X"38",X"0A",
+		X"CB",X"47",X"20",X"04",X"3E",X"08",X"18",X"02",X"3E",X"07",X"3D",X"28",X"03",X"19",X"18",X"FA",
+		X"7E",X"32",X"9E",X"42",X"23",X"7E",X"32",X"9F",X"42",X"23",X"7E",X"32",X"A4",X"42",X"23",X"7E",
+		X"32",X"A5",X"42",X"23",X"7E",X"32",X"A6",X"42",X"23",X"7E",X"FD",X"CB",X"04",X"7E",X"20",X"03",
+		X"FD",X"77",X"06",X"23",X"47",X"5E",X"DD",X"73",X"04",X"23",X"56",X"DD",X"72",X"05",X"23",X"FD",
+		X"CB",X"04",X"7E",X"20",X"0B",X"4E",X"DD",X"E5",X"D5",X"DD",X"E1",X"CD",X"37",X"0E",X"DD",X"E1",
+		X"23",X"5E",X"DD",X"73",X"06",X"23",X"56",X"DD",X"72",X"07",X"23",X"FD",X"CB",X"04",X"7E",X"28",
+		X"0B",X"DD",X"CB",X"00",X"46",X"28",X"05",X"23",X"23",X"23",X"18",X"1F",X"DD",X"E5",X"D5",X"DD",
+		X"E1",X"56",X"23",X"5E",X"23",X"7E",X"23",X"CD",X"95",X"0E",X"DD",X"E1",X"DD",X"77",X"00",X"DD",
+		X"36",X"01",X"00",X"DD",X"36",X"02",X"01",X"DD",X"36",X"08",X"00",X"11",X"0A",X"00",X"DD",X"19",
+		X"10",X"A3",X"DD",X"36",X"00",X"00",X"C9",X"CB",X"41",X"20",X"2D",X"DD",X"36",X"A0",X"46",X"DD",
+		X"36",X"A1",X"47",X"DD",X"36",X"40",X"44",X"DD",X"36",X"41",X"45",X"0E",X"48",X"DD",X"71",X"C0",
+		X"DD",X"71",X"E0",X"DD",X"71",X"00",X"DD",X"71",X"20",X"0E",X"49",X"DD",X"71",X"C1",X"DD",X"71",
+		X"E1",X"DD",X"71",X"01",X"DD",X"71",X"21",X"C9",X"DD",X"36",X"DE",X"46",X"DD",X"36",X"E3",X"47",
+		X"DD",X"36",X"FE",X"44",X"DD",X"36",X"03",X"45",X"0E",X"4B",X"DD",X"71",X"DF",X"DD",X"71",X"E0",
+		X"DD",X"71",X"E1",X"DD",X"71",X"E2",X"0E",X"4A",X"DD",X"71",X"FF",X"DD",X"71",X"00",X"DD",X"71",
+		X"01",X"DD",X"71",X"02",X"C9",X"DD",X"72",X"00",X"DD",X"73",X"03",X"16",X"17",X"1E",X"07",X"CB",
+		X"4F",X"28",X"04",X"16",X"15",X"1E",X"06",X"DD",X"72",X"01",X"DD",X"73",X"02",X"C9",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"0A",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"09",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"A8",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"03",X"00",X"18",X"09",X"04",X"10",X"10",X"10",X"05",X"08",X"F8",X"02",X"32",X"87",X"00",X"0D",
+		X"01",X"1B",X"02",X"7F",X"00",X"FE",X"00",X"FC",X"01",X"6B",X"00",X"D6",X"00",X"AC",X"01",X"55",
+		X"00",X"AA",X"00",X"53",X"01",X"47",X"00",X"8F",X"00",X"1D",X"01",X"55",X"00",X"AA",X"00",X"53",
+		X"01",X"6B",X"00",X"D6",X"00",X"AC",X"01",X"7F",X"00",X"FE",X"00",X"FC",X"01",X"00",X"00",X"AF",
+		X"CD",X"14",X"95",X"DD",X"7E",X"00",X"CD",X"14",X"95",X"82",X"57",X"23",X"DD",X"23",X"0B",X"1D",
+		X"20",X"F1",X"AF",X"92",X"CD",X"14",X"95",X"18",X"C2",X"3E",X"3A",X"CD",X"31",X"95",X"AF",X"1E",
+		X"03",X"CD",X"14",X"95",X"1D",X"20",X"FA",X"3C",X"CD",X"14",X"95",X"CD",X"4E",X"95",X"3E",X"FF",
+		X"CD",X"14",X"95",X"CD",X"4E",X"95",X"3E",X"0D",X"CD",X"14",X"95",X"CD",X"4E",X"95",X"3E",X"0A",
+		X"03",X"00",X"18",X"09",X"04",X"10",X"10",X"10",X"05",X"08",X"F8",X"02",X"42",X"87",X"00",X"0D",
+		X"01",X"1B",X"02",X"7F",X"00",X"FE",X"00",X"FC",X"01",X"6B",X"00",X"D6",X"00",X"AC",X"01",X"55",
+		X"00",X"AA",X"00",X"53",X"01",X"47",X"00",X"8F",X"00",X"1D",X"01",X"00",X"00",X"00",X"00",X"28",
+		X"FA",X"DB",X"20",X"C9",X"FE",X"0A",X"30",X"03",X"F6",X"30",X"C9",X"C6",X"37",X"C9",X"21",X"00",
+		X"80",X"2B",X"7C",X"B5",X"20",X"FB",X"C9",X"DD",X"21",X"00",X"A0",X"01",X"00",X"10",X"3A",X"F5",
+		X"8F",X"FE",X"04",X"28",X"03",X"01",X"00",X"08",X"C9",X"3A",X"07",X"42",X"FE",X"00",X"28",X"25",
+		X"FE",X"01",X"C2",X"CB",X"26",X"21",X"08",X"42",X"7E",X"B7",X"28",X"04",X"36",X"00",X"18",X"15",
+		X"3E",X"01",X"77",X"32",X"05",X"42",X"3E",X"03",X"32",X"06",X"42",X"C3",X"87",X"00",X"21",X"49",
+		X"03",X"00",X"18",X"09",X"04",X"01",X"10",X"10",X"05",X"00",X"FC",X"02",X"44",X"6B",X"00",X"D6",
+		X"00",X"AC",X"01",X"04",X"01",X"01",X"01",X"47",X"00",X"8F",X"00",X"1D",X"01",X"04",X"10",X"10",
+		X"10",X"47",X"00",X"8F",X"00",X"1D",X"01",X"6B",X"00",X"D6",X"00",X"AC",X"01",X"47",X"00",X"8F",
+		X"00",X"1D",X"01",X"71",X"00",X"E2",X"00",X"C5",X"01",X"04",X"01",X"01",X"01",X"39",X"00",X"71",
+		X"00",X"E2",X"00",X"04",X"10",X"10",X"10",X"39",X"00",X"71",X"00",X"E2",X"00",X"02",X"02",X"B4",
+		X"00",X"68",X"01",X"CF",X"02",X"6B",X"00",X"D6",X"00",X"AC",X"01",X"02",X"06",X"32",X"00",X"39",
+		X"00",X"71",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"8F",X"00",X"1D",X"01",X"20",X"32",X"01",
+		X"01",X"01",X"01",X"02",X"06",X"6B",X"00",X"D6",X"00",X"32",X"3A",X"00",X"00",X"6B",X"61",X"76",
+		X"03",X"00",X"18",X"09",X"04",X"10",X"10",X"10",X"05",X"08",X"F8",X"02",X"11",X"AA",X"00",X"97",
+		X"00",X"8F",X"00",X"B4",X"00",X"A0",X"00",X"97",X"00",X"BE",X"00",X"AA",X"00",X"A0",X"00",X"CA",
+		X"00",X"B4",X"00",X"AA",X"00",X"D6",X"00",X"BE",X"00",X"B4",X"00",X"E2",X"00",X"CA",X"00",X"BE",
+		X"00",X"F0",X"00",X"D6",X"00",X"CA",X"00",X"FE",X"00",X"E2",X"00",X"D6",X"00",X"0D",X"01",X"F0",
+		X"00",X"E2",X"00",X"1D",X"01",X"FE",X"00",X"F0",X"00",X"2E",X"01",X"0D",X"01",X"FE",X"00",X"00",
+		X"00",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"45",X"4E",
+		X"44",X"0D",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"03",X"00",X"0A",X"09",X"04",X"10",X"10",X"10",X"05",X"00",X"F0",X"02",X"45",X"AC",X"01",X"7D",
+		X"01",X"53",X"01",X"00",X"00",X"00",X"00",X"AA",X"00",X"00",X"00",X"B4",X"00",X"B4",X"00",X"D6",
+		X"00",X"D6",X"00",X"D6",X"00",X"00",X"00",X"20",X"20",X"4E",X"4D",X"49",X"52",X"45",X"54",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"3B",X"4A",X"6D",X"70",X"20",X"74",X"6F",
+		X"20",X"4D",X"61",X"69",X"6E",X"20",X"4E",X"6D",X"69",X"20",X"50",X"47",X"2E",X"00",X"6F",X"72",
+		X"6B",X"20",X"41",X"64",X"64",X"72",X"65",X"73",X"00",X"41",X"64",X"64",X"72",X"65",X"73",X"00",
+		X"45",X"52",X"00",X"00",X"DE",X"20",X"B5",X"DD",X"CC",X"DF",X"29",X"0D",X"09",X"44",X"42",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"34",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"3B",X"4E",X"6F",
+		X"69",X"73",X"65",X"20",X"34",X"0D",X"09",X"44",X"42",X"20",X"20",X"20",X"20",X"20",X"20",X"30",
+		X"42",X"38",X"48",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
+		X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"3B",X"4D",X"69",X"78",X"65",X"72",X"20",X"33",X"63",
+		X"68",X"20",X"54",X"75",X"6E",X"65",X"20",X"49",X"2F",X"4F",X"20",X"3D",X"20",X"41",X"28",X"49",
+		X"4E",X"29",X"00",X"00",X"27",X"02",X"81",X"80",X"62",X"D0",X"00",X"00",X"62",X"01",X"C5",X"00",
+		X"01",X"01",X"62",X"CF",X"10",X"12",X"66",X"E7",X"01",X"01",X"00",X"00",X"27",X"02",X"00",X"00",
+		X"27",X"02",X"81",X"80",X"BC",X"D1",X"00",X"00",X"62",X"01",X"C5",X"00",X"00",X"00",X"00",X"00",
+		X"03",X"00",X"30",X"08",X"04",X"10",X"10",X"10",X"05",X"00",X"F0",X"02",X"43",X"1D",X"01",X"53",
+		X"01",X"AC",X"01",X"00",X"00",X"AC",X"01",X"D6",X"00",X"50",X"00",X"A0",X"01",X"A0",X"00",X"71",
+		X"00",X"C5",X"01",X"E2",X"00",X"47",X"00",X"1D",X"01",X"8F",X"00",X"6B",X"00",X"AC",X"01",X"D6",
+		X"00",X"00",X"00",X"41",X"4D",X"45",X"4E",X"44",X"FF",X"43",X"00",X"00",X"49",X"4E",X"41",X"43",
+		X"54",X"56",X"00",X"48",X"00",X"00",X"54",X"56",X"44",X"20",X"20",X"20",X"00",X"50",X"00",X"00",
+		X"50",X"4F",X"52",X"54",X"31",X"20",X"00",X"60",X"00",X"00",X"50",X"4F",X"52",X"54",X"32",X"20",
+		X"00",X"68",X"00",X"00",X"50",X"4F",X"52",X"54",X"33",X"20",X"00",X"70",X"00",X"00",X"43",X"55",
+		X"50",X"20",X"20",X"20",X"80",X"40",X"00",X"00",X"43",X"44",X"57",X"20",X"20",X"20",X"C0",X"40",
+		X"00",X"00",X"4D",X"49",X"53",X"53",X"20",X"20",X"60",X"68",X"00",X"00",X"4E",X"4D",X"49",X"20",
+		X"20",X"20",X"01",X"70",X"00",X"00",X"4C",X"4F",X"43",X"41",X"54",X"45",X"06",X"70",X"00",X"00",
+		X"52",X"45",X"53",X"45",X"54",X"20",X"00",X"78",X"00",X"00",X"50",X"53",X"55",X"44",X"20",X"20",
+		X"06",X"00",X"00",X"00",X"50",X"53",X"55",X"44",X"32",X"20",X"03",X"00",X"00",X"00",X"50",X"53",
+		X"4C",X"46",X"20",X"20",X"06",X"00",X"00",X"00",X"50",X"53",X"4C",X"46",X"32",X"20",X"03",X"00",
+		X"00",X"00",X"49",X"53",X"55",X"44",X"20",X"20",X"02",X"00",X"00",X"00",X"4F",X"53",X"55",X"44",
+		X"20",X"20",X"06",X"00",X"00",X"00",X"49",X"53",X"42",X"4B",X"20",X"20",X"08",X"00",X"00",X"00",
+		X"46",X"43",X"45",X"58",X"20",X"20",X"14",X"00",X"00",X"00",X"43",X"53",X"44",X"4C",X"59",X"20",
+		X"03",X"00",X"0A",X"09",X"04",X"10",X"10",X"10",X"05",X"00",X"F8",X"02",X"21",X"D6",X"00",X"AC",
+		X"01",X"57",X"03",X"04",X"01",X"01",X"01",X"53",X"01",X"00",X"00",X"4C",X"55",X"04",X"10",X"10",
+		X"10",X"D6",X"00",X"AC",X"01",X"57",X"03",X"8F",X"00",X"1D",X"01",X"3B",X"02",X"00",X"00",X"49",
+		X"4D",X"45",X"0A",X"00",X"00",X"00",X"50",X"4C",X"41",X"59",X"31",X"20",X"00",X"40",X"00",X"00",
+		X"50",X"4C",X"41",X"59",X"32",X"20",X"00",X"41",X"00",X"00",X"53",X"43",X"52",X"45",X"45",X"4E",
+		X"03",X"00",X"00",X"00",X"53",X"52",X"56",X"46",X"4C",X"47",X"04",X"00",X"00",X"00",X"50",X"41",
+		X"43",X"4B",X"4D",X"4E",X"05",X"00",X"00",X"00",X"54",X"45",X"4E",X"53",X"4F",X"20",X"06",X"00",
+		X"00",X"00",X"42",X"4F",X"4E",X"55",X"53",X"20",X"07",X"00",X"00",X"00",X"42",X"4E",X"53",X"50",
+		X"4F",X"54",X"09",X"00",X"00",X"00",X"54",X"56",X"20",X"20",X"20",X"20",X"77",X"00",X"00",X"00",
+		X"50",X"41",X"43",X"50",X"4F",X"54",X"78",X"00",X"00",X"00",X"54",X"45",X"4E",X"44",X"54",X"20",
+		X"7A",X"00",X"00",X"00",X"55",X"50",X"41",X"44",X"52",X"20",X"7C",X"00",X"00",X"00",X"53",X"43",
+		X"52",X"41",X"44",X"52",X"7E",X"00",X"00",X"00",X"53",X"50",X"45",X"45",X"44",X"20",X"80",X"41",
+		X"00",X"00",X"4F",X"49",X"4B",X"41",X"4B",X"45",X"98",X"41",X"00",X"00",X"42",X"4E",X"53",X"41",
+		X"44",X"44",X"DA",X"41",X"00",X"00",X"48",X"49",X"53",X"43",X"4F",X"52",X"00",X"42",X"00",X"00",
+		X"50",X"4C",X"59",X"4E",X"55",X"4D",X"03",X"42",X"00",X"00",X"43",X"52",X"45",X"44",X"49",X"54",
+		X"04",X"42",X"00",X"00",X"43",X"4F",X"49",X"4E",X"54",X"4D",X"05",X"42",X"00",X"00",X"43",X"43",
+		X"03",X"00",X"0A",X"09",X"04",X"10",X"10",X"10",X"05",X"00",X"F8",X"02",X"11",X"AC",X"01",X"C5",
+		X"01",X"FC",X"01",X"94",X"01",X"AC",X"01",X"E0",X"01",X"7D",X"01",X"94",X"01",X"C5",X"01",X"68",
+		X"01",X"7D",X"01",X"AC",X"01",X"53",X"01",X"68",X"01",X"94",X"01",X"40",X"01",X"53",X"01",X"7D",
+		X"01",X"2E",X"01",X"40",X"01",X"68",X"01",X"1D",X"01",X"2E",X"01",X"53",X"01",X"0D",X"01",X"1D",
+		X"01",X"40",X"01",X"FE",X"00",X"0D",X"01",X"2E",X"01",X"F0",X"00",X"FE",X"00",X"1D",X"01",X"E2",
+		X"00",X"F0",X"00",X"0D",X"01",X"D6",X"00",X"E2",X"00",X"FE",X"00",X"CA",X"00",X"D6",X"00",X"F0",
+		X"00",X"BE",X"00",X"CA",X"00",X"E2",X"00",X"B4",X"00",X"BE",X"00",X"D6",X"00",X"AA",X"00",X"B4",
+		X"00",X"CA",X"00",X"A0",X"00",X"AA",X"00",X"BE",X"00",X"97",X"00",X"A0",X"00",X"B4",X"00",X"8F",
+		X"00",X"97",X"00",X"AA",X"00",X"00",X"00",X"00",X"02",X"FE",X"00",X"FC",X"01",X"FC",X"01",X"0D",
+		X"01",X"1B",X"02",X"1B",X"02",X"FE",X"00",X"FC",X"01",X"FC",X"01",X"F0",X"00",X"E0",X"01",X"E0",
+		X"01",X"E2",X"00",X"C5",X"01",X"C5",X"01",X"F0",X"00",X"E0",X"01",X"E0",X"01",X"E2",X"00",X"C5",
+		X"01",X"C5",X"01",X"02",X"08",X"D6",X"00",X"AC",X"01",X"AC",X"01",X"00",X"00",X"50",X"41",X"43",
+		X"4B",X"20",X"1A",X"42",X"00",X"00",X"50",X"4F",X"57",X"45",X"52",X"31",X"1B",X"42",X"00",X"00",
+		X"50",X"4F",X"57",X"45",X"52",X"32",X"1C",X"42",X"00",X"00",X"50",X"4F",X"57",X"45",X"52",X"33",
+		X"1D",X"42",X"00",X"00",X"54",X"49",X"4D",X"45",X"52",X"33",X"1E",X"42",X"00",X"00",X"54",X"49",
+		X"4D",X"45",X"52",X"34",X"1F",X"42",X"00",X"00",X"4F",X"49",X"4B",X"41",X"54",X"4D",X"21",X"42",
+		X"03",X"00",X"0A",X"09",X"04",X"10",X"10",X"01",X"05",X"00",X"F8",X"02",X"12",X"1B",X"02",X"35",
+		X"04",X"3B",X"02",X"FC",X"01",X"F9",X"03",X"5D",X"02",X"FC",X"01",X"F9",X"03",X"3B",X"02",X"E0",
+		X"01",X"C0",X"03",X"1B",X"02",X"E0",X"01",X"C0",X"03",X"FC",X"01",X"C5",X"01",X"8A",X"03",X"1B",
+		X"02",X"C5",X"01",X"8A",X"03",X"FC",X"01",X"02",X"04",X"AC",X"01",X"57",X"03",X"02",X"04",X"00",
+		X"00",X"C5",X"01",X"C5",X"01",X"02",X"02",X"F0",X"00",X"E0",X"01",X"E0",X"01",X"FE",X"00",X"FC",
+		X"01",X"FC",X"01",X"02",X"06",X"FE",X"00",X"FC",X"01",X"FC",X"01",X"02",X"02",X"FE",X"00",X"FC",
+		X"01",X"FC",X"01",X"0D",X"01",X"1B",X"02",X"1B",X"02",X"FE",X"00",X"FC",X"01",X"FC",X"01",X"F0",
+		X"00",X"E0",X"01",X"E0",X"01",X"E2",X"00",X"C5",X"01",X"C5",X"01",X"F0",X"00",X"01",X"E0",X"01",
+		X"03",X"00",X"18",X"09",X"04",X"10",X"10",X"01",X"05",X"00",X"F8",X"02",X"51",X"AA",X"00",X"53",
+		X"01",X"AA",X"00",X"A0",X"00",X"40",X"01",X"AA",X"00",X"97",X"00",X"2E",X"01",X"AA",X"00",X"02",
+		X"02",X"04",X"10",X"10",X"10",X"8F",X"00",X"1D",X"01",X"EB",X"08",X"04",X"10",X"10",X"01",X"AA",
+		X"00",X"53",X"01",X"AA",X"00",X"04",X"10",X"10",X"10",X"A0",X"00",X"40",X"01",X"6B",X"08",X"04",
+		X"10",X"10",X"01",X"BE",X"00",X"7D",X"01",X"AA",X"00",X"04",X"10",X"10",X"10",X"AA",X"00",X"53",
+		X"01",X"F2",X"07",X"04",X"10",X"10",X"01",X"D6",X"00",X"AC",X"01",X"AA",X"00",X"04",X"10",X"10",
+		X"10",X"BE",X"00",X"7D",X"01",X"14",X"07",X"04",X"10",X"10",X"01",X"E2",X"00",X"C5",X"01",X"AA",
+		X"00",X"04",X"10",X"10",X"10",X"04",X"10",X"10",X"10",X"D6",X"00",X"AC",X"01",X"AE",X"00",X"04",
+		X"01",X"01",X"01",X"AA",X"00",X"AA",X"01",X"AA",X"02",X"04",X"10",X"10",X"01",X"6B",X"00",X"D6",
+		X"00",X"AA",X"00",X"04",X"10",X"10",X"10",X"D6",X"00",X"AC",X"01",X"AE",X"06",X"00",X"00",X"02",
+		X"02",X"04",X"10",X"10",X"10",X"8F",X"00",X"1D",X"01",X"EB",X"08",X"04",X"10",X"10",X"01",X"AA",
+		X"00",X"53",X"01",X"AA",X"00",X"04",X"10",X"10",X"10",X"A0",X"00",X"40",X"01",X"6B",X"08",X"04",
+		X"10",X"10",X"01",X"BE",X"00",X"7D",X"01",X"AA",X"00",X"04",X"10",X"10",X"10",X"AA",X"00",X"53",
+		X"01",X"F2",X"07",X"04",X"10",X"10",X"01",X"D6",X"00",X"AC",X"01",X"AA",X"00",X"04",X"10",X"10",
+		X"10",X"BE",X"00",X"7D",X"01",X"14",X"07",X"04",X"10",X"10",X"01",X"E2",X"00",X"C5",X"01",X"AA",
+		X"00",X"04",X"10",X"10",X"10",X"04",X"10",X"10",X"10",X"D6",X"00",X"AC",X"01",X"AE",X"00",X"04",
+		X"01",X"01",X"01",X"AA",X"00",X"AA",X"01",X"AA",X"02",X"04",X"10",X"10",X"01",X"6B",X"00",X"D6",
+		X"00",X"AA",X"00",X"04",X"10",X"10",X"10",X"D6",X"00",X"AC",X"01",X"AE",X"06",X"00",X"FF",X"53",
+		X"01",X"02",X"06",X"D6",X"00",X"1D",X"01",X"53",X"01",X"AA",X"00",X"D6",X"00",X"1D",X"01",X"02",
+		X"04",X"AA",X"00",X"D6",X"00",X"1D",X"01",X"AA",X"00",X"D6",X"00",X"1D",X"01",X"02",X"06",X"AA",
+		X"00",X"D6",X"00",X"1D",X"01",X"8F",X"00",X"AA",X"00",X"D6",X"00",X"8F",X"00",X"AA",X"00",X"D6",
+		X"00",X"8F",X"00",X"AA",X"00",X"D6",X"00",X"02",X"08",X"6B",X"00",X"8F",X"00",X"AA",X"00",X"00",
+		X"00",X"00",X"4C",X"43",X"54",X"20",X"20",X"20",X"09",X"00",X"00",X"00",X"4F",X"55",X"54",X"53",
+		X"54",X"52",X"10",X"00",X"00",X"00",X"4F",X"55",X"54",X"53",X"54",X"31",X"17",X"00",X"00",X"00",
+		X"03",X"00",X"20",X"09",X"04",X"10",X"10",X"10",X"05",X"00",X"F8",X"02",X"42",X"4C",X"00",X"5A",
+		X"00",X"7F",X"00",X"50",X"00",X"5F",X"00",X"87",X"00",X"55",X"00",X"65",X"00",X"8F",X"00",X"5A",
+		X"00",X"6B",X"00",X"97",X"00",X"5F",X"00",X"71",X"00",X"A0",X"00",X"65",X"00",X"78",X"00",X"AA",
+		X"00",X"6B",X"00",X"7F",X"00",X"B4",X"00",X"02",X"06",X"40",X"00",X"5A",X"00",X"6B",X"00",X"00",
+		X"00",X"20",X"5E",X"00",X"00",X"00",X"4E",X"4D",X"49",X"30",X"31",X"20",X"78",X"00",X"00",X"00",
+		X"4E",X"4D",X"49",X"52",X"45",X"54",X"87",X"00",X"00",X"00",X"4E",X"4D",X"49",X"30",X"32",X"20",
+		X"9D",X"00",X"00",X"00",X"4D",X"41",X"49",X"4E",X"20",X"20",X"AF",X"00",X"00",X"00",X"4D",X"41",
+		X"49",X"4E",X"31",X"20",X"C7",X"00",X"00",X"00",X"4D",X"41",X"49",X"4E",X"32",X"20",X"D2",X"00",
+		X"02",X"24",X"03",X"00",X"05",X"04",X"04",X"0F",X"0F",X"0F",X"05",X"04",X"B8",X"00",X"00",X"4E",
+		X"35",X"20",X"FE",X"00",X"00",X"00",X"4D",X"41",X"49",X"4E",X"35",X"31",X"06",X"01",X"00",X"00",
+		X"4D",X"41",X"49",X"4E",X"36",X"20",X"11",X"01",X"00",X"00",X"4D",X"41",X"49",X"4E",X"37",X"20",
+		X"02",X"24",X"03",X"00",X"05",X"04",X"04",X"0F",X"0F",X"0F",X"05",X"04",X"B8",X"00",X"00",X"45",
+		X"41",X"44",X"32",X"20",X"98",X"01",X"00",X"00",X"44",X"45",X"41",X"44",X"33",X"20",X"9E",X"01",
+		X"00",X"00",X"44",X"45",X"41",X"44",X"33",X"30",X"AE",X"01",X"00",X"00",X"44",X"45",X"41",X"44",
+		X"02",X"24",X"03",X"00",X"05",X"04",X"04",X"0F",X"0F",X"0F",X"05",X"04",X"B8",X"00",X"00",X"00",
+		X"44",X"45",X"4D",X"4F",X"20",X"20",X"F8",X"01",X"00",X"00",X"4D",X"49",X"53",X"43",X"4C",X"52",
+		X"03",X"00",X"09",X"09",X"04",X"10",X"10",X"10",X"05",X"08",X"F8",X"02",X"02",X"97",X"00",X"2E",
+		X"01",X"AE",X"06",X"8F",X"00",X"1D",X"01",X"75",X"04",X"8F",X"00",X"1D",X"01",X"AE",X"06",X"8F",
+		X"00",X"1D",X"01",X"75",X"04",X"04",X"01",X"01",X"10",X"AA",X"00",X"AA",X"01",X"14",X"07",X"04",
+		X"10",X"10",X"10",X"8F",X"00",X"1D",X"01",X"75",X"04",X"8F",X"00",X"1D",X"01",X"14",X"07",X"8F",
+		X"00",X"1D",X"01",X"75",X"04",X"8F",X"00",X"1D",X"01",X"80",X"07",X"8F",X"00",X"1D",X"01",X"75",
+		X"04",X"8F",X"00",X"1D",X"01",X"80",X"07",X"8F",X"00",X"1D",X"01",X"75",X"04",X"04",X"01",X"01",
+		X"10",X"AA",X"00",X"AA",X"01",X"F2",X"07",X"04",X"10",X"10",X"10",X"8F",X"00",X"1D",X"01",X"75",
+		X"04",X"8F",X"00",X"1D",X"01",X"F2",X"07",X"8F",X"00",X"1D",X"01",X"75",X"04",X"AA",X"00",X"53",
+		X"01",X"6B",X"08",X"04",X"01",X"01",X"10",X"AA",X"00",X"AA",X"01",X"06",X"05",X"04",X"10",X"10",
+		X"10",X"BE",X"00",X"7D",X"01",X"6B",X"08",X"AA",X"00",X"53",X"01",X"06",X"05",X"04",X"01",X"01",
+		X"10",X"AA",X"00",X"AA",X"01",X"6B",X"08",X"04",X"10",X"10",X"10",X"BE",X"00",X"7D",X"01",X"06",
+		X"05",X"AA",X"00",X"53",X"01",X"6B",X"08",X"BE",X"00",X"7D",X"01",X"06",X"05",X"AA",X"00",X"53",
+		X"01",X"EB",X"08",X"04",X"01",X"01",X"10",X"AA",X"00",X"AA",X"01",X"06",X"05",X"AA",X"00",X"AA",
+		X"01",X"EB",X"08",X"AA",X"00",X"AA",X"01",X"06",X"05",X"04",X"10",X"10",X"10",X"BE",X"00",X"7D",
+		X"01",X"F2",X"07",X"04",X"01",X"01",X"10",X"AA",X"00",X"AA",X"01",X"06",X"05",X"AA",X"00",X"AA",
+		X"01",X"F2",X"07",X"AA",X"00",X"AA",X"01",X"06",X"05",X"04",X"10",X"10",X"10",X"B4",X"00",X"68",
+		X"01",X"AE",X"06",X"AA",X"00",X"53",X"01",X"75",X"04",X"AA",X"00",X"53",X"01",X"AE",X"06",X"AA",
+		X"00",X"53",X"01",X"75",X"04",X"04",X"01",X"01",X"10",X"AA",X"00",X"AA",X"01",X"14",X"07",X"04",
+		X"10",X"10",X"10",X"AA",X"00",X"53",X"01",X"75",X"04",X"AA",X"00",X"53",X"01",X"14",X"07",X"AA",
+		X"00",X"53",X"01",X"75",X"04",X"AA",X"00",X"53",X"01",X"80",X"07",X"AA",X"00",X"53",X"01",X"75",
+		X"04",X"AA",X"00",X"53",X"01",X"80",X"07",X"AA",X"00",X"53",X"01",X"75",X"04",X"04",X"01",X"01",
+		X"10",X"AA",X"00",X"AA",X"01",X"F2",X"07",X"04",X"10",X"10",X"10",X"AA",X"00",X"53",X"01",X"75",
+		X"04",X"AA",X"00",X"53",X"01",X"F2",X"07",X"AA",X"00",X"53",X"01",X"75",X"04",X"AA",X"00",X"53",
+		X"01",X"6B",X"08",X"04",X"01",X"01",X"10",X"AA",X"00",X"AA",X"01",X"06",X"05",X"04",X"10",X"10",
+		X"10",X"BE",X"00",X"7D",X"01",X"6B",X"08",X"AA",X"00",X"53",X"01",X"06",X"05",X"04",X"01",X"01",
+		X"10",X"AA",X"00",X"AA",X"01",X"6B",X"08",X"04",X"10",X"10",X"10",X"BE",X"00",X"7D",X"01",X"06",
+		X"05",X"AA",X"00",X"53",X"01",X"6B",X"08",X"BE",X"00",X"7D",X"01",X"06",X"05",X"8F",X"00",X"1D",
+		X"01",X"EB",X"08",X"04",X"01",X"10",X"10",X"AA",X"00",X"81",X"02",X"06",X"05",X"AA",X"00",X"75",
+		X"04",X"EB",X"08",X"AA",X"00",X"81",X"02",X"06",X"05",X"AA",X"00",X"35",X"04",X"6B",X"08",X"AA",
+		X"00",X"81",X"02",X"06",X"05",X"AA",X"00",X"F9",X"03",X"F2",X"07",X"AA",X"00",X"81",X"02",X"06",
+		X"05",X"04",X"10",X"10",X"10",X"00",X"FF",X"AA",X"00",X"AA",X"01",X"06",X"05",X"AA",X"00",X"AA",
+		X"01",X"F2",X"07",X"AA",X"00",X"AA",X"01",X"06",X"05",X"04",X"10",X"10",X"10",X"B4",X"00",X"68",
+		X"01",X"AE",X"06",X"AA",X"00",X"53",X"01",X"75",X"04",X"AA",X"00",X"53",X"01",X"AE",X"06",X"AA",
+		X"00",X"53",X"01",X"75",X"04",X"04",X"01",X"01",X"10",X"AA",X"00",X"AA",X"01",X"14",X"07",X"04",
+		X"10",X"10",X"10",X"AA",X"00",X"53",X"01",X"75",X"04",X"AA",X"00",X"53",X"01",X"14",X"07",X"AA",
+		X"00",X"53",X"01",X"75",X"04",X"AA",X"00",X"53",X"01",X"80",X"07",X"AA",X"00",X"53",X"01",X"75",
+		X"04",X"AA",X"00",X"53",X"01",X"80",X"07",X"AA",X"00",X"53",X"01",X"75",X"04",X"04",X"01",X"01",
+		X"10",X"AA",X"00",X"AA",X"01",X"F2",X"07",X"04",X"10",X"10",X"10",X"AA",X"00",X"53",X"01",X"75",
+		X"04",X"AA",X"00",X"53",X"01",X"F2",X"07",X"AA",X"00",X"53",X"01",X"75",X"04",X"AA",X"00",X"53",
+		X"01",X"6B",X"08",X"04",X"01",X"01",X"10",X"AA",X"00",X"AA",X"01",X"06",X"05",X"04",X"10",X"10",
+		X"03",X"00",X"18",X"09",X"04",X"08",X"08",X"10",X"05",X"08",X"F8",X"02",X"52",X"97",X"00",X"2E",
+		X"01",X"5D",X"02",X"A0",X"00",X"40",X"01",X"81",X"02",X"97",X"00",X"2E",X"01",X"5D",X"02",X"A0",
+		X"00",X"40",X"01",X"81",X"02",X"2E",X"01",X"5D",X"02",X"B9",X"04",X"40",X"01",X"81",X"02",X"06",
+		X"05",X"2E",X"01",X"5D",X"02",X"B9",X"04",X"40",X"01",X"81",X"02",X"06",X"05",X"00",X"FF",X"75",
+		X"04",X"EB",X"08",X"AA",X"00",X"81",X"02",X"06",X"05",X"AA",X"00",X"35",X"04",X"6B",X"08",X"AA",
+		X"00",X"81",X"02",X"06",X"05",X"AA",X"00",X"F9",X"03",X"F2",X"07",X"AA",X"00",X"81",X"02",X"06",
+		X"05",X"04",X"10",X"10",X"10",X"00",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"03",X"00",X"09",X"09",X"04",X"10",X"10",X"10",X"05",X"08",X"F8",X"02",X"42",X"97",X"00",X"2E",
+		X"01",X"5D",X"02",X"8F",X"00",X"1D",X"01",X"3B",X"02",X"8F",X"00",X"1D",X"01",X"3B",X"02",X"8F",
+		X"00",X"1D",X"01",X"3B",X"02",X"2E",X"01",X"5D",X"02",X"B9",X"04",X"1D",X"01",X"3B",X"02",X"75",
+		X"04",X"1D",X"01",X"3B",X"02",X"75",X"04",X"1D",X"01",X"3B",X"02",X"75",X"04",X"5D",X"02",X"B9",
+		X"04",X"73",X"09",X"3B",X"02",X"75",X"04",X"EB",X"08",X"3B",X"02",X"75",X"04",X"EB",X"08",X"3B",
+		X"02",X"75",X"04",X"EB",X"08",X"04",X"01",X"01",X"01",X"3B",X"02",X"75",X"04",X"EB",X"08",X"8F",
+		X"00",X"1D",X"01",X"75",X"04",X"8F",X"00",X"1D",X"01",X"F9",X"03",X"8F",X"00",X"1D",X"01",X"8A",
+		X"03",X"8F",X"00",X"1D",X"01",X"57",X"03",X"04",X"01",X"01",X"10",X"8F",X"00",X"1D",X"01",X"75",
+		X"04",X"04",X"10",X"10",X"10",X"AA",X"00",X"53",X"01",X"57",X"03",X"04",X"01",X"01",X"10",X"AA",
+		X"00",X"53",X"01",X"75",X"04",X"04",X"10",X"10",X"10",X"8F",X"00",X"1D",X"01",X"57",X"03",X"AA",
+		X"00",X"53",X"01",X"75",X"04",X"04",X"01",X"01",X"10",X"AA",X"00",X"53",X"01",X"57",X"03",X"04",
+		X"10",X"10",X"10",X"8F",X"00",X"1D",X"01",X"75",X"04",X"7F",X"00",X"FE",X"00",X"57",X"03",X"AA",
+		X"00",X"53",X"01",X"75",X"04",X"AA",X"00",X"53",X"01",X"57",X"03",X"AA",X"00",X"53",X"01",X"75",
+		X"04",X"04",X"01",X"01",X"10",X"AA",X"00",X"AA",X"00",X"57",X"03",X"04",X"10",X"10",X"10",X"BE",
+		X"04",X"7D",X"01",X"75",X"04",X"D6",X"00",X"AC",X"01",X"57",X"03",X"04",X"01",X"01",X"10",X"D6",
+		X"00",X"AC",X"01",X"75",X"04",X"04",X"10",X"10",X"10",X"CA",X"00",X"94",X"01",X"C0",X"03",X"04",
+		X"01",X"01",X"10",X"94",X"01",X"E0",X"01",X"75",X"04",X"04",X"10",X"10",X"10",X"1D",X"01",X"3B",
+		X"02",X"C0",X"03",X"04",X"01",X"01",X"10",X"1D",X"01",X"3B",X"02",X"75",X"04",X"04",X"10",X"10",
+		X"10",X"D6",X"00",X"AC",X"01",X"C0",X"03",X"1D",X"01",X"3B",X"02",X"75",X"04",X"F0",X"00",X"E0",
+		X"01",X"C0",X"03",X"D6",X"00",X"AC",X"01",X"75",X"04",X"00",X"00",X"01",X"01",X"01",X"01",X"8F",
+		X"00",X"1D",X"01",X"1D",X"01",X"01",X"01",X"01",X"01",X"AA",X"00",X"53",X"01",X"53",X"01",X"01",
+		X"01",X"01",X"01",X"D6",X"00",X"AC",X"01",X"AC",X"01",X"01",X"01",X"01",X"01",X"B4",X"00",X"68",
+		X"01",X"68",X"01",X"01",X"01",X"01",X"01",X"AA",X"00",X"53",X"01",X"53",X"01",X"01",X"01",X"01",
+		X"01",X"B4",X"00",X"68",X"01",X"68",X"01",X"01",X"01",X"01",X"01",X"AA",X"00",X"53",X"01",X"53",
+		X"01",X"01",X"01",X"01",X"01",X"02",X"06",X"D6",X"00",X"AC",X"01",X"AC",X"01",X"01",X"01",X"01",
+		X"01",X"6B",X"00",X"7F",X"00",X"8F",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"5C",X"46",X"92",X"92",X"92",X"75",X"75",X"75",X"85",X"FE",X"85",X"85",X"46",X"46",X"75",X"46",
+		X"46",X"92",X"92",X"92",X"85",X"75",X"75",X"75",X"5C",X"85",X"5C",X"5C",X"FE",X"5C",X"5C",X"3B",
+		X"46",X"46",X"46",X"46",X"75",X"85",X"46",X"85",X"5C",X"FE",X"5C",X"5C",X"5C",X"5C",X"75",X"85",
+		X"92",X"75",X"75",X"75",X"75",X"5C",X"46",X"46",X"46",X"5C",X"92",X"92",X"92",X"46",X"FF",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A5",X"9E",X"A9",X"98",X"AE",
+		X"92",X"B3",X"8D",X"B7",X"85",X"B7",X"85",X"B3",X"8D",X"AE",X"92",X"A9",X"A8",X"A5",X"9E",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"78",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"21",X"8E",X"42",X"7E",X"47",X"E6",X"C3",X"28",X"12",
+		X"FE",X"80",X"20",X"59",X"78",X"E6",X"18",X"FE",X"18",X"20",X"52",X"3A",X"AF",X"42",X"CB",X"4F",
+		X"20",X"4B",X"21",X"9D",X"42",X"35",X"C0",X"36",X"01",X"DD",X"2A",X"91",X"42",X"21",X"8F",X"42",
+		X"CB",X"46",X"C2",X"09",X"22",X"3E",X"08",X"32",X"9B",X"42",X"0E",X"00",X"08",X"47",X"08",X"0A",
+		X"CB",X"57",X"C2",X"45",X"21",X"CB",X"5F",X"20",X"2A",X"CB",X"6F",X"C2",X"83",X"21",X"57",X"3A",
+		X"86",X"42",X"CB",X"5F",X"20",X"08",X"FD",X"E5",X"C1",X"78",X"FE",X"41",X"28",X"07",X"CB",X"72",
+		X"C2",X"CC",X"21",X"18",X"08",X"3A",X"00",X"60",X"CB",X"7F",X"C2",X"CC",X"21",X"21",X"CD",X"42",
+		X"CB",X"A6",X"C9",X"3A",X"5C",X"42",X"FE",X"E0",X"28",X"F3",X"C6",X"10",X"47",X"3A",X"5F",X"42",
+		X"4F",X"CD",X"4A",X"24",X"38",X"E7",X"CD",X"04",X"25",X"DD",X"7E",X"C0",X"EB",X"DD",X"22",X"97",
+		X"42",X"DD",X"E5",X"E1",X"01",X"20",X"00",X"A7",X"ED",X"42",X"22",X"99",X"42",X"A7",X"ED",X"42",
+		X"22",X"93",X"42",X"DD",X"E5",X"E1",X"01",X"60",X"00",X"A7",X"ED",X"42",X"EB",X"0E",X"11",X"CD",
+		X"B8",X"23",X"C3",X"F3",X"22",X"3A",X"5C",X"42",X"FE",X"10",X"CA",X"FD",X"20",X"D6",X"10",X"47",
+		X"3A",X"5F",X"42",X"4F",X"CD",X"4A",X"24",X"DA",X"FD",X"20",X"CD",X"04",X"25",X"DD",X"7E",X"20",
+		X"EB",X"DD",X"22",X"97",X"42",X"DD",X"E5",X"E1",X"01",X"20",X"00",X"09",X"22",X"99",X"42",X"09",
+		X"22",X"93",X"42",X"DD",X"E5",X"E1",X"01",X"20",X"00",X"09",X"EB",X"0E",X"21",X"CD",X"B8",X"23",
+		X"C3",X"3E",X"23",X"3A",X"5F",X"42",X"FE",X"20",X"CA",X"FD",X"20",X"D6",X"10",X"4F",X"3A",X"5C",
+		X"42",X"47",X"CD",X"4A",X"24",X"DA",X"FD",X"20",X"CD",X"04",X"25",X"DD",X"7E",X"FF",X"EB",X"DD",
+		X"22",X"97",X"42",X"DD",X"E5",X"E1",X"2B",X"22",X"99",X"42",X"2B",X"22",X"93",X"42",X"DD",X"E5",
+		X"E1",X"01",X"22",X"00",X"A7",X"ED",X"42",X"EB",X"0E",X"81",X"CD",X"B8",X"23",X"3A",X"5F",X"42",
+		X"FE",X"30",X"C2",X"5D",X"22",X"CB",X"CE",X"CB",X"D6",X"C3",X"5D",X"22",X"3A",X"5F",X"42",X"FE",
+		X"E0",X"CA",X"FD",X"20",X"C6",X"10",X"4F",X"3A",X"5C",X"42",X"47",X"CD",X"4A",X"24",X"DA",X"FD",
+		X"20",X"CD",X"04",X"25",X"DD",X"7E",X"02",X"EB",X"DD",X"22",X"97",X"42",X"DD",X"E5",X"E1",X"23",
+		X"22",X"99",X"42",X"23",X"22",X"93",X"42",X"DD",X"E5",X"E1",X"01",X"1E",X"00",X"A7",X"ED",X"42",
+		X"EB",X"0E",X"41",X"CD",X"B8",X"23",X"C3",X"A8",X"22",X"0E",X"00",X"08",X"47",X"08",X"0A",X"57",
+		X"E6",X"2C",X"20",X"19",X"3A",X"86",X"42",X"CB",X"5F",X"20",X"26",X"FD",X"E5",X"C1",X"78",X"FE",
+		X"41",X"20",X"1E",X"3A",X"00",X"60",X"CB",X"7F",X"CA",X"FD",X"20",X"18",X"19",X"CB",X"57",X"28",
+		X"04",X"CB",X"66",X"18",X"13",X"CB",X"5F",X"28",X"04",X"CB",X"6E",X"18",X"0B",X"CB",X"76",X"18",
+		X"07",X"CB",X"72",X"CA",X"FD",X"20",X"CB",X"7E",X"C4",X"35",X"25",X"CD",X"04",X"25",X"CB",X"66",
+		X"C2",X"F3",X"22",X"CB",X"6E",X"C2",X"3E",X"23",X"CB",X"76",X"C2",X"A8",X"22",X"21",X"5F",X"42",
+		X"35",X"35",X"CD",X"0D",X"24",X"CD",X"5B",X"33",X"78",X"F5",X"A7",X"28",X"0D",X"FE",X"01",X"28",
+		X"03",X"CD",X"89",X"22",X"11",X"FF",X"FF",X"CD",X"32",X"24",X"F1",X"FE",X"03",X"28",X"04",X"CB",
+		X"4E",X"28",X"03",X"CD",X"89",X"22",X"C3",X"67",X"23",X"DD",X"2A",X"91",X"42",X"E5",X"DD",X"7E",
+		X"00",X"21",X"C4",X"24",X"CD",X"3C",X"24",X"DD",X"71",X"00",X"DD",X"7E",X"E0",X"21",X"D4",X"24",
+		X"CD",X"3C",X"24",X"DD",X"71",X"E0",X"E1",X"C9",X"21",X"5F",X"42",X"34",X"34",X"CD",X"0D",X"24",
+		X"CD",X"5B",X"33",X"78",X"F5",X"A7",X"28",X"0D",X"FE",X"01",X"28",X"03",X"CD",X"D4",X"22",X"11",
+		X"01",X"00",X"CD",X"32",X"24",X"F1",X"FE",X"03",X"28",X"04",X"CB",X"4E",X"28",X"03",X"CD",X"D4",
+		X"22",X"C3",X"67",X"23",X"DD",X"2A",X"91",X"42",X"E5",X"DD",X"7E",X"01",X"21",X"E4",X"24",X"CD",
+		X"3C",X"24",X"DD",X"71",X"01",X"DD",X"7E",X"E1",X"21",X"F4",X"24",X"CD",X"3C",X"24",X"DD",X"71",
+		X"E1",X"E1",X"C9",X"21",X"5C",X"42",X"34",X"34",X"CD",X"0D",X"24",X"CD",X"5B",X"33",X"78",X"F5",
+		X"A7",X"28",X"0D",X"FE",X"01",X"28",X"03",X"CD",X"1F",X"23",X"11",X"E0",X"FF",X"CD",X"32",X"24",
+		X"F1",X"FE",X"03",X"28",X"04",X"CB",X"4E",X"28",X"03",X"CD",X"1F",X"23",X"C3",X"67",X"23",X"DD",
+		X"2A",X"91",X"42",X"E5",X"DD",X"7E",X"E0",X"21",X"84",X"24",X"CD",X"3C",X"24",X"DD",X"71",X"E0",
+		X"DD",X"7E",X"E1",X"21",X"94",X"24",X"CD",X"3C",X"24",X"DD",X"71",X"E1",X"E1",X"C9",X"21",X"5C",
+		X"42",X"35",X"35",X"CD",X"0D",X"24",X"CD",X"5B",X"33",X"78",X"F5",X"A7",X"28",X"0D",X"FE",X"01",
+		X"28",X"03",X"CD",X"7F",X"23",X"11",X"20",X"00",X"CD",X"32",X"24",X"F1",X"FE",X"03",X"28",X"04",
+		X"CB",X"4E",X"28",X"03",X"CD",X"7F",X"23",X"CB",X"5E",X"28",X"04",X"3E",X"19",X"18",X"02",X"3E",
+		X"26",X"32",X"9D",X"42",X"21",X"9B",X"42",X"35",X"C0",X"21",X"8F",X"42",X"CB",X"86",X"C9",X"DD",
+		X"2A",X"91",X"42",X"E5",X"DD",X"7E",X"00",X"21",X"A4",X"24",X"CD",X"3C",X"24",X"DD",X"71",X"00",
+		X"DD",X"7E",X"01",X"21",X"B4",X"24",X"CD",X"3C",X"24",X"DD",X"71",X"01",X"E1",X"C9",X"06",X"00",
+		X"FE",X"10",X"C8",X"FE",X"B4",X"D0",X"04",X"FE",X"50",X"C8",X"04",X"FE",X"4C",X"D0",X"04",X"FE",
+		X"4A",X"D0",X"04",X"FE",X"48",X"D0",X"04",X"C9",X"47",X"7E",X"E6",X"08",X"B1",X"77",X"78",X"CD",
+		X"9E",X"23",X"78",X"FE",X"00",X"C8",X"FE",X"02",X"28",X"18",X"38",X"32",X"FE",X"05",X"28",X"0E",
+		X"79",X"E6",X"30",X"78",X"28",X"05",X"FE",X"04",X"C8",X"18",X"03",X"FE",X"03",X"C8",X"CB",X"D6",
+		X"18",X"28",X"3E",X"50",X"12",X"13",X"12",X"EB",X"01",X"1F",X"00",X"09",X"EB",X"12",X"13",X"12",
+		X"CB",X"DE",X"E5",X"21",X"BD",X"42",X"CB",X"C6",X"21",X"BC",X"42",X"36",X"03",X"E1",X"C5",X"D5",
+		X"01",X"00",X"00",X"16",X"10",X"CD",X"CC",X"06",X"D1",X"C1",X"CB",X"CE",X"C9",X"06",X"00",X"21",
+		X"8F",X"42",X"3A",X"9B",X"42",X"FE",X"07",X"28",X"0B",X"FE",X"03",X"28",X"01",X"C9",X"CB",X"4E",
+		X"28",X"0E",X"18",X"0B",X"CB",X"4E",X"28",X"08",X"CB",X"56",X"28",X"03",X"CB",X"8E",X"04",X"04",
+		X"04",X"C9",X"E5",X"2A",X"91",X"42",X"19",X"22",X"91",X"42",X"E1",X"C9",X"06",X"08",X"4F",X"BE",
+		X"20",X"03",X"23",X"4E",X"C9",X"23",X"23",X"10",X"F6",X"C9",X"D5",X"E5",X"DD",X"E5",X"DD",X"2A",
+		X"A9",X"42",X"16",X"03",X"DD",X"CB",X"00",X"46",X"20",X"17",X"DD",X"CB",X"00",X"4E",X"20",X"11",
+		X"DD",X"66",X"02",X"DD",X"6E",X"01",X"78",X"BE",X"20",X"07",X"23",X"23",X"23",X"79",X"BE",X"28",
+		X"0D",X"D5",X"11",X"07",X"00",X"DD",X"19",X"D1",X"15",X"20",X"D9",X"A7",X"18",X"01",X"37",X"DD",
+		X"E1",X"E1",X"D1",X"C9",X"3E",X"48",X"50",X"40",X"40",X"42",X"42",X"46",X"46",X"3E",X"44",X"48",
+		X"4A",X"10",X"4B",X"10",X"3F",X"49",X"50",X"41",X"41",X"43",X"43",X"47",X"47",X"3F",X"45",X"49",
+		X"4A",X"10",X"4B",X"10",X"38",X"48",X"50",X"3A",X"3A",X"3C",X"3C",X"44",X"44",X"38",X"46",X"48",
+		X"4A",X"10",X"4B",X"10",X"39",X"49",X"50",X"3B",X"3B",X"3D",X"3D",X"45",X"45",X"39",X"47",X"49",
+		X"4A",X"10",X"4B",X"10",X"32",X"4A",X"50",X"34",X"34",X"36",X"36",X"44",X"44",X"32",X"45",X"4A",
+		X"48",X"10",X"49",X"10",X"33",X"4B",X"50",X"35",X"35",X"37",X"37",X"46",X"46",X"33",X"47",X"4B",
+		X"48",X"10",X"49",X"10",X"2C",X"4A",X"50",X"2E",X"2E",X"30",X"30",X"45",X"45",X"2C",X"44",X"4A",
+		X"48",X"10",X"49",X"10",X"2D",X"4B",X"50",X"2F",X"2F",X"31",X"31",X"47",X"47",X"2D",X"46",X"4B",
+		X"48",X"10",X"49",X"10",X"F5",X"E5",X"21",X"CD",X"42",X"CB",X"E6",X"FD",X"7E",X"06",X"FE",X"01",
+		X"28",X"16",X"3A",X"A6",X"42",X"B7",X"28",X"10",X"3A",X"8F",X"42",X"CB",X"5F",X"20",X"09",X"3A",
+		X"7F",X"43",X"E6",X"0F",X"F6",X"40",X"18",X"07",X"3A",X"7F",X"43",X"E6",X"0F",X"F6",X"30",X"32",
+		X"7F",X"43",X"E1",X"F1",X"C9",X"E5",X"3A",X"8F",X"42",X"E6",X"08",X"F6",X"01",X"47",X"CD",X"DE",
+		X"33",X"28",X"06",X"E6",X"30",X"F6",X"CF",X"18",X"04",X"E6",X"C0",X"F6",X"3F",X"2F",X"B0",X"32",
+		X"90",X"42",X"2A",X"91",X"42",X"3A",X"9B",X"42",X"FE",X"06",X"20",X"05",X"2A",X"97",X"42",X"18",
+		X"07",X"FE",X"02",X"20",X"03",X"2A",X"99",X"42",X"22",X"95",X"42",X"47",X"3E",X"08",X"90",X"32",
+		X"9C",X"42",X"2A",X"97",X"42",X"ED",X"5B",X"93",X"42",X"22",X"93",X"42",X"ED",X"53",X"97",X"42",
+		X"CD",X"8A",X"2B",X"3A",X"90",X"42",X"32",X"8F",X"42",X"3A",X"9C",X"42",X"32",X"9B",X"42",X"2A",
+		X"95",X"42",X"22",X"91",X"42",X"E1",X"C9",X"3A",X"8E",X"42",X"CB",X"47",X"C0",X"CB",X"77",X"C0",
+		X"2A",X"A2",X"42",X"7E",X"A7",X"20",X"12",X"2A",X"A0",X"42",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7E",X"CB",X"47",X"20",X"2A",X"E5",X"DD",X"E1",
+		X"23",X"47",X"4E",X"79",X"E6",X"0F",X"20",X"24",X"CD",X"D5",X"25",X"DD",X"66",X"07",X"DD",X"6E",
+		X"06",X"C3",X"F1",X"25",X"23",X"23",X"23",X"23",X"23",X"23",X"23",X"23",X"23",X"23",X"22",X"A2",
+		X"42",X"C9",X"06",X"80",X"10",X"FE",X"C9",X"CD",X"E2",X"25",X"18",X"E8",X"CD",X"E2",X"25",X"18",
+		X"E4",X"DD",X"35",X"02",X"C0",X"CB",X"50",X"CA",X"F6",X"26",X"CB",X"60",X"C4",X"44",X"26",X"CB",
+		X"68",X"C4",X"41",X"26",X"23",X"23",X"23",X"CB",X"70",X"C4",X"44",X"26",X"CB",X"78",X"C4",X"41",
+		X"26",X"DD",X"35",X"03",X"20",X"1B",X"DD",X"CB",X"00",X"96",X"CB",X"58",X"28",X"13",X"DD",X"56",
+		X"05",X"DD",X"5E",X"04",X"1A",X"FE",X"50",X"28",X"08",X"FE",X"4E",X"28",X"04",X"DD",X"CB",X"00",
+		X"9E",X"3A",X"9E",X"42",X"DD",X"CB",X"00",X"5E",X"28",X"03",X"3A",X"9F",X"42",X"DD",X"77",X"02",
+		X"C9",X"35",X"35",X"C9",X"34",X"34",X"C9",X"D5",X"E5",X"DD",X"E5",X"01",X"00",X"00",X"DD",X"56",
+		X"05",X"DD",X"5E",X"04",X"D5",X"DD",X"E1",X"7E",X"23",X"23",X"23",X"56",X"21",X"B2",X"26",X"DD",
+		X"5E",X"E0",X"CD",X"99",X"26",X"21",X"B5",X"26",X"DD",X"5E",X"00",X"CD",X"99",X"26",X"7A",X"21",
+		X"BB",X"26",X"DD",X"5E",X"01",X"CD",X"99",X"26",X"FE",X"20",X"20",X"0F",X"F5",X"DD",X"7E",X"02",
+		X"FE",X"10",X"28",X"06",X"FE",X"4A",X"28",X"02",X"CB",X"B9",X"F1",X"21",X"B8",X"26",X"DD",X"5E",
+		X"00",X"CD",X"99",X"26",X"DD",X"E1",X"E1",X"D1",X"C9",X"F5",X"BE",X"28",X"0F",X"7B",X"23",X"1E",
+		X"02",X"BE",X"28",X"06",X"23",X"1D",X"20",X"F9",X"CB",X"C1",X"CB",X"C0",X"CB",X"09",X"CB",X"08",
+		X"F1",X"C9",X"E0",X"46",X"4B",X"10",X"44",X"4A",X"20",X"44",X"48",X"E0",X"45",X"49",X"E5",X"1E",
+		X"00",X"56",X"23",X"23",X"23",X"FD",X"7E",X"06",X"FE",X"01",X"3A",X"5C",X"42",X"20",X"02",X"3E",
+		X"10",X"BA",X"28",X"08",X"38",X"04",X"CB",X"E3",X"18",X"02",X"CB",X"EB",X"56",X"FD",X"7E",X"06",
+		X"FE",X"01",X"3A",X"5F",X"42",X"20",X"02",X"3E",X"20",X"BA",X"28",X"08",X"38",X"04",X"CB",X"F3",
+		X"18",X"02",X"CB",X"FB",X"E1",X"C9",X"CD",X"47",X"26",X"CD",X"BE",X"26",X"DD",X"CB",X"00",X"5E",
+		X"C2",X"65",X"28",X"FD",X"7E",X"06",X"FE",X"01",X"CC",X"B4",X"28",X"DD",X"CB",X"00",X"4E",X"C4",
+		X"0D",X"35",X"DD",X"7E",X"00",X"E6",X"30",X"7B",X"CA",X"B1",X"27",X"E6",X"C0",X"5F",X"28",X"05",
+		X"CD",X"6A",X"28",X"18",X"18",X"79",X"E6",X"C0",X"20",X"23",X"78",X"E6",X"C0",X"FE",X"C0",X"5F",
+		X"20",X"0B",X"CD",X"AC",X"28",X"28",X"04",X"CB",X"BB",X"18",X"02",X"CB",X"B3",X"CD",X"C9",X"28",
+		X"E6",X"F0",X"20",X"09",X"7B",X"DD",X"CB",X"00",X"DE",X"CD",X"6C",X"28",X"76",X"DD",X"7E",X"00",
+		X"E6",X"0F",X"57",X"DD",X"7E",X"00",X"E6",X"30",X"B2",X"DD",X"77",X"00",X"3A",X"AB",X"42",X"B7",
+		X"28",X"11",X"3A",X"AC",X"42",X"BE",X"20",X"0B",X"DD",X"7E",X"00",X"E6",X"30",X"CD",X"6A",X"28",
+		X"C3",X"3F",X"28",X"DD",X"7E",X"00",X"E6",X"30",X"A1",X"20",X"1D",X"79",X"E6",X"C0",X"5F",X"28",
+		X"14",X"FE",X"C0",X"20",X"0B",X"CD",X"AC",X"28",X"28",X"04",X"CB",X"BB",X"18",X"02",X"CB",X"B3",
+		X"7B",X"CD",X"6C",X"28",X"76",X"59",X"18",X"F8",X"79",X"E6",X"C0",X"5F",X"28",X"0B",X"FE",X"C0",
+		X"28",X"07",X"CD",X"C9",X"28",X"FE",X"A0",X"30",X"E7",X"DD",X"7E",X"00",X"E6",X"30",X"5F",X"18",
+		X"DF",X"E6",X"30",X"5F",X"28",X"05",X"CD",X"6A",X"28",X"18",X"18",X"79",X"E6",X"30",X"20",X"23",
+		X"78",X"E6",X"30",X"FE",X"30",X"5F",X"20",X"0B",X"CD",X"AC",X"28",X"28",X"04",X"CB",X"AB",X"18",
+		X"02",X"CB",X"A3",X"CD",X"C9",X"28",X"E6",X"F0",X"20",X"09",X"7B",X"DD",X"CB",X"00",X"DE",X"CD",
+		X"6C",X"28",X"76",X"DD",X"7E",X"00",X"E6",X"0F",X"57",X"DD",X"7E",X"00",X"E6",X"C0",X"B2",X"DD",
+		X"77",X"00",X"3A",X"AB",X"42",X"B7",X"28",X"09",X"3A",X"AC",X"42",X"BE",X"20",X"03",X"C3",X"3F",
+		X"28",X"DD",X"7E",X"00",X"E6",X"C0",X"A1",X"20",X"1D",X"79",X"E6",X"30",X"5F",X"28",X"14",X"FE",
+		X"30",X"20",X"0B",X"CD",X"AC",X"28",X"28",X"04",X"CB",X"AB",X"18",X"02",X"CB",X"A3",X"7B",X"CD",
+		X"6C",X"28",X"76",X"59",X"18",X"F8",X"79",X"E6",X"30",X"5F",X"28",X"0B",X"FE",X"30",X"28",X"07",
+		X"CD",X"C9",X"28",X"FE",X"A0",X"30",X"E7",X"DD",X"7E",X"00",X"E6",X"C0",X"5F",X"18",X"DF",X"79",
+		X"E6",X"30",X"5F",X"28",X"14",X"FE",X"30",X"20",X"0B",X"CD",X"AC",X"28",X"28",X"04",X"CB",X"AB",
+		X"18",X"02",X"CB",X"A3",X"7B",X"CD",X"6C",X"28",X"76",X"79",X"E6",X"C0",X"5F",X"FE",X"C0",X"20",
+		X"F3",X"1E",X"40",X"18",X"EF",X"7B",X"CD",X"6C",X"28",X"76",X"A1",X"C8",X"4F",X"DD",X"CB",X"00",
+		X"D6",X"DD",X"7E",X"00",X"E6",X"0F",X"B1",X"47",X"F1",X"DD",X"36",X"03",X"08",X"DD",X"70",X"00",
+		X"E5",X"DD",X"6E",X"04",X"DD",X"66",X"05",X"11",X"40",X"00",X"CB",X"60",X"28",X"03",X"A7",X"ED",
+		X"52",X"CB",X"68",X"28",X"01",X"19",X"CB",X"70",X"28",X"02",X"23",X"23",X"CB",X"78",X"28",X"02",
+		X"2B",X"2B",X"DD",X"75",X"04",X"DD",X"74",X"05",X"E1",X"C3",X"FA",X"25",X"57",X"CD",X"C9",X"28",
+		X"CB",X"7F",X"7A",X"C9",X"7E",X"B7",X"20",X"09",X"FD",X"35",X"06",X"DD",X"CB",X"00",X"C6",X"F1",
+		X"C9",X"7B",X"B7",X"C0",X"3E",X"20",X"C3",X"6C",X"28",X"D9",X"2A",X"A7",X"42",X"E5",X"D1",X"29",
+		X"29",X"E5",X"C1",X"29",X"09",X"19",X"23",X"22",X"A7",X"42",X"7C",X"D9",X"C9",X"DD",X"2A",X"A9",
+		X"42",X"06",X"03",X"DD",X"CB",X"00",X"46",X"20",X"15",X"DD",X"66",X"02",X"DD",X"6E",X"01",X"DD",
+		X"56",X"06",X"DD",X"5E",X"05",X"C5",X"DD",X"E5",X"CD",X"06",X"29",X"DD",X"E1",X"C1",X"11",X"07",
+		X"00",X"DD",X"19",X"10",X"DE",X"C9",X"DD",X"CB",X"00",X"4E",X"20",X"42",X"3A",X"AB",X"42",X"A7",
+		X"C0",X"DD",X"CB",X"00",X"7E",X"3A",X"8F",X"42",X"20",X"17",X"CB",X"47",X"C0",X"3A",X"5C",X"42",
+		X"BE",X"C0",X"3A",X"5F",X"42",X"D6",X"10",X"23",X"23",X"23",X"BE",X"C0",X"DD",X"CB",X"00",X"FE",
+		X"C9",X"CB",X"47",X"C8",X"3E",X"01",X"32",X"AB",X"42",X"7E",X"32",X"AC",X"42",X"DD",X"36",X"03",
+		X"FF",X"DD",X"36",X"04",X"04",X"DD",X"CB",X"00",X"CE",X"DD",X"CB",X"00",X"96",X"C9",X"DD",X"35",
+		X"03",X"C0",X"DD",X"CB",X"00",X"56",X"20",X"30",X"DD",X"36",X"03",X"50",X"DD",X"CB",X"04",X"46",
+		X"7E",X"06",X"04",X"28",X"03",X"80",X"18",X"01",X"90",X"77",X"DD",X"35",X"04",X"C0",X"DD",X"CB",
+		X"00",X"D6",X"DD",X"CB",X"00",X"9E",X"DD",X"CB",X"00",X"E6",X"DD",X"36",X"03",X"80",X"AF",X"32",
+		X"AD",X"42",X"21",X"CA",X"42",X"CB",X"DE",X"C9",X"DD",X"CB",X"00",X"5E",X"C2",X"26",X"2A",X"DD",
+		X"36",X"03",X"03",X"23",X"23",X"23",X"7E",X"FE",X"E0",X"28",X"63",X"E6",X"0F",X"20",X"17",X"DD",
+		X"CB",X"00",X"66",X"20",X"05",X"CD",X"DE",X"2B",X"38",X"54",X"13",X"13",X"DD",X"72",X"06",X"DD",
+		X"73",X"05",X"DD",X"CB",X"00",X"A6",X"34",X"34",X"5E",X"2B",X"2B",X"2B",X"56",X"DD",X"E5",X"CD",
+		X"10",X"2B",X"AF",X"32",X"AE",X"42",X"CD",X"1F",X"2B",X"38",X"12",X"CB",X"41",X"20",X"09",X"CB",
+		X"59",X"20",X"F3",X"CD",X"3C",X"2B",X"18",X"EE",X"CD",X"6C",X"2B",X"18",X"E9",X"21",X"5C",X"42",
+		X"3A",X"8E",X"42",X"CB",X"47",X"20",X"10",X"CB",X"4F",X"20",X"09",X"CB",X"77",X"20",X"08",X"CD",
+		X"71",X"2B",X"18",X"03",X"CD",X"6C",X"2B",X"DD",X"E1",X"3A",X"AE",X"42",X"A7",X"C8",X"DD",X"CB",
+		X"00",X"DE",X"DD",X"CB",X"00",X"F6",X"DD",X"36",X"03",X"FF",X"21",X"CC",X"42",X"CB",X"9E",X"21",
+		X"CA",X"42",X"CB",X"9E",X"CB",X"E6",X"3A",X"AD",X"42",X"A7",X"C0",X"3A",X"8E",X"42",X"CB",X"4F",
+		X"C0",X"DD",X"CB",X"00",X"EE",X"C9",X"DD",X"CB",X"00",X"6E",X"28",X"2A",X"DD",X"36",X"03",X"8C",
+		X"DD",X"CB",X"00",X"76",X"28",X"08",X"DD",X"CB",X"00",X"B6",X"23",X"36",X"22",X"C9",X"23",X"7E",
+		X"FE",X"23",X"28",X"03",X"36",X"23",X"C9",X"CD",X"EE",X"2A",X"2B",X"DD",X"CB",X"00",X"C6",X"AF",
+		X"77",X"23",X"23",X"23",X"77",X"C9",X"DD",X"CB",X"00",X"76",X"28",X"77",X"3A",X"AD",X"42",X"A7",
+		X"20",X"09",X"CD",X"EE",X"2A",X"CD",X"4B",X"2A",X"C3",X"F9",X"2A",X"DD",X"CB",X"00",X"B6",X"DD",
+		X"36",X"03",X"FF",X"47",X"FD",X"7E",X"06",X"90",X"FD",X"77",X"06",X"3A",X"8E",X"42",X"CB",X"4F",
+		X"C4",X"0A",X"2B",X"E5",X"21",X"10",X"00",X"1E",X"25",X"05",X"28",X"04",X"29",X"1C",X"10",X"FC",
+		X"16",X"00",X"E5",X"C1",X"CD",X"CC",X"06",X"E1",X"7E",X"D6",X"08",X"77",X"C6",X"10",X"57",X"23",
+		X"73",X"23",X"36",X"07",X"23",X"5E",X"CD",X"10",X"2B",X"AF",X"32",X"AE",X"42",X"CD",X"1F",X"2B",
+		X"D8",X"CB",X"41",X"28",X"F8",X"3A",X"AE",X"42",X"A7",X"20",X"0F",X"3C",X"32",X"AE",X"42",X"72",
+		X"23",X"36",X"24",X"23",X"36",X"07",X"23",X"73",X"18",X"E3",X"DD",X"CB",X"00",X"C6",X"CD",X"4F",
+		X"2A",X"18",X"DA",X"CD",X"F3",X"2A",X"CD",X"4B",X"2A",X"CD",X"EE",X"2A",X"CD",X"10",X"2B",X"CD",
+		X"1F",X"2B",X"D8",X"CB",X"41",X"28",X"F8",X"DD",X"CB",X"00",X"C6",X"C3",X"4F",X"2A",X"AF",X"32",
+		X"AB",X"42",X"C9",X"3A",X"8E",X"42",X"CB",X"4F",X"C8",X"3A",X"8E",X"42",X"CB",X"F7",X"32",X"8E",
+		X"42",X"3E",X"05",X"32",X"9B",X"42",X"AF",X"32",X"9D",X"42",X"3E",X"00",X"32",X"5D",X"42",X"C9",
+		X"E5",X"2A",X"A0",X"42",X"01",X"0A",X"00",X"A7",X"ED",X"42",X"E5",X"DD",X"E1",X"E1",X"C9",X"01",
+		X"0A",X"00",X"DD",X"09",X"DD",X"7E",X"00",X"A7",X"28",X"10",X"CB",X"47",X"20",X"F4",X"47",X"DD",
+		X"4E",X"01",X"DD",X"66",X"07",X"DD",X"6E",X"06",X"A7",X"C9",X"37",X"C9",X"CD",X"B3",X"2B",X"CD",
+		X"C1",X"2B",X"D8",X"DD",X"CB",X"01",X"56",X"28",X"09",X"DD",X"CB",X"01",X"66",X"28",X"03",X"CD",
+		X"5B",X"33",X"DD",X"CB",X"01",X"4E",X"C4",X"5F",X"36",X"DD",X"CB",X"01",X"C6",X"3A",X"AD",X"42",
+		X"3C",X"32",X"AD",X"42",X"79",X"FE",X"E0",X"C0",X"32",X"AE",X"42",X"C9",X"CD",X"B9",X"2B",X"18",
+		X"F3",X"CD",X"B3",X"2B",X"CD",X"C1",X"2B",X"D8",X"CD",X"5B",X"33",X"3A",X"8E",X"42",X"CB",X"CF",
+		X"32",X"8E",X"42",X"C5",X"CD",X"8A",X"2B",X"C1",X"18",X"DA",X"3A",X"8F",X"42",X"CB",X"47",X"C8",
+		X"CB",X"4F",X"C8",X"CB",X"67",X"28",X"05",X"CD",X"F8",X"22",X"18",X"EE",X"CB",X"6F",X"28",X"05",
+		X"CD",X"43",X"23",X"18",X"E5",X"CB",X"77",X"28",X"05",X"CD",X"AD",X"22",X"18",X"DC",X"CD",X"62",
+		X"22",X"18",X"D7",X"46",X"23",X"23",X"23",X"4E",X"C9",X"46",X"23",X"23",X"23",X"34",X"34",X"4E",
+		X"C9",X"7A",X"C5",X"B8",X"30",X"03",X"4F",X"78",X"41",X"90",X"C1",X"FE",X"0D",X"30",X"0D",X"7B",
+		X"C6",X"08",X"B9",X"28",X"05",X"C6",X"02",X"B9",X"20",X"02",X"A7",X"C9",X"37",X"C9",X"DD",X"E5",
+		X"D5",X"DD",X"E1",X"DD",X"7E",X"02",X"FE",X"50",X"28",X"28",X"FE",X"4E",X"28",X"24",X"CD",X"16",
+		X"2C",X"DD",X"77",X"02",X"DD",X"7E",X"E2",X"CD",X"16",X"2C",X"DD",X"77",X"E2",X"DD",X"7E",X"01",
+		X"CD",X"16",X"2C",X"DD",X"77",X"01",X"DD",X"7E",X"E1",X"CD",X"16",X"2C",X"DD",X"77",X"E1",X"A7",
+		X"18",X"01",X"37",X"DD",X"E1",X"C9",X"E5",X"21",X"29",X"2C",X"06",X"06",X"BE",X"28",X"06",X"23",
+		X"23",X"10",X"F9",X"E1",X"C9",X"23",X"7E",X"E1",X"C9",X"44",X"4A",X"45",X"4A",X"46",X"4B",X"47",
+		X"4B",X"48",X"10",X"49",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"BF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"BF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"EF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"4B",X"20",X"35",X"38",X"00",X"00",X"54",X"52",X"55",X"44",X"41",X"54",X"15",X"39",X"00",X"00",
+		X"49",X"57",X"44",X"41",X"54",X"41",X"1D",X"39",X"00",X"00",X"4F",X"49",X"4B",X"44",X"41",X"54",
+		X"41",X"39",X"00",X"00",X"00",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"16",X"00",X"CD",X"EC",X"00",X"CA",X"26",X"21",X"3A",
+		X"89",X"42",X"FE",X"00",X"20",X"59",X"CD",X"DC",X"00",X"CA",X"26",X"21",X"1E",X"01",X"CD",X"EC",
+		X"00",X"FE",X"00",X"28",X"24",X"FE",X"01",X"20",X"19",X"21",X"8C",X"42",X"7E",X"B7",X"28",X"04",
+		X"36",X"00",X"18",X"15",X"3E",X"01",X"77",X"32",X"89",X"42",X"3E",X"03",X"32",X"8A",X"42",X"C3",
+		X"26",X"21",X"21",X"8B",X"42",X"34",X"1C",X"18",X"03",X"21",X"8B",X"42",X"34",X"3E",X"01",X"32",
+		X"89",X"42",X"3E",X"04",X"32",X"8A",X"42",X"3A",X"8D",X"42",X"B7",X"20",X"07",X"3A",X"88",X"42",
+		X"B7",X"20",X"01",X"14",X"3A",X"88",X"42",X"83",X"27",X"32",X"88",X"42",X"C3",X"26",X"21",X"FE",
+		X"01",X"21",X"8A",X"42",X"20",X"0E",X"35",X"C2",X"26",X"21",X"3E",X"02",X"32",X"89",X"42",X"36",
+		X"03",X"C3",X"26",X"21",X"35",X"20",X"07",X"AF",X"32",X"89",X"42",X"C3",X"26",X"21",X"CD",X"DC",
+		X"00",X"CA",X"26",X"21",X"36",X"03",X"3A",X"00",X"78",X"3A",X"7C",X"42",X"C3",X"B6",X"00",X"3A",
+		X"BE",X"42",X"B7",X"C8",X"3A",X"BA",X"42",X"67",X"2E",X"00",X"3A",X"B0",X"42",X"57",X"A7",X"20",
+		X"0E",X"CD",X"AD",X"31",X"20",X"0E",X"21",X"B1",X"42",X"35",X"20",X"0F",X"3C",X"18",X"0C",X"CD",
+		X"AD",X"31",X"28",X"07",X"06",X"05",X"AF",X"21",X"B1",X"42",X"70",X"32",X"B0",X"42",X"7A",X"32",
+		X"AF",X"42",X"3A",X"8E",X"42",X"47",X"E6",X"43",X"C0",X"CB",X"78",X"C0",X"3A",X"AF",X"42",X"FE",
+		X"03",X"C0",X"3E",X"14",X"32",X"B2",X"42",X"CD",X"40",X"33",X"06",X"80",X"2A",X"93",X"42",X"22",
+		X"B5",X"42",X"3A",X"8F",X"42",X"CB",X"47",X"20",X"10",X"2A",X"91",X"42",X"22",X"B5",X"42",X"CD",
+		X"E1",X"32",X"22",X"B5",X"42",X"30",X"0C",X"18",X"08",X"CB",X"4F",X"28",X"06",X"CB",X"57",X"20",
+		X"02",X"CB",X"D0",X"78",X"32",X"8E",X"42",X"21",X"CA",X"42",X"CB",X"EE",X"C9",X"CB",X"66",X"C8",
+		X"CB",X"CA",X"C9",X"3A",X"8E",X"42",X"47",X"E6",X"43",X"C0",X"21",X"B7",X"42",X"35",X"C0",X"36",
+		X"03",X"CB",X"78",X"C8",X"CB",X"50",X"28",X"0D",X"21",X"CA",X"42",X"CB",X"AE",X"21",X"CC",X"42",
+		X"CB",X"AE",X"C3",X"5B",X"33",X"CB",X"60",X"C2",X"8E",X"32",X"CD",X"A3",X"32",X"CD",X"7E",X"33",
+		X"DD",X"21",X"6C",X"42",X"DD",X"56",X"00",X"DD",X"5E",X"03",X"CD",X"DE",X"33",X"06",X"08",X"28",
+		X"0C",X"CB",X"67",X"7A",X"20",X"03",X"90",X"18",X"01",X"80",X"57",X"18",X"0A",X"CB",X"77",X"7B",
+		X"20",X"03",X"90",X"18",X"01",X"80",X"5F",X"CD",X"10",X"2B",X"CD",X"1F",X"2B",X"38",X"58",X"CB",
+		X"41",X"20",X"F7",X"CB",X"59",X"20",X"F3",X"DD",X"7E",X"08",X"FE",X"05",X"28",X"EC",X"CD",X"B3",
+		X"2B",X"7A",X"CD",X"99",X"32",X"30",X"E3",X"7B",X"41",X"CD",X"99",X"32",X"30",X"DC",X"DD",X"CB",
+		X"01",X"4E",X"C4",X"5F",X"36",X"DD",X"22",X"B3",X"42",X"DD",X"CB",X"01",X"D6",X"DD",X"CB",X"01",
+		X"E6",X"DD",X"34",X"08",X"DD",X"36",X"09",X"80",X"21",X"CA",X"42",X"CB",X"F6",X"3A",X"8E",X"42",
+		X"CB",X"DF",X"CB",X"E7",X"32",X"8E",X"42",X"3E",X"14",X"32",X"B2",X"42",X"21",X"CA",X"42",X"CB",
+		X"AE",X"21",X"CC",X"42",X"CB",X"AE",X"C9",X"CD",X"DE",X"33",X"28",X"05",X"3A",X"6C",X"42",X"18",
+		X"03",X"3A",X"6F",X"42",X"E6",X"0F",X"20",X"0F",X"CD",X"E1",X"32",X"22",X"B5",X"42",X"30",X"07",
+		X"3A",X"8E",X"42",X"CB",X"9F",X"18",X"CB",X"21",X"B2",X"42",X"35",X"C0",X"18",X"F2",X"CB",X"58",
+		X"C0",X"21",X"B2",X"42",X"35",X"C0",X"C3",X"5B",X"33",X"B8",X"30",X"03",X"67",X"78",X"44",X"90",
+		X"FE",X"05",X"C9",X"3A",X"8F",X"42",X"4F",X"21",X"6C",X"42",X"E6",X"30",X"20",X"03",X"21",X"6F",
+		X"42",X"DD",X"21",X"6D",X"42",X"06",X"03",X"DD",X"7E",X"00",X"FE",X"00",X"C8",X"CD",X"CF",X"32",
+		X"DD",X"23",X"DD",X"23",X"DD",X"23",X"DD",X"23",X"23",X"23",X"23",X"23",X"10",X"E9",X"C9",X"CB",
+		X"79",X"C2",X"41",X"26",X"CB",X"71",X"C2",X"44",X"26",X"CB",X"69",X"C2",X"41",X"26",X"C3",X"44",
+		X"26",X"C5",X"D5",X"DD",X"E5",X"2A",X"B5",X"42",X"DD",X"21",X"34",X"33",X"3A",X"8F",X"42",X"47",
+		X"3A",X"6F",X"42",X"4F",X"3A",X"6C",X"42",X"CB",X"60",X"20",X"1B",X"DD",X"23",X"DD",X"23",X"DD",
+		X"23",X"CB",X"68",X"20",X"11",X"DD",X"23",X"DD",X"23",X"DD",X"23",X"79",X"CB",X"70",X"20",X"06",
+		X"DD",X"23",X"DD",X"23",X"DD",X"23",X"DD",X"BE",X"00",X"28",X"16",X"DD",X"56",X"02",X"DD",X"5E",
+		X"01",X"19",X"7E",X"FE",X"50",X"28",X"0A",X"FE",X"4E",X"28",X"06",X"A7",X"DD",X"E1",X"D1",X"C1",
+		X"C9",X"37",X"18",X"F8",X"E0",X"C0",X"FF",X"10",X"40",X"00",X"E0",X"02",X"00",X"20",X"FE",X"FF",
+		X"21",X"6C",X"42",X"3A",X"5C",X"42",X"57",X"3A",X"5F",X"42",X"5F",X"06",X"03",X"72",X"23",X"36",
+		X"00",X"23",X"36",X"07",X"23",X"73",X"23",X"10",X"F4",X"18",X"23",X"F5",X"C5",X"E5",X"21",X"6C",
+		X"42",X"06",X"0C",X"36",X"00",X"23",X"10",X"FB",X"3A",X"8E",X"42",X"CB",X"BF",X"CB",X"5F",X"28",
+		X"06",X"2A",X"B3",X"42",X"23",X"CB",X"A6",X"32",X"8E",X"42",X"E1",X"C1",X"F1",X"C9",X"DD",X"21",
+		X"6D",X"42",X"CD",X"DE",X"33",X"28",X"05",X"21",X"E7",X"33",X"18",X"03",X"21",X"03",X"34",X"3A",
+		X"B2",X"42",X"06",X"07",X"BE",X"28",X"08",X"D0",X"23",X"23",X"23",X"23",X"10",X"F6",X"C9",X"23",
+		X"4E",X"23",X"56",X"23",X"5E",X"CD",X"DE",X"33",X"28",X"16",X"CB",X"67",X"20",X"26",X"AF",X"B9",
+		X"28",X"02",X"CB",X"F9",X"BA",X"28",X"02",X"CB",X"FA",X"BB",X"28",X"18",X"CB",X"FB",X"18",X"14",
+		X"CB",X"7F",X"20",X"10",X"AF",X"B9",X"28",X"02",X"CB",X"F1",X"BA",X"28",X"02",X"CB",X"F2",X"BB",
+		X"28",X"02",X"CB",X"F3",X"DD",X"71",X"00",X"DD",X"72",X"04",X"DD",X"73",X"08",X"C9",X"3A",X"8F",
+		X"42",X"E6",X"30",X"3A",X"8F",X"42",X"C9",X"14",X"01",X"00",X"00",X"11",X"01",X"03",X"00",X"10",
+		X"02",X"05",X"00",X"0C",X"01",X"06",X"00",X"09",X"01",X"06",X"03",X"08",X"02",X"04",X"05",X"04",
+		X"01",X"06",X"06",X"14",X"07",X"00",X"00",X"11",X"07",X"09",X"00",X"10",X"08",X"0B",X"00",X"0C",
+		X"07",X"0C",X"00",X"09",X"07",X"0C",X"09",X"08",X"08",X"0A",X"0B",X"04",X"07",X"0C",X"0C",X"3A",
+		X"BE",X"42",X"B7",X"C8",X"21",X"8E",X"42",X"7E",X"E6",X"43",X"C0",X"CD",X"10",X"2B",X"CD",X"1F",
+		X"2B",X"D8",X"CB",X"41",X"20",X"F8",X"CB",X"51",X"28",X"F4",X"CB",X"59",X"20",X"59",X"DD",X"7E",
+		X"08",X"FE",X"05",X"28",X"68",X"CB",X"61",X"28",X"0B",X"3A",X"AF",X"42",X"FE",X"03",X"28",X"2E",
+		X"CB",X"4F",X"20",X"20",X"DD",X"7E",X"09",X"D6",X"03",X"DD",X"77",X"09",X"30",X"D0",X"DD",X"36",
+		X"09",X"80",X"DD",X"35",X"08",X"20",X"C7",X"DD",X"CB",X"01",X"96",X"CB",X"61",X"28",X"BF",X"CD",
+		X"5B",X"33",X"18",X"BA",X"DD",X"7E",X"09",X"C6",X"04",X"DD",X"77",X"09",X"30",X"B0",X"DD",X"36",
+		X"09",X"80",X"DD",X"34",X"08",X"21",X"CA",X"42",X"DD",X"7E",X"08",X"FE",X"05",X"20",X"04",X"CB",
+		X"FE",X"18",X"9B",X"CB",X"F6",X"18",X"97",X"DD",X"34",X"09",X"20",X"92",X"DD",X"CB",X"00",X"C6",
+		X"FD",X"35",X"06",X"AF",X"77",X"23",X"77",X"23",X"77",X"23",X"77",X"18",X"81",X"DD",X"34",X"09",
+		X"DD",X"7E",X"09",X"FE",X"8D",X"C2",X"2E",X"34",X"DD",X"36",X"09",X"C8",X"DD",X"CB",X"01",X"DE",
+		X"CB",X"61",X"28",X"03",X"CD",X"5B",X"33",X"23",X"E5",X"23",X"36",X"07",X"23",X"7E",X"CB",X"48",
+		X"20",X"05",X"21",X"F5",X"34",X"18",X"03",X"21",X"01",X"35",X"06",X"04",X"BE",X"30",X"06",X"23",
+		X"23",X"23",X"10",X"F8",X"76",X"23",X"5E",X"23",X"4E",X"E1",X"73",X"06",X"00",X"16",X"00",X"CD",
+		X"CC",X"06",X"C3",X"2E",X"34",X"D0",X"32",X"05",X"A0",X"31",X"04",X"70",X"30",X"03",X"00",X"1B",
+		X"02",X"D0",X"33",X"10",X"A0",X"32",X"05",X"70",X"31",X"04",X"00",X"30",X"03",X"3A",X"BF",X"42",
+		X"B7",X"C0",X"C5",X"D5",X"E5",X"DD",X"E5",X"DD",X"46",X"05",X"DD",X"4E",X"04",X"C5",X"DD",X"E1",
+		X"46",X"23",X"7E",X"E6",X"C0",X"4F",X"20",X"1B",X"78",X"FE",X"E0",X"28",X"64",X"3E",X"E0",X"32",
+		X"C0",X"42",X"3E",X"10",X"32",X"C1",X"42",X"11",X"C0",X"FF",X"ED",X"53",X"C2",X"42",X"DD",X"7E",
+		X"C0",X"18",X"19",X"78",X"FE",X"10",X"28",X"49",X"3E",X"10",X"32",X"C0",X"42",X"3E",X"F0",X"32",
+		X"C1",X"42",X"11",X"40",X"00",X"ED",X"53",X"C2",X"42",X"DD",X"7E",X"40",X"FE",X"50",X"28",X"31",
+		X"FE",X"4E",X"28",X"2D",X"CD",X"C9",X"28",X"E6",X"03",X"20",X"26",X"3E",X"15",X"B1",X"77",X"23",
+		X"36",X"07",X"DD",X"22",X"C4",X"42",X"DD",X"E1",X"DD",X"CB",X"01",X"CE",X"DD",X"36",X"02",X"01",
+		X"DD",X"36",X"08",X"02",X"DD",X"36",X"09",X"FF",X"DD",X"22",X"C6",X"42",X"3E",X"01",X"32",X"BF",
+		X"42",X"DD",X"E1",X"E1",X"D1",X"C1",X"C9",X"3A",X"BF",X"42",X"B7",X"C8",X"3A",X"8E",X"42",X"E6",
+		X"43",X"C0",X"DD",X"2A",X"C6",X"42",X"DD",X"35",X"09",X"C0",X"DD",X"36",X"09",X"78",X"DD",X"35",
+		X"08",X"CA",X"5F",X"36",X"DD",X"66",X"07",X"DD",X"6E",X"06",X"46",X"23",X"23",X"23",X"4E",X"DD",
+		X"21",X"60",X"42",X"3E",X"1D",X"57",X"3A",X"C1",X"42",X"FE",X"10",X"28",X"02",X"CB",X"FA",X"7A",
+		X"32",X"C9",X"42",X"21",X"CB",X"42",X"CB",X"C6",X"AF",X"32",X"C8",X"42",X"ED",X"5B",X"C2",X"42",
+		X"CD",X"EB",X"35",X"3A",X"C8",X"42",X"B7",X"C8",X"C3",X"84",X"0C",X"3A",X"C1",X"42",X"80",X"47",
+		X"2A",X"C4",X"42",X"19",X"22",X"C4",X"42",X"3A",X"C9",X"42",X"DD",X"70",X"00",X"DD",X"77",X"01",
+		X"DD",X"36",X"02",X"07",X"DD",X"71",X"03",X"3C",X"32",X"C9",X"42",X"CD",X"38",X"36",X"3A",X"C9",
+		X"42",X"FE",X"20",X"C8",X"FE",X"A0",X"C8",X"3A",X"C0",X"42",X"B8",X"C8",X"19",X"CD",X"2B",X"36",
+		X"D8",X"DD",X"23",X"DD",X"23",X"DD",X"23",X"DD",X"23",X"18",X"C0",X"7E",X"FE",X"50",X"28",X"06",
+		X"FE",X"4E",X"28",X"02",X"A7",X"C9",X"37",X"C9",X"C5",X"E5",X"3A",X"5C",X"42",X"CD",X"55",X"36",
+		X"30",X"10",X"3A",X"5F",X"42",X"41",X"CD",X"55",X"36",X"30",X"07",X"3A",X"C8",X"42",X"3C",X"32",
+		X"C8",X"42",X"E1",X"C1",X"C9",X"B8",X"30",X"03",X"67",X"78",X"44",X"90",X"FE",X"09",X"C9",X"C5",
+		X"E5",X"DD",X"E5",X"AF",X"32",X"BF",X"42",X"DD",X"2A",X"C6",X"42",X"DD",X"CB",X"01",X"8E",X"DD",
+		X"36",X"08",X"00",X"DD",X"66",X"07",X"DD",X"6E",X"06",X"23",X"23",X"36",X"06",X"21",X"6B",X"42",
+		X"06",X"0C",X"CD",X"69",X"0A",X"DD",X"E1",X"E1",X"C1",X"C9",X"3A",X"CA",X"42",X"CB",X"47",X"20",
+		X"0C",X"3A",X"CC",X"42",X"CB",X"47",X"20",X"05",X"3A",X"8D",X"42",X"B7",X"C8",X"FD",X"21",X"CA",
+		X"42",X"DD",X"21",X"D2",X"42",X"16",X"00",X"1E",X"00",X"FD",X"CB",X"00",X"3E",X"38",X"38",X"FD",
+		X"CB",X"02",X"3E",X"38",X"1A",X"01",X"0E",X"00",X"DD",X"09",X"14",X"7A",X"FE",X"08",X"20",X"04",
+		X"FD",X"23",X"18",X"E5",X"FE",X"10",X"20",X"E1",X"7B",X"FE",X"00",X"CC",X"97",X"37",X"C9",X"DD",
+		X"6E",X"02",X"DD",X"66",X"03",X"DD",X"35",X"04",X"28",X"14",X"01",X"06",X"00",X"A7",X"ED",X"42",
+		X"06",X"0B",X"CD",X"C0",X"37",X"18",X"CE",X"FD",X"CB",X"02",X"3E",X"CD",X"8A",X"37",X"7E",X"FE",
+		X"06",X"D2",X"7F",X"37",X"FE",X"00",X"20",X"08",X"23",X"7E",X"FE",X"00",X"28",X"B7",X"18",X"EB",
+		X"FE",X"01",X"28",X"49",X"FE",X"02",X"20",X"30",X"23",X"7E",X"CB",X"BF",X"FE",X"00",X"28",X"3D",
+		X"DD",X"4E",X"05",X"47",X"E6",X"0F",X"28",X"0A",X"78",X"E6",X"F0",X"28",X"0E",X"DD",X"70",X"05",
+		X"18",X"2B",X"79",X"E6",X"0F",X"4F",X"78",X"E6",X"F0",X"18",X"07",X"79",X"E6",X"F0",X"4F",X"78",
+		X"E6",X"0F",X"B1",X"DD",X"77",X"05",X"18",X"15",X"FE",X"03",X"20",X"14",X"23",X"7E",X"DD",X"77",
+		X"0B",X"23",X"7E",X"DD",X"77",X"0C",X"23",X"7E",X"E6",X"0F",X"DD",X"77",X"0D",X"23",X"18",X"9E",
+		X"FE",X"04",X"20",X"17",X"23",X"7E",X"E6",X"1F",X"DD",X"77",X"08",X"23",X"7E",X"E6",X"1F",X"DD",
+		X"77",X"09",X"23",X"7E",X"E6",X"1F",X"DD",X"77",X"0A",X"18",X"E2",X"23",X"7E",X"E6",X"1F",X"DD",
+		X"77",X"06",X"23",X"7E",X"E6",X"3F",X"CB",X"FF",X"CB",X"F7",X"DD",X"77",X"07",X"18",X"CE",X"06",
+		X"0E",X"CD",X"C0",X"37",X"CD",X"FF",X"37",X"C3",X"B5",X"36",X"DD",X"6E",X"00",X"DD",X"75",X"02",
+		X"DD",X"66",X"01",X"DD",X"74",X"03",X"C9",X"0E",X"08",X"AF",X"CD",X"A4",X"37",X"0C",X"CD",X"A4",
+		X"37",X"0C",X"18",X"00",X"F5",X"C5",X"32",X"00",X"48",X"32",X"00",X"4A",X"06",X"49",X"02",X"32",
+		X"03",X"48",X"32",X"00",X"48",X"4F",X"02",X"32",X"01",X"48",X"32",X"00",X"48",X"C1",X"F1",X"C9",
+		X"7B",X"FE",X"00",X"20",X"2B",X"1C",X"0E",X"00",X"7E",X"CD",X"A4",X"37",X"23",X"0C",X"79",X"FE",
+		X"06",X"20",X"F5",X"DD",X"75",X"02",X"DD",X"74",X"03",X"DD",X"E5",X"E1",X"D5",X"11",X"06",X"00",
+		X"19",X"D1",X"0E",X"06",X"7E",X"CD",X"A4",X"37",X"0C",X"23",X"79",X"B8",X"20",X"F6",X"18",X"0A",
+		X"01",X"06",X"00",X"09",X"DD",X"75",X"02",X"DD",X"74",X"03",X"FD",X"CB",X"02",X"FE",X"C9",X"E5",
+		X"DD",X"7E",X"05",X"E6",X"0F",X"21",X"24",X"38",X"06",X"00",X"4F",X"09",X"7E",X"47",X"DD",X"4E",
+		X"05",X"CB",X"39",X"CB",X"39",X"CB",X"39",X"CB",X"39",X"0D",X"28",X"04",X"80",X"0D",X"20",X"FC",
+		X"DD",X"77",X"04",X"E1",X"C9",X"01",X"02",X"03",X"04",X"06",X"08",X"0C",X"10",X"18",X"20",X"06",
+		X"06",X"06",X"06",X"06",X"06",X"00",X"10",X"00",X"10",X"00",X"46",X"04",X"B8",X"05",X"05",X"05",
+		X"00",X"05",X"04",X"80",X"10",X"80",X"10",X"00",X"46",X"04",X"B8",X"05",X"05",X"05",X"00",X"05",
+		X"04",X"00",X"11",X"00",X"11",X"00",X"46",X"04",X"B8",X"05",X"05",X"05",X"00",X"05",X"04",X"80",
+		X"11",X"80",X"11",X"00",X"46",X"04",X"B8",X"05",X"05",X"05",X"00",X"05",X"04",X"00",X"12",X"00",
+		X"12",X"00",X"46",X"04",X"B8",X"05",X"05",X"05",X"00",X"05",X"04",X"00",X"13",X"00",X"13",X"00",
+		X"46",X"04",X"B8",X"05",X"05",X"05",X"00",X"05",X"04",X"00",X"14",X"00",X"14",X"00",X"46",X"04",
+		X"B8",X"05",X"05",X"05",X"00",X"05",X"04",X"00",X"15",X"00",X"15",X"00",X"46",X"04",X"B8",X"05",
+		X"05",X"05",X"00",X"05",X"04",X"00",X"16",X"00",X"16",X"00",X"46",X"04",X"B8",X"05",X"05",X"05",
+		X"00",X"05",X"04",X"80",X"16",X"80",X"16",X"00",X"46",X"04",X"B8",X"05",X"05",X"05",X"00",X"05",
+		X"04",X"E0",X"17",X"E0",X"17",X"00",X"46",X"04",X"B8",X"05",X"05",X"05",X"00",X"05",X"04",X"00",
+		X"18",X"00",X"18",X"00",X"46",X"04",X"B8",X"05",X"05",X"05",X"00",X"05",X"04",X"00",X"19",X"00",
+		X"19",X"00",X"46",X"04",X"B8",X"05",X"05",X"05",X"00",X"05",X"04",X"80",X"1B",X"80",X"1B",X"00",
+		X"46",X"04",X"B8",X"05",X"05",X"05",X"00",X"05",X"04",X"00",X"1C",X"00",X"1C",X"00",X"46",X"04",
+		X"B8",X"05",X"05",X"05",X"00",X"05",X"04",X"00",X"1E",X"00",X"1E",X"00",X"46",X"04",X"B8",X"05",
+		X"05",X"05",X"00",X"05",X"04",X"CC",X"50",X"18",X"53",X"9A",X"50",X"C8",X"52",X"58",X"42",X"A0",
+		X"70",X"6E",X"51",X"78",X"42",X"40",X"A0",X"F4",X"52",X"7C",X"42",X"30",X"40",X"28",X"53",X"58",
+		X"42",X"C0",X"60",X"EC",X"50",X"78",X"42",X"90",X"B0",X"B6",X"51",X"7C",X"42",X"40",X"80",X"F0",
+		X"52",X"09",X"16",X"04",X"07",X"3C",X"04",X"E8",X"50",X"00",X"40",X"42",X"C0",X"40",X"12",X"F6",
+		X"50",X"01",X"44",X"42",X"C0",X"B0",X"80",X"7A",X"52",X"00",X"48",X"42",X"60",X"D0",X"10",X"2E",
+		X"53",X"00",X"4C",X"42",X"30",X"70",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"09",X"16",X"04",X"07",X"37",X"04",X"AC",X"51",X"01",X"40",X"42",X"90",X"60",X"82",X"38",
+		X"51",X"01",X"44",X"42",X"B0",X"C0",X"40",X"F8",X"52",X"00",X"48",X"42",X"40",X"C0",X"12",X"2A",
+		X"53",X"00",X"4C",X"42",X"30",X"50",X"20",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"07",X"11",X"04",X"07",X"32",X"05",X"68",X"51",X"00",X"40",X"42",X"A0",X"40",X"20",X"78",
+		X"51",X"01",X"44",X"42",X"A0",X"C0",X"80",X"78",X"52",X"00",X"48",X"42",X"60",X"C0",X"12",X"6C",
+		X"52",X"01",X"4C",X"42",X"60",X"60",X"42",X"32",X"53",X"00",X"50",X"42",X"30",X"90",X"10",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"07",X"11",X"04",X"07",X"2D",X"05",X"A8",X"51",X"01",X"40",X"42",X"90",X"40",X"82",X"6E",
+		X"51",X"00",X"44",X"42",X"A0",X"70",X"20",X"FA",X"51",X"00",X"48",X"42",X"80",X"D0",X"12",X"38",
+		X"53",X"01",X"4C",X"42",X"30",X"C0",X"40",X"AA",X"52",X"00",X"50",X"42",X"50",X"50",X"12",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"06",X"0E",X"04",X"07",X"1E",X"06",X"A6",X"51",X"00",X"40",X"42",X"90",X"30",X"12",X"34",
+		X"51",X"01",X"44",X"42",X"B0",X"A0",X"80",X"F4",X"51",X"00",X"48",X"42",X"80",X"A0",X"22",X"AA",
+		X"52",X"01",X"4C",X"42",X"50",X"50",X"40",X"F0",X"52",X"00",X"50",X"42",X"40",X"80",X"12",X"BA",
+		X"52",X"01",X"54",X"42",X"50",X"D0",X"80",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"06",X"0E",X"04",X"07",X"0F",X"06",X"68",X"51",X"00",X"40",X"42",X"A0",X"40",X"10",X"EE",
+		X"51",X"01",X"44",X"42",X"80",X"70",X"82",X"30",X"51",X"00",X"48",X"42",X"B0",X"80",X"22",X"38",
+		X"52",X"01",X"4C",X"42",X"70",X"C0",X"40",X"A8",X"52",X"01",X"50",X"42",X"50",X"40",X"42",X"34",
+		X"53",X"00",X"54",X"42",X"30",X"A0",X"12",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"06",X"0E",X"04",X"07",X"01",X"06",X"6C",X"51",X"00",X"40",X"42",X"A0",X"60",X"10",X"72",
+		X"51",X"00",X"44",X"42",X"A0",X"90",X"22",X"F6",X"51",X"01",X"48",X"42",X"80",X"B0",X"82",X"68",
+		X"52",X"01",X"4C",X"42",X"60",X"40",X"42",X"AE",X"52",X"00",X"50",X"42",X"50",X"70",X"12",X"B8",
+		X"52",X"00",X"54",X"42",X"50",X"C0",X"22",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"06",X"0E",X"04",X"07",X"01",X"06",X"E8",X"51",X"01",X"40",X"42",X"80",X"40",X"42",X"70",
+		X"51",X"01",X"44",X"42",X"A0",X"80",X"82",X"36",X"51",X"00",X"48",X"42",X"B0",X"B0",X"22",X"6C",
+		X"52",X"01",X"4C",X"42",X"60",X"60",X"42",X"F4",X"52",X"00",X"50",X"42",X"40",X"A0",X"12",X"76",
+		X"52",X"01",X"54",X"42",X"60",X"B0",X"82",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"BF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"4F",
+		X"FF",X"F7",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"7F",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A0",
+		X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"D7",
+		X"FF",X"F7",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"4C",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"7F",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A0",
+		X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",
+		X"FF",X"F7",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"4E",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"3F",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A0",
+		X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",
+		X"FF",X"F7",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"BF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"5F",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"7F",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A0",
+		X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",
+		X"FF",X"F7",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"5C",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"DF",X"7F",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",
+		X"00",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"80");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_h.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_h.vhd
new file mode 100644
index 00000000..12e8a1f4
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_h.vhd	
@@ -0,0 +1,278 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ZIGZAG_1H is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(11 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ZIGZAG_1H is
+	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
+		X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00",
+		X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00",
+		X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00",
+		X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00",
+		X"C0",X"80",X"80",X"C0",X"C0",X"80",X"80",X"C0",X"03",X"01",X"01",X"03",X"03",X"01",X"01",X"03",
+		X"FF",X"99",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"99",X"FF",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",
+		X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00",X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00",
+		X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00",X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00",
+		X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00",X"9E",X"9E",X"92",X"82",X"C6",X"7C",X"38",X"00",
+		X"FE",X"FE",X"10",X"10",X"10",X"FE",X"FE",X"00",X"82",X"82",X"FE",X"FE",X"82",X"82",X"00",X"00",
+		X"FC",X"FE",X"02",X"02",X"02",X"06",X"04",X"00",X"82",X"C6",X"6E",X"3C",X"18",X"FE",X"FE",X"00",
+		X"02",X"02",X"02",X"02",X"FE",X"FE",X"00",X"00",X"FE",X"FE",X"70",X"38",X"70",X"FE",X"FE",X"00",
+		X"FE",X"FE",X"1C",X"38",X"70",X"FE",X"FE",X"00",X"7C",X"FE",X"82",X"82",X"82",X"FE",X"7C",X"00",
+		X"70",X"F8",X"88",X"88",X"88",X"FE",X"FE",X"00",X"7A",X"FC",X"8E",X"8A",X"82",X"FE",X"7C",X"00",
+		X"72",X"F6",X"9E",X"8C",X"88",X"FE",X"FE",X"00",X"0C",X"5E",X"D2",X"92",X"92",X"F6",X"64",X"00",
+		X"80",X"80",X"FE",X"FE",X"80",X"80",X"00",X"00",X"FC",X"FE",X"02",X"02",X"02",X"FE",X"FC",X"00",
+		X"F0",X"F8",X"1C",X"0E",X"1C",X"F8",X"F0",X"00",X"F8",X"FE",X"1C",X"38",X"1C",X"FE",X"F8",X"00",
+		X"C6",X"EE",X"7C",X"38",X"7C",X"EE",X"C6",X"00",X"C0",X"F0",X"1E",X"1E",X"F0",X"C0",X"00",X"00",
+		X"C2",X"E2",X"F2",X"BA",X"9E",X"8E",X"86",X"00",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"01",X"9B",X"FF",X"FF",X"9B",X"01",X"00",X"00",X"00",X"00",X"00",
+		X"3F",X"1F",X"1F",X"3F",X"3F",X"7F",X"FF",X"FF",X"FF",X"FF",X"7F",X"3F",X"3F",X"1F",X"1F",X"3F",
+		X"0F",X"07",X"07",X"0F",X"0F",X"1F",X"BF",X"FF",X"FF",X"BF",X"1F",X"0F",X"0F",X"07",X"07",X"0F",
+		X"00",X"00",X"00",X"00",X"00",X"80",X"D9",X"FF",X"FF",X"D9",X"80",X"00",X"00",X"00",X"00",X"00",
+		X"FC",X"F8",X"F8",X"FC",X"FC",X"FE",X"FF",X"FF",X"FF",X"FF",X"FE",X"FC",X"FC",X"F8",X"F8",X"FC",
+		X"F0",X"E0",X"E0",X"F0",X"F0",X"F8",X"FD",X"FF",X"FF",X"FD",X"F8",X"F0",X"F0",X"E0",X"E0",X"F0",
+		X"C0",X"80",X"80",X"C0",X"C0",X"80",X"C0",X"E0",X"03",X"01",X"01",X"03",X"03",X"01",X"03",X"07",
+		X"C0",X"E0",X"F9",X"FF",X"FF",X"FF",X"FF",X"FF",X"03",X"07",X"9F",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"C0",X"80",X"C0",X"E0",X"F9",X"FF",X"FF",X"FF",X"03",X"01",X"03",X"07",X"9F",X"FF",X"FF",X"FF",
+		X"E0",X"C0",X"80",X"C0",X"C0",X"80",X"80",X"C0",X"07",X"03",X"01",X"03",X"03",X"01",X"01",X"03",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"F9",X"E0",X"C0",X"FF",X"FF",X"FF",X"FF",X"FF",X"9F",X"07",X"03",
+		X"FF",X"FF",X"FF",X"F9",X"E0",X"C0",X"80",X"C0",X"FF",X"FF",X"FF",X"9F",X"07",X"03",X"01",X"03",
+		X"C0",X"80",X"80",X"C0",X"C0",X"E0",X"F9",X"FF",X"03",X"01",X"01",X"03",X"03",X"07",X"9F",X"FF",
+		X"FF",X"F9",X"E0",X"C0",X"C0",X"80",X"80",X"C0",X"FF",X"9F",X"07",X"03",X"03",X"01",X"01",X"03",
+		X"C0",X"80",X"80",X"C0",X"C0",X"80",X"80",X"C0",X"03",X"01",X"01",X"03",X"03",X"01",X"01",X"03",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"99",X"FF",X"FF",X"99",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"02",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"60",X"30",X"18",X"0C",X"00",X"00",X"00",
+		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"00",X"00",X"40",X"60",X"C0",X"80",X"C0",X"C0",
+		X"0F",X"3B",X"10",X"00",X"00",X"00",X"00",X"00",X"C0",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"01",X"05",X"07",X"27",X"3F",X"00",X"00",X"00",X"00",X"08",X"D8",X"E0",X"C0",
+		X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"01",X"05",X"02",X"07",X"2F",X"3B",X"00",X"00",X"00",X"88",X"C8",X"F0",X"C0",X"C0",
+		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"80",X"80",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"01",X"01",X"13",X"1F",X"00",X"00",X"00",X"00",X"40",X"40",X"E4",X"FC",
+		X"03",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"E0",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"38",X"70",X"F7",X"FF",X"00",X"00",X"FC",X"20",X"70",X"E0",X"FC",X"F0",
+		X"F7",X"70",X"38",X"00",X"00",X"00",X"00",X"00",X"FC",X"E0",X"70",X"20",X"FC",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"06",X"0C",X"7F",X"00",X"00",X"00",X"18",X"08",X"1C",X"FE",X"F8",
+		X"0C",X"06",X"00",X"00",X"00",X"00",X"00",X"00",X"FE",X"1C",X"08",X"18",X"00",X"00",X"00",X"00",
+		X"02",X"07",X"07",X"0F",X"0F",X"0F",X"1F",X"18",X"00",X"00",X"00",X"80",X"80",X"80",X"C0",X"C0",
+		X"17",X"37",X"38",X"3F",X"70",X"7F",X"7F",X"00",X"40",X"60",X"E0",X"E0",X"70",X"F0",X"F0",X"00",
+		X"02",X"02",X"07",X"07",X"0F",X"0F",X"1F",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"C0",X"00",
+		X"C3",X"FF",X"FF",X"7E",X"00",X"00",X"C3",X"C3",X"00",X"00",X"7E",X"FF",X"FF",X"C3",X"C3",X"C3",
+		X"00",X"01",X"03",X"07",X"03",X"07",X"0F",X"3F",X"80",X"80",X"D8",X"F8",X"F8",X"F0",X"F0",X"F0",
+		X"1F",X"1F",X"1F",X"0F",X"03",X"07",X"07",X"01",X"F8",X"F8",X"F0",X"E0",X"F8",X"FC",X"78",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"90",
+		X"07",X"02",X"02",X"08",X"00",X"00",X"00",X"00",X"C0",X"80",X"A0",X"10",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"04",X"24",X"04",X"4E",X"27",X"00",X"00",X"20",X"40",X"11",X"80",X"A4",X"C8",
+		X"07",X"03",X"25",X"00",X"08",X"00",X"00",X"00",X"C0",X"20",X"90",X"A0",X"20",X"50",X"00",X"00",
+		X"00",X"00",X"42",X"20",X"04",X"0F",X"E7",X"3F",X"00",X"20",X"44",X"C8",X"80",X"80",X"D0",X"EC",
+		X"07",X"07",X"0D",X"1D",X"29",X"42",X"01",X"00",X"C0",X"A0",X"B0",X"88",X"44",X"20",X"10",X"08",
+		X"3C",X"62",X"95",X"A5",X"A5",X"99",X"42",X"3F",X"C0",X"20",X"20",X"20",X"C0",X"00",X"C0",X"20",
+		X"0A",X"0A",X"0E",X"00",X"00",X"0F",X"04",X"00",X"20",X"20",X"40",X"00",X"20",X"E0",X"20",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"00",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"08",X"0D",X"0B",X"09",X"08",X"00",X"C0",X"00",X"C0",X"20",X"20",X"20",X"20",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"06",X"09",X"09",X"09",X"06",X"00",X"C0",X"00",X"C0",X"20",X"20",X"20",X"C0",X"00",
+		X"00",X"00",X"00",X"00",X"07",X"08",X"08",X"07",X"00",X"00",X"00",X"00",X"C0",X"20",X"20",X"C0",
+		X"00",X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"00",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",
+		X"08",X"07",X"00",X"00",X"0F",X"04",X"00",X"00",X"20",X"C0",X"00",X"20",X"E0",X"20",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"20",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"00",X"0F",X"40",X"20",X"10",X"20",X"C0",X"00",X"40",X"E0",X"40",X"40",X"40",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"09",X"09",X"06",X"20",X"C0",X"00",X"C0",X"20",X"20",X"20",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"00",X"09",X"09",X"09",X"07",X"20",X"C0",X"00",X"C0",X"20",X"20",X"20",X"C0",
+		X"00",X"00",X"0F",X"04",X"00",X"00",X"00",X"00",X"00",X"20",X"E0",X"20",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"20",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",
+		X"00",X"0C",X"0B",X"09",X"00",X"00",X"00",X"00",X"00",X"C0",X"20",X"20",X"20",X"40",X"00",X"00",
+		X"FE",X"FC",X"F1",X"C1",X"80",X"AD",X"B7",X"9F",X"0F",X"E3",X"09",X"81",X"01",X"61",X"F1",X"F9",
+		X"C7",X"F0",X"F6",X"EF",X"ED",X"E3",X"F8",X"FF",X"31",X"B1",X"F3",X"E1",X"E1",X"B9",X"79",X"03",
+		X"00",X"00",X"01",X"01",X"00",X"2D",X"37",X"1F",X"00",X"E0",X"08",X"80",X"00",X"60",X"F0",X"F8",
+		X"07",X"00",X"06",X"0F",X"0D",X"03",X"00",X"00",X"30",X"B0",X"F2",X"E0",X"E0",X"B8",X"78",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"02",X"05",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"78",
+		X"0B",X"06",X"01",X"00",X"00",X"00",X"00",X"00",X"86",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"08",X"0C",X"06",X"3A",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"0E",X"1C",X"38",X"10",X"08",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"07",X"00",X"00",X"18",X"10",X"1C",X"0E",X"06",X"32",
+		X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CE",X"02",X"0E",X"1E",X"1C",X"10",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"8C",X"8C",X"58",X"58",X"30",X"30",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"30",X"58",X"58",X"8C",X"8C",X"00",X"00",
+		X"00",X"00",X"00",X"03",X"06",X"06",X"03",X"01",X"00",X"00",X"00",X"E0",X"C0",X"C0",X"E0",X"C0",
+		X"01",X"03",X"06",X"06",X"03",X"00",X"00",X"00",X"C0",X"E0",X"30",X"30",X"E0",X"00",X"00",X"00",
+		X"00",X"00",X"20",X"20",X"10",X"18",X"0C",X"0E",X"00",X"00",X"00",X"20",X"20",X"64",X"CC",X"7C",
+		X"04",X"0C",X"0C",X"04",X"00",X"00",X"00",X"00",X"3C",X"38",X"3C",X"3C",X"0C",X"38",X"00",X"00",
+		X"00",X"00",X"00",X"03",X"07",X"07",X"07",X"02",X"00",X"00",X"38",X"E0",X"E0",X"E4",X"EC",X"40",
+		X"02",X"07",X"07",X"07",X"03",X"00",X"00",X"00",X"40",X"EC",X"E4",X"E0",X"E0",X"38",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"0D",X"02",X"04",
+		X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"02",X"62",X"27",X"10",X"E6",X"92",X"0C",X"68",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"C0",X"61",X"13",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"12",X"04",X"F1",X"52",X"31",X"36",X"05",X"04",X"C0",X"20",X"A0",X"20",X"20",X"40",X"40",X"80",
+		X"05",X"04",X"02",X"01",X"00",X"01",X"01",X"01",X"C0",X"40",X"40",X"40",X"C0",X"C0",X"FC",X"8A",
+		X"01",X"06",X"08",X"00",X"00",X"00",X"00",X"00",X"72",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"08",X"0C",X"02",X"00",X"78",X"20",X"20",X"10",X"10",X"20",X"20",
+		X"13",X"0F",X"E3",X"00",X"00",X"00",X"00",X"00",X"70",X"D0",X"10",X"0C",X"04",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"03",X"04",X"04",X"1C",X"00",X"00",X"00",X"00",X"04",X"B4",X"FC",X"FC",
+		X"1C",X"0D",X"0F",X"07",X"03",X"00",X"00",X"00",X"C0",X"C4",X"94",X"9C",X"8C",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"06",X"09",X"09",X"39",X"00",X"00",X"00",X"00",X"00",X"7C",X"FC",X"F4",
+		X"39",X"1B",X"1F",X"0F",X"07",X"00",X"00",X"00",X"F4",X"3C",X"1C",X"08",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"02",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"40",X"20",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"40",X"40",X"20",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"01",X"01",X"02",X"02",X"40",X"40",X"80",X"80",X"00",X"00",X"00",X"00",
+		X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"40",X"40",X"20",X"20",
+		X"00",X"00",X"00",X"00",X"01",X"01",X"02",X"02",X"40",X"40",X"80",X"80",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"40",X"40",X"20",X"20",
+		X"00",X"00",X"00",X"00",X"01",X"01",X"02",X"02",X"40",X"40",X"80",X"80",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"18",X"04",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"30",X"0C",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",
+		X"30",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"0C",X"03",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"30",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"0C",
+		X"30",X"0C",X"03",X"00",X"00",X"00",X"00",X"00",X"30",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"09",X"00",X"0A",X"00",X"00",X"00",X"00",X"00",X"FE",X"38",X"10",X"10",X"00",X"3C",
+		X"3C",X"3F",X"3F",X"39",X"0F",X"0F",X"00",X"00",X"08",X"08",X"08",X"20",X"20",X"60",X"60",X"00",
+		X"00",X"00",X"00",X"30",X"0C",X"00",X"00",X"00",X"00",X"00",X"38",X"0C",X"00",X"00",X"00",X"38",
+		X"3E",X"3F",X"37",X"3B",X"3F",X"1F",X"00",X"00",X"0C",X"04",X"00",X"20",X"20",X"60",X"60",X"00",
+		X"00",X"0C",X"0C",X"06",X"00",X"00",X"00",X"00",X"0E",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
+		X"00",X"00",X"7C",X"F7",X"C3",X"77",X"1E",X"00",X"01",X"21",X"20",X"20",X"20",X"E0",X"E0",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"12",X"00",X"00",X"00",X"00",X"00",X"01",
+		X"3E",X"7E",X"F3",X"F3",X"CF",X"CF",X"7E",X"38",X"01",X"00",X"30",X"30",X"70",X"70",X"70",X"00",
+		X"00",X"01",X"06",X"0A",X"16",X"1F",X"0E",X"0C",X"00",X"80",X"00",X"00",X"04",X"84",X"C0",X"40",
+		X"0E",X"07",X"07",X"00",X"00",X"00",X"00",X"00",X"C0",X"C4",X"CC",X"E0",X"60",X"10",X"70",X"00",
+		X"06",X"00",X"0E",X"1E",X"36",X"2F",X"3F",X"1E",X"00",X"08",X"0C",X"00",X"00",X"C0",X"E0",X"E2",
+		X"1C",X"0E",X"07",X"03",X"00",X"00",X"00",X"00",X"66",X"E6",X"E0",X"F0",X"3C",X"12",X"06",X"00",
+		X"00",X"30",X"10",X"78",X"FE",X"EF",X"C7",X"6E",X"00",X"03",X"03",X"03",X"00",X"80",X"C0",X"E3",
+		X"7E",X"38",X"1E",X"0E",X"07",X"03",X"00",X"00",X"F3",X"37",X"F7",X"E0",X"EC",X"F6",X"36",X"06",
+		X"00",X"00",X"00",X"00",X"78",X"FE",X"DF",X"8F",X"00",X"00",X"01",X"01",X"01",X"00",X"80",X"E0",
+		X"DC",X"F8",X"78",X"3C",X"3C",X"1F",X"0F",X"07",X"F1",X"F1",X"39",X"39",X"F8",X"F0",X"E0",X"9C",
+		X"00",X"00",X"00",X"08",X"00",X"08",X"00",X"00",X"00",X"00",X"84",X"1C",X"80",X"10",X"18",X"0C",
+		X"00",X"0E",X"1F",X"19",X"09",X"07",X"00",X"00",X"04",X"40",X"70",X"78",X"70",X"38",X"30",X"00",
+		X"00",X"00",X"00",X"02",X"04",X"02",X"04",X"02",X"00",X"00",X"00",X"38",X"18",X"0C",X"04",X"00",
+		X"00",X"00",X"0E",X"1F",X"13",X"09",X"07",X"00",X"38",X"18",X"0C",X"64",X"C0",X"60",X"00",X"00",
+		X"00",X"0F",X"1F",X"19",X"1F",X"1F",X"19",X"1F",X"00",X"84",X"C4",X"C4",X"9C",X"84",X"C0",X"C4",
+		X"1F",X"1F",X"0F",X"06",X"06",X"00",X"00",X"00",X"C4",X"9C",X"04",X"20",X"20",X"E0",X"00",X"00",
+		X"00",X"3E",X"7F",X"67",X"7E",X"7E",X"67",X"7F",X"00",X"00",X"40",X"60",X"30",X"00",X"00",X"40",
+		X"7F",X"7E",X"3C",X"18",X"18",X"00",X"00",X"00",X"60",X"30",X"00",X"80",X"80",X"E0",X"00",X"00",
+		X"00",X"00",X"30",X"1C",X"17",X"09",X"07",X"00",X"00",X"00",X"F8",X"CC",X"64",X"24",X"24",X"68",
+		X"00",X"07",X"09",X"17",X"1C",X"30",X"00",X"00",X"68",X"2C",X"24",X"64",X"CC",X"F8",X"00",X"00",
+		X"00",X"00",X"00",X"0F",X"09",X"33",X"3C",X"00",X"00",X"00",X"3C",X"24",X"24",X"6C",X"68",X"C8",
+		X"00",X"3C",X"33",X"09",X"0F",X"00",X"00",X"00",X"C8",X"68",X"6C",X"24",X"24",X"3C",X"00",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"00",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",X"00",
+		X"00",X"01",X"03",X"07",X"03",X"07",X"0F",X"3F",X"80",X"80",X"D8",X"F8",X"F8",X"F0",X"F0",X"F0",
+		X"1F",X"1F",X"1F",X"0F",X"03",X"07",X"07",X"01",X"F8",X"F8",X"F0",X"E0",X"F8",X"FC",X"78",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"1F",X"04",X"0E",X"0C",X"3E",X"30",X"60",
+		X"00",X"00",X"01",X"01",X"01",X"03",X"02",X"02",X"C0",X"C0",X"80",X"80",X"00",X"00",X"00",X"00",
+		X"0D",X"08",X"00",X"00",X"00",X"00",X"00",X"07",X"FC",X"FD",X"7B",X"76",X"EF",X"77",X"7B",X"FE",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3D",X"18",X"1E",X"1E",X"3D",X"7D",X"0E",X"07",
+		X"00",X"00",X"08",X"08",X"38",X"1C",X"2F",X"07",X"00",X"08",X"0C",X"1E",X"18",X"1B",X"93",X"E7",
+		X"01",X"00",X"19",X"06",X"00",X"00",X"11",X"1F",X"FE",X"BE",X"F0",X"EF",X"F0",X"FC",X"FD",X"F1",
+		X"07",X"08",X"08",X"08",X"07",X"00",X"09",X"0A",X"C0",X"20",X"20",X"20",X"C0",X"00",X"C0",X"20",
+		X"0A",X"0A",X"0E",X"00",X"00",X"0F",X"04",X"00",X"20",X"20",X"40",X"00",X"20",X"E0",X"20",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"00",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",X"00",
+		X"00",X"00",X"00",X"0A",X"0E",X"03",X"00",X"00",X"04",X"60",X"88",X"F8",X"F8",X"1C",X"0C",X"04",
+		X"00",X"00",X"00",X"00",X"06",X"01",X"00",X"00",X"00",X"00",X"66",X"0C",X"7C",X"98",X"70",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"04",X"0C",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"12",X"04",X"04",X"02",X"00",X"02",X"00",
+		X"00",X"00",X"00",X"00",X"07",X"08",X"08",X"07",X"00",X"00",X"00",X"00",X"C0",X"20",X"20",X"C0",
+		X"00",X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"00",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",
+		X"08",X"07",X"00",X"00",X"0F",X"04",X"00",X"00",X"20",X"C0",X"00",X"20",X"E0",X"20",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"20",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"00",X"0F",X"04",X"02",X"01",X"20",X"C0",X"00",X"40",X"E0",X"40",X"40",X"40",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"09",X"09",X"06",X"20",X"C0",X"00",X"C0",X"20",X"20",X"20",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"00",X"09",X"09",X"09",X"07",X"20",X"C0",X"00",X"C0",X"20",X"20",X"20",X"C0",
+		X"00",X"00",X"0F",X"04",X"00",X"00",X"00",X"00",X"00",X"20",X"E0",X"20",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"20",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",
+		X"00",X"0C",X"0B",X"09",X"00",X"00",X"00",X"00",X"00",X"C0",X"20",X"20",X"20",X"40",X"00",X"00",
+		X"FE",X"FC",X"F1",X"C1",X"80",X"AD",X"B7",X"9F",X"0F",X"E3",X"09",X"81",X"01",X"61",X"F1",X"F9",
+		X"C7",X"F0",X"F6",X"EF",X"ED",X"E3",X"F8",X"FF",X"31",X"B1",X"F3",X"E1",X"E1",X"B9",X"79",X"03",
+		X"00",X"00",X"01",X"01",X"00",X"2D",X"37",X"1F",X"00",X"E0",X"08",X"80",X"00",X"60",X"F0",X"F8",
+		X"07",X"00",X"06",X"0F",X"0D",X"03",X"00",X"00",X"30",X"B0",X"F2",X"E0",X"E0",X"B8",X"78",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"02",X"05",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"78",
+		X"0B",X"06",X"01",X"00",X"00",X"00",X"00",X"00",X"86",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"08",X"0C",X"06",X"3A",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"0E",X"1C",X"38",X"10",X"08",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"07",X"00",X"00",X"18",X"10",X"1C",X"0E",X"06",X"32",
+		X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"CE",X"02",X"0E",X"1E",X"1C",X"10",X"00",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"08",X"0D",X"0B",X"09",X"08",X"00",X"C0",X"00",X"C0",X"20",X"20",X"20",X"40",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"00",X"0F",X"04",X"02",X"01",X"00",X"C0",X"00",X"40",X"E0",X"40",X"40",X"40",X"C0",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"09",X"0A",X"0A",X"0A",X"0E",X"00",X"C0",X"00",X"C0",X"20",X"20",X"20",X"40",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"07",X"08",X"08",X"07",X"00",X"0F",X"C0",X"00",X"C0",X"20",X"20",X"C0",X"00",X"E0",
+		X"00",X"00",X"03",X"0F",X"1F",X"00",X"00",X"20",X"00",X"00",X"80",X"E0",X"F0",X"18",X"18",X"38",
+		X"63",X"C7",X"FF",X"C7",X"62",X"2E",X"00",X"00",X"C0",X"80",X"98",X"F4",X"1C",X"04",X"00",X"00",
+		X"00",X"01",X"03",X"07",X"0F",X"00",X"00",X"00",X"70",X"FC",X"26",X"30",X"38",X"2C",X"2C",X"3C",
+		X"01",X"03",X"03",X"03",X"01",X"07",X"00",X"00",X"C8",X"C0",X"FC",X"FC",X"08",X"38",X"00",X"00",
+		X"00",X"00",X"01",X"08",X"18",X"18",X"38",X"38",X"70",X"F8",X"AC",X"20",X"24",X"74",X"FC",X"F0",
+		X"38",X"18",X"19",X"0F",X"07",X"00",X"00",X"00",X"F0",X"90",X"10",X"78",X"28",X"1C",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"08",X"18",X"38",X"78",X"00",X"00",X"00",X"00",X"00",X"04",X"74",X"FC",
+		X"78",X"F8",X"FF",X"D9",X"4F",X"67",X"20",X"00",X"F0",X"F0",X"34",X"34",X"3C",X"30",X"00",X"00",
+		X"00",X"00",X"03",X"0F",X"1F",X"00",X"00",X"00",X"00",X"00",X"80",X"E0",X"F0",X"18",X"18",X"38",
+		X"13",X"37",X"7F",X"37",X"12",X"0E",X"00",X"00",X"C0",X"80",X"98",X"F4",X"1C",X"04",X"00",X"00",
+		X"00",X"00",X"01",X"07",X"0F",X"00",X"00",X"00",X"00",X"00",X"C0",X"F0",X"F8",X"0C",X"0C",X"1C",
+		X"07",X"0F",X"1F",X"0F",X"05",X"07",X"00",X"00",X"F0",X"E0",X"E4",X"F8",X"08",X"38",X"00",X"00",
+		X"00",X"00",X"00",X"08",X"18",X"18",X"38",X"38",X"00",X"20",X"70",X"F8",X"24",X"74",X"FC",X"F0",
+		X"38",X"18",X"19",X"0F",X"07",X"00",X"00",X"00",X"F0",X"90",X"10",X"38",X"28",X"1C",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"08",X"18",X"18",X"38",X"00",X"00",X"00",X"20",X"70",X"FC",X"F4",X"FC",
+		X"38",X"38",X"18",X"18",X"0F",X"07",X"00",X"00",X"F0",X"F0",X"F4",X"94",X"1C",X"20",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"30",X"60",X"E6",
+		X"11",X"31",X"31",X"71",X"71",X"73",X"3E",X"1C",X"FC",X"FC",X"F8",X"F0",X"E0",X"80",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"30",X"33",X"13",X"1A",X"1E",X"1E",
+		X"02",X"06",X"06",X"0E",X"0E",X"0E",X"07",X"03",X"3C",X"3C",X"3C",X"38",X"20",X"70",X"C0",X"80",
+		X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"01",X"00",X"20",X"B0",X"90",X"F0",X"F0",X"F8",X"F8",
+		X"00",X"00",X"00",X"00",X"03",X"01",X"00",X"00",X"F0",X"18",X"0C",X"0C",X"FC",X"F8",X"70",X"00",
+		X"00",X"00",X"00",X"08",X"04",X"02",X"00",X"1C",X"00",X"00",X"80",X"88",X"90",X"20",X"00",X"1C",
+		X"00",X"02",X"04",X"08",X"00",X"00",X"00",X"00",X"00",X"20",X"90",X"88",X"80",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_k.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_k.vhd
new file mode 100644
index 00000000..5afe4576
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ROM/zigzag/rom_k.vhd	
@@ -0,0 +1,278 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity ZIGZAG_1K is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(11 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of ZIGZAG_1K is
+	type rom is array(0 to  4095) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",
+		X"62",X"F2",X"BA",X"9A",X"9E",X"CE",X"46",X"00",X"8C",X"DE",X"F2",X"B2",X"92",X"86",X"04",X"00",
+		X"08",X"FE",X"FE",X"C8",X"68",X"38",X"18",X"00",X"1C",X"BE",X"A2",X"A2",X"A2",X"E6",X"E4",X"00",
+		X"0C",X"9E",X"92",X"92",X"D2",X"7E",X"3C",X"00",X"C0",X"E0",X"B0",X"9E",X"8E",X"C0",X"C0",X"00",
+		X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"02",
+		X"22",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"22",
+		X"22",X"44",X"44",X"22",X"22",X"44",X"44",X"22",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"3E",X"7E",X"C8",X"88",X"C8",X"7E",X"3E",X"00",
+		X"6C",X"FE",X"92",X"92",X"92",X"FE",X"FE",X"00",X"44",X"C6",X"82",X"82",X"C6",X"7C",X"38",X"00",
+		X"38",X"7C",X"C6",X"82",X"82",X"FE",X"FE",X"00",X"82",X"92",X"92",X"92",X"FE",X"FE",X"00",X"00",
+		X"80",X"90",X"90",X"90",X"90",X"FE",X"FE",X"00",X"9E",X"9E",X"92",X"82",X"C6",X"7C",X"38",X"00",
+		X"FE",X"FE",X"10",X"10",X"10",X"FE",X"FE",X"00",X"82",X"82",X"FE",X"FE",X"82",X"82",X"00",X"00",
+		X"FC",X"FE",X"02",X"02",X"02",X"06",X"04",X"00",X"82",X"C6",X"6E",X"3C",X"18",X"FE",X"FE",X"00",
+		X"02",X"02",X"02",X"02",X"FE",X"FE",X"00",X"00",X"FE",X"FE",X"70",X"38",X"70",X"FE",X"FE",X"00",
+		X"FE",X"FE",X"1C",X"38",X"70",X"FE",X"FE",X"00",X"7C",X"FE",X"82",X"82",X"82",X"FE",X"7C",X"00",
+		X"70",X"F8",X"88",X"88",X"88",X"FE",X"FE",X"00",X"7A",X"FC",X"8E",X"8A",X"82",X"FE",X"7C",X"00",
+		X"72",X"F6",X"9E",X"8C",X"88",X"FE",X"FE",X"00",X"0C",X"5E",X"D2",X"92",X"92",X"F6",X"64",X"00",
+		X"80",X"80",X"FE",X"FE",X"80",X"80",X"00",X"00",X"FC",X"FE",X"02",X"02",X"02",X"FE",X"FC",X"00",
+		X"F0",X"F8",X"1C",X"0E",X"1C",X"F8",X"F0",X"00",X"F8",X"FE",X"1C",X"38",X"1C",X"FE",X"F8",X"00",
+		X"C6",X"EE",X"7C",X"38",X"7C",X"EE",X"C6",X"00",X"C0",X"F0",X"1E",X"1E",X"F0",X"C0",X"00",X"00",
+		X"C2",X"E2",X"F2",X"BA",X"9E",X"8E",X"86",X"00",X"10",X"10",X"10",X"10",X"10",X"10",X"10",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"22",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"02",X"04",X"04",X"22",X"22",X"44",X"44",X"22",X"22",X"44",X"44",X"22",X"22",X"04",X"04",X"02",
+		X"02",X"04",X"04",X"02",X"02",X"04",X"04",X"22",X"22",X"04",X"04",X"02",X"02",X"04",X"04",X"02",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"22",X"22",X"40",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"20",X"40",X"40",X"20",X"20",X"44",X"44",X"22",X"22",X"44",X"44",X"20",X"20",X"40",X"40",X"20",
+		X"20",X"40",X"40",X"20",X"20",X"40",X"44",X"22",X"22",X"44",X"40",X"20",X"20",X"40",X"40",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"20",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"02",
+		X"00",X"40",X"40",X"22",X"22",X"44",X"44",X"22",X"02",X"04",X"04",X"22",X"22",X"44",X"44",X"22",
+		X"00",X"00",X"40",X"20",X"20",X"44",X"44",X"22",X"02",X"00",X"00",X"02",X"02",X"44",X"44",X"22",
+		X"20",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"02",
+		X"22",X"44",X"44",X"22",X"22",X"40",X"40",X"00",X"22",X"44",X"44",X"22",X"22",X"04",X"04",X"02",
+		X"22",X"44",X"44",X"20",X"20",X"40",X"00",X"00",X"22",X"44",X"44",X"02",X"02",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"22",X"02",X"00",X"00",X"02",X"02",X"04",X"04",X"22",
+		X"22",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"22",X"04",X"04",X"02",X"02",X"00",X"00",X"02",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"02",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"22",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"01",X"07",X"0E",X"1E",X"1B",X"31",X"00",X"00",X"E0",X"80",X"00",X"00",X"00",X"80",
+		X"30",X"20",X"20",X"00",X"00",X"00",X"00",X"00",X"C0",X"60",X"30",X"18",X"0C",X"00",X"00",X"00",
+		X"22",X"44",X"44",X"22",X"22",X"44",X"44",X"22",X"00",X"00",X"00",X"00",X"00",X"38",X"3C",X"00",
+		X"00",X"00",X"06",X"06",X"06",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",
+		X"00",X"0C",X"1C",X"18",X"10",X"00",X"00",X"00",X"3C",X"1C",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",
+		X"00",X"04",X"0C",X"18",X"18",X"00",X"00",X"00",X"3C",X"1C",X"08",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",
+		X"00",X"0E",X"1C",X"18",X"00",X"00",X"00",X"00",X"00",X"38",X"1C",X"0C",X"00",X"00",X"00",X"00",
+		X"00",X"01",X"07",X"01",X"00",X"00",X"07",X"00",X"00",X"FE",X"FF",X"FE",X"70",X"E0",X"FC",X"00",
+		X"07",X"00",X"00",X"01",X"07",X"01",X"00",X"00",X"FC",X"E0",X"70",X"FE",X"FF",X"FE",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"7E",X"3C",X"08",X"1C",X"FE",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FE",X"1C",X"08",X"3C",X"7E",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"08",X"07",X"00",X"0F",X"00",X"00",X"7F",X"80",X"80",X"00",X"00",X"80",X"00",X"00",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",
+		X"C3",X"FF",X"FF",X"7E",X"00",X"00",X"C3",X"C3",X"00",X"00",X"7E",X"FF",X"FF",X"C3",X"C3",X"C3",
+		X"00",X"00",X"00",X"02",X"05",X"00",X"03",X"0C",X"00",X"00",X"00",X"10",X"50",X"68",X"88",X"C8",
+		X"03",X"0A",X"03",X"01",X"04",X"03",X"00",X"00",X"F4",X"A0",X"C0",X"70",X"40",X"20",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"02",X"0A",X"04",X"00",X"00",X"00",X"00",X"00",X"50",X"A0",X"00",X"20",
+		X"00",X"09",X"01",X"02",X"00",X"00",X"00",X"00",X"38",X"10",X"00",X"40",X"20",X"00",X"00",X"00",
+		X"00",X"02",X"01",X"01",X"01",X"40",X"13",X"01",X"00",X"00",X"00",X"04",X"0C",X"18",X"80",X"90",
+		X"00",X"08",X"00",X"00",X"02",X"04",X"00",X"00",X"82",X"CC",X"00",X"10",X"98",X"84",X"00",X"00",
+		X"08",X"04",X"00",X"02",X"8C",X"0E",X"07",X"0F",X"01",X"12",X"00",X"04",X"00",X"C0",X"C8",X"E0",
+		X"07",X"03",X"21",X"00",X"80",X"21",X"48",X"81",X"C2",X"80",X"01",X"00",X"22",X"00",X"02",X"01",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"20",X"20",X"20",X"C0",X"00",X"C0",X"20",
+		X"0A",X"0A",X"0E",X"00",X"00",X"0F",X"04",X"00",X"20",X"20",X"40",X"00",X"20",X"E0",X"20",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"00",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"08",X"0D",X"0B",X"09",X"08",X"00",X"C0",X"00",X"C0",X"20",X"20",X"20",X"20",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"06",X"09",X"09",X"09",X"06",X"00",X"C0",X"00",X"C0",X"20",X"20",X"20",X"C0",X"00",
+		X"00",X"00",X"00",X"00",X"07",X"08",X"08",X"07",X"00",X"00",X"00",X"00",X"C0",X"20",X"20",X"C0",
+		X"00",X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"00",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",
+		X"08",X"07",X"00",X"00",X"0F",X"04",X"00",X"00",X"20",X"C0",X"00",X"20",X"E0",X"20",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"20",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"00",X"0F",X"40",X"20",X"10",X"20",X"C0",X"00",X"40",X"E0",X"40",X"40",X"40",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"09",X"09",X"06",X"20",X"C0",X"00",X"C0",X"20",X"20",X"20",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"00",X"09",X"09",X"09",X"07",X"20",X"C0",X"00",X"C0",X"20",X"20",X"20",X"C0",
+		X"00",X"00",X"0F",X"04",X"00",X"00",X"00",X"00",X"00",X"20",X"E0",X"20",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"20",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",
+		X"00",X"0C",X"0B",X"09",X"08",X"08",X"00",X"00",X"00",X"C0",X"20",X"20",X"20",X"40",X"00",X"00",
+		X"23",X"43",X"4E",X"3E",X"7F",X"5F",X"4F",X"63",X"F2",X"FC",X"FE",X"7E",X"FE",X"FE",X"FE",X"FE",
+		X"3B",X"4F",X"4F",X"3F",X"33",X"5C",X"47",X"22",X"FE",X"FE",X"FC",X"FE",X"FE",X"FE",X"8E",X"FE",
+		X"01",X"03",X"0E",X"3E",X"7F",X"5F",X"4F",X"63",X"F0",X"FC",X"FE",X"7E",X"FE",X"FE",X"FE",X"FE",
+		X"3B",X"0F",X"0F",X"1F",X"13",X"1C",X"07",X"00",X"FE",X"FE",X"FC",X"FE",X"FE",X"FE",X"8E",X"FC",
+		X"00",X"00",X"00",X"00",X"00",X"02",X"07",X"07",X"00",X"00",X"00",X"00",X"08",X"0C",X"A6",X"C6",
+		X"0F",X"07",X"01",X"00",X"00",X"00",X"00",X"00",X"90",X"A6",X"06",X"0C",X"08",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"0F",X"07",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"F8",
+		X"0F",X"07",X"0F",X"00",X"00",X"00",X"00",X"00",X"C6",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"06",X"07",X"1F",X"1D",X"00",X"00",X"00",X"00",X"00",X"C0",X"C0",X"F0",
+		X"08",X"1D",X"1F",X"1D",X"00",X"00",X"00",X"00",X"CE",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"08",X"10",X"00",X"00",
+		X"00",X"00",X"08",X"08",X"00",X"00",X"00",X"00",X"00",X"10",X"08",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"20",X"30",X"18",X"1C",X"0E",X"0F",X"00",X"00",X"00",X"20",X"60",X"E4",X"CC",X"7C",
+		X"07",X"0E",X"0E",X"07",X"03",X"01",X"00",X"00",X"FA",X"70",X"64",X"FC",X"CC",X"B8",X"00",X"00",
+		X"00",X"00",X"00",X"03",X"07",X"0F",X"0F",X"1E",X"00",X"00",X"00",X"C0",X"F0",X"F0",X"F0",X"70",
+		X"1E",X"0F",X"0F",X"07",X"03",X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"C0",X"00",X"00",X"00",
+		X"00",X"80",X"40",X"20",X"10",X"08",X"04",X"02",X"00",X"10",X"08",X"08",X"1C",X"0C",X"00",X"00",
+		X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E0",X"E0",X"70",X"06",X"02",X"00",X"60",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"00",X"04",X"08",X"18",X"30",X"20",X"E0",X"40",
+		X"00",X"00",X"71",X"12",X"11",X"16",X"04",X"04",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"70",
+		X"31",X"08",X"00",X"00",X"00",X"00",X"01",X"01",X"C0",X"00",X"00",X"00",X"40",X"C0",X"78",X"00",
+		X"01",X"06",X"0C",X"08",X"08",X"10",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"0A",X"0F",X"03",X"38",X"1E",X"00",X"00",X"00",X"00",X"00",X"80",
+		X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"B0",X"30",X"30",X"1C",X"0C",X"04",X"02",X"00",
+		X"00",X"00",X"00",X"C0",X"C0",X"C0",X"FF",X"FF",X"00",X"00",X"00",X"03",X"03",X"03",X"FF",X"FF",
+		X"FF",X"FF",X"C0",X"C0",X"C0",X"00",X"00",X"00",X"FF",X"FF",X"03",X"03",X"03",X"00",X"00",X"00",
+		X"C0",X"E0",X"F0",X"F8",X"DC",X"CE",X"C7",X"C3",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"83",
+		X"C1",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C3",X"E3",X"73",X"3B",X"1F",X"0F",X"07",X"03",
+		X"38",X"78",X"E0",X"C0",X"C0",X"C0",X"C0",X"C0",X"30",X"30",X"3F",X"3F",X"3F",X"33",X"33",X"03",
+		X"C0",X"C0",X"C0",X"E0",X"70",X"38",X"1F",X"0F",X"03",X"03",X"03",X"07",X"0E",X"1C",X"F8",X"F0",
+		X"00",X"03",X"07",X"0E",X"1C",X"38",X"70",X"E0",X"00",X"FF",X"FF",X"60",X"60",X"60",X"60",X"60",
+		X"E0",X"70",X"38",X"1C",X"0E",X"07",X"03",X"00",X"60",X"60",X"60",X"60",X"60",X"FF",X"FF",X"00",
+		X"FF",X"FF",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"FF",X"FF",X"03",X"03",X"03",X"03",X"03",X"03",
+		X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"FF",X"FF",X"03",X"03",X"03",X"03",X"03",X"03",X"FF",X"FF",
+		X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"C0",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"03",
+		X"FF",X"FF",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"FF",X"FF",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"03",X"02",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"30",X"60",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"00",X"00",X"00",X"00",X"03",X"07",X"00",X"00",X"00",
+		X"06",X"04",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"60",X"30",X"30",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"01",X"03",X"00",X"00",X"01",X"02",X"02",X"80",X"C0",X"E0",X"80",X"80",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"01",X"03",X"00",X"00",X"00",X"00",X"00",X"80",X"C0",X"E0",X"80",X"80",X"40",X"20",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"40",X"40",X"20",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"01",X"01",X"02",X"02",X"40",X"40",X"80",X"80",X"00",X"00",X"00",X"00",
+		X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"40",X"40",X"20",X"20",
+		X"00",X"00",X"00",X"00",X"01",X"01",X"02",X"02",X"40",X"40",X"80",X"80",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"40",X"40",X"20",X"20",
+		X"00",X"00",X"00",X"00",X"01",X"01",X"02",X"02",X"40",X"40",X"80",X"80",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"23",X"64",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"F8",X"60",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"F8",X"64",X"23",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"30",X"0C",X"03",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",
+		X"30",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"0C",X"03",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"30",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"0C",
+		X"30",X"0C",X"03",X"00",X"00",X"00",X"00",X"00",X"30",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"19",X"10",X"3B",X"31",X"39",X"3D",X"00",X"00",X"80",X"80",X"C0",X"E0",X"F8",X"C0",
+		X"03",X"18",X"1E",X"00",X"06",X"00",X"00",X"00",X"F0",X"F0",X"F0",X"DC",X"DC",X"18",X"10",X"10",
+		X"00",X"00",X"04",X"76",X"6F",X"71",X"39",X"3F",X"00",X"00",X"00",X"00",X"BC",X"FE",X"FE",X"C6",
+		X"01",X"1C",X"16",X"1A",X"0E",X"00",X"00",X"00",X"F2",X"FA",X"FE",X"DE",X"DC",X"08",X"08",X"18",
+		X"00",X"00",X"01",X"01",X"63",X"33",X"9F",X"FF",X"00",X"F6",X"FE",X"FE",X"FE",X"FC",X"FC",X"FE",
+		X"FF",X"3F",X"03",X"31",X"00",X"04",X"00",X"00",X"FE",X"DE",X"DF",X"DF",X"DE",X"0C",X"1C",X"7C",
+		X"31",X"14",X"02",X"03",X"3B",X"1F",X"4F",X"7F",X"00",X"40",X"17",X"B7",X"FF",X"FF",X"FE",X"FE",
+		X"01",X"01",X"30",X"30",X"0C",X"0C",X"00",X"00",X"FE",X"FF",X"CF",X"CF",X"8F",X"8E",X"8C",X"3C",
+		X"00",X"01",X"01",X"05",X"05",X"0E",X"36",X"34",X"00",X"80",X"E0",X"F0",X"FC",X"7C",X"38",X"38",
+		X"36",X"3B",X"18",X"1F",X"0F",X"07",X"00",X"00",X"B8",X"BC",X"3C",X"10",X"90",X"D0",X"70",X"00",
+		X"06",X"03",X"01",X"1D",X"15",X"4C",X"5F",X"6E",X"00",X"E8",X"FC",X"FC",X"FC",X"3C",X"9C",X"DE",
+		X"E4",X"F2",X"F9",X"FC",X"3F",X"1F",X"07",X"00",X"5E",X"DE",X"1C",X"08",X"C4",X"E2",X"C6",X"00",
+		X"07",X"3F",X"1F",X"07",X"31",X"6C",X"07",X"AE",X"E0",X"FB",X"FF",X"FF",X"FC",X"7E",X"3F",X"9C",
+		X"9E",X"C8",X"66",X"72",X"39",X"3C",X"1F",X"07",X"DC",X"08",X"CF",X"9C",X"1C",X"0E",X"C6",X"C6",
+		X"12",X"4D",X"19",X"0F",X"07",X"31",X"50",X"0F",X"28",X"48",X"6D",X"3F",X"BF",X"FF",X"7F",X"1F",
+		X"5C",X"38",X"98",X"CC",X"4C",X"67",X"30",X"38",X"CF",X"CF",X"27",X"27",X"C7",X"8E",X"1C",X"7C",
+		X"00",X"00",X"10",X"18",X"30",X"38",X"38",X"3C",X"00",X"00",X"C0",X"40",X"E8",X"64",X"E0",X"F0",
+		X"3E",X"3F",X"1F",X"19",X"09",X"07",X"00",X"00",X"F8",X"98",X"8C",X"84",X"04",X"04",X"04",X"00",
+		X"00",X"00",X"00",X"0B",X"1D",X"1B",X"3D",X"3B",X"00",X"00",X"00",X"00",X"80",X"90",X"D8",X"FC",
+		X"3D",X"3F",X"3F",X"1F",X"13",X"19",X"07",X"00",X"C4",X"E0",X"F0",X"18",X"0C",X"04",X"0C",X"10",
+		X"00",X"00",X"07",X"29",X"2E",X"2F",X"29",X"2F",X"00",X"40",X"20",X"30",X"60",X"70",X"30",X"30",
+		X"2F",X"26",X"30",X"19",X"09",X"00",X"00",X"00",X"30",X"60",X"F0",X"E0",X"A0",X"E0",X"00",X"00",
+		X"00",X"01",X"1C",X"A4",X"B9",X"BD",X"A4",X"BC",X"00",X"00",X"80",X"80",X"C0",X"C0",X"C0",X"80",
+		X"BC",X"99",X"C3",X"67",X"26",X"00",X"00",X"00",X"80",X"C0",X"C0",X"80",X"80",X"E0",X"00",X"00",
+		X"00",X"00",X"30",X"1C",X"1F",X"0F",X"07",X"00",X"00",X"00",X"F8",X"FC",X"7C",X"3C",X"3C",X"78",
+		X"00",X"07",X"0F",X"1F",X"1C",X"30",X"00",X"00",X"78",X"3C",X"3C",X"7C",X"FC",X"F8",X"00",X"00",
+		X"00",X"00",X"00",X"0F",X"0F",X"3F",X"3C",X"00",X"00",X"00",X"3C",X"3C",X"3C",X"7C",X"78",X"F8",
+		X"00",X"3C",X"3F",X"0F",X"0F",X"00",X"00",X"00",X"F8",X"78",X"7C",X"3C",X"3C",X"3C",X"00",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"00",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",X"00",
+		X"00",X"00",X"00",X"02",X"05",X"00",X"03",X"0C",X"00",X"00",X"00",X"10",X"50",X"68",X"88",X"C8",
+		X"03",X"0A",X"03",X"01",X"04",X"03",X"00",X"00",X"F4",X"A0",X"C0",X"70",X"40",X"20",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"2B",X"01",X"13",X"00",X"4C",X"10",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"12",X"17",X"08",X"00",X"09",X"00",X"02",X"00",X"03",X"02",X"84",X"89",X"10",X"88",X"84",X"01",
+		X"0F",X"06",X"04",X"00",X"00",X"01",X"01",X"02",X"C2",X"67",X"21",X"21",X"C2",X"82",X"91",X"08",
+		X"00",X"08",X"04",X"14",X"01",X"63",X"50",X"08",X"0A",X"16",X"02",X"21",X"07",X"84",X"2C",X"18",
+		X"06",X"00",X"46",X"21",X"00",X"11",X"26",X"20",X"01",X"41",X"0F",X"10",X"0E",X"02",X"02",X"0E",
+		X"07",X"08",X"08",X"08",X"07",X"00",X"09",X"0A",X"C0",X"20",X"20",X"20",X"C0",X"00",X"C0",X"20",
+		X"0A",X"0A",X"0E",X"00",X"00",X"0F",X"04",X"00",X"20",X"20",X"40",X"00",X"20",X"E0",X"20",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"00",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",X"00",
+		X"01",X"03",X"0F",X"17",X"31",X"00",X"00",X"00",X"F8",X"FC",X"7E",X"3E",X"FE",X"FE",X"36",X"06",
+		X"00",X"00",X"00",X"07",X"09",X"0E",X"07",X"00",X"0E",X"1E",X"9C",X"FE",X"FE",X"7E",X"8E",X"FC",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"02",X"02",X"0A",X"06",X"1E",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0A",X"0C",X"0E",X"02",X"0C",X"06",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"07",X"08",X"08",X"07",X"00",X"00",X"00",X"00",X"C0",X"20",X"20",X"C0",
+		X"00",X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"00",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",
+		X"08",X"07",X"00",X"00",X"0F",X"04",X"00",X"00",X"20",X"C0",X"00",X"20",X"E0",X"20",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"20",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"00",X"0F",X"04",X"02",X"01",X"20",X"C0",X"00",X"40",X"E0",X"40",X"40",X"40",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"09",X"09",X"06",X"20",X"C0",X"00",X"C0",X"20",X"20",X"20",X"C0",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"00",X"09",X"09",X"09",X"07",X"20",X"C0",X"00",X"C0",X"20",X"20",X"20",X"C0",
+		X"00",X"00",X"0F",X"04",X"00",X"00",X"00",X"00",X"00",X"20",X"E0",X"20",X"00",X"00",X"00",X"00",
+		X"08",X"07",X"00",X"06",X"09",X"08",X"08",X"04",X"20",X"C0",X"00",X"20",X"20",X"A0",X"60",X"20",
+		X"00",X"0C",X"0B",X"09",X"08",X"08",X"00",X"00",X"00",X"C0",X"20",X"20",X"20",X"40",X"00",X"00",
+		X"23",X"43",X"4E",X"3E",X"7F",X"5F",X"4F",X"63",X"F2",X"FC",X"FE",X"7E",X"FE",X"FE",X"FE",X"FE",
+		X"3B",X"4F",X"4F",X"3F",X"33",X"5C",X"47",X"22",X"FE",X"FE",X"FC",X"FE",X"FE",X"FE",X"8E",X"FE",
+		X"01",X"03",X"0E",X"3E",X"7F",X"5F",X"4F",X"63",X"F0",X"FC",X"FE",X"7E",X"FE",X"FE",X"FE",X"FE",
+		X"3B",X"0F",X"0F",X"1F",X"13",X"1C",X"07",X"00",X"FE",X"FE",X"FC",X"FE",X"FE",X"FE",X"8E",X"FC",
+		X"00",X"00",X"00",X"00",X"00",X"02",X"07",X"07",X"00",X"00",X"00",X"00",X"08",X"0C",X"A6",X"C6",
+		X"0F",X"07",X"01",X"00",X"00",X"00",X"00",X"00",X"90",X"A6",X"06",X"0C",X"08",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"0F",X"07",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"F8",
+		X"0F",X"07",X"0F",X"00",X"00",X"00",X"00",X"00",X"C6",X"80",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"06",X"07",X"1F",X"1D",X"00",X"00",X"00",X"00",X"00",X"C0",X"C0",X"F0",
+		X"08",X"1D",X"1F",X"1D",X"00",X"00",X"00",X"00",X"CE",X"C0",X"C0",X"80",X"00",X"00",X"00",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"08",X"0D",X"0B",X"09",X"08",X"00",X"C0",X"00",X"C0",X"20",X"20",X"20",X"40",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"00",X"0F",X"04",X"02",X"01",X"00",X"C0",X"00",X"40",X"E0",X"40",X"40",X"40",X"C0",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"09",X"0A",X"0A",X"0A",X"0E",X"00",X"C0",X"00",X"C0",X"20",X"20",X"20",X"40",X"00",
+		X"07",X"08",X"08",X"07",X"00",X"07",X"08",X"08",X"C0",X"20",X"20",X"C0",X"00",X"C0",X"20",X"20",
+		X"07",X"00",X"07",X"08",X"08",X"07",X"00",X"0F",X"C0",X"00",X"C0",X"20",X"20",X"C0",X"00",X"E0",
+		X"00",X"00",X"00",X"00",X"00",X"15",X"15",X"2F",X"00",X"00",X"00",X"00",X"00",X"E0",X"E0",X"C0",
+		X"60",X"C0",X"FF",X"C0",X"60",X"20",X"00",X"00",X"30",X"60",X"F8",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"01",X"03",X"00",X"00",X"0A",X"0A",X"07",X"70",X"FC",X"26",X"20",X"20",X"F0",X"F0",X"E0",
+		X"00",X"04",X"04",X"00",X"00",X"00",X"00",X"00",X"30",X"3C",X"20",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"01",X"06",X"01",X"07",X"01",X"07",X"70",X"F8",X"AC",X"20",X"20",X"20",X"20",X"20",
+		X"07",X"07",X"06",X"00",X"00",X"00",X"00",X"00",X"20",X"60",X"E0",X"A0",X"20",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"06",X"01",X"27",X"61",X"00",X"00",X"00",X"00",X"00",X"60",X"00",X"00",
+		X"47",X"C7",X"FF",X"C6",X"40",X"60",X"20",X"00",X"00",X"00",X"E0",X"C0",X"40",X"40",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"15",X"15",X"0F",X"00",X"00",X"00",X"00",X"00",X"E0",X"E0",X"C0",
+		X"10",X"30",X"7F",X"30",X"10",X"00",X"00",X"00",X"30",X"60",X"F0",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"0A",X"0A",X"07",X"00",X"00",X"00",X"00",X"00",X"F0",X"F0",X"E0",
+		X"04",X"0C",X"1F",X"0C",X"04",X"00",X"00",X"00",X"08",X"18",X"FC",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"06",X"01",X"07",X"01",X"07",X"00",X"20",X"70",X"F8",X"20",X"20",X"20",X"20",
+		X"07",X"07",X"06",X"00",X"00",X"00",X"00",X"00",X"20",X"60",X"E0",X"A0",X"20",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"06",X"01",X"07",X"01",X"00",X"00",X"00",X"20",X"70",X"F8",X"20",X"20",
+		X"07",X"07",X"07",X"06",X"00",X"00",X"00",X"00",X"20",X"20",X"20",X"60",X"E0",X"20",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"03",X"03",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"0C",X"02",X"0E",X"02",X"0E",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"78",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"E0",X"20",
+		X"01",X"00",X"01",X"00",X"01",X"01",X"00",X"00",X"80",X"40",X"C0",X"46",X"DE",X"80",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0E",X"00",X"00",X"00",X"00",X"0C",X"0C",X"04",X"04",
+		X"0C",X"01",X"02",X"02",X"00",X"00",X"00",X"00",X"00",X"E0",X"B0",X"B0",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dpram.vhd
index dafe8385..fec08f5f 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dpram.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/dpram.vhd	
@@ -16,7 +16,7 @@ entity dpram is
 		clock_a		: IN STD_LOGIC  := '1';
 		clock_b		: IN STD_LOGIC ;
 		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0');
 		enable_a		: IN STD_LOGIC  := '1';
 		enable_b		: IN STD_LOGIC  := '1';
 		wren_a		: IN STD_LOGIC  := '0';
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/galaxian.vhd
index b881e738..f384af19 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/galaxian.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/galaxian.vhd	
@@ -15,6 +15,26 @@
 -- 2004- 5- 6  first release.
 -- 2004- 8-23  Improvement with T80-IP.
 -- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
+--
+-- 2019-12 Multi-machine support added
+-- "GALAXIAN"
+-- "MOONCR"
+-- "AZURIAN"
+-- "BLACKHOLE"
+-- "CATACOMB"
+-- "CHEWINGG"
+-- "DEVILFSH"
+-- "KINGBAL"
+-- "MRDONIGH"
+-- "OMEGA"
+-- "ORBITRON"
+-- "PISCES"
+-- "UNIWARS"
+-- "VICTORY"
+-- "WAROFBUG"
+-- "ZIGZAG" -- doesn't work yet
+-- "TRIPLEDR"
+
 ------------------------------------------------------------------------------
 library ieee;
   use ieee.std_logic_1164.all;
@@ -24,8 +44,10 @@ library ieee;
 --use work.pkg_galaxian.all;
 
 entity galaxian is
+	generic (
+		name       : string := "GALAXIAN"
+	);
 	port(
-		W_CLK_18M  : in  std_logic;
 		W_CLK_12M  : in  std_logic;
 		W_CLK_6M   : in  std_logic;
 
@@ -40,8 +62,9 @@ entity galaxian is
 		VBLANK     : out std_logic;
 		W_H_SYNC   : out std_logic;
 		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
+		W_SDAT_A   : out std_logic_vector( 7 downto 0) := (others => '0');
+		W_SDAT_B   : out std_logic_vector( 7 downto 0) := (others => '0');
+		W_SDAT_C   : out std_logic_vector( 7 downto 0) := (others => '0');
 		O_CMPBL    : out std_logic
 	);
 end;
@@ -50,7 +73,7 @@ architecture RTL of galaxian is
 	--    CPU ADDRESS BUS
 	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
 	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
+	signal W_CPU_CLK_EN       : std_logic := '0';
 	signal W_CPU_MREQn        : std_logic := '0';
 	signal W_CPU_NMIn         : std_logic := '0';
 	signal W_CPU_RDn          : std_logic := '0';
@@ -59,9 +82,15 @@ architecture RTL of galaxian is
 	signal W_CPU_WRn          : std_logic := '0';
 	signal W_CPU_WR           : std_logic := '0';
 	signal W_RESETn           : std_logic := '0';
+	signal CPU_INT_n          : std_logic;
+	signal CPU_NMI_n          : std_logic;
+
 	-------- H and V COUNTER -------------------------
 	signal W_C_BLn            : std_logic := '0';
 	signal W_C_BLnX           : std_logic := '0';
+	signal W_H_BLn            : std_logic := '0';
+	signal W_H_BLnX           : std_logic := '0';
+	signal W_H_BLXn           : std_logic := '0';
 	signal W_C_BLXn           : std_logic := '0';
 	signal W_H_BL             : std_logic := '0';
 	signal W_H_SYNC_int       : std_logic := '0';
@@ -76,6 +105,7 @@ architecture RTL of galaxian is
 	signal W_BD_G             : std_logic := '0';
 	signal W_CPU_RAM_CS       : std_logic := '0';
 	signal W_CPU_RAM_RD       : std_logic := '0';
+	signal W_CPU_ROM_ADDR     : std_logic_vector(13 downto 0);
 --	signal W_CPU_RAM_WR       : std_logic := '0';
 	signal W_CPU_ROM_CS       : std_logic := '0';
 	signal W_DIP_OE           : std_logic := '0';
@@ -86,7 +116,10 @@ architecture RTL of galaxian is
 	signal W_OBJ_RAM_WR       : std_logic := '0';
 	signal W_PITCH            : std_logic := '0';
 	signal W_SOUND_WE         : std_logic := '0';
+	signal W_MISC_WE          : std_logic := '0';
+	signal W_SPEECH_IN        : std_logic_vector(1 downto 0);
 	signal W_STARS_ON         : std_logic := '0';
+	signal W_STARS_ON_ADJ     : std_logic := '0';
 	signal W_STARS_OFFn       : std_logic := '0';
 	signal W_SW0_OE           : std_logic := '0';
 	signal W_SW1_OE           : std_logic := '0';
@@ -101,9 +134,9 @@ architecture RTL of galaxian is
 	-----  DATA I/F -------------------------------------
 	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
 	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_ROM_SWP          : std_logic := '0'; -- ZigZag
 	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
 	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
 	signal W_VOL1             : std_logic := '0';
 	signal W_VOL2             : std_logic := '0';
 	signal W_FIRE             : std_logic := '0';
@@ -142,11 +175,34 @@ architecture RTL of galaxian is
 	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
 	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
 	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
+	
+	signal PSG_EN             : std_logic;
+	signal PSG_D              : std_logic_vector(7 downto 0);
+	signal PSG_A,PSG_B,PSG_C  : std_logic_vector(7 downto 0);
+	signal PSG_OUT            : std_logic_vector(9 downto 0);
+
+	component ym2149
+	port (
+		CLK       : in  std_logic;
+		CE        : in  std_logic;
+		RESET     : in  std_logic;
+		BDIR      : in  std_logic;
+		BC        : in  std_logic;
+		DI        : in  std_logic_vector(7 downto 0);
+		DO        : out std_logic_vector(7 downto 0);
+		CHANNEL_A : out std_logic_vector(7 downto 0);
+		CHANNEL_B : out std_logic_vector(7 downto 0);
+		CHANNEL_C : out std_logic_vector(7 downto 0)
+	);
+	end component;
 
 begin
+
 	mc_vid : entity work.MC_VIDEO
+	generic map(
+		name          => name
+	)
 	port map(
-		I_CLK_18M     => W_CLK_18M,
 		I_CLK_12M     => W_CLK_12M,
 		I_CLK_6M      => W_CLK_6M,
 		I_H_CNT       => W_H_CNT,
@@ -155,6 +211,7 @@ begin
 		I_V_FLIP      => W_V_FLIP,
 		I_V_BLn       => W_V_BLn,
 		I_C_BLn       => W_C_BLn,
+		I_H_BLn       => W_H_BLn,
 		I_A           => W_A(9 downto 0),
 		I_OBJ_SUB_A   => "000",
 		I_BD          => W_BDI,
@@ -165,6 +222,7 @@ begin
 		I_VID_RAM_WR  => W_VID_RAM_WR,
 		I_DRIVER_WR   => W_DRIVER_WE,
 		O_C_BLnX      => W_C_BLnX,
+		O_H_BLnX      => W_H_BLnX,
 		O_8HF         => W_8HF,
 		O_256HnX      => W_256HnX,
 		O_1VF         => W_1VF,
@@ -175,13 +233,22 @@ begin
 		O_COL         => W_COL
 	);
 
-	cpu : entity work.T80as
+	int_gen: if name = "DEVILFSH" generate
+		CPU_INT_n <= W_CPU_NMIn;
+		CPU_NMI_n <= '1';
+	else generate
+		CPU_INT_n <= '1';
+		CPU_NMI_n <= W_CPU_NMIn;
+	end generate;
+
+	cpu : entity work.T80se
 	port map (
 		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
+		CLK_n         => W_CLK_6M,
+		CLKEN         => W_CPU_CLK_EN,
 		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
+		INT_n         => CPU_INT_n,
+		NMI_n         => CPU_NMI_n,
 		BUSRQ_n       => '1',
 		MREQ_n        => W_CPU_MREQn,
 		RD_n          => W_CPU_RDn,
@@ -193,13 +260,14 @@ begin
 		M1_n          => open,
 		IORQ_n        => open,
 		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
+		BUSAK_n       => open--,
+--		DOE           => open
 	);
 
 	mc_cpu_ram : entity work.MC_CPU_RAM
 	port map (
-		I_CLK         => W_CPU_RAM_CLK,
+		I_CLK         => W_CLK_12M,
+		I_CS          => W_CPU_RAM_CS,
 		I_ADDR        => W_A(9 downto 0),
 		I_D           => W_BDI,
 		I_WE          => W_CPU_WR,
@@ -211,7 +279,6 @@ begin
 	port map(
 		I_CLK_12M     => W_CLK_12M,
 		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
 		I_RSTn        => W_RESETn,
 
 		I_CPU_A       => W_A,
@@ -240,15 +307,21 @@ begin
 		O_WDR_OE      => W_WDR_OE,
 		O_DRIVER_WE   => W_DRIVER_WE,
 		O_SOUND_WE    => W_SOUND_WE,
+		O_MISC_WE     => W_MISC_WE,
 		O_PITCH       => W_PITCH,
 		O_H_FLIP      => W_H_FLIP,
 		O_V_FLIP      => W_V_FLIP,
+		O_SPEECH      => W_SPEECH_IN,
 		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
+		O_STARS_ON    => W_STARS_ON,
+		O_ROM_SWP     => W_ROM_SWP
 	);
 
 	-- active high buttons
 	mc_inport : entity work.MC_INPORT
+	generic map(
+		name          => name
+	)
 	port map (
 		I_COIN1       => P1_CSJUDLR(6),
 		I_COIN2       => P2_CSJUDLR(6),
@@ -260,6 +333,10 @@ begin
 		I_2P_LE       => P2_CSJUDLR(1),
 		I_1P_RI       => P1_CSJUDLR(0),
 		I_2P_RI       => P2_CSJUDLR(0),
+		I_1P_UP       => P1_CSJUDLR(3),
+		I_2P_UP       => P2_CSJUDLR(3),
+		I_1P_DN       => P1_CSJUDLR(2),
+		I_2P_DN       => P2_CSJUDLR(2),
 		I_SW0_OE      => W_SW0_OE,
 		I_SW1_OE      => W_SW1_OE,
 		I_DIP_OE      => W_DIP_OE,
@@ -273,6 +350,7 @@ begin
 		O_H_CNT       => W_H_CNT,
 		O_H_SYNC      => W_H_SYNC_int,
 		O_H_BL        => W_H_BL,
+		O_H_BLn       => W_H_BLn,
 		O_V_CNT       => W_V_CNT,
 		O_V_SYNC      => W_V_SYNC_int,
 		O_V_BL2n      => W_V_BL2n,
@@ -281,22 +359,29 @@ begin
 	);
 
 	mc_col_pal : entity work.MC_COL_PAL
+	generic map(
+		name          => name
+	)
 	port map(
 		I_CLK_12M     => W_CLK_12M,
 		I_CLK_6M      => W_CLK_6M,
 		I_VID         => W_VID,
 		I_COL         => W_COL,
 		I_C_BLnX      => W_C_BLnX,
+		I_H_BLnX      => W_H_BLnX,
 		O_C_BLXn      => W_C_BLXn,
+		O_H_BLXn      => W_H_BLXn,
 		O_STARS_OFFn  => W_STARS_OFFn,
 		O_R           => W_VIDEO_R,
 		O_G           => W_VIDEO_G,
 		O_B           => W_VIDEO_B
 	);
 
+	comps: if name /= "ZIGZAG" generate
+
 	mc_stars : entity work.MC_STARS
 	port map (
-		I_CLK_18M     => W_CLK_18M,
+		I_CLK_12M     => W_CLK_12M,
 		I_CLK_6M      => W_CLK_6M,
 		I_H_FLIP      => W_H_FLIP,
 		I_V_SYNC      => W_V_SYNC_int,
@@ -304,7 +389,7 @@ begin
 		I_256HnX      => W_256HnX,
 		I_1VF         => W_1VF,
 		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
+		I_STARS_ON    => W_STARS_ON_ADJ,
 		I_STARS_OFFn  => W_STARS_OFFn,
 		O_R           => W_STARS_R,
 		O_G           => W_STARS_G,
@@ -334,15 +419,25 @@ begin
 		I_FS          => W_FS,
 		O_SDAT        => W_SDAT_B
 	);
+end generate;
 
 --------- ROM           -------------------------------------------------------
 	mc_roms : entity work.ROM_PGM_0
+	generic map (
+		name => name
+	)
 	port map (
 		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
+		ADDR => W_CPU_ROM_ADDR,
 		DATA => W_CPU_ROM_DO
 	);
 
+	romaddr: if name = "ZIGZAG" generate
+		W_CPU_ROM_ADDR <=  W_A(13) & (W_A(12) xor (W_ROM_SWP and W_A(13))) & W_A(11 downto 0);
+	else generate
+		W_CPU_ROM_ADDR <=  W_A(13 downto 0);
+	end generate;
+
 -------- VIDEO  -----------------------------
 	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
 	W_V_SYNC <= not W_V_SYNC_int;
@@ -363,7 +458,7 @@ begin
 	process(W_CLK_6M)
 	begin
 		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
+			HBLANK   <= not W_H_BLXn;
 			VBLANK   <= not W_V_BL2n;
 		end if;
 	end process;
@@ -371,8 +466,8 @@ begin
 
 -----  CPU I/F  -------------------------------------
 
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
+	W_CPU_CLK_EN  <= not W_H_CNT(0); -- CPU clock enable in the 6MHz domain
+--	W_CPU_CLK     <= W_H_CNT(0);
 
 	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
 
@@ -382,12 +477,12 @@ begin
 
 	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
 
-	process(W_CPU_CLK, I_RESET)
+	process(W_CLK_6M, I_RESET)
 	begin
 		if (I_RESET = '1') then
 			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
+		elsif rising_edge( W_CLK_6M) then
+			if ( W_CPU_CLK_EN = '1' and rst_count /= x"f") then
 				rst_count <= rst_count + 1;
 			end if;
 		end if;
@@ -443,4 +538,54 @@ begin
 	end process;
 
 -------------------------------------------------------------------------------
+-- King & Balloon speech board
+kb_speech: if name = "KINGBAL" generate
+	speech : entity work.kb_synth
+	port map(
+		reset_n       => W_RESETn,
+		clk           => W_CLK_12M,
+		in0           => W_SPEECH_IN(0),
+		in1           => W_SPEECH_IN(1),
+		in2           => '0', -- GND
+		in3           => '0', -- GND
+		speech_out    => W_SDAT_C
+	);
+	
+		W_STARS_ON_ADJ <= '0'; -- no stars in this game
+else generate
+		W_STARS_ON_ADJ <= W_STARS_ON;
+end generate;
+
+-- AY8910 for ZigZag
+psg: if name = "ZIGZAG" generate
+	PSG_EN <= '1' when W_A(15 downto 11) = "01001" and W_A(9) = '0' and W_CPU_MREQn = '0' and W_CPU_WRn = '0' else '0';
+
+	process(W_CLK_6M)
+	begin
+		if rising_edge(W_CLK_6M) then
+			if PSG_EN = '1' and W_A(8) = '1' then
+				PSG_D <= W_A(7 downto 0);
+			end if;
+		end if;
+	end process;
+
+	PSG_OUT <= ("00" & PSG_A) + ("00" & PSG_B) + ("00" & PSG_C);
+	W_SDAT_C <= PSG_OUT(9 downto 2);
+
+	psg : ym2149
+	port map (
+		CLK       => W_CLK_6M,
+		CE        => W_CPU_CLK_EN,
+		RESET     => I_RESET,
+
+		BDIR      => PSG_EN and W_A(0) and not W_A(8),
+		BC        => W_A(1),
+		DI        => PSG_D,
+
+		CHANNEL_A => PSG_A,
+		CHANNEL_B => PSG_B,
+		CHANNEL_C => PSG_C
+	);
+end generate;
+
 end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/kb_synth.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/kb_synth.vhd
new file mode 100644
index 00000000..350eed5c
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/kb_synth.vhd	
@@ -0,0 +1,136 @@
+-- Sound synth board for King & Balloon
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+entity kb_synth is
+	port (
+		reset_n  : in  std_logic;
+		clk : in  std_logic;
+		in0 : in  std_logic;
+		in1 : in  std_logic;
+		in2 : in  std_logic;
+		in3 : in  std_logic;
+		speech_out   : out std_logic_vector(7 downto 0)
+	);
+end kb_synth;
+
+architecture RTL of kb_synth is
+
+signal cpu_ce : std_logic;
+signal cpu_ce_cnt : unsigned(2 downto 0);
+signal cpu_addr : std_logic_vector(15 downto 0);
+signal cpu_di : std_logic_vector(7 downto 0);
+signal cpu_do : std_logic_vector(7 downto 0);
+signal ram_do : std_logic_vector(7 downto 0);
+signal rom4_do : std_logic_vector(7 downto 0);
+signal rom5_do : std_logic_vector(7 downto 0);
+signal rom6_do : std_logic_vector(7 downto 0);
+signal mreq_n : std_logic;
+signal iorq_n : std_logic;
+signal rd_n : std_logic;
+signal wr_n : std_logic;
+
+signal ram_ce : std_logic;
+signal ram_wr : std_logic;
+signal rom4_ce : std_logic;
+signal rom5_ce : std_logic;
+signal rom6_ce : std_logic;
+signal buf_do : std_logic_vector(7 downto 0);
+signal buf_ce_n : std_logic;
+
+begin
+
+	cpu_di <= ram_do when ram_ce = '1' else
+	         rom4_do when rom4_ce = '1' else
+	         rom5_do when rom5_ce = '1' else
+	         rom6_do when rom6_ce = '1' else
+	          buf_do when buf_ce_n = '0' else
+	         "00000000";
+
+	-- clk/5 = 12MHz/5 = 2.4MHz (originally 5MHz/2)
+	process(clk, reset_n)
+	begin
+		if reset_n = '0' then
+			cpu_ce <= '0';
+			cpu_ce_cnt <= (others => '0');
+		elsif rising_edge(clk) then
+			cpu_ce_cnt <= cpu_ce_cnt + 1;
+			cpu_ce <= '0';
+			if cpu_ce_cnt = 4 then
+				cpu_ce <= '1';
+				cpu_ce_cnt <= (others => '0');
+			end if;
+		end if;
+	end process;
+
+	cpu : entity work.T80se
+	port map (
+		RESET_n      => reset_n,
+		CLK_n        => clk,
+		CLKEN        => cpu_ce,
+		WAIT_n       => '1',
+		INT_n        => '1',
+		NMI_n        => '1',
+		BUSRQ_n      => '1',		
+		MREQ_n       => mreq_n,
+		IORQ_n       => iorq_n,
+		RD_n         => rd_n,
+		WR_n         => wr_n,		
+		A            => cpu_addr,
+		DI           => cpu_di,
+		DO           => cpu_do
+	);
+
+	ram_ce <= cpu_addr(13) and not mreq_n;
+	ram_wr <= not wr_n and ram_ce;
+
+	ram_inst : entity work.spram generic map(10,8)
+	port map (
+		address  	 => cpu_addr(9 downto 0),
+		clock    	 => clk,
+		data     	 => cpu_do,
+		wren       => ram_wr,
+		q          => ram_do
+	);
+
+	rom4_ce <= '1' when rd_n = '0' and mreq_n = '0' and cpu_addr(13 downto 11) = "000" else '0';
+	rom4_inst : entity work.kbe1_IC4
+	port map (
+		clk    	 	 => clk,
+		addr  	 	 => cpu_addr(10 downto 0),
+		data			 => rom4_do
+	);
+
+	rom5_ce <= '1' when rd_n = '0' and mreq_n = '0' and cpu_addr(13 downto 11) = "001" else '0';
+	rom5_inst : entity work.kbe2_IC5
+	port map (
+		clk    	 	 => clk,
+		addr  	 	 => cpu_addr(10 downto 0),
+		data			 => rom5_do
+	);
+
+	rom6_ce <= '1' when rd_n = '0' and mreq_n = '0' and cpu_addr(13 downto 11) = "010" else '0';
+	rom6_inst : entity work.kbe3_IC6
+	port map (
+		clk    	 	 => clk,
+		addr  	 	 => cpu_addr(10 downto 0),
+		data			 => rom6_do
+	);
+
+	process(clk, reset_n)
+	begin
+		if reset_n = '0' then
+			speech_out <= (others => '0');
+		elsif rising_edge(clk) then
+			if iorq_n = '0' and wr_n = '0' then
+				speech_out <= cpu_do;
+			end if;
+		end if;
+	end process;
+
+	buf_ce_n <= rd_n or iorq_n;
+	buf_do <= "1111"&in3&in2&in1&in0;
+
+end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_adec.vhd
index 7245ce8c..2a35d496 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_adec.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_adec.vhd	
@@ -57,7 +57,6 @@ entity MC_ADEC is
 	port (
 		I_CLK_12M     : in  std_logic;
 		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
 		I_RSTn        : in  std_logic;
 
 		I_CPU_A       : in  std_logic_vector(15 downto 0);
@@ -86,11 +85,14 @@ entity MC_ADEC is
 		O_WDR_OE      : out std_logic;
 		O_DRIVER_WE   : out std_logic;
 		O_SOUND_WE    : out std_logic;
+		O_MISC_WE     : out std_logic;
 		O_PITCH       : out std_logic;
 		O_H_FLIP      : out std_logic;
 		O_V_FLIP      : out std_logic;
+		O_SPEECH      : out std_logic_vector(1 downto 0); -- kingballoon
 		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
+		O_STARS_ON    : out std_logic;
+		O_ROM_SWP     : out std_logic  -- ZigZag
 	);
 end;
 
@@ -115,12 +117,12 @@ begin
 --		O_WAITn <= '1' ; -- No Wait
 		O_WAITn <= W_6S1_Qn;
 
-	process(I_CPU_CLK, I_V_BLn)
+	process(I_CLK_6M, I_V_BLn)
 	begin
 		if (I_V_BLn = '0') then
 --			W_6S1_Q  <= '0';
 			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
+		elsif rising_edge(I_CLK_6M) then
 --			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
 			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
 		end if;
@@ -213,7 +215,7 @@ begin
 	O_CPU_RAM_RD  <= not W_8N_Q(0);
 
 	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
+	O_MISC_WE     <= not W_8M_Q(6);
 	O_SOUND_WE    <= not W_8M_Q(5);
 	O_DRIVER_WE   <= not W_8M_Q(4);
 	O_OBJ_RAM_WR  <= not W_8M_Q(3);
@@ -247,5 +249,7 @@ begin
 	O_STARS_ON <= W_9N_Q(4);
 	O_H_FLIP   <= W_9N_Q(6);
 	O_V_FLIP   <= W_9N_Q(7);
+	O_SPEECH   <= W_9N_Q(2)&W_9N_Q(0); -- King & Balloon
+	O_ROM_SWP  <= W_9N_Q(2); -- ZigZag
 
 end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_bram.vhd
index a6df1ce1..5bafe7aa 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_bram.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_bram.vhd	
@@ -27,6 +27,7 @@ library ieee;
 entity MC_CPU_RAM is
 	port (
 		I_CLK  : in  std_logic;
+		I_CS   : in  std_logic;
 		I_ADDR : in  std_logic_vector(9 downto 0);
 		I_D    : in  std_logic_vector(7 downto 0);
 		I_WE   : in  std_logic;
@@ -46,7 +47,7 @@ begin
 		address  => I_ADDR,
 		clock    => I_CLK,
 		data     => I_D,
-		wren		=> I_WE,
+		wren		=> I_WE and I_CS,
 		q			=> W_D
 	);
 end RTL;
@@ -150,32 +151,29 @@ library ieee;
 --  mc_video.v use
 entity MC_LRAM is
 	port (
-		I_CLK   : in  std_logic;
+		I_WCLK  : in  std_logic;
+		I_RCLK  : in  std_logic;
 		I_ADDR  : in  std_logic_vector(7 downto 0);
 		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
 		O_Dn    : out std_logic_vector(4 downto 0)
 	);
 end;
 
 architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
 begin
 
-	O_Dn <= not W_D;
-
 	ram_inst : work.dpram generic map(8,5)
 	port map
 	(
-		clock_a		=> I_CLK,
+		clock_a		=> I_WCLK,
 		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
+		data_a		=> not I_D,
+		wren_a		=> '1',
 
-		clock_b		=> not I_CLK,
+		clock_b		=> not I_RCLK,
 		address_b	=> I_ADDR,
 		data_b		=> (others => '0'),
-		q_b			=> W_D,
+		q_b			=> O_Dn,
 		enable_b    => '1',
 		wren_b		=> '0'
 	);
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_col_pal.vhd
index c4dc06ad..eda4677e 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_col_pal.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_col_pal.vhd	
@@ -22,14 +22,19 @@ library ieee;
 --  use UNISIM.Vcomponents.all;
 
 entity MC_COL_PAL is
+generic (
+	name         : string
+);
 port (
 	I_CLK_12M    : in  std_logic;
 	I_CLK_6M     : in  std_logic;
 	I_VID        : in  std_logic_vector(1 downto 0);
 	I_COL        : in  std_logic_vector(2 downto 0);
 	I_C_BLnX     : in  std_logic;
+	I_H_BLnX     : in  std_logic;
 
 	O_C_BLXn     : out std_logic;
+	O_H_BLXn     : out std_logic;
 	O_STARS_OFFn : out std_logic;
 	O_R          : out std_logic_vector(2 downto 0);
 	O_G          : out std_logic_vector(2 downto 0);
@@ -43,6 +48,8 @@ architecture RTL of MC_COL_PAL is
 	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
 	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
 	signal W_6M_CLR     : std_logic := '0';
+	signal W_6M_HBL     : std_logic := '0';
+	signal W_6M_HBLCLR  : std_logic := '0';
 
 begin
 	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
@@ -50,6 +57,9 @@ begin
 	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
 	O_STARS_OFFn <= W_6M_DO(1);
 
+	W_6M_HBLCLR  <= I_H_BLnX or W_6M_HBL;
+	O_H_BLXn     <= I_H_BLnX or W_6M_HBL;
+
 --always@(posedge I_CLK_6M or negedge W_6M_CLR)
 	process(I_CLK_6M, W_6M_CLR)
 	begin
@@ -60,10 +70,19 @@ begin
 		end if;
 	end process;
 
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
+	process(I_CLK_6M, W_6M_HBLCLR)
+	begin
+		if (W_6M_HBLCLR = '0') then
+			W_6M_HBL <= '0';
+		elsif rising_edge(I_CLK_6M) then
+			W_6M_HBL <= I_H_BLnX;
+		end if;
+	end process;
 
-	galaxian_6l : entity work.GALAXIAN_6L
+	clut : entity work.ROM_6L
+	generic map (
+		name => name
+	)
 	port map (
 		CLK  => I_CLK_12M,
 		ADDR => W_6M_DO(6 downto 2),
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_hv_count.vhd
index f310321b..3ead8849 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_hv_count.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_hv_count.vhd	
@@ -35,6 +35,7 @@ entity MC_HV_COUNT is
 		O_H_CNT  : out std_logic_vector(8 downto 0);
 		O_H_SYNC : out std_logic;
 		O_H_BL   : out std_logic;
+		O_H_BLn  : out std_logic;
 		O_V_BL2n : out std_logic;
 		O_V_CNT  : out std_logic_vector(7 downto 0);
 		O_V_SYNC : out std_logic;
@@ -47,7 +48,10 @@ architecture RTL of MC_HV_COUNT is
 	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
 	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
 	signal H_SYNC : std_logic := '0';
+	signal H_SYNC_NEXT : std_logic := '0';
+	signal H_SYNC_EN : std_logic := '0';
 	signal H_CLK  : std_logic := '0';
+	signal H_CLK_EN  : std_logic := '0';
 	signal H_BL   : std_logic := '0';
 	signal V_BLn  : std_logic := '0';
 	signal V_BL2n : std_logic := '0';
@@ -69,13 +73,19 @@ begin
 	O_H_CNT  <= H_CNT;
 
 ---------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
+--	H_CLK <= H_CNT(4);
+	H_CLK_EN <= '1' when H_CNT(4 downto 0) = "01111" else '0';
+	H_SYNC_NEXT <= (not H_CNT(6) ) and H_CNT(5);
+	H_SYNC_EN <= '1' when H_CLK_EN = '1' and H_CNT(8) = '1' and H_SYNC = '0' and H_SYNC_NEXT = '1' else '0';
+
+	process(I_CLK, H_CNT(8))
 	begin
 		if (H_CNT(8) = '0') then
 			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
+		elsif rising_edge(I_CLK) then
+			if H_CLK_EN = '1' then
+				H_SYNC <= H_SYNC_NEXT;
+			end if;
 		end if;
 	end process;
 
@@ -97,15 +107,17 @@ begin
 	O_H_BL <= H_BL;
 
 ---------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
+	process(I_CLK, I_RSTn)
 	begin
 		if (I_RSTn = '0') then
 			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
+		elsif rising_edge(I_CLK) then
+			if H_SYNC_EN = '1' then -- rising_edge(HSYNC)
+				if (V_CNT = 255) then
+					V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
+				else
+					V_CNT <= V_CNT + 1 ;
+				end if;
 			end if;
 		end if;
 	end process;
@@ -115,24 +127,28 @@ begin
 
 ---------   V_BLn    ------------------------------------------
 
-	process(H_SYNC)
+	process(I_CLK)
 	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
+		if rising_edge(I_CLK) then
+			if H_SYNC_EN = '1' then -- rising_edge(HSYNC)
+				if V_CNT(7 downto 0) = 239 then
+					V_BLn <= '0';
+				elsif V_CNT(7 downto 0) = 15 then
+					V_BLn <= '1';
+				end if;
 			end if;
 		end if;
 	end process;
 
-	process(H_SYNC)
+	process(I_CLK)
 	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
+		if rising_edge(I_CLK) then
+			if H_SYNC_EN = '1' then -- rising_edge(HSYNC)
+				if V_CNT(7 downto 0) = 239 then
+					V_BL2n <= '0';
+				elsif V_CNT(7 downto 0) = 16 then
+					V_BL2n <= '1';
+				end if;
 			end if;
 		end if;
 	end process;
@@ -141,5 +157,6 @@ begin
 	O_V_BL2n <= V_BL2n;
 -------   C_BLn     ------------------------------------------
 	O_C_BLn  <= V_BLn and (not H_CNT(8));
+	O_H_BLn  <= not H_CNT(8);
 
 end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_inport.vhd
index 69a20cbe..c10bbf64 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_inport.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_inport.vhd	
@@ -35,14 +35,21 @@ library ieee;
   use ieee.numeric_std.all;
 
 entity MC_INPORT is
+generic (
+	name       : in  string
+);
 port (
 	I_COIN1    : in  std_logic;   --  active high
 	I_COIN2    : in  std_logic;   --  active high
 	I_1P_LE    : in  std_logic;   --  active high
 	I_1P_RI    : in  std_logic;   --  active high
+	I_1P_UP    : in  std_logic;   --  active high
+	I_1P_DN    : in  std_logic;   --  active high
 	I_1P_SH    : in  std_logic;   --  active high
 	I_2P_LE    : in  std_logic;
 	I_2P_RI    : in  std_logic;
+	I_2P_UP    : in  std_logic;
+	I_2P_DN    : in  std_logic;
 	I_2P_SH    : in  std_logic;
 	I_1P_START : in  std_logic;   --  active high
 	I_2P_START : in  std_logic;   --  active high
@@ -66,9 +73,31 @@ architecture RTL of MC_INPORT is
 
 begin
 
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
+	ioports: if name = "AZURIAN" generate
+		W_SW0_DO <= x"00" when I_SW0_OE = '0' else '0'  & I_1P_SH & I_1P_SH & I_COIN1 & I_1P_LE & I_1P_RI & I_1P_UP  & I_1P_DN;
+		W_SW1_DO <= x"00" when I_SW1_OE = '0' else "10" & I_1P_LE & I_1P_RI & I_2P_UP & I_2P_DN & I_2P_START & I_1P_START;
+		W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
+	elsif name = "DEVILFSH" or name = "TRIPLEDR" generate
+		W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_2P_UP &  I_1P_DN &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
+		W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01"              &  I_2P_DN &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
+		W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
+	elsif name = "MRDONIGH" generate
+		W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
+		W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000"                         &  I_1P_SH &  I_1P_DN & I_1P_UP & I_2P_START & I_1P_START;
+		W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
+	elsif name = "ORBITRON" or name = "VICTORY" or name = "WAROFBUG" generate
+		W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_1P_DN &  I_2P_DN  &  I_1P_SH &  I_1P_RI &  I_1P_LE &    I_COIN2 &    I_COIN1;
+		W_SW1_DO <= x"00" when I_SW1_OE = '0' else I_2P_UP &     "1" & "0"       &  I_1P_SH &  I_1P_RI &  I_1P_LE & I_2P_START & I_1P_START;
+		W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001000";
+	elsif name = "ZIGZAG" generate
+		W_SW0_DO <= x"00" when I_SW0_OE = '0' else '0' & I_1P_DN & I_1P_UP &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1;
+		W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000000" & I_2P_START & I_1P_START;
+		W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000011";
+	else generate
+		W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
+		W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
+		W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
+	end generate;
 	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
 
 end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_missile.vhd
index c5aa6633..1971b9e0 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_missile.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_missile.vhd	
@@ -21,7 +21,6 @@ library ieee;
 entity MC_MISSILE is
 	port(
 		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
 		I_C_BLn_X   : in std_logic;
 		I_MLDn      : in std_logic;
 		I_SLDn      : in std_logic;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_stars.vhd
index b91197b3..1c01f7ae 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_stars.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_stars.vhd	
@@ -18,7 +18,7 @@ library ieee;
 
 entity MC_STARS is
 	port (
-		I_CLK_18M     : in  std_logic;
+		I_CLK_12M     : in  std_logic;
 		I_CLK_6M      : in  std_logic;
 		I_H_FLIP      : in  std_logic;
 		I_V_SYNC      : in  std_logic;
@@ -52,7 +52,7 @@ begin
 	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
 	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
 
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
+	CLK_1C    <= not (I_CLK_12M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
 	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
 	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
 
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_video.vhd
index dbe0d0d8..7c10aba4 100644
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_video.vhd	
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mc_video.vhd	
@@ -30,8 +30,10 @@ library ieee;
   use ieee.numeric_std.all;
 
 entity MC_VIDEO is
+  generic (
+		name          : string
+	);
 	port(
-		I_CLK_18M     : in  std_logic;
 		I_CLK_12M     : in  std_logic;
 		I_CLK_6M      : in  std_logic;
 		I_H_CNT       : in  std_logic_vector(8 downto 0);
@@ -40,6 +42,7 @@ entity MC_VIDEO is
 		I_V_FLIP      : in  std_logic;
 		I_V_BLn       : in  std_logic;
 		I_C_BLn       : in  std_logic;
+		I_H_BLn       : in  std_logic;
 
 		I_A           : in  std_logic_vector(9 downto 0);
 		I_BD          : in  std_logic_vector(7 downto 0);
@@ -52,6 +55,7 @@ entity MC_VIDEO is
 		I_DRIVER_WR   : in  std_logic;
 
 		O_C_BLnX      : out std_logic;
+		O_H_BLnX      : out std_logic;
 		O_8HF         : out std_logic;
 		O_256HnX      : out std_logic;
 		O_1VF         : out std_logic;
@@ -97,7 +101,7 @@ architecture RTL of MC_VIDEO is
 	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
 	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
 
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
+	signal W_O_OBJ_ROM_A  : std_logic_vector(11 downto 0) := (others => '0');
 	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
 	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
 	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
@@ -145,9 +149,13 @@ architecture RTL of MC_VIDEO is
 	signal W_SRCLK        : std_logic := '0';
 	signal W_SRLD         : std_logic := '0';
 	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
+
+	type bank_a is array(0 to 3) of std_logic_vector(7 downto 0);
+	signal bank     : bank_a;
+	signal pisces_gfxbank : std_logic;
 
 begin
+
 	ld_pls : entity work.MC_LD_PLS
 	port map(
 		I_CLK_6M    => I_CLK_6M,
@@ -183,16 +191,15 @@ begin
 
 	lram : entity work.MC_LRAM
 	port map(
-		I_CLK  => I_CLK_18M,
+		I_WCLK => I_CLK_6M,
+		I_RCLK => I_CLK_12M,
 		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
 		I_D    => W_LRAM_DI,
 		O_Dn   => W_LRAM_DO
 	);
 
 	missile : entity work.MC_MISSILE
 	port map(
-		I_CLK_18M  => I_CLK_18M,
 		I_CLK_6M   => I_CLK_6M,
 		I_C_BLn_X  => W_C_BLnX,
 		I_MLDn     => W_MLDn,
@@ -220,7 +227,10 @@ begin
 	);
 
 	-- 1K VID-Rom
-	k_rom : entity work.GALAXIAN_1K 
+	k_rom : entity work.ROM_1K
+	generic map (
+		name => name
+	)
 	port map (
 		CLK  => I_CLK_12M,
 		ADDR => W_O_OBJ_ROM_A,
@@ -228,7 +238,10 @@ begin
 	);
 
 	-- 1H VID-Rom
-	h_rom : entity work.GALAXIAN_1H
+	h_rom : entity work.ROM_1H
+	generic map (
+		name => name
+	)
 	port map(
 		CLK  => I_CLK_12M,
 		ADDR => W_O_OBJ_ROM_A,
@@ -251,8 +264,6 @@ begin
 		end if;
 	end process;
 
-	W_CLK_6Mn <= not I_CLK_6M;
-
 	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
 	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
 	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
@@ -299,7 +310,19 @@ begin
 			W_2M_Q <= W_45N_Q;
 		end if;
 	end process;
-	
+
+	process(I_CLK_12M)
+	begin
+		if rising_edge(I_CLK_12M) then
+			if I_DRIVER_WR = '1' and I_A(2) = '0' then
+				bank(to_integer(unsigned(I_A(1 downto 0)))) <= I_BD;
+			end if;
+			if I_DRIVER_WR = '1' and I_A(2 downto 0) = "010" then
+				pisces_gfxbank <= I_BD(0);
+			end if;
+		end if;
+	end process;
+
 	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
 	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
 	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
@@ -315,7 +338,20 @@ begin
 	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
 	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
 	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
+
+	rom_a : if name = "MOONCR" generate
+		W_O_OBJ_ROM_A <= '1' & bank(0)(0) & bank(1)(0) & W_OBJ_ROM_A(5 downto 0) & W_1M(2 downto 0)
+                   when (bank(2) /= X"00" and W_OBJ_ROM_A(7 downto 6) = "10") else
+                   '0' & W_OBJ_ROM_A & W_1M(2 downto 0);
+	elsif name = "DEVILFSH" generate
+		W_O_OBJ_ROM_A <=  not I_H_CNT(8) & W_OBJ_ROM_A & W_1M(2 downto 0);
+	elsif name = "ZIGZAG" generate
+		W_O_OBJ_ROM_A <=  I_H_CNT(8) & W_OBJ_ROM_A & W_1M(2 downto 0);
+	elsif name = "PISCES" or name = "UNIWARS" generate
+		W_O_OBJ_ROM_A <=  pisces_gfxbank & W_OBJ_ROM_A & W_1M(2 downto 0);
+	else generate
+		W_O_OBJ_ROM_A <= '0' & W_OBJ_ROM_A & W_1M(2 downto 0);
+	end generate;
 
 -----------------------------------------------------------------------------------
 
@@ -374,8 +410,7 @@ begin
 		if rising_edge(I_CLK_6M) then
 			if (W_LDn = '0') then
 				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
+				O_H_BLnX <= I_H_BLn;
 			end if;
 		end if;
 	end process;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ym2149.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ym2149.sv
new file mode 100644
index 00000000..1aa73ff8
--- /dev/null
+++ b/Arcade_MiST/Galaxian Hardware/Z80 Based/Galaxian_MiST/rtl/ym2149.sv	
@@ -0,0 +1,331 @@
+//
+// Copyright (c) MikeJ - Jan 2005
+// Copyright (c) 2016-2018 Sorgelig
+//
+// All rights reserved
+//
+// Redistribution and use in source and synthezised forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in synthesized form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// Neither the name of the author nor the names of other contributors may
+// be used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+
+// BDIR  BC  MODE
+//   0   0   inactive
+//   0   1   read value
+//   1   0   write value
+//   1   1   set address
+//
+
+module ym2149
+(
+	input        CLK,       // Global clock
+	input        CE,        // PSG Clock enable
+	input        RESET,     // Chip RESET (set all Registers to '0', active hi)
+	input        BDIR,      // Bus Direction (0 - read , 1 - write)
+	input        BC,        // Bus control
+	input  [7:0] DI,        // Data In
+	output [7:0] DO,        // Data Out
+	output [7:0] CHANNEL_A, // PSG Output channel A
+	output [7:0] CHANNEL_B, // PSG Output channel B
+	output [7:0] CHANNEL_C, // PSG Output channel C
+
+	input        SEL,
+	input        MODE,
+	
+	output [5:0] ACTIVE,
+
+	input  [7:0] IOA_in,
+	output [7:0] IOA_out,
+
+	input  [7:0] IOB_in,
+	output [7:0] IOB_out
+);
+
+assign ACTIVE  = ~ymreg[7][5:0];
+assign IOA_out = ymreg[14];
+assign IOB_out = ymreg[15];
+
+reg [7:0] addr;
+reg [7:0] ymreg[16];
+
+// Write to PSG
+reg env_reset;
+always @(posedge CLK) begin
+	if(RESET) begin
+		ymreg     <= '{default:0};
+		ymreg[7]  <= '1;
+		addr      <= '0;
+		env_reset <= 0;
+	end else begin
+		env_reset <= 0;
+		if(BDIR) begin
+			if(BC) addr <= DI;
+			else if(!addr[7:4]) begin
+				ymreg[addr[3:0]] <= DI;
+				env_reset <= (addr == 13);
+			end
+		end
+	end
+end
+
+// Read from PSG
+assign DO = dout;
+reg [7:0] dout;
+always_comb begin
+	dout = 8'hFF;
+	if(~BDIR & BC & !addr[7:4]) begin
+		case(addr[3:0])
+			 0: dout = ymreg[0];
+			 1: dout = ymreg[1][3:0];
+			 2: dout = ymreg[2];
+			 3: dout = ymreg[3][3:0];
+			 4: dout = ymreg[4];
+			 5: dout = ymreg[5][3:0];
+			 6: dout = ymreg[6][4:0];
+			 7: dout = ymreg[7];
+			 8: dout = ymreg[8][4:0];
+			 9: dout = ymreg[9][4:0];
+			10: dout = ymreg[10][4:0];
+			11: dout = ymreg[11];
+			12: dout = ymreg[12];
+			13: dout = ymreg[13][3:0];
+			14: dout = ymreg[7][6] ? ymreg[14] : IOA_in;
+			15: dout = ymreg[7][7] ? ymreg[15] : IOB_in;
+		endcase
+	end
+end
+
+reg ena_div;
+reg ena_div_noise;
+
+//  p_divider
+always @(posedge CLK) begin
+	reg [3:0]  cnt_div;
+	reg        noise_div;
+
+	if(CE) begin
+		ena_div <= 0;
+		ena_div_noise <= 0;
+		if(!cnt_div) begin
+			cnt_div <= {SEL, 3'b111};
+			ena_div <= 1;
+            
+			noise_div <= (~noise_div);
+			if (noise_div) ena_div_noise <= 1;
+		end else begin
+			cnt_div <= cnt_div - 1'b1;
+		end
+	end
+end
+
+
+reg [2:0] noise_gen_op;
+
+//  p_noise_gen
+always @(posedge CLK) begin
+	reg [16:0] poly17;
+	reg [4:0]  noise_gen_cnt;
+
+	if(CE) begin
+		if (ena_div_noise) begin
+			if(ymreg[6][4:0]) begin
+				if (noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin
+					noise_gen_cnt <= 0;
+					poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
+				end else begin
+					noise_gen_cnt <= noise_gen_cnt + 1'd1;
+				end
+				noise_gen_op <= {3{poly17[0]}};
+			end else begin
+				noise_gen_op <= ymreg[7][5:3];
+				noise_gen_cnt <= 0;
+			end
+		end
+	end
+end
+
+wire [11:0] tone_gen_freq[1:3];
+assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
+assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
+assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
+
+reg [3:1] tone_gen_op;
+
+//p_tone_gens
+always @(posedge CLK) begin
+	integer i;
+	reg [11:0] tone_gen_cnt[1:3];
+
+	if(CE) begin
+		// looks like real chips count up - we need to get the Exact behaviour ..
+	
+		for (i = 1; i <= 3; i = i + 1) begin
+			if(ena_div) begin
+				if (tone_gen_freq[i]) begin
+					if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin
+						tone_gen_cnt[i] <= 0;
+						tone_gen_op[i]  <= ~tone_gen_op[i];
+					end else begin
+						tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
+					end
+				end else begin
+					tone_gen_op[i] <= ymreg[7][i];
+					tone_gen_cnt[i] <= 0;
+				end
+			end
+		end
+	end
+end
+
+reg env_ena;
+wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
+
+//p_envelope_freq
+always @(posedge CLK) begin
+	reg [15:0] env_gen_cnt;
+
+	if(CE) begin
+		env_ena <= 0;
+		if(ena_div) begin
+			if (env_gen_cnt >= env_gen_comp) begin
+				env_gen_cnt <= 0;
+				env_ena <= 1;
+			end else begin
+				env_gen_cnt <= (env_gen_cnt + 1'd1);
+			end
+		end
+	end
+end
+
+reg [4:0] env_vol;
+
+wire is_bot    = (env_vol == 5'b00000);
+wire is_bot_p1 = (env_vol == 5'b00001);
+wire is_top_m1 = (env_vol == 5'b11110);
+wire is_top    = (env_vol == 5'b11111);
+
+always @(posedge CLK) begin
+	reg env_hold;
+	reg env_inc;
+
+	// envelope shapes
+	// C AtAlH
+	// 0 0 x x  \___
+	//
+	// 0 1 x x  /___
+	//
+	// 1 0 0 0  \\\\
+	//
+	// 1 0 0 1  \___
+	//
+	// 1 0 1 0  \/\/
+	//           ___
+	// 1 0 1 1  \
+	//
+	// 1 1 0 0  ////
+	//           ___
+	// 1 1 0 1  /
+	//
+	// 1 1 1 0  /\/\
+	//
+	// 1 1 1 1  /___
+
+	if(env_reset | RESET) begin
+		// load initial state
+		if(!ymreg[13][2]) begin		// attack
+			env_vol <= 5'b11111;
+			env_inc <= 0;		// -1
+		end else begin
+			env_vol <= 5'b00000;
+			env_inc <= 1;		// +1
+		end
+		env_hold <= 0;
+	end
+	else if(CE) begin
+		if (env_ena) begin
+			if (!env_hold) begin
+				if (env_inc) env_vol <= (env_vol + 5'b00001);
+					else env_vol <= (env_vol + 5'b11111);
+			end
+
+			// envelope shape control.
+			if(!ymreg[13][3]) begin
+				if(!env_inc) begin	// down
+					if(is_bot_p1) env_hold <= 1;
+				end else if (is_top) env_hold <= 1;
+			end else if(ymreg[13][0]) begin		// hold = 1
+				if(!env_inc) begin	// down
+					if(ymreg[13][1]) begin		// alt
+						if(is_bot) env_hold <= 1;
+					end else if(is_bot_p1) env_hold <= 1;
+				end else if(ymreg[13][1]) begin	// alt
+					if(is_top) env_hold <= 1;
+				end else if(is_top_m1) env_hold <= 1;
+			end else if(ymreg[13][1]) begin		// alternate
+				if(env_inc == 1'b0) begin		// down
+					if(is_bot_p1) env_hold <= 1;
+					if(is_bot) begin
+						env_hold <= 0;
+						env_inc  <= 1;
+					end
+				end else begin
+					if(is_top_m1) env_hold <= 1;
+					if(is_top) begin
+						env_hold <= 0;
+						env_inc  <= 0;
+					end
+				end
+			end
+		end
+	end
+end
+
+reg [5:0] A,B,C;
+always @(posedge CLK) begin
+	A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4]  ? env_vol[4:0] : { ymreg[8][3:0],  ymreg[8][3]}};
+	B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4]  ? env_vol[4:0] : { ymreg[9][3:0],  ymreg[9][3]}};
+	C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}};
+end
+
+wire [7:0] volTable[64] = '{
+	//YM2149
+	8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, 
+	8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, 
+	8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, 
+	8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff,
+
+	//AY8910
+	8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, 
+	8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, 
+	8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, 
+	8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff 
+};
+
+assign CHANNEL_A = volTable[A];
+assign CHANNEL_B = volTable[B];
+assign CHANNEL_C = volTable[C];
+
+endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qpf
deleted file mode 100644
index 38cc2338..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qpf	
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
-# Date created = 17:34:44  October 10, 2018
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.0"
-DATE = "17:34:44  October 10, 2018"
-
-# Revisions
-
-PROJECT_REVISION = "KingBaloon"
-PROJECT_REVISION = "Galaxian"
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf
deleted file mode 100644
index 0dd7647f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.qsf	
+++ /dev/null
@@ -1,194 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 21:14:56  August 16, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		KingBaloon_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY KingBalloon_MiST
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ------------------------------
-# start ENTITY(KingBalloon_MiST)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(KingBalloon_MiST)
-# ----------------------------
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/KingBalloon_MiST.sv
-set_global_assignment -name VHDL_FILE rtl/kingballon.vhd
-set_global_assignment -name VHDL_FILE rtl/kb_synth.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/prog.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/rom_h.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/rom_k.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/col.vhd
-set_global_assignment -name VHDL_FILE "rtl/ROM/kbe1-4.vhd"
-set_global_assignment -name VHDL_FILE "rtl/ROM/kbe2-5.vhd"
-set_global_assignment -name VHDL_FILE "rtl/ROM/kbe3-6.vhd"
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name VHDL_FILE rtl/ttl_74138.vhd
-set_global_assignment -name VHDL_FILE rtl/ttl_74273.vhd
-set_global_assignment -name VHDL_FILE rtl/ttl_74367.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.srf
deleted file mode 100644
index f79ee3f7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/KingBaloon.srf	
+++ /dev/null
@@ -1,56 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 113007 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 113015 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt
deleted file mode 100644
index 7c62e33e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/README.txt	
+++ /dev/null
@@ -1,26 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: King and Balloon port to MiST by Gehstock
--- 22 October 2018
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
-
-
-ToDo:  add Speech
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/Release/KingBaloon.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/Release/KingBaloon.rbf
deleted file mode 100644
index d409f213b138b678030d8e360046f00fa89edb8e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 333436
zcmeFa51brVb>~~vE<__H&|MV0#n4Z54K<=|WGop!o|4BWuG@24?lEoLBL*_-C@>>N
ziD4nO67mU~&3ox9-L__6ge4+aZSVuh850p87~&VQ8xp3io>+bnYl)bwKRjNr`I!7A
z@rXxWv;^?`p6V%kEF@d9$Gc|HwbfO1>(;&Jo_p@O=lt%ennxdf^7PJsPSgMUFW>%`
z?|%2x>C@l;{`ddu5B}x*-~Yj*|HAL-@BP=)r@wdl2jBhfch`R8$t(IF{;or6lU5$(
z{9<}~9PpOY%BQouXL6MK@}!l=m2I4Pp0$<bCnQbE^5rPk7n-D=l_{(LT*s`v?7loJ
zZD#p$yigjX{7M?+Jgfg)$E>~VzC0uKWcg3`nALZ_$E=;KywD*jn}b>YQytG$Uh=ba
zW*w3*d1oGXk=Bspm?KFUp-GOCB=5}Bzw`L7+|SBpxmjLzogG)^OS{68?4BIuzNGB@
z2uaRsq%2>qvm|+v<hp;>KhN%G$CdY1o@e*vDES#pS(#)xW%uPMv|LNd?qx^GmvcF0
zDZAGoW#@8~dZdlDB$?ZiBri+CmjRNLc^^rhX_72S^5wo<iyS{$+Cq~1_2ne>WJ!@O
zSx)X5sYsHn&T`6b%QN?o_K@V3(9>H^e@a?;zVbTD&yE=lBP6MFrThsG<h~pWB%dVx
zl_Yst>gV)-g$_B(j?!m2m!srMl5@$+lH_G{WbI}1BkOP0R(6zUL`H<JfRsHi_hk&_
zdCB{~NSO>QkR)$qlDsTs`BFYR&)Sot$Uv4dy0SjV{j48SpR|97G($Q@`Z6hN=Um4J
zN!h)ueK}5&D$7aQktB4;QL^RuDbgG%A_;Bs%yE+Be}E+S<oavNNzSvB<;n3cNh_~g
zXQX{3;khJ{hyGciAT&slIUz~%Gk(aN%jTExL#~A<a+D<J6U(We)6e@V=>d}5I)jXs
z)W5QQxfb5No+Nb0b(U^hPLeOOAv_iN&&KW+QZ^r+Y_8nDoU*b~Pe#{PlC+o6lpQk~
z<e1SR=OO84l2j>l%#-9ObxU5>#`zqj?O!4ZJu>bhd(y_aQh7OL_oWZpNb5*)OX!qq
zkq^;rl2)GgbDGV6Tu#|NX@C2QbmejyBFU-TlJhM6-g1)b%SdwkI7#@hGOgr|<UdTx
z?hAhokg{tz%KVii^vIY?%I2*cg%%kfX-|$aKZF#yCvqy!iW~?nS$Z<LIM*0S`zw>Q
zC#g?S|F@sh|NWEYBv%=~gvCNzmNK5NJPQ9;Cb_rrdL<2VF5`YS8nV2-Bxx_BO=Rl_
zq>KhR%JoyFm3l<Zv$>KTv-Zw)%-YND3+>XkEMM3qG)P{So{A>9pS7PIWsS||!kN60
zwncYJl5^1?ZzugVNn}mdUpb0QX6ZZ2Nv`EI%g>H7$99vXzAR7X?aCzgRwn8D%IiKw
zkJBV{3msYdo#iCgLZis2%p++}j(3rSHaX9d<cUto(#EqS;hD6RrH_$BUu4&^9%Zzh
z?RX#QR+7l4+?Vw!%ai;slB7=IvDhS%UQ2q(8A<Z8B)5bHNkWI%145^)9S4_Fwhqf$
zBT4S{&-%ZAznsp@6FMaQ@^X6Rij=j#@+kC6%JPH`k^Pi7ene*FI!i0(>DkT&{CI>U
z<DVs=X9XE&J^jpb5;~-SkT3N}w$LZMU)f$pj~rL#pLw3qkg0j$Yi5Ip{>+l-RY_u_
zNs@fImbL0Fq|$QwC`qox?vUd+NobIxq&Jh~D0z~E9<d)YI)uM+p3RMn8FDT9OO9d>
ziB6LwbNyu`v30*f%Is=6E<Q;*Q^)@mN%Ar}vZJ)OGG(-7bP3--O_DMhuVnoZK1h=D
zEXlR-W##eA^GvRU4_T5qklAU{cWEo5L+;6S-%1-85FV{3NuI31qTeLRxQYtdK$3fs
z_a8`Nw~UhHzSwHQOUV-(Et_jnPV&b{D`}FpCCPl1qui6D)GtYRBT3H1c9f&E^U38T
z=bs?SQG7A6?d2$T;%|}UJj;{oEQ!ozNn|if(zc|G4pDb<o$>TcI;4Nnc9t@_L}!S9
zEXVgRr#~ZoWI1JdqRZa2oP-CzNs?oh<d&QZ4U%M?kR<f>bNYGN*a@%XJUfbACg(Si
zt{}<1>qwH9t(mVO$$BnH=CIfqA_GsBvS)=KA_pQ%BKxv#$oe8luAeH&nkgwOC-sOf
z%hK<YGJPdS$<OAE9Hmc^<owknIlhV{vLZ?7kfY3HIf|Z;JUPm>BsrJ7EJ>b>izJ~(
z`Y85u=8wxU8=oxi#iUn|vV0l0w~-`IlB{2HE&59AXi0MZR#N|}|GQGR%GgQ!D^u2<
z(3GVtPma=#BsmwFqz`{i61mEfT%VavoRLnFR%WfFLC!_?vi9XD?Maez(P1KAqFY7R
zNRoN~|BxgvOLF~GNqDp}$()tBnI&oOZ0UO>nR_emi7g@NY<ZIZ_2nez7m`-ick%op
z2QG5pA_vZw1ET*#pFW{{`w4LK6K<X5A~+-Oi?^lL-HKej;`{<n@4I#20-rc{@ui;`
zJL6{Z1kCu1n@@hZ^t~tO_9rj=RCj;lrO$h+BIkYohkJS6kN$AM)h8?j9~Q1Rf-1j-
zR8-ph)*S9+DamoB9I^^tJLfy803}26oIG5a@pyQqki(VIu`}d+<~MTbBiZxmQ9G3!
z&vRa|o<k)Csr3nI-&TrbsS>$^D<pSGf2$q2&LL_0#L#r`vLTALijI>6-l3t;ck14?
z9wl13QF8{}Bp8PpC-J2e&!h#~L$?<ltuC+CF3VAU>2o#jP|<gs8-`t{a(HH<ws~mK
zZC59T4)Lt6`?<?<^6*WclnF?=hR{|kO2z$IR&kxS^yRT6eG(}a9#wX^!ZgR(SCe0P
zc&6g<@UFN`F%`9Q5B}#D%B@vN&v8Lpl|DMo>d%0Sgq=SJF3Q;X^QvERCC5@_aG@2f
zEWh;e+gDybv-68H=|cH;kz*G*b`}oE6yJ50{HK$ZxL17i*|e~q4o%C?{J2PeMU1^w
zNx^-8yk=D@l1h-W=PqRz=Ak|rPm2HWK5kcBT#cw^a!y<m>v<&K?2n4ycAer7z6##Q
zrJl3VF4(lT3x2@);$N@YILp{PS)VTK9`kJV2Ks;b$b~ijWTl_u3ING)QYRL<aF)fw
zd4`!wfAn492(EB~EcP9_Wl4OdnP2?mi)GPxHmZKfi~Y+-ULIc-oxJicH8do@uRLmR
zs@|odqn+QVe!S#wJKY(2XLRzHzOZ<^PuZW{aM?rZ^eytt8ONb@_NL9x*~f=+Li<qj
z^ewe(hwi3_^Kt*;b30S!KAAM1|Glq&cJ28Weu|Q4iq+GVCqA<RA9;#~pX&B%tFWhP
z@4WA?B4Gvh&bO?Z(l0vyrgPq%$O<Os8nC77zL1r9=Ewiuiu%7<FIR1y43@re?=$Cn
zR>Oa9{%3Uj(D5Q+Kg5!!$XG3orEu}PyQ?O!&eH$%$<<p(eiV)F!1+w+1y3=0=YLyP
znTtOB`SXjC%M0_fVZdS=)4(&d-Ou_s2EEL|v)+4#nHx`4#L`X;>X*kuVuD|FrI@BK
z53byHde8QEM%~Was<)T?%kRP77TX--yKi2fc^vviYK=cvA0Ija?N6|`moHxa&#S87
zL>wdedB$n!^xIckTRvl&sDM>r=}l>zXTP@i8CJUVPpgYVJVSCGe|!~<_={VBkF)iB
z&sNKdk@i+|rF3ro{ncH<&zB)jS#GsC_LL2tZ-G@NY}NJk`S#<<%hAi#vc??eIga0~
z8l-(r41DR|ec;L2eIa*OSpY9u-50|Ai&l3PcC7^XgP$6>2zIX?*qxmE+P}Flfqb&k
z=!%&qyMH0~3MYSW)v(*lcfFAI&s}!4HR8Ejy1+XZ3A;dsJ*T4!SItzr2zFnnSgg9f
zST*Bz)%Eprm$KDbNeXW9`#*~WoYP!hHG_OLV@#gbcH=qaoR#6CIyonI&U&N2m_9>{
z_^gjVyFn&&=B%wg!%P9vFT&ktm6WHIiFmD=>J`LeRkUTgYgxSd?azN&T{`2TB#nLe
z%wMc(FwGflJcG+0A!C`Bo}O-c#ow*USf<TC%b<S$4XdZs(Xan<?rA-Dwudg_-Dl&<
zljS|ja`9wMKl!~M8^WG@D@i&q-yh`gqh)rly61P%?0)h&dgk4WX7>}}?$7+rB^U8-
zi4Izw6x{T(7d$t$<wd;vf=BpA$b`S(zCHH9kBt#?aix50%+KrOxh(ywreZJR-RC6>
zPbjp!lB^o6eNGGh$0E+;$0}y+VsLl=^<w8@aCiJH1b06{O(jnkvs>E!s`jddhOB(2
z@@Z3)_3Le~_#gc{Vgl-4{gsQ5em3IgcYH3JYUkI3^C<OW<EWemFV3&XMUI^xpB^vu
z9Ou|ME#+0S#aA=LWc9Fa*}7Z$@anyb6r5P)S3Mt>pl5jYENJo{Ih$Kp_$(295$aw&
zsQWpqD~mV1^x`MaE=&(S3u@=W2sl^ii-etvGv~^OV;7O`b1~=a`Ojq`yNGn3eaz08
z%V4fbtfDk<5$TpiezipK$Lm|9&yod;R6fH<>$5)oEPlu2;v1FMuIA?hSMFG<b85l!
zy|MJ6kFFlp-T&;<`8NF&<$h>UPWTMx(@lH+<gq7J;;mpCl`hw-^<zb}Lm{pnFINc8
zY<%fkzx!DEA3jO{ECtz**SWH`e)i+FQ*iRn9;-z4|ER@d*PIA7O3FX>3>6nv^n<@J
z#@&^zIZN~3d#nncmnWBd+CS5eH`C9Tr>Qf&;5@BN9#lLl{Ym?@^t10@QLE1SNnToh
z`QGE_kDtjcC70BuJu1#_Ej`p+ek?nzs8wjr3T7vg#Xm0jU0F7J{-Z~;vz5n`cV{au
zg`~b8PU#~zeL>}x|Fnp568@}PzpQrPxfTvc9wp_FR#cEb_~vP)_)8)QN6M!ir$pc>
zp5Vc>4y~mD>0Uv9=jd-`?We7BK^eK1rhc1T>wZ;fCN-rMq|(_h3Tyl2wI`>E`y0RN
zuBZTN=|eimJgHJPE>{f^LM}~kC%utAmtH=RJ@UZPhcg~SkAkZHK%^bxqTj)S)F+7p
zElbBaTh2>`?eTWfa{S!<cLPbfaYwNgLY*=#l^svWOP}jYU)s1duhOxV&Ml9Fj25N&
zPr99QCeh#N&GzeGF@03p2O5XHLPz>TGYlSA%k-ubLzwmi{gK^XdTl3`M@a=QB}7gs
zE*)R~ksQg&Zc7iBvmVb(3#AV}XknSKLI{wd7I}L7cK=L%(@Lb$Z15#hn$C!0K(h1T
z>YsdJELWtoWBqc=qzdECBseW9rLvM~#^XPC{^r^!8WuW*MiG6P7ZiqC1e_Tn(<2=#
zIFq&@vnDO!A#w;IlSL9``*Vr=<fnDX=+eJb=*i(PsM6oy(b-F)s80fON^Ac3E^QzL
z@>n|BBHLs$fQ+*|L@pyIa+4Ng5T!P%7FyGZD(v7y8sHz4%413Jo%N46Y4_4nOp)~e
zv=HT1{*SoJ0IkegdH#gwX^eX-o`AyQqksQ`c$hyhBxwGd<C>`jUOY0cFZER2lP{Jl
z{&-N`OLXiu$F%e2tKy(qAJ@rHS|t6ZIk#JIv8APovGv;U!Sic0HPk)%w7J}?2aH1O
zUKgYvMEAYqu@9do<J_eKOE(TBTZbayZwn&n5sh+>6A=z+LS%<u`9nysD&>ffCja0s
zw^LQZeV(L7c`Uu)R9fJ<w4p1jPAoN$U^Z>ZfKXjpPu3_U3;i4+gvu#O1r(*~`toE;
z=akTzB}!12^RbT&^gsDV0XonBQj%w3DU`|+!jxpWfwX4nE03pD_9uz_rp;xw_q*W)
z4|ei#UlMshm_>!sGpRhSM1JUO%Dt48QZwoCrt2~#`02NpQYA%HT2ERl#UJ_OwXLDF
zaSBMC(n!iyDoS}kMpjrTmqrlbjQP@Z+C0^!Ln9Pro#r{I?#{bknErJusTdabE0jv5
z9*Xzd>^CfB(o!-q-0EMaO~~nTvvS~Js&JfJe=aArBbIzrUD)|<$!+GLmBy567imKA
zy>%K`zLh>l%WanyR(^?Ho=iNdDu{qPCu+2_V1-m3PP{k%bvj{jz^IS*3kPaxQ|atX
zw-!`go=g9XRx>ZeaQ}z=wX}GMa-b2Yyj&PYE2&@<ysO8apHK%+wIEG7`?iSu%D3D_
z_5&~Eif_F0``Df3`7U=f1jykXQdBDK4^G=95B8u&vOB31Ca3;l^ToGg|Cv!*os^vV
z@cz}QNorZ)sUS!!ZR8<T%Lap7iIB@cK0&GU6^i`IEwPoPsFdxe!m0cJ@8#390+~(y
zDnwY)BoFh@vIH+19%;KsWZ(Mg|57@wJgxqb|Fl*_H%t9`(-MyrPVe<=UM|+}R`v|H
z`u*u=Ed5C%HC2*^UYAb-9rzy7@6igSbP`P1wEg6<s4AgOD1z34WR^UiKYCYjMGwfz
z+;&qo6vAMDJ@53nCH=a>+CnaJbevj6g}j*-)t=-{A!n%Hz?KfRqK}pvf`a~%T!`I5
zkf;8n5sJp)@9D{(9&~Jy@A9a1Y(1<-s2OMJmY2q+;Md?!M188BQ>M_!#XMp-%h@Cx
zNE*z~USIvCJrZS()rqF@v^1sjj`AyRfu^+MtBOJ$&`Ke%jMK8V?H(_NGfZ`7Y4g_$
zwOUT|w+r)5YeOm@!mY?rhE{5Rv!Nka=L?|_O)&&X7O^DkuX_b=A%uK}Fo{*(=~ATa
zhC0-ane6J_Mel@lA-v5!zfg5Q_7Rs_`p%3DyE65)j*wZ%@k?K*9~o_MOH|QvO1zEI
zh}Cq-vpgjE^v^LH!%5?`mCi##-eH{7qX%CY6>`v+<cD*~i!jt-3&m-zkb`_fbHckc
zkx3(3&ZV(b64DidOsbaz2kml^w)^P&Uevc2QVP=hPGp@z2<4ESjs;BaKbTJ|PAgAG
zJnbB}WO`t0_A3pgpW6B2W;e;17-=Yk141jKEwxbTT8&WWc}NUMGSb@95@KwMbxU<Z
zB6L`I2H{OtA1%VeL|d2a%9yRVa8Uk+WAdH*-a}QiU&wXqh;7F+g@D1-zLyHKHw-W7
ziZ)WIR1U?Mw9*QMri?0tI-fN1)-N?0aa6=0Y&7zwGG$6$$1CO4$duX0A8@yR;b5o=
z1HQv31xx?&SCFWDEHgi%0Y<Fh#Wu2q7ul%ZppuZ;Vm19{n1n`Q0Da~N8-xy-D6DQs
z6zm&uoqd5p{Zv$#Ps{p_@ez{5yZX8p53kX2z2OG|6KT3r%XPMFVY=G5;}y2<ij9H<
znNE3?va?@%dP*bdQ9G$-^TR?MxvBV6jDiT?YGqaE7aI9WF?QQ-a=QFaj`OhX4d*+#
zs8G{hge(?nxp}IJ((Vf7lBD7USAlBMc4auB9JvWKV@D_J`K~Q7SD7jcK~MQi>f<5e
zs#S@x44p52^%4sMp_gA39Zoz3P&-lLE#~IcG&hogLK$(C`ehZT`sE~jER@j<1}-X@
zNnM#QDr^@AdQNEPRKN@r#l_qnJvH~sF(sXOZH-m)BHGl*A&UC-6$Tt*ZC1Gql>9Fp
zOU4_>cn^7V7J{}b!<kQ}jZWwxBFJAfEo^Yx#iqAMEq&t+5Q8FRnCsz06``y9foBv9
z%ynBet5Cq6wld>UmC#Lplr$=BiPn=d+ZPhauF!-ex?vFpn(HRsq%ph4!dLwE3u7rC
zGb+Ndyiqib;C8K3N3EjbbR(U?X$?|IsyWhLEm!HIi2|o9nvA-QbZ&Y5puo~MJ`mSy
z<+n5rA3nUe)edjF_Kxw}d&2`$!{fIw%eoKMCx+^4?eN4<hr4C1$8YcUI$l@T8>z}*
zY9qU;fXKv_xu**Fl|qH?_8g;)4Q;5JMb<a3^e$B@KVXacSb1OIcit1^yT?_qp&P2O
zH#cQWGlIiyrsQowX<P8G?kJQz8$TS^*T%Lr-_`SKNBG8|JP{Z4VDsAA#Er;LT+h`9
z^VS-rx=O(jGy^IJQKFL!1M<Y^qAJ8OEtCfe6OFE^sLg@)HwIzhKv>e_jr!(t=PGjU
zE#~)yyIozsQOy=_E0-EG5Y;`3wlHDoSU7v?Z$Ficf4nu*8DF1F9NUrWOf=+&GutV9
z_KtP@%e9VuGiUUUwcJz`C7*wCAqs&1Ma0keztvC)1sL=8R9Cg9SkQNdL98BV6z!DJ
zDlBpL@t?tmOfet!x`&GE0<{qCQR*e9Ui!t>^bVTo?YPP}Us|^#*gEr}U)(;tzgoXx
zI_msdGdxi1OdN6Usdm0v%P-#WpPhOM%8%FMv6(NGbz$P(_4?$@)?@g^*<bX+hbV;O
zJ#oYQeF1K2eZ4lm_Tp=7T`HS#?wfU+`7f0n^M;~5RJ^aNXn&?YU+jd#+lzBK>OQii
zahLzF8MF2H)NP?{9x2l1#*p$G!@Xs-bkjGWqc%~ElZkl88q=AWj_hJ7*Rsm#48qiW
ztGYPQnvR^sZP2LU(s6j&t*4U~@x^z6naCP$j3_1;3Cr^j8W#qZJ%1f^5AG}vv}PdC
z(TwdOD40<<hY)Jv;-I@YFbFKLH{4^KTel3vb^7q|u<uWN3${%hs|WtXyo~Xj)7g6a
z6qSd$#cS8)QttJn@NrG$jxnhlrJ)Jp5H-d*B?z;F;cv~<y<5%LjI%CqZsso~7impu
zx5dyKRQY;5Wfq&PO0fD?qflv;&jzf1w;Ffp`+x3S(?}+o@TswNedNHZ8>6Vh;ySoC
zY52Lqi;}IisMSmX2E+^<0yCJGB55fpLKF%Cx`eG0dMOM$`K7Q-_TbJC-jL_dDbL?y
zlw&%f7uvdo*09Ag<(-(>S<Wxb{7P%uv5V{ctuysO-*0T8=SS*mj1?Aah+5S+YQ1X*
zGcIRZjFd2CQ6u?H87UI3I#W<a3O>nraTJAjUl-<w&Qdv$r|Pk*6dV}SdeE&;Xas$X
zftzL2>UzK*9TVF3hR)SL@Dhl4>rgWBso|VS{My93BCJ$snMO%6RMHBxYR4?%Aq#rL
zp|62y8rGy2E%IOq<g||0J@hc0w~N>^_EZ@1P^+Qg(8Mtn&biEknf61<Ju$N>bZ$EM
z!n*IZ5R}@)ypBx$tva%utuZUPvshX)KOE*vXP^~F1*VBXFD`mXh`G>T+eAY83y<d1
zNm!LwJRG6)8p>i4bhc^V^jUHIP_fmMN!7@Qtg#JG*no70-W&gYG9mrUg{_!}udF6p
zw?w$W^y-8x3ds#a5x%w&$yf;luq=savev13CkF-i+MRsim~|K~=+NrK%-C_(F7xd$
zWctmROKF~tEZDYdogSnwePuie!&;bM2w9oC<5k<$g~kIl>@v?D&nM+v60-88cax4!
z*98d><U%wbjKH>M5TFWLYaVObvAN3r07FGVS7_Ri(w*(bvhH4LUEAItHuJt#m7Q39
zyD@2Aao`2Fl-DHV>)UF4z0(2_!)^w!xMPiT`7PoT^mgRX1#NtY7JpM+8a=Q@#yy1^
zh;wVZu%HhobPm)+`8s<od_n(;5?KIlm^6vGL{v`W9jOwQ0zI)qxWDwP|8`RS1AnRQ
zHE7>=b6o%4@c!4`rQW`KZ~7PBrgra5|HNDAfeHB=Z&T*e^4BIfq<`eCd-?;*f8<S$
zuL*DM|JAqkr^EEmy!{APQoC0Ec*Z0A<+pxsYS(_-ezhWonOJ9qM%WNX$=Gzx_YEC%
zrj?AdCNWZ;kbM4fe8ogY%-W@|?|s6(XLOMUzF@*p3C6=i5Tu4>?&M<rX;f*0tRAif
zd0wiu#686m;X>3|YUUxuZFdCH3Ufsa#>C<{H>M2^2sjyXUcs^XjdjnX4IUHAvAotv
zN@BMqIc_8V;y@vm{VgQglIpo54dP?qg>!(J(r6Wv8mkMBQv0bwg|4Kk@=KTfD#cMi
zVlKw=EVZK<oP<SNCOo6T^h~>v-b5WqmuQE>q_kFXF+WpZkN%`;!g4K6t6uuKH*@M3
zJk&MaRs+kJdEBV+Ja(>b7llGht;EAw$s3#@OiiEPk)kw#wn=R=d<MAehsOHOs2kGp
zfe;Rv5D(v1)(P9j?bsr?#%|a7`t3i_!EL~gl$K+YggOVWU`~Fj7Zvi*idx3Rgw{~#
z_34Dz&sH;)t<zR84j{zubCND@3<`N>K2_3`R7%f6=aE-F-{AfPsMOZ_mMt_VVvE-|
zu}j!3ory}@c1h8Nkp9*48jF^y+O+6|72`TMa|nWyTourAdw*cCGyIZ=E$_paN!1%M
zl<;lSRmPO?C)+MA+6HBfQ8Vs|4KHwp8@S66PSA^RDYk^Q2F9{=<~Pz%oYcG+avEA!
zU4t73^$dSOH@t8TH+G=y_6ijDlYGcPjM<F={4(P5B^#92Ri$1)*CD*o*c|Lu*1ayg
z#+ZU0n1!lfqJfeOf*JKUfB9l@$#6>mHu42O6;${F?h#E>94y2*$hb*`w4TQ|PvEYM
z2P3L+1-lHhNC=eUM6p&eX~bewAz(m=Io2-Ts7fJIqL9Dy>n{-2c5<xRtW{QeB;0Oz
zttx9{3f&-ANIZJOI`}Z$=7)aLhL{q0JZWzG+E=4^4e0h!q}PZ`T8dr9A1YK^914Hw
z!ygmj=eeAoR#Yc+&bdi|S5Fm4Ay`p1F;Zz^dL@v<pv$}{fO2t>rWTkTjue%r<Im0S
z)&4B;B9(;f3N>=vfJMUth0tdug&BAx%yh926AcK4<oR|Xqz6p;2C8HsC=9fVUuzhb
z$vIafKQtAWbzO9)POyl8g9dbAS}7eG_zFw~Lu2=fp-VQ}&YB*S7uF01LFivA8pMfP
zLp`?MN*<$$JyKDEh5_FASTnsszBe1~5Bz3irexwWTRmJLoO!>?vlW#eaW%df<>_N`
zAn=n$)%8`{XQQ-5<6x;Z9yz^+o~9^bTo~kekqal*v1!$Mg=-<Hk-A@W+DlcEXa_nH
zyCGgY<t@Ys9uX#t2&p}WfQzX1#Hob|1&^89?gowpb^QG2sXXrL7{1YN9g<=8`%ty{
zWPl0IkS5`Qpp-X|(T+$cNz^c)9#A6vL|x7@S@NT<r8&#sRb0bd7n_O-5h`XYItOX<
z+p5v<9(~_WXh@t-)*>JUKNrKw>B0d&hSsDO<e0pO1|p0AAzKtp=Y>c`2o`}x0|A|J
zM_pq<Y@iB_#xL+g;YNd8`E$h?*A`}s%pk_-z2Ea}%-y)f?p|w`no4pJ0s+QK7{!Rn
zcWU{14a*kp!vPJ!3S}V9wV?uLV4=|zz*LR6c>5tM8V@U{6a)u?#N!GXfU^TEXeq7D
zO+mqH0vj*A{1*T_P**yIG#d;TXpKUhq(drLhCIkT#F(bx1PO5%E_f%b$ZJjeZTeQh
zE|W<w+^oP!n1B>;X_=)!yQ8Om@$Pi3%iY1w(7f&{cxnozD}zFAI;rIfOc(%vd4P%T
zjTA%C@R~;KoSQZlGVp;{56g%TTxg@okOzcH<$EZDHr!@#jSn^fF+sJMUwX}}QAj!`
zm=P5*RvLvfh)tpZkz`JKtOSWLwJ?JRgzXvntapBb1S6Xe-Y&+nxK$zp4(>@$Q^2V(
z<2u&?L*?r%y;3!H$)A7J>1+w#a?9}Gw%FPoYwOoGy&a8-8q>xUZX0}ec-Te{cea$8
zy<kMu0B#D+a<6>U?OF@Mb}ZaIW^K1Vqrw}FE_uEx9SHXZb7Ku-dwR4OG~W||oos6;
zixMr}R<`xLKW8?D{&nF3GkR0lWpo-dDnB=7XE&9b?%se2HBx*pN`7`fU|F}kJ1XW!
zO&6opjH>VLyk(<RJ0`ZbhSYq^PE8$FcZ{P^?kEiyHN5TiZ=IZ1`KWWC{Ln+wp_---
z+Zy$}I$qS}AiOQq+RUlr<*r`}ZZy8?FcOLd3zV^WJQ&@NLw7LLBT#Qjx)&69!uozk
zH-mUnU`u+Uq0QdFr>(Hn@U@*Zm6HvSAZCpz9t(Wjf#&{jPJOL$s(JN-1%&Es19bs#
zX{C6JKrrI%-%-L>9nMX5znL?o6r2&@<XF)Y%tVS%eTJQc`LI+*-v!<r_=;!u27scS
z0P{Zk!QqtBX~BUogID~tq+KqQ*4#&9tT|LHl?Mi=lzPyd3IpZ;(MNH=@Qrs|>31IJ
zjcs>6^uMovi@&#8e`^ZEG(k>o_^Zgj=SbAd-+FlLAES+dU^O_NU<~3+f9aZ9u(t}{
zF{pm2F`+O04xZ?^9t1vFu!Cd0x@YR+y^Z1ZUDwBNKU5qX`_fS9v*DYL>%p-jdu;tK
z{|=nx`Qm-E>X;oo6_yvh_ZP2MW4+c4K!*SkgT?UD?Zv&D>-iQB?5nK{3-iT$W(?@e
zeagKve2BsiA|!h0zHg+Ru{-dJ$2DI54*cCu4MVTM7uOyt+BkYpja?S8wVvzbsa*gD
zT*rEIzL;#&_>s-J?E*K1;@pPL+^KRPJI;e+^!5G4o(l0R_26g2v17QoGZma|x>Opc
zrdw4JZfKNoUM8v!hh|wFDPM_DH1y@>@JP|Q^|zj<S&)tZiyYapruDA+8g^$uZa^Ta
z!|QIxZyj;~6#fnpcX$9y)XWcrSz$IzbGckdS$uLva0cj90yBIm(9Yt352a4HNOx!$
zFTB+hj?Yv!g^K`7!8kQRJOuO(6-}2Rn881ssmDfvsie|@nHJW)bx5*z{mTdH@3CGo
zu>~GPSP~YH3-xvf`YBo}mpgtAZ(djp3D~uX)Qa<O_v40Fiuu-Yv>~JkGI6YZxQO}+
zgds==%NT9TsyV3;5rI(fzyT@MAljNPQe6mxk?yuz_x2cP>GOZz(s6{@;!n)PPUo#d
zk*&Y==Vd6p`8#f?`SVVzdN^WrqXE`PL6}g0tr=lXi%}B2$;n1~CzzWcX-;P#oEt;L
z81WM`#k{|ln@a&8TqmEh8=Rq1gpr<EqyX&ZdVd)`#*j~%>sdi=`pM^~$PI{yv@4N4
zbua3$dL3r@N!~h?t_bN|A&O$g5ON_1);I<xy1VXS*a6b;EFD)+S<j1zLE<s&E@zLS
zgiwRx5K9r3kO3T+PjNxu2F!P77A`IQ?gOA`k%=7>Bh+sh0^|X0Tb$6z;I;F7`?nD0
zFeSylD}+q}w^}pK8~`5t4pW4y^FUL{WJMi-Dt8*FDP#`31OUsQ9fLNEm=rDR(Rj#t
zDmvaQ<3n9xkNMI$Qq)VI{BW!1I6J&KSNQRpLsl1ZL}A3>F)#zSaS_WJZARdP1eRPX
zFdG06OBfYu!7}J$P{o&>>D*RhDLcuO@@2=w0qJ3J>!bl8`)cB*o;ZfXqFCOYPQzRJ
z!QBG$0C5SDQ)uk2(N(K1^^B<$kI}lN%b|}doh#-mY9gq@5a-eukpr*6y6}&?lLi+M
zhlr)xyq1lrO(D-S6h0+7I!_5CyS=H5m!J<vgQ`JY2Wz2^#2(N4vj`D0$DdW+t*6%9
zQudrUg?#i5LP3Ueg@aq1;gWY^dp_B=-sw$Y9|`7T!Mm7Vt;Rc+b@c<V1EYa`^3Y>J
zRgMAs>3EKL2W3^l?MiU~hH$Zf;W*K#o9(I6Ij{u=SYU2}kTBo9rT?<~BJ#5W$T|n|
zgQ1IY$gDNY6mjslp2aBSG&SY=7Sm(DZ6pT4OyQl>8s`dQEd3|HoVQ(W8}~EcNSz$+
zryd>0r;$*jX<B;yhuXLZ<G7p<s7#bhRFgIM)_KgyNFPpS+yZ+!G{s(L-h^7FyZF}l
z7C6#eIyZ+gX9xz)H>w<;22(s%o^qTv&VA~??#5qCWTN4{>4jkFCvS1=VTl)j6`0W~
za+Jk;E!2XE7*3=NQptd!dOD9Qff1VSzdEDrL*@<MjQDNrP%CQ<^G50>VTB2U1z57U
zW_}`;mby835e6=Mx)^ZdM0QP}(x8qcP<bSi_+EixSUdnB7%y^_)J^lsCSX|}8^*B<
z2gHEJ|Kx_R!(NJ@Fu--eGsNT%m+l#JS~0GM5#X!?2pqEQwh(|>F@ENiRCU6lS_(7K
z7=9R5x8-@==86@y#4ZT11zpDPEL<h}{N_+kV{bDBkE$Eh9u@9mxuOWhrc<~oaONVH
zog_5-oI8uhw@(c6Pye#)(+_)b+$@gAbVU#oLxhRbx(wb%k%CrfhMsz=i^GJQ0lLNv
z50iL*$e<rp0uvc$V@RKI^EBJT7$O_oePN-=ZYtQ$sM!>xOHsvKLjCs9FRuX`i|cfK
zO2=xR<+l-x6B(d%30I*r<eE>o!#P$ti*p_NJy=PrWopA$VY{~(b;~0zZkV_qqbIF9
z2S}uCDL4Sk)2K$O@j#;+uroT@y~bc?Yk-yAc(X|_7%ettx?$6}D%l)v3~^O*@S_->
ze&iRO!nL`UJsj(9R0zW@YmKr6;*6w*;cBrFgjf0uJ+?g3ZwqCQrMQcbLpTiJ|BV67
zIBH*+DKLUFj-;TOCsm~z)<H#@>OcUU03CQ1$AXbfxK9<=jJOt*KFFKd$nALkLO7(%
zgKv@$b=Fda-WIVF_Up(-fHo3Uk^14NWC4&6Fp?IHL8*L*HKax2lN*_+g18|~^7x30
z)S+f(aP5zwB<lG@-&k7+m-c)fK#}mAH|ChCY-;2z+%Dz)#0QqRyQH{FO|pD~mZkD8
z^ehAl@|-<NS})C@Z5;eQHQ<yqqkvfIgVMcOL!5)P*J1x4o6LEpj&`no1K;$QIl|0y
z=0UsyFB0NoC!%XqNdp4va1`bW<Up?>3n}Z*B<{Ce?ogqu&5|fY5^!_reZP(N3~J*I
z?h|3bW|xxMZR~`zV>Nol6V~Z5^9OVfJ8zPSg~P=UQeLn{Fl0q_m0~d7&=q>tRvP`l
zAXh-{ppS400H3hMl(ftzOvx_l<!!IHq|#vA3U6HF*m>M^s+GdSp5IFyYkFYmo|Y=C
z1<42}8ax}K1^D;gppoAgXjo03^i1TUoRBxaUUd^5>`XI}#(;kJp&5Y|1ZWs>g;k%v
zHwN+n?~8Oa91aqHqOeu-(;D?c*wta~s<sih41o!NNArvcqbW){UxIyIarICKph_O<
zHJR=TVhruzGTN({DS6D|T?mQ^U-$=n<UG3Ng$eaX6!WH?2yLrcyNqLRX16PMM-b#X
zK4C-z!~yAvg&+zn9rU&uuptehur*vp{hH=UP(4uSJaSBEImM`m8BTAFNE&E~psh&H
zLU8pPw-AWqDUtqh5loxPKqPdfsRC9*-Jt#{rfwD1CGze;C_)AE4Q-pWAEM1fbkKv`
z$NabGiNdi!u((2S`rm#@D2@RuW6EGNn(2gLQAD*3=cknPA+4(`0u?q>kz@tX5Do=C
zQpDq7*Abi0q){anC^IBr0Zm|$Ws|P-tkdWLyY!Q96CXnCRZ)2gy9~kgqJ02?tXFwv
zCIX70L;z(*N#zw}lF{H)Tf>|Yxpk3tN1>3QH;IuE<UFhsArVh0Ed-~lGXsD1mvg)5
zw2BEsjD^GWqEMsak>UY=ilNn=@kYuQDr8P9(Cjp=J3tT}2BRQwDa&}<g(6I1AWLpi
zfWc#?LWta<3ryuJ7HNV#7Ffngo=c~ZEv$_!rHsI|^Z^m2gXt895Q|dbQ5{y)K*0mD
zHVU{3wlZj*?lS30R4fT*(WbPu^jBYscQFfsb#M82YrZ$7qwesQEnCL#PPW<lL@jyC
zyp3je4*tc4sfX$Z*X`Kah%jU<Av)VY8#z%u(`1%)df{w0yiS&rM)>O?D^GK0u$heG
z`vYcTw_AFbInH|Z-Y_nP_XC66sE$vWSv8}Mg~yA`mHVx_s;o-@jn$Kl;(;<M&~Hw4
znZycwYN7#5*XV^EFg9Q$4WRYKn~2j)w#J3=c)BNxXdUAN3@_j91c82I_*4GF_eB24
zrl6kNaV>hOPEed-!dcrBYE7@}t5Es-!jb)D<9EYei8AjEgKc)ixH9<r!_v5IHFm3Q
zjj&7k-TSc+c2B9J$}4$-h=#|55HI82{d6<z?hPu)w?DcwU@OJweL*4U1xG=i>!;t?
zTd>1xt=>V@30um7H8nDb2@eAwJuGeey?x<wU=QHVN{C6YCZtD@B*PYRcc0LeM&|UP
zqbJ7iEJyMP$P^BwXcR8V6EUVfBo&b_VAN!{+lKIkuoHNXd@L6e|Irwq_RU__oj3n_
zyyfJKKVEAcxuz$9IeyK%=g1vjt%2r50;|+Lf)MIp9}NjXnH>sdx8iW#dU&Vi4H(cR
zT=&o7n}YrjEi*9q*<cx2X&tYa;?DTt;^9r*%0to4#=xt`!o?s9<QY`UxYC^=$iz&&
z9FNU>=*HT*;`=u#0+akb_D+x}!Lfj@I>+o%IW%{MpAD46+Yk=)A3n~WJ<AAFheCA7
z&$SxjnoE$4e|zy(Q(Q~;@ci-e1wdKEuY=Z|5=SAJ$0jImj}aaLoF|UI*5RNE<HN-s
zIL$hVAsFjvDRa2!08;4(CH^J>8Dr!p4URmKB-D3UARpkQ8HYd|t{@)F!u$?VN3EGO
zr0QD{fR<+y;z<_S#;$wud=$PP=)x)ZAasR^V;Uq3kOj8xVLE$Mrl`pZRKzV`s2`Nw
zhe6}kA&~xpE766+RN}7#y6J}f!WGCcNGOm6Lj=Ksl63~!oXiXE<lNIW^hYX$>ZQN^
z_s%QxoxA{Yi!3e-a)D5#V~)rGs~tj17>#F9(_IB>v&d^tAq)^W$VVKc!jK_%!HzT>
z1k<Top$RNY-5Ek*$UXW=)Kb_1W+5zRY$lnfm#|NsuJBy?#J+N`0`Hu}ecPYqQ~A_6
zbaHDxMxC2Q(9Nws4<ctGHW6WkKqi7mKpDie8K@L_+XpN5<LW7IkC9icJpcXlwa<;#
zaXQ{TR0KU?jlCXpP%2Orx1&*4-k<?e1fM%jCcab!%b+l@^fMnq$XH;|=vGB&XzYGl
zSYtuj?ooH()v=0Wg-pN~oc|V(qC~0Ji3djSvf>KNDuTshDT;*ZUu@c)VJcLDK}yY3
zX#`=`ZILkObOq&-cUi!7%H9><#s-vEf$CUL*fgy2tZS_!g`py5hWKJe(<R_-4J@fa
z9f<<NxEa#|038H8Gcq!8p(!1lp?VOBRAz+bh#n>2gVC@<3(|zBuqQ!CkJx<9qPO(n
z`;su{=qTiMC_#xNRz}_{BBI3~&Lua%2HBu5G)xZh1tdGL1vE#4ILo@lLX5D%5NCWd
zOJ?U_O`@6>=u3M_mTQKKTDKc;lbLrgwAQ6wvE|_T(udxZl(EdmYYX9GgBgBR)#wN;
zjY>k_vzO0B;fArQ^RS7SmJ7n@9?(peM!~VXw#lDph%+YR8LGD13I=l;3-2AE%GiG(
zS(sbw5;72Fk4+Eutr}*xiy3;bCc8OcNZ8bh-Rhq63;#IDMgf~!p_y`8ud9krK(y3$
z=}J#wr>&tu#WV%R!ZQU(BP=|$do8!T$u8=5HzB~GMJorJWyo8NOFfQYT_IwP1%la&
z6-`{xcGd#V=S3y<9uk1EUY8ay1x|h^SGxbF?^55`wKI(u+P*6dAG+#w4>V5SQhRyu
zI^u=)Y=7sJ+1q(r_4ZQffnWQ=;_ZIvfuFjI!@9XgHs7VvKpT$V*mbHOF0_4DKYr+}
zl^prT770Fj+uT#sGP+#LN6uPHM#|@^E0CX631RwS_~>)j@^`ca#t=gg6~aIHMM9A&
zB8f0Pxx$N-$+Vm(Nv=pJr6gf6wsGGo7+YE5so)i-UzlA!<0IdAL2fiL#o>z}wZ-nx
z0N1IZ2bSrv^Q8=%v>Hp5#R)T0gH-Gbagl(Bn3t0{O(Vdgn7szzLdbPBz7igMPtj!!
zB7_ebMQ*~@q*#inbzN~43;XkVnBESHjZE}M6A!2+At2&2v1y6bYiYGZ!%S>h3J6qD
z1YWa=3u7_VdB36Q(k#X;9tq_5ln1BrXCq0{nns)fD_}E$Jdf-UR^n89%o>x9NK;|_
zV#y|cV_f=5B{WE5YzmLMD8<x<);MKSKdPR-rh~T-R9xHfjFnl<12VD<UV;lJ4zS@*
z9m-frZzTMLSgM@wMA+}UiaA(H?-)!)#}X7ADvX{fv^6jb)?YfX0<OUdiw6Rn1Hyy@
z*1u6rH*<>|>=*w$pXBI3dV|t(w4g=uDC92Z3nerro;|5TzvL*T*aDVJIz?VetlV*y
z_P#dlrQ}03zDJI_+eP2g)DH1<0Z2{BC9XX&IJoi%1%wHMXpga{_g>uxQ=chTU7n(s
z)J7u)O~Z-Mf8Xa`knrLG6QoQ3!&Vi10QkYji;Z|(qAM5)Q9Eo=0Et1nDTFcXXjx&n
zahh((8&et%S!hwxG@EJV;2`V0yk!9K5*m`Wt<}~4j<6sY1~E@aX-8M)NEiE=%fpf0
zq)%xNR+PN{!1LjU%y7XN0ZqJg7-EVDDkNhgXbRB{@+6&<)OO(yebE#!{F8I5#o@vC
zWD2pz&ordF>Arj+_|A8KS{i{P^0au>8+nI>uF18<J(HP&K+C*wgh>pKjCCsceQ{#4
zkO4JNW#x<lQqWm?@3dU5PFnFs<TI}DIs2K(i-cY1*ggv!Lz*!Io$Ot1nOrij(tvE|
z@xOE?qJAMoU-2tHGJn?eLI>gT@~b`^&*1OKW>lrR$XWXCheWHfNi0EL`EJCz!3vZ}
z_%HyU$w~_b$*@XE647F*E@QC4^FSioY$KrcLFX!fehp7KyHT(pow7a@@^AQpENX-n
zvoiOUXsR2R)vMIluaC+_ews*CKN%k0NGw{~YMRwwQsv2|e|R^gm8fXq^+9x`3D*7;
z7F35Rm}+bCpj~cdl~kzSh?FLtw1gb@>1ItuTU#o{9*6Fx%76XcJjwfVYloYj8kYAq
zL-x)q?xm3%i7`=e3tq=_e4Ix$5LSDR12V`Ckd=)MiDK4lykS^L6pBBh8djFmyxCXQ
zKHx5Gk6X+D-bW00$yC;9;R}A?$Nmefx16_XNsc`tAwS721iSIrlG1^|R$P1tI%rQc
z47*%f7B%+zi68`-Hzh&@*{$aiT8YI5QFgJzoI;iDMNq?hV!=^U(~tHS0+#kG{%I`>
zFbig6Vl|BiPPgi`yAQXL9j%0LEXT)Yzy={W+1wmX8}MN<!Pu<2Q8mXbaPN&Yt-TRf
z_XuMiQ3na=l`dI~Q$jN7Sk;x)nSH1VTU8FX=$emx__iz80A)INVD*?}oOdtQ5t~Zz
zr-{OFIPd$@h1%VrJz<pu8YCcz@QxSm2nYA;o5RvU+97gaR8?K%&cSSD=O!R@S+nor
zhoE@j9D9YHKgVX7gjlvQ|Mmx9d!tibe-z-Imq+qiVmMf=_XQ{3x|W?ihc|K<1RG6v
z6&pf~Q5$$EoJM+N0_Y);qLwX9V~O#y4~`zalRyBKIuqdeKIWd!{$d;%LPUtTlm60e
zwn3&P6coN=T*!OSqwdvzFQbgeVu?sGDnW8nz@1u0T-ohSGt*(i{wBb4gst5wPC%$k
zg%AeK<iq^tIRJA<i(QP6mOQb3*n+|;X0O0^ZtnC|ZXrj-u{0KML|7cB-9>(Q9P^hM
zA?;7nL-^^+FA38y{iP7MW%S!j0Jbp5t+>18JqBz*Z|SR#fYH<lOy^C@VK#`Fi(RCN
zxSH1Ou{w--yBU+TH)$+kiJL<!JWtKzNiz$hG$H<MX=w1?yk99E2oXSh1uQCk6dR7M
z@)-iL^YBlomB?Q#KKiD`-uvh$oLh3LFuto>07KzE4Xb!`tN|ne(P2yu1S=&wDNK?y
zCBQ4}N`$gag0n;~C(Q!0NBJ7486Uk6Yz_>sa}x6^6O0W?);{BF9`qK9OP@N{x?2px
zygaHS4cm}q<i|>_;bLyLtB9{H5G2XIsGs2VwQ-ncWs4rL8aYuL*eS)AVq(K|p09_r
z1do9#5NF_R!TXUNuxcaY5zY~pIr8GflVJf>%yoi>*XcVqrF5JC*j@UL&{)dr5FR_?
z99Y>#Qw$hRV7gVE>d6rW_@&^9NHHccr3I*xRw29az~465swkAgt+x=`taHP`M2+qi
zv}V)Yv6m`#*tUxnV!ML|3ry7t;$+*1gyZy%7YCeCm1mB08BNb&Be8+A0AZS5_APPr
z9>T;lLpFGpH|s}u@!T(*{{Pky>sH|P7lQBc=X1_9dePaSa)n)EyCQV1{M7;p!XgAo
z_D#`mGx$buriYecR8X@T)82N-#C@F=2H4{gfnm}2qiSGZ(6LGnv{l})MFdB^D?Y!L
zEeKErElU=OuCcKzoM)5@L6h1?*rt;=2<Zh9%Dm*hwF~loEvge1P(~82Fb(2hEMKMv
z)`6wbdn@4@aaVbPNSC+PKz@2oGNf`&S6@ocSr`V8GtC2b#1)BisNOP?8=3ObiPC#g
z>Gx$4^sAMnk<<e|;9%R4OOGLX=g(ZCkk(w}s2wyo435~US`=()konmz4o#_Mq{7Ak
zN+%4MU2T`G6N`#LC$OiAiq(BVVs#6Nc^H*fWlV>!89*Pe8PHm*!C=bL-=9`(w{q&!
zU#NsPe0-i;5B0kGn>oNV+p_gWb8BPxforGK?8#ll!Djfr$P^#AtXnpwXGW$J{}Tch
z4D1bnL_)Tph)fPkjbq`+lqs=2<CA@jVOwXsadX%!6U{s~)jc|;!V|<h93NwI=W7jB
zE^iLabzzs8q);04ugKPoohu#>daPG-eA~<Fl6MsSS>cuKKt5A8N;JaUSa8Mc=+;<I
zX-jN&Ik?tSyivn;B|*_l{kIe6`l{%}$EPCWgd3&~m*#c`U^#x5_i%{p*&M2F{aE?l
z{bgI)EbC6vI39*=dc>Cp=nR2kjoa8-I!dJSNz1m<P9&(OHQ^Nm7L-C>de?|OW(-Rk
z659x;yPc~7eGT85=+$|XbT_Qn9O`@3RRNQ<XCM8A=Qk%l&bqU_54F4>B@0n9@lG{3
zWzvnP%k}|2uV1mjB=4BZCKClZ!F;j5-^2#fx^fq45#l}UDx^`&>)1r<?=DHv^vts;
z@Gdf)HX|EbfLZB3gqUqDBBodDRT04Vl2Zp?>+B%(^hjO8oR5vMS28t3*mCEs+p}$`
z8-6z$JavGVp4f-#x)n3FiyesT*r@5?sSmnr6$R@y8#UPV@390e^OAV)Q1J~fv(4(s
zrb|dfeZar2ETx;3{o($hb!>;ciNM;EM|NuO)k*?fl|S;bW7faMIJ?<F94NgvAm*00
z#C`uO@%G~2R$ZBjwoK?(vz?M3JT(WJ&92L_jc~5VMpRhzzIfy(;vK|VPRrIwYkHUs
z9upBe+yF_xgDt4}!w5f{G;y>y+$~ID&6{~_V+1f>b|(m4=4JfBu?E`{b&mjNh&J^B
zc1{iz36JF+ZlaahY+-|7rZS}*33c7b_8>UFkjnOkuPTvjiR}+Hn?=%~O6!uSUcD6m
z60h|FxW~Lv{g&<6_MMQB=6ciXz+tfSp@<jU2XlTHMQksjB-o)~d&nq>()BHD6iQ}Q
zp3dva$)3xui)NQaVM)pcRj)!bR<<tMn3fQ`H)Kh*nq6@VlZmlld(4-xV@Ecv<eLM|
zpecGc&G01v+zi%iR!3OpNJMjIB98dNN^Wo}x`P;l2*^`*EHv@9a8Gul-e1(t`w1RK
z0}>6pr^_8%PnR*)NsGE+Q;xPE;slm2nwOQQPas=OkSBx)i<~zU3BGGQ?-eI=ty*g)
zX1A_B;M93By}^#*BC*J9t;xurJg)qq!$riEU|Jfh6bUlNQe($RcGdP0-R%vc-O6S9
zCHr;9(`}vfHFQ{_`<W8SEPJK<0$wyD;QJW+G7>z@7SgP2o^e}LB$UF`B3o<Z$^Cb(
z#T%P(?4l<T=sC7Cd3(xf{XBx>I(yg*a~;$Q$Y~m<EW30pi%1Z=Y`p!?DuF0CC*~x?
z{FrczC7ee>p7aUlhFt~becG1t3Ehs#;kErpo}?h*<Fa$5m)`pOY=jx@$hQ<?;R0KN
z*maFq@y$Ycdtao3#(g1Hf{|JE`}~<3J6?eVHaxLz;7-#evMqf--eZGBHcP`<ml86(
z$PiKKZ33`cGYR{G4q1#EqlGxJ@0S<a9dv<y@bD!Mv${KTV@=1|VR)0=VZTK_;?T@b
z3gU;o!mcO(vzvl!C2R*7#`_qK52z;W0!b&jIjFLdfmmQq`g`Y?J`DJjQHP2nyr}Q0
z!N{%Ou?dzj!FY)scZmviGfOmY(8HEL*oIb3CN{9!M$klIeEiZJAqq+3Ys8Cu6R5Nq
z4($w^;jSsuC6Ge3cb0i0ll`IHE-F=Du8Haotn5Nbz%={NrG_VOkP~uX?uJ`1q<gvS
zYPI)=$Jr#Z6;`H66FRdIVJk+}4@W+HRu9x-c7UB(D%uxz@jyJw+iH*e{+e5wIopb9
zN;xgRN@T(im<@i!r1><xA9Cz)jv*sJ8qJ+XG>7sQy!4VV=mGY;uq_sFVO`>#Unx<B
z`y{ejn4FXcgpEXQW7!yXygGO*vgO9I%ZsE$Gqv61)I0v>zj3hhW$%2#cGc&q4?X$I
z@}p09S^mh!*)qG(H}3!N0$$ty;q9t#|K-nCu&f;nE3ukL7@qt}^fIE(YgeM_WXvsP
z`nk&|WXNP-Mo=Vjan+c%{r}06L><AcuS=`%XY_w7%ePnNtvpXFUYYUO`O^L`ofyJr
zM-wd8v_3XipV&~iVVCS7joV@G@Lqqe>&I#;-WL!zccbiH5uAsgVna4ruOn8PcWXfw
z{1KdB0#2KFLa4+xv1ud4>ZY(a8Y#<W?F^U+VMbOFHf$uGx`P^D07k(d2zlYl;*+*r
z-z2d+vMKiWU;R&OP*2!kEvtANT-kU&$#JGgj@`fxaPe+luEK~$?_v6aD=81>YhM-8
z18-ysEQ7rfp|*>m8`=&KhvIGgycuB#+TzXP%BYH4V*dISzy*zC#7W*cVT-o-hqpZs
zV;h$#hap|hX}o#%6xK$=H=0Y`R&9!RJ`aR`VqE~GeS|)X?*=5J@tUJ(O7X1b4#9_v
zs9RA7(CBD9M|X)h;X`HBB5w)eDlsy+$>Kv-)U+}itInev)<m(s*~k3~)~(?)IJnEl
zQ5|;2jp}mT+A9Nep@*UGba_q1TM$o|ieLd)goeR%rJ#9V4%ZkFG+_^)7T1#b3}C^F
z_69M6IcgTTNr>j1aU#PH3Zzw-`CzquWq8vq`PnJuM}##FxwuZs>Q|1TMSyk;-Qf5t
zg_c2kDbFYo=9`0X!uD86Umr{w%<XGTC&pdscsK(DcG{EH?S+U!K<F+H7OF<ke+l@b
z&N(C`M5T4x=^LI50cg?(gGmJh_4U{0Ke0b}yZRug-Nw?xrl7Y~c{8!qC^g2d`P;Fo
zFEOF{qp&=#xI~OL2Sy{8Vdm9I@m}!NRA|gKW{(07+7$SF*~ux0yN{Yy19Q=ov3?JT
zkM+;YPIciE!3n!r(on!7CUPrS7|l(g1-dXwz6Dik90=6xE_cYZ{nK|8on~=s4X>i6
zjUtBaeu5Ju{K$@s#YEcsxA`pQwuG$eBv|iiaaA|Nb*6do^<jyK*eXB)(AumT(9Qkj
zo{!%?Q*7jWme5-tzu;(*L6nzk>)}DFHB&0}zjc$|-aCd**4v{>2Ls>YbMD5)Edb_K
zEo;Nl>Ayh4-yX@xIeQe)idS)sKtaeM%o4A1))gcbdE!416mT*8Nr||nB-62QOd=-u
zpLwG3&^=S|i~|bDb~fI;DG+FlQ|*PDO(i$^w~mS&6C*A22%Muf`WB~t(nL(ZjU`Hf
z9cpJ^U^OqEb3~eCJDl-O!VPE+f}eqz=?2Ray~D*N5RwncSkq=nVyX7(>~c!*KXLGo
z4#o10#cm>*fBF`LDhFJ|jBUFNA62ms8Z!FYK|s5Ti*pYi=!X>sn!*90oCy$>U{Vu}
zjQ|aOOat_kc?km?9<U-uRkQ_NLZ2+ej`{lL7e;6}*m$DW4Z2e*nv5i5H->}_=rMJF
zO(Mb-E%FePUTeM-mlxIG^5rZHaV6hx0C2*93&CZ8kui7&kTd0|P+Zzc2vmvapBY5d
zu-T86D0xWjCA?sj|I8=z8>VgqvrTj@sIfe6fC$u2l+^SGdH(|}zHlWG2DA<60LyIK
z7!(eD<uwd?oo_Ypl3XyZfR;CaU>k^Kt#T7IH2S2#mM>sSlNjHWQ~9>ftHW2u_2PGa
z_HsC{%mSD;*n;6}6IU^r7T{Xp+B_c%WQN1Kwp&7uWZxYF2P3tDOvw&vs2K+g58h_Z
z(|^PfTW(_+KGAtyDO$C`Wf=Gn8|7J8D(+CFmcQapUsQ4VmH^{2d>QpjMyMG*Z8hj-
z;#Z3~o!npnRK2bRrRSTD%~<7+%4ay7QK}5!B&=`<bfBTO+vQU!O!$q==K@wd9SN(f
zyGXr)bZsy;LH!9wa)zqcZvw9rEY$#7`Z);ZYg}$b_@5UQhFsJQUFb2nh#`1==zv$v
zx_pn2PAmilGZZw80fO%qtXw)v`?CnU09$};lL#sGIZo9ck~htpxi9`}(5c+UU<2lH
zsg`fm%&Q`-Ss$Hb+!)2{#B;7f%*vjDWWJF~3#<p!EpI&tqh(28nLr1F7FyqD-a#X6
zCq0yp(I)IB8#V=_E)11;5AIe@{pv104Ct3~yem`lV5RgreK4kstZ2@?M2xU%$?(HI
z>5H_goh}$JwYJfs3^Yq9(fdAwtSlO6Z-9&#hT1NK@}X1Q#?jo6wkG+`Pk!r8Yuphx
z=KGr6WJpzc!*`nH1H>%vyvlUh1pwD)pj1~}&TwSRDq|AVQ0Otui(wfOMJ6x`Q1mEC
zL1gI?f|=rm@Ox5_<COCnU8kXU$SHsMpRUU#!PdK@#6z#eZX_yTEu-MG{S~JoFU|~;
z6}82V(PWoFV@3iI4`^PfU=8z;dH`dmi$cTYm5=1Jr^NP9%C`{-W%r;A$$(p|vB~K_
z`o)b0M!Thvouyv`R#R%nVEJ|HM$J^zy2Xxw_e_}$UA}XJc`|%sRL`l=o&HY+^5PF4
zqOBhbG|Njb*c;T}8yqYfFfw3o1f8Jldv{`h5P5ylMqo~0O!_uVvr!bsQ9`u4vdoOQ
z3#=xSj8mCaCS)ZP>}3x)<Bg^}8exsx2!hoZu)D$1S>cRtcZ1Czibftn#qGVS+T0p^
z=^t+PUl&BpvGtt~mWRh<{qVQcdwBo5R@$}GUwd?CaICbr)kbk?yE%M$IeO*TQ1fK1
zI6kkDx0YqaZL%c?;NCUn=q5T+nq%i?3KNNMK=Ofrh;Mq02_nU!7alFn?Jw`87b7Pd
zQ|8_xDzyAHt7i6N!0<w|eA=TI@|luu52FvD2SI7**O!kI|J@5<mfr=CCKlfAsTJ;u
z_h03|rd+-E?#*v)KBy)>-sZ)8;IzHv9XW8Z9XNADcmu}}TW#+sNnGt^pc>reHU1sB
zb$pJi7|W*@C5l+Uw8s#$KCXs;X{3A?Keq_da<<|t9<mh2*(?uWW8sTYy8qpQwEf4b
zrqtun<JHS3T73<TABe8_KYn6xECxy|udBa~7|<ib{+DOQKK-hpD~cy)-ZVFSmwzhk
zBWQ1~eskS?@%l^0j$Cd*KI;CJA+P=0=vKqG1W|>Di(h$Ht#m5fO!zU-(jcF4ly3zr
z5)k}`m+@_ZlX`6C&XBO>jYRu<piF{%@HGN?L_ng!E#Y0h9mC0f!^=#Q4`_e|r~!X(
zxiSW#)Gq#Sgo^VWf)rC3yr*}k|CJdReB})<BlvspBrw8dpWFP~#rmg)0P>pk`Bz^5
z^0n716%6eRwrv3^dCPP(ICeY=_n1!8K4cU@u<<vy=>`7|jL6|N;WbM9V5a~YH8_Uf
zL7X#IN<D^gdGvZ^Q_%4SK_1$h0`Lt0xIHNM!{8tNPYm?KnnnHj0?&N5%xW(X3++IE
zJqEb}kCTY(ZGar6GG*%XLqBziy6pC$deeUU<$sWDodzRXw}Vf?MBssoH^i5o<TH6Y
zyxFli9Q`9ZZrB2r>G-!kR9xd<Kjkj-9Skm9)M@pw{h@x8G93_<h<I?|518P|j%N#O
zO`^JeBJ25w_8*(894^Ybjgxq&_$9$kQG{bn`Cx)dqlJ&dU_eNK#1xwA<S)DZC8O?x
zyWe!I{q51;<IVeP8qv)`Dc5P_h%N37f6ym%8#<;;Px<j-up2C!ZMF8!K<C(A0e}M*
zX@a`+K%}-|s|g#?@+{SgZB_Z~z)m8i#id=8V0lxw1UrkphBRO(Vs~MJb^Gk39k(OH
z1@Zo&p}|*<>C0{}^3B0-|Ms`r<X!X7lzioL)*Zf*F&W<?5&iUpk2luihoZ3~@)kki
zc95K?^M|~Y0NMkLb6n!$Q=m<Onl>@97?ogA&@>r+0lOZAtA~mSa{Yd60p1GarXft4
zk#{SA%K)H!(jkbW<*51|@TdTru#kQCHZnSojOO^g`kibb0Yf{jzmbI-m0IVGF}eiO
zHeZZE7zv;DwX=?mS!tO?(DzLR$0vp@U{NAQUPXix7*5_@;4@&n9voo@LDk6_-Z+q-
z&^a-a5~iJWd<6CalNQx<Ed96xUT-S5p|kNnw%rQrqQfd(ulYlQGvfRJ4?esj7WwOx
zbN&c@w5m0O@cD}pKQA&a)GnsPgoe0%U5P~I2zd|LqF_-3oMQb<smvpHe4~Kxxngr0
zYz|0i$+VzHFo_ogHr2hQYSpQ3`-vWl9=IqW;{Ikj)oB1gEsksFIKdub{p=poh#p9&
z6IAyYq(i<zz=vIDz@YN&DLhQpTzR=5F+;8*9D@jQFlYhu2=$lM9buE`_h9f615@tb
zg2<s4_#$KlAp-MtmS+E$-IjJS$j#yYB#mva+l*;Mj5xc$;fC&9dsC>R@EVwSwCK%k
zDuc>&^x=q5+-_*z5fd)p&+VUSvj^*grQRGKEIYHC@ETYrg2B5XqQs{yEs|E`Ljk;h
zj5C*Kz0$ml%<R_VgFbd~@j#7lI_24A04b^Gv21to{h{)oP96iJ+dURz7v_Ba>V@B0
z&tsQb1&Y6Li=(F;%i=^If%wudRoeasDIIXQr0nt00k-cXn1P5b;JP&CT!PENNxNO5
z%0(&i&Xq*1gY403567(}IH`A;8mO*s1ifhQ|M|l(-XB~5?De!my<ZbNgV^;f>U=qL
z{VB1){?|8;+@;d5Z=MwklsI_8==o0NWe=&-AE;g1kD}-L)`RXYtZRfBOV^6v3Np}+
z*ih^rfar`n%Rj{3mk%zbH_^;orCE=aburm_UVKoJt+;7*oZ&T-k(_$ZU(1cBpUjF!
zm;UGf)W)HAq7H913`~XfTs%_T94ai*5#wU4CRYa0$WDJVA4kIpRAy4~_KCa$h}Ab6
z$&ACSO|UxmC<DQ4nYyJJc|nf%uGw+*OS%f2S1p1$jIiI&_wfU;oTh7b6S-lDt-!6R
zx*KUy!expd`E~po0@JC$p>8J;f19WsnaOHjFw1@`-X5_a_<wDpieP4Hb8BJusNqc>
zMxoT;6~q~rd!{siQ%<YQ&I1y=#1aG43VsA$0hbBPnf+iummG5iAK0WHPGKvX(uFmA
zG#rSFunBC@nEcp}<fDeV>+t18@WiT1hpiBgvF<rN8GE2k5FZZ-@FfI+ImEsl4O#iV
z<~2q_$wfS*FBP{+2AjxBxBk52RI0mXa))*~L+Qv=a@7?hbmplzYX$reMcbU<%}i=)
z2&|`Sg;;wvRq^;MQ(mK}0?NH@G@on^itF#+<?SmD#aoWqq<dw}zdkg%6T7amo&D8I
zpSNJmlCPR;lYH?t_6lR&mqoSh_F&RoUsE4=Y1QaUubK-eXO4&YD~i2&U{VTR-f+@#
z&3v%omGLQCtg=0Dv|&EDm9OzGS6D4RRD0muEwe+iIlR-C8lBhJSF71mrRsx4wfUvR
zTY8N{{{LECfA_98h6nk^`<42^5cvE48kFp-`LlO_%HLPpYt6di+y|qjsI#u&Z+yx6
z+Bd9uneGmacpoTM3-{km|GL#nV|C2#b}v`WeCbFu<iFy}d?M_CzkYlC(qsD{47N{i
z)Ypf*cG;7=t~!tvm&!Z){dLtV7p#5RwEt><{V%K9%nP<WG(8l&$C_Mtd1K^XhqE87
z`3tx{`)k`~hNes~)I35T{?#34j@i?{Ca9b5dgQ?A@;dHW)g@X37^GeNU|{`uJ{QZP
zqaEfYo|)hgD4$vRc0-J#PgH{oQtJbg0J9sT@TxY0^v<zz6Vbth5dlQO5MOblve;-A
z#ER90lI&9v<&Hhzbh+>U+&>cd<Ft0gthUnvoFINvW<Cv9QL%hG1D{{!pdr?esjCr9
z;0W+OmK0PUYb3tyZh0$P6dLQ5%v9(O=U5EEmPOC;^;Tvr(K8iyV`%a8ZvDd-cXB3@
zPhsR+aYxJd<Fo|7>8ahtFV_HtQ5&qM-Etd!6c)JJZGdP?$IwkKU)-2h$yNBXO(LCu
z!-%P*V<n<4@KKroT)fo+;!!cgWdsMsP=SA4yi7jgW_!GA12SkMV^G@irps=3(ik?@
z?i$rO?bu{(tocJFcG4(bO7Gkc#}l9iJ>>2KK;iqU17PMT8k7s488LvPdz2$z-i!C6
z&zi*<n9|^Ldm;bx4O6}m(Kr~OO@bMs8Zha2C!Y83^M+3;7-NV^0w#ujfmaO+wy)VU
zoK=7GH5khRfohUKKS#%aFp<ShLOaN-cMOaa5Je%J6Uc=RN95C^ELhy0CVWt|E(I7w
zkyTlKcmii<4j1~7k8GjCqPPwd$fWb?u;y-r?nLjP{q%qal_G#@5}jmr^9H5>q#!UB
z36q))pJ5`pMxd7hXmvP4e4B$1P#QT1^CPM(kz*3IN?aV_e0<3K*MtmWygVQo#o9OG
zk^y3Qi)+a<O;;%%X}boTMIv<xH^A!*dScG-AJ~;17=i6bI$|bhw6IQEp=ra=&>x1M
zJ}=$+8EQ;&gy;caLZnTC2A^HzDS(=TtUslo+~d10$}_D7gIH&DY=QR_nQGL6tfSf$
z-^m0@At+S>d4U86HiB_!op@{nQMNE(3v({Jr2t;Nbav3Flbk;IiNX-yPw|PAj-BDH
zv2}Jd__m|=FcaMk>;xt9#GGrDMI7;!K-5ZAK@ss2Qn>mWIw=SugPdpChGle_J#}W1
zwmdruX@u2D^dI6xo1QM@Zw^M^bLpC74J@WFe3l}|nHu)gJTfrsh0}tK^Ci;FjFj@b
zjIL&E@<t;=ycpCj@+nDn4`vjbF|%$@VtZ*y`yg64FHAlbNW%+7s4b0SmuSu0h|v?u
zS87sS@i7<f@}Z1jj{!^?YZ;YKxN*GTPeyt=<XfH{xPv|ju+JHYurz1f-DvRtpS8Dv
zj^n!SJgb@oxuwu{SE0I9gj-@)u|PE;$|7jWftmQYUbC8PP@vrnHY7-<B!C8G+HoRL
zkzysYbKI{{EdUmHM9^SN$6o|PI<nWANM0$&J3Bi;OF#@JbVNGRSe{8Hl8$}G*-2uE
zaVGMPC$qoXpe##qGMU|lD13BRSG{-Need1-fB$<g{uHNMqMe#LAt(aJcMQL*KBBZS
zurjw|dY~mlEg`Nl0z>I<+;b%ZYxTmh<Fvcfn`&8D6qyuPXynx^*+xiSBipKj4#bn9
zZ#2y%Tc`mxJA{0Bkw+)|jS!D{q)!lG%0~)w#H8_fU__o){Vn*O&J{*=Z}p6va&)dw
z93n@B(7r`XKAstC;ADY!Wp3h1&~hf`T2&m*`r&FL(1xJ84294R;Q0YOBDXw8brE^a
zDqfN7GBImaa!>oMek8K&q&JZ!Rf}Uj2d4DaOEoa2h*aV+O!y)Gmxjwqz>s7@9--(e
z7=9-Ltj%R|v>;!A*wEPw&F5g>9%djoCHce+Z)+MMpf{lcGVSF;R=F{*+GR#fIS?Rq
zlpI$qy4Z$nG*N;Pl$(%Nu_j<1v0KUA6WL%`Lprfyv2xI4lnjeWch(KSc)5FIxxe3B
z7oxvPMNZxoRrL)tH8UK1RhxeA+x(B%Dezq6#7!qjN5T3aTV??P#|9J0U=QKID1ENq
zmA0_R;9iHk%(g(3w55gPo5-_ZcAMO#!CZ@1zy76rA9CV)SRUTmDwRt0k5(UAIyCxG
zh!o9uNtZ`YmtQ!1#2qeP2<GySxz1mx`P|^eW^He>1g|eYsp=K7#Z4&=t40&=8MY=x
zPS$7GZ#bS|3o^kjXZ^N|BITCyZH_@HCgTY{>y`&#3vmWcff=@hdZoSSE_%<Xk7?P^
zTq5kat38l^rcH`h*uDoUORQ};@=oiyM3VXG+<ZR&#9#f~xb9v5Qhe4O-8&9}k;+i8
zby(F#A5zz;@^5&h;+*^C+RNn!o#z7cIt8z+;<f5zjUrOFd>8{CR2YwTKA*YYb9XSs
zKj)q!O>PVvo9Bo;S#;Y;yL{4J%sVl5&<c{@#_qOsj;<;~42D9xo&XY~t5P^8Q<rVs
zYpZAM2~?Q4PXK%PqP+gT=ggmGF5(N|)^-ZzT&6C*;(2GUB8kR38v?UR0@e=7nt+Lc
z#0ne=EOnWYC`c=a45?LT#$RJEwt!^UVA9SfUcb15u&yQDSWE2Mxo?NRc$vre26S~%
z5=O}5ci7K9`EwKH9LW>zynB=V!e7?l*)4anwYJjHeM2N)tv~v`J0*cdPwNj8>Tdk8
zKY1}$*S@TUf3}<#@)$hE+(JLtlYb<RpLG6Ka!`^_!<2Ly9>|hpUM&C=#s(17wchjp
zOBjROt`uHc=#L+l%a^Uk=R4UqB;5nmJV1mJt`?N8-?M>V7hoiUh3-j?m4x8+#Jt=a
z&~Uw^byewyCBMY)|H0c}GPWwCn@OZ`yTGaS&?nNpx?;3$-%Z^c!MCQ`%UAWh;^q!r
z@rdpx4eK<h4p}z5gpq-%r7R&F0;ZBYfULM_&_mTpLJ_lHIC|MS)xnB|c?qHpWCM!B
zD1-UPu@OKYC`Fl_c{KJ&)*;}ZKt_f`-IVAR*M-m>ul|=GN5i1At<jQC3JJu$6w*7A
zCQOqM;d}Mn9)p3*bPe*TR?dCitNA=DQyD;r`Z&6F9&^KztfDS|OcziDfk=%hGNBlq
zqABnhJJn01j*eLlh2$lmu5OT}6-24SUBnD1<Jaj1w*Vn#%_)ck=r7|1tFQ+)sdeMu
zzy01O67{aoOJ$4dJe+(;JCSF}_i~PtI+|}?MgLk4=Ib4fok%Z}U=son0%w65^Fjh%
zdf+@yA-@Bd7daV5hmZ;YnV@rIAVFJz+{w030f02|axL9Lu}F6tlE0+P>8t|UeB3h&
zoHnc%i1QREan~ceuL`L_RPN*@r8SkkPN{M`H(eg3F&+cEQ2S&-qp_%M2@06dZW(V5
z97qpg2-q1nnBxs?(n85xqG;B&7+=7Iz?+hi7m!{Of(T?y(oDwXs7wBndi=P@BtV8d
z1+L*3zgQXRg({c{880xw;<B~Pi(h=Et9m!A5@}gLV2aPyCfP}J1b6k5{+McA6**Vn
zZ_u_CWGuTHn>Sc&!%Toc5e+A~Y;EWy>_f<-VD)BMCi4N-G+7|Z2UaNKVzFzp^s*6L
zz{WdelV8}TabzbEfm@iRFD|_;EL&2YNR<&5O+rir?LYcGc)3mr;Qs7YJ$U>aK9H&e
zeIqq6gSO0aXcjPH(7#stUPy{cP-elw0seSOCnX1)VvMN3KsgE!9n;1>7l1b{+Rt<W
zgO(!)fmE?aVuXb)aPPsc#K$V|mO{$z%mpL_Ch~&kmW=QQ-su&VqjMQLZ2|7#v*FZ=
zELtnGNQcC)unK@qy~M7>3;iPWNk!(=wZ^Q>8rSAqoQU9_N%9$-7g4aX{u^1LnB()i
zQL0n+Vp5=CO!-qbV*0zc$1h><_|O_1CtaQ_Rq6)~$<;Bs7oc&P$?P@Tj`nfTpsnVi
zHMU8}p$hnHH^?#pdX(m%5g?^)JY%9@4TYn&393<gOM-3}+Bkd22lp#y(R&?flG>An
z15-N#W~nhmjNFj*uU;5i39-b`+lazO;67C0v8qACyx}2knIdpcj_wtp=s~R&%ta=i
zYb|0zV;KO63M`5~mbpErxUKo!n9ss&G!!4_X`T03wAK(;h>v*Aye+Iq^1!B7XO9SC
z`q{PmJ~w~1Q{U(Jo?K%aKKkU~KVIMGuGz1JZ{RF$jQ_Dr9UJk2e@2<0hb7;~50{I5
zZ@A4*>IBi2SO14~f@sC%R2>h$A#KQ0Z%P~To4ej22|s@Hn`^m8e)Q>&eso+PJ#p8U
z*K&_M-+^AA;)j5yXL~!K>G18BLDRG0T@zLldm64>=O42dryGQTB^6v;%r<^TmiVa5
zYaf6KS6u!QQy;u^{IWkMALOgR+x*9&?)2JwunSlc#dI}S>xb7a`v2p*6#c>DjuT(M
zgcaj@rS(-T;t<zp#c9-<&}=3+b;j+fOB9d5>Tvp80TDDjV95@o@EzeM5bD{oG;B2-
z4BgJ3Qz09`06-;kmm_L!O>R)=0E&F34P~h*C7uEqQM)kE;eK7rUkNP9a#~KI`|?#L
z*F`HOu7d}-%0+@t;(WpBiyQb~5x!)@%n`$evI{f{tj5wwzSheF0i}U<A@wB2;s(Ni
z?rRE8Vw9nwFsUB@_a=6KI`Nb7Bzk`xf}ODd{zO(#Ac3oV;;{zhfQi--IfU_Eu)|t{
z&7V;4fCdUR4Y-vD9CKlIImtOY!78Vjup|n~iZv-EXc+J_7eiHXaDYI2vHdI77yrQI
zgY*Z{gCO9JipdU1&o{OKTrEK_CD_vi{RMC?m~?496aX~~@H7oyWJjLY6x9(XfK}j0
zNNUw3a0&!NLvj|^iIa!-)zEga&Gw5w4eYo_gJ$f~8j_;(_aCZOGHwZ1KPDoJ?kL$J
zR2+zd2=_AtvSyqSBj~xx{bC-M6pxo)02?R*XeD?EsxA_t`3jLhccP6F)2W3ggMUT{
zW^A0pFDsHr5MN1Rd42oUsrk%MY$@n1B<_$jlA~*WoLb^8F+EDWN$hoQ%ZjR?G@LV&
z#XQN3NUO&{O8JBdN%2HBVPDk~xP}14^qB$*1|Cqs^jh<7LGU|L=4lC+W$AN46B)1!
z(MD6s@d&Vuok`!f)AvljC316KX?QEHSLKR0n$U3)gO+o=G-;=1mD-HphuU864tJKd
zRzubx3fw!EhwE-7dXjU78HFp8455)q1N`BG9d*z7)D}sTl@taL$P{UkTCC0!NRW@j
z7I+X*Aq0NnjZT`ATB<$ZhA_{|u&{32@K%XFUs8;WFx_I*1LX&hKm{hWiW8Y6IH0T`
z>>>t84Zpzz;y<WQycJ8ZH?Q!kT<hSa@mbb)`IFxa4is+O$J@OYPbgQ`m)BBwWv((7
z7+}ARd%zkMH%NO3Mu7UKap5Z95NI0*ibE#%rhoLt+=f%v02>vY4#|)y%mA9iV*z#H
zHJPuhfJ|Y|QHeH><3HbN8RH4su6R5h1*)<N=x9W{;PZ32bXS~S6o~F5()P8yn7p}5
z)SI;y#x>(XGIj2+d9pl*a8aEZ;Q68xbcu!HW)hza#Zr^V_qi@XT8WQs<r~p(C6nr1
zpW`Da3x*f&vSly@J52@eL4%3QOMt?FU&OMa!K6qZL;J9a5*9}+Xv|#_Op_y%^-!>8
z`fL?^^TuDo#L;LuFLYLVra;qVDG>OC;gQ#boXX)TqZ=oJHwq93FHn#_nT4n+&1vAJ
zaHWwsjCH_lrCAt@&@d|`n*<?X8F5#C_`6&YBL!s`XFw0g`V&haveyC`^OY}<1;}?L
zmVmq=s@4vg5?RYvXYLhDnnbP}G9S?{1R@I^NyMlPZ7k6gW;R0t-m1Znzy`fa{;>X|
z{}f8suJ9?JBB8WAM9C{4Bb*cs39cmsQGWLXKgW(Kpeiz4@f7=sF0UYQWhGI<Y6h(6
z`wF(D=|L1t#+A_+R~$c)_R^d5&2t31b3`v#2<Rc#um1g)*{U)`(eAdiFNepv*P&3V
z8uJTg!DotCF{39io+@Zxg-jjIyp<)8RG6^=ftulEP-2TrOjNKDG}&OQRhl0Rvn39n
z+@kY3;*DP2`!A|Z6|*~$GD*n5{ExmV!m`;tSQS{>`FtYxQ7q81_48BkB%}(gxmLQ}
zQE&n@tiV{XzXt4FncHiVR`y$l1zrN9u2?PW^M=o;YqT{^5fp9Fa?9}1KA)MgMlPU=
zSw<3((`KFww8B~~&JH^eD$G2RkBCw*knCuJtH=_t#=tb-PfK%Gr#_x>Ss~eab)uyV
z@}UwSIq1|uIh{m}m}(*l^0h)<wwRR;_hEjE6g(Li3uV%RPM0wVq(hQanDJ&~=F{?p
zUZHWc>y?)_M~INSrDCoV!*dA>A;mrp8RuePepw}KqOEyM;ziC03=sT1><Qe6d&nXx
zx5MqC+MQ<75GgJ*8$$`yO$OEF70UatBw*Qylo{uk2dVD2l{;f6$zji8oZOzMvsODf
zvpifmKfd7P2wrXCTS25=%EbfheMxQyNp<rC<pTYYPB}f~kGH23h8!CgC>^Fe_5~Yn
zG|?uDtmKwm0)Q%?^b);ClzeGv2G1bpPT<SO7ZUZkJbhct6YI-<MwBk*)iw_(hPd-g
zzH$<LG}c%EWojon&wb$K)PyhzDTF?rxn*;E;ZViv8GSl2mL1^VUs<R&^_0(Z{6o!)
zFRT22OlVEJ4YjfYfunuSE&?k-d~7elLCh6R^-SC2yqli1EZt5LkVJw5C_J%b9Cee{
zjy%2%XHa@Z&H8hBJRJ_f(@VIOLzN0yZ@r~me%qUbFaj$Cj(B<&3+=oa?@~i6`8|4d
z<sm9V<E4~SmvhM8y@r4-qjQuf8rKVras9oN-lGm(v4(wh_=lJAF5Z9rH&iSCdRo{P
zVp$_A3Pd*c)7Lcsy;v*oWu`E$<bEAe;aWu_z4jN*3?tXMUBXq}N4l>HL5j!-3!8A-
zCT=tP8$ez&!(R<46CJPL5)Xg!P<Ui^_>)8FqdgsnVadOiEv-7e&&8pB{=sm`o^k4c
zJUyLiL(8v~CrT)2q)jRlK{^yySy#n-J-S&E$if!#dM4}f^|hlE7q*_MtT2Vx{gW5L
zpMdM8@kFyk1ow0c<8KP63lyMiePbH#Ah|wk(-O6tP!vcj>#kqun(zfZiAE<vAQd+U
zGQ$gPy!P9RKvO;9s*m1n?8_a>eGLZ{SDfZDY#>x|2TGz!3uiA(YVaKSjcls8jRF^?
z8=ZWxFA9v+fy1O=kd_j}4YLf@ufm)KcBnIH%b{<NG7kj>1B$@WpN07Y9^~b%fAvcQ
z?NUJnKDX~Dt<k$dxwejj&ZMaw7aZ}1n~ipl?-O&JJE+T2#0O+gjZV{guMB{8RI2uh
zU<n__)yHG!)C6n=Kf3dzr4BhtNM0Z#W$+@<rKmn#7+3KsyM_?ESf9!X5E83^08u=F
zAYy@d1mHnbuL=(Ee|{YJt~y%=qPZe78Y*9(@rB4n{Bw#R4G`Gjz_`{q<Q%6KmQ;lC
z^s?~QYUdT-kq9&nZpbLIVMyi&S>%>28U75hrD<RhAQjpSR>D#bieoecYN!JCYNQ7!
zBI7tsM6ebCBfQc2g;(BAm@2`kC})N`%D3N5vpBUo5J$tGL<qMx!Rwsz6^oAYIqIdc
z9kj8WXJ4ZCAZLtWS^z*QKT(5bkHX+&snoRQD2GoG#k`LKlQc{v8(kvyd!hk!Inj<!
z*=<2X1fz`QK&f0mFSv>H{RjV+<4hL)TL8%p-0dfzfy-93H$@r}CSKgpH%E|O8MjWM
zC?Hi)W7-5xL$u|P#U6YuFjqn&McK@R8O@`4n9<QP8R{7ZjjMSmVxk*10*eJdWURm`
z31e2Po4-Kao8jrGqhK0g_oQSbMS*&f#`wa5&*2Rv)_IM5v<VMj+I8|BYn(u$keLbv
zn#z_Uyi;T)8l|~zNs;+CMpU#Dm<esc9DD><omL8iQMAei-|W0uv4}FR#mnnOnGEBR
zzj-?Yg}K8tizq4-t|b%eX(y-b@VoS!RYZn_2UUmM9)Y5mijW;4{iVIx_AJ}fm>8;b
zRN&G`-^U?3^KHIFVIY~c7gsp<0SS}A<`9!emq=6OO8`2(#o~Z;g<%;oxB=q0@e^3w
ze#Sb63#=2M9?yzSmZFknOdFwM2NpXX2nh&EUgv;G&vsxp(F^<$FwA-nsa#{rA=VeW
zBH^?qDL_1Em>jmns4_?rk+mkE(#hQf;#m49=1>Ab6B>uIZv64jiG5ZL8|I;u09gr^
z%dy=A@OsH(I8mcTLn3%-KF3Uom_6_)IkJF~zZ=)hP5d_6*_L2j&@G<D>0McqH<-nq
zy4WpC0(m9QS0RcH;zep&DjzAKQ99@htw|Kl6y}-xyRW|W_1v?t|K6B;c4K^GM<@C0
z!?``LXP^D?a<N0<y9@!5b{2FC;@tk9pjuCHpP$M<`x7APXD6|J6E^lg2WtJKg7zCR
zt$%JR+&9t*U&FN4h=9Yd69GTIQ`WGKjU}qg?=gRf#VfD<<O^rtFbd4gpS*&7_EW#h
zUt*Q9;9&y4a^LPZy!Zd<56~-YYg7~qHA%2$;Hpq5*2<CC7(!1$676uZ5ADR`;T)jh
zytl`60k&Pz#`|V3#GIwTBK8&`hER4U(XPx%PAd|~eZb&yk_^j_+RVj^xM!#{j6CAs
zbGS(z0uWoLV}IkLM&!k%3I=jHh4;pCX(X7vhy;6_DbkS*d_v*-5&eZQ9P#ZD6D2s-
zFU44^*r#m||1OG);{vS+eMmJplW;+Ha%n|lMffrftG~I>84fTvUzThBP$2rghlL)c
z8sfdkxjfhnAx@<50&PS2^^(!BiTTaAzlf`fZQcMLnWXH8c<_AjIV}1_+)gC4KGE3d
z)6z)_JQI26tbX*ka4%%^qx4dn_41s_`8`i!q65iM#~MctiyvHtmf__RkBd*8;5&L^
zleJmXSRQaEvD1(bX?fB>fl`^eNO@>Hc5GyEere9wq+}VJWH~AJZ$%I>+NV1~&-e+@
zqQ|(*#tG$!2|3a^p2#t+r9{(!xgb&{;@cqMS+<pFc0e-N(PHS#p2lV3?hb$v%R!EU
zDRhCofh=l>9W;{?J_y}dJ^NUOg^%_NLx4PjfC;*-<5s*P4yg@57ZatZv^3;%Xo8T^
zU|g~k#c4(pH9`|8YfRe^GHVuk1$9zQ!GOWzI*(Wz82?K+P=mVP(*+xmG)#To6t@cc
zX?oHYf=qJZPv5eOl*LAZ*+6nCGs-jMkVunGLNA~I!i_DwSI9aQ4=^J!ILYRu%f<a?
zY&aIcIYojIB*jTHp;DIE^hp7slMe+CssTjCL?vq+WDL$YB`Xo=D*39YmMW}QBn7?e
z!T(??R7F~WFU-Fk5-^1)CVvWQr`bo)NaI4{o6Lg&nB@o(jgitX;By6rJ0S{K%ZuVn
z8a!Y2-VS2~#bT8CJ4&y9_Y;lI(8_g0ETBOA0@O@1`8*pK<4d1-7WxTrf`$+$i*gm1
zIP_6omrG|j<q({>AuKuZ)1;pm4`7iwGHS_8v@}-H54OYHK@a$fu@q&ZaZ7H(2jmy-
z&isveps>>*cj3cYbR*_J4L)sj@FQU@b!HR06|h0&u;y_Mln?aFFz$KPQrU`YSGsH{
ztu<z)o!Q`;b7-#ZoBM2V9Uv?Iq1ALvw5DJa%&pOQB+fFy12diwmJC)FW-e6+E!16Z
zjz`Q>M1vhXU0HGHWU6(kd)R17^VNDj99b+h44kY`$`Nkg8Uh5%Zi$5x$$R2Pi#5PH
zfD_N1<!-=HyZFIv#fIwK9Z&@1ii;pA`4^9*?2KtAS-CX?u-I0%&Q@ZR<6i#By|`t|
z(x?Nl-I|P$<PvhDg9TGY0=!2K+<~1s<BGa;9z}Nw{D%~IJxYD?ox6$5ub2iw6{bpR
zQEXRCs_Kq1+&qBM;7Le|@AP&wp&CF1XpV(l@o+?xAO{&i03g2546F!xE`Xn2Ybwy4
z2sAWS@7sbUm9~xNGISfY$E4-KNmWClM3q(NRwAA%)`iG5y<{+U^olhXJ!O>W7)_T4
z@#h8FEr=8A8tN#smzhD6{A6{Y9Ley?%*qV0a7F2wG(x`6Zp9uTTgF-gWlnQ9>81<@
zYoh$1BaS!5GRtMT^^UBOOzF-Y_>S<N-7Q()6Qj;|WFz_$b+kx<H^3K?m#Kr(`GhnC
zmDY)(nY_~J16s@^koP+X+~o^9KXR$nslP0+L@|ug8pHvp%Ud0T0WO^!jmhT}vcHh9
z%*y`M`6tzX7;N57+WbQq=nKpul?d}m%C2{WBs~xnXJNkKQe?W?ZI@Y&07g)R`KT*1
zxX*H1WPqX9j1)%*@<a>-)MC=)shxJpQpI$=+?}--nf4tqq0+K0v-Qc}I>}sm%pR){
zRR+|Nb?tJkbpqyYwPMF7+ykmTcd=}HD0<}@UNr!T3F9n#2P$z}=>$~*9wG7Dlu~Nx
z8Iyr&=OFWkL=YU-;3kzFJa$kG<N;YxBuBILR+CxaPI4jk6AVvARpI~?mDX4m!DCsr
zHQCgJjW!1-&N%al52fpo*|O`{C^Z%3E2ExUCjEn|+{XPc=AjcPd>oz2#}o>Jk(IP#
zX_KJH;3MUVn;(joyrm?WG->57<+`!OS{#$af}J7h0EprkO49(2hzf=knJjkbSu#s?
zGAsKz^70(^ZrxCf6xh_IAN|f^QocqpC-KMY@(u8(UW-OwsNqj$yQ-ee0ka03@4O@L
zioE#2|M<z^03;!lD-=U7#zW`FGzu?XA_@r<oCd^N#DVH0bCbMm++!_08>okXJ)j7j
zNI=>Ox?eifRka}|jNEUVgS8rkUnu``w3w~ctHp1-YD+w->plJRC%#iF)>g`C$&v(e
za-KM+B^BDEnyhQZ1Q6gpN(Ei7aEsS6u1&RZ{Gn~LUL>#{Cu`r_JYhfV!^&`S0VJsV
zxrbVng4NC=@RV@!%j>~0R)mj1CFNO)5OHG-u&_IQeT}W~@p%~jLOGdcZt63=&ZX~9
z7}=VgsdQE2tioW3Dm500x}irFZ12RNrb<zTgSHFPlC~?sF(Ts`p6GdS_ZS7^0I)FL
z7ARR2#<8x*7zoV5w`Fh&emMeT8=eOT3;+dX?5br_f{ik)B0W~2j`zu_6W9yP7mg67
zb#Lm^9EaFhm8M-5qC8)=5|QNei7WYkwB9gn?^#t_;i&V%^h<cTa7hGt5xmHvP|+He
z!=?>|<C_$8<{b|846>z6<N95k#w~`|ln?~zSpX%@H#8$6#HlHWihvxgp``O!;WyC3
zq*JemV#)vol*LH>^_PvSJtUSj%U0HG0fE=;Xw=JgwMI99@>hJQxPo<YSj^_&BwBKV
z5tzAzMM^SVNH_4#_{LfEQH&t=v!o3to5q1=@C&kw0m@Lp`ikVM1NdT}L1f@NSiX!c
zm_1GFz+tork-4ic%o-!8oz!q@Rgi0D)UF$48?AJW6P{n2Rvj=+kO;DtnE(ueIG|`G
zG)A%Q^aXZ$PD(CJbHB(!Y9!xbV~{F0j31SZ3I9Yy0={vq0#6QYV&M?LNsg5yQ=9-P
zFZ$-{_vVdkS5&cif~Q1oNxAN#S2Y$&!?o!LCIZirc_))fcxlYlL?9|B5uZLT0AjHK
z@J=jQ)|9ut^CQiGo5nYE(lCwc3ThEUHv^mK>=qqVMeJf}2eq<N@7r}{oQ(ndT$dYV
zO<lIo^$}1oem_wgA!nHo#3}^HDmo@u6k{dhg&d{)l?X|~xiw&q3vrKG@Pvna*3>N$
zodYYA)N3(^u+uS8sLg_(0n16II1v+znd||lY>`o;6Z~p29gRPK=amvS+Nuy-UYo8G
zM5{|uZtLWGWNGTr7jGj#{9!4>G)p5%<;O}Sn4<20IRsQwk?bQ9wi-9aDZSG(4w%OL
z6Zi<oO?YWjni4)A5)=_^l1q~^zy_tD(JEsP>x$5rAlajV?trF=Tco1~2og6$GhV`_
zdD!+>|L{Mu!D3LcpI2xiu7DzW*;^gwn%M#~2)I;_>2oHO!~&4L+Y^}h>O^Q#;k8pV
zXwro7-R77INg%HHtnc7zI%I1j9U~{mtfh4T8c-$-M;FVJ)==ykSOvR;dOsq!DE0V<
z$k1j}l*slX8-PmKL|xU<U&l)CT1;#)I`fwJeeAv+T*i=s)9Bd>-c_5OT}&d`1%Q2|
zuiTutPVUY8Hc%$#a+ZFqLz*OJ1bL`l+5f6=lLUdGh!CWt`@#q1=UVt<@pAZM@p3A(
zzK8!`RT28E`|itVP_C0u?ebk-V->xTn<O-;H4G@+{3_g}H)mA)nW31VIco%`HC7QJ
zrf<9nSkoJFyS=eP08_8=q&jF&@w=@~VWi?yl{I$Kqi4fMc0zL}I0C8i1=xTDU;kn;
zLYiW^@x`z5d*^58l7jjAm9hzodBiKMo$l1%y#Chz{BM_A!v{MLzGwdDrU6k%52W(x
ztXPXI95^5?i?~a3$P{xu=T55%WETNO;4XlOBuRpm3+)18ep_fVBwrJ!1dAD5O4>f?
zYZK4A!Ty40gqh{x>vGO)8k*M}f>%w)e&m6-V|ZflcCva$d<<{P5Ud$t$VXX*c^FQr
zh1ZE$%>959<fR5{GuC3<AvrK5m`OywcQiL5R*T;80Er+iXl)iuZ}so4LBbVPp;n;c
zw7+E`$|Xnx35^p6BgZBKTgvKK^~n;?K;}}cWyl<&)ie>$kBvF9cr5L}5g4MuOc*}j
z;Aqal91&U!K8+?u&RA{zOAdU&a>|llyv?dzuNaE(&S{Lic`xa<zoYsga|}U;zg6RU
z;lD`O0#nk=K^@{*B)ub@FxE$IC?Q`L302zNO0q~{NsnQGN7$Bnthvi~XdS`9tknwX
z6q@5fLNI&}K{<h+OMm`bbWmmHyqY2IE4@m0#z<6?UgF#nWO3eWICVwl81`KNGlJ(q
z_+m?G)&V4;lPV&y*@xIwY|<2M2Rkt}K|8t$VJyxRwZkI%5T0bw2({!?GVXc#?S@#s
zj$5`-B*msq=KG=aq>nLKw2P`gJ39`Xg5d%NW04BFDC}wo1i;LlRB3E@(<<R!m_h_+
zS?yW7&bhALs_P-*${a95+Zfzl+~vf-=u&<&Pz@afEcTAE)NsIlNKm`o>(i-iJzg(T
zF;>6u2pR1FV$xZw0qo;)9Aj~6m2pj0$r(H3+|6x_t7<Z7wnztrjV%QM2=+ING+Iw7
z*jFxSmb1-G#6eLpQ4Y*Yomt6VO}T-}z3xYJuH5#n@zl&Zy-TN(#UdemwF(Umm^FDI
z6i3YrCtmx@FX<G{XW)yr-1LiRG0M--YQ-c){c$s8b3o%*_|Y_yzQgh26L=EjAz}V1
z!{y@j;^;@7nK7#xVUO9Kkaf9UMJ8>#H)KU846_=-Xae697R)36x3ZCg&AP+7<c&&5
z6jU7#Fp>nZ71)OB1+)b=Q<AWZAf4@P!CvSoI@w}+Ag&HUBeP-~?J-)MlhbQ3)?MZp
zt6r>NS%{p;f7I~(xq*V2nQo#5#s|LGMPGC*z8*M_EGTrZ0f7Qrf{AWI?cyE!-*IIl
zSu^AXzHl^L;%y8E%z^tZ3P~p-gsGU~frQ)W26<fR9dlqzKmJ#{hW(5;s+Qt0mAFZ=
zl(9ANkGAKMCEKx$T4LLE+nrCCQ_8loF(z|1-eI@q_?LxRxS>W0V~lrU@E8cAife0l
z+=MlP386LY^poLWN@WtWT8t)$;)GTlw!?<=Ikz1*))|}Ym4a!sb_c`7FP7F9MA#WT
zT?C%Yfv<sP*q&KaT%$6uw~)c2du)R|F|(do(XiJ$-Z2Rfh&@HscZqVEkuY>`2aB%g
z1z*frb7);mn^=z)i?OjiO2wd9gidw+_q*T5a;l8Xl`4*B=Fl%@yx}TYC4iNNKuZ`U
zAo%s2CUARzi9uSV@Vk|{-}bJwGglgR!Pd5E+d0$zoN1R${PZzh=+8|$!@*Xw8qAnC
z0D>1x<*Uiz(@<qffr(c47K6Fqo<nbwJ<ztwCIcQ_$r+VmJTr#@Q*=iMSVDOt9X%&U
z8o6}0**#}tY$cyE?TkNXFG9{!<(l$p+w8dP?O=PLvNfDk*D8B^M@!|RIe~M%Hx-c_
zZJpsqDIep#XWprnnD2k`a+U4FUeAFnz?BsV|8FEcADNj6!Id<o6%v%4#@68F7K@Q*
z*r;uW#&is5mR+=)#3wAQgj(rh(W{2^w$$X{mE2`1V^Ys;4<n}%IM!A(i~_)hp|3q}
zM#_wc*R<2~hR%{^%Cl>VJG)7)jdz9FW_SCh%5=H$XH;c}OFB*SYJJRx1BZaelyS9=
zHC_nj?}W;56Q&qYGb^Ewp3u0-HqB_5MW&ZONuFrN6m19!=6N$$O8IwvxJ&t{FWS>!
z-bJ`0n#?aO+MlvVm79yZs+GK7bE{rtVwR4#UB_LtlR=xsYkq@bA7lOz_!%+TIUNCU
zAiP1bD#><`nb1fNDqF}>RZa)7(YiuGllF%n>Iq6<xIz5vuUVqgUJVLQe9}$?LxRkQ
z+Gk{QFpL6^;4b)5G!foZ#@DuO&!KRc_wb8-(YDcu%pAXF^QLFpG6d*~gREDIta(m&
zp{SXCU?B`dF6B7E;^yjBs)qcxcfP`NpqrUuKC^Mq*bFtA$22xHWawz#Mx+^&BGGB1
z9WT19=58dj5A@rTRHo4QIY_YJ5F@%uJHO4gWvS{cc}vD(->m6-+D}3(h^fFcrhK9s
zQ>{|yo5AMv>Yx2l715ultM<sKSIfpDm1Fr?d&74I)g5YNRLw2dMzdD8Keu73c49s|
zIDRp%cOP-R=fRD#HMg~7@6zgi`+f|C@_X_veKB9td*;r!ui0?Xvp1A)x~6rLUCV7a
z;??rE>iN0nu5ojBC{9gX^_jN&r~O&?Q?=1s_1N42dvIJ|t)JUvN(M7nT+X5NLi>i|
zWA1e-_ruUTdw;I-$%}jYbDQ1yfu+qaRBBJRxA;#4pccJ<`cUe|64`97-Mnx6a_PVR
z>TdTT7X^+l#&O$@?e?NKpE=;R?D)!Te2tfV&`vLFyRsp!RodltJ|b$bRUWCdk+4;^
zm+UI>hHMoiedFY%O0GG(uIkr#PJFel4$jP7Qyv}Ey4u=fCpA@@we36d$p$dC@ixap
zz)9Xv^Xb0UL))FL&VxM!8+ijxxXYZ{wa4Gn?ETp3<fua;!JGZxKH@pw9e+AM<!|=3
zd#j&$Y%%Gz6#-IiHvvv%8yC(c@y%!r@F3fjw6ZN;vGsU+*=BJpZ)kf{s@%T@o?WIg
zbuM}R8y73NI0w82jq37^=Li?XY0q(Ij?Le2b-P_SxW<q=6wro4O`a&(-@H-M@N_s=
zXMZys1KsHxSKn*m->5^WcY0H`L&yEQ?o5X_-Da=m-FmhL`)Q=>TJOYz;e>s(xO_);
z)pNeRR6bE^jegU<_j6u5Ay?D$`+&OYBU~NV_;%FG#yI28|6+Kp-LwCW@>x6l_H!dA
zN<FndD|f+dx~L?Oul7PGN^m**k|qV4%9?!aCHtjL?zL+>&l({<>Dx=$r<@18(LV#Q
zOHRB{d({4BetG@F0iRzwCjNeP`kVPfJ1Cg^{LY~F;&f>^ASTfl%GFni1iLib;}3ns
zpE&!kgXU?0<C>T98`brj?%Mv=u-9z8>cSLhrL!b(qwUe?Qhk-k!~;|pzs3id8q`Ah
z0S6hW+pQH>(KqrjWhGY_OqUaGkGXsYh{(xu7s>bUb?Y<agRI&!{rMVW>1ilTQW^Vs
zu5m`XXyS5N`?Zr<6WHebsUTO61;@+zezJULa6M!c<sNqu-Fw=G?f_Od{1v}Awa|M!
z82G?=?JLE}ORn47lUm-LdhByXKW%wLnV?<=R2E^AZFYL(wwTx^aEuXbWMIUeBW`^}
zfTp_b0fQ1up9P;GLXnhswHQcc^jx_Yfj`ejvgU=jHUs^Zt~$VZ3SL-pq?047W`n6L
zm3#Xsq|NQJo(3^nIz{w9jG4deeKIJG{^bO{lL)(q?F_ZIk;xzW#jW=CpvS2{+IQOD
zGkz#{$tynFuI;`)*!aU#d55O`A84x)TQ65s4MLI8BDzo4J|l>q3;5Ae`r`T8pCSBm
znf?tb*KCbu$!xryG}`WqQl3FTGmh2fZAAY<)^yw~NhJk$<0Oi}NWd-9!`<Q1$~&@}
zJL0O9tpJ+)QR-XQ0>pj*u`^OnI!IyqaYyRT6KvoGFE6N|8Puk?obHxN6U24ae{FUD
ze~N~?p-jd=N%a`e3dHNg0fD#=DC0yPRvc2?mtP(NCA44ENAjcWa?>LtcCt(*^E*bm
zdTO7maY8v-Cz2E3KUZJ2y*+BAYj(jN0nfpi>tJjnz2=F*kgD>x)#%}Tc7XuIR=T)H
z0VRD^oep$)sOgNJ=_O@j*f0sqTc~}1C^$~w<j#PUj=?^sH+QL6oYIHB7F@dFo@m%X
z$Op1G4wic@wubD6s%+})ZTM9uuIwRgS6Sw-ZC{vGfT#5u!$=4ntwLsT)(6xbEgMub
zQ_sf)BbJReN|LFx$bX29V^wGDQ{bADH4k_UIP@UYV$aDOY-)eo0IB=8n0iZa+HM5f
zy|X<J4L|B{IqiI4TurAY4w0enz(n7rKY9`)94K^Yq)X!Rs~EWK<sHV~OxA>@=!!^5
zBH6BGIW~=P7A^1j+eQFiZAuZq%CcRjT8G;;Vy))$RU|%IhNV^k%x`7Qp4tdA3h0el
zj$!95HB#JsUr+Dv1<m1bV&|ud#`X4$x-UGw-Plv=32GnR(tO(47VO-la;G=#%k^I2
zOf8hJxNHAggk<Hq6uyXU2v{lnf%jNC<1a|sW9HXV-R`-#V&fcHlGLoqvE8+v`yR&f
zdDA%H5t%z;SC`7b)D=#|fY9M!je1D$SPA6T_&oM0`bqLLtMBFJy58XQrm%PNpk58a
zzSQHvmjdAw2D2ASj|SUw!(S?5ymr`(?|bZuC7<C<H;#A~97DH=+2OrVvJ%%=1aaeE
z1lSE7MC`y~q^!*R?uLz|4@mx4X9xq4+}bh5T_)Duqw`SYl8+Don-~|`az!9asyHmc
z+sX{JN|l~a+b2s#@11e5m;?c7YEJvHei2tZxaT4BAx=HnrOdKP_HrtQGXl|xT?A@$
zB}ZF?U6*lXIKHi7^C|*<xr7Z#tBPEcHQ{biKgQ+6NYH8cVX}R~{z_%E>AnYB)b7f?
zP!Ud;6(p+B??EJs%WQA)p~+2VXb|%VY#8KTI5>UUslF4k*=A#k&F!v{w{>V>mqIq%
zUj{~eBM<Cn)*!ze2Y9&#`BSgeAg`@KZC`(l19o#KnD9-7%un34<!gtfsKW<u=;O!!
zpWuFBpD@XOg8SY4jy3S`jkw>5PrQcv1s{F=CcEBrll}i(@G$rpXz0&K2KU87>ze>V
zSfujRv6ef(@l8BxzLL)O%YSr!U;FkCU+KKQapnz$$NiuB#6R~}TEQa67q!Mdb@bRn
zDB@sO{e%TbWlxi!!90Lxiox$lo^6zfSOk0h<Pk3m=$0mtjWfiVDrZ|Hc@Xvs4xqRu
z!qtKLK&A&=`3+>dlmzM8Ne0P~<rE!#tf&)C8uxkX8O{`eG^kgWbHhz-kOnVsox-H)
z&7H3}md4d_+d@vkAE=X;WgE0cK*Ld&Sr<1{mLp85)(GI&FaiA<<VnIKRp8ttaA9i7
zm*5I8Znl_13j)d{p47%UR|-q(1@ggN%n%yUD1p$;K{!b~{fQ%Q!K*BrG1x@|@C>YK
z5uXQOw7|_hqnmq!BuTzEH&mA9o}5@nd=Hc`06#>4Z<!#q0!g>>UOcVFbpf9P+^6Un
zo4sNwX>-F|I^+SS7oQ?BDa9c|%GeH*<Oly-S5-yL8fZcSM@lUvEzqS*x_ge)8XHWi
zssX4SpwGm%@SBnO9Qz6I6Ub;`&W57J+LH%?lsrbciI{jHiwx|yte;ddL8L@QK^Eii
z+zs2CotbZyO6eZBpM>V23DIG{u+Ay=`KiKOQU7+TaAW`uUSa}JbWJD&XBG@YlHWPL
z&Ri80*KxAN@<(WhII21dP1p#)Ks=dp*q*uJB7Xw9dK=QZpnd$kNtRM`5+9KdLCT6(
zSZ7fOP_ZJX5R&t2(n<TqOxwHgv2|6_+;6dmIK+&5t#~mHdWljN#%+?=JELAW1&}#p
zUgM&L6)!du6}j;WRO=a23UVZ%Is|T<bTvX72X#AUw<eT=o3g&05J$3mzyrR6+vnz{
zCzLKQmTqz+^zJXd{Iq=PonAtUs)NmhDAb}u^(iONr~S<XMeP-n-+tP2R=@fM&Om$2
z`Kltbl}(K~;)$M75Si6b>S|Sxjg&D;{F-JT^-RtH6V2d>%EjJu9>we?&3yorFq=*}
z=S+fB)NCxtVRF`-qeoV<_cFX=dTwS8e%_>eSQXU_Ildjx#~}$s-Q}wRK%4R6E>)sV
ziuSf=p3X;)I-3rv0WTQ1kjPS#F}JyPwS-c_h5(Xc^8_L;n2ff`?!^Wq#1M*VBq(xJ
z1WRD&K(HWU%&i5*RRwd=Zul1Hu-V7krTC;5M59F})1avvT)!9?nWkC5JNx;+W(s8m
z)L=--=k62HDJn3AF%zdWYBJZJQUKJN83CdmgG!T)E|WgrW<GQl!c4kET?XGI;DDC^
zNhVFWRaOxW7nshp84d7Y7;vSuPaIXC{d1;vf<n_Q>K{CNrQw70STIQe6*ysSx$)MN
zU65m2dM@B9ARj;3AlaK|@crY)aW^hQSgOFfBO5q&e0r%+GMRfU8+=CiT?G}=&0hZ6
z426c96`2)Ybm`h($#909IQ6``Evzkd*Un6u%h;}|D2_J+bMI0PHlA1W0ocGgfC)~x
z;6p~8V71DSI^wFXF|0cxoS9zHNmfd-ljk0^<H`i)<0;osyDg*C3ayecnL4(W<ddlv
zODYwD-ZoRfB|%71EFujSi-zxSzI5`hjm(lAN3LsbATI*Ylb5%B`>^fRf$K~ovf4~n
zmu@f+V<?qvFi0GFs2zllL*ZqiLkAeJLBLZS`FIxA2lz}T<P66Er@Bx~Ay^;81(e&_
zUT7ZljblZ}*^%6QXF=svzFZ=0SI8%|mrV_sz-9niTj_EfcG!M$_JobZMkw4rMxS?#
zxLp8%Dh(TBk{8Hj9f=oX4lo%4qog;dNIKI>u>>-1)DsCB=GNoh=D;lWq{5(ReDkpk
zwhnv5gI=K0a!#T4gFSckb3)-8V6wfb$ie~y9O6(MJk&8bSAag&vQRh<PN&D&6g*=T
znx|2PS!(3XLCZ7R6`!zmwJAkpB!P9sFg)fsi#>*areNa;r}S*<>Q@bDdf9Zpq5R(Z
z-s&#fk6e>g(XX;Xy79Q}x|tG~p{j9S;;xUFS`tiW+LP+atcCuOF;0)inM9i<#{g<Z
zCN!lp5yo_o6rs*#yi#SQXf%+3Gi`1wG9UFBFZl3FoDjRwm1WqDaJ9PF>B0!L!K+X%
zI3-6rOx`8bi!bmuPG@*52MPksF&n?n8hOlRRX0KJ1gK}@QqlS#veXuEXu5qYV6q@r
zIVoa)rPOog($uF2ePG#3QBbxp=T!Gj`Nxp0=Tq$zbXko%z04E<VVQ62-gZPrs0OPB
zk$p@eCZN(8?{j!01nF_8(eJVlVBi!=s2$u)Df}nR^U|%9HpYU6;v_2h-M?Rl`Vw<)
zmD4Ouk%eNQ&ESECpsJ`6=XG|ztD_>))Fs|$6JCrB#ra8h*GR=$%tvj`M!MZ}c_l72
z+|gn<liHdJ(GTx%fbQ!MoL5y!&9)O7LABUuswZx~LY_k?Y-T&@AX7fWow>s9Ww%rj
zQ=->IZqjPT)y}5pA#vL_yBW}@)By)#C2b+lFDDaF{u^~pZ-~K3o-PsN>YQPTNg@ZW
zUc_`U+5QSO`kU4-UjNqai|(9vH78EF^5CscUhJ)XWM7ZE!OhNhf2`)$_Sr)hef95p
zYwn)@9Xobp>wxK_e%aY@we12m){^XmwsVywmv`J-0jje#7Q&<Cs2aEPzR=<vN+n=(
z9Uw?Eo;7zbk=SsL-Y|Y*Z@+hkhox~X=E;K<rROTU{cwl3`(#|1`C(X@sW&e)?XNq|
ze9ygs=iT1)H>JLO5ItRRu50Qob3NBJR|79|+_}*|Ui|X*oxlC5;D+me@OxL3+b)LG
zj6J+nKQ*7rZg+3+9&=B)sVzqw)7j_boVs&=m`m-q-|NP?Tf*3{qq+(MldzLIVb-m(
zs^?n-bXGnx7p;(A;A4uo+$G03H(yCw;e7p;p?v<xf&Re@WSOWYvC?-`bfT}ONG!=V
zb|o)A9X`MHKJQy$YF}SG6@&!H=!Jzdlc~u-IS+aVeSMvt3Y@7;lR;|xrYHLPdy>Uq
z<0DtbWm_=DciEV$hq~8LK7!pwt|Qk?w&mCEs~NrBCRf>&`nz%NQFr;DjM}3x^wuEB
z)@3-d-59?dRe5_%*0D1#@Zuo5N9#mcK*mmFWlh4e&82op$CbS$YH~_>Rf2th64(C6
z<LWDNdEY6riht$U22#ai&Gv4$@A+nz8rer+*ntOnL45Aq?pGiCaOp-Mzx_vhpK@OE
zkHq_)a+aOsfz~VYJtzKsEe*)GY=C_&^y*i<eD;1@y>K2NSF(vM*|YmOoH^>;8UscG
z9Q~OK^R9J~549D%;PQIFJ-3|Hr<ddKto{6tC*s`2>EZ8W&)Tiu*mp;~#jU)m6e-TU
z+2_=HFvYFbKDRvmd&RF2E>F6q-5&S+a&Ut^aE9suM~V47R+{o#S2@pqxi)=c>Ct}P
ze)Rg_9pvgyz=wKj!RiAWs;ryIa{U3Yt@51*>122)@M}M!!ba_mGF|YV80odsK773v
zsE*ok(-F@jJh1E@vPl;&j6!O5PHA@puxgYJd0sYM9pZpPV%RcgViKK^UTpchF<F;J
zF_KAd1|O|zSEna;DA2wi$8kl-jKQ@7?FmURHr}b65ghR_L>w*f%%fDASXkI}+JD#v
z6Fm-#>P0>0WiHMBa;84wR?nARNedVBw?;qKE3BpETlNT0c-zQXI8JBx-|Fbz;cj?U
zCq`^S8~1SM*hSh8*yQ90`@Ipxw{pB7VCHBRdRW$E5LdvPh`c1RTBYSx0QZ(@DNUQX
z6%2$DpWxY`O;gG41+YhI;MsfB5VZ&<)h(NSqrAh3hJ#JMx;@xLOMq0J@YK7&MFAbA
zeBY<$N9a$sdoq{)*Z(6ED>b?VI#vDdO}E-fNdL*fMRu%F+q>4u{v2@3iJo;mwG-~D
z>(sOQmAt325`Wqjb|SSpU}L~Zt4_~lttp+ovO3g;pvN-Zf<cyu<oRtH;uwC;Ds?Uw
z?3o1GR)X%7g5;5L`wAl6wk+6DbIyy7OUB5pq;%Vv(pygZ0EvA~(_i$Q-gO&aHJx%S
zQz6?=CF!ey8r3E+$V0tA*flqsw4D*c0@7KtI)b%FIVK30*y@B^GT_UDH17G^1o1t<
zW;(h7!#*DuKtu^v_Ts(u=_nN7`UB|6Ozj*pJ|P#Ezpg@ba5e@=JzuHDs_$z>irS>g
zci!y<XO3ZsPB$Ta1Y6Z_1<ux5(cfu%oHhDeQjaXy%}WP|`G_k~>%(BC!xLLTUsHwJ
zzdYh0DWO}|6(Dd{na{RWY~E~V*R>wSc#E?fTVx3Cv_ZRTBZ_JYwvn~XJ&H{+HonnT
zd#$qNIHz#ZYFXlS34ws|xD6g)a&ufFb=Mixxmwy*Y&oa>OeNspcYBf)(euD(EgA^M
z^r@gvm7If3K;QTMySMdVweJH2G|KlozFk2fv-@{D5!Aq=-l02&i7c%>%Jh2{$Y}v3
z?mpsyqG6wmu8d5ex0E%JOHS4Rj}u89w!!QXoE<k3C4M0>4OSEz8tfUnS_b)t6j@?o
zf}uam?9)#SC1-G}`d*%-YRdTaL9u+`?wt$oIs>W?6YyULr~7BjVCQ75S={-w)7uQX
zy;KnmzCP$#=U*Q@`(Lbm-Uv(LOUky}UiI#G*oi(wo!HS$Ugl&8tU1?W3=eoIiH}`%
zJ=Z<jVM3b6WXgf1b-t7N>;=c_sf|*&Pa-8D6v1?n!*}36vgM@xQnm8_*m(a^X-w~B
z!sV!-Vyi=&PjA=Z&Pk`T(4R|hKK-s-`uc-Co9tBIL4EY0KFSCMe%~(O@n))U>3v@p
zyTkRq;m2T(y=Q$gk8OcJ1eK89)x61zgH(}qD{sYtwR4BtFgKD0dr5rOpR6qb+#TEP
zc^raz*CbeVm_zt{Mm);y)RS^cp01AzjpIBHT8+=C0`9E%?{i-0_8jL{+T0Rq`zqsx
zS*)%iDR~>U;NENAvV=*k%j;&%9Z`A*QKj}<q7!?J`>A2)VMRs<-i=?y_;6JOfC~v0
z*wM8OP{%Rd#vV0Vkd`YD0`f^JzRfZu-qh_{Oz;8leo6tSXt-G^V@DCAJ<()P3)$#a
z9xC>kz0D@oEdW}K_l>3mY#h7{HUjZMRebjkl_VW|6HeH=>x}`Lm%+v-UjrN8l)3Do
zn?JjDlfC~0V)^7+l;^;cwGKIO;Hk@q<-lu*<y!i)*IM$UsZP}DiMt-{AeP_$;0+HC
z-}1uFr<T7~{N8d0s_gsTPeYbqmv7)ZzE*nTO_1f*K9I}TAj{JGN$kc=ek$VhKm7NC
z=?soz>Z>7qdWIJs4-kwP*PSnIBw|Ek-52nJ@hKX-sqx7$y@e8EH2efRiT}d{L;DS1
z+ls}Y*a&bzfAHVl{N8I9igo_eU%^lPL92e|*Ny-As=+yzJb`(R|20*@@R48e`rS?a
zgnXPcXWL%%1uvOXnJZ%`4J9jURTK7t^*N!*<X}<5;F17OThc*O<>9ECAt6*lyXoPv
zi!aWDiWs`kUjd$kl2&ncl_q@EazMp49|rDGt)`Iu?8?c$#0x0qH&EE#x79pWoK&9o
z%7=GBQRxIo!E{fI>|szwC>DTvlQ;nxY;EzOV%w3@m-wpW?xj6ACjvdhxO#-pc-FSq
z7}cLK=Wr2%3rS)o$+oaz?V?KHv7q3mHsjqG1zdoFPHjKsJH;=T;71b6@H<xwsst=?
zy@J>ikl2T{pm&EyTnCRY_oU~bN&%qZk|dxu5~?Hq7sQ~9D<EeQ$1S8qXsDMik`1RU
zA+e75%%ptd{aned9B#skn^qG(Xv9gJ$4z9)0#n4VN`cAgdv}pQi%8&5EB5E;_y+NX
z&c<no)LaF;rl}~QA#4ee4d}!YwkHCb7PZQ(z!zDm8-{*ZEkYY<_1lvl(uu8iSIm6_
znRwbi*qm8c&?Sx)xCmB`2`q6+%@u#!4;BD-JslNa`NFq}7YbQWhRjUKN_Yl57t%-F
z5W1`uXw(dT87>wbUr+zRZ5k%Z4Yc9q%xx7sMI0Ycj0jG&Q;dA&A!*WTHOzzyo6UZD
zP1n-Jkjc_8Lzy3|fBA2S2trVEZg@u3m>d`S%xKU(@K6$s6zMcLBZEnPE(RI!nCH3@
zd8#3qOf&HY&2CebR3RHO`9>2v$@dS!*X(u<&*#<3dl;g=1s^V;-_$`<rYB7aGC^05
zbK3Fx?36gi|M?4yLC$jtkg9~Wr=3LmV_;|-4maUchEfxGJ@^BdyBi-ak*=m?wJ6~*
zW43`MCvAXmoLgd@K&VkTFTR>E<a^yTB+ewa!5hazXLBjkJYtK;S!Jn7bN0Av6m?<z
zG^cs%;F0UFK?1^H^9#js@(}d9ejoAMZLc`>`9%kSCF(MkmW1L8*a%R<65^&{g=#@u
zL^DtaNMN0CVAdeuk+g9PRDzz8G|w{T<x`fC1iOeHl!Cro4!9_CU^+OPkczXqcNxj9
zSDawt!}}R`{d|ki77cO9<sv>77o2(prN;X%!}?vqUH1|b{3J&8;*+uJCNvIH87`U&
zI|_=Dts&fM3=gPJl(8Ky0vLd<7(O*nlLA)+;*I}c?_1GEu&9O|@LDD`H{-D*bH2w;
zK>W5mfg=PIFw-d@&x|Kt&yZ*@@GaV7^BlJ}W)molAXqb^q6j!j2T5e2Z%I;k+KJIz
zU`?a=Y^y8j-Qe6d4lH92gREy%eG719W*Cl57J?JK?M=nJfna$6Kd@#&1g$DoEHoU@
zH4a<6ZO{oJw}EF3G*S?!gcmK3Z<LU7>syuMH!X(I)>0Ux$o)<Bi=mPgIfsL1|Kh6a
z>}Gc@bV7R@l*&!!hiav()xGvr%*;$z=C`^-?gD@<3GP_>*kBlF3rTG-VGf(@^2|V|
z;+2d>GG76}L;Wh=<3(+<BNd&Xk$Q%;UE2dT0Aw-*{SJ{AQk<%$!?Aa*{_quHlfe;G
zv^K7`$moMrtiY`>FkFlRL`qo<HV6U9nCo<jFi_KWyG^4^dpLHYgS+f2?Z@p@zSPf|
zwq5B5rtFS4J?+@nI2(qGQR$$+Ri$jh#mk9?eNf73FcuVhQ=3Yu7t5(o858A7J<Lq_
z^mdCGE}L+t$)!sl&=t*7hy|2q%karRnDnz8k7T{9zeCxdvTHhW=WY9HU?JC>Pp%QO
zyQ=3SbF9|=;aK}w3WbDj2w(Jwms0bCrO$-f9yo7qGE+(^f+thS#vfd1)KKsNJHy^$
z*gArBZt*aYKj0W`VE9!M%irMBPzZ@LVTt2a$0)HOQqVKv$V%F)8n$J-TZt>~{5{}u
zWM<#zL;G%+7+;Va&#X@TO|$_Qz;i>GZVO<p>r|Fm+-)l$=e!w#g=H)b3<>~jd@1<`
z_y>>GU_xOt3X{$lMVrh9@OV$N#{BeKw)Te;yHQG=F?6x9shQf)JYFnrNELzk(cUu~
z+izdAjc7@-qGeJDoZiNn`a_|eDG5Bsa|j`jP~WwOBFaINRwRC$#EFbY5}&i;hUMwG
zXgW+%##q@qpUPBBB+wu{oE%V_P3kO!b{<<6m1$YV>d?ocdKfF{)3Rw+OG`fBKeF-N
zL>eKB7h;iT$D?!?`<W0^LUx$!+1Tz%TpPod0G$UQ&b4f%Q$2xh+mr6Tn(9eGdd~ql
zWJ^q-0Ba!ItZ`=g9y{X@P}-dHgWj!9(+*O``~Dy;<W|=oG{+4mW)`Omx3|Q6<&2G<
z@ii;!A^+Co?dGsHjxo>jR>K<8(Mqf<z@3Smtw1|ww;)5sP&}N>m=j4W7!M3zi&+r;
zrX40m7^Tp<h=Z0tzPPRXsR{e3i6d@qzseu6<6pI(c0cUzbN1K|Jm`GqEL=XFwR*F=
z_N(5(KN*;_LpAOLQ7);Bo3{wjNCaM%tZ*%C8?83@svm5zZP)U4KlX{8o3ne|i84F=
zRIU4Oz48Z@=N`3_DL1#gVe%z+PVKWdx9xm?cIozm>J!Z)@2EHZ{!go4-P9jA+uo7;
z%rD&dt&8f2e?I%p><w2>?e`P=y~X}uLHCZAdf5bZ??;<A1kb+jt=AR5W6yVwd@Fy%
zb-okUD&9hMb9|v?-x8jfcRyu6VApqKM*JtYF~dV91_v)z(vFY14l6&zeRdDUe^^nU
zcdv#82pckIe<q%@4_Kdf_s-eF=jPm{ZukDd`(tlpaAQ*QKI?n=`#k%wyHP(kdZ_!v
zk{zhc&xME7bx(X%)pssmeA#|*d+E6MJN=*br=08V`_osl#n#_$?f$g-Uac><VbkW@
zf`J7Xj(3;F)k_@Uy!uO1i^(BS#6$0b7v1?Kl>jjcov{NkMx$T_)y+n96~|ej2_uxZ
zEG!Xpf{ok6e}naL`P)ABxp<#?2bmt@y?$-<HgLuVE5cqps@@UeG_;;jfR0DihT|T5
z$8Kn7^>=qunYQ-s4dc2RfGv9eGLY*|^z!}er~M!~`zgMCuerS#A8H<KYS6}wucSc^
zFZv0jvs<&~@}0LfYTvu=V1A)Ld*_EJ7W?TWJ6F2ad0@o3clP$L;DeS^<N_X+{8uD=
z0(yh;7=swD#MMWqV(>zO2p|8PO}s93H&2)klka?FLqCzPPsI1v?33O`_sQB*p8b*1
zowb?$m7A$~N~+qdu=-w6YU3?mde^hWBwo`Zxmy1HabIAL{JOu;{egwrrk{7Fnymx7
z-qHQYq&-f6aL@k#{g<!nyX5tJI{9F5{rDpbwa;&KP6yzQpWRscO2FUWKehd1YJF>^
zCoDdDW_`KdFPW=^qUgnc=Llw34?u-h%J7m-5VuGkv#Z~dJhjU=m2ZSTi*a=tDjD=O
zU~5uiT3RatG$qEeeuqn*_gdC{*#0B?gYo;7)*Ib3b+VMHy*GJn0hA`;5DNtHMfZo}
zhXBA%z#==E-}u}QeShb=k>1U}njh--gXPhY8=WHq73VbVX<hvI>7aV@oxMBx-1EN>
z^f{w*bm?7ZT31aTp|l5O8Ni2wzxwm)M79owR4oH<P8@m)WM;JDZ!*gt4Czl6o>cEh
z4lrwjHhZryLdi{5omLFhG7K=Xn30tM7KN2?^jFii2cDZ9r<C7a^$EyPKQ5Oyy5-9E
z=>o^s8|&dqPzbX<=AS?JWZ0x#Cq}^@^($p1Evu^hY5&=U+Q;APA1$^H9C>g5BYK^`
zX~9mmI+wWim0rK+PaduP{x$y2{g0m5yI_ZBzXT_%9zX7l>)znfNQtTnA0Dt#K2>w7
z=SSY+l`F>uR{FdTR(y2C0*$<7I2wHqU}mqI!kUwnlnh>(JP4!o1Nt{{q`JJ`*;R|-
z$d2m|#Ph1tkN4Mdm9GN^dZ4J=JQwWk)pA+EJlzo5PsT3wCyE2PTYjwwUw8DT4SzD7
z>cupF;r_1$sn%eZGqLHkjS_wG9YNpAy7r~(18>mu6VEMP_nl~W9p>rqCXnlLi8O2F
zQnLoDG~5Dl?i^U;em5H4bd#@!OKd^{MjHgt4wWqpl!vb)6@-%lq|@g(70v=bEoDJs
zmw=ARVs@quoQ8i_j+r~zA1SrdNxRe@u<f14-R!cz^N4%<{qF^|PI{ljq6@e9wfEe(
z{cGD1cT!Np;m-rd6>s{lqGhdr3p0)eo_<#n7VjCb)J?+<BtdY=$hl-=f-$>l@g|ZX
zM5SBn(d|8ckJ+0`MX6+&jWrDn36h74ETPq4*VqsD=G_{oBtaAW57b-dgzQXxvR0Gq
zaL;#nnU{8dX?t?QGiPfTH-g4OHuVl!L44D&J-IG)X4H{QXnN~azc&bbuK+IG-yID<
z+Sde<HCm<MzW*!LWB1ULn{DCk?invX*$qHjj60;?JC9rs;SxyHD0hXv4_L}xS{_0l
z@YU9`B%UYD<%)#lQ!wM3S)b7Fva6^OLN{7o8#q?-A0+lLi<cDj{nN5JBOs_-1LssP
zvU)71H#*JXGdKOM-`|tk=2Z1NuQReEH5RGbhuyy6M^D`5AS35={~rI4h1&VS58nH>
z<SB=Vu{;Es_8aZ;mzc>(?-S0tc$`4>U#5nV9lfyE+hk&N>Ik?38_SS9Zqn!HcB94>
zg90T9-!vPsOJ!~M0#(#Z{x0j`={krh3Gm1?SO#9arUf=vKNT#gpcsci->!PLn?+-L
zu{!Yaz-WD@1cdj9zIaZmFB?7We0a+C{NkS<yh^#gP82+j5b{b{mntRLjl1yZfb2Tf
z8eWKle!4|sGPK}zm<8w4-k$b6`Q;Xwmp5_lM<rZ!n1Z$y?~JSUub<(7KS&K#Oe5dK
zH+C|q$&%;W0E&?rB*zX8oN4LPzB4o(G>JSU(Z}|IS#$N^QiK;DbKI7z=Qw8DUW`V3
z!=)Z?@6}xw?jus}3am+7I9e1#(lny^-TX=Dv!OsAfh2*z){x0Sp<=BQyV*wVF6Tfo
zAy$AVyYC2tDOLWI|4uJHbleZBPLY{?T}ooFoe9R{H$2W=HW!1X-e#&AxWD_r6|d*M
zd-t1j-(5x!KPu$F(N|l2AMG#=x2^>kKmVpe46g+{zs6Vm`kSgk{L{hCZz4Uuh9JI?
z^w|0bq{r7{o%?>eCd5C&dYr#!%ady*aJO_~z<<=bOr3lq4!L(NUi!@Cu<O#^OUF+a
zaP|N~0Lwc6&G;}}rhx#!i6mhawygkG_;nR{Y2sDC_Ej<p*tlzdHLSwr-#YHzYnRB+
zAb;tPcNRLILnVLuOQ49$Uk&rM-(LIq4`1P(wHI%^_3eXcW0#q6>xBF7^R8p1NOZg7
zOh*{ql7P&oWJ8-qr`ZEBzjfv$3=K0v+j1^$gvu-xnV6FRuLMaYiy&H3udgsZ86|<~
zZXdFfR59>oy3?eA@n%y15oMT^DY%i>7H3m|5hl*${v`YA$_p6&Onx<&vz`H<%0O75
z76Xl=5jZI+uuP-|21T;t^kNa$Te7wrDrtqdM#o%j%xDNw_<uADFFk44?-{^_BQ$Q;
zw_KAz*5W|G-~doc5lo!uM(OaRQ8e7-agsM%KVVH_9%W)CV+g1rG1Gxc;WH6*8XH>S
zLgA6mvnY^)(%{Yp&>g%yuRRl(1avu)%}e|j;ZCZ+Ak3!`_$d~Zf~k)YQdQ8-iU*&&
zkeVTBX4o*t^e4WwE@Hf0<ZBq&6bnqiX;;w*GG-%XAWhsd-T|?Z=doX|ja<Vr8kQ6B
zN|A1IgG#{y8W1-akr;A&#~2V`=b&Ny%AGV8Pm88)Y5Q_V50oJt1&*l;bOc~iegNh;
zev09f-+?8?4U1AdC*dmXK^{q$N+JF=Pc@8fK};j0K|)S5;@v6l=BMO2O@$k08^s+)
zNM{mQBC){=W9UW-SjaXq{YAqV!{w_w#D2gPPc6{a218f~Q<+qh+6~n%)n=4>Vcu54
z3U~tGf$y)2GpVpN))fD6z{deE><%sOvEPzx-h$=N62}>n7#M5QQ$)2vlV#{a`knAV
z-57>+1gaLTc)sK7Nk$CnN@~oXwDj)u?!zTrGJFo5z;-wi_^zwI-&D+6KeyML4z?E&
zkD=T^J4Ro7OTqV3fY!V=SW4^F{S}c21g6L;0N=!gj)Zst01RlkxWsQ3Y_nWSBU$nN
z5rMp!0x^>L0!K|Z%!UiqOztCJa+yQ}3l{b2zo6u`zyf2C*bJ{);-rd4NKOGE4tF}(
z`6M0X3H+CEH`AG9RhhNo5})Nxky+}l>%A$ov7x3-9>6%0p~x|cEfYxI@QMZVSg4KF
zX9fhL0{rF~LL)W;G?E{gaNU|Z3J}f>*A!H7AD@+NF%*{`Rc2=KIk!S%{6f=_V;Aya
zng)m{y(!W+lh1$PFWzFz&<1@59l}vh8bH84kCe+TG-r&4@>i-6q?{Oy;;bf<Dp)1I
zR0!i#3Cb~GxlD)79i@Hp2Q!=>CDBc%^Zl2;W@LzC*E1<e3Z_J`9N8I#pfpenp!oAK
zzI0^qTM{<R1O^jaEO{|*n1P5%hP7apQ=3x;Fz#Z>E0AiT1S&Y-@5P8MF_dGzp(@d(
z(|_+8*<vb5W>ZOT8l#5r-E;uQ)0gfAO|wz5Fm8bP8BIC{)h%Rk02l<ZC`BozvGPl&
zd^DOb&PD)tPy4>Hm&Ixa=OdoAH<htYIZkPlRpPnR{)BJD72}>h`uk6QA$gJP>tCE>
zbOhFUrSrJg-+S>xSHAv-oNF2eEIGc^<?&y8H{eIagQKEIn}Y=Tn^Ba@L<Q(Ok3iUw
zd^oaJH~$-c@_xn}Z}NUv;?G@0M^v5miK=fYk&Z43IAL<PB`kX|w&fE5<Tg)>P9v$p
z_5^*Sz!rDpBijb$jesF)Y-gpeY_YTq*el=pE=GC=7=el7I|~8V)cw7d@pzKDd71&o
zdxef_{y%iR4Rl=RdEYrR8Z)rV*tmD@42KX1;l6Y4U<iI`K*EY+=V<Q5y+cp}t(l99
z5tawbXht)TlQ^*eNj^UN(PH2k1xz4YWVJay*(4@$NUfS}W0R|FbFwFmh6YleF0&?R
z?bdBiQxTQiY}-8+xo)cNN4vl04k%IX763tsxHEX~`#vB4=l^`%n5MLGmj@9mZ^M(-
zT<hSmg>$vyL(rUsfL~maACBe{Qv<wo+HF&Y7t=3Bwk&NXVu#Hwop*k;^W9E1F&feI
z*3!TKj3j$kxY>ci%6XXE=mW-!AsK8J`%~bXR*Dx!6DW}EEf+^0(=4mRKk|VH%9eMy
zyQEwv*RZ?azx)ZYYSC=%!6ozDL-ZAwuenJruMJFn&_US5C^#|Tc#NO76Y}$WF0XvP
zbFb4e%^2g%W1^Ar<4X$pD_?L~ki2-5$e}yn#YQi&Xl<W9&H*;8gILl>J5PaIKm<3)
z7yV~ZtABKA>_K#xoIrs$X^R8FR76L{S@Jp-Bz|l(KAJ4_|JmYqbHr#ARhPVryMp&=
zuf#1hd)k$s$ostW$3NTUbr&_>_B9r=qAs}nM8^5Z0mit$m@zJPlT=si9e03R5sSs)
z#7dVG*M8UK2XD#Sb$AHsgFgs9`hhzgdw=8zu`=66Aw;Zg954$k?1+2FlUK`a$2u6G
z=`{j}!Rc*nH4!VQkN;Q}itiZhX$MS}%8O-9Gwdj9kv9;y@ESkEJKs{Tv9|sjuXu76
z?>}OTy2yTJ4;1(h(GDg1aQ~lgwecSx{j+S(3b#MV?vM5Yb~4(vx2Ab5zbFeK%WvRK
zqHSIgT=3(6_!<5;`rySJhiu&Lha3+dD~a9z@BbxM^??t$Tnf(be;oVmPhzauBFOqt
zd2$ljn|NnbpHTUPDFZRMkn|*ZKqTD}sU|W-s!@!@uGJWgPv`|za?#vQl7yPPWSvLG
zwA)~i(XYo<DPc_?aV6E1j6L-`+<>5HfkvGU7F1Ro-3u?1UFL_Xz@4osu;s2siI_|7
z1QTWP_A8y_v|P;_Ot<lu{Yj|gZ$|m)BS${DPaVs=W~ye{TeMDkM_l*$&h*c9{{Gs`
z&vjlU6Ze}M1=}NLVW0N%tEP5Uy*73K1z+rZ`AgPQGe1;T^5j})>TByaI#UDZ+S(t{
z_%nS+TV2*J<v5l@?&n@K?=_tL%Kedd<K^<b%?`h$b8`JZ`I7x_e)L<c2Y<_d`X$qc
z+=ESZs9aF;f)76bZ(`Qq9fdMF7BWRPrHwLvUB!`}l$j_cw4=%;1AvL6QXVY*u^&DY
z{Y;(s@Pz_+)uRX)fb9SGXQRBQO6FDaJEuQkmCrZW#;Mob!MEMyE1mD%=nURi&r;6W
z8SU*i4$$nb<=eCRFQ~<~+b|B6-&Q9!4<@I6=<faS;tn%5_1|&MYxl36_~~nBZtTAC
zGi|wcy?x<7zP7RZzB50Z{<-y;f%YrwKXq~Hw#vQis@GU=dFprEWB(|5s$DebNM)o%
zPs{GVs+s5YFF3QhX;&NCONmxS4?N$k!S#5~X%c5TO*ULPq76Id9aFoelTfk)SDQ3y
zdCv~5mRt4~Hl3|-#-Cs7Q1x~0T0v1?qVf%8S%-I2Lya}^KglaQ$lJ9>izlUeKIv}6
zmY`sKbweFyYRPqV*uAcf=9Sf|<y&r8ruK1tv$r)ry}3ngBX9eipZ^pOVjXHj-i}b3
zpT4VU`hM*P>aM1rNb9qDde(3HVY5|hnr0J6kzvAu%)en!g<M-Se?i}8P6oMRy5`T-
z%Dz!++GoeRnT45dxK7zIAiGN;MK`;)q26K9hZCc#uJKy_*`RD2HJ2U%mK}Ps_GGLe
zAL^FUb^U@GQ-_p#Qa$CmHMz;w!f#v|p5N?-HykJy{LY_~8yM-YTwh`N+02rDd*W_N
zGi~;QC%Dzwm!=G2Vb6V*Ej}PSL<7QMvMfvbtg@YIDqVHzt-$3TSM4)5w&rQ&-E=nl
zqZDsY)5B^4W#3lI>Yh@0_kZ(tlv^&>n#|L4cyB-H#A4$ciY?#3lpRx8w8Pi)g_G)J
z!>*}TruL0)CZuJ%Lu2{O0M7LLRUqQ1S=3nQwr1ApSja7DvlElSM0#$n?gtI8Uazxp
zp2J4R^bEVK(OsWLtd7^sVyZe}oe2H8d|fuB_WFCljb7JSm|^Avgj4rMVH~hnKuT<v
z-M+5I1Mj3e#U`?zyd5xOI9l|I+EC+4z9kBUqslrsp?q$Ky}s;!%IhY#!kawP9TEBA
z+P(kgZ}E`AWU1}MS6BqK$G@PDnH+k`N{2aH56iZ$mtCIX==qz*C`Gj;jm%fOs2$R>
zhnJY1bAp}LCYhCBdtsw>rs0R19hk<Mg*E0C7P`}KsEbOm2+L-Z?Q7}+oPDj_3K1uR
z!PLkHyBu5DP^|WdA|-uIxyzi3mp`HE5V4m3DMsGTZ}z(3CR1PAuN02`KLbw2YO|K-
zwfKHh>oJ``uNEh(DjlfF!1rCxt1a4@Ov3k!O+%*;BAa3s%Tn~omRl#rikVq8IjghR
zi_J>DRbHSZln0M*Q4!+vOu@B|T3KZS4=K~kP4L$tbwv3uvaFU4_LfI)AtbVD6nAAu
zu@B=7ZotmGXq5xc_JSX^hRFBy{P~-n(_^GV;rs9Ip~}~c8<e$*b`3jPb>c|s1eQTJ
zX)4zP*Ru6JqA-sCrosHix3ouCah2~#2(LKUOO0t`q=~0aR&yvkYG6N6^BCea!>eF#
zv#32`^SHXECRjL&Ke(*CH<53HclVPe4;$jK-zy><3VkeLa1Og};CWL)+4MI3`8OQY
zHQC<WVyoL@-?-()FKTp>WX@|TBDWFU{(5{eRn^l0w0LE)UN<er8+_Zl<7|6z{T+6h
zwQ8h>jZCAMnVQv$gH?adOIp5ncKr%ZP%-9_X4b(<*WKxX@x-gFQrAf+yl+`l1^c1p
zyDkq$aw;AOA%^f=WRnjg$@Z$cZZRh<bbX_IX6?!X%e~P>kULHrYu7n;>688m<5c_|
zGWbqiJAk#bB_&-&D00<Fy|(Dr8dy5dDZTAgJsQb|oh6O0Dgv#kB~72r4bDERai!;r
zJkPt`aINDo8AOb9r*m$(Fu(S7)M`T=)NhN?umj{`3|W2A^1O1n>}JTA%L&RJi~g;s
zh8n%D@;gf1_U@_tpjS@z+CACnj@NOzAe={D{tT*h%8U<bXwrx#lS{O_OoMsWv}Y$y
zq^r6=XYz~ct(xngk<4<U{$?otJi_6~wYZwh_0*A+U7bJ|U-0M3mf14G>sRK-9f#x{
z=80HlomPK2@-f!SyX7!uWA0JwAnhplFJ<p>{3J&oS?W>b`hBI|QimJrQFY7H6TDw@
zvpY`(@;ZvR#<e_V;NJiBZ3a6#7nzu#A0Vanh~`|?@9J85ITbKL!wC%DFl^YoeUsdX
z7;0xKaz<&5DM?&k*A8nN+GA!qIBw7CbJdf6(j0VMjE6_Pe5cbDU2H#!-5VE)Miosf
ze;cEa$1ar184sC8qVbD`!uTqZ@2+wxqOOIb`J>h`wQPl6sm3^#X^wH4bmk`N&3pd)
zzx$T)ltaz-CG8fgF!ocxv6Q-|FQr~UVrEn6u)5R=nyoPJSa!mRF<e7Tww_*sS<eoh
z*Y#8t(>;4UJ?9r&awz`7-@c;HulKenMnfLa_|C7detmTnRm4nSiSrk%ld9PipU&4F
zWL?B0CVQ<!q%6xS<To&tC*8b(iLAWr&$}ohhT8Y|7CU!u<0}<!#CTF0<<MF50WDo*
z6E){}>M_llOwF2F-D;Y4tz7aLH|_Z^8t=+IwviBHm@Li^Vx>Q?>$4N~6fJsQqJ&TA
zvOUuao47Ej)%mqwUp-m?IE$A)sH?;?E*{piEWc*qM?I)sBm|8V_i4Lms^~()J<YvU
z7R4(DiYJOY&L*{I9S-n=KQX>*#GRpdHdWNHdZKLy^h`Bpp0KB;o(^BCd38U7gvpze
z)S{Ja$h?Y=(Nc9SUDw9UFPzuX?$p%OT$m2a6>Q%8Dw(~l`5WyXHzpf>QJqVO^FXkd
zF?JiO^roesV4D|P!6LHGPRqOFWz?!zJ`<s4r>%U#e=(1I26_MN8(jd%79zqxmUZ5=
z{WpFs&U4tV8caorgXo5?>OK9CmeKKaR%OxhEIX5IicNjfC>rnpNJmyjob<yQ#rRwV
zQUQF#25X1y+L}xZ<|H?v(q1Y2rjpNb1*F);AM#hD;j&_I4PWeHq%cWXf&#LEd>=)7
za|v?WNAu&in|jg@m93xs<*ni2`RQI|(~&p+(`P^PsI<QfiA&VlRZXWw&OD~oiy1c+
z6emNc>6gQ%*K%DF%!r>eC2hx;Z1FO8MI*PdDvjdfn4$^0dOZE~99Fnx)P7{oj{_UF
zhO^n>kgj`}`*HmZwSs{|xRnaLqsRx)3DaJqoQYS74O~V3k#BC5o8T+|uDgMJ^E31i
z=rn&5^n`Q+7FO<k{d2cG$7;9h+QUdn$}!`qqW-v6CC^!$)T?uIZl<Q3R%lrsfQzSn
z)*Wgpwe)$e#@eR?04<o0o8c8>Kq#bEA0EnPSq;f=@LA{F2JV_av4fF|yr`ydeGbK}
zVzOn&#gaq_8xvv{#E|4xS@utqWdfn<SktX6FkxZ6f=@tO*6;nE{U{k!D?VDJ@mfn?
z#jx4cl#QRCT~1elLrrX_yc`6TJhfz8)|?m*Zew(wrWI4xq|U+E&Ky4tJuJL^X0_ul
zY<8*D@z`u;C=kM4Bs9i}TvuPdXIUp3O%w*R#!GNDd;^HcHe*SS%C)qxaG8h0C}Snh
zG+5_mH|cEl#7nmS$$wXR+ar37AHXI!^l5+23D`Srl1+X(WE~bTwTS@6xGpk~Lnd&K
zrYH7T<fEt^(Na~jSS;E`y1b`?X*hc2ix|DFg&W<_V_wA?qL^PJEH7aoSh#mOk8I%A
zW!c;&rVqo1$!4oJA_r<7WBsPezi9>TN!KaW-hFTA4DhKtJ-pB%Ah=QZ#}CmY6Ini%
zydNX7kA>gPRl%q!-JLTn;OC-a2MxBP^b-SH$J+6ujC|bgOE&-ch;}t~NqgK}(gM>m
z(?-=aZLeJW5u4-#pawu6>{6`FScbx?S`}~v&TgnLPgti_zSeB|uHk{C`6JSeAhCY=
zS_al0ivH`Gx@KLo8m_~|<d6NC`I|jNg+l7JYcrqpreH_*v3C53reWvkDb7tkWZ0QG
z>_uR;j6Ka*sdL9U&p@zj2FH##i^<%l?WahT*Hv?xHfQ(=hp27q%s9=!zHBNb9&02N
zU_>tnp1SQOehI|4D;*B^B`Ev;ju-NYaR3)$ZCPe6z?9YA72lr3L=E_~_^jPKc;S|(
zL4M+9R;n7kK}Ym4Vy|j0O<47`lP2ci!HY>^4hK1W$|1~*WaVKZ%)ZdzYWSxyvzQKY
zEZel*kS!Um$xc(*#hMq^+3Itc<Y=qKHea_+x~G)uiP(r@dYBW0TZz$Tn-7T!9F4Yl
z$K4=$oUkg*Quwl+-1HaLkUd=30J8V}uYMx)ra>ZXcw6EyB0_fXF>~0NO6kt5J2y8L
z^Mgenv~DCN&U}*AtgOC&3E{?FqQcrgXS2u56O*&YC!e0HnuB4vRr`Z06j>%k-J-q5
z{}ET2c$|RPQMq5WYK%{fwu9X+B_sI&lc<7eJ|j`)1$E5T-^P8k0OQVk^V42uYkFbE
zVG8^7*M9d?K-W<-j=d%rJRs+uxu6pq(0gwuClmODW{dA$Z16>cp%}8;S5ZaC2>Imy
z*zaRzQLiX_wozeSHLvN1moYmX!m-`m?us=5On+RkPbv_105Cy!LN8+SKqS#Ni<Lac
z-d|HYYNvr!IjZs*0~dAXb&lTOE1`!s&pEzQ_{A6ZfRTvS?|`R<Sy6U>QPUsRGTiYA
zyXL<H2(-f{Rg{E%Gd<%}+Z5wnMVZfIgwRNV6H~PHS$I#s_M<zO94h*eE?k=k2YJDm
zDGK{qz7;fDwM7dG5nCc`q4-EpOCqLLh%W>0v?W1ZIrzqvz#E*uxs`<J>J+}R^a*x(
zi0N)Hz`DM_nzP2VjKdB)pI~T+XVb~-G5?#Im{Y7@AJH<VkSE;5J`>+xF9K2x`x8aB
zs%aBW@H|DIr@CR&pj>#!z&TV9Siu{LQ~<Fp`>Pf<*e%yAlX%8AJOS9FYLz`jrWITd
ze_=Tq?ysmRD5MfkfkEsS)+9tgn7bd`{@z;z2d3%ZGeFtj)iifQGbg89NGGhc<$+Oc
z=<QuWMiPX1O79xINIX()M4FG;7v|FGz^yF$BMX$U^f$Ln2M97zz?CNo<`GLBv7U47
zuv|9<>aplu2qHT?&T>~}?W@<V)ASkIp;xy<cWeHM7%s8R<`ES9>))eb4IjrtANWk)
z)mV&z*dPeA6J{lEii2V0yg0_7Ko6td-{R=nlt?ueTK_*OCoiUF!Pu!e?m6@jp4Jm(
z#2M!w?Kc5xET+s{Vl+Vnmdp$0g&;;?2zWl+<!dZ?L*-<b4*@;IXdp2i0Q*e1zQy=)
z_{^{U>Ze8wXNaTDIA&YC9gYs_?k+@G@q|=JB_OoQb$az;*~nfX9z%@G>}mVYYx}p6
zVDXNR0aV>!*`LF#3Km-UMq2`~NQOoJqHPw3I2Jj*FDraHcGSmBTdW!T+xIGLwUB&A
z6_<hg#xJPC47yhe7A;}QjO5nB+7@nfy<PfN;jdr7=ukEgPiy$Ko|e8%B>RHqk{;BP
zre|?NY+lSeZJd_Kfm^%-#1p)?MC`bv-A(D4yE@E*VLP+HE67GpMojNOw9%0iX2l&w
z%Z*?NH!?F}`M4K|IQ${k!`q>Sz(D{wrcSB+hRT1|%74`gAr^dA;)6m&SHOCu8-?fo
z^ODgq<0Ifaq7wqJBIx=+>NtUcVL$Eo@F9zS#&BJ%MTEl<?Di$RAm6fx_`}-pRaOtu
zs!mKY7_rjuYhG*N54;Lu!Rn3S0dh0)d04C+n{FM(E?_#8Kx`v$OG!Ukx%lyD$0c;M
zS8sEhN7ON*du#l*x13L+v<sbP38*T@Zg`jpPXFvr1~ROkED(CemM^gqEdZ-7rK<WQ
zVU53J1OA(JJS$tzYB~&zOqqDo3|~vBWnIn)S2~+3YM^n?4HtVB!s~^QTs+6*oLCYw
zr|Y<wT;S%zaxN%?!^;=~0e*;zteaazm~zp6LmM~L6alY9fQwgLoj1FI8HqxU$9Fy>
zPFjb>eppL$@K-gyio`9J_?Y^f7H>8^-;MB-N4+aPk&PbK@QK@88HX7h5=$AkLO(rA
zbRsV0WhBK1Q;ML7GiS{)+}%L|AxA9#ZFe~zy7jtEh)zf#Kt*DL#5i1cj%x}B12%dB
zM;^F2%GheFAp1>5X-+#1eQVPn{LX&~3Q4Xwcd-RH#%;uQL_2(5FJ_$C<C+~BI29b8
zk+k>Fmx0gcNC15iC9*G)@SZlbt=COMvvEV5q#kjP-?);XSefMrZo((V2H9r3Ids`=
zHDTdfC^Z*L0@8yEj<_5|2}Km*6_%mVpdUA%b0OZn?7|aZYt$TF=j}dd?mTb2X5a`(
z9G}N39MG8iv7CBAhf}qQ3F4*NViPqJ==2&S1W*tAH^Oo;Bm1~q{v6>S#&9=Ugts(1
z(ez<gYnPFyk9nLn8@`gDufFhB{-k?a`DJ1l3-RDyCFB)0Ffoo`=Wi=^{h3C=-{ZrM
z`qT4Ya(o^%KR;6fVRz2m`}?1L#{u!hw3IA575NWyMGKA#2%4K~5%}i)OgU&cw6lo~
z)FCq;5eQNgbJ^2!+xp#9>M_$|wCrpskiu<&<Ff-!m&pz=OHnJ2sG}W37BKH7c<>4W
z(h6PEB$vy2u_1W+0z}WF>LA!#aNbwg?#N|yE;j*$0;oN)O0N`t{NMfzoYD%qMSxzH
zqt~`4P%wB$dsg|{L(Nt>6T;*f$y?r1gqsK|<D*DLTOtAI%mk=o&T#Ndo)3p!-nDvL
zqJ(XQXE9+FWWB6=#@)0K33eC`4(t&DkJZFQHORR5>#A@>c_-cHlxksD+}1SCK7^l4
zB4jrTf4cO^)5a7l9V%+6I60YiQ9oQSl0qWR4*YZ(BkdF4qESxFIq5t}X{ullvit3L
zE`CJMISI4rS&^Od&wc~{Mg5u>y1hbcB*;UvNL!K_@+ZL6{VEGzM3!67O$Zwr%Lh9Q
zc{7?2>VYiMF)X$Fa<KSp(2x|uQ0<qQts_!Vkvz$*wR`{7nOojfu=F!njVhv<if4;f
zx~SorQ}*1PV>X>urtAt4M_7589<wOC0smpztGO@Ki?plGPNbhsJGdflaR&S>aS5YI
ze@Msz=wN&0>$XZfZ?SWjIXzQrfIMO_WMp6x7;$CBAS92f+y&(vK@J5}jqqq{5H!r*
z-Zml2x6>sIKztODOh*_L@1{4jW5uE#v)x%keg_bO#nyP+89-j&#`STuxD`Ig9mN5n
zvtdOwiN^i2mj&lCmx1kzLPJ5CY#`DA7MA}$Y8|znR1PEwt5(r2`$-fJrvg@5g=OVr
z4q{f+_-z+2{_I5FHo~&k(x<(J_0AS|jOpxt@IRkH|L};oH8vWQI#e~^*HU9pA8u9i
z(<g!Ge#RsF5SzJb0G>0u_#b&HYL8&~9xv95X?<#T0%-!}HCw|A1!r)8y$;dvP84Y+
zEQADeFviIvC5@A=aHJW;RZ;{FRzsv(LdE_KTvHHyg=6lHdkxCfiwLU2-N37OFcje?
zEue*Of9Yq*R{)#pS`0Mwu(rQ_9$I%f1-qE8<`Gzza6AyDK?5WUufgsVwa?YfN1{l4
za<({`N^6NG8u&WjrV&7tLBd01kbzYJ)Gy?3;7;iidD8^+yN-iw;09UgC_9}XbF`Wu
zQc<PL3it}yP#%Jc8lEA*>I3PonV;(0iV>{@1*z#N?Ve7Mm#Zp^x15Bew#X}hH<%$n
zx|b=Hj#%W#Ad?g;9?>$I9^}#_m=famLTuZR0g082jGI(Nl)#6;3Qnp8lZV>v;W9vy
zziTNF9B3s|<yJ2!`?7kf;gSr_l;^);XP_TK44Zh<Quc#C>VcuB+HI43k)~nVo=>fw
zr`di=)4ha5ADGt&?D8<RXr(>DqM521D;k*Jsp<>lr3djCnHv1S13>OuXnzcsDG|1N
zJ@3EWY&5{*)}Y~X^wHU`Bt))B)B>3VGh6xmZA%PE-mYz0UDpd|aCSIz;OG3>fAJZL
zd$DFP%+DjYK%rvl#Nn!LOlm<jEujfGj+eUf-sl~<Bw;bM6hiP&v83~oxjB{-!Vvx0
zduJNJw=OE-LBqVtTKR+*7x<RHuBNV&c@^@{X%hAc=#2aY_5qX}lf*{hp!=qUk~Q&w
zt-W10-0X&(Hr|5gPkr!*FGidO#TWd3?JW&P<HY2$9%$^xZ0I0jzN|MR_NgzatdYF=
zt0{{_co9}FJzGszZPOy?@p^UuZ!VTh{AZW){Ra_p{(=}_Ys{^iCP^}u%ooPDzqu=k
z!!850l^Sih2ZKdUvu0V{Jra?03BfzEvER8FKTR?VClJesybhCgJ&(%(3y{jMRS7~}
zlm)3J9|;-C8JHw-<3eMYb@PD!SP|;QL^egRB^tSW1@J)DSGX6kIlKFNgdl|N1>Rfg
zmzGsz3Nm_vO&E-_K@o>hh^XoYl6zaZuVeJY#}UOHy^;j4F>~G9ilWtL{||yI0qVnX
z7L1lZtYwc77Qt~&;pXNnvsodIa?8omrg73aMKVPnUW!s!yy$&hVyJ2{?Npcjszt1i
zt$q)cq`NHg7-T_4S8;Ga1lVxm>$+`Zu<NK=S)@jG`6H8XOC_+;pa*ptmw^CoP4C&<
z0u(!>H%kNm>;;PZ&>n;0h~c{eF-Q0V(T{6BF`1auLbnt&O{~Kp@F6k@I&q2so`(e>
zEv2rfQh<12PW?}y!mjV0eZ9LtRmTm8aufvf)$X)e5H$obHl6H083T6@Hk>cXSRuOO
zdP3!d9>R?r&HFVAG|eex!cDIy(M+uUe&hF{^#Ny+dD2p-n3jU>`2}5@lvLFeWhHjF
z*aG1WCLIs&aMcj#ki}O6=J@)&HcXhe&n!-I4pn0ggUqJY*6jt*-+DK>>2%uA*<x(b
zHa?n;Sg=+N+mK*Oh0S_Ebj9H2maW$mFsJU9pU_<+oCcIRJw{&?e*2*;vs&A2R>@AK
z;`{Fq%{L%!T&gmjPWw7+xXr$jab&Ro_WqYi1`eL$s&*GJOe{DCkR)>TC3>|(%g%zO
z#7M5U9dAowjy2g?ls5XPsA#=bQ))tR4G&n{aok648GLq77cYjXvHWnupZ{e~>Onf<
zL?|kF>Yon`ZF9&ZGt*J-I9)^{%n|)K{=tfoM0C-jd`YJcrvrG~<vVp~ar!JTX_+0A
z&V+a~2Q!%(j&kR{U}wuC>oboBs;uz@%Jm8AA|pzilRA<I$2=#%CqifnW9Flnkx7d@
z+F|!L5bc=SQSLIy<3;SKjfFU~v9-4w&a|;<dm&pkpM9PjAI?9U73y_KThg}0YZ;Fe
zt5UjS*-vYe3Cm78EmW!Ey=qLImw|}U)gs3dY#iU#sZv2Wlrb6lf?XL=xY(V)-gDR?
zQuZQ{m9<-Ij4i>)C3X$+?Z&e8_TsVvwALC}H{_O>LyR1dfdL~M${Izi3nccRauXHU
zdE*R8q#JFAM{_bNm?Ycx|N5t$DUnv4nW6YEEwcng4{%GR+-mB?37^Jt*9#hT%9F6k
zG?WVT5l<&f00MSZYa=fy`l<-;l0Jnc=)(L)_ls~lSbi47lQ=1hkiEy398?LAn|#6O
z=Rq_89@@o|5vbpl@V6+Kak0&K>M=L}THZ5#H+=cMX>U06HaSgPQ>U`_FMjLMs6wfI
zhtMYz2l%A#YFetjeY~0~TIOWUmztOs4#mhMA_D$YU9zAU8$wwKIytJVB)A?ii&PwF
znwEZ=s1RFy`O3W4<%`EbZ?f;?4sH~_4#0m)-A_jxMjQmZ*<gEaSC1H&5?E*)z?pal
z>nQbA2NT}ZHH)$i4DNgL3KTTGaFYk(@=V?A2miz802ohdqNfD+B)0YJF{EhB95Xcw
zpAA};t#s<#JGg+b%ZlV?G>*=d6tbmP>vN%PwV-tUv*Y#<l0H3bkksROPd{8+E{H?y
zM<NoKM1S&Ah>R3~p&>4Yn#vKW3%jUd<9L+|3N2;d3uEs1?Zv<ythufEm#;j5R(M-H
zBxMGr?|v}*t8W>Sw9HZ-1DB#_t`gpxg8@<0gkzVfVqm1E8(9G0j1>nC@j<bTq>!B{
zXBOa1AnOGkUzeINwt9w8YI=Yww!V1d3&kJ02+6XwnUC1<T9ZwQ+>6M!q`wJCs5stH
ztGY|RCum}T@Zpv}yfEGI!<h;q!fIaxs66GgF>P02#Q~iZ5z;5A9{^7fLFMegsQaGo
z1ul*(i7CQ+#tzWtfYH{W#180_)#LJ23n#Jg<ZgLiN&*&u-(jaGzvD(hiBgiP$F@+d
z3J=z7`avFr#0*9x01J)@cOk@MenTB5MRnVS2r>QSC6P2H0d{(u4q5N_|1kHCfQW3&
z0LS;VS5t?#O(2?<n$4xd22>6q4*V$y!g$+rFob+Mju@Symd$OOC~lQ{!OR@_*FAOb
zy`iAf-kMps=}E0iXYgwUd<+H~P+ul4XIuR;xoB1y1x~^attz#l;A09zr#9B_0(5ka
z>c$GXx7OL3VG8FoDThuMlI-5*=iU+HM^sIko-KPAi#A4BQA|-$l6Dd=37^HSO0pg$
zq!?^e+D`~nmh{_P#i_cUCjt@XH?O#7Nq|l7-NJKs#J^C>4K!pKs3oAA^ellijwavY
ze_}E5F)?xAFaTqi7D)l-U1O64<BJztXO3Pudt+;Ww0XsA<6pBM{H=dX306`cB2>z*
zn5MI1ZYzggS)J#Xc)AfZWoPlXGjS&-$=Q<Aqv}f=u5032Jf~F-7M<3a!**~JaL^r|
z*(-0m#v=n)WQAzi5#c)Bx0_ftStdaUfi$Sd??X9E!)StgBAX-5rLp5)$mh!>5<+G2
zcI2(*J*Q1`;@5ugX@-E3M5CchV}CzSWo1<#bgM6<=cuV<p;0N>U=j?+0q~Tfbo9ki
zE&F?^%#_d?uEDkn8EMzPVR3xZ9ne>_v+csKueOoO*h)iLU*1rHPZ0#3pdz@wzuHki
z9;0hq<T`^3;C}4d>-HJ76{Wt(zjN!;AAE<<C3#UBr1S+A3R`+aYFksfh5?z9T~K}|
zY@iBKnM+5T061)Kl>lTr*Go+<rJ%PcbeNs1a<Bq4hURx*);rjQa2+8iAZT*Jg9O4c
z^Po%4RFE8Co@F9b;<2NT6_O$%6TY`s>Kcp%lKA0fgyp~aKYsctXB!@cs68IrC);Hl
z(1*8=Yf}#u(_v_f%f;FbLV^<3Md?&C4g%o;Q7m<zW@Tn4N>#Jca9*OWwp9apz22Q!
z*c@EA+27G__Diel8x%IchmQ5rPxb{Xl2#8pD=VhJSHv|o3Ldhrb7{WjotBF^{@QBm
z%*G~bo<^x1MnevK=k=du=)r5oD6|@pha;?N{BYfrieT*4tXs*os1blB!9B3IJ}9J5
z9+FI@7rdvZFk2KFRiPuo2BFpB<*nd)1rL-(&M54fUb|LEd|hF?;7KsH*j&|cl>{AL
zNfKpjve*N*y_B#>K~At#mpVl|RF2mn@jXl}%Cv(V3~)wI{ncmiuvwtkEw)Tp)JMQU
z4^wP3W&&}Dm)P`lwQeB~<x1Yh+Ik(H<VNMc#Q0o^&HcQVxu?NlYW8d~Jw@$HD=0Vp
zp|c9ZAjBhUr!JC=42Yi1mC#94X{T|`TIN$!&IRcr7J@?&ZwM|Z{DZ6=_wB!FxomdA
z&v?@_2EZF~0()Ni;0uRWwyCwi4I`adh$IKd?BvKLXh7=*_9suVr-^FBsAiQ`1<6f1
z+e%V>24#Z!<ZQL&1(qEyzWZLngF)|X%3?u2=MvqY1C33n+y%fX^(=uqqklF}0WOQg
zr(qr(;Za5bZ5KI$1h@x7Ms@aSLhXFB*_z+z5q!<e&&X5TSC)tNyk!iTD7_Y=!W|%1
z%^lp<s=3M86oXo!UL=}tI89Mxhm!Is>@zjx`ZKKc^OOxA!KV>Pb1`+!CZ^~5mK)p<
z(jO`9M2*oO6sVCB7rU|wwaG%Dccioo^P6uH+9T0yE(BX*)J+sdCzO?2jo>jcYw#tY
zWzy*;ozlSiz50(U-l?LoQYVflAT^}qkkrw3iW+ea`FL}XVo%4jTCScXOXDDO0xXs^
zWJpVK7(9|=)}%yN!eMfCo9)Zpu!GKRveq8F`Sk(@cr_7)#}Z_K9r8+mB_}<YNyJ1D
z&^sxU%2Vt5T_ve>7z!xNd>y)(#}0(J-o4PS1T^m~e0s!q6`91DiBN)Xr3CH-MhzOC
zZ0KCI?(2K3mR?TaGLtjy^ISZ*L>)A1g)uy)U8SrzEvm=<wjB1f_M=O-Af1{1{z`Ib
zXEj&@!icG`Mib-Lp)l2R4K}wGm7c-V`0NJjmIxKiYar?5e&rK@CUyJp1bH7Z=ZVlg
z&)J&B9RSbP@BPNe^Hey2CfP#KLW+zY){I;Fwoc9Plolv>K3}i7O^k;C6jYYu86}4n
z$90tI+T@N_Jq}ZECqmL)kg(<9g$+2CX@7bFDcnoO^Jw9lJY`T|0@AFr!U9VgmmGT&
z%h&{~MyVavPvIFK)C0mTzpBim$Q1E4u*0Vq!HJRoK>88t_WQ200+PYuN`^_xYFcJl
zH{%c}Q(8J)6o~DZLN4qUE=cJmRl|2REzKWc2kjU1>cpTnTb%<2+7!$7I$an{UPEXN
zPCLp7mEXkZf)OoAagg(BO7b`I(JImvQ9}e?SmO;v>Vt(JLtL(rQq4D&$EA`~Ncy1o
zEd(6h?)=){A+H8jfOIzu7E?EK+6%f~J#MDw98!=q3r&HAEE!G5r)(q(WHyG85v;j$
zJyqOil3&v7JyigJzo)r14P)j31u-2Wj(HTZ-EWiVgLp}cLQ;_YvJ_^+0BVabtYAf=
zQf*F!2S*%E9K0a*9KE${Lob)lzHSfAU_X801Ex}Se*D{?%A6q7)*&qo>V**VDz<?<
z*(?#O9t2L&#vN90wNfL{6Y>LtlO^~Dj6AH_KPXbWLG4^nW#xG7ra$t<FUp7liO&f5
zrq{60Z6LZRq${}BURLkAiIXm3%?XIx#*Xwed$64=i1=Z>!F5;~JUlEpcm%>-YE3~z
zT>vlDeuzrv?@{`fu_!JQE@nR^8TvtDK1%rDJhjO%FOdS$1v(%J2$4*CHF^v~k0z5G
zGZF3Tgb|YGsH2;!Z5u8%yBF{^yjM5^0=N}Ie%A#US&ACIetxWOIuYY3E=9>7=9;Kw
zh5gP?00u~}TFowwb8C2Sr_(_Ze`zQ-MBav!7(vpjT3Yhd`WIL!wSH!LHt?&@+L<Wu
zFa?uR4ob-jS7S=Ve~MT?hBa9t6b}eh+`y?@KsoE(t{zB!$S1vpGnC-84XBX(Vn6eQ
zfE=OpnjHsKQ=-i-3;5{!LNSyH%fv0t>`;hNr{pHM3^qrmyS!(T&~)J2H};N11x`G|
zXIMNq#70FO(2v7)2`z`+M8R;gbjxNog@=*012NT)YOj*gBVnT9IjdE_OuJRfn?GuU
z<l3ksoQZG&=iIO1TQ(GBIID>gsa#1fHnG^rK7-NELyjh5c_^5MI;xa)%X2M?ylvQs
zV0ufo8AWWj3y&Z8WacMSyI}BOG5g!LPj*f}kkT|vc2R3OzV7ZRNxgTBB9j=*3x@$T
z;ewuyrIz}*$*SY;VSCH1Gvi`6AdYTqdBb~&)z@5FhlQ+1G!f3AaSC3jiF;weBx5Pk
z5eFlseNhQ~VGz7wzh+?trBkBi1~WqVZt}2oaMJsK@l`57hIqnJx`-xm-tcX@endZr
z15XDNlbRoRwodw}1!F@zDvq0WP7z;CGuw63Di&>biUbx}Z2#<06GE;_fdpGC!hnvD
zucJgi5(ebB(Ku}#&C@eK2s@e-w~`bXioi&jRKYB{uUXAJTMJgTx(k~TH`GI1-v2lM
zwJ1J2o4G^39YP?^WdC;VJjLU{2Q597(c(bCK~Mpu4h%^=ZP4Qx!8jqcK+Z+&1kngF
zf6i+WKoCUw^M~y-07p_xj(lJ1ehdB;2fm8fM#}H*aOC;l!UP}@VxE=Y+rB%5zEh(F
zYX=jtnTWW@U0RNPW{2AGj<_A{_r250D_4yurw=cvwJ!;ZNZm#E*yqRkAe0GG8G@Z=
zr6Dy2*$mSo-_iy(VL;I~J^ccbWY4B19k><SHEQp6gH?orbDZwsS0WcE736B=wxWze
zN-3yk4!mcj+`=?XZq|_!Y!PIDYOL_6!m3^eCAlxE&suU{0AMMw^cQZl{bZ-z?)>6^
zzlZMFi^8c$nJ*k$dMTxfI=vY{HLXhBn6G=aGAL94I!zy?ZI(IgIA;5fN%bDSQfjr*
zb0_IhY1I9*hfVzTLMH-sLN3!N_;bX{IApdFo0|vWlc)*UYN()6Bp2eZMbu-^SH#$s
zFU2f<+q*?F9ZZYXt=#*?KOWVLj!C*dp1w+|8MJi#5=dW|ctJlJKBQT3Z8yqdSk4I}
z22hn6T4I3gm^q9ErWOM+s?I@mHd^6ja2>Ifs2#YD5@swhPFQmKA{J7mva&-K6vvl0
zLKm;5yAq~|Ws`KeSY$f^P91YA<yO)T7QI++3)H~wb~-D;|9Vk7MRt6MI11MzX4aI#
zt7S^_C-EG1pi$XDcAwN1=qu|zYVgbz><QEg2%8qB*m1rMx^v}LhUz&F4ggHIFjKjK
zuio21j62-|ygclhq?*}2TB@XUVnWqf4A8j=5{TkJoF3t90mQ$0fm{1BGO?VOs48E#
z-GxrC6wdU#D7gOG-}q~^n=p!D8z=H8cv#GArmAa}n5}BMNS~W!V&4)a$(cE$juVwP
zr?<^*C27@3TutD-BxlhIF8Azd-oA2!OuC?aX&fD(%maZn)idrX09-@@0Gy@l2B(Cf
zP?%xU7T~G7Z+i*g425{BS7wHj+<coSr429~;B@3JsNfYEHaqCt*5lX+W0IAo$!cRW
zC9ao{(y*#tcGS`0!vGH>b6y{=nk1$WgdC3z+5_4gSx}MKg6}usfY{hP9&R)-2$4Oi
zuvSh4lR?VLE=!F~R3M2%Bim03$2z<k1**SgHQ7)H*)=)T&5keSzHL0l|NRpxI<887
z=23DZdN#ZNynfIj3rS%q2qK*cNs$rk*qC1?F_;K>Ra`||YcFAXEG{}>ge?JfEpK=T
zZ<Jk#V!Z);1=YQytLQm?BC-tBV7*4LFGhhnJ<JnuDmJR92uhfP2|EF6b=$jLPSjZ^
zMfW#)@P+F=M!>GMZ~Y066``?qg|L5^LUoBW34?wiMfR2lLLb)#F})1-Q^Yr;RgcOR
zY&IeiH?yQl<EEY9LEQDG^X^uH#5OL14#gg-&{n^`+8)I{M1+;3HyX-1B~2m7NJx3x
zATC0f6%KziVMkZxDVA!SBILjv8etyuMh1lX&Ap;r?audq`;$DRBKZy^8FDK5m`qVK
zDV&(4o7U5s&AK2hEFdC<8n(?gos9c6cDAP#p#-!OAhHT5#U&40CfZ-!gj&GX;?t(5
zzf~Cgqe7wpj!fX%yn<H|`)T1A&~4#Y@n>{gtSan9A-{^xi#h|pENLb$1i`k>T;Cd=
zq1K~EtTC{%ye~dN)mM~2A`MW)+>U55+*T1_3-d5J1$=Ss%pR*w49)wOnmk-6E+J{0
zWK&iW20|0iz)fD2{1{PxjSlK@`-z24H_6Uy_9$w*QRs{^^iBjps+Zs?Ap0cbC<7jZ
z=)(F_Vj~+(`4Fa#46nqm_Oe=C=2YOcJuF?*CtD|1ZIX}&Ky<!c9LS!!YJkT3DN`b$
zVRmvmSJX3_ORQ|B9fC**J3EsUI*i{liX}tckenq+n$kQvLFk>HnnHi_%~rVcUSczX
zlr&mKwztz^)(q0FunSToXv3<o;Wj8$z@#M7kzxfxqxK&8IR<fbDsabeQIscu4%d0G
zHFc)M=#Yd1KmI45nn6URT+>96u42WCM^a3MELwEwq&0*CXA$IMP-NZ|ZdfAkHgKoi
z1IJOGLax1-PR}j+ebZ|JdU`MbeSkKAJHt)DyRszrvT_EK_HGB4*oVFo7A9jN3hI#e
zLh~f{u))0qjncx+9<`-gBq7^{AODLz++tLg1bA4|#O@B?!NE<gR*Pdrb1)wBr31~a
zD7<ioCv6+aXM`SRV}+nIogiu(l^w&NJ?-LO-LvDBX}ZKvK(K>&igEp0c&yw6X;Dy5
zBp@f<lhWS;qLe=#do0^bcIKj5*^mz0{Hk(s*@2=EnfkU$Ggj$vNr%&A;qQF;QyEX{
zVMmyeKoSop2Pmj(U#LzHVCJYCgLaceE!r3iJpD-ru1iX$855PoA=?czLx0*V9;5n_
z0S#RDN6vhxhQpAB*@DifCN<7!6In_lg5^+LOfeThf8NdrTNnvOfz?6`6>@>(li=PG
z&anm=L=(@k2MWZS82~hA*KY6MJ4EG5n`NfAHHTR4s&)szRn&8Fvq-_Hr`MF#tf<&v
zr|vL3D@zz<7^$`svGxgTvTCM7zk;+`n^#;>KJeL=mlcX4|D{!#98id{&Z9Wlv4;OP
z>Q!58$ruGt0UMk|+9K79$yy7xO9%>Zv$&RWsdAloZrEG6v1Ra-z_oj0z95KBe7Mb0
zhuS?Ydq_KGN@^WWB>?CWqU9}5tU-eJe#XHfuAJ|?Y|<l4tjJ2BL6};7iAEzkY+k;E
zVlT{y9A_oa_|j^AAlkZ7q#_FRfh19tn7{|9ZSi${h`EEhFC2D>G)$XDBBYsIk4^uJ
z)$Sr^GoCo+_xE1|35%<vektR`sU0*Ok&4WOj`5mEr>jmYR3!p^E9R}x{w(;2WGWIw
zX=&z~j>nTU0zp!heXBJ5T4&3Rs4P4lmSQ^l288!08wV;wyl#utVvCz(l_WjEX-C0P
z<ef3h2{@I=@%+fWmzPo^lAONx#F-A*J)G{+70_9^_vXo4-W`WUi!^8HxDX;aen9(N
zFGb0GYF0BTTFTjF(n^`~9*<{-zG(39&|#8%Q41xJ$2K=fDZ4fssbM(AU4mLR?vO&f
z*)A>25P67SSr4Sl`x&gW-Pc3Dk3pK)z%iU$zK-XPR8i<GLGm~mG1b=LWo`qug7YIL
zCCoMw9kj7S%QRJJh2MMR9j9lEwy_;`*kmjTQgU0d@m0;lhdY`BZBO@a%yDqtjG>6w
zQAenPgJ4m~NnoDCF<-j8SZp6;z*hUipbUYU*@8+?=Pf`JJ7RmrXUTI1u22*>6%-Mt
zh_;T3&69~t6V$dKAd8M;c9XcpwN12unLs1oBOImSx6Uq0o|YZoXF>x_fQZ%PRJ_;<
ztrFP-M$vWR(vuV0PaN7_0uuq9Y~7{!zX|}Q>9ovf5)3o>g=tcw?GDIb5Q`BJZu!K@
zYEaJgD;z`gi+yEJv0Z)NC*<Y?LTw!cj<}~;EDiKY&_;k^-V{EWwLYHuWWUi(;DbRt
z@i6Jp%!Gy~cBh<bjxKOj(%l3a!nj-q`56Mh3vQwkR@y9bMY56vb`z6Rb4>?K;?5T?
z3ph%8eW;OzwK|7eGm&SZpln=sixATfJfUQxRVO1-7T0d&ZsVpA0@Iq3zB%9BV}W0$
z+hSZwktmOU4?_z(i2kMH2I~b~xi|(6x9Wm1%}Nu87aKiKof+Oc4t|5L)v1U)qFW~{
z$v1%TT|fA<JAez|@Gc}m?ap10x=V%$a842;MfQR`5;X~ApZo2_m?3^U{sXq9PYOtH
zmcqcDn#hllPK73G1v~x#sa@J#lPKS>{=H|M49`5%hn%7Yn9sDgqXv~9q$mml@1*b~
z3?2vm+6iKgcbzsqS{oFmSx;Z3@NHY+-C;BZVK{STaHAh|?py|5OydQ;;eir%j-hLy
z9f_O+9zwQ58Ttg~4IAKM-Uz`&dd0>SN~EFL;Bgu-UQ<&6&HHp!%<QGpwQnuj@BhQj
zMUBfPrl4gS{AS-at2%2{c6>5uSe9LD)FmxwFf1H0gTn6~p;R`FJRAduP+fH5ge@^r
z1CYazjH4Kd4l(HFu2tq)xU$oX$WZ8T1TCjvSMnecl#_g^2u4!O15QsBzKa}>LI+?9
z)pg51fr(obLT7rfY;si8{{Ht`&p6WA-Zo9b&<HYP89sNXxLtIh*sK$p)=HK<eNW6;
zX)h6Hqn=W=vj48s$RQ#7?-V6?ogzm@9Eg3x3zOXwY7E3o(lY{aQJXtOH^fAdVIwHH
zK;hsKYs?k<U}Bv`4T(x(g#8KJ<ro0zn$i>bhFkEzsz9nuAm3_-t7uk}B-OXIpCKZ}
zU_eV9&;~W)=-WDZeBh46noht8k$n;$IG6<U(d)<P7eP@V(BpUYR9cUtt}bh);I(%B
zy@Xf{>{VovvjgX(Oh}ogiC9N;5HY`kX`@t)xzEzX67iTK(Nvrs1o26or$8qMV;t;s
z;LO6c9?%Jw{hPleQvs-IJ1=Hn7}qwU9Xziy&gJ+CtbnPd%X(B8EsV+v=xGHU(zh2_
z<YQ(pl|keQ3QKck{Cd*?<Ri(up-D6u0}DsZPn6rk4(G11oGBPHgsHYjktO1c3W_bh
zs76;wf?Ncmj^6gJ=UFEuw`9HG%Q0}=SG)bpU&bg7Lqd^DZGTmJUZ_DSkWP_ctPr0j
z9XsIziZDiR8H0Fh>EIMzTbv}U{A^AyVgDS;M2y;>UBb3?KEy<#cFe=WWtasSapf+$
zUtYEtw^VlBGV;q2M`&|Zfj49D_JfI27X&w<>Sc1EJ!Tw;Ar?IU`0wpurej;;Hv^2r
z*bzrcxuFCxxDO3hT|6f}b!H5a(WfwN>;Zki4tOGwm6mZ*{=^<6FX-Oc>k)d~S2vJb
zK@!puG$8^9NgajWjGn}>qRP}TM<gGN4<eg5qLc;jhry8UJn9-7Jaof8JJWWYEw~1O
zK!5WOVsvt3v!n975Tbk3W+a8qQwyo{pd%7Xd>ELr7^okQmNizO=~Luz?oqE<)F^)l
zPx?tY&H2MHR1m|{!x3DgkUO%gveJIL8WLGJY86J^Fi${eNAU$1NYq9^d_iigT+FYD
z#9Uxg!@QVlcOF;F11W@jXTfW~E7*Z&g7>sEkXT}mp?JmQ!6*#u7?f6VNM{T;Af84@
zN}Jl3BwGs3h`<k_H_k&l1_6Hp7luPXa&b+=BiIHhiG^DcF#o01bNX5$>Q;Y?2o7}I
zT()G3fp0=;v!o=^2i}>;Td<v}RNh^-nk0d}X2ml*n?$c&@h|Q7|IR;Mxy1AtG|fcS
z_S61%O$RyRnB7#WIyFe|ZOb6iB4Tph_DG*o4F-UaJ{9WSh^xkm8tf%#{-kM3JV7jd
z=7tZaD@7b22_O&poS-mpP*=Fzsby=iVX+Gmc|Ze-A(PdDG7=V3Nfq$S0;5@FgG$hh
zt`9G4Zgx0{LBjHX^-D3GK1}nxR=P`RzvLS&`&rGN0!1WHb3$0^c->?v3H65Xz6y8%
z@)HKOdnn=rrbB05L>VPReny^{W)=#17S8OZqhBeUBY_AeCLX<@%p=yTd3cq&{4u4H
zS5}HuMt*_C_6Aa8=3lfr2^?RAqAH|!Yi59&c0B9)y}xNb<6sj;3Fz3dhv`0M%|&rs
z`%DHeOeGoK0z*!55-zUeyb19gwN2MKkBeGrDdi%^lc*(7Eh2lNT3_zE?!qR5EK7!A
z6RIL6$agHl!Ga~EG%4{MIe*J@TGUU96pI`Sm>7qopp{eQ$$pVbr+|qzJkQsIm#-|$
zcpa86Mq;3FwDS%=PQ*8At!o46fy24&2`E)smxTPq&xK_X(tHdT!yQu(&I1>mb_9hP
zU^Pa(L|tq(6;^%VE$O-*NeWRyNq$Ay12rC1mgXS<BNqO)d(FC_o~59V140K`xHt{*
z&xykG0y+vP;B{+8k@RSiwtIJLFXArx*BM;9_wZkT%a}o@ATwnaK?NB-ysfaq`w&sR
z`a%iXsiH`XVwYC#ICrIp6Ay#$Kt4#Ma%B`1N>$Trsu<4U5d|t_7gq6f!tGMYA;HJ^
zJ*lz4>GFj%^xLD4HLhD<VfV$})D~N07m*lDnN(@YHRG!dwF0s1@<)HWp(snKSgj|%
zm}ICDwJc2DeE;A5l{BKue1Z|uyVz)<4y6*u{=xAj5;ow^ird6Lw~Re8%8|v0m{f=e
zz(}3voA?vzhwhkH^<wIT%_u+EPS*riwz4xs*=?tbI`ty0RNo{Vl648^N(w}zna}+A
zP6Oqm|5kp9ko4jLsV9^5LyqQnMFZc$SQqsiHM$T>d%9A>FdQ92=dHqzk9@*A=}g5(
zDJaWo!gQqsX|THx%agO(WDpH=v`m|4&cs%F^j0%C(Tsmr69q9S9$3=rMaaD1czVvp
zXWAKW;V2*)uz{))N8!i*a<#E4yU$vz!{{qtJB{1kP6ONn6Ha0To%99UkuOPbT>_KJ
z9IP?bEckMNBxB4?e{U(=<o?><{k>1mfaKdIY#hqEf1AI~<C-bBIYQ@<8!T1RUSwZe
znLRP2GRqUHrB;iJCFO%sr>>@|`mv%DP~%08x`hu#J9gUq7BV>`P_c&X&bh=lSJ}!9
zC2cuW8@l*%pYa#;kU?A6Npa<ZI##$uvVpYajAM!b+ouS-Jv+=p$+o+cm2XL7orB`N
z|9FFH0P4~ol^`|U&yT<m=`sl*n5bysTy@H6?Wr`VX5i72nHLS|^}7ZB+lCfp6d}^0
zlWZV4>CWYem>NzC28roHJ*G6U;Z#btJNW@N@fdEfq4J79%htQfrDRxmXMyMxSM+5)
z+H7SZD;!Whd0HtS@6P?bK@<#Fn1;<B99UmI`ZFWO6gGyh^AuK~x1c??o2Hapg+MDk
zNt9Lhp-}_Zal93WL2n3qR(uZ@-8AEJgSVkMNVAy~-%D+!Uu(QONLemfYZ6}BaE+zs
zBl0V8NR@W5fBo*gpWrWXKuiW9;DYx=SwXTmO?>7GV6Tvu<TX!XQ8Vy2EwWbGvhFQR
z_qtTm4D<Yi&M#itOZ7dGK%B_ic%Jo`b#th0nnn=@Y{`cSq~O#}$dpFE>F86Yj1tRW
zCxsd%A+V$q`RX=L#>p^m#6GLK6nXk|YS1zOsdQ^?XLW~K9nc3r$?jv7i0t?)OD5`2
zvLj2U!3S{^$0SkAu3%x`m%(AT-G=+5Vl)O@c)9D==sla+;+dny0v!pRue|cJL&&`B
zyJ@!ZsgQW*fgf!dC*maLw5MG^iM267!lla^lgK!#6xUIId!7J{n@LOp$LHp9#2Vb>
znfw)Fc;SXX&3+LujRR6%jl_&5V56ULJrk#4V<R&Nx@<b?NvH_!N<d6v<WG@>^*s2S
zri?p4g|`fRGzE{}D*W9)k7W!CM|2fsLj(?hvFVK|>SNl8Nm|<H<{Ew|v+@D}x+L~_
zz~M949yAp4yozO!W>6f`3q}i{mtj+C-+=Aj3U7AMH~^e<9JOP3304Rx=6=@lmsPN6
z+K9MqunS44Fvs&N$Rt6qEcht1Jf4Kxg$oNVvrsS(l~HX!D_i_Z;hTT(nUSdBn?t{Z
zkc)DP3?I=SFKSajGddzor%5c@3Y5fiATyr3Ni>Y@feky46_>FokV(c%q~J+i*}?B$
zu5gmxmZ&CxaNwM9VKEj>110nYR1jkc6Ec@eHW;jn4OzwGue!(tcSH%=1sbg-6+3*U
zAhZ3t!+STGbhY+Y;a`2Z^crsQA|426S`{|I)Zo9&9BX3gT==X{83z@&Wg!XagAhxv
zb6>zL5U(R(k|M=fEaIdt84$cU<7hU0P)kVZ$2|31l{E^Zn0G*2PLv|H`$+zzYkxJ5
z4e_92Fx!309fh`X7SfWzfxPWaU;}-?_x$f)DMRqiASKLv=+ZQCZ~OlprQ|^n3xuu6
zvMhg}d91jdb96w|)YFE?dX!_=R7`jt7N4<jpRdB2isz9Ui32(fcT5`~`58P*N2}2J
z4SOj3ms{T6_LfJ}F1z%8p+GpMMsYoPqVtHp;hQDypI$mi#kytLd<PPT0G$%44fQ-;
z)?O7itGxGtAUG2*8?5>snR7b)rD6=P_D=`Ew`{q|+KmjV2|0S6Vg^lIf2)ES#guXv
zkh5=lNEF~5A4EX^4xV2(XtSLaIR1j~(<0z!g3VU&FNM>)*`;up-!SkB6@ce3DHlm#
zfN;rmgQrf(C|n0rA$@+>K|(4(3w(AWFC8Z^Ps{3U?^=F2GCJOT!6x0=onaubbP{x-
zS$^CefEE$xHA3hB?}WMuZ~+A#(8*;#WM`@;A^BX}OPcJ8|F(C>`H(4&CLvr!F&@U1
zUX>}BBNDz(YE$Jo;smeGE7$GXI`n`9oF0!Q_+exnH^jxjKZ^HPJM1n0D?R0TNtuco
z15IVG1jGpZz5m6n_p1Z1DGpF-G8+x*O2YD$pwJe-*ROXPAb9zHF3#{YDf}S_g^I|;
zLFNtZU|h2?CbQwB#3`Pg<i<epyQorpnwTjxLO>j!DQ-)nAfzY*9@4EnrsLQCtZn*a
zufk0s<fC-C0L%U&nH6<i2_OTWu}EagC5Kx^cB8n7o8s4rHM)OG>;leBM!_BJOXQR4
zD~$<d`r)E~X3b*XZc48y{1}n)z|T`E>o6PvB1n5*L|<I0$=GKqegJ8VF81{dGxcae
zh{|l3CmqED+*ci-tZ`0qYXVe{6~&QJ=L_K(BA*^z0Q#Bft${B3iGgBBI5Iabj!aHR
z?(4qBi0)jo?&b5(HCnYr+@~p7RWV^wetQ4TcnRDWm&y@GgS4LFz?+dzKKmQdP2Fr$
zqE&)6`jbDBHa(E0!{}X5(dRY$1??f5dJ4vYn4S%ymr6BukLJlI`IM8wAY;Iya9xBi
z>MA3vovzMeyP5zOtMZL^F}cV^uR?c=OhS|@+WrE?=d#vA>X;O`M8}kG5|vPfAto{c
zMIYXaU^(dvk4}|aSNSp5XEuPShSy~%fY)OngJ{$@=RZlACnINgNUCN~Q`^>-^=FGG
zP87|`9IPZ}DR4Pf^pyrFiPa*RTLRNX$HO<eaT&uTG!#M?<ov4F+GDk9FK@XFJExbh
zD?R=q<3~S?W=Ki&ZzmEx#<b)i7QkN+?kEu(_c2A1$l)+|FPaw_z;Oj<4C!=cgUy07
zmFcV0UQK7SKRovt$D=8~r|DF_>tu<U-a+YadR9MSYazymu@o&AjTO@@Q^a;hMTt2V
zUXR-wVYU^vL543)iBp^-a;5&r3wE3<wVRt1BYR!?M+UlU55#95DpFtQ8l2Iw2H8Zg
zU!L?2X*vh0>!(g>IXWiU15v1PUUSlIO7p|((v>v7My(TbY9r(K!N2|2Bnlv>k)o0y
zq>{dz3MLG)v307M7)nVQi!bb#x5+*Ak4mJi4(^h_`INgtjkE-9qzEaKimax+Fdm^;
zY#ufY?{I5Pq^>V>vhjp$;!O~(r$q2hx;_bLf*iquY~jZZo+==7awiOCB90hyZG<y?
zgUPDv!pCQ4m?GMpUb}bs<v}1855a=<g~jS&8DM_3eZ|K(sfo$iy6@m4pnn<8>U*!<
zKcwhzs7KzNgL;Whg+o-6GEhP0pq>o<rsQrz>%B8BmURp4GAte5ebaD1l9qI-Q1ACY
zDHtQ)!Ty!yi=f0KE|OsMLv1>yBIVl=Bfe`%i0>%1^MWU~_O`(s?LqEqpnYudXK1s5
z(8fFQBxZEu^IEQ_XX4PVlQo8aHCu^RCIJkjZ0EjNhz4M$q<S)HQ$~>pttC)OF*CEp
zvC2ISEvyO~GrhHU6Cd90MCJ7#J0#X7g2bowl+aoUA2<mvi*Dy5^WAS05Zkb8zq!28
zP{a`EpVdubxjO)mPOmLl#2-I75ViiY@i-bp2?g2K+M@8=IpJs~$uETIG(1V&s}qUF
zq_w?oB>KV^S-j{LrFZr5;!+BSn@UyZ=4wrlKzQ8`{y}BNC+PM(Y<UD6?w?c?XUHkA
z^QcolqXHi)jR8;|;&C4|;8Fl6hbEgq#^_pJ5wx_1y%`#i`~~i6Ugn;5zxLjz{WlFQ
z$vsh*A@nq)-K0A;s|{AQm#C{HVgra`g>HFr+x^=Cr}p~Bfh`c?!>kgCRYFNm(=Qah
z+YMGL>x6>F4CV;iz4M{v=45uAY;-(%@tDA4;#rdogFe87KX@OQl2u+KC&ZsTYNtqq
zw?YL~GBUv7KyFEQWrxXwf3bg%aFucD!Vmz3wj((Dn0Z7SD?SFeoTxCjC}5I}^y(@x
ztYY)}{-}RILMzCBajTIP&pGfRPNKy$7$DK+rOR7X4imgEg6gMC9!9+HWki||0dIaq
z<;b^##wkz1W5`1b9?+u5LUNRm6&L$>2vFXtDJH^gT<UCLCy1nnv*IYeefF<85L9%G
z?gI$vqs~(5o~|D*rYicRo95)3Or7u;X^^B{^r?>k9u-=ERSx!H6z^COBt(K=Y(JxU
zYE8`Je7-v}(483`5dSKX?|ttIT#lffEDntjOE>1$TNEn!F2cQ=Rq87o-y@F{;RLRi
zTR-MX3QE9mHh@Q_X1BKqJInm5Z~sr9ddeX~*Ct{Zt}@butj(*bBOsxoR;(=h)suF(
zSOJ*iv88lvMeC1lLGDE=>#=sEB=~D7MTS+cK1<(-BwRA#8+LeuMCUpRB!eu7Ud3|v
z)n^y2_Lt1<&<|vxF&Kq9@CO6;pyj^yfKBX+9tdM1&;2)AI@KJ*@EltUGlO*2F~R!Z
z4xA<)qdKV1k%-I@k}dH_Tp87(PG~0#EQ0IfCtA|m>a8GilFi&b8;srVM215mbW$Eu
zs!q&NyM?hUmxs?P=<ObD#7KA+jPjf6K5}4f{Ze24W7pA&`R)Td!udKB5lBU<qCPU;
zB4-Cbe1RBo&NrXWMI5T1fGx&V&{Qd%2W;Vg*p8pt_MlJhXdDsTG&O&E77i#y^%Jby
zTzZm9+*+B&JJQ>4dk^Rn2A_MABNQkesS|Ax)Pv5=B{*O|ylw}7*`sQ8D_loIuoG`_
zb071z_tzO&Xn}co2)kBT7I-YCBKhF4A+>U2U_!iEbYD9hWJrF-wfy-TVo(hlkULEA
zy7%X=T+}>D!YSV%aB}Keiq%SP<qOrEN!R79QDhoAVWpekw@^NK-;Q79cq2*VzTmBk
zcNj@%2c#23sQ}`O&|iPqCF=9Tn;ampCDN?>a>%lXy+yCYG(%!MNj8=nLh~bM%S-qY
zD)QsnC3ZZr{q7Eu3wCW{k_tk4Y|Y=;Vl&n{EBF5R0MZqEMoZVFZ&Z^hL3Lt5O7Frd
zbt#-_;F`Dze8q>u#3D5GA%49oUixwPSpLHFsiIb$lfp<Zc-iUJZgxD_vI>|_B;%v-
z;$x;yaND?~#+rCgz7f@a3_cLmqLthW*a&H5yco`wR6nC0x?nsZv|)L(oYC^HNs-m7
z@@Q%&e!Nbdrp_?r7v{oe@kv64kfHG$Dz@$$39@NOTK_Xe#$RWy9*;(t(iqwAz~+R1
zVAs~D=9c-UQAF{P#f$92{VgY$#l`sK6KZ)>HbQn3Sv+tia(Sdu0-LypL+ZH(d9&Kf
zEg4(EL<NFNo{if64@-N&Hq@%nld`{uxzmc+Z3fGlMiX{q4{;HXXOU5-9|x)8hByM^
zay-#7{40ZenQuS&H1{E%DDPd7^u-pXm=0JKtS_PYee?ZcXf8Gxdmz&kpKFK#8Z=xX
zy9ksXGzmvB_x*d{X-Ie^g=RjJW6oUfL5fP_iGitGzxTDXG<wo;F=P@PWwv1&hR&xB
z)=kR-rWTE*I*86Q+%hPanEa!25!z5px7Y#6&>s_~h3;FXE7g7ATseHb6|8w;d9dK5
zdp;h$-bXSb|JN*Z+KSkoGPN(9zXW3soQ(LQ!hJ9oY1lZ)T1wRIGe?P2a77q4PQNtp
zzr0fM^wGAXnWzdm*di4~Mf)M!_2+C;sKK&KK&BZNlO{$?LLo`@5ctV$U<(m2ZUs0y
zVHmWyH%-$I{<b}B@BkBHqT!jomfXj0Vt9A+-jT7Eqz_^QYbAO@^ew5A2ku0iFlQmg
z4DA=3gf*)z*6rZ>7OFoj9XvBhD2(>G+Ydh^7&=>WBx+3+xgYI<uxTcRI&-1Vy1W*N
zUTUYJyNQlQV2&t$Uwf|VeDeQ+vb3}@H)ad2@X;8$oVNrnh6F}*DPAjlC}(mmQ9RU-
z9Z&-xj|6w%n7mCBRx+wS`N;K1A~d>nfv^z+)L6C{n8nb-*DrPFZ~6;Vf>+js?K{?f
z2rH;(W4AODhD6(E+ApN4qB+W_E{UpnP23v@j()nU_pLLCXS=UA9M2=7I>kFhI&_1S
z@#5Uvv#>u6JG^YuQRio~9+qa92~rOdC6Of)ITPb7pHpm{=gI&^4kse~Kf0ZMAk;t0
z=zwS&i)LY+eZ!{s2jGh}Bl7}T{OygzN#`WoPn#1;(fh2m9g3rt^pqQCnnG)jkNbu8
zi47)64PXm66ak?O2^FyeWZ%_O!udGPtj_b4sMZFJwt_dd!VZq68+siK4g>oO4{%uz
zh#Q8WLC6}3n-CvB4DkX`jvx6M5k|5{9L#-SE(Z)ms%*X&jBgnO7&b2nUz+_up%zbS
z&I%<eRWj`DHqb!2#g2o>s=7gMY0`#RpsHt(stfS-uE5C+MTU*Lk^qSI0YC(8hoS!x
zfWWJ{^)1F_Fapur?0TfDh0VW@cEkk|IYd?f@xgcg3WF2twv-8&*a0cx{CJ!y-2s9I
zB59LQ5N?jTdHA*Z6+$2OO`71~N#KFMo+Mo)hFXj1gGJ3cSkz0fzY`ueLY~NznjaZs
z`Jpio7{qOSM4sw8^##@3T-Eo(yyei}J7O%{M8uK;Z8{%=HWG91>NXVt=y!B90<9gg
zzfu1Bqk|!z2N^6%78$^Md26hJ5%&kK)HWTjOV<wr6C*bMNC5i=8&4sF%s<wQ$3=G@
z6GA{u#^DHQbF+v`!Gr|n_uXdHfGA-P|Iqh0aEo*pRbNP_%i*F`w?`IMdsu<Bp8p>c
z2)oWdk{M1&f`xp(To%&|Q3gVb7}E!}2CE@w*+*#-&_RumoC-;?+5!3^RW}`9CS-I!
z_;>$k(7MVnSIWzXI2q0ND5jdIxhO<1^)Jmq3fWp@%b@<=mH_qsmy9_R_lc!W=|fkg
zup?np@9O~_e9*&!b!lq`N8t3tRX-T~Jm5W}Bf_pl+!bh`VGDglST8sBfa*xV&?mR$
zgedX2mY={5Hd?_(>xtTWcYd?&Y$dnm*BGn&oqxczIq*QHZ8{Wq$r4GX>QbiU`o^4U
zniw1@g^HcprRwFLV1}a85xa)se4e_^G?S#AD)mPo0A<%YSI*3I1iI7YAqm)sE{!Z%
z<YvH}+)Y0=Wr@;viIt|}Lk=kUaUZ%7d8+;i^$p=uiu>{0@XvUF2gzh(22em(eEZv9
z__Xd($Yi7(XIop+G$+m@7}F1tjjzx77y-{T!8kHD`abJB!YTG=(8=)-ln&iZfxN9^
z$*txAzj@&L)|tOV{n5`POhpv*e8l|r7uOGW`Z@%Pl-hV-!feQ2AN3KY{(<v}G-%gQ
z3mYfE`#A--7;avYS_EbYk>2QZIi2dy%6>dUJ|)gPqn^gtjURA6X(u(?NGECYU>g#s
zsXUD9>PLPD;S@8yYpS(JgxNuZa_OhFsvQC*xU-|(ku2H6aIJzX?enGg3HpyAXqjCr
zN*>uZQw$qLP(Nkb8lpp(LZL*2K~V{);_IC&26<JyLC=#3pCA11e<Ai)`k`aQ1A38X
zr;s`}%xbHgkX5+}EWrZ+S{Q@K42Y}=DX&Y6S4{gfBDYAya|grW4Qb7Z@bgd6ZUS!l
zEI<S!Ep<|H7CcE0TZJ{?<AEbV7;}*g6fqO`1n{(^!`2H|-<yAeaFF}hbT&Et>487}
z!%wqH5^kk-T@y{Hs1a?_O$9V&Ica@QE40Y@lV6nS<o7Lr)aUeZXWzCR)9w@_k`5<@
zT-u=pMSPaobqoiX-gJ6VtoG^y?&bk}69H*jc%s>ApaD855i!um$4Q+-M4&s^X|d`3
zJF@Z=Yj_K9T+zdu5IW&B53yK7&VKQCDVEDl#dRJGkdZnyIzjKy@^S#Cs&ZVjG}8ir
z+FoSYjE}SjTOd#N603pT;Ec4?zG9L2)`3%TNwk>uLg&g^3O>5vw!US1fR_Kbm^C8A
z2ExIZmAD@V2m0~AVE1}Cpa|n}L{{FDDG9YTV(EqHN(bvsw3hu~Vi7`~R0CjI`Ylsb
zU`yNrY&juaQpGu%7(jYaQyjnp*d`}+-zY@tb3f#XLN^}oV9|4PyaHOOEmn3~Y#R^N
z>~xcxViA5SeexjlCJ1H>e1xUWM_F4*2!D(MAq3qOy(p-D>i=Wz{iEc#uKUiaLIY}1
zu+*=*dRQ0^!LFL>VF83d%m9!eDPC38R1X>;D0Vk`pdo_LnBfdbDJKy@k+Blztfm^(
z)L;pS7zj+{Y#b5bfTn$vNTBKX?8aVU;29g1nV8^8S;l*^CSlrEeC#8TlD*s{C)&@g
zo}ZAkCwn%3><p&o2fC~4y?5XJ@x9-BUxa>WJ^~`vbT7f&CEW>~5JXY*!BZRG<UZx-
zQ@~Ma+t6@@gh8ZGY;cMwfX+z8Ag<PeRr4d3$4R=58yW$A(mSB}PMt!PYNN_+h3L4X
z)4aAo-y>l&i+^x>%{sxaS{o^#xw?Qaoi)$~5+^`8=yD6Y8vbQTLv~#qk-UrSsV4@G
zOoU<Op|5x7aY!pDPTZuO{R4mU!9xj+VeOt-RiyS=cKmgdevaf4>6u>z?v>pH`H`I{
znTD<}Dt=B;R9qIup%_pP#0roNhYy#Yf+$IQpVp2`TWhUrRXTF9d9!rd_LW!xNqQYA
z5{1QWMr`&>!6AAWA9OYk>q1hVe^vCGxD|+>X!u8A4Z$<>I&d+y#bZDo36k*M{;Rtz
zj>x8%clv}1+t+vN8MS`AI@%wA+J=sYeT?yUmPaCkD0XqFt{2KVIT9$DPllrB#<3&w
z75Wt>oz07A(mMQ%RaA;|S;WvIV%-N(TOw`}^h8ZhTD#$gu609qVoa&s$TWz&YH2K$
zmP?HNtCx-tkHV-xn{+z_-W-1EtQ8-C-=rz4u1bTHElhB{?P2UaH5ZwMgtCrOk!1d|
zuIqM1&8$!Mr+a}l>CqYOAH6#cD@||Vt+(gN)KO~0h+y2TaSoOO=Jo#Dk<5}x%){Qn
z6`Age8IO!sl9jS5G6|wX@Li*ry))HvFTj?Tj%-yDKtitg+N+!F9tlim;V)4+o-|y}
z<?`yLH`%CcqGl2dhtR4H0J5sMmpp5<9IhK$n~np}ae^a_5^XXkD<j9eOGjqH4t*6-
zSJcd&y~Pf##H3jI%)5M4mIp_v5>X(+%-tes;GtdTS~3hI>IQ&6Seu1TvsOQ}m}3%>
zEb2K>dfbZ14qs7rT}hL7j%?r%P_p-jTTg8Yj<8G~iY9CN+Fh8-#6>g<5(kc<kVyr!
zK0G+M7dJE_HQ-G>^mK=GJqTVO?E%mNKQ@#VL1VTV%td!tnw%hL3|(q<*SR@7c?kiP
zWy;VscxXN5k*ib9&n}4CNH}~UO_HxYuqlkoIuH)wfo;>Lj}0FdhYyd(qt+%ODoROB
zB>B)<30oIh%gPL120B5f9S%#as6tCjjsl!Z#H)rOgbOcnwpOVv;eOoL4F*ECqg(Vr
zj*+z7EdV?*Lguh$QkF&Iz@$ij<;c@s*g1yEJRQ>#n^Oor@(4bTW)&N9nBf&g&&N`6
zm<Y7dl(SYQt4AJzx{FymyBzQ=XBabclcldDbJ`z9#@^AE!waHHw6)dl#A6F+XBuy3
z5bm0RELla|>g+SRF#*CPbUy(I2zb`{IiNThC37j->82x5W0fN>Ru488;uIGL?pQwg
z=6|<|6Erk_h9LzYeWzKW?i{Ub9)37{%A{ZMl#~HMZ%&tyH9>I1&WL<nHUT_o1gJ_P
zU@dz2GVomGp%)j(lpdofFs_1itl24R!W<a}At+!B)h+B}=mhdUw@BBL6D>~_btWb$
z0v{Nm>Ns`c1WzEh5Nc_1uf36Wph%al(VWb&K00{&;2x5_*zpM9hSN<%ue=stUiO|d
zg)GC!Tu+S4Rzhit8ycS<RU5zuK@~IOk3{9Vwi1fp3fL+7YsFZuEQsrg!zq5Jzyj;6
ze|98C#xM{G!+XA$^}`@nT2EiN#G2<qPKi5~O4qq}-}(n<t!bT%8#qT@SsInD#Ujx_
zbDYp~oK80!_cX#rp|V64K}<f3C1`LGM~iF$cNRa2c{Qc<y1&BhNQm3~Hogpa_tJ3I
zjOK=$?UHO96KoVgY_iPE6huSGyRC}@ki@p20$p7ku_T}41(T5N;tP&s;=>Ne5EUn9
z{LlTVK252E))S(WEJ+PCT#3!XBVm>O5pQxTq$soeO?M>RJ3*(2n0(5r$S!HP^f)(F
zwKYj#vUv0=;~>|zG>)|{%)Q*mQVwxNyl}D@Mzu$r3(U&8Rmo0D?2bbW3vo@BxR;Jl
zVNyA=P|YopP07tC!gaql2ZcGq2BEgF?MqL9Jr#+dVP2I?S}IfZD5U@*WZmr{W00z^
z<?Jp_nR6i<PTj0Z+)1_ejVif4P^Z(2j7Kn`HL*aJeDB)G%;pIq&?Hoyz_@xab$PQ}
zRq?><Zg*`M{{$A3*n#$mM_&Asj37skwvOmXqMJXsOCLu3HIq6H*#g1~D~2x@2a9{*
z(N56Cq0pSr#tEaOqxeeZ5b?@3zX;pqVy4yZc4)#v*m?KlR7}e8($SYXxkb9V#sUdI
z0A2NCR(5}8*d-p`PyGk%F2sO@;Vp6|K1?@5Anu#kRBylQROqK=(tM_l8*58r-}L6M
zR!MWy!dhx`Ewdz<O{ks4263bsWv*O0dwa4gwN-<^yfjPR%N-Io6dm1zPvA*n(W@N$
zGDGO@mk{6o7NSu*+bo$kB1%b6a_UFK;Ja*4lvq}nwF*FG4jJ;b<inr<Bzr@UQE9$7
zb#x-FFOYzOILl$soY(ZgZPV1r!!;)Wkg|_DwTh-=Jz2_0;T44~5!1C!BSY28mPD3C
z_Kh6HI7rCpG)@q6dgB!UAtI-1sp#ZeJ%3?4WTBS(vRM3`LJJ^h!toy$<$*3+ugs83
zd16-s2o$iB>@N{U^~jA29TSqH5Rw<Efv>&i{uyL)GdmVZ>B=r<N3W2(aPTr=+c8~L
zATpezF0`?v&X!oB*;o`yLnI^Te9<=x-(QIj(-S?kqay8FtE;ih8XS6=d?%74@SsRu
zwpld58f@L#L{v5!*);Ohi~#1w9{zahfz+f40XKn#V8Wk!Y_ln7Eg0wRO5+F&G2tA;
zhq**M9}b;yu{I8f00NL5#+NCAY?BBoux$G;6GC5*13$CS45oKHK0diP_HD|W7CMsZ
z4Dtklt26?vxd>7wJL38e4BRbp1_6va6b2>2wkFpu2@e@}2GnFk7lJZ0#@ma{U#-fi
z9@RrMdCdTUZ+&kwTwbYDKtFQ|Y>0v@acrizzC@W|<1!W8DL>{=1Iv7=EHV?iRQL0)
zZtfOX9b!@A32L2$9?}$54daI;k{12sab!@-=|ZufYkg*f2x1%Og&`Cp066p#SUV^I
zIl3Y$a)&Pm;QMeEFOEUMhyB&T<}8Z-OrQPw`zR63m=VQfP?Z=I-ajYoGG}|6!`0C$
z(KGEfv(7|oVgOMInHhaYA#KuxcWY4~wXE&cprXq$PVLCz(a*w)Ae|eNY|9CK^CvKQ
zGo4K@W>5GYfz%Y_Sf=%xh)uUd5WV5Dn*`^<>P~7?V+R+d*ct$V#_ImhrMKO0Q7E7R
z4&pc8uKG`yAf4oLOP_A-H72KUnI|y=S5_8hN!|py6?cICCxZ+O&<Zg<L1_V={39`I
za|5(9Q`0|&cCP5@B_$`(7N=iP3jlsACqn)hW^)U6uoH%Xq_IX~v<Thk*+&ai>KIc>
z0@6SF$|iP^W(5j$U7{J1lr9n1IMva~Dd20e#U5VN>X|1Q??$bP+b3{5vlr2jsz_TR
z>NY?RI9+vd^P)```GqhA*|@PHYO;T1Lv%m4zdQg+F(6Y7Z-EWOzqO%rW^}W?vto2O
z?8wAwl8m&;-3XP9-IMRU_x8+LtB|uTRZ6h)Wi?FUqyiO)a@>;;Rx6oPD+K<_)>3YI
zy*9{Hf(Y7HaSIAfS2e1wiOIOqd+<}Db{4R2{5!oS0lIvD+#)v7BW}bbqI^YFGa}-E
zwYmV-Zl<VZCFKRuPL!}=fDv56zo{Lf`EK<PHBRX_e&uIGk7!n5masWEJhU6GfNCC&
zpQ5e&Bv7Z|wnE2ShR?d;{}O&CF2vSuvXE%I(jW{XAZHd@U!H><9xrAE^qJvVU6>37
zU>sRcBhCsboUEQNb8Xh;2^oZ>;g(eZQK<;2;B7|+=A8~HFB0JM)g1Ak{a*A@=}kkw
zWS!%cU}vbL;Yi?&Z7v$4jfg5(Ae#CFll7W#hn7$P+4LDEC_mt{VRnl5vapydtJNCE
zy~$O!w!W8zHh4F{f>~;sAWg;~3VI#KaEaAP@fII|w#*09yXq2Td#3B%QHUuoNB;%n
zzmNJHhrX~#uN^t4JGuGxSC5BaGeYN>)(e+SO3A3OHe%A!6*`Cu$7D$Xbe-sI9Qbzf
zTjoMD2+78oF>UcD$173mk;Q{!huD#?l41Wb&7AH2W$P}^G1)SSHsK3Y#n;76lkK?{
zpCN#_iZ>uJfhaT4&I|^2Gsc6gO}fb1@QM_!)m^{#q25qVm!{!$Nhcq5SzUMZdjQr=
z)%<*86rC|S)dL+3Lmj6piBB2RQtFfBCoWNzj55{Xhf6Jodm^;`o$A=16F;MEuAu_J
z0oF$b>$0E7k%y;qw`epdojnrb%HCN!C=oe<55+a;=5Idd4tYeB&8I74-%bhBwZ&GN
zbOdtx<h}X*u=BM(M-SkvHRyHi^bFJ4$SbuPdwa~>c+A{ktJi1(R>#5h&J+T>sA%59
zz=-*Pc7{hwPaUCkY!uF28aXE1p@j}iJfKG^l2`T*aO*OpEYgQNO*srj8E`*^0wrFE
zsDtTDI7LLe6hp?vFPVoRuEfN+1QZVqbWALD3?CxLi12s*vO>MCN!5{77Os0g0`<{B
zhw_3E`q3kI<o_H8kzQj#Z*dE{dYY6JFZy%~u^XA%^!C))|B!`mNgxTsD?iO6kV%&U
z3;5lDBh0#Fqi&Ho$+RzNgv@|)X7vDgQ!Bk>pl?ohS_^gBbmr4f{%74Z<@gQq)HF5F
z?}hF-WQx9xMjDey&j<&LaBWBs-3`R!a<cFpVWy!6?ohO&;Q93VnQBdXl|J}(L<ho|
z?NV-5Jsak?OM(!ME7K0_6k!Qa)6BGlInwKXbyc$Gud0Qe-os{0UfQb=5F7%flw&);
z>OWB0B<H}DX|YwBRrmq&xq}+!BE<v_VL_F87inApeTYR_I^B$sbgk!gVW`L^;*+3S
zI##oJK&mXrgCt{){OLH_OxXH|x**!x&9h>1ZbS@cB69;Wk{aSAdTqUoxot+&)oVNH
za4oLGNY4>(VUE7(a->C`_vG}(_YQrJvOEm|lhlpm%*;0(3Vd;ji;d4$Ipu}f!h(bz
zOD_bXTeY;TRmSi9gn|K4IxMYWiFGQR_cwL0)&xfbs-<Vid{zth6QWRVGmHHnh+ZBT
z8gQf-W87ixBzjppBvFX|lA;!38{5d^eU5N<F8S|H9>z_^yaBy=;PU&$Nyh)YDT@Rh
zd{(+v?l{4@){UV(aXrGlg{eO!I-3nDGM7aOvUkiiF&rZ+LY?L{mXJILw5is`P9G_v
zYrxMjJn(h3R!ivMvX7Gm%cOFr0E!}3D93o#NZgHO#UaTXSu8=UU8xfti60tps+(iT
zu}~C9cF-Zc2EAQKQ3Y6$cPeiOTvZBZ9Wn3jxIEx^psXbex-=5mKR;n8f+|+g?vU@|
zhyF#SPqMl&q6AG}ONHQ0mca3@wZ9SJC!lgDb<IGGA5&{spCzh_M5T;H^c><dVqg)-
ze5Y0NDs{9cjmZD|pW*mxy)38<ZH@;4)!iQQv!;XGG(qVRo+|KKPi_r)0B>^%UdsZ~
zj0nCI7wq2KP^yY_*GH=09vD;j155`x0gBhEPPjGN5m0@9gek=ZWxEEsbuQ?d)m%zM
zkpUHMdvx@4OhgrTTBk`U0Ieqf>95KOu0dZS$Gj2q!2VVeR~nTg;ds!)`4_AXhkh?R
zZ9k?Bmg}sFlB2I2wlGu_5F9yu$)>d{UR#&6dW$!`f<hCvpbroNPn0x!N6gN;XmqCp
zud<MtB1A=ds0>`3ODLT#w<is0nfi?f-#1OFoffZhm=htkyN%E-G7k^a!zE%xOzNt#
zAV;=+26HZh(2`HPZ1QYK1AALxY2*mCAl~Gk2+sz`a307o1JhURCU?K$3@qt@E+OdA
zF8RT!kQ)?E$1MZt7sV!!x_CI^KfnZI8BFUTj@?|88g>elwe&}Sd&7P*e_>hQqN@^d
zweHcAltyuThnt}qpMt4M!xk1j!#$U3-!d6nfe1uNXZhP6$}M-7dP<`s6*D*0dI|ZO
zA)b!0Jy|@xs?{<HV~)Ea+l>gNH8JV27(Ir#Hi+6<-;;1!ERHC(dlAK*j0Ei&&^~M)
zUkwd&Xkn3qO4BcX?L!<HM!$F)^`w=eAvVe$=7$4Hsh1#|NRSRsec5nkInFhxfUFAy
zS4oSI;iy7^s~q_{5C`j$g5L_Rc5Mybxkm0qlR=%6gz_Wcmy;f1gXJXCxyFOW;eK7@
zN`y-=0rvfXBx|cj=dzMz5<&<~F!TB^ZIJM|%od?5TPTeYn?qaF;UR5ubac29OI>f4
zwAa?;o}~6Lvzkj0&O1t$ghLBdWkYbJRlz`Eq|)j^80rg)o2i?@s;y;mEX}ca03t3~
z+%-X<=4k?^tTUPtp~~}E36CeUM{s)H?$B}*TB4{gBF}v4|LE^-=B3lRHm$3mt!KTE
z8VLI%RYO3>i7M(uC=M%L^P2U*RI*BN?5M)TA8S2AkQr^h^iV7_C7>|eHwX^Ttkij|
zQCTAP6J3;ZAnPz8p#VlQt6^DnWM1y35tdg2=MuV8J$`#WL8cbwrJ)N42&TzD`_1E_
z8KQ%G9JD7@11h=hhD`-avc=JapiTreJ#u+LoR;_dt?O}FJZDpi$I)Bi=p)EF<f7g&
zx07dkP)tIIyX0RkV@}Jtz$_5PsD~)6YD8y~thi{c$zQu55@pka16^Hhrf^(P?<AVR
z1B5I{l3fo?3_jhfbjTW6{OH_6U(?$Ml|w!(9Au)YNs<<e8M|S1L_{<zsSY8nD9|QV
zRCJ!?RURDJspz4nFKuP3V2#6W3VlsRFq8hJ?Vf@CQeKpU|2l%Ll-Vn+*Th{fPMlJK
zXQ+dZ;_+}HCHn;5{!p$;t$0G}^sVe=))nv!XOQjAnLXifGm1}yQ^I=0R|ek{lE#v`
z?;`26>X6T+a!`(AmyS?_YLIA2n7?zEr1Ufg8Hp-!f|zHQ`kiDtXgRRYv@34^gw&dN
zax7G)wtn0f<5l9hT+D{y8tjSr3a+ahJz7g)9MCN5y?^`bnjFhPb+}~(u;mA>L1#~?
z5uX_MoN8>2ume{SruAtj3<?{)csp38biblIij>I5Jx8w<j@1bJaIkLyGPv_wLx0wS
z9a7DSgN$8VAG?s%Y|Ao8#(XJm<B*5yNbBoKh=!-#2bd-f%US>b_%(tBJD~4F33zs%
z6k3L{x?UVkae0o2il-nm@GjyaujOzrIr{<ufXjelkVT7Q#*Ta}T#8UFePduhIRQ=A
z796h_$0ZkDyh9vbLW@Tvzrnu5V?nLns)uDLnFf=50IePcX1Y2BhZ`_+p0EPMnK0)2
z|I23152l5&{if2jJ{@?n$M~pIF~eq5RiDPI7PbXH%XZ67t;zO_42G?hsbaA&KxSDR
zcu8>%j+PGNRKf;1`eNl+jbv?&^fPr3OXVp`yFWu`M9F4OBDgrwrBvdLj|(s(Gq~13
z0?r86@rKxXHv?xM#`&DW*mGuKjYyeOQBovL`;9-=hIM*!AZB+d48}MkvT1B(5|r&{
z8xq6>9MA=SN*aE3H~-R>!I)$N5{x#h!IRgRqt&o-#I5EoQPh(FX1p3NAvCMDK0|1_
z<^s@6s=R5>CAp`Gai^Ppj@NA(_(NA^X|mlWu>lDLM_hxW-(Iv1QPU$d9guS}PrvuU
zUL~z}EF70zOgiO~rK?H~ccbcYNFj76rbxQVvVB&{ZN#fw>muX8T_%%=N2d0Ex>2GB
zG|KGAX~OYEIx8%a9HQDHS&wS2vgz(c;bti)VcAb*gcEU;S*0~G3>umR>IOWS?I(nr
z!ra3V+}b_%73Fanh;HWH8^0U;(2{znX|iOLy2}Ze*P#lM>~}1uqK`tP14#_nMpdc0
zV<UCfi3M88+jPAENpuwXV`&%;N;v8e|Fj;dJal?a%4Uf-@n~c>2_(2AcI&)=8<9(=
z91nL{v@`qnCuwLAJ8@<_Ngi-ZM^9s-!8bV+j5G)9)Om00fqHC*6h&cm610K^d%^2(
z3}FbRM1^|_vr^*_{>jQ{2+CH>4GuIf$siDuY#JR@n60NTJyctWQE-c~98&+|P}7RB
zksX1Wreo5Sq?QIMIP<_7xpmkxl!tcL+5m6zf_tSA9yK&0X=M`yv-FHOCWoA*_x|N=
z0=yA2OF(A!s?VDf&TizcIYjMm9D4+e^$D&ISSzk(cWqW;G6|rIz?@)bMP77xsAW|*
zVc92~#j%NwNO$LuRCTN;JFd8z-R!?eoD_QUCX=iVj4G7(`b~s>TM0`=@C0phxhwDO
zw>U-{jRSg8MIogApWjBN$E0YDmUuXuu;Tia0MJnhs~nL|<5+o?o*d!I;$&&{t_kg$
zQBJQYG6Vg4twxN8=ZzC!e0v@weP%I^r9Uwd*>ZVjS7UdB<t61ta+&0<Getj7sxwh-
zYn_`cUS5U@vf_3Rg}_jpbiC3!M9^2KRZYrZq<H$S4}VB@9%m|)+2foWwnr*eqfs@A
zo{l}dNGR~#Y|RRgvBY$gp-2y8b^BmRmgev%RnwFmZJIjzSO<emAPZ%Sld#v;5oUfT
zlbtP$&^B2b+HSE^syTK|j{97v2;}(^Val2akRgG!NMl{j4GrkUhmS*?k^i~T50Qh@
zN|>F3PBH^RTr(7nPMXG~c7~V4VHV4*Y<`BZ9LxwofC!+dH~|NofP&z-LKfxN#ZE7j
z8iIbPuK53*{HZmmn$@J`3NQhXfp^9}5T*#q<HzHGEO9G%vj`X%P8cstnRFfwX$2^U
zb+GoItVkTd`OHc&ue1!)g)y%xSeqWSI{9(Ae3e*WsUw-}5mC_ZtXLeXi1DA<F}npg
zt2QQ(GRusQZtonjIYFvQ^Po%xJacP2AleCUGlTeDdPYuqlhDsFpKB#7Bdm4@f}6vl
zbfbPWBx^#gG9a_o$$#^oygwwEQPZNr>aOEyL^LLstU$l<JcfhPTR<0g7bHWMuXESk
zPqw^}>&F>CF-?o4b893PYCUw|1#((oF$i$hAZ7)J$#(sUU$c}ybH!7cq#0T8W7Ghi
z&n{!YneC)WM^r^4)lU<GQ<g+nhPRnd{2%?p_nX~1yM~%Zg~4++{|2tS*&M7lN2|iR
zoUHW37C>AU(PaB1!~HV}%is)}sH|k0aXb}04>)%45xN@^p#k?;waxH$q!53(R$VNh
z$kh^tCvKOthRFe2cr1swp6fgsw>y-~Pa~rvrU)O)K6Z`7Ipj&K%e=HU{_LI5WPl}U
zO{NstnMD7DdK1LljP%JWI0V~}AVAQVjB~nn&o6HlfPZNzU`AoMUrDYF>iO3z0>_Lk
z%wr=dep}0LSQBYxN(^L$$Wfdi+DT7pB3rjYG0WsxJQ@klP+tI0to}=#vC~zOfzZRU
z&a>&wFTC<vJWGEO&duP<(I4lwsAi<so`s_+pu}X5mF|e3tss~L&g46~p=Y-enk6Y6
z-d!DyJz*2RJ&&P3Bym{>Fq@=y7C3iZEQIFum1Pkv)@>g`EwqHpo+sb5bqaZv-;D<?
zmR}HNQFLkAf!dH%SspA5T?+x2|MiCsDfqy6SPE>J+{~cZK0sN_#b7wfCdTz{4ODWV
znYWH<RiCj$sI!k^aCud$WEqp*LgnZ|Di9WrEu>w4FhQ5CBsW(KX4h~?7TpCfcbsaJ
zgMM|3BFmOE+c`_(26>BfB}Qn!5MWtkJlDc{Dtv%%{Luyo4s=B@;nZn8x?LG6?$zr<
zQ~}1sz)qEvrSztykK8TRp9K<CkcDeSa2a$Vy>P149Dd{E+!R<=z#36^j~-YX;jFVT
zq77KL0VuRFdv2*O<C@@xPO{xdKs4EX^f6|35y?*TF`Srr2sQPEd95=x^K*ZgBVZ{@
z>wqG-@-Et&atLI}lu~GlYFhXe@woJ3S!D+OSiUT?G4xAulx0miQ?1EKdYRBeg8Vsb
z+L+Ew39$b&#4vuQk#1QOA#Obyk<NsQ#ZXXZ4Ckl#%#c&CF)qF$Wr=CWqDV|Sk{x4B
z(wjf~3ukH7d!HgXBS+0Z529zXw7jJqSA(8$jq3Omf#Br0hLB~D(`9Q(5%ew>4a(r|
z#ajjlDamV83FaPAZiP}804KUR#tUqmjOlb^nX4fw&8w_Pm$;1amyFW@SS&V^Q`E(e
zS-Ui%(pbJO9{aL45us`@lth3i0k#b_HA#|w?i(MFt<8ouryWkdv;qH}9ih1aXR(5f
zp+6`t)&L;9kkFR5{Yqa4jHZN}U5|`cgbJygM3OJj6n>Ga?xorjY|YF5GSr0FOA>I!
z%aRO>Yyr*`0?RB&P_r&2v%F!%j}Z=9*S8GD=8yooqA!vr$;o-OUu{f>DI?K{hI_a(
zp_Ya>fGSTEH*l&-&YK#^g;RK#Tz?JdzeH?Ug)*}|K(VNM6`qMt7S{hoy;eWXx$_G&
zXj)enlm*V&Cdss|tVe5ru$F(KmvP<Kh#0=*RoPGclS+26{Osb%%F!=Zjx5kK^;M7n
zA{ii>_nzA?0G}KHW0#S!u2mNttk`23C3C}QD<u6l6>|va2u4kunHBvkjpEk6f>?$F
zD-MUyX9$Af)n2MmH25k82e<5Wx8dSCA$wiIdKcl5PtdRl0h)1_qjAZfGAHYa!oUGp
z|CHtD3s(z&x!QN+Dy~3Mjp^ryS!3ot_xTO9t1&qoU0Rc#VB@I0Lm3?t{nQW09^yhw
zf^QP5E^nPo<OJf#+<}z>V)y_oY!R(Sr+Z{sI>H_~od{r)!a@SDmHrt13V^=i*LNX~
zopeSRj#^RuktwKdELFyPoX*xpR*0vIN6`I;$cfu*#m$SIhfp=gt}WsaWVH@Y{pxG+
z2}=mJeNIB8HcyoRol5(|$ZS4gg<-{ns~0hxuDdBlQ`T}Vk6Zede?sksj&2^NzFUEZ
z(iu9b2)2D_p@4srrt9*VOETA;?o5{Mj?n7F+f0N8wz*CXusGRxa7<AcFMFtHvNy;W
zlZGnb5qFl32(|al{Nm#rnr>@$L6;0*ao)5Y4rkQ%9;r@ks=Jb;h_W-%*7b~BT9)p1
z!*RZBjyrIkA69e(1xT;7<~pA`gjXwelSL5?EuS*A$XNdp&5s??O^1u5k=3wxvmCc3
z;mjJPw&ZilfU?2h3CR5yr1c6wKpZC+&CYx2?`y*jdO*QGgKq-%6uxdMoW>|8xn=f%
zH%?L@huH)H=z21^3@6muoJJO&$&nzWXiVP4#W#tnN9NwD9HrLD-n^JYziDTLbJ7(P
zQB%uQ1w;mqc)}C!8R!W^ATGx`U~mm_Ky;d%4djJYssoP_Vc@7;E9B_Vb^7&RGLX)k
zSs<8^9zt7A6pcI7V95x2S||WgxmHegj+ULJkr|rIdtL+1TowWi;{$Xuf)S3wVjbyy
z`B^xQFrDZtbts>~GHaaYrEw6Zye#SespccNoE0OMHcvk#JHwJNj$x_!Zpk{3ml>nY
zHhs3)llT6^4~ErL4;rcf=xm#>4LSN?Wf)R|1>>sPV-YCxvQU89rI@Chjh$unGTGvR
zt%CxDI6%AY(&5n)PFNXfrc+~neI}$|s3e&>WE~`;SvECpJ2M(0Ug8V0=SPq!Y$g#P
zdh-?sU?tB)njC}4yn`oH#}3WM9Zo(ZQqJGJx-Dz8VcKUEry1d7@=!E6fr(SGtkF#s
zBD8S_h{Q@SWA&Hp{xTbI3B)K~HW4<?>S&lxwm5$?BJbaK<T2n(asEh;AIiEdt;NZ*
zP)h;;{F0rN`3OssG#K)gW4?hHezItFvjCVGG;6LyjW{YLov+f)C-HyoSRNt_0lx@V
z50)~F$c|G9SV2-pj*JARbc?Anjuj|V#<2pEy_IeD6M)RTWYhvXpB(3bBs_@*#*z^K
zbxQ-5)Tr!_)dG}>Oz0oQR6GJog4UOy?5A&$Wz{7|z;=$kx=>$`P=QFJX1_Ol;7v*E
z+4%bokvz4HwA{q1(>g~w=R7)fga970jPwr5vi-~M7*W5ZWss}Pv}P~qS8BA?KV<-6
zyqG47=y@DW$mdn07$0MGQI?9)QDR-5NY_%zkqU(9j>A}TKfxnoE@V@A(lm@3d8y8v
zsn-N)X0G#Sum5%9evbRWximGx<t?+KhxgKT+~qJb?n$r+hQi9QpBVHqY|isns?dd<
zSuAn};!vfi^K9%1`1k3B1%lZ_Fe9YkeeLNT453TP5&_FZjJ+a_#^sz>q9wtwG>qGN
zS7u4;WxF1p1DgrZipEz!q%{V!m|6U<o&L~$>HuX<crjKmj~Op1HB`JEV^`cjGBX1*
zMywIZudj(=mQot>E!+NgkOlaJ%3j5}@sr+oeX{=LIizf6aV*sqNt~{U{j&@J=1#mt
zagoLEuUIDaz`|<BDZ9me5lf%Ba1z2u*$v6`1rlc16SOcc$xN2by!WBaLR~nZ+j5pi
ziBbnl%vtkpr^kRlYq61=BlSn(up;Tj5d5Fj>DqgqemhO7GEb)4#UXo137C+57FUeU
z81BU}dY~PW{zr6iUu|)Fak=NzlAM8LNE{$ma)3oaXA*C%xA@)hWbOe2`r9tv0Z|W&
zQ(HiuLH^L-qRYPZ+0EeOa&RJOY&U~^Le0ap+zkbwUnBoKg|cK%gHrG&tD#xfgX#7S
zT7v%3XhnIIQiG$`=s*~br;BtAA;hflg?FB2VAFEvplpejG&7q)Y|IoUpFjpV5^eTV
zHFH)sAVKUnKA0c?RT_F{$B@|X&A(cY_lIm9Iou5g27CsnMU)!Zb5$J~X+<6lw+cww
zx-#0;$iFu$*~H|NHXm)2Mj$`117;RF0>~~T^P%{c>zuK5QKr<AzwAkdRx;;8)Rq9?
zr}!_T|2&)u27Bz<0^?Zdu>Q1(#)Cce?(V099E&5aA|4j<L+t2T{h{Gl_0~9zlxa=g
zqALJe1FUJq`(JPR#n)VN$qG?eZH#!JO;+orON1M(YbknRCCXfDGG*U%1Axr=m(0Ww
zdb6OSGdr?Y4<Me)Msu0Yh*3JSAeFQT8jDlSC1N*Ee}Yb0c0u8eVZhZ6x@K`mXnnX|
zL4+NY8Sa=A)5%DdHVUe|3(97LA}0gk9FE2?K7XS@!;o-_!H?}&5L;8VV9d>E-L%=N
zI|c@r?QL;>r5pexY$O9@W$XMj;}6XQi^;mDY#F=~{BT4JCLRdjkN$~aR$sBmTadm8
z!xJieOR1}BhocOwH6`*Q<#7he|NLrpsq4vH@A@&ac`lo>F!Gve!>z*ot+W=rO9z2v
z0hkuCaH&8U02!-pOtvNrV**f5;<1Se+(N3U;r<dU{WR+@J`bk=Fi)+w7Y`n-#q(^*
z#cV}Ry<7Z#5bv>i9r^@~(>)MNlgujblkEFagK{!eRkxe?W|3ux$AllSR-qAMFZG_l
zPZl~RdB5(fO1C%TO4Cc<ib-uBBf{X{Opw(GE^mLr<g21`#nxozaA3&Q!oZLXgP5$@
zFcMp4%h}Ce&>cDwl^2I(N{^-DmWkC&I&Yl64XfEJb%DKznCzEC2Qt?!`ejlB<BhXh
z9Kg)1`FJK^>sF;Jau=whBM>Z&j+US#)BLP@s7Ysi?99SEt&=w|tx8wEmPCK4??P8C
zH$4wVE`fy{=JwO}i7X1D$eM`tzm{o8lvoY|kc9sK@?2S+x2B0Cv6W;12J5co(28l2
zmd_(ohQsJ3yS${qmc8UP@G{`PSunh6wFke)soZvnQ<6Fye!&|OO0J%#BW{`a$KB5?
zsd6u(C1h-D{=g&!Ksj+@R-<AWGTuw(!XQ}pVOr23NQaa$v<}VB$5lHg`s;!3(}Gvl
zgW4>Pz3xW~o5iBg7#jHOsPBQWg5GOo8-6*1(Jh{3B`#9|D2S5aufw!J5&vzR=)O|3
zfnaTR`e~3Wf%>{DvEsih*+?uTdYDQkjQ$8EQwR*o6wz8glI2%R?_u!%k*Qo}Qc%Le
zj~DNiGfu{S5PT=5JqsyI>M=O1(zzQ714!RssYmtn<dF2bi(Zr^VSi*}$-I}OD^dW-
z0DU5md)Zeo1uWCRgL^w63ni!}Dj3^HSiEzU5t{}0-P~(;gP@TnB8{~51WSUh{K?y0
zd>x@V$%=3c8LkoLBxSDz$Q8NDhdyANbVZgfOqQ+67u3fZa<s8iIfBPKLMRoFk9#b5
zNPNHCA27S~Rl0H!*+O9eZn&f?E5!FPk<0fwB(D&z#T*GA0h4J&+g+Je@e&x4<$2V_
zl;Dz%W47=q*1=<|wxo-{g4S{~IFxw&tr{DU{g<A4`D>f2Z--Ji&yiivqqjKx$g#mG
z@X4UMJ3v7bob}8{77%w=f!H^5z+`3QY&$AUvlkp5<skF8+8mhb<Low?h_g$Ce$j1@
zz6vD2F6*%5<_jby`-EO?c$EZ_h!#5QC(4$f6kUvhh&Ww5CiIxh<;Ns`@$YUrYtgz@
zr-2@BlTwlv8$#&!9v-&paRmZtJg(vBuQtk&7=E>u8J<G1yG=NzuZ1>Yk9g??d7F7|
zDov!zz{*l&AnNL7ml%X31r-}~KG~EtWcUd~$W|@$Q$*;h9P1SFP{Zv^CD(e_0|%Xm
zdilB^m)&H1_*Aqd&jD#AzfIYNt-bniJGDf4)$)O7loQiWbj8W6=!C#Ard=~NJS{ny
z&XeJ=g4}6OFLRubm)ntY0Gd5)Xj&8{QIe1nYjVQ)Sglsh)!c1~lj^=kC*t!w*~{G>
z|9lVSaB2D6fT_7<Rm;19&uh(7k>UDQ=!dCR@a3dR`{ag>%4^mR1Er*)6Kw9xtlgbf
z4Hy>iEwsq=HBal!9n!hH^3%y=nw8ZH*YL14cU!90cJ!x)R(AGy2X!-v>8#=US|LB}
z>V-JZ_)<SDU8OgbQ$9DSr5tp~jf4sBrpo91RQXrrblc*|_6FCTju!a)@$|mX)WTX%
zK00X5xGkSUYkLfHI*N1V^I_nodUPtM*|oF2=DI-i4Y#MQPotHG_Y9rNMI-)o_lGy`
z=LBwzv1r;^M`@O(Ihu0;W0#xPQcXMM>Y&gj{fo4ML2X<i7o_@Gn-NjH<jOa#R^Aiw
zjX#!oF3&c~Mop^~BAy(}mCNt!`4#yO{zuAfEv?MJxLzK~XWn|dzd3xX%Y~@+vbBUC
zBDc&F+BtbLTat`6H>5?j8%@jKYP_5$GsEwV4g^*oxWuV*{>hUsIHqs+3_8VV+*I%Z
zjfzo;4vw`u=vljutz9EYdfL6<?3+#=Rsd8JX5Wyr$EQft^E^<h82_uso3~GoC#S<}
zQt)gabS{h^bmyY&=~Z{)Zm)K?w<CQrIww!wV;!2ePR`q@-2>6HNe|-6$%{O3;CI}}
z8)<*XU5Iu}a?Lm#9<)w!y~OVM-XDHY2KC?M<L0LutJiT>fBb*`iS_J$$V9JxB--!)
z6D{6$*z4nXT>h&NouiebuIexBXeLF&tJg|)YMixB8z;w298D)t(|WpS>fiK2{q($B
z)_16yZeFo=s@O5jX=7(?$Hwwtb8A$%VAam5$DKX)onFCdC6$*f7P~xWX$OEya;8&u
zoQ7vM3-(<202{n@(K}naVrz#kcy^+F^4iAWANjkSR7-;VNu%x#UsZvwU2v~BSIl}1
zxv<kPaZhogJzKP`pY<J7{4Q0v2oj=ep*sm<HFvzdL*>2ZlUk(NSG<#sQI4bhakK<4
zA9hT(imRoCIde=4d*fU=Hq4W`5j%e%$tBu9TlC!NhL<?5hH$b+0z(DEP1&BMrsc;$
zYS@<M26-gj(vL@41wGOe)pS8G>_VzsqgI<9w4M)Zsz1r8Lek<Vd-i#&rg_uJoHbjZ
zl3_e4m{$Q~kl7%AykGMYFVyx;=X|?7>;F-rmnTf6?eeui8FnIX#;KoC-csonQ>h$m
z)`AX3O4P{CU{!+<tr(YeW_sGN*h~8HlxvoC=A<WY7V-&C@)eJ?_c49`%1P0w;|@}l
zr2Xj8P21;{d9v+<vt}^ExyAnUhJDF^bJh8$x>GXTiq5+fjKJ5!AVhxzc|0YwW0}7*
zqXk1A(XF{u3#7`{_gIYIQLe3>o=D^tgIq!9?X(1e(aMo$rtNp0++RNVusLg+-l+}K
zN*QM24<%;mn|A77@GR@RTj&mSn;sTW$XteaOy1B(AJnFGhaWwZf}bngW-2x>&HhYn
z`*)J0%@|!2&RNA>4j9~M;>=6a@Fa<H_V@eVccA}p?K5pX-DbG%FRPwCHY)i*@}>EG
z&o~8l(AM0f_X)p!(JVXB+eviUALJ0bljp32v}29c_Kz!VNImaN>(84(TW@U3eb}p6
zWD_RCo=G(@R8_(6nX!3#PgqRi&o0=0v}I`I@qKY}q4~Ju583wf&OzqM58ZNTO%5N}
zaF3}S9ctd^xNiBfHy)mJbN7DvLx+;k^1^7s)Q0*vDLX05s)Gr11J54P{9wj#in@)(
zw95uIGpKp87@@XHX>r-WK0V1O)Y&L>hIM5h$OT~(=c95Q=KVl-h9f62PPry>rNzUh
z7kPTT)jJSkHQIw7r;SJDwtn+(H_L7`6XnBl+qi%@C82-C&lrae`^R-lhF{1JJl5{$
z{x0NbTIAq)_9OFxbEQQEFV2^poW@Q<Am)|!nYOwZm2<WhrPlKn=s5CvR@wl{Ygi`Z
ziWmN#yYbIIsCj8-1JZ&RQUl#%7924gWrCeF*jzA@l#S>fS7-$B6}0Vo*~C1tW3Jc8
z8uXcVzC2%3S`ukjhG=?=$a8}x-`qmZav4$7zaR~L>2Eh}-20b#Hdbw)y3?0`YIaK)
z!PoXX3a86a{RWPgueO+`j#X31`5+13e_ji=i~%QGqM)e5qzjm>P2(<D=^o4>G8%`n
zBnj`Bwxd{Ah0R)^<56%QJeON3Cx+Lv=`%n4$A1i??qnoG)sEv`z~uC&je_Ag14hYk
zloRMy-L5C-Y3f#Vc|UmrEu{MpZ_(rACd-zYAMq_Oo=lI=rNieHYdsiGPb6`@#=f`2
z;A`yIvnEqYqF%FZPX2GxVcyevYSA^9t(p4ThuvvxI`8HpBgY+-4?|*U(LeI?Sc7jK
zYW1#7vCs&{*&41_VM8S!oU_ZhLVnwz+kdXt(bB}al&j<%w7ubOQ|6F++;w?x^Yw^}
z{?RAjui2b!k9NkBVMmvvFYxCz9}JZb-iUc+$_uIyA}ly1dqO9jZ^V`t%~$h<nRFJZ
z&H07+u`tCy<=&0bZ7uYT;o}GyW*{;X{_tP^nWj8VIkT=RIEK^HHZ)auzrPK=Q_!s)
z$c89;8K-=(rrH&?tHelUy{tIId#B+>NExk~QF^P8J5K+wS_(rX7bl)&A8)gCg#{Nc
zjq$k1q*r+N=ZCMjXlkd>Zn%hPJ=uv)X9XRrFT%3PT56_U$n!^);*rUU%5pO5=}<?<
zu!Z8@TupAtiCx;xYQcGD`l^WtIN5G1;~yJLqp6+s{Kr2!qMK=Yyv;yT+%Lq%)doe3
zkQiP|$q66lxqgZ?1OQWf039&wZ2VeHOU~Bp4vGYOk?<b@JHoco<46UdnLLRKLs`V!
zG_w1hU)a#I;Vj0%dVKqMvImV@tLc7^&gWOn0nAg#+<PU1+mTT*-0YFJ#9HAy%byI{
z<+CCJcc*3U#Q~DgNDH<Lk!`>Mjvc>Wx4rU^X_tqF>}~zw5B_kJ>6$CIqjr0|tzk{t
z#<XsELDY6xOS#m_NA`{~<;n_kK)SltV40nA+-3mtg<Rn=#KrLn8!qfJ3r$B0BEt&|
z{MobaG&g_q!LMH_s^?zcH*xNl+`i_v&h>4>|H@IW8r$|yhqi6I>fGU2w<lZPF`a?K
z&KBy7x6p#c^Q@9F$P@<$h<SqAmIrOMB~*0SR+Q0%gCz@KQ|(t)!+J1G^f-)r_sBxr
ze_xu0Uy8rpI$!$_-|^4a&P3HWb}SzFz0yK_zq9}8e|N5T{;iUE>}2JrKbP#i?bo9*
zv*7LawyA$)x}4>)!wJ(TO!s=^4EC5G9x@-b{^&Q1UNicviF@)Z=Uhw~UA&yr?ZnlG
zIunj>JC*2R*H@LVD4LX*QNs>&D?vKW*ZGMR(yX)Gsnt-!^gEvwNVZX!R6%ZA{AXc&
zt#)Uv`h_?=y{E6UXr7<zTQEE1?&DfoN>6-j^6LHD;>x4#OT%{b@qK$vs*R*NhX!1K
zXkfx6ogZzo-RYq{=7Cr4*3CU?z#bdA!x{LhUHQu3NAh>O$CJ+W{)_Nfw_GHi8`{#=
zD_?Qk`VghYL#j|4RA+5!5UCUGD4qSqKhq+grxGWWAB!6?cV-+~ft8LY9V?xZhjApj
zr|*Mye88J*e<_^0=%i<?DI-npcKi6hy=`4{>l6NVVkdvQUcvaA-G`SO?|%8rn@;0$
z>9XIPall)Rn}dVTo;>W3(0OL?x&PGfeEg4{!O*>D{EWHxvU^eO_xHZz&TWsHyZ2tU
z^|`_NOexemW2(0?qg?BZk8C^<hO<%782#pXbv=AZ#iOOm_60S%MZZr~-vZ;lFD_kB
zr6(t?b~C=$dc}OlHalaDd(^YZJD<A$=Uct+oVR~D{n^fIwG#&)RL|_Lw!U-6Wb(j#
zV`{Me7bWurw`9L;UKo7tq2YUWdm{_pHVy-V*S-4zKYTrUY4>Dx&V9z+YE}Pd_u|k2
z_2MI6yqNd)sAt>J!3*v{UforE!Sy_6tKIpv{)@$4-QPZbq4H~tEEv8(KaS!HG*ztV
zotn}+`K?&sf;~oQYXcPqRH2?%VTpX{17X9`?o*9}G8+DNKLg2?)UP#v-EOF`_p;si
zgU`&VXVlMz_ry2*`hKf+Fn6;W-!YQ@!FZ#8u>QThFFVbdPIK~JuJzns_Yd^y@xYwx
z!D85cQB?rgo9^@OerJ5UyW0vs`|ijeKF^VSgMPYq(0Rtyw!Lfb^9mP*n|aS*@RoV8
z|4eV`oqne`Yz}?Wbff0bU~kCL#f5xHPr!Rp4N6E}V%F*?BVaJSD#sc;5QZ)FW{C9(
zTBYaJ<lh-Nm>WIp9Q`ZXe(u1Wde&+DWeuwC^~-Y%!uqY+XJ1s|=%m?s<L$;1I~|U%
z-?P)HzgnGR@y~ye87%Daw8?wikDm-Lx*s<!0I()>*o!PiW$uv&c5bfkKI^B>olfeN
zCd@Q2dK+Ke`|^;kwzN;MOP+`1{b9$iJ9K}6rNIKERxdjtd9J2wB^}<?#@<lx4O_7=
zZ%ZY8t5ve}c$CpJyhkTB?^DAv@vn|vf{ypVlTU`AL*__R)nEPP^LLpSci#kdYEmE3
zFt<lh!`$gF9&>x&vF+;N%00Ua=e_Ml46^Hn#>c6cd!Cz)9d~O_<<h_d+qhFzne{tk
zyB*T)pC95?q&Vtdg~4x^FAhHIDAVxvzT5BkG(9f{W}_J7t-wZtw4}q`D?m#PR|<ur
zm8yC@yd&1`YUP3_X>xAnC=`q9ezlVGI{DZBBK#HCto|^rero(w^Do}y*!elHqR%<n
z;?W^3^tVUmUwd9}(jaN@@!?JPxaL-CvfsVogx(MD`{bJry0{iK)IhEFdhvzbUcu;a
z+O0W#vAESP4WmsQO6B#sS(1B_hQTRmTxlXYO6dd4lvwFizQWRlxbVX;)Sw5w66H$z
zJ#k8LWH46UmaEU+6W3pz{p{2F=-f!Ub?e|gP|nS<{_RGm`H1%1pGT%a+~`fs4cX7T
zb<f$}J^?v%n^855Z@3?*7n#S@Dc)!sp6Pp<Mwc^e$VJzC8~{lVOl5Ewn;Fy^iuuES
zT5y=Opn*$Q(yOge4Uo?YT5(B_`N|}=^n+;lV6M~{t@}TEg_{nZxbHuO;Z3XOcIz%{
z&b=8{?=su3rw#LyrZHFjE63Rm-f1BTKN@hh8`W1l-kh7;(O~f#{Eq=Yu-`=nqI)0x
z;9N!N-gH~HJ{IOJ-?etQuKuxH9mwm$oh`VCL2ZL(VWNo*4Q};pB(r)fU&kI-`z#&)
zOv1g_y}S3^Gg()AUykCj(J3z;`}{qz_OrjsOkTUQdN7xcUUq2MR7}*^r|)pnYU}U$
z^?&!d$OwKoFsTuV9pZx2g&*^L^6Jj-4+dk~t+ZoYu}|vT3~!I0b~ZTLHm`}dbgagW
z;CKZ2>G32`+%zr<w-v|Qp*(q+;F!o^&hFvIp7ShF=+tK_x%!Q`@W!75BUJqM;dDCs
zsulaEAASq%*Pdwa^8DcZBiiw3dorK)w}&Y??di*z2bA^hZ~ic->6kC98TM;{x6|%)
z-C*`%ZO<0twTT&AK^2S*p*=BTm|eflVK&ysB*?$gk-rMm0QH`Q_HjXL=cB;R2iH=K
z@M0kh>@jy*uW}2W)*ioJs~C*ZsBF?cj7lR)<9EmUyKf&4|8n>aZ>RmG@bB<_;0yM5
zKJrTV@X0gj=loZ~@snpdU-Vz>>3L)9y^j0Y@#LTX?%&*jPxsG<`S#ZQdtc@y+usVa
z?>p^h!}p$+YrJQtpWFBU`664o7x~Jw@q154cUX6w{9%oI`O}_vRP9XX=lmNzCmL`3
zgWp`dVLsJ(<KwUJ{jVCQzt7vs4{7$pxp%tPm^k;f?9TRl<loh@Yu%m=>rZ>e6S>kw
zhR20)DdajA&8?@u@6UCI6&<|MeuvTU`xl4aFI_amWjz(nFz5U%*(qXz%!$Qe$GyxR
zru8z5LI8<Bs#ymwga>ECsCUxZk_!gITC;BtYDOLo-Y|Le2fEG*T7@)`_B?onT*xJE
zm^Mb<`417l{WtpfVriqRRiZb{(5TdEx6PSJWqUZ}q}sqs__*`EXYEQ&Ar=5wy}-f5
z#>AsB_3AQ6y42*%nictljS*g(kl+p{O{;akGOKOlc=+0Q&&)^N?dOLyK>J-&er)eg
z1qm6__G!-Z9RBHU*JG1#B`Uu1EAR6?k2lln?F*g;jCglqItc(58KuPAWha)*X;8yw
zm&hw*wnGVinVI8YW?C&Q<F;$T9#v3yf76NHV?-}ZRNPOwGF3Ei1<hc&v>^tgO}E>*
zgUa-t_TJs`2mJT82Eag?%<+F)42Cuxg5CN=82sZ+*+cnQbIZDl`%q3qAA%fe<<wAI
znSf6V-LMtb!flZeU#UzR&zsqh$Nltp%(GnyhsVkWNPB!1z$<#-pKkVo4Nw<}xMVCy
zg{BP>eY8UPm8fp{Bhb0NKd%V`Q01J0sSYaDO6pWwFfS#U57d-funE(XLM^Y{QwT{x
zFPr-Dkcc5p)52e$d4bF13(Z6k6<fR{`{=Q-r^KzqI^15u--2BCp-c}L`7u01h&62x
zu@+pFmqd#zKzspU1yf_Q4yZ;smw`K&ey8{;;Li)%U}4x?eV4(&%2Tpdh&QT&zVtSN
z(Gx7QCRcZa0Vz3!I{u7NIjHnI{rY)7sYVB1Pn1o#I^+Z9w^gka<^lrEf!e7dhD*4*
z4=_r??fh%eJ3qTv(5EBpTcWA(cv7NWORJ53?NM<}w+bMT1kGAtao5}{5(6AmPc`?f
z^Sq-D82+5EIRoh)4A1?}h2iKyFIEROol*Y2`|X|~|5NtxS6uUqb#Oe~W|Us_&RPUe
zPwO#lc6-gg2#w+JF(mOmbK0aJ<)TIS^zOf%WI_Vo&I+|S&4wH23wk1Jo3LqQ!dUF=
zJL0Ki3Ck=?oqL;BxoL+MFg+UurPM$QLlC!6vxj1h$XrGs4|o0h_h}laM$97g)bzyT
zx(5FOE+erl0yQmS$^~@ojK!a)H-xgtVFV6!`$SL+$4s>|F3h-5c+Ni+8?UAA>z-ck
zLl9YX5U6XGmW1w(=$fbPvZk-vV5$G-KP+ru2(!yKe+W~=J7r&TU!goOcD}ASF5f+u
zcgFZ=2cp`770k@5LL+7S8ReX>&U)DmiUiAz`XP{*=6>p55M63}h=7?N6@m@uRqFlK
zETLu-G@@>T$K(QWx!5Q{4%{W%FVn^@Z`wF8<Q9nTlO&)dBX3voAPruaJ7wCrBxr;K
z`PrlpZq&>=`_>|Fz&!`CkvN|ld*7}kEVY_oZrr`>6g(q^<P<pWPHT9j9Pdpyt_dWe
z0*TC-BVd_q0|t6O6Mw~<j%t3COHZKzWG;d&vgl<ay+S6B*(d(VgVeKtX(jxR-Xl0=
z-D`AmvUdxzN%&u$C$H{q%IpWtw*qof!A1-_xMidlY%_j8N(M1YcugtR%NtH|3mQ;=
z%2I;H`Pw1o9zhRYe)|IffSc#ddb5*3R0H=y`aG5f)CH#`*0qK1+sJUxsG{QwgU%L1
zwt6s#A579rALxXQq~GZ11xqgjxrAY^2Nzh^P9qeBT%w)zNnwiIg%51M4Hqd5oglAb
z?umKkQD!z<t5U8zzU-H-^pufMgNH&sEJc_aw-DD*x+yPl)8PFn@bNtOR}eqecF#Dn
zHPS-f{?@lQGi4S1d|{)fJS{Lh5eEjQyhNR^U*N{s4l;@YKavWOM?Q2nL$ZQRp5`#u
zDYvf0lI>+mO!t(YWEMBQV%b(A8Ic~H^<h06@8*B}9~oB|I$`Wtn1{K-28Xd(W*CKe
zf=$Qq3K9FYJ2dW|4^qWkdFd@t&nQo3)}CqW<+jSBAec3+B<5Aay78EB7lniGz3|5I
zn!H|C1%c-wn?aty)#b@cABAuhJOlW%s`K8g9cY~1XV&rq!@0+OT^q<t9%Kj<E1zAa
zOcu7xDlvy~@K;a%BA4NKV=t^Sh)8fP-YF803xEqrkvrrmyp+kz3DTLvizymx1pZcc
zg8qnXpb79QqA0_iFZ1Rnv9`TKJlQ8%XWFg`ccFTi*e@S_JXM4S@u=CV47WZ~YHhDy
zv?_Nr9=6!&!RSz{@&SuO2sTt2Pk2>joUbQV%SxFCK*^wCfro+E0H#|E*z&iSp+0ck
zyxQ-(!AN-3Idyeg@+I^1xoz`X`_sO!xC6hq53Y5M{QvcI|2eh4ot(e^rRJOG!Z#At
zu)b8h-#(rs3vM+(f7TE7`6<F+CsX#(bD!M5u{B$5RJ_s1Rs?ckE}7*`+4KcwI}8sr
zvA}t&6g3k5szwv>zmYXm1NW)G!uZ)Qo^u9fy`nj3_L+@})o0GTfom>0YGBJ$`}*wS
zb)UbS_lsBk9+(F9z%@18PLyw+w@dK1?33f|-g8?Dw*5EuB}w&~UEJ*_zwab=kUKeR
zcZ^4!Z~f~HhsMsUdTpv0j`5(!6(j95`X$!e)6j^x2qhA}Bs^$YN~A}AUjBE7yWOys
z9s;7(vf=Z@F+2ORd&YVRC({HGOp|i>Mor}g?Dvz_o@u|8;1l%NL^+9|Z)jUnJFUhB
zikE-%KH|!fzIbf#Zq<2XvJsZ_QLky9@t-?3?06%M(zYCA*vHecQ^)e&cONX)y}kG8
z)nm#`&-9J90JvStCjt$gsJ6mwxwy3}Rmbvi=}*j;{iwA_{ArZ_dN-kPqv+Hj4VgjX
zu+#Ym2OhMx<)$9Iy?5~RufGw#)K6E^+s$X3`mFzKa(G7hr<*gQbAw+x+4+LE06KQ~
z%udgK_QLo=d{6Xj62`gTJ=M9Ee!Ow5v-ug$XI*$RX}sjz{DX;l++Zku2Czc)a1nhO
zjypjqSNBHsP6VuVG^*&6QyU<6RZ9w<x=O$)tZJ?vkLra{*{IeJiIUA&cdM;Ep9F#^
z6b-IXkH?*K@o$ytGk>LCRGqP2Yx@r@oZ5Y$BX>HdE-LFz=L{f8>rQ8<T^ftcXOqSo
zcQr49&(z}W@7i|fP!7DU_bt?L_Hf3Yb8i0Gf98ER21kB=5ZYX6KS6#B$WnSAg$mka
zSg;SP`d?H&%~4CAt~6$nQMqGoJ5QWl(hHz)Rlaa)N8d7yuyomJH{*r^$20Y6laTqy
z-e7F8RrjBJC<H>wZ~uYax8QHTKnnka|DJ7Ix0`NKeag9DRyW(s>32&PndnB!lf&?v
zc4Ovw#iBe<i-GXXM6Z}P_U6M++gjB$8#9Z?_9{TBTrkSiSf!2i6Qlava}V;j#e;e{
z>C_igDIB|I!4eW9qF8~jv=M6;$7*}jYL$&vDT$(CeR7iI`-x!eR4X|6bG-8<RCVi`
zJEXbK6g##v(N0I_ieEZe-Av!ZGsAL&%1W8eQ0~d?ZKR8N$Z9J0jOrZR@U@q2t1<&x
zsc0-d^z$0jb#tt-7kirvqTHO)ywStOpebHZV7HV?S$YJQ<IHn~MkB*HOVtZ*y(;_b
zNdXhhdB>g9>Q5=RGghtY-goYIdK><84P<}u4P^j#bnMPVI~>hDn>1(2`YZ^hy%5r8
zO=Bi!tnJMiqIuNt&9`4Dw8$Q}_JcS~ZPGla0PF%dvPVlS4XJd3W{;x(>!?Z!4N2!C
zlY!b;SEK0Y!YhsuT;Qg-e?LTb=N#=$hrQD08qcX0ik(_=acFB_*}V}qO8&t2aKe&m
ztL5+9r`f^Byj~E-Uz|2dCGN7ZWjeAp<3_=4zS;Lk&;p(Vwc^BZy*}x5#-{detXJ6%
zCrZ$S$G{I4??;$M_co~IjgkA)?095Vke>Qzbz{9z%~lm5ZnY>vzQg5^UI0fIQk^#X
z_wIfHK<BAS+VrRXi&p_4w3Bx%ySn3|bDxUcX9n+6qn7|m)6%74@8N~2*O)0SdcFGS
z-)d>2;YPNW#ZF{z#@ga$=Ucz@Gu0Zb-VHP+)x7GL49*4Ds^|B!&U$)hDjMu5Cpgv`
zWOK)*>oaKfj$krulke`&)tS&Mcxs~nQ)6&jTP<aWmEEo%SN^eEk3Tta&aJoZjb3!q
zsVCey_qEzr9TSW=y*LE=9?Ouxy&Jci`xaXzK~%ZGmJOp1j`r%`y*`|)kB;VguRoZt
zFEDp0Uz3$h&-}8$Ik91f%yFyfr{8I5;b(I6X?!ir3-%QBSw=|FatuC-L!*Tsj<rTh
zpsKjjjt=c{+&BhtBCk4GopoK&KntJAC3~$+C$AsOZ#NI6Zj^V4?EKRkV&9Ehe!6hL
z)fYY-7ix!c$)Wu5u$r%@1X<e6&%Ay7T2<-EluE+Z0FK$oC=Wwrc39h^K$J53atX&v
z(k*%y&jYE#Nd~AY07e5;UBH#cB>6m{KK8L(fe`MPjccompDaVQYe^)*_ckxeYv!5M
zcYDa?V2LWxJKy^F|8Ie+|0ZbH|I3R+2f?XQ!Ku2iTXgW<^bgDUh(sL;pZH~bWRuDt
zQ~9g>TmC2$G`YU(PrGeC4Q=W7>|5_ev$yTQi-FM31Lg3u6o;9zu1hZ$;7hZf{p<&p
zFZW;ZT|8_)x;NJD{<7w=@V#*33?iHmz<0ti^1S$~S4>=Bx(o9d61#PB!~h*n<$Z}A
z^eZ?iCXTi*E~pDzBtB&LXT5aaS(p>SzJ1Sz<`=woeC3$~FF0vh4Zq+~B$%(}d-A38
z%1nlhun+qX;_XwN6q|7{=cMWrzbC%7+(wed89#A{W8kKz0baiN>V@}bAwuSyXVEzX
zPU61+WvuNYMGaz7uH}0+lg_aF%*cK$@(&mQ17+PWCrmZyw*>uaMu+xz^WuGkq_S!%
z1H1S!0N9$&Fq#60O(DfYBeEuIFQa|l<TnYNyvMERyhn0hK4V8adD48tdcsySMz0Z*
zW45f6dsdAt`fRw%+oGpo!T{pqAq0<l8h!uwKWJ(30epHT_Z{<TUBSr)l<>L;7oI<-
zqXjW2pB9F~#w^3O@{B^8DrKi`o@MOE6WBMnNC7jX1@Gq$Jv$DJWY@rHgSRgTBTCcG
zy1V?Fe}7IE+tGTIQDrtlyTQ0ac|)c<Cy!hKG6l#qoQ};RVEkQ<I^JPWjlc{IfmgeN
zit$LoI%Gne<Cx;(W+^8;S>*;D_<N4_jr||cfSJre%P|>l2rn<pDej(20t0}O@ke>T
zFm8aD6>>WeY?fzO7WjrU<n1taILWLF!OuhgoYWl;$O6Jxx#_>w4?0mu6#S-3;W;nu
zYu4ZfvwD8Pi*kW6kpEUm&YVvO2Jo)))8W5VHG9FTg!|Mk%aTYMh)PGyE4lc5id(N~
zv)oERfp)GO<=iVyXbyyF+jSVWYiw_{zv+j!r6Vso+K@F=xdz$Ds-Gl8O8nViQ>O*V
zR1bEX+cH^gyg1O-o%3mYWykcel|N~2`rP#og}fcXiLE<YIS-7IB-xDfhItfn_H)YH
zd(-^L@*!vpRleL51S!Z57~J7`fknOK?x;G}){wqn_$t9I;XR8q7rgiEN5KedaZWH-
zqQ=;E=1pE@@!zbkEGpXuT#)O^Qpa)$a6ST9XnBmW$F$GeusV1Ncgt;@*Dm-XOJ|*e
zetfoSRP%ws%5B~kr_*lk5B>{yXLhYLd^!YYBi6?NX19+hLTTg|qHErp$WC)(m;Wkw
zZ8kB>%yq4i+nCG33_Q0TI&YR#YIMvpP%rF6a6Q<{$XlW1eCs!E6NmxC$gK8{OUGH=
zV^AJ4>Uo}m6T%{D4mVfP9S!b_#{NQT&<FiG_YU|do!#wz$aGlLeGr<ixZ3npNh&!W
zU&L8pVNs0Oz}rjBTp5n`JOAc?XO|LF5^V%7EX&*^Of158UJ>Lp5}+&+J2T8CfjN|+
z2Z?@&1SObfpB@;ejDnqi!4QZzpH8=V`)L?3Hpsr~32K~*!r=q6e)8M$!-q{)gV7V$
zvghIg&t(1T7N1-{!^IuG_n1?Txh+YOMzqT`9hf8fG}z^|q4AAh;vnxP{&d7_Xs2{R
z+fbmjysce0Z9azRaQ|WO?jQdqf3ND(*@l!X3Lk(8uIRy#q$^`H6q9Pf7t}m2ykgpu
zfg9xz8*~GF&Z-W_F=P-Iuo5uD1aBjS!LWR>5)7X!vh(Y{f7boR*amrvVO`UTkXY-?
zqFL5iM3$+DBnc`ngUvo*d==WDH;0T}4rIVXMp?9Pta16mIe2#ihQ}oV2GgKz3Pp-c
zN64rwz^*d7UAwvOFS(GTd4+Q(yh_3Q@q7$MBvL7StL}s{%_1n>kJxq9apjWP*teAg
zNZc{J#FhUFbWESl9=oluX)w@bXUbn^jKUAU{)$$JLH$C_n^tlVq$b%8hD~fz(NUGW
zGaoTuGQsXHM+4X7Vwx`$w~C<oY)jie&-7^nKFB{B`}|pTS`XdCw(-i;v|M7^_{Qn`
zB*Rsp?JB>sg<~uU(k<vDW7G>~1|l)BTFLP29(;#!C-!VF#%l<tlR>MmZE$b)@P^oi
zONhNB0`&^eS8)fhQt~EpW%)pT|DDZ@QT|Y7zoH`eCg6n%bmcYRTkt<3AbQNKdI+W4
zKOU74ZD3{%DyU<I`Drtc&Yq64X-KyVCz>t8dj%5-s@z2ju)J~MuYcihg86Ba!D#=J
zh4W^QarYo)i%oZzwaX%QZn~Z-m<_WO)6A69>8oh<rYo2mBiF-vlf;({_P`1Atw`S<
zUiO@m<7(KP-E)U&4t>N?iE@5>+fD|(aC-b?VX}R9n_#bV)$g?1ZFWTPSbJc+jobTy
z)Ja`WI~iRw7rf+T(@qgA_duj9l*YTiuwAob%ETxNwu;|zL+5%JMmcfG8g>XCXLt=T
zGHKVlr%_R1vB8m^OxFhXz=kX4{=vshy+`fg;1j*PoB!7PjJ_f3Bl?g{gVVte?;`az
zH>|$k$4LGe)1NCFzij$nG6%lubjHoZI`xD<JZ7K&=C<*{PWV`R+R+`5I8q%hD$6w<
ze%E`96{_Q+Oc|!Cw9!v&ILO=lO=*>);88*ABYe4;aYr`!E|n<q)umP0CXT2|`!~3K
z7o4*W3FZXfAD&2L&$tswXV!7+?v{ym0!RWI46^$y9IuA5h3M5Ywh!=XOUV(+BWhsk
zob$Cfcc}4Q6&(5KZasWTZ8#o*F!j8sdM4ud9u(a8<7w0Va2g!>{9aXy9{|u9EMDpH
z_Ua|q@T>6#Z)CIqGpbptoJfs3J9f{=ch!*H(|Y}*X79YEiYE;YxKOl<XgHsa`hQ^e
zj{K(gvir2!`l9>WW9@sRUv-~RdmmJ%jCAh_A7JLKq8lA-68HK8QPR9T`aXfLMz?+E
zrN;j?y79Nik~=$E2z|_K(ZGSgclU{Zyg7s!Ry{Ic)u{z15qXaaJ`Kw#2G)r=Aw-M!
z-o7C&l{QT79W53tgPlD(3N#SLT4^NJ_rml!@^Jaacw^kLW2Lqm>JFCc2{UO_2e(Zm
zi@%8@*E3*TaBkZ6-s{Q;UN62rV~(lqG^m*KKwh?a!Px&)eP8<BQT4ce^tVcSnm{3e
z5we{#@lx*5`P{$ynUGBY`b-xFfG5wX?<rkUs6`yBfHI+$H(2+ciu6hDxg^XKqdxf5
zrUFP#W!&`ks*CWU+QhH@{9p}0yy&~I+nf3bI8E!L*um=eB1kchh1=m;-*(eBOMl<d
zgD3hG)A@sbKoAE=foi1EgC?lMzc1;Xv2V!(XROEYz}&b*CF!-$`Qm*aiuc!4(EL0S
zxL4WS=sl`X%>e-6fNB+^VD$h{d<0$${#k2quh`dML){wH>pi17=c4eMrd4uYwi+MV
ztA~~ae!6qe^`=rMJUr!|v6G$Nn@+gZiw+u)0o7fm3$6qDD7Q&PQ4tKs;TB<wr_Vh&
zs_p&sDAKA0Ol1^9U+T-<^=~%CB|T^z*6N4FyQnzR4Y9uCKuyeSbI2*ghgG39qUuoW
zuqpLPh&EOjG@BIIRLqNNvZ`PCznOa<_&AR1&a=BQq=%GjPu27c8!$yrHM+q8Mamoy
zkSN8DyBj^^kf!44AwWa4Vi6Ev%icH^Wzk8z-qZA;M*=O<B4~1#j-3lZK@PoVuPsJ)
zl25X0fF=`V*G@=9-YEOYePU_t-6ZE+C|b!Sxx4j!Ybbf`Y_j{g+r8Us0E79{(_QuI
zRn>dH`n^}>(P7Kj*oh`$<Y)|-D+)BR5wEaD(`5eYwiXx<)exYwo0UXsAuU9WpJfvX
z)~lV;H;YzU`UCV}88yinv)8;oE@)(DmjwyQXwD3pqhM>S?UbUNH)a`Q<vy=8DTCH5
zn#gRbnv*nd$m+l}okFyg=rbl|C$!fXB`>wSL31*P-qmwkTw$|b2UiSaYuE}#pc@+3
zP`Z+NTXorJo-e6rYF`zd`vv`sUfqh%GFBhz09(D~m);1#2}U?s0)#lM0Yqs{zH6qP
zOwwADlWV-O{jxcGL_f@dVPZkCHvov83pV$#F$u=pde@k5j_ns$W|JdhXzk%!5bifc
zXMYTG1_kiFO4fh>;m$b$TGg!jyK>%B>-oPvz$)lA9vU>8J2ZFCmsa+nnG3S7{;;>~
zI!FFuvtKpfLrugG;XrSmg$?)ScdV)3Y*U<ZSWLP%Pdxl%HE_<7n<O7Zl9O@p+=uh*
zU};>MTWb{3aIF!{TczZE#^g7nT=R~)XX<eQJT039(522|BI#FA>m$R~<fJ?3Ci~u>
zYra>xS7scTLc?G=?bd=fmX5b}oOQjidCU9Y(3WT_zICSR9Ra3wv*Uzj=uX_c1b+8*
z<Cck)jUnr`%9#xjL$|LUWodY77Z7c3<xzw1(Mv}#T-qka1Vs8=;d#mx-QYq29c|17
zxwFL8ED<>1Mt0_gd=A&XnjY7njgb{DRxw5~gN{af7YEaH&J7!%*>$CwWYdKgp4CKw
zYQ2$5SL@an&L3J}@^717#q@P>mtzcP$~3M31TlqV1+#g(aPV`R5CWJ%hViu=x$RLs
zg`9;7%v@r&^|ZVb$iO)hu}EQDfn?3}5wRMUuinO@lm^Kt*KiK2<5{c@!lo*g>c7y<
zm7o7{cta2=HTP+z)1yL--u}W3ve4~tpB|g}z~9Rif^yWuVl?%rM;7AAOy}=m932)t
zCe=@i4LvH=ZTdf4s@ueyZ;+{Y@+zCE|Hc)(p}&5O2z7&!b-2bA{>jWwi@%eT^|E-C
z1NE}_TO6pryF{NYZ|HHLUV;myxm~w$+1E%=TmCi)iVEKMx(>Ej?-!ej|37pT@IbJ%
zc=+MpLlUZ=P@SmH7_+3U+yLZ>CiJlh1Kni3EAXgs!oYO(%WLx=>AkBT7>;<rT>X(l
zTbr*Pv}*65Nnbq*W`!%?IC}4X|DU{m!H^2V4mNQd#E}9=0M9ozCY})kdGyW&!x_r)
zTy56~abfM<>d?&4MZdrnScBFcITKBL`_d72`LVDnv*t2Oq5}=lIXMy!nf5%!eryx9
z2Vb+0dt4SKR`*+bMpV6HUJ0$(jaRf6x9@uC+uTYS04Ifx2;C0l#K^P^6$e&$qqh2q
zhr?^_F_mMe6*s^W$*#EC7q5huNJc}C^sLN7UQvw8tYmD1=0^cmu+e2@r*0Jhx{;c9
zV(S<G=5@v))$a4numTny!^;txcMxs|(g=a8xKXe6ph3ApluPkdY&%*r<ide=rDwTn
zoW1`dLI!p^RX3AE&Y+d08Sxjzs#P7zuPB`RV7)5jzHWvmyup*6TgN!sXT^J3jYE;q
zZ`!|j$4z@&kujMxhhi14Fxk5MC}3e?5L>ViO?cs4-!!g8At&%Fh?EtV*cc(SSyIJ!
zm$U9T!G9JWK{skhcn)RVbKTT)<p<Reume4sN~o@-xTq#@Ia8@E+C&o=Py?!ee%m_3
zs3_B|NIact593G~^733td(U~CxV#a1fs-S1F2Nth?6G88OC@mPMqGu=2c0sjv7pU+
z1!<p`;__-0zDFif0Bx(zLTOKk_~)F{K62po<1Rko^t899HB+ruFWM)D{F7Mq)cG8D
z9(XR2WDIyqvjy4}Yr;}pkp6l#xim4DOp)877CbDc!s%xApqq=`3fv33v9}T3?B}i!
zP+G;6bURm}BZq1A)ag^zU=Mu<@`4pY@Nn`4r_l(_EjXp7u{87j-MM(B)I1g2FB%_y
z+D$UZFo&WPB36u|0qrP!D<HFAN)<x^jRxguI^F1u$dbZ-CtN93<J;s4!gNDMP(YO+
zFK>tX@~mrYceDAvQ`qlTsWCC|bi0#uoWQ|keOJdlwfd#1P-0#G>NdI5Mu;iSOrwxp
zwap;6WE@sp4boB1OHG^05)d-5A+)sddowL)dOd3f3KrsxJ`RGFXVlj3&zo12=^0o-
zrjZd_WwMUWEL90j=h#Kbx7({#<1HZ&wLU}2?NI7yqjE?)wecG{fCwlZ%_;Jyf<4wE
zNI(`>aBM+iV(J-a9))x~HydKcv4Uqs+_r+e^7C79EFH^O45qRb#|BzOO^E_Cw#zTR
z1x-6;ghmC_#Tepd(oiWk>kV_1L_6t7FN*<i3R(1<+B-)G+;+R@ReD91t5&9wg<u^+
z7Nym}NqikaaY*CscUp($HS-h~j7RS39g0va0@$=bG$6&df{2<jVS>-D^uk{m_*PM8
z(3li(X5Q*)yiaYZOW0Rv5j&PcEJ`V#p^?0bF1yE6Jnxl%|4$LfxH%q0$d|h+*oS!1
z9Y8>RLtk45nqQ>{Ep7tzgzpzb9fp`N108i~cH~e;9yA<1HRp9@qJd(gVs(oqUn*O$
zL3zy?FW>!{ATt3&J7&d9d50@<JIc$j&1M{tNFt@`mP#ooF?x+~&D<GTXKY&X&Fu)g
zVrtaZ&krVUFtb`{b!0{C+M8De%dT8>3-&t_hb1hkWE*LlTUL#x^eUFdAPO(v?pI87
z7Nq0zgprxUreb<PM2L6VW29JQB{*RbL5~`XECM_EQfHCCLDQip?J;jvMs{db9y8k_
zM~<1Wkt;KH7+yuf#i1(biPs#oGhMCFSW%!LxvCp1Tz~KI4Ge^~p0_extN@W|Ftm`k
z;9cNS)?%=ieg#egC<kAyAlGsc)i$}OpU3RU4bu`T^N9;JsI4B=X%H{ee;&_f5qw}7
z@{9jsO@+FWdxWO6j6t-eEjuTvBK|7MqYK9&7zsg@AS~&(9Hr1U#)})hQa6l-&;ku{
z0fq*PgZwuF8yzvYix)_*Zz}qoZ54~owj!$vgu6}~8b@c`O4LAkbXXm=(zh}wJn|_x
zkyW7%6-J-vgbn3(1^m=<GsBB%udHCNbD3&V<B}2JbD(s5^AM%iy~;J-{;w_P1Y|IV
z#_|Iy=$N|P%8QL5YqqJnLW&%u9<LtePV4evq~ruW_abWEk66PMTQ=Ra63wJv&=%#2
zBOfC!Rqm7zvb@bKr9nwAQ)#fC!qAiGLFN#x%h8tAj`c@7)*Hqk^3u}hmu}QU;RdZ~
z5JIoeh}MmkD4jA!GdoS;SA>zskE>}KF|vj!0^Ot>wW`!Vjj0Ebv(?!{E~`+z5%Pwt
zT!99-%}lhxo3DN7eU(LBz>Ch^tmCeodntX+{TeuyQgZ<6d!m2o`6J#i_RBW+t(HHY
zNHQr+Wd8V1j?7NBQdNi&x72#zRH1)jOS)OqU)X7Wq3Dz;%=lIJsuy0A;q2=6js7PN
zyB|o8%WQeX|9JT9)(1&yVELrfh@#fk6*rvQyZ22~ofnhQQN1!F{VAtL+bT8uTtxK!
z$sO;Pts!T6xHD3Hpt13lr#El6-I3cI;0o`Ao89g1qsOE#%Pm*va@J7el3P9Qj(29<
z>XokC|4dd$HkTZ`NYL1F=$l#KB<bbxJ<dI8(|b&8R>ws-FLo>Gw6D4+?aj)ao4MGH
zAKo~#y0zw%x2z77KjMryM^$>*8QJ(tD)oZB4eQC)qrThnGL#Ts#F5FM=QZb_l9(S}
zm7Gi~g3-kl2c&;ae$aK?$6I^9x8WNVv+77pSAebu-OdsrR|6&!pWk`)uZMLRb8xcw
z!-9mCb%R;8g`7`QcR}yR=#_K5KVl5)9dIt6hwg-{Glwjrb{{aZr>tP=U-XYun?pK+
z1D*u~&t}&yOu1;9-@!Q&E*EbORo(XT(Dywn_&lLl_Q0Gw{=zY_?B3>_o|@e(s@;Dv
zB%_b+bDnW`O?_g#Gm>?mU9L8N%@>W<lVj$x|6v)va4ebe!>Qx<gG$v7tL{T}NL3Tn
z%TpWV?%}bkVU_43ukft&2hIU_jLM^}OZ9BNwd8IRM_b<>zA$pXntwjN;6Cgee6QM`
zJ@srBw7w5vD{8&0x{X$?Xntd(P$Zpb{q<xyawp>9oHyQi`IPkbEqu?GbIwWUohr%P
zV-RwpgReXuKS<J<?yqi4hRDuEgv`mEhundy3)23qn}+Xjo7L&*=7LACR6~39=QO8D
zmBdu+my3;<sHAV+cL!d6DQJB@8CaFX!aZ##Lq@Yx30t#UTq2j2i+6?AtwMeq(5c(_
zSr3BP(o^e$7JQU4$j=>PVV(quU$@6hawA%(Ta$6U{*OJ$%X6yUx~+nhb}Q5(<F4x;
z`VjF%8Zdio+J6+P+JT`HJL|ElgW{s)9VsZ3oSGTRbq6lE9nc_M;t@*R1(8VO`Z!dq
z2v}%ttZYq81g&R%UnM(iSw1k+4kNzuqDo#Zvm9x<G8lCoCmr%00=f5mCb$i5)EXKS
zQ&rCwQ^!UralyI_Rz!)LyY{i?qpM{1Js+rq_In9NtvoaRmv^2vz*4@O%($RVUvXcW
zPrhFN3c1p{|A*@hK(-=HSak4TZu5fH$G5->dXv>G0<7+Uf_1o-T|PLZn!h@>!7A0)
zEI;+0mgA7(4`4LMpt<GT$UySmwpNZOYX$JA75CN=neFLB2Pq7)9a8j}tlJV$rW_MI
zMm6s_veu~QJa2R4(1~7lHu`TM;nv&*_oWWX&=4Q`=j)BLt~0ALq99-DB(Zl^#Qxgs
zTalIF=}07Gm0-5Dl9Jhs{Lq;Q$3S+i=I4M`!Zpj?sg^9W8;SHV>HN>SKy&XU2yFIN
z<uDo6f0H6C?CG@5_o6$S=fAwB+WfFen>(6N)0mfO{nBpC0Atk8!YG1K=-Ztz`igt8
zT3L2~=@L?YqBCN9U#iO3I@;n@D(DFC&I?l>d@T1?xA}SQ(`#~Vt<=lAMI+Z-U=tB*
z5;LIQB5}JM>pNllvLkX^tW7f10MaaD3J9eW4_dPOK(qzw)h@Qc_@@-N{v^rNORa@K
z68;(&Dcog%pGl)xSF%ack;{868LBVsG|#%fc<%M}cp1d%J?|a7UftP!Pox74_b=3+
z(cHWL;0@in19bGAAgoi*&H<F3-_mJ4`_1<hg9E#p3ztfoqV?>NgvjD&0nipM-*>>6
zsKd~zOQ+N)K_7t}XU`4>UvWDCXUpzDpFbkyC88?bWMNBZhXVw*@Km1IxOHxGMx|+~
zSOmAlT(g?D9D(dqU*jEl*8wen{Uj+3lYgi5<BTGTnUP@cD@S}FDw<+qh_rV5W8ZpW
zo<?YqC2r_0YH?~8(qN=`HltU6ok+`#)M1}}Wx?c2;RL{Ed{{M~e}68WvtO6~p#uO{
zCk*uxW4FfH!+S~5Sp`Z8{@8U@vT*B++g)#T3E^XOf$m)j8&gFaa;reMfG<wh`<jz?
z=DZ`NE|A<=QMWe%5N@=dNc$Ss9yz?SF+N+P&$~NgSX8t1)Qw(oJvVqhS{vB8<>QYU
zSR0uS(%KGfVq>}%S@P04U|CRxQdUW@QI_=r$fM_E;JFqKrPmqH|AWZQR(mLxr2>*i
zvYLGfeT1hK8}a*zxzTjA`c%Wv7+Pw4(I-SC=yXgXpqnE*4UbS~9c$^XWI$$MHDG7G
zIC&Ohs=?%DqkDRHFhz7f!Ea7F9o8);^V+7j;&kKQ#58|DvlGd80OAtYxH5x-%y8hc
zUTz)3SZT_to{~;P22$PjD1JP4C^Mn)h2QxvF||%VGW`ElNa21R+W6l#F7dyPsrA|D
zC)6)~10K<kLmsdphkb#E&Q!5#;2Yie!PDcJhB1ERNBa+%Ha2@MWbX+laxzad80tUx
zF<HhJ+Ayu8>PLReAOGl$ul+xJ#4P=x<H}dx7!#MwAVhqR*(Mj?o|9~4AGAWlxIfIr
z0lzRM_r{ITLNTzjLZho7ZIOX0Tr%FLvUtfe(!1|UGhD`;s#~khiP4_PK8??kWq9;)
zy4_vfZu@c0EsfgtIEaaeP23pPv%N#1y!M?B6i$J*^<;n#5wPrM1|GDDRF}07-mLf+
zSll{=nuIIK>ag-1yJ5NMRukcMDVz4(B^Zv+byKJtkR0hd^fgU0W3@QoT5-kNH*fy<
zkK^2ED~uYS1(m2e6GrnS%h|wcy1p<siAD>p7yzVC7UI-wI)xcB4HZW5ON_$kRy<+c
z__{@y8)KnSVd@H^7BNZ|xXsO>3hg-A6B17_p+fBxX{Z!4|IPo1hzbIoIxg#z&`Ht<
zt0${&>Spcfw7sa^ZCb*^EeYB0qY(#>hBp&$*T~VQ3FguTW@^l{IEV~DP_%H6NR0oc
zwW{}~egia@3}1LT?pOVM8UQhw=~)@KQ{BqWIKlRi*Y*L)r@Yn<ZA#VjEAoF87SeE3
zR^UDbtgRIm#7<dXUs-griizxRoWG>M$T;>YYAg{UF<{r;{Xt^|7yN?6L2#>gyKZ?w
z=7)a1SHW<PnGJO;#a)$`764VktZUo*a;wcO3oilK)fu8BZlMHHb>zOV5qlvT;j9*_
zHRqVFs;;I=dtP#{1KogJ5DKl^@TzaV@XkfA+$T143_vmOXqYcY>^Y;-@ThFu>+J3T
z_`pF-;r>8Y$O_J#{b6{?NH1G9i3+l|X%OSNBJb8|DRW!QODw2^Hw~NRcv*%>o=8lZ
zAhZoXo(c^eK<VMuXQnLWVI8W9iO?$7OPLK;rkkd%EUH632-Yoz-e5GdAP3NLN%QG;
z0z>vtonFIn=M!ZOByhCBDm1hNfd|GgPk2{w0?sf=wJ4;cc+)YyIP!WrDTt{KbJAx8
zH)nx{ssinHb06N+=@;@wLjECM=s^b<jORp&g(I<k$6hspm}_&g(yw_I+|1`B9J^Ni
zbUSZsw1P99p|bWOy>kg_au5CL3BQ{I_=-^+zJ?w^;$tNTfl-50rwZ#G4$7yWcmdQb
zN=+y}h>$KDN9Drf>(3lg)vDuWAV)5u+&+k;AzpermxE};9(9P@-A^RZ;$ZlIFt(Rt
zWh+}2esa7b!u%-twaTYtfl#N3PGE%rKnQoAE@(yt&(SiQ-5NcOys%6WQj(@;cwq%v
z8v$g)VW;Ds^uF)ItTWhyREA+61S)5{62Y|Gq&D8qFy)u9EtRgM3Mh6KGo0sQ1i*y~
zxh|~AFhxE_sCUiED$}Z`7uX5;k`vL~x-s}-&*krlqG}xSR-*gHUSDCekcu=tx7;^<
z!WLY^*lN0r7Q|N;E<+ou!EZl2YW!T-O{%H42f{~KzvL*AGg-Gd8^iU=3#@KVwZ+eC
zUevxt2dFQb4x3Rk0-K0I@>+7DR*J*d+W`oL84yKh!UATKkC2wzVxDj{!t=z}*Lal(
ze9TqO3P?JbvFFAaQF3yyV^+Y0&>qb=qQ0rtFlIO<!R2&AdKoMCUbau<Hq$S4qlN&4
zi5o!mL--T8GAR(_E=1RKo8A@I+?s}#%MyrTeCWxWKCVeOUjl#`T9`?dstmGDBHLEG
zuix@uoLQ++Sg)F$Y)<A2Yk|kOdZ9L;Vo7%^xQFE^80elw>2tGu%0$BX05(!1I*zqu
zsJde*qtMz(mxHioYcNM`cMEIpcNgR8`1M=<VLQqnwJK4k&mN~lfmyL+oC00t=tgRp
z0W_wa8IkE3<gqv!T7ss1K#hm;=8!iJg^G^jsCLLuiB3>gL}0{e!9)=_;nkz!T8&5E
znq!r16FZQKuqF)1XD4K+W8pS-nDL`9;X(jM8=3W;6QGb#VhEFVf@u5{G4$Q&l0&JC
zuZbK!r(6)$a_n?-v7RicT!6ccWlWiZwY~cW7TV_7w66i=wKsA9=zn>m4mwpZ83Pkn
z&l9mWSksZJ*QBg9n1cngo%liS76#ze%vtmq<mLt6FDNo?!UbWStMM602C?!_naCVG
zw<pj5Y)JIg^jZ{YElyjQK;c1~ELdoa*>8%Xxy5uVmJwb1!_NioqLP(-wd(2ox_jo&
zsVXUBXNl{#pp#u$Mo)|&%xTGGbhIor`lpwSVbNQ-$;zy*%iJM`&K0|G$=14N<CliS
zmp0Q0rfn4m5tm@`Nh7&!VD3WhTI0vQHL@s5=j6uc28&nImMmT<b{=xw!?rxUVMJ{k
zJJo-`*f3c9Wi?&A=flowP1LH}?YBAii~VdHbCF9=?p?I^FP4Mo(x&vw(Z=v$`{4U0
zo?Mjut3~JVaBWk)8s2Vu^U1}nrvI~Yuk(=H^{|vLd?4BSQ;Tqy+4f{xc~3GFl7c-t
zFj}&APtC+fB3tkLzPw@j^u*Az?N5yh_0)b=azue0O2VzC_n`c&9GY>5T)o@hJH3n1
z-7}B;*19bu!+q$kr{&1}kX%x4cVAZW7wq?s$Z+dP<^P*e>)lEgAF4eU)^?Vz3$Vfs
z(Vw}6crZCR7m1?Sm5hs}deJ`ES@rkbyECo-wmo}wY-U>S2>+F=Cm&e#x7NzBKf3W!
zIybP>_QsPTXIuF(^>y)(b7>&_`l5X(B>Q1LZJvvRNuoQO@|0Z<TT^zuPc@ffe?6mV
z9pd`vXqlZ6rbAMicBHpDv-dggm1jPFHXSA8P;Q%llhWBzo-BgCvF*Sh@99in(*LBt
zMI|Hsz;HTks9!|SiiE0sQj~FTEgp`5K9sU>>Z73}pDL!)tKYGpa}9k9chjD8iF2gD
z<;DaL#8h@(Op^vD`epnlquk@JY5v-cKk{douf|*A(s3hvr`Hg`ZPCH&U)=L8wdbSi
z<!W`4eA~RgSlyZozC~VLXsPLKM4z>$-#2ordP3Fe?~=FPPnM`VfaX5a{k_)5@w27*
zQ_1u2nr4se5b51=GQGMW4i6n57BD(Er{Osew7B&>^`$JC-_~_D$+=AzoN$+O!Fh2y
zc`qQt)Gqb7nEc4luEm|pxa3bP9p1O`R3zsn;_b(X=ONe98`9w2BE8%?a)(I2QT8W`
z={Ij5I#Ip6p%l%;`s&eGZg<uHz47X5Syhj^$)(|QwQ&4Y^o!j!n@Gua*Y7PPgWDAR
zCU2yA`D32WCU*JX44nkKJXQx79Qe*of5jR5vB7G6;<L4*0EnHE`MXQWklkaAb@guR
zBToI^T}CqwT8|k(0B>3nyF;wvvfY`Uo?9Cnm{n<5A6gP&8}#EC1mL+i*OmEej{VI#
zq_`a_y*%+VwX}Oc6sGq1F-c6<V)_TWa-L5>pt{w)GAquxF3_Sk`1GHwZSLsrd=H+R
znRN%gR}=&Lzw3Wi$ZziX6*-fh{+N1-LVtPF=6{<eX+P<UUb5vol}L(LKA%hnjRTu?
zWMgE5r_HG*+lm+Z+DXkP0Xz&$avdpWH`{ea&b_nXN~G%&mk)S@y;74?{=0rITQ)Xr
zn!DTdjwHowxwOBSeS54(&huP$dVfo4GTaabNMy1Zn;N(phteY7*V+&L#_Jqno*ZW&
zp|T#g18RT+_*fd3x;6Io-ZJ9MPNpR68W@7}wzsCylOuMwabQ32?!<;|;5YFcKwSMm
ztc?1y@J4~OS`eJ11WKD*OO~WrBc96zt)X@@JC^}V-YmB!zY_)r&l#JX`cI<nKNB?W
z{YWjlG)n&eAq5j~lr?GsVGjqbVmmzWULe$RYu3FhJTP<X(A^(whe`3S>&^hV@0#a%
z7)ZYBUy$bMM+Up|$r-T4bK>+p<4*IOPZM@1$^kiMKJj957_@A^GoPHFvq(>-g<LTw
zu?}iB@Q}ZDAc-ju8R>}PtDln8AO|0B7a&ZWL;vZb=M>o9ZxJE)GbMAmG$EVIN63E#
zTp1i3BevA=rc0(bT65|a>C@YtmsB|Pk*~k*6B3@O%c#GN2;14S#PV$=jpU?2h2;^c
z$n*|jYfD>9z=@x5iE)Gnc=_I$?G92Sz;RhLXL#b4*dQQ@6^uNKHV`>L&RuXnW=OJ@
zYM3mnQ%Za>$08th7i_S}qNHh<jVITnL0L9hGX%G;F@TwU6B}mtv>J9>Ui<pbyy+}c
zJ`j_LR;w`2l-V8liZm}j;&;*1XYY$#l=r8jfmP?r&b)QGksh`W?53x!Chx0d-S<py
z7R^5{bi%3kD!k0en;~4@B<s7hN|af^K!y{u!&udpH#>+&U2c718k|>Mvo{j2>5a8y
z*4^8Z$CC4tkU_tThEILx$XXra+}w4Tr5#wQYgu!kRmk#Ix39na=%FQ_tb9+Trg*&8
z&EJLsF4TWn?q9h4nV}JY=AX-@-+Ze(u){h21S=C$pD^y;SkO_xLnoYi%wRq-Qk8XL
z7tZV|O#Nj&cjYCL9;S6`Wg{5JoIHt#kOuR8S;4vz<pz>Jt>?Ngu%EW$d?zUeI#|0p
zXB~ICP&mN>>;DAcGpQT#KdJ|<naP}UZ$qUFj}&;5I=kbYp~${+c+E2I3w_ogl~2{3
z7&`3+&kW_HZ)fwX-D)+2XOSfh%$GLaeH#1S$bp0t4(AHHb5}yg8W4H8X(LD+ULiwI
z_ay7r0Yfcs?8A`MuAwp7#(D-1wCV)nh9A^ayY_0<u3;AAfO)Ts|G~G?#=M@u7S$GW
zw7(BX5?YW7byVd&)|Htv3SUv@wyY#Q?5<yh@%&60(`OcUVd<@P<QFnf_<M%{0)XXe
zaIlXh%wW@6T3vgsJh990dl|ptIV-sLb|an!TAu3zM%1vKPR2&`=3{y>DY%yfrFdIZ
zeW!iXrtJTxIl=x8?CnRO#NYqX>|~&S|Ml6){*F+~-z060KA<VWVE{+aHlusvy)>hB
zd+9@Nyw-m4tDm%S>NGdWNpZk&e17nI<MW=AY(yX0s?FKI`@nS7y7Su615$9b;#c2D
zU;E&P{#T#a@`laQIp&7zcb{vYJXyFja#WeF;~iBaPIfGnUmHoQOVuSKI0e$y3)9Nd
z)$Ed5wKEwX6OEdaH6`nlSt_o27(1)6(LLoX6>fe^$@!YjuATyZz_1|-Y;qvYykO$V
zOBqg8GYtmVeTCc@rT|JRTU;dzUvj6XNn*`LFrDksPk{y+M#l&|vz#At7Xj%iCJ`C<
zQTV=@u2_n^$cttk<qU9+)I4TZ4$J%{Jc{gdCbX;;q!es-<eb=9oT@-H1bLDm!ep0l
zE`o4E3wGRGu>q5ap?vUH@}D&c%2<}Szrh_|cgQ`u&Inpgbv|^?RMl3wAU`hm=7LN1
zG;X7b8`{7L%xmOMl${6E>0B0`a72hdVdrD86*l&n4lAj`@?@2n?7<CZJ&4{<OhvGG
z;DZ2gf^#syZ|#YoZEkZnxmD@PO8VR_ua|As^8zcy83)I60UZ@N&7j!nCJgXMm6&K$
z5E7F}4wj$+Eh6SM+gzJk8!El6I4aX=Y#dU&J^`&oYZ+0Ld1pJjK;laywpae*s})#o
z2#Qx#{;#|W!tqoe+DSAxo8wSgfzHGc<i`bhvhj$JIs6Tcpz0{MHd6F-z>!216)>8H
z3jeCUxsZP}r|YsrU5LnpEw)lbf{NRv`g(Zzpt)Sv&e0IPsvI-RHZsE{BiMB}Y$fiN
z;z$-iB-$bF8-93>Qepks07NTf;qnN@ax?02^xHoH+H1Np1}^uU-?rpwatIkaIm_Md
zfK+xnq1A?=NAfE{HkU$U>H%QT9%e;N$Y<B9t|TZ4*$2;50b?s>&nXXbM7L~T@S4??
zh6a{yJ3}XXI<r?CCCh*i1?O-4KcPMa8wL>K;aQ%R=+#l{jH!vS1zVdJz2nA51@nZh
zbNkUm+`jjLPMTAIF=m`qJTS>AiHpm|3-7*}2uXd)p-v^4N>if(ELpWG($d6}vYF9Z
zNG%0A4-uDDh?Kq=MIqCCPce*RRsrZwUl$@<3PcMw!fnZK2mS)0ri&nr-~IXZt|6*7
zn%3iFZhyjoWY-SS6nz>GI_=nvqs_>rd!??k4w(%Q2H*$YU5=5kQ?M#=4ssqRi3;E|
zN9zC0#=o#-dr>%|W-tz%kYdn8`H3nQYI}9Ndj)IHR)F5<3MnaL6;f&pdKI@t$BY@2
zEdMv{GQ6frxC^MA*jd8|Znp}%Sb!Q2TlOrZIRFiMqn>spdYS5~7{*A2f%)2}<Fg$>
zCavL4q~&dCEO0#zx&|<*0Cz)5p_(Ybb_h|$at?voQdmBHtgx1e(zi6tEu>M=Mna##
zG_1{OI1Mr-VilN5k;@&~lP%mD#&yK7+U5qIv)?HiX+AjYny%jh6%55mEDln%ZVb&)
zf*E-RhzL^3Ep!=}!zl<)fkkPYGWZD#7M!4C?0kgb#m$ad8cwRsPT5p|F`HAcP6M>Z
zghj{5`PMKLjeFS0q1Vxyov;2WpcqV|TmaQor%$BWESDJz9o4-OWL#?!(I$bXXiZ5N
zy)FUE20<>q5{6(z_`)+`g#eW>1|E!qa#AH5Sedhf7J<@*byr*wT6BE<OJV=$->qj<
zLenTun{oRTn4rO!VpA%8Xl@!H9bP~82EMvev)jPfh}`WJ5dEr9R~mC|42=_Zv_g+{
zvvD?aYXrZ|C&sTMEmc+TJg|mp5Ut3?fv7aT&XES|dgQVKGsHy18`LSL^+HXXWC$(1
zt~cBEx|nlF1y#i$6tYN^z1ELef6^CvT(!;nHm`L=TPzWNFjU4yw19#u*1YAY%r{x<
z5v&9tPO2B=fXeNh5pE}Xbx<+r)ICKoj|RYXC*{U=e2L&W4%&op$@l9e;V7~kPo^6C
zn>T}wd5FYNEK$v0_s$3A#xTd`nRQTyKEiLf)uQrBkv_(waVyx%9ATj!ttyaZgoL~T
zyJvxz$wKt;=@ivst(E~37Lo6=47@_B0{Z_SxT}ta@N}Y0JLu5%v`+|Br^nm?H8kw|
z#$TV|l02T;;PVy4i-=u`+TQp))rJV!)>!3Z1lvrVm=O@P9ysF7VZ4vLBqE+bs@eb&
z_Pq%Pup@4<$+4wXj$C`G&dnx*5bW4+E71dP<uC7F-TpLNbzdKp#~yN@TblB2vHgd{
zlq&}p<sFLOV>MA;mF1gYvz-&ZJUnO-`8YUA&Z1Mz4gh88X1|5?J{OJ0Fcw<!{i&D%
z`rRhv`xosm6s5l_-fS|}?hz+TzMPEi6)ig`p0f8HmRaJa<&W5h<$-SbIXk?=-g9;I
zu-#Z&Oj`aLzYpP;lP&iAsz}vf_(?}K=bh!|mMx(hU975Y)#Kq$-)8rZ2zkq<+eA1t
zS&pB-BE>`US$QlxET^O@PcMq0npgz>8fqL?jn<Ma#-eDQ7l`PlIjcSpPqj#BT+fdN
zLx*KezBRpCuF384tziagShJ@czt2y@K1QR9Vm5}X{rqV7yt}&5UptI{JL1gM#30LX
zVmkhYxF;-6%*@(81PA3w`)DX$*r}3%V88mj5YYq5V=JHI^2A-yBOiOi?yz23B3sSW
zM?gR(Ztqv7j~9{*Vs~lMT94NT^41IIL^pgZm>4p;`fp>dIm3A8_u#blbU3#j_rhu?
zLjh<S2!j>aYXH(R9j7BSls3RQMYwo3&@__u`!6vvjCBAzx*~lsP40qZpzmZsa$^b5
zzYt#kn-4r_Pb`*}YT4L_YvBujY!0qEr$6dmmtZ-+_7?ZT$V*Fy8#~pl<DXA{euw)|
zcJSz1qAE^d5$NPiR%YKJvf~<;$iDfpp$S>7w;m22BK7%juAb~4c>0uhZhyWWCB^h^
zyZ)}?HOA?~Mbn!dySkA01f<sL`zMB9REHaT7Nc^D4QanNRoz#;`ap7*{kZVv?!!+#
z5Ef0~y1y*q_A2*QQDwy2dU($|9pU*ujinIYP65{e_L0p2Ue~$d=&uNny*2zl-`0#v
zd#L&oYHIEd$%S?opLWa&@7Ql1xgcSnxLazD|KUL;8#`RL>oDYAAU}~~rrual<b!14
z^nLWE&?w~`4{i>zBvUc&{yV3Wx-^bF31k%3-%A%$0IW;AnyzPX#@b2aI|72)k%?mZ
z?fMaoJC3|vBnwTqjG6F|Gj-I)x%T%9*>&EelIm0Pf)lme!I#ov{@PdmpncDTecbs*
z`N)Q%GZ9ndP+njs0;gFUtT`vtK&x81TI{r{V+8JYAuSt%lu8ODOP6^LqTXZz&{L0z
z5j;npc_IjFhIgb4`u0Bd1^Fe4S>NTFlLvOoLZ}Npw-#KA$h>?1a!iG-@v&(>FZFq2
zuORRS#R9P)el-lut;y%~8F%q8RaGNi;lj?Os?_g%tUU$nSbxu;%DPj#%BxN{FP(1V
z!pKFZdq!0^Ij2AER<oxbcP)rO@bK-iaO%7tY3Rdhes|QE074=_&@slaM-t*N>-&i=
zewcTsb)u-bY>AN!wC<=~A<<PX^Vd7|sV7SyUAK=xCVH1|#&w{_ZX==rYf7HRa2`vS
z#Mr^2v&mU*FA48N^>Ja(-1kR$r<4fyZhP{81f`1yrc+M=Ic{OR=7WLgpscYIpj~BU
zx3z=u8-kn%xnj<?E<3sAA2O5Af%kdJfV?<6K@vAy01Z(2Cy9!zXJ+>v0M$@qX6M-R
z-~i04t6nmwn$K$B&LalegMQYmd1pm;k2yf_duo=79q5E-dn8DA*&F=!|F+&Sjsqb*
zTtj7x#Tt}4s9WI@`}r`gEs3My4!1B>D_Y&W(HsO15>V@kg@%MoHaY1Tr}IH;ZW@Ip
znw5kw<&qVTNvnAW)HmR$(b6chG<#yqNg{w5H@Xx4SrLwrjO_uBpij!!q?3_(U*D84
z>_pU{stH9pYgn3|f6^Tom!0eX;19{{l`Lfb$e_-S_sd#Cy8|xh>>2y6*23vC>aOP&
zl7(B;me%<%qXpfmPaDk|jWnfWi@Q@bz@!BQNAnlzf{06D9NGUah;}8j+!BbXG$|M>
zfOMVa;WvvknVr=;D;)U9tssKTU{}v4|11s;eq04pj|<{a?dXL+PA2^{@y0@AY?Sto
zaOpDup;m=4;n%@%({SKiZNMD7;QZSq0PNrW-)|~U#a9+S>_qN!3#R8hMqbCAkEOzE
zE_`WlX#c_}?6-xFop;$r#3YwKyDRh^cbbA4Ox!*U<#bXRrNzh?TjN|w9E-Go^3q?J
zXT_1%A^9hTjQuBxN99@bx7lx_JLN*2`$A@1p8A;GyBZmTofy(yprcaJG|-~Kw)xMW
z@S%)4d3Klh(oVDemw$E(N$j_nV=&Jusp(@R4Y}5dsBI2*tbIG(DrARDC~X5MTt!yW
zVT^fg5C$xYAWyr-ZDpzeE{0J6{d3j_AbW7M&8!Pa4mU(%v|!srgmp6atYp}XKmxAi
zMZf-qLt%kHy40L2n!&sqig~cJ`?r|BFt4;Ano6?(&);Gnx*qAx2B8BFvvWj_vaU1K
zo?e~Pvzb#^8;~MjPiiof17@qMGdlNKUvRJ6R>|${aDrO+^HyP=y$mvQw1=7L$OP!v
zg^TL@t@Z!-zg-0Be<5f6|IG+eAh2Ep>7C@`|K#yg9~yop)DfhAts_VY{XBi&a4+=p
z2f*33SJV3Y|9Rky%ly#Z0DpaBZ-5_M<i_3r|0!_x(vxdRg!7}kw!i%fWGq|E(o^~`
zCF=l@Y(ns71}uN$SNDENM#hBZ(DW+A8Vhk2@MSCJjeQbuiyy$bD>N3&6krrohTvUt
zn3We)S_4cvmN<|6KG8Eje5618;s?*Q)vFH_uXjY+l-0+p|8Bf6j4P}s)~AKhX*LWU
zt2T0?ze=VW``EM~RxGPw8RO_^e=`iM*@BtE87jCTZjb}2QVDZ<7cCtDbu1)zSR>y~
z&G~R4wEK+ZEDP3`ZqA%c@t37!o;5uRE8?nb(#zDaeEIsku`krlN2gabmq*tiG73Kl
zGhX8g_>sNMB6==)TZ05fR%Qx>738G5$lYrY@p@cj7|aE0g-`DlIJy-x1w9E(s4@XX
zgf-w=fAr_Ca{%brY85C=Z>|T;09Tocf-I?uDYKqz3iv=2gUSUK@hudEulIyj$X7&^
z4=xJrPPEBwm6q3M!9uiCW?&S2hlXQA+;qgHa>mbW(N&@bu<Y`cRVQE%V4efVfl=Yt
zE|S%zqR|kJ6}eGkRmL!9JSgvSHe<UoBvs6j3J=^IUyAI=d`fn=qSVwP4kmRD@7kj;
z@ec%wtAiS)U?uatM|~G4a~VepXhnr`$RSCA0~9hoiBm0wezVRPoO_HdsEBvVFK2;G
zRx6bGDADV1zz~3L4ZW9br30<++F$&y`o6kmL6~20j)skel=|s(IJ|{;PoD%(&1-@f
zqBFM3$H2l)(I~Y6oZQj!2b5%YRdmjY2QCV&)uxfAIO*F(YS`IPQ=@=)zIs~#T&)v<
z^~k|D;-?9!Kq6nb60AJtDc)^drfeMxKgnQS2ptm=G;y#WfV#L*;Tp2up_ccV^$sn@
zd;l;vz6v4H71ilguV~JjZ87k$<C(?8h24=I_q<TXv<EIC5^d8yJrEp+@g2|7?3FO4
z5p+4&UIK6mpItH6APbZ=1#DH&VrWQuc46RWK^z|?SAeBQ^DxGnHL?Il6A!M&w>`7q
zkT9qRnCNT1dVKKn`U&X*=~9{o0*u?cCAg(NS&LmGnEa!`o2aS&pOJOIG-M`wDufEt
zFPO7bj|mr8JttV>wEDuv+o#^39pK)j3ZPC50?btU!jzkbLN28RL}qfG9~?cbaNLBd
zSqW)kp@22eoqhVQy{q*exB;1@rcrEkkq4C5cYtr;9u7pzv8FgRnu?=<M>Si6Pmu9y
zTB)NozBx^jIo->_&lqDU7F|-ylFp~e+r+R5s8P+6My6269`2&cpsK7n*8WjYC9=e_
z+rptgf@o137+dhYml$`XhB=tb$%jgMWBO^rjfqioXwUu$&(QF?20@Tz1+6J8kSWhR
z79##b3Q;gh>jCh_;Q`G><|p1#q2|C7TGEsPh3urd53@IWw$*f)y(!$CCfvqF62=8Q
z85d^FH&u$=s}T#N8$>4c)3h?$RksYYJvgx5UE$Tk1@Zz>>b(5<U*|gn;gR$!8jqsA
z5yr)4!54MP<6byh)zgE62cEo4CPe3Ef5O(ld+Y>{n&jaBDbR`*J{Gr%JqGkp_b+g@
zRR2rUX2-~=k+-N{zILcTzby`@&>L`lnT8~Ol=caM3X{#4_5gTEN&ki1Y;IIvS2s%&
zp(y3zjcI6#g!XNE)U$5Fs=c8}i~+dJh#Ej?z2VWy(5vS|7_z)D6tV_Ss(Rj#RlT<B
z1GEMd8?3J$Mf9j12lZe?S;;v0Y5=AJ$0PxWRVyHVBp!0{93>OINisyZ(0>8Q0Jo&w
z5q)4?){VAQx){2TeDx`^p!Gnou89)ZX_vt)qJsraiU}4lrc#SwtGKAOyJ>qNnhE~_
zZ8As%qWdI8Otm^Npcd+lXQdr<!@k#8s6A=Az@dh6pZND?hoOF@SUAHV-`q)q+1-m;
zq)i$0X;iD<luL#}MZI}5^SH9UxLL5?nwk`kf&hNfP=N--s7U%+AI-c}Q6Em%%O*&o
z2WbW`|JkD;il#0@#biif%;(!2P<Yjqs<{lL#_Wi3Lq*VLIz*q*W#4DhSfPHT#o^1n
zXQ(#fTz`tI`y|>2W2X8#h*n>1MgGE%+n>-|%w8S2N_HVCSKIccPbKHdFSx74{^YL3
zZT<b~YBlWty^&=2*rI%!{LG?MZ<D2eDVE;m)Z{j&Ha69%`4>0(&)*jQj(zFQBxITD
z`5~~Z`-OC`&Lq?KULA+c^;@;lXpwyc1^66kK@~#qVKXkGiA*Kz=9-FyWaqNC{EQr%
za+~Kiq?=Xq$*$#3jSz%L=%)p+sH*-&_k_D`<ciyQNWQ#NK<zGu*3&*gvs=Zp^60AE
zy69{h$Tp|*Y8n*kxGXV|*qfIQE!lUdXQcmg&{32qMSCvV-Z$jz*Trm7FUIzSSGu&J
z+?iI+Hd%gn!^KkRz$uZ8#U$`g>NOFsP7s)K2$f;;&uNh8<037a?Jy0e+)^W&QQiC5
zpBlK`3HLH}X@#dbVVnEbA?0~HANgqCK%+l}GFBvl(1#{Qpe6e#-ZKaZjBXC63%sg_
ze6gt4do|L-z%-qVwe{}gW+y0tYi;Oq4c6Z$ejL8cGvrIEi4{9!_wNXmCo7IJ!N$6I
z=qpUG6U%JUHzeB$w-SD&#MB^d4&twWI|T0awwJshUiy<a23WhT;+6AaN3lC~bnv36
zvRk1%KCsIqI<sVMKjuFd<+}qq8F{K*Rs2z!YY@=l&jxkk{mBFG(~0*rool!4u<PV=
zNxpty5^mUTc3=b%3<+$CH-M~6-tG>NdTVf6?MfzwmxVpK<{kar7n1z$&}QdJ;-=nJ
zY*r`j;uL!yr`?BKd9u1Floy?dbd22Ys@j+Ld~4D3*ONWTRo`D-7u+Lcv!);c?U!8!
z;(%mRcKgMp<a0Leux&i`?xHbTTNxOGlh+^&@*wP*$+9s?l|KxUpnzD$_7@))ciW{+
z^9%@K=zuk>wehM;C#54MGw4~dae7@d7SMnuzJnWGoh%CwrdpaRJ6!}zpuf|Jb)=!;
zofY18`FPUCD{n*WYMv+P3|>v%7}a^Oz#<O*ynsj3J*Xq{zWi>f-T3{*0h$gFs5A~H
zd2H?(9VdBDjnrW=X~oBChTlT?p97hx!;K}Gc?qswGOO4iQY=a-$mUHUxzg!%SJ-6%
zpkUG_u5r0uXWOrk?WVwNy8Cq*J*5K53qK0L6Hb+9JhJBv^3ep&hbwwaDlNqBe!To{
zzF8d|TN3jk(s6P%#r18dVM)~&Fo`4$X8I8F#5WJJHz$e8*%K4AzXW%v-;$%O)lb&h
zuu!*qJvU$mV8tPm(WDQD3|z%7nWQM6C@qPsz8lnP#4b116TsXPr*}h~%rMmf(=R^s
z&(~@sM3c%OM52Py3icOiiKCpMf=Ek;j1n+>Q%-9tLCf&z!_>H*^O)828PSGw!T|$9
ze&C=cjeHibAWUNYXLR!ehgsx?_Vv2p;4IrXeoLg`UI4?)??Y_#8Xo!2JKXZ^(`%Vt
zu)x@%b0Nd~p-v0NK=LU?bgweL%vNJeD1c|p^P_f_#qh-j^{89`h4X4q3}LLPq%JCm
zq&~qv%P5&xrS%*`<LPy6+zp|+`7tZ?O6SD93ICieqI<I+Dn?hJKm%ss`fvVe+cek?
z5t9%EH3fmuI1dfj`t>pMxa=M*@^_S!{Y8Q}4-Ud&Z0wh*=iAmdZ&u9`8*|E%=tCpC
z?i<gF7*LVTR^lscb*iOP3Kt2%OeWA}T8;e@uCQGJFyp<GW2oQx`nw3Q-TSf-#}a_6
zP0lkuv(&4FGl*N>LMAq?VSn@|Z)BjWgn~KRO0&_bgYlRjhP}4#(9-c^ZS$#{0%twp
zo16f62mfQ(x_pZXzX`iwU=^pZbxeFKH7lB<nZ*1HmTJ0xGPDR_B4J!f@|6T<qGU>f
zKPg*v?3cx1$C;9B&yfhFQ6RW?8Li_Q8L2y!`<A6QWW1-B<#nR2W9G1D2Ih)(Ua?dv
zrk=lJaL<Wd1|%@gu9zgc-<8A0wuo_&EH0g;B`W4Ne6(0zA-`Czaup7jO0&9kbUFoB
zXv@a>8+YD^=^m_ao9f!$e|TttRSs4+^k0_x^MiWjBLFx<&$d0vwkoK2Z(9|oiAoba
znN3Vu!Rg(`Y(fsQ#~A-(O(_nUFt`wF;g}(CQeI7AMjm@K0z+C)`5jXyF!OX7(BD_1
zCcU#V=v+A8_y0l`vKx_)|6Nm=ecHRNm&)uNpS}S^{pvG&0HU%FoquLeFO}J2ANYGx
znY~CxwEq-BYW=GUO_!o5+SmF4gNiqL)GB=S-ba`Q227To4*+IVNpB=2s{s(zfTuN_
z#BcvP{d>kSN@w&2oB#3nYR_@juY1=E|Kle=`b^u6Z9NeEXOC<5X6-!d(h8pwZo-O_
z9!*n|oKGa;84S-rgOJC-L`v(~CM+N9V}ntH9ajxI#u0l+#-noDD7z*LuffI~Mm4Me
zprk>T&hkxL4vWh$D|8g4-c{U@dWj+Kxk7mS6%x%_+toXN_x02R+5(wX=vw-qx)cUU
zYR|dZ2xFj$5Lm#DtsdiM*c{OmBAgn8i0$4EiSWv#b3zP?h0w9{A=%6G8OCl;a0-lq
zB-L%}+V5{OD#{$?7F_*Ucn0<s0Eh9Q6T8Vdr)0^`o0+{FID7EQRU5{qVD*rVw^mr_
z4E-qAHe<dT#&in225q}-1rwXVxz%ZdvsC*Vj6zg}1IMoF?rggkZp&$lT#p|aTER|9
zj31m_SicyU*=k`Q83ix|E0|>ye4oy_S*;*pLp$VcllFC-E9q+gqFfQgAEer4#(Liw
z8lUQz1u!Qf3(=R*yb(@`Sk3l}=lZrgGFT8|1WPpK5}C2g{c&qZLe9n(y`5RX6u5;x
z+9s`x!_hV=sV6HY;cl$?%T!Sxt+nmMIm)RFWc$r=%B1nN3J8g7{PezHK`{XOnAjW@
zL58oBD9MWB1$?K8=eZ|4DiUCFq$-0o8a7yAky|xW$$hbtWsrk)BN2CZS{yYuPK&Ol
z^7KOPR-99~Nm>l`T4_5mwml3}7u34;>2Zcs1Xb7<t!sx@8>XCx(t)F{(JIP<yb4p0
zY8ngSPRAc*W1B2UQzfPac2V#^c$BD2S_DlxYNn1jWtY=wad-bQ9Qp7J8|&2^r3CtA
zbn!8P4B}&os2ien%65r&!XWE&Tmx|8fA~XPb$naI2Xv{)fLs)Qi82csr{Kk7s$!-_
zB~`$_N>`|-5I{fq0{jk*OhU`$Z8U&`Y6YHx7zQ+1$gxkb*;cOU8E^jmn9p$wS9`6}
zi~7`;lBgVLN2(P&<_%#4R8r%bfNT0xR8xeZGTA*YM;9;(V4Q*GN9eL?kdUvVy=QgU
zt8wk(_n0AiM*)(J#bphto1b@CP{G{<vC`k;Xon5H5pxecIU0p<Hid!)$*hYyaS^Td
z&>?9}o1KXb4exPQuKJeC@4!uGtbo~J(hFCy7LBFHX!%ex)VO|Ypx2$24S-R51rK_Z
zcYSLsP^P8ZObf{dnJTQKqTET-np4IhyjcOjf^KuAV2v(hSh)T_e#Gbi48Us9+FsEy
zr-NEanyJB_<WXpr!&-43<UY%cMZRA!H!8XmLgjM!)bw?_1@7@twlB||w5>xA1H#A{
zSvZ148@5WNcSr42%h|wu;v26o_YLZM>B8`+FTkl<aLrC(eb#g1ZxD@e0W(oF?V3n2
zNX3<5Aw(z}0||8t$YhTvDnu}?aOQj6tl7X!3}SQ^7n#D%M&VG-4c$YL{PVAo>xqqI
z`If$2c8WV<km&a`V$iG>WW(}O&j=n^^1KJhejETJda$h(oifV?7Y9yA=X0TDfVrDW
zaeu%DU!l3S%(mMh*F#wu#vx4VdwZ5~&Hjlt7AYaGo?%dA6b>~2TFwUyl)A*3>ZyWm
zG_tUvn{9JzuS{vs4`>lA=&?ah4UB^t4-GTUeC=QjKX~PD?$U^q%GlG6&jZU=T~nYJ
z>^*7pV*+a>pc@(JQwBd#1vmOq!76Da0}h;k40?t;FaV`o=gyGipXg`+E@GGBG3tX3
z_I`B7!F9O)!Zi1xI#j9<i3d{dq&s<LpE9IhrLmjJ<|tUAOP{luWj3NVC=qap7CDYK
z#oBnaV`gdQEMWx{s+z^bQK2(p^#La_1afMd86eD6-@crG6e)NZ!W#TfKgo+SN>S7%
zKFvb|dZYp2kN+GL#|mcD2IV<jHX5F(p{j#y96%4D$!fY|7rBw5;388eih7CaL_b*&
zSz(xfQ%mLb(YEaGzja-~ta(PQV4~Z!5<{@ZGu;a)BOCEWCf%(8WG0MbS9#R?zLeY$
zV}UJEn;jIiroX8n(t_zbu&2-ogObxS+87BL<Md#lZ-<HLef3xNjie<AQjX69crnlh
z+2F&P5T6Q9_ID2#pA|gcpcYRdX5~jjFWO&_rRdIqrv?cie(E77xnT45`^Dnsr*DyO
zT@-hyax(G@vh?%f7AeO@`b)03nkEA!=N`q1qEo5yD4teFQ;6f;ajY95`a^vaTioI-
zZafS<+bksAJ)!-=RMNe>zZBPFl6w(pb1(P~!&1gtTFZ;K6(9MYbqh@6F>AAWOpMJ4
z<zv68g2u&4EKV=lkBQ>6AU<(i?8z6yPO`;OV}LwabIWo%2${>@(T~F>)6Gj;l}2>@
zR`t{dRa`8R=l_m$n<zgAlpxEkB~NUfPRkejH>eFu-5pLk&#QZ?pRYMx`F_#A+K)iO
zzOB>3DI}=_1MQyakmbqj52wTaa9Y$?MW`{wLXL3YJ^Q_JangPJoo^VJx}Y&6oC?Q>
z>`G327*3!^B87tB2$&r=UKcgUgc$&obY+1s#_2TmJA4QnMPw`?iMS>jg#w7+*?@kK
z{tldyU&bpWRq{aMj6tJe(;2uV-9CsDzDQNryDZI3TZ7BVuAM7SO(l+;NCs30dd2)2
zhlG5D)h%$cPO1+bu$nb8$D26N%|YK3LoHb?P1OdI^Sc_0(b43SzWKXHlTW=Z8vq#k
zbzp*laQ(oGif}mMuAbKHiqg+&Qr6?O(!tt5I1)lW=(20X_*C(2nS}i`GA905h3_r~
z2gO+U!ug~KVD-5nveLIy>6~~>>D%BPE~$aT$69A@$p*~R15d)H_#{9?UT62|52xy`
z{dn#4J#p|*n21{w!~W7KHc(9I#z9_3Bq{lp|M`u;67pLr1efr}u9L(Hh+rW3)fzkr
zAzF~Lt~mo=20Pg#Pxtdl*eddZ?%cypye~=kO!tfo=qXZz6Uru(PudV>6hH}aU?2dJ
zBx){r#;=ZDAheTR=M*BTDM#~6G+}A9rlFY<cAAave>C~JF%aHEvXHv$fmR|0)nLUi
zM~Tan`1fxb;M=+otp&ZltBhsfJ{nYdrM>18OUXYaPV)3k`UD+srpp2Mhx9w(QOS-0
zpbp`90$*DBYFdqsnLz@dqv}g$p&w(ma|dbCntCkdL|~19<b0FMER>QWQff)eM|Qfq
zA{L?a0E{H;NjJ&RX-_aH8Dxfv&$?9zW$~@<yMFep*igmIZY~5Ev8s90<EnOBugTDI
z3qIHWxUVG}P*Af5l@D}_Fu+ld#+;%Ps6%ShPfgaXBARD;Y+Pe(v{BY2WdGN62UuX}
zMUn?$_o?L9#JA|8B4gEwL}J<Hn~l?x6O5`xDY4HoqUcr4vqfMlsowQ9c7iOPr6Ji|
zfB~_@q(v^|ary{!98)0`I7T(Vc;sk+rL@>j^bC27lrdJ+G&GdP*(#tY750<fS&|Em
z<X~ei-4WeO)LD_$xK4>qXVfx{`4vKvs1GD(h)vXYuqjcgH%S6Z+Vc9peFxx%-iiUH
zmK;dKo)#jg!aa=h33?~{&^=Ys<zn(f69s&j(Sk*eG!P_%RP(xf6>WMrdC6c)p>@Sl
z4b0}aBh)}@>P;e<0JLoQx>xgAYeP&d4aOS!nj|?}j1XZTQ!d@MO`7+Bd#(SxQPQPh
z>hLrIL#U*yz_X<8t{#Jcrxa62DI(oHQ+Zn2+ovT}95V}mT&4ZUiDCs)3QW>@TEjaF
zK5{#K&yGRxMOOPIT@ApLre(4Mztl`Bbd2ENTw!veEn+k@!RUESyC@q8^WXD^jNGM6
zh`La++ElelcqVe-fQjI_hv1BjV1F7-W<Uj$H&RVY_mE`qQ(!5W10XdtK|5qO5IN7%
zC`>4MD{Ae}KjdHzXuQd}@&c*A7Rb-mK*ml8bB`cIFeOb=ozS>dNbsI%5dBbza@SsJ
zVTo96?RWu5L1_;)2=y_hY%;&DH%8mj3Xqa->#O5hDf5<$x+@2h4s(=A*dEXh#R;Nb
zQ?g`a6~+X(OZhf2JJ_i~8s%+t@d_*4MjMNj%Ejv1llu=XjAC2$c2WdM0;p&@!wlX7
zy^R)e4)F3JHl?CbG=ZxkhlK>lS-_$?B|hOUSkHQsOXdmwB#2WW`bY+bJ-@BX!fM)M
z*b>==gUZA}{WA<scGJZGG1!r@=TLa|Pu}PK2qN{6`_W#0{11=3nizlclgGP{od0Zj
zb1#GZxiX2we&g~5`b#gPz1-BxME_c9{Oj(2-!xp~uZ04FN8Kn1c+_A0a6I8Fp}l*a
z8dX1A-hCq{{;tEeuF^{pRoegVt?$rPs(w4Z;JrwW{^&igZN2yt-WOHmYF`vgZ;+%<
zWc0-v&Qg*9X|tC1oduJZ=upo;C(jJMi}!!Pg?b<bpwz#57yB$F0_TP$pP>`HWK)G8
zA65tz0O@4K+r~dOg1<QRDSesV5#IQxd+pyoDm19hVDswHyY*`?dOG*oi)+vP0{bmc
z2h4q=Fomb_K$>OQr@*8J^38$FCy6rj6mPLjDRGct52a>Bq0GwB25`1r!Yt@eFL@|E
zbu`3@yb~qXAurn{0rRFSk6K1b(WP^X-Ck1RzM5@^8_n&aiJu={@`kWT_MKGU7dL6S
zaWvTo4iXGYrHE4tgZI+ryaqsep92tJ31eCj?4~P5pL32;6jh{XnSKLe3%jf7o8qd`
zNx>Afvs<zDSVmZ_{<H7tv^TGj1<DIx8|8II;cIsDWTv!*f8#zn)pME(H#K{{oiYQn
zaFd_kM!GD+S#e5v(LO92>x``!31B<IV;?yX8^b_6b@PxMS2erLsAt#{ftQdKpWvEn
z`(9?*J&je0Dk%K8Jq$@!R<7cdij8}#(`l&__6gW1@FJ>AMuB-Kl+7x*l-$aol;Q{x
zZxl1)RE=XQ4cANWGuYhFdhBYrpd+`CNw!)|ab&k^ib9Z6NGQZi4NrMxWc|)hzpe>D
zB@07IgoYi3*rQWs1u<?Ipq;ZF^V47hkAAX-SAdxiG2%v{Bymo7brvz5heF(a%Fmm@
zDM_SBVOFKu5v_7R#>0FpDvS6el-eN7Y&&}hRImN&abkwzDG#lt@ygClZnffk3XOTz
zwjs8p3UsQ!CP!0|I`i<bC>Y&^WKJRCMVvUcG&?SvXH0KU6$q$uK2>5tn4c0moosd3
zR7*tL71jfsEh+dQS$YXwz9fus@Wr-LW>^g$w4HBXd@*!qqVg;Mx)F3za^C}Htp+v6
z;QsSURE6n$Dm9C%jwpA`is=;j2$bqJRua#!3e>dQDQZPNbrZ<H8UymeUV6%8&(PHP
z92&z18^ayK`&62Ok3s8~ZOtmHnAx}~E7R!-afn_}g32h3JxeMk^~`K%z<MnD-REyY
zQ;jY&B|a>g>;S~{96S0ZlVD0KXb-ygma9(%oWYD}n_k7N;0^acr(XZwUgg8>&|LIa
zoSnR=8bg0|?B0N6_F%#}<4|gsovKN3Gdmq19oLEk!fXSSr+UBw=d~9zdQ$~0<=dgY
ziyjFwdXk3J4C79ddT9WLl{a2yD5nvZpGPU$JfYpg_Pl)MH@;$&a}){3STF1b52&^t
zKf=Wmg2Ay@)}U%>s8iZ)IxxdvMQO1^hhqWXsd8IQ&)+D*RBT;TlugG9S1cL^aRTde
z??TEqsTA!5N$ajWMhy7XPGRpug{F~x;6QC6zfgF%pOsmof)8D22!?9tYN0L6B0ntm
zu@Y(a#uP1jBhGNQiFM2)@_;XpI)O8cpkyv;z=Ccf*?>-0_leP)DpjS>lT<QvAvSDD
zY_u$(>iEJsLJ`<g919n4@cAwyU}zo^0XoUWE69ZrIO>D3Lj_i7RCz*RhqH-i3f~2J
z8n|<u2L2K(xPz{>(fZ(<!3_08aVbSt=<HgUR6AIodHNankqHW0$PxRdR~JZjF5=yy
zK$43|Yg|N(ODqQJ#R2CQr@ZdaVnw*7hw!->SS!H4fxQAiN?QPpqw-~I!++4IB1|gt
zP{M~j^swC66C(V)4em@re?|@J6Q)6?TO`!pL_vr(qOhhEOLKoHy4(Pc7|25zY4Wix
zl+B<}<QfPoWmxYKel^)s13T8f>*c33=185CowDL#+J_ePxkg#%?AjPI+@xuMSVLns
z?Nd&v7B4F%9e{ANb-GH07Bvb4+iIJ#%yJ1Ww1VchF^Duw9GG1dGM=rVXw<h&zC)?5
zz58KqVlO&}!i?I|TY-|8^3z@g7%Ky2ju_0+shgV57Y80vA}=BJDvuJ1XGb;!x<Ql0
z9>kk;03-dY^T?5rs*N^jzai6?L=2P`rH-pq;?tvsp}@}rY---_#dISX!#h<1@(Yld
zRt?NJ+CqmJrkd4ANe$s4dX1Xt5rT)zDCJR(HucvBIFZ)dwzaa8S8x7qy_PmpE!d{w
zyBR-Bv@|ZU!oXp=P>lI7;htw*-455pL5^K_LGoe8p;3WtH5)d`aV%(zj&*cV97^eQ
zP9wi)kO0#uo3u$t52#Q|9px!)AS<S1!ba`;-owUM7z@<pMhq)iJ~J)ic1X59_=b%0
zS=JkNs8X-=b^yrE1K)7;)WaMiXyp|uP2bw9+mLJ7k{wSVCl}1S!3||xVaETzSbP8A
zw$Ag;7l09$PTiF6!69`>K@#5=2Ovm^q5w)VZC5tW;Q<86luba8O1o+*!ldl9c5TvX
z>UOpp9Pl8f*3??0r9__AW0973olbWe(cUzjz4xvtlZmqHOe|W-_0DD|mh5ISot+zt
z@@Cz=JG=Muf^yPdd;hr?lqiZg=ivSEyw8vC^L?LJHAkNMPmwPVE?KdqwpM3f(P|xE
zLcPOPvSy8zf_0^9boM1AgS~p+7Of7@O5s^UxZ(~VCm-<AXzjP^SDlRM<QzwWK^+XU
zkivquoC5-C^xlkR0w<BEZ;tHTX&Ubs&LeWRb)VBOT8pNY>^DxM1u}Q}z+|mOU(AXr
z@=b#d$tR#JXH>+NMC%nmYW@E~-#DG_Pj~z7rL4JS=~pQG2HC0Z6r3wNM>EDu#yYVi
zrkqj#IRV4{C8y{QjEdIpw6(aUuJg=3qtQfyWNFBOp#3n+2A{GzhG+@G8u83AfrcZ7
zGNSnkJM>Ikmrb-cV~G|F|Fc%OWyGS9qtfW~W72`xGEdZD`o7N^K*JgSl$0_f4zeXv
zhFQbiQY}*5DI~4r+J{e^o82jBA*K7Rk)0aVLj8hxffLo+G)ThFvd9MoujztaZP>@0
zfJssSE33x?u5F>CEiA^C*FY-(%-}!>|C+`M*+mEf7Sz}GDr$6R9RjP13kKjCrS^5b
zeRk9oyETfC6(_AJq-lgq|8um1(6rGG9z?f%{dd%_E-0hAKrxm%`NIFWV|cEGhHkbv
zxb38M$n3L(GEb&~O>S65{$bJerd52YWnMs*x*UKKJR*F}f6&{84s8(rjPU2hp?;g)
zgWn&?4ZnV{d<b&Yp<<5hhQ$*@uhZZ|;(6iaHt`5S)tdL-F3Mhv4wd!U)0or<%2!Pj
zP!+Uca72KG@wxMCIBYM@Cnv1wBC>fI)`m6en(YVAcpzFEOm8cr)N)=7T1)khthlFq
zWBFVk^@+A7e)Od~DR%z?t!fE}a-Rw6tWMUPBdCM_upZenBaS9U#r$?hGiMIvL;<*_
z-SO;MtN!pI;(6yYP?}nd;j?tRz1YHcuZ4Mh$Z;Gh`HW1+P={aq8cnxaMg)Kp;LE_n
zMdQzkHJ+nELKHd-rs-zeFBXd+Du;4@_z=x)7V<_McIzk96KcBWrrCN<{gDCOCWzsY
zRhn~XR~Q&A5a)#7LKn^elfZq^2$mCW=F{u!?hA>Hf;@J6`1>Qp#yhVGZl*bB3gLE<
zo9DDiGrTVh2r+#qMhcj%U<-%^`4<078#sV~viOK@DaXn*vD1#N5Bg{Uhs{4N6e%jV
zSe!68ukGFUd=Z7v<#aFTT0)CzZSpV9iM#rDF)a?emPX0~494Pk(g9AReBUpU4>`j$
zLZk_08WKW5l9p=%T*hl>a5qKkO^03+nDgPYq61Vjbf~QHE!|RGtSNNnH)3=MjjYkT
z(=A~;X@zN~#G42-35!Zt&E+C@fT-xv48O4CM9&FM!R*^?<f6azfB))mb{E1-aVCJG
z7LT!nl&B{?^uF&n;o+A!PO+504Dp#wT0p3O3N~46DTYMZ8g>qy2U-DG)4gT|EVZ`8
zZp)P(Bca7sL8f-sg$DS$k3K%~Zy52`QkLCpY%t_!c6Wjd4LGd5Mwc`&rDcbe#hB38
zfiR*PIwwN+d>|bL^Pm5dfs)W`kLI?7hs$j=cX(Qa+QkU-4?@ArvlFpoz%Oc`kmhD#
z`A{oO;4NWrSg#Ed2k>RSk9%S`un-3h|31i-))I2ptMKK-dP_4Q0K3h`YsRY@{5u!}
z%Rxd%L<<_^?T&d-Hd%C54$&Dt)Z)|7m8R+%^%}Y-O>a?6e)!AlcQrajJ^Ifu>zE|%
zkXvV(fXNs#R`%;8KKy{i0LH~H=#t32#{4FI2h<7yen5y0wqP>-V~vfJFh4o%6&~s^
zG%N5!J>86!K?xKR_c)JKLIcJ-RD{A-tg=czipRZ<HIwz;D9QB=wf0HR`}4wJ;Hr8z
z>hQGYQw^MTadX4Q$r<f81j%r~O2=gm8_Q-ITrl(p;6H4y(;*hgbx-3@Mi~4lw5t|A
z0~@M2>>p_g%~Ord4*AG6UCsHCocWpI@*mJ7ptBJ{Q=E`4u(creI-xIhf9^asNLy&2
zut<P=Q!rTV@`?`~&kFq+hvn$JEshG+cgSeXx>fv)AvXOr;!q8u?KDHQ9^Y&_O2Oog
z*=f#fwFon`M-y5qw?`cK5?_c8J7o>sIi4COY3q0&jh)f7E*we@wAQxAOt+GA3Dsu@
ziB~QLL=ubv(g(xMH<2;Vzs-Zx{|AAF{Q<#9+Xp%QzVDa;#!X{r1G9r2VNA>Ay539`
z>=fFlu&9JF;8QS;pYGPXrk3jTLeacr<V!z`{2dJK)3YTzr`8X1{9AkIK3U&G#~F;>
ze-}YpR2psqzq*B6ZSg9#{|~&bg&XUj*QEMyx6rRwZyhX|Z5(v@yXHEcxAwTv0QA-r
z|K9WF_h|-%tb-eqy??Jg8`p6(&FlI_ug+)~jT0*W=8XF7^^+xU_3HTsh<1LxE|<H1
z{lrYp9RATKchvMwE3l3TL+1x4pbp{q2D(N&J}KwmfNb#py4Mucqr@_XXB_oAI0-S#
z$x`G(2AV)4nrlVM3fH8gv!5M;qjr*!Mtp$4Xpl&UnfwHSN5i^b+NVPY{n8QBKYW=w
zX5+(gl*2Y3dFzT#AE+ZtxAErs8y(@$NBd$IYi&AWFPe@Y5R8RRdx32pCBQJ!^Z?S4
z@3Rn2wb7YSFck)v!IO>qVT)BqW$I{a)E^#fjkKyFJMyfZx+KVJ>{5|myRAnww_D^l
z$*uZ^)x?%Yw$b8p(tM*0OiB<(Oyh)sHF=LaskKLnD5K^kV#w2aPZ}Rb4SvGH6JSHs
zY1fd7P94*-P={!upB*~%;LpBrsLg>LNpUX;VGW?C|DxU*R?t&Z6?gbMI3a$0=y0s-
z%m4(VYWTl?5k5NMzSh!>Fqeom5)Ys5a0?^8rZ@Sxqr}91XrP})6Z85LW|+a?BZtBr
zqTo__tlhTjVH|l&z83BgK{8!*->HQ;s*1yc3>D1!&?|$1XDz8Q_V&|62W;2@(rEU^
zYTmZB&c{QNTGyAXU<@fTf+_af@JZ}%1Y$w=IAZ{gd>W@ivaqRUOc4b$&NclVez?QG
zjc&;1c+)%Su(aOt3F@XO^!FM_NnNPb1;wE(ghQJPRd_=nXcmejogVOl(V7Dn?V?=>
z&A92M_RfFDhfmQ&;5+<pkjt<^BOpgLH~o-@`kE|ewzhKw1e^RWb8Z<!pdk;f4E+J3
zPzC^e6*V>L@8~CLBl;t3GJ@Eg%KC;<9hW3%s?X^i1!aUe(vn?;{aHT2dS0d-tEz5}
zePQ6U&HYv)90+;Q0y;oQj|yNN%df9s)lJ``^cBg9XiK4KMhdg=YaDszkeq>Mq}$Tr
z`|jiH?h;0AmJ53fPD5Lc&ypRd9wQ6uv%DoD|1yzI-7wNAW7@C1RY=F@#NOJ`B`bH?
zKGA5GmpU)^*81BcAZF%Fje^u2ne>--gV$D--q-uAE;4sEzJz?X#HWR4S=8-+Dcl@D
z;xOXHrJPk5p#qUV6>)}rmP^NydBB3`bQYl3m%PG;*W7RJE80#l=#CjvATO_uN~_a9
zW&Ii2dTI%VT+8LO?6|-I1J;mFK@k6W8KeOe(#^9XZOr(@FHIa%`n-|e(QkD7Z(03b
z=tssc8?1wnW~3Kv*d`i5MJ?e7L{Ahk!=E{k0piq$Z6bawUY3Af7aT;!&?%Nx+R=~;
za4BXxM6+fzs-c(#(Q%vp2bAM+q*<>vzY3fgP}BN*UxwQb?4)aTIU+PAqL$|e9pRQV
zO<|P-d=Hpo$eJ-g9<a&qJPN0Eu%=OLzGpa~yP6%>74C@zM|~ComUp%T>2dq1MYkgz
z%<y4H!Eho2$kPCJs)~oHp8CDdf;jlT7YvFhSg{{q_SlBYhiZR@HC^Y&Wy<JjZdvnL
zqU%ulsKd^!5`aS%1%YB{D3WS~OyUm4f@qruqtlx4YQrpi;h*YPKz3>ClpXqM<(HaG
zx5*LU40No%)B^e;_&^G@&4f=g&lZLsr33Gd0)kQBx2j?%(gAQFoTHjdVu}{Sq41QZ
z_XvVa2i7I#ScLDE?le$cn5omq2yJDIb!)0nh5R4=a8NOYTFvRdI3-qene0Oo&onjh
zDMTI=eGOFQl-XxK0c;PlLU|8L;LT!)^sTyeXbM_4!#NJMq8}0i(~;PqH7nYXQwC#z
zWGvsgByBa{dBPQI{|an40&|JnO*K3f_F3p5kMDeOG9l}`IUeO_<QWePtJaW%ftIjd
z{2{LjI31DzcGXc?b?z{YSHpZZ0F5)<0A=ZHx+BsrI4Odj^GX~4^XxB)i!A^rLSq-9
z0j9K{$R3vy0KyZ-5+lcPA&gHI{Hh7qf6PI}Snxjwj*HWl18h?bOWxskAWS1@kQUa7
zhSEg14H|G0s0(2M+wDR|oal9j^fuJ^Z0DVH#7O_e^T0DmOW=V0@e?b9&Uy?VD}<{w
zUd%td#1N}WV|>z)OG2yb<~!J0XAF#LR1n$W7%zQ~#a2_mChqdMOJm9C-er3r`qSUR
zJvRra8&BuCBkovTPIPt|<A|b160leL{^rY88wxB0<0@)a!)(?ba+)@1o5kd6K_5U)
zVj00^YueipNi`|ddZ51{%vx5{d_V^c=$KRQ|KtvB^%y=8_`VD~aS&YpA{L1OB?f`r
zItwl*K$8HtL@^FLgcylos80lX8bM~U>UTqck08V$e2jgZED*5t8uryebd3Q97eVTX
zgwkmW(>t*T$q%7rSpdFS&tU!=J4wk{Xik`JBl3ga5$I-qnlf-u=)z^d=4r6bKOAKc
znsf;~><}NGHez8F@=i$%Rn?IY9@FeP)7)2NcI}ma$yQ91jGieT8X{kZRx<~ZxL&@4
z&ue*zJSegLWay?`!pGos=-Qc#X*C@1rU*{s%kUl*rKiJnK3VUZP7lml@klD%&@i0o
z(QH_2tAA||U2(#j;w=o=-C~2Y10+n!jJQ%iW6kD9mNqyqjslpOAa@&_)>(0~r8ReG
zskP{AaJ*d6Zx!DWv2ZZ8)W)%qOC}?~t1U)h`J!VUU<P6nW-&PE_+rW20PI;Vj<poj
zsEl((Sez6mG9vEGiq@sJ83AZ_k2o(<&S<O!V-1rv%Sp+eGn;91$Y*XBu~9=DDOt}M
zLWQi4EV~}KzrAoW_NCO`CDBqT_5tQOp0i7|jywBi@wpC;UWxm~_;b!+Mm#6pUV?6(
z5l0YQSm&*0EK(bvL1r7N;L9L;`^u+tkHc^CXHjvph;uMl3{KOB0~kWXA-d^Uf?d$!
zzNb}>^otT)?>S*pA@cMeOIo!-iK!Rcc3-w$FvJ(8Vxun>NwNxaJC8Fmbl-^0bCFvI
z=?y8h&n*X?YVbw-m1piWk{f;LWZ2aRAeSQuDq5hWBkSM9dTB8ByXZYHMvlwOpF@1W
zOD*+Lzub5e_>C)Cy*7W;;j)XSejKKZc&Pyg{@rg35py~fj^X{A(7i}}7l^%0KAGTk
z*lMvOAx?ZzZaLMqwkvtjJhb5h|JqWK_RSPqbQzxS?$wA`8;DB%51rznt;G|1uhhiM
zh&9x7(mHcU_?yi`Llf3zv)CfeTJLkq2~f8ed_#omf0#SuZFMv@AvI8U<aIGTqX9&m
z#UaBTdHoPz+=;}bF)v%3ML-YZtEa_QXIN&82ik0iao`2=eq$jvd|`vZL4LYo*F;8^
za<qwEnPbL1PS#Od51zDIMh*2q+w69~dtQW2Ocj^Y-5>bQVs`Bd3(e(Ba@P9ypig3C
z=+G4b8sX*6)4<~Fq2QYDJbXxh3>cfWGUB&<X0LOosk!V|C*oFFXr2@RC&iiSMA(Ol
z?ZB_+z&*~Et>=8twDvj9gk>EeaIlhx5ieImU}qjN^b<io21+%}w;J>(tVc2}^D$fY
zsmRfosyA&hWQppJ)482e4bb+wC6!TrX@ijsol6+GKU2WDuCX?F_9N5aus`cgu(P2<
zaKc2HyXwV5%}t;lAgPBm?i2u{vLg}*Zx%qLy*P77IEBIl6M&{4HbaLzIginTi%9V&
zNUnRG<}1@wTr-64{obz&-?qWA;8d-T!$sp?hug2s7i%rl$)7K#&q+J^uDHZTvvB-U
znzoCn5_r~dF20Z%Sd#7R!{peA%<zd#lGaNj7p(QC{p5oBkAoM@-)p^OZH^!E*#Fo9
z?`oQnANF&MJ6It9{XP}BfD|2Fk-td$k?GI804A+>>RDF=4f3mg@g=|@?;OSvz(<5u
zeubkB!h7eF#^A`G9V&BD!nA~W26jf>v2ce2{^Z*kCMfxrs&?C{#EC^K+%`wi_bZ}S
z0@Nzg*igEkT30mwRZ;(r)ItL?bzWJU+s&=&p+5}|IkCZ?fE}8_u){EDfw4{(HD-2*
z;buc)yDz}a^e>Ffm?nK-fYTCYb0$p=0hDWK@XW}e0nke@P+TCrBUA4d_Ms?_vuoA(
zE5TLLFwPV-{`->n$g)HW2o^~4K>;$JoX=onBOeKIlCvN5DV+1Nxma$W0#<Cl4e9C+
zoy&$eE0i}AYZvzHFk74p7PMdC)4q+son9`Ou&jr3?}H1o%XXQ~gQwYE*m8#jMh48q
z=Ml`9(B!~P;osHUJ~PFBRZW~mddn^TEIngy>*2k^A9mRd>qOp}*6dEmnbY9Nk7z3B
zK@H)ze<U^UErnwo8Mu)_$iPr1B%|=_E-bPQ25iNCsR=vI)BS}=`o3?yGgdq<>m$pD
za>&F`RAaMIX5`@<tzod~DC2SFz`R&F@*kl89m(l~MA0xK)9;hiAd?NnY6Y|(G+s;m
zdkpvYf0Lb^q53CgoFZ-Yk^lUAx}4p}>ynT8+O9W@Yktw!OjUL(1ERmNi}ttQtL_;r
z8GGdRbZC?Q*2eL(JVT_rBQ5@dvRam;K4;;wmXpvuQ{j*L`yaYi^yF{79of5-j3N0e
zWzDf1q8-!2<^H+_leXzeEz@<FgD0np!`@0;I2R4A#2b4*+u4wi4s<hLcF7xbTsaFE
zo1^6C5y01PJGm%ZvkyPUpxeo*()7+uhd4X<wAF5eTURN-RevPgQF?vX8&XBisqXMO
z^<2#XNxNon$R&qv4$Ld{&U>$;C_|8;SJ*ObMV|VnzcOrTc)<6Gy9(eOR(Pt&A(TGx
z;5*vY)outLQ**&5?uZ6d>}qy2^$stI5UXR9T?k}{pz0)FmGHJBLC_W5R`iqM`lSFe
z>RF}iQ)+WMq^2V5J7q&D>MXR?RV*><r8EhkQ1_DMRTEC+&$oWAwO}9=`2IkFe!>xf
z3^yRcjw_m^uML~VRP_ZofM&nGY<4eBFF2|-Y(nm6+^eqyBUE^2)DM$5bSLZUmXm;k
zy6O7;P|m05vW5_Oh=yV5Xj(P9H^f)%e*{DPW4)>KZ@%nq@%}LkvF8@r)+pxniz@iZ
z|M#;n;qn35-2x*2UNNtq^XE3&57ll#h_`UaE#BV({u=zb^`|`FU<7`D5hjyn1U8Vr
z{*R%XH}K5A&%?X>&3(`8yu~d1l!vFEb4LBH2@v_euPiihNdD0*yq^PzYqn<dajK^M
z=l_{Q4?q2?mvKgUHG8HP1rPqkSL4?~LyAsWpo}D`Lp~q_tRW39Hp-Db4nCuuWE|AS
z<**AHKM;L1{@)SScZ`f|$&$JzVqmU#!(YF4{TH9!x&FI<?0a*x(Zp)w{`CvK{-q}1
z7dzZ6(q#A8K@vVeiqtnwnnoMQ2OFX0gyB>*4aW~4a5niJJ{TJnW!hv-iYC9+XfpQs
zjt!n2ISO=xMxLhFK#YLZu>4jwG7c*r5>{)FYZ|zmu8vat3pl3g?6f-cF2<>dvRz`1
zDy1`T4DJqDxq=6^Aq0lyV{+`4roDbnLY4^v--?A#njwuP!cOD(QX<!ZA<ff@=;S|r
z^Fm7@+Gl}^03wEb+V6zeXU@(Rm$o;bP1C+m^)|}zagqXODELQf9bxWBZ?~#z*JUG!
zfKtKZcUl+Q0tP^_btC{Bs}jEuTsAi?ffx|wbnBp$J5QP0?&uhGbW|qUCBqD!2tOyP
zz8}5_oCe(hf2AsHf{+~rD>zyM)gfjIbr?;y%a(1zm;3J4ldfm4g8;?Xu`bXHSTnO5
zbDGli=uBib@QBFyTpisuabd`?Tiu8Q1jnW%nh~lR=`aPdh>(q=H7eSpYW#{%tEv%)
zW7^UkVK-1A{nasAd!ca0z-Ne}3DyXf^}ii8*K(VhO+svsF-s#~)Pw`MAx1A3z;{j&
z^}#LXaSfJ@GKN9Bs+y~!KZF+p&eMkZkmhK|PCk#{Rl%P=3SJK7AjzOCgJu~4sQ{wg
z-~+``J>3KNY4-YsuK}f&!r876rRs-kRZ4#|S_Xqvl_2ZMnh3(7{?KOCu@t)qij=<1
zqf=}-tJcCtr*yA%*V1<Ww0X+fe<|G@m}vkREdn>EN9iA7Vc?xIPmpB+<UeV9>DDHS
z^AYC<`b>@1avjaS6zIkw<H*RAoR@)t%gJDOL;~OiP3i=28>U?vY-^p<(|g%&k95e}
zIwAwF%dF8ME?WgJ?L1%@e+&xiC_l)iPuvDmt0SU5`gjXN(s&It4Hv5VumPW-oZrA>
z(OhX}7m@CWbi^*h7h(i8J}?EZw@T?QJ<3&CgH;8ZA^orlRauFIx870L8Qw>&C6=|L
zAOGM8M>qJIc4nT2d!a|iQXLTWfyM};0kJi-23v+NzXQ6t-)KZthL!CP@RTZa7Jh}S
zB}ouO5LT=sSOCo_C{T$hJ~!>}rv0IG=;_P+;}1l&FnLvH+6W@+RrP=>`DHyy!+qT>
zUWgUf>Mrr(X~2(^`~rH4=#M>G8;I)hz@64)J@jIK^Xo=cMnbCa)8GH)P$<>7PfNdk
z27x@!Z43)5Jmly{(1@xL1z4ma7atyC|9V9CL%$$rhC(vramPSZzbhN<DIhubPh$$B
zSorlv?BKz(&0nTr5xv!}gJ+>l2H<}2DAwVCh;)P{kbZN}xPcM28lPsM6(F%ikD}4o
zKp(B+6EM&&?Fb}4MLv4s0!?<E#%&j^i|K%7#KYBy>~I)H@DLOk-*g|*2G!C|8g36n
zy{f)r0Q~ZzhB}z~$PV3|i*~au!*KPNEnv)M3Tjk!#|!lANB>6GPyG3d5Bi5M{7wC`
z|KU6T;5SeG87=UfPk%ok4HTZd^<Ta85lc;{LZLJ|_vwXt^z<)i3O{MO<oe6*z(|Hd
z@4ukm1SAcCW`qV*)J#K|<tpf)8j?htNY39fc&Dl&JA#nZs~YHxVO_r?DHTZe13J%!
z#ssb62lNcRa&_Iq!KP}|cF`}S?>_%e`J50rJpE8P6&_IDLLP*<=>c|V=xmh(Zryl~
zJt3~W-wSt42GIwmsiV)EjTI?Wi;Q$Q+~{@Owj;3r;hWV_={8jRU|}(!Z~_a_8L+Rc
z{Ss|M6oI$_r|5H)Cen%Z(O~RCrs5Ra_5bRT(R5}8rmAtk#+Z7a3Npr$%eO`OJ)`<>
zfAU#EgAjZMJm&%HhLqirqtN>Qu<(W(?O@0rDl|c5^#kMrryD5k6=Q+arDf+A-KZIQ
zI=IfP$Y%YF4&HBGe?(}YVsGW~jr$pZks03B3P)@(emfExxNg76ib*%#E`%C)KfUpn
zwG!)~aknN@-%cxiG#kIYm=?<S^(6n|_w*2zL>C8Cz<uj8-*`sVU=pj|-@e%T^S6Hq
zR*t4_gf5D11}ojgvo7k-;P=f?AQ(pd`%^BzYE)d|a)(um<Iit?el@1$Z#~7*9sT*`
zA3gji2a_>Ddaz7tHS@e4S6^~bk0mq1=LJ;B2@PDKW^yR>j?zOB8v04&P2E7i<-hYL
zhV0g@`dxji@#%w0Te0k+p-=Qf8z1}8pZs$@U<}O9#hBAnxlP~tcYpioXz6{p4UtFX
zkVs>z7&r3_Jx-ra1!M5(<v&e)j^D4pSh-}SKK&mb8C}w~@w9L7=?l5x)&J>#|FM6c
zav6AN5k4^#FoEH>a>~3+>q~9smtqGUh)iKd`$x>{CEn6!YH*KkIUkSNGtL>RpDYfX
zXUPIzZ$W|X_+gc;Mw)9ul&$Hcn?Cx{7k<$OR+rDnHC_$v!V{P3f2;L);sbPu7v2kK
zKJhn`Q>DG@FCNd(+<N`{zkXV-Rh%~E9`nZXlipQjNB2$#gU`-f4hEY}_~M%u-upFC
zn-ud2m||PqyN}<x;m6+PFXz{mgC5s?Iw<r9-<}@o4^9EjJP%aQDRAix;vO943+nXX
z2G!eoS}Oa&;EBiWhlbu$w)gD+ueXG^x?N*xYd+ohj87h)B)K=LTtXAnAqvSPzcM@x
zNmuP)>3#a1(H}4uIsGOMDDo7OsP3n2WXiEw$LKMi$@E#V>u()xJW}oa`CBIxh;9dW
zsc1??e=2{;&d*jj;El69o3Faw<(aoG2hEpf*v^a-v(y%!yE|)%lz-6JqmKD*#q7#o
zRXdlvqJ!_bLze@6@q3r2uLPf7o%vr~oxgQ8kA^E7bX@cOxlb>?Uq0H3U#Q!WAN&({
zN6@nz4E4_pHTiE(kNQ)%%bTrqo17A(Mt|2;mHM))PT#t=_kY~M0S#~v-aE0B_FtL>
zpOl^I*NVngnb}noI}a_XM-9%v9e0gL$a~+B;dXLKEjKa}q(rt}GqUpjMC5+CDy|!)
zY-&kvG3KO7x+P^df7aKpfUkk{rF3_#wxCq1q<U1ZQp&w#Z&#^&zT|r2rHZ$lD~tpK
zBQvOZ?m4lTt|_&suBU8|M|FK%v5%RnZrSFPgUT1Ky0#ZDQ_mqd3A_i{@CE<I)xD6;
z$e-7rwQh+1S48RT22Ks%U~HFNoY<S`%xuf5`;{?kcdEV0&P5z)vmVe=92Eq3);1~U
z6WhgB&fTn4vhfo4wOo*sDk5!rz7AT#tBIb}FQ@B|*QOQ}b>+6J#2lUJQCrovOKPZ6
z8Ky9tYuAlOhL-#lGfs%1kFTq)D)mM8y4tNO_Sjyx$4#!~y+_M#@+<qFvzO}S!b*8)
zDq}jR1>;9Q{v2mT&P-V83F~qHxw#kSRN^feyPzhG8-|hIDbjbT1M*%y8%#;05r1FQ
zn_n!>eS1}PkJ9eDFBsw(xh7?=x~?V@?}`fS>|{v|r-!F04M>0uv2)t5pG`kko2scA
zbv1NHwlgcW)qF|i@@~Yhmxt<R+=>^<Gu*{1#4+KMl}nZVKTy~0Z@3FCH$0gi-0AK=
z?taVdv^}rhwDN>AG!dT$`qU8efuHSwl>VIG`Um3fyU%oy>QNh1sv>tCRC{FdU^Z7w
z<Xj`_*tbxG!LV^uv|PxP#0Ft)BnNb_(W%-dBzR&rvFlwisVd4Ia9s`;*RNr^U=`AC
z6UJ$PW1+f@ihIC*titKB<A=Q^ukM*~bExcbX}#%%TEth?OSCh;rc`GtS+V7V_7fHR
zA^YQee!O+}gPmh_2%{_Cq?SXjU$3zCwSWDy0T0D%ny0s?Hzs0liH&NDDrPrjWAG^x
z@-9~NUjB|I31e@^C&QLnI3I?wIYU(eA(o_hudud?9@VMhrR=7J*=>|q8WG>-fHCAr
zH*FepYC)xw738RsujGR2u^)1c<1Cbc64K<B-(DHHtk2&((pVh9RHgR3N~gOoRg!BI
z+dW=U*~-?udaN>j++Fp`%I)%6%ifCl!$Pq@1x|)(dTspCVJ}!IOc&2?N^hAX!vZy3
zyeK=_js2qhwbhK8OJ>Ghv+O$ZQ<>@rx6=X3+MbE83DK*bQN>u_quIN%nGK40;N&cO
zes~(*aRGq}{Fwzc0~%Rn$s`#b#iHn}C`aYWDUQDw^E~`&Z;2l37khesppLtf2q-@+
z)8ukx$ov_-IlaHv+eue1FMl__&-o!cpzEI?PHX*hJK{4JOp-Pbpo=2CU2f0lWKYV!
zF0W@N)lHR1-AGFDXk@&k_#>TW*h7xh?#pWc<(p7T*J9VjTba$G4=O)f;5yaL<e)%J
z+07+Y*IN?(faNhVJ>y=+s8bqAA>tu>Xw6RTRb$B#1^=wlP*5Klxr`6P5~?@Vr{{<b
zl@ZxGR*=2+nw#3|^}6Oa+>bqP|C{-p`D8RVG!iVg9ydn<VC}P(vEeU6%YiZQu=T>+
zs<;+gl%p~BQ_C)`cJ9jdBn~dh$yBM5D^*5ivK5%^w7J<FBxMsP4IyH4;=as%a;xZ!
zZ5F+;)kF!E)x9cKC6XoCEUuUnlFNjZO()YV@HCn>Jus<^irQAGY`2r8F-|b{%*~Gs
z`AfO-P|h=>A?7aNy6#oAR&kT=qWTwhdaD|Acjgbc2-TXK-)p~M+i0{E@M6l^w|?@Q
z1q8|o*c}mfZ^*9aSgzt8CUmeQ_b7Xlx_dFHJK`F*GZ`MSoz<$@&YUdHYjdXU4e^1z
zX~bf)swFEEr3B@!C?;D%MQMpz*HAO+dM(niplo$iK|Azh^6;@_DL;B`-uG9I4AqYe
z<*YK-4^N*0c9zMkyVdTrlZ%y|t}}GlBOmf${y_dA`@^v@FUSr3FbF^7&&HqgPfS=%
zy;g){LBhd_Yhtx+^`&dEn-XIt5;qN_S6q@w=SrrM{Y@F8iV5?cclAur2~g~Gswm>u
zjq9=6nxX90hSlTdyA0J=QNya){Y57NBqY5$9bpo%sg#c1R#H#6%c*4P*qH6He{^`r
zsYjR5V<XciNI6Vpp(4DakR!F#?M-D>ciG*WPa;h2W8RY}ucMxqi<hUFx6RgD6V^8^
zaW?&1|K*pQL9uMLJKyPVy&*I41+gVIII8X=pRq}{TsPbgvWs>FHC3{0rx_!zi8Akt
zE8?I~ZGD+71WLOm)w_wTk$gjyL=Q`4GBK%8v@8z26~7KMv@s*;`gE3*NLs5g1SDy!
zs*=}blu~2kWw-eeZ)Jo9bfnO@x}kW^YVqrF6O-<o`@8P`4^?p8TU9?B^Ky&%o!)_b
zuU)PTdLzpL2b~_UR^DT|`zO|(`->g%1LUUIrf~XY`N!(a1(}r_Rr_3~S6#{6>{EBo
zCGMw<i^)|vX*br&xa(5Z&kL5!4(ZD)IIe9A@}8`W^~F*K1yLq2gQdO=#wM+PrA(H(
z|Bfv@nO61J(Wwe2L2g&cIkZ<oE8@pch{<w(9&2*s?d6q1d3k*#o=(56{Ay%7^CY{@
z=igV~s$9(Hu8%FVV)DoA<n7v>Sw3KHj<2A;5V;H1TAONKjt^3b$$Xjc@)g6yzsOw3
zOv+Mri!h3PcH3&-qP>{NB5<w9ozg1IIS<S_Dz*qhUa=9S7r!PVi5JzD%$iJWQ1`OX
zWUZno9UZ}_aDGFfG4LbPsZWq4g_j~#dRwGxL3J(KYqs54q0pz}upk1O=#6O0&JyD~
z#oFoQ0=v*_|JcpiLu1~)k6mxC{iL^_5WySrE}J>6$Lc@vGwk5`^Z)ZUKUc7<%WY?h
z;*5Vq%t^{>i`H3X?_$KCu_vVA9ZrqqFnOFR8Ep*+LX6l2X=LPP*?L9Xl-cB42JWKT
zE>p!Uu9}iI*+cmnXN)yml!iJUcwNm<ZL!;koKo8{l07P!wI5TDmQv_Q?Z_?Xjs&^5
zw{9JM){q}kDGs?)%WkjwvHBOT>pZ27+r}5&(_W|7X(zmL5UgB|uN*fUb92&qUOX>v
zhP~F)r1zh-E?X`AvTae+E@WQKbY+a#Y+{c>{vMu_gALm<Zj{{h#0MK5+QU}A>c3~f
zuvGWpbs52nT2*s;K!=t5dzK}5u9mW1SLakpMG&u~;pVT}DC2T!y!8>aG+f}2F@y|r
zI^+I?E=RgAxoZD{*L}=JH=kEex{u`_y_zqldc4sdZ!gtuu&JElZUy?=%+0?%eu{tJ
znWnzddoSI*JN<J1>=t7!qdnQtz73g9fz?D&-Je};si?<P@-VK~fL=FzMe$rHB6UNs
z{NEK5nH$={-<a4Q+agLvY69cGC$RyCtP`D(L@@vm1OUzy$HcLxsXO?+oq(&L?0tHC
z#>->lrESB7+>y6)BX4`l+Oh`k*U$%uS|@*~o7<y)x3cYe<s06bU2*n}q2l)1J#MF`
zwe^tY{gBOSoAIdRZ*|}K9j82VLOg3-X=5S0EL%`?n`B!_?RG2pxfq@jWEthi(dNU9
zYn18HR@1QJ7qI>tvs+>l@<N7NV@0(`^{pn1cVm+Y)b_nfLTiY~TMmFWCc(+{j8?>H
zx=OUrRjawTZ%>UMPGNqK=1LA#fMj~>GOFDfjL%k2%HIy&bPub+!<7T>V`I#fojYvj
zU9Ty3*@Rb=8=2m0ow(*twBI=>%xz?_1qs-xH{`6?ViYAOUL{&GiTksqSa&IrM6}0}
zkumx~Spm!@G3<`aM$vXbWD@sWNlav&S#=kRP*SOiD#>zvIzDX@iy(yT;SiwQd+gMk
zc4=%pnluh~C(WUe>E)HCTYAi|L(xcA-HLrQm3JrIOR0Q$EE#=j?CLR-|9Nii$TE|G
z+Itqg0@?QdKZ)vNi%<W_CHW_{IT^nsd(=*m*|jR?WJ}4kS?%M7(b}+=+II<AaiT?d
zT|hybBr?^vN8P>Jx7tVPC*qC)!)V77=B0xxzGmk1$Zta_AY|#Z=j}7lSGiWR{Sh6I
z#7BnKQH-u2+T+U56J?K@X7+)6Vf=9SiE_cOn@5ILqTn6<FI&z3-DLZlRha0y(6!k0
zhFsJo%H-WQ`c$l<T1tsDf`c)j84R*>O4p2O4{sDP0uTdJfxEv)btd*??^jv1QEe+R
zKaC}w)FBAEwh@7hOm}0syR}$vRnRbqLkL8kw8zUTS*|3_JRBL*^t|%VonOx7aC_Ws
zWtIR2dHlzCCwZf6?=M$8Cx-&ay=k&<?*tK)e`57rYKHjc2C?Nu_wI~n$z<*`dW_CY
zXLi@5JecW=Y+#%a71?mxo9$T$?`C{b7Kx!+G6EUDo+TKh_*^H=ORE%?8*xcS)@}4H
zM+*_~6-v{^kl-p#svo<h{J7hCyZ2YdBZZZrBbS4v97|olsF9$$PP>v<r#+nV_KrO^
z=KhZNSEc><WP~YizXib}c+L-|!e9C)cMg$aY<}<TtTckJ8fM&2+{S8U_Z89UhU_MJ
z7a<NVHr9bGSx4A{v)4W++ouwQvTMrdl~Z$xmbC=&Vr)_e<H&PKt(!TmPU?mCrYkjH
zb=R`WCd{uWTgSW$>PbYuRB;GqII7Mx(f8{wjd9A5Oa#$<bnlow<RLpfZq7uCV1MuR
zgVx8<IGe5eSK)sRilL?%|4|<#IkO$rnYx0d?ooGTlSRg|jV{>4`^sYzI_lH01_}RQ
z){EF1azSns{js@NkFh61tjm04HW(WTe-k>WQ}`h3rmeAF3B>E)OwW<1-4^Llsq3i7
zNp;%pNf8WEuTR!Xzg;iCjbrt8Ze8bScM+u%>b1>FK(<=-<jwQ^o4jgY9V@4M+!d^0
zurf2cq=TpWd(#)dL|$W;Vb1!P^!J6f(b+Avh3s||kDiFc&bCq?4i!Mpz1ZSz<(ef|
zYQsRU9>D)_mNG=YTMP`M!A6N*=6<S@RY`8XUk^GjR%^o;G~`OhoZqBw2bx|b=TvGz
zEBx(DX$k>6oJWavzh;iSy`oKa0llcr{d%9O_HlR7J?$pvSRkG~Ua=qZ9`kzKZ`=9Z
zh2@}rB=8^7JDoM^gWZ<@#}{_sQbjqx{Ds-;bK#A#wm0OYfZQRIR~pe#uTg5b3tJ~0
zNfqQ<Ui>*|Sh!R)e`8`}wk?YlFg9hAjeswCgFt9fBBa<kL;H!p2uSKp&(&Dzs%GH%
z)|e&tcAH=`Wpl<&B!@4>^35G-xGoK|FtDo70+IdEUe@@5yj?w>|Cxse(&Of})0-<C
zH;+tf2+Q|h`1WUp1FCFU=0(eBb+A+!HZD&Z6#`YFLPtDG<IAb_E(F&g%296zR}lWs
zLN=D|>$+lG$Mz<Y&!`WwwaEmt(pW5?+66)pKRv|>S<UK_+E%O4y+L5TV;;g&za0YB
zN+FJAU?xCIbedt&W&cuSn`cCG$MdH>_Y24xtqw2<4oJjihX0iHrT_Z56SHP3U{%vg
zYgYOriSq!0C`Q$u7-v0fQZ3KOSXu5x=N#4nNJYC%1GXO~sqlfJ_3RcSo7t$^u4k|G
zVU5wciA}7q*c|bab~BQZI)`1-_Qra7hw$UM+KC#dTq>eci*#kEX0#rzc+~l?gLxcT
zt`Av9)^%IMsD$j~Bmx!9NAj&@+kVo`AGY0XCU9f0G8F&sW?YXx<3Dwy^f%{(!$-X?
zHl<rGU@MFpBEt_AW0OQC620pn!(L;n%E6MwacT(DW_X|^rEoG@w2R)hN{P-#(N}k6
zv?bq=-IAS@IKr;(iZ;@}z~6v4jc>9<h^8v4%WVi>FTe@bT2(5!2r8*uaOy|kyS=^Q
zjm+p^QqPP|#FW)mullC@AtCA5Q+D}SuYEi}>8|b1yV}iK{+@GfiAACp|MSA{ec)FH
zVH;ZY$Nl<CnR{xtrDo*@alcy4-Vl9YvB>foQNlh#M2YS8N|lB>1_8e&Ud3qNvnUob
zYxsq7GJ7K?0rrW#7!ms;Vg?4dq+X-!n^sBd1AiH4Doq8t$iO8QJ#k`UmE*;dWjklI
zes0OBo8=)V7r!NFKIUXA3tWHMop$e7^vV2Qz3!hH^S<b<s%WloBnYgxIcX5RJQe<K
zJOrC!#+lE&Or1JsRBY_)e#`i}a4)Hy=^S98Eyr;|8lIE(0ryE3*99_I+N+(+ToH6+
z+nN&hX9g$GcfDD_QJhDr0;ctn<%NHdX5Sa}8PzGRx=`6^;=r8ix}|Ne86yQBymo0l
zbED_NjBNFK?P!nZC2gBf{YlSz!QNT;w&yST-?>r{J54GI_W$&uu;V-+g4WAz=5sZ1
z!nq<c@_sogcEy%d+bTi2aY>tU>DfP5y!b|=0@7ssW~SkkuZm0A&9RMyB6|{>61^&$
z5PP&a!GFDl#H}x2>M2ZjM^swc=^lc=IrT)v9jdtCl=-rq^vcVGenUu<UhIt?SEHTw
z{*PVv>uwO0JuX8}T4>Je+UeyALvLG8n<F#23gy&n|L4CJ%3YntiM5*QpQPn0b642N
zb4^>3*s3uRyMRtrta_)GO(fks-mrbkh4p=$t0fkA`aTe>E%;d5v+--0w-Url6(cDp
zWtN12!ES8OhLH9IPo)(wCq5toRC6QSktNT20)q(DoGU%<tQ;w<#I2!*x}_&950=JG
z9FxSGF3_TT7^!;F1!Ew-syIxEw=x8nJ(T;CIH?&<s#zO)y}9iDdvQWeShM{vOY@Jj
z0Jm#0vsv{Rn`1o^AmCv3E|mt*N|x1Fvo;^v&im};cocIUYs|}h?4IkHr9@{R!6}o1
z4&F#pJGsYjDf_4$k9D}vKLJg~NJrACNfcK?tAtfmaXTv-)&guvzg8NeBP&eedN9j>
z`18ENF<4b&cJ)JBU3K%PQ{GeFRksWz^i!Kj`?i-GS+4(Z`G#fYw6zCHx?%Od@Q2aw
znqJPb-UE(L-zQ%&RyB`Whu&?^C_uVI*QC6WK(1EBTq40tCG*C52O*D>B7aBR6iinf
zLA@SZ%#Ip8ncb_gtW06~F0t@+c)=OGdfac>{1dCwi|NHQf~S%-*S(G>R;fJX&fy2U
z<Hq62Yq<JH3Uza&K)ba2HselXMe!$6Z@Q-y+2^sunp-)xtoG)A$0NMme|qRa_pRuP
z^~1Ms#DP+@KGSA@=H|El=p)PA%NZ{t)2$<-ZL*8%0!y+bBX>{4vYAZ^co?dBR^sc~
z!;M&d-;(LjE6T#oD;#7-0x+or)^|O-8Y{)xK$B!eg@A_KQujKJq7PKPoJIyau$mR*
z)SblSXKmJ1(lbljwJumOM+i4Gooa@z@b#vOKHjN%?VnZL{m1eLDo-6Nt9@^R%0KA7
zfD=$R%{#wq?p<1%xnQw@@@BT>obYrW<BER)kFxD0sOJ4!lv>RgH^`!aqZ~BbCT-Uw
z=wHv1>~q+<KY(q*YOV@AQ@Kgpb2A&;l<8!P#AIR+n0O<?=SH;cY(R_afy#Rr&$^Y4
zR0-9q#8;`)w#pqQ$Xqe#gW2R$FS-d~ovGAVb!ywU+-+CYk5i{Bo$5h#?5bV1pYXiX
z?$^qdDYHD|ti0#Vi|^`k5^~9U>VFISGhshC{felFc<o)(fY@CG)k)l&Kn0mL=ingk
zpoyWX-XQ*Ukyv0OhdUqZ$!<3G#CE@%b&FZ#hBd*O8PHjC)NnPTk<)~`z=GPUQWfPr
z=BB_-bB9y5#6H6PaY(C2R0q;#e`udqN%dp9;y$5N+3Q;N5~p1+7j+Jp9(7_RnVE;4
zxb1t+gc*OrX9veuXIuV2f+OIBh*gZYN=}H0#9N8fO(lCvtA{2#%lYwgKF4>I31~8Z
z9&)aDEDxU5UXxSvGTkc|jU}Tuf%49(RBcsdG4ul?f4aVQ`Mz!xN2X7vQJCo|RjVy3
zRDCDlhf1e@;7z6?c#oy?Fx0vFZ)bYeAE6DTz0K3wV$vP+x=!ai?I-o${eSh|KRaGH
zavAraZvAliicY(+Kjm5LlRp}4zD%LF;&j_V|7BrW?7C8NlQ#4*E$h1uig6qa5`Bo3
z8}%-l7b%4swpu2{tfYE~+7JVp!R^s{tS8ZeK=o>0m(WW#?`NYdU%|z6dImpCb+dj6
zdbcU}EA|tUsl$0drJT2a=uUj$07p@4ziIZ3rY~0VB?YutTXvJm!)MuR6R@0hU;8{h
zQF$2vc&{@<jg#r6^p8Ks{%d^7XRV_6>WkYYQDL`~qohfC<(x|IY%vd2v=5dvO`5Nr
zm5y+05!Cy-L6kyL<+`}8mPBI0xW*Fik*Si{rpFKK;%br;%@2i$chg7J*Ht4|1umZ^
zlpE8|jOK#k-Dx%j$=hDlFz@!Fo2?|r@<R*mzMZJ1-@)VuQJmQW<^ycIGDvtP->gos
zFxUWKZWNTh*%IrM_spx0Vq({gglbuo7|9LBZzwtL=1Ul3n(pNA<b~}ou}xzm>v)54
zk6aXQBx=R%{aM1^?M%V_IFMkb1`&qMde+THFX_dsp^|ReA9-IP{%*<LSHhT#^Xy#f
z$m4Z$2u>>`Fs?=l*>g$a-R)>yRCF&lnfe%P=fg4c8{V7yqf0BKNms6VSoM<);Ng3x
zqu*g0nSpa`#MipI$c|+6B3V^evR90GmA=bpTjj*9$&}lAIPaihb3}_*y$hzq&XeCU
z+WO>1gDlTtqNq@=b22&jmi#E85*mPTjr~SJ`?6pg7{zlcMB{92H1W6WTtEUWKT!5a
zNJg>Hz$Z~nxd}B#dTmnA=kxd~`N8rrr>i{nVE##Wo0pF|&CB3@?cp6(@58tGL-PVo
zK=}F0SB)UueL+r$qKwaHw)90d(gL;ES#rlC4lb#l1*E?<sw*u3nOvchvjUL%MNGq}
zu>ogB$*(6Ogo1?ZE~IuuM+-lXjdZivalh0ycZ|nT0D3%MT1Xa}ko;w5*+KI4)dhs!
ztk{WQ*&V!kjBIm{H+0;+`s1<lF9c&`6OSzCe&}V)b~#E3{IxCa*RA66_aKx{55M#h
zh*bvt6f>ygjY(Tdm|K)_!`8UKnC%fG5KkR2sdQ;peK8@gh)L2qYZ;aTH6CnSd^wj$
zP9|>a*3z#R@M{qyq5-wlo3>-yx&cc%d9QXImjvv@EqQ~Lial(PF8O{v>a3VUumBJs
zurBy!I&|$MjdkAJcHFyKvAq(`qWP8l*Gw}$WLkH=KxW`M$UybWe|?I=qs>jEj=N6w
zpO_<zXrlyn%O#-n?dsQ7i!MXQ3P$%uwMjrpO$c0#tOlLQBiQYYb-71wQHzOHva~cZ
z!s@I+oMHl4nkXHBLR>U_C|a)3x9&?enN$43F(j;k=^!}zb;^C;_6Wtd9e44YlC4>9
zJpXaNu+?)M2c`bB8DJZ%)}K83IiC~W$kV<zO>6!#T><mZSi<g-+9Zq(S^Y7css)6A
z5wfKu2+*~32tP7-78gWG3@3VGy`r`X?1m$_Jz?J6P@74&{j=IjqVPFe+iQS?JgIvT
z`3a?P1tZQwm6Dq*d2)Otz`GrJyB_t1af9h76i6_uPTNI{%H9F*fcv1^<Bd<cllf=&
z>rH_EJ`O~@0(*aE$@<=-x3RPDn-;az>d(r*l-ah8SxRCJP8w5hWJ(zgyX`@zY@1Zb
z0>Ck6Qe89$i2=gx*ggVP_H4y(kZ9s-I1?-O?GmerOZYn|p8@zktih(xIT9G%HR9FO
zoYH2Q5b2UVsOSKQO)`Qih@uVFM}C`qRh@QixqqiSJocFVpeuXvArPUxbhBI-8g=%u
zZ2;}r_0{H~CJnurC-0tFZCg+q#P-bQ%w5X-x-9kWkv)lIk(d=Nh~t^W@OJ?2hrn<I
z{n><xz>|F=6N4s$i~4TgYPOUmY(wZHq?4e~51=>S!#|zV>sHTVB7)8C#t^$lE2GI)
zl(FqNuy**t$E`)(RIlm`l3i93N65bFnv?lU-Z=g7rgnOux!zu9hk0V2ild+W&j-(m
zpk0u^v^L${`ku9x&cyIAH_CgnoqcUtuz*zp3kkT9%nTsMj6U2WUDJY7AprF;Zt*1`
zkGNx0vYjaZQYK!Zk+#M_&f_)ls$y)Bd89@kir82ly{>W9o3za`1~pm0NAbwyutiY6
zPPwd%H(k%2!v`W<@E#gNYxa1_9|zvChBtH76Jw;ni88M|@T=BLxRDqa*J{Ao0=f&~
za$+rOv;oU#tg|<}S}8euv>t&U#0S8MqCDi+rEx*TCNdKMC4Cp5Bc!=7=8BAhb2L)J
z7t&fDORA+NkyTyDjRcAAcF!wkw7LA{@%=i)*V3@w?y7y>J8B~-`Q6^wUR<4AHb4IP
zz;*`WW$yvOk*`&MZTUOwF*2sa<Fg-G>687>D{cE}BoGA_YRyQbb?&=!a!YA4Ss~Bm
zj=Qd#M{26!s*ir3LufXtYG0-^VGv(#Rq;zo-36MFboY;RYl<aHkHlj)OO<bvI5}HU
zGPRQGbzKe53><dPpC^<il4i&`Fj2E&0hW)u#wB;#az5w%z+27_T}^q9pFip5xxyPN
z2AuQuzQ6VxAM0(}kNd&P@=S5|6&!upCNi-ev5SbS<)%#Rx+#;tnFQH)507ycgqw>(
z?qsy%^CAm8yOe3i>SqjNca~NG=4s$tYtl#lR0m`Yf^7h$qoE?J#9s_I*LAvkT~=%9
zShBUeyz)qQt{kiskQRE%AN0&|e5404rmG4;$(6?r<a4WI<Qn(?G=NY6=GSbFEuExP
z#O3~n_T9;`p4T{=RewFxb+&C|0xVgGwzXLH9eI%8StTEx+@9P*)5emf8`1oqAq@gp
z=OBtK7&^}05?hpS^nH-MlIfGXUX=DO=Yj;|chT~XfF?I4A($ax39$;g$Ydcu$qz|Q
z?{!CIXq-%3IY4Z{$v*8v!9I$wtWnqDV^7&v^J8OUdp{(n=y^eoZ6ce^%_QPLRs5OE
z*P4IgWa3k!zQ3u<Z+SgI+-Ph`JPIaL>H}I)W^YO1RUwra*^rkD<Pxr4M|gw4C`^(b
z6}zv9#n|9Yk?4`hX9z1*D#NNi-<X2{zAllm3N%=`RmmPjx-&Vax-QwjgYg)%$3MR?
z=G5<WmX~sO(p6T;z@oeCZuRIv=a@StpE&NCAG<@6Jn!<#ojLE5xCwj3G-j?$%NuV#
z)KT>IavtB~;$&vSRQ*3#mogg(W5DT@(Ap-uh{rBsHxj8%HwOV{Y&59>MeLk*SaqUn
zUc{yr<%=0oODNIo*4U=l{W?I%WTj}EBM#QM5~>!5KL~s}V>LaU{$^T5NQ-LrJ!vkK
zkAas4+-8;*f|atjoU`t1=uR$X>*s@RvSRNa!(Z6x={(C9J{-gAB#e31iw}8kTRxet
zQP9`th4H07j5eCpIz4Osv3O~%tN+DU69#!(NJ7SDwfkm5;YAbRUP5^!A_J&(6zD$4
zsNr^hA<><9)#z`3gK2AjMomiX_H0pEph`ewESFYSXhcBC2o!^^EU{N|0W0!kYTRoj
z(`81y0gM)IKkhOMSyMD!h#fi?QFh(r58My2TJBIe)r*ELd(At|!3$;s(z@~Fw|7vg
zyOEFRN-ecbjf(qZ`v=4xMI(s|Ky!NyHJ4&A;RqUL^c{S?P?as`tz=b{+AO=S#Xyhv
zaeJcEpm{X7xzw!<Ek3W$E+Q0Xbyck@qh>(2*;{dPhbww^a9xIchgqdml5Vv;#p%&N
zs5bgN`9%;gK)fG}mDLMl$64l19seFGV|<G8ke__WHZi!eg-<LJg<q|`jKc4DHL=x5
zz8mW!vA!pfnp3}S>~bUH(4UY3TyPKg5{BbBVQnx(jPyioG4ZatArgHhoH~F#6P@pZ
zp5RqrZyOoi6Iy*PXkwXiwX*8cVu|&2ol(?U>*hzi<|9M&fGz~u!+%G8sC{Kt0W0BR
z9<rvFx5pQUcA`Q}N=pEsPF=9Vt=6;e-7%#%M_MPlws+NwZ931tXgs4Jl_XkX84@}h
z8A>}>B4big4utwa`~@q{ncUqVJ&TzvP~C*_Oy9eG#)SkT-$H=JmA2HQPWzjw4qS_*
z(|Vvg)pnrZ?WmnEz&_KjWF%)EfdS{~DMGZQeA<P5<^iL!Ain5bO&xa++k5Q;uIG6x
z<pSlwDFO!O@X$AY)fy7fdI3ATV5p54-?={7FLq5R@uKReRK|_l#~cU@xTcopp!C(b
z#71$?tnBJj84_+-snjz#`inA>jKDBiA7|~-``wk=iHII;ZLY{|FRGdw-RmYwZnFox
z=N&05LD(VE<0J#UJ2#};+li%p&~*#V=JEWT+sS?ax8_+^VL5(6n0L+y>%H#Jk<$w5
z>EiTk?213z*2Y0(u?=eXyNQE+Z6(%N%Opn$DaTGiT8enh!8PZCdBLPcLw|OA#@am^
z!*7oC$W|W-*4rLf2@zs&bV~E|CGt5_wHgZ-Zw!COPPvP=DuGHR%g06$+A`HK3e6sL
z#(+F&sM%1bHQ6Hlpq<W@@=uMG?fhYP6z^e(6BkZkUs{`{<h6ZG{_+Z@Fzvsbp6#xo
z&U%cyGunQnCKH{DiHe)cN5*n)lqmC@7`kAh5U&Zoa3emz^SKto^-p{N8%ErluoLQf
zb`FsmAjjF1bb0PA_1=BG*5Ikv+*(E1dg#ggLrY5K+{3kT%Pn8d6-*Nh1QH#y<99GI
ziEn^Tqh0ji_u7+Vs1pR{V=td?zdbiH?Olx5KU|_T&SsFcdGTA{|J8w^LX&akY}c9D
zt~Nm&+iCO=3*K+IgM)*`%3hblha`X5eAnoN$Yfe*_LkU-&|dECyDxTsW+L-U0-4FI
z3T7&yb5RX-PAo#Zs(>?9SGlZ8R*cF4%xDecg+8oXu&3+sBY+`II^c!nV!uxUcOk#S
zds01xJLx5VaO}AIv%K3Il&6=xcV?Wj$DWIG;zwWpmA%f;Y<x;54Z2>bQFTK{r`HYR
z3diN$uXO$h0zhwRO(uW6k~%y#mV+vWKZPIY9VZp9iB)<+o*|ySB<~aPYsQ4AWbdBr
zb9FQT8yqKC+ClP>f7ZwhG9itBXG+s4jFgIWMKmoxRdbbb+D?^^jhF2pNFE86VT&yf
zXxf{8DTS`L3*E=noZGciRY0nHNI#9{{;#0?@0g9{mG_p#PkfHMo^E~CDtzMpPRLtg
zEnJ{cFK5~oV&pLrli6#TwG3d*uED{?q$JTYngm}!?F>-)%z*>b?&BS7k|zCl5u)rK
zk+uQj4EGufg4N)<hTBk=jb)q;PSAd4qpOCiUsCUQ?ifI=OHk_~OhY)FcP_E)&!%<r
zu~FCUR;9jy2<FE+kBtK`JmekElNd;rmh0uAca|^UH=e**%UDx4j(?^3Sy(jF&VQJF
z_oX%2wZ&M>K#a+}m`IAg*j+}i0kNIThuo7&wZa0xBBGw7oEU%FY}X*0hN(cd@HX0R
z#th@$3=zS*jKX&Ozg6XGl_bxz--89KJ%Q?E8V)Ec18$5==%5ic(&^M=Y?a8}K0wyl
z^M>MgI@-G+k|ojMk?BamGPB*(H^#23Z=gum^6nP^Oj6}bIco6)2jbr~wG+dH^jp@y
z{pWY?6Xh9VFw5GMenDKXRbod)e9<Tw+a?L4b{&*#?P&RZMPQU_06qX!%RnX++-nn#
za}AGTv)ndm+%!Nr+0K#Jljt?b{vuw|PCn9&Wbvgjx65gNd-_C#MXm-KF88EzciUrl
z)VbE%9UJ$d9`!vypHPPa=3P^6cVO?XbgU7Cec>yF?qt^N<1UnC$IqFU&6ST$b1-9B
za6@nG`<L$&{8?+tLCU6$>6*VN*96#xe1^;z^mTILIcelEXZ$hXw}m=<U;4sllcQYA
zWcpMob655*(#@ql{)%1Nmf3c_0T?zYyyui|6{dVuF$=aNF50)2(m7erJe;;y2-urB
zaX>SCs*!@)9|YuLI&BCG_O>jmVth3PCv518L!NoWTcX^`zA({x`{Fz&1(N}IUQpL-
z_l-18{dEJh@IGkZ+r_3t--`_d^DPx$O--uXhjr^U<f8!>vYVU4X1R%bR>gego;iV*
z{vcK|er-)E8w;irv$#WGK6?8czyn)|RD@kaE-9!4nC&TyPV3=gV9vO=%b*VBWrtvs
z380S}Vt<hEXm=%{Rx3LzV-Mj7eI@^7K~pEaWrvhds~LbjJ@nH%+MUZ9I@e|Fx?Y&m
z!%r;MHv!!^E0foZQf!a>O*w%plpmFPryT%e2+~O#VByBT{*AGXkk~JXYsx(+m;@b)
z_UV{Rp0{<=39oc8rcg|YiUO7(jl@D2Wc(j3d7&VObz8BTAQtLa41ceqwyMs1a9!Q>
z`}T6>;@I}Q=J`D4p=eY8%5^YqLqn8$TF$*rS)nEC&)GUp5!2^|xy9$RUzwY2+hX|W
zd)&s^MBf|Am6Pgl`8O5#@L@OSw&G4{W$So@5|gR*?5J^3wl64a=bpaATq0JIggL9+
z1>$o4d>y0LSO|QpUrwL6l!h;cd?i-#GOjb&w(6QpF%#qN=WDO!3CmdiQF=}6mdL97
znya?jTgSGJ_2!T1q^vtSXnw2EQ+SQ=GlxoxwnEiwmpY=n`ODv-U_pZjnED$|P&MM1
zuEaCi(cD1RdlM^^l=yEb?3jmk1V3z`aHyu1@D3S^?5fDtNi}NN+tsevgzkWbOWbuF
zqKb)T6+{5Q<{I+R?Ye5!E2SK7G--a`bsTRciY*QK&oc+A#v0y#ehj#3Kfs~a<6-pj
zq?8K<+@!<UDzoW;nTt{|!Fr|ZvwnaIJ6)g1yd=-~gJ7A7-K&}F8QsPT4St5E9Cn=~
z(HO>>!GRG8Q*RUs3=G`~Lu;%1v+SnJUeYcVG-?)U#FrXC0edAUH${so1pJra7}m%k
z+o=>jtD7rro6ix_b20(B(kAGuCu+3_npXANZ@T{i7q60XZS!XU{$IYz64?FVpW9>b
zj4cbg;J0<-pY#9YcPLIyDsRHN1}_0(7`A$$&)kxDD~5uf#bgsv8KpyiL@0nUWv5U@
zuQo=&dlTo09XgN32tbYb?0t|9#iVgiCHf$T;nzV%0(vHSv7U$sbT(3Bp(ot4h)1_u
z!}TD?SA+JB14(92yUdowv&%D7V1SF!VN_CyGK+ykapkJ|&|Oo<)B*P)$Zp3y^S>3`
zVXuA!zOchi!0LqcN!x#FCLr@UdZev5t!B4~aC}iN#df`zfd8C;7-lS~6dth=)sun3
zXb?ZGj@$a%=VM!pD{_*g_y^fl_*B@!o<zJPJJkRh700#V?uSrB*a7_ujo~IQsj+T$
z31I_V-2UY4!^=64S*?n63Q2DJ&?YyTCjx$aFVuy~175FJhBNu#{=6N{9r1QF>>2Sv
z_(%WjHZ)_s@J;K=tozNbH`1C@v^|q@-z6(l(&C@kHLo7dDoM<Q1B=3r5&`2ZVF)zC
zaEo}C5Gb=T+XKVpW`;m+L$=G+B;Aw-e9sT)s@+;0Ax`Ji4()Zz!~&e7uh=QgQFW3d
z!D|{HIx^J!DXPMSTl4!D=|Ah(?Kzfy(%znb3@+7B`CG}g{oWuzQv9rWbSa=A7t^o&
zm)i*Fp;12P<HD|Gx;DYC-<T1xOy9N%vDgQr(>?fT?&D77<qjXiQ$`qxV!hL*2ZPcu
z+pfVf5Y%SN-k0sVBC~z>s^p8ZWz^^+3sX|TYmcOH^$?~)V=Lo~Q6Mhp$f~1?cVW=v
z%-t$U&h~I+AhNt%r&G(|7xY+j+Q#hO6!{}{EH${CXY=2O1P~7nZT05qM6hJ-bq-+E
zC~qBXIehz|#2{b8Dt}dMnOdElyL*cPe_|7uZsK4D2M*<$Ss;zxX%Bds=@D`|2zsi%
zhN3~YHV`Il%*Oh%TQWB_DQ1JpY$5hlKoX6dfS!g>sLE1JKaIco|B&@IP;s1Rz9+O9
zMUyylsp<wAgaq|gb<rR`+>O4h_=7I08-&pZZK6?poWztG<d4KQEv+VZv-d{TG!csB
zD}m+2IZ2K!EO|WH$&SG~zS%u<b_7BbWyjfwmNw(enVD;_$Hz10&P_l*Uf;R1clP%b
zk}b~#Br7K%)m!iTJ|F+*|NI|4bZkncpw7Fb#&fxJMLKdPhC<TOvWs*qLh*9Q8`K`B
z!^&lboii|Rce_u^mXO5wr#VARH>_JZGEBb+6T2a9oB$JTHo}XV->Jn)W+&Yut$8!A
zK8VG3VK-ut3d?fKE{c+&;ZuAGpG_w3OYD5v+z{r)&p;k7l=#hDRuIg)B(dj_1(%3d
zPJ}9jLQqnUBF-JA?3?w52S?6lAH|7X8JElJj!VuK5Dsv9tsi*K$gDH%j#L+q2n_VK
z1-Co$LNDL`CjH0hEes`T#Qc18a1!$NI4ul6EY(icQj()WA1)co_%W)G>Yi-4&HSps
zy8L??PLItkV2^i4b`fbub>_UBHL*ltsu&Vj%$kd8QNLkwgBw(-bDl7~g-13jv)`ed
zM}#UKP1q>U#u1?owS-zBgoO;FF>f8UBeaqZdVhDIuWN9EkPY^a9HX+=6pJBk_OM7+
z-XXStcD%(IraG|S`p3RgR)u@H{t6?Fjxe7RypGcFzTQod6F$u72@cZ~xSO_fDGZ9(
znQT34Y)>}nRg1=|Y0<yxkb4ae=F-)fHO|3;pq2qOeNL<I)LJ?dMBfeC>&a1$-#ZEL
zZq2!d*nku&*`V_eeFxhrUpM=F$9vx|&?6f^mgTw|7M|}{uII$|yH?u$${(M9NLXOw
z2j2A4Yd_W7dqvo9&GRg<w?(oDaLNvctm06v$vXIM@q@nJ^TP9<xct_Ynfif+pHXO)
zLA9Hr4ZA}9slf^T1Q4FFF}~6G0ni;lyX_gxvvkvKrx0xXPq8CSM{Ra)Kl_%+VCxqm
zRDq($B-@jE+cLdd_ENaBbLV6dBFrrD@2E6t5Dnw*aU8d(72JP5uEg8PgJ2u-e@a7%
z4V}m<xl;tn8LU9Cs-S=N;gfR<H#zL<2?9#WI_k^=^7Za<)zGeYsi*FC+V=eB+~ALo
z7lnoK)=9c&|GJoZpIw`apPK%?<0-c&q<sDRdhbdtyc-~I;-*<PV5w97@pjYx%P*EP
zd3!LIBa!4rusXM&AH%HG&v6(%q%|S#bZ*kNO^1!9&Mlop7>e>Tshx8m*f@#5gVeOR
z#=|L#kt33Ev|D#sm6=fbp@1bq!&5)0kbIn+j~821=%Qn~64|qDn895o$;x|jd)+gc
zj(3mj`Kx~zoVW~;GJR+I&1m(NXz}D>^N#U%Q_^mi`gLtq`(gNZ!%oTrhaWW#>akJt
zsPV;A6UT%#K;#RyiLpAO9IsWu_tOxLtV@K=6^)ti+mrUF%By8PYvLxUpiBo(Cb`7g
z{z&XAzX;%$RbkmHl)Sv<;=c}n^cTs<`9<uz_JIVn1N<zuPMW;{R1P_*LvVfyP3K}?
zStzD^-;Ac+|LmuPs$cvU>$6NwVGPwk^oOa@=J&}YLObI3>9JWe+u3f`W)E(RRb>Xf
zm>XbVF0ngmTPc5@9Ct$!2?Kf{^T~IJ6O+`MNq(y)xk^OtU44ChvVdSWB=?|=c3ut`
zR#++5J_3b>M4uJNW<0!r%U@stu#w7+ZBeG&oGC@+fp#EJs$B2aGs6!}$NCQNjlGYi
z(*5uIb5xESzWF=R>YqlbLY#R%x)N`$J#4^Zo7CFEt%X@kb$G6+-MZh)dUB*Z%YyBM
zW|Y2zhGw2zMK>fnl5|58r5H`gdnufo*fwf`2MWQ<#KGXbCHH7?)V#8nvDXy&r)<+1
zw1x-IrF-}E3jrZ26pJzi->P}tU5<IdTNkq<*K_bgxE8&8i`VC+(#1BVQlx!#{^~}(
zQAUlOfb8=8Pn%ccMx7KO=wGUzqfiSL5@~B{kJ%%R5fBAMXu&UUEZ?Zr&Kk>ME&+d9
zkp>SxpG@IN!NY3<GQ~N0hw^bO)W}nFXkwlM3xT|%Tqt<^RXUq{H{JJ@VhZ>*mFBU_
zlsY!AV$*Ju)x6DVbDHfb0<10W1FrE@@%pzZqGUilufp4MkCk%+bJ^FTemRByXf5vX
zRAEZ1Ba1Uz=+HN4c1zZm^eHpau2iJ}Gt>@H=c1|R9dYU#RFw8}v!ioG!>=QF(UF`t
z!XcB;B*eX2dvaWQ8Ns2&VIesJy7%-CY`VvY)SWbr7lu(#9|yj{Xg68MTv{NVzAbK9
zEDvx)o?$_+AP-4Lj)1%HsuNHB=ij@u$XE>!kE$#2hC-6expp?emW~pXsCW~(f4Gn|
z$Tj3q%F1>nfJjnEVrZbu$+}rhI{P+vHYFk*l*YFnHag9HCLV)lmT%{Sl*b>#0X~g;
zY%UODc6fTuIpht&YT+9}1k-YR2uM!o6YPu8{H`^^t~4)OMY>hgp&W<(g3G~&VL@QJ
z5a~%Z`iAz={tr*rr*|+GLy!M(w)q`)p8#pP)0|Or`p#Jsvyq5h3cPag4r9_Hentu`
ziHMHo#eIA?E2XTmfq!jt`0m*R$hPQJ)F8e9l3_`Of(3}A!V7Vh0Y*c7YmfmR<2$j(
z4xS)a76Ub*&I6t0g*dFEF-lpIVM|)^0UcT1W~;+<j#wY$+`e}$X`~@wcL+?0io3P?
z9nlk$@vqi@KDBEmf>RiX{)m>7DI?7It81X~ht<Kv)7THH5A+W3!qQm_EI%b54`}QL
z=vhM3p~1Wywo^+6mGy=MaP+Dm`Yl-vL1>G(5PAcvSntcn34I4qdY2<Ug3?JLtNQh$
z7CcZ=_@Nvy-~l?~*1lDmURBw#GtTCWdDIDYIM6P>>kc*XX58LA8Mm^&{!i;^4Ik5X
zfYiKbtxu)8nbLk{WAk`9k}p6Q;R1DYP1R4q*SseiNp)xKVV#zVU^gO>Es<2TaYkeE
zNSy>PD02`2YbApDtpkKqTZx$1gtNDVQr4bd9*P@mU<hNZp-q|mZeOsIR+_tziA05W
z8f8CZPohyeh9(N3Sl&~`c`v?4Q90fN?14~+^Njn4xv{}sv{LvYlG1?wo=JS`!O#CJ
zMdVmKF*NDd=+D;HgzLGZ_dye!*1tes)4fEzHCT^<p@THoQOcsSLN^$}Vo!?N<4uft
zDBK>PRxfvkud$D$f97+fuJG?{!7ZsuaH;(BH#J~bnnX<Bh({-s;0R8r70W8c^%j7@
zED*ByciEP?Ihet{<4BMYW72?CLMQ@zc9+8mws;MW`73I9ZJ_>t?(C&XJ$9rw-y5v%
zgmzD4?u2ykPOJ>C{I;G)-AzVvYI3m_pA~<`*hxybF>&_*wb6taeY0IvEmlo64YNc_
z4@0pa_$K~NL-0Uz!9NSY*`Rw`wefONw^#M>{Yf&ys!>zZMwNrT7|*r@8y2MHEN+de
zdO{UKrlXVIQnuFf)^)tlaF*CK<DW+yh8~E^$VUWS1pLhL!l?q=hqcRD%^!esy^?v-
z$#`y)*OTeUxfcY#ZTX4AzccrX$XpLR0x6mDgQwp5y<esV+*BP`>cnyZDF%H$(L$%0
z*`)66+%`n<C>st>SzlF2Jk|)&aSB_swmcB9y{So}{z#-D>>xojmNYtNQIX%tL8A}b
zC?%#03!8``7ZRIn+^w+qt%>XeO==<Pu6#pq#njX4yBLk(%wUFpf{sSo?xaVpeyyWu
z?dM50FFKD$raU3R<*dvHDzn$SK62eX<5qsum-!h`#02r<*j)4%f++GsAGv?>bp7>(
zfs@6n6O&rYJnAx#^bF(f@*0Xtm}5eb{=9{Y7$zu|(Ac`Uhu7U;g)#=ims7eyZ#k>C
zybe?03tE%v3{_n+tClbvSil3Xo_{D<pQJRhPQGM`VCoR2TG&Mu>W1<wqzPyEEC1X0
zL-ZA08GrcX<-uFu&QGwocq<uY2Y|)0HS0_P{B|epj*;sgP3lmNztKnA9((@R)aldT
zfT8=5^x}<w^n+jT>wS|V35mdQA7*+!K9iV+?pmYjw0r`y7}J)#RV(%f&Y>W|*`K?$
ziwh*Kv}%JPZ2}9f=5UiUfHf_X;&^~h8)>I#P-u+smMkC)XfCgwUt8ZNOD!HR6vsl1
zlK-o~skN)!fH9O&V-Nj!{3~#zNps%x7uH@(5Mu1Z^czm|d#v=k*6xuf09OxL!=-aa
z_8bT@fQj*k-{fFY0b)(#SEA|l{d1AyK0;cjCMOvM@#2)4PQ>Yjgr2yPfCJK`(^q7F
z+4`1;#~~AhLSx4=QqfxAluA()do#o=7x?;POWHfyHC)DKqX~H+Kuy-j-AS@Qqj)}`
zg3Gg#<4A`EzqQk&+epS8ig)pQ#M0eCULoK3m0&*(T)C}5S2YW7EoVPYn);-(CzE>G
zS#{wMx@~>q|J2*}GkFb{AD%dsqA4tWB}&ih$s29Iz8FFOU<~f#3$I7>@rg0R7eYW=
zxWVA8+A|6O`HNqbwdHcd8SuZrGxjgKL-;qcBFc61+9r%|^^(4*5VhIHk8M}<WRSfR
zQj}4ulO@T5ZWZhD@%N>G8iK&=2#u3Amy&WmP_~uZ=kgl<Vf?_A1=zGOBH1%Om>WZ|
zXI*g4xu+@E<x(kJ^w&Oc_B`8ry!f+)%Rw+ZxUiSlx>($_<C`x^-hG-OQqLGQ1$)Mr
zRvS8DlSi9~mjRNuC);BiV~23^`-5xY1lvUc@?ES7di5yUZBP-R)yx^@q~3%K$rk2b
zLT=;AQE==FHs|IhU7?g+e1?$jY5YO!G61t7oB=f~kmm5i-;N;!L<n8nM+Osoi0ygA
zc7n~)=h1vB!3*!ZPOk0t6x;e@y%L!-)Ar<Iafml|^2Xo%aoHM6SR2y7b^xPxIx}iC
z`HuEFoyj%HSSh<|SbIHzMjR=q=GY@p3(8$Y-_?mkOTwrL$7}TjjqULmR0+6xCMHwj
zyAZj_k8i7`qHP#IsZWF&iA!b!w7eC-d5gs`qu~SJj_u*u$YoNp7-Wg1xU{T_5o|{*
zd`}R52z+m321j=HX8x)$$U4{>ckkS2gyi$3#GgF$yN}SlLlfD`j(GdsJ~}{Jn39NT
zX;OfzaW=-%M-+vfL6}Ph@Ssqf-IRV&t39aK=q;+#sHgA{UR29uZlmUN=GF%p$zsIx
zfIRl<&2>oCj%5J<A;f6s6;Z8loRg}_O98MwTp*uZAhD?@G6abWm2Fldo@IIP&}SXB
zfUSzT*WDwTw~B-FJ>)+Nh=VUg^p`aKx6ds$0uRFIIHfW0{(m=~Gg<_3GVV)OKbP#B
z$0^53-Fahh80OU=O>i-Xjc_?wff=CYGHPfunlx1(riQdhzu%ZiIuM=l)S*Vu@^hRn
zd3rE3AgYu4`vvJ7BNl<WgtNkFwPE6hX=hDSIRDDIa|?jMH?yI}LZPsqIHPsllTM46
zx4lk2R}JQND0k>wM{!|K&w>jfhSr0MW5!DJ{nVV$2%C!^_kXDG-~kHxPPM8T#A~HQ
zp7%Rv{X3N#&N?Z611}FgNdu!hx@fqX({!U<???>k_nI*-2sN&<%Ix%6dF)$t(`OXD
z3PgfDKQS(k-wb@dSrJWuljLGq%FN=>rIN!@qR3ZR*K1PXaLT&hP#@UNA<H_HGtaoa
zu(ZGm&oSE>m^}V3e{n}Db$OyZ@&m)3i$6E3m6I#b@o~?JLEvY#(yuU3vS~Wb;r3FN
zJooNM_ki0Cu_9WdRnHmGO?35ZE1kN9awY13plN#O{=ix}PTg%AKurZ&EPVNb)KDo+
zIv!1Cs>iXnS;LedT|s-ukK79C38!iE6Z#OOf(&NO+Uz}Q^nGAiE!#Yr5leO?Qc^S$
z?t{+Cu_i#%POKPzQdxhYJ`wF&oa|n#eOY0w^2Uq_8#n=#>0Y(9kWKAXh=Nf-aE3#0
z9s}mTgg<)M9Az?YMW@j+nYiEZ%r6);v@}!11~=o#Sa?NaZ9jtQ%Q)>LI$y7<mXKje
zo2yBDzym(z<<%fj2=+r6DOgivph0LJjS||;DxpbqSk;9=uF)3j>mwK4^sn4O%Ylj}
z8*@5xDM5N6YC4<$+iUgYtC98f<)`$*d?Iom?z=g)Dr8AiWXQDZo$F0fyTY7AGFc8l
z&_1$AmJUs;9N`)5=4Ya1RKL{OM(LwTx7c2-Di29iOjg~R))7`jfZSkJ>&1b>A_6dj
zM{pfem>$fzmf@ySMC8$4{&LQ3e2g~5c>K}LZr>{-<~DD$<07b&d5p;Djm#0Eo;32R
zhyk6`{z8LqmOx<gOP@)l-vY=R@BO)P+^;{}d{!I-)>j?Y?|51rOlrTMeGunp4@ab5
z?B;^BBasWV#27Q$>lD<kNj0bLEL)UFHfarz)a5RiA;~cW+>B*kJx|0ItcD_4@ZV?S
zV=w^WJ2tVh9>?l}129A~BB>K<D3G~G6sO{Rl^t^dNu0hSl`^*nxdFNaU`Sc+(Y}1I
zjw%ZI;t6d_y?;XcX>?`Sq7!!Tq^>`!{pjwh0qvP&{p*QoEf(59hX5QiO7D7)^I$eN
zG#nvVGvvT=M|&i1DhDpwWT;34+O&RJRh3|hFDIRZ0Zz&5k7Xx5wG5p8H{#OAN;VtA
zHzL$gpmyTTTVKQBIw0)h**>zWK^{>yC`drqP&lTAqiV|Qo6bGj>-4yB=*U}~LvHH0
zbv!pt_SpN2$j`XZbnucc9hmsdw?794x2yc5_EEIC#(#dM*75ZfGik1dDI25RvQbI^
zgHtwZ8R6An7J@ZlQ3l;zBqqe4Z|kA>Hp*st%TQw5bBIVJ!Qcq7gY$OVx;}}SpT#O1
z!(#9qkC5Fi<6kHRDi_owcXm8Wzw5(viT19wDZe$5j|Ue|UFAAm$7Nnu#bs;R+2Vff
zJ!>%2lZ*XIo$3EW>$vOB(UH}gdg~;Rvov2n8$EUEv%gF&x?C&TMWctC-<qVplStGX
zQ>N7{t-Q)pTT>6Z-%@$7$)JWnnjI`LeI!7VqQuxDYg2oP3c|r~<YKt0(?pktpoJ_;
zmH=Dw)gZqOf=_<C_2oBGyMn~ad0iIi)(1F@^pn%~!+u>RDX2$#VeOlPv_myc;YQ!K
zE_l|w)8SMcoX_mdy$gF*|J%nS2d<Dq{G$FZv^PiVNg&p8!QZTY{xTvtr+gB@Q+_u3
z{qUE>+tU@+*=AI|Zj{3Fsv*A`3vviq-Tutb$2%w)eK%B&@RBw~^^-O6``gA!I9XNR
zrnU|ws%9We>W)JY`mgh(XXEmDLWO>dU){%>PzBbSu10Gnm;TCkq}svmJ$z;E=BAS#
zvxl(e&Nv1vXIe?@H>@LS+HD=QpIZ2!x9`-uM|!Cs9Jum}C^cy5T9y<ky5l#8LOS3(
zofF5$=us?buO|-bk6__DlFMpU8Cy21eVLqLq%m$~DYuKp7yvLW{EiT68lWXEQ*K^O
zhO3u4SCxt3-V%uelta3DRTze4bRko2j+dESUIojUK4j&*=ggD!iRVu5Z$JM~5xVdJ
zv9<&jg8Esgh3fEo+|=+EO42a7Gtao0-Y6OksO?k8tzLii-tw{XadN%)C+Fbum8j`z
zwO;tXM656xzR_t4QH0E;K55xbRt?2m2ZB$(QC<e&mBY5tsDohkax&4OYX>p?HdQ=&
zf+Zyl@$}j6$a7QU6nrFJW+@|XGXv6b7Ayj%G`TQhF~sH6K`E#gix?4jKVIJ%JkgZX
z=af9Bh^R`8dIzPPKRV~K!UOK^`n@S1-+C4vWwfFAIpM~jbrpS1`^ZQ<qjp|0wk;XX
zH9bkvX5d)1`aFGg*0GE(9$w})@uicICUy!V^c@(Xe448&+}2q=5RT9SfTAF%Gl>lt
znJfUFMp2qv8mG8L<T99c%i866Jr0#aM}N3CCFEOz1laz)6Pz&tOO7gi)_KFb;B51n
zJ?F8bo@l#0;Wp*|$j!ULyv(Kc5+Br2(yhDk+#gcv5aj}6r8e3ywi<69hp04dZYGYW
zha$W+YiylV53d@KGy$SQ`_vjM6ztt#6eR)Jri49{Tv1wsmKUPmRt*|vJ)BgInN+Z)
z3xQQoPU0O)6ND%=JHdT-J3QVF$D;simS~>vgQV=%evt3j#WTvB@<vLI=ky=7tCy|F
z2+e94Yp}?o>AgTnNS1N+dw0?^b=)t$J-Il^5*iAtQRo3-AYR?R7N&iR@(Zcsy~=Hp
zTs}iE>;@DK2trHH#OkJ#HLx^Z)}ff`oArB>^kEPYw9Xrb1q#VHLFlbz@&yV^6h_d0
znxhuTkR<Jcw2u!B_xDvxK?9%0z@D;W!Da{szuDd6;h(%IkM8)U4018wb@vu8WFpF~
zC&1Y&8FQJg@A#K(>&mJDy?ofMzip1H$Oe6bi82>G$BBR_W72y$pbv3AyfQf>WsQb`
zD0{-Folb5Dw;ZO?F1h7ib8A*>VIM#^pd3OgboA`BC67+srmRu&6>d4#IZ4EfQTMnK
z8JFsglPWHh5e(ma^m)}%vBzsEj?kZwv>w~0n!w^=75|m(daRJW>K;mUmzQ1ra2-PJ
zWz`d~&(Ut<y+O)Nz=-L*q{8Ih34IO=Z=(;Er3g-=m5&9A)C%;3>>jRTBiagdh9_E_
zv#QopE%U09xWzgr54=_*<B;JZrl>VHhhpEga^2W6gCbuHLJXg48A@YF#XK9~Xn;_}
zCe;PU%Rnk|(?b0}bZ&T>P@S*pVnQ0z^%p<*T}ifh;SHKMb{u84`x3QkHK8{Tn6wXp
zzUuZ^-c(p0^jCRq-Zf-0>I_xJvOYGeO>6flX&&zcEw#f#dW87Upsk+oU3+fcBM_lj
z%+`>x+cF8Ug<KHIxy%WWKv+JSLHp=uanV82ujj5q@*m6@P1a*BwVF!0kBMCQSN+v^
z;Wg&u{<B!m>ct7Vr#EUZhG*e(YQ*s!2|sVbEHYFL^|~)x!=$+uNKuY-K$7(>fMHw|
z1}|!i2-M(k@4S?_H`zg|dm~Ay02v~45*|~6K#NH0J7kG?UCE>cS2;Nwcfd5uaMMPN
zdz&Y5PZ<#NY$ExGCKmW7)~DRc^;hYHoL20Wd?i)utoO=Dhy8|H_NLWi+nldwo^q-D
zow5es?{ViUqt|=O|3dTcqBZ=xsmj*Li0?;UoE*|$oZ{+kOC=Hwyk?<`bPws~s;Ryl
z8^{e2cgObIUBb;E$w7z*p>^a{4igI}VVW4t*WiMq+T4)jve$rKY&60i_l1Ja`G<Z?
zLMrPaf#*MC^Fn<KS@t}!J)!cdvU;2zr;D^JH?$ySGFbMI#hAP$&Ox<ErZVe%$l+3+
z{UkPw+~(k_=XM<hVQG!@MUWBfPt@<4toKEzyza(_*Y1iGe<3G~Fw4(JUr0OyiDbvl
zS@pV}T7vv9?T<zfdyq>8i7+{<3$h1^be9<Dv$Vq)FDFRm5;T@1v-(wu?Wrg$qa|r_
z){K1<=Ov%#ldqer!tfAt!K8_C!;`9i)mG#~6{uzPmW@B$pQ28@9tv6T+3r}NN()%2
zJzhuVoYfurS|m?>e{Asa45>i>k?02m&tuTM>u&t*Usrz3-yJQE`IF5*fXrFjB0Oic
zZNQA31yPNWwHRNtIlqEU;IVJ+QZ>m69ut!H1_K)JssV)wSJ9bIc2ZBN2MsXaNiK6w
zNGT;>3D)5k0jGQrm!HO+C}18z45yElk0yvgN3D$O4CXE$c(m)`B0GgC!qb1epv}2<
zC*EN%cxa4R3eC*S83d>IWcxCZq~~@=j;HD<1JWKW65v<<UdGd--&}mQwqY{g{9l`!
zzkg8M0M+;ldh3d=U|?|Qlk>Lwgo=Suf-r-Ck@VBwA-m-JlYH+69jao>>)H)nZ=TT>
zN%;>G&jK>HQ}AU?2MV&5o7=>H-Y=j_62~$~-xy>JDufG`=@3!TReFH<8b5->piqO>
zmbF=ue$JlAxi{M-cU5JcpcdUk1$xjvZn>A&Up_<LQm1W+GH$bO_4$9Ud^37!5kOtv
zSo@;Hc=0)&v*oO68BkkaRy8PCH01}s=sCk8-&DOWSdw-VNirs7(s5$jQg~W#Hahj~
z+7}e!kVsU|k`4e<o{Qb$%LPbM5e~c0lg6!9c8UW9s7KzxI!OBGV}0Nkm4b%dTnq-W
zXn$AE9KRlb=5*Z~q(8BD_nyANI6)*~;y8x}J*6@KaLpavbJ1@0>SDBEa%rq|VroYN
zQVOe}j%J(IkSKM|n$D5}NFMkm=bZG^OReEz7b1d>`~H$PrzN3n(Zqt{v6g5s=e5n`
z%kXHqQb^qxfP4n0uP=HVI8ziV=}TDt_-jg6Y|sTOZ--!|3Gl&ch`;cZM3>Uei)6+b
z4_#o(Q*B<8-JiE%kvi^m>qurlt#TIZ_Hm?>(#1)+Op7abru3iDp?KT}_BW2}W1fc1
ztiK~F(gYwhYFWX!&mv1T467Q%Kfw96z$~}Qt0#>}yRq}-&UUS3G8rojBw_(F71Ksd
z%$Z@FJCC9SpKCh<N){AAbs{bv4pQbT%IHx;L#Z5}sWc0zU}J7tZAz1#*Y}3PbgRuH
z?bhR~7OciCv=|IBQ=_jtQa{+6{s5Jv6d<KOcGl?FUg6`T2<hurYMUFTR-1Xpq7|XP
z1Bof2w>}7`>Fy+{^1dd(1}7F`bBKjsqYf`4KQ<UOYY_lHfp1OTv#8BrvFr6~IxPyO
zjpeosivW@?7QW(RdYsp7;(;*O+y#(Vh*^}xbFoPECR9=B!>I^j$dl73eSxjvi&m94
zvTRMWL93qZlD(W^T?h9&tvTrXa0{Mx2eJ6>+@@&R)d?2$>pKvH)N+u}Ks6wn!VQNq
zPE4%KYl*|C{Dx2;c_&*^O3%2^7~RT<TMVcL1o+|d`Xs$nVK2Pdq-v}kPCQ8OZ(a=~
zkjN8X)a86uCgsto7F{3r$3k&v9Zk~Bi|9EZ^6r4#($(ANy1n%TlM6*gMA4xizv*4u
z)kxtL_4q5^W>2>0DetHy4VknUy=$Ivx(Bbgsn?<_k@~uFLCvDSoT*@l@b18dZ%kCZ
zUzkqVa|x6u+O-a;p<PtSlefnx$~sWi!Nn^hMSqU+XPpm$#ZWtl=-$zZ>BIMiYmxvS
zFw#=xJg->mX+wJMq_=S*bV?FjD03kTXXz|^%T6I{rS(j9K^m_gUP$@lg9{KnJ~?YG
zo-Mh+8=h>71PYl|8!t3yAF_654iz7J*R2@um+mB(AJ1qf&Kke`+s~dzMRNWaoJYX!
z_}Oqo?VQyI)TU0!okl4;+`Y^}&sw-2J(3A^LCorwgty&@a%*UGHwTg(kRlZz42y5g
zYL+29{sW3t@U?G()-|d}g#y`@Mco$6v(1XbiQljGEe!K*;|~)W9Ows|yzSP|9a)mq
zbALuUyxH8W`fwzZ7EOvbrIm`ZHVudVF2fM!Z}d0s{%*B&DxaLwCgacVfT{3~7WS}6
z*-pTIkOeQR9a1R_jboKDgA1uC=22}xvqeS(Xp;#9P?BhCtkS*NW;RcWHK!CtK{_kT
zAZh2W!1Pm45<QMqJmx{}_tXP~IP`)#`~RF%i0&~x$5`dlkR97^Zpvo$xZp=0@{@0<
z_eNHE1NI>SZg(AVe`Q5r6A(Tu_{eL_K_B?mp5Jk+?}<iF4n$wn=9`ZfcGAMe(b}5T
zt7#83uHo+WDXgmv^2>3df!=k|Gs;0BDg*2zewe1eJZZErv|&4dMc$Cqk&DfoY_5J8
zo@QJ`HpmE%l@R5X%u9D9yy48|;yvIg-~ukO6Olb(KqXy`0;%6xP6w$l3N-e#w^_9;
zXJ)Ng3kfx3uE@z^)vmWN9*Iyx?<K9DgQBhbUtTDy&cW0^vE+yB-lg!^K^<+Jd^pRy
z2VpEBGp~#x00az~tVPH~jYHa|M7+L`S_;3cwNM2^@+Yi^4=cXc#D4LvjTk~9r1Rsw
zG^CNu$1%jxNMr{_xn1pbvKHK!9Qgs;<3@UW<=9UYPfKwiI94sw-s2a@>BT^AwmUK(
zTD1J{9m!d}dnqPaxm<BPGPsbIX68#vLION-<Jz|>ADyd9;Rc?cOPtaQq1u@+`Jr@!
z2ti<;Q<KhlTw*sz3qpzsVJ@jgiu532kJ3T%v@z3}S2x1k8gn~{8NjEk1Q$~T7?Rbj
zFB@}S1zw4%LSdQX->$wkEk_JG1rW=5r|-_W%MTab6lW4$(wpmG0VAspoAROOwJa+N
zZtTlZJD1zzW>h5eKLb!8OuFy@ngUoa^iMvTyHWXYF-7Puh~;y6gW2ejx)nVcxu=sT
zrU6v~e8vA`QDtCLg#)k_dCo-OIY0r>p-4rdwL`jS8HDM@K%ULqa@y!DX(UVn>{I=3
zk?>4P|3QvG#=|L+hL^Pv+Gw6uF{{Lp<ZlPRgYV!<moKJy{cV0`R^>hXjCztc(e8DO
z%;uJ%CuDlu7}^(4JNZ6mu%9^K=cAF<pvo8hR^kpAX)}=}e<sS1daYBdzp*1x_grFQ
z;$A&^Zzmn8B@=bEfsL^*^3M)BDMD+ON5C5tYNBP(cTh{Gk=4`mCQ%cD*$&TvYBEAX
zq1Z#yfaag9EJ`??oj4I{DPY_{$#_oFbCj94sT`FVaBCxS-7wJ~dm8{7u=0_|G0{)5
zqz`k{{jhCd0Zc(@qa^ziqP&xg7#LrmChq%h_ujc{4pe45zQlxyb{To_oYqp1R+$)G
zw<gNf?N&pUoP=oF9pao&MoCjmPLrj+q($rRxM<vGsQTBz4xmkL6nXU4Ww?`&G(yDD
zAFrn?*skLRq<ceXt^x1GBsgtxLNc$Zi!hB!tTb>lv`ADBWKC;FkZmG<AfKD{-m^bc
zcFU}NR3U7z;O_3<_xQeE&g;*$Vj_A%i_iS&=TfglH0C#aq}^Th>lc=Js8Q<n8%%4v
zala<H3nk+GMhke{7DZ6#=Z>_%^-qH9kh@<5-GD&$4rQ87>S-Nj9tj8O8dz1r21Cus
zU=O%cvEI6eIDXV;=x?~mK^Y5SDXfc_2?57#%CZ;;$R`d0T40ysAO!0_wsoxMC{Bo2
z2an2#vuO`yZ0iB%u@4;gu?v|q?jO3B(A|ng|5&ShRrBjs|LKW+ZuNoU*l4u(*OU3$
z(fChyD1&~Q4j7b-HsKt#CMlXfmbZA9?A5SCgBAxbos&jtQ2)dRqw!^ft_ZwQQ|H|;
z8;a&LL)#jv1nUWQM;1cE?l@hp<3h>^sYk>SAb2BH(aaeO`z`oW-~N8zP0ewsie<NX
zqjq4kY5Vb4<T7QZ?e>wUMvgc~-I6^BtL7(&%S8ZXFKHJ@<|G#Vo1Ir(WASA9z85xX
zEgrs7>pshLwn9Q9tcDO(!;FggSdWt%b|P3PJ=mx;{j%T)U{X==*CpxjXiumP^Y!E+
z-I_pXCC*Bdj#!bh!9I-`jC#pXgMAW{ajHO`P(~7$RZlA?slJwlo))7{V-R9rb}NWS
zQ@F2Bd8O&h9*hK`g1w5&nD+)Y!=7TuODY4UW{mO&Bb-m9wnU^^{~4`r^_d4M&uP2R
zXqnS~)EvGRol2<t67{4B;i1HKIz7T!>ded8d{fpXKjm7*h=kXq^T<&F5*R>0=Md5-
z8#-&k8?`TVc7!!raFPf^p_OeC0y$hRp#}*+vQJEgRF!B>rYFq=?0-puA@Uj}Jy3RP
zxZ3>+8VXQPIP3TVak@7h6(i}qzGX#(`W~_QEA|6;y05#m)p;(^TwkV}vpcanGM2K)
z>7o=uZ~Xm#uPkcsiU&p|du&mgj503ab%P;0tKsA(O1$^8dG{JsgTo|uBUr(p5-J9;
z2QB76;ib;c0%{R_@6?t|BzF*@6(~_4--y;F2ww5LY!>TU!?Z*;6Z$|SFJ3~owKflm
zF4HR4M1w+ZC^wv)mem!Dl@ZZ=xaEd9x)j{4W&1sD83rUXjrU%Ka6=jqD`j%l@pIi|
zdzbr<5MKRULnPn7vBP*RT3)0XWitM~u^%NGM**ChjBSMk18s~k2KDF!XPAIc7tkR*
z5UHqzjVW#CS@h%1YMaAthWWaYghJb?K>-PM5$Uagj6~Xy9^%2wz<9h;lyS2ohdj#p
zXvvik-nnIxqkjDGPdd%m2KAmI8FHrWC)8#qcEn|Jp!<}ykRcs(&!F2$<IGv(ssH%-
zx>PR>%sZk#91UO*L<}J|sBV8&FC|JQkzLEIffE5CUwiPfx;c#=Pij!3nxud<S#=h)
z6&>D6=PYlTfXKp(Qx{l!dX#f$4lqCsz~J1yT%O^<k(l&Q5?qmAgYw;;nj)0vp!9`(
z3oOFOG<z|fiHXjITegSH2Ou~QBASH$VEBgzKkI|Noy5MqaCgmEd-QuklwQ)4$xRYA
z5X=>(ROd8d7{^1N3yfEjfi<ARN^O9ZFB-0so%&|xJZiBal7||7D`aX37;e6PzfqDN
z=n$enc5F)Jx=SuXBiyHo7%#O#a_ifIxMgL(BEux?S&tiHlU?U})YqNI++R7@)u88;
zrFM-*Fi72W6wE|dzWX;!6CGb)zxcw9X5-oBAB08OUaDUmN^?31>&ajQ<Ie}BWF`$)
z5RleU5~voGdd}FCfI64hIg_}d^z8=olkTVIeCuQ|ETb|6RxJQD-LPW?5DW!hZc0X7
zuovytt|VRj5tmZ0F4#i_!S$!3xOO7A3l6L9;3mv^{NYKf!%@G=9dW48WDZ&AF|#3*
zXd=-uu|UsgU;Rla+9(37SF|6(1RDQFGx>i~l*gICg_vhVf?}B!K`%a)BN=i4cjp03
zR5bNE5uuzncF@8JaIMZF5n<UkfB=%Pvx6X;$W&It*J+GVs0Ab{R+!~#w@KH5=Lj_j
zoz(pqG7&`Z=iJo43QT3L6WNa>qHOBp?*S5w>~)InQRjN@jLR%m6oo{rcQkS#YLwp<
z-MjTOCx(2#`mKrbjqweJeRnMtjl!&USPgJi>a&d9VQ&oW_qp3cmSqIngFr!f^?+7a
z(jMfX%^97edZ`oA9Romkhxg1IwiCi&RepADDYP8W-&Ejg7}Bo7Tq7(yEKr>=qy22U
zVjK_X23zy-Etl*4fx{3axhIdmfr(o7C<I;?K5=eK@7Lh(5r#(T9yn3{k`~{XDbsh+
zwo?72XpR2^r6D_DsJp{c6lJ!<bGMiD(7#h=XdgF(6?C1`bYf~Kr<;r_|AuDl*b$x$
zcfwfh40;ac0Rc_PL%HQdU7RlgW}jgZjhrqHO+as7CTY_vhWEQ?&$^Wd`l(XPp<wy(
z3W&_qg7>%tXR77B%zMtVTBT_u2bGpwI!>RnTgf!{y{U4P@5=w=-+i78^dwh3dS+w1
z_Apl*vtO?-suhhZ47JVo*pEL@oD!YFA1pN&14mOZf|NLT>duILCAJM{TVGfFq@AE^
z$22MHvkjDBshs&mCGe(d76-3XEU(Cno75p?pctH68s~=eW3H&dUirjPNC{+mL_nGr
z37)M7yzW0oMI|!jTn=>;Nu`U6FtL$4WFp;vN|ZBAp+4HR{t^F20Frd{X<_<nAB1%!
zBg~pGUG{}0IGCWDu0&$wIP^A4QKxz`5q?g3q3t<jztma7q;RsVmrQ3;vKyl2PwS1q
zho6#Dg?gXFo|3k;PJwjvP@ZxP3&gP^E&U7>sE&QSC7jKX0uCK$K=Mx~;G;a{Mc^dG
z=AGj?^r+mq)6repg{Ys1M*q*BSKc|t9NqB)(c^`xU)Lf>nOX@eIO=988HzNQQl%zV
z63`gez|Av&n-%mSEoz<~zC`ng_64IU+!nTIuotuE=|UzkFj}8l4nXIQxHu7zXRHU4
zAzU0t&g~LPI!oYk-0ni!m4{jwt71JJ&aAbpj(Wcm`2~<xVv`<sZePDUHcG3I;IuRU
z9GW}1NKe;^foRo0?T^4JBjEupL1XQ6z%+O31LoiW>@1MfAxly+nfD{JArjiog7O7!
zp4FGtl9p7JhfOE}VWDDkyU*PY(Mojet2Og`nl;#pHbyM(unwDu$_5bar?!FsOHr47
zk5FHXufzRTNy=imOx_t(;~_AOJAauvtL-B6AgwgM^~{~A;@pYy@n4@vCW<n@n3Aip
zLv6hV)I1Qj8M;xEeFAO~s>@!=!0NO4DB*~%-!a;98Z=grFgAnFAl(|;I%Rh1DeeaG
z%EwzF>I*)sGKc0O_^wSVHmzDEc}~-{h`0>QVcmh>&34F=KIIZumBXHZn882w1gG)x
z7Al>vM}~d^YL>d}ZmF*ZIDaiV8Qs0N(tUx}oPif=wDJGiOnw=$hZu-tFCu2FszOc4
z*iiNXB{0Acsq)Rmpv%KrBJ~a!0GXvWi->`0*TaBKTOaJK0@WEcgsT8Ma}5Lt)FfEX
zGfL!)<LWL}#4|b`J~wi~#sm*45{R$F-LlKzfVZ!QvsDb-A%!DCd+bC9UefKc4p|-U
z^^q-o=iQ*s#XX+d%O?4+MYWGM`KRljj;ufKN1p#RKJLYE2rxXKa0bG$Eaxn)e&6{6
z)&&1wY8%A(e0HZI702cb?7|M4Xv=6%+Tmm;Oh)eYy_|0oGet^*K!((E*_~jEppwgq
z8hJ{`kvv$!pC+P4ve!ta8i3*aI?fvxXHE*AAEQsRWY&)gsDWhu$Y%QiyTd!GsC&9!
zciNnnKj;l^4wZrWh&y+}pb6}&PgKn9D{|;owB{38?fZsIys=dY@koT4!=7GsZ7|>D
zIn+})9hTf4se3NM)NEv~Tf1Q+bzY#0&!AfXouZayl{I2MM_$rLR`x1aC|Fle%{`fn
zp9)H9zg5Z(NkxWxv@UHq^x9YKQ(R0C+X@kox%i2J-t197u!39kiY?AkmPH6nm!7NV
z-4gX*W--w3^l%YHC4KzW#HpFj&sAQh#qEcossqs-gzB+@#MVxe=1u#C6-%*_m<&|P
z1!$zZYlw@hN5afSeFqL1oQP}5(awP|MQzyS2F>T8Sm^xCq7wyN@)Klm@-%^k9$^7i
z%u}|k*d30z)q}Yqh<~J9Xkw#HdYf&Q#DCh_Yy;WKV$`xTtqwW#2dn-g?$n;2IPUlX
zckXKMXk-U2f2{n^?*BZB?{%8Yd98Qw@0zjQ*oT6@5i7StTx-H%dTUcrs+&WI|7Z^F
z*)v8`vrJ+!Ry%5HLCgs&rUhjxa6oLV&nL`Zo;pN5-RW`A+j8X44yCh993mJlOZml5
zJc?{l8yH1k#O!5Yz-0$Bmf`9);!EonqVDeKTv3M=UsEZ~<#YvaioaNx-%&rE(5j39
zy{h{;leF-fp=-?3t%PeK5>~DR!1d+fN$Co{p(U7fLBXc`u(~9Ys&do8CxkqMWA`hs
z#NP(x6U}v#JXe_f^W<~Pu@nZmH5?gq_E8YwgNperR9UjA>ts-J!#4}qN6`F+jhI1O
z#(Kj2$G(_L8~v3iFyA??(I@@;4eAaI=GbvuKQ)!#v80=`#;k%cwXxHNr_%;E2_X+h
z<8=vNO7ak7VF`Mxx!=(ZiMkb%DTEwxKMgbin0aGaO+jd56=X`5Ncj+_ph6mN%qlx{
zm24oXdK{2@XP8-ZLjXp!=vSm=3poDE+zwg7tWt<^b&!jI!2<RZ?<)0_qD7T%3->SR
zLxW;<!0j*J6cO<x{oe0XK8lz;Vq(!9wPQ3nZ%ZWVlHqp!-cG0%_e`OEnKx1)t|yTq
zZ<qe&mw0YG$ObdMi9gL~qm*jy4oWVIG$kO~$ZTfe>2ZkG4#u%U!Bf`L3i3j`)sBu;
zE;U3kJavxn0)JjvF?ZX!pH_B(snR1)O04Tm+fO-E!l0Ue-OXG8Ye@3=LO~Gy@8drG
z72o_XB-cz^)1F5`9>K}_c_h$cQ@T}oScOxQF#-oyUMT#wbDAhoH)vz9%r_<I;MSKo
zaLnII#0J!ssu_j<3l{1Z<s1d7&LLiET;cX4$_4ts^dIsRnRv|I-##9qpwAkZb#{BC
zyNn4g0VGIdHOuYA5(C<8cA$e~5K!xatmp2I=tY`TqIFAOE}wfk5`EOKhCPn!JFdS?
z{iMlI_i9#T>!MLIu*Yz6*7*FMm{jQv(X6xDYg*E<hjfXDH|kBDHAbB?YO)6jyua!S
z0R{i~{95h%CXYn?#0f-XERJL$WS3MSk2nEf?JyuDB?GCp(7OGpfS2m%bdKQAUIyF8
z_s!;3m2K+3@{kwXg^x)2Bpy*;a8V>yp&b7D-;9-akJ5E}jMHRK#>0*n_((GeUAwsz
zQ2#+Th?oz;REVl1X@_t4DFbAr5$3Lz50@k&3G?k+CsjR_M^eCj(`8a=p|skPlyZ^c
zYRBOl&U00B>M4SH8>>t-LMS3VU=@@u*X~1bC0=n_fkuMb#Cy~wFr`i^ElDlgn0I?!
zSLpgKaB}p;|MHpC=?D>f<T;rGwyd-J)euH%OfZs??yMTIrxXs3z|58Ckh3VsFg6t&
zC^%Bf+Sp-jlra){H5)dbGws9X0F)6XCGwFiK*9>pxHX`AOf(N$LUCo%iH+MfnzQax
ztj%D~Q_6a`OoSpp8*azBv9NYC03%2vNywAl;|#^MXxQl=%(Y%{uRj`z^bVd(jThMt
zs;lKs{o;;Cp!Z;B&qQeynK7<0*uLeO(hE*0(6AUax(6&XWDSR~@fcc|Ccw!^%=64F
zUW<HzB6b*-w7HcuDtuEP3U?5@nF@Brr<EKksj2cA3!SFhsFem_6q~YCR-Fp}vSc2g
zN(Pse`nGJ4x7q9PD0|_kp^|;wZ5~uhPrDU<I#MAg>e!O+ue_S6biWbdtvy@2u{KhR
zc*tC$J#oM4o|G=IP66wCvT4u5rrhMbq}?q-^7i5B*Nd3wlKygX$Bw%Xs|U5K%6ZP@
z!X&IN8o>UCcms*q(6ItGxD{R8m~+N@EbGOna}NETUPqkk<N7~kt029+!M+6n?yR+{
zP~U?=jnd#l@$SKX3MiK=bYHm9zs&rOj(QM7sNV8RFO(**Qd&zA&}LChCa~HR4K}Jr
z^iF&jI1?&{6}sEV%(snN6+Z7}onp{)oo(92WE*G1*jmy<B7%Xzs&qs_8Efm8*~IBM
z3xZ3Urs8e(u8^Bc501DoFmZ|g<l#RFlw^hq;jf@>Ez1se?FnUOy*5ByX5|15xp1K-
zBZ!E6^FQ1b(JvV(HUPZp3{$}h;0U_C7|ug~sDk{Zj0UlA!gm|aR7U~`-t9?MZ=vBx
zB!KzaND*jB`IC$dZBW#<7y+!^VKH)R`aFVxK-4#xEn{B6Z^Q?Heo-MQpoj6U6QW<;
z2BJT&BN%nL0y@Y^@GbFnYhS8>fgwV|*z(CPjMx>x?y<j)U+=9z{&4(E<kHYwz?<-Y
z`;XsyNh=m*W{`lHtIhFK(A}zxNwam)cn-oFI+R%k*(i~HBQG5emASwQaLd3Jpze{I
zykzP%;o3?1T~WZf2A7XiV-cEHF!0x4ANXQNTA){QG~(cheA$IOcH<%mneJ9Q)V49T
z;yXUICD>Y=_mf--iOKPP>Iq!F(PIs}MakdNtX;GSz*_4@|MWAdlLN)Fw|)KRjBJy!
zDKyZ==G6vd8ETSOm6sjPiOU(v4Rx&n3kYBN0oS!bE6@~hFl>5>Du#e1s*+}{ZenTm
zY~l7K_M}b{OOt@&LbQYc(mm%O+~SepYNpP)UC}%DxeF}!Q)OVY0Di94@>qh_Svx=C
zY|9Kg|9(&QQ3qeq8@*f+JyCw#f5!New?22G{A6l<q-rG*AOE?u6NWT0Sa^daMKbX+
zn@aQ-16B%g?R?+oLNtV#$Y6vIhIi(Zc{Qq~9>fa7x*vp}pejR_@$m-W0E!e5QA~4^
z0`3q+MRNQ?jWHIX1+UBnp}PG-kc~i@6b_Dz=2KjXJWQ{wcL;<j$Gh)}6bIa6e!2dC
zCoAv#Ic>vNVc>a%9~kilUjJ4Hi@!*BhBK<NDd~CP-LuPUl~BBdynS&KN$@FQO(wS`
zlH0UoGUk+cy|knXAz2uBe()(*Li%c_;_+isDyEaG0qnStE^M@Y0|;02(8|&eQ;m~x
zCAY4_W+8-eg4C08im24I+f81sJ92~{i=*unSwFV8phYL35yroD{?12IaPUrR4Ss2|
zeA`)5t6@B0{exjpLZW9hs-byUF>vpY+f{*v{5g%m#o$;~WDc;qIsL1Oj#Ouv(qA6;
zEz(GyL{U^eg0<Wn0j5rJ7lgQClr_&Qb<t|cTao?b6?-0<PWK*=4q*uxZ@bmYs<<rs
zAdn}lg1s4NL`@?dxh?L{o=oQda(jyV7B1HBg3v`M_=x}i_Eq*y7+UWEifQ&_qIwcI
z#3bp2f0Nut6#iwa4Y_S6=VD&hv6fB5;w)v63T~|rsEDP#dj`)!`xmwOaFe=faHFwL
zu|Cmtl80lMQ;RCdI`VR+Xi){d!gvxlqQu}Cu~3SDoNEfjvv}-QL_W=T&3YG{z)Ntp
zxYcsEkGR#<S?`ZUBDa`wku}hYhF|{FU#@3TjNg^0ZEt>l$Bz1v=J+M%Xc05vffI?^
z)fi`CU0P>CKm|o?Un`b_H}9joc^~prvq{`Z65y~3Uk%S-ir3ARILj!oO2~FT(O;4^
z2tHubn<{yz8I-y#o8w1&B?t)E6gh=o`2s+}Ew0_HBC8O5jVS6p8}u1-KZ5(91t<sC
zU4nSH0-(r}iGKCq`Z)#+-Nm+O)r++S9|91gcRFK-;b|fQ!?<5#w~;tV^kocF3?Sf2
z!5t##m^YYHnCFtWCrk(S5TvvLnt+sv`i>bg3^`V1Yb%k)+4Vtdknx&ID$H!V^;l>q
z4HtjVA_~N|_NFQ;DzO4Ly~M0Sf`}`@lm#2a(<2voLaFq-?gfYN2}L*exXTDJ#EQ$x
z^p5?X@!jIdRPRc(xjk-wBQ9VW97tWYY4zD;l^#B*+%G7XfWyh4Qp{wqx>V8kQ(&S~
zNK(G84QR1hHL52WQ_NuL@b+Yl-U%8-hCwINdQMYtp12kv-h6CcnI)9(l|5^5kr*^V
zel#rOY!?<5=so$=%@D$)vxl8{CD@Vn9O(rp8@)ig-6l8oR`L3Lj=Pa|e;OH$xUXtO
zreIFbmJxkK4@8SK+L=v|f$C?%VP{F;%k6rb*=~hbsReU4+)#}2Vq;J_ucvbZ!3wS3
ze_dS)SKUAwU)k48-Au9#hE=3yDIh^vF^<+D;U9b&pl2K%oLZz2_j^OJ-gT*>ywwyG
zfR7#a&61yNj4(ZM64U?>S$lH}F6!O?<Ph)mSI~1_UZh0ym!teR%#-y|U^IQQR(naW
zau&74&TLZKI*{CF87X4dG+d|31<J-Qh4EuEh~H~fVx_btBb8c450zuL<!!ZA=hNjj
zKnw&Y7+Wq#Z?o7LdrH|H7C{T9tnR#px@K&h54}-@gy#Gd#@ol!eaxW&ICI*BQOD0d
z&Myotpc`V00e4$^=lXv>6CH2~!~HR;;vFYHlPX4OE{it!H=+g+HaU(_I~BG|iL4&O
zk8RZ=nyXhsu2dXdXy2AVH5(ETRU33g*Av~g9pSk|lNM<+5vtZ^4Gd98O0UG?@*%J$
zJ@rnA*pBqbnziWo%MoUg99593L@NAapLhx((oK0SZ+Mv3$KM+v*H%aEqi`aJk7lH`
z8I;5wujnCcJoe6`cSOmczu){UdBJhL-qV$NSkG#kiI}QrV@fV(^=_AO&@OHNI0{q?
zDu6m@!V-l|IYju1*Uc53s&|vBQ7|`5#H>IL3=2h?>GPtGans7S%m@8_t)Z7NbzB&N
zAi7>ixF0Hx?}0yut5};BSv<L1_{7RGEg`T^lBJUB<({<mf<9+jBl}18^zH6_c2DNO
zgotWHY50SdP`tR~_fN@G1E3^hz^@uLKr`<S2~+ca;39L@gc*nD=g1h~W{nu<D0=of
zJ)`hO;G08fekU<tnlOKo#KKuE%vNBa02_k6c%&ei-DyR}5xPhPgXq`>=8g46L+O6%
zd#O(aAHXc$v;`|h>Xq-|EO2@%!#wr8n{%7aS(MKED|V$Ss^hc`ZM-5T69RDrVg7{e
zhZ;29>#Uw6y&i=M+ZZChA5=pYhe%rK@DcT>2~DfF!_uEP74AqZ>gGY!s!B*1b}F$-
zR^TG!Qiw2`e=O7?zS^pkE8UXK2&HSdIx^T-$*~@1s=)tn8IZvc8sn2<U4<axwY&Y;
zRR$Qk$zA~eIrkTl*Xk!Blbx6=R^C~*?}hK@jY&hDMu|Yiu<2%AjU~y<w(1pRq6T24
zl=DynoFnL#<`V96{X1$>w>BYjusyjEMEo@)8FXhEY>_W-{a9e`%}}!g;?y!v^AF;l
z0!NdrcU2HSQ+vKGTqW_kfc1ILhKTtJ6+L^TXT-=2JJ3FI_(957yuq>Z-yZ*mixGFs
zNJXzCAhS$SPSxU7S#q%&eS7j=MOIw3)y@sU(}B9moY7*c0+Lu9_nl8j0@^*3SV@Mr
zE@9gl-Yqk82FNYAm*>WB(fYgApIkf4qVYS=_H$_5mXeiJZe`}7ljmtg?mw_lOa+oK
zB4v6DxRiqezF`YSGYjfOHVv82b0|z8xX@JG)AwwD@pAuxi8mAV#q|61Ri0e(SO0Oc
z%Z-u*9hmrGX>ztXtJNlr4dJcMWVmV;F$mMxXnm=4kPARW5Odbn1n`Nt;X%E{92=9^
zynB>U2u5r`Z#PJQ^*iumxVO(j9+#a^g^*G$o>IaFFO&#6q&Bx|+rt&`_|m=W(yl0X
zSA5Df@b{b{o0galjH7)7qiT)hT@PYn%qwQL;n(Y_C`?8~Xz~92<(JAY?}(1C|9-yt
zOSOKzhW?PQ?#`pJK-=5)WYv%oWJBjNa1|;o8OI9;wth*wV}nL}Wt*-m%gpLB&<#98
zd^4B#W~k(=u@D7S18gGHGOuEPPPmX>N0}a?k`ilLk)mMzuUrC7L~xuIp@PijmZhE|
z%r<8ad0!r#Mi}Prr?g0XCTgtI<SQ#Ermo*qOIH2;DbQ53$9aZ1Qv=gRatD1E5+HJ#
zuD~Je@)2PvFMB&Y9o|5%F~P+R9j-fJ5gL?4dE%4Tu0fo;AVF$L<%x|*Fi1VyfsA3B
zuB)WZ1@cXxlY(b>TP=uF6el{OW`Y3<N?a;Avd0Av*y0))0S1fZ0;*6niT?X{%c9j2
zG=OO}zB(R8n;r{qqFH+*X>K(n7q|ow5{zhFPOc_{-0<YbkbI%}75hm7q;Jw|jO}n&
zJSl|B)Hxc=&&3>$&aFVZ0EDj>3Zx-=*6F9G32vV=guf3^%8E4L{cRzIhl&lRhu~BS
zb+B-hLW?YCF&iOs$ZDhL>XI+J)eF&R@z`k7=N|F>;#eyBZ?yrxzA$SDuGN&N&4-2M
zL0<m{Mygt;_y7`LQPxOIF{IU($2S?M$3e?8O36toKcVJ=BCTZ4uvf7VQJOqGhXyw+
zh3&?WsTWGF6mC)k$>*#E&P|2*Vq&J-o*moC<AUe$Q&3m;k~NQb?jgFTV*f{GP{E*t
z7IzU-PH&sP^5EsWB3Fw{wtDMC7CP%U5;WaH$FE-udn#NC!|pcB7Iq#^lME7*G{F!C
z5lt*eK+F*sArYW0nt)3NR@ca@DGcfwi_6iWsN75yrh|n*O#=<%2=Rn5lw8yyuQHp1
z9~eq?aVS!sLSnXY**W{5FdqAmTjh4my6?K~k<66aWC1~4br;=W5}UD-`-9U=*h7AQ
z^0e{%TiV!kXN?a1Vry!Y2}E>CRcYNw1PCsfDysy}l+p=#L<2-L7%JpAJIfi|E+Ev)
zN>yD$ScH9$JFNEw4%n}ZOFJGJTau@GO$nGZt#(s>$UwGHbI^#>6+}4rq9CjbJO|0#
zw9_i3lUGI<_BbM0Cxp&H?_k6|>N@Mdy05|lzKc$pqW+iPWL%FA6YY<*@LW8~^a-N>
z<>X@Lip-`(hDOzg{;kLTi$t<EoS6uN5P_1;YJBIC4h*ZNlT4mjHfB3ZW;PkS#N;1|
z9{?r`R*|C=^cJo^8A9v8dK))ArCPy<acwxY;lXLEm`dMC907sn_B6+{8K8k9-fV*o
zzhdw8j@tOMJ!sZgz31)0H<96zjzAh{j;%a)9QbC)FFP3mXyoZ9wWvj9mK#dZ*=)1I
za)$Vob+`sNV}PfZrF}J-fC$Jg4AGe!1BU0e>nUNZ>9Fo&GGdMo)e@4TZEL7aon{MS
z%MNWCYS<mj>{}=j3UMA>#M}6|&7HL*y*BlDkSwzol<kgM+i2|Q$@SzitG&)Xl-rQI
zj6~9wUw$$ApT4*Lk`_Vhc5HFttXX_9JgOOI)mBfhNo?1*!<^rql*e_*ydqi4;xbU)
zWgCRjNZ7~tX8H%EA*79Dvq_I#l8KrU5|R6NQO05+*!W@#6bL>nn}CTs3eS8>UG<U_
zxmm=JKuM4+nLvFzQRo$Cj}W!QBE2{AMs8N+bFQ0r_q!&$LH)76n27XHdh@l9hX22P
zy~k3I`p?#mr?i>c!nC&Iey-(!wq4)aeTk@lz(`p`MmiLe_C&0y-nFP5hB}w$9L+;=
zG6h0Io~4P9#O|InX(1MeCRssI`nb?!La#a0rIhjnQKXM^$j!}JDOWUSx}xr<D(Kkb
zW*9-iCeR!p4O1N>gWeE5x7XW6Y?z6FF4MoYxW6*<1JoSh1|X|57eDiC^KqTgRgsnl
zl~Id88E>mOw9)QSm6Gh2f#DgxUml6?ER4OJjPFc<RilQmk%)WBycZ+1fw~p3C`Sr7
zSjGo%FjeEUiUnv(tKu#L<1{G<T7+8`j*O}-?>##4NhUC>YzkIjs4}dTJ77KKEGz4b
zyEixJHQ_x{ZZZ89Mu_KM|I{D;8-|b-%YL*YoSl3wsgc)gWc9`tJ5}m*5J?8paSb@P
zWl@)ovuG6H&SdyHoXxtzR1y}0exGU)#Yq(FVQ28pLzNDcf2xPlNfR{C;)p}7+}UL@
zp{RFWw}niaCdYSlkd_qU4CAtZH3KA(zoY{2$W=g}Y56c`Jw+gqbj>4~L8Rx4;~cd&
z2?px47oz%4{;ZN({nODCD2phn9Rr5_I$0BFQEXIEh^k)4<)xy){Y5#|FnmtDRvS)m
zEfV>#XU1lejwdS5LvXPq-Lj<ou=f0M`_Tftl8{o(yhCbXG0zzy$7Pg48q{NOjSWh}
z!tIYw2Hi&+BXPvE{Ulj2_D5Cc-E5}Gwa8}bQ8ww<D58tZO8n0<pLP4OpfGyrG<{L<
z_zilPaDskvh!vRkRb^80Uqu8#zdK2q60!(#qV&vilE?^v#kk5V8m(Mnk+{eACbp)=
zc+`2L6&D;Zv&0w`eGoYrM$}U9l#NM>#|j{KGQ-X#z^!Iv*u%YL>0ZRvCj8s%QM=cn
z-nAsA;15#KrBXs->1CR7Pq?VM?zLzG%2XhMqd%a@9FP<K>f`^hi!BxLXw<d>IwJq(
zF;>!U-mi;QQ?Vm3LSyTAx{5Nezw)|rin&@C+M<*Sjb(1XFdG;s<17ZQoCt#>6`U#t
zB2zS!z~~r9Mgr^2k|4*jw!3d+Xdg0C6+wt}ds8Mc7Gpuk^ofe>X^z$#ITmF93W9^%
zdM1NO>R*^kEdZWS^;sgu8#}B0_3w_A7mEnfe(C$)3k%I!K82Y)uVE)Q8utX1p9nZZ
zh)a8ODah>!NRM?Q%8;xLBSox{TG2bJIb%r}*LKPSqX@x>C<g0k6ywSfV|QcoitC4b
z`(7-tWuyml`{s*tU}4<aRFMVUN_z0q@7YW&Qo$dVZAmV+*@vvY2$I|j{XNCGGW7d~
zq^IQsbh*S=|L*t3-T2}JJcnOXeOry!o}!l-MrC+L<x#{roZt_o&b;xu%+|nOWj(A=
zh<kricCUIa!HCLs6ld?#?$b6Yp+4N`gybQ_tQwG4q7RGLU|1A?s8l0#c_O5aCDmQ<
zlobK-pYylU=wPI)fk`l-ly>nQvZmVtLCNIEdx8+$UUrr<Y|>M35i^{z9;=(CABQ-0
zH@&0iFTev#AmH%rzb{KiD@d!6)<2~un#198la{PDj?X=;2U<$0n~MP7h-enJvf&$`
zO7#M=)@n1xS)*=LFC`ClHqj9%Z6mch1q=l$6N+V-5KVP)z28U`f-SPajE$>e#@yYO
zMC438Nms<G5A?gKl+?memHMQ~jB1u-L(6=EBGA;_?j7>><|xe_0vGVdG2Wyh)b-!C
z%Yj_qh9noKouxr{IQ`d{m&1?_T6`$E+gojuni&;a++RP>k7mn~c2JA7Ye@XmNh(w_
zr0Tw68e4=_n-B>+p!;ChHm3}_GRZ=Smh9#NPcNLH05lz@xyvPH$+}&r_7F$i?!fJN
zoCqEqp6}yelv2n#LR+d;jJXx*JEH{gIwQLO`?F=BdR-?9({e)qh-MA6wmB5-2DmQ)
z-9}@Vz7EpSx)_zGRM&MEaUWp|7<9ud(fIog2hktuyytLuv2)fagd!9R<vLYn3*x-7
zMkp*0$8y)XA=GxK0H?4C3>6!uYi56L_`r`Tk@faha8J^o;%>Cq-+s?#y|M{H#Ke!h
zVK2CC5d4OI;`Cb;m-{Q^G)2o!`ZrqlS2DYjLDB1rCm+<R{Q<3WC{Z=Qxp+jG^9FFe
zA_^g>fTD=+f&P|~R=@_JRxN6FFB=Dqu>PRI9m0-<42#51Jb2J0$^nq7gLp#L!G%~R
z8h7(H$A^+}1+gH3HAR1^haQs_|Ft^-nHiSHGJcRnw3E}>AgqVLW%KTPNE}H!$;5z*
z$Y)ty`7f#~T`<IFqi3qV^nI8P;zMA4C%eGxJHTATn0`_Fofv&iTyC;=ZXbd{jpeFk
zk&`3s@T<CRme++gE2CA{x*g1#c*0;lrLZ*E1EM}v;&!x3N<k(>-vLkV_=c1l=D5^o
zrQJq@<*7G2&7iC8gyZnVEeH=i&ez?m9Hi^*jFP?_si-Cvug64b)$x^|y#A8b#h5-i
z?lu_D<!e_U8|y<_>k|4mD`9DOOK37IV;2X3w-AB`-Nkz@e*|<jC_8kLTsNq*;o4DS
zmeG9L{i2uyQGi{`PE*6;JaHSk*2`wR#1dlqJhx1>I`bCl7BVnHN;2sR1b5jAU)Z7_
zTPFf4r|%692?>BE*7N|p$~<+g3-GesUwu2`P-^dWyA7XYd2Yx5`c?MixKE9AR9l?H
z37RORX|3IhIxl-#EJKg}Ww1MU80mzJ>;|bVv7v<Ji%c2kB9ULnd+5*?iRwoU_D7lb
zz;Kcn#W1=)dz1ALmy2CcQa$-C?_2x_MNgwgL3?oCJ>M%=gM;<2t_C5kRC~GMP)|lS
zkH~6fJ*IeP-gPmve>A9i+<g<$>QeoYC`%RfZ$0|C)XDNOt@ly?YSb(&haFCQ^$lV^
zrr-?0%@ZV&v!%exUAQOZBzko(t9lQAAsUzj)geo2xLl`@pno_(iOo@1(wPs?xJ<B2
zor^mn`*p;o&`zYqHpD`y@xlHsw?DYsx8VC(r3!dGn?N1HBJHl$hdFNc!6VKVhg6}$
zox2DzNs7D0Zw-DnRb)$}y`#<Fzq>A<SkesrFeWn_4wtaC-HBL_DobZ=o+`K)01YtZ
zb|mW$L+_hbbxCA<8=yMmO$@ByTNh>GNhoMF5(g2bgfgvg;neL#8H++t8z@H7vPD+~
z0PcXoJBYjjqq#qQK|BUWu?>$4XaH=3i6X#qjV5b&(0<14u&7u7_jI8}+BI>bvzp^O
zzP>ueEc@o?7qL8cc~>$CpY6d1tDfiO=8Q6ob6I~m%4_w$S(u?jGLx7wZcuH{Gf)n8
zxaj?EP>on9`i^OihB?EHnBbzvLd}@CM^u-^^^$fRdX<O<7vSRDeh-8kfD)0IB*`yY
zKwec(rq{eaGU)!X8{(i9%aJssB>kKJ<xT?6$>&i!omTM;rqm0<Rr;hjHPiTgeE@4Z
zXzf!udFknhRgQF-5!U>IN+dQI+n~ADbk-yrk|h*9xC%Hm3=$9-@r8H==+P8=ILDlu
zcypmdDNT3R4bv`w*gJpof=rbD*DitkVWZ(iC)6@v86_XjvjGNG`omtwa-`|o<wxS>
z#ounK5{+eUAg^o92*hLaD&AZ&OU9H@SxtCgbBa?bM$`n~hy~(HzP*;S6?_{>-Q5zX
zR&rLxZytAsPTsQb0;?9LczW1YZhDIiPZ+X+LyI8#u7V8*tjb&8Ewx3$Z*gaGR>YmD
zyyc)QG8~F!Dln#qD>0V#qrLaYlgs0j0E<e*6%;ez^qA6|ZSZ_-n0|-`!ORd5TX5pp
zC$bF5Gl+2c4FzInj(09S#=-w=H}JkpB&X)NMz#_m0r^;Cy|o6Xp@Spe<k*a60BJ>O
z45u(IWYxJ(OC{jdC_F54kJ_yVREy{3hA9o9HC8b$+4UR%`k!sOqwHd|tSY*Q%u&Q%
zLjFuO>GuHBXU(c?cU4smyAyE<if{oHv>Qch#pMm@On_YC7CLiGM$`G73}RjpmBz9K
z>_7d@a^g?&+@UxSL8H7!SROqN<_0?YexM8}I^*lPuAh!1JR!PC6PiR4+-(BWgQ3`U
z$Uw2)P<rr+UkRmteYESNh5z=FR>>TMNaPt%-X9osDy7Yb8xpIXxL`VY5(8;Z5!qw@
z@W5TJWnd~JHI&V@us^NWPpS@zyOcx|9DEH4XWvs~q}IM58j_bU&g&RX*bMR4iMV;2
z-IBErId0Ba_`5pJ{lY#1>rY2Q(iPB0^E|zCxM2bb?+^*xRU1=(%Cb0X<BVtBMQNm5
zKY3RBmoHaPAUsYJV01|vjsLywg*V}e8Qv4_9!kUzJ~FD7RACnR!^%ON5qE&1gzp>W
zm7qzO9PM?GrNsYF+WUaFao%^HGeg9I6DP$CKxjzO^1Lq~dI-z104WZvGzkU-Wk_LS
zl9szl)@?*uag<yWTZ*^I_1SxZ7Z_S#L`9@5U*tAzNm}+QckM+|+?;#cUPxJP)!p<W
ztIo6TZJ#|!$z^kWx@Sqr_LN?GxzBGXrFNR`_SuC*5(H=7dH?+0-=FXA&+DD`80wZm
z@kW%0u7bNH8G!Koc$%u;!ob;CXnSfsZ+{td5}iUU>usznS4BUy1Hi_1e2)N(=cjN!
zKl(|~u}61q8_G=;Kd}c@z>K=DHjGj${_NG?xt&U3v)}{MpL1XAI~^`+FIxtEzq2rO
zrf{EBZ+XA26o=~|tWnWQwm=jhxdq_Ry1%moR?lveYC1pzR1L@#_UjvtP2u=bL`#kZ
zy;GDqI1hT=RQ==iv2E*}kLA{RJK2o4K|^n1_Lm93_z;Q^LYHh4VplnTVDMKO`D^w1
z{d-pKERGQ@=?{}qI<x4;{a1JX-uVW3vjgPJ@13Wb<j|LnNd2iLZ|&yyNGctEx4U#m
zq2|hk-0Agl0MUqq2{w2o=L8Z~ya=GF`Zl9PtSy&T^xfXN%GUiL-i*J3is;mwn&$vN
z#;B<nVme8?W|{65%UU(U^}q1w$5`Kw{nC@i&t@PJe6Sp0@Wvnj_A&k{u#V>$&^=<0
z{z~yz8jlutJkj{o4_)7}V|pMRQTLC^T1IhVarX!9X04GrU?hLpf2J=iaiqBWxVJgW
znjl{Ht4dK1dqe;bHik~g6Xk3yuSN1%wxWW|<k4-|C%PcD96m$Ys{Lw3Aq0wJA>p_H
z_Y^!4B{+<yyX=wxPC(KL<zfdZa;IuL2S@6{T^kXlWqG~Pjfk7~IH1!_*lZ(<^H)=i
z=K6^#j$oE^OH<_WfKd|JBmTo@c4fLsPH>rZUHA9=CFSeFRqbs!Qg{zGkGpg5+j|H-
z#A`f~yCvd9Vrmq5oTJWyR9td2D{C~?^ScviF<Fr~@1lwc@{~FmQei?4x1#(yr*A=K
z#W}q}+!Si?EQ$g7B=Ae(K_C96oJzB6Ho5rC@k*=<nw>=X@b4bdWv><WW82O)P)9!0
zyeEFOyYnpm)Y%XE)98{c{;6%r*+MUK*f2)WVQL(Gty(x;cGgzz^xj{-R3@tL6{2N|
zYwDjWf`CaXUrk6&PKc89bU7Fpj=NMSeN8Q9-&4uGH~VhlQ{4LyI9XBYko6Mi%6}$a
zBFfNYq#DC&kZ4I$ulbA~Jc45Xsp7}=<i|K><d;rRO8RBabvav04mCMMI@Gn~Xn}-p
zXimu%F~0OD=0)+I`u<0+ZL6>Ul{#K`%APmy(vLM-cIy%ziqF+={T2mjbDROr=^)Rl
zgOU+UB+1Zapyl@fT~gS%a?iwtof8exO9-HvT+QEn6?e@zIz2PAq)J~ylX^;VUg~DA
zbT!L?JyO<gc-$L6!i(49BVTy#jiJ0r@oRvC1@uBtFHF|@g}U~hDBiN?V>|zF`Xhfa
z{ctnW5aj`aeZ$C3YYCSV7-SF$IVDLTporVf);Cb5;?KYE>KC49a^u+?ky`yGy6*cw
zuH1GY%5QjuvJB(LatDxshXq0;Mg#Sh!%y7uyEm^DQK9gx6)DFkCwmP_0?^T1B);U@
zC3iB*NuqxWXocZ%jjB84HKKfpv8}Kw2+v1=%Hj!CCWo%Ec&x=?seb|wmrx3+;<^4b
z3t7ZOoKm%k=bw`kNJlXTA`1=j?_Bn!!8QR0;;H;PKpe*W)T@JW{OZ{!n!noo2oaiu
znldTzx0Xnyh~+HUSGrT3!$+39!AtH-YUneSmvliOQHZNZ<h4T2o+2NmuJ)iS1Bx>&
z;TiTu+{9FFxa@AGD(ngg_FhF1?Q$ATf!$VIFFYWjNt5h4Iaf`>n>4H=B!oXPcBT0K
z$Ms06_%VQFw6rA8@nt!!><uXv=rVO&xJgdJ)IIg@)lZ8)vA=%d(Ve>9gt4RiAIkZ}
zV4E3r_2IvK+;4D7Uc9a^e@aalY*r7EsrGLsS`Oeki^fIy+bMBcH}>pltiMHeTBDKQ
z6HzrFag!5;1G)%;a=J{?l}n*GB44f+KpAws?m5S)3(IP;$8MY~3X4z9^4(CcOTzlb
z!IAIkDLq164N9HMQFQ2zsh?V;{Zk0#PoCCG?5+puOZu+*<hBb_uQs-f9&8vBNi`s{
z(#T=E`rd!jQfi;?H~%kpTnf&hhzT-6hC+5TU?(-khRaH0?@1M5{NSXmt}9F8>cH?y
znYwCg)VnHp5X$c@^kScAJmEzYQeG&EC~A~Es5>+=f#!Pz|3?z0IJrIrSt0h{-~}(?
zyL=w73gjJxw|GrcD0u_y;C{|ws?_U^sHF(t#gW>7^}zS6{GWGS9~tn}es!$eD<<|O
z6i7J_q~yF?-(DoQer#&QtCN?WB6kV~XSKX}7ZZwboZH=@%kHGY4mtzTD-KUU7Z3pS
zjaksOkm_z4=N}G!>WA(}PiUVmo+*mX{oRp|H1R|ZP@@rDO+srErY7Gn51yq^gCJHC
zIV<DXGd1!;BR;$B{^JMs+#j2>D<iXIsvmN~7FO22cN!0n*FEREf>QsMhkF<W&5i!l
zqY$V>UwSRJrp`bak|HQ&0vL?nC*EWtYo*i?+Fe=QQ(oD8=jPl!UcJzUoypbe#zJsv
zFdB{?gLW9El(f(v9K5r>XJlIg-vMDoi0TBox-kmTbzsl9jzLNiTM?ae&z(3jA8YKS
z(#%=>vBN3+Xp*V|40Yww#!SN>^_w4dd;e@6`tN-O)Ad3@A8|Lc(KXLLKPX+oWgyEQ
zVW5-4IUz6!2aUUH@Eg1rFDwZ@6;%_T0QE7TnlZhI{}R1Gf*s}5>QE0tkf)&~&>uh?
zy<uvq7+D|;jVO8<#xszFwA{qtm^Y5RtWVuD2ns6Wm`Wnb_23`Yhf|qXL5WQCGF7!e
z$!BaF$v@upHftv0&<TNY%mtVYsZh#Hd3SG?j8oE4_dRsAP<%xEcahoysxJu3St;#8
z=q#07z<wYvg0VT5FT0L$k(U2p_Prp}M+${H-u?Qn@Hq9fZsv=a!Sq4a7D@ri3JV}h
z&c%9Vu(oaIlP`0yf}F;HhR}>(PWYV2nVXI_#v(ouv1b^bR6qct(|hh89O4MzUwHmM
z?D#6IC!QYoa;_17%eZM&w(p;M$Dy1zYp?S&SLLw!H69N0z6xa}_Gzg`ai_Os@INXD
zjVMmG8vwBc(q;w7g37Yu+}XSck}|F-a8iGyGB{qqqs5+KfdrPbC?beny(}gH<x<cG
z>VJsyRkFBAYg_LD0ik)2Y>0aL211hnD@G%l^~S+ZbHk?_+sP2PtMREO016c>b`f9x
zc&>}Mymt0~$owS*_omZhGgL@FGB7DJr9R~iT_uS}I|Oq*;5j4pJR#-{F<mKoCaEvh
z9PD;*#f5E6W&OL|yDRJGm0G_~PkKd!V=*H&G^xS_q495qD%@mV)SxuL>I!LXh~0Wa
zfwkxQ`*+R0jPM{JP2}lMq-ZiCIJ49;63Hl9K*GX4EhvzH)?dlJZDiM|@rS7s+9ixO
zK5VY8KeUO{+>iO3p?DCC@i#&eYr))}qIB6hl8jdM%L>xuPD*LA`7^oH6$-xiMD$c8
zk)*t}@SW@_?=yPEy|a9m2E4vj(Ai3X+)2&#nIx`OYR{OEIk$=%aHH?njTZ*dcyPuR
z$$3h!o75`K{ddbU7(YJ+H1x^K+a%*qe-Ak}92dVUx_52o=ysdhQT`RrEV$o1<wH+q
zU0Ax%UCd@rA<@d^jp&@0vsA~ZfO%#`0N;tD;$ss!swL-T5C^1e?e`1byEglNg$Km_
zPI<rPNK#BTaSEbr$q1I>X|zr-GYQI@bs(BBsOz?5PC{PzX1!a8VffgNT}_gzVsr=W
z0`UL8^QI&G>U)tW-y6IP_r~I!Iz70hKKkmmC${~o=JXTf0VQ{xBiP^f^VjuLE%L<t
zcwpS$s16^Q^6pJEs)`yq1(!u(JW}8!#0^tgMMd_%Wx<PE1Qj9*WxQ}Rg|bq4FVUS6
z6R`QRsExW#0(A}1$%~RRORz(d0Z_}-`U`rh{>!)uN4DK!VJ%Au{x@un(^?Y>pi8p3
zvCr^8?fE1g^ljU2kt3Alatg4a{4ct%pL2$(05pL049{6}<Z%0I;gYv?sSp<MA4mwS
zzLVa;n?8!(pzx)oR0Hlc>K>(BJvs^eS}zqUrOs*nnTqV*0@F{iRM&fiE$%rKa3$7~
zZ&HJe6NLr4V+7dG=%vU;!Gi9rKjKj#B<Fpkv;th(gi@&S@Kaml9!=1;2FNH;zwz?6
z%cR#23t8P+{Aw|`6^M0Lb32uOr;lO&6Dae6nK}P{L$U3AlhRQ`RN3B-l8fBCpiX=4
zXQ=oku$T9>_1;6eF@}rHv8cC)W@9hA101zX96g#rd0*k0_R84@3+3zt=?!e@nxhtz
z6m<kkhJyqkt%4IG8WU-!9;jcQLct=(rCuyT^Wa*dsfc=+Y!aZ;Z9_>dAl`w(bA6py
zNt6}JH*YwLu2M^N#v3S0E7d#iw}xMdS18u-n)w<crAiP+c3zbp;aqKz@PjV_Em6#Q
zYQ#z8bqgh@g-Pdrtt`<$WN!4WRPF?WBKo$H1cy@XK(Rv{YitRZNaC>#r|DSB^V(Bz
z-7~s1QM|vda61>NFVRSW;KeZ<;ATS1DwYAeO1N(6c|zy+55`-zed1N%*E^5PEq{!2
zmh86fV)@5Edh3A*jod$k(|F>U-#|^dBfCW5cJ6oY;yY!0J(6GUfsidW2FMtG9S%>w
zL|}tZ7H9h0&VkE6sCXN*o>kbdqena~sXem64Z8w~a6t@yOf80W2J%z55{56x64bZh
z-@F_XW+JEgth(1$A=S%z3IQl0UVr_j6QsVhZToi{#aA_Dj?Yf}sm3N>m;z3z&;ReZ
zwYzrju_SNd4q~2fR~v>Oghvqw1xdZ%ySAR)QDI+Ot6GykrvNR88Nks#;cnQc|5Vu7
z;P7}^;s`2=>oR`-YOt87e*iG>n56qRAl`8J!nXZ7$Kepa(4C%`HD{47k%$;-xn9Qf
z`ianB2QdzD<`4p1Bt&CyOC!3Iu+Qg?>{u}kApDkn{*O4@r!z@yuMf|E>B#M6D*t53
zg8?Na3Z8h1GYZcuj0GiDIE|IZaFqIr6llN+H}Fzr03$e<&_xMgP)I-V5OOq<B<Hl+
zIG}JG4j~t?<R|LkP^H*Fk6)ih07Lw5WJ}2Ed-SV1(WpesiDU4zzPC6U$Hzfj==s@3
z{5a6P7vtam?cW}2HVzp1m%F_$A6@d0TgvZyM88{z9`&faW@7MNcdEwvZH_`dGy;3U
z&A)=#H|4!gYO$566SrX>Ch>!Uscr@bCp!9uGPRTdMihHYOr>-jhMWi@AsA}?84Wz(
zd`w(8L@r>={sk)d%Rc(Vs))EL?1XwGXj^K=N!<nt;0@jnVG-u`srqBbf4HOhFTQ(r
zy7@3*%P7a8OHJl{^Tp@iNewxv{X28jcW=M%OWxD}?a)4VQI*gf?xq;|is~I7??nUO
z!;VmB?Y=-Pc`;Lx4RHsKsnQZYk?>BB!ZMQt;)~(6UqkI$9akdocxfH9ogvWc3%Y)q
zIIK46I<AZQ4qVQST?93!-kh1VA45I~lA$W|qtImOd-W~b3R~*;6eTmMet&Y8-#^~)
z(d~XvIGuTzdXT`ZSNr<DH2+McFZ(sO;=ZRqOa-#zE_{6h`-`B&zkn){OPz1H6dGtr
z@F6;3AD*f5X0(>IDu3E5dlr`00H?aseX|Jsm6qy0MhY-pkOLUQ^BR#t5k+cbk9xN>
ztd+%=Q-<86r~xX`loZgLzQJTmzY19YJ@ymdK~V5CY};|RVZHRijwh%WyQ_I9x3Vrb
z?H{9N1A5elPR!+E>O`k!FSX$#I`r>y`(NR>xU$<TM?<<)?UVdk0BM|q2yMULDJiWN
z)!h~9%4IiG;-GiGa>p@|l#=z5NOaChL*H<ulvhwsZPX*%$f+h^1cMTIs*&P~RZf(U
z(kBy@=~41-$w}AuPwgSPilEO6njzLmpdBUP#kPL@<U7qbSNsg;+U@s$6jn>RpeGcE
z-bl!ixXB=K@D1uY)uS<t3>-G801C3f4Td=qyRcYzT<r%!Mb5upJPhS`omNMr)98Fl
zWIv00jbscb2{po`(4I`lvcA7waMpu?fT51w#t|hE{<WqQioO|>bk|hji2me~cmy{h
z&sKLiF6I68{lvZfb#rvv!(F)#JT2m=-m7;XZNZEV1JCVs<&YAo&TtxuwYKseZ++WA
zE#PRbUsP-AkKm-L=kj&L!tRLRRh#$#j=(vszE%eQz|+59x9d~v+Mx^hw^W(^DsdXH
zF)Tl1L*THWV}#Ko@F-hRARhu?888QvkND>|mb@3?4Xt0s$&hG#Q<u?R2cPFq63}R7
z2oKxYTt0S-=uFl7vzdp_f}o~N-)Gc|;nL=<ljwV1rHD#%w?@6jdFi2!7Q6=KKUs4W
zrf8VjwYJr_*_BgEE@fBnA6!-|`d(-@dyQ&?mEKqAXhP}h(VE0`l_F%EMbcpztRmii
zJv34OfZndz!u9&Z#%byd3&bSBCgNKZOfDfP&Qw_1Bbt&#@9p^jv4|y(=xt0Dw_O;N
zlEWep|0LHj5h~d!pYxYq{*z4u;M*jzqVilHs;;e|JshE|%Acy!*&~qndnJC)YkNEE
z<WfXvfN1}O=5t_C3(qYM7Gf1$?^5CN=2r^t4+^-NiNGkR0Y|YW1XMXD9_z9-GSwS|
zuiLODk=Not48xBL*%$YG>=uPnl?`IOF<EKj)F4+*k=D(3hV>Zr6Sw{HcPa7u*q$v|
zdv(^63^BA0zjJjomgt+}Ca+~TYPV6&ea7uZZQI|VjlI2oF5F#*IGos9&JonzI)c3x
ztat$@@zrefH2yYGr&tuE6L)~Ew9T10UM58z+py!cRwn#Rmr`X`gt*YHw=|nU)){Ws
zQ*~tpsZE~-=K^(5mN#k-8;90sCOzLOE{Dr~jTvVS?I4Ds6Hh+tm}Rwlg816diU_rV
zBcN_|ZB%M2j9ZSj`~o%Zt*F*E9oMO~i%f}CwSu;4+qL#_RfoH`<g*W*gW=!@a6GH!
zrgIrv$D#66-uZ1eW$8^iGS+(bb<wtRnJ7INujKZ4qpoA+qT1OaowCr;trm~Xq_uBZ
z8|)1)<*ZFbnTas9JIXZB$E25@?$2>CRUx)x(Z;*ux#j~8yj@^8_??w;?VN>|SYC{W
z5g~+J&t+B%a@Xo#xX_}mM#w}L<*n7IrSgK($o%snu0n09C&QwF!w>hYiZYop9w1l5
z;^3AAmKRT~IT0<<iP&Ng$)~Hm;5t5%2YRcYGRJZmw|?v4cSa)!j<hke%GjO{mJ#AK
zA1tc@lt@BU+Q&I59?K9dkmI%d^sEi0oSn?(a)VKMeU`G(MFLa?Gg3?za>cBs&Jcxv
z0%K5*dJw%+I^?g80=yMtX`g@A=K$7t#@%a3s5CZ_ZDHW;ub-(~$k<PCS*p=kiDk<l
z9(w1E9{<<>xbjcNTMjdjVQRYn=;k2Vf8ce;{<ojc&HK1$Q+lKavTNLSDvle^*uA@s
zdt)r*jJ-Q@2_}wiwcM7wvzf8i#}fn5bUA18MK_gkOr~w3wv$h>1%P{(Il|9D>A&r`
zf839YkXzSo1Wq%a$yPmYll!c)*F?1~I<Ffi@<l_<jM;WiIP2avddpYKZ?7F!Ec?WE
zOV@VB#n|$5UMA-VDR?PsC2%Yk9n~qeCL*Cqt_1=uYayYQU1N{Qqg!^7Pu)~BqiyzX
z-RxenTH|eYo|Eym)L|bSemIG(bmf63tbwSSW9&ZadsT0-a>u8mEq-l#Xg_Jka|9!d
zyJ0QrONW7C?6F%*nP`64J?E`4QB4yf&7+|I%-IrMsfD)m16e8-YrV;Igxd>j?~}em
zxlUIpv&YR8wP|#RL1Si@yq0qyG9Rd4*_X4%Vp3Hjbnx9WCydxPa5Fowt&wA{7dXql
zaVcpOM7PDYb7~IV)vNe&E@;VgPUW<=huUy9K;)n&U`~-kCS%Wq%L+Ys!Sfcp!BD|b
z0%z8#xwq<NPIc*H!s4LbwY>@(__uy!=R-pAN7DXCIzPJCFccGSl-vRoP~)S*S8D0b
zJb6yRJcyW|W_x-wb`bfEZaX5*CbY<G(yey%Mcdm{^{se!+xIK?b}zI$w#n?M`sCvJ
zAy!7KheROLD%iQ!k^;l8c;2k+GOUmIrNXrf|9UsjSkz2snxnW@*k+a=TRI=2on}He
z9ebu4wM4iXro6Vt#Pk^XqN1Zfx2E+}SUnlehufV#<7zvs#sx`{P|7wP)gJE7mj|be
zpXoa$br(!9+4ee4EnN*LWsp0>vt~L=gcr1o!9}bOs-SIaZ9M(?|9IQ>MdclcGDn-4
zYOa>%`JUM^FM!>71aH$Q`q#1V<&f=6-xns^AsBV$m=75lhEU0I2(F>1duLwD6wqpQ
z8P2{O7S2@s0}6DcA>`_sir=rt+jBm3$NQ%ieLdQ)caPB6qQ|+qUjGqFANcDwJf53Z
zRe!A)aQvJy_#!5UKj<G+->ihcz9$2luQk#bivrp%!^P}poSFpds`(I^V|8@B>%^Pj
z3VA=>+uYkGLT6A9Gregj#M|yQyPLzX-}Ab*S=PRpQ#tGB+Z>v3&Q~>ueZlFqewysb
zOnRU*WtLs4HHn0?bTqgHy(1jF{<%*CZjnbe*uFD%j5K5(;(&eU!N=LjKc7T@?KT$O
zXd#t}V-qeF*3w#bvemJR2A{8qkR=8N%VzhL9(Euzzr=@alk(v%iVbc<su)#abn^Ao
zf>(pd^AI0_Q>Ve$XAv@V)~lTxm~(5kv8<PvX{;W5#zqNX|5jVd8MbRS93@{*kGi)~
zUXMd|9D~Xq=p_|fE#A}CZo}XaolpnEa!!VJh%~xq`0bl=ltSlevL_6DD|vhX)7<T5
z)VOb~+;l2t7sj=CrPtc-M7hRvWNSw5c+B(^yMVEixx6Kp(GQw}EoX+C0jIdE84L3h
z*ixKA%n!#}P`)p`f;qqPH>Wbib3TEZpgLS*A$a4!Wp8>}+d7&<M@ZM;Q+}iNK^wtl
zGA^;sqADRhM;*U9>Y!i@YP%J6W%yR$^*OscEi<mF#9Pvg&Xr_fw9k`KDOjJ~ZR@KK
zr)BjU5Rr$rB2Tu2daT-Bv)go#j9v^u<RbV0Qo9y9LVe0CsR4Vy&eiOkA55|WFm_|#
z#|O%@2ionPmZNhuQ@3;4t%cDs*XVG-8DLUtZc{lHc0gcX`Q6JrhiA2tjxlkZ?JBch
zbL}`|_jxdQueRMDo^;pL1H0x%IlI<4yPjjXbIWcmYC1XT@1}5lvl&KBQ;(YV&zGrK
zQM+F7Gp>KDyW6AS<16eP7daa<BlCgnYt54$_|{u}E1H>SRK7G4!;Hv>BojAwS>*G+
zr<|ON=Iy&?Bz^z9$xOO*z~<4t4VUwXBM2s}rQA8MV4PsexETyjm8+f6(q7Qh=fs-I
z4p14ARM&U}vd6IOhRI=>+SeZa7gmgbP03zG%cBo6_p#^oG9?}o(i&@8^K3Q?1`xKq
z++M^-NaNM%qtLK5=g;)e<YwiEHQ1ymU9unf7MXcD(vWH1op4q%KVskdR`%^yo~BLh
z7&{g13f6~kV%Q$FaMOY9GFe{Q<JtT<&#d8{wV6406aR{uTy{sbY)iYAi^8hiF}79q
z0u{2T2L;wt@oLS`K^RFd+4-8TSpJn$KjHzxYGkDYdpEjBK<sjjiPg})$I}AajM{9}
z(94MAV$Vf2HLNDRF$m1cq5bwdfjxU#*|lAsTWd0zo7_3vrOrI-nu*SZ{_UaXLi)O_
zGBXa@n|_U>%CG$2ccNWnQZbv!;9;>LB09k<&+x~XfZ8sGZ>^yCi|(--4#<wQ8!bm{
z&;W7`6$*uqk{LkCIll<On`zRGgf+l}a;3;<+l=9@51IT{J$-)ktyJbN`}rrxfZ62d
zLnM*sQC8FQp(YRXRS_JYJLFpPyG?J^^^BVxM@1M_uQbbj*(loLns~q%cQW#}N6mf3
zOB3>S$vxw8(9GrW`lOe=>`r*=3eZ5`e7SF*-lzVR`^=xJ=)cKsCPVYc-5fsUtyQY@
zinrgJSNXnA9N~;Wa@eL&y4IMZvsABe`&QgOO%R^9E*zX6n!c)hNMlo|4|*IW|JC2I
zkBodSm!?>eNJ5kYm~0u6;>#eu6TRpYZtm!SyEjYqz;XY8XAWd%#?8!p_>%j%oIRdz
zs>y7o_m!NTd%QTg(l<H2G1t4N4odi7=M(~deY~zvxleZpR=D>nV&~p+*!wwu^3=?O
zo&4le2kETGIa=Yn3qQZV{Nmb5pSz~bp)G6G0k5x6f#taKN3#<K$X#R0J#}R0sfzN^
zX^1=S90`5vj;DWaT^ud@2cpP}4O*gUDLeTgZ&$yjU8ADD6~7ae-FPONck}o+I7N3C
z!!gshPZJN<JFOyj(L1m*0=7RH-S~dW)fdi<-`iK{DYOYV>s#{jyZpY>deTfk#bxHX
z<og!+e4^5Kxm`v@n`)a}-y<DEX?m_*%C7ULX;Qh})tmWF><R@5<mv_WsUs(IQTl*6
z%SP;fr8_=Da#w$kb;vsq&rS4$rGAT$uu+o72x>j(_D5Hh0x_eiJrRU)?tNuI%oT1q
z6n^`kbDY?Tea*jJukMOCWl}A<ALw&8K6kzwtv?cOkFG1V^#{3J@1h<%@vcg?lm(Nj
zPM^^I51x4Hhf3}0A16|L|Lm^!+)?iq$m2W})+e5QkKTHjTpSz*`j9WdN!6-bTP)8H
zF6v@^aDK`QmejC+RXx|wW!;mZ6PyXH(zW9+U5v)hp6|Nk=v$lvKi);3S)li6iR0)W
z@5ZE>xORWkcNIy>yz4QX?uR>Gqd49jdG(<s8P=B@TR-FP+Ic$%le)Q`^8TTmMTm;p
zx-YkL=T_(CU&1F=aA<bCyH;<#>i6eLrz<^0s`>30_jsy1U#N`fcP;Avae(xLGJ^1M
z$F_Ku(mo|PwBK6N)BbDjQpK1O8s&kuwe{Mc|32{)R}jA=DPtB~DU#v!+kv>PVH5J(
zA^+)J?pDWL*gU<<bxRWxZoK(r8QalcELQ!8qUUsf^vX_h7jR(N8MUMyh{hYGrON#g
zCvVgz3hyb0MYQN(X*0c?B&x`twyV>-`hYe`Dk%0+0}lVRtH-)-FKcaCPcv*?<6G!W
zha5!jKb`K+?&>bUdfyiwHujb89K0B*G_9p-=>_+Iu{aJ<P9tWbVW~+Qx!l&ClTZa^
zooV}hWhnnPkJA+X$wXzk`Mc|vxNGEz;<TM(GWRp_y@u?j?}8+c>}(K(Kk=9APnDI^
zVjFN&9$c_@v0%9XO0vFe>#<6?){N}w=Dd<gwyb_+r$60w`rUJ?G%Q&fj#YZFo4a!C
zE+S7-oq4`lOe<v!Y-=V_8)ebb{g+I%eQ~qzo~&NzM)pA+le@!_Shsnd@oukS@V&p7
z+d9#8A9`+c2GV)?HhSkgt`;j}JF^V!WAAY}1PGc-DCg;YRD2k}@BN;vh6YnVV0tfm
z&N}a1pV5nYo!>j@l^lXu7Af-8Z&Mt_O!qA^tdhg9W^!BWX(-e#9SNt?SJsYFbb|ea
z{D3~>daGX%cg}EY>5FFk8MmZu*nbWku8%2-MgZKWZ`ET1<QGNbJNxZiuMy&<8x}M;
z_E4X89$Eu9;6WEq`9ikFPAhU$WogMhpQV>&cfrl|)ziI;R3qwl(?NaLGrZ@>M|xmd
zF4L;%-u_UC;otuAxtwJp=#~@>RzUQeIN5o#<0ePEQs(A%i)*|aNpJFd&C=%n@uNFS
z4)3(z3ws#Jl~oAAj^wIVuRTWOuBiE5e>90~-*S)VK-F}frCPyTrPkYr{9f)5ic7X<
zzqjidmRhsLnVfLJ4X~Vl-2ZcDMF*O-QA!M|iy4X`60(XA@ld6<*dB0>Fl>xWFS(q-
z+B5yaozLqUfAZMgIHYz`ZE|PejN}%*u@S3=FvbsH4;7u9vPLBb$j#+yA0bXTg5BDg
zMOU7q<LPJW7JWMu6SHBshy!^o>+_{s<H-6TX_Q1K;OIc4TbW~ZvgZBibJ%*^*IH6F
z12?PEBVa^b-*xU2gLVICQ7^~38e6b&;Rk11b`AaA4We$*ZN9Cwa;P=$xAcmSPHpXO
z<3e_ui1?W$j#U|Y64MA8f2Eo3-^`T8=A?hw*x{Ow?w+AjVu9qUVg@lc2K+LO;^N}2
zaxv9izvfOdb;G-M@vQmbAVQ|COuNB2O7N(RIENIfJ*7OEnNZi}hxt-;womH_EqjZr
zJIoBt0O5!Ew5z?`eW33Fjo_E{7_(Qq`oI3>?&v=ZuU)?pdHSj0wZ*~D`LEvlLi9-I
z(9y@j7oy3|q3O?u&*$^6?fTKQKFH5s{ezd0Xs>O3fgkH;U$6dd#LxKk>I>23_EkTA
zj5ky5!_oC8hu3bo_qFErC+ll-_j31_raqmcmFrLIPfnWO`J;cj0crX>!~D3ka{Yhe
z!KF*lUw@IG53IKG!>Bm;*Q?Dv^6a7GZ|ckSaQdU+Qqq@iUq&=bGj}DOc_AWjVBPW8
zxBhf*o?q?FU*G7>^)F4)i$hOKGwZ^nH$<72Zgl61^&QEW2vOhY%TVe&uD$+mgS0@N
z@)8?Lbl#S5J<;vaJja@`$pdfl*W_EOmNGGaOuqSEF_TtA#jy`oZzqNjB9h-$+u7~j
z|C=Cl$p?HBeg8lCLbHC;>qb{@e3nU{|6ktL^{f$!iHtPUEjfb?OEFF!YVzqhpEQR>
zY}R&9FCaswQ1%B?#_fI0pEQ0gKI3|`^Ti5LQ>LwrQCEw8Bfm4k44og$maCSx+mz5T
z=c}FJb5-*=0x_JORDPvjcP0xlxXDyo&rY^Wwr{W_C{eKDA2kPDiWB&Hwk+WPlDD8*
z-qp^pS+!$C4`=+`2K3OQ0$3@f0BV})d^!*iwFdw2<58~)_uFl}3K4OEfM~U1r)})V
z!&H<lZ?VQF^9uYfb3)CiXTA84TY1*rpw4*lZ>vRa-MwT=Y&$=2PbduU0bLI{G>~$`
zpf!FU%?+kIb_MzDd}AAXJQGG~d_jJ91rr|cv%(_4jGJ}K)vS#IG=0>cb>gbnS8ngo
zKFq%X4jkOBZNFp#p8@?aVdo?5gqx7%v&wc|Q?kv1ca$<d3U`8mEod_sdR=r7@R=yR
z8{S#BnQXB%oaOMId)|uO8lP|4F(%#FA=m@F$2WY_M?rBbOb!v25?v)04t80k)@4Oc
z;x5pB6xa<fCp0o+=KGK%xMDT|an-BvLJY^{YRvS04a+jd_OdS?v1g1jw)TP}<-pc5
z6K3DnF~3q&Om=fk2f;EE;i?o;@7Nu?|AMbD@OHP!?+W95*9knBWBpuFK$q|==#L!*
zSbKB62GkS_7!>fLaq{VkC(uM}g)=sJ@-fC}ZZ8VFV<EbP4FhC=9$fxIo)sDItRH8Z
zyFvgWHeD?C>_t<@e2ltL8ZvTf)F6lb#x&45Q>=RVuF>`MFk=~RM=1=yXH*-|1S8KK
zim-@$rlGSE&bBKe6b3;q<Cud%Hu{yh9F%AFtF!<f-X;(Ytz)kDyo=AI$f?;)oFOB|
zFVvm)feHQmF%I9hXXmS|@0?HVQ2v!v6gt2noJ~+tn?36w9jdt7&uqb#Kjk0swUs}i
zDxn{i6mx<lJHYKGDziDg*_G-#H9POl)Wb;^TA2Ze2ntSU@LHV=#k7n{E9H(o+pbS$
zJN4+8fA6{KL4d6Ob{hde5sMwSGKn&cR9J>4pe)}HMLogn?O#&H!}AlRTSxpj$fo^!
zk5ek%n+s=c&Dhx;NuSU#7Clpg4frk927(KEHdW&skPk5SrjT6=3kyLC@v;X>KkL<A
zi|rPkmC*~=dMuBs7g1VHT9H|d4Z{^86jZ?K!@XLI7nNt_Vn3Y62KW5sDw_;4;Sz}3
z0;UT6`5FL+ZVAl@D9W9f+Uz5eiw9%|OU69nG4ldD1O?lAefBLRRd5+d7hh!62@(zT
zfYB=t*Df3824^*a6VZJQ>L5T7VFF#6kJ%+o&Wm&I3}Z_9I+KP(B_R?MEdVNtO)dlc
zv7jon_xgQ3fsDAp6!X*$@0q=p3+RofYSPW+BPMfqd$x?tfioozYehQ~kykk|IlfM9
zlGH=8Coj2mJ3kV^>=<c2QeY(hvVublz%6o{{N->i#JSL30UaV;7@#RemGV7eqObuh
z9hmv>8=r+q&?WiiTTrO@kcbb;!4F_Yxj2Vq-RFSaq-*w|sRQy@gQ*3X6)r>rO7Nh#
z55J@p7)KKT1VO-qcn;72ixM(IOB?(rl$$%JuKZ@d72&5v0A>>Dhu{NkY8fv*+hfJ3
z6~LInpRI~KA!_N!IG{{&KR;wX0j2<0TmS%?r-roc@grkwYaSqPMJ+4KttKB!1J(n7
zdn<OC2ZGtKI>sn_w-IRqK{I3nH8Ymo25Ff|U-Ty1c>yVPq@XhX!2eAy(3iZChu9%N
z0f%j)NR?I0@4&wELo79K`<+cdUnpPTC|=O+F*>;P?sv+aFkQa!iY?YX@@=ca<O;ad
zN>KK|4kqhX%iuN%Z05AVS76s*W6m53vi6`x)Vx+lak-HOWg>Xt*a0`z4-CAWq7P|q
z6tyDuGVIw|b}fas)U@5IKLh$V=ZAQWGLbn`CjDv3L)#<B9f*n%^Z;94^ngL(v7pC(
z7TvElZWs<7$%F!(GdrM_E(^=_5>+Quk2C3g@3agHB94EP@QoH9$3S6W?Zdt`=C|t7
zl!zwW%*)glwQ~VjomDe7OUfI-d8ilO+~NZU*&6q2Fk8#OH)oxe9pFAT2vyuRmi73$
zw?pVYo1LMx7$U<>=oSPD%{YW^=@}Q|c42$cL9ia09k*H$n}gM{@F(Q}G?U#O#{hkj
zpUbNXWE|!~VFC+mBNJ#<f911pYcL}+u{?zyCO<OitgUNoYW6tWUc4E32Cab-El+Sk
z=!O2xLNwe5i+1JJ=elY6c{`Kr^D}FMtK0rb<+}4Ol(wK?iC6ye&uV+3d^Pt?+l$}`
zdDfAdWy(xKvP_o&U_0Q>A0o2SoN+soPtE7%k8bSS=sr_WlW0c+lkEFDqWUQ!y814A
zYNfY-f6)fbJ5%OhAu0j6x$*m{`fF2D5m}SVx>1CmAbUvV`c~xbd|5p;=>o6Wy~q5%
z=)*W84G>rs7n#+&7d*|)f5M{<bZ)Je;~2c#*{JP~={W1c_{%@|Y#C_Oi{YVO1TffA
z#tkDzkY_z(L>)(a<3(RfHwMECJ_1V5XI16CK$Xh}J+Gt)&#JiVR8+G2b)n$&dupDd
z0^@z-k&DBm&+fA=nMm>%T==59#(?q0ef!-P-6MX03cu+-(D1>qT;0Uu(s>Sv%Fg%Q
z9!g)cS^Cm57@n#2ladCi+^?@)z82s>-RGxj=a35+W`LJJfdIuqPf)v1MbD^>fPn7g
zn;|+vlCYh;+=u0xyc?NUOle;m9PnMP9tALz>Vr8~z7XmzXd-gaOJGHJ1q?9}3VnYE
zHjcwOesaBC61Y!KxpV5HFTEwQ`Y%DjV@M}eH=xL1cImsu5Bb(fD&UNsaKTpZ0Il#y
z;v(`Wc%^$rj<7r(dYElbe?|8XS4IffeBSK^QmVx6+NG_8Ds%pN?<dHt%H<x4FyVK)
zdAKP^;)E+;P5+m2y{9T)_ucJ_?!WGP`jzN}o^h+{pw~YRl$Sk7CDkm4-ech(z}E@d
zVjeVW2&GzcG<&-896{Jhojw{}nmCaKYbu?tI`I`ULEYd7e>I;VBGhxN5zZ*g5eN&6
zj9~MzE^(l{o+0%SOcc8wWzG-}dbmSfr?F!j)mEEH7liDg=k%C+$HbC5_RvPAy_Y;z
z7x*Fa!jV+3vKL%`%(cwI=7a8hubf@Zcium}q5#?UdWSoLMWLKgr=UH~GpEyftG(MR
zElRf+vmU?@!|V#Y5SFHlwPr0{Uf{r`u?EfwM1Um-UjmV}BFdpe9LQkj4uu)}a2t^6
zcGba$1|F43Ex7IjbzJd_ASOF|?S5B!`azPY%tV8rO2D8+Hy7~STl*g|y|-R8(T82a
zB>q?dan37XI?|7EdaMK7oahF0yVtZk@)?sbu%yP0fd&x=UO?-enzz2OE45vv34$g{
z6of1Q&{|+&+%zZ1z`-B){U0fTG1n4u<_MfKP2SUGGYp(@6#CgbHZD}uZ$B^rxUx{_
zAAg80+kEDZ?4<XQ$c-+$EebIcb5CN6k<)41(j^0NB%MA?v3Tibol+1Nx)aIta+IvL
z`Sz>}WK^ctOW8vLq*|mmc};sw9w2BIEiMuv!psVE4HdJH0%wD&33+c8@}6;ef%g#e
zC|W>!FDkGo_y3e$M`g9OZ42$3cO8$8tMP}xZP$oOVdoayqkxb8QA(Odprn4UO!2sz
zOM2^`@79~qJa`?;;r1?aJjFt}-|k&3Ly^1*(Tc*3UAp$~jxV?))If%Afq{@#jIQ72
z2eTkOWp8kkpBr!hj&tBdS&W+VU2-gGxcA#Gz~(EiGv)@4fYMfPL{uWP$}Yf(+G|e}
zh*I*>y_iQdW55|(b`~(h&t)Cs4z48lA)T+O_M!`sx?|5|c{iOFqcL94uQ%-v&_9kL
z#&PIPBe>WJBDlB_y@Q9j?m;C0v;~n8Lx#a_3}_H2W{GYM(j?um_<e*h1;{h7dzIAO
zrV_`8UC_Yk^s?VuRV6|A2iTzp2pTBWIo|c4=5f7XN(HDBbTkC(?i17*G&i;map8h~
z;QvXj8=!>kIm;gd6NNW{Guvh;g{B+_?5f#uDsxHqK%4}Nt2bTS+c^|7P}dqgrWSz4
z1t@7SBuno0Gp~6m(zwRDho)s4_vv<YN-cTQKCzmt!`jLqHRt=ClS(hSN8j%aIt%Rd
zhhN0fpQZ{>*J0`|AGp;M?6U?8PMdLH&(--gScw;eg|lz422iJKHaZ@EV@uQB2q_=8
zoLUOlQo15jIux@?wR5uzq?RdthBy%T2R3FUteH0Wnl<#K;|>~UG{mzNyySzbTL-^g
zV@f+{YnfQEI?NFdoHIfmok!>1<-34fxxO<Z8aDb?U%_jdM@$AulDqFoW%oJD)35-7
ze6T$P-viRKr4^R@*s#bjWZI!=7jP3T0+%(D;`%hmmZ%C+IOg9ME1RSh5IrpOP?LIk
z_Ok-$-O;#K{CkLA{Md<`h~C%tO3OD<v^ODoU}tYc^o~FF;?F|#z~DZABEbc(PwP)!
zG8caJ_rJ|;;qN^7Pwy5;4=8Uvklyt#KDhP<h$i6T^&5!Zo6yCiFHe8;M1tu3{+s&p
zcj)5wRdn&i7q+jWiyyd&F8;cpi`Nf)@+Wv65ao?Ve)w{DP+-B*cjIJ4;S0^xR!+Ro
zJiYWb2@(_;CYm9fOUUvKFFwTEp28*-bB`#NlxVIuFN1(AsZ4?bDhN(;pNZuk_#atU
z*Z*csu=?rECR>o&n_onhy!nxD{&Vs)vFPfe4PWspbFr7-u#(H9R{UYX96H1@#R5f)
zq1}Vfp!kLM9Kmp*L4sjdcNW#?X&<F#uGrETPk}K;4A+)J;1weP893z5JS)gWtA4Jp
z26&>hu>rA-i7&QSsvUgYxX5RZU_1C(<!C>235-@jyWnKHJ(;V2Ih0A=Z!%QxnVrw&
z*$b%DL<-m=X-^C-d!8B`lWm!wbsGYe4egR00Q6z{!`JBxHk2O4Qb6N2y{MavB94vm
z@G35NKFWN@^}CD8006Y`%-6!Rt`3x{pBh?$fv_MFI`IE-;CVpITguN+TDawIKgM*h
zYGQ~QnNtt2qPDl)sCBbvtNwOp)B%FQ_9B!c@5YLdJ1{wgkwJVRH-%o-*w_&8v=}M?
z=*yF@Vu+NhU_oLt5Cl;LLm)WN@_ziult->p+L&bwMMjb!g?7vsz?14HXm1($6VEc?
z*w`(eLi9E<a&`$jmM7B&OECx`8OG>f|D`ee+ly+!3z;9HHZgMj*`7i0(7@I$Q)p|N
z4O>RHPyNfDxZySY=~NWcvP{+r=4K7Ng*N#gcWj106x=3K7@B})*k<v9*Q#J7Ian?P
zFV7G`NF5?yA|nA_Q22Gw12{)m=@|hP`n4cvfVxHli7hCvA79%%0N=&7nKJQ}{3mOa
zo~rt1O%$6MI{+6Ht4aW8W&@-)Y(?iFBk(~n>^jB+DZxOrW@TNa%RF2Nf~7a+-Y$gg
z1&f|f6t`(H4e(%pcW033M$$I~m}G5C+q6MfL3S(XeVD^DZF9N3=*@cRJ6`PZhM9y$
z-rw0Y1QH_v@*z_#v6?ZXbYRK%hKtJc4gx($DYn^H+GSrGKvH6c2GcX`j!htJ@o_%|
z=p49v+gOT|0QRz8;HkcUV3;$CeDC`hIpeGue+xa&gc&@C-mC#nU#V8TYHLwdASnN!
zM55^)7C#QJ+<({_rVK(7&JNefq&?gS5E{lN%-arYh)4p}`9MOp=FnXhyc#Gh;G9N#
zwHQahPR@khZHyzZ2lxdl>2MnkDdQ08&$P3{FB-?_KqduP!nB<2?_iQ6VNevQAS}%$
zq@Lis2p3=2s_%_jJ#&yq8low7?9f!H(WxA(HJsM9RNx4q`pImv5sj(1?j~O%UM*OY
z;oAaePN-BH7Gbr($7Fvy0KKhihn`*Ka^hn%vd|K%3O^%2M;Khtc0`2Aa0TOn1wkXw
z!XPXI@@YZGaI4lWEpv$-DjSK0r&C;w**^>J2CGXRF!t-Ma?T<wS5{o$Prz|BG2z{`
z&NrfJ+f0=(aTd!0)LLcR;6H3eGz8#6#(?V*ScU*Pc4OOVf#+Im6^2P*pHfaR96lA&
z(+B<_74V>#C1AB=!%5T3Y#s(A7--tCy@Vmi`Z@tBL9)=om-rYIEZ>xULR=J>#exdt
z!NMO{XBuMY0^h(JN|F7I*WLoM7cJ)^go}jqvTHXHIw|2tv61KULa$7R7C;#TY&lE<
zZv?aiqmf8Mnb{tGYzk+zY-rUc054#-3Rzh#ZC6=1mV#e?{8f_rXpyJ!Vp{TWhCmPu
zU|xO|4>KIWszAIDg(vKbS3rX-9B7U#G^BJggfs`4KWnh-b-gqt1OY~&#um<15d0nn
z5E^~uiRT~<)<Oavh5aKrm>wZ37K-u*32m?|S}-9SA_raMLEMx421|p!!@)Epn7jfn
zY#-q%$;9}?=kbrVv~_spZ%=atPomF;x!uhrMqp%N=)6t-#!foNw95Nr{45~Dk39kw
zxQ;KL&DO!G#;2?6Bv7(o&KjBE=^y{qTasz83{e6yDKdpJe>^ybCLtF#F%9w|b7P@m
ziVDYE3BBC>#>H@F+XT#;2kI^B+TwEPN4#Rzl{KFOp!OnKPbHI)G`tKENQ6Js4>MwD
zMrLxi5NV69x7ZGRgWS1}6{0v3(RzbqTF}Q$@Gk=h7n@8-K)h3BA0Sf*ex<qm)nDkX
zp<;tlax21C;@(*uVI>d&+=M>~6ANs>QF&`Is^n+#o?VD=F}qD@DqeK~sUYNS0wtXV
z=<{_b9VFgAyk|M*$L5>SXgdC8IY-o{hzdKOMxKB}btX-o>i>iW&(V>XWRgWi`1vH#
zch;_uSprk+!FZ5(ww4Xa`Uw6YN+XZv<bEW1hwOARlFY0*1E@N<*HlVMeaD=s8mfN{
zR&k9r(?nPvLAJ1>)oMj^h#_7r#y0b;S`H6*|MNE&@FESsOQ$i`QNj!z=z#b&5x<__
z0qTo8Q5STGDe8E8JLpp;ZXpgNz%En>lG#)2j(`BQDU)xa_#|rx{)Vzev^vFQ$Q#CK
zOYJi**xR063Gd~*u@8E)FZrEIZI^2AyxZv0f20<}D;d?+x`6LBlmQvaoD)PU-l41I
zeG4YWPH|H)LGXf>{j4v<PQp+KU|7B22BgNXh#J!pDz%}OpWtlrAzvY_b(bn{2y$x?
z5!WIhF8M2xOY9P22B_A}d*C#QhCAu*pRyYxsdfJ06&sH&fb)zVxawEq)+;AeYA6-A
zu725HW)B|R?8R5A)qcCbeSxAPOPik#>nm9M)nfgmesa7Uh9Br#jxm@ia)H%{HRxNM
z1qrHEm6Hm7wV59Jq3<tf@1<R!ZRJCLtPc_nd$0hsMO4ute<2$_9bR^M_B7FPmy{|V
znd17BN9~Qr0X_I|28?U#OMLe3U(2Mf`2M$ul!6nF5g~@L36KKq3ce$J4CtnGhBy`7
z;lxOAs0DQAlE!oe@zA>8C2(aJNC#r)R*w=@Y-bAoTGafB_?(cRif_FSuuXKrt=#Cw
zh6~tM!IHb6fg%D;cMi8V`@wgn-n!i$>we4FHLQFhu!y&#8xp7#Gx=6ODXb-jSR*S)
z0*0~#FvW}qtV}*z%F46|^s(BTfK3XgA>i$>0WtK<bUI|Z7B*uD0|jYNKCENrm^TF0
z!0@=An~7wiIl6S3$6c##yBO_@Q`5W7jiiKyS#leo1Uv?8o_938wS)TTw9bTPp}ZAm
zBv0y30@YeeWl!2mV#F-s3+WNvienm*34*gNDC?s5Z)3Bd`C@t`&I~0U$+9G?71#@v
zI9IxMc%YWzSWu$QKsOi_M{fumC1l)UmMn`kVeAZ21_}WY7bN{9<G`|@41Qr=<X)>E
zA2Uu0>!3RwYKdml1Zi@!KHMSV3AJ<U)oK+PK)ew_O+aJG%4@Kt5)e;|4@%cA?I5F(
zQ<c#AQY^i|r7SB;2|@9Y)lnQU0TonOX%>O;(M7Idc&n<5bOvfs$%@eli%VwVt>7Y}
zqAX-(Ofnl92%09K8(H5gA!x<55&t~Z^(e6LFrKCnq(*C%S`sQ@PFP4<l+KsHL20rF
zRPThAV7Mh&XyQDV3QR~sxF|CQ|4x%ol9=$qCf6||azD6|X_41_GOQCKM+3A9ae&e?
z2rd9fUPo*9^xigd+cNQ3EjzMmD629XL$CwO13K~82Gk8_Buh*K@M||0cAy*Wv*l?;
z`via?`($knw|iDY%xY=42Gi&rqDxd@tFMM2qA8L1!v?hG>eBboE?7Iz5q&%aJ?f8s
z{vAknSRbpf+ZYMR@~oj0K?ODeS$<4%Qc#hYOHE1(f&lke*j{pD@F1hNnw3~HAY9!t
zBXgmJ71o5yLhEyN@nem$8Cy`U?q@VMHc&2v8_GaZ;J!Vhka(%x({ilvgAeYOO+0Hy
zh{{}*ZJ+m#)gdY?{~BnLFkXhc%!c3zkMLfwCO)$c!9C=UqMHZ|7PA$=<-mmqG4ROB
z5)%U&@GAl?2^StJBBf(yLbT63x|6r8Uccj({HyOH?&^W|K4QQm0P82QVDX#cufSWt
zeEwb(mqc$RkPkms<EGvW`TXY^xrrP7qZ)boMpW93p8T6P#*-y+WdG$od2lr-?Thsf
zg-IjzgExk=<6!aisq~W+@8e%ecEUgAWdsmHRgr(Q9GgSH!Hs{gF#aWNpj6)Y%k<Ul
zfA;sA6?IWwt9lko4U75*UP1@*x_Qgr+}597&W+$lZ#HvX*WYW<jYv{VoMwr}AE<&s
z0gWLoj9j(?>RGL;oLOjPh0+V?;g(1Ez0qb9T4jsd1uwujuXxyx7+0`OjfF=J9+#pX
z5?MnaPZ%hINjBmbCxQAqrX3xtx?h|`%a5iTWKfV3h=rnTHXZ66G>cN0!7_*KGAW|d
zz*q$+a=ZXV#)06)^S=yq1EHe`o0e${ZX-%`ChS4?J+g}H#M&2=)T-)bqB$^jY-^*h
zUpGAh5Tmm;m~8fyC|zjiKsD@8n_-~J&WOQ=LkP_neb~bD!KX+rtwV0y2!;@&;9>Jy
zIza5hBru4bxlrQZ(K-wEf<oI9jL2)bq0@4(!HM>I{5NhJjun}D1T>{*c;jQDjWS|G
zh>#MswPgo3eoqv3iPAGM@0b;24wDU*<OCod@ot%Ba%Ryt<<U$wo0{@sUWg9OA^|{b
zA~jL$ZwomoxI~8;LX!swSnwYB>l9$&{X`+`lsJ*(m{|Y;(_#`}Gms4T)ox?@(Yuo?
zAYS3|h&IA$KnMh*gG1qo#p+q`s<6bc0_f)%-2pn3nWGg7=@Mh$)7QWbJDaNkF;^|;
z1D~ZT9QAxr-(MTBnf`nlkO6hq{veBC<@p==p_2D436YqAK!h$?-jE2+bc2@Y&x)Q+
z*D8a1I~ZsO$x|e}45Ee0RiTar6}D8Tt=nx7d|!GLR-srQ9EAj0^l^0hS!QRZvk3gt
zPugH<rCJHkkGzxP@+gVe0N^~A<n4L>=sYF`jFT-F5V1#y2mv1i_ONB56P^dv(x_Mk
zpr@wLfo@ejty!5FfEa+&W=OOlfg7?3`ekkkMj$tK#j_xdm_P(!ZVt&iCg)n;oAxSV
z%7n8@O|{Q|`kgI^E0Q2Cu`IVkj+=;kU|R$j;*bsTIDwcqm|?Qlv2d%JFazE(C#*ge
zuS2w18q=}0D4$f>(JT|aWf_TY!<s~+p&J&0{TnOq09i;0Hk78WcUr7#mXW7#;%U&Z
zBbW1;1dPBPWY5zR?86uXm6Za326eVUC0QLFFVLmMpK-?kR2p)Z8At^#0RzjVzxw{3
zT8c+t#o+{EYDf}I2XsDQig^mx%C>}qFi1K8ib!*GLSO}qIk^<cn!NZyRS3BV+ygd-
z9u&ZsN{YAN_`M!!EV{`ycN=Nia35d7aD)SOg&_zB0x@E{SQU5}dCJTaQxM8iX}HaI
znFho=p9`xN{xU;%H~A!0S%*J=3w1i8hHo{*2qruc<Bctf{>z@_Sq4fq@|)~Tp1Hib
zicFC7ye0E1Ppa^nT)}=9E?1R55vD<GgiNN34rRCOocVwMXbd)jjW`xd%tk=CICCqZ
zFLJA$OovGZOB$>V2Fy@sep%FmSPz~97V(Kt<f+NSTR=jfsdTeNJCL&j*wLY#mLu$U
z-nah!4rbvjGa@nUbc);1#I2U$B7PSjQ>r|08`K(uUvsZ~NuMq36$Ne$|As??XeH0o
z+?*iL+G)X|2oYiuILGuWx6rs)_B=S*dNM)8uJRC}f0>+E9?z!|xktBzP0R1>21t^(
zd=}Vjblxy}b_#D~a^>sFxBfSa=4+{_1)~?xo36|Kv<1TrX%(m(8nxKoG-Obc*$F&U
zc9Se9G{EHXNzx$8!c#1E1RI&CR`^f|gbt|q?&mFwhr|{UqjZc$xsEh8BI~%jWgu?m
zhmFJ}@(WMrR|_YD(7qJ|#Rz!EoCV4-cS$Eow(Kj|5oi`|z-tjg(QE3hUtl3>Dfyc;
zL!7EK&1N+=Vgy$y)GUmgfkGaFWYI2PE#3!D$!OTJJS=&NjFy$)SJ}mJh2MC;(S7fq
z*K#=~2sMEn&!-}^iOCf*;MSJho?HsfCoDvR@%mB*)>wnbgaJTwNCB>tamgDmVG}WY
zL4=%Dt*{7TpxZsK-~Nu_kct<Fa<N%i5rH9E3vPr>uw)iyjvw$}QMo4#`Im?#M#^=J
zh^2@P;tFXZV?rST?L*hVmO(aJNE_nPLtu5_RtS@0?X=SPQowrJN&`@Oz$c_PJ<{nQ
z9c<M0Szzr>yKp+RzkKb{e{bdYn9=dLK{1GYj^t!lYQrM4?GB=A9z@9mq8}|I!kBWu
ziwH|+s>nJd2C5ZR6mTJUR5@rP&`?xrRe$DE`x5e*o{L247ZhjFtH@?)ITi9A7Zj1M
zOR8lrDF5CQp1Ihjg27~)Y72`hv$vz+7O`Kt`tqkQM!Q&@15s2<(jEV?K+l`epf20-
zA|8<-A`a}0C=Pamm=p5j<`)Tdg&sC)C<qajgd{rV#q8o&yfv#ik8|q(SnE6xVPKBj
z=9v$Y;b|o1h+_k+!;30)*SH`Mf7D&(6b499avszDJRU)e5C7@#3|E3|=+w{_EVTYp
z5;PT3_Oo;Z<LrEw2%l+illKud3gTm0m%(pNdvCS+%SS<lFo2D;*AtL9NQ#-x_4h24
zi`&w7O<+{&t()VE^)GM$1U4q-C3bWFwY_Jsgt4)$ms8*;+`A8;|A66Wc)P`0Nwxz=
z=qH>V3X4t4##EOcVACg{fTR@d>S~L7n8S2H$#%xUMg4ZTRlopO0w=K31<u(D)Dc=+
znM8nqQqOdHD~9S;L@ov}*i(R^xS&71crwQneJ}@<60?C507lwyGlD+}T9cLz)5$od
zq1Xb@=*Ku0aAS^1OX8s%>dIpN@|PbVF<amkOwLxDc7&@kW(@o`lZ4%m*<G%s1wx?A
z7Ex3Wau>$9SlW;M@GTESib<g!QzPkvKzGtAs@vldY(l_KS0Yy^^d>BUPz|!51lnSD
z;4>0-B(sB!L8SshnTQ(iYC(K@06UD$_@vp*uxsgy%ry7|Xh{KVO+w5C=>kNkE$Tm6
z5kx~Ou}*WgJ25F1l?5edZV^<Cz!H>gnmXwVSs5822-zh%#lE5|0>D_TI{=#H9e|C^
zFriF_B{N)*r^-SJuCh8k{TGO9TBu0y*j9PVWXZC#ke~6>;WrMY#~N0CXTw?<;e<F~
zDM908RV6=DmLK3o2!>AZKvZg;E`A7pu@=gFT49E{4k{BQ4C$G`YRmwW6<UPkz$Q!d
zyL3&^Oj#4~5X22TGWq22_uj!wKy+`K4u)(elYuhF<^^jK5Q$*|Wy!KISM-!-g~`(c
zW-yryhMp{+d@PJdxc0M}MQIVvNAX|?Sa3ZF9AY(?lhU;#pCu-6tm}a-F%>n#ngYoj
zC+FSr4$U%9b_2*P<^zs0Bl*KvigR@kP3B@$%2BgkbU}oDE+iv!DGLt6C(ANv@`d)Z
zq-!{$8N<+VGI`V0>DSK59;l@u2|97%GjFvrdm|pe(M*d9!);cekRUo2L-8~+tHd9V
zBAIlrd8{tde3Sqy02WbVh<l%La#itdfdK_=Fd$~Qx(@%LXv!2HV4B*KCZ<&_Q9j_i
zVaYa|B$49%zwy@p9#9KU7rs^80f6`DC#x6^s1z!bz%&>(&?q51N!%(Z5kG4nJRnXq
zZ0RJWK!fp+iVCA0dLDWO%0Xg<Ksh0lBkyXa2ffW6It~#9diBr9SVGMYZ?so|oYkDZ
zI~r5%B)4zN8`ANvA4n45es%;9DSU5?0Qv`W`hKdB-+%c{iGe?9Wc)v!82IL%{6mdI
z(#Y}02nhO_*@Zu8<TQazlFvu#&2`D=O9Ftx<Exm`#Eu*BKgWyT_}#a*p{Sd$mawXy
z^-8oM(QZ~%KDh*+b#mqEC(wncPo{SD>nO?p@ayLNjW=C#qxm;|mi%(%pZ!{EZ{$Co
zOGjuA)Rw5C(;S0;h(2F~)g>A)JU7O^LR!K#F&$9@#Y2kn$QAxfI|AIGcXRw*VS&<B
zwh-*itB7;k^ic4{ZdE7<rB;x!?KU53xl*4u*9I<I!**taD3f?5<A9KmbL<==1EDev
z%1ey81wJ7jVCE0AIVDhvwJAgiMMZ>d3LKPZdNP64itth{fMeMjRTp$+sx5jL3a$>W
zedzm)iCSXm851?DKHf1IttIYC$u`*p>w<5#3=@C}h1JMTB0Zrk14WUpixDKuh3^4o
zqwq`FDyVuqfvab1Y;HOa)8qmxe*G)(u6C>IEVTJVUWp$#dH1uvQ8FWiyLI(XybV(P
z<2djlAJyewMx~l=&9=7vaOQipMU|a6r0*J^&JEb>y!ysC{Brwh(^C)l9j7?Er91Mp
z{z_`@%ij5kA9AP%6^5o?b6@m|m+Jd--)~3zqjTn>yD~VO`l4I=VX-u`CC&{UsgHHH
z&)9c24pSE8sQ-+9#XZ*OoZ8?GpQ%i(i)(+pb%%Ywk66FE+1a%-Y_9i?ec3a2kB;6I
z-RkCF8xN<<$-+Nt*7fnF+8^gTFKpQ#8)99D)^qV!Qs<jPHlDKC5S#zZY^8HGejV4p
zJGtZTrj-pZt53wEx8^qJ)B`?@Y3PZ#IUka?JbH}6^3mwqEbr;>*I#R==3HIeb}pvx
zx_%{gXPvqFaMK*w0joUbpZCtbfCcz7uY}<bG05;MZ#j=feUE$gIMEF5=yl!nP7?7o
z6_2LZxy5?vTI{~*Qh&a_?l~*pGz1&!=9ORi(9c@B|FX|M-}{yZ)_Mv$Gf<UaaWNE`
zV5W!?`7AK12hb!2xx-|`Frvm<3;n*rXW&2@pbvZxdx&ia8De0p!?eP?j>(}B>zn)%
zl`_+yn}R~bq2AposYT@xe)8kLAdnz790;33HYC!CJ;#>7eJqAft1c!EL@PEPy<-Eq
zX>3m^-)13?WV0aAS_NE@ju_n`L0{;0Sl+TxDj=GnMbuM)0b%Fj;I8V&cD>_3gc50)
z2)kJB#(0(JH!lgi06(CFuNZ$IM|24T3`tlEfe2)j^{$~rTs&Lnu%5PY>7E~y!<G#W
z3@pSZ6lBf;$fTf_g*j9`NU>9brbsxsHw4#}RAIY9K-WP}KlY1nhc`voawC{AbO0U;
zI2G6uW55Xb50^od8?Od0sAAg*?%FZRm}ga<yikN8fV%>!g+ob*4SHq03wNWFm{-7n
zIM&HT-fi&9Gx>yUVX*|5f@noOyoH7JPZ{&o({E#rXWjG)N(g2glgpEhgoV(g=rp`y
z>5fE@*+y6~xm}h4d7!`i5tbDS{=yveVEv=^Vjgk}*-pec`P|0hh;raueCn1!xyM%1
zziY%1aX%)yG$I-hniSX*OczSySIAP#N!5c_iYO0eNT5qpRx5;&@>~>3?gJQwQ#%9*
z@FCr%10f)Tf4!J+JpqED7+%61`yIm@Sz-ntoR%jEj3R%Bx5~<6_$ME<Y$IZk_bpG5
zZvH4^C$uU6%n}&Tnt1$4oNIyGOc@Hy%>oC7LTz3QFet<=;s8QpMD(6GxiW+;Wy07>
z01zFFHz<yEL`FCZiib-#1i_SNK}33)h&z&B!T2?93mI}?fBb*6+Vq-Jtq?x8>^c+q
z%;k-7AQ6d8wOjO*VM9#}k{gF5u@Yf|x88>Gm`tg4BVv;0Sk{7K9KZnLDd0O(pXqi0
zVe9JJzx;SY4}y~?jY%92m@^Z|<5_!oju%i95mAOfHpWU2Iaxkgj+^TQDk$tg5%3wd
zl*23=V)>jFN!uPXur6evap)21sIUFXe|KY%WHTg-#lp+-2*MH5QVZ)(5ISBNj=(LU
z`*H=XF)%_DQ4^VM8>fK@4C)NTDKc?ZOj<Nxwk$}D+-h0B`3KU*ZOj@|&fR>*#$XYX
zTvSlyM6G6?vDh(`X@@UVU}%adqJ|;AGXuzemXyaZonrPd^0w1S{zzx6*40xTny*nd
zfwVg&j41_gV**9W%S^H9Kp26kB?3;6N`bF%{D3wIUE^vMqL8PffG|7q1_mb-aU`_h
z$pLw1UHiBG-P`<z&=F)0-+_aGCUG$(%6KXRq-BV*#aNgl=?mRR$PSeXo{~HQ-3IFv
z0{2nGp&3Er;K9ju<>4Ji<8V>+>%VkIzzs5sFiUx2V%s1_q;s<82y9~2`5b2#@GZ!x
zZ8Y>vhZ)msPe0p;-r&bc)ET&KGC=uAb~i2aJJ?h0)VJOu^wyAXR-CN6VRy=7<gv*U
zA-v?pQnHFjF$DvXUdW5qPy<<?fM%<q5r*WoPWx0EAO;fZwXXD^4sI2EE1pgPwRLd1
z@FO-J0aI+RY7+2^Fc6o{viQ*?K_2XwsC7tl2AqsgauBc>5OgD~kde|@7{>s6;9~?d
zdEo-+7wRXpbOfUcFB8gJ3E={*RD(suB57)Xg&m~}o2w=Bk{>)`0`@=ed-UMdM?c<j
zi^g7wVoEfa83XT!&ExJQ{J0zOc)DxAV|fJf%7v6rDvbb(xI;Od%+Ktlh(~B=_O>y+
zHu+V&IU=>}l6ZBF5jjKz4|+37b9=JgX$x34Uj;HG%+RN70?q()q*`US-5XMeqB_IT
zEA<z{l`sw~ot`j8usyK<)^+g+C4>mZnieDRKNE~a2UzvL_XQ9a3rHtHLjJu;BT0=h
zusbeajkXf}Z3(zJ)YNh9kya9z?x(*U_K3*3Oj~p6j(`5Pu?EmZ!#n>?DNg39%dW|i
z(RHHSoT~$H_Lt*Tm~I-ZKfY*)FY>@$1h^xwRid}74M}!m68Q8-U25y_4xj=ad$>bt
zSujq(Rj?>AToP|Z0*_M1H6VdSxRu0o5J2O{VgDJ_g*Gq@fZd_cEa(FY$nFtA9I`Jp
zzh6Hg;KRvs+orx3n4EXdvp*-<eFQh%_P9WFY-Rz)uCTfS@(}eyOdF&K`T)QI>5E1N
zQp8vjFik)`2>(ho>;MPx+2PKEf@BE}#lc6ikLa0;V<QQ2VLJ)rr)R10MqMP3!!S0%
zMAs}3VRg|w2rhEZ@4a=bK~62uSc>{#3D%M%!*zj&xj*3a$Sxfv8Ie9ogcN;~c_iOT
zIxX2+0%Z|w#1`k+1i2_!<gpBjC@HWzMn()*L8eUb!~|}W5FJ6|<PVIrLfxn&4u*g$
zf%DQ=KHIhKZ!%NUO=e0SD?N!2T?Qmb@GKr{Tlo{Nz(lA;L_X0Q306KRbM^nT_cl;+
zT-SYPRZo*@kwdb(*qSX(MqpK83>Alzh#Amyn^x9cGc{sE8kqnE$yl3-W*}|?S#kKW
z%CY1<4(oNlF}j6D@F7ZpHnBAT83)IXmjtb~dE%@!O$|aYf&x;O)?7y?B&ay{iPzEq
z{=#On>;3&-&p@O^$x^Ju*|TYa)7{lo@8iDv?z{K@?!C_n-K@}}nFEHvFs^{QECO0c
z5Ya1n?9>X3iWT=AWQNpSjz($w-CY|6t(0IcMPRo4+fH5YP+<VWyt;QmO#w?qrgeNk
z71s`$!aqw399#u4gjG414mha>2wbA;3Q|Ra1)>&5GUD>aLmD55<eZKOR|KmYXR+Yv
zRGH-%Aw>ron@s(R24X7>Rw?)Y3!gRt-IXniHlc1^X+0VmTz-eG*}@PRTYx~zwU4&I
zS{}%7C^*eE!}H{hCmMjI0{d>XB?aLUMx~}um5ma?h(Ju>n{;t21x<~puBk8l&FkjN
z1)1^iqH7`15%$PU=pta30wL8Cp+S=p>g;^lAd`58mU#hVE`CM(cz3smVNQl+qY<8S
z*K=^8a7Xc!(hJL7ipHau4*A4ef9L<cYYiT65iSWoHBU^VfdQnc7JE*CmW+HKRtLLd
zJ87)dIx&qaqnZGo#p-VlSxBPgMdk)Y)X{PspvQ@jd|jx39Hy&oT&9>*Lj2$>ybHnA
zn0N!$CH4gAX!`TNLy|MrIH9?H<)Xt=-n)6y_lkj~Xsz3tP(k0X<M~h!<Oe6N_BDDg
zCl@-{QPARP0uzqRvSyD1>ESAh`XikVUxKhHoGuNH>_dzP0p0W2_%y4aedj-X!zaX#
zKpX7laGMjvH<u;0>7r=2h^hnN#{&5ZpDlMC?=h?WY@A_mKVe`DX}Abmq#{}v$omTS
zY78LsaqP1M=d7AGUv9QBJH76AjSU_aq&t287lvVdFSq}4oU>e>uD>^Tll>OR;FWkh
zm+kADkijR@uV?%E)_!6{8j^VI6@FqHVTz}QsNVZHhv^l?%nq}30qzaG&3^11m*Ou(
zFb7)DpZn4t{%gHpUALR<ehb(8f8(`olE%gh?sG3U-I#B~SF^<XAl>*je4E|;as8LR
z1gw|Y?O~RqT2O@G+bl(;U|$n}E%LGCdNXK<g-;tThBXGP6^Egip!o(3RIY6m0<~fc
z!w&X0{4XyUZ~-+4fB*K8)TEtG32WMn9mo56hCVTWweee=h|}7`CttU{PCXpc1zv!H
zNcoa37})F?11fHZ<)joN1NmQz194hth$h5ZuTZ;TB9WS@ax1Dh>3lNjxYFNI6=^&B
z%7ZZ7*E6_~#!NE<n@eB+lY2hEnTYJZ+bZIcJP)a}2+@LDm@K}>ofy!RGu*BY18vCT
zTjIPN5`_+7TLtKFkx8~9uSko8i3=oXN^}GVmu>q^(LRZ=xTC^K?iqv++N4+P0|Ouc
zq_*r~d5@i~hx2Fc3A~9i*@6Uh`8mbf4xaf7+Me~Wpp0kcuq>qNOZ4QP#wRVYTBF`0
z5njfMvN+NRo)lF(c#1VV%h4yCcY^4M5<&>D7=6nOhJI+5?4*&gX8dVVDcKjFx|ZzM
zSzh03s|~sKP!6l?DrOZ;mYE-sKCPP5<0kThArM(HBlnx_xNihzF2*@Sqve|b7@?WY
zRnXG0*&}}&v<TTT4}xv2?lH*s5?dw=sr+royVBh{8`IO|?tgRDoIl2as0;VnXODKl
z9}L3*z=Li{00c)3_(Ec3ITO@bL1R^}7j40VgXlB70Tcl4ayRjK#{|U$_zMOvwf)sb
zR7-<y{4r$qOh8(;#r7TW76B(6vy}~Xb0em}j&z2_4|iD-w3)PF079l41khdj$uAW#
z)$eT$vh5RW+=m~o10EI_r@iNGt&25J2#8#C3OUpToEQSaZLlaM)Dg<?G;Bm`2u;}E
zF<H?zOC8L-$P7{i@FDd(B~DE+@m3%z{Cf#V>9<Q625{DmZ)~MF3X&S?(HQuLMTFd0
ziYU>*-S&wQEV-RoeW9ESeF2s#aK54PMPpzM2CKrlDf|L?5P~g1eMNEOq;n#U7}$hM
z*a;Ch7BdDrAGXJQWFchti_dT#dB+e!3}npUM!t93FI?sAg?MacVHb~Dej(d}W-bLN
z+H$#!$jVug@G^*eLn-hJE03`dMFBwyEY)u(f<z3KI_#=soPP?(KhSPX6x<xp6y)W+
zJxp%;i4s+N$PI_bP>(ezAzYC$%>M|GO_4{tv6u;7EF%FB1TYIdu%duG@6Z7v3Zn>Y
z!N`xcCRpO&5v2m)D!BZnU#G!2Ohu1~_u?08=KKtExs~^8_hmWaJo8Ab14%?xL%T4x
zMN5`V;i4q-G2{hH_8GjgSi_k-h0jX9*tU!drQ`HL803iMe*E!DUP_DYmrK#{damBk
zW}$~fGnE&i7%~ThLtV9AK?WZ*4P*$@PZ`?#enXSGqX;l4hz1anR}TDMo<Ck+cn7=#
zOG5;boAIEeC<9EjfA;p*K{J60WI;DM-YnI%dcHA*X~nMATFwRoB11A4h?K=hl89t$
zozh}^HHDN2c=~3y(PIQXzUOkZieip<LFWg_N%{t#H0c+CFwXEu>fQZAug@Tfmk(gi
zE+CUrr-W<lYQevZG7pO#VKBPfLFPFi38*7vGXU)*aoB*^1ZqNlkD=h-3Xla2B^<I-
zBFsu9PWg9#-_@9T(-RpbBS`BNqSF~cLww)PcshJnn0Y%*R&KJn#SP3`M%1k}5DAYu
z18i$js-a%0Xm&wkk)~idI5KfoY(iI~*|elV1AP-4dETGB_lBw_<QhXZmglWUgca{<
z;Zw>o(=2bV=k&`hQ4ELpk}<BLh^?mEDH%$tKSk1(W(gm2#of$Q#~TTu632d&kP4r6
z_V4+}id3wQ691#8pjf7Ny%5AWUg}v9Myr^XV_4@%x)MiEYk6j5;XTZ9S_o#!vd@&m
zdkL0shYNTp189=o!I(>j|GOImyCW+gpeA{96n<t>sq<lzUeX(EP-LFeV^%1tH`GN#
zO^W9whwA{kfc_mvAd1MMH7z#u5_Fk}@X|IdG)2(mdBt)H@4R&GkD6sbw|a=X7cQVe
zqqPuYSx6sPw(2cI<A_CBYO>rSB^96_-p3qJN&E)L;M6ot0S`VIurT6)OlRRLW*Z~N
z7^Gg5jQq?)5OnOr>~h@OvcTCHTleK7^+WaL57j>$65!B*ZGuDf{4QhivB}-7%r4Z*
zi`k%u+N9MQo!YP-07+#aJYn@LI~ifpc~mJCMR_}eaPCc~Q>TfTO*s3w^Zqv22xlN4
z4Y#l$Jk1g?o*Ya2EX)Y*u@)h9;5~!1b0VH0VPj*a6Pxz0gxrC)bubQQ#_{QX*|c}0
z5C1>c%!T&o#Lnq(Zg<P9u~jmdKVHAfNVhnUnY+wft=^DF_wH6OHgVq|2<9FP>!jb;
zK{;a$X*Tjs>-hAN6oSMLpG{{-q4lzvNpaC6S?bFMeFh&rR<wgbXO@FVm-sL>-RQ(i
zo$aaFhFk9p`qOlS)4Y|6>u3Wf_|DUeKSw6AnUKogKj?ing<f&(sqiE|Z@0bkb(=Z#
z@jR$OWENExTvn>(I^Q;tsfp2WY>#y=WuESEK+~%cD`H=qI~aMk{B#@3^c9ye3f;h(
zFpiyLn6r2;rS49AH|_{iI<t8bM$eS{_I@rgJ~qXFp$0ep_L2G;spa!Y|I8@)TjpjB
zslm65AIRrF9eg^hmB$GbTs~`q`FmU2L((&0vy!TcEY*O%atb>PgcTAj7<@m_#r8)m
zDYw8MP9+C#l+PDt=ba>luiSYe0hBs1jcd(A;nZWvE$=pV>g0~k5ra52f_4T*M$ir1
z6t2v4cALdoYL$aNm`!hakR|A|t+S8aIk&f);zPzklwb+tm%1O^rL0rlt_7^?y*bMZ
zhVz-S{NR99Kmm3y%#Vh5XLR8Lg1|<xunnyEm6{+B?jZXRR}L7U48_<be3&Y&Op|5^
z6o@Xcr3b(fB`*_n2=c?+I*j5*Z@7;Fy*s}G$S=hL%;8RQP$@qY_`~bhKl0<8F$X59
zgOUMyJn+vwc@Snphzeh`iQL2A4Bxjhzaz|c18(6}C1)KriJtHJQz*fpkbpZl&*8OG
z1*5eo{%ll@+P5Mo??%$R0tej#3UqQB`J*J?gjo6};`Acr!dIFu*QC(<+Ss-8lPu<P
zkJ^=Ea61@lE!rT|T0tK596!MUzdJw%k_i@K{|xv*a1nSzQHqjxtDD}`%PfXo+NjEd
zjr+Mq>xrQRK5_K96DhW`LwVnum4;9hfpD%ZP5<E!UPTUkvWb-OXc}i%f~;Ht=L1ao
z5J+Gir$V$MV5{f47fDG-gDlix%nP6+Cb9b;Y?P_&Cx?Xjv?0D?Imi8U3JeSgED;8w
zccsxn=xVP5q>|OZ!b0p338{LthRy=XIhEUA|DzwlvduY1d~c2@2b=M-%%eesAnJIu
zowYItMbsx4Ob5>#FczqB124i=$~oRm5xFMUI7Ot^Qtu`B20am&B}rfs0UyyNq#+@L
zslo~Q!E+<#0$ry-IEQYF8aeOrUjZ#9V_*~3aZYU{oOTq_V4NV~8jIS24E_ok%LvNw
zPgo-et)RPfCX9j#M|{AVAj8yU3XulH6?Wp^Fz68Kz(2eI2Z>2#sxgiXHJxM?dm_G`
z#Zml18=5C#QAGfdK%Q~5WEQNu2N*6Ue*&1##r8p10a+eiU$8dosTS!w{iYFcX$^j5
z9x0-@3J<dt2st<hqEu&ic6D#r$0I4iM%XZ1<^13N)o}{x(;W5=%HV{{Pjl8;5T3#B
zi<H3x0E&v9UCZDOU@lf+b8{J8YfE^pf?kHggYza!;R&6z!Jbfde4mz6;3K$)-CPW=
z0*rCS)L$|fyw={ljpcQQ_6u+|1@rL5FJC=2ii#kdN`7Y}=m|&Oj@61l2Z_rh$0y3<
z3n*$@QJY9IL!37)L}#P3RU|V&6<e(URmHxJgR;<;&CQd}3GI2NtMcFLc8_~dK<X%{
z$m=8fP}CBf+fo);>@6va>;LYbe&=A-YvqIg)(8=<X$~Q}lE~^x3aVFzBfiCDpd$0s
z)VIk%wFxtQLnPrd-+(f01U3H8bN|4>O#hy|_LJK#lgElYS+54GUe%P%Qr_1GF#9K8
z+w?$tWh~+2AHO<p4s&h5AKF-d#Y@_idr7I<{KdUnaV$)P;wx=RFYF%%0nS2vE*=_Q
z`;Pvq@Na%?77Oh7v%hu3R?B1ivpmCddu%Q2$4e&2ltuyBQm)qPX9@kOVAC#;XVlEe
zTMXZoKpqtU1X4LL+hGgkGze#^Xq*X(-(q`}r&v`DhGB2e=(7a{UNSj@<<*@*XTt+T
zwlh41a%oxSnknE0o65NH$F-aO_UmA9LfL?AiWqa4S#%alqFT@8%fLP;xWEFtCo(28
zsMG9H!4mCK38piGMT%L4yunVRoj~y=lVD&M1Q6y8wntM^Jw2J4tuwgln<b_<t#Ilq
z21DB6=%|se{pmGXwQR=9W>@R8_!mr1RIP7!`Z=PE{>lbcaHI!>Q|y2sLYah>U?iYW
zX`Ms&#J1@G;~;HZI+B7k;Sda=fd)-T4#pKXrr5X4I=VsMuzMRO`opQ;#Tdr+t%r|H
z5N0tsT_^EM#-=MOCEZlb*aNg$NzT~k##ygeYGWo~_;M#=hqkcOjAcbI1W)kPI1vuv
z_J$=23Xp&R1dda6_;!KsMU_nd2F+4v2&PG=J!p8v$#|@Ly8F7^3mU{&=ar0&Uu&`h
z8TqTRCJJc0%OZlq3~&;wYZ80|iJPGPwg4HLm6-(5gByTlpOy|04#AQD5JxiUBOq(e
zKx!ldPGlimf=2e)bx&xj_R?nxh5_G<ZI>VZNel}1B1;@ILoO;?3vUl;#9aKmo#tRf
zcoz4-+9)0XyDeMRz1=qBgh*(D9aI7!pl!fN3{8><`x>V~u!0!3XXYxvKE2>LmIAP6
zk9&?1Wr%0NYGYeCd5q{-T#EqY@c*4@z>GT}K=d)p<_L!yJS#u*cdp9OL&qk-Pe9Aq
z$iRjG>pPG!2stJa^9Zk*08;@oIl>uCmH|^-L5;oGXu9>|K^@ShOPDUnZG1y(!x?C0
zrea(+N-`eD(vfHuC#E#zSWQw+O_5sUD7^cXc6>T)Gv69y%jzVx{hf|a<}#u)lOK8m
zTnF63d?`Q>Fe4cp=qfiA5iDl4Dttr^Nu2?roaYBm6nOv1YX;IKiIYH}A~05paR<)=
z;OZtY1n?a;Gk_*MGk+~Yrdh}QaO-X1pF_a`P*D|TzJjkAAS1y-3Xa7!ThTmyzY~+e
zU)C^K27DirR!Tq)w-Q#vS%p+fJaroE$H|M-+B0~QVSB!0PR1T~5cQ7`WfPlAKYLdd
zp2P!*X%^LTU>Vx)E%;$7P=t>(Wy1-GQTNd^Y%d07D3B6R1nr6^<)%Rx;8ue^O}(hH
zg}_E<`!b1WVU>Ib9y-(me?lI5qOHp|U!Gjb!Y2GUx|m71UMu|Oo|ZjQA7lB?m=8*$
z4rL&-XIEl$1XP2ezlih?rf|w{aS05F8xxONcq(qPOD3d8ROjjScl5ov9{bEKN^4qB
zHZUx4Het$m;Bg3q^5R>jBJ_r(_{0ZL1uZauJ_W7DQv#`)0&E?O*=@EQYe0k<CVHwg
z|12%2VqU`8dtq@SP?>5@zzu%naY)5(3(5(na_sb%@l%uw%9^^AXE1SfPm7LQI%>Jq
zbf6xeF;juif=UN}K|HMBfyMTCi7tU$gQX#w6&(v!C_n)o;g|`kX?91P?=mOB-aRqm
zWsC^yN+0@u^L8ML0)Guv%*5s|8!U8Kn-?Myb2%OXgv2d}lp~Nh;d&qGqL>&4GH%bN
ziM*fXre$!0NurqJSH*jc24m2<bgb26rEZoD3NOor&q$7fWbpxELJ2;@X&^0(&sI70
zi)zEV;eX=S*^>}yX-&bpUE{Rk5{F2pEL{vP6kv%eMI+AJ=<)qmM{an)>e2Bz@*&0q
z5uk)h-E7n&Iu2#PSHzTx?!yg)Wdi=7Vl+Zlw}f;lL=Ytz@`B>gnR(n8i;}_0>@`{6
zxC{@3-amK*rx}i7CM^l}1avf+37*9f8+O(ajzM*zl7aldoLq7=)}u;jW+ES6SZo(1
z7&9=W7DFsROii(ws3hhpv_TVT9|iX>PBN%o{>14>s)3i&Ag<<KCbUVIH|KR!bL%>-
zg+$5;>lS~QmnJdDUW$KzM<CQ##o%&FYdEkqW*1ezX#WVr9pT!U#VuU3yH^56C^`nq
zbp6Z!R<69BC&sj<K;S@AZ;>w3hi5akUR0sJDYcXrJdv8Vj~V1v=)}XCf|77Aor>r-
zcf-~O`44#!0ST^?30S*?XY|l-jDBLW_DCJHbG~)2J&+9s;o4egcP<SM)dvT%&mIkd
zuh^ogJ~DA23+8~i#~Kr3YxViP*4~9k6g0$2(F4tA=N~Yb^|c$b++e?wu|3&BTxAj*
zjC=2I_hQaQ1R9!2Nf!51SW4Kn=(h(XgnE?Bh-rwrj=OzN^0AkIkdd7bsIvqd2BM{P
zoa~7wViwqwaSvg)?ea%{5IySliMvcTAO&H4;Ef$ewa6Zsn5&U;{X^keeSlz{t_ROf
zPt372S#@Z4%MLoz6CIE^1dlwuV%jx4=BSC&ho8_6i}M!HHTWBew%FN>KZeUK&6-JV
zr?aE6#jQ~|b+t>lMW1aTCiHV>iAAeN_~w=rCw?LZ2)TYbWdjc73~ps&nK%9HOIcW^
zb#=U|9Dwy2e@wA77!*rc_UDC2I+#ixQN_Ntc`ZC^X$V>Y;|?PnizE=5C16Z;61Ht}
zV0eomWGC!C2~W^{47K}jEAO(x8uGv#3Nv6J@T{Y0Hvd@d@QDW($P3@weU2~B^zgIV
zy>_P3c|PC0<{cjR!SY#7!U*1w;*y0@vO7Isp9uDJt@lh9*Z43Z_mX9r-wBXF++-Ec
zt)mT--kJS$D}8e2PaRq`e!7p3RZJSAtvD-VLO$2^@4T3%I9c`I4G{9!?9{PY3kb5q
zQY5IwN%CaPV4hz(`ZJ`=Caf`UR=`8%>yMEv``o<6W2l9Sb>?1x5Pzk1SBBv~4FG4h
z)U#dPDt!Vcko7xs8)DjFm}A+ed`~3{<$sk-k&Sc(YXW2lJ(_$;OhTr;{Bt-35IxbZ
z+$iTKV1TI+Bj+9(<`n@UXXB@Jvfy}DM+;}6X+Bn~?#Y$)3iRyED8LX~02Afl?kp=m
zXLrjPt2OB}!yT06+X#Ovn#?MO7C^DkPLZGpP6YH+EOZdG2ebzD2ERW+Rrm}EUP@WL
z<$WXwz@znGXy6Jg2lsSU&TrrLTuu%wNJZ``=rNx^hNsSaIbiHNZh*<F6`ih&IxHiZ
z9DTYOft+f%TybC#`LU^Sh6OQIf;5z0GM6EBz|4?^oOIVcc_U6UsSXoNR5hr{N<xo3
zJJohwTQuA=!)169<tSMJPyO*9WGvM(px(!*ArCnR5|~TwU-07@2pH3hGxzpaYCEy5
z7HHer{G=livW|9X+-MIOyP`{|C`1DSCQT`&d(@r_(~|&>jF8KaEfjDXLqbf1EM28>
zySfF44qP@8;U~sm@SOMKFKjf*?h=DRE^!rYlKh(=#f}Qk4}5RVFF1Mt*0M1w6MQ1<
zPi{~Eqv<%nE1U$n7fq+i=7iyde;(2~LJ?&lYRK~lU&0PvW@N15S(|V-5Ark{ru2?H
z=YMoP*xwT&x!ubwiPmP^C;GruKs57Z^hFS@BlR2|64xmB35Az&(TfeEQuI)G3J{e2
z4wPF(4KrMvap9sX#XydA(K```8=14j=}<z0OHtnX|MZi)))*pHMkHl5+)L0h=)3n8
zk}sCMb98sU%n9l^sbL?MNoIFqS`&*<$_vI9oFi%|W3OM3SgI+7z4}zLtwiq^(l(sJ
z1#-$mlI4~`5nx&zpCu<&_hij1!1LNQWk#fTpSb3owS3WRnaEee9O0AW#RbBosLb3W
zq!WDv7m`$t0UqvAEPkZmV(x_FgMKu?wMuU5$`^whno?H59u<5&NwR^L6`BwZUYJra
z3a8j$>8^%H_OanrBHdM50y;p6NoEk5KW9jc^#HORWr27QGfQ+koc+k#hhgptog52C
z7YA9fyM?7L(f?|MYwWCLp#Y&mVh{fp#FersUpu~U3U`8%%Z0`6*OHOHy@&3kq+$DX
zvyyPJzzgDnleh%+{_z*xsfi#$Uq3bRSHCSD^ve8HN{&8+rg;C4$&|I>jP;jN$do$-
z@}Hdn)=D?eZ`?dE@ro<f>^q)(?{#g>2u)JyRE4I=clXk+K3+Q;51s$z8(#bIY<PK7
zF@4ROhOKzTPxpW9`fj*50NBD*!}tt?ohBQNjM;4$e9!@O_^}YJIPjM9at10uPlN&y
z(}arI!wO{|U7PFpyMr^KqN6>bII^F)5=SKj(@Byx`J_QA^+(W!PQ>i*z7<rg`!OU9
zj`v^+-Oi&i%5(41;V*hs+-`Q(7Fw+`mN+q&h>mbqOW+Bw$VX`v0bOcZ%p6jgl5_&&
z21hIE>dc-MQikyqyR5TbZ{!ZeMfTaAW;O$D(0*VH>^(~(NPEs^bWgz3_Vl@vuaEpW
z%0^ei;UGu14zjhJO<xCqWSojLfg_HWV+vq7$#$%;#U#5KX~&i{wmLIeNBemklM0<c
zwgX^mRP(64uiYzgw_u}L98sjI(xs$05wI8>Nzb3Zj)vdplR-Qj1ymj-Fvpl0IGVC!
z0p3A|Id<wX?fR}x<&4r;P#K;K2cZB914&?GhJ_dd;z7_Q#@q2R+)ieQic<RFNWK|(
z%o$<{gk&LdutcB64JL&;Q_p|3GytDMeZ)MD&}y+8#>&;v2kQ9KU_y@FYJB?5-g9+S
z)*F#v?23bKa=S~}O|Va@U>2DH$@Uc31?`{{$a(}<U^m(WT_oS7DRBb30R^J@ry$W0
z6t&gVd*IAfSO9mKH=0^&A>Z4=uHDIQu}rgPvC3=#`RuaAAS7F2Yk$VbD5^pRh;p15
z<R(V}Y-Ksbf8}^u02j1SH>n^<0pU6Ww*Se;g~ov74-?GH6ea~+LH70#gT2|xjB)_>
zPNyi;QT#FiaP61hML;LS$TQm<Ewa&&9s2TIZ8S6IeB9OGzec@aD<L~OX#j#473^&Y
zf@*G-V5Gi@V~`T?1+a*oKYk2^gy!NU=VRHBdv}CfUSbB5j3-NmZDaD}c9nJr!y8XJ
zuvR7wmapF<azV#F5%h8CLw^-qfl)A;6itpo@G_`_x0U>J3KSG$gxhhNrtZMFWHHr&
zYNX$b0OtU3KE{y2riAFos|gbqMoZhX-4QS*APD?Fz;&25j=g_f8%$xq$*z>N%pMYu
zU5b6rC(t9doov3~?_}H~#sd~9OgxR{Na7@1tz<hYz6Z690i-|&<=T!9NH&nNLE9o<
zx{2B9a_nK_MJRQpWHo*9jvESJk;WP9ZRiY6Ul`lc4d@p9BlrSd)NhnThzsh41OY1=
z)6Ygg@sy2mL`E4VqTIzi{IJkX)HR+@n8t)?mOgXyNU)0cVdilYhZrE?%EU_H-*T3#
zv>?d!B#E8@v_VeP6$g?rqt%Q=%>Y6f36)&k3Rf!NRO>$B>xFxuygoE(kf`YWc4qwx
z2fVh)<yVyN#Gx~&PR72l%Iy;wAevvTBX5yI-Wqngp?@sJ>bsT_(b4k?*c4SZ2Km5A
zf>IF!#M{DlDdJSZsIB;Mv)GQ9?g<hNIA=F5Z9nun2G27&Vp`^Y6W2?!n82h_R?cZR
z3x8f+C=2Q!m`w_jF)`6kGsSEgw@Y-EMsr?gg&7TU1@VEM=`hld;Cb+8jWzTV53p@#
z!E6a?iu_L<Dm78nATs^P@Klmi^E$p|eEHWb8zCV4%BTZxB6bixz*TsERib#G;d(+I
zy8<^PylF5#;2ts_0;WJdjAWR$t;pJbiC;}rDoSSkL-WE_Xfga7=2^Jln`S-<r(~53
z#H_qJvC~JVW89fLtCA;FZXxbakio~`qqyj*$;?K?5jzxYAn0fCu|(@Kd$+WM=K}9d
z|0iSy=gtkALa3W;M;ms0Rwt^X;&WKhsR9(EIfukz9CaUS36Oq(%8A5>x?o}vk(kYN
zs~ItXO7t*7C;-(75@yw7Mk3-Eoh12*>(Nv5++-euhp6^oP0bM@S)NoyDprmvhL@uS
zA)UMr=?)?ZK$E_b>y6um%6VQxJ&zEPfXC`HtE@Gw*|6WX%KCc_t+)#E9DTP;2pRA$
z^o1|Uhk$comT^pO#Q?s_b5FZ0H0CVg5R<$p&5XD431-&=3xicP18W7}B;`3U227<S
zGje03^?bvXm*{D9Oc^fq&-^G1s!3=f5Jwt@%*wSINkfr{+ttD;2|B7qnvFO~MuI9y
z%@On+IMt|3eh_m5e?pL=WZA@GX061gDbSj$3~7Nmw*EIJSHf(pHL-w(o!><i2Kl!P
zcH&tMw12MkVEs5d+ou1#HAg4%pcvGtdzZ}y`5J-8E_Jz<XA*FcbzNDyP=eUyN7T=8
z)N+EL@9jVZIvbM9d|P)%cra!~Y?zfe1=SgE2d83Szs5EK>hMCGOLsuo#?%F7+Dr&u
zY3xjYq!+*3_R~hAc)vLq*I)eP4T~l)JC%-$O}H;w6uE`ziG2Bst?WZ#{oWR<C4OOG
z1ZVNd%GjFA*@oEDS`)lB#&!f+R|jE<Fj8<L`6xOG=-SNK@dloTN%Aoqsis5D!?~k!
zgf(=op?G#OiliMwW2X@Jog|*)wCY9!2mC$*i|^J2()Dp#VT$F`W51=h1CXs<x+DDx
zKI{JZFI_u+1*n?9P<bu1%6!j&s+a(^VOFky5R?uMTF&iC`}iBKS%R|eq#48e98h(b
zv$6fZ5`VCb2FIsh`Gx*&FoD|5I9`Dm92$Q{o>zOiXBNuueB&|^e$SuVeO3muCDqcz
z#QdaU{BqJi?H*=yH_`5t=)Fw&pPuRQz;-|rrTOYU*|>xV#o7Ag4rK(>F?q?<J*N)X
z^ydGDgvqBLshzb`09(j~l^w)WZRN~DA0Q!AzV_$4BP%<$1f9tzgI{oos_p_aOAJ`Z
z)-1h5?53aI)O+2yoOFhfRDEzYu!I5w5sWFc^YyY|k=^GIlDg?!Ruu?C09F7-PBL)s
z0G=$sJjDg$%QcAH|M(e$JN;n;t_7hXW0?GUa0>%j!J2ojTVyT2r_1Is_XR4x>)nZ$
zO+rsWxH!78yAt=o1a^Sh{I`rl^40e!RoMI}Zawn*V#633hXcT(<|K**pb%^4mOA*-
z0>`g)GdZ#Vig+~EC2_)UuS)?yK4@HrJCF;1q-2~R#9AjyPsYUU6*q>ElbUyslcI#w
zw1x7)^9L*eX+=(Xjw1vb>HA5dNI^P_N4%f@*~_mV2gd@b1ov2hdYpIA!hp{mDPacr
zgnV8OqT&369Ftz6u@sMMjB@YOFepeTqpg0z)q_YwfqguNT?Ab85Kgr4K{88Yl#&Wz
z=}ob!Ae{;8NT45W34{zj4bRZ3sS@Fq@uiPE=w<L`1~irDIDq9DgaH5qxrwwPL(!)v
z1g-&}ynxEOx0|aq#pw`VDWF6-l_^V`Be=qxzoLa3Y>$XclL*;s--uTWDCs?2xyOz3
zjUB5gfa(Ipc`GrjCqXWp-xBUjpj|8)p?Cj#M#p`z8%U#(wvq|Lf@qMO3c*3x!g*$p
zu|DF8h6_3CAPcYHzP_(Df&Bx-K14;qfzgr~<|*J7t2!{17hyIc&n;^~lt4P5K8>pa
z#Dv`h-W{o*Jp9E`R;YI&>E_D?gb8e(DFs-NF=o_?<i=m>h=vlNY=f05(4JX9Gih~t
zFlG)I$iXUzvW#&9Q?W#i<Fy5qV$4PcifB9%+Tn1=+_-bZ>U;y|w-pwbc7A%%%$NHt
zxvV_(@wpb95*(Rjmu#FwR_N?3xuj>{_#v{Hj?XC{nRCfnwV-1W-_aOZS;=HhdydS~
zD!id+?$kalXXt#1L!0pQg4ORF0g2MwLNUcJEP4FVtE!`_o7!{Is8iJ=Z)ZQU7ywvh
zQ8o&<4rl{;*wM;ol~aXiK`9AGxFTOk5HsB6W=RevH}2=zM^bOi0q`r-wg8~3NIpip
zq!h^sD`DHd9aNfEeS$=R^a(gRSl)xPnG^0VNjs{+Sz91%Jv-cf08q;WG0nMMgX6Pk
zG@;VGYYQRSM-&qXw0yCa<ckF`MOfgrS?w;Y;t@zWGTBg^6j)entqEMCjfPxd97L56
zn#doS36{j}H+^uFd|;o>hM|KxKo8LB&xzM#)p+5~PYdMff9*;-u>XZ3E)Gxdd#xl~
z-xT!snuVwx|G5j{WJ0?0M_(eJJ0}y~^Vc`?x_{pge7olzm%jg(BDfA7=g*ZFO!!^B
zkO44^g_Tm1U3~KoY(5MJzN*~K>%;fxn`)6N`;D(p{qEH}!^r{e1QoUiO$O>yBZNW#
zHHpS6M-&~ifaz;d_mz1ZFB5D7EF&~MCWh>llwcA}1{CokPKfTppt0<AV@)KS(=?N&
zhLoSOGD_^xkvJT~fSH$gA#NGzO#GP#uNliL9e*JMt*NllFQWh%Kw@f8A=GkTnqyv>
z$C$_N1?XXZ0R}O@=whQ+T5QYE@Z^7lv0fkmwd)&cJ!0b&aWW&P6U+WP%09M$vfN<{
znJT9L-nZ!7LKJ}oY!~`LjvOp-Omk}BKt!^jM}9U>@+Hk9%&-$N=AabcPTP#2%cp_|
zxR<2`t5uev{2S1EO994{pU@0!Ezr7zNvSj@saL)HIm8Bq2#i8LV1`JH68yo&aWS1b
z0|phTRIrbYBaaaz1xdIET^)b%cw=BGUuFqKppU194-AOFtrR2g(r?^EL1jW9z=|*|
zAv%%^6N%g0E0+PprQ!dSuE*Uk_|ZX<;dS?1<f}3Clb4L{hi`p-v#c-Rm53^>HT+``
z=|H3o@B*~}73ljwgWLnfu-;W9VM?mk85RX09sCqg9ab?uNb2&i8GuaT`rcpW*J>G)
zvDpRwF*w4(c-E*>u@8jkg3%aJies>`s|r6tQBa|-FRYCG!Z4|+umoo@CHx{}OZ|22
zjuVy*&!+ch*Yi`8+B~nom{rOn-Ba)@FLgpYi>@>t-nhK^lNeAf1HfbLCBRB$^Ge+S
zy?BZMEnbDc@z^RY<%yim<v1O2tH={Fx1g}|Pf-WB1JH->tlBD{w+3%~q<m^=L?c{d
zd4+80O$SRGb+RV7mP7B1Rsd?Gs@%Qc5UpSgD@DKo6mI#%izSN6ffP4NaTobRZHIqU
zepcU`*ZPm{{@xU%Qb?rsJuB?LHtf44<$vK6gVCK=yml2g9PjBN?A$aZDQJ8_`O`dO
z{(R@RUflgt-z}lO_5J_<Vc<z8w4emK!ndZ!xB4Y{#SiO$cZzk*ld+?#45(g+(yWL}
zNMOcub$HP&IYZIy?m>E6K13x<Dy@<%<t)w$@ps~#Jq(cRe|WtsvPrzhrr3;N51!&#
z!F`(@;e)G8>%#D*`?U6WSDK4OrLV#Hdqy&zE@y6?1#ELP;JcNCcEzx4=mjLf-;GYW
z?;CB_<sy-5o^&VI1N8wN>HcT0rB++r)5_naKCy`G)RD8<SlKH;6e&(o!;<fA1w*%@
z0+aznKIJ$UUG({sb(R%@m34&(j93wnc-XOGkrTU;SoT{=c!06h1%{gvdK@L$<!3(1
zT3pofI<0P&^MMrxYF6up16Nx0G%FK5Quu?l0mvaaKcPR!o=!ZVYLq2^M)<x#fn@pj
zfiRDSUZaq*cw>cxbrBkYWf!1Cju*5}<<{@`Ae(F%EVbF!Na)G>=>`g-#{bqDM^ke=
zuM*<-cU#m)Q{CHIgBc>FsF>f|T1L;6cQ`SqU6hjoqpQRQpf)=CW)@#3y6p9F3kPzR
z(}uxEj{{vmJ7V0Bxr)94^qQ{Hqy`l4#ch-a_U5XWfAO!PViLL4A}V`1Z`BFUIa<eM
ztb!N6SH&j{uB?W*>=8E)VxIa%4P20beS9!i!|fd1h3U<(G*3~1+|StZc$yt#qBwOf
zCH|GeCIKblN-!cLvH=YVq-KvM!G$@E2I<2;cLS{!#zDvsO@JAe^WhecfqT$E^NIza
z756Ys9=jr-oPdhH_zhlVSm9O>UP!|UI5>btZ1aeL+4Nz578eg`bzFh<Zu@K3pgU;i
zBb(Q>&@;TGScr7P%!JG>kYU{a=`8!h963t!ydDD*Qz^<zNG^#AANY^i8x3Ux*9!oE
z5(hBzKfm7n`1QD)P=OlQ%yV!IE4aGwcS6bi8PdQ_VP+D#&_+uD;~6i`6GubkL41_8
zjZ&1{90U>OI1<fiDX>yk;jGl&{cln8QM1`A$}Nb0kh4*3W7JZP4>j^a=Gf$%zEY8i
z{q0he83%gbPWH74y*8++xGmw9n?|$j0g|_r(i2qOqBP}ez7<E6u7i2dFKuHZgb@SS
zp7PiK%16Dq*W(N90$j9XOkL1&Y!Y+E&?fQ-ROaz(bxI=irB85^&JvyREVGnb=nS(O
z2p`jn4La!UVUw7|ggy3XHH_>7faMtW2ufaae_-x^^jZdyathyO`2cSlu=r}d%XsKO
z={)tl0jfLCX@f4{BfKT{1=mlCfO9I2Y12%{Dl=aEeo6)s))J<T3=C$rL2#tF=5Pm%
z#IgL1-eM+_@q#^o0I{_AjvF#g&q%0x-t{>Omn}ce5>v`c%0cbsUc>0IIl_E_9NWW}
z+8H4@6>QDK;3`~6pdH&OPRq91lE<uoeZIzKJ?v4=**VBv?iUsUlBC26FNeZ57(mK?
zEk{5RfFvUE!jeO7@&SQIImk@qRAq#DnBeNdmu1IhAFP<_C*&pshI75!&Okk}c{ML9
znjZ@@Qx`J+(!H`L18dlS)Nl71e)CK;aG!!?hQ^n$9;_{rt)*2uRbu#qal(g)PGL($
zdl`5CAJ=#u=Y?oLh0X6KRD?0f>;=);DT{EjtCtIL1@Td`6R?7a)`^mKQtFY_tewO@
zZGpmg+ZimVsKowq2NFl382p~HDq(Tq&c-yseL1}R*2g_Ow&-0(M_fH1ZtNyv9yiN7
z{R}aIw>5&^I1^8f6&+YtQb{k$W5)%_13VC<ZvU<aB_p+ibxnMTs3>Y_Ou`TXi<0`o
z4`0h_M)Bn8sF<9hG9(ET8N>_hjmyj_ZMK>YUDRjZX}ma<(M>vxqszkTv7E@2LoU@G
zQa^37AF4@Hv@xUN5f2G2o_+BJf2{mj;D@!0;docL^C(+X)1-qT(2M<^pfjk0^FC*@
zx7G1h2sy0fR<g&CV_<9zp@I*EmP)Ku7lu!`Bt~d}Lj-=GGvT(UQd3H{r5vJb-ATTk
zlQF@ZY~1yZv2Dfn)K}VrM$|Sj2cb2R{;~8(qranp&ohIZ;_fiR25xdk+QH4FcQOvr
z#ta_L{_@4-pRa^D-ppA&oY<c&f6>aJ`u2%A<+B;oaYxE_#-u9s$65;u=jw|Y4jyE*
zn3%YaST6RoiKJ5|%l)(#_n#{H3_{M=i%7n+J)Jp%Q#G*_9EKC)QgMnrBX4E#?k{yX
zC?+n^;Tar4aHi-TOSk==rliI^HUK|1H2A`h4w>LC_&7NoCOaCPk~#e45tk;wC9C`f
zkLoL%S74NbGnL*F@&O0z38k#dLfoH0JB9r_d~@?1{Bpx%TAtN-p9m7&z%%XegZsuH
zY&c9`*{}j-e-H>i<*#5+D$t$mvvB9(wz60L%a1=$&qp~>n80kjtJ$GE6n^}}llRrq
zGq_vJz53q#mfdVk<-vI{`i1nt@ZNL9#X26u2h5pK?Q{8Tk_`8jh$6obKgij^@9C13
zQ6~|z16JWInNtbD%nzn75CQ*W<J~>BtqxAJe|1<l-;yb3z|3cN{@(0IAEL2Oq$76f
zW%HZ3Szk)izOQpbdP#jt12kU=3I2QCo{%+Q;nWVIi`YS%dbvXc{nnrRH|zC!=1wk|
zFWWP9*ko@P{N66_$;kzIX5ulD0<ia?gpur7EZ^Jp-pM|LJu~W^Da*+g7hXX1!nt2N
zuVMruyC>~opgFrwisa`u0<X==41pSuSJ?=`*3%x*{m-#BN}EvHMYcn9g2}0*p>Im4
zxYc_i<jIxfrVm~<m&sE#=d7bio}-Oh!VUj$5IH2!awRy!jtg$P>mfebySis^Uhe|*
zt1y;d1QE!70dXVRr!#SI$)$k?l{hUi%#n5-*xyRVkEvs&XdheGI6t$>!C&}lvJ>K>
z@>85U8HsTpZ!<r6E6%{);X|YOT!p<xvaRCS9I1Wm7O{Zk^EPIm#-o}&xi^P$=Xqy{
z9x${AQB1kC5+#C77H#e!<mGhEW}L$Ee-q~}QbSH9_ptpyF{~+$YHTeH-HS;wpj?HB
zz2$EE3;4#ft8*s`%>h$ifBaX81_K4lyyXRU)~v{+gbFkbXY7D29gcM;D+FpP8&?bL
zYI)jHirBMcw?iT2Fu&Y)SG72?lez;^pg_311Y)QgMJ&14(~4y5GIt$J*gqv5D0E@b
zJ&C?`G9kHnn|>BZC+}0AzXlmiyd9z%p`bLMat#N=h40qjFM{Uwki>$W#WQR{GI$1m
zT=qzuul}NO4Ri-hA0$UAL?ME|@R!q)_NPcK3D&0rt!YoHqqJ!>BXz;}th4y5M=-wn
z6ODL1Xtn-}KZ8FGi{LJH(Q;g%y_Fg(@;u%vWTa%Ua7xFxYEJra1DCwvh@npLZTS=#
z6qsGui;y3xs;R)-<LqE*n-gBa%S#tE!pt5EYZ)-|;%SIUMpL}mf9*OuUuI=eMp-<s
zIV`AkGt9C^bgLzl9zTtOgyul+p3aHE8ydaS8y~oc1rF1J?ZkRGZ*WdQ^zQDF*%`(n
zc@Fj23%7&?U3AXrLGwf`T8pJ_Mgrk5Vj~PI>>jbv`Cl0!u^G9Oa4Kn{O_tVRRt{WP
zmIt^TL+AG{R9kq)vjJ+^Dl;TL({VQN(>XwB<rG+nap+>zZfci_qj-qr_eckzN*EQz
zFY#WFF!#(Yvkla6_Lk5es_8LY;*<A%P$oeQ-N|Gu*z;^L8F=K8w?|psY8x-c@0*MV
zE~@~OSIHGNh=H#(g1t!C$0A&(z-7ZrnkMlP>&iJGNlyXf7bx1?wy)jcml_c?6}IbW
z(vf}I0!@b7VQ7XlV>(=o-#2ybEBCQD2<Fc_*5;p``HO8qZ5}4WLUYB{`CGbfKlSOI
z-$81E@6vVq=3m`U28WNoZzBVyJJ)7oW9~JQ3e3La(*ECqjW=F+vMLA;t&%@79%Pom
zC+Lu9e!Rr;^1G7NyYb@JjaSe-E~S#EQm$C9{>y(a`ucqvH!%~3F9hV*AKke2E#6S;
zc&&frmLf&(%`tcPSWW=FFM}t^HiRz@J3Q$4tM%rZqT}-A`oiDJWDldyagRld@lhTv
z?ML>orIKQvq9+|kaWY)NFy@p9vMMdL!(N-<=Uy8R9F$>Ffj3?<$qc9p>Ju;lE)#FX
z=1tys>8pQ?b6*)GDqp4G96c2qkiIibu=DxQ3>Osn(oit69OFPQT<0;p4N0UF_y;W(
z+rxQ<tx8h3sI7QyP@o8ZjUs0HA+1U%>#Je<+)rVUv+$6gU=-7p5b9c9Mz*1kQ-4NY
z#zRtCQM0l|lxe8Tvc!umEp3iPtR{gr#~Ki$7blo-Bzq)lB5n&*>=Q1VCQ)n>{1-c0
z30VYn;b*8qQ+t=DZjZ7&PvsL;UUL?L%s0HZ5N=wEmohkma9(`A*%`uy6QwPSN30@{
zm2eZO6#TLMNKbNV63l{1%HiiFp;M{Ub;8V#Ip~gR0e4`c5I0`-*gLbAKmSja6_1z2
z8ORK(XTuEB$jf>-QI&CIhHuYe!?7zRmrHKNO(-@puoe6c1t1-!9YkF+9+hEF6w<wY
z(TM*s$X1}4_`&Uh>Q?XmpS(I8%W-4%tK~I2Um=~DvF1=6^0MmV#f3W-!G!o_>^Dsk
zLy!($92J<3kNm+bQ!arHiw}PM6&&FTf9x!~Poh#Wz|13flDwDP85S5SJ`UJG2P|~t
z@Q-|g26!hyd>e}i`)tQYwUndL+l)1ZIoO<FG@z!zdO}y%)C44(Bp`vcO6IP?y*tE@
zR#q4LqXuIGJs+sVH22S;3xHJgbirpSOZ#j=gOVBcrGUx?c<^p(;T^upjw29VvnzhY
ztYm_u+Z)PNK%$#le-ZA&erBW@7`9n)g;zwkXo^M39AGpe`VU8l${J}F3tGfba0pCn
zSaDpQ0uUD-AwU@?sGj^g;ngB8!TYTGiO&VB_QZShi-m8ilN7LK;4PHrpelAA!)Fv*
zJX~b%Gtdm8mT18g(2V|e7-+W(h7+plm+Ryz;{zMPduXlNH56t{H*o7#Ish+f%Y4OE
z=I8&p1ClbJiaK)&?UPd3ljaR3l2wcVQS=Xl)<sD`=A;=QFx-+Up`fyr>|VKZ+3ePh
zs;y826qQuN%isU=a(b3iA?O2pyU=sY!i^-oC9gVJ2=WXWM5k4+*JIAXuMt|KR2$%w
zp@61t5U-Q49?>N2HiYoDk<gba_<<<r$k%;{G#X%<mv8;5*A~7T0k@f)SppdVUJyo%
zl;^F1aT=@PHEw&<^^e{opWKGK=*q}S4sg-yZEa(8QwTGz=!|g1cr&uR8-;&<{Mu%j
zWuygc398I5YKTQ-<YYk2fDa0MjWL)cxs>rzqsTv6R6qr6Z9egt*~3VwWH1Me4>JCO
z@R~*At;Ak2;t`~={*HfvU|y@!_<StK`mLt}Aw6m$k7Z~~xQtugB~chD7LW=YpzT)L
z!Kl(S`LCm}a{p=y%*Tz~4fBqu2)YD1i(btk4Waj$C3IKT6J>6RKvo&L7Te6|_;iWq
zaCprueW3u>QqV5^b!&7()wmY9zQKjyAW>XGAVeGlzi1#czf%=DqteL$hat$;PyYfV
z<_0vX-Re6qj=Ruz!fH;ci!#qJSjzC|i0BB5QpfC5anz#aC_q;B{G^~!g1gu<QBAHj
zw2B9N$)&e3z1;)+fhj<Vx}rW$vaG`OVtkDvv=>;Wd$lc31g)FmTvYZR@HSSkG%8tE
zR_%eOh$s1Kc!judu^nYk-F{6wI9J=FWt3GNN;6B4>+CnEVlT*Z1goY6a~+9-wCG7r
zYhDs`LTlk#t-Y28*@*RuJ|ac=LC7c|JYXr^L*zk|ZMbca6Kws*{ysi1$PMHvLIt&4
zBS3fbhk<}HiUdJ&QhXumG5%DfYIxJYau1Y=P-G&6H2Bo9w1Ch6R?KMKmZmGQ@sdyd
zX6YDS#tXGC+uB0@<yP%nz2iSy3tI&5$VCTsU*msvcKT+z4m#p8Lgs_DyI8yWEMvs|
zGoDMhkt2trB?JB8E*zCvLAXU@y<JGW)<%-NXfp(F=QILMIzmRv?NXL;ma$|nBHjsy
zN{+p9r<-8q9BcGBm89K{<LPwU<$Jyy#hiY^eY<V-i!Fkz?=y2m$#Y@JSXld6pHQ6)
z%>~KyNH{o<Eo3-<lkNoIDX=U?oV!d89h`wWK1nTEuxKe+TVY~$JRm2H2C!;|ByS1E
zo(kJF&^J;tjF+~j+kmOaN5c^^>LI701p7NF3k>>{>3~KhI_hhNJj_cSo8152(v^&q
z?(kywhlwm(cZee4zqw=v#2)Rj&vk_~*+cbji8NK%xL9SicIvHET>iK4GC0SQF%%>l
z<Qp(1k}3?*r%lvKw|@P$hu?g|-B~uej71&!pT{G9*XQq=9pf02GYh~mCl0LT9G}O*
z7DVs6gHJ9_2(JKN%0WIpk6&~~9Q9-19zvK-hXnCo496A4zbsGHp)2)87m$vogRQI#
z0rE1A_c_n#mD*&dtdmmi{6m-TQr0VOo8wtZ{B?8!&y(?5JgWju;WA4G%bWLfvD7~&
z7j2G`HNaI$C#VdKTOa<&b%f}X#I8mZcv+}M3*X7Tc#1yX#eWtT<8v83QBK8s&#lz%
zCPn38gY#^8*8)9oj<fE762Vdh00>oA95%w70%U;bU~k|BU=W^MOF>LPFw|fm0}MV8
z0IYiC8f}G0S_r_1IyD@s@f7Ar4r1unehLhXz<BbLmYXf><8F=zIm+;SXemh`6D?e=
z!yXJvS&0C4oy$S2=rm5kqAo>;<Iqy$z%evBcEe>OfU1?~L6&%7JVdi2b6j@Bl^S5r
z7Fq98_;stfa*D=jHUUYXJA4NJqlgt?s)v95s`0q8e3@kOWn;2v_X1p{(I+N_`I39y
z0~333N6sNLZuANo2M&Q1Haw#hCyjO};(>|ie`AIu;@}<J&pi@EMu`J{Xn8z5<^;Mq
z)IyHSpcuu;VOK?HBnA0vPVTV9rQf*|B(!|MoOjah%mg0!WJ8z^*9s(nbbQ8@rup*(
zj~^b8YO^n>M84WMGozx3AMHkV1cWjTVM(P$daMgt=Sbo3CO|GFwFJfVrZ8^~t5puZ
z1M%R-aTPVA?3)~@oNhs5`pkvvs%1_;U_X*msaqaU3#qvRXoxYxim805Ecaz3GNKv9
z#W5R%18<Y@0l6$1urR}bhVZNKCV@S`bD&P`l0Y1UC(TK@3AJ#Br^QyG;f$A<^IbS@
z<~aGO0sL6fT4gi8U`aBtU|GfSY#$AF>O2~<HSE$3imL}n$r8;%rZoeOkwxuNVgflq
zmj)aYSn+hi?l*5+879)%mN<$fP}qaFGSe3WNyWMU53XaYhLfTT)*HDvXWp4d-X82)
z$lM{occJ5r-3#{=ekM?bcaBuS1^sztHD^htZ)C#->;m+mF?h|u%4b=`QV52p0ml>H
z!zn3SSz4Em?{isH7oe3x;vzpiZ>}C|!5eb;M#o>9H>G8|9zODRTI?w<zfOvhGbB@~
zw{*@|4n|v7(c}oA{#DB#Q~|aYsh}xSP(lBok_pg~#!TtaY1muSrtC2J@8GkHmp@MY
z3=!e2$sgRkc$VNv5Ym<eF$W<_*armkM`U*nmCj_iZBRx9!I>Io@3{(Qsh}flA^M7x
zaiEaST_KN}euhes&pEcXK*<N*f}3PKDu~~S`<pFQc@9&;AW)u4Q(St(^ef}|zmt=a
z|Dur6$+58)e)=z1$f<8z$j(jwY8<@}XP19r!_)f{vsX@LxnRDq_wsV`6R%8}`Rap`
zXEzQ?CZPZRWxtIr$58N+b1bay042V_Z@4`mIN-i3FX?Z3i5uZ!)Moe!yM+;i;o%Hk
z#{FIYk^d+cElt61dNoToy~*zq4`>!RRO8kRWemioyliU|9B<LIB#o;8Q7ptu8Mszv
z2J_h7iw4UCWn>^GR?b4a5K#RsCLM~ZwP;`11}LYfYN!vu8^oRk#J2GuJZ3srW@vgS
zXUPnDYGCiE6ey#pX6(r(AHQBqK3~a5-h{d50W9DckU7bQpF!laLyO_by9^|Zj3&C1
z$NZ8bDOQ__GR_acgt1&j8$&ZxR%Zjy0`pq-Dp7#R+RAPib_P0Fh1i5HkplGM(ht0s
zLd;k>NB7Q~Zw$-xt?<5VO#{aMAS&B}zu=p5({%uzvGSq;`7r#JGDJ)pnIUMflrEr*
z&)Tg8C1J|*J0=5CNfHYB$m~i;gXJ;tElC?Mf8cF$H6pe)FJq*FN;A0+VQK?xSoW1A
z@A92~^=}RAnkc*-xi8Ad#-=7isaT`vqwG!8uuw4C0>ZI4^aN9fUlKtS2DC^UwrIoH
zcjC36elVtSAaTJ{U(hK6Kw}lzaF`)<f`Oo&GDTH#WCnE&xw_U&r$KD2bKem}7*-qH
zuAz`&g*n1)bhZ$t!D2Fmou~=YU_9^y)r0GJ>*r2C5SDe|K>n<6p(Pkzt9APXf5_B}
zMS@od_8j)mU_RVy!)H;6;Y30uLApS8IzTr%Vo<OS<Bp2SkfUQ)KsCTV+5SC?Ive!j
z5;8Mlvjp=V<_J-(izF_AozPr*g1%jld_0MR%dOkJkQ2m@Ly9mzTQ?v?@DRCK_d~PQ
zR0fI<?^juDZP1%e@z-MioTEb^G7&@;XE09107KHkKt4)&iEK}etpbpNgfVE?vBiZp
zumL%U9D5MZOE@3ji7v&5i0Q!+(f}TeN_~@<_80!-bx3JO87?A)HcJV50K*3XWzi80
zT<sd_)1W@<a|y$X<({<id|GUi-3{r3lZP!ZbDeePfxL0EycjfV;2Gu*aRa0w{=0vT
zN7*&cIZ0%1i^WNXmt%2(AU!}52_o?vRyEO9IF~F*2VtfS<qLBM(m_=w2bU7ir)d(x
zF&QN;pfsZdu&Ff~9-Bf^z$cxV^#0}RK<_k@B=Z<7oKjN5j1l)Z&q0KvL(ynO#4X%O
zceLphiP+v7oUnwB_|EAi4)mg}^eknX!F$2_+%15{6fBA`QQ?#FV#W-SnxeoDOtO5m
zTIONfq;3gKv@1;lno7GtM5JHI^3^q`*mw+<RaFv;XupxtCffD??afhq76~=VgkP<%
zhRxey+B&rsSdI?IWhP{-yJM}Cyb2Ou*xIy1M3ejy_qWg(WJ%HwC?R;BH-4ZLHw;Wn
z`4NqsiqYZF9d28?mZxyhE2GURPCujJhK4@ZLK#yVcQVw&r36VV*FklPp1HoL0SvMz
zs~4T2V%P?cC0|gpCm|Lp73IaR{3@_}ZlrhSJPXZ45Xd@w4c9S>QbaTQm)MmXB&K;4
z;E}Ffx@@T2RSGJ^#mG;D#+d5m<uiqHFzh0c3gs#lKn^{@w-<C~Eb|PFQ2Thi$-#=E
zC|ZNWVyp2HfXZbzafU-hb@*8!UOj5$3saS!z4P-|vomXrPZ)lAo`(zMIM#_qT)k!l
zxgzw(x?mf4h596P)nwIcjL;W~66NTmYYiW146YXHGx!g^u;%>dMsg^^%p=jRLt}uh
z72)Wbp93D1$xMuR0$fygEX6spi?}@oPqpy_f=o5>2Yrp5by2?HyfJ2qtE})pe=6eY
zyAZ`@f!%VC1DNVzYcdNtOROS#(Nml2c1>69kaz+ubphsMj&@uNXo9vk;FFC?J=SD-
zt4Xo<_yHQ$-}lfBgf>xNhIF^{xMDgUlR`=T1>F(DG9k4*3HPH9P=yS<>W?QDa4+VU
zD9Q^TLHbYGFg@`zwf&m10W1IdKl$YLN5*ciAIRQCw(320aF@YTX&!hJh@*#N;UHj#
z;j=YX2i{4S$P3pYKDJsf*g<{3(t+Ft^adVAa?>J`|FScHzn0-P6km1}w2L7X2B}Z0
zrLJHAA|V7zB7Bgw!iU&d+m1fOp&~3fTnL^3SQ;<QY)jFf$DV)VH48Now`5~DFRzW^
zvQ(dYFx=C^Z)s<(pD8O%KU+wbP?*fv@d;LJW*M;A19k8tfG!G6GZZd;;ud6!;4g^-
z+F{6q2|JPY+0?qRONfe0<Yr_B92c<C1K|NeMtCcNnX@u?;*6eB7^k$1b+^V_x9-4E
z>ZXUT(b>A+CJm$%9iHd(+8Ec)2g49d28%;s;C$IMJHGxdrR!A~lAcGS<=@igC-fAE
zxCt4(;=TJM!{yRG-gxnuzXLjXP`)vfwHFo$r#HLLY`d>E{_ZvT@QgoWiKzc$K#kFL
z=W29uq7I57*aZU@yAbrWBhR58iSue(0)a-{jeR{l`eX=ofCc&P6bc>5D>O#VNryR&
z);oM6F5j{nBxL*|X|Fl|WE?A!uZIoDBSa;)osRmwz`Y<40iH=$nU&gkSj}=9C#CEN
z@GFTqKK9aYXptHE8r_>mwFz*UQCI!F`AcT^f_K0;lwbjmA#~roysJfMHn2X35MWC&
zJoQ#C51R+Mx)x(@3jyM3cfKu_GTnF4^zv8%Kw$<MnuO6xEnPf0xP|XnwV)tE9~Rr3
zmh$|y8AP5Fs6`e-&RQXb;6<p~DsMsL5@dg`pg5gEK~7E5=gE@_@FNErAtj*PoH)%!
z0EUZSXYZ4NM!)jFdmPXqX)D_s79KVqRk<%A{gUy8$dG2HD_NpIc4GdYoZbpDvejFk
z{+-o&`z3R<p5aU7nlw;Va<ah-YIIde7avep&JSwLnR<B~DQZMGlzJr|M4zT{EHuyr
z0fX_&Z;B~*A=yn}8|b^)D3mUjf1UwesnJ6EMic3U@<ig+^;S-&$^5VW8t@wO8`yu4
z6G#pygFlkNRW96hR=|*;sWYQs1PAdoqdDB9MkpPDP?(O8AIJcG84De&EWC$rHj+D!
zqcg(<dcfWM!si20-EHBU2$ZoKvHl|>^awN;Qo>;}_|N?CqgR7X0`uXGwWgeyIG7E>
zGn`)*WqW~(SSk!vWYln;3DOL4=>iTp&B-E#+C&|ob~Hg;BI&HEwL1uGh1*s@12`Xt
zQ&2eL7z2S>f55<PWJpsH8xR*RhD;Jp(;4wze3XnU_}a00<B&u#*t3A3O&uajyB9#L
zaMXjAUei*Oh6{#;LJs*v{7VU@-)@nS#s$-o9>B4gfGd|A6&!=IwE(h`iO<bSOp7iU
zfBlDki>1txeS!saxdLFsasv!Zh<-HS*7-fmvwL%R2VyvU)zmpG$b&pbW+{=_DaK#R
zp6u|Zxg@=gGiEg?FPZ1hvSzVv_3-$E^+=V)_FDv&B9Cj_cxZM)O(Nmr-#<z#mr<ul
zL>AhkVOAf1C=4ei{WZBSWn@~=`IQ5l!<Wmp<CDj|Y^?JNf^mrN7Z7`{!gN-)FjhlI
zsT_=?zMF+W1-U+GE}I|D<p`}+$PKg4I&_JZuwQ`c&Ts=W@(2DybAp7l<yH9C;+us3
zVzcrA>$^r5OIb!Gio;hvE9d@%;C2X*i^FHVftd7WmC%G3kPY#K2k<N^XbjB8ATYyF
z&sgg9tKy&?2KSshtp$H1T$9&-^MkL%jyM$L!{Hb2_+I3I{6Sa9BloAD&XzidmLE=E
zb+E{Psfi?Kzu`1qe3AacJOjD`7BOpKGe#IycX$a9Ndpcu!V;2B`l35FUR-+hOZP}I
z{o()N`u4^z%`zX*--ge=`u5FRVDNAII{%?^cc&jV7b;*Xwend0;X3v$h|m6knP)Bl
zJ4o}z^$n9IS8I_WIDp9C4nA=}D3*;3u`xwM2;{(yicn-Rnwb7FPHf6nW6IeMn4=1<
z=d$!PkKMPe@d)}>?f$#a7Ey3fpip(5YhhXes*=1z)-N5vX9AstI}j&m==4}hmYdAh
z5f`qN_Ukza3z~Q{YWwz70?4yQYBEk3xP2G#iJ0g5{^Ps-BXuyM45H@*gK2EWMu9zW
z{lE&wCkG>i*&r<&^`8~SQz#P6MqV&YQDT`N3<<N8-z-yD9cDiqB0x6Tndo~mDUsQs
zEcK#<jqu|0*P&gv_FBUc7@)gAiU75e3^X+(umlyJQRQ*W8oWr(f{Jh$2S`suZb()%
zZ76SAv!HfNTj(#m2ntXPp*=`CIsiHoW$a8Tz}-9lw?_xgMt~a4a=u*VkIhg=Wpj|k
z7OLwQ3W!eOTo$Y0K7%^kL^wcIgJ+7)nE^qe!@R+ckXDrRB2+yY1>7TBy`T^g##=wu
ztxjO9@FFN8BebkVzZt5mim(Q6EOSDN^j~n6W{b22($+2fPz=~uWiMHIs!VpDv{opA
z+^RM(l6;It1|K{K=P$mn%9<+bH+Z=)vkI2#cFY2lea4ZKnzYUR@cXYJdGrL^)XW~U
zoTsS1ebwCGO;$&`ZEWl<#PMJP9<(V)2?%Ik{%D;HlSCU23_uBO9M6H0MPUcNf+@(-
z7?YeWuBC=yRsdY=(@*$}vDdNHGEH&I!AXr2dAiq*C*;n&X_A?_rrE36-wa2Q-40B^
z?PqmDyof<9!;BYf2T&0NSPguk@I~WM4VCdvB}BB2Qh11==T6KypZGtA288Qh&Q%EB
z2&8qgz-qKhhgk|=WWqE@WoA=K1lt-Jrc%3@vAhhI;bcv2{SJ>Yr&!6EE5Z~yxVshd
zsFRUW_;7|<PYyPHBwVW`9=1)+dMw*F2x^&Bqd<|WU3f){?kc0BO1M##4ZBKPbeDS-
zB^pYj!I8wlV)4>q`|eBE=xM$3W<KgZ826WTOZ}j&1#6_cNj&L3g?9Lhr*5b+hOU5h
zjEX`aVHdi~x7~MxJYTYE-WqK(J1cASRX62pP!YDxntNIbE+bTl2bwUn16qK@1etS5
zq=Grf^T$sjsF3twbQpjtazt1JRAqO|-1dWhww%jph~cqKX354@gB*60h=Xp3FhXm1
zfSHW!RU!uTD1LEW6)F)K!~B!7OKWumLxIVF2aby*LSl<DFMf_8X_hmyT+Z~Yw_Mf`
z=_MvdYz*7(oK$p`r&KkKfSeEv=^zc3Mlh1p2N152)F_L8B5J+(xg{QKj;aj7NfwdG
zZ<&0ETw@VmDp(>?DygFvK247Q9IgcKDa1!y;AStSyAcx?@+?dzpy#I9tI$WOmKR4q
zFXUx@rt3|*gls@#WfIdLUi!<t5cAO#kX}AofLq>FU;z)f;jC~YJ;Se+H%flXkL!-X
zAop_qSJA3LuqF;y$0w+dm*}b<@v^}9pfrx(C_&mLFG}Pg`NoPZc(Hm&_w(L&dIWr^
zHEI|Vaf{|0f2jldGV?t$3+l;+<US*z8K7c3Pgt?*6)j-M>49jYOZ0<xzOe9Qexx(k
z`?brv+Z^C1XpbN8E!G`wovbi7^@S%XUrlv`<r&&cnUPPjT2M<ds($2YDpLi378ouR
z$MkiS^`7}L4O@P%9oPX$X$H+4OQiyO1Q#RnNnP$ajH)?0=j#d^$X)qoTKQO66nPi<
z-Ko)8co9!ElyQVfCxaJ2Z(wdT3dYQ^rph%a?C=C@FsPlB*q&kMfULV2KE4+}_@`6_
z(zs>@8OMpthph=5jKhUJfUW#v7VA(h{$&DXjsvrRy0Wi#oYfWegUq-fRHVwxgxK_I
zF71g3FIV6(wnY%Q`2Qez1G5M<7*8k#CZiRA)e^vmbF&=M%K~8grgnMDo11&Aa<y;%
z&!+S+PE2EtHFS1BiMEMzQMPd!E!-qD*r^rF0Olvc0X)vRp;}#$E04gIMQ5c8rqQpj
zfM2A>k1z4-1%t&d`{_V!d+nBwqhVmp1<##R_PF_N`Saa-&f#YA(?o~e%xMkV`}oTc
z=Q4`TlT|NIgcyAWd(Yu1bsgq8K0JG48GFX1GYo`Uusj_wfFIbwe6J<=1)=gCh`~}Q
zG`Jfr#;zlsT%N?2q|MNUgEgH`OL94))23UXE?AHMkQ+IM!7#{rfXMk@{Cy@JiR`ea
zXgin&hmy{hjT{elwa&QctL9S^^hRbW0EXHC&Vc!g`vYdW^hT|oC@(nKpefNnzVTV+
zD(1IN!36UF^ym=bV|bUrXRxNRFA>+)GLq8G&`Z1@{=ikZXfS@e`kdXB3!s8RvX32v
z;+?^(hIp`D-NOTLm|?_}OkC%HgF1sKHF%p~iHC&BfS%A&7AsC=Q@jp;{2`2hhYr>_
zEj(ZdV3Qle5dmJVP3k0rYp}mrU3h=VTsZ2l-}QaoJaJwNWo*M`e64i2t%%f>n}{A@
zL}?dxGE-S)&^J1+17suSVu5){qnKAn8wN-djs`+Ugb@pt<r7T?gW@4k>;Wb+(2+$_
z!(=Y)G=4e}FoOS?kB;P=5W-x85>Uxxc)E-tLMUj!(1~P>CXm0@cbyljRyevS*b7Os
z8fqM$>uRY3WfxrFTuJ11LyxP!C!$cEgIX9TK@M_mQoj^hC(?~wrawQrCV7YFR)%7~
zjNea_|B+*|yekk4<|0d=R&OWaB4#?YNB2eIQ71zPN)EI5Lx4n`<})PG2`JzfNLys0
z>w+>-BHWiNPyFAngY4{iXIeMF21E)8PqzpVXSdARx~!-h0V;CZg18$5hW$K|nm|ql
zKxEMfY%CwHO->F|D@^Gz0BWN3*57s;hrV~wz02M%0SlYCV-WN7Et}`~2%1w*y`e{q
zd_^4W18*M$yer@)VzQ=zT{zZsR^BkHQd1Zr(UgB<mHK$1I7Py+zMhn3{lFJksgUY&
zg7L`vmomoQ2bhkYIY*)@T8tLOWMVIp)PeK_M;f^HMD3izL=pam|8=$<`k>GTB2961
zfehgR`P9IMi;z1&)Vd-9M2x@+Pw{B5hgj45)L*~Wva3YiV@X*Yc0kW?sDVUu!VaJh
zrlimkPY4pqp!z_>nZyu(#BKm34o10|<^mfbZz&p(gvKtKrr8Q(=qc#%f>b`y1GQ}Z
z_ka685e~9>*6aW0aS;34@V<Ll!+(6@4=jm7hE~W3FpY<ph`Wikb>rRXH^VPZS96#7
z!&ssCNcUNP@gHqo{4U=&i+#mo>!19W%xSm*aZ#<16vgrxRV)W{gGteQu(?oDF;QWc
zBWxG-efD<IWobVW)9od*^h;+$d|>I5zh4_QLjO_YW-u4=Eui1_2-c~1w-4h}s7J<}
zi~s(A#Re#Rr<K8htoi(dG0`yC-!e=&BSSuF%RPc-%Na?`$xS_}9(u+@Qz7=ncYEG4
zk*SP(k6@muqpOfsEnmS<``TNOQKEcKhezE=cp0-y`MXi=Wwb~&VthEa%=HufpQj6%
z`Vt3pp6sN~;_4gfl=B_>FpfZ&2qhZKy}~6Te(@eAX9!bf_>v|L-K6kB7piWu4X%3l
zXuX0b0a;LH3MKcUDYOZupd9{38iTor)S?^3^RMu^F00r5?5`jFS!jWkDpeE0$b5r3
zXh>8qBSSl+v=m}<%n9^^0Vzd{DF+$S*VD6&c2hn-F;?O>kYlW4>gBWQTK~V^Nk<SM
z0-i7|BrZ99!WTm`$j*W@sDr5Nv;iy!auO7UUWue5YD{HfjyHi9I38Dl*KAzUm&k}E
zXs)J$>T>mq`_u+lXZ_hrENZYQ^M_%gf3#x}ZBqvgpxLsrz=I4CXSlJ&g{@`Lo1reJ
z`O+Lp7(-zWb0jC5rPRW>17y%1)LN(noz-2ssLD0dhVdVKUY|awxjVEWL{2_xKGS1E
z^ZFFBiq@_N`+WD%zBIo2#8-_=q;71y3SVDU{_w*3MO@;Vm4WVqU9>{8Ebt_P8|vxw
zTvrAaVoSpuE<X=l>11URGQlypX%W}5L8+(&6-8x2@-|<tlYII8f6X5Z0xEKV28%Iv
zm;{opyT6X}+^1Lmi6A&Vpiz2>Bluf_NBM?-TEw2k#rMz&70sLBFCWDoe01g~B!;V~
z+c}{)w-nv1h6*awAXB9KB*Z1+inw1x!DT{pJ~9$<zZ%K758LW$(_-ju)HM~tH)k|D
zX9;+Ns|5vdk0ZHckbAkY<8rWCTfg@y`mMQ2A^hcyvYE@wey#|B9oFTnekca+ML8-7
zeNrui_#3R_ny}Fl*LwJ8@DOD(=T!8t54<^N1?P??qG>vD4c(JMX^MjXbX~7Vm)uLA
zu24*OuK&~zIGVUWL#ntQxQAT<j^t{m2cyVz8{SWGwA;<EAt6-mkm3vopVvS6({2#C
zpT0Z6j6gBWdxj8$mAw`Xx1k_4owWeELns*Q>s3&WYdn7-lZKZo{L|~<PhKmkN^tOv
z|0#XrNA93=h2*>8cIZX{t~dA#NEOvftOMcc)UYe=8U@e<=Jaz5!@FGDT@9L>0vq)h
z^U7g}8c+NnXfs!FsWKWAAyz7q|M=iOOE3*zBAPC(pZ^*4+v(8!f}8_Z<$~14VOOYm
zST8^Gh+8zM9x=aBl->&Wg#zJGCqTkQ6#AgJc>XhpRrGFk8}w6<0%8}|hxmf%$GXOk
zVndf$ljLp1KfpyC2A2%NkF-+yV{scnEK;YqRl>K3hZGa#L^`$@^sa8v1bB68O^!D#
z85(1HM9u0MBi|Q#A<=FOvPa`@6y=PbY7oeDx91LZVU@43Y=RWvMgc%=H92Ui>XAC(
zJ|J`>!*^<>RgzDV&^PLyu()_&si3zm4T)zlZm}_VbN?_)!6IlLg|pV9W<)x;%~`)f
z54a#lk3*=|VAZ<Yp$3lmw4>wxVQDyWD>=rMi!sK4`+noafA?b`g;+Y-3wR{$9Xern
z%MXznW>438pKW2TWAQ2ZgdxzO#@4bTd}i@U-^ED=M`n3;g@_=zT?}osasP?%0y4w>
zaIp4<be0$*47Lk#?BaXIPg{=Zq<V)HMBIt>M{ExVe~zrwZpD=&^SpPW{L92s0Fac3
zn~suW3X?-o2`(~0hCEc$x1o)%P5KW@<skjO>@@x6$cbqQtz>MeK>38|kVm&K?>4e!
zRgTLz(mua#fl|yIT^jzc@uG>E75sAe4}d1ARmL6lV4yM+HonL(h3lnrptxy2UU#~4
zK%K=pG+SlxV_ObW#DIYiJwSyKHLG?iF?`jZ;l{Kk&Sq1f*7||BdF*g7-5@aX%@G1x
z;5ou$vYAm+6urb9@F`UeTS6VWN@IugQnz_YLU<Yg_1V3<9|}kjbBXuEpD3#!&SC*%
z(7_Q1G5y0mg8!+pkEJdkME)2O%fn3i#YK9yQd109-&d_VlmM!zk31$KGZQu_EJ>yx
zs7}p@d{Ki5`rbcwCvtMp6S0}AP@SHM%-a!VaupGoMGe)iKSrHFhgUo3LO>(LVfyDr
zSA`7)Dp&Lpc_jhY|7O=oF~c=!JQP5suzcjpenfMWIwrD8i;yFPx`%|q2Lq<U=Wtk>
zD{x5H;a^8aI;A>3FMZd^%_fR8DNo8gr7Zhef1Ng{>rI>nC~QIckSkWpxhz|Z^D=tA
zYLZ?ddSUUqFqyAkUH{4pNC}G%unw2vF~k;b2K0;6DdG>b6lfm`EReZQdk9K#D@C7<
z3_TaLCpxT)N?1#z)Ig=?i5TkPE<o6r8A!2a2#|W~U+Qp*rQ;{pF?k!PR9eqJ$!o~T
znFL%sGAldjkd?p^@}^xqL80oO12sa99f<sm4q`Exgl=BxxB7m6r}CdUSIW1IN%>32
z`TwfaFT}A-UC1tTPUSE-hVOTux~?rowc=#B!Trw=h|NUuq28j2?7nO=JY&oEO}2Gv
z2O6&=0jsIr`OCojH$D3L;d591Zj`g}o#AsO!EE2bYd!eah4@dFgoQ)gzAYH8cE}8z
z*U>(vMTm^a+D4smA}ExOU}W8BXMxW>ECkeaHjv;d7I+$gq9*f#1y>Buwc*N7CsEMa
z{{OfDNhIB9y@*8%f<9=aOt}a<kN?p&aLB|A@5a8>B!(UrOv$ChN1SO_zVIo*^_L1@
zbgGj)K@pIQ;|DG$-l3<ZD@nnW96^=fMLJ1lJ$9YwWVoLu(m8dHEqb-9<0AnS;w=O(
zjYNIaE7uOyBN5>GNvAW~#t$!Udp-3)Mg2o!O0hx{i|K-cGK^{-{-Ju@dNJ*3EM6Qc
z)lwjDj*8TX>cHJzVfYmqqPNI?q)r}L|Kh)*g&Q1XndB`Y2x#M&LfoXss8pyS<-j}a
zl_1Y}zM#U0B0MToT@=P8VJfaNK0z}L7@DH-KlP7BkzXiXbVLfPG(`9$!du`79=3{m
zR}V2%lw?9~1dLSA;Jr+3GT*eGIClnmMR`c94Qm$(LxubkQ;7K7H)NCBe)nqqAp31-
z<}>oU0TU>5s8*utF_+{YEtrOy<-`js(k;srqY=0TV2x|I=%P{4>JH{B)zP^k<~n4B
zE>cT*mm;)&;bRcRVLsAxMF<|$o232l#dyIrVsNQr45j>VhQu7+Kp%LyzG|pk2c?7h
z-p_2~2RM$&ua3cmLu8bO#dtNq$h1yeO4+VR)K9)IvM)D8sAw`x^(j_=D3S7Y0wLq)
z#tU2FeaBP;&2lxt6+Vq6<C&Xa2y<#@J5FsFZg)~hBoevenhc$5Gq)8+?g1LS&0cuk
zn{MMi#+c`w)wgMVv5;^VcWN3r>qGZN@*?3PGnPLar7#i<1Owm*Go+QM6#4f*&0S7u
z8d6>l;I-`@#cHBx*DLmmXqNyjerH0f0*~S3uOqx}W1OQHl2WeYcMW3r!;@vFIZ%o#
zOE-#0+@zVVM(8JolD$X>5CNzI9l=+w3QygjU~W=z+^*{Mkn57S{_Ah%J3{hG;jSCH
z!M%(ddG6H%OiIyCwBUx}^cxmN?T+f2D7u%**FXGA8)a<1VRa2jWsNJxU3Yn;_@p7`
zMI*IX@QE5+sjfWzG$hpF=K+0$Z_s8994|_P?OnTvV*phob~Rv<E4U~jrB$}>rvDMM
zRv-1!#MYZAL^nV6YuBng_xgX^JO3Cvsw$4p+b+MN!R^}CZBaYBF7jxD1vO&O$YZ;h
zMvAuo)P$I9iNP3&Y|$7ZF)~wLaYe9_h%r&17ziK)DhZ-d=r&*?LDEVv5`Ps;h`%t*
zCV~<|>gRjToq02F-|Oz%eI)$R+wGhC^W1aJJ@?*o?!9wIaD`Z!qoC^a-*MBDC|*V@
z4Fq|Q35gnW&1+*i`8aB^gV~QpWQ3*vgS{e6!1;BML||L5WY|^|#As;nZ1{W}2YDq5
zUtB^!t&^Scm`4a*TwteQ;27aFF3G@$Ga6v9gH<^_l`d~Xx$+4b<C?sYxP-J=)NS|k
z5e>u;;Ebx4iUhNI2tjEKPzEj@s)E-X>N@+z%%G(>^hFNQF!!oeZ6=@+O>IaxBOjfL
z3aLXY-;CRmRaHDZa`ZmV1HdIs;0$;ogk~qevMH^7Eyt9+{Y9x(-!Z3WwXn(DC*xal
z6$^n>8q=jTc*`-K!Z<A#%TL!(pH`({8Z(;mulC%>8E=}j5`S21YAAmEj~*6Mgb{H&
zO&j(7bbEh7haBCkPT(H~2|6!684DWAX-4j^z~hEB>1JN!X7=!bkDQ8e#1`WoEbDFD
zyE?&E{7f`Hk=xArR-m27#ty*@{Dw}Xv%ab~A=dDzKwf*lT6eBuE$U?jZgjny59a}I
zB(go@2*bv9?b%`vhVyorQx~mu)A?F<9L=)ieoBn%+t0x))VmLRN_pJ8URTRD)@>EQ
zY)Wk?i&bV@>!de3bfD;Dung=wmcGd?gG*cO7<*Wnx|0NSvBm6Sf!u_ad}th$O-q}_
z;$b9)N@$cxJqyle2Us08!xa>)d&<NW&4&>Y$~3u%fL&wcT}-!Kb~ihz@WzqUtxW(l
zkyq7Z`D6~ZjB7J-EeI~kWG(8LX1B=bQlB<k(>b6I>j^{bRlO-7)_^t}%680v%5*#e
z6anQjhJu>ZWNjjw^c?!Q5wFDq;$`+4)g%awxVHbj=o-HM18p+r<;<L=g(HsP(-LtF
z67^`tz_?N`Q)ppi9Y+HIf~D&X5QI<&vUorZa9ox>8F`8m`k$mq;7@cNdHY*{Z*}HB
z)=?N8Qyo^&ppvSwWDvq);{;=|?u4KK>{Brim9rkn0}2&@QYyaY9US6AsfDi$1PB(a
zkO(l83oQTyu#zBKX`;MdzR1TqS(yge#mKoxj4HKB%26Ta$XA&iZ1E-7y)qjSi>;g~
zVCms`k*skNNwl{Ji2eSAb=z5=5zI2yF1jeFn4Az~hA6f#wUT`pa?p3q*aN$0ehr{@
zk%ZEDo!Dd$S=h;V&5;m3oqhW#z7h7AK_wx*hFXN)$l3y1Gw<fIi4{o0nd6ent%#5|
z&Ebz}Uc!ghA~;jaWfMpMhh1pI{r8<9YG<(}c%6XzNpg&}rfE|E(d@`88j}cP+&+00
z(@U`_wqRD<Q2|)11&F9g_3)N!Um?I=2yi=Goca0-$9KU?x1@G>8zA2W_i0+PVfuyU
z9vjPS-lNZ9uo4j*VV|pH9S|T|$?90B3ySloU0Vk7B8z@n(YUP~;bb5?{qs^uFb+)v
zK$}i6ann)G@6T{#p3W_?N>SD^hwY5%4Wk!)*yeSa0hH54{=*#Z*C4`tONR$#QBoVz
zi@U--Ni{DgwFo6TVw8vn4s5k^qnda%|7#@BXGl1-KU15fR>YVS>TI{6VqBVXLXTyC
z0XK(Hm6$d~I3Ye7qh}<w_lsHR+TKsZK<EFahef#55jm;T%~=)-LKs{v0X)#+q^y8B
zdDt`-|7GO>kqI8)GzWDvPYl>lM;s#}x3zIc+|&n7wWhT?_(4VDygFQ=dr?@snPf+`
zvf4mW?9i<W7Dm_8)BJjfP%49?Rx94@l1tQ+;de@!2vfIqCz5ffU%U>_FMb^l1zKFo
za{+>zhLlh^Fi-_icJpRg(n0aI0)lcjQ>!iY=^UL|$0^(fag7Wh4i3Z`$^Zqvu}5`^
zG}R79un_D>&#rhy6^pMaxIqgi7hnyWy5MA_NslzD*ep4yEex0}_B5L`iZnpsPK9uk
zf<Pwh*n%l}NkT9q>Kn<X&ax!$b|wa75JEyph!_vm!cv%_C5>cjiv*NPa^lF^;ul%#
ziX6_)y-`nDPzaKIv?8f8%I#n|7NPWg8HU_GiWN<Lf;i$fE?~tHVuinTI_DD|N7?8-
z*}ebr%GJ)H0r3eRLRO4?5>Q8y#vm<_MMWIECq+)gDNH*H_ETX$7i-1ZTUlJ#%;O*+
zAKX-k5-Oe0dsFi(TyYM6IQsVMil*1lh1{uPxkLp8DM&t{JSkM5TvaFe8F^jo4#eXV
z92hI`j+!;4B`{Bmc9Z2$Awhfv(ojTs4Gz2;vzy%`8-ShnWb~mmM~kN_3$X=Ptqy@L
zIm^e#2%j1-SQs!4Sd_UG<-qbn0ZD?C%}K};z23<A^1u}R!|6BqZBZsfjbL>&JXB^b
zt|3?S3euIO>H;0v=is0Qk+et-&<O*`TPYE<_0y^}WG?|0*L+AG$&Ne{(yb#IB<+k7
z>Ghgqds+Q5kZ4dfJiVHNhyX``hextk@6Z}R)21L#(QO(w5LoLnFepfzwY81VmM=gp
zH=0+k*(t8+FZ<bD5#^9tMm~&BnK|T#C<%)>JX)NiDh)QeM9Ib|xT5;Bq%jH|HnMnu
z@Jmdr6lzJXJmVywGpRxa|Ext5(%|%^DIBml-dc?sl2mL_Wtv2HrfNu#5$e{}atX0m
zO?BjqsjHUVGY;(Bo(+bBEn)yw+B&2#ZX2@x3#s;kur7Tnr6^id&|-S3`D}2dko0}#
zvfmzD5os@M`;06w?Go#xcw=l3&GPIfcC6ahfDDCwTr)LKuh~W}i72ve)7Xjd++1a!
zSH@~hqlj4$L!%S7pA!Lh<Mt^2$#=C+%v(qpvNBtCU2}?-&b0w)Tc0T1xOJmC7;NxO
z?wnGf$!6ifA4JKV3L!kQ#rQFw`|;A^DxytLj^Ml?tILmkW8cZE%KVl-m9ypv7A@^2
z=@GAFGr~aZtvFR1nboC|R-xC3H>?!I)R)w<i@yYds6!GK@BMny9sraRNHu|~GW4va
zoFt$EfCOO-QXPm=3doYe9{PnRf*qBp9(M?<P&Y<UOE3?~tT90h5ejC8SS?O=C>tO^
zrXv8&*$+RfIo3uOXPEJc+Eo#?Ao!3Xk60##i9RK^JQeWBAtaKU8>s%VLrKgw5a4Vw
z@~zDRpM)>}K^A71_);QPpQL6P!Sh^ViJ-&>vwkrcrWy=6XpkXC4cLz2vQ|t5x)%0Z
z#j9B@uxQiU_=|mr()pbUanrU_y+nC~768Kh@WrPz5qaAL;ykqqfmmJ!Z@z`<k&Fp)
zScnE6iVh0VfNT*fvys+rg683uPIAkT^)5S<om+-Vre$G-y}4ePc|PrWd<5evN5Cz*
zPL07JrZsGh<5Ts@m)95b#R~sa`9nPP<@JZQ^K9x1?D?gBz~EB9>o%YE!4EyV<<;w2
zm-_LUh&@wv+l76^f#jcWFMw?C2;_fVfK)b6i*LYp!K4e2>P3egc47Daz(h_Ol1psP
zI<=?7Nsb<2KQTeiRV3vd&O5!P4J)($&*(EPr-Ch)gJ{LH`C5~|Cp>w-DaH~Qi-?)x
zQr0W#Xcn`s?J<%uH>6lXEQsQzM(tdp-LkL&N;b%-4;y+yQ>R@GF9K3>vkl{_MN-e4
zWvf7%XthHlRa#?!>B3gV$W$cfo?(H~z)TiZNM_G8QLP?LWcJZdki+P(r{*%2-uY$g
zii{f1uqaujOSxzW9Y)9+r}Q;<AAJBO4&(HzQgSv@@pJT#Cn!ko8c@e0li}}~fNmab
z-YnYfs<ZGHT&d9l#5`r;=PJu`#UJzlPTgUFkw^}r5j=~8?GVq}3_zBa1UH4<5d$$p
z!zjdJ)9T8tlnC@Bv%igN%9TcBpoj@dt3oBIxO6;Hv3QPNEy%e`iM4Wyz>kH6)K&SZ
zg1{-Vd07ddccLgd@*sz2WZ2<MuA-(7ccD<hXO+Qu&Zr8~;Clv%Sa$F4l(pzK+R==V
zW|_*VNfAsCMdqxqd--)JMX(5G2X1af=DwmRr9|qY-E+5`5PRP(iWn>hQsrThqnoEu
zJ2c$}EYIo)_69GzO52jhaJ^8Pz4*W}AoZBk{j1kSLo6QR(W|%<vFz02dLgY`HahpU
zN^q%xhJ^g^8kXN%E^)#42RQcVHhryYk<xIpSfJAz2X|NU76<{%5{igQw)ugE(8}KR
z`=pELdWl{{cWCZohcx)fGF&-^*5~HVeykEEEY2Hi=u1%lR*t<hU6DMm<E?jc>3egQ
zLYn6^Ct%Q^v}w;TiZ-8&hKFT44`ivx+!vl`qs?|)M$MLxn#oLL#%x=zV+GHDtRet{
zV*4*Zf*)wBjI*%0qk7yGZuauaQKjjmB*Q7DT1mZaGMT;76~g?4Ms4qD)m{Xu!YmBW
zczbjEE~w-;GZBlzJErOEP%m|T@$R%=SM$2bB*-xg0GNAZ0QQ9K`4cB17#cAOeSRON
z2gp6wvP&B&H(z0;ovE9+3VQ*1$~Fd2+94HLvnSt&VA?Dc%$UgT6d$dz^eS;+zQfGm
ztXaxV6tkLSxjVSdH6Q))sa+B1T%t^MfosRCjk#x@KE4yRxSgn~pe`xYnET#M?V82H
zfa0>`C)ljH%l@{vGCrf5DJjpN_w$fFkIqZCGUhQub9ddD`|asPl2Cseyh_dxC}YR`
z@v9BxOohg0k!_QCUP(~^bD;3MCwsaAt}V64pld7YSiQP=m_q3NU+EP}$lnRrWslDX
z*3OHC!VW>X)^Dm9x0Vo>C2D?Ux$ZqbB|G=}`H^ig3jz1+QXMY(Pg~J>!4B-1m&YTr
zrw?{XSweJoRkmkfjoKG)>bX$Y0)0d*%09ilYdt+D97n8Imi3EcL+Z=ZYpXhGugK*2
z`wC1zS5B{f>k@VMrKtO_{5_{+`OkhekT6kStEl(OK#$ArZ|zTO=a?-6nQGBKv#edW
zUXuFE99WnDg)*G2W<9K`xc3!!`@369vMx0F<z_{JU1RRn`f-hYA&otzar@&|9eSj-
zth`*13<F6SGwtnlP(c+{U0SJz42=fTF*Ns=yW4Q8D%qCUA*!uV2wwhZCBC(<X@+zu
zt%^=HWZ8sV^uT{P8-Hwvh<7O6sm%VLSC=w6<ymap8>RUS@ft&;WS<G2Tv5-TWgOMP
z+ug<M+haO}I|1vEZP(pz%VULFn~OWt-j<~t%s%taa<HAwa$1|eQ$?G8)5fQ^GQ9-*
z*_^8mubI!OUXUs0?I&VUpXb&xp3C#USrOA>%kn5Im+mK(tESh!IfZO!ZpT3_PqwYm
zmlo8Qpp<tnGQF1rzkPE3?rVM1AXa66eWFh^0;Zp0*l(6eZRx0OYo42@$o7(T%3fOR
zr9=;S0Q|Z)%obSn(l-Z=U#+m_+4I8jq7H|8>}rKR^^nHgpDyncD72Pr$Kw@seOZuK
z{(Ir2Qz}qjS=eRY+G^WK3+Fs$j-Y$LRzGI0o)VWdKs5$C*RkomCCroDeb>=VUDnQ8
zzAD`@XF2kMa-ig2|L}@ZXnEd#55$hmSb-Eb94_R#F)e$~mrF-=7J||}-EDwto=5BV
z(@>4F9o)TK_mq+7&^^G=q_b!Pw>z{bdytoFwz*-|2i#t|w6CiM1>&n(ty;uYJ>B|J
zo-2D)=g|7(mekuj*PYa+FI;?Y?<TJW?5WlBx4nwQ9zEVaQ!BL`+3?|ZmoN)p(gmAy
za-qI^{!i^7Wsf9v&MrcS=%O5;j(LnLSEHt1n;}4UQh^*Lman+HmL3@ICewtH<hHN_
zot!+O$lY-hIONYJUZj_9t8bjVVQe=SL!_rq+%yWjXf-9Fal-(&obQ{g>m$GyHpd4!
zs8LYP+3sQ97Ti9wZ8EBlt>Y!?Wc-e?sF_-A`zCc*@%owZ=Gc$;F5JxSEfX6CcBbj%
zX4aMfHh9T1zhs#$)-h8*!f3^EQsTj+7A1r2%TSUp5RUm`OUP~y8)=%_VbAXSr1NKd
zLcAGOvhAKkqAGE!d0$ZRxF(qs4tPd&%2Hi$6X>+@%pj4;$y;L1T9T4&yfsf={<DuA
f^!SEh&&~11OzZ)TnO@Lo(9Oy&dvfj3zPbMc=BAwD

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/KingBalloon_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/KingBalloon_MiST.sv
deleted file mode 100644
index b6867af1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/KingBalloon_MiST.sv	
+++ /dev/null
@@ -1,194 +0,0 @@
-//============================================================================
-//  Arcade: King & Balloon
-//
-//  Port to MiST
-//  Copyright (C) 2018 Gehstock
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module KingBalloon_MiST(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"King and Ball.;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T5,Reset;",
-
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b, audio_c;
-wire [10:0] audio = {audio_c, 3'b0} + {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-kingballoon kingballoon(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[5] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_down,m_up,m_left,m_right}),
-	.P2_CSJUDLR({status[1],btn_two_players,m_fire,m_down,m_up,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),	
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b),
-	.W_SDAT_C(audio_c)
-);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-//wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-//reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 	
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/sound.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/sound.vhd
deleted file mode 100644
index 39532f82..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ROM/sound.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity sound is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of sound is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"21",X"FF",X"FF",X"2D",X"20",X"FD",X"25",X"20",X"FA",X"DB",X"00",X"FE",X"F0",X"28",X"FA",X"3E",
-		X"10",X"3D",X"20",X"FD",X"DB",X"00",X"FE",X"F0",X"28",X"EF",X"FE",X"F1",X"20",X"25",X"21",X"80",
-		X"01",X"01",X"4F",X"06",X"DD",X"21",X"2A",X"00",X"18",X"4C",X"06",X"02",X"21",X"FF",X"FF",X"2D",
-		X"20",X"FD",X"25",X"20",X"05",X"05",X"20",X"02",X"18",X"CF",X"DB",X"00",X"FE",X"F1",X"28",X"EF",
-		X"C3",X"09",X"00",X"FE",X"F2",X"C2",X"5B",X"00",X"21",X"50",X"06",X"01",X"8F",X"10",X"DD",X"21",
-		X"55",X"00",X"C3",X"76",X"00",X"DB",X"00",X"FE",X"F2",X"28",X"FA",X"FE",X"F3",X"C2",X"09",X"00",
-		X"21",X"90",X"10",X"01",X"FF",X"17",X"DD",X"21",X"6D",X"00",X"C3",X"76",X"00",X"DB",X"00",X"FE",
-		X"F3",X"28",X"FA",X"C3",X"09",X"00",X"50",X"59",X"7E",X"E6",X"F0",X"D3",X"00",X"3E",X"1B",X"3D",
-		X"20",X"FD",X"7E",X"E6",X"0F",X"07",X"07",X"07",X"07",X"D3",X"00",X"3E",X"19",X"3D",X"20",X"FD",
-		X"23",X"EB",X"ED",X"52",X"EB",X"20",X"DF",X"DD",X"E9",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",X"3A",X"00",
-		X"88",X"89",X"88",X"88",X"88",X"88",X"88",X"98",X"99",X"99",X"88",X"98",X"88",X"88",X"88",X"88",
-		X"89",X"99",X"98",X"98",X"88",X"88",X"87",X"88",X"87",X"78",X"9A",X"AA",X"89",X"88",X"98",X"87",
-		X"78",X"78",X"77",X"8B",X"CB",X"87",X"88",X"A8",X"87",X"78",X"87",X"78",X"AC",X"C9",X"87",X"89",
-		X"88",X"77",X"87",X"68",X"AD",X"C9",X"87",X"89",X"87",X"67",X"76",X"9C",X"CA",X"77",X"89",X"86",
-		X"67",X"77",X"AD",X"C9",X"56",X"99",X"96",X"55",X"6E",X"EC",X"85",X"79",X"87",X"67",X"65",X"EE",
-		X"C8",X"37",X"9A",X"75",X"76",X"8F",X"CB",X"53",X"88",X"95",X"56",X"4F",X"FA",X"A1",X"89",X"87",
-		X"45",X"4D",X"F8",X"B2",X"5B",X"78",X"45",X"5E",X"F7",X"83",X"5C",X"76",X"65",X"5F",X"F8",X"70",
-		X"8A",X"94",X"56",X"6F",X"C8",X"50",X"C7",X"83",X"37",X"DF",X"F8",X"05",X"E7",X"71",X"48",X"FF",
-		X"63",X"0D",X"8A",X"51",X"3F",X"F6",X"A0",X"89",X"68",X"32",X"EF",X"4C",X"05",X"B5",X"73",X"3B",
-		X"FA",X"D2",X"4D",X"4A",X"41",X"BF",X"FD",X"32",X"F4",X"98",X"0D",X"F0",X"F1",X"3D",X"3C",X"51",
-		X"FF",X"3D",X"06",X"94",X"F6",X"0F",X"F9",X"A0",X"A5",X"7F",X"36",X"FF",X"F2",X"5B",X"29",X"F0",
-		X"FC",X"0F",X"0E",X"24",X"FA",X"3F",X"FC",X"A0",X"D0",X"5F",X"0F",X"F0",X"F0",X"86",X"3A",X"F4",
-		X"FF",X"8A",X"0D",X"26",X"D5",X"F8",X"4E",X"0A",X"46",X"A3",X"FA",X"2E",X"3A",X"83",X"E8",X"CF",
-		X"0C",X"65",X"C3",X"BA",X"8F",X"07",X"61",X"B8",X"9D",X"6F",X"07",X"80",X"94",X"9E",X"8F",X"14",
-		X"A0",X"C3",X"8B",X"5F",X"F6",X"80",X"F5",X"A8",X"0F",X"F6",X"E0",X"D7",X"6F",X"0F",X"F1",X"F0",
-		X"A8",X"5C",X"2F",X"F1",X"E0",X"8C",X"6C",X"0F",X"F1",X"C0",X"AC",X"8B",X"0F",X"F4",X"A0",X"8B",
-		X"CB",X"0F",X"F3",X"F0",X"98",X"9E",X"0F",X"F0",X"F0",X"BE",X"3D",X"0F",X"F0",X"F0",X"9F",X"27",
-		X"2F",X"F0",X"E0",X"CF",X"A4",X"3F",X"F0",X"E0",X"AF",X"67",X"9F",X"F1",X"D0",X"6F",X"64",X"FF",
-		X"F4",X"A0",X"BF",X"20",X"FF",X"07",X"42",X"CF",X"70",X"FF",X"0D",X"20",X"EE",X"70",X"FF",X"00",
-		X"25",X"FB",X"43",X"FF",X"00",X"07",X"FD",X"31",X"FF",X"09",X"08",X"FB",X"45",X"FF",X"0F",X"00",
-		X"F9",X"18",X"FF",X"0F",X"00",X"F2",X"37",X"FF",X"0F",X"06",X"F7",X"0C",X"FF",X"5F",X"0A",X"F4",
-		X"0F",X"FF",X"0F",X"0F",X"F4",X"0F",X"FF",X"5D",X"0F",X"E7",X"0F",X"FF",X"2F",X"00",X"F3",X"0F",
-		X"FF",X"7F",X"00",X"D0",X"0F",X"F0",X"0E",X"0D",X"F0",X"0F",X"F0",X"0C",X"0F",X"F0",X"0F",X"F0",
-		X"0A",X"0F",X"C3",X"0F",X"F0",X"08",X"0F",X"F0",X"0F",X"F0",X"06",X"0F",X"F0",X"3F",X"F0",X"00",
-		X"0F",X"A0",X"7F",X"F0",X"00",X"0F",X"F0",X"FF",X"F0",X"00",X"5F",X"60",X"FF",X"F0",X"40",X"0F",
-		X"F0",X"FF",X"F0",X"F0",X"EF",X"00",X"FF",X"00",X"F0",X"0F",X"00",X"FF",X"00",X"F0",X"FF",X"05",
-		X"FF",X"00",X"40",X"FF",X"07",X"FF",X"00",X"A0",X"FF",X"00",X"FF",X"00",X"01",X"F1",X"0F",X"FF",
-		X"00",X"01",X"FF",X"00",X"FF",X"0F",X"06",X"F3",X"0F",X"FF",X"0F",X"00",X"F0",X"0F",X"FF",X"0F",
-		X"FB",X"F0",X"0F",X"F0",X"0F",X"00",X"F0",X"0F",X"F0",X"0F",X"0F",X"F0",X"1F",X"F0",X"0D",X"0F",
-		X"E0",X"5F",X"F0",X"0F",X"00",X"F0",X"0F",X"F0",X"0F",X"0F",X"F0",X"AF",X"F0",X"0F",X"0F",X"90",
-		X"0F",X"F0",X"0E",X"0F",X"A0",X"0F",X"F0",X"0E",X"0F",X"E0",X"0F",X"F0",X"04",X"0F",X"E0",X"FF",
-		X"F0",X"0D",X"0E",X"F0",X"BF",X"F0",X"0C",X"2F",X"F0",X"5F",X"F0",X"87",X"1C",X"F0",X"AF",X"F0",
-		X"CD",X"2B",X"C0",X"3F",X"F0",X"08",X"AB",X"E2",X"1F",X"F6",X"61",X"1E",X"F2",X"6F",X"B0",X"5A",
-		X"4A",X"F1",X"1F",X"F6",X"02",X"DE",X"B4",X"4F",X"FC",X"30",X"4D",X"E4",X"7F",X"F7",X"03",X"8A",
-		X"B8",X"48",X"FF",X"00",X"5F",X"C7",X"76",X"FE",X"33",X"49",X"C8",X"74",X"FF",X"60",X"0D",X"DB",
-		X"83",X"BF",X"96",X"27",X"7A",X"A6",X"FF",X"50",X"3C",X"BA",X"64",X"9F",X"FC",X"00",X"8F",X"D3",
-		X"AE",X"88",X"57",X"68",X"96",X"8D",X"FD",X"10",X"6F",X"B5",X"93",X"9F",X"F0",X"0A",X"F8",X"88",
-		X"CF",X"80",X"2B",X"C4",X"88",X"9F",X"F0",X"0C",X"E5",X"75",X"3F",X"F8",X"01",X"AA",X"B8",X"7F",
-		X"F1",X"0A",X"C6",X"78",X"6F",X"F7",X"06",X"A8",X"77",X"6A",X"FF",X"30",X"16",X"B9",X"7D",X"FD",
-		X"21",X"57",X"88",X"8C",X"FD",X"66",X"26",X"96",X"8A",X"BE",X"E8",X"03",X"88",X"77",X"DF",X"F9",
-		X"02",X"55",X"6A",X"BF",X"FD",X"22",X"55",X"58",X"9C",X"FF",X"63",X"44",X"56",X"6C",X"FF",X"74",
-		X"66",X"45",X"56",X"FF",X"BA",X"95",X"56",X"33",X"DD",X"9A",X"C9",X"69",X"42",X"BD",X"86",X"AC",
-		X"9A",X"75",X"AA",X"64",X"8A",X"8B",X"A5",X"BB",X"85",X"77",X"59",X"A7",X"BD",X"A7",X"89",X"57",
-		X"86",X"AA",X"87",X"B9",X"79",X"A7",X"79",X"75",X"98",X"7A",X"A9",X"9A",X"98",X"A7",X"67",X"79",
-		X"9A",X"97",X"BA",X"89",X"89",X"88",X"66",X"A8",X"8A",X"AB",X"99",X"75",X"A8",X"68",X"9B",X"AA",
-		X"87",X"B8",X"66",X"79",X"8A",X"87",X"BA",X"88",X"99",X"69",X"85",X"99",X"99",X"BC",X"79",X"85",
-		X"88",X"86",X"8B",X"9C",X"95",X"88",X"87",X"99",X"6A",X"A8",X"77",X"87",X"AB",X"8A",X"97",X"77",
-		X"76",X"8A",X"8C",X"BA",X"77",X"96",X"78",X"69",X"9A",X"A8",X"87",X"99",X"79",X"AA",X"78",X"86",
-		X"79",X"88",X"AB",X"89",X"A9",X"97",X"77",X"88",X"78",X"97",X"AB",X"97",X"9B",X"88",X"86",X"67",
-		X"88",X"9A",X"99",X"A8",X"89",X"98",X"99",X"79",X"A7",X"68",X"86",X"8A",X"9A",X"CA",X"98",X"86",
-		X"78",X"78",X"A9",X"78",X"98",X"AA",X"77",X"A9",X"88",X"87",X"78",X"68",X"BA",X"99",X"87",X"89",
-		X"67",X"AA",X"A9",X"87",X"79",X"88",X"A9",X"99",X"77",X"88",X"67",X"AA",X"AA",X"97",X"77",X"66",
-		X"8A",X"BB",X"98",X"87",X"67",X"89",X"BB",X"98",X"87",X"67",X"78",X"AB",X"AA",X"A8",X"67",X"67",
-		X"99",X"AA",X"A9",X"78",X"67",X"89",X"99",X"A9",X"89",X"77",X"88",X"88",X"A8",X"89",X"88",X"99",
-		X"89",X"98",X"79",X"87",X"88",X"9A",X"A8",X"79",X"88",X"88",X"89",X"A8",X"78",X"88",X"99",X"89",
-		X"A8",X"89",X"88",X"88",X"89",X"A9",X"89",X"98",X"77",X"78",X"A9",X"89",X"99",X"98",X"78",X"88",
-		X"89",X"98",X"98",X"88",X"88",X"89",X"99",X"98",X"89",X"97",X"79",X"99",X"98",X"89",X"88",X"88",
-		X"89",X"97",X"88",X"87",X"8A",X"98",X"99",X"88",X"87",X"89",X"98",X"98",X"99",X"87",X"89",X"98",
-		X"88",X"88",X"87",X"89",X"A9",X"A9",X"88",X"66",X"69",X"99",X"9A",X"98",X"76",X"69",X"99",X"89",
-		X"A8",X"97",X"7A",X"8A",X"78",X"77",X"98",X"89",X"A9",X"9A",X"88",X"98",X"79",X"87",X"88",X"88",
-		X"A9",X"87",X"88",X"89",X"99",X"99",X"78",X"78",X"89",X"99",X"A9",X"88",X"87",X"89",X"98",X"99",
-		X"88",X"88",X"8A",X"99",X"99",X"88",X"77",X"78",X"89",X"A9",X"89",X"88",X"88",X"88",X"99",X"89",
-		X"88",X"88",X"88",X"99",X"88",X"88",X"88",X"88",X"98",X"89",X"98",X"89",X"89",X"99",X"89",X"97",
-		X"88",X"89",X"AA",X"9A",X"98",X"88",X"88",X"98",X"89",X"98",X"89",X"88",X"98",X"89",X"98",X"89",
-		X"88",X"88",X"89",X"98",X"88",X"77",X"88",X"88",X"98",X"78",X"87",X"88",X"78",X"99",X"89",X"98",
-		X"89",X"88",X"99",X"88",X"99",X"99",X"99",X"99",X"88",X"87",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"98",X"89",X"88",X"98",X"78",X"88",X"88",X"88",X"77",X"77",X"88",X"79",X"98",X"99",X"99",X"AA",
-		X"9A",X"AA",X"AA",X"AA",X"A9",X"99",X"98",X"98",X"88",X"88",X"78",X"87",X"78",X"78",X"88",X"78",
-		X"98",X"89",X"99",X"AA",X"AB",X"BA",X"AA",X"AA",X"AA",X"AA",X"A9",X"99",X"88",X"87",X"66",X"54",
-		X"45",X"34",X"43",X"34",X"44",X"56",X"67",X"89",X"9A",X"BB",X"BB",X"BB",X"AA",X"AB",X"A9",X"99",
-		X"99",X"99",X"89",X"98",X"77",X"88",X"88",X"99",X"AA",X"AA",X"AA",X"AA",X"AA",X"BA",X"AA",X"AA",
-		X"A9",X"AA",X"A9",X"99",X"99",X"87",X"78",X"87",X"66",X"66",X"66",X"66",X"66",X"66",X"67",X"78",
-		X"88",X"88",X"88",X"99",X"99",X"99",X"99",X"88",X"89",X"88",X"88",X"89",X"88",X"88",X"88",X"99",
-		X"9A",X"AA",X"AA",X"AA",X"AA",X"9A",X"A9",X"99",X"98",X"88",X"77",X"77",X"76",X"66",X"66",X"66",
-		X"66",X"77",X"77",X"88",X"88",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"99",X"AA",X"AA",
-		X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"99",X"98",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"78",X"87",X"88",X"77",X"77",X"77",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"9A",X"AB",X"A9",X"88",X"78",X"89",X"99",X"98",X"87",X"77",
-		X"78",X"88",X"87",X"77",X"77",X"76",X"8C",X"BD",X"C9",X"87",X"67",X"89",X"AA",X"99",X"77",X"77",
-		X"89",X"99",X"98",X"88",X"88",X"88",X"88",X"87",X"77",X"77",X"79",X"DD",X"DC",X"87",X"66",X"8A",
-		X"AA",X"98",X"87",X"78",X"89",X"99",X"98",X"88",X"88",X"88",X"87",X"77",X"77",X"66",X"9D",X"DC",
-		X"C7",X"66",X"69",X"BB",X"A9",X"77",X"67",X"89",X"9A",X"98",X"87",X"77",X"78",X"87",X"66",X"66",
-		X"7B",X"FB",X"E8",X"56",X"78",X"CB",X"B9",X"66",X"77",X"9A",X"9A",X"A9",X"87",X"67",X"78",X"87",
-		X"55",X"58",X"EF",X"BD",X"66",X"78",X"AB",X"98",X"87",X"98",X"98",X"88",X"A8",X"98",X"77",X"66",
-		X"55",X"56",X"8F",X"CB",X"A4",X"7A",X"8D",X"B8",X"86",X"6A",X"88",X"9A",X"89",X"76",X"65",X"66",
-		X"65",X"8C",X"F7",X"E4",X"69",X"7C",X"C8",X"98",X"6C",X"7A",X"A6",X"97",X"77",X"55",X"45",X"7B",
-		X"F8",X"D5",X"28",X"79",X"E8",X"BA",X"6A",X"87",X"86",X"88",X"66",X"44",X"49",X"FF",X"9D",X"06",
-		X"67",X"DA",X"BB",X"8A",X"85",X"93",X"85",X"57",X"36",X"9F",X"FB",X"C1",X"66",X"6D",X"9C",X"A7",
-		X"B7",X"78",X"56",X"44",X"46",X"CF",X"CD",X"71",X"85",X"9D",X"DE",X"97",X"63",X"84",X"75",X"35",
-		X"5C",X"F8",X"F5",X"5A",X"3B",X"BB",X"E6",X"A4",X"57",X"43",X"12",X"7D",X"F9",X"F4",X"5A",X"4D",
-		X"AA",X"C9",X"96",X"75",X"31",X"05",X"BF",X"D9",X"80",X"B5",X"DF",X"8D",X"89",X"45",X"43",X"21",
-		X"7F",X"FF",X"F0",X"B5",X"7F",X"4E",X"79",X"93",X"70",X"00",X"4E",X"FF",X"F0",X"84",X"8F",X"4F",
-		X"4B",X"64",X"60",X"30",X"9F",X"FF",X"90",X"C0",X"F6",X"BD",X"4C",X"09",X"02",X"46",X"FF",X"F9",
-		X"0A",X"0F",X"7E",X"A6",X"70",X"80",X"33",X"CF",X"BF",X"09",X"1B",X"98",X"D6",X"A1",X"52",X"36",
-		X"FE",X"FE",X"3A",X"49",X"99",X"D6",X"50",X"11",X"5F",X"FF",X"F9",X"C1",X"82",X"A8",X"79",X"18",
-		X"0E",X"9E",X"CC",X"CA",X"86",X"A6",X"62",X"37",X"6E",X"F8",X"F4",X"B5",X"8B",X"6D",X"25",X"16",
-		X"CE",X"DF",X"5C",X"2A",X"56",X"72",X"87",X"DF",X"8F",X"0D",X"0E",X"58",X"40",X"A6",X"F7",X"F1",
-		X"B3",X"97",X"46",X"0D",X"7F",X"AF",X"17",X"29",X"56",X"53",X"DB",X"F9",X"F0",X"72",X"87",X"45",
-		X"6A",X"FE",X"F3",X"80",X"93",X"63",X"AA",X"FF",X"F5",X"52",X"36",X"59",X"9E",X"FE",X"B7",X"61",
-		X"31",X"5A",X"FF",X"FC",X"54",X"23",X"33",X"8C",X"FF",X"FA",X"63",X"22",X"25",X"AE",X"FE",X"D6",
-		X"71",X"31",X"4A",X"CF",X"EF",X"59",X"04",X"02",X"AA",X"FD",X"F7",X"92",X"10",X"19",X"AF",X"CF",
-		X"6B",X"03",X"12",X"A9",X"FC",X"F5",X"90",X"31",X"3A",X"BF",X"DF",X"69",X"12",X"02",X"9B",X"FD",
-		X"F7",X"A1",X"30",X"57",X"DF",X"FF",X"8A",X"03",X"05",X"8E",X"FF",X"D9",X"60",X"10",X"78",X"FF",
-		X"F9",X"A3",X"20",X"09",X"9F",X"DF",X"5B",X"03",X"02",X"7C",X"06",X"F8",X"90",X"20",X"06",X"EF",
-		X"FF",X"97",X"01",X"05",X"8F",X"FF",X"DB",X"30",X"00",X"68",X"FF",X"FB",X"C2",X"30",X"36",X"AF",
-		X"FE",X"C8",X"42",X"03",X"5D",X"DF",X"CF",X"55",X"02",X"37",X"ED",X"FC",X"E3",X"30",X"14",X"BF",
-		X"FF",X"E8",X"50",X"00",X"5D",X"EF",X"CF",X"45",X"01",X"27",X"EE",X"FC",X"C4",X"40",X"14",X"AF",
-		X"FF",X"F6",X"60",X"11",X"6C",X"EF",X"EC",X"63",X"11",X"39",X"DF",X"FF",X"67",X"02",X"07",X"CF",
-		X"FF",X"C5",X"30",X"13",X"9C",X"FE",X"F5",X"60",X"11",X"7D",X"FF",X"FB",X"61",X"00",X"4A",X"EF",
-		X"FF",X"44",X"01",X"38",X"DF",X"FF",X"85",X"00",X"06",X"CF",X"FF",X"E4",X"20",X"02",X"9F",X"FF",
-		X"F7",X"60",X"00",X"6C",X"FF",X"FE",X"52",X"00",X"27",X"FF",X"FF",X"77",X"00",X"05",X"CF",X"FF",
-		X"E6",X"10",X"03",X"8F",X"FF",X"F6",X"50",X"00",X"5C",X"FF",X"FB",X"60",X"00",X"5A",X"FF",X"FF",
-		X"45",X"01",X"27",X"DF",X"FF",X"85",X"00",X"05",X"BF",X"FF",X"F5",X"20",X"02",X"8E",X"FF",X"F9",
-		X"50",X"00",X"5B",X"FF",X"FF",X"62",X"00",X"37",X"EF",X"FF",X"85",X"00",X"05",X"BF",X"FF",X"E6",
-		X"20",X"02",X"7D",X"FF",X"FA",X"50",X"00",X"5B",X"FF",X"FD",X"71",X"00",X"37",X"EF",X"FF",X"95",
-		X"00",X"14",X"BE",X"FF",X"E7",X"10",X"03",X"7D",X"FF",X"FB",X"60",X"00",X"49",X"DF",X"FE",X"73",
-		X"01",X"36",X"CF",X"FF",X"B6",X"10",X"14",X"9D",X"FF",X"F9",X"41",X"03",X"5B",X"EF",X"FD",X"72",
-		X"00",X"48",X"CF",X"FF",X"A5",X"10",X"25",X"AD",X"FF",X"D8",X"31",X"24",X"8C",X"FF",X"EA",X"41",
-		X"02",X"6B",X"FF",X"FB",X"62",X"01",X"59",X"EF",X"FD",X"73",X"01",X"38",X"DF",X"FF",X"93",X"00",
-		X"26",X"CF",X"FF",X"A4",X"10",X"26",X"AF",X"FF",X"C6",X"10",X"15",X"9E",X"FF",X"D7",X"20",X"14",
-		X"8D",X"FF",X"E9",X"30",X"13",X"7C",X"FF",X"FA",X"41",X"02",X"6B",X"FF",X"FB",X"51",X"02",X"5A",
-		X"FF",X"FC",X"72",X"01",X"5A",X"EF",X"FC",X"73",X"12",X"59",X"DF",X"FC",X"83",X"11",X"48",X"DF",
-		X"FD",X"84",X"11",X"38",X"CF",X"FD",X"94",X"21",X"37",X"BF",X"FE",X"95",X"21",X"37",X"BE",X"FE",
-		X"A5",X"21",X"36",X"BE",X"FE",X"B6",X"31",X"36",X"AE",X"FF",X"B6",X"31",X"25",X"9D",X"FF",X"C8",
-		X"42",X"25",X"9D",X"FF",X"C8",X"42",X"24",X"8C",X"FF",X"D9",X"52",X"24",X"7B",X"EF",X"DA",X"52",
-		X"13",X"7B",X"EF",X"EA",X"62",X"13",X"6A",X"DF",X"EB",X"73",X"23",X"59",X"CF",X"FD",X"84",X"22",
-		X"48",X"CF",X"FE",X"A5",X"21",X"36",X"AE",X"FE",X"B7",X"31",X"25",X"9D",X"FF",X"D9",X"42",X"24",
-		X"7B",X"EF",X"EB",X"63",X"23",X"69",X"DF",X"FC",X"84",X"22",X"47",X"BE",X"FE",X"B7",X"32",X"35",
-		X"9C",X"EE",X"D9",X"53",X"24",X"7A",X"CE",X"EB",X"85",X"33",X"57",X"AC",X"DD",X"A8",X"54",X"46",
-		X"8A",X"CC",X"CA",X"75",X"55",X"78",X"AB",X"BB",X"A8",X"76",X"67",X"88",X"99",X"AA",X"98",X"87",
-		X"77",X"78",X"8A",X"AB",X"A8",X"76",X"66",X"78",X"9B",X"CB",X"A8",X"76",X"55",X"78",X"AC",X"CB",
-		X"97",X"65",X"56",X"7A",X"BC",X"CA",X"86",X"55",X"67",X"9A",X"BC",X"B9",X"75",X"56",X"78",X"AB",
-		X"BA",X"98",X"76",X"78",X"99",X"99",X"88",X"88",X"89",X"99",X"98",X"77",X"78",X"9A",X"AA",X"A8",
-		X"76",X"66",X"89",X"AB",X"BA",X"87",X"66",X"67",X"9A",X"BB",X"A9",X"87",X"66",X"78",X"9A",X"AA",
-		X"98",X"77",X"78",X"89",X"99",X"98",X"88",X"88",X"98",X"88",X"88",X"88",X"89",X"99",X"98",X"77",
-		X"77",X"89",X"9A",X"A9",X"87",X"77",X"88",X"9A",X"A9",X"98",X"77",X"78",X"9A",X"AA",X"98",X"77",
-		X"77",X"89",X"AA",X"A9",X"87",X"77",X"88",X"9A",X"A9",X"88",X"77",X"88",X"99",X"99",X"98",X"88",
-		X"88",X"89",X"99",X"98",X"88",X"88",X"89",X"99",X"98",X"88",X"88",X"89",X"99",X"98",X"88",X"88",
-		X"89",X"99",X"98",X"88",X"88",X"89",X"99",X"99",X"88",X"88",X"88",X"99",X"99",X"88",X"88",X"88",
-		X"99",X"99",X"98",X"88",X"88",X"88",X"88",X"88",X"88",X"99",X"99",X"88",X"87",X"88",X"89",X"99",
-		X"99",X"88",X"77",X"88",X"99",X"99",X"98",X"77",X"78",X"89",X"99",X"98",X"87",X"77",X"88",X"99",
-		X"99",X"88",X"88",X"88",X"99",X"99",X"98",X"88",X"88",X"89",X"99",X"98",X"88",X"88",X"89",X"99",
-		X"98",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"99",X"88",X"88",
-		X"88",X"88",X"99",X"99",X"98",X"88",X"88",X"88",X"99",X"98",X"88",X"88",X"88",X"88",X"99",X"99",
-		X"88",X"88",X"88",X"88",X"99",X"98",X"88",X"88",X"88",X"89",X"99",X"98",X"88",X"88",X"88",X"89",
-		X"98",X"88",X"88",X"88",X"88",X"89",X"98",X"88",X"88",X"88",X"88",X"88",X"89",X"99",X"98",X"88",
-		X"88",X"88",X"99",X"99",X"88",X"88",X"88",X"89",X"99",X"99",X"88",X"88",X"88",X"99",X"99",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"89",X"88",X"88",X"88",
-		X"88",X"99",X"98",X"88",X"88",X"88",X"88",X"99",X"88",X"88",X"88",X"88",X"99",X"98",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"89",X"99",X"88",X"88",X"88",X"88",X"98",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"99",X"99",X"88",X"88",X"88",X"88",X"99",X"99",X"88",
-		X"88",X"88",X"89",X"99",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"89",X"88",X"88",X"88",X"88",X"88",X"98",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"89",X"89",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"98",X"88",X"89",X"98",X"89",X"88",
-		X"88",X"89",X"89",X"89",X"99",X"87",X"88",X"89",X"88",X"88",X"89",X"89",X"88",X"88",X"89",X"99",
-		X"88",X"88",X"88",X"88",X"98",X"88",X"98",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"89",X"99",
-		X"98",X"88",X"88",X"89",X"89",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"99",X"99",X"98",X"88",X"98",X"98",X"88",X"88",X"88",X"99",X"99",X"99",X"99",X"98",
-		X"88",X"77",X"77",X"78",X"89",X"9A",X"AA",X"AA",X"99",X"87",X"77",X"66",X"77",X"88",X"9A",X"AA",
-		X"AA",X"A9",X"88",X"77",X"66",X"67",X"78",X"89",X"AA",X"BB",X"AA",X"99",X"87",X"66",X"66",X"67",
-		X"78",X"9A",X"AB",X"BB",X"A9",X"87",X"76",X"66",X"66",X"78",X"89",X"AB",X"BB",X"BB",X"A9",X"87",
-		X"66",X"66",X"67",X"78",X"9A",X"AB",X"BB",X"BA",X"98",X"77",X"66",X"66",X"67",X"77",X"99",X"AA",
-		X"BB",X"BA",X"A9",X"87",X"76",X"66",X"67",X"78",X"89",X"AB",X"BB",X"BA",X"A8",X"97",X"87",X"87",
-		X"88",X"88",X"77",X"77",X"78",X"89",X"AA",X"AA",X"A9",X"99",X"98",X"88",X"87",X"66",X"66",X"68",
-		X"8A",X"BB",X"CB",X"B9",X"A8",X"97",X"87",X"87",X"77",X"66",X"67",X"79",X"9B",X"AC",X"BB",X"A9",
-		X"88",X"87",X"87",X"87",X"76",X"76",X"77",X"99",X"BB",X"CB",X"BA",X"99",X"78",X"78",X"78",X"78",
-		X"77",X"77",X"78",X"99",X"BA",X"CA",X"B9",X"98",X"87",X"88",X"78",X"78",X"77",X"67",X"78",X"9A",
-		X"BB",X"CA",X"B9",X"A7",X"87",X"87",X"88",X"88",X"77",X"67",X"78",X"99",X"BA",X"CA",X"B8",X"97",
-		X"87",X"87",X"88",X"78",X"77",X"66",X"77",X"99",X"CB",X"DA",X"C9",X"97",X"87",X"78",X"78",X"78",
-		X"67",X"66",X"77",X"A8",X"CA",X"DA",X"B9",X"88",X"77",X"68",X"79",X"79",X"77",X"66",X"76",X"99",
-		X"BC",X"CD",X"AB",X"79",X"68",X"68",X"88",X"88",X"87",X"75",X"57",X"6A",X"9D",X"BD",X"BB",X"97",
-		X"86",X"86",X"87",X"98",X"88",X"66",X"56",X"77",X"B9",X"EA",X"E9",X"B8",X"77",X"68",X"69",X"79",
-		X"89",X"86",X"65",X"67",X"7A",X"9D",X"AD",X"AA",X"97",X"86",X"86",X"87",X"98",X"88",X"66",X"56",
-		X"77",X"9A",X"BD",X"BD",X"9B",X"69",X"67",X"77",X"88",X"98",X"97",X"76",X"56",X"87",X"BA",X"EB",
-		X"DB",X"A9",X"68",X"57",X"68",X"88",X"A8",X"96",X"85",X"65",X"87",X"B9",X"EB",X"DB",X"A9",X"68",
-		X"47",X"68",X"89",X"A9",X"A7",X"75",X"54",X"86",X"BA",X"EC",X"CD",X"8A",X"47",X"47",X"77",X"A8",
-		X"B9",X"A7",X"75",X"44",X"57",X"8D",X"AF",X"AF",X"9A",X"65",X"65",X"77",X"8A",X"9C",X"9A",X"77",
-		X"54",X"46",X"78",X"DA",X"FB",X"F9",X"A6",X"56",X"47",X"88",X"B9",X"C9",X"A7",X"65",X"33",X"37",
-		X"6D",X"BF",X"ED",X"D7",X"A2",X"63",X"67",X"8B",X"BC",X"C9",X"95",X"63",X"33",X"48",X"8F",X"CF",
-		X"DE",X"A7",X"72",X"43",X"68",X"AC",X"CC",X"C9",X"84",X"52",X"22",X"59",X"9F",X"DF",X"FD",X"C4",
-		X"70",X"42",X"78",X"CB",X"FC",X"D8",X"85",X"33",X"12",X"47",X"AC",X"FD",X"FA",X"E5",X"52",X"14",
-		X"59",X"BE",X"EF",X"BB",X"66",X"23",X"22",X"35",X"9B",X"EF",X"DF",X"8D",X"36",X"23",X"56",X"AC",
-		X"DE",X"DB",X"96",X"53",X"34",X"34",X"58",X"BA",X"FB",X"FA",X"C8",X"55",X"24",X"68",X"CC",X"EE",
-		X"CB",X"76",X"44",X"44",X"35",X"4B",X"8F",X"FD",X"F9",X"D5",X"54",X"24",X"68",X"DC",X"FD",X"BB",
-		X"67",X"34",X"44",X"34",X"3A",X"7E",X"FD",X"F9",X"D7",X"44",X"24",X"67",X"CE",X"DF",X"BC",X"76",
-		X"43",X"44",X"44",X"46",X"B9",X"FE",X"EF",X"9C",X"54",X"43",X"59",X"8E",X"DD",X"F8",X"B4",X"54",
-		X"35",X"65",X"64",X"7A",X"8E",X"ED",X"F9",X"C6",X"55",X"45",X"88",X"CE",X"BE",X"8A",X"65",X"54",
-		X"57",X"56",X"44",X"98",X"AF",X"BF",X"E9",X"C3",X"64",X"56",X"98",X"EB",X"CB",X"79",X"57",X"56",
-		X"67",X"45",X"25",X"88",X"EF",X"FF",X"CB",X"85",X"44",X"37",X"7A",X"CB",X"DB",X"A8",X"76",X"66",
-		X"55",X"33",X"25",X"99",X"FF",X"FF",X"DB",X"75",X"34",X"36",X"8A",X"DD",X"DC",X"A9",X"76",X"55",
-		X"45",X"44",X"34",X"9A",X"EF",X"FF",X"DB",X"75",X"23",X"35",X"9A",X"DD",X"DD",X"A9",X"76",X"45",
-		X"55",X"54",X"54",X"8B",X"CF",X"FF",X"FB",X"87",X"33",X"44",X"79",X"AE",X"CC",X"C8",X"86",X"54",
-		X"55",X"65",X"55",X"59",X"AC",X"FF",X"EF",X"A9",X"64",X"34",X"47",X"AA",X"ED",X"DC",X"97",X"64",
-		X"46",X"57",X"66",X"55",X"7A",X"AE",X"FE",X"FB",X"97",X"43",X"44",X"69",X"AD",X"ED",X"CA",X"76",
-		X"54",X"56",X"67",X"66",X"55",X"8A",X"BF",X"FE",X"FA",X"85",X"32",X"44",X"8A",X"BE",X"EC",X"B8",
-		X"65",X"55",X"68",X"78",X"75",X"44",X"8A",X"BF",X"FF",X"FB",X"85",X"31",X"43",X"8A",X"CE",X"FC",
-		X"B9",X"56",X"45",X"68",X"79",X"76",X"54",X"5A",X"9D",X"FD",X"FC",X"A5",X"50",X"35",X"6B",X"CD",
-		X"DE",X"9A",X"65",X"56",X"78",X"98",X"96",X"53",X"24",X"99",X"EF",X"EF",X"D9",X"56",X"13",X"56",
-		X"AC",X"EC",X"EA",X"97",X"65",X"77",X"79",X"78",X"75",X"33",X"26",X"AB",X"FF",X"FF",X"D7",X"64",
-		X"14",X"58",X"AD",X"CD",X"CA",X"88",X"66",X"77",X"88",X"77",X"64",X"32",X"26",X"BD",X"FF",X"FF",
-		X"C7",X"32",X"01",X"57",X"BE",X"FE",X"EB",X"86",X"54",X"56",X"78",X"88",X"76",X"53",X"24",X"9D",
-		X"FF",X"FF",X"E9",X"41",X"10",X"36",X"BD",X"FF",X"DB",X"85",X"34",X"46",X"8A",X"AA",X"96",X"54",
-		X"22",X"49",X"EF",X"FF",X"FC",X"73",X"01",X"05",X"9E",X"FF",X"FB",X"95",X"52",X"56",X"8A",X"BA",
-		X"88",X"55",X"44",X"35",X"7C",X"FF",X"FF",X"D8",X"62",X"13",X"48",X"AF",X"EF",X"C9",X"65",X"54",
-		X"68",X"AA",X"BA",X"87",X"54",X"45",X"45",X"69",X"DE",X"FF",X"EC",X"87",X"43",X"56",X"8A",X"CB",
-		X"B9",X"85",X"56",X"78",X"AB",X"AA",X"97",X"55",X"55",X"56",X"66",X"8B",X"EE",X"FF",X"DA",X"76",
-		X"23",X"35",X"7A",X"CC",X"DB",X"A7",X"76",X"76",X"89",X"99",X"98",X"77",X"76",X"67",X"65",X"79",
-		X"DE",X"FF",X"C9",X"65",X"23",X"47",X"AC",X"FE",X"C9",X"84",X"34",X"57",X"9C",X"CC",X"A9",X"76",
-		X"65",X"55",X"66",X"56",X"8C",X"DE",X"FE",X"C9",X"74",X"33",X"67",X"9B",X"CC",X"BA",X"86",X"56",
-		X"78",X"AA",X"BA",X"97",X"66",X"66",X"67",X"77",X"67",X"9E",X"EE",X"FD",X"95",X"53",X"34",X"8B",
-		X"CE",X"EC",X"87",X"54",X"35",X"79",X"CC",X"CA",X"97",X"66",X"66",X"67",X"77",X"66",X"7A",X"DC",
-		X"ED",X"D8",X"76",X"55",X"6A",X"AB",X"BC",X"97",X"65",X"54",X"79",X"BD",X"DD",X"A9",X"65",X"44",
-		X"45",X"68",X"98",X"88",X"AD",X"CC",X"CD",X"97",X"66",X"55",X"89",X"AA",X"CB",X"98",X"77",X"67",
-		X"89",X"AA",X"BA",X"98",X"87",X"77",X"76",X"66",X"66",X"66",X"AD",X"DD",X"DD",X"97",X"65",X"55",
-		X"89",X"AA",X"BA",X"87",X"67",X"67",X"8A",X"BB",X"CB",X"96",X"65",X"55",X"67",X"78",X"88",X"76",
-		X"9C",X"CD",X"DE",X"A7",X"55",X"44",X"79",X"BB",X"CB",X"97",X"55",X"56",X"69",X"BC",X"CC",X"B8",
-		X"75",X"55",X"56",X"78",X"88",X"87",X"9C",X"DD",X"CD",X"B8",X"55",X"55",X"68",X"AB",X"BB",X"A8",
-		X"66",X"67",X"78",X"AB",X"BA",X"A8",X"76",X"66",X"66",X"78",X"87",X"77",X"79",X"CD",X"DC",X"DA",
-		X"85",X"56",X"67",X"8B",X"BB",X"A9",X"76",X"55",X"77",X"9B",X"DC",X"BA",X"87",X"55",X"56",X"67",
-		X"89",X"98",X"87",X"8B",X"CC",X"BC",X"B8",X"65",X"66",X"78",X"BC",X"BA",X"98",X"66",X"57",X"89",
-		X"9B",X"CB",X"A8",X"87",X"66",X"67",X"77",X"78",X"78",X"77",X"AC",X"DC",X"CC",X"A8",X"56",X"67",
-		X"78",X"BB",X"A8",X"87",X"76",X"78",X"99",X"9B",X"BA",X"87",X"77",X"66",X"78",X"88",X"78",X"87",
-		X"66",X"8C",X"DC",X"BC",X"B9",X"65",X"67",X"88",X"AB",X"A9",X"87",X"77",X"67",X"89",X"AA",X"AA",
-		X"A8",X"88",X"87",X"67",X"77",X"66",X"78",X"88",X"79",X"CD",X"CA",X"BA",X"96",X"56",X"78",X"79",
-		X"AA",X"98",X"88",X"87",X"77",X"88",X"89",X"9A",X"AA",X"99",X"87",X"66",X"66",X"66",X"78",X"99",
-		X"89",X"AB",X"BB",X"AA",X"98",X"66",X"77",X"88",X"9A",X"A9",X"88",X"88",X"77",X"89",X"99",X"99",
-		X"A9",X"99",X"98",X"87",X"76",X"66",X"66",X"78",X"9A",X"BC",X"CB",X"A9",X"87",X"66",X"68",X"99",
-		X"AA",X"A9",X"87",X"77",X"77",X"89",X"AA",X"99",X"98",X"88",X"99",X"88",X"77",X"66",X"67",X"78",
-		X"89",X"AB",X"CB",X"AA",X"98",X"77",X"78",X"89",X"9A",X"99",X"88",X"88",X"88",X"89",X"99",X"98",
-		X"88",X"88",X"88",X"99",X"99",X"87",X"76",X"66",X"77",X"89",X"AA",X"BB",X"B9",X"98",X"77",X"77",
-		X"89",X"9A",X"99",X"98",X"77",X"78",X"89",X"99",X"99",X"88",X"88",X"88",X"99",X"99",X"87",X"66",
-		X"77",X"78",X"99",X"9A",X"AA",X"A9",X"98",X"88",X"78",X"88",X"99",X"99",X"98",X"88",X"88",X"89",
-		X"99",X"99",X"88",X"88",X"88",X"99",X"99",X"88",X"87",X"77",X"78",X"88",X"88",X"99",X"9A",X"AA",
-		X"99",X"88",X"77",X"78",X"99",X"99",X"99",X"88",X"88",X"88",X"99",X"99",X"98",X"88",X"88",X"88",
-		X"89",X"99",X"99",X"98",X"87",X"77",X"77",X"78",X"89",X"99",X"AA",X"AA",X"98",X"87",X"77",X"78",
-		X"88",X"88",X"88",X"98",X"88",X"88",X"99",X"98",X"88",X"87",X"89",X"AA",X"A9",X"76",X"66",X"8C",
-		X"EC",X"96",X"44",X"68",X"DF",X"D8",X"63",X"46",X"8D",X"FC",X"76",X"43",X"7A",X"9D",X"D9",X"67",
-		X"44",X"8A",X"8D",X"D9",X"66",X"35",X"A9",X"BE",X"B6",X"65",X"48",X"B8",X"DC",X"96",X"64",X"69",
-		X"9A",X"EC",X"86",X"54",X"8B",X"8D",X"D8",X"56",X"46",X"A9",X"BE",X"A6",X"64",X"5A",X"A7",X"EB",
-		X"77",X"64",X"7B",X"7D",X"E8",X"57",X"37",X"C8",X"AF",X"95",X"74",X"4A",X"A9",X"FA",X"46",X"64",
-		X"BB",X"5F",X"D5",X"58",X"37",X"C6",X"EF",X"63",X"84",X"7D",X"6A",X"F9",X"37",X"56",X"B7",X"BF",
-		X"83",X"66",X"8D",X"59",X"F9",X"45",X"78",X"C5",X"BF",X"75",X"65",X"9C",X"3A",X"F7",X"47",X"6A",
-		X"C2",X"CF",X"63",X"84",X"AC",X"3D",X"F4",X"27",X"7B",X"A4",X"FE",X"42",X"68",X"BA",X"9F",X"93",
-		X"26",X"BD",X"4B",X"F8",X"33",X"5B",X"C6",X"FC",X"44",X"56",X"E7",X"5F",X"C4",X"35",X"7C",X"5C",
-		X"F7",X"46",X"4A",X"B2",X"FE",X"54",X"77",X"B5",X"7F",X"95",X"56",X"9B",X"2F",X"D5",X"47",X"9D",
-		X"55",X"F8",X"25",X"8A",X"B5",X"FA",X"43",X"69",X"E6",X"9F",X"73",X"47",X"DA",X"4F",X"A5",X"52",
-		X"5F",X"8E",X"E3",X"47",X"5B",X"78",X"F8",X"35",X"48",X"D5",X"FF",X"54",X"44",X"B9",X"CF",X"42",
-		X"87",X"97",X"7F",X"B3",X"45",X"6D",X"7F",X"C5",X"75",X"4A",X"6F",X"F4",X"17",X"88",X"47",X"FA",
-		X"35",X"48",X"B6",X"FC",X"55",X"78",X"93",X"FE",X"64",X"67",X"B5",X"CF",X"48",X"55",X"B9",X"6F",
-		X"64",X"57",X"9A",X"5F",X"91",X"64",X"6D",X"3F",X"F0",X"34",X"7C",X"58",X"F6",X"53",X"2A",X"A4",
-		X"F8",X"37",X"49",X"A1",X"FF",X"46",X"47",X"C5",X"AF",X"67",X"47",X"C6",X"5F",X"96",X"54",X"BB",
-		X"0F",X"F2",X"81",X"3F",X"82",X"F9",X"64",X"1C",X"D1",X"AF",X"7E",X"00",X"FE",X"1F",X"A7",X"D0",
-		X"4F",X"4A",X"F2",X"D0",X"0F",X"90",X"F8",X"CC",X"08",X"E3",X"FF",X"2F",X"00",X"F9",X"2F",X"8E",
-		X"D0",X"8B",X"5B",X"F2",X"F0",X"2E",X"83",X"F8",X"F6",X"0A",X"A6",X"FF",X"3F",X"02",X"EB",X"4F",
-		X"9E",X"A0",X"89",X"5F",X"F1",X"F0",X"0C",X"B5",X"FB",X"8E",X"08",X"95",X"BF",X"6E",X"60",X"9A",
-		X"5F",X"F3",X"F0",X"28",X"4E",X"F6",X"9B",X"0A",X"87",X"8F",X"8F",X"10",X"95",X"BF",X"F2",X"F1",
-		X"0B",X"8C",X"8D",X"AF",X"05",X"78",X"CF",X"99",X"60",X"DA",X"C5",X"C8",X"F0",X"08",X"4D",X"DF",
-		X"8C",X"07",X"8F",X"48",X"DC",X"D0",X"90",X"D5",X"FE",X"64",X"0A",X"DA",X"2F",X"5F",X"40",X"83",
-		X"6C",X"FF",X"C0",X"0F",X"79",X"DB",X"4F",X"07",X"60",X"BF",X"F3",X"F0",X"97",X"DA",X"D5",X"CB",
-		X"0F",X"0D",X"6F",X"9E",X"40",X"77",X"F3",X"F7",X"F3",X"37",X"4B",X"5F",X"5F",X"00",X"9B",X"87",
-		X"F3",X"F0",X"59",X"08",X"EF",X"7F",X"05",X"79",X"8C",X"F6",X"F0",X"84",X"28",X"EF",X"3F",X"03",
-		X"77",X"BB",X"F5",X"F1",X"55",X"1B",X"CF",X"BF",X"03",X"6B",X"A8",X"F5",X"F3",X"46",X"36",X"EF",
-		X"1F",X"02",X"3A",X"78",X"FB",X"E6",X"24",X"46",X"BF",X"7F",X"81",X"0D",X"09",X"FD",X"FA",X"03",
-		X"60",X"BF",X"FB",X"F0",X"29",X"07",X"CF",X"AF",X"35",X"33",X"49",X"FB",X"F8",X"40",X"32",X"9F",
-		X"FB",X"E4",X"16",X"06",X"CF",X"FF",X"61",X"30",X"99",X"ED",X"FA",X"64",X"26",X"3E",X"EE",X"B6",
-		X"36",X"66",X"D7",X"F8",X"B5",X"47",X"5B",X"CB",X"6A",X"76",X"88",X"69",X"A9",X"C8",X"57",X"88",
-		X"89",X"88",X"9B",X"79",X"A5",X"9A",X"88",X"A5",X"9A",X"87",X"87",X"9C",X"79",X"89",X"69",X"88",
-		X"88",X"A8",X"C6",X"77",X"6B",X"98",X"9A",X"5A",X"65",X"A9",X"B8",X"A5",X"B6",X"68",X"9B",X"7C",
-		X"89",X"77",X"49",X"E7",X"C7",X"88",X"95",X"7A",X"9D",X"99",X"76",X"55",X"BA",X"D9",X"B5",X"87",
-		X"27",X"AE",X"EB",X"54",X"86",X"67",X"DD",X"C7",X"77",X"43",X"7C",X"FD",X"A5",X"67",X"55",X"7D",
-		X"DC",X"D6",X"05",X"84",X"AE",X"DC",X"95",X"27",X"36",X"BF",X"FA",X"71",X"65",X"66",X"FD",X"FB",
-		X"51",X"27",X"5B",X"FF",X"B8",X"32",X"44",X"7D",X"FF",X"B3",X"23",X"65",X"9F",X"FF",X"84",X"03",
-		X"57",X"DF",X"F7",X"53",X"34",X"77",X"FF",X"D8",X"32",X"27",X"7B",X"FE",X"C7",X"30",X"69",X"5E",
-		X"FE",X"75",X"03",X"77",X"9F",X"FD",X"61",X"15",X"78",X"CF",X"CB",X"70",X"09",X"94",X"FF",X"E6",
-		X"20",X"38",X"B8",X"FF",X"D1",X"13",X"58",X"8D",X"FD",X"86",X"01",X"AA",X"6D",X"FC",X"83",X"03",
-		X"AA",X"5F",X"FA",X"42",X"16",X"A7",X"AF",X"F9",X"51",X"19",X"A7",X"AF",X"E7",X"41",X"2A",X"A4",
-		X"FF",X"B6",X"30",X"3D",X"A6",X"FF",X"85",X"30",X"5C",X"97",X"FF",X"62",X"02",X"9C",X"7B",X"FB",
-		X"46",X"00",X"DD",X"6C",X"F8",X"44",X"03",X"CE",X"7E",X"F6",X"14",X"28",X"E9",X"4F",X"F2",X"64",
-		X"0C",X"F6",X"5F",X"D1",X"94",X"0B",X"F7",X"5F",X"C0",X"64",X"6C",X"D3",X"6F",X"93",X"A1",X"3F",
-		X"B1",X"BF",X"44",X"B0",X"5E",X"D0",X"BF",X"13",X"B3",X"7F",X"70",X"FF",X"07",X"80",X"BF",X"70",
-		X"FF",X"2B",X"60",X"CD",X"52",X"FC",X"09",X"73",X"DB",X"32",X"F7",X"2B",X"37",X"F9",X"07",X"F7",
-		X"4B",X"19",X"F7",X"18",X"F4",X"99",X"1B",X"A9",X"0A",X"F5",X"78",X"4B",X"C4",X"0F",X"F1",X"99",
-		X"2D",X"B3",X"0F",X"F4",X"A5",X"6B",X"96",X"0F",X"E2",X"97",X"3D",X"C0",X"3F",X"82",X"F4",X"1F",
-		X"90",X"AF",X"06",X"F0",X"3F",X"90",X"FF",X"0A",X"E0",X"AE",X"00",X"FF",X"0E",X"A0",X"DD",X"04",
-		X"FF",X"2F",X"40",X"FA",X"0E",X"F1",X"6F",X"05",X"F1",X"0F",X"F0",X"CC",X"09",X"F0",X"3F",X"F4",
-		X"C6",X"0D",X"F0",X"AF",X"45",X"E3",X"0F",X"40",X"FF",X"0C",X"C0",X"6F",X"00",X"FF",X"2C",X"70",
-		X"9F",X"06",X"FF",X"3E",X"50",X"F9",X"0F",X"F0",X"8E",X"02",X"F4",X"0F",X"F0",X"B8",X"08",X"F0",
-		X"1F",X"F2",X"B6",X"0E",X"C0",X"FF",X"F4",X"C1",X"1F",X"A0",X"FF",X"16",X"B0",X"4F",X"50",X"FF",
-		X"09",X"B0",X"AF",X"08",X"FF",X"1B",X"50",X"CC",X"0F",X"F4",X"3B",X"30",X"FA",X"0F",X"F0",X"4E",
-		X"06",X"F1",X"2F",X"F0",X"A9",X"0A",X"E0",X"9F",X"50",X"97",X"0C",X"E0",X"FF",X"20",X"D4",X"3E",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
-		X"FF",X"97",X"01",X"05",X"8F",X"FF",X"DB",X"30",X"00",X"68",X"FF",X"FB",X"C2",X"30",X"36",X"AF",
-		X"FE",X"C8",X"42",X"03",X"5D",X"DF",X"CF",X"55",X"02",X"37",X"ED",X"FC",X"E3",X"30",X"14",X"BF",
-		X"FF",X"E8",X"50",X"00",X"5D",X"EF",X"CF",X"45",X"01",X"27",X"EE",X"FC",X"C4",X"40",X"14",X"AF",
-		X"FF",X"F6",X"60",X"11",X"6C",X"EF",X"EC",X"63",X"11",X"39",X"DF",X"FF",X"67",X"02",X"07",X"CF",
-		X"FF",X"C5",X"30",X"13",X"9C",X"FE",X"F5",X"60",X"11",X"7D",X"FF",X"FB",X"61",X"00",X"4A",X"EF",
-		X"FF",X"44",X"01",X"38",X"DF",X"FF",X"85",X"00",X"06",X"CF",X"FF",X"E4",X"20",X"02",X"9F",X"FF",
-		X"F7",X"60",X"00",X"6C",X"FF",X"FE",X"52",X"00",X"27",X"FF",X"FF",X"77",X"00",X"05",X"CF",X"FF",
-		X"E6",X"10",X"03",X"8F",X"FF",X"F6",X"50",X"00",X"5C",X"FF",X"FB",X"60",X"00",X"5A",X"FF",X"FF",
-		X"45",X"01",X"27",X"DF",X"FF",X"85",X"00",X"05",X"BF",X"FF",X"F5",X"20",X"02",X"8E",X"FF",X"F9",
-		X"50",X"00",X"5B",X"FF",X"FF",X"62",X"00",X"37",X"EF",X"FF",X"85",X"00",X"05",X"BF",X"FF",X"E6",
-		X"20",X"02",X"7D",X"FF",X"FA",X"50",X"00",X"5B",X"FF",X"FD",X"71",X"00",X"37",X"EF",X"FF",X"95",
-		X"00",X"14",X"BE",X"FF",X"E7",X"10",X"03",X"7D",X"FF",X"FB",X"60",X"00",X"49",X"DF",X"FE",X"73",
-		X"01",X"36",X"CF",X"FF",X"B6",X"10",X"14",X"9D",X"FF",X"F9",X"41",X"03",X"5B",X"EF",X"FD",X"72",
-		X"00",X"48",X"CF",X"FF",X"A5",X"10",X"25",X"AD",X"FF",X"D8",X"31",X"24",X"8C",X"FF",X"EA",X"41",
-		X"02",X"6B",X"FF",X"FB",X"62",X"01",X"59",X"EF",X"FD",X"73",X"01",X"38",X"DF",X"FF",X"93",X"00",
-		X"26",X"CF",X"FF",X"A4",X"10",X"26",X"AF",X"FF",X"C6",X"10",X"15",X"9E",X"FF",X"D7",X"20",X"14",
-		X"8D",X"FF",X"E9",X"30",X"13",X"7C",X"FF",X"FA",X"41",X"02",X"6B",X"FF",X"FB",X"51",X"02",X"5A",
-		X"FF",X"FC",X"72",X"01",X"5A",X"EF",X"FC",X"73",X"12",X"59",X"DF",X"FC",X"83",X"11",X"48",X"DF",
-		X"FD",X"84",X"11",X"38",X"CF",X"FD",X"94",X"21",X"37",X"BF",X"FE",X"95",X"21",X"37",X"BE",X"FE",
-		X"A5",X"21",X"36",X"BE",X"FE",X"B6",X"31",X"36",X"AE",X"FF",X"B6",X"31",X"25",X"9D",X"FF",X"C8",
-		X"42",X"25",X"9D",X"FF",X"C8",X"42",X"24",X"8C",X"FF",X"D9",X"52",X"24",X"7B",X"EF",X"DA",X"52",
-		X"13",X"7B",X"EF",X"EA",X"62",X"13",X"6A",X"DF",X"EB",X"73",X"23",X"59",X"CF",X"FD",X"84",X"22",
-		X"48",X"CF",X"FE",X"A5",X"21",X"36",X"AE",X"FE",X"B7",X"31",X"25",X"9D",X"FF",X"D9",X"42",X"24",
-		X"7B",X"EF",X"EB",X"63",X"23",X"69",X"DF",X"FC",X"84",X"22",X"47",X"BE",X"FE",X"B7",X"32",X"35",
-		X"9C",X"EE",X"D9",X"53",X"24",X"7A",X"CE",X"EB",X"85",X"33",X"57",X"AC",X"DD",X"A8",X"54",X"46",
-		X"8A",X"CC",X"CA",X"75",X"55",X"78",X"AB",X"BB",X"A8",X"76",X"67",X"88",X"99",X"AA",X"98",X"87",
-		X"77",X"78",X"8A",X"AB",X"A8",X"76",X"66",X"78",X"9B",X"CB",X"A8",X"76",X"55",X"78",X"AC",X"CB",
-		X"97",X"65",X"56",X"7A",X"BC",X"CA",X"86",X"55",X"67",X"9A",X"BC",X"B9",X"75",X"56",X"78",X"AB",
-		X"BA",X"98",X"76",X"78",X"99",X"99",X"88",X"88",X"89",X"99",X"98",X"77",X"78",X"9A",X"AA",X"A8",
-		X"76",X"66",X"89",X"AB",X"BA",X"87",X"66",X"67",X"9A",X"BB",X"A9",X"87",X"66",X"78",X"9A",X"AA",
-		X"98",X"77",X"78",X"89",X"99",X"98",X"88",X"88",X"98",X"88",X"88",X"88",X"89",X"99",X"98",X"77",
-		X"77",X"89",X"9A",X"A9",X"87",X"77",X"88",X"9A",X"A9",X"98",X"77",X"78",X"9A",X"AA",X"98",X"77",
-		X"77",X"89",X"AA",X"A9",X"87",X"77",X"88",X"9A",X"A9",X"88",X"77",X"88",X"99",X"99",X"98",X"88",
-		X"88",X"89",X"99",X"98",X"88",X"88",X"89",X"99",X"98",X"88",X"88",X"89",X"99",X"98",X"88",X"88",
-		X"89",X"99",X"98",X"88",X"88",X"89",X"99",X"99",X"88",X"88",X"88",X"99",X"99",X"88",X"88",X"88",
-		X"99",X"99",X"98",X"88",X"88",X"88",X"88",X"88",X"88",X"99",X"99",X"88",X"87",X"88",X"89",X"99",
-		X"99",X"88",X"77",X"88",X"99",X"99",X"98",X"77",X"78",X"89",X"99",X"98",X"87",X"77",X"88",X"99",
-		X"99",X"88",X"88",X"88",X"99",X"99",X"98",X"88",X"88",X"89",X"99",X"98",X"88",X"88",X"89",X"99",
-		X"98",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"99",X"88",X"88",
-		X"88",X"88",X"99",X"99",X"98",X"88",X"88",X"88",X"99",X"98",X"88",X"88",X"88",X"88",X"99",X"99",
-		X"88",X"88",X"88",X"88",X"99",X"98",X"88",X"88",X"88",X"89",X"99",X"98",X"88",X"88",X"88",X"89",
-		X"98",X"88",X"88",X"88",X"88",X"89",X"98",X"88",X"88",X"88",X"88",X"88",X"89",X"99",X"98",X"88",
-		X"88",X"88",X"99",X"99",X"88",X"88",X"88",X"89",X"99",X"99",X"88",X"88",X"88",X"99",X"99",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"89",X"88",X"88",X"88",
-		X"88",X"99",X"98",X"88",X"88",X"88",X"88",X"99",X"88",X"88",X"88",X"88",X"99",X"98",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"89",X"99",X"88",X"88",X"88",X"88",X"98",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"99",X"99",X"88",X"88",X"88",X"88",X"99",X"99",X"88",
-		X"88",X"88",X"89",X"99",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"89",X"88",X"88",X"88",X"88",X"88",X"98",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"89",X"89",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"98",X"88",X"89",X"98",X"89",X"88",
-		X"88",X"89",X"89",X"89",X"99",X"87",X"88",X"89",X"88",X"88",X"89",X"89",X"88",X"88",X"89",X"99",
-		X"88",X"88",X"88",X"88",X"98",X"88",X"98",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"89",X"99",
-		X"98",X"88",X"88",X"89",X"89",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",X"88",
-		X"88",X"88",X"99",X"99",X"98",X"88",X"98",X"98",X"88",X"88",X"88",X"99",X"99",X"99",X"99",X"98",
-		X"88",X"77",X"77",X"78",X"89",X"9A",X"AA",X"AA",X"99",X"87",X"77",X"66",X"77",X"88",X"9A",X"AA",
-		X"AA",X"A9",X"88",X"77",X"66",X"67",X"78",X"89",X"AA",X"BB",X"AA",X"99",X"87",X"66",X"66",X"67",
-		X"78",X"9A",X"AB",X"BB",X"A9",X"87",X"76",X"66",X"66",X"78",X"89",X"AB",X"BB",X"BB",X"A9",X"87",
-		X"66",X"66",X"67",X"78",X"9A",X"AB",X"BB",X"BA",X"98",X"77",X"66",X"66",X"67",X"77",X"99",X"AA",
-		X"BB",X"BA",X"A9",X"87",X"76",X"66",X"67",X"78",X"89",X"AB",X"BB",X"BA",X"A8",X"97",X"87",X"87",
-		X"88",X"88",X"77",X"77",X"78",X"89",X"AA",X"AA",X"A9",X"99",X"98",X"88",X"87",X"66",X"66",X"68",
-		X"8A",X"BB",X"CB",X"B9",X"A8",X"97",X"87",X"87",X"77",X"66",X"67",X"79",X"9B",X"AC",X"BB",X"A9",
-		X"88",X"87",X"87",X"87",X"76",X"76",X"77",X"99",X"BB",X"CB",X"BA",X"99",X"78",X"78",X"78",X"78",
-		X"77",X"77",X"78",X"99",X"BA",X"CA",X"B9",X"98",X"87",X"88",X"78",X"78",X"77",X"67",X"78",X"9A",
-		X"BB",X"CA",X"B9",X"A7",X"87",X"87",X"88",X"88",X"77",X"67",X"78",X"99",X"BA",X"CA",X"B8",X"97",
-		X"87",X"87",X"88",X"78",X"77",X"66",X"77",X"99",X"CB",X"DA",X"C9",X"97",X"87",X"78",X"78",X"78",
-		X"67",X"66",X"77",X"A8",X"CA",X"DA",X"B9",X"88",X"77",X"68",X"79",X"79",X"77",X"66",X"76",X"99",
-		X"BC",X"CD",X"AB",X"79",X"68",X"68",X"88",X"88",X"87",X"75",X"57",X"6A",X"9D",X"BD",X"BB",X"97",
-		X"86",X"86",X"87",X"98",X"88",X"66",X"56",X"77",X"B9",X"EA",X"E9",X"B8",X"77",X"68",X"69",X"79",
-		X"89",X"86",X"65",X"67",X"7A",X"9D",X"AD",X"AA",X"97",X"86",X"86",X"87",X"98",X"88",X"66",X"56",
-		X"77",X"9A",X"BD",X"BD",X"9B",X"69",X"67",X"77",X"88",X"98",X"97",X"76",X"56",X"87",X"BA",X"EB",
-		X"DB",X"A9",X"68",X"57",X"68",X"88",X"A8",X"96",X"85",X"65",X"87",X"B9",X"EB",X"DB",X"A9",X"68",
-		X"47",X"68",X"89",X"A9",X"A7",X"75",X"54",X"86",X"BA",X"EC",X"CD",X"8A",X"47",X"47",X"77",X"A8",
-		X"B9",X"A7",X"75",X"44",X"57",X"8D",X"AF",X"AF",X"9A",X"65",X"65",X"77",X"8A",X"9C",X"9A",X"77",
-		X"54",X"46",X"78",X"DA",X"FB",X"F9",X"A6",X"56",X"47",X"88",X"B9",X"C9",X"A7",X"65",X"33",X"37",
-		X"6D",X"BF",X"ED",X"D7",X"A2",X"63",X"67",X"8B",X"BC",X"C9",X"95",X"63",X"33",X"48",X"8F",X"CF",
-		X"DE",X"A7",X"72",X"43",X"68",X"AC",X"CC",X"C9",X"84",X"52",X"22",X"59",X"9F",X"DF",X"FD",X"C4",
-		X"70",X"42",X"78",X"CB",X"FC",X"D8",X"85",X"33",X"12",X"47",X"AC",X"FD",X"FA",X"E5",X"52",X"14",
-		X"59",X"BE",X"EF",X"BB",X"66",X"23",X"22",X"35",X"9B",X"EF",X"DF",X"8D",X"36",X"23",X"56",X"AC",
-		X"DE",X"DB",X"96",X"53",X"34",X"34",X"58",X"BA",X"FB",X"FA",X"C8",X"55",X"24",X"68",X"CC",X"EE",
-		X"CB",X"76",X"44",X"44",X"35",X"4B",X"8F",X"FD",X"F9",X"D5",X"54",X"24",X"68",X"DC",X"FD",X"BB",
-		X"67",X"34",X"44",X"34",X"3A",X"7E",X"FD",X"F9",X"D7",X"44",X"24",X"67",X"CE",X"DF",X"BC",X"76",
-		X"43",X"44",X"44",X"46",X"B9",X"FE",X"EF",X"9C",X"54",X"43",X"59",X"8E",X"DD",X"F8",X"B4",X"54",
-		X"35",X"65",X"64",X"7A",X"8E",X"ED",X"F9",X"C6",X"55",X"45",X"88",X"CE",X"BE",X"8A",X"65",X"54",
-		X"57",X"56",X"44",X"98",X"AF",X"BF",X"E9",X"C3",X"64",X"56",X"98",X"EB",X"CB",X"79",X"57",X"56",
-		X"67",X"45",X"25",X"88",X"EF",X"FF",X"CB",X"85",X"44",X"37",X"7A",X"CB",X"DB",X"A8",X"76",X"66",
-		X"55",X"33",X"25",X"99",X"FF",X"FF",X"DB",X"75",X"34",X"36",X"8A",X"DD",X"DC",X"A9",X"76",X"55",
-		X"45",X"44",X"34",X"9A",X"EF",X"FF",X"DB",X"75",X"23",X"35",X"9A",X"DD",X"DD",X"A9",X"76",X"45",
-		X"55",X"54",X"54",X"8B",X"CF",X"FF",X"FB",X"87",X"33",X"44",X"79",X"AE",X"CC",X"C8",X"86",X"54",
-		X"55",X"65",X"55",X"59",X"AC",X"FF",X"EF",X"A9",X"64",X"34",X"47",X"AA",X"ED",X"DC",X"97",X"64",
-		X"46",X"57",X"66",X"55",X"7A",X"AE",X"FE",X"FB",X"97",X"43",X"44",X"69",X"AD",X"ED",X"CA",X"76",
-		X"54",X"56",X"67",X"66",X"55",X"8A",X"BF",X"FE",X"FA",X"85",X"32",X"44",X"8A",X"BE",X"EC",X"B8",
-		X"65",X"55",X"68",X"78",X"75",X"44",X"8A",X"BF",X"FF",X"FB",X"85",X"31",X"43",X"8A",X"CE",X"FC",
-		X"B9",X"56",X"45",X"68",X"79",X"76",X"54",X"5A",X"9D",X"FD",X"FC",X"A5",X"50",X"35",X"6B",X"CD",
-		X"DE",X"9A",X"65",X"56",X"78",X"98",X"96",X"53",X"24",X"99",X"EF",X"EF",X"D9",X"56",X"13",X"56",
-		X"AC",X"EC",X"EA",X"97",X"65",X"77",X"79",X"78",X"75",X"33",X"26",X"AB",X"FF",X"FF",X"D7",X"64",
-		X"14",X"58",X"AD",X"CD",X"CA",X"88",X"66",X"77",X"88",X"77",X"64",X"32",X"26",X"BD",X"FF",X"FF",
-		X"C7",X"32",X"01",X"57",X"BE",X"FE",X"EB",X"86",X"54",X"56",X"78",X"88",X"76",X"53",X"24",X"9D",
-		X"FF",X"FF",X"E9",X"41",X"10",X"36",X"BD",X"FF",X"DB",X"85",X"34",X"46",X"8A",X"AA",X"96",X"54",
-		X"22",X"49",X"EF",X"FF",X"FC",X"73",X"01",X"05",X"9E",X"FF",X"FB",X"95",X"52",X"56",X"8A",X"BA",
-		X"88",X"55",X"44",X"35",X"7C",X"FF",X"FF",X"D8",X"62",X"13",X"48",X"AF",X"EF",X"C9",X"65",X"54",
-		X"68",X"AA",X"BA",X"87",X"54",X"45",X"45",X"69",X"DE",X"FF",X"EC",X"87",X"43",X"56",X"8A",X"CB",
-		X"B9",X"85",X"56",X"78",X"AB",X"AA",X"97",X"55",X"55",X"56",X"66",X"8B",X"EE",X"FF",X"DA",X"76",
-		X"23",X"35",X"7A",X"CC",X"DB",X"A7",X"76",X"76",X"89",X"99",X"98",X"77",X"76",X"67",X"65",X"79",
-		X"DE",X"FF",X"C9",X"65",X"23",X"47",X"AC",X"FE",X"C9",X"84",X"34",X"57",X"9C",X"CC",X"A9",X"76",
-		X"65",X"55",X"66",X"56",X"8C",X"DE",X"FE",X"C9",X"74",X"33",X"67",X"9B",X"CC",X"BA",X"86",X"56",
-		X"78",X"AA",X"BA",X"97",X"66",X"66",X"67",X"77",X"67",X"9E",X"EE",X"FD",X"95",X"53",X"34",X"8B",
-		X"CE",X"EC",X"87",X"54",X"35",X"79",X"CC",X"CA",X"97",X"66",X"66",X"67",X"77",X"66",X"7A",X"DC",
-		X"ED",X"D8",X"76",X"55",X"6A",X"AB",X"BC",X"97",X"65",X"54",X"79",X"BD",X"DD",X"A9",X"65",X"44",
-		X"45",X"68",X"98",X"88",X"AD",X"CC",X"CD",X"97",X"66",X"55",X"89",X"AA",X"CB",X"98",X"77",X"67",
-		X"89",X"AA",X"BA",X"98",X"87",X"77",X"76",X"66",X"66",X"66",X"AD",X"DD",X"DD",X"97",X"65",X"55",
-		X"89",X"AA",X"BA",X"87",X"67",X"67",X"8A",X"BB",X"CB",X"96",X"65",X"55",X"67",X"78",X"88",X"76",
-		X"9C",X"CD",X"DE",X"A7",X"55",X"44",X"79",X"BB",X"CB",X"97",X"55",X"56",X"69",X"BC",X"CC",X"B8",
-		X"75",X"55",X"56",X"78",X"88",X"87",X"9C",X"DD",X"CD",X"B8",X"55",X"55",X"68",X"AB",X"BB",X"A8",
-		X"66",X"67",X"78",X"AB",X"BA",X"A8",X"76",X"66",X"66",X"78",X"87",X"77",X"79",X"CD",X"DC",X"DA",
-		X"85",X"56",X"67",X"8B",X"BB",X"A9",X"76",X"55",X"77",X"9B",X"DC",X"BA",X"87",X"55",X"56",X"67",
-		X"89",X"98",X"87",X"8B",X"CC",X"BC",X"B8",X"65",X"66",X"78",X"BC",X"BA",X"98",X"66",X"57",X"89",
-		X"9B",X"CB",X"A8",X"87",X"66",X"67",X"77",X"78",X"78",X"77",X"AC",X"DC",X"CC",X"A8",X"56",X"67",
-		X"78",X"BB",X"A8",X"87",X"76",X"78",X"99",X"9B",X"BA",X"87",X"77",X"66",X"78",X"88",X"78",X"87",
-		X"66",X"8C",X"DC",X"BC",X"B9",X"65",X"67",X"88",X"AB",X"A9",X"87",X"77",X"67",X"89",X"AA",X"AA",
-		X"A8",X"88",X"87",X"67",X"77",X"66",X"78",X"88",X"79",X"CD",X"CA",X"BA",X"96",X"56",X"78",X"79",
-		X"AA",X"98",X"88",X"87",X"77",X"88",X"89",X"9A",X"AA",X"99",X"87",X"66",X"66",X"66",X"78",X"99",
-		X"89",X"AB",X"BB",X"AA",X"98",X"66",X"77",X"88",X"9A",X"A9",X"88",X"88",X"77",X"89",X"99",X"99");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dac.vhd
deleted file mode 100644
index 91f7e809..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 10
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kb_synth.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kb_synth.vhd
deleted file mode 100644
index c90cf9c0..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kb_synth.vhd	
+++ /dev/null
@@ -1,160 +0,0 @@
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity kb_synth is
-	port (
-		reset_n  : in  std_logic;
-		clk : in  std_logic;
-		in0 : in  std_logic;
-		in1 : in  std_logic;
-		in2 : in  std_logic;
-		in3 : in  std_logic;
-		speech_out   : out std_logic_vector(7 downto 0)
-	);
-end kb_synth;
-
-architecture RTL of kb_synth is
-
-signal cpu_addr : std_logic_vector(15 downto 0);
-signal cpu_di : std_logic_vector(7 downto 0);
-signal cpu_do : std_logic_vector(7 downto 0);
-signal ram_do : std_logic_vector(7 downto 0);
-signal rom4_do : std_logic_vector(7 downto 0);
-signal rom5_do : std_logic_vector(7 downto 0);
-signal rom6_do : std_logic_vector(7 downto 0);
-signal mreq_n : std_logic;
-signal iorq_n : std_logic;
-signal rd_n : std_logic;
-signal wr_n : std_logic;
-
-signal ram_ce : std_logic;
-signal rom4_ce : std_logic;
-signal rom5_ce : std_logic;
-signal rom6_ce : std_logic;
-signal ic3_out : std_logic_vector(7 downto 0);
-signal buf_do : std_logic_vector(7 downto 0);
-signal buf_ce : std_logic;
-signal A13n : std_logic;
-begin
-
-cpu_di <= ram_do when ram_ce = '1' else
-			 rom4_do when rom4_ce = '1' else
-			 rom5_do when rom5_ce = '1' else
-			 rom6_do when rom6_ce = '1' else
-			 buf_do when buf_ce = '0' else
-			 "00000000";
-
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n      => reset_n,
-		CLK_n        => clk,		
-		WAIT_n       => '1',
-		INT_n        => '1',
-		NMI_n        => '1',
-		BUSRQ_n      => '1',		
-		MREQ_n       => mreq_n,
-		IORQ_n       => iorq_n,
-		RD_n         => rd_n,
-		WR_n         => wr_n,		
-		A            => cpu_addr,
-		DI           => cpu_di,
-		DO           => cpu_do
-	);
-	
-A13n <= not cpu_addr(13);
-ram_ce <= not (A13n or mreq_n);
-	ram_inst : entity work.spram generic map(10,8)
-	port map (
-		address  	 => cpu_addr(9 downto 0),
-		clock    	 => clk,
-		data     	 => cpu_do,
-		wren			 => not wr_n,
-		q				 => ram_do
-	);
-
-rom4_ce <= ic3_out(0);
-	rom4_inst : entity work.kbe1_IC4
-	port map (
-	clk    	 	 => clk,
-	addr  	 	 => cpu_addr(10 downto 0),
-	data			 => rom4_do
-	);
-
-rom5_ce <= ic3_out(1);
-	rom5_inst : entity work.kbe2_IC5
-	port map (
-	clk    	 	 => clk,
-	addr  	 	 => cpu_addr(10 downto 0),
-	data			 => rom5_do
-	);
-	
-rom6_ce <= ic3_out(2);	
-	rom6_inst : entity work.kbe3_IC6
-	port map (
-	clk    	 	 => clk,
-	addr  	 	 => cpu_addr(10 downto 0),
-	data			 => rom6_do
-	);
-	
-	ls138 : entity work.ttl_74138
-	port map (
-		a    	 		 => cpu_addr(11),
-		b    	 		 => cpu_addr(12),
-		c    	 		 => '0',
-		g1    	 	 => A13n,
-		g2a_n    	 => rd_n,
-		g2b_n    	 => mreq_n,
-		y_n    	 	 => ic3_out
-	);
-
-	ls273 : entity work.ttl_74273
-	port map (
-		CLRN    	 	 => reset_n,
-		CLK    	 	 => not (wr_n or iorq_n),
-		D8    	 	 => cpu_do(0),
-		D7    	 	 => cpu_do(1),
-		D6    	 	 => cpu_do(2),
-		D5    	 	 => cpu_do(3),
-		D4    	 	 => cpu_do(4),
-		D3    	 	 => cpu_do(5),
-		D2    	 	 => cpu_do(6),
-		D1    	 	 => cpu_do(7),
-		Q1    	 	 => speech_out(0),
-		Q2    	 	 => speech_out(1),
-		Q3    	 	 => speech_out(2),
-		Q4    	 	 => speech_out(3),
-		Q5    	 	 => speech_out(4),
-		Q6    	 	 => speech_out(5),
-		Q7    	 	 => speech_out(6),
-		Q8    	 	 => speech_out(7)
-	);
-
-buf_ce <= rd_n or iorq_n;
---buf_do(6) <= '0';
---buf_do(7) <= '0';
-	ls367 : entity work.ttl_74367 
-	port map (
-		p2GN    	 	 => buf_ce,--15
-		
-		p2A1    	 	 => '1',--12
-		p2A2    	 	 => '1',--14
-		
-		p1A4    	 	 => '0',--in3,--10
-		p1A3    	 	 => '0',--in2,--6
-		p1A2    	 	 => in1,--4
-		p1A1    	 	 => in0,--2
-		
-		p1GN    	 	 => buf_ce,--1
-		
-		p2Y1    	 	 => buf_do(4),--11
-		p2Y2    	 	 => buf_do(5),--13
-		
-		p1Y4    	 	 => buf_do(3),--9
-		p1Y3    	 	 => buf_do(2),--7
-		p1Y2    	 	 => buf_do(1),--5
-		p1Y1    	 	 => buf_do(0)--3
-	);
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd
deleted file mode 100644
index 91831325..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/kingballon.vhd	
+++ /dev/null
@@ -1,455 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA King and Balloon
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity kingballoon is
-	port(
-		W_CLK_18M  	: in  std_logic;
-		W_CLK_12M  	: in  std_logic;
-		W_CLK_6M   	: in  std_logic;
-
-		P1_CSJUDLR 	: in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR 	: in  std_logic_vector(6 downto 0);
-		I_RESET    	: in  std_logic;
-
-		W_R        	: out std_logic_vector(2 downto 0);
-		W_G        	: out std_logic_vector(2 downto 0);
-		W_B        	: out std_logic_vector(2 downto 0);
-		HBLANK     	: out std_logic;
-		VBLANK     	: out std_logic;
-		W_H_SYNC   	: out std_logic;
-		W_V_SYNC   	: out std_logic;
-		W_SDAT_A   	: out std_logic_vector( 7 downto 0);
-		W_SDAT_B   	: out std_logic_vector( 7 downto 0);
-		W_SDAT_C   	: out std_logic_vector( 7 downto 0);
-		O_CMPBL    	: out std_logic
-	);
-end;
-
-architecture RTL of kingballoon is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
-	-- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => '0',--No Stars on this Game
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-	
-	speech : entity work.kb_synth
-	port map(
-		reset_n        => W_RESETn,
-		clk        		=> W_CLK_6M,
-		in0        		=> '0',--DIP
-		in1        		=> '0',--DIP
-		in2        		=> '0',--DIP
-		in3        		=> '0',--DIP
-		speech_out     => W_SDAT_C
-	);
-	
-	mc_roms : entity work.prog
-	port map (
-		clk  => W_CLK_12M,
-		addr => W_A(13 downto 0),
-		data => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 5a4d0094..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c0edf061..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.col
-	port map (
-		clk  => I_CLK_12M,
-		addr => W_6M_DO(6 downto 2),
-		data => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 69a20cbe..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,74 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd
deleted file mode 100644
index 95911cec..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,431 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	k_rom : entity work.rom_k
-	port map (
-		clk  => I_CLK_12M,
-		addr => '0' & W_O_OBJ_ROM_A,
-		data => W_1K_D
-	);
-
-	h_rom : entity work.rom_h
-	port map (
-		clk  => I_CLK_12M,
-		addr => '0' & W_O_OBJ_ROM_A,
-		data => W_1H_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/spram.vhd
deleted file mode 100644
index d8043481..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone III",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd
deleted file mode 100644
index e16bd235..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74138.vhd	
+++ /dev/null
@@ -1,48 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-Use IEEE.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-entity ttl_74138 is
-	port
-  (
-  	-- input
-  	a				: in std_logic;
-  	b				: in std_logic;
-  	c				: in std_logic;
-
-		g1			: in std_logic;
-		g2a_n		: in std_logic;
-		g2b_n		: in std_logic;
-		
-  	-- output
-  	y_n			: out std_logic_vector(7 downto 0)
-	);
-end ttl_74138;
-
-architecture SYN of ttl_74138 is
-
-	signal enabled	: std_logic;
-	
-begin
-
-	enabled <= g1 and not g2a_n and not g2b_n;
-
-	y_n(0) <= '1' when enabled = '0' else
-						not (not a and not b and not c);
-	y_n(1) <= '1' when enabled = '0' else
-						not (a and not b and not c);
-	y_n(2) <= '1' when enabled = '0' else
-						not (not a and b and not c);
-	y_n(3) <= '1' when enabled = '0' else
-						not (a and b and not c);
-	y_n(4) <= '1' when enabled = '0' else
-						not (not a and not b and c);
-	y_n(5) <= '1' when enabled = '0' else
-						not (a and not b and c);
-	y_n(6) <= '1' when enabled = '0' else
-						not (not a and b and c);
-	y_n(7) <= '1' when enabled = '0' else
-						not (a and b and c);
-
-end SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd
deleted file mode 100644
index 9f60ae57..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74273.vhd	
+++ /dev/null
@@ -1,136 +0,0 @@
--- Copyright (C) 1991-2014 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- PROGRAM		"Quartus II 64-Bit"
--- VERSION		"Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
--- CREATED		"Sun Aug 18 11:45:39 2019"
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all; 
-
-LIBRARY work;
-
-ENTITY ttl_74273 IS 
-	PORT
-	(
-		CLRN :  IN  STD_LOGIC;
-		CLK :  IN  STD_LOGIC;
-		D8 :  IN  STD_LOGIC;
-		D7 :  IN  STD_LOGIC;
-		D6 :  IN  STD_LOGIC;
-		D5 :  IN  STD_LOGIC;
-		D4 :  IN  STD_LOGIC;
-		D3 :  IN  STD_LOGIC;
-		D2 :  IN  STD_LOGIC;
-		D1 :  IN  STD_LOGIC;
-		Q1 :  OUT  STD_LOGIC;
-		Q2 :  OUT  STD_LOGIC;
-		Q3 :  OUT  STD_LOGIC;
-		Q4 :  OUT  STD_LOGIC;
-		Q5 :  OUT  STD_LOGIC;
-		Q6 :  OUT  STD_LOGIC;
-		Q7 :  OUT  STD_LOGIC;
-		Q8 :  OUT  STD_LOGIC
-	);
-END ttl_74273;
-
-ARCHITECTURE bdf_type OF ttl_74273 IS 
-
-
-
-BEGIN 
-
-
-
-PROCESS(CLK,CLRN)
-BEGIN
-IF (CLRN = '0') THEN
-	Q8 <= '0';
-ELSIF (RISING_EDGE(CLK)) THEN
-	Q8 <= D8;
-END IF;
-END PROCESS;
-
-
-PROCESS(CLK,CLRN)
-BEGIN
-IF (CLRN = '0') THEN
-	Q7 <= '0';
-ELSIF (RISING_EDGE(CLK)) THEN
-	Q7 <= D7;
-END IF;
-END PROCESS;
-
-
-PROCESS(CLK,CLRN)
-BEGIN
-IF (CLRN = '0') THEN
-	Q6 <= '0';
-ELSIF (RISING_EDGE(CLK)) THEN
-	Q6 <= D6;
-END IF;
-END PROCESS;
-
-
-PROCESS(CLK,CLRN)
-BEGIN
-IF (CLRN = '0') THEN
-	Q5 <= '0';
-ELSIF (RISING_EDGE(CLK)) THEN
-	Q5 <= D5;
-END IF;
-END PROCESS;
-
-
-PROCESS(CLK,CLRN)
-BEGIN
-IF (CLRN = '0') THEN
-	Q4 <= '0';
-ELSIF (RISING_EDGE(CLK)) THEN
-	Q4 <= D4;
-END IF;
-END PROCESS;
-
-
-PROCESS(CLK,CLRN)
-BEGIN
-IF (CLRN = '0') THEN
-	Q3 <= '0';
-ELSIF (RISING_EDGE(CLK)) THEN
-	Q3 <= D3;
-END IF;
-END PROCESS;
-
-
-PROCESS(CLK,CLRN)
-BEGIN
-IF (CLRN = '0') THEN
-	Q2 <= '0';
-ELSIF (RISING_EDGE(CLK)) THEN
-	Q2 <= D2;
-END IF;
-END PROCESS;
-
-
-PROCESS(CLK,CLRN)
-BEGIN
-IF (CLRN = '0') THEN
-	Q1 <= '0';
-ELSIF (RISING_EDGE(CLK)) THEN
-	Q1 <= D1;
-END IF;
-END PROCESS;
-
-
-END bdf_type;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd
deleted file mode 100644
index 161c44b2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/ttl_74367.vhd	
+++ /dev/null
@@ -1,122 +0,0 @@
--- Copyright (C) 1991-2014 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- PROGRAM		"Quartus II 64-Bit"
--- VERSION		"Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
--- CREATED		"Fri Aug 16 22:43:02 2019"
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all; 
-
-LIBRARY work;
-
-ENTITY ttl_74367 IS 
-	PORT
-	(
-		p2GN :  IN  STD_LOGIC;
-		p2A1 :  IN  STD_LOGIC;
-		p2A2 :  IN  STD_LOGIC;
-		p1A4 :  IN  STD_LOGIC;
-		p1A3 :  IN  STD_LOGIC;
-		p1A2 :  IN  STD_LOGIC;
-		p1A1 :  IN  STD_LOGIC;
-		p1GN :  IN  STD_LOGIC;
-		p2Y1 :  OUT  STD_LOGIC;
-		p2Y2 :  OUT  STD_LOGIC;
-		p1Y4 :  OUT  STD_LOGIC;
-		p1Y3 :  OUT  STD_LOGIC;
-		p1Y2 :  OUT  STD_LOGIC;
-		p1Y1 :  OUT  STD_LOGIC
-	);
-END ttl_74367;
-
-ARCHITECTURE bdf_type OF ttl_74367 IS 
-
-SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC;
-
-
-BEGIN 
-
-
-
-PROCESS(p1A4,SYNTHESIZED_WIRE_6)
-BEGIN
-if (SYNTHESIZED_WIRE_6 = '1') THEN
-	p1Y4 <= p1A4;
-ELSE
-	p1Y4 <= 'Z';
-END IF;
-END PROCESS;
-
-
-PROCESS(p2A2,SYNTHESIZED_WIRE_7)
-BEGIN
-if (SYNTHESIZED_WIRE_7 = '1') THEN
-	p2Y2 <= p2A2;
-ELSE
-	p2Y2 <= 'Z';
-END IF;
-END PROCESS;
-
-
-SYNTHESIZED_WIRE_6 <= NOT(p1GN);
-
-
-
-PROCESS(p2A1,SYNTHESIZED_WIRE_7)
-BEGIN
-if (SYNTHESIZED_WIRE_7 = '1') THEN
-	p2Y1 <= p2A1;
-ELSE
-	p2Y1 <= 'Z';
-END IF;
-END PROCESS;
-
-
-SYNTHESIZED_WIRE_7 <= NOT(p2GN);
-
-
-
-PROCESS(p1A1,SYNTHESIZED_WIRE_6)
-BEGIN
-if (SYNTHESIZED_WIRE_6 = '1') THEN
-	p1Y1 <= p1A1;
-ELSE
-	p1Y1 <= 'Z';
-END IF;
-END PROCESS;
-
-
-PROCESS(p1A2,SYNTHESIZED_WIRE_6)
-BEGIN
-if (SYNTHESIZED_WIRE_6 = '1') THEN
-	p1Y2 <= p1A2;
-ELSE
-	p1Y2 <= 'Z';
-END IF;
-END PROCESS;
-
-
-PROCESS(p1A3,SYNTHESIZED_WIRE_6)
-BEGIN
-if (SYNTHESIZED_WIRE_6 = '1') THEN
-	p1Y3 <= p1A3;
-ELSE
-	p1Y3 <= 'Z';
-END IF;
-END PROCESS;
-
-
-END bdf_type;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/KingBaloon_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qpf
deleted file mode 100644
index 35d49f9b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qpf	
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 14:59:16  November 16, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "14:59:16  November 16, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "MoonCresta"
-PROJECT_REVISION = "Arcade-MoonCresta"
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qsf
deleted file mode 100644
index 5fb26b29..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.qsf	
+++ /dev/null
@@ -1,190 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 16:56:24  March 10, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		MoonCresta_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/MoonCresta.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name TOP_LEVEL_ENTITY MoonCresta
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ------------------------
-# start ENTITY(MoonCresta)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(MoonCresta)
-# ----------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.srf
deleted file mode 100644
index a455f0f5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/MoonCresta.srf	
+++ /dev/null
@@ -1,51 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/README.txt
deleted file mode 100644
index 846fd542..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Moon Cresta port to MiST by Gehstock
--- 18 December 2017
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/Release/MoonCresta.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/Release/MoonCresta.rbf
deleted file mode 100644
index cb89a4eccffad7512f78580d369f8f494cd7655b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 308269
zcmeFa4|p7Bb?-mBS*IHapdB`1B3!dOUYoJwB#ud`8rrhEUYUsy#1<melcr!Bhq{#h
zlF;@xm;2l&Gpms^ve&U4LhGiKNXCF@Y2!fdQ*QqdD>$H1--|=xSO5BtI1kX2OB*?*
ztqZ03eZKGP#Ihp)QLOYDq9bW%=KXWt^Pcy-=RN1V@2sAA=FIS(e>Lz=-}|TUe(!t7
z|Lw%TfB*a6|Bvr}|HOZM_q*Ra@$WqHp@;7-UV3IkKlHg45CGG!x?h0j$AMfMrq@o>
z&gUw8d0_f=dK)wE)3(y|D$oGZbY1m4R}h}*km5hxHEl1=S6#K4rt3Oa8dQEd4Z2V9
zpYEErm*%UE@TBR__nP86*K68NT3&Pr(m9x>pY3|O@=8x(CJv=5ZRWKJTny-%1yn{f
z=_*j#Oh|H0ekwmLo2I5|>2rFWp00MqlQd6P<qOjLaX|NVAWheE3Q7~`Ik`*j)BN;0
zJ#YGbny;(UQ<~B;)i$L0x{8)wAk9m!O4q%vDWrKmklyPmJZj@5fabP9X(@;=mjWuY
z9Z;P<AOe)Gd_7B!&jjlL<@dBfcv7eV7quZX0}6nWhTD*4tIijIy8va0o<nW;JTU!!
z`g59|UQ-&@0>U|6{=@_2>)HX>fch&?S_(-@@+mrWmtNIp-Rr7!f$o)-g3?kt()QB%
zk@h!jE4`|YWJGiofwaEzHHNCMv@Zgw3>*ZMHXW3fLYl7f>3!Osu9ATiQo7PUC_n9o
z@TvV#AO<FZF9T^ir@KB5q<Lxkx^4tYZBRP`(V?r7b^RpJ0?L4BQ=P+r((eY8r{}+J
zgYHvE({%k?VEXg=8L%4=&jpf)<gTMbGzc^&1WHf&p*fe%FY!aq;)$*T-4C`QNlDWF
z5;zJdYX%wXg@1bcdKT|~5)d7FPT@msP`YG8JeB;XW48@R=fj!i%2(QumKC0qu6{u6
zr8K42lm=Z>I&|*<w*f*aI`#v)3b)eIHqPa$w%-Sc9*w(XPi>qI7PleIS08Q$mH^5U
zoqCphNVf^5-zO=3egD{oG*9hso(5~$-~zf;mhMyd{Wj=%C7|oa0P$fuOy`Z#zYe7N
z;?KQ6`mC$wuR!!@%mwMZ)m5};eAJ$<nja!Xd6HArl^lqc6wV|UryC=+KONMbAfYJv
zOj451&$dBNDZj*G(UwBW^XXUde>x~{`tx)ebgyxrjfOOBC!qFH+9X^50i-nOs^_!8
zbUmW`bgrb=w7t_^)ArJQ(XPIw>0*~?P+AISqe=N``{`9{Y&sWa@<we-cM5bb{qZi~
z?*Pe~)?ZyElPP?s4SLpXnx0-Y$A$pmOVc!Or-SmQgZe)GIictzO`=<Lr10@J=vg#M
zMm3Mro~{o8qD}WHC`~#kh1Iiwc&4^exF3+dNT0PHrL@g<{SvSXkbEj%>r<Mh^oIfA
z6pv+-2wn%gat0_Z1!ai_f#{GuAUd^n>}^B34r{FuC@;B7KL1Y}W~PY_!7sOA=`={&
zpMDknf;3HZNcIhJd`M>XoWk^ZI@`U1A5Q@q{}e>eG%{wreV`4ZLj^>>@F-dIiTBgn
zOX<;ddiu=!l!jEzi?68-BK?_y^r}EMnn3A#)>?HV(AkC$1A3O-q3Zx38gv!B9ne*2
z0?{M;F{MNN)qOfQQfBB``b$^YL(*vi&GpLx*}7i^QoCB$N6!E=b^JF0rKNPFSG6}C
zQrc3w#P{C=R3_z>)*tafp!*c`EWS*?&b&|MN_<E`b0D?T)OWR&(xE&(Csx{}mx@Qr
z0i|gTmVOgxT%|%*0m@U_ZvwJgt_PGaTTQ%FnryUmuBn{THvrRVQriN}S6!8-tMCiN
z8-ea+JL;--ezy&}{{*0`d@<Sfy2?(x572#@rsotSb16s$Q&8K2ln$voJ*PaKNr(EU
zwo^#ylFpEStm}?8{2B0DZAjCk%ih)o@!$i1t|=%>_o6|dbwVI|lawSa9Xs(#_vux3
zneJ}|t_GC%7C>p~nt2tV^<1DiEIUIoa3)CWiXV~#$&zGW>xR}Bfu7F>S~CS{IpL8m
zOX1T%s;_iadOB}(Ri6a9zXH(pwSZ(rAUbr_T-H^3LTS3{S)hBRrJyv8i$L_KkFuXr
ze_YpeeA2X60IvbkbdB3P0i_AFe(72IN_MnB_wN9br{r_GZq?YS{ppalCz?`7({xok
z0^N%y_2JI}$yEw^o(V^0z+=Glr0F#1Ub2_AudCV<=w3QZ@+I9WT_e!E{~JJQDd_oZ
zARbKz%~{RO6x7~q@b7@;-t;`#5`x*%l>W6g=zcCR9pA$J0tXg2u)u+H<$&~`^yw+(
zgHyuIr)16YP@IwW@P~|bH!Za>?S788U)pu)9BZ7u_|(sAn2}jMC1yM$^URM^|9*;Y
zKXc);<=%POqO%n_=ltjP@|>$ax8VE}<`5qi*Zrc$XNM7$fX})`P72j5cQuQoj$Dwn
zEh9ixSM^l66z8ZMcVuy;8Wqd69=J1Ws-*SJwPBUA)aSk<%2^=k5Y|&*cRxi^D3vo^
z(<FDQ@$I0Tu}0PQ5qC@Ra+jj(3zk(a=0;t|wt8~CIZCW=_;sr*Q!Nfaja9W(iaMr1
z;O;9}joOv<`pPWmJ3m#=jTUUnx@lR)Dvia1^=`K-6L^E}D0Le>c6Mb}m2drBO+d=|
zqOD#K;$)VUGFG6zJPYcRq*y#EH8WzGW$mu(Q<dXVj>^qSK(Sgm$UgqRU#hHmfeT#F
z=B1C8HUBeUfv|Juz=DjOJFk+G(>Z38!CVncFF*CMebXP$?|xw>&6R%(99!VnEF91j
zZ_bkbe3Gh}t3UigTG-Errgohdi}aUd?9B@lzw{>;&kG_ULCP*%%I4;wo{1-gf7niT
zDTAv~u7_ExQkV6-Hs6<wiXCLEf{U+$_pu^pt&R>x2HTt~SP%c*yp6NQ=1hH>TORXl
z{s#KTe`{`ypQ-c(t^kk>%Q&&fh1C`d>pT;u{^+~n2(EAySxg+cwj`c!;={lD3N0Eh
z1nO75!oG6tt1BzZkF9yA=DPY^`nl*<@1a`xbHjIfAM3PlJ~8aRr~KIa{`k>-Hf4Wy
z)yiYF6Wdg0#?@UC-P(P@R(G?a-R(QEt={WCLJ#*>l7~;-ZkT%}X+HP7uRZvZb1!_B
zl4y$g)0Iaam=+&7OT%Z&o^KU)w)W07zhM31@VS;fd%1a3VMXhK&P&eT;>;3?8&zf|
z@_gX)KTKwydimV&9=)v0t3kA2cF!V7XGpqGC;7Y^P-o!5+_L72V<xbE<o|uiy!eR*
z*;L=p%->4#gJ^X>PX&CM@z+4l%iw_j#pT4m5Ed-PF?>8v<9*iZSoHF)X3aa##MQ@3
zGPR9G{pyM<8~oZevQ1xITyyh@yEeb4JTd%EZ(pZ<<rgrxWt?MuC-(KstNVm8$1l|C
z?h$A|#o%r~y!v0~&vl*p(ceAIT%CJzdFsZ$pKonBcPeJ7QM9Jsv?obV_FiWxGl!(9
z&;QaKN}r|ZJQ~YC{0qF{<%@=6^R-f1w|)9~_)w>j+xfE9UQ|PQVd`sb^Us@%Sr>Q!
zXWnAkrwxKn{kOYMGiRPh@_Z|~`5Na1tNVO|$v==*ck#MQ7oy$s7wxVd|Lb3T9!lXf
zRnQgjX|m>=-0|4&U${GVbMDP76_O)`|1H_joF#wmN%N$tIb;dkdGy>&wJMtu)$Cb_
zz3tO4J4=ak&;Gw+_Ze@kd=?^i|J7Lv%psexoHtvoIQ7Jz&Y|hE6rCq2Gp+nz8OyWu
z?*$=jzN{W=-WB$ROWAxaCDlyfjUVBVfc4_FyiM?YL7$w<%s*KsQFP}SC7!kV3wzFl
z9?aV6c_u29z7X&}DIVv0hj`7K?p4fVzSO1lLvMMTk$cgY9_K5k&(?p@aBSWdO6x^*
z9`ji-Ij@@+jf|Zam!?;SWAi7kY{CZf7IjI^E53M*ZnFzIUrYQ#xch<*cWXwz04HOr
z$KQY5g3<l2)AikX-B*wQ`ko6^TPA1n&Z~DPD=)<8PV(a1?iM(9ZhSgfYQ8zPuu`7n
z?K#|C$d>Z_sn~^gD$hX_W)%5BJl#F-CkE$F1Yblx{CP%*XRZFi#=5m=ya0B$weU{m
z!aJ2S)aqFuFXR>Zti+#lf%!K3&bi^U6<i?fY#f@IzreAX968(b0>{qAp_%zV^c*uM
z!*0D?uXDe!p>EUA1OMlT|2qJxnO|zZBQ;Z)p3n0IE`YPz%;%Z-!kXL+!g<m+YxRZW
zCHpI{p1(+U^39pkzN+*zb7!_Mr+9ABsdqj0+{EXTqO-+?J1;-e_wAk=MW%5bp`P0C
zO5IDQ&L3`j<+&YtK9`m*cz0kv-axgc{%Gu6m~n1pUI<-Xoe#m7detAFTMy2q6uq3c
z=+wf|?sMVzDP`t+Ue4FP#lq3<Q-<l>9@=LWUs%gqq%6Esd2RzTt<-!^v}vf%@3u|Y
z3lTS7c&BpV8w97nqEkCRNu~DG2R|Il+mXB%_K-<cFWEd#xa+gev*Ik(UI;UCmS*Oj
zv_RNgd3K?4ta#-4d>iCxdVirWl&2wkj>#A5Q0h$J9J_Lc;`7<d;;olonBj<y<2O#g
zgVTNi$-J547xdS5pFs-dl(i7=o;4tR?ukE;@$TXSAHQhfn@se*kMjc;y0V;~UM~DY
ztU2>>K3C)gOKq;~pHGf07~ON_{spTp7L4vW52Z1>qtl!+39I?p&GC->^Q>~~u9wf5
z#M4!nPbDCcp119@7tIUW2*GpDNh33}9Oal}(RY?JbFA^4xclkp0Qt80Aad3wr{4MG
z#@avdUvRE+?yCI~*X4IOUwQpQwRa8eH2*zk)6h=y?{hkj4(k8sYzlu*U*yfj`~#hd
z6L+`&fsU?MIlGeosI&ZpWB!HC4<M3yufCW3DgLWY(wlnk)6rkf-&C8=FZh-ch)<_&
z=A8cht~pmZZG{DE^R%ovO~wMpPQ#efCeJs==IsQ-!q<DBcFazbG2cUZnr7ynd?6Dy
zZ}K{?Uz=sIj66?Un^5O-{>$ZAEcylWe6BKmAxrcNYC*rC$QR7>hid;hj=~R+d0v_N
zmp#F}9a?!|{_ka#bHT}1aL-kdoGgFq&1c-7)x<k@c<S5paZ)*H?<@hAjya9Z)X_Jb
zdoRvb@<P_aXQTa`^UuQmbH-x|!m;^t!e2yRW-vD{pRV+L59PetuBRh<&gt}W{$%We
z4)iQo=<^ytfAPG3@`75?FDUXC&O|RhHInW8%1=L3d!l)}37v0lnn?P!uRrRWe}wsZ
zLg)M^%uV4=^RF;FkG^03g1+<Ub>@Fzww~gD&6}7r*C(3ClgRnzW)e#O0YpOReC4s)
ziM#8)NpE<*Vf<zDrt+sBET6NAe@+GLiZh1L=VZMW{>pt$1J66*EH>iYtk*B?n3J*F
zCi*mOytDYyx%TSxui!p&$DEO!w(&EYDdB1B&6@G}ug>qkZJ)J~=aYCw!Klu0oS)fr
zrniviM&6m(KQ~+#?3s-P!sa-T{1dIq=3B;|dn$HbY=`3;er?X3J8gye@AYY$np?&N
zMp#Gg*{?0wb@zW-@aIe{d#(<hy6W;XRXE4I_M2h$_a90sJa>7W*79>RPi>`?vg(0*
z5|ux#?kOc_rq6s<Va=xmrapH^ax+^o<;*mQW<INoqf<5prarN_eP=GG6iy#P>zr5S
zH}*eEsOU>EOltzRosRNprIOnt<7YEH&Nc|sQ0{uiX;<D^$edPjw%e<pnO}`LU&i-~
z>-+a-8=1MM&9k~KomR}|O4`D=3eS~ed~44?Y+u;kHWuBy$>Boq?8SWibRl?lYAo<S
zKX^8~jl(}PZW|3}G^ZZ;ueo^cT6Fdr=kOo*Qak1xEUE+bS$3t*RIejz$eP_2eQHmV
z+cs5aFEo3%o|`)LhX4B9#B)hWnw=3#d*kvSN$Q@dbF*Qet^Cx@ADXRbns&0^vrA1{
zu6=z~&y0lgcs#QiHBCro>(<P6r+({aW+t8TOh3=5gGr^Iy7`pK=k-807gpA}aq!HN
zF*jWE9l}f%*4(I=rS!b-dR(}a&Fg}KVwm*{8lLwXVT4L%Kc#y7U!I(0+@5FBe9QEF
zjrNNt0H77+g$XlHU1q<a$Tw;N&HAp_`Sz!J{KMYD%VN{seS3jVqfU#^w5`+UsZLC_
zTYvGQGpp8fv7Ax@3Rk~<enXTgVyp7(-N_rxmve^uzm>P#lGlv0qfN_Ass-6IRIge5
zC^%ok?8~tqv9V#*t-49BH>_Hzn5%bWYJQ=bsa3!8?eAHUU0D8=W^Q-Et*o28w>sh0
zr=mhDySu*D-{Y-VbTA61>{{PTs$St({pf#cxdZm0{gC&#ntkWhxuDq}?z+B~ci(Ww
zRrOVq{@&`uyX&<ZoG^P^y}MOxb=Ko=)V$p9UEi1Q3ip*SJK;t9t;@gRHtMmrskr3b
zzREUpSNdxQomR7vzw+MB>;roaMV9AYcB1><$odIWc4SNOy;+KmRs18(Yr%U@Jvw-=
zedNAJBPVbnq4wrD`x9Sx57{@ync{oLqwAlp6ui>W=1)e$6W)qOzHde0vF(ozJHci<
z+Ex46rgvv|+o?Iju$^m`Y`R)v&ht7+7?}+MBkLrZYs6<11(}XK`Pd7>OkUgDnIU{q
zqCrN5j=TdGGorFVqDrCF;W!S$YU<FG6@}dMp(Jj7bI+r&lnT#^b&1Cms?c%Z|9KhM
zLT!y0OGQm^6G4^m0Ff1TfUTNOde+KVG)MW9JxK8-S2d_V%X;{YFA=3eA;R@n^|yxV
zFr+34>VBlw9V$hu9TieT!jLpbLOYF%wtGq$%b9xYz3sj$Q*EfrT%WCDdSkdFW~+d0
zb$DO}z>q+@wB1hmkFrS?g>3+18`^22&nngO2h)uw9%;E<=#)!9D-RrA)E-q`QaVH>
zm<=vS7FEu(_*1z!1=q=kAoEwBYBw2%k(y39DeQ^N=^92sA-^$1YA^yiHF%;2m%hYh
z29QH)shqKF`<WlRIFb=(XpKT)r!FHXnP8xxJ7p-hR<w~%Q&tQC(M$lbnhnBQX6I|U
z1ycvqNZd5+ZLyM&ndhXrQpUDqyO`#ot(2JsbF%#hej9n{`j99Uh$@<iB&2H2Kti^j
z5ag3mG9$u~lubXUeqo!+iqdu$mDAz-k|%?PM+6t7LC93%DltA21Z6t*#y`@622x=M
zXuxMGYxbHH!yG4H)$|7JYHYY_!xZu5v@o^x=S`mGZi2hrd0I#^_-r=|JF9s!G)dN}
zpH3jPqZw)K94h4@ODF}&wT;i<<sPc}RbrAIoQ_I^lrP@??6*v5$devmq<}Wggxg7y
zp|2y)Y-@8$<(>l&DW(Ls|JX~Lk|=)RKm;=xC`Y5E>1m{kj*#L=HCqRrgLE^D?2fHr
zs}L8^reG?CWt5>&x-%LQF+n+G0ByVT`0@?RgerAtDU|3UZ;_cDY9o)vL_PaHpGY+`
zhgKc0=6e}C*n_}?nwXG^<bpE;Av0RDn2liuadBu)L>*uH-N5K{sy*iyB9NBn{%#D1
z^COw)NPLZ>N>X#6<o7wPSq`MMe^(doe?!Jv9}nm4;iGY8ef&YM{#e`}Tf^`7^D72O
zzpXVG_vMENV~b)@X+ylzv4#gn+~Q7eIKO`Uu4s3i%;0#-8J>)6Zbu8&Z4S8X;Yr8p
zDwOME*I4$da_))^T^Va_zAw-CFeWp;$k2ZC<p-m#v4S-e)-W3~Q-APHD-vBDv^=aj
z)#PT_$txMw(@P$dOxKl$l<#rq$$Dt0=65=@H=KtYe!I$<(E`uU0X3;V7{aA=e8RV^
zVIOo{@*Qf+a7XAxh6FgGB{dq6qX+vgQ~{KLzSHo~G)fO=)ej{agP<j%rYm#co0pdI
z;6*+}KS~Rn(gtcvD|M&@J|hc81dOc{MO5ES=O}J^G^?6uHzOWYGjH6YQ-`eV{4$6l
zS`ENIS}{zPaO+9Ge!i<f|8_ADj&;C!Ok$yFYY0x7oWVx3rrKSZ665wc6h9<0USeK*
zl7drJV4h|Scj8<)TId{%OPbQ7g`{n9Ci$Jw0`sx0r0CIsU%>EYVrkTMlV}X1kF*eQ
zLzWN(nP98{=^fIl;7xHn2e~LvE?xZZuM#@$t)eGPD{^#Y5}ui6NRO&vmirYsI5NRl
zBpI?1s-a6~cGpW8>!28>Ka&i(yX!n4`v%L@PrsK&BCC~QP{KN?D{|=Fb}MAH3b3i@
zA!60Nbq382O;smvw=yjCNlRTB(Qx{fASuWkc>hbxA@u~IMrE%k*_qJSAw5V(p_PtW
zR_A0C)SNt8D?(|aLdXg-yX(x3XNga1Kr?xL$VgBVn!A2&!Ha+1Uc81wfD|xQv}T<F
zV75^$Q-65u45iMHHJjgmVBi&TQbiLfAwXuo#2e+qoiT^70Y^54nC~G5ikt;A`KD_+
z3Tg@pN(h(HgB{1$O@Gl5?DPRJ&8QW0o~&E!z{F-t>>+TUBy}cFXmjd4za=apL3X?*
ze;X-SlJa~;rNY**l!-8?#9Z_eiPTQ0Qw^X^aY7a*o;`KV5|Sf|g5E6uJ;n)B$si*Y
zjp<<w3@~mD(a0J#oSIJQI`keZED2VtEK{4dXwh+GzNigpOs7<4-6!prj;aC_M^>jS
z7SRLCO%pWFGAdFrbg&&pSOVlgNa=?WMWYe&OmA&HB^@y>TkRfF^x^BWWMGGYG_vs|
zjH#ril8&@-VLf5t;7s`4PUl_+!v&O%y%C*ijH|tlE$suZ=}3SoEYY@AVxbVp5N5$S
z%4Ck*nS&;lE!jgdcq0Y`4<=vD(RcbOg2i%*&?ww6DrBgpp@EP5+9+*DQFf3Bbrl_>
zHfaL0Eu++-j5F2$KdGQ$<w7C+LP<k|ViYxC1j-VZ09ue7%T9zJ31fv)xyXl#I5uq7
z$XWK(-)+)WY&B#+gn1OzM!w8qLwD4g&83}RVgZoy6-Q15)56pnhlLTKr%ApZsSHaX
z%XGn@8p<3pjT>GiB}Iu!W96AoK4^~TjiEL5+SezvChQe%q0yg+G<Fx&J7O4!NMcIR
zleXl8AtBdL1j-<T2q(zNAYtlN-(V1v;%3eYBc;<OC=8f<<8M^`7(QatXGlYO^=a^0
zRSzkF`?L{=c5sBpe)DB1I>}^07_C9KxJ{YlA_Kz60V(8l=9x=|a6`BFq72%B<RDX$
z{cBqfe=AGtiI|X0QDHQsA~TX6J*yHBY4{_`sAd92__(D6_>)xpT;%VYYs3n5tzGn4
z?7B%3BScvm0HI3?seMcm)1fv?AUra7DF-0=Q};h*$bu6FC!aJUIuij=F=aWhvutJ{
zPs|(hlhzQ6H3CLL8S#YlXA12v2L>A?YPA<);TD)Sz#!>p1NC@F9Cal@NdQuTCJ)(q
zoVvC}f+}eUBSudiv}QA4WJOtd*cdX$<O!K3slYEnVQPsUp%WSaq8UiFQK}t3euqjT
z6h>{Cmds;&B*hy|cj*_ZA}VI4o92Z}>7ir}dWSMf5txny$G`I`^;mk!#K4ePDK4pD
zDGMRe9d2IIv+7>Q8G%Tx1>FwCSOg5mXu!5d%D9^lYUYV8|1M%^%vvD*s01wrz~aY#
ze34YW!aKO5MlEWxs38=AWDDhK0)UcVO)A!a5k{O<Adv)HYjF^kaagrdX-#J8(k-V0
zBArgNSjhP_jl#>|*mr&e6@h%V9Vg6vJ>d}OF7d9EWzv$IC=51*=5M!?)NN;yY|%!7
z0Ade1LsHaG#~hdcnYfx=8SY05_Ughjs}>ojV|I_zTHT8JjA1Xw#13b5H%AL^z8rT`
zCFH!_g}raE;eU>}OA5Qfi>zH^ayfV4j2Z{lcm%t`<5F^?h4m`cO{FDv9qZPz@k__?
z$PPI83vv{vdTwGw<iVh#jW*y@K8i+)PO4=&fsCqHW?YeoDI7c&Z;0`|q9d`I!tZf*
z;33E()ZY>&E5)e-jw#34g&sy+5Z~dvT(vGZWWgug7P+kUJIAtyRcbEzYd^NvFv++a
zWc4l?uV<-|2h<V`45y)?BTs`?7w()PSp{*_^+}s0<NF|(Tp2P33kqKI`^H*g+MHwo
z!X*|kZH)9trQs*@!A%rwfKH~?h8Vi+2nSCcN;<DP%G`;EjtWIOG-+v?ZllC-9?P}N
z!+&F5k24L*?=|gEUR8|aFC8lHQmx7Ez{ke#1e1nGoQ271)2LQy5E`I!28ASrN2-Vq
z$fa$)X4T7$s!Bwe;>>qY1JnSA@&DCfCUvMf<`?CX45}UzJBAwEo5d%MGf4E6^8Jqs
zpJ)N8!EUHGX(qLusRFCv13jcm5Xx^URB*<0pOG<cvx;fB+I_I5KDrk@=a?XMwe3ru
z;uXq~q)Or|22!~iTbR&=cPFBg9Eu>o(i(~5+jdxKNrUjUv5QdWe%_dWMGr+PKQgoq
zwlwnMP}`YJT;poq>6~mykkJ_^_MoQlbg|pP4&Pnh2xlj?QfRdbGAy^`&^ClHb?_(|
zRMB$eA!B5<AOW8nUZuXcY8uxy@x_fxTRp0Q12t<L?z0nx>NehZ;=7tvLBrwDJz2^t
zax4OEhup3n`|bR~+tw#v9-sZdD3grk$j9l?5B9vCrT2|go0XSgVO&WyYoAe142wx5
zP0%rYJ4N!1gt1y!#dm%pmz0?Mr~8~LxBh{IMoU~Mmq+FR#;z1OOQKc1lxxz3C=5x|
z+HT`Y)$*&IQjKL*W#!OS38x~=miBD|^UM6fP@{*4k32Z^h=V25alGqS3>88}t8I$Z
zFio*0YmH}h#={aR$Zw8PSV#x8j7w-On8Bx-0i@EnD8X2?*3`sRYTEe8sv&_kJ&HtI
zk94q-=#DIH=4nYL6G1{Uc)rHLn25j)R<T>{)$*l6Ol*pK$BYC90#zRP^^2{JODPvI
za}Bkc+@Zs|Cok6tJ1Sb#)t8}6i3tuvnZJOj!i!2QConpzoesspt;j*)mkN2%tagZT
zYt%(Hc2F79=qX=)PI^^E3L*w+H8f(ms0*Hyh^#Pm$DxDXHHuIXEZ~7oqtRF^4>}Ix
z+|f-<?f%h5AnFYZQT6h;<#L49m!5fP+CN02fhxoD8oI_Af<A&@*qILgZ!}S5Y(iEl
z$14}qqHVVdn0i8Dls=-u7c{Fm_$onxUP-eyvtU?c56R?l#9H`nb3c>`pLso*)`ZnS
zXJX@N*FgIQMxn|bjXJv#2n@?;q#!39OO8>F;Jeux!hzT1%kOsB%IH8^=^^-GEi$-~
z6dJEmU2=nQsZTN-dur=fG#Raq2BOmzKqO-~^@;B}98aK2%vAbIwu(@kcDP775<W^*
zD--FZxa3lWb>kda#rCf?oRi#2P5`(c5G-J!4><z?Uo@_o1Y|Q5j4uuHDcmY8G^`Gk
z7J~zr1!nnnj2$V~A1q0VLMxJ7lRsjr(ko_Iw`1&crmA{(P^>h)p!YP$Gi60BawGDB
z3<R0#<O^);nV-#wLk5x_C>4^_T>z6BgIa=)ylWPR{Oopuun^Z`kf^R`r;Zs0jPf#_
zq8$_d!8>~Bb5&0bFrJ1B+=@=vAV-14P?|>Np_rl6>;oZXg}TJ>BG-N#G6`5uQ8~z}
zrgG9T;j)TT%YI$_RTU&f6oI(IGjSF1*sPjx4nQ9Hq*a7hUXkHF65Q!cIIS?#f*W{b
zc&_-^QlRWksgSVnIrWYYsu8m(ZMbUMS7xYLDjDIPSX06-?gb^1H1Cbvlwcb-h`_U8
z(lLl%Q~MDH3To+#Ar^BIb1x1H`AC5dO?#Woo`7w(3F?DaqY3o@^Oyt%UfiLqL8?`N
zy(L2i6(m<d#(L`dml|BE2B(BrfF=PQ`mv2MiWnsYGXOgwm=-bNRouqts4^<D$Py4W
zf~jl2ZLlZO#F$EAtFg9K+MqZd{U3p1s1XQdN!^5;&bH?%YuOl~8$*U-2&>BY#0))M
zWA=YwQB&jHUT0x`Xth|xBxRy0#8pLkhIEE92X#*(BLp#M7_CU+QIIhsA$KlHx?)ID
z6Od-#_V+KPwqb#Wm);X7Go4?J9}ItxNOXTm>m~hQDCh|_4ELb|Sux$#IwUkq493t5
zL%_0Am5(1ByZ;qUB%cLDaRUY+63g%|S(ynNMot*oT9!j8u2#klqoGZq&65@qn8<n~
z_2?B)T~XB96yhoqCA6_d70|S8m3JaXwfJM^IaEiY(3o155F3;xqEiaP@c2J{6sqY%
zm6;@N!8I5KeJmE8UIEo?TLcu5nh<q1R6vuna1bulny!J3Y?v{W>16e=qp(%p#9vwN
zJHgEf2TdP@VSyU#+maX#Wl%3+vL-?^`q1Vd$y4a~A3hn-AzaR6Pfc9WudHkR?FPMZ
zyGdnBEloCCIi1?h(R@*j5tPWYwVo{|EW{I9+BqJ{II5vP7{R6}(k6F75336gAAOl|
zK#jBAadH=Uo%V{YsSh~^Sta3<_73s%aFaghZ7z&lG+MZ8jGf|sT(r@`mvE8$ybW=5
zz$s^@9PQW|*RAckzb!6pU|acs{m;tkN;a0ej_YBEJafm{>97s0EXVnv_e9~i)6K(#
zT|Z!d6nFB$do%d*jy06J^6z}>w4G%6i26$yIh<#U9`-Ty%|>e{?ju19VYlT<?g}@=
zJQ*#FufCqmZzbZLY0tMq;Q`z|++7u<D!U_OL_3`T+AK0c5|jO9xpawJjpJqCx%`r6
zJ^7R*Edwf3l8!y#pw~p{4*X{XWVC>!F<0fkmmYLzlI$lrilW_GKmRxkw}}GSU0h*&
zmrfpl>X<a14eJg#a$a$-EH>ATq|0I5^^X^qj507Trj!CQ&UhmanZ%~+%$Jy04$f#u
zU+{{TXi&_!sr2KhsxCyAWTw06H8M*6k@!Ieep!xUGhH=}JH1DmB_2`-nLED<X;yoC
zKXGk|p3u?tF|FU`c&bizNvxC_Gfuo{01a^+H7=$r+Q4ugaBAkS3;mVQM;XOmLWW2*
z({%w}wQhsV)SoXk3d*Fa<L%)lSb+bnNDw()^c{BE8ee(h#?40upn^cDZE|MiZ7j5!
zT`)*0jtwBAtqmWwShjt65Yqd1ep+#EVNi&{L^|jZx^Il0K{!T(2|8ICMs*4jMmf%a
zJZi-FH32I0DyzZ~7LzUrK1c@<8$}pwx_w0U2(7k9T)W#$oZtDR2^7dEBTzsvQ+wE>
zg(H*Tr)h}_L&Qe0<A?n*IlJo$59~CoA#$bJ7pOBuk0B&Jfcr0{s6UNRu^X<Qy8HbX
zZ-5g_trk?9;DolBc~;l}0*v8Hzp6fJ9dlSA1+%4$wlNC`8l07+*j3N7`tPkDbXdN2
zMsTZy&O(*JPzV-1`18`2edt{oM;t`>$R8wU*28H5jnZQXgeVpwgSxvDaoSx+&)amA
zQS5}7Lm65^YZg89AZ&^>1;7o#DyaBEso;n2lHSa$h+tBm*bgJB$M1V&&fDNuuAH`S
z{I*vwGhcM}w)8)raI^gM|M}$KK6qjO`;=J@vw!#<=p3!RMsgTB0W%>9BN%Jgq?q*N
z1BGQu=t=h{L9PKRh0o#xLqBpdojc9N6d1PIV0w`m`44<5AFuaK<bVYpXUJ@QVU)=<
z!EY{Lof9yKYmT#*jkJR@K{8ROz&w~jZ8XZi!YA9SRzj2*Hb4-T%ak)VhOASzCGl{1
zv^r%K+oi(stA5g|GDm93#KIV&C&CZ6I*qx40b*g!8rqH5hJ^C~s#ZqLLakbZFE&;L
z=w*x$%^(SzSloh%Y+Zf)EeXe^1*7#e10Gp~+H%F~!Az1BAnPJf*Vw%<UBeyK_JrDz
zr7dIyc^U$YLNpr9=y$gXD?8S$!#Or&wF6AP;Uws33wsb+B6UZx1bitRAbJr|*9r=9
zUl{8UKagKq!@Z7LnQmq|m_n>`WJVP*IWQ*mgH`6{?_ZZA8p0NWU+eK35XPz4Qo)$O
zkw#I006LqDEHgR6K+EIBi#JSXXo4{LL@e+gORI>K?WrIUdbNd_tUd}&Q0o>`3;v1!
zb*!4h^vq98G-?DW@(g-Vn8ZSmjg5r|2^m`C8QYd7YkQ$JW8;u?3Mmb1&z(Nv3`|gs
z9>XI%9K0oB5gfUot3w$qc_cxLMvy6m1U=YivMoNMTX$VlE&9b`p_s!QMP3%yakc#J
z#j6?kj&7{eiU<!o*~s6!7)Mi^N(5!$97Mo6tOSf;jB`W_u5{+1PwYpE4mwW5!UjR~
z^D-JEA(FeuLWr%a?M>7v@%s~Nzic(a_Ou?3av+;D;j@r13!XiK88ysQl>C%3GOyA2
zNRf#Sg|sK9ORiYWOc9H5A{@hT<MjxyBq4%^sc-RmY)$+8p@d)V8eB1`6GcJvMDk%v
zpjAmDOIc)1(nZs>#n=(6lB+;+8(0-I-d6R*zjI=x+9>!riv>{v9$F2Ns(^~xlo$w~
zCU5`;S&o%KB}JrYp~b}0B5g@ha9&wNObmy5+UkXamUYALUV>OKa*a#d1aL{tDkzX+
zh$Y1!R(k?X?Zlf3XjsQhKx>?QkW$7(>fj@{t4FHcQAaV~P(5*n#@Hc53L#y6;+Y)A
z5v0r`(8@1V90EVl%Sg1;AYDF42`&(BVktBdN<?`GGGQ@#=f^47sOGARg;1`vfX-7w
zERc(tq|q4yL$R4)7NJvIF?ec@=BOYl!o>5yDh$x4(TRviOuhNHt3{Q_)l5bkok~eG
zXw&SVBRCMLAxumnlP{(~t$M(-B712r=|-<Td{-WEY8a#<TcyB*BJlkfEkO$g3<8U;
zO93!bEnHK2A+gomWB^*kP9$m6#vc_Cs8WlWK*H3fNmwEF7{+rCQq3Ph371ltivG}K
zP$2MWGNdA5KcAgm8B1UKN%Ziitqj(MM8$JUsIO-SV`~&2&tyl42N+C)=24Pi0728R
z3WP9SdePz=RgkF<nJTOqggDRvqDn_!_0n3S!LVG)CoLr0(nUl9Oe*f_4@^Pvl{Gmm
z6dBbC50EGQ!4F0FV@ZuOv=>EaKRBa^G06;g_4xf?)o{~^q^zP25T>3aEeHd0B^Ike
zfNTI|jm0R95o8F3D4@y!(!Rt|N|w&3t*JlyW=Esp4@ASoK_6uXZl*eoP+D46Q=b-D
zqkK+uGn?s&?X)szN&*M$yQ5DPI~zfX?qRVt20_gDqh8ULoC8OLD>k`R1)ZUqPKpsk
z=tS9vgbYG<@`+SoO`s=_KlIhrQEfQaG2l;3RM7{p2u_B$@zhe!Mp$o{wsy!UYz-r|
zO+IL3j_g4LXDEgBDl;P!j^G1^BZZhK2>I+<Y}678_Xya8%sPVd^idlgPRt3pFxrjL
z&2Sa+Pj$b%&&fr@1C8onUr!F^iw7rvVT-Ya%_oDJLA#n?L=zTi0&4I7c9w8sL)?X-
ztOprKt=o<3&9rA<njUO?_Ik3+PUi!e!fPIQNl)X_;lW13KGLe?LcJi(9=F#%aXwmD
z%fWQQ2nq|>+DuOlr{i!J+)kZgSI}W7cSVipTGxXgDojRQ4>|=CLr{=89LaPQoE7yw
z-FSCnxBK}kHYjS*b^JpP=MS_?jibCi)(*W6vf}`bxSb}{Fy(ZuYnQ&Q<#Xs=F1mcm
z9fkWTee3sL*688De4{6~ezMIxMG8!rWSd`(9k}Jm8n=&SMY|7%z5~z*GHrn%DRR5D
zpDy2&^y5iL1nW+o;SlV6oN2;AITNTLH-gZDe87<KODKQbL``b>B|2*`_1CYqdU9fE
z$6%|$6yn$HNy`B=hXj(Kf=H8VsX8dHU;?~L9Q@9RKMP@IvJ!gDJ9vd=ubN25XaUEQ
zQAk+9)L{yVew=2-Bp79yB2>T}961Ilulc#^uSB`^vFMr9{MO7x$S8=NY{DkE+|_)S
z1jok9=7ybdmOEOFN}Fhby>dn-!a^Vja!jEb`b$+s1~e0F(SyWO5W1_lxnV%l=n6$q
z=*h+~EKc=zt=CXN$oj)QIjE495kUl*)LluIg*UvOxReGl6KTQF5Gmjzmsx5K*B`Ia
z^pFoT60HpOTU0_YhEFhJsQe^WV?@D(a1<NC*+)~|#$x==55L^Rgs^L1mJ}S*44sOn
zY&e5=Z>)Y3v{Gck7z!*N3LBxJhv<^ni<*P?CRV^oN*IQ*BdJt|pQ11$&V&R6zP4w5
z!@}?nYdtyYDZUXJMj3t)x2h!puDg^9#@jh9V$SR<=)pObQpSqzLKeVDfCnjI=oF1n
zKrDh|thmexV+P@u+{W-FD-1j~F_zU-I5O}G-g)pDlMeiNI=#D2ui-8)j}nI(rTXI`
zeF*3r5?$>2h$2{py>*7L0C_v3k^}_i4>MsXfhZHdc%R<z0Trunvd1rhYBBWHunE<>
z>l+!4Ny8-u*Lvy$FYoblQAf_H=1h2l5*jAkIn0rJ1Zx7joEQyfdl*tqD@3}ksPKVM
z9X6ANwSRrg9ALe%v9iM_OmwP~pa#7TCR(h9GG%vYo=}EWq}XK+HAJ{ifdUhZTBNbL
z^T~@jvp<|Wh}oT-e1IIJ0eU5!hy+Z3_N>RrGx#WBeyZWp49ZyN8=TIgphXjJ3XM+2
zD)Gb3^qdnD8azcUl!v{4+utpG-Tbs~&!7DOL=&H*Q60dU5ojb5VAKRB6PWGohic5C
zEV0LWK*!;9Da?y9*ljEplZ-v{%-hfZUqZ{gG4PIw!1o)u;l`j}YZyura|^L#nRj>v
z4uv(8Va3s_YwScIQOF)d$*?38q5VRv6r$N^NW5+wf=*s()4m5*&rpbUq5Tl{EMyvv
zVDHd2&N2smu!7ib>~;#T>AbX~QOx!DPEMS`d6LCP1(quU93;p*=0l7!%)$qTF=q1{
zKe@!YN{qCPVT6xLoExV_idLqi0XeKZSy%sZM)qJ>YZ$B33`M85>DlZFgG@A3=+;g%
z{miJFtSEAxnGO&N8@LavUQPCqydK<HZHQt?;eL5!>D)Wrqfr=VSy)F7y^C)6*-TK#
zl^U_^>^8MnVj~$$E%qH3(b0{x&IT0?Mj(~x7O`AKU}wjPZgLZLbUReQK&5>Qu}mur
z!z^1+Lzy0b($Q8@7~xFRxzU0^{eEcJ6neLQdr__7h6fkd4mF|%#%3O__pwl5O2BMR
z9%SK8Ifosr1+rXTB-<6Ld|F|Nko{{U5c`qfM2EOz>m;=3r5JKb?{{;=Rdibn0NkGX
zxyw4X)H?D@8jW=~M_~==s6yrh1{MlwXo4V0goBdlri+#jXYs8ayzjSS^J}*YYnE~8
zE#rA(Im0!_sm4TRWG>4}#v0UU5ovHdg0P#yPXCUgGwHO9xXIcThc||;2|@{M?=iCo
zO=W&#2m$Kx{i5Gm<C%a2xkE@OEx>7dmmkG6w?}IJqz{T{sOE!J=CLS;CWI@D`b+ZB
z8Fvwzw+J}2kaMWOpysqi(+*(5h}l`BtDucYXqERkyDx`fC6q7Py;V5z4}XD-=c+l^
zvuY5+kI@Ba;S7AFyJ5$q4^6O);59=QB3I;TE@-$6>}G|jF#-~Ioz5_GL*i?uN+~m{
z?ZxFM-m{FQwBZjTyOJo&TFczxgfKJ3L;_iJq+ulUq#G^7$Z}Rh?y40+^iXYUXo6pI
zjZHEWj~UN8qKKT;LFj@bLh_rY_Iy^YcR0DkDa546M9^+o%Z05G)bK$d7owSIa!mVK
zf3FeI5-J%cRItJziwZD@tD#HrNR$R*OC2I85cbq{_&yyuRa0wZ=$#r9Xh;+Vy|wJ2
zC_@Xzy_OF|ZS!kBj8-+2p=OZYGOV<4(ldeCoo0~kxWDQY8+lqWHWm#rNf9QZxeC%q
zHz54Xj4(jT7#%ew&lIl_oFWz9SSke}P;(mN$T|oSQY+Y3I_7{6YZY&M`^%EyQFq{k
zIs~zt8Bm|Qa$tk}Qm76icTOo{7acZ$$DE!hWi&@+=i(=$pa~4H{jZnMX;77+2u)4;
zt^bleRLx2HM2s}F;hv~xSj32Agu_yf=$&sg9SDeiN)?!3E}rpLl4t?70G-??W2Z4C
ziUA>a9=|xUCP-Jl$z;GG2J@;O<g6$(W~pDwCDL5=ig5+W&oJ<Ydo-m@Vg+#xj^qdl
z1~TJ=xH}*SJ5H?FAyyI0OhGb7Rde{<>|^m})gm(CjDn<E6~tPJ2541UBWGlhHN=FB
zrRdaXpb@o$<M02DidRh|rZdcWu1aHeQcB$~aVZh5rCQmvQW9FTKcy^yV;UMZ^C0gz
z&>bK5|CYY?r6WJAPEbV4s2Hn77SUn3@rkjrL@7+K&Y_`YmQfUOVmP=*AT*F<V@RNX
zgqvi#u`#rCPK0A%VoUY-AHIV)A7i50$p=@w0(FEmF~bUS)@YFrh1AqxFri1=^ByUq
z+o%m~0l-RwND~YFM0+?>H*V`F4x&~Y&Y(Z6g)c<AiRqoJt{k+$I$(lzZVly_4n>@H
zAgqBML0}?BM|`Js8QR?^3_(1bLR!?(4`|aNG_4E^>D90kTu#)gdDPZ2VPT?bdhu3;
z7{Kb;Nd_^skgrRq9e?5hzFx=ib2u^-icq&4tMoZ?fez)so}5Nb_xYV$rHF@eG)ok{
zZg=H6;%EZ<!fA1_TT%F9PS?HYuTG+FI#@yk#nvVxdyv)G(8ofwhsBB!Qx5t97KN>v
z;}QGO(Hwe;K4X2EaGu(dB?v%Ri6{zxlB7t#>Wcn|k+H&sl^!SFUu0!7VG?^NH;5cO
z`xw<Zl2Ia>)2@_W;kT(^!YSBbZL};u*b8YPU5_{n1UNd5zh>BKtdAePxxvYe!yCAr
z5lyka5cB#y``I1ixU1e+qc^wH>D}M6lM@zoq8{Ps+bhHQrFcU7Ilu8({Po5s3w&X~
z{)RS%@f-2Hv`?QD#&0qal@;H?9k<Mz8cF1WxvFm&FsDaw5_NdPeA&RRu}w42d+0ri
z)wr|6<GhsrvCfWxLy*5%u>t}HnxM#?JT&dj<NGsN*!6|%fq1mh`>Tng>gRhGQDS(!
zQ74i?h=(>gSmKnAMf)3fA=>()01hsQa>^-&QaTpOUB-)SzYKD~!TIDAg2Ef}^%P)H
zumh)e3Mth=5WaT-HXA~J@na^wqBug&rD99+Rs!R#7?F9~qKkbKDC(sbH|-}8EG$iy
zEh_P8ukmqU?|{^dN<d*k+yPE}BzMT1$Tq~X2*6H59VZ>c4msILaKpU5PlpwM;AOIp
zzYYKXaIH$1Q%jj%?Xl$59$^(KW#}%vE7Hw@7D|UHgB%a%edn&QwZ8$Doqq5Bg4N4_
z;=Lwp6WhfJa^<Bf5=|^5#6BCz5FAiQf}Js3W1;~%S3~f^<`4s?UvPgjU)%Lkj3h>J
zumM5s7b9rW#8^rhc?NKV5S$4dc9qqLPUIZ)@%Q5#Q749471e=*RFr)RACrKMc^uXk
z7Z4{&qAvLE46HKv(|H<ml*pR;*WYHyFlIaan?;Fn!7Z`cm?KPfD;jNRy^_x^er||+
zbHOz}a!}5V7J74uAfZgJ0W<o8<p&Egl5w>g(-HlJzs0E8#O#<q#EqDmJn4|eog1`P
zwDq-Kp;1`Juv9CZ&U#>!N^Gs(N=7Y5`wL9V246X$PYqha1;(60bQhUH+W_zb+SMT`
za@c8E#A-0MGS=7r<Py3`u%p2eE$dG2{?qD2J03#dMInX`f9x7-w4tvVh<YnI`>ltp
zs5kd`IMx88oFT<)Y;*9!oU4dXaCDsph%#J62kNlmps0y7EI<D5RiBOE-A+w4tB9b2
z8j9dhiP_B5f_~l-@#q6ssoSEiVpnE`gU}96tT5e<#6(NLC{2mygYnYEk?n9TVH5&G
zls|$1(`u+5Kk(!$pqtJ@o%!YlVjo)FCUGaFFjWklUe1`q9*$LJtu4U`t-Kbxlb%wL
z4sqcm2t&t-7%5k>#bR#FX&Sl<GDoLKI8s6}<nbdv@%+w$yzOUKtvohy;%<(9n6n^j
zU%l)qNB_ES=2?&xr~HTPe;fWmI}7r@-yqPLBS=wYxbeJ9kc9Dm7V3UAU-#=Hl}JBZ
zBA*98&6Qxcs~|kd6Dy+`c?lg;Z|V#EX=y#CP-143<knE?bihEjjnsAtPuDwtAz$rl
z4ET+x$61`mKG0cJCl{LKypSImD@H*%EMvUnv9U%9-A-4opF1oHcKjzeBFY}j&>n?5
z*|}1bpUntfqe$FwyjIK&>};ftuLAJ#uC-NE$1=l8N4_|~iVeak@QH$ht!3|d%~Sbm
zqfsmt9r-i#Mr7k_BknMSZMQu3_{3twwXR#*iP-(YlEhe%=vU1YKx>t1lWG>L6!VC$
z88P4UK%fu<E{qfj!1U5tsaCk>a=50*>Kp%@S&n_zh@fw^PmeHpz=<2wkF~ZDvzxQI
zKD&%|S7W?vVI2GP1Lug{YPLMgB;(r%wuT+JT@fZNS!hcfSR4(F7nWnC{f$r<f>Bty
zrr@Awt0%tsFV-Lj9ENhZ935MU1w;c1{{)%A#M;G#8(LI{7F>fm@dTY3whs=D<nZa(
z_j3I0Iht=OTot|*LvF9bPIrWHSH(AH_6B3+(J;J+z1`M6J6Oj4+17YOVFcT68dF-l
za;;~2GL{?iu0jq<5UFydQsjJ4Tv-$p^FeEDYbob>&5}1(4A*(CZ0b6C;~rMYmYa!#
zam-5%Qw*}$8p^S5aGHE5Xyi+|lAA4c`>l&c@3s8EEw5^3@31{<O{rXV%Wjmh{i$CY
zvwFiK_MN|uIpV|Bb@86QdR-1fR}^LZ(0XKaTQEFkzpr#CCX5%3hNYqtj}`HnAM_{0
z$uQhrelQ-J@KJY2;e!M~h<a>_cRK`a2u_uG&Ryjk@C#n(?sr0WsGk4WlQNi{)~dqR
zDE3M_KVpxrwM&<DTd=1DgX>fK|Cq17Bwkn#!#Y-YTp!6H;~fs+7yF<;bWOag5$1Zg
zuN>QC-4XS=HvKGeC}w|ch#6iWOy=*X?Wj3Rqh;6n;YfI?z5QAm1b1joIAMGHt%65~
zBA*_xx7*yx#?WLpK9f6ik0X!5375n}-dGKRjiY1HCyHIoMFbM#Rb%$@e5?HQJ%3}S
z3KqzqkMyEQV%EUgZr>VoN9&dsZJo3ROIaT$A*bL3j#&w%(I{oM=Q_q~OtMxv7f=sR
zz>4C{*l>7vSwbA;OPoOlxW0O??+sdvtp{fx{`r?xa}7c#QK^wfQX*zLgU{T|HE~6n
z%^(x?TP=Iik8p|x>k$)SUA%0#yy)|L{b*z?ss}n)f&Z%cXyI&FhZR1sIPFM*khwF$
z9_|qFq$UVf$9h=<9HYGSkPV)G`e6!YLLWH`;;3QHgK#Jc#kJd`9LY>+*0X9xn^a}r
zF6Eeen8LDUK!ccCk&j8jvTB#yjC7~nWOo@7N^XvIuw0OTYEAvwpKJtEkOP}4Cmy-)
zmoi>8&&+Wfaki8>=mmSdpb_VY0IrO(<_yDVjVi0raiS+4RJ%i&z4&uOO*<~2H@%#^
z_aNJJf{RNG7SWnUzFEp#eP<@xUdbW<mbETFQmN#)v0}=`*2X5O0jkRCZibeN^)r&A
zg-SS5;amp-bkL91<$Fz}i>~!%){Pgf=m0zT<!o5>+}uI*M$_4z8Cs<tm$Id-+bs2Y
z`QA)%%2`g7fnP#JaojBBhw>J(f!VM+F6EniN$KWhvzlioCvI)ah6m&AkHk$YzK7#x
zu?Mrfd{^X+hs}`{@rrR&51T}BuGy8dgFIhXhr$Z@zSMBs9v_W%?>*?CMv->k9<@>K
zuC+3(G>vBKs+2QRpV^5%rr-3b>iONYZ*3cotQ}~nI<z3)Lzi03nDN(w5W|!@?yA)v
zn_;5v))8wjY#S|B^Raa>W(BHCgO&5@mR-8IxwRgY7jf#KbjkKi(+Z9~aS6&^x{GDj
z%Td;9(shhJ&kYX6b&r9vyk<CZX)9~Nk3C)>A1xDL=CM}Wb$c?l{1JA+CSqQ2xFpD|
zjtOtaZXE3m@^LHIm0v=DYI`LcWL*bwD&+#i%=+vS`3!lVhRxdD%F#p1Dn;d7=*8+D
zl3`gsNf!n8`eCb8*<af}R#Q%%R7;}Bn&mW+G%s>(7hW<o*z}0QeKp-MiB*uZI-mV?
zDWYT5m~ZM;Wx^wY*U-s}p*^umXmr=*C2CDS^nxfaRLZc>otFKGHR^Ddov|RpiFbr?
zX|d;f`KHrsviUI?s62Azpe7!<$9C@jFX$P1gTx|E+x&ce2#G*X#gZt?YSypf4)z3b
z!Mk){iIv7<NoiK&e3087j-lQdz3meyzA^&1Egw|y4n3$t1~$eAK(;z=HiyQUI;fn@
zrL5!nD~HRgym3R(k4`X}J`)#&s$$VXEZm_Uobgirky3tpt{KGfHF0TcXf+v%W`H2)
zhv-#_eOtoNo^jsT%_!%rjj`|a6MFZ=6XdH|y2vV3!e*wF<3)TX=mVSbe!W#>8-++x
zcN}kw>qGw57#+9$p}0Y9XRqIiSCwP8%l97f?4h5Yj7QuR<9>5!RkJ(ZF?Lnlx;O40
z>2}@`hnqd8H!goBj^g3?x8wdDyhG{j4+onghn=A(<8ZI@<-OZC#dXWyws&x7*|Cr>
zgZ$0C_c*Q1JC=BV>)HE8D)E><^rw?u{^Z^pKeIRb{n}0YLa%H2#Vg0I?Z0k+ZRJP9
z-f-s!<KD34WgghDs5x@TA8KgRgtM8j;M#Z;iEC_y$I;Ml`Vr@B^39=-^xFQ&zR2CS
zwfWZAeI#!2voDHQ=3Q@NG~{h+4rNF7_&bU%gf(h?#;II`8M1qCI26Ul;;7u(6nAwy
zB{sw^we4-6akj=oA6@a~p$8}Tc)!lWNTu7kZ%eo%?AjVHiJM*fKiZqQ&RhA~kJR0j
zi~9RlMq7V$?|soH96z>i`@~D*xA^s8C$2R38;D0dudz37)}x_H%*`X!y?*^5!c%EZ
z`t{{|<L&#Go6kx#GTwX88yWZC)A)=(?)ja2Cz~tZ#p3QPiFf#Qr)!)+e9&P<9$7J7
z>{LzjiMO;PY7Vk@s8_Lal)fvj@36a`jQ3Zra(0Bx-W%hcDtuQs;<YPw+VS>%{kGq`
z&*tNI@Nxa#Xl&2je!XifTwS>H-uzTUUhi<czlUIw@qq7-$G5M0EPf)6#~YO>E|Wff
zn75JM>i1o`EB^mT9ocs|4)acDSNw^?_VAPO*x}x<#<!1*A6ooa{2+yUzdC+Aj^h=3
zoL%T1&HxQR*;ut9{@;_m#qm9S68OO1=d{r-+8E$_M8f!6U%%|1o$g&!Cb-oV#a9$~
zU56;i7e?-icmZkG2ncz+?-Pf5ztipP+}pgaKfc@PtvnVVABo*})OLk$i?@&e%o6*H
z<14RtWmkFsI$m804>hjaSMYiJWRHCP`!1Qf>AltshxRvMHl3E&9}UwVddMepd-yZ)
z_#pxWJBS_~-wQWsa{H4ezO^eHKWvSRH*WeBzK(Oe&)!kqK7Qz?E#c01rMoHI6}86o
z-c`M;{F%v5HbyW1;{L|)iFhvuaANF-(YFuhzxYYQOt;75G5Ci)_KA1;)^>lKnBRSW
zAAPcM9f6qf<?1wNx{#yZe<mQdz4Ecb_VInz=)1d1mHh>~_tM~4lymO8#NM^-lJy$6
z$k*r*0UL<7(}#^z%tdiWcij8Q!s8L0Rw%4%hyo9F?;H8zD%&6Ld;foNPQ>wc?{>$b
zKkp9jj!Tcl$6BrNYgkO~8remE?dEo!7>U<YY`kaq4tjjkWmNiNj^U2S+k>-%fDOm2
zBoZY==Q~dKU2*IUPr|mh?<nk~+d~ua=&yE-F_k`2sK1AB%V?bu>Ah4z5xrM**$vj4
zeBKG)-{^qE#vo(ZfCr-uf*5<_-b;6d5Be2?r;J2p-yX)xaeAXVqttlMU&M&S7ugi*
z{iMypz~tz|Zu0iS<^MSek3K<EaPM~P1z0oMxT(h(KYW||-83g}dYMhTB7}3VbGJr$
zF9WtK9P+&E=%Jgw5oWfJzr9uP#zp(eeXk@wwr#91TDh(~c6hX~{S$G3#ZvnZ3xcp8
z36U_YW*lN-b<HXQ5)((XhA6m?H~AdK<~yE;wCC;7#%iZYFNc^Y`#7|SJRGABxsk20
zb)R7(owY({LVVL@@cob-!BqIQEB3t1XdiE6-4zA5?|qV`B)_}ca;IXt7d0)e+vB0k
z%I4CHJ6Z_#zs~+5rv4@VDDMpX!9^uRU5m!>xFm$gmII07F>xv)y({vgm(zz44<hf5
zS!Cn<NJt#;?s#PulOkUEX(v<fsxctB`^vml73afdv#WMA#(o}Uja2xkD-3h?_RBGG
z9uN2J**=cufQMas;5VjLmz&w{g&7y4!|BaA_wd$OX#MzyEkz_)@B;=kz!dS=yB|+t
z!#fJ`=r#9UGFt9hF}`_aU2l<<9(2Y)+Owkok#?t-U-?Q7N{x+Rn8yd4V{w>Alw%8X
zpxH#nlgidV>;32&tMo)T#(RY@wR%TPune)zj>ewl1{r^4wl~5s7#*=5c<N=53_l&|
zsE%z>K=cY9JC5U1qrcfy@NDH+q4}PDYf3TK#WAO+I6fDzh{8;hC>JkyHCglVM&#qf
zMehJZRu0qCL6&vh6X7MUs}oBZEAYd81<SQoRI(N?de*HkR&tD@b(@1PgMlOzVX>F5
zGYxm+g*HojoIXzhvz42|@PHRy;xk0uoWNT8fq0ai^u6_7_Ipa<M5F_J8$(7>r_A*Q
zEij?F_mMiz&Cy9tQ*G4&tgv*^Xk9^A{Kul_gpYJxe8AmbvFoLa`dU$@M4*74-~XpC
zAxLE2_^-xW9d9=_cL+<ure0*@p_R8v2mzM(Hr6jMAAF{n3%s~?l#pWB3??v%N4&hl
zAM4n*Fgqe!ov5N+%JT*oz64ghr^POAV!~V7!nHAW?G;-c%Y&i4t~=&iOJc$cUHRgU
z&(Asjw+d$c-r9EjZ|$@3KbA|y|43MV!ijF}eyH}Yp`FpK-YN0F6F+eAzo(<W<nSNv
z;%YxS=o8zsFrac)kSpbQ@FNCvW3!Hc`&BQ;xt*L<-x&EGK4V=LrO#}%N`-uVwNFU_
z%K_n%YyH->zSXKkIkK^-eJZlI>g&}FzLES5q$Q>GNsaS>$A9kPm<hywXtz&nCmbnu
zJ5eLRa3zpbW%m&ecr!;4W31&70?y6QUXA}2w(Rk+KFArRR>mH*x)k^fNA6WLBjRlK
zNRL8`yo|`{a{_EGo0Kb>d_BqLC@Nj{By&oUGTU0?TWbb`vd!LUFEKsql@I;|ufT<T
zrSQbMB2D=?TNv5VjhrMQig!3?ajwRSUHt6G+Rib9jCas0mG>9zHKgyTS=%{xfD6Sz
z8J#`qtr1a>2hUL?D=KBL$F~`|hX_eH@;{s$I}E&J?JkmENYr1!0{d&9<)2sZ5(T3}
zAW>g7qP2!d0-K~cOYDgAa^QGHKf`MY+-plh2S7Ml&_&p*Vb1>3a|I_k2<41Ap1vtk
zT!=g3J=$_*5D8kiMMl)NW9#v2Uv70p&1S}`d-Z4&da1+99`s$y*9nH8k{NM)H|NS7
z>CEbl`;6@p;K<krnsL|aoS@{Vjt3i+GZiG|dS~4C?5z<8TSkkvv#}v5Dox%PL>C2>
zEDlU=WiH5H^?s{V2L~~qET6>PTy=(*K`&bQ^?GJI!A=y>%A9;oyjMKxjAxwHOh*^h
zDh)fBXsEnZvFwA5uu((s{YN6n^=1gqHhnzvtW&S%tX+@6??$PdDdqggrH|{qUfX%H
znX|4(?^zw=n}W~(@xgmq8JAslI$LOlm9b)H)^_Xm+NfL}s}pI0sdmS8jZ)^#_QB3Z
zSFW>psdlzD@hw@+a46naTiIBg8@gz;*gLj3+-!~dRW}z8mbZ4V#S_hz>^zi|j{n9@
zmhW9(A;RNr?(ix(?W$+2CMR<2xbbCwQC<6rVN{Rm;UmP0!YjKYq@A^G(*fJfz1z*y
zJF*S!5mt&3v23E}y_vdeIh0w#EOx3{&+_X<W^Mnc>R~)IUfjk=l&<j|_Q&hpmBG>S
z-sQPRYJPp{XO<Hkuvn5>#I&pcch-`;t*=`WRc1B<Wcg+fj&O3;)|Uy_f<<c^xxT1e
zLxc$mI7}igL4{S#sv}-?qFphPK?h5@6}dHQNcN{jP)*fCel;5{kFx<mB!#wOb_MHs
zf^l`LG~qDUq-fTAoIYR?9PKAEw$<`GvOcqb45vOAEb=|XGXs?(bX}f~MIQ|toG@ri
zLPr>sbM=)3Ar4l8#a?D=?VBvgEl~5NsE8p;zvY4`YaMKm)Pzvzw#v<5gKIH^xEE##
zHc}Y|i@586Nq&*YNGXf69yIHDr>2P%WJ`Q86w%;^$8t10;y&W@Uy9Z-ld1%|tWptC
zzqmw<zZz$)fMmcaBb`KJ6lf{egNqqqCY;SlDh@s*ettEJ9&c2$Arw2EF}o0i$Sf$a
zwl@Y|2Wje1%?b}R5MO(@N2HrhRoy!AQ#IiSS<hYW=ft!=<jjKrVz4<vZLZ~(a-|IT
zD~kJUUZ+SVO2yh&YTBSJSF@v)Qr^EFR8u$q5_GQf=t$#{A~s2*OlW7fS6`YfMY++M
z2z0@1IE61>Gcg`eqs=?+X#|x`HD<Hh;byBjC%7eYT#3(U#YFn;dN~SSQrcV_A-rR)
zZw5@1Qogj0|84Z>E5sg!Mb(*SL1|*0AUHKENj&wlUDC3i`2hQ#lsBVF83x93eUcim
zg|-d2eAdk!hM2jEl@)WB6l0zPuF^!w)Hgm3iq#c`R4?-gTW>5=KUfo0hPBN~Ax67^
zJ_~B<hqpE#*ja+()kd+Baii*Bh#hKG>Lo;LEybx)RgSejgcheFVo0y}t06V=E5~1T
zL#fC#LGM<ba(`i^o2j~ueGN*j{8W^$bl4up#Bw$AY4)-)*GjXulfB+0YT1A$W-*mr
zsO@b)m%BFq=2+4Pb68eQ=9;8t(9D`l&XS?JZ{PRwD1c)uBuG7LRWbs|GDp{#OT@7P
z<Rs%mb_Es%7$8K0#WE(G;d!~tZe0T@S0W{-WyR$RLt3j<bMX!LT{1k_LOwWGV0GMH
z4nexPvI5?%JrPA7hWTJzgGwy&jZxuMb~lVTnIB~9ypcoe@-i*5S2j5-m*#Jam=i@|
z=P*aq5f^VS!=Ru>K2)rZ-a-sEi`&jzx%I@$utKyZ!3@4jGaZOJ)u0{jYE)qngsqO~
zMv-Kd_D)H*LI#k+fnBDXAPFit4YMEmRx|$F?QGQRts2W(3?a;-D;hla<+<ksM-I=5
z-j5-r)`5BshGREpEm|{GI#ngv-xmR25dnB(szAEIbhpat???X<?-beBQHbheg=W^W
zuB?lxeJ~ZAtpRd5Qo)IWA1!-U;C|V?w~k6Z6y4x6@$1oW9@c%dz^tag%2TS-qHw3R
zr)3^Rjn+-(k#FggSkBCb%c*^^&OF<S*dZZpHt#M&=PF2YmCQt-h~YlPQ|?cnQ3i*F
zECl1eCfcq4V7~Iy1B-zY^_~lUngsS|!7K?3DvbwVGT>WNAAB|9+laDkm_mv<GRVTQ
zs{RtsFZ2F_-U)~z_GLM&z_tptJhxJ*cuR{}tFe~DkRvQ<m}O@B$A!t2)im0Wb&{13
z>0}AM4rJDsR&pJO8V&2=|9-Jws=y`^MGX*Sjjh8oX@N-#mT$|tUQmg0-~-w-Nw)#!
zzOHRxxGeCYrkjs@i(chk-Fa`B|BBamcjZluE9>>!BELKOLfqFKu`L~PE-Nf9DSNLf
zT-PiY9(3<rn^t&h^xmzN8~TpAmE4=+Xzd-X$!INMg2HE5{`_Nw=KBg`OC7s#Mg1p!
zrTp~f+U0KjiN@r%bx$9P=Dm>v$mQ}+ZH|&AzVuTUF$0$~32T+!Yni?IT8NBc(U-EX
zT$X({uZ~28I@ZZM6&cH2%^a=NH@YmisLmOA8&2lA2IZS^IoddFlee-y_3PWKn~N*f
zeP#3O8!K|PD;v?_?p9wuJWOnlgP(RQ^J;sIQ&=9p&HgF(-C@05_Rxyl+N1Tp$-|$U
zj5;P;4yR%w?41MU@=#%u-M#Gi+LMK^Z5Mv>(5aZid#*8<|J?q{(#@S-W!-~y$Vf}i
zMD1O^)Sxb3U2(V7-Fr7Tu3WeFL-oJiR~=~J3$PlLGRx}r8oOMs+Kn6Q%ZmNWZ>ih$
z29{lUPqD@ekbM1<HIfN3R}`Fbxuf5$ZQ68;Jy7YnIr@6f&4=_mfaF@Gd%V!?azC}k
zc5k;IahJONn>#MPrGHCL<Kp3g$@P7Q8egdOWtKRcgzLP+I~refUAXj@*JQ6;GwLpL
zvptR6E%p9)_jC@{8^gt$CwY@_Fd~jNeB!sS)uIj1^m?~aUY2bvTX*A@o{MXnDz!$f
z*0`ZoAV$EkS0Z0yh28ejS{6D7Dz{`SNWi)QpXP^e_KDU3BWt{oeXi>*vzwdU*ShYC
z{`%T_=fJvU{qCloo3{4ce7JF_Z$n?_-Xg)a&L_i1Jhv-!n}z0t?XJqMs5cH(Zs~8_
zGO%U;vEiEz4f{98JvTS_dW?L>9skISBsD{686qpzvTPa7_Pfh2ZuDry2+O>#p<`oC
zr@gscwi-PH@4jW=-8}=9T5XwKEDo>_7)2c7zQa4=dEv^Y3!#-O-IZLfu0LI=T)$@d
zvf{v&^4PNezDNDW;N<6y7mKwegrRnK+dI~Tqpw@N=89LY*u2!c+I_@b_Nhv}KCrH5
z00Q<OYV<UmKAe&$oZ9?z)y9B)LUYEiQdzaZT_!T^f#p5*{zmm?Z#dV}SbVtnmf{Vy
z@IeQ%?N&Hepu%g*SK6;F!z+Gkw-j$&-qT;{8T_3wmgGkV551-Mzo>D|V%|y}D=hJ%
z*3yr>&Kb4KD>l1VxyzoWGd&M2f8X)}I$r5nSMP64AUtm=E-4-^e47K1!{gU1AB=}S
z@;cYP;&scKo61+?ay{)Xzis)u-7U4A{{6!@`H%Ju9P0V&#_`3)wIM<C+nq`8hVNbS
zxns2rEt|<iPzy(;+V5fp+5MZ>Z)PC2l*6!QP4uiP+`E{Ubvii^+LgJwyuqzt<<@Gq
z+{g&5+p?_xiQxhN5GUZA(lJg?|FpNWdxz_+94mKMt}cJdt*>!|_f@{~?)O#tH{Vhp
zsE-|bw6EBAZ}F~L^rz<7<{Gc{X=i9(p$qa?9AD!u+vhS0%iZ<sZh=kfe1FM6-=n-o
z_J!IF6MGhigrlAAr^fIfdN?YqSHko%<{G;*i`8_?fLrTWSFFRS#$c;exVGqU&?zV*
zK8{oFgf+-lqp@tDzO2z0*gWyk8xKEv^I>)}G7)d|vd6H*dHs{ki@JvPy>g9fmk}Y?
zeZtJH&Ko!1V&7aJ=FPi96L-~?6dw<dg_)714|*55*Ijh=(oe0~<1YOil;7i4-t6|g
zzS48!x}J4|-bWYT95o&tXoWo|7CX_70{@=tpUQuA#NTkJhcix&%@Iu7;f!h5rg8<@
zfbJr*<i^d*-tn<zeFJ`VaI$MdgRfG<DzoWIDbp3+ZhzS=7wXwYW6QF}K)tc-=6LvK
zCMv&i7x9u-xjf-5pLBM-vU_FuINgAwl@*V;TY9c_mv`3J4SfEV{;h|Yf`k69T5UjE
zE29N>r?<ntt~pk?;&sjed$YUj3HN>O#Xnzv?dHms_1nI2(~~^|Q8ausI#zouDpWRw
z(Gu^Oe_gb*xOPtw<sh)_t_SUF?4_H^h|#ijjRDkQzsroiczuKU{ifRWNNP7qY^bnT
zJzjc^y{dq~t>3JEth>=&cGLEc-V}$`qtS!K4N=dN1fjyNJ>HHrJC?32e`M*BHSX2r
z&$-L*VN!4Ya)W8z!<_4{SN%&L?fXh!VIX>QVc2`n+2bug8h_+<-stO=7Mc&zi|h*b
zp2}O?O}C(=`<u&dY7YAjDzXuc71(rm+PiA?;<q@D-k~o}9N`2STDvQ(J#E{SPN=IG
zLD_OkabVxF{>hHTxwkmiA1^w8R^Wh7mnhsJ-MQNCy4|+v?v@5~bjvL_uDj(O9~<sP
z3lB!M+VzD$cJ??2oHgDKH(cqKkGV_xT{MDwg}dy1?l<fG>t0*mf<ikqT)!#iZHAv*
z{N_Rpf$Z>*uF=<RTzd7=aE-faA3AsQ%52X-y|(4hE&e+WN717L4d)PX?D0bQ)L&-!
zvV@7<oJQvmFc#8nww*0k>vjVjJ+Nijjdccc@(^lc`0KT6ibOwj9$d<7Y2j1<KTU5O
z+}3^V`4JGK$2iI>aed3)#i9)F5BEYKMM);?@vxdSkN4_c3X-9SLQoWCIf?-TieJ`m
zpT&4mziDP4FK}Uj5fodpX6v2iH6|o_RX0sdB{TJOGxH1@NT`IaEk%E*Q+HxA(yN=@
z>9ghh;coM~{T!&3<sIiOLEQWMo!>d%^F7~lewxD%+u~p5{bGgl(OS>(XFK5?>-yP`
zIo9K|&1dT>9+`ST#5<^x?ro)9{SIftE_#+-tXG+<)BJEdb`KX8(4BBTIFC#w_%y>h
zc1(LyJ*J#*xyLGAZLeLp);xpz-wL;#o_>l|<nU3@{P+K2fwC6WiPJ66-<*3{n~Pf2
zx%|BC=BwU<>vZwPKQ|mJ@)4i;0HIji>}tu#SQIzxVny@w!?n^6f^N6lFJTP`>l)__
zv7?vkGX%OoWw>p@t|)6d@A@w&9-K&ctvT+MwnL-;g8nm|>K=14MlRsu<I9}0Pc<!h
zTA7b2{|`#pMLE^Auje<L*=(WJGn|W<b3nJr`)@yTGgfG`6C=&++XhMEVbfV=`Z3|b
z$F@^)w*7d?>-t84sHZQrq`5;l)FJ+V_}3lfNAXVg7r*Z~;DYz`V~&3%@p5p9uMnmE
zDu<t?CFIZWua@`rbMm8BO)DyA@W<B^X_H0^V<eL?$D$@Swonm|jw3C-xnA7rqB&VT
z?Y+myFS;yF{mVTkb!L4a=$YkZ19{%MICst?ZsjaNYQAir3H{+d($3)~@<>9oWtk>t
z0w;n89k$(4{Tc?VU(t_l=onO6Xj@#>#4Uv<iP=$!<DRb<=F47<N1+46d)Vwm2;mn2
zO7!7sZJuCWx=t+g+5IjXQECUxbnNpTbHVE!?P8<MIV1QO=48a=35d8BajoJPtF`>5
zvyklpQ?@VZqACrCupItG%_=8RkOIdtSkD7ydi|x|Dd(L2)r9nKj%}sek6y<vc1@?k
zf`K|%cQA^t5&2K(1+O>PBa{!C_D~Y>)=_iF9xGTTKVj9xTWu}0x<o&u1==Tq&;IGZ
zctv+^N+oLrYCEPW9306RTWse$wh<-uClnEB2}cv=hIU%<y{?Nj%A<mgJfA?rfARMu
z-|g$eM2D+NWsY>rsgC)i`#@7E00BTnyQ4Cox|+N6lGjHL++6Z-=g;AguowDers|iC
zBT2LK_>*qOOz&6XZce$;V{UD%$Tz8GF&6|2S;N1g^N|a&*&qFnUp(d9^2$LFa2jRO
z0x_M_t3^ja1O)oCmhVwF_lA2PY|kW)VvV$4qkG4lN3_GH8DKrUDgci6b@TQ0()S@G
z`lWW02HVr^a4bvc#+vI<<A{2oX{lXvS4H=OalEJ0LF-#?wOsb|?RAZkcJqqv|3OcH
z&<tWgGu?Uo_2iM{uDLdIK&4F_XU6)=3jVfMsMPX5=8*^SFW37ezJ#7#<L=FfmouH~
zG3JxWm<H_=9Qt$_V9B%T`j}pH7wVWK3*BeAU*ovljGPZX3TVq1dP_5JfyKqGfSm0@
z1zTS);gkaIf@$DR0u&Uo-xp^ureCgKN~<IFU6nisIu!tUhydmGEPL1@Hd{@>FNN)s
z22TArpzt)c>xR;<&#3s-nf=Mb=A-PV$p`bES<`vE@P6sz{?Zof)&*x^DJu`wA3UE3
zXA;uw*@$qyECYnjF^KX8Hb}CV>Q;UB#s7n$`^2?oI^cT%K9@9mQ{(5@69LL8$60f_
zU71O2$ll#zGEaCYP27L<$fJ1n$;$)lN=A?0NL3WRrCP4#>;Ar`I3&-%9t#^AMzB1)
zHG8B{UwhnSQ4iqQ4-;iW3COHeetz^3%&K45df#zMtyMhN>DE^gfAUnU*TAn+T&90#
zLQKVAGoqN(JZMK7E55|X+kPSE|54Yyr(&<i=;YoqCL}T0Zw_KHNr?s|<nZkTpucwi
zZhIr)AP=YQuMr`KN_Hfm?wUabweqqWeqI$kHoQ|C>Gq98j$eFAx}SM%)BFv^(_~{q
z+t7&h91S@jX3C4!=Dp&koy{3KJ<XiJuO=uH8^PhjUv|QGjE^WI;ow2`CT<AGY45G&
zEvH;7-1AEvGOw_Yo%DV!cf3fc?;&6|#knt#|H#7wraJ7c{57a10qTT7(10B)yMU(y
zrkUJSR_cmnlU58i;Em?Ej!QJ0u@@4bV-A?!*mZ5SW5$E;WY{&q<mS|-+FwZ@gfa%`
zsB6tquBjUz<~9<yyh{m!hp~F@-|ln5?%0b&IOd4}*fmLDmU%Q@gELS(TO+_}`IknG
zLa%u@8#zwmMd)WLAK;TD@}Q>KQNn`<m;gfGyN25Z;V_YS)r|3A7unehX5-b_hFa5(
zsG}Wof09K#q^c*a!>-GRyyC7?bryPl_D=SeClYDUO1PRtCStP5$#U|rirN`9LD=A2
z*PEp`!*0+_{7@J8c|o*5#>bg2y{Df{+}t5Fwr`QiQ2Pc>4w9>Am6!;EnaiDE_k1#|
zME_10+ZV^(XTb}kICV3E*^TZc^tkyn9o1L#;~RSHTC4#n^SJSHog><rnOe&n0G{Gu
z52@U3kF`}mD7DZD7TSK+(C>J+!U*W`8!eh?XIBI$WL{Czw^iPKijVBahpSrQrS&K_
z9pYWa_1p$Pd4sELf799H_`_1Wf#I@93YP^Xn4a(D`HBkQU>**^@#5sDM`I#@kH{q8
zm2+Bs20&!8{P;YHRH>b2sSTjOF+sGk5&UhaKqZ%PD2-+1l70QbN|^(b9(7A(^4+Im
zr@Axx2QBvXd_6#aqGHSHvX=aYnya`USb0|hAeP|fx8}0BrJSEYE;V%UAH9<3fk^2A
zkp}Q-XW$w~^Pt@Uy!^#bkBajp<6-uXS|T9l8nPs*;gmRd^;AvM3x@=nb&ucjc(vo$
z)JL2^vre|2x~xrO^@HqbN}{3b)#gi9z_;g`+xqcaIKOzLu@gimI!TQe)RY;q7E}u0
zFz*(t{+UDenVjdBTJIT+TRmB3ac%9-{^}baWN-B@C5%z*bD^bCRx;$^n%HoqJem*h
z=hJ--;N9$uaeN~Y;WRcPgey%0(wjW~kT+yiy=rxR@mI|y{CKW=ldu<<rt@)Q8KFw&
z(W#$;6F0Pm+Esb{i2n!6s(}%#UQNq~&fHS_BG&4xGVUo%&yp>4%%r(v;`8?tz4uo<
z+#YVBn6gWq5ck)8Pk-Op>7L`1z8uUT`TO*5?73lwhL$-4DXn&yGf0%J4DoE30NHH#
zjy^Vgl(R~sgeh#pwCT8jjHrW^u$O*eH-zqSoNm`gDoT?=s`b-!(9vd7^=@XrxnHHN
z6kyJq&#PK~+J2<Tmgi1qHIO2j{-isbo{dKiJbEB@z+B*|0nk`CLFcS#FLfm031NS_
zb6j1rWgPzVFZshziTGn^TFZv7u}D1dFu-`QDh?zEsvu{YAku0>$u5w5l!qnG3IO)L
zzW6Ye%{Fy7V3I{*c}q*1=CTGqBQPy}%su5Ur*u~<cKWPwUoQaXPB|tv9Uyome<R^P
zq#ewtIrnxY`aEbE>|W_wp7<+%c%j{V(E#6kW&Ph10`4L8#Mkq8VV?b9$-KF}jzdvk
z#RTT8$iK168i8ntrN_sZ0(91zi!E?5Qi8$J<Mh2;&$lk96?Iv?LO8JwC@Z&Y6<mLK
zuFzRq3t+tZ&@hGGyJnZ21vMH*Cf-rTxOTuiZ1VnA^^}_jVCGYH-h&;=1^}B@zYzA>
zxa{ZWkNtlIH-oRY1fJjy0K`OU&(C*AvpsKI4`JZoYFGqgWyg%wad_ZiADqCO6;pj8
zx{*jMwY#LfpW}lK7^g-jv+`;tbsMiO&waSEZ1t>TxUm$E>)85I4#)IWNlIo7ayuHw
zrh<rdK$~<ftI6BSjUH50p$<8STEPpu{kvJ`u8bjU?_ApZj(!YSh8XP?2n<b|Ch?XB
z!r_%cl|brrU*9)G5HV!4fh1CGL6wE64_O#)S=QskAVYw)XaRHo4U0$8I6k{_HKxVY
zPqm+_835%n4*M`v+@X|N^?Y|}sv3et0^?L*#_keq$q2>e?U)<tmNKCR0G}zxE}XU9
zVIQbg@S3^o4~clR=YAACxKmijdQI9|d1I+u+0ldIfvb)<>ayoY!#=Cn+)8*yZy|0A
zV6Owx%(WQYhGai@D59}8R!Eh1SbR_Ze$ViJNTfW^<F_9e>GSo~H9QT+HvYThW&DSA
zNbyX*D**L+bDosmH}u>eiQj>FjwB3P)pT}2AGdKh%SuytlDT4~TKhVUVc3a~I_LDk
zw&MRj{`-|k|5*kFXe3ZW6PGj?0Um3<CPZ-YZ1Y4>a)(~i)1T0rxSU3WeyagD1D=lo
zG3N`FD)Gkl;Fo*y=VhGJ|Brr+3p2#~jz+EUGfkV^F)JW*NVD6Oy!TwC!sqZmZ>$%4
zMB>mpz7xzOWdGvKc845}jAxE?)tI_X$iG8~ea78eE6kfckP);=^XCZ%d}jc@&IhNy
z{iS!E*D!1VeHZ|hXklEYgTo!1S*S<=43uiPo^?sUhn-{2Nh54>!b8R(7!$FKVBjI)
znY?)~vG{FC7QCJgWfd8R7}#m-)?ZCeUCkW1p?ybnz~UK|WL?3v)*mbdt&jZ`rmzjt
ztRAF@^Bxa{Ks$ImJ=IW+r1`Eky_~7=?%>aVZdu<VHC3h`&;P2|4TI*hj)#mY4F7s(
z52wk07G4Y2PUrFp`~o1%9EGv0;U@^Z^Tm2oqq%dCmU+hl*ts#*3@j<{Ads1t@Ff2(
z^lGJDe~HCvg#a95>}_De>*mze<m-<g>1YQY9lK3vJ*;lPrXJ!fr@Uen!+mMp$l>52
zfKK5sfzIu2x{;Zkef`l%bxAv<CI^8m)l-h;mB|$WVc@(iHook1n<M9g=I0mw%egyV
z><N?=k$^5w#xE$13?m94Am-d#_`a`~ypY5grwl#|5f2M_OxTM|L<k7b=(sw25vry?
zaGf6oaB8&1W40G(&o^GK*VoKUJo!K)IDiWdsdPGZ1=fsZ_58&*?M07+7d8`5=ugE$
zW~Q}b*R@8&>}UtI<Ob~Jq!vAxI$Ejtx}JCK{EyeiaH3h*sXyw8F4=C}`TXD9`oMDv
zA<7Uc@7g=u&l0sj2A~wn*GZ7iq=PV!-QvuC*ur1K)UKHLRJ-orcIUJK&BqrMezF$u
zs?F_0uG|#}tc7FG)(;ulkq#La6`f4{278cEuULOhQ72!m`innci$QK6va#>!@M}y7
zXkOPcvvKlHC^OzvO_4!zdQyJW9$x~ZEN%CkKBDd*Xp`JuxIfX=$BpO7z2{)=@k;vz
z*33mm!P)BGj>k!Dez+BT*6F8%2&JeP;6ZyHj#6Tw>tSxivv}5k&&b$KTu{Iu@a*-O
zcq2Nsk=f8X;Pzy6QhS0hGtc=l7*EJv4d<L~#zDSjjHlBVjr2-`{NoTANCi?5lHri`
zyvm=g<=wJhYF+C&1h24P=yjQ{(w+V7fAHn=j{h?~VlWrM00L;%q%cmbyHhp?B{HkI
z&ujK{Z+i#Z49^GbK^&X_N=ElPC%is?g}$iPFowbZlw!+i62>@wR~t$nX{?!(m$93t
zF|p?~{fShK2cqn>4xKLhx#W$7v1euE*z9UU0emOB8DjN*IL()ET%Z(h`2Heg8Ogw#
zpC|N?Nv!OV^ZCr_54>~w4?(%akr2XrX!4TA!?W@{5_=2JxA0OkkIOERFY~TnHCD-&
z`8K)?B^BgtC1~TVc!hZ%(#KuAz7C4;yrt|#eH<bhc}9CDxZS$lT6-M7dew}_#II1x
zdd#Yg!K&N&9;l~<o80!iv86WiF=E;4=9JlqX>VztWwar}V7=lVy`3W81kjI-B^Fzb
z7ly|p487rHUNk=c+PkkLoHjkhpi-DMGcaewy;!5TQCz-F6@qL5T{TWpm|`J5WVFCz
znr04-LI?_y3)X@;yy#d@hpZ=rebm^T%^0sgJ~@*)5Sw=0+p6Louehl~O3*d~Hb#OT
zX%NK3h1g@HAL&NNR7Z}g8<Y)FHvmo6J7igT;>Jt&OV<e+4E{ZSPES}EkMU0*{UiY&
zc7@w-koMu#v7bpEnmP!zs6quRDz7i15uiSsJEyZ>a;`{n@d+>u&}=Y~HGy{XwZbpD
zO+B#$B`6gT8f!=`S9gNl`ffd$>^z=6Y<{M+aaNtDA`Bc-SlTgm4Gx_mg|8dAk{668
zm^ma4%ZS%+q&qX3n#7od)>r9+>M51Wq{{w0o0b0<Khg?L>aWN8cq%fw&&n4*p#aJC
zD$>wS5E|46lV-$RaEIU%%H@U79-*k&-f?h@M)PfhkDbS5OU=PN5aVUR%NQN0qR=O9
zQQn0jt)suqv>3^XKcA(b)9B31PJJh{D?Ij*T~=65C<sZL-)nib#ca11_V4Cq^y8<)
zv5_GD)Aa2Ysr$rFGv83gVb~PT#UX1U^^8Vf0<2wYCZt~3Iweo#w<569>A(4BZyCYq
zHgTlEG3Ewi;CB~XYYmyEX9BJK;c_$o?Lfx#&3&#@Y0LsMU~QOlage)$@JLYyUU{Jt
zu4@TWtPi)(C1C!J1x%)5TQ1MWuV&)ruKHc_7C29%u&E|HyoRp>9m!Z+Ks5wawkzRG
zqopCpq*JXVwlyW}4nL}<Ny|^dFD|%jq2n~;-Z1w3zSB)`#}7{W!9N)r{kcx!Umj3N
ztTmpVQkEG5EY0DAU3YIEmmutP53vWtAE+7p8Oq)r)NB=tlI0K#bQqL8h;lK63*v8l
zr@I4Gg&-bJzZ~31Z_L89b&}&Mc|(KNJ;*<YQmGd#(3qyrFNRHhpPyUun%=coFxGNr
zjSEy4r>JI`;~G_6(5=c>PPsR%Ws*(1fFnt*k0%Hu{iPh{6tcRXzxe`q+X3-45PKt`
znT$+3042-vswRe9EB>8dA|vckBK1fc0aIMWi}Re=(0FOMDhM``g&N+22NIep0q*Rs
zfS}K%UrdjvL23F`)-?r71MkESS8MtCe*Q$yPh@qOOd%s?wb52&YAyMewyDKQkuwSs
zr~@^^ra6|KudfeSt@rdC3>6e~*a&XC`Q_DHy-(?$-!Om-xM*fV00N{i4V11GtBzGQ
z&8A?UZAN0BcX}KRQ1KQXn!IGi+0-Uuz(QA(5<8?KITT03%jNE5%T9yeEJLUn!34z6
zMy4VXxkv=a1ju@vgQ=RQdv5WiW*i0#h>`0VP#G7EcJ%ew5m4%F01`(CX+bsp7p&2|
zJ(f>37wfF#cCXpman2>ue1|ssqt+J*OKd#V&KX0Knh;T<%eMullUJirDG`$Q?5>|c
zj?n7$j-Kw}L&=|;5-XVVcv@*NZYH%Nc0%)Dg$4E%vKJEoaAyXu6R=2ElT)2cI!*?$
ztIiR!r=q5E4y9_4PkMgSJ^>zspxJ8b`U|91BLM{`H4#x3zMe4T98)amg5_B2OU!%k
zm%>l<#8LVW;i+&S<NwLil-$qhObq1@g^LeV#8@Cl*W3cdWcXx)0OM7?ZJm(48Z+Le
z$|*j|&?X}XwFSyrV;%>{p7%<>2aizE5XX^tpA8VCM*${Gt8^Sjhj3BPt7L^^eN0iI
zD0&NLYo%wsULV9wAy4)U#QG_7&VrS-nKW_NWEVILD(A8|W!RRILgUc#?}oRsw?eo<
z0^Qc^SKj?okyd<~Fd$&WG0Mup5KK^*;R#JtF0KHIYVC{^pTp)-2<Z#&%;Dz$4XM%u
zw-kveMLNm-u@#D5Q)>fnOEvpg@Gb;JsYO+T9HL`t!p3Ic2@WSSBy*DwU~=!wi=#@_
ziYl;kBYiYKHzU7<S<x=cth(3LMB}#FV<pQN)<N|gXHTd`Ht@`KlMt9~LgJq0Ji!LB
zCxn}KM-BaFApHi;3I~Bl6#jQmWLgl)-tvo97orW(!F!4KbokyENvdg&B!F;Qgakbh
z8z1N;tkI(7@R8JgVk6vE|4QQKt?-h}B@Hg752b18nw|Pgsj1Uy8V4e{VpB<gs>Kue
z5OS_ZnI?W3UVQAe*~S|8%R(P$ldq}?+><-CX_aB}oLXX0IRPuyPdw*vBKRAA^J~%E
zt=_o=Z5^buEwHCCO|3$X2K<5eP?!PhTGJKGxzx&GHZ;GI<b-o+xEQwIz)^u?UCB^M
zG#6Z48zs=6GiN5Eja{F4i;~e)BVxmsWrU%KzGHcIVScpmQZ3rWt9ji9LF_#^1fk$l
zuccR`@jBXydgOpI-@)0;kLiVq|A;*{+{~4>xe^CaQv|zB|NY<YIp!R5NaGqz#tH<G
z07MQ$NKzs!U`m56sFm7wslCt&sk4Ml@G{Gf7BnC}Vt4Vf7!pU2H}y3j$rzbFq8?sC
z(Ckqm5z=a^5v(aH?lA9%&2!qWfRQQajZ?5QL>a$W?XH)?uG7D>eNLw|$2mdUvz#6Y
zjvxjy&G=4IQjaK#l)ogEEh+#*@y+#tQlweP{n8<Ol%quk`SRMA&O4sdFmYGf1kUQT
zniEX``T?mg&DRQ6*X!$v1bxXb=uaf1gv602uM_0BDa_bhR6+)Zo<G}nrRJ3*NozP_
ze@2=d^U>={n^Jqm@@iVsmgQa4pKB6ls{Yas__r5AQQ~m;rPT0*$|eicCO6?TPphel
zvU^tgC>TzXeKjcPZZ}KWt|#`Sh5zdJPdfr_#nd^Fu#aP`ubkLX*DJzOlJj&~U(6}j
z{G$OQ&*zXmamoRc__cTh($*ffqh&Va4S(_bUB|&;igm<IbIqKpH|hWoK$IrtWFjEQ
zpEZ3gUxh697JB%OtoJ-lFv6!amDbFZ3-5qB8ch;raepN6IRgdnJg<2ko~RuBw)f?y
zVo$~1!#GIb$E7ofKN$BzM}tDi6#FPtch(WE>3}czdxyX`N0gX|Jk9g+j_lJgKUS{g
zuldX-T%ydqEhpdqSpxdxZ3ATX)AWt>n#2morP(w}5_{LJFI(SDX*%rGwRH{LmAf0B
zM(z=k?u6k)bS27in3Agxmu(R+EOyrCOQcWP{@aPuJ$y0Vaojld+Q=~nC=9y8io#|(
zGEp||U8r+HjK;5zB0(vAKj6fnKG<<sO#BNorhpxWk#ugu+wmI0`Gd~cT)c4#Wa|^{
zgrSi#WpE+c$QYEr<F974WGn+4APOJ^ac8S`p;~R`pY`>uXJr4N^8qe+2t(SBr%1oe
z$q1-vQ%$-r0SWSF9jn{qT}Sm76Bw}`Qkpy;{Mmo;#c^E<^TfCzUU{(i1FNZ+Ubq$x
zdA%`fKm$kG!2mDuyow)$@04}-^I;7PFu;4h@q$hWVH(s<y`!e;9qln?PBtjSVD5+A
zs7=U3?NG}fYQl=?i2~6Et_pEy+xa-CM-bhc+Vpo+6uH6hKT-Vp1yV};OwaSPuj!hf
zYteoB@BW`X7h*Ud12Rme8A3`-o*Pi;mg(3;bj6|StV0I!_f9xtjO&c!8Yk<**Ew%P
zA%M{%`_Vj*L{JE`P!Z&RLRObZ+#wkV(8Edfzp*0<f+$pyI79?wsVA*dZbsFH9h(P+
zbtgl+x#R5c>ktf}a7t6i)241{x73a~LsD%=r(Av6qC`Z6<|pgLt-e0&$k7(-X^xz-
z_dFFl$zwHTLa4k+5THeh!3~d!d?QcB)#)$3>6f-~R40vhZ-ovK5T5ASpqYIQLOCF>
z87OUB{*Vh1KisjR>o38Bw!24T`u7Zmdaq`9<#;qb{VC^>qidsuJ4EdToZ;HKSNb+6
zBiFwh&QNa~sLnKbM0^i{QevyT$Yj(bf$*s{+4*bsQm>hS#vQxU6FhMq6`1+oRaYKz
z`oKlNic}%^dr6xNB6w4C2pVNCmLfS0`?B5W5_=?%AgdGP1hWKxdPy6_M&u;G&=#sb
z*}iZbIsc&`=-nBxRorZ>Jsw|6LNASzq>d>(QreSz2w8*cp5R@)laxbFvnPYBQOjI3
zXm%kdHxJD0H&fW|l>3C`7Zk#rH`W$Buj@H4J2CwU-UTZ$|LgzbEu9M8DPZ8>EqGSm
zMI&aBgb;_KmSxQq6rkL+jT717IZEn`>!&;?;KGRSm{9jgNI}jq2O0vR7}m0JUC5W7
z|APKuSPl&Bbv4z|D1J;`R!?q{+yE{}Zz{X)GXGh0tK6K*Eis@{WG!&(cqOJIKys$9
z#^QDJGgRV9b5Gh#g;8aD!`1s5>1-bXboW^Irl6h1rSvy{1o|5{e1UVgSXS>sjN>vx
zv^o$=#)Li|WmBxV#cRa)t+1K>V?saG1s6zh2C^hzQUVJuip#QTu{U7y1=6A)<Ib=!
zz~&{E=~lQCaC*D5M}Tujq!4&6vza+;%8_StQfJ*1(Y@vsesRB~nz-mv%Q@xn2?3-8
z+zU!DDUA4zoS#XKSlT+~mca%UpSoN=3q=n+^Ww36ut@*$Z=XgM5@I-Va#|)^1hFcq
zuF1)95idE&rhQ{^3(-TVEi<{gLQ9G$hz|h)VG$fD`%CaJ=L#-m3cIk|%unILh1z2y
z2T)VYvx%ab8bwFFo*7qP)21`Zly}-+nYv-|U9J_b<GVQzg>C<PIMwfoQyMo`%{5Jv
z#N+@rL&4BS7K6x#H4uTJ)1|6KKr7{b9UD)uJw)QJ@jvvxe38|k(V1gQsTrdp7(()#
z<53Aj_AmmId7%1z2^MW{0fk==$r<mr3Y|c(G0^wGq~M%~7AnH?z*-dAI9hNBKFxHp
zB47b(LKTxTL6Mu2%c`QLLFvaIq|^W&q3!#6PG9N;@0Pm~9~ip&dD?j0%uM~xJbFW;
z>cF;w>p_T5;5dD^aA+N=SaS)5&v~hi@tHP>%0DiDklhK8UyydJ#mEB@Y2v9TH#95>
z4^7_X*}&IgeSNWmyV?fpYh#FnQKyKsL1WU{go8J%4BUsP#0c@)5*ZLYTwL@PQbQ7@
zy%ASykE$axnaSnM09R3?^{B-`vRCa#7Cc|XMA_z@-f7}j5Hw#)^D9u&3BYqO7M95?
zPTQre{&4e7dxkw282`(`PVm5f^J%B|KFmtMgcZQJ5XJatg0}qep?5godNBl2^9H%*
z67c3^;yvsw#0`SX8sKrZa8pZClokTFm@1bCFVZgwM!X15I<8Cj!0hA`hm0f0ucz?r
z#<ba0spvuF`~^|ANI+2c^KZ&w@Oz2e>7F5S-7r|$^SWu*V-GY1gIP`2mMx)45rQ@$
zR+n<Y&2x!r_g&FZO7j2U^HXmn@NWH)@S`9`)eh~NndCfh7_3n|=r9~nGhb;AHw!SJ
z_;Gv&WJWL$`r6S0F#s&$c(2OOk(28#KqZIjkrFh^BsgvsW4oG}TAP_Y@aXi8xtj#J
zLqnxR8KSD@LdDMSvJFcd)38laBcp}eYctA-KZC^i621_NC+Iw3O-2DY^H}`uLg;%-
zfQ4g$@yUP?{OrpAjOV6wO$V2?AAwX9f9#C9=+uj;8u^?<&~Q#t<03zK47Lq?%ae~0
zU!t<{$Qt;80U@4)6653(^On;srC9J}L!INqrZDqQlvE?CwPNTmDlCZ)^}nhc4oEM2
zk_zwZARIOQ9X#YF4uxdwSjC>tS7Dp*T^<@FfvrvB^R3kt=Nh+nv0rkkrHmpRgjMxy
z90GA-_kQU_zW_zQ)t?quh4X>rka?emF&zxb1cD0-6s5q#r8m~&)Ly$mj^DZ(OFJ#q
ziA^;27?V*6B~+xb%O^Q8?!2D=b{~I8ZP)7=qt`i$LKfki;82t1Wi|!&u>vw9R$a3Z
z4sCH9!&T=l>8~VIcmLBr?X#4F7>63sjF^*M4S+(?VqnbnJ~C9;B5J!rT;9YPk#vs`
zu0XhlVSNs2Xej53@YL3jwYGjjawEtPsf!S!1!|pda44rtQ<<-72a+Ettx`F@OOjVe
z0nM~CZw46s*7mLJIh3{-A`|z4Cu-{Iqf|QL&m^rWHcI(dRH~Q)J6KJv#Pr7gQf@ra
ze+@KzarV!yf8iay&&LAJ7>|WOm$D<UM3$8E4`y=57b$kjDvkI*gv<pB#o*xLkz|At
zrDaF)DK2z7U5RGMa)u`p?>o1`)9o<`-MG0qONnBZQrB-(7lHLIRDqS_u>egF)D*LK
ziR3|V&I@7osNf>9Hp#h;P&fk9cVHKuu%25^p?;vkmu{ZfYJxBCv`yzqg7Wnz|EvJ7
zf07dq*N2V=^54#A@S2kUhy+RZL_&kg*D$UmC>qR4>OeG|z~M!#gBmVZ7{t8gKwp)v
zuM@lp;Y-_Wf=@E_mT_bDLE30sO{R~0hQR1MLNlX-NQ*L6ffNC6i&Hk{nJBbz2cVc)
zM0hcZmF=rBMW8#Vrn@jcPh(C8QztDJwOXDlB9q~3a(CO8MB%<+h+Vfo`{yrx<izfv
z(;OnZ5s|Gqkfw4PJhrb=EjzU{Q=`LOKNM=zn1I)23<cqX+;B271l|8|)2hAzs}t-e
z5`<o`DyFnb-qC=%pW2Yfw#g&WLUg-=I`f!I0o6h9UL8&B>)-Wuy0I6C)*q45WL7(|
zBYR*Ol3lgm<jAMo8`kZ4Hp4C`Sg7yQ35Mdb)#Vz*k(Ez3shytoKv@I?=IRU*3dy#U
zuxg@D8`~>KbSbo5efS+CX9B30*Tk?X=D-IgXaxvnS>kPBX@R*UMK0q?MsA)C-vc^C
zf~niB8?(tMrEHTddY1zYowRIK(Y+C?3Ws{#(L&qt!c*uvB(oX4KEvtR;n<(kZe;2_
z2}N(KMuupW{ldL4AU^jN!uK8LwZs?zC-(W)QOZdUNTb1)oaZtH$Sbk)K~S{FyK2z|
z?8)<~8d8|k9iLD!Bv%bWRsw01L-OPZM#I?_)9Zr*3^m}Fov!|lK?M&;n7yvWuWFDm
zc?B#PC<=1*OzJ4BnxCigrv$Eg7ZZ&Qonj}N-Aa8m*fSvx<7v)j@^<C2<$qUc(m=3I
z?94Vt{KUsyRJ4+A|F8esf~Ps6kb>ByHX5Z-!LoqDCa>(-!%d7t*Qs_^MRpu%uuvH8
z1k9|FgtFn>L~BL-`q^6HUjGDMeMul~cOaWUBh!%lHJWrTtHa4%6}9n`!h2Wod0yAv
z$I<CFa|KVN&=FAu9GboG_>_vqf13GJQ%5l6$;}ipEmf)1@}8Zy`q{A(?uDv%p+~|L
zNENd5>|=@erGzv%2s4X5825^LrfiN;sm7o@2sLt9Ap+6Tb^YAW5|LlyzytXW1Eq?z
z)j{M!HbjS5v)bYh)+lRt9k~pZ%<AJ{nUV$8aaF|~VmAR8x!XaiS}B1E(QEe?Tf8;?
z9{A-6g`uq~9Ki(>stU~VJ2Rt_w-sxFBlF4>CwZ6ac(QKu3geK#5i(yJ6#C#lpB`=9
z3L_*fEz~yPbT~oqs3`@?nxt|Z*=uDR28BrEi*SLnkDA<h7OLtU>eX>a8bRnKWQD0x
zdOPb9-@4tKr@i-Co*0Sj#dL6_-Z59clc|4))4d;FW6%f%W1gRP{4>|+HY1LQtgU2O
zG2B7(?OEE6lJPx8`T$?@BtiYMnvOoD2%|+#_nT`14VShr;><7U7a6-v>`njmf3(jy
z)&;$Z^aK-=PMgzs27%$AZ!{972_vzXX4&{lUVjI{rD&s3ssK1ZJ-4WdVPqy%n|T0Y
zs<!xs+3n(<TV+S%1h(EyPe4f}zo9bIFr4_Q{VJy(SgbQI1KspS6PJ)kFusUi4QCWZ
zZa_i2u|a$>_p2!oM}1Ra>k#;hZ>+mZt)Txy8Y%rN2IKV*X@2HA3t3t#4O($=jW0qC
z0;@H|c4Id*6Ew<ZqIafGuV~d=cZn>!=l{$YIA-{EAUh{bdLEG)4d9_ku&jYU<j{BF
z%;dbhXAnU|&WDO7n4Q4PK2sTNtxo)adin*_>rv4k0Fsw}g($w;Txt_M5bctkvppZz
zfh~1_5V{pnbOBsC%2733XyK*inH*oyq`v3<8W@V1-D*8}=DoLcBFSmS48obLnnZLp
zKB#5TL^Kb3N&Wa<vjk)0edtAC+km+k!h{(iVxmeD2}lLiJ+QU7X+g{LAAolMkBI@5
zA!-M*SOxK1QQ{`hfy{+BQrcc@IAyKRQ*K@IE*jn#SBKoiI5I~2>f;k@Gs60@Gith0
zIf;nPk=63np;4Q<_hD-$amt}DVG9I)Y4*4Odia=gDj+NjUJ4H^6XB%?ax6oe1^`tQ
z&hsGDL@^!G?CKql{ZMx(En%Siq)_N6@mMu}lpH><u8C3{R5EBpx`an%eWU}86Ej6`
zDM3&htFydON>VRalD95=--hMEe36LDVL@h9YRzioy2-Ui-^yHl)SQk^MQ!5df@dRK
zMbh-`W`Zu-RT3m#MRLvyGym}T0*JK*q8t%L_qaAma|TQ7j_Km!H322)Avw;?7X%y%
z27qCYOX4vEJ7gg{dMInD*5)<DAY4(>%;g3dg%(P+;bp`HYnjZ{PBOS95F5Li%G1bm
zSskmeAyD&udf)m60C7-VJ1VxX@gDR|K02k6&m`lQGW(MjkidS@Itc!OZ{NGKAT8Lr
z=4%P9&!8>zS3CdB=u*#-Gbe+<rXAY+Ec$+k=G0fH$E7S15D)d6cC3q@C}MDdA72!o
z5z_;bU`>MLJ)1(>*O#_Py!v+lFAgU?l4-AL)bKlx(h<DOE-Z6I4p|-|Qw4<zB`{Xp
z?CV*A!*h=R1d9|vjw^1-*#mnz{Tn6kEUeIz@ZG~z-#ydfD{@}nds{~yf_|e3g!|in
zF-*F1EO<Tk2_P$E(t1!9Y)Mpv4e<7g4)b1(wQ_>~9TXzc?za|`OOr?+=pfjDwiK!X
z#(SW7gxp%}n9iWlWR|k1z5<v2czX5m*&}-l8~x~K895s?EbuBRoZMc2Nv#t{OYI)d
z;rQRvuY+<g&NeoU3xq_<mWP2p@Q>ii4?M~-U?11<7q8tzFSLb;d&6)CVdK_x^rDXX
zpThx>0`^-mIUAJVOyCu|GetloEjW>Xc44dUeb~E|o#C~i0?^nQOwh;m()|Nsr;FVk
z(Ak7f7v_zgaZaJg;m5LfQMD37wIh)Ok54-{R9>Z1?i*m;6x+SmF8=sh*mat(>6~++
zXI4Hl(y6!8bwz8$vVx>WA`B*bMb)4vz5Fk_YrO!U^PchUP8Y;V_P_es<7b{X$hhPN
z8ZMHc<z|MA9^@gw$&X@P#W!u#nz>%0d9S;ni<5_(0VGmxi6jRQ(d6(5!{C!@pSivc
z0+M?#a*h=VAwHf7xcrEPjUg!J!A0p|owUm2l5Vv&X1K#)FXvF1rcVU@#q2Ay)S69z
z`hGK>(NY9<_XW$!DBt6B$4gn?pv#;ihYX8f4qOd?^nXW=JNx9~3ogrELBE9tlf2Kf
zywQ1dnm9x{)9-GB0zg<&oRsSvTLC`^|1Flcpg8*ToPLo3>(PZRQJs$6f#8X}Zl=@3
zRTQwsY}!gv;{%i&Q^_c3n1WKL$paO#xl5FoZ^oE8JJZ%6xmIqg@4%&uVW%iZEad8F
zTE+@f>yI>tyMaJ-f_B*cG=FF`Jg1Y0Qj-bAe#TgEV3Nz#?iEt*LTZk_cdi3qA~Kxv
zKvOGJI#eg2j*h=VN|3M?4fv&ZL&gSBm?M!7LAEAh%lO*kA5rj3=2>$&%C?Bhy@i+7
z7hRBHu&{Nr?EF%;NA3bw6IW-F4~V?*QgZxnyHS?0M%o{cu?787E`ZSC$}3XK|M1xl
zvgI!M;Xpw`7buSAKn!Xex{9zxSEfxH4roGwquTv_6vP5nJ&4dq#DpFTdj~oSgI)#w
z7GCO?rZ~dH1!<@SGg4<D_eb)!roomG-G(gOkadUiNNQ0yYZs@RkAz{rbt&QhA%P(W
z2=Z1pX9*+bZ)o$_(4v!dnz8wD2=IA&J=iMBEKA$|JqowSBLf!e{oj94^vcavnT7-?
z2eF+lj#7>!7E!6uYf-tM&F=HM$0H{bg!KqlpAi$_*<X*@74&M>Kzj|~GHqajCsjRh
zs`LbNAf;^ZB<dP-58|E*vJZ=-&7zBZ;2iHcy(R?%>YBgA8!{R?O`zULlj5z#zNXom
z$|OEh0YoIj!&GbeYxlF*zvJK8I!8sS9pSfMG`@M}3pvLlLF9@f`c_R~1_6PDc9;;7
zDg%NltkXVEYT?Jrg6HWYmNfMPwPQLMsA+=}YubDi9lJIXc>W!d#$O^IM&AQ0hgH3h
z9HO&dgA=VQwd)dVpNX1fvu4Ee?f!6oAM7xm&1jqF_}x?WdPGZp20lpMQc^(f;0Qsn
ztmfhmu2Co`<P3U?LIlmRkw1HCBsdCbslfq+koXg))ms_>8~h5enuokYY(;wK4c#<h
zU^rQZ_72Z3Qq#$@xgT)>v9DUK)-a`|m+ZwsieNmU`!C|vS=1X;R8jq@Bc06G6thEa
zXuxVIwr_HbzvaU0!m0kaIv`4J&Lm(}84}t?tD_nnHIC*Krcd;BoMItvzNLIXf3fEf
z*Z?I|7CZ`ZBrtCq559AFA$QDi#)bIPq!Hou7!No&&92V(%#$B>)<oVK`ajfvNjdRY
zKs^npB#8*ZX4<<X9Psvzh&>1&wZ)$_(eH4Yz@k^UN5X)Ax}aXJznVUBRo;np&Kv-f
z3wv+~413D0xW4D+-{>#?icD#cGvtVHcm$Lps}JaGf{x;E@(>BxVUm+6j`^~6#p2EK
zRj0P}WBcpFP9GWey>1K+hZz4^w)2=i`h?8#Aw&o%B`F4Yj+#W3(8zP*AY7(1qC#~H
z0bBu+GHyUqq{lWEh8MvUv4UFBqCi4~%aO%vEYvI|??*?DsH;i1=K&{fGmVXzDEnR0
zkCyuk6(NP&GTtE%L&hINzS89tD67Rc)Z;3?N2Emv2Q${GN`~wpU%lp_<?#32bgt+)
zwl@Ce&wdj@diybi8g-a7cb_phBQj3$o{VpyQp3ryVD-@~yIIIOM=zmAf~|($FrGGn
zeGgw?4uP(OxI+|B`fLZF#EeMC>3AAh`(><t4NGx4F|yEImK7G~r0gK;)AQZj(zZkL
zb_z)tma@S=0|q_Kof1>8YNYx5Sxi#Cs#?G^jOEjU<ml~epUxRKHw@=(qnrN9Y?QM(
z!oUb)gxf6*>lF>2c%Y0j{jq|&w@{IbYVTl>$0IDSG>$@m&{AxUN?r#?Qv8Kq+Vq#&
zj&mHbHuCpCDj+Y{rOI;E1bXBApA^sUZYpVrs!~0y<=<Fegb>K$(copimzW*M|Hq9(
z=vD)oi;_utDp3Sa<h>L^pR+b})Cm~`L-R%8IAnC$*V2D|VBcH%ErQa+F$tzaGbn_B
zK^)+u+hFj*SreGNeuk{27YrSrNf62}#HcP&UP3Ylmm^8e5I+YSLJX^&fq-N$paxNi
zh`tcKjvz6eNv9`(d`g?f^Gpu(6Hlg`DqP)S+VkNyJWdkPh_b>Zjssb6oV*smbAZeU
zYf4>4*#&t;X4BibhgOZWOE&Iw8v`r{pFCR}I@Uc-yL5zNJ#mT{8#4f~tg}7uF}I}%
zJ>cdFxepL?8{ae1$VxdiQvFZHi0(qX4fIg+OPzZ?{(wfPs=Y;xaXC${Vot%3r{Dw|
z(e$K7DzU%9DJt%+qb(${xht?xN|G>@s8epYHfEy+5u4V6gX(EF<<Z3?s=O?2gBKk-
zCh755`rO?wfu*<MWcd_$@?p#KAoXV%U2(L9Ix93ZL?u>_ZveRwOjGu})gq0XAg9>@
zs}8XRj%2R2=t6p+*euXhtPxI`PW%8Rvzmy^9wd#KeEgwkR;lCU4lwrfLr}$Yg)E8!
z-Tx!Nf2?(hgFGOIZfK8Z4r-$noa_Ph3Q&wzQEwsb8zX&>LhsR7mDqxzex>=v9RE#L
z^RQG0lvs&Oo+ijVtdP>VT+_Y$A*<_jn^~_XDt(~#XgUCwZ)l%_lQ{J5UQ`q*KR;h9
zwwq`0MPau~^g%xKasa(2`oKLXa3(5AjRcMW991V3#5fU5-A5q@yOp?N&@m$#hgBr~
znIq=anW+YaEsz605B&K9Zd{WA5of!0+*@ibg!uYnfy`?#KfQ5dln!@IiUVdOn20>a
z<40LoZ;r#0C)3chN8n#R^v+SIy~pZ<(zUsPGL@neZW|?ti7TC#m{<I}E~jC;UkZ=U
zVAT$xWLBj!vs3CSy!#C${J6baiGGXFMN;MXe`?c@FuJ81+orrR6)hEeI~`noG@TUe
zHzpr2_g8YatC<v0sA}3L+<j64ZdTz|2X6H5|F3<{vA_p31>Dj}2cT0iVbLHpL3F~@
zxRzfGabX-&p!d-k{nsR*D2fOmbjJnGZ5103HInZQvR2C;AuWL^34(E*ooJXl!83J6
znZ?)CN2JCF$p(-y(`~a!&z4zUu&yzcE9fqG?<M-fPl?`OWPDb8D}8n5NF@C=h}p?a
z6nN2-ghbE8@!ex?Nw@DIwKTkO<2cs^Pkj29{|gPdF9McDO@aOLbTR-;;+9Bl7AU4^
zh&yU|)$MiZEy8lOqdV*eyK$Y%9(X4KP*lfUfV!&MP_(*-T&R$9`o{NkF8#ydb=2xc
zx}LnMXyVmU^-YEsbd-X7FTkCBzgdKnTgtts#}Vn{U2tP-$&d*Njg1UV_9j&tt-gzH
zZH|lk3iIqBBugI!A+7bqH|~(cVSMw%pUD5b0O2Zn2#BE(3ZWYE{z-O*cYztnr$9-y
zaqmp73CA()9o<M=5{V9pFW?!vjn-B~G(az2oh(SKYrd8%{l1A35A?vrfU6Fy;l*@w
z76J{CR|@&VD=J0Q3ZZC;72y3hn>iX}x<anMyF&tk=sS&?Fuv!LjIuORQBBLJ=c#@<
zPR%_tZ7+G<u3re>J*U4&ou(1d{`TM(kW2;e{U9jp9^%zx#Z9O^(otcN&YB#M;!nJV
z_9$&-r@9Pvk^&C^N)qZ@Kz}e4a08cCm5j9D-Oo>vxQ9((32EO*BQUQjsxR6{N%wLF
z27JFTnu2Om)!JTw<h5q89WJzkce@4-B*5!`nohT`np}?%=WswuKBH_6*yO&DBEz>)
z4MQdLbCQ)3iX_DsG2#XDls@8(8QYw)2tJp~bk<^{?k*W8l56NzvH<L+Zuw+*UhZ0q
zY8WK0m?9D@WAp|&jI<$X1l0-%m!Q$I8TKRufhXPsBv0#1$82}hR5Z<~l}_xi5)Q_W
zrtZPq@Y{#Ydsquiiq9cr;Zm&`;}Zt&4MBMV-)-vrmC92Jb$OIz%`PdpNND2hHjV_g
z>1A4}jM=}O8bSP}AHT#*?N8-|5bhY{CPSAZ$RkEkm#1pO_{M9Lxjjx7H6&>0$dCbi
zN|Fv*7XNovN%XUp3F`uE?i+v9jjo)atDLvsY9>Q57-Vj{x0SlVOIWF6m73-j=dW25
zntkTb`FBW^4IG39_m5E37UJt5qqaCuaxfHL{f%q3OQoiFF_GH|Zc(?RruyEAkDOpb
zM+GZEV<nKHHUxnTH369NXmEe?)diPh;jys1-BFVd#>t*3!XQ7|&|-rmNpe-pN!j^&
zXlF;7c-%{zx}$(ghDEeGnn7dg)KP8MlrzpYq~VgqXsJg=1$XEzUced*eNlC@ll(}^
zgwxPv?xy8DT^V@vGwt=o76e{)=rIxlD3)OP{~U3)gBd_~OJ+LAe4GO$KVu*XYm~f#
z&@}Jd>jrbZMEo2%4?n>!h0-Wu#0hyx!ZsL79v$^EbiqP>sOR5d1SAYz6QTZ|^aay6
zBIuQ~vt!C^1oOGu-maTT`D30o=Eflmwtd~ZqKAMbG*GkZhzaI1#$5Iaf+Gc1<TnG9
zsrP@oX>dJq{|V#x>9z>LMnC_b{?P~7U`7ucP75r^rQrsdo0)Vlzxl#hYQ3&?%{Jmo
ztUrT?bku@71Y)8*1y9+CTMCksG^#3gWU<Tr#kwPQG!Utw;^g?J(<^(Xq6d=G0a)&U
zf~KkFZln<Y@`3SEh4gM1%go(sgDLrf+pt_6rKKqaCmSxg;7QB=u7c3v4bYeswmHtm
zovdR~&%r@{^KVBOa-_dc2D&9xNUmkYjyOR)7mb`yO=aKJG|J&HNZpGZpQmC+d3N4`
zQW*e~o;$j<C1rBTcEKe*_p?R<=(@BG0m)eyBee}Ks8vZ-Rc4M35#_o<zH)>;A}LIb
z6ZlBWE=g815o^_xotcUHE{n4VA0Z_?@cn?}yH>sjTBi}UCu)4$#M>kr@z4Hhk}F=2
zKE@+WL3Aua7bx)%OgLthK9s6G20J|5+@d5ucxGzAa#{%OlwzPX!G1u$GFXv9DzhY;
z9)st4VTg_lE~}Hw3>{WwHCbUm%&tQ0c)U`vkVm?6g{_`P(2)v97OBQ%NCE+5%bEH!
z<cAy;3!atsL%&${=8A(UVa&i3r8Qw4k;dPA!Qg&xsY@G#Jk0wrmLU~I@TiM`rYLCZ
z7bH&lFgy*A51)b$5`G;{YC}6Gq9Jq%HIfH82t69Be1@f6)B!cbOMzts1);tbS~K(k
z6s}%J2i#G#33xQGjeR|eBMs;7k-)Hy4D~?;6r~M)M#;=Bi}RjxDDM?g3vTV}aU?IK
zx!XbP4r(kaTCLAMQwuq2>oP8605_WH0f{7)M>z>ntn>1&S+$3&JRnEm4lS%#C{Yg-
zLB=~^T#*7YW<j{AijCx4>JN<mqd((Q+V!|{3y;msX42%SU<Zh5AE-KuJ9T?deN5S~
z{sbK5iFrU$6@*osV?K3M<_l2<{6NtxP2U%Vkm`CA1nrf2NNhvyV$XhlGX9FuquFoE
zKoSm5%<~(QgQH0tkybR2BI9j`*W;yLAJMV*FnJKX1aof&Kv&Un!dY@;cwe3dm9Ds4
z@RHBqI@q(j6qkj)?j)yfWY7TL7<2_PL+yrjBQ=<1mp?02n6Upt!*I}JPy`=giiehr
z5GSJtMU5%21u53rnokM0kUPE>+a_#bIt^-azyIG~L1#+fl;ME@0`Zbmv!?O!Sja+!
zf83f|{DpImJs54x0L$K?wJ5R@5HI(e(?XX~x+fmf!jr#tzm)EZBg%PUgx-b=v3Jsl
zYvPf#9VHSA5wMw}O$wgaE1tEZJ<o9%RkvcAku>BcTY4F!I%G#Jr{;}GLbBN}?e+yh
zy{BvKTd?5`@~;QqtuXmgCn7_)itbZRXW5*TwX~_Kd3m<h!;gMj#(B}ueDoZnb{jLK
zlo3PvSUzIy2VnpuJjko;IF7B+SBq5JA>g+o0khs7q|>WG^!ZGMTbphx(%_6WnkQ^4
z|LdjSV~?oXeo4U|&4f9V4)74_Nq1S!ZW>*ge-9OaX91o_zBpgqz&k~$0Q`po{rtp#
z`&dG23+urPm4jfQQZ^}ZRsh)+`+t^f4Ch67s)q~V=!-l)$P1W_Yz+mPBE=h`ppq(s
z{0IOqH9-)Au3&J}2(_58?8o(JdNxfAyM&y5rJ_<#T7E?s8wbZm(TRu3_H`>pnla0T
zHY;?BsmM^enyOX+yYc{OkNRbc$(S1n84oZD+&BI;yp#4+Y|tzsR4XIr;0X?!=yxIC
z3l+bBEA;HB*_|6csY41eohlL#w}{i&6xt`@z9=g2;5yQZ#p`|U|Awu#q^6vn+O0Fr
zWvafbo>8`V!O4z#uKpmUp3yv+Rs4w0pb!>5$02<>U|=G1T!f9XhE7`5DkNdi>X%&L
zlux}gmqVE0P_g)|`121)^=14SuMm<UND?frelYu#!-_m?K5DxsjO=jtgOI8SbC22>
zB}5jcUY05$hUE^GYqBlXX6aWFYGD%+4vZxhc`4nX*hz~Dp*GcteGOMb=R0}IZMB?Y
z81#JUrRLX{vi`nyjP8RV4BD5|?Tj%*1=3!|ws;8_ID+C_EB>7cF(6|ToSQUh(fDw>
z^{;+A`aS)__Cx9H=v`p*kY>FF7#=VzUVeTq-&r4YoM9-QKdS@m<#wcri2Z;RpL7~h
znBVV{kO@(A?HU%(pHsnU;uNDV={xQ`K2aeb2{O{E+riaW=se!frz~=xACs1mk1|xN
z)C1gg=~_j|!*wh`RP<v}%W{Yds4eZKpV;8FT=uTuDG9VtGv<c<<(uaq2vLr63#4qd
z1XRK((iUK66y#PWlBVooZi!&%F4OHp)RPS7;K^|YWx|@Wnwo~xg_Bq4o#f-<wCbco
z$VzUg3U|@U<h*)@$Ax6n3cpy-w}Q~m-Q9{vMIn@Q`Z3bF4@ikFX{@_TzM@BQZm#3l
zG_>S~q=5}bejQQFKc1d@fq@B<2$Ca_shb2?kS4Vyq-Zsnp}`O!)6Qk7Eqg$geM2ik
zT}aLk4hQ5)&%VbGLRlYLrwNLj=EJSi*<LUwePyNAq1lP(N{mT!YIKto*Ir0Hq456}
zq<zyZ<+@(;4zrdSoQ`X5jxb~cu4!4LjVMBWG`ipQ=ZV6F%1)D!thDilr<`(kbw|oc
z?d5Mq=IGZW?zh4026Gqy71%dMTyUwO%VPGq@qRV-gmk}-Nc&dg0~OPh10dr7vy)<(
zE>nG*Mv3Z87EseRX(e;tHtNAZ$6{J(bNY6rp7*{b$G$edSZ@}4bGhuZ&hgXSfxL2g
zHf<ma>dY`$Ku9JZ3d_Y;-RBo3N@2H$_dFVDgJNEu9cKK&V3?I`v>3JU=z_0k&Lj3S
zOwwWND8$LY=>c&i?Hq$F1m<wS9r#PvdX(akGw3Af22ybjU`IWzz+h3}*Rp!T@<GA4
z%kcgpEuHY_qq$O>8?wmjN-eZ6<_t5Zlb5jQWK`Mowp)0W`-|7b>x4ej^Vx^&=OuH9
z=qyh=Cn(CKx<_1aa6V@pdu-V8G0|aAir_MF>~z^z%sGB?2or~Sp~AZa=bR%>a>_&G
z+>}dr(y8c*$bU1^r?9C^Qn4boT)20CaWm}aO0E7<?pS~lmdfZT&Fq<>X_8K&lVzrT
zTtE%Z{w&@vaGI1k5;-~t5Jddw2am{u5B|^vLf(VvdiJ~o$_kG<Y#cQ&=@USg6=M1&
zjqz4k31VnTuPFiy4fT3+*@2eod_7bX^$Zy<r_HjjVYKf2UfKX`Exr^ow54aB(}#(&
zz=-qpm+P7Il&Zg)A(&6PjM}O*(9EftwWVnYKo%cAg(qx|d=&ozMYx+x-Q&oUWFkQ!
zeW=QELc<aP!}YNQyk|=qR$|QkK(d4+oK@|_2*}D}Ra2;3ZKiB#6#Sadg!=b%@ifAf
zxYr+Dxf*+(Bvb%6PW-5JpxPL0;f?+XK{M!=!eb7_lr4k6$>h59EUCbrLr9b2ylmRE
z@42{WN-6WjdVg^XwPAB<>!dMvMVIdQ*o*)6i++_J+ZI|3!LTbazKaY~6mg0-@T_vb
zbb_hfcVveBxOCm%zfogyDI;%TvNeQ5*q`~a#S?^Y;lBFhRyS#{i9wgS^sxx*$Cax4
z3Fl0G=@2e7raQ?A^}NMR5Lb_GxpVrxE}R5KUzlNr!C#)$jx-)skM5dz@h|RK_jxMC
zGywSdEuS-(z3WBBn5T3RSoGi@ezf9Tkvbh=HH5&#9neQh*zn30e#|fK+5}dB7%@GJ
ztn$x09P!v?vSBxBnT`WysR_B1vaxJx%903CP8rL-Hv4*p$2X`<ndUh$9qcB`@5FgQ
zL)xX^i*OzV4TMh|@>S|U3<;f$tH>vcQFs=9ofc^NjM?VGo9n}j0=&C@%VUxnSzKiH
zM@RNLE5InpL{Z3c-G{V1VHgW6y=9tKSVoOSuNNYw36k9f>J-`pb%)U?dM)uc95i|x
zb4#JaIS3k(Wf5D_iW*SlU<N0YWD>husD4W^?P}9!zDyt0i~l0E`CrS`xEhyRe4d_#
zyUtLqgzPty!l6|?Ka;ZOY3XR$i=dW$$9Ei2jt$Dlj34>!sD~R7@zp5K!4_gf8n-d$
zifQ3PJm>Y8KfDs5O@dMe&&m(bR0Yz?TixbjTl@!oW<zsaPn}JxDBQewT3R;Td_{S%
z+te2A(zMWNlnh^k8jQ`7t24cAHl2FSm<rZrEc)=EjDT9nJg6MdY`evK{k&?@UD)&Y
z`2;G?=*u5|Y4oAXBP?JQQG3{0;3;c+De&N*p}9ytu;f=H{zZpOBBU;5;lE?;K}r}9
z0ssyUr~#-ERV$oZZqAvIks#7U?#}1wCaU-PqUOyq>NO#qRL#~*`g}d0s|N84>7G)W
z%A?Wai{XFIT)*a^q$+K9$zBJPY;B+OFp3bQAC~+_$sjQTJL-7e=o30T9QO+$t#@uK
zm}-0=8!x4&;f1<=;*o_A@Gl8KF!~xJeiRum`v?T7OC<&mMxqJCkuue20YHJp9Ut_Y
zF;}Y9nV}_+fj#?8^f_>WGUvPux`4GSx{w02tY;koAw&Pw4<9p5CSarKoizjgM6gmj
zD)AOATBYXU^YfdM1m+l4ww;*c!bfIh$#4p5KRG2&Bsu#$E_%Mu>7fwcYUZlw&-6B$
zT>3K7BNx<A`U45mW-|I*)c<a(c$RZ~=DN*XMkjR6J7Y}cg~#2&-37ty>q(ReG396#
zmD{wQPch2dBeS4vyyU%N{L=Az*bNCISo$~r{m`i{9FDNS(ny~cc?HCJlH@DzI#dZN
zWq(|cHup94pVMyrl<?MoD54?G-NlHBmmbw48~Xl@`$n9u(lA$cR^TQex#R9@X>ACl
zw+s#-6q;TxgA{{-DAj&^kqNfmhwam7W1SG%D&5wgt+@Juvcry9Q7g;pXI4d=uH_di
z)_Q)MUL}UzZ<hnn6U85V<B5eFlaWz|K)jLm2%U(pmO(gC5Ry~1Jk!_RxCRjgCz7Bl
z1wt|T8T8#`#*>4jcP@&ho6y2SJaae6He(M?Gme0Uo7RSrnMH{i1j*aPa+&)h0QrD=
zj;WN`(j0IwapwC?@saJ5`pwh5E^BkaL@$wMt0se^_(spk<>wu{;Mw`kdY<pmOIr<+
zl81DLv|jG?_cqSyRfh4gflO(c9n@SkYtRF*P+=gdPWt&Pr-!$mrJY_UE)Y%V0pcZI
z7oBI67iOw<*&ig4@+KbK70Otc0is{K5uJEdS+k>(4CGy&XQARP++#2$Nh8G;ZJbUy
zU~zDPn~7#&g;jD5=Yy}tdMtn`y-RibOfKkp1}`b?Yde9YF9#|M-bv%A5D-B?$Zeo{
zAa%!OIuKH@pS<=Uj{Kks>F6{+Y&pHeXnF?Yk$1pKOn#UbfaZcQ5ku<PrA>|iRb!&K
zGX!TMR8%K6dnC$nu|6Q=R8s>nUTxT4Z1n<KLVDYz-VWrS$Xaitqp<F?N0yoAwIK<7
ziZ)SpEe+#7?2nBxg^v*r&80S$7vD(m?6MQ=cJ>QT#RfUfpz~2w9soYN;4nskF$7OA
z6#ubw$ZDd7&R)?ynAryD4<*<LGtZ>Ekb^H+0lL_C<M9(<$KdAa@Fq+F0A_YPO{U1v
zPhv~4yqYFbIQw0^g;gu2E!?GF+NOectjlJcr&gFg-#C<>om$h3C-Z8ugH%uLcZmhZ
zT+b}~OW$wqbNpe-QSkq|1fq+^N8kODUv-3)OM`-`MiTnXK#G@aIlz)^$172o>H#yt
z=Z&iKe!yNzb7&;w76?>Fa4C+wF6LAojjlDLqttztvP>=<@K?cVo{1PH#~~RRqc~P~
z$EuWA{CUwAhU<$h1j_BznS@*%GPq{uT$&R8TINXdHwqcT?~?UpC9Y-K-3z6&d7rC5
zdw#ZkiHftF1rf2F55Dpbd*3a0Z}MEc$ct$8@v2FbYj{gSyjPPp=K1+TeLYTckQEYA
zl$!(R&F0bAC4?Nkp?Cs9hh>ukNx`p5#=Ns$Bz8#<gVC5^y6U^>i|I7Az5|(5eK0-H
zG)Y#NNWom+&}60;Vx}=sC&?J()$Z(*AUG-tQ^7_ilbKYJX`1AeNw)y`MejapNrU|2
zB!!~HDacf5C~bcJ*<U}8>YB;U2LF==P7VOwsM26Vt;`aAn!|%GykzIoPQR3Mx`^4j
z{@oT^2zyIS2n@%*Kx2aDC8)62-qLl5PJ(sw3C4s)(7OQA4P$E0fed_SdMG8jr+XE$
zX9{=)T+f@l^cJ;rgyYBPho#ON9x@n(vNki$L6^>GyW)P}F=z!N88`B6udjcYJ)M0j
z_U=yL(6o^L%73<pc2^Y5Wz=8d*R6-O{k<%0)yCw9?==hIXkkk<7AMhB%KYsBu_{Cw
z$u@~@6`Dn#kB%<3&`NkxbU>d#Tj+}Wn!%GmnpsAiiV+ciDu1?0#^iDb%sdi<{uRTM
z8*c&-9Tzo4FQ7}&UN;ZGx*jlj{{5Asw=H6kgDl%>7F$5rEobOx>_yzT`RQNHzmjO5
z(?R&s1FZ!xT`-g4rKp}0rq9+2mKombQ4J1X!4x@8gQhYRf~I+k*&z5REy`k72X3m=
zSto-lwYxHdBouWc^PX>{FBw$llTmpCV5X~kXDb49&-$fj2`_Dlnx`<LcM$A<4Jb6=
z2`7_{Pc_U<yN$rhtS+3bjRBtc?S<{YhxL9+WaJPRfBi52<ai{ccn{#kI}9OsXC|p5
z*_C5QeW7gMupj9*(Wp_)Jg2wtOWcV8{UO6$X$Wvo(`x$I7|dRDl$yMV&k<lOK`gD3
zoS3UK$da{q6i<_K>jXN-WHIOS*Vd&WKL;tn0EE-MKF3Sebj@5f0di_`?NKBu)O}ra
zkWVUKy2PfMWFk$Vz_^q(@qLl>zx(Wwfes(J)QC(*A>I!?ugQf!0^8<fG$WjrvDZPZ
zaxsCHDx}qh@J3J>)N1zAzb{1^G66>jn-pzEZ`cHONxR!+CoVU>fZSW~M<9Ke6~=~M
zR{U<M9NBDe{;YRDOAAX6qPY)v1h1jb3ueg=O{or^(=r)8VVZ|<#tPg}Kuz{$k4Bm8
zo2R)#or24EUj0*g#PMpgsL4mk4kv&c5UqTRxnOYus!ZHFL=Q&L_rA&z_$6$j$XlTA
z49+hHeh9{y#EYanN`1D)NV^2HqV$LsFc+*G9D;dH9|3~VFR({2M@73+CByYN#GK&o
z`-~LwUP+97RfqOOaT26var8&nU@+Ex;)%c%avL9131H7LZ<9hFhdB2Xj{%<qGw^3S
zUv!S)Wm+(QGR^Fv&K-H;;5|IY#F3RvtErtxc<>ZWL?xkI`9(GstVp8HQRXB|IH6@p
zSV%aaI@EdhJ!+z%0}F`m&b>Y}(V$0ahAW6T3??%dP!pUjn^i0DsbM29OfardZc)P*
z)}abIFeQ{-`Q-wMcbOl{a1SIZr4v1v>#V^%4H@h%BU^s^(j(1lu~Pw>5<C<AXai=3
z6LBCW-D}c0krF^^`K6TElnF7TKO|FUvQ7hK-Vh_AInZQ+pc7&`{<L>({S40}I2<h;
zx4Qvu5x@O39hpkftfWmJWm!8a=l(&dGK}WJn`U<aDRn#;tr5+%X<nLL-81o1AO|JO
z1;pqnZ<G!f$ce>zvycNH9Y<hu%)uI{)HBf_R{My-kNodAv$BXRAV12_qR)l|XEwGX
zTJwa}`z4&V7j_wfN0nLLID$ldA_zdQ=JX)#0XXf&prUJ%kTmg?bVd81G4k(noerFb
zvzYBoEq+_wP&j%owQP~gnD_2$Qt0=ZU&S%;YenoHhD?rM%fw^R=QZ@uNS;#9V6*d7
zN=n&olk<~%F>#F_BoROf^7p-H|K7tED#!|XJ9&|ZZF<Rwg%2rXjf@T~O<4<Db5{(f
z7m#_dYeT_=yzKN~uEv~*XR#<M71wGg!ePGQ>3XLE8PnOmlwQF^HZX1s1X%3;%+kKA
zU=V2SYM#h%_xCx?pW`!Pg%(Ecylq4&V5>~V;w^^uD;a&~4f0#&DU`Nhs#eK5jCTca
zP`>+o<B7)%-}sr_i8BiE!<n_YH)_8*m?VueAP=gQer)gU^Vy!xU<t#~B=ttL7MU0T
zjZxB#8hcGjxoJ{BBZZ^Ef(y<701yAAqHqZXg=rjCgkG5$SdSi54&h`D>1{6mrjJkV
z`dj+3?oswl@E@IjQ5kcQ!5xeNWX(DKj$$Uwe0iZ_FII%QD&=|suqz1PNx$ED<fy|K
zyfUX0XSD+SnT|+mpbdjD9AC?)88Pi;htD%9J2nzZ-i%xc#A=av!p^b!uGN>dN2l{N
zg!8~08Whehn3?or8HOY7u`jE~)Jcoy#<mHWO)bY(LE@L%4bn0(3a&lA`uG9O(#*#|
z-Bpk9Bsa62`7zkAi5QV*rn_2l@*k~z(SvCh@XVQn4~fFGk0SN8YLH0~RLnE+M2SdB
z$OJK@3M-L!*#0O;VxTZ3k9^nw>5nj_#0f)+Sj5$f>8U*o8u~;7_fKh2q&L=``HBm9
zQ~bMyy3-$F4Ent;_-CxuO{@0*%i8-!$8la~p4H6~-Lh#1UFzvm)4?)bh3aMjgeVfy
zItb%+x{B3M5o$^x0%Nfl9+`jun%3HpL~FdtpG~@|tHElpDUk>#fgPU-0D)Rq*4QM?
zWI211F&k{ykWAYYt({eNd?q3-W#u{96H-=Ym=D?P?>6O3l5_Uk!n7!njY8F1?|c6|
z_qopvw)BPfLGu{k2!U)8ql^~|w41*}!4YWfYW)+Lj`%+KVD3X6*$>DnEjCm%?$=I<
zDa52>N3ugOZTgK3VoU!GZ#i8S>&giUB2eRwLR5!kASFSmQ4*C=5@*pRIRzv{B@J|+
zd2cofV`Be*7t-`Dk-eb%AMz92&+O>8-<fpVBUd5qRw`3m81m|Q{bu-Lk8TcbCmN$T
zi0PcxW~O(z96PuC_!^l`I|9GcA8XNv&>)aI@L{A9_lf0%=8>pE6_+RuC#>Rv9sF={
zV`9al^c+JYe1yLIL>5#5*CBKpN#sFV*i}f(&UV0O_tA>S6Li<T%%Wan*BG_r-sK*1
z*MNzv%}sV}=tkFzg#DSZBLXnPfkroH<44|9KtwEJ0d$zzeWy{_?a{4IYP}CKk4C<C
zz`DN(ZDMw;xY{YwHF+NwyIUly?1x0|y&oA*XWE(lX-*b$25E%5ZWu-y>LvOs4x1X2
z!kb*PS{vQKqv<z1vR1?s1;XGZ3LEIW)^XlK^q2nIBeUHVAnG!i6I3!f0mxEwH^YS4
z*K@O{XMq6O>{&63-?lzqWOL4rPS3i-k4NYmja`KRt8@11QkAs(0vNL^>FfpU6#$}X
zp;zQQFg-m@6jB%kcb?uLOK5M<j`1DRJQ(@*FSL@R41`Cvw4gH>Cqa@dG2RY?Ei>Z~
zkdPqrGv6gh^(dJ^-UA%&^jBz5Uidh#2j-W&N^xuGF%$RL9SZi<L<fk4IVq4KlfniE
zXpw+~fVbRfifRYXv>&2UXVKhYipkw{QhQU<QPY`T$m|v3^K{Q`lb>;3BVXeExT|EM
zpoXYF=%aLfWYo&*^k~UX0j$5h`oG?yi4A>KoktWkKWNCg#5o*ff)lK{-d17_Z)BGh
zVH4`;m^}hYNX1UT{s;y)Pkwi2&hQ}K)YO#Is%uE)>(z85aC+lGQn$S?YBYSHaC5(O
zicr10V9KzeeHc~V<U7NoF;VQcD{SB6j7VJ62O6dk8dpq0fS&snKuXsw5^9d`xOX<`
zwA<y>aR+w3wBR>x|L~P_-J}B0O&Mw+vQ5+yc={GJVp3!<7dHz!Wu2Yabi5INpQPbL
zW%y8Dh!FrBoR%Ox4SF*Tj5WhcAsw5Pu<uZl4j!p|l2jAX(Dq{XEk9TVvtSg(1-!I-
zlc^x?)Xd1x>c-@{WNw)^D$cW%;JGto&dgkLX@KL{JH?S-z@4}#k9Z!As#piWrA3k6
z``?nGiU0$H|J{E)mpPqjL1dyjmg1DkkW}tV9s^rCM3L2)3JNqrs2gW8r!p9GD$dmT
z#YOkBv3M6kbi@qt6p+QK?UI%!z5{E3a3+Cwdr{NO!5&il8~lU1xjP4!nXaJh=$v!*
zagRXs%?Nfl3b<G<+~W24!NHu7gnt<PxQ7hdn(=I?ns9%#tTzmPUw*?kTHPCVr@`WT
zzfS`J=U1!+on*w{1Wt*Lg6v(s0^tdV7%Dz<3O<Z19-Q$@@;VO2HR{wx$E$1LqC)ex
zsJTiSjq@#dTi*r_*bu48mUJwU{vkiK21VJVy#hdBpfmlrGf(80g%=?Knce<4+B|^U
zjA#+9{Ms`*oAyE7Y`mBrsD5+c83L!9f^u{)Cz7blxJ`ddyH%lPq`kmiq^x^h|K?`G
zX<vbpkCV`vl#p}~u3o93Q^**f9sxV{ANM_{E>Y&b(@<un0%($)B3+j#oHrtc5rS6I
z*CVr!BVJ0wwhyH&!p_4PSs!flgfE)J4#WaUsSA(|UH7m-w6hk*nr{<4P*G10iqbIU
zoyK&~q(ARLrT?1)=d~|r7kCC#$t>$BciP0-anR2u+ft2e2fH(h$W8qI-|Xgyk1)Ac
zV~z;-mF!SADfo#VvQZ{%nxsw3L!cJ{<Q8vEI*FU0Ycli%tWdz(yRU<u1zyLPeb%dV
z>%?V1sqo%6ZL+#cHk7Gl_~Kg(3!Oe|W*23rX}W8Lz+s&oNA-Fvs<1-e6{`GN`ox~?
z!s7-u9Oyp=Do2`{oY{AMn!+FcZ51j}8BxFTwh?cGtcxxD(=QxFheZm9T9)}ykp6{;
znv;{u&LrY6ta7(L+77zD(!I~2Ayaa9k%q#9YCY0rOXaL{lw84P#@p|V4zodU5;R<a
zIyZur9rYOqitR<mSo*aQd*ipFU4*Uz_@FG)@;=dIp4{scJYz#b(<g#+gUfp~a#LP5
z1Q%pBv}5KO%QGmadX{r`lE~eYLFcXA_<~yS)4%pl>CDNN7AyexYJw6w%$O|R+TB`U
z0<X!P-KdYoB`_wyPW?ylY2-{%`sh%_1d&n*#9S|vBz2i8YmWnSL{XJ6S0b<<he*R9
ziWUYmq2B08?%<&JPrFY|PrC>e59veNSiF&9fLTj_H6iTS=CVnuukT$+6Xq{ydwF-H
zwI;k?Yo<J;4Q)rWDsn0<-KnA3zkTq(d7Rha;RWRpKrjG2q>VWp;;4+0%sefP7E7Z~
zDkX0%Et5aBAWxGTiPJyeBVnc_shg>b)s=U!@ht76Bt&#zu9(n{dnjeI{5v(9c9sET
z!v<(X?O_`Z(H=P7Y?tZo{(&Py1kjpyE)8CXQ97XK;NkrgH9>*Otn#ze<&NO{CW;Z=
zBQYSMM*nH&XrI&{{>;;v888X@1F%=bM6$a0W<&U>G(TJAEI(~@-fM3V0=7vMK(;_>
zq=iJ0opnEcgM8K~VW)=fLYG;DiIlEGk%+JyjDrT|i5(7d(Ua_XhA`^_*%7Vh)&a8&
z&vkTVs!e9+VA!BrT%kux#)V$6r$a)sL47A)Jg6Nb73^K7hva^X0At)OPp%c<DMt|^
z9Gq&69wx$tPd{`|ZHnz8W*3q?#bT+~?=VEW++ul&01#*>kH+lAv8euu?k<J~Xb^2g
zLq~!V9!Q`|05psz;V;<21cmpjVsuG&UWEb>Wu>`_5wipK0~l$jDHn(vr;%H*-Y<gf
zDO1SZv^{S_-OoTc0acGP!jk~@#XSRfvJMs|v>|#O+=tyqK=mZ`M(3Ox^55{&nTtB^
zm_7W%mp=xIg%?~-%l}0UTXdrm{e*)Zl$?zW%0F(-)F)^mk32fUJuC}JI(Scn76cL2
z3Jn{$f6zeBfSC&crLP4L#e7BTk^0lNzed1lwkQcuf-9~-q3v<UXQpQ1S1`t~>ncMl
z7HM+?m^4o7gTe;5Y4GzA14!oS&T}Cdpy#+!cyuD#@X$iPL5WW8l)U+;FFi?6m3<aP
zG%y*)hzZH!CXt5Ryn*?gp20`sr(f!tK#hYI68#DpC`R|1m{eWw<(<G6reF?UO9rit
zzcl+{hp!GJ_eX$2vSl0R2N(1c15297cNzVA%;Gd%Q|>Na1&NE;pIrnz!3LwAN&9l(
zGPNssWKi+ociCFsl#Lax7wxA^XxGFgg+qO40#RU#0UZ%|<rPZF?ytVOHHU7Vw2?o}
ze+u9SHA`+!(kl2|@<<&?a_E^&P;<a^J5giR$e|^zdL42Ac{<yQU{^9&g1y}K9Ftp9
zcqBzQv4b7y5(L!-2BB{oPjghruZqQsIFJq_XV&*5h22lx?{s%0mC%8~UBH6+Zmr)j
z4Qd=0IPgyl2u=^IH2!2KTm@xO^#&Y~*Z<Q;0YD^o0~VyFWynKxA|{HXE`C`pk4;Aw
zb5t^327#B;_znYwqCs&Xo#Vl~qY!U6RE}mxqq0U3wNj>F`9@nhW+>G1xC?f}43~{T
z4D=3zxh}SKt7uL+Bh!qFqfc3^+&(TRKU<VtP%pcCaS$<9NX~^><V1b3NWki>B5_y-
z+w+{pK~FSG5d8eJU#lL3JR%fp&N+l}8BWVJP@<QU(Rm-N6N{kMM_-GAk+^bRKcBfl
zoXZY?{<4&&r3Zs7pUg_v%oKYHJ!*ODZGv5o$}8#u7i^8wvE_a<ciP;^Sk_(UwP}|3
zVctdO^BZGPtMm#7lbnI#B~S=DI62zI5<B-G($tR!{J8ZwDB{kP_s;N#K|kUE9Xyb7
zlI_87Jaw<8QLkkM6oOnqj5Q2y(jYP{Ws|d`t0PTmpw6{2cy1B+fJ8tRPvE7%Ai=qm
zN52hLk8R?%J%>hONGZjmA){E<Swov!*kxjz!ed3Y_EdT7FUpgfJYWli?%@EVM06_*
zVifa@y#c6#_VG}<EUA;Cib(!v$pE+U=16<Qzk<=Hkj;1L-}=>$<o19pBkbn*h#gWG
zm6=__o@4h|1yA^g#kvMYgbW7l)t*)h42g_!8_G^tfm2u_K&Ube3}tY`$qowY*Pqp?
zo#0bIaYVuA#XaU;4V3>F&cX~wT~S6GBJUF_pG_^e(mn|bW<QptA&2ZbnmM*cNzl%6
z{*A&`&OgD*$n;qr8XO0x-a{8eh|grpzp(vd9mPX(JszOWJg^)fjMj@lhfz?0a&b#T
zQ(hf?A2^(kInQM5fW0PS0#(8&nz==#T>yU2g|QjYJAit`i$JiU@|cruqK-ox7_K~M
z+I`QM3z|qn^<H-|G@mi$^p6e|B&+tk=0WdTBwJIc{Pr><t}jrXy`Uv*a8>W~7M#EF
z_2ojRsu9yXhI5pyFU7|LukG&MPKQgti)8mLr9oOb%_Yf{hBEvEt^)!pffum0%n&2{
zfo8<Rc8)WyEB%4qzcW=Jmw}D)C_y}xI{EdslZM|;<|=L6Qo%CKK{nOL7tEfU=Ja&m
zv0`R?21k)S<kw;8)xAMtW&$Chb~w-J3|sDDTitgPce>qt8Y5e{i5xFm#5Is|f17gf
z#-YtC4w(A!j<B7se`}3M7BSxr@<HMyTTDPf$^6Kv9cxw_U9E#EdG&2iBSn8AeNN1W
z@C(E|VgID|g`>y7Vqx8aC^n#m22V<q;w2PmK2d8LAw=)ngj85Gz=R9tfcd#mZ|Y%J
z_Tt#;Y9UkUo<P8`(cyUs`{acnd2SF1?H3;;wY(p-(Otxnh_68i0$G4q!QxG>&Xj}<
zN25adbD|{yLE+E;`Olq5?<ca7UVALAcpY5e0%zUjyo`9WUUD{r4e~u4&PihW&P+^7
z#5S}Ki4+ZsY4WrvGPriC3@rJ$1R}t{WQ)MM=%;;>Zpa>UZw~?MTRrXtlTcB#CnQKR
zco?V9jYL$-^H4FO?W42SDQ12fd-s_1yFlCmy@F;qAgJq@TmJA_{5VuV{c0v_v)>s9
z^R3=g){~J>R4%|I<h(<=(K;udl#WyEmZ7nY^cy35=NZhzA`i*;5+8zeqAQR^e1~e7
z>j@Cbuc0x)==gf|b>x+K`&5nxKOTn&C7Jy_D}dQ_Y+ySFtn$Zcm7R4VZcdPtV?FB^
zGj~;wvYUhG3lNPgr`cZS_JM4NzgpDVyu%r1X67BBiwqSgr*^O{{Q}@m2jjmwv+Y18
zdL%7e2!a8r#o#vpi#seL$pJH}oJ>Z__XSQD>)gV`kp4>7XqRmydU$fhA|A2s8n2h4
zvl{y=Y9sO`XHtGr0Kjm8S;54Gbf@;in|66C4^ZKL9}Rf$2%|jtpQIu)Ryoiu%Fjp#
z5MeMH<vN{<eZh(V7zB#g;@)X@H%-=3Y0XTA5qUgwi6+oC<aF>1k44EJI5%47yQN6e
zNsfqZ0u0GcsK12dmW5&z?Z6;X6liWL8+yC@J5GC_Y)2l7I8Nuo3L62JVnBAE5}Q0b
z3H%+Ao-?HA;T9S@)KK9O&<wO<ntLA{*kQs>MJ2U|XoKc@0vQ41>qv8ggMh|e>UJ*S
zYq_{_-o`5Ltr_P{v1nf)!h|S)ecFA<VhWU19uMC^)j29tR@Y#_H!*9Rn_qU$vFt+J
z;pAXYgxbVg(t0``o*j#U#(oyr-!nm>JL4aUPcmLkSeT*=Ng64$hdUkA#AFI9K2sRG
z2`EcxtA)Nmq81PXHm}Dhumq^~UBJ71f$cUeM;b4)0OT?XBs~nOkJzY#ZXfK33>goA
z=@;}%H0Y-ROnYvaubU5QJ)_KUbgR?T<+0-I(Bpk)^$9R<ZxF*wV1jwd{q&Fi<}HVS
zUV7$af1rUtbh}ejG(b;`LYAJ+;>?Kojz5&4HXu7v3ux@R7Rz@Vfh4-14m@~Q5_;iE
zePWH`4tC&s@-nl6-kA&NH_$S-fZY5!LZ=mz+oGG;H49XeXq}&ol`>JB19(li6-?DA
z>%%(#-2p%xW8b<-kZDeNGgF13aiU7UJ0r??Q$cwUlSMA}-ktBC)9GMzq@+g(RVO|d
zKKu<s_y!b0l7+2oonqJMyOdYjbvkgi>-)}&z87F_XS|h&bdy)}7+7aEo8jE3PeLQ*
z7YDNJQ#!jmxQhWwWV{J`FQ229Kqt$9S$x(!;*PKa6Z7@Q(Ksp}YF73jQQ2Ya;L(g)
z7+^I%IbdX`4Z9$RZN&SGYk0HBGr!hS00~i})xQ(excS64=C+;8lvmS=h`Tb)k=4!~
z19TzjOP0V$@#dyu!8|{sYa)(8z#{|zUOlfx`WbY{>{LY@0Eh8a^gKb}`PG!E90x#z
z-vvG4G4w$WGBPf-WY9B5S>Yy4?bZ{7R3y=b?GrYek+E6bpm_9I-~>r#h{ghL2XK4<
z!ezls7DV@jusJ*AP97bhF6*^m>j-&@t@L-x$w$)r#TrUraySUs_RN{+0h5E(H6;G!
zrB$!)iFwM?7NIo_Ah`szDV~>!m$+3N_^ebD{z4{Ah(ZY(e1f}XeTHM24czyZ9mY8g
zu`EDzZ)Ccdr4Tgs(nhXBC}9U)nF_wc_Tc9eT6CmYL6V=*IPC)(r2rS09__TkxLJ_N
z3ean58Hq>{q!eI(`j-+v087YRqp63Z!qc;<_~oEInU*-1lQCm>mN3*_?%D<lCO}Xm
z3~2(<po+Jrz9T!TAgt6*O~iXU0#5-FslTshJQ0H$Bx627V0hWYAQs$^b>U!47ijUE
zHk`s_djn3_Hm`gY4<YL5)E&4w2XFa4SmVYNp`<(l3^QQPjnVmyZGxsYn976t8fa+a
zy?1I)XCgTibSDd0N26DA%D^>R9;p(Csyx<TfV%Aj`o4o6#SlprL;?Z-E@CwtZc$&u
zj1qBUvI|KJ{hQ4_-TTw*KWY)%ITt5^M|)Q8gA07a2nLAm``xz*r+P-^`V$fuaN9^z
zq8B5ezWh(B7<t3EAw&f%2p1Ml4JCNSDNlrNZ>UkZJ3iPZy^o0O|NKA_Xy=*k6mbd<
z7ReHvCMYHV6B%$Gr<9wVAGtc>R}80{SRN&vh;9g@hfT-d0x)#4`I%+3Xo8^Cx^g~q
zzWW(~146IqFzO>C>`R+l9_ZnM(~p>+nf3q~yvLs}fPPOj10h&-Z=|q~6qCa|qr8?(
zi-Lp}x}($QAc}a(%*N=GR6RD{q}t=WlIFxDq8}VceFy%T*j4<62-QoE9Y+<J5{|2c
z9XJ7FW`<I12~;Y(jn&t(c3N1?2u~51K&~JqJwmQ9CCl%TOkLgh5v{!GKhdc@Bq-2s
z5pI1C<~k%+1b{0RgabXB8GCnxmW;{<Y~A)F>5}L)+(fe`*^%Wksiq`FFY(!;aIxLY
zX#d&CN*l>gvhQw*NDwQ1t#72Fz&_5R*_+BI`V#_4W9+#j(mOWAUqJd|ZZmoB{!W>%
zBm@jL4sR5NeAz7}UQmITPsv&oDIO-GcsOW~5d~(D7$hv*(tEQfyg(MUPHc!(lyZVm
zKeQPI0cep2$4E+n#|9U5;CiL7a-S}^bwRsejbeAfXNnu6A@P_0X8T};;FM06&A|s2
z@9mu4?-Csg;v;G&l2%Av^Pt(8Q9NQox#_e|n00?^-G`lXAX9}wk~m40Cvl1)D)}UX
z!r%nm;c>q`%P5hGC_Z`@Wi+A~7dwxFW+L}vgMjG8P8x2LbjfVCsTpvmqZp#H8tj8o
zfgqNQ$vvs(&0r;6ki)K^CoqcvqWoUiK7KUVIOJWsdOj08(=DaD#`2zD`C1~YUO}Ap
zG(sN`zSukB5J)?c+&(Q+D!QR5%BKF+gvgO0v!h{rM6;GaUe2z}lXbnqP-eKJXpa0e
zbG}7K`$phy+6}`Dm}kKu+$o&?q8p74%@mk^Hg}e0J0RuqHioi%k8K~(AA#;5>Oz#U
zubYk>^8#jMWTwmmWX4yG`qnZa;l$=~=V2zKvp7UZxBu>&pdnEWwh&{9*%_DF`8^44
zEQ!;k!*r&Q%WVr3$)^O0Quqj?)HO(IvhvsjJ^>Wxk+{1b<bH4XQ_idGpbpiiVI&d%
zk(@nQyl!glOeaxNt#>BFk*oD>AoJ1rZi*x*y3ulTVn9Q&i8g0sM5ay2k5<eBMZjmu
zALFJ`Cvxdt)Cm}$)^+mB@BJUuG?Vdi&p`ge9?DpBXcLA+U}X>-qntGA!{an{UyBd=
zG<0&r73re^y29=hc)@bx0wvBY6N<|vgGh`3b{xMt$Z~>jtUL&y-H#I^{M3?W85E&R
z6Y$$2G}o%n;8q|irjOz&3_BMl2Bdb*!rxzX49RU~$2>U6SL-@^5_z0%3{WhV?Y+Mp
zlc`Ts4iMDT@W7ZYj6aS^fTgYQ?4%YmF<d(2M*(sXxL^sNNRW656af-DIsssk(pb@%
zy?cax)Rpxs2k`);tN53qzt*FfIdn7!mJKP3SvCpO5Gwr!aASs9$%n4iyJsL=P0<!2
zcQ#eCF<Q%#M7_9&<k6U6ih=Z+&W^6nPOb+**;9dOaoWda6E)v6D@sH=ksUZpq9dw1
zX!aNm394IyBIM4j8o@~9)b)qDwf&@!_zEphkZmS}<?3?CXJ*G|I4fn5fy4W@p%XGM
zTwcWq;{@nTXmA)oG#KtjgxyEpfD#2J+3TX^maRZjgQB1wDW(|X#~%RPzHJnUt^5kn
z)hcJ2IMn{X|9B}44S`^%0S*s-DJ41Xf^V~&E}9@cqwaR6yla&J9y_1V#F^s{5`|-0
z5;iHW#GBy<Sx)Qhs05#7|6Pb}>?_*n-i)cvoS;czz~W||Wbv2`L~(Ywq)*-ykCuTU
z|3RCN+^j|Q3BO^0N_ftV`Y5Sc#s7-FKLJ9+_Iu!4+p-rk=~vQ%3-XI5y|-}2l=4|y
zvD{EYN6j*kdEMWpwU^SI%?54P>|x#jr7&Sz-%Xi`pr)74j#V~DU=YUKpI%LCD18uR
zn!5fLi3q0|9bco@Z4+={>Q*+iiONPdjH^?bR~Z}#-2`dp>%jbl1!@|F<bLX^834rb
zn+Q^s#!%^LJr+P0fcf8i@9(bf7K#tRS_jCdL}vtna}41>upEUnu`p(NQ_+T-rRH#r
z?ChD$8~75(?yR3yB?9C<5`=CQm=D!(aZLpJw5xy!vK9oRS~Q4=FWxtI-*wn!yC7;!
zea4+BGZv{lJSwdB2w_t1py=|)G+z!#b)UM-fJy5X%Wm<QW9A5fj~}$?)sUNzgDGM)
zjrX4YhLXJ_u~R2DZL(|e_JUfltmMRsz^t=$t>c%_Sn2j~YDa@p0?{-REWh&}pTrMS
zWb1IZyzv>Sk;){`j01Cmhz4T!4W>x#tr68Y$)^X{+5Jg84dWH@+$2HM;1wR++L@LD
zY1}TRcmZ30Zu_<CSVX4)H_ig+bqvpIwdz#l$Z0xtui&R|`fridb3P@81Fl0@1Is4x
zJJntC2a0BBn;k(;Uq=Qw03ZI~L6P5qaUgv*6dMv!w$peBGAFvJ&q}gIfwb8oU!l;n
zDYI(B6@zKQ1BG={23+<ofHhd0y_Z_h*fZM*@B(BE&g)6e+e#X5bj@_ko45dYXPW91
z4#j6l$go=zSHGLSDpQY-2Q15bZ~yHz^lo$lmb-C5o!;3XI8C%QeK#&PFxpc6ndsy6
zJCTE0l8!{wc3mL@N}Q6o-j%?<3!~CeU!9wsFr%mqHw-qM0C|m|V_y`zH@&V|w92~w
zp3qkIPqCaErP5Go)yGIIw}Y;TcH*)zz*^GD`WAD)b`SJRZ`4fjA(Z&a2!gyc>kmyt
z?Y7JSoPrySP{3OH<lt|wo)fsKxrgThq@lw>2;L%|!p3D`4Uf}C>|)k)>~OG|H$=|o
z2LZ<EZg>aFiwya0Hw2GkkTi~he<6W4d9w_kdK-rFZ45V5BDO2(%9dPk8uFsR%j<Id
z$6Sx3z$uLOFT+DCPsC)5JPpxDl>4T>z*KP&JQSjvL`OwrS3D%$j(|=b8MztNGu>A+
z)QURxO<u)&+QtY2j&P6|8>G+#*$QyESu@Q`^}xNx-O_fZ!?&FXa<QYo4c4t`yLs%A
z@ZTkz#w$-bQ_$L@)rhaA(6w;3;;v4D+us*MQN(hZ_aT`?8>2BxSmBj5%wxBgd9#`R
z%N9X3X69Gp6DFEt=H45|dkBOwJAwXD%{^0`rC>5rEclfSe8x@vVW(386*ka&SN2nK
z-%dI5T@WmZI0cBvV{bUHorKFVMrLMNG%B#=L*52L0|^=n;6w2*aQMY85m6PAY`a-T
zKaQ`?^7=^M+Xz2Ndk5SSGC2CT$b5-3`+$X9`r~Q-B-$Tu&km21XQ4`fE&vJ^A}A5x
z5J|ch7)e2f^I+di!?|G65VB&vMa}(T@E78Eoj5uM?H2fQ4{0MQNaObBehd+!8{RYQ
zen<q+5hZvAw9|GF70BL_AZTQ@ppC{()XKNIu_Vaau#2H_h>4QVNq}d~@>oQ|lQ-K$
z^&;Nj1KQCbjyp48Ye5IVIxSOLLyZoi55Yij)*D-$og6MBuhrhahs6JTw2*OmxT4GH
zfu3oiLku9F-d)^*k|&B(MnT<RAW+QYhu;Db^yA>dw?2f{wDVm#w_4V}Bw(WCj1IR$
zl^tgLky+%T5wi=(Uz)9qc3dhIorA<PC|RC?r^8h^WkHBX<_J$D`68Z&aOu#tv(&?x
z=<7Leit!&XcboX)3M_9p+L=i+sH<M(b^n>nwi*Qx5{2f?@U*TE<bKucS>B_N_ML)7
zGGjqqn1ozPq6u|q#@W|7aog>$JtdsKZnT2r7hMW`krSTMINBrAWgZ$YGj^m!sX~k<
zFHaymqG)(K5Xz+FD0DOYIn_8a03P-6mp_Q0QCCgy;UJ)_I~wy0iBFnc7fctX+ym33
z0PfvOvqe3aJy{j795jl0V~<IqLu0AP+k<~OMF4ZS!#9~r>ElEhm$d%|iN#&0`GoO}
z9ru#Nb$3XAWG)flUT}jO+nGiV4QlBW@zpe1liMex>{qui%TYt{Uk$64hpu8w85+@y
zi!w1G%~_-j#GccrBI7+I8OJFVN%!p~?USb7vrPQiL%>6Wd09Fa#^bl??z(!-cUV^e
z{BfnWnW(-<|E~f0cG`4yOcP6s-J{QD@@f#Y%b&;)<JJgDe&zlok1pj<vUZsl5KK|P
zhh+tiiM>DVwa>D7>I}56_fx-Vp(zZ~ordGc{=u1aK3l-t1D{9}poAu*?{vnt4|-)P
zUQ21ay24a&-OR2JpigM`tQUdgO>Y*|)hOirF(e9Kz~*-XKMk1WL>eF!Dy-JKVp_X-
z+5_fiTyF}C!f|Yu#)!KzFh_6PonHEbmMRnt5~Xu`+7^aB?F1c_5V9-6QlceE!bY2g
z<i>=@PV%A#(E}T>!yh04kT{PxyOTo_M;{5!j`=}wDszRjh*v>YNPmh<OEV0-B7364
zCPU86aRhH^o!w4P>Bf)zwD*<n-JD^Y^Sfl^+;y$@f+?sr#&=ZOJDlijZd)BocSf%W
zu+%t>UiRmWYn9hM3<dkIVKBK9syGRJn$UqQ(M4YCjD&>$t)=wCLjG+Mm5>38aG+)|
z9T8({NaPQs;I?U^?Nkom@ErtfYH2#z_t*fT%LBmW4Djd^XtsdE_dp#Bo<Ff3L>R1B
z_vnxrWFFSZ!RmQE1YKX3*VVINmNc{lJY!^NwtF<>v++j7Ze@sY_|?39@K0}L04yI1
zxG4@VYC>yiY({ng(^X=?xAdwyuxgQN_QtN}4tiHe33!N_bb0Ad6B}XTO0x2xnnz~p
zqsVcd>ZFe>yr3E{)JEeI_c1|fOZI|x!$_Lg!y?sQu3MhiHB+8oo(d$1Zd7%_at4v%
zW+Y{<W-e=4I^c`$v}rtD6gZhkuMasJ&*?&x6d4ZuZl|#E(@#BdDx+Z&F^nC?j>K-1
zp*y7k@P|w`$qGA#VGW7Gwtj_!O&pRq9$bsT2&4n&V23l{s!~^jAu6NlfA$g%icEM1
z0_E)5Br6tRdcmc`;30WwM`m$N_3d~+|3?)P_-DIy`vy6Hc4;u6TXB!UMswLf7_BoF
z`=8#4mx1=+Z_rmpyK^o<r2WJ5AJriE5IwU|@nuj6$akbFCn2^mQgobI#HA?r=$Xt{
zGBtTs;{7F-BF5&Uola3=BVwIt&j4g#HmoKSx#9?rqbw(Ye{Z^WQYZ=oT{z_MJ&q+E
z?HO%ree&hN!HJc}{1IN6fnkeuH0kNV?qRXIZkpjVTiErSDK9uHeZjz9BkhN|UCwOq
zFYj^6YA5>y2?0j442KGfOSVtlC`v%urT&6NP3QvZl0AV6@z)*}8Ghe}Hc3cE^bk1`
zQxglV+Y#NYi1@f6L4ehhbjn%K>$im!o$<FJuObE*%L~>#NNZ)<*7f@(0%8gWp3QQM
znc2~yfG2LZBd!YXB?y9FS%&m<H%E3!9f1}EkC-aqVkK3k7`B?OCV=(<Jl8dBBG5Y>
z?Q~&~nNK!Fo2HbCHpH$=U-W3KRHYI}+hox^W_oW}?9<ZdP0VZsF7oC^=2Avp5B1Vh
z5S_&G>_iP^JK<b$#q@StpyxxH_o&WPc%|I!aZx{Y%PV*8P*KF}F(ITYyVW5-X2hJQ
zA9fU4j}jvG-x9<u$qQk_;xIXM!(_FRT6JgC(g#TiVPmfl1{O^7Eeu%ifay3RFG0|W
z%EUJa@oP0lC&1C{q?R|+0~$G<Rou#1!%Ulni3n|8p(IdLkGlB%&j0wEU3XtI?d~oq
zX(8#zZCFq<Gv18jQO-6XkYoJ<^mBx`2~JQRKQb$jWdB*VyrMV`$QvQ<@o*P_q-l>p
zalODGBeQV9>cn6}-rKymW&r>F)zcYrWAUE&+AlDyW~pZ&_u#-zis2~fkpEeg>qB&!
z0e`dtAdrl%Zv&my@BHy^j8qUI6XU~aBJopt6OwD7e3Hp*B`h%wCbM)T9n&i4JNQ0F
z4g6OgN|MzXP<Te$+_eFC5=VO60)|c45vo)x6xB)?VSF2S0Yb}c=CV6<=;h@R_6MD2
z9<1+9fhn>zd?6zdQ2VFiyM2ImouY|&IV?wZA0MBb#~w#ct3KvQPy|U|zx`jdF10Fk
zpyPpP<Z-v4089Xfi-PWxQwE!PB%SZ@m^vAG`j`en(2<iZK<p=X19C`}{8V|ODHo9q
z>&Ipi`6NCETcJ2$*|K#2kEmWip!pv8K{oSB8btry;AV)P^d6A}c~B+@@Sw$H@mb4L
zOPtoTnuusdWp9vk*CDF?!9yifs0h%6-Uk3BCl;NMF17>x@m)#W9wS6Do&q_USc$*i
zVHiXvSSrb0XS|^PvvqDcEm`LvLeCH*yKWji>r4QsOivR%kCBdf?@YwdzkqvRb-Z^)
zhb|)M=jZB6%o!8eCZ#m=kTvUh+ScXe4FQ_Gym$$&`d450SZlxV#O|&u2vG;XAo?G1
z3tIsh9giA;Pn&8c9bv8#gaA5Z%hx50!Ia_3J9#luqO<BMQ*OPwcj)f=B35?7H1pw#
z2>1~06xi7J3x~Bl8kR|P;3HGoU+gZ+NC(E$#Opeo>b)z*PDa*XK+N8CQvfHdm+O=&
z-D-fHdye!>aL&f<|J?VFR~Q{#tz#aHDGSG7DyaN;72~c;huo$s`SY5?huF~qOb^ZS
zsy$qZRP@klxVy}BAVp0xX`6IA5LT3qnK%R)s6-%=oE`f*yQXW*I|*DDbVjJs;esMq
z%>)w>U}2hSw*|65SjH4JN^c-YZFnNG+OX8_JpOsQc0O2aq=hVn5)1wGGZ<(>UXy^j
z9SFlfcm_nQ5-%}MB2h{@4kd6UDh#7qwn-8L$7AD7sx{RxOy<LNQ=z0w%MX<DQB#tI
zNxu%t0xzF#7lCnX#)R0pC%`nVth>Nb?EzXSKw&dyD_oLFB^KN-cgn>axLd<LUEP^B
z#zMN>`8%-|&uG(z!R;zDEZ__Y{njXO_8ZjVm?9x(Zi!4s>yeN3BuFyL(i(PTYId|Z
zMR?1jwcC}c78{7n1s-S57DiwexEbsP-t6!+Fg{lu9`f05hpsv~>Ak7PHz;~-ft?8L
z5k)~`z!X6h;Yk{0La_-Z!cMfkrrZKn0z2^+|E`O?S=ea8DWujYFv)q1gn<`7q_U1P
zgbpYjwIJk>kh3oUA}DK+t+0P+4<KrD#{}U(B#>hW2bB#i{E7xUnEoVavjaUfNZI@g
z7WXEsjuL$ZNu(S`+F0|5!>TAb%H?K)#Mpb-J&dz*$KIZu><a?a@%&c_hd;RF?eO~y
zrWf8jiN_Q$JNXbH4xmLEg8@<wqXFv+<<xbepz3(4l24#>p_78iUz^SpU@vXLg^7>_
zZnt^lj=4BVQ&<gm&_`NGxPB9-Co?^5dml)P$LG~9X<03+P*_Wp2X!gfnBo{&0$C^T
z(CR92ag%<vsg}f$s5VThufh(KNF4*(VO=V6qmJm2BxjTGp{3ASLVQuQv8lrm-ze4K
z2EmhL;k5Hm%VMMR^59wGoY~10Z<~Zd+9jAxoV;BF11K<Z;~i)A8FOE97AgTEACG?!
zV?arw`YRX>x3PUN3-?5-vb{lzlz$x@!YR-bJ%bk>w-DLmxJ+EV7Iij=5#0XH*CCEc
zc+}Y)sGC&<H^(naDc-@B&6Km_rWes19N@Ku$WB;EpBtVMJe5{xR(<kiJX+@$XmSKB
zITb`qSPD%uoa#Y2ftAJ$?t8CT^duiCk3TQ3aLhl@y)T_n!L>~6J|STN1-9hK5Y@4n
z!kD>Sf1FO{%{rHEQ)ca4wt4=}$GFLVwBi(>4SY#SnwNl&K~Ts8%KA1@Fcz*U^((RY
zur*3aViwCX+I0pz5Z;L0sFXVjpqgzGPSWzI4cNV|nVdO5GiT>shY&?D2|8O$3cL{*
zY}M^3lhE|2YkQBu1;mc$-O=g&oE6~WWc1GDYa3)w6Qtk7`f>)1;Po(pad$eMpi+HS
zBpesdGVU2u;F?<vizRj{I225VMC-&FxD{e{ag|*p=%y9D!!Qq41Djj&-;6mN5@4cb
z-#Lc&n|YCO;)+kvr{J+k${8k6Zoq+&v5L=R#QbTw9ylz^aH_}*=w;g@MjhqM2V8Av
zl+p*G#=CWKoy`p&2QJ8}6!;!FJ_4tr^B?STv3(d2%E>5NLjas|fRu<*C;Y16bbtV<
zd+J>jF(fgW@%S7$E3b2NgV>YklY8$(@BxHff(^Pe%>|$WtNcZ4Y)G#5=wuYM>xcXb
z^M~jGfdE0k!9s4)dtXfV%V50AK+57EMAdh+UseV3X{D~dD$q92;vfE(d+S~#hOc8p
zIDsFSkfdR7mZge3Q&Q1srTnc@q-ArHkN30ph1FB=)G~}|ZUxy@WH0$YJF2bMDDbR{
z;-v(2T}1Y#0h0fiI}O0@d0RbvMk}cQrQ=xQ)Yzr=3os2)P+2yxfA7IU<J9zOtcK+f
z)0`b9NUHc;SahO+vj6Uf+gi?kV9pN=irlu~Ua|`a@n$s@1co%aJH^m!h^Y#DJAt3+
z$aD~-;A2P_@H68@2VO{-zCW)*9UZ%K!ej(m(iC8(kHd?xwr9lxjjja5?ISn_dDn+Y
zcW*%2HI>}&4#4oD*Y74Q!fAJky$Vg;9HBM?g@+7TuvLLFUQes9aw6|`Y$K!FF(DL;
zaW9?!J2*UN#ESqB9b!8SAp2XuKhXfkJ4<>@)vti!f$FqcEeV9c4w<VKn`W{)&1Hy2
z3rX|ym}|OIW^>y%2vO+HxQZzP_@jXU*p)<jhw(|R-??t`csop!HNfN@nWcb&a)G~*
z0WP~6EH!U8L#$r&^atm0QL>S{eLgsJnsM11<qS=01f}~WRpA#m&F^%jPTjSQ7Q57Q
z;r8HSFeRMsPE^{!Vpo%9&jMzqS92{U?V`Kl8Fe?+DldW^!iUF@qUr)ir(>qm?27C$
z_P=2j0pl&guqavuCXd+ECo@{BL-%UjKKi!ETN8uGYx=;~P!`@HllCOGn6b!B$O!dR
z#d#a$FW3ipb~WLJFjVD3iq%nOIReM!>><8`Tu235x@^~>oCXT@1Kh<mb3i=wfnt%8
zf3iL?j~s3VfNzx=MyJ!6xxI`AK0ol&4%5jfNVAwn<WzPE^CU7F^GY;)V`Oq{=ofzZ
z!>^*imBER3&LO|U4(P14gw$*RZUoUPp!KMQfC6X-OARoVD8XW#VoM`VG<HNWqE(u<
zu-N?ay}OCl1$)5`@}Wy?%tRE0dJJ<T<a(}G&n1HZJq`e?w2c0yYXwWWcAw1vMO-@S
z79?@yw}}^q9IH*J;7P!DC~mOAQkaG}_aFYB5yJe4?12gPn7qq4Jr{E(>EXELC{A0+
za{%#(SXD_4vxIpLfC1r>l-$WSIf1R#e)9W{_;&Mpyubh<Ie8Z1U>Fdo0+x?iay>|y
zB+zYQEnZ5*F^q6t*#RiyhSbKvr;ZheG&+SQ`ZysOeOq)~Dp^Rc-udwtG0vAe2@9zp
zk!iK1i3l+HHus4W@Gu#v%aFw>Wz)N7uq$$?J5W9VlT-NU$dJ(5COgG|F)?&eqI5Kj
zi0yQ4(y&gMec^!hdB6xZjp12^$76z|lZf+g@0Mw7)fEHAa-z?8PaD{!*<jo^%?sAL
z1<kcI`SMwu5IsfFwRR`w5c~XxT1w`fIv+Tgj?s`A^VGa81@p`#hFQ=8K`oFjUQX`|
zSYLJpN5^rcWrKU>jCx&~x}oVfD=G%5NWPfU^k%HZN#4?R6HR|(|9cj}0JvCr%q9%Q
zxWHj^x{!se9}SDT@Pn<wbttLD6|<jOy?}3?%P=4CD<Gk3kyH#>Y1;8W`vzreE73WC
za?3`dm$%LmV!U|ege|PJqUfa#{vn(VDQqi}l^aw4b%lY<S!6{i#Ywv>3B->xVUo<V
zMLf1#q%wN5^C+dOG^RS6gVnGW)~*bY*@V!_=yJ6R8KEXmzPo|ft5j0-m`a4K|Jzhq
zv}WatNJ<DLoXbv8vkS&B$DLnP4hV|!3BU{knt_?HEM;m6QH=5SS-(<YqX$k03g9>#
z4GG)15~hsrb$8soRF(tIl{Usab~x*}+pZ-vvi0JqNiz_b3pi{>0GH9|>~N)mLv-ru
z2bcWX*93t189bC!Jj`8o9KIkqA6A3WB%Qk_c9tJZ{5@1Yge>D#9@KG=z!iyVNxg7|
zq8Kiy5wz9LcXMz$&=ESie7nIX2qzI)1EN|x3lR!G4gw^Xxbw;XUhz6Vrwa?$g?kvA
znNkdr27c<@cc<JnrAdodN_@dQ??V-d&ILV_dyJG1K0%tA?KHJHyyp+Ds#qW~R$=Q5
zSZHB1+?be`<_L1?3g7vSU;Hpfl79gMN%BGNU92{D?C_;{><hm5V*#0Dp@GW@nU6T!
ziF~O+=Svph?uP(<k^~1>N%`t50T<wUe3iD2905ON46xxj0>6QMp_}-FkMfh`iyzKS
z%#65#9BE_IB@v$aM}KEgeZG4ak4~(x?Ec-vn3uo}eDLj@7@olrIUnwoUw?lE@gQQ6
z4dN-G-@H_KROKy;XgTk3BL2gp2}H9xx55f=WT`HBP-RHvhIkkM<nM@8I@GyCP}6_*
zHe?|?Yw@#hAA{*i5r1mR;%|Po(2$)-<%|M)3ub|)i}Ce$CSC?ll32qBt-SS{3xB^a
zc@nZ-#TsG2G!ZdBz~P16ePbW|-3+nH5SwOJqaRBi*{f_*6ihGqHT&-F_mhP3?Bg!)
zS+dH%zktPoVq=aKjq-RAr0vj?>`PeDa)IBu|D$E{S@~iySUqq&UI5R-`{N5%)Ia=N
zLB~1a&<Sq@chNDa9<e{Tk?8L)Asa)$zKnZ!gZ%6#a3hk#$<LT2Xq3Vp*?4DFyht`#
z{m!rax{{AnV}EABw)+xQHE*eOrzyQ^DNLGGSM6PK^AEW_mO4%95+qH}%V%PDO>0Jp
zF7u*mM#(O<;B5nK8|G9hfmurFY<9z<M8f^0st@_Q0odYdteVO>JE6pjimP}_cF8>B
z=cC`cn5ei>CVAPb-s34tPEIv#2Jo0{clW4bRtU3JEtvh5ms|q%HWOMkSxpv)r!8OU
zGLz0_vPw1ZFeZqYC;gzQDnm&(9|lQ}AFl+w8(nh`2a4_Hmlxi$RlPR_hUS!1J~@2n
z&;E@P<Y%mFb_nvlY+xDOQ$9F`s#ILnuDTD|t5*KZ(V=(%qEceFw_m;NmzW2x5R#}0
zu}x_>6;z3K^NEJ4n1fgdzTN4HlBJaV=&Eg3tVp#7Yj&h3d(_KTs9d%#hxvzm*Ly0s
zN9ppZB`9`2$!e97ijr3qA}h$HielReE8#1yYssT<Z+E|{b=6+tj|`t*`#XOc$=`sB
zC6#c*^z&+e6s43{30Qz{T(}ogCLhQr^85g|s)Cz!zKb8sA1Wq)oL4WqieUO;TC0>6
zSnMjFuBuj-O32>+;BOM0@5gW}VW@<d>(swEK_?7fn|6~9tza2-)PgZLH)on{)A!xp
zGj4y|h5e*ba_G1`sI@EFKy~?{(aCUYU-Xh?_WXM@YP<bv&kQF3^Vkm9n_WyJ)AP&D
z#KiQ`qtiCC<XrO&v+cV6X8|H*n|G6?lBbex81=w>$r=t{nmaYUGkP@id(N!)UL4wt
z_8s--X8ibypNfL$z;|Vp{{Q*<oqu-EKfaJirvL0q)>SDbe)gZ?&;I5A^Y>d%{&scF
z@MfY%?W(4S=8R)0ynI5lr|ng3d^*%vw6UlWC6t;PlqT$a+po3!Y7|<@{IpBXquOr&
zv;Ml*-`0l{3Ui%SEtjx$dB2eelt(nJ*q*R`YsgRP%5c&f&AF*7s&UQDq_R;;tEA>z
zW7Q`^_hG}n>~|fTUs)KAgIch8w0g-pZNKpRN6;lx8#5r?J*vyb9A+nRYj_-cIkS7%
z+V1OS)Mu%NvfC}`zMHUXY~xp)Mq=3P-t;}UcG~BB>WXW#;T(dzTXqJ;9M$Dn4hM$f
zu-$fhUEYGHn6VPqR)_aN$g)2k^(I}b%TBrZMDs)8T;{o#x4L}T2$+eNJnmS5QZ-eR
zZ#t><C8D~@Hbv&{Xe|mf*Vl$Pf;Pt}+8^F?nKaGXttm<~vHz^A&~-EsYD$z>OO}yj
zt&}CJqz<;bbUjQ)moskAQ&x31%#Vh;9|o64<DJIK_1cyYKskKxZ~vfkPB`X%Du3FJ
zy3Y6j3&}jM{BSMKB}e>WP2Gp7Q<O*d*4#d0D;9;5HI!;5l&F@#Mg)E}z32y|Z+0SD
z%5Vd3g$Zu85xGZ0H}bWKNNEV#a_^EoY$OgxB_gystG{IHPrb6WIpb(2A5y%0QbTcl
z-|uCxKS{k6?B7FEDPFshs@@YiN;cVmSTkit6*|im7e>5pG&0E@W}u(as&*kxxVwFs
zXC86X(<w0+)O!c|C@of}qCT~jGVP{qtY*l7s>y&YsV})TBdM5CZN^c4Wp>+;AMF`b
zoWt(!jP6t{<3>PbIjA}IX`3`8p|k_#(M2;<rXMygM^V+tX`a7kMZw`P(z7d>ezk6n
zhS%)KXvL$4gTTG)^R9>C_WD6SZ3i(!^?Y`6Ur;09k4|J77wuIeu9{CY19!OPkN8W0
zvgTH;0speu2vlV{it?#H|IL)ycTZ)-@elY{lcekV1P;J9=i-I_nyDT@`FNLq!a5wf
zo?dnAm5H94{=o3rF!8?_$F1gRch*gQ9D-ZWI~~l~-?7i$j9lyBN?bjo`@6eEvyjGs
zNEwMrXiYQ1gxEM|dQqIn9(52sXxeL*UK?0z23IpRb#7CyY*{M!qqW$$Z!un44wi2C
ze11pE|MbSa_PzubuM|Vsg#>PD`9X^;J$tm4$Dw7_ymQo0;?)t;5pAC7{zNvVmy%J0
z^q}UeI6ZtHRwcT^&MT+LD5<PTU#%V)27}l%_WxxzRX7pobBKX?so{h_pXl>8ah48m
zA(#qoeJfH>*tB+>u}i67H;e5?;t9ON!BFb*pg)|%XIwV<!~7X7#sg>cWIp+%;R2s4
zyUF7f{2_6TjxXR=e4gPR#SZgRQM4ZWN|?`BL?J3J4pVKG)&`YhC40s7Ywv&di~Oil
znJ!($+mzI<*qn~K>@bs3-ij7<AD^mT4ZmbMiZ(%@VyZZ#t~fMO(GplAHlb=zvgLDZ
zT}~9+H=j<KN~lEHNM%W}eBjth{zdI@>^8P&`5@Jm3Kdtm_4e;6{ytUTZQ*1*MGHJ9
z&o*nS5!WeiM&*>QpyAyrZL84O8s=3uuBMdDsvS7VsG7>h2}|D{D_t>1N>LWNQq>^7
zS5cnlXC(%7KMM07U6Hjc#i5MmNSrVp#r8E-f}l<0rRJ00ct`b#qP~(*E@u>CBFo>_
zi5l?I8c%!Jc-o)S)%)FjMp`%1Nuv;N=^e8#yCpX@umgsJ)|==h<d7%F)U)PHI;<k?
z#=F4bSLc#Tnfc(};kD2-2?=5>>JTwm9L0T!ST7lOdQOy5PM5mhdn5AnD7FTpTq=$#
zsW9AU51yH`wbZFhoc~;0fe4)1Hx=)Q!_YRL*8(k{y6lIC8~H_FYih}S%F6rp(V%4e
z_Gbg`Ar)bMdCdwdQ8f{e<DFgfO#&coX`-rzfvdZN)j#%Es4<v!{$t9m&7u-8aD;GY
zH@POE)s}oavt+m>l^3a113OtIT=V#^`G@B7uZ7C`Qg=S3031FU=i~EX+D<9!c|=4(
zgYzx@FwF@p2t@0=$;+u0)z?Dv-hfwV4+pu}G}e8S9p0xhqTNudI}*44`T^oYwxApB
z1J5!dgZiSjkaq}$lxl1z&Uwp$f8040me#fWy}_wCP<p}yrzgo~%5&^?Q*VRiq$sr%
z%UGhPJ?1?&H*GGEwWCxnr7scx&L@<G#)@yw6Ja*Er%)m8`t|VVs;aL=U8-hQhuiiw
zKhoQ%xLJw)_z5OhVrrDGZMwk;y+_|YvE<ZJ6q<B>BFv|<L_Ug!;XWLJw^kEW`MKqE
ztVU*4ToInp#W;>O?v2AztjB&FtJO<-YEhZ+O~w9RF0U$_7(1U>()>mt6(jc8wXJT^
z_M`=;nmkZqF&I)kt?_n{5;P%IiW7NY0Dff2O;!yt08&Kbx4Tgz=qy{XIp9~dl&{Ri
zZk()%Pcd1Fr8>P}`mNQY`Gl)fqbOQ+;(cHBpU)^>Efs`wGmYc^%3Lbn@}qs8ZLitQ
zqidnIJDwYiYpKg|P(ANIXC_a@m*f5*wWO7joXL17PALsPPJxHUin7QyYOn^;IUC1g
zqA`rMoli1U$GYgV9!ag1Tr!lXnhdMairsxIP)n*O89iIV(@T~aFCgJ#M1eYQq`9=s
zUn<HPhd&sK{iG6+;Sh+V!s@+?{B+8PykVWzN8NR+tOY++Q5sfHQt8s|)%{8o`euGm
z|FRmMvV+4h+tlo%CV%T|zgYEFGeZx-z4r#ZhoeU_`z~hw()()nBbo1Bc_euCmzs~*
zo6lSOX8irj_5uI0zq_sP|I^Hxo<E<t6s5mC_CV{o=vd}X<bU>tJ+;zkYp>m~58BV$
zUt1{n(@kT2N3eZ3yP($x;+?2J<@$eOY-*7aG+vD_`&#WwL<m7MrZ>a*DkQ~>KDbEG
z00DVfuf1$&N^T`nJANUy>?cpof9B+7cp|918{LSFUqfHHal!vd<7V`eX3xxAZMJq|
zx%rdW=w0?tL`UowdtbW!!p2hOcv&CH9Cd1MM5~tnNMZk<dh@gG?{+^P{cHP?U;;_J
zD>s}A8C5%BL?uK=^nG9QtAFX<&bY^&?Q!eCu+wWS-@j`yhCpEdB={{e{C>=v-t?QV
zPCh;0561V$+vBX=+gQ|g2F+I7+>EQ66QHD0KzbF%Y>i{8Yq1vj(dGC=&Svjw3`MtJ
z9zF5Mv48Ckzv|ClT)bd^zTWqhc(1+Es;$(T$zA?l%bxFD9_(ve)M-_(-r4^r`PU;W
zdPdJ!#9{l1fhw0)S2Ni+{Xs$(`R7FEpM6vGPTyz^Hml3Q!?8_0DEf?Ddei^)xp1o1
zcrFYfZaf#RXxU4?z367&?6YA2pAEws!E^JB3wSOx+xm$hbfd<aKP=bc^C>;M7|Xv{
zG3u3Sc94OZ2IsUEtXjpG&plDQ`{~Bo(I=h7c%I8IZoam1U({H&_TC5v<0UP}$8Ls(
zv1t6@$Lf-&AlH-oV|zXGn78We{b@aVK6;dy@69Nl96GkSxw`W~{djy-`#~dUw{Lw#
zue{>bmQO$CuN^raJm&vR)E*v-A71Ny<x?-zz8Tz^4j)hFejGpNUKssV`-M0)5)Z94
z^~dak=C0N1tKn|_%YU|V$wj+GkG1;dBE!A@m3=cE{4h@CZY<y4jL&KRl4;p-ZclVM
z>UuY}FQ5h!EzzAbyjnhK>#x1?#TUZsjkRxYKlnoM(>Q+Z>z}f|y%z7>cT#`UAAZT)
zXTLr4b@R*b#;FqnU;asR?Z}BeTG;pA+HWtVtLk?Gr*AB7Ieo`(N74SZPifz4J~q5^
zUoN;~MLFxX??3kF+Jia6vTiSa#jP%%e&p&coi>%VX6d=+7r)I^?3=dziBTA1Yu~<b
zY~PzPFRi}TT-W;#hC7jXNEtcjrhUn^ZZy_nIwyIe;2<VHL=tnJg$U-?(xuc=`b6Bf
z@?Z{5DPc?)_PtL}Lu|kDDGEC=pSTvUt@V9DkF6DR$umv)*1nZ5y|y~@N#b?;&v$Np
z%UktwxAktXkFwU#>JxexPM%F)SvxWi%^!7j{ReHU2zfPfZ=GpAb~UAadD-hbrr&Ai
zJ~Ly~-?Z+mhcNadKc_w)Kkx2*rpmqA53D_ea*X!j+?4%5oLXwkU2q{fu6fGvD`_$j
z5j;Yhhj(<F*{ag_gkOspx13h`ei$!%e%)S+_MUw(er=6gi{s%)jpo<xJE_mFy$gBO
zd-A0{@C&Lherb4>GGu<u{LQJQ^!{iyy`isKyX^X)H@s{fi01o^R`h*u@;~ePHE+et
zPIw1qV8xyEeeHYQ2fX1Z=v_NfyYbmOb3;45=s@_?(LWh|){fUUbMNc=+`IOlXlK)5
zTzW5D--&h^a}DcX4wusL^WjdfWUqPowKfEJMVU{X)0bm~rks#k9Ph`3_ktEB`Ndjg
zy02$#bBSk-SG}b;%>7hn&t2WSCBJ%KZ6eOEq{HDb@qA!E^~n$A5<V-jWCdP%^`P!N
z-<~vH_tx54j@?z^w)Og&-A6})dMnDD+*Hm*w)sr+{fNen^8XgTl0Iq2JM3JYAj;l3
zojV`fsrp(xZ?&|uW^(?honQXa4%?vJEKZEX`L$040af+qJ1^om|IFU;840Hhs}w+O
za`(OK`mp82YhK^)*`e!0{C({e?^eu?+S6EW53lyr?bV@yc@BojTbkLsWj^(-BOfYR
z6!u!_)gg*|zfnxQW*Y~+M}AFTiXU@h=H~eRBOx5<NSVL087oVkt^eRvL%nwN(zjFf
zqqb|*C+zQsMy?glr;Z1&rL>c|!lEe~AeK7WF?wVJFt9bYHb+>SPrb!*pYvA<HP<{2
z<O<pteFFr?DXqB1GwqJUy@?m%wb;zAZJHzTuw|~qyumLgmN;H(<}X9p9$xjj)V_<h
z7Oy_h_s!_t%Ia9KZ>>-E%v-}NJ@q?R{g+=d>)g6uy}h|Pyqcb0^M<X{%}2bBo!WVI
z@_l`<x>}YEb8-5m^ir(Mze2%Tdl@dZ9xI1!<66u*F0p{0V(%y52BuTUEV16z#IV{h
zY(O!GFvjgWqld4pjlC78Ccs>)$@#cHkv9{{-o$IoWG+bk!hg6oB7mrdPO7h%_`YKw
z58{{E5$DXU$Zbcj>{4E6_p7&je<>Zkrry#Qzwgm=w6k(+P>&yVhLho=uA58rVxmLb
z$~q=Qxg5_Wuf=R;eW@~BPGxLD$yBeE7+#H)tDM)cO0eGuthq$qOFiGpB~Qe@#?AGr
z%>en@ioJSYsGt+=Qix4GHF~dJSG7t)cvO06+2Uf0alt}&An$BO`O}27dfrVbPZOY-
zamFTK1476GO#YvnsVWGEoSrJ*p2`gJ5`l&RHYx;Kzy!839Bzr9<8g<U1*nOlUiC0%
zEx5YPjuf-G=J%bktEo@_;uhAZOSjs3;14G%cOpmsc*l{JE{3XhGTMiRL8N3q(Nvm)
zQMDEAOEp{36QFi;LC<Mcqk4&t#i6cMV*F`XZSiM%j;zN{X{BJAq94!H8yO^luluRP
zK`l1jRMiO7U3xsPX5*v!U=-sj<4fU7;1X+ApYtX-MBj2y<I|*x-N#7Z-}vN3=Vthf
z{>H~II@95C=kxo1{vmGj&Yb)6nUCM`>%U{al-=&1tbf{G$&SDI8-KE~GCKa|-aq2E
z$D4mOc<~^=NAmm4mA{^dp1Sl$&U>c+Lix@dmwDjD_x&?Z*%zJL1H&(j-TD3LCvOCA
zOx&sW{hHRf(gkxi_&59hMgIfljn<v#_x(K00yiA~<qxb~`U?)1_yenWN9Up!ohNE1
zqo>v`I#aciojc0D$#u*V*=*;IwCtOEFK(=8+vScNewRDqsR&D+;$No2&ei_GbMf8B
zr=LW;tMgcLk^h}&f{XAQ7qM3heR3x*!Gv7HK5PAXZVQ2~O%g$5@7ktcHBHq9|EpT6
z#!=`mwDnW2tK9DnC$5?Nu^NG}v26e>C}a^%`)<S^auEP}wpUdJce;xoNG{J8_=MyY
z<XN{fs|tCF`d{&H`TKwRRZ9NTKl#W1E!XON-THE_r21%Xm+Uixr}R0r5~}f3)J$G+
z`de+YoQf`=8S>TeE&pF-4lKTSnuNo+U(bHbYCIE~kcLRbdeZuIqjv@J+-v&I)-}^k
zf8D9_5J8K~EMP0fwFH<5TJ=h8i!#vHn=ncLoxw$=HXFNxaej(a%byQ2jA=^+wm%#s
zqNk1b|M||6I;1}&>1#4__>N88H!pX4=R6yI{pi%0MrNBbnJj-eRE!s#v7?ggmy%+3
z@|KyT`zS6YJ*5G3#}|h+;*<gxX(Z<GGV_TGD6It(jKQ%JjXzpk=~k-q#QjS_7uY4f
z()55w?0>tZw2i*hDBz~_Fbf5Vw5<y)1-`bTgu9~(A$In2al=n)BlauL#Nk2Pih2@S
zm-&!;Lhmv6xUuo{XlkdfFOTY7seH<>UDB}&Bt|_zYJfUCv!<LtyEzKg(qN`<%A+k&
z8%{CTCbU8|AE-ffWrF^6{rv~Nfh|ttgS0*qlm_k6Q3xznEghv(6Ph3OCCt&hp<BuO
zbDAG4jM7X(hfG*mwv_7mc_X1*W15Q|tn!8$YLHJI<|Y=hi!5*$oB;9xW328O)cXu$
zix%$RlDC7^AXl^!yL7VFeCXK0H+4&W%Sc|1`<A1DCD-hG{eS*&6EwnXSJ`i7mz8F5
z{O*|m`SVlyJ}0())mg~fy?(}5BX+Hxf)~r9^UMk;z!DIUqG&N0Wi!$Fo+?k5;04W}
zwoA6Ezz|;J^Y9e&ftd)ZiDq(P0LmH(TlDY#=(6tU`RUf-nxYi#q<|dX)`P2Q-~MlP
zUqc|?+3v>+@nLs+n0+}IjrVVA4z22xf9>7A7W4!O(CvvZ41(U*O~bx7;5PCp@}wxh
zz-JdH=+Tc8IaRkAS*3-I<f}=ox*VA|UrUq*W8I$4*T|1AuqF)@d2)mLux$ogqsPAf
z(Y*JrN4NdK=(6oqoNXkm`cTR{Tr0=HhYn11ZBCH!<TmwDS`xkK;DlCw*{?mTxBX#f
zQU7df*pVi&>~CfI5_IzHo(SlYH=<wCw6ES%GxqqUH3x9}UT*G^j&35v7A+TVVR2Jc
z@@aBJQ?tVxq4AM0s7(c3dYtI%4UUB8{HfY*yD=3ihXc|-_uZkNJC(`TgR}~t!Q<>i
zN)0a>mGq<3DOhtaC`G=WvH#g1>R&A-;x>j-+5%=tj8PXL1-Y4=F3JX+FnlK81$x*B
z78d!JoNaJJ=lq1erkIh-{Mg;L4n|34cjwA~q<of9y#~fFx60$X)cc&Kp^mFd4zIyg
zl-@mhly3v%SzcgpS*?fT*eKgDeeR_=qA0_O>S=xsn}Pj{jR?5;s(Ej9-REQ_vx7df
zkOi~hFPDf$l7XT;;C&>|%%3PyD(NUOLKUzCxSAWVL20TjkTOc0Hg!~=ap<NBhUGcj
z09GYddlJii0q&C@taKfXxL7`s`@qJUicNd~#vw?b-pHoNy}RCxIB?)VpZ?UxJe`M4
zc@C`?UenRlz)`3y+syC5mtEE?2`Ab|gdQ_#I1H|n9WCuY6+2P>UM1KKbx;lam-T$A
zma6iE*wLT~ls)G&+CFhPmZI`f7%P3Lpcn^g<Cpy0HrH-0f)JlrsD}4$Ut@2^r(z|%
z^<cnK$m0YaznMYFOO>_-7|1s7P~sS%Hw#lV+D!0?C;&RU5vy91=a_I@<2-gR5k(qL
z&Ugb>ARgdfyW%9Pp7T>gg840)T@8*>2*svU-QM@Izfn5s2Gzh-+g<ji9s^7en<wMA
zLa<D*(uf!1(2L{4eh7MTl|KVxgk%x0m`SA+Zo>*j@`6eIxg^Em!I+!iXE&3|Kt74r
zOoU24PTH|OAF0&P-wjf=qoE!x_;H_gT0gb+e_f>f9OOrRzWp$~2g*50G1Yo2pla^$
z)S!wU+aGY1I!UOrJG(&AF;+^bg?W7tbD+$DY|5{y?C4q?n5m_~B|ADrLApU<J<#1g
zXKggvt5)Z5d&C0O({VNNKdpman-wGBaWO0k*_fO12D$S_I&xC{M36Q`b4xL6Ut;}I
zo2ArTin+f6|0)qVG!BDjWdXWa`!JDb!@1Q|!=;&D2~I5*W6zJDAdvKnseHJls^*>4
zcls62)K3v?b`3_(sZTgrwXMx%-nTPsoodJx@`SwsfVaolnpfTamfw|G)D3o5q{oNx
z3xeKKda9-3MuT5?t469C$BDckoOydsOq`>IRXgG4>>#xmu@7Q)gR&G<ZC?HhH$LK5
zam`B573(ad76*3TRRfHQ*o#0Zea_#FMa)OEbF-U#m1opSZ13bm3CCC!ELe$ye1d``
zrG#a@N~X1@>+@=UKo6^_xuaox!m6&~srqd$o(%oGjos!Szi{CrA=cW<s&WZH<`vru
z=G6Jqk%RB`A7V4lc?){HUr+4_<~Cy<S|g&t?4wclVJm+llJ@{OTqT1uAR8QQ>|V^1
zq$($LmSxU1){F%$T(ai_Q>`X348BQaqiRM|A)efx3Zi^uo$-}3zw_!nN-?9S%&4T=
zO+U4EId+^lUgBuw_t;H+HRy^4qf>DlQI3hNs%`6wanJ-sO|6I5t17n;8;yW>!2h{D
z;ULhma5-if2@Mx*B~Mh9QrHO{bI97N&4lD5c}%>nKQ({v+{`|wPE&6>Rn{|aAVjnn
zy%lTmVE?O3LHum^NceCqj<8jY8?E8!fAA~u`OI^f=VEnn|6udLeB+RHBC21|``?Ye
z8l0$Kelt40f1iD{*<725{FB<;yK!st|0V5hpxe0aGw%U3az+lDCB|dER|uB{MkD45
zq7{i@TtrP%%y39uf)Mo)Im^{<TZ&P<jMi<e#7&i)oObTug1iF`B~qomi0dW*jd)>|
zO(jRkk#pKpl7ekWW@5{A_bBi7w34G_m7L_QBs;Cr&-WS1Nt`y@J?DKH2LeH0FmvaA
z{{GMZxv2(`J!goVlOohk9w+`4khXBkg^FLnZ=#rxPe&d}U9!04_o$DRhu_$eNdxi#
z#_7{rc(U#OM%T0x)SQkA4GtH>XXs{oBH-QGN{7ZyX5K4{ze~Dr{^cTqAm^KXZZYOI
z`F4?Hhq+ta5WeS$3!kP<(*K^GE+lNF=duG?no8q3jsDm)w>#!1i!C>-%})|`iWfh7
zd71=0l1*$04yOmPwwq>Cw5v6hE?-N__qCEVn2-@(?~>)TO|)W61ok<}YveHufT=Wc
z*!^(JA5cB(t?O<$rp!Qz8*FSC*`(|p{df?Y?kZ9>e+HXf*V3ob8k6BKRKS*#xBl|J
zB{2lzL#Aw-BBMyfu56<JZh?me78dNBh}IYQ2P-*FGi&Jds+|=}Sm<O0$m#pQSJ6@a
z_@N)E1OdeZI4cSqt6E?QXwfmPTzmOvJ=}RK#RAW#(IlZ^b!&e1ejFBzHKL}lo)G1Q
z{Sh|Bitrp0r}Qp4jQ}^e>Ds}`(I4DZu<L`FTb)Mg9tp`p_E*F}GZ8!~B`tlt`Ko))
z6gNY_#Z!rwklVXWBwr7o*e$k`J?y5y?v{;857{qw(GjurUgYfr^4;5xIkg=p<b<{9
zfyQ7<Y~7c<*(z@p$(v7*O>a0Nd8Tr8G3!hx9{*?~-$#;LXhPN`_~Oxkem60fostsz
z*%Kj1sC|OhB91srmIUkrB*ljqUD$!A$w{9#5+BI^H@VRH=kiOk@zAG#K$7LgLRzHg
znfZOPU@jz%;}Za=qJEf8<2dPe{?e>bb*Ig!Be~*#5aMu>otExi`89cJA))VHyGj`T
zcsGr(A1*xC8O%8!*OWc%*op}*H`Q1<2nU?Txs?Vsqn2{FKo;K)XN8=o9Yp}}ro?4B
zcxeul4gjXCmCm7;(S6|IQQYZ>CgI+uarS8-(;1X-^e(wzmb4?2@iKk#9=w(Zmn=7~
z?ZiJQ1k*g->Vb7&BV%eb<3GKcpS*>?%V)#}y?S`se1W6GswZ}i%K^v|B$hZha`I@n
zSOyQIcv8@+8_U=*Y2cqGMcyT^J}7V@Gi3~{rN>v2KLBiOi7V-wWq`@9WDhvziKn0S
zd&Jc=XuiuqRyc?*P2<#kY&#&~IoXiN@IH=T5tu8Z6wK<z)WQy2S{z0E0Wu@~{ShsF
z?bClt@U~Oh%Tk5MyuTnpzG^|fK8Sy$`O+``obKnZ`TJV~s$wUv7FWa`M$>cXO%pR=
z=5Bom#S~LAmztWg+t@9t2@7!1-MiS@65R>;Zu-Q2kinjLV5I>yd5O-iK<y48RyA>a
zWs}AEIp;9<!LD)oGB$<NjqaF4as`H9jtDBYh-^udCO1$MbpyjW8qhu|_m^a2TXgEB
z#wmKEB{7UF^eP#XKfQXy+Aj^0DS0*Aw~CeeUWv$o)Rh9Z(K*C+3-40cIQ23%am;?L
zvWul|3Zq{uU8fu4rDI}2CLfUDIlr-w6lG(dn2J7|h)$_2aHqc@tuvJv)5}lGbP>}=
zKxkBwqu_@~eY}c_0t-V}ANVMFlmwhA{Tcx74pam)E_c@S<G2JH;I%P%@Y_6=>Tj$%
znYb{MuS@dv7IgYDzc|Rz2I#HLu2%#6ENK)7j^HdbG9v&c1H{MESJ^o$4i&t4vl5ok
z0D$Q}=ckq9;@t(*gGM97J}CYsY|wTYSTRxBxl)!lNpec0uF@=s$Zg;EBJPM=NR%6J
zB9ka*UlLMm$SW{l0TxV|wT*Bb*l?sfp4t>$lL#Z9yK;215mYdzILx)*Bd1rZrUV~N
zelyr`qwjB1H8{p0{;;+SmyaGn_ps}8bPC5p%-)p85um75kcwu1#ZmXr%F5OUO4l2=
zeP`<f<hXy|%2pRXRwzvHbZ2WJ_kWkqI@YDeC3D`<d!F@49L27niloqhblrpaK_inm
zBWQ)n%aSUnCgniOpoL;{C7dfn>Zr^Ls=GK5$~M5{B!AkiCd#xvz7v4=cm95T7ZCO<
zIOUYTuZ0G=ERORms`C|A8GM*X(6|CM7v@mz&_L*qC+aRK-CA)DCR+Zxjrx0qwYA_R
zdBw?n^`a&0Tlud$W9hA~vN&pD=6DIS?8F42=#G75b_E5efFokYypRw+?UhwG17X6r
z#8)oKGUCaO$F2C1pgZT}#Sm}GFIqdl8EEvE&>t>C%BJR2ofH@dqn(QLEq9eh1<kcE
z+0=4OeOTU=ez@Yq;i>08nHKH3Z&wC$@lEnjtw7?7l$guO_7xIoG(c1$ii_BW!2aE2
zDTH0NMn%=cY&eT4E&#^5s>O1ZaV&s9%V#jt=aF^hIK`6tY;3ZP?q%KzX;%f`1(u1i
zREx&Y$)~X8Nmc-Q!s>oCE0nI#&y6zRQ@alU$jIs#93$$fA~Zh6aabVIB@_-Kj+nLk
zV_Z)14@aYGn&VBg(JKXwNS|UBgORhws~E_YtT#dO<5<6#@zVgPf+OH43etQnip7W0
z!n&NDX}%Spe)$eS9sa$a0M!2-Xaql9qm^IY_a?2}_a?23jsaTv*c}S{!!-)~mV<0r
zh>+)>;M4#Ak>~%{gGAIdqOX`v{NW4#sV9Sf0C6#=xeZ{tb~)gucL=VNzxCLCsWwme
zSl=)W6ZYr_Yj$+FshAgIjt+hr{iiBUBuR+=TSKFF-uY9HSRF=pHiku-g&|ui9@TO;
z|MvIad{gg_-<*p5_-V8%`_T{T;{WmIkA6#)SA3)`4lqdXKGf#zU`uqyzzRMd#sjCG
zMnawWDWbY5K2#ygDNDZJ=(sLoMMw(dQAdls+vg>5(u!UKeM)P{sGapgsVd%88NnzC
zsscGAh>jrDw09MN1>2`5rLGli?IhFhKPRzX(dnjLbdK~2&Z;CyU246tnf==L+mu19
zj3HSWWoTenX(4>jCQ{f#&E4LK)(R6W)62>wA$S;zK<H-JT|pzDL~skO%h!Pu5#3lT
z2C%e9Nt0A_8f1c4W{8|NhRKO1x5S{9P>3^;a%53;bbL&En7;A)pD9>l6Oat2Wh7NE
zt*+{AdI72fIlfF&wp>6fS7iSRSyi2I%VF&KG{zkpN>62pNqvNXhNpR&L`c)}vMd!F
zD;9$q2NYD4=-jdE3}l(!Ty`2ESZ{$Bi;O^{=3C3u2TjwLGJ5o$Ea}!VyfW%p;thXS
zPMsZvO*NPcIzw&?(O-<~E+*DO?1yj#9~;Av;<v}&Wv9T8pq7v67W$^~)VN3`sEy)A
z#d4tLE5@*`16IJcHjBl;$tWjQ6yx1EC9KU*X*nn|c}y-CI;9M198YhgAA>2R_abRz
zv}ygXKJ|8}Xl+lYKzvvSIKAx#7RR#|H?eu7KAY_ZjnRf;L)c(qyVSw0BMb_KnNr01
z7m^3XcPh9Gl-ym2EsX-`V)6h~fj2;QlZwq6xOy<xVvBllCDbqwDHJz9laMihnYhwn
zz3uf4qP?$^6ytkEaMPeJ%fyy#ak_{5M$2j!c9tX!APPN<^-t7<Ktew}!PBU|>v0~l
z5Y@@e!GeKX!Yi{92&gJH15yhJ6H%UcwTSYBU^j*e7N@-9Fp$kGnaz3*?vv)57t_A!
zPo|GTP@EOCxD{JX2Q|N!iGP}@Zbphle=R+T%qd|v8Q)D-ZMb_alM!OVZxA}hnFC^$
z3^uVDYe`|pBbPnwK`W4LZZm`yHWPS#0U^($qIh$}o#q#KI&I5&gdQC1?v2G87S7oC
zEssSLNnv@X3+Zi+gRO8gB{2UPEyv8`q^J=rcql(lmHT1!OyL1UD`s!7?xioh1JOO(
zfj~-ZpEw^AR5YD2yAV_QW1i(2(%RrCpg793A<)H;0gBNDa!M$oGy$NG;=+xJk~{@&
z8N!69&KzCQ7`h;nMd%bY6aXPc^;`?;W7wLVq>A|KS2j39i3v1R&IR{Wyq&zvxT6W6
zTvyX=R7TZ1gdBQcT+M}K7CEm-vT~t7R}?E^`=}&f12&1c8uMb&wIlWn?uo{nc4?DB
zF05SPEr1B{5>T*BaWw5MaX?LZ>*%jXsIoY20~xMKV7&<7L>(v21l&X^8xlN-U?3Mb
z@90nAdb?eNULu8XLR1tA$VCUCcp^NFK<|}R+G!l@HFc+Tn_#m*Q$%DDheaUh=Ih^Y
zSDn1w(Ay{6Zgg*PksWi2P>XtVMy8LFr2=6^b<7?_S0w^9uxvjj927mIb}qh0N8mP|
z0xM04Lp&N!ybZV&k#k_$rtvX9X_^j@{<uJ(qe1)?FXoW)GLbTqXi%D=-3|H_Z7{#Q
znY83~`$XgIY=0C2QkGmX#yhZ!B1Wh}oSbx*I<NR54k-*MwA}`4B3md-ZkAf0`Dy7p
zOa5M})Jy&b3`cE}bN`Ca&>=!nj>vG8<CIeYt_%DeC24jr33;S6WhyOYx>5n(NiL)@
z@vd_J-DhG$+_nZF&x5EL0Tqffw{;)NA{2gZq5$2X@8fo0k%)^58l9;PehRR>oeCFQ
z9LsbIbJkIcyF@iizW^3z@qYmrib@M9yAq+ns+IH+C0^LiyEPLr43TK`d%fhMna1Fv
z>Ft-_tI=*(#_e`D8YZAEo?OjRyX>2>B~X4SQ`Mr4z&Yw9#)w=J-!D(5VmvKT_fuL~
z^`MN9?OI4ToWv{WL=-=;0r;pW#`Z&tCtE@6dCiBK(|0lO;DU6fc=b-|chkCa<EbAg
zrYVw-847EsRst+H@aJhN)(-@|g93dq3H7XkR4IsSIk=u9opv7=j7VT{Sx;fL?IZDu
zf~7-ADkHgeRFP4Jm=?zgWZ3q?LTXTB$kRwu)Fd4(=3ZGBe3qG{Y9p3Q*v}8H7xt2s
zgC=;ph0$gxPRJ0)(xUJPQ57@)8cG1YP;M0eXNJ)y3F18{W<+-JAkgFZ7*8-^M!Ucr
z!03Yb0!oLXX#tih#kjLX9L%U2Cl%eq2Fw_FxEH5h1<u*uPbkhbG}1O$xW-)<4XzyX
zgc(~#ZSb%qDz!0WNB7jnpEyZFJ(cEZMK7kgz>uYbyGE@Oa1jhB29htlp~kYOneEa5
z$E4K4IIn*NOLZ-r@ij<8Q;6e~<7G6RU;L66!$z0wZAd0j!0;QG|4tMk3bt?=iY;a8
z8>})<$X;KrO1Ytk>4b_)Mh}={CayZ_9&t{oETR!oNK74s*p8;5MF9+jR_knGdSZkI
z>qn8bHc@p1*eQLU6@@x6*suqsuRhqYN$S=;zfyHL<y7(Xc?;#>=G?;)H8wzx*^c@p
zV#->{xF`|0%n@mfHz1q<#N}S3Nw(z4VtRw8;amNX5h~LfP6EK6D!z%#uWb_2cy!Iu
zi(wWTp=r#7;+Uu0_~Y<2wuNg3f5x8F+uvZ;ur*?FT})ngc3{WD@ciTFrggvnyDR%x
zH+bf^{j1`u7Cp0C<GOqPFW8*X?)1skz9$0l9Z}K$U|A0e6PE0Wta+Q4dyG-4zl#Uo
zsZDUm&u8Vd9c~D;ke?l$fP6!4l-bHOKTeL5liNw~QNFf$!qcR@FeJ+yQ^n%%PCO;$
zYx0FgP}_{@%3@z{uy7SILPSQppVWV~fz`4rkvi48(Uv<|Z|h@!pndY1!(VfCnjq?O
zH$6l7L=a>vGiS>;E7s(7o_W@KwlUvX1O@J;QzPN;wT>Gn<uLEh8e~R)`6=3(f03;C
z`lMFeNa+)PswIo`sx;V&J~>Y1rr60zAJTyRlQN>Jfc69dg^x;Dpz|dCIWCJE5b35V
z^F2fvp~d@KviuBboXx)0#n6xawmdmq)4O3zP%Qp0OssnM2Q^|&cZ%sw{k3;G-zMiq
z8@zbyp=ZbJH{t4#Wv}T{J4m*EN05rq9>gM(zQih41|vTlV7kH=(TbB1U7fNmy>z+t
zzR3uzLY#_KUj$GI)^%%=)HvxX|99%u_`4{)f_NEAM%pmmLSi9cjUX(*EVlKCNGw)3
zNe!;~#Tv_FbLfAeON}@y#c2eK(Yh$8*C9+jC+m^u=ADr=^$dBM<!>cE3e(Y%LPnTS
zFs@K+!|s|>{-Z5{?Y{OGhRa6|(3hHx^41UDXco4)*<mtxeNcW}G@Gf~#@%5xQF8V8
zOH4-cv(L+kZP2AcFq)_CGdNk}Sc_t-=+VY~*mQo&XEAzw?&N*tG`1j|19-eH(~X3<
zmmWz>?@+)d4@tRY9$Rr~=UEHy4*>S^U!e;dMP^~s30@2HkI>7qR`~Q+2&AbaUHgJt
zQaYc0og@dfEe9aC8_7KL#8uHeytB9Rb#~+{FcJ!7Jfweo=x_e#-(0b4u1RmWZl;$G
z%)1dU+XEZg6MWql#SwK_F6@jwH}4{dZ{2lTs7WY^S$m~Z0UqnIEND}=8q;95D^6Yb
zX)z_ri-{aOIZr%&ri?qW<x{@?isVuQONFKuoDm$Ti%fz7>0o@C4l0Z}mVSbNLpBDh
ziK>}_;ISNjlAeRCGUMYy!I<#Qg-^_o>Ov+S)UV;_Q=*aiCa<-|d;R0fnfQ#9zj5fL
zuVO1QXf%%+4R_49A-DS*k}X}vhTO33e!|M?UxOC;9)0q*Ye6*$O()p4QLelC<Hv;B
z(dx9ex(|nMxNZcsBT46BUXnuf<!Q3aU}C!8PuT~}wEj6CI}?z{(-_Li0L>vTLBlmA
zmx0Yl36XIxeH(YDZa%JMV8vK!6r9kZi@y+YWY#_^FZR?E)$(54lm{~>p&8E9&E(Ue
zN&Wodc*fD#Ur*kpuQ<s|t(rSa2hO_n!&$M5EfH@a4RCns9(|Ad8Ml5<@+gz_drqJR
zyGi~H7dFYeN!2Y~Z?)Xyy*PogxVI%4!^E(Q9B-A?sdP;#A45;S?BD07;UQ7h1mGE9
zEFSUeq=vf#fQkL+5Q$3xl|8sK{pJ-kX>d}qPrnVtoLmnP?x+7;#!fA4nq}bM9GvpA
z7gf`bE~FS(Z)AYSK-H$Wn~4uxbL$U;s838w?kfxdb(N@$?_#bAL1yY1@u^nbt!~7-
zn^t<sPwV1@yiVnMd=G<i6c~6$UToXjNZ*i;r&G1caX)>6FIN;4IQ>Eb!xnBVM61BP
z5%`su;m+U_N1l3*UNvDZnOA41UtS!*q4JCSO4`N7F8~t*c8250bt7yX#1c1Q=cYzD
zekFLC{f52g@7EE}+9wC<rZVjAw8?EDqOF}L^4>m~(Z<-&Qwc7VlOe>JydPpxTgSyX
zFiEDJ0CX6M6{sp{eXRjZJv}W`wIHe^2u4idl9HTKnBg}hAS>EN8r&KY4OsCs9`rOg
z$|rm}LnS*R&PdsFK=O<70D9`3<{Wh8=^TBkw~JhC44PGz5r7oeJO1WB6};FHu|LEb
zCiyzemPTC|k)dB(cU(4-@vk#yuXHl?#Pr4!O)beMu*?taXPg6as`0T%!hIAH<ADy;
z6_!`0WTX*aT*ZQ==Vlr6-v3C`*dJvTT7wu08WXzGge=4Jx}*WHf{k954M<`W4HGij
zao>m57qv4qw2M6gtUh@t%r|!M!N%dtmnu)UGOEweB2eiX?n{UMop8p34?-vrvv+Qa
z50v6l@{}3pTaPGTZ{l)fVbMtzM<u3Uh>PT5pVMl%xD*Id*Hv9-R&GHj)O1qIlj*TE
zW{a08c?Drl1%d%(44&Ai5!#kT?6R#CG{~(>4HI`#!nEJVm;)qrg$N&F=cfks@;TqC
zC8k}#*h0fXGi0e1scfTYkIpaO`wkuVi!0oAQ!yiH##1gmXIgi;{eHX<E~F<_d?VI$
zIm=Q76sD<$aJUarHYgEIe+Zi;V{(<k++HDmDuxq7H>Yf|K&MGTOCi%p33iY?mg-!~
zO+?DpUavBaAPe(0E#sZ^3g^%nu*|Jb{`^?Wb|9g$F`RiwvLMF<pl<=O%8rgvwv`cx
zRK3^?AX8R21R~WXq*KPjIoYoXAk^__iW^Z@v~zuC5_3R=vsm<ZA8-m#6)3htM#HDv
z%2J8w3696<8bXDP5+f;U2(miBSvMu*Q$`1=I2dOeJ&1=cTA66%wCWLRjr_?H@BaIL
z_pijNA3O7=G!!D!HEC$$sh@_E(-9~A5o~?KM&vaTn7$KyH<E;Y5CYS`gTC|GwWG{`
zY|B~uXzyESD<rRL0@K&bJB)MN8nZnMiR-^DG0j6d`<BBr-aO1(C8m*b_TN58q`!U3
zL4I^DZ#@Xb#NsD9)%wS1q`v(`wFeVis&vb^qAXzsZ9?Y+(G#?)0_$bSp+N~8){eiT
zmi0u__jL3W^LA8^I}cC{jiC<S`N4W>ZSIU!sG?xWFZcAk{mnn&mFP1+{;_}j>@82w
zV4~^uzxqkN`QnYg_=Re5Vobmdx?6snUbDxY?b-dr2^ah@u6JwQE}S<aj#ql>5x3&H
zdOvpA8okfp@3NdAO!w*kWpl@bTl`3A%;iWBET$io4%wd`kfpS>IVJ}?wOJ;M9Fz-4
zl|u<PoaXvt@*czsT9OMM(WGRSP9MtaS(sK>L)x?frJs^o*SnoKIjOhkJ;i$GMqaZ~
zJvH;)y&K#KrO6}M=VEz>aE3y*_f_?mMJ#uW!ll7V7*LWs6-RbhhTfa(ui22qXgT_v
zWJ}3hYZQ=MhAMy?q#x^{<iN-Xu7Fh}D4S9=W9^ht)1@oO#uwWeSzBXaQ7r<eG8zC;
zS`b(M{2#X^&DgY^+I-R~`kUgt#m(tQEi*9rAwS0o6#%ECb%Ejidg`;I@3OfwRzje@
zf4w92i>Uz)SsJd9tF~7&u$_I*jks`9EixD6EUZC@5(dB?9wcwv<LNKZE>?^S6B0BH
zDhc$}dTQPM(u!qbq_gP1KQYRvqm#~C|NKQyb+Im1y{JpFaq9=P{#en5j1iz3NvKe_
z?PDC?3D8-^#LHp}|G6QgQ3_Cmc6^!hisJZ)6gi53ILPUU&PNF{>A1r6hmmA?1-hz2
zJs-$~G+|ZzTm!4u>$01hEl@phFQiRlMK_`J^9_IW^J+C6iFx6VfDG6eX*ZgNex(%8
zq1L+sfq#rb$-+Y{uwCIV>&h~gtIHrCtZI9kdD@Tl*p?cq!p<33|1#Fzhx|wmxeFW_
z^lnRC>Qr)+8x!1_L4Gu09h#3OL4u|XOw)ahTd`-rrDkdIZqLHiVL3l*;dU2d?N)4g
z8*!s`HpI#V5E^}`NcK1)rqk4+3;Ofc4kKAl3pdKTM`~Y{0Zt&jM5;Eo@fuLA=JFH@
z0jACjRPCyx_HUSs!ctoPB<YV0Z-%v`OwU7-0liL*`#Kh5@zB~q_E(FDYl;3^O}_9@
zd!K>*(JI*XWM#r`Zl5T^@lZw5ys)_*{-%MZU^;~}35O>7j2vlE(fxjF#-QOx-WBXa
z&TQ~F;oTEF2bxby`UERkMklh`cer9eLw<scbrrCg8ETpU=;h)I$W~x7J!kA6)pN%H
z5(Xw*K1<lt5D6AZ@e{t5d_UHXM}o9W0?oEJU`Hy-VmT}Ln6u|F>Qz)j#za48@v@x)
z2jMQ5CeTuQJ)JU7x>V`Z)rcDi4B)0M;-IQyC@-jr(EsQ*8dd~lSP1(NPfaBlA>A>6
zjX@D>KW5OF4YA(&4c@&K-%Eq4bNS8*e;lA)MieecJo5g#+7H_{k~~m_m=5k6^^%^e
zIk+9O2fS$eKX|oSu0pydAl{S!x-n1nJ*4g?m{7R~kthHL6k@0iK%(eBqsEnn?+#2K
z1X_P+%Z4t{*!|3U{53}t8cW4R>Q?%jDOI$K1haHNJ#^a5l!}XlRUdUo$;NTJtr)WF
zmzb4Pg_1*aZl~&A#+e=E8MLb@6)-Fcz2TfOuIu1#sUmi65)u_r^V$F~g{NUq$9wY7
ze^SVQzN5g+4X@+`QcRTgmKfq+HJXwZhz60`HrXu18&x0i=5BR%o(`v%ZRusLp}S4{
z@wgp8e+k}VgV8Cr6h0cg01;hrycmirsg5cN%Zc?Ui7~m|<@p#<PUg|rJ?nd%3W~ey
zlvR*S=iR$vb^$g|%rXuz=pLPRW@N2)Z3gx!q-6zhj;5e?3oG6q7jDr(EGS4604Ost
z3cXlxh#@ICZZ;857{XNujoWKuk`I)Gq0UL+zAH}E@Idv2&zW}^H^r84Dxw#_colOr
zsVa#-dg^XBV$HUl0$sZxiLV42lCPoirdY0dR4%)_E3@LX)j&=}C;^{N$^|L=50xYN
zYP<G4qZ_2{R7ah1O_chWKP#((;~K%rQtCk<B3DCMRiR_Ymgz#O!%R-uPHH{w)I}@<
zefd0Hu&M$<^CgB84s3GsmwydUaK{h<Kt?@AV;R9_7gaRnSiU(=VNS8#QkJrNMK|hq
z|C0tdr(@bC4loIAIn&xL<jfns!hOy$BzxFND$$95)snglh>FRmlVcJk6J2`>Q&&Vg
z<E;JmKfSJ)+$^Xlq?p@o#ceO1Q{h*iif5R%jE^<j!x)NJn_?+#m{nP~R`DAV6)g~1
zK?U@(!c~g0tsH|%0yuFBZPN#$BP%KVi#UzqgPMvc!Xnxyz~$HO8BS>0s9L}C;@hdy
z??{LgKmuJH$p@RaIk&rdly-*DCSMWM`!Fh3e|!kwo7)`tm<F*~3&P-`xU0w<n#AA%
z#_ScRm_=id2H;SB3mUEHlc~QDX;NoSQY{OiP7jH4tZL+Aqv(vi7)(&Ik$M&NS7SFW
zd<r+f&Yfj(?q{^3dS@Pmf}kB#qqbu!j_JS?#I1{*s^rvmbs*d4N0-y1wokA?WgY=-
zPicWrQSQZ9G)?oYG>?rUh619AHWB?qVFgqLEVn!v`|CY#8?!wX<C;)X6@d|_1$6?1
zICN4pxGs8AEqO#Xxa<;PaE{?GkX{E`dqFEEDEd=3kHifu6(qtts%s;J<SP|VTCxdl
zt}e-FT7!_vaU)!oNudSkhlXH4A|3QX`_bAE8-Pg~aR4e+oUdMyzpTd<93EF|FQFcy
zlTqL>fSAqwA|A~h_lomrXF}*Kj3Is{faaxORopq;XDVIU2U7xp`G#!av&fcmQfU>r
zh!AfpPM3=j8D-?D(JW|%QRayc3#uqBh1@8uVlXcZl80P-d9_LX;S%<dVHG+#iYVex
z@8zc^@-xO)o<RID@Rxgn*H+<tV-<d@e%&^|+H-iMaOA}O?{B;~accQMdD%El_xQE!
zHgOzVTk!GxG(G>_&^$@a;Vma{@^+Vy{g*|y#q43WJajnhe}aYKb&2Btb;(+CsS>Wr
z@LEZJOPpbRarAV7KH7Aq#WbRLyXDG@oCR$mcKI3oP<AvqFN1^@{JIGKkh0UVq@QDO
zs@Xg@THL|(<3s=a+ejX`a0?Dr6aD?}S!(ok%H53_F>~NJeG!78IqPM#v!LAbWIEiD
zo!&Ady3es*@qs4m4L<cqrRS6EENl29*~!lwhU|Fx!iAm-6C>Lyd;D*RtNus(3m0Yg
zM5)*-pZcDw6)K|t_r-C;FEz!52{|p!yVs?4P4=~l4}}M5k5-(JVU}D>Ully&SJ`Mk
zeebGs!8$AO9U|QPol*s1+@Q(WeoV+ETxR!ALrAmPcZ%oOrf-RpjOEj)EJ?Tt{m=L1
z3@kQ*aV@n34CO-DGn{wU<UP>?9mg_p_#xoaH-)lTCw7V90v4%wogEzaXXb|^_8R?$
zmEt*Ju6-iHu6T)>f>U!f8!82?TBBp5D&2VupmG&=9;gNp><XYTC`%-Pb$}ns(K@ph
zz2%&M=K&lB@JM9z5P1`@BMbUuh2^2=#ivp{dN;S;`2K%>+1=O7JVPOw-R0_;SHzr4
zGxz+k*&MNxMKI|V{e|Z4`qusW3vydM`OLiCs>6Z+Lc|6Hn|s)DD|0KGeQD^2u6yL$
z{t5u!;S>JrGvS`WRWMp4&Y$|EwWrWn*gDR4HTMkO{o=+c@f&rdD}S`$1XqWCD8gJL
zF<?C)Ut(zi0p~r9yfKr-(O2`Y(pu<mx%YY)))T`UXV?f#4k|B*{8^HC#MQ#Y+2-QF
zY4L2ctwf$K|0?9QfV&s1eT@^L7O5(~-n!VG5Ux5+iejE7uL`S~P1f9lZ~WcgZa3^J
z9Q)9_%5#U^o#{hz&&c8fFT2N(bgetP^2x`@&^dt(zB2w*(C7!R*p23xkL?cK`h(L*
z{{Qs<;;*%?7kaQc0#c!CiQU4_-EM_@M($3*%HfsOW3FY@BDgo5kRyVXF0VG^L03cC
zvd&iyeuS4Oy~=A%Xg0Oe#_d&P<<E)!MYnw(6lZ=o+$&2^JYwGknQzOjQLzzr<Q-Q8
z&{S>igj{q%L)>?o#V0|9KbBeF9|Jdg?jc}ByTAS)rubxC9((|2w#$LF^Deec^y<ay
z1uVHT3p-xK>t^PbF~6svo$zl7vBzB;4EKwC{WoEV-fT1v8pp)qgFE9dKxesM9&hb-
zcdla-$&ZWG7SjPvlJ;!@SAk=p0J5vL4!#%CLP#x-LTXr|pMl^uN`KF*pPL^kIHYjF
z1*WpEF|bH6Ea0s#k<?adG=X~|CuWUnnYds(i|1O451Pr?k%fDdcbcF7{yU%;z1`V4
zRL3cVg{VILnR}fzT=+Yz?zRAj<uJ{Xp++GIbz<^rOQX0VV;3_sz0vi!{6;gXi-&;L
z4s;Q}|I~rxB_!bYmKv=+&f<<Fua9TD=8rcSY>Tz(XCs`r8x0iOSx5(>6|^!^rt&K1
zcNqC4sa~-!wbUy^*IC^yv1|B>5<4r}q8*Byd<=N)I5seDv{nGzS+%!(N!Fpnt+}YE
zPbS)LKJxdu18(Li^SJ}=k-MI2xD<T(VjJM=ZcBNA?O}d#PW(UDk~kP{&`TFkl*ya(
zsB3N0n_g(4={$&yH34cJ1QzN7c1dObD!=63w(2wrci@WdQ8JT9#jCCqX^Crj*cIvv
zV3H3=QI-ZU=1Sge;CE~_0t^N|PStX&fc*Q%FSt(bI$T2@me*a0_f#JMXof`*E~mPB
z<gSwDWEPM(bXSsEF2(h{(JZys-5c5LfQr8^x;qo+@X5tQNk%Ovb*ye}iXC|ermZIK
z$EsY|QD_uscr<*~T|~R_hgT1N(~r0GQbT^Xp5_Bq6!AC_-WFC8b68wbQ(%6kp5VL@
z=2aLyGzPpz;b1IkCn-$8d$1#mmw1CgkUPB5S6<*P=jE^=ozgj+H1xm#ejK(xjR%2u
zQ86y#HdIOVLF{ydUg^O<{hkV|lJVqCqjNyb=<28cmS!W+A1RV=quHJ(YaLwijBE)s
zDBw|wjd0<m@wyN;-TAs<42zc$yllwibJ@vy2y2hya*zAP--IK|w&)Wxt^A^i%JtyR
z+D3#=&{kUrrOeNxA3(&U@c?Ws&;tZ%w3lV#M>zsD$gHEUqUv$+Lesf2bhK$<lZVeh
z%|5}tjz)=Zs1BgJXt*3;JXVGz!_C*<Qx57bEjL8QUkGI8R``o!Jg=gV5c~f0yXNG9
zWdCSkk8>(f+$Xml*_q}PyjNt**X%SR4IvW?_w2EMC|s`=K(>8v?~;A+Z8xsD$=GhO
z^$1#l`|Y}U#a*<L9DF%x1L`OCFrWzpFcjn9rdYXtFOIwgJ|v%Uaknn9MR%`zUfbKW
zu`_C?O1>5%tb+StWcSLJQ<Ym=5Emn%kuLT=j%dVdk|GfRlKaf9fBa+2ii^vgh;G?h
zHggE4?x(XBxX@N7!xL?(WkE^*Mj3~0CRV6hiZiZs3M}XzmajT0rpa?;CQQv4zzMsF
zKgRp9R9{Z<*kmn@b!ZQk>{~33h3gKWW&K3U7HZROXHU2}Qixtpug98T3p#KmxgUA}
zXcQ<|ykkzM5yF2dk?Vw(pAy%GKxL9UqpWN?k$zXj9E#$ZjEjCPvmEwI^A(iOHi8j*
z48!^^h($o5A>mnbE@%m;mLa@dLHD^7+REBsjy^0JsatkFj<r(|Vd&NhW&=IKK8OB>
zM?-yzinV_M<{cuf!$<-~eAiM%p$)PU3+qG7dT-nZK=A!FB)n#RV09l`^Fmm29QYAd
zh6lo1HLv$!s_|pZD?a)!sPa3l?#Q;_EmRq7`qAInvUZRk{!HQQzd8tBSUU*p3;wM$
z`6=~n|2yy47U17E`S#B|$fJ>^!;dfLk3J4dhqtJSf0`-7`{0^!>j#*Sr&JH~{OIA$
zpXgV}+allnG|*^1dcay8GxzAffAxdK<DDNL>)5sbWhlUD^elS)-Phhca0*;ny!lo|
z>51KW3PB5kQE&ahg7;tju(!PO`OXdb^iktFKgnGCVLESgGi?Zx3O<CImtd_<dcj0Q
z7sAX4O=|W98(<TQ^5Q6Dq1J`Y^M|k_D_bU$VxZ!7$uRvW!xq@as)NlDx-beaNuFaZ
zL+2s3aZhL?&<KYUSkviAeU+g-Eg4~rCtY=^FqE)XB*=6)NB2uF+QlfR=?;JJ?oO=m
z#>(4?_?=g^LF1awU$e1Cf@^azEBIb!L)1P1-@1~BF|_iS@SP#7*DqA0eW4`NHW4j4
zWy8s@tpK{CL*-PAh-w(?(4-4Dws>kDj8{RIj&ear$-$0S5SQ#_I4-DN1=%C1W$J(!
zm?@Qz*-FZe0TktKZ~kpBZNnsDFB|iN9aau^I7Y=#ER~S)^Vs7fy&m$-6qZT`WR@Cl
zB8zy=*v>>z4fgrTvqU~pG3cYL$opKD9$RKfZN}hS__GEH&HxF@+&LFQO-PN?F=F<g
zAy6tJmHgWx#--!Bl`&ogib$ief<|(91Wa3L$OfOJ)!KG)<BMNaa((b{ENoU&r7f<O
z>NAv%3ewfI{dyPcoi#XvK2d^^4n>+;#m0KQO9E&21CpiijmdaUylos_7~}+eTWO^F
z1Aqsi3BY{f-dwgAOT|2uwWCk+p*V`Px$BVQn``J)gzFVCRx~GyW-RGn8hN{oRB(;(
z{<N?S$=5-7Rfx%EN=2#XC?KQjc-H2cAcc#>RYID$y9wN@=Hvz3(xmG)2>culK{d$D
zxG2OtI!9rZV5TGJj=bgQgu&5i3@&`x$mJ1e155FBRbrALo{E)Y((IyR<(EG9cBGwK
zaN{TnOI&q#RJ?VB0Yvj5SQB317Jn~Y>g4CovV^d*FeMmjl3^#x*0sXe1si$Wx$7=J
z6o8wMBnE|w*&(LV>-n@(^r8MUNhlNA$<#UtB7mHu_B60_q||0QN=edn07O122b_49
zki}-chRNR~kEi&TWcu6EyodfS{ro%CJ;q5xl;&N+b~BV}=`if6G3-p+)Arc1+nh0W
zah+^~!?h@0orEI=!qG5xe9T&ABNTmkLL1bI{19&<XVMA2++(-Mv0?)IG!Wquy-00*
zvX3HLDF(T{j}nEY=K+FcX@*;Aex?wMvhbxCkeY3V&B{_GzXdwk<Jc}oZb`$nZrmqT
zV|=+>PkXUb*fH_fKKOIc{@RQb4ls8a(o$G*H0&I4>5fh(Nc(e4+25|65`Sn1Y9*4I
zq!QXP<aYw{w%Fr-jDvbpA>i{7-L&U{)J<p&BdHu(qPL!*^_604!ZQVO$+Rk!NmM0t
zlkHN(WJbjn<k(2?wI1&-Sam`J;40o1Ea0XbeA+oMNYxp$!IIjRsPH1$Z(_m*<Z4%U
zp%VhwRw3Cc+--W}_!YU`nrCvvm>^C@Oa=f;?X~5S5ja$nQRXYYktpFkbe*y{>O}P$
zpZne{2fKmk283fJSJ)7)+uVzxUh9a;;Z0m&E9fp#=rdHpS+PjzAoPX;Ljbh$QBRzM
z@1{T-Z>J7L7nTMd^id!RVEY<p);&$HS^}L^Ms*NrGUNaJ+jjvKLo5BfJG9HP_<YYG
zTt(o_i?~}(E2$`CigDcC@9dJ;C6qI%&APq^kr>cWB8rJqWhi|Yf0(H_suxSqCN0K7
zOXG0oieX03Fz}w7CYG3YU#nFv#gc$Zh{Jhm63rLh4~{~=_$3Hefy?9fGtHevHafJ1
z!5rPr&`UORE_&KX(<vt<dSEhvc09$}iGW*=F6{!u5WC66*ra9BxKg~ks3k3e1Dki}
z<31e75z_+hO+`IR3I~bK1?IOL+HrJM2zOEa#v&c#DKrwT;7T=VSq*x9ESPMNB0VOp
z2?lwq0xtze5OFc)`?)@V(IO7D9e@%vPw5BIm0Dg)(K_Y+cDbAS1kV}FLGiB^uCOxq
zeZRCG-=_G&7h|&cS*Ak+tORNixn#7}I>~^uxqnyHfens-`}ZFNUxO<G9BnPk1D!F3
zQb65nGNo9HQcIHbeXj1xy=+oN=QcSn+#wpv!G54$?MJI+N#wZo#|Fq@krLOq)nW+#
zr#q#vG(>pN({88q18huyvKLErsGJ>4G#tgxBY&0R*1=5>^-K+V;zaz@z11PO-y_m0
z(3N*1qKof`XaG(=@Gi$KhhI#;#C;r;9PvjaPHabnw_O_mcm(jK8x)1Mx2X9tW15p|
z6d}UZA_Y1sHp0M=12ct>Nj!k_hOr2F!;n=+4hzDS-bs3F8?tu(`q{WLXxVLO3(CNR
zJ!CSb&S2Qi;oQM55h!_B0E4<qQQVMe#4g58Vrt~Y!gNe2oUyE!PVAH`7HqexWlBe!
zmheSKADgB%A7InaT9_yZj^$4qw9Gg)1)<s^{F)WCbj9N_$sfMf=DIm6ts>%Pw5_a7
zxW)jU5p+Y4#%;5sBmm)|qUp*miAaj849Tc<5;&&o-aQj;^^m(%s6xmUaP5^U(@j%)
z6($)HUYMt~+O-Ng4Y38(PB>1EVvJUtl!|<jNmNyZ-uSz30J!I{r-PEJ^GN}rq~4Sv
zMD>#tE5HoqcCKHME%Zp<XGIig;Zo6|YV)!r#~Kh_Q`9HSblf0|)kR)wpP%s14Mi7>
z7{jy^)@%y-0^$PrQp7z|oX4)9=dfuyww-d(CAlBqtf<m{Yzhra&#57zELd{rIYc^?
zd|VNH!c)2L$ilLL&QTdU#B8Oc`Z?82328$tJf1qlAWsc<h%sC=;wRf#j-pR9k?ug1
zwIA=QK+l1zT#t?bTe+mLhekY~w$P!=zq)`;$=)y+34UP6ps%O+?STbH{*P<!nXs>t
z%y#Yy3Vp)eCCTxgZRB|^N=7{Yz5|b)bsK!}RYu(k`5zTTk}AS3UV;U{<YC!SxbCKp
zRr<o?#xA)$Y<PXp@|+lGb-MkB+;Dt(Xvg91v(|iJdcGB$t9)BLJrq1WHO<O(F<r}K
z<u*B85AF-TOkOK39AYD~82n*mup0C{QJHMXaJ6-ueMo+py~eMJEl*UE_0C|qLUOIk
zgO$<ZqpdtlZ8vXYPFXxU;Xu@N>o324#kS^1@u-`9qG}DjDjqC8Ul(16PoD4Dc=*Cf
z|NG>5$aPZE1{?0J?BctE{_8gVY~e$6<5}6qf)?p-8I$i1!^`5Mvg7^p{SyHM!UX=J
zQvVQAFUn_tZ)<6PXguh*e(5vMXCE5QzDQ(tP^N1=2QgKiCda9sd`-?Z5JX=$ZFI<9
z@*(<%WK1~4M;V{YwlL;!$T~>zITATBKu6ue6y+-u0d`k}6a@OiJh$1o#vxw3dEf6}
zu`dH-LKZyK^AR6&k^F}vW}MGo<*&fp_Ku=Bx=X_}68vVqxtt9>C~O4m5nu$@PY3Qe
zHT=X6_s&Ot^axPgCC?)*wM+Cjx}!xHQ1ZLFvFHU+{s0Xc`RHae)^157lfiT7gprC`
zx9|uGO_Gt=>5dM0?OkvVyvpGSX-skM9mRyAu0Iwr=mZ#a9?HH*Q+yQi_E-LWTh~1B
zDj44xBfaR((4niY^#b{Ca!=vfy`_CkfC_sinICnxoFzBqYNib?ug#|Z($G~V@XEZg
zyO{^`-Q77X+po8vPXt$a;0;R{$tMA6tT#w<IGjAI-wV6U5pjAxea+S2@30ykc_zDV
zS92UJlvH*Vjx=fESyx`;p9mVOziKD{Og6%U56}}KeWv%n!{PFa$uB*@!T)xg;I)WD
z*D51`jENJ$(-GCGtl(mA2J*YtjKkc|i$8DNjBIls04tZ)TxZyXBJ~WjzJe`(@v(VY
z(t1Bn-m%BN=|-3oY%~?mTZU|m9DJ1S24zL(0td_qB@p70TWPY>qS0cda}`iXu?(sd
z-V|~dt0rCmgpRIVKp6T$xPrZNoQDZ6^vHtg4_a?f(DZX+(cLbNBa{Q9hKpegqS^;g
zLEsZR)5<&rA#mCfAC%FxtUXKz7qybc4n7JLh-H>6H}0L{Fpf<?tz2#^LDmKxYrftc
zxvaVXPnlc$I+YO@We#y^3H{Frc^Nr9yMbe^(ivFnV1ws3ToE~zI*|$M9+#?*L!k?^
z&ETUfZ(MJUMjzfS;6VYor%Zk!@ij2nH8%HZ#F*w7gRey)^VB9ege#(Z*da#6=_b4f
zK*t^+C}C-gO1Tr_XZBq)&KRV-xNU-Ofspxgm5VCg);tKtnwRULZcQW;4M`w2#=0Ee
zn7T{JgZ^Z0eQgRxrfO*d7w3W^=2Z#V_L3NJom4|^Cl`Sz0kMm?e)+rwxn;|P-|sMn
zz!#<Kr5QA(i6U+68)FL2xmjqN;*339kx(!fuQRJ|?io7QjPR>_a0m5Uh#g3LHi$ek
zF3ZJJuy+uab%xC0hH@#y8PX`gBw!Wyp@ilHQ`71`sFr1FUle|EVOQefdjMwDRD}OB
zx6T5MMlUDw;w+7$J$(XhiOqu$ZioLl(r?enNO63W-L8vj!l}OJMC&RhM8o9kf+a6C
zV-BBOlo0l!Cc$??Tm;S^#=TGQvTRcrY(H9Tc7C^D92KgmiQ~|+?#m!HqTp=8gHS-j
zAUU3IY=gB%-9kC#H611bQJW^T4L~qo$LT|}jwk^V5r9a+uW>EYP~)QJi@C~_IC57K
zPPr%#NpC$XQ<`^%#IE?!rR+=2i5A-2vY5p4$f2T|@b|EH!0b2kOy}iL3RvVad{^Z<
zVg<8dv@drGOWTVoJ~%8%Dckh18r@!bX%&j)mA%p*svqVvvH+S1<{kxITt{$;HZk2g
z^+g@62!tZ9dZ>O__3xEl<6b~}=iqwj<e<XM0WYH^ScigAqr1AXYGoFr^7&s`ms6Di
zgbB2P`am*@Ah>9zVx+mB@L^aRhl|Hi-*B68)bA8fkIEA+yMhU?>O#*yP?z}Yq-Z<<
zRSRlAuQ%Ie-CdH$3wbMXRxCPvxROW7qYCc}uS)G;38lQa@3h380F4Em<N;Y2wW3<j
ztDyov;s@5m>!&4Eaq=l#iH5Qk;%23CBGjsti#-S~$QzG*3={diE`&IvpuO%MB22$g
zK=t2>czr(VAR@|p8eMPHM_|%Pux9d;u_c~dle$IHWA~z_k2IarsI(}#yjtbMg>j??
zCZ^L%cK$&i5gaa`*)L~WWq;H1szcET-7&Nf!Tp!vnp3@Zuk38R7yiD~Mc86%D^<gF
znus0wIQNov1vSU2O65<t-UWHkJRI;^E>+;sfFsO0dnN0SKyN5u1{-4Wm2L}T*p3A1
zImUe(V-SoWwpg*1mU03slQF??2b~<LJ3$<W<EEoIeAY1qvbbsq&|s*V^bmQORjf@R
z8p#0`CS$Yk@y3iEqT-abCLOu)kN*g$iw@Vo$X7zPd1REEccKv%r1!tF)FsSeML~-U
z99H4O7`Z?odl{C@5huoE7f<DXW!Ux-><owP0wpG^@Km~PW0HAkZRG8i*Gat(7Pyi7
zqTD)>nv*MLN2`fgF$Ue7w9r!^Wip`jFz20hYc1-lgBB|ge1a*fcp)kQ3+v}wo2M{|
z_`sK8*zgn6+>h-zJG6#rpI*};|8H3DuZ5Tx{49&wpEiBC{n*cx{{G1wi`p;Wv8esA
z&uw%fkw@*n@VWgL&JmCP+8yVJpJu&3KFC@7XCCDCPwXdtWcu)9%iS&t0)F35xjuYh
z4LkqcWFD>$AHFkrR<PV(`^ixsU>85BwM7-4L^KOORPo|U3V(a^2`IpwKdhl);9*!k
zV7eG_;<X8R3Jc3$I;AM~+Pl^`1D;`OzV>tH-w0gX`FV2=|D#`j_P>AqyKzVFH;7Sq
zB+}gSaEA;r<AznhX0!*pVMn+O=3`B3|9J-*#EuCmCPzh)oa-bimSq(-We0QfMeL#?
z!h0vMG6@n4!)x3e6e=}sbD%PDy_mjQgx)5brNyh<<iAVzi)}>El*$1)Q{MtF;u%7h
z3AWh*8udpY(~cIUA;eaZac;5RUpdyT3Hrq?Im>Pur#t(^sxgnbdt<pB!nl1*NxAc^
zqs3BvmeZeTb8`fG6om{UnM7w~xx+eR&_1B*2~lb?3B=H2XuS*^!33M-c_M2_Vc#Zo
z6N<QQ%Fhz$!OS>E77EnC0c4@r3uPTr6UAwk#!3_z3x2j73_4gmRM}6r6Mawcj<V{A
z$5bd@_rl)75FvN5u<d9WoM4w9v?6S)ZK{Yfo=hDzZlm7{4vTiiq)S)@Vq`?0bPn!m
z@{+51Cy8y^8L??yXgS*0B-Z2WlJUH*ampR!xI%PP)UoKqa<F(vdRsJzW5G-3ut3K$
z9?NZjTmRNWA04w<F|E3V7=%p~81C+Xo2e@tM7;>CR|Ur|AQRk8)hsW89bT-6Z>##|
z>pae2*h{uE3PAQSmhr-+TMf}gM~Js>00<YKD#m8BkYo`FUJo9lkAvSy0bn4MAWkDJ
z!^Q#1$SYWwC$H5)oleHHNNnOCfA$?dvh@qG?IZ`Kxt(j{SHLp{+k}mC2Ya$ryW=5W
zw{wt}6YHo8`X&JO^;J0TwxDSZw9}DkFK}LJUhbNdnOGj%22Qj$(kV5yV8MC7kJi8n
zcd8wcstR4M2{9Ua-Mi`NG#p;5(dKPbx$&Dv0TF1lziyKY(J?BvM|W)>gJmc-i9(ge
ze*od>gtfz+vXi~o0~u>=qBlF7CgEZ_UD_`mW|*s@(l)s{=4{iE;HHP7*%;|5o-^Y6
zS@LY;Z2Sy~SM5v<{vAl0ohQl!ygWiCYkdOuB3_K69tO3Z?I16WT#Hro8_cJAz8EJa
z?KS_j`))R*y6tLnkgOt#fNLYzLZ<j!CjfF4z>pW;OZw+KgKvt2FzZm!7ZPB>L*pSP
z=~K4oV(qJBjPK&b>oWa#CzghMXdf$H61v6t$<E+x#VNEE(p*K<vu52-pbjEFkZxv<
z@}w2V25{`8Ufhvo>?wFD+6_Zqk%y!o<-5qwR-&*#O)tJJ(6dC2W7PSkZ{L1pO2JG9
zKo-{1pk>O#qw01v33OjFLE|3wB;gKJ);Z>))}BvHl-gaif#M;-vEnUi5VmHG4%MX{
zNX8cs$$@Nvkt&!sVJO5C0Ew7)*oW~&dL1g9NU9K;qtlS_S%~8_-|6km-9C6&0hj}S
z1`ghiJ09E3;6S3zGB>4S<}eDSy#gj3#nM2qa{@I)4}jGGcwi$yfHVVix26dhBHm--
zOTD!D1-<<o<*Gy}E3+*xh&`sA;+l!lifxx!59@&K^oFfteE0ecyK3ZMd!jmA-)@9B
z7}T74v1uSb0D{0mtcYD=UWqW97X_2sRjBnz=nEcOa+3sRSm+-W*ujRFJb*NIQI}`X
zM1e{vpgKHi<XVr9NQS<|2)tb}m`F1FCy*D~Y}j7H%%<?Fu&s~S*r$${1fUH7Fd+95
zY4*pES8hW;s<;ks@0>Rj!Mfo&NBC(nDsrlqXc~&$t>)Tt1r2?cw?kkeqmFWhly+2*
z6!yUbCTdsBGCJ=h3}YymFS<JrKvOC9(rS;t(ysA8oq9(SIo=Vvns8AmF!!@zZ~<j1
zMA*1GR~<^5fch?@`&drp(&h}DnW;%_zpacpA=mp1KtDy4Z4q0Iyjwx9)R$q3f^viS
zeL%HM_&lc(ae>Lh2Fy~eWg;e!d{0PNT=1v#E6;6^LrBTawRtwv;EIes5bmrX`nat&
z;1=v&aj3`>)kAIqHxovkKq_klz}mKGKPL@<cEU`$Q+*g^h^r#0rx8sNil?GR3VR6Q
z5TzJL&yRpmg_I%mZ!l$SW;{dVpm)#I-hmxr)zM{aPzeET!o^`{-2sZLME$dsoE6Wh
zO?=gu4JfUMZuk8Ra|br5k^Y1lP`fR6072Jiw(F(i(PUvzs(}gtAV4$Fpvp}XeHKci
zJfNj&=;z`YfnOC}%HR1Gs<YA#PmlgsM;qFM4e5RKl7N(ZP#tzq1MC5WqEj2t{Zdpa
zMai|f5&7*TD`8Fat8PAqi>PxC+xMytTr9kAA;N$yEc3QHVd@tWWP%fqn!d&=0TMlM
zZoaQ6<DP&}_senAw*XL8EynOwgIF?i#Z@rs;ya?LO4R%?9%J-YX9eKB6L|%9BP!~k
zHl^-qq;qPddnMbO(e1&whkgZpI`uf{Cl)1bxDuUmw5({yq@WycKX+{1ph}<;7c4dB
zA~hiz0=64^I|y{NH5C5aj=<T&%+T~9!_ZhWg>$g6EWv1`q!8{!Bqi!8iZDs7adCw=
z(bf&Yfq-KkDDt48rc{NV#0la9o+j}D_ywoaTm1MRd`np>gbAad;`(4g!xL%_;St=`
z93;L9<~2Ny+vc?l#Bg#hGB2W`N+5KJR_qU@4Y$q3K<08Mb(LEn!X|uoMJ!Zvs)8t|
z+O9sY<)Bs$``|bbqM2$4eUB?j)zE!o_lI%8IH6QRO-0}w?E<?at5LgBJX=knnqg+t
zCrfqWBNeP2a&5=MobC$a3tU<D)WAYgQ4CQ;=9nHP8-z>RkL3#zdvG{-$|7edLhG2U
z$W#NhB8CFPz*@d_-(PN@?{a~yM@arAGp5CdF0+rg*b;WR-+sa<ru#bk4?X9ePY5+I
znEO2&TXY|`m%Dnp=iNXznuT4QpRcjPgbZj4dV$VsrH|9YrSoTqwakj|J0OP6z_xv8
z<GeL+Sv>2WG46K}eCT2qmYaM0tL`%E0;f;@4U{cKuF~Udf6&()eI+ObXABjy*EwVG
z3Ag)?jq$;0J4t9wM>f!@LtF%v%lu>*HtDv}V7!=_znnD7-{gJAD#66bm)@rhz1J8q
zX58Im#vPn*Imy0J`}`#qd(q~*N9}$jeNEX#j;^zVoHN|d5aWBcnpC?EFYB|eXzKk<
z;=^mV&X2oYf+1_i?<&j~yX6uQUG9r~2pf%IncH#LSzi73i#5ILdoLQR&vd@lyzW28
zk{@r)v#>%6az*U#TAdc*{g>IVir|ro#n;aq7;M<fLw%MzoIc?$ELVy){R7{hp1fES
z#m~y1#)9`r9xS8-)ejq28(%$}y)MN>abad4@{(|o|1<CI7c&O-I76<hP3}A#V+IU`
zqLn09n#+o7kNG7-ICujz6a5<2mv|@{);QjSH}bqZw7l$0_jVZSzc}Ks^Cq~(1O&IF
zewakuwhRYeP+pkKti9dA4pDsq40_FU0>%WHBM$-(OVWV_55^II<c@O^kB`I4cN>`w
z{EfH%Y6{*FyJ63m{Ey&PHiH)K-n#Rv`=)n1XTZ!gX%C#$Ap^$ndGv`EB)|HuWd>ti
zy_tW693z+A`mR|rR3FeESj+>^J_GfjIC!}BLi4o#2$9#=V&X;UxLtjZy)3FblHZXO
zn;p4;Zt;PC5MrlO0fp&;><}KgU;Ga+x?QDT)dwJ~d<eQgazZp+vgbmrfP_0Zgf5?P
z>jT>;8J0)jpn7kkJYoZ-HWu>FCyS!uaEP11c8K_mX7ZAR=<`9?^V*H>6MU1l^VY{c
zaoR}V;n|m56&@Zjkew2>E=l{ETfY}+|MqAX89|6~3LVAKPD|DG5qEnQzfo+>W~KM7
zuIR9^F7zBFqtf2_Ng{#cruYnN;S{$ZO@2r`Lq85}bUG69&JU<3d{c8^Sn!Bje{boS
z{0Cv}T(`0ZxMq6e705R?zSOF_SL}V!ZcFDQaVh{IYYaeD7%6LS!CPwKK`0TE>IqQ~
zQ#F^SpcGv&AFsI%>;wQ8&)xg7`wh453U{~5+8>I5?EnB4RIu2_sh$`x>L}L{hK}3u
zF13!jZDhAG;#PZSAR&#r{g7o0Sc3E0u1jXfb6U3JdVz|YggB8(QcSfxQ==z}uZN_+
zZcUqIB<<hKW+x-#iEr_v@-JM0oupPTyQg}E++DxIml=!$pkh?qJ+69#bVktw=nNm6
z;w7l9;Sk_W!iiNYonuy;fSm-aH~3N3Fe$ER`~-heDnI|J4MWFVRksIJaBWEF6D~W5
zx|gfl$$hSk-}z8IL0Dc~lFJ1=x-pd6B?*aVNyGM5;l5_MegM03|2g1&wO1bwFG3Vu
z6tLTf99-v)3lnsfA8%${t=#ynNY}cG8}v2#-BbTpsUk9s#0^&*Y2yJ(Zx3XDb@#M^
z8{-l+-$$$RU=!PY;bwVpQAK)DxeXWQrlNWVQ`Byl60@55%m1Jb96&oF11fMes-gX=
ziz*hgUzUK0i6G{BTzy$^6=TQC;U(9K&$`||x6l@FG#t3lHWh4S#xxyq0VEMza_zdC
z`I520oZ`DNnQ%woZxY~6^pT;4yR(Tof(=>iB#K5HnXD!90MJ#pcq!cHMtuPedE^#y
zB~hcQs7~FHnMULj0dpmoBG|WO%Y-0zd>egygZXZHcQP_DIAjm00vEOyx@9#IS7RON
z9pZV^rj)9?7_akcZ%V|`bYeDyC#XI!7D+_}9F7V=k$V`yIe&cK6}KpT;R0+5_ONrV
zn%M-c`UKnMQUo_f-AsHc+~Y1Jcu+U>$M>z~)xA;B<&X^wy>{XUukolQh-qoU2L@Ym
zrEfBZi>oGX07C#uSKl)&m6x)y-G+@V1ktAV;((DJ9PQ05;T$jz)UTiiLE+$_<izq-
z{DBN7M&P}IYL3@(bvOS7m`C8jhfw_h6v1BcC|hj7!~vyWtE@KQmLrEH+5s9Q`kk}%
zH3o(Df7yvB78)x*F7}Lk@&9G)ZQ$Fu&U4QhXrzoCB}<H8?il4&XNDvC2x4TBV!Vi&
zq?qB5Is~aNMsZPXHx?P%VOhuVN80-8_HO134#)#wBvB0G!d^E8VOWJ!)wLAGm&x{S
zL<)9bMe)~7T;02S8_8BuI?X1w;&zp6?(IH9#Yvi`{VipaAPE99XU?3D|NFep+o=y-
zuQvfwcQyB9*KgDZ8<xHcTpq*e0Kyg_K4t1+3Lzo%pF0J%CU9+GIGvWXyEWBiMOEjb
z`#SXv5i_p+#n!z|Pnu!q2nBS(g1XBg1vP6cK%KCaFs^v(ljZ{2p&f0oL4$dSjz)`X
zmpke`nz#^+NwaQJev#w$+s)ywoNsuS1+{TC9#bc`rlYHY3se({?BF7Q*sEKYQJu?9
z#Sl!fHFnf%;DTT-;A2ZT@B&q`92es5kge#Ai9)nq*&+_e7@016>!sb)UqV)d?yKMW
znv4#L{Yw*!DS_P!Qcw5sF?3|4-XYmj3mpWYV1s*ppGOYs1FD9E-~H*LQ{fOsn7#S9
zXYUgQh={utEN0JRHH*!bGSG4e<d7PGvU`w2{DZ97^#>iAX?3{%z83U%;LU-QhtmTV
z;1{uw^H-sbbXQJo4`HQEhivTKq{99L$wYJPtZVGU^xNXmgpB=i1Zq8Or#Xv(_Gab>
zr8aIZaeoXa)2>IGD+uj0FOfB6$B;L3M^Agu1+RzWEJQ@UY&3PRYGZ<hIR(@us4<5(
zDXLMGwHk7<2`~u?R_Q^<wYy$BIJ7DZ&izan{C0cf%L{N7RW-YkfBRo5kA`AoH_D?q
zKP`_2z8aNB18{vUc>BhK*YW4S;&osa@#>{RKY5m<K3Rw~#wWiGU)}y+tDn5#T=C>n
ztIiep!SP6A{DHGWzgI?SH1f7Hzq5=YYcu0h|8_pI=S|%=zw_{_Kkp}3waUZE8|eAu
zXjC2TZO7i4Tdj)r>t19y{Nw5VU-#Y-8oyCSl{UQ4PwS&Svg(0RoBO%rFv19{hvQ~n
zE4`)HKZWm4{L~TxTNeBW&4zFPs{a&eS!%gbN%4tlB~vA<wooHhqejm0eiGDz;Ylle
z&4mMrn+;U!X@q$IJh1HdW7s(uF@K%pQn!Ww@h=OFH~x{#TYF}((ZC14@#SCpY+$+m
z&IfkS7J28JpMQNbaf`IkbJ{2P(o4KT^J6TOxd%=cB8-@5cIa>F9_KvcVcU{{c@{WW
zzFkMjQl!S;sZ;v6&bug<>g-|!2=x51^wZ=t1<}KDx0$;bE89<3CYm8zNMQFeyeWUR
z5Lioz&}7U+2UXfDHr?XvrF*H>#jlF}lnJ=ZMy|QL^{U3&i87eh&G7x{nIYd63#R3U
z)*<t{_BYZ+xxEA6Vm-P)6nG8<i`}yHd;;4lKq#b9@~WLtoUVC$lxd#M+Lg?H4q_Qu
zyR!c6o(C_0cJU2rVZ(iiUJY0e_Aps+6mU?OV}kFjMLH)Y_s+FCA0$?++)>m7YHTp}
z9I#V6_P`S7n@C?e({N6*1(Tmk2kcuU=FlOv9~-&i1j{=VEb5$2d8XL`yxOjVW_sA-
zJJRz#L}$=DXQ0gDZIg_-D1w93;xMk0;IwVVqY@pm6Uwuba1=Hm4qn)VV&gHq3X*+`
zvcY?G3mf-o#S7PZnZ<^Tt^97?u;jeWHp!v<HJu>GxW=od_2GN5F}0)t3cT(>IR+Xv
zI4KMnND|?H+PRO0rxTXBjt9GRR<==7SMf3lBnNS5b|;so8=6CMS(CF9`tB&nJG_?+
zrG*Ydw|$f?U{jg5>Shro%}z(@Wf^1)K|kCt4>l5Q6&uyYa^dv67{$6(ZNE8yZnA}f
zc!flRR8m53O+aq@*6kx1TV@=Ca9fUo_7TTOh%wItGDFFr7RF;l-8K@ftj#7o0D29C
z9<Dn{4Zg@`9IXeu;6RNUT6a5I<W^^fv2e_-I(VWbGZSqhgBKcWds84nMqn}MciYa;
z*fvc|c3HAnhSDicOcUM-bGmh~%cup$1Gf62xyA!R%lGOq@LejRS*>$k#v=;m3>_7)
z53*j^4~-V%>2#O9VE2Ysm^<GAt#Oa;wAqd~DF$JYlFspq>;vh6$)Nac-a{b)6PKnN
zg%9)W8|=rpElADf{o40z_SxvnmaV60u%x5j);NQ^WxBWos%NrsSIhU&OxoVO7Fy@!
z9ZFk`XzdlPNaQ0lUr%IT=f_AbS*nq(BE=unm49=^_q?>%KIu}&8Sz?)jovmdXdAiL
z<<3^X?Dk3rdN8y>j>|0&G={~<IeimkNN^SA2o@C0u>h0CeQ=zVIoLNVp4KkdT5q<e
z<48ASO^CA1F4m{FQ`!JVM;ozoY2yhS{vBFYK43NV@Q=OHnu|P;`JG~@F~m?!)jolq
z`1whHEC|h;&g75Hl@!>2hL4iZe0@F8DdH@S1j7&|GotXw`v9R06yXzE-36G(^xg)n
zgbo2G2MLS^Wu1Z{StEcf-hd9<P08}1YXnwBp(Po7u&TjNAY4e~Ro9ZX=@zt(;7Clb
zF7YC>%*_kQuqSAnr_wp{kCk`3(qZqQOFh0Dd<O{1aMn9HJ;Hxd0lR)c7iURopQ9IL
ztRJM11x^EgkZrKL)cGm1Bul*3mV*_pskjFjXE{S#jN&yKd4KL8gG2y4slB_0G(nXV
zR$*PLyA5|KIGb*9Ch0X_ei{VLTNep(0nIoY@`SCT%2rftux&jUa3&GRMJJJnIY4Pl
zldNXsZ?qZ^^bFkh0Cu<x5hx|?Y6P((fwLbAQAKjS)TYj1)-XU6tt1GWB;~-prGN9g
zIM;dfYDJO&ivX(eCn3YSn(gCQX0)y6z@Lt1M=d{r96*oSX#7me-kR`R!0dtRVf};y
zZX@{#v<m?lMbk&6t`rFb)K3VPoCtP6dn{ooR)V!GH<i3%T-)*$DPRQeH-fc0XBiw6
zxQXmQMA_4UbqxY6MvvF7bj?#MZ}zM7{MewxzLvKDvx%!>KtLHWK4%vdhDvi7kIV@m
z9<vu!AF%-P9g1iJZDC<9F+;I<6{yk$ydv<R-3&8q5t@lb5_yRgWi7!z`~}IwwWe+x
zw^8!SbEV8*c>r-ZYIGRe_yp?*i#;E+SS>#`!UMPk_s811sog*jOSDKSHiz5Ao^*oC
zV$Db#WFPB6sJ&%~{?X{hEvg}7de_*DOA#_#Fu{DoI?S3(o)Bn{BRbJSDAX}$WYoKE
zMQiy33fe*{ni>wGt$V^jUr{caaz=-KAeMPNA&sabw9bN|nkJ;K6|UDgSYC$T)R36a
zQtFV1CHtt4p(&}LqdiSbx0TiiLI2=B5HSd+grJ_}r(nZJ0QVST2vnLC(zhO3kM7`u
zS7QsfI;kR4XsH8LPKC^gw9PAU#g83i=!8C?rQ41p#7Y^RKz00pd!WM$fRP-dF3sWX
z(4}O?@RGXc2d_CC-37NIjNM@uZDjz7ahtiu^-Fi-+T*1_jPd(u9*TO6<255pb<knO
zH8*gwx0467UBK~1a}0!T$D9mkvX<^roo%*<d<6xi`wW*T7T&`m8l{Fq;^6u?4D@^u
zVMLNRSE`QHrlL7?Y0q!t_H`(tBNU-t@MRkp+si0uqpgXmnGDuQeAp&r<UBaUOSDOd
zH6oJ$OBaN-W1?++KZ}C{;Z6|(&Jc)+<iKEMi{VB^2tZf*kz<n}e3M*G=v2254T0ZQ
zyP9(e9-;<_v(mpl7*Vp(y%pW<h*6=xp=~6>B?~jS5#!ReAebhE>J8F+un-&+TN6A(
zdI=1pR5IKV1bH>+6_`M=-H;4VAZtZN#1>Z@0e|mz_-rDFV2I%%n1mO^OOI-<26un@
z*7pC1j>bn6ch)n!KF>g^1-D!-xeU!=#2j4Z!_f$c3!@1(&0*VfBxkHgVNRG~TGMre
zj)wwMeU4tjdIsYU50Q`pI3kwyVH<yj1Hm1sus{ro$VH1Y#GMoxwY*eiD5Ux3wf|s{
zTgYv^&l|C$Pkr=xtQ$dd9rv(({-gAu6Y^tJpH0m4@6x*_-2R99Dv6=f-S6*)MEEVT
z-}+z0GyfO;Bi@?N|3;(hYJPFz3Tl@vo#huB{aq_8c)etvKh<8J8|vYEN^eh8j?!a-
z4F|<*qHnkTVal^hRL{<(KTJ~t6<y1L(D$bEXYM^l@|xI$HPc!Bs^>gxKWta@T;3Kj
z4C~=yW1i$eIp^oXp+-*2Z#ssXZIk&df_@r(Ytwc~I@mnw^m%T--RBKX@SVKBZ=_!#
zyRgbE@cncTYyTr1&I)q5|M{LjN}frypG|lz@A;SM9H9f4=1$Yzd2gq9zHh!vF|VI(
z_9l+HlkQPEukR7TSf1r4gYv@p6{nW$e{Dd&ceuQ%oa`e1dl-C>U;!U8c1E8k<5-U%
zLCyNC4y<bCKOW>atT2usLwtV!`Ol5)BIEsUCFm$J{`zwH|9}HZ@h=hxitEU8dt_0!
zpTN|8l?4S0f>dS~;%R!0W7SZ29J2w&$-UUcdNg6X57T*@f-MgPV~ka`_70T48*>KG
z2WA{62@i{elLppKuS$=x?a`3_5Akv8ZfKDEPid<NI8qd!Ay=G-c?5xvLe>=h;XFJr
zKAwj@7%!YfJ|`4P*vCe%prgh&ehADg-Jr}}H!PDY;$%IskuZvlU7knJwxg|Yy^d!W
z>-McCg90nh5^sI>k0AoMU(a214=6*d?(Ah-y^qC7Tm2J-(Th9X&V9leMjrU%dSoeq
z#O{vf)bR~S6xa4Fy$pv3^6WPNXrT@+@b6AW`r+@??Za9yve*j;-r*1#`P<L`HoP!)
z{3kKQYuiVT!3qxbw5+4SX!8g^^oahshPyGIT!R-qYMOOx3ox9IcPp&84Kso)XLXsk
zUDp%C-hodeb#0`M5@*E*4so@t(@4sF4IZLf91uQRIp6T^n@BxWX?UPg3-PdS9nC}W
z+511+zWkCvF1srYff+s-X9J+;`hZu58|u<f0E`Ka+XZI^s-_-HyglMs#WM*gjis+T
zU}A@f=T7}lCo{rzBd62h<5_owHiT7pxb=3Er_SrF+B3tD_6;w#G|$%J&vvV+<@ud-
z>Nbe>-qc9}HoZG_kSEN(kr4uTJ>te-U()>@@Zt3ilfo+971e!*$q|SYLHJIVpjK?O
zAZGQZj`to#qotmUCs!$X9>DqYpLxkcOLcS%dv2S}pN#VXCFz`9J*8(Kw)s9W?Clwh
zfsj|XJFuUw_3TQ3WNCbm2cy(YZF-2G<$Qt-)W;`_V`3}c@v=D9e6GG7rn(k6TKsKL
zKp@Tr&Uk)4+YLbVBHTT;AI(Gg3}9TnX9|Q_N=B?si3)r{{=E<A4=WS2@P6TqpesR{
zi>56!n#naNsfMC!tqX`S0&i&>A*h6NMyIK4OjkYfl^2wqPGA6x;tJKBHd4phYqxi3
zP@lK8sKJKEeXv{)ie-7K9(TN~@}hIh%ici>g3q8(Am5K}nx%Z{NIj~ax2w4mWL8H7
zDkzy@0P<*m!$!<v9_FpqvoPM+UVs`nqSriC18PP)MyGK<uE~z*!XR}Y5@R{rBm=9L
z1$MO`71fbL??RQbB)m=QaaP7fG0V3`sJvHqr=Cg6yB+H*zkl-(<H}LT<O=q_5cL9Q
z!l)TqP_W~p4B@iVIvg@^@9gu8*Bu$i`^wTWFJ-xi)jUw%a3l<p-$Vh9J=w+sN%@GK
zJfp|2((YIR_On0KD=$W5_zLa8QOBQOXj+9_^TMg$D#KEu{!uuB9REXD3_%;}k+z(e
znvUQyrk)p<BFX%xiAs~VJPhe^mR*4~)Vhq@Cc1jKZOV|?);&_b71R}iUWiiHNS_(F
zNrOssKy|@kAtwhiN27Bl6@ZHkQ_*)iFM0}q?H<p@8}*NQFNsksbm0xK3=e43xZ8bl
zJIo%28qoTO{gH+oYb<oC0KC$ILRF+5Box7&2{dTkn_<;^QlDUGXmol7h4dQtSiqUS
zj9}02MEwa^9Cq55aqPl=68^!L*#h^S>sZ(z7a^;_KAO5+E2yqE3I7F;19oS*;#CvL
zeIe>p#ii`GS$sb@Glqj*o(5wGrRq&_7mT?}h6@kj+4`qb*LYZ}e-yZS(XRi#E=FR-
z)BJlhig#E^Am)L(g>XPBIKvlk@3(++?_nHLV|6NuanM<?dx_!KdZc~bD>&LqLepJ<
zc{5*5ZfM~4fQDPj%hJ&zRM)78*s5+v{W<cFCsCylff;QWJQhjiasn!J^bp9oKj~>a
z`)QBMyPFbjl)XI5V*_=sic@fB#S6}XPIkRHaY%MP=~;ZZ=|CHgP6Cg~R4hc-mjJ4f
z(oyefTR~_OF~)l&6XI=kuNZ-?1dey34w_wvxU9sFERllRf`<jv#E`Tj9&`?3;!33i
zF>xd6=tsp()}F7u8}XC;Qo{3Ps$mQ*bgmiTOzsR!*>EnkAZEfsf3JXdD#P+0+>H5Z
zLD#LdSS$nLhH2r;OW0@;#+F@j&PlGrsq7V7To=_Mu|Y!d$|@oix{sxge}&0|3@<z*
zZy5*7;0lB=5X9>$;r?{YKQpgPcVLn3f)cxJ@P}|I!nuX{K}2vtCk}H2N0vy+>EKaV
zx2hqK`|+UoFlTT+uGrQ&{(C^c(Tt2)aTN(WaFZg)yAdTtAJI8h7zu*e7I9;sV;DeN
zk^7V}j{KZ41~HE8Zq*CO_R)%T!R8FYWR%c@_c>k-*gcwYp*_mWmw)(<oAFz^{mEe%
zHT<&e#0{8xg}r*C)>>iJsA2TZOFLHK@~Iz0;@#1Yf#sgv_b<U^_!-}T)F+O&Z={Dm
zcNa{A@4R#fBH+=V!`z>VfWHVf9Vv+ye=0|wzEOkj`l<-{`VG|mGuw#2`0IaK`7JWA
z`1TEN<vpvf5+UZU2vOs~zg7?L7tAM4{Qw|2^)o|bU~+u_8T~zA7+CN}AFebh8Fnl}
z%voqPk&1ic1ASxlff18Z=n>$xcqAEtf{hFy@9O@^!9pFI7ehc#{L_D`h3`sO`Mc85
z_&Oi^4D5uWC*yexe|Y0fC2U$Uc)52zlF?QHAAanex5qcQt$z9AuCcYKqv1^yuoDDa
z;_ug=H{%IZWINY^NW|_w17$zv^!CXm<U%%W=q#-~_OUdoc?RwWni^{NI@#E48f+5+
z(4ekqsij<g=`1MFAcQ(ayI>|n-r7zqJ%2v8k&XhXOjb9!Ks<A~5e_JqWv}pO^r_-#
zwy{*E=S1>mmNlVjPfmA#2Zq~_3z51@So{YMy>~<&;l~opVUcw!pQR2*nq~s`ZKQF-
z`>i<MME~K05o5kwNaTWQVh~44>zdOJ0|uUFORc20ek7K)o-{Ly;p?oIgql9VLWPp{
zMctayyVPxn0j)JyY;?(w`3@>)dxI!6Rw+C5NG=o>Crd&yunaGJuu<yTbh8LZ2vgtd
zZ(NcFl^JZaAcbX{UZ$ozq+R09RnEp(^YDape*WPiV70_DbWXno3MS4p?2`3<6B1e8
zrCVLGWXvCh?Yn2nP%oQ`Z(>Bco4Jy|4pQe{Jsc2sW5sOL+I`bT_A@Loee-p%m$2D}
zuasHZ4+=JTiFM8aE$TG;T9)+ve;aW)Wk~iQht0s%0|ag>M1jm^oFPfg=A3;RTbFDs
zA1g8>?+PHs%p%=~sFea+YsUA|Nu77D@PJr=`)LTcJOjcUX!Cr|O?ftr0dr7TRt$c_
z8b#==7(15$UFbBIIyBLhCg;!#AZJV-H&0oy)Y@&>vN83=Ywz*rwE=`Hv<g&QhU_hE
z3yX17Sesnl8RRvvxuQAFAWG>G+GS?-kb_H5UrGJ(go2)aJb|=lUoMImnu5i8%OFa3
zOb9ACshWUR!T1#;hL}MGa|-SY!Yvzn_?k(AmuN)7gV<%!DKG$sYbBPRwJc2<a<Bip
zru33)vL3>@$5G<5E8Ve653kU8`h!cMdH&uMYwEOYM_v##Wb-2<@R~z%bxVgF?wsC+
z$bv6pv(y{OL(hrBRxlnm>{3)aE<X;oQVq)b6oaPh6I~n0gVxAf7It;gATX3wszt4r
zQF{-<f@tKkaBc-9|MIERdM&WVtw%^F^xnM4$7>|TW`gA$cSmAd|Gi%~i!pdEyhK5G
z?$G;muXp4X+LN9}ix1{_@f-9@q$h{qD~R+)I>h95dxDiU-aIw0=iv%d*iVb##<Tjc
zR`_(H;q=?qF;u2V)#flj!BwvK2OZ*7dR5Hn(vGywUvWvE-NOt`?O;zPiq>h`$({v|
zbCWf|VOI*DB}t(s*B`)Ar)ZgCfUt$Wti{aOmfSU~#BKZ5>sLdh_-C5nz8U3U(54)8
zQR~h^4uNx7Ffb#ILCvUXe2KI0UPoup<EyMctH7=yFCVmgK$-LXI)v`y=*WSDiF#IW
z1AWf*iD_!6>$Z?g2Ab+hEI%mJR^(ug(D*n@)-Vfdxo&ck^$K^zn+yAWWyZy52wt3_
zeRke~b+n3X3eUD~SwV~GSR@dD5CwJYaA9$Aqml(Me2+;!shJsDzC84rSd*L&ftLwx
zhCbpNv81MM0M<f;7C{W3D3PU&zcz4-LayMDWa08Qwe033=@p3@@{wNyZ$<P<3YQYQ
z^n(t(s)4h>$FbOg;V?sxY!r)O3f~-u!*m@>iq(-1gC6)Xkqm{<X<aem6xIu}--XE`
zv~j(PJZ9jrA47C0DkSMjk68hJKr%=n10k~*JNlRFTxSq7iPJ}%Ar%HRkuP~s9a==f
zhGwBlZ{(RolN0bCwRH}o)sp875vGp7f(VmOD-k%-Y<;BW+{fXYDN{JNyH$5K$5`2A
zbP#Jc*9v)kh~<1908&9A8LrDin+$k_Bac~_`eHaWoxk{v|3NP$>UcSw56L9N8$2(I
zKx^yMK}w_9uC^dK;R>CLf_Ir!-(G(?%?8lV*-I3+HJJt)%QNP6G_-sS`!JXnXc!%X
z1=wF_V--xEnESx=C};kyQNV$<tEB*;K1CRa*<t2R-b^y=+JE~yWY6D&ys;66K4+Z8
z=-=<zac`o@qRj&?p(5R>4l0ozfF!yV9`tuF3fbr;%BV5Vjo$r@djt$&g20!(QOvk#
za0!1y(G6k}86-*|aYKWlM64~1A4+o?%Og>ZMy1U1c@f<Fj~_xEF@-r*+c~&2n#<<+
zVBKZhWfh-ru`bK%)436K4=;YFpxf`8(}$M1yAky<;r~`*N}F=To>ugH!<2Bd-Yod8
z3K35y8tqlOjl0saK8s$5UQbgh{6N&Ijg^G2SS}$U#(F=Nx``3jx1I<B8W>8tO7q7k
zd%6dq4Zu~0=g<Pax}0g~2Zw@wf_^X;1pTTA=C%q+lqSSZF%3(FQXIE3e5?&ZkT+B%
zh&OQEWkzh9ZLC4RpN{CT7NS>3<54e-8i?Y?NJ893C_*EmItSQ~U=ijtROS1xe{RTm
zs3y=CjzslD+LgA8cGb*4ik^bWIs~Ii23lW4LsYjPRDPmJeI-<QrsZKV>s36-#aQhX
znzqGVUPgMdnstbRTVHP@wZx!mpnv)?N^Y#J2=>AuTUWGXDKuq*Us<xBP~T*~f#-E$
zJV~flzdEu+hPu=c))^aZC#9m;5tp?Z)I_WXjS$Sg6~64P5?~9R9nx0tdjoL~G=JM<
zP{mAc`3%x#rqv##$)-puNy}z+mJuF|XnY0IX@#S4gb^cQARCHry*=}sA!O1Y4;4hX
z$%t|>p*~mfSO6_|-mbfTmuY<tbMWV=R&<4_aP5dr0ZpLKWcCMjV}bT#g#fJ^GD)ie
zZ2MZ%3aNIKDU4k>W_;B`5H3xkt{VAC$&!UtT@1qzN&>s82G$QbxxZGF&Lbad{s*tV
z#~ZTtQF1OpnfnsQU4BwQy=jL@$ec}bW+&8*o;2%uqca}pum?k|AaDe71>};0gp!Q{
zW;}fm4LD`Q9DL@ckv@sYgTG+2UM!Yz%O0VjLkMnRW?>nuNFl--NW$^ab=;^oR<ZG7
zfh&FM!S(%(gm!+u8%Ahd_SNQ@j*0$ZqU{mi&h{*}4mWp+i+UeF>U_G=cj^3J_9vIg
z9SyzxY~|C5m8^NC_5QP;r^AJNCY#Ttf9KV|YF=?359yHkp^N3E>9hLvx}IDNzs*{?
z&y&gg7ws=5$ah;;mb(7pmF!}xhlhXn^=p$bR4NZwT7wn(0^&yHMA@B!Cfd#i<|jBE
zRLgc_P~9zpQRAzVkU|_2JoHvLtN(7Gom<(KI~Z8ypxBF$`&sgB#@C*k+$tUv$#gDy
zsl5B6-`efpJqQZ@D*sRP6?!*6|12##-`B&`+w=7NU$wsA%{6z1$uB3;XP^Jz+ogs6
z<nc|t!_zO2jm^g<2EMznv`6&)q&(XHz}v0nbMvj8;qz|@`@izP@=ox|^H&Qk{lg(-
zHi_0wUUss<9s1T>mi)WMRktaI4~VbP)E`~F#Jiic%tpS`WcCtmZ#|sv%ege)$<CzD
z(%{(SJuUiLah{g>^0+%Wp7O{f&nG5>dlqRUiSy!Rn>A8>lZ13FR_rV6%Y@aE#YZYE
ztc_t>_@c1y7VbaxymuoXsskU-IIGFE0A*M5udF7=Vzawgj|>6vU1S7E|Eh^E5GzN?
zs$ZjS8D<uHgnc#I)qy#?m*|%wd*tZpKmSq@!$gO;wz+%*Ca2!gABU|%gsmg<3}EXe
zJl)<(iulrZhu(0rK-8sGZe823`fe64)-i~bY1WFBqH09Q*7dN@w!7fOY-3$RERO%N
z(Z^fB8XBK)h)FyvDy!F^zh-~y^jf$SLq-hs@;-0Js2Es;b46PJH8J(QTi({wUln@>
zPd+rW@YQgS`{mxhWp9PB94_^8dLK^$O}}_ig}=ZF3}Fw2fTlZH0KojL{w;BRqWLk1
zUmp@_m>=uO3yb!bwI|~*j)bQ+^pmUZ)@zl@E}p8JJLv_%uL)Ss)(1%Gjgk5vZYA;T
zMEo$Re(%t4HS+eE-ro{su+E<Ir|H$fQ=RRLwC<Hn?S<A<y;F-sw?+9-z4Lz)R{H}w
zP|cw~(9g6QsVxqC9)zg(4BtxcYo>k({9-?oe&QI!h|lO(fUgey!>7s;ELu0}FM=W-
z!X?501?PZ$+Ot1tHsQ>ARKV_b$A;@-B=ufHf!J{m-Z*~^zMnMZG{WA!d|Jt)Id+aj
z1aw!p$7}4@#m=mTM(IA)1IMlhqnc%KP=KFEw=(=FrB-EFq@E$MYJ4v|9v+%uoS?<Q
z*AKGL#@V>;4r?LITAgOY<Ggw|ND-+G%&-vD*D~wDj(ZpoV+hYum!zJ661Gd5TRnwx
zr2hQY->yp@^QK+_p-*_J!Q91R5777JaAkz7oo?_$Yjy&N)-3(2-uJIYc#}dBy<5;^
z@CH@VM_Wr?R?B(AEhtpq3I&v(9|g996)u#$yO81b7Nw<A+rjYYLAIx*CZD*~rMUEO
zHNEUaa1`!Ea6fj{2x))s(7OuijyZ@=?}^?fdmL))GPIWYg^M8YdN%Yxji+WHOvVAg
z80534C74Exst)Un88F#iew35r+mk1}sk8d)#S>7K?(Z@dMy6hk&a8S5D|FZQ^O@E_
z-P69>8m2qm_4V*6dq?LL@so)Oz;fk&{&uqohPnvT<kW+_agnr5P>O5Chg%08fc;n&
zrXm!D2Hy-vF4VWr0Ge8RSIvok)a34)^NA78N5xKh<5J<4JM|FQUJA?#^ln4Q?0Ro#
z;*)*>h)chq;63YiZq-Y$5C0}=Mc$KrRxgp0z3nULe;WR13d+|X2~;D)#hTc$@aPei
z{fDisrxUW|;T*7TiXuNfoQ@*?69N(62yFl=ztCzSwEdF!(FpkHnR)0~z2r53h5F#$
zi^I(%f)n0>-$w;9SmMI$7fRugQ_US~s^gd8)!aZWMTS?uE;>qefWdyQ7<JqfetjP<
zB5XL=%Yxf;It4F$paqhRdUjp7UQIkVYaj209e5U|KLFr!x>0&1Qk!p2GCKzJOH;?U
z2N%!)r3RdU56rhIRfK{73?GkV^G>~)9LT}*WP;6ze%O&8h2z{d8ks9!!UeH>4&NDX
zSY%@_3T)n^0fnAQ9EJhNPU=ENUz3I}mg;e7s;(tZ2!A2oa%X}U*=8X5MUIu3t20#d
zj81_S05P!|+9w!n9UB&o8TJtf^c?6KMQO+QB^bK*N)4pN(h{km9*@7k;nCbcFkw4P
zfm7Fh?;j+WV#zt69B_y@bvMkovjh>XovjhIfO{9(<*0c+z^R4Q0GAwv0Xu1jzXqj+
z6@kkUXZ--sYwxcs)sX;3uIO#R?8;*cEmxmu4YyK2+<UN|M$4n&9gbdf29XOMWi8-D
zqT~Pq#(sf(1J(Sn_nZ2nZmQXD<I*%l_Rr!a#I5uTr=VbOPAR38@YJ{l2{mdeR=xZG
z<YovTQSk}NT?vUC(`cLaOCuFmY8f*4@cm8OUKaEv(F-4vY!Ls3$Cc+VC3ruCCbtyS
zPkNG5jla}_i?By+<?}kNnlCPmQC~*YkvOa~VrXPmsJP>>Sm)LiWMx2ejm8^eCG{v)
z(LVaaNAqhE$%k}AL&OeKjug{bWN|>d?Jr!EHsYr6pte_ja9n9hks4^Hr`<0ovtm=K
zUxA$ob$dbCp^3y=mqC?;6**6|_yE)N^_d*}DWEV+!g2{-iu0kt;%a+KHxL9a`VQPR
zwx=1<+fW41l98T%m<Omzog8QWE6A5GDPf%0=9=fsO|ow;!2v{rC1Je9(ZndxLEvfq
zH{QXbb2*S57xHPx?V@kPK_jBl(EEFE&|n|r5=QOS+59r*Va(-An97Mh0>5Q;S+CpL
zNHm#qv3cEW3sn(T%kM4ms%>oyhY=WD;{9qW9z8k3uzm&6RyZ?ahdIfl1vb9eR`_xi
zQ#KZ>Iw7vQxhwi=y$oB>G3Mj{svW{&qvP7MKe{|{Z7X2$*4&Kqsot|rBtE{@b%Qkj
zzpKU<*Gb_s<eAAU>>4RVt`!@}&n$|6=6&(Ywe#LF&=`g~`x4agKR3{LAaN=8qt98Z
zwiW;J7g#fFIR5^Z%K=6dewA4NGtXs6pmWzhXHCKO`K$k&d*4uIug2z~qyB{#Syg7k
z5u|){^!m^B)L3do2p&tV2<1nzY*MeEyfX0PBhXU^Z{5J&e|kN3!HQ9AZwUUSp=*m4
zK$>r%{b7kGV@Cn0A9lIe@}Q;}><93O7agRQ$MQ`q-dxw<wp}dRyo)1^nky-rzw@uo
zu^*$@GD*g?jd94OtN%(iuk#X*Np9vXdS~>~6373L!9<_2ul(r;uy^L2?|$~+onK=2
zi9OCg`M_p_Nqa_a8i7Nl!u#d(eOP1Y9z2Yo_3&uNNVmMRfFI0hs9aWxZKLh;iGJsI
zuwqWCZ5Q{qBYSPeDeK-&(Vl>Dv%XYi8_6<6mEoB4wS~j&Bahksf~l2xer~e=xH;7W
zx|EeuW~b9iTiR}-LnW)Dd|lbZp0gKu+@xI*Y`i=<xOl1dyG5jh_oa7}aC)hdI@a1q
ziccoM$!_N-&M#uCE=mg;$-m5A`Oi1?yA)c+4h1^qX6Pu>D&!TO?d+$JLTXN>c!g^X
zf=#B9`CvzwA7dOFGe~0FKd3uPTISwj`$Wr7LEzw1@e>>IQMb}=GxGs^k+xte@<AX=
z&84I8$AKH?y}btmt=fmj9GgbhHUZGUM+=KkEGt?zhzU~Fkh>}cuOuzpYj(qg67Bkb
zr&7N>>b2?f2_ItHrGraeCdav^=b>#g#vEUEN5-7?^*&eIT8Va;>IQn?@C;XtW9fdR
z(CGt>q+P~aCKu_=#LCueU@YDX(qaWH5^CkSyC?$LU(j5T2ZSQh7c?H&HK)2M@2)T#
zI>TZIG1sQ=0~ocY)p1{#eZ+X>uVbDo>9YVZL$Nk>n>eDkJx)=^Gy&Ne6w*!Nk<2*b
zkq#GXGY;OHMt?2JAa*+Rx7}Jh30@1*lo!1Ubly^t!FQW2H~<Lkjf8LI?FF|B`S&S%
zj=;haTYR;o*^Oi}R$_pQeh^DB<(zJ;Aqb|lUH{D2eI8dCw%xG3RWXCWiWT8K(MvKd
z-PefBNAoe$m!-A<h8q~*bk?nO!*X=9ONkq!aJaV=%Woo}p7ZO(1z|zh$>^a-e}}*<
zyMUHrT=wT^6;+1{jQ3JNMb1W_rm^ZM0f5k}x}f^ypWI{&Ahlc1D4vB7XgJvdF(}fJ
zhjn|203aLMd>Uf&!&V-Y6=*CDa|$)@tXPhoBZw<l3=tYsAko{$p*pJ&o}UO<s)>q$
zFd$FNaUgOC!l_t0C_c{HMZRY0E}dFRyBmpQD5PZBMZPGkH6nXV&otV%Q32oOIUHYa
zl}`hq9C}YWEBDXY2Ltwe0+%V^0F49pGRF2IP@`-VR!&bs>2Aw<YAsR$wz-29{iqG$
zl%8X_b07?UbWSf*EsY3Q8g!I7`Zj2=IS)S(6we}Jb6}hoOYzF3C`x3_^roxJEVVXk
zf*`_cL#aZsGXT>lwfJGOaS}y^+QTAW(l3SQy=1KN2V%RPSChSj^p-Zg`vQm<A_3O_
z@*zXcOt_qR45Y(zLuUl3-ibtxivS$Pm$A;^sr|$yx((YF@H_`Tw_s8jSbbBdLp^SG
zSwyIKT>wu|W+(<jG)?nAE}%Wf-|N!372gVC?G)XXEK!Ti<pVjqUD0rWPJq#`D1U4F
zdaGZt5P|WK5>iS4r~(jX#LZIsdIV~;$-rPXLYVF9Ia+8^rej!%23DRmnaL2N-UL&e
z1hSTj;ux`5c(b0nL**5ta{)3tInYwf;^>~Lun-Ai`F@orVTi8k{ye;Rq>{NzqB4d4
z%^2lRvI@Ctw_-TRV{fAh@qnQWl}BT@kL8a-v{bwSJ|xZ2ZMH8{c%v6*#lZmkZJde^
z)uhX_!8{<9l;^T_4#kjTOq#^Vq?3m)JD48`*Rp2JWuShMX9wmfSu#3-jU<VFrTA{#
zaxnIRC%!gK`#1*=cY;|SWGWm&;;b4JxNd{`&hu@2C=fCOz7mqZA@E}KV19KHGTmz8
zKDZ3P`l61A6ivw_*_Vc^dt@*WGpu#|K?H!hFg;c~O8EZc0S;S12n0ces^cQ+QrAne
zb=T&18w8UlD5>xdi3ELIwDk%9Wx5%Qx4>2Oq$=9$K{)_AiIKeCXLZF0Y=(OY?)4<P
zO4YS`Ee-c_I2zz$848njAYnzz7ZtWF&C+d%?w6Bdt{Sb+@}f?+t@!H@P?1P*2U4E&
zbKv0?R`@mdT>Q=Ke}k%2b)0RmL-EveXzbMqowT)VX_Cx%v*X0akQ`e;I2)b~l(Z2f
zBcbUD`sP-ehmnJlKi#r`@vKrGP;me;teE5>Q-UKTfb>-W$>WDd(j`bMNJyAs$l%Pf
zv>Rh6V4*J~?E0DiuJ-qMj)ymA9^8lw)li+C!r9BwlXXtcqok&xpXI%L7tv}GggQbp
za3fo=Wn$Va_AsX8`t><P)>0A3x3pfIJfS$#kOd&VzJ-A+MsY7f1&k^I(EUscHC)tH
zn%{&#3Ze&ZhOeSI+Y(UQx1;!;pvtu3s|J+A>9R9TJzLeSlH88axSdpejCsC{LYKJo
zE_!Gt))q4`{7M1C{Tk>m=sYk~oWI{A3@pn1P1aJ5)eN{4f$<h)iyQe9f#r*1q8FW&
zA~qwv`Q$TLx?mZ_5e~~J4lad*zAqaL`9atY^~d_5Bc3IGT;QBy?W&ZWBbkb2B8nsB
zqa~8%#}M?93==Ul3A}wRca54W+#2)?MvcJrRvN7$<3Yl>1AnL_B3Kk}{H;*I_281U
zO?cBH#?Gs(xSk!+FUn3AnD$ulqFI8SonF&z0ox!B|7x|31lS|QqF5G|g|=o#(FRQ@
z+w`X?%u-h6`;gg7XrGddg0hjU7~_^55ZMywe#mi5sl80<HB27JpE~}Y=R8l5ylAP1
z0}(hGhE+XIChCu~==&-hrcyFGuQiKOuYn2fh~I=v7dVSqimPFu39Qj*#Gr^(-vrMd
zj!6%LXEJtBBv)XRBySVMzX^?m=^BF%{nG#O-slZ8`*Cod<z=u!L2U}ef5Z~UQkS&x
zo59Qx2uE}x(sy88aE_W%I~ErRIvMuej4xNoIblo&=g2bT>liplAn8E9A!$tpDERBk
z(MjO=nC@dW9K}Y^WN&)4gLKfN__w|}<FsE-i0O+wzp|Vb*n7>;ouZiLNr3%_!90o!
z+U|My7q7Hl&sVMvvlqH&Qm<9|F9hd*oH)6MEcF)VgxD&ITb9y#Z~k?goq<Acj%sDQ
zy^_|uU>=uwtv-jDdW9z^S#tVx<r&epl7BRv+T0-J_m$1^=DA16d?P4cDa?^)8p+aG
z@?>ADbcKJ3{yBR=e~Olt>0`$otY2ICbUL)pRDzxg%avVTc}geQ)AR}t3g0ONHb(s9
zeIkF}{L{Z)(_c>vT%z&_G?N1lCoa*R#B`3HzfL%6F_TF#0%69S=;}-BcV6fE(4!yB
z{~bM(c+E9;h}+q6qW{6t+uZ>SrBCb2D2*+)Rz6SkBp&itf(LrXgW~G}T#C&<cS3DZ
z@71?zyESd$iK{`KmAr->o~5-!neb_Hd!r9A==bXglAx-F`34hL0{-!tk_B}{@%VE7
zD!aH+KJXniteM&?(_(0m+#RGoq)+CpFNtyS6zwg$b9X@VeKnZid6QXhi22qXME**@
zJW}y855qhJW*ksdt=e+@>=U-HP;Wtym7RV|4_Doo=l6gk146UKCWm&K_X|j;J0llm
z5rO1_sBPG&FJx=I?U%?|7hAI&!LH$bZq`df4H;4B{dnq0ycOIC-}%&7WzZ-o&lW|!
zE49Ett)V8z7YoQbNcWaS4GE4ne4ZO8BZueKg;lgZh0lw^=H>z-HrN-(|J1oD>8S7y
zb+nf*#_fILf26~uMDZ0NRQu?Nx)~T#04+7FuL^b_s`x#=M>MSB7v|sax@*?a6PE_N
z*L?l4yVsF;=Xc}B$YEiT?npS@nUv{{FU-TQcKj;j#VSg_*|+nv;~r4vg9sZQdLsVE
zqV&C6{$3}g#`uoE*R`X(5p3C45d3)jtHt6~Hw<7pFx9I+_6F|;OoDG}_l8C#3+?F_
zisWkiv>yAeGP6+TC%<gn38&js?~6tGzN@5wigXj@&dWj^x5~Fx&3`;~lLWhqJxdNW
zqh6ajtw7!k#o-=-ftPbD6G@^UFVw9awfOKwl6tW6<H6}ICYe??n{F%#5u&gVr%F8;
zH)<Q$;p~>d6ny@y%o&#hLDR`pth#^4XCX6vS(qX`9uIMC?!-d&6#Rt4x?2@xikS)a
z1SoaZXr)}*XiXjO5v>DX)Yqg=dO(A<G&IQ&Zt4WQt<-%yZos$7IP=MONs;ofkQ;%N
z`Ynz}2qELDK<Wu6V8jN`Uut4aNg9JV=Ih>I=Y!<oP&Fe(C4@UbWHnQQGS@ik9tWGn
z_x)$wC=3Fy2Yg*n4}39w9@zS{J|>nAAO-<T6#RISUpNUw<+}IdXveF!Li`P!3VhZW
zd?_+9t@rqK55(}Kw-Ne7!m4OJ-KbgUU@2QREEqChn|TQKzI)+`8wqu*@lp#GMbNF1
zhRBGVXU$+yyK%lOs#a-*HtsP_j8v_O+lg4{u_1^fSZUO>Ht0cL5_Jz{$f}+87B7{^
zLE!32)jvoci+p^Gji<(wW5R-S#&;WW*p#>yWY=)Aja)a%@lqsNUxs>EAca3N9mo?A
znH@)O%`Y_U9kGC<*7(=v{|%DuP@@hJ_G<hn5E%oL$7EEv6q(bcVl1oddK?wbemKt&
ze5l1AJJB@G2)d5c1E~b-=e>~PE<^mfW6j`W){YHowRfXty3z$qO;B1R>;SYGEcYgt
zpnE`M7}PS-^h0(#*ch)qicV3ESNYT(5CU515;|qIMtE@Yqy=g$6<WaLxN;Xx*;-Y=
z3{WO_neW=`RpS}VcQ{kP)k~OGhIF9qNs4~x?Y$WJfxPK?WXC@7!m^3iHD`i0?0gzl
zGKQf>)2f3z)^zt-P&lPxe%<ozItpSuxg9Ec#TUmT2W)hWl^tKu9ibc+#YUGePuUBC
zP7PA9)cS^!n(fo8sjO1Ou%h8d3d`f(`3O30fH4IVytU_dVeAauvlGW1C&9s4kaHXo
zNU>K;qg64n@1YB*)nnc?RgZsOyWLJ)gVbZx>I~c%!J27QWNJNVn2Dr}RBt2%qD^5u
zV$|K#D3t!GfFOWmHNHRfAOckvQrdM&UrV6_XYF-Ig&FeNt+*fyxO7Y`AFB5l=&#jg
zc7O;-%Mn0P!ljnm25w#N#QkC6jjT`YTicZ28zVtSE+w%VjSYCpEZ?lmB77l@sQQSC
zTXCR1@nH;N_a<tZH?2KL)J<%SACtQ4+D5%Pn3P9C^jj=lFeG3&PIb!JCoKqyt)M}t
z)``tED~v3dpXxlUkDMALQCCEXK<KV-#kxI&W`2j<QNKqsV1O+)+X{3+S4M~e8;}^U
zj%Q%v^NB;quXiF-3kf=4bb=XSN}lty{xUB5$W6wE1V{Of%%V=~@qBzz$NB_Xw7734
z^uUIBpD&x(VC{uK080^A4dX7hZKvY8TG>N1U<CT7<bM_rNth%6W({SmbrZ=>N2ol&
zxBCROicSc<vx?Xi7U$BZ-uK?=#{qe$1DzaqE+H1g+=}Q|_tKB6?E(%Lmq20V^CA`!
zF&-p!{#xMJ7*3&L#-e<7JO!=*LK|tFSEs%9oCP(b6vm^9dBsVn5sMgd#+cXwYePZS
zYloZeK^9cCP+%@)!R6qX2n?KRnq!w0hp~soN`VZuvsP4~dGoN$fAi3X{(ltNduH;d
zjuR0f{Rtc}P?cd-?fi~ua-?>KO1T!Plp$Mw(E2eReBi9}Q15@C|I9V{L@j!mi21Hs
z6?dnutQu+D5Ew@U8mUy*BV4<c9v!&;2oUs#=~3?&+3_zNO~h+|D!u;c!Q7BuJ3sSH
zzTxY!<E-;~`E3eIjCZ8hsI>>_bpg`rM_&C!?yGJ5MY;2Lqv-mlAb0-FpRAuleqxlN
z7=1+RZ|=ujERkJ3V|~L?HpOl;^-Zx(8NX=<Y64Zl?#puFpRNGd`}ID{hrk8g0srAS
z7PQil42j}j2|^Z^j^m-_H@c~0K(0pcuMvHIF)K$tobP;KuOE?SeBk!_g)bbBv9tIU
z9|rat_#-R&6?%6YjY)g{LQUT5xP`jwQ4YZ=tXpBP`88}V!dPZKHvc|w;l-D^WkNxz
zO8kV^>)AZl-f&px(8s&EF&t?)k(h2-PD8^Rv&(^pZk#TH-a#d?4E9xn+wIH>yMyW<
zBbWJt%|?^4U@>{`%=ma%vvs{ZT6Q!&r)RIQ*SMSxt%_(9{}aM5#QGcJYI;%a66&x2
z(R*DFnYJ<H+G7_uBro|fIIZeUNuRECcuT%~$9lfE8~LI(ABF8fjAbSR7*BwoSXMq(
zMXfGi6><(y6^Xl}Zn0se^RXl>DS~lqcw8Eq?+rPgH@a1~lJg`5sRlOWJ;XSzTM1#?
zu4utj7Q%cq%{j=|ux}G@KKu#8G!vrThMe>mDq1o9Fq=lWg;I)5roquBz{F6u!sd{D
z1H1b+az<B*^1!4kHH<Y@9+$KjV}{&C=V{*5usFBZYELHu@bCpwO5&+jStGO!1|w9s
zi0fi=X%uXeDSE00;4o&ndLW4|QJX_?5=~Ty#((ga@AkQ-o=b2$1K_Gj0C$t<sLY41
zNl$}}n$LP|uLQD>d}jxV63P8RbxddHKs+s}Q`XNsLdlxPP)UfD`17=6t{vqEg<g!M
zfLFUz&>P$2JwhKBQq>G)P=sodC6VYy^+D+3@O=?id81`v+YEMaG<UP7K~gFWYaXP2
zh6*?l;{X5*@>7*zGGy#Te9}f34YjNEZn>HmMTGd(o2is{pwX2`YDmbbG%<Q7fm7B?
z*2wy>3t7iBzeG8V6m;TDN`^xeY>crXjg}Sghh%0f5=>H~-dAPP?KAJHCdeR+!}c(E
zs}Mz0!PCk~&cWFNq=9odBH^wsJN^4p{5G3oL%NVCE@=R2^}Yx5W1zBgRwzF)#`NUP
z7_p2>cfOxIBkcOT9<GOX$D*fKCJzJ)j*hN0qPo3Fy9c%wHmsI3E(s%cQchMx*^vet
z04;C>fg*Cj?p`K9nuS2-zxlW8>1={5wTWe<*)(xC>J5|Udnp5nMb7REqKjDOdf#Tj
zQe!CA72EthUg-`__2{#?&8GQW4y<z@(Nm@-K1;xz$uwJF#^xac|NmZ5?BwhXY>%*J
z)Mg2=V?yQr0{RfiKgpo9FDH60i(nbMEoO2#30OV_=pWfcB&}m4?V}Zl@t(Y;{>jI{
zT!7^XM~|wyngOJenG{{P`TYgQuwaAj#4x~d^wSA$cR@M_f@4+9YEJiAKvtL#(}9R-
z0!md7QcE(T%2l{40jbi(XyAgNx=jqIKJ>c4IDQSGN*^8m&5!(hi18H3;!-n2dc1lN
zSCAJcf*dmXv$v{5s>0GF2C9MLl5rP{WW6XSk+;rZ*cvJ7j4KRY3i!S6=_{Pc=q$w;
zdMIujHN<U+<CJQ}Kv*9yphE~9#?rte*x1Txa@~idNe#A%%ysPpzT#LO7Qhl1C1Mn4
z2jbgGMu7>2x-D%l2Vl+GW!xh=Vk40Hx&(Y2A=rh;;dWFyr-KzrMjTn^7{77*`%Fm^
zB^={XhlL0Ozr|f)K(1&ghyhsCuLW=Z?&Db2R9(y!yXX;00~$=?7r2VFk)ys{Y2le!
zGH=akZ83}D(`E+mk(hKClNIbW{2J^$a5NG(;F@3n5?N^i89D|AUR}j;I)@08C~mk}
zaVM+JokF&@Q5|!V;%=ifR3n^ve^+co$$<l2;xTYM+`|o0yxE8{VsPWJFRieKo_dcK
z&@H4qS_l?fk@15HtZ4PR`WDQ1nz7JfsOUl%8=|s)*vVFCBqS9<&UZ*LF2M4HBpnpY
zHy4P8t1;;_8>0%^lEGgiu;x0{KfA3B1DxiZOAsvlaN^^9oCr*AhJxb8eF(i`i0T)@
zUZX+F`vK^?AJv~w^A#LGF&0p~I!Eq`VG8>%I6DARNK8}3`|8n%Ch!2Z&v-jm<dtzW
zG}nVNsYM{X$j3Ol6H*(fIjc~5hHt-m6sT(&=2GJs&mNrQQh--CVn+8mX2cM$G5RW7
z#a4<7X<AGZekmSHsYSsWPL`^~5(sy~NGl}enudsBmKy?b2TL}DYOLuZYcN?Gw~EgR
z26%=Auqul1OI^o>6d_({U3|VCr+R(U|LrRw`l=brD1hE179B;K8nmgQjF2Yk_W|>6
zo3!SjLVz~{W}bsx2wCgWI5lKH2486zq?^dVjjF!}cQ?z+=+_2|aAXGUD*IGL`=Sew
zSz@RN$%r?*zK%mwdR>^cm^djMkgL{=R0X<!%xJhfq-+DJH-w{qV^(OZXcSkSOTL0H
z0YQlX42)1WtJ`$uVpD*}1`bz5cac7ai>*^5E)Zgk4g~Lwi6Y-5zrOW7ZCG145Nt36
z10)}<fS!?@LpY__Lg{U{k-TaOHfbI1?G`kM<Q|pAMvD`hV5xMF69g)UEJ$ClX_5@M
zF6Jg_TVu0SbP&SDjAX3$HC0^ZF+;9mG38qbMIcWCPY!Li##keLW$`^eb`dBDs2~x^
zSCR^DN=d@L9i}KLUSMkobIrDzNxLyvSA-Cm<yx7ACGi+iGDy*4qNL9GF<e4{BEQ6k
zpAuq(z7S*s&cz3a4uCMq96DvJ;o+yFRUIxE?l)~kLL;t~EZ~ySZKPx6Yd2wOShQkE
zuZaK&N#O`e3I!1+mZ41gPoi=sx*mkhrlBqrVm>py#Xy$!5|V6*qHNhxNfWVJ$_#46
zj|CWm+e9fCXNIG`LXrV~8U||QER<KN8)W6#ORivucdM?k-Zc`~ZRk}-5x}9J`M%tb
z6u9s^!52NZVP70?o)5Zq<btgD^LiJCo6^Z3KN(&REwAwi*}XW$ZlC_M_VE7+^gGTp
zzDagmzrE{?!rUP&@y*F%_Z#Axu%5OW<fyeGuJwxBQoG4w8M66c%Tpb_TIvL9TCNC_
z<Vh*p(C-sf24$m`{Bolwt*3AYg=0n7Tp`v9I9g?3epmvfE8&rObO<`Tm_!5#{!dR$
zhTj!6o-dxF@J!?jx#HuZy`d)?3wpAdb2}bRu4}iyfm^<uD9-2lpPNKRK$i7UI=5n#
zUB<;WktZLTL?U24UCwna=4$q6wwE4Xw0g*i*T{0I_jbN)&5H6+nLXCm*nFW<%3lwx
z-Qu?5wX9`+L0_&tN62Koa)hLczp*%%ir7)>QvOdwabajwyi&=ZSSXr{`h25WKydb)
zUIDzcPce*W`OOzrSdc$fIif?+o_&<&?LU7d|79^&oNEO63C6U?mPOg7Cl~TN$fhOT
zDw7X)N6yOFR^=fsj+`xqAoPWF7pbtK)HR4l7WSpfJDds>MXSuz1~WZ!L%w@`*~Q-!
ze-yZpsl{ys`_1C@U_3RpP;5Z+`(IM1lQ+gdXg6%EY@yH<FR<GL<iBN1`4*s5^iCI|
zq}#^i)ZGk!gJ(yz^~Nx*;?2^+wUPv`8xfuD0-eQC0qEj$at@#Gh#m)HtaTyQ9v$71
zfC~ABwm5o=(pl%)H+x{a%%|!-$uaNHam%5}AExyU<U4T|?VjuzUfbdx6fH=Hb7D6q
zC73R21k%udNRy-Dw0ml28KABE)ZM9l3%6Of-@;!f*T-LrlI>^0lfkRvO8x9>Pgy(3
zrWJ4N6|xvKCag#1f~n(iASUFn!RX;kx`$2OdkgF|N>2^Um@^?bEudhlwVXUX4>=h8
z8Hy?ll*f=ouQ$LtZ%fTp0{3awnEu#42!O#qMsX;Olbe-N{rmSneo3GX-}WM00q)R~
zR{+Vj1BbpHZmpuGU}Q=RuUpw0s`r$)7fJo2Rq@^976Y9`Mn6jXMTO|9nkcuXV!;bE
zaviReF3ejTI@v$a?Dqv*y!@5Mb$5L8LL4x9vv$4ZZVAXnZDESPB}$uZtu<#x9t<UT
zK2|QA`ooQBF?9;n{ThP@I8(Lc!o>@xOt=8l%)^x+TenI8serm7^$!GsHxyK3*~b1T
z|2|tEFQ_MDRXX)vq}r!m7Y_qw>ZJt_*zVS>`jz)9dmPAi6R7A057pRiFZsj<P%;I$
zI~%JK>4<0nn?+^;plfz4n6j@FPX|ciFNwxSb~uj(2kLP#_1;LuDpIcqsLQ`&?G?B#
zM}p2%-sR1YM%U=5kYSuGP&ZD{Q4MW;@lbqHoIKeXal<I;uuu3u6e2ni5u~hzM=#Xx
zNzI81r@TmKn_SB-H10`0AR0m{)oVz_C-vULf=_jsaAvR<ZVldi?kqZAf4%F&Fvf7L
zr%}tTynULS@}yLEtXfLNij5XjN9eW}>bBnqCwIKuIKelM2PO5udA)EZh>Qiq?qw5r
zoT#$`!|^_x!-k^`NGw0EZC=$wf~5i^a@K&Iz&?}>8+%$bYC8f*nZK{Ws3GY#z>56_
zya`V<r;b}kM4&T#O3J~7MrZOg;t{B|h@(fxu*%{vw6+Y0FjYIY+i_n+IifwDUF+ey
zVZ%aV!`_>O;9x(h2dSD}6&5K>!V5fxfaxMtpx!;@mA3;UVr%hWR2lEdUOs(BTZr3R
zL=uf@p)(w9EV`jP8dN(q5L~$NMqIRlMOWkE)U@nU9M_J-!-5dpVuc2Usf%CheXN2@
zU6SwDSBml!S}jbj4N9l>fx2f;bwOfJVp;&3XoDk_ZpRb122-`|$>OQ5-`wyn2b%r~
zkmG$omjgfXyp-*d#w{8c?7G0hgzKi(P|)wgNM5j13q64na#*yoU2E(u@ywi+hJ`|{
z8lP!wxhJ)(nW?};nV5xRehn+osNr|45iMf@cVH07Wi@R^1W&`OMAN4mUX_*9_EsfG
ztviAd>?JHgQ0EODxS*C0S>UL8MzQLFOuI3DKj!tj{_?$hy{TS=`fTMT&$g|ooE#Lz
zlM<M=kD_~0)<)+8$i>PGIbV}0`2q<(B7`QLycu2_c&dJT$QvlaggX)H{pzh~VOTIo
zD0+!dSU@%5YS4UX7}wV$Y?Xo)xNoZYg=1B#fPoZI7Bx5^i(u+bfi8%pCd5u<L93n7
zcep;+zWdG0B^((f`Z$PPUe;O`N1UuBpIj$xwnwqcKF5t1U>0AVv=AYGI^Z$DRtdOT
z-i&3WdJcn6mBOe3Kf$&M%j#Ky-@~}L;%dBzeLfr+<Um5vaEjWf!V&1w2leC{VSGfu
zj)7&@11L)&4C(M$D0lszH-U)z5WhpHlEAJ2k{#R{%y(O%5n#^{LI7iD``nP}XRHLC
zA`v(dy<{PxoFz_+1L80{z}2umBK*K&(0~)s!EYPI9A&fF@$t5XZRr;gfKamv7Nwi9
z8<2uTv|&lgTij@ywiK-eT@guuuU(wTJdRe;pv>K>dqdosi`oaH9CBn9gDw{o_FU7|
z!$rZ-bS0$iBqs?;#aBpVPchBL5vC+Dv1QVly?{vih_GH`paL63;Gc%)G1^PRvpN~#
zF(`+(igg9f!e3zd$n{PQ;gS;`Tb(5JNj=*Mz#Gk{i-FQEx>o^k^xg_;-3Ah-$BD%7
z$5-(#>c7D%`6E!k{<4|HVQ6}z9HSdv7QaG8yD9YxD%w>n+x4rZxWD2>?mB#<uHF}a
zSr&XlUL3vJFUx{~c30gn{)rU#R~P5|S6?LJx)Emnxt=$AkrW~i(dn$}d2je5-}U{7
zl-;1Z*mS+~k%_%8>uy#g+f6E)ZLIR8&9V)yy9wTK(MRNTu}V{2d}CpQVMWN666{2=
zFAUZJb)nl>F)H~ymiW`HH+dKee)_TcW>6`<^Zmd075B=o_#OWI=^mB#YmdWAlt|5U
z7-e<~mLXcYgE&QGvHS7KVs@OTwf+T%o%klQ+u9()&&`-LT*?*K4(g34SF%#EdfU~q
z=9|xo3nu&xq+RGX%*gX~sOLQ2*huqp!Z+PCiIkUeS1qwoBzelJ)19H^=G8E$LAe!f
zVlw1q#{b9J`vA9fop+)D46965ZHem}_8MhX+=Bz~@}DTetc&X9WqA({E-y(?q!3iY
zakW_!1|?dNBZ+0aY}Va}dvO4P7W9wd<}tf&LsGP&Y}3|KHF@ezW-8JkP1kZFt9V{b
zpXSw48CTuOG?vVydVTKp{SG8MZFhEd=7Ewe;?Kpo=X~e;^ZS0^cS!Qe#9~4yb}y;C
zx`H4f+3?i|8=npFR23EFKCS3?Duxfi8{FV%S^2D{S$4w=ZEy^YYgFmX0tJmDQ`ZRo
z%^6$lRHKG>u;>A`9jS`4<LE*MiiQbRh<zc{tyYLXo!1`&D=6gXuI`}Y!SC2R;mtS1
z@-topoHod{3#vWiSOzqt@~2BoxKJIx_`i4zv5R6}8EL$W7)yk*CNxyYThXI)TFBvX
zyXg0X7ID@q-08yO9<=-`p)>(_mQNckE{SsJG0jxORpaWYR-r3)eqP&YS7ex8XezHD
z;_uMs$}=4=hy4kZm}-vUlo9cUe89CDFEA~1+4fP!v~t^a=Ph-?Ir4)~OSq;k9j*+N
zW##}qCd&bTfdq)ZmuwHK7gU-rj_DZnga@aH^{}XqECF(GfNp&n;BXr9)=0!-tq>Ru
zw^QC_<6LwE_8wpgdB2n+5@y1yk<k6_HVMN78hX)lQZ`i48?|X!7#!+v@K6xJ6b}V&
ztL)W1G><o7XsA->64DC$JOy7~@#&x!O2N!S#_^!}sMn+KB0++$(eVVs7kE4$EFSk<
zMR#gIs&IlrKFo%v!+(@EkQI;H)F3oajeJnC?Y3?&4xBX<79P_n3pHG2bQiTnzsQlJ
z#&SUmHMD^~U+}e+XBlfHk2kr*_3O-_gBnKQU>wGZtxtp=Cy{ah(0V)5JgxrMB)k~)
znLr<Xv93SBj?~X$)ZpAU<U!U`f!2eHgqD)QIb`cJ<tnMv1Ot{`zNbk53_Y+_<U~9(
zXXA=kJi~rZZC8zS{8Z0Q;d*!(XyT`w!mBE1;3g`DA8UJ+*|9xF8Vv9}nv@_3a>fQ7
z60JhpfW!m|K|J2(zluZC-Nyz#jRO#u7BNZKzw)8v{T^|~@SsA*tgJ{hn_Q(ZN2Wx|
zQ<zK4Ye-o#jRhSa2uVn;?07>iR0w{TSs!R6$73~!1vBpr;R~fodK`CK1R|8blzhz7
z25!H+4$uq}7^=)7)fY=18|cBe<h@w(!isjT;Ps5|`*hwv-;dqeAbVfBfP{p`ahJXY
z#-0@b9H8U;g#gl_@+u7cN1(2NeO$j2LyED@@A=^DU*Q!9b;vR6UxnYK=0yI|FB^#y
z9j;2=2KIt?Igo!v=PvpZP{510AQD_gepSmqF4}Y->g4fB0J-=y;CUaU%k}`TaUp(&
zLO%H2BOdvyAF^tnvE^IwtH)#7^&1v>9}xatj8q~`D8_+Sc1-!n5au864H`ZUo*?&x
zs4uh~Blh!r1Ccue1ICx)k$-SHgNs7N;{-6D4tAlGeMNV`j#JS>RUv+ytEn%B92`-Z
ze=LN?&e+ov^1}oZgZGB;Su7ex3~>gcWtTA&tXXdZNC5Q-3i%AY{ZIY@BWUzN&v~E<
zB}(q|Pz=1WM7;pedQs;q7r7T`>9Y=|MfW6dO)kF$w}UStp|a1gJ;<1qWj;jCIuFTG
zcGJWg9*zUw^B2F0U;g={7nh>{{K-##2PN=-^yr%YbpFxx<d?`tqx<OX4=*TR2BK|1
zE=?(_|MY>Uq(Ig`i#rcdKv({<=O6yhZFnD6K?E@2UdkX8zC;6Z_Os0C<@E)^O9Ij<
zUsF5@T!hJsgB&gzb--ToLmp4!)3Cyg4fzS%gS?#Z1PET~C4Pv)E`isbUSTwFrRz4-
zAVvY$D?mPT4r@(#jCn#a@tVLAG&q<_*#E}XG{)1rq|&h8z<1*KYb=q&Asx5_d=h4<
ziE!+AHwNM~E<a+M^0M+iKBHqnnH*K30mEg^NEu+{JFnM|X>jTjBeMepqrwA12vMq2
zK6l|+%*`1lca?nB!D`nf+@p68RZe$adasWjq}NC5%Gh)I$2edI6C+z#QW5wCrOk&M
zyUhG~-RVZbF<z3d^N<79`Z0YGUrkv%$Co8QNTHCW(G8CYW(^ufHsIqJ1hp<PeBYok
zd>1{lefW3?WpucHuXaz@!JTo;EN#zuJiEm3gyGlGO-{pleejioa_M1fJ)QuJNh2e;
z%EJ}FuyKP}Gx_cK1#{EkYgNF9kQT|KV8%Vh$FKBaDeCVx<kMKlpI$}#i?iG1-J&lf
z^~l(xcUE2wQH4hr_(u@m-E>wye@Vf|uFB_%4f?|uR7_3Y2e%KoMtlHE^V8?$%s;%2
zR4yOv`+6_(0LXm>JRbFzaL@1%F{gNkWbt^QI(5{rU_E~NBGtVgzxwc_Pki!fr<`!l
zd+gz7Ke=%8JAozK;B~oLpIlkKdVTQcKi)8M1{yz}0V+Chf4E0o6M--TKUZfEPHdW=
z?yz6P2OiBaX7`hg_utLr2Y>MQc;inWXV6&rA@ShRb9sDK{n3k?|DQju&qK9IZC|fS
zR3PPf`8lY$Mh=P@mVp7#7m$v;RE>?U>I2;ys?9-y!|^~`A)p?TC(2}Yl{NZ2B^9UR
zUN!2kBH0C}#`T4KBgD#5NG*3wUjD$Cc{H#`V+<n=g3IWTc}zkmAXf>3r=jDK2Lfm0
zWB7;s_s5Ta{O^yS!~Z|{oy$k{`&siz!m>PPP4XII&Pf4+>l<ZMZ=ON1*a@6hsP52>
zUkL1W^}rvIxx_D!uBJJi&^_Yt1RYM@{Qvb4e_vT7rYjpF(SU646%Bdk+W~hnuo%{q
zKs)=jsYk=Q!#7IS{i^6>?CAe^TyU0JbEF+qGC8UTca|U-&k`mD1Ty0^!ihrO7=?|#
zU))O`z1GM{kAU3Z*uYO-H2=F7A$y8+K*?(`>e!+?U52gx@UpwGo+0=tU=Y+l_#QF*
zzx>S4Q|oN@I_cr9ezTK{Yw=2|!MTRMd<7F-`<>Z9ObbMv*UewnvrUG4FYmMxudrRB
zvno!C*EdAt&5g1dN4#*``RTiVi5zfPR&BMm$bpaF{m(CbN!JU3F{SO#lv?=FwNp2<
zJ=Io!;wDRNROGccD)nQjLo1r`WLUmC-dZE1#K>Is;d{3x!7xG1xcuuB4IetJk>C;q
z(7>Wobc^yK#6p}WdN@mDxO^nh*bNU@eqtOFVv5i4{>%I_n#K(Bl}d)MWvVO1?NCoe
z8%O0~I(@VyLRkyd*^q@F{sN<`2Spc+i=lEtb{0&k`#~fWup=R_-jvn#cHYjqvN^o-
z<*jwrm6}?;%=zkSIdzkxaAeGOL1*!N|G#~@7m3_nyG&f-BSxMq@h?$pIm-rlA0OD{
zer%^t#*4vX6P~As0D=HLWL3V0r?xoXW3xg|tnE)F_g6WG%P93ErFtu^GE2b@Vf<a|
zrS%$lP-V$0122i2<>^X|8}lLwXB>S;VPeySV)wT5aMem=X#W<sI<4W3k5+m3hq>wM
zmJre;othg`2c3S9QjXqvy#B$WT}H~PKCWe&J+wr!X!*6tH!+u@hnq=IEt8n)JodLQ
zA9c?&<B;Fn!;_nwUglFNP0Li1`!U_NFpGA5Bp#i1%(2!@S|d4nJ({ZVm)QC0aBgbP
zjXynXzg>Q#+&^8B>2EBJ25U4zBC|~IWUYQ&mfuNDxm&B&!NbG3o@yhVuuqAXAIypQ
zL6G)B_g*y{F9ZsX?i@oWIW4w(Q6cgCA{`*hbPw-i{aZPR3L2I5@Lk-*3Ah;!A;HKo
z?NK*cpLn=HnDOcf-Z)w|ldq_z38BMbCXG0YN4u)%tz(phG4H5>e?IkY^d<MRcBgwh
zg>l;_D}&%Ypl9-8pn&?d)9zDoK(NZ0H0>f=jI_{!DPFVg3)a$6+FIpZ_7zKD(#vj=
zPS4TqIgb|n%cjS!YMufP<<mCeg(cKo5j4CVaL-3~(ti3r<QEcwsRuWLL(-*;*M%lp
zI&TfELZr-8j@!e0ieFCg(TyUSXm+c^0Fcp&7M1nr)rwY3v&_0fdl<EvGJL$o9|-G(
z)$gVLkk*zat__LAMtMk8lB1OndWT<(XWfEZaJ-#Lm;Pe*67GYAH!+>#Hx8ib_Yr%`
zT7T}lR@E&nmlIdSP5#H?!r9q{fEK*}jo(23|GmhF&LAc{7X#&Ww|8MLauVpG(RRnW
z!=g)&Y=}9;X^N}39n-|^NJ%2TiMHh&cEJGdvEM()?LGW0?j$mm;`X<j*D@ekH$j%l
z2nLi0n`L`o<J-BFCcJ-?y->;xt#@79+B0yPc3dkT-{_y$R+8FFICcpK3!W~xj-xNe
z6n#gw6*u!G)<U~zhId@p7zA~>%lL?~FQ!_J%L1GDLb<PhaQ<aS_Xh9(_!slurg<<r
z0;A=bb77+`T+j=z%9|NjrNb-@@#0bo^<#(j`mv=yk*xD<;*kFk^+N&8LH(flKXa<w
zaq@cs!5nuAfEmFeQ@}Rv(ti+{V*p(vG2UU<qBo=B+xA<$(@oqG(?WfzqVk-B9u7F~
zcGfuY6w*n0+ixm2$fmw27e?>GzPv;pxYhP+?Hk{-4(7s?b9CLCPi@R4u&K2l{gp3>
z)8RCwh!!gI@t}K-#M*EhCK6!WlA9wj#}id<`8j{Mxv?a2dtige+kgrfq~uv{GQo-y
z0)%|g-CQj;G~t>8-NXZ-cgUDN3iXZQ;L+)hzsuw93vORIxq9l2@=*D>{pJO*P$xFv
zTNJNoiMwvtL3L-xUNUNTk@E+_??><FXxjrS2E~zyE9>!6_!@4X#|5en%uQ2AFFxZN
zUk3$DRDdDC6R0eOjorl6-Q}bduF@U0nv3EV<Xl6+_V7m4Z%Wa^eZa?AMk%m>j!pQO
zImr9BZ2M#?p*EPsdJkGJLho)3$bZLK1u9BhX4of*s(YpsS+xf3KNPjQxzySelq(vu
zoD{#?EL-%H%?Db%ut-kmFif2>rF|^8ob96fNEf}s?~~FI`@w4IRH^ImEq0kz*AsK1
zR275e;r=TkE*1ic^7~)MRtapNN1X}bB91TU4G{vZYosQ5j$4~t2qBjwnE_!Ff)(-+
z7<gc<>@p{p>Q-$Jw@-_VUEqH4CeCzN4q$pPJAhx{j(c~o$STt#JVRS(A5DB@@nNI3
zJjdR!lb;oDmtVi&e9h?ADrmKh8tGuc{ZNTTS4oTBLUv|Z7u&Q}$q_omE?HRD)@2@v
zepd9^D6kkdzb;G-@yQ2W9q`Oh?=j&N;~MG{+RlaB;52^II<#y-_gYB`bJ52e;aGAM
z#MBLR2ym0n!|FPL?V_m+^Z|pCylMBKua1p#4V&b(p2c3#y}I5snMNrI@1k?qY6m;^
zlv+|pxc#D){;!;`jq;Lu*T#9d7tov~h>W_j`yBWVPmvw57MMNk(~f<7ki2|ZJXl}v
zI{aX@da&a#?XYvU#&@V7KRDjMNr&`{+C?o8$ILnL6G*y++s-|aKi`L5NCW4i!)z%#
zXkoN<S7MnbGIBxWAL(t#P2$N*^@eWhr5H6$*1s%eFvodO1vj4Wl6?+fN0j`E627Qx
z(oK4qZPFY~)>y}_0}s}DYBP74Z82{7d1}JmA!ePRgCU(GC(x8O77P9vIg1jlFR(+G
z*>@PdOfN+rxR9*&$`Rw+sbRXs*8lVZ_Q||B1^F5T=Ir@5<9U5C0EO&{V?NqQVKESt
zT8l$=wkYjmgUp21+QSDZv|v)j1NZXrmbc`Vk7D7la_>PB2Pnb@-0+avXATDPaQ6`m
zYLWX&`WbmIJuG+C)n9N+rI%LUr^{k}PPi#>;}Txve25WT>~7P~k&cVX<#d&GMZd$c
z#Hv{jMCp5__HtLpmL&$cRpX;v9%PCNQ25CoeEA@D2m)K(ITzl2E*1lE=b7{9N)>JU
z4vkT)gdBVy=GnsddpXQVUGYkHYvPcARm?KhOXqNSF|UbDfyGE>s!|{1y+F_$eFcW?
zGWMlhhlsy*!|HUURjUre@fzsboEBA)xLJ*h!N6cZ!8|VLanz1420+F|XnAla?juJJ
zU&`Hx{%3Jz^?_I)ObzE=VbDBR1oj7N6PD*)EW{rcwt)_eU>!yAq7V*;iS8`vAloql
zg|y6p%pf+XKOVY)B`B%axLcJ<Y>LZcV@4{@$i~~vLn_WDF9hsSNtIL@S(>D+7-Q7z
zWS!Q=DgHvKG|m5fY5LlH**#eqYJPi;C*e2m!0ya{Rg1Ox!ee25pOU35(VSHywH(~J
z!&B@)3VQC87!og|nT|U9+MI*qr}ZCwu_3sE(;jiYo+!>6v9>TWZ$3~(umm|csciD0
z|2@QqV9GB;M*27&a#Kh-lFNXMj?D(h5+ycU;MN6RK-Lk7)`|%XRDpLTx&M0W3Jd?3
zF^kl){uji{wcHiAb|AOe&cB&E&PO&*miz3%v%@%*uIT{|m|X0}akqw{fJ=K3)#*F3
z`&L<d^nh}o)19S1u!aE@l!j9uvC=Tj<%UGL|0cg{-?jgE?&2J_gQk5W@-GTrWPVX1
zh=icl21D59k^=cA9XNmBOS!~PXbuO5aCm|V`B&;LQ@V@)WT(Su!qQN}Qyh{7OR|T<
ztm6!LtP3=uaTd89PdIP~`l_ApVW}Se!fM~)p=y@_ExO0<TmC)F)3vo)6$Pn-4qT1E
z%pz*waL}}_!F9!cjYCbm-y$}nKglw~NKP*Q#N|hfE8@GWA640&b)1tcu80YH*lzvn
ze*FTr`3H*?gi-Lgp!%C|LX@rr&js3i#scVV=Pj6d83G|rG8;Mf<CcDE-d(Z8jYD%-
zqyb3d9^8yAptqXUT6J$lDV)_5RH6fuL2_U3;IoYGvG@yBKAd~Wz03~(@cPndd8mSh
zP!EKP=7}47abVy((&LO`47;Ipx=DL?J0ph<kgi;f-;YMIzpUqf$Uj<N@7QA1VSEt5
zx7f7b;b&Dq7+Ubd?+t~_D;ll@iz3AYm>lpb2v^-(#8N<AVM%Z&k2VeptLra9zN!E=
zoaBRMHCfe)aQ)yf1mQYFe33Nq;BS&=*m#pa!h9ne4$gJlq3%#&I<%$>Ks{l+0&Rap
zo+BD<TqT_(b)Qn6+(*aRzG!5h6z=O7<RIo7Cr5tx;PuxuFT8#j@RJ%y=0H<)UH1Ye
zuS-k@q9a|9#=2&DI8uz0dwNqi6|IcE!`n?EMe(ABwkwXJX&qy-+(nNtzfN@;u`+HE
zdM#C5<Njn^Lt;@kaIDL@?zqt&rk$jVOp;4PNwY!HM{?sl6XoOStTeKzMJO$KD0$F(
zI{oubJ+8p+fovi~S<rW5oG$fQIi8$?-jvFpV?ui$PA6mrT~b}T#2GUgM}ki}t%!*F
z^}sb8*9nqIL$Qo|-AnXmbsgve8==qD__Xztk|<48(%IwoN*`!|sbi{o*YVB(Ie_g$
zZDAY2nlAkY@efR8qcu9o-nFLrK6cPf*aTpDa!T!y5}+u5pF4xjT;*fhT|_W2$tVa>
zU_k<k1~;y46QXRxzDnQ7gH|VUqCFl$FvU=&z5WDju!mU)B8ysTL*>w!4M$P4f*Qf_
zZH&4XN;49jE@8r+!~LKC!80t$_wyA|q`!vvLIm$?hH*j<f)Vp)Bn>h6%4F6TUX2dX
zVZv5R9XH8^%4(-O481Zh5cR*QCZI7f*FXBdKh@hXf{+U*in#Dj2>>~)IK%*3PR7f1
zMe-1#fR4m=OXavnKFPO3y7%)Uw>d&z1mFN@QTSxK0ve;Ehey<X)QqI>^zN&!WyA^}
zshaY8plfiJUBuVKE|Fy!4dKRKq_`gByeUKK+E|R4TEC7^=D&R(NjkV`P1sSzvKO=x
zh#U!#9J5r8K#Z!?4|IG40WwfOk7vRL(ZaA(KqG8BB{ISkD@i-GKQ*KdscRFCY<}(J
zy$H}nhES$ktd_%QpWn>E*<2pWtt3-8WPD3i@tq@O7>{_o&D#-JCBQE*tIPd=9-S5A
zX;Mlba63ywa9oCjYtHUKd5`0K_@90mItSXU;>C$f73uxs2l%nPC#k<Mryed7AD=vW
z{V22ESX0$099*0P#)aJ}0AbR|CB;N)j4{ZXNh3}BmYo$`MhvO_@8BGWlgJM5#1EXl
z-HTxYo%K0F;s27BEI&vNVrOM?=%T{?L+X3xMHN;gsNeq5&%rEe=vpHyl>n1s*UQKc
z`(0W=)O~-Vn(EI9r|MY|IN;JjV;R&^0Nm)1`=@tXM9D<;oH-Wxf?eES5oo3_k`28N
zFI%`lR+M(M#EZ-l_|IxnhGB7_!MM3YMSKs}RXP3Jp9c5~r#TKKDf>&+MXtW`a$7?d
z<OY{>_Q^!ae>v6Sc8FWE?H4G@kZG@o;%m{R_SrVpn?5iiifL9Ys+kRr7XiuO@}Y1{
zY4U|XPiQpFMzZ79K0X#nM{&>BIfM*u5@zP!@}#HHhJM3m09N4v{Z}7=)Y}h-BcJ$W
zexMKiaFiPw<pHn7222v*V;Yg#+Q&x@(D6((xzBo)sai%jfJlWLtkmT4Jy7dBLn7ST
zcL2ZX*hDH=kos9Q=nZ<m@$R-~og(y})X@NO8Xm3F2qHsF2;Ph7;q@`r|06>blgkWk
zGE+(Jw>iYm<2V&B{9VirRI)xo%%o!N%j(M`*U)aFW&>6+(X+^yc`R;pFt$osnG5wj
z!p1X}KJJsdUaYA7z^xG~opz*MLnl+`J*Y)#D<stndAUdP;+Hn<A6Yd|uL=`~ZP%De
zsT+t*&^Qf>#wmDD0+<SVyMT8olW2|-QJ9*^(lNgI10`K`%$5GYM{4sRIs!n8u4pIp
zHh2|_vEZ2AMQ-caaP$(nMD8HajH<9|mbx#>VK$Po72PscQ3)Qq^|OvR5tu;?VjA$1
zJb8>Ck|ihX;b42~CK!6{6S<O_4%h(}*Y8x3=jpxD3^?vW0JU$xS=oI>flc#4ym(Sc
z=OW4%+D7bRruv$Olj(3*Cjv^vi<lmP*X~QoA7Pw-6q|&LXLOQ2Hk?(O(%Br>bG`l~
zR(LNrW#IPxuWT!fL0vkq@`$dmHD#g?1E`Nu?pdVB{_y}gb|b{7Xpi!0@)qw_P1wYF
zX&F(mrtDHW%=&bu8K;d+>8Kgeo~b0!PaD<c&RO-eGv;XV6Jb#}rv#T`?N8`%(=L(w
zgmh%H(XA*Xl8?h%;AvuFHj?7Dc~%8k;@&^p!r>C;UFRZN7_S;LPr%<$f<@}JJrlii
z+#JG)<zSKd_DkIhVA2K`>MG^12MCUbQcf|oeZ)T5tR?4ReP__$0wqHFZT&Nslq$PU
z{2NL2-JE(Om$6>hvzFeFh;j3+YZn52D{lorH@K%6pEH~|Ot99T7=2G)CG8}9Cwqh6
zVSh)(;hVI%x=thO;*3bvu$6~YQwqU{>z7~CR^ZzxClFd6g)>#~0#!wJE??tm`28Fh
zE=CQ}c{Ilc_K|%x$NOicp2FE7nQJ4dwe2SYsTIIPSG0gFuMq^O*wL*(1*)rzkGq*@
ze{=18ZMkM=Y+lS<tFB3-VP8SVRW!y#ukZLdNc&%si?NH!k{-PeD7rm6NXGXa07N_|
zMzX0<J|t2bV$ccBt3kM7_x|=<o+bn?&pL%g-3iH!_9}*r&Hk}qNEK9%cqIrdtA;%g
zUCchvYAprnFdc2B3CEJ{(2%(f1y<AT0jfjA<VUj|qt<vjH@?5}>Hr_DUR8@VezEzs
zgFU%JLI<t`aPBG6neNi>#W2s(QOn+^%Vr<TMc6)~>kv<DwH;~_Eo3$2di-aB>`9JU
zQM*~5jZ4R)J03i5j-sNnRLv!k!N@=k<fo*fz#U+mu*`Vmkwx$z2w_~PH39g919o4_
zR89mEuxuz{_aaM-gi?A3YyGm~)<~6YTqidf<~_2Wij1PdW>l=zDvN=n1h1Qn#qJa2
zq_I0(Sd6vr-7PMWcgYR%B6eZ<1#*z(UT}v>omJYoT1H+RU@^8WXtVcjjxPk@KNkVC
z?k%5o(s0=nLotF>cU;%~8o+w#KnNiRUst$t&gG=rMrxfJ<{4m)Cvk^14!XN(-!_qO
zasWx8!3n%$-8+JSTcLV~dLvsEky+l!hIni3{9Gz0u!y%X`@f}jfR%by+hN3t7oGr&
zwe(aMc~#$;jm~BxljME&05&U=i&(4G$n0urUX;z$Uz^a&a0!hgUjnEI=;$m&QwZq#
zx`_YOEIj(xRhpcmn12ZNMk<-g$n-{^$)(kU&IvkBx6*M8M6QT0$0O-nG83hGGQDb6
z&E&lLrgH_31Lj#-KqS2wi-m7P!F`pq-hd*$L~ig{G@6EH&5eyK>ADid=JJMMGj?`i
zI48BHyXXOFTrY=pFHVWU^g&%qBQ^s65k80X34lZ`5cy-1fo*Nu+N|a1#Cu#OHFyPE
zOC-0iB<Gu(umdqyd&^D*2FSUs`#aN!>mVBqr?}olw?BW2Yzfx7|JtxUy73nB5yPlg
zhr+5X={s>QPB^Z$hd-xGllE*hM#4AvQg*zS+s`{!$C9f84Q_aOzW+_2CMb7x?)}C@
zV*{cqk-r}|0A*o!EX78@vixNP(Dp!;4^b!)Y4o7_{8Ep2JPWA2k_hO6H8HRpMa@HM
z)4IW@=qB!PfNu)^lAYP;-G18amVV`osZDDQkdf=;UYhMlKa(MQ7~uWYm#>IhY-@F$
z4|nXhzW?poozc|m+ExXq$Xj3k0QIPdVwB>vb|H4+39``L6@Im^EAsEzp>18!&Fq~$
ze|J86r0s#rhbN|2FO`s7>zD_kGm4?2!8NkoAO7k-I3l>Q%2@;8NWrVcfllMxlT|uM
z2D5z-P}>GX1#JCeqX?(k*Cu}uSmhQDELf-pXgk1w-r{d%%T5*4jEywkTLF|+2N3v3
z9d9fK&af_hg`Hu5GCND`)N1Qib@hw<IrQH-HSmYk{Tmoo>QqI%1w=zkYgb@k_Lc=I
zXu^(jC%hQw*iuO35|WQ8ASCT9`7Y%@;p^|wYIP7m?qIpJ2`FK41}V#+_iz47Bm6e(
z13*Ub8v<o#u^U!4?D%@C6mgbRn6UR)G3nhx{VX6%EG=gjvN&pWmXkevfrFqg;8tcT
zYua{fDn&+aCvgfDXb!C_>2^R>$N>WPjH*Z=nJ=tHE>&vC0DOO=;dFVl46k-?84`-N
z>e_Co{+T6xw>Ox@vAA9OQkHaVvRS0mzDsYC4L6mVW1Yer#8%d-YLZG-<lOsz|9%0s
z%0YIeTVlv?m!60PoyE@#=%DUB^jvTYy>O=CSYb&dF#+%!?nw$D`p3feOU<mP*Y={K
zxG;tbq1G2_uJv}Lo3%vXz|az+9qev6?xYIefUmvMJZ!#GH76YTfzySUv0D!>hTHY<
z-zu?oj8{5^%j5+To-Dm6(p*n6Y*^?*9J?$HZP2-4{G7C~2z2C)E5~J_w1eFVyX9$|
zqOeu<KcH^NF!B@41Q!FoH6IbC^Dsqh&OqxoqdUxTN4B8ULfr}y*3zqwq#3TEN0fbh
zJeY1PYMF`{YId;JSK&{b2%mN@#g~*eatvEq4__iA&4$^HT$aJVPqH*+aP9ahHL>{Q
z%QDbaj(qoVAk^JRjH2@cA)rgv(>{>)hiXZBh0x7XDTS7h$piu@an45EI9ytUgDbtZ
z7<0^`>@aprX5u}aQ1LA^Of#f)S^x`<9<;}^_DCBPou-Mssr~?3G6h$VyF%tDd^T&b
zOU$Q-{r#h4+)8IllO=euBOH^G=vEQ-eX#g>RAiq<(_sxEfM~*@GcrJNFsB3vL6oag
zGF6>}G-LJQ`hPsH7_6BD#2}8^&^2OByHz>cjB6fuq}CAdQUOC;Q~>4gB_o7$o$BLh
z-m+YL=H)(km3GZulx_o-0S9ywa!%Q;-&e>^ARiwBSZSMtMFp%hL|fRHJ`z1hEniZl
zK+guh-UK0r$lfmw*HbDu*%l)|so|{gb7Z%RPFFN?o-#}b!~yD13WM~w!S#`PQ;wg7
z@Vqn(aL<tjc0_eZeOnz~0rvUq!(EMSqG(VIEs?M}%OdP)G45ag8XIyW{>Xrx+U^V?
zZ9L}4HeKjEeG+kT5P^exDYi)$d%9YLk42+bO112?J0(if0%4f+w=q5aju%6(?Q1lS
zAq5Zpv4|v8kT~_g!D9eCVLdd-aiBR*EMvm!YX6ftXFMUJFU&lc0|Ljk2EBa_&h7Jx
z5H0}6{Fss^Hf(EBWi_JiBf~j9+6LIBf~nHp)_@Nqi3W`Yh(6YKR-sLR#~WinLRiwL
z>j&wc5<e<1XIfu>qKw^jPd~m(gOBK7y8#t(rI)BjA}!P}Evt(0`5$?Ua>J1j5^oIu
zlMzLRvt&aOTj)A)&ZcR#p#VPx2nV`@kYo7TUgV>Bi(yTcG6zZ-i#om2<&3xvQ0@)q
zSvj-%U%Jo`PXzUDB^@@?<S3gGQ>7l!XY@_zmcsmv{*coR97Mm@mD&Yi+JW}ZNZ%TH
zZyZSjrvR_Yz0BRqIhk2Dk^HyhUW4dMM_dlo2nix6{=#__{wk0y8OWP&?nN&{oFI+}
zw60`yeN1ovOjArjk}!;|a0>LFVY`+Ub8aUq-nYwD&$S8DEE=~lw>QeOMsP_F`V4rs
z>6p<@TYK2yE7cpU7Oh#e1DR~cbjiJd-hK1pJsSw*lUNx|`K!OdHZ0nZ<P*TSkGsWq
zeBlW|+=mwR-Ag=wJ~v1Qvx6M@ae>heNC--r7l^a%k^Bud0XJbM?kveu_F=K&n5m2E
zikcX66exH}!Gx@IMI8Ot2`H4v=5VBO7|$g!uByyOr^+icqt%(OHxIp1x)3-D8|i~9
z63|H7ZBhfk68;Gz)_n#zHTqx4CAw8ACEtzSornXJ`kp{Cs()i{&>8NJt2p_p`}BjK
z#Xf?5J&BEZ64jtfu@g`2b_<VX(_cYuO}r0c4@`-)De@uLLZ;Y}Wb?5>nw+9Fn4T$!
zZE?Rq4qyd>4l9s=VmS$`rz41%addsr1eW*fUqJStwaRqXH_^h~$k!NuHGOv^)o063
z{XeSuMj7rlqO+ngt7+)Iw=?}E*8b(L==)JdvOMuO_I=^DZ=8b9e&n!Lb)hekz{W1m
zNem0r(+|J(XS+ZQ>DG$&&9V|V3dk0Wg(6VX_8_sb6Kha{{kgh2fu@n7B@<L3U%k7&
zf8q>wzK6}I4aH`D*yL|Guzp2jFKRkv$Bro_mS(h*U1vas#k(x-=1Tim*SEQ^%CDA>
zn?sc~V+@9_+X#gTypLR@V~X7%{6=;^KR8j!8Ic?sgIlZXWoS5Lb=1_iAWcCivL8)8
zUO;9F`zTOOmrurL7Q?}FvG{JWWF9IlTOh$GV21S}K7~2z$8LqH@ncEk!(ccf4)-=h
zvCBE%Urtd8xFPV=!136D-sB3}N^56WrxNT@_AtAPRxPW>GST5&h8@iPaGt#y1)`iu
zC2Qih)P~cJX-~)Ry62vNXB%h@e_4r<iT3Qy>`vDIjMer)xI<#txS5T+hnGc3ObagV
znu~$FSNZLi&p>XG_YpHOw6Be6A=k^YHaSF8B$y#05EQ>u^it1Da~ksDuONQ1ixS)&
z66T>yxynWHmc62;&NiP2pcx8$C&XU)cL>jd(MBWLTry`zh`%M*#W{}EtiEBdZOyBv
z)HmT-;;qh1p@7<VZx@{<VQUt6+V}yZ<!~2&$$GKWv#!HI^!M3Ab4ZhTu$RB_{->l7
zoe9_zj&ULkJYhGIh0EiI&gTvZe;z+f0`k&P1V|urfXFII>4zjGp<jmJM%dM4%1&kM
zrcLu$^9CCE!(O2H6Z^P5&~ynI;!V2DTWD^CcdmcWdI8z`NRM0G$I&sA7jq^oD-hR$
zxq))XbFtm;kVP2QA5S9h8lB3nMiaH{m8A!(ZkO?0F<%;DJf-=|=I^SCq`@fvW)i`a
za4I-r=5<4M&JPJ^85uH`gOFGd68sOoAjba4SN9KWJG9M49`iM>Vy>Ou(MnM+NS^}-
zrfkA*fvnIyX?<Xm0{h;8gDy4bsCCMX{N!buBD{9`Y$P@S+7}xtju*u~zE<d|;w6?L
zVG#GY=$iP7xFj0BCx%MlITu()e?zjWHUWt9D1UL%i?*r_72Pxf<wYHZWsVO3(ZD1H
zU5Bdb96TOKN765MCwu^S<VzIMMV5bw_D{jRxy%9F4`ep1R4P-xZjZtB0@?uNeg;T!
z$Kw$eV;z@Sl_#pJ2l*Z=vb9=0yv6O`U$^es4W~EC_g<N6qIFviZ=f(6j~THJP%BtR
zjC9-w&nL<|bE%uTTm0_f=I>ym#H$jA0Ttn{%<H+H(6Qh7dFWcmIixKPe%n{I-40~N
zfvoU6r+$ncc1waWQfTTCY(4iB@-r-ilzx#M-Qa=?AOeVicW5)W9Rx?<fFb5K@8}nq
zzXjkxCJQr|Y-+N$wUl$k!vK=5si#fzv&}M|37!Kfudo!3w|$j-PU&!$vaOf0H?nu2
za3)E{icDJDC`3~_PDrv31`v1~e{uv}{UDWaPv<oOy$q;VcOUcEMw^c``V)RTfx*}J
zr_?NXAl>>N_+TW3xG#CdRwt@_Wi5krN#9BWu5tlNUa3R>fUSHq!Wh1pWpZ6c#y!2P
zPTGfUr=ZEqWe47kV8A%-E@Fehf&4J0bV$G!NMqX_3>#V0gJeKW)3G5IIly0TfU`|?
z9l+OoP4<F<ff6V?U(iwNqbx)iX4J<4h1O;JW9cUL0uM<VYTZ!>&2__psZZVFkPioR
z>n5BZ?C1fwUAlDxNxqal<xV1JHkKHrKlt;q4Z7?8jq2Mf@=4IgSlTfMo@ycdI%~Sm
z(xDfTa>-gl=fCJCXK^x5-^5ihB1L-(L5~TL&fETf<!>W|m;ru{wn`@y*}^&=Ti|U~
zIOoWF;%`5nl8!k<{NW563)%d(L1HF+Y{0+PP>1PLZ%Yr?d<S3}04N+&0zAO0bSnA1
zgo1*eOp`BivxT;Z<I9m6nx<5e^Od*NQ({Lm`Zd1;bR00i72`2zlWv`K{2z)tOCZ*4
z=)l2ja@&CD5eN%2h<%bh>fn>IV&h-`D_;TrPy_HxxPJ}cNVdV1akedFd(}Bw=MG>-
z=cM(4_&)qokNyE`)WI3LY%S!ZyN(2&Q)~bbBj-VR&jJ5v#tW`V``%}6N4^X%GR9g#
z=~;bl%Pl3JW=D*S@%w!3L8V+?lY0Jl=U)ePO9uRfb1^Bal1B(8VYkxGS?hPm-93|~
zs+HWAJ7V0;i5jtMd|sSU2WJM+^DnPoy!9#M2Sx$dt)Lk)u5vOSEG#}DLnMc|r7TZP
zQi;3dxCQ-?!y-J4JnEJdipKQ;WCG7EM^im?5V3z{D`g+$nW_m?|G1gl56Yx{*FpB6
zPRvyx6bfA9cAi@WSA}<VsFzo3=O5Viw-1B1w6<BkA}-F`hi4G>z!b-K0x)vmCu%#$
zXqSE|yP9pAC5L8d_>y}oy5H*R=(x<cn6RXKAsPl}f(FnM?SrjvNQYTK$-zO0X(yBd
zTn4#pyM55=1bCCR3D>?3xXZXnCXNXSMbD#l)o+5)F~vWNw1f=?1mH|yil-d_cipI6
zlqsbyeUtXEc9Ytz%ff=I7~VX5cjB-;zG^dOuBkUu7n|>?SR46s8hC#!E`812@DJ{U
z$HULO-!hfOCXN7+Y3rJpCTTKwEum$|;RfEnA<X`JLQNoW!cv|-CB2*-GBu$YO&4%T
zmV<JHg`^#VXP`(>0Gbp00_>BA;Get|puxQyy3&7L`0J*sQt4I!Z90%J(?Ey>6>(et
zv69xBWSEl8!?Vd!{=%NfDlfiLIRW-n|Kf~t;z^wFzNp9IZRfgoJAVlrTM0g;(Dnny
zPSOA8beg7V|4sI75b|p5f-udiVu#oT_t?4r&F2>+%85yXdj5R*1TqKGYeUc(^MDqC
zeGO^yOCt*|2XY-gX|a6J^`0~IS;pVv9QD0UF(cl**Q{Q<*No5B$s_`~%^l2&rNc>|
z4q9x^NN%mK9-Qb)AsshbSwonPHEOz9fn^v4{2blT$N~barxc6)D%167&PFP??Vx?|
zFt{c}L%`)vs&hzWBL|-UaQ5GNP<jNdcho?!8bM<@c7}$Kev|;~KiR}`+u92>1T9p5
z-Lm1#3nZRxL?%M!JRKB6DbUw2?~tX;f#lPCoWIC#mU21k=Cyd)Eq=S4jLVOdWwZZC
zOgW0sHtYu_Po@Ww$`p%LbA2hdL@#KGzqSJc-tjSQ8@g%);O`gY4IXzP4Nu5YwP#r$
zlOyayE_@fqqpm3>(1_j_ezrh%<$5V5{Y+{EsTE$lCA=I?BJA-DjLeBZ$V<CuH?x>8
ztj53%)wWjM@%K}z^~?n<QDy@<^1VC(p7Pl^h>=f#hT*yw*%l!K5aUi_oj1bqQo@)P
zIpd&#_9j4h<Uvo~4>}hc!TnHzIO9zd4lF048r9>m=BSxa{7~q1vo9^b+=Qt03gO@l
zz+}lDK#iH|>*_R|L}c|&1YQFZXa^)p*WZztq<4qXbSZrdG&Y^)8Zlv0*1p{OEiz>v
zsLnJLu9PpL-`A6sdoZ>qjiv`i{KQk*ZgO9VJ$-{b7w#l7v%iz_j>%k;G9~t9pF4~$
zgC%uJ&|^aN1MIsW{7N1wQJ_^2lp-m>Z$uTM54ICcn&EY0$4MU-8}N~vh?(AY$VWnW
zW&l&&xLvG`UNhg;-Y|!7_SXm$>_u1#;Ye>HsBcD&rG2nRw4C^;<R&*$`*ZC!QigYm
z`%`>vzxaOtZL|B8I(`zIH14`^n2@}6pJMIf;cV0h-ypH&@FBbObg9K2o_OH0$h&;P
zhW6mnv?jcoX8g&?PdUA1=~f>vU|WC+j0}bJvZzn;Cg2E2uTd%t`N*OGRDn|AhXu!8
zLJF{I`k{MzHAoutj<-qig)@M<l9>ZmCU>wy?^_<TzG7!8?(vOl@7NRO@iMY|4frno
z9QYIZb9z|!h3}9UWHULnH0i!r1?pon9d!yePh3%t2?`g``;DpXvL3La7%`9w5Z)Mw
z^rh7CL=B!Hq#BMb{(L;mApqymkS{UEQE0-Mxl-lD{q~4JO-~Z%T!I*&6}<V|dJhYO
zylum~{%rNsYX9Z+YgUU9$%t2js<xk>)L#EB_1lmqq?cB-r==kcy83Oso3&?J!YndN
z4)lnF6YfC+aEzUZ3lP5~q;Z`)#~>fjNFSc~tvmvCz}iAMfI%IvoW@?DTX4foY(x_&
zefbm~A)jIP0kT7i_p`RsS6$Q8S|yO$j&H4dX<!(P5M4vCW=%4mX{DnUpJM5q*0jAp
zRhlZ_+BiFx=q_U$od}$albNq-AfmQHVRY$|pw>E><!buC_|w&w5%KNfW<rA?-v&2C
z=8k^*S6<U}FYMrL$MF>aAj<Qg02GqYwmc@+PD+JQhdv+r-999a4!P8&bs)x4Gi9;n
zcN#%iP_<WN7TA$#a-?rrnEn7jt!}NB`T)1w%5J7oQ|pr@w1aKdUJ-9=Zv}>$O?&`)
zW;f2wIM)qSE(#A|at8^Yr(u_9FP=Xz(Ptpi|4E4<yK+iEK4sQfQ{qS3e+H)zlx5kF
zq>#u8V9!yC4JReykvazS@bLpG<!BC|MaX|#REwi_u}AA$S%c_GeQbC`UOkf48<ng~
z%kdmyg+BU&$pIq;g<q^p^uGbN7D!(L-y+d{8l40qss(CdELpW$?B_nqFcI(<&^LVn
z#w>X6-C6LtH3t#FMJ?+TW&ujTMZm}3V+!w~CaPBQe%NM6ue5QPS_2eQciE~>t`D-U
zUIyC=$_=oXZQm05F?GHf92HPpk@%DXwUUMeTZqkC=!Uht(PA7)NmOKfzj*cEl~XDF
zvJwpRK!!mlA(xEVIOt{=^Bxwyl#M~ZbsdP&mh2H@3OLFaH&Ac1I_D;*1a{U@6(S3^
zTK6CRhfkryvL@MJC=)|cUe|Rg$RFn$>fo|;F+QGV)KC~6ZgD<kPl)59m}<CoOsj!E
z<zOo6oKwtB7XZc90C4$86MqpAE^_A8fs^bwqW29^oiT4#0#GUyHXol^>W)E(k#r`D
z5M(4M`avnqP(7*ma|xMf;vN}>{pf%F7x3kp$~vkV^rJ=`hrOZrQ<4yN(jjV+_hg|f
zh6y{3JqHq(^e9~az<GYi*XEa#4R?<v?FJM!6_Kr3>8s;+aQY<%3KEVtcn|(i`)BsZ
z6q|i`f_F_c->;U2jd&^Y1rga_g<eJ(+uD?>@o7|-8M|XB!2#kF1QDSn+@9HeKTDA1
znItuSC%c5Ao%Zsn)%G%~3`V&N^)+ld7ga>t!F&JmLjZ2b%AW-@6`_?B8<{-r6~08e
zF4r=XD>a_HmHGoFu}a&r%=4b`7r_L9qw_ZU4ke|~fGq$30%C}JXb-fmC=qbnd|;CC
zJHV<UtM;qYyef)0=;+j&&F%-_K}~DZ@tfrW0l_#T1Dz<zlAY1S5<Joj)H`?$1o{92
z=rj8f?*1nKIi%E(^XNqimxQ3Q75H&To>4{Z;cz*iKoF)u(*Ln1ca<Kc8U7jq0anaZ
zMk>is(FDshD1n!=Fo#%GEqIX~V+668-Z8<^3J{svQfz&EKYev{0|9>noQ{4k>Hs&8
zfoLl%1(eUlp1#i%BrQrVnH06?WNFIHb(FG3Vl-=FmaFOqstQ{by!Y=u3f+eHDUnEI
zc+mk0Ep0-Nhj3q06!sfqm5f}eO5~t1%a7bSGvVXB+9!(f)W|iC4%+f6l9cVh@4!lF
z!EQyTEqW{9hDet4<cq8+W3}YgCRvWZEsonI90W3>eeH^d8AI0eT<k>m?!~8q5}^to
zL+~DBq>W9{7!qn3`W$VJRb4k>+_m*TRv{dV`td0bVr~%U@U0FC4LqoQ2@!@Fw&1J6
zAY$SlCM~6N2ZR~J9|3NTkPAHds;I)1LfxGMp_axF{*O-KT`~$($=VVn8g51=F9Nk!
zEozcYht3~{I0?>59@txW_iZXwM|dCM=ch_9x>JHpxfxROS$=+1dVx^Fd;Jh18-fRv
z7fz(Ehh-03|FagRlVgm2Y(wcKNgfk&5HRU^|9}s^5t1fgt@iOXj-8a6Q^gE&OrVcS
zusZ-|CJY)4L0zz;R+_w?VJk&#uDo(;F4bMZ7a_)d0{C>Huo&*rpCjp=L?=3+%5AWh
z+%$8EoNbnJb{~Ecp9(qm{?(BXnqHxOocFW?s1L+pRD9@R-?P9#pvx`9c`(va1RlC@
zayF$bq<D{1+M`J3tO#CA<yHg&<73hfY6Jt~14RjYDbwM)u`ia#pBBk<bi6s0E*HVv
zy{0ztYg#?`8oYt?B~Wjp?GEd)v_i2L>7dav&;k%7`Lz2ibR4D&+eQ+}wfwz*TRQ{#
z_;FYRU>DdO3s1Cx#ff-yiX%dW#q;CcfE1)scsQw`cEF3qvubJ@|JiTjh>t~3)NbQP
zQtsfrL9evvT5BBy(M=Gv)fYL7vsXDXd=;D!|Eb}!w`f4>+@0FYxu<q}KS$aXtqnQV
z)-*Gdit?hhFABF5){jq#oc*=sCllYoCRo%5zv&SuiNw)s1p93<Koo}TFUFU9xT|_0
zs8UklW`L){LO#YB??s?m?QOPsM%L8!V|+m`oHZSe*E{4Q8`D_?{?Acx!TKh~GudQQ
zW@07T+>F#K6i5GUCvex%7sE5inxP?Ldw2MD<nyF;iG-2f+cZdaB9fy>RYxpL7@|wb
z1ZaOFkBtkqB#=(z5mB!MC;nLm_X>lv@Si&6{ozP4v4Ar?y)vxslcnSqg1Ra*s}Ay~
zeJ~j^^9yrPoR?IF;9gYwDJ>v_(wqr;>NuOUGV5>9$W$tG%~=x{E63C=nN5Iac~M)`
zE8#_ytt0u{9%#`?n{OaZ`j?0d_cB%zfjGmidDcc@6)Ktadu@LJr%i%sS8)Z&X~dI6
zhXSkHxw<UW=eeFF%Y(qc5IVsGN^xFmSObH@T;a(Y+<)wJ1bOh-G%YOSrSLHnJrL<f
zY>Q;Fn=28vKUD?U@B8L$^O%Ycly3v?!?8%a!M6kDA~G4nwxrzngJ?8njb}K8!j{&l
zs`i=n;y)yOzxgAX-kXL_kcCN@AP}fzhj<AqA{a{eK@SF5>0>vd%_sdl#08KRb4|k;
zw}8m`o8916$_hN(Z7)nbq-uwPaxq9Rh_@rzh@yhcUf_qJp|1;P%q$qFOY-Eyi%-Ra
zvx?C|@F&W0))6)d>cU8F%*^#+hmD}ZZ`kY>h?WDv=XRfgN|0t#7TX+mJiDa<UckAX
zP*;*f1$!n(TaQQ)kRst5st;YN3Pkq6N7uGvLWi1*h9jc~S>voA`vC2!Mtmr=HxC-9
z7GXM1K9e1>*T70ti&d>36N|4uW;{UO!o}_w{0&71iRuioCJD`wh=Q<x+y~7A-Gq31
z1;+$?l^+dnp8=)hj8=e3N0P7pBbjCi1v<erv8Uwwe>$_CHs;?&QQs5i#g|g5U#!hF
zYiI_Af-!tOJ|DS3oNkm&`yxOk5Y&Ke7HRr|eOv$;fP0Sv+JUg6$QkDkV3%X0?co;E
zs++5X940YJlfD)n*%y`T$CLCOj*CKl4gclODj}4Q;shqp&!NsG0UeqN8V=wTMu@RW
zSLTt;0t)28vVb>Jbp%Ra8bmLegP}@i#+!HEK{i(JReW$&VW^aC<NFD)AW*Td6>srl
z$X#yWcs=l^?-p*9p8#Zwi3B<*!NDcs83s2fH?CS~%Y>hg-5@svHi_|9F<@sHmu%wl
z=pWeVQnlh%@aK_cm4nRtqS8yi*m20v8`U-N<M-RLI#$+IfzJU14djmwM@ps#O!=gh
z$&P1OwK%X3bifL~rr%z<2L;zO;hc=OF-)YssCO(XJK*7lmq>&t)o2oA6;M|Xq7XsO
z4t~)3<it;2!*>9@-l)4Apb@#!BM0;#XA|R*oOP(wI!6^jW!?Tm)8XS%Ix8coBm$q*
zmZnzrRuC4*{RnIrARMUct{0mK>XAP;dLX$?#~P0Cl_DHt6RBrOF_FBZ&zCEK3*9lJ
z=?3Xm!eoxL10_jbCTyQIzAp!TjGd3U64)}JJmRvyv<Q_dS-QYRp<}V@@jJG?-0DzA
z(h<ObA3e-uj!Dm;p}IC|qm~iH0z0%fv4aW$12K$)tJ27<La~V=3{t})`)EW<Pb2}P
z@RQAbW}nk9vHBUzrzE7{?7a5w7JWx7l7`P>M1MjNxTOyy!O5Z#Bq<<(oFj!M&jtI&
z=YPgo2!Jgxk3Cdy7Q2ybTn->c!&?xc$;GaVsdQZG>}z!E5JD_-gBgHJYPi}EU$gfM
zBy*~0-=czXD1_sI0NkO!q73jGB*TUTsCD~U=X!FkG@dSl9a0vly(tvSN@j0GCzrHy
zF(Y`JESfuF?WW|VE-|yu9?u-Oo`VZ}xNOe}jvNCLtq1_`Fa2kD9EcXsryYcG_Z;r}
zJe$UG)#q92e6)X(`rqSKK2YVoC@{l3L$x5=D#wi)tdcuRu~<X=4DYYnPBqz_*{I{P
zpeSnvWa%5=%Wo-Q7S6Ffl8~3`xGWA+v?AXURwn~(yId?^sob<Lpd|-bg`?%`Wt`|p
z3WX(|fRPaVag4RiF?**w%>T|^JwoQi^B)QKiyPr<>wO%%7x|L89WWATnXDZB@Mln#
zcoISeD}i>aXe;9SCi128*@?E*97hc@{@BpH^+ka2<nacShfhqjx#xN6e4RaP+cR@^
z-NP-y1=T7@HF;%4GgQV}+SZ}ks$eaM=TSXsUAAuVTkn5VVkfIZ<?om0QJHtsezVel
zR%^27<8XK#0+0{rCDYoLvuIiHE?XD<-=#m~x5y83*Q(!Rsh6tD^%Uk6ao2wG@*KX%
ztNh6q{f;6K`X5J8EE3iWaNeZ2OKk|x_u)S=eE9%DH=p4+UW8v4m`j<z6d;l9XkO`U
z0DvotY2ZvomLT-L>jcI5FR-y89$6na!$1l#*KXQ&RUm}%;>c7zYLIgQ(u8&o0gPHA
z6NYh+g&9gd4vg_3ffCnIj<hj1VK#<;!z*zm98`P~Mk=(V=L@=yvfX984B7*?B>*VJ
zzV1$<tr)6wku|740c(N~*&apwwSo-?VwB8b)Y}tyuQD4=0rWGh*VkSi&*We__K8;;
z9I<wH<DLfofm+u##JoTj6r$6C5>v8-d_X|X+hT72&739&3?nBC3?vZhc>lK{KQyWU
zb?dkj2jICBfaQ0PqHwnvsW}Q|<L^hrCOrwMrKL7Oa1XGRcqVWwL%g>Kr4fVtWC}*2
zm`SYw0BwF9m@TrkD3(NldM9gge?^J7{>Zi$n4QefPOCFD#EM_A-vIv^F529V=EMbA
zCW92Oa{^WB;ft|uWkQeMAjl0@>G&2|?_7UD?5Pg916-{^P&53DYUaJh@K=7$0~XLO
zn1l)ePyt+QH0aN}Fd!gZRi*hshTabYT?Zy43ItRhfKQv>zRs~(la${o^X7&XWXe_q
z#ti4_xP$a<D1h|A4|H{w^)^kF>UHwTSvEdp4fLc;y!+Z)XNR5XIVf)AAs4$zXz>XH
zoUGg7vy&a`tZg;R%fn>8<Vn7py-71!B;->K@GC&kLr|&w$&e4IT)`{B%VOQsYkBBI
zV_=zuw($htge-HZ3m?g{foV@!ej>FcN}X*uLaCM1J1Ow55SPI-*BW4D76V}EE4^sg
zlS|I=aoqks(pf$&kV1fE;$Ri_trYAAa9#*#A%*+Eeu$|6fw)0tS^o`^j^>6yxEg;N
z!8A94x8fu)0a5V&?>`E`GYo)5t~(+a_U#UP7uba7D72sD$B^nX+$%>54D2D&CN*Gb
znWa=wg9qw?ld+Z&(8#Hk9nG?YN7l6i_IkwY)&D(c$<TpN1hRCWZ<XA!=gOne#TD59
z?;;QcgA%BXb~1h)2XK;5fUU-MX2aGUvVP|jaLcZNyY>})@S3Zap$eo6*ObHDX~T!M
z$u1>Mz3An26!^y5ob&sbkwte8Uc-;SA2=&^B`7m>_C8cN?tn~?i3Kuo$c^QUo!suH
zRbHr-QR<*=Uy}trZ@`+s`8^JmT7ZMl(W8L$-a>8GS=u8abE5Qa_9ZkM*<*KFLzOC&
z@vYRDJ-l+PJb~?e99dBu@QzBL07x9+B^eXkN4}eMd~dmQgHBoNtgpiyHZmkM%FoOV
z&AH(FVtH?rQDb%7L69nGYUgycp}|})?p2=g9umG(X||rShaOLHX?y{&)FbQq{VXuZ
zR@69DrGwE4TNat))a0t&Cmi^HH~Crh4QU-JbwI0I#)Y&!6CRJW&;c-NI@gDJ`4)Y}
zdj6wzHZ(9yYpXqc4V{Y0<>Y2LK3_yu6R-dP6CY_+mwvsI?SX=9A>m8aLv6!G$473p
z3rqzl_Z0YK8)yjd$Lb$TCr0_;KmK}MnS(8kf?f3KS`06wwfr`_ja;U)^h@XhAhQtt
ze&q4FRO%0n>=NqnVVL9soo54c9OV5f?i%pMno4i4yd%8W$PK9FF?6u+5hsugfmg#K
zHz>%)xfj@B^)j2{^SFcWqoUyD+biAb3_jDiVR-WIkavh0V{q3xIck2Zp!{3aRdCR-
zwB=KxjGE)Ww&Um*r3{_-2$Vel{qq_4;N#%_T;-hOsBb7tIsMp07%|j)ewo5HAud3~
z#WCkA#pdSi$*E?5FX+Pn*cvWWhhOh)s*#$t0m>9go6Z-5nF_KiJ<Z7<LLo~~0iAtu
zn5(`+X$LDY>g#1wIj(-q9gDn6ZDm#93;Ru&W(2Ss)sPo#Yegf7lMoIp^gw}RS+C#b
z{UCTE;>JLwHh);cR1)sC2^&2U`tMWTk6mGVip@ZYYS&~#05Ba<5nzL%h`<z*2y2gx
zTE%W<FNs?2Ba3yq{r;iV@$}2dhSapUS=pOXhCv0EhxE?O%8ngR9F4I{?7tAivaNU6
zsq&wbo7q>^Tln)0k*Y}C<PE7nje9+)V@lrjD1e*5=s=-7@|8rfwKPC)G!VmD0PI|r
z)p!qmaOtPOda{X-55|Zl{V4dT2{Dyw&Xkj*WfZ&t#lw~Xc#T3z)IT7cHM6=7_X)lD
zj^yU5xz<|gBMx-@Svy&|S&nNsdO}9QfwFQX9)1jMAe#1Ilfo}1xnVXPg$=wx_>BX%
zqTslJ$ssGI`@c0)Ha($xr`~@}!y?^<!bIOK>8}KRA;%Y5qGn2k*{Wf}Ar+EORX3zk
zsl!P@z?<U!tEu8fYHhT_iyLZka|OW%Mu7=D?jV-mrD&2L%)k{_tL|Y`D4|*?_)LnQ
ztT=D}mdbnP(Mr%MfOicL^EL@wQuJ+<hG!{kfSy!tSn9jP_G9Pat6u}q>G|6**cbsD
zW0l|&sE^3h2cGdt;viH9-UW~j!5LIK#)w=MATP4SJkN5I^>KlN^w6&fW#K>wG^irU
zoI#i)DF!Wi_*In4P~AFU50wt4zE@gDLjv@5OcSJos>!+Lw<T^-LAWV79nfarbSz?q
zyQnk8kZeIV%ROR@=8{jBk}sB;)U1v3<87BKgK$hj7r*>7FdT?fo63PW4oVCzhC}Cm
zC6CrsWH36&`j~x&GjyZr!RYII&p_85Jbc*!a^A{jvx%oEsP9w282hU1c+~=nv^>;&
z8f9og;xrOyEPGM={^j(N%4C8VoWeM=5m#8x>M+lBSg}9-)<nvE1C8>A?PFqU?j;mN
zK*}n<nLvZK`z+I+NrIB6hpXaGuZZc@sp|dJQsSd^k@$$YtEXg>jb-#Tdl^SYXvV+1
z_!y+}A+UW?J6-^zV3BBOe{pE>GwcwReF!aoY7_QTY82SnhiijP3ky}huM&upY#?X#
z@hCmOnQdLMDdq4U8>dz6yP71<pg~p{Y<EXTM7c@LSr*Pw>p*Hewm#f3UHwjJs`_`O
zf#2f^VV6O(e!hIV9H?WL3RV}6VBmgQdB%*vI)O8k__qBVdN=hMi3cUOrGu|;3E_g8
zDuUla^%C0cU6Q5Y=z&sjaDoeD5vm8XpCBYkaTEC4haeiBdR?v{TA-cy2FbIQ<%jcY
zBSJ#TaON1wC@(haw=r~xiEL~J<98bvH8O}So9p8dKz52cWu@DW%L`VEo3^*FTm)t%
zLo0_o7WAR-R5-E})_0P&be1P437e`;xi9i5E-%2POretI*U(E}G5+G0e;#z!f>%Ko
zFheGy9oTeFzDn~##%}<o;8MUJlUpG~e85?O^<kIzJ;~<%DDy@Ct6ECJW~hY|O&W3@
z7zh#-?ZD40)P?(aIdWjajPQLV0=lzE^5sB(fI7O2g5mdtgI`wer_-KJgw4@W2B!_a
zwlyXV24YdbP1+m((1?6hZv&hScM$+FY<}Ecux!>Sdnv-Z#hlh*D5+P_2#Wwo^-qv&
zewHVCAUx_^%6UVWYyM)*hU*1n!T{qO6ALYHR_Pdv=tz7oaVrOZ1uCNt6$lZMYObYh
zx`B+FgV2447MjJ8?}4Y0B{1|BxGSY(jn%Aa_Wt3UR@@z<lBApz<}xY{JRkh)a0s~t
z%|JaTLR~{gu}hn~Xoi*<LoY>EmF2WDdg#X#BYMWvN?}0yI3#?1%w)ZroX_#&sN|7#
zY(pvrikJe)Z~Q|CUR{;c@D|#5pRJ-`LO*4-9JZ}n=Q9Rq<f&_;c4A`Xdf5r!Hidz@
zz}+>JCMv-g921MJ(;?B9>zcTE0378PtmktaO)q$V`N_-bS$q+=1+o3I<{BeMcq>VH
zAuo<$^WjK%BHS&GA{tReSf7UgNINQZWPSL6l@q>1nkSYyHX@J9#-*eDq*}SCqJ~zo
z2adxhX@Hv4o8WjWu!vZ;uG|#s;o}UB*6~~k)z^;s){OSnlQS~&1$H7%vhYS^<$jl*
zA;i-MXfqNMVBADU$uLZinVMJs!vnMpfSFf*`8Po-?tU1Q=uKcN?=GApL1+2baaMdu
z<QVt{Ju+nDGNl1%(C-PspN1}3Vp;U&Tjr<%5^$1a#cFbUFI;x8@p8`VD{u(`EkY$M
z21Z#|MC6dD4Wpf2Zi0W2AEZNk{H1|(*6G_QW)Mu`NDV}lGNg+~=h3ojH;VWEj4bZ$
zkaaezrD6N;mP$uDrrjDloEkQAMyt({8OJ?rs3ta#(pC7>d+^!IXv}C3XF&-qeV!2(
z%JL{CY!G;x$C5rS3>E(Tf2_TIbR742-#fcnGiy~&fZ-Y$BRKTV?Cf#?f-is=6=8hb
zox$v40D>Zk;PT?CyfLv}P_RN(BF(C5j@#}G2H*e$MG{35#8;;QKuCsll|-bORK7P&
z0C*|EHXTb0tIOs%wMf%8ozvcuG@GhDzBl*t3@FF#U;X1QLGT6p@|)j0zvuP)d>_1A
zLn_Wj8yC@6Sgg*wj=k6EzRqbEt6TS`NhyQ)IGK5~B_TOPLUa7K=JQVeR$f2uoN(5h
zKKL^WCvo(iJNBSl@9D>NcbuSSed@*NhWn$*j))ZgWD*cFap8`EzVGX5&}p<*%B9N_
zN2_lQn$MXg<dx1_!dppreW$ne&CpNGH~zsVe*ueyD1~&Ys78%bZ$A^}7R`!<V(c^>
zr!UnPR^<@5k|+iA&czrNDt4QmDJ){t47zd<sAaeODG!1A4$_3@JO-o_`G8)f88B8E
z{jm)wpiAjH?4f1$qyxuk&#|4yUR=BEo%BB4U-FJcXV>p#W@lz5c`1NuNk}u2GUtE1
z0(9FoKM2gN-juM>PV6*c;tcnOQ$h*lot(XGGfp&nZ}T$UT9#ajPpr<_Ff@bYsP#-x
zaRm@urf?%?8u*pmoQ;z~A}?uJl~Dtr>YCd<VZyey+jHQ?{rdR~nPeo33Ob5#zVUg|
zD_{`-;=!z&0?cyFasR0N6KA?->1_4II`z`aQRA^_HSW^HF<R(A8euS4=*X4SH7DQn
zpy2euTV`?P+Y#hDUd&Ld|H%Gos3&Uo|HaL$&4_L8e?d&5vDiquoJ6Uc2_<&LT}S1{
zCpk;iRB^j!(5^^W-L4l?^}4%@8H*y-J|2h$dxE3kAT$ghY1PqDjM8?eL317};pSAm
zdXfF*%uiCDz0j!PN&tWyF!aJ9S1+G*2TVFT3luDnPrEMs6#hN6jXrJaH}6CagCsyH
zI}R|4B%)kKiB~c2<mcjzMdP62lbi^%0Am{Gfn(r+zrZ4(|5$R^K!y$&<N;%=nLUYw
z-!hlNT@$q6xm&H_(x|ny8q!+rkruG=!F(A4(12&F8s=@%6+Pb8(H`%mw|Y?Z$3D9r
zu9Z?enR`PzK=<$c_1g{Lg7`%ilfWlsI8L$Zv~kZlo>EnEZ0<fw-B9dC)?9Qe#?e8J
zZ{2l{gkd>7PR}k=W?ezw2*9WT=eBqP2hc5oxT$Wf_Kk*LS}J=KSEDaX54mLa!!V5b
zX-F<RQbaTPH1p5gt)uS93lnSM1RA93?WMPHieeL)`<wS@H)cpd#CIHRtfZ@y!<2IX
z*HCiy^560>yxuidi=k&dt5@&{57gy{G5c{`71!M!PajbS%RSaevwJccs=FcSbp>rs
zeUHTh&T|JUcIgnRuu3(u<TRyhyWbzR6%5w#pZxq7N|{)wgCmR2%dv^8VL05__*jXR
zIR99078%C|@xm0G@IhHwDNSwRF$}Z63b=rTQ=>-v<U*rKB-p6u9cREPx+f<n5e&XM
z;!r#HOZ~UKVSD_J-$;fE95lLd^B$dqy)Iq}eGCJV#dNn*02y?K72S<}%gY(*gVRx4
zzrCYI#vC;79lU#zrT7XP%3taVEE0+yk;D|Qi*thUdK*%#U5?B6U>(xUmowjN4EISZ
zb$rz%)u7om8BZtm1-a--=};v<Sp9zAQ}iQcq$JoQP!GX;Y@w^qdDFTeCwym4zocH!
zDTbK&0r$B|#Tju^Bbki6M+y>;UY){+^>=SJL>O#95p&uTA6T$zb>V*I^NCR^b)+xd
zhmj3?%JGqdWo2J=QMajXVUz<)BV2H+SKPzv{r2k+<^W7$P7R*iL1Slr;o}F4)>-G6
zb=%U8TKO5LG_+)bdd%FIwoig#Cc?zm4w&AlH|G{Qwm45+95{(0-^DKPwVw0-qB>OG
zR|hHE8j&R4M?UL)Ti7UwN&jH|v1W=e<X^UsZEhq4l^8ooQot&jj+^RFp-$QChfU{z
z4`k7OPSxp8mECDb)5f)yt1Vw!ZPDUxh;YpAk_=9}PoZ(m;hfmR!~2}liSqRyxN39i
zN{hQ5ZpnP@s}%7lHaj;W=<JMU{i1PPUF#Izu5hjL9wdQg|BZros8E`9i5xjGb4@fZ
zX0SKS_wEfqFNN$=IHtahi=WIcm53f=X+=6H&<MVjNJTcfE#Ummn~vueQg$DLZu_)G
zLyrTv5eG*OXpy<mI6zy?+F>{r`%g}&N4=%t{7hIn?1BU;wJ@GIMk1aQo9$N2TqbFh
z9t3agjes0%4}tTz<lsrM_6y&Sv?!`)Urq{yF?@JP0U3FU>#n$-oHLPkjy$4(YCr{G
zq~3S0xmCxrd#G7Q4MU;5DvA`&dA<~cR@Z5z6tr`B&>Ttqa7nU(Hf^o$sYnS0x{e+Y
z3=N1MdG8Tm5m3MlR7#h_C|z3mo&B~(F^qeD@2|eC#H#{tH~>mWl(~^Q;+9jKDhkUK
zLy0-!&12EEO_f@hVx@KJuvcC1>LgRa>@p36K$|W}$8@&WOPKBb<_$9gvs!7$uu){d
zd`ge`AdD1cML67XXwVfD=E~1bd`=s1bE8(&@1^L*wuMkuJl}gK|4WwW;0`B{T0jo0
zH=|b=idAE``q^TMHORgcANIRrgP2TMOFiRUb}5IV$-W)Bkl#=NJ+GCH`NX!3-iw;N
z%ZduAGqQNVv9~+ALlz}-X!`Zt?rJI09%RDadlbJx7<NPCu?Stc+WHk^wUQ_Qf6Z7k
z++%{k;x5mU00FrfqAK?KU!;d~q2rhCH$V|2Sy9~08-z*32akYhVL!WFlV@XvL@r~x
zG43^>0t;fNK6aG#azV%zZRFC3Ab308N1Pit+@4ow9Mf!tUv>z#`2Ir`m-}jrAL_rN
zk!k!o@Dj=`oZIH_`7>5$r)F&XwcIT|r~kEK<nJ57KM3uo>Aem1g(FV{ZlIi_s`!u(
za-rit{-2x1q#h@bdeN_ztpRV-DLVQA0)X_8!%fNJ&~Y1OBAJAg%x)?^Flma|#St2>
zhRRAN8wbhsrb`k=sln63%#ZiM1$SRB&y}Aomj;fS7wYBl7R`&6=iISY9ZNJh5Vb8l
zZdlt+>;OVz>O`K;n{~tPA1b>DdA-}b<9X7UvERNJ;;|yKrEk8W*)Z*)pb6;kJ!|yN
zC$f4<DQ`$Fv5@FvL7kzZaQZx=IaIIcXjkh$JPl7k|CyF1@SDujJr$E<C<6P`sdi`Z
zPp%ulrrks3Jg@_;+}HBh>b{mOnWkerR~mUHFX(N_=3rs7lq;M{Vcytbc7LJpTXa@q
z7L44GleGlw0ouftsQ%m3fy9ykuPp*U;~M050=JGm?XR<~$T4morVKsBVM7fl^MyC6
z#LNNe>nHu5dx~Cw`W4tK_tC&JDQa~id}Gscg2*RFY~%TNxzCw576)I?Ynks{{UDm2
zzBe~p`c#BUI75<Z4>=w15uE@hx9LZ*yE*l8LG27jP6Q7^f~P#gO!|l1+Qr!)^}?Lx
zv&w77lM<#-_Y>|-3TbZ=$g<&>V5Zz3anKETf|-<@!;Sq$gP18I2^ZgcH@;21=xWpu
zZ+I6ob_N$9e4pE<`B{I}QMZ*$Q`g(!>>emT?Ui0A58mo-8HiT>`nR-_NHt@g@o<|z
z-{qzE5bpr1Rd1P_jVFwqrt_d0_Vm3J?l*_Z$25?_IC?46hj7bi>a!DcEOyDM5FbUH
zhGsvwzzpd;3Y5dfbCC!UlAk&a^DbSo`^fGh^E8VK+s8V3&h4Sen36T8guD)^C<27$
z<7n3=QLzLX`6tTdljZwvd8_%k2i}wPY^+}Sj(2g6TKT9y=C5|03Z^e=#$qQ;Q@P|e
z<DBu#3F8D4AO?U^xX+Ca8Be!IPAQD$GBX<GN8-W%=ZS0r*aq4UCxY~*U@1gk#6ycc
zY-B|d-ABMlrwLz1%E)4eW64MOTOg#WU*RuWd*dvE$8ci5fo7TZlLIr3;~}N}>F%Mz
zPAmP{p;zBtcHL9!S5AiBr>1EIMD5TBdEe@qTrl<+_f(_pp3{jQF?JZvj>3+miN7{O
zxmkd6MzAV^&F)@k>=rMu`Tk%2?*wK-y{?kx4yQSpq=IQqs*%S>W8<=6kW=FK#(o-E
zgtin30kB%7DmUd*?(;Yp_0p{NHK}HB2UTI!5K+WkL)c+Kbz{51Y?l7(M^C!{()$vY
z*(=>}y$@c-nb|L{7sC44F=K4OXiFHHFyr2Wx$KtlN5+~t@<L(I7~!sZTTS;Z5b)u3
z_eY-p<}7adLdUnSJu(J7Q1TsYLpVt(l|nAKyG^KWNxTsmb6&+(%g*CeIBq#b(as4m
z@ZstK_ic=r4^N5IoAKE6#%qS1q(+hIajTf^{z2pW1AUZu!B}OQ&x>`ETnxlf*6GdS
zukFnJ*uXjElp2P0Y;I|I<Ph%KNSR#4-Vh+4d&9*u-s`jFvf$4w{=%3JY0gc-{v)9l
zXnsFQrVf5GO3z3LFOjq%8~?MbCVyVTXVcPk>OU!xno`&YaD;>>Bmmy3Z&#a$g9Z#Y
zug;LREY~6bap<sts9IJa_g9sm*_ynh8OA~f*!Rs_)SQ39NRIAz)cb|7*Bdm4^?rOI
zWv;nH5@)*q<3IVbK$}ABv1~H-t=WGBNMnMKGA?|wxy1}8P-OeVO;&&@$ZB2SSCo&h
z2(YPXcgy?Y8+648L-+$JOSBFe?e0-FsWMo2-WfEm%z2@|FC2e4<2QYWlPiFCxUc~#
zFXZ-gvdgWjMh>IColGFA#XNNM+4{2+!vN4jErn+ss^X1EVOam&0@*Bd5jX`YW^reM
zHPWHPfs}`5?}`ni*vN<5ECxQ+onqnPYQ3ao2K&FI;ooq@C?#rw(ufKgTwhgNUD!>#
z2akHsmKnAU|J8E7NqfvMeTt{k=Y~Ar^e=Uxhha)-WrQ{j9RT%L%7!)aTj8^BDI*lz
zA{+C*w~;I@AT$5||NC#wVbPhoE!8G+OtnQpSb)tI&j?u{#ZXLb972qZ2O6P<zE+Tx
zSwcL&;jt^%y@Sxp#|+}2m`O^5=-Mgdd-)($h3K_D@vQrFwQm33lUF4qCi8xpYBW-b
zzS75%lexvtJ?A@HhxI4c403I`nNSBBSA8}t?GCE_9zODVX20jpWoilS?61>$ERAsz
zlv0Xkb0sN;!s{Op&jYg#fQ*&nG>cG(qsNTa06jt@m6=){XWwy1_hmSHgn7*rtP+yn
zLX6vq+Q?Qa+Z_(z0q59|`K&iQeyu(fT?sYhsB{wBAjOt6wZWX)JT_xIL0xXUA)D-2
zg-gZ_(|aLM%LC37u}AQZ2tVhVn|EtG`F`9FAq6ryI)v5o|9apj2$-+C$rwN?yDe*$
zZ&V3cG;aMn?reW3-XI0aeHk>o%5hR*gixF9wSn!bF3`8+KG%G@`kYBi*A=fBBFe)=
zOItF&)U5ojH>|H%#=_%m4~a0%9iR%^uDi5EpKu{X;;zg%-P&xZ?ERhny?$J`zn|H<
zivx~1g3U=-3`io<N-MK-#jc>4<8&ErQtb63!lYDcDUM<pEixF|<H+%Jt)pfCYC>jp
z6{SLhmq+ZMPn!Arj$0c%noChKZhz$v9!q4O(Y}=l5k=9aPrPYef~y196pXj}74<eA
zHHN6-Y+vgB&GLI?bA3Y3pA73EWyoQBmyq`Q_w2u+vP~8AMWOAY8Y>MyqE{2-D|qy}
zt{J9~3&Bmw!(-9sOz}x1j$U`KxZY#aHrnK@pNQ)+SzkY{2L7-P&~~6wY`W&AwgR{+
zY3kwiNiPLxNb7AxPpo%6f#s!Cuz3fUw^RQ$BNrIAoaEC+r8Hm+=bJXIgx%V8_sd}I
zKM~8r&DoENlfXL11Z|CL3Otl!*SugW0ymOHvg9~)k$<sTgaW$Jtk@L!G2f>V^>z2^
z@fOz=h3*Th;dywC{DS~$)OVmLaw`BT3VL<l)JU4wwM^>=>%DSE{mB#7awohNa7um_
zKkuI#?YJBLm%^FC)8+0P6=oqoCuy(>SDH#=zD`=dKKX-mjL7ptJZk(6@j!e7LFVq;
zhD6fXJ&_I++lCP1^QGMWR2ZH`Plv>H^{?|fT=I~5m7Zw2rC$aSi|uFtS?mlt&pMy2
zGUQ-<sQ=V@Y0y)P5Q3%8Sr7~)wXQ8hvz@SO3pmVp&T!Q0=3u#6a+1Z_kOoFU3^e}h
zUsEXhGYhO}8Hr|^OjsJuP|CH%2g0NH>DnNSA}U0a@eRZdopA^H{iaMxP#6ay$WL*7
z=H2ZMRVD(t>PT|9+Oz(O^JM?wtFHF8-7rhf4Sh!1SfU1|cc*TsCybd&kJIB+x6}Gb
zNz9ZCRZ2RNI$|>4-)?Il1{75rHvxjF!btc@MDpSNj*k>e+%OE%lz+tGEo57Z5Z_!m
zd=>abW_L@df*)In%^7MdfvZz>N8WNL)I;X&KL}5H<t{o)rh~WbW=I9FMEpL3ZyCbm
ztj%|5+dEC8)tNE&g}iLA>Ta#tdMULM_M@-1#01!PU;B-kj*dMionNq+ka3n-zeJz0
zPa_WeLtO>d9pQ|H5*ImL!V$LXr)lEsW*p)wAUE6={Gx4*+Xve7ndDY*i#CA87bXbI
zzu!lmbdZzZ;@7)>C8jy?KMil(7(pd@?%aJ9^f>POjG;VTIW|-tE)ivILcGFv!I1A2
zJJtN-|9O%C0}eI(n&TSjV~#!P@fFuDxUyPESJ70+<A)E~&hCusrrj%AOI<r<hv+x)
z993DVb`F24lq4H6;Mg`2P#iRW80AMp{|YoX1nanBQeL~L!Ap9EvUjHjqPUeLlwrV4
z-+sqY2T7v1`RnDOf*YY7HzHDWy)5?lKd2>W*^$71@?ux4XmyT(^bxGYLLjDV!*%~~
zy%;o#ws1A#p$|nX8Q%r-6z2?N!2*4UiLLR7nGZ5>NDowp?U6%;D??7`uLj@BjCEur
zh#C`fc{YHQfwtO3onEwS243!rkv|GuqXT3bwz-nSYQtixTPHQy{Num;$F!5s=qyZ}
z;(SRsQ;RYB92i+9wrV57_;9I`u$1M~;!ZQTmR@N&WxE(F0cxs~knr#p`88MzoTOfD
z0CbJxHL_*MxpLUE$JbkYTTr96L^4mnwYI2s?zv=C^xS!@Rl9M`xn$likeYJygG{(c
z##SDmtGff-^Md}|fBrdE2%_>P4r<a8bJd(|9$(Zw%j@6Nn*mwLvI*?vu%%?}^Z4Y%
z8p4*nVje(A3H15^MEYr!3_^yO0-RhTM4q(#E%45{RfnWQ=(ewy^^x*>6GIc@Pr2ha
z>O<kT!sgZ4kWUuo;f34|#_)C27EaLLahzNxuqUJagjub8uI0Mpa>?S-P`l-^msY*|
zU-+sxU=m5ttPy{l&@&L_lbPNC-o#!Qn_MGt#aWXF5iFAuH9+pAt`;&$&1{>9Fq^C=
z+G&Q+377L3sD$0mdGA$+3^eMv;EVdtWN7h$rGQ&nSnrz58T$9gRO`o$fExL+6Xxy$
z*%$mTl3twZOg+<!R<LX2Pv3q5*jpTeU}7~7<)3H^@(agDu}k|*%kE8~Pr=<HuW`H?
zuh+tnjI$S*vyf?+S2Bm)u!r8EeV`45FBZHThlBABV48IjSIY3nTAeg|c*^>{C#SoB
z=aNg%w#@bT#93;1YHadS7u+sgJ9AH{JI(LYw+v2VrV{NmocF3Pb8GO1#J3)FwY}#x
zi~_6%(<#cC^NqqpZcY3CBefi7t_C;u!+HSWri923<(Q-jRspYoLb5k_l?coqznpnD
zlvWM_WeJp#rjzrk*AB;#`Hqn$<$K_$ZGQi$wSAGlFDku^D+7fCbvNyFM@(zosj7SK
z8=b8wBBh<iVg-&e<LL^{F=<&{Zgc-Z8S1Pjn*aP$X+8v|4LNa5k!o>jniCXDYNj;G
zm3O-i$?e#j@w#};hRDVuQqd5y`G-UIihv4lz~EwcUqlJhyZ|VxrY{^MQp2p9y3YO_
z&85weEr&dU(JO;AR>)0Jh0>=f65ZByT1Q!QHjiC&E*P!1jf$C{HG7`H$0Q$ddla_<
z89qP};tr{6_SSlC%ce1*vLyxxi_0Bo<z_G~p3;vX;~8-DNc;$JLVQIYBxnctUr`|-
zCP=LJXTB4@%Rao#jTYeu=`~oOzKV~n7iR*ubqIIL92s03d1`c$a|iegjVysrj7B=^
zf6WT_TzDMz4a0b#s%_*UP~g?QxaUWmV{*32N!u=Fs&?Ec@r{26@(r#7gbVII?@h2U
zxRDFLsGZ0r3z_R^GBOOT8$%}t;h_l`RkHji_%~#X>Rw4|g8N#U23<545F|St`pt>E
zD)|R3hhw8wTpCj=c7E{I_)}|mH1ve`c4+puWk?%YGOLq;nE^w}wl%JFJ~30-X;$#g
zd%R~0TPu77buov$(K~L`=n}6fUElqsM~YyfX`e~U%ntFqRscVyYMJ_mNJ!=wp{P-B
zkxh>C-{Rv$QY6ID)k-k%sRH0cvB6s){XHs%W3c+{#AmIcTd$<W%K%05)t4bLnQq!(
zh6ZF7EOv@S?lg=S(BBBeTA{~%+JNdnH%m=x6G~*`=`>Mm!RvnRmp;mzE}R{Tw9AZ(
zAp}Ns#b(1*9QIREu0P`@N*sTZ+_4>&waiexK3=s;KWPz#$ka|6vFW6y!)rh{=|api
zu;9gjI>il(O%)*1ch*-kr9URFN|R;yahEkoBVyn~+`=8$nZql?fS}oEL}EV4@NgLu
zjc>g#Q%Xs6@ZHCM9;X&31uBLl{+P~}#0+dd(&EavIC3JCh9ov45igR<S=+EbnDRQO
z&HYwJwSjD&XH(-cE`lYoq}f0v#eE?JXKk78_lI7qX~(d2mor~Sk%H*3c61RqEEruo
zNLZdXig4qtl?zLTj=)eb#0Md-t~E=ax7PLTFa3fRt}xT)T^ewK&VRU23@*Z$k_i>S
zV_CJ_c=GOeX6&-q<mm&U4XB5*<35e!0-EY3-+bKV=0-3&W}KfiOQ<4%m-KEI%<$B@
z>`>F~)r*<fckn^wsLPwX)aI{s=7x3Mc+${Y*UbD2#vzKwhmOWs={IIOGTnq?{{8=W
zNBBPE{?p(kB@d~@vT^vclH5bt#@j1)n1__(IZ~)x)(@IAwaU~et?7?7(l)9l124f_
zFeS6G4E{(CL>|^1PL-cm2R({eSEsO15ZxkhXZ=f7ZV}$B&ZZNcYieQ5$aix4jpr&V
z#Slc@j6ZpWIzf+(tEj3^{-z>@P?>dslN837Aqg7gh$}UO5|=?l;o(|E*^-oWyHf}1
ztK)~mD}#0ZMN@+e9^hC_5}5DAcSZvcn7hS8m0`2`^!oTyx5OyMb<#0D2}KJJ<~WUW
zdoFa)=(k<{w9y{m?-=gRN~dw4@>z_xEEVDFO;8*l!2RZLH>6Mb^keD6zQUHOL$b~y
ztX^!K*j#D@vebA_MF$81Q?~jsq5<0$T$)J~-Yg}Nco2?~ry2m9tC~M_lq$S#+I5gw
z!}gYz{oFJ`C4R+Pq^TF@^=9r}<HwysLcIp@!w!^G?ph&*-Y`wYJty$kIGg_WZhlNv
z1*gMFkTf!mB<tkp%l;KpE+UzFxRI=qzjKB1l^Pdf@$r;aU&XhT5?)Ar$V+$XHr`^M
z2<#{~uPUwD-WHm6yn2hefAt~+HG-FJ>VoyHS;xOU!B~}djY}%1oWL;#s@>Qavy|Z~
z$y2<<DdnCw|M{zr!UM`ZpyTJPzj-L?qTXS7mA*xzFW4l*Axq}0dzZaO`-{<%B@1i)
zys(m1Jz%a!UEX=0>+mBXo+dZ?o%*}(LHFxqSh>B7z7vC@o^zxZp}gn{(CN1MlX^JC
zzjwM<ou}KwFHQem5S|IgAB0iqkEaj9;E%>TqfLL!g8r;iQ}<N#o%ze^A5|VyBnrLe
zd{7N{I)5B|$NW_IQn(eGq1JW&vO+GKiD@ARZ=vIdzp_if3zU$zkjnQb;enLo_JXc5
zio3F-T4Dq!X!O1ZE?3!|lI0`jA~GZ)DS21tV?-T4Q%w_hBXh^i$jF<)uzPrQHN=Z*
z5)f9Fq{w~M@#O00G6>4E;dAb7h<G2AC-&cdaFw~YCm9n>P8A&F+1{^)3!m7<$%1YW
z$9#{z@c5_IZNHp5UV#$YD1(6N@qVNJ99-u0KdW!+fAXz0*pmVw1O4jkG8q$aMrZG#
zP{@4YF`o6mH+I5$)5_&8JZ{bBNBb7t$`RM=aS?aQ212kU*Mv*N{o<<RhHdJbIO)#1
zu0z^%(0w}`cgap4t}`0?y4%shV4V2yb9NEet@=~nhlTi>aoM?T*5BG2J{$JlZXY`O
zw6{cQwDds~L56l?ov3KGg}fNAWVa_5J3DKOm1kywh2!w&X4m%j{YBv?L9lc53*qJ9
z<zONhg&7$K8L1#stXO|@<&pSes6fO8KfFtA9@t}IPmrv%{lK~9{FWr~Z}ZC(6(f)M
zWY?1P`5c{hvY}gbOD6>da@u{HYp$>I{%^E&h#n(UC2nWS=oQS<73N-Yt~*t?9deyn
z=g*wCPWJuRzCRnQdgF8qE=PMm5yUxb)Zgjco=0eXFt+JUoleehf50iKJn8Hoz2knT
z@Micx1~1<6y26Rw;ojew>X^+Yv_Cz}aY86mKiqRGpab0S$G%iz=IS$HSQp=khujc}
z4q0JbiHgrsTgbQ($mTrvN%x2wULnA>8(wZv55!C+<bKA)cz9a|cIr#^HrIU8*^boi
z3r1cDGWCg(7bk9v4te|6hdkeR-{+ZUu&UFKcTJw}()Nt~Siq;|e<C|;s*6tB2jSAT
z^;ho)Z!s}$qTSMhbcx^wt%QYXKJnfo-1tes(u3<m1NpogeoGe8EBEM9g|W{kUAkt0
zG@j%l{<ai|c%`06)lPC$=H2?3`vtN?_=Wa28yPhf3ISa>MihVr1NIct?BuEERWm?<
zOFu9HrMBO`eX{??^w2uF@t0=R9)Tak)$!&4j)G3+0k!(*T{CyTf-75i*31Qi#<o!R
zqSDE5DVn$(>i=bSw)>+PvhV)I-)WWxZUEhEgf0|{bZe1sEI;*;zL3yB#839WDE>H^
zDWpj{3u%BFh0qmS!3mP911Z*k`tk|>#iJ+Ofz0hZP>h}VR3A=Ff0sMrUMpy~yrEm)
zTb~N;`Z#n>2-_));7vcbS&J@gUZH0D%eg-{cH@5kwK1`GV&a9uABF3|zCZ_FB4({0
zE1AhA)X&_1%$Gd1P^RcID;@s}>jQaS*12p#d?TDda(G!?Oh6Z(f-D}cvCG`&7H+#K
zr*v7M%eXmVzkNMQ2-tGmvMqvP6R=s6gPZGOJ6hfMs)x-B--)`so+zBYK_cl#{_&PK
zF(b0+)+FNFXzf|t3>_7WF&&*!5hS2oGVC7bX;<Iwj#SO<6SeiQJ8i2}U@<25zVX&M
zRKN!WY#iki+MPgO=*$}aQc3k{EI8hE47B`BjF4m=<QKIRH=BBA<4oYfO&5pOnQOKr
zsP&t)B2ZbCy2SfH7Y7EKE;*Ts*{ZqBKMa8oP2>-~M3!{jzA_7CT9fwgMQ*jpYc!*w
z@Gq+W$xxsA#cOyIeLpa6xE~bOdYty53K5%K#pt?t>f|2OyD#1%a)TpM(z@ewoSs@j
zk`H%HvjiWRtegO?C_?eDSS5>R-?Krg-+kS!J68aqxKskU^2B%-2?)*&xO<$RtvaLI
zoK5+rCU?yl8G5a~%Y{Pxk416LHN7sd9SuOQ1z_g_EbNWjDF5m^b3&_3bLRn*B-Zdq
zs(93maI~+xkk(@cNJ9L}zW_a~lIBlX<9CA1%Q{IAN%)~vSf}i=WTnKI@k=p47o<GW
zmSVyIa1D_GaZ7WW`%PxXbzp029gvT%I<5Cq$MnD?5*Ft#g+or>88Y*S*T;vZOV`5=
zNX*arq!-1cZ?UGo(zVEHjcuRbvoM(B#>`Y&Z@5h602x@?G=hh6$W;(<(em_*|J~2O
z!OO;}&<ja}xW!VsNnoD@AH>Sgj2}uyEZNiwyVc#Mz-j6*|AjmS-QIoEei!y6$=mSd
zqqGhhF)Z<bQ7sM{^nu&?r<Pwie07qX#Xjv{&fX2tW`fs&=Kiz+eF5=&2Q$TT3r4G|
zE*kl=TP74Ts%2c<dPeQ%%u(O@<X`=qDp&}?3{O^kG98kaz<G~R1hN)(nML#9Z{TJ`
zmb1xuxAu_o#15g70l+oh)nfO8+E&L%4v>b~X0IR?(liKL=uny82JX9|mr{NmR)?$a
zvd@^)cOzKs^@R@ged8ahmj?daxNlUp13{*xx@wFNA|!DJQ3sh)n4lQ^t6yM8IeH0l
zby8A8RmC(Shyn7zgY3h`t|AjQWPlPOP17IZx|G$WV<H?A?wSPpMh3|UE)^geey#hg
z<1XY6_50z0@awG*u@S~FX1NPtZM)P7*TtuebEMIMHf=BD!GF6W;1*+RSGAi6*0uSL
z|M-XEPtd{tZX`uN)P#7$LeIf&lCF`Y0?IfBAJI{tqP!C`N)R5Wpb>`OrUY+&CKQqr
zr~@z~9IGZnvQEXz!4Ol`^aIrqCsj(9u4cLqQp6%PJnG9ZVjPJzwe6z%KM|<C!5$jj
zmC9D9<Q^)FFaw2Ua#(iLw@^#`-=9~ebsbh3N%v>t^NR{#fid5w1fUQ1kN={`iXtG+
zKnxC3kKkyA$1`bCVogLo3ET~n6%zIG36xAIf{;rbirn!*D2nw}s-ZyLIQT}JpIcCy
zf6dso*;L7!n}u0(Cy6{VM4JSBn39mz?QVpcTeZH(;BU%$5*83ph7=}zN<Az}VhTKT
z5y=nlG5<?=X|uVmGESG<JJGOhlRp%{nzA0jC>Pj%54VWC2ig5po^Y~~A6zzpDf;es
zJ0m4e`Oj0-`#_^z4TvcWlpSp5iOw11e5VndC>(NP&by<-dE}ogV<W?-5Ip!oc5b3%
zDlLL^`oVI>Uql+Y)qIHxVr4(wOYS`XqbMP;QcZgdhhdec(+WoK8;+ZXUq$SLu#@S?
zl=+@_pE6$YQp7uZA?(uW#J4}tx`<fSJq$>`XLN2?TQ^@b7GcIq76u%>3a5?RgwY9a
z+Bfa^aBF|^Nr6;Q8w~*p{94rJ>xRy66HK?%L`2cBN-8F)ST+?o+Jpp06}N@~X0unv
zH9&DKb1lusGee>Jyp&pfGzAV0MUY$OZgR42FdLL$xV8n5QaWtC^6OWxcp1&~VP%%s
zaIS02M}@+KXlxni%vE!JmkhA}mBm8)3FE!0q^k?V=ubR^n<V08B<p;~XZ``hAPLqG
z9=Vf}Jd^UHoG;orpfGw+HA^R}EZ?4wH#;uuvA-nExriXumNFV<-E-6lfewuWG~-&s
z{m@rk$7P{YSh`jT{>jU!^rqw?i*}0j@^HV~S$3Z`7sjtn*Wl<5NA1&}@aZCfVt*hK
zlJPy?Gw!QuD+F_fvxtD4aAymp6V!|Mn}?6?b=zOWuR51$dH_b9`%9nJ(jY}KX_W=i
z_-^!T(b*tjsC(i#xuP6FmPME)m9wF_SUuQ8%otWs+RtR!Vci}-yj~ML07)lALBn{D
zp{Vnh)P;kT%u-O;Y7fFSeXloisA6^x-SXdFFZH{U#%2e#n*E|RN0hlI=U+Gugvk75
zqwj=qs}MlkUU2`q9P~yvoFPMwQE@izW1}GS+lLAM?#LZr{tzJs5QG@`hr5Q<31M`%
zgkChO<D|z{n4no~gLKn)yQr{0zFUUJ4RtVmh2;91nmr4zf*>OBGAV$-z$g4+l!JB8
zw6~Xs-Relw3!e8+dC~Y%G<`Ap(dxyQCEy1#zr~vDq)G0=<Ip-^Gam0e!sgEyF0KQN
zpzeLg(aY!%yHxG%y%@5_#GgDv2NjA0k&XMQAYfJYkn~;ncs3~tO=O28g<Q0p1X0c#
z<WmAsj2|gU`I0ZUugtYb9EZGM6r|?9aB!!7o?)4$?zL+VCf*vUj*dJCg4_D`>CzV>
znj4UN*TW9_7jn#jrIt=+a_g=9zfvzbw~+p8&JA~YaeoECJstabcTL85D6Z=A0SM*&
zFTW|>jHiH|lU~Fhm)siPadRpZ@CJY)f<vsLGF^#JkRjB2tP_Q(h3Gfc9j3~znHqCt
zg8X=Nu|-(1@bRhA9*hL4INw-2A%(fErt6sb&a!FhPn*^9kXJtwX?rK9?}<Bs$X=8T
ztIYO-k4%{9Hn)OXyM+L3FYI?Z4R@b2{JFtu@1WBoR^s_^cShXg+K=zN61OLIXt2I@
zp2f{(*YM~Z5Cig%t>+=<RS3Tvya`g8+!J;Ia~O&S6K;OuoY;uoRUP$7{0aIS+UpY~
ztRYhlhRmGC$t%r<_QWhW;6%6R$*yLDpj2(UaD1n6aX=q7;ZWM?eBdtaH(2Nm=SFos
z&||0tE|9>ul-j+oUm@olv&v~?Fyq5nOCZMdHT5{G3gBw2zhi}tipet5AZc(ZSR?0o
z+5Cn`UL{nV&H8!uhz^JZwx@2`QUN6vp01V%$Sb=^BS-r(UyP}Oupp4o5`6HwPXpoD
z)={`6kTavOW|DWiUP<k9hxc14XChPes37hOvq<$P|IuTpBMjtCKXGKNEk}u;0XI5R
z3kB>Tk9eiAiIf7O2a4Q_i5`k12kG$_V%Tre#6m(bgf&XE$s6kIz@b|@S+lj^ZV;O6
ztUKXk4&54;K>k}=x76R8;S!n8f!KVUGx%wGWd336Eu(7a+ZOx(tGV`^Gvoq-7@_1M
z2{cHDGu*nnhkrS%-}EWbUKBf&o<xH@qIRkAR8k4_*jiFg)r}ipj3pTTp;WRE{X5vo
zYzjxBBh%x5?R;Ff2`NnajmANvDVaavsOq3u9cGS>Ik@=4@b~K7v*Gwp0KDy;>t6t<
zf5-Q8W0c)Hw6<HgM5>18!H%1S%Z1&q?sFy{IBu}N-8EjPwHD3{T2x7D)_z?2RD(sl
zAvy!lBqIbD7<IAWHk)C}vwI)zu$(wi+_Ku*63GCOYqyw@0-}~WmmwI(?9z`)*r8=F
zs{aOf&XV2gs@E#%mx5hE{s}N6i*>Hw_T6tI?ArT&VqP!6iu8Ef*D9TT|GCq6vXX;4
zW@*1OS9sc}mIe#<fr{i*4v3cM#gH#FerA87_;7~$P~>M5Sp?szIoDlL5xlv)zv$q2
zxpMA!WRq-fHpN6PIvXh1pd#p6p}>^Y4;pzK-Mk6}=BRtO?2g<oJ6m1acxTq_-l6`<
z2>kcz#mKfeWo?}}Obe=E0972Od0y}cI}LXRAJH5vc==bE5h1iUb9+Cr-~JtZ9z4M>
zlu*fu6<npn^doI!IN_dG@tppu>%}V+wM@tyD~5P$C7yFwvmLI6VK|;iYg@>{VZ6ob
zB4$A`CfctIY#YRUo96<TX-Wjk)gCYZg)muykD1=51nsDlKn_M0H2D?~=C7!`)%NnD
z+j_s^?3j4%gICR-%7JnoEJeOacDF&=wGf1V@+aawoyLQg?|2JDMtm%>T(NG7!xG1!
zZ0^Q-<IP2}!F_!_tcJ`x3#H6BOa%tjA|5~j7Y22<3chq386sUbslnu5b@LC(<-P8O
z2i}^0X1acMoeZ7(_9VW2nm}&R=-jiYl44v{cjnYv=-wHljm9VYSw}F#`<&KgcA4p6
zo@L!6QAdqH>p8AWlklc>=Utk2@HpBM3iv4qcx9Vot%YRZTf|1=r(U1Zi-fyU<CKOZ
znvrjW__dUvNH9s)#v9H_d_H%^*)9`rJv>$TDBXd-x<Zl5r!*IK`#$rw=t1U)Hxr6b
z!+~XkJmkp9!foj;3r##d7ZhLPZCpJzQ|<ch&P|9jxT8DdWW+aMcqhl9Ink+-d~o+d
zU@M8BC3ziN9or8yGwRnPCo1S7>f^Q(lH{ebJv6=gtrh_`30F`Prk`xb4c^xGfyogD
zP|6&vyi*-Ky4|go58dhsb@)lfUna*wJH*Lpz<nCsDom6;-C^vxpzk@}dCl-=z@VAd
z(cJ~RtllrzOC-UMb#WCdu%K`m;!{B2`Z(bRT{7pHDf4-483Jti-vxC5hF;dbvG`a?
z%T;V-g>bgBXy<)WBs&lu0J1S%KLh3y^)A7&FI~`MSQLg1;Ix?w6tvdZdP_@E!kGxi
zox!W&m8+R%`#NfdoX+WvCa9;N6aMEX3X8uCy^;BT;e>Hn`s51l9o0~mI7>E$mMF6+
zB`C`KpFfR(#!X_p5t&fr6&=!uxWr*TrVHm{35j9hXgg^@VdAng?-YTyXH)F?;MFUc
z^qGuX=RKsA1<;3ZDGE*<&)OuuPQlmk9z#^ihbnKI&``MPs9!ugRP;12*kbL_PBTFU
za@39^`c9+MU~~n+0nOS^SM!T5-6za(k%chp40wv~lObFGbpg@PI(iSi0@9mT^M#|D
zL$4v$8;@9%#96I}`z@1BYAFmMk8yY~nd|q?dV<(y0}U`HkbBCRQq24HI0pv^bqF3@
zPzZ);e}BLjXBpa{wC~Kr*9gtzqH(&hbB}*h|I+4dAK#{zD~7YRvd?_pa1Xh|BTcew
z4jO|f-*t&%p$;;iVt?g;k^7)_ghf|aIUO^Sgga@*?i`4<hc9HEA}e@FZ2UZ$kWD{D
z2<fHIXx*HbL|n!k!@S~Kk<~)8Y{m7U^?18mx>k`n9PSUz{9{)RPoD`V@6FC?dq2S?
z;_2w)QEu$Q=H~C^E^N;E0%z+q`fpK+?1t?D1-{ocd&pSCi2mNj5NmVq8&B_I(>2N6
z0(IehjX{_l=Qvnl>_>};#1F~F#Y4mBue2Ld_BhnjrNi~B9a_`L7GbXweavR#BWzc5
z7uBjxHf|;;fdC(I$jKct>#G3vT#{d47{(IKi^dtPbI&84dyeXdE_E`5)5yJLVB(%I
zN`psT`W@M3)JkHnc(%&f)t{4+E3O9#c{ZC%#y68hOg3p9A;2cq61f0r7e8na%qH7n
zVXsp(a!-Yb@qviekyY($k_VJKCA?C+O%n~u(*Lg?sJP^Z->VFki-%qvPp_6<4zFCE
zy|dc!G8cx&kfW;#xZuT3DiiG&J7d?*-OucTLvD{-y6=>S_qzE`S3sbQI6M#NmYm)1
z-e$rxdlN^#(s!pfQrw8k=~DcaqCbxf!H%6#S$I<7MG`miU<h6Wjb}98e+R-KA1`k@
z0eyF)lD`JD+GgD=6ZY28{GqCDjy$z!j=M}nlCh1Y-I`ysqZ!a_q{Q*r%ub_kP4eMR
z@1jx40B<d&@+o2sr~sN#-ny>edu9<(jRc3}@&%?qh|Vz-tE?ETltp1r;xi!MV--U6
zU&1UpBZ`D5FER&-y_QN2AO%q&!tQ)9@?|%ql4a`TZS-o1%pn<lXGF~m;0Ih^zu{h_
z#r<m^C4X{JTQtHwi#e@%v9oDLeIiH}uCdLR%}QlNt(u~)MV3=cS9}0M9|5tx{i`42
z1CMJl!k^=JI*u|}yHIsXMk#)5c+|*9ob*)C9!QG|%0eSd!kd*YUPRe%!p`ugB!Hw7
zLf;yv#IWtveDc8215@<Igtqp!-Mf)e#&^-1<Jl04o4fYV)bs1AwXKlHv=iBFGeC3>
zR1OqOG;bVVXV`0W-jDyozd%!yv|zJw*Sf?T(REQBFg?o?(K9i=jlagOsYrHgC<{nM
zN<pT5C5+#KIVLa0<XEU8jk<13r_1LJ9tBWZqThXJolewgd(t`{k;)w#_Kh)v8X*YB
z#y6;s2w{;^cu+8u{O)o|xELJUh5BF8H@+yj6P1Q^kzVLDt%&gfqqZQznUZhvU}fSt
z<Krvx4;$z13eDR65a#0bH}InPzBf3BFnIu0kLHJ_maf3h*plYwG-C_zfetFvh~ac4
zRb}8%X@KZbhW<8Q&T!H%4ki4Mpo8<z_jnnxWk{j_|5hgDmc|bWL+MyN>9XvYX@a;J
zbeB>T3<@Z^DyRbR$OELfem{SR+h1ZREO8Q-3G06vatPuPCz;Q<hpHo~(xHO0OVSZx
zN2W>Anwt9CFTe~T=zrD|ZhYoLIYY&7Y{~}S2xH4XQ$?Q48?Y&4fQk~v(_XFs--=V2
zt!ZWi9IA{A7~!yq!NdCk3mEYtq10&LIcl<~!ka)i297S?nMOPhV#s^#*QGN)EvSKq
z8?#~EH?kr>lU=onG@JA0DIZuSg04_ekx+qG9WaV?Nf>$&ZH>eY6!cdHo*DPz83Um^
z!8OW~IZTFb>cu$6%Uv9FP5O1vyAssX$;|g}o@HAkR0_{n;}K1{j}W%b8@-pzPLnQ<
zCD-dSMc>8M2ZV+%9KU(zeWz{~mYf<%GVfd7+4@PwfUS>vEkXf^g_0DtNMHN$fli7&
zTS-*AuqeM!r{n0bvvv85_hgx&a9@ZHPYXHNRL9GrZS5{WQFPHTw%|5NPN~nmWzr4g
z)b0J%{>A#UU^$jTA{)2&U8p?YoaM+XpB(==U|_@;8XZak3}C)zZK(=!q^2^(jC=cV
zW94KbZ#Ba(l16Q*?6jrY*kG@gf&6!pIE)?h89x(eUN&ydJCMz6ah`Ox0;JEmOjCcW
zV!bs`&h`JM^PAyN|AhBq)N(mIpTYUlIHzIlf~w?aoNXnC%I%X*?N0v}g3Hczlc}q(
zy1iaKJQr&F?N%L)a__emYPxjp#wzq$bi$%|lMR+!hv4u-$&6KCtWL5?P+N#?>^&8|
zRK0lE^XX{NZKRrgUif(2vx}L5Q!a1^s(^~gX8+Xz_X;#B7>#KR1(~ODriESrC?oio
zM%6J=1Z~fGH_Ah%X%9nlL#YRI$cYgH@Lcy}q+>`U>y32TCHQy@IDJ8i{f2wnedsK)
z){WyN-?K?nktafmzH5j@0d>idc*nR2JsY(LB)1F@{aV?5>i55N`xLr>4xH()v+6ks
z&v>>L8My>rRFdCJ&8iSW4}g6!!!&|2c|J1(7W3ZbU#i8abrPdglFtSwtcaj7_Lap*
zbJXJR8_G^r7VA3l1Vu^7`C%~)FT+jtWJ7(l|DoEU0;o}w$JWEGqb5i8X{%HoY71@R
zf(-PhEgAtYPH&ofe9mcS_YBIz94Sa}1HD~iyOZRRuS15}j5kQQJ+er#jKKis8Jp^p
zHRn;Rn>)<HhIiR}TmIZI%JMTFy-8wPFYSbWSORKEDFt8&tMwH{yvwaRU4CTZAhQRc
zh3|7a9Q>;*hx`5D%6IzLr@uYPC$U6EV_SO?X6?ABpaC#(1>At=%({zj*$dBhcVdQ8
z-ap&^QAQ(!eZCQ`S%oxd6q_x2C|?gHQ0^y{a|BZM6rW8y9F=HI^~c?e)UU}5+p+W!
zAhiz~t?o4=g7%L}2&ITav^n5glv=KWS1Uo{j8b68!5q}W$=3g*I!$WessZl&z6mN9
zW<FC+mbh)Ds@-5xar(^7O};XTAQmwm$az9GuNS3+LYx)+krb_dM)G!<*`yMl@%*tA
zB1FAmNN^csDxju8{%XUd1i4>H1kM;y-$MrXc_Ra_t(LUwS7|C>c6?7HF##3}PBh~k
z+%*b9Y<L-1ez|(!Xm1#cRqxy^$>=Nx_)kxu$7LJX!r&UZQyFT`vrI82Jg9xjW8)rM
za(g|GBg|>BArBGlA5ynP21N?_59Qndo=ZDvK&Ku)ZQ+Q^{DJQ~ho=2-oEWd^u{dUF
zNKdl7m4W789?(t9bO6<LrG$#si7Z!Syi!g4l0W_WFZeL3$89>Xfs`%8AF+BLdMjQ(
zclBq^F1xGLLQ3F1ufyWW$SSE8=n2u|l$$sk_<~3!$c|Fxy`@=4M=WN;KtxVy5YpxL
zg~l8{uCl#Q7%XrzM-El<*Ufr4PEHF|gfGB&|DG`s8y#MEj*O5}d*xvBMwXP<$X8}#
z2SwkB54EBB6pGxiR<<C9Ly{ejtqfbJY!_l^mu<TS!97hmM@uyD557)+*(!aJEwhYV
zr_h%Gq1M?sv}GXIh^G+zrYV6-89yBSfa?mTk}@*UXX3lR`cWJg39|$Z{h{n3rsl(%
zkS&t%Gv}5~m75DCI}VHN9*ZMTVb>IGD>_WXj$El*rR`^5dF0yf&jL+@scbHq#_&pR
zsv#|FW0t+nOtuxc*wr%7dpD#z9jEd^W|k0;Y~4RQ_^7hNeWWLyh1C`gB2KbjaV#ZN
z75JbVJ1FOZMR~G;ioz*mmr;2e2ZB4AMjszn4HAyHOt7U(r&oS((bUHeN4{O>LnH-4
z>wLOvkDeHcr=}dc;m%DAlV+|`A>AalbYEt#)C9Sq|La~wvQ)VAqFlM7oLhxivFsVk
zBW)W>9h=8b4=i_8QC2+hHx(&qa`NyhS5!hf>e;4lk03z<1)9*7^3-y0P5b|gwD(eo
zWS3c0BW6HsMAen`z;`=*jE?|w)Bp8Z!ceKxedckvZQdb3VOi^zKbb_2<P%7J><!}%
z3t(FuU;=#ECwXjmdg7TeT035rh**qR;jlT*Oh}y_p3X}Cu#rC$NokX=Py$q8z~bU-
zxkt<)L=59aG82$Wxu~KDgpIyOCP}HJ<wxIELekT5BLu`|8=GaFGf@rh3JXHl{)~Ka
zAB%X!g4QdN(?oy9k`J>Q+a+z2m{e}iU;%46*tWeqKDbW4*4{VwHXc!0yw<Kxc-sh!
z<XJ~YHqq{r--HOdxPgt(4T&@I2Y&-y+cYgg<58fdYXL-@qm0+!R7%P{6>r#2Mcz@e
z8OaNW4YE)0xyE{S7}*y)-=RM5oM1+j)9ET(&8Jb=Lp$<M_51bWY)exl8pWokqIprR
z-PG@?jzq@p$?!o?-fB&xplN#|#6_JjqYk92TlaPS-amSR&%njv;~JtMSzFL8&l@GL
zv&Lo#MQGe<`qSkparvSl<@nU!<VY&`J!ok;khJ7*`YUEx7(%F7;uN1O|5LZKj{^xm
z2=<2THpkFQYt6Zwe-W<$l|19PD`Z=pV83N*<<1bR-F>H5CuxA3z57o-q5yp0;2UEk
z<+I5?J#U((824C#Z5&Zdskoi2O}_A_)8p{>3_`vUQ4#03_@ZW69)g2oQR(R)$w2={
zF#1~6WyTqlW6~NdIvEllkj5RIwTlDC2OL8N81D`zDx)JP+=>@q2hang7`I3%84%a^
z|EK}MghN8|$`TY%B~y$-)hU?NDdJz<=5CH@{Ma}Kih`G%g>eeggZW{hGHRZ9VN8_A
zIoU<A2Gs+`^JONG0X~rck;%B@FO%cKK$8ApFd##!+8|QcwqX`@o6B+St<<GYI4A47
zL+&#LORJTP<tJx<u9$}6V%(|(d~(u>AMr^*{?In^*f978duf^}CqB6%bl56_QlM8H
zjIqQ+A<WroCm!(8ew`*Yb9iK+?G^Q~hj&G%*m+t|c`js~O!z3@($5>F*--I%z<Ark
z=7j0-ftd_mNLKgX-TW~noE9&elT<?-W$(xo@=K~`PT8yq&OUb1H})=zGI7dXE;(_V
zHXwjSB_JSKa$z{^Lf?TwAd;=PC5E@1DATYsJT4srt5;Gz>pXQ@=NvXf^a0pOQW-(g
z9-%ayaoiKm6JfW<%`Tb0LhEAfUgJ-2g2T9d%kbNDJ*hnv%O2i9ECi)gylu!s>}Sft
zMEX!DlJ^<cQpL1P+LBZO_cS+RIt&orY9it6*HMXY)qzSKVIqI>&Bk-F>`kAr(pm25
zudBIxj!{UmZ>6Txh+FljS+Wb@WqK&&;mQB*K$1}|042AehsfY1Vnqix5s6k-bkeQ5
z8=HsI`JvRY#B7Ri8&lc<W`TfCE)YwB^Nae$k_wu2t5~7(3(lvV@-cB%!qxrjjcz2)
zPGls(mbG$@gHD4+-lL^*Mm5;Fqh5E~W&X)az_2v!?)r<8=J1VOWJ1sv*$ojx)E-Wq
zjL#6OLfBAuvD*g5DWx=^@A$=8&38KDj;kjeI*uf7gUK>VLh&f`KZ&_Wc4_f5kC=HQ
zWtz%oHDk!=u>u{HkV$1}rB&}P!@4i;C>ua093tiL`W}}xAyY{F&qN6ET5Jb1ArItS
z;C*>HhwMtj3(TjX9Av~DSD3clA<vU1kp#fzk&!5?ovyjn?M{~%tKOaNPAhM8$_K|`
zJ%37^ET(6}__*;;<k}rcyODVN>0Kfk7P~_Y_+$vtHl)=~(_q2m6%U`IJ6y3|d?KuV
z)~kBMAP*f7LYNWW;xm8v81KCCkaPln+c@SMr#t>ZECzgTe8lB{SiK|p4s4wxA5G>d
z7I9@_L+z7s(RETHAW9ns%THHfnQ`5~4Q%=O-OU%`ca6VooYbG@MK`WB-dV2nzj^2w
ziLItd?jmn`{5_x4LH|+Fm6S~UOf#2q^ddM`5<DXkmvN1FWAc%I`pn<H*MGaO|NRX;
z!fpQWxm*_#<*@jCS>5gAD<<G3Q7zBoK*^KvjTDmwIVqZ1)syAS(W-o8>{or}_doXG
z`^c8!8}h!wX%~Ouhg<r$Pm#ZI-g7B7R1ZWz9G6=OxrD@6@y8u7%1N$VG41@JvW;--
z(o9B&KcaQF_wWDAd&RcHrr(nXpC~ta;~}5xrv7$s$w(2m<df!s0(#jVIa$VAXo_ED
zPi(xZh>1>;K(k$(^J+O$5l4+rRPO%jSS?vhHl%e3#ETP+hLcp<5+?kEo}rYCfG(tq
zYO0vbCW@(gLz~L{VzaX$IZvMo5W7wObgJm4RCkd!BV0akm(<S{u;qKLR+H4HQ^w0)
z38&LcyijUB|M0TmqfvJdEpr6CyF(*cCqAf3-bx_rNi&-d%|`slqydJiA?b%%-A<JZ
zhIODIysUZ9=q8iMRfWY=!Awr+V_gx8Nt=eJIDJW5F#?i&X*}Ozn8@<p*+gqfRrI}P
zly#Ewq4T4PvQ$jJqNWwCAr<D6_!kQqMc2_x^8@A<&!pBYp;)%jN&CJ9fwZd2kClD{
zUz7I;_t8PA?A4W!i^`?UKHaVqYRT^O8$l+mIL<zARjrMB)2zZ!V4udRNjA7<+M5cr
zq;mJ!A1V@oD>^mkTJnfdOUgg&qHLw$Q2Cd#f`oh+q;a*O1zQHrwsfH?rUUhDP2Pd4
zWXD0g*9<2}>Y`QzNUkV<^F7|v=h}H=##ghk4!o7fZkUjlG$fAztKct=l1tS@L_&TG
zay~8`HSpp-57<pA{s2B!e#(<gQCqzK-M1GocoLj7jq0kF?NH%kaDp|XHsfqH9o+-f
z^jUn2BX;-smN=0ZHmnQzPAgdrtVnysSTT+UL}MYIU_bY>h&!bCh3Jx{k3FJxsz9C$
zBS@B$t<1DP>8v>~!54r}##cS^F&1G+=LNMooGOD#6lC`RslwFf=0ZD|5Yx$3ee3h_
zy8nOq_Rl{45h^MF1CNcp`k5#G_y1w=v%8~zq;OvRB40*t;HHcfOXIh$o>7&$-qhEb
z$(f&Bb+y*8v(MjUVXJEybxms^=+Js}bu1`3&f=)=Fe1cQ%+%_Z?}W=%)O=YrFInN@
z3?zItYt1NFOXic7m(|nR4o|av*Vffq?jx$9*M_?_cYQia*HQ>ZZ^BYT%e{N`C-K5P
z7WWa1m}O^&bxk=nob7P3nd_dOSn%~?mj#a`r`a|WSlnC!9@$Z_-_~T(@mH+rCB2qV
zhE1<Fp4buAAQoA1#)3jhol2SrtzAgDH6t~*FIX`&JC@j8WIvCT4Yip1(x}3xhP6gD
zZBE&bxVq)|s#4Gl=TTi*HG3Nu)rN2(W1V(<MQtVMXc!0@j3A+$vj$944g8e?Kq^B+
zi3Gc?Wvg}B9#|eT7K3cEW+e-x0TJlhaH!c$=>{VKYA2giI@SK@#VBC^Q}DhfRP~f=
zD8GG;jc7=jN4P)fjpN#&T1#r)$Rvw1Lk(%Gm{hn<MQP_-gO)ToYz^si5vP==`*L?V
zci4K5<1@e84diqwZgwuzI93gooGyoh_0886ojhAu8wkPCPp0g^o>o1k!`2)t;TNss
z3LG>_(W>|;9mzN>k=u}hQcdr$nvFf0p%yHiaX-MAJ4wjkemhoiDHyFarWIB7vxzMJ
zyOy;QHh0-&Md`SqfLn1l{CA43SPiKi>Ue0oL2@i*hev`iEPH8d!S^ivLa3&94X9zZ
zQ!5x9mZBMcF>PkK;^LzmdK~1(HKU37NUx?lHJLUZT$<x<7{<IcTC>rw>R1ZjQ8m8i
zM~Mi{(QOmwr4{~~<$TtN2j2Pj=x3a%@ysU0^oyF~J=*XoEeLb=kWoxGG+V<odl+H+
zoHy*W;=P~JYkFg+FR7%3d~!0=<t)q%G2WnJH&qPMz5e1@0SDJ<ZZVgJH6tV>nQyY%
z5?zWmopRa|E?z#Hubk^wLqJhSZ0?Go)l&VF-1)wQ|GVEz>D<8L&y%XbLQoe7C(;d$
zc&K0W$jVvDN@yw#bDF-QD(taIPA5O3p-oAvq0iIdJk4faN-bI@a%ngSNyx722@aKV
z#6`*lQjfHFSwBHO>AO2VhG;aT`Ek}x^WuIViXF6fHtF!Hm1t|2rF53e`X)SlSTZm4
zYF1*!vCM{~^^!LqR@lgtQ)$bDh~!p131@A}QMt>3q6DE9@glk9wWQvVj<|IneDxpK
zQc4!bOLV%<<tR~8L_3QJ^u#7*I;<MXWJ1q!0WIn5@N%d$rB%f<J>5kD8dAPhBb*mo
zAFf#Z!M0^T!p<nlki+|vwbK+XPA>D@5<;jdZzZ|xY!cz=y<tS@{&a8TrOt%mzfT|I
zeU{FI+k;>w+~zAgLO<}MVp0hrULA0bifMy}nDh~>S=tIz@>{idD>-#(WfyG*o){&S
zCCc`KCrBw`8~6XKP1z{Pd+;cxeBMnWf^1Tm=3Y`(z*;Ibf(bR9rDZI#<as1)CJnky
zC%brhv|eMkG<mN;zA1rsF2j9sxhec>GD_4^c9c!+KflR!j)ZuOu1i&b&(|7EEoC1F
z`LG5k*-AlT8>%<*6$XIjA}!e(rE}KY)Gq#&)cL;C3Pz&|hO1d^%UTcw%Dk;cGxI+9
zHtA;bv*~~nQ?t@RP_v?RK&HFuA(j4Q3kkAz%Ukxc)ILpXIQkEr+<Fn|Y<ki$(u<lB
z%v)Ja9SRzF6EoPA3CGe30?pPKA?YsT2pU4ojrv*N@Qp?*VJP&i`*OWms+Rafs-<~&
zP1(>&WlbWNz{$3IR<HRO$H)ntAe&a517UFY<2MyMpK5q)6=mfa=^zYPM4$({kAo9T
zB(qRk$$w>eZ#80MAZz9$xLS?pp_S6v$guDDft6_HQnP6qGuU{xZ7Nao$p*O&G$ElL
zCY0&M$9yb+(~x%8$4%<KfBKgx>{E(0t6>rW5QGkYG^9)Enr5zs-Hj<_msv|HOA5C=
z;&AcZvJ3$5%2=Y9t|8uR0~f8RGss11ode=2^PXISGL`C2@hz~YQp!+Pd+>{2<IY-~
zr<xX~BR9%=;gB~u<V7wgJ#vpYky{JA)bcT2+YlgQvYTox-NmP71C_0BNKXe3MO-m>
zvl@PJE#=kBbnPQ}$eFZ1m5LO{D;~pzW);fc`}-dSQ3{iKF;z^;>g7^-TeIl8YPv3$
z#7DE*klW_t?#06Xh{`dlnfTsTQi*tUS+(d<BrKQ;BP+GWAC?(C=0xkKeJ_H<bUEC@
zpF?3^!t1wILoX<gdgsFDCO;}4$iq@>jk_s-4f&lN^%c}X6fUD@AlVPn#UQPR$_n=u
zXQUSSb5VokKf;3j_z2-Ru+M#odCrk0i&o<BHbmuc^OT*x@-erUl2pp=rKpsyR->HO
zKbuj%{*AELX>ngJxH|7tx;8o!(nPxU#5et`|2Xp(US~9>9d^vHH67)mu3+-fGmGbf
z;LHD;+Db-y>ikUW|IxP4JQuaCE^BRXYBSOF>fB4#OWNr!dI4s=BT;tBUk;<FIkGOO
z+VXT;WTiE4ZhHIct832GlD9TB>u#y{EsT4U*S*>4vGa2;d1Y@jJmXH!dWY7%>H4(S
zx9q*t|JJ8Mum6L8`>8j=3giS~VbCkinzaFQuXV)A&b7}(!LG;(md0*a$w?;~uqL{~
zV~_5PI%fAz>AJPP?EZ!oO$F&(G}ksZ6rd%hX1IO9c`Ns3v<Sp{YAv!(&(uDLDxu7=
z618;=eQ_<il=Uq?GMG-bfT5hyKNjqo>$CLMsMT7sX9A~p+0Xu7@0c~bzAM@im6pfx
zA^Zt#blRITzdjxGrhB3vwn4$*ID~|Jtw7A6oC&)lTbhK!GZTDUP{Ow@rT@i=M=9cj
zPg}*gs2g7=P|ifb5ud}1azeC6Eo%%_W)<e5pxK$53!bMU6ZFx;83mNQsV5Un840WH
zo)%4^lP9e3qPFZgwJ&>peA-^mQKPA)OcO7nM|6GdKsZ@-SEAEAgJ*@4UE$q-{VbfK
zORbB>m6j#F?OHuCZ~R|Tu5Z<vpqsp7d~y1vrEQgQZ)UOW#Pm~B{mVvpW~%j)wKlPH
zbk5je?Oz@;w&^>pxnn@Aei6>CA=Nq+nXQ+!i|fnFZB1R#w&k|3ynL{2I~n-%UtTt}
zFZ$N4;Qk!q1BUh`+{DxR??%g0PugeLb*uf}dh`ZVe^Y5=?<d}O9;HlmRnY=R9bb;r
z?DAD-{KfIxPu|J+x#e|l{JtBV8}Ls@-$+fZdh6=+&Cs0Hntz1wpPigsDt&wO=Sx*H
zcPJ{QjPV-~Nwp0`=2Uv}MD&4aw%O@dQ{zK-b~*yjX-oR;UB(;Xi{T!lI8ex`%X1T#
zjN}<C#9FWo2>WVe9I$>bc+EO!`E852Gr^fa-?JD+#un{NG_`D;4LYOw%{#PH(PH0V
z^itGjBu_=JO)WJBuLVr#F|4!L0M3Q0^7JJ;yX^9`5_6U^TJ()2_Z>H_z7b8Q)f(+s
z(dm9qowC{=08)wi(r5pdWXbI`#?!8lw#^&kcdQQr%z(RhaZjT)+6O`Rot=FoNZXR<
zqFl0Pbn9sDmj7<J5E->Q-m<YW6)C5dxd{5@7K?wexE!cUVViMt`3}q1qh;gMU98Dc
zN26#@N7w0SD*E`F(emORGUU<nYt4!1HCO}Yjk|MmeW_;s%aNl_E!Umw@^l{y-0!{U
zF4@|==NyTY_Zb@{RWfbn?DXqY&c6}e_VwlP?hk&Wc-y+{ylT)OYPAj2m9}fkb3yUN
zX>X~6_Knw!@fV}lm)nwZ2@?~G#=eQ?kgm2%EfFQ#sUdgXI2~;d^!aFF#%OLtt{m^p
z;I+;zS{^{(mbtCVy7tA^^bYn|Plr=hwAK}7T`=;^kDQWwGauC!8<o3S6wEiO5yv}9
z1%U_Ii`(O>8W-agr_*n&o3Dd}>@$HWzV2$xt*^Ub^N+OG-R?(=;ieM4U@4_^uLpYg
z_Ii)UDx!T$?EL!Fqvk7V<*XGY&1Wa9Q~v%R{aa(s2q&WSkw{lgMZp220e!x#H9XqZ
zJ=8|{hZqJdD~xJ08YjS^^lM2;CrUT_TroJ*dvkN&cr2Ut?#^l72vbwh(!pl^PXF{P
zjlnmpR~p}rYEnj6?r*lOl$?y(0!M&9r&8ZN{&(ixXOJw{9H3ENKItVy#oq4(cG@W3
zh~6|e#QlhuOZIn#xoeSqt<q)q(Y*1FWu@O)e$#k#d@eGIUz}Q0m*x$%JxcFM25)pd
z61Az3wY-@l9eDmr(QB_Y)|T7m8>g1r40!(*H^&0L5cP#DeyuMxWtj-Som~(O)C}b*
z5Ys2!y-{;xWQGUVzXe)m*t7dCYs22&@crJOvz=#92;)Pp=!I~e19gA;CDuNEV|}@;
zd9$_L)|N!ho!1Ogr$?vZb)(H#j@oXG{djh^ciCu5zQj3gt5{nty?B3du{Al#D+a8c
z(VL5lxwHDg*R~mZemvLw2g`Ft^TO}&{#3NM=-*23`R83YwqwhS7HlhR$%xU(jmjI*
zm#-o$Q&Fn6<SO4-J~$usy-po6{Zwjv)GNLj-gdz{cwY0xaM+t~-24Br_df7(71yEv
zz3UBG94Ba(jeZx!g}c{_b1e+mhEhGJ4SQEt_R3yj*&(T$@`~-ai3&|IG{2VSy_UUK
zBl$|KZP_7I=|60tQkABGP}=90wl9(+io(wYlgE2MH*Ft=U;65{X<1X+kJBd2`<}VG
z`eV!ZpVA-s#AA8yznL><&YYP!=ggUztDaX><NEY-qy8tJD?}r-R<HG|(Z&+ZHM&0x
zHbv#p*3};8I}cyh6}2Yv*Q?e<(}*)x4O_!6WL-MO0{u<jrVL}-b&oq+qR(&Z8vWgY
z$HR@I*H>wOyTWTzEnW&|+SLA4EveN@7G#a+aVPPla~aj(WXh>yft$iZ_VNm2g5uup
zUfkjYsdeVWJ*8w<d2M-1P+mU5HY7*=WXr~hj{MhY0P9OTLQ^r<n;f$OztA0B-$P;_
z+ZGe@xx#ZwRPnyM+zK;#{o@!0`$_@g7A**w?{I2G6gXoMVkev&7^=V9YWcLKXktS}
zkx0ssa|p|4HBGlCYE3HBb$c6o7aHC&MyoJ`=VJZ~mh0xF&#;VpZhU*+uQ5~QRnTe+
zzB#5sqkOP0d4xqPjGzX?XJK(t!M0<FxJIAJDA{x{Osal2rOGLzCsp8vQM85DSO^kP
z#e6bM5@}5FDmBKJXdthG6vN_fZ`}f#p4z3ZD;fRyq}nx6#9A;$1Wr^Avp;gj7Vq!d
z-;<|D_ddaO>HXGAw><5Av}c#P$9>w{+Ow<o0r#=y=A)ZW_BwZM4Sx68A79?erJc(w
z<0p5Mr1cd~UvIGXcqjV=#z{-v)AqFYv#Y*VI@wozPxif!#!%iH?CQPKeHA@hz})D>
zaBg(!fUe72J@OjqUJVfz1i-d1hIsQWM`J*@fX2>kpdoOE!Rk|g^go6(%|};1&E@K<
zB<8AS0QvnG$iwaLnF-{ZzpR0L=FVjr$R9rw1K|P?OkcW4#dR?vJnv~;IN)G^L|BUd
zaS&s!C&bn`=f7=^`(DRoX2$udBa4&*{i21HcT@lI0@%w|jXBwC#=r>E94)Baj4i-X
z6{gKx8)hX`O#_RWfj;MzMWu_w8nr#U=ef7@zW(CO7aMa?N`Lkmk!(}$$|8)%xB5fv
z1D|Hq*iV*{ZpY?swbU<lA1JIVu1P5cfWeFrpibwT?$0Eao4pT(V?#!sCd1Sv8$VVi
zGx?E0cUh**G5Yf9XkDB8v6Q6-64w4hM*pz;ptV2exS`v>B!S<DG1<RdMJlz~@CN-R
zrO>cA7e`^9RGIPL@QW>ntY)=!{ku=*`i&JO!vQ<1DdExTxKl<ReV}5hrcLU-5fZq0
zppwAM(Qjf{x_04m2Wxh<d$NEBSg{lYG~k4tuw+s#%t?XK$6E5KmL!^5V0+Mp=ABVZ
z$Neb3(6Li5eE1#9{ARY=QN4d+m5Zgxfw6)7@&x9jWDr0E6{xYLO`F_I&gxB49iW5f
zMJg~tF~kJuYG%aA#0l%kDA5v)l#KD=9`?*nJ;)h`rTi+_i0s^PDSX8=JjWYUOsi1|
zMV2row{&_Ln>|R?)^_#sP04E)<$IEt>&CGRrZ_4vQ=xAV)BiHcu_6+>beh;CQ?3$8
zzpx#*MkZ)0Va^;JiYOEKS!k(|6R9?=dFhnBz(rkjgo(yV1}2G&H<tJI=M?9eurA)s
z;D%Phptj*R-k#s?iT^3q4%FckDq$Y7`+=*JZ8E)L*iPC{K~>du1I7y3m$RwlCfsHY
zAus1rM(EgS*I5{<QH33HP!~HHWN0~oaAR0OL^N8V7p&csPxO$3%tgGg@10#73t76I
zjUp2h%s`b>y~&Oti)o>26Gm6q8YC)azjFw6mHfLsJ7J8j4+~JhP(6DWXL>#wxI5cd
zEUt71VJ2|>jB;8p$3Rtdt*FGYX_wihD5uh+IhUyw84c_d9j~{_YG1fE^kC*pC7o|S
z9x``hzl|36!uu9p?>p2}FIxhQ?<}tOdJ>3!xgj@)jWv_v`0h4!n^kerPSWlDdTuBm
z1Rm^QRHBT(*|R(Sw#-;t)m*mHYJV!5xIyjC+W#L;6~(5KQVH1vbJX5Ovq&s;mpqoM
z?p%ah3>L+u1DPmFDAj-EWI4Rr?M!4kuRL1vnA}oTWY^y8L)OE|Lu%}yb?K8|{5K31
zM&LEwQCgpc9W6#KN+nGO9#e&zT}#iqQ0H5E49_;@xcRHT?xl9;tCw3vm<S@SpxY5^
zLdmHzI%2pnsAy6g^W7Awsk3AurN;fBB^9Z`ta0nEca+>phDMawmB+l4tQOfqI-jU4
zF@q-M7W=}aYt#NXo7>3QA&g_RVfM|Wu;@4g3B!)MeK>&@V;Hmv)lY|4GMbrD$SK-u
zv6NyRTYy<KNOWNLhwU(@wI?_s$~E_VvzVYq%5Q>Gr8~$m4Tu3Khs~R3pN;}l0qhz-
zhL|t*8Zs&*-KxpV8=0hxQ7jKBY&H&G>C<RIM!@3m2jOZnGtuZ#ZU5xYuFbne{xL@|
zm^Zed@4J<S<-{mW&N$YYsJR>r`PB7lkYg?<A(ssTDrBCZDGE&c@<QG#r5K0pB-30b
z+XQ8rql5!q5Q8(?977G3_Ln^0P7Q2QecOxeDQ2WNFD})e9x1VzbUspBS$O=Q6o+{e
zLm`65Qj%n3<om7LOST#0js2mKSs$v%2%-wcAkR-pqo7Oc$I}d(Zy{y0q;7HDgVA;-
z0;8U-Q4rcmJIuRIOQ{rHJ{<NSKjFcZq$l+p8Ed>uHBog^&8dAs#a!&Yv2(m|s8~sk
z<(rar!lS<{q{0<>qrB2}JVW@#F|f@<gV141QE>`a>bA(c8aDLCF?jnymnwZ_DF1<>
zO!ezQUkZ)266N8X?O~|`BH1X}T}cMYg<Vr&Wk~g9qlGPzHIe;Fs*nsTQFl~1?z_Hw
z;?e5|eW&EWuTInAe5&2uR&snsU(bM*hJ$u1xuuk&=%9&r3*~OhV)RN?v6dP17m6*0
zQUm#7%IK#9DpBlG!5uDDs!<Z-++bvkjo7KOl~kjd(cWbL0cBLMmtSr~n~Z_{8ykKJ
z!@e{tAFHbu+E$*<xG!J2OgiEGz_#c*cYUTEYZ-!K2)i+Vi77t?1ues8vUZC{Gkmg?
zC}CtRwIquL*eba$8qOQGa+2#(+ZglV2pbk+K<G~uHyMf?lM}X^to`bTDv9L@m)7R`
zj%{r#RaZssSe{{qsh+&)wsV?9s)vPG0b`QGY>vCanh0I&h7{by-yJcbl1suB6^}N-
z!JfzysUG;GViJML_kfNe7A{o9bepmmp}o#j`^k~l^2L0SN`}!CJzFVB4u%^VD^zIX
zm<6$!=BR8|kr!oFWH}kc<IeI2vkX~7Uf@|?gj70dgsrJ!KbEQp%?bdcN-_PoEZ7zu
zi$Yq-K(cdDm<h#X8Vw_)?z61EB&~zC`R$JwPKR4eISviIHC5PNv=i;&@uF240Vo8)
zic~1JJS6k#O?lVt?hp4Bs0Ym9J^w*5*f|EKjf6d99Rh7CCn_06RGD-`=v_^PQE0oV
zun@JnI6~xEfojrocDQD7o74K)yqzD(77b&~iJxdLWT=n8&=NxkqxG;av2`t5DY&pa
z)n-FaZ<QBCE3&TFq@-8!yj6HNjFn2B(eI}!6SV!7D4(kA+gwSOlria)2D>?;CrChh
z45SQXhE1z9sjVPoXQR~6m;T~y%bJINrm`(Gs)<hLId=ERZl63HPL3$Ie6;i__a!w{
z{oImI=f@9UH;#yZ%ckz#ne~Cw&#ps9ODTJG_Ti_|K07BPe|NUi-K_dPneQ$+LB{j@
z+J^jxZ_bvl^sVjX(!llz^|iev+&j5@^Mi*z5ItC|c6RqyuN_@Sqr0JWELs}=NpyeD
zfnu98=Jwwe9SdG6{jGPiDo^6&d$jcDrM7HqchKK9dUf=b3BNz_;DLu9dZ-kYe~o#x
zQ8oGSiRvG8E$wPm!P29OKKc#i4(wAMLu#b&aCF#(Gs^dmPCV8#X*q7sQMK}+eDyB3
z{G7W!-0haTqX1oKgoQ;O*8B|v<3pKU*|kw;$$ClQj9tlXjrMKv4&x-fZPWUEuqFEH
zK>oAQnuFcPBlQj0d|)^7*rRSMg1{>GvC(kA84beLXklx2*dK;&x-C1pZ$&ozO0nB3
z+#KyJZK`&3Gw^=i+7SFo)+3|z52HV>SG!A{-~9Mr8rQG8F2B@Dxl56+?sJc#vlWh(
z4l1Xpe>X+D)Oy!h8ys-akJ_qFy03Wm_YJ)6TDz+4F3UOFQyhWOHexkPO5FHfoaBP?
z&oARYyE;5udeVBuvy#|tO6yCT)UF||sy#0HTCB7=*f^ha68(y`z!*8#4LdEzqmjIW
zp>$h_$+XBO2m{HA>lR6oz$*G&cyD&7R2J=KZK=p=&6BEBWcAZY<zM;6s%6Fp)-2h?
z!72W#LCZT5z22*CP+7P4-yVCc@OnAgP(0{-c(mh<ylNf3>Nk%U-9yd0B7<F6LX0XO
zoHTZZR>z35I=xa|o!;d}pC7>~I`e`$PO=Y0&rY^Ke&zbBf*VFwvkBI&$XU%^!3v|q
zMt|MtHq2q8s`cmGwqV^ivM)vVMWfH(<v%q!>MXlG+W)xQeq4RM7(Er8oSfX&Gu$6J
znQ*}E8MX%4SE%D>K+#(tx%p?+`e<3UO|AcYOYR`uLdz?i_o_wvqqTmidg9lsA5fXs
zK6XXNOCwJ^|1;WDwG$nSskZx-pGmwBO^)PhRcPX1o4%(s>|D*>?au2;{nltM*iga<
z)_i|erK-j5(*Bj<4T|N+VaLc#)vc2QVSD%FZTXfZ=Khs?*a##VUb(i^p<eA-&^h9_
zZi@y|yW9bHVfFPW>UPzBmQX+UxmR)ji*{it8Nh~)Av?vST(a-!iInSk?vCn^GQ9QO
zY;uI1Wl!gil?{)&>N%mZ8_FZzFMY9VJBM5iJLC3OqfNdi#-p91*nlA6H;P|$5*uK_
z$DJb|JL!zbZdmf-&;G$mv|OGmj6|)6n5^FuJc{*mV>E!R^roP1GT+j^S*;&!`9~}g
zEt!`NQ-s~hbKl>#!8@V+QtP2;-Kg*Oj!tw%eWS<MUDoHOg3?`yV@f$sMWcu9;j37V
z7!F{Fj7EL?ppW&zH+D|;C6ASkf8g^hfA(Ff;?K&dmJ<(U*Or?&oxU8svHfx5#<J=w
z-r=|6z3T07?~i^3)8RA!GVB=M4XU-+dQc6#n)9RtKlROO)oA%jpSyIZ>S1VJTWWp1
z%?dY^T+D*U)-7y4snla5SME@6j3_6w-*MKbpDj5~*pW}veE+V?_G6tMW`x0R^4J=+
z|M9|cHM)(N>-}X&ye>*a;T9N*{y{yjjNPg)$*EF?|NO-MG~chz_F-n~{Ow6>Cs<Kx
zzx-c~iWu$|IZdSzXP3LX@4Cq7J(+*3EBe#wZOZA5Mnf0=`Jyv?<=Rdub+&nT$idk6
zM$2J_F2Aw~8*O?=wY#+XO14tIO||u&tX3mLAMCj=mQ(JAQmW><8@#Rle%dw0(A)qP
zS{1IVCLWAJx5s=uwcj`PL<c9U`Qgt#7d@7KI7*SPo0Q65G^Pep7~R`b_UJIH&V}l`
zBV$8}3506yE9%MjFX;Gs{^@P^xtps-*F<HNo5$4L6)k<pIWl>_QcM|K=VE~S&6eSn
z8@yjotnS~?*>AnhwsTe5cugsLIO=3w;J}b-@i;d%Y~4un9vHonEgO3O!cVP!1^n3$
z7PDI|iuT{`V4%+BMkiaZH3vpBYI5BotQ);2qset6&aYryZ!tr|9=$zNp7gCu=vh0W
z&qY>dw_5)VEN3q3>hG;4o8ItMvFAnq-iZ<a&%fB^-{|MD`QGk34sMN3xZFzY+I^$*
zD}Yt1b=1jYHy^``;@<2}Y|lY}hmA~MUTmhfDJZ)Wg<xmouU@dWw4pS->Ila~KJFBf
zt%-iD?|uip=?3qB0=uaAk&&CQgLYK6Mx(34oI9G!6xRvy!{-#F-|w?sVPwGf90Xj>
z)0gd5EyHP6cV?cf9$)u(+Sm{6uEH=r$vjTfU9Jth)-}<YbUGHfts8x8DW7%*qYZ8*
zQ64HfUBk=VRn{le{&dGnAG09-ID$)?(K@^eyXl@V?6$;UyLv(S<nTo6g0ee|5md@#
z4?BlbY=E<Pagn$YyCppuWm|qL9XP9hD?M;<_^~UQ{4&aJm>5VN>kpQPJ-Jld00#K0
zEx+Ty%9gzf^Zuu;XTIh5tmT>DVPjNY9^RByrNW|hw?|Q_w$w9nun6)=#o3IicAc9u
zmL<E~XiM&=qeTCYIh7()cWvU%VibY}6?U&*rpzX_H7Iicq^fwEOUN=9kTX%KQVO<(
zeWN9&0GDBgd^|CR9v3C5X~+}-pw#5|IvMPt53Mo0&SY@dO8zNo#Dr(~?a5p3ewSK4
zl3$vt42vgCUy#_PJZDVZ-R&GH4&@!Jq6`kk)m5*;q<zX-p^Rv)<z|rRiB!UqlzBuf
ztIc^v*s5XmX7ehDk}BBk6>)mOdaC-D=M%doT!%3>Ssi6i&Cup<U@oP=R`Z?_g^r4@
z>oyo;&2n`(gSelp9#r`xR@&m72NKOMz5fj_zahLA^XVI%`L!YD)b)?}+KxK<bmv9c
zQP15NdyRjJ`SaXtsI$zUr`u4^0%Y{5?rFR52kUm>;!hy|U>Dx>;I*+`_#+SIf98a7
zZ83XUSII+dD99S1_$MWLIVvvpx)kC!Y~fkxTWBmnvocpO1r(SD+LwiPtqi9HQM=fx
z5~7$Gm~EVLCW+fM7OSM4NmekeH7~-B&oLfW?;AIN&KB`pLN>lk{Ynn86=LeuoHurm
z^1&tk_Cuc;RQWYlk>fWE=9~OwR<db%=1{&Vo3e}UN~@gq)uEdW_qL2NII;zFDTHz;
zUm?kj)rNVO1<4L-SFk@nXhpc+ZFXs2xouvP<%|?7VK~CN)3A~pblv+}wuMcT*)`|{
z?R%G3R{7NgjE$35pTZRI?H@eaWcK5l-H~Dt@w>3>iHc&c8}MAyc7kH6(-f~>Fjs-w
zZ=$+GK*w;cL4~VDC0R*UgH*+fpr=DL`!YMk_p5>$R8`|`h0@KXjANA3NyiWDgq;cu
z+G5ag@(-_R^6xJuno5bLgr5)FQ~tP{b07dU<omn&wiGkIt8xaSr!1)xrM7^qCObiO
zU`geu8i!53@v20p&3Vz=K7hAf#mqDv4G)!YR<?KMD8-i0#oi~lHx0Q)(QSua_A?a}
z7R=hMI}JZi$>d+8a7uzoEC@<0k4&{RVHFZ(vo8UQq39G+R`8@1C9EyzZkV<@y=Z|k
z6sSP>#!$^AYmw2D=qZlolwqU23R4<r#gNSqWR<ZhXy(B8RLozSyVM7Y#sP1sX3wT%
zSSYT`9#Wnm7FtP|2#g4&Z-7<$*yZRralxeaj6UBJ)5AXMz`(X80oI5U7!IYc^B3GN
z)+wX*saE5a?bU?eiyamZ@QE$%nA@}{@{PPT(UZ$KW|OlOhpr|!)m|*Aub}q#Ci^B`
zn*~b(w>j%BXlIj4j1Vh$u_dTN^Gc!#@c@RDMrOlG24|OH3B#s`nHNj2f{Z?TyKfW=
z-+J+?yzgH-neSPZXNRy)x)W>4`&?h;+AkZ=DPOrON~71NoM5E?;PS6`r`c2a%bOI2
zGG7HOyA7&TXm`-;Cj3t4P@A>by~(<ELaoSWmR#O>AoO}hGrlv(5$BAcxF%PfoU;JZ
z^kX4(5?exS8%?Rsk4|`=Z93H==QkyrITSd3&=RZ*lUDO&Y0rs-G2wQUQv36PSOHm$
z4F5~zc`7I*g9#s-06}UXjXLgN9xY(C&IDu8U{s}2bkG*Uz{MJZjRg-n0a8f-g~3UH
zRf0Dbf1t@puysYAH5ExmTzD5&Fn(7@Fi{pu14DjuqFhAfM}iId6XF+^@!Wnlx6s3$
zFz7Vne_mLG3!UrPi8h<DQmwKwEASg`vy%>72`_lGP0R5LNwM+yNmxfoy)mf}JdnPk
zvzSe|uCdiAU7Pg7T*)Y4bnuNwDTC9Fp|{DR+{*S+Dx^$L=FR<?J~NN;$I6NQ7Kwu)
zk0{c=2H1#<?pD)Sis$HxEd7P)U<~q#iX*3D-dR+8w!_H5Aujg5oUzNPu##a_XpFds
zB4e15l2~SZzp`M!REMK+<b!f5V?~wAS<N+;&GZK;b}fRfkhc`=zhc7B*wi(}#eq<&
zNes(O|0L+BRTaB&(jG5c)qh&G+6e7TDG?Mda}eheVbhSpG0q+iqCA9hMy+KFU9TEN
zPWPnY^d-ZL6ZE0thrwew2sy{Xoa>Y#*u)4zj&znRD*;0YT)--V8+gMc2z@fk8wV}q
zPC08$4y(2k9-Ly?TeG!;f7n#aq{^EV3ci!b<wAAsLO(K^6msFFe3J^kdT1}^@8MkK
ztBgU)7_Fot_EBhYdlEw~hF7<e@G8<5?hiD@rDX%3m^5<fB&75TOD>JcDCZn=MV>Cg
zf*9sKH!kv*I9S$c3VHgrvCs%^3oDylPpRO@^3-TyotwU^gm-pSO=R4jtwFmNg{i@O
z#N>))A99ZcP**|_QoqJ3xZ-M8EPgsL%$PPY95PpJGWZrs^l^r<<2P<gEcHoB1I0Pd
z?b_y%v)5GQmE%8FY#UM6g}yPsh~g}OFW?s{!wy%v6+qC*E4T<IgS67;!8klpP|Z(G
zKkZR!`dh`$u(U|lDct(cDX7ro(_0QQNfEI|C+nmtLm4|TJ4^XgN6NCJp}e$L1FjTX
z^~#8y3xRL+nB)MTI+X+ya?-rXlUg?E(+q_~%7tXS>oK=r`=lk6YQ-Dq`&a<T6s}SZ
zPPhxp&haAl#?TF1Kd7eseRislPlbLMNpfZ_0-+Q$H7SSrB-c<bRze0wDVGIB#k5O9
z60>Y3gWV|G!T4A)%Q3fufKfaADLb*;k>1mByv~HNwGwU{a3Y&!1@v-`v-GKa3cux^
zTta5Xoalz?7R-?;V>c6)kAWLSu%kehEpo37(9kikLqP%mVh}J4x@yCp0OOu?l5XC^
zBwGsB{L{Oa(sFH9U5-$pd<}XW#!?p2RF(zf4_QXeL+P)CX;yaQ0&>9etYEZa231Uv
zL76dw`m$2{>@<U=^a6^3njwldB=uTQ!QPuIY+4-#2pU3qFyZgVl8$q|TizD_^nJ_s
zxsPr;^a+^;@4P=8I2gUI-2P8N^2w3T$HUQ&_w;|1GI#!q(}#<u|5KeqnfBwQSH=^q
zR@>*I2XoCsL!G0+!Itg^`wwQH8>)uUb3-=__4oAb#mr-M?i-4FCfkf^@a3pFYV8}e
z+=6Rjj%{PoEI1@5N@wi7E}fA}0|z~}!dg&H|5|pUyw6h2zh<?sblc6Itv#F**<4E6
zrnN5jlJ&-hbz8dI!_2-s$Y1*rckS@5e9tzg?>_a_(*5pzquY;1)kBUqa45XmVcS1*
z-_^qthr^>zIOL+6hr?lYxaT*Pw;b;e|AT57wH|c)|0X#2kn?y?f9u}_t*hIDmVNB-
z_~nDy$!MUbJE*R786-#D{)16F!bfvTxm0P-xXUDNb(}tgCe)J1$b9VztL@2bG3k37
zg8Q=FLBRG2#Yx;Xs-L!cR&tuV_2nE3(L331EPHaeIHrDb_qMS2_Po0@eCGD0?$XVZ
z_+5(s#8PKO+a__%T<^AS4Gw67;9uh#ip#{uU6h?Y<88`aDu&6nTaHFzk;H%~t`VhC
zNzgy)uEz2bAlU~is~qkT^raL-_|a$?SA#zU4{Vst%;aH~l|L9G<9loeRnk9|tu$f*
z!E_iAQPn~GX78F;6CFu0X+2ZEWtIE6jcb;0|Div?$#R#wq5Gs0=7RQbtQ*=UYW_Xz
zM$@}9IovAMzMQja!`5&1?G~TEy|>}g__|t*!DGpTx%Wivf15tA5*0nYCwIbEkAHC$
z4qcCru6&{26kDWaJsY{JAH8ZI8otTE?143|byL5S#mV2z7v1Z&8Sd(vRPQ9a>7|wX
z;7u(a5wFIP0cR)EdVkwzmcN=FZ(~Q$m3wmcmKI(2vz-0uu3n|aMw;+lVp|0aO!*T(
z|5+o4;o+ImLr!6nvuxPu_+*&b6m|S_IP79jSwHGhqP`95hSNI_<Q$56RrnP4;uA`_
zt*>W?yjC0{M>4Cu6o-SDkF$07+7kYBb|g+{rnCChAjfI(2d>&3(HSSOb|rc_G8{XY
zbk4(^4c+Qsa7Mbs-pW4CPH$@el7RE-zF;M8$O{d6j~5eYCn)}b)B3>(69g(&OQ7EP
z-Om;_`E2F1sk$B7vUA1~%tnVdlq`^+7<P74aV+hMHXO%0F}-}_fYb7NbqIPM+ILTP
zo3k@~Fv7fqozcC?4bjG<*3p|XeeB7wHyUQ=A<p_*X}vJ%h6k>ifp{T>h0kViVp~E7
z6S5WHEn_-z;;bNkQ~yTa-x3@v4rltYi{q$jVe{J=h{P>B5(Vo<{9B#N^B>38-OF|P
z+jCuqF^?XRv)J4tksED_UJzePNYwgh|J{+(`by`<k1gXkwd_^Nr77miu(7q6Hivz7
zMhi35(biQ}NPNf&ITh)%m0{GTI+rlpO1JN}W>RkJAvV%aP+6hrw!%5MA=<C>e6VWt
zZ=CR3?qd@YU!tvE!sq)ec)~&w&z9~oyZq}g?QELl;uLOiv?;E4a^Skhb1T&6M_Lp4
zd)6%!qt8D+lv$Qq{g2s)Z*<$7)hqEr#r(6jw6?U`c@(j0|KqJa_o|WM7H4HN@c0s|
zchsSmp)6tOws<&3?1@qkTuECrE1_9&f{jrHUSim~&vH3QC}ljzaY+4XKff{RSd?km
zSnY&oD6S7x)5)5Z#h$(42jAA^ySr$eBMxPER$#CVZ*Z``tZ#LU4eO$xwNQR<hXJrT
zR)%k?{+RFXP|4MSxjy3LVa%ROwv@uvX4S=R((8uX7{qdsJIoFiPFDom(s8sVkdfpg
z+sZ&r?ipT8huwEo0ejLh^v!P+!*t0FH%4}%X;C3*Ty2$#|Lco|VhC?ec4Uj2w_iKr
zIK6GEE6Te|(2L!|=;Q8k_OD)S?TOrQ__G60uP2J0a-I8CKF4|@SaYFuIJIg;^f;ae
z!%KqQ_>ABhNf~hU#0tCrrae7O&9fb*)6&DMo5U{1e_B*})L9*x^jdBG^6MI_x%Isa
zPs2IOUoY)*<KYd(;UyCPnLDs4uMIlzQ0z>;>?ah0s!@Tbp}@5Pn_EH6PZS-dC^?Qt
zRlKLe$a%Ft9XjFV$3ini<qsUHt$*l{Jsu4>i83xCl|(hwT4bZ*)^KmMe~DE%kb`Mf
zap?TE42{UZOlb9%Mje{gCK@+w3Fc>_rxbiN@LL_nyr<Z=((-S}V;^fxc;GhSS2)$C
z_}Zt<j>S>J$3YPdFW=Fd80kzY{}Tus_PFu}vlGT`i+dAeS)(;Qsaju*yi%~lOO08B
zMMSnXoHR4d_p4M!^`x*wW8F1^tjplA3>ii3Qg)E$WE(!%`|yRp?uWpfGw&{<S>gWZ
zwxHu7EZfQNJa<LkX2(ucUJcEkOgLLug)-?lm4o5Z#Bv5C^Lkp|xLOhoXAZYvE;tah
zM`2(kZ;9?#!2%h$j^IAMbX&kAm?}q3k%QSqBVpHd#7~hI2aCwS7U&|cv6ci4nX`tP
ztx~`+<!uT4WePo>5{rFGp**cQ(ejkIOJ3u@sttWld-vt%(O>f1?R;<Ibot!}@}PFO
zeCCY4l3!dHqQx#$NQxG&1XyX%Pie1(YzabpKE7$ZLTivPsHKHmIGmvZbMhBB``o2$
z$-KaD8n5(Qn!@zI1loraGFsq|S-`}daauxCwDnwITG{V>2u3@vAfgMQeu*FIzqLR5
zulb)&<q9}C;rrf{+*$gmQW@1H2qwH-&%&;-uo(5bYg=<RSxxi@iLlBt%)ltPla|<C
zgl|HtiU9(fTR}GXL{!FJhg`bCVyG4u1x!zzW1FcsdtG}~o|T>s3NdPS*(?>ZC%ijk
zNm?Rsy4*tYnL{e?=Lg-w=F)iXy^KXoKJJX@0fVDnziG3+9q<#jsJx;qu(XeBL78me
zhu?=3kRLmPW=6Jn0n!L@jkJqNc?PAdo%Cuy@&{c`DTg(}Cr;E=(u8rx9C7t2-0t|-
zBPO7`V<VyCPcS`C1ey>I7W~SOLQB);S;NkW=1Z`AG`>`mJDl@yKPZdJZ+N`l@rwyA
zUHJk`!K1+OkR-8287MPBlO^6y;H`m(w<W?hyNYIpTuh~_TtN;#!EQuG^c6TU*{ntc
zl3!3>QdCd+oS<SVfnGS+Z5rFT5oJ*aj%?S8uRKT$35xni7}{W=;y3!&1}ao#XsQT&
zV<($)fGo%bK9?iEa5=k-8HLN_fuM|n7-?ED{1K(eii)KqF9jmGXY%$w*R>aLVrZft
zzGe)RCHdTlO6gP<V7+NZ;iPJ@Q+Q;&gSG@kER=T;Eu8%4cLNs7qu3L$OR@bKeyflV
zy}y*%vZmk6QO)==(WQYob<&)~>S5<h8#Q8^=NPIIdf6y6p*X#27{X!V!HNnvCOD7^
zeRic)x!1~XQVKQ1od6BhzcO1mdHn-TsNeMv7{)lbfXDu#6prUc5d8}eQ1~78()zlv
z1=c4>DI6mK?lhVf)5Br}GKm)4`TK8Yiy92;Ng<X8<M0xi72Kq8*b|4+rO5{~)Dr1Z
z;=DvIIJ;dI!bb|1UlK94VxfbfMgQX&3#$ie?pDFgQozNCST<`<J;*b8NETSt<QM#C
zf&3D5gDE&B@qsa(1%_C^6#QtzZt|7{AjFg85f~l`8JH^q>B#1V@H}iTHWnS=2`O|J
z@Z_e!g{+MX>AmRBggqQUPyr^+MKSV%2keXmrPIScoE)dtNnU&R6Gk64iUx2EO$Aay
z0)XU~myE3(M1lLS#!`R5Zx4Z`B9tOj#CFh;LQ&Hn18Gx*x4rxV<Yj;O#tu6~)NM%H
zuXH+m)adA$RFJaBmG-AEg1-$T>-Iu1lUQe9(v(uFX*0kH!8JiU*^{GwQq*q{(*wk%
zvNbC5jdB}ypi#9Gc0$(=Rc{9Y9h&rVP{%fRdZc0VIY}t9MAuxmrs&tpC$AcT4E@Hv
zrjaAnP@zkS$x+c6)MIp-wjeI`$CxG6)|C1?&&aV39EwQ**?Q0@$1mj8b|6I|k}--$
zpn|4FUVNchaVhvvgq8Vl_e9KpfwAFvjs6sd7;Z4H(KO&UdYS3W5S}!sgr*MUb{(5J
zr6mi*Km)VD_hdq2E}PQKpu7|z`>l@zD-?Z&-$0+73UNtd^odJOO4v@LjExA)^-ujp
z-00~WuvipI-QYwTK`h8V(G!!!*SHDJz#_0^P+Tmc344eUtqu0mO-OMifH2lkX|CJ{
zTRo`M%zF6cQcl=RidlI2mll1Ly?q-zBf!W(+aEc)hxrx-Y*<W6D|^gX3WLkih$FBZ
zSGiRu3_~X~>9SKr6^ok)5S+xwSNym|Y@lSeoXZ=S?db{28uzS%kC~m#;8aH`Nyq)t
z+F!;ndMyMgBn4-(^Qj*n+edE_o@Mvs6x|k6NNlOf58D|urF!;SE|b=bhi>4wc9`Ll
zG;jmsf1*{|IOP_Rz+i8YhqCQKus7RW9>Pv_yYk2JMJ)M?7kT5%S1mrd=9?II64W1m
z8UaSdUYSTOSc@QaZ#Kz+0ALDLRQ*p3E^d#5S0@f@sfvRaqwLE@*X6e6&`M9S)6fM>
z*=pE`An*%|7X`kD9GCsV#6rL0YP71%V74RKlq=FC^F`KA`9^yxGCHJJ?D8{5I11iK
zJ6V^t5qvGAR;V#0iaZJ_Ju{mE*a`V;heap3ENKs~T#xpF_XLV)K@=_9WIuoFL-|AL
zmJj-PLgnr)FS>4H%f_<NQ;JeuhuN@g5!+H`9;j-K#h-4^V8w3iypSK9M1(}#NBpp<
zx_;oN&es%N4#HrxlTY-3Oim^_pw?rHJVjxQ4w_vD3umK_<Td}V*&!5<TTNHQMw^=t
z3t*iYv2`rTfSdT&4$z#K%<N4Ojp}COZQb~BwMt-N(V62VVv%QVqi>^@cZ|qBt<W%H
zQ&cK)vtRoYr_0AFiGm11x+v<IMMke61~zPJ%F@U91Mf)Li!uWv5JO5G7_yHg0sBZL
zFlFSYs74EAwJ1*}U`rFyDPx>71pFpS`nC-{3-UiHIZkyDl3oX13g|dYlQVv138D1G
zV$dTCJIDU|oF9RMq{nv3(jE6^Qw7>cNAlJ;OuwU<HgtLpaUmNuM(?1j3gX4%7LCMh
zF~x?WtBkyC3e@HAur`;aq+Jsoi-gct^3G@9CTRIFK#DkxxX`5$D%4R$C?Y}WU)d)m
zex=Kh!5!Y}@D<fVXG3@60k!t4?<*{#<75voqpsDGxST?xA%;#qrR<I=qbKc#GBs$2
zCIfs{8ltgGG0J3c%~`<eBQll=4bpTZ+0L9t9Iikeyql6weC}N%I)YJ<Ay9uVlM6X@
zXymglx4aIFF){OqrYa~DN`Xj{e5fSGl+9S6cr71p&$hvMnZY%-*^vZ4Phc5Gj=!^S
zak7w<6^V^fK@>FO*b{@4Y9<C-f{KH|%h3KfP66R1F<8V}lVMLJ3=5zEGGv(Z{9uXc
z8No7GA%z)Q16)Lh;-C2TKYaI=9)9<=VC>=Nv<UK?F)8A5#L`7p8^#VZ#dWW%ui5N5
zL;cSPKKC*NBxk&fWk&r19^)GS)?>h@@GYq%N%l*BwV=`VsMI$LHjs3}H;MG*KVHVB
zJ3tn+bUR}x3-US#BpcoecS$HDkPf-J#+b{c!Wh(&fbkiY<TK(C`kz-u<`i_*xG{m?
z<Td@(Z_udms9*s_9BdK#B@!ZyU?=bc{Yk@jh#dn&r-?f}{n2NYp}qkLkNBQ(=YL9Q
z)la{TA)saJC!iCwY*~M0C!9*L6d`{)74+UpG3oTjaT&LDY2{ahTP68>*L-LZ(y$w*
zjK}~b36%KEfs#<jxK~8FXU##<h7KhV)hdM1WE$y$>22{}=v>5tAly@P`-}fqU)5|G
zdFpewxBYaO-EMg}Jh$ZAyEE0Lw})ddHLogNzp?xrD%)Os^OtxpdE4{L4|uIxiw{*7
zwI99t@0L2r8&!9dtu}9;SoVrHS?tQ}`rNvaw7oItx00=2?fK-*cjcQ$mA80e)n@Ou
zy>{~Y(Vp$i>h8%2x4gu>(fYHJ6^-2Ny!&YBzD(3Jv~jqoto#SO>-*gHllgRU&1kgj
zF}K$nT63H0lyl3D4s@vCE*7thyf;|)kI(;up)%>mUJ8>>2DwAwn#qR><4&=r(p9>W
z_R?N=+1ticP|JAbg#|bLO7Uoz985d;?{2&>+rRI_9{HxP^X^z!=uRJ#d|&&mcb&QF
z&hty{M>o<II6sEEC1_^VYb@cM=@9c{os&fXCZfD!)N3>-njFp+ILL|WBm%Qhd;c?a
zX=p+qNixyUxQ!Fb%c<1zphG<qx#w2qw!wsG9*#36FQ4puhcp6oKlC4hSZHW`B3fv~
z<lQMjOZl-Dhtwe-6{C-0I1P;QxaDV>kXJo<|H#i@!EYfM6GEdx1L9E&^CYuTqXZw;
z#ZW@QOOQju)^P*6jS3$GG4{<uhDUr<thd4YNapA>P4_>ukZ+QKpdE*)5|eyJkSF<6
z$7048`H%#1ecu0pUwB9SQL>fJCsvBMx226&67+DAo1QV3D1-`MGzOT^SZ%8XGhJzz
ztHkWABOUu;L3Ty}6`w~2VG$w;l4I42V{3RC1^r3LLy)z!I+}jMPW0R@#<j`ZjN;4J
zxa1(DYf~epf9fDa-;!GtvI^ETMRZhmpUu>46WSut75quowlNjZVU^x^<XL<t=<P+(
z6UYIoA1oJVqCv__q3iUkI^w+0?-ierUGPj3=7GJEjB>6C9@*O8Ukh8yU?MT)KViDu
z`o&a{^mnWt0dM4Qx>Qn!60LwyPJHapkT(36ccR+^S}Rn1Y=o)X8OgykehL7gaTX^G
zT{rQwScb$1CY-(D=ic6w$kkh8y@)fB2H1?yctXZRX{>*cN*Ah?M6+TT$Y$HJh0+^$
z{&r)OB3FIJm9)ixKx6?_Cs5<20Xu$8g~BHR%BeX1U`>>b@T68S%u98@(DP2-Lm)<7
z9U93c&J^VOH+@m@YatC3B^J#bSCTj#o-`)72j6-6vXI4s<l)t+FoUo&^N9&BiLrfv
zW{Q>TY-h;}GS`|eo-Uv+s8j&WE_a0!Us^dOBuUJfpkuUV;@jXH;LnOF)s|`2v=-1W
z|Ki)%x@?Qi^u>fH_ym+KX5qMB)%obwBX6ZUtTT;pK7;^ziK7vMEkPg+R*{~6>^`FK
zjchJWT3g0xMXAHMXci_HE2JN_D?6b&zWMyG<qK<s`&kFCE2_aaf`w!<vwT7!Aq}X(
zIhcsVWW+X~u9;y5K;HRPoQKn;GNu}9i`PSo%9fH7?Pg}8$864?{Mv8Mv?)-=nSYI}
z$bb)0!PDWCm=tVQQgQE~Ye=ebdWpjQcyONh`ORJ1Rj#Ylkxw7>)5%_IS#jJ&No`Fo
zV`gZD!rMYrSn%(KZK_NzEGzCMLVl+jETRpyZ;r~C5IKMX-6%6i)$et({h3skt0SO#
zfBEt<=lpu9el$BdfxwnSy((X@(mz#Pd?1HPo!NO{=Y)Tqw=*cHd!tmu(XwRNzHwrQ
zb^qd0{=~Ld3YX;yn|(&-4%n66M=)ZG7}3V~(@MWQ#k<M(ipD1jE`;GC@wnwr>;ObZ
zyxqlr{_xk}Xaw8rweq6x--|&dzcqMfao$VW_h#=XS8&AQptf@I<y+p_vB?M52{8f)
zQz;qnP%cr>C6idYCl|g*)q{a_1mGqp!c1Dl(%AH}&yttINkaS%`#oKj3}-sxK{0{<
z)-x6p>(4A!uLP!j@8WXmJ)A=)r)T)J=f72OaP=7PNCq6bMXAV17YQv}N)INWqOp@M
zD`tIAk-m$ZHR0mdm~@yzC42smCpeVlK>8V9jayy5RfXkqrk~+}@RU{EShn|O4bDBe
zeaHWL2dY3X-H=#xq}b#ntf#Zo)esW};_yY2K=@MV#7`h}NKy4RS}(H}S6e(*Hb&1Z
z!j%L+*hNPoldt62RhIsvYSuo;@+?mz942zK1xCQtgQlc3u?DH*GV)rt3Sf6d?An8=
zo^hOIS2AQ}s6N}<eAqTUxm2j+jWTz#15$nIeOGYAG1yQruGo@v1yahmbpe=Kln<Jm
zy0Ob(CU5jxV!{$)+M#|qx_&=y6x#kGq{p|%D~)jE$40+{9oDR8%Fz0ma$am*th}7y
z7?O?tk?2Kb*50_Sun0V?WEJa1S2Sg_I3l%3w!IukktR!~?xCojyC2g$r>V}F%-~RB
z!>8CP!H!HXmRMW^uk)XdIlutKGNYZrGh*T@|I|nt8e1*n;JbF5kIlHl^d@Ux`oFu7
z*O-&X)>tY9%+WWMhKj=OM<+Ee3xCC(3pPbMRX(N+a3qT6y&2!=Cin)DxS{FBhec##
z>Gl@KOLDx`8mq@+Z&0>k;!KaqIEZG9C$7ArFGXYb#zemq5;P4JNnSUx7*y!AHADjz
z;FM3>LV{)Rr!3?ZrvY}n5f6efxI878dVpoE6l-1hE(*I8<XGD~Stuks9LYK%Sy!WX
zU7EQy(W(0zG0!gh8*!O)f1|Uk&8csa^cDqzt)o>I3C-APX~XC{Lr8p4K_nZNO(X$Q
z8~T6HoZ~<ZpE=~``~*AA2)4Q7hu_6^0|J`9Lg^JnFhs2GaEXUvx}dlzlT-@`A~)zM
zfw+llyMpqGhKeBa9p0;6FB7=F+NhYo{HML&L_;hH`Z|z<v`2zS8j>F)y}Z;xXC+dA
zM1cooCn93<I?h3IW5I{)<ilP|Ueg=L{}rj25+L=KN@iN)B>GsKMICD6p*PvcR3r@1
zZU}l-G$suhdm1k;$R4$?JtW#2gS4QCyrab?BGGasXxWIzI$h&j#sz!*l1QK%e<Tk2
zn}K$OS{H~}Q{G!yqjno*kHKk}^3y<fCRJ#=Q;&#_^p_2Nj7AGAT@71MXrz&6jIsA2
za!HrM%#qZspiGVGU&))AltR^Wq6Y>5O<bfAqRHzOc&OvwXNW2eEwnk7Ly#zi>X%=^
zpJA}}mw%&C7GnB=%+TT$5+9Dm7)Ej_xb!@Q1jPiM%0^v>F<G<(h<r^n1RWdHCA)wh
z@%YgG*)J?7Bdzl4$aQ*3o&;TLO|bYbE{_b>^)O8{UO)%^{6vtH&v{Ac^Iu*<8o7w1
ztE&Svx?ElW3j-22@>XIr0%g~T3lZdfj6l=LAAY3~Ltkg8K>E23!kZlld~p$#LAOB{
zzKb4?nohI-`Y_f(zhKc+XD1XW!f*9J@nJ9hATqPCny7aO1-gD|Zm2M<tC1KalgZSk
zHd@&=KbW+IWK)1Nh{n&%Qr8JC5*l0wqYJ4kX@2$i4lx_4jNe;8qxWaLsDC;A4ajL}
z2kwc$R03oOkckJ;=%gc}j%-u#pj!UmG94i)ztbUx+9*IBP5p94eyRd^`L6@q$`#pj
z&wpYDq<|tZ6a9LmnHLBuI<g^H#4{_PNgsuiQk)6a3Yr?PSXCr!uWFxoU31M09HszD
z5%t5YkF;Pwz;&$8peA)!0$0vp3(`FBi*euOPXTM(%#PQ1+rUnqh0+Qf<(Do%lUi7&
z_N|9;4e<4Jy3l1hfTe()dMREtf*I20R3tvyreq^@!6GER4qbs&Vkv{cn#1EO7YU7~
zV34rh7^grW!e|a`bV?FK?io+mxgXFvTggL)1^r;W_OA%nv<$Xt<1!Pv2Bo<?CP~F?
ziqb+-o8E@<Lgt`{Y818BH4%8EW9#uai>({IlYiB8cObS1rr;SXQf&Qid(u|+-0}9%
z=bQ%F*DX1N0=gV=J!!Jo^kWnVYJdfzr*t;@SXa6j=pvNKG?iSBxqVLIn1szm8ARm;
z0o!9<9Yn$7hyHX7i4u7py%QLxh3P8LpU8{~wlHl`#rjX4rv9d1^N}x?*S0=exP2m0
z9p$`tbizw2nawr|GMR12T(@-SO6z)6v#FuM$~<|rKmBY!IxZUrt3jql$5=#?;iS%r
z`EIuuEI=o`OFfzSBu4`p>#rgnS{h4zEp>$b#Mt|Wt=m519!j^N7u;7$u|bOQq+;)D
z+$SZ{Aa36FiK2^<W%Gmqa>*H03*uC1th4IwM>Ge#zzy*YW53hA!j~4`nJ5Mgj(nkK
zZ84FN1LlndPllwuXv*TJ0Ey^i0@m$`Vq1N2$gDj-Qs5-2&E<|{fXX<XvFM8RoayTz
zsSv!Pvt<Zi?TTcJBempP5zllv7ZJ6At0g+)&H&XFbuNR+2Q5}>+ss`e#^Yp-VR;8T
z%+<c$(ZmsIL2s7-{;bSFgnEF9rZY$HL-RmE<JgC8N<xwFlV_e1Bp9mqr|F0UJfB^-
z(ay=e&R13$Xs>1R<+Zt!<Gd-eZv;%8PqUe5N}B8V5kjDnk)9ERW`q@pvdGsX4Beu)
zpy*K_=poe{BqnmjRCYR6@aP$POqxUw6|w{0)1<-lwx~*t0BETVE+mD}VgP`+fR#~z
z$EH*Z!jlLIqN-^ImpFwK^u^vn{lQ_x5^SVi3PYB0>za3Y_%m2{pqh@yPzAEI5ps%k
zU8oihUF<O;9t5a<Le>lp`P3I*Sw_G!@VN>Tp>(2oVSqqgC6XxQ*g~Y<g{fLhAsQ@z
zvq!*B#@G`O?~%K&m_Ub`G^!gXDg2arN(&QBoMNA<o=W-`Cs}?&uGlo>j6{BV^`<1H
z11q(b94s4=-8tCIT-lt!E^g>J{6H>HD;&r{u$CY#Dj?77VFAusrEM{5AFYZ8w`j}~
zE}J<OK2s45P?n{iSe9fBaCN+Dvr2{kMl;58ltW8tKlo;g90EHSSK^kjH89xUpdz|y
zK{{A8P-G51k}#0O{rrEqJ2Byjy%zQg7|Lck0!WjZMIT*TaDi=R+eGGFhMmV~%)JY*
zR82!L0aH|Fp7F_#tJwI`9SbihsMGrP+zP605cBaPbAdYKXF;3MpUirHmWLbfdV5rn
zZTXM_W;R_(HVdS19V|mYVni8&4`SI?<X_&3Jfi=^RgZ345;Il1=jnyaX5-wJgkyAa
z`Kd#meqq3OG58F=W^_n#R4$b`)A(7UARt8MBfql{WyOz~7I<1vD<maWeaMItXz5<x
ziq54p&eEG|oky>S1!<t-n!@y&MyvMOogzb|5IZ0U&_vqchFJx2=RpHOUg0%+7Su~k
zQw-`^%0(zr4{=c>npPzNvKVQLwr=>bIIb1PnTbgVWr(0($`x=@JB>*4Z0GbODfsX&
zMiS}rh7X`2B*hum;|ov(j6%MXq@XTO^gSX1;oU>YwXlsGNnt9c&X|}Qd#xnkWhkXK
zgg|BwhG7|AETi_GpVROFsc8nt3X`kM_3B4*0bz7`NRACz)M!Ihf|SYx8NiYQL}37f
zBxK6qC@*+LIvx-aGt38x*ZIq@#1gn*KnM&szR^*oK;(cElgLFCs*51bSoNUGBh-%_
zes!_*XUq5pp$w?j(Ql9^=1`$?qcvz6O2s3RY6b>HP^$>D3j8r$yKJM(Ta*%A@Es4~
zN#@5$P*jSJ^edihQh-L#F?q0KH8Gy^it~?Y*eHe&hSA1OpZw$BX0O^L|Cr{4;99K^
zzKlU?!q=foHOq$zqB!-S8AnQNR6Nq@lEbf3L-Mkp3bo<>m;Wwd>oqsN#z1gw0GDX-
zL(EDbC#8?^1s84``B!<5WGT@ROTdAQ)FVH#NWW-ABEH740hMbbNEExSJOe3CA-^(t
zGZo+wqxRy{`k5(ax$3eAlJ!h@uHQ|i5+7T{bZG|2{HQx%E_mS9PyZv8PD`R}c;K2h
zemFq`^)+OoPs5n5L;){UBFOhxVQajR7jkc@8BvUDHnIbIJy0*x6rPPL;G~BNkjv^>
z#NX=_P`aHFNpJgt1?}6NO}_Moa|G$Vh%doH#}j+PR4joWe-ctb2zfy8Ko`-EwYFPq
z$faZ9v^<@V=z@Yon;GO$g9mW@4cU|kaWu-SGgB3F!|&n2;Wt<y1|f)^0xwP~iRd^;
zOa&2xb|xX9TSL1O*;NOfR$cRF?+gn*XE!GS7I)t|vPO$ukE<r00Ei!(Pz>Q_p*Jsp
zs!$!}SDLfxNtaL}nKBnmve1ULPFf8brq(Q1u>X8**Kv%1r7W!E>6Rw=07-W$+>>J+
z!&t&L5ZCC@;c+mQo}27s2WQAjRKcdli!k+|C!5l>X_Vou08`-uLszgnnK&MJ0EM#}
z%%v%y3p#aIznP_rN_0lFslQnt<xA~PzGF-n9X@Le4BWN%y3E^blbKZX3B{JxFaZTq
z%Jyh7buCsj%cL^aMnO6CU>fNF!5x_tlrx#M)65)ds_-eTeJbPGXiU{a{tqnG6*0DO
z-e>R`cU!uJRnYfZv69-Gdh#K&%)#cHqZRB3$AA08&puC)aX{8(lo41a(5NC|ZBf<u
zi+OQMW6c;(T4;+hqS!ff7MXyIlhw6H@Sv^lPm7W$3R|X`7$k?=dYA~znOj7ayzw=<
zE>9B^1{NR)2k}fU9jN}}BbtRMt^pHO5XVGek$w<e7yNZ1m`2jFC|&C+AjYD3nRXUp
zpaL<aS4yG!7@1v`Le?5&-m$jshm25068`ElntH4!dpKxD-snO?2~km$c&MwX%(W5+
zg>=?5ZN8A2$;`UyEWM$qK%#1Cy?&QWK0oj~mx(Jpy`QuJDXmN{l7$d{s)=iTN;FAq
z0A^6p10rfd8ry<a`|4DII-;xT*-pwwaYZK-1x`<`vNp`D{m0iaifv}QENLs!(KPTT
zA@xeWAQG2BdMp^s78=WIbY!3k$VPs6lcU5*&5BC^^{NREk}`jr>5527{TdrS`VM@1
zo?#|05-y^GbS1{MCD7tJ5yJD0LdZNetcj+GZfdgMZea3JcBYV`#53iBgH|5JUmphR
zH-)||m)B~oxP$|XiB>>pqPJiv;p@wPaJleD2_gk3(S<-Zq+ueE=!av<i`suAB7H9t
zo-D^s8NEZ8he$P9m2Z%Q?BG|}N30#C11mweAWEb54M%^L!>6v+rXRU2pxmOkLK9IP
zWpb1a7SOt7iWM*$vhTodfLb4WtWyJlT9y>1L+zssni;5TnYW}$_$D+w%$&S7cx(w|
z_JTH)6=R+x1xL{)sVq@mt9xl0GNBq|S%Yf_9(bw>N3>MMj>L`FQfkkCaLXj3a>ew{
zLxI&%3v@|HXM!h%(_AUb$%T;yrMP?%gMjpSA8)_pQ9i>h{R|%EaM8Sk+7JBBxxy(V
zskphq^q!2h#lKidVdG#1w6HiHn&>}hJ343$jgc7s#HmR}2pLPo8BuyM={#f_O}dgQ
zb|s@ipCQsjoT*LsFLw-4wg1-2+;CDRDGAaSG~`m^>S119>28`~kM9CrIxa9_&O$6@
zW76MOP;?%WF8~#>SR};S@0<{Xk(N4S`I%0mbKq+Xh9^Y*SZ<X!D+H9tUo!LwHfST<
zXtAh=@l-!Gs8BJVxcgn=NT5efS>Z;p8Ne$EojO)$B{gA+Zu&`L(LA^pD(H?sCXBQw
zrEh~Be<+T)F`7DF<5okM1swTBM{SfXjxqZe5v<l()mC_4zR=BxK+e^PaijWldT;|;
zj1Cl*Ks-@u<+C8cf8Fxq$G9LOa&7pT%NfmqCL$2=NF&j??J;#+?xbTNXB2i(>fi!|
zK~aEhQ<F$$TG1UeMdFFH07XkX4(rOXYJYJh5R-t510V&hxdT9F1szkr6oIrNUn}M#
z<BeE?Eb^(;yYRBiaD%VB)dIKR3^K@O!n<&a4pOFwfk@(_5Q?f(56B5ST1CYsTLo41
z>jvTKaR4Ob)TuOm<qq*!kmIi&kfcb?Up>#i`xk?i>>@$<jVQuV@x7ov6=In}asg>U
zVM@r*?}#etWU@=zj7(I1>7xmoc%CHDZCWRjr#R?#8zU{h8Vpxmt8w$zS%{G*{uU?8
z2CqH6fHv;Y(5K&PmXpUi?p&w2P?L<00$Nblp<W;<BLx+<X-d_ue??3_nivA09#t;7
zDNjGofF_lqKge&RMGGo=lR{KhbOu%X^{+^r26l3<gT$+cdUk?L<F@f>)-|rW;K5I5
z?#08oUZzIY5}A5GJ!q(LvAM02n4VP(AJVHy5t(SUp6rxKW#Bf#6fn`mNjOCr)j(f&
zL6BDZa_Tz1Yt(nWG`IfmD?(qu`kI&x;BwVq;#?XK8=rX#JIgo0To_tPC$%VbiE4sq
z^T-|I;XD&#jbh9I_1q;H|Kp&s)Va!6{sTMKn}yeOii-K2_b&>4A0wUb`xAbgoX=z(
z*AMr)&xu=G47kBzASmDX)611fEUpitl<FI_Rsx%-vP-RO8^WBqyy$)L+l!dNB};GI
z=Sl%IF1qBBfuM;>D}ug$)R^nGr3*vDl&>@_ly2#fL6N9}3B6COAiK=u2GU*9aaEba
z4Zia!IUI-P<O>aFlV1SE<cM=`Xr;RMouQyoJ{|S+Ujt>l>BI{kW?r>m;iP+H!ZaGL
zy*<fgtnFS=MIja4n$e$Qy3DTVGt8N8;w&URvl=U``a5zoaw&>Wuf-B&V)Tl>niZXQ
z%6%9MU7ESB-py?I=Axc3cS|1Dv;AbUGY}<}|4d)+c`cp{vsmC;LYAjBPy)JZeIs3y
z3~8~#GNrTVZ@hya<sHNlJydHX(h{UL>iQ$vh}OuE;8CJv-ZdBNssHW2$b2fNGR5<7
zK#H^FM*qd0BU(=q<pHfiI8!$-MDtjGieHm&%+NAtCrTHnkVJ}LYt01#T@=)e@$x@i
zq3uH=fk}RGNl(j9&o`2vmbZ0jMAf2M=`sqQJdl~FS|pAYb!dQIB~x)|(YtWNG;jQ?
zx1p6HD2X&99RX29SCr-|T`)J2RD%Xy<8}NTYn@UZLSZtL_>ft$<b}|xg05J>o+J(h
z?{CKWP1A`g6#DB<J7!tkHZ;M6r*$OK&nTDV2tA;l;6<Y%c}z-CnbEOiT3_5FScM!J
zdnOi9ESRDzV#@%HkS1mwHK_ru`_?G~aQ@_DJt~h-URNkMNO^>uf{<hyJ6}r*p%f+-
znJkwnR?GzbsHk^0gQRGU%!SuobH$fdVD_S}X@Us{96@l9=|9S%6;E<S5!9sAu4j5K
zQ6>h#y}mUT<Yh!*<FHLabv<V&Zm%*W9;>3pvA=$YaFsV`O~Bx&XYz!W$z_I?2@s|)
zsQ|oqF+~6Zn(9U%TPDTRswkM0<FM3|)D+dIXH~hC4_4-|OwTiKyM?;_($TlGY#F(k
zv0f{$WC^Y^pD7plL2AcM8Nq0dDN_+7;so`D&SZ?zD>%X*TA7|&0^MU~@A>bSymx0f
zBhNiK8p5sf5(+2&;_fp5Du|prJ4hpW({Sf#Qrfb3zDf^FO~X+%0UhEtFN3wTHr?vv
zJ@>kw&_asD(S0oAGhD4Z2^j<6uoYJN#?N3|WEXxfPR6e^UHz*wkrX;roR%-V1_{B0
zn1YU=B|j1|{=_2!;*Ng;v<_gWW5?0!F9oa9=`r<@8$nVBflm`W_O*A`U&MtF1Vvm?
z8jGn<vu`vIi77y0ET$vWe);3m4;OqV&<V9)zhN4L(4QQsn$t3!j>KJzI!Nl9Q%iEq
zFEmI<)L33>q^@V$c$Cte@~ZJk(@rarD7SyRY5KJwHzUk?nDPG1w@1E{JoCpHUo>I@
ze$Fh=+o)X88?X6_DDxK|Y!ety{15c(c?wew5Ay-<fp;@GJ5S*fV&_Z9w>ZTru&zi1
zjde?LzZJ_LbIJne7WKr&pFdwhojLv`20jCAq!XSq9QoGtocpW@r=^&)hn$tfsP$em
z`^6cbPJ@1W%-Z_jl9zL2JIAXT$>$zxYTe(NVW|MZDMQQ*05fjICt&XI@~`MGvDJIV
z5Lw6V%;WyFeO>@h(c#ITdwYE%mA8_b0aql5MvQX>IEC#!zdqBPgp5>I(sTqZlubpI
z8$B?^acI)@p!3)1;up1_2m3;@{#7d)+&9WFH{ly!>xt@@I+<?$+9}+pi^;G%4RtzQ
z9WS!c5%dRb#ht>Cyw<Lk_rCm4=5q|QF`tp_SYB#Hn>{rs9Z_({wi8QwbL0SLiBFQL
zcg_V>;>+;{HnW*^XDi+W#<8z2ve^qS1|W7SsdjDtP$HRW!T5COnl+kSoCrixR$H`a
z%ca085-SkXU$9?zCrf`F<6h^|83p5ZE{@XnDxfg=sc@lX>ao-&KINPSkJiU31*VQQ
z6kUQ^_fDuo5$f=TEYqZ%k=u-7%*Zvq71x!DNn|NHsgK=$IUMH4Y!;U`7GlpVMM|Fd
z;#rwY!OelR%vaeaMkiSp#ngo~buxfWPOkjZDfX2d$r4>y&=W(T<S<*5jS-g^{MQkI
zr41{xfI@N+Z^JkoX_>v%NZnefKh7w1BRW^Dit8VM=qR=+sTy5VA$4nY5d>}|5e$i@
zc|_jDGXjmTGp|g#2uWqgt_SQyz~uqM?X7=$1~HE$!mV!_AP}?DGCeR=C{_E>KPs?1
zlz;WPG@&AVh*Be_V{Mui8!YDTIbg%D#Hel!Sb?JY@ycVtl`I+)UdFW5#;UX`)<soK
zV@s8Q%aI1J9@_9X$v)hfaA~S%jIu{H$8AYhs#KOtZ=Rknvz}N!dxBhUC9Vj$969EK
zTpC{{Ye;x0!&H2Kur=u6_z=li^49sPrjuKLqP`*~=6o9L)SqayQ-7!Ds^c+*FVpw|
zbDm=?k|6q)`iuI9Iyixqe&C6u*RiOH&8+MDKpI`6*l003?Wl?YmK)KgV*@NE+7~&P
zL0fSRqdmp4Ypv~x`(3=OW>smhDAv(0RL$~e8Z+4naY<s!0PVHZzp>xBI^Bk+e9KPO
z&b%Z}746m}^(kQR5V`epoLnHA>BS`%1D{yc#KI=r6JHw!xYLR+grO?-voR&BQrMb6
zQtps*99SoSg9eWKWC)GKN+{;K*M55;{fl3p&#D_}<%3x4Br%Kz0VMiqL0iH2(t=-S
z#eCAD?;<{{tSBzFF>!+tL?z&ra`c7*t6nG-#Un^ovE5g!eA0BpoJT!#IW1@sV7e5q
z8kVl(yo>Fbf)ZD(i8&L$CT$=Q5*5rxeq0uxG@5mtgi>Z{dt%Z6={WCGa{>YCj>^*C
z$&h6`LU?g&X))=pF-7Vf1|*s`zutPsJ3Z>lmoAkcku~&~fa3C{K~1&g89DNf#*|UE
zNk11a3uW^OlX5aVFeM=5kPsNp_lgHVJxI>l;Hvv6-TdPm8xf|jV(}HTvUuKB@ZycP
zroe5;q&&FB?34_owgu<f(jQ=#NTXuLYKX!xNgp(cU?Z{(tRoILo2PeO7!zX4|GJ7&
zz;eq<o!q!A-P@w0<BNr5@=9hZFimnV?m`qwTRH#ulWYrac#Z7XB|*&Tbt5W~Vk>Bo
zcXOCQ$+hlcLo_M^>WPO9GtwE*HsT!>1h;GcvpK;~*Kp#AU6OR6^pK^?B*s<<F)Ll8
zOt>)7rlxmHXl4~u51k4H46<#q5`hCGSXnr=R)yHv8`r%3(vp;aw<Rgrd#<{C-b}d0
z%U@U+(RCDHBDkAwDTwW$Jjs}Rs+mq=>7b_@5HnyLX)t(uD8@XzedL7>O<!n!hrsn4
zFEr=!KqhAnfMgFCX(e(6g}SdtJ;e)usS%YY#&|s=rQ0Mw2nTcZIuezZ5u=4XBtjOB
z8Au%RMTcXbuUlJbh7F$}=_%-mgdh#^DUST6zqV-$=7#Z0AJUf@KW|!UiKojPt0M8O
z-18^ly|2et`2}&1(;Am9gD7^>UuWG-)kXa+aO?Qh%D))DlWsu(i0=<IuYn7y)0X#H
z5P7IW&`$i^>uV#<YwugoxYgA%(+Yhy0!#y(0%6oXl8zsQDeFO0f`*1h#m*T{DR`ZV
zM6Lbmt<woKgHJ!6|6T2H8#N(9K7t%n6da|PQZKP+a;8Ef4x&upPRq{!f}Jf3j1UpI
zh-fA5-2B!4c&iZ#S5wZIl)|8bCvaiQ88WlHJSFH-1EtPd&;-chzgBzcSBa_{x~8gb
zNdgww8vL2CCdzEeqL&IkP!{9P7HOF}CD`hUi75ghr1H+(ibRR6E3z78`Qg7@tlD)4
zW2gd9NFexW;5?r)Patn*gcwsM&*dG!z*C3X$F{{cF`Owz*QBU_Iqf1gd*llKX|O^?
z{_A@U_mLmGLaPZ{deCz~G%SiNg@-1<K4a$uT;RxZHI1e?@^i<N<iWq%558i@Eu2O$
zyJo1u^9`_7ZK7c_BDqwHkU#?lO%Og4A!K4jBgu~~CwgRrxbj9&rEMMWx8vFoRZG-L
z@vM>i0?IT*&^j@X=*c|J6`-l`y{uFNt|(1HWy`7raZa{0jlg{2=66zgfEGxi!AVmP
zz;Y*Im6ERnDc#(~p#U^Dahev_KglRAlD<+lJI9)SQQK;rcUPtrFlp5@{-{>!x$!qw
ziDVC}sXwE_g1Z@iLQwtp1FuVY<eWytZ#ElvF)FfY-Wt8s<I5;rlmf=LAqwj^8vFXs
zt&iz#4lLQSAJBnz-iMkjmQITz#s-Q`^16*oh(0uiOsu!`XYc>ahG#C5s)q|=-9ri`
z!n}5BkkLkrb9Lor?qaeK0FI#6WX%O@#p9>?w*D2<c%dKrA?1kuMuc&Z!9}AXXbGPh
zn-j8r2^_s%ou&Z+<<^$E69$woWXd9e@;huPf%cS$8;aI?G+4;T(0-;8fOd>Onb|aQ
z7#h$5ofe2Qf6lD^&jCSSI(q4Z#3VqCHEbsoMJq^i7Jy~!1~eABNXyo@C|5c8lV|b}
z2a(r4^RC$SL^=$i4d4lNy-W1Om{{`il%Pq%b`Zc50)cg$T}5YVOD;z3sl2pyO%VV|
z1!(y3RV%U*ZH{0ErWAoS7GP@B^OEY-`^Av0ysy3cL)yj|t3VC?;>e`*eL^r+<x>DO
z4=!g^a73AcD6%(zCJV~c67Enrj0(%`$sDKDjB%^CK+p#nbRcPhqPaDR=B9^-F;-Kt
zZi5;3GiEfcFiE!#5Zjy;xAwa~w<Q9w)|d2VaXJ@X9MNuEx~M2&;<&<wcxTQ?N(99)
z&ghm7&a&X&HaWMB>Y_;0zTSzy_W7$Wt&I40Um4-e!S3h(>PY7TX|56)O-esZi5B|l
zY(F%kINaH)cY_jGb#S^fll%Jf89+@znEI|0K5|VAZ|ZG)Ba+lvf^AMkn7ZBbooQ$S
zqVndREmHvIxG9*%JwK3~<HMW3n%XY#)M!sUI$b0|%{~{@&HycK9Q)tX&?G16a^mpj
zwa|z)>srfyVb=3SJ)Al#eXf{6?>WLfC#EZOj?d@yYQ9|#?AcXtUbxJPoUOg8J@;q5
zyx@mZE8v0wk#N3Ab}_ijN;}_(g|nbv#KW7o9bN!b>hi6NS#$vfIz5S~d+G0dPG%59
zg_u4W>`gQXy;0hf)^WZ`PW<!n)6uw)H)8&&Jv@FPN#{;ObzkaK<|fUV-a@jvxP9&$
zTZx1AImzF5=FIP1;Fo4S{@rFh7>zEf-R6b6=>X$U+wjp!<G%jt!Y}E+$22fs;o?P$
z`biriq#pV0GdN~k0Jifj4qN~Vb0@ik*xYnE^V_#7#R}#p_MRE*^Zj!1EonN(w<^WH
zf3%0`y10ltJ@4^}`H?2IGJT|Z#;TQzK#Zi>rhD%;8KAz`By^0*=93?ux50E?IXZi!
z`TJvKj0iRrtUF>3pVP7D%oggIrtmqW_S(Dke#qaOz%N<U&t_4-xISxU>Z#$@pZWFz
z@2~OZuid8adH4Ku(z?gL=c?Hv^^~jn`IS_|GLGH+*6cTpsmeURQq39r0%WI#f5PeT
zYTx|Nr@y?=H#18a&ljH+(wkuRuPtXyea;bPVs_4n&Ja=PKVKHkf_bBy_B>DF0yyK$
zInOuA&YaVEez}C$`4Fsb@U`cqW7NIu3xAA<>pX>~7eD{KXhoOO&o>*+SC?Y!_`UfX
z>)*;f%J;5}jw_7zwmDauK8`u(8udH9@493}KbsMK-kO?t`_EHPs3)!~^U_Nj(&vBs
z&*uj*ap!pQN57YPlyj6kPb1Hr|9uWgY#xBcs>x~DoyUs@UYb`fJCB^t5_QHHcm}th
zvjCX+`H8Q6FLBvS%+KTgtvsNfM={P4bp~IYCFa>bU!vIAX*4^=d{YcT>wC|LKK}yx
zY$9L8)Avj3_}&%JzpI#EGNS+gU_`%&=GsU)-`#2h?nPg}%ZRxbj^N?xT^BDLNSyNY
zLY|X1`rO&pe)WmDKU~P$@0afULTEF0noAU$n=WU5dx>Iarp?@6zHcaow=e5a>zfBn
zpUHi}uI6WUXuoIAyXL0#1-w1IJHG%RjU?YUb=@fNMPH%V_pX=tcNOzX*7LJj&o7$!
z8UW%x;0zYlLNbmf4g!87#hYGVcyWHVfR;?&tb1y>ESwuw0JBd#eYU;A&%^7b_S(nZ
zlnm$falU#^ZR0-GmFK)LIVJL&Rlq4x&;B@HrIeh$ZxFNRXD$jK%1cW{&(5N=W4tAq
zOlB30PyFs|OfTkXo}1<TFs$y~UwC?I1A>bwpiX<q#YK}rSbDzZ-M@dl=Dw?j=<iYB
z*$vlUI+W<FhZ0?MztsS6aoc0!x-=^s`POCP{4_5?de#dCgvI2P@V-k+<xZi<Ssve#
zLW<!0)<8_G6sLwgzkeFrof_qwpXalb-#6>J&Y8MrjX2N3>sj+V=LqwK*jrbn7ZJVo
z@Wykd$k`$`o%ry$>_&CTjDBe=m$UK8Dc@;q($AlVgZ6nu{cdmN(uedUa?t!Qa?QTh
zpSWa5Kbs+azSLpkOdEIwr*P}JJ=T8wp2`Kw)u(1L*Iq7Xu=t;vbk?&Tjf@-L_wQrk
zpOy8wJj~aiD|yYQU^nlpl+J}1=M?7>#m<RL(~&O8=+m?~$Gf*Gj}=Zl{1!Dfh_UA!
ziF@{F^VyMIlF?&&!_xCJ&jGmapNY9kGWzN3M=#0ffAq}oS<UF*bs7Ea-RN8~=msv#
zj4pFNr-t-Zb1Zy3HPSggUvQs4mr_vskEfmbbdG4u5$#lAppuv)(z(96=a*-%$h>G^
zN*|Of$63^a-?%xKYi>FcnB22<{^~P-_pfuv#f2%7(@1fri&p!$M-A4J#sBM{&%^b}
zF!D2CI!3MMB{_m)#=8r=)yQ45D?aOZ9st^AZPj`2VM>iRoZe0?#uFQ3W<3woyi;K`
zo-N~nr>B^=>7u2*FO5u}P}a!e{I3;wg7Czj&E5>^`~gj;h<hR#`OhIVWs`3ntM=?q
zzIlZ6`8u;Ja?U5=9C0(X+y8Zr*BAI|24;o+3-2JMi4z|A=0&sDR5_$N^-jElMH|F)
zM^Mn&xDp34(thg4&~oLdkOW7g($j=QD#|AbrT;Tv>C?dB1QKjgXaSnz2pn&5dIQW?
z0UFvaJxWcAf*g&iP7@V@<}ru@b-Fk*XfXk=oL%6ep#;4D$+bm=1$a9WP!s}yS8)k3
zH7Evl057H0P?BN<UY4q|L<w}!4G1i70bNql)uGa&v`8?Zqoc{gNsB3=vC+jDbVC;K
zlHRB*dw>@#DKG)u=>WX784e&`QDA9cWN2W46rFH6@WsAB2P-h4*5%-`p#@aBepurN
z2_F?FP}nGfv_iJ$gM8Hh@in5XX#py3U<A5Y1E?2h9TYeLN3|6?Sb%~J93H?R2bE19
uwCBO3DW{Rr8pVc@-R!_-^QgnHg$h0~^bqU7rx;z%fe}^Y!)eL?R09B%#$yZs

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/MoonCresta.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/MoonCresta.sv
deleted file mode 100644
index f9a4938a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/MoonCresta.sv	
+++ /dev/null
@@ -1,193 +0,0 @@
-//============================================================================
-//  Arcade: Moon Cresta
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module MoonCresta(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"MoonCresta;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian mooncresta(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-	
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 	
-	
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/galaxian.vhd
deleted file mode 100644
index b881e738..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,446 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
-	-- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 014e6f7a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,88 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-library unisim;
-	use unisim.vcomponents.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 69a20cbe..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,74 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_video.vhd
deleted file mode 100644
index 6c7c3250..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,447 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-   type bank_a is array(0 to 3) of std_logic_vector(7 downto 0);
-   signal bank     : bank_a;
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1K VID-Rom
-	k_rom : entity work.GALAXIAN_1K 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
-	-- 1H VID-Rom
-	h_rom : entity work.GALAXIAN_1H
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then 
-			if I_DRIVER_WR = '1' and I_A(2) = '0' then
-				bank(to_integer(unsigned(I_A(1 downto 0)))) <= I_BD;
-			end if;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= '1' & bank(0)(0) & bank(1)(0) & W_OBJ_ROM_A(5 downto 0) & W_1M(2 downto 0)
-                              when (bank(2) /= X"00" and W_OBJ_ROM_A(7 downto 6) = "10") else
-                    '0' & W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/scandoubler.v
deleted file mode 100644
index 2a921604..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,195 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MoonCresta_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qpf
deleted file mode 100644
index 842b51ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 14:59:16  November 16, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "14:59:16  November 16, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "MrDoNightmare"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qsf
deleted file mode 100644
index 916a3e5e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.qsf	
+++ /dev/null
@@ -1,190 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 16:59:54  March 10, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		MrDoNightmare_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/MrDoNightmare.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY MrDoNightmare
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ---------------------------
-# start ENTITY(MrDoNightmare)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(MrDoNightmare)
-# -------------------------
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.srf
deleted file mode 100644
index cdf208db..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/MrDoNightmare.srf	
+++ /dev/null
@@ -1,54 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No output dependent on input pin \"SPI_SS2\"" {  } {  } 0 15610 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at MrDoNightmare.sv(86): object \"m_bomb\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/README.txt
deleted file mode 100644
index af0153f8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Mr. Do´s Nightmare port to MiST by Gehstock
--- 18 December 2017
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/Release/MrDoNightmare.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/Release/MrDoNightmare.rbf
deleted file mode 100644
index ff1dfc16305b333094f0d161846d06fff35e125d..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 295678
zcmeFa3z!^Nb*Nj_YMGLdVY)mh<;F49rN-H6za-fwXQDjlDGjDPDA*Pd6!NenIEiph
zJ{!V4;gI`X*RHOScDLHrBZ3Tq5BH1(w=GEgz;K-hVPupr_;9fuIA46p1KZ)An3EeA
zk(?kNiSNIvr=*dr*VrwNd^~Grs&?(?+H0@9_F8N2s(JR=)59&_&ETJY@SPw0;QNQa
zcjSlv`maZR@azwN`0T$u`~83Y-uJ$D<j4<?9Qn8JfB*Y>{PY$5FP~}wF);To;RSep
z6e!NZ+|qg63%N^u4lwsVw~Z6Sd0TmW9T)-fc)82-d_n4&3wiygy65fX=~7nO%;V)g
zUmPU=TpT2v*MF*e-d>(AWu%@w{`ubX`p)*Ax0B}=JOuJNn8%;#eyaQupTmiDNW8?I
zcu#-}0J#?c$s;()T|nYagkH+AtEA_7^VmEtf6ni7<E34pNuDNmNf*e&T|mMikjKk&
z4iYCI&%IDDoTumaxoLC5dAi&sKF2A~Q=f%AUG9R*D3GV+cZrv<+;hm&A|MaTUFwlG
zmI5-j1tcy9q02Hr^0WXcvmQtRiI;SF7Ct^5Tn9+{>t{jg$zd2+Gz<0#Py!@sY!>ol
zDf0zjJ0MAd&!JiPb6{?G?sFcW-*X(+0aE8&{u3HVy4(i<7m)r6NL&uRnBG<JkWhY?
zK1*2c5-%WOiOWIaay;_(^7)bXH*YJyOBvx2!D|r6%S*b9p_G@nM}V9MrT~eX3lf(@
z9xwUxaNeHWg$HuT@yh!k>3Kh-K54%L7+@Os3m|XjRQD%=JS}fu?wbIA7Ni{k!9(s6
zE%#3XZJ+`OZc^q;fW+SkNSZwV^(;s@hdfU1e+$fgzVQUu1qjUrgdcjLfdRomK<0#i
z#OL&oIhW5bp@%#RP2?^h;f=G<i|NIE4R`{Oq!ZA%QR<)DzB~)<eg+Uc<T;0r%!0%V
zZwO6=|MRii2ITYMbaUmavykVNdUCur0McHLQ-05Jkb91YggxLkK&lix_5*U4x+N}e
z<81EI_Im)qN5)-vPue&YTrvxJy7b|fflC2N5<KNu_(Noyz}#>zX8rna%|f0g?QfX_
zYi1z;Bq&J|&fyPcL7r=X+&>No9p=JZ+DQC2fIMC3vlqyp<u3DAK=6?<7s%(W+yxgI
zA8AkSGCu?rNfSPmvcd;~OAe>wi&Kq}v_BW5J%JuZy=yO~cm2~@kf)qpLSn%!hn(hf
z??V5%AZc@-=i(q?8TXUnkjLEtNP9VM!dw3a<T%J(p3ekx<%opyxsu=W_D*%r+so4h
zcj;RmFXR#&Brb<D;UwvK`}tkg*nBRWNE>NeWT$|HMSi>k_<KNjP1awz3s2_o&$A%U
z63pZCyUei$Aob;OGH>UCq|F8C``qUqM#pdxyakUO{?A#EXTec;ROXSiC-(;d!A-(B
zNSw%|99EqKgl5uK4tD_}FY;$uk8<2jc7GJu2?&2mx~xxmoWy?)kUE9NqLT<*16*_h
zNL&t*Bsd5N9-<Ejp0aj~&qBTq%UUBKX}wVI`VX^kVw~V1@LRL6Vh-f(&%F!&0(qR^
zA-ta<$3=Kno^zNxPfr#W=f}4J8UGvvpE+opG<feU2p*C_(3g57TJRIv&uuTqNA7du
zPYmZc<YHdvn(H7UKXVYdDj+(VfW*tQtX01NET4ss0`e?+huq%+2o7==cq<@xi4zcf
zM1Rcj5c*0upBp(b<XPmG+(jP}nI<4}{bE3L-Tw;YdbQmD>@;wqjQ?+d#N~M8cWG}f
z<hbQ{3Eh7mkUTl9Wc?932uL^wc^10Ny`LD)`AX=JgUo?kPm{h&TR9$*CeJ-BZP_xR
z(Pe<d$r>#3O+dy~M939@q)FU|0MT2n2P9o|HKC=%iH?@fHOVLOHvw~TlC}k8zRF$F
z<Sz9K2yFx;EV`rIrJYaAf`sn@<Sw?D==O3KJ#il(;XF>Ba}b`(L3l6+X<H!2L&Tjt
z=QKSL59yz@okNb7$PBTM<-TJU{tNKoS;*r=mc4lvga*G0$UO&1lCa<)AnSyH;M<Go
z#pPosw32Xs7rjivw*prKlJ@g}#N}(|Re-GL0y2k1&k!Cs9pq(&9>NF0OTzoIZpiu~
zAkSw4Su+Lld{U3dvK&4I<nl`H5}(f-xl5k}Bz!p__n!cSR|EtPxyxLZyT}QNle;_%
zNLb=>kT@9^0l`Q5DEf15kIOwDpFHlBz-xd!UdHWaK;i^s{gP*qSE5G?NcdNQ-c#>7
zSGLO7N&9mlZ%=T_A&-;0v?Cy4!Abh?6+rkZ2YEgb9y<XZ2j)i2#X-WtdwKhEm-YlC
zEHX^^OJu9a8UdO2e*;Kd4)S~^5E{(|nX@uCbCC8<20sL3?#)dTT|(ewaT5RaS&;C2
zU~YX2;ROmTP+)-qXG;N*e<Dwh%O4--ZayyQBoBip#C`4~nRYiPc4SU?p20_VE}LhG
zQ)i!f+f64V){pZUpOAR^$C)1<C)-b-`An&|ziRQBvYd7Lb9;H#MW36o|A=|`hlT3V
zpyE1^u}aJ}v`ERJULZ7V5j9YZ3$B$hP(6@xQrI^|3Y&ofrqoE)3aoo?FJwjX^4WdF
z@(YwFJdhSGDjASkkAqzs$dZF!vFD&*J^Ge{=UUdNRB&Z@-R=sFS+4@qkzuQrRO}l^
zIwKZ2UY}Nrof5IHm8z;0F0U_Iv1G7RP`2xXUk$4J1Iu+cRW2W~$`#w{yp@XGmU(Tu
zBCuVPytYs)SoOD5D;?T+eeu3`ETIyzMBJ>fBn|f_nQvRMbmb^WmxPIhM1Eom%`9tI
zC|4<L{33;uYD~7_N?dsI%P*ItzQB3TXMO3TWxb#YAbdR+Zig}Y1q<XqBPGvY^3Rns
zbYtdiBWLW)S!bBTv6=8Y>w+iCcx!Fx$)cZE+yckWmuxR$ik-mWr|bEQ`F~EAJioL#
z+&{m9C&_(g^8ZilrSF^s<L47KIP>%upHI1ym-*4s|KvEFH1>Q(EIBF0&m*#a_^*HC
zc@#TE5lD9aVrEW(^t_`79{&TGN-o+$DZnVf%vf2pR;5#ER+W!YFi;6~!K#L$Sg&)|
z_h#O_3(Wk^o%2TSlm+_D&V3u`+dd`6OMl?Z0(c(n^qXQdjrgy_7(Ih)mMvar<mW!|
zN@^C>H8YT5MQfH5UufjaAAesKjdM};s>A-{YaSe)blof0y}BC6_1ZP-k8BHHJ-FtV
zk8Iy^OXc9$&1!PFd*v5?>55u~yni<7UYg!IBxR1j2Tu<l*>?UG4;};e;NkREwZ9rj
z4@YMoUj5y^t;p8QkAGqwjD3cz@O|H8rS-4nGqg63<a00~=h6D9vf`0??7H(&ggtM>
zN+<8?t$&8(>Jyv?g8D=+^lZ=m_~t%!k!oPrzRmFkt$W_%avm_*$#L!%Vs&vBKDNBC
z8y@{(*lcn=`rx8|EhKfj^t!vn7dmexdcFlp*1g|7fA?1UGdj@mB_&SIg$9dqER*{j
zY4l=Uor|h3dS#|?XBzcz5Qq-G;`8XH4-Qv8KX$wN_;UA`kBkMkR33lNpP+D)7w!A0
zOuw$4cn^AN_<349C<yMyDcrq>2j2b4zL~Dp*YEGEw>$1R3WTp-5R|Ne!#CgXf~q*K
zaQ_r<)`fdt)z|gvI7DC2L;rdy8#E`L9I&#*y7Ig*{J;M7c@;Zpp>y2JY=8dw_44+s
z`fFeGZJNK7JX9y;nR!R{naTR5_4M6Q(l;JEUzZZ>i+jb&n6DZ={{k-wZ+G3k`lBzM
z<?mc*urEq?_u$%P3wn3|^zOdzTK3CLVa@Ih&U?W;X@Qd{ktfY}R*`*PlFzEmv&yu9
z*jbTjPNwsjVtrH9UQ!OKIfMHGg8h~keN%4xF0apD%=*2OoO8W<(7N>-;#ltw^qU12
z#L4`|rMEP^`25}U@*E+(aL(kr^JAgY<%YfbCVIu=(I;uifrZlR?&^~i6A$LSwe#^n
z2P1PntA3|poOybMXU2Z-G?mRW=|@O1+4X+zJ7cHB_b-oovHO(S&MJXk_HC`S{{4r~
zs?D>?^dltyS>bau(*j~gNpY5eK2xlJ{L1mixKCTB3;ynG@3LR3{DQyxg&yNLr~Yo4
z_~*b$UqAf*wF`Q8|Mc$q;ScUUPo-t)A6sX+dYnbJJ})q5(c)QVSwQS833W8vONL?#
zE9KEKKbt_m9fW7o=2_(dvHpqJ!AC!P!CAF>Hkr<A%=)Ky_g0ery*+s<&$;!vzweu^
zaI$lLXEUTH&x6eD9}B*OZ1{8JIhH{>2g<R9MlXxTxu|;Kc=x$F-rbikqx8w$4fCAS
z*DB@vP|p{(|LOBBc|tjkOV7Oh;0cj0;IV%SDZ357x%UNNa(vOs%rAWN_?Q>+)W2Sy
z^bGs+M(w51%NOhR%>0J+d{*J-*OSxbK3`{2-*_zBle_g|IgNZORk?r4c;60p%e(0_
zA3QJD1>W%a&E2PCsrjXy=M4DbQ@SDlIYN5D*WEu~ci-fj%(i|mRRf2A;rtXkeeLCW
zOa2AK=C^#1yWcCwf~$L8L(os*)9<nDpPzBT)jcn!$TBaux)Du%W5Jiyn<D2(gB7+s
z7Y^xj=j*Ode11Xg?&Bu}=g9FF?(4R0{^pXtIlIsCJC!5zm*07b+n!nY?+7_9&hFlC
zmGtadJ&Rl~1;k!b{;9JV^Rviu-s<p!w_bdHzM>*$70-gOXPKp+)3S7H_T{M;k+WNf
z)K3cZlbZ)0TYi2r;JKjKIZ}-o-WQiXzi_aduXw+@f6nf+5tjASo>r^#w&GE^>uqzN
zjz&MPz^t@<US%nC9A1|7=)JEvb4>%M?dh@dJ74v(V-GJd)K8IkE+o$j?A~ng^K}t<
zNl<J-?VdLipSQDeLG7ORSjs}e8g|mNBm+)*iqj|hc@{bRFVD;y!&4UMx7h602AcI!
z`68+4KF`&V;hE<;tLK?@=2h-IOUwfgD&J)KfaJ-We0J;=%fI?_4-P+_yxaTgPd+%j
zCD}gwoBRWupL`<9{(;U<KCw~$gU)7sNA@ptmOt@+`Ih(cC)Q^FL#O@i+5e#<_otJ?
zUiMFQwj?`y|3&A;R|y)qe46~uaJ1JOo^R-0*te;6zJHkYl)`IX3FqyCyMWld#*xe~
z8H)L5X)d0bfG?qUrOr%@v&r$2;jyzJ##!ZoV*TUSet+)-O=v+qzsc&G&aj}KKgVG{
zPi1>SJzr4I&q}T?sOM)#ra8I#?bVo5^$QCwAU0q6ozE2OpSrW4p3jpn`mLV#O)=`X
zwC*2|o!9?Cx!+Fmll_PKo-6*=ooBI6dzReTZ!YZHV83(@jQ7J+esU-D%@zBcR=(|=
zdHx5#-7GBl&yQ^foMZp_Y5(`bS$-_Je(YGwqve9^tn>w5;KA}aSP43(KjKoIAI2ZO
zXny%mm-~EH5>JQsywdu;*vzZ((`8;j>~z#QS=s`{PDYi}#hvFAJGln&LS2OM;hTQ@
zbVQk7+JcarAHB}sgXu4cGlegmUEcY!<tg)@*Fv&i9+sEZ_x4XY*7Hi}v*_=eo5Gs&
zO76TmbkfYQ|M`nq+_$3~@@a(ycbTk#eH-lsci9U+gSy}@TiDM&saQTS^0e-<6EmOj
z88L9ac*~B*^|Z=Z<@mg3e46>z=gyettTXgk8#wEB&zNxmu``nBgbe+r*n*ON0)bEe
zc-lFB`l8QG?ekdnO*vXn(w{q4XN*};(lZjl(|zN^1ton!Nndy;EPuuAf99U{8KvKe
z84v?6LM8pgUYzM!7VyA#j1@b6A<G<`uE;=9enzZeeyrX@Xoc25S{x1ssv||qFIs%T
zzQiW{$fF;;u&zp*!z&}};!3zBUB6`TilBIdcTia?uT2M=dp20>J?HAuq5W3smaa;F
zwD~R{Uca=iY-x7pe}tV<Gg)2vgG(ymZF*?vSCjgXciqAN_6ybbr4yA#X*^sP={@1V
z^hdnM+^<Gnx1_vRyH~X*;>Vl&!z=7Vw?zlP6YlwWtr~jw!|OJB%{`&D{$h359bWIG
zN?mlYU2%gS->SC1_D$aUAUf#2CwW7;T?u}dig&A(#i_ki{MIPl^^m$~x_z~_YkO|m
zR1GiNUs?Xe)|Sbi*M4$1m|pjbp1wSE-K$bvT6t(}Xu0!~_Lnv$GnZX*x*?li+WZx|
zxW_h@v0$L%nJ2Mscw!N+3Kx4ggxSq6%EsdfkdUj8z3CB0r*b;((o*QNvb)%;>1ZA9
z(NG?UsU)znW&D(%FWJOar)AysaQ?ACShoj91HH#Y!~oO7;UZ4V90qx;7v!mzA&<9S
z^PivF!J~<D15|KE`01fMOPCWf&JoR1<Ssaz9>|ec&)#!}|A1$tqE%U5Yi@5#f^0=v
zV61wSl?ThZ^{ETF`o%D^BEMS9kc*2E_hX|Zb!G)qpIW3Q8OvU5mNe%QE0V1l^Z8>h
z{v4}lPCkNE(3Z?SIKH~<Nm}c{;LOISz^@pmY1+FGABOTMF;Ns{`4Znrs5ZL^!c-v7
z#LiX~OFA7uU>b*Co{VK6iDZf$lg!-xwYWGJVF~*XLmHs8G{7HKaBKD+vZstJf&{hn
z1hTXsKSp{%qa;{QK3m8t_fwc)wrUB`LI$&Fa-$g|Oe-Mbor<L*31mZIXf=_r1;y#c
z*FTz1ge>y-%WOTp!jc3!W;P3ViJ#3Pk-cnJ|50H!hXrfo!K3#)e=l<uoy?ZZ^YqZm
zpKiGN!Xye=Zu}yA7FrSA52Ki%U*sy;AgoWHvs;GI><Ics@dJ{QM}j;Eb%<iH=?g<h
zH+o@{TykXf|CZ%F{t`<Y^jl;>c9W+x3+0%e&?)K^nC;?!xxW)dVI*@UgcU;`vMxy2
zPw59~vkfFB5ws}JD7DSFgkxhAC=2qYhdZbzgiUsZ5#=FPic~@gIB}sKschTffBckC
zOlGF=JMF<iVKz~jt3pQF7Q)dA<p~MD2#**;qrxGAkFYs78i%HMlHVkWjZzK`JBBuW
zB@YDe`(VM)qA!Ef`?UmvqrcKuDK`5n*dF_Z!cq(E&57?tKDR*W_N_19l#Ujyw->!=
zv{<_3(6I9Nk5t25VQ0izrw*l7XGBkt)cc=02O=FPr}~H)4}E7<I+b=zGSD?`r(=A(
zwZtlsp<wEh?Olw|I%mDpGLAN>)pFc;!dMrnQ9WrSy)_;ZDLE2LQ=Y!xUn<bF%*P1%
zk};`8yM#uIAS2M~LbjIU_ii#7I}oy^XkL;DI`W&%R|ra~5SsBMixiR)uxnyAX={|W
zWd2iiEWyqQ6C{)tdyT>3P!aqgC*|__kToDRWq)#^LE6bEp2)b+yi>}Wee(ZZ+=--(
z(UcxU)~K)wwF^0k&j1X;iGq})n!F~dB%6m>uRxsyf*BJ*0Hz=8<kQ$C&b>p6;-Zj^
zTIB|>2<yP48D#QSIxhsFA?O#&Q`RJpy_$uR!k}E~vQRal8R-nHLw3Y-_cJ1j{US}o
zMOvgM@@QGdnxeX1J2FU)^h`#Kp3udkJ)q?t$s|+8l38~ov$Sk|d%Kf0A^qVOM#{#=
zijalUMJP@wC?F$!ln0pCV4L+pVzXhE4#hHx*@cJM?)lElSGLrhDF5mT9e`gWYbv#v
zZfQ&hZ7bgDshBD+kEoRtW7VY}9@TBr1?kR8kjWE#$AeHXKS)V}vDORYOc_vlbi;+c
zI^$wp7yMphsJRZ*OG)n?978rTCoCz4vcxJMSJ0Al!Lq<DIogn*=7SnJ!7R(J95AzH
zp7^IthM3R;|4a5)Ny`vCBt1)!9ny{gb(58Z+#oP3H)1=nHf7z7XK^5<osA9MvId0^
zlF}<=O>vj?`p-5E|Kqw>SFiH2@3mAfdtdhXmUlGnNN-gS4sUMUF?PH9`10j^zGW=n
z^DV#sg<ra&#%&$9rw$&ulcL#&PO>U`pKGaJcBJ?HmKR|q;pn7$Y5HwU^{YJTO*s0U
z^lMP>tU(JioEm1_>rb6H-xREs>7!+Y?J|J3jstb{38u*);F`pRNf`VXu++uQz~SJ%
zJ~N^R@E{-+`+1$hq^AO=lZc26;w+y$%-r>yFYku34j-!}Tj=8g5j}kJ`R^B`mf%>%
zEMyps?;glxR_~%MEt5lsb%zDr5`(Aihzc(tiZ-CKYrUs<(jBH}oGeNbiRX_hxiD2h
z_|{Lp;wS~O09AxcyC}-4CZmxiq+&6=81BRe_t<raQgJ~AYEs1^{)9RrfE-!R$RdsW
z+xtZP0&<B+jYpiiDq7`1RSd0EvRiE=#%u#}PlId~v9wA>5Cu?WGU-}DY6bDQ%CcID
z1nkdjd7Bx$B`*55)I{Z0G~k4rw6*If_H{?l--g^8htSiC+LLquA-Bt9osu@uVha2Q
zpdN@_+s;f|mDN8^^2~dGOzIZ^<;=v4dYBxIl*e6)!UNEyEnigYb%R?WHX)6~f@9WW
zDZ~>J{gL1F#Xb&+h=lBMI_%H`$&dp>lvU-U5<+)bJ7%jf@|5AL2!J+_#aT0#Nz5@o
zh-N^|J#v7C>1CC8w3%LdcI{O(%ZSh*Yu&QmyqJ)vuCu>ZBh55Qc#ya>P4!&7d#L)(
zY`uO7`Ue??Fil6pgu?AK1)>S7`jLyLX{QJcsJ~YT{s=eC(ks<4yfko>ev*eFGl>rT
zP$kY#-~}D8Ww)K!j+2TsMRvj7PqKCgZ~MwCqO1p&Xuw$`Vah5B_w<@fVaU0Cu#{$u
zwC_M;M`}u}CzH%t3s9Ju6^Xx8ScIe`Mhg}@^6H;@g(zgb8d)`a2vck5!<_KQ+z$Az
zDG-MyA%seNr3+Svv5H-(EZxI;6)!Qd3S=G!j4iCo@9p0#g3K&v>IBU}N7Fe=&mG9w
z934e`o$?t&#+U~MNr}6?VRvC6(gbe1`sI+n7q&o5hw-4(6EI$ee4fN>iVR&=p@<YH
ztm0s4+<3qXB0-T(%vMP@zYzEd{j;p?-+;^G*#?e<@>->(RA`g~^VJz(TBdG1Y-}%R
zRdgYiSzmx&enpgmT-41Ryb9jI+&XIFP*q%PqO)c(kRX-c45W!{p#8!wlR#xCi=E~8
z6?;7K(W2B+d8W@|OqrG)8(otJv5ZKG4!`bOR@kencSXxPM*8D;NTwERPnIpNI0~W-
z4>9+2lDd9j5AkYt(q_Z+^^F(CRVGt4V@V%Rg_SnbbZ?aUhoV$pXGo|=k%xdGS6!5-
z*-nX2P$t=C0;QHFNvaaH%}naryBb4oYsG~3K&|3AEgh;`%$g)fYn85-Bn_o%D_fXw
z%2ECSmD!JCMQ%I%>-WTImBu1$)gDxf5i3r#D{2cq&Gb+tmMl1=T7E?CfsI_!I;2Zk
z8>TQWlhm};GmtTO*t8P0c6{7jv%K5*p!qv}K)Xq|t;{{jOt!n_q&7|NmfgZ!JK*^y
zaDq6fVT(d|Cwca5FYB3=N3Y0)D6B(~v{@CCljr<*?%1&S$#|+lM+I?L)hf2CP3T0`
zbfzncmZ+SJ4_XD+B!Q)Zj42rJ(rdn0d@@b3gD^Emivttkn}$_qWOU>`k+YJqS=Ao>
z#)zY@>yGG642WMc_P|CR464-HzdhX*ren@+=|;2OxzVT{LEWi^j;rqQT2A{fnq4!f
z#=55d{-_&Vz9k*&*3=u!*fZgQH8aKpJA!=&P5e~z9^<BWcxKAG%XE`VCRXpj{<xyj
z9uM7?X{|}03=af|sMa$Ef#Kfptpdow^2~(HRP2o0$Q;5V$xPHuDFZmmoLVM;wr(_j
zq23L~Jg4>^<+Qp%150^Kb%UBqvhmk=R{7m9eeLeu$!*?4gmmj3Q(o<Lj61f~B;|_T
z>XtmyRaUJ4)x`32X5RI;%nq9MA>1g^Rge%Of)|hJtN`d?02*V+rcRDSCuk&HbEE0h
zkgo&yHkx*)bO*g&J88ggyM}NBPN&qEFrYxoB{%L~<NB?FKM5&1Vj8xbkA6lZ4ZRlQ
zi<t@rJ+lm~q8@WFcQzV}5t19@Q!7{uPrSic?G5x~yXgcBN>B^mXS%gbn&8?M?=y}^
z?cSxHmEJ+d!^R|D`6<&iF?0yLWKvnm?^)ZIIN$#1#WW_gk1#tke}H%<GK|1!R)EaT
zVWy6(g@CCe{W}I^Ox<azhdr^+-GusU6DAH-*Qhix-jmP<OO-}Jy%Q+#5}P-%zWv2T
z^i@0qS<}6nSnxiWU`@&;gE>54)#x{Wem4-NFb4`Od)g$bVOwLysWqJ2ysk-BDZ}7%
zamOAa(?uPl)~>K+%5)%^h*9TVPR@c1H4VnaG;0{DXD$V#aMt($R3AI`7f2s=CZSXN
z3$sB6`VO_-BsZGv=D=h?K7wOLJ#KC?)=sn0_!GOy-uOE`VJPq(<E;IPc{8{j_PjgI
zWVxZ8vLqc~X%nKf5Z-3yH?9*RhaQLwjuyDCL}Xa&mt{ECon4-+5QB<Uf~gC~+?Y+=
zxRCak^E=A3WR_e4f)Hp72{7g`E2dLxySCs7Fw(zk{O_nCYwh77Ri9WrHV*pNxVyHL
zD_RAG^(^;R8+?4{bsLwY=zOtlVW>iom6-rrZ<rgzi`AQ3(N>)XETv?{4Vtz&mf%jM
zWDHW4;Dj>B6LblCWg6Hjm`dU2tg1&pvrG(WKef4viOp>#gF?sa<30I_!di0bUZg|h
zwm8AW$_AL0u1Lde*x#+7a9>hn@w3-E9i(SqEKh#L1|O1Wb9p4<m6kL4nHl2I;ZJ|!
z#cpoD`IoMoHT++j8UAk;-+`FQ1Tw?_ryd-}@ZUS@J@`QGJ@~-Myay*SxBuYFLh4zN
zv7ZYAk(d2Ay#O+qr8c`{Yi@7l&92SOnyBSYT#CGDPl8@F?vVs59osOgAAbE)bL)R$
z;bXgph*huxdo;s*g%O1SPPghXBCI58IP(vELHIp`z@Jnk6dHwqXD`+X(*Z!owXD+T
z{+`XmIS|vv@o*xwW>YDAJR~vf{JNjYH$12)g`SRwhMOTtZj=_mo1*eIyi7H)Wcvzq
zyFH7R*hD1(DVur*u<a>4T4e3Pqx&vEkXTwwoygkdp^N)PE7leIMAxKeUS@|u1kJP+
zrOOR8bC%hZroP>_Hzm7NP@Z&^ZWkEIWRbCU8BfQB%(U`tw^PC1?lm{_w;Z>nfefh9
z^8AC5wQA6Ho3>x{haD@nW#Bgr`!=Hz;{WoO1~@^KcrDOw@o~^O@W8P4%M3~#8@Rxb
zL9CvoDP)`3{Ywb!$V#aV01>}xyVsdYWi?H?zD+H?kB1{P2-e3vzZxVDvs$Vk2o`l!
zQt#5<2UVe6Xk#EuR@&~gni^6XgUxjHlL>4Rq?;1RA8Ta~AzGx1sC?GU?|lM_=D<J1
z(_tgiiy^K{{|1!ZgyFp*FEs;Ojb0u_PRFHdQ>rmMWZH#>=V;wHDC49JRPg9A;&Q;@
zH?TAs8MdfjFc2!pnlZsla5!%;%mc2k8A%&qo4TN>6W3#DM%T0gD4e=%7EBqv%FEm#
zB6TIvP+F))XM9^~j|;u}zWvAc(V8u5gjHb2uosa=uX;J4DIrsj95yhpcT$N?-PE-P
zSo5XQT^`F4tVh2xLmgtxf>QVX(FMo+S5i=>T@OGphS7@*b=`p(Ddq|t2qF0eWD@w<
zP<s+KL}g4XY;oTP@o{4z%Ag3UX}Db37)_zI3OfbBv(<LSv5onq17fb4#EI`o+UOE1
zC($3`h`l6hhnucqMWcjKD)yY%Gizj3j4PPJERyI@qVikT)$et}B&SwHM+85{F~bS|
z6UpYzc3!MZkFF@SDM8OtLoFnZ?@U_tA=%Pe%KS~1SPiqqJZWr}ur=rg4jHnR>h|S-
z2mZwnuzU=kIHi-}Xr-E_`-lB1A|vZyh3p>Y`ha3^l8%Ze-BzL1z_v&mEWTz+S#Am$
z2GE1it%G(rWI!9WFjaa7L@T31_k;#o-OS+|a)(DG!Xq6}v??NdqkIY!^6Y8T;cTFU
zr~K<>ZrYw})s421G|EdhnIKK+vQS@`Eul-sS9T0r%PitIc5Xi)-WxiU(GoRbglavI
ztW=BA4n+a#ps8WPL2N6K)&5o!ByrM87?hgY(?!K2lkaSE(i9%Fhj=JRDXHSoUt1RS
z!d6B-3H!x5)q!%%^ciqmlV$J=L$DR{*U~r+Ac$ox-<s$FT0v+8e&8xstx;fQbeAi_
zssKItg(RN~Uzt^cR1#o4^n5$E-5v|Nf}hCT41Ajbp-|0;wyYWssw)Y*n7#=EX<Ej^
zq=65RWXuF0raQFwvw!0wGnt#1;4xzYo5?-aDg9XPq%x<#2Tz~o3Swzl@N3IOZkBtW
z=NSb92B9!564j_g(yVqt`HG_eAey!4ANkm4X{hJ;@{8Ip3LD5{T&)y+n{L(}$j6Q_
z#i?JKL-UF;j~QtjvdXN;>aqqr<3*8T40q9OiIffj#=7@k79|;PSF12JoQ_|isI?BS
z>kh*8k-K5T=)_>uNGs`PhC<sW8BY*4#^_x}D)S4quJ*j($wa-p-Pog=)8nRnPua8{
zFn^a!8`E9$nXSn-Pwi3L6w+7K4kX>?zU+7HIJ?@aHK|N<vuUnavTw4S;5SZKjFj&&
zsjMWq>wBV;OTQtykR6{^;}Bcdl|l2d!HvyI3cmD5SMJdX5+-SBh?wXE##MWEOtf};
zdwiT4zW0o=E!{9bWtxwuX2}E-UUQN)HF=okAAq5kPIXly3HBg?lrfDJs~_6qy2*Gq
znKS|Ps@s?{iP_m*CL7xM?*NVlM1HfHR&;fL$&JDtrLwLT;T)?xQ8J0Il|juHZvxX?
znFogOGSq@ZnP87eYFiRBIi;{<gDtwLRIr;+=$Xl&J!C{<R+o))xk@#alQz}TO9@DI
zDAsh4blegAmj3TAT5l4g7Ka4JbZN^aX<@Wjz0O%VX!eiXw|8RXO^4j(#7N|NWP6L*
zQL=Q?cANL>ZfkJIYOKi8&WY92>|{g3+uCep?`(d^)F!Xl_eC?K)Q*cgmF>xRCun|3
zcg-c3Q>|{x+g|yyp+s3btJ>*R`)g~=ou;-&wYE|)xYM-Mr_|GCWjA<Co9KSeZkf%M
zhsobDMt0koqEm>CmU`-IuMi(Vwy!)|6ze?O&PG<04@c2xb$Fv09dx4bNo}+A;rB4f
zllpP^s#G3^D0jewV@~Jd^geH5ciXW3EgEliuUSL;H<_K#uyT;#WXZ?s1Fx1Nm#zr{
zF(-Eft(9VzcTA^Lt|*1M4ofpsK6BH${mz$V==3}#&~*&SB$o0{eUlk2rgy*uosk}1
zo3wZ%F7+@^8TM@;wmnD8hYdQVZPXlhOKa%yO(3LJOdw_^OEjnkx&c#p5^k6bI`CS{
zVL=yvMP{TTp|JazXlxa~?yoQGtcO<Oy?{Vt4xzd!&am<gIFaZ2y`g0<D6w`(t2^~>
zV+OF%F<fWH$2Bc5UOO9~8rRNP*O<7`HJ)@QuGmSZWDazLG@cBSPEZ4%Ai%MNgCP;#
z<$MGpUW{f)<HOLA{p@=gy8NgC^g$F_VpZM&E6#AR#h)0laEjC&taG~0$d&CoVc6~T
z4TQ?qJKnyo&<4hT4>^Kn0mb$XuvmjP%%3m`&arH`YRCmu*kKGF0WboK6uW++gc!pF
zwF1N@b^2X1bM-fcHVj!c<0Y_S#fp*qECiqh=cBA@h8J8Kh)x;s&c&MXZ!#QBV+u)U
zb!xdc;xItvC^JkB1N5XU&@D%19Nv(i$ui%Xyr^vZi;%p^$_S#IAN-;ShESwp6%-)H
zC~mH??g(rfft3tYItCL%`}z^wL}eQ`spCM(co;tZP-5+D;?NNv(%K2PCqvdYo-z&t
zCkvtQg%Sp~OrR5Jp%OWJkQ6#K1!lE^Y^bnz02ANv>q})ca3}c1CkNBa3z)7f>NNDm
zo|s<dYH(^-iepb0dzS}R&6{u*K>mbe^H5SGXpzyG@y5p-*!)JrWV_M0N%<WbH-?q0
zT|{-v!kRnXR`)@nP2vnnt)^}52-=Z$r$rQ4mp_abFi_%r;P`=1(7E>$uSjFWIU9<Z
zr(<9|#O)v_16<2XB_3w3*xPggD@k_iB?;zgvUYaXSZd4}RNFao6gn%btYqsQWf}<0
z6vfe?Cpfi2T?e$bD`a7(sPDjpoW~elw#^hRKV|ux8XhggRXHue<N7OzVuvuwcts9B
zfF_;|^qTcT%8o`Vu&bn;%M2$LQXkjw<&mFB>n9?l4*jxHolN2SP-#=Lz#?SvC`|ja
z{f-V_v-&*neBh(_k)2lf!0juua}(b?>A8uMcs~AR9a5$Tj9E4w*e4ZqIl{eLFEw!E
zV6x(s6MJB*9&&MYcy3KDqPmI#8lXiM_$44EJFb#Y59){i>RYqH<8LvOHV07(k3xM;
z!qLb)aNFw_n_f5)OC+`0wzo;U5wgefxOkSonyHT!kmag7f!i+VO^N(0SHWuIU4~K0
zk({f<L!e_@oFHu&S$EYcB@$Exh?%&cI%vJl9?N&{|CL#U1Y=!yHc={#q6SYwDvzBO
zd=3;{&eie{D)2%n6eF=@D%6}<4PBsSP!bh82?X<AC%BqH6pWd#eD@eVd}%Mlk-&*T
zTS`fV?CH20W(x&wAWo30Jo?t)=$u32Q=T=fQ{`dwAgI$id)^HuEZtGaZvI+GD`i{3
z%pd-LAl)1+itwh^%&5a7Qm#s8+-y+M=&|d>1j>dOO5oE}bWRp*(g+n$tkC@G4oeCt
zw2+8}E+PJY<$mzS*q7%4Y}*m650z5sfK!i_p}e6LDQ_1n6k`a}lxX+plzZSJ@^oC}
zw}&~3RDzc*OPH(duz=uqDEM3SDxATzFkoW}Ix~OuDoe+!qk|Y$S(j369fAY!r;1dv
zys;`WhyA`4mEE|4G`h7IaUn@<RT%e!BuKEYbftpbV5GAcvA#*BVFfFN75qh*#KD>&
zJWkS~K?rKyw(k`YgYG%(lh@z3u}IG4stU<;x~jw?$OvN;X?U`c9*k1=;}K^b+~tbh
zvI{mSw?2)5rv|(s<+_`6%6JtTcCgJ1vqxC)=w>-sY6ZJImc6I+Qv490<|ldyN2?_K
zy33Y=NNP#r2HP@C;Wbg)#M=nfJuxE@w<+gD>Z)Rc4ZaGR^zAsP*z#|`a7MJL)RM*k
zI-UJV4!mU;HXK6x(ktm>2E#0Gmbgiv0CsCp8etw-R<qh0<+|8#xbPWnu*lk@put$O
z6bli8+lwbw(gr97tQ{0ZQySSUwQK&4&WI_f*Mm&E!pof)RIg6ePn`sgV@!NU%S??6
zUK^ho&#Yc}(H2n=^-4?zGmqR%-E5&+&7!`}=~;MO<8*PjA+*}nv`C52<s}br5nRVH
zeT@8$aW*1|Te9`vf#fJff}roLQIkS~M7*hfaG;X7Vv=LL@|(CFZOy##87tAOP|RRZ
zOodJ$h&Vkcyc4dXh3lMAUDZQTVqFI@7$p;;#snDURs#3o1Y~(va5~*ez$@rZW>ZY2
zmT_?+Qpo0?%ietdg%)CnE#XLqIxa?Oq$7H?D{3qjEj0?G=I#joyEZEC^``ao+s!h+
zy^PUlSMARAk?Mr8F&ALi;+?@tK}ZBNj|Tu+VDZ<OeKA|~Y#ZY>VjvCfs)vHI>T0@c
z&HOgVL6ubcnQdm(4V(AEcs2~;%20EU@r8g)tkfDaT3MuPw#DL2_pHFO;uV_gO9Qe(
zG2Rf8>5b2%wZcj8S!8Yt%i8$|qK5<UUk`+q2t_Io|7Uh;gH}DOwb*y!CFMelV6YlC
zt{nQJdS#3?8RLa=8qUX^1h<j=K}i_`d*=3E>t*WkVcoIHMNf|+Cww~;x2yO^O)tv;
zE-V#9E^N(Es3e)h3>Kg+KXKJFW-?(j-%VJH&}F6iY}!CAnGMgn7f3z6Od%>|pa@5@
zgvfLzr)%wj6H(Yif(q+MFOj#TDO@;phq)cwu_2zgfN1&4>NcP-v-v+jONPA&yJ5}K
zPz0mtkVj6V+q%iIjK<;}8_l%m#zh(rt&Ncz>&2ae(;f_AP*Cl7$+$Zni+_XZ6eo0E
z8ZnxutUuBqP(S=p&9D_$MVr!1sFR`GQux17EvBA7;&lgOK9bzfAj9&Qj4ILeqJ%k_
zY>51=spVhnq;4zomHQlHaSU!dNU3S80fxvknSk_;`Dh36%UhbGDD?8L{*yHoH8=?I
z&h)yiY2%$~^V+C!Z4_QN6oriuhhq}e>Ryk@zhih~7;b2eePCla;CV`4>+QH+?`i3K
zHYTa@pGj^0^jPr`z5PG7T6!`XFF&GM532`)))u@FWz*cT<BMJ3PA}<t?WFJ!-ncH#
zP2<$NNgHxSMt9LhS#|@pqPxd<3F?tH_vqGy9(TR6aR$G>eGy%X5SG_6TjghpsjBO0
zFM-j6(Z=TLjm_QO#;CD-quwzXwf9Et4@8aXH}yx%M$GbV)Eb-id?s=fAKJJ{Kl9P8
zL9N*xZcnZ(FEv417rJSZChZj}n8r+5)C|m|dl`IM-qOPBQ>*;<WQo^Jx}5G%`1<P{
z>Ijmg#e(MstqBoaiR(9=nGd`scEVJ%SRVH$ZkOV6b}P%9brY(xez#Y9(FSsj64Q;|
zUeVnsbTMe+s;ur_xf|UwxrS>fXFV(uTr-IVnfX(Ejfsijn{dzpJ5Nq7xM=Uzq$l1N
zsl`R+h#py1j#qZ#2|aN5v%ieRtNrS$o-h+5qxhpZ=Aomgcg|yHTAWF}aQzhry`5=V
z)tl2zdZ(TksZV?1hW5L4_s^H>MUO1Iw7fIzn#*rWx2L1aZfL$cdS+x<>xh}IeP(FI
zH`8_%<8N(v#Ed6ydY5r7nJ95O;r-Lj%0nLh4fSr0l3caFJZZL@+5<zA1}DtqHMn1#
zbf@7^#%BEiHC@7VT^@YWtlVGXEXEtXC&O-K-vo|<52f+M#s1;n-!EsyMyqczDb5$2
z;zx*!dd!jSc!()MCU^tKPZ$m0QNmTVjB`Txx?1>QbToY*dyB;}rS=EqZ>CrLv*$IP
zwQhGjzTd-sR+OV2mdB)J@C4N+-JQC^8HIh{G+nm$AMlpo@IWucGa_CTYGz{D!4S@w
z^2CR%&Ti|f_an1Yi<2FK9ysDYz>uyV;hn8Iah}kwh_@!CX1Xz^_P@T(5tTOWj6^$1
zNm4F#M;^ia55=?|-GABIyDxsk{IgOGN5Kgi=LZLBM4aj*@phCt!O+eon64=|ISBL6
zcvFz))Jc4k5ob|LbxX18UW0>R#XSZQ{N%+;W`64_BuP<+uxZFq6^?Yo>7Y<>XS#m`
zy#{KI7F}}e)KE*0rh}d`DFoU-a;ZnhyQLI1!HFdP6MR=!6wCKS5j%9@MyMiLIwf}}
zf{>BT98568n6rj~_ba$ju1S;n6XF+JPIiT30dFvMT4wE{IGNOV36@y<uD3sT@B$=n
z1h1NqLoPDtI4I<}i#W7k&@?TA2QJKbB!YOnT##<-rdIOEvXpJ2&X=Clm9*IEwri86
z@;#tbUZO5@j7lXqVLEJd6fVU<sIYZ#BH^t-7s1yR;^0xsS>k4lX)P7M3SPNZx9i)!
z#^Iq^(yTB4rR9$}(ddX!EsZ#bB&URKLvv#)c{o#WdTDX#zyX}i+88^dgN9v~BF?{&
zNGjeRtiAg~Nd$!*+#^<_ke&WWx&zFV2Ru8eW&9WHY%Zw<(md=pxx3|%?>-cQn-Hym
zpoWIiDfyG`z6z_k&+9&~`^P0I92haMVN~yqgkzB-{vE&g80=@keN{VT1;j1L;N59V
z=y%(p#vLgBpY~&NMCFe0?P-M5>XG!TCREPO<SPbIbBB^~-KpQrQLfqsGS^i0a3J%`
z`OF>CWwzoxx)dL5b_8baKY2rAhWWxtm}IhKYTavMgNGA;)y3k@WDWe&w}PBTD-2U{
zb+Cx9L|us=pLSfFc5Yi&t0gD&kf^K7ox^X(S(4(fpnDu%d1gcv?=VrPbm@3<n;JLf
zF*fWVRbku2>YcopoNO@n1^YSJVo$EwsSl<xSX#BGbj2Ba$g|1VAa`TY;Lw;e37gy(
ze0+5WiJBZt#q*7+3VvTd^0Jhh$B@=_0fl2_k)^0{Fbzd{gYCk2vyR`X^`LU&Wr948
z9N&&Od!>qN*qUY$uIm+r*v5qu<75%nPZDDInIyL501aBBy%M$wro;h5qZ~r}!v{AR
zVKF*xWps(FMZK~J3r!u0E4ztbE=2JUftL+kMi+_VeK`~6VQW1TQmLXzLLat}Rb}hZ
zLoPHxD}Lr6v{+a;|DsqtV%%ul-1Rt|Dbto6n|uHMMesj@zqc)X_27@>zZE~{dk`P1
z-mw2dR)AEvgo|(qY>d*}12j>7o9vEzTM?wapT@)3`@7U--qxhKC25A^Y@7^9T6>L>
zqXnev_5<oE&ExEC(k-*ubCtKFlIpD7I~qEbY84(MObUOp5@apT{JXugO`r1S!*JOd
zkyGY4n((@DQD3E37$-2b##s0K#eNaHA}yl`Ghwy0+-&CHf@7FhzOLHV+U}^oQz7>2
zC@dU&Mmy!O0#=DFt`1mz5<X{c;UOqUQ-Nz@oJAFazCEz|!=fE$gj^?0TH3caqJ7I@
ziK4}UiIl|Vu;Z5s2n`GCesN?411e!RnZ3|OV$op7vym=abF>uWaF(i}6lp4^`^cPC
zY?ceiz%e-;))~NM*9o8d2nVV4W|@Q>5ZNzhUt;>iLW-D<(VpcZTi1a_ZAdb4_QcfR
z>yK=e5=)b|_2?xp?+p6(2-BX<$i!xGb;Yehjt#;bu`cpwOIPgJqwYYhiS?w{EHp75
zz4}&zYFVTEuCJJxD9r)=m=v)I)Xkz@M$i{a1~<fA`)nB~00C7mrkv@nJ0xQUrqNhY
zycQS{DQF9{ZQo9}#CSjO4uLUhBC*QHO2E>{vS3##0zy@r0Y>)Cd^WXyo)E^6G%_#<
zb7N~YhRr+0LfVw3;T?k@Rw;6hr{rLz(poBqdKz0ATfCaynqb&Y;xTACxQxW<k?^Q$
zNW&n(Diguu7a$_!6i1|o0cWUW=GT{75x$wQS;QSN>}fet##ZqmPr4PBi;zo>n5?S$
zyFJe@CWyY212g6j<Ks0d`!%B(MEE7*%4Y2<oSw0EaDfPKVjESYLE2%?ia*46@ModH
zSjO{LF1g_s#aR^><y;g-5H#%(k(OP4>cz}WCVTgo1`NE<NXi%qr6oy-NISTPX#>b?
zdr~QY@>6zp{^H`e3fp3HhI)jJC|rJ+ug&UWd@ax)7lB^@W87<5rL^k@`>ELnYu|2Y
zUFfCZZ;&==PnvWYQ2N4fQA~K`-v7{RA92O=>jitC>{3J^B*=udHbMftz`m_$NQ&+<
zWQhwMj`MIBL2}114>yRFxaFh}8%9f6>ede~!x+~jWZt4pf_QP%4q4oNxyGr6Qy3NO
z&1x}(T!%19_D<u_NsDgSeCHTS8MWi@u@yEJK}Tj*(BW+ZPF!(Drn{zQCXzTadc@#`
zWyp2pcOH$45%t6W1CcPja4Tkhh9&-*I)@4p?L#=*8pkzSP)yu}BYHR*@Uh_3V~DUu
zvw5t9u=cpTy&?oiz(WQK|1YopKK@G9{T@W(qU9+PVI*&B*PZbxQ+L`(zpWZ~j%QLt
zB!lPfQrogp(w7Q242h8FVHaz<oSg+?j7Vaje)<PcFr-$<7_GwXfD<BKyfI2U!%=;D
zW4u>Ri$p8~#m@CI4W#27h$wDsOrrrr;}JCrd&m()1y58QG(}_&kDND3RLf47AUHNn
z7U4H5j(_BJ^8aG+LZrp4OT8{4_MMQLZ0li&Cq5d%I<`Z!X2`_x!Ypw%Gq+4QKudoS
z?>8}+P>|XCC;y4w7GXO&)F=wsEPpW!7xE0<DC7@9pIzQA<L(&b^evIKiAr#v!Y_-A
z#i8w2D%$p&wwJ^ZG;0tZg$1%U1Pv-+0Il0MFH1vQI5H*zb(M-^d4P)G!zhG5>7WcN
zH*t|!)*8s91Zj!y=$K<+Qfti?jwb=2A4-OpHhgVcf4qUXQ2InA8N^lEONn7TA``cZ
z?NlvB@wffgijT2|5*w!hG?Cs~ye-9%9nL4i*uC=1EC)I#u)D92^{jAC?9>mxtp*!F
zFP1@w<x49>@JEAwQBUDA_m{L7Ky%Re5VnqK`0yxZg$R3=h2F4(zF$bFQM$`GdYt|u
zLIzg&JGOlk{hMEocXgW2D=-`BNIN|g!DdmpdT?WBaN|b*5F8kW{H50!{S9;QiKKny
z^mM{aO`G;Rb@Pz7(Y-TjP7F6E4!*B;#lem3-4C^g9UMA#t*LF(@w{>V5|ywUhBnX*
zaP_eI1WfRb3tv`N9B>b4PPdqsi;h4(9QsO6Xj~cF4*%~%R&&I`EnB=!alED;sdU6)
zq&KmdHWk&?X4Z@7O<w3l_eFZIm%Pce_L^jex6PoDOpmuJ6NBZS@tV4FaJ>9<s()g)
z*KX?H^=ept6A9}_Syd)*rnR(g>Xk{?_54W|)(X2i0m3j|Gz2GF$pIU_*b{J^wPv7t
zmj$q8&-~RNvZbEJ)e+BRe|RRUVjjlT)Q<4}_kK5|*fD7n$BtY^E4$IoFZDQ;vzblq
zQFN*1{>yf(aih_vlhs}vI!MBxr$=&SBe8~d?(<5C45FEgp^=<z5A^JdLG1gYFks&*
z@9=xqTJ3bu>Aapz^2+{^v5n0w*X`!@pKxpoF9={thvn7nsY5QI(Q7^YXm~^PXmw=T
z8{J=8engvF-dSosjh#MN?YVvK@WR#=_wPLzjmV1%cbHo)yL<PY(_!ON-aTebJYl@@
zZeHan=>|TBOWlW)%WuL#a^GJ2s%q!rgcpd)!)Edtt2`Na*4p3IQygRg>!&J}Pa3`x
zWz5?9$+~}SgBN7(8E<pKz_@q)`BK(Fc?}38Bi^H6N^>e`%;C)noGapnz@<{=kjq}L
zTq!<@%PMmh@QC|i|KLtNVZyf;cNz+CnBWfaZhf+}vpHmLNmkr55^xHJjXlI#Jb~vW
zt{`?2s2A5JFHQont4r3J*j~GcV|RWx;lGBpx~t_?meplEF4y2^kwXrh4_P;Z?ntEh
z14k@x!4@X~4;IHuqViLm11buhv=fdNFZE(LBOE;>&XiArr9Ijmypcl|kDG~UPT@2;
zptYm9)1><=`}F?H8uyReYOE`TLC(XeTG4n<JcBvj2~>HdDwJ(RNnmxZVS5Wq*K{Cf
zr9!5%-MOas4Uc{In3>IwBmbah2xfRD1X&ATl;Fu>rV>sk|0WZL>`lN5VW`K<{<k);
z_tUq(#dHpBxRKtDJv7~&hLZmN5`5LYY^dD*67Pi35%nFVIz~JwoFl?dVsJ%*A*Xc8
zD>?E|wt3Nq2av>bR<>Ko-6azT8fFnBIVpng&ngewJOBOy@sIg<D{x%Iyb3frf<Dw4
zkz+JPlIX*Lst$S?-|jG@pBzaUm|>`=92|Y^{dma2_}v~pw_7;+(jB?wX}x<KG0Qm>
zR&fT?i)+-i)U`S#gTl+CRtR`b7+I~>qT~SQC%Tj9I~h)*qdGUd8Of-n?Q9c;1rc8l
z_=p3n{O-u<lpyDmS_|IQL!ODCW->iGQIhjSozj=5VTvfk@3TGi182+F`^KG402$l_
zB~aBk(nKRdqF|pr%Xrync8$xcRBDlF9k|Hv;e?|XeZ{%!8x9Vf5gwQm+1p_^8n}CZ
zDRbiCx8zKk|CF}zFp1AYyPa2Yr0DJYOLrRoW2Nneck)K}PxG45hy|;qX8-Da-7iHy
z=j|A883vNB*X~}!m3e)jTZy{|%6M-MEG=_du&HD;<-iPXM{Dif*Wk3AxTsSrGoZ{3
zFR3jBtLy|;GV>?@2Wz~R^+miVELrky(ilhC@Awk@j3W>67jaOnQfyc3Cp9N&?k-sn
z&fv<xQ#zGqR5M|4r-{_eIPXs-cQ@n7N-NTfTHRW0QR|_}{qQ>|9pu%WeM=OT)Yy(L
zxSb$=#_O&QI<>X-eaZfd;%>kp8P>j32zYy`kb+m5+NhyAgphb{;^FBOYLZ~F<yK5V
zIYs+jSwv-siUUzMRFW19p;fSM^*;Ae-yiTO!@^qHdmZWm-UysZMV<H{ON28s{kXj7
znNi``aUL|_$D%8Wq6y=#6B{&4#gl`WsTS``Qd<)6<)Af$W`C7~7snc4%-!`Y@!1+r
zG#(xwhZSy|Dw=WLO*VS&I<Q3kQRVedC-3&Y`k4o>-;(g*kT-t#+Mj$PI<jr_!#&r@
zEjxN&45`We{eSXjlkTy9?Kt${aQ2OjA*tgqUkZ6hDv>vc-uUX{YuR!Oi`dxBYI6Ap
zvr6{#Dk)#umhbi-DD$BX?*F|dl@Pe4)%*U)gP##p!dLJ83?D7ozU7v8HM2@S_}of9
zJ$yjE_CeVmCIotzteeH;<gTFqnsw*X+`vSAtoI(&hPU_XP#>%Q_S5KansLp3#TR42
z1imd+NX16AkO)rg@N$S)hv?{fB@O}>jfn#lRFl?fugyB{Yt^jimGWogj&9AI?gqRQ
zBPS&IX{>0h&}bOEBU4T)njdMvMY)xq*xqq5ymtbO9QQ1`rauhd%>gqfJU2K~`Dmuy
zNoTC#w1Iw&>dEfKYO#+!7}nQd(BRyubasgwdQ)CU5A9HRCj3Biw7gZ(3C8mZ6I8TL
zbfH{8IYr^-h<j4NkA+<$CM}Ps)<J>_NmHdqe@@Jf3<d@bA}Y2w>h(5Sb10EMrU~{&
zJ)q4H&xCKbw9!p@6I3UDQwJ#5s9b)fLgmzsZz%4yMgV$AbEw9ZfUQnzkfT2z`G;fO
z%myyyxQ3jhpo_SbeTGmbrxi~OV*F6;6vK#%h$y$+Kp&?{`lJN6W00A;JTiI5e+&8@
z!p|Raq)6Pce6PgwA)RmoCJ3*r(U8^~G0?HJ8n(gS^!$km9x|zLoKYKxZ9GQG4-DsF
z?pAcHOGmITY+vLE1ONfQFl_z9@~l*bvc$7%U~d|u7h=8jtd-bCSg@Um`X73Mi<vL}
zE_kRlY=ocqEEu?D#yyqF!6Lt6Yz+69fx+oB)eZ1-9r^hKR6}<*rMxC92XpZ_u-YMq
zH|e-CjP6<DRlGVc@1bnV5t`=W`#h${;?4%Fj;%fzp?x?F`1l^-UtXrR%Z{9&!l^Qe
zYoX9e^dvoG!^{qX%o_C<={P~A-u7w!M|8R>LYQ*WNM2pla@@;it})0q{-V{KA0AL8
zRVm`qtBmjEJV0YN{<-lXFXk+%X4E=z+NxpK9Oj<3V;BdkI^e?TQ@32evcj|;hgz1q
zBcr}$-SFGA`+9ncrOTK}>wadB5gG~OA|nz(BW+evO3b}714als%IN{&b^r$CQ4oc<
zJJf;?3Sr+N*UZ;`M{*G7OR~JcNEptL6@m~kzRenh6<NZIB$cm$^f4V^Oz`tD(BgVw
ztfkGMM#r)?X@qCOkG?~m!4m(CR0xQt126w@(TxV2O}$7pjQ<C(0#(7KffbOC^}z7#
zYcXoqkR*{(DN|Xvq}VW!71R#D>)QiwNryucGlNoY+LH586c-`12~(4T*w5sNc~J@m
z12_2EF#&D(+QFLT{e)Omma@Gci=&_;a}JjxP9c_IpRI{Kw_kZ-nh*;e<qC>|K8=7h
z1Y_1vp;T&dd<kVeASl1a-h<H#Aq5RQ8nlU9Bl8$h2w98H14Cwib^DG7tai1S(S^q3
zjw{Hv@W==cBtC9IaUVO0R2AW~1;K=>_xN<CLbMy;E}#Pyt|sfZ)Ip3yqc)Nw@t3e|
z^VAnMr7|`$TB*<{15FuV3e+*YX@ng9Ye}5MON}d_BKbh*C=glUIIpSIY!jnS`4c)x
zT$8f2w~zeMw?weXs0%JBe^l$+h(r2@7ukuyI4)+D`ObTwGjq?zG9U)Rah05kKNx_Z
z!~-0_lH2EGhRlJi9~7!P<Y(9->Gw8T5XDn^E<WO<Y%sBHwEuC#xT9VfMqVY|1ecn$
zhUz69<QQOqC*S#c^THGYW!2ITI7=oyDVv*a$_&xunc~eIM0Eyqk9%y3n_GAqOaS_o
z^$K!PR?Zp9>=!Px9{buN@DoTV3G!*e);OM7VI|u)Lxy1+h<LYd8Lu-{mDWXww%E#i
zV=QG86(%DyL8N>Dft6GR2nkf8;uS$)7V(-F)Ftk|e|KTXY@sK(BIs9dC1j;w#<2gv
z{6}tzzlaJ%W|WJ)4hX9Fr5!_`v~a6Xhdc!|2V(i0i^JI|8o*)a4m|V4mt8+NJ|eYf
zwpDO*${ssmJRvx{4f6p>nx<)EtMPa*r;XXfd7!ki7++Yd?%@M4BJ0Y9wNBZfe(2`P
z3Dg@|y-gro;mi6S#6}!1IA<E;yl&(z&(7yugr0+9qxkO1?|A;!5$TR#AwIOk&}y<=
zj$W{aV_C@Vl=8NkUE}^V#*}tplhkFg$KtxuxBY;Au1VG^Z6>_6Nbjx|uS>wFcBzaL
za)oU2RnVPlmj{=3an%N`%}F`9yV829r0j<6uZ)g-<I7X&_4ryGMwk71Ig5*Zkm>|`
zn_cYXLs(wrB~u)dkn{NBTj4N56MGZ(bmdN$laPn(7oAN^Q9LOepOGUpNx*WhjHuJS
zU#N$#1?`;e3vs%XI3$Eys>$5sg(>f;_b%Cl#UhKwDz8-IXuee)mCfQ#>5UhUO{W~j
zz&zbIEOsMnP6u=QA{FYV#k?M#Oyv!wcTacQ-Wx9t-;{dekEp#vt#2B|8=5QCiplY$
zR{50fwl0~d#I1wwBhKYFVa&eq;;9rL1TP3(<hIr1MV!%1maMI~6UiV4ZMx;*$#(6J
zg3C14+ym)N9KTt6H`CF*(?DkThSx5wJ7Y4Du*R7i^0^ADE<_l{pvBctUV<N>%<B|F
zNE<SQZ-)X-hNkOR(+Th4u%_R|yDk$9P-41>Ns=ojsZ0n7lLR{vyE-V}J)Q)?I6GJ^
zI&_g$*4iw^{c}KGl2NtbCdPabbB-ecSm85Y--oq-Bhwbd68ZXxyoIBg#GsQM8lYCT
z>7gSp=yXS7lNPb$@t0g-N0Ga)I~}gslc+LBN%&Y)%fK{UL*`D`<HIj}^F^HO96_BN
z=eUUnvnOO;gf))ehZ71az~l{*o8)*Bvxlx&`<l+JkMQz}xSm7`C4yYftJER_2hJQ~
z;U6mDi{ONXX|;<9wA*PuIqj8oT4fGZ_gBhY19DA#ci=UIwvF8nzj0EJ*+%t&q{(p|
zGN|rqWyxo14wT|<SH)f4x*t=MtFr?we9OivZ}y)2%L_+_Lomz664dw|iwsyW3&zC%
zu#YhWNl-S<ZFnRQ;pN30Jl#>*j;kDMsW#Yt<IT51+^q!iE)Pd{<sCCZCdLZ}wUy!(
zDCJKWaq<MbA?9`xUgYWG7r+iz-WWTr!Y9;TZaQ~;Yw0j<rVJ+rG5cH!DPw$w1vKF(
zq)iXg+wj`NY8gVW4aSvX$9u$4<GjIy@Z(cD?5BdmfyDNix4dM<q=l7mcXRNLH)tFs
zyvw&sVAud|YY8(kU+J?Dr|EqAjTdkn3kMgtNLHZ@Pr~NB@g-|AwBoH+B`;--7CX~#
zU(7o2$uD(E;=|#s-0})746He5#Tl{{oD{;*sqxvsN;u?T1cd$CiHmtDZZ(HrYP^MM
z)=peQDt?IWHN3@!N3O=6=jwfM37mvubLMBiVfn&LkI8b(hm^nw_XDDIJzqK%d6q48
zW^i=5>8=ms@rUI#u_s5aNGEoW7CFDNB#=)U$q_)PzD-Z!2h3hSvVti-{HvVu-|0%`
zr3q?yW0_o>P3hD+B|I5ct1y+u6T2C!OUIcu)@v?WEV3MZ$(Aoa@g)LeR?3Hg4vNl)
zEVb*;poFp^I1uRz(y+Xkb1b7~f2n-%5Ig2!Sblh%59w$-s8!gram`@4;3pM(<rS3*
z+vM~pP7bnZqbn?xo;RhD=D5~(J<Wb$@YuBB)tF4Vm}z`|)=9$m4iTQ&r(ERgF{_N#
zh9Xm(WMNxP-dKWTIIqH@vR;n2#KSCe)Q|PK4fByiUc^FuNQw0y#>bdA^0h1z6b6S-
zxU<)^5})2t=qbsrqQh7Jo4oGy;S;{Adi|L{iF$K8b1UGAnDvr8AK%1-cwEFw^63*R
z`SfuPj{L04_kJ&PwR}KaE%<9bdkTNe{4hDLl9QZu`Ptt@y@4}f(jLghJGPx1-4`7a
z3s9Jr*UN>cWopTjn1yH>6>W=ta{@?)47|a8OAz!Y1%1-k*+^;T1gK(zz3t-I89^sO
zL*f5_q`r+(Bn$*f81A<Aqi)0pQ`~xY7z-(l_?SXvquB_TRJKPfUK|{;8Wm-C%Ipah
z+_JN#gF2`<Gbrj?V0IalO+29w;{mb6^hUFb_uxe?{Y`~45!v+R|BY~$nI&j&jKtBt
zr$!_WdbL$`*>b0{G4WK;S)TYS(2XtLgt8B4TlvfsbR}0AUv^N@LWSmWNRVblnX)di
zt(iTaAeKfL6l^`}9f$7nSp&MsPRSk%8^^C!Ao4ACXON>NquO={3cLrD_<X7a69eTI
zeUDO<K{cy@s_ZreZbM@E^^5WqNi|cw%et&sPqXo2K$3xUxH!z$GnN+_Vt=@3(qZZt
z?+kVZH%XThzj3XX#>EaO;GU@2tIRGhGUP#tA{`9NnJLNuVmr|`9vGT}htNRxB-YKJ
zSu`T~EY12j9NRnu10x9Pm=~{rqg)7%(!&ONw#1{ta`)+6!DP?0qzIsYgLgI-@!>z*
zHb5=3W$7ST<&F6E8zV@&iVro~)^*5hJLactAFwxI3#K%PiS|xyZL}Io+y(~;+#&G7
z!3T2}TN-+c0oT#AD>W#_$1lovaMFY>;cQX`B;T{{l95$!0SCs*x9c378AKqe)Z1u{
zRvNrM;y&yTdhFk&;wka>$Oj{BE3?wa6~~tS{Yi78g836y;1;h|snW|L#yiv&HsQcR
zr-I*ZODitofGHYTWBnsP_n&2_ofnM~IRU^yDq1gWO6f42#JUi3F2>$aX$OJ`gUj8j
zGfqrupYDu8U!e~qr5Pa&FDNn#$m$ol8Ye#TKk%Uzhbfox$I+Z3_mq88W<R(#i<*}M
z<v5D8N}c?o=M0aldROfU30D%b^+r%KWf0qeMG@Fg;5EB1l=?G(g2Suu{b5lBLVzf1
zHnR*1SpnjpjTkl=pvcdL(x#+f&Ecksq;^Aw8TBmJ>ltU2MgzsTSa-6f{KAOGfvVUo
zVpj_nP!{IETb7U?8dy<4P{<YXCvSt$6<cn)ro<9h<O=0<WNv@`D^e2WzYuXWt{4a<
zEe;NCLvzg%$Y#Y$EVU;tZ0rnY_|i2~S%S7H1ud&n1p(iYptJ_^Ndzx3W$DCyzsR18
zG_0l~L-9fyNEZf*W}rAV0!@ZFS>)3g{f?Ie-l%3=&^hS^yiL2v7#|w>#jUgwqmEe!
z3~49eK#4Vk0UK8fKId7E?3f@nhm217gO-3?db3mNJ0r~0-Y9e+U!AUT9)b{fvihfR
z(3pe-NpX-Pr?Mw4)yKywhk=iR6wl!1o0o8hqXsGk%c@FG)`{B%^zcSnb&qJ*lXw-Z
zb9jGj&@sp54~G0Tpx}!%$2{-VvpfKyV4bO?X|<?PAT0Om;mc)8+3xVLE(Ncm+G<!`
zQ7zEi8zRINhLtdlbu6uDtx9Lo5pbcPAx+<?vx3Wmku@Nc6$}R)G*+sm;SHt0s?SNY
z^lh@MR6hK@`+J?`DwD^@PfoQ~%qk6@G%OSgxKS%wYW9XNPksd~xsfLaDJ^kvG39#Y
z!#EeLfolgbv<BW?nV^d5bq|E(U-wMpgiM?<IUBe98+y2Cm43`+zpcKddie<X)*VUH
zkhaJ0LdlXpr+8{BNj@Z_a0jHb+`RhO&Wdv|GrfU^@hi}WOMfQofslS>;ph<dn9FDM
zAqrFhr&WTobT%KQD=J0$&8TLKc+$KxtG@uh)r;$?sJCTDMUSyM*9YY?atP^C*EEZ+
zYq?J%@_S0EoV@U)fWMmrQP(rRjptS~CHRcNWY)hQ5eJYMc*EA<k5?d*b!GS)BNj)n
z?<AAF%V1&NfI^;ld6t+FA!Yofs8xTwG#P+h@Su#qdI)^RqU4yl;|U?kuwN=#X(^z$
z!tC`bmCF2iE>#d~SV*J_b5ui!`5eMh104AVHqfQlb??YqSJTxDq|P}oOg~NpY4Wsi
z*Ox9Josyc`SvO_kXF@HhBY_WQJ}2QRYYozXud%XN(W=%$5Fp@85x0m~yvA9S)PY8!
zi*ZpVtM$>Fcpe@esgF>hyjV@eKpk~JqNVL)FpIC$Axq1108$7xWJ~qUUwhe)1y?WM
zTM4Syjr>~m4I@{E;caO&lzzdiA4)lLRC>tc#P(CA<UOT{6`otVJp8HmR=%@k_~IaZ
zdSrUrb>BIZzR)7OIJB{&l<L7tE9%EeYm-Xp{$TIA9IZE{|8Z;ehV@Sb)#4jWy6%1L
z>2#gpsBBi`lBaXT?hE#Ymp!m0?V+{vmtSdxw^f;C!>b}Dl)jA<MR+t}?qC%Y&@a9r
z;PYvzf32K@Of<yMj7s4mcqrUNlJA64%!kyy<@tmZdD+*uWwKzwOMRCG#b5oE`j)|!
z7hD;x+ZzsiH5{2vKR=xgJTYyC`BI*L&{G$$Xp}a)LzjHD@@u>^e%<aZ=E{fHeI#6!
zUU?|}(olQ7qrdc=y#HK!&#&o_dbd3h{LG=1#dS}F>!;gN@pRi;E)_qe^`6yhywYX*
z^TR*B<;2X()}L50|7s5;qD!}IQPps^+V}p1&C28{wx1?0T6_13^4%ll?Yw|8`tfhn
z{(rLG2S|?ly7QYIuIP~r+1ddG52qY?rnfO{b~d!JlwISE;}crLRl92ghY%^FwtVN~
zXa&zr=^~Nl<zSvGp6=-#{HC|DFd3C^jZ);9-rhm8J%J^exq>TlEKRnMz9|$e%c?q7
z;+!QIQMNX`Gp*<nUX{<v=k<b$tFl;vtm6Lp_3!uI_kG{@z29qZk_CD=RnE)ymFx;a
zx#tZNx8JPvU#uA4?lYgYzh7R}%!763;IcVsn=$g?Y#xT;SJWH!&t=2ge9tzj>Q#ka
zz~@yj^t_^G`o2FH4Ez8g4Hdp*S@hx<kTTbG>)!Y@D=DvDESD|I86-v!hKbxu3;0Bu
zPn0JL*7tw>{W6ZO%uR#72H2Rf)#*l;oynGQ9I5Up+nfK5ZC_C9?<jSRnN!WZYO_+l
z>RxrLUv7RwdHeO|TL0kLN||pmqx(sq8A+DeJN8bie+m&xDStpCl${x&7infu<I;lO
z?#2&}HFFv|#?-f*B+S3?hVkT+bv_;;5is?*WjpkEp(1BNtkle6*XYzL;mhCuU!b+s
zh3dYht+~-@q#>(1=4Wp8o{G#goVEgEY7ajhZu8CCx7E?mzFm10F?c8y`2DA=%j46l
z)%rdIgxcn<X^;$@<gVP)yY9cN-sI11Y6Sffo0w+~hO{o(S)hD2Fbk#|j(!SVbXa~(
zwrzEEdUTrZcK4=bXdOodE2Tj9jd1F7laM_IJO1Lsz{LXV9czd;%jWWayX@%uRyS&N
zqvWU?+cYvc@rI>Xs5(-mYDZxi9k*X!sMfJ2?`F%PzfF%CratkkdBQP&#r~e1xjU-A
zr-lS%H@AwbUcYD-I}Y{}bA*<0oTf7?Q(550(qwgmx)!~swdMN$k{LhmL?1IuzY(oO
zL2@@p4uh$k%{(v1*8kybLD<4rmV0is+DB@->@+4@T9UQr@!fB!H?r@^j$x0tRYxKI
z{q`l*um5$$SX(uA>Q!z0v>9ErjE-fS@gQZ%D#0u^hJQmV6qa;NaRW_Eqm<`=1-ot8
zTDKU<SF+3ON$l4!AFkMPXAgO>e`3$(!TC$8R@-J5?3tsILuVzNhRA-3oqpTh<oOWk
z#!H5||MVK)vK;-GGdYWGI1|Pp9a(cVZOz%=2mYHZ`zos#8c%YqacAj^&DWYccyGDf
zH2t%hH;6BrX?s5PgZS<}b;s@~-{0lycT|`=A&owy(1ztim%EczH*TegWe1BGE&W#p
zEffasrPcQ9tJUbE7dIPM8xhA6XHINeLA){Y9cpC~tv>q?-V5b+-F>anth)Pkv$4Nb
z9e9gQG(DQfVK4D_Z0pV*zu5ag4jbFe3ZLP)Ok3O9_+t0qIR_l@V?UTWUNBYRT|2z1
z!c4K=K%CE}Ny?CW!`@^a&vqs)Cw`#JK`25s->1;3UG-YNaav_<yu_#2hu)8Y4&Phk
zr-}`=oD!!apX~MW2J99K#jCY_8dR6#$DF8T4kA8GOn+AM^RreoUAn*BWTKltTxevK
za&vX`ti5?Q)~$}6CLL_f+32VX_PU*6B?=G!Eo1na(btN!-LY27jI2(Yw9}~_tgINi
zK9%FHQaYl5R_6#b!`$|7u6NoU6TP@r3Z{2a+kr)vs=&p<XYZZtaG%Sv(Ydwg=}vWF
z)7SmjI!<O?U99NC%Jzm>M4$Hk!8?`8Hvjl%jyy~cv@l)&re)i0$51Pa;MK0WbL791
zVZ~R~bp<pIS+&ce`2>tTKi;yt@j5pF6Ym(*rP5<L#tMr`hOfO=#;ccBD_XT4vCYqR
zHvK`YkCH%7!kITWSUS**k7FDE<A-2^qa|atxyHh^aoyUS0E~mEeXJJeY)F=cpR?!S
z)tjo)R5vc6_Cq*cHC8#sGU&K8dJ*IBW3V&L{pvz?-G5G94_WlC3PGDt4BPh`Z>ldF
zK(t{vEWXp}n7hHmu>)T~7=^r-480sZDuSI$tJQ-~z2Z;SJ9Z+-=*Jtx6-Sk@4aqmY
z^`8_U+H`Yme~FIN{b%q33rBILkvR$Yo+R_v_tfABz|CQgW$Y|%BRD@*5s=<rvR^sa
zS|xVH9-4C)sKpERuKmzVBqDnK3QgsPJ0fa%{9vsy(Va<~x>AkE5>9Pr1u3MLP=>>@
z-vyAhv*Tws{Y7UG8&r@SJ&bW$ic@&3SoN2fe8P{dnBM+5aHqVcFV~l~XuX{#_f0IX
zc10ceE8mne_x<3=wUedr+wRvYXA)fTwCqebUUH~^#qnI31dHh*^9<ud2V<ll8sG~O
z!{0HCYsOG37QhWt)3m4&rP07yi8lxY%z6k6WjsmuJ1fs4`TptZzO{LvzY^<hr|6i;
z-8p8J9L}s+Zsx2Wq2&KOB^(4t-!HH2(`<I}Vx=0lI@~2!foT#&*QqJY*>r=*_!`YW
zXOy;I?(aWMSbWhrc;3Q;pdV3caua<Tu6M!<U^ELCrtr|b>HgHriPbS<&E|qKR>e(X
zJ0Ns$^axUh0?Jr(xneGum;_$Xb{g?i%p=+G_(wrg6dx@4?N9r%-2nEoxesk3F6;4G
ztsCi<<3(u@mS($|t^6QoAKR6qA=~eMsX}Ax&N-TbszilRx$TT~hgd#Yzi+~_Vii14
z-%|vq-@vw{nXTmevguchD@Ie$BGTGei$B>q3Zl+^i^b<K=qY)GAFwC(Jo@Nn{HaYp
zYB`bb1pX<4q%+;HXCugnd~M;s__8Di^qgQZ?*1p5UC=e!>h4BI^TnWK_mjhWyc&d@
z*S*nH%q!Zy(#$Hu{Uu1#_;iIaag6#8%t(#Y;0lYq!XI3izbm%<m#mskI5ZzUyz6A&
zI1k`~Mi_#5WzFR$neO<*JkvlMq}~X_2y43T1AlxfzWLw2o?CTOYno6^jmOtL45OP&
z_}yGdx5MeiwanU1)HTI<haI{I=v-gglLr$Ne)xHaC*tUtJ)hz_w9N=9<Gcwju35~z
zkPRT%#+N}>hoCXd*f0mb!A!WCJbc%pn``cJ^qiwjbYgQi*3<YdBvHPW<IAnN@V54G
zd1`(`k#g<2(T!njn$`ufiK50<*#BI16#(YzDK4ID75KZohcEYZ7QwN}zm%b`#NnJr
z*aEnDwj80jXrpO{_+QS$8eM(TJ)R!UPdso6!IoW?eJ}i-4e(jbNnG(Efjz<;4DUA|
zfB%Wq&=mk(8!xZv`_H^G@P!d4^r!{X)~<cezNY-`BSkZ_GA^m=`FAQ6FjwLWCHBpQ
zvI8$}cax|~QF{(A?*I60RoPShL>!9Ds>ZWxPNX?ntasCCn)-7C&KCMpHh|p?jQ0xh
zsR;6exZ~3otM&K5PFiy>zROwooSB-lU><;IRrr;ce>h+DBRSkc^*&l&?Z%er-!k!{
zSuY8%hYx(=NlisZ&wD?FpT64sdE=>O70*~66T`0(LR;NwBaK=!M<9cFN^W21GgCQ1
zIzDy?DD?hl4Gu4cC|&NRM_uCF%rO|Mf_avL|3A=Gw<jMp+MO(jY$x$&fSfJvhV{$B
z|M|bcn0v0~3CgXmnrHh@Jkf~PnH<!e+R8Z!_4v>VO1o-6EcY2T!RLnz^A9S~66bTy
z8GkT0=k=};2Xk_d#8(#C%E@l;JzV&($ZlhA?XDlMi;={KvmhFPx}M@${gDzg`a4*s
zF$lJy6M>Rg5$YwDv(<c2j&ti+lHlC_GP`%Kx(`8)>e{H?PJ&b$g}rIW5_Uo^R!CrR
zzn})U1>~@eGw&GkeM`OV_~o3qHQHSj59TZCPz~%Ob)@(!Qy=MoTu?D#W11IR#GG}B
zwomEU$@DIWFtaQn)EvGzwa~nCYvcM_{LJR$JT|pu1*yVaXRv!~L`Ehyh4Fv?FHuOq
zDcro@cMrJs+ts61*ND<%JyzBQ6?{{D+9yT5r1<M-m~VIAZMzhNfu^NPn{NF*)bo?T
zRFdt@KWxu(6U1{Qq`0o>6%DJVlYN?L8fjcZk)R(!N&{|QlREtX<PIKdl2BV6ARNyl
z%WKU!7Qk3!`L{p#vpL9B46{F8Z5o}LAHxS)-IZIBsh6_gjqHK{6&seMcEMzlkP4H7
z!u~hVLb&megIA=RQNwVOmC?rhl=C2b3;XYcKnsZ$-v{BKpbXA=EVd1k?u^#iy6Bk2
z#F#(ebz;-i(htbAyMLNjyct~|5^KiObgJeda2U75qI0$C?RS1(40@rrPoA~ETv>~s
zd!-Ta;~yL+7A8GY)`09ZxUFbf<8KnfD~tem)wu3{Lp@T3<CzB^cg7zDMU5`8TT7M7
zg39d^<v@I~k4K6#UiZH7kmQ+~4*zyEAMZ3vqm1SoI48@ISiE$S1Aqt@tNIU_g3l{y
zj2RsU{))fY!woTsKmJE2s5gdgJPqWOtCNqGU(p*dlpswt%m_%hXNM0|1z+4zw2_B@
z%3fcqxI>2SfP3}wCe{a<!Q2`~8(cb4D=G=$gmy=L#Lk1CJ7l*3zjX{+3?ucU`xu6@
zkq1~vU{H^fpt69oz}U`}s|PQv`C3D7Of5*@;mir+!#Vu5ggY{s?<d~XJEA)M$o$*_
zHqslUb}C=iy1;h#0Rgsp$NiA{ZOOu!b5PnTuQG+{;Cz$1sbfs}_4tZCe2#lP*A#9`
z8=ma&uq?_hA__lyq|d#?A-HB)uxJHXtXKWJ5{K_=9!Alf#wL#)6D#eJUn^nP!i*l{
zH5rgO9C~e;Y@rGdMei`<**wv*U`4&<8=qHlMaFZ#HMBb}vlxs=B(Y!vTGg9*6pmsm
zm<VGbjl?wPhQVdc1lZssqpC;qi~vQ8a7}vRCt(f~^SCwh3h)ND3o(|Di{(|>{jLsR
za;!Q(aB;>NfXF;lq42x^%>rK~fecLXFk^RI2M!mBtY&mM<zrC=t)z9`H%JMGR|MqL
zpmbse%NQJNpSkJ>txY{{Sq{M$$ikg2WN_zc2zTI@2?u4tClE(ikJsB4K+G5Lgm?3&
z@CDs&81>h4!q0K^-TwG7=ZOiVnf06Tp%4=GIm=O*mH)lp5#bqh0|55R0t4>8WonZ~
z7tz9;v;rdzZTueJJK|Z(-c|RfD%+iYlWSz=_*|vBJ$_~cB2QL=$;KRVWdD|;#36r%
zWGJ~w2*%X}Fi=8RNc6ygd+}I7De(0YPeyd**#wm<mmK#I!*-&>c?!qEjn$$=8tHvw
zwO{yaz)(E&91CXC0Pq(!`CPOOXJtB@PqW^X=n)z$mz)Yx#4szAuXBLhALK4~y8KFg
z{4tP={R)!KJcjv(A6D+LBDg5O<6EAUa4A;<tXf^<0wTPH9+L$mRD`pUnCI)R9QOa`
zbJcihQ`_G%ef`m>rW=XfBU6$yBN;Eey_3nRS#}*PJmC&Y)u>JqVa9hfqK-W`?gG!Y
zEi^7sJFFx88aUB3kw*CjE}E@Pp52UJ$Pf8Y*~bZB)KdMQvv)$a8E77sPPEZCRa>-C
z&C|3+0%5T;Pv<j-bI<t8V)dip4deBkb8&$ux4ZrG)r0y=hCHsp9_l(ah1Ma<&#S#3
zdp<v#W}XoeyQ5FO64zgeEE9V9RK!}sk-wX*mu5q9(mrp7L04zkShPIMx4gc88Y!h0
zgXiBd)0r8D#*unJ@V=l1nF8uc5EXGq`^Y2v&I7m~wavk#edMI`ZY+*~D4>^QMZI?^
z$BDQL=5m<pom^Ma^_6MMgM3KnhNl(^KmW}WvofPR6l>K+T!)>L;=@aCSrC-3tIuU@
z`8E!DP4zp1WI0ARjcd)FCAf;VR;*5l6!BI9Rs^xizNNNAcP3r;9<H2zGej88)bU<N
z_dP;=8mK^r$xMB5UWIlbaV6)bIqP`O=1r)nu+zXyGCN3sv=CSo$|N@9-j|i<YM9Wa
zr^R0M`oM$Qk?=-`l7n#FeC6}_CcEAl`X8z=SnX@XL~I7>qq?v*{@CWhuiED1vK^@1
z#reuzbc!R@QT%mDxgj}LNf;Bm&Zc*4ymQN$TsHOOC{;+frQCv95!1xqUArh5%i|YB
z_&`92y?JtXbSPFig%Ao0m$m=VH)-e;1R68?89>}8ABfL)Ck@R;#9EmsC&}je1ApZQ
zSm;7kxdFTsezJev`-3KSSs$NY)9Za7${Z$HN*0A37@zj}H69dzp*tXkOa4tR-a<*n
zRa?%jB%S1jp8E;Phw{`7X*%YUtN`yb*2b;P<;hmp=gYm775x;h-EvCE>V&Pgm;av=
zd!em&b#07RX07@0$J*`QEj>sF<Pi4E@sEhQ!mZ(Eyif5u*?3eR5_-{u%!8J*9Ip#&
zK80^9P(1iNdHCOCxrGVEW=*-;)bSvyvhyv1y3`IPS~|H)Qjle~4bTt4j9T5xm8P+^
zIo9C`j{oSqIM?GaBc$1u_YgRL_nV7(ltPTxYPh~$?2?y2#FM}Sy@O2Mvz?#IBvTwV
z_s$r<&U=>_6o^W_%{y8R%|a6B`JS1yu&Qh~8@!2qplUb8o7ooPaM5VvRUIR75EzM!
z%C^Bawt#^CgOUXawduoCCe}P6O8Z_<S3cPvX2H++KmNrDjIg(-=@MOwK8f>w3c}Vl
z(?(!YFqrxGY!-P{(V?zL0o)HsiEhZm#PZJ5Xd}pm5x_5-7MYO&%Og|2gx_xGQUNYJ
z6w5wIgs*y6DX<aR$e*JmD1sdTcS#l#C{9p<4FzZkyxN!)KwyLzIZp_`lHq5>RbMjP
zoQ%A~1v;*rFV)DmkZ*sjy;+ZS@;N73Nm3&wFwFR31k{HT<oP`rWK?&T_jxT?YqK%A
zY-!yU4ZW=tyygG7qI8fi8=_V6J|bk~DWh>)aHJQrjLU7zx-n1N0l6&#-8?=d3Ub$k
z-d%R#2gtqTjDNZdi;8DTL)eE0kiQ>#Y`KxMmp{J2TTa}Cs;l)SR)XE<=<e<LXme(2
zJITg8q>%E!2Zt+cpSvrYza$X&n$!=#9nPq=IT%b@9g@)*(Krh}tac7}2vRtF$&<x*
zJeCgLqWS4gv7i#t){Os0bkDI*y~~Z3h}}6ytsXqTdGn*4cCBba#|nWczGOQkv6Fv&
z8OvviVl|h<<m>z64_<mji`PfragvVboC**iOLHj6p4ujs*l#K_#c;gj66obTg%h0J
zjMs@Jjr&?Uy*pQWUaR>HG^LY2)Doq59=5$kf(SzK1<4IMmEJOrr)*5fk+6#j5mL;X
zc0tJR_}nFD{Bqmq>Uz;c2wPcM0Xw96fJ-RhtpD4q((rQf4y1CWV~&OHv|vXAEe(w%
ze47f8-~V&0WSFRa;tsAbo89<%V~3gxd*h!S>*#Wg1`uhi_z%=K`O^u*4gpeSqEbtD
z6Cbsr)wUpiE82{Iaqh7{V*|ZvGCV;7Asjsyixzjh6QpyyhwUXT3-qKuS|Y9ey&q+%
z6y+9-wMW(-xzvqc2Da>ugE;LZHazkkTYx#RP}Lc_+^c`Fa=Y?>Rg7x}nTvcbkDq@<
zI8uX@KS{%tY4`z>mpp<&<iroJi5Nw25tgmx(Qzdv%*fX2Qy+W|l=1rTwY-dBa$&NG
zjQ28##Iom+HKIlYh_k;v{Fd#t4zUlUFpyJnd{WP%InhnPc|yLf-U_MIZY!0i;tB5P
zx?iX8Q-f91H1c4y7d}@KOM~nms_Xt^oI?(C%@d~Tew8TRE28Tn`ddc?Wg>HI+dwX=
zhf=TApm3Oiv}Bbln>rsDfJ$0?nUBWCqs!enq@{2CFxXP=k&V@&a+QLoIew8sk!6_F
zp>O%~l9SxMMqqfu7S!tSlmwD<w6IoRY$EBS1y{ZJx$40)2$gYcd1*;GD<8JS@gB-c
zJNc3ehT#fh0z@SvK=Nx?$66Hj48o;=hQz=iUy6*QfV4}w>frgZLAltcQez@`c!a?G
z`Uw_PDE!`kOY4o;d%e%bt<~L0dGqYSI(4mv8ANy0-2b%lGb`AWc;W@WE))K!0Mr*q
zgU_vw9^2f1fhz5~Y22EpD~3PKcI@FB_MRG67@DC5&?Y__!u8l{GVn&+wnx(dl?J9Q
z>Z8s+66N<!7U90T>h8g_J=h6LP0cQBhEftpSL2*9ir-9sR5qOZA}qSHw(LfaZH|8x
z!PJRj!<^17!qJ^3N50Y`wCt+h>yMwY6_YaiUpBO86>HY0BIc!~$)p>ZWE0HZXlBFD
z19Xg)d3W7@$Z`m=-l9<;k!h#YERe2dg#zfsMnBG(FEP`NL(dof{6$U#1uaP%S}sDi
zECLa<MC`fnC;#?TFSjSeFcA^TRE(=P>%`ilc0fhihwxlivG218cH7&#E-wqMRG0g!
zaJ+gw`o!kho9i~@)E_y-todO!Tx1<#rXDUBI(tzK1v0#t^du&VqxciyU`W_(SYkEa
zXzxaT-tTU8+dNo8^S^BR(-pH3<+=wN!i??%POwn;;$J-~_rDQNqGg=Rwl<5fOwDNo
z$$Vx96isZ$z^;+f-&Di;lW2I&3ij>2TH*GOR$-^xZRy=mu{VN$9XkFg&T)j|!Mii5
zA<7;{ZHo`|@x$XZn~~aqw5?1M5<W-TnpQN-$unh}W{sAUPEuSn|C$YoUYr-e0$_aS
zSE=DcyJ-=mYj~e4Te_G~!<hu5UB!-3P0MVUaK@1+j_(X_!#Gpn=2>lAciiOz;20S(
zIi5MmA!*v@vK@ct1T*lz6QV(i%l3juk816%HkllI03qh)02~&_%;cx)La$!$dq`V7
zeXt-pw=<mvKoZ!Uc|;q|OwyIY_1Axd+q*!whZ)zj<w=X2V$c{QPMg&#XNx@zQD%14
zcH-`GyZ)+M9x}58*{r<QUygtJV%yS;;{<L5&w<I=dGvs-!jy87M4Ai6NdzerL`XL^
zKsd1#NLw@brag}ZFrG^5MHc^P-2qOS&eEx^oS3YmHOuWcU+ypN=DqVvYtgC(UFL$&
zna%OXG-wgl5bVYoJ2pl0co3F|@;-}r{Hn`6s3i@OZ$zt{NE=eJhBDqLdTGiJ^*&G`
zu2*t_q))Vd7)4HWJDfyT?)i(H76J{Xi*mr<LhR%=hNO85M)%<5E=V}hyNQ2vESLfm
zVm+kAULX|1_{IA_EH}#-kWdsd3V0rn&|Y@*iIpZPc)yZm$XfO;3EbcanpyD}^jSW0
z#i*33%M5@kTf!D2y>lFg^A!}$&t-YF;*uIlPlXsp1!|q=vKqiiT?26~J?>(~O0DF{
z60W3ZGKc9H4{=%JJ$?~dyFZV#<K)oh$ZfRZheFhE{&$O%D;COY-gvb}`^tW~{7Mny
zCrLIq8{2scrSXA(n_ZKV@{t<vg~lIN+*d0!EA@9)hom%7-Ed;4(Uuci&MiHgQ#@%6
z40XyCh3B>^iNGrX7D0$ziMP5%2)aIx5^F|)Ehz%ALOpmLs1=XW5MsvbWvkYBbdDYl
zWR)^o0-)G(@aPF7FOP8#5->BSATw!q;Z9}>!vV=Z9bN@2l=oFE8aJt*&#Bzc*b)Kj
zg~}#Qh%nDlCdWc@?mEqkPa&VgZQfy+n+F*84gRo=;Kl?nY@0&mTkX`C_&C>`Vnhyf
zJ(m3gcplfy!NCWs{-oVTJTQsL(@bR+Ur+3TY~zlfQSS%F7x+h7rIxE6f#QjAy<2n|
zexj$T?;w>7k_{}}@2Kl6XjfH_+`m>8#xuL$c0cKvQ5_CVb`@!)A*n&GfSz{eO7@OT
z2SQ%!kX|5nz=I%wbUa^nu2xiDQm|&TnL`o<>ra-LYEdpUu|57di*juit$Auh!8CN(
z7;wA*{Ud?>%ilW*-p#T>FAcp`2j$KEMpx4&UN>@%sSK&vs3kQ28ZT2t&trm1-s*7`
z>9!uhI=16yp+D^8N;Efp{5B(glL?Y8-IlalJ}`4?k|+kU=1vey2_*!2Tgb*p?Gd?M
zBsvP<FuI&?Jlg@REh9+pXOJqTY&buWL{=QUE=R%-B?him%;kE&|DIQ3i$Ywtv3m<w
zjMaLjbY0m;3I@DW37`CzLiX#|-TOEK5V8bk+}ezE!?Nb@L+7>TN8t)xD&7}45LiAR
zS3N>Xp%%69G^9;4@e}yhoMcH4S3-eGb>nriJ8(K;ULR7}C!Fy!4nb3;Sr^G=9y0`N
z2I#PAkzs%3AG{w#ha>IRIa>Z+z0{;L0lU-gr_)w8R}a)XiWWe!=sg8@3|~-Z?5q<0
zrE66f<GH+lUTan#HQ=FoVgszs5oMMOYAz}5faGL5-)ESh26ru*F)0LL$kSN1g%$?g
zhe5CwMaLjLa<0bFQOk-xeyK{FkF2f=o<fi13oVD(!m<I$QsIlsKT@OV8aYIQ_vuxw
zQayXnGP;75riuINaW>n9mtxnKhzqEN$VzO?pUPyc(Yfj)^z68vHqp9Klt#Owa29?q
z<LePPu8KQeSCu1DtP{T!6y!3$R@Ah%8AVQ_?o)v?lwzcry1_bXB(hJJd(lgqbzr-w
z97=&cH4C5rACyiChYvp0BS$GPX|>7CV0W92ypE|y_Z?~m0DESyCx=(VAwdKCOdh8*
zb4WAF6?s1=*e(c6rlLny$4DcEndXv#$bH*QC}~rD;3QK4M9QTC_S_SBCdq)_JX#1C
z>;<n^UgH8aS53_#+iYs_2QfH;{nk7>KBlEaTs8J{+QGvW{^X~H{xjR{Tov(warbo-
zs#ZThF=&}nvnK)rHq~<HESnSmmik%f5zPkI-52^#Rp<vUlO;X7HlbgL4$X!+xo4>!
zlN0BRZUv!pqjvisUXd;<z<kT`{aadkYfd%X*Hu`;GG13f{mDGM7!PUx_?+diACa%p
zbfDl{bKh8mLSq=c?|%BvK#qk%v#gCy8$DXtZho>m*)oL<YeC+X;QXA8+zgFK)X+E@
z{$XW_Oa0|Cz1P)+OPk}zHe+cw@Mi%yO`Mayp9`7gd9V*d*jTMdSSgyISC`a{I+-6#
z@1T&)F@L@l6Qw-+I7o*u!=|Agn$eG4+>D8yPISwhS{YG}bIE{akfU(@f6h67&()SS
zmzs+Q=f8Q@(7N7~&aIXmOz*BI_WGNObek13a6!!C)#lnP54h!Od=Y&VT<VyU74z1v
z<;k)ipw8sLEUj&>L>Nk*5Kf7RgnR-y`@J4@Y%c&~6w4M%J;|_E@v3~;XEy8J<T4oM
zB=?W0Dupz6IQj}S1)l=+KKSoBVi7~6>JzP&dtO~Xz{k-gZ>^;1%+b}#mVcej2A_m!
zm^@ysqsr8uRsGj0R9&i4Vj2_6Czj1R2&Ak6`~_SEsHMLe$xa#%j2b!W1Q6*N6Nr%D
z^eM?c#*aU&0+6eC3r&F9qMxm;!3sPxwr81q?cz)+42gp&6n6gzz;j)c5RQh{RxNsV
ztuFdkTlhh0j<WgUJq${;BoEr3{LU9DK7!2BPMv%E)ki4mK0|0GWpBj0o@2xrJN-@3
z!6;tz_b9-SmkDpOkG%W%42}zG5Cc#bqRBimk9GQ7TVx7kA+Nv6NF;!WT!L-D!>Nr>
zqZLLboR6pph#cBvwn_}8_uaq!uV|O%LY^k=jLY;Ye-OcwOrSx`x8{iSI~x{K2dKcA
z@B9w3?sndOP}Y8{SuHjzoAqtqmvT+iNqt4>@zB1Yq!%_Mo%Ill>{5+!?nU};h>P@<
zCKxKG!QU(y80AE647qbUs+%HE$={pqcGTAFBQqgOAR3_`96BXJC|}I`(|;M60Z$<8
z3tF4e$Je&w%N?qTY<<=ZV-?)Bx1kYNLpmR+b$zMw3&xwuT{vTu_heTHr3WCDw@9in
z5;w!g@HA)~&iF2~rX!5^zOda=@M6!Qe76va@+^FM7{K?&k5};=;i&x3Wt06|#ff{`
zWY-hSYt54ln-z-zie(!=`QN_><xbQ)q*dviKD`G1^2|3sIfB|!?Mg<r#|crJ4B79&
z9<u}<{{kHK49uxg>3>`y;$h<Z&%Sc->??T0K-2ux58xMfq(kh@oP*p}Mqbf3!Wqd5
zHavlmlh%o`6ug-gC>_8lRg+gyOIb>N3<^_6TVA{Qah3wCcH{fUG?Ak5^0Zzii5gEJ
z&iU<sN5JEIq`<e_ry?r<eY$(FRE--QXQBsD+9mdWD~vaWQ(u_WRW(Rn-K~5fcW8(Y
z@(m@J)8<X`p|j8kLIb@Txah{cT=V&GCiTpqB(#rDY0JAUSs4QA)<_3%;m77=*Cumu
zfL@(^CwQH)4v*){I!7-oS(8w2#FmeWT6V`tt$FO*)CF1&j46;9Tj;&?GjvBhe3E@E
z0{*&x?us*h@g-C98@^o2AlX>?@xAP7=x@{ewpZER`vOr&rnY{m@?zzPJPjsS?F&?%
zCr#5(-lunJQ~!cA0Iw{Po3LwA=DlX{mLTKHNZ1C~0DNyS(K`0boKSHF#wg1II|S0-
zxgqJe*r!yG%bo7{d1~I5HD@Y8$tl^&v*#F7$rGMs{KUWc5ut|&Y1~6+OUslJH*bE*
zY&5(@%G18HlH@1APSSBD3}ERCmHxtq7_CV=0HkPtxjK1%^NG3^H_S*6N_I9<^g6wP
z#}JZ)9&!TLjBCaY>mETnThz5$V99X;{hems+=yEi8%m-niWDax@(%Dzx(nx`tc9R}
zM$tZ&u7Jdb&H1p~6V&{ZpMAgNnK@LMG%su9Oz~E2VvVfhAe~W7QqAnAvY}0~zBe4Z
z{e0I;{g(`5ziw2_11g(?$rj5>&GZf@Jm0utzhh@7Mh8~8V8vIB@V@7HnijRG;Q{xJ
zERE*Y4C?^^*-RKrbv$Grd)Syn)$%2x(PX_hd0=^Sa0*C>eFvKceZU^$SI+zpFR+kT
zH<Q4uVUGQMi_Fx*Y3>B?Gr{gf{NA;8M3?@<y(fR+P4#WYLi%n$T1LZKH6O9N(Yj{F
zgRZ)zym=CW@3-0VoEZ`Y85v*<S5ajngocS_S;`6Gdvk8^j9N3E1#8b?r^i!0Trl9f
zZX2B$DNja{Ml3m;<FdFdvF^KXyg(;DyrHPA)gLkUt&2{qwL2XrRT?}1UzLk3cUkTp
zcG7=xi8dTL`rFO=LUXOY!1YA*0W-M(f1;gy_!TskTxShBd{6#?e->+vxIwt%Nc1RG
zWIeP5*i_*X^%}2KSP-d~sLXNuBwQ`SY)rEGicc-cp{Sm(RY>^T|MWNV#WGQw%mLJW
zsq1_EV7VTV-uEON(Rl3qhQcZ^>Ahsg&knU&WoJ20Uq>wm$qTDUZ(VTW4RVvOD=Mki
zg>{3dLu!qeunbzu3KB+fMr0h)hxj{AFj+@Q<ERav(++se$KPG{_!)ytk^G@SZHRK5
zz|W#1<pNUrw;TWAB(-GC@L=3vRNg%JXq!{Eg1}@QY9*s3i50-5-%)%0uc_V2nU3^4
zookvzjof=5tDZfp`<iE@y95DTeIvs{N75`J&PXS%7%BZB7XRvc=B{xIc@^d-9ETOl
zh-KLYw5ioK7(jXR=ErJmo)IH^`KT0B(NAH}e6Z$oFFstec&kPuk)Zims?n`B<*bxG
zLfg5U?QE<cDaisuHGcfJOH`81@TxPO(`Z)f2W)i<g<!5l7c2~K-n8AmBs$zeQ?4(0
zF=?7$AAZ8`XggHzAVrh=+I%XR0eB!BTRmL(NhGan&H-JRFky)DMB@xWnnh)i?E|TW
z!ap|ig^!3O<7JJkcwDYv(>MW{ACxa?tsl{xI+ZMDM}<GThnVnf3N)8g_+s<6@pKd0
z8h_M@A6wPzQFNRHWSYoSU$N=eB4D9uBcVtLrS+%nY5eUk;@<isMusa`*2q4AV76N%
zZE|^o5knml#e@|{>mxr%ca;^Omb9cYDLKU3|NFn7Wr44zw^NHK*s>p|H}}zn2hp8w
zY8@k1D4n*vxBSu|-|$zjyXS3DO8!h)yxG0FVB<edM44v2JDr*lJlJ@E>(czUy+`d@
ztR%?e{_q><+I`@|l+Ic`FYSD1X6gfJBU?G86cMu&yq?SPC=ierJnhov!C6P7Aq1_!
z!d9R-B4|=7#bS7Xy22f3q$3I9DiUJ6<L~RRqVB+_K+P45Q+ICL56~gJ9X4@@z$QTQ
zTgLWnV;?2FO_58}8<TZR>v)PY9NJg?@U0NtV$h+b2d+rT(GnF=qgf=<EpiIv+SEph
zaHRS{(}kRWK;@VZW_Ug_dd@k}t)8gw^iA?5hF_vXByY6%);p9B7J9H+(tqj^e$=Wp
zBARU4=`_THB}6}`b`=CMQ~e|LkKAoEh%&>9;A32cx@c3G&^j43e-;qtaI$%cB$nA2
zV$(x0=^jrXx5!4@@J=tfKXVcgheYpGt)wahbJVeAPuoAo%YdEnW8GM%9uP$IcV;s%
z+MlzzCmk(iE3b`~*NQ}xRd)5I>V%sP^wo6Pu2c3r?D*Rlsro69a^VcaWcy2rrV&rt
z)%a7@M;(NlQzHeOi#Bl${p^y0-;?U(bzI-nih2BQ3r8NLQMx;|l>i5;=#|7Cq?eC>
zR%=fXwtaolIxclFmr?)<gtGA}k?{8?AA7%i<)~iu`cZi;S~e#?M$=QTF}a_Z6KBp<
z0neiNTN;vW9l50A<^FklufjJ(7rXJN)+U!7ZxYS5v=yKQaqQu5WC&%-|A<&XE>{x%
zJkFl%y=6|ex)bW=>HDCqL}ChCvJkr2nW7;{KsA1DGd@qzlFppD0`ap<K!va1saWr4
z-dU89pRUVt3B4w_3T`$e_lzdclJ<-*w}w)4#^(_!86<c9P4%@3yXJ8f!t@s9UY9?J
z^rOPe5mb5LANe+LSO`wQZATk|TF?vA_kiZh-CIwYDHxPDD$f(8IEMgB;Hw!K#QWB^
zw-0pNSrm;Aa|ysKt{KVC<DbG8zqW|gQimuso6X*&ToKuQbZ3@i9tn6T?;Hl3c<o}g
z7cP8Vxu=sd#{iydR(H_wit`{|S9X?Bx`9_He&&dK1v!(x>TOfqD44qMq3d?cTSlr+
zFqjQgM1mf>ih_yF;#WqmzhGmqwk3||B(}#=v0QpUJuKlQeEj{7KQvj5vqE3^<faZj
z`94H4J)(Oopa(r0=EVwRk)~qqB06gSRfA90Aml~QY--z+Ejg`G5S&uk@SE!8OrnQ<
z#A;ARY(D6pKoPSb2|7PI2?7nlkXw`)z{;JMcg@y*iEd<1pB%PritV(P*(|yywnEZ!
z__u|csALRitgLBct5T+d*QT1Ecxhs**`S$S_l5j;*CmCLHuY_)N7XOOy9>C#xNKZ8
z;}<sdffqkGPVe7$7VYqF6!?X?icof&09nf6OBE3o5NL2S%ZyBo8Uof@s_7*LAi{)1
z)f2NFeQ;B+>zYpS3a&=2amCk550UHb&wpBMpy&3Bw4JVwEJ0h1lZdI0(<w1+seAUd
z?7A{C6?W84WpB5_Yix(ls%>5#hXjGdsns4OV)^O)U`iUZL0i2$13Q66ib#6~7SV@E
z(mG8A*07H(Q<~-J;?$8`F&PX;csc126LFeM$gWUoXjzt*(EyFfST$P1<)LZx{>Se}
zt63lnvPg<uL^h-Q9_G>&@2BYuLUq@{XE5E0>Tqx9JRn;^aBhgu3pDde6WXzGN90>0
zG!S=T@Yj8a5}lID{VCx+QpCIJaS;Fr({(K(G9-i4h<yu&G(#6gIa0~q4Os+lzUD;%
zyra7VxG5~a@MCJliz*Nc7lvtk=I4JjZy&3>piG^%$Ah!4pj%DgNnzrl@*YBZb_7Rv
zResyTJ5#v=c{r13eN7{9>j(ACMy!dVq&cUQbx-*hAZzSfVAwXcV`p$47R_@Sy~(=O
zv5BnRl~}WEFn7ZSZw*<@-!b1;;`0~Vi16LSPBEEzykS8jz+Exm!f$Re#z$U}qLpi0
zfInF8a+h}EQ_D2Dxf5>?9j^OFxEa6vNZsDEjfL&fPQ6Fb0?G2nHu=U{Jn1G`FW#74
zu=}@d-s;Q&Vh%EG<hlo6C~9!ZShq%vUaF<hx&$(&4C0>o)^VjBUt?rfxojRhQ*Dgt
z2+}yVfY}AUm+vr3l@0#--~KR*r6p+pX-coFMt7U8Ka$37JP6`>jUvQ#V5~2#ykEzL
zvPvJz&7=_Lxg&o1#JXgnP>u#OHubJ$t%Cwb_+>7j3sOrX{cW;ovEbOUyOS;3)`Eod
zzz_^>bFpcBdJywboy^!pZ!A08a;43GN|{t8sWW+wDv9zWLGAm0`a`H1_*@gj=iL?N
z!6zII*`JQB$y4U784>NSntxMmDN$uYEcmzI*{f{tkw}N`3?!rRuJ5`NLhGYOPz<Jb
zQL#y+Kb(;#o&3qQN18ldGV+_WvT}MXy&}Yc+CnfooKM3Uag$}M8?MyifMKDY@pG4Y
zMKHoiNr;ndt|yRUUs^lxXPWDu$&Gno6(P~A*R`83ztq*DmSR=Jm&LghTCj~P#LbKi
ze~qi*zCZk*@F$+N9<{knvet;U==q%n2`vo5bV`I6=>%g^aBfkTlpvaieH3db=&={z
zfU?7LdPJx4AE-&V6z}$0?P#MGQv)=<D7_%rB?1i;3SAP*c>9+R1&E;yaGbG5zr#ht
z=r#ruElrQ87al6gQ>~^ADa1Ugc5`pLk|9hZ0C7L-98k<ATTYQ@^St9k%{&Koq93tV
zQNN`0e^OuO-mh$4ja<g6MG@0KBQBNMHhFA7n8WHQP|;WgS~JPbi!3L;;}qwKk2MQa
z;F+FCEdOd(X1s7`h)zYWdPJY7(0PsS@0n>wSlLlXqT~19VsBAMk(P&y!z9UQ^2!IY
zDIo<n*J-Kf4)nx2Mmyv;ykV0=OMj5$qf*Atb0i8#Wcvf|dbc!<Y7A0fCMom=00V&#
zs9+*hH9B4C?U$W89jqF(;e9xW4Jtb&?D)i#cZ(91t72HfOS%i_;IJrXGDxTQY(O5K
zJk(<vG-zj_WoxO!47ME_Y?do#OzGa|sQn)y)Z5DXZ1#gHY@R%`*qlmSGkhPkH;ZP2
z*iU`|*3uh_3XO^nt<8-?vFiH5sNUoKjhOLcmmFU!ssLNQ%ad`xZ(dRXpJEqZ{^vQD
zs4W=85^r+;619G7^qu>#BeKfb%pG2_^Nz+h6*ruQZhxuN^nJItP;(E?Q=zc3Ahiql
z#l393<FDJ9BB%I=l2OPNCS+$Iggfg4KjbElf67S?fwehN!+^}ZYr2NHh+3+Ryd>43
zrV8Vd%Oxk4`{i#Cx{2H)UePhu#1K71jE*x+QjN`Y{I^1=S-1m|ad{f1v(4+jm=Itg
z5o)84qbc$AmYu3Jz+tlBbGYRWnh+bn+L&`;&V==P#kNI)+3F4=rBT!();cT!7gINA
zw_K<#FhbQUR-7^2KN@ipN3<m(+Ya>KQ&<7f;^HES2XMx_U*J3@&48CQ>i%0@eHzU<
z*czpI8O}kXDK$1#U!Y0No6%`0ZVB01AkapBJ8F-pL@4T3J7GUJS+0(V4FJLP!H`sR
z<CaO{P1(xvqFpCx1?XRFdcNjimACR$NRGu9txNpeM>7=+2q=VPC901E49?&9O!-H8
zb;5VOrtQ<`IBs8Z4jMu^5-;$=WaC@#x#7w$OLN-po;$z-di58)r;MGa1+s6Rx#D1m
z4O4~(&@?rVLy?mI##Z_C1tB{&b}MO{OWszb!lf@F6tVD#Yvd~7$a*YUVUO$|FFuZ-
z>xOoTQ6HL4i=hhGFg6+QNcbA~5v1}j|6Ojg6fKIYmDSP5obh>5mdSUz@4G(_SGN2e
zn>36~2FXZ=bE73QtL$Jpqt#w?-g)9|ObPSO{lMT-OzRGLyuS-sF9|o`6pe<V5g!n~
zL`5a<Hyh?tI4*q7cNBTB(C~Lr*95k;0W~;1Ju+#z#$Y6e&+|)u)=&QC4}oL!)6|<x
zLyn(oc97p1-HALD{;2%x;T!h%Y<@e>XPoc2t{;x;D8JlO=z9^ZS+S0nF_=5aU@+OP
zTIVE@|A4UT*w6_uoFqiR7ly&kO*AK7vF|$uW3ERmSstrQyE7}{O&~_k9a~1*iM@G|
zY<#paSH6@1*xeiw+HcfE8(wIZA>gazP8AU-PyrD>q9e#uh`Zlu+UvsGhe*ST8j8qc
zt55ckF1<c7m_wPk0bPv0(+)JKgcrP_9-}OTMevE^K@c=wN`X8a1keG=xVT|X2SS<w
zHA!RG5k*_iySf^*cygwCc3<=fRMCku&ySBskeDo-!}yEkACi^BMx`#gOta%l=E2#Q
z3f;wHg+?rS5u+;5$D~L`h3wb&?7X$-s@u542=MXg-qnL=Hg)aM_B_$LiUo8+)QT;(
z`eB21&L(8>HG=YlrEm?I+u`lmyfi~kTNL8>P*M}ph`_T9k*FTD2uaf0lun%y7yeFJ
zJRNd8E?D@L{~)zxDX7&eWwgEh^Om!J*7OEcxYPSw!kTiA>AKSM1awa^>IqSvm(jb`
zUuyy&48&dJmMI#$j~B)>aq+iQ$G>3TA;r%~??E}XU1IrbY&f@!Xt*>PP}NAR6zdJA
zS&xiW0`EzqD2#?e;HXV=@Tv{Q&ql^Ejg~>&veg_vh1?T4ZvPQe;}?3=u}FJPv(=0q
zd8SKLg23esyyR9>o6BId$EZP5RsXQEF#J>XV#VMV0u8a=_=B6wy`lJK(rK8^oN4w|
zZUU8li(2u!bu^cbQjyabCE`$KbS8&R@Dyt;k$=keohWH&F}ac^om}G=x(zQrG}Czi
zorrCVaD!>99G-vw^-~nMnaqfFP&4M%G?fxFzAREIw*%%r6iD34Zsz_qOe+1y$(lZ7
zQ2x`Jl=810oG;5{CQdKXW{xhc@GoORZ?b(<VpQP+=u`B3l^|^}3jB~piBzemCVXO%
zRq#i;KCxw@czs+qZ??E>YoHAzv<NUb1iP?nF+Z=Su#G>t@@Q{?L~xCSjT*w(y5yX_
z*%)awd2~#b*z>piUxo+mgaIuhl$rMW_4Adz=GDFiu^98(N_+GIs4$rvM*#}tGz(7_
z40?#~vWX8h3TB=F9$ur!l|@t65cWXk#D|L!19|tWR9&<hM}6=?Zv23a{ya!7%$!rR
zSym8NmHyYi_%GiFo0oi_iuP)G^pbP%VpSI<bRJADplgmo8>ykGc(;Obu{M7jUxBSL
z<9Kwjdp3RoG&Oz74jZJep+CTSM^f?N$)tneq$GCTTP3hD{K19*(LFp(f+^L!MW~vb
z0fcw__`@BRlfG$Lo7@Ytl|ymFfi=Ti73d<4$`1d;|N004P?DzN2-Lt5;!m}0Gm^6U
zoLl!t{^xB5R9t1hPzm-#8dgj1G^tb=<(}q0@dOMn)>BFity*%IVF8Eh8TlxiOTKgh
zcQjoxGYR6@l{U()D4ovi8BH^&Khn7zlo%^qTfpfU+SJxAU8KFhk9jC-PQ1}c1gQpt
zaJkpL{snn75i+!9MH(k7o0CsD(Uvo~rEEL1xyJJ#WR8%sJN#9tU=feY#hG(tdE0wZ
z+@w+Sv5O*?vw?Z)7H75FTsQ0si3b?H5WEoe$CtJkYQGSSh7U1CrI_0JR?8*4-iZWH
z@eXYVsN*M#JGX5koz8<;*}*B<24V`E{PutT$2BAkFzyipNo9#t^Ne%wjKjAH)1ZKH
zckX{!T~Ko<jy&pzDj$%xqZgZb2|8k$gckqw=A)Wrrg6t&5!pJB_9kB~$c%C%X@Kie
zb8LIWK#i!<A@hy~mggiJ@Dk#>81fClX0mBky@a%M@YqF>`6#-0$3ilw2rqgVGfl@J
z+`s=bX>y?FS_Bq=+4J@v+nl^W>*>~!`MxL!Pu;Tz1i{c1>p(QQ0mSvbRQZD@U13xW
z7#l38943wlH=Ab88(G{^Atw_iClZ_7uOjyro=o*lBgMI&M(q^Ng|y&Mal<xHH<lPy
z&4n0gb6}^PIu$W9vg{x_&agSkp7}<L2mZwR`*BqOW|bU|8=B*`b2diEh1Tlq^PFr}
zY&raMnM&mj(fTUaD!hvILzPw6z@TVWqPai@Wu@u#0<HoHwr#`}cs>1pCpjLOm)FN#
zNJ9!{LyHEcS#qZI1l*lvb3&S`CY2jxc_$#Z06ago>H5CrtAtT56!4P6lZ(iFDQo_#
z>U-&isJjcsh)zov;ldd|*D=s7GAe@`K}f>TDqWBm657e$7f3FKunlC0FB^{(%qQ|h
zXp8vjkeAxd%8_D&Hvj^6xJMtI6rU`5U<3wf#esVf#xzA`L8|C#5xcmNk93l=M(~4S
zPd;H=`OTo@$O%QTpn3<upMczNMyGNIgi6(lG%vI|G(2gH3ur`=XRd5yHnY4!LN2H5
zh4k#$>IL^7db~Ic5HDM8#_2heDK;r>0*C#t*k7Ui3&>GQD&=)Mdf{DGt3g8Z_1<U3
zRT_p#$oaJ#v4~3b$(*7|Y^YeZMcc9hbqaCi5Vp`FIth5Qx4rNFvQ}en3DWgda@gfH
zZNFXh8+yEsxSvK2`4~Cur^C><kLbVIQ?ChOKV#oE+N7wS_rz7`S+pe@Qc4?@(v6?P
z&7{-$<PWbAL9oB?-Iw@8;w%0Put0T^2{@qU<Rw#SZh)UXDNUjBZX@Y1`?2cytnJVn
zb<59=;rQNMm)u2Gt(fr(1*ObTH0#Sn3be1FQ*twC5_cn-4U<DF_=^2abqHR$!;WGs
z;{Zb0KgYaI<c-RRaRnYEI0_<_B9-`C{_t~|OPvmCA*fvN8yOD778hA-chMjlNzBNr
zaV@rlu^YsZ@lf7L!)=xYT4tUxY&erX3Kd&y2b5=NSI%QO(DvltCw}lmG+<QBK4G0Z
zYg<qi&2sc;mU1oD`Ly5P=qRjFik#IW`a!R{zT5m6C2!|2_cf*q5E(r0RvhS&nq~Ls
zbd!vhyO<P{xK)woP)Hlp&LKjrj!mw7Of3m)Ih@g^08vgV!I+!Bw6P#yk%C^LL<fx~
zZwiqVLYsivA`_5j6F{y!A@WL@pyTbsWK9h^xM)u9JBjHDqn^KE=a;}3WFa+WG$cmC
zUiE-^*d9P7`cAuzgci?jM|vu+`wYIk>Ys=!NHWGrPQsF18nb-HlV}mjlw(2)gIpdE
zL*A>_-z)J9*}Zr09J`FlC9>umtI938L;#Tm|J6%Bl$XhBEOwdl*Ue|kwYZIwPLGZe
zH1v#&kFGsh-$Xp#Rpm3yJ@-tB)=DE<(pJlrk$$lk@t~z_l+`|O4-@I;^|;%UlVd4;
zYHfP8HA9W=o2P;V@f;F_;i?-l(U5enunKvEgXy(J3>Enc{)KQzGF{+F*wYtc5<T3F
zhH>dDpvFzRhel+crj1z5Pu)pc;pbSJPiY)5?LSU2k+*wt4)`xp5uQU%>Pr)1eD^xk
z@;AT)!ZQArU+S?lqtW3A;KMi=9TAc>-FixXIA_3uS6FRH-hd^737Vwq)(_5F&SJ-A
zkdZyQOKx>YA+?q$S?*`<70}oaFDWI04Bq1A<X3w@!_<tefTSb*iv2Pdb#^gBdUbfS
zm`lKI_Zuay-$lzWRU6x0UKdJsVFe_z%)~9#gn@BjY-?s<T*U&3`8p*0@HipN#x}RJ
z^+gYRg?n+4T;q=$uS0<?yPdUzB<QUqwkH8t0R=>dU;1aHt9e(dwp?tAOmez<^H<x%
zzwFpB1~QWbS&i9wki?4d?ctM8o~Mjx{7jQYKF!T@2b{6UVz{1{CN0aphj)daRz83$
zk``!J=;a+^EY;>5(5e89G@%J!ni}$}iWM4_me5Gblrfjd(q1|EC)HT9O{5Rl!p7(j
z`l*LV;9>@apZvr3lNHrnKB;8VC}Bpw)ZC0O7rM6^=?a<^9F59L7#<NT36<PJ`)XzQ
zT}C??eeaR-C7E5~pj^@!n;v;HXn>7$`C<E{yGptwD3F|JDlTOayiprWEUPPd%#?ts
zGEwdX69g0#Q&#|7O~w&XU)RQ;s4j0)?TEIHgULPV15(5{y~L?WHu~B2`{e~OB>z1!
zw0g}wyF3^~-<c=ooC`vC{cE-(T}WIGp<&6UROc7^{nrc_zx#xL6*6EID8gcj4|u#S
z{|>wXYx6is2!M&oR<IF)JkMWA8J~dJhO@c9Qu4gL(W`JAhLMaZM8Hz1g^!;t+l5Xq
zZINcM&2%3>j1bI+dHEE1FCynT{MKOHSf2Ye951%C<7f_J#@6nsuS%b_WbUxE;cpvt
z-a<#=fZj|B2S%s8dC)@Par`tk;|p`#*}07o%kz;M^-6`WLe5TFXoPQdW4%p{21K2i
zvT|Mng(#&0)LdFRWR5VrmgTQ4Ank7+Tqa|6;+f(q+eYRXI`JF3M(%=H{_(#Cd-+6o
z#z+PSbpouwYW!626bBL<LE*2-1;8WzT;jxo7l!0Y^?EsxtPuz}L#n{j>gEc00`4`U
zayDcnb;ZsUX>>kVk-D>7fG=uo21=n=Mvdb%=_a8g-6(O3m8;R-YXO!@cR2a2{2`q{
zk69<VG^4x0w1rp!tboF7N8vL+LB21avex}Nf0J*&GU2w~<U2uXj}8NM#KciMzl2Zj
zQF+bXCi7@8Rns+>m$m&f7d5E)R%h<rI>c@BOFX}v2N<Ab4``G~2c=-@KuLawSL|S@
zP~&zaiN};8D5%ZC_sV;(ao3smI4?(xL1tv(rq+)rJ^CKZ3Jwp<=ddh5*SZNyq7wo5
z@44Ph)D_+IS#?Y`V=#{i=G-N^EfdJ32n~1LtCY7Z>U<`;u<I4Cm||8(rrh$Uy>1R`
z>lsH%Mq$~~r(7%)sARP5PA^H))St1rq%#t0@v7Hp{}Y+STc%N;dmN9l{76FP%rRIe
zs*B`x#xFe&-JtSBhNfxFOB%+5mcq&I^2>d({^!(=FWH9jzsP_KdcC$w*P7u)Mf}j3
zZ6fEy;!?&WqVlUY?4(6-3j`7+4$Jr*v|ujnNYLPOy^!MX^5~g}p842b2%o#a+igeX
zE7nLSWdBGo4MD-fz<`1iH%OV;&41~TVX&dNMA=+sgAQ6fVbxkk3zA(zmx8{~ft-(S
z_@ey&(r}4;I!&X-g-muphwG^HewUpLV|dwPd$|Q%hnl@xMUv~moIr8Z?n%e4aWt1Z
z82};Ffv`ZlUApn4a_b9B_^f&TgI1@&*%RZ)n}~y_L_I8>0NUH1_+4SZ@@9bOT$$bu
zG>MB;hp1r(@htOZ7qV;g6A)&ly#twwehG@s!U~LX;fmc{8*sCe3f-JD;I?*0T~I(9
zN6VW)PdHA2z0y4fQ(I|*$N~?iHJbm8e|hq|$Mjz=k=aNbqoK{7E92IN6B@)=zD(ee
zZT%TWf#%gC1jA)-+^(J-Z=o*gOt50Eju4z3%8%*;QoNPoe1Bo5&IK~=$&FUc$tSAP
zI&NtIpE<ef1=G8OE7_asWknoTzG7qe$c$@PbOi6kQ_RWbF6v1{8H4VFDZ6H{qEbFR
zy_OGnk=FVp=fJXik?)vMp0E&`9X8`##`6~+gK5xM;X%sk8a-L=c%55%h%#x~)sxKG
z;vzt}ailt2CZc>KIr<rD0RpNh>`}Wd<&nnZPS?;V{D6CMOZ$Q_q`sIs8(a$8<T3KI
zsR!tG2er^lOCy+iW)*6Q`<n1{jjnPAia|<k<#mEkp{$QuXjho5Ab{MGl3VydfRvjx
zdRtx6Vt%Nok7k=Bca-(%e;7(F^Ez>6=nqi6BF!(<wCJ&pY~Rs{gmDUPZ6NUXN>UOz
zfh(j{DSM7E?z|(7qnHF{birX)SMZ-1#ogq0Zai5cz=1$iW?&?Ue22`TyF2G!6qe)G
zjE>!sh$X+Mq`1Ih>6?<<l5(fkxf*F*AKUL7PZfr%`plH@uPas??5XmgQlgX(Ib<5v
zm~x`OOp}c$$O?D^XnlA1l?>xPN!miNLmo)NGSr+KkcK(nevcLyi-k-sxyb;Xd>R)i
zZms@^@FGhyEK+gOIbNxXAtFzLvXsF$AH}txni!VQ$f8zeUI8hwbcIb?Bujpv9y8ux
zr9(u#*A?S|ue#wv<BDMvSIL`6maxUPbBobe83Qi4sv~34eVoiz&<9dG>G^vNtK}Eq
zxm43ocSc4~^hj0i0!$opZAjsl*SLyAGDc3{JoqQv!DnK&!yb^9Pd9QcBP9F^-oE{n
zf7K(s1D1JddE2HML|PuvA$gx9P+6$$-^(C5+vud>ZN;17c!Msw?rozU@rrfZDPk25
zjv3TeQiL0;|Ck_ciMobe`XWnp3%y2TQR_v6c}nc3!<4&qzCIOq-{TkeiVOgXTaI5e
zsLuevj&uPj%aJ`rBL)zD_tyL2k_H-<_$#xX=wWHw-6X&U{R{?pAtMwFub}zzZxXI0
z1P9JwCoifLr9r>dG1F+|Th1xPdmsEAe`r9eC7tr&Ku^)q9BDO)-dZE)n#a?-sIC^e
zb}Vu(ZpShUBxN3x%6;RM!#?Ub0B}fXBfe58qv52sU>0kSjI7nsR=0sa#nbeuN3(ec
zt@jNZ2!x!=ATXxA_P=HfBW)=82Bh^S=csonudVD(cZot`&!liy!+ZqM709`?7vzLM
z=5jwJtc{1W*aq7$RgeY(u<$%W4xP+~M5kJDwdRpbRP{&gOd~JJ1K2E^^@zs8Z{PmU
zzQnfT*v6`c+I4>Pj1ysm(PdC}5MU)LpHM9~n3OM9Xgqv{x&Fqp>Kc=&s48jP2yRK8
z!_;&SqCGc`)RBLf-NRlaRc4@oI9Eov)e0j-0KEb6Xm`^zEwNx6;?R+ZE1|!@iwKHZ
zPhadVLg0;9&1_&c<a<IMP34C0i_gE8sc8~HK>B6{#h~Mi^-jm?dKAo7%;{k^+qRRC
zs{7u~@9geT=v-ogYO~6nJeSbp9(=F@?Hb*uggD2;<z_6Vz^!`mf4NqA&5->S!{M3Y
zEjk*tB;`sOHNhk-(1$C_etmd@OhT6Nu1H49!lKdjjT9Q?gNiDM4^N_*2v7g@ugQS?
zo~wEE^_UBkimB;F>&_wunBH|3=bu(;UXk%mBlU$n`06{{_<oaDf>J;C;^!|xQ$Xj#
zc}c318}^Y;9P@#alO|w#KXX6;a&tb@f+<lFyoc}1EQeJWMo8pft$|G5L|Sl=v12_8
zJimmE*A^|F2@B=~e*YIv$t^s$UaUfB`s0sQ$1UEP(y+}*!fhv&&F&nDU0zV6;UO?a
zDB13~?rNi=5bWy=51|m)ojhQ8pBBiy3Y_h*&*tH5BLbcTi7Un><x2Xa71~zYi6-bK
z!4x@ZW$If(tr&}NgQT4o)hy99RUiM@=D6;}TkUL=m|QWWna+^&%DwlC|1qFUL%4MF
zH031^GK2n6v<8zjTZ=LaJGQ8^7!u63m2sqK?fz`VxTv(+f=w$h3BE}Q(1=qDU?e{5
zZ1g`T5f@fDl!OBT$^EJnS)#naiB8vz<60C@1F-G+qHr5|V}dB@yxy^FU)sD%bt7)I
zoirF_y+rXd9RVAOzJ-7G)6hlfUq{6!q-h)naCX^Q3Bbn{<Iui`L54P_z-X4e3c&v&
zjFm}~%_>u3xJ{4XGa^Kid?j5|GggueQNqp~MZBahTUP7#u`^NpTR2awIofU%C=5YH
zN%-s<YeAEiFT^0-N09!XGaSD$(ecHZm0=B*onvpVHhur#hlSc<6w)uHkpyhV4WrYY
z3?fM5JlOyq!V9)1Lr-@0cHGL<VMQ_>e_P&1tTBsu8(f39n#_5=2l%T&W;0lct(6y3
z5G;~>)m%1W5;tiH#DxoUl--Pu<|z@#PLV2(RWO7uFdn{K?YnfH=!7%NDLTQ_1}KsZ
z3%-}<5JckMcmJbnJzA>@+$pF%vbNmcj+a)ulSWt5(&PClye&bbTa@1}eGxkqUIFDZ
zoi?F&^z?{!wC7h5Ea_%WqnggJUyv-cQPPFF<r<mHvv>)n!+J3wCvNc{qabP{l7usB
zM$ihzG#S*0z(tyM>iziH&HCAf?k9uVByR#!^HKp5hBf@vip*%Kxy4n=DsJ>~OPc;Y
zb2=j!w&rg!yXxz#@*|i8EbHoU+gM8KS4mK!Wq$V=dSn`pj&{>qhd@7Hy@gl^H=-b1
z`bdc*-q8xk=i-!P;OkDvpqQBLYGpP#0>7Uy{9YoPz~hKP*!4-vjQRAV8N|jO+1U(_
z#I|6L-~ZJ@kL;m|dXBCK{GWFYE}O-!Z>E+upWd~0Rj}pHQAls&Y>GihA5kw-X_p#$
zJ+fYM_8XQ%IR(-h1SO)Ie=R%FNJ%%qV6n(y+mkm0X_`&M?PMB_IyNS-a*Ch@grGha
zc<C(?4sf$nafDsz@gTSratMm>Ox(a~^I-A!n(xPMWqjHyUF;OD8r$PfcH@QyBR@Xo
zDDDPZ%K5N8Ok`-q4$dZHMThRbcHR4u;Xw!(IJIT!q{qkw0fcOWsK3)<;8d@pc-EYd
z!G%%$!7@|#irx6K$qbR`IN?k0&MXVZCyCw*NO!QurmUwwK3~}+_0$>NgcKPp(v~te
zN}QLtoAD?A>3exZMj|aUWMFx1->NRY)S(Zm&4m~<LGm|lqxWNzne3S{R-a|M*S2kp
zH3V#?-hjYG*^9(n42-vE$EBf01~zUVF*?RTKy@WU&@`)1AW@ENF7$`6vX<2|$kMry
zOM0jQV_g}0z0S3Rsc#?0en3av%(mEAG*hU<KmET6XykM9R*b05*oSDDq0S#`+uG4Q
z?evhxc13S`Lm7L*$Q0dDJ^~pX$sX^=Lo=;v`!djnW+hWi?#yH+zVyr`@>H;Mxz|uC
zXniVcwC9jh4+h2KRH-a;U}hrNKpAd4`8ttJw68Tzc}+j~U>Rh@8%Lf96QUNv_W%Vb
z8uh^I!Xjy`YEsK>pz+5IldLZ_h}CL-Xfwb(8<fZ>cPl|w@nE@JdWu$uz;thNo|}rK
zNGv4s?(+?V*goyUpI6j7nM#{IOn+!r;tvf3jMRXsc8LTLmlmZNQ6U_w0vBx6du5P1
zqsAeoK490ev*;+BK`odJAz@O2F_-xwY8PWho}fyDy$p}iwr_qCV(vtdnaY{)BKX<x
zWt(hRrg*)&x6516X>0$s>)!XCh9EB2-1l_3EwE01-u(#6A?J8Zh7SQHp=}(g4m1Lu
zVNnCbf;AiEfJWJ4mWy6J^&v1`B^Zt+Ue)^hWD?bVhCMu2jkh%5aV2wB(D4dHmb}77
z>fZbA!A&8-Tyh{k(U4iJj>$Dv%}o7NmsIp#=Jv&!Z2DS;1Y+B$f7|<Vh0wCf<lplh
zt*b-jsJWmSy`^{yy=azi@&{F0OoBix)K}|RwTO~O+~}glu8=ga){L$5ya4bc3oBy9
zG?}gQ8nZ<ZEmB=NKG^RK_%9T$BzeVO{JvZz!-AUfssmac)*=|sr<@7E>K{`FV}@Ob
z5!+WXj8Y`>pH-o;(C6y4_GLpu!azg*_@+iu*m060=xU1|iMPTne_a5AJ(eA&d;^yB
zJkO)BG>}U#VS*~VfgxLSED5hu)%sAxk#l8U)wX1;#pe;G8^xY*lDn3(LWsjC&`WX9
zZ>2ws!AqeipFzk*k5BUr7dvL$a8|H2$pY-ecHr&(j+CrkfBZv=)^;X=gk&81%d2aU
zy94}0T*Y#N2;-cg{fOFdRj7~X*`iey&?-k%w%gop<DGe4#OC@lhwf}*0-IQW@=56-
zFc85|ANNmR1eXW?qfYAGCyU#dE2<k0S8e>nX?f)^`^^bf$Nw*B?*kskdEa-=E?4wO
zW*lGzGZVy*JUbjhFIOlnQi_W(X^kDOsNn>rB*u0aHqV)Y8D@<-v8^~gRo6B%vjgzm
z!SIh5)qxeaSuB_6Xb)i|+sUzsd!bNRUZbqyxV}_vb5CSONf4fUp=`Cs-nozO^BYjM
z)8_g-_jCmTATXGH=lA~pet&;nlG~T|0cX}HdMgZQ8QQDEtd#^Ob@~ciNofA`%_T-O
zS+}gItCE%3*Zm3Sc#VN1O+U!z=EwqM*ZkA^&}Ihv-><haY(-5BCD%nbDeg=H^spKT
zjr;4KmL>CI9Bv_144na64_8Ky*P?_XPu<!e*@VS)rNjj7A~x@jUi^Nz&Iq?j@%2;}
z4-gH|pS34ebv<)euVpmmuYp9O;?g~@=!O}ALvrL`QSf>?DS34%b4j}dij%EmVKebJ
z^`^#sZx4}iNw!eVj_shd1WwjHAiIq`vHRktp^tMchd9FFHu|Q0xUAckW$GZK$eD}8
z-zmh-{m<xa;R&3LU1U;!VLzs^E^4!%so8XO-AlJJLj=Z3eGQw0bq3SfzxV)$I#RAu
z@#eslg4N6Qy@O2Z1|)O;Qo+STor)hUuKO{)NKm~<pvG{Hg_T3(vj8Dhhq1RtDu6ZT
zB&%w|6E<g4aVEz2u4UIj>Rf;t=1|Y1_-N!V5LQGGC3or9ahpj<j?$7&G0xpM6(0yr
zJAFj^E{A2Wp=x8@-hqlW7b$muhokv?-@HX_C8sJ<3r`8nY#k5#a*DK)>Zst@6=%B1
ze0wl9fGOX{BaF+6tRi|1(8L=Iya6j2lB=Q?-watcfQht*bEp=;@5&fu=mfS4B$4il
zHISGG-xZ4%<M)$kSb{0q%sT?2#+Ix&K`bS*xqpLZl?_0p#pXHj!o<TotVh96uUP*I
zAh%w!h%3PvRy;r!cV%r>`x~!iGOdIp93G}m845ZBu!EVmwj2QE(atV7A8ANV(!rwj
zGjxHdI$4B_p4#pK0{A%xIk<YYi6Ozzq$c`;+|ax35C@1_BN(Ii07o=XwTIXrs`nNc
z4mI?<Su)I~bQ_bP7eB@LKlYg2ctUBJ3)1`0{_)<uaOcXQ8@=l{`s)P28}y%iq(FnX
zw1YJ%_(FU)qdQCFUbcI24@^S2VCsgnT!4>2+uF7|;Sr5*4~<s{*L!jOZEIi>I8_)1
zGY(;g_f%z|cF9IEaldxq;W^{G?-ex_-^l$rl2YEr(0?8on$p>@s0L_7U@42W1Nc^W
zOT8y%gG&$lUHTt^a#m&IUiM!?CF1u`^FaG0v-8S!T*idV1}GDsC@dZ1=ryv0{*XP!
zy(voESq2Ioh~crL(o0g_?5zz`O?QZBVb)6q$S;ZF6S3PSWgNBEQ}eqnp2XtfE#}t@
zVryw5JDms<m|3oYUgc2I=v+h}$^K5<t^sXddT>98NPTiOPWv+fslt;P<V|1#l7*-h
z5j$zvp$-OsBmsrO-r~X!af?j`Y2v@>t>K`{HFPz@x(=+672X}7ToZ=bIVr{wyOi{a
z32-y9AnM!;mEzP4nQ7XsRsGrVl?J}bEY1AtGPuS1%YL?`=Y<ucSK-Qe|4D18-u;U1
z)nr5l1J@s-3<Zm@F}QwXRj2wR8LExLOr-=(I0+$9Md*P;0r%n!<Wlu0>rj(uRw#(J
zAT>`oVO00yY&MRDeQ&rntmi&9W`nIk{|Xy(wDkP<QS}9#DKKKFs^uU84=QTM-31a{
zYw?iY-4>KW{cP%|^*BCZB+W$~cA0ugxaWPW0<VANayq%t*WOxM2~1XbyD9Y*8Ju<o
z%*O~R&uj)@s{PmIv^$}*)u9(C6Jubdcx)tuq$GbTi0<%%?eI$KB=F=~h$;crhO)+Q
zeEKasRLLe#Wx@;(J~sYOJlkD3n+GIKK&P04)+dld{dbi5k`-lCZw<+H3(GT$W;Z$&
z>|!N#2Fj&N<|E0G;mep40jt|v0TO#=Fp;AvPI3QaeSt!f7;VZfCz(kCP0^qsI<=Uk
zzyH|yC66KAD}s&r8*WDS%FfXpMJnL!-w?FA7A-SI0c3&to0aPEUQ^M<+h@??#_Ia3
zn&y5?Y=j<dn@jD(7I=h-6W^;+cv@e6yk(c?R<g9`i{;`#u+RHfhF~X4tQQZL*KLm&
z?<ZdI4DeOQ=?&2&pu89j3Ucs%SiFJ8Llzwb^T5Q)&&<Uuv%yL)=+yze`qu)TObWxW
z#i;Vn49Ou%=usmQ<cvC?p97bE_;|0-l&gE|t8pA4LqT&>1W&pHUe$X(jO2le@4^58
z7G3<w<M&>a-1~~!-01sQ8RmH$(bBLE9DuTrR3WMYyMZIYqG-#}c<*aqd&JGDR(g-F
z?ZH9cR~0(kjVM)*FE;`X`I=i<p>>feu7s(bx4n7eUDxkqAT{JJ(b|v0i3?VYX&|KN
zq1y;tHATKmBis}L0>TEPX&*Lm=GRox5%!>%>Ns=97bvvY+*tKBZr);H45;lRrr9d6
zEqHm+A!zbxJDZrLGc&H^^a>70I2s~*Bw>j^aLsL~-9O~jk$czaP1N(3iL*H#20D`&
z5Xt+Cuf46%+)$e0;kf2p^qz|PAF8{UrGyO)GW^?f2^xSt2A~us5w?GX0*=i2xXQ_j
zgQlRs-Fqj<MC;9g)@tatr~LLi5F*{V?Ni`auZgvD@F>Jt-acTf>7T&~im8w>LDulH
z_mf}6IzKgk@3PxH736z|b<)o<o`=Co`3SFna7S1q<ee@hvZRPE?XIuP&T@oAZ*7gG
z=Ah}GKC8(XTjP4q;a1e)fCWyrR*SnVfjj#jIPTJi3_@^YFc4#dQ3(1;Kq2B*SD&b2
zKCaLnMmiQ>kiBNXxz24Y0yq`USPB&ih#HDX&X7K>w;x}ANcn1ZV-OHAt<LCzx`-e=
z|4YC07O61d{qb6NF}(wmzyefjkZ*`fMG8nih(}{e<q^Jl=SP6wrEy@B!fyg;dcQ91
z_Ruq@a3=ElD&Bd29qA)5?I2h-J|p<VnhMc{vkr+G2a4o#AdM&iF7=4#t(2LJ*xgzr
zXEW7E7rlSHK-XTPVUEa^T81vj8oH%e^AG(qiZ!foxkgLf#a+nIrJoV`2o_fB-Iq6H
zkk98R*OGalFtYvJQv1%G^q}R=#1)I9GGK|L<CvzES-jJFPdW$kgfg1X`K!oXTOvKm
z!L}$37XOOgFKZ{q74R2{)4SaB;7>yurRWatj$Zig!WnS**ii)rPKOZ5xd63+4#mAg
z28sKB^-rYE1T#%5PwxTX2PUuXt_DfcORm>16M<Yq+n#_y&=%3AW`^mjQLV;2Y-II;
z{ha9xT0yd{zTyn)h523dBlv#-r%mC|^CFRi<E9`v=%wog1F%<md;<ZtH_#Xg#-po5
z*n$o|+=h!)>Uxe>9Ng$&5X`Y)QeRT?XN!tv&A<2QZ88P9%dxsd$jn@$ng)P7=uv3v
zrF($}H(t{;CHik@79J(wXst*lwI$W@$D^>_8=V@z#8^vr!d-a@?;Jnp8aktSWO!&(
zZ(`ZwwiZ1{K#fmdhiE;pE|%UO)RSa&9mF`HpgN|ihbeR7=|szgQ~#myOT_?8cWyN&
z0PqP~yjXi;u;CO2KR&!oJPZzOj~(Q;-am*8gNn0sHMpDxQf@(V%TI~!)uv`8ZD1@x
zh@J;|E4BP_tXuC?y&u=}**Ox1dJ^E@ghkHqn8F^+5~b$3YSzp0K!wqsB~z110Rp}b
zwjyTXTOJ0=qr!X+e-;l<#cmFreU35HxN&gC&0qQH+x~_4=5gDJdpo-#g<L&IZ&dWg
z$t*gT?4a@pOSssfk|)WYR$&~s;~o|0p!Zl~*VP%YT=4bm>l(v@VqDlnDPXVer*eu^
zpEB@{XQ3_){;SvUaQH|QbRx?r+>07U6~#!cD#?A%*r0U>Js;%jX+?OL$6>AC{3F<c
z{i>JAP>s76cRwYP1Y_p)yJEKMqz*nmEF8x+Ml~{`({cTRQpN$ml{sMQ+2KZSlQ3eK
zt`g=qNp*CVbf;KnB9%sB6Dd1&R~RTWxk85h8d_ol@DF^@jPdJu*|kfJ@dZgDvFRJQ
z6vH%c+Le?Ck>|bnn~%v=5^AwdP#TXYe<GN0&Q1<=Fxl4;Aq-*J5SCqBN~Y;yH>3LP
z;Y{_uX9JG%F-X#cy4M*GT_%&ev2fIS6v=wh<<OH`bDeKH@yZ}w*#JeQP%)WI*i<}B
zJWy;3{{i3<pn*f_`e3~~!?Vl`VN?)$S?j}(fCw5O<Yh9zUbqF>0Z|XsfNrppdM*1r
zx(xpdQ4y~5%><u-%nIlsr48#vT$rv7hcMyGJdmJ1rc7-B$}VHpxTB=5yh0<Sy$mmZ
z2*a)i;@qOcBr<i1|HwNBfO`}1US=^7>}l=!T(iZa>c>pMAq?4fynNS@4tNi-i@9O4
zcGh2Pp3xgbMH1P6O@GOv7(G%67@)(|cNiG?`ed@Qrg`BQpvdLj<%y(^=ybeS*|aC)
zPYNrG?#y^5Ru{)O4gy*(3ko7cFV-pvu308*WIaq8NFnlM6!#=93cv9;-UV_=VxPGd
zWW>6-)1bV)wRGUkqJ!37BD)=2!8Nn=bC%?2r->tHW2a5pibd4>a5Hm1IT6T&`H$#B
zTJ1pA=xg8V2v}k$onYMJr%R_K`Z&vWV18GVkXVS0XL;*l^IH&q!cnt?+?zKhlN=On
zeT|Km_$~a(-`gQ<ic5++ivjC51tIY2ch&oPqoSF79-YfbP7yqcgA)So?4<*b%Yi5l
z36+xm*}>{dP%5Qym9C-Bp-h)_gf8Pn8BC`PsEQ)RuUT2w1IFzGIPhW<uwTfr?7XZL
zgVA$m`Lv4VTHlx?bGj~Iu?XDFAKqWEXjnw8%+IRK%5L`9__NS`E&Z_}Ks!dW(*o9g
zQtQ&llzN`7UGN+xQqa;LJ3~?^StiA08Ae$=2>=ywaku)&3_}*lu|TO_UGsg8f~58Y
z`DK}iQ6WX_JP!<iIxGF_o3n-0mZD(sgp0`McYpW}Q4R7mVR@E%;FXE`!fJoen<3lQ
zpGk;=QK06$pd2ISJTVWR7sCiC{#fyRhiE1(;=<ujQbGluF4CkkG%2Qa78VV~>8jYk
zkvDqrT#>fGsSR=+Bb~TY1vz<c^7gP?z3)03y*R*+gEKZzwjy$v1;hBAoh%i(bCy{x
zKCqe-owv}#J%c|ri2!m_=k%tQl>DNe_GLHKUL_}5C{ex(_%4G%y&vd6wY221q`wTD
zgS#^pL<%9D9>Pz^gREb#4;D67QT70{03K+kf@HUs%hLy_FmjD)YtT=I0t4Vv;?v6A
zjCX#vEL@6S=8j}U;n72cf0qY)VW$nX32|^jM3-7IYKOTRfHw+q(3IqQ9^?Ul!{Q}8
zmt2*RwL-G-SPTizBE#UKIs6qgRF1p_X!BL<TuiLM`+t|FuG6YR*i0O-)n>>wXcLT*
zSf!skCns+a;EeAQn>gO?eQ2)#!-%qryEGRMj--kDdiK-0qufnBlmiYoiG-r@&ypLY
z;9xxIkK#7X_1ACYH}D7J0{DRT1U67&!7ua_swzSVFz|39S-HeRF5y1$ICRm`eV|N`
zK%>{LVEO$)Op#FivL396c0xVR1buWLw}Yr3J@mFM4iGvy$pY%M-=AZy5e{@5P)>$;
zEa|NpmRE66ilc0ej)OLJ?v;XpQ$T1`J|6-bL{4anigB%IAeGt;MUqQ`WB3GRx^ilc
zpYFg(%21`~UD1>B>AR#&2<Z+%Tq4&d{JIVYgvgZK5Jce}a{4FESy?8Pa6j%k;SJFN
z>4xO3PA17>Mj5QXq*H*-M|FEPMnCo*7iA8H*_&Xj$qh)Gy86oSb3W%$YUvY%x^2IZ
zE$sf@V(v$ws9>`}EK)VIF=;|rTj#=tTS}ni;J_WCId>&Z2Zx6Esw6tG=&2ZfuKFeG
zEyApXpEQM+gZ?R1Cn=GqEr&#k{yd>fN-VXh)fN3>(Z|8!fs-YE!1DslKnrzQujc*z
zvwo7b5*ffXB!7rkz2)-3Uyd<rGsF*9HA_iItocJWSmPeDgo0t^eifvuC-vJwZ(~DR
zw%ts!!-CY9aKIWTi<d;Xfd@iX&@4JmfXjN<Hg-He<P>J@`&-igq{ikuSygmQS)l;I
zT@J0KmtQtgin9DCiLiJi-_Nxmx5cZ?Jy|4@<pt*28WDi&BGYe5{+lY*5!-lD^nO0b
zo8CrFF^=rI{BNk=Se2bOFwFHB<-{x^!p%YMYye^T6lkK%Wrcbnmqs5V54fvWQ{CC8
zL_Q`aRu+1sN$}3j4$18Jc>L^lW(wy)LiWeTjQ7wHL5>5DOS&qcOwdn=|4mr{%2EEq
zF@lGC@dhbGE&=D+;dv4c+TuX{)=#iTvA5)%sS2soSAaBJB!3{fbhyCeD^w_Q*J;VI
ziblKKri^^6=Qe;?t7q$%Ukaoo5GnQKK!^yZoZfMClS9XhaPi5OKV-5CR|!_bb?~LI
z9PfWyKcPhDoCOCgg=BJZH)1ZSfhZjOU;Ep##xfo|1Y%NQ)j=&^AM_k3K0J|~0|VC`
za?V<RO@!U@Erj^IxUXv51@A0}<vcaLwT(QXt1CI3iT#{^5*G%|#4}``Z=wc#0Q+*C
zs>A^<(FU<+60pcEr??;`ar!|{>pR$z97KJPI^0s5_9V-cpy|v1^lk8@Y!0q70~<N=
zaMvu=qsgp;$DUmsM!^)OyCb5@o=<5U=QC==GVR{3qeo>BH?f-dY$++o>`<Oa+vir%
zyE(zAW$w$Ci{rA;pVf6Lz9Ht!n&)XW(iYFLOffXICysI;BD*+ygUK=&F1_KJ0fHmQ
zuJO)qim4ZRI_22_U&QI3+SJYsFvFnluN?tmL1xH`Wi8y`d0IHnaU~^|moPFwSQD31
z7-A?1$LuwYbYqp&R?uI#By@<|6T~1AL+6TxX&kJ?EvWQey@|K(@JKB=_&YP#h(ieW
zaR5cNl32p8$E_iYAP!y+m<zrv*VW4P0UeeS{IpMIi$cWoiWYn`f!`92%n|a)$Dui#
zyFR?+Pb-lc>_&`JP4ybRhd3E!I1@ck_{+&)<;X_DMZU0Hv4AbnQFCZuDZc5SqCj?T
z6(!_SH5zQ)j*(xhGNcTLUKAELUFd;fp6agT>17}2V0c8w{+cW@%a=&;Kc+jS>?bs&
zSLor1*;&uN3mkChpY^l#A=JjQlk&=hhl`hKmqi6RE_x%5#jxXluCm!C;QMzXB$05u
z&xxLL<Zgj$3K7wiBHw@GJ#y~5CHf4r5~Fk-hg%SJ1kjr73iW_evmq%$K~3o)qYujP
zA)=56Qo0MgE$&y6C6h{=8vJ8ZW*-;jUgFQlRbo<`8=7*TjbfEM;7POw$_m{g)MTTv
zeh{1(Y2kA4m+#1BPrM*?YK3ltoP<3|A{YYb_x1EFTaNREv-Dbq|MMh+D=BL@W8qTZ
zi(0C*-#<_p7yFm#6_iY(*C;C2?FS_~CNT%+Co)e@<~XUA-<<`K^6NX8WksY!#TPM<
z?rOSD3FL_=wpJ_)fbIBL%j^B(t{ZqE%H?*DjwOF%-!BxA5;tWY@2*~>?k)r5Ax?3+
zLogK}%f;qdN-bZ}R{*7#@$M3PHf~FSg@;9CbGaD-2n4>y#B_$1!30}qr8sw2S+U`8
zA+>UDQ10qM-^WzClVXihxc<5C#!8A%1*d(sK8WkRjWlB;NHL=u-~<U%zwr<Mm57v4
zAP;iCda`{^rDrE|&>3mciizoSd<*j|Oqjr_k7*~eV;blIksL?&)&f}nHO<heb%suX
zvhzPTEJkA~pJqddx>+9#ZvZ?A?l2Qbxgzo;v_d+Bto1mNL~9>cVGvLx0$v>?8SE_R
zi1D63ehV6uI9WKL-oyG&P?^zNNqaoUMsiK3pYVw-B)KLzM5_9jzcSy7r3b@t%Kof}
zUxj-Il5{y>wQDg5Bm<wM9cC;3+zOXDAx(gi?MUv*tnVWYkT|6imW?$aEP_+0aMnCg
zMhT!PNDk-MhxFJ432Ws_uIWC^n$e@^F<=TPN{t?_AT92_0EfkVnXo=J6JQdY;A5KE
z1h2+bRXPw8`qw4=b#rmg*1U}=DYL~7`yMYOBURY-SQm0L3xno!dFHL*j7&1wL23OR
z+lgw%q4Vm!mx3M-eJ!n|(lNFbE*Zw@x62|~p|B{A+zht2S{s8w$n5$By*@lA>PDP8
z2F0Ks&1vnaZS-MbK1HNAl@h}6Tk55Bs-Po(a2t3a3`FnsoR)AX;!UMYK|$&XG=IhG
zyRIjXK{&s1sJ^%7406oIFzq*qMKDTo)w@1h^av0n$}JaGFr4TqcAkAnhGz-r&d6X@
zIh3OFoMu+(k`<ky#*51V(J_lX@r0Z#Uw}w>zeVfK!Vt^E+7KFUT6VZK>c=UZtBraO
z6`0`^z^C}3vRIK5VN_Vv<DRnIV8u&G9mCD26|^s^UzTe;GLT`KT~So>2MGnTM4@K~
z>W1j&{>)l7<)1~Gu#3_R_$aXFqbMr_`ir)dkL%o(#O}4B?{An`KF|W1geXcaG!R^e
zQY}9BhjY9=5{)I#Bw_r$t`jl6_@F4t-e#R*du@K_ZpO_Y{nrJD3QE#*Y<3`s7Y3_R
zXaE<T@rQ>boIk_*+L(F<$(0UxmfE)8Zuf9<D0S+p0RVw78!lP3DgGA|h2GuzD9CU4
zev328a#W~zY<z}c%<t?x9%#=)|JVD3CK=uz$KHrmC>;5l**9f{P|(4-d%WJ?J(rLT
z37oXP!hJxx7luQol4_i$Y3e0S{1KUbd7VQnfktX}1QT`Rxq5z9i1`uRIYJFCMvrAJ
z98nNig{zD|vNAyyJLlsXftN^pEW%gprr0MTJKN%r-01h_^7@U!qen-BG>T@xmj29b
zQ4-kz4_5RH1mN;{>fn%YmZ{FZj^~t1ifSo7D;VC1_zcU$wIroC3w!omC5~mbA#uks
zo%x&EH?u7UO_E3$v|@O($opiEGGkAWTeOXqsP{W6bUUO(d7wg_o&+1hMxiNQKVmd>
z2MRQda012P_f8VNlS|_$%mL_Xt`FVPK+;*lmb06(=LsvECn2V6*X6yvRN8kqq=}-I
z*Ah-h;)#yw1+5@}T{a9JV-`})4YI+?OB-l!vK|or_O^>PDCB{X6KKgQ+}ZT<p*4@t
z15bkR%`Wbw{^+Mmh4_f3$KFC3G#E;@o?c#y)BbwEI`Qz(4v0OQ8bwHuA_3cb$m3uz
z3};ZU16-<)WF9U-l5N7sdg0B0_%sKT6BcqAw9L=ilhT_Yg@edAf_9sjvOZS1f($!x
zy{@$axx)cWRk6sMH$G8Fj~zL+*sb`)!gIaZJe{1>*<?%0kOsYoG@OQ*sc(wG#t|r!
z(Q<be0zQl})~hocuO-*~>?0^q`iOPgGywS8><@&(MaIjTqqQ2*ZpyV8$1jO~hupVS
z5k(CXbD{~Z_i#l5d6aO{ge4%3ar2jltWj_~Hv2<Q^=nU+>84q6QkpzheQ=m8Sf!ih
z99+5dye>V;gRzHI!VMr3Z<vzE@rNWSSztx1<n7X3k(x-*8t9DqU%)i2Vj(FNOOqY4
zI$?(`nPE2F(c`^`B_>)MP?yDHC_1l#3c3IX&@f*8=^bL!37Q!`Jh8m{sRcX$q`MB1
zFP_IIhFW?Eq@kcAT~fMKK+5RW1O11O9`%f2*WZx96+PWN;x81%Y?4nX%-V=5ZxvH`
zU5D96*9*@B35VOnO(Owq6dtHJb%bu!<IaN9yY38DUZx0-A}5z63L!})yeO2!-*UR1
zBf~ReDwc=7sI#GWF8PGs#EFA>I;OOK&YNwi6D%7?y{8C@iXaa)vF_u`UxQ)EecZ0P
zgDn{Swxxq4CR)p5-G%5|gye>AZZs|-l8py*YHro7gX2-C$y4wIg=I2+_eUxFL8u*y
zwNWXQ@HTm>m#(V;c|>*@3yBLSC-i8(!EGbYwI;^_???5!Pzwz$x}q2xA#=4*lc;f-
zk^_v`=5RjSt*}jbn)cXloVcRwNMjWVHonV^A}%Wva}rt75}E<XLqoBN-+p7eV2D(p
z%UplTGxxQ^<t7fX)4xpipsT5_eT8^q*v5nn_0omx<4d<Jj5uc>lBbQR0pHcz8C)!k
zc`mp0yq7jJISC9NY{^qWScWgOoic01jDsRg#B;)L9;u^B%#i$!O#Um1%5A1M;yuwX
zbqIi3CB1CJv{z^Rz_b-KVz2+!zcwg#reL1hVMb!bmzwqMxCje3VrMW+C-dZppJ8+q
zgu=MBe@Yv4{B}NL@fTK5b1UR3^Nl$HT`0MF+0U9q{(B0o05y<u86NDeP#Ga}{NP>;
z&jx`oMv~KlSR>_fk~3tS((>3Wr|vEchQt@Z@@qyBJqb;J<!#b3QKGlxVvX+E`tpaE
zTgP!3&O}e?0H1(zt1Eh4e@wQM=Bhu}>hE%j{9~H&ZbMb&;No2zVzo<x@m@bDx&_>i
zBoI|nT|^t&FJ2<=0CR=LL}#WD3)Bmt$9w10duFl7EDgF$rbxjD%Wpp#mNnh~n)Oaf
z!WJ|MMrAnj4O(HKX-M+gF4yM?o_n+Pm4pF5lv%~WB<~4*&S`T||6~2hS9AjoKt#eC
z18IHV@Vd!R%*yKeOOhCuIYaY4PX;NFDLHV*F52klB!wW55@cl!74UXjW-?WoThZGW
zvh~MW%1(NH?uM_q<^`zKBFMP;v;PzMVxc}AZ;G06>PBaot<tpdJ67`C$C!Hn8?Pn!
znwZI3+Pbjx><boE<1ec5ujpT9oN144z>*lDNq2A--ut@#Ly9K8s<A{18cPI|;&~JY
z6qmsf=X$T<d2l@_LsB6kOZRjrA}F|2(Kb|aEQMVib_?&|8fXb-D8^X9qwhNPR-k!W
zy{RLhXOU8`AR>%+x@4r(Ky3Q+EENhN{*v?9gM-$YH>FfDPTK7nv)kBU#C~pNFAxS3
z;n7}1L@`=rYhvOn8ea-K+(P|OwuRE^XJk5N){3o1If_J4T0#*YWvCQt9zAvpZ7*Se
zk>qx9=R}8!k7PXZ2XBR6;gz;bX=z`4eEiZ62jbGzozz4*)9wC@CNC#@I?wn|O%>(n
z>1c5@p>Jpx4dPT)j4vOgm?#^xh+(or;wnw~QiO?WTY}GVK80m*StRrnyX?h-)l}4l
zAhp;k6#uvxe=o;UBRyWhMrC<xz)jf-kLz)*&}=t1)(W1brC#V<_JiF~&!vPwZbePN
z8YOhR`xR<iusWT*)Bco25h!B_sgPsZW8;``0%Cik-aE8Gll;b%FhIO8L<t+oRdq(m
zp&4|o^u-^U!<^?yj4lY!+sce%+<B`0zQep!mtA@+SVjvTBCE98rKW^?LR=U})a<z*
zeT&SNp>&lpK}RYDorTjC?z=WOsK@DQ!p!Q<=i$N(8lU6zuuc8K61!)ei1tztJKDXw
zp3KjSB9&SdZw;V=qY9*!fW)U+sMw5Vdi0^B-Q~KzyBSDV3FoiL)JbEh%JE^}Vc)9H
z{e&Gne{B<4%ux)9OOvO8)T)nuU8XX#;F26TDlLUUw4J7o;ancvFozqPGOInfg5h7%
zon;b1%m)Npl0RS`9E2^5;12jJdvdtR8NR@xsikhmpz{oO#Q6aZ2X7QTT+ahGmJdx7
zD0m_V;>k**<r=zn>b9<hv_ws5EVt!CwL>hd0FUqTh<#BF7KdhVs3M<t9a#QF#^Nok
z^ai<iJ=JcWEzXcHhPG|~C(~4W(o!#2`>gR%YYOwn){Gs$^e|Ruj>vsLMpl{~ST!+G
z3Iid1h~^p9X4y~!fje2qTyrBI4t?>lSaqTPnRNU;N>|SD;}IdW+uy8{7a00ToPcb?
z6~DG;8^bFixB|!WA_r(d>7#SCWzU&4f*d8N0~+RtolYiFi$)$7!!~6x&V&+PVdCHt
z<SRbtj#usu368jTa#eCSh}@G3P+dlDfXnb;h1-gQ9j|$7czOojEhm#~m2;thtK%1c
z;`k*_)ge%6&gGL`_{>1>L4rb0+<gD)*6>dmDoiIW>pj5nRQFyYPFz{JF_^1^QMzBp
zU8uCbuGJ8hT3))x;wW4`6{9Q}Kz)46%?>I8B@~`^fBlFCnpvW!WW;1-7gc$&Je13$
z&GlbPQSSZqA!-Qe^AK*cIHH8Ys9no!2K8C^(3jr-RPW>*;mbk{iYrxAVvZ7Si%zDf
za`bIBf@jw*%I@vof1vMGIquADsf`{85jfSSeQHo;C>I)QYUx>cBC#1|Yr=*e)4`;v
zHwjEku|LGjAcT^E(%40cqVT(=iIx|90gnoVp5!;EF69|Xus{cRgV`n=vcyG<PMs}o
zNwz4U>pxBtU;;4bB6ouK@agZjse(gUP*S;Xy!i0OPbbcTKo#*uzD{MvAL>mpT#~LI
z-(;ZQPV-ecYEUZI<V;G@wee63kbTYfBc4m51OYT8H9+?|ih@Yyq~GE>(sTl5Ght&X
zQKUAJ8WEg-be}^WjG(aP1F5!p^~-{c4}BjND}2ZM_V9l6^RQO58V!sTo<@ngJsxfl
zZ>?Ti8zDj3(g_XrpKPIa+xzeukT#0^i4mMI%YA>S*RU3wG)+QFfn2xFo)!&;Yoog2
zR~mJ9urbI)91?GfbuUPxv2#(nqnGz_^sajp6u@B){D25auc3lS{34TVe)x?)`xY)Z
zep|V^pA9(PzZXY*r9WU2!iM5gdq-H5I(2d!mlM&6sLe?V(j$X@!klaX-w(IIED5Yx
z@mXwyxC-Kg<JyyeDgzVrZ%`YEGFX-NU7Q~%Y_p9eV?XC()Jn7H#X&wp5V7jR#%KZl
zC(^p_Eg@=?LR1xA+@<_uRV3A`D{=aE#2cG<iGk=X6u?qDUt-`6RZiTrUW<}MHX13x
zO>#+ft1<Q%$j27G6aq>ec!Zf^_r&1V(QcEK4QROLZH+AFT+mb+v*b8>nZEVpf#lNT
zg`2Rlkk5*d@r)QJO@t`?#^S%F7rDeL8K@{O%25wdW2{||L8AJ#>`82GW>QdEY&wS=
zvblV+Oxy!3!Y9O8$Nv;hO0(uq40$Sc{7D&}dmEWz2g^ptFDphkVBJ^(q=<kD#R8`F
z9L&Ri^u6tB?`r>(hl5MC0s_+D0J#=QtQ8;?Wc^itYpvvFWmK37lHJQq&#6y3gAJ(v
z5sg=S`-lsPv!ADVo@4`E3^=t>zj2JF)|0`?$qh}R!I~FPKn-w!HF#C~yvRx<+?VAp
zByLY^2Kavca)$Xz3eIEyQ`!q7YBy^IWobzmzf_wmFrW=xFK#MP1Gf|h_vXrPOW!(|
zk1{%!8EXzRnB1qf!~C1+pf|grvsQ+eT4Y9`?{j+5$|OFIqzI(@cJC<M#qop%;7D2u
z6ez=$VF;GMlXwWirVeq9%VlIFW>8H2&<`dPM1)5FV!)wTd`9$9Jss@2Bp2SkAL^-z
zUy0X60oVJtp`1#gXi`3QMZ1!FYe|J(saA@Elzv^e=)+pfBw-p0h@KQ2dqyUjnO4<*
zs{g*HU_-a(#q0&Rr$4k!>Pw^awsSy^ipU#2Xx+B4l~$a-4R}Q|S!mIGsVnw%nVqK^
zyG7ppIM#I{p3rg;RUZXK5&J({ppLghxiU6_=7R^AJ{!;n<+@3a;vfe_mMX+0k(CM>
zw5ZcBX-?-(qG~ik<WyyNfS6ajL~Oj!tLWDBUov$xLedSQLQ;4@IYenL%mM@A$pyF$
zf_$v6X&u&{TVhDP6d%iEAOgWL&bx2U;fOQty|}4_LhcT22z7sV<}M+wbSgmIUGVLb
z)v2StOhmeztf5#a%-96sBU<1a*fx<VeoS5}n6@bst@};p&eUB2#Ua<y_YhW;0mKFB
zi?Ne@$fey)@dLsPZL}0GrJ#^vQ_-X(S+HcMz_9Ac-gx5n{kE#DjKBSYT?!>>E^`-w
z=#LXG*Gc>h1}$*`<QU|0^breH+plOEc>l3(|0hf4Y2(XC9sNFKNAaciQO4nUb{}Vs
zs04%k%#a)vcHp!|eM$ZUGX=&B6ad6RRSoZvVvYhXW$}d)6+6@gED<I55ZT0uiOO6r
zee;G=o+vH=0`|mDVF3VHp)9Q{0IdcE_h{Jxl{!Gn`8AaK;`;p7K$yi(RonkYH}X+1
z%udN(Zh%O@wxX7Dk$+h)y=CYxO8_IBL&^??Y@)mPSUDNWKe;mHUz0mh+%oY)K$J=4
zAq2%$G#mFY{<!M=GfPd${;<+L&k?8Ek*stV9M(JN_+BX0fxUHtq~Y12)V|H58e61E
z8FIKFJzb5QNo-Tcj&lw)V%|?YQC7BoO(S4hisiR7>>0`eJ|hKSUGWDIaiXuRj#!y^
z3xwm+C{JlFu-}%)2xHGV{ba5e_vChcGHpN$Eb@&vLb}Lo7zRfysVyI(KDI{|ZBQ3o
zow?a0>>0=U!lFeJ(CMhkh|vfa3^$!1g=h|U6_erL@_jj@N?L&M%F$TGi-5`C(VZ|?
zH^j7UC``4+Z)Tw=At@Y=9o$-_mAZk-^|$~;!Q5J$`e1Yi@(W6Y!C?x}Ap+%Dc73kC
zvH?J()2}CL-Ctu<VrHkDwW<usrVO5)W)d!NhS4RICemY*AA}=uyk&VZiU}*|4QUDt
z`(BGBa7%$R*gXlc66i-rf}htdlv7ptjAW#Cc=gS@aSa57D%|J#wYL?<EJTYk(+dFP
zC`Tn3K({VV%<3>ua=61fNpUUtGeOZT<57wcB+Y-4eGwNYi80UU#O4v~gGS*OMSM8^
zMNbm=WeC&a#0W=7EYIr5D6mRaAOkPJz1zZkqU?jgckUKIR$VyGKl^|U=1&k70%om@
z(U$2s&Kw<xJ2VdYhzSjo<XH%5k5Yvo(*Q#vsiV{jPAZcS`DF4kYExRgir_^&CWx6N
zWF=&h7HnAW*Xwy2#{tN4&`($+q9V;w7XR7sa+&C2RrR_$W}9IHgamB_Xz}M|@##vK
z%l){4wdDt&>U&PT|EGiWE-EV4JTMEKktw#Wqc(9XfppQ7iCq$aPhOR@4;%KAmxo9E
ztcjRF!X+wCec!ylC^`lMb!U0aIlY!#i0jR8M;;cHNqI(0W3f#XA;c@+zSqWT(+`Dw
zEb(JMdZ%Zfl#{cY)9Yi+g-RCrO;Sf*GpmicNv&)vb=Uc(VMJfD#+sE2Cv>c+do`~r
zBXr42+@-abmJ%b2#-^w=HEb&3fznF8o!}*jB=|l*WrK{QUCwF=X1Ui`9Ft;@#fEW@
zztg<@zlN2>^Sx$LZ5Y+0xpRy=IEO1<BP`FD>;imn_^18oaLItZjKuZ?P`-ow_>PFe
zoNk0F3KdyXi@LC|EZ~6Q!w@C;m>``%@y_*lS(LW%3O^gU_5Oc4Qt<#%cN~2BnNaC+
zq@wdyy<~i#S@EVTSCil_R%h(25UNJ8<#asL2`gd6ve{^%s&)RDFK?4jnO-)6T7@@6
zTy)uxtRAnbQk>1u{!qlxL=Bcg9-`(ai67qj>TdbHywDJa!7u&kO4AtO7A%d&W4R%y
zBd;oHTeJA4YVcTFFMM`>V^};IFHr=%<cBv;y)1W&_~+K|44b<gHm7gj1Z7oRE7UBm
zl6kMJf*X6j+_ZRwC4OM@v)k_s3xDlx%|<j$sUv_gd9qz-wJJ3UhsP=hPd5F-&m<@O
znW<#vN!^4krd34O8Zjj5nGhLACaHKsB>BSl(o*~JsPi=LD*{0%#wGIdu&-g_PMQSz
z!Y&X24IENPg%0M=T~M59aT0(<hE_JJMxXqt;@RI^@_*OYn?G6fr2Lonm}Vio!s3mD
zOy7NdXD7b%quX?qf8T8UHVKbXCt+mxH8=UPUx}_Zr(LffPgh{4(XmRSX<3btBq}$k
z@QEs(<r~SgFGKFfx?^X_S=hDOa*e&$RYn;{ceHCYcbkj`Gf_9Tt12SbWioAHiPNfR
zQAx-Ft7+4^;25!@(xp`~RQ3L*p_&iJQIj><adel=kt!LDtL$JkX1r$8jErOOM?9iR
z<4(nI^Pog`h9>h}wJRter@|k|llg`i>9S9rsch#B!<aUGWh5hcgea7a=TE&AUTN2=
z-0{o4Yng{C%|_E`dJ9dn-55LBI9RDRdEnA{w}CD3;M{TodBdm{>4vzl20dxz5z~%J
zgx*BVwpxzlTmvMkc-b{)cT{3lUBr5nU9m<?^o-%X^RXSQ#)uA<?5a6!CEHZPXf%S7
zV>qhG^EXB&%gsicne@^oK?cHj-s;yFp7XS2E7@4f7-6oHWlX{F#N81;>dIbobK7YS
zc}Oet)R=CdCv`Y#8XxRz51SRCq+v9T6OkI()Ui3@mPV4e<w5IaSn`bKRm*F;iBm?X
z*brGRWvdp`F{32py&;rgq&23fhzdb%@J(2W!jjP`$*(NKw|1J){oDVb)bP1$XS8A@
z#{8IDavbCEcv3nTmlQ;vm`Tcy`V*Drc|ROQgC-t%A%l&ws&xf<A#f>tJQ^Wnw5h3A
zqp*<Ci<7XN@Se5^8)S46MO*xNi-Q10)R=0Rp$kA7dB*SjmR(6kkaV@~8Pl%W?ADse
z!RxWLG&W*(%C9zhs$osL;}z97>n6?n{k&}k(Xthvh+}IpibwLX%u}uCO8ZVb(#sLW
zeYo(@F}C8=sqLvn<{BKt;5cnvRiT=VRSTP1jp6EufvPcMdYn<y-o*g;GES@eo>$)D
zPn!rqnGG@zj_P)Ky|dp^6c(B1$Lf%Iy0Slf8_Lx56LhC~8tIreIdr&e><9mi4c;H3
zhpK$RuF3X<F+D@<=7b4fqSw*e!hu`*k;y9F&7b`N4%%os>QUblYE37lac<#Mo9sxa
zB9lF{C?D5Q+w?WQpBY9MEC5L(32Oy`!DwRc%^xfNcRJ<Rkvs7%8&TyiXo!kTJ0@Ll
z`u`EtJ6*ZzzBpas%~YAkg7xik!)Q9j$XLa=%1x}1lQG>fWmZ%b!5#5=BP%MbY-k=*
zrWgk;jO37}EBK4|=6t0pt_<n}-{Al1-?G<y!?;Is=UZ3c>lh>0LWg%?SNOXfhz#1;
z3KLW^mub2N3(`bsWb!RqU0#@mY2=wF=hj#GVNTM6MJ#0qZR6Yj;QJEMBX&8*UPdI@
z>T%haDf1JPKemd$<zcbth#9<l)xv+|0VH!`L?Hu#GbIlQY31E`u=_1OZAmrjL!PE<
zx4!cBZ~}LY0SK^)nZ~l1yr~VPrxP<Kdr6=hO|kWIr?MS8=GEczemNF6*MK3z(uE|H
zP2z1>HzX((qB(6Yg{39=e5Wix;tO*`m;K~-|M)G5=bu*zru#hg)QMsHxUS_mByhQ3
zL;9qx;&OaKW8<K!WA;>RueI2au8W@G{^*+fEhLXek#?I<``{AtQ!QJPmZn=Bh;+e#
zajSNxR*Ct`_~t+V;<T^43g#6ZgqNq}LpzG6w|ZP3hbBJ_>b1&H*E6l>w9Yzaw`%D6
zom%5n^BU&>xsH&tcw|V$i;YO+2P6C*T_;;D9)ub(&wcz(<Hb$|#>8Ur<CMo@+x<!$
zO-~^PWup;R>?wk|a#+C+=aOk?g=ygy)7W){xK#Y5*hYCTwr$J5;Ma1siPj%ZK1xk0
z?<+ei7H67UnBBNroi<@cA`*B;-VFV2g`|<V6AOl3ku5i^%0}{a>$UYv#V>F+V!Lwl
zXD=C?9O)R1!~0!l#jTnRJ@Jel@gG!8pcK)Z1_mi~c-JK!I>P0#@k0?AV~P8)8diTN
z4^?~@3e)p;j%=3ZDPr-Mromf`pkx8Q4E@t%=iXEHrjtWHe`;GNHIMfthxpJ}=J^L3
z2E1|@O3u3tb=bX2w(W%W7tBO0=rzm9(B?xFNn{Z_^HYoS&#>}_-H?UcevPmMox-VI
z>jVJ={wH(UkiF2X>YM-jzX{*%2eISHG|CyL7iY1#uo+)b`UYw*jZ^d5U5;~bR;Sn3
zkQjcRn%N-EHltpwGH2j-D2~3K5SFJsOOHF3t$!QWwjXymiGz+y25P6Hl*-({6eST>
zrnAS47Fx{5;AyF=qL32m!BQh8J>ri?*@t0|J)IBBDxXtEC)%T*J0{(u+UR_J>GdCd
z@p<>;Li<8<VyKLE{Pg7BWHD|g4-=|hj~N4zC+o>{EAI4a`QOyeUTeXfTT}0)moc7j
zXJd7u{SqMyCsL|jdI4N6+OC|y*^^7~irGPcMut}ONf^?ujS|0C;aXFCA0xV7p*OX<
zGt<m0BLG{va6gm4s6*FjRQvU3E?7(UyNAK8>tCFHrWwq}^9bIVvBuQIEB;h6{mSr4
z;&`w4Tc2~~JY>%Fs`n(Zs=t^V)Xv(QpJv+~D#bfoA)o4Bi=Kw4)ty%E@;z#4Ia)BY
z7nqKn5O3_X6o+9&VQtjpd*Q-DPQ!A<a8LOa_o_n229?Kkxo|m(y$+vVjrUpUgN+aV
z_3aP6ww}DCzEA-}`ogj1fsd<K9=hcwW1T0mZ@GQde`MxXzrSbu7yUGM;%@K2H$VO9
zRDH(!h2)JStA9hOFMPGBKC7Nc-q#HNG#XuAI22X$y>nhK8+>N}?ppt{I%w`qsMpXa
z3v)j2q^cB}^T#>^Kl%nL=0xo!^S(y3pv*5E(=#RkuDLjhj6~gCf?wR7$M=jb?pw(9
ziQ2g=*L%i5H}%Jezh_Kh^`JkRHq1q5K3_ln#%mqp;bhi%sB$1aI((?V?`D!bR7rks
zc&qO^(R=xR{uqGMQEiNWbL^Qjy54)>5&y}ACeN>|A8XRS_AlS@NHeQaJDGVWv^Q7g
z{v?Z&+5Lvve}RnQkbD#5WpeerX`JI}EI|BGzMj_T0VZBi=xNrg7L%&%d~_U7oU+03
z1`AHnT-~SRz+E1N@VE-!{=%cpBhC7s#z&hVXh*Z|183B~lodXi{5`ktBwrjp5)7P2
zXL`<~+Bxvev9WVn_4YmDztYT|`V+~wl4R~r<F8!1)m(S}rWI!I)17?Q=Lm}4=x}hB
znwPlugXAZlX0E3Rwh(^|EQ2E+9z~lkk7{;6g23saEP2{D>z*tb*oD=_-O+h-oYCiL
z{=hj-cd=`G@+Lmm7L9{9ZhXr)>`ut4A02k@hQg0fbNEI7y-B_LB>dvmkLrh3^GEf(
z?(O@%7dyH)`q2BD{O}9!YtH?a`bzT_D<6ZzLw_E;_eOoYrh05N&H9cE_2Z-^tnNG{
z1$qKk0UwITOKqGKWkP$<V)#2rx=s@Dc$)E=e0?1*8gI}nbl|g`7FZ)^ReiQ*CMT>{
zcUK<zMAQ8PTs~Dl+I-0EITV|mW~!-da;oNs+U8h{+)?bbqvEdfyoSt<wm(DVQuscd
zkf?~rrqsv3X|b1e4hNafXQyQ1Fz(Au%lc#vOU%On(L7@)*=WFP&WozaVi^pDzQ+J$
za`E&MOi+dK71hH4YaPZl6vMpku{QJ@Uwr?gfL2W@7!{OQbJsJvH_a-Q5v97!8euq=
z#@~SZAq}ej6`ij;NvbOIOWK>x*|2@%uMf3Te@vfF=raC&oGe*h8>z#M7HXd6VTheT
zqhx`F4UAHJU)g=uh-1U<6IhSPE&y!aoSIr3r9R~Ms%G+V^JB_13Nn_d&u{6v$=^EA
zun;L#6!PK7#BBCy7SmjGPV0^S$;DCrwc4B}Ll&LU_BTi}&Sho4rI4Y}JY(Tz!<JCd
zH0E*Mm$m(Z#m*Y@WTx0tevq1pWVEI?VGBFgkXLG`#F(Ke5_`GRZCcE-8@<P3*8C^_
z(6Ha9MF&30AqfdfO!R%eI925t(?C#@Hsmye*W$-?ka)R1(g@0(yy+$9Jr3WY6sCM+
z-F85a^fWU~_!^C=5zS(*#Mx-h4$mm_91sJ{Xv|;H=9l#{vh)spH<mhF@}OdO^h^?B
zSgZFe8RIWlHS>{Q`+oRT{EulrV(bqE6<3^!{Agy$b>h$gG6G<%)%x!A=2%X~IZd{o
zzaB>JMD0Z)E;goCvTHRgy45L-jmIV2-8~h+nqkH+VxYJeJvgPYscaOjbl$5*#{TFU
z`T4Mt&`ciR{DEiL0M{{?TNTd6dLb%f7s4yCTh^%qWgOdd*a=5tjaa$^?LtP!>pc@?
zy3nsCcG<v?Ps36r?#G`;Xgm+*zRH^y{?1iG?y$v_Nf_xqA2Jv-!bR3SP{%*?`agR7
zMC0Ed{8e|ab-M9$e4TjG`s#0euJNJvndGDDbB)K_XXbw?U)j0ym1DQ&ow>)OU;pCY
zn#5lH`oRxopHW|X@z&Xc?@Yv6{>9Yi4quO7w~~)u`P|{z_*~=G!jJ#zgYSODzqR1~
z(Ac~A^V747Teqpp*QdVq1<r!s`O1Me<m)}zUrfExz@|31;SaHxt-p6CZWT9tb2*2L
z<*2`EIjpK!%@1LWzxO8Gt+>h5fALKJt(%Z#lP6OBVj=(cf){*d=l9`D6Qc>UM9D~H
zT0o$YRum;)YFL#={f7XYeXs$69Jw-qorI5~P&_>tmK_-}MK)q%36GNv;5vu@|I#Zg
zkDZ%;ODLZ3RzUcdetY{LcJb@K{2Mm+_A9Ks`Cak#=8+!=%SN-|*wtobx?&`qvT8a_
zuwCnZW!Q0fKJm?m%m!;ek=SFcq+Lr?D^9XO<NUFxv-@cu<YU^*9@pf{zyTO6+G$0v
zM*83t3yA0ZQn(FzFchPPcdeCbs<JqY@-qaWTeC}@Qbg=&jJ*CupYWt<fxb3~ghk6W
zrxQenZ|V|BsI*CY5#AhUrcn0qY6R+?uy`<BGa3;cgO5x))G)d=K~KXD`rGhsKQ7C(
zowy_pKMvw&|Kay3LY)F~wMzgK1e9gR-c~nBlT0T7T<>VQGbWE*@$5=hMX?`uD#hcf
zsFYl_;>5{HJBL&sw<y!7CLI;s*|}5pK8o>v?4eJML835v)8_P)&#v>fQ-Gb2|K`*O
z4C^5Unv)0|F`bmd@^oG^b~0x1s$b0rf{439mn5X3xHv&hm9N*dpZM9~AvkF{UaSHj
zRiiknQzm>K^ogg8ll@sKp%I%mBeWsb0b^Nw@VvImf^AD@R@~Ao#MB-2#&7=`e?sA?
zCkie~z@oCKq^9nF5Rk%tJhG^X6MbTrLEBxBarTMtgEB$fy_&f$u_a+~ghGSj;hm06
z{O6RdtmKgEaw<W|b}N*^6U&q=lBY6OoN2x-k4eXs=-Y?B-)>ZzPL(Gj;F<ok0x;a!
ziY&E1dwML3J@umEBy2T-#oIAAr75aUe1N<SpOE(L`g2R(&}Y+Xs<!-i?A>pTTjqpB
zAyIMCMYy!|yj5m%obyWA4YT8ns&aSCuDQu)t;$(8I|IFm*tKznPn-L@uD=*n{m#(;
z;BUTle>EsUkpLjnFs2UI8kJYQWy)rjt5>Ivb=~@MqdF5gcdH#X(;d0Q8dB2g0XjX1
zujAC1LtZQ8c?7R*Q@(A6Ow0uOf=v^SB9<y_yX~9;ISQgmHPT0c!ibjB`7#98bWSmH
z%pu_U;B{JqIduyZ!2z^du2BURKJ9WecR1SAP&cgAVg;NOmh1`zc%r;niybYy!U-X1
zGQxM86n+?$ZJ<7kbGcrE91p53^x+suNnhB;F~-aL!5(7g^|k-pt=e~>p0-{yC=$CA
zJ0s61m6bw$w+U8&cv&8?xm!y30`?L%z_pQTSY5OXF|uJ~h%MMP(r4Kf`O4eyD4cuN
zj#+I2mT~Kae<vu2k(JRpg0#kV$sPk^ktLHWv6EkJI-Q8N0wXs7HV|^sTwr$~RBTOH
z0VPoK=aANLt}46c@Qo*A2Dvi`etBOI2LApp-c>#kpNOfb;c5a&yR?9RhS@W!7ibDX
z+`NQz40q~M62=tWI94H&@)@cS(8QC(?Vvi`i1#xbaEyGX*`}$doMb*@^~+lA)TP)O
zK{rk7sM57ioFxPR^<s1n9{B42@cl__0Iei|fo@c>lL|?bJB%6f)QRoJ<ntQU%si#H
zjrY8E&kIYDgLpZ01TI{z#_E2MQ^1iDUVyDlt#B*KX}Q<wl$OFCKU!AyVM|v!4PSMd
z09*CicDid=gMVVd3oAH<UTx}KSN*U8qlPv2&a{%cZwq(OP30=n_jt6~v^4Bm#sy$m
zV3Zcl_;QpwCG9(5+1C-<tcAgn$N*O>0rZ5xwInR;5`d!z$JuWcKo1>zr(LTkxs5+?
zFR7q(^Y`9=m05aagOyZ~Su<>cdg)L-GquwM?~Q$X+2fpmaF42VK;Ympw`@mH+inZe
zq(aN=UC;mxDdFdZBr)P?v!hB8?p0zP1xnbfyK&Y7(Y4~vomD5k5V{={mKzU*zx2)f
z{{D%D5C!L}tmi=i9HP39<7VSTS=}*ze6Y4;I9}JCn%%D`7PU)AMBa_MaSKMX`xofv
z;dybZz;!}Xx8tGK&QeD!)_Fl+z*cJ=nBh4{5D$F`h0MBXEQRr?Dg~yUkUr4HJOAwa
zB!hB+^kqVq9xs%3P&&~tB$9)_%Fq{J&Qf^v(8!*T5~M2TLKTIuHk-gAO5K{RQ6>;!
zZpojX(rmNGGG)6lwT@$DBnfuvp+58PjAP>LfoUgbX~U+TRgh&c5#Ad6AvV$q@eJGS
z4oScG0hI7~IeiH>M{$*<H>y0rK#rP&4k-bV^9y4?7fsU?Sp(UxbJt3>>x<k4%VT?6
z_FXo4YTMoCQ`xun5*;uqI;8IC#Rpd>51Zbs5MM2-uXwg1BCv?+P{W=PXXUQnaVoz3
z+>{Nl2{Zy<o4g$=u!AOspF*q?#!%LMzq(ML0_xWnh#yT`-<c&9k7T{d_GExa)348b
z)cA21y1HIP);-cfWt7lZ4HdJ!Z2eXE6lyESHR%?|`$)jou%ZZ@VBRUda_BUCyfS-e
zO{<c<T$|=;_d~cu=;ll-+;z0l6a33~*OS|Oi=O9Y5475SH+wBUxo~_qbzCneXH{pI
zzih26X(Ht0pXIxkA3W&ftznS+=?h9P?;c-`v)yX(UszX;f$3$N3%UoSerGjZzTic(
z*5Fc<Ui?b-KYN{e3fx^+gSe-91TlH<S;uNEKKmK<=bg2s#pQ8T8&ogjv!Au<YQwsq
zk61^To&U+DsdoNj3%Mfan71c#f54Pq^_+EK$n43nja{oja33WdWNLn+dgO&~|J)t*
zXWnsYbK&u1ujL(?oNd3hu<XuSL5ab>Q~tsgCZ{@g%)PMrLM!Txt<5bjcrWGcpSPY!
zFOJn;@N4ynTDwPQ({l;sw3&Xc9Y(dkF*Q}SFIwYi@2^=$A)Gy>aaop}{p1#_MDB4l
zjiS3-paIt-wMPC-*MG#y9*?hg?zl(QKV>Z}sZUx{e&>NJoX5!Y$Wi^_*jqdpTpXXh
z9youkuiA_=_<C~dM}FdJ@?Ib8F7ksX)Un~=zI(de$^8KQES)$NbwK5+GoN4YRlgYd
zM=;}2+JE!&3sydJ{8Zd|Zia)%$?^c(IZl*wY)$d0#F%%kK3R`8GeR*P+p*G448F^C
zvvOzRovqK|;O=`gI9PRjkG>vrU;p@Q+}Wc)1TvV9-lMpR_8+<P(|Sz+LMACx$64hC
zi_ae5VD8`jA8x(#=GfRH&4ebqsMf!C{*`MVZ}w+TNB>CocK$v`59Qb9j^;r=xNr96
z`uZbBE<bRt6ZNl;U;I?Cdh)>Xr_Sox@nyb0<q&<(9RIWS(^37k(M$Wz63)-wQ+-+2
ze|!ILTEDN8mC=WF_L_HjH2u<W?sL}i(;KU&u39OF$#80fel_|gD9}5W_l5CeIS5{U
z-^Zh~deD2|$A56TKf3s-r2D}5hqbf#K*kKrMdz#zRu7(Qe>PIr-~I-0c0L^cliG5Y
z{`UUUulvJ|eAn-FUibaIuN}BJ8cdd-{qv;XJQsa)X-NnF@$c_^wE4(-|I|HGQP-J2
zcI~~*1HS@R6MOTftXQUx$b%lb{J^~G&yHXG!HxXXf#n}GtY?>Jo?2nC%j?Jgm#JO3
z&sb7s*v*db18b??V-bu;oy7h4(iPo5X^sDR)<1PFdce|OCRol#qf`M1p3#H)>l6e6
zD^&q@0JFlu1F^CA0KG+uqEdI6UcJ=^&$YMB^+(6Q2E=&0Mk~s$$FyJn1&f-oIi|@z
zca4(SZu49lL@Ve&{Lb|qU}ye4);#b;^o4IVn+JYzN@?m4&+4udrFp&H8-1kthTA{D
zTT}k_z_Sq`Aw_rl&qd4Y^xv|abw|Z($GL6dor_)&DC>`-n!7R@wfhqwXVxNJ{rkXa
z4xMYiumqUVLl@qyG>^n-tzbsZ^cBAQeGT`1#`>@h<L87ZXP3OWmsFhQfBlSN$0keh
zT<`7G)Ks8k8v-1D+&2%z`MTE~U7Pzm>ekZIMt<n>@4$}_`@z^1D{`C1n(w7?w4GlQ
zsB0}~T6rpuGjr=TR~brnXY~|=ZauI5O-*UmAvK@Rj4wNSL-j}Fwb}U=x;;9b+@PfK
z5I>@4VD)4u<xFc!Iy|a%{W`63xwghX&Yn=IS+b)j7d(`ALCMFtcCuYj|CAHy1OFqY
z_xK&DUT|x9Y`;Dn`t>J3Oqu)+-o~E9fNf9c)>!Z#5B?t%w0#1|ANaN0Jw?x`z*if3
zOoPkzM#1nn)`}DVD8H=too7qk2ly^Xo<P{1`qQYLXGR?4&b%2`^Q`CWRDH*J_PK0s
zWt2yBupumK8qnk>>*oNBd10h(k9ufl{2SKN8O`mMwR6uD`<u;GqK*Coi@>>H&7fpE
z;Jf?)i}m>%sso=6k_w^<sP!q``uT4f{;N?#S4MRIvG&Kco~*>am*@fSusky;SAA+8
z=ml4h2g)};2Iqj+_H<a$;Rm!awNvG5;}2Nj!s|=aAKLj${TowLF(56)dZQ6m6!5NE
zESn^Qpv=J95W4H&cy>RPW*#>*x-&+qvRWzCPAyNk2vD37)R-$NxpUt0a2W)ydp8t3
zm6iRcepA)-j%h~segKS-Uk!<D`pvpy`t`D|Cy(jWJRKw82jVDi9yO@_eq49&o=2L3
z`cZwv56bhcgy;J~<6QfnTk)6CdFD8xGS8A>Q2^tMfZaxSP^CDuc4lebtS+T02J79(
zc^f(@*#BnmRmRLg%hViqO6d-}GG5}>>|@e{^v=2Xtu(1@^S$~$%ctJGWicXWjv^#@
z-=B+jy@;g;WnS|@T$vSw%5QI4{ZE{rX1!VMEP2l9$lq8vs?V$k6)MVKjqU_>ZP!3X
zjq%6y^zy!WQ;(Mx^&Y9|1XRoMA`L8bOsyi5-L>geUwud7u*8+I>iIRR+YHRB;$0-f
zFJ0%?-u0Fw@{%ZAr@G9UFaa}7)hXTQkr}Oz4ilWB`u3d`hcaC7>Yr03FK|ll=<ha$
zUbL_@>m{8edC@x8)b5(qc9YVg4>)z+`Xu#);G(#ej&Yw?Zy@;X7n5!+0-7faRUg$!
z{CMP#SE6?$cWCWb&wEt6RjrvFj6q8pQ@$UTZk~Mhg!YvaCcSE8SM=FNunikq>0F5`
z;pC3$%&Hse3bR!3JmWCJpvJ(9=QRfS`M6)L7Qm$jo>Wd|7N}*tM8M_ag*wI_*Lhmo
z-Y`+!h^%lDtBE}Fy}g#kUcXzj11=A}P}27?EggX3>bmFXG%06FAv7n)e)LZSt`vk&
z;7YJP;L3OZ|A6-RlfR4){`hzB!NY$E^Zak&ga6e{WFdl7z6mnsw}I3DuA97xzWx<A
z`HlUb`vMj)6Ns{S9FN*a!Cv|IZ~WamFBJ8@Kvg@*Gg`uPyylz49eB%j;wJ98PpPI~
z1n4;TKA;ajy@SmsW&q+Nfdja0CHjJ)0oIbp1{DLp<TeGaDcOCyR-Pta;h-h@65i1(
zCbIG4|F4(LTjR0=9DL6U&H7iq-t&L%7#<}K@TN5f%H2O^H(IfM2l`0e8Pq7rzRPx1
zyF^v8T{USVvv-@Sl|SpCx+;zrJneUPsu;cwJL<0F1Ov7Na>$}y4Iqn_i=mc)YbSVF
z<W!`xJgJ74YASO|Mk@u?!J(5={d!TFD7`;Ay$d>leNmd>Gzi|i4a0r`{I;l5X~o9W
zk0$|<oZTbQPaK`L)oV#y={7t89k2O5)ekYh!8b0Qh@5B35@_2Jih$Y>+fiBEAc&+?
z($Fm=1e9kx^$Is@-wr3nC{w9q&bG)VZ|3lhF_G$g$;b`kKz}SO*=xQ!3qpI05vCr$
zt=di{VrY5WWTP~d@UO;_%0CK`o$<0o6`7<?PDCn!0KC;P05vOOT!E2p3!hnvDN|4J
zg?a4Sm49EdzMMqP(^HT7#>9>$k=%*s0~KN-yKEd$<Eqs46II{c^TO@p6|hPJC6-Zm
z5rzF4VO@Qn?>q6q%E5AY7ma?SYL`z?syZ+cif)1h11fcE8PVVVSCm&BPuzY&5NPj?
zoM)DjV3)4efQo*>N=i3B+8%MY87CHu7p?bB)f*g`+9u!)8_z7YqfziULp=*J2mB0#
z1TvPCQi_9os^Appli77yF-U1m*cVW-qyS7y*{)g{Jgv4|`$`5&ajr8b%J~LobOKA1
zW9x!PW1bVlt@-gA`k6-8ZU2Wq_&X;W`*&7GrdspK=*hKvCJ)|Cbz1g#bicK;^1K^S
z6?>R<oYK!x`<j-V52)Uno%9~0PdVx;6|ow&V5oecGvX~jTxy;;h;#yUR2>oq^->#9
z4|!9ah8`>r6S8)O&5`It=*ta%+<C4#WjOx0u6^ErJbI#A9XsIudE|a+^9&_?w|;ru
z-u=H>^A*foSiQ^Gx$akIUIg#*+}dnAi+6pE+>ml+s4H~rAF(25%(8s)VD81qPE=d$
zfz5`?o^q6RbTJOe7NWjEiaGd%x|C|1?wfKJYiawfR-L244=S*^YFCXfIB%hu@WHyO
zmB`JFpF-QL9mpF~Q^%~luKQDAbcV=y;?~&D8`DJLhPpRl>umS&25*Y8aTG~1Y{Ugb
zA^eo6DtkxhUi1<vA$8P?Es8q3<95H6s~Fr=s+M$&79nLsm08S&a`bVp3YZK>Q?3i>
zQ?hI1&T8c~OcU^OGzllT|0(%Mw|3Px5J~=qx0&5psb*EYXUYtz9i6W5=k{(oqC!>b
zg?S@f21zN8Q<G{UD!h%Mt);kL>Z&D!H&=*5c$X0-PNnO{qT7xFS<2BX9GzCY#~=NR
zZGI5dwp%`;V}E=Mi4<^??(wokow&nYN9FHWi&Iq~IgVhS2G7P1P&fz_7%vrpN<PO&
zZIlW4Pnc9FXKi3}vCbZU8ryD(<j(8WZ`rfa!x8dnsH@rvA{Dh5(`URwE0Sr%S6xs(
z4(uM|ODP8Bq5{$~&Mzs_AAp8;g78&BT?+3yuZ^B|$mjT4M|VbHY|7P9{m#A87^jfx
z{nQu}v&DuTl|#J^Y`h&giTm{9zx#_j5}?rvWmAsTh=6p;Q^#zSLR^+aO!nf~R9Fg2
zO`Fpr;2z}5rU0PB`$GgB3Y;5frW03VK;|foca_dBwaa!3xU^-PJ^L=FTQlmwJL7O4
z^`AwNXVtsec;-YDQ0?llu!!5Vow$~|@wO$SsTjFr8i^$QwZrXUkQzJ=)`**C>r%Sx
z+ZEdk_Y3@q`(=azNZVy)Kh0=WbTitxgkA(g3HT~7I#0l%R!KX#x2)nv-n9)gAgPsT
zdI-1;jBLS{r&LO^%{JpCHtwh0;e=<GZBtts$&XKH?jL(tv2X`?Z`_kTPaHTsQ&p1`
z4=n10rDL9BU)TRHYi|SH#(CcP&J4#2q^Joog0T}=hnaaXf?f`(4??Uj!kcY4gCRA9
zXwhOEFIOj<kT9*#Od3aOnyNm%H}k$2k^>O>Vi;fA>m~pMGZ3RX7NhvES?>)=)4sH#
z`m1TH_HJ8AR=R51O)bSuo!s6%_dit9B>mXkbM`_aNP^^GX5O#o`91&VdF!@+wVb9$
zB6%P@+&vS=(d4vdaCZCqza^x=a@h+ivnsmf6eH!aAi$j=3fN`0>_y5!m3wwQtXPk$
z!rF_j5I$7uv+xt%w1L-xGI(qP*b&JO35pPOBNnLT-E|!}F|104G8$+<(CK&KFle`{
zzxH0x^^H&`M8r&&`zEN4QG$5<nHbI<8gWmLc;W2?QEf_$u^^8x6Ohe;s}=E{T7ZRU
z3kWH0rUqdzE%P9Po<1Bfb*Q`v18al{fyTC?i-$&or<1q;U0mpPsl@WIH~KrN4IGX^
zA<W@QybeQPP}Vxlqe#R+WKhR-76SlaY8Qx1ajgvR6E=B-79u67h#jFZnthxV_nJ8L
zQ`Cms07~WMMnK_&>NqH3HbNRf^0zX7g^(j8jUc{}2CulP)-ZyS<h2(iFWKPW?7C_o
z_$kfthKD$11pP$_`+`7b@CGiR6W$0%6md0s1Kc4^n!`C^!o`;X#C7256`B_a1_)+}
z?y<7ARr!zKKnr<I;W=Wm0kVXp7MCj+I2hx&X#|b}!wjO~17QzA81_MMy~r>ElVJ!J
z<2!Wn5SxN@If6KXgm=TS>|wtcl*wicPaKl7V4I{6;X^I&CIxFr&9mbSP#K`_Wqvs*
zo}bA*fw>~cnU72s7gjAoOZuWwTn`d+<=uW(y=eulbf52S=76<G_^2w6BM-t)(M`RS
z1^T8U<{sXSVF+UFm(OuT0;cscYT>abg5g4f=TQj{yffpc8Z+kF6*t$g)qL?BFP*i_
z;$NR+=ie|J>XQ=c8xg5Sw25L3B8;bvr5w3!|7UG+h+kuyrj=>MeT&Af9)t<pmnpZb
z^Xc5;!o)c~Gqdn?;d&oaE_NchWg&s|#Mya&$^XLa0d=y@`Z9H}5*R!<)7F~0a3K&G
z&8L=JWS#H4>61KA+vHfuTWsh{*y$P-NRS?<mUvgNJ19I-ns*y~_gu|n9h91_H(8^)
zNEgfI@A%ityI&bAT=)M2eZKJx_vLqT-z&Y?=qfi<Q!kV1R60j$JLV`z>M?hO=c;z@
z?9?-Z+MzXi3fjMlo<c2PCv)$W{^LG|LGc~m0D$aoz}PwyT&gKqu^+boQ`rDe@wgv>
zRN@1^vOJp&&Ta!E(ix057Sc$y2qx-d%}>x^5!Oe;AkZ5Uv=hZU&`1kx)jNEX!~sze
zVev?fajb6mgFD!g%*>VQo%hbcCys@5b8P$$3DrTJbg_XC{I>E`-S`z%aqrnNFxaH_
zgv1J-x;y?uN`3dSzonTkuhZ|}{d(~GLF1XhQ&qivDP4=c5&*0{DK@%(pw9KwN!Qu;
zahmu6W=Kl!gLJJC?TS`QEz!hTDC6GLb^n{n55WfjZ_;J^)Ab6=HBu(O>4$I!&VG`X
zS|P&v?Z9*aAMoNEjS=7cCix3C5}1wTK=DwpyKY`D0y%|mbu#esA<nGe>Ckk?7aNyb
z4xM5vAY>moRXyr9YHde_?>*CT;C)w}`F-j-^oWUK!#-6wd*;&fBR?GKsYD0X{4@ov
zOzsY!JEr%&K+oSD9}B*>aQ6xL?1>4zeI6BfNaE1t9%C_+w4l11Vm)=8-ZzUj!ia<x
zEpavqG6ZIHbiLsNjM#SNefIbwm0oJ(Ly$shbK$i>jA;VrgsPu~8UbO#r}T8xtC8s^
zD&Vt;KFHjP=Uf~CQnbe132}iw-4VDUQJD&AT_Q^5Riin-k$kfC{1IIKEABW7s?E6O
z?Nq0C%W*)A)Dx<`m-=?s4`^n8FyNLisw2UGJ)cdWiE7c4ZXQSmioQAEV=$rL^bK;`
zpM^<wpU)H3eE^OqDbO$<Lw7UL_@{i?RIqjdc9rV+t|rhflQf_xlmdt<0}h2AWMF`$
zC)AUWQKHima}iK5ywm5vZxz}&0vL2T0n!Y}diW0ltI^-}w;Ni&g=FP2q;?^Y+P85*
z`UjZ#Hm)aE&$peaMEASnk7uyM`4R5be`7j*0-CKGtRuK@EitK6?Dk!%PvTlMGI$x%
zw3!2l`XwkOgAOhM1S`b%3*$RjgF~)&D)4<ffDkoNMO_j!7M`(G5K;;^z<UE@2>249
z1i%;aIkr&iKviUV73$1N6iUa$HCEjE8YX{0x66t$jaNguMHh&IlvcD!#ZkQT#5=b}
zr#QOp=m~69<vg1?8+A>Hl&?5-Qv5pZO5(ftD}4IH;Fj;BJA)_Yseo}^#90t@{OGGM
z>r^TQ=wz^Ikf$qhGlYNU7B+#dRC~gc0j}k#@Q$O4KxsP(oEhG3oO=z8F-aHnvM507
zn_%YxYVx3AQ%HBQnOTrC^pOBTgD6@)UAbK8s5o$&WIBfmGzq>r_qnIGJnP7*M${hW
zpK;`Pro5UEPX^=ss0vLfYS7qN@G3A#Dg=zQ(lJ$plgts9r(z|b9<D3TZ174dgEra~
zqP5FB@Bn6k<-%o?AeM;RjQj(fF5o&LGr)#5HPka!`Ui0USX>-JLkJM7m$5FIXP-dz
zLlPPH_2Q`V=>NGH<V{8|y7S~W-RI<Dk^7v(n|cgz!+H+BG_IFapu;A&XZ`RUK$j^d
z7P#$Z?LqVilE&0CzKNZ1$2UF6>W)yVJ7B5-5)BCYY0w=prHRHyzeazim~Mnq#ZYz1
zg;RVr;2}!CWJptJgiu{e-AZ8M@=GWri8_XBx%#%!xwY}SUOIPq>_N%T$)JVH_z))E
zUhB!(kpZWD(|)%V<(WhEo{A9ka*z#b1ozQw;xygOFkRG+2(9y=mZ+ZP9}EfqC47Nz
zV24Be1A$`$bBNHkj`n7}d)){16o}8?f@cZ@i{A-OA{lN&eYh3-Itd2>K1+@MoQ&EE
zz^>Jz@PGZvFoUUI7HK&efi9cJXxVB&HQ7uUURd@kdjDoZ%F!|mezVFf4a!H4@+q+m
zjM25}@>)*P3_~m$vIndrc&-RxlF%w^5oKb%jI#{5jq2M)Oomr^l-38yaBM7%8jjNG
zJbIBn?3nXOs4ZK-x>1Vlt<}bG05MExlnxizByI!Z>}_Kt4BbJuLH7C@ZokGeKCJl&
z3Gf@R_93r?Bq8GW<CTqkGL%LE?-GV#7sIYoLelAL4Mph>q<DC*`Bh{d^V}*Vq8T_*
zEGbeONAY!5H-!GJP|MUIb+Q3Kt=oUbhI=*$<<L}5NGNx^8=pIW#XaS0Xd&^%0}w-w
zUt{07qp6(O&{RGQP38Zbi1FiPWF!2Xpz@*xJE0C?ru9={rnMo=oX`G5n3?;jFcar;
zn@)V3*5dJZ%%2K8H%{iqp&auUiRnLvo&OA{EN)!UBO6z=5Xv%<^PkvIRMwx_kapVl
z)L(t{u2t-ii=J@NJ>)xp$!;#{%sPTLt0Ko*)I!@9!Wlfng@sZ_@N{NDMhW}UlR}><
z^bFv15E#SVNLVkUc)AxI<Ds<=Gg<@mlX&P?;;9g+z{-;_qvJ1r_P}x7jqkccQ}~}g
zLem;n_njZ$4F1Vu;BO*{E&Yh|3Kr{jv3Eq2;#%OAm}53fJxKPZW4l%NbSLtt!x94F
zwG1=Z<dH;>6f>wsDJhwX;bDGbXAMSh;$b;3_zA;Y(-)~l&(VUU(z2K-$7tF$W0ArR
z9@fIhcvv+JICj|Kl)?V=VZTvi3bD8U^`l<lkPmu#S`~^b;H25;R%Ei727~0IYEA2Q
z=+!{l6`o8t_8G<KQB+OG&<I2uuX~){9Z2w4k+ve*R6rA?GF0hC!GFAUF`YT>mXImD
z;U8;Fnv}tMfOxqy1_3nDME66Vg9fTF;)8Rbftb)Qra_QWPa*$#3t_^uF)0Uj<5qNn
zQ}Ftz6nJxhn-D8%j9=HKj4~;q^b!)4!<z;m16PcCcyB}&;Tltyr#0|Z{4qi9B#cAR
zSN6iq(NbcrYOAqt(f6QBydWYgFMXok>&9kbIAF5DJW*t1VnsDO)qddDxD)XMf{6mk
z5VU{*q*XFfHAA&&pOiZbS&+ftRdJL=ATAg(sDK_+6`{<x!1qenLCp?jZ(W$TWj8<y
ztp+rW8UZL>$ITaXv`4NMOOv<$?kj@jmv@M%NGc*ID5*usLDfh866qIDw=?2UOfQP7
zEIU9VuBTHm%k(_vH64|5k@bxPSdgPI?~@UT2@5DcsNpj-WGGBl&>6Nowl!VXn*<di
zFjiQhP&0Z>iVyXZf(pdQ7p*hTFm5k?5GOLOi>$mt{Y(}Ga%N*icA>oLVsn&xgLEt&
z+3y!tGX0Bc+9>M<y(8vy!xzX=1v(tY_RR@4_R<a1Rht}^T!=_b-)M4K&JG|OB7C!w
zm_@_EuT*DHJs?vqv_WEL%5kdC>p~@dtjjRKE024)go-jbr=nlr5}%2a+(T^aQsHUC
zrjP!LNU*BVCf0+p<0oQ;*WHfU=F8|ijyu;dN352{lU&a(`O$auSXNKI5G(3cTyC&x
zXw^6-4WMM1pgt4lz?l`)Vaw!TLnI44qC5#)5cp8V657>(1_$-=Ojgq~nQ$l5vvyjc
zrRT;d-<e`^g+7V(M+Z(ulbG^x+Aw80M$@F=zw^e|!1z4rwBfU>wr-8CbVrcPUAPdC
zeV`v0bWy(}gAoQ79Q`-!rWpAemx0+m35%E@Xj=dzU_M0X91Ri@+;{*#oEH!<R;wlt
zLO!Sin=pY1iA{$wo5-5%YR0YqaE}KMk)gj<bj15W$&_&ZD!~eE@jcOd$nuilG>(wK
zs$W-fQQ#K???uuo(n`@=FwLQS0F1}Im^NWIsa^?`!y^)uqkMLVXq!~+?jQo(5K=Zw
z5Q0ldMrgc$X>$l2!j#e?66HmV>t_QdVKk?JUQR<A%Sga#(2j)yt`N&`?8=IxfK@?7
z#?dYmgiYhRNN^9r!48e7E(-*|0r~)h3N1R=p+Eu+Tf};H<e8_IhZs8D4$*g6-ZQ8X
zxiVbT0$Evg71-tepUlwG@B8yHP2zZaF55670>xwjW1C^<<T%|z0>n#T(F9!QdV~ia
zg*6@l$N>UnFrLDfe7@C-2n{bV<gh_71qU!r0yjWh^z)5(BQ|98uDjYM;rrW>ywMjK
zTc&$`m!9s_WH#iD`ba6%?77ZmBx5BcydQuLY$=d6Bskk)i-%Sq;tnL#Pjh&<uzV^s
zOpp&VJ}an&V54}02JxXV=E-TIq_tnt>bfRHzYeQ9e$@xx_L|C4u9&1_{Ut;E!#bTQ
zC3R!$#9o}qOs&RGVp<dm2uXQjh4Tf_SqffWl5H5qUSk&DAvd~4(b}OZP6A!z&@5^j
z?F;H`n{r8}c1?q2N&vH%j}}YRsITO4XP;wlfB22=$aIWAHO(Lp>5q;2N&#I{K+zn@
zR&7YHolKy;5(80l%t(SKw{DO|YUABxoEidWcn%-vA9udMTuH(nrBle8aZVnHCFcJK
zS;s^|BJcm^X5Uw@`beHc0f*+u+Cf9RU{uk$5>(1p0GEYc^zG?VWVp|%h3$#;9^e@F
z6bD5ft^^6t#<k+@pf3*%2v5{P6(B~7>|*J3k#&Int%-;$Xqb|rBz@oYZio^+sB2+a
zcoFC}aaetodH~irDLnBo*jS6x(p?&+dWm3<2`mA)qX8AraUu;&JQ36|fDM90w8p_x
zy<m#-&FG^g3`yL2^lm2Gn5LmvN2SC4Ul&MkqyimvO=<QUmL~Rh`pun&U^y!+4jZ}8
z{*G^7jBU+sR-65rktp4T$`XQSauKJ4Cgh$>!pjcBkKr4jFaPABZGz>36?GHSM4Mxz
z;eO|Z%#iZz=iim%{tQl;K*woDxXrEcs)3fTc9uxF$*nw+BV#^C`i3dSeJr{b1`%!r
zn#v{NO1WCW1rn^7N{KXiuvQ3G;;?d$CQ-oUgmeW{%yB-aAy3$!gBJzx=S6HU2;_U*
z25{SnhE5-KHiagY3zA%fh*@Zs!(;oN)QxBo4YY{wrvbY~+na>t2Kp@H&BZV<B;vZ!
zMl}o`oEADi$N7~+jnYlwAiQ&*gK$BIIihC9LSR~%_^WSd$+b)o(_$^=meVeKMt$z0
zOV{TH$}4Lnc6@dzLvOl#ftB)WWrIDhK1Umech8kBxR<`ux2JXb-=ClPl5>EK>$RZ@
z%P6Jf`I$MCI^J0u^Ck%dF*S4!L^>tH)uqx|_`5uS6N@mI*#I;ROdSp*3QNwJ4HQgo
zaJ7+uKV~4Nk_zNiqS2axXhbHXqTG9Y{AD^eRAQ-``^=$leezwjSc^>?#T|9)D!;*_
zna-*H#0P`^bH^8cdG^3e_S_5<xaat{)laMG2iNCbT0g&fxzTsPy>!7pa^RU*?Es%&
zTcd{?Jja5G!j9su1+_%Zx|Mb{k1|%6|M$>ZyQ!B@XN;DrJcD+E5*0|IhV{=3rV$!r
zjRFGVJi!}<)zakI`ja)|`dFe)4@c<D(qyAmJIfd9+%}nicA`|xtR~Efx*fa$M!KhC
zvjSZu1RHEaEy(~BudFxR97^;d=XyS_obV3-C$6j=2ouYSHyn5^!MEKU(#x!O{Qexi
z^|L{q_kY08bg__b0)_s=6H#E-B>*>(9)~BmX%tRfCJmvjhv_W**ifXv4W$9BRD3|S
zN%%Q87k*^}g3hNxcaemL1(W%yYP8Bux^R7}kcRFUxJOb^qY#2d==pLF24H@_aU%2O
zpz+Gb4xPxny54x{v1|HK=R3|)`YX}g`OAqPJf%+gW^j9M?$z}&(HmtmRSovL=~Mi+
z@9%dGSNCmeocvgn2IC8Nw<wpO^*of&&+n$$)*H@3GSS+8F>^NXbM<|o8XjxxOKhtK
z+nH3_Vq9vNt-cP7nV#*gCle8KF#{xyt)QQ5poTkvKJgP>Gwgexg6gla`>`WoZuUak
zLmu>_U-$JJHV$6BJbp35iXjSo0!1hP=7skpu0gGdB;BfW4BMsEf8$i)3m~H(nPR_J
zMxrRxh<;Cf-)qj_J8S6{74ofA?THiX<1^}j^|D*pHsFHunAdqt-QRz>3e95UZmltY
zI8^5W=jrt_K>!?31_Hq(K;e;ugvABs#o2ubb(F%CQHnIzMh!uuMskLu<bJUf;CiSb
z;->dNuILOVIGz850@-8@G%{EJ9tfUI%%%+~;uG#YPS@GurSlJ;{I5{trB1OoS=BN9
zLEMXdAwVlb&<4ErZ&W^DZ=8{v_=4KoIFbRQar(!R<qW(rpHzD4M?wyF{!oGkWx0|^
zwZX=M3iIz7f~R>10z)+@uQ(L=hDgB9z|(+j7~>L0q0f+F7O=H}X!7bDO6h^-5Q?or
zo=#&Q^$Bsj_8@pHe%~HPq|m5sdlD@nB{q-G?|X9dJ^9b?e|H7KO9h%zQ-K0*8$%8~
zz!w0#!UkMG!}S5z%rodiyIv12xX_CB)S+%W`@WvKQ$|-#Of;41htTZb8&WDJw0HG&
z6Hg)kE1geuVL?2CFs6x`h+)z{a?Le(UbqmwQNy}wR_976_X17U+@*ljAbb3rnQUAh
zQY$BOQz29bU4y2%7Ii6o^4w+DYXrGXO73~<_JwbF;`l6OmDEH8o6B^R8<*YbD6;!U
z>s@zQ0ZmlP1N~+DxC>;z82oN<zPC#{=|dG;qNuF`)_=@QMiO`7&d7XWfd~t}RI$<O
z0d6@!96HgH#Q<~@h*{jI5R9B+0{jP-3ti^9kShW@l|r>9DMiL7#a!7J7s|YfKP3s~
zWAunPEo5=w(n8L+YQDX;qZ0M5!<M%5(9&w(3EpragM6{!j!Tn%LwU_P@1&RA5PhK{
zt*I~hjeM5~G6=}mYe>ij5iUhw$w2^(j$nJ@s>$_Gk@`N4u7C{vgeYhY6Qarn0j&+v
zLL~_cEE#geL>RCjrc~*{jwf}i62PRx>k2x`LR2$q*v%oOLVGGC8o}7VG9Y6rN;&wJ
zauFd?7_DYKidFGHIgRLa)Xvq@>c&Lon1&8k>*L_(dov{@b%$+yzE=a8TpyRcx`Q|J
zWprF#!!dvk!MjzYq5u+W4L}m8X~UB1IA4gBdG&plA|56b2(AH6!G0UL<B70eM{RQ}
z4n{fnB7ieoUt0d$Z@mYl13T250mJcrx0gv?{a$Y_uPW=D`2C0g+TECGRg4@JI9U!3
zuH-P=9z0xNAw#RKt%5b$!X;VtVU|bGups41$;GOVy9<RP?kHFsQqGGU+2pX>6PT4@
zMF-GoZ?FHd61e!HwZ08!j3WsZS13oYY+zfGkN^8$Lgw`h(iUCSuaM%%dW;qhIR}h{
zw9;B9szb?ZZf3MA&(=(SG^TD%bi`nZ#eFJvS9O>tLEAWmox9>!((up95$uyEqP$cf
zbn7s{c&krDxNZGdmGC(pL8OJb_&NNYm#TVNgL}S24B&F1Kj29n`u%(n?xgCz_38XD
z12Oc#ZQz<qC#{?ma9aVqRK51|N_>4y2&OT-uQ4o@;ktDlRb>2RVNA_nO*3)5ppOlT
z<KpiGAB-!!cT_-rI0Dhna#<*a`QxyM%V^{h0A=9fEn@g68S=9nz4#I#D|i>2g&(fm
zc%R!e_W!fI@_zsp{w$^Zzl}fZKap3~@8qSQ8Vn)o2*c-JOicf8ALVBv&3}el{*zPr
z#Y}ME+k^Vo{-1~^`pkz5Vx5Rtj*oPI*OdiiG&}OfN60c0sIVF$O&HA{5GO{43p(Zs
zu-VaIq2;bcX6C|gJoGcX0K**}jT2-Y;-|2&30@PF`;I^m7Jl`UhZdUscOE!_pMThJ
z^WiMvrJwtqpZ|r8uLmCeC7~dJjoJ~VCqR$y1c~WIt)uHaHrhL9cF^2vXLcm}!qk}u
z`c^XZ08d-Z>rNIKu?!BDq9ygnVK`SbW3pr|R1O9ToNc_d20@Vq^Q%%#qt<Ix$)J-a
z3E@@f8Ev@v@S)%scv414XIx@04MD{dLix}Cm#xTxT!zHbrqaqVbC{Y*V<&0skWzdI
zaUw+-E9#vwR^cf30;qyYTWMJJHI*)-yfC&$f;amxgEFTHZWl!rhtLaF;nh$I27?pC
zyKuNJ9{56dPay?O06^L?s<^1|U7?BF2R`g^B?7vkMFUZ>JaO3fbiOYZ_a((m#nz0M
z#XbmKGgh-)zUIsr1TBU9NO&4=U@GQBuj-zp!ec?JA`2YeCKFu`De>tLV*(lpUV&jM
zBm@F8!KSznPr@A`l|)YGq4M*s?<{GCILv%26>zD!uBewEW`6g16!lwHTY%r-S5byP
za*?tp<01|LC`cZT2wJ9z86;&VMFT&lMN?7>0s0T12a};xLgE$9AyAb2X~jYhJ3Esv
zZi)x2X<9eW>8yOgg@<KRZq(Qe()?J}B5%Di52RxOR-&RH?FI`*5k8aYQg_5sUHJaE
zicFXvjxMM`yI9s4lZW*R98JxoqR=XZEEi0R0zX)Ad8=b+DcI#mk%matRj}CtZbEk;
z3P|mPOOEPv05n@rSBbGEFY?ycp8<}xGAbKJ<VB>Gy7!~y5$5+q%B!k}O<fa;FAW!p
zVgi-|l4qyvP-=u<Xob#!iCR7hgGSRc;0|e})kZ^6k_wuXljt4-0es2TbPAzG7ad_l
zO{2Z5bSP|+x#0-`v-rJGHAEn4^~Cf#Nu+^xA*e?9;Nw61C2ZAJ)vx+oBE#9jzjcd#
zN9R?>^)F!Cqihw02i4tbdfG_b;QCn|Y3qpn2QulaLA0~%wpp1$`29Es4nO&HT5AH5
zp{Z43QYBC98e$b(58DblktY)9Q3}bl!377AA%KS=Vpc&kZ5odNCb;lc-bkb3Jb_0_
zVIeoY`tn_HeM6~TKXh;%F?4nX+2??A5SM}g2K00WyE$MC4z;3ovL~u71bE7WqYQ^y
zrNht>O07o3Lxg3+k%!ZbdlL>Jt;zNX^Ci5{M8HibVg_l%a3$alCVi;qz1m&NF>S`c
zQu%VM3~L32X*5tkfx^SWl}uTH6y3f}aboZ$WlaS01b5U$k2eWa55a*NWHf@DR5YQD
zsQ?(I!oU?c+6CwmiRqf`S8PFRm2$v+VnwHLjo#@wP?;%n1TV@mIzd4aycJbFrg|}q
zauvl0FrA|4t!GG@9=<WiBW?>OTOEBhB6uJ|c!bJ26g>!4av{K_m_jtZG3_EN6C_a-
z>{=x**uq=sM?BC8RY*ZrjqG$0&L?wyAp@cmrm`l`^NoT-dL_C`9iAu;)piG`7lC!%
zWS)5Ls-hiNq@8-Vjb=jf4z5@ZCc%VJDjl{4<~mAnPbC|ru;f9GDJ$a{h&2)nrbGmv
zNFB{fuMciQF@)}b=?cvw=>#=p&>h0Lu37fO>jhngmW^<iK(&uT5;K?qn+T$unF=)6
z!A_$+tW%>C-o6FoL@*2`NCvR9bUh?ucR{^Vu`%I<frqdSg$7kJ9^}}S`025?K3&#y
zv73hFI(^cOnjL=CQit%SmP63!_`*}R+EmLd1)2rwDS|w<0}X@fZXTS$EE!PD&Z_Vl
zk#t4JrbwQok9k}0ek2*B5$iL22}X>Bu5KFP^nh*f3L5%ePGp#)=T7xYn8uW{gxga9
zch{wS!Oj>cO^f&p5wj9#=|h%LcDS>J6>UjtrBp9UORDCNU?$$wN`}y@nmI;(Z7;_f
z(JmS=p=QRZsO;sgpms|JCf8MTh0GXnF*Gn>JVQr{yMT?vhwQgbzM@4~5tCr|7>jT1
zQRU(V=pPHpk}4sN5)p<OB%zX4KxE14MvLrK3Q?#l@mR(js1f4S+_)qdih+?OHY2EJ
z#+1BXY0cS^;d+YHrjKcS3n#E-$I!e&CFT*?#tp*B*e0Z@0}GpgXYnmVU)6QY8aO#^
zo9vvxsK*`Ii$V}~E^Y5s?66PgQA0`XCX7kCSJMggq7r5W2rSXFL#&2*3&)AX!SUo!
zQ>ghSue;jT3``i3q2Wo8K^QX_g_`Vt?SGSTDITgy;DIFo{|R#TF_KOr=0S$_Y1%BI
z9)f^T?V&lqaGRx?U@Mfm-4bpvjueLLaAQRc^6RkZ1kj&^GsSv^00k~scLm||C*PaK
z>LaEiER62=pbj(oCgLQT9IoVwV4?npUss<cBUCV`PPK@)4(ubfi!asCgBt1%lBdI1
z+DKTQQ&IFGVHwU^JKGEs-F}vcI_4&r0GO%48a%%V(qPnN2T|3khD%YMs-axH_@3qn
zbd{RuNkT!aSUnNCH)aW@RYy?Him%6tT+~l1%|wYbD*=F@g%zv)x*pMO-Booe1bTS3
zVKhaX!D--=3?F(%i@<0K1Q*5(UO~JEJy9@aVJQ3_M*7=7s#kO%;1+t)DA+gIs!`@q
z^`mb2Oy+=MK5eiUF1YDfzm)ESk(H)?|ElT~lhRk5e48<CBv(z=o==`wotc@YZOS|s
z(+~0sgnhmC#k9F&k*t&Tduw`<nH^-u>gq|wJg)FxuMy5Z$lExd+u0hRwD(RO|Bq+P
zU$516?9|l-_Bld+jbPixx@w-!Vr$&PC2_D~Q52wsbTE$4pvP+4=`nKLtdC?!-d(Ca
zdiUlGDz(t^7oZEGsj-6k!lJ75Z^uGDJ<@ZN5i8T)(%$zFZ*iznc*C`k7_yJXjazx8
z{KH&)Y-hfOq-GbohRouH(jV}p#nEKKs41nz^wP|%lKj6(GM(N-U*g7Y#r*pj(k{0h
zZmUw#+DS^$T1;(Twc|C*a2Kx{V(Y)+^9h<<wUyR-R*mzKq^VEVb2+m<c?=2r>Y$xS
z8S@rI(ep-PlGk-}l;v&L9xB!b(__<m{%c>nt7X>Dh1h^Ypj8wz_YSRR`3ResHQ<Qg
z*?gEyplspM*qjTECKA~escyk@>ri*uxnoovO68Db7VM-d6qkUm3UVk+{dE#LbcYb4
zud<!==by3v&~I{{Y%(hP{piD3Y?K{9vNJ|*LBUmwhJOV|S3&L^fl~9{H1_*J)tWKH
zc!52`<a0bNq~k%|fU1+#Q^<w9RNwjjPi`5oHs{{XKzpduTiD?l>6aPxBily-oIZTH
zr~Z+N$NK-1lUAmq6CZWDelVv_1gI=|Xq{fQ4nZzRGZVk%)UCoBjp(BNxccSBJGIq4
zv5P7af=i9hwuD1#O~EF<`?AHi^EVRLTVE&Vd#A~lX7&V2`T69NKjN!x$m6_1E*|^J
zzI%da>^(7mg!04R1yA8^*~BgU-0k{$jJ-`pyWZ3<*hoO%*P`rLBG{r#uVe2zK*rzb
z`Z^0n!Gy4N8Qzk#&Vx<VAlkHd8&H+1l~G{7-bSh`iInTNFVoi?tKqb$(@|kJ<P=@k
z3WJw>Ag@LJ!^033_PlKvUHgY{?fU?Pz(-!(-mWagEP6~;w<=To_gZ?MvwN{=+bX@r
ztlO)rZ3w5hN?U*Oe23aAnbk8nK%MLQUmBnaUz*uz=#{yb7Sm^eeEdoWGO<CHYvziw
z%U%b&bldWf|LNe9iD(VE?m(Ko*bBF-3MMxHK%$9`&quKY<sgg&a5F<mC4K`EDzm<i
zU8<8m|LVK%iy<LBR2m}D6+*auQ@rP+4yxK6x?DNpzj&S~_#t$XNcl!uenolJik>IU
zGCjpVTyFPgX-|AHkNN|RcUE~4I?+>&o9%uQ`M)bl+vT=$B74kUB-nAUV->d|UhCJp
z-faEN)f&{__=C0%<*EVv)wY%ty+%j7elc&d5ySKeS}H%RV|uCWgE(EfMCa2STeXGw
z4U0H3u#LK2aVp6Z(6*(~as=e7_v7zu>5+5Jk_x_rI#zKsf*c>}uN;Avm~=JaT9EXO
z++mX(3f98Y*{EAN@mWVM4$_C8%io0@-18rq2-MmUVWH8XoJ8WR(SFfJI=VYPxuW1U
zqwBR^%%`M1^!$-fyQfT&2JjoF@ml$NT-Rsqt`%T6b5+@~XxGyf2jOFbh_;PhG(IK5
zu8>W%8a0oqz_S?y>(Z#*cd{Sga~`aZ?54heLXHj;pV1-bv6wsLg!kVep-dIb6kW<&
z0a%KjvaT7kdC1#(QiH);d{v*g(pcgs5Qzeh?T1J!de9m4;^gFQ{H%h6qgu!0B9GNb
z34?|3vjOBGF4`qzn;m%8GfKN*@ZYte#l+%766gGonnoVm$&h=mYV~~~l!mSn4kFGq
zs(AHnV4jdpu8;q4`;4}EJd{;OhB<cknqv1m2`kcL+(5S)u#r!y_Q)A9X_N|$MY`Zm
zycJUq+HIsf=;%pQ++0AG7JJ18$_%<j^frg%?2p<C;x#k55Y~m=*Gl8(e5cX2FO7<r
zYH-ljfdLAyW4o1t*haMX)kcAHF;w4&n_fbN1oW4?JT9ZRfU^q~r;Aq|1jwt-7)p-X
zANr%sYUK#xdb=suuh=6eq6mf9Zi6U^L(YCcNe^f1$m)GD{OndN_6dg;2Azj}>1zAZ
zAjo6B?bkt(8y#1TGHSkJP?>qUryY!!EZG-r*=Tdxki66AZ#$B?ikH>W(rUd22zQ(y
z^5UA(K|7y0$#Yv1Z_?l8YDlHwGuI(z^?kU}B7u2U(^VKRIRn}a!22VAGb_a-<D0_M
ztq|q@2dE#81hFk|O5voVF8dodSnfI++e%T0p<Ol)^?RJGXA{ZS=@NSFv;2Hix%9zR
zM5p#RTOnGP6Ocm-&)QgO#69ijN&0H6jBv!7Rt;KByLLIZ^{PYZn>53PlYyR_tOi<L
zL6uWsJ9H~tJZ)>hq07kC5+M1`$%6fPYm*OQry5dRt;z2Z(@b+BAga?*$2%MCr&#2e
z_a=+d+BP3+v;t=v;?KgFU@xkX>NysLa=Jf~MrTXB5W4+)AsT`0c7}9I!f89B=vciV
zTvc?We1~>llbx6>jKyF#@Dxa<1o6;{k7gEasDYV>J+$pTJ0mDjNm%G%3CNGn_zbIL
zbS`hg5`)``XSf<W_;nr~!p3)OXC@=G!MlU{a~ZN&an~gEjsvb-XUDmu?&a_=cfyYa
z_UVQSrBzZ4P5M*-fI^4a4)|4G-3S@hc7$6zY;=*=nBj~4p=;@L3k#^Kl>FO&YF@Rj
z{7NXOJgUB(3gPB|C;$9w$DV(2LzVfHgl&j1!+7S;M45QuPPNSJJ)QTy<8Bn)yjFPI
zo%lTRzFXWA8>-9)uRMms3_f_J3x^r}7>Z@$FoPfa$zlHXPUiW~4)Y5|H({CFIS6WQ
z{@l6z^dSG@x%`hD<R53C4{c<iKl&|f^zO+P%wvK1U`J>t;j}RUIkJTvFYf&7JLLAb
zvkrEg04D{L3!ST<{3q}W1c3*?_)idQ4c;J(WR1g?-e`S+U@CxR4+a5;_49vv7v3lu
zn%H<ikAP<nf6<JiZ9HIE<AH<!45`|8e)7|2Pr}gs+2czIO|K5kQ^%L?o_heoEAXim
zkSwIglkx~xG7$5@RZ%lpCZ6bY+x6%gEj;HgcGkh3;xrm0Q&l+nw9*Oe^5i7^ybe+s
z(gGmA5}?iALF~jML$VNoS2mY$_)1MxS|ybeBt6-*2u4VJuo9Z^nSRzv@N<ft_n1C!
zsEN8-+R3UT^vl2f9&N>)=KhqGATv?75QV=6uri~fV5gyrNKJ(AC<rh6hNQ4!Y|fd3
zuBFKNq>j5W1l^e$QWFTlkfjN3gD1QLjbQU^VoQ^flG8<;k8VZE5^l3A*vN8~3J60g
z&}bkmu1^w?=R{?kUH`MDnF_<?cbfK#+6bG9f~5&+CX<R}y5U@V*Z7E~YG?KHdekR1
zMC=J!iH5m}gdmZW(wuZ1eCiAtd~y?qW`k>6a>(Z06pHu6Oo`ov?W}7_2`moE1YkwX
z8e|6(33lBX6w==B=(Y`qQy$l=NCbZC|2^Qn(5V#U3CFRAAm1D#dt+HEvNz@^s**{H
z73h|b9L;qO7WS!4zCKVB+aVmoB(8W5*=b~q^U&Ai5ptRwBW*A-O+BrWz2q}W1lg=o
zrnq7k(sN)b3}rvnWnw2J+ici*m47;RT15#!ma8g7Q5(hWQ3<O#$b?YG5Q_TN+<u~B
zi&&wsWEecJXRTSa9FP?QWk)e+;9<-fWjK5lcDmjtR#|hyfO55Fc_V}sl5!&N@Nf+5
z*A-jwwn?Sh3Nll>iN4^w#VUu;2huvpMsR`Od!;BAC9hi0?1;}?!se_=dcg<`CDy(P
zREiY}N|2+vzC$N^+9kWbYuvkNF#WEz?kn8!_1EofvvjUMyKbmi)yGaItyMc)>x8gX
zKcJGn-;MFtdB>2=%-D6?YA7~WNb8vl6gzki(bIX<5H)b>rCPnPmw2lrT`;$_LIOiQ
z{RZxue%CH2;potG3w4RItSn}TZ$9FeeYQBpuK4<bzT0mevx?*{#hV$LP9W`ei}$n(
zX=w_(f*<p<GoQ^X*hRN#SNmlpl3I!>vnZb9^kHk4;4E<7en>pykz%&44CswcvzjQ6
z=xpVYmi5>(YVI0Yi}jX{rfF5#6<bu=fzlDU;K>=%TDV}RNv2#i%4_7LLsE4Wq;?lH
zOy)IS)w^rzU`fBAO#Tpw+i(?SC7q-Na1vUst7$=T<MkJ^p{bjppNpa1U$RsE-^<85
z8oaljb4{8L-1RS~-<91F14C<m%IKcS9MJc=n0PE`)Y$$ifJCNf`6GR%Y%Zy*%Kb)B
z>a!$6Ijtl`vKDv}g3F2<gzGo<<~D?3`wc<Wbqq_=Bw$REB<c%*E+nB%2nW9^SS4LY
zh{`T2p`fm^l4H^sN5!N}wOPWOdQwrsWbJqRmK!dKm^=kR&j^-g#Ukb6(>Chj!DANH
z(_lVYO*b@YhtzIImI)$^SaYGC#56NE;|7Ymmtti_U4N|6I0XWz&0>b`cZ539fSguA
zQ^SZD<hUO?`ECOGQ7kB{;Z%(}ACzE_;&huML`})+nyMj;6oNP>#BgZ=W)UW>Ol#E|
z6DkJtU}JIQ5#f(DW)Y48CccQtB+u@pF&Z!_VaNp{5iI$#X-I>^ebBu=Zft?<O?dzB
zzsq>=xQbz9HOID2S)LSEj5O%k%ZO)nxG?CQ!p?NMThcZEmz`&A6j2s5ok&7!QIQho
zk!GwNBa&-$bDt}co|E*H)G7(S=8J~CYi^n3Z2kxEZ$zT$62orGLcy^82x+FWk|mow
zm=z^N28@((A$I%I)-t5kSA8)THT>#ivqNTSZzLB;bgtFcW4=X4Tk~ugp^iO%DSr*U
z1p3j>BqSz;P|)KJ|0pERI6Ftsm5kahyWQjr5vc7mPn?j7Gjj|uD<TLevM%<jl#TM`
zeg^SBM9hQ@Fei`!dyCw{?K4LdHvQe@pooa2zvjAYN{e$JDtw+FOWe?BuS^fQ$bu2p
zPr3*vE!%yqbN+(gaGjztbG&HIJ-Mee@^D<05|N!oO42rKqUXv+HxY;6y6_od2%ZhS
z{l)?=pd>PaWu|EOs00Dg#zx>g_E{%rcV@98)K))dp{9}R2$tem>uUDxCm+3^ySkqm
zV~X|w7gmw-O%QUu=nz!~agO+d&2n6!P2GqefcF{bOjzFl)rcmU)J9sb%_Ajr8Ub1e
z<l$db*V5YKZgY@EvP82fl?FNGj84aF6k6?x>~;4d{lD9&W{<=Iaj(JcY@n|>s?#kG
zB;Q*OIUQ)V3~91}HC5HHo#WIFzc*hf%+eF2Zw)C=fpNe#42r%XYU@t2okj3RMtfOw
zDvGf8ShqAs1Q$Tt?UgDBPq;)N0FN+IbZo~uZD1`HHHr4gDn^*3ZSrs_)SAlL2MpXY
zpYT6l++uY%lor>EMY^$9SJRLuw>w6pn@_-q?X-s-H)HsfSP&<M<X|yFJ0~Pfx=JX|
z${wpL?Y^kvTx?3O5<S3J+M%whdr_=V+(Fk+x_}EB)_&1nrU|See%XO$LWxCK0@X7R
z6SU@r_No;hW`R?@T|b9uLtvVysq(Px2;6e6TC%!=%mrj(iS}|Pl#n-Look)taX-@c
z3@Q~M0F~lXe?+h`Ff@}Ui_AT1M_M=UR_sa1o8i!IB;+z+o{*HVV)T-fI7uR5ZH%5U
z*q4A{XVez<8Wy$lz{o)E>sMXrtuOznF$|}J2!%-8mE7dZF#!dQw1`j>gt?*~U@NC?
zC9+aLO<lQLB8US8o-S&e1wi>@xLX)Mm>P|i)rzjsm{gjz6SHpj@wC*{NkERjiX^&b
zoW@=hfksrWU$VN_I{Q(C!m%(@QL9gKR7>ghBisM@zihGurhCyv)QR_bZ<$(hdqX+p
zvSWcfXQ4=Qvph`wY{m`JT$9=(lQKt-Uq&zpCM@?PDrhRki{R*(-YC;0O%zU(&xG|a
zdh^^h5QW=C(5r~;sxE?hT78G*X!0_;t`}gVHaozMoTq{<d&Z*26Eif?8I&Ke<5%1-
ze)P@sN59J4{;E}e;&}fT>Wyq(|Mp7%GfMoT`qI$jSLk>A%=QCMKX_5SeE8lE9^b=n
znNE3p;%nAp@$Wryg9S&GrTQ(UY_$-(0h5X*8!aYcDy5O+0d-~%+3}%!$JrT@Hrj6x
zWAYoTw`<C?3hgD=jW+*9weV|XHC=w%IRB7d?xZaX=>mJ0w2!rs8p$PPly^ZYSmLv>
zrB7Y6ZXWPgwp;hnp|yBtY>;N|qsPjFeqUW}F|vPcA6;|bcAhwOBWI7+)l>S6TUs3o
zUihNYcg?xkUYi+8uJkre*r<dV{9FIeNa+UaAKRJB7yj@&^mqHmCI$+}AK*V$N#XC)
z{2*<8qt-<S*h0L`oy)R|v84y7@xmzBiC!B?{xR9Jn68hsv((Kt|5n-t8*d+>N}F-O
zNTp+KgG#RI=jQBW-fX!vco2IQ-I%y-t6ksW7w!C1TXvd#bvABx4z?-fvEsp?C7?$l
zDf(SL%J)z1_j`kfxth03mZnoq{DWg|VUpi6)ZNYt*M4u&NjtWEd>}Zp{Y&&zNs2#E
zgNcY-Z1*tA({1mo$IzNfe*NympnJg0!QX>k7F#r|WzQ@7*&RV``P+8{wKp4gHZ{0%
zq@GI6%{|&)|Lnc+^!~!$__I&I!(Q=Az{c%B(idW{lX@L!6TdYIHjV0H_;h9`&81dD
zN3Sy-fIh_NTm1TC-~-_{Mqe}PVX*>ys+-q}@8s;<b5uXdYmom=7b~MFoHGdc1a@Hp
zFTWUyf2Uxr<=F{Hvha5<?HXBm83M-<tFLaLdS<Ne;-TCB+Ir2<J5eU{mYUc>9tb9W
zY}<#c>5m6XNB({=s;)hJQTc(YOqB=RZ>Ik!xb@2VfU^)i6};ZKXt&=|pM3R3-BIGJ
zt3X|l>K^JH1dZEe51vr}{N~V+J+Zgd3@~V~)9M^^>ZI*xh`7r1$=At6dwyU0tx3Nv
zHBAz?oPK~cFz8y(Yomuo+ep`-z9)4>k&Qj6=apYq$NkcrZS;PV%<ucQ+WX`DXd*f0
zkIyF)D?uAMRd^GXt0&yZV}GY+{@}Na8+U(0{qW`a`e=*NgRObm@*yi6=#^g$#NB?^
zt-0-|F4vLRKj0qqQ3>@2Pi>#9lRZyJ2ckRc_Eg~nZ@oD9KmhGg+uaFkmbX2iO#J;{
z)Y}H*?*!!or7-RPD<~UVPft~!4(ic?M}E|QFgL4y>M!f(Q|hbN-f?>IhWriMVds8b
zeW!f#;d_;dcY@NxlXvY8Ss$t>((C$)-L|I2Z%<CTAkYJ&7xTm#B(C{}bEp@1(rCNv
z*^Bv2&5c0#nh~pQi~l%hw>e#6v7T2GBNWQjX#{`O$YW0{R!{xzxcU^r0nru5RE91O
zIGd&zKvDI5*>WvC&^O|OWlp`k-%Z?p`!AOtcawG0u4tBgJ9$Pu$p_leudVN!DS%1{
ztxJj5gQG9qPOT+C7Hwtv%vT&e@dMxAW8jYA?;b`~UG|C5L_K|yKRSBR_OH<)l9YRV
z!mLI9o@KkWzOVgS`%`(u6~J4G9bVPoXwP$mWEWQ>-M6o=wxJFRlFE(VB|^Tg9<>*6
zszKPY+giYu+sJhKOW4#QFfP);wS$fgIpL>A$E6o<+F@~qqt4RWd3+WLIZ?i^3@u|{
zv0Nu7<_@ln|L}A7T($m~81*DOXy?$62gy*^?~jhPLtr`D9_&+JY|t(go#ijJ-7r5K
z0Ac&LW}o_`ldNy+zd{;EPN>uGd$^wJUhmZr0T~z#b)$}bKSaaTC_3#r5VGMXFRY^U
zL<@);g0Q6Lf!>O42twQULrN>?o~XAGsFvGhipT>zVXY3%ns}O6eX{bb!R3kPjqoxK
zt$+UpqLH<Z6G30tNLCTV(|X5wG56ewci$J+!!CP4wQ4DbOR4M|Kw0kG)6x2XQ@@+>
zzAf#yE|+u9>|+Ok%x|meNw>{Wf^{7u*pEH@oGnj$kDmX;DgJ|U`6Lft4N!7Ig%Eim
z!Jt|VLX4cYyUxxH^go~9R6^AQ*Sy~PBhJU=lYEb{L?)9<tJ|fkspphKfnN&p`ks27
zU`wPubsuWsoBqW-u>3W;L~dv3m*y%*PH`I&@4r*k7ZIyJRPL#FCJy=c84&FPq1I3m
zHT~+!E%$Pcti*!xd40dt7u^0gBljEN)}(8n>b9lscP+i!&nWj_9>~oM#$96zLPp@j
z#yJGl1{>4RhfdC~+3LVZIKF!Cr=Rq5e@p4BH;2eiMwc8cEMRbzB8Jggk3RX%+Dqe;
z*Y$V&$z+|hU*L@+Xwy9uF}(Jh?OTQ1tb)O1N?&!7<V|)V*NO9d;*?Q8(v`hVGq~2k
zLwywn8jWJj@u706{%g%+wx;83aKm%*uzSE6_mBFrDNPl%+fO|PQ!hUq4X@}33!e`y
zgUaXRp8ra&kFnBCY--j%a=z{RU4!&1^)|yK?_BED6JqO<-Km}`9<m8D4sx#=yt1la
zb#JympO;WAL40MkZ9QZ3&e#}D*RXSCbW)M7QWt`^U0he25$?uskO{Z3PL&-hSFUg*
zRV5@tz+9N~?TC3Ocrk+NRTxI9C49#DYd4T`veN&fa$tLZ=|&Q7I5+#xJE!K~y>`$x
zuNQtz9VBfj6@3mj?K7)iw~4gJTqL@6aemWl^kSY{Z`kd)okOYo@<~09>7!?ntRmM~
z2o7c`<iR;PXv=$INlvUx+KFTbuXL1$2;vZ8WgDtEiJcT@Y&NmB%P7=O>?^qljSo_I
zb$kY)ps;*utz+2&qt<E<C{C*^90<r&F!>_S`M3OXHc}~Gsyl!8tDlL@A${<K(mbP1
zjX22_b!x09$`74Ct&~^%R#|=I0Y~*u;p2t!jY>3Lo+Sl@?t1OwA!@^qgMeSL^tNrv
zv!uQgv>eXD{lv3!60B=Q6M0N%=1?6Vnrk3oY>sqCbo>wV8oiX*!(c70JVJmT8qxT=
zFHE)v{MtH;WFCLY&%gg~B!36b^ALBRcHkgFdE8V1di|s;oS0lym0goL>DkG;L0W<&
z_1O>sIEULKc4nY@M!i^7F}V6#zF}xEqVsG=%^=-~Nxz1Oj=1BjA?zYHeoKpj?*SiC
zgG43MQp4{=#G@hfv%eDqV|V(n_~Z9hu<{ecB1|m&a`&8LHwVtGmuka(|9q9#Ul9NP
zL)C&7dWW;O(0{3h!jI?gD3R-rcKxhc>?7gkR&@UH$M0-z^+@p_X#F?-pq2pK&V0kd
z=Mb|W`d%rluZkDGS9<#nZ~tWBl!LvY?wJiYxB5Tw<B#0o?2q4p^~xPspZG_d{mxOs
z0K!j>^4}>sJMj+}WanywI2C%weuES_cl%>EHKwx;cu3GALlU(X(|8_Hl$u`P1pg#-
z2vDUQ)RMWH4Q&{--hTg*FJsda2~A$oMTgs0dm0!Y2k-%u6h3U|Q54OPkfa#FH{k;;
z2M(7FG((3JQ$+feb?tMZQzC?}Jp9%0(G9@xFFtT4%*RhP*^__rOB-UCjj#3a`K{{@
zYjR;^qIZn#P>$1CT7E43!R@-rii;GR1)RpV>RC4R5QE3zcf``lNP_I6gOB`SJx>a<
z_W@OHue0{^+iN+!kyyO?i2P()=_OUawXwQ`zfd!SzalQ`ywst!QxfN6Dg)?J(hU<V
zDcwxA@v1?SNW-^N0ZUeCo&ro<4CbvF52POafftCL@{<S@5py#+*qQi?o+Zle)lcma
zJ@DsvBC=!MAhjtQ0_9>Ag0|#COvPqHd|RZvE$HYp#iZVdnZcQq&(8U*#$2z?+;K|Z
zWd^`Lt3<Wi^nwwL66GWzs-TxR-$v;?65rQcuz78Q&kovfxY-woK|s|>fm1Ye>ns)Q
zBFahBp(P#S<qpIIA-<IkBOQB8$klcz1-|Lef9JieGAjq8x=(#X2!KO@stV!+k-Jq$
zpVVQC3NK*)AxxGz@*RUqws7wiZb_3|mr7hWM{*UEiC}s|r_0<7zDd}YT*RcPpD#lR
zI<E7e3F1-2VNtI<sYD)(WQJTo{hAI^Yys_&jCRH)ZceXT_&tBcK!o5W|1R>$FKLo`
z8uB<>m0HjG$(8Lp)Tc=K8Z_G5=VDF|IUb7`3L*Zd^wroUy=qx|6ZhNM^E&0h%wB9T
zdmynp__ltzLHlf5ZYXLyq3IY>`<bisok5%>`&)>EAOlbgP}A-@_p|FNt{b5how}Kl
zUeG&1`ucbzupPBrtj8E?H*kq&gc{;HFN^)6QnB}LcdT#yUXFiJ@obss1<BVDViB{p
zj9MO~Pkh#qv=Q4D`UzKPJmzvmc2W^-bF-XK<a9>0mP!1B*dv-!s-W(Kr1ARpp&T<r
z<dy^P)kbOvsW3xtDsBSIgVe|nma+I`<>vYhXzDFlWBwVp|EzsL@#CF_DH7YHZ-3=~
zF&^Z)g{w^t*1E6r5lUW&ZfVoigCDd|(fDOOk4@<enVQin#u`-)?9$$K#8$7^A|+Xr
zdlUDUvN!FqAU(|vP-65EQRy35c|6j`$T_MW(6g+;Y4(HdLtVyK;)p-Z&8fxJrNm4q
zZ^rO{hzpsnx?+~uS-X(uzMb+T0oIdpYwE_Nh<&WoENMbMfPE0MU^N~y&Ke|sxt@Ld
z!mVY5lt$UH`)K(MVn0vyk=3~DOx)ldv6nlPEc<<<;{j!WuTa8T=%q86UP!F_lP{=B
zF2CYr2l=N~4o?~@+p}y=F<Uuj2qmpz6{La7zCGAtsC%*vwU4FtH|lQgI^@xRvU<1}
z%#D>${0`O2R%Xe`jBrFkzvOhGZqsQuVFpHRtRUxjrvYN;3WHhx0X5|p3Y_zO4jD6_
z))S-?;RE#M+r|GZV9`uG7XuiUcCKawZ8a8072B#ltz`N~3fP58A+CiO%&?8kz4sdG
zu9%YQjB!dYBk?0atO)Op*#3c7R&ua}PRU-)RujFEzDOe|>R$>=!yvr0Y(oq#6@5Y`
zNk0{v4Fkv=JO?Xx$a*S<-AA~%Ad>a>|F4@cZ6h42cu_}PLk$lD8sC*&&M?<VRSytJ
zfJ{dhi-&xYqK7zdj(kQ5HlyT=K>BPH8wOQp`+%xMQi2a)lQDz21?+9*&BdBAC4N?+
z{#i?tNr|;$f*;G<!jLTleYg;f>8)f1G7SaPTh(rV>o_twYy}m16zrI#iD2l?#`@s_
z=rF5~*y`K^j-YEY^vvLw<TTD4YIqL;wS|PYi4oVH!A|M8(f~DO#Wao_#vzjp3u^_c
zF-zP_ih^($kqAeHKnk${PtQQADSRlg6>A_V5)mU)yBmSx2O|mutCG-d7=!*!)?!p*
zK&NC<nxwdM9>JO^^o;RtMaB+PWl{G%e$AIaZZ(LmQ3y&#?9!zVhCAI<@iX1<C7br5
zsB}dQ1@hpuGcH;}(EJF*q1Lm8&#QwU|Ks=i9BZ85qRfWiKkLtK_s%#@9OZJHZV5&k
zM6TTuH4MQwGEg?tqS&s;di$A}>8g*XS{2FJAqlB1eY5SZ<$-x>{JL*7RtrU4N=`cT
zX5b&M1rb6qn`k^))8j#t&`mEHxJ{T>qyP;8dG99Gj=k0RZ9~u*6#FC!iSr6pSXao3
z4(vx^cT8`Np_erW&;g?<)aJFaBPgjzaYZ#(=K7coJ;byml;whK6F2CMtU}s%7YqQe
z$;Q>e#xRf-BGGK*z>4oU*|2PEUuO)#Rm3la(=j0~w;03jzz6O^KkCRJ`Y0?r8nSD!
z6Eod}K5@U#)E>!sF+T#mGP72>a5`<Ih|V!Ndm!~1;?Oz?s~~s#gl_c^b+<L5lXXto
zeTf*ux?<dqSZw!L0JCFd?=0uaX@fgllZNI{%p_xg5I2-%<E<0Nx{re=cZS7omFAf0
z1Xi#fR4jC<FagDa7Fi*?h(dmq@JHyjnw|<Q$gm-$FIt=QW&$ns4tYjtmX^8Tcw*oS
zMV(0uHkUDs7}NdOzO5CB2dt|52$L~C5QKi_f^91XVh~P0rg2%g>Qt?Po*vspe?&;U
z+0diGh=1C3l!=%u;A&Jg*@TgZVdp0!&CWMtW0uwwH^gP5fZQX0m^i|&P811_Heyz`
zM(IfukJy224{gCM8rve3x?Lc$=0r3}Q(Vd@jYj%VJswh7FXAB(CuC9Ah{DL)celo)
zlt`NFdnhHLtMN?&LS{+qWoC8Dn&kI0MHZg*F}93uTBF@I@5<CQe#lmJU-&L(T+T^7
zp<Sqnj3K&)KqF&;rUY_QN^XXfKqF#9C<d$B13}Z7j`6C=7CN7I`)|xjEAYB6Ficp;
zOlX!Bzkel$;9oD&<%GO$bj!Q_)4pZ(M3(t7MD)-QJ%Bk-#s1xs5f82P6<fz$(o~8<
z)Cd<rT*MM^Gj%1os6daU+vxB9%x8n)BE*g=?^}fFyA8rz)+8uM-%=cYe{A6QFk|8r
z5VLUv&oaisv)k)H{?tt^CvV3`eFr_K+dy@2NWmk_b0zW`6_Z39&NeHqG?x)<b(~2M
znHm}w8D*%%k~>YGrMePvi>q!J$HmdH$$WP(7GTt&VuvU!8+4|^yZzNzPC7+5l}4D)
z3N=gc%Xho$u@>iLHp=>{&`iWT-SVv%&Gf$*Q`)0Wdix2bd|jW3m5<tML`mBD^=H(!
z!d_bLP|PaTzhsgYx^y!2@}QmmRWr4ur02e79aBHsl3z)##`X|BT8p>PH;?6=H6vU2
zB{jaJu8mD^AKUG=&}shCl6sx}A+6iH+&z3Y@Tc^T1z&ARo~gCjJ9+EfW4xHAGrQID
z%~vi2N9Sg-ZS~Fa_3YBc8`+!gSx&}BvZi>L&`zW8y8V|{jUO=7zUm7HW2p;25_gi~
z1H>&t0fhNb**{^~R^kDEpfCRX_Rg5&u$ED^d<ZFi@wMIo{*m^ql-@tJGMpXFuEMBG
z&c*g~Yrl@nkwxQz`i8&Sso%T(-ly916Y2P$)UQ7R6~JX>zNYWdBlgS3=I1{3QfGfQ
zWz>9ounQOX#)C`r0@S+X6H~3D_1#yJ*uJgvv4e@}*sipF<od~up~9<lzG3Wze*IM6
zvDusMh3#Yg(|oaS{Qo2EeZbo|?>kRm1Us;z=ExC(ouEDj^I{0S1RzR;7(WO%Pr?}t
zsR0O)5~H}RHcv{zv;xa^Y%6Y7@wRuE7cZfgAVf+mqeWa_4uoI@Rv257xjrW6OGTKL
zX+^Ok)lJo2w=2=Am-c!SNl{%oyLY`WXeaA-yU*=CN6Q2$;m-gw^UnKzzu({Im+WIK
z(Z%~zxxbo~%+K>w+UVEXJ+zCeFPLYv|10-)*>2q!MD0qN*$BgpA;4_E{CI=ci`Gy>
zh_4QqY{c&7*Ysm4#6~@PtB~wR^!pjPoH~@x2fmoPKd<U<5M;xKQi;a*1JI*J?5FGa
zzW6t&2Ws58BIhnaQ4bDTeW~P@94d70x9tXmH^=diHOoj6z>=$@#M_YC&r&C3(9w1U
zV`va%K8>YiT<8sN0E#}=efVzTwdCw6+3RUMgQua^>kW<l&;R@?^w6+5#a3*)+B0@V
z*wrr`QT{Bl--AfF=x2eyReU>5Ow}Ljy|rJHUlE${fq7wt&eB^RuXf;G0df4EXy{h)
zsfW?qXV1$62Zm(2(+XFVxyP(!9!`(>epRi~*Pq!_30LUY<#&+gMyUIdRos#z5SGGU
zoj@<H>Q~8civ#a^-Vos4TE4ebh=Zrjl6%F}+=~@<%Oii^>R%#L&)i&2LYvc9p!K}~
zVrsG)7+XfKEqU!oaiITtvwe_*Kd^5^?JM?$!e8_~X5Ow=eP_6Oy%!nr=KiG{v|~Vj
z`=Y3J^d0LfhE_hc!FSV0K1vTM)YV8-8;>eO%ZAaS@C!B1nC0^At?h(HFOBUZ4(~0i
zpN7(iJg+bVid2KqJNcl9t&=k3in=R*O3K|V7Qy|T5(}C%Wj6z}Dn$N=c*{@zE>w1s
zSLVqrN<p+JhVqD!dKN^jMj9=}Dxuyhbe^0dPof7IowDCgqGsP2(5|!Gta-qMgJSX5
z8_131C-LoBh_}tV_)aS(?=lbE*??7Se)6+Cd6EnyY!rQe2aV>c_y1U2Rc{)GI%c6O
zy@h1(_@0Z_5M<tW+vaqi?%G}ZiDh)l2!Czk^F;FPAqP%w_70{46{0=h?n16#Q<Ysj
zAdCf&VRnq&Dsab?x(6ZT9aHq1qKkx962EJzU1_0Nb|GeVo!n6danuIrz^4m01XM<G
ze}?wH{e`y5=0}Z6a3bJyCS6c=@1Z@9^Xiw5^7c{R;WK=pT9|DfuwFE)0p#6JcJ!5Y
zT1kE_amnQT){H0a`g<-#9%IO9lN?a2V+vRY-l1j72Q8D;+nxrd*!lfrI0$6|5*nf2
zz2v}UaaqIBO+tei6>0m?M`%e_c4olruzQN9NOf$XdJ1S01flJ@5;^UG;#`i7gZdEU
zV+{gDbJk_s*lXCqq7ow4fY-ubj=9O<@x#b;X=T!m>0U^t)nHM&;A)z`Ui)W0y&CG0
zF06uOEgJ?Lt-d9H<=6!jBwR9A@17g|#g{fA^^IL_IkKAF?DE}FeNgxwSBA`Tb8b)X
z0P^d0ljKto{vObs;a;4XI73xP%4>N<hNCZkc~tc;5FA{(o3_YLKdy0Xl2TEpRQ)>y
zf~*tTrd1iW8|YfVHh`IZLty*MAW~2Qk$7tEsWcMX&6Qq=>({h~W*&h;dJnE@s41w6
zB&t_{;Z6CR@zoTN7S}AaF$>HVcS4zOlv<GZHPaPh8Pn*>xkK+gxvSiqbP;ZZBtP1|
zA;~*pYe+XDhrI`<j(N_fI$Gqh8i7WxyV@z@?kefIx3}v=;PvI9Q5BXWd9;BH_8Yet
z>!~7z2h24NJYZ_dgs{`bJjIZZ1gQqxmmYXBz{X^yu{Ed)S5<`D5q>wZivz$`EGbXA
z@gAbWBJK2uD7eq@!W@G7JCmUeg(CK&T_xp`UM37>1tV5Z)%;iYXRm2hT#+yWnY-~S
zJ!1+E%CVuPhvo-A>2_$}Pi`~#o?5Fc-7u1>+!Q4!beJZ?bQ`7_6#*XuYIB>ACPfJ5
z<LsFN8V;h?1jRGQaY*^j%+!GXKz~6&a}{h503j32=!!Wj7-HRp1tv8tn{p{HBjg_z
z{#kJ$f~QSF%?4j*Y02l*zh*vhqPef}*qf$#>XZs#2<ieB%uRHX52WUTK%iU<z4x{L
z?wZ-{UPlOLo&7yYvd2tnJ?^b$_pPMm(6;6sTB}5>t(r?wi82oLdo$5mZ9u*mQ_CW3
zb)Q8i(l_lzPL(G!)bX9CY@$q*(B=rMSEq+IEDUUR_&l~z_@VI9%6P<0CWWJ2nZyS-
z8ag9trf*5PdUy44N8jiWJjzB!-h@y-mu@gmOx!tHP2ZToAo4d(v?a5F%&EwjST~zC
z*+WG@ZT3hL&8>{-SJH~B=Z%w`jV!iG-Fr2xC>8X7{9LUg8>`5NZSkNb`!0dxr?j4=
z$^c#D0d~#4Lfl=IPbJ)_gs*id!wQyxK93u^yI&fsBVu`)NIXkayK2AyGtTiZb084%
zTJsydcOErUL3Pozj(V&E<coZlnUP@!@mtjs!=hCpn8#(EyAei*ntHSsGgle0cFYpF
zZnP`%2vx=#nRBVt4mcx3vfF}bdlcF>EO|d9uI^2g<Q5Iuu9!LyRUV2Gu^<BQCz0ON
z$l{V8K{9+0tr7r_2!BL}(NdkqYcg2FXsl-XCB*G?MCf%&O#kgq4gCKm4S(^s|3AZh
zLG}Fygy6M*k`UZ(P3dd-k7U|MKG52|-Vd~P#1sBIo+bFvrfUBLujBunGn{<l)*W>u
z%bS3AJZkph|J+`F)NFDY-OFZU6{2s)QqT0by79;5KxWqMz~2K1E16i~V0q=pau6h`
z+d%3Kh~k=pr4Iy$Uw<)&z`7JnkAf3-%C70RKl~R9w^-}_=Bpbks>au^v*+0le{cMq
zfBk+Rd~f{z;TJ>?f5&&TZOu|~gg4O_6we{Wvt;qy?|T$-Lfx(u9y8L2eFs$g+G54X
zju;j(Q+FjU6BZgYQdsO{+IXH^g0?4zj``?T8FPPf3`+Sdi}iV$mdLKNeY)XDA64Yz
zLUk86rpKl66R{}C_=AfXD;gR<v6y7<F!f_uqVdcaBEO&*tFt(vpj~xns1c3&f+q%#
z^M7y78uu*O!A|wafAY_I+MLiGW3)Fm<e0F#V?$V}C{*{lXH6O>&hf>&9sUi;Khn$_
zibjH(q2a_r@rhH())g8d56nWq)JV2y8&Zo2r6s!o?3=61oyob26`v!*0$ZDFt;Ao^
zzd{gcqGb<dK&e1{<t|(*u$V_{d2HS|smzAdS&)F7lub5g-+S?$tYNuxi<W~NrH6I1
z*S)<l5V#8J%ygsMImwtl`Kh#{<Y=81TGNt86O%qZNt9N}|3@-bnYKiIQdGoJ&Yqf@
z`eTxmEl$jgT?!Cfs#H}%b{yMl)HI+-$8Cj)Sr4MB##P9@NVtM`+fdpXqX=gvzh|$N
z+K{^Q-~Hr{Q0M49GW2WIM#B#!MdyfZp{tmGQSm}Fh@3DcjB|3g6sdRWLZ{uI^Rx;3
z8O-GGu%oH)G{jLU6hr$(Cp}Hn-?~?8rX41nh~8C=MOo!Zt)_x2;>sHCZJbDmefqhb
z4?4?nZM^fssw0G;mt~Dd4aFe36}O`NkRhwSDnIo!FYwPlRg+ob)>Hl4J*rKI^EB7o
zMT=6tuB7mpB@AI?bZuPHw@0E5ueMk%27<?zh6S_`M})X-NaI;21c){#g#06#)u-+b
zMoBqNp~eBcz%^v&{X}E1A$ShBL09$|MGrzvNuqAbL35iTuvIYN<(%-b&MMOxjv{Ru
z&7M%lTrFnVFn;ep{Z>ow{!yEdT&wJ!FmlpPI({rBw>8Hsit>l8G23f^<H3%Rcxy*>
zo4rD+TH>#a4!#?Kc+=Zi0VqnAyIkY5a_uTpM>Ki6tk=*lJ=&K5V!OAdwwvjlwlYk%
zv!rlF#|a@WYux$0I2@!R$|}<GX{DmK;d0`QC0pT)x_-=0z^6;5Q3NurS*eZxAyede
zo3rN*)e3J}b>3%}jpWTg{5L-(6{CH~7`F$hnKDXB=zjfeoxe(hp1o{W>|D@Wl~b2A
zl`!^FFHNXXEvzP5cc4Y4$GA;Bj}li4f9c!P4JpkLaqDeqf{%Pwh20WJ$6E;TMgF}}
zH3Id$<Il??@3gE^_V6(!D76pv(@4!A@^tQ&Tt^*7eqJGmzdJZi_@?9;g!{)ATT-*}
zmeJ75u|!;%_f{f(G!z4J=dp!}`sXd`<@-tQb7tlAtDgWy*x^_jwvFz+mSelec7%{l
zjyth?6RHXk7yqiFF%(fRHA-2K_B~0Q{t5=rvYN&D5)El}V#SXEHVP@#iDRXE+R9h3
zZ6P(SLgdxR9U0rG`x{Z<Hr1YmY(`V;&MZv1vIcP>U-B3l-uNG~VH9YvP8tjPHgy}L
zMytEjLcOL`?C@+~?+}2ftL#cl%SIC-ysn+7?$Eu=a0gwEY}C`nnx(A0!7mXod)&G~
ztoEeO4dMX{BB78~acwX-EJNd*LJl~IpV<}ToORR;T{m1qeX=7pdnlE`X#wiHGJcoo
zpdvoU9_@49r!HB;y2EeK=@<f?**x#ih^|KyhP2yiazn4uzfo1?tituWCrd?}YT&|v
z0+wO017&{)(KX9blDI%v_$05|L~0>rkOyp=9Zh4<Z2U3cPc-9QARcgzI!O0j6ol*8
zIk1`j*PnkpC}Y;-AaYpsx>&cOT+}e4LZAwbsE%?R6$D7&AG^B=!-ef^gbUg(aK$uL
zl2Y9QOr^$dv0djhIbWr;AeC7`Tdbi8`ZLCK&~4!3I#-&&;LEF)B_hRTaY5pG6W^<)
z(65H;oG@GF#NoS_Z-;o=t=!(BIT*HBX^QZ(5&LP6o^<Z7prsgbBCBj}XQt&a{6Qy<
zk0u=4_!Q3&i~;~nO`}GLZRRCyH)7q}`Bv6P^`lV3RDdv~?E;=>h6QM>GA;#6%qH22
zx}7OZwZ|p@CY41{e1(IP*mz7zYLhQh6iBs=_O>|<Yw>RN_QW?d?=pqN3245f&mOj(
zWP*l;m9YvH8W1IhDhC!?=1Na(S~yA~O!L}*Xc!4ac}CL-9ITL?j?*UY)`tx(A$z=@
zPBS49f|&*;4b-t*)+vP0oXg?E=UQb^4CV#f9ieG{jt=8^(UF<yc4a$glfs?4!|WZ6
z^S{5fv6prx(}-v1?(kC0<=;YF_np@oEILCoK(WV3B)g!V`z3vSLJ@Ljn`Kv-d5I2_
z#Bq)^5mVZdG1Ou8QJFm+C6eQaY_%GLbT=ile$@b=<udk>A?|3+KmguiRhkGrVEIk$
zW#;g8@;ZwPcm8vE##o>7+T+7EDw&Ag?LMkil<{WQBIHYi0&rkUj)q@Bk^ONfyEW3y
zC9TP&>t$s`4%@OBH##-s=CMmt(;79&DHo9PT-eak#W_*7y50T_{td-MO{<AAcLbQ!
zc9+G4aM;2wGkD6|l|EV7?roBKd2>yBCF5u{HWe4~!Y-cB+@`;To^{;sCJthTeX!n8
z-_@Xz_%}9AXEmZ%XCX{G8rw;;!U^S=J%EOdC{O{K$*=_i|J`m4=h#uDJFOXx-VAWp
zjkNzxVh5!yJt^tv-lJyHjUAXiifV`8JFOMnq4U2!i0C;kaQ^GIT=G=nrb3&kQDs>b
z9qdq6$6O8@0V2#L@rO0QRj7TE6l!AFX&h9bjXU&mwX7&5t8S;W?un}5fQ5tJ3se$Y
zg#(j7P7R;pMwJ2a+mcKIWG~Su;e+~im>j<tcNO^TNRhE)mSO8w4s)R@kF<}q{u_@X
zHtLaQt0B#ma|+}PMCu_e#g=&)Rt7!lf!BybuG>YKs)2hYp-4hKjEOR%e%CbUN+?BO
zwtcPG+&J>m!eJ12GB}@zvvnrqs10j975j)L(0h7bc5PuAnvj(W;kKVLb~pElRpsV4
z{<KNEGwB?c99B@$czy;&eGUQm4tK_-f)gV{(str+x<@S*KjskuX;@D={nBoYVH}HK
zcRAE<No|tk?S|3H24M(MwTT@>!A%g9LpiLd%A*GLRE(UqGDgh0wQpJ37o|Q+yNhmR
zNh=>|&e)K)*sIJRgRyw)``2%<{h^!pK>CJG+D!M)wwOJ?vgQ+AUrsz`jfTI`+1WS$
z!XLm>JnLcV=d|Q4O`cAY;P+%SgoxMf4#i@5&vhE@^o|<Q__sZkous9@Q}tP{c2E3y
zZ*;z$Crac6a?n%pC8V9|QBQQB^&NVPr{hb(zUhYw>eJQ8*18;8lUKLch3A#C^lud-
zc0SEd46^F@iWtd-R@Kn|4Pm|J*=EmM2kWKKgeA7+{<9nzsEk@Ky?k*X_*m&4&x6w~
zk;B$b@lwfr=;E`7)x#t<Wqk9mS6*2wlK9_iazB62vz6~^tiyQX)Bn>3?+be`SJaQ8
zHfKV=XD^?!&R8|$us)I7X~&Hhc*j%zM4g7*8m2UrndNrR_-w0Bu*<CQaZ>4%gW4*=
z^j44Z&-1=%WM#E8n*F?|t8<e0ujy$uwL+aiLY(iVlVSFt)-&xnerNr1zkKlL^2#=i
z&Ds+x`${OcHdr9fsht^bl-g(8MQNKh>zkMkyvOKRWiS^Up~b-EVA>jg`((#lpZo|Z
zb?z)oS=VaOyYKs1@PCZ?PHgUKe=d2c{`J3(Rv#h%%iZ~T@4=ZX){f#Y{&Z6de>e$|
z9iZ3N!)*MR*+8xEzGU*6efig%=|-}BycP*{cp^(!_yT#^=wCP40HsXWI2%(j9*g1|
zkb57<<*5?F4*EQ_a`{{pQaPF~p?Z6ShOQ+V2`pkfp06MV|E!UO)4r|Ise8eKHi%w6
z^$XC~uY~YOTr8oa&DsceHe&FN+g3#HCyhoD{`N^@eFN9>>5zKU;+STQ*jvx9qp+Vw
zXzqjNIqN8Fyxw{rpFVWjd#-)MfO@mHH@tsBg#Z{e#w_p)qJI~QeR_GpxGn2ND1F;P
z&wi#wuJ1I$_qE7VtC`+VnntRO9!5YOP>mB%!P8y$El=jdfe^dN7?Q!w_Y-e}`|uX}
zhiL=mA;2mk`di7`jyTAttQi?=(kFV{6q?ledf)`v<=w@e_%7L8D{lKFcpKr@!pOAe
zL7Y|*p$sqkemNsQr`;x1-wtR){%h*BxfhN1kjVu&B}{gIAo_3KbK&v9OX6m+@W|I*
zl<RUFX2BlcWBK=j*B>qV-sycd@cPKwWHB7<Iy>_h*WHKhiEjfMy#LelA8YY&HFQbn
z@}P)3W}Xa;WitK7Y2`7#GFofSLP{J~U$2!$Lq=L_*Fu+zHBP&3c|3h)NYdjqLIyJK
zP(|*!mnc(q{N7RdG+)!SP+ILd2}#=>I<;fBNxR+z+*97g`arIguUiWTzZ(_H;V)5*
z9?09YMs8Tk7a)#~RLeU+b1JMcG}Mau-lj3*QL&1TySZnDa<r!d54rMINF7;@qcx-N
z!R3Ke6<Cl0iVBY0{fpElI-vi6FBnj0OLr&eP0xM1M^l~Y2FJ#Kn<6i;?<NMG6{;;N
z`AToN(>G#Oy2z!;h2TkY!@y+u6#*T(r_%&;<CWTd?vNoNyxlX+0?xw1Nd$8TPzDx~
zTHnB8#)07OB+sr`ii-{;9y4Bm|I+gw&v)5@)ktIv(%#R(^{<`kVruQ@zBl3VfalWj
zq;Pkww7ne>k1H9vO^a|+yZD4=%rAXTKBBx{TRYzyk`g5jPv{K4UAazMd}9rXekyS#
zshuQ!-|o8@Kr_GB_4iE#;XA$n&_$pGJzjuf!=(G?4}KBHYvUMJ-~iNL7<5ethw}7)
zUNIe8G)T=yiaRY-aaMyj#N^gIbmP4QQm>P#^6uWiEQlYFi$_rIT891$LQ!RNpU@ox
z`ZLSn{Y3AXA8eHhr9sC#Cr1^=6!|$mcdF}6d!!2gqM*7-q+}RJlnC~nMMPvS*!>>s
zO+twm+l*(415_9F%+iZXbg<S6#?R%*H%$&B3P-+$cfNRY>E#>s&zzIDjn1blJ3zJx
zj=95T^hhk<S@->oeT;|qhwp2k$4_<mn&;CIXA&Tnvom0WhkohtlzY2wau#rtU3sLv
z2T-g4aEyK($6nT|b||eYNno#aR#A74h6u#^lkl229{?9bGwLkaN>;V1j@L|{Y-Xo~
zvC`n);FvT56*T%pK>)>QKykjEmjMV7po+izR%TvqUc*u*yaO`su4+iybw0ejyH-wz
z4&ME<Qws#|?f4^^7eC0(7i#G*+`6mB1-k=pZU2}>s^(NKURn0tk*~CaC^L>zrt3a6
zReLw2GZ$%@xq!ZO5YaVdw9QRfD}*(U5k-F_8IpFJ5HX*v%1sp#HCwsV;_X5H9`7eC
z47wY~XL+g3i6Ai=T}nT#K*k=d(DJAJWLDr>UWLBDWcXJj(Ej)ExaNHM_W3jrPx;%N
zhomi$HrH+nsLIOnUsP)Q8}|)?Q+4>&^60kJO%dHA9Z@t?;xJ>-2=`*=oMkT#y7IRS
z79LT`1)ucQ%!3!o&8qrSlWI60I?eLt*IzAhM~|1yssr>2Q5bgAzyU?-!{@5C-a1)@
zd7>XDvNn(b9dGphDxo_mlIfCOh!MgjnGY9=LQVD8SjZr7YKAq{Kkf!e=?8`f{!9K>
z21}Zl?QRZ9s4MxB?<N-}R=DC68T(5NnkF4{hg`Y0u}fVo(*yLyG)7Jz(CY)oKF-@T
zm#u|^q4+JsFnHt;JE5Ip+b~aK5b!VWUrnKg=aR8$x4Fxtq$j2EJs0y{h8iA~jBZid
zh<<NxKr*)i_#<sgZq&B&FzFubRl8eo^l<(N&Tk#d#;c0hu$?uz!<OUwh0w;I8t(Ej
z=D%jcODuQnhFz?P2%ROSXWz+Ydkd9;;+rE{uk8A%fip#dY3&+=9rGTIP1qOst(Jjq
zM6EV7N!9JqN5x)Q?e@;d-3xiwZjyjYwl$xSWFtgIY$N+7)g>j5QA}$6*RrEkLMehP
z;#9Lbf+-NiP}N)Tuo0bwWk=rGEh*sdO)IT}Lm{VFG~`QlHH3TGZu_SmH^+uIc_c?W
z4wRIrVBIV4QcP7z=&nEcKR<E&ub>C{ohW!sXxbO80i~*e&eoSP<WvbGYYJT@(3~QB
zO^<O1Z#+o`t;RIKjEg{gFK{v@YZT2r01bbAo&eDIh^{yC?7GA23F2tKGb%oZ#JiYG
zhjgqQGm3YavF<DBq6GP$7;Z|&*I2_87+=PeV$j+e2hDHUKoi3UGq~G=i6p`I^GUL@
zcxaMI#Td(8vgoSkvi33W8~=bsv!-b1IEeNd*4lC7ANBTYLvO!-0Dx(kTc^nUgARco
zh0(n50RU#^g*A$h{9C>MG)CrwXIXFVhhY5*;_d4R``@r=K5rdCso=c+Yx(~-M4LvR
z!L69<eE*BMY0PrI_}i_aYx??a`%uF?fH$%3A{_tVExq4(OX!_A_&&1s*qCqq9^TSd
z==c8|yl*_sdhf)S*D$ME2jhe=*BYAYK|Viu>!EhP<p$iqjsD+QQXv28#DdJRh_Y*}
zy0J)w;Ge~E0ym8>TDGA9U}=V>C4RNAYR3(fk*tbG;~CJ~Qgvn<i<1w&x^F6P{Q75y
z{^3t$^*4X@kACQG1ew;K2(R+de?ycWFAQ<S;duRD4pf+;6gv>>%Uvd(#}&`rS1jj}
zjAkwO854t7dq^N4g%+bYzD#{vW?Bmd7d0*TjpB-RIsaLfugg2zy4gy=tonRWtt}lW
z9)qOrC#<GMusD&H%Zwy5p~P9DeJ^MDUBu_|Eo)Iap<3xAW5IOZ2rxCkDm-(61WmTd
zkd5SLEtaSgQjqD1e8jGffz2q(!$k{<l&3sWRzG<=Jf#tY$%_#F(v@VL0w67)zMI&K
ziXWTpp~(%tC`DFr1EG28G|=9JjEG&BIE^?6@#jWR_Uw0V#}b#Rq=UTcOi4agUoJc!
z<Ybm&6SB@MW-ViqVfZx($X2yt7$J@2A!9hoIzQK`1#7LjvvOS!bswv!YDDE#qY2SC
zroQ(dBUzh_FoY)^UfKLIZ;GgHzvLi;rcXNOi7!U=sHt!5jIS7X1wm4s4$f5C(xK2u
zo9&e%_ZtaHE~ELZ5=Uw<OOI)e?2+l^tfV3I?(m<`2Cv#^IY6`=FQi$Jt}<-~hmg;m
z1jj+;WJyU2W7=QQnIkl&a)G2@9uO;q95mALn-hB-(H?PLDc0|4O0#D+yF<;NP>&L`
z2N8B#hvXMb&&H@N%U3NjqT&cNLr$MzZo=j-My}a_Cac<LLnRA11NuC29Bt~^-q>i{
zXI2pt^%OQFXYFZTX;q#CG@zj#b`y3S>w8T)in!US#i3k>Ha@Lg+zgT#J`fvM356MD
zZG7I6<QrT555H43q1Qspij_4vWv_6XNpU9`u$fM0HIzIEs6gjpj-$SN+^EPG$g?^V
zi&`v3OgX-x4fPsr0jWTuozxOt+B6P(Y$362XO<W>)yF?pWUi1i_W<ug1y)XF7`oXE
zu_7>5z58uAo)A(3iw03>HflojRRwze-TdkwI40za>VA8CP`gKpT(%4$ZCQd!d`qS&
zV^hesUy|j4in@4cD;>6(S6qYOuWkV4%tMus{$(Cl2~lA!1J*3Jdo;(O<~Vgmu6Kr2
zE3DFJ8#&v%oK7A)6eY?~K;1B?6gnuI3htpf+e9bGi8g!4*674w+XgTjXr$Ho9b-bz
z4O$n|^#L2nd^8VK$TJm{IugZTr^Uvf*5n(P|FG;yylIo1%qzyzu=BRq$D_)mJf+8c
zJ)q9(eF(VSyVSXrw$%7mYAd-nCpuBn@TNW;i{E$OOU6^$VFM`wnY>*0DXBV5Eorpf
za}P-)M^2n%*pPK!r8VOtFPTA_PSOLj9uiu#n%LM04_uCl8W<&+T9g#YZ<SRfU)6DV
zhmt|FPuof{CX8Zo2G$o%#0<Gu?^F(<Wr^HRTP%O>LQQVx@yYjI`{xj%Af3?><e1Bd
zHqQ{ajjjoguC~yfsyEhPG$~5AOO62I4zvmm3S9}h6H6W>^0lml0|0IyGNCs7dRFlO
zK;vrD2y@vv@ac#kgg6kd#|hN!#(i!7D1)w-HC%QCP%LNAf)vdihPCZWDKg{n-MQTp
zl$R(7S}M{6w(Mp0Sw#wvG-Eb_XpY0Fu9<PKYZ11DLk)OFSqS4e$}?~(`6bi9(x1iM
zdbXmUL+y>vg{-(7VJ^e(EH7fnH-a^d5L8SVIa?J8?Nu#-QlV%>^je)BY?~qXYG}9t
zj(^u*Ie^BNvM$a~d$bL0pM`vP)iz-Hp&_fGmt!$tV;!lDusROo6JRp<`W)nOoDNJv
z9v&EXxf?tP2UX!dWNlUQW0asOv`JaPsMxr2q~*{iNSpXrOt`9L(4L5dk)*Ie?xXFz
z@^_t%VKq4jstI;cTavhwcuoa9XQxS%>_QDnw(${am}C`IZPB`_VR&*9k#+lB223}M
zSQ~{Q94$+bXQwM!cZt+k+49zud~AA)DA<-nm8&9(5q8xda-&THMRPbKtGam+!Q730
zH{$uzWx8F?ILz9kKlrUs$28RHoF-Y8t|!&&ZITiAeT&>#R;>w3p@VIzrfIHw-Px*z
zqYC+Pk{{xx*)#(ZP_UwRYk1FaO+ALWpPZ9*(`-X%-Q@@WT#DqR*@#3{2S%)|ie_hh
z8v{nHQLms#8dOw=wYxF_bX3UiYIA3$3GHrmZQ_6<$xPP(mx?wJtInidvCEtuP>Kqb
zsNZl+aGDgec7(gV(||seJrKa_?7O;t!eu08Dpz$kmK^d6qY*#9Hfk*e$=48KqbhYD
z<>(IRW^hC74NcIJVN6&kDqV~LQFM+KAX*M7r8ZTWreU<Ikh2{E9F&^jP@zRrq=-&)
zRl8lA7&cX#$DL_MV&-u;KrT!u-2zSO$F-C@l~$X~8n<LCC0yqibG++z_?HU__ps%E
zJLtrjr4Lh|`}7PMu>$DBLDH80FNsrYc*lr;1I<L6N($GS(4-s4Mt_>oCMeVbmZw0y
zNTc@zmiPXR4yL}~E?yJ2ewE0&{H@?38Pv#|CmF8TvZmlbHBxS|)XIr~s|97aY}-RD
zJ7Wnm!MWW7H^?s~Ew(AuDO;oDs@{ofH{M2B4pdkcx%iOkVhW^oH=tH!mUEXeMmE)K
z(S1tJ29Ox!jWQVd$aFWM64_mGbhDBsz+8Rt$t)RZ>{uNBN*y~MrjlGTPpF#g@=Mt;
z4xp@*$;L%a)lDwx-5$+}BM2@Rbq^a39h!3Ms6HGHU8fuJ4F`thFj9#p(I7%12ypmu
zu-aNyS!Tl(dlDO+Rxt#{{HO@XP_EU75lfS-*WcghPumVs##Bw9Eh@nw3eCL5l+hR+
z_h(#Dv$oUkVh)CjKof7A{}^Zt<*I6M%tC$c63*+ph`?#rCICp1L=$o1l$4gUZn)wK
z>%a&nG>m=JQ9@UMEtVs|?^yc6L!ZcN+=b8F007m-$;J|Cp%f&XkvTWdR$|k}Fs`ph
zIWrwB2qrU1TS{_7C{^1$$|KA&T)x#2*<3=-AEmt^w-D6A80E;K$ullgM`V1W#U&Zc
z`l~d@?0mDk=?Y`e+U=mcjG04d5#bVR8FvtK%sosvBdq&o*WE}(S&f}ySbBCA!!vd-
z6OJw|uw*DljO|>_YgJI@(ZAIw*e2gpFmci0s^rjzumP4o&N$KEz@Cyv5Vo+kklpM5
z4GV%A5P%h9ipstwM>TPd(ZHV2Fu_=$DH_YpMgsI&!FHZQ6@bPaK?!G@deqYYr1*(}
zwrcC#pIgzpr_AY0#!5uZ3o9yp+UiPGW*(}{kLNPECy!SmwSE1bv^Md%@wfS_d&mFd
z=<H%9zf%8psg>7~zIRcVHeviY@$Rg$Q;nC*t`a&f_Su6iz4v^>lUA{kWV@#0e;RzU
z+LvE#VJ)Oj?u)fn_*NFV?O}rfc1)&i?AvFTS@E61nb7;wr1-lGm;7xNy=G55y@ghu
zmFts4Otg*L?=X5{VcRp6>D-&bUY^#zLLw}Zdr3ZW_LdksNTY|wFVWR!NO1*=`)Lt)
zvN9lEu-1hBdP!=(H~sl!{N=sWu*%xkJc*Ue|K_QTg;x8j_Oq5RljzFyof<hmKu^Tm
zTlOz_g74G4qVV)kazV*h^~kYOSTW-K2Yh7d{O5cxbzIT=?oM>bO`V>0@6HH`M>>r7
zeWSt7`2^iEJD5llwuLfH5A3+7?Ozf0FG%4gnZDdg?we?-<$g(+w^TcExpIpR21}uB
zY{7Skh&94qz-RyI!U7c+=v2@h<`Z<<x2lqFPEVI6X)$e2q7O=q9ma&4@d!REae|$f
z+Sw#2{)!Lvi~ib6A8+BidLe?NZ?&0BGbI58O{$h`Xzv9`@2F~QXztcr1f1rQ)vtwa
zDln&vacJ*Cg9;_K(825vc-3<ldAtuvIk>^<9R==}(w|#W;>WO_xTb$I-;my6oET90
z^+S0^>inw|iM=f$)Q7GyAl{YrSDUggp}Qy6pHCyJKV=^(;Kp}|omv<Aw@}(n8+pKW
z=6mSZ%y;h<Gz`Q;wz2|AuRpLwe78mk9#_$(zyYXPzpXv@N6yjy<bfCHSr5{lT_=gQ
z#SHiQzHYBXRzG=1{+5=00+fu@9BKPI#drQ!*RT72DST7aYQ=X;dGg4`khWsIZ<^_@
z$3*`NX-(=gy8w9q*R^e5d&q-(ifz3M2N&fFhqQU}bn{mqdaw{0p;r4+*EPC^;)JvG
zk_n|Ay6|^q9?8tz7phM`l6h*-w;BH|>wf5@;jepFinU63<OY7e9=bInKfOk-LnsB>
z{eX9s)|PL?lsuyGJy*puBHWWZV~clz+M$PQ+d^|+KO)y@c+ZqNYlZtm2a8uu0TbVK
ztyZd|k6`}t`4`hCJ0_p%Tk3k@7tR*B-$+9pf6UaFahdRwfnE9YWVWN{t@NqK9~Fl*
z4OE~bY@mOx`IXtRP?dmiQxr)8g>^YiUat)W!#l|?zKex7PvssHYy5oplL)>SziNcP
zC=VM^-=*G6f3!um4pcXfZUcWJ@%BS#s_A*moKH)Uj`M+5slN`;&LY4g^9N5fL!GP3
zuNf79GPYHr_%;`A8cZdHOa#Rfc15(oR}kB@O?;9CTt}3#)ySz%R8t5MUx~y}5b#|N
zVICxWtweGM`SnPQ9A>+UeMRF(&5nnAlP7odEF0lbXyTFTzw{r<&kx?Q)7oN%y%WuB
zAX$kXHNtOoK|Fkp&!_Kv{nc-uPv)QJ&lIWeAkGrjmOsev4dRf9p|C)N_hPI2-|_{(
zQ~~APsP}91sF5K(cdEqq_CpFA$!v*)gY=;_g9WNPu4<iwctF@Zfaix;4EV^!@Tt%W
zDhJT_vKjBtU-{H)j7-@hw7(uoGk{7u<%s|Y_ozh?VoQ7Y9yAOPm1ZyK@fEiX<zAYa
zeZRj5NpWUdWWfM{=@s$XQgZ(74e}!yt+J!%x(2X`v>mFtxz@|WdUoObi-S84agf8M
zFvqKZUAa=|G(s!(S{*!-mBe3|RgF$rdUcdevIqDrg^v9YNqL`Mf6JG17AoqE^Z7nZ
zrUKPb0JWExRW7AqTs&}z%otFb^V=*uH;ag;5qEB@?U}Nj2&HT9R7q3CK%K*r+vtl1
zmkRU7&qTcuRSp>kS!FNM>PX=3Ri=da&cP|$u2p>T75ZY`#pkN~5x)P$>WfB@TrpiF
zZ&l5||EALqjepRzP}*UJs_IVb5v%qknT1XUl`+b`2;b|JxGatt2dd3ClFQ*y-->0s
zX#S)~a;bkQ2_)4n(cf#J+@LVIv~NQKR#vP<jz5*Bnw6}okt_Qb($cP(ft127n?GQi
zfNSBsfl9|!8k2!v+7|j@^aQ9jA!!@M@rvRAH)uF(g?dO5VJrEKScWE_B4u$jI)yNL
zSUjpM7sBL;4d_m~Q7bp<A$*n1Q{$IvFay$*1u8oxiw%BJ&;93QEP{~bc32tY(hn^K
zXPdzQtC_nm7TjZ3dTYY>m||6e;I<rEhMj>EJmlKN0<~U<%Kh~K4y>N*w9^2@DW-)#
z>A+xVKOS^>S+#e!8E~VU=dz<mn<J0%Z!A><UFxd#IeGoet44kJ&_nPyG&BJCRnh{R
zCNM*k{ECJX$oADPhDRGJ`hmS-Qi!lQwjeO>-g!ivs*!B%YrCl$-tU_|HdgB;Jyp@@
zd@*3TZ~Wn#jz`Q+ta3rSGRLez(sf7AaU<Z=+RcD#r!`=~P|>dR^2@bL4LJP312@@u
z7%QmoN>&0pGY>5o_~mEm1>;sMrnSnI=Ez$8t*(#3oum-vP4?hJAt_MRe1qm`a*`;0
zMU^H-A{M=|ggTWS;x!|T;+wPeB8;&D-8fcB9oW<&C%NWK&h?fRoQT0|Z8#xEZ5%MT
z6p$L<XIcyCv&QeB8h4}jY`wNLtoEKYT&NN<^9Ni5%eZN~Md>TB7dJh5SM`3)b<R)~
zt<59t%yhQhxhwxLQFohdF74r^ucj1l{d@rR1tW*}G$B2cRebXRAas-Gw;Ev*)$@M@
z`Fo920@7(rkC#J4dU)x8)U(7;c)$~`Y|RRA=Yy#yq{!;sc$@ZuF^6g~DD_&u!NAJL
z)UTX^@{+6)2TPue`fK}x=zF46N1GNv#d8%FDs$wVk#t2CFCGA{Ki>-=(VUfZ?c(~4
zORsl-nINy`G2E?yAwA9xJA3XORqUQOdO`h{CGQnO369jVBrQ-TUsu!sV)taaaly^W
z?yV%r^qF)tVs{388@6%`30s+iBRI<1=F<LI%Lr}gwYf7rsPM2MPpOMQ^Tt<~P@Yp)
zdP`}!Sh51HT**i)wqZE#p7Ri43}s6OvgGCF)SPxyNpLN_xXUokdHSr-!GG&KE>Lgf
z<@ko25Xmj;Nrb{rdc0zR<<(=$7bNubOalC^ah*~=YcoR;1+e?9CEOEn1CDt}xWVPG
z`xo)afySb=h@CV$qW54{ks1n8%s*l=K<!b~yTI<0+c0VHUP-%&fPd(Xv9g>S!IYyh
z%~7J`L+H<TgAw9&Hyj7>!>Iq#0XHe)yl8j`Fdc+;`|PX3`Y)olb<9@|>yJbmEc(Ox
zuRR2?Z9HJxypJ}U$WRQeq0J_4pLp@lRt($%MSoUX7w$i8;)jNE|7r7<rmW}wKW!e=
z*0cM!^?z(f{5O1r4`4h0q#N;}0f4~8Z#<1(KM8<8AJzY1BLMT$n7KWR+x8E(1(5!=
z4_t}=inRl4<M(Qf;@I_Kgb&^n0vp9&(Cdxh2LA<}x7ITkk084-Rr(ksrUROk!)z><
z;AQ#sCFm7gS<<t*$Ky5;+vEOqa{+g9_#tmfjUO6cwxcOyH*O)^5d1*=U;?0to7+)@
z=8=_9jqb*s9NT{6Ucdhb-`4$rkNp0@kB#S9|HASRWg?Al_-b;B#!X}U{>u$2zVmyb
zR-3_9)ku$y?WN=Mz0XG$S^QObEUIkDM;1MdhaT(Vv${gnq<Rx%g_zQpn{J`WWzR$B
zdCG8^I=2*`Rf!`*&3$PKd<<!RJX%pB;G`q2RPUtmW-K1})iOao&x0r8%km`B=+c~+
zrd~_%Tpi^6irQ3>jZBz@Tt}^Rj-~Sx`4VYbw$S|3e+i|~=|H=nY?xeS&F-u#`!r8V
z%a80qlj*33<TeBj(ix>kjKl?8<ZZKOEoeSyf2aEjC&8@`?(k%teS^LOEctECc(|7L
zxcqv}(`N6{vh0|UCluhtA!CbBheku1y?I3k#rd!vI<{19^)<A+iXZJO^z4dFg3L{`
zHDkpfS*cj1p(^6E8u-L6?$<S&1sIVCYKHBy%CH*PP}b@LKa!|i+{-n+_s$^c+;6v#
z=}|jdm(6KeJ^|*#7F9V-d4Q;HC3~zB;Dr=-o1#1-cWVYzaW%1n1YRQdxP-Uvp-YaC
z%MWA6Ct*D^DG#b-&c08OqSQs5Ih_XZQKw~<Sfq%#&^aXss<fTAbHP9d9S=x9g_dNw
zRlj6sXtv5jF8X(`43kH-%hvss(cVs~b8`$~HJ(~D%}OfjG0V!nx~GMnR%RO23FtDQ
zHg_u7PE#8;^ng>@#_Tf!eFU5Zr<S#wrR|>fMkh6%R#9reY{*??mJK47f*iOg0s;@w
z8=Q<Y)K*m|K`Z8p3M1hJBOnyai$x`;1xC!QU5AJdHmFw7V)VxeD~=YgRxTdXzVP=S
zZ(SnTdMHk6c5{i?@;0`3_b~I-BQS2Jv<?2KmSej6G`!PhDx;FqkB(v$PBed{B9Ccy
zpt;64;?69mMHh;74~wZr*41u#*}S;SoUOunRUCud7G-v<P0E2%A|R&wI}F^5A+g!!
zw4%d?(i6)l2~{$(BldO$X<x!%ulo7lZb@qqCWS$I>779#f~wOap0;UE@}`&mSk;50
z@i=qFM{;A+LtgQ`2i-}k^0<1*8sAVH?X}fbbB4qs$A+R+*_cqtaf-CQSN!$?H8u%z
zQ~jROlDVoaN1G(8QSwh#atriT4C^Wyc^;$k@r->|_DXVb+LBRmisr6p<>?xi<O@WS
zEuU!JEb=d*%fSp);&_2vP^(+=_?grKK!y7gKkf`FtH$ljrPHQ50$lyLvpYkMq(k4*
zOr9Ef>G(xYi?-8#Rhlv$>x}ulK(<Go*E+O5HDMQ?^!Q-n_~d0xPc6#9Ie96eUbhKM
z2;XIHM@K_<6vmvPj%qCS&`Yw9jWSv6V^<8AV9RB%@1a?rhm2IqcDus2aO(RR2~<4y
ztmf@m18U<A%F+8x;$)ZAUqf2g7z)mN(A&{@P{jJ;`zmq~Z5Jk5i&1ST^lyzyTS8;E
zkGH^~Rhp>8L)REoeMff*fg#dU*MO|Hb5hiFoF%?ddtp0ej_q=j%R+|;*&Q_?$ZAnO
zj+~iBFzix?;qbdLN3t3XK(lJagBOFB<sU=KTLnjVmOrav%G+$ZP`m(fhf+ULB~p+E
zO@^6V?i<;>UJ9k8CKvn_{W@Rt#9#7UHEhEz(`V2#Nl9&pC72rlah;k8v@=JEpxPmu
zIK&g`w+(oqKp3F~L4u6gpP}bwd{RPleQ$^qRFgVwMIG0zsHH_*v)M{(7L8Rg!*P&q
zVQk9U8OzUX$u1i?_e<`Oj_z!Hv)hki(`hYN%S`>g6o*mS?52JXd=5v#*=V5H<MykD
zg!69$u0YPF>xPO%MZ!ey9KVz5ivN!FMul*?b6TttQl;6ntf+p&-Dqx3iv*vKgLFZ&
zZs@^{evhbIa6v=XnABa<leP;l$Xg{x)7sV_f$&i<Ojnc3?2hQ#h(S@+q$?`ku~P^B
zE9(lKG3@(|bBG@M1olrz@Vi8IV<<8hD(jH9BgNUFGV0pfpnj_uy0gx63#<Z-B+a%I
z=`ew@<PInjnH(zD`2@?Y3bwTD=#CvK+?k!As?)g2arFCVGTETHOn2HvcKgen-8ifg
zBg{yp%?T||?&tndPRcyq0M5fOy_Z&vand=+&sko~0Gc|h_BrdE$0mAd@$_C}NE`RK
z^y0PIP7k-{TzvS19?{5U?%YLbk6Q;UMyRTCz#VgR3uhDIwvQ>LivJjMEO6nMYK^Ni
z$w`fpLKlQxKeS@~@&DPC;H>J={SuLT-AtLF(5ky)S`S^;x<{?-s9m<0(l$CS2f1Vw
zq}Rw*x@4U**+rLkw3bSX?ZTosG_tN`k~&;k&U(yI)#Sc9HJ;g!RV3^tHmy1kqK>wy
zx<pZd?D8A6xSxR<$K5qYPPj`s)Ci8ZE!7;RFhn-BR(}dyt6`(pJ?7$E*&+z!TqWix
zQ^?BW7}qPn>1<30o?*;j{*9(^gkwUb{&bw`DR)UmldmN25a&EicT0k_E#P3z!m|n3
zvglA^Kx8R&yG6!bWwpi}j&{p%<eW0|yX~avCRfLqRQ7QHUB|0T$kUu67W?VvrEV9U
z&@oL)z{;>?jmZz-9L4#L0}U3uBH+lovJ$3TI5HiMIF3RfVDvbqRt|;wHa2_~Of@iS
zxSJ%c+wDJQ2qinI+KjoZbk-$XnGpPFbom@}`L&7{O9WTBs>?V2_6Oa>`~=kvZu&H{
z(=-!xQ}@nr3*r3YOs9oM1y`(@>TWG7ro~}hH*_l_dZdIi?$i-4p$6s;MzAuQvk&Fn
zep$0I{bKvHZsII~^0k5s_A@jul_|^F&a*0`kg;V>$2W;nqe6k5>2G#(nx|%r8t15u
z9nEEjt=RtC2To-_DfaT=d|As%NdqgTM*n1q@*u)+<LsEvQj5nt>0Um%E5*?x*VyhM
z5Zl?+oTh5cVnbxnGRe82qo!=->qgeA;iKp#%fz8YjySg)O(m*qA+|S72vLtrkI9rd
z)hrw*XO=o0g5jie<Wbw=<1$iLurwLH@!dU+1L}$OSdCI#t>tK`BC<{<CNZxRsf`X%
z%Cdr(_GImd5Vf(I!(tW@zWn$syJ}Ka)4?@joJm78<T^(jIxVY?tXu8QFa<hO&WYY*
zl7ke5vvIjL;BdKFY`c<E+_@1kY@?D(EavXY_)DgL)_Uqz<ads0O)meR(P=BK+Sr6%
zmpR)Xbo9YjGjd=EB@NF^vOizkt68}Ao98s$?(<Y0h$)~4CN!l=<0|do+qqARlI>h~
z#E%snO>>wWuwmLQv2Ny`g@cUNFL-Ie*j-5`(Q&sx|9UZFv0)(_2J^a8DmAX#Y=brJ
zZ*%%7jLx+${Cs%-H?CJc^9P3S9&?*nx7yxZS}g4v3fr%~!G6foY=As$wba^qEb*;q
z`x}#Y7q9UZay?$#>VvP)H}-Sy`FZny558;vh<?_@>M@@Y2i7!W(z9!5($hEl`K9>l
z#UInIh2pKf;)U<r9vBCU9%!K3oubbu{whDXtB`m~42V}eTUIVU(RrnQD7cb2DA++N
zwX(bRr*kLjbbN)KiLK_BG2Q5*?U-<c87G0u<Q;y7h<9?GN;{_UjRn%TlxMB+yGq43
z^Y)Ldgm}Kh+{Fr?F!oJDw@;iL8?W}UBsxZv#4GYt`zI1_>Z5A>`BA;o9McXCRrN6I
z>uagz-d<|^>~vpS;0yB?|9P<|y4RQKmwno`otg3ThvrN5TQA(6A$@(7iI;X3Ykipq
z9)2#V7XG8Xz}}i$$yFm^eY!}xJn<j4oUOKMm)Y~3qZfQ{u^)K8Vtj8gbkmcGv$O15
zWDD)1kYvNEnrEN7C6no`wa^**wvFxtEw%62foo(0B;+GUD*G0cvx8^lShOwlJ=#80
zpU|GQCaMR{EMLplW~RlYHGOX_{~hW}kF|&=E7SLi{cK|7Yo+|^;RUY!(e=`6%0y)U
zg7Txe`RK>JZ-C;{SYjut8el%~Es)V$s8%uUh7myzV1BrO%gtf?`>FNh|9G|GT@+sz
zxNX=F$t2tb9f*JJFvGsa!<QSC4Oj&i2T*kIA=~Gn7q6pE0i9+WOV<IcSR0ScH;Nm)
zkLOvM9hrfLagPE4K(*mvbdA{K5UP-!V_0W+8*bpWhJ(?lRoFuDs0q7(&4tfV{mec1
z&edb<Hp_a2L*ucH+#R+QN$Q2hhR)gr?K)exFIpeD=i>t-H_iS7w`26>zuaHdkI<jA
z>@-6!#0G!zz}jH5_sY^j<%em|eNx5tYMW=MKF|-;%cmmOk+_~}d;j8V>G5mykXbS1
z*I)e$v(}TVdmzK_3|-dOdfB#SJH7l`{fYM!*+`s~|Jk9X+uEq_vEm9+v)AR<m*3~-
zRoW*K5#YaH*RN&hH3pE$Mc+*t`_?<by>e`ly~cdMRD6evp|kS6wdeRk8sH*dpi!xC
zv*dfO+DW=*zx^6qcl5qpj*hK~(sI{9x;8FCso9QVZU5lZED9`6{gC{Q$glR#b-X@)
z#=72%O;0>_ac=*_X5ZTv>2>?eQ$JWL-hTeGHxL%@rDH?yK4Q)r+Mu}qto&!<pcpd3
zJ^bbQ$`8qwOBZXWc8gz_^Vd(xK#f>8lqaWFsrL1mm3ON_<;TY^@KLra541^0p68Ie
zFVzn9p7gXRuM0qGcC;uzxi~rM)AyYUr>|OT7bhY41!|*LZ8aw6ZWRT>#Zy2U<)IWd
zY8OE8sBPB5R_GJetqloULx<F6bV!{u%eF}7S&jQPjMs`j?C;gCk7a9t7A3d9=b9UB
zgvl!+Ikz8bZo*|F)X$%I@1<Xso41Wtdnd@tVxGJ}2hFc)aF8yq0)+1SjIy&fKq~j6
zcjtCx+x6SQD!??yjIhzQLo}q<(;n>3Mp1@xe%i=g9z`Dp$1c{-0aCB6y_Mf*UMae}
z4=w-7z)?2)nAK%;-v-0jcWD$&Q+vDrYJbfPLK|mE9<Rf==&skHoh!W7^{2I)Y&o1E
zV^12W061KGdci=i-EY^+%~SR>g4kp3C+-zT05n+??>yU#{VPrtY!I9JmYZrOIr`KT
zuchSyy~8vnnx~dm&AI)5vgF>WZ#6RbAd3T|nmI(vBXnwY^&#$AE9M^(cl@MyYNPTu
z$BmG5+Bg|t0fj8`Ee{#WkDDV4WIxj(fAbZ3h)o+ukeYVc0~YYy6U_serx@DyI?<tJ
znPWfbukqbttd6RI@fE9<@^9#`I|{X8n{%ud>iS~sxgvdb$5@v^l(~hZ%Xh7<qn>n?
z5f!Jkr7q_Y&|$WVQ_rFYVvDlVnp^^d$4UlQ5?9Q*pdu#CtGPE{eS5F_-_396Yd%eW
zCN5X^q(gVUe9=6Rzg3)kZArF!PKhq(>w=ylhi4CCg93+b10K<oxXG81_uj?pVbgc(
zsizWiP|USz4-)nBb=tZIigOJ3a=?qOX67rX9!hGgB6>R0S1CkP`f?Sj`~>-lfH)4S
zPE8Ac=_*~Nl~FiGwMx@a0nvR!uJkr6kEeeKvaU$FzM~W(_lm=!yag@=%Z`W;+DbGZ
zK_Mdw3SM8v8;*<W{?I}3E=StD@+ov>y=IS?)}PF}y@O`x8(?{T1-&kIFAu=x{MgHL
zOW_{-uw{ln^HbqQ<;h_lFX}Ll2tof3E0xq9^SotMNp^v|@urT~6#@&ujA)l?Lq<}E
zsaS9;Q`M*7LL5x`Dx@$p7jiucJF2_H!)EZ17&5Wrth2IHu(sJ|Cc5IMM7>*Pl^uBm
zGBwo!K2av?e&S>0lwYk?pZJon1-jN=EE8@RM>)nKa@iDfChw^UGIh*_(wrH??rHQB
zFhYjmWk8MXGl#BkA^SGGB0{yO_m*iq(!XhJkOZ_5>)|ADQ0EuYeA<&gZrtFg20-0U
z&n=^lh8mGIg9psDVo`58v|Oz17&~aulVnN^iEyyt`HA${(DD{bwfh8124SRxO~>R)
z5<NF2fh}@wwGKRs6miug`6wzen$O`NxKS#hc{45p>wclQ;2IWW-zQ;oUJ|n+1w+mK
zXz>r0=0;ItbPcAMZSFLaZw+qrK8bn-TWhOC&HJOqPpzS78`?8ITnT^jsA$8?xHlZ>
z{>!u*y%#XqEo`ySl*^JU@<U3+gAIKcQu#xr-li*}WOT1tq8#N@OYn`>iWe;3Y-vKE
z5l4HB6c_Uild3<SymMGP(CS3f4=vCDNA=@~CdCD7&Xgw$TOw-q88gXkyoHmSuX?yN
zUOTn#j`5O#rnY*>Smypc2=|lAOG?$`yLj9^Rr?=y+JD1F?cyckD(YWOC!2>vYwnn$
z<(V^8>ZO`#b}#d6^QcDPkRarnt;l-ZLv*8=uo4MuI0{(S$Y`97sCY+m0)UVm9+fzb
z8jj_Rtewx@`KS?1%XZtHUX%nF<mxC5F8b!QJLl9FjS5hRbrd!?3lA3Sj_m~F*l03z
zOi3Xr<uPe&39Yq{o7#%`agJ71N`vm_MA=kojq6E_Mv00SqHGn-eX5a=dg;KNR<`d$
zb;GsAD+IHTBkOa9hI@d*#P!GAXPbSQMm*v{tc*lbI(HtH#x5f%6*0xB%I1A2gMcsL
zmpZ8|3TX3)CvQ3hEaz74uV4;ALyJPA1m~_z1=*0dH()LyBd39Dk80O6$B`vGArczr
zM8U;v)_e2q!G<5vz~kRsuVwg1f8FXw%Lu#;<(~dGOBx!){`KbovA^MIta}n46h{0P
z6Jg>57EuVdC`S0bB8n{GYTSMqC7})U|83N8G+d4NAAe{h{EI(s7zzB5&wkiIpzXt|
zhBib`{`;UtJq;p~hN6a^wT7pGVg~c0rp7h<jdha+GqQicM*3BwsA1iW_@Jl(k4fHI
zyYivZ4-dfMXrw_u`qgA9jsKRZU6j{<gtx%$Vl(O>J}?VDa_4pP;Dg^Agjk2)<@v>y
zPc;4_3)u)V#Yeu#M}Gdzk601@S6?4KskQzOr(eCxu@ubcJ=Q^}z0gN(q0V}XBaDz3
z$a$C+$BCL(S8RC!I+2>47JZP3dSauZNrOR;Drt#;EFi~xRXMHDBvaJ@vz=P6wU?K|
z9(f;iHc4gp7vw9njX$rf%%U}~OsH~DOAD*eDmp3Vvz_VOC;uP9-UmpM>%Q;nZ8TRS
za0TL)0J&L9RL|Syu-P1f#F0)eSB`bp7%ZEuHAuo#in=OGWOH>IcchR(C<_It!k)h7
zsL`4nMTUuN#TEAU_6^#d$%3+D*@|5zIb1=L&Y7ZAQliL_NME5)SL<@Pg5oO4Nk#em
z-Yh6pRF%vv7Qju<>)-qR`ToAY-+TS0x4oJjz1MrBW{YLH{qy~LHu*2FJe{ci<oN0B
z$>q=e#=qvwSN7v(UmdXR)@BpD`&IgFWj{Np`kZ{EzP594na8-6`Sq{3U#onBM#j#=
zO&=w(1DEdH-+wPB>tty<xz+D~K31P`{tjO-#3j`uI~j*14ga3Adoz7g5h>1k$tJ(1
zB9;*9_wRmTOn1zgK04;>bHiItj(xUUUu(8$y?n*p`Gs-xk^Hfsnp`>m8$WGapZPz#
z^Wp5>>RU_N0@tqYy#Ikj4JQ8T5x!2tv##|}{q_})U5|M*;%EkY#kM=nZRWt*iKUWB
zpDo3T4qTERv2tWrZ~6t6CamPh{a~6rXq(&i+_lZb;n{dA*>$V;esuD!^mX<FN8zMz
z*^_FU(frAeer@Ap+iy$xuFq>dx+?}tGRY*}-ZEUablN88p3_yQH*=UdU#XJ4jpsMs
z)cbprH}>|j-*h)h|6}P*_qsb#oLAiMTRZAYJDjEKvT|lz&gk=@Rlfa(g_{XqS30o%
zn#(EpJ62+T>pCO*r9ZmX`}8Y4`aW{=(RKgr^6U<$rl-s+>01HEtI>c;)V71eb0$4k
z<rCwB&inft2Fq^OID^Bw{-$g%D{?$sJ)A$UIIP}yH(RD3)DExD=*rRoLz*9@11Q@}
z=`MfzZ5wahdM6EB9#O-w4?fNk316Xf=ksdh+DGXV8_!Ryh<6Ipt#}l|argavJ2n01
z-{1QN`^A4ee>bO!njf9MH5*T_x&6r_J#VtXw7)empWYti`JS3^3dZbp&reL7lXEg<
zr~S|K6_Dop(!_b5IjVH_FRw2H<1-dp;q6!d(pxxi`%NFtcDU#JKgV$fj}YsB+rbuQ
zLcjE@&RbX>qT4#!Nv|7Uk+ya+xz3m5=H~Nz8(#l$_f0gOpRf34m*oCe&B1*(yep3N
z8gbnJ1`95H3AAxdWl?5Cpa7jQPDPstkQf8jUCdjiZSI=hB<($;zLjVH^B-}@p7h!b
zalr}OUkw^XzwpSLdJ`U3!5fTOAF+&UG_g&Nz;-9}c#P#`9^^sq*!=SbC&8z*E8Po>
zN;d2sF3R&#=D<y9EpOzP)$<#<{~P{;^wXc*;ppt-tDL@ftw*!ZxXy|8?3AS`<-YrS
zw<n_s?P*yZeO{T#_V_x3(nq6Lxb-|}LT4#RtRPE4v}@|r-S3rtkgzdcA;G&*=tt9R
zV(??wpLan5Gnx3~sruq?KlpCPHfPdX+|DLhvM~ZK5R%u!4ogY$qPf01&RP9^_mz*P
z#zd)Ym%H!xXf&tWJ{K#|64x?1x6j1ec;swHCNKZ3fMDbNr#T92GO{1x8;Ev#sX?=J
zLk3sI^QgiN_W3f&oM8cJIcZB?%*}Zn4+V_aE?-{f?^x21zYh$<7d7&qeu7O^V&c*1
z^Z5S5y|3gy`X}EbS7D=vM;0sC{3pk4^E>JJ45G5@d^V?xoME?-ap3q?j##5>R?1R~
zOoHi%49rE}CX>HQ7+t((gS&t6pKK%}p1?~ua|b(d@S47hk=g5+d?P!}xh?OBkT?k1
zefQ`~qYdNvk;Nl4<s&HCNL?A9kMN_foES5ijob=y!aOI&dH;vxBK;C2|9`zQeYfvi
zq4o2f|I`2R@IT&uJvaXIFMaRa7;);(pZja($P3%)x5a_wmFwTkikFRi1{yU!dXIl!
zN45`6kbJ}OiB)x(ivm%0Zg22?#Baww*ObN7p6D5V@G#oPxmaQ9n?`b-Hw@s_H{=8K
zVEM{>g+7$U{hsLA7Pc{L*Zspk{7G#a`#PU{`jWcVb9`sd;-jC;EM)x*S6#0!8Tw5=
zKDz81m%YcoK;4KtelSmZMAF07=hUOzb^THIiQdJV*u1>>Xm;`DpC9)(Kk+&yX^fbv
zd#(2{i#xcN&o7$?6&M}CdATkRWjf3zvwNfTnuWM7mu$%IfIs}TP3&thHUj>Vzw?cZ
zRRZJNjY$oUR*o(`JnDV!`#)bPoZjJE@J6otaPNuxt6pF{yvh**E^j>ihyA{18rSs&
zqP^Rhh%p0T1T~CHZ{FtZYxkUg=tDRr@6OmAw*I_fA6+u8?fi*+o|&$1;7&LxBFhpa
z#&G99^1q0p<%?QSCU$mYrdaNpj!R7Kih%<C*I(;tKgpio;4vTLbKm)UE*JlqWK2KV
zer=Q-J0mCe`0^iI;|g?cT>E90dwj`9Z{HxOj1T5q!Z&;ykNmvi((k-+?U4`5J3lBN
zIpRL$_B%ez{~rhiM0NO{VLT#}GN|<o<F?$1zrVI~{}+2%W_&P6n7Q%D_vwj$L$O`!
z8pr6~o-v#Z@&50;YZ&kJ-$k4n2lwR-J_`bF7$4mEvyVC(##cnA7w@h=`gT;#N9FFk
zxw?4s{G|`cOs_c`*Nw>~#bC}8j6F(?YmYG9Yj~wNy!^c{m&wOav1n%JLi=1HdXr&*
zrfa>6@X%4C|MvXj6>mMvu<}ATxRrigAK|n5b7)<*i)dumf2+-~zUtz)m`ncCz8L3A
zzq(};q@(NC1d-Y8!`EQ2aDu4f%trpv;D9AUf>T~RhxTrlnD>1nd7dYSs2fK;gf>VU
z9J9w;25+UQkunjD#zroJlC+FGPxJgMzsUdbF)(`_ApEZu$GCp|I^K|JL!gv|C6jB9
zSUY^>##fo1eO=6OnX9=(|K?K<@9@~1{=fCFhl4*(f8>+>SEK9yj`E|?;r=tD-&T(G
zzC3&4+1ZNS@}J}DkAMDBHhJW;m(pi09qsLGUwViC?|<sz6Zb}|>He#y**huqzw?>i
z^OH;ec<1^~@Q17czxmQtwwe60`oa@$R_}V#7y8P1D*K7C^8vo+(iuIQ1y{0P&kwF-
zeCL<G&G+8>|GCX4|H4NedCSFJHs0aC{ZPGQpD#J$9?$;D>kR*+%E$UXF-NFRKpYr~
zZQ>@jHBc6z`<=IphusZBed!VbsXxWHSid(TP(S|{Kb5ZENkyIVA^YMp=P&%)wdj$z
zZ~mnJ#25UBf7>7ZZg6FG(4%#~b9(D~Z+kZR{NtB*E)6DMyZ(LA&56&o)88HZmD9Id
zPyDXGb)c`k+xvfC`u+WzoCml6xhVh1<r9CG=WE`1`jzZ!tL)*`jAJwz_ANW^_wD?J
zan)<%{^u7LU%SGgX<y~qEBe}7r%~iOJ`%{4|Hq?$H=$nG*s&jA3)GHx>u7Xi;0!81
z%<C*KPgg~qg}DnmNe$9innIq!c@(Ppa1}o2xlNu7b2oG43W0l`9%AoQdB~Qkv`D=o
z8*ce_#${=m0~)GQrBbf)W6Q324rBgOc@Tu0N5*=%+~L)a2e|WOGO6}B62{wmU>x2#
z45xF)4d?a!us#SEryLbu&(bp2B5@Hv%4E;9T*m@O+l;;XZkNqw^=Qc^+9sE=5smwf
z<9Z}NX8c$-4}+pUWqB}j^IlpYf1(F-RZ@?_`Qg~BoUmOKCtoiX$ha7-LONf(80^LW
z?!iQqc7>Z?t@f_+!TJ7;7jDLL{ZpOA^<BDC^0S~fZ}$*(J-SF+MR9$2ap`>E&A;Bs
zrKfUr-YdBSs#MA|JyYZj>wT^b7nygm-_@rbbCZcBsMPKm98#|}pd|>`x1Yaq)}Ea$
z?soEn#%AbX{lmcj{IA+bZtOl#ZhLIe*?Z=OgHb%Es@kTb3*9w$mtm7(uas^mV1+q7
zldqwuo!FTV;wFu{de*taMHXT*UR=WfCVSCY0b{XYz{guPpDnv4TZY3St|1rkex(%N
zQH_FeTydd_RU3BBaB<K%&Jf?>)iZwKzewZ&;{FDY5qtfkzLy=1LTem(i@e~Br+T!)
zWK2FU^FkX|p)7H@%2z6^^46_cr>;+zOc@Zx=}hD^c-s%zFP_I$<u$Wq=q{L4&NbSP
zaBC6GPv*V~BDU9cS)KU-Yz94`=ktSsB%mGlDi^XR?pEKKOsgntoi?p!OWV!R8SCX@
zX!Z`OBvnp5h!QI{QOD8<^0Z(voC|c6*rs>^lL^zoJnf2>mh0VOF)A{rhbxv`RVp_z
znbm&Cer+e6zue~4XelcJWCwXc8Gil$WMj?IrQQDIXiu@8b@}Si_H##nIp(McF;#bu
z!{rZ1KwS^6M|^sinrNw1<VW#*KZ+N(z2V8ITZ~v%5xwQPn1B#a+?r#XdCjN3S5N)U
zU7)lDeGil>_LN~>^JWLD%S}(>v-*H550?It3*}`PANX5ufGl89Itz(e`Zv_1_T6}v
zS4G}AvnB|bvG^x2BS}+G!Vfq3QnqS;nWsyn%hSM54RJ@Jh~o~pGXjo7Cu>qSUv+gx
z%oeDZK^hbz!+2N$Bp@;sy|qf=6C;KpZZN8G{_p-(R0r&dRJ%O*U;bsgasscKazW4y
zhdq{L7*5n7F~H~RL%iG#QVs*VTg(<S^gyttf-aazNf4+s<A!)rMUTA)yo7Eu@;MDr
zTnLwtaa=E(-}L5AJW$ie2KC5xvR<mKbDn-t2$_BKxByCZ**o65I{y#D7k)gJxPB!p
z0DuKB0cdgOR7{FGUITzX2P!8g-U;|4KoMq(j4)v?A^}%};1YX+KY(0(GA!z+LLv}Z
zvn||LqovH};%CkSOKV(vrEBkNNLi!G1*B*{?Ec6=a(-;tEvP2PA9@x*aDvWN6#$fn
zv#iExl3bh++t9d~&i8{LP+>kV_-eD}t{)D!@PoBBF)o!dk0eELR=?b~0MlvVX1!JC
zx>yCYMw^mK>~y~GdxKhq10LsV1MWmni3bRX{!Eedk1o;9+97J$V0dNwMs=O&4pr6`
z65t(Qh9ObOv}H(wLu{B<qtJ}2QL;&X%kqu`lecnWQah;N7*=FGZtVNP%5JlqD~2<f
zUoH-VH%Jalfg?ApBfj5c+BJUK)#MPVhUIx+!}#)BXesc;pA)s=?jCP@>9ig_R~?4T
zL^Wr*-_`lD15*T2u$+r*HqvGDflWkqRT?AOvg`Ri<24eHTtV5Nswts3cS64MBlp18
zS;&b|g-dL$F&NbvaqWP8o29ejNd>3ZS)z6c)${j!3M1}N`0e)bRD9rZuiCz`S4X1b
zGu1qmF2k*5=%BMy4@$5KCrHz5noZd|vItN^ng<C3uJIXrtI`LVvD0)~-ELLxTB1%{
zyi)Me)Of>pU6_8HI%r^)HKzeMr(a+Gu{X%^(>v~!t4D9#J$iiig-197Bdq<nXvb)N
z5fnp<0FqcFZxZ%mA9BQe5Y~sKs#>?15sGQp%;XxJLn6^M$Z9qLQVqf?yvG5)tFC9@
z23*2841=GR`#z4P{IR0P?93#XeUiCmD*w}pulB&Xb|=Su?^s>sfkp4<GKVklapo@<
zJm0!l0V7)>z$QM+ZEY;XR4ov!p0<^nE>~%h5uk`=3-}>EZtVw3)O9mz(;;u>Mb^wn
z9*vfZQU>TF8DpEn5}giJ<{*~s<h?{p{PX{{;2I|!ZHv0tz3bJ7QHW2}(>T?+eHIQE
zry3`bY0Zl;K{Uq1{#lAT8;H@YurzFmI}?h8Y*Ze`)lJV5MJ=*!wt$M93Iu8g)!9n9
zgfxc32UIcZk#!_jNN5@ExBu-!xD}^h><F;zZR|>v9X$~MLOH%%bVIAa8txXJgIusg
z9Yj%R*)Rt0WZEvsk$JHdNTMowYoK?zh~A&79U|n=du-a|0r3c-6nK(AOSB=Cm!%p^
zRM?DF02Ltn3or|ZI{%^PD3y1i!IR0+B@nWH@*_{<iSt)r9E(|3uedYmg<K$05tv|$
za5eJ5h=8Z>-1eZHl`|txFtl7@n{rLLPmrZ1w6TJLox-ii1Nc3&leYmHRYj!}t2zp+
zQQSu8c4mc{CH_Y&zVBzXzHqWDSLw;`R-}a|E|>i<1M8Z0u?m5n1-B+iX=<UN71qEP
zgt_5BWvXq$*<zG-)(YQw&4V;bAiO^giI9fJ=eh!TUg2h0a^YnXlBHmrB1_e2RXBq>
zvxk;|P0j?}FaOEr&h~B}jj3CcN?n1gm5<-3Z+dDvYtK@!JSX{pn0ZfT1KwkF@?uu`
zk%wgSIPVsDkQR037kLlV<SKlKtP!a)3a6@?R>iQIfq^+si;3`rCSZZqOt*}T*m6}k
zhpT5nYFjvsfnMGB{WBU9MCI<0(4kA-(Hjx-t#2DlO;uF;{tEbFU#^&v4;VH>Ntj14
zjdI^Bs#&s?`X$lU;I>F)r`!#FI$@U0M`hJ|CmHdP`*<RL4O?Oq#5NR}%z`o1sz`xb
zv7(KlWQ;HWD(ecn<e}Z8zPfyQw{Pxz<Z0+=R(XY0WIb{gp1O7%4LgY$ZsL7uT@?WS
zkh_&L@f*Auzmag9`y$W2SA%JMI)gsD^{7J{5uAGxJK&o$wOmPLUP1qzsI-Ay&>7cy
z^_Ot?<fy+3$vC=H!Za?~M~CH2yYjG!P_o>Yp+v1fmT29{DquVWO;f+XbW|YNgXl?8
z-~lx91K%wVlcp|UzN6&|aFdq|gFs?hm()83y3k`Acoz2v>`Y97ri_37CLMz!)3$f?
zxVr2<4aP@75Od`+4J|)pmOU8{k+7UnJf%ADs+)cuwyp1%cZ+6}5TR?pK~Y4QGanIy
zY7X{Qx4U6;mrV><R@_O%5@>TvNcemot`V}uWFFY;$RTJ@xJ2P+UwHivTji6gkCsgL
z>RacJZwH}MskTzclC6R=^92JLO(=<gR$6n<+AnXaE(NN{8l43;izYNZAQFTJGd;8r
zFQzL+Fszo0A=j)0V|Ee;PQ9=EB+YBwGAq%TA>7AEp7~b~K^|!P>}*36uYx!JvzMcA
z?&N+&AfM)ToiP@nCGG&2x&S>O#+|2)S20rI2vO1umJx9*(ux6Jc7$2SYF?y%00~Kb
z24NsH&uvY7-L}Rc8=;4~ZOiXqG$NAWzW7t7U?@B=HTez*uiD$b5=G^p@rrD5;IH5d
zLqc6VT~v=y{CE@?#9rvJC2d)_4kXVY7|^}2eB25YDpg1&tme4-teZJN9%3^ZcNJbl
ztpYbEN~cBRhPag`HNr1=|C_)5Jv+eYZhr$(u1egTFSe~BH;CsaL3z4NA!Zm`EF+F(
z6YnJ0OifeL#fj4niG?m-1mst~`iBvb35WLx!HRmI9{Fwl5Eq;l^#KkqMT6LwL~bSn
zf`(2?P_Xb@pW?qRZoo~9FI|2}S8e1RlNoOBR+l_;=SDq}`Ff^!Oi;30Dbw-HJcN%6
z9f`EZ4CXIG80u9wgY?+=yV%%Mia7KHr@X<OVxaIm<PO~?$hAmZW1F@FVdyB!T|pj*
zmaWjzb(P_M;wQGGz(tt83uE4<<~)K{RGF7I=@M}k2dhvcm1vd>VI+<z`mn1!_m@kX
z&E6bnkFX*we;-j}rWH)oD=6A&8o=N|DD*5CghNWJ(=mO|wG=nnvModeoc`)RuyG>D
z!VYfBm$sx%{iz!cRA)Mq3FX=1G|iXdl>)IifLNrWY7eLNO;YJAZBd6^&b*iQf@l(7
zS*s9CFvh-5rK%n*FerQUI@BlLrpsB|RD9kiO{vQBvY}J2LW|kT`^E=;^SgxbL5-_D
zcC06<vv=pmC?%L-zIcgXz+N<_Sm2bbP~w(SX(`|JK&kmW_F68=&>-6APy%tqb-0PR
zlbSn5X!>O+>M5EP*XaN15y4yo-yrfl2hiuhf#xx4$X>WrP{BYcV57zd@&`p}*ljnx
zMXI5Fwr9oM-%C%VDiTVU1%c0GFT{f<ptCpw9B)EoQnz(yi<P~#v_%4aS8j=Fr&bhK
z1E13*y*dv{0CZ{Vnh6^c!BS^O;U+p8RE2i}+`7#{0&swMXzdfPJR~*tga*K#keI!r
zN1l<!TB_h^6huLhSpWiIBlrob6M?Wf<xS_KrkGO*Ia>)NSnycPSPD*I?-Zb_1VZl@
zxmQu-kSIsXgp7=P;gz<@m06a~p(L9$S++tnijB5pYTWDmfBk(rcp?}L06eIFbUCa)
zc0(Eys;biRZbuA~>5vOJVyf$zQZvK@SX-30RY>Lyd&$rtgW-!k;!7#uC`&2ke3EmU
zQTaBs^L=4xf}r?>Slf)~fSIvm!W5<u(jw(eM)=mhc|9g%Jxe`ccsvMkW8SyTFl*Y9
z(7T%kfH68?f|^eWR!~#bRE;;?m{tf4xVsqJ0sDL8I3$7}n<}XyYF;a3+wZVw0-P^P
z1H4R|8D+ur_#^6c;Ls+pr%GxUE0AJGQ-Hs|B@H>YoTUA#&zWP@p|rv3Ie=S^5^xPS
z{If6v8@yUts6jLi7nN5(1%x^f?l9+`NQPiIAGv5wp&inQsFrO$$La4Dxzl747;@Xh
zM4@Tr+ZLI8?zFk8PM1PtLNOtN|LLb50wq`##C`zj<2%pn-szJlRDREcx6g*n4Dd71
zxkdms4j}bl)7y+U!N@A=+#ZGMmM9gOBz=?KlsN|7$APy<Tb0#pTl2{~nldCJIKhfE
z`w%O!UzcW9x8)ZW))N^1(q4~>u+JYek^bcaUi~Ro%DI8^9>g@%+fIfW2oKQ#h*SD;
zwu#e4xd-75mYutWg|(r9QtAw1uqNy)HKxHmTzOl-h~12YE5Ja-t3;Pr5nh77m+atE
z;#M6@H$^PE>d*Z$IdGds$ZntPe#PE9a-PFg%hP*aI|Uh*<N;cHYa~P_NzQ6q-h_cP
zCn*k-ua--g(Vs=Cgcqg>=MgcOfJsHs90Woaq=6)w&>5+seiJ>>pGmcznEw{LXOQa4
zKlHjag+ZgoZ`|FxHLX8<6}?X9{#iZ`2v%J50AH7hG9a_Wo8?zE8ha`HcwV4>iHrk^
zl2ljFq6#uNJ_19b#d*(b!WGJdAD^Nu2EzZ=3L~G=^*;2+v}ox3g#aoG5m`@rR&wuc
zU=4V>dy5f|Bs@MddEsMYZ<;NtcC#DStH3vGqFO+lRS!G|Gr=TlLd|LJx3tG01;b2R
zTV?<}h<}kC>-~^=N<?IHQdb|WppZGL6_<u=yGEE*jv{x?{j{xD$;`>NhzHT>fAkIm
zHd^*Q1#<@oDOdq<RM9nYxEO`?0pkgAz~e<S?8w505tI>GD6R)*%{>L4+@&U5!g|Cz
zxP)p%DGW*LVpD~LVOQS`7yKTD+T@})FqKU`Nwp7+L>+;rnqq0!Qk)1KD|38*yh-<n
z1y#P))tmH>KYn@lg+5KZLE!b`*%rOIj7}e(jbKoC0m6ioIbbCyZd1>7n!7|Ba-l96
z559uvL4YHA?VwuW4;sU1=Mb=D&@~QHG?CO*tSszUw5K3leQNmPWk~(mAN+2p1WQV{
zXaTZT6Zku<)$qj3=w92VLANC>=uFU3v;jbySjZ{|vE@ynEbRdu)F4={#5@<iBg_;U
zWsE64Rz=eUG*nh8OI<Zqlmvw6q)vnUGqr3QXMvql=am^juTl9ozW2L`M#|@-zLy?v
zU#%{?!P7VD_l=cwJX;U>SCA#gSqOX4YzglI3Kei)4aQ8iQpIBevJ04^+%?Zds~{Yr
zl~EM<0nkA;N-7Xf3?v2h7)*<10401Dd)J4751Tj0q@$(gQ-<;B)$3(ZLB5>SJMLr1
zqi58O>c?nRc#qZ9SvDk=IxN}43gQ>&-%U2d3SLzWyxO7dC>ZW67%?Szij(1B;$sLX
z)tJKEE1!l)F{E9K=Yu>9gyKPQ>5lEYbn6`tdQcvOxs=kt00(FM((COFTx@r5&twDP
z)uT_vBrG+r+p0aI1&isi2f85Q#g?WxKT&SQh?f;jdIld1^C5jJF5~AlB8qk$icJWX
zOV^6>RsaL6SOW%_4-pde(=(~iER*yG)u^Q8rfFgrayR1#|6`G?579B{hFrOP)u|t4
zHX)6tsW-q$C|ocH6ikMdPf(yTFqzvS<y6!3e%cLLWl4SN?zL=K6J%FWAV&36K?}^H
z1?EfbEh>XCNfeC{NUS*@p<ZW-9zd6HXki<}_~s2d%`CuBC@N}ez7*z>XUoH}o5!v1
zEk=1R%V}Ugo|~gI6MR)lx&BzB3)>>^n$ytj5mj^;1yit-0{qR$jVp9k4VuE4E;6IY
z++h!-7P-WVscFMaB1pi!hQ!BX4`gyfyy4t`AN@8|#e?S3JW_jioU7H%IGwT{WfimL
zpjdmXAU636CauU;%J)kj?$_om*}cw}W#BJyLT)MCi+c(Zpw&$;%kx1sgRTZx5hQ#~
z;VBezOrpdEt$03Yxz`AOCg#xD`~H?RDa%XJv);S9H`#QbtFcgBhb?VpD4{J2KjJ(R
zZo<Mu6;(tZin~{iUkqC;(@}hc#0MJH%0PC2KS(m*(`!^K0Yd5FljyaNX|<arP;P|-
z&~Sbljj@dnYafwk<aPeH{~;WVuoSj)YY#XZ^pD;~E^)^^vNtM;r&%WVV@OmiQYng1
zyuW6Jq*YCr<-;apssgT{3W5<J*bzQs;n-=f1!6lZ@K+=SQM(BjH;IYC{4k`H2x+pU
zkV_<5CYnTl<FkA#1EuvgI!|R8e9zqp@4Qb1Y{mB4MTi;#aLnSCaz94&OaUlrr}-h>
zJI||ppB8>IqUQ!t!<IM~SC9h(d!T556|>yoUg#U0H@KE~12d!FHg_O$1C<WIxLzRT
zwT5ux{OK<M_Y^}k+*nxI6Ti6g;qds!0R6+2+qSm_dsaq>vtE!^jXVsSR8SRf+71xd
z$8}aAx3w{yKr5;O#3Ce{`(9I*=`!tlX&~4o^j-5Eu9%Ogs^+pP1tMlOMhs;GTq+8G
z^;do^VH<2RNmYMOarWvhTD9>Yt5)r>0huhQ1HMQw;#_1RvPcj?p75|d&L7Kq-GV(C
zq6e)E?OU3*+MD>+O|MAn+l3W$?A^e^Hc0`&v0@5U^D-9wgp846f@N4|M6?vQ5|IDi
z%j}|}fRs%aJ6`|R@rSNFO_!h=uw-yhSm7d1>3G8bumh5zQI@zEvpg&T&C0nSmAU9&
zAc6}ppG!b)MpA;&5Ug&ms5_F328zTEy1MwhmPytk$?K7q;ae<x0TVif8eja02j#e$
zot-Q2E00`x{N`t$n>vH(Ns|_fgEU=ovE)ZGphhK4mQB93iC`SJZA0X9*)m+0t8!n$
z6-$C#(}4plHw_Bq^CKUn0~Gqc=ztlHL&Sl%JF@ovbpRDY6a?T5(>wpySCR?aKj;b)
zi>%&NANRu-eEP@~6)ihOaB3EQGBJS+DL8={26G_#5WY+<_ZAR~Eyl}*FAFsU=soUI
z?~n0U=n(6+bq-JS(Wv-?a0>qM$3`?}Ng>1};xCrqEwlg8|Kxjisj|0uf+9VVjXbJ<
z^s%SMlowFsa<mc@L>MxMxGE7Ofa%eRkKnB-J25)g_6nEBKr%-W3DknbsEW-M^K|Jg
z{2*BQiIoEn8e_yi6KW(D+6HcHsk23nqHuT`Jxq!leeuONuxk>Yv%Pb*TDNxJ7f!ND
zVWWBBv04~X$pj&?=_pG~Zi;j)fdw9mA{A>GZoztcBdv+ovL4zj^#mOK?^(K4Q0lCF
ze8CWHkhv7$T8|)9l$dp7x6{xfciI^<<AP8Bw+~9P22HQ<m>=IIb%iD3`q5pm#P{Y+
zvG_W>4({6Zsn`!dWip5-S|cFCD)J!=AY5Hg-xCv>py-&DgpTu|H#gt`%af;2s!vgr
z^kfY2dvpf*I*i%XBg?&MJD_a@Oc0PF8L|baj4d#duhsVDt9Raf<tkH2XroPq`BI~}
z;?RXeE@~j@kvOo>K>4vs+m}{&G89LX2!_-hrZhESF8JZ7s9F!KDQ0fIMfZ?_kP0FW
zs`?yF>D7l~aaqnN52#8owMg}Wdc$VdBFnFQw+9L1*74Kf+o;qCkj6XlyBv;yTrLBH
zIbs5uU!))Midmv9xK{zIYOv7^$+a@5noz3pZF)3j?y`7SlQe1ci+AZH#_V7?W|&cM
zk78QH2c2wxxgcEUpZ{;5HPT3(n83rHIL?#1$P}mZG;ZB)E2Zt=K;m-&LeYdGPo*iV
zA=KM`Q`xs2Hm~K)O!vG5n8bD<gf~d1{8!?(OAK7()-qoTm6ga4mBVdfR@vAE=gU7{
zed^27oe(bO{^CD)J>i4X!?)ge<?7@Gy@x|!?xkhpQC+z?MOw|cy#%Kadcz+_81H=G
zuKczNAfXl=`d-mPX(AVnWy^N3!*Gu842X$*CDZ|^KQ$QW;wl-*#Gp7~Rpmu}%Fhz1
zB%hxjzeU#dH&`6&yPOThW}(Z^9X;tXA{g!#Cr_p1;-M@g0Z8KVWIQ3hI0n{)+E-m(
z`DmhpNML6K)80WUz<W>}d1_z9b;`em0u}DCIfbCfi+M7V$))1zO2w48k%AU3?m|?N
zPCWIQ|9w-|uD7=@W6SjDJy-8M`mBm#{4B0Gf1h0<^oT}yB~c(+F~s{TYO(T=QcR7<
zWg4uyW<@Q=wmT>X|DX(4)1WE&Oi{qMEVpplj$9&2(=)*AQpG5sVjPmsmR?IcmtF-y
zsbBB<SKlR#IaH#|U5cVRmv--54+mL#f@>cXcrDC`{<U~NiwGuu2CD*s2Jyg27ca3o
z<u85eA+g!o&#)(w4KjL^bqL?Y6Pu9`Go28`;6&xXiU$_NvD$}^q(LA^!jz03{aX(b
zkC=0Ba(tQZiJ7Q7AA?GVgZaG>%p5N6QjTUb(L1_jbX~v<s>3lYn?uPhb5y{_fdoP!
zE+%Q)g>!%ci4ag=&Z*DZS#A{;<cxK484D_50=W?=&zeo@n)%YFV$Xf8r1Ssn@6hU%
zF0_4wv5)%R(e-C`*<T?Hlv=cX3jdl7^PyNz_kidfGfNd<ZZ(*{)QVM$Ex24GD50|q
zBAM726JnT=mp;~bXInll2<FQuB9?|gqCW~P+OrTLgR;wMPRkM9cnwG2{DFrIy#_nk
zo0wNAxsRW@apyy0Qf)Y&${vagY{>{oTs23-kT1qln1}5&q2&$Pt<lkV%a;M>vmp!X
z8V4f{@aVu-UXxd6O@Pyph%hrrTlZGLdn2wLd&)xkU|eR<GawFk=k0U#k7Tc_l#P9w
zg~xkk|H^ZB9^GZ<AQg&R%wMAYy*Nl_jCMhs@KWFxEBRC<aNwJ9b5D1D?t=M{A=I|^
zc`WX_;~-3@8Qia)wQbG@q`TqPssL5MG0~a;nIDWnanh}Pr?7!R4e<rOpXx&ov2w<0
z`s23RJHAA#iRDAdTC@SGhT1Dx1n3`l)Nl@|C%&+O^2a~{^egsQQOHsj1T3zC(~0Av
zR4(!(RwGrlUoHw&&){cbO+7{76@oi5QV@8X;gkv|r9|_oI!Fq-%Xj|QeupjZsO}in
zME3TMKYrur(Hm@e<fnP;zSo>~ivx<MQ(dZwwZvS255L%iq_S#oA7(KH@Sxo~Z`oom
zC>Cn-WIG9%64#aIQH)~v3}1t2VR=d6EIVd(M4PTBa9HMn4}UB)n1B0g-_06YvT>C&
z0WM!X?(ZJ|(2b)J4du8xE!rRikud^Y8&C{m<xH2U$`3Hcvz<g<JolPNM@r@lrDucm
zYon8RpvcKw`Gr^A&Q~4GVW_*wh$iWcA4LWaa5&$q3U81Dmjs1u9+2t%#=rd@R<kwp
zK_9HMzvtPj_4Q|{S#YW*2w>@y7sx0k&H02xC-+7=Xb=2?5M$MB0mzOD$HMfOm0X8Y
z0(n9d$M$?bY*kSQ(nG8Tu?T62_lvR2fa)-<Z~FXZwbz-|0o_~7&MaT}A8ENtV{Gz(
zOAlqI-1F+kw^i(@+AZ4KNwex)3?_;bx6?LN<dn*n#0aU(=5&PTtFF%2&O$hI5mz#@
zwCs4%`5SYQqH{3~&T<GZ*VQNos1c{f@t6oZI0Pl*g{r!GWcUmxuq=p`y!w{Eq1!wg
zNq@p2I~2V~@4IpQv3O4U@v8f0?qXFePScePDa;%-3t7eG`JUh?u2}21cSf`=SLizR
z;S}03c%9a>pP*rQVK!^-uPXqyor#_`^{_Qu+N@4HnHpr$>5&ezBq`=-yjX0)hTx86
zzkCnhqwJ-FqYq<Tr(B-VI>KfwiAXsOy%KDK-lGyaUx%Jlg`=~y>0nG-(hmZkUZcI}
ztwj2)CTpjK=eDdp2app%C2a*^FKm;^*pRj#r)d)vGtR#%N47;!NyL1D6Y3xyJ3Op#
z#k-|QF_ix#$NJ25D_PlE5*VlpFBW4ZCgD&je;iNA>fwn>&n&+Hp#z`fC|pi58lg&a
zgHD12-8dyJh8cZHp$8g#8Ao!S>AI24N)!>;vEVa<q>&md$#-1wf#2NZIm-32X~pK8
zE4%Y2o{qDrn%{F<r#c`B4l_#<jm=GwOE3<q?S~ZG)xK99wpDshTr3A79HB(Qv@XEL
z!o$;AjZ?2((o~l{XW<aAA;XCJZD<qSD0U)@#C;ooNn&7=4pR}Wo&Tc{CPc45QDE|&
zR29dDA3K2lICiIt73rB=vfhcQXS}X5F(^HzShkc!5h)idQaWV|^wtx!k)Dr@1%h!n
zk1*&gpWp3>gKmh|8YC|<fP?{?Dp;naPvb{jTBp>SbgLMIw~fy}_c|U&W0mqq(Y&TE
ze>%SNQ#V*g4r^AiPHq>A0B92QCGaIyCHN~OTmP`%!zJG|!~1P>mjz`S-Gr*}Yf&9a
zsTk-G)&TWO+n{x~2zyyHm;D9UK|B}839VSxE9rJtg^zRN01lKHtmB$bW^cG~xhp$Y
z`{?kAr@6f}*FqP7qr5v<hO8^=jL-GNC~8q2BeI^7&0mh%ssrmB2+K_Di)v7wq+a3~
zayTbqZc?;W2(V(5It!Vs0IfJ4NE{@a<lRG8(GRDY+`%R@@-F)Or1OB@Y`C%GnY-lu
z2X>v~PwiGCT1Hvpds|(d(|0;u0{xhe@c`ixe+Sj^xFFt)+8Xk<7%fvaCJR<$SW*`V
zY*JgYbc9;wH4NO_0*vsg5UuDWXp-<t6<SFh`Q>dlA^BS9jkgU6)ZYlUXv~5k+n2p`
zlB(lNH}3SG8N206XH`z)9NKS%(vH)ObM3;FFRTCXX20b>1MZiHv^E7$Q5&-3Na!qv
zJfy(Z3C-e@yX21`0Qe+sP<{#f2FK}-__VTp*KfB%*?K`E!O|<GK*%nUx(ij3B90@_
zb|<%vp7iPck7B-QMJT^ZW?al*;Gztjvjp8FRDF8XUOj5lx>%vIOqvt2(~--hl}$lj
zj;N_ra+0<w_|1OdU<DdU4rB%pH~}l)_ckHDJUDb)N&`~(GB?E9=fBtL9Y#Xr$k4}^
zFPGQZMKki<h@NcTtU}o&&||uKFcOTZ)iED<8RV0s#sXixUfoA3aWu9M3DQ7B*vVOs
zB9E`?X#E`c0AqSm9djMxV@<na$&?<gxx9~#fp4_dlL#=3Z+jayX9UpYNboa!TSk(m
zUD$dZP1la@7|@|{fm=#&a!bWdbZ^s}&t28kfzfTz$Rg|nFEzaovCPC`V_wyyl%EGA
zvamjtMuE;NP%?h(iVXlGVA7A0#i*z=djF_P<a*bQ?*ekgma<DTnH*o*ee0daBiTP$
zXN78Kt1j=64`eja1><Sa0yhfS`#M*vxW^qw{z`MG96L&6nvm0wo^ezz<92*T(5^zM
zKi6zQyc;u`N#z@W3)Oq$Io3*s$(IJo<VIioJpD#n<T~ENBiZ|Y{N~*|PmVpaDH@+T
zkD-=9$~5^8F_PqL+;-|r*-2X+c1;?y%2BYuG=kHDm4X>kL#r|ZuUUY-Y1cE=x(oPe
z0H#WaNQEK}O9_hAYvud7q6ZJ@bcT+_y%0Tl_3j_rJhf#{2;WQP$DX+XmQBsDF6b1J
z*jLbiMjW=`ABNLavGk}^L_qD+(ymjlnE`lk4#<LBh}LYL)br^udpN&ec4v!&&dLEd
zoubx(Ni&2=){apQ#&Nq$tc0z6*k{clUVI0l!*|7P<k^=;N`LHzkokNuqlW8*n}SXv
zlK2k0nEcX7aQykG@mey&4Ei+^9|Ta)C@)$Upg6$187^pG2+`p4G6K;m?HjzS=23xo
zVERS74-Q(!5(ddf&#&AkEg7;m%S4?p){ogVXAti8;%<l}nFTtC&R=6c>#Jz_fz&T`
zl?%kV!zS=iBDqG!WRIGXCx?QN&1WwalrmUlOMF1|Lsbeg6AUnw0bjq65Dpz12}C>G
z<b3=0WCWaq9?yXA^DN-Gm3X1I#_tU65YD;CvvzX0Hk+R)Vd==;Z+XrU6?Bdz$#EU?
zjAug=f*{<Y83H4sFp_sgBvG<>Bw!Uz2Q*_`RRDmj?yY?PVk^&iD>WxvYzJjd$Uf=Y
z(xXE+P_eu4Y1=HI>??61MwGa!XteTAn9WJGgLuJ&xga2OFiCxlu7@1Ub$w8{&42-X
zd&Qe;-^F%hYgm8e$Eno7h>i{kJX#aX{QO`1Fgvm6EwZoS@@2!j^FyJU%x^}4G#2v`
z@<O-?FF_oE9#_%BaDXvdE8rLdg)|>w@!0k?C6yAIN>2Y^b#>t-^a7Si=FHZFRUFBb
z3=t9jA?5oRkg|NqsG$U{_NLGNF*=e*DaeG!@432nba|J4y6?wU=(S((@LF=%%0}@5
zQYapnN{C1mnh|dmd3nkOwvGT@+)y+sx`qz<*{5w>RXoQ)Uwag4QX}|8d;oS)dD92y
zoRge1<FZC*Uo^YUAFJ1;hhA=D@hCmI6g*cA;>@YiCZ!x?cSVMur$T^{Nir|E$R_@Z
z=V#L@Mi(S#d<R$JwRR{mu`Teauwk6H2e=h)1@Ln8E`Kz<f@KbQhGu_&W|!qD?P1~;
zE`SLS-^n$7k~2%p>VYe}R>)lwx1v=@oMa1@9T1B-3Uw>Vrlzbe9rFBF(9W7u+>Kut
zuLr?Im-x6EW1F}J<C`<6z+wd!kg$Ydi6;=@w#hSpKFug!sTD-?pv?S)U=ni}pZ=W<
za0w<O9L3z(eQVtxvjE#sRSl6OPpJ|l^48Hwe2Q5jH*nkPzPK-7Pq&1*X+n%9!GY3=
ze1gp{PP#yZ0TmK#Cz^)I1M}lB+k~_P@Ykgw%Zq$oZt?B+aQe#5_7xHaU%>msZuKO&
zlLctE!etj3i|X2M0l<XVH9dmG$Dv`Dqsmi=Ijn<#EP;l!n+Qk-<$hx2F8EI>8Trfu
zd!jpuSG+qQ$qm>>lv1%LJpzt8R?IEc$@%avVJ&GoA$FybJ8urQ%Yo|_1*+-TghN_I
zu)L=&pH_JGILYW8QZ?tQ%vhs5;7}3_i<=>e0Gz|hHe1eCT@|amqn|@}mBhxxco%HL
z>X1WkK*-JSg^K(`b6}JPMy`YHOW))$5jL|+U?#%uswZi{WL?{NP0*3b!8pt+HWLug
zbF6$;%fW(WJ4_d|j-L96yoOE1{t8Wyj}AS|aX)Pzt56Pg!G)qlV(sw?mVz6C12?@!
z9yA5|q&kGCaHsQM`RTQy_J|HMx$~&Yrf42a$vrj!6wRp-f^E!@IogtNNVqhsSkJ8#
z8l=_9x|JnsEbA&*WHNc)$AOPmX;Br3>$t-jcf>TJY=BmfX)HULDSqb5q8clt(hQys
zY!CCF|LlRp+N7^55!dU#(7()+L#ilD0K;9Z?W_$=jl?Z8#lv|Ox;)EeCtntTS;e2J
z30;Ei7!N2sIk_Koi@TyLEt1d#QKpa~rF_>XO-4RKc{3jWrlzGv(Tz;wvrhrwJhnXn
zSF1gRcLh(=;+tnNjzqV)Ipx^}Fo2O!zR(k9D%z*cO9#{WB4DFiK-49(o?NEyi<O9R
zpDKFlSXC1{i_>&zte50OE^S6Lpkciqw~p5oXq(0w?u(w-di*yZ6a+vP`&hZV=yjK~
ztv7=*Exc?&;R(~p1zQt|8&hD3eVz2qSe(oj!zO0sXx1ar8BQ1qYNvMQ65<?es!s3O
z5V>%HkuNNWP@3);glp|2{B@jffql-9J0Q}xf93%>s{^=@sCuA$^NkH)c@$?9x$ItE
zNkd*1zc1(+D+JK>z$c}IQ?H7{W)<dJOK5M3>qziP^p(PjGb=EP`HaSl&C`OYufR2B
zTHq2BqbKfT=lRQCQ^Ctfg@RpLh2Q=UzMJZWPA?0g<>f2e?nibf)f3p}W<WnnW?C#(
zA$$y<kPk2#)o7GR1B4Y9Hw`TSVU=v@vRfoVCQ8*q!r(BTI@SG_PC&5$FC924v%@$T
z7NEloM)d3FH@)m6_o}al&8Q>-L1)}V!0hiA>=k85PAWK7?9aYVJw1-=d!DNndgaDn
z7F3#Cz9w{HK^pcB%<o=WJXQr1g)7@}@TOb_;zi$~1~}?8besJGS}1*h8qxx4Fg+3`
zt|`^md=R<5#}fb~4Hyf|aUBfC?{f}apLNIn2CMAHec4aN!cj#`FL@$$35o=MkZbuh
zT2T_BSx4dL^-EqGo#pIQ%SiAwxeQC84zP-nO3j_P+8=vW7Um~xH(<9|zLpKm%M>XP
zAU_^~I+#Zx?5=QV|H4{UOUic*#-IK@S%bv(JYLzy=Xcp}AWLpbD9Ng`N-D@99xu{i
z1e{PZ8+kOG-(=sRM>LT3h)UL(FYL{5qz@K3_9KKn%Z7kFqVqnAM`377UIU)~r}<8y
z%}i)ZJKF!~bv(Lx;a=kMw~qJRE8c|OD!vn+)Qy+Z7Za)K9HI1QUK?>!MG%*{*H&k)
zQy-uYseTb&ctoN_X9hHC2Of>pdDghAZjn)Jh76TU#0qjrvfzCx?P$#6-<(p2U=dH?
z<$nL~JRtvCzeHO%5zL$4JZtHmFHV<5E)a)c7hWr4=^p?Sh2SXgB#^#2SOPnMu1-)4
zDb$32V(RuL#J|#@t23yJ03ccujq!?nc@dBlLY@5FUCOQz{UT4N1Il-LfaEH*w+E{j
z({l0#YJQuw8eEsWKHSQ6QEh9tC2DzE-wCHC{>->p2MCClxf(5i6Go~4@eu_C6={<f
zRC77@wNe6;4_#<uj5j+n(%k8)F`az<gAD{)2o<^T#g9FpH^E3O!ysi#{2f)^jKatA
zlc&OZ6a=!w3d&wMn@N(S#`k$dbe<Nsn*bKy1U3a3*3viTfud@JN8w%dJ~5Zo2SJK5
z^z8(9_=lX~!u;z&&RPg$I`hjcaRDd8_}2gRdX&XRCJ4vX$<N*SP)x}JjVjs*knWhN
zsDx~MF`l+M&5)Gmv{ZA}HS9VZ(U|Xg#FB(AggrG$#ynCr=2x?7NqS3Ixw8;1Ar6+9
zQc2YN<1#9JUj<&C!86z@)ziI@^ZhS~Gobf=e`3N^(d)=hy?RNpk#&%Npr_z|c(f#I
zHUT(vtN}w;qAevu@#q05_5viJnUznC!2&I-EVu8UEr{#8z;jO++Xa@GhRbtR(o`P7
z06VN5fUIe-gd?KoPk!VL$RyvfAy6H@?dJydVAZv)M}r+29cY7Tor8jaw6f=pM_E(T
zLz}hp43UcrvL)`mzN{jd%b#dWAsr6Vlk|QJdVx#_;3m^xSh;ga&R@?!7K$jm=mTUy
z-dXsuSWrOe+c&lns?+3X53<aXn3uiqW75vds;a12uj~2rJQIe~h$xRmNl%_~m$d9<
zJih7GnIN{m3b8NFrLjUu88AraDhdZxebzKF2;3ZWL;OduH4$r<gtJM(=qResxFJkt
zg$!neZVwC)AAQ$v%AvVCS0!~JToAr+-Am^qzpa{Lk+D9tlq|@U1qZml-kL)-SD`-N
z_q^(*W!S^f@?3VDh*e=hsD%A3KF{BaaoeJ3r^HS}`1DeST89t9p^t!Z9QNlBK|G(5
z<w1_=K{}!J#-IL+@8-AkQh{1q>_3RYx<1QWpC&u&nBq(L33ADFAu~MaI1u_ll(%W?
z<XecQVGNZpTWwU@&RK?B;&270wum`tJ1nJvDtD#4qGQ9NFgh_CMbSi_Nqt~RyW{!s
z@5$!lMD{xJVDCnF<ct&6IE%J8Yx0mW*aoLp)VZHDij5$4;O$v;Xg^lHgt4WU3^=9Y
zLD)$CK>TUOdg)@2d->wD*rHJ^2}j&QOJu;)iF`%CPhA{)WD^8vLFzf0X;1#JboqF8
zmK#3KE|~4z;}7rN0afU{G_%$zK*nVd*yvwJxhNF)!Qg0&EH`b6j&_jv&#8}hi^Wle
zBqc8NS#~GWL`(04^{4~jq@Jy3AS%^k(Fdcxbz%#Aiyf*Z=E%LInl#)W*|FIJW0aS#
z;@K>+WN$m#hlspvS5KwsGUtz&M`v)U7!r)gbMPqyG49#TU0Kc+R=f5aY|JPsX2si^
zD|J6^W3SHrB8P*dG|PM1Q{gDooyx+!M&L!&Nc}k?rO~6|UMTewi`OL^$p-f$<}Q1;
z?tB;)HCHP_tvtZwFjtg7cGFXUl~Od&rBSgNW{r0*+`=(RxkNw%U0wK=k_Sp?bMx%|
zOLji%<x6svb{v5xd|5~s0p@{0kAY`!P2}S9JZ<tX-(c7rD|E~*tH))t9AL@1GP}f1
z2uv`=3K<Wa$bkSQ{2twBm>5l%c}ovx3wc8*g-{tJA|j+kBS#)onaX3*5KCu0UxHaw
zAaByxp5p6TqJeh;enVNyQAcM(Jm6h_lbv726>emTl4$vACB=CibPiOf90_#s4_=C^
zlg%PKLrHVx^FZMeE#6IWc~peh_<|5ajjnQDj*_aeeJag^)F5!kt5{jG3$SViL^0gJ
zsUx3e?+AVKtIp{4BG8{cZpuDdiXmtri-||V#NHHutCXW&It0{((oqwL2{95uA|8+1
zQ_fnH;seipu$6^Gaa0N>M!je?a2?l<)qM_L;|g>Zq=A4;4<r<H00aGyGLP;&>;(9l
zla_>I;$O%{-u}8IBtt80`#JW7;aOFbDqIWSnIT$+I(kC;gysmHjx$w9QRJP>r0R1;
zZG<{n)9xo)(|;&^l~S{LQ2<+EFC6x`MB+?R5maBGo1VN#RL{u`sEk!4+0DegjCZ|A
z4@vBFMIH*=Ra16P#qIzQ#nZNcdO}vassy#z39>Q5mJU}nUSv0n){M9cTWUkCg@VBV
zI}ibk$=YWx)G3!FFFs}{Bpb&-12TbwVRJ9Gf>ppBabsTRFGiGV7?OQMx6&hyZ+QI5
zPW+iZdI?os0L>{d-z^A%yhmq=xytebe;|Bne#p3JjZ#rk%*>bdX!M4R+Sjlay<?YL
zPp_t~@-u6dhwhA(ejKC8@is!zpdmi6IOXP*u&7t0$Po7i$h7X+i2R9l(N@0EP9Zah
z?s;ZQD`b(=g9W%W7iAzS1<Bn`Jb;qVr^UR>S4n+9_7*4Pj^bn5j@3T2qIRP2WLli~
zen&AW)K5Z0V35#cG%E-K4mI-aDzFzL$w0U&c051%VSR}_qvvhjz~}vO?zbk@Ha?%p
ztcWCuHB-T2Sk93`#;KR!_w5ck9$G+va8wPsn(B<Hxy6Ju*vHG|lI1;TCNo2o5|5+`
zBl6kjGR;l~HriQsv-*@!)NbXz;UXA0Se`@Ncf1!kHj4&K3P2Y_*XdCNOHWB+kf$MF
z*ZX|I3%!!+<*os6VJ@p6^>JgcR4a)X6hacy$(HR|^<jex9fURUlV$Kx6e@mzp1jmz
zK?B*-vVaj5xok0F_6&3W#aQ&TZLr>HXQl!_d8!I0rjIqkB0_<9Uz0d;#ek;KIHK=T
zAlc%SN`h_gOkX4A8r{d96~b$xCeG(C@tEDrnE|;jLL*IL+9--;5k{)_qjHqyemN4%
z5MvnM_Y-nx%7#d6Dq|-+c488`@8z>5=oYh8u<9hqC0v^jd|X6bPhETyx}xT*dmVlq
zET!7*iPD*rt#IwYClmTPoM_tBdEU9R8s143<Qf4M-IU@qi7{&xRYL{GPtE`mnm_Q^
zgV<zJ_4%5D%T%$Glx4A1+=NI%3a_)Sr(>O=0Cr4AVSv#_@KRzVJt-th&e9Oy=0_q^
z+?yBxg&>>zM19u^=2>Kbl$qt+G+|~eWMl)!sb0!g_kv`&72w+<(0TQ&ED9zQQ#xwf
z&$6}|g;nIWvwTGfAEZl?E?_Ma&=&Db&lzNhO+i4<R&nN{P&r`Jz;bep1VMnnmEW}a
z0CKeoVce3j#M2}r3wDtb?5R`Fy>!;hNb3RJEz$C?{}b63BFhteSF(DxeEgXxDCaRt
z;KguAsX`w}!id2L6Y?KRXFR@s6V~B}4;37q0GQ<d3VAN}QAoMKA4$12{i{W~VnLc6
zW2+Ek)6|RrA-7}u((xk|x<dt}XBjR-MNFN&D!;siOng_R^xUqR<A_~Fw8NZemE(&P
zbex}r6ES^ZpM<W28x$a|PW@u&ITrj)&<|&mAi|OOGZt))AhN~ytN}^Ec|jZgU>5Of
zs$tq-cw5B|&StgZD2j_m-+uKyM#6zWge$i?CIWu0`Z(6R>75j9i(;0+(kH))=l~XK
zBKW6i9fiXR*U;y=&4vhshair?1M{b~=cC0a$xpImtE0iBBT-P@q-~UNZx%Rg)9?{P
zUgyqzLLFy@4nYPuE@Ch}`tg`mOhAuTT$lF(!^cv<y2J)^24weHCvz&6^0P%=4B=wv
z1Xu2@eTQqPz7BnQ^6^7%IBc*IZDQ%y3Vh0KSt|7*X1>n`N()E7kmeWPN>N2yRLLtn
z@<Xt!qM1~+Ra?%CTozx~F^YDTiDXfXoty#+UI%%&7}5U{BcTy|s$!I}@<Vcqm$@lP
z1E1(PgG5LKQ$k$$vb-RZWDTSA^|9k3q4CrI8C&-^46T=n9n8<Du=+TDIKOwM+Wl@J
zx06SCb+<>u7@=;!9ilJ=G3P`cIg@nfkXp0?jf<3^+(@<-(O9X|;^a10u~C2)4S}vr
zDOwKr1!Rc9E}B&5yHDaTL=~ZT)Q8(Ss3!{N8IKXtLzI<&{Sbr36G*TKPRRosB&xi6
z&`@a+?yRxRSWT4R!=9+xWE&IYbM8Zm+oGsa{Pb?o9H1bP+7@&&6;29!fDKsi#A;<*
zOv|!KJWT4<|LXVA7wgEf=y$Zoa}G~mk$YxU);4Fw0?M1QDl<z+FqogbC^Q6?Q~`HW
zm9~|!Di*U~rKyFD?J$eT<vBH3+{qhq1=4_0NG{<80$~{VB>hwxGGH`o+{t3((`&Gj
zUcw0f_rEdZ2?9gpc3pg6gRF>Iyp#RH>K1p2Ek@!;w2e5)+^1NpC@|9a!F!#%I0(gX
zhSWXWjx0rK9#BtKS-v6yo50?ZVh$ZKc@jO;!)BK<E8CGzRb_>4W?@cw_k8{+zeU;V
z0hi#dKtreSs?dgx0*1@)AcoitD463KgP6S}^}Ma03X#?xIzw(IL8hf~6X8ni_{kni
zG1<_{g_~ejc^`4a_vKC_&zbN0UNub%7=ZM1v8jOE`FlS?)wIq$#;#+br+{Zai08#f
zTFAQm(m7m)N*q)Zxh`d6L$S*OEK#KW!_e1A!VoS?)C(VSYr-C<r0hM#>S8@^iA_Pm
zkTge{!Xt)g$VWvy9EZ?fe;mPgm_FTVezQ>%(`M#<uLs6k`d(lV>cmzkvQkkp6+OLj
z25>D_g%x5l78~J0+Nz+h%g$_;0S?3ZWgePrB}DK6dY43+)&sUz$~NhH&V3qf`LxcK
z@Z3D(0-aia^b_oy(l{UngdhlIVLt8_y$Ff4ix-@iIpTMK3hz*$nDon1=`gE?>E--A
z77~A3Tj;e9zV`3C^6e)(JJ|lH4<^<hds?`EIxk!X&eHNU1lAZu`>R2uDIO%K{D3T$
zwztXeY(t<2!SFdaLX1h-i~~3jD;D3HqFWrSip42S%LYeTTLkPwk6bGS#=udzRf6gD
z$cN(TVT>0)4f+5(%0}a`6HZK;S7}k-E_$nFQIFtEYlnk)!Qo(lbEHmdD0%x*ny$K>
zEyR*Ca~($7CI<D1Q#w_VO6T(+g?_^wP$$|XtVyd-;LUMNwr4LG<dkg3hK9A<{=m;{
zqB8tL(8lmxdGc4*G$HZQvZSjf1QkTb+wcp1OkA!~LihHmtUXvGiJJJ;<u}t5d|R^%
zCKx+TsuqnWJ2Ds#S3q=3hh(4#{Z#s2hmmg&<^k{?Zu!1!``0A>6My{;zzxA-ryDAG
zdQ6CqJ$If{<3cZ42w5=6qK9vQ6qI5%T3APWL!}lJlnw~9_H%-T98H%mF(K*m{66Uh
zl1|}@@%Yg&U{~v5h;bGevig-y0jO|i#GU~K=;{2~AJ-@dkvENyrGKFiZGKi~DgHpU
zf)>`w5=DtujbRT1(uL!tYzQv4IPRrny+W4o#jCInWS-6(Fz9h)B>VGb!yazOAC$yh
zTv=I5vq8O-eocx%i3KY}n4kPl1#tNOh9up*F@G{rUi~s|MA-6t*y2<NH`)=q2?I+Y
z-yTg#Alu`3Jt|DXlmfJez!wmxHaWX$e~ho8!7Q0sNKx><_K*ZX3+tOezcV1h#kB*T
z0uo7H{43HRb@^5-!ru)yIA?;^TzNMy54vG<>f=J<LD-zK1HT^7X!qt3ZRP5zt|5ko
zEM*hbf4&eTi|&Us64GK=t(INR0zB<xUExUdn6{c)hU=r84F982W`S2^G5%nW9=v>+
zk)AmwHCQfZJ4b<)c`jlxla&)uu3TZNh<}Cb@{yWN3d%B*nAek*k0$6uxl!0o#}R)|
zGt|<IRs0TOOPG=!EH5MGDFA&Dz&LNe$ZzR^ZVN?BHpgrxtlB1EE;0@6bGA4X$^ckY
zIT8jltXpo-tn$=f=3rujj1nf23pPVXR`b*5tXIyc=VmNR$^g<KF==`dkr<cfCKqlR
zu&_vN!iSA-{xgBWvQNwG0WJ)WuJiCf^-|k*k;HdaI3xmYgn<O&Bml;u(M>$IDct!1
z{5l{JYGJsYOjv;>TtZL%qydj88`Bkm*oe<^g=Ad2ipoQLo)$OdP(5AcHoz@Jk}J+n
zzsAC)VQ?ItoRp6{s3W$}!mFaT1<`pXj(-@>5TXDrLC07C?h-X!MQ+0gJpClGzs^e{
z6Ol$EgEcxdQ534TqWTKmEkqK*WE4|WB~Q+aIRgkubDA@K=!it3@#TLi4aQwimosDJ
zK?K&}LtJz?FL<UgT~aopaPG-f^xlk;D#fc{t7RbV9uaF@TWEu+ageaG>)&TZ<gB?1
zL}qrKNov-@5Z4JUG-pulhpDot9c&y+hCYAk=lPwGusxKL_CGU^6s*HJb6fZrTbV;9
zjU#g{`H%#m#su6Z_JES}NdBtmQJZfO(vmb^17ccU1GIw}_r0uFu<_op2uN*p2y0?`
zHJOjy9%19GP=6K#E0iYkyh{!+NZ3Xw*pHdaID>AvXH7)I<Zfq$l;Gs7wP`UuXcLJC
zRX1G@0q_PDmyKwc1ln5KU_x!kqC9Cct@iK7ENYfAvHDcoDi;k==i`l05N>({mR^f?
z6)&=|#_>=6M3NtuyzzB5^c{7BJ5J?9^cB>qQ@}~jr&}jA)I|>TaF3)?+G(jDdC(?}
z-9^s&ay?p#T%yj`bVd8ccWJuP=>b@ZX5_DI^sQ+IcLGZ#al`K5U743}6|%t`(KH7F
zO^x&EWy$a?nC?&^+7=m2c{#cQ+jWp=C=})LuHwn_6a+g>HSnzaiaKj2$|?u;w3(Jg
zF2i$@aAqJyE^eY<zR#`;pNv4J7j!kg`Ci$ZC#OX1c@uN{#?LwM)n<tnnt+`tIf0Jy
zxDv-9sG$0qU$8tt<<Fv+&~NdawK8bzV@TPvo(=L@k3GJDgd{N_o=O;zcSnrN!Ka+#
zY$RK2vlyTFAEdytkAST-9e|6b_aG}u0emf4r&~ROs8UW!lpeN^Z?O@_X>ZFDmq?>s
zVJ)j}Cu=5D-z*PVNeXkh>@EhDeFRL2X=y(YASNBB7LCePBB!2$Zs3H}RNwfu*GpEQ
z>`?Zt!E|quRt^uLuLK?F6?4deG^?1FcsX=}<xGNx2!=^iaG{wy6X3@YG+7cH1ZoC2
z%V9X22Y3K<ME1>V??fArDOi;sU`Fp`kVmOKs}GP>=Z*87w~GZ)Az#E2vAHqw<~82S
zI%n?Zp)~lp5gjTaruZR^H<n*$A+)n4tGb<Z#Mak{|ATE~FRMwXPWAFx&hb1TQXwbd
z;4Gz%6~$G|i`8~PoN6kwrMi{S)dGF_(gSdbWRFJ!X?z4c7Cll;m{Vqg{0CaYqD5(n
zm;gE^W3_>wx*{-7i~3;IQ79s_h)s_Qqd6ctVC;Jj@w^>%%iYxyx`9M^n7EHHHYyt{
zh}ghJjYQVNouI8;0q%VHXKeYVD?*53iB`=svNJiXvhr@{)FWy^r&qXQco_>V*@`Zv
z?1FFGN>D!ob=)l>FWe1lh@K$#p);*~veJFXHrdaW9S1UwzKoWrI3*2QKy@6U@zGKM
zha@4{{``+_A`rb(*WTl?;_H`h96dp|`eqJx77Hu~Axyz$(y4$s98nN+05J1F+q7QN
zUC6tJ7DtJD6G!@<l9%L9Sc6ZpgpeuW832OMKvD!DKf01RLe72o<bZflg#`l}+2~3{
z`z_Rv^pDXh>ra=NrWM!~ki;SyL|BxI!NtFAQ(|8^^?np94hre{JV`?p2Lx(Q5#u3^
zJfllPghvFYJPJ^b(tNoJv963Et}PunKySdqZc04})Q;#%a7shMEsP)d?1Mr~`F>hb
zyKJ1fHIHIc!3rrPOY{v=pmN;{fytpLhuJ9KYu%FDq)Ye$?~CD-AeBgrdT2m<^Hp0z
z$0<4KB_uKo_629e=iH!#9S8itCTK8|+~sxt>__B*HN(A18bFPE-h4Ye9?0fx)zS}}
zQNs_ZKzm5EHXJD7%BOieeX#(X$pTrx>Y*eGEGL0&o1|SUW=Thdi{kznRzD4!11Xhd
z5X>(xJ98A@L&D_HmSwNyIr}a-|B&Ez-7D_yVDE^mn%2vRnrcZ9<UX8QXB(v8R9!sV
z1k4QRsk?=8NNQq8SP|1naON@0FCA9i8MQVpQ)YSq(Vi0htCVHN!1Vw|QxxrM$<Cji
z%8G<u_U9WGNXONFOt7j&TuJkm-Hxb(yu#JsA?*W>evC~&h4awcr`1rC3^Ys$1d*=C
zA`I~2-W%Toe{wLfqZ6V17g~Tu*#bi9$B;g0OG`oJ@J}DwhF!>+Kg9Y+0-qvgKkilF
zX`KgwFC+zj(fY*91I~O?QaO-z=_}N;ZkAc79JS*H+Eefr8u2U-v+DbxC)=f2D8oyL
zhPCtRNMa`eJ6pspy|!U_brv==C}GA$^1{ns{euH?I9qS85X79AalChB8~BvPet^L(
zngf4T9)z==Oi@yzz%{t(gO6m9rL2IBmh^VmU1#yWram4XC@F^B4vZuqdXK_{PD9Ya
zrLB;NZ^VJ5+p3LcQf<+2ilVbBzL!GHM*P39EiBE9UtRtHk(NyQ6V>P4&p34->Pi!<
zXoHTnzaQAOxa7Lv1|AqTW0gXHu5!oJ(M`TW&5X8oD=nP>vrm)vrive=RLDt?ER9Iw
z=e~NP0`T0&gy%sI8Xt~of#u?P+>FP6|3prqgEd~cN@VU(nm^*xRJ7RQAILqIJU0WH
zh<^zWK%w}M1)9*vm`7+XD>729rR~N=Yun;q^ysLR<}WpcTa6?w>kKCtkDnTf=?-FL
z#cj<22XqvNjF1Z|C9nQg&7MEZ$rkwS-IPb;s;77FJpNoYl7lMf9ZEr5&^k2G7Xe6w
zNhO1HG&v)ijZ$fK)-`w%xo0TWl$=1MYmLDd=*}Io1L7=KC&8)%Q0q}B$xhP>oIjzN
zFy_~YO)f#SlIAMrmc<li_gnw{>!gn7j(b=Lj*VKOMD;ztr5gh&3Y{L0>~KpIrcn&p
z0!8vs@g@hZw~wXZDrkQy&65<#h*?IE(Dg|_@qpaZw)>&$vKftbB#tH^C6C2;v_xDQ
zjZApv&F}Iw!-&q8V4da$=kNR_@Jd64Tsu~@qUnGSVs9b(V6G15fr#G%jv^elm7ml>
zXY3yxRIjvE<w1VJtssN|qB)(DfiHqVc0okcTg$X*XH5qDK@%_BTi^)+@rqH2GWNrs
zSLIN@&`QH$Ew>a>a{jKL!uUH^s3qx@?;S<t;Xy14{C|jh8|XN$>&~;P(4yNi?VyVY
zw%qno^<EcRg$78GO^v1x&+Kt`p+z^_h(t1)3^yMmvcqUG*d(?UpTzNexT?Ac6(LBX
zU?<DTCP$5C8>fQ<%M_!`cxRF|2{SQ_D2b(HVr4RWEYUexk1{iY7;VN$c8>RV3!vrL
z$;@VF_iU2@`s3Am_uY3t|L?x)8<n+rB8$cK7dCp$E$m1>(*sd0S=)--B5qG*^^ur6
zh{ti8OqRSFRUot?M7G!@LcTk#3iqyCSk!wKm++_QR>~Aa6Btw&B9t}f*|uN3G2h>8
z^<IELWE<vX#1(&CL=%Q&Q)z#y1NSNj!Q%P@t;OLBs5kBhDH6Vr_w6tb6V>GBk)9sD
zwx(Z09pa5P6&rM$nGw7X)m*tb13_6@tW?%tkgsn+(!_NLSq#=Ps7RQHbLGYLV_SO}
z3p%&**|PF2i`*iZfNy81wD`nhG9Xi}tgjAlhJ@BgG&042NE1N=&LbI=k?_hO!36*M
zqG%^u*eJ1xcoxpfdIB*D=;y7r)`m$tK@k$%Rc0ZPaAHdrOW~DsfQ_L?8tP_7;MVs7
znUK0L|D&4VTongD(#Fybv=0Z?ILtvri_3?ajP<U>*FaH8PPaA}hkgZo=ti$aq9kG=
zc)Ty8Aqnh5Q~=icSe%s4Gao72pu%l9rKxYw;hs)_6%2QsBe#!X-wcD|A}8eG9nc3h
zm*Qvr#eNzxMC^LPNEjor00AlymFEq(^*<57;-J++!bO3k6CU_G5JWFo!ouv`46>ju
zv!fcH>=PbXAV{8;{WlzRcFC{)6x?u4;yEbnor1=W4)M7$p$K}GBBj_*Q8+|_9EvM*
zjOa_ij!ooaW(a*d9bhWh+N)S?qWNS4lf&n?VIOhtv;t%HdLA;M`QOQCkYArW`ZoE)
z#+}Pe-Al~1&)4!;GCX_^846ZsEi41oStQxr#W%%gXF(1!0fUIp*8DYG3Hfg9B3KY9
z<YW1F#w4K09#}VbhX-`~zSCLB3xXk!lu5x=kx6k3qF;~(-(Z`U%UA+k!uVb0yRpTR
zH|0OsT)9ss(!$JdE+UpNLD(c+@L*!uW9JpWzwl)o>+S=5Mw+KSH4ovgs_uNm+WGmd
zl!akEWnGYF`Gn#I8I&lr72phBkRRDj5W04o?Dl>8&sR1^I62AzQh0os#F)r(j)13+
z%t~nk%jOb~W$7dA?2F8?S+iQkjIBRAmtt6Fi9a_pp<q(9Fj!P?wb_|ZyneFL3*z?r
zCbPd0kQB+{i+;#9TO~>2GW$%#=7Sa=w1_Xm6qUwle)<P9JfVx6R?MTit2}L0^l)Py
z&x=vQmx~05w&5xvO7c)Fjz7OTSi2MOcWEytr)VLnfV%nNYO^)R9&12iA-7k0VGBb;
zFevsEjm&@#0s#VV(#Q3fX@U7*9&>J9%#d-{gKsBlbxrIMpx~*GtrD2FhitMkDN>78
zYXkkyOHVzPQ#L=^asQEd>otHcl9a9K_1Rtm_%2eLg`^BN*CMAHCh5&BFGre_u|@{N
z$V#%i2iHjC!iH|U)n+P!Pi9Vg`{`308>gfiqg4%~3EW+o$)6kciI;}6B-n!laTQI2
zazf-7vy9IPa~RtG8uE`P;{Zkm83+%BWZ+=EXReJV5SOm)#cWOwBq)VH8Jn>Obb?dD
zZ*=B4iRdMJ5VKiM<c9fd8?yRO<qp6m8-LvWSFIfWX!}$59`z`(Yt0Y0URx56z0ro-
z%t1Jckg%k=xj>?XxWCS6_8XYDbUi@~L{zgwHn{Uusti4f@S1b4fyPnZB57EYj3wKI
zgPS3WD47g9Uweide9U%bYcUsK{6&<W>C5iFtKce&SJs0^I2pZXv6A0tF9D$itUne-
z1cikY#%rLJ)u4yNtn@Zw{CM0>QZaAY`qF}qNZ-7K97xY`Uo5_q0HkJc19=fm5oyY}
z<*`@9Djs`n*k2?6X|wr>EkW^~`9~vC!D44YTq#~{$_>oLQmppZR*!8Bh#YVlP{nc}
zQwTVtf^2{tu>`Qht4t4DcpWH;k>SkbF*&9PhR7ahb3SGV_<^ltu-W$ZZp20wS_pDx
zu#J2!1RKC3wR*ESveZlR*~c87dFW1VQ;9X`+ci@ER<A*-K(x1xJ&@>3WFpAyH-dqc
zMe!;aX5Bl-7C=YOudh~CA6OhDZGU=rL(Imma<SC3;<z~Ame=w7cySyiW&?ppc05)#
zOXeuww9zDy&Q)@2Rt%DscpfYjm$E&%NIYl*&md!j)7;GDBsH9IxxcZ<H)X7EN{$at
zu$N*hclZWVa6d%I5I_J?S?vE7Guc2%<i0&ZA<Koi_H}E1Am5ILiRiELtza)~Y_#(*
ziAAL^(QIOAV-A-EAarhSxVU};*9{V~7n)hq?TN3E4#|yHZ26+Tf>W!tKlPD{2Qs+2
z*jih^!DdC12p`5V7dM6<!n<P>FA?g`_ZQ-un_&7u$^>vD^eEtqQDLcCgnRwwYZd=V
zGP}jS!ZUFTd3=z}u3`nPHgQ0XTsud!)@<iCxSmn`hyS|~ITu2){s_k6Sg|j-SDQjG
z&Ngg;>XX&w#kny9Y(A^RLKBa912m+vMnP<QeHL*{@gInYEV)L;`ba%XNd=9k*ZPax
zZKJ(gbBcE3`3;<Uj0c*VUwwq=28B%aGE@K)h3M_Skh`l0RE>w`7Kg@BuRQRE^ZhMq
zM>e=k201CS6VnW15q$|0G}#9DnB2i@b8FZNs9Q+ha=7B^QIUBM<p!o&?fL975%pj=
zNrfODc35I?TAlX7o_Wd>gSneq15Q`sE|W|rxdoD(1Sx7IqU!ff1)y2%ehq{w4qK$T
zEd*MCAB+l`)+50oeZVpe7EsEqbpQ~!B{@Vai!5dycPeNuL{*aEleo_%-&?=o!bmZ2
z0#2Ynal)Oy$ZS@9d?bFSNg-9Xdd6KpKf+O0Vi3P_nXg~4dVGIcnY%oJ4-ext?9yUx
z3o~xWkdRKSgN&E=w1Nr-pzl|njeD~j=@$Aen4d_L@Df~?S+ADGa$#H-m-eO`E&N5M
z(k#i2W%f}AOwu2{R=JZKp>mUe8*P@3PG0$M_K58&5|?pr;-aTaB8`}P2NICyM7+uH
zXekc@ZZbYAPKgfkLZpZ!Ld`<-2`=&4^ArYfewA8V-<QI}7?*YX>YYA_Vddd}<}U7`
zE4R*yFITmDIcOClwz10nX)YPIkmuPT5S@^v#sjg`J;G;rh2l5;HDa$VjyNGV`P<7Q
zEdX2R<}rxUZulDM!_wXu%M{W`un^&fMsT%8g#Bmx*aD9}Br^%+<IjBXPPv)2!MEr{
zsvBMI*iM_NRj8I)To}#<8yi6@Mv|F2WT6=FcJ&wlkN_}$Sm9n5dqGJ#%aS2{ED=j+
ziNBUa#+rxl#ldg2*O7{0GuR+_$VMg4ioHZ9R%`y*C;duJCWQhDAR!F?SMQJ;@o*Fd
zQSR?^xXU(QA^rU$>?v>x+K+Q2WQ6O)6GYPDWwqGm%7A(ZLFpfv*Q>#6!)6QfAc~7I
z3Xx?Dq(sZ&g37`CDiO!}{NmD5Zi`}v1f~nyNn2uT&ZR1m&ivR*$<H@p3=B&zi~5-#
zcqgU^e)Xypl*X#GFoI=kKU+!lMjGab%`s~{7!C1YxL!ci((a$bCeQaJn_L_;rBu8X
zWEr)XUBn4_>QnQN#Fyte5LRAW4Ymfe8(TmoNE{}fp~W2w*K+d<IpF6_4Mf-;fd9jU
z%q0E2mqnb#p2{}`oNljpm0YJ1uWk0p93<or#TSbtt+SFfSmrS#&Y;|`_|GOZ1DIpB
z;*J>;ODW*wJTa~XZ&!Q21vZmz<pY`+VsP;%Sln0>Mo1vII;>EL7i^(wN#+1(@ythd
zbWJJE4HPlpy^@9}8(U;!>7vB`=?1Jv?imn$l5|Q;d}U#9PPY#(^@%Du1Gc#lig3^&
zveg$;iH~hl$6Z<dBYsI_p2JGB(3yO(KY~Pb+7{NaSH@{28|2)g{wYL%qqNtMZ&YBc
zl|t1%+U>41PRWo%j=WP&L1><n$kP==2~EQKIRvSH4EpEShjVKlyGVF{a4Vz+^^jE*
z_Z$)f5m-{Sf=pEUv+ZoPL7<j)^CchkK{>>w^qOCr_wQt%ftAS-#v`Uo@3$+t5LD7+
zo`7DCgFGxO>|I-31hSQ44KXhwI+>n{9fDa%Oa*x1*>ZmiMH|ev*Fieh5etzU$<qnP
zd(94!%Z*C9_P_?x5D0j}5)!D2mB#~%y9<%7gd0(|+4S5%QbiDU+5XfMmSmDO7nxSQ
zPS9R~y>aZXR)|=_#7~xp2!vlqRu8e4b5_TCiSBK}OiAsH5YfvlJpQ-U3Ff^4BrT+p
zSqxfR97IY`GQ@#4FcM~>hB^pzpxt-1TtBxFhr~t9=qry|;N4*tg?5bAY0=r?Vowwy
z4n(RX78cQDb3|^oBfbS4*^=rLK7hx_HEs)s#vWx)r<J^xtFXP9YGCvkJkwr1$L-<z
zdWbEK{oJk{Hy-}qN3cxXh(~TtpsB^^$o@)<O!&jC^(A5KMk^JpCF_s$j+hWb*da&o
zQmkvbMLi<66=HT`AnZ=)ag-$Ru@Xy*{dSwUZZHejzY}g?NCbVh@HPV^aiDeUX3$zp
z{6T_M67jp@>}7dE6XA;bhyBy@gR=rlwb=t-TaQtG-`|UxiTaBx(hx2+Ley!9)jT)9
zwlyyZBUuT0mI<_LA^9P3cu*mJT}_AWrFF3*_!5k+h!(<!?!yCWjS?~{Vt`>Y9L{2M
z2V#?4+HC*XyD8?u$<j`CtTh#~9=-O5YwL^ceB2_~L;J;+hzijl>?50OM-uP?MK2Dv
zkme21v?W+7%g?&9wc`#tvVYjwN>{hGa!B*uHueGH;U!9@Tg1S}<}H$Ge=S+Z0Bq4k
z0y~+WVf?56Bq~-rN>Hl#4gkoSpa_JeSy(*yEa|62LKvG2rV_Jj^`wS|!w_X*)*?`d
zl!{?1eFn`)M_(;Uky-?1UVD0BeQ^`h3~Z6PPFj%T!BAwbAI$G*lOg4ax0<c3>AlFE
zP{o(c{u6d1*htoW#m%4zEBBoy4=T?MDbB^+u`j(hZ9_i%+6fRO`_v1oAhE<Cd)L5D
zsj0<j1SuO5;xq)Lkbj-tBW>zM=AWJ3yort9f+56=V&Y_AAq>w#>d<D(jXo-iYs@Ss
zds&%EB4gpLH=f~$SC$>rsy%$NTG`iLx%VhmnoXN&vA`|dQII*d%m$N=L!j)10OrKp
zQuoFNEndLzLBC8vc2vaj;6AA4#s#Kp<>_IXIUr^!Vr^&<i?*bx9V#{b%|QOO<mPyM
zXnaq}HA7|k+Nrvi3%WQ^&@)e_w2t7=ZVQ_~NKkHp5@bl1fR;#~xguVha!Q8%+f9*a
z8W3YMQ=9_wAip{|aZgv)`g5-V*MYX?#YW3giakY2H4#jC4-|pr5<)<e%<944c_*7+
zM7>pl=W0=t)z1?wG2RwTo^27lY@pa#KDJ|uU<>gu;<dg+i&iV$Lbh(Vz@PJ<>_|{X
z;*3QS`P9pyqvQ^(vE&W><Mdm?v6ZB^K`c5*LL3j|FdyUDN0>JNBwq;vIe6;!YNOp}
zqif)U5qU5iF=fRv-622pTNNS^sX%Bg_T%|=Vsu<0?vKIXI`N(8JSCA{7$<Ao?P=IT
zl7PM#OY|5$$Dxq)Cb{-%(vI_3pS|r|Y!FD(<hRG(L3xk32@=T0DTIe=H<n{MC2AF)
zvr~hGGsMS<J&?{k&tikCydFy%C|OT7#GQzR5qkJnW@YIMD|0iIz!%>5SSjo}>qSr$
zCpmm%2Xo`6L3>(UX-mXVsJ`pB-!5@Eas-3;I^{v5jWy4bNEB|J%@=~fynq?Iy|GQ|
zVel4`*jig#fTm5OJ$<_Y)<RY!+tU@AhJ1-Bb$5BBiw>9<1R;gJAS@>so%waIB{&ER
z<}U4^7~!oi{vLpjAO+L`$Q@li)kNOHLA<47GJhiS6nBOxhaN*`>CS2sX?-Nvyoru%
z;aV557mT-~Xi#AhpHPj77_BW1`v&KWb_{PQ4gq;4lEVWbsDYoxnpzy6McGSSCVKYz
zJYNkbRav-AD&1Oy^&JXb4lX4UEDe%&9uqFgBQwj6Pn9v3f#17{BW!2zY7*konEP#c
z6%S91Bi!kT;$hS>ao%wRt`+7g+S`L*X>XnHKX>zdEKBtZA4K0JofQ5wP9e+a;UKA`
zs|h!+xDhN0)Ixtdv>3R7tV!i|lO<w}V8`G>%g##eK<qK0)FOf-is@oKMOFm_C5F&e
zz&#6Ng5o9K6`rt$x3<23R+(%xI5opLEp~q%p=o>RvkR>a+ym<gZyAM9gpg;h)5@f(
ztrwq72ng5t<)M8$EyVS?BJCo}efIPGL?W*xcQ;`|h7lOf!UKKyF5A0%T{2an@x;Hx
zE}I}qG|4JUb~!Sf!#xpXZ~^HeKN%s|5-&mHSe^DTUMwf;@GZecW*S3xyXvG_NT0wb
z?e7GfFk~o3ROA8s7qdXrP$s(X^VSBPhpaA4-+uC+$O$f!ZBM=crKsN)puFYW;`F=P
z!_5s=>YD>0aN-c>MfcAU4SIkgJYV1W&3)Q-NdC)9wC4A>M2XmoS;`U!)@w(kU{5f|
zGWqalbAx~3APMssz1x3RN{SJ3mMO$4wE}_}Z%8RHXL8}c2n!z~*<_C-(j;tDCr+=<
zX3=yrz|;~Z?~WsE$#}FD5Bo3#Pm7&N^O@=2Sv?ecfqLVGxZ+bSI=vSnvVVs07vu0H
zLya7xcd|%;rkM#r6|8Ma9>Gen2E<i}f~!}X0bq|F3@U50i?B|-c5`F573?Esw<H5g
z7U0EjZ2)72t$5S*5uI$p68clCmkZJkmEg>i{iSabbJum*9}-tqqSU(T!@R{cQtG%x
z8ihDWT#1rG2M>#W5Ye?1FHM6qCzSRO26|u*N$dGOTZQOPJWL4za;fl@kLjNOMyEyZ
zsc!F$QAk`{CXL%~ur6{4678r}!(>IFuh=KhNUqM7MO0AE$R@HS6YAj>bIZ$*NHYUN
zSuc=`s*eIK`fG#_v4FASJ5UZ(!nNADHnlIgv=_L!AP!gy<N^rqi}x7VlCUHShh>w$
zTGMlCgeV=8V+<6R`~RTY;?I^+Z;8O210cd2x~C*ZqFVg&Trk&;4?gR+&^cO3Fd)jZ
z(}4&m<YwB6^<e1#>GSeBb6naCbr<(lMwDVuH%~f8Aa@#w7ZnAWUgOZBbk6!CA@q?=
zzlC-!lm+Za*W~j|mAP8hMaG15CV*9tQFjRV;9u-z4=5XxTN)ZQ2~sK|-+U}`^BvQk
z&LMiTYMUFfqB8H>jBoclU{C$dO>y_gClg;!d9VaBJx2bHng5U9$e6A&rlUz2*D<^?
z3r+ySr9wLol(8+d_p+dXbXI1+`#GXd?!hU3v~`E^!$qQ6sYSz{i66-#jf@7QO=OSE
zmj7AL+aDzSfHL8Km%A)|s)<u9uWAWC+Fni~48pujwwXhPIg(3|ijr=0+QZCI_nNFO
zEwT_*9I&ew$kylmVGPUt;m*f9(V`d(;c?FI%;~vc%|ZnT7!#pU2H9Txs%Sw^K~Je$
z?mq-V>glg_&}Xb6)`ythfTzM2ItnQZ5mz%f*ZCSE_vGLPZiHJ85Wb-n5)HU$D`|$#
zmZpPBlUkCH0-zAZ(n8jR1<M5hhrwb$*g!lsND!e%M0ER;6WJ1(+Ng!xJXyX)^-iBS
zFSnS_!k}GJkbc5u-I@#Yt+f;oaLFUT+M!~1f##@^w&sH2%^_iwRGl&iVxF-U8eH6J
zxW|a+bM5@55kMJY^OfJ=uHf0dB=}9;7)RPy4)ZfsWf?1jXZ=v{OGHwP)b2WSWHKN?
zWye;t!3K7jr*d;}LxLZ%G$<*iEBoK6Bw!_^aQ*UYiwF7Yu3&LGT@plPh}6IwObK}$
z0>iPQWH_k!A`tZL?PatfYv4cl@jKokP(_#bWv{ql&xeb95SB_hoYyT0naS^EeDN+j
zsvcWy4nq?&udelp4K|5%2g&Uwl5p()#~wX0&#Tqd`L+3Z4#47vwxp~}h)grlCeHHb
zI9<+$0xrv|tbs*=1x)7%IbvBw|8xIq_9bMytSoVx6$stOrVih;1zx}4uM>#)dwa8O
zW`#7veWV@DuCQHZv}1qB=hJC!gDv#k&%cGlKG}77ezh~-@4qJ1lj7RZpBsogG@_;e
zpok&xxNgU6S5_8?fLB|KUfuwPL{4dN>v#S(0n`qG@DajbV&P*e-(8h2CG^(#rh`1C
zIU@Ta{4!+$9Efczk}{mDtZMlV$6#}dP<4mbq9Xb>8#xq{QCNPh|JrLyLn5*zlsCag
zBEe#y#N~T2F^twshio6^#zWxHky09b{64GR%o|Ok(QGywGpAeHFlJ5HG)BknP25Z8
zMzJU7n|qsK{`|duH^?W6l;MQ2S$`o-?WB8$F?(-ow3(Q0zMfC&HNYs`*#eUv%_k8o
zaN$JV@q_#lJza?JG~#eBHG*jSH@<8{MmF$q^SIf>)_=k~mQYhM>g3W!G@3UWD9h+r
z%MYB^Tx>MRH=iHNMd_7R;oh-P-wel`oMB(_P2(cLvg<W{E7L9m5}8>&UuRUq2)em0
z!a{%P>o32(5$2#%=6Jl-${WW6$PSZLNKKX&7B97odhU3>X<SSpZpJdsG!Hd>OnrSU
z7YFs$rP&4)hi|X@wr^kZ4dYC*>5t|kOiq~VGU+s~=OZK1trq4|=OLx;=c2n#zYTJX
zGt4(M5kI`u@v$+;xX^+rP?J6U(PX)KEZ?Aq2L3IC6`V*Qt&{MAdDIc9+l@m6kF_<f
zwG1PQVtN0rcXO{}*hbQTp=IU6Tq9%@J`|pEEe~y6YZ_rQpTJwXW(XOEXV6j4$4hyk
zGm>`%l`xnFe3Qrf{*Kj%q9hq@%|+b3i!U2fV)Dzm**)LWI)1MC{v`V1ziFLrbuT3s
zYRL?Vr_+KH^o&TC&jkmYGaqTT?rk1>@1@Nb<~A?1el(h$JbuZEx`lisn=@<}YfE;W
z@WR2dx#ZX9(qy5QcGF8~ot}hAqHb8OIRTcJ&LtO`G)cPYW;)t(@}K*%95MWV=du0w
zPX48iSOvHti*WmKd(CdY{?Gnh%+H#7X8G@+OEZO>aepU>>}vRQTK0d*zvJ;nSh&}3
z9KXXpZZD+;1pLB7NwQ={Gh@lk`0(_?54I{!?OywfpKZMwHJ#+qvGm5+wPdF8N&EV%
z$NZ}Qi=|Q_Rc2z?zY#rd>-6zcXW}G^>ZxZf+Lwk)&-qK%A>WC{^YyuS)Zg&+HQ(_s
zoLfk=lWexymVYdNp&S3ClWR2m8E9*0qfz$sLSqoWKPLUTo*GY_6Ro`1G}6!O{OD}1
zJN91I<k-2EUpwDy<qmny`1)8k%C+p|1GdxrV!<;T7n-RzGU`XF+HyLzWWRqgy^u4y
zGx^Z7j0OJ_sc~oyv5l7UOIA6rp)lz-^9Xq>e7dDi=?l01?IQ^15;OC=s^FVmlN)kI
z`7?1bKHL7jyz@%;#@GdO=DIg}$!UZ)F-fr*TI|x!wrYc9*=_k_a}EFg;aKG64+ZBR
zihcjWskm5mY^;)2pB>BVa0HWvco~a!Y7YZ2*Zr-?KI8;`a2lmcLcL&Bo$%fkaL+YA
zeDn2xZP?RsWICkGD3ulN%gHHnq{B95`Px@dU|q5dmpido+%qDKO#d1ofc8~rc?eL;
zHRI7uhl`z}wSZ<gA>ZTdEA3#?U28hp&={b`=)Ldd1FTEXa8dJ_#jgc#{`2UX=GHET
zTgXq6kgEuexMtPulZi&EWQ9tJd`iJlDCOSPk2b9PV(tyCP4~L*j9bU~9wXl~lxvn$
z6j+WM1zNT{!o$^zzWo73nZ2o#(6VQ_yc?TE9e8mhDp|x12L3Glf4sXV?5Yu?x)jiL
zc-`i9k&0WYh{Mnj=WsfR8!ZblW~mbioHDIU{`0jq#`H`Y+1jj_)0P*SZo@Yf7>DON
zT3Kfl2aBew9^0XQxa?o6YQB#Er7>TLs$+C+_|2xf>>V0Al*Em1IPa*HG*^*U-PG5|
zs<v_b)rQ^}^P7D8yTid#?(f8%p7@@myr(@qc~h(9Pmagtm1B*Kn#OcrU=6SNrL(HJ
z^mHryte099^}~c3&P)^+($ow+bvEiczSX*{)J8hEU>V<U-B{9Aq7OPtR?Tyo?ZO=L
z0=d=WcFs9-|3$CmmvcI4&c-i2Z}J7CxuQ)LF=983N;JYwPHDs=9LG2thsMTZYjRm1
z(r1+88BQr;?bvZ@am1m1$tf<>K3OviWgz>hga0rh$2jB|Nd&)&xhFhh)bFcnzJ>~<
z&b;P?L6S2*5M1-bW%}Do(}rT#$SC^_JBiIEdOh2>%Q#D;=8SsW*)~N|oNGxO8OL&1
ziu~iW?#96>4?l1%E$S_==hby7#;ryANNp5O+r}Y~BAwWsiixkZa2z*+uw=?Wq1p3X
z3s3RI?_vNa72gDH2%~8z{1+{xcroCe7zSLlujvoOeb+pdCd#8qAwGmYvC8&w6Za!^
z$FP1*g^Vw5iC=a-f7*>KV3!RK(J*?Rq3dJbtv~)8AMP0Di<+mR*d~36a}1YlW16uY
z9YMZtOzNlkz7)Rh)8uolNBu&cNQQRkLLu))`e|*9#!+;q;V&ZiZiag`5#|x2iE?7S
z^@CsC>!wfR4txbO6*RkQgmFW&%4^<7;{_S=MEIau+{Bqu9o<h{zeXH!5&M%KN|!H0
zu?j4=qVo6nXMNV!r51{*(}P58+7wt$X14v|84-mL=I|k<ja^eXC0@0s>g?w+(^1mI
zYyPC=Gmx*B%+S6w=`lRkRfnb<H{f7+iE}EfKR2JHV+Qbvpzs-z;V2*f=332BFV^;(
z=kIe(G}&+)mT%PIpUi|AGgGd0t;yILw_MY;fl%4*HeFu$b=`@0G6Jd0^l9IYMlG&Y
z1VL)#amco?;`9X0AvacLxf}JI)<!eDb>a6}BIYK`j#ZG)d0~hNA%B(ear}r4>tVQd
z-aYKVj!0Q&bmU><9pH?pJEdBAH*e_J{isja#RT)Q%OwThYJ}E!(#T0aJRbc191_O^
z?xIdS<X!+WBwXdeGz(TeZAkcqXuImex|N4<7}-A79bqyqtYBV@n&&;H{iL3kb4giD
zXUwX2gdQ?>LHPFf{h4bCzr|BPQr3Sqid?{q7#pS;jLfayphq5Q`1aHbm*a5JLRM{b
zb2>j2O*djJC*YRPMbdnRzmno|g=>BM-@Wq?ES3&sDu<-25N27p6*<%DyJ*g+wWAbf
zbVwg^qRCjBY^Yd~F2>QmJOMq8%GRjXrh+-uGEpZo;atGE$e1k4XpWQ@E%58P=2QRZ
zT^aKX@wsp%t6mdHps8&sXb6?*5szZzphvr=tZvxwk&4KeRQZK96*Jq^Fn-orhTaSL
zgnmTXn~r;!E16r}BZl36^I@ZO7MjlBWW6(rzBClE8%7LO>ME@x^?6%Q>kWNIW0-A)
z2k6^LIX|r$eKmg7zkYPd?CMYG@%W}TA5*x|XnZazKALu-h4^q<`QqZ^YW0${ddc^n
zw1-PweYUiCO0T`BOQ)%jjjpHZQs4i%eso_Nn|6Z1pINbIt%j@6!5LlkSP0$F`t`NF
z%dfyDrrOX-H{!F(_8i<{1{H_6)X1uqEzi{(EcbY<p0jVUKHUxHntctQwDe1UWG$Tn
zDSR<*kfI(YZvGd(>38R%#pt?DmwwK_&{zF+y|O&njsZ=h$)C_KSJWjv`BH3=f^S}m
zZF?zFjhaKvCFoHUeZs3m;HShCdNi@${M}o<$YawE=|C<VyN(dDPEzGp!EE0C0Tii9
zfHK{;$DNd4c|I!06DPgut42&*>V%y*3V*o!L>fExg`r<L8}0n=(YApHE`BtQulg&|
z1kddlU^K2(qcH2nmM<E~esB~!|8ITn%V8s5(Iz)on6Udt3U}-ADA>^ceml6>DVl!q
zNOEnUo$#vPFC=V3Pw30qndlczsB))Jzp492#&vG;p_Ji{eBj+H_XNWuPdJ_~Ubj8{
zg#Sd*JNl@9$?=LWrZ1_v%6p?*>Ee^|iD6K=T77?@(?9v7bAB^<W%A@2Up}^fdE#Ga
zhFKh{<f+swzS`ZVZWdP5uk9_qs?Ii>lY>IDoSVtd-q~zk@q^~xdhYvwvh_~x6V@xZ
zIsmdp^u01&^iXSk)O7oY9fQ1|Xb1YV=hf<gRS)Fd6T=B;-*0>V(LdqKa_&6(D%?Aj
zJ{1+N>RY~l{`+<D!_L?IR=@D2;n)0O>3qJjc7**O^1NG@iW66Lf8X?JJ*A(Df5}-%
zbp%LW>YhwFK>BMx*rf8O*$f*^(b=YF5kdvI%B>%t3C)USdnHIcdb!|XJMQN8KG0e;
zZ~s&*$EaJSIIt#_rIfSH2XA1dD=!VrDSdP%;26$VRl(NLNxkhjqgVB#e#^dUNBwm2
zv$mO*px$v7hik>l1vLe=;TxBV2jVGhKWRhsqmGjw1%Plaj39jHPdAHEVa!`8G#W)S
zv>FYg(a@t{Ah*8yF<0d)mWR`sxN5H)@su(S;61{AfvrG(@JN`ANo}dg6+LQOCo($2
z_)#Z6r9rJ!sb45I2r*CU6De%22vhS@h5Bb>=!_??R-uzx`og$lTgmyny?^=Bi&NSV
z&Q=rmCTjsl?>n7_5nQ#4g|WmGDydYl$8w`%13mhOV}nON_XBr0o}ysJH&m}MYR9HO
zC8yIvG>or=FhRY5KMN|f)YK884D$+xmN!S?W4FLiPdKCff^$)*FXBzE*e|6zb*#tI
z{^U!kN}21G{+;7_^@{(pcKW5CJ;j<A&Bc6@rmu9rm-V(;Z{|zIwb9^<>d4`GdNfyu
zi8uRuSRcN!%C)>67a4UVll>ROvLJqkwmrSyRz1zfb<6O2N1UY6hu88e?CZx?nA5Z=
z3oVV*(Ua+uaqOHJ4)u9|xajOJ_R?((%C@t3x34NFFibX(#U7DY(fqZ&l~Ut*&#LEy
zu6oXB8v06epdb8Y)AJA}i(e=P3_s#cz_}?sY4yklp;a_UxM$hM(IC)qz_hDJM<#6R
zie8o*^Hl;Qv9e*a%+>uimZRXPNrV70C#tr4T9;M|={=Q8)u*Df>EfCyp44jeGz;vU
z|JQ5qkyiSAE6tz(I*8qu(o-<<M0$UMB$hq1aldE6#D|(j<Nkp@(QMBD<Zr%fpoH;|
zTxr;SU2L4H`t_@t71L!_6wb~L#g``rQtMY5r$FkMR@d@WF*2t*M@QIVDtQMMdMN#b
z<qXIaUR9>5%$(9r{n5C4xiI~*)>oaU)2WstO<q}fF&Jw5DKyR3$%J*D?`pb5XrdpB
z>nn$i`#pWK`D5pN$kW%bjHjAS<NjI1@*!4Ueb;!N^zD$=-W5BZ37)fcBfe^v%*j=S
z+qy<+J$E6R$&<%qY^&8yRKv!Gu07!-Q$ewNlBpbcGBhVDR<fe}6FO|P$$rKrF&kG1
zr=zJ>4GX_^n4X9i>khjOrmnd|G-1rI{~_UN<DQ^wHD>fm#u!o&eWU5uy@B`ClkWm1
zlt9I<N0wn+42US~S>6IClUiylK|LC&YwKcwP*>E8tyJqm9#12_14C+`(6x){-8J7%
z@9`}=o!rB_<gfWkREyEo(<A~s&-=z$&BphblL^|$tO+jadDp7H@sl4t)A;u@@9_>g
zk2QYmd*9=gKkEGMea|;=Ysm-w=No6cPn`d_zdAnt^69Ui*YjtiPk;Fb4lw?wXZZ8#
z^{+q4rIlA3+24cCQ;k1g;EnRvo#cbH|6C_u_<`x2PNx5=PQL#CUnfDkZ|_fD_XjZK
zsm9kAg7&S)FB4Y3^+3zT-b!@#Ee{aT1fY=M?KWI!)SZ02MkD#lf5A$>^)dF92dv$Q
z_^r3Iz<KxOw?2QX#qKj1==MVbXu^8?{@5?1-9pRGQ%_AWdp0UsVFV;YMC`^Z%9-ga
z$7vGnc6tAB%{HQIez97uMp39Y9KE!GUb*_P)>Gt)zc^N%?!LHiS?L3Iv1Q$@BE8T`
z&GF9UM-OtMMFP1}=@Yi!v&+E4dL;&Va|?6t5A_l6xIIwEt(jOyGf5|?HXE~X;5EnI
zSbUK5)jB|m@A>d))E^-~##FemvYPy@`|OdHUXAc+ei#2s<i2DcB4rIr%F@P%g8XAa
za(CcV)ns1TcgM8^=y`gmJmXMxI?#<ygw4h9lF!<a<dEe=Ggr9<rZLJH*2MbCf6S|k
zeA$~@h{1S9fL&oTOp*}ay-rpm4AP|$(MgBowOG|fP8fxx0!tRD^k`pAMk9uD&qm}F
zCTKyL5UtzC`l>?i11eS{Wx({?i*Pi|9X}6*V>Q6FJ=dJIX7x;N)+*<k+iRZ+Em!Tk
zWRL2n?a@2cA)@9UMdz7Vk!+cVnDt2A(jFOK;&e^r)pf&C<(6*TDR~LG&p5XQlR9;y
zYPd>8eMQo0dmaub(iSe%Z;S#ok^s{wP_<!{s3WjG_;YW=xY%c+MC+R4Ty*?$8ka2Y
zQLLF6-yg6tPJ)5_WMUPnh|AreVhVF=p&pSeyed!wopRd(T3X;cWXi5pC+LQ4AUdRn
z++7?Srd&2sg2?POTCYFzE@<(`osNpi`iE8IsPRi2K`L4l+4F^xkk3iFF;ZT}B5{+1
zCw$s*5+}4f8Y8Qy;$DhR#$JuPV8encSsH0_WN`$Hw2wrXGQ0>|Uy4E4Tvm8_%wzRU
zY<PyP1LKWW6;ieBKjVQbLABdg(}jFDij-D|(G>fl%|e1<RHxK<pLoXZ+n{yij<0HS
zJm}j5i~G#+IO6VkFOm(Bk%jSBIU=A*7oj{{v8(nJeLzVJQ?1Z!`8Xh7k+d_i^C2f!
zox3t->Ek9T4>ullJG$ER-Td)|TaTO#O*%$0bhM%(o8$<aZ68EwYH)ozGDo#6OV|(!
ziJ=U)N*g+6Q9|4kw^|TeKsLpq3y{K9#A9Sztd8M6-RwaEcn)Miuh9$i_FaDgPJuPC
zJ)D9u4!t0&z)XVQxQfBZh3eLXWmLn0Wt@pw&&R-}Y{|p@uxq*ttX7CPhEZY~frqWh
z?3(?hmZ^QeVT|V-sEX*^%|9@vk68$T;q5fyO~{N*Jt^p)LB47!(MaS^jY&HI3PFw8
zTSBFLbP`QOyEE(S#@b|Z#>E}W8WOkh4R_&LF?95?{i}aVj4^(W7z|{NR-snfG$t*j
zOBT(UbZBa(6*jD@Fz%wCxR&xx=ns)z@lO$MauITU3IN-gj_i2D){_7cpitH!n@k$%
z!`h;6#UMT#7)E^zDC&J{BOWj^I48=0uGKBh0?NePg0?^<`N?R8?};<ct!KJtBZU1B
z!iQ41)`cTJfRL96{{c!}A(lA{BS;$+x<=nkgA9w*R{6$zt#353MJ8qgKJ&i{n*=U%
zkue}A#D{4>wAS$Kq83x~SzAm9SAY-O;{-*fq!O4Ts}2fp`qP1><?kUDhE;HwkixK$
zN7$nfV2m!K<F7yU4(N&^=wZ}d7ztreBAbF~g(}8!IRK7erc9uq&7_94!oWkm8!@k1
zPtg;GLcyDZbgn>ZJei?Eq#CQwW9UTweB;68z08r3z}B*zHNoA5zuNGwX*Y_a23<^=
zut|ghb7ItW;N&MQ4_xpXG_s&*g(?XEuiXs*%xNGQo-+i3#+Pk8Hx_qb3wHFPSL_7T
z1^Tc29{2pT{3{MOmcL+KKtr%2P+zy${vg_7#cV5FhT%YDv|)q`Cal5~xaO4jUbAbt
zCN@Od*dM56fxIxtkTInv_>6aCaiNkwt>$M|-pRtqo3Mgkin*|stPWWfYsy=RJ(@?L
zB#7gsLo*$PY&O|*x(Wrc>6Tb%kpMRq-QDR;go}$wFez+20=edrIEN5yG7~T%!c~e*
z6;_6R;hC#q>x@EaT=WEB3kV-|L>83qF(0_#0B1uktnljb$Tf{5^Vbh&nwG8nX$!e#
zvFp!0wFegYk!-|*<<m<>l{{lq#?p0EN}g&hOV4JIIX#knB${L5QxHR8z6x1q1jX<!
zYPf-lWvzrob(p#Ro<Hc>PW6gkxa6OS*`dGgW2OY>iA*pvjXgc1wLfLoCWCmShRwW2
z{dQ!&f;TN&wW_^eS1+LG*T}&1^x1e)FKewY>dC4uJzcpwn%rl<qzf<OWL4DYtGl(0
z!Jks4BUQV!kMDE3YFDdwV{^k;kJNP`-VlJXuQZPC_$eCST`E7MVT-z`{cGxf_^C4`
zHuVnsuV4lb)e_LK&?FzlG1}wAG1F#6-Nc)$DDjdbzWaF!g_(3QZd69bhxSuScSoME
z_0q_=RkkL7xI3Y*>ciCuOqO$Zzx!d^dQ5e%SCYwU6<|#rsZRcq{ixQDRxQsava_bt
z0lTcb`#SoJs@<)L_QL1vz9Mxzaxb=yK(C5H)YC6{*bAygwqJMvNgyC$pC&v@==f>`
zXLtWYvt%ZueUfH4A%T>9G4n3g1$=fo-37<8?8TnwYfTDsUw$H{s{?ume<RJSsPFtG
zEvqNMbHAi_dj#vx`Z>V`ru1cBR3G;(C(%cNYTT0LcH*D$gO$T>ReOP+nyFW{o@w0-
z{2;I{+*FN9U)8Tx`^f9ck?-#4v0@-N+WCri)&4&mCkm^{`L6|Qf(kuOI{jI#gWzh_
zawe>@qfXgR)COP>89p~IXvEQ9`s7J{Pq4PHuCLZ+PQ?l+%j8SW8(j0<Reet(vOXB}
z3*P&i_dj2KtnsJX`%q%P6fDks-#PWT@+Q{F^xtSUAN_BOhTGrwRAlOM-qk_=ier`u
z=*UcL1=>0xWW*ZsQ9Vwz@J6>0SanD*oQJ_gOfLIMg8dkemprm{P0~-g9@xuh;)!&W
zhQRNDE=P(D-9Ic%Dl<0FL9t+I$>mAfS;hAUbaB7eFWL7mmn$F-y(0~po@o9^Rd0`t
z^}L7w7tC^TUtRzu|EY)*iMA)$l<$w*aokaAl93e932Req*j60^oKf7TngV3#?JG9&
zz;8(fqcb9)LL<1UEsw@WM+~sbE7i-OG^LZeB!q&F6qu@D3D(iG3Y-Mkq$KBiuVD3i
zrP1fTK08~!f4?;upK9LU*C+1p1@8;q<);0^&<9ydU~P`az9SSC8_Q7oO#-vdZObT)
zj4s<oiD#8lY1BJ%KCe;a84Ezna|3vE#BiR906wV3CP0})7$8|ud5<;&fa&^jwSG#M
zOs{g)Hn%<RsBYZwDi$9+bgW{X=qTgChmt=%ewqW^-<yi<wew-a#x3^_V+q;F8nue1
zf?FUehj8Hv@aJl^3$PLuY9M&$KdbxNnCw?sI-(RCeqjjJ`Bq=!ru__0`l=Fc9f3lp
z*szXXC;sDoCFtOG**j{UXcoKXK~Dri*H4{O^-~?+xPQ?3u|KclqlkfwYCZoUr^WeY
zQx;BUsOy%oA8wyj6qW^czglOxL2>{uhuWEL<m;!X8b0C~ToA_yXpF#wIJ9jIDBL5U
zR{(t{k;M`+XWM{%8CY2Y3-avxEjVQ{@IMfFwkiT}ohX+$Yqk9k-woDzBnp|e|9A=K
zb+tOe3vXf>i9V$#`-e{ulQ;w^bzw%;c6bd$It8K#R{T<Wa!u*Sq6tI`(feU_ULaCc
zx2w8hjRJiFWKpdRjK-XRM@#y;eMlx`+0&vm$OtZp6+F?re^9Fb-Z6$Y>fhJI{rw1E
zFZ*C~aO|1S<pzB1C+L0OX2hE@$d7T5?*Rqv(qM=>c&RglE%2j3vctXuGLDphn?0(n
z$D;F>0%o!ncGQ6d7z(eQ(K`*#XCgkJUl-()_|lvT4CTfz26^`+@rq+1W<9$O1m{ge
zfNxd%MDxd*73=;}{5p_;*zGxS<44A=2OB4w?dAWup4YX<3+}Qnca=`YiUd7V`<#m%
zBu4vR>ae!~0H$Z0sz$jaIw?iwM8Wc=8F|vv$U*ly=R6A}3Zo)gL=@d1h?I%aU(tI=
zLIhPZ5+ycS$0m*Hmtk{aHUB}`I@fToFNB4MIz4rNJLexi+pN49z2{7X%MJ^`CS!g=
z05X}dkp_B|1vbPV>@fmd5m*W`Ca@Kb#@B4dFocE0k4xr6cgA@cc`_ykZ00bD0}H#(
z<80*h2$=f(&@9sCG@sIuO+Zg0VvIyWukC;Kz_%b^f?j<G0`@cCj)47@;1%Fmh8eB?
zWdv-n3#0wa$0z^U+^f+o|NO(lt8*Y|UwC-ws-Gcg0)qYdw<Bp^|F(Yq8aVF%10?O)
zT@Vas|4k6==i999Hy^CMJcup{hOuD;<V#gQiTFopVTiu)N!H}A{RR6;(Z)92{98@j
zoo;vE2;TbOo6o+b1?K46AKUX^=tZ@N;Bkp??!t#{UC>b!DHW*^q`9K3Dm8Y>>Zyvk
zGOFY2#K+UQn$qJwj`6-Y!f_DfMh#|#VZI!U#)rw~sXJESKnAx(j)5Am1rZ1V(1GeS
zTy>al;8qj?3VuQP0nud7R-PT+d+yzT`X3*a#ItB`3ZyYfg_@)vrL!`3z$3b<R!rE%
zKb5Q~(M``aiHb+H$xMkLOI}2%R|i%hMd1!oSXaZ-E-(&R=Byb$eQ!9@beAb?XoR+|
za@bduEW4+UdAI)Ed{5Pkh=7{B$D_v@DZNWT*;CpbVdfaMGdheLu_=j+UHPP4+#qi(
zjZo3zj!ed6Eo2V97Zw19tRCe{p#>;I9!JFO!XSdRLt~0mK%WTU4jqy&_+b*i+5Y<m
zN7^_IOvd0V#UiXgonJ$J1?$rhD?%1iHT*M5>IxKrIiwj1NjifYos=fBVQ(C;sSS!^
zB}opO%w$*{8HjA$u2Ev50P-tlmAu0|q3h|R7=lpiuD9^!k3El?(-LbN!Y-*7W5pmy
z$=i}ia4DUe5CGQIh}8-qHDv0^Ze((e4q0-%O-z_idPj(YvB>5P8p8*qLC$!D3#QeV
zuy=;q{^th>b#>M4TJ90jnyy*nD-xCT%8CJyWWs1N2g|8WGB^nd|CCvY&f>rrHyZJ(
zz7S=zzGt*i7c|X{HiQr+?{Xn>;U7eZgV<CQp^WG{SdfK?>(a9A8I|in(E7%g&6=}R
z@MkEeQ6VzCME|Y=Uvx+y72wr%BJ#s_U6(fWHGM_Ds;p~vl}t~lRi>++wx?GVC|a%N
znje*Vj@qeEttfWY*@q7;w|^Em21gKBew9U|Vx(%H3G9m=Gi7b6^?)RV2p)!O{qXaA
z$0h<tAZ3QaT9*XU<SHrCGZDcE@kZKvie*A56$N`Vq6KI~j7wk@N=TxCX2B9+hJYD_
z{IeF%tNhTv@ytKTp|piOsl20Ybw-g#RYQVgN^YJ85d#ki(4vw>yc8bRE>KWWpju=>
zJ04G@$}iIkSs0UPF(iqs(8)LiSJ^n)z$+hQPu-0z_txY8!Hu4F#PK0ixG<;=5e1+#
zQ&Mu?94E~;z3g*3p);f9!2rQ=up-*RditkH_YALw5=r3cnkRyKjxH>pjcK&txQX!n
z_RsC%T6zQkU@fsp$OtwG;s9lJB{H>Z)ku_ac$TY`Mrc<Me$WkI+p8J}$gtVfkriU+
zFy9r^BS~ZJF<cJ%LeHkshN>ghHDT!w-Qf;}5v-15fVDyaU1abFZ}Dmr!+=<2>k0Zw
zQH20@p)OgD@E_dM2sa2n4-o&MF@#be@tXY69bwI;KocZe(39-4k0|%tn7-$Ido&*3
z<^GmHypgOnG6*Xemt{~&p}Fvp=b=fBAA?z;RSvMsgb5m^(~&gcrXMhmn8LK(n}`dW
zX(qV`;UPB#fg(CYjyPTP%&$_x>Y7L=76>aL2E%cvdBrTm2q+XXP5Q!QGpe*fOs|PN
z>Coggi^KJ#zOqq4?I(i)nZ{hso3dhF9l}Mju56AlFr8!;C{*~G2-`~bBONiI4Cd6a
zS28=wR7F*6lpMLbTUS-x0&IXU29dMjm(T&gzXKYcasl89&H;$Vlc<}Q!H3>MJv@^%
zWp45e84uy88zU6c*g+_y1V%n`p&57JT4#uESz7!RZ#nFZp462B&c-++b&AFWUDIIF
z5*Yygf)1|VF8>>`2O1{He8uHRhdeWd&l)C;B4EJb!W*J6$Pi`V0kJO9An&7^5FojV
zTqqrtt+EAB!m8@gWemk0{h7hrch&)Ric_UM(|64()`JTS6iM^s49s9$B*d^)nKpG<
zKs488<3})9>I@XuE3prNXL>Y_F}@^zDps-30<R$O%-HL%zYA_)Vp$k@Q|g{Y+~o(t
z*)S77CC@d3$~Bn@q$J7(r!o~5(12HU=8M=;2*y$XT7zrCI)Y~AYDm_~p2QCxbtBzn
z7fI`C4cU*>Wm^i1yB2N*A>bS$(X3x8EpwU=^Idg3xAav&E0iC<!!i|O^;H#9u*J^8
z^jTGT+MYy@4%oV+4-?(Thlw{3Y^6S7->nYHbt66=b^^Ca?BF@~sMwCrDrZWSwaxvj
zXf-{8dcs13dX@r>TI~(>m6!LfiM!O7mB!pqag1`i?0`ivJ4|3{Bg9NTH<7NfAM+D*
z4jvS}s`_Atj>G05$_f-EP&5HPalyDXeci6!gP+wS2W^b&bX3^Tm9r&!?tx98Elpq7
zUU@@qr1yEd>N)qZNeL!(MolYK*r@9J=xjyZ*H;rAfW1kQF8^*leN&&+XhG%8>5udx
zSSW#iSVEbwN;^Q)TLoV`uTRPb5?&kok+qj=@Q0|jyp;WRe&MXX1BTj#s|q_UcAHJa
zrI86P{}xyas{QOI>!<Y|@4;v9sQdj=(X3JkuM6gT2~*>alA^2u-^{B&@a|WF#Stn^
z8@>g`REnvK8KE?6tO#HNYm(&vY{&S(yVZdNkYP$cUT`KTbERxTfGQ8<<hvi$x9ma@
zsDOU;)JezfA9=q&u`xJm^)$KVpw!>zxtFOW1H1fQRid%)m9AF5sub{6KuQccR81ys
z28(2wQhg@1VcH$M|KVlIs(J-sYlP195G`tKC`pl`m7^x{4pnQ{?TKZUVQL?>3W9!9
zz)ek(GL(`jfcTvxh1W%7%P@}41k1K_hO8U&EoCBynOyJ4xK+`w(hh`;aL=kQlWPOO
z)Nip<U8P6{3~7QI7@0n$Hx{Y<RU8<HXg~hzdySsJARtWKr^Iv-Ijpy)4u#Qr1=kWj
z={Pv0kCJx-NqA*hjEcTVsRSQ-VL*l0h$>m2Er3jiaRl{c;%KUDU?Wf&*>?s;uup7y
zlOPO|zk~iv>8TRv+)Y(j);`un;2{QEhLqm1kN=-{xG5GK-N&Xt4aF>wNKQ(r4|GXY
z&nfQY(6AIWa)hw2V5aJU1&X69BZ{&hVk^Vz?ZbKq_yw=%r2rHlbyoX|1?Va<nr+ps
zqa^6YH2$AY0Cg$2f;W^25y@M1^QoVDC+{hk2>0O-h8NQd6`)bLY+)D?R<U6fp#Y}}
z5wD;SCC}hJ1@;NgH5{QL3ApPT;fN09S}E*;H(*Eo5?rz{`o<JxXpa&X0zO*Cl&-T%
zaUd{EU>R=i$Imi4vo|0`{7)!L1|5_P3WE%;QR1uEYe0^8Q7M^}JRuAMnP|8MFH5p1
z1ux^9kV`FPMR$~lMhQF&Y^{%*fVp&bnfoZ55OiBOL2o_%#Gm2A3G!}>ibZ$gn=+VB
zGt&%e)1?4E*LaDY_X4XzEma*91_Z`BI%BCbirBJOI6A@x*0gwJOn(MWf&wXuF|eWn
zt(IghV6H%!NC!LicmyA`iSVfX<`4aJJ<rfYEEX^lk}<i5r<50=Y5l?y!pyv4x}nF3
zPiW&FSc<gfkO^gfspGJ^!qa?D*X_8}pu+85y5A`-DqaVlu@yMg_-QQ~lVMC1ix$j#
za!|Fsp8itcz#BK9>X7?#ZtfY+_Ymb89=6Vj7Z@^GW_3V&aKTIPY}_hY6m){eJZG0o
zMV>q90Uue?&v;;+i6)3kmCGrDdPL+oaxtJ|`&uG_Qo`o59gnz{2O@>=QJ+L)DkV_Y
ziY$wM=0_=!;?md*l?4<Onim72Btri@f9jNNN$6}y$5csm@XG3X!aLNR<*CPtsY7)~
zCb|GX7-FiUWXAyThdfAXd2gF*HWjM%t`<veUhJ?Nu!9hZv4%>k{@i=sw%>cb`h4SN
z{Nb!TsuMrf_#m&py-aGq|HS!+{r>oV|I<6b%x9{<{I9_6*I%zae=@5qqAcoW{Kigw
zR40}aqnY>Id*90~N{!w#b{|z%k9DZB+UaHd<&XX9uR-U_N1x}<{v|qT{LMO<>{Ge*
zv0wSG>xB7yM<*0WWo2JMo7tQOn;LizzL<-Vcu`aySxA~iQSxf{fl&YD$9KH(*2h8p
zja$EBhz|Yr4<zJU9y<ePZ)9}*<-sE3!Jpn+$@^h6VpMwyp`kjwL<r;fq_u~s{sp<j
z0FV<J6S|5Dks!w}>Jg_$D9oMU;<F`>@(6ua-?yQWU1Bi2p7J;j*Tq&T5-c*I3C-51
zdzPIjtxJR@*i?sz2nf;%*}Su3n{9Qnj#l9_&%Hy-wt3iBu0-33TVgr{nIuZ_2rvuB
z25eCC&@AoK+_V$DuoXU(U4M2)#Wo|-grJ`7NgnG)%5u>G%>sB*{(hBB1wu?gRY-@p
z&b1<b>+Q31h6@xiVj$ZnGC?3UI65NmeVSe^%&$vj6EQw{KRE_k$;mVVQ4X<b=M@@`
zz+-}aj~;!49VIfVqNE)hn6p?Chz>38=4q2q!#NTjIS)aq(hB@%TJM7QMbw$OVymN2
zDGMcLH54-@S4`z?`rLUhg2iMZbV5~5Ut)M_D@_Fu1e_NEk4T)&<Yae&P_!-p4|ZgP
zjb|i~WQ-J5f8;;B0~`*Hc4N~?{BaIWXX$`_AH8!PNCd^jhLXc%$(e`%PJ*#QOOjEZ
zxR$%3m@m93MUoE51@HrM<Z}uKcr#Rb&-TCl$A)tz4k?`Q?XWOZ7jUN}ir6|(Gx9CM
z?~aOjk98NgfDx&}lFyXBZ2NxI)dbPZMYB!d#-LB}hz;$+Yf^{MCQVmCtQ1n`n$^0j
z7j-`sv&PKBH}`+VwZ?r#T|I1Mvq4fz7Ep%(Ze%8MD6kB+#R5Q(un(*wiea)G1UsbV
z=nnl5!LXyk1d!kuu~dk;W;6s0N6;A6BOG!)BoIgyY37Kd;5?!Ax#ul$Tyz0r4T=AR
zIp2I_DK+bkykuvcVxB`IpizTa@DF{!<s!$t<fNc=2&Ygx6BuQWrjq`Q@VPO4CsiL}
z_3aCh0$o8lOd(o2c1L8bv`|45&$}zikc82wvq^>|W0COwSyc>KEGh+G=~7DlB}9=_
z(sLV{X@=I5pQ60tq6i~%fm_m%Vl0Mc!3e#0XXjTaBLeZULU0oNmd+T3xiG*qDFy0{
zrbu%cNTv!k5W0O~iZmK;C&wER2^j_Im>((v!lMxz1T4E!iXWIHssZkapkE^z0v&`{
zZ7OHds?{wuEs>H&-G$Z|kO)th9l69Z$%1H=yX*9Kar&1Dw^D1VkPl;Mm#H&LY0mdS
zLo{`3xKIQg#dC3tA+>gtNe2iD#EhQOfSbBDuF2%kO+p<y$J)p-E5=65c!M9b->FBp
z{@{;g%8^lx<Z9$v{)nVOs;0FBIUzniM!-y-V$}pbQ#MtRuu_S(N!b>+q7wT8<5+L4
zBc>y&0Rw20mHjx|zyCUCL+QstgMh3P!TU9mFO;($=o`Z_JkJcnB?Ij#dWEq-Q5@8Q
zJjD>B)&w#@wi=rHKDi3jk?XQq$sae-Z~o?QX2%<o=z_UqJ2ixl^~gR{ri-MSa;|WP
zcGQr0qb`h`3DbB-K>|ihLVrv;i;nHlVt5cjq{$TTQnOvXj~kV!z`gawFZ9GuToB`f
ztZ^p-mKM}9wBUy*w@?N5<P9ElBg*t4%mt@pr%QOKvznQXW2gBg5fJTY1<=4%@=sWU
zl!}A=&>MTD6OP}a%3YBV<}dwa@4|&lYs4D#6ag4yNCSC<3NbJcM-WmJ7WXIfmET<L
zBg~*kEIOXzkN?<Z?UpRoQ7%RcWP@d-DyA1(1pBfJg*^zfHZ#@=2Bi#O*(iHWcv(e}
z4ChdlRx)|93|x;Q2k}|_1SZ88yX!aha81j{e40)@k0lNfI-GzDNl3WmA|pbf;-;Lg
z$>dhh1Xh5Vm&n~}GGTe2Mi{S26E7>vByx*#i!o=4b&E6vetpD$SL{TTA36C$6f|FV
z_WM`-=Nt`)gRNEAR>LMF$Vz%BeiKsU1CUf9se)tc5|+4^`NZ>zr-&o$Q<~D8Y4dKi
zU+a4SQta?i!u(E2PyUW39-%0iM4<Eu+#<yG*xusCl;Sk1qLlzNcT?I^BGq!0_apXi
zSKp@X3u?njy1`uBJ?uYj-{;Il7oeBj3!A$m*0ALi2m9QXkewTt!=5obGbtL;T{;Ay
za;jAa5XY*#s`PUd6baz}qE;WSZm=)lmmtq^e@DkJ>6;Kpq0xS-k%+Rd>B@6bc<AE%
zKvg0DuaPPnbHrkJysE8g_h_@qJJhZG=`a6AFES2NYUG!leC<BRk6(>!*{BvY<~x3H
z{gfN2Z^v|Qzb0b_dHFWvW*5?-yX@I+-BNb=?>h#_TF9utHs3QFHu6u!LEb)}njBkm
z3iXx3dB3kH2D(yx8wvX1<dtApr8Xryt=B(-tH&P~R1k4EF3`EDpCCt8Gx>vq?8wsN
z1snXv>y;|;NnI`OQv%t{P*il-0}Ij%8Tj!hpR_$W);Ha#>c@}RgP!0<oMI}jR111P
z5D#e|J<r(2mBgG~D@>F1Uae7J!yR>2nnxe~`+JM#w(mz_Cr;cCb6={$cq?Ba6_)*c
zA_(Fi%58W?*$tXxkQEb`ffDgVkQZuSD)Dt&g@IL*13={S3{b^#lVuYym&{4f6Tx$i
zNL7U+$Cf~Q4jWklPd7+s2Dy-t<D3j`p#8wd&>YK1$eI%>ljNuq?Z|KeD&%kzscs)M
z0Xrk<{ZR@(3fOW;q5}{{kOa9vDut>Z=Zk=L<g@H5Pi058Ae<+z5Q0wA;%FCuLI4jM
zex6bfke{%xUGL`e@3dpu2_3SR!-zCR#oZAaX9Tz_`-CY)-ar5|GPKa^b4-ap-c+@2
zL(oAoYoc?r1cDUy_nnYi6*=Gl*`S5uh)YdeEZ0E+41rL2dabd&^y$#-?Mn=*xLkzl
zJmtX%2{Sw*E>ezG33$e0SQ!~+D7S;;<HL+j1}{xB;wYcW$~u7Cr0Qg9=W9qjE%j)C
zXuxGuwKF5Eno+!rc1w&3fBD%@Va`5cQ*CVj)U0d5Z`cvOlmf&cEciE8UW7tM6|ku)
z*Ac}LYfwakFA_!|P*B4js1Iy!ur3gxs2$=cs;UX%#^=3K9eha98MA@O+GGm&5h-X1
zO(gM^tJD@VSYiNorG#QWOp*YNral*PYq(6F5LKw<t4rk_WFvdCZuwNT?PGh$@u+U3
zZ|Ew{1Tkk@Z3RCk1;Minc!Bfb9E8ZINPE9<2;9psg6;qQ2hT*zOyWOq7^1}iKE|2N
zvqXoJkf2VQ)guB8&`p6fD%LEZUQZ{CL>LIHV@yOAmrr^SP&7ekcZDIj!sYY~0v8d^
zYXB3-2GhW|C5F-3o_UnQUJ7_67#b5#J~>bXOTafo1^$^xJQ04B;A%v^xOLK#JZ9D>
zKCZ#8On2`Uyot&j&XnS(1ug-A6c{H22DQe7;TJp1>sq2K9YwavoGjyWzia-i99Lo=
zwU$I<wQ(m;Vn%HZo^KY@n*l4m%=+U0>XBFrJ}<K*+)abv!OD(GOYx?e;oms!2`*!T
z9QDhJb4(CgYI9h~p4^Q=`p61=GK0&>H5fx5j(tr%Q@&%rcl&Ufz%2rpytH#VZMUrE
zsZ%?E34eEvrwQ!xYV^|oW5ndI0z3Z3u*?6gPLA%(=dS{Qn85AhcHdUt6MXCWwEF>#
z+PB`+JrPfNAkcrK2O1|2<l(K$#=i0Sx4-o&`xqVl>mRMZ>ZAHMFS+aQzWtKT5h?aB
zNVFx$LT;%+6L}}{B-Emaf%ugVTyiTiR-}T&lW<cLbvG=6vPjY*PEZh<5Ub(ht0Xm?
zvjH&-yMo3OtIO%DX*vtZiVrt_;7>v`GU_STm5vFkLPELhkP?P-Ml>W#QRr2$5qE^%
zBU-v<9eoXj7y@xO)`HfsIY|iU_%&xt-gPA1@D0XdR08tW``%BiN`glpGC#=Ua?vs+
zI0<+XLtrVGHj$Kc3zekou3StwN=QazK%%c8fU6MyED7)6Vj!;;N-vZK7!R*Yr0>V6
z)r*;dJY4Jc%4aXX?H4zyFdB9Fb^D*2<KI}q??%wvd9x50g}T`|(|qdp-a+X6L(cgz
ztMXFxx8}UorRFEsz5BfHDfme|mBi<xpFK8Hc$vGOB?nH<PU^rfTu&zQmF1J|AV^1!
zUH_w5@8vOH-F+)a-@i2G|6=ai&v(rOC)4u4j+`HIW>3dG{q9eB-qH;(e(#Oy;`!el
zGj;!-<mF^Dy703Bh;Y}uyYN7w>%;MP)3ra)g-6GO&9V4_#<ZqyS|8ZFzxA{~l?K7=
zKXopintl5<($wn%b?ocSe^0VkSpD5NcO_CA@v+TM*01YeJ1H!2dUl43ChxeGMB8>_
z_RhLrcr|!A&Rr~M@4wLQ`ryEv@$M+-B(v`ro7TApo$J{1dy}yX%cqQ4Cx1`j2K4&-
z{@VTupVbrAtm8aq-}sb~jGG6O1Fh``&wtxe{a3vF_;=s2do}75Qc@#og+L<W$Q%#x
z6ry(opcx7wB2(jKhB1of@rEb_B841gB5WdAxKZiC_{tlk_`5<)XQB8ld5H!EnV^C*
zgorI|`HUaZFP>9E#u!{L>cRt4gI;H&kTCWX2PNh0tj)v!l6%ENwY-FWAS%&$nFDs9
zD#Y^~N_VCsIz!$d1LBQDYa|boS!A7M7#@fluX?BtfkZY9^v(FkQ(2!`cbQHy0K+n#
z_)^g+nJ9bi{Gwb08bnE}Tq*pacg3hci1Iw6lQ9HM%J?UFIr9@L^!874M<00zs<$&Q
zmtn$ehC&Z?Kvy;&oOIT-r^JBBQ^w;#S6cqcYk9t->Dxb^t-#JD@}cy>kK?W=euGQN
ztR1R>7}=~zi(TTORA`qsWSO%IWg6gve4=DZGU6|+!)$3J51K(YPssiF9cOcu4|oFp
zoY9%RltJiVr~92&yTr@e`labTS+DfRLpqcG5LR+FP-dnMT^LG1K8VKXjOc);I%^MI
ztPf)fk$fgnEKI@)@CHj{ZU4awp(3s470VZL74n$<!(L}|li7(S-jR}+YY<C$K^Ia!
z1%!dX%UVDa439=|M<#RNf5v}fY<ug+!O3{Y+RIwGN+FXwqX}Oji9cK*Z)Fc+nat7f
zh9E;(znl!k{DVzvVXcU#Tq8>20twvuh3qEg@}_jTGY>`W46FrDVFW}6(tsr7!5cdd
z*eKk~WERQI1XbS3<WrCUo}dD}^YHKQ&3fLsE*qYq+}M<QDPm5ho#m>`MrI@{A;JfJ
z3<iS$kq98sM^q3Gy(_fBSej%6ed8m$0mM${yes}MdkA0!6`64o>gba0rN#mZ6p$VR
zW)D^&TU{C;6O^Fr&eh+3<{$D@7|eyT;ygkKk>GWQ1jDGx%I++0_W8~Sj$k2Sw#K_}
zU?hm)Gp<Ox_x*3+HqxUQ1?gS77s_Qgx|2Wh+GQxAi=T`tP#31bixBuhR6Cn6t?64N
zm`ep5H_C7P?ay<?TMyO}S(e=f7%HP+*Z3C1Y@8k5L#}8URPqa|q_gZth(Ttmw>#6u
zmwshr(F9Ww{fbyaiELyo!w5m`Vum8w>;j{96#;iumd~z{#=sEB104Ck+B^RkIm+{n
z&z=uhXajf0;he1`o*BE%_DK0*lIG+#?fL|f1tbTwX%tezuk;^M%W0&xDv`?U`Haq?
zi493f)dF4{P!TOTC!uXpAlUs8sjY%dN}DvLN^n66A!)}ag{Bgb`}sca%--(Z?C#Co
zTziLieBOQM{qg*IpZ9s6=Y8Lqm474^3}B7dEV9Of*vB|!#In@x&4+?9GvD=KD<+1m
zXM2tS>KHf3H6-=ZCx7i<;XtE;&cU(an=^6lpWHW6di-Iugao%TfJSSZ`#5wOY=%Xg
zE$ty-&%ulsF=H%|^=)O^ki2omcrntUAY|YIhr9>*e+XDefeLg6hG6!0?`FkFeTW_B
zj}A0B@F^WrsDdUn&i81~$t+HUVz7!XO+%ur@i4Iv`dXMXw+=+5)&(YYtXDaowtf49
z1Mhjm#_eSm7%<R7BZDC^;}I5vhWforrjASv5&Q2ws7Iabs84-xbSSum6&qFtwpb+&
z>t6i`D<Ai;sqOg(F<XZM1G3c?fX?KBFr5X`vuM=Wxc!lE8-X3GotLqw1SEcQjT0X%
zKK+RfI3&PkD?zow`tjz8YtLh&T&p_BMQTid8tH6>qIP+>ef7(TU_I6&I835Ao^zzA
z8iFw8qj!OdR36l!B(3WZP7^Cr%z}iLRagnoN(`!FQ921;{e0)IGYNy01rLW&35cM*
zTQH#cZk_rFIhbL~JQSjkEOj7M=)_taVnLYA5Pr6UWtxD)AcUOAiMX9NtYAKQRS#$(
zS&Jz&7@fWRI%X=ZQfLy8nNXUiR78qQ1wVR<1=hggi6ad!*jGc6j5Fht@Pzkwanu4C
zPnK}osfW@F6iD=Vngpee=WjS3`Y?#N7=55KcMHR)^##T$WJv}FADD1wIOus<5lHbM
ziAtz6$czoPXN`QJqnbp+mjJ0AbWS|X`n=dOgJcimp!AFqsXWy#(+v#~YpA4k3g7St
zPTgW7=|?2Ys+|eldIrHlGmL?b$1~pir+gwGMiO<6FSU`<@C_-V0P97^%bIIN#u|!W
z5UcMnL10wvN#qEtrdSoaoeH!{#4zzcKQZO{tMR}O>NLob0`DX!L*TkPZ#`m6(U1Gb
zZIw`EA+N4hudzx3C{D2Slf1f&WVh3Zz1d{##@1)-Scx8(_V#_YpPdak#@3Lv9gYA~
zEMsBV;A<GA!>{CAO(}V@N#22&1(nY+6iuo$@uKmvjVixXJs2<*=y9n&iYoLIi&iY8
zJ@!{Ov7!jBs8mf?I~a*aVL(S%WQ8y{o5dazh8A1UDskbCpO`%gt2MJTx5zvVX(<K`
zzPTn1l)2hk#h%w$XSq`*O`@SKVw?Tp+q*s8H1GXB^A;TDz2E2m@zp$qP|~t~;@<Bw
z^(`M=DdtK?Of$5ozxl2?ZNsNIqa{7!#qW5zUZbA_)-p7qG6eAh6#&T2Xq$`aP_8OD
zvh3RTVt}C#ayQ0ULBYX{0;W-S7M|fIE8!mubTojex`yYAIZ^FuY2=dNi3322N*ak~
zSau`?aj>6xmsd4tMo<+TXofY9cW@?SD<*}3LENRm9isYp1h_%8wGT4;WOckMo^M>+
zsoghMXk1`i&|i%X>?OlT6q>u)a2nNELr%P4ALY%$tQf(QWTHG65CF1$N<JJ4Q&jrc
zH+E9N_WERrmFChH%`mRMLKTq#4T9y<N^UiuQ2@F8SEhVC{)gOXM@{3>+n^#Zu6<9<
zMHb(3yMV1P_)so;TLcGwz^6GRa26?2rm;i^M46JU_&UsUif9la_eKYZ<<5+Sm3YGy
zKxc0haO|ZUKE7n9@QVN~Y?e=kz6~;{WUb{hDPXs$j@?XH@k1CJ6S@(mRnNmthxNdV
zZ+Ou+J`yNG0R6xpI-d`rt>N)w-n0}@D}kB65El-HnH?k4V=VDor6CY+!Djdt4%x3m
zQRqL#AG{yQyYQ>P@@l{|2H>6k0UtPJAmIpP&U+KTc8kyu6U8j^896kj%wy$_o-)Nt
zWX8^?7ysd<l+#ePBGgMGM|gA%(1Rq21(7Hz{Zj_QfW-7dg4&=GcDz+hT*-C#1fv<c
zI5v=Gsn)QOLvMpbR2zAA!ogsWVYzcn28B=mp&Pt+9JMDkyuEj;UyUH)c9)$EQinn(
znd&`_7j-AxZUqBQHA%z>SsaV1;Y0Hta;P9?2-X=IxP#=GC(rYLMnD9eF<?_VSdfLp
zVPr>=2-tjWkBb66IsK)DPu-ZsP`11L5@U|QQ(cZ8-49%3Aws32T#N}fI+6wyD@)i#
zKDI)L)lCGSrbAd4GQ!#<MFGoGDZB8iDe%A^!b{)e;e@JzWB?6=AJ9fJOgaHMsT$r0
zb}|4m)tO2)0wIDYeW>8N9!u!m_yX%8(#8Q^i65bj3_F2^KKnvWBHBbq7{r5@!0{MX
z$Pe#^n@IX15-`3Vwo0`{AVr~g;fdqX7X`~yG~pnrB&DUb1_6zQwFX*ZHrk1BIs{v$
z^=RTWqOK$cRhgcdlichI@A&dLE(I*3NUZ@5%Up&<Qc3TCLtElJqzVt#hyh~Y%&OZW
zp>KWsOIyw|NCqDms!Rq=?J|%`nGy25F;`jIs6`x~9;M0{s0pkBYng=l^zMNdWlJ0&
zBrg&jf)tOi83=6xGYHu7#$!_Fpne=><2`RmA!)=d_CnnuLVZQS?5USDM$x}$aAcZp
zqIWUsbe3q-L`xHl5e3u&nG0S=qTK-j^n(F26bB($T+wt>Cq~w(%R|`2-8J4ZM_^5W
z&6)^tcP-$cMD0)z4vo=WMA*LKS_aR)51ez4;&Q0ln-CDW9+wprX&6ESfJSNYkQ_fa
z$TN`~A0bv^!r0748fhN<;h5G|-g5%kyatS)YGn=#nC&^^yfF-dfK#W$?R5^UGZjc<
zWQcj&`78BWG>y#U?85WHKhZGnPhO|}$Kh;^g3W!E3!D58=K}1s0d4em%V2ckz`4Ag
z1cEs%`a(^|A=a_wOay#}cgbgtOc6NT#i@cazjUaHZID+WTlxO$I3PzDO|Z#R(p6rj
zP{Pt-qPLwN{PiF|Fv|w~_$W*Ao+97Nyu+1ABIMECtm95n(@saM3rE(6JkfIPh(~;U
z5urGbzv#tB+rEB)gAvo3KI?;b5!wW930+Z(i*(d0NC}1Fo<EDd2($=*2|9?j<QWj3
zhUlS1)dV@42}>zNN7<w&v{T3`DICHIkWYMc;9JBB`c+53Z7+ij<<^Y|5E5y>jat=`
z=8OA7o7qPvR&$XPle~^Juy+lgq6eJo>TG8drK^R9Zc9u!R77j!dFxA+iI4Y<ObU8^
zutp_yzhO1(a4HUkjZ9JsoE3lTjEH{x7+B&~Cl54Xa@GP&K(;{62sMqu5lc9Ywg<D1
zzh)@B5uO(?&cp(2LST&?p^EHVcq!5iBrEJkR2+pe-tFNc;(ypcBoLzG2aqw!{vCqg
zK^EK7hbU0jA!+s*X_T(r5^j1Cg)8ZUMC>9#<CNn}T3R4u8(ke?(>WnQm!VziW&>%R
zqI-fvIx>x4>CCs5)J^I$;}IPfYR8%6sJ=wSj5BCqQs;z={19T=fNX&Bd&^J_T|ieS
zibZFn>zlQh;25JPquFQoeWzwZ^M<Mi)tnbwcowJXAdPT&)q|J9-Trazt}aWbkJ_=0
zy5{9!9qpx!$kVbD=UJveElzc$0bYruE3~sE2R%#T#aDglCR3MEw7sn0n5cOQ8aNR_
zBZrfRNg+nN`KT3fIOC>Tw%2xHm4|s-WZ#g^97N$!jwCTQXoZg&m8t=nP4qs6G>%M#
z%pFr0tWxEUubi!?Od`Z3szw@sWuBbvf()3UlHMKSTS(360@l^BJ)TY%uvDX99pl6S
z1!trPo3UoJ8B4-us8R*^MVH6RNd4*G=v)8XFSb7Lv9sfo8c+V+vYymf)R6%WA}r#W
zk;PG>H}!US@T3(;%i|tAyu$sD>GdUE((0Bge*V)f_jY3n-;}L;9hL5I>2NUDD?f_L
znm_z$bBdWqWxDM$$B^kiVD3eASRH3BLJL{;=B*cfOz7lti?%UP7=Jh}L`uS~NteZE
zv{$Z?{Ekb4iy!JoIT_{^LE++4D2N$NJaXV%B*LxFBt3@KxgpI6tbs;>AA=vyR&i43
zdC_L##sH-Ur9w}(5KnA42csYaen6onDt9SizKV0U!0a68umq)yAg!4LMhG!hoQ-oW
zBZi#90k|^92*~j}E+QH<9^`xa=6g{O@laRHgUL1%1kQXc2USiXR7*g1S*#_NbcY*;
zpXSY6z_J`KW<cb=^7*#9*nV#48^cQ$48XQxcvBJ5{2>zh(k=_+Q`o9`{3Hj5fo5Q>
zrt0CfDMRA0PrHE`!2&n~9m@^b(2cEez$pff`Fw)IVSXP+D!%<<u|7pDF#tG>I0C{!
zQ<x=W7Du9MB0|nN@~Dxk4h;QLJwOv!sTuP7wMRSYQH%E4XZC3hNlaioII;CSvy}$W
z#4k-kKA<Cyv?YuY?wNPgl9YIgO8QeJW!Ozf%IZXY`|dy274V)4Go{=?DYcz6;ZLm-
zG**=l0N~&Xy1OD9FJe;_1%VphzVXcFc5-Wh3@o8{^rT%ZLaT1@5_1Uv(u?{v5?!R?
zs8>6baprR%AmK6{Mip4fx2^3oQ-t~=Q?xQ?@@}4*`q4DNjg%(P$N%ySzifPqXAr2*
zNUBe{H3q;;TH0W6S#<(3NmEHa63nTN3k)^*oy!jah?=rFbb};JRdu)L15EJMRNv`v
zkts2-9Klp%XBS^Iv1(M*_^rglIxyk@svxcE8YERIM{RvKbc8}m?2RE6KXHBl3vg$T
zq^D@!?DcPSq7qUKa;dwkPi>$yKDf~ZNE0>5x?(s}H>*n8tdCXm;%6Rq3HwCO5vEJB
zR?r0&GHRA*oI(krNC1a4fp6#&a?%M6DW9QtZ1-7Kq6&bqbn=l1(a9ONmw+3<TsEGQ
zN_<)OC6(2=Al>xRxsyT$)Fc#i)zd{16*O^3p(u4~5lXTmCnd<GF)w}I@4OnNX4K`v
zzR4<ONMyJYM=NbS$i`dp)ni1H1{iHNtu`cdGcvmIqMw{}mVw1w4L()T2+$E3R#Y@v
zSr$V7$W^xRAZoUIp`7?tcnD5I788j4d5DERwKERLHBb{eNg51+S`4L0{I*AdEnre>
zXo43FV}R2Yv}Jxmg>(=8lwdj-rU*azQZUS@;_cWxZGj~e66ioiv_MNV3_-}_6{4*Y
zUv+c6W)o1vWR&%1N()l==hGPW_(OxFRqiH@PaTBTCSuRUsIzZ9hy$&Y(TMQipgUI2
zdk%?EA0}eClo%9WzBbZYg>B3if}o#Y#qkb*M#p%=y?w-&8Xlv4+QsFNw~q0jse}0!
z@!|!dTsgm#Zwv;56N5EgOi2W54mlBQ*&F>r1qj3*n<u_>ro~`VS$b1J24O=<A%$-t
zh6PM6Ly-(hrNFaJ2b18#MGc67DA5L+7ZG96T=!Bvs+pc%{42!WE*MjwYr(GV8oNA;
zVL*UFy7tOQQQ0W4u>eZ8M+KX@2^s^STStq9k^9#7Zw$(+rvOZ&I1PZQs6Nz1()d(b
zL7hXRJL_IUp&C{*B|a%u==d7@dWJ$9uYoZq;&m}p#5}56lNbd=6fz{}IIzj^ngl6_
zoT%g)x*#w0SkM|tz@PopRq6~4Xc-pj1J5z+L=LW`-yBdI;*J}25~GfM^^2&`x0|{=
zSug6|@B^d-xd0}Ti(EfSW*{>myCOpi?M4)!>@rkziE5@D;!74*N*t!{k6(GY%JU#r
zX?RQ)Pg|mT7o)Ee_+~A&GfNd|xkZ}%B8p;s!DZ)?a8U0xC)7kmTsT-Ctk&?O2a`Cn
zjC6TujUUPRqazZ&YY6Kj3Q~2r9d?M_NP}5TdB3V$1QqZ@bLtrON!f6x%KlrB3$Y?X
zNw#tcTop?u0WX3RxY>`tm%Ue?e7Zk<l_Ue{$dv5BcDHj2{bL$j3L#;@!&5=M623?g
z3)k6mE#v&dnXHV_w+^`aJrxs%!bZgS?Bi>5yOk5?EB=}Q7dOuQ!<mz&d5ivV!z8nM
zeA%1l^3`EWx*P)DRD0D+nrVEEb^+4TFcUTRj80{_Y!%75N82@>@yR{U_6MY?uCxZK
zd>uzoC{Ljh|JfDRQo~o4#}#s8cXKWsaBY@UW#OP400Ldth74vo@K9c5ff+J*ed~wM
zW*7kwC{^HNvH+jXy;d{*kpBibGB;do>*$NR`r-nHm?a_1@d!VmV3#}zc#CcxWVRRe
z<_H-|*C?si<%>~;&$;#A=BhOiL$WRn)vgeeI6r|BpSUtf(bNz4byX3Gz~oE7jwGR!
z0C%{yw3LMh{)TNP<5c6_8cW8qz5o&|P+$m@Vqq(?o&p59lAYs2AVo=9sQWt}O^!!e
znMy^M-<G)cC4%Pdd%*d^(CGdU0e+a3X@;P=QLGFC(U!~AYRR&jf4|ESBuB47S47I@
zy+l=Y?^Y#K0H!l0GjdcMrX_sGPoLmZ0(A^q>|iPiP+zdpVpZvOnZUyXpFGbmtEz#u
z1SvW1uDu3uJ04w)d7s1aQ!_wQ8|W7c`tL>rX{S&f`l=P2`76<hFP~#dA|8EA0yG%}
zgPb&IPPf9CcLzwk@b7$*!}Vz!+dQY5z}5^0$+U1@^Q>DFW&E|T&1>R2DkV?rs)iJ@
zV9d{BlE43#tycge01Y`NJq3k?gDPCqB}J-K;$7=~_N@RRMo~@~W|`*%sFUrY09vJp
z5G(2%-uDR7OfN>X;0uY=AQFWrk=cN>PUmlpu}!rzJ^^_E(RpzOB;!cyhl-E<8W9i7
zs}Sm`l}Amn-#T$Se)1zX`)22jI3)#C0~BRbzy}q!d+7&gt+7E)*GnsQER3Ccvb0gY
zkqH4)287l>E08B-e_g>^1s7uN4<38kLM)4Z6k_2#y6}kzOAjtrO5Wa5Yk<WQw~CJr
z5B*e0JA7ppg7NM&lB{`^A3k;GY(1~WGLyP*K#y8`TZpM_Q;?8~-_feGJA3iAGbDNZ
zQaR}GWurzuH$5c}TuE(0B_8tPn4{V34Y&IeyKN}pLIYmDFd5Egmun9$dD%j<sEe7y
z$3dU@J}+RCXKj|l87Og}3Ey_JmO!r;@@kH!ukc+YAOHpt^(SI7-fcSzmXiIlMG>q@
za)d`^?GquJeFrSUkY$ySBo%eSVlOiQGxsK^8ffKP$k=EOiHH`+xjN0Cz3pQ+)c^uH
ziZ{~TGVYjGA}PI#Z2G<A3~2khX%LiD<zOeqWp>-UfW#Pa@D<MhmK`%*AS)4IZHS#n
zrBO?Qcpfk!uuK|}%EWzV-CK^NW(t`?Mmjrz8kCA-(mgWqF(y@Sge&bJitBmEb&xdl
z-ZcB3Ti0f2qgU;(z|T#t@JZ6)V^8tUl6IFmX%SbD)`{Q!P;_>q5sHA>uv;DQ_cWNy
zVNRg3wM8bQQ=?9o---^SWG?N%$)9`BRnVvO*+#lG1Ug#iQ?vP^j_|cy)bxTzPW-kX
z`WnaXf>NN#PB5vtEF1XB(Ulyrb2oe@by6H66k~+*dF81_on<HHp152#C@+5hwaW*R
zLTDn)2}0XU*0V_sxi%SBYcCPnT10CLVDS^X(gx}$&#6KxerGMx3QgZ>2e>R3C0jba
z=U7uUC2dMjVh*V8I$k2!`qld&k;=TQp(hEk^NKs%#?O7RLut;Urq0OOa$)tA(vpRk
za_001%PFvx81N{3mh&=i8qYD~yQ-Uh%PlPA<uI%M>8K}KrOtV2zDlq7o!?87oxe4|
zb-Uu{w<T4o>C~Ftq;)E2)M+Nn^FI0&cUnE2ZX4BHqKhHd+|Ud!{`udY2VfbuYsu>R
zox7rg6fXSF4uv_3vLv=-%4VKvT1s(*L`&xK=?}S+D>)g;tS$pInOTxQvs$|N0rz^u
z{B0MuI2}#nLMi0QDN<t9llR`82Y2VXS!1bli}t0%yEdF%l*V#Y>+|PKx5t&QWZ>D)
zmD??{En!`*OOunYem5U^ooW}^K|PbwNz$2Rh|DdlE!Q{oGCbb+f}u4Ee0bt#-|#v=
zZJza(yQZHx=z7|G;*rGV%+#xVnM<*(tqU5>_~K{Z5|x`XmXjX*!6$MwZ%>o~iC_EU
z9KgC%HOtv0c<2IRu6W{2#r3B11{S-YGDkyZD*o&*Wacj^v*^iYNkn8dTFr#{g^i_m
z7OnkRqFh2=k?yOvn!B=4?{x`+&TfMEi_@{J_kCoeT|_Q@IlYK#i>vbEjatRaw?p2=
z6VKXIcTINfD>hPJ9E*#ng-DC*?9;`dwApNSn>|b254Sbt8~F)rdTnJEtO0%}lZV!u
zmPKSHb@7eg?d^UyeysjSpIYJF@1pGL7TJjSqL+*F(2vh7c|FtFD<jDzy$}9(k|^M7
zb$S9s4Dt0x3t%q+u{ybgxYLHPqP)7^Dti7=QLvH~=NffBt(23|LOt}NDJy0s8DJ6_
zIC*R>`sgCv+qI$C4X~b3$u&k8A=Q<0b=T}VIy(S8C%v1Ko=ed>R%SLTYTOpTLD`Y=
zJcV7B>yp!ki-dUm9-ci|{^i!;XZ~gGIQ(*9cHwf-;O)>;eA{DcU^B&{Tehnh-#Xi_
zD1Uyz4wMKeW=|yk`a}7-Y1g7aE~}-TtMq(CQ5tJPEKp)Aal*4*N9W5gN@6yykFP@G
zV?*)y`odh(!GX`ezl5We`8e5<7t5n|53Q}%lP<&F%=)=Umh<V{g4(B#L0Qq2?zIcN
zchF`1H`8CI%y_M0kq2FhGWa%#i<}|{cU@43k#?s(?)YY5)~UG3TXWIj_Z5B2Wq~<e
zTE;T^(&kw60D=_vsYh4O?r%%X5kK+!DUG?m(*s4-zO?D4|0pDOGjJN2Ma9m&h4i$C
z7XQ7B0k8l`VOCbLbA0c$3lJ<hqhKzJ*)A{xa_p(zadf)1;0`Lxq<A0w;wqd{H4X}v
z*xFr1=dE@tb&%%No^yLndN(J%sM*_AzNOiPT+Brg8$-oh%RcJTL`Gqgq+k|o1e(ZP
zX0k_EUIF$b){|I<1bXHoLns}yR<*=ft?ZpdFLw2yqcY?vT+J4E?XGgKDCIrxyqkBP
zX8?4pyQ<A<N6PaQu4WsMhmVeRdtKR4JQ;;OiDd|-V^&XM9mSJT*ppa>P&#H6EwSDK
zm*RGP)p4iGWV&|O&R3N3-U;;o(-Y_&O=X_KqRna^+#T!o2<s@GjKZG8GKA7Gt7wV&
zMQuV2$0z>2BjvdYPnW4Vmry!Ze%(vV&Ux*8tQdv0r(cdezD|4dg<QQ?Et(i*o{HLV
zKYfnNt*D#3MuGQUwYchEwb<Tp7WWcc4j~S{Yh!y%xk@;5eEi+7tMhVxf2IJwy`<MR
z77ENgRN6Rto{|~==JjcE`QNL-=aDC|WdSQQ-{|n0KnrSj&M4C5A3k2(17f|!xX%5S
zQCehI7Pfq8=e&1qI1Nrc=xHY0q0{^+Q5&~CCp}|$w$EbVu2DZ)uUc8L6X?~G4^(=~
z=-rml{i4>`yw&-REDf7{??Z1t(5$2=zs^>9b{_45Ek|*F!Y*$Qed6{)pT@LlJR92r
zFFd<iBX`qRv%`u;g&c{ZU7qxD&xItk{?`1$^7%Q(Z(W@(PtQl6-&0-h^N-8+Ad6Jk
z)%~MI?PZX&q)3qsocz_Jy%(a};grJshSO(nZVJuKd@XoXTIS2f*X|q9hyQDDU+*A#
zw}a?K1;k$U<ntfNX+JwuXJ#vOkFo=*d__gte7BUP0K16mnG1@5;$Rf-ScuE8L0~o0
z(bn&>y5DBqp47}*nvbUsQd*GI4&RqE7)b-0Ov?WGpB&wOUqZj<rJOV}l<=|2`rrB5
zbf0@WkBs|rF2fXm;P;jTqqXfk^{94b#hRz0YlY>-#~Q!jZYAv_op}wjZsXgY%*xKr
zYeP_@a{R{Y8tJAkZRF)i_@#+IKQB*%j&*Zcp@II6u)O%XXB!o2jnono@n5{U#FiP&
zn)GauI+g(>&AQ{c#@lGGsm+<9w0Pck7u|?TyVe&QMq3!ae_VRDMYK4ED@sDFk+WSl
zTmxk)4^4TVKgq}&cbT5I1Dg_+$CWwhPXUMe@%Z;C-t&d=zpaELLwm~Cgu@#`imqXl
zRfqfQfWD&t%BgTNC|z^;j&W~eiChP;I#S*ecxrS-e-s`Xyk^?lF+SQywv}Jm9|fiQ
z^p5dLxUsZnx-z}xq0n1Dvg7T;o-bha_f7mkX{zRhvebLZO|Kz#y!ic5$&30EgYQuC
zDP<jCucEKjz?0<>9{K!Q$EV-x1hi#b!U_1FyvP?`?036i+p8u_&}Iw2xKs1I3T;7`
zT;sUQ{&YW?QF#Y4SN-_H2h!r@e>bV_vVr9q?cK2T2<s-H`Q`H^Ha)*Wr~7KDwKV?6
J4W|mb{ul9OnoR%z

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/MrDoNightmare.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/MrDoNightmare.sv
deleted file mode 100644
index ea1623e3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/MrDoNightmare.sv	
+++ /dev/null
@@ -1,192 +0,0 @@
-//============================================================================
-//  Arcade: MrDoNightmare
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module MrDoNightmare(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"MrDoNightmare;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian mrdo(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,2'b00,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,btn_two_players,m_fire,2'b00,m_up  ,m_down }),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 	
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/galaxian.vhd
deleted file mode 100644
index b881e738..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,446 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
-	-- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 014e6f7a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,88 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-library unisim;
-	use unisim.vcomponents.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 496f01ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else "00" &  '0' &  I_1P_SH &  I_1P_RI &  I_1P_LE &    I_COIN2 &    I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000"           &  I_2P_SH &  I_2P_RI &  I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_video.vhd
deleted file mode 100644
index dbe0d0d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,433 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1K VID-Rom
-	k_rom : entity work.GALAXIAN_1K 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
-	-- 1H VID-Rom
-	h_rom : entity work.GALAXIAN_1H
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/scandoubler.v
deleted file mode 100644
index eba1d598..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-	  
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/MrDoNightmare_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qpf
deleted file mode 100644
index 12eceeac..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 14:59:16  November 16, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "14:59:16  November 16, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "Omega"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qsf
deleted file mode 100644
index 4dc86db1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.qsf	
+++ /dev/null
@@ -1,190 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 17:11:29  March 10, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Omega_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Omega.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_global_assignment -name TOP_LEVEL_ENTITY Omega
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# -------------------
-# start ENTITY(Omega)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(Omega)
-# -----------------
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.srf
deleted file mode 100644
index 14cddd5e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Omega.srf	
+++ /dev/null
@@ -1,54 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/README.txt
deleted file mode 100644
index 60917297..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Omega port to MiST by Gehstock
--- 8 Januar 2018
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Release/Omega.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/Release/Omega.rbf
deleted file mode 100644
index 4f311a0c94994bebb5fbb79d595c9f66b807c32e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 301983
zcmeFa4VWBPdFNZz)0hSum@c&^<%ZZ*HG?RPu`P{>x1%S)-L1hivcQ%}SO-Wf3E!;4
zhQ}Yty~(mquIqG{tR6H%k}(@CBw<E&h!Ph3fwSRmJ}lX0(FU^EK!TGe36hd5BzF^!
z6tZ#ni0|)zs!M7~^J$Ooig=DjQ&s2lJ@0wXd*1hdPSrg7?EK-q|7gSCfBVF@zx}P_
z&ph*;?|kRG-~Q+Ce&^fYdiL4x{?m8AOUyIR{PVZI^{s#V7xP#2FFw^FB!vE}?pMNd
z<3O<&`b+0=&*!T8N`(Gve;a4s=WXTjb;39ykJnYtOAV^0Kjih#b<Nw$(^Xb&=JC2N
zl?LVSr$P65{c~OO_VRR<Q9XJ5bG_#EE%utXljj#53i%w&;}^Qlm0$6BII|ALEAGr|
zn{XaM*8)L#M3b%xiaRr8DW`rbJ<prR=5hIRe(jG}yW&ZnrmNBw^7{h>-8Tt&yq@!*
zI0ZdtciDZOo?rXZ`tS2}T@|0xl;^4ULY}UxXxT`})AFn0b+2n4^0XEqzt>gusEwBs
zG`AHLmk06X0)p~<fS@v)2q{7FO4qaGc)oBALFsSm1=W*>24SEV+%rO%ps4M=kSD9m
z=LkCpN)kPf_riZA^xyYC=kfV9r(pv@b@t1jc%XD$2MHcQ{Z&w09<rG1x9HGaepR1!
zudCt}bg#HPC@!ZXZ!e!8d4Kb^@~g^7MnqSIke64w#!%%I_xprg1`ZMw*B=y@hdf^S
z^ZUF#T_po~$mz=ap!B>Ss!#1t5xRuKgf9{DcILVsA>?U!`?_u+1ihek6hw!viq`c%
z5he*CLA0sN7YK^~AVFz*{?lI2eID{SUH_cW|9t%!VGlt(SCBkpcY}kXK|ymuLGd|1
zH0Sd9C4T5xJkeD__c!)J7L&#O3E?S%lFlIGdez_GzMjRqA0mhjJ?G(<dO`7$4e?a+
zpO4*LgnT~CH&?#W3wd7ElhbtrLG9%<<=31BU2{5g?-On#s7ldsA3;~ut+>36#az|)
z9R$&%ahL3=jk&^WdLd6&AKp#4n4l!lsb|TDbelr|eHOE6)8F+%o~HJ<^@XushzPn>
zlJ4{Hsb0|YC_&ec6U2x9(9avi|0N+$7k};{<j=Zl{wjzbjk!WTZ*>(d8XvW%tLBGD
zQJUmbWhDoqB@gq-#av^g_WOg{Q^+XFerGY+@89bMJ>~ooi$z-=a-R2J#sB`GwEpLQ
z8g#F5pN)n*ZWlrA<+Mq*{+W=|psSu23jKOS_xW7OuX%fOUGw(xbkVN9<?&*dXi!`p
z7NSY%dHeZQYivFj&g6~SmhM#0z4XU>2wx{i*0lcWDw)i~H+w<Py3OPBtL9jTp!)JS
z&D;K<wEm#J_djP8ouWx}i;g_}S}*8XG)hJ_kJO&74--V2?(?8H>7+cYoh688YAX*P
zBS>H5&svXi+Ge|ck+7Q}`Bb{rr#w#aj}TO+cr2Sl;Yz})GlJsspd`_tAUb3Zh)%5?
z`+6Z?hqcxyC@s6oe*eF{aAut7Q23c%814&s`~6qZuaL)y4#~bHj$e{lJ?Ei+p3ZhJ
z@Z)KM#y=0Dr;m(TZ}0B~(V+|?U-c+j^ojTV?dA07+8=-BeNIEJ=Ec|C29f^EgY>F`
zY%~SM>sf2nI|xI)@GAs8%kI$iM+l-pSA`!X=&Cpc(IfjYr$hYJeLgpGX6RY^OIO)L
z(rF5s>lYDZ>;54jx2tvi>^$L29sfTFip%N9uWGM9<h12<iSM5zC{NBStv}*}g6{L6
zXYr-~dggsDSK>n+GzW4!O?_8eIUP#Vb7rMoaDjNVnxHtX!P0LE8ds^1*AtYcxc^9y
z-SQTK(q*fOmx_~(md`ciQ~YK^KTT>|LGx8trRl2r6~r3_-OF~=RqcGD7j*yY1YPBe
z$+p*3cH&0}y3gbEoCnEV9wdW#P}>SQ9a49C&Utz!9qOOj&O=U@bcXz6U3d1v=LsL}
zg*;BW?CrfE9(;(PYaW!Od(ohvbwWY(W-(b@K6c`j?(?hcGTq-wxPqXxw-OYWubGz<
zw4N(y4$IDv49pkuvf_v2K(Zv+*SewgMM2LC1+AG1c|O%6U6zMW6LNi}tK#!{qpSL)
zp!-V+y1tGeSy2!jx@s=#Dm|e%UG=P>d&T8JaT*r|(W5@fe$M@IUGwqD<6cF$gpkK;
z+-@Q$PC@IJo~5s3M=R+5CkWY7_PbxVYV6d0f5_VtO?k-UbX7YFx))9A!<Pw?t32rW
z%<#k+;YmV&R6h;6m+a;3>#Ft?bT1ty`I2sxu2Imu|1*N(@}TF1f_T&)G-ow8^Pu)-
z3+ya>M{}<~O}2!>Y;lVJS}*8+DWSi<mHQPAtZ-n31B>N=^q=(UY59}W;O5hkW_hTb
z5%<V1S?jJZcD(O?iML<eeZdk-%$<GaUvEAmv3?q6d`9B@k2BvnO}EdVd7;!hFMP>D
zSr(msb}tuQ^z4kwPnZurEUvdIF~0|`s3iPuI;7;GUf{0b5H(m#3Z7#Hs2-`D3J2XH
zg}Z|VT&eL9Cvxt;vtWzl<?VIc2?~_welRUMR5GYqPYZi)AWI&C(5?1K?#%fAOhVV0
zQrk~NH&-r-$a;O*aq5-gROEZkn~EEY<hXvk)pV+Ez49Ya<J3LnqKwUuMElFmc;m8W
zbF@J9Lk~5JQ)SO_-uYVB38uR@HfvGUP2wA)Daww&$t#Q&RQT3UXabV2CEA*0Rh-ST
zz;zP!<z!HwB*o%U(00W%$Jx`=Zx!waMGCh^60$YIq;TZFpRc543Fo+=ElVFAXZdHq
z3So=qz>175o>y7UevVmXu+$3r^Ur*IfB)n2yI+|}OXc4R$5uEt3kNjC+q1+!m#DgX
z#jm`O7WQ+YsaNL3BK?7ky=4iNFaGX%%TkdlLCVfu%9iG#&c~DT-+qAPz{S-Fo2KB5
zG-W++C~e9{#Y<eL9O0|reXJ=uYtw_Nt!>E#oJYRCY~!r4nXgYvOJklb-$4JXk1nn8
z`EsA*3ING)tP_h|I6bj&o@eCDZ+}Z1!4<9}i<u+Wlf>s6`N$_;rA6a~sCw0_yvsJc
zdSo<wa_r$o6zTWyW9hB&!;SE<?RUl>AM)P)%=YNL;gfg#&S&>~<bBucM~^n1xl3iv
zxJDPJx7N<t;!#1gN1L9xtGO|HlpfwUl07_hyJhZt(!BVzuRZwk#b;h1Cz@jUbmbHG
z_u(T8G`vvqa;va~+FMLI;0}n?%w3xnlX-D@mPv;R{i(YTydO=o)SymL_N-zv_uPC|
z+;fgtrf%BypOa){9Xu0?roMN5-*fKNSp}DKrL4>x`)_A8@SG$5xAT84%2x=Ri!-yt
zTOod8Xj%QS<umPOzW)=;wv<!`k6*bF4lLP>UUGqR)$XplGw<EI;>OQ13+9RHEe$V(
z4U2h9!^sO{(`ypG5LK@|9?00XHubAVB3a>Y7?XAS>dM%=pV_hPz2TwlH^uvhyvsg^
z$u097`#ZC+&%8#*tU-RR7LT5Q_R~!6-ovZ^aalFoJi@ocBv!ue5{t~4eelUoox9+{
zoK!D0;W-(8b2YMJc+AC_x#G`djxFCDe-Qyxa}D&;;+K0?F4xY5<18~yvV1azrMxsA
z&zE~S*AeHtRhn9|4ZY+7=c>_dk8>>BIKQY|_!q)_{hma->(h^|7~RWgbT9X&WwLCR
za<(-%pKe}4+PQ39EukCpXI*YvVgA;Zkh((H5}0MPiet-Vs;wL{St|FJ{oLuY89mN&
z>+5ruvgKY$mTX2ZwE&p%HE&zGsLfSkxtFXJbut&HXN~WzS>JPDw>t9z5xsKEM4J@L
z6A-WEQ@zW#H&}O_!6)DQ(&gzRwJe|I$KisRx7&{-EDv$ZtzMUhDr#APFh*zz;p#)n
zdL(rTEiaIDF}(~IsN-bv%m;qw<o)x$fwJYBnJakr631it6b211AY@A-?OY~o`Q&x^
zRuY(-9avnpGu(69<1_#MgG(C9c{4A!%&eH*^RoNQ#NIS}fh<^B``$v*>&M@}eg*IT
z$1|nmIX~Br|A)QjsJ2|eyO%nu=kk)g)V|D}f4LW=xm#Ld%5oF7vQjQ-0M2FUUp^JP
zf_E=TC~W4Hmnu<B%O`>_A|L*H%Q$vcUaEZluXO(Z{Zi%GpMhGkg1hzK4lLW*?(9t7
zl1Z4oK)*#)FU+22(XlsOaxQ+AYz2m2^Z=g9crKf2r>K0scm2};eCt}_*it#T!m)FJ
zV=q#y+wMu;deO42S9SM&dzU(zbLT(D_0spA%?+zxAfi{G?&X8J&)MD2!Q<~ZH1}*>
zYRWl2yO-LX+4HX~?z8h{?$~phV=GAa+yggD%DFt2%Lg;AAl<VJ{Q^-dNH@#hvWeiz
z8<o$~tX+Ada^*87{cq^lKYy@*3R@ugroVpKvSHmX@OMnc7wF17$+vxD<qspw!=71^
zR@|Ohm@;qFGIH!ig-^}P)I}$rvo?I?){9=Y=w2+8aXEXbqlyc)xA^pBlzyjt>xKGA
z;)@jQ7SES+oGVWZotpyqLI8*>=eo1+W2~I(=HuP3UOuq<oL82M*VOanTu#07LQL=Z
zXkUEVa;{Y?99ul!vz+HD$5xE)rH<sXnkmbwE>?{0C6A?y?s{qVuLlm6(mBj=^BjvD
z|6ku&GKF&%SZ;m3T-#^PZJ&N|Sl$T1EGIUQnX|tXvc#-27kW!9aW=$0CmmG2Md0UI
zPQ$V^`Rw*r4t?c~4>yjrZ}-1))x(W#?H!Hx@dfXzo@&`ocwhC@jrxZ7R<p}~#Czze
z_v_E+3_Z2pe#Lw8Y5q=*zT&OxvG#G_{^6W$?cLdTyubG<!5-IN1NvZdW7Zp<uRHLH
zWt(ct{khmA^P}d}Ig3yDm;PsUEGN!Yqwd@_QC>703zlsry@+0vTD*FhFXxL!#^z(f
zlG5PV^2zIRf9wRaWY%w#teEFZ8sn3hSIqP0Yx%C2=PTy<$>}uj%`*QrhZXZY=eDPt
zgg<aRf4J`Jb3hS;bC_rIRXFoi+v@x+IxJSoVJn(1|IFWxE>u%rdRA#)#Ob#)?|l69
zh<TruwX%6z`rq}jIDfuz>`{E(m(N?I(X)ukX1c$+03-6`ys~7TFHS!4Zx;E-a(#b3
z5$iSi^rwn><MUp<!1QREuhN+he`elVP9<hNonP3le*GL1@l-X7zFTf9cA<vzo@pfK
z;~4eKT>J-%l(mH#Rb`9)OFTUh>s{uk`RO+<{Mx@ANe?TWssfkJ&L?&=qwjM7A7?$s
zG6!&epzO$+ufoWx%U`Ci4mcNk%?G?+E%*L7{T$^=wwU9+>(A%t+^J~Q?M#*F!xVo!
zn5U{cRko3*@|<>e-8~C_<5e};x>O$z{LEM5%xktT_}2%PR%PA&*hiN5@#L(5(|UUH
z;kI`zPEnjJu&kAxto7_0W;R~n3fK;3)-Xf|nO>S=_2a)1Z)yB3e{ueD-=gdztAE~t
z?(gaBvVW<5YiF1JQ}siD?)<I#t>%;ZlbKxXAFDs~%m;gatX|j4{S0IuS^Z3gx_=K=
z(%fkG4glG+-ZVF!NdIJUiZ@e|^Q%e@p<lMhg*mhT&X(l<nC~7+7PI(Sn$WuQhw^oI
zEO6MnS4D1r%v;@&YZp|0w!G?0+=Ym{^{*GLq>`+kXA^lU=Cl1w%j|g5v$yT6$T~)p
z4Raa#y<}(RcUI@O3tm0P)_RJRvr5cd`#&rVdFy9oAR^<|NrNGA^IO#$ohkt<$odOk
z>+961#3kR+i0{l?{)UAL(kkKXF6Kn`m7nSUfu0uPa9;^bh*MATsatz@e{<1Naz@Fs
zA6FpYvw1Rq%nHZm=g--x8OJnVDiY=Xg<12bZVHaGr%B2t6xLGBm*bm%?(7zyYs_+=
z6nU<6oK@~$24QC_%hNmhu~D7tUu0O;$`)udli+$O)A`Dr-J$CZBAhF0tNQbY*{jTJ
zxabw9(odD>Uk#O0ReN#}Sr2&53!f?qAxs_{uIuzI8Oj;-J@*zRd81xd4LQib@3TW*
z@Sp#mURo*}de+dZ7fR*DIwx@vn>lD_wPy>r#w)(_4GWotrzoQCM7{0{LG~o3WZ~KS
ztodblT4;5(@^X50eKp(LnGffGKdZmLy+->o+o~8BqE4&u<XDiPQpt%6TYbf5yH$Br
zXRDkoLtos?&-}syZZT+{<xC&n=B~Kze*USx+Go4<wV#-U9>>+KIl|1>etV9T{%F-_
zS(oG(T7PQa{mgf6=zE&wHYWwjs8o!cFZ`N?Am+=l__Rf6<D6{^S9-<wU(lXESAyTL
zQ1|j0DsR3uzn$xvGs}*x>YZ;SZu`mNLezzs8u5IjB^wJTA#Scv`Gak9C1vp_5zq5`
z11gPWdC7II@bpK{@6MH$#Z!x|5RnlwXVDn$=L&<zZ<tsLG8a5}kGlzI?g8HwHs{g6
zVAz~q=hUO(n)?<B&Fxs|ZwUDU;w<f8XE`{Rp=xt=<k{CPpl+#95@59z9G(x9QyZ__
zxqt$qKFe2Cy5JP3%uIf9F3NlHRU@AnvQ%LfPTl1(r>>8@ej(2&6C>&**x&QW)y%h^
zJXQ6qcXZdws>x)EO!KkulB)_@SYXT|Y~G}SHLT87VrX21ef;#;`HQWco_i^kGf(|R
z*MF;5yz3-MbYo6C-uGrP<mtmKv3(HTga75FE9YTP9q)bK=V4Ky^M(5HKfLi&dT37F
z&wE!tIS)_IHue6b<XhCIo*ATl^UBUMWykc?qOT-tE}mY+=}&{le{gp%X2f1k*3y?R
zTP3m-z6?BXc-L2%sq!urvMRaJj5$qJVVl_cv`)+sdMPuv|BN!2gPPA>gX&kvTd)tB
zz$|B4d_paWvgLbAqw+;IQ_iW(Xbaq+aMNGm9oUL|%vwv1ed;Gk)n<fqmoSa7z>TK!
znSnw?Y8?%ZdiYm$y{wVA#vkhOf&yn%j8;?qvg)Cj1zC&xnSFzwv}t#_oOtGwyiJ+b
zTP3H?dm=`I?453s50-p%nn<NN>Q%oJ)cffqTmHl(k?aSdg-oyepZr-!>SVM;eXr_%
zqEGU@$6nQYTCc2@4l>cCK~kr}H~wEV1C2d0v+*M;3pN&6$i@NwDw=ZrAvyJ!ZKU7X
z$rju>zP!>Cs?&SiUm^D-s@ll5b=$`C)&6`1;H0fVdBijO?~FS2$WS34bl{S8uSnZ8
zQf92?3>qekrc5Tq)SlaTdI62T4V9T2|Huj!RL}$=BPvVn{nogNTEvE2#<p-;hLaCH
z?J)CWpJ&X|1iDWqopmEQ%JL`k<gz?u5*+#2S5m|LIq3j`N4BgF+3&O3wUq?N4_~7C
zOnDw&YU<daW+m@u%KXVhTj#UCOkGHy$qLQ#TlMLGCKmjjjYPVT56|zvvOQSpDUw;L
zBT5zIB5oMe06|d;vjm8z#mXc9j$M>9rp)QNEm7nSRMRPPPtT+$GA6F`K&{v|Dbn77
zm$qj_o*5GDtou?%_6N;}ZgT8%#*EVnNM;jPV_CWXb?2iyj4uT>M?ft7z=VeW`{EoE
zfKww$NSKWmtgk9T8S1~}%WgNV`z3D=WLUb@;WLBWko+fct0DG0k5xCJhO@%SoW4{3
z+TUH^T;EOk?+k{=$^fP#%{@&_%?%}ts@cx>Rv%2=P4RTu=}ebX?cd8Osg}cS<?29i
zGz^QEZuaLsGB8!X_M(GnmEt?g)kdl622bAg@;V}9Cz>^JF@4Vp5;@8sA1caJ&yEhj
zOm+0^Kt=Y4x*qtwm)Ra#ZF_c3#RSx;?6zuaX!q)$)#g?<c@JD1=h@$QWl-9FBix&F
z^iNjL$P>gaezKk@;<O-!s!Nvo%8}QepN~$@4IuukU<t~IvfRkKBj(JOzej<j>1{t?
z6~cCiw>f9yy=^a3(ug40W@Gp%(LAzafj_d0{L*q}2Iyw4z!;E~9kV~)z}TglxeGft
z9&?dOHG>x15}-m^Dl-$mD*;?w{f;xK+I=nGrXvloCZ!LvIUs?X#nOqJ))($7F^Llt
z(ENQ!!b2&O)|xZ@y@2PlwZS<A<=$%G&6793V#Uo_ikmZ^@CC-2*IZ^3&tA#;?W^aW
z^|O_mFOHpn1Ti#@FHM!H6Mmnu5N3V}zJaQ;YgW&qIkRdnvk1%ge=4gDDLk{T(~4-~
z5Rthkv&?Y1%zPmn`EhI4Vv|w8meKFC$fP}LQL6+kt@h@uU!s!4nQJzYIc|3gQ|+Gf
z5)|UIa-WJAEb8C5)3E;>tm2^PIL$_DaHQC1jt3P|n}cp+(5;Z|?>^<EUU~Ib+Qq@}
zJ>fNn@2MY(nlov6vaqMQp|v+&^OA$9neiH%US5yON1IQzi+jq^$l~**-q3TbaD@48
z9`GK&4+4*<;aflZic0)ZZ||ongWWgmyz1C%TiutvExhKc@tJg8Y|NTBq?I^qZ9ja^
zQ2dp<KYO2#QS;Z$R$TnSqtSS?8*jbvZL8OgU+0^4@v_!qtwV8`9{kGCE$J2I$5SWX
z>FwQgZMX1)e;FQo?W3*khOOndMb{L`?fLs)gt@zUeRtDOnJ4bv-gUpQ-+RlU`zF6q
zF8tu3==Iyuef2}D2fvw?H%7gh*Nm6Qd*Qwt-t8VdaC!LyWG-C&kp-0hsS#Z8P7@-t
zekJU7LJW3g4I?syG&O;1Bzh7uJVJkMW)5o(N!}!JJwdk4WJE0b+M*Y+5A+qy+?66e
zsyZb*t(djGXEe7Aez!ZwN@CBOto2iagyY(3dXOVcvEy)wp(HS&_5Dsx8RZd0_?Tm0
zmhH%$`PSoseE8HcsT0tH!O{dBlR@VMU~w#MRBb$G@UU-EXrQHzJY%)t7!o_$rqd(#
zS#M79Ob_?OJo=u<@`Gj=nf7oYo{27}H*Bq8lBR>L(j+~x(>t4_q!2W7DX%X05w>Eo
z*C!r*hjo~RgV;Aoqs{ybL#qZw7d{a@^t~xBaz6iYJ1VJxfm@6-p-yL^XA7$#&q*~H
zLK@Y8rT&!4qIKJ*Ef%N(@{Ku94Ckr^Fwq8+T{6W-dlZCy{HO*lbt@U{17`UYYf}be
zRm#1V$%6OAzj;;QI&e6vh%Ah>4=V^+ODaXsWw6^ol*ljk+HjGsq2mOZyHCrii7@k?
zud6&AOSyCoiHRnYStaM?Rc*GB<~s+GRyh%;5^bZ(E_tw5?!0He@v0Q3dJoHjodY%@
z)4RPqYKH=u{ZIY2^r<THTwKYb<^xj*3YF;2A9~eLDOIq&faEmjwX6CQ01BhROf3qD
zJtW(X@$2+J1*!wl2&O~$6&C*S2Gwy;vkI~1UVu~1E?XF?HBmDcTWuhd{0e}6dQ_;!
z?3PH9h>v2X@rlp<fF*FRKY?f)rm7n61ysVRCwtFeqzu0rvd!c<;RiWw=D<$bSgl>X
zv7nimk6vOd1!|9QY6MR1ZP}^aH)1wl->;+)44VhvTZ9LbR5i$NUq<9C!Sg3H<Dnw^
zIg8D<46$|)RmIHomjftMMlHt*_Olhbfi3*ju-RbqaK{|Zx!Oy~%J&}PBx)YN>eCrp
zvba<1JXwI7x`hu_+Z=(>vPhigB?adf<6xf;i4%?3<r27XKyOYkd_A5bJ6T0S1p~u>
zBG7D&Ql{Q|1JTQq<;7n|OIn>?jrNDtC~{x(<mU(ciE_zcYo|EQt;7DrAvBN4dm*8g
zG-xat<k;ZphvhCx%|Yn~AtL~Lsn{+Qy}qe&(WA*D!jSSPDU2F(V&ncPu!Wi*G@e2X
zxBDf3hcVR8j~y0U0j!`cf_3e1)#y3iIReQ|H7u9TaMd+=5dqPu5@Z?;-FS4m{6P7{
ztN*k0AD!*3Qgw6p!uVMEL4QN3dfcyaTK_kF*ZKTKW)pp69&9fKo4XS(**MU@E8bqJ
z-_a_q8Naa`JeY3oZi<hZ&D{rl>&EZ$S=0je!!d6B+q+Zc+0Ops`(-Z%2qJ(-f(WYa
zp4dxA_g`6cqdOlv50`%XfpXSr!!K308WSA%{q3cy+Hx*tAW}J-zzucE>Q)1hkjL?N
zTE6UN06a4RFSBTQx3EVUv%tM|Q~AY;MCxc^Dk9g^@Ut7KQywa~gxK?-zqyMuOzRCi
z^t8Wiho-legnE>MC%bO&pl_Y!86?UvhT^3j-SVsZ8ixe?h;J%!cwk-RMzKE?J^h#9
z0F-u+fNIwBRJ2LR7z>K2L0>J}AI9RwE*Z9$d>A4rxZN+YY>Fqgw-TAYkkODuCQ;OI
zpS@NYuJ784oE?TPJ76l>DL&bphCgeLtQIA(t0r~PLyIw>O8R@py_!JURU7cp{<5=v
z*o}VS%_1eGBP{b}j0r|k7DP|EsEn9tdFox?4MN(bt{p6{Vlz?91^ju{(jSOnT7q~)
z{J+wf`LEa59!mFOx2P0V?#5Q)Hs>JHtUgigAcDM^Mm+=1h@&~~L<Yrz(;8EEqyRL}
z7!^&#sVHzqPrPk-i{VlFxDr$8jomd&4b}1mTT|WsegaE?dRyiO+sA!P2G4ooaA^ze
z*&ZH5TA7iips}2LN40uL9D{cNN4LCk$S)xgS|ZcBX|_sUYSxS(JA3>ulm?Lo{USAJ
z_$?*ZTl<>C_~r{GZ>WXbIBCb-<6|3M?3+q0HGy&0jL?x&K!HFCOcfE79AbJq)yI4%
z@`5`a%{N>JTPC8&oI9?8rC2bDMn)`}E3Z_V-JacI(DyUPKD6>$MBiH;bG;UUNrI8C
zX##)qB?>0z0S(8BWLOUPuR+k-WXB@Uk&R3*-O=@}>rSPeyvvs9Y^_BQSicdB$QeJG
zVV0Y0<8$UGelp3<Ct}GXL_W%S(z-3QhPbkX%frBjf-=yzz5X6tvDBbShq{N5PvpYy
zgi@E-16dzMfn+IrlE-AGL*E}uTxZpZuRWewB&w5jbHar?EKiOhRUJsRY9CUEsCb;+
zrmn$UAZJ!zUbkJVBg)iCgG*2#YemcY%r9T7WrqTC^JG5CCD7b-QX(hug--Gdf6O-O
zO|D~&qQ#+-2kB=RQ8bf<#I*4Uv3bH{58*AP2emO^JXT}l)myQ3A;C^2v4dzy{g(lb
z1MV@&hDyO!Vkh8ku+ES17wi5lCLKZzh#rBkcn$Q4avtp95@2Z<Hy8+p_j@sR!;y(n
znv{zoMw_Di9&B~jsSBymCInUyqk%sehKwD9MgJyOl{#{DJbyBD>wav)Pz+7+>a@z?
z9^&!X?Q0Bf9+E<}kn9&lQz0F%7UJk{{|G<oactarj45q5S`y<<gokKe9w?@c*Kyfl
zUF#pDd6Ncc^`X`+X0n0PJGhT-AwQmhUlV4pKXi*Rs7D7vk>~=A(CI)A*h&x+C1E?F
z-&5gKSZ%B4z8^(jcuCM;HepdxZFj4YvwFzif=7-$2wDrnQiHxvWgIf>lXz=5m^eXL
z-iWDhhDwlbY$GPIYzW=4#0=0^FPIJ)lGqxDNM0NiWVAT7pfENz6~;sHiF6Z8kk!qE
z7JR@INaX+pL|IRSesJ$s3-Fo<jh%~rmv|e;sDGsMD`MD2$vY+-8_7jQYm{wru+2of
z|Ks^oMMqM3_8OCve6&lmvZ?8wyhV75Oj~$COPqX83Q<xMN5kmBp(=VnfqwOFl7i0u
zzVDODnK4bXK@A|ra+Wn&7-`u7De;;fkk6f=hJ<mVVB*G%xoS+b1i>nDBQAzG1ZtEy
z;>`T~=U6PtG5<K_z;OqJ9ucAzcE_}dEKNu4cGHZe9K3n4-_&EcF~mTbFjEN-M+;ye
zYB4Fqa4~Bf_aF)jfg308)4y^aRoF=ZtD(0SP--*-FBLP`ig7rcL7(+DcJW;I*g9Ek
z<;&<t^@>9-y&!^C5eXvW2obFuDWAuXcgnuMPllv^q_eC*kcoO6YdA7Ofo7PR_EKUs
zUS!~r->Q}Y4+qpKGT12OjiLck=v5=*#=(i^KU=QLyUs8qrkD|8C03Qp9%j8pB}K|0
z6>=p3gA5$?A^SN4)Gb<p{K$?nPk|K*Kc4xkuj`3HgAm+e3UWiBFh8g)<N#JlDi|3Q
zo0&AobK)A-HD#m(YK!WqUKi<oHKZi^H*??*MJj%|R3w$MvS8#mLve$NWaqnTVir-6
z4P+Bn9MfU$WKs6FIsvH&NXB5J$t5Jhi66M@0^7%+*KHb-{M)gVPGzK>j7b(oQZlI$
zYu%95+BWnsYlG#gM@$66uyr<lk{EcLib~5^svryP!6oXUTq>FKSg6vD2^%Oe1>_^8
z8xA?i4rhAYC6#&!6h!6lmg&21&XPnyKt(zMV=Nn(qJelttTT9v(O_Az0%w$FQOFwO
zMuH@-yFUa2qfg%da?cy8`9nUscxWG2Nv}7t&PP8AB0_6VY&Fz_Kg|#i#XQjZq#Lk)
zctoOpDN07;vyym*QXb0|KZ$`ZL78v}&pH@@o7Fa`sFqT^S~|*2G90pg$%h}E_EsPN
zx&NMo>--5SH%PJRXt9JY1aK&Z!M@*N^+*g07_y(DyJcP^ThaO@)VwkNL@3gRSOaia
z8Yp#O02*eN1gIwl(gOfymO(@mu#gN7NMl%1BQNqi)|Aj2i>mEt+WVoGY87WCN^weA
zlurB4Dhw}ZPC4rPe4b3gB70gU3QaKP7!X0Dmqmop{%JqRZZbT8AW4=SeobLU?9cx1
z39p{GKwHB&57*<LS2s^YLwjp!aCG|iR_W5syA3|9JuA!|$!x9TQ(N~4chqjqPnCC7
zccc$^{{Sbd58hKgoO<|D_{Ywqaq*~B;KRTP)atxm+xTkk<Zk_ys&W{*s`p+A3J_04
zHDLtNdCC4Oul0{Ke`A$5745vTejuuL-1R5^^lekU(*aL(UF*WbDeI3PW$1hyv?Fl4
z>f$ov1j5(}7st%tmg22L2ux&>;MnY84aEgy%mM=ixBGqxXU;maa0yYKViJz-kDT?)
zbR6+9-~b1A(&041{#B%`a-yrvE2O+Kj~hpMryv3P?N#w*JsPz<lkv)|vfQQTyJ(ly
z?-0y7<ddh$5aVB`DR@Dn^Z?KT^PzW&81NzDb~GB8ibe~`y&x0#Sx}>C9AuIEBR@DX
z{zrCB8+<_Z)nvfOZhD3wgOSj#C+`+Nl&LBju|?z|?vRhm)S_N=i{*|bL1Tmv(O=k4
z&#Saei$X|r3o)=}v@KrvK~$*3m;BUuU>ESy!7Jw&LK?U*V{;dBv_w<xhyf6h7hQFU
zlwfRDM((xWjl^g$EY4w}mA$yWlwwv{Ok^~&%m`hG8MD+)MI<{(#1g523Bc)ayr(|`
zoi1LyPYbeTIX5il*^wvhJm539Mr;r_Boh(`rf;g8<N#z4vxdl^ATUE90=INIB1Oy>
z|J#_3tj*38@I!R<|H<-TaR^i*jc(@Ti%@Ab36a~sVK6rUe^`KM@^+uvH4=x&;Dau}
z{O!-^mv9{X5fuxhPf#V)IvU-J9E=uVzfRz+g9JfS>v<d?<Nj5M`;WeHi-Aa4g%)pM
z-;E{0+cimKs*Y)TXF!6powV(x+x({v(;UODF@a>2<XL`rVviV%HcO-J{c3uEu2-0U
zQ>&ayx2gM^4lp}{W=S*c$>S{3n77hY*LUmFVG0pCz2F~YDW?}&DCkBd#<DYenhC(@
zAyO2Jk;!5@Ng7MCtCrcfWJ*Sl`iv*2yfbPFd^2Q<yEUsBfzF{cW;~+mF@vGxCnx^H
zI2{jMDs=%X80Nu!O$HQvAz_umkmxYK#Fg40u!>nzr22y_$|wubFzHIOR$^4C+NZn{
z6=?~~PJ86Y3)@Xmij`SE{)=W2D8zrhrSDV7-}!88zs_*eB;PUU{}%FF&ioegN3#zq
zZ+vy-><=na%T9e!`J1}VR?TPhS!R9h;o9f(UFP5HRdV{ro&V_<=lQtvET_MB|LY=5
z6dz@?C7RvLS2q(0MO&REYlVeehEvZ#vLd5$%B<ha*(?O@0$D4&U(@$4VlRoy$f?^o
z?=thJKly?G@=BZqto}ik08Ct5HOvC(1cThj?t?N65bSu2tfA5nR%z_k;|9)!3!b0g
zzB@@-mV~?qG!0&(tfeF@sI%?qFhIs7^=u>Pe6sH$)a-{u`@K~s-gq}k1}p+OO^wr8
zr)3GZ5l0X4We<YiM!V4XnV2QG`Z$6zY1gt{>`mg*($+c%#hRxXN}x4pou=7{#t1=;
z*dB<9ejH5WYX<G%6Mz5fmiZ~(Ds2alZ%<pwHl+r9B|J<zZ=BHKqPFNIsZ^7ua``ZL
zVw*S6;AjHIY~2P?n|3i|@n})YGk^DMs!kimuo$1KYeIv+Iavk_AfvWxz#?wpXtyjw
zrt4r$JIt~|+1>HBm^cBUG^tK02E&C2r;q-jc!#<Janf#&VQFFQV9Uzf3Wo<GKML+;
z!zK(n?##QZiF;cGMl#D?f3nB`3NMk%&Z<D)jVlla1;XBHh+{}2VW>@;y&6W3$-XC+
zF7my>ct12GVK^Onv>Of&x9w0P#R0rd=_WU9Kt*LO3{G_C+ln3vp5EX}r~b}L-N&3|
zt!2^2g9D9#Z!iM07w@_O9K$XV7N$U=Nn^@jE0|CG54VA&Y-z{o#F#4UijGk;Z16s#
zj=49K$2)4Kp%$>9)}i0xQ7uXUGNwZYWJ8Duj(KB#@X$ZLOs*Sy_ce>9!FZfX5RnqN
z2t7geP=E+@isO{h_Fg{#?GP&FV*+Cxhx*rE=Xa2!bW7X!Cqi=L?k9(08NEn_chNe`
z;A(qV&1>=kT$y!D36C{%6fT9v?DvA<Hd^+C*9{N=hP{N1E8zpN!BvJe$S{(^k^(6*
zRuBNt2z<0uXJ_k0W?qVfkP)q{NtIxIPy(4kk>Iy5Cy)z-DyB5D7{|_?5ot6<{S*d}
zaae4j%U~y|ZgOMYa|Q#^OkBo-%Djj(c?B|d+)jhtJjW16t27R)FbM+}F{w%3oe1_N
z>LWgY9~^)0b;yt<n^uA0Rh!1fhScgk!wM9kMVRu$l1UR;4Fon{U>dG7RvU{FD2A0Z
zPp8zYz?};D#o3#Wee=962Jp**FzhvE^-CO?s$@t0EI;fa5mf_6IJE(XgwP~71M*ms
zLO{E6q4}Zt0+USnV4TL#^=|s^c|)-@lI=Z{j*4hh6E&4Wv?BmFY0}105tSxe+sq_W
zZ_ymn0+p1YA!NPAQz1o^MS3KN29g1|SvM!Hy-Lm?GlVgkWEoDGU4t#*CMXZa324!A
zkX&c7;WHlS8i|JIY-x`nOESm+t(qt>wL&NO9f)no0C%WBCkDrf02)IYj7N>@T=rIm
zo;<jjvVetgS&vrh5dtTXk@A8OPPzpx@4`3^^dRmr$b>;>z&cbeZMCB|-~%0^VK0b`
zT>^Lz1xfqFAAec!mMXHRS}Zc-q4g$!7aiIXf<kxIBoX2*9A!4zQKJwE8X-rW)YbMV
zP~A~fND9t%-~UQ_;3CT4kIZytv)~n*dD2BRRHcACs(_9ZA&%p<AdYCG_#kB4fO^$n
z*m_+xkr+4N3=l&_I?SHA?_s&Rv_hT?r_&M%-n>?%Grd$hqA-av)%r!)Vu+*R4hv1<
zMg$@mJXAW_sRtRLDW~R0Fc8GTC1bB_YgbS#W|=~bW{|yVWAdmrUv1Gnniz~5s4O@F
z1@%}H)>ca2$n0y_`4@!4$TwPpWgEf22;|6jb{~2PWh5`~URB%rs1g$ZixoWsbx9f9
zoq@J90@$KnTFv@j0FFSr1OrqG_hJiKM+^>)QK!06;7FJgBQZSt-Y@_3loYP-0e0*|
zdp5L@!Q$()@m2>_fUAg@)I5lT)<wW;I}3*J{I!uMLn$>KyTrLW!;aVLZfnO^eZxG2
zG?s5Mfte2d>i#f_t4Kst@T1WX^dqjt=n$3)<}|BCR2U6IFcFfda14lX6n)}9a^cH;
z4~}Dj7_U>V(Na2LSe6b7TsPPz9acu*kFt<=h7@3gnRytS8$a6@kAP^*Sj_1PZ95KX
zRckjfjgZ8k6SX^V$sdcfR&%5*Y~L#_!#v@s)4n&XLHKCc9v-N@rZWIN-pnP2QxKVd
zOas<g6;gtiE3-ZSkA$Df)Q_a-NS%K0)8f?-w;GgWTiZrrF$e_dT`V3l6-GUvBpwYp
z7IDV^^`ZOf@al_SYQY6Odk+^*oB28_aon%r|L@K*6FIhDoZu)#NiH}Z;BG_4z-}t<
zHk(a!G0;GE974#+uYwzRpPSeYazYmmL_3GQ^tRg1`=uFl{ra)m-e~AJQsfOqBM*(O
zcH`=m>B0N7(`*1w)(=>BaBRKDdlu8{@C*MU4DX9B{TUp`9)u#qVCQhPaUfbRPx5^i
zIq4qxo!g&ciwajak*j_?Dpm*yx0cRbY@Zw`rvNFO;V`>=K?=C5kWc5hn<|^+c1&iE
z3Pz*Q-O|~?nT(i23&T4)&{|@)#OvGqXO=+=|EI1b5kv(z1K4AfLjbxW0Q<)<4(=@{
z`^OybiZ8vq>fVOruwV&6X_P$u3IJ(<E##+)jH;^xCi0@QJoZdR0>B_-f$L`dqQj$@
zL+ni}pEt3p<WG`d+-Q`;2kTi71RIot{Z~4|IDE(feyYOYfka+4@Q++g@DBJEoTwg{
zDz~LgQ)3YVfF*m#rpGl7S_E?K)hCu$IsCZOfDc|rEE6UKPq7Kj=>9QAWb#A8Txz>&
zXrmOOVraEQ>EuF8i-~pvbdRnA>3|fm43gr}flB<yGq3WU3C@=|P(z=EmxvO){Y)+$
z22M!AL2b@dLF>_C855bTFcIdo-6y(V>M}mgt{P|~vB*-JE*Hd_(FoqKFc;{)mJk6U
z5xe~R*X68{?1^Vr{KHE<)?*sGjlDk@A;bZS0d=HNtGGz^c#iNS0+E_LqnKmW8@f)X
z5SS+F0>wMJf0+6)695@l17JubEQ}P;4y}!-b4Euv$mks#E|AA?eb-PWm<bYMbvK3s
zSO@xF2(37vZBNJ3DIn->GibZ@D^908MDszPOo--~jJa5yp&*(&Leo2=;46^Zh8=?c
zW<Ky+c8^0#MWx0{x35X^rfkQ>F6Kie&=-(1PDTiH+BL~Nhh2tB;Dw&E6F6yjpi+Gg
z<G~9a_pQRmIhZoXr^1xh6Z%;<wA2QP;6RB$n52->*vuEc2#CSvH%kaEVau$-SMm2W
zIjQ34*aikdijuZqhEs1DR{C^LQ?@53ClvjdpX?9WQ^fA3{b81Kcg@F%h}As34^z3;
zHITuuZa{lDzm6_saoE(|UuHx|hdY=2*h_eyo{`p~Y+v#RPjM_{BTWn6ku}z-N-RRn
znpCU*E=EGIN$MPFmrHSKNM*#<oJZ`zER7Y}s$xM`QoE$_0tzj{?a;0KtH&1swtRf(
z#r`EsdFWe=gdK+s=gLkslehu%M<$;&JU#F>Tryc23=y(LPKP1H2jQQjooIWJIOc(E
zmO|x=*Yu$-CQmwfH75(umW&@;9<iP)eEp}A5|SXnP0H)BFGMN!gJZOBpXvb*7zdE3
z)J&8QYhx%OHeqWEK*sSWn{pbl1Tn=i$Q_nQ8!&lsQ$&LwYfFX|CbZB?CxjR55@ErQ
zhU>x)egvjqvT}m99J7gnzZr0B00{@M2!z?lfCh!o=d;<AqIEOi^D4)_*tuMq7L5cu
z)kQpDH}i(n-8kSu?k7e+sd93Hfh)fFQk=>b-c7gBDrjKDV2nY-q)BL(&EXcF6g{$o
zh{LE80~%D!UqkdD79#r=0Xl-?ATEjll!AXWO>L;nz~EJDB!TLy1q{*P#0M`DVHo4+
z1Us<o4C?R<y`Ycum?V5*3?rzSfImP`Y|*(XhGXZb!Pk#gmul2G2~Z?+lpe=pwY6~y
zx3yy6STiW31oA;bmQhS!d@S0$|BZTUBW03f^>+ag2HDM{*Mb*xL;&;O;!5B{z#T->
z1NPsL$iXfP0zMG$oQ}oLLCbErVuM|}{%9Nkg>{;O;jl6a$uyV@Dvfepbz9lFpBu8`
zOm{S(U91OeZsVo&!5IR1GGWLM;s(CqGW0Hnq_ii_KhhtBp9aVaK~gZ2kveb?au4`>
zKsYc^IXE}qn4KZC?!}3n@Jg5a?BF@8OJGk4Mr}A9`oT0CfsS7ra{XuD4mE3mZa}dN
zE^w!TH?kM2-*3f-fPsK|AP!l_oyGJP9ULr1*K@#RlJPjma84Y;7<ZBl?eI~ove?_l
zs}(|Bn9M_^F@K^B#1bN#)ySP3h&rs2qbA&Hv=JVU$p!Ihy2t3hH%z9Hia-5fgvK5Z
z15gB(awJ|zgG3T3(Trk3N#M1128}ozK-%yEY?;hE7JP=yKq(2jiZKP@jX?K={Y~PW
zFTRTkNg9mhPNu94a-lWh<hW~0kPo02zYCLmtR|W)mueA(CQTuw447LR$>Ugzaq$Zy
zuTz)`@vkM2To``%EGWYx3xY7S^UJgcyH!}Tm!%N^S`AQ(Jl{lJqFK_IS9K8>ssjiH
zaVe7ySC`%@E;ddqy%~WqkORaGBT5KH8eQ>~mr)zXjk*xc)KE7K|5>vzS(V?2s|Yw+
zRy|N)rZB%I%)pj5`Qb!DJXDTBW7331y^i6ebQDHF8B7eqb^%^J@%~}}@{4A4*lwYT
zRGks@f^7^YtGyKqRtz2Xh3eKz2tTFOJ#}>pode>PI*O&9jG_TNB8CP6FhZau&?vF1
z;#OvU^5FyuP&XMgW#KVZB~>Jib5N|+@Q1jBEH9#)5VRZJcEKP^s#PFdP~dnPmL7q@
z7UIJlzXH&iCx-a?k=0KL?WzU@g6f5aNxZn&cN#dkAsCCm*n`MLI&K1gv!E#(mJftH
zNxJ}iVNXa!swF!1^pC$%!T>(0Q?2N24iLaY6;A_TU-U7~H!4NS$E9NU2rZzttOH#)
zuE%Xn3}ALA<0n&FJ-|S9qZl@6J(0%4Zelwwyy+;L1gTaB=ugyh3vEj5DUYgW1#naJ
zzD-8nZP((7CIiU<1k@2SJs2bRR1VJwfCv#)*><%)bBIe_ylIT{1&or`2(W7CV}1&0
zRG?yUQC2?_oIoEKsCw)%;(-Z8m;@X?+OcFjfm1N>xe@7t1rfZD{lR(E&;lig6pfBS
zB(T*{KqxUrfx{ehzyg?=Hb)qQI*FCC<g=4bk{ryxM0y1Dk%Dk0&~8D{X8Az9ft&i3
zpE@65hA!I$`wIdI$PHs4j-l5fK+6^RA{Kx$-GQ=XI<z$4L;%`4k%`j4M6CP3w*ivP
zGR4_G+QgWTE}1T{>@qb$#Xx+ulVZT#5LecWi8AXfFE34oZk>~az%9(L6htHxvJF_y
zNtP0eC?x58$fUU&Am?zrGptRtSx9x}FB+W=m9C5LT@J?LafXV8qSNepwc6$W1ojB0
ztp><Yv$n5421~1`7N2t}H?Iqj$HO}8A-jSDE8Y<9d8*@MEG1x&dx2rl*bt<1kOmBC
zFJKtUipvUuib>I}^b4it`KxbfUmQ<-+7~p*(qh;haVNt@d?<E0t77vW)7c;50U#In
ze_mv;Ev7@TO|Vf``vGq%1g#&2dFC%xy}Zf+i|o7!KJZB>#_nUA)A5+TlPxEKn;e{B
zk34jbU|dXv!erjlv1O;|Ww*W6nEVFLcquuNliC<X%Itnvs749d|1n*wATy6#dcH5T
z0%Qg~H(k~%C%bCaC$3(@NfvuJ<M=Q6Dc`-zKn%eQ&wyiRI71&QvwK>{RBV9<IY)}1
zZ!g);O6=~O@NtoMw+mD20B}q+^kf$pXB{V2Mj!I{Zr=J&-{W3>A3%jroGay6O}b-g
zIyLsjS{cx%IuIQRL%^AB0z<C7=tz@eE$-+;eg~+cs;%~$4i!;<JN2rI558~`aM8;O
z_WX)Y>TEAP0l*=2<{(g5!1TV&;tqJ=PjubnD0$%|{wLT2XjNQ;C!@zOdt*)*WM~Co
zmUV?KAOyYg?Wdw$H9T%`wXv8J0c_}5KcAg=yyf-#foHDNVUR<-5%cs103R%<g#pWi
z7P1jwE7-FmV3~qy@b!0}Jo0grL=mmyxxfNWRS*rM#6&;R`5DgMM9!GtitOE*2na$o
zKsIgLw}3|PsC~wFvE8P|cCOP27B*G|7>R6P35(o7DLkKfQ!NNfDexAW0$>EdN}xWX
z!JdJIf6yIOjsv3NEovY>kqWb{oN7IOAnu4`g(-9(3wq?nf-dMi4KuVNZhZr1HU&<!
zOr|R|j^5KrhnNkicA@gb|9!qhObeBYmFP2A14so70JE{(Rg`KIJ%Wxpf{J*ZNr#CX
z%P<SO!3n`iQ^QvJZs<;}T5k``Os%4pZY02N^o}0>6oaei$cQspa4xRVn%WksBT?J0
zS|pfYI5EgpaK|6MQX?sk-ePO${1oCiHN*lT3`^1|^agDL1~FB}2Xi%h6CK%s@=@WB
z&C+^HC#XjZ6XUj}=u6%5fe5||g&X}+7Zzd6$2(W?K1??nhD{6{Vzyprn<Mh#n|8j`
zcXpVn3p22l1n4=4mh?O8h(M+7Le?-b1FSfKkQTOQcu{o|h<co|EK0<ks@|#b1^lh!
z7nM@U?sl^j?*g3=`YL#eRWg$^ph?#AsddiiiLXAQBQY$B+gbDKhP4tnMt}rH7e5q%
z1E3@<oLM{)q7o?!Pf}2UQNe&~io)S;=z@Q!eZB*Lfhpa=D!8LvpAI={1k3`1L6AUu
z0D2tfvWMWY&W7#scbEX|qXrcoa1y4&&{OzBj1!0c$iQ&;X{ENa%;E(d4BJ8OWIx4-
zX$=*+Go%sRWY1i>%`w67p)_VZ*U?HMVFE%#=$t*<pnyX!*b(gwB|8Y;|5WdfhzsPw
zV9;42qyBG&DWcNiOm!2v#PG%*Q%$sC<dAwf^gk*awPiMxraWLMB1bt0lVWwoELs*<
z7Zg=Dh`^}3rwQAl0zeaUZHq?f>A!s0zmyM-e6tbTzY)ISqrE>{a_vV)RzJfZVfoC%
zZ?S)b<-o&@1^<#u^Xxx;@=vb|w8M!RXWy%E@icm79}Gmj$xOmluy;J5(Fo!#fk^i3
zw8fg9`bWI-U~CBP6y9;?TUCurFl(N2?S;J3D33UG?X_?!;#3}Q$L}4K)n<Zbjg2pN
z0+lla%AeU#96?~$iy7~0%NI*iCJ#r06TH|-4j&xCilRr|Mr`Qo(BTmPjIKR=OHG(%
zI8w5R;)tU=RqRQug0Nr?*05}LhHL3lh#^S#^nyuyz^h@}ly`l*UW6X{$h5)z!b9L{
z)CaahIcbAa5DsJX3m9Ynjd(mb$5}n%3IZZNz<SlY1s=Ky0`V|(HU-xmQ*oQo-XVG`
z2q8I&ak{n{OsR|i4>39cxx%Ex=jS*^3XXzx=^9XyTTFmuj#)|`4k&O`0qAQhOROi$
z4d)-v9BWSoJ+PEv*OO5$0Ng|%EZB9cErW1TBaB{bcqmHok_RBxgazkg@4p~%gPZB3
zlm(`{(<$mWMBu_C{{{%Iw*aAVF1Iiq0aO4pu!T}!gC=bos>OuHvJ_a-<~EHd0XjHj
z&CBS`5~dnnQ8X!47Q-#9W!ai^IC0nhp{l+Bt~xD}8TX08R0Gc;v-e@HTGO!;gcD_l
z!#)+7l#N}yU1DnK9u!S9CYEk79W{i**a4v_;Sf%sb@i4K)kKU!#}vGo%ifH(GCRiY
zm~MobfC6j%wXHNMLJ=7DR728@bAwvfu`0HEL3<oCS*Usk!gO`36xFnp1G2Q@RozEx
zQ5w|_#)AjEq4=1=!Du&Q4jNP+jj;lvp?D0g2>Ro_@=#uf=XAn$=zi@-A&aB$@YS!i
zu*>NcXKLg(ryXtc;?{$q%Nv0&riBw`hEjYO9i5l+#EBsGXmKk*>{iEK>p(aWh9Qga
zRz|`z0q(AeC#OT^Rm9o`0}yWm>v2m3fR4g0t=9wI*l1`5qU(NNpL|T6<mNPG9;xSp
zH8q~<4IF-~PY0x>Q}N!O7}rhG&uFrmByHht8Z7ItOF__IPv(Q%Fl{k|#Rd!jd6*M3
zAA6X!Q%iViwfkVHnz|rcOk<UlWkyELK*M~Zw^S%U4tlt7qGl>&gs}VIsG%1ebaGg5
znN>J3cCMqd<akTUqJrli8GF_BDOEDPl#vNYM*?~F8f?N_iim$hL?M<;Twx;WbVT#W
zR-5*b<9c^Pi9=;L^+>Z|1wpw;7@LGl^n*<26SaF0*cfQXWRjN@{U%LHUejs?H{MnI
ziM|1#t^$T|axB8P$90cj2bFVXOjAXt0>#o)`{9oGAzE<x0k&`q?`*zGSOinwnJ7XC
zdAWe4QAvwOjzZLYuyQy<3{z~2Q6%;sb<3I85YZTYq)SXZcGbW|8(pv~a-f@dw#6$m
z7yS)%+yLq}exQP)0PoV#2pwleBQX9<NE|kpPi?)^Ob{Dc2yiWv9(S6LxKO3TqyQ9w
z19J0W6hlC_b>bp%X(ND}OrqmI`et!y!XV6gy+f_hwFDT1-k_8MLt~k)MLXzK5SA_W
z457$?Zp0QW&$<e0;I0b6Lfm1N6Idt~3nf7&oj<#eDJ~A`jc4VYd;<)`&_pFPeH0S|
zY>%~|YY`2UCt8*k)sJ*_d^d9J$1s>Wwis%@oLxi1Y@aAtl}m*LILZ#HsDK#f+0mDR
zmrxES-Z039Ib+0RS=Z9x$BbA<V}{bxqD&W@G3ik+iY1jyf&@9zaYuj)X@TC>0jo@~
zzlU>4J{kP`-}nkn+BeLWl;`YlQId|>(RZC@+GL8OY%~|^C8%c#qT8HE{1?NRDtB`@
z6vI~aiFW-O!YG7`jAvntD>pO0H!e976zW1An2=^0WjaMIPlDcQMU}!d9utiu0tmuM
zvoRxV;`B(HJ>Qi1%|F=TBDbZ)13P3oMlg%{0uh9<%2(ft)FFoarw1*v(>Z~sBARYX
zU1aH6f)h8G4tXQMF;F|f*i)Hk08|DgrbGOOSwW%3MUN2-N{&A^4Emp@@94V0hy8aP
zsJtUa!wQn#YML$9-h<$VEX4+`O)3xY4#A{<gC#+_tmGVKr;42(tJEIQpol%I?%na~
z1H7HZdroYT9E`!4wzccv{!z*XN;15S<8jQ%iRm!$O8)5HxY{m^@y2Pb8tJ&qaA-^z
znoi+0$A92zmZyEK&Q`<r?q_|j?*N)YbX$`T`svMV%<w|f4HFn6!N`YO)goep-Ly_d
z5gjq90kAp<^mz;Kzs84Z{#fuR5*~35Nq|(Rz*;leJnVy#4a5`ehvLxdZtHNUltpD{
z7!05@yq#<~xY$n9A#Q>W6(z&r0IOaShAtLW`}o&>H{d%RoLjN4G~ow!Q`jQEU}#^f
z37U0aT#!~ZJk)AJHE%xo7OYU@8UHQNb1Vah{8D_C%|N8xAI^^M;4ZRPZ2w12ZH(Q0
z?_>tx4Sm)m`@D(H?OgF4eDUkMyUp}CuR9zVf9G+%lmtQ)<7$uS5Y9L4(H8)s?S~(i
z1DWc8$;Omu&=U@FC{C|2anuK&n$M!B&_7t%V8e}k^n_%AK2fz1pQy!@iQ`F^E4b2-
zzNE7L?Qv)1A-<$iE{#6)OXY7gW6ajkyXA!K<P8{a;%-cjy?{hJd0lC21VCx*JiSll
zZaRQ(x_i~VWql3>|MYdcc?Aj&c6$7s<NN%n&7cJvQ;R6v2JmteyBf@4<A?y3sq&Gu
z$diZHZ2L4-7Q~@jy(ndmrGSXYU5$iW?CyXF+#4BZJx68eLc*TZ{s@Bj8eDcW%FCi-
zpo}cYI-6JBOCKU$M$t)$K%j&07~W19zVpJDiQyOfQ{!MsKhlNG^2Grb?E67b1cePu
z<c&p(5}~g28W-m!<mGc(1E@i#ap5VT1%9)jw*>z^+KuZCBr&>y-eUcZ9y5(@A<e!O
z6JLxCc7$9gRDC2St~vJ54EPDElam=b$ukvw?G0>YV*^i(zw@YR92mD>jG;lnV=fLi
z=W)X6@fjZ{9F?Q@XvH>!0JsfQhJJ4a<PbD<qE-We+Yiek;Xs?a@u=6MYnx#Ym0ygS
z9~@)%Q?PjoA2_|H*U9z+c%X<l>Y{I^gpKLwi=TM8%w3>_;Inibve0)r-xL-B*wT&n
z>HRyuIz6t<ZW8J`6`es#dhJ(80ZnpT=Z3BWf)@#Z0C!u@cl@HT!5I|f2JtKayR3f<
z(<4nHwpr;cV<xOm<Hr>)k=1uT_V$<REvb#;eyL?-*Eo)32615`^GH4*a`dZ3bIFQa
zB3vP`iZQmr{owG_Ahd;*28Sjd{g777L_&oz<N}iVXuhckMQvaP3n#D?6IU903R`97
zw|)rgf1khczH!57r3@CZkG=&{B!_y3fZ6Z<AknG<yS~Rl<3_RbKn-3@;`9|Pe;CCG
z8r2P9T6B|<;k;7JLwq?rW32I+L_DhxzhQIeJI`!kxtt!~__*(EEY?}LpeZUk`iP0v
zEeMyzVP8M$02b-9$GcMP7u8GHlL@u(4il(Y!~aZl7jmqlclr*EnTpbc=MLwv%BA%u
z;@DKc&w>b4WQy}&2N@b!!sxk~|Me5FJVU`axKXKkfJ#p2rLB!4;h{+<l{<h9&1iu5
zRKPDeV>5zUpsB<9>dojOAC=Es#24gSk51s}yD!9#@mUy598~uf3@i4t*<h&fC77<L
zfXC4xQ4tR@-hiurH4ZN@OnPU4(Cs<}W#J)YAw|v0u;!Co%u>)E5Hjf6#eA}-W$h6l
zipFDgvjME%-Ls9p#SzDl*wTtlqC+qf3JauacWqNQ0&C(RB}Ty`e^biAp&P$))x(Wr
z?Vq*Rzvz6k^}Y6oao_&xkqjL=^H21yf4BiUbl<J<b3=!=e+#3i^LVSNf0LENEsP+h
zDHdkS?$Ft-b2JE&i*I8SC8JnXJ!4H#j7NVU11^GM?*Fx7e*$CQ3(TARw*N{=8y{zp
znX%TF;p!iMnd7{v)!NtcCm&}=jt$wk;m1V|J|E(+&1>bOVGh=XY%t$ss4{^7jCeoC
z=(I!uH*#HtcVzGfj$$(CC3X%^9K<jga4=@dF&p|3kq7-ag<9-${LTSq4BHEXaWtF`
zhfMkQD>$q&SZV^P#2m3h*<obXyCZHBGzhDbZlsjP3Ff4dHV)+tYu2zm<T>NOA$a8P
z>3CIMSRy+vOyq)h^AWQUO@y}`n`SKzz*2A_P%F$-gqxRR+V0GctYM?JaY1TKGi8?Z
zt&#@)$KgV=IJjyh?WGMCP@t5S73@#8%YHXBg?LLOkE?!5+mK4v0(N)7BJk{3TJ%}~
zYl4P|9~=mMam4l-E>`>p-v273qSYP8uS!79QVyQ;x_z>@WsaB>HReOZoA$AA;cnS#
z<dM|UA#FKg&pWI6&Pt&=f<8p49E|Iwt2n>{l(5A(V=Rf_G=+3^DLLBS8>fCvo^))c
zLZ>FLUovsUg)bj>9^Vj-w<;s-zc!K3z-<CD$XyWtK}5Y<q{DRDj3urP<7{mQ1*cxb
z+;FkS@pH+I4PI~pkconaD;R@N(_`LfSSzE@xI05k_W?0`e>fS1kH+_Z={(14q?3=g
z9v`3JEJG*NL3XgXraJE>#mPzum+eirKnvp~?t#ylDr0OW7+V}>=gme?DU9SLu`OmT
zNIA{W^<WHhTKmuJZI<+<8ctqZ97mDiy{(Y9urNy||AGTMtdX5|ScuHejVI;DFACPR
z4z+NN1|RoL6XC6Qr@d>yqkInefDM6u0RMow;8?-`RtZ!P^oAG78f>0-%!9FeG4B)#
z9U5ZM0U2zT{2H$!?gYQ{Mz`Xwkfp}qeKWwucv?uB2SVW=QzIOz>bSMoA462zowgYc
zx3=SI^BbQmIh96I883~XDVkd3{4_X(=r=$#aNdzO$s){Ni>8-Tg^Yu+^5Iu}D^l=I
zC<(HI|4eF9h?+<<{+15aY-tA(`^-$l7%v^lpZe*S48B2!;FwVuT?QcngzerV1qJ_U
zN3bU_AWyil!qI3G0H&4#i|(m$U<9_?!!KYpOh)}U$-21C&b9yuma+jMxTpcNAv(ps
z?P<0#6E`S2W?aIS1_kLrp$*n`)R91m5>P_H5eSVuQkIT#z=k?weNAU{FR%<#oXqV8
zN(ykwW81#%-bhWT*x0GzZmx@+BR_Bf3uD7^8ZDwHi!Ew`LQYzN99bcw&%)uD1W=`;
zkhBo*L0_5GynTm}i_Z@hs;SJN@x}+=eV}@I+&ZwBH1YLdb&M}g%`+E%$GMw!pufA_
z1vbA0^-1kuNdcZZ-DQBRauE6rj?(2jCL!|(Ji`q-Ab53PP)tfBz7~VwX-2LU^LW7~
z26ClaQGuBd6o$HP#HAAd_BWuV<RmFamC&7tqNx^T$4h@`UNd+GgOO7tdU0zKJq4{>
z+LIApC9@>HochtH7!7m|7PJ2!@!Cj?9i<k)4}kFXdMT?7J*L6{*W-u(DR3Lko>u*W
zjvI`ZoGCsrmI@$Zm4KKAEVIp@Tzo(*9MDB0n$kUZYUn8~8Qh_{(OL&W^jVCI>t!NG
z)~m(@zL%nzZ(oE61aOr9?0a8G?dsRs7A}Ud5^tqQ16gKp5H-Ri<|tz`v8_GHwz6PH
zRaj$@0;NKmCI}8EDThtOSy4`kqg!GcNu#IV|FR8QfLIMuR1?htQM*88f)ss^DMbSy
zVJXx=hJ8bgT?!EuGgKIsc5`Ep+9NhaAcU?XfW#WFgsenN&eb|J#Bvc8?)=OJn3036
zV(^k?6S$msuf^QJ<dvZ->60muElt$KDuc<0$;{`Ix<c)?v_av>hDwN{7<G>c9Z{0;
zGcgzJ>tI-Dqc`&>H&7Qtb4{_uA+eFr&O~TqHKILDYknNVszW)ojI4O1(d-d}>V=;P
zf3pKlG8<)W3lEFXcQ_fGUw1hg61Y)xkWLD_{jHld72LFCE*`I!ZbW}$m2TaR%7|$>
zVI5FAn%|S5D>IgM1e_)tIODmc1C+}o3ncMtYlf3^B^oqZAXs{82rWI)IHG+*(4|}d
z{QxJV*7^UfculF3{$^`$Ya$K*(%e_^o1Gs3%#ZnI3nwDGfJfnU<3{Ig*fPNJ9N!BX
zw-}%#IKwy8Slu}!YTPOMS=bqx$#xiR>(n~O+FLtdI({_qp7u^JnjDKKwst12jK`v#
z?0I#@Y7-xdgHQX%+F|&iI9`2AXDsHZP3J+r&dR#Oi(e5(m^+~fqt3e6yS&VzJni|l
z=wpBE-pvOZwA*mF<?n2GJ1cuySS0KG8=Jw%R^*HQCr%t~-F_o$6Z>Gycj#cFg4cpW
z_y*-@YQQOW&GvDIgvEd2QNdu7+d8q?>D9ax3dWexJH6O+hKH}LO^nq5%+d*VC^+wn
z8kqE2pNT`M>(1V|Hs<SpFddGKb$E9;1|6IBM#~4-W;=0oYzmQH=eL^a_It)RZe;@{
z|J5l9cS4iMHJZ3@oHg`uTrCW&lVB4wD94`ILy;?TIXSAlBbJ{@(pMWuIsF$%SZZ_X
ztumcVvdNTI4QKqn=-5YIQQiDFV8ZT0$H&Lt`6Jz3{#(cSa_mHO&Gb5X`A6}X*Yc9n
z(X?1SJ_-Jm`rDsrwI1*VP3$&qu$dz4Z}NE@VITTRF0qb%Va%_VV;vtV?d}{iZoD&^
zbZ2U{-YaP)8a+0>HRZSw(zZYP{6*>IX%%>4{V+L)clp7S-ADPeoTD6Ms&G^)E?n#Z
zYK{FB?MBs4-^2TB-N*cN)GL8u4DT>g!+*PLrc!Yx_f~Mnx8Jzwy7Buq8?&+K(F=&g
z&wsF01OovC*xcPYp14!vyX@OzL@=QRGciYW8bVMCk@j#$FwFu3(L8U(A;u@?1*t1}
zWv0N%4~rVH3R^5Dxg!Rk8TRnsZ|HJt1bEEngo)s+VE=Fjh>C+syV?GYuYUUlZz?|E
zKUiU-yLF#EGKJ~najxEjUfT7|&T;UIBk+-<E@(uiK0dz%#%K##_-YVf7AOt82Bsq>
z#G-;Eosk$V7~YWL=uW!<E~c-<IJ<cJ6W~IJd}2P=${Tk;SRsWIb`3@&-hID=jkD1c
zpZI8SJGS+v&ExeOH(fj4BAehl`{q=GVejE&544K<?ylawg9$pYW<OdB`}9szqGuWf
z^WZr)0eDoGZ?zbySGtmYw1)-3OkD|3<e8~4i@t#s#+-?wSNhT`r%s^Oz4QGqxvt@E
zG1r#uuztZJB>)`^VvvoQnhO|B-eF_pIAg~76#d;;9b3}C(*(voO4m79LnB8V7E3uY
z9YhcL?i9PY=tNWmoL+zL7{t2~RmAH*?dv>}M0o;+I?;}fGjn(oRr%v01iXPI&)Jw3
zvybnpIiMOzRVs`SHe@V0!YZ8|4g&Be2P}!05uD}%m~%#>t&ElIE5wK@ogHo7<<j?c
z<Mm`7jR3~jq#ngN0e?!|_|;#ze%z6qn>US*05GA~4GRH_FUPZF^JZK?o(@_j1dKW>
z1&q;)Qer|>-JnjgB48~fE{k~V(0RvMPrEpRoDkX{>BJo3MmeK*BPl-fo8Nc+<8LZn
zKmMko&tD;Ffiu~!@#qyVPGdFe$UTzFfa_yA7T_te$O>J-P6C<SMT@pVz2XHQ*RY~;
zZU<j}f218eSQlO2<xEevaDDgEZ5{{Y0IDY8MoU%eJ3zPnrwfKQ73-UdyZpw6kxJ{9
z$}LVX!uNlR;OmFPqACNaqhPdDp<51rE?Cz3u1OYnV$u5iOb%3P7|z}U(FhdV&-cop
zp-kjpn#HNPv>CxwXa_KF!AYEJ=W|=dQ~SZ5sR{>Pr{5sutRqA$v-XHlYT!ZwuqFh6
zBS!B*xAVSO8tU6$;sdIhb9oU6BcSAfQD50KSTnNCB)v06R+%Tj1j(_sn}n-W2_&i!
z)@^l>vMK+)gW>LfQ_R68UtrU=_KwE;PX8#*Gdt$_C{FF+24DM0pXPezSALf8d7j_Q
zE7`nIB|Ed1;6~re7lJ=`)8s?3z7(wM(L>LCa6^tZ<!6zISpAGWizKwE2cGS|;h7!p
zrTnh#H^uv@?)|^>S-KE^a>Kh`KYH}gw>~(_VWfMvBL+ZA%~rF;O&#n;5g4YY2c#7H
zEsK-w#EfEt0U4KNr|A)3Njb8oVqNRU*Zf&P>}(;NEz-uRehf5>WChJz8v>WgzrHmo
zrF?D$sL6Cj^xdhot-&r^7#Ft!tZ%5>h`Y|-C`aC88)<tSi#x>f#l|R@F%P#mHr_35
zz9+dZ#y7#;=ePy?;783^4f{s#iA0_K7$#wXH-#z1j0G;hCwvS@iexOTEjqWo>cp@8
z0aDEJgqdYpoFKxC=dewBLv~yOZ&EMf<4EXLYUp6<fu}I}It9ZP9DAjq+wr<!8&U;0
zJLnSsh>0EpNhPCsRA*P@CxKPqZpC7KjQftkEPL|NvH<G%&#%;O^te6xl44qe6=Hq|
zA+{-v21Thb_EG|!pLo4Nl`%>#s<dqyu~&-r(6bC|8e?vQS%C7wb@bvCdw}|)PK;Yn
zihwPmpm{iUQnu;_OEZsr%W0(J4X1v~c&jyf^LRZPA1UfELj|XXLk@vFw%6jKqDl}Z
zcoDl07MN({CAhEC2`JZ=#yAUyX~-$Z1wm-)v@O2}1%%7Ype3Gt&7<Kw@qPU5$9SBI
z=s-gEi)0@x3{oI*uc?6gm1qYypyiC?R~G6d@m3;dqwKPP2#lle+10O?!a9J`!HN@;
zn^7AlW7J65V911RusHMC-*5)~dqx`G;5Wuian-{k#gUeO!-xsev`}eyP6$KsS2o;i
z)^6m}Pb1hUaih>&TXCvhT5!UV2@_3M>P7GR_LeqVMF%UGt~<iD{`gRduf<%SM$?19
zJkC&&l?54#M8r_LFu|5>dk_>+7$OLn_pw_`^&*~*v*$*P^rVP$*jcp~yuoih!C8j%
zEuaJlR8kS{+bC^tI{=U|e|Z7FA0uLqHy*>vk#xkHGUo9&o1w$F?IZ-Q0e5nbGz!j*
zYqm1eI&JXDdNFo3?X4ihNg+BC0rKPRHG;xd|DG90rWBGAcicJnV+;*Xj0WzD#y5eH
z6`pmTi`k!)3rz&AUPv0PqD}?jva;$nOK?co0AnU%Q4-i30obnp+ESHQeq86a-=-My
zlDvdT+@uX=2KZsb!FW;~Mp@9Xp&UjT$J$)OT7o>&C?d@)(rE@e|5!?hydmask_5u|
zTO>OK5iryJ1?Y7eR(J7cOQQrB0Y=>@Bv~$)PLSiTdBool+g?cPtmj?lkcY%%Nsg6R
znhao!vLT}=!N4o7F5UEZ=Sv?3<Avl6&9@XaqD)-}*P6kmfPT;{<B*ZKp`|KpGRKNB
z$@JbdoDo&1lU3A{e;sX;>x3{4CK)!@zILO-A2Lg*i9a1RVkZN=51HcR%R*`|0070P
z<+MP6L}yS4;TixERi#eUxUXIqp-RgQHl-LIjcL8oZJzkRBQ#N_i7>cl<G8^N!8)b?
zKm(0E8e6R#G_Q7i%}2^Nn;y-<=fU^}w5$_Kd>FWRe1wVFEY`_J%v;<+Ph&F#Ks@e8
zBiCJh9>b&>95oMA#7)ya_I^=lwxE2og!_N={J!c2-FQz(u92pO-O5RS8MUiHSC7PR
zW$i^liw=M?*tUO1q@wC0E?|4D5uswek!Dg@RalFF@Q36q{zz}j5uKnh$JtP#!@&E+
z!4Y~j7y>b<NE@(bLrKhG@-$Ed&h;i@_`D_^U(0MOFwM{c&p!6j!BRuBHXRJTP=ASa
zWMh#W52Pj9G5j4njl)GFH<Yo$`w|BWOjH#Fa4AO@h6TSKjqj(U8%o!9ok6dJj3M>L
zQKJ0Pk@u?F5fUM@<OENCt(ZzcH4S<^MoQKc>!k))av%zJ_?_#cV5DgIs;rt}1bPjd
z$L(LHPBdo}Mu_)OYQ<+yyoB9cs=zNW<x4!i9TGIQja=5?6B%pMTeX2BPZQUqip%fc
z9!^InkCAKchNWxM>kgOdkxu9{T1O4&uuXSHu6d|g1lo_UQ~A7pdPx0P^7U;am(qWV
z_o_z{uDfr5o@k|V2B)dJ)f+QOEM_vCb;{cyI-*`ig_RofD2tAei&=6LeKNP?eCGG>
z#5+I(x=yoBFC0fiIB%sgXNP`~klErkUVo;8{4F_UPL_X75xG!KF>H=#^AnN&`iPUr
zovD0(h%7jlHC1xcGbv^Dm0Jj>t@@K?{3_>(=$@vkwY<nYvi`(}#mJLI&#YIJ_7{Ej
z_VXkUmRr<)keXY_8EOYTep<9;Vo>SJd>XT)o|z(co=Q^fFgUmVFsea84FserP%$BZ
zOoapibdugf7Int&=+yJfGaH>oqt0K0lz}mY)#5qjRnZu_b;JoTYqlV~j?(5$&!Sbq
z6dkF<un?_PAIG`VUcQdM>fHw{wCf{u!&}Og3cAcmG4`Y+1CnAZ^5fL^#`~!RCP8q^
zQlj5m#+_F7WTUe9W-kLzeKhwn^u^44_21nVp4is7C~9sSzxkRw#=jDc6yH3VZut4h
z!|4Y7F~QIHysUb(+`gkcJ?wiIJsjP$;rpU1hVBWYk+-Ekeapyoo1S`(MY?mgQogkL
zgFo9N>)80=yRJF$czRj0d0X15rJw6=(m`<0n{sL@7l-lpmDh8``qJi_o1;swi7iz>
z|Lf=13+2_!x5mi-$JqNv$8lZxoj?ntaBNM2sxCGQ%_hkAx~kCtK~miiB?zM*s6rLk
zq(BpBwlG)*p^X-r(#+V$B*-}O#)(<zY7;cUp#agx^jcmCAn8@S&Wr&0>?mimJ8Gyg
zrY&e~K%70CUFD1bQ4?i$&&B|KHp<!AWIwNI@0>~YkL54P7TBm)@4kD#_j|whJ{JQB
znlTntC&DbEB7(JW=9)eEh(gy+fJp?{%)|Iw%l(2>|4F&k|Mzd<P1JvCxc`Bi;J^7x
zd(@P?`hPk0-$bnbnWDF^zwfHseB1SIO}}%CV(PS#;88SdNz7)lrj`nh>rcv4fm<}%
z`)?N?skJxt-Ejy0lP@-3(*FN{ZMp^GYfSI9SChq9`qvNfiu-W5uNJO!PY-MhR;C#E
z0FObV>ivg^u1Wa~S6;0@?<?+?|Nd{p&lq3ioib?YQ|<99`n>*K+4H`(scDZEGp)&|
zlDp*oWM{tX*}`+r%Tm5*56^!*a>S`EH?3?YjM&IDeRXK3rsp(9Bn(MQBsD!U?ia>O
z1=lVVOZiUWkE~R@!mZ23(Zr7_h=%dx`lL2>UH^s5>TTjRX-DKyt4}Ya{5-!xdt|^b
z)T);aARYwWVp>A8WqYn?l9P*aR(52i{eAhnSsupo`wLU!mBQ5WK;hPV#tL(+Snri!
zYvM}txC22|`AMc#?9_MYyS2QQ-KAT*l06&x<dzV-#NU@)`TqJtexo$<Q_u59a+ec+
zA$(6Yj)kpe?9NnuO*8sF{j~1tdFgq!o45Q2J$oeGP$}G68Oj|^9D^TI6kR-PUhcjm
z&7R4HtXRs*&Pe-)J7Lu<yT9Q2{knT%$}f0+VW4ui8qA^e3tPKs!{iE(XwRE+Cc9sz
z_saGq>u|C7y!5@ibeziYfIph6)C|97`aDypUm=&NDydn^QaZ7w-OFV7hn&c6>0Jl1
zTgl`;xmzx^9m@Ys@sRX~$Nm0XZgk2Yt+A+|IjgnJggL!he?zp^%uru8+h=q;Vl~(i
zVY9-beKHLFk!gS6mbv^(Bf*fcb+xqU>#{tTfw1EV7xXdNk(c|WJ-KB`ujCbEDemco
z+VZG()Mz!#>Xm@?#owXXE?%C`bf;VOz2Yg^J}=V)YhFGzX2%NSVR-XIZJCFwRgYDN
zlnsTKGXMCWK5RUrIeO(2hM9e@{R^6=?bNK)@vhkM%<k-jILq9YL+&Bh@`q2APNr^t
z&KtSq->zu|ulddt=0`Cc8di@LMQnoY5_Z1mV^qWA&EDvZ!O&^&Uo?Jc7=c;2hLM~}
zzeOTMk>X9c1>qy@qTDO(d1(Vd3*+Mz#AA*>I?V&c1MO3cTb7xbr^V-^ZNlEtWt%)8
zC)7{tk<{~UiMO4v*>T+%Ws|)Dr!XA`LFLoRKOM|DeY9cboNc?b-BE2w`+{hVZl6e=
zO&*sA^oiuNLto9ir9!_`Yv2_+%OmRVhwu>FLQ)vZcBQ5(<14X0&bVD5M)Z1rZ5Un|
z@B$q@xzIgFSE@|TY3*B_4OUPr9&`0`vQV`1<G$hLbCri)G8~^p=!)CEg7$z&e;|2J
z*IV^$Lo)~IT#8S(y<vItq~|S<<eV#xbIo7|p!Ui9gYRnIVJ%Hx^@z61+$C6t_JFV#
zqS@#^aZo!hpDjGEd_zCSHXO`_%E%3)Fs+}4^$rPKx*M^qUi?ACvkSF3k7p`)hZhXy
zDD$Zo=aUbo&7L`VKxAYxqjzpeDfUZ$yx8aJ{qE=w1xKMUb<{ZI9CL)Dwqh=WusV*J
z?bTBAnsq=%thX&T!H9Wm_{i_o9ItlR@t&YGRhioQy&pB#47|ZreTQ~g>(~I#wY(V}
z(hq7~vOSx$Gxp>6Jpm7Wi<e(r9<BLwbl=AhUl5kf>*xQ+)^UHhw4YWm+@I&1S|YA}
z!X`|Zw>bLjfw?y-<IxS7mueAjNafEgXRO5G_q^t}%=KW#U<X<;Kfbu<x*9Oov8n6(
zvU<B4@s3)lygTT6rG)2sM($2-C^tY5-d5iH>i^j68Tg~hHL+t-+o82;4T7T>)%ELg
zmvtzQ|6~&j<Cb-I&|7YDlmk^w(5h%Ggs^(^5<ldX)B_c5BVY7tjvqE2bF^1@7U%WM
zYkzaX=d@(~;UkAPBsMo@=O=AFQmf=bt!Ah|!HPdBtDat&Huq-sMq^q1fGo<iJ?#09
zru=@sS1dp8g}zr9aE=8U0-H~Qk1l@J>{|^5RfqK;lit<-l*TGzGf{iBYn2!FSoYvO
znHts4Szdvoba&ZxM{_*n)r8*^27p>>3}eDBvKt&wm#rALjY7(HVMr29hcm`eM)7E`
zBlzlmEu-(xwh6P{otH`C-K^ED7c9pfdBNWnI+ZDiKI%LipTM2sAjIeO<XomrB#UyN
zO#P{K%ym5+Ordzwjq~#TYYCnkQVegn`DfLJLk^0g)nG{5K4k8W%A)q9-j>}bpU!Ma
zfdg61=Z&ws*%U9izcecC;c&TWxv(<e+zGXjDX99ohPd&xJ_{M3PDMYbt|%(5K60y4
z$YEx&k&p;<A(+-)L;}*7-Iuj2y-iwjpXG={(kZ!yn}4CVDe$-HPC%JBfS#24UR~g3
zc?4<y$XenwjF%p?jgh6^oHsg9jiGURfl-c65B(;&*3Y#`cR@@D7O^1nx@gbqdu6I`
z!uGym5#joW?+)gw)n%^`dWRe|$O!forPgR!f^>fzLlY(Sb!K77&y8^6J^cT+iegyd
z?%03jew!n}1;0O*mww)LK(SzK@UHB@R+15`V@)o~Eoou&UrF`rO{I~^N+BGqHRAw{
zhl1Wu|M8E{BkyiB%nr(WyF_$W8b%8ruwQO}wp5P+`T37e6f23*f#o~71!L7aW4yro
z2+LHa_lV$(zNFiLX}-Ug$7=E^o;j@Io%|2HRd2{U3I%mJP4(=7bXr(xA?%19Q5YmL
zCQ2uySM%OB-ZrKcN7RAZD<bU)pvcc<R{A(sS1r;h>AFz}ee<f}-wt6|oll?pv(v`i
zV8Iv*%2jPgK&gEDSai2Gn@KKa7xXuydL)`3YFYF1p5y1oZ}>-I1&p%bc@F*jF9ZQf
z6l7m|Y)u9NJT*uR>vu|dz?3U)x+C6l;%cIA!Kk8jyvPxpejpnc^ZMTCUSaJAe%X&$
zeD0~iV$BNp+|k-mo~)KJn18b#6oZTN8NDO9E}j#jeMzP`=$#YR?S6gOb1+p=iS&9S
zUJ!dFL1(Ji{8xYW20n|S9~XjGGTOI;i~54Lka<}<AkKg}k_R}q(IsK{h6*;NVP0_R
zW-Kva<gnsyvkWo>w$K!&naLTw*;RYt_?$(%e|Wrf!VUdIu5hc>paiKiqEskVrum^H
zELkr}`3srqosgamW+;vPz*7Ljd1nZP1fb+hn%;oqTr&QSZnb7(OR{5DT8G?YMZIu}
zUAEnk4QF}aq1t8RP!(uOufp_J{-c)?{_9%oEmQkcqdL3RaxWuVwluL@Uz7K;(Wf&&
zDOSX3PVEwp5#US1L^Xc>RmCXemPf;20GxtOkEzY@2JM>EF!TEcpO-gBCIb>>RYApF
zO~X<X)Lf8YTD>N5Sh@vi7d%mN^`_q27+}@t!xP2DoM0*QUD>?=igj^4*@lIuvhuJi
zBf=RUvrl?pO*V3%iUuIVg)tYY9e)1P&sLwIL`>bhyrA8CT$DGov!V)M+9_$>F;Zjt
z_VxUP7%y6W#5V^}9T~Y7&89B|6}o*Wz3dT<R!omHD~vQ=8b0OYyp4fEtpZX%n(%qR
zDdOvE8B`<cQsV1+XRv_vw=c>y8ENC?U}|}3sT+aAfcu7TQGmEkH}1Tef3q)Zrqwdq
z@TlW`OIArmO{-+Ko|q1LUr8*VGp^E|l)IJQ{ZAjfq_rk~763?tP4bUmOJvG(ypX6m
zG+SBm+cNXpGFsGe6JQ=tMXgqOD5#9)C`RgGd5!^_bS9B`bdCvJ4YAsFN=Bi-{`&;x
zW*YdWbH?pZb=}6FLx<7>#}25+;}1z(UomA&aGb{h!Il05y}F5QF+fI89t-xTFD|C%
zlV<!)J+e<fAR@NDB~zX~%;9%E<8z$+!ixVvsC~`&6!!Z9GPx_aKYPU)@~U|H%2==?
z`l`MpIyN&}yv*hn<s-Y2`;)sTHr%2dw|vjT*N=KZ)xTvN-UK`Ax=N?+P~YLcq$=24
z;K8t)I*=%x2(7AD3mwPt?@TS22z8S0&@v%kBQ@I8r2ue9(H9w%#B0$|!=3tXC5CG6
zYH=DJrs(Wy?3vTw$ZksAY7;_s&dX=ymu19pO2c7QEDz*H2i{A>t{QA;5Zv4Nzi8YX
z4+8y)w$QyXxz(OYjcJe0$)~i=<HAa<5kLN&uy+?(iBCw*c>|s?a;uNlQVu;;VX6hD
zLa)k7`a#r017L0`cVfUF36~4Xo)M2;Gvi%m>h)yDb;cNHWh>7<L0FIn+%3!UPq`)6
z)AN%aw>ON0KX&}4*z4N)xny^iTMdY|OVUzyc0jrosLL(&M{bl%a}<ZXk~nJgfiz71
zLaTY~R^+sSD{pN{UwHXjW=8DR0(N6Z=7}Y_L+;4#F0O6Qj~yyn;{>;mT(IUjl@D@G
z;<oDeQ6e0O0sz;7enuy1+bUTd_E?TjzN(K-H?NrQYCa8QF9c-}&g<DrT|M*J({e&5
zx3EcCH`JQ;TcvZdiE~r58k%{^=BrBGt6$7dQGw_=!&hhZhh=g?{&$wj0?8?y(#Rj)
z9G-S6Bh%qe#;QjVp<D>`>CNXpJ&jpkQXNwm=_Pbu`?a0f^xjNT&n88i-lZQOI-9Md
zR@PI=83z7i)myD;qx5AV>bzCge>rOs^hrMBx_Q@AX_ZQ2zA>g^YFG)?O%x>Tm$aw2
zawgqzJ(;za^!9ZgaFW#|CBVeSIQ59#-!xdOI%Xg5`}`6$_>N#cBluh#YJ><j?zR<)
zU$%F$vqECzCk94Io$*~4apmTn|N6I_!($Aze$iYFij$Yc4!wJ~p3!71UnkbI!f4h`
zDOfmsWBEvbVLBjO{@6KcIP46GK!9wkaZg6ABQJYn1?gCJB(%c8DaRq)hyJ$dU@mhh
zc?q{7ANV;-&SE<Xp&xJ~#CwM`mX~nLM$Wsd)QJe{(%m}VJJQf5JC`i~5h=%6>5a-~
z2E%ILzXjIFB+7x-ZGQRx_$+#nKE<;9`BbJo^_`a8`Wfwv(4uR6roAOO?%RLo*=LKz
zx`Q=Fa?2z?1O7QsLnYmKAwao7M_b(Cizn1$2+uEAK2awEP6n$C4lIMBmsL+5f#NcI
zEgRbJWyz_N_rOvcvgmr9dj1q%+#Z(W{Oww$$%9;cJ6(?O1>(4Ti6K4nB)1*zFH;<s
zl1gJvev{CQD;){(JI0R#d=843Klv{ocvpKydsl<H(l5+>Ti-o9+nqR*IU`oZJJDUy
z*m2RB7vs+kS-wjMzx(ltACM#GmT!k7;Y#NUSG=STl6psMPbGN(DU@FUC@44Gc&v(x
zLlmsw1S7BXG|$u~;*DRBvaL9PA9mgT{Ebq6zUmN#27XMsH<S2~4Jofr&g<P!D@%H>
zJ4;OI!2UphWMkf7DqK#Cdfw$k)p=KA@VXjJm43SXz)@pmX!=9UYtw9xuW5@SD|U+L
z0t8ojNAzGO`J{L(f7Jec73A&VQ#Y1#BLjg`tu5cK4NaFDLnP7U$YyM^QQ<=2gDYY&
zV>tZyh@Qxqw-Oh{OyWESOv9%cFVA(cA^0K^6e-#ORd`}`Hg1k|^p1K}=RG5K8ytf8
zxo46uCfVJa(YqfdX+ocK%!L;j_W{-)>-p(wSh*dZF$><$K)>t3g1Pm`&cWOv=MWy1
zn74aIzccl|c296UY*nU?XCKQvDW7CDT^lY|phzEg*qZYTp3|Ekp`D_uhAhT}#8Bo{
zPXwEU)lfQ-s*qs;ExbxN1mATLl;1^j$(&F`PZno4r|g#)o{F?dA5fKdaTK085(c!2
zT!bJd`AuGD*ic&U?wo^4cr?q7Cf&R4q9lcqgWq@9_*)I$Wn)_VYZ|IQ307bD>}8`i
z?cA9fGN<)zJ)}?jMN0%aw|5~qn|vuL)DJ&Lhl=?@IFs<v)&{JaDI6$!<74807!$%G
z1@S<T!~G?FIE4``!>sYrjH|{wcp&f*8pli7OU%4al4Q5)`()4LhFl^}%vv22WVJ-p
z`QUEF8_CrwM(&{sx2AuZPM5Q$nnJ!eX~iP#vofi+W`gWwSc<V5z6&vCj7}dGtF<x0
z(bUY2<}X%hc_vrWcC~yr`I5F%m;n83vZ`g%`^6wotR<p~Cu&F(LPLI_YBNzRHY!iW
zFQ-(%#mCqyi*w6Ce=nh|K9guwXnih|dOh1SSO4{qT+li12jrsMkQ>E$f?m?aa{EWW
ziF+sDLKu<aU89rnqMVFS9bJ=?%1gHuk6H(c6BapR(LV9bN`z$8|Dblpxb0;OMr~c(
z{Oa|e=Y~R(4@fjd8A_u=&)|Z0%2ZxJyUDd=KA9>PrNxgMH!A4IPy#gPfJiDUKi{Z~
z9$ybqiFj7YfZ_8;Z`i{tRgldJ*jtgE>gSc<xykOH;Ci(CDIM#24(>%I+_P3&(T~7v
zo%q4c6C?~P%Ze@@RjC6{v^JHW0#nlKBpUXy=uY=5miHBl*qdknIbzdrbju%v<p0Wx
z<+fcWDgQelo|!~&A-LSqa;AGzw4`Hm`tInEcnTl(R5Im0@S(eC<vs9M!DAX%ZZH=F
z183k5>8|BY15l-@zpayoSXMJfv&7*aJ{8_w_67>M%8yLUcR~Fzm$?wYX3uFo&xs^~
zG<%<XI}DtZcElO{;ox*-ps8ZsGQbaIQ2RyB?qZtByp*gDfTla-QtGI+-;!_uDf_{3
z_M_5dKBJWvOd{{4%;&HE=EdNQ@gkZe75K9kKhi#mE>V$OPda38?~A;6<cV2vs7QFt
za}eAyJ7*AGu<N4+gPeO`pyA?tqdlomOS20K!_}2IEUmeM%7j-QPCTRaHNFiWl2*xN
z$8{~`&Wl0WiFy9gvc3d@P)_Aka5HCY3%NpZXxc<)Ipvz$B<@>FMqxtJ`=z2C_gQ4A
zjvdpFoV?}ZdY(wM8VU?uGcVqYJ^6F5YW}3LJf^*>HGXHaI|C&@r0q=}&@$1-!7K;#
z*`)W6+@zlG7h_{Lap=T=DV3vhW|U48oD`?B0Au1pnW*Sf`rL^ZJg>5?=CuNxFOmq6
zH*kfBSdt%#Dvvaocj0nkZe(n1ENlkSkp`SIt{DU%cvE70&txzw_eO2GAW7;m!(Yl&
z3T!{@`mxa?%SOTLHEw8!xhUgPGrcp{{DG&v5D*u42hPZMK#+6V&gf}<Q`a&gnU(g(
zc}4r^F+KLsU~SN=tQdWb0lhaAjK6^6s_Jznk<d77jRCZp^F01w&h%*UxTHO7mdlZj
zGNoz~nFC2zWuo>evJ#ivsc=`^^gJ_H$dzZH;HI5!y3rXoQI=9jZ5DP&$UWfYqw=|k
z<#@u5@uiT^u-(-?IK+E@|D!j|v4Bo;n$lW=mPVsxRa=N=^u5|+nmwf3$Fu&k&y_e4
zO`gLaynCamTCW-o6356U1{K&<)-x`~y+O~Zk0jL2OSnMUxHqedM;B$Jb3*ptwz6cL
z&_jQ46Cz=G)N9TWfJnQMb28V+UX+cbU8#sY?)qN8V!w=G>3Ec;%|6IDJ^dF)=u4;J
z>TPma<6HkiLr&V_W}-r);E^ADcBo`I4i8W{f*Ch?9_>enFAy;`?$dk0nqD*9V87o#
za)h)QG&Bv*jL_+AvnLX#$)RT=tIx{LtP~w<Mg5mn%4sGV`1$$eZG(ysYWAj9X=sw?
z=Y`%0O)k>y`jYe-?BRZ&BWfygs;Tyjc34Ba5x;l*EyiAYl}`e(KC^00n5#3;Bbm4}
zB=+l1W)J4O?BilrTQfk2N)wT7*~pE0htDLuuQ3T6aT6<UuuQ9$&|LHlfS=(OPFb~O
zPu0M3u|myhRWkqeayH#fST-SAgX1!}CV_qXtuGYqeln5X2dS|6#t*f=p-^ei-!kWt
z`@0z=0>Ave42tkHvoejNJu06sj`<|fDN!W{>%Hq#6HY)5aqQCH#p~cOD&Ohu*b?n8
zZ|M3$W=4|pW;T;@U$WC(8&VibS%||Mph#46aGzK4OA23@d{3>R6V8pd*<d-%Bosw!
z4sQ;pNd@a7*q-i|>Gj~9bS2HGi8vtK+Ly)8s2D)?8TX|RyG}UnR19Wn4CSbT19&p#
zqp!<s{CXxnmu(Z!{j;)7+H%pte@mFqCcwLq%T13tv0oBd@wMGg_cd0%kW4HwlfE$f
zsvazIS8>l~G<!g<CMV?C<W`c{+a*gAQXxoLIx%k#hfbyGs0kpLe%L%s?f!LbPh;nT
z9>Bm^LNpT#NX1X2aYjT+2DPiY7_AzNPhwbnax<H4ch+Q40SuY?pS_9HM5=Jg=^aT`
zfa6pXMhE=6&Wu5$RBKvM?LzJ3+3cje4p!VC7|mLapXZE?--OW|y|rAZQ7m-`pLkp5
zi=@BqJ?OMjY$S*%fZMWD`*!)e`cBcB*&SUJXOk0(!(v^>rPO#RJl@!x?V6)gPIy6)
z=)egmnhVgQ`kooR-C;q>?hB{jAWLrEo4c`G2t%Hh<^<Kas<(ERowvHN&+K04KBmi&
z$$9Kmn;ge^QKfK}o17}T!NxKU#wB(lrC*hbygQJb<wZd9>f{?^p6|lupZG!VD53gR
z<!*HbbfYe|`lGqu{K<>~8FkA{UkDNl=?!f|e>1Zt`j)7V!A-v;wr7M??>_&7FsJ~u
z81c}JRp_d+&O#dXb{HH2f>-MAFPyTy#EDx0*^g%)a_EaagE5rR#DZw&IFEXJSC)g{
zUMvnwSi{Pf3EOb{JrqSqFV4?PSx4i{%b>)(X9+)=GBA+-CQ$)d<<6Op806k@ZR*~C
z^;U1eW7+(AHCWfyg2k30Eq+F9YLJI*;<1dqCaK1@$@IaZdj9<6O*P~xfZG8x(MWK<
zk#Lr*Gb2Fs{!+i2|Hj871Y3B<_snAsDcNB#$R(}b-8-i-&t|V4UzKOFoR`xwB1xt#
z%d@C#;^Pb@9l@-acfuyM=VhIH6Gy25JTC`bLee%6!Sv5-Gv>+yd~Usl_7`t%E00l~
z5m;1Z!JHA_p4=(6&xjq`!7U0>S~4Ra&&q=t!Jk4jgma*N#K`KUhX^x=$lTf+n<KW@
zRLWapV>pDHBh$+x)0GcyZJI`_`LkgC*T&inFUE=I*P8@OJ$_c7q(G*2O^4PdQ4$v6
zo*zoIBITY)N_VlId6j;oI{4k^dbpF)kr+Em3{Kn*8y_}*adP2}L^Z)X!gz*SzD@3D
zKBXlVGOOac-cl75If{BGu$Aus+P5POh{V$TRFn0fT{;_0^g3d&A9Tli{{|*XGE{|G
zQw6$rfvdb3RjE7MeXaXaG=5$E+N<r&Wcko^n>#Qeo5=8Z0T%H{g(64QH_~hbThNOF
zK%a#3^$-j|7Zq^<y*0ymMhoHA<}!csxxe?eNol3=!pyD~ssz_eqvbjMAnr-qfS7t@
z`}-NN4nL>`O@`>!x5X6VhGJB|f(D+v*(KJ4%~Z}e?A@ps<|stbodE>=CW8UcFNmS3
ziy{y~hTN=8SR@@q--1macCFILej6eVzm#|gdRS!+(-BEB%E`^kH)JHWB=@HV6bEMv
z!$-_7kNlNCf|lSGj?Cfwy<~QOzP;(kPK?AZ_DL{wE#CLLlUc~;_=ecXY-;)rVeOLJ
z-$`yC5-B&r0LVB87*JmZIM)jU{5!%CB+<kQS<mSD9lww&#Ya2Te<BgMW^j%#0AVky
zZuU5-Y5SPyPOeHqvT#^UDdr8&&)IQO(y-DLR`~~=@e!&u9r)|^$wfFphyrrg;gmlN
z7$2<#72}J}0EJjSm>#mVfAZN&8pU1)8?>Kk`4?iMWj#6<-Kn+e`}N(Kb-9*t`zSnh
z;e^yN9#OOjze4m~{EJHd*t&*Z74!gh1Y;POJk>Gk8lmG2tmf98)oBc=p1YUJb6mkE
z;9ogB;(c5sv2QXf{d~V28=kM^mnsUDn+g7`FXf^{ddOLTb>ASeSe=X3mb9KPj*khi
zl#3|t#XpxAuf|>^00XrD<G*{55JOwpCGC6N(bbvNmS9F}8In&_le@_kw3f(rE&8`t
zQZdOMSrM7K+79zqOA&rS<=5oa5CxbwxMzC7Sg+ReIWUO`>i<S^M-L-)Dk1n%5R(7k
zxIfZqQxgoxXFUo$b<<KB{j?oPi+!@4T+bht)Z~gvcmOP4sTzQ^^<a!->dn_9RR%dJ
z8@{-Dttu{?GCH4$ZAK*t!*g15hD;&vz#D<4?BV&FC;qB30A8phSOqC;PAvwb;<VRm
zkoN<e=adR5o=NTh%9z8TEHPG>JkcJTjn5_Z9>wftvKD?jUp(v<fV}<raNW*NJ1X9v
zN1>u^t9&vEWi?rTnG#^cCMSh?wtPYf>z00^@Ou>wN6s@S15)arNncs}jaV(A=smNd
zozW1&WLh)&_TV~o@14p0qC;OD(x3H8M#T4WM@~*Fi^qi)RJHrQl_9x?dxB2u1sZ@3
zJ%ZLZZ+<S9^KMhV98g2E=*{K%Xs64@^Rj1MXiN12+*x!ff(^T+;dx&_F-;YO(F(j+
zOao=kmB}*j*4zid%2$(y0$RMnsppGgjGA%&NP}PSRu&Rtv;|%XzycT7R{!2%44HnJ
z@QS8r+KXFSrd4a%6oTzvg_BA3ofY>)>X2@g$XABt-DT?8%fP>psh<o%Gu96c{|Jyf
zvN@_mQIN1V9M17-4Vrdzigf&!22~_Q4}Lf)=aL<bopMG`mLoPrw1-oU7=(c8&v{Kh
z$*7WHc?{2>s6oN4mdQ6|Ray`P)XwImum)3Or4!$`M?xqYZ$NwKC<!<+p3(iiw`;5P
zT=JJ^cF!zjUhdK!ozdEd^sbC<Yx$_~Z>NYC!xXN`kv(Vd*77T6Y?RHZ9}@UYV3SQg
zL}e*&u>j>>UZ?Es?E%Z|5n}RXZVCc>ugV}9)up>+eYxoN8--Kj!OaIDwnlT$XtiT3
zGTun*<D1MZrZk!iw1^PBFyzA?F!=k+Bi~#enObHv%7USVjqzY>$4}l!Y#Qb}@UpGu
zceU@Ozpcx}8Lg^Wt<gtfeeUtDgU5#sLh*oD^79|(H#k_Ke`kft6fyb!>!&u)p&_i;
zZWAR~$kxeljs&#<sLkvx?hO@Xv6x+ybD7wp)F+pu^QF`woUAH#klCVaGNv&)?>+2j
zaOzSfo}VhqMx2>YZ-qcx_W(M8=Hwp)RRjdeOp%1`p_=riepRvP<7(@5?Tq==bhr3k
zX1BJOS&ufxmXePi&mi<l8qX7|DHRqWLY5&Xb0cUXLPFqFh_6LB3%9IW1Z`<KL?)%$
zv8pP~8}X{)@?Df<A?_Fst1>koO#|be;^NE+iSt~PQg0e8TJ{LL*INh&)*a`Sgpv>e
z$~q)9G`;<7c1dqbGDF{;rz{3KR-y7Q{Uf8b<%Ic4;wMAi1&R$Ep)bD@A!PhG!2ala
zPUi!;lY&xF>$<L|cW0K8yR(Fi<Ib~gKZu2Q|10xZ3B3AB>hTZJI2(a25vY6;KNg{|
zT&}QE!*Nbs(qf$onL)J5u}KsVl=$)gD*Hh~LD|lgylv9oBhZ(4o$-J<uiER$)D&8l
z9<iC#yW?(_(||$qmBNpdPNKv#M!c}*#l8li1Vp$b{=@&Evfg0Nx;Cbz%=PG-T+Aw3
z_0*Wyepd9oPl<0>D-E9_eA@Yqk5Bwyd4zO^Lp=~;pZCp5xm%S(Q$*1tAUaqe_@&|b
zWv~S*B**C+nxd(W-ns7cORz1Sn3g*^FAqoBa8K+Af7Kmmf+VIOSXE>8>a1t7Bf?S6
z%hVdY0zt2XPtB*`6>d}m2c|S|r~oAt1$kwv>B9i>TC8hm?9#-E1#M0|Nx60?dGM^9
zNap3ie`G(~X6rF3grk3Ob96xMh-Z%0D!E@{k?wjBXGhd3z`Fo1deBBgo<4Ng=Zjgh
zyQ3^87t!sU){BZk_+r*NRP=1}yz$;)ueWe(z`0w^pa)l%O6&>dl6$kUHJQ<qMM^u8
zy*-DMEka!5UTTzmd4D+{^hAYK|BHY18*dxvBra>|mxltaXGYU^>5tS4F4lH8zr9{=
z!ByV4dE%DO*%(==`d_<`r_?U61)K`rB!74XmpGxj57```roi*~*oN-ZlzbrD5uJ~A
zu1Ptmq>eA~c2f>4R7W$iBLnXICyfw9Fz4YO`erT4QLe7LP2+$k*QfAt;-_qBwaPJo
z{%AZO<o|fkLqK*zd)tgPe(T?8tJ=Df4QCSTh;6lBP+umHj`PsId-4aoag`hp0BS0c
ztD_FMa7bg>i1aj48nzr;*-i>0B`0D^!Z{;1g<LFaa%IlE%&OwHmE2N%L5EwjeqZu+
z{dwyqS~l3KZ65g*?GT_{a@ICMPn^A0oVEN|e%u<fhdY|<pXzu3J#<j%SC^amsGnmt
zjh8ijdqy+1i%fK%_N0hq#D0<92W~}N2F>W7_+jNFdv$A>1lCI+s;<9rrv1R@SZHUP
z#JHs%d^!Jv8ppWmcN^$|2x8$SN-02w^KWuIROU?FNO?7mB%i9>iwphtHYx@x<rgO-
z+4uvevlI9ryI7B7UtF@%<0YjY)=&Ht$KdhqXAC6~BA?pYdE*Op9L}`9O_AQMUng^m
zW;7*hICxf%zMst}?Jn_kIg!erQa%;EY@YY8w%|R3Xv;r=nDi6~2C}dcOy1TX^z&18
zys3&Z*Yh8NL5?A8OkS8IxevPZc5Mw$s(wdO=d30&<B}fX-9tEkjU77-OQ2ujWK%;)
zWA&mvsku@wx(6tt6jBZaln#5Fw~WT}4z&lp`9-ea>2Ccc_0t+dKjT&H4Rc<vtn1gi
zQmcq#?X%H**LL?fwTSH#RzI;Vzfs3~+tg-IKCPqgx*G}_ddVSFXk$Mf9EXF}kD!^^
zrmmm8psq|(WsyubqZsaGrQ9oY*`f2G-XV94lw-V<KN3_y>t~D_3fabst5eB$y19lo
zDWA$_TlxAu3Kx2)3<^cthzJY4Ihd+uyg_jhhxLZJ^|=^IF>Q+fdAen$eOLE)*0uMw
zs_3B>v_ns<W%4MP^>gejVXHs?dZl$Vx6C<y#hhM+KdUc7onp=dKS*{x+oQte-CfS-
z{LwHZ4phz=ZzUWK5Qs8~Yz;mz^C)`cS&U^bO_y2gcaciT2Ir<ymf>!Y@YK+6s6i6(
zMRUpQfJ6)CMO*TKaF-;(aXeMCa9=)7X}B{OyyXPdqlO;F9gf|=Zwxs9GJ&8zx2bjS
z(5~(hyQ5Vtx|o^O4`{%?9eT$^a;R^=_`C{4BnW2C81T%RQPzwfflI@O8CLL`)=QyU
zgA8;PhTxf~dY7=RWhk)^R#Xj&2W0(kneJQNb6x1si)08EC%gz5gOpK#RkndpQ1u~0
z<n5|aX5xCbqwH*{EXv-%D<EBL`rV?W^pKY~ZVnGDdx|}y#C}($6e#Wg?LTXb-3~Je
z9R?=Y1=G=!d|3%5GRD)H)odQ+X%gnlQF?CPJZnJ%wM_e4sB}pUl=?&?q}e{DCcLkc
z7$0YAKF%NED@lxQ55U({wp~<sJX=A^Ql9)s0>vjt@Y-ZM1O|l#1iF^6!cshslYk}h
z)}5i66GIt0m&pb_^8k>TJD<Txz~Q8>T3?pruEa;Xsq(o3wlYw;mLRnc)b@*ai?3<^
zG(a3ls+Qh8x%BvMeM>`Lz79uQ9>e5P8`%jmzR%~8Cn7yI9s+tyS4KlvidJZZ7<m$c
zT1p3~<v~+cZv=wc9$tcegrm;gzU7Qp%W49Mn$TO0T%<J7CA00<MG87dIuBc<BD6K+
zkHGIb@G0T>p{Z$zwxx8LAhe#Gr5?_gQV!k#0+(>YHe8QBk_Ho03e%U3%587KPz@I8
zzxZ5)k_M^8Y4e|DzALu>i^n&jU1F#9v^bkxlVh3feX0)WZi*BEtCV-gZknHgjJj$%
z>K-CByt=UgGEE&E_#_wv*pRU?-+ZX*=SEjRRW)6WRJsx@G7uJ*JegdR^LqOPrA;ty
zDy51(Zj+t=hN$T5d>Fh7&yE{-Ey;-5J=e2)qix8Nl4B4$N-%Y-h)YFYHazd=PC#$h
z@B^0(|Ej5G(ZCCDiLdNg_1Gx{VBbM?a=AOTu5D#RB9m<6rF7+^ZF=V5pE)dqk_wd!
zi}z7UpbV*92wu}D*B}%CQ57k+6Y-jjVb}B6nH%=W9HrjT74KNkNc;3<(zwYiBe`|6
zRks)Qd%98{U~jWl()EBkH%J7aMU30i<cj1D_q9orTT~L}^my{Dly3rL_K^WbfHErU
zF(Tfa7lat-z}qH<R;I>(ulNs7;}+u(uZf{+S7z5V5IZfA$&Po>p%W=n>q<{Q(Z<=4
zHXC$u-cmY9?_G`cD86=Ziqaxim9dxT4u~>MoN8$IlYgi>eE`=V(3nDR(7PIY3AuZj
z3+vL8^VtrKf)bnLPAKw&dMU4C-11MRYZM^D01k&m>EYXHq$F|5$~{Zj{eZr8>ioY@
zRIVbR;otm`A6D`n`?Or}eln*$qmjZOTv+_yB8Qy5#w&s9bUS1I`?N+*%L!5l1HUq%
zE34xhZ@3fe10}6+ZjNR7BhxsR6}8c;stA0Iq66wWeR7Ntij0c<4Mwiu*?GA>=a1Z~
z)l{-H4HeDO2y#VIZw;F5wXQZL0ojZ5PPvQL1g=L_^S%7{L!SWYT{U#?4YQFFw%IeU
zUz`_2qmGY~0lVC}Ar~c11#N<57$Ech(T<xZJ(Nky|GVR`RaL4C=0AUBFsCaK@2b|A
z%CyHeMP{dleTZG$l9)%lZfq~8Ov}!HpFb-Pc~}bb9toBjT8jptO>;!pd_GC89*fbo
zTkzgPQ|JH40AnH6CH#<gFJ_~lNm6dM$J$C+hsXmA;LT?$0|_IiZYT{KE-?bmG^q%P
zeL9I{<O@ZI$m>T2t&c}K0w0)KOL&K>4uYuFseAr>^Bu48B{TM&_SW{6uI`;#TDZE}
zC*-RBkv=Q7YwK>lpaClThvm&9ky;QO<*{B;C3ZDHmQo<^p3P{m>*a0;S{MDGKcG~B
z*9=e%RtYyPKf=V~lgY?a*bL<xwt8O5qp1=iBrku%Y6bxz!s$C>Orars%UqqB?WVxo
zGcWdv55+`Q0inn~Yhad|n&0nv52^e(VAhurtFh6rmWb`IKF|t<Sq8;ALo=!e?TY@g
z_%Qm8jID`#8Cs_oh1;}0mFgenM4T#dUOmoU<!c-`|An9z!WVdGHteHv%nw^xGx-Jd
z)JV$yOpPg0JmYjD*H$X4>Y3b<+0J#b$U-`o@B|&;t~?Rm8@JsDeM*<hHG`?HWu}FO
z=}Q@|dF)-2&&feazeYi(2+_i+oWP@lG|lp=$MK^2bPIs9_fH2YvNL^1->H4;pUIi0
zv=6o8;E17YTlU}t{&Yfo#X2Y8OBzbXiJw-?hx~yTskJ|0=x-oXy+HA18xgdXpBB4g
zu}ZX>!|2+FWrgPgLYjRPo)~+gqqt2<Y-=m4+wO!a6(DPWMuPX@v+R6WwGo;&Ewl8*
zLr}PLnJZ<v*v(KlfTxZts`GLjjx8$%?)6>W$bT|8UH$nqL7KuX+$Eyx)w93xh5-xR
z%~5IJG5PB3OuHhpc0@a?`V;Q^8TwJ=lOo*`@qhy-Eo<2vSqWZB@b^QM>Wsb>NDe!l
zEnVl->ybgqs+0my^4rKq9DiFmSe<U<O^0ZZB$b0Pib3pR+Sb+XJTISzfoC%xL<&h>
z@`Mq4#Uw-#qZm+o5my$lg>ynE5?-cm$S+wcSN8mVP<#x{u;X~A>2+xM#Z#}mZGcjo
zPXgyVVpn@Ps~L|jh-x;q6n$a?hnbN_1xKgQPppBxR(tCkoHn`^i6xwsi-7jt336Tw
z5(fusNBqKmJ5TRJ<#w)W#C}Q3Aezp1;8e=<Sijy$f$s}4sY1IQ+0RmX-Qn-s`Ux*Y
z$r#Tdc~F9%OzN%l95q|5C!?pf^sKb@tQ8~ADbvlL8oObiz%AdZRS;L4F+T~E&h(E4
z{@x`GY=XnPF!QRmHnn!GE3->WN3-IIAxTNCUbj8CHZ+mKRi;2-_zNRZSXtgSAQ}-V
z2ae*0kRLvb-H=fZ_OmBmX*3)Max52WLAh#>sVe0}U|y21W$B!gs}dUC)t6Fec3^Tj
z3paW{<5hCCgpQ}+vZr-+Vm~=h&z$JFm(BLf$fOE%(i$KbL5q}7rMgW%T*sXp8EX@%
znFuz!zW%Uz6psWXq}Y}bmoqJ5LtD~hcBi(TmfcSG{h>U*l5jT6cN-0>JZj}!;zx$F
zje$LCU;`%}A8cV$MF-*o=~YE1FTV92A6)C>ZpmBSGIcHeT9@oxAg}_o2wV-$^R6>i
zBDWlol?Zc7M8-JWh@2^m&vH$NKn!ZnYsf{Ejx3LYAWa6OEI1ZdT`YH|hjOv$MsA8t
zzc<YJ2;mw(3}(_T8z{o4GiRJJ>ZrTq6BF`yS6lY!?3#lxeR$j&=RxzZDpOuF=bl4F
z>&M%48*=8=I&3%6OiaM`hHtFfBP(d~p&OW1`np!0>Ar%vp@$iHRCThQuBvmSCS}A{
z4PJ#GP<!>1ev0<4zOi5r;#{expOX9aG(^TcJ!eQKPr(9~&`Oj>jzF*yn$h3?IN+jy
z%ju`@L_GcQ0@@d*)|E+Iv=}`Sa#t3kq+8aW5bujE(e@8)0z7nD&OCuWx4>NJ*2Hoy
zjoRnDMxt*52o&^}wo>W|yD41Gr(w1RYd>=sip<zcP%nrG3Hx;|xg^B_*v7m(j0+m`
z#GrMPJ_IKWeZvUBh^<5h^HG|PI?7e~s5*O!8#v%jV%b!j`|bREDL)wuQp}s;U~5Wj
zmN7s7zx>uAXC-4GL~l*+l;QU>(ekDyp3Js&J(+wui4d&Q9Ul4}=~GJ{_lM_iBI#dl
zBDane=p|E^#B$LDCC^r!bB@}i7qSJN%<%Zf?unfL5X7G8|4TD)km?{YmNZ?xnI*NN
z<=0lR<ck|_BvqiPD?fR+LTF4BrfK(mM&p{W3qj8k1yYH$^*)?bU(a7VMRHwIdw$BX
zPY!V4a}MBPA)&s9*tfs8sm%K|c4aP<cXfBi&WI{HgRX35pUBt?Qa}D|dp2d)9hbZr
zFRXZ+k-LsYKYugn7%5A=EaG}&^jE?$p<hs9KJTzo2+LJ&&=8l?skEF^pg3uzKpo1L
zS~NQq`YAos>=UljoS@-FWv=G7GR+Zlg5KVJda?^ZuqfSGX+L;W_F)#W{v-9qJilpR
z3~U7n9A8W@VDxrKdKh2T#F|!~)uiHJp3<O?5_#=m@hn3g$$I<~=}P|ya-|QvF$YXc
z_)y~<5rol7N0}H#ki^RxuZ`VkE=*Ad8GusznmI+48dX2l!sML3H~W(8oSd8oTKx!h
zl}#emZ;W<Ob*_+ghzwbAkffE_lpV*3GI4-!o-H7W{NhAPC#`djjBGTI@B+V<pb>_N
zNWmp>pyfA#79_{U?%<4x%mn^UoQdXXWE_(Akk;I|9fjoB80rDH$?=(6LH{0fktM#s
zVE`oY9+5_l*`xFJk=y_rMemCVBtH5ZY2f&LHk<Ag`c_t^kRG+cxkwT-<?V!r!z<Jd
zBW{L!Z;TP_WfB-!6!CXt$D|uM<es*G&~y_I*JS~UmVsO%=h^%Z<VOIC^}so!rH8KR
zhGw*{>Z{qIs67-F2Ma@)G28|brsV3%7|>nSHEb9>Ey&ah>$qb$<%Ojqq;3$|15-}o
zA=D`ODS0Ug$@OwJIVRfF`Ca2Dj=o_WsxDN2)AJA|_Nj~$0x`JA^JJ8MRe+w{ad+G+
zDGmN9s7B-@G=L9*g-m_-_TS=irb;fo*`j^x&x129>yXnkS{ItZ$1_pe(S{s<hzQ~i
z^L<<>ZuQh2Z<-&Nhw_~EgX**Uy&I}wE=0C<G;zow4N+n$l?BrN!F-O6>xc%cSZ;(D
zF4It8#;|8um538o258Lr1m_=Qx(Ulda*>syPQYOesoO;t6?IH;gf9L`l_1U`Covno
z-S-lnig5vf^P7V$FRyC|ax}3|YuH|YX1_%2Q(avtz=G1_DGiPK!4s<*(_jioj-H?Q
zkMKSQ2L9SGjsb~aQz%tWy_rsm$sjM$ed<J07r9a??~dD}p&%QmR*XBjM&C@M2IOKO
zE=v#A<eVU?=j9jYc_)gfP(4Qx$7yaF2<oNiiJN~nh)s>5j?i{xT1k!XwP*Hc;)`M<
z`CRtk8VBNlPVbhTT6K|`VJ6=YD*N2#Ctf5N4Q#8VX@7W4drcE@2iHvw;rSdL40g;u
zF-eG?3TY;+IgDuSHq#w5$m_BPM4pcCq$+4^xN?cK8+bE3-rM9M;??88=XhgqF^MX5
zPUr5d1%#3UV6Nb@^~)41@F>upOxr}b+=?;aJf!Ng;V%+D9Hco0MSgJgbo$OrBchfW
z?Ev{YhdP5gL!`DuYKJRRh5<uV_@?k+)V<JSC?@xBT?o`TK~e@vWz8_m<LoNdH8$=b
zQBh<KIFk|<GnZ+)hs0xg#FDfqs7reT%xqDmK#@dFnX*4;dWjqk!<#Weu6PL3j22BF
zNUlpQn{7jeRCK-PB7>eN=_VI017N&|oTKQu=<7T7{m;HrHT@~=Me`@z!|+zODh@1a
zRlRdeYaU`~)M_EGazL<ypP#p5P=W(BlhT4}AKMn1>Y#T98rGjjeCbdbAe8*Ts|;`m
z0cJEBH3so5He#WhpgZ5SSF`0A2?9Dm_Alg@q(r24$~Q;nt6{ThYYf7GRx=uVvXVpr
zhqRBMDbfWGAom=b9m{`X4qnm=2XlRty2HjYN#ec#{*#B9X+c+sO2l{1Nap$O(9HN&
zGz-z5c`W&4au?M;_xQ8hDMipXJx&2E7lO_c1uu+qoe7-oc}+PV<?Ml@@QbB<$4$Ku
z_M*?(G|*pD9o?9m1k4bA4v04q`p+lZsTBO579^m0vi{*4A1f*+pi7Y4qL~Td#mS3M
zxgCwYK<fjNq=MA2bWTYTpdJ#1j!=1usXnD6qd79TXTR9|0zKfj%*0Ilj^NeViN}ZN
z7u%_4l9VmA?KF!%>$h>NPH__9A^03)n@?~=P16`N3Aj}3iMRl3qp1|5!=z}#g;3ih
zrPdFjYT}x__?&1(Q+-|Um{YpW*6d!C_H~f<CChPq+++O6u<8{zw;eUgPP%HQ%S5d`
zQryexaK5Uhrp$^g&x;MapnG~#{Dd{99bP3?ATrwe*8fBcFG?32@FnfL;?>#3$JY=I
zW~laAPi(0WoYw}OXx^88ldWJB>X3)3hc#xIaDQD)&0RX*_;cytqR0#R5;^AhCpKs&
zU0EJki8CR^AP2(}P`bIKGt%LD6p99u2bkEi;JPA*5D;9-&#zZbQgi;fr*$eO2x}ZG
zUztR+KpE$ZT+(UJn2_uZKK&?hJ8w06?ultXF|rcAtD&t>X;0&2bJst4!+?X*(g?~g
zOzuj5Pi$9#cp-WmntfK1TTdkOXSbiTCagSXlm54S+DBJi_5V6yc+YSRSba(Mq~;PW
zDC*-IRlbigjugRkgbP}p!wc*q$df}~UNl9rypEZzi?f)&&6%+}7E=U+lAEtNWM&OP
zmBvE#8eZ4T*b9>(;ypcnCY#k;vo@-#30&QNbOFF~&qg5`5{(qK@(Y82@eBB{FJEp9
z)Yt&kHhJ}1|Gp*N@}?>o?9A-Yb_=KPIf=US9l8C`rX>#*$?8Eg9ro}*74l=mJLJ$_
zO%ko6Y=NNOq6tH<hbp^p${V+E#y8<WL-3TUL%z#BWaKvzW=$q1*O7*?5LG$wJXBJC
ze_;}jtT^B)bO<1?04h>vIJAsFnkF^1c=-0b>pWjn88$EBL~0z}g|}iX-zTWUu=_7=
zKBNx}O*0bcMbq4TT<o4)$jAvzM8yLP6tbR_``UI{UoY0>#Id}`00T%ZkHdP%Ic?(3
zn0QTp;t=yq8eu<?r;p<^(HAX`bX1_>E7y$Wt4yV#P<1Q)R6U+E1ifb#;`ud*Na=1A
zH{3O==$6>k{M~BkQ~N69sFtHrRILE9-0MW6^PHkAhmHaY5r&mLqpS}!lp0Je=WkV)
z6CN811f|HUcmM0#xTx?@5O5LqOnE8&ZL*@+oSsEfBJyyPkIARAM5(rvYC}C$8ouk)
zl#&Mb;xlpQZqUfxGc3*2+l8Zu8uV6ZW+K9><iEL$%4KT#Yp`d;usVmFCLk|#OL<*K
zr;|bYyokF~S{+5F7hSN=@MI-l<i+P0Za~vpLN&hCf0t*|Iu5>PJ&7z+kJk?s(2Su4
z-h`!-E%gtlD#+ky45#J;DS#k(CjB4&xc3~rZ-~=}re2+iTz>otr)ncQr=>PBtC^~N
z<Z0E`R2+IT#Y-LcV@-SncKiy=h%*$@q)3PiFE*aXQ?O-`agR)dPObj_k>A5cAqI1N
zD~Lo6)pS*DS~qRj@wuqz+0?W9sm4WEnlIHf0#)l>syfS~TtKiuPK`R?brD~idZ0Vr
zsJO>qN$yeU30i3k(6h#>0?&JE8T!mSmw27(-L%;J^j!jCcyS%w(Dv8m_p~d~k6;sb
zYpddnJR3c$t8{!{^092;pGegTRD`qD^DB-wSkpO{5Xt1?043UhOlqT;1^5j2=X!i?
zSZQ)zGPwE#P0}Ja1kz@Ti(I5hwoP>@73FE_9Y9+_Gjh5YNylYFug|Es+%1W}5sbA>
zV0k$219B21w03F&-VxE=iO$fg0-UcJhXT52VC(LE>0g~rj0cCfA2qjn?Vd@cRPnnw
z?%A$=TBa*Y_H|a?b@P1`So#H)UaJh`4D&YA65==%lKO@{bJ`pFkc>r|38}*vkKNxy
z!wc%UJ1dz4z6gJczU4w0?I2e*L)rvYncgSgwt6E<O*hw2A&tLSRaz$DOd<2-%yrWm
zGN&P`ElQE@n3Wz8qJLCYl#0z%<!XE=pSvx1^<R_uy<$wm{4=>A{R%~co+?VF4V*p$
z#;olQuI_i-%=0dp6W<431ZRK%kLu{Q@FMvGYLY#T7?pxHI8bKIICf$FMyUEETMat)
zAso8PaxslydM-oH!#+JN_N!EbsZJ44hF+Me<a0GHMXDKx`8>|ElEG<Q*xJ31*8b%A
z36;F)r;1pV7v8vw%)n#4M`>9W!A$q(&pdR&ao$s+)XJHbuX0;R3n}Za%x~*I7tTij
zsK@wb&)#m!Q;-07ITcEF2&~jHs!FU72Im`vJ&Ed5xwC?0jg^|9sBVyI6lxxVnZtmA
z#`wGlFJ*NKF*tEr;ei71Qnwky0@%myrtL^rbzV}#br{>D$EI)(A{$S>ncdXo!=O>=
z%Egp&s^o%p+=~~&<pIhfM}gHG1M@%nk#{vmwZ)aI+U52gGvDiOS)ixvJQ8zoa#DG*
zgYQqcLv6S~zn_&<P6BJZ+#MzrzfGqf{o$%EK~bWPY{-31!SZ;m`K1QWXP%2nm6c4?
ztfYgNX<TgFtD6UelFrmUY}TS!0O<?&G@7cQ@T2LCpnM1j48y!<Y?8(I%pp3^CRLb0
zy+yZqNssjxQl-!3s7NK~BGy*|7Ju37KK8W-C?eiwIGbL%Gjp~*w_u_i;OD_vJ@Z)9
zelwYcUT*;o7C6+-oa0l@s3n%ck=v9U9KlkZE@VH(eKH(>_->U-TgXDF=@XbCKD)E8
zAs^J$r6Xt>ENPv#LU=0L2*S#P735Gy@AuJhE~@DZ!TAT`VgppIPawBezzmE@_jtt5
zPgZ*=eAoP6LTLS%H^l9}nLqk?8;BNv7#lIa_c)>v{R(Qb1+kUM{C2i2`n0ws#FNCP
z19Gj4UZNx!r^@p0lJ!!Q_V3i3tLRP6bHsG8Cec!`qCq)MV(7sa&(~`HzyM%VwFE&L
zatU#!qcJ|CL!eCpebQbkj6l}2BXhm5vA3uRA@3ejKyg~mba%(+>5GXw#iZazGmUEG
zuezJ-r+$k={~;w`J{Ubm+ta7bbH*#24emOdXy0r%TNcHl*0(A)x;C}0r)lg^p)t9b
z+_J6ThRFBH_DM9Bg21bM5GwAm{<77WCw%tXdeSMXof-59kiGrGf4Mx89vrBKmlHAX
zj-mrEHcr2pW}22X>5$k*vvR!g0LU?!cb~z~O87P`mtBH1RhigIAnJ`3$d)TpWig+m
zG|li6rOHA2i}UTr`SuHHxi?*JVBl)vg5$jts4)v~nG^qQqfXQUU0u*B3qsGBzYv-D
zLUKrdTDzxHqM&;vYyUf&VlXigE+7n-y(WiA3w<*Q_}t(EJs{_`4eW>P(pE^O6w^Hf
ztARsp^r-pHP>sa{*55EE=c3&`*GXtNFdD*)<m9Y$C=&K7#$YK3Is2i5By>6ikI@h%
z%N&2$s{=^}IY^6A_5oKVq^WTRF8YO(JsgtehKSIE8Rp<nv<)^p7HNzRejHRt305zj
z6`!`7<>%1$EXsRQYtw!^`FJ+jrth==f%R361n=J-{=@NQ+9+#P#@mff$AR8sYRdR)
zTD!BPV{W}oiijZGCypr9g?D>u2C4Cx#MJ5(Jgi)w<hBsxvHR)`6(s)dQpy24^D^?2
z_7QU+XFjxyh?$0UG)Ir#f)+00(7I%DQ%Vwuy)w-avItpCgFht-RlE-fZ2mct0W2X%
zf8J9?5KQk3?FHuc{{osRqebc0TGburxoqmW32%F`2r&j`f#O1Xg~>b3>Sp;p0s*rk
zE)*>SRxUM(lFNzp&Ic?{Z|KqAGARVaiHGg%ARCfLiZA#pWA^a;jhl?ssM13()*bDO
zWDB%MlvQ#qvmNU)13?dySA<wPisrFI>BDC#3&)nwe$2@*h=WfS>;L>S@E2?blDcnW
zE0wCYoe5)Sm^nHm4<6SI#^Q2TAgBT5w7%kv?{h|jvVm|*xM4Mrn}++KfVy)A93$j&
zVXn$^(e!KDQyfvfGlD=UWrP3>w#xq8hzuzu`6i+xO6_H4{9sN>;{YE&A8pqVZ1UPw
zUmn9XQO&BbE1DyY?}Zdco*|iU)c@C=FPW-gP_KN|JfjU=oN0&-CGE2~zI=B3ajjYV
z4OOUw@v`%f5q_NtWze$Zp}~isc@G1K#XLp=v4Tg8JyZwf112YWLdp#&s7b{X9#H+J
z5>tk5lY<=|an*zG?IQq?mME#<r6@C2_|=w73SvgPI?zxu`>p5lU<Ca^!S}}hI|DSI
zn!o7$zd=GI5PD*D=8WkC3w3HS)21C9(ziQ#an7JHGj5a4=OwR`S6?US8bm!(h;g38
zp{;d%T-bc3Z-hZWpLIIhF&Cwb5ihSNtJ&lORzn|rYW+i$5>oXjOjQ+l8VjJPXiDOO
zv28u&Ncw<q^bKG=wF37M*4a;gW`EvoHkwGiyuL<svAg$ww#+@qpsqhhDJpig>=cQ~
zS#5`SB(bXN(IM^Jv(MUUP!J5n_wAD&qccL&gWYaa0S>Ie+qN9rh=HkxzhURVSG{+b
z`c|kpaM|%>Sx~L(2sV<dGWh_<tuya+6kR*!x~)fsNw;!u(^FZy$eFK9T~Bh|7t<?x
z%I>V5?ch~oA_H5}Qlb&J^dK5>q|t^Bo}`8T-Vc{gn}sl#W{6bx?&#Xg!sFDEb|E5r
zwAl5;M_ol-jq=<~+K1fagfwEvZ^rCIQ_cB_a2_!NE}!BCi$*vgcn8R6gW5NhL!Qi|
zPy222f>Q&<UEs`I?!Hi_>F+wo8ZGGLa}=ovn){_{?NbDLKewHcGja!s37-{vf$Xt6
z_6b+o#LL%3Qd=S(N&<l$p|~g@7>hS-8gTh8E8Lt@;oiCKpZ$=M#(lwI%U8vpx9As(
zI=l&1qRL1VlhpjP9qwaA;!cBYo>;0?)%Cf36cMQ$kQAAN@^qadRip37$o1h#-;MEI
zRB=+>%caJKH8Y>>dRKfQJF6$fD#2+(P9WmxQ%X?Z82-!3iJyASO-GG^YC;V)V~^{N
z6MCG;R|g!Zl2T1J)sdz_uX>Y5PJA%6?x<N3r0_uTd*A40)F|dpRJi!6p1<}mbKI6h
zD$+XyW%D##ua*8fTyMW96(&n3es6F(@V8ZYXG|T^k&fasDaGklQlnT5#vqem2!k7p
zdlhuyAJm2@#IO*)-}Hp}$>jB}*SdOCd%yv4z0Uc6#Tw@g6&tLZpBbE@bYu3-Q1E4}
zWFt;!4nKtv4sq%m#$i<HPA#$)TeUOf5WucL%$bMh=&o7k=jO$Oy^k30IOfPThO5%q
z@v073+9eEnd2yi3s@W$KTPbyp)vuEsjK{du3ql1kt*fhID)f?*iLXjUU30n}pcBvL
zg*Q*u1{oMQnrmhL-}$lNL)vPx+3w_mPAUkWl};{Nvl8NuVU>502RKyJZ&6@A#Jg&K
zJ@b-kA=e*<rKcvVPi{#4YHD23@A<#9$UvwXHoakx2)(AoK8^mtOC%#9FrZ~Z{2M)j
zAW?`%GhOy-bWPvje=uchd|=C#q=wd*J@N+tPLAZtWrNn_#>%Jn`<l_a1UkVa#-U6)
zxXI$6q(c)wQoT{F`H3kY9XUv4+m!(SzR*2S%??idO-bi528L<^Emex~l&t?xp}_pn
z6{Rl=8bfBqac9n3rkq15Yr7jl5vN7gp8j&NC~<^EzxBuwk7vTnxR1HA?UHzU{qMe8
zpH4?`uD64}I&-%B->17@g-D?BTHDNIpVD{J_M6<1-HwS*tUbF{QoY5#`gP+jzM8aO
zB@!NUR)LfxTpZqb<A(%mP*FVxY^G=cM^h`E;AyA*hg4PdSal(>VE*d6c0ZNwc(eO@
zSI_mXr}%yc1R7>IZ00#BIpQJd;4w%3uySIWx5<U?_3qpH)BgI8ZpFTsbM&uj@I!R4
zLcl1c%wgh!5rLE3@Br5zD1i*$S|JfS<TlOjKiSUm>;L=yC(Y1ze&yw@_U`X?skLWz
zMiKNxcZ;*yM{)zX>HA}A1pu3`d|Q7hK@x(vZ*&077}7Blx%al_Yib0srpA89A~s|)
zMgB3Uh0@7ssxd(&!Eg@6`rIFp3;(Vjy}t6EkCO0Pal#`WenS!!kCEZ3O6bWSs&0<a
zTg!K*krAqf-Cyq(|JI#mD0i3Ap=@Te%pA}`hjODhtC)3{2Zfau5O(462RT-MEVzFp
zd4SC4|LxzoLLWAL%)kD)SBbKJer=(9L3KGGPff0q5YXnjBirKM6K(!KwA5T0)><lj
z!!8UU<nrsH!*`gMLccO9Rg!@-urGvwyjOZ~oI11&>}`QhTHDIcy6Z$m`nNWGuc`@T
zK?D2m@ArOoykr#QjmpS33B|1ay~GuV{Yw1J%8^uTar<)yMkD@_SjejBws;OX5E*+8
zCYq)@k}j3^Tn4?Vcdf?r@Mq>v{`j}*pY<zqzcRDg((>xdTj|GN)o6-k)WAY^U0ctb
z$xJ{JLZS7s4_`_>Uo4Tz4UaD$8AfQcqIR1t56ieF=9|%eLP1qD624hD!#;e(X5**<
zc<lsO4j8}Lp;ogMoef$WW#~$4qgIZoACN2_1m`YVi&84~pzxPBM_y;)%cHk0|7UAA
z@2{N?$*^{eo{zBV!95kiBe3f*2`&+__7Wp6jxnfJeQRF*z2E<#DlPwdw=tfU?h7-Q
zTfVEsS+lko<>X;Nk12_EzU$!c_&(cx|D?k#u-7Zg?D#oDsnSBO4~dH)P=y9)sv__z
z7E|Y3s!+U)Je?Ph!M%I`y=$%AObb-YzTUOBi&3u77Ya(<XGql<ufO0wy-ABYO#>s-
z@4@^Y``cT7f%1d0TlSpiRI+>MI|jos>>vfjgcM`gs(h{~fWDp6_~uH7!n)@&|6l;k
zVk=SjS1WJ1f}MYw?*4AH6(_edx;yz%mx7iPB8Y7NhxW5rc>R2X(6Dw=ZJZncj0=0v
zMxa}sREuWj4hc%+2Ewph;Ju{G`~FE%HlFF(_|>6imk$t(t|t{j-;jzG{(UJ+c}o!4
zf2xA}=!#nF-#*o6k-g&(nJA!kmnkf|wAv$h{>2oCBvs1at?2P>eiPF()M!z4rqy@-
z`d>Bur=P@u{tihFhW(LtPgBEAm=YrL8EZSDAP)2}$d|?bsZtg}6x3}SrWvq_=!cm^
zgEHAjs6{#HjDzQBds_-rHuAyBy0c!b8xxidSm{n*`qln2b)C)0>`f{!RzKBSOs-W-
zT7Lc}3$C}!{(r2wTdi4bZ{{hI&jVsX=N<!9#yq^%A1T4Ym4^4*M@Clo_A7({X6@m|
z6^D*L`M2MF;AhH3{LQg8yI-BzYHwk(BO{D<MxSPa3ELgl7leC8{Fx86!M3W6PMmb>
z|Axgb!>CV#wwNiPM$9mQ+(IqWh#RL+K4y&%rffG33^cBptppO~Rq6)TvzY#WNPGY2
zIL`CFcXqg<Hw<lK2TN$Qg5;fdXP3hj1rs18L2?@J3}>M+j403w;XxTjCRPB0s5!L+
z>!dzzPP{Xil?LR>B4IUQoU{gEP(gH*SfZ6wO`Dp40GE-Knxd6noqN)2k)~WVZBA&}
z&0%iS<NJ9Al+z#i??U_~a<Ti)`#wLu&-eN9-f&+ZEq@JL#L%a$Cm*On|6|30+lRjK
z4%jID@qel`kXUM`?_+LWD%f`n79kUdsL%OyD=oU1nON>LXE(DO?aS^<1uWr~MLRM0
zqyPRvS;UWJn?F51{5N~<{jFYf`n$a^?f=@)OTCX9Z<HAYI`r|mIr|Bwy~%^~V{hkS
zG#Up!_NVOTU_V#fg1M<wq>c*oG$*rjmD}(ps{XVLR?9Ki@l64Cw=<I>b)aUEbAR7;
z-?5)2^RLldn_9Dhw4#;l7qnypt(FF}r1R%DPVRp)<pc%KL|<dKNiJXz%io9GEK{E%
zsl_3h;MfG}6mWr<m?QCmw9%)Y;0Aj5!7u#kwg1&Ae)$xO`scS`(DOy^kGOU4cD(q_
zDfe^Nw;!3a|J&~BmNjo2dSQA~GCpH48gR$=howOpQlYg<?m5GqlbX@WNCBpZ=H{8(
zkNicrwn><AS?rpeek%B1V{q(`u?ri3F&3jn**jy_ue64$Qk}hwD-*kR<n^ab+>c1^
zk56p)e|rAZ{@y-hNLHB}J&8H&#-Z=6Rk95T@wdp`^0~MYzFmgRede!z;>7=EB&jUL
zNK%7yrk5tsUOD{l4_W)?%HfsfrJwsdp@+-GmWwOn`Jd<~#FnZCNNUYIX)s5v*>a(X
zJZAN)v-&12BQ(b&cZJlCVp5-(|2u2`QTlOzS{|66cYxPEO1{gVwkk(f&pvzsQ@$zX
zebfPb>+jT)KRH_h-%9|65i{;?;lnCVGGVASO}F8h(52<~&tI2s#ISC8@8S<G{D3gI
z(68rvJvXzf1$AK!lncFjHBb6}xzb#Q@Fu0oD4HP2m?g>*2&gU6T6k|%ooVj${uCG>
zM?0ubgAf-7(pN{!-9t#+q7`ujNJqg3g(N=1TG~1{n@Mq3Mc*4y$Fp8N*tCC<(0zme
zZ?6q=xG8gf8I_TXKmPNXM%I<Z?UEa$-ZrRLyiFajFZLQ<o>UbsRZ%4g>gIM{HiUTA
zr8?Q@p)!E>a!sI;Kjk-?UR?1xmwuYaXqG1XO;H*v<l8M7!!kpP0Xr<bSDi8@SJM>N
zO6y!$VmV5cboU=AA(h#GY#G`O4V0~$=Jjd0Vyunr%ZEeswpG1@T+pE?hJ)!nDBK+@
z1Uxp6YY1w1H0*I+qG?2UH=}4h&ibXqtiUZV1ogKI@TI0b@ck@P8JWC5RaBEs9+<fX
zLk}?3Os%wBKASHl56LZ1HN6bWZre_ENL{mSFmdW#mn#!v8=DXuKDU0D*Po|Ikh>CH
z2F?vw{fkz=&Wxlr%lVk9SO&Fww$|bE0{o*zqKVW6S0d0BTg=a;^>0+65J{nO{iEAm
z+RU?!og_gdeSj%ri2@RB34}*HKg;L$FmPKIsH^s}>d~PK-zLavd2-tXujht=W~<Zh
zkAc4n1*UMs*GBK9Ot79IYURdqW{r5K7=yX%;5k^}s)wU6WDpDkF}azd#NEF%0PlSe
z`GG!z%c+d`P;3)>dl>2%j8T8W3s_qnJHrlJ9K3SJRa!8hBY;?G&KC(J%hytHD~h*S
zQOLkFa<bBxTm_wU5Q0Wl>$$#XzlO{fc4a6(s!u7psvjBz$K9g}ccstHqw_;9B1^xd
zx)cCo`P1Vqt8u70-fA$C*6(B?(L!$ig8h@16U4|^JQm+TndmWwG#8;`M`fywHtrGq
zQ$|^V4YTY{>RMz;n)ajBoA{tzZa(kw^C5#Nd{&<S%`gs!FQyf3ebptT=Xj=lWR`&f
zDVOI;<y-pi{0qH06(H9H7^2zYcb_Hl0erD1Bpzg;jFzDAlGjYb$7y`;weSBSFDMko
z^Z7y{pKd|#U3sI~y9;#`N#|73_uv=QpHEFmUyvl`R!&Ly#P=%|EwY)mMaEYs(X?WT
zU0}D_cn!(n>kg`W=8&Da)braYsg!r}+KLVh<nmLy_UePOqWpNCMHMVAmVtad*t7~Z
zO}&_a_rD<NiJ=Jn+-ZxJPiACWqQ%I=4K|q#)W^N?=>~PR4aqSn`8U3hWP(Ro4;g|M
ziOD%e3tXbO0&ZmreVpm*GaztpoZ-I?)8!z=?t}E><=srd-i5HfFD>@_3(_h&f61fw
z`0zZQPg$&ok>sq?&y<&0$gu2}P7a;#->%i=^kglvoHB%+jA0p2s`^7rfaXu}Eb<Pl
zJC&y|U*-;5ZJgpu7re!+j9nf(BdbXd>&GXh)wdcsDAYz?rfmzM#a!R0&Fq115OeNM
z`4GB|f^n$D&LJ-djJBj0T&0czDEH`hs&RS)KHVBZ>MG3<7gNjTiD3Ww2YIQ34Ud}n
ze9uE%q0=-5xjm$(7u8;|ZL*PE>zawvOHNT+1c%uOGlx8XrVj-V9vCy(Uw<brNC|Wz
z1ras+LZ-%Hg$R*k!MsAqYAkk5u`j|15*?7QcuzrwOTdYJ<nSlG*r!va&f8r}z9^Q*
z9keKBQ@wMR#qh5=YWvI8bJi7O$hu{SrZ7ZfM+kD48A&o4S}w?0%2Pbpf;&ya(~+&<
zyg9puD>^dPLlH>`zb2NR$6;^{=Sv?(-$=pB-Y}1B9kbWU=o&3oi>kb=+}*7*Tiu*K
zJ9!)eXp;mZqaG#_{O{*~P8ZE6<ZCUX#zbm0VBM_jy{uDuDQlPVkuLgd7Gd>*+&*&&
zBn4k7(~m0=1q!0ib)3v0zmm1BO_^a~QdqwxGl0XGZIv)v$6k6q5jiRk0ZLjWl_ohl
zRg2is3Y$TMDPU~+Ab|7{>WgP4HZFH|Z0>YJ*X6U#;QBY76JO7z?KI#IT1UCQuJUaj
zQ+_E|UbX(tZkjrS1dfKWTwY+tZSqYF&lImHe)||Q3@5ZPb+(Ut8$fEbmx&Ff*&VI6
z5!4w80Hzz1+LBO8)kX|tiG#1{%m_xg$eC4}>V6M#Cwo-AT!DNnOm3`o$m9udo=m>;
zIgTS+51Z66sX~6&pt1(<EZ_A|`A(~n&m)~iGm15$wtQ|r(_va6^GHh>3vfZk%+MQf
z5*2-lKVl}rO=v*r#%F*)Jr!Y|1Ra1Pq#5UiPO-waj(Fm`m9<Bfc(FBSUu_9N!AQ7}
z(3m6lLt4bm+>1jP`}!%Xw`CM=G2A!G%^~|{wd=BBWKLS?@Dzf-X2Rg7kd9XNrbDTg
zRPc)Bx5wo}MNc;BqXm<r6rmKP#DTJhf=7LOMt3okHk-hwigTzji|!&yQ#ps##XstD
zg9haszO~^qV$%;hwEQ4r7r&DM&S_k&Q*b!wGf0N<UfH^b4(YO`=jBcL0$Ah#a^neg
z69#?PcpXu1j0Yxm3MOq0hkK!CXXt`cWZ0pWZY+!Tr^E&IVY7WP!F<W2LP{t+1kc(-
zG2y`$NCFr84Q|$Q>4b(Sq#`=^v$wJ^tsY*YZOTGB3bevKWI2UAyU3L-KnffP(y?4I
zay$q1oj~-s^k721$g=mi0&b~+PKA%rHOOAq?{FxEoiPLrs0VY5<Ft8&#SImdl>06M
zhy%b;M9cUGz0#7K$gEn#u+lxGbY}eKlcdRrRL0ZJ?_9_gZ;$+u*w^}l`P!V78K8iZ
zl^wX5wGQ5<DrFv$2-(v+rXGf<37=~)0n(7U*=1K4V5AD@Lv~>MREL^5VlHA%7g30%
zLPdZ^YUDw{GdjY82#P<;qL~OF;zzTyU7u4b4K29?2XScd&?%Nm#_5j(gEMa>7k>Sn
zoqQ7*=#(X9hfSmd-jF$){qI@UEgl;xUx07~k!%4?=0(_jO-Ac(VKg0^Qt@Rao;lft
zucc|-WtAwPm>%(hHiv>Z+5{CdhOhTzMWs;|8FUW-FEbZ0l3JiS^{fp901&$su16C!
zX37#7?F6BG_rGq#ND?kAS^^_aF`Z!ux^e#;iG6jO5`ez-rSswJskE8LJ#t}<VG7sC
zo*|kRR>iWeHj0N|Czk7BaG0Q7jJeF&khSuQO_L7$k1S7k{4R?XgjCWshkdPF+F~k%
zXL0XuQ71lSSNe;GH^_B03jJAm_V}y+`NJspnpK*!^7#;nq!$Gp`Zl%5SaOk2`N2`f
zbp{{CqDcl9tXqQ4=>IupHL`YN@;R%6rO3+l-E!*U1awS2ZHy^UIyMDNYKU%&-ErFb
zK4n!=>&hk1%Ra)nRO3#wwkD6zPq=`5$JhShOY$gnE;;ff=)zs!tMB^0WnJWd9Q4=j
zjFP*mujad%r=d)Elx{}Kqt`GzRz02AL8#&#{=x=CerNJ^j(StTyId9A!{X3zh-j-q
zz{MmXz;9Nf6HYopdpPbYXU(t6fE%=6fD&&PIaeE(35v$X`b~~Hj34{;oPdk-WbY8d
zB`N_02+56VOywwlTzOZ9&f&(>@IgNdfjWsB#UE1T$F!L+^CH|x`%Io4E<?rn?i6d8
zA+1`o!*qOD|5&zz*%HW(s#B)Qcrv#lG1x>EFPfGlAZlp)veH0cz*H6sULBw(w5pm2
z^7Pfp;Z=6FGuZ`^nL9baKmMm2Q6YaGE#emp)3*l=4Aq>HGN(a|vQ?Qpen!+{JfY>9
zJCf)>+(%<ZS~e$~us;L(nx2|!9DbA>ox3^VZ-h7~45#=5<dKx;1XPSSCBMNq)CCl=
zy{Y-s@Qc7AGO8bK$>acvAqve1#{klZ1werYuATU}An-!LxrM+sT(|b8Q;1Nc#j>@l
zJSPTJL)qw2=p^(6k><{uIf6#Ruq<pg#?uw&IB^wdKb}Z8JivgETZ}tf33k(GvIK3i
z+!2v9eiAFzBHb=8rcIE*KgN#@+2hkQ6D#(L>#sGK_t=>1avWd%+;;f}r@$5taK6Mq
zl$JkkT^ei+-K+{WLqoODj>Q_)N%vXYDii{R7;`4GXNkOYz%=3P%qZk+|IRh6qU;``
zxutI+m{Ks#tPV=<IO^19iYZdywbHsON1h^0tj7IcB;sYGXSSa;@IH8e35-hkqkD2}
zci|Rqjlr4g)-Kl*<bCrHMN$gry?aZsmn(;Bazi_?q7OL>Ly9u!v9)%~7J|GcT2q|z
zCWVE<9(QGxA`YQc?8!={lWw{)F#-^>`D9UG_F32!)`>Z#lcFpVxi`{x3#J3NgP%c_
z8w5SV38*JDQ6N@0U~x0RqE*BFK>g6&`e5(9oH|$!?Xb>RaVV-=B2~=jmoU>OCn(6K
z(mYn5I5wkKKC~(KZtP6qpTG+tHFyOtW5^jyxI_;UYWWDPSRtj_6wmVv%YdhkwwBc+
zB;0L4(#kZnA($7bjvFw>@wF!&=44J<h5mDNOX^f-4N*4Fh^O*H`|nhF)ST1i6X8p8
zVVqWHwlj5|@y@hK(gN*|AERn)lSzx4J7d?!2lIn>wB^wxP@fsW-!!2U0UYdcJ&PS8
z45t&Iy2v(?@LadYE=`l1CFj?g8lPp#D%vt0V}g3F_nqR2T&>R9n)!PECA`#~)*b4u
z{1;Va&>Ad@1188qpRwMnR0Uu(G0~!>93Tx=xIBNxd-wt=0xG?EFYGGv%4=lnEmA-j
z?~0C#uW(ja9f9IPO|f%L#Z`zccBASas3Nc<6W?oihl3R6ZTkJ$IK23MiSYU%Q$Rtz
z%{;dxP^H234_C;$4q3a{ySUDk4DAe4c*wKz$@Kaz<tYqA#3ZH?kbTURuJFT2?6Sl$
zSD5@1ju1}E<Do4Qq#Ywuq_Y(%GZpEM2Ek{YWCNuJ6hrssG1BL><x<ehrKVi6XYQ1X
zM(=-ELs|NDR!1C@ziUoCXzby}5{pYjZnLVXx2DU(6FTfX!(ixsna==%ph=K1Z##w%
z!+f>TTyHSm!S6Q<{W-BsD0CV{a?snS5k7*}s<0a(@+qd!=o+&3$Pg?d1gG+Z-6ZOV
zRmYVd*;r#xmye)yUb(ze!UL!>R75U-g+aU1stlIzdIM|QKU7v4rm!jKfa=9kNJ)Zt
zjD3dHm#%LlOEn#q<VaFEJk}V?G95}H1c_pZs%_h{r+v}@slmo)BLJ*Xt0_T|QA<jA
z*u^RZjnqfc@GBsy@6h@t9Tnriec-(Isme`oIw^H_60b5~-D?Ph==~Uyc#rXzsG0m&
zwmTkB4iHHJ)_jIIyT_Z89po_@ATx3>9HAe(o7uP{1{>oknzBXFSQwBI*KOz+CtO)p
zObz^F6e(6}kuPkj>N@(Y-w%xo?j)xhY{&UG#&SMYK-U&;5ihT$9B#f!u<h8DZ|^4>
z6fGVvqbI`ev2h^<kQvdfg-mIU$ywzz6N(C;C>WCX>iFv}TpBSkY9bI0O=gKa#B@)S
z=(Z~EnSYkPQaR~%q_BT%;+}O?)$tP~o`1#$JWk<8-<f>3lZBKfY7n>gpMFIaS<g=y
zPQIXSRrex`<pIT&j`+2k4Y7wB^F{H@^ySi15F1jpXgVRV(UgVSG#he%QPm;|RCzeA
zr+EOpzXV;fmz0m_J<<~bzJ+YWISbPxU$`?gnjm`_CZ!_vC~yJ;RUbeDe=c1Vdn-pa
zsJ564*2cS-u#5llCJ~ha6BZ(YIo7UB-n#b^`F?7C#6nizXPg)S0icmfSSfy`&pHg3
z^6du|6_GY($lGqamepu(tU(xWGTIVSB-F&qq$rmcu(!SoUaK}Hrm1#8J!HzFs8L(s
zn&a&8DBqL+)>$zRFol-O$UckmQbKlMWlsCn!cV#!M#~_|mYBgAtYDK=^#^otsMb)e
zY1vrG98Oy<!sJFr+G7Tp8<Wmud>js%g<xVp*{T68H0i8KRUW%H0XjxnWN#r|QT9W=
zMtDFK@(5#FS*!rdk}kW8d)rL_nPSSCaCdeUG{;EuDb63ekzLc`xBvYP2_4_S(-0}<
zIfub=vv-fgwT!dB&HDKJ>O|7P3B?j}{xa%@Cc`%p8GBaDm`r`RBQF=T!J1D<w|;eF
zvspu_HYw97jL{J+qzh+~A~w*xfO%w>f+cPxPQ`)EqQ8;Ar_KapD&NJC^9Y|*yl1mD
zz1e(}$KPZC(!>~g!@GU{m$DMu)$^B)7B?{63|#=DWPpS#e5+jZ1t)@EPH!e=U!Mx&
zknYqtWawx`-@_K8LZFC4)0Hf}a!(Qs<cO#lKp;mV2^}1QfI3QVyy*r^WdjFK;zXc_
zh_3>7$WU^_z$Lf52D8j1MHl<wrimUffFD-=v48lJE{3CUn{|uwri|WmmTDROLl&1_
z5wZ1R<8BzMv(06I6e%4u*GGjHCbcb9aR5x*rWDFl-Ept-u-zfiz<dHfUW<u-AfG^(
zNC6HO9?M4$rwMR+K*Yk$LT*4+I&DHo-AS1j%s({yuc+;nroFO4kbhy5`wqByCg3Fh
z_9r+6kVoM~Zh#xG%5&-zCc$!%+1pfMuXrY1{GcQxE>N9hF=G*iupYf+<oPF52E+h<
zRaZN-IpaewY^*gX4o&3hQ>_lkfXr98W!-BC&Xgf7tn+<a0EnyT)?RO2m2_Jkcm~<0
z-#HoY`XLhr<IeS~uhqfM898kRdwj(3Xiua5fX?Cpb%3dnmpKVZCJ55WrB@fADf5{U
zZ9>*wS4=<78~VZ;|K5x);yE$quE7XO6fgb>0Y-WSAyudRsTp>ZpgfB{v55}Tju%xr
zGKqM?yXws;Zh$_9<^SG{w{v5B1Gk8Xecgh;(h3~3mwyR5l^!ht!1vH|Ml*W3=1C}l
zbcHxXW;)2sH<}(x8LnlOIxiife<sU$UOlt1Id%k;1O{o~CB#5sZh^v_vFA^XQ`#h?
zG*E;uaqyTXrAmO9bVdrQw7WH6ms_6Ai>_WiOR93x_cxL6hCJ>^j%2{6tW<C?aM;<^
zGIm+|fsbI+c1@}3)-G0>&y#@CAXZVIZidQR`l1*wL28|thwDU+O}TDmd*|@_<`@?g
zgT&}kfYp+?7xRQr;vxxTE88m^HKo3oaHu2J3*u~Ff)l(0$Vr5@ulk6Q#guI}k267F
zOi-72p3e1^<~Xk=w2<7-lyQ%;nM`86Dhtd5W6}>OHn~q2((QuGHOpWdsWt(R$Zld?
zAk6DyWJ9%(DHq)^WGiJa)7TNH)R6cRar1@I<g6v^sp%yh)<Ba=8w^oZRi9v@%M=p5
z_e`U|pW!|ATo1JGJAcAm^Ei2Ike4PJj~e-lg9H_K8SguzO4I4+66_d8k3$KnlL@&l
zhwj33c_=nT39O(=y*LssCT)V>$vX?2<1mS9I5CVAt`k7VVM;3l$Idd5#*&I8?ocHo
zx?~Ht0czO{h$#B~oeXsZLdG9`=|gN`J>ziH1`<hZMj>8x2tB`L(E@T?MBtIe#uPI&
z1kloL#4(__n2$27K;z_QC^G^=d;?$?NL<>;Vt!zzrHDyKB7yECoZ$w2Y&s#2Xm!dB
z>Tu{0T2p@yJHF?NcggpNLlKMCJBOV{KU@h<lhU9c{mc#?3S5k@R2qD5OH~Om25nnZ
zhy2slS<A1>Y!9am<<E_)Ol-c!V+kmN*(G~o&rl-470%4Nq7Vr+6BC(&y1FRWRE0f0
zG%^L!mtB+}oS=jljv$adI!<$d0s<*kY2Ymj#8QmZfxq*6cE<JVh1XM<Rk&4Mvn=?6
zOO|&qKUBWQsJtY-3+Zk`3kY=A42F4|v;l#Z4Ay6}Jq2O!y~?4)2iwSy2FaIT97%$1
z9d?C9k^-6-Aw*-#Ssg#KB9kZ!9OiCS2X;bFRBJK<=@{?$J-2fxVJIzS!jKPf_;xod
z_?YA^J$`fzSOw`P`v*j6+}~^1RU)KN*opXPD4I<x8FB7z3x#Hp(~SbfBBb4?J4Q2+
zqm;U}m|YZ|hU(Y?NUDdNHrPWoJRLqOE1m{dLndOc(#t%HfH}D!z;_`Rs%N>h!S4jj
zE{C}3TtED~X@<GrfH?_y@|gl&=cihV;P&yYgSPo17-5_O*@qY-DK|k{065gf7jB+R
z$Vyl_@_J*8oQ})2k*UogMndN?<3MA-$J>rYVGl7nTZfFsST^TOiz^7v@5@#uRyLbg
zLip~r4PM!mIO?-kh)OgqU#G-jDvd6<>!3VW&J(buhyoTvAVM2Wq56hm{~j({p0a?L
z_%BE^dxj%BbgU6HJ#Jzq#^s?UV#fmt00n^()R4fRuIQ-=PT`v1wY~TTyAm0Z@r2DR
zQ}%5GSP47udN>|HDiKnD_KV;Nn0|vEZ9_F>d@T-huP{Le)UKB-9Vd3&6550mlMGW#
zGFsaTanF1%$|I<t(Ptc5Z!{n6P=R*jLKs2`X+Q}{)LW26hK|E%O^bsuj4XRAZej_7
zpr-|t@P-r{HC<)GU;{W*k;*RwMC1g}6ui>?uxvO~TE2jb-gQQie_dC%m3OhqIqtt;
z9TK|;;in;hTsL1oZMGR!mL?b^$7P|Pk_ofV9ttRw>W9CVz(@R$IB4Jy&!IP<VZb_l
zB-nL7U1AzTqQ(vmLg_tVbJ|F01rdk``&AQ7>M+1&QVu!yKb|HE$0+vCS*IXWTZVSA
zm$np1=^Q*I3Wl!*xj>aOwhX`5!72*mIc3N>^AuRTR8JtCyOsVinP0leXQ3t`w3Waz
zIcq6=5WCaDfRpNW8|<Z68vsR*P#Kgql3FA{`y|RYJvHM^zJ|7KtYKuR5(&dE|5r&w
z)HA&;B(e7j>&&-X0wb>&bC!_3*iu%ze5N8X7vo1P0trK|y~ocLE$d9)>WlJHlh6`|
zlHAGV&LPem34zvOu_?zd`%3u|-jb(cOB;w0r<jtCQn-X#+Z9PGr}u{s*}v%3eM0=h
zUB&>D-O%KzIneN<$37rWN4CVuU?I04B<)&i7YDy>7uZa`_!jm^lgXcSn3PCJ@WqV-
zLZc#oBdPXmoayjFcnLRN6LiLg)^S~;-7VJ@^WB=Z5EWj`O3_y=I63fT0zp!hV!|Vq
zOAcHzdDeI|%}WzR02D;#{bEg`GwN-^E94$-RnA`TRq7h;z3b)M)MM7xI!S;ty((jN
z*-gIZB#R_;VUb82)hf_qfQG&!vzw_NZ9qW5CC4$QH3dJClo+REtZ7f#4bPyKM3C+h
z%LGc&B@*dYbr~xuXOA&DG;+1h{Tbo7AG)Zo_VIj<{U;MzJ)`pdEr!{8Tw=PPOf4e?
z%lWF<3VWqu?0^<v^q`xg!6hT7N!(x&>h>5=`z`FHUZGio5$~)LLJ+JQv-whqAyk&-
zT5L*d1|X}0%Ondz90tEn)Yy`QsE+Hs(u(F3bCPjg&t10TG`uMgIfI$M{!e$nF`WcK
zRtH5suNargwA82kIoC!TR==^8Q3hf_ho8ohYdvJ3G_6k|mcr{&MTOIDJ{eYunEFmO
zmQ)c`jI6Pa)uLu{O8NjRAO}}&aTE9m+$HZMJPfs9yEzeNNTe3YUvbZ%L7PW5V*Dmh
z^sQI7i^Y5}uh5}FuOTIB5ACn46F%s;!#pU~WAYq?R*&gev~2+^OjCP|Pfjr!Mv+Mq
z@ygkUgV2qMys#cO)COt58lmGz<Md2n1kdCNU9csSLKo?!NLS^i61u4D`A}|j`oa4a
z4?Vic1Yx(6l^||1`K#UAFq)VnlA;;aZ;*eQQy8QDL(EnkumH%cvgz0{?(;-m0>#9o
zlZnDnGD{5b1Vp=25JC1kW|Km~G2R!k5T7V<gCI24if5NtVT7<(OJOdIWt*7Bsw}I0
zs<Ljo_ovj0Pm|2Mj4+AW!HEqQnD_a=_<+db8+pUMY#46%UYR|Y_BWfxz9p6C2~#tq
zDh8pmNr3~`>88q~Ro(;mVt>35pGpfPXrwVYyP2Av5MAMb1fTKUAW1kk8u#SSo~+SL
zb7brywMU#XV~?tH%6r*vwkkpk9=f{Od@Wp)6fl_B$K!qVKWsy*doCL~oJ-2Q)L*g|
zDXZhCowRn~usX{@hoM=QNlk`ygK1K2h*zN=zBP?!n|b(2CTv0E(5lu&5P{G*#uT4b
zvaArcP2jNWg33f)+PcEPU1M<`+OpTcs(WLQsz6~cobHTq1QN5$@8P$0e^9IyhUaGE
zD5S-$q-<M5Qqr=EZ0*N~n&lVEL+@iqgpA^b3m{yX5A+z7iqa-;SI!yK6xidfh7^V!
zn`$&wI4ux$JlUj)CWka3QtYV=HIoZQXOKA}hf3ebcIcrr<WAX(W%v;||4ZtMLWCK*
zK*g=1$;X|hrJJh(1Wc|q%q(ws?VbOKU2ii+#ZXY|xAN-UQuHubM%fY5yu=WmH_GXA
zs0(?=N^d2bVm^^ZGb_dK0xs)P|F?ZSsuTmW-#-#)YoUZ~DN86yggIdUc_yLLV87ti
z)2f>Gvf@jol*0_CzurNAPJ;qJztW7YP7}9&<aH!r4X}UxKmLt8B~O^rSwN&+0x9=2
zdp~Y4eXiL{5VW<$me?EoV3(+;lar28nWd(21$vrrwlpG|DMIIWny+mZcp*)#f|A&d
zl-ZOAX4UK#6~9O$Mu5EqE~Q3ZY$&C3q;-eHiXs|UXn>z$x^!i7rD9HwZNL&Smm)pn
z>jTe<sAKEL^Zm;pV%EqAzA}h?f795*Pz7+EMmju)HcS5>U9thm75w`fDx6~TQ5p})
z!gq7tlg>0r_YUndsBeSt0u_^OM#kA<{Hq85&gKbpmoH8hLq!q|JCKeeU6(5_TsC)_
zLbF4VOpH+$CRPON`ltUg-Crr<SQn$8FZ6n$LWHZ2s9UJi(y>%tbCp>eJ)lpS_XX1-
zX>u7htOLkr#J_v&ShoUlJVK=?slP4>$<%M^pd|xk^oWAeT2>TVRE8xg?WnR)v^&*{
zie?=UKKn^6LeLcC)tSIt<v>00k6!%{=OCQsvI2wNX7x))?WOXiGF&m#BCWfUsS%kq
zCB{h@qDRs><T4Xi#_H3wa3*gGeS!DPl6&N!=_F<_kx8(+NvI*tiSO1yc$n2JW^1~_
z2*(x<2L?gbib-&sy`<74V--Om)PaCL553yq4k|`ub2P~QwLkwU4SY9_8LgeOl$1sE
zHjU~j3m`JUb}HMp>ywdHC!EAnu*kMl*K74lT=!;U({0zCfhEpXg2MvkV2Jw}RwZBJ
z<V7pV<8Mzlk{F0)I<`{298!KL92-ixSc_2w%17&_-42bQ;LnX1LC$I4*^|SGYSaN2
z<fjEQY^7bQMlT>3mF1{MM`bE37`ZROdoJXYOx+tIivdK&ACV%%_H6FpbUAFQ8GCXN
zZ5RU%*~8G|+btY>3wxQ$BCEq?vbu`CJ2k3{%6F`aAQUx)V}HFv*AE1!P#fm;Z~j^8
zB5t#Ky~`9XD(7A@&}^intvLBx@tR^+YAfgtYAfS}aqqN(Q`=@9Wt@#sraTL)GctqW
z!Rj2@dsVzA<M<h4$$s)=p~g0&VXO!;2GR?o3X&5nCpx|i4a`o!t2&rZaxLU8DoD67
z@r4!MitsdM98j0D{?=xOr#mTSS+_AS{hVqFXK=232~Fo)y~pvQ95<j2HIr!eB8EoB
zSZOfqdoySchy*V$!LL64eBB>|Z-a;mc{H*2nw=`R4?cx4RzALpMM`}eXAR^O{C-}_
zF01b;b-#B%12H*kdwQnnts#x$ulpOkQyjltORHdkBC>-$QwBwXw_t*A#$gpG)<P{-
zI-`0Rhn>~DfKRC{5%NgtwEEa2kJzjsfj7RidzRrKGNjA*d2_)etQ73&>9%DPa%eaP
zbX8U<-3Rblb1L!(g)ae2J|P(kPO#Bj*_>=`(8VBSbrfg??|vpzmwJtwamvEe_tGPA
zC+tQwy@%~!J|jHE<Z%lv2utp1F0XnV3%Foe8IviFmY`1JO!N_#f2Kk!W??7cHGzg?
zDltQKy(hJmyv`m+R7Z3^4aF`+<o}ih(CuxJq+}nfZ~6w!jU%u%Q(Nye#`{1!@lMx|
zd{<yrq41bRQ3>}kOwq<s_?Q}$jQ%cgD7ju8cbJn_@bD-%fXGmw9*{|Rifrl}2sE{V
zKA9*A$!x2`ku&W~7((7(oIy$vvYD3aB81b^GrH8Gv)H!Ic1EO8hSZ)*{3eHgr|s|d
zsuJFLhwZc2|H<z7SemJizx<hPJYGFdv~k&>hLF6*!AA&)sx3lyv=M3>4pXFz@)D6r
z3=C3fNCgyuhR#kx2i1)oE*PXS<^x2KU|D3UJ~qLy)kC_c>d#Oe0BjN~g!-tOm%2zX
z>709Wgd9g-_UgtOqS##%k<sF>?$WUhg5W9KDD)0lpumSn8CtKF?E~;{VkCL^v(06E
z&H@R)Q0@Ypx44)AJ6@7uf|i6D6g=UqaekHNEW-IZ&SFEP2^D7}#n$T@r5n@0Xw^e`
zyJRP}kc8+Do{?iGoqCC#EJZ^Kb1?<qI=u-2)q&%2<!P^dcA9Xg&OPc}!h`;xG-M|1
zv|!7Dg4=Z}^*fd&5nh^OlF9;hM}kV5Fha^ZN8A;<<Pf0#BMh3E=)%@vi}6C7GokDV
zOx=h*WeMmNY6iuj$ZZeN8uEw>r_N1|8;d!DZtp$&Fi?)#!!@8EVbyoOyd6WU7222b
zRF@P6tlLy|J<U)OudAQJ3eE9=>}Q2BJ(vSXc#|84xHCX5&dpGlMIKcwqJYcsV^HV5
zRoNl@AkLAJJv0vUPTCmZCGxgyjV=_4#L~4Awuu5cRoO)Z6C>y~m?a^xi&tqLufwBs
zm_f_K2f1HZl&*;$*9~d5yg~tRWl-&Zj|u^6Ki?=2$-oL>hD>voDs}Fdr|B-oRRWpz
zn(?BMXTN|O?o@+oR;qZmuDeMS85QP7gy-7|JV>apovL1tpu($cCq6>aMLKH$jvDU0
z?6p`grCV?wa84d$5<1kUW6yYp$>bxyu>)Esjeu)<zPe_SE3+K9!&BBtOG#|Gia`mv
zsHpFPNwOcTK~0Aal}SJX5E2q$CZ%v;(cqaGK%E7S$~NM@0Yf~5z&81__Wr`8-d5kM
zp9F`O=j>-0dV>O1uUeglskQav4X_{k5?(V_$9-XDDe}LZrg<Dm=l+9ob-jEuCTwWH
zdcQJ#nG+|)MyGBMeVd_H${a=3DhOO%fY^v%pyf<9n;Ib84Z5AWaTY~lz^9=LrD?#-
zpjgsR#%HE{FgZgiXLa~5g#ym>9rDjq%wTNnNZ<p1c$fd@C3$h7(0eJbfIoz5%DQ(E
z(bzv%{vrg@e##`gQICj0;-{D^o97v*$tvfJRvOf5HXkWCEIwP5849nHLWM=hZFxkt
z4G4rg9znGz%~Nb4aU155^sPc)xFd8o(YZ%h*=pUdrlu>0T5D$u<e7P=eqRcp!%xkA
zKv0mzB{ceN6t|@c!UeeHAys_|1IuUNZEBoYM{*L-8#KLTO4gKB&S055jWGgKu6tHI
z47w*ns03I@ZW;-;Etgo4<?(vrmXyns<spEEex3!A&cj(xRnekDUR>W^_Y36icZMu%
z;X|^namtd_#k@ot);&Y_fF<A$dX0=ml4?uLnFNzR&8-fuL(t1uOHZ%ML>e2L<G$m`
zC<3Wl<>&ynDGaaU<guzS?aHTJnQfD=C50VyYE7jqn_I)HS3Pd#XyMK2%=K<RLWsb%
z>XKfJul?gc5v`!^6PsNnHMYllgRpD2agVY85|a2aGWC$75!g&}5fs449blk?(=?0|
zEbL7!_P9R<exzXbozZ5Oa#HRXg?X2N9NpMLJJ26ltB!L-Z$*+sZK=}1eCg!7<tkJ_
zD^}`Q3Uk)h$nyLBI|&ot{bLE<3wehu7^yHCa|X*-B%y5IY~0NAf^mvKRnx@uq80|A
zg)2C*zyMlF$B+0n(1!R0vH(~M3=@ULO6!;jPfGgrbkBsSs_8^6J*l(_X1Eh;uPTLR
z6{9~2lx6cN79dj>-?IlKgrn;T*R5OLvxxu7i)z=wN9e(uvs@g2eDS_~6c;0ioduR6
zL<|=a$9A=I_%)&VFk*6<ZY)H13b$-9Y|AH*AxDP|;b0_r2znS|)S`qZ*cWD;9J8k2
z-t7t<YgvS$r;zJ;cl{^C_lCyf)|3IV_A+XaTo>PQ*FzS24QNOS6^*GK*bO3Nx`gQb
zl_mzAH)_Cs^4T#)cTA*=zsa&wXjNJYBK|>eE0)kG+}JS0ti-zPJu-Nu@(t<u2Yy#R
z)HyWfulbt=n3-|@`_|8+m5@@Qx|C<D;C_*MJOn!ite&$Z>c^;Yj)xtv%Sm&dn0fXF
zSZ>4Pr^6jd9J&aZi<rG|HbpFQWfHn2!6*h8lxo|A!cvL=K?R})yRd(PiE3#GL;dqU
zRXw0A*B!Svi#pEMk9kPJORxOS&eXi!Yybqbn~jeFOE2x0;(V(5%eo}$$qaeWCJda)
z%)1o5-)_!l+8K$LsYHNYaItOr3dv@64pim)6u)q$Y2uZ~BL(kOq)<)ZseF|pMUfia
z3N6K;2Y#Qh;W1`NH#wH{H;_k?&H<dmo5$0&IoG7rt9{N|ESH-`**I5bA3uV!ZfU5E
zR%$VGE~lWvnT|^$yB+4$6p1cu1Wdfk5syEA7XOcVg9FE6O0tW!Bjz-V_}My1zy@9f
z$AE%D-BOH#`A7@>&ST!H)4~SWh;Z#Ja|?0O<D9f4X+Hn^AEsPDtAnMgXB6(>R<+;2
zp?rG?{9x_cCIX0i5K*UNAicS!n~9gG%YMvQBq@w;a9{?#pocGPvVk}VnuNh!xRQ{3
zg5+n=X>7+hevY%y<ZRoz2q5%0K&8@BpX68B<kr;+cOXn&U`P~bub#X1(+^AD3HyQg
zRpDqNvA|4}yF)Qdv0`mO6w2`NUOdazWmp+4#)0iKc3XS%Xb2OHrl#0Hcd7?w0b4MM
z@UY`O68`~Bu+W-aFHmCV^#DM!tduW6RHVaw(|{;>gqG*uS(TaGoV33Qw?qX+>~^xU
zgV+A(_a&Jr-F_6#dHKiHoO%`KkB_*tpGqs98D^fgAo1-n<1Ry?!@86ym@+w7A|(m{
zT5w^J`1Z8TpIac1KsHc<H_O805zJFiEQiY%MRGdEr6TFA^tJ@+8sYwS;wbaTEJzuX
z8Lqj~xb@brNx>1-Mxwut&|Z=^zO#%LLw^fmDT{YSg`2CC?dEV1X28`1nYL6X;5~uN
z%$A^#+MSvBeF`~&cSj(;#>AKkuumgREM|pHB~H2^{ub2{KcQHrLFyFsP3z+bjyUC+
z37Z*OJE$`S-}!L1L}t%?Gu?JV;KD7@vQ!=MT)Vzz>F{+m9UI<UrXL@ne~au}rjzSq
z+lhvYF8_vYL+lT=#O@t=t|Pz3G4?yfKB?ss3;<E0rqC9P-Q$(wIH~K1K=Df7BUezj
z^(v0o->8g^jd24<=&oTu|H~hZ3oI#6O}6Wd;-W&F44Zyw@Y4R4+V$O`=sk<Iv46Bk
z?!e&EE_c!-MN8$Dp`{bhz#dv%h|5DB&=H$JZVWd&AwiMAEdlYofkq7MHW<u5C1nNa
zW{_-a(<U>gI0NSQFRO$4?iT$6Xo+?9Lw*NKU&zLIgU<E8JS9p+H~C4c<~^9dS@mFI
zh%l|eeK<v(6;_%Fabnn(`=R)b9J!Z8qb@r;BGo$$nHe*_Aya&LPb{IRhB#VevnOk(
zW>TE3upL6ZX=L}or7#F{bj*E12fr+98{D`>8<N1tdT{+?H;YpAtjSD8j32CqZU0o$
zvIl60OyQg*z7wutA)T-lVw}N~Xs})uv6B*Z!Nh*y$U3B8KP%&81+$CS5M@vtW<_rp
zSsGtG*2WhMjF{$i#RpWqMFjn%I>;0Fg@@Pc1iK9a6K>UFfgk;*WKnPN&ZLyfQEHxc
z8}}Mb0~9~Sm^;}pu}(!jB%elo+f;~AW(+AOTy!H+e`)5iicce$op3s6wG^htYgFV5
zb=f0C7EV`u8a#~DOQb8LM-G8|TTz5}i6E_pldoN>8rk>XCO~D;{VbmCA5RL1p!u9&
zry8<0W*D%vH45zI>oD+3lUOi@Q%6~ik~?JJ&@A{qwrWOL{x6(;Kv4FD&Q9<;KLpOO
zatp2ipNo4TWeQf7L&Zvgh^uldjlv?RgLBnmQX?bj|0{xaWTcD9`+VweKZJ~=-9{>p
zOOukev{snjL_!I%_VR-QBJ`RIb6o0k<f;Q4ZY8qvo}PAKlU5;{H$gzb$%+|Cqs1+f
zO=2<eZF0VlH>t|9c^J~Rz$l;qGNh(|#{R_?+m>d#x&$WJcGL^u#uHqBr$1#a9TXRr
zMj2=tHuC$e>cBNi)pg<Y2rkL@JVmuCoF#McrE|-q(n;fU;n2CVNZ$X*akBXhp<95W
z(#k|!%O@d(TMSmJz@U74>wq!LQYPq-9EZh1JxD(PqO?uH*KM3ZP&P176m&ohvE0rp
zU;nTx5X(KIXhu0_ty>BNBP9PKV<RsabVuz*gd~3|PAk;rxhI~a4=ZQwX3r3v*d8Ye
zsAR<x_Kf+kvk8(R#OHQ+0X_0fh$E*07sxtM>8+&-sUcMo<#cqD?O5E-H4Wv09qN0a
z+3mo&0Mw|&i?xAIq@l(w-jo4fS#`O0kb)C<D|n5YrNAN$K-G%fk#V3G8JS|a7Z?`A
z#y-Wsk2Co?JxFkZSYdy98hcH~0~!JX3s)lDVS*XiQr1S%pag8T7^fRMilSf)IdqFp
zRpmwCLc^y;ifI@@-09!h5jZIE=qtB=Sk@_RJ$MolCsNa9+;vK>yX0~lR@#CPl%VMB
zWF-DSEJ{)Me7e?)2|Z_N`@L>pSTqTWu#XQX(xyv79zosQ3d>PW!G_oe)LOQa*c+|d
z!u+zSH5Pma`bl<*E)aFG%J%S9hZ6#^P2pET0-fvs=F_Q{+?78=U45Qm+i;fUyB5_)
zB`q~bdI(sI6~T0e8a9YJ4o+PlVmr*p%&iRnCU2_)te<Ppuu90k(UC(>V{<X#A~<X*
zXD{5P$N&PcwW~_Z54Na!iC^UUp<47_6^lv#G0_)q<|9OFxR<zo{h^K24W75EnO<<j
z0A2?7M?n-LLHi?IjTrRGR^pd~?2w#ZV2*Hltv8<6+%w2+;_McQaZU|AxZG*N5@C>`
zf{D}9ZIw_Utt%6zu5R?{LdNhV^9(3^>j8#c0sNKMZB=cxVBSai>C~m6>qy$fTED(I
zTo+5$@4b|kR&yu3(s#+=oJ)+&0Vx@RhGh#pF@_yD7{V!joXBf(yNkqBm6pIQK-e@S
zpo-&)>?J~qx^BWK;6XWgd50}fixDNVfp*&>38j8HZ3?g|S5!2|Vxg|*>|;vaE3`Dt
zCp^PmcXFTqtq;oCGgQ@)_Ggl3-g^0C3?kxCZU)?L#Rb+`h=Q0Qq_O-*+%9mM^VCov
zs30-&8=J*6Y@di-hA<(~Vk9_s4xI<71Kdz}_?@i<ruEAdZ<QB?{Kr03HtaD}ga`I~
z`%F)c1HsV(>VDMwK@f%JFg-P7T1CsCJYo>QcuLqod=_#=T8g9NKllXMNMVILOmb?w
zS1|L~BsT@!4TLEzvlc(ZdegJUgz_P1xg5AX?en{iZ`zVflm`V;{ItpJ%78A%lF@8)
zHYB6XQxZF~<C3xLx&F(Fa9+zZW~!j6LQm*@TY2Q8c_=w*dj)A{LhnAgU|~KZ<2B4a
zao;^U&x{iyy!DQ(R&Ey#hdwXaKn_UgRa=l5xf9KvL3`v&PD~hoS=&1Euv>~$Ik4=~
zNZPb*ZLCxnr6SxM==9T*+pq^cZ{*i$*VL&F9b|M&-EdoIHL(I1hAG1tszTc?quzOZ
zTIn(3a2^f+@CB|Jp)UOh)CXo*s6c)YOl>_AdcmrM2+6Wx66(oz?IjqMaDYGW8Dbo%
zFevPi9TT?UY^3h@+QEm?Xv%SVaWlv&)RE`Dswj?tqTbStCLN@Xm`3hxW5RO6SR@4B
zI&V;8$2;N=Cq^p%7!!;|GjbcTbXZBW%u}&xb<`Z)kZ1gHDHeNnj;alH4&ioWqzrTN
z-hZ1GiC$XaC4qkZS3f5^3~4?D=I=en-GK+ci`EWu{|5<2m^v+9k+PiA6p0xm>|jSV
zGB`RMA4OtF@C;G%7diweTf;B?Bh;2)z_yO_hAHgn8(|l>S3KD}L5wA`IP{J2E-kO|
zgnB|rDoCFp7fmRJ%O~9KC)D}!A7><JXzLOntJ1QPiWii1h;V@I6Iruu*$lZ~=^`Wp
zcR}Z4x#YB+!I^LX(_|eQect41WikOOU+8eWOfbxe#!8?k9wbeDq7?)Jmgpam9)Y}6
z{kG}LTvqirx#aT3`#5J2S^T^V#gn%Qzx=BohKa6+9uB2nDK_vn3)6h31y^(BeO!hY
zQnuKj(_AZLERc)`x=J|T6FsOnWDaI}3d&)|0QZQ848si;C~M>=%d{<o4=>_V?nqpk
zZX=6SHC+kYQd$I>{j7Is+US$p;9+FtO)&CV`S#BBPyGvmh-^K>Y#C(mB1t3h%^wFq
zG>5puS9$NVy=SO5mMZyJ5)Q1EQQk&|`PdRrNyqwfXyHK`oVJNox#2^IAY>o;68L}x
z1Q2UC0(u29bIQ7OXF9~p&SOg6r860=xxC978RRsB{h1H5?-%otS{LQMg{<cRN_Ozg
z_W;a*lLAs|!p}1{A>{54lL8z=Gnk$X$eO15oDa6w&OQtk#}A*FgU8<bnQmTs#9$mT
zd`OL)v9KW;A6BJW?hfh&s^73H2e9&9vwQYoYOh{Ld$(NWWb%c}X{g6SC~!=RYRSM;
z9yItd#oZECjaFPSeEc}W-i4gBxxi>4uDNuBVH1E0v`I_6#q^P;#H2pCk^+*Dax|h+
z39-b-Nm`%RrjiZPk$5a!>kSJiS2Q{`PdswvuciC(5w5i{CZ2pJ*ui0Q9R3=gAAiJ`
zYAh+c;g-d`6-lek{tDdO{^sBSm$<M}fn&l{ASYOAYS3e@oaV+zTY{`QrC@M$tqNlg
z*~Jc-em2z&(`S1h-(VLxYS~Sk-i-~FB$&cgRdu<mNWHC$C)i%Qa%dfi=0Li<&xTOl
z*B^PSp5@5%Olmq$b1<&A$@u)CGAU#V+Bm35$CfI;kN^suq1;M4Z@?@G{)73FJ)DR@
z^RdVx)R&Y|r~IKUddwcCqd9?yH`Yd|#RxzwHcoUA4?>de9G-3KFg%9M2|Xv}cJh(e
z@BhC_&8U7M@H)*PFg_9HZ7Ty;5mu99_Go6WZN+*ud(`(iv&CTk*$J~JdoUA+9(f7f
zYu{v#-K0%_!hSZGj|+jm&tQAoE;_pqL6BMHmc^5o=#pi^lQu>Zw8fPRrB-CJ`-V2$
zj>sKa3p#$*|69!o?Y8}_SIizPWW6P?;AsmJmR8Cb<ui6kZ)deY+Y?Xw?R>Vq7Vr^S
z4^QQ3+DXsXRxr}0&RD~0)`6NHz|x>dS*^a4-`LTk^EgD?v`S&<Qk&9V#I3`uec`T>
z!8_M^q3`&)x}^*d2KTa2xX2>3a7F7eZ7Qd-#(ef9AIcR<mRZlX)w90GM~5u$Xedv_
zV`c^ngLfKJddR{|!!6}=?MSam7b|CDXk%X1Qei23?KdA0Kbd;zf*Gizg}fwdcy}ON
z`YVshKeMtjFOxrFclZDeO-}zmb<Ofz^3?`LU?|~OdDHmXOTWS2#r!nsf3VW;w>bs2
zK~O<Eq~?VIB$D3f5xM;FS3P~}Gy(JDzmq>~z2@52e~nD8=sN)dklVQ3eb}0P!0P>;
zakb!m*H-oc&$`pIg)2_08$^RRJJW1VngZs$(i2|9@$woMPY0>ek1dGfZYcRIvt}tJ
z%!+^_M4H|ss2P%EOh>{H^3~?wi6j)Rfh5S*Kl=qd=lFm4UzYp->wiAK>n8br*{Hwg
z>+k*R@b7uyjlcT%m7in+=_xOW7dE_E6$X=ix!;VbW691N+pL3@uk1pu9EWb!;3F5}
z%qPNZDbq6<T#Qe7THlVPg0^I6=Vu!UmFEjnR!KKv&4``zC}C+^SaNeN`;u8$<W7>a
z@%Ew6Jfoq2?oqr`56#|@8|Sm({2PIHeK0~K?7SA+O2wYp&5VRExp{NYvFvzk&|L}g
zp&cN-WTe^~=EVTHX-|b~CkuQ0;9WZtYC&h2uA`%o>1b9vWKaV5E74g9a<$LVjNww4
zVHu58qokXaTstFjLmIV|x3LGMeBt`X{%<7M3~JNy-Z&Ozj<vB&J)^ZVUi%cwMx0~R
z)oRBse~Pu9*?37Vm8PeDB8aE7J>IOv8^jm@*cHt!ijJ8LJ=V@Uq1zK>_ws$bn>ycz
zD0i~8j51x&_V4PSzx{*lX7DNm`Q2HinG65S#DY?8P|(OIkrpH!5^W=bas-pI1E^11
z5wjcGB<JTLfz59kVXSJd(+Z1vDKk{kOJ(XPibIa484LgVStD1H9k+&pqN?QLcBZ5<
z=81w@sD@&qR4}Xk+r2&9GyRm;&WvEbvm*uQdF^&*)Y`5&-EdnxA5n{Ae9|?C+6SO`
z`PVLFD(y9WfurJe^Mp~I<-@C(>V;78woct~bER8z)!C%GUWn)ONtBsiMnb~w{=Hgs
zqS&~=h$Gz`33A<GrzbI1?V(X7>%|!41xq)V3iGENL#a>w-ge)K?~m$*By)^ts}SBF
z^KOottPPKb&zf2-GaSyltA=8ZT=%A-Fra`jr*Q=?RpMPfcE#w+6@Q)U#N7+CrEuL`
zau2$W8g#;TcxJJ5%J~;gX&a|#o^;H4-3tfIwfmgp73Y@Uc1}8Rd(CP8E5`=oJCQ<o
zGL!09PW2^vbEy!Y@EoQ7?aK_teZuJO%GRDOc&3`44!bWq*$47>GXyO@+8M|Xn8obq
z;LyIwl2x|CvdBw&f8haQ?;sAL3VI14C*xxD2hL6Ao#w(!JbK2`%-TyMYrzBR?KtC&
zMpK>8^oDvIZd-fRDK0h_!gIq}l*{o|X8w!j(Rf}(m&0Sx!gPG-6({2vao=kA&CvLh
zuLaQobGFzzSnHf|5390ns<F8)GBVAb>Gk14K=FBUIm+Hr(K*YLL3qN`JSPp!#C;5D
z&7KQH;7{A|!0lxtI3F0?Y@K8^YB##d_^hY5w-@8Q6VtVQ!kAZQ-0-5}zU?J*9T0lK
zEIInfY$uM-2Mb~Lylq@0OBI{lGv1IB80JYE`CW8A_5GW0KO?!eUJ6yVi%&q=P`PgA
zT0SUI@~PTJa&tEHy|A0bv!h4xfT@+j>@fBvrVs?j9kvOOfKJLnB}xbIwWV$6XG2v|
z+r5&GGb|y2*>InU0RXTLUHesqRddJVHlK%9iKeyJEYs7<8AK2t!atX$nC-y_S(#>B
zvf_*tfY0j5`b4ld+n0n{qn>2AhX?C`Mht<CFg57slBESq_0fx7uxgq|y(Vs|s0X8w
z?d6X8zjswT=>%hT=45cvSu#*j{@)lKLc6s%G>%4XXm^wc#h+I<89m9%PUeJFcQ%5s
zX05nd8?WmPv1lj8;no-*9hy!%3d4-zZ)2lWjyT}<Pmm|KkDs-Q$&RA^teKc*DbBss
z&efdl?N|QE4x{epPWoB^_{nj3rK8Uy&HIOIgDlC}X9n2(M0d=%w2k-dL6#NBg>KVH
zvAhuOfQtF)$lEupX<p4G2AJ1X-BC9wLvw^|SLr5p9S*DH)K)yf2SGq>*L2?b?{CyW
zM*t5mXL_awc=19r7`4Dvh0tRYO@h8+q@qkwS1RyIccWKPq#FTiD?S-z7a}7E+Z0Dv
zqO2AUPin@f%IsTpqOLm4GDn%S9GPuv7Vp=!m;2`zrjrxai;i{1cuj@T2TBeWz`EBw
zu0J1IA4;6Xx4*Tc1sVXX`E5q`^kA#BeF5j#&bBQbJKvs;y%Fc`z^f<Opq)K$dL_%w
zmRe7G!LT=9$wHz}I;G6{3+-I#baFBY6O62pYv)#tq@=QKXA$zVbO6R(Q}Y>wGHX<w
z?Hpf|;lnf8N#v6+N(eM;j5zout4?iuxNODvG9-k-f1#ae>-#1V3wCJ8(e~kK3E@jg
z5(6#yW7y6b4&u74y=~q}GWciXc;xJKiq4MH9DbI!(UzW#s3LwTqYZnir1M_L?yB8>
z@_<<ir$R)K=st>=w=>M=mbT%<9aSRAJHhw%tXcxj<g1%WkQ2-^e>OE`@J(0Pvr+dn
zm5jC6%B@G<(WsOwt=OfUR;mppUbN)2v(dMn+O7pL>S2@?0~3_o&fwUfAr|zbqQWIh
zW)Uq|+fcN&ZtyqSf|01KhC77#Js)TzryVcQ+DXF1A_7N+lfY8(<+KaQ@#urj+hI1*
z+PS2yx1BJFazzAf?+<_Hs^-NnI+?D1koP=FCV@I~!UkqvXLtsFiM`MxzG)(k{E>et
z`iZ3@r`Qh$=<IWf)zHU&MOu3YcUM#GgpUv78avcYbZyBVNpdRGBtlxUN-Gu{#6a@w
zsQOC5(F(u4Lq3PdO-_^A4*t(GW;HmbjHa}h=q88*4@230GNWM>I6dw?U&uNq15c&E
zx|B1{C&$;#=Upe)HYDL6g~v0Iq8TO|cO9qfJ6@6vOE)d`#~8WMC<c!X8G&|Rko(B9
znbGjS`Pibz{G7Y6;+c<L4sCyU(wzUmfVnXBls7cL(wtxMP86tKU+r_~_uF1Q?aW6n
zn^&J)o1Fho(ShKEd!o>Nt}+nRX2KIz?Q%2|Hy?Huj&*A9%x?r<_nu&KKCV=eglC<B
z;PA5durn|jCQHMA5&o;;*%J%Dlnf*%ocXUg)|&HTus*!7I(#3BF<<)%!r%;CI1&EE
znd1D+LU8=l?D4PkAAfRr&wZ~X*2}M~9CXa#FGbd>u^ueeR_?6r`6c5!g>At}YV|U$
za41wK3iH5`1%LIR)4dyCA1+QhM(vby!uaXngmt?!zigScsd-H1$mt+Bap1&3ug`fl
zXwIInz3!&7@HOXhG!@Tpm<x|QRjYhsc2xb&RP8S2?fg3KcGinq^VU1jT^C9VtHp(F
zC!EqJhgXdg#@(kK!@*+C-%<XGHUE!7;epkcf};yi!oOi2|Ci?aX-^f;4X;*~4=3fT
zQRR!nLu&YhQCvCLti5c$aA4N?_@8~qVCx1kxFGGL<fx~@(5a=r%*dY@=&)+b|Bo&k
z7<BH*%Zz$vvU1>Vekt^s$#Z@DvTXF74m@7Aup%$!*As@(<<I-gCA-Qi@4nky4NBqa
zto-Y$Q#<%pBHv`D?>(QKbIybj7iZ6haVuI_4MsmRd^&la_dlH+f3D9M<vXnKg#muy
zJ$WgMDe|iH*IU&`Z~5TSjoK5=g~9{=qX(R^aAo9#@y}MhhaYre=W{fqtU~M*-PP88
zKj1FcU?8rMCwue{&Cp#vMomLzw!Z3r?&lJ|qwkcX-Pd%y7l;19JQW1R@Bg;>RQ$k3
z&3G$WX%#c0c6E*{`BRZOy7J&NQT}&dFBG>Oe<9!bT(J859j(U_XL<k6F1YWGypWGi
zBuiFtEjjPdK<^igcaz^8JN#y1oY}bj!Ek={^~t^8Pm&kaJK^Q{h40n&$Irx9y$==N
zNLKyu_<!!kD}!G+{o39iyz`xL{}U_TQ_;bf{FM>Lj{54U`Oqse|8VrlhmugKzUx8I
zs=2fAXqB4vQSQiGI`*`KSjvOlN1|`lAEg)yyIH)#XT>YMxARB}c)Y?qBWFcD6)stL
zKW@svpBu+lxd=5mzN#KeRuwltE=?DWoHB}`qaI2|v(H5O=*q9~YjQZd6dc~2Ssn^c
zj6H8Zn0Svat7pRBO+3Jt|5UV)d-S=*i~gYRoEUUn$8kMpxZ~Kg_DmPIVdVSXjqT@p
zPvqybwJYI+2@GhdnP{Wi<KT1eM9n1dxO2U>;!|zVN#Ygy124xbeyy2|td88b&GTx@
z`6d5pCtjK&xjnkmJih7|_2W5Koh<hnac!lyvzm}ANH~O!6C1P1=nKbcnb%g_@c8Q0
zfFnsthM91+>Z)IRPCc{m6Qgmox-r{%C0X4V{p;U4URv{KiwFHU^4|1Uri-j-6h_E7
zd{YO8`N1SG<L-)o-y-BFXzrQN%Z(OtLG5Md!Gx~wPEyr7xnUTyCB=;#e&A?cF%z`k
zBh7W}1d;CHA2MO=c#hqEy_h+^N}8BkGc%9soy1XJ`ORdhx6Mv3a}39d+agnYe#Mst
z$;gPit5HpVDsI)(-z16lrBz<qeYbz-&;O0)&0f54#&_mfZ<aj?7+vHnvv2MycQ5AA
z0DkSR9Ao3+N1s#d^a;*Z3+~%BnRs5fRDJZ<d6wFP$un_mUk)>)D;9&$0$N_O^uCPR
z&17`tp%cB~YdhP?^ZD=#$@7Vk<Ffbh#A9Mwv}Ap04<Dfi>S^bhWHp(S58gQZXNi@(
z@L(smWW=w%aHW><9^HOCSJRKP$15D*qksKZpB(o`V|%WD)vud-<8#A##M11n9)lBA
z${4lPa^B<0iq&H^?9Pf+%#0_cl^KQ=tolLRwkhOEmaS_+FuH;;joQn-&xEG}5AuI>
z#aG1)b&<h+U$NrRtPx=Wh7-0A;l6KMCt0y>HzSSZEGs1BJ;y;}?)#m=r40tGJ1^v)
z3Zvtz<?y)kg4M}6wZ{|3*}imPJXuO==RUH%G40o$d=DCiy=?r@_a9vuT=GW?!RpB9
zn~Ccvw8X2i;A2qLd|F8dOz^xvbkMP|^qf!b1~mzc;`f7~L=L=b%YL*)su!BcQVZz^
z!HsemY`jdofg>-il7>w<KB20k_1b&pur``Ko+LJQ<hUc6aRL2!iqqZCH95)Zv85y$
z<uc(UckRhv9^d$cy{vxL&997fAM!_6II0I+M|*U8+@rFicJ^(5CqQ4qW8j0?&eE03
zKRa5uC(e|z#@Gv<Sv(cAFNee&?COBoUO84|M!2!$6{(1LC5kg)DO`&w1!jliCANM^
zJrivU?)$;889f>5QM8nQF?zx7oW9_VCu6z$zMbT>z9joph%x`+AO1r9xBa8^w`z?b
zTMt47(mbhZnRcYsVn@{zMIgjTS|1KQQ$J(T#_IOv_G~X^v~Y~wUh*`kjaD}k%sJ=X
zQnWg1_M9dPjoTJ$iiZfgP9~b^0a!h)V5;_xFuY^dh!=9_%?G-{a43c}r|{vywTJGl
z=SC^9z7pkg&fU3!1M|Uv_|u+Di8te?V?3nBtDUNuBT`+l?`E$?TVcDZhkKqgfJ-&&
zjo<|vIFQBJiIXBr$fyHz)&w0ByuT7{Kbbfh?_^my94z8R3ta6~ay%~2ziY18eM$11
zVI+I9M)2CQaXxmI!U$Gs6(p8KBbN)gzBhmR58Nx!<K~-p%kNK2zIpe{?sw;Z7{s66
z^Rj!HKXg9tJlA)7@O0->&T`+Ow?6l8{%pB<=&k$yU~{>7d-tz~Uv`&`+hh6tO7wj*
z{xpARMbEg`pFDW$fxF)du0QGBTDbeI$?H$G9;N1#H#s*u75?78`}w^*(eEAPx65nS
zzi{wYyLQ=4e;?qkrvLZJPu^-*uk&vAz3e_R|8)Fm=Vf<l{^@ineY{ymo#?yW`MrPl
zsqQ)EL|wY?<xLjBVt(iXGvs}K3wXi%JjWZS?=$@JC(`#>z41P)V2$*B9=#mCSNq>q
z<FU~^lCzS&$@S;F(f96Ild!}K(*KHfEdLR^2F=MPf2aK)U%VJi1<9xX(sRKHQCs<Q
zDdIN)`M6OKfBMh-q44#~TZCx(qV#Xuya4cj;}!B-{l@?B=6n&x{M{EHRRWarq4JOE
zKmCtCCARG|yUjQp-&@*lgkddHg{&kf;S%unN<sA`9qW{%Ml%F0!($K)yauXD#q&d^
zIc#(@-TAekHaKiJW}`-nSex?7P@NBmYLrC|t_p=ezvzU93Y6)XLkpW1jQOc3j8E8Y
zYeyF-_<$4t%CiYXl~Fru1!lLAeBeG{S7yLmGUf~4zkjlwiOC{_p*=s<(KP5jGY<N4
zN8=zIb!=l8){o-JP*?4Pm@cl^P-;zr_ncG8GGWGhil`j`PY|N`jHA(#aWWy9Cp+vB
z_I0flx?rd=9S$@{g>OfLv+Yx8FEw(|0lE{J5R2H3OO<VpF<<GyK>6C!g%ZUuq$%ei
z2lD!Pvj`ty5y&v!_~fLpE59@y8lg;LG3ta^#mLHVCFO<TqCu>E2Q-eRAR!Fyfp8NG
z0^?{1(^WbX!PL~kbEc7aj?QAtq}|Qz3l46tWk|B!?$qq)uHnhyqFvR^_WS|!tGjh$
z{wC*W>~-~_hQveNI73mY0~gyK#CY{hB2uL*URF&q+6%&^>&p~eN1b4!C~|x|4)v0q
zF-Dv#p&hRi0I7o}wKB#~GgisnIrEt5*o-5X#VCalwTCARsHpQ!G3U(BCi9nL#~K`t
z3?>7%;}r`YDK^{5Vn8VMo%Nla4f{`~+!KA(iTG$7ewGD2P%s$McT>-7RCS=3`=DUJ
zZx*|TWS$(xzD>F9wc)UvDM_r!xeh}sl-6-$UHFuq3qc#Qm2q_4br20Zl|TZWb}nfP
z9MQs1Qi?LFo*O>zw3pY1h~JGOERV9_nu4!>Z%5zD6LW>(!hLTBeLv;QUyV-vvZ8gl
zF%L|9C1AJ0%aLV;nUm(w-AR}+%}+MlQ6XoBLuz3#Fn!tAB4#>){M%=OX;f%9+4=JJ
z1${u+*SKBX<><qqsp9T8F#3<oFMP>#zO<eU|9dKhhpM^iyYso8*)aY>&>kE<t~;T5
zeA)6SN?0?U1r;uu3(q<upFQ#6V$0<=<JX7iEZD0<T$|L94?BIy<uG=WZEASl`ih78
z^hq1;S!1|+7RpzJYRtIqOpu~(KEQnhubA-{9pk=uy3>w_K3giQ545+nJJ7)Ku&S;a
z+S_4tYIul9QSZi=L+|wDKv2&;KNYU3Vr-q6Ur_7L@$Hm#?Fr+Owc*Sb)tN=rUQ6PI
zRtSYqRMF*7-Q_syQ-AqE)fYpkxp?FZELYfrBEjWDGB2zJU9OvOoL~q-O>>GbPY+I#
zUO)~}uHu0J1zmy>gN|r#=Tz%XrY|>dg+i`GXle}4)8;53dGr`&LfAf^yOE7Wt-Z%G
z5-ZdfOJ6ht?b@F{OWx3)jzd2Vc^%XVOb?`zqqp?{Y09((62<X(a|G^=fdJ0sSce9&
zW9!&FZ(hnMqEAc&)-;2RYB6~Mh}fLchGSL2r^0b*5S<_+jz8AsLlT$9yqEjx9ox+w
z`@t9<xhL*q<n+xK9T)D%(S&3x#Spu&E3Sq$=Z$#=p_Vmm77lZpsX1=R()rQNz=YaX
zCIE&AmNo*$80SJKDou5Yy14RL%v0MX9uzObTGWqT&A8oXr`=B)N4+-1H0TIBwxFYE
z+=y!VNt`_z?;~Icv{BRvgICR!V3f_$dVsyq+O|P|Z-z;5;N}*Lo#vPk1&7{j7{$@s
ziOQVkfUCLliJ1iRdtNe+M?1RT#CCQQF7jL0(M=rq-gDm=POkm)pE*B#@B*pD`S?Jf
zf|fTs8dkE-!hxXe=7Qi*G9Ax)!*CO*_#k$+OJ=v8GfJWAka%Gis<|$#mnW=srUun$
zBn9p%X+^w(?zEtbowc(L`@{iBA{PdV<ktn5FHj%banuNYZ5dp)&yMM`f{=~h4s9Ld
z3zLYYaWqcf6EiZBWMfU(XAQGyE^ITyk_Ez|Pd*c9)#N5~F^IZ<n1q!~d*P<zvF<Ej
z<6bkDCyz%X$zalxTkM{R3_cfuxEwlR9%;)M3GCp|g6D*1oKIcezGTZmGcIn8k1^U<
zunqYG*udk15Yyqd?>txd|0sJO=r*qV&UXeHDPvcg5+fL$pju|;a!6l7v`kWr7vW|T
z&TvExA?P3Nq&#}N4GGIC!+o1tj@zgDwA;Bem*fR86#s;FnKat~5Uj$gnn<$ZD(TBB
zNz)GPD2eT)d;EHOP9#~$s@c9)Qq-(=PkQ>kL)rP)raenrAV>m(nLGFI=lA`6Z&*+9
zIhqfM1_G6bK*X{vXc)GjJI7EBM(p^ipkk6@;7rUdd7Su)z~|C2kpl(wa|j9mnW2wM
zaF7QBC__cR3fSi8cYf=KsNR@<(8AL$&ae+E%}inrjl46L2Jr<e!x)Z&!v}3VqQ+ou
zz{_a1eGNxz69~BAPF9Abh_EdPnU$=B4;XBji6DNTP9BPxoFrxHrX#hf9F18Q!uy@u
z8#gIbkUkVR25zM?r$409A+}#foWf8t_|Ma`3fiPH?3;C9)rwZKRz1VUm=1)99v;D?
zE%9)ODxyiXa?nTLPjP;o>zFBP6fg7%<QX*{Fexz9z&FuS4CVn8Ca9N9-I@B+Wp^a7
zOXh_R#We_5yprq<qa8}6&G>ZxWv^Q*GOvW{MA2lL(A+>qvAGaipeVL26xW-z2>OgQ
zG3R+$I7AAQrWFL+INy|3eI>HgWz-oGyy_uySJ0posM+-fB73rwRdL@W>A_EIMM8`e
z=bu8+S+doLrO+SQ>fKqGgSWfl8P8AA6_0rw#68v(lq^2VF|s(C(aL2YQpA|22cZ6z
z3=yu-$()|cCdH;;WD;jeYZ5~N_;NglL^a%)D^3$~5ggc?yz+<d>f?ChoX61n#H%`~
zh+xYG*hYT>A5CHf-EsKK<LJ9X4N;vusiyj<sUT2;Q5xXB$VG*-{UU2_HPn0+w=|Kb
zp<r7Ns{>%oQbw(qtP<cua29<YC67(Viamqd*8|3G?f=kO{yP8UZ`*sFW%qISxO>rh
zj16O8D4EvO`)J5k^rP4Lymy(o7xkC*<}t*B^R?0AnePT`V`aeCu-ofh^k~^Gtqhmu
zhs$>KYZF+%R8oh}>ql7W*;e#1Ae<TN*`C8!S&tWfLGK>h>5=kiSbd<}JULb>Z!hP{
z9U*=2(@Wv=;$+A9a!2V%P<k}_+;CYxUG=7`4}_=r=kx{Ei0FS5i0jG5-;~HgE;_H*
zG#Xu>S{DK4fZ?NT`ea(qJ{M+|E|!Do`HNHA-}`s>WLx<g-r|!hu3NV9=RRO{<>oLh
zS2fnAH#8Pr<5l=|<#Lhvk{3>%YAvQ4R_-t%FOLnC>S;Qp4*}*b;JO$hn;`-dWvf(8
zh3C9Sr^;GXwZ>W7^B(y<8m1b~aH(slT;H#k_2`^9N6#&FUktlxIV}A?P3JC_Ef8yM
zvN2Km&h$hbv)0DK3B7EFbRE-{(s}($Ij-lHKBq60%?}D->GpF=wFS`G>p``rME<B+
z%IO)J{dYN<IX{+be7j$1=7V($%<3=Q7<??cd0<)ZM-Nz+mg<)N6Cl=P@nR@s_0|}{
z{u9I&OD4ShM~|A9zZw7q=ZgW3i|G;&Ym95h#_vK~Jf4YHfcO|JTQ3THtFjaEo6hM}
zptqv}Z=$hE9>Dfz9yyk0A_QXqxCKBcv*`==tqae-<{oo_=7ugEaIFuE!7lgkcUZDI
z(43s16+EvV^VIfh%v3U6QFP5|bOCGD-E!AuUI$6buzDMv0gQFayPl?3lU!@K!?V>c
zkF-Aml2vchU;KZ?+FEa%Wl%rLGAo{ko9a9T4pTDg|5x^#rN;j4e=Z&sr$2Z9#8d0)
zj$-EK`g$X~E6QJUPIomgeSJOOLxEQ`b((&k(pmAG0PgxFar*jwRTGe<@I<pV6^R{(
z0CIrqy7s<@@2vNp6i#-5>L&!93Km{%Jo@dwdiNfCUm^Pped$e?KO!n_W<vI5=3EBV
z123EbX_kRI&6pS_rSXr5j9G63YjS%*H#yX--Z<DHuWXwD?R9#G#Ee%-hOdh{k(?X3
z9AH@f0uYdQ_&eb(A@brjHcb|dQ`vV-iR|fJ*zw$}M_H%gLJF*Z%5$h+cR8>lwipDf
z!(>0mOgt<anLp9Nl1`t-uE}Ek)jEmcRJPVNBc|&yOd^>;&7c2+Uu;ed)Qi2zYw#{B
z^jr9-2@$JHox|6dj4el;%B~4DU+bCxlCBXwZ=KJ*#aO*aah8XxAd#*nRgPkFKup={
zt`5Wcm_6(9-O99>_2N{Biw8jlE<3dgpd7{=S487<=7N3<@vTZ>y>}bL5V*`)5rKbo
zd`l3ZUJzd3y3#kn&w)Ng!`5-y0jqki)^{;{CU!qxUk5KMi6>|SFLi$1No3CPx|Ojn
z;6m0MFyTYOKv_EuK<I1Y3Rik}>HEF>q_*TCz8fRhD@@KNCREf=yeuCxc<X%|FFxiq
z+B81JJyZ?=Q~;^A4{mV(*F+)@mLGv?^2x?`H&{2JP+o}M{^Ov9*#&%_6nJD-sC`R9
zWQ#0#)xufi+m!f%K=(!VUTj*9>aNW!Inp$x32}naUw>WQhx_34ZbLWVs!rxAG%5An
zxYQ$uKP+I=qU!)6N%ZR#jp5`m%fZ0njAb`KZZqZ1VH13^IEBo=1V;hsbKW>fUi1`j
zNrI|Xb>}Fn?2g_Lw0_?V>hi0#;>2}S7nt>lGePG2_<$_d9M2W<iAn*~^AOILWS_t*
z&gy1k&50qT>bxcdT-@+CQA?sQ>s`~T&)Pe>X&|ycxb^zusUDYR`cZ#L!aICU$9{b>
zF!T|mGJyOtOu4b_w;}40JmlSbXKBLAoYa_;$0XK?WQqmoc&!ERIMvNDv5)Uk@GuB5
z;qlY(oDf?law2=GZQ{6SG`cg@LLND`XaSIe7*xe?WBxmXf`5ydje@5KjqD?0O4OuM
zqX5`iIdTx~NkPb!s(*WJb7sZOTIaVX>rOP}_ScKEVH^}WD8_3?CR9Q*CO_4JWVSI9
znidC@WSGZFc?<E4-BP6u$-S5~@C3_S@&rBAWz>&OVNDG@-bT>`uf+BI<KAUKRc%&S
zr*|=9OBsB-o(zQdny89{0!W%5yr3eY6TEuLt%&JqW}a~m;w0kG5iqx&ZxAB<+rRz3
z5r)CyvdzGHA9jr&=(!26Y8@0HzidYlmxdt9C-gVh8*TmyWCf}-0>bJmrKDHw!Ilci
zIR|Bnmrbl+lF-6ygjWb!x$!Nr$*3ns^vtG87Ib~bI?<=CdKaqb8g`%%F%CAAS#i&6
zB2-bEXT)Unh#q8X0~2D&=`CUeaiu~7JK#;%-9A)iF8%H3mOb`M2>n6;gI+=FtD14K
z=yMJx=o;{DH7VtqQFjqSp(w0TidUdY(cUV~605VsGU8djLbxaS3V7HA^;m#alXsCQ
z6Dp2bP>uH>w^gQ`VFeQyZ-{MUsl!b6@^1*a-D0?HKp_!ixU}vNEug)oNpEGt5i!Vv
zQQLELcMwYhw!Lm?KyaM3EAc2x_{<s};z5^7purC2fy&0K(&|_d$hi3SSP6u>1`!ov
zsCalgh8lB=dQUeyVdwkfAZJPgMaSG5BP>b334ToYw8d8h9;z(xlN54{F+ImcpwEdN
zV_AC%&v-!)Cnux`9J?frr2g!|EkMID)CC%T;r5`_b{vTK=h0Y<>Oi^=;3R(@(!DeJ
z@Q+YzjC2?OG19$zkbjN~$58nlp8IpS@J}7&ffz1-?k-&ZUom993zz@NgUk-ynHtBt
z?{e-mI5(Jb`ptLHGOf36kmVsvQDV#uIQ-H7jMg0chyCw-8Ca;qE7pzoyaRMW9vEiW
z=id8|julVtK}de;6E^7XPyGg!d*g*a^~<J<e{xUukF{C5xKcPoNuh^^ybG`)odb13
zNZnQoCL0a0_Cl<tA3Kv^g~H8^lvKn<5)29x#7nR|E%nfHt6_$_y8Q)fAeSX&ldzH;
zvEZ=~ay30Phj<%p>87Ps56Ti~nQUPtq{xBDq15#ze_?$L=&C!C+b~sH$#q90Na#*Q
z%U#qzD3YJ;eYc<JJ7TikNKgs^r)|#kJiv7>)zm|6@IYBA$OtkMa1LD?1P8&%8Joa`
z=V>hN`PG>1WKDbB;%zF!1YO2rdW8a0N%~%s!b7n^Gd#gTZ^p2$drP#9M(MHgQB}ht
znLtMwudZ1q)no3r=|O92w)LiN?Ew(&C)N|5t9FC4=n^_L5;B&=LJA8y;Ltc}YmbRo
z3@bRQ%Ml_1g+ZZZpiauvG_zDQ*+5{{OiD%=6gF#M!Z?YY`tGqn3MUu5Y;_0=J11l@
zV^pD&Q$`rmq28QkFHryn8fc`%IQg{R+t5nu^czR-IlFx!#qmMQ)B{-K5+Intn61tw
zp|HD8U(_|@lc{b!N{|w-TDSxb=q=~afxzOtPeov9Eti7;R|2Lh2jC`n#`~6NAy|nw
z2#(&uVl;D+nxi<wK#o9I*C_X~fenQUbvhx91W({rF7?I8vdZ$Lg|B-b`fcoe?e@zv
z?nIB(r$%xq0XZ^V#y=JXGH!|=R5b%JFz`cRCJ})E7iIwW5M7h*?9+gyj1Qp>hY5OC
z4-yf887Wz<B*43gLxyrjP&Ju^a0Ui9s!=3w7_8q67WDK*9i<E!@6eWFk_IHSFX{`F
zem=jIWk>DZV=Jgu9k}<%kOB~cHcQUhv_<CcWe%;T_5KhMKz$H$2XwkarRoq;<ak!j
zo}=tVy(vejUh4N6Lw$6G=Aau56K!hAh733nZh}5IKTq)t;1vs_1ur^B=W`6}SE5A$
z*byQrjL?VfVI!=WesY19UZm+IsxRjrf+AWgHB4wB&g+e^Y-<BcV&Kl7{AYjE?%bYB
z9pv=Vs7-V;G+SF()oxQ@VjB@)vUy!k-=Qfi!lU=;;ah>NqAu)5AR@ZLiUAK>`g8iw
zWk%vZxRKeyO>pH^ToMXCz~o2g-8{;uD6e@)u=Qp-Vnf3NN~1&XsznR!jD(-eWe7fJ
zPtcEYM1`m9q?xIi8Y-BKYTd1sO@>^dZ$Aa!1#~(qom2y(Zc_6}q;4R9E2ARCy;<5y
zt>w_8_z<TxVI2oiG7>>_a7y%;z+0$!;OGI!g~kvKiMu2;UxYV7S$u@3q?CtNy-CyC
z7A>uBj7>9{WLA^V(y}UYv0=ML$>(>!+mKz_=XDTMmPUYIA(mH-Zfq8gdpu=pxn*=I
zAft%U^eP(b4oNZ4;+I9}Oq#?N#AG)5%s60!-$*!dU2-7-_vJZCrWqnobEu~gYITH4
z3?eD}N%Y{FzYB=+cfYb(L#$c5&$C?BbuI2g?R{1!cmW6udhIxzg>H4(gV=pJ<wLV|
zK~HGjfMC!gUGN~AHPCqRia1mri46jZRt@<jLV_rsM1W`L?tp{vGt0zkSo}5l%6ARf
z8F3@RQ*U|`%4NotP(ido^OXTLUxfItj6mh`@W>?3f=z7#4$Z|vV}fG=Y@vlp%Q#WU
zP-ET<*%$LaCSs9qqutQa<EIe>*(ov>lFC(MEU5Vic4a*AF+nO-ObI<RA*58Fin*>V
zvLL71ZhrW?O-F3ZRf%gkmNUkq&7GdXO~seP_|zhk%f=c!3Xt2Ydpv|D5`_un9~}5M
zVbvJQk`o8iV*z^+xDnAx$*{=3rdAD(M4FU`5v)i+#+wsSph^vpQuM<O%Atd#i0Jv$
zoEJ@Zerq25jRMLIY=Ah%SP2?f$cQ(}QzDF%6qaYanv%R>dK^8qX9Rp@O!Cj`N?P^$
zXj0`6ZxVA|52hDrK#fFz8$eVeCon>smO&)50#GirDLA>*gxk}EsL}{(l^-NN`{{d*
zD$GvnSVkc&m>{Ns<{&{_iTjB}DCpTesKtFYpoWUS8K4yl5LPsJpb(FbL0?dH977X|
zzg?}^d07gG=i`rMB!Eete*t$4OR4x>40SLfW&q1`mLUszlSmLFfy(yY2RD!G&M1YH
zP;5xtQL?^*(NFR!j;~~0bvV9gALI}^0*N6iLpaB%6PXTl+Bj+CKt{C`x?Lj(aMPwO
zMbL=0v~<+!-0AdaUX}8VYMGOzfCUl(DX%bJ&D`7IhM)<Yi#aWbDFk`HSPCB8p*n12
zB9!T15MTf}>m_uEz$637$h=9+4`Xm38U{)S`#qt5MoaLa>(@pmCFpRwsD#2oE5OA@
z3jRU|=q7+p-YvmDA%XG~n<UYx2YRRmVfV$ejV>K`%miv}qW6FvEBqgR|6ZuMja1HK
z?jWf<9$K7|N6^4Qt-^nP;;8D4AYvsMZ4k<%6cB=eG+FO!q{sA+AOsoVbdfy)8b8Kj
zMRPpn-h=ik(hVE&qdtLm;IDET-If&K1yZA8jtDgUJh^rLurEt<sBE#$*_ZneRW1c4
zVg?EPBuQfqLHjbf#Vwa|tT!@8Ae{B6RI!-kKty9<IwNtzlD$cFdPOW@RIg!~q8n-{
zAom1X05yt%Y1@WO9g!?n(V9Re{RAAzq+#;6ZHk{-b5So)YDQJ-q?kCMYl313AU|L2
zLGx#x<4CAZKIS<_xEY1IG)x^dL2JPy5jvG+uc&**q6nN-bdQ3mkfD42DZc7&o>qLd
zgvpE~3Dj?zHdUNJ%2$yAf{tGE@BDqX^O3<v_#Rd|=Q=<1tbvQ}ix@SB^Tml_<Cn%J
zkjr#GkT^n>7O9Uq)am8l4MwM;`+rHC_pS!5C!OeiCHxM%%7R)CEnPuK=>mOhDpN}j
zk9}M(w_;#DOs--1!&;u9NEAtxwa%sT#3XG1w3=kP+FlFKgfEMh;6)l%b7kHpsu<E2
z^wVa8o@%sX`haOnT5Y?iUuVG=^;*DAnB{OObkvEiMl|1OhD2a{PG2g0iiS78Z;!ZV
zb3Liju8y{x)&GMYFSDRKd_RU`#Ej7<Bb#c-+?hvo@8vPVi+b2XT32Y<3Rh{VI8{!K
zz%8TYek(N=c4w}!dOB?TwW(qm9JnVJ{-KjS5<u{Cj`GRi{P6i44@zsp{-^ZpCH+(*
zgzPiOU1Z&QxmtlUOy&eBe-9doV$hbO0R%tcIn43O3=-Y3VCPcXMM`T6+dhdWm=0x+
zom<i`0u+<ylc&vRuCtey=pST8?0ufIQ=hU2>uo#f+YC5cPc_rKBshk^2w30&c}E*)
zH<saUK;R7>?!N?q&qEyj6BM|D*Z&LzHs{wNO1gXOW>NO?v3B>wzXXA2*mNxSU4m?z
z<p3V5Y*NJ7xZ(Y>Is1cq?fq{41$`*m<Mv(+-dKCxt&<u3K6(Txel`dzpK~Uz^ExOV
zKj*Ej0fxBQv<iGR8;*jeoWzUs^<S9{wpE?&^{$BqIlQOH&vvJCp4a>QXUuEP=LiEr
zb9$Lshe}nh*d?s|$A5zkm$KJWPg95l|A(G&PA@!hcD;V;@y~#=e*D@EUCfB_I{1bF
zOlIwkme)k7p-tRjq88)n698V@(od|5i{vBX_m%|dAAIvrqpSR$6XI;H<sK;X^x4vL
zF6{aL6e3>!G6h5^X0;!>u7_PY>MkN+`DbBL0Qlx)%u()uY0PrVO6&&?-ULiQ0q)G%
za2tgL({2nrg)Ajdo;v9Td*fLG+C`vJs2`30>N*?jI2J}CL{(Wk45T_GrtifYtTQpV
z$xc?6UWIf7D(tE*fB^&lDmw>S*POh8jz1H_Cz^dizr%o{z6qLlU$yHGptEbql*Cn*
zq>Vj)3QJ%wyGXyby-+6y*Y@EuROj$!?hVD70-m=N@Gm8j9jP+#5XBvenNjyl&gY;o
zc>)M#vXIwXV&08Y$2pPseiU)p6_-g*-9)yJfHD?h-u0*cTYNq>{j7K9uO$=;WXd9H
zv_aQ7t%S#L)^ikB*VvW;2NpO0&(f9^ak@qh&Sx7$JD9|uXF!Nr-p{0^SI->%Q0AUW
ztWDix+xct3P~m_Z^IVi*GQJfl%mXmug7!KYB<siVZ7iVbM{ox!_AJ2a2IYqG7;F+R
zh?!&eEcS-wi76J}D{uS<x-R7(5!l*xTVs7F!x}Nn1Wcb!Wah>A>1`7bTK9f`X=ye(
z(?&8TWao_~@tVNdSCF4K3vuZokoQ_wNv2?KPqSD{eMrFKA~{=nMO0cUP!i)+>g*fu
z-kaRxo~1);{T42SJ5T)p#pXDg-xgD8WKN-;TQF1d@?;2Mh`_A6&TI(wUyQ5Mhi60R
zkmd1HAC48M6FJW~nRK#S7>0*!0Pa`WCxEfyn)EA#i9G6~5cSruDzZ?o=HHE)I-V#m
zf&UI<gXh-i#2t{U2DyxTPz4okK#73I>E1(P3Kx@nyi^K?1i!DkYqoSnsJ$oO6KuQ%
z;#KxoCArTXYXdXe;@1iD>#pQMG-|Bk{JB+R1Hu9yvoy)Ul6DOBr|!;B2;cAX8b^mG
zRD(hFqx11C8KC#0k~aqI=t$CG7>pvmGJ~K=HHiw6K-FHA9I8K~R<;Ra%dBWen4~O#
zQbEs}(GE_>0i{MZW8P#8P?Fup5+${__9?Nfv-OXUe*4g-eJSHSO}LJ<8(l}>P%DW~
z%nyJYn><8VLwClBgUMxOU@FucnswByrsg@99lBA*7d>tr)6t{kIpVoQ_WJHX25$AK
zhr6hMCJA<H!Fp66TkcZ+Oj1MJP(J;NS40qL8p72DsZ2n9les`>sON-CLBM{RqR5eg
z22;c!QVr<GMZR(Lqo2BmgW)Fz@!3Y*97$1x(TR4J)Vnbq$R-LMTL8`pO2`qiqcaEX
zcfU=gF<|K(Mal8m${H%L#WAJynS!=|UnFmDn6HUO9t{uB5#*8f$_0@SUS%7P=bAKN
zLLAEpkJXZK{oOdy(<Vgb1r^9VQxrhw$~QjxE^UuXa(ftrHoFC~fBLGU1k%8{SgBo7
z^ySzV(U3i;H1L04wF@j-YTtq>WC5(is=-L~av)bMOtugkNg+lCf5#3GD^;6`2o23h
zG1SPE34}(QQkc1G9G9J(SQ3>k9J`z}0;mAY(wQS4eQV3)cFWb5Tqlxktg*NAB7&%n
zHs^p(VBiGOjYFt$OcYTp4WsJS03G$CA?R<9#>U1?87f~5&^NpB;w;#R1^Is*H$|QC
zi@{~R-jf!Mv7%O5D(XH+u7-nVp&cYw8R~SFQ588)allkeLg^)@39$IZ0JXk?wp@rq
zq&Z<+WmGshz3JxPV!{9aZD7zT`#;4L^q*n6+3|l-ru(x@_a|h!FF@oAlG><2X8U83
z3bF1#7W=*fb?dQo_@~6ajkk{i-En-BKR-`@iZ9;<vKyBZ>y6)$48L=fyHek$WA*ae
zQr{n6(8C{%HUz^o4nIRL?BLdHP+bI)KQoRgwGqTB8q935^hj)c!$Ul0-}vJ3BdS#V
zb@xShf+Z^+@NeU<@xoe4LQBI_cmm6&e|H#<cb~^UyYa)@UvD4jogaVVJ8I#^XWDOn
z+K)a=l0N#e&Dl>`dxBTCJ*ks7JmRF3w%qo<|1)e8{hq!~yTg@SDG?D&npgC0Iuhpk
zJQAxwL(o02KDL~TcI9+nGSpcl8nGjjuUr_f4mlrmGmD@?WfKQ4X+beatLf|FnC>=)
z+7M(p&F1ORfpyxlpzqXoZjVgUd|q1s*=$>ff^b1ZW|c)(5Mt;;ni^Zuu$(>#VJU$e
zE9^pI`?9H#!&igb-A^^~gnN)P3UUxHtYXn|R0U<yGzuHHCg_9oFkbIbPGYbFMG~^r
zQ8*b#MX7h|VO1k(oF4}rin=NC4{P>8FHGpH77koYoktf6T0<8!sWX>_I~BOs^a=&y
z!84yEJ%Pm>7E?&q45HgV{D+E`KC)W+Ca>BpT1TSqc*~oxv*Kou0J@5_b)DK9g^3xr
zY6FBF<Y`AZA`zi9vBsw}sfR?8KCcHyCIK5Co1Ae^K0B0Obv?+b*^p-u002EGB$upa
z+TACnlU`3Z_jl2+_5ePaRT|C<c$+QLkg~4E5;Kyb8$l!)Yjc{*#-D*1ej+PxH%;tN
z_R-&v&6TO$bTHu|BLLi(1Hj28kkxd<Ow)O+8ap)P^_lrigI%eImUIGxMJ)0Fo9KOF
zS8NuM1c!}?LpK=#miw~Lo!nAqsx+^M5A)u|B`LaaM1bq7ykb71OgYo$5;c&cT-bsP
zG%8D>ya3RSrDS%6cG8lp9fcNbXYwqa_ul*EO)Ip|T8Z~P*~1F3lUqIl0?WE_pGY4~
z0ij~`ufj0QaK}Q5r4wd-P_v*a205v$T@EmE#)73x0)`WjnTRbHT1>kqg$!bN!px;O
zRL~K7sApo4mQ9S-<uPq?kp_bf=205#COSP_nI*tMJ#i&qT~_ygsx4$?(8k%R{fWXY
z-R(aQP7XZY-0{S+uH`kP6)O;|`!DL+z`BlNU>w1a@TA4zxzOz)MWaU#fpsYoBV{OW
z&Otv^ng<pOHl-;}uV$728k;>rIw4@{PG7e@(D)DwHYCfbXZ0Sh+kYLXDc5Yh_$7TI
z^@b=V&eA2i(=7}^7*Avf=y>Tpo<$+|;1QNxUG%GQW@=AriSVV%Y}K3nGW38-Vf00|
zveKq64iD`dMzn^<*`a!&e+gRKu<JcMN?wN+%}fS}qpax5V-mtC{hI(-H5^hWY2X2}
zst=d@jm;UWb+d^UqIn6r)9dd)QkqG*(fL$PFFEVmFPZ1)%3^5(6s?K|T-ebc)XeVe
zA+I#ONVT#<*Cv5g^r-y`3^nrNLh=c%VMg1IFPeCLZo&Agz&tM&3ZMNSYF0MWb##vq
zf{xmeM$I_O8>936h+1$19Lf$bw8!F4be<5Hg(mu5V{)^D3Y$Pqv}9IVZMRP$qBJ`B
z_@Xdbat$mKNu-*V)7s7RDSC+e$fGZ!_aNE{XzZoHv!u2q&rVaup3{x@=PGm`{j)D`
z27H#>CJW-#WDFl=hD>v)>wvc<vW%%W0wZbFZBoI7p~1M!<@o&2Bf)e5;(9-Uuo7W~
zP0$I03ic_6BH|%{IZ(MuXFW)G9mq7Lok>aWWCnJ!4j^b`w}0nZT*@#%$Olv|4I_!b
z)N&tyl5P~8ml`R{F*i!9G>%o7aRxU-PaE&qZ6x9>AkUD&YvNekre~<DV7PGmD6=pR
zv2&J0HBKt464cKVoMPmXAxy+wHlUz(P<DuW{O-SgcfW#=vdYO|BC=4@#eiT+7ld*a
zdUIGf#4&Qu->o7ZmWZ>X0w5!wB>V&}90OnmC&Nbi!<^S-c|F1qLdhh`I*B;1B0i<;
z9R}-7_zR8Y9->JjPB}*cq-01WmlZ?>!lYXbQ~k3~$`#}Q$X;ZvjbW<QHp(-KF=5GR
z^)j2Z6u9=#XZyXPXY2w3b5Jn&SPfU2!niNtz%Uyi@(8P>C{8&_0QHwZ)3xjcF}f~5
z#DIQNDuE3^JroiHs?`>l-$+9O-EacG!7H|8+*=8JW!sy7wn;M)SVSL$=n9v-5`@Px
z3YKBmMm$XCNN%ZHQl@R9o+?>NoDSgmu~h?-IxyJbCR>;x02NA5O3Oql!ee6EQ@bNw
zb)k;6qZZc1CB%>734tVarjWO(b^FigxGl23%ly#azgx1k_#%4H>qB>rHAsmhoQP~7
zev~?t-SNptp{6!b+)C8YQeun)w4vT0E@8+*ILksbi)>>dLST$o$a*7{ezGps8z(6D
zTq$rPCda`TRC1zAwiNV1XpJ!|G3S2vsjX6zzSZjloMfne7>AL7>iLOgKvF*zl}QfH
z3}HkAV+BGJXdxatlQ?96UIm=iCvxnk!H_Ys6v~&~#4;ZVE2(7xD0wetK9av;NwGZD
zu)*=ER0x%fwnlF}a@4;%Q5!Ysa);w9j^j@%UWO}JIV*Wnp-zTu3V~|5hY$<l2Jml2
z0UEb4omUY^F=QY00>e_g&9USl@5c=jz?86e@kc|+M&+GO7;2xT!l!`*Su-#{r2|$&
z-hl>;+5PIY^58z%jw2Ds4b**@aG0iS$VMD10GXFP$*6*LBOc{IcY}^XAoRdbn&<;m
zsx4CzCgQXOAo6)v(gy3M+ZT1~ZZLr%XNxCLO!>HKv{B7sD7O(NbV7_t(^dTdr;Ijs
z<KO-l6gerS73m``hU=0XwkqgHaBa9u;M$Q%LoONwzB-PfpeQlW5{`)wei%VDMYGN!
zWLD~!U%wov!HDfh9JVSnFRlXT9N9Y{WE_iNxb%^Cq2OeF6A>4J`M)pU`1m;-Z{0=J
zL>LKB7#;5jM`xR$NU+f;!TMQ>T2aVIIOwDVGI0o8d_=}D4U4tKIx;t?Y~Te%a?(mC
zb($2PDpH%`N?5=bgt(_k4eu?9CGixjb~_vTSIzC}bfU}}CG++lo-(RX{OaX28{|X$
zBgfr_^>MwlhhF2|NJhgz8Wbn@>pQ*5X!Z;G1^v8keJ6M}Me-;6vyV+iQ~c;;bS=D)
zLo994%dEw&1zCG6+>a^2ClSYhWrJQ~SAtfO$bo*6n$rgJ2MCJ8a&=)nx^7<=pIi$L
ze`&qC@HhJ2z$vrnA84xd0<E|2?bs<!Pkd?d)RmVn>cL4mc$x|XMuS{N=N}97^C6jE
z$}B87<zW0AoDeX$H^#d@kd0c7>@9_pFRpz1+~)r0d##6PKlyH;td#7<VeIpmgpGH^
z5@n4ac7&prhsr}4@|CgUNcrm0_0kKuYb-4u8tXk04ztpI@v5$iMyZAg<$MZfu7Tis
zu$%JlCsS32LwUiG)G*Mq6#f^zP}lc5r|v)*eJ98F1hwWP<#3_x1K#o9T!O%Q@0jx!
zWb)bsX`$*0LYmp<*uv5Yx^UVoZCVg-l(P3~+Qrgy9pOp7SAW&~qW-0|^KW*$|KYT;
z;*4*ocgG#9Zu6ta9Q+w99IK1!ZP`Z|7O!{h8U6`za7<}MZRoD2!-la#`~X|E*!dv?
z%>~k^W_X}OqjZtu#T(y-u<s<lONIBpBMpv)%qW+gI`mYeq$9PJ3dH+>fwdn$_@}iD
zy{id+Ppk|s9R7jxd}rzauak1iOBdaG%T(|+y}y2_oP3(PU4RycSAc`hYTpuZ=JdJ6
za~_1cfMv%#u_eR!LwcqPIb6i*$4Wz`?6nkVu&5oKc*3LSH5v8@yB0xqwOJNhM1VJq
zKMB1<{V1~6yr+IcKVE7~4ph4UQ|_NKzjA5%V)yg<&9&%z>VXoD|2gsvai_4JKSlN~
z?Y%U9HGDob&wI(OXvxl0$+qkH^&~wY?r>{(%A9idIPDkobK)=E&vn1J<P}b}l<tVN
z?1h}UUZCY&WpThg<Noer@5atG*r9kh8mu3s_Fi`=V~hGDk?b7?Y6PGv0}WS``ys?5
zY{nyD4SDSYF!VC{lN5dpe}}AfkmQ2`e+M0+8KvyPO2Nq{u!&)v043(FH$;G^4D76y
z3>%RHD~EczS%2w=oM*qoZeHS!{tbr0EM^z@-t}zT`Nb}t{XvfIP3{HuTd{j<=JXP_
zLY(y)!B~_$Lz?bHYwNH+DAiZ9Lxr!dL%zG1+PmI%F86u?YS3$Uelh)Do%+$<hu7i8
zah?vX_wxw|S``L8x6HwAjB1j_4i301V8xgsXCY^Ywpiar>xTfuPC*fZytkE@1wzg_
z#c2jG-67ea>JrU}Ib6cYJg-CYh)=JI1J0@96njYl)&5#x&w%83*>A4jSubR_oZtfh
zuSFY*Lo&5)>)0);U%ers{F(dGcewEFJ8Kc_qsDl#_X+;PHBlscyuq!_`hj)zmydo!
z+w2a!;9Lt~aG7-$-614~%YOYn2(y!XmMge36OAGgL<lIng^*zEM!^3Lf@mn6ZFM{*
z^T3qhAu$dK=!`cGcIAyjS1soOJ&#VP-cz96rP$x%26s^gyPw3<i92HbKx}mpf_l$H
zvzHo2N4&4EL8^VlzT$~smE)F>eE@6+BVg<lI}shot9-vWP>3%iUn3{P*CR(N;4-2+
zuABT1UB;Co7aR-g4V)ng<ih~8dFz5M8<VIrgiY~00VamA1ZKpsS^_9PzJy-^DTFXR
ze`*_mE9xV9K2*eH98$ni01*^sC4B2)@wG^J&HC4P<x#Y&#&l+0|H}I5tuY+!6tioM
zHlWO}uaOT@-6dq&t0!?20{<olo=sn0Z%ot6k!X+++~k%~jyfw|RWpym)Z?>XdDlM8
z9RE#vJSFOF6S|TIR?Kt7pG0Y5P6Nva37S-4#gP!qw0x!FqUOip2lxU&##}KYG~3t&
zBmTAvJp-9Ij#l%ANI1EJ1t*rBe`P)2h{39FA9s~Lkp08~_FObxOYZ$tfJnjlluYSY
zg<oqq;0a;g6kKG}7r7wX9nPoE5LR(+M2mhM)y6oVJLJO4ApCEA|Me(}`;fQKbwcNe
zTa0TtUO0~OjN38J(Xf<d4A(eq!0C7u<zVib-!QXi0cbzf9Y?#4pnd`74^-kduT9~4
zUA)7Mc`!7zUj9_Fq@ozz1Np5`%sbRQ;GH>o**or9nA;oxY93m5D+J<KZI5@rg;M>c
zfA41OJC`o)akCD1bTM;m@rPc)A-j(hM%Y)@4|wYA|8vjo4-Vv?q{FW5z$n6lpF=9Y
zsZz`j3AV$b+#rd<R#2WkVJX<836rkAs?|gjQacKtWD>J3&ZUYzDBVC(whlcqZUecT
zs=qIeOcjdK4o^DZe#?ajdxlE~>@T9De{D@iDC1@-Wz*blrP3ny02J)5ujO|S7uuDH
zHw*Ow_Jv-{PriO>zL4in@a=FTd8saLeBeT7s<rJQ^i+dZ@GwU%ft-q0bim4(r!8~L
zFmx!WWGIWF8RQ;*_Npda!TY@&Y>{*%b#CJT%oA}Xksik~tVyN4+L)f{*D2m-O8q+G
z2<X4wLbw%~HH$8#>6D@uyt>xy?yj0m*WBO;+kGc+JM~wNxS1~fQU|}fGG8cWuB^<v
zbBNOp@bCUbf*U-h*FJ8$oo_*4Bc-u+ZbL(CtN;z0F?1I^Fwu=<;hUCLH&`<T0|#36
z<rxmlr5Z)%WAOCBqand6d8`GaX<|bREVGy)&v4q;fZo4Z1c2KC&0+}=drpXoCP6W5
zvIZq66&(t`NToy=w_AVk6KHww@Bb89e#dm-XGrV=;DdkM|2ByQwcRjX!1sT~N8-+p
z+$f%Y$Bp8pAGuNd>RmUAp<m^9-6;NUnE(34_;9!J1jqe;k2mYynRMRk-o&#<?)+YH
zcHm}e!`R~1SPIS-U&gV1toZ%0nZ#Y)@H?D(<Dfsyss9PW{EoB5&v;2pI{VGf?%tdy
z8+@5S!$!dmpgD&o7T>V8z|U`g8A{xoCGW@o!=^@=a~&K1u*jIOI9km+yg7aoM~o!?
z3LwbvRlm*;{Pw?!bDB4P`STzAc(D-wd1Gbq&g<eIzz?wKihm>G2T6MG7yi{~W&s+3
zk+AhMV~=*{x-&(V*2gAF-ChJcw5kbn+-917lOD_2v@6H6Rn5y3L$EE#NptuUPeYW+
zqeTyRP|qg+I%tI`nMKu9G#Zx95hOY~CWCdu0A1*jN^4jhhb_pBY&a!sd@0e=JlRi4
z(aoL{Z+QKDl@_{rA!vmY++%i_Tu<$W5&l~Lm4RcaB^~K_?oPC|luO)w&;YMl2l%aQ
zM-z7}xwI|iEsjOlpCvvue??CbDNPZ2`HT#&${=v?6mrH$#(W27DzOqUpC?%23D*4(
z-IQnMqb%%Khy#~*b#54B(pMg80QlKd?T2O>p7c3qe=ZDM3m2}mVU+_z*6s-q6C10p
zHVB+Wkiad|U_7C-A<g@s_n`;2nwqwca*ORJMDrcBVxe4dIw1HQyNApXhBFOY83%jd
z3{sYaK9k}IxMAJ6T>z`5W07q_(>r1j3ggUqQoFtqB%uv~RG73~$Kt3%cChr_nF2VX
zrLU$&CVj`{SZpuSLE9U%ZN8iuTzMqc?C3S8P}AI34taW^$C`6?rtJ5A_!rU(`b%WD
z=PlAT*ug?7rJ{ylb;zIzN2i9>Y^R0mf@r#vB6gzN5RzODWX@P_2o8*<x!HkvUn#kU
zS9LSkC(fkiI?@SVK;@x4#5_dD@>g^HbHMjS&L=qp>L;w>Hp^Sn3#<BCzQ5i&>x^=}
zd?6~bz1l}|ma{iNYVMxLntEM*4WhnPI$}ytha(IjM>03e_zsh0XuN$TMi#iAA>5(y
z6vE0h$9?GIP{1<ZOmre9fvAmdIUW*{OL;Zj7}DuTz+t{fxX)KPl&7%F#Zllq9{5nX
z<83My+QCX(zq3rff2TEN4t$Hx4{>IfV30E00oAJJL0k-@Mt~foSjf24L>i>XR~Q-s
zFb`b)FUf2fOITcZw6NVE6R1Rdvf9Ip7pYAK6senYHna~Vo$Gtk3)y)Hjt5i^2wWcv
zS1b;Bp3OOL<IoeaLc@MB(4S0QcgEPIB5$+)O>VzFeU4tz_5PDX{pP?m7E~8*{MmwK
z?X{5!TDKY0Y=|M)!!(3?S&p!B#kxAJmSk9%$a7k=6`j&LQE%oDo{Uxs;T2@LFQ+m^
z8x3uccWobGo%$s-<STX{v(PkcPXQOHlcsezURF{4p^nN)53TEZzB=(DGgom_h3M*_
z<)9x)t5<|`hGjlOGr838bQczX_N%GzIeI)y=6aAyt6ki?kmgm*7T(O?_a)E)N=*$|
zOFHP5Feu}mkymWhf*X9o#&3XKAaRyl;)0ecM6#urg9M7r`n&{c>@qC$OYnIB*eFe;
zR7nRwGy&gAWZDGuRf0C_3g%K`n~T3?SrU3`ncw(_X$cx_)OlaVKyBgHMYy9dyfWpO
zco{Vtw|5P2tVw-E$yy3jcWLp5DWWk0oyoJQk}Pp<$ehGmTjRvk3WOoUATc8)UswEu
z)U<Wk$|SfeJc7Jz1y?h#2mU74NG)-p2V`%?zuo-US*_z~NT}@r*TZlx`{=+CLh19+
z1)wyvk`q5M6c9UPOQ75IlL*I2l0gt%8;rYAuo^U3E_I{j+B+ep*7X*%pTq9dxGECR
zx4L3b_08C_K^m8NW?D9CJ)lVH=l^{ov(>8DPMczBGXo>0)=cjwkdy{NaFk@NqDeZ|
zbdQZmt*Z`(kjPp0{7v3v`x;xYny#~iu>z$l{IZ~8M3M1|<8$_y;0uvjszY?Fb)Kie
zWvDx+>`pqM48wQ%buL59dCv$mFl^n@oIc(~$2f8h(2R++1SkHn7o=s%Tqt;LTg$i}
zXlY(X#vl4?SEN+`DD#%V(LCY-n=XTjp}=i4c}#!gK^rTQv~Z{b?u%X*mr}KS&1rD9
z(=$e0goUcW4gh`(V|3FRictfHp0_a8mWmGgy2(Zg#yLQxw_cd+Yna-gv)&UfS|)8@
zp@63~YYr17@c$);osk)hf>DlshB`E_sTGL%;lzQxA}M@}up(7lyqM+_8f51h51eV%
zqmKymHw%(+55{7kX|IOfKqEmVQv!6C2{PC<6=Nz?h_g1_kDs#;x?p1w4{oRGO-`Ul
z(tw_54J?@bV1CU}d$DCMs;duuyY_Jy=u~X~K6p?>DV`E0(Xb|2cf$qG-y)HG!siOa
z<Q`<xbWL~zVogX0#F$$$!WH#g22?U4*Z3=7!^;A+5%xA1P6mru<OFGDl0$0S^oXYw
ztW~Q|abG*OCGfG?hU$$r1&Xum^r;?NA&Y)b8*4WeY~PgOjE|b=6)9vLSV0<zWpv~U
z0wSp5l5Z+a4Io%%K%EV+e^1~n=|Lt4&I^TUtxm&w<(Ea0pj&4lLJupL`=HOq4y{rf
z{e@5{K8$y1x6N<-`Ts<S6jo{}>k+R_X(y`$#<($@N5CYZwKI&(CiW*sj9}vnF=Wcp
zXfr-AD$F}f3`?u<cYp%fn}h8RQ0YCMZ?PWX>|FEP5mJ>=zha<jkX09nvj`E{z}W<;
zRtdY$`rg!5^jMjfU5C-30X1r6iqq0F44!Q$CB-oosbgGl2q*P^RGm!+J&Ya{rGb04
zNn&IU=2i%XbDSIGH!!60JzZ=jm@za^)zCBu>YGx)$@{X@PwFu>A7M1aJHnc&|NbO)
zokkCY`h=d4<1ov*bTB~t3VeHn8L+lt3e$(@yxl^P((5^fSW8?#8aBf0s6#Xjqba-&
z3IiNj3KP;<1l<C(Co@pc>LHmfJ&aL}$G=w*xR5xB5<`6e{iL2TuE%xK(A7Cl8nJj^
zw+_@Ug>g5wG24VZ+i?&X@D&d)L#!fxj@Zi>e#F&b$s0&cfDw0s)kl3L=!58ux8SS{
zO@SF6W^z(Ll=7BWNlgl?pC=X=n)^3?f0Jo7k3Ep;@6iwNqWf$0ecprS1@B6IrTCFM
zo)%unpMztbj@aw)z*W<Fa%gq9*(rk8_6!fyQu&49lZ(g8Xb3eMx&Ku={0`$cA3-Q8
z+tq=UR99{c)4<_!4^$319XD(Jw6sP!g5#|8r~0*tF<u@Fue0lrowk3E-18UR*Rx|`
z_9eP+xJ<vaIGp{M7;ikwU1Kyry4w2oss5eYFWF=3QI=dCc!kdNl(kvMyiHRB^ewjV
zfoL^%v`*dAH>o>$F|}&VxU~=MzPJ4eJy>jh@%$s$!1SwD#e6OM7CPjPB5Us#@b)!V
z^@p;L2J9opwQjw%l6#0A(`u%6vTN)KQVfxgk_kRBY{~tTpX}gKO<M`OX?DJ+8}3y6
zoYkd6+s`l1_Z^29#%M60(`WRLG=_)5FN-50{DL?&xN}K+;iA`=EVqVV)PHk$)%ii=
znZXa989x{Fj7?v8nVp0+6L~dt0?`1sl-yd<a;f~)>2ur9rxqw&d&<^y%fD%aFYv2w
z*s}TPT5eGLYlq$ZR!@aJkasXcxxg)V*!xdT45S|<8$`Ojp2n_Mu|dR4ywFO&nZ>df
zv2)x;?SVW*J>X1vbZGU|L$Iyb@EG2J(s<ag3*OK+Z;z?;Pbigt(yziB$I+l>#p8xw
z#m2`pi?7D2uFRbve%B{-B@4rf<D5SlPNbmwnpm{5<{@to=QA8XKBKSKv!g2zf@|qV
zINotg@8OwSr+4_?dFKWC{gl4P%bX(nGQZ|}5FTH#uH6TmG?A(O%4~HM>a*1K`US#o
zMw$KIgU;u+!E<*!?U4)4w?v$Q|7dmr&Ioeyfa9`<`QA2dqSv+CpVajW5WDraUvnF~
znzv6Ny8=1$r{E`B-_1%@_@(A@_tEd(_cWbu6fz&CQ&INQa9X_*)z>m`Hjb{j>a6&m
zJjz>F=ocM&i_(|2_P!zB5H~p|rCT$|5h-^~iSbib$CYT<ZGS;OwoXrxl>u5$mXlL}
zpiqO3zab7?^76M=-&;vqI|j6G*jL;bxO`?H3ze&7c^Uik(LB6|V>{cDrNBR!^tM2T
z>Gl=t-fRffDU58@OsnkV&E)@$>zU9~$SYs8G9d%soVDSzfL-4}x12n9q<0vXP0xIo
zPpimtYh+uh$(i-(_=L)C!AeX;<JML4;;ItssVf9rbZ;#9{f75u43PjmcW$1z!}(<x
z1UDjS3V3tdJ{UP!*^|iu3cPw?#k9W9{-W=e<Fs65piKQ%Vt1i-{|v~~;X`8Lbg?*#
zbgmnaOV@Wepsdi#!kiR9Jg->$9Ww^(P;ILj?1F$SeEZq}?uX|pc+)ip*a&Jt1-`9b
zwi`wjRo5#Mc=>_>i`Bzl(B)~qd7@FPB){%uPjxZhniqT4K!7I~0^^YD*GRArdq%tz
zHIlEnjcM=Tr33kU0la?5*Pz6P(TVf8{-z7FjfY*Z#N10yy8Qg7Wa~j|k@P-XDAbR@
zHf7(yj^qd99rT(JVyQogeD}B-1~oFp{Q53nHqWqe?PmA{+EQB|t$&!aSpBTIJFSfD
zx@UEJ&CP^WWaVSFn5>XW(z^`Vu5nC<pckeDtg)_*h|^hlmUo=OT>%{CPymzcYOteF
zL4Z07{|$X&xDZHtkSBE`iVmP$Zt%iB#3g3D?3Nk*YXuL?7njg`GqrsmY;ZrgQ?lAo
z&-ekCZ`u972HYJVp3!k#7qr)feedBvOv036!s{*Ko@X9##!qed<mR_@+;p7w+em_U
zvZ#@HYqO8~v^Gv~8zK7-ZL8KD9`k6u<$!Ig*-fzDjVldqB-rV$59X#De8@+LsRwQr
z+3DBgd+cQoi8B`*I6#X#m!k2u0CvzD%?3hcAwWc@7#^CA!%i2*49CI6k3$g+4+hXg
z2KY}!rI>mBlGys~zx##2YDvH+WZ+=qWAzq@%bgvEq%6$K5r9fUX+4%5YTycswH6Iw
z4KABEa{3fA6p(gLzu~&jqO*R~Eri>WQF7@>Z$Hd9vb$2OvMV;*jU9~#ASllKMh+I$
z60&7ngogkC5$U0gu1;u}X3!dN$pM@z65m*nEAcPzhMQ5eTj2;eDbj9y8e;Q~aSMCc
z)QLe69Qg#dl+PY}*JbMhxf;UoyDjT{+UdOoyY72;BxeKrblVu4P!EcM#=zz3iql@-
zh@M%JISvbAgU9WEce&*?*HU(0bCIvW4!OJGK<y4F6Y%ZO_t*#=B)su9R7*#KrZ|nH
zfg}Xdu)zuZY9V_n$<XrLY;YVkJ)2lZ3*W8K*&sjz$6<nl0zM*nW%`a~NdVuy&+7=-
zofYB?5)8yTn$-ah#uq=B{Z!v|1WaJFp|kdSw>B}BYHvyGC=&PtBknQ*D~R<;Cr+JU
zj$W^{mA6IEIH#%Qs@r+O-V-~-B){cY!677}P&hka@{x5!{pe+e*YV1IOrVbWP{&jF
z_f9n87{P1n9g2u!b5Wx({t>Y^DZ%o1QpwnBY@_~6Q)T+%sT1<6XQEzt|JwHw=(Zi?
zjl9Zh+fH!r^5nZRNfqlK2wAA2$Nn6!W5HBxuGkI12*0FuBhglO#%Rg364DKwP7J4V
znq460^+VnRM|$UVw~$~3mDp0;P^|#=msr%$2{m;b6Ehh1@r08n_!C4Tj=|oe#+{X1
z(XzH%O~MlFU2{%16yK-1{EoVb(G<ZQ1{QD1XFvO{W??zt*D(Khq%Ci&5A?^G_7FcS
zz=W2Sc;IEH58>UuVc6N2a%_EJ#c<ov1qM^x0ptcE1L;k#1CP1@oi^6sENbC(7}l4>
z2^)FU@BsOd?FFnr3TLeBig*!Yyp5cr07@xHpo<~HHOJtaeQXQVR^&AZJDQ-Y@Dr|o
z>l1%vHS-^fqu=WmgAI}NKWSq8Q@Z9aytJVu{<#GEnV;u`{L|v-fBqo<*iO0pwyZh+
z{?rd&if0#Z_TGMp?s&%udFNeU=E0b!*MI#>7Y6V8GVlGYdzW6{9!%|tJ(U~Z1uea6
zhK%p=p+MKzA3ywmbbK{F6usu2w>Cu5`>ohN<IZG$zjfeK0|6LzKvpdRW({iHN#jS%
z*Rh1cqT=mm@%Nwk!jg=|TjYVk^`ZC?HI({}V6iyE`^A_j<N&e7#xrb+z7@OV^>K5}
z8@T=5&u<*Z{?XCmWrifV_=nZ}#&;|?u=@GwFJ>e*e&OH!w(&fE5l;2<<;@7Yh&QrN
z($uA~-Pv=grJVJ+US!s<!o7e&2@@UDJT>g1+zh)@ojq9T_UL^=`#_GK&8%+6O4sHq
z(OUtKGts_kA!!|%|0Y&Jk6WwA_2c&kl(l)VQ!wG3JWr2f>oLgl|0o54M`<2=bXCm~
zGYL!sTrA1M)$Mzohn5y6u~^<C!uzi-j0Pw4QZlDk%rtZ?zf9W+Yi*3C#ab@9{el19
z<X8)5qPjT}toTdlikft6mlZmQHW4uGK2I3|!7_tK0|)wT>TCsHn6TtE1|o05CgM>i
zVr&#in%EwQwjEgwQ}B0~qhQVV7%U-mccZDDG^K?RP)>M3%%`Z|4bo`T$I>a6u5ehk
zpQXZHiiO{TZR&+u8U7gX{tItE<r=DOS-X$xmP=N)6HA{mH48cLBTVCM!@&r)&FY6D
zOHR8RDZfzu?na|rS<{+a-Sa>&l-(%y05$`<Ua%J-WrT<7A~JjBG*XPSyK$kcHVnNN
z+!z?vg=vATu|D<j)R>cQ1flMx#(4OZTpL^}hbty1c>ue0qZP2w36K5vcbn<elqC%&
zw;E<_i4eXH&Ma$eggeZadFL>w`LYJ@XpP$Xm^UJtydG;eFtGN(5?O;{kn%QsK&hJY
zauRzq*XX+lA)3yRJU&K{PRD&)ZG~zav4e`qNK_1b0wwxfY7k*39i(SDwTC_KQgidi
zb><=+#qFohYBN^p*84x-xro5AHqsd3Xd*ZX$fR(zsA?kHI6`4VEKQoJhW*!Me4be~
z2N@!LW+bmP>8=1&f;Qc2QaZ68pN47JxNT3yS)m}-9E2V6F@y%XwGOta6Ey~|CJwAE
zQD>o^RU}9~J?Iq!W0PKfHt^-?BS;jw!Si!zt@TMS(f7z|*=AsB*n&1u=LTc8xWX)j
z!SI80=|<Jg96|H~6<$s2*PVHYwC7TxHjE(8{Ps4FI{GDg&>KimWZ&n_esv=4j-d`>
ziwc0yHcVhl1J#xyOWbS;yE2d~Bl3d~%Mxu+#twS@=1a#lx6_pdpWc49AP<pf%Pih+
zopVQdxxY4Rck6%rB9?ub)zpOYF$J5imR2%pu;vJ%mPRU0KB#)>>8BwtUh%HarHoDY
z!%?9a0#!`vLOZVW6(sMap(it+>*oi(iiylr+KZuvbkm_Xuvc74ZCcV-_Gi#`H5fHt
z394*I2xZc_oZ5L@)29hL9nen~gWTRAOP3l*&VE8)Tsk1kze1;A{qj;{{5kBj6S6M7
zySv#c`X)oxovo4IIc%Xr8jbtJIh<|Z824r7Sf~d`3G7o$!$JTA7>kpG+>i~~kGEWB
zeS8x~Z@U3=J3E@j0f`9@TF`|u^ccXAY5)<QAPeA>-9Bqok;{a>5CUT~c>|)#8{`?p
zfskjEQrAk!g$xXIlazs=!(TY*s0LxC++o^$9@vVav(|L5Z3u@*H4UJPEck4zc@HAP
z9!C%hRm^8hW_T5Lu|iEUSaws8BT#Dif{>~yTxeuAIU1R+4bM?<w0UdDkae1Nl^aiW
z8zysl;3(lr$45+Dlwps7n88~?z^Fjxh^`^FiOhUOLMDN2B;WMp95SvL<~E%}St_qU
z5Xr7E1*4A%VQQ5b8V*p=Xhk<j09Y?Id%=WdtDOxN%2{-LzD$jP1)C(_y!AJKDK!C@
zTYZiPK-Ndxdo`&w!1TrfAyxa{tdSL%++)%rT)`(rjTdUnKdu4NFQr1o^ZdOk7iqqf
z3hYa|r5YE7jD{q9kE$bZ)M9oGg2^I$QgE9+^ky>H+%PsE$JT33V-a@Z4V`3_im6NQ
zz4fj^bZ#TnLW;VHkZ(qq!i!77lQ2zgaT7be;&7ONVE7^GD0-iD-N6Xb1xE?huw&cx
z5xh8b3UPvrk8p;B4~t{LGCB*E;5+r4@2u0#?bC^V)lZ;*>rY^mpuuSeTS|D+ek-Hc
zpGn>pUz}TLa>iPvVJ>yJ!Ta)()czQT=|r7{*SKj1mIX0^g7H?`FPLp8?Q%(7@@tmp
zQ!)#dKUVD%YGI7EDg|{=Y%=cgVbZV^G%ZjJ!(}$Nq+4Lc3G}5AB29_XsO`_EaFYgG
zWq+%yALLj-CI$oT_IJ;qGMFAhnp3W(_XSTna94qL%3jwH7LR&7-p&*w(cL6gC^)t4
zMar^3i$=Okd9-33jIDx#X};){6hFaiABumfPA8^=fFbCMvgs71l8UX>?*2z%qXm;I
zmkcIsy6kF(I%lD-y6ChY{I&uaw=T63WWDHtX@OP75hmQ2krp^EpnW2cR5R1x@?PRb
zHAO9IqrMh`3A7^Fl6;tQOX-dvFrf{>zKyIU(T*(wf&>TVjwenWf$u(b07*)~mqvp4
zn=oa^QFZALzTD&_+Re?pRUP3bwgg0uO_Qo2VuSdSc^^@nDh`R0LwREF;~GP2?Od0*
zD-Ec6n~M}pOn87`0}0Kg8*?)R53tzoNVF4@fPof5Fo|HYJ~+uy>MnEpMbIz}M_+So
zXK>X*Rl4!HZV4VLh@E)tGP-MYFSs^lH6<{jGye*kgq{+WTlm)ddEo7CVDS4`KquEk
z6H*gF_f;{-hPmLzy6^#<CCO@1gURAF$2o;KX+y0b7`3dg^ttL_&00<&C|lKnwE&9^
z9JkP-803~?O6Cj}1Cg@Nll(^l7Gm&GSfARFT#8eO9I0YSrFj2NA1=F=nx`pu%autb
zxNMWQt=NmAV}(9I_U77;x!v9yPH;9z1W>;Erb+3vE~Z1Vs)=S4{G4b(N4KOQq!mc<
z19ede96ZqF)MXcKO;aASM(w^wc$0hVo4<(dd|MUMLA=d$tR^oo!Op8bQ}Tx}2C#tP
zZ<u7E`grJeM4!HOr#^u0X+VXASfC-$Kj^{Ykzq`gbD4yRaz<Uj4a15}5?nIw8{=~Y
zOchWPaZ#~GJbm?VT}(Yb>1f}AIG~g~vE-VqKt*<fJusBU$WB-E2l=S^k<-}tOgjUm
zt4Uf&U}@O|58;2DeTfgy&#dph=w5f87CRPJnu7yD^<(9!^5Q;P;xBvq>5I>IU)=si
z?YZGUVn{T)NMH9}_m(&eTP~JFsS$K{?3g}Hqp|kpfOJfsHsid%6FD*YYVCy92&+L9
zyedlfmg_g%+_b~T;AFqo>c8S_ZsWHseJ}4Gq%|}DZ&UkI_TG;4g(K|3kz+Z2#V%^U
z@@tmXvZ95Df=NfcpF3~K_nTqz4Ql=dq$bZnm2rqVWqV>(Z~61u(+I(yoX>E5r_+ha
z7$;%yeOLeb_URt+_0;#wAJ(@2)j2V0{{j7Ujgs)vBSXdJvA1q&^yF_X6bHlGoQB^i
z)%5>J&qe_~of8WS$S6eqm6=^3+1$kkMYRfZtmxrj=Kp8y?W5Z`?|aXg@mLuvN(zi&
z+%c-7&J2ds5Tss6vsqM|O)(E1LPH3WNJe%UpEe<BTBcRIwj6Jd)~9EKXYhb}K!T#g
z(k`v~rX&o@uqr2(qWY+9?k!2fHtndf<+@w7H}^zRWLHVt8%c3*m7MI}{SM{4ZQDKj
z$3hbLA`+OH=b7i_^ZWk3KYPeZ-6^bFCT0ZT)%)20@r)Rsd&c|J*JCpd$#$i)Bl#Wm
zi6dMjUiOvjd!)1QDavO?KNTA#+3SzJZ}!`8qWXK=p>xJffW2uIW8Zv+K;lIL`gi`g
z!}lAj4BJ`?>Ggg?8w%Kb_o_4+_<Du!c8`TyVYh+B$w%fHkVy}-=V3#<z_tjdiRIpQ
z7xI8KPj?|R*kV^)fM{%xPuX~z0HSHE?6KDr&%144*argfOP<Tq&|(YVbPjN>)9~pK
z-_d~Lt6qnp+K!cwvco49&#_r+N9@9I|E2jT=<3~~xr-!cjVDjpm!szdxq>p~)0U;S
z_fJMQI_=chUAgEq`J(<+UMC587fBtnnRzjQdBzj}Vi>pI808!Kr`gx|mCeWXDgAXg
zA%Aho*d<b*e7yp7?;+5)=S4f}$URNQrrBe20E#p2^a_$}ehoeW8=~nUyZ!d~2tQuy
zk3WX|@vgTja>4zqm~I%5vCdejOC`WXz$h>V{$V=(TPwTsXT53mL(W6ZZ^!<^PaLOx
z{|4hN@h%1BHp*9WDy&G)p4iL0-Oc*m&4_t9Km3DdAB_#PO1)?3EX)l$9vCIMlRQ0e
zx5(7)PRR4oIwzR}{uu&J^rGKZyFGD{ciSnVT?mlO{~lX{6DOVHU$K+f1H5|12FY51
zOR_QFdclewM|rPtAodz;LV^M6VNy2|HHgLAyTWo^cNs5=_T#|Haw@n~Sqj?i)Fn3^
z95w>6?|sBS8-D72_Co<JDNYNRem4p03~ndeqH{Eht<?NwAk5e|oBNL07ifKS(w>U-
z)a^g%R(A&X1O4?o4->dXL(|yrwnJWBPj>6DNR3WGIgaK7t?ee#pVFiw&pVh08O)1u
z^b<Fl&HQB+y_~~=byj;Dx5N4Zz8MI2<&Sm3p95`X99?MIU2)AW4Xo^d`@|uLp7mgJ
z&}PGaBbD%$;Ytv~KCt|Q!n%NSN?i|~sG9&`a7O8P?sll<DJLO7y)o(lvag=indX)J
zaq!dmy@~7VV{e|II?aZfR%Tv*{Q8CA&y8GQ-hU@KpO^2+6}?lW-p?bou!0;^y#0XY
z?(+~mm9IFnC`cyzXrq^0B;UWsPV$EDN9tpCUvr#48_hQ;ApQb~Gk{;owHH8(Yx?A!
z*k`{b<~We5U~J57Q>Mi6<H?AQ8gQ^k3D94s8*nimaoYth4fN%O6aoCL;;N;~9Zo&E
z8~WOMJUnkHe&ei|a0y(X>s=ex!`Wl6?fLnf?=RT@gMVT}%(3(j0Id52-937G0Kc(`
zw4>zWahgP6z&vSmk~}}>_S<<!exXhia;|2lu+Xyk{AV{96Oi#XjU8h5?>(hY8Lt}k
zyDHbtitO4FpmmA^ix1D+M_(v_@=sU3>!#6kqE|d?mvM*56OD;<8CK0ToP6SWpl*P`
zTIci&`-3xf&32L+^gG%G(0!cZ4@Gr%0g8Ai-^<41PW|?HnjYd|VMuy4w*Ji%IcW#o
zmoxSNi_bjwXiTw;9Z|n+k9hSlGDGz8K8HvxGXxQ7=zUq;GE5NpVx3?fL<-!!G5|DJ
zd#`NP2gC)xp>srb8qq2Q@%G5@iwFUd({!CXz4ST9nsVP5^AokMDN&RmT^+!s71xYJ
z8!Rjgsq4!}UkrdF+C`)>H%~)0FH*THenTMM088UN;;^&rcBB41gU!>e2D+6CwRh-=
z4i>%piI4SA^=-O@JEA;D9~f<q8dnKvhZwqx<Wa$0?|?r##SSj7me1gZf#e;a9~-;*
zC?ZS~{9Pe$&)Hi!G}Y(C{^n2W6zRrp-TFp!yDx2TqbbZJa;nP}hj==?tcE#eTV>a6
z+%=WJt)Lm@Mp(PA-8Ky+bQ@{zTXRU{T^RjPQh`a#jvTT*4!}gYd}C#0m$PjEHbD4|
z&|wC~BiYajiA!7bPxP#hlflu4;i=tU*hD0!<!eO2iI`xr5hZgTFuJ@#NW$|KU}Owl
zmTWAF@dbxZoZ*fl9`U(cz%|BrHh()JB!KiyeD6|lJvN&awJzZyb(^`;gc4dc8|9-D
zrZQDUOlVwJ>QZ>%g?;15V7RwTnqEG4Lm+8|N^QsvXsqP%AK=ihc0d`9;(><x)hE|A
zpIei;hk(Q63|1cKLi$Ohi%4y7LO<vv)y1<?9j}d@tR+h!ed%FAlw%VMk#$kk7n{9~
zCEE!*s-$&r4Pg|05H2`K`Wb!VcvLTF38=djRPIHAK|9T0($dfOxQ2;c#2K64?jsR*
ziZAQ&52_7k(I6viGAe!Pj1q@cvc3ruH*2vSc~dr@1+liGa|E+Jru0qY#L%ZmSjx5|
zOkQFVfO`HuHpO?t)`N@QV>&OO+@U8L@M&J*uFXrR$J6fTVdMcyJ;gnvYY27N#336M
zmsTyEF+{?rxyI0~FS2yt7ST3GL|{lgEbGUxGn>uXtFt!5+304FsjpWJ>aD;2;C~zH
z{W;wJcbq?79$Pi-_{eVKRm}0LKzVW%DE~k8*-%#B<jMb<ZtvGan!IWt@^_)U`{v64
zN3ROBPuU?%{+VqDO7(3Fez9I){-^Z<e+h7Z{nb;rkfB`slKqj12tfBoO7GCR;}?(T
z<(qW}XJ5u~{DP_TQ>#`aGe4Jjy9n<7-2S8f2)_QKZ)24W+JQX^q$c50$Yp-|IX+rY
zPe~FqgxCd1P&VNi|Bo;NxV9y6C;Sz{i;lYbmufzAc=(nHl7X^B(La6{Ka1Vk>SHL}
z-2AHtULs7g{fKG*^uLMs)6ahP5pNA+k^k~9rX^SVN#Jnac1^EV``sdoDsiG!<xK|C
zSgrUuaOX|>;R#)T6jR&`O3*{egUk5_5c{YX_do5Rtk|dZgbtKY>ax$;>K2Fa<yh;$
zSb6z`bI{|Z`v92NVb_^vMRw7)?0141gAa~uA<5DO$y%dNB2l{T<r?1E%fZr>k_R^1
zIT&;ykt{&AU;qYY@AGu}tHE1$-3k-OEYmX3xyp713C{R4?-`F8a)m{)MZ}yo#w<81
zqMiiyxwJqBA(G}p%Lc}kSXUL5d^*<H`rABu3e|zQfeJs^jFT?Bp!?uRzy*WiaR#oO
zMhTI>Zl9SBZ@Qs@@fL<v@H>gX0b+6?xpyJuyY@Q|BjMI-(aOXRK8%Y#7c@fZ@RW-D
zLe$WPAGNg>#nPosKKw3RDw^&NYl-t>V0kgBO4eawSj?g%LR7k0A6lRtOEK6S7+Q~^
zm66sAj%65IG54gg8^rEH*kh6o_8E0AdZPiHe0fGD5{!Y7xdRjapw6<)<3B$2PDb~~
zAJ;XbCrz>7swl7_C{wk-<dy^aecVaJz~9}Lm`bU!)MKnew)Q^J+-fXsMUw6elKM>y
zOWT9=;^Q5bYRZoQq?vNqu{cP*wn@juG#7%*THRb@I;mEh2Q#yUhH-Q>DC`Y%RH~>R
zF}PW3DcM1;qNKR|QsL5{f6SwyO-59MQaRWf)4jfN#6=^6K1$5X%;C}oTQ{8f0Ng^N
zpqofK_Re|^W{_-fWESWFB*ZIZp(=wvDTrSRL6fa%;{rJ%ifSCEm{^+<p(B@McFpBA
zJu(OF@NkJq^HzE*thA~!{6XY0opmo9`b3ZNw%r66Z9+F#lHu#?=@-xHTJMtKwY{5!
zc7}Lq)S5#E0K}6B*GSBpbl*77Evui~_eE8Nd3=62wrpHjUeI5nUo@cGOUe&`Q-`jd
zrh<2?u)D;D)<ZC8=&%^;6xIgulFOBWTHdyg=@Z?^`gxEY^je$1dyrxB3OsJy$=<|F
zT2GBe-AOCOqqA=5`uD#LN8}@@_{W>MhxpkeM)F)h{2A<gmSUS?Q1Qo!eWa^Lumw*q
zzG@7lT9$mHR|P^tvmrr1Z?oU1!k8EV%~)l@dS%6*Y%vPhCU^3z1-Yz|(MN;G4LjC4
z=wrKQm=M+3ke*Lm3g%Gq5n4Qv8q22I?qk*VU~HmG7k=@(U^1n@aBn+h6tyawWcrP6
z;ngOC#wop;{2@Zu{<k0dm;?c`L7R;0ZP2}~k;*Exu6k0z7*&*gr0mPw1GsQQ+Y0b1
za~O3O;ws8NqL83mR4g|m2zC{rW^-nqrQ<?ln4*!<?tu9e4Y<#bNy2E@<|pREE(Pf2
z3fm0x*RSmy!JBvy`0{EN(7SP`*A)vrRCN>y1hB==7-dy5b>Chxn1d}m;t>k-SA~&_
zVMi-=q4U52D29A@Bed<6+=-HGrVVKV*K7kqrWM7U3lIHHzc40D9fNcib|D_ZATXiE
zE&PrDlp(L_VPr@}yxW#tj5boiQ>;ETimy{*)^#kYbSDhDU}RscI&qPN{TRQ@)-Y*2
z=HOjfglZ8xU@R1vB69<Gm8CdE*~T4+v<0`gfOnJe2kRHWOBC0sE&!}^eV1dCU3(>|
zxa8XzqQ%!_m#9?LRf-?KUnvKegzzdBNAPP1nkg}8Ds(2RZ6uQCvy=vG$ZSMLGfp5H
z3tjW@mPh^KMj*`xVYF7v!(c(^?!ZV<UAfnW#?rdzb8S92?kF4<K@Fg*l<bydM4Zh1
zf3`NBt^zwbD#YJDas+A7xx=6{gE`G)?j3e$MRGXCAoS!Vb<!|E@=A78YqN%Hy{hdQ
zhl9=I?$(%t^M)5Z!n#VNRw^FFkT}ACsByQ6Gmv>Be2R8O>Zo-oxFSkwAZ*;bh%Lfu
zV(g9!|I(wt6Q-p=bIrjPjR8(~59EHE^g`;sljOQ7X)D;>zE^yA#JQgg=b8PKKeEJj
zIi=Y>?3J<l3Xy_E905tx$Fqw09BET<tvpQJjgpJT4?u<+Zp{p2*M><wf~g&v>1vYb
z!VHt)IIy5nS!xtL4#g>2EPKmW|MC-HvcyMPeoUz#Qe!~qkI-R!&cPswi3tgi2nYLJ
zn;a5R4Ol=I<pLX~8NM)UAMYjzebfg$DiX6Xy~Jg^xNIPQ2Q7qE0F0x<dkX6ilRIKG
zFgeg8UR%+P3(yw3LqYEvjFSrqiI=Yb(`$VQ^{TWG#jQEqLr{~z#!$~K9C=*1&m(K3
z)-i{f!7L$*&V0-iofKV8m5d=8S4NzmAm{8(SOSM#5mqsH+cvpv#ImJ^j-F!!IhvTn
zKQ2||ondp}55g}JE841`ac;cOz`ZI(bgk77h~vl^-&jvWw;V*S>fq2`+mjUiRK+fx
z(;=|THVCPAz<_oZH?UUq!W9wi^_<&qiGx(Q;3_J(Q4uES(n0TH^Ny+J6&!=oRZ*)-
zv1Z}@5Uy6L_znFByX01Ns66Q)>VZro!^70O)q!jr+;g7ebO?UYl&y@q)TWiJw4TKt
zD-&Dc;apf{bKElRS(3%YHq#CS_{fcvk)sTqv#VuN3I-00QS(HAJ7YnI$Z42WH|GZQ
zrhz>D(%m0_YLHMrE0^~;UI$Jb5fa*gV!PGOnAhBnER0S_n!Ai4fbSN)LHrWJRO5i%
zW!02z$)IDtG+=BZzI4Ab47h$I#;|!s1BT53@wqKFxvSI{nKj`zG1!DF0x6xxm}W=Z
zf!Mb{_X))3FoWh4km&5KdP?0uh+S0fC5pcQqb9%YR^J;mpL9|%tJmkVNc=@aL`C$$
zHX=dIGh=FVpy=p>4o68;L=B7bOtHZdq7AJv0ZDza0VF>Or$G%~qZW?F1F2@vt2?(~
zr3~AvHr9IPMJ@Zk8JE49mweA_+PUASWQ0A?GVMJc>)Nw1mv!D>;J1H0HsZCD?QDxP
zTrLeiSNc|J)PdcYRgZ1V<*&s@Du3p`GL~KLsJ^$<e0Mr~I=I+eK>5If*&W`l^@TAj
zap|>l<g|0qYZj8vl5e&?^u6KN=plP^Y~yIJ^PUG~1{w1vPC`A@T4T<H^)*|3pSgCh
zJm;Q*??ji~=&1Z@;uNgKk9Tig8Tks-N&}B=_VpDhQCr$R0fEGPtTE}9g46Di1BcQD
z_qbPuPu#^|$;Hm%vVQF!PhPN2QF)iKeVjDui=%^oYTb9vzt75_!}`(Bb;nDc>tA`y
z_|ULlx2CP`!qht(@`K5D-KEjV*h9@d8%HPOUmbpV{fDSyknM7|un!GVC_HZP|4RPX
zGmm$j7)-`S*=M+2_yhM+t}Xb^<mi_7f6s~kL2ZO?bP|sb9O&Z1gg!L#Mn_}jRJHAj
zVBcff+|f%x+ZC&UNv+}7t-^ONPFN|Cx>9ndH=h{GUkP69K+N(2<Jt546fBHfYuPVB
zl#E41bz!&*hDWWXx}NAZvdQcJ_0$E=Xl)v=FFi~MFMkVaYiOBQ$#wZ#t*c*z`-c~E
zSzP27Ngl-bpGZC!_QEYx=qcS+cd!sasiRK~B6&SO%wC-xh2#r{UH+RjJ-b9etrr;Z
zHxTrB+rhTkkr8-Wb@pJ;TZb9OA3b3xzG>_+=7wg^6LrUi+N--u1SZV%a1;!4C3Ck8
zS6Bmxnx#&)S+e^XqZFOBc7K2EcB|=vUTxSo+TH?6brH(Yg}d&)K0>zK@myzlr8WP)
zwZE_e^gE^hpzf$|y#Ua*g+iT4>N(bPJvh6s-Zf=xbdrA~-r;aR(3{5J-njJImOILy
zUHMATes}$?W&>6G`1AGlT<SZOYx#WY#9c?P`T3X9&qjCU^L1;3aoDcD^TD~jXY}FH
ze-z0l^o34{M1xv;bVDNKGwojdhL~t?Y}?NV8(ZLK@$^^W^*))LxFUposnXUM-t11z
ztvqpG=}$!C&0SvNS#gN&yQgumdi+$^nuB62@rUcHmvd`^Ds;Ry{GCeyY_GR}>CKPp
zEe?E`W9xV2+H;|(@%PKVUh}40wrjNgaY#?y#21ZwYyP7~7lH8h$2rtSeY4RD#qbkk
z#-6mDc1qaj4w|@iH$v1;8d<G9S+1QuK5^a9{dOBl=iCfQB$x8-bSho(0&H%~lj-~1
zjs_U(MHd9|q_F^J+^%WsB+8*}`>boF?CW!hLjl-z+qGcAI>;uEOsFs-SlRa<8nA1a
zf`c(wugfZ;@!6~X%9}zaE)>mG+XhO<z@K%lO@9rr+_t?RgS_QH3!ea(#gX3oT$F7l
z`(S(F1_SPvdT5;Bwwxkr$9^zeu*?&=Mc4>T2Llc3UiGcU6<Y7VDkdHv_uerEwMV%I
zhwiQ^Jy*+xq!+Ewb+j$C1rNb0&^7IG!c!X$nSF;AYDY!muJWm%aeUi=Yk{#fF1n%?
z>anjv+GUB;ZcPMFe9DD#^B}uG8>k%KsKM5NpZH36^M&U$q=!Zl7(svYAJ@^OxSn=L
zalADfz6~F`u4AG6-cW1u7%XQ;7Fxaxdq1Z3HD2@)Z`s|^5qB3TJTYf<c#u5OaYnb~
zZyrnb0Ii8_<Usx}E*-bxH}ZbFv+X+;oW5K2qY$8O8(y%IBSHCIJGqpe7U=*A`GaDU
z-JaxS6xTzzqmizqdHFAp`T88<Cc!xJL#i*(3t^GO{E2uKA7DP*FLuNKc`{mZ8@F%8
zoQTSXk8xgySHnE5$~$}VAO6SxGBjK~7M;GhpPV9V%0R#{ZTJgvdH_BrSDYGrHQjCf
zjpr}>=t5z5p|4?)%*)M=+U*@DVff+}>!8F{em_@fw)H)B4!ih^tdo52L>F(T$(mKz
zPfyu3>k!{bKmj+zEt~fYkZs>#$+-Yai-x_y2x@wjxyQSzGVpdZsM!-Mffa&ozY6i}
z_RkooiveP~bF>c@)387f<~xf{U_+7(Uzvk}*h#N`=Vhs#+E>@F-$iUVwX~K88&={u
zIJM9ubb*QfMvJY+2LkeFc)OsWVpS<0CG)`IVHo02u$|_kR~mC9|7S)g_Yi#14>fn#
zZuyc^&lv}q(>`Jx{hXbA7h&h&!!Gp>r^f@hrFXciQH@#(cZ*1%Z^5s7!PQbkSIVxn
zt`xW@9<L|}228le?m8^yqZjzPZJx_9k^%%DeSy9$l4*MN3)hFNT{LwpsgJhr4P9=+
zln)%*9hvJRt@$;u3HxlLr9odZWXbtQPKpcF6!rZsQuafQf8Rq}+-JyDap;lXgWpwj
zdgY4m_BVcT;zo^MH4<Otr$_j}+1Ft>0r~fKy6-V}u=$dW=Myb2cRgkdHrmp#87cp`
z7FdwEYtXAdcht7a_a3)W*G1yFIeW<6=vq_8m&0;|(BC(*)1|NwCVWd859QTEB7lc=
zYFvRy$vlE0xx~WLAo248Pt!Zsyn2JcVup^Uf_^6tKNoG!y&vnjZqs&~VO=rAJZdf>
zE%?P<*rgq666SSu6C?$+sHK5M%Yt*k9n4)|3*upl<9fvZ33c4^Ka6xV>{nN)v|Fsu
zeTWh+^#l;Ej}G?<XJgteqwn;I!=$g#ru8*8ar3${vC%cjwg5)oa3?{6=9IhWK`y-y
z#@mykZB?mlvt7*z1)}n^(wFC8U;<RHe&L-paYN(a#!?1ZSUrP!+eIcjhV-Cw(TW=O
zuvIV=CsK>X)1(cSpys$N={>Zp^vpO2$l~Vr+muEApzQ@}1~tr$7AW(Gl_KPbow2)g
z<0X4sZmGG(+vJR`h!!x6ep{MBsHfy|HG}%w4z__<SQgL0u8<-J5mC#G`h@^y)?u~#
zra{{vWZ&uKZ=nx5sGd1XGAlI8z4Q4F%=N3YJg$vB;vu)A-+!<kYc*CpU~T4yL|)e|
zOzC=|!wHO<W8eG=FdM0w3^fOlBZyi3Cd$TI0GvOx^b)|?h}57~ee#xZX3I$VBjJ>8
z!@(MUuEk*%=GPg;>ks{37rg76KSIaXTk%Qj4a0flu2tV?;M>#Qa4D?gH?r>{yY7}l
zi;xX23KRajH3btl!Sl}v^u}kWR$Z+3cZKM9WZzAcZSTV>2QRZZMA@eS##c#p|IbMF
zmLMe15P<)CMEqZK^`E`U|C{Z}4S)4uE|xwFeNSE<yU5-JSjW+nS5NBx@@lok_g=m6
z6)dC%K41R<suXS>obG|iN&dQZWga^NI7JlgTZ#&{YHqlPTYVH)>Gh-I%RIZnlPf$s
zCms+}d^`S)pZ5>&^JBh&KhLahTGV4LgMQCX|8n+k{t5ZYM}I)n*dc$Ck0T&0#>3)4
zqC=hc^X`PGJ0@#Uuhzd29z;YQTHVRqJR(W*@JZ&Q-OW$Gck^S2!ZRxVg}cI^K5lM|
zZ+><4QnR>%-Sd+1o#CL^t@9<v*{PG3uJ!S+xv~**w~Z}qBk!~67H<@QNF9Cw2BwUZ
zPIXXqyXfU<Vwqijj}{P5ca7gO+`^sw={<8PJ_(@IL-vfEJ>xjwu1ZJB3zBm6oNd8F
zy5H{FXtOqU#4+rIX1G;kV4#G3!>gsw>pOx;H*<zt4J+-k1QOrVDQf}1$1TUMJv%9J
zD=X7)SY|gI6pEd3NFhrli!JE$v6l);hCA{>&nZ3`>tg8sOTCIaMGv}An1NOl6?<{e
zl+9a5ijEBA5^}d9Fsf9tERX~97S?+U1-pc02t_&jH6p)|FpiEedolo8D@K(W`!M9X
z3+N1AI`%8RURC4iM20FHo5${ae`-6sLy_oVqh)|weKvcrpI00u9$OnxM=JK3tyKxo
z#N|C&yGuNPZB&*t>dZ@MXVBXQ9oq7ae}*bZFwZD)+qUEuTf;H7C=XyTs93f<Cly^~
zsEh$9P_r;bKEplO2HQj{$#%+8x@^{5_!AG?>y|NqLQ=3)<QgM4o85upj&~;ZSd3?s
zg`(`_^ltrvMGAZJ9x~+#&FpasGBqLunH%%a&YG5-QDNLA?{E(%cngmzNjWJyQkULZ
zvm9i$!VS~P*aYMukSGJHFy>)sgg)8{&xTVm#jNQ<M+rK+e4YFqHr#j%q%uEl>~SRy
z5f|tWO5T|#V=4wH50uX>$q|j89VVXFD;sT=r3Ucu)jeHmr7>Gc+HFkU8Q2)baXXgb
z8*M|f>2ll#kLorNN%Wu!oAGVp@(E=JqZ6{7sT(A&z@rs%^g3!tYF!oGolSeSEdelW
z>2X74nPzW~zs=zA6!F&Gq4DgI=wLh=SUtqHmSPB6T!f$UfbR{{-eHoJ2Rws<hc9x2
zTcaJ(4(sEs>ti*m9AJZ==&B}Xc*i;48zB+pc`Mb4+JGFF+CFI6?nYE3j2p`nQqq=l
zZcx?7@~m*%9Ga$AXj_RnY@tTn6>r=VmJLVhfl_cPeIxciZ@nkN2bQ<9!>I^DIsS2P
z0F=UJ=Xj^_HtyKx6iD~RLZk3Fzuy|{!A^3R9`0h9*qGObnuO=-dIM_7Nw39Cu1~w^
z4Wja_*OhG<51MXu*~kpyK%fSIT}kxK1h{t<=c0qmloDx3!Ht8-3O;@%n70zAT&G4#
zE265Rs@Mvfhs$-RTNL_A$WXSktsOA3v{A@uv(Y*l{MF1Sj0nY$rt~qEf!;c^HuDgR
ztOMf}R76!riWqBp6bUg5DekWeBp`4!eyiKkH7j}0={u|?2Ffj21~iKZP>lr=de(5j
ztps=+)U&|gHj}|$jmZukNa<oAqYWi#2_jU`ykB=n+>tG*OcivZm}yyZQE_ym1#ZBg
zbMOG}j+rto0x?POOrN)`67#O`{=m*b=`9d2AgNp7Q3C`BXcig(9d<Kwn1|b$GK6FB
zw}Cs?0^h_e4J~Ies>1eJF%Qa<L7Y<6=rZN3a&>Mwqni3`jDhum0TThP263SY4J>YL
zj780`maGJCp&`b$&fp%Ba5u4HNtPtrclql71TZC%01xFLW4MUw72#UJf*3^fLMl?%
z2z{?J>T1Ll7azkCcd!2amPJxjsRiM41h{^P4<@4ku3o@E!&qGPx7sBYs~87<3Kq9e
zXCO2_h-gj`|39u;_`<}EopP<)#9?qW0SPgl@HvJb4##of71E9<E%T*CzkpDsl9Fw&
zV5r$Z1RAs7djFHAX0eLQXrD9a;H*qJqX3EFOeDwij2%vqsJJ&d$Gf@)kSJK7<h~Sp
zET;5!;uol0lmkFA<|cu_u)xF6Y+LXpm=8gosT5UX2%(CToRhTc^;$RpcV2HuMmAWs
z=vz;G(mb*O)*LK@{-zd}RxL{gy+K4F)W|Y{5!POuN-+MiZ$IZf=tKqQC;W&y=6i*p
zIa<V6hvWeS<<y8H&j*n7YhuWq3EI>60G!Y4VYdcl>x68&;M)>2Wt3xJ@O;rkQMFBF
z2<ubl+8+fDplGs(C>&}GQw5*IBSiNx$>?RWzbn?O`bFlcI@v%Md4war(YpW#r(%<4
zx<`FeDchGkJ5bKzC?I`r3lQ*;5?WAHI>6g4sq}FPqF~5_Z&!<yhfQjmmYS8jBI+WI
zkCA}>+T_O!W=YjOcyDCHsFH)WumH&^CLxxw5lM;06g#^o0LeFkxFT)VrGaD^VU*es
zJYBXsLJL2H)FWCIr;0Z%Vzxw!s-{*9ATL7wV)RsBLtg~;l*Bx7P5HuK-%=dqIm5Qp
zVvCx?O`j)%si8rKM0E4HSdooFV4>PYwKzv%nLVrfp5zTm#k!uo6>ev0Z#+;Vs%dxG
zFkx|JG<mXya3~znY?M&Qid!rj-MgqP;~iNeyb7*3J16p5x~Q32&<u+1Z9n+OPqrv=
zh-SiUkRqdX54W2s7dgXauX~c8QHD)LiX-@HppSVM;9-qvYJ;=r79sAAI9_;3F*t=w
zKW2uYJ)_yCoP?sh7U1oNyzC0~Xs`OHaXN-!-w7~jpuQMpF(?pKDR}<dCWagtJ$i`g
z2HW9To)iX=7xm0qmXs}OGQ5QgQ+=WsGg)Rh3QeiS+AF3zGm?NH7xzs|Fl<$by`rOa
z94tevAq<d*?YXvzsN$M6CP_t+00NMte4tbml5+wFI}w+_Y#)9;Dov1Ur~b)w<N@Ma
zu%J<S5!N6C?(v8~UUrx|xYaK@xEv1c;A(O<=9y|_l$vU<+>xeOoh4QH^mv?@O?yhu
zKIRAos+*!_xz-FqjT16@LtqEIW>{NAMne;eybwY$(Io^C!c>95H6rFVb3w1(o4y(l
z1fK8RsZTpB7N|S(m47w}HxiHUIivF!hIPM)8zM2v>eUYoYHT2_GxYloEVAfW$IJ9m
z{T*KS?r9Egq8sSv`G)1)<*}^M`wqXK7P@1f$&(xzB{cCaIn`YsPrbL-dQ3mt+H75R
zM&nm(_YM651ic;KuPwM8)_284OPmar5(&Gu&{nhB+ni&|_Qc7VAn*FF_~hpG-Y)JH
z+$Wvv2d|{v@ek-Jcg3flcji*g_U?|&vt6yR%QW>muO0N`|NQ6l(b$Of#{RsriIkNJ
z617U9jb7=r?`<<W92rAN$B`I9duiJ4@x!!rq}KZBuJkT@#N9zQq^9=hgS%n{=g4a_
zy$|Ql+F!GurUzRR>fo;RpXYJ+v-Lt^mc%cA$2nr#tq%0t3vF)ojP5rQ+|rNY>!)WB
z&JOgxpsS@}Z4txCV3YmS2-_zdY$f35dU|%*&o+(h4;`^{>`*%U4o_EiRSTy&&eHq~
z!-=}PBj#pbaCh_;x=&9zpNhpk9RJTS4<Q7Kg-v7t`S7b2AobWm>{daeixzWuXUtzM
z(*&{B!z7PtH&8cY3`60i^K{kxn(lUyTU-b&s`bLBX$rppczw}3z;CLDcnGoMds-9r
z0DZtscZrQIl7F^@s%yj&+jV^t0$NtT9m4C4K-la+05*kz2HV~)ysYD#gXa2JZdK%M
z!%nriqXRi;H2)Ron|2iPFGD5*bJOrGe}n(3_571pWAQp1q0gPz59(B&i|qhFn=<bH
zw7tuN>CW%cwu@FLeMx^V`TzwS3)<<XX5ZNd>$KEQ>+SYtn4E5LU>g$bC$0C0FO1z7
zB^&xTq<bzojl1JNK3hHh7hUhOYZHfh>!{iX5%Y=89Zyd;8qQ?&%TMk807eBH5-sD)
zsNJ_^tP%Z;@h9R&Er=z4D8!c3S`b9;*1ia@hzSdxu!9qu>o5WVUpwWJftt1L5|n=l
zdIO@skqyR^U$1`vS8ce?9v>}_@Sf9l>;`Y{qKQ9@RS+xugDPyNgKNA1aAi!*0;AYl
z-uR?(e>c&mhp**w$(Vn66dCgGjLwpSjBY}oOn7^!o;X4tpoW*6g?<sBD6eKt*=siF
z&c0SM;-r2{>>dLM@5#LHp17lO4qh3lYXEZrxH6=ewfDDOpZoF_x3SmQ?SA(}!=5hv
z%|p?6m)r9)PwSJnI}>O0{l*p7h3Bj6wns}B-ML`f-?%d5*`a#^q~^hvhH*U&rLc&>
z-=URxhno2hLw8`D0G;QlAbx=I&B-g=vB^((^(EH^tB1Qp%s9kT*YnTJM|-%l6o2@m
z^Q++eP7ge3jPA<i7ovdB7p-BZ2h3C7MaTu~nooTlCwM6!_UuTC1g9UnM@-xZZ7>Y_
z@N4(p0Yj4=6J6y?1p_73E;+p3IsM%qjdSZI{yEq@xNi;jx1w>BM_l)0I(Z;aP!#Tl
zZR@CWb{ypuI}A8|N0ktWPq?*c$ALfxr7pQ{Oq-~a$=hk~I#?p}4;=@F+Tyr&p>Sh#
z6ov^LBJ<|%vnO)y#E;-dU9)$u$oB5%KDjg2ULaT3>n$@RGE3W<Mi122de1vJuBc~T
zwD!|hzNF`Dr+>63v}|zl$84Ge$yXjcJ@Q+tCuT)HTqcR0!IeXGXdth>DcT%waH1V&
zG5aGS+DB3sdk^HsYx;?P6563R4)Nr0P@YKZIy$icZ0i>;s;G;JWFuNHYl(#;(}=Px
z2U}bN9=>mO&_VI0c)v7IEvSk8RU`$Z?33b5eQmLR39N75_<;Ww>{4ufhkq6I(S3IP
zzyHpn-V?LWHP9y^XD<7v2mV&bz{iM6&^(vXSRL$fT8}!g52;VlJeu(0D6%7hOT(SS
zmT+c|8-vtu<8uD%Iy`{uwp+LSZI=MN{cW}A*3jSP5N`{XbqnQ))x>?lgf<@yj)$f-
z$1%$MI0)K>&YgBU@g4U^L6EE^o$zd;_&GkIfrWeU!QNjz@tT|H1iIH=YJNaA%e&wr
zev1F7c{YVKg=@5FU#Q6LUw!Fgaiw_CI%jv2ver|h2icI*2HCRL-V-i7tb|PP&x7Py
z-bva=c>EOM*h7aWi#x5>Ogw26Tzdd11knB3Fq}cOg%~^I6Ad!WMl5TqOXuy$+f9J(
z33n|M6UQ+lx6B0Cy@KfL(+k&vz%m@rVfc20_mC^}D@bO6QklNF#?+);bT<v;NxH8U
z==rU}2|Mw%*{69*L9tYBe_`J`2ks>L)CSx?D(yK2eReK~^o7y;j{y)+-Dw%17jSlU
znz_C!XQHpgF9k~2%^YN@;8OLx+j^RCxxJbEb>poS6t+CzA4OAwSwo|K?|)0GJ+T=w
zg$8=m9jwk<2ZMt`I>-(RyDOBEr%==t@LLP(USdGlFL2Y~T#^G~ym6L<!e^dB7x{G9
zIbL4@yBDxkVdL-84)}_|r~Ze0Zh8g7g!m@n4%Mpk)$iW+>Q8d$MbXD|tvtGiwy8b$
zJl=MT_Xs*r<lUV5_TI;H>Qyps;bysiLoM3#49&0c9#T`@z)098o3d_ZhU7i}-JCNZ
zI!+_7`41yPK?DfaCBp>zYGulx62$)FY(R+OXT{+WAaAL>!flwE&w<P?VM6N@l?Khf
zi$Xg7*g<xP#~>+R;@O6+?-UPW>xQ;IztXU;3Vslb`;b6-_aNlzU;4o(tKc`TrDlAH
z_6EB0N*}^2Fx5UnkY2saEkquDe~3ktLO)4z`F`B_PR~hlyVep@3Ueb;%Nl7Dlsbui
zK&NI4TFO+Y<SsJoX&0hcd21*liT$n_pv;oB`d1lef$Wm12b~KHK7t_3xdB7R;*U`E
z+tVL^>b$KYjg!kAPN>>W!#^AIJ4Bp1!a0kt5$JE=v4}N*4=Rlm|FEp%g>VUQIG3`P
zXtoYTIq<aU*hgqM^Q-d!I=2W|i--vj_x7=r<=L8E5WxZq%wTo4H#NX*+uIX!7r8eQ
zncHh~kzKdQT|3^*T^JT4BTI^XY1^;F-~G&KFHHP;_vMf#hYlov{BJst{E|rf{}W8U
zsfmt#>L%F!*F^fye#W)Iw|_xc4Xpi`{o|W_`-@%w;Qwfx{AvuG97Ot9d}CPU(Y@6A
zOMLvg{qIP<S9$#^DE}q@?0?f29MC@0d54Ru4I$XR={<6c<R5!t4K`^|HDN=8e?NVM
zpGRCDJFbvL&x!FtfN1=A#W&7YVbzIm4*D(k`h1GFBz$AAhW~8239Sd+)t>}`i1;DC
z4)cnC{uJ(cq24yRihU1u?XkZ)v1av6Lo5`5@C*;^j=~Mr&ma8er{Om9=MPkWEQVW+
z)yFUX__sSh(R&-XX5Lt9S#d4teR+MIw%Dwn_XV3`_iJs#Y=O1hQ!gpK7Q5X!qBBH(
z-|eslm*41&#lPiXcT-@=iqp;gN!@_tNa`cTgO?Vx$-r|r@pA0(SY9!3!g|FPHddbr
zR}aV~Ko9qpL$Q>*5~e>hS3niWBf{<UtF`n~V%bPT^TL8o_a$Gpi}10wmYh3p^nO7C
zD%Q$f#)4#VN9Q|@kfU1BJz+9GbYI5$eL=)wN<<%Yd$fWVBaSy~<krjwR0yfjLETWg
z=@sqHprqKta6`5-&{-Fu`9;Dj5~qu{4KN0DVrs6-7G1IEv5dwH78fuZ*H9%x@dLYL
zGy8}CvVO>uq+YoX<+<cOBz$|0;g!|4=ziiJ(ewS}uud&_0z(;$!enfS1<$_2Mbz;W
zBv%+@*_*eDo(eZ=JNlY1(=l_<_h@9og37KF$so3i=mlzg$*9dZn{o|TwBP22-441o
zJM{u~r#3W{Zc#2WY``Pc8wdUpY#~>Qg|#JN>cXK&k7!ZzjsYtJbald#jXKvmAPhvl
zcOR!O2|3a*GB#D51XZla8YiRJeU8-EVbm8<)Ruy*K~}yMwH6J|ivWSx_%2ezpZ86d
zF&XM#bk5nC;%qD^E*Rt5gdOGDj`NW~UNnrpAS-7G_U_zh@}gXqiZI`XM}TF@8}UXC
z)8h(@Y}2K<)`OQekdDj&i)GF!s5H9wxQhFXz3oF@JD(02AQH<_VV5JW1M=^$L+Umx
zOjudX7^-;-)RXEGG;TA{ubtbq4xDhk1DE1gWK*u<H5u@W3~*$v?*tGvcv&$v8S#9>
zvlx=Sme4-0LN96{DZv?xD?RqD)`I>DgVxl@X_s|4fc!2nki)sh`R4UHv*y^NFnKV;
z!fgR`X<Sq(_$P+>b)qP9b3LTIVV#6ce#gnQTX82muKlM^MPhq=EWov@DzOD*YU*i2
zuLB`kWfnEI8E_(ydY5!*J5M;n03GpBR-%OwH%qa{Mx(z1&q|$f2&}s&vwcpX$7Yx6
zQD18rtIY?`*>dwLhi8T7`*aRIwkEvgt8T?cjowuY_!ZJ{4i7Sb2)+7;e({K5wpmHE
z;#Sv8qGueJ{a+(%CFvk#EUazDD{>{OW-!n(25(?w5m=FR5?Vl_MJD6>Itm#ANEViT
z>8@L?AqFOmiy`q1=oILFcrI#4J1EI$#R|%&N?{l!{QYng0w^^txpZy$e~-i{e965q
zhKI})i$nd`)&jcA5zS&nv|b6ydCDq~2LyW@DWitHn(0XkR0)$YfLdgNJQljCi@<`V
zuAz*>9n1*d5S+D2G%}BSRI1vlJ_99bLNSCJ@zJ&1wO9Z8H$qvh8A81w%1y+5Vj6O5
zpdMDJWwKFRPF=;J8f}JZJOz^jS3-iCUxN=hu0akm3==_aEyLCDP+L`;Gvva-BK&dZ
zeakK?oafZyt+*VLGzhyB80bhD_rEV4T>TDa3?+lIj^XIy04{bg+-5}#uM*&rBNHIP
zB*Htl`i3JB@GUDD>mmV`!QlmzIG%BP2)tDI^79zp@fuQK;=JK1pbg?n*SPS%tmT-m
z^o2+)yqoYd;SYsl2<RQ-TnFEVs>Tp=bCM3|<b|z6!yh}$g@o6d#ED7x<?wwlqJ;m$
z!0iFCag=CbM0NpheR=xVKZfsE_|@<}U2S8hB0nojR%Vo&a5yJSB9xfa!EuaOBu><g
zTtewxXMu;uC8R*W1$_{xB~&Sg?}TJbbt0tLA3cf{#?Ub^t6gpV7QPn_a4J4Jc!7x0
zqM5Q|M#mWP1Bh>`FTuyH#E0v8j?5Yp@&!+YVtzm;$&TmzEOijP8dt~B_f!D3CCm&#
z(Z!G80^;ED?h%#a5W-V2IWBjAGsU>UuLfN>LmY4h@_cmH@JjNGCLsuy@e%EnFydKm
zH2Cd+7Ll9^PYO+XlxjF=D1!k1fuA97Ey^Z(@6CsS+=vkCM*J}men%&(&(d2@ti=WJ
z6&AjxhPN;+4-P$$Jma2_EK^=UuSK?lz{cnWv<-KVn<8R1x;9*t!gPbx#3W|Sh2e+Q
zmR~(1+zKAPG6jPy89gP0(T_~yQsSGL@N$L^B%DCiFLmG+?arf}rGVl5G(IFuGzde-
z2qedY1~Poz%n3;I5Etq5i{Y0P13AS<piLqO4zb8@!$oz$n)R!vd%$xwhO5SK_;`zq
zvf6r*CFRgZhB!KXao90($ig|o;S;@*P!SzxevQYmXf|*?^@`{eR7gEYSA4_ssf!U%
z;!TMy4f)K=sCaD&1QZ9b&R^|^8Q;Hl<~+VD89iuOTm{R)5QjStu#c6ZFf>B!wxm`(
zfq!%H6Na{cj4+H~zK+}0R150XScJytx`K=op5f>(CW7r@?+E+F&4<AS-dW&MfzOBE
zy!!kzCdSdXYf)dN8H4ElTFwp|5n~W$XzZZHk*rf0W={M=s+aEPrCY1Be(ADBS5_u@
zP`SKt+W&4_eRh)Zr!Kd+;skp2;Ip^3z1Pu6+x;!{r2hCaUx@`h?$aFUB)=hg8*n`l
zyV;ni{DzpT99iEJRyql!!_^|vSa%9$EK-!DaMb}ZB&uAKiq^WkrOiNh9O}(u4}0OV
z7DH{1R>r{QU_4&IqK(4<aU}sWE6y^HA^3dH8Q9<WIc+jl-(5W-N~4!6cl(pEo{=d`
z`2!n0JwJ?@ec+x$qn9@XJJ@#TQQBZxIWo$;U{0T~D&G|+*Qe(yZF6&_r`LOl6~Qs1
z<5IqXUNL8Cf|=ayHgYH&k64f<1ewV%F!X2{%bk+E>2pO`c$R(J!%`_!Ka~v(`I^B)
z9~jKvP&a|-AT6uJ9Ly^qu5)4nLLvxv!%qW4Us;BFG{>!LoDgFJhr-y{Fq_pDc{Z%-
zhaaf8p%xM574TAyapdM|9N|X^PZ>3XQ2^r`8oIb}=R8vXutQylN~yb0-u{uVAW6j6
ztn&E}`blK4k{r+>b;aENgs-*tmj?q2)AMuZNvKZkM@+202@eOci?sKYSB#ueK2Z7b
z<y@@#*~acscqlAfTd5Y#0Hfxw_*(XWFEo8xRAUEbf1f-<^uL}fxZaKGGdp2s7ya|P
z&j!v4z5E3II!6eg-`^n~tquyBInOn=+xxD-*&X8gVr)WVcQz(=d1<js%1^AgNEYr`
zw<8MNzi?;p5@-RRPbOsjH+TF>Cfq_h(yO0uwaS`hF>YBnYrbH?G&PD0=*j4FT1oDK
z)DWf2kYxT3cKz<e#m1QHmj^F@b2)$OZei4;iT%x49(h-&Z=c=IRRF!GbICoT5LH25
z+>^#dfg)<sstq!d>Z5%tFxo8(ZBiWcBaJ(Iv>~5LhcF_zjvC;A4+vMo@fu{sIBIDr
zY`P(wy!tQUfXp2$L!s`@E38Zu9Qu5;oL~EPqrU;ag#}saqj`XjZNxA8Gf0>R8>xPs
zoF;Vetkr%8&ge96M2+1v&858h==u}XPgqAnoc3k(3>Fkm8s`ctT&e(P!UcDQqln;&
zui|Z_w^ookakL)?o;B19zLr;mylRT-9x;VEWo0G7V7i)sBy?Lz#^O|(p85m^2gkyU
z+UGh_-9hI~c=x)}!G*E{<N?zQsRvgIl)H=c2^cNB-MoR`ni<R`Zyhhxp>aLb4E@de
z&yvNNTsL{UI_75vg$c6Q#Fdm^_i-#cdHCt{${DmjEN{>DYFA^khj^dp#dk7wKoT)g
zRmF-ACWM)ydLmjx6+jn9c?;(A3tzZJLPH<`-E+?fn!iOU!<{TV&cQ}_zd=^*t(AJZ
z39DO#p@!uVqo?CEK|VZbzZ<I7D&Cv4hfh}V9GxZeh~B72na1aZ9v>4sgcQnsA?p-p
zxIix!VYB0|hWYDlQZJ(85>_>fSe1lx$B8Ih4AcYzbCgnw^jGiQ8Xg;j5urE|pCYi1
zWfWjji;_Uzv2;IlEl^!^r>%Z>`~Yu72+ZgiulGmbP3^$=0MEYk`o%Y^u)y%f9D@E9
zIZx5BsAub|5-MOu%V^SRVXU_AwD8sWJ3T3&(gZSwUDb3|465e3(Dj?l-znWZtm$9<
zI93W$2Dwa5i>^3Mc(>Hc38kC>37xh)d=GIF#-Uhe4*WBED#PO8aY&Dw59iwZjUMXA
z4?NW3$S>xtx6fYt=2?VJIv#Y;1E(ttvh*oo_KTg>om~3sDwrMU9X@>(Bg4%;c%Euk
zXP?1;T;<grq6iNWH1R~^YzV_9PS9clUGYscavh73h8@mV|Dhj4nN*DK!HpAYH+3DV
z$M6||&Iq6dg;m0PdJW#XC~DUdz(n9ikahb;H<5eM#eUb%ytDT-S3AyqPpGe7Og89+
ziec|TkDo$%CXBxaVPMb)uy<n|PX>?T=6P%709WUq?!jF$NX-Q?Px-`^SlxlF)`7cl
zpw6FNhBHr-%)_K5Jh-dB^Idd0G_K=FPPZEwv?UxOQlXuK5qL_`^La??12r-;pmz+$
z+7!pLczKrS#$k?qqG!tH@B*`tOo@Y%dYIw?49@WfVXWg(EK#T@HNEiJEAA0Pu`xh8
zABE~vAI2F4G@)!`$)-z>yeE(2a59)hBR*3w_P1eiv51X|WI*AD1!+;uTsG>CPD2}D
z@w>iM=uja-<=)r1qgI8(<)Fx148q%?K`o$Cdk}J)LO5~ZM6qDSLI@?gfA+%R!UBd3
z-~QE)hd{3P-v)Aj{7WpY?HApAf5y_hf5p=Ne~^g&*)Qo#S9x4W_5NrCGF9L>97*VO
z@VB*(oDLE<eHV@=R;ga^_a;6PtL~e)seV2EOLhq(`yQ;|MH;oIer}h5(+OY1g$L9{
z@5hG*U`-WT3Ioc0;h%2{LW2a17~x*%r!r71lQ|0)v<x5c$tq{l0NBE1X}DbHo>Y#h
z)qda04EjYZhjG2JXw$<T4=nl)uZBkn@GYXG;UMH{MIcmdp8Jpq2g=pgeiXhCe(M(=
z9#**4&97JA=I8$f-QLf?_{GoAcd%T<zpH$3o_UcKXSC04vKHTmzu-!~&y8rtLM7T|
z6#Ik2iF(D6A%kJh#*CxHnD9^@Yz#y61QaqYV@_m*Tjg=?cVkQA2+F-ao`MVNqLGMc
zNHRAWBsdUpRAg)!Oekh5YYVfYU~9NxL{UbjD7rf5rsW13vC_iU^{+;6>EmoDh^)Qe
z7$DeS_<%tg{NkjZKxP?udD?eqKCYWIWHH7(Ng9Bn0~a?TR4;A>5Hrah_S0+tyAO(e
zO1ReuGph}0Ya`-xjEJy#u+iYyUzo_^T^e(XY8R4Tul75r^TptMsBxareWgRKV?&kz
zGV>#AUqH1<tj032!GO2y<9x<x)x<`t&xQ2H8glwti8bnHM!h!8!4@WhbZCwpPN*6~
z3&IT0Q^VnaN{nz?TtVIRutki_N)+3op{jwvJX&k!+ijnS43e;`WUz6@w!w$;1ud?l
ziJ1hr>wsI?%<<RkwwytimPat8gbQp#hmTW_T}C0fOd9=*%aAW(@bG=qz=~r~fkS50
zh^1o@9*g-dv_GLI7mOSU%Y};{DPH$<Qgq5uZ2+07)Yh;5<=(!qVpa=8!(bl>cW9j0
zJp3c&5E!>w1YFnm>Y8UWo44!CmLh@PB~V!q3*yMSEX7`B(a*$!^FcSI9J_AGMM|iK
z%Zu}qOz1#uu6N-oc+j?$XHj<uKBC4e3Jqg!MiUl+!8`u&WGP_u#shz!A<8R+s3oPx
zpc<*_{+wUpp3uQD&iF^{%I(;?sZ%2cX?76zc2`fW8FhBWoqBl>#K%-K3bEKAx7eh`
zGO2z({P`f~pAUC&JgUYute|}`+ygPOgjTC!Wsx>|p^zHf9AogJcRHJu=K8G^l1$#?
zR_pAQAjYG-#Zm{Ry}HikhYMY?-RvpXCVWe!a0vpWR-v!=W5U5U4>j(xy4KZ)B0E7j
z=0E0+Kx5bCW6uEXRY49fU&J63ft)B}{xNnqXEDKxOD?y<n+9r>Sfrq`t%b_U`fuP?
z(j#i`$(RE5T?mKI^EZr_uthy&>}Ci7aJPDZBTbuE#1SKFGv$@<a=BV#C@D#?%&TKx
zUk!wQ<D0)G(XEcXBo(ns#2BVYM~aY9J!^X+oNEALY<$Q-`^n(<7-mSDx}lhsY(@bu
zA`LIA>KFqeu|eM*!cXdq>W~|S8x}i6s*^mkg8m|*_M2Z+=3`70le+6Fzj<_*QjBU6
z<(NtF0q;}=ZBio#{F;R+5tgV5=B13*CinSCPjv<X0m2~<yK%2W#tolIH&~fsa4Rmw
zGI*z@pn`EyFAZ{rFbD<|34=wiSW{^oW(M|7kSjX~ZvEP>Tkj$0d?jEb4ADShDLFjw
z$PA1_Fu-6)!DzE=ctCVGNdYG&86%~MOzZH0a2M_&Tm^s&6IKp}G$V;c5%{ZSmvTg{
z${4ca7_aScthxGs{%1*Q(TYfZ4<}pvegtzi1C7V$W}QgP-zfY5rOvo-tI|a5n2%vB
zaK_U-aDw^uP$>pk%N0rpFo2(sz5=q&Jba~iJB&!$wK2G5)rv|uV+cJ~!%)Y(n{wa4
zf);Pee)G7B(aZ3K1?k=pccl^q>42ydIRgtZa}9x0ESh)_D8vzc{&>OH#@F%8L)?N;
zo`4<n1?GT1gl#e&RRynwEds_-Y0l(mAzVY0N;{02rLIuXO~duD+c`+NBx3sC=@E?G
z9-$sCqLIN(>W9--M0?aw!j-ehX`o8aV#(t#`lPT<@_esXwTh}oh8%M?Z^{@f%%G}>
ziVzil-44J)@ETfK;dxD<xq%F^g9rh<$J0EbQgmr7Z9w@VLU-7WKlz^|pSIw-m$=G^
z1eAl5=Yzx`TYbcBan5Llh}v?NOE$u=uCD<5O2Y(jk$RHnp*x$}Op(bH3;;hGh$7M8
z>}7`?0NoSUBDmKbepMvaRYRW@Z3w{@@2yb{w^In-2FL(T7_AH;t3phbgrOR>szxxE
z9p+NumR@ZfOMFy6BoTE5QdmI+2Etx{or^2#1HfSg>Z4yMZn0(|H{V=_f-s}G8R&w!
zgw_lf4Kmgc+?F2MvTpT!yrOd0#f5ey{3H$<5AIhWR4g6~`hpJC^D<gBR^1a6xuaPf
zj-di@<FZLMD*{SMXy@=YXJ}&&Yeb%L<os<C!6bomE-HA!<LVFI3|m_D!-2uZv4mKU
z--Eyr)}=)@jGNV!iUH@iLSQL0SOl$-q~a(XqtU|*XO5fQ_?C~}fYqstpAWg&m|#$;
z+orb6QFNoR*~h(xKUnpQyE87{8t3)Z*1QrCvly=Cvx~T#Mb&Lnhl0a)aZUJY1_EIi
zCZtF==eUWn@M7i_h6~Yi-uG?Gw}mD$>6JVd_ltfYdRNf3=4LAz7aY+6(JQKJg#>}5
zfkXFjP*~q(!hKg(r6w~trPtVS2KX&+p9UVq?2cEhz~e;oeI{*k_0k$r3GWpwzK6J}
z`a_iPt%TTEc@xvI=wpyos!%77QXCwP(l|Ve^#Croh7|`s;#%Ty*kv}ZH&!Qj2?<b>
zo2bpZM5m1&a*rR`^^9KvSGs4;zXwrUVw21W7Ax9<UxHt5b+`<#9T!Mnv5=TikCjH9
z<sdog7O&8iiAfj5CI<cS?l+CnPkfy?yXNxlhl0M=T+Tk^mMm?%7(e~Y9>0XZ(GgL3
zVTL8rTs(D!jjdG9#KfOh0X%WZQXfFz2dnq`&bh|8aNleOd1a@+v{!>gEF#cZ(bl@`
z$5;Gd<Zb@-&<KLh*%M1f`Px_hhh#NN>R7INkAIL(#{8<q`Q!eKZ&Kf1L7~0bF-~}C
zls)^dtBx(^=Shh|F<5tczvbBC1Bz|?Of$RwxBc<CYR?rb%?Esp6{mM}WDn5g=84n3
zJNL{X)C2woKNOpC+*-Bc4S`d@wCHxmCXH_}qW~5FWld@wsyECD=2ncAhA;MYx|64u
zDk_p(W(TtxuU>pp&6jH3)dopfJ-Af}D{N#}w%pQJ!&vLzI}((kmb|aTQclxlV<QK#
zLP%kCh?xCBR)J)3m{qX%0(^Mec5W>?YT-=%rrgoVg$}i_sr_`**pAe}#VSgwDFr01
z5d`SBBXwYk@9>8LR?A;xGk}8e^H2iqM<pxp0}znZ!jWvlDb?6G>}$`hxZ*Jv7hL;{
zQBEVXg`sM^p<Q4yJOplo#v<m-8gZ4t9iX?{oBqDiGhkb62}PZtF+wdgq<h{mU~lpu
z-PzJw+gmTy?e>xKjKA;LUE3RzbaNdE@juS{V@Qb4HAbfc{XDdGlXhhR(locL^2kGH
zy~)l=v56+{akHoS9J!in?pPTTP+o#o-N-fDY3bT5f8>MM2%9*-9T*(`h&B@o$s>pO
zuKppvprO!PwfBsE+Stzl?OxFejp&XeJ7D^1CvJPmxW<Lq=}wFN)B#Jm<I1ipcO1c&
z5HL<#*P7Mr9Hdnj3uCA|wBEW*#r3)MuNO#!HYn7Kg=>`F`}kM2(fdD{`R&zH-5Hx7
z+3Z5@l-vV7+bLUz`BF-Gk+knkeG%rvC@W<f2g7o0ks8KoClxaqwB1I@y@x=>Drb((
zjIf>6f>u7i_k2!eNXO>a=H`C4(B5k7_Rr<2;a5~IpKqS0>nfg6?{WVcz$tM~oNFS4
z*Nf9*QsU(7pL6&O)Q$x6Q3^8v<dtuyIE#Lft>1xDyFvNAU|gUoiDCLp4qt`+zN>EF
zy9CLosKCW{(>ndlsxo?iT!9{}-n!W>)?23orKpx0t?hdmgCMgn)xH-s>-tmet=p~}
z##BBzE+?He^<38ouWxkr<yH>88ABmA5$yiGuMn1<<C*Jx`9ZK}2ti?3{KDUlb#QiW
zWc{+S+ha)J-|lbs=ev4<Dr1S0{0xXCj5R6D1ESMDh?SHW_Pu>;5^y}YRQki}L}M>%
zft{xyk$ks*qQCF#&ZZBpfh$)%%|98|Q}Y*R&vvLiI3s)YjJ|Y!jn|??>U7^J_>KBc
zJb%|J+P!Yu`v_WTTlSO>spuDt1X}DnR<!19!!`uHm$w9$0`d>Gy4n3;r3u4{@^zXU
zW4$Xp^A0^h6BjKnaIT5*?R8&2dWHz}z}|)pUt=&|y{E|&^(g2n5S}PNRCtJwtDtHd
zW<8u)fD3tu2m3AukBNrwqw|Y8PGzFrpMb}3AiX8N?$o=GYx3yaPXr}>bRKNCzp%^8
zpMG|&1JXzGvB74K%A7V10Nh1ZTUl}ra$lcHlwA-kIC>Zk$t!#l8T-Fkd;jn@?)%Pj
zFhXg>Q5(z<LJ=-c<$N&%fiz{Al$2A|w80E#AV{HO5W?a3uv|re0Y*(X8%xb|>$~ed
z!GHsYa_H1n-JY-8Yebsz>auPc>w0~1Ke`cRFjf1g7hCJ?`Pyz{t9I7S?Xywb+^)J$
z_j0e#Kz4pydVd`RQ4|3VzVrQle!M^L&*%I3Qha~)aatw>UtB*?TRRRbSbF=$;Bl#U
zt(>sWM!$FC^2%$Icl?2MaZP)G>bc$7MgQ^3?%v#EQA&v6(&aURCe8%hj=ZT}YDyQz
zQAHDLQNpj#oc7|v#WnY$@wK(J=MHL9BOlIfS7`Ni^jE3tKYl@b$WLky;#K*}*^Ei;
zgbh8e<&$jJCjjZw)NJxlt6%ADdEvzGw#?K+)5#F3_aEj*o`{0v?fJ((5eY3R?XF$4
z_P)aHDD%*n=_Isj@CuO^OZ|HIRMZ>8lKE?EmNC7S2rsJRYaAA*WSjx*K&JF#K4jxu
zlHnfnVa~PBM1`%{F%Cvl7sF$b_FIuQbuQX{`=5L^{T;ttN!MlG(I1UehF>l2vsp<h
zTiv%$R3=`&yzsbJ;yapKY~@8qYL{*LMY9urlb+VU^46>6r@iQ*x9)7-I@AAhgvQyQ
zC|jj-Z07jd<XKNQ_nPi~zWLB`6yW@Vf8sK1uy4NPzlG?a<cpAa$0}rGrdpN9qAk^B
z_&tueo6;ZO@~3vu`ekJ2ZzKN%mEG$o4^5B%SN}N`K2iDj$k*2XW_`Y5KK|dXQAqo>
z>zCJVKe|==Tb~OC$=plmxAwuOTcrzLev5*^F&C4a`^?7v$E;FKO)8fpLLp6y3i?W%
z^RBdNYk&Ca2cA|m<^5!9w$;Tly|nVd9<_sc`}OUGf|c8gh{b7u^~6J!B*m-Yk*bf2
zdvN_1E9pfF@HkT>HFeW3rqp^$Dxxp0e0KICU7z)jxL$SsA%8ma*4nG(-LK96?Hke5
z+?~peZ|c8sr*ggf`gyjoajx9$nTMc8LnIpFFpQj4{UwzQqe++(OZ)A0>-0vymy9;j
zBy~tYD*UJOlnU1uTj|O(UTG<E?6bLBer{y@U)$a7@z*W-?P#2m3O%;G_IpKRJ~Aq=
zcu``Ggbg_I!%z8Mk%S=gpCcaI1-A;}VMK%dbm4I4b>4EEEqw&Wv-64De_9}n%%wca
zVUnDzrW5>3Ciy;sB283)#$NO!yCh%@uF{;=w#_et+~&XhShD-U!32u*nhWoK<8np5
zS?g`%nJ4s&FmrUJO-5l4KMuw%5(8>aM7`quIb5;!SV)|}=LoY0@RNs|`PS0N_evZ;
z@Vm!<@Q}5;jOxdSJm%#qXQZs~qfcBZ^6$xyu3sq*JHI-xkl)`y_J_&}FaPfGrkrc`
zLuG|`n*i*O%L-{7@S`vC({V3>r$0F<y#(I9$lu7O`|!8__aE6w;EQ(~65Qd8HoI_V
zSSk7cRp3ZvV|a7eN8ov>Y>Y?Z#iT0x{kQB-{x9#FH<P79c34UhLQFt6k){sUXIXLB
z9@6HrmH+M&Ry+!MC5`F2`v9va)Da11&L`-X*kwN|J^Vt>!{LbV9ATz525|0fMLk%O
z-o&pFx__h?cHfAOu62`e5UI?EBv^Ro0S!bnD51-bdQ^VY58wIO+VGpNzj`l>-8LJ>
z-0WJ?BK0o^zm#%Tb5pW~zwL!p_Q;KdAp+ey5`8we^%>Xt99<hTzCN8IENagU_Ojtj
zCm3-ju5qXfWJc<l^t$EdQZ+UG7PWP>seHzDmG*~E6=B`X@L0G;wz^0DGB<m*sM*KA
zdF{(=&0Hmr{m<_F)pHZc$SYC!c|Ji<j0Q|teu_=jx7L!5{#m!A64plwlr5y9|9-m|
zJ`+00U!P7$!eE5aY|p>4m6#3}NRq(s6ju`(WJdS>nUu-d>T7wTw6(4kzUNrDs(Z)6
zb+wI(t%j-f#G0>-t;u0<3HJRk5IDev=v#~Tq_;9vLLQ$x3?=sDi&45a0)2%gU8b;`
zh}e4#*8okXSQ^((>&mb2=_Q7}n!sgw5yfDoRIN0dTO@!L;z<KHCj1GQn?y9lxlB2q
zV>+(bDH?M=8QuQG&k)=CsiLnYgo)^0C`QDYMdIa&3!a)7;bRLaxS&b>I2^J{XO0|N
zB_VS@S<3j)U_4;2q@RjHm|2g+EY*)G!n27)4bJH_6>e!eDMSH0$yDNq`(*jaLx`R3
zg5M_CLl%De)!n`}p+5!d+KrwnYNLtt3q?O^(RqT3wWN0?ozV+LKQ)nLD>%Ir3A^hR
ztqhT>c_rac<RRhs#Dz+6LZ2{G{)CRIBu~I0d0k!Zo_CdsZc5~yZ_VE^f1G4fA(efP
zs+`x~|1`}%yB3<Wze34c7q+wVn%defq_`YerKgLLN?-o~2Uvya$Lke0I{s^zQ({{?
zIq>I`59a!rV(1G!F;Px&df7#DJ<^NjX%8MI5h`;1+h&C=s3-KIHppEyyP4!KB#$5T
zbJ3A>a`j+FikY%^&OQv$XFOA!?|Emu^Bm9}rq>P@qxDfvFjkdlRX?)orMed~#V0xP
zRD%wO8|{xCDHf8eFJ`j8;hR%NvDu@lhV9Y*ncl`~=Ix5QT2VQ-xA<b>xJ5U&g!;on
z#pB8Kk(_g-l2}@cib<)TihA9I`OIlA>ZYbb%el2d#V&rFvbQ5{Wy*T{&ac9@xg1Or
z!pTx}5l?t}4O!3HI^w1<6<W9D67mVh5|!4B)L4(zN_CT~N$Om9CzU%;IS%W>zgmdu
z$o6g?HA`arT=!&!<G23hSq(2%te@}cV@k1JqLtm*3Y2@QSdhYCO>Q32i{b!FS8n&<
zc=n2Kg}ZVJdc&nJ&E{3Fq(8#8PVLu|S$2+|hcP|vTh6@`w!4*qxmaV2YrU?UB)dHU
zWw{97uDVi(%Z+{MGe4mnHyL`;M@+)=bP)D<1+kU~H-|FCkKqr}DuF&eP-I(u#6~Dy
zMJn{LrG@2ZDm_m#yW9g0X@Sb^dKwa)-hz@cD@FIG{`S4Rgj6HCW9=T_pN>k2t_L+4
zKOnArsdCil`6ypK=%!+50T=jRDY?y$auZg>yC?X<v~)$$`Qew$q*n3#Sy6_B`xhS+
zUC<_Osie2gc2p}-)J~5=h*f9~t%{a5VP|x@&uWuVkFS=8E>0w+?Kp^=(MRV=T484{
z+CEDaKd98=^9sr0JVq+L7U|t6Ve#oF5*O{;|M;xdl>w;x*`RwqQOS+<_{7&tBbDj)
zGKSt&rVdL4(M*n}!oqS%OKy<qFGA9j-3g1OVzRUw747Pi30ZLw8ymBdtoZ16h%!eP
zm|p0Fv1E7Cod}Z${=4C{b-9Nh`Ka9esXhFc;mYIg|As$%_bXKO$)7|Nc?b(Nk>DG=
zEbnG4{2TKBp&IZrhNijl*7(8a+nPi48B2;xAZxDS1gwP33c<l8|0!1xI$ld#s830;
zKRwjvDp-dnWst)cv<a6NwBm<xST+eVEL{8ocW;`uhb%l0@#awB|7^zhep_cO3{RWm
zGZ}R$Y5opX*6^j6V$E1JHxx|~JoaX34@9>kei_y0)*$+=nn5{7{90F^Te}jaiWR6r
zhBA@BHP;NKm6X5P=GqlrWSA^^h7<zVoqFe0Un@Qk*%Xv;UHQ-t9sV)MZEhhxz^Y5_
z&HEFKn*Yj#X;{l5bJOMfl84|yEW$AJqQ3?m9RD1-z+Lh)sb-dcD)NQ-5}s4L{nzBD
zQa-mimeA5?t&nTnI`lGVDZ!~4XDTfP)7-~DusulAjGyFC%P8FXj7`BnB*$)W#c;qC
z<<~>wr#P*J`J*I6$$iMn)Qw$dJdh8m_}7_>mi+d_ESFCKXQ}r%?Q6Hc@ycC!=q8vb
z86VpB05tHsvcr$N%H!u=g+-f4-j%6z&SE;gf6Zb^d*>o76SvDMgrEM*J$;7TWtsaM
ziZOr5`!OU)p!8LG?!_-;rg}`}eLf?;7GY~B$a(h#EYp{~q}H_uT(RgqAq@dy`<*Fz
zaxs4KDz9k$qL`CU{BzcZr9nYUFF(c7X#2fMs&NSjWX&jW;+Jw`yLi>$)##;7!p3m;
zGUh@?N-Hs5eZNfUOLWtf%f}PWiwtT5>y!CUtm54lfk1x~QNAZvhDty10z=nGkwE)e
zsC@65CpV5%vz`nREqK!6-)Tmzy;#)cPLYzkS~L8ys6ZvGFc<u$%;#0c0IN6$is>>N
z+J9{F%W^e7DJ7RLc6G6^-~UkYk32+8=0@Jmh2-&rZ$qZB?0lAX+x@gw%4B3*I6)EF
z@fqX&ik)gVm3Q~@VaUbecKVoo#gB_mdK#%j-<97YtH?eIMuV|&^oa~SFP(((MZiFL
zUDGboTBnB*&FB^P0e<PzKfg=ljG==4d7WQYMTW$HJjPj!e`#G2H-r}<Rx~w1JXi5b
z42~ONFvE9fi04J`j22EX&f$Z@PA^(hiEh&5Lbty?{fPB;%YDD{T7J8H&VNPO$zyBL
z+@tIC45Mj^@#UPGtGsUX&KVo|oN3(W{q(2q{=zN)`eWs{2XH!G^zN^ahs|+#N)%@H
zTE(9<j<Q|g1@-jYPpSjir!8fFB>D$u?1$#*2m8HG`Tylt68CwNZFOI{7=Ol{J8QU=
zrjjMNQaL2aICPVP1rwO&QAbCY3kqbt=_64g1r+gXntEVCp|_{w-&66gx#Gpi8%^k=
zmi*fNKm6LNN@#3&y!(5%|Ky{kR%WvNO6vpuWYXR5NApKuQo|?Kb6F05n0Wmu_XW#Z
zHJauT=jD8h6XnZKwO&#m7)&PTUiDz;Uc4Tqudj1tvCFBwiO=_b_`UxA^4xD?h4v4k
zCkFE7SFf+Ra^>w@@%{PXg}*(gRzgpP@g4Q<yKj6@#&P3&Z;r1#HTrf<wTiYULq0T^
zeELt>LhEXojFEO-!!Rl4KWvQ7p-7tD*NNVc^N@-Gj!jtKFd)KAGvBnbG?A()*D2Rq
zR@1d@-^YB@sin&~X3rW&pB+7VW%eLjUzM7kl`d1quP9Y31T}xFzgX$}i&3zABU>M2
zD`&!J)ksk?*MkhQtIDdjgNEPn^w%9TlUcqI_3MKjHgnuQb$=BONy`|9vBx#sL}t&z
z%%0kebMm0E$CF2`*ryj&F308{CO-RU?o9X@hOVW#u5DYE?YI4)v0^uyw(GmDf6Se;
z<gt<O_VnTbW%jPA18P%E-t?~6=j?L5>@-%KI&Dt-%WKijk<4j$AfxEAp$0#0QQ&9R
ze8+E;J9QN-t#7!|PW?uDc@W`DqT45aC7one_arhIMrs&ozOfD`W-N>GIJK$jTGXd-
zf?>)ZPD&2xmC3nhMsB~k-<&jH#>nDYPEEC0AJOBn#MrZngSv)KwRctqOEMwfYkB)T
ztJHYx(&DW!>@Tl}bM6N-{YP`DRgS`54Xx0)X37LOp5F25zB3Y>dhXKv^7;<TKm|>O
z@rIxOWnH{>)!1XmkPp|?o|BAo)Y`LakEdH{)4W$iVKqTIh$kf_NB~1JS~5mQcbnv2
zf=tb`{HpKE>;`s%*H?A6g^kg}(%P%0;k@^$`wPdshtCy~etRqM^k95(&~NkpFygYN
zRPXZ(*$Zag)vXfS4a<#!Gry<?Zs22&8AAWje>TGU;SHEqnOdVdYa26rMiE)dx>QrL
z2_aX+jJ=TiHanB3l0a(5tnjRPQ=JvDwc6E|!`x;~&rCwJQZ>xIsEt`R<{#ZW_?miI
zT~RGHxv2^R`#{U96*^ufTV7rdQaj7@FVgm$nJp$bnkA9Or1H$x{Z1X}D)`RQ7yMv(
zz3PV?-V%k;fxmo@3v}9(NGCMpw3a_y%QLM8g2$3r8`U+6ZHG%h6_Us!jp}Ai$CF77
zMqIm7V}`kQ(tRM~GL_+mL2>-d(T&lu)y>gj{-l~x^i99Ha?WP*JGGT<r#?S$`^&!R
zzPOECQTOpgECmZ{+VD)1EBmffUqR2Vb!tUU#ST)m)`!PWg@3XO)xZ{%5~T%0*7fA<
z;o7WIGcyRT%r09Cx%V^S6L7EcHyYZ6vBUwIp=7zVjMd51${oMaYGM^M!~w(@?wVTN
zFlfT=%+5NS`N9QNxP}~j!Y<Ujc2M^m?<c5J@BafgIFu1BOZ3^(ld~rm6h++_8r$#G
z3Z-2A3p<PJ!FYXs`>vXO`0ufUM5cF-A(Ft557!PF)ltV4OQuR#h3XoWf?^Sla28Pt
zOmo$AdI{FQjhwm;V(g7nky!Vb>(YU3Lvhx%`I<`XHw)K92KE<_f}ou78$Bvi`jz^8
zHghQR1X5~7>lWH|*1SfCR6bg(s!qda4WgYBd+U+!hJ8Q7Hkhj)Ecv(|cfmljGL|!X
zGVh!;XBe_&+a<AFA_Wf&jlmrbBz!%DPonX%;cOZfT^F5N%Xb={(`a{Ov@QjJnM}m2
zZm1)(N1wIEw$<2zI$)t+lQ-4ds!;fjvOngvoqD0PbS83<+anp51L|`a#j6~p&~-1E
zmW}Y5zTR}aY{olP*;)1jf8O`S*t&m+vE?`qH-X_Q)n=`k!-n_;V>Gt=L$Q4zhsyF~
zR+)`4Ys1)Q?KQLKn0GGiV>}y}P_No5`F<TyaOIZrbneS<<oD&R1J(sKeN*++HT#p^
zxk95AATn0p<IR;I7KD(df~i<^87>(D+j9Im%^qyGQ@3|&J?!mHZaf(mx4reVyHOGB
zmywofMrv*Q&>_ol6S47^)#<bN*~K+EHxIiYn(^7#pWSEVX;MOwb_qF<B}5vt85wga
z$@_As+rgt72hFkBS#GYSroEe<exP;E_OrFNZ`%R>)AzFyL;+nnql$(UrtX-YUoWr(
z<u~43y5;vXb-%yc$2Wx0?O*@3czQL1k){)Sm|w<y$S`b7G)h-feZ4PMdDVTC<T!&p
z&)=8UV)x5J-)A^2EV3?o(_m8cKum9jPjG`+ED}eK@?PWud$*al_N$k?bN17Ppk8o;
z+Gb}_1<P3ex<9uN9m77**iGa(mI)h?<hs?Bj_>bX`lEibzkI!qP{80Vu6_6S--mg?
zt1-pe9^<5WcwsbcCJdvbi!CG2q*nM<&>f}qIjjy34J*fVc;z~Jj<2kh(X@bu8=z~@
z!o}ICXGbv$`_0+OUozD>b&J2R_%;8S=VZVEwJ-Kh4R#i9L_3dW{3Dt0Gx%V-YRI8m
zD5#@z^>)du724HXeRJ`;8xBG_m?ylw|8I!oOPGY%G9U|kyoG~@4ILjSM)s2IW{DSr
zT|x}>U2v0S%4S(W%sR8x#5T2?lzAb(K2y7492x6v%#1y2n0r;BW!V_%ecnUfP5)eB
zB*@mEdvmD*TIes{*!ksg|AU$JW=NYVwu2bdiD7rpUa!Wc(}wEQ%Rzn1Y0M9{gZlb*
z09t+R&b_1s(YZZ%Viz|Ic!>Q5SoW^j?Vkzdc^%2c6Fg;3KZRpwuyR{AAa@A)i^U_k
zBS)s5ot@q`52$PS+}lb$QZO5K(=qG4FkO$_@I_gB3_{VkE)tN-Z=3t95*sR9tWBxD
zQhnYT+ug4$4+6iw9)(f=&Yyi7vxBX5F=QeE=-A<tVsG&h#^Km7Ai5R=JCxX&aQ$`c
zlhNIfk%~^(GSXyFuK5U9%Wk7xNP%eBk#4v_PgcQc1yxf8b<@8hqm?;otUIR${rYvE
z39b99A;l+WNpK8@{FIp$V^eKa%hk5kDeqls`K9?qe><o!pTBcIg?9oIfVHAzhfi92
zypuDIw;(EZ_xWy+gm<&CF$iakX&SKtkJAD0yRljkhFw%jyI(2CI|nqlAFuEbZ}^yp
zd<2<BvA=``@8=dP_$AR?iAZA)Z~Jbih7^f6U+M+*L9je<w?PO*m0$Vt`zUY5)9ztL
z4c7Y55YryoGwQOQBBy_+(HfgEv0K<?RV|cE(G(lcEA4QA3Zi&Lu>tso{Mp%A^FFI^
zla_@~(hUb&(F|%|?bJ>ncRS0`&ZovvEI{}f{0W;T>`5brG~izVjR#iR41@aGU<a!_
zPqFXf+JPv6odJr+!)DyxN#x<6Q#*Lr#9#9$nW?|qei^r{L{>)@YUorOe8Us-#Z>bY
zB@4sEkugl}v(`RqUp~8;pT_7O@UGdulk9knTTZ1OZKEMCy7sonL4PO>PLFk^6^&dM
zc;i-8pJB}B7T5g&3EJp(=Zlb7m;~{|BE6=A^q!pMt3(jGV1*xL!O}yMY*`2|qT%A=
z88AMWoC$Tw-QKgaM^~*E&FqEQym1TRP=!~@66@H_PVKoqQA{#8k`b_IMv-h1xQ0gu
z)6iQHEY=!We&1h4#0UK(#Y$^Y^z{Sp6~!nem|BLq#~2l91vnl&j9l=29PA)&STI?S
z^_SPe?HpSY1myxB(PQSJg=BUb<p34&bu6yWK~-p?6>f|o7?`**K?-WpYw^x<yV(T2
zmT*}S5O>Z!GA=VqsXKPd!TE|m(*u#SMtKk{eY0ODf@1`gfMoVs_}kOKXbE?)T7)fo
z=7y6@oW$c@(D;Ma>t$f}%W4S3Yyeh6;e2W3AaVe_@9I;l&ze)=DpqcWab8n}-?h1W
zHqSXDmmsU$olo)RxdhuUqVwXvX3Xic*e^@Wf!~p_E)~#;K9>u9iOSNIJJ*)j2RQU#
z2C<HZRah7$(m7PMw0A5*#KVlT*MYaNUoqm&IX&0o+FVY=tBpz%`}#>2bnA)*qXQr&
zEI}hARpo>g^_r@c9nWugE>h!<r{)%X=5zflM}x<J=B(M9F=3bSGF~$<F%KjCMr>><
zXxlnW*w-Gthqy#Mn31R&_%E#2oXPZRX#wGQT2L1iSg%uGwa$qwtbNnU$B{Wk7z@j@
zQ*Nx#AH9^+(nxBtON0|{Skp|D<?^P&@7ZrFd(QOgE5Y(Kfn!jg@7F7HZaa*!DdN#+
z6%fA9ngrY1Y0s;-9l|l&S$gb^oyGZn1_TjMbEtjy8b#zKtgJYO1d2WD%+1wi><m4}
z5%jwr;T<URLe6+*h`a<cni4eN!Rjr6GPbA{RiUvJuzJu4Nb42z942f`m+<jE<rnIn
zjRlK3OI|P!0$iN;gYn<Y5t8&%arAhaAOm-U`SsgQ#;>(Hi_fR$mv3wbnej}rpNjrj
zLlgUj6~O8e*;GZ*Eby0DTx;V8XoNU!fJI<crAWo1xK+1Y070_Uc1>XrHmswYsyNl_
zdHOU3hYIK5bLO+M+wccFOPh$^eEoVh`3Eo^ZjpNzZ%d4y6_sjNmD@3iA3t}gT(4~7
zZ!6V^WX*Sf?tNloOCSL84QcVSc?5LN9O1Y;YARN%kj>h-9h?vT*UUF9GcP6>L&>ZX
zju*(&iNJT+eRNTF7@JsB)wHJ0DW$vVS~<uzzOgg5G}w{(S@xry*m83@+R0d!$w#JZ
zEn3)gMuG}(aK0W5d|a16r|+60_*a5O0R&i2Ea^csYNjd!z5CQf?|^IY9CxVJ6Wp>I
zJ|+H1XpZUF6Q}hKKssowbQ;P@qWav4*fQK#?^(W^H79j2tZhyA%uf|!oZC6|xl0&K
zfu_rq0S*AL*&nJ_B3o1YP-fk)u7Ds4fX+)^ea+>@U`{pdYfs%1#I`DSyoo*fj8mK0
zGgkw`FlshC4PmS}aq(fod~r6=wmHrIA>H@E-C1C)?h57?UPfB~=J-4Lmsm3wv^9B7
z{kmP!9q6r{#S>yB$1CGp2?)g(>Twdemz05>!cr+WK%?+zwY448Y2dR{CYQVO^}mP<
zKQb}QGT^uf!4Do@$RGBIYI$J&WNhYeRwbZ$A-Ax0KDGiIM)qyf%z{l(fFRjH0dR)}
z?39KFimlnjSz!-04(4AlXUtj9dCgOSNi5S27B~B2i|evx<CXe)4B`cDLLwm!j|g`H
zMdxGt%(8##IcISmnj<s5JlLUrB|1=H^}fd;+0Y1k5{FM3hmls?r%W%Vl}0<UF#JkL
zQ1e-Xn&P|TW;j@|1wNwXww=1yk+`(xqik&=b8%kq(R3a~FlNU#te;a>-n&*P_%*xg
zbu#tm-w5haL=VZnKmRJ72t^`dWqZK15oO@9Gt%_sJ{|Ma6iT@~2&)4sZ5G!)_eWw7
zBtRGbYr(M72GQ=qC{XdPEZa7kCQQvD*L@;){^hj<)>n+~jG5;NUuWCZa;J<bZIo>X
zTRx0=#XCp@8OIF!^7)71!7QhTDSNF|Yj^4^fUGZGk{D-wduQ5xGy@w*gF+hg;?ab+
zlTfne`F1)BrdWJ@gNS!A(%e9hLjTU(A;C0)5@PeK4jlq13{gXZ%@{BspmB+Mg{~QU
ziZ%?fVu2km5^XXoSQ)>;SC&XCCHY?@_>1lfM~)`)XO&t|ljb>Mvck=FtrgU~PVK9g
zYHNOfeDS*fV&WK9clBjy>G0~B#em}wvZ|QPM%!W{It?3lJ|AS3;lnay%MRp7foO#2
zdlI-dAQ(Xz(rxUT;kUHm924NYg-CB0@wMM|Z2%itLzp(Gf;#bO(lI4ScY$F98W`1h
zJ@Udx>JIj|)IgvcZRgbItnHoUHQ0hbaD!jYK(<0!NL<FRIP~8X(+<C+cgzgtqE<n#
zW${2ZsoNhpti=c&h@Qv@ww$rCa$v_j2Ffrra`-nEBaEqqSfn{bi$j5ldlE$IC?nx-
zY+68ASUJlIlE5+lm<!n}GCdTIu}#ZqS->2-SPY&nG&>FG>Qi5I_GU8v;&qG(MMoA3
z7{}{5OQ<}#Xq7WjV<Q(Vf}aK@nGmgX=coQ8X7%IX2kDS_7F1sw<rd&nA#=rPgu*W@
zt}z+e)VlcMF@w&eV)F@9>jgoCu`uhf6)`LmB5!rmJTmsId9-(K)>AL23o3uhyI?<j
z&TfF=%C*ngJLBW?%kzK00hz?=#DP(4@)$6oiURV$Qrb>=ytauDXEM1Ad{g+fnfC%x
zFzv{3B4d|~#0(r8$=>wXm?+SZ9AlOT2A81U7GshIj+MQ7!C}38A7C!d7;oHF(D|07
z3Kvw>JLdUL>|DIgVg((;247!wKgf=P90d8$K7ercBU>0ur(9Pq0MF`}%Ww4;=iTj{
zaU>Ui_sj1CKSOyW(5*dpNd*bh6Ab9@whUNdu?&{wHf@Ly<bZYO5fh@sIHO0cgR}X+
zv^M$d>07GiKgeR@2FpRizO?M``18vZ*yM=zIk|piXomCdIa5c%+aS?)P%qfd;+C@<
z^)rNWIT9;ylz;J|7>!rOnk~SG!8WSHa|x$r0d~?NHmpCmEt`8QoXL%`wP|P-#$GVD
z;q+x9kfKf<jB8?Ceb;6AV|l%3OswWXk^0g66|)JkP@GcccM2*<LK+OVoZRwtfW!{M
zvW%T%SMWPNSr-dzS5+y)!ZkK`YL5r?8z4@YOsJ*Bwcq-;;_*mAVaXDL%dOamB?zK9
ze^%$N-t`(U!0V$3qU;;S0mSwIHaJGo1*p3=j3e9v1x>ykl7J9lJ$Q5@Pq2K&+y<N3
z2h=U^Z2}Iz-eRpc5r{AbDVcgCM9uXa-cRBQ93BcO#=+5Dr{3~|+E;g$zPTfLlN-VK
z?l2<q`T0ON5ezT{9wT==Q2I&h(4jp#zvc<m#G9f%wXXD&jsL8k9g5x9wwV+BW9q)!
zL~}@m=!CyX=GmW12sA$0lK_6^=*#M_XU*wfGOvMt_p8DO>|-A0dZoE_Y3cDD0U6Lo
z{PP22$BjyiZ8;;hMF`kv_m@tf#DhMYTU~~9`}OCAI7iV8L2wHe%?zQ)PT~|mk4Q)y
z3qwiA_*cHlq25qfOh(DW@?vw$WYZF~P6!6FP#l2Jdl~+2L7i5-3(B!jw*%;r<uCM?
zD@-u}lPSIngyM+Jx=Y{yR3O_r^jmkRnLa@dO|lYru1e+3^?xb?s0mMsXHK7-l~4#s
zlqW7GBD3v~;66m3O;TvgEn3a`C33mRr$Cr20uzkQ!JMYcQXWB*Ibqf(HfJu*Ts3WS
zZRQ150nSOG8J*fU-dwsKBECDhqWkFht86bPY8y&~M3^&iYNq7Xf!7ST7F}ApzEfG8
z7em2s#rJoh{u8dGDn*3T%y8A5aTZLRoERuEUA7iuF~WeDcqJIL@YYsICcrD#Z1(x0
z4LmNYVhOmXoO5LLQFo~CW^f98HXnmu5!t)*DST7Ba#(oO4>fBB_2)M5)$Y#X+D<Z}
zD=?d8|Ma~uP8!k*G&5pYiOA0EF<qfQL>T2$<w3ZInXyX5Wx$jM&w?+`MQ|jbw+m1f
zjb?u9ZIr3D(pkKGDYqD*)1gd6%uKMSD-N6l!;max!aDVW4>7}hr2=M+%tWYtDF5Sv
zq-C}Y92T+7jA0#KusBv+CQF|04hwbU{}QUZuog{=rB!Vg+BC-EM4{(YO?81ifZi;*
z&USF>@&3|0q{bRx@B1bT@<sd+fZnz`yqW(JM*?a>nNl?5UwxPR%%ml@Nhd58bFP*b
z!=!9h@0|zj0~wp(&qlcoX!X2g$rm0zegpBM#;JUSSh(~0wM$EHg#pa);{5mNfvg*l
zS|&1EFPE~=cw{?E{_co3l~U2|4}B9FKua4C!kR(ah?yB>{Ulfs&w_n?=fRROJdVn$
zd4ZY9HsXm9cO!40ltcz=wpu=dtFV5z-dudEpCf>deT-oKSeQhPxH6`iRF?0U4HfKN
z`~q(Zq$m>B>CtQN6JO188KAhTI%M0jW~!PWT8^cjg%9E*OR|fcK9cepZrH~ZG`xU*
z622@Ldww@5kRcS}POd1jbska+3xE}WZfEh2Fl#VT!SehucUx3kWa+Bp!f^Z0R7yOh
z->F{?OBDdpeB_FNf90bi$ajg!!c9Y@>(v>?Hg}hnv^Fm3GN>q`Nh+5!5l%;Jw4JW8
zLba8kRuBTpeK2#3P3BZS9hu+;Mdmzc->k2@!dC9BKh82@%qpu!W_c|u2B-h!9Glqp
zlC?&xY>P=J1aL;2#m%kA4@t^bTsDZT_3wP={jwSYfDMpNCJpbfr)C%|&ah!I$lu&6
z8zY<HUh2+qa$)$o^=*^>vRpWpd$GOnV0@5Pikj|2F3!rb$oV`wJGBa4CxXKM`b9Vh
zi*+u)>G?kP?3F>&eQ^9mNzM$zmk@I6HjoP0hubMr%3wS7!KK=@Fh~W20!g+c|I|Ga
z;)`O+dIQ-{j>h;0)RRt0eDzs_Xzs1>g<LaSg`3|nCK&GakcEiJXnYUT>e{FT<R=5&
zu%<Rfr>sr$fb}xT7P%`Omv*dmtOd0yCXP`+MezKZyD*qrSQ{fB`~V1WOfF207R!Vr
zRa=&S=>$8)2rOc&^uL`e4Slg-NRXuGN??ETptFl<11WFzIiZbZmtL+Snsk0dG#&ne
zb0A9v^LP!MjVsvsqS5X37%b=4!Ic$EqM(|308osWG@>^vwe?_rdF{sQZqwanN=*(T
zNx+_C>V{DYBedFtu~U+lLIfD*I5YO@|DmIgtUpg9V}Z;v)tN&!wvL}lDOW#b(#Meh
zpsaXs+sB-@NsX?Mi%Jrh_-!Fb@E_Ww4llA#rLkV;3IMg{7U}%$z=!m<UAT@gj5q*~
zB$);90xn9J;C0HUdK7?E7NZ^FvfOUe{`P-;ANq&^X4Y8c8OJ<H3_x6_7!{ALzPCi=
z8w;jz4ev-MxO^;pSsAQ{<fq}h30knp0khYg$<V_i1jPu0x-pu|WqXN|E}9E!7tV8e
z8ir)vkDkcPy&QdeJa<0aFa+nqR1uWLWE;0#$JRHzevSC5zkGwcC*2$M-#W1y;DK0T
z7Y#|3rAbtiNQc3<vEPU#vWOb-l_&fH(B*(6>VeMaGIXmr7VIH)`j%_+$%GcUvDFQ0
z?BHxJKQo)xp=PiM1O*7>Ry2Sc!w~ta6kdgN!DWY~Nd^WqK$(i;jli`cKLv+8`XCCH
zuMheZ%cpMto5zSANth8ZK#iM{K_9IRYZLgu?>Spct|dgN!?j?Q+Zc5+j!BCC)CBdN
zyc3%YO^bC@7#3vq)b;9hjSqo!A=MN+Ys9WZh+c<%z~|}PA?rYZMS1P@7h=Ugu*E7;
zb>J{*099Aup6G^{dofG#gL~%5&(K4kR8F?$5vZ}ISpE26T~*e!RByN+^O~A-Zy#Mn
z3!i3x-@>{yi<06`M2@RK71>mRc#fZ~w@UQfz!^oQJ7$q<k>~_53lFeh9zL0eCqiY#
zz491-5MLP!K!bUyc`Qe(Y7^OTQ*vAKu=gqFrqcJ3llMr5*H<hD4#;WXJm<Gbv%&d6
zkVd>QD-gtEeljF<n{CcX6wlblGK%NxSMEIaXGFO}5(pH6Ze~h&4<;!7Ail)fDYg=H
z!FW`<Oo~#9)EH3`ah&LZQe^D;YqqO2*K!u0?|V69e4A=e3{NOIAo9iBjyM!7t}yB~
zPVRoZPmd6mOG9TL`ty5A+#T}5W5Hmpa1XK5pZPvtk9TDp8gaVb#(g2l{&1WVo5(dU
zq4fgNNrTuf2?c+92e7z(d|}{%t=IS*4S^HajIVNPq)W1OyW@crnUDH)jEJWFu_vn(
zN4yD*WG}YLIXUV8KNty*w1j2DPbC)Tzm6V=UlQ;NAQLmdt3|5b#m4UE4;fbGOK&o?
zWQpTZaxP`WVv-5!kryG3YO3inClb<9=Mx3<xGvth_KUyD@-Q4gqIjYV6DT~4B5t{h
zg;)}v!}0KyH;CR?u0>-BrkN~poLpc`Q#w_-uPM*Fpx~ABHT7Y2{G6T5FjXWK{60&D
zWbBS8;l&zH7-G?Fu0&oKTB~zn>Du;Ag?2*~ni;0TPk;Q!_&7nXiK^wy38AGN6Rgke
zl!m|+b1n)Y3zf92j#%ML9k@dRN#Houq>4iB3u+SazhC9A*yjp5G*{ah_p=${xo`CA
z{&pB*&$+Rhl42O@9*`h2Q+uv@xq6+{Y=%9h;MVXT2LLRfs|c}u$UY=#4$>Ql>JQkQ
zl2i=HlzG*H(`flV3m~+CFFA8XU{6xx0T~f*V&&#qt&e#fyiDiRTAx(#;`Ly;GVeZ<
z35Rf5CLGU95Q7r7+vMIrY&j@a0;5RY!}II+-Ge0==CnXR4DN8vqDqHp1DbM6&Ruar
zx<xomA)bH_4WFzl@q>#$fSZ%7D^jJ3j7v@Hg!H#n0p=v8O@i8U*okf2;GYi`DmM%g
zL)w%4<%03Er4h=*_MQ5I?{7!jZYYfV;@ZQzCH9samLM}j%HOJ^Gcy=%WJrc4H5g33
z{AC&WsoP;{>dJ3}ZNUrtoLN)Fi3=)w4VuBSPb;@wA_lp2sdlTMioGqCf-EGZ37UyP
zB1we~y1;QDuOBQuMoN<?GU6E8C<+gJV%M;6Fb*NHl$mrbpD~7OhHd5ZxQ>iRqANyN
z!mZ(3Nqd@5{wO_vljz@+KGkC__gVQ(M3UKZHjz((U1l8$VI3?>sIh~d;n{F+(lW=+
z8?k8!ptA`}+V1ObR0m-+fbCC)+P8j#>y{FPwtEs}Pq-4xh`sdmwD;}`GEZW*W8mSr
z0GCEV{5k8F)VhhHiU(CBv5WOS0Kx2i)!x@~5NUYNHy1z7kgEPp<R-;-#wE9yZy{9N
zfcr#$%HD}(^fdNN>D29?|NPLU2z%rr?Z_41)QrP22B)^k*NC~2?n0Wxq+*hgIyb1b
zn|x`BI{9qpU%-)N2wSG|`V=X$NmHLT;Wv+|0<+ufWE&q3#^>kb_hrV>Ht`Dh%NRqC
zG{urKerM?|ny(T7k;=QnmTzuZ>VL&_DTl&JV@_ONTr*?pX|WMQ>B7|^T(J{}IB_!M
z#K|%<XL1FzI6I*z`33UX1t~!}?H#A;6OyGvIZ<YDGsw*^UQeIdcBREX9}g*G?_<dw
zkyU0YTLT(2uJ53|8BE*`Es*+;n!C|RDf<<KGOYOorkteg6M_YUA)rbjW)nuyiu)N(
zkfX5@;@Y{@mQ*5oNhwF<Di<k5wGcJPcPcm3^cAIdLCq2z$5i(64R>cb8i4HSNW`+T
z9S=q+pNIv;@07vdVqoa|=Y|6;FuT>l+vWdL;$Ko>3CtMr2YDIEG8zzsU<H<yX6{U&
zY?okTi)qQlOkm~;K*>e}a5a2=Fyo3U^c3}m7nD7X>9_YQXNB4=v$0ZY41!v5XZboY
zT1EQr$<7z4T$9y6L)~WEsa+#E=BDfO7)cCqbo=<fybBn_Lqb&>Ggz}duB410Qz}DO
z6pyMK=L$rj9G|onS9F7hjhFAbNrrV1Hl;hOtos$qDyq=-u(q8#@y(kxNbBp=Y41pw
zL(h@8HJ8K~l8jFKwSsu>LW#URRg+jVd3^mpeNRjo;3|i@u*aM8PL3XqDI4N1u^S?A
zIRZdBK~RWEA6=?@fx7|9-0@&)1RNcr-dNMRo0b}D3DtW*^;lRnHA{ViA`G(L5IVFj
zcmW7_jMCURmw<vnyyYbiYuRn^sEBZ(Gd7+}Zu4OA@dvp(c5%q-;isgcEN^A@#4$%~
zG*C~SXicn})H+Z{9wzp3l#`1zdfc&)Tj&Rr0anfp+CrIPf6XbiE6>t8*VIc2hp|ru
zEN|Pdo(RUrm*;~|jVA+4oOmNlaL%;$i7lr#QDL5x6)ZhxfsLxyLqSPl^xxbW4pHWj
zVjMn}mCjHQzYCa$KX+uW<%FA(r<IsM9z|k6b;`+7YsY_p-1rsSU_*JVyHmIFyCyw#
zQ>iPe_qJUKMzCgtZEL)7r;^#d4FjFf-~cpeKL8BUopeaj*H=3A=+dc*q`P-ANjEB0
z?)<~QEg?M_VV+@!JP@?7=H4!waT2sabzq)YKMv8NE_I(J<t8i%9+f9~e@P58yjOf9
zle}oKffQ|=s!6FJs5;+L$GkbLnSA&gRIcri4_*s0Dfhg~W&6~4#>9bmd?zaipTT<l
zrOW;0H6O-<A_gS!SE73)0uj)L#GN$Z(5%CAH3&7^);1VhC>I-Jzdu}z3{DKQEUHaJ
z?!jQ$SQh_NTtY1Jv$GtCN|m!t)iCq-HkB5({}B38Uugyn^`@EIy|c(+){6seFQcRB
znKU2(MPQI62V^#GZC_fxF(5V=>;NsLh#~r&pWY=!mw5ab=t35W?W33t&mpN2@v)q(
z5+>Nms7c=5qGG$8Bsc_>bg1G&0-3`E$Ho(_kq+rGFb;>OZX8{)@3$ZFW--v^Ad_8w
z9P#&eVA9whu(p~AxoMFXflY4H@jYg7ELZc%UoV5e$4QK&zWc96pkkz~8B#-=A+I3X
zQj<b=@!=wYVRX?*p9#kdwsI81#A&X04t!EdcHq<`e07QUW5>H?<cL5x)REwo(`K!g
zWe%<BO{E^RKVdgrU{T|Fr?$qs2ghF+w-(moVoS7z*k8-#>5U*d?FTiF0)WO>1JfHv
z7E$SSEaD@7FyaCWK%Ii37~ZI9?#fgxR7FNxlYJSf)AB{CP7~d4n<mB;AmbA{w@Zz(
zYYl@t?9PN0>NzmN=B#B;D>mjlqAp;}sRw98F{kYl+_8kReMl_7m3L$55q_cVfLO5o
zm;B}V{_^!u@B@zI>;D(q>*5-GLOXP~Hd`94nYa|@Djwe^+XpEx4JGFh!pkRe`Op<^
zL-|A`<v<q$DI>%m(+DV&fibWk{l=`sRdT$7C-6LsP#jOEK7EOeE%T}Q?aV_iv<7S<
zTEpA#qw7&@z|q7qOJCcfF>z&nF+$W++H3#e9!WG-Q4!p6o~;710ppN(7*r-A<f49m
zH9>Je!hBK~$^%vt<cAWn6U&DvN`fb4vHjdJm)cvFjVxIgPHxDwK_aloUZCUA7Ege%
z{6DX}kU5+A<;>z*jt;shxg~OCO&mNn7=6?_wasAhnlMIqp$frl6n*8Nrx+zPs}Kqa
z)I|J@4AdYj^-e5Z)}pJhL+c67CK4@ASVYXS^C*KrnnLn<!T~>+d63C@ihN9$x6x97
zbrAbWR^KL;2iV>VS>CTl$IoV-9;Xs#-9Teuh{)^Y#4~FEGT=|`t3k!9pxFcLqXZf}
zzjff=n7NF3HlPA^UPP{>VXAq4(IM}*bQv2(Z3|_7Pvq9ObL$}|m@#T<s&gb`EW$nT
zoNC%m5`XxLzn%H8aU7$DV8}kR`wWVL02_82))4<Dl^;uQY1{qGAhS33hlzE{oT9Ls
zsH$8X-k4@m5^;9qEPCKMpIq&F6h*fmew~bgm`L()5@jDcRMPp55Q8i|{*SJs((aU&
z9Wf;5=XIiJ_9QVjvL0+aVE0m2pU_oKeV})aETJlRAFv-5FT~vJT_&L2-JciQkTgGJ
zHF-R?F%WzRGOPkeP`_4?t-nRGn*zCUs=dXN|I}~YTN2nRz>vYE-P%D0xd(00!an=D
z!_!O!3Aab7Ag5x*+-KoUg;6IOQZ9s#z*s*>@@0-0<1v+2)XKH;7p<e-EM+AZ?1x$=
zu}T5j(m54lj`22*SIe?#8K$303Vf9bW`4a|xg%mRA0(wz%8#_@_D|lQ78gjREJI|d
z)Seksl!$f2`8t&osS*k3cLh-sTAJ4&RZHYq>K^(c7TizHhqNz244)+uH;bn&7%n!d
z5u;qOYwDPiLWRcErTOs;VC-p5JjvwF(^`aH#X0y@N=SshK(AJ+7{=_f0uBw_VA=QG
zNW1-&e<9(aSRTo_NirTh5tDCmB_EPlIe~#%4_~K>H<rX4Tc{azZjx>^+&{>#vEn4f
zKntFTp2{GGk{EzPr##M_`X6SorRapB0ie2S&r$JMUm=6Lg)}Y?ut37ABHkS0qS?bd
z0-<#aV@3QLqBQf!Vo8F|@E_$FEK>@9kY=t%7e=M*_+&mK>LzRx5~;CA7}tbI@|kD~
zGYO(-!SjK8lD=?_l%N9~RgS92Q8jmqpx`PM+%<o{{csI`5M<{Y*Q4tEPR3qXCl;VF
z8o>(U!}<_5!dr1c&l&_v9|wx<P#2d@qAI`eU&I^`sbGWYM60Mf_ayZmI~d)*B#{c+
zuKQrTRjF#A6^L9iZ%H{lqUf2K29iX&K!UwYB)sn|8zn6B=*G+gRLQI2RXg~UvdwI^
z(Q9t>iB{Z5j0*8jE;W(Bvnt5|>ka{igCWD)G#(pZZ%8n1$EUk!pL{Ci6Jo+qNx2Aw
zFY`AlNxSr@u5E2?MHobkh;V(O_K2yPNI6bWs16UcA-Y8%pJd+{ey!V6`cx}VWgIp9
z%BHl?rgUMS*CCAX8%293M-Bh0?7{o6G4?u1nAfGI&U~k!ZVa&?C6%Di5R(hg80jFJ
z5>E^QoFfjjpDNw?{72(iO^bk{;No-$1d-7U#GNS1_p+}gor_?}DH$WR(P;59;66!Y
z0+M8~x|G4H*<n8K8k#k*feh`=Dd@cQpn}q}mh9%0f+^xFvEWoF1h_74Xwa{n*;)3t
zWt$W}rhn)4e<4JcFdt~Qc)%(#-{|38aBU^A-$fvLNa-`@Bji@MbF|A0**3>UPtrsV
z``f4+@j(`jq{}dNn&$4!%*9nBK!57B55o8xH`TY5a=<~wd4X(<qg{P0+zP;8Ydhof
zx!+`;n3zM>3I_#;2Luv*3`Q*H)N>)wCuYMc!FVd2yYr_vVuJ(|2n>RuojE**%DTW^
zx!FrP1BMl#!xa%2mP0Uur-OZPdQwrqOuNA#6JtsE5z|z}gLC?QAj!fl<z2C5FApfK
z?(cYu5I5I(%Gov)z&8OdCJPn=a*P_71*;CeIJFMXIKRvSq2IUv=U=CCIZi){-ry6B
z+UyL1>f*&sSdyil#+))q+qB~*LzZC4V<^D(r`n2ZJ0oq)b>~4p$LVAaNGguOle8q5
zzMp%!rfiI*hh6D33YVxP4dyeynalopM5j>xfcAls-2^GhX#-gjsE-Nu(4@}d7yCI{
z_ah`kLb&<pql@?AI|TctnM}h#)AvC6QnYYV47{yv^-uh;;RIo!RZp4H$1AP3s|>^M
z__ea^<ML%+45Jo6lw;rI)W+<Q1Nks~7@JR7`Ef$-q-{~pQDlowpNbVaL;W!|Ofv99
zNDQj6;Y@-u4~*rIfmAZ_Ar2oUq}(BQXY4$hG-MGa18D&`AnqytkbRReDGyIi@($-2
zg|su0kVj~Ehg=W&Gu@T~3oVOF>*_g${hWRnbZ!-uHF-;Z9hW9cw24WaPd-Ay7a0Zi
zRFGFaYql)B5VMk|^0G;E{Eas~G80(zz8~{c;YYua!ix#C6f#B9&SZcVD5M!Bxf=^7
zsmBmY9AY|GDX<DBfR@;%q0hwBVV#KNRTJap`{~GnN}#KRIeYZ4XHDmdIXn9jv6x;&
z@Cxh`SdO;(m3j7$u}6UQl)WFM5QiqTIdquhg&Aqf?&oR)aufmR(r3h_FN0zM!6eRv
z%wvAYIv<u?uFLF$$E^)^&xcR4Ba%(tvV9GMY8jqR)=*;Hmfy+xW?44g_*t+O8T4Jn
z+1%8o#jf6>bBpj>Kh73B$VSU)eBly9?bm(Eg|UavpzgyzlFDYE(msZ2mB9XWv3QSd
z3s_%-!x{vX8$@4Q_%RtNRf|~9jNy2O%&2)7u1bq3<Nx<CO<iIY6bXcj0=NMp;Rdpm
zMPs0=JryQ6f7Z6{L-jFB(=G3Ss^P1%^{pW1;bjJp#DhMOPgWWn^e;0^Xp9(xw5rs3
zLuNY5cH4L9t>se{kqW=QJc1s9lE~t_#vBo@1De}oE)bhxfGPFDou5yv8<!1gOa%jD
znvf`}*nKdo?@MJwOEicl(U}yk9#In;=0&S;&2(<6TS^R*KYy-}&5i_(H=rukFip5c
z>XaqF_8Dm!z~lmJWeIhGbW-GKb(X)_&wx1x_z=PiLGICCT$9D89fct-$z3ohkl0gG
zq<o0TWs}wqj<(D06vv~%K<t|sC!UUMx$XLHkVKgzx|m2zY%BQb!mKLjr#%oxn_VpZ
zrJ?7>!%Jl-b-}9!V-&S4VL2%U=tww;8}VHvle>qJ`pT)@aefZQ6XJ#a=8}gZEjEY6
zK~&}W?g*ut&?KSF*x>txO7+uaq8ql9#zC4uC7R0Xq%y|5S=Hq&EzfPM091Ty+xdu;
z8ZssGXb`<39wAS`3^ISQ7BD8Vb|W2j6%zaSVZT0bDOJ7mkxxqo2l$5Floe((JY4QB
zX3y3*`$mu(1+Ag<!bf3-<-P)sDD<fjW3$^MDKL{IP-26|WJ}v*?<TrkQ}Z>yeXK<&
zXLst)_ZzG*iw3gnOWj>+xWq)G%z{Qh%B?t5WLCck+Mp<OfR;(E-tDb@;@F2M4(vv0
zoK(k|qsB>rn5Mq*y+MLDtsyI<ESD-tF+#vM;U^g-cCx6t3X|}N>ap#E*dr@DjR#hL
z34$A@W!@*5A`J_`>O$yZxG@kwK|(Qs1rBB>wH*aM^Nifz`J2a>yb>h^;<ZaI1Cog0
zU<UG3C{qc<_`;~TMa(gQx7&2x4nj}*l0k`gm5016?w#aN0mqW{8s+}dnL!l#gKcnE
z6iVqeVNMB1fq{`x*>0O1594FYC{2AnB;Tjq{@pV}IF8yvKpK3aXoEQ;o9yHxp!vnZ
zu%&<O9XsfnXs%{67RzdOsL1wWSqtohsI8pFJ>g!E?NMM3xPW@Ogt@M5UNY-9-01uQ
z+mD{eohAu%9*D}=Jgi?9cTRCoyHhW0vE2AZR7>`PR_+XbcIfgFQjGzA6hcL6V5PE#
zS{4C3@$m4Y?;4hKtQWLTwFTQR8#g?cI5wTch$m=+w?Mp%CZh@&OoZo~*>Y{Ly@Q5s
zWA&uGlMUc3CN??d96=Br81?Gbn`2B}UsPs3O(7-#@*AH7t6-b~4zh=is(m`f9GsyB
z8fuC#_8mhaYAVMlN%kHO&(2pDHHd=>6Dq|mCF567JzeC}E3-4*5d>`3r>ORb`ildf
zL!GF0M+t<w6&nZdNJT4nzVUotCkz8lVccj4a`?vuBnazGWhkkA2XcNE3zBA=Cj-DF
zN74mLQtMbDQV9rI8dJ&QvtTY}jhmv`6Me31p0<;8h)(^EH(v39&xrCo)yV)&8ZK&Z
zLo(S;26nOCv}|e(cA)Fo4~0%r_JFzl)|4J+W#b@Pa5iD-D1?dSNVgh!#A(@X;&jMq
zest=KgHjBO>u^nr$PXbW-!FZ;$mdPzG^Tl2v5|rNkCZGIt4L0^el3Ka+3gRIh-jTC
zh2e#eBbEldY!myG+ihfF%UO!HcW^V@1hsXr@n8A(N$yxGG2s=dPO>b?YSd<!7ZgBB
zBsGeQQc}*Jx=Pe(m<s=DS*)Az1tyE>K#{n|*{Yk6c#13)<%U$|1N<jy-u=YOSTlSE
z+pv}}8c{IFnFClM?iE!ha6r>YuC^>I@LAXs1O@<G#yFk~*=g|?casDRki_vJKwou~
zMguZ$I0LgbCCMaOQg#y|^^T}I%Mm*l3(B{SF$MIAHvj`57CBPLoQ-o+C7j+l=<dl2
z_H=E<(S4_`h%_LMmi<zSL&(!>Fm)I-1OsO;bsp52+MQa@l~r}OsW<_keD?FholR1J
zgf}H7b&Xx@tavAn96EX!M$syVyb3G@<nAR7$089hi4tf4Xk3WMTo9q3nwr&A{va&8
z$>P%3$!!+Ovd!?s;u+v2#R{e6NQ2`AlQpd;+2qLRfR0QsX0rALe<vBRnLnKb=Y8pU
zVVEdB7d4Q$6aOe!kI0GNqHvV9P+}4!vBy+WU_b$oXFFMH8gZa_W5EfO0(5oF>769+
zD0`VHzilz{=bWWVP_MXQ@bq|^g0L{ccc<ypBD?NNNoX1(J*Rf9KTpctr!JRRxVrX>
ze^ml~$5TZuoX`xw&e57laD?|>Qjp`Zc}F>Or3+G8hvn9r7IlN=X7g?e*{J)+6B+=i
zmyl!%OMX+)Xy{>v->Gf&7r)u3v~}^uALoQP2X@A&N2*|~X*aGeVrK%t0~50uVQ7~t
zVL$0h3G5^P)sI6Bz!RdRj1DqM_60g8Eqjk?jEd0_vnCHRQo^9Ys30KBKcH}hh^&(x
z!M(9gcA~2*jo59URCpAxD%(X3NYwhB<<Ip`-C%@$N?gegOVMilq%6Q@HRYB)AC|jS
zT7GWJ?JrY_o?(Nt2;JxZ^Y?IhsVx^Xg8e)=Lst_PS8Q0?L=7gOJ+k;vSS?Ww!d(X+
zROVi>tVuYK*fg4unHQ}OAPonsmdf`)?7r+lqY%<{mY$EN59q;0zeh>I-<`iB9DrxS
zj0!lCx$|6TS*j2E{`lg$TP5RyM>z5K#X*Y_AkYSO0)Ki~D&oYqN)WEo&61U%lP)|G
zc<!_;Fa?7xhXOKm4avnj`*VrzhDAOZ<|yA%rE`MRiv?RInH4K9GKUz6>$1w32j5v?
zhRUTivX~4q>*GZVk{zvmGu-jV$14~U9P0i_q#BhVNddex$xx7+ci*wZRzxdaF|-8z
z6PBwpD6w=7sXRe8I=D*wgOoURH;vbrGo21byz(jg4YrK<kRi|QEWO3J`peg!$ZbD3
zz7tQN9MZwy*!zRSXJyE96o{KwI`u(x$;&~)bGj%Ji0%H+&m?25rMen)?tw6e!H*@(
zh?qRg9VWRdJ{rt~CW|hU+Oa$Ab=O?DZxY`dGgvt*oK@2amG>Ct0}6)MuJ$fbH?+*e
zu>o~?@W<bqI(U<o1yLsBL!6<?K;{$ypK*Z&B<<;1&Gvr#?=dz~P(#*Q9b!jIT((A1
zUQ7tqxF=R6kzNZELe4wa%wZP>>Wkp-1;zp4@cFDUZ!^KaIJCTeK<RmpHJ+O-G=s9&
zxOQogNkj&jN78vBgDA2nOPC`Vr$S4BgqQR?w6|&!j=d28lY_-IpeFCBu6^kFdr(7J
zXi1m>1TZc6Ly#L8{D!4PETz~hNiEZ~Q+Nj^mwg5>)@8AhH387#E^<=YKTT(|mWn6x
z-`NnD1v0XQH{M*l%(zI%_J1=6ixKaLjaQqwG<DMR>6(YIQjI26wu_aJU6NGP(2Xqh
zXE#yBVX>Vwq9Jvnh#(e5O9|0idn-0Foc_h&Eanir3EW>1_sB3cFl!9xHt3NELeZ!l
zu<S{C`n2$PjTRIO6NZhs@x*w4F#gAo-i(vrfteA=DUg^@j}0dh^<H+$i*z3$YKnj~
zU;67G7qG%kJkemmDkv}k?cv(NYF+{b8`Q+8s4WTk?xs2mAx8DH7D&~6eWl|81>)$z
zlyt3D#7a7|QU(aQYLlL_JDCOzoBn8rh=m0vnY{A@HjvJTF~0BtRxM|wIwiu#00Aw-
zP0(Na{rAR3T1=o&z*M(NAZA*utjwLw@}eMYk-(yA+LzdZEoGQ21WX9x?a@ol*IbV3
zWPn|junPL5@`$fJc3pcTxGdTB1<Vzxn}2XzmU#HY0zNWCdvH{B-$JCzP%N%5lRYm{
z4v0PV>HqS5Qtd6_E42g6^hx-?lTzvi{$zlq934jGfWq|zYK+UouMo$yKvOH?$no(W
zJ|vmuT)1u?lCo>{&ML2WK@oqUno`A2XkT_lz$%%{)0rnTM8E=|@oq9a0IN@~1g}(p
zqe@jt@KpxVJSX+}(R(mmV(;*8{6mSSaTv)vX_5SdK<zm-TChc=JxRSLXhFzD@kby?
zM_6<6IcdB)CWeIkHU&Sq;zg*GDK@MgP%kUCMNr;g-L?ybdbv|h+Q2yiQf9lGK-V=k
zgH6WbEz0jS#JU8H=j@ojN(IbG<;$1ei_qO=PeBKm6yeVf8y@@~w}!@|vT_7tNZ(Nj
zP;^{KkSR+Mg#b9Fhev?>)y#`|brCODq#!s?M={XUgLaeJuQqjBEx1bUw2Qk0Hxd!;
zv-o0BqGp!419#_yu)i66H1Plhw1i<lCt)k<Fa*gskC_=qc=Nb`iJ%3aEAgvITt`iQ
zcgCdXM?5(nC0gU?Oj;7|@lzS(GciVM@6CKw%}Naqg`n0kkN#{`j{ry}he<Fetb}-T
zp|ydER7f?6raSd-^x4^&0vY3W=_ttNf{#4T&{$OIFAD1zS9+_%anU}a^+UoY;=us;
z1V{G5Wj!Jb7`&<vuwUI&N2YqKH`VA(CC!Y;gS6)Kk0HTC{3Hosko+ezKrg}h(rwF%
zQ6pjoIxhQ5k6kk3<ROdhQuKM}-`tP-0R?2r*lvvc>*R?AhXSK&JxeN+VJs0{L7?3P
zb{Qn#)jT3s%kGq!I&i!Hh8q%&^DZ`uY)VgyFoDHu1#K_S+Jg&m0WxVA1=ofDl%~Mq
zDFtqfG-E0y`KC^3vSiJ)^qu`b%dilBtOv|D03btPILc-{_$yEUK?y_VVm!u53KFo>
zF)JdQLj)p-waFvVyi#qo`J{sFG7!z3L;NNZyvfSyd8(GG9zitA#~PwXt}h0X_i49(
z>0dJz*bvdjJqe&Wb~bONCF74T6*5~6fhHd36eTP1fH`C~`B=X#F4QAY!lmQrX0D0$
z^QqcIn2?$U9wj(*a22WSK<pLB1;fO^*)bx3Q9M0~1gpv&z~|yESz=88?SJ$U85Oah
z>`9`I1Jhv6NzJaQN6rr$FL5TdmWzqSf@Mca5=>IziNYfzFA-(QQdk<VVX}NyS5kxB
z1)l|vjaE+lI8P#epDJk^Ep9UmEE^-%wBLU;UM)$UQJ-th2tjk0<ywe?zna?W*EU0r
zQ3w+f%5cpmWy`79dEITZ8QKRP$)fN)PEy4+*_ld#L3crk(`TA3TL@jhieJi7m&b?7
zyEBmmI7t8|xj&@I#cRRQu1F}&+$3pp@_TqenI!mr4RQ_HmW?OKrnd3@RtnE8sJGgJ
z+=mi}k%8)je?Nwyi<isrbQ8&Eg+SD1(uR`3in&4ZnES4M%Dd+zKw=yL{cxeOtfmeB
zEY?obUi)_pM+3|XojYTJaSoGqWhkNryu#rO^m(K)WyrRsINgA1=ng@iLu??GQ_MR#
ztRy?S6Ko;t^>&Tz%4OfCa|sdOHSGQh@vp=N!{Qv~$8`}ja_CYTE%BZum6C*?5UVu+
z7&KjdfOx-U!deWiCd+3W_Du0Rbi8FsxEaggKndX&C}xRUi;F^87(B31iQBF7AH>OL
z9ge7Cjz5!$csqezxY?p~&c~S|+n&ydg5+_7vh}-`NvhJYBt8Z+c9ji|iVP}}&htrr
zi9t6gE+x7}z=zK&;14GV4L<CyLoix&#wZ(rtEaCI`p&f{jUK#1mHY=ADcufL!LeGo
zS2OcQlA7x&ngAVfdWmVTrA`wmd%~xt(Ri6M{`%c_q)KiS8O3R3%iyNQX0v~4;F34?
zOB5=lZoB`4YNaHWAs(NBtFFx$)(nfB(3qefkg%!}6;w7`a=|!dNL-P#WGTaniHzmp
zWR6}?1${61*9X*oo3^m3Af;X&csDldE(Ffd7mA?8N{izz5P5e92YvRd(3Xhh7i9hQ
z7vIBd$IBX5^ugcGos=MIZWo%sP_SAPMp4?`WhrYLOHliWuCd-W=BCg@WLyV(jFL-I
zW)6|FV42P0WQ$7KUQf3VP|-)Pi&~-Cf%q`RR>qde)FdH_72<BOH^?N2n7`S@$4P@O
z`&D?k3?afx|M4f#(0EsdtZvC0om-fZWhPAsTE1(;uEOeG#RSQaMHsa<?PVGs5k=c>
zqg<keG0jlSU7UT=Ec8^36zpWJ^+<u{)n<+IDP0!zY9?Uq#q@M#2Wc$6ZM=`~)b4i}
zdFbxQwr$2m&#}TT6ju61pbjvT?488W^XUe&g8T9A)eyKW#|fSePlsY69jIg!44dg-
z?vZok8Yk3EV4~m{q{v^RT3FjpHtPblDG#-16jBhnZ3Il7iDojnxzGwNOqqD=xU3o2
zPmNQ@U!vlsUXdoR^?8jNzW$xd{~px?=nNN@z)8vr0k1aB8-+w^i{EeCAU}ZXdW;Tj
z=8h^*QCXl4Nh}bUHKCIfJgpr3dC|&WuzvwnZR4}KXT&=#Fl{0+ktk6tCF%gs02mgk
z9wa5urh21aUk?ZLDafV1_J6+z=T(xtKLv54Y?hLCT?d7Dw#0hgE2#r6wn`2CWur@p
zU6z@{3)s-_J|9;vSU`ZgNsWtn0?%1#29v*lQaE2lC-~q_W5sP^vSP{|OhOq0y-RXr
zmcX7QAv%N(tk%c-x#hKRXLmsRP8fyX`YS0glRf`2aa59s7+z-2E+h|V-@Am%M9_fy
zV&*7IfHDH4n|f20G&|BHZG@;bVNfwLo9d!@QF4Bx`XmAIzSjMs3WTM#LdP_@fpi<-
z{f>9dv8GzvZ{j<F+~do)NK)<4imf_`n@}A3)H~S&yeEoEj-L-dykJ<w9Sn_o6d^-=
zH8GhOKjpg^O*;_B2u$?5O-jFUm_=GFk>XvY57$$(7nw7NE%Q);NppbTHjYSkb;~oR
z6Y;O0R&kzzKf>UEK3l==9TANr+vB27pVTFYV>Q$89AK}*CTCf}Y0<`o2T)pr3NfP+
zF_)R1HOZ$4E5>{gX1W0;L;xK|D^#KZM<qM?bI6&Rx@P+yQx6N8k?8_Ru;j=-)@|Co
zsW9KnSQW?6C|I4n^EC*A{y2k2J)y70|ED;iLFguSgPL!`4^(tkn0l~j3<nvSls=~c
zWRO?lX1Gt;Ba8=!iV#=io_1Z)x`fJ^NB9dMVa6<A+cCv{7zZxCgY8KAr{lVMi9r(k
zEHZ_t67ZMfS=*iE=}V14FitZnpEE|H+yCJRHUI^{0~nbZv2GF;nLLmH<|>T3+Z5u3
z@zL@n87US8sb@LO2G-3lMMm2t1xGrR<4ULyaW1IR1qy_adZ9Z4x`EXNoIOe5Ev_A@
z*l%`S5d>$XZ3RiE_8k4OT)(t?ryj-P_2EB@$3zH@rNFxCY%!qM6o8*eVZlzEIKgB^
z-Nbq#mNGIMU}$VW*>ce%e8GrVPzvZM8zCHrE+B#=*C<`9*%SU9CG{oH?jG`pFka1=
z;^j4rt#CF-7d9gaYVsOe%|3J>8ydsvU?&yPFRQXU-lRcNUiK^DudG8e$i0ZyB|StW
zga9(3<7vOhT~-xC((Ps-Xw5Bwgd{&Zrh4YAl2)FxN;%)Lu@eDs$PKb(h)5(5%@;F)
zW3t?qRC55j()ATwyVt2b)*nO6m;HW{tpa3@zy1uyMKA|)8OM&)h?thKXA~obSaNEC
zC1ZjaMZBn9QAh>;M7TX(FJlAvbcFR0%nc=}#aYGSa1K@?-2;#OqN=X6JM|T0F;3tj
zF5Cn8NQ{Y<5HADpY!uRr+&MvNnIeY_q~mU)useVMf0R`D-PXerI}(jZS@fJ62O%8t
zm$*upMi*xR&s<DLDtw<^VtR)yk^&zI^;w#nK((oxik>f0;E7kdiKpHldk5hZl>@R*
zN;hv7QG|j@C2pQA1f8-^j-|cvM#OH*#kCy@cu~sRzx@K7YaHJqV2GA^Qoztb{E`$X
zVOqIPE{ZuRri$6Oon*DeOj!h6jwc^;oXCI^0D+JN9U_X|4V&z22wqt^ry72B#W5Q#
zbXH3r$`Bgx{`5^n>@MaD>1+wc>(tl|j@7>&`T@$=zw_mvmY^Fmf#|c6dDs+(_JJfb
z*y@A%lH?~mvT3eL&9f#!Afsyo{Sj!41TrE#Eng-QvuY~eTWu*e3aJ+Pywj}**<oN4
znmLUXfRIeB9|)F<iD_hP+LBUbhY*P|`oUP^@u=$ecbAa<Fn#Cjzr|BZ5(7OXJh3v4
zF*;g9&SDWmWolCxEI9aF@vJod!Z=dG$=(A9H{uJ~C4s?4%%GRpSu>F+QnO17PV?xj
z+KXA~A#m;c?FR~N(ZDtm2|DA}hSK(kNvVh^f$VK*H$lnIZ9DTR+R<cat49*(XAUBi
zn6H>iLA;2YWMz$nXy(?2aChP^<y50dSF9VGdSULW0C^SYa9%#3MnlZl)&(J8?Vp|E
zO>78tiL;$@vO_9J#>5=N5(asa6M1c?sj?ws(K)r|P|Cg?_LFV|kNL3+vXo4gK}}f|
z-+hpt7AB$GNfeUjW++2K^nqqvk;n;0KvALPH`@R+Jn}q;)QeB<sb1LIQ1_X3;R^O*
z`c|uVp^%4!z=3;ACayu0EOw9%q%I<Cp+sJ`wn9l+f61@1e=kFx0+ju&XR$)CCt_Pk
zPe^sMbdbU?iKSqR4A~wACOJh+#aJ`$A<J;EJLq`R3Umtx3zG}JhUdJ<2}Q<z)_rtU
zXLFfVxTW;_?R`vF)*NwA0=&2T|FHHp&~=>WedpZah`Cl7``*ztIzhDT%wR4!06~d_
zXcyselRGb7fCCUBK^SHjR%-*-mo%-|(Z|uc+HAYNGZ;`q2oyg8d)aK70PrPCJK98I
z8L!edH9&(7<0`SFs9ANlT}zC7>XVa=DOF9GZd&i}8Ay(k)6?BOr$gf6YcThHpZ9s6
zkN@-Wk`?KeV1{)%8e@<#Hq=MJEJu#?Pi{c15uo^O^9a}PZ{I51D8nmN8>EcF`lxVo
zk4!08L3^WaH%Df_L_ROQSY;hOMCZsT{SKPwN+Abt8SswbAZ2BJpQK6L&Yplq8@_+Y
zH;*4_MkLgZSi*&e-xFm54h!`Kyk>7Ujy;@3^PoClwV1Cze}2=cD+%jM$s3}!GDWr+
z0!Hi|pE0w90=wd~ijoxLpYUpPgq}XoKscEdGJJ$ZIPg)w55B24)d5t}krNSsWyIdr
zBJ|}+=WKZdb`H8@lHASj92*xGIg@9==$}v}h$O*u*@x150T}_zFW-wTk-}Sl6>TLb
ztH4Miv5_m_eKv+G<B~!SVzp_StlDA!%f4h_nte^b)&EK_O_2S%h2bE&Tlf&8j{m}7
zg~>vgzRRSl{FKfRXJF~<>oTXkeeDrbENY?;<a>Vz>yNLhq$C@jm&oi2VIx)bkf@j?
zj@O9v3pKF4@E74Kdb6fe{yD$5DH#8Kez?D>z1fygx1c14YZpu+K4AbD#Z;iPV3@1l
zQQOIoCbURD#d4P2|F=sla^Z|i<dtrUdqI6U%m*h)YM!V1#pZ&~t07f!pjSOB7>dkJ
z(0bZk0h^-?h@lVfsSOwCDp7RTf6MlJ%{uiORIjr>EzZitcmY;<7g}XjqA^G}J&xe3
zPdDd}sT*{=B|`z9jS|)QJN9p|p2ap~0g(}^L|Vzz9yzR~2*(xNgfSv>WR|QQs47gs
z=vtse5<d5r2YvT(-!|_nJhcAny=%R*(FoyP;XasHARL&oz%2P0n*>RBVs`RYy*xq=
zd5yH8$wh4D+g}JpX#l5G3NJ{C5s_Kq*%pFIDH-x#LR3MU<X2D%LTP!pWP*q~*<M3v
z!6*Ht{<-w`g`e*Cm8k5ASM;qWUL29ku2D<Sd&J1QsA@4o#GiDRf#;^PPW>QF2Kle2
zH;`HL&UZg2+ZEh`hB5Fwo#bQy(jIZL2fjiKi)Akt!ES<$5Fg-AAGi1&HV%Fie;tW!
zL&hG-4{TcryoJM4YKM>Xoazk--eNy+k30p|lpQL4NKu7KJ@gC-1ljt=x+Z&+Mk#lW
zJ_xrO4Z)xhpaNA4Gn}f8x+#)>{xZNi<MoL87Qu%FhxstYK@CWS5s;Lwy|v=-8XUCl
z)xm*Pq$wMaj>*@Nqb&@7^2_R?sA~eKBS<AJQh2mbVQ{GD;k#V_&N#8T=?pgwqDjpB
z_ICrx{y+mEvPzYY+Oh)#GuvEMb{@RVwJEk(L%wHSn>fmd@98FV!;s*DZj24%EA_9E
zAB31k$`4W%ay59nw|76rgn~%NO*W>Cv5;WKfHW6k5k_%rYm%drO|G(c6O^?^M$DJb
z+FOJ{DVP$EgLo0rO9F1ChMHQv^jEOgHKaWnU9b-UX~0sjorEDIqC`_bvYDlk``bis
zS=`=LzwX;7aDl-fyS7%W5sUL+Y!`b8Xa$iC^(<jSb>tiK2>K0Dm<eJfM&;-U6c($>
znNO&oVQ`5pctg_X>^+PEg25oRY^pjOt8mSZ6Tu>{0<=)T<-Ou>v_YFlpMvefx_`ZQ
z<keor43Q>LRZvKi(<h`a!W=wCgfY$=;->df+)Zz62@u8lhPaOLox@UZErzOK5+7vg
zvASsVRM{e~^$%fU4vyoaC|F!aq>s{F*moF*%HSmHh}lzPov!%%yjOgxQYfF`C>;Oo
zAm}BfQoOV&MTP~?B^)MR8hcVKOR*~v9Uzk3$G$7MHb-x6OzI>_j87~;Sqa172uY-4
zu#PSGA$9}v^1QzgV1;xLC&3%3$$?G83~Xd_13sbVBr(_gdU_Sd?3RyhAAAa0N@J4(
ztd2$sW<rKxG|Om$5u8O895(@Y$x)|qDtSvc$d*dJ_4j^+(Fkk~nWCy<P++cm1pYEQ
z@39l{G06=V?;yH>7Q@OMnQmg-iJw8*xu`iu6k>_q;QmlJ<n<@gL&d%7b7Dxdw~O4P
zQQG}snvGb|yO?Xi2_i38#8ILQCq}l{x*wvww(MDiMfvvk9!Ijs`my^&SluI$$H@F3
zYbT(Wyuwj#6$ba}R{cmXs1kukf$Iyy!J>l%u{<mXcgpWGU-#`-Xl&67&>-m)9&b|^
zfb3M(PFNiIf<N4fj#DXq;yAI9)%9e)Hhr@phnF19Kk<KVk(H}~#$lY2^gc}EQ;a}y
zeTqxQ^DeY6K}Vz8lhbOv#;C<Cskx^aj&8J~f~gGOCB8?#Qc$!&9wymmG(Z=hK)Nw3
z85#R@6JZry#(Q{Tn=<fVqkinxd@Sv6XitJnxcy~YvV5e_L84Y7lB6f=9)b@tBQ7yP
zu$D!w@e`<S<EGI52X!5cm^@c<jM*$0rlh+8jZFFjc#LGa`Q$GY_A*uvtIU}iLUtCf
zu!|6*$1%cM$B#bqCO8*;B#OLZQlmbxbT^aOj9Q6Wm?CE!ylV@4k+t;5u>32)s@GS-
zJQ7|7jhH;an0ZHPgD{yf^H;HKQXkhp98fm?POtSTRlsb(<`!=>;hir~6462;k1<Jw
zI|=7v>tC-QJ4vt&2U}MJkG}o&`2tqOyb^<XlJ>PE&I}KmA1c%{f4!*|VGG-sp{xob
zLN@k#b3}tQ6Rp8<gj}FqAmt%uO~~*2NlJM<0CVC-L{_~JwQ#c#%q>+O=P|~+?2a8d
zeT%*y74Y6j%21NzSFU5E37&+$f#D@fR^cZ0ymz=jFprBNzJ)DawMbl)R)$@#6x}2X
zAz{rPpN2UY8!DF3ae_||$vlIDfp{1cO7;y>ov&N7gw9xa)?63X`6jH|b%9`}LfL9~
z!o$U&N?Wpbh#t{Q6rvGm_>WQqjb1DUD5oKLb-}*Cq7mqf;gTr~R$RbYB6k{~5h9}X
zh}Du&jlliyTJ!y4-H;{|^ijN9r@*c$1`+Os1RBMh<!YcRSW27f0L&X*KXU7MY|V2T
zUINs^@NWO)TRfFmTj7?$Wglg-z~djJ&zndL{_1W?sT53=#})B$bhT<6={?RT1{F1|
z2`>ud7MgQ%hSYfq<sK`<>L8JsF?a}3P(yZ6$zVCrgggj-j6{#I1-90^x-=~}Rs(Vy
z_4-DG14tWpe(P@*E-Xd^a=mCrUBnd#1lj~9DH#WjFo-0FbS(s05?@H-kcjYJTv)8%
zcX`IgPbAA})(@p3?m7Q)Iyu`<1mb<4z;a|m3TVq^<0Rs);T#0G7e{<7AAfRy`dx=X
zHINe(=Y_wyweY1H{8b4{uxM`f00^{TmLfp~f_M)|b(tT0kI}Fd4*>~53OJk$&Q-vu
zWSHz*9bC2t@1qXNH+P|~vCtxde*$JfQ=5PTJdg5x)W$;;k<+3|n(~clzr#v4Frqc-
zIkbp-tAH$_Q;{)YPZhNh_^&0TL~*?<>Y=;XSx6E*MHU1snb<vP*bbv&MJUDek>H$#
zEuoiHe@4v)vk@+<#+G8{Xaz<jTmYMi6l7(|7D5zG_pjWb8vrLKP24*njQ)ui-zO?m
zQYC2CSEY+Q{8hzfy+_t5%{m#ZSuTQAFqTL9K9!e~O&Q%J4!VZrD6cl!zUiWV>Lv|P
zE|69tr_M}`vLVpYVj#Y%=^0tTr<*PrvH>BZk532KX%8*1Yp~&OI1`R#WWWAD+>Pp_
zC>=rx%5{%IV<WZf!|Wir=FLPH0lpFlRZ1-}*Se-bMW6|dMJg6{X5rquzR$6$*Ngqx
zFS0Zm`CPBnI!+9VcSo)vP79eJ7;5!#TZxDX2;FmwNrV3RZPEPE4cf17tOJDaNJVjM
zc192+obxXPd>9l^P*l$)h|QRO0HFe8U_mHl6_5jhL2RYS7(T2cfGr<b#K#!(17CtI
z1Ggv-+SU6>vxR_QS1>#ooGc^AV9}bIS&B^yWR5D@egs=Sjz~Rhpog*~`SnX%Wh==-
zB36;{AN6R$_CbldAmzCViB)WAqpyUP#R}jT!ml1R#A4Z@6#GrrPvP@PzsH2T4)~Aw
z{*)4_Myp8Jw^0Okh5BMaz+QlWFg)@~b%Ko>)`rHa$tBG4z3;wHCV>4e01_)%DZ&|2
z>1AZ3O^{{1DM3X=GYs;NFd$kjQb!Ow8pM|#Aw9lHeivEHJ&*`|a^ONR^5NdPMlT`I
zFqEMOZ&Em9C>%B~qK@`q3|Svr^~jH$BrFk0L@$}Y^YF(uU20)>hJ;k7)j0W&6exkX
z6}}G0k>PsY9?JCFC6;f~q{M<pG#sJSfdxPaN36>}vmf3{lz)#(k)M7r48RwRAlzqB
z0gP>0Gc4B6g|V*Nn=q_CPA9?>$ML|9{n5z1*ofr{t4HGPufX%-hY1h@%X2ob=o`uL
zDpY&{xRFFb8*~qjK-c$RLWtf!F7_Mz*Vu{&`vkg#W<TLRe~V2>YS1R6L8pVMX21P8
z5|}+s`eB4j;ZZSU85`p(nmM7s8oCP<e02Kq$~+blGD}>r`8)Ry38G7g9XpWI8*11O
zxYj1a!d6I8gIqt*6Jmo;G9&;ix-N?r)PnIYQ}<wsNHameuLtLPdqpHokBW<?af~*@
zWSFJsWO2QS5POLBW-xNJncbM)VAnwO+n*g04T#wQGZ~GK(lBRg52z#xSu!SMAnlU;
zcZ6gjA5AP1wt9;fpif~E^7c)?UlAi%^@I9VWapy+>mlwZ8-CN1l?SmW;B7F1X;!m!
z{K%=Kb;FwHI1BN($d&&5&wc>8D1w~5M#?=T!G;-D?>Wxw4M>A9z<iP5@N%_?<rV=u
zC_jQ>g+>K_FgBw-f{{MJE!(LHk$USs)5kz=0mHT6Z~1S%2azU^Nf8);1xd|N8fW9<
z3zw!}+@Rt~<K|?~VR=I(3>O6XVPSHyMx|Q$9@5_mLA6qZdfpwHOQ@~qe8HcS&5Ai9
zM#!{69Jm6IwoRKbItfcX$peDZn4FmVjvp|C;x-wX)<wh}su7F|b`)Di?3-E4`0tEw
zoqs5<NIw*q>1h6UK8J8-`-u~V{PgJ7!xwzOPeDgoOvy$)n$JZ;)cjLPB<B!wTAS35
z(apako`Dr$xM7=`#MtOVEd3Gal)-5|D?ZJLIldE+^1Ka7{k9*>G<!*dL8!nvkzvyz
zKq|zgrkKac5e=ZmEwCNM{`M#l`lB0EUhDM{Yn^=Lv!5=DamhJdGD7$aQi{$-MIufS
zeaFI1lJU>ZXi>m_TZD!~4w%PmFy}B+sZmA&H0V)hkL@AG<0Y#;_Qbw)7Mk{{^p-EO
z-(CtnrH<P)kQ*_f{D`%?=HNTBvFL@velW2){1J(2(1#|icWDq3;<I29W#jK;Vt^qv
zgb}4S&qL~Slufm2$PQh}ic+}U^w*(Y75KTK@N1zX41{{da10DXw`U^>B@WpnI<DB=
z*9U{X^M0?gANM=t86syW9|=HTHy2xCv}CA}@8(I~uR;)E&Jn(uK2;y3;CBLJZ5!QD
z{#Rs&5D-Qbtpvp=sU<~$UP8DZjNoW~X*0d~H4eEd`dbu>Uc5X-=ZE49-|nJCIvtto
zCLLx$l2mQ01dPE3yWgtOxJMSBMU|E1JdmFp<lK-wJ9}tmmx367N_`S^>^OYNc0<-I
z@dt+@VH>&KlU^(Qf8Lg(MrM&;A}|6VwIf0O*fW<%#g6HlGjT5m*~~xrDKjc;C4oMf
zlWh8rlAi(;g!cDVR)~O+ADq!P9iRnvkP&sIv?~ZaY;@%HarA1#YP294zoJo>*M{8t
z-tfM3k3#}MkHRQ`NQ`$YH;Nf&&=}o=6WXAp-phW8jbGo2Qffx^kNX>(vqC@f2}#!f
z*26y{LXyGA&?Ij_uupjvbt2{o^o}`ah69Hw6{Q^(dq6t-0ML_)Rp-z{d|PZ*(!ZVV
zHzI~d9b$iK$|Uah-smxdest@rCup_?F(o8H!vJikE}4y7JbClvH+mwmJLt?edVH$4
zKD}|=c4`m3m}Hp2M&;!1Z|YzqCrFi?GYou&y4xcx0WJ~X`xR}b<ydbTfUH#KqKn0*
zr7IJeHDc?5qku6;1PLz+aaswgBuz4*)L*gN&)Zi)0x?5(FowSOZfwepMO;8QT}ox!
zvz%MRK#|1YNzz=ET8>G5L!u}|3<>Kv<<I6~vI{U%ZIFjS*3_O4Zh@bR?Jo_<i6Pk8
z{0sCcIbE77aq!7Xm4ia5T9+-RJ&hE=Dga#;d1?VHeW}Macd`LVCT#k>XhbYv7M%MC
z0zuH>DxqK$vuH8dqOdT&IIWzzrWb-_Ub_8Lg_mSm^1c6Xw`_a~TgXQRGlu-ss#FjQ
zDc}2FL=Z)%iG75)Yv4Jz>Q>8>-C&_uNc~}@-4sfkW7wgtQz~(soJ;PonEtzdmqWun
zZh`**H1YUb^(mmyTQ{iP$hdI?Bb4B@`iBB!K_TJ<AH?CpyO&lOMbrXXiHep)BqSSK
zZF4DWrc@MY$ixy!9}iZCd<>HNu~Ikh$xzND8A(hKlL7{k>9qNEF(({1Y+_Peo9k4%
z==tgF#>DhSl!+qw8~<uEAFuFE1<BeY+7QHOv;BS0A*q<rxFrVHE>-0C);e~m#%Km(
z6ssUAP=Ai8l9M0_N3(2?4!+{kI@V`#PSmXt(6~)1bpc|rV>caCtQnwR))0d*nLkDs
z=c9Tf(d(3Ma@h7yn9PChzrcOaMpAt~R0MuY)ToW$EuF2{c2cF0ICH>jg*C#iM<$#&
z4xWJvYqZ~p*upR~Sw3{Mm0QTh^L7ZQ7n*{uF1`U%5eyrHFEM~nPf`N9vudNB@Jqmx
zCEReN1J`dDI>F{6h=22`O~{DmJcXvlgb<*C-V###Etl+6G2z{WORAWHBC~9=i3vqQ
z76@kq{3IDF0yn^26wsM{dn77g?r82;W44rtP)1TXIlzC~Vm}u8j&aH6(j(I+U_va7
z??_>(9Dqgq5Ft!6f`3p(slfP1I*!-?ZbQgXBlH9NrtWb5nDB=|at2+oDyBHC(wBjZ
ziY^T{P@vdim-d?t!uV_8Sr`0~Cj$BuMs>ntqX4CxeI#QCeue8rpiwHT*owzTr#HTH
zOik)_O^r^*8f4G?v%ADIEJPZck!EGYrP+ucKsP!rlk10DfX#FChp_o(lR35|tkx_R
zwV^kpIg~8E)BaLblHTs&uAV6twilDul1wzHBiDqizDP2f6xKzjV|)XkE5g&qkKDR3
zKAo`>){|rdh#4(==fkojQk90VAmAhYBXC?jY=&XJ+_Vfa3@MMqOh5!Vl~;TTNr~FE
zMo=M99sNfKyfuc1`XCr(4t5U$YvX5JN80w^QjZ584kn44h<^<)h_fhL0uU*cv=NVK
z!W<-_HI7`KFOM93QL>^D;N|3}FE(U!gfEaCNRATxHau)@TKBk&;+T=F#`cl|H`$#A
z0E~)2l*s1H7_JWr==(Iq+UYegs_I#jAP}CLwmd8xDzGiAaWPv&$;)6GU4*cXwD5|i
zR_CW~CX8iX`dGo!w=dt>R8vAI#)Db4hh=3K{J_GeVEAr?1|~$coMZ{M3PJ=d7MX29
zGjzDJacy4JE7b>UB4a5ir6j0-*7Lejb6^nPdIYzlxDg-;lZpB&U}w(V@Jeo}`!SnS
z*btr!l)d76T8yyn>2&01yuLvKD9x#;`1<!B7S3Z)D;OnWVu?+{F=cz+^@|GsOqjSh
ztVvjTQg50$>@AF9Ku$!ziJk`r_XQ&9H6IK<NoIxs17sY?PLK=h3(3z1`iKMpLsD6&
zp+nZvmUSA1gs{!d9=c0hHF6k>+ygZ{C5NEU68qhR7OaF~KmxxZX$zako9v}}e0o%q
z>IW6r**N~8G1v{yhkX))-R%#*-Rloy{uXzQqR6ADQ4Fi-EL-^KA}~n$898#xn<sPe
zUTIq@dBx?k|BytEVsnCji$}c|6()*6+6{26$T{pk=#8|;;h15DNv*=H#}ETABBri%
z5O@-gYRg|Fd~BXf*X4VU`)bf12C0<PB~7x80C0lqGD9|rS0b?c7}BGH`6(LV2ylNO
zHFicpvH3eAR|$$r%D5<T3=IhXL3IxcI{d?|2EmM{s}+G!B@9$#@F0%BW4A&#9#FKs
zLz68JwpZ-kcJD23(5CBjSZ}G`sbIE&?kJShZt76j20SicAdrG_dEN-8qfMhU9;V(k
zA<+h)ha*n@Ng@7-Ukl;zZfX93&s{hcEMy}7tzpcS5@R>;{NwznVb0E0EDTs7Rs;8O
zxu-a5;5pkT!QKZ~3h(RHGz-MmVZBE9%r;~8G9I^t^XQ?OL{6}f&Ev4(GxJk=J-Q)1
zE$#(E&A#oKVz$8WNL#FM0#fn`T%28vS`r5PLA;C;u`qg}J(#)&tb{Xy+?0i3ApPbJ
z`r}>z4VdzyvF4`XPqz}`L8KqoqZHC^3JOFP!^D_9>R;-LCu)Q;G}aEV{I~z){lc*V
zRB}SZUO6s{?RU>%NXsQ^nk$nR8Hk5hTB~hEllUHc4=!Q<Nq)0QuYCWyq{a3NEP!s5
z=!@iy6X6)q)HKN@=7^{wRnX4&>a>lBkLVkc&qNayJiYR_pS8ptY-}zW(p}=N?`7XH
z01xqwX3PpBY|`(mvhR@tp4SRU^#o#$+N_#SFeRNMG*BJ%$v?W~r#8Drz`24v3<}<c
zMw33Fc(KvI|9T1O)zq<7h8xGV>5RTXartkYd_UsJz<-wLlc*b_Pd~7}sQQ#cZWs;>
zkhDF(S4j#mE7~R<6TMy75E?#e`#?4At2oQHM0f^#pXQyxEL7gSX``m$Rk(;_7cd}%
z5vUs!yHY^-tt0n7^dhe71bVP?XZlK^X~?*%65qr!pyl^_6p|tX;O^xrDS&632K`hw
zWfXB>Ro_Z%USL_QbZ`eyZ#N-?PskPjDj>#F_f!0c&AWIvR;@TD2|5|>%RU-Vq_5u~
zI(mF+w8LiGz<AcQd89&v{uIA*URX(_0N8iQkd(U*ezZp_GmuB*%QxuD?Lu|9sUiYE
z_{s2Q#kutjTpL|%I8Rz;c)`Fg_^<ngLC8sAvm;QWZo=3j*cV#xI@$hxk#Hn=903~<
z**SmoD<resAk(xE=-EquV#?m6=L7B!If>ZLf*|#L$dsK{a5mahOe~%Tnv7o7ErE)$
z<zZnq8nFs|GEpzeq+NzjAYX3;#XU$H0khxLE^H4;s+O&fFT{}o$Fb-S9{r;cl6x}g
z>Ah~ynfT261Wv&06AOmrGd^^f#{7rLa}X*ib248eY!3#;68@kOA)<(cA-b4*Eu$h8
z%MoCIssBq4aIW{zPWsub4|-wmRbP_%d;j82scw#nsWr?VArz{bWy437a>{Q;m7^Q$
zBI?1bUT?|)vU0wNpd6?=mX4L<Rr+N3{2`K3<lAyJ<F#(55xcHF3P?QFLi@qxs5I`7
z4&y1E&|mSd`bo1#vXFKV2^a=@Cbx?v##)yeSZrk=fkGb0LO^T6P4GGbqdr9h^PvqQ
znNb8B@j`8@Jh>sUlnOB&QrmFHD1^nD<zjRds=<+%yXiv=dgpBFgi%ZEQ61G;o`&o{
zx^{4|&VVU-M?udk&Fg_=eQe&sJw>$=R$j@gUzaoh`7POT_!q~I{8}qYFoN|4XP=b6
zR=o>z4N`5cA*uxcg}UJfK2-9U&%83}^x)9x9OZ%_0)WTGhqaEI;K9Lc5EupuOkx94
zeMC5VU<-vbb?K?I>VMY9kN~9DYAX=E1c1<Vn6WH@06SRDvh(!p$kf6mIhS_697$L%
zyZyO`3o{3<q7%_!a2)}uNGhc_*rtsDt+^6;k=Y?dr4J3=7|9><;d3rzCT2^2N<X!$
zgYx31o5@cIYm(|fltv+!wu+kz-w<N}%>$u|P}xJB$&GA1syrkn`+WIte5hzXC?|}f
z-+UIT2x1OysumssfyAnlP6%}q<KI9I(2os~7ezGxE%ue0_!N78RI0QB-~S8&`xBp1
zjODmwZzBzaCuKa+Oh&R~1^Z$L%Xm4{fsUOuVGayCVoMDP5(<aQ%1KsTL8PgBss-31
z<HPBq9~eTj{1m+_C3?@uAbyLa9%Nn%!EDLVr>=+jG>A;I`@NU_Rqr|E6k~gpuJiB|
zcLUiJe&K_X5CIo3!zth9LmV&({cIJ*XOC|~$83WL-~BbozYw#N5i&mXjQIG2;z3Y-
z!P_xLiJ;&CgTRz37YNm2%7S8d)w-ss4+<itM;#^Q$*$Sm^9zy`avyf*z+muT?|$iH
zwt16CPd!}FY{naSj94<b4V@T{1DM!HIwMo*dP5|FL<y2C`KgERCU_#oxyUQbgFSmF
zkEJQ+9<hBrPgYTM7AUTyUN9sN35{2yTMeRdunWKKHc58Hdp-|Pb=7Bqdf&StY83p$
zJtSNdS}!P=0AbgxPk*IOgwUFozMH5Q7V-Xl9}sa~j76e^f)dvZugX9QVIZ7Pm`<#j
zi>`t#s0prPIPx~4iAlR9Z_S5MY-y@t-0uCM8(=3GO8BW^7E6U-k}^)EAM!69xk(Dv
z(TwdjK|S5qoVz1gF7m=Q4Fg6qjA<YZ$i??BT93$Rc$Vz`%@65XgC9y-k?=M^41I9=
zn^;)HxX7*`0#`>!PzsDD<ceS%QA`4!%L8mnrZb&=2guN(N7_b&BF(;i76`&<09N6(
zgTs6X=?&bmndZb_;|m&HVtd=H7xtXjC`^2qR9cW0yG&B=)0LjELJrY&-`nX=+)~$j
zTL4;rao2KHASS7GkY^xw$z%0e>{q%cUxF?-j*=iiJ)fkF{@fE{he>WU@~AkN1g8`G
zk~BzGMCQVtBpPkA(HIpz8Eyrdbd-sj6o0T<BqWd{(DoCMMgo(l5wBO8cZe7?;5t#x
z5t9-~P^^*$$v$Kv!Nb#+>r*G?%oo~*V`gU{df)$ojK{zPU~@&F8Xr20QzwzrB4`tI
zI)Mml(5ggE?&kQ-c4_m7DRQwTdrlwcs6kJ-!x?_QmXwyg<-z4ar(1!!3=rCVNvRD|
zb~bM$t|W9t_llmA?1B<8hCzYlNI)So|HR0V6JCe7_XNYNOfSmGtM~u86lhA8C@^h=
zqk^A4MSNS>sSs<jf>3P{?qmVPXk@2g6&3Ob6I|9%{-NAZa06h+!*2)v2+;;41Hwoy
zF;&=Vpa-lV5`{DoTe=$@>8&5@k2Knipf%Y|-%sBs+|4$_isM`vX{%5dl)JPCD@U@y
z-n|+~po*!{M{H_OBi3-5m<HZJ|CWAowkx1zwAkx?RdWzj3;Mi!lk9p}o8S<^HU@(1
z9YsK)NH`tx6m_fXm;gE{AZ(oSLmw&Q5+H>n?S%Yxq~jn0@uRZwapzYrVFVn_&pEFr
zrAk@OYawBFvy;4mIAUzaH5~?_fJHfPl|pw~oA}{i*n8ckXZdyXUXPri1%5G#=_fY=
zdOTK>l#e3j+OA#zltHK<D`|^`h_4^Hyi))8%?*GbD+1#D+S6OmrdCn<TN5THdx+Z)
zgJeT91D}QEqoF2p60_Hobh$d^?V~u{Q%!DwXhg1LSRULC$$WiCaeP*QLYY<tWg+b*
z%_KTkkc=D)u&5?Il5VYN#G^oqWQvxh%zWra5R^uxBwi&n;!rArBn3vs{_{w*%0$wM
zaP~?(5T;^FDYks?h&ju4VXgQN7qpXAUqlsfKekHKpFq!v_lv@)6!nL4CmRi6)h^kf
zc#p!bydy?5WRg_Usm`VC(-Suy(l@5HWT7~B{<oiL@E39@A!kMldl6H+hkO)rm<lbN
zAU_ixM-#yk6$>a~8qf#FyFj|cLe~xa5;6!4cg3eX!1t2325A>3huOT+dc0Tip-oV0
zR*|8B-+Gvu1b21;iR`jP3!@P#j86_6n>xi#oS4q_I(aAv%kN#<R!H_jTvbWuE0WZP
zMbALa!efy3O@>nlA`YRJ+-pQOGRe?Tl%(j@p50U)d!&MypOLJ_F8W`-djoUgzM!6B
z4++zYWN9&=7GnR3EMdjrtd%@zy!NlL?66$1G7D{2Xd3BIQ|LLd#|v?QM6f;JnJV+$
zG*v1hd@K|URRFGU!cN-<dmiv-d~aFQ85^aLPVbuQxWJpSUIZ|*myrY<a6h$3vC>4=
zxK~To-v6GXju1@^f`s%6H>Ke{#}5e=<$nOISt)ZSM*DfETE_ecdP=Z3qOK;6c?7f*
zu?n@I<a&wOz1kBt2JJ8;!K&HpeZqhDCg@l&+^{SwC_m>TNg!T`<Pqs%o&3r4J8Ii}
zjgotybPDdBJ3sM;C{nU11V@)F0mLRAr_d&-cROPF6+1?Du1HOIlD1RWD6;{#$eC+|
z9Y9>$1c}YprGkSy_AA5?qP4h(#5ggyxG#9gFGB5%vl&D(unwE$W`=sjrO6ZH?CKU2
zk{I8pJa!tn0aZ#R@BmPjygwtENkoJjI2d9S1e3iuz|A__6t7kkvAe}hQ{<8TI`$-|
zWgI}=gO(goJeLI%@hy*GHZY&WbwE;-{&;_#KJ)nCBx2K`zWnXS-X~-c(T!Cissw;Z
zmO=)yiC&W6#aIeW!jn8Kqa&z+T9N05Ue!R%lDZ^LZxeH%he1)27erA(8m~Z5STD^Z
zM5Cik;7H~pggZ`ztA1n=`MoGd5hA@Cclw6i>%OsDdG}`~L?R@Zx$2_ldCq{<{b2=q
z8^)v8eT7W2?A?L>u%%)W(Rv5N?yO!qcTxkzoz!GyhuKD4_bubmX~#Of5gOywvgfGS
zGmJ4)8(CjgE1&a`lkx7jlACrmHRHKi$uQbmMlY(Tg2p?4IEV#Ux$eid?;EP&O(kw-
z8b@u_ZPxs@PfRSejKrWOSa%}FxG!!ZhrCh}WX2>%!eyQtSaYq!^-2*r6H58c?pPrf
zyb0mDJ}b@u65D1wiNdXl$X6^0qml2f2lmuaH+uGuU9~kk7ke`qJsNMNvssAEztm2(
zS@R6nbX!5}>M;AFI%#xuY!=>7<V>}f)M%R8+jLeC!D`nAmC>%oSzw1|qr960h}~c(
zNJ(SS8ov<E1%sS^aF?+=b}xIO$CK+8Nf}0vjheUr$Dm<lJlMrBA-vhopK%2-FB#Ue
zFD3?jXi4I0!)#l^vhraVQ;dcxbHjk%0vGVZHh=7kU_7V5;ItvRF_rT7AAUa%tCTUe
zxjSxK@w<`}HCVK&;itZ91$;{Q*wjVx9HYlH+)UWK_&KdjT#L7ejkd*m^0#j3_O1u0
zA;iwS8J@lxCMzDtu2tXYTKAei9*icvZ!3SmQUjUxc?wCp#eIVur%>uncdQKecY<+0
z^H-HuPg}v<t7!|f=xDaC8<_Q2uc4PD-b$^z6D$Y)!DZFE3gxH$ct<b_i~-|Uren7J
zS~!Q>$2<F%qVbiWKkL1W)>gZe{I6eEn2OQ4+RS?9a2odupWMRO|La`0fBNuWJjjLk
zKe#p_V~F*auePxNf98^?3D?hkg@;7v{Un@wIkwAA*0rF@y;tns(%PWErW$Je?r>-{
zZT8OjB|n_ImFW1F0^{`FVA0YW8~#ezuAc0uZYyvaX{H^vr$I(%xi8C5)#Yr)OCqP+
z4@#dqrBBWq&NE>+82gFeuKIrMVmwf4m)cRh>gi=~=J-J;n!;L!-(Lvd`SP7}LEH5I
z`uecBX#Y-73C%M$%oMhTUC#{8X^u>AQwW<)A-~Ee{nNopv_JI&!;AcmI-0<73MRVG
zQI)vAw1%vp;S2jv8Do2#HS+iqaMC=rGHNZxcxGViv^&FD=|Ow6d{nZN+-BlGGWUMk
ziCGwxHK#mREze|+_Ivk~+I#$&U?yO9G<#=)-iyu}7;2VmoaS-5p{xymac|I$LJR9D
z@{xIJF4HEUe6|$ZUdB^u*JG>&$NjM446-&AICIR)@%+9GIJU<cFVR`EVuiMHw6Tm4
z+Fpu3{>z4^jNO6J;OM=)CYcCsx|QX7F7}z4F=4hlK^(ePTbKEE$Ox71Z5WM|iW#es
zdE!i>sLKOhDR!G_x5D>27c|N$Mp((#io%j>ZqGUSL%f!f5luO})$Q;6F@hkZQ$Uhc
ztY9&%ny#5K^N6?e*t0XK<GDR%5FBMsM@ATb#xGb7;40|tblL5y^Ga;RI@w+GQM$2v
z*GO4q@iXCzIv<V`Z%YzB3|^lsBzwTboR>225X0V`wb_ZKImGWHUoFj>13I@uyPR#1
z!FV-p7WVYHraS8!%ihzfZT6NI{XK!}pGsQ@miAJp+h!c?oDw2T#>AWKjbLA3Imt}M
zdCQfI$-lmC#cHHHJ{Tr*Pfo{S=^k^?4U*B!G@ee{rDe~#eMRri*;mfmQakayWN*mQ
z?EG7Xp1I!d?YMAqF1T=VN1DZ*`3;;2-+#&u=gj-l4Vt|K$y~jQQ&Rdmq9rQ#2Br1|
zrz`B(`;!-Y&IgWuO6>~!H~NomkDac}JEhavXl8%qnjh%=c{^Koj?xm^f94@)e`?!F
zyQdVNe!^a;2gjqwpR0x1YKNDDg%9T0jo7iDiYAt7cANIt*+PO+L~TsyU{9?(d*?%6
zHL6&o{)I5v9roGfVBSh_3L54jT_?}jZg7|3Ia#yfV4j6O4EbVWMuy*84toNtoy=KY
z_<CXnVIzen9OJZa{f=qtbA!Y>cKLJXol2+HF6VQWG47X;;>!`;m(tTwc>%4|M)24N
zoW`B%Zy8aTIHO8uSqd-i4%yl&)@5Wxdy8>!uis7s&+6w;_b6**elzj2NzS>w8tC%r
zEtQj*>yvjhNKB@2;b>zhX8&j6mT8P36`#%$6Cc?%<MuW+{=UW#ex+@6Th20NRvq3Z
z(y<%7^Q$lO2X2)u31$N4X8jQ>W-gj&?AY%^SQu?TD!0jT3ImJGgcMsI??b}g&Wy&$
zt-}a5J{;)^k2+?ax<QQ;v~sLfWaQvm<>#`F=iqd}zmALYW!p{}Zt44P{YccXbdrRP
zz;-4s%HaqoU(dD>USsOwULxuxee&F1f8BXeS&=_tPLNI6wy9H0=g!x9te~N7D+;5v
z+H&8rAVP`JIGJaL`@Ycqial5Mvpm6eaLT!}+J0YtWx*O#xmoDm+>RS}{?m^){EKm$
zHStiT2t_C=Rt}G<+*=+u+ts03C9@DGrG1v{C|1RZhfB5|<jst{4N`-nVaTaid2Zxu
zS^H*~`v{pl<VQo?;dDHEIiW)y?4a}L^Z)Z*dd#jZ1wq5k6%zqiU}nCaN!w}lI*{+~
zz_%lvVL_B8KsIG4R(*p5`U2^-Q|hzM1+1}K=Dpi1@l3osb5ADB*f<66o4#`@_il#r
z*LgcL6G_lv*<IRKsz?5hE#nu|x#nq6^_`#+TfKqRWZ&yXZ)?Mw3wrmqUQ($wn)@G$
zX_k<#2mN{|-~m`YQDCwSdQCrUX&%>8_dIk1#7**{EZ5y(QeKYWi^#cPtkvAI3%kQ1
z?#-Ibx--C%&Mz+TllGte`foMLp`Z93k{PS9g{>5|uZu|pi+Y(3Jxn8GJVgpcFCqOS
zzO&ou)^<|80CLLrM%2Dpb4zYDx3b7kgrd?kFYnG1*2po&O`{!JA;;*rUy>ui`L)&c
z<WFx^YjLJ%)5gBB5I(ynqWxKv@EBMhxj%09SQXyxs9S1SEQ76;(mj#Yw$3pF-nDH_
zK;paHawE6g72elol|aTy=m^8V=!WORbk(^SNBKm4`h7;;T{d!OIN!6B>$3;M=SmDV
zLnW^c1?Za@?f4^Q-p9R*IIzK6>b8YSYn!P4G%z8uR<Im2<h^q7{StH^Be{GraIN@U
z?5F&J5zeLjFvV41nf!9j{lPm2zH5-c2;5}NSqFmM+N}-6zC!d*)CRW3=K!Y8jk>Mq
zB%9K&WcTEerTY1@)K*piSfTBPg%9GpW`r@Ens9HP#QC<ovEfV^dM%(%7@!3HH!>#W
z##Y-ep)*}HBvRn^Po6NwvJ2YX8+*#NAos8}SId2snS485GK_H#|2BaQRNRQQHGm3c
zUE5|OH60^rYy>mVWI0CeE?6pcQn)F>H7YMBsVkczb<y-!!l*wEWU=x#!Q9+f%TmoY
z`}W7I{lSTi)>-{_s844n(lhF;woh*S&J!o!sl~$^t>IV0C-l&Op13vgxU(@aymZu$
ze@Bfj=|3Et{`$tTi8r$A1EcXjt$m|*z#jeM>s6;_?WfzzfmtzL?GIbVSTcBIe0FwV
zHv05$)CPmG3qfQ!d3rHjSfQE5#b1sW`%Z^9Z|={rQ1W#3C$oHYaVYB#uY_|igeMpB
zQ#bQGKh;_|m4#QF1AXwz$%Xqa9_Smgoqgf2I{C!|PWKC0@<O(f960*5KfUX~_`x7L
zs|Q<)e~|W``dqm5nX#rG%W8if#Or6(6T!`ak(<H9-jffW{Q9cu$*!GzWA;KY`j3Mr
zTAbDCy}8lE?(WUr)<a`^f?j=ZOAqU-wG+eJgRwpONbQNK;Ef>hTG0-lgx`@{`h1st
zAe!K0fxTKEh%T<C$MT<eb-`Qwvh#Fus<U+J;%l#*zEm4u&xiA04X^y;;9q8EhVs)l
z^V9wL3;Aq*;Y$1r)1KJ*6HBS_ba=Ws<|gxB3iC8gyK{Vq`1hPYxwMu&I6mG?=Qk9u
z$)`I(@6mXyQ(K(6Io3PMm%jgUd`<h0J9*F<?5cHw{x_nR13pEy%vVc#yyv6wSfJxq
zgUem^=u*&MUmqRr*mfVcuq>9-^=fa>vH44Ht;T}~^K{%xuEgWs^KqCTPfia!TkX0S
zD`$H?mtPGbbUc15J)bXR&6Jl<&gH4<x|lDla&X8M_R(oxywdopy**3YtTG=9!M}U*
zuTQoPs)xTA&Yui=K9)bbqSe`S>dc{0O<(>e^^%%@eBxi}tNzygtzE7Dx0jrQYFB0-
z@(w@Se{JZat^IHIuRcJ*<-S|#)Z#(?@V}Y6=Rdae!RSml@=oi-&yP;&;j4pRsvZj7
zQF`c5-}CCt(Pw-1&wfgu<CNe>Hafch-_~kTzd7=b*2g*z+;gXseLU)3%@65kKepY@
z9?beEvpBnWZR6SMKmW0_*_(RX@8-Xo`_C=CrEiW?%Jt2G>Xm%lN<I+}bq+?S-(Jjf
zJ9s90rsF-D|MB=0Z}@!&H~Rl@%qu@#o%oko**<Xbz{dDH)BoLMaB!UJkJz5dUmDH+
zGz{nemA10^zpF3%llp+~lPzMMU8$O{&qkMnr}u2P-|YWWj&GmV{@isc;GV9|U(<xI
z^r6wqC%Q}b1r&B19Nnq+sa5^(Wjpw+c3*D25p?w6p{PXrgF`x7xhLNrk7tMV__H6o
zjkRP`NATjrft+N@Gx50ft<!(Dn1|2ReiNFUP1O|*dZqc@gW1Ft9iCa-AG>eFCzbI`
zHqoD!#)ChMzMQw8&xSH%Y$&t;+XKe^tt^|$$M>rF_=1u(Ts)xT<i>wG(HqN*8iVR!
z(625i<6G<1tIgF14n>cRUT&QU=W8ARX+L7^t_|7Speai+y7Q+SPXwJk-Op>*t^Z5a
zo%-R<o<p;bDa+YEd%v#1M75F39O>v|mmXLsj|XpM8T0CXD_cyZH0H$@e{bVC=dCy%
z?^MtJ&cD2wuU3D#c0lv=g)1+<p04KO&py!apNz+Ack;zU>hA96vx`~3`P=z{)Ga-H
z>JP^r%cRD)JQM5jclP`n<B_nVCvOI^%<Uv|yQ$;s##jBXHqGdO@2;yJYbNOH_#7s&
z(6hQ{du>M$`y(+6`jCG3R(cQlE3XHaKh_9V_jJF}>S%jek6*TRpJflcrAIxx`>-~a
zHN7}^xeX)U^=KBrcTZ0|lPwpkGymuL;_^MGt`&=uvN)@LI{vJ`Z|;Tcik@8j%H8&X
z{6OAs@_NNsKH+a)Iuw^*k7H{sJ9XFhK4OBX?QBlIs2+YN3<IU;j}bGMtE%HS-c+mp
zZarb0O;+@B^~ScHDm)auq4)ZOBbJ|yT+^Kg7KiU>9nY6(vYH;&fOpYI_I2Cij<2#H
zHmfkyT@B1h-QBq-UAR)U7xF7rXD%m^_o@8%HoB9NyOQg$+q;>uTbFaP6Y_;}|KpjQ
zP?%rwyQ`fmJhVUeOa19Ts;%UPekL;(V(V+(mXTAP6O;LPHl3eSEZ_WMr`GtQiYwQG
zRln<TLVLHJ?w+huz488W|CSeZT4x*``EyhHfS#Hgp4Mu<j5(<BLOXsJ#@*zoF``Ys
zyA)z6>|4px?$U$VLfPIQr^avJ{HE2mo~ykt?0$Z!k8zdqnbf^f?SDnzWFgo;{eG#p
z<F~&Xhbco{J#XyJQe!ME|KhgF7uDp=@xA`p)Ep0pa!+I=9YS;VQShnYem3hX{$ABx
zy7bSQ)^_K9eNFwT6K0zGr}AiUK7K(n#gXaOz9f1g$jqp2;j(wDTiR-<YbsL~a$%$s
z`T2uccZn|l5cqd97P<T77w=^J$Z&qSb|?;4{b#aM9e>}~VRXNLHD7+feKO0;v7?M*
zWGOQqTpTMK?O#}ul*k7&<J7c%>EC~#GYgR6Z#eCa&gQ3ULjV@h&o&!xkLzJ8*tMa$
zqp4o?`s|)@wsp1qQeJYW^TtXrUuH=$ryE<{^=#SJo{<F}!4mAp(xcg>Jum67Y(JRo
zjEx)jTK2>?a&f7)++bkcQTe%WOWJSd56&BmW1l}8e^%pr9g590(%nX^+u7o9`6Vp-
zZ@=<^H`o0|JKNhF3Pu7uZq>S*X=?(AdYAT{dTIs}&Z^xCl>cnWqoj%&t&%gOYhk5!
z&Gw_E(Qz}-L(W8b&~T&oFWXV%JM_~|%<0fRr7cJA(#8f!GZST6SO)3vFD)+Hc{{~F
z^P}mocPN`MooH9fue=y^n-ihmj10Srh(ztYR^N&~aO$Q~7|+#<n3^Li!KA2E=VH@;
zDc-C7wGD-T+V~|sZjx7~qtF;h%(iLtZN=o;m4!3WtkLyQAeJd^+ev50NS$-}P8{z%
zZQRU^JT(?Edeb$GfkuAP3Hg2dg%le)_tvv^GL*H~p;J4I-+JTnO!R*Z|9Ehp^HlU%
zKKDN9y!zp5(I@B5WRHZ`qS?7K^PdkdcXhpX^v=Bh@NDwG{Py1-=;zZgpWax%^9+B2
zeNcS9&p8|2IVI1y<7AHv{oo;E|1}=+|9d3=;qvB4IzKd$|M!Qe!p`_!*nuE28#Vs;
z-v>Hy(`I^_&{f!0<x08jr~G7)oWQ|w@q&}Na=Q1;cuq@)DmkN&OF8WTq2OjX3WN|0
zd>GrIeKt-#$$c^3m--W)^K=0C!#DCb;(W<9`j+~c;tP4ne(=?Q_KWb{p8`H?Ua-mL
z^%qZd-}>2SZmZ0RvM;Hlp<g+9UG<X0{RbiEZsvYE$Z5IM5c}Tg2Yf#cx^DHZhsmgU
z2B)PdGB6rbcULUEyjMTGZa-WiuWzX~QR>>-WsN0P<V0~h3Hxf&9lVt!$%FB8+H|9d
z_{~$Z!=WDj`io=J@jnl>ujkBOCq8-lVD0H3QP9x$n{!4623m5adY2rh^2Q%*^{5i-
z=~~F_d&??J5?yy36L7+B_?+@eT<7QPITcvLffWOzJ?flNj!8PtKI>T1n<5!lQhFPm
z2*@ADwVRp?=bV#)o*uiK+}tpo>q(pH>7~)y$?>+gPWg29bfV|B#xp6MSAAS4m#D0}
zBIgbNgI`<IM}b!6&Bo(FIdSz(AKXBQRWbWa?=+2M#%<8XEQorYz)!Z;{lhqChEEW}
ziv7U7&~l8=l)C6F;ghA(@0H_*a}tP`!BygI`n1lXEV3pr2$a<rx`OPJm2R7r9GbS1
zn$Ao1BVQ|3%%swttGjzN5a%Xuk)L9O4arK8i{}Z9gn&gHv^~p+8~i|i(Xb+r!c(9_
zM1mTbIpm)<X-TEmvW9ia(hcIVW&6>f#EqaN&;7d}McKvDBPL@Qjm@VYq%Z_BR!k3f
zo^qsfe#3%U)l~O}4=V#K%UfyJD@V4G!Gu$Snh^4l9~V~x2#DBJ<}85MAt6i7BRhXI
zFp^G?^-aNNWiJaGvAi1)1aYdY(G;MZw<C@E(`IDgTz|ots-%hK&f@Jcy>>|xh_?`^
zQKLN70Hf=bt!Daz1k!>i1DUE=^VUS}c?pN!{EVp^ftQ!s&+mM{d-dLC8if97QoD3s
zPK*h4_ej}gYd14!wBjuXPB+kPB}>mchCWjZqs6Ff4@bcR!LXNYG5n+F*b(7aNspY=
zgc`Q3)!I?`1;9?r2~YdMd1pBpY-Dx~M94Uua{eGujM8!+soh~JN}xZo1_cyy=5+q2
z|LB5Y5Fe=E_s5Vd^B_Z;FI+YS<r=IgrNtTFEPFnHA3)7HI9z82)RxQ55F7-^q?@U0
zw*6YJ$_DT#PnEySO`c%4-#PiD5f0x2^b^JdHjfW_EoH#;29S9}TkRi#Zs0Ohgh%pg
zH>zo?FEF(c2NVEZCnp<p+L(#j)jZ(gZ9lg-KN1#m3G>DCmS1Tlzf)qVhVzn76cM1c
zi@ct7<5w>IsMJ1<a*A6!b~w7m7>OA&7!*}=JV`)2{w&Hu4nPE^gfIkp9Uus1N!V^1
zgCRM_aCV37Qadk2gU0Uj1&4u)L>b0d=6V2>Ox9hB{eSYG3_`jU@T<1f*J~A|tTY3p
z@p9BgWVDmgT1}Iur207ZNDq|wmDcaFI)Zu1-KG#AK~@D+Q@}ZIXfvdgz_5L|u(Ugq
zv_YGxLEQ;iL-)JWKWb!LmAfmB8SrJXEJn=fx{TWMc$(?4QMhI(Lo!@#@|KXUko9B-
zLx48_VL;Z8It`Pm03ckx!=)(u?K~~9d+459`e#F|XVy5GRZ>zUJ!2+QJl=3^pq)UO
z1EyPw+u02T_}HaWmXWWrjzXmXu|g2OXqS&Jue)W`49GO($j<X~0L>Cx9ui8L12xnj
zIz)0gHs+x@{uC-$YBx6rrb@E58OtAAYPs%OssfhO<5>r4aecLB#B{ZmRJe2gs5xdm
zO2xP1)&kvPA(fGW5^;@}lzT-@oi4Ru2`6%SD`A8N!wnH4th?hn@BE#MeCthy#+RCY
z<?g`cw?-SPw@pbhb0ML8KZE61Nwo@iNO379hM`mL=6?1GROUc}hNYbp60;=)xJ{s?
zT#c-J_TXRRbE@Oq>M#Cn#w%m8eqkT0+ZvB}KV_cth2vbyZlsYpV$v_6VGdiO)MfY(
zm8VzAz1xgow!CY~D-41-O8v3C%ugo-k8MBsc}%k1G1$406#w|!is@RTrkpz)vY5!)
znr(erW*fCja9u?QUX|1tGDU+@Y+Nv)n!AC7X_PeprLYVr33?1pIhXAYmeUy}$)sj6
zGUxk`Fzt#t6S!NIYq5@^NnPIGSMo1#gQcm8p9M=2FX*AfC$Oz^s(HVXF?hI{@o1*A
z<J!2WmTT_fHX~-uV|CQ^Gs1dmcg93fEociyOt{fE7Pe??nW*vdm$w8kAY?HzIEYQe
z(m)m0_CXq>G_xW?Q9Y`rmn1szpz7aHahD&hDkF$SQVW)`HMUbe&Nj@6sR*%y4(;&E
zu9ZxP5he*CT*IZ@SSV?jTDwW<Td$S^?3>_>dWw&r`K)g#rg0khDhrLZW;|dKQ9s$Y
zS{oX_KB)RUT7bT->|o-2*RH)gYxn6O_WH=t+)%^s(7Dd*d%&+>)2}qO`N_j-_^`4k
zYOwPJ1X~{Ke)is*-%LKUm^<vmSan^grBiWp-*-=~d_BBRk6#Vq7i!lLxx?uk=k{Ld
zPtx<9!3CJ&77!cI#oY%I+CxUv#hrTV*tZ*IGB?$Kx|Jng+S@<w4>IGqrIVw+m9$M2
zAN1Fn%PeEhHym}JeX{R(pt`QBgZBPle=xeF_6OrH_qMcG(I@ndplfNWYjx^#gS0W(
zYrhnDQQFe6iih8fg3Rk2?S6LbwS`W0A<f(~*PLs$f%!MH<jpKUG2h+kIz9hl+`iCR
zPQn8h@FUu#;hn2a`+XOk18Lr!dP(_!6#3i3rLngjyvL~L%`_psAe(=Uutt{L?+2Nk
z2Q=T2#gCQ$5<l)Ycd7AJz6>n+(2w{*$J3uxP00w`HF}`e>3&&mn~grJsJ=ejs~XUk
zk8!WG(5ZC;9V$CF>{wA1+9Avqk6$Gxq7&dU_LiftSCos7^7A>bhm+dAV%sU<koGKR
z`+Q>RM~(hlsX2OeYC2z>4R*Hrr@p*X*GL+f|M@t->W`|`pnovisqfd@ZY#C3d3vR~
zqXQ(f9XxY{Zk5XU*yt<vT_b-AxYP{x>yah3-QM3C=~VZJYa7xkW4{J5s&&=xHT8aN
zpR0{_s@>I<XFgsXN*A`B^;Q<osi&(4^`VLU`NfjpC2#309Lx_b=AR2ME&`<8N-xv^
zVP469A^FP9YWMH!J6Y#-Z_mc?3x2RC8~)1Ra2cTP`K3MCIVTz^I|r({{Zs$qE(0(p
zJE(d9H)4P>l59KLxX<q)K|Lh5YUil2Q||<Hp`%$3SyrnL7~@v^+LU*=<sIu(qx$6&
zM)bP(hJJ!FaiwTZ;aS~L4NIz{D@(fjQnj74|H3zuxANTB?))}LM%Qb3w(Zc^pXKqx
zm;L?m0l<O%pb)38W<S<>U@&z{`{U*6?(9H+ch4SP0pONX=fIB*m+_vB1J(5PS3Y1Y
z`@#LeUX^w353V(*@(wt_+cfDYMqRnuv;t7wtuKLj>{D;EAbQ_0pZctT$yDuD{pyr8
z@&}{Wn)E;oKBa&5M0a#mfsec~yGME5hg<c_y73O6Q>6vMS9PDQx>sIQ+nqBqgKsTv
zYurJ79UA-Z^DCo|W*b_~+$6K<nJn7(nDb<Ql<-=(`oJ2<<sN(DW@pIop~|P@cBHM>
z4=3fH`UG;eUrqUO;}ySiV*Y5ji}5ussPU=14gKXKh#~kO*fw=nuhXzX8D39T8u_B#
zT?L{=z3mzW*b(6AK=qLp1V7@VomHjQIow?WPR++V`su3iob$%SosEsk6|HVN&LN!#
z>31g<U(H{MfspL@T2^LChhl&-Ud!F<82|$>Wn<aizI4j6k*V8j&m_11WE6TEqgNG7
zax&O?qH&dKkt^Dm&&|ea&{);u9Up@4Y&yY?pod~W%iyy$GNt=2RilHWsC50hH``*7
z{8O}jX<;rY`hDneOOFy_?~J%tZmMLVZ2VpZNHrd0E7kGNsGlFy{<&QD4-#PZQ|iV5
zl}vpgZAaPNP*pMhinR<#eEYLcH_U#!T=yB_!@*9RtW|CN9NC1#uLE?_PCj|v>Tz|U
z$@6O_Tz<G=9kcYZHss{(;E?WA8&~~a&J8pw9rAE>+{gmU&F;$8xPA=<{H=VkQ++hP
zqHS0gXjfP_?mzW-R&KnImAgH^T&%lGigr3?8sShHx$Bq@+iU6Vj|^cVz<{2->^#x0
zz&^DwY~R*-=A_is=4D~%4qsnaJ4Xk%ckf_`4^S_!iH`34paaX&1}E5sbgo&Cs&BNI
zZ)Q?gKqj)O+W_l;>?r5E(r<$MmMcdW4^4#CC*v@C>z97%cNfR4Lt}Tc4Rt0wdlSH}
z|AIr5AnQ*4ZO+PHse)W*U-`-d-7kyK*q6MlzdOEwSq=JLMpjtoILhjgf4`-Jqh@k;
zU#AygJiN2jc-wFGY<<q(ikRS}sZ%?f21{3}n^fv_s&))KH~OVL#zAGAQxxi5uC8US
zIl!4Gy`(Bx2FB05*_H*yn)fm0ZH?D%hQV7)OHVC^{-K+Wb$f9!YTN-ew9n>8r@OZt
zik}QR)#tK1X=~q>1B}~T%ZLFSMe*OO+mh5?{)fLv;YBw8^U6G3^2iFQ^_hv+XC-WW
zEWQbB>$aJ#^b}5SW2$x%-BEc}Sw`fnWif2KCQ-~Wa_OVYnyC%hsboH`VMdT(LF2V-
z)S^hriSVJOL%x!~C7rU$U+JhlyB--`LHUvI{iql#8_pW(F|XNy)wU`Z6?WblaNIy(
zWqj}}=!h2kNM^o75dWNFM=ST`=Ax;On~jHj)v%OvP8&1MxVapwcJTmvV!&#nd`sh)
zX8qVLwNPBSCK}9`DD#7&-t)Phzt;8YPhN{|rH>UDTr({oxxF8LEe44C@!E&M;GSxN
z!JV1^#FbSbxu5^1H&*Sg*Y;iG)Aq&h4P84dL9*`+{l?*2>01K9{YKPGL9xC#{NwVF
zKl|e5L;mc&hlHCC`4`1QeuGc)kl*<K_>ljp7|9nt(YM<5#n*oRw{EOn*c?fB@sQ{%
z-7=DE(H|`oBe@nmys(K5Ui<3ibe6ulIh{|RW;)^O7kLQN`Jsn|olb!)Dx!n(3^2K~
z`|rl&V~tXi<|icoiGB6nKQ~$NDB>gx?j~OGuhhm6_T|eG27&xae#zIxZzImKb58M+
zXNemR5hV@VCrM<;Pn8ERUKp}3UU2M-zlhD#ce<2!V`nem*zy45_J8wf%*`LVydV0y
z_!7}1S0X;bf8i>8c-IQ=f1sQLNodnZzFZp&C;OdbWsw;g8He0-6llndFJ4Q9bN~*u
zp{saix0Ek_m=knsWl9bMd7#!ri8Q|QNcll$YJU>jlQE!WK&H$<x+PJGYic83@S-5J
zgVKdzx|YA_&BnRo*b961E|l)M^O?WZPJG`o$g((%HvpRA4%)HX<0&&Sj5Wr<Cr|9|
zh!!oiG6Tb^Pj=P<grv;WO*Gkj*-WzLC|vtRKf~pjp&Xs!Qy?9onwy?qa<a<edPdel
zB`e?VIcj8;Cmr)C&$whZ?2GonFadL-O59S3B<b=NID3E=LP<MPArdHFCS^&W3fc5g
zB1q6VUFl$DG=gnlua&?rxlF`zbD1wLA_k;e;=3d{-IFADcKjx@)HZ-xR>ydE%uU}9
z5*rNw13vK|cL~QYC|qZSH^SSsYuR05+Zt`JYO?NW+z!hrnOFE9x?#!xwG2eE?d_?h
zQ6>1NwJVvCe*Rh0wU`qR$8+H^)W>@+Qsv#ttMg_&ZARwU07rQ5;%26yAb}*bR{W9*
zZStK~<^4;{uH=dzBmlv$|LYI9nrt8^zMFdA#PhNSZ-nsVu{_d~$CFqe6kkUWlQ&m0
z0k8bM#V4-zY+!i2S*p}{Ufz}F7bOuyPvk=#(6$Cko|VXkeIqJk|Cc6K?lmrce+K{$
z^O*`=%WGRn!cZ$pnXXwpQJ#((#O?`Lek*iHOF<-;jEpEm83-kQJ+X|r#UTItQ<xFa
zh0Isba>2{ZysgO3q7hVXMmWIHgx|6KsFHbQM^~)dkDYZ{kF27O`lAJU$S7p0n=>ii
zJjnQDdyL52WKX_zt-eyRD}gkXOuc0IyE8O`#*;)_w1sK%c4Xzo=kK$`dF4NkPL?(w
z9LghwFL=eLjpT(R(PMXn(Qu=k@+>3HjGOK7O3fH6Pvqt)D@{_&8M$OgAOb@^MjBs5
z#-TmrrOW1icj)c1@WOjn>@+NRfQf<3Fp+i%4&qhH6peXn#%tHga<8PN!C$G_hQ$~O
zP*CyApE@AJGO~u^*Ld#+(1rY<ZLz%-ONMhyjjU}NaQT2`w6zIqy0ukO{EQu;TlQ2s
zm1L<AlTzhg$x_u*Hd0sn0CR14S^;J$Xg&~hYBoI8cHVj8?-^+&v^?2AlVLGm!)W*x
zbCAkN>Js2FUe=In3}&YIc{>rvPH-ioaUnaW7#~D#*Q~Sx`UHw(@wg~A+-kbQBfE2*
zm1^lHK3~pyta<4!VXkBivjOArCg((A@}pok!{eC@(=EurtCGbZI3Bpxb$24ot<*?+
zG$27h8gm-=Y`Y$$?cDowcECWe*qd2#x(pQ{=mt1MuH4gMY52*jcgJh^5lT`05j>%=
z`YoX?-zx);-3_LFm!HW<+Ke2D3c=-<jAXZ}V@WwPj6iwUTlR{VXKs0>zFRfY&@xg_
zsT~72_2#)OZ(mIFof&3qIXBY2o2QiLovZD1UJusOe21PgZhzsAg`qNboXlIU24Aq0
zz*=N?Bg3Eom3}62v>-~4g*QTT4}|gVn0|a|tW(4iw2CU~0^HA6{EsPu;W;w_Yif@>
z7DaAx8X1q&N`|op8}gnBFWfolD@;pRR#vu=S|Zrw_a3z8T|5Mkh#>jW9ZI1i&o$gy
zDkQ0zyVD|=f}D&=$mAaWHm;=Q+rR&Nh!ONl1<1HT+8Gy<;y<I3DRRlJG6XEd;(NaK
ztqhu{z{l|dksyX+43x3OG+fHl**EPVxsvfi{^HD7d#^fe^;mt`t3E02T$Bi8dzCU?
z^0Ors2P%$7{S98J-N<-rxF{~h;IhN{B3={LX9o>@H_WcYsWF_z*~wU)Q(sKA=}lZy
zA<3vWb$-g6NaPDI?#q|bb1C`)B-BZ>q~?cYWknZLuN}WNwTme|DmxWvY1GR?NKd|O
zm`0lsC}vP=%Id}jOa;ryDB6ewi-3+PI;ib1WjN7A@friAG$c_l=OKBXp4$*m7Z(wW
zx&78e_nK<AvS*p`#`sgg>Ak9tDXSeF_}*$<SEJVz+?_6|o*;u5eSm~2fF8<>y@71n
z=Nsab{9g5dHLJC$AQom12>P>UcE&w-Qk{=qS-=10(#?%Dz4^1*!oTQEw7;Z=2cC_u
zU+-J|On3ltd?X$I*Z$wt*VAvL4-e$er~wER=ELQ&n<;5w=k0^`DYZJ5+6R{Ues}6Q
zY@5eEQd-dE(V_7(Dic=CJa7I&9QUw56|>HA!I7hI@GiwKp#w9>0?U2XXHS>|K^A0I
z5OV`WVO?4NVLrZb>*R*IdHOSX()z}&R{onh27l<gxHM{x`q$FzWZ-@z9UattVScw8
z`uUGt&e~3vU#UF<G7&`SuHVdpA$4=iI}?U~cJTjhzm^8tdCmW;FR&0;*?;i^*4sqM
z_?(sAy}SJ~Kg{nBgCMz+s$<bb*k{-E>xCb(J>%!aFE?K<J`&=K%FS8I&Eutf!CXtP
zb7CouOZRW4LAH|cOCYLnsQURUrDe@2Pxfjw|5}~|)A<)(@b$~Nk^~d0Pn$i~{&1(>
zwIR-LU#)z9XRm6k>YY*hc~vv355H<>IK3i2`z$qH+&fXm8NQ}!@l?vj?721tv%WO)
z<eO7=_rJ|f9oRTFedVbQ-KXEa{*7H5k7hh~*T(B7@1*HYo#fxx#!s>|ekphXQ1e`J
z;&ZBWd*js3j|Ja+A^1h`=CNn1hr$&-vF%XbZ+;`Y=B(tWx>u{exRT%gwQm~n_;eoZ
zD)6xJtBO>bJ~CtG(*UyX2*!DRJpexVf7&}AIJc_n&OgZl1chXz2uDm3cuyk}jXhvO
zDNATlG|$3_!Lh;lQ!i~lI1}0cA%$j>ly;NyB%TK`ag1>tO4(f)4-<AmXfdqQCD|m{
zj+4@)i%mXhmQS{=4a+A>+Uz2yBz5{H?Du!?lSVTm&1lS!bw2SO&HHozoOABE=l(h8
zop&EL7L8fY5xv&$Phj(-o9*_E9f#2y`v}7Z<KX$eR}V+dSzYdpz4^u!89u*5)wZnu
zS|Z<nfxq#(W$^>oK0Y!)oj*v;2UjKCBiB~@!f#$X8D1S*SAKlrl&#^ahg0d*+x(pv
z?r<loSA9M^?j=_~b&7){RY68D-mb-;%2-S3PC=O1?elm*TDOm-W|xn_G=n=GoLshz
z-k<Nw<5weEAybC0?P?ANjYEYae%L>e8hGKl$J6hs?XO|i$X`*u{?xJ3iqfI-EhAy#
zvg>Xdcw_v=7jAr;zdO8aK$TmSR1N(V?><l}Ck~ZgSTm8zul2q3ecM--CrTT6-(n(F
zt=7NyDQ9$|BoDSLk&z)WcA`Y*VRZ5xhJgX-WH{Ogk1;dG4VRZepo5jn*lS9TPyG+k
z^IX-?bFTPH?k~M?WN7e~&G&@P2f|gS9?FC9x^*RNQ)^fECrWQ#)0Y_8wfa;%4%dd>
z7&e26l>35w(~j)j*BfJ0dhg{WXY`I;eu)3e&DXysAJF<MO1u*ee=5$EHC*K&VY~!G
zv8k~?v+wj>z)A&bZ}!u0)n;{^F$_ks>Of^;C$_}mhcNOa#!BAC!n*uDe(#Rjy8PSL
z<ND^*_xUSo<jus_^*>v9+)s=Q(>-=qpZc1!rMmLQH;(7lUH4?Q49#By!e!-$;$yWd
zO2u?8QN7|X%e~JQp2>xY`?g<Et3P%-V8T+F9p@8R-ue^g`F_Y+fw>XkbC4RRKa?19
zfjt&cRb}XFi9G9BJwsXx@3E^>V)RIL^;l}-jr};j!l8WsOMXaaNc8^LuX<OORx)y*
z7cR>sRuz)V*O#_b`x2us6gDSDk<lVzavt)4UGAmTd%dwUoP%GDi(T^ZQy&=0l=sq0
z3}qnWrO%>Yg;<*U92!!*b_Qr<84cCmFu3ect~bVp>BO?pHY4+8*IicXo50$K-EGq?
zo4*Lw_g{DU00Nwevv2fu+c7C_3CoABd!|H7ebm3(KU8>p<coe{-E|l3b=G0?O!j=3
zaT~Vuyfm_JD6#5=QUU&6R<6Ier+BYlOfJLZnx~Fep5M<Zf;kz{ym0`T>`R3Gc?lgm
ze*4AsBufDM6Ft0~R=}t^!RAqpSI!3bwcWHK98ZlNS&i>s`K6Ikac_88$+_{=F(^!2
z`TTpGOD`DlvhN7rT=1QD6>^upG_o4HZz@xABynIEH?_5V0rn>&CFk;T;*s~C5c1%=
zA0==@&JT+_@?k|LDb`2%8&56z@#2##ka)TPwHcf_=<*J$D5mGWOgy9;Nx^fj#qDcw
zu<!H@<?9jJyTj}OKY3orOGjnx(_Urff7b<t;syJ>-Qo3#^TJhl%O!jHcB!8Zy&zV-
z`JIW8T0T+1OMvcr&Z<HWlTrdqnpmj5CL2ixW&}nYG7P~Tt!QZP1H)QJ6z@@dWb>+R
zAp>4!j`=qXzIi0Rdoxo`V$I`BEqgH1Xfn!9<b!N3v9k(;lLDjyXEM9{K{E5iig?#n
zuE;<&!^$;itz5eXBP-XgL1X2@^Q^6@?3Dodv9)r^K-JFPwg{A9)tYJL!f8S#6ZZ6x
zve!Adv1Xc8AX(trm|Vf0Q8ASXkBZDqpIy?--MsLcSDh~^DnB#%A5Rai&xgCqn|wBB
zaVnK?87D37^LfXw(7AYyN}0S|G0+6Gh()IZPBHG#7lYW=Qq6aYg=9~<`eC-uV69R1
zsu)1ZsHrU0GjRvM-Ak){|IF{%zMlE(@_c?fJLIPB{LC+;eNZk-;xQuB=n0@I#@$5T
zEyWo;!9@fYx)MU!K6<LLs#5}kn?+kG#!JrDGD(+Xu`%kk6O`knzQL-O80?Q#vm4hy
z>j!=b2zN;Tb}E~Ufe4aOs<1)cOa~=+XqVsuj|@^-D(VExa;doQ=3}J_DSm%U>S$j+
zSwcnkg2ZNa2lpH_6esPco${($Vok!wjr7pfrve<67;GVM*d_%gQX^9f?hQg{F&C<t
zcuincy9ehZH-={9$8%oZrO0|im!oY@$TEQEmGi`ZJu#9Bm1+hz(Y)lsVo^*ZUOpiO
zXBc(>*T_|_Kkg3lj3Ju_Hv7V3zYxQx$Yy{6j)_vVG`T6rFwlg)R1ViTUXtq>_Y3_o
z58C>@>S|KA=Eerk_awBc-<xk&_F{QM)!US=d5l-5IQbx>hGqtI{Jc>JJp<P3sXm>H
z^R$?P%gBLsgym;{hPTL_JnB*3_H-{o=&$g2jp;3!ypL}WjthJRptP~y^#*xMxaKBn
zm*>$FYcIX@7sA|Aj$>;n>r%~Y0?4QxGjoiO#>7n*lf041EhUv>X<T;VF)HDa1up6S
zOrDRz8V5^?<JJl<RsNI|d|WD_hhYzChHHSO6PR}8v4?36Y<H@h(V>Y^wXdwQD*<{P
zgF3wl?o>l^AP}UwF&C7zRgmL8y%aNz4M5QaG}GQNjZpNt1g;zRRlU4ZQmjcrWCW=v
zUnzuXa^ZHNG=-XrV;45?yWc4>&BNVz8Jj?m*+z4?`GmKOo{Uc1lO{sJ;5ApwZ-|vI
z(Gt~w9f}oMBD!I2A4dEk(VeZOJvZj!Tt@r5UM(pFw(4AR`AK1wo>zfisBYSL&SB?#
z*)=q6Hf#bAPanW2p=#*liKRtj`yeMvliaqPlk?6?_f#``b2*2t>CfeL@OV1NC%uB#
z=cRL*VQ-*tg10eMFI=%P#B*xdUcX447)7M;JJ`#N5{%l5D$GK{-~gYhWLk+@<_QVk
zN2B%~xa)>|%O+i3k8<n}ug*;jQg=Av`C|j+s+*{~l|phXKek<JJ-7AocZ1iuvEfxb
z95T$PiD++gMH?El4n!Flu}ntcElM)W5JOlNclXf~Ty$QUD%kw~$>1}7|3H7THaYNY
zzH%>v#87OghU(gXS~hs$Ai@HNFd`&W98j}+Z4@14Q8sbfjR)0O77B&fJtdd*arB7?
zIpE+N^*cX0jaI?Dl0?svH=s&c9J-=is0GbNX=-5pfs#P#;r8k{TZ09Iaa@RUt8;#Q
zX?%I+F>D{QRvMP{hWY1miC?L1aCp@%magAEETC>81QLcpU2;JDmD^Hi?(L1*j%U00
zlo|VEK1~OCOU|S7Ud{NCb_SLVROnD{jM-`+7juGTg_!J9XZ6Wb&`lul?uY%P4-(8D
zVVLNXtr3fnX$vEk;)!Y{gr?qQ1WA`0IRz&a<7w`K#AsqPGhQAW@-9w{2YY?_k*9fE
zgejpKdga4k_?*m7KC%a+qE2OnO;zAWTpm^$cIr$Q!^*KS--Gs%FIE#EWn~F%GBpAP
zIG&fsHN-3DY92;ir^bXb;`_OK{Bn&48`u2!wR>+1ugwo^r;k7B-?81NBdp$wo|*Z&
zFO`~Zey!{*yZr;X#5sO>Ai-`;=FjsO1^DrpLz_GC&z?*?Bgo|u`MxldE3tnG7ibGk
zUt;O-vi0RYFaNpph3U1qu{@t){;pTOwEC@F_<Zhp@B7Oq_N?rm*l_QI*RR;{LiMrH
z9bZ{nt={lxZesnwr?1$Od-BZ#y$^>gHuZ;_`>)U5`o@#Wkn-X3`Q-;P_YAEb&gcDe
z{MEg;_{qKm)|GwOeEP!=`|-XKNdu68_1gp}H<oZXjy+t|)8n-PFEzzv8?r*7vW&Hf
zrF+v@1h2}iO%Jg_YI@mlZm7bG-IZ(E6L8tUbNLsR?+CZu(Eq(<4`sjZ)h4r}6MNQf
z`}TNx#j?WJ9~e1v@4efrE3zx|*A@0+mb>JOr`0y+6F5*|e$mldjyBY^Mu*_0ImoQm
z8Pb|R_3-GIpOw*=nyl3a(+@8-SRX4-rlc$pUggNRIbtL7Duu~(df?#!?HtN-v|%Co
zaaA^>LiX@?cHlZx{3qY<yQ;SNQS1^Jihh51efkccxD};57EeAAT0%2fSxO=>ekK3#
zb`0w2;3^zByxg)13b)DSdFO?@!=j%~Cnubp{=}t$hdzG#`NJzSAzHUFJJEf54{yhR
z;+%cGdmw&=|A}0F^`zgs3Tx5D59YS|D}FV1`VXqrWtHK=%H<DVc4m6-Lyx1$Jyl&X
zT)3>@{r2;{d#f0CF38@u?WwPOV|R@fp5C{Fv3wKc;;V)O4>p%`&}%o98Ka6-<Pgsi
z-o%s2i@OQEM;aKzhUjLwsAW{%D@y;~YSm$7reAyP!H3rbd`rkR1V^Mnwue5uSe<x%
zZsfUh3t{!~+(pB^ULp5DYGBuJ)yKOfJ9-OmTV~TJ#`m6lXjjtli<2d<_#JGcGO`RM
zCNRPPn<oroB@9(?k_c#E2QkQjJP~MU<EkfqWsXfKD2A?E^i`j9bs{Ctm=z^H^7Jg_
zmp|w2D6P1*chFci^4`_AKUbJ6t-!=H@MZtO)M#z_cxvrloPd_1^;7111GRkRg@J7R
zUN8B?N0MV06R@U~WV1p@kp*mgA&ACHOh{!1MA%HK2}U{=EpQ6z#6)xDIRl|#D?mi{
z>TNh{d8u)|BYKWs0JG;`9Fxs(B8L!tqyTr~?h6GGR-McRczR*-7(;_xQOe#sxw$-6
z8HwFF5l2PETVxw1w8<4E9s(WleecRi89P7@H{3)qPFvEX>3ESpk25LaAavy!kZEff
ze8R+T*e&8@1%xUrCzYpjyLi2kCXjE>t{m7x{|9^b4xKQPo4gi_P%w_PApzy$uwirm
zkLer}sj*u95iRXE^;YT3SLd*pt;FcKsVvk~K-|JGQl#IC8dm#;sOU@{+VBvpFcvDz
zC*oHel4L(i=lzRU?e&Kc$j63HbSM1mmg;C8GtP4%rm<6c_xL{MjNf8Jpg>Q&=A8A+
z5~e3$Z=-&UCPnH*EyWueZ^$Bo8Elp&IR}>&DyX9wW!j-6#wN&KO}9X<##86{<=yF_
z?P|hj^Oy&h4(Hi5FFy2O-)OQgR(opvh7+r!)$!DmUcpUlEPOo~NQ|nZ$^CzLLWl(P
zXgYU_4_r$dSvx}>*O=YD6RymoxdkzLUWL{otr#zU(@%mH^$r6DLtJ_yPrQ=o>~(*H
zuV>_P&s8e<Dr0xHIDU4n_O`GZTYllN`*`leLxssF3%kR<M6K+ETQI&>oF_7;gsgGE
zQuHfSc&qOqB5PRpu<9|Z`3nj#0UXY5GCKNaDX@{)vNAha-lBr?T=5jV@c5RL8_#D}
zc<1AU?essGb_c@Pnp)1oxEAikS^NI?oFwxL=4NB6-@R(cPij=}R}@}X#<EhBNroj(
zOoMra&MZV+pEIJ7o>ffqNx-rl%tko|AY;C{QP!()@JVzSGrsTk{qt*E1~JfJ-Zuu9
zd^MLo=W9NDJjZv}mZ95JGq-*#`LkntY5F?-G;J^ICQqx<>Zq&|i7rFn#e!H+^*m%M
zF#m`cf@4Ew|Bs1Vq`+otK{90PABlzyNYuQ6S3823o6DVD$uDuy77LhQc(3I{Xur;e
zLN?o%a4TM=QcIliQtnIihDsUhWjS7nFtB8uLQyoeIS(bU5!7u>01H|XeJCe3us-In
z!C4yb8LtGaG7|nx|Jgcl+3faca<xRb4QMuwf~@r2crKmeBdjc$d4VIS<d)#`U5Xb_
z++yxB@ErVe4%MI*4;t-eNN9mO?Q+oJubALnJpSZ|!AQU#X9c48TtqC>lUV)I``%O>
z{Pn?9;RAzTiT&Y{{MzifVefM(CfawrrBK=8-%%((UH$e*Cb6bJ^-Ox-!zlW1NS(X+
zGo|Dodj5E(mfn8m*|(Rj%=Dhmczs7$PHkJg=9${wUFqGg+qA3jZ1s!P(nYB?wF|PJ
zNdMw+E<ZGwzy7YmXTvKq`D}G%<yRigY~JRFTepWxH>_V%c<#1|!Ja*}b(Ko)o2&Mv
zS3g(Dj~7Os{mn{d-={CmS6&(^e4~)ryen6ltghh=>t8R2zf$PECp)@lqFi`n{I$hG
z>b*nfl$|$Za|73fYfjD#<Pz($dkRkf1!3lnZR?#i+2qR9z6oCBOPw2%@eI!&o}JI<
z334TEGxj{|A4!+f*%WTX*;x>=GXHV*K>GQ?<nD`l)6e?PR1;fM#o_SW?S;(Q!u^#7
zZUggmkEZv1+6kA&gnak6ZCfnH@z&FE+H(9kx^$pP*$S+5)3U`X)0YkS4SMmMTOF^G
zEACV=<~jB69EnnAp9HOK5M(6YWyEk0=+?0F5t-6DP?<M5nXWin>imdY+})g917_f%
ziRb7oh2=@Qp~$RZ`@6|>JIaC8Hvs5T$bBPty6~Cz6{-IqMm8>E{V_j?<;uJu+7mB0
zY~CM(6MB;~XcS*}&B@AYh-yYE#s&i#hlO}^K#UT~ZcLUW8_Y$c$F5u^Mktsv2C}&|
zu*?;QvX(JwEU0Y6VQ*kZ!T7jyUX>`7Hr3$Fvyf&cbK#q!Q*qw3djlK4syu`-rkQL7
z89V{nBzotsO@ldA`6-Gc#b3I++sJI*TyjrfW=6bZ=&E7{EeJ)<;CcD_6KJ+3<t9!C
z96p-YMh?uKu#%v(GLq@2iRBQ6fwq~u82j5>nm5xg(3X7$)dW8-SXJu+Gl4I9d7lvD
z5r8?PmTkCYs5*WDD<8T*AzR1=6$W644&s)4=hpY1NM_2)7GeUWVWpgF;E9eA8w_|T
zF{TPbk!dJbUU5OJKppgTYXn(oIXC9U?WI$HTn1qXR6<Lj21Es{`@zGRBv9&#Xp59W
zG=sAt$a^tn6PE`f5@q&xFjy$@$Uip?riP&r{Gy&~wh69y1CX#1(<_IB081kC6R#^x
zh5FOKD8ifoJ{W4C$DGZ<wFR5mTj~Y<t}1S&+n#dGjK6z6LIPO9v|#NO_10h(7(<jV
znc*_P<`UP1VF-3B_yFM*41ifTpSwN5D+z)O_-fG7Q!@u`yuk`R;IqN-8bsV#{4^wS
zV2c>X+qCo*H&!S}3}xx(#Z1S!2pqYBfl*JJ8c0k;tM77l5FJUMpdgL|VP1k4C<XpW
zkYr_2%er|CtSVw!+0BQQO^Ix|H$Og@&aN*Ejbp>3bK%>Zbw5+cUUdFNy*Xa(u;Y30
zaQUAhK~`B+00G6c>Wd=;JoEqwx_n+(Wo4n;lSg$6=ngK00*tD$p~?wt0r3DkhqD=K
zwOXy*_JGH`!lPcL>h;Cx6mHcpwZ82(svhJM%^z)q<}8F9aJZVDK!mtyax{-Z=~eWP
zg~lFY>0CDGTax32^(qwLp-%f1a^}%d&*2-t>x38(*mcr(Qp3D(fJ56>IF?wITpRL4
z>kw5z*G!W>lt|t1d?t+Z;9q%y2~0UWY0i7Rxn1D%EeRfvr-oNo;=E8JUmx<F7Y^;)
z$NN9SpYS$@Iog=78jt5vhf=YzT6)0CKgMH&^TI>g^RZG)I_}{M_E1~2Y&D(g3!{A}
z;N(u=Lcl*fm%&4fPwe)~(u~O(VtK$i6DE|ER2SZlR4Xb^=g4IXxa6De8^j%LhhJa)
z1V?HVgb0(|Ah=^3(3vQy_(D8HGlG-Aqa>J36oiq9s;RU<pw7#MMEhCkwGF~p${A&T
zDd?RlE5pvpOHX!_N;AZ(AVdP42wGOdGFS~9L0>&yD#k^JiSd;e;v5*>%Y4fzs6e(s
zr0Q{z<Bm{_J@o-j@WBN(l!|yaw2Y*jv$`tzL|Vuq)Q9jc0u@(*@>3;KUr^I$cBINT
zoaiRl{HNet{6NmZU;uDx*9bQ~_*zxOa#1`N6vGx137hg3wLt*-mdTU)P(t~D&uRR1
z7WP;wfKkLXS+^b}a0Mn%6CvRwE{T_UYo#!_$*>VCi{h1=+L)#iBGwRMMfrx2IK3%|
zkNqOerB>2N*1%MM^MgfD2Qi**RNx63bYR};afrtE0haDYaW)CO(2T@8vQ=nZ<?Bry
zBm<KG8-|1c@p%;w?^(EIVC~G2dpA9RG9dire-tLUlc=C8WgUn_DY`$T@<c}#hOaUC
zS-JvVS!zV%!GUJulRfBTjhJEBs$pHoGa-V;0=oITuNg6vL*E-G@~{g$v^}O2k<K-B
zjglfW%kB_LidZ88{0ia24oWqW_W4<2-&-jU@d|Aq8X2Y2TZfk$oNn9@U;lS^z3LkU
z&A&ZQ7rPDplz_;l&KpiG8wLF!{EkbrEhM-w+b+}!2rMGN+e$ISID%3C>c2Wu3q61r
z8!1gBYOZd>i$_kVDX#=of~SB~fK~HNbWKdO4zw{yvT{`Nu^{vk3`$TpmUdbBWiQH3
zGTot*v-Ja$e9z&pe^Yr4f?_fcSbIx{Fc$_F*MaHmLTl4qsTl0;tNR>LEQvkd*D*^z
zgZ|drjPHtla!9WsV~u|U)ob7YEb9@XUBePC2reWm8>>qCKT~qRs~8#s{FKR8Kj&Oh
zs{A)YU<&4&_rNvWA;MNeDHtSOx};XVtZQOg?*++5k@{yoVlEpzZp53j3wZf<G?<`B
z3)ifC153XPiBjCe3<fQ9%`f~<-OUP3IvKoK<*68z6%ya%O*=lfZ~-@mxGUwb3Z<$r
zfQ4b*$O#OGB`7MI!YTz3mMHQSbxj7CPBiUAaAPzOXoghcNiClN8aFzzk_8vYEAKze
zx3``>0mcAp+!+!Kp`t}Z8#9&3G^7!Hilroj8W)cG1;5%X-g03%=nN_<NaUL-jP6`h
zjb?yYf?=(RtDpW>is;1#8{8HWo8^#C)*>w_R!|#7YVom3bZtmJc=nPRxuew9Qy_3@
zdYj`L>Y4nI-!wdBF-#Ith4voglFdQ~e`|@W$!U%N!}+xa*d~oc1ZUMQ_=B@lW$Cn>
zrCCtp-8ICaUig>RGL38KY5pL{bX#;px)c<uA6vG&phyIjDgUy902of(ej$@<1KiXZ
z5RuTEoXX*wTKk4?fXzya$qtPV7J%;D<Mt<=(K!3<OlE7ery3?m);DaK0@?XWMC!j8
zEQeflS8)V7-CUeR7gI_7?zdByX3nV#Q)}PqZGvWMU?Fo!*KIN?V5n3VOco%M*YgT)
zE(tDpo&>`;_RngeDJ14ff@UdX-NCgmsr|I><X&qJ8gw+yCKsX_;jTIEk+)scmeDj6
zH2V>EUE6|)h}zO<`vJ{^)*nt}*j|IRVWMoT6Qi+eH3#tYwr$mj-}JryFA3qy&=3-_
zz_Hwe7BiZYRXlREsT2B1!R&ZvszVh5^|>Hd74ubvmH!Po+DVJyJ-x(&_vtcdYe7f_
zHpsz71`N5EP%Fw$46dgp6HAB2Grebzym?urf&yJ*cj(c|^4juRVNyFqKQ=j@3#yZa
zT9v;V{h{_^IaURdh@BST4>}VEsii(iphq(Vw^2aBj@;^~rs5KZn!a#kJf9twP88%S
zx8cK7y=Oc<TItXILasm<ttRm@6VkK3cR~%aX9bWpe~}1~&HRuqn}(24U2mpF$kbUW
zpn<Z{qj{=d8|C3;u3AX)nkv6_-#ukxh=egB^muv(CVh_=5|gYt^$qK>($!WUTrPbu
zQuhK}$M=QOIVviQoS<>^?C>)MmiNzl9vUJ0&#sy*t=;FicNY$Y`SHFin_*;~<&RY+
zYh;^T?vIC){Ry58o-d_vyjJa*tZm_~w$Z}jt8bs)JtKCo03R!9#ZOB+x+KD^^>vLX
zxbR_uS&z6hSzN7y3+f-s<D-+K!FcVVB)fU!vbBe>ebzw5uUh}LyU}B&j66-&)AUx!
zln9u9Vss6M9wAkRNPODCJQT_>I)ttqPT)y~f;J}D%adcZhYGRka(1^UfN8Xr+*wK1
zzxljVHHDja?1gG$+EL1_bRgGMRy7P&UxSr5Poxs2v#PaJO5cI0U>q&fVxu)Ac#_?3
zYY)Y#o<<tC9J}e^Q;eE710A<u1gK3k=#&L~j4{ZrFlbzo((BwX-q%~1I9tom-pUR(
z++_!zNmRrd*s3s7dkBvv-CEL}tkw6?M6-L1QR*XQ)z)9Cz0ukr#86}89^@o1ukJ{V
z<<xW+FBvTWcGMXy#DmG@jwUDuO*i@06Rct=s#^l3)lsO1iG)E3E?lD|S|wZvU?N+G
zOq4E;m;L2&7apn#wXsxHJ7;*4<J60WYu1YvJ@my>Ls81WYt+0}Jx*(i7UfFnA4v7j
zq}9~#j5dbRi+G&lsNP5=UR!=j@c8(NNGL^W4(`uRwSL`2#Uyzc44XP&3&82<F^jMO
zU^U`T#k*2V%fLwU?ICyEEAH@eOlZ{=es49Fv&tt-EhG<q>Qw25?dv41u(eW<Zyt*?
zA%`*7=*Munsb=D{1}sLn<uOJVHkb`23l9GNoN}t0*?-olZ#nb0&e*b7Zd;wvNN%?W
ziOIC!R_XqYP!IPtE?@bXXJ$16rP6@ayoe&SLRD}RbU)WprkRCK<Hma9?3Ea>$88MZ
z@M_+8nwcr0zPh#Y;>Wm_;CBozOKx>%Gws`4fh`{ZIL=G=ph;rxjDlMz9QnQX+Z%d>
z)SxyPh_pnLs8yAMd7|Um&zc7qK+M`iTZKe<>t}z}<m=+l0NIi?BDxv#1b(nlh!on!
z?ToW)Y8z3@N%zs6U_zy3dVSfSHcM8TSM4sEH7C(DlF1~R1zSxgz)rpVITiy>1glMz
zOfiexUYb0DF*5~tEQMo_Jjxtw0xi=@MHFjK7C^`3MqW2|>w6o|2ODwoojU=A@cJ_t
z;*w_ko)3ymH?TTXmK-ntL8Gn$+jVHAkcO>Pa5|=N);aW{*D?hXj8M0QXPXFKPlbTu
zQ#9K7#d1Df-}Xn1d>uL<@GP(vkd{6Z(S&R9;%G)UZPV8pSU9%;YTjj|;!SW|1ZIf%
zn~I8ZU`va+SqN2vBJk5uMAAvG7N~>6rvS@9)$JUi31zB1AgdW{Y(0H%Gp2K^G_%aQ
zFc7I~gsi^(A8ZTH%GerVxfStD2@SeLQv}I&uKG7HY1lAdm7BFh8#8*P8Kmt1XpaJE
zG2L{wu^Xvj^s-93z!p3FNNJQYMR^KHTjMVWHVj7`^-@tFha*o16?pk<%m=o=Xls)W
z!Bmq8rip_HD>9}4ckm}IgPeW(UH{Gpf(TeAs1T%IOq6D2))IA4+VWG%v<P!c#+@IE
z7x_eo8~Y?5Z2VNg-&1gkdOpUJFD>EBgD=?HqG^q#t~g_NsOK%8NEMTM;=()Oc)+5G
zotgG`razr(DXUgZ<yaL?1KK;7#13-!Umq~veBPvSy3;r#Jmw$G#iCO6dSl?!#f$(p
zCAwa${-e!Pz&kNcrK3ki!eMTrdnGjkU}2ymurL2B)(R-zlq~Yjd!?CW)<rjP0a?)y
zhiF~$2Pg8vw|;P<16b8Ls`pgoxr+FslRoRMgR;31>qHvVq@DWt%PpB<$7PEF)nG+b
zC)Gp{)y}a%i8_EtPms*Xz|T7Mr#{}`xoOj={Cp>oOi(}O-_orJ!$G$3t6w%E5#7Ys
zH?FEVxV>izNM@@#W5$koRgWOX{G$;fh)E&JHk@R^AEGA4>VNjQhH5@#fM%k%v*-n_
ziqVw5(tI2S$Z0B1+Ay{?Hi+?Y4Ys~cB0M)AIc0=R!ID9WW4R*N#D$}1sA*HwNPD7h
zFNNaz?}o><mHD)l`6jBs45yMnJ2SUTO*XRiSpQgCvvX?}uk~im>-sGhn6bXoU`XL;
zH6Sn&GlDCfq&cVJE5a>76Nt%jR+cTo5w%VM@|bNbFtVu|5;P@E0kyH<RyK0%{ILAx
zWNn)}v^bhI$h8HGh80~ZQ+>~Ut&sF|X-04d%`Aw6h^>}4rHjqTX=||Y$r;ge-MX##
zxQWz~sUioz!dNgBG*`?Be0-B2=9|JBJ!aS@1C=tx&%k24_20DUy(%2V>(U0602Fh~
z<fHY58mf_|vq`iO2Gs{IZB6CcvSLQ0xiv*+B)5`Frk9r@ICBT~y%#~IpnzF`GvE+!
zu+{y?=Y}>1xw8t^?=!D9&x)Ul5YA~845smJDkE3*kA%~nuuV&B-n0Uk2HEClMrG>%
z{(H?r9WKb+3QkLa)-Wxte(=MsY29B(6io+x*7w`kj@!d@XL77r#YX=6_NN+`-JPvK
zcgXuh^`s6d9inH^(~@uhZ=6_dxovYPCP%!PRnwW-GiUXkHZ!iP`v@{)Cu74Dn)(kP
znQtC~G!_j8i7AIN6V<oTt}XzBW*cRm_?!9ICjgP8SyJR(*tr_Fzs*cXoimsYW?5)f
zYd~*+i-vxqbXZ&hlREhM*A}scPgg0X9^T-S-9}-!EyhGcifh%3JX*#Hos<l$|1GM^
zqrW1r`L065$myL$C8PBzR|nqIHMFTJcS3&6UqwcdP8nL_Em3p8%-nq4v<a%E?5xY_
zV4`;8#1goru7`eUzPe8FC1PEKsRbh9JC*C^Gp8P}&mzi1OyzB#E`_6+^5PGdX!!wa
zW<B08L+iZyfHn7sc4bX(WpA@7N4NT(Rmf?#fYQ?`fhH->s1>dB!S`nDs>DcF(9M&P
zIpDOdedd~x*B*aIZfaBUHv1Db-jQoc(;OGmrMpeW%)w`y_R==V3yU&u$5CVs9e`A1
zNuja6jt1Sv*sI}Hfm{K@=@YLv^Md5LbBI)ch9(dpptudw=I#Bxyd$yjV2Nre2fh5x
z`hEjROVYwFryzg!o`sd1E4O{+YOWmfrgcl0MhZfc-MWdIK$kN^eZ#z3=gcCV@8_;&
zLk_2E(isvdJJ&3<F&jeL2JD|-*Cz5Pqvo#V!hq687gk`d+{X!<i#zSoj&Y9BQx;`K
zGQ&7{)<@=B-M8aa`?#Mg0j^jc6dJ6^H!c=-{=Yw(%0F$Ko{BbOq)F>Is5MH~KfbL|
zu1Q!UV!`M1%KKa9_BOaZKrV#13nnQL%}H&kK^beJX;f+Egr#^P<$Uv`7D$>(c<-Mp
zLrV)_yQ)V=21XOE(p&XgQ%nXnvubb;pLG{kdO#Iz$Tbrv?^3z;*}Zf}z(PnAtogBV
zuOxk+Qo%j^x1Z+()QZ&)Ozg}9a4Df!-s=P|2V46l4aN@vVk5Ns|HN7kEKikvb}*1k
z-Nc_Jq(GS?rbH(q>X~nG<h!;U8&fowGXfx+aN6e!8a9dh|8_p@tN}ZS8HW{B0@_;O
zn@gfGRcg6-|Ampoq!WE^gxmGtWy91#&1o#k8#@K&gvL*jVe4PN=pIMvlX=+Eplars
zf|hNf(*yu$bxYd=nq&?JdV{&e*d-62Dt_``=_LJ4XptF(?9o+V7TXq;V<nH9Czij)
z327$rz{qMNL+jZH3lT<2TjkVdYO>gLk04gx@C6bCvGbDNa0+6ZWuYi)7m^TOs%}IW
zZbx|zZa5i>J|M#ifIEX$s|R$$251;cjQ&L*Cv(ufBK50(^n6>BiapIf0?Slhh1^Di
znQTzoK%_b;1INQ(_!}5ND^)^Ts*`}JfC1ME(nKo31f|eTT|LH+WnO;y1Ot|&PQDfq
zs8%Sg*Ge{3NBD@x(dYbl4`1lfzf%c2i2$BudTLD}hzU%;2y~YPR<yaB+yV3zYFC>|
zLT!a!Ln(wA4rhyp-*damhj}U$b|(ybvf5a-U7)C-r}fmxz_yvptvq&s4I@B`bdZ%3
z5KT06;Iu%;T>E<gl@afwUpqYNw#b2fl-6`gfH$Vg*&}qf++}&VY_fBF-QlPIgxxV~
zZmJe@@JhIAh64e@2^(6y5}Yg8(Zj(d0p9|($5_g^9UL;Q-A-Dmn0H{m1`$4d<n2ur
zoZk0()?s1ic6L3g#LmkW`IcU+{uW+TrFPoYo(J-qIyrO5T%{-A08X0=@Y*;~z(Z^M
zQo4QWEbA4|=9K`Fw||m{<=G^H(SBqWSIKGsyAloEDCoJqAlcy%Q08GjtfNnokQQ1!
z&VKssJkvnvcoy&Q6?j{?&Cxu>C*C|-Q#v3m7BNz20I1d!bb}zB&g{&`9peF^0kfh~
zZGs)wY(aHmibv3CV?{$MC*!ohjio&1tozPM2DTZ8JHfUD1prZ%BiJAit#lN%Ltr=q
zDv}Lu(No{|%kn0GFGO}4I0V*d)L54aL>i=mqM8VW35M=#ww<Jbh)kQ3bDJL1dOw!&
zg{)bCG<5}I>kD|yNv8mJrgsTv90Xik2pnf)MSbU*-#;ycaEex%<=T291QomjBEJJT
zz+1QlXr1A1kj3%|?|5CF0dP;~#)QRj?%zdKK(jfOM3Z5A>^Yn*TI(Wk7KvUohDLl6
z3~s)W&Z|{fOsq%&-INMKT)KGpcUE?GSD4)OQ+f?{QC`S>=Ns%E=m0x6YrhhhKl_M2
zV7P1WeYbs*UFGMf&O3i?VEMCqj%;b;T)qCIaCGiq7BkbHHIu(FXGTStRm@fK@OR5D
z(lkey*(cgQM5A#{IQYva;{}DRXtOa51q$kpt%1)&2cDfnY&kM8vzgAMLC4bS3Z&)(
zcIAd#YQ-;g@CGyo31!CsNX>vYU8oIuppg*4G##eFk#zm=ZGgo8Z*H0c=0Uc>RyVak
zHH#tD?AFjA+2X|G!c3I(Ax4OIEVZ$n*H5lyfT;!&jru1_@sMxsrd$y2|GfMJjL%ks
z!^+(fZ1o|_SZS?mp`&eoOvOQE02|I|(hw)y!#}x)6I5z-s+_X}vpuv><L1hitE~oX
z#98hE=E7)C4F(AJ(bp}}+KHLA($a3)psXd(`joSffB}6vx`qp6vk8jO;)Wv;^?`55
zXOlIDzCYNBy8=U?LebT<rZ;Ii08dQVzeio6L+zE%Qij@KZ>ArK6``Dr8-%UH!Tqxy
zn-yo)y%mft)fzMH`jY=+bf}qqa#|i!6=Ir0fW$$R>0iNZl8<OS@$pmU830^3PJ61f
zZCn5ul?gZ!aU|1YNvL|0MN1t{j&tAJJ2i?))<HS-@0t?!s0b^PK?TGu9m6?z|4Gdm
zy3z#F=E77oP-#&V5o9j8f#OCuaO?D@Xv8<qT8{>rEiE8GAg3)b$*8zye#G+co{9u$
zPH!kvL%^znqRF!>_(rGU){GtzXp`%b{@19_Q}H<kRP9cF)9IUpX$911f0z?3TSWc3
z$Ck7m&|9ixFC*b;jva8-f^TIg_5aw&{NuAAHfe(k3ZmIu=*XaN@e%9X`jb<%Zq?Y-
zIhYwmQw5@qunL-Fmgdqe+;HJAk|lk{2$;G=0Cbsx>L0pZM1w<vUwb?Ps#ZedF_7S>
zXv8w1Tg^Dq%hVqT0F|PoW~5dcH{r}bZjqj()i<GHj<XJ|A?0!_-DgKim0&F?=UT-f
zGgCjC){JNX`rTy`k2F53EgssP-6?wCf>*bIS5TAGQKTlFi6(T&>Pb7<{dE#;Mak5G
z<!Q<rPO%VOicdI>-D%#kEyU2W(xJHh;y?X@TFH9nqA9fvFded?-vnCQ=q((8Zn_#v
zbE_1ImvSxE;vIHpom)q&BCx4!{C_)PP(`K?P+08O$@mKx?LuN=?pU~6W>W@9t{1jA
zRp~Jul{`STKzFPTLv7TfrPygA(~UGhb442Uf<5(z_R{W~Af5OQfikA{)Y^n8y+T@E
z!y^L%)DJnSW*ppD{e3@>f-F~bb2g=C9wO<o`WuN;&~>d;I4+s8Y2rOu47NvpTlNac
zEf^vho(Vp>C%+&F7Qv{#05WWss5KzMc2g&tR{z!SsozQ6*@P=J80K~877JX|rE!2a
zHJP#0nWkN(Wus-VQWBhWFZu_F4lzw}TK8oX8a|hqRbzl|JuNaXIyV+bwT@sSJ?-@@
zqnxQK^)voxBXGrvCLJA%i0Ni&sezikia@2Um9nT)ByFq^OM7FHx=5nc(3|X3u)nrM
z-W`{lZ>;~Bz8uy08|$yyzQd?BKfO;_wckcL`r3Qp)62})r`BH`ePjL8`FH%4+rj)r
z`<M`o+tEp5L))NcvcLL~XWHgCsz@GS*6g|)!I5OP4Pd6DyL2n{FlHE|ALyQCeq-4s
zIUxcfWxY!~AOB<etSqA}87pnU5@~ANs57way{0!ib&&-$+y+|aF~<h61J}>z4D4!s
z05K{CNt}V9U`_^wxs48w44()KWLm?7YlAkwn;n2B80I9%!oyr^VVmqQig<`*J>dNP
zBeOwFi(%#=H^D+|Niz{Ptr6=!%J+vbr$T1fATt`O8(ADEf=Ra0b{$5N>dU`&4bi0=
zk;|DF#4f%6eavmikkyA4A`RGNofcZy)+878IGXM()BxBTMil+`S5Ta$pF?420ZCpJ
zo*f#}wf~)wJ>1L%v-8b}nIchjpF$)$kx(5DeZf4%R(&;S&K0K0w~*Ny$@R@%7tYMK
zjs|^%Pcd2$ifvr012EW<=*FD-%m0GiR0=FaR^}p*G?9aCgFlVdvRxpI#+Yxa?5g`3
z3q4tt=*E`D4*oSSPt4Ik(@;`A3X(E&$02COl6Z~BtQS24?IcG|LjtWhHW(`MO^{GF
zV6wOv_zhF@&d{P_5!<vHh9*|yQG5hz>K2$k+!rNwRdqAO35*umT1{y<VT4i_=iUr6
z;;B<VbGZab9f{){GG*)9tg+f#1A&oC(~hPCflycv<)Rlw=Y&adanhWk$~8_+JSL)e
z_}y=43VfxJr|sE{bkj>KA4Ku90;l^IE3c_)=+uKnG|$d0)fn6*?v|-iQmC*-bpX+H
zl3akBL6yOt66tK_*0*cG4|(|0I0|i>phnivtKO{uRDNQuK|zBdxt=Bxkpfa0^X4xt
z(Tk2|_@C?LOaXD}LF%2R!5Y&st)?-GL-Q9s2-(WhfNZ+w@PGK2hE+H93{Q}F6!ghL
zICG;QL*uNMQ;n~=hVfKx=?;(Gv)NsUm8%pdR<crz%=in;rIjV_v*=ALuHu7RB)hTm
z&fxh{Z!Ep;M@uA#=E;j*Tr_-XcToMPMzl`1tsYdgE_XR<=`5D%41W<cTCO)%zh8sA
z9hy3~d(;|g6%{k)L_Kb3C@km}T8<N6VU;V?O!7CJ=0dDdSPb#P(<VTV4F)QefaMxW
zEgZ8H7kbk;=3$bP&eVVNQz|2IG7r`)fHp@fMI0ru5DYTICTWF6F?MbD7c!S9a^3nS
zS;^+ov!?JEHARY*sx0DQ3VaZcBR$lWDiPsy?)<kWipPfRDIl}1EYTKrOt6eTWSDD+
zr|+4Th*(Yk?Zdj`IGd?JrT|aoR!7XsZ-Oe#LJx(2wkApK?F+4XzLFE8`n6##I)v&a
z@MrzYYjvWkbE_m%j_GtK^Arc2gL1o7S}&Fcf}ZJRqEURnvn9vfBMz?I8`op6-C63u
zd$}BEJY$-HS(^z#kA3oFYr=Ccb?-s@tcXiJlp-ml5+Xn;G3Swwo_Os0wEuX-e?#WN
zXEwA~Say9Cm1*;f3sjvx)%bAlUyY~b)6NMXg-_4==I+6N=z2>LGrG_aGXiXGglzo_
zJ2Vz7PN=`>vw`#xMn$!M#~>S?+aLn*GS{wIK}*;O#+4wbcz5ZcZ_nYs`yX8_r8K2d
zHHo$$2#9b<3M~emlxo&7JpcUfW{oOx=cLv^5l92rLbpdnnvgzELqYv7|6_Fj%1)U#
zLbn@RY4?(SWw4^si{%NLd7Vh}4qv!kfUiUabsSH1*T%CY&K1Q^3pOTd*J&vcN3Ak-
zV4{m9{*2<CZf$LOFlC+~iM%MxZs*zbHu6R?V;5F8U2I;35U9M06sc}8VY9Z=XJ^Pq
z6Q(XCPxVT9THGtT!OlRBTbz)o51qAWz?}O3`r+b`B`C+LKX`EXJ^$(0tEG|35AIo1
z!n#uFy25zpI~M0vDs{-<>DQlVMRqahOP%$3&972y@JM4FHe=t>_UeQj{xpGg^?0V`
z#ns>Wa@29>&>p&Cs4~^xd5O*2-4c0DxW!ogw_jc~Xinz95A+EI!m(CS$GOD5VcM-`
zVXM*cc<Yx>)-1z(rw1PMt@zD4iM-ve+t1o#9&s$7!~(KjgX4=Oy<2h?2E6maerVB`
z)0-O0X%^#CuZS*iP5vqZY4ft`{tKfO&|=KLFMlFhopcn`?h_Vk@hFTvhu^cfb5i%!
zm?!6A*7BHLs~jh69x0feyx7am>TDE86;q6@yl=5prlTTccA>>)*=!6)8FQSlg)mMk
zME&lo+(pqX&0b&o^*~^eLeJBGD*w=<S#=-9LjCZMURWf$0kha*xL8AqbMt@UndKsd
zV|hN+3QJ~~#)}LshVky#;%yhd_0!X@D)8=nkB+K7FK>EH=N0<m8@yk|#r2{r^V_V@
z7qXqqyuIjPbEk1u#j_UcF48$W<Yz~jn7mV8(;qC#I4yVw9%+lcJx%2AL>5WRA@~39
z2DFByv?L@)7wTWQ^XLk;E4A3;a624F6?dGlg|h89$BuKX4F`_pMMxWRk23057XIT)
zbmzDbE>y1J*sHpV{@DfI`9<ov-aK9vy?MMS??4|rK-#=W9e!t_ver5OPjgsBne0B)
z)0fVfc~ODQiD_oyES41;YyX)!ySTse)>lw?2K?D$aEn{WjJ)&S)~`Be-aK7rn8mWL
zOU}+XyOy)_bRBb?u&!AZWjxNY;~Z<lfn&N?hSt|*mV^A!dbD)5t>1KK*N&@gm^eM^
zm}cp8QeVN{u{@q2H*#`$bv#9Wc7Y$apig<*w6~zYg8neQXvZ-?zQ_v=_1ph^p+!39
z|LOJH;=-zW=&i5jin=pH=1$4*EN<ndquOh}9pE5#)1^Njk1^ZT{^;TsTVfaMiS%(N
zmxZ_IVz=eODVSZtcz+!D_To5w3w+1He>U#<W8m0g2`pdmee{&$J}$?ukIT=`i1M>*
z<bL%i&#XJ=wBt+kpV|^VbJH0ow~VZX`G?}pIq=uI|J^4o>d+b?3l_GBZb#zF_b1v#
zA5~oXk<))pmalRsS_J09<wq``Z{MQso1(F_$aP<&bI$q;_e3v}cFxmv%FQFk<^n2n
zVCm0^#CF|O^JP317wLxPW0J7Q6Ma6Wc9*`Wz(8qUX*zC3msh*HST3lU`g4ELU2Are
z>zI^j5e{KLyQc2$K5g1|Z_Ii8(=#vL5kJ04pKq1kvas%^6Lii~Jp9)m=$yLH6l8j_
z7U?M`_4192wXnt$<<`vcWy->uv#XKQ>k{TopF5$;obzXEEYj!C*+q^SwQTRRl<xwN
zveXZMu*;lXWSc=*7bQAoDaJl{SI5K!CoCdii*CzZaAi6bcr}Hr6V9&UWmoAcV>g)=
zvzEofcORodmb&TmQ?V-^e_iw{w!K}PaNLys%3WZ7cHb8*9=@+|+#CJ9l|N}X*SGaX
zUo?%_$?X5qqPa+D$_<RJ?zXjkFUW!1aZ+#k-r|fXg3?%7v^NYdkg}ccS}cpi>_^V+
zmx*06qW-l#({h>z<kMmnaC6|>(dJrHWlB?*Q&+9bEAi5?Y!7Y1ouBOX8^LV~&xksT
z#YGW~uLEUIJUGjRbZ`bjbK6=`$7y6KOwXEi*6pXFmFclZb7yvYtiS$TTQ&mNzGrm@
zK8V#n_GM?@t@FDBhUC6=J!VRJLSuuxSMq2h>%6$~|C1g!*jB1rxbVc)ZHKd#9Nk}9
z$?YJB-Gi|?5B+*<p+!38Z|zd488Y3mP@4q1M``^h``e@)T~xOIp6$(&jhFqK5i>7(
zGIaDgf*V`+t;OY<aSYw+t7qng*pA?ah4cs`T!RroJxMaBX??c}4Ss{nG73bH^c7ik
zL*S6V?th<tb!A~iX>+dXrIM9p{#_pMoYN^;8g!P&ohwUYr9zIqhc6BD3AWfK)&{;5
zosI|IRkbTiP9fJD+msCQ6FDcWnB=jNb~7HW<-^=~>dIQJTK1R6H&!a8Rpy&cmnN=$
z=^vhF0L!7+IAH*~C};>}eD~#{Es`7Y_B_a`!Z+<_jIu;A;;=EdQ$MoBGAQqhIi8By
z2};!pY_*&F-vTC&2Pee~U<!oV1Yvh;2_l1J+2uRJq|{g3*GPWl=f+Cml|!06xxXTq
b#|c{~`(|>iwh#ct*!0}>Z=CV+qJ{qlZVx+#

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/Omega.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/Omega.sv
deleted file mode 100644
index 788b47d0..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/Omega.sv	
+++ /dev/null
@@ -1,192 +0,0 @@
-//============================================================================
-//  Arcade: Omega
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module Omega(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"Omega;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian omega(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/galaxian.vhd
deleted file mode 100644
index 5f8a3a74..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,446 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
--- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(3),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(2),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 5a4d0094..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 550e610e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,74 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index e924e09e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 0) = "11111010") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 0) = "11111010") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_video.vhd
deleted file mode 100644
index dbe0d0d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,433 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1K VID-Rom
-	k_rom : entity work.GALAXIAN_1K 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
-	-- 1H VID-Rom
-	h_rom : entity work.GALAXIAN_1H
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Omega_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qpf
deleted file mode 100644
index 258424fc..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 14:59:16  November 16, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "14:59:16  November 16, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "Orbitron"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qsf
deleted file mode 100644
index ace21d2f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.qsf	
+++ /dev/null
@@ -1,190 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 17:16:41  March 10, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Orbitron_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Orbitron.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY Orbitron
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ----------------------
-# start ENTITY(Orbitron)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-		set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(Orbitron)
-# --------------------
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.srf
deleted file mode 100644
index a455f0f5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Orbitron.srf	
+++ /dev/null
@@ -1,51 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/README.txt
deleted file mode 100644
index e07cca59..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Orbitron port to MiST by Gehstock
--- 18 December 2017
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Release/Orbitron.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/Release/Orbitron.rbf
deleted file mode 100644
index e99fac2363313842dc783872de2bfccd78f03636..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 300739
zcmeFa4V)ZDdFS6VYAtIa@XV-p83eJ_>mIQ(Hntqu3EUC7M?GR}mh))65_>)evx?RM
z0tiUBaPYr)NA49H;#V*S2e}h+WX_NfJA~wtyKuIQ6dcZp4RJ0`J_)ip=jB2UkHAS3
zUgG=ys=8-;W@q(I{!Z|tRd;p0JkL{4JyrEQRn<LDKYeU?^WPcx=C{B3?Qea%bM)wU
zzw_PieEZvffAm{VKmD!me)sRcd-UjcjvoDoZ++`qU%&d;i2m89I=~!|zbpJKoSFpO
z6!N9BxYM}{-!PEB=V|nZGg?`E2*f}Zue+X47KA4c8UE$&8NDoBWkoZK*ZpL9Q2sm*
z3TOD2yJz&Wbd?dFEdEsQ8NL&}XLPds;zN-2!7ToG_vP{{K7)Q7idS6!eK#-!=w1Yr
zM?C2+P+ULQl*Oykv%Fbs7MDF|_k6tQN+wyF?n)PA;ky8Z>p&K-=L{4l(6bHMaF(9k
z^J)2Tmae<vGoG?MVG3Eg?&9SNAWO^cidR_o46?K)kcD*@9?@6@sBa4tmx1K68c?41
z11d8CB!J?Tu4n1-v0w|J^hOH8lR*TmNTJXNWk6B$DP+ki^9A62fRe<|!4!TQ$cOXK
zS$uZSc-RaGXI}p#1EuR;0xE#&D^OepHpX7XheFw1byiq+#S0WxTn38E_{ivG{UfVy
zMk~9kjC4eNc|cZP>1sojSKJqYOb6}*6qg6ZWst=ye-_T@=`J0}Amb~mgVM8l2%qSG
z99RGz0KN=lbe6k624ra&ecj&xtV=<31mZ(?MeF`cz>R<ph&Ppa5K#QhfYS8*Cn+eL
zK^CX`SAhI;s}F7kBy)lE!G=mD@gPv25GX#Ahx%OBza$SmOD4Jt6rN7O#@M(&1|9{J
z)W=3k`1ADjEZO}_Kz!&qgP%`9@zM>+RQjK_-5wz8569{&kED?06`qW*NkH^6p0az!
zgYFq03Ri)*141c2_5->Lx8gDyCvq3<cLL%^?JnIDjpg9QDP-xY!!^J;fRe<go~0ie
z+XVTrjhUGEdJ0*Z=<mqEB`J&n3MxtA41PHUJ)aNg{s};G$U|N>ihlyg(j}kUf$Uj#
z^<RPbQJV|0eyh89QTvFV?&=?6MQPGgm6aZdmkf@j7t6Jg=;uN71ePOvwK4YkKT^<B
zCNGItyk(HdJb#z`^Psf+bDjr<)$W6M$l`7SL@(n_y7do0#)Iy9J|5)95rwn9lHD_U
z%iS}2S-N;v-LiOzOFSqpgX8g}^o)LX*BqPmg?`zHw#H6@!Wut*4EPH`x~BP8cj;sX
zPo<z|1+)0<u0D1HAbeSz`fVPRmIu{6|7<y0<Vk#sj|~1x3VIfg(oyvz(bN62fOu0l
z1I1}f%HZMwAeo6)273XG7umDsql~vf_lJO60O_aFH9uu>ioX{SPRUp{iQor;HGQDC
z43s1u1mZ*XfcVth@sSj=d02CeKxsB)uU|`{KTdoIelmsga*)x_-^ITmixVHxeZw3V
z>8zeJ$oJDhVJ&_<38?)u5I;FK1_tj=L3}8K*cTo}i$BRePcP#~_k4VRIO8E3<|Wt6
z2GRJLfyPyVY&3!5^{lySJ20BUe+Kj{yF>RWKs@L!*aqmXIDz<){h09~`6`_CjZ7GN
z*7&8n>>-V50`>J50<v}g0LbiW-47iD`p5V`2Naj_k=;cv4;gP6Uy}Q$0p-bLrTIs4
z5Gb61o+X$3y+54kmE@3t`aou<sqUhc@u4(5TPtn#YRPClpg7IJ8s7wJR}CQ-07_Hb
ze*|Q=Tn;E*wwh$AIN4}fUsFECZw2x^iMBxfRd=Q7F8l(?Mxd~4N8Lr|7gJF9lYs8>
z#bn#-E<5p~fWldvo->fnWgs2QK(qxJ9~$oToXNDG57ke!GsyVTm?8gI_n%AQe*zy%
zA&b*kc2x?J!3P1|Gf<Mk;z6K!LLh!^jE&3MPO?%syUQ+9co%RHptRQlip%EAmjRm3
z1?t1HGo%B@f~>6MAw7^TN%u8xXnqms`FNl?Q;_8o9*t!g{3?)*SGp@c>o>ZqP6CBr
z3h4e4K)NCjAG)hA>#lJ^ak}eSps?aHP@LLDAbwOw+0U6ju6x!#S=`ycxj+`LcDoi(
zoIvxJo;6;{jut5VdcZ!}Ykq81+lhW2GJ4`EgDg&W(Ge&to>Yh52c%aS=(!&r?t?D@
z`KUY(3QPAg`nrprKw*tx(l3pz8fygV_kRi~E(1Lu4<w^JsL!fzW*~Zl;5&f&UOr8>
zgkVsd;t!{w@X0_P-?QOoCGe~So|V9fN<ibE#?zksb3Mz=JxK!|yuP@5f8JPkx!5=t
zKFQ!ix2!(N63b`ryl!h>V%W20+?ROl$If?p#`a@pK3?keBP)-W<%H9h*7AglF3ou6
z8LP5BEU7oWajqq!Dsx=x4k;OgMM9B7RLPwyRve>1;h4&)@VW(;!V9G$u2dX2W6s^z
z7fq3@yt&8Dx+3KXmlD?jNl93H;MPg9WU$UJ<XCVXnkrT+j&p?&Tv*?7n-4K(1Wx0~
zIe)ibXvH6o9db01!2Nic*qTrUK9`2;%qfF2KDM?HdXJ0+`^TJ0<qiHzV`r^ja6Y~b
z#Fh6i)RObY3YCT3wc`0jC!7lWk3*y3-t%K;frKngZce={!nTvGD>!qiN*7cmDX~Pf
zZg)X4bDUf2x~lNPI+wz`gE_KA{#@~~-+Qi-&Ip{Ip5^KwZaVe;u6Y_fo_VD`Rc5|F
zYS|~9XO8&4-x)KbL7xy#>ap{QJ5DP9F*BdKUgU@6l*F}LPSq~x>yyIws(ARAoS#hM
z=?#m0lulJ-%o9st@4GauoC*v;clU->29qYA4CV~g6Hq$v^)>0P`BQC9Gf`$7*!#7O
zQ?01V_i=U$Q?tMr5+>w0CtT4q|Kjc5n@_!-i&$((nzp+?@)V!L!bSi2%yM>WjPwa#
zNIJV;e`>e}l{(c9<qYTo&ffoXMn$&nj15BGL!TQORQnT%8$3FmqMFHm?t}2i5By4B
z)QLV0){T?%RlBqXv}ft@YczmW=-uTpyc7J54X$%>a$jOft;0Jg`So_u3F@-2HxEzP
z23w}U$IHu>c<j#yjn7@)mJi@(*s&*{rJa8`iSXJ1Og!YRK1DSggzc7(p5j1EJ(oad
z;=q!)6N?zc8WlaU!u`3H%HMG=`b)X*N-<6?TH~ZjbK;Q|O*|pmW!<+_x14KVr=EOz
zs0SDC{P%CEslOMfFFvyFOP72$x}#FLaPy0TF<m!ZGI4ZI{YBm-*BpJ{jyL-U=C2*U
zW3+PN7yiu!=lkS6bVuc!WY-U?Oz(Z{tI^Rt&)ni;55xP|{mHKJ{lS=Oct!f~qQ5)E
ze$;P&NdKPxs@d02@YEqhwFI|ZQCP5{GjRRx+S5alF(oYbyzA`KLzXN3jIhFU{G>rv
zaqb>D#erujHs={yOKi3!E3E^#KhdaDw%G;{IMa-sYA0X9n%DX2?<|Qt<%nmp$WFOZ
z{RPi-TlV8W<>xcSm{}Zu_<vbP`;@uK6@;-fqp)T*`k~LRI8zfzSSY{h7qpVFj4h4(
zb#lh{@&!8Yy*Ve5(+Y-#&YN#LEet({>9l92b-?<4HJp4eOjxXAHO@er{4^u){l&B8
zPoE~1fyLLHZ7gnMQb%KBGQ!XMJjUr~BmeXB*N=Z<v~tbS`LQ?qUwY?nVR4fe^ZRjQ
zU<dv8F>8lELyM0U#e0v%Z67}K4kKK(-RZ;OUpb>=@0?vPI6c0MXIwh+l`W@-CSUpt
zSqpZH^1XJoB#-};!)J&wL;p-o$_Cjoj7b8)N!PY>^CwTb%(4ZR;cVIb$4Xd6WX3G<
zk5zDB+TLxax+b|4ojB7NdPd;wzj}(RR0F6lBeDTGPax_ap)F5<ivd~AFk@%T>Tx<h
z@QVZ3J;f+$dB$|ic_vOJMlKKEt!3bUQg*lFoM8n#V`IrPWgBgP#-C}CL1Lf@dYX|K
z$6)>*S@arcz89#ySFC>4?mlyNcX;Gaeqw+IpJEh>f2NixoYI$m`ApdGwkH4VZ3W}1
z-1Fu$BC$}jlymo~EQT#-mEZH*|D0ChRm-IZT-j9#o|$I%_t#Wud;IBM&+r_6=Irj%
zIB>F5CX9>ET+Zgs$Y@5T%cU>ft5XBtzm~V>+&y~M8EffhSG-Ttvi;t!c%$j3$=|@@
zI>hqqQIn-(=&8mq!<^AIk7q6KlWK{7_AY^u#u+waPD;YZ%=}Dd?2Jv6&JTU;m_j(I
z#AmX^PO2iu%KU7vJeG6@rJYd|o<;pLW_3HyE_a{7t+VehAO18~wg(pfo-TK*XAY!#
zdXeFg_q^g+qx<g$jeDmQ7asW!w=FljpWrsTJ$hlOcg8+;=7!7i|9$@{)hR8M=ZjOp
z-}$R!Aj=;GKSs7J>9Loa72)jhnD;^JqCEw6eW=*;d^!*Re^?7AcIf2r%TDNk{c)vb
zq;t`y|7nZtgqm1wd8Yi~@2|=7gv5K?OlR1=SZ<U(E+0!WJiFk%L?p+Juye_oJITG=
z%DHpzU!18$`ZNC~%b8Qb?;|&U;L`7DMt*OXyESQ?o|Qeg__GJRzgGvm^WS$k?oc)`
z!>;pJow4O^=X77J%yYP877g{P%_+kB{>SkO8lMGg9-}lY8p|{+8k=&Ug@64ApJNba
zCag+l7HH5dK}?1*BVXc^Us<6n&fGiy&c2jm3sX`kvz(<OPbpIhC=+ou**B@(ym_ph
zH-0hyXu_0DStzN3VeT7b8975ctBxrI4c*DmdC~teG5L!@*^MX-uAo8M&16Y|_3eK$
z(7XpFG*!=D=(5-w-F<qM|NL%vX}~nHk)G1JH6+@mq$L)~KDIvn^w?6mipiJC3N6#V
z26g8<Uw69XQ)1k*qIrD2aObIZxm_&hbPl}MJarM|k)`>h#=^zDQZXSXtS^ykn%QyA
zwN7P5EmzBYl(J{fget;Us@DhN?Ogjr7kf7lP}fBSrlMk0U!yw~ceebw@9Xj}JbCDS
zLV{GlN+(AxUqIn&&(momBkcb2eObFmOun$_TikuQ_CC4z22Ps6Ah+3aB$Q}{XOjZM
zZyz=u5C3i<ADNC!X%zTiD<z;?o~eQS@$INTq??$^q}-^3E11SHhFP?tQK}bf=FjGp
zNP&Tv_x=l=4lx}Ut!s^$E+W)M2Qwk0M2Lfo`ER~LXlPQnHgEvB=MyLLwMn=Fm;Hki
zaUf0&eu7;vuY+7!XY6T>omZ#^e(4=!la=wXQrGuWO2y67V;3e)tx^mt#Vp6hv058`
z&4*O{i<5v1`fy@cJg;y;!EgCWHlJAuvhS}@(Pi!ZCl5bQItPCE6COXPnc!j+l9sSd
zg5e~b95an;8zQSr?-L9aNIATLkt>g$vU)bOY<#_Fx|+yZ?4}#19U((L;NJPeuMwNc
z#<yRO^cB$>Gfy@N#WuQ)HY}nyO;73Uz7%~}IQIs+PpTs}Jsm4lQQ{ZtYrb2VJ!bc%
zD4o4O0mdF-SgGekZS=XzC;@{e)7SwxO;qP?{Qf{#uM`97oc#yu;zJf`?kGD+OVj)1
zF;F_U=uB#<h^{&Tn#S$cx@lCahl=*+A}Tg{$++T|q&n4rwzy4QVuMRiUwcvSTgK==
ze1kgNT*RQh<O4CjL3M)~_|`hPE=*{DiLA7{!2F-)ryAK8VFtPt*Z;c4-L6a2<e@+R
zoZI~>4OIu>rg3s@aM5G32Bw2|5#&E%(|Kj|>~cTL{XuICsd3dm4a~K^e>A@xc+;#|
z5yX5vIQ-MJ&KZLK1!&WoP4_d6OnU>&7*xh|RXxf8CZEZr=S46>pi}<BgNspw49=by
z`;f+KTD8{O(u{Ub;M}(@J$$_kk9lGi@c_b@)1Q7yQ;=%K9BV7b{6}@o6s(rf9A@S*
zRlv$2k9;6n$N89jJ=1WPRfoHkRodXo6kQq}x{n=Ts?_jNM3pq1)5`-40|J%0T7`*<
z*#yL9f)X87CL_2MWj7{req_JRnDT0FswZO8Kx*5~kS5mmP34y$CtDzrw&jhOI#2#g
zO2s_p@S0%{UWr$dN$E0V0;$M!v!t@X)4!lGD>d5k1rdfRX)Ym>FacXw*Q^niklXu+
z^(E6bwn$W68`2fYay9kSqw)Il>54QJw?rQP^z+jqDNe(MX&y3S!6^TrTATPmm(EZA
zh_f3ShNrB!QHK;yic@8~@*0FFiwg^PUu`}Q72-7LzY<b$F4m0dpjIX=D|n3il~40Z
zY)|g&q015!7TckVYCsfeZ@*JkeA?0`i!R1!?Up>5z^7lAViQ-kszPp^o<7EV@n+TN
zjdeQz>W3B6O$D2Jhed5-yGeZ|2TFlFSHAzO-KGIS5~OxM(bOAE_HPNMV@8BWBEyah
zI2u7=1gIO>1cOCylF}R|oV#54^UvF@@lb=09Wga=!7tTk2<2Bhjklqp17ao<G;;_{
zu&1*vCVJ=oN3>E?Btshhi~fmMkRlJ!DPdU=VS3~-m|sNM4c#-NPndPR6PZg?vHNVs
zcH4H{BKZJ$2SNGzf29Q!T#$0nx*(<0g?aV(eTgwm8JyX_z{NSy??4)HE$g^E{WUko
zh>?LYm*E{7RIpUsxdKaq*L(CcQ@h35r-;(qk|M{7=+u5)Lluy*k=--)j#aupEiAm|
z-=%R`Ytv9tEg*|YGn~k+voRu@D!NR2o(Pg|o|{Iy!8DMyM1TAVJa<0!DRG5q&m3OA
zZHyp>Hq1^`sjkN1xdPwl*}#Lb`TI@v<44~83XP}+i?!l2+nz2vSD>*C@`v?{3Cn$n
z(n@WhH?iwO&!OFG#VTF4b;-DTmhlrV+#^k(tsr5)RXKMI0!B~+Sfu8A|8)4-7iO2f
zFstsx$jB(eU%!uG{mbKPpLfw$mzvfTQ%^a0xc8HGQ-emg2sHojz`T(zJfcVZDGFU@
zxIdBZSpM&H5KS(+^50G`=1D&mjbW9dL=fOp|2Yw~4{tT^IvTVf=nh+kf-ayoU=Z5i
zv95c6%}Datk`tj5fzFn156qT&C|15bOSuEHcOyIR{-51&CPhWa?=rrZ7*p_s8I1o=
z4q<=L2!TtAEkkOeds-(IF;<GZWuRzG^DH*bv89``L7C34&+8#A-N&Ad&6pyw%SFm@
z`fQ8Y+^_y`eMpY?xRi7kYutHoX0dp0mBdw!v&C%7gp~KKFB_b=l!d|ha<O6I$Nzoq
zacQtyiKR(PV>%c9(9+0UjF>-BCVi)~HS;Siih-=0nCu|hi4WvB=?nI6Z}cTEeSGLw
ztuxt|0v-MaGTN83=kf3tkM)tEUWMr?IN%{Xvi0`|MCYRL_Xl>pT$VJ5a66w`<^%g_
zJ*lf5@|Tug8pD9|D?ipFxQr7h@dqX?b10HwerfroF>)K;%Vu8}m>auc6R@?_P}dtj
z_=&>hC$Co4yj|YJ+{?b`9$r$J+d9_W$0*k4T(&W)_uEYh=Oj-sQPqbpPxn3zN32|@
zj1n+h2b%7*dBE~_H*qlci?N-3f4unMbS-J(Qk=w@jfxXD)~`%@S}x}^Ebd6C-R!PJ
zp87Ijs^xW}9~hjPs+ST$I5<yVEcl%3-#gqFYadCY;z9)9eHt>bKpJ`P9}e6$r%kj)
zl>Qe|^KdLoJ!$WIM2~~a>p*_N(v1gGdZ4*HAd;T*-#@$@fq_&{G?G@iXRX$g22jmK
zHpy|)ZcF$pfApMZ?fzbMOUJ<8-2~Lbu9#??JRt~=Tz|m{Wjvuw_QcS!iT9<dYqCa!
zH7kR*e`GH|RM!yLSLTFx8Ib9gS7GNbi!1H>eJm)}x7>ACe-}}I<-x`9Vo1IS>sLPO
zcV;JD&&Fv{6_>yOhMxT216?tS!cJ%{b5NO*ws;R>>mcQ$IzMx030+}h2Z6DksZurM
zZs$naqiYH0iup!DJ!rqVDVM$&G&4!>0y>FlMRNisW)WTJvKjL`>ld*M45diAX^Z8%
zQQg2T$M|icMJ|>KFil&`;+P*x?5w}Bi#i_wfwE?tW%qoRG;9Qz#ou#Xes<4dX@M-4
z31kml{CV`fjCMXy%dqs`g#%>Pi_Mo;d~a5XGpl!4cyfGzzNQ6~3sa0`-yRIzC#!@?
z%kUAr_shMbSX$KZl+C_f3~8cn)>O+OO4DBRf?TG2&@6W6BNSHUbjh2gh8h={Qow8X
z>)H<_W@78-ZYfV$4yAPVeX}2zo-Hy~6H>ojw(4N8eQq)B;s0rtDi$Mb2!!yTQqEZI
z&(zZrCNVs6^pBS25`V&xRb)_(fpMMx`{bbbnmvWWVm`AI8I}wTnLtQO#c3MJ;0llI
z`rW}uHN4W28pB|hg89)k<6ZYu6Kw-$xNdplz#-NgB4JNJ$43|ueJn0)!+iVnqOs^8
zPPDOmOJDl=72)t;W4|<<n0<nRGja(>mDnm-=Qedz>EZe?r&B6QHqOQRdK;5|ox33}
zI%X50Qfvpc;jl8sIVWf2onxd=j`2fNlzw|s#Go>$E1&y(R=wUkRWQui*lv)9z^7u^
z&rEajnc5n)MD=Jgd0WI$@)*ChimbAh>v|13XJZN?%k)$dg!z-vZuOo}rmN@H&K~rN
z15#B}q*{SST2|o3o|%%8TFG17Jjr)~9h+b(+=;HS74N-LF2k$bT_VIP45hxml<Sm|
zDSPgR2WpWKSr2|oI@8KUMhyGr(bnwY&mGI(7oUqDC&REhr~xgPxwfU;W9_rhu%#9~
z`dX^&j^ssZ(;?kl(4Iq@J*a(f%uwUh5)RJ&d#r<VwRLo=ikrM-gE@Y6Yu)U4$;Jn*
z)A_ac=(f};$T8ycJITnF4F{yr&20GKV)h|&xfi!Sl=q%bK4(w22zBcoK%xX25vUi(
zm2^&vw6~CP5r1Fifl_fg|8n*X(f{Sgs9simU-VY)>)%~{<g(93KX$`S=JWV7H{4{t
zk3ah8v_6nO)Bd!6nTnhFLjHlHH&aAk$k+X4)m!W*^Vc7(n%}JYCy1neg??!3Nq)7;
z)~0^NH<CYIhg|!?_#xOb@=xd~i*Ctcms>1i&KEJp@@M7-bzcLwd~E<~n-rv3bPL_w
zLq3?#gz@n;vnP>@M7;n-m@}^g81q8TLNGqnF|%Qxy$NO*nPN;Mvg!?o0nw^moxG0a
zn+&Sk;cEwVV6(7Jszkvh9Ae5+Nf8!ag^UTFMwxh`j6H64x}9BH%_2)qe%aVbK_n**
z`Ad)P8f2ydDd*hCB0d;13_BFhFg*6R^4$A?5+O2BUKP#}HW?-K{y3AM%e7w^Bn2Tf
zOc=SR=Q_G&a)DAY%02PZ>CW5U-xFaUAWy}SUtol}IF{OEaouGR3l4@2VVml7zL@Ua
zb|brN#U;<wTXmF1&{9TJ<`Prh+8Ze%9?1tYRu3O~@5*jMe?S5Y$eRhin{Ha9%SaY&
zq|o{Di_&M6Hei-Og#%m}97CKoOE>S~2WiqJ0J_kPsYDTRTS#qUkzLxw@-bik4@=My
z0g(_fa-o&Fx@Hsl^7rx6x%1P`?!GK4hsA81B9OuqR{>?af-w<FSR&xg=l<Fz9_u<l
zhJBn_dW<FSw8Z<dWz48p9}i-;FG{&A?~lEAKo7LYmvWFJs_xti##K2S4RRAKQw%?b
zcXZf{SQ(Xph`P8thrZYi_Xg5taD>+I$|dz{x*4-5lb*)jyO-nlOCeo+Fp>h}(yo$M
z`n0%3d+*;4sx(<h22)R7^I+opnnbx%Nj&^t2N`#o40zFoF+1ccykb#P7PoG_H9#25
z=9VH<MicD()U|^qO{&gVOHngO!wF%_IAgY<Luvkm#u6Zv0MDW&QVQ>V<M2XO+uWT_
z*!@#9EO#f`T(+e_NO$h6$QI1+d|+wW-?(ju#xbe-PWe3ilDd6?BlT)Za%#-$8`$yX
zm*@qJp!@zt?aTFHY}a<UmJxz?K#r9Km+Ht5?OVzmQj&0FJ=g385i*g`_-`fz+4B7_
zc9_JTc$w19xt9!TaPuyKF|@IBEdxlT2fuMTQlyrsbyVb}7&hR}i3Sa6rldhGBi;Zd
z%+AK5Rj(Fbd`d&Q8GejMl|8-c-8$gY52+*5-IRcPan!4_(jl>6Zqg@#c~Iugb-!d|
zdan{be{$0JuQV$oTW#tNMo~|tuuL?fALx!NJNqY;$Ey=dDci>37_iGCA7#*gan+OH
zI8VOPMWF{;{rNXMe5XmSw^XSCu0uWrpTacWg}5!gvtM$s?|$eVCLMfI<D=l>el4v3
z-AkACJ$Pj!_Y=SYzEhBSUcJBUyDSFh+*b@Q>jybHkF|&hh8b2cth-K`s+c)!10y?6
zd*6FE=pC2fMDZiPGwqwqul$Za`X2q-*yy9LFhBEq<CE#n{ObPI-AAkswPUw+sy1Er
zXp^7OeUW$BKL!%~ALG^4uds~p{L??a4v`Lqv}2pZ)DyDXH2r6_`riyO$6zz(X|ag&
zP>@;+<{bK9qDx{!lxz@m&fhXOtidY}>TC=w);USjh%?Td=At~LvsFIIDLwVqH}^!O
z51P<4N15JCf2M;QY(#lI`MWb|H#U6ggEHar#IZqzOP59d37N=lK@%7d<$P_UJ;)#R
zWHqg&lU`j)S+F;s3L*a_SGe=&U2;||)->J{_G>a3WSfc6)cZ4(vfN9WvR$eUw;j8R
z^7T73e>kD%cBz3!sBjK__HYywUfP0-<vi{h^4&rv&@MH#(kOU3V8#=NND{DE(g56Y
zn%kgKV_+Mn{Hl5|V@#32iK0?WVIfEqX<_dVn|a9mlmjun((jTXKEr8>8LTM=!llI?
z)%lIjrSVH|)=M_*bTP+bGA6H$$s<k?oclIh)Id4lJO{9f{JL!AOk`!UtrQkRH&m^A
z;c5T5eaLLO#Fw^7Zvip5gn`9sccy;W*`3y-w_v(mfx&3&*G;wbEnZY6TC8~6=6U)L
z3MP<cNlV)Ls+oE!+?NZ4Hh+pt55H@_nvmjIycvuEwZp2Qh0=cBFYU$rnf8Q7|J#K)
zqNsXa+jIGHLD8@+l8ZFDsrfB~q_Z%Uh4XjAA^c^^3A4uoqmiAOcAb{e1rL7~t3lL7
z80GMm<YZ?6K5=^Zk;3jcbm>S-v1VDhYazzqq?HF|T<kE(z2gIS+A?f%0!_Vh>}F|8
z?y&fK`_@(6NbR4mi)mdn#=hzy)zMBjB4F=ZSYk5kKadtH#c8)uwcAQaoc5FF&~F&6
zmJC?v4u8h0F<nxlr}bG%jD$TRu!>(A7T$y|B-}~z4-edzL}DT3LIf@N_6B-^ag0pV
z64CaS1Z~?nJhHkmb<k<VLE*Jt?3BlN+m_9keve37HQK4MJ2_ae+R9;kZq`{^mn*d`
zsJDx8UrC2^Vj0eNHitLF&EboaWMa6rfT|=;W$*8}mi3;iOim2&%ni`ojY-bBysclu
zby`;Ktem>-;k4V%d{xM)*!*zk`a1~3OL{5jQ@2BeXc0XjFC#KxhCmK1k@?{s>`v#R
z>jt?%7|w8s+a%1X$0WBwuoSgz^!e!pT33AsB2F^jEL`*nRuf2!Y{Bj|!{kVl^xu#%
zvvhA(BOW7UTQ-Em)9)H;OvS2PZ~e#t-tM2|zylIbk$0)50YeGg^iTK|%Y>f(DEt2d
zIA%(>O=q@uj60(Ucu$4Wi`~i^<nv9MF>xdsr?oIYe9y*0Le?cm$<#yU3Q`ufY+#tT
zJ#^hsRilPX+h}Ir`{o7@tfp_38-=+EQp0pLF27u{I0qI(=xro_YaL#Uld(Jn#FSD1
zANXlub>&WN(;KMMz?$HZr3B{CK)RQD|KP0DD>A%<)sNI6K%b&014j7x`k~QBeneiy
zJIwCRj@@Rn=O5Rnct(3SSKh@de@lVxWLJ?iDBH!QY%(QtNQ*2F-bFVrvs|})nPpRW
zcYTi5901}6HuV-Mu2-OLl;zSKV!_x+d3L2kPU$y)qMJ9(nBKCP6LhQwQt?G#hO`jI
zppWcuwV3QAUwb6?ln=s~cnfS?PL7J`dsI|g7iZTe&z7~MKl8kJvAaBGV?iEQHWfIf
zYCflWZVJ|V5ZdtQ<ufTCS)#rBx(!U}&DZ<X`Rj)Q%$|WvVjMzGZblE2OUCgOqh;6f
z_(!uu%5X4Mk8?ERLGsF_=YzJK+UfeImfyI^mpDdvu@NphM>}BAG4h^7($k+RC^y3w
zZ1#9{@kzG^EOie4$Vm`CPSzz~i91gIV<q>0g5p?tkDK-^W5*RyUxsJ6#Il)w(Uf59
zTE<vmVCc0vmd|?byL#SU=#$CGJ$~OSaIi#P#~T7W-<_n)Qajk}W?5_?4ULD8pN^AW
zO6)>)BMyIg(9Ysg*183b75LZ@QkSyFe8uc9(1xYF)4XXxbfR&3aXxS|1{L+#Z=GHC
z%1lyJ%h_qS;n+T-lqsNPJV8JX--PVd1Z{#G2tl0Q&BLoNfacZ`iwJy*!L{qDrC35U
zCnU`o^!;WLL3DEfk~S{0aG8UIO42jygza{l2YH^()4R_08s)-N5E-81(q@a=c!9=1
z(R$Psip1FHu~>{pZjd<pGRwtD+6jo;ntBsjud{z!SPTm)&HvIcPJ39_BM_(JwQ{j>
z=8C+u|5z*yn<T$&?0>39K*l{b6|CR=UkbUBu@ez*L8L77@Jo~tY`_(l-LfPUidEro
zxbux)H3bbSqkL*Vi!X;OU9mA)xsWl*!tK<Avn~s<Kk-@|pe%LqE&*wpU*t7S!}5Wh
zG}^Er^~vxP(b@4UkgTw*w370fIU<fNhuVKIxQH?>W|roia8*J*3D;<yVuJDvn|iD6
z(ulMYQF3_wS>-)$7!@v^^h#6pDE3FDqD#HHJLT29$;kJ-a@?xp89)YQX9+y}noC*(
zRZAc?wC9y-UkE*04PD#qWPZghH?J&}qvEBNt@W_((c?;$0zIZw9xaS$VI3)?b;<Cl
z?_dL)SW^A{;VN~}wyJM|)uJl?A1hE2TKJ83zr>124XK8ps4wAXZ3s3Zsf0lxxzq3M
znGxXt5EC7yo$w%ur4TrsJwKlgA!XbDj6SAjYQ~UONdX=MLmQ{6HBJP3=&jv`8G{ee
z*ySxlk-U2kyG|*JDuvSKf<8h7=aCdatb$DLNw6p!QEQFqD#S3mKOC;Da)KmmDy|nw
z)na?s9~H|QMK(p07%G=*ZYhe3<zS><DR&R>>Zn3m6y_nwqg*Z%7V-TGiDRRuwt3sC
zNa6&YKmPaLZlm}i82Jc=Pd+awO;scbttoP~U=W68+%(65i1m>)I;wPVn_)I5d*8eM
z&4sA6&2z$dg~4M!JQ<soHrTQr6woqh1gKCI8W2Q^Qg;Bl9ai;loV{bOen%2D;uVc(
zYIJ6{ytNY7iW}qF=JMv1BYe^zx+)l%^t{$sY~NjF1<;)C@P!gqxFII-#K>GP`U(2l
z+D$t&n>?`kfgW+wGeE~9O1;lKIm!Oy@jD;?uPaK?R?qV`zGI}a)vIkT#$K&FS%Yfi
z$E}&xc|kcg-{i3uQKOOwlz_ylaTVE#54w8=)K&Y>_CUtvw)(ufy%_{FN6<T~)k^&v
zmnZin%m?x83;4gLfS!4m7Q-@ua%t+4vNOB5I$(Cnbv^@P3Y)b8?Jsu!v}`p$eZG_M
z&8HfjG(E;(yC}WX{L#3{{Pg<r-pX^se_d|vy!4$FR$xa)SB(5ru%$gYGrKZ)!Bpcz
zb*Hg%&*az-B;n-xQgd=QRp#qFTgUi9=z2aeN@eS})&rmQSiT^t1-5p8?0rt4l#1Em
zdVl^sEWS?NRa;y9!ovI)lh$3nSvp)i0;6<q*!g_(fduYQlJ;zHB>tLH9w{`YDkFtf
zxm<Gnmd9s*rphc97h08Cp|QQL28TGSo-FGTX7NoAX0^`>M#*LgueH#2TAw0M7fOh!
z4XxM=^GU<~xxXyM+sdstzO)dRH?~+mZPh%dv9%mdUgtR@l|o~5h|Ug?^beAt=fND>
zFs*MFE;W#ale_)ag7i~dSx~1+Om84|ZShZ5H#Wi5h|?M^hugRK;kH@76>VD?`0sLC
zYifm{=2Fg7P*-XqR9cPZKaXm2m|-@kOtMNz6{UkD*e*<2t-Q9S?1p~3R=Dy3PzJu&
zibvu?Tq;g&az<7<K3%#HY7Gf8=AxTXY4ePxLDZi6u-f%0XPyH`cahhOM06<nbh;WV
zVy*Fpd+o0lO9d@Edo*LcSeo*kZ3U;{q1CkBXr5dkYN@2ue2|lFiyH-}&qtK>o+84N
zesEbFmrBj)EuGiDuQU~TPCQbGP>{*%oNe104hzmS-L{oZ12w8=_ybc%L(hgx6;)Xj
zge`?tt-ByosYrBo4Y-}3fs$JBp?A1RsZesOEzb+5DjSN8ZNA@%U+xC8-in9o)s>Cy
z>&-ao<7Wk%#x<pGkla}&_0cvqnsuDMcH0<SC?Wau9+Z?67M>qo*eb%_I7`Ffut`l1
zl*|`9^-s1EZ5`Fxk&Dvb#^hsBLzU?{tV%D0yXWIWBp|f80{1q<#`MAlSIGaERc>}$
zB+$$sZ1a(!Vb+#0SBa<kSAK2Po+jhaWh`^ADTFr^v9-OIyNpZDi>oUcdlG3I#aos1
zBSntGD>%|T4NY?eKKYn^zKGoS?Qs%}6PkOjfL@HNtMi3ok)+5lCA>fVvG4u)n14d=
z8Vr0*;0;Y{U9q9o{mY$bu%Fqq(~&uxXq4S4WfKy2O@U|`eu<jd+-xRYOT+VjbNDA0
zpN|<zyY8{_JodXo?6?(!I5g8^KoNFmSIBE)s^lq<IcWYcQ0PiybQ3eR3oHFnyyAgq
zzGM`@M$w(BGp=EEnV}$QweK$5eOgm}5h=N0!5E;T3sP91YnV5QjUBD6Rj>n?=DLB}
z0LU{+wto=YdEpJjQVE-dE4UmVgT##P*%h)O5u$EQE2k!_7=uXt-k9Rja~?cqJX0Gw
zL3s29AC`IS!|n`Iop_Ikh=bVpe+DHuEm&Hj!G9StNm6Uphf8(Z)$tRSrH4Z|1l_@s
z+vXA5G?Buzl8dHRI$l^nDO^(=<epQuRcL_^%oaHW2^jH+424ZAh_NQ42{plWZON!o
zb10cAF(F<5>E}jRg?>4##}&6BBdO%hlp_Sy+97<Qr`gaaUZCAiu60G}S@wRry|2BG
zIxsHLK0G74C~^)a$-EnBRB{f43{R`0usC!5+n(cKP?x-+*<uhuv$!#IDdnM2Tk2C|
zVCI!cu!j}fw7yzLr0gWgQaa-)>ZIDCNBbkPx^nSx{fFB%<O%;J_w65a?P774Z_rSS
z&^6K#>v>QlXsQ}aEvPl(w2so(wlXC5?m(s4GW3SPTN>h&V~pIHBa1T`x+Dvj_Ub;s
zEZ!IYtW~Y}c0?oWCLl$6mB+C**kJu4=2}n&9!(E0Eet_`pm|blY<3eZwqw{-rqC;b
z7<v>ZPv^J4!u%7274(xC96^<hUqq_$>6A%ea>LLVSxmT8j1z~Z8!oLzY+-$BJmeTe
zX|+X+Dbp^E4o88OdR}m|Lp{o|DaXa=hhY>F{K2glHet~+RZx>A;fq(9F~v`Kea8)W
zIjAY!YBX(j_!(~p5uSmU-0}y{cgo>bFY@Frl}l043)C|<T8#7wYHu!b-zABZ4nc|9
zkMK06>xvAksG!=K%EdVOh^n=}<hFK4;qVV!8kQrruS)fJ+j-)#j9E_<4!G4!bv|P{
zD$!61Z3R{9K&?O*muHRil6FjcRO_bm8ZW~4B~@CdHFoVU(me{M5hNYtQz&V=mYLWO
zl2|G=x`4_nhgjJeGt{o8n>1OfAg)vyayk#_`!PYd-HZJo0Ix^S^avEwo@-mekfyl+
z7_jKgV^UgWx|=u^jhLkaj^w!s!*Nn-PVGV2iq0(`X0RTqxC|ZT0z@cM2ugMUXW&4M
zLX8%pVjfMCI6AP0!-r4CmSk9+9-oKwu%BRp6Q_zLr6HE7)HW{TSXhjb&<#50w%1h)
zUL&F|^o~}gRVh1V298p}v+8E*k-Hc*rlO{MY1GFP#ko|oASG=CCNVUyn;5oZMDWdz
z{D128vaC%5__h}s)un`{z6`w`4qJ7UU&|EGFzwMAQ^_`zk-B<RSfu9=m2}>F$s3yS
z)~S(rYvgU3il}XQQ@K`-(5h&2y->R95@d^DbnI3Cd~nKX&YsnF6-0-S40t@mSkn7T
zSC6&MZ`X={raj))p4#+SYkfPsI%rHL`{K5L=hPixGj6U@vFY)~@WIA(eYQUIc*6Vd
zJ3<d`8ujSa+a{-K+kL&;v0_u%D{ZZ8DwQYwa+#SO_Gv-7j(GE_ICWCXau=6~#SbFA
zIOx^u&DHbq6%&;S9Ds2Knr5-VznS*T{M7nJ(+%45mFjf!K$6U^+UG}Mb82@jt`9NY
z27mD{=Zw)>4yP_F%SXbS4(JM)ur0i4`Axllsk3OtD|9UTW46Kfz>zM7*Nl~hZK2s>
zIJL!r2Tq2d!*{NABL?oN07d=;6L$GYZ*_QiA-MFNYYML&y|hu_1$A$HWb1kU#nH%Z
zb!Viox%uU-!vUVg<Q-06KW4j8Z*!P$-NwA@ZN7pfZ(FV`?siluZu_?Z?lyjfoau?%
z>+@ItRs8lFCqH#z(t6`QKiqOoF=~tzF5enB+pep7<3Yolyz70*t@Y&2tGB#;p~~U;
zcqfiCzSJd^CqLr0%1&_U<Qiw&niWjJ8w0xYh*rCT5u8rzU+M%4ts=kAp>fQa9LdLg
zJBvJxc(fSo^yizgJ3sxGHFy5%PdSW5jmh<XE0|?U_KFQ}2zO7eX;`0(QQ#PBW@?8V
z_KRMGQ}2b7=Upm4-h<M}RX^yLw$ceV!dd~Mh7olXl;7}ReBP7=!<MEIh$m5N;n3Ql
z`N{W#{Xu3YC$0^JqeJ$@Q){6?o=?rX*d9|z9s2`0eB;o&oflN`>|r37VUTQX#KmW1
z-dqSPD>Ted#jLXSEE1xCO^wo~XE_lr-wgP`9?amqiFRD`igC?_I9)%O9i3dDL$_Fb
zXJ#KQ#y(B3<{NKX8%|O8?dKt=ZQCnmxq^B_9}jC1o-B1$o5hUu-G4~4AVEv;EaC9K
zL5Tl{hD+1Pd|Yk9*c$jro9a)pax)Z8Pf+>ch8x^jEzVDmL*6Y-jY$zc^Wo>Q@DRMK
zQj9lk)bdFgT8z7(F6&~dujXfHQME<TfMJ)^pf*|z`E!%`tLx64vO^kp?!4}q9IEht
z)NRF$QK;gBzn_C~aCc1;br`KrPXwL+_9<2%R<?H5Dk~b3uVX%u>Y)*I4{F#|LQ&;U
z<V2q-M{7F_V^#<pYHJL&b~c8f5|yT}n`w>vPIL&$JL#O)T<5nB#--^eV)TQvXRVk8
zi`HE%lr*1^9#p0emfrb?&udIip)+&Q6qvp7Fe-#!I?sjDmp4}n47Ciqa|N0LkD37+
z|JeQxh-Q2Fy^X2u<Ib!bKC;CPx5x5h8>?FfVdmfrp8SI>#NFtPw;Krk);hJk??z|-
znj4*i(#Z#d&Rbsq9^B-}!!92WSCA>J6vF!xDcOETM}H0;<R_bTg8LEzi5v?kM^oc1
zT&n6Lb+>(}>9!xFUWv26Eq+lB&O?@llH^Tpn`MOu5;=+o4<Ng9KU|PUAC}vN*$NA3
z<IV`*D%gxj3-`^d>7fze?K42$p!pWI317HJl*Lu{MPeq~kI?Q#M{5`BsS#t~dZf5s
z+r?qA^pP!TxfmnfM=!lwestxtXTuiX!5Q%83unXjc(EHt=AWJMk^2b%jYh-EZpU_r
zX)0R1oy1Aogmm$~-8d#5G)jdv!W|#NCmw&^g1pm4#nn1w4U>Zb3RPW-fY=n^3y_f{
zzF@Q+Y5BD=++bO}9(&g`sRIy)#l~=a+x6>TT~HB*Qf=raCe2<fv%TCZ8$h<U5k$!w
z#<v5)IF46i0mg(&lT9bN_b1LGvOX1{nix4_7`d|1Z~>NZ-xFcPiy^MQZ$0_d2Sbc~
zy8>bOj5?3}sk5%Qdu+j(8(wFHIW~7Jp~9jJQ}|2&t#kS3C9YEnOvtU5e79K+3r_s>
zpACoO<(c}8?yYOq*LNfnXL%QlxmQ*XjF)x?&D+j@(}+7!9lof1aKDpO$}dZ9bRRy?
zxB15Fon*}~@dHPjo41W`Sb1O4?o^_QRiJyk{y@`t`Npwe%feaSTgJSnlJbpNKKH)c
zZzwF{YdWv2zGQc><$>G717jdu%qWESRFYLmJnFve#tWOB@&D1P_-mqffAZkv&cCRx
zzkfH_r!E-to~YgyB>u#v1#iO#wj5e`JgN?FI5^)akDu=s9(<r#UVqzp>+i2@UpVW&
z^{@8IH<!ng=uMjzqVWw=kG@cuFO1Gfs>%4p{)2ycL$c!KQT?lXb`N`R**G=+%WxB2
z81MFO3f|;a&q>-3SCWMt(PcmEl_wV5u~+`^{@`un3zu*8g30ku!Gw2Vyk@#O{?@qk
zX!B>wx7BaiT3t9WKI-p&pn3i`s{dJ<b7p|EKrHF_XrUKJfeeU6@FV*~bUs1n`{KGw
zk;XKGI-NOH{}7iMZK40LL`%`gsquKx2Uj=fDy8BKSXi0Xe9b%}TZu5Lt*O(1p=QED
zbC8uH^%bMQu|tqcq`S$SsOYYz3tMByZ&c!`N-RHZqrs<Im^TP^n);Z2!l>WX^axIa
zsN^-h>1I1*VTuJjdNz2mm`GF=Ft2^Mjya#;JG;KgK9wr%x9VXG^FEoPR)rFH1pzJ}
zvtf{Sc|*t4r7e_nd9b;RB*t+HU5u6p_Tq3l2w7&++7vUodry;95ek@+l%j~~ebmTT
zU9<Q!2V+wn665A656(XL0VIUTUjJ4NPywh*ZmnP>*j;f^uC^|e>I%m^g3fggriof`
z5{p&0)Wm-T7jWfI^GX?VB!N`iL)(m4lW>Y*WHOPX7jH(+)GW=y4Sm6!bDi)TKlKTN
z)QQU}4xBD?Si&&KWf7q&+XFOW%&LTwVEKZp7$<nth-t>?XXl*roZT4n@aq+Pji*Q>
z#;1mHxJ~gwf!6FntGR$#Aw&~WafQWpX)PL)*g`C-%opx{=kuI!q&!mgK!{(>bfdKh
z?T+WL8TUPtjfrnBrouGfL(ADOUt3D)m%g#*=irfQNFiX4DrlSD@0QCny9aGI)p2&V
zWg5j8N~V$$B+CQC&aUaz&Qw?^tz`aU<wsqTH1H}%$drTR2SJ-iv&Nkei1=^jOShq~
zlbNKSdB|e}Pb(xTmtKfm3T3lW0OC}Gxeox4vb;=P^^Q+Cj5N#uKy0iRv-kcXQlRUx
zDTvq1@<mjD8wpzec@7`aFr>1mke&?Z5+ZU9&GLvyIpGym`6jCEV>{2@JX|WE)mzOm
z1%d^wdIF$Z1oHOKGARkyFs|CQTsn5RD&DVBC<&a^j{NEU(lvt@Y17xG9P}0oi=i}P
z$!)giw`<r1rJ|~_DqK~<2iMY5srdB&F084Rqm`V>iK9m324Ou~!P*8VMP3(`%ViGH
zm=z7x!ncUk53+Dd3bD}b)r#{KZ#vjtx}v_FCM#XDJ83tnlOWY=qH6h|z3HOMI3m(0
zGzz7unGu9oFGqzkJC4P2qg>wVZ!$kt=8G6bOeF~ihHAHFNw^w^0c~d$o8?xhRwvJI
zjWwt!TR+pyeMu|XcV}hzabv~t;o)u1U0|U^XA$_10NL*2Z>zH@TQ=#UR=|?YqSQPF
zFss&w!z=<!k7)<m97bS`#4FB6Q+F^al^^>3vs$;|^8IAFP~G+%&Jxtylm5tx;04~T
z^<d;G@8V?SKzf{jQv>`UP&IHycCd~T1Yz&nVNUK_;9EFF(43Ah<}gJ##mXtuffp1m
zFMAwC2&O7G*4K{KFNq_LBHX#fef3>Bu`m>})DRXchwojb;}#W`BPRc?2CHCXMaa&7
z{i=vsYDZd*C(%@+uD`6Ri+85!Hct_LCYBt3ctn%e`AJe63a`QStWDJoBF~iFd(&C?
zx~(-@|JZVAfgz0LyCMf3N|W1l?m-T?{m<%y@xpsYIZKyq+|qQMQjN9l2<`bRJY3t@
znV)cjKdZR=so*F>F6?(c`3YxFxj@}o@wTmNG^K9zVWTv;S&Kj9FpjmxGN>(2u;DVS
zbLmpNdW#%h=HJ#`vz4LX&Q)3&pto=G?|t|4;}HZo%IrL{g1!`)TDHpXTG=XVEy>7)
z0o;s>>hj${SG3{ugEAKmYVHo*)_BZm04*(4QK%{lPrvNU(>kpS+77Wv;QNPfcn+hE
zj}&JcjF61GTJRd#I>qve6|G&`u}eAugiH@oAOm{pA-&M;4YQ1t9B`7TR%E4Pr?1tO
zcAF)Y+BEI?DNV$U?NA^0@A=zRjj64y2>g(<^U~K<v`8_s6|HevKRCM*VM@OI$Cx1n
z29&`pWhiX=aY|g9^XReOJZnA3asr}mALRf11WRs>(aQ9LEFV-^(Ks|Z)Sh2kJVYOp
zJesQ>-gS0knnMtcdU^NOo$t~@$_>R$=<IFqdI?Nl$Vk9)>KHw@DqZgTdDT5qf&?~j
zuyj@c7I5-8ti|HO1l%0dQrk6we^a%wI&4mEAD^F|n1wO3`mx2i>1IE?dbiVHu@sih
z^`4)U>Fr*%QLnS`I<B6>3TUn3-Z#(4$iXDOl~|zWwcExdfDNuQ@Vzq@d+$rk0){#k
zizTcvO>LN5ICM4Zd0PI6BIna&@SXkp5cg|d@rDHso?KF{wzT?tgI0eX&MdI<J5j|r
zHmCE_3Tk;{=@&b6C;=&?hY}DKK4N>eU8h~_qDT0ESr5^A`t`q5e0Ejic&i$_9W7~O
zed`qNvVR1O#!ly)ubA)|x!{~Fc(@(q;wB8+us+Ei5X+G=C<^r4F@}Jc!INhu1(^cr
zpBbmbK@u^aV?VXqdcrf98snVdWPqEK#0QCDn{O>AVgfJmH(vCbm2@nRy+Em5&1J1s
zJ0WJ{vBy+^78#4W$}Tk~Ln;EEF-t;s#%HXLWx2^eV!WEKL~iGkcVe-z3qd(C9lA{4
z7Buoi8t06a!9%w)T`MJujCGROQ+T2bcK*j=hdqBT@$}fkpMS2$bfHCCI+JS-+as)y
z5ub>~YG^PAH9Zo`3pW84+l-~e;lskZxt1`4+NG(aw3?;`nS83wUwtQtI77gL`355b
z*n|;nr9q^)SqhB!8r<Y(nzJINJ#-;LRQV)8@X)~twty<)9XY6eEQGRlwZh2S@}I*@
z1Qn3XaPz{Zi>)jdEeaX@+=$AE`y`1Ew33pWSoROZ&fdS7D7HAS&9-CEni0FR1)UTL
z%V^S0X%z^IKJ5b+U6Gku#UdABKN)O@M4ZpNrTWBB8)3_&iM7F~a&E~x`q9gs7V7IV
zv(VP61rCAOM(nyd>6Pm9M2zn^JCzVCjgegq478ezp=K*s?X8$neDw3ziYMe6sSeoE
zn4-o_GU;~CRtC`luWcBXI>Koh!bQCmXS!^n?Ynq2%Nk<4DC&2A0+lJ~u|TF6=F`lf
zRuRM^G!0ghz(sKeWLapHvu&$NTv`k8KJ?D#q1nt6w!U0ZBhctE1)lg*t11$Clc;@m
zPUV7_?i|rGk_3VXqAlzQ7F&RaD}Uqp2#II9o@LHBw<Lj4kRt<LfOxe8Cb;1-R-P2C
zU3P&EztHj<PaunaFgPt5l1#wjx5U~+BDTozY08$WIB*sk&EbdcC^}nxdRZDJapxdI
zj2be2pfFax`=CUKL1Kbf#x?9()(*5RVK|Q^73b~0zd{2e8C;7;Wekg!H$w+8cIg@P
zN<%d`tbp`0w%RZlA!qQ4*Uo1?8Lo*6WEB@0ah;lc&&B4?VI^5Ml+iJ!bzdN*u2d#>
zbJNjAgBUgq+cfc0zwz7p%8tH@(q(Qj09jifOGIK(o0_(Z+BP2#G^PgLMc_5xkD68L
zoCb9H%*!DyA`e0<GV;QuUl}mE#0hm3?l@_ON3MILIv!&}hS;(vNdoqPBxGfjkEuZT
z3|c3cmxf!e6=RP;s2qdHBQJUWrg#${5#b~cD#WZnuPaA5%^I!^ViRde7?of)WR$^l
z#bd3+l^1hBDDr1~TuHAo?E5qOByi*sw^(F1Jsqug!8e_>Ui>4!8LnuonHtlc)s&D@
zh1MmZ=o#JNp4LZ+Fe9mHl#Yo;-uwK0rB&_HHDd?-88gba6G*k0t5&0%d}emoIY5)(
z<u;DK@y>8+Q@Q)y8zD@mK?Qq(HJk3AW>G2$VWMV>306n<&y-SYv1(a<^(({rYdBQA
zv+{7fbw`hDI#Mre)_yw+SiycrA1BezSg{-Dn~yb?iWet7Rya~?-9hy#_f>RK9`|%S
zW;gxKalBz_{Lay#&sV>gl&*Q1-;QS2)~6TNZC$vjiX;8Io9ka%n7q*mwr~ibJs-QD
zuRf5pnn;2@lmk)a-d`*>wsZQ9J><rgAsO5#8gAX1LXbJHRKy&+Gd%|vggbw!KY~x-
z%#Ic#HZX6DTH}w;(4?&k4zOM7Vg0hpjr~8t-sJ-gH#x}OYBN>__H7!NJ5khm*U?t|
zt}Xao?EY`@EMi1fxvC;waAajs884c-&#;DfYPn3kPe+^4mVP+BpB3EQ&J(rgYwJEq
z5AuiZd=uyAK*T)5v5(>KnuFTdhM&%z7q#>bMZ?9X=u&sQjkX&vp$#n~AV`}(`cdri
zx4$;wCW&+K35Om2gb5hqs_M3GbP#clXo!V3)p_biIc&a$GY`yo`1WSJ2q)LzRnx`I
zgo^;6Q{<)*O&11S{-`<<iK*E<2E`V)v`X(|g*r7Ll80XGBJg&DQG!vE!<LMh?a;k`
z^f^I`7T!V&y9Ofyy%ZN4ywpN^3R%;?@NW%2X)fBh#Q74AC03q~rZ+g+5}}8Dwubsm
z$FX+E7ZSFVo2~{o9A6GsIP-j==XFAyxvdO|R6?vP#;B2TCC9W#LXurA$r@SN;A>W!
z@|>7}LgV!)4y!^_f9`0XUJQ$H)Nor9+BnC@Oq@gb{G8wCPz^uq_!(Z7V3Dxvu~IE<
z#D`zrF)Wh%VQ4PW0!{6<F?rRu)^*Lk!_riD#@}nPVa~jL=;v9icn~5N-sl{9{V(~g
zgFdyj=`0(C)6KWS&HOd&3q8Q<3cB@T6n-M={OZ<lVq1lm^ZY97XL2m5JES(&3OasI
z2TSNZPF1}rJM*q)<|l`_?N`gQjO9#iC`R;}+qd8o;bLl(da+9*{A`)SM$M`51b4Tk
zeS7ZdrhdW^K<Ad%3@55+fzi4xbz06{?mDh)){~8sMIqbqb#sylH#xbp$N~WEpSr;I
zC4>8zm&Hiv#b3I=@T^CBJdajddq%+9^}@j)cn3Spy*y-oU78~`B5pbQe7q)(KF5BI
zE`s7^>CEXo*$*6sIGvj28JDnmQ4)<Ax}n2ilix6J>nJf!j)TYNMx-ieEEcJW_m1Dg
z9%h2}W0bl}f-sp3)9AU3%EhE^Ffn+9O;%f}>9N=?-enht?%qQ##tFuS%ZLN}$|e9Q
z-3oSz!89$3lrIjHgD^K3VZ(nP&n5H5TcVy7xhjnnm~e?5=RX~`RvP$Z5oOjZ$T^{t
zf#n<Y<N|RN#cWsT+l;aJFm5YDu@QJUe30{y+PQ*2;)GAl{;9Bl7rO;%yXFBgL?)oL
zE`ZDM&K1sbfcGMis0bNGyw#;|jQ*f;z#@*qv(DAcF8+PrP*GmXI5D6O;DVi22ANn6
zi{aapGfz0It1*}0n^`4hl#gF^=_->FAx$e*xDMhH8#lycuxM%4gtO*G%y&9jOKlZ_
zSXQ^gDa?W<7c9M|q9dol#wI%u-+J(8EH7j=%t(oYzUl|WfvGNhTGYz}GO@KWrJ>0^
z*_HlG01R7QR+$hD0!X(Qj4JA47?58ezR&^1U`S%Ima3li=;2h6t0_BQyt1|;Z3yBF
z(6C0j>0^rCK9z<fcY`!bCb!H|8T1kVQOZvHZJ}O%+lk83Cl$#_N;)TvX}~g^^%&EI
z<(ZPNUId-EPP52i$^d<S?9rihBE)>xFl|O|LjcMOW<bx%f~viGLQj>#3A9gAp?kYd
z7=8Ad0<VV~7RX2yZ0T-Onw_;k{ZN2wC6z(ek@~2H2|Z*CSn0qK5T31f&%;WLJWOMl
zE+4u(O=`-MZxGYH>qQn23>njy20_XS#oO@8^lsteFX@h-0w1pWA+LjI)bQeZUF<{5
zFdL-#IlVcC3S&%kHAuUXvKYm$7A_>HG<W#Kjj+NC8|b}Rp(+h&4JLG%|6_70ugz+)
znHbU2qk2pcq3m4zX$}+*Uoa6{Z8S3+zG|hj$v8kP8(Bn%k1}c4+(5(VE%OSbCdntB
z9%-=W)RJL9xcP&v&Ts$vy5V$W6_W;iEWeHiMqaK0@CjQGD2Nof$0i{YokSt2z^_0K
zdgs^QX~Jqq>9P@;h9ZHKf)e(>;ntug#U~&tdU2a?ZCGVglx%z5fzC^B<Hxz!@dUOE
z`87uCC~|71vr^FG@VbuPlG6xYWN12DO`oB-R(H*G#j7?IH|<6Eu&kk~KK$1}!l%pH
z;@vcK>5)%9H;~MS{03}I)gzEn39kshK7l$7j#|0&FOd^zX_(K?Kn9$LB#vWo#Yo3(
zb;b;*Ir7;Nl|CwSlpJ71ylu1v8REV^`2%N9G});dbK+TfpXi@vupxtCJ)Q`qjDDxJ
zBV+nUB8q4KvN)4y8x1VUyyvpS=csl-`IeWRwR1n)MB6!DUTviNqvH+N4_+NNZm(nc
z?>6sqZ}HoW?Z1r|d#g9=70Y_%n;u%fwJyv5)#Lir0jBWDJFxt5g?ASGlCNXx>~vnj
zKC3$uy*-&6n;4E}@j9kH;Y8VHEyA0BXN(IQ@<q<}#PA_}_;~ev(+iG#{)bwD&H`Tt
zPW=ybTA8EdZfmCx>$EaqDzZI5XYvjQ27??B^{&PilhUBIP?IQ9bPM^HJX~7|KrN?T
zG`x?H4Ze9cirv<O(c6D=RXjW7P*wD2i%&~MvC;b=_MI8VDV%EtYA7LW-MJtL;)!U*
z=sL12anL(<YTN6gs^jkRDUH~1bMPl(dZIos8B=Mf-WYej{RgF=+QT_!@Xoqwd4?5c
zdLGe>B0&g%T#m8Yo&-~Kkyp=@oSd4a8uMx{MC<zB?Xk(BYnaN|DaBQ%((p4sJk|NY
z*3uNOx~o!?yn8;07HOd5H9*y8C%c+41fm%(8Vdp#NL{{wmEa-bv}WK#MI<Ho8LA4W
zDu(=Uq8bw{yXnpC1~qb^yZ74X?u3EKosMd220-i?h8Zeg&5WIqDu;t7MMkO$B4RUg
zT6(a!W5&uBC11~qt?9x>w@WMy*!FbUzU}<O2N@dHa6nwA-o>BTGJPPd4~4whgvN}r
zrwRe8M;-03hmc#>sVTLqDkajfd3F!jZRE|5#ug%3f5=s`g?qkWT~@sffs7A-bk!3G
zD4r{D#Tj&*H@TpF3#$l$b5PQ>&TRGz2TEhG3;CRFV+hAAnEmiri`N)R?5wt~n{^-F
zLA7f5g|k#8o-4cZ0cnQY)yfY)Fszpk@KdG38wyEnOM$XghFpD^ls3v-MIW~h4>B;v
z*%2__E1G;E+rGv@EsgGuXu+WNp|Mg7?K<4n-1`#L(U))N&J`Hy$B{+*;DxbsP)8?+
zl|Vat?%@v>_uv+&$}oqVadCG#a8B3ZZ~)$~2DZM#>{NBG01rg_i|n8R>`{YC<Y->_
zlvk@GKYB6UyYg+%er7cHa}I-#lJAy=+WF0fPWkGc`@49RU9g9|83oYV69h8n;OTEZ
zcR_;+?e6<Cp^KYQU=M~Ifx71mck|B}2iAlnw~P_y1Iz@*#aO;)O?DJp04^mpSfi)L
zS2JClS4+LW`T8tL8c17X;mU}aKYiI*!;#AX?`swjUTUKMCO60!aZ(^Q>W1Y48ffF{
zz4R{>q%Z_DQCO-Ps|+tnfPgXEU=utd5HPTFkC}}yV8p*l!;TnYgsgF*M}wt_>Lh;^
z1Z7y1^}<V;vYS*|5Sv(Pq~ewh_zdeV7rjG(^%W9^Guf@O$iPm|t*}BKA0VD+yszl)
z#`9nvld6jC6)e`39Q#$=LO@Q#B9AEpo)ZRzES)swDJubn7?6kVEx&wLtzMoQ3ra8M
z#cY|=%r7wSn?lrvTA3rn;yy*HYLOMk6^jh7+n_QgA(defnyJ4Xg;VTFss1EK@sEEL
zAu#;Js;aSsEdf|IfDt$EaT3PJNKNDWK^#Xl&z-4Zhk&D1=ghI=L((!16A@GMycbs|
z;?>x=$w88$pDoADrz-CWX*6nQa9c_#A*v8T%eHfx95Y5!X>QV9s%Fbcnp7}q%fcI;
z_t?@U<aBDEr5w|+#Rx(Q^#DnV!U&;!1Kp9{0fCyBJI)TAA~1Opu{lqh5OZHOa{gi3
z<RnX%>m-Li3Jc~*#OWHmsE?!$Ql!hWElz}|7B-N?=RR?E#FSQw>viadGJ)Y@vHQ%B
zD7_V0H9uM58V>A-?rTG~2S{&YLkrn@tJ^d%yGG1b+VYOB{8|yemX?}HS(h+HM{lqa
zoGDH1pfoETJhbYuvoppwsMPh*7wctN;i#|hXEd3Xk3|42lK1blTh)7RUePGZ{xHaU
zFX0dbz`{9}Km(RiW13d#M6gt+H7FR;&rKScnX6cB)rOd<+R^X4O?{DGDEGaO2z+a$
zC8h~fw-6RU8>gs53=nx6;>vyxTpx5CDsjtC7Hqsmx*YI8^}>1_8|g;K1|%Rg!-S#4
z7$mF5=)Tw_&3IkVGVtBIU;{OaQjrr0V`^xcnz4vzvk#1W6iWXCVL};c7C#VLHHndl
zt+DB}!W^e{`N~lxYb=*cd~T+&vX~yr6^!Z=LVyu06>HTQF^s>bOct}U2|G8tx`X~d
z^|H&u3SFX9L7NwWF3bb`nsJ9a+?Xd@crjzztBe?v=%7AI(KgFDEOPz*K92nhEH)vq
zfJU44^<yy}@lrBYtcw^>RD@?}(iJ=e?{@n-B%~(Y7Ju@kD;s=5gAs4k8=CP^GX1Br
zmW+>}%)ffYovlx;k7p|^UGYxxSith==v2MN!D7rUKb~pO4JeDdO9{S%vcAQe-8}d~
zgcqyEioqKlRA)#cyO{_x?fJiX@(ULyB`@YHm9#!%s}F7}iHeF5J($Ih*&<(e(wtKw
z=S*!#zt3aUN~0_TToKQ~WgMI>MpOeSF!`w$B0Bd#qdDDdAl6n>rwlj+)Q;NoPkrtt
zK8VH}g@JK~;oItk(Y>zYOZ|A~P!msW)Q#{J^pM8Qnj$LI%}&5HG#puvIKeStuZx@6
z)V=qz=kDCkmehHC2(2;H^7RvY^@{xszQBKbQn^1tvCNN$U&6L+z&Fr-d<R)319o<?
z#Dkswy5{`}10GKEC;ZmV*~{>oaUu8++V;wLYfCuhkt;GzF)wZhGo|7Ez9XNw)!=M1
zj?sH2u8BE%7+<_FzcAcxpk=F*Mm0Ec^;cUvafI0fm3t^(%lbsv>eR^yhl&QX_^v~m
zQbrkzxU_c8zy?|MCT=i;J7YZQ(kQ1_i_lkDpn(!Jc!?CJh7Qzr4#hYdY?M{qy|)iZ
zpfP^*PUC+Xa`He?0C`Pn8F|H9U<`UOy2m)sB10pFyyDpP+bPndO22XF!tD%0c8Z{b
z$z!_F;b<w_kgW-PCiVb-C%)(NE25XYQCQ@NS<ermwwNLB;0W=`F|H&xF#77mdh0l?
zuj1rSYc>#3O$G+2C6oJfQ+tj0#W<)4KwEwjD<4`|$*>Y3YL*wII#5bEm6Hq4)Qm}t
z+90uj;o8(*46Nt>b@Xm(%NL9!blS5Ri879+OaS;~e-VD>*-U|?T@+5@&fgwr?PNH^
z&z!sts)itRRLfAKDva!)h19YdL43Xy2OWsavePK>LKb?mN<@wpAfvouNr*w8S*XEl
z00@(IWg%d7=gGI)MGnMI0a38SI$A>=efiWZz^FJptEFJKv3-ZCM{R8F)ZZmo)DDMu
zvJQHLudFmF(^7&+oz{fTFB6Iz?yJ64*iW5sUiG52lvbO#_LOZC_RSvc=(uRT3CFYH
zKD?z`WPm(~_PBG=mZGB#ToIE~j52YIqQUw~>xr&Y%oZ<gt9Oq}?!&AE9F$)17JStC
zz<0wJt7_?{XXa5NVO;KXD-?m@Pvb${pD>TfS8lDJE6`}8Y}w8hOSf+cSqS71aj{Y1
z2r|=-QsZ_pblWlhFf2`ATt_&@VCnqVA9}+AgR5RGU+;9kk4BB*8~Mm5k?YGhDvU6w
z^O!!6rt*wlPUbBew>WV0Rka}9VTNlQY&r}aaVA+#I5%B7d#`);^J%#sjUV{=G;B!&
zsoh{7PU?yuMGKoE_x^_MJ||VaCo@Wv!P753YXgTbw74e67R(q@<_}{EFhc^J3wwww
zHh?j99IS7bj!IOl90JV(vWHAY8-Y_;e)6@h*$)}av&MfjF{cK6X-J-c!MD>S5sa#l
zVq#-QDxl=fo$rQO^k3$Ub;vE-SP8ZkS#gtHU*s`P5w5#vM#5piuwboG6Tu>R=w7=}
zVE6*U7h<FM28WeSL9u0+pf%tKDS^!=c&m0Kaxho0tqm!i<*ZiPm3G^4E&y@oKm9tQ
z;&?MX3X7##C^ZZ1a1E##0pyTrUzt_Mgp)XJTxKJ4@*06_KuJM|JJdo91hT1Yvqtl-
zb9=Jx$l+Nv&pzXW$IZh2q#O==l2%GXJM3&0G#gFE?wD17nvWp}@lb!zRx&D1_2P=r
z12wTIRh^2EwAYpEydS-5*YJ$b$lx;mgB~sutk#0Qev_!>B`pr*T|f!e)=EQFYNG;i
zNKy?kKvx6-$_nCWrozq$)n~81qVq`e=nzg*?dTo96M$@@2#a8qv%`BA6+5rl!il{>
z1Z*in8`Zt?&MfrUe_dDLESZFx1nn37g3_5^yV-1j!@{LPtgtyY?BI7{Pa4$d00m4E
zaR!)EjqfE)BL3w4!;PZ6EWo%xI<OcrhP#~lS0rEmG-(wVc_XYqQ-f6;Gf61XKuqg~
z9B9UW^z_mszWXCDr&l6Xka4D5;+5wovA`?h3BrO+76RLxh7nCZDcH`AebHi#bt;M9
zz~b?^Q>6>R$o1C`MSkQ<6=}J&1mi@(sYSFMVhLB8x;Rm#>Reth(oWTWt}xdwWK_6g
z`O64yBlh`XE4jSPp)d^ZTH%&&pB0s^;6cj4l%g^$xN*_j*$Dg2XtF7>#7e1%6_CZc
zWtB2P^$iV@pr3a^6FW(qIB{qHBb&<Y@>X7$RJKxqJ~$uM3(U3BztXUWD$~D9TkBFn
zDJPm~(6594MM=>k>;MxnY1Z6!8z$!`#{;J}HQvUwXsm5cHg|oi80rIGd^{NJrFz+r
z;7bakCD6bDydiQbCQwQWBI~H{c4-;LKtNY59thSIf&)QS$0m|}{#X9D<L^YXJg2rO
zT^iXGDaYt4{RHmc5D6_kQq3NSfFWV-TFwM{#04I3qoeQ&e(5;Y85l;spFWFrFc|}T
z*R^yOB*Q{1@kE}AA#WaF8<3<J;7lPdFe3sGZkOCdBUEr>fy&hDZs&^2ywGhFyii5L
zdK0;{!${}gt<s0ySrJQN%r0PGS5P(dpJi6CR-vc=86kV8MFZ2V=vtf%nXX>6ccSR|
zp*zBGB`VEnbtzwC7SL7~qWkGHf^^b#rc%&|(<V_K3s96+#a!a>#nK4^B?6_VcHQhX
zHgEecQ{|~fw9*Mzj8yA<3zJbiU{!~&!37@Q0gQ^_StD$ev;#iAH!@Y9V!6n<*xNkA
zjCOhC&J}p1h2j}iX`S!4eLt(3(X}{WWhsac%rvUkB=Mc`mbKHn_aA6X-#=exGx+N9
z`Khlqe)GG{%C;Ncb;S!CBN1ORVvKm<^oFF(XGr-pU8PkG+QIEktIbE|g4_9U+reO-
z?=W-d#EmcZs?}=AyPfu!hz@%9dFajMM!bfVtoH`eLi5=bCdPdnuW3}KuQ=HFK$Wwy
z?a`?V4o1<=`Ry0%46gk1=kg`-s5#~F5i}~M-mKTxtfh$KiBRblUR;=;s+kEZs%~Zo
zG2?>XIJAefrALdZByTVCvJ<wHlRHP<QBIMLUh}dR=IW}1ucECvGVwX5_WCuvo%xP3
zUqG9kDwj5n`Qyo@<@$S?|GK<kYQe7+zOZoTqgM^jPk$6Cadfr1v7Fpg9U0v`ebbNc
zn48=%G8Al{!V_+|>xLI9?6zH8ZN#hBZjBrIoyg#&<&wXn%*Z&(%fLawu^&uhwJq@Z
zT-sJPduLx=$D!UbI(e7b(3ZpY&?mQ^KQa6TpWR*gtF5=px=+Tu7|Mswv=ff+245d4
z^C|5Q;Sye2UeWp(@0tGEuv2CSvs`Wm8_Vsuv1RMR$khzXF+Rz<!rbH0)_Cp+Z;W+3
zuYu7KeZ1^c*A~`gnuC-BEl?RBY5NvjO`N2i4fmWX?=_#}HM~kRx!!Nbv+m(nuI7_$
zmHFY3sL<Movt4ZcO3;FraPl|Ht-E+-_by%*E6i7$S5;Vqh|0~1KCQO(Jn_<s8R7Rq
z`pT%_tS#U&dv_Q{6bVZyz=xKgagjM=jFE6fu~S_eIIk(!hUKFl`d6dh_`O$hc9~sa
zghIQ(#Q4aH`RR}F*6jQhh5c;I&tJhu+W1;rvZ)qLFX-}@HLrL(uUIzl5fh)fH{41j
zE}X_E%8VN6WM_C_w8oLfi>nkvu`fq_%<ojIcMgBNJikiI4z2C}-8Vh2R9Q0&mEh7B
z(Crfh;o&wHoq0ZKU*NT3hfykws#9!SH_KST^cL(OaljvAL*PShUB2?!=Jig;+36=J
zc<^Uy`8wH{b53QSTxqv;S8(w;C6C(aboC41)A>-D7mN!iL&5nqUf1T^C;t3!xzwzz
zXlr}>Lq!cp)K*Qd3a>4@j=2}+ateUdwHm-n!uZbZ#H^7dzH^Ru=p1}+)*GID6K?la
z3#}14!}c{{(Qj=WSu?qy2AJGf<8|$;)`XKEyVL~co6W1%%unA{vsbjW@vkdX7GHcW
za;19G#<g7N^e-**j1VeojdoZqVEKqZRKt&Eg@gr}tKZV#K!E@8@}I2^uU=o8{_DX1
z`r&YzDLUpAT0H(qHjzKH22y;#5bf9)e)%enG=Jzt#r>C-Cl}fyYkq$rnp{(!Z}K+r
z{PfF>!`h119Y{pGdQKG$jOGf#$ID^+7l`QYMmvd?uFMC;E=#wm=c~o=(H+B&`CG?K
zYUMLOt+_lJF3%Na=oGt)iSH-3))5k3y3d>dj?(UkbMwKiW5j~I<W}w@Rw<+v!+ky@
z`mJ>)^lmiaaGuqG(xYr~zhAyJ4Vl#3HlMTX{OFEw`Z7+zdTo8Um6Zy8e2wAr0fW%d
z^bk(*wKmteb&EsCn;2eKc5y03J+~T1>k76+f(E275HI@qp*NIhfp31)O>WxbRQ{|O
zPB1-p{@s`Rz4jMAa@l92AN$}<$*%FwM(^18==9O|?RZ=H1?`*WuO0vD=sU`fzUQ|N
zeYL{<6`$pPq<rI({OY9wi3xn*$P1HQ#O(OM-stF_%`e(?*&j8J?y0}Xd%+Di&0jzM
z=iA@mfpUKA&G^b+_%|24%;UWCul>Pig2xXWy?OJCYUe*59liOga~ogXeWYsf?7k&B
z`X7YnQH$rYN2mY(eLE<A(}%7dzhiXt(f54r&>gug>C^oU&d-dCl>zSiOTJE{GAM_b
zS4`*nlAZl4H~Fkx`}W%s`@fyEM`Qy?37Ekct9@F@T}K2BxYTYT8}SzIK6fY$VW4zF
zrx@7vIibZUtz&}h$Ly-RtU3KZ*4{t3jr6?p1X}P!vBx(11wdh7jf8%?0fHbU4w~Ya
zX4YeLvq4E7O@@Ft@?6gA3}JHY+$K9Cj<dU!%Eo9Aa^%WnZOY?Ivga*}<apz{Y|0kL
zo7$9<vqWn)-b=C`(ay!YxvVXY?=DsAoF$I8F1J@n?(@72XvW#>Uw18vKY&K}^FHtM
z<NN%0-*y%iyW)<#*9sU85rjeYAVdLX*fSt-M(*c9R3V`&fqxC`w}D{1?-cqhRtyB{
z_e=IQc?hmVe0XU=c^m>A*+#=lZXvG_v>?+Ca4e8J@J&vB<H5-he<R%zbM}LIs4u0z
zaFd{!!XI%`nL$`9<mthPgRj0^pkcEmw_K9)g8WU%KyDGqJ^scZFh5e3i*B-~D>x8b
z$``BCe(+~MJ_5E3TYNOt0-udoPuclMCb*TeWf>yAWTc=9>?h;I&SH;THJhUJ3(doI
z*@y`Qn~Bb*LCRI}J1N|dL?w&|^+m^{$Ql*YN$Rbq;9WlBDL`cZKYTv176AhRuoFx-
z4zJ*B0gI80%{0Oj-LdpH7OtK#@Tqa85S@{wXPJSmxhE_U?&zi<Rl<ZwK)-jRRL>J6
z$2J@0rA8jiL>|F@p@ofU1VP?rbE6S+ubBF=*Iy9<>5nWOrN%p3V599zX-Xt7670f~
zCwuWzy`a&@*OXd99b5)zGcLeeu$~TBeb=CWrnep(jvtb(Rh>Zn=7X@H&(kVcmYi#Z
zOJ}g{_7c+-^YpX^35k)f*`zm8{kShYSZ-uu)>HDe_+qNyaFr#UCu_~cNH$o)A1XwF
z4A6rBmO1zP<Z^DZ?HuG-0q<N6zxDfXGQ=@_BfG?aa4$+p2ADTE0{-B@L1H{5Op(CT
z;T5z%q6e9`I5saJup{@{f>V8c=l6e&#CD^AXe8S~*~vcM%mJAWE&<eynE}*A{*vo4
zwFoiCsQfUqmfWAe;)W7rd?}KKMvFnD;xGIf<dfzI_;8ft2frZXX};&o4Y;Db0*}s^
zs})k-Q4``Puba0U8U7f#FR>zWS<=&_%jO<28$FwkiC||Mt)8e{f2fX(y^&@|LWCNI
z1Uy&jj72Jq$c$@9{It9nqJD6U7l@u%&1H$Y1&EKtc`%FH*uUHONDrZDWR~QDOO!k^
zE#8!IHHlAi{T!V)l1#9dyk;RH^R*PGazPx&+@{fETblbv6tc)C8WzocQCNsF%N}tg
zghY#BfJ>IuN^HKw=J`*>&#LggCPw$8fBtAY4qD5t5n{$>nn8@P&=c{G>`Stkmzg0d
ze;^YC{6T=8Jd}V=GJ;bxHP>^(Zq5?b3d~Pl=K=0C1>;re$iU$?$mM){?NDToq@$Z=
zT<kZ(#n9Z1REzY>{bt!`j={jpRBnUpRKaVg$TAo7L{3Oy@W)NF^W9=K_#AlxmAL`a
z1JQ(_k6gc?Zc^gz_r1n{e&A)H$Q%v9$R3je`7#3dXpY60XquFTNU!Hf4T&9qw-)uY
z3Q>$GnT8SFFy;FwonT@~STI+l00QAKHCl2lw5hV~-e=w<mML$Hz3>RLLumnvD8rM#
z5t<Bl#Dp^8$%xP(?#ieJtm7FyEaxGQIAZl7brBgmJkkbx_MN_59b?k}{%<{MdBQZi
zAEkoDn2SaXNHP(0338>JokN}NLou((Xho9P4I$%kpJ2qZGo|!=nlqOA$egrzK!dpy
z>=ThhgUG9#3&=ACcmDJ@W$$}YTG)jE%d;Eh4)zi<U<2ySI$g0Jb`YE)G-KmZmTxZh
zy#QVs3JU6>!dWMF48LP;kaA*CZyCE8I>v+d%GT=IFJ<6raE6OsvJc02!;!-;$a{P!
za=01HN%K1w;Y9`xMfi~LuxeNgAGH$IX{f@R1!ykE;x{8vKyDYrBVM{tN|(|qaDsl}
zUz}^7$}c^f&o!4``1Dc`Z6Gs05qvs&?CcXkp4><HM4ZbPp19G7o(Q6)xEZtp(SYXB
z=qL`L6*OfNF}6zV+qwL?_u^Ti=!|+&d)}y3Zoe2g<@Y|RmAjFP&IM7#D(X(W`d-#T
zm)q5m4|Mv@Vh!x;G!L`MR8uW|EWVUmB0xVEzQ4*tEPnOa&983cPCJh&o^z&__K(-!
zG+(fD=P%jK!V|frTT5}{sQrMQS2kp1@)?^aov~}XlYbIBZ!h8^xM!5lrAJzYV51qF
z30uLX!18W3&gG6SRlJqh*>uWh+8<u*&DV>;FDo^Ainaxih7)hn0`O!=ilqJCm)mD<
zZ(hoH-i;eC<3dJ`9zA?%=}a7bJoxw3^e^Y0EkrBJQTf7|OAFuf?w)+)dVlpDBqwsn
zWz#0J-FUKKr!Lv)J|dFKXAq$?OaHx1%7HUtWQShrCkfSG&cCUDiSYDND`*_OpNRd<
zv;~lT(JZc9wMO~YTaKfku=r;|>T~Step2>rm-U_%c95@dQWJZ=YMJx~FrD;9clpNc
z?lJ{HNpIL+K0?7$5fcZp_WR;Y`i~ybW!7YWdL|pLoiq83pFLvr^50O0n@c$!CHBOU
zO#}8)R#tEm(v4j7qPYF1dAt4jU%C0jr^8E6{-^pwmp}bWhhP4{_vkIQh>cIFOW*o@
zK)m%wCt2-%{trB7bS;WrX!9JBzD47}=Rf!6#g&opO#5lN_X#a|WE=ejFCVqM-@D23
z@ypHkFWmV|@x^nWw_m>SwUK|6YwtVk5bfO>dz%FL@6VGFBGvKo2c9N`y+A?u?>5OV
zw3>u=1f0+1(>#JKe);`R<apE<dkUsffAn`rg#6Ke!yaZo+e|lq;x|Z_3}{_hz3<Yu
zF1NJ97Vs<<hSH+F6iMjsl`}8D|9kW#NP5B}erJKP3C_tHu`m2D*`F(J+5OMme?8Y!
z)}>>)gI_q+SXzUsGkKdGtb+8VCs$JW_dUUO*-tEfezDn5^CSZ<K)RhL?*JpAjsyW$
zfB6H`4CF~pTfKkr^Z)XJL;e3vItHi>N6>ZIbNVm8?Rw$m_b(9jNv)sf&n>P%RMUzt
z{lwEm^wO*#jrcq#B*RP5oq~GNDc(IgdXu7en0i@d{`%-!nroM2yRme?$%DogFOOKQ
z8TMZP(Z$QF@5{1tJ1yb)`UnW`(iywO#$6bRmyb&>3ASBs9zkAyZ6>|=uN~}?WY?gp
zY{f5=AN?K$ZC>Cy8JxK^-9tKjC50ion$w_8R4S?Z@5HUkS8WnUq#U^LcUQ9qn`bGL
zvs%8zQ|q2+XE9JCt-8b0@=~X`8FRdd00sykZ<|CL9yQ<2BJq;s7&$zXewku6J`BUg
z1}*IsC-x*6Lk^>v5lX+u{}lpm&k#crE%KbyvRO;OnnCZ<o9`Sg-srX>$*Fzd={sv5
zYb?#D7TE(W%7%xV_cdCKrkS#v?Db}+R#GdBGiq{kp65rRF>CdS7Mxt8m`yj29d0mY
zViz(x?WehASsfG#QS(KJ7nZ#I0j6w)WG?f%V%iqq3tJJKIeOoV=)ke!?Gh0KjRwni
zKJkZ*rB#G9%8}E}nJ$z7F1MbLR{A%QT!S4KvhpZF*>N5r!u02D3!#&TA~f35GwD8;
zWCe(6wE>efNiR4BmQcv1a5wop?!!W<?q_bvt~S_;$C7p1s7=IL^~H0a!;3oon`P^-
zkNoIOsY{U=K$!l)xV7>GT>Kf5K<5`4dw$_QZ}o`vUHp$-APpHbV=L#;oItiJ?Y;XK
z(MO&7t^*t?!1zVBnlCf;!OtM{N3H8USg}Cb!s@?#&ML_7i|kSlL}-3yLAv<pGZ?vF
z5MtAM{M`Nhm;^{6Xj*+1B*ZVk>G6yQ^uAn9^P|5(h!m%j%*G){_DieLyZ<Ed11sb=
zMMQ9q((B-*S=qygep#Gtf0=150D_}W%aU?(8_7FVR376wba?#df3NZWhf&*{{d`(1
zcU92dyD;BuH!pCy56I1R@4dA&o>|1szaIrM(ZF!K`EoB!wq-?@6Ev1;smKE^$$Oap
zsxk1ty3ly?!>K-N8Tz*&3uCTxU-<L4{;ez7Pp?Z}<p)8IUnCo{Fvy1d{oLu-(;;7a
zd5{h{9`OtLkok9bCkv!ONT+y}zew^TA2e6`Qt<!F6Xh<RdP7oW+$2?g=ZBLjKL|XN
znt7d+<55RaGbY9JdTNGbk)&qG75yz&`CC>C{KHLfB>8h@7`II$A$4d05d38S>3AeM
zdXD}+CYTV8S7gWbK#-#BQDEYtxK9Hg@C#r>!G(NFEYcy6Ds@S|4UR$DrE&K&zf~Hn
zdY3@u|Kst|-#&a9ao~Pw%vh4T5ip%*JV<oLGj!C^IbMmu&_oaszd4r-m`m=?3qo*H
z9ahWyCb+efcF^s^i@`@}J1}pjv9RW8;2wWE5^1zzur_d!^ZFh+S6(A^m<eL(wUxq~
zT*`bn`H9?S#GLUd7}aeV+D3lxb3Z2+M3eZ|<TDK@HCVr~#A_TSHuse=I)ZEy)!>%g
z{PjadNjWr*CQW?ZPu^L#Qjh-_!B;<5CYY4<U5)g}sX~D1?XwLn(cwrw_hjFG5ko;n
zBh#d8#wUYRYI#IkTBB(xmyA>wTS^K+F4|8y*Qrm1nN-(Wr*Z3W<FbnG@2A*>KHVtv
zRljF@>8Z<aPe~JoeJ%~F`;4NIj-y3B+fQIR7mB(}&*A44+=Va16^wwRFhaivU_GON
z;OcOp@v8;7Z^MeXVO%2e9O;-0#K+U>_@CTQKH*7clngEjn;-vGc3FO*5WEn{JRkmC
zyU%{X^zEOCZMNtTI+ywnq%T49$5jCr#6}5F6OG(gimegPDts~*dF$yu@j7i=1isG}
zG6nCZ+`eCJC>}cWNssvUvQ^2H>`olt)LrXrTK$vXkr@2VBlde)p!DR6%uD?K;6c&{
zjr*l~y%@^!cQ!|+t;XY0PsI)=hhZjQcxTj^!=Lm-nIxRL%-r)adI6<wTqwj2iMA>&
z9GR|Fvkw<$O*O8R{`OD4RTfW3z#@*Ok^2mRnOuTbn7ZWGgq_KEd5a4lPU++~`QA<A
zwz{Oyc@45SBH9>!o1Za7uUyP+pDYkH#V@o7`WE|em=pz3A`)M)CT*te7fAp}#)Nx5
zZ^d!r!(kkgGcocra`>tvq;#(kKuXw%VHi1cGgq?Kt?LC}Gx@2HJL&J2-zwV3J)v}w
zs0b+)bpwuByx#A}@HP|kiYSK+aMCbIaw>8nSrv)Os`8tpEP1)#=%+c8KT>zzyD`#Z
zXBGL|F>lIekV^^m%yqQ6N;g2P_}3>Ul)J}>n$S?<gQW9huYHn4ogn7r0<Uu*kBv_6
zJOA)4<oF<c<Z^&9G`AqKn=N!>meyXWj#@gdrmB&I^>SgHr4`G^xwKSPJxD2B4n7?8
zpK^HexKnUaqA}(`TS`t^EuN{S6k{v|`U~&>k&+!{mKb9J-^;YcGIb*#j!RC^3;e3r
zRaHxZ_o`TH872~hsx$S<Foe%Ml#5f>72PE~j4>HmKQ)>uS*TqpPAl{PWgoFl_wM|`
z!wDfj^j(CD@eYn;EW^L#r?CCMIMDypo%RWNJ>Wm4hwo-q_$gQHb0IzndzmOlSRe5l
zgv%%2c=S0boxH$lDfY#YwP}2GG1lbx50B~`LCZs6)?_YtXT-5!_N0@kmNZY-V(Ph>
ze1ta&amow%OI~(_suH%R;6R2K65prh<sompjy3wqzqDv+4G8&DeS2MP>QWr&Xe&xJ
zX8U*g&=oIUM%@*kvUPq_@gTs^dv7N7yx;#~U&R0A!(5#V_D}Wl<z6s&w|e>v?>b$Q
zz}T?)G|>~EhT>o==e^gnO8)B?&y?=|)nCiRVmUGp-N*<JQ5a=$dpQO_KuYp^B&<rt
z+SR?D@Yb9mJVkW42JiE6$=Qr#KKs~PV?IySj+ZVvn;IT0?1b#L|4{#*^gYIxyo*u)
z6;+ddRNl>`Qm4;6j?OqBh>^@yN{)jMmx7Kr5vBO>6b-7x7tl>-Qp!Fu{BS3ub!z_4
zcu0FUE!V#D>k9*F$vbG6KA0IMik#m~%4{-YGBeOW&*cX5)gK*9*bl#4P_~X!g{Pc1
zp8i?;ZI=#v)aH<(L2WOUdWFoQ*>lT?7Ast7UIEJTy6~E4u2G=+o{DnkEK1g?@rd`N
zxVLy2A-c*tF_%JA%^Qy~64_EKbthXk#zd;aja&8>#H3Dy!jkLoli8D-p4+q=nZ~V+
zEx7%P{*v(X++XycAG~|-qp!dDXYwhLwk{8WPURkSYH&m@3n}OR;_~3SBj5eY1+mOe
z_6^r4uco|tt{wHjcrq#x|JdfH4b96B$;Sq-j*MfV-uNmPIh!Wk2$LaIQ}1qgRIDOC
z(~pn;kN0C(BT-m}$Imw&obg{d66<8%e8WjdW9k{I?HDj5n@LdA3Wyivk($zzO0!*t
zS?6&gqq9hot|nK<U-B~N-=L|pn=V<^Dpoy2am_&~gN*{!IVX;{oUYX{C<;<P`ackH
zrY^CeDxQt>KjB@#2NHV7Cq=k9cH$Pc$T751jg|N&sii~%c^!p*vL7`vVtjDaVzLb{
zMfGle<+p$2h@KjK!QuHj(bL}P=tLMk+dnhg|GmrSX8WH!T8Mv1(pSfv>JfXc=h)Zu
z3-f~yto(TYr$6jHe(qb^%bdR4pZ`bCf2}`%_~WttuL?oo%x$~3W^cO4_(b@wk2nXN
z-~k=(M_>Ec!okh{58nhB@n5}(_qX2U-~7#+d{Ms;R(3jl9scj!;wPiGG<XVuhF>0%
zLxwlTu*C}Wn|0vtQ#wS-u(X&MoSqt~rc?SMgw0D;UjI;2-VzNeS>{vEdgi_O-p7*n
z)Zk<9`PDah3mctR^eLiD9`y6dnc3&h9ghFt@{IzOF7=t<R_v_X%WAfK%k7L-2j|`#
z&&+=-y#JT`U;SEt<ZI6tp05}Br5lCngR_3YuEginyY<s?*vXAAe6w@vZ=U>^x$^Vz
zmHO~xe|WM^PF}eGTtbBiq`B||t|7uX;diQDIDX%WaQ-vl<L=vK>k>73&Aw>gu#fSt
zxM{z`p0FRZ%Pp0gX}Nhik90$Xvl}PJmac8-Dx&OmoQHSx6+OP!=^f~bE|03wCC`)2
zXw(CXs~zoZP1j!H3e`z#LZ8spT93T3Ca_09Idn?vnzAPMbf^!sp3v2knmR3;m0$tn
z_{*OyIZnC}K-~kk<Xe18ZDdIaXTx+J!Z^>9^OP!X){B<%=kztTraI1O2w}TiucEzj
zI7$JCTyfB?=WrucJ?qzc=`np$O}?sk^q%fr(Y3Z_WmO2R@_<%3s=C%=q_th`Ipe)B
z^tE<8N1o|AP~iXgXAE*vzDAerQQN88YP4>jDz}^&a$hzbMP-Xhin*G=u0o;v4gH$0
zCT#aPZfkufJn$-!vwERJ`88@rOHs2QZ`xfh36nR~te)G`8>%p&-96ogefp$kiCiev
zn1n(QoEz?H$C+G%gL_)b(l>HM$-Bq@;_a&FaMW#^%w&GqK5k#L@2c#3oQv7E%S4ow
zOs@ya8B(F>n86gPb9&1~>wDX3d|9~C)|D@L2b!m?b^@oIv!Wns(jIs!hu^Ge5eVOZ
zM4wP&j?WxU=qcUX)h@Xy{uxrbTg)@&&vR9{r5#vWt@3MIJ0|AjoT=kKDsw2ze9*QZ
zxM3f?VdrMretzCglLTATWy|p(gi{Ob+ER+O#Wc=N>AQ;CI^`>R^1$;>R94%<(9rRi
z?UC;W8@Xcos;!XNx!CP(Io>2<c7idT(3PI$h9NW<3R7Khh}KB;6<z6Q=cMqu${1MA
zI6P%)>_?bGj-$(V;T?AI8nuydzJ){tVH!3w)iT+`aTMd;I;Oo|`;?k|Nw4W$__C%S
z_PoXtBdIL27MPrAhQT;7^l5j!!~b1wTdnkvH_C5`?4-KzSXWDsUbzBY<35Acy5u9O
zBCrD<?|tQM33-L?226a=ejr_L`->`nUS{8;+9q;aNSG|&w{>mXpRHEm;w}BE6Ygns
zMW4H(SC<x+DJEFW9L=btQ3Lw4w)EAys?H*cTlER2x~Ru{J#Ni42Q*gUaTk4=R4B7T
zq0n|%D9jtoarfXCzG93>5CmzP4##@dU9P{=o@v+fEkBo6G8rTinGi#ylP=6wYugG<
zDDLVpr?};y0uy>AdOY+!o?QvcNtj3H(q{)s<JPvabFOp4AHVI~(jh#WgmFwKS|Rfz
z2lKqeG*?B9Ar6bQ#;nLNya68%idVX*p>XJ~ZD&ne_z_#V%l11_Y(z4fmIN#x<^zR7
zQO=Fi)hhHA^_q_X(uc-GZ65Z<I&NF9thSNIK)5MwE~OX(itF3cwJpavp`gogp`fEN
zdYCE%hy(jt>-Avd742zPbr^+~nFc*1?|=V~-keM%(%7;KN8@<Ie%FSYvX|@5Ov`p`
z8+DOJ7&`wpZ6g<5CVO`FggU0^MLnS>dpn3#lSQDF@{(SrARMI%^8{L$fjWHIcIK>c
zMA!15MKd`p)HOpk^fB8|i0Qd5m%75VFxz87Am=3{{^V!hWbXTreZ($d8?zT}U*&^r
z%dI;(8L2=gu{s=^_AFN{x!cp@*Ys`YIbZdxla*@CXOpb9(C6V*g3-PcQ@eAp%f6~P
zw{=SwKd8M4CSwZ<G#4DsvL&vjc11hhl-|*p#w!}3MG6K+1VK3Xv3~}kjk=w`XfGS*
zhfd$ks(12AYr1Y@RbaU>jV6335m{~9YVIx;JUiw*EVrD{HO$W6(;w=rEU$(U9w|c?
zEp`z%Q`~f`#dU^O>9_@Vni*sop;AoBU>Z>?UDI0QTd+74Usv|E_R$(LGQ*J^tiCK-
zLrXBvXot`v&girnv-9)k{ZqNR7#%UP!s%{Wlu+wpZ~d!k+};<L>UKJ(!w-ejV=g>h
z&R`RB(U)=;bHYd>soIu8!De;&Kp}`#cx8!kbQ<@RL5w@<QbR)b5SPl1Mi^_*%Mk93
z;@}hQ#1lGbcCPTCVdin?wsRMc*sj}kOb|Y%jDCwPz@;;bc0t!1cYXa;y{%68?rq)H
zle@Y))nPFs+Py-?G1H{;ytt9;rmq@O-7WY&y6gKV5jt-iJu=pL;ErJ?v|fb)6`5|w
zJ1NtHIY(KgWMZVUyZ6U$PZWpm$L!Jgwtd@1&5PF*p5&MsZB6IT*Jpx&jsb6I+xX-N
zURN9z@)+L7LxwYuNGj-Nu6Qlypfo;76FpI%P{+9GIM@T;SLNZyGL`1esS=doa@zVS
z?c%MC*;&;02s`-jjGSlZ(+W5-W92Vq&pR`sai|@@gk7#u0u2UV^|>v7ZrjI#PfSl_
zkHHeOaB@fQc>6jGqx;GW;X*D0kw~Mc7&<+RPHP`2lQraRJ-)_-P8rP>(~=M=(g+`S
zkU}oDhtsM~@xp{|$T>rXeDOEvRmAe(09yuII5}Jm|5f?CJ;RxfWVOWdK(;En+y30<
z^xSrK?j`@4T6T3sZe82goeru^g~(f3j2hpJ(vRA7XvgclZ6`Hbd{y6ed<fj<+=^ir
zB8P?>LX*j6zA;VA43MabNC-^u2I6r1Pv3?sRx0bX>@4^UqgZBUv)NYNUUbDN$%#sY
z(K)1iJ-4YQ)Hs%}>Wyg>T6?QY7$2_;E(@aIbRh63r2uC3oU`qYxl>@XDUAye3)5TU
zw*)>W<}am7mH;+aJT_|6;YUqj(IIu<GVlEMgQ5$|cD8QkK#p0bj(q3a^_lba@_afk
z9B+t?Ea3`e-nSiQ&@XPe6K+M{7E5tbPj#+%)n>GCq2jH!J0yL8WwbUs-FRynw=|~5
zFT%Typq`qc(MWMJ*?5_1skfIXy+-jFc$GQEP$nnbdDpiL4+Y-_i3zXU<@0VmSGL=3
z4g`)35Kky}9F<Ol6JCNJx3E3#m^0>LPh91rjjYBF=zjr30?vX+1qv9q?rym?{Tvil
z$6U9K?L&865qAL4aH<hXUFqm&WyocX$jTswLBwY(_ZdHf-O1mwZyA|{rfD8-k0JM|
zO%ATbSp)5Xkx;lj?fdRF6k_&JRjhZJeaPu1qq`~hA{nCsQicg%?_or?IIp||D~T4i
zbR&d-Av!|{dm15Spx5=dSY5I5u2KCVI{JloOJ<`%T#%PQVRYJ7(C4wf2&FP3l@wf8
zTe{?2B!W4BkTRpK{BwO;SGZe;&16zhDs`4XqFS>QM*bH5FXi$P5i{edh7@V*Dsn6c
zz;n<b(O)gLNEFi?kG>n9!hAUwiTqkPXnMEPWviY?Ih-6w1Yphw5Is(c)5T3^PU}O6
z{*=3!J*FPvg5N>vcf2+2dx1D}*~>CGmcyN=5k0?9TkrLHxAaBeU@u%t*dzBJBAC=w
z;NqTUvb|alLFbB2qQA+cAN=6MMm1qpHn@o2Lx-`?#bt*8%cn(+i<#IeIV<kTv_O;%
z0O6j9+LZ2u<#vY^4vQM}5RGP#QUikK*3`aU#^Y)tk#Xjf=n1tP2o&H@Gx1Y!ze<cK
zE@TorST^`ne61Yc{_xu*BHpmC+edE`Ro%Ah_zt{sNX^&=<0BvN+PFogQlSoTP~&gG
z1H9**&_VehR2I|%Ryv}g7B1pO3S!Z=RB6KpOCeC@D`;fR$ANkGLM2gJ)CJAnhb$2J
zzV7Wqtbo!1b=Cjy-x>g77jF|Z=Z>PfN0{Uzjyjh0>P{J>UFUQI%;~GZTof(Qp((72
zz2y*(1DDQ)AMtYSsGLbfbb>sVJGUGJr8r)<s@2rPTk3=w-PI$^u2sQMy^d*kSK<KZ
zuR?uwlF1d`VI~rF{^DP}H3jQh641lH2R5=^zHQI6lmyNAJJi+a!%$fj_O2=hMNj*W
zsNzfhfyg@&FTw|U#Un3ORztXWJ=f@`agl_hb5@~NS9;2+GmmQ;c6~>OR)b3?M3hjF
zn!!ibl>C6jq9&xn%AA#)bLaNI>86?LT#oQ5Z=Y9-Zq7#P7TpmhP==IZ35zHZ2ObXh
zww;}FU-J>uDVK}N6{o@-k6%GxE9Lgn07_UnvclTFLU*%X>uvk0`;xLP_gZ2$Wcqz^
z&W(GNBGu5h&nN_d;pLcrTpd;ewi{VYRsZCtlc@6;lbju>v$O2DqBl4_b}ns+a-pX(
zHdP>mhH|Gcw{43LF?kRiK9`q0Wy`tIc7>*uC^dQ$U&4ts0JjAC6YgBBUlUI;p(}b{
zYmxGyx4?Kw&SVYQsfDQZxFzO?bi{z?cmC>DqN|jQG1A>zPHWn**0K#l1t$$B9W%1N
zDd48|sy?qLMbH6NKh4&-(F&XSP!wwb4Oxk(W?`aToz=6i=njCL;L|dh1#wJ<J6#J*
zSVfbuXg=S@Eq?a|5DskNuYb#sWh{&Y^|$R!`^W6@TUnrBV9g-7g5r|tMskf4#&^_S
z(l4po&NP||%xvq*igwin0OGQj3O<=T%^Zv3t7>htKDS96;@nk6mt9{&gycrVgvrq*
z^?=23J2+_=+ZJbC9Z#4yoa1Ny@KECAjs{|O9*8%xC+rhhyN>F(_KXOFWAbVWvxIF2
zDgYSjATGic2j-Q-U7Y)e-~ioYUim%((o8cV%t+790k~$1>pPO1!l<l?EPCTQ)W%~B
z!uJ#uBA!(U+(on*gbci)d8m;DUS=TGss8;5l_YT<wDHI$57AOU8bwF^B0$_S$vq?x
z)e(=U5iQk=Uv+l1Gai1d6XIKG`<A_vfrQSjXd_p+Y8Mc{Y=PiQ`L6uGg+x@xdxBFv
zL=1f#P{3UC?<5veEDvc)rvhBS;2Hu`cmAh2!yj;e9paALPLKw+<{U7WJ(IR&KPs_Q
za+1L_SY(ogOuCTQ3*ihBU%}kbiKTJKkL5}+=-QEhSuE8t{fI)&2sTp!vxPe(PZRE-
zM!L3#F%qX7?w~;8X0$l6fsS<BEp&jj00I&kEvMn6L0S$gxlOhVQ4vUOP)xmAD9jeO
zrzfUGviuX8nS;79J+BEwJ1ZixY&zqm=OzAERj^OJCb+e{t0ZvMPE}V#A<S3|fmg-S
zBvTCH@wryH*W;RE;9vJY|M+(Xz6BDM{R$4|=!Shl74mK0A&V1;Vhy5Zk^f>$o@p~X
zXU$Id1rkVQE;uFr<r(G<=iD3(+nv<NHzRw69Rj*(PWGX~(GTxqy~nsY=TbNsnq`p~
z$m|h^IxtW2YS4TF<--`=OB_G*yKhaBND!IJ)7w4L(&a#%pPp&+@J&%F5g6nzT{@KN
zT99u7s1sZ$asqZdYU26mVN4ZH2h_s4n0SCzQGZIgpHculr|J;iS%}L}hv8clr?Lk{
zJra2#rpP)0dm(8c0M%#yj~^WX&`puN8>HIb!7l`$N=?;oW2|$Hd3w;vqTCZ`CPs29
z+=k5S(gF|HSy@IHG6A98>41f`B<Fw?a}F?iUq7de_ckmR>6&EX5Cn-G<&ZGid`Ub)
zKp+ub4@CkhK`9n#U@|*X_cGf-Iv<#9?7P*`Tkgdy%W&IHIbC;9Q>YZ+FD?*EOh8&A
zr4U~umxvQaF~@iG74K2<iTG%24lqJix1S@U2t}oB$;s;5?ha6_yoWF_13lzUwsRiZ
z946Z8?n0Zp%iA@^#Q@Mx@qWpWs-OL}j116VYZ9M@qZ@>HD$jZjIL}rzGR?d#)~mO^
zEe^DB!gs2#AUDx7nx4)T^2N<?l>YUo`GZ`Jc$tN%IF#a+nw_1fm-o>@6~ZOKZQ=|J
zD^rqdK`zlBq0f`tq);YiJvrlx>u<X^+r?%3C=LelkhBwanIu^Lyvo%Xi6cB0hs;sb
zE(H^p%+{uwyd~=F_QXbnoldjuHShCil%he)BYTquQTl~y@f#Z8$%)TuwWVJXhkQ>5
zOxpOWP!&o9U=$h|VPb%j!!Y?Po=}O=K6;BlfFE%XsNF36xP<eXWp#pN6Z2#!+;U2;
z3)H#o*43CxhP8LaEAybRr#<N-N(DhNkkCn0Rn@O@<tfMA#T-5)76)aP;P(wIWN<Q}
zq%O*#$Ry}NP8dK_%-z8|zFbO^6`_JBnHtH`WJ%j(=i6$LgqXRUSZmmb&=H~=(4YzI
zp2KdC<@a@Jbxq55uc6hX?=~~~rJON{1b5R{r<L<?&)7|Gd>3xZtzp+dr_q;GNyr*+
zBYkDf-9%3ya3BLy?@t@_M+`rj9u<4|PDI%TgE{$7rBU3$ND`+g`F8nwP5Xc<MH;9b
zKB}7w;Mau<UX#riBXIVy1lJT%r>!j5dClKZzQoUDSjFa$mmJ)l;tPimNahYr7T7M+
zEqG;UmJYtWJ%Bfgs@X-no^3n%x^i+eHnj_!CniE9a9}Qp^m<z^;P@r~wtL&LEeFZ*
z4k{J6f>G?OTBva@`et-3Cu85Ns{*#Cu21@NH}ts7CHC(MA_kuZP7PJDN?Xi6pcPTT
zdRD<pjAE$ecRn5(8p#*hh#-}V8}@_h?`&l2UOhj5NR(YRhD=Ge#32>x>mp^9O&s5C
z0RvNx#Y~^5RI48fS99S~hZG&X(9KghliulVW4G6DJFjUq-ok(wOVVRzfPjOL572;p
zsMb`tquT=JQWHX~b<fJ&`IFx?6jF<d<6HKIeKfwMMPbS<SE4D{Xz_(AcheFxOSnh=
zWy^IxsP8Z*2)TDU{28x&VWD{+PH!b52hz;2Hd~xIceZMW#ybwBJ^@vey`Dx7h=Yb4
zOww}W)(PN@Bq8=u9M=+qJ>X$?|64Rbr0~RDcxR)`*A#vwtFSbUmY)wyHAzkeK_HDO
z36eIai`!Xn><u-!3kPd^VUIXCr2MlQE@Xo1IdE4ojww%>`1Q~uL<$(3p7;!0pok7U
zH0BTp%NWFb6MKt;$M^Jh1lursLw%`!{{hxGQq4_6UwY9!MS94w7qj^QE{cmYuwiHm
zH{BYRrVfamuxA|tW}xTe;a;c&9WJaaGsOW3*aEA15MFvH7*c85A9D;I8f7Y(QlJ)c
zlYl>_xZC5!3c9kU;o*Uq7;%2gwaAwo&wl+aGSwv7?JS88lElYRnlbxGJ%1?QcJiDE
znGBuDE~SlBtUE50PD>e$JU@wypWYAm7S^<Cqu2;p215Ir_B<tEG7y`@rPy~&iJ)j^
zTU!;lIJ`el2Z15J4J9V+a6+|YtfDZ|P<ZF~R)S$~*#Yy6S=_WoDW=)2Y#yjhY%ex;
zDBMtpnby5vjR48mHc*LIS(3zv$an<wVqXRc3Moxd^*Q9vIUjT&X-o>BF7CpFj>)}g
zZ4ng9TM~p$Kqs?89n~bd4RzHo)ZS#AnY0s(ZrDUrsP#K=1Q>6d97LUhA0<=F4xUP!
zALctvCA&+}0s2A=Oan}~!rrksWi&*cjX6Xd1n3-q4qGs;!t9BdQOOIr){r?vhy!Z9
z0(F9PO&vh|9`iN~R#SiVyubo!eQ<6W4jzNX>6Xs7T~=J=#Sw^no6C}#GoahYMrKj%
zn)9kN2$NvbqnMsb)Lw`dD;`amE0jyAP!}ZAL+P>xy;JT6WYkD9k7<4}@rq+c&fu9F
ztV0E9K_bD7<0uzc_6;%1*RTDESiU+ENvZ0h30YW&VU!=QW{gyqXoXHnWlHxj1#c^{
zWR;*G9DPAIBPmWTd!jRETalt-nkt~Mmi`V=Cz&uQ{fwi&)H#MJ_7v}yv_kgWeXP;0
zq=pSu2u(86fBN4U&PcuDC{rs)mVeIe`rT}Hv^{NmGwf-USOA%1F+3;~UW1JAHVK{Q
z)Q&GvkXW?JTIFfII@;E&xpqjG@!92I<VCx1)lp1)&)LeJR1O1@g!`BV#h`}xxrB*m
zHOWR%XF^lgpx#M|3~(?*t-AAze}4#RO;vXTY9W~}gYg^L6IqPejG9j)9t{DFW_aRm
zE-HPIY^=rfbadq-6~9s@VxeFm*^#pp)yc+U<(WW9&Xb_A$G6?<Xbckobh>9$m}FA5
zaN3y^GJ&!^<O@$dOpa6^yJ<`b30a~5N!GzsHTs%#H?Yx)(+Ci9V|m0?n`5?0Ik!+4
zr`E^Bk^1QL+7-f<DB!}f3u<ugA{_>*+Fg&y-#m;QI<KNI@DCpGUBK#43`r_=dxCPu
zEn<c)H<K7-$i4rw2}g30BbE*qis8qoh37-NH9bRRPrxLq!YOnV0_-<6uEiFF=uh6p
ze!x7&-25h0dv9^2oRcIN)Uja#VkiRP;-Tpoo7>Ri_L{$jrb^xw0meWGlLq1@87TUF
zUO{3cSeVc$v68~Vp+J82kKc-kZQQU&<7*ggH7b+$K?hptF*xt!MH-ESLu(?77O79i
znf4#<5WRCrm%Do(>bR=iDO*jeDW;orom5ncJpyQI{5z5&9dpqvpIJ3|C1KTo2Gd{A
z1(6L30SsPiL*#&&-JP9b>0T_PD#&;FH(?*6HRy;v6IgW$yUdPphsMibQFIArxFMI@
ztw<m=)`=W%nM4kvD8V2W%1IY{+ph2XfKctk`+8SbzzOhg7?Vhj4l}5kE;tB0w&Xq_
zjUkV}zmSm`kt{>@BKRijT*JfMwN>$Uy`EjPXU<dRvyfXO+Q^|uV>d>^#0pErlLCq&
zR#^&H$d0hs&D$_AV#`5M>ebRk920>a+O(q)ID;UDwz~wY1kZvXWrC4YEs}$5Lt`QY
z-GjfJXYx>vBh<`L5xn$8^_=QBG=;St8;QZh<H~_K$v|i#K~HMypCZBelGZq?|0P=U
zD21&^F`TB1AUKy6VH5~4OQu;DUqacXn`s=+yoJs(4=`+i4=~uNG5KP8u4-z9^7b&A
zde7;%!;&tJIh`A^X$?B>N;E-91tDeRGK{W?RN!z?Zz~dsCTlEM`z4H_$e_TSgNj!P
z7urNs<xyz7o(s-OBhzfj0;=9sr1VVQ+QjfUBr#eZ2dv@1qrf$v;A~I#_BGY$-Y!E(
zjCXR%uRo9k?xqNSOH3i62uf5fcc$&qoYNBJ6UIvs1Lg=j>m<4S>MY$jhz`j1i+W$u
z+ZB&0t^=LyQ4KfG5}c-HweG^neFvohTw-uMiK3DV4v6H0BwYf#B_jlukmR=!$%M+U
z{I73MrNq4`l7|$Um6|`V%B?JEV>e0rNoqy>I9dXlUH_^-8NaHz&z{~3_o6-A^Xdhj
z_m}|gU^F9+uec7I3x#Syjc+EhSQURMaG$wK?hGl~f~pYab;O+_+CG9c3|Uft_!$1g
z;6%vFjT+BqZ>SU52UY#lDHdmnCM2mJ(M;x?657`E9CQ8%<$<^^_yoUkZoh-JkZg*U
zDvs#!$VYPD4G6ACoKaPfjLKGa%30RlBbo%g5CVemQg|#wsW6c*4G#fjSR33QIzxXQ
z(k8KLa@N7o#|>sAm6ImEk`Tr&hb`JOG$nhf4~R}D;SeV}lKVh!ut|Q^amM$<D@gk4
z=!H(OG7=(?^j(pwo7GqCYB4?GkR<7d(b?zrNv;x~Fyv&{s!qa3$0Oggra4C@2;Y;u
zU;U5o=9fj9{;q*z#W_po$VJR{o?Zfa*8&JLdsc8-q2N=Gs2A@N;BVVT1prq2oh|(g
z%>=7F<4!j$Y6G545(2=%GL33&pX$n{J>gCYb@&w~lID(kGl{-bfMylAh7=%?A+~K;
zro40flEDoiMf^#gIG=i?eIxrIDfjSvc4j^;Y9eUScocFF%=Q-2v*l8Ql1>Y7GIlnk
zrXq1O?O?2iiypP5Iv{h0qHa4A_2Lcvh^8@QA0z{AxR+4JFALr#s22UGSYjQnW8x%U
z83@3^+22A#6?LkS8&dEy>BM8m%tiZrHpjZ%h9%7#q9Jz4Nmu=vvrW`Vsfq?2r5={f
zQUJ-mbfcc`ICyB#x6pbsH=pF*$>h|un|5FFZz!-L*&2c|^aG3Xy28-)E)-rtX-Jst
z$|YsGIZ3|ETvxyTe^aVYH7KVAfrMB;W*0Bo&t++MP^~PCWJE{>s|&=ZNTH=(m@SN4
z@sW7(%nuWA%!g`p;R4OZ(%S+^JeMv>O_Jne5hHiiaVbx|qE&BCGiI5afksO*OaR1H
z-9QFq%qcQ<4ba2zgoEv076_JR<+Ys^ltVk1a40)^sNANE#*Aabjocb@h<G82+_+Gv
zIeOWhuvK+DRP=+PiK`1yCSU=Abb}Q|7}G_4sOmGt<sEXgQj`P@UKQWQu!p*kBo%A$
z54Vjx3ZKbwLn0m~neNoo-C+aMZ7C99scn)b)PndmO|j25866|QqVbG~1pMsWmV=*p
z1ZOsdEtVuhG=HEgi+ZJ*S?mbRc`P?d2aYl%;0o2Vgp1?EfgN4$Bz78W_Bv2t{t2h|
z@iHWcCb8MQj)qDYG%z{U<9~8UEHj?t9YQ2!)bvyJBeolyujj1<;0UQmMi(m6YIbhZ
z?V{HQ${%yEHUvRS3m@uGsak1T1TMfFb~2=rp(wS8&D&83Bx5PVs9p%<f{(*=NKe`U
zNb-_zLL{}Zi||!)P6PT<U-|M|gg%Zum1wd$5(}tzE9rq)^z-&1p^gzDyXGwHaT<=^
z)-Ms~-$oy)Kka%y1Enh~<u(CmJ8EP~*T^mk5IaP3n^oJ+PA)qW?pUHTPhoe4@`%+*
z>6(Qf?MWy}kHM}f{l0;~J3lYQR|8`N&6+*~k;^d$AE>xc&RcX7B9RRM&){q_a%3YY
znO6>!gi7+S9Y#NcE`&T@!*STfIeILo9;ZE;wPZz$Hrq{q!ktjX4(bgE1~zPI16+*W
zO5p(DLCr-hJUo?{8q6V)tjK0^(lb|BJKaDev62EFFJ{}my*NFivRONg7>a`tDp^?(
z>vc`aB*y$4Q?9SwT|L&R?RD1lXj=#@XPTK$=Drh{cKun(Dt?Jm3Hu3RDl(_UC|qxd
zS|P7yG0Dhcr6Y!-r>z8+4UPO4_GPYNrh(iKNRWk!k9O+VAIt=WXfqPLsxgz|uQ_nn
zgsE%(R(5m?z%Bp6$`U<UGSzI+7!{fxf=kw!%q|UN?%Z86&&T{R-RS5p`dhI)Z;)a%
zjq)0?HR&b{S`{N;c`n+ID<A0gCw`x+iTs%KlkgG6p{-qdBd`>JGpJ(X(K3`KEx>|8
zFWo*!#DOM2Cd1yA*)fQs9a8CC4XFZ>CVMv5k4b0MOIy>rwhlMl9hENO>lip@{9YVN
z^;9&wtf{Ygu2r#;4ndfd*zi|shZ71-K7zhpBGo#Pi>xV_Kd))9vky6qB<+nkO~ls)
z%1H8iiXM(nB0Ep%la=6cC~NB=2^~Kvbr)h)Brz+#^EI+O@wN;0l7`fpn3*?v8$%<^
zM0UhdB)tnsBI+Kc)sO!Bw~)PzW0sAe+mxfpET2#(2(-x3OD%BGNimm<ix&KJiUw|R
zi}V3L;vW-!YUwaNr}v2ZnV}|b46%&nZwF~S>FiadDQ)@>?`e>`669VB@jA>n^Eprn
zC^R^jS^kdR(~_xYx*5nl(XD>r&t+!-O!p$OmV~R%nHFxk>)0s;v&sY+t&x$?WKMkI
zsN!oZbh)N3N(od%>STqs(unrD#V}ycn6qg~iPDQv)tbH@I==O&g=9eCzJ|bisYVTB
ztz;pF+gsCu9Yub`5f29NiBG&Ku|VtsLQp{C!Mko`j|Qq`pURnNT7rLLd&K6&l4qEu
zVy*x*x1G8IDU4}?ef>e`W1?C5K;pZ*kqg+IwkA#+EABt%Um=Ij6brwJ05Fn6&1TJ9
zt!MaF-oeI8DVSW9D9nJs>U&n{G8g7-*!dfF;ei{dxWEcxLL4Jc`fK46Bw`g$BYs={
z3q%7}xqcPjM&%cGOK=i_)0QI2lnn*IZT9W&25Hr$v=7%e>F;qXS7@`n&X9;yaLa~M
zXrnQIUAZD5!?@a&yy%qPh5e%IQf(gSPW9V=VA>-<yXdwUpt?;-bq!JUOvr_7K<7Za
zg<95J&{D&c`xA~5Tyc_m>W9J)g)81FPr!1dhyV^(B<fkm0YC5fD43uNjHE~gAHiaX
z49P)qLM%H0YXhe4Y0Y;ant1KR0(JL}WI$+adX~5w@!eDPyS8l#mcA^!5(2{zt?5$q
zmE)?K>#bv16}^;mvhrhm$HNLs!};h1NNi-N`PvzEwVs--7V(`Q)K57$<j~ijG&A#h
z5{$S7E~0rd9UiLhN_QD5Dt1|pXWX|M1Gz~7hB$_D2lZZie8VmWRHdnNv^3^9kzcd2
z0M>9diCbyzy`joi^vD%`cDHgmq`eonT`4aRa^*5-B}+l(sz%#vwRqtB<4&v;h_X5^
zZfkJ=uGT$Ex=U!j<E=7&lJO#~+;LFkfA(X>J|bfhF*GndM{iMJd6&&n95<h?r_ioM
z9Ewid>rw7aBTGJG^=s0@{Frw-q(z4mBeH<DV7h5Bmtq^q9Sl^u*1N6KlL&^C{I2Ly
z2UKParBEP+E-|Gi5P~f(3aSuZ{*cLeWJ%232#at?G?G2pA~%0gop<Uv`r8EHCZi=j
ziQRZJTO^6S=~Go9rbeo17h~00r^EUs)24$;cY$SH$m=;2l`Pl2MtdcYgIXZxC+#;w
z&_zahOKZ0+fN0G4NL_~9ft`~ne&r)?O-xP__m4WnG2&n*sI^VkDYoV9c_u_WyJ<EB
z|D(t(zL~45XMOJKrDQz@5MuN`Pt0LJ-32uUsZ*1qrs_`AnLfu35kZZtL5zsZkV0{Q
zTVP2@5?EI2NkPkWiwJeyz4yI2Q4lPRET=;PDMQvTW+@J3XAa?{vF>P_0G%Yo=pLHe
zB7uU<9#2o`5mY1mfu}#D%S&_~bY#H@{SYj?L5I8B_1W3E4gacRGWXiTJP8cL5y;J@
zi2<9Q!uCiAMv>B3Au))Jp&2^(*^Y@~M1^xXVrpDH%Nht((Of&vq<AKnmXNUo0N4_I
z3FxLv412w=W#S@`a`QggD)D#(f;V&LZsa6=KZ|AWZe}0yN3Dmq$o{m^Ea1052pKX5
z*4onAOexC?c8LfOX%gYw*1Vsp9{+!g)gVs21_*oBrko*AaZN4P$DGA%eI}Hmw3GDJ
zU|pb&R1K*Jt~{pwV|vV;;0`)yw8JtMkboZr_E<VV*`?dtrs!Iq+jkgGagEvq26zmg
z3zcv&NyiA86nrJDrgr4x^7#LhU|Ga)U?&fLsV!UthM~kZiEpBQi3RN`Xbs!$43V`l
z)iOC^3z_X?_*->al%)gI*%2)~>DAV}r=`}mO8X}S&}8z>D7eX*7S`R=*0;1OJfbuU
zVAj`AuRXLwoCZ<H8|NH=dlEfnIK3UXE^Zu-I<!9+uHMOhO=1*ydJ%avDHKvEWh>8m
zjI3lJ?ejADLG4RwQ<7D%YStsPaJY3fqB`NDdMsRVST&+#MFxK5g&dtv_;g0by0MZq
zrLXDOWbzF&uM1LuWdpNUr7S2DglyuYsU~TdkKN|B$;99J*!M(XrB<nAfsnL5!Ku*}
zZFi7K)h&$}i?DOP0NXU)O1lmzHMmLF8ZEq?UGH(SW#t7+%Bn#SHBRLoHBrx1S^9^S
zstViVuNoeT8cUpDj)Vv;8f1K81u|t7sF-8!JHX$c-8w9x9y0e1do;%FQR+}fobr62
z0y`TB8!?ZV?=FCYc*|sGwpHz`K5%E6E4#!V)PAW3k^s1%8}~(Gfu!8lrHW1qI8C=K
z2ct&K{U^owZs~F6(j;^e8cP}&A$<Uz!v%4H)+8`bpkOlDsqZ_(E;7*}N62K|Hs9Yv
zN7;kfMStdy<VO)pGvQqx03ay5juoG#9hEi%G^3|<*a@*eiwj;k7mnhiO=^^K)**6I
zJ#q!g?KsDDWgj)JLXMerW@xDCXplvpUs(!xyL#LzVX8n910wINw}eLmzH<+Vm%d@!
z&P<vo2pr1Qh3AGggCF?TU0+`(DdM~a?=?npOw;ldR!))qCOH~el8wsH?6yHi2ST)E
zcXwokg!f4d4AwyG&pq)*yGbW%-s37zhLx0-vU`G9{rUsRs&_W2fUaA%oi2ZsWPjdn
z`Q@xVFA^x2)>u*41^`2nSi%e57B_*<-}T1Av9Ng`53IN^qR_U;?%sIwG!cO&2-LTo
z4c|1Fl?BU~I6A?fGQ%Z7i4xQ__5j~g$P4q285;(QcdmR??k#z|x=nHD9S9*}$WkyI
zp!V`vkwO`-Xr8f-(n|{?wx<gd<dzGRp7xQUHN95h5v+mdtYCE5_>R6dfO494WDHMl
zQ;iaL%hb6Rp}eFoP?dq2NH@%N(rA0)Xb5Y3yoRxl=Kb!$6Ys;|8L2|_MmM0*be@Cw
zM=xg2*D0nFuS(qni9qX>p;P!sN^~6A3nh=Rrhm)Zq3nC1v%I*%Za^UJ7L4o?(v~!<
z68#!2T(qjv^HT0v((;b*3GkGIoN|dPbOb_bgBXdX#mx*u>97CzVTlSh?GaK>{Lcq%
z{jS#ZDKd>o8$YOt%b0i@Ur0dU10s-^S81qwIJB_0wUC@GVHNcad4T8H8##K%DEPu0
zHJ7e!sFR9qlnmJ4k~L0}3mM#ARzPTSjr4*{;$rCK)~+w0VyMO4gOg<<_=1^WCDn8K
zB=Ci@zVk?Z##ZetOAeS8hGa~vBx;;^)1m%yLX|rXJ>C1v4-2cPNU!kiX{y8MiJ0wU
zxd0oFqV%v$fxcm)6(kY#f!v^@gLnik>Y9aOZ^2yDq-VKk@Ib*+)%W#EPBP7q_elci
z5$dPv-B~~c_0;;vd1G4*5Ce&sGYis6PFwOz{;Mv=T>@Tj5_1^2iq20JM&OBvCQAZT
z0HX`u-qfnNZMz#(v}8@PX)R*V;HcLPO^M!wj;4pbf*?X{4a9*)4^Fr<`#)o9xV`w6
zBeqn1ZJTrnaBN<+r^|LALSytFy)tLgE41w@t+?JpzTB;&HJ*i)+8$e-GTl6<B=@D<
zvMIU&Eo-!!(N0f0*RKDt3K^6xg_1WJ2qQ=W@GkbhCumV}MGt8sjl+E8!Nb38>>(kl
zWFiP!%!*U{on-T76s@3S@(>S6e}e<%Ai+R;cYSs|+xrGuDrmnQa*NY?Wb{6|#{zKU
z<7CK~Y4o}W{9fO8(vt|@xMUi7J6c?siPS`4Xs^LrO)8+dfDDNbOl&10I{=sa%RdUV
z71(XK2;^Z22?(f_^-h5%MHUIJWXNK6_)m3860wU6*BM8?Sk=(XEo4?L(HZO_NQW+t
zz9T_cO|Qo<`7f!Ko|Dz$<IsRcykU_o4G3GhyN^v2#K;%~o0CApj}7QMc;7!xdN|Uu
zCpX1ulF4=Af_GvVeWDlELZdAM?`*OW1Z%~fq-X4q`&D+mYK3R>I83t#rTDxr<^*<M
zb?CWu;#>L}<UJ+HZmZ-&#1Mj+oVZLd2CX9*ibk&uif8`eh%lEv)t~)nLK_;K4{ST2
z0YR{LmZ|^`#bGC28`Vc-Wh@lUud?C_Kc>LX6<itfQDN_e9*wk})%F5UgIWqPh|voI
zz2^zES);)Sd@OvSM1|uH*2y3k0l@ciA-o3smLid)C>$5Dfg@6iOysosefAAxibsLm
zfyv)VbC${;cP^?{o$z!%-N1(7T@0dS*##z)#2s6a)Yf|z(Lo2X@%2hjUW!&$X$W2A
z@}_j~LN35St!r{RHmhRKGoUd?%Q82nvm%BuHQ<zt1N4bi^e~-nh^SgPLlM;hm0$lA
z3I~vxzi6jf^#_gDY<h~6J<6Uh)6#qHfFOkH@gTv-(&kNC6y1k?<&tUiys2<MJkVYx
zcR~71XxU-AL)zsdll-~r%+laprJlN>uq)pYL1VtTCjMnWLsvs40!^4IcpN(p=tl3~
zka~L0zcXMFhEhL}9XCiXj^9!@*l@#Ntj`=m#xMagIbwF4*c4SsM1U4gs9CdXg6Eyv
zds>8XWp$Lt*)=1&1Zi89Xrk2XQP94kkEvs<?ci()4lK;c>nkWrJxIhmRw+AyCN0y5
z!!1Q1*?{iLgE)E+YCVXTmL-bg3|hL+r)f~Yf}4d9n5HyTx?3)IKkK-?4%ZcXOQqNG
zRu^&-6tGP3BP2?kG>eP5b85mpsS0Bb5T>JX&?1NTB#|f;Swu^&!af1HbnRfW8R<Zm
z_rCR398{t3K#NR{Fz@IMMIa4&@E6%Dzy%);peB$7V^}TF#8G@nfe>epX=7~mJNx05
zw2SdXd0DR(G&8Bk191d=(US$DB$K0b;h4yvEH1!HW2x?`L#kx4y5I^fdKXW|30oon
z*mbN(!oy$xNra3Hjw}@tBqkkh*VHvt&&~wrv$mJ3Gaytf@%q?KZLs#M&T~{swq34C
zL;GH|TUiY=tE_4=Ehl}7U4<@8rk7~_n$MCA8y+fzu#6&LB@o0!S5lffekru@^k`iL
z+c@s?mguxO?)<wC$jq4}d`^+exozKaZuu=)BI{yuq+lr$C>V^I0&Iz6D@79IDttJh
z1Qvv>86R&m#Z0tx)QU3C*G(#3)eeyj0~ZuqdP3T|Wtw|<QuveHA2kMOLYjkVxB~si
zqX5}^4D24*-w+%vIUEW01>OK~u-ddaWwT+6eGahKCTI|>K`yZtJF+Ikze|dnjx}vf
zb=JHeXph$Jur2M~lAGoE^)K2AH7Ok;JB8r5**#X{iLN5FP(eQ2cmhMGE@8UekV&qH
zC~D5~$><D6k@~{7jUtQV8wGP8vk6#E$ZD4sOR(&G2$Y3~#)u}cSMc`wI@-bp4AS(w
zDJZYg2^PIoD$^_}!S_j9ElSUzsQMPS*_dj_7pv&D1a*rGrgaSvKeT!!OTrAqw9=Ch
z->hx2r1}U$6K)?rb-#FY^(?H+OPMYGAjOOaT6*R@h&G31V!eUbFOmOrDb3ZodNW%N
z_cUk-qg#2w8xNPBZsz1c4KyLV5~TwY@kI-ET&2I#J>>4{3UWv~T-@&K;T&tV`8@oy
zDu7vxO_k*)yw6F7w(8?sY?>ws2#}(E56yxAWz!ru=+;xB&L+kY@F4wkx=?es><L=w
zip&<QIjQIOFczcKt)c~*1lf<~QCksOVQ~tzL)F?h^fmt$?God{p%PR}RE4E5G;}Qn
zETyXwb`oa_mvQ+P`gAV|(LMOL_qOc9tI)TTMIs4V)|8J#BG_cfY={x3DoO*L#Q5YD
za4$6s)a0k66^M?LE&ccOX$?}uFcKn=r#1DplC(&Xf6^{XJQ&v%T@E2i0xazEFwG#m
zBwNyxHb>JAigmY)P>PTZhtqjyi5v)z55hExL{8N=g_l{2wittSFs8T`ih#6aZ<-Km
zoGurKIqrmK$-YDxvQ8rw1s5LS={YfqMbQ;8BtL889dR75XdOyWI}H3}(+UDTNiJ5b
zalH?Vjo=R?@DsmyzsQ#8Ga|@u%=Xb+&W-H52~X2A?dcqhW1vR0q>W$B-mKGbvQA?7
zH8u%Tvkp_kt`)ksM|Aph6MSbiGqjDJ+aPEmy-iNc*{;{_`ubrDd;lfmJ!l=ldki>(
zRfMI25_{sNFtSV$W55&-qOa5=A0nhnHPU%B7}xx6^yGxSNC>TFC}ao@LvCbH1`j}`
zKU<6AL%O`D=~*SJBIK<^D=VJ2ihT@H=aw;xs7m!J>vu>sxl`n&s1gv|ussqm2X8g>
zY|J+{rm81_iEVnOiT$ALUd&bf>@#MmJ<M6gtGq*y?0Nl8XRKbAh$Sr?v>*+`?l5O*
zE;YAVFZyICJW9P12<&)BIMcLLF%~;IYv0U?F)X_1(<}yY%B}k+Xqu72DVpU}Ot3WY
zX;4S2FOy^eBFp=xf+0<;0#*`5+L?IsAn;?6;w@2WvrhzC@<AsXgy*N}#q$IxN*F2G
zM44v7zBz%4?jvMq3DyNg?^3PvPIqw6tpBTwMC5SjGWim{ZBprF7Wdr)ttLq<G9OZ}
zaMwTy1CJ%N)MV{8`i9H^za$+mEx$thP!{go^i5oqZcxp5#oov+I;RLu>EDnJK?FiZ
zjTRSJ&^OC$Q#{>JP7N=?)w~KRFf0wSKyyhW(@mFRi#2s_+y-}**EDuoG8GnXNDBE0
z2fF~)D$PUXQ1W;C7(yDIU<M4~UL4*1`L`KMO-Gg;1nGCPxDzHGVUrw)GP|Y_2N(k*
zx<m@Xr7nSs*q(Oldh%7YuH0KAf`dktyRZ=Pgtf*Cx%nH2AiPG6=VGMH-O+47<Mx<g
zGtXk??)heHjF>~db^!pS8?o#@Fqg4PRwg0z@&C-GdmI>;SL|E#z?c<7Q^4(In}RPc
zMeLvmwjfyK(K$rVs#CkA*RQGdEhYwh&yt*uZZC{1g(E7;Q7mA?Cb?*7i*Lnv-=QG^
zxB;~?g9smFVpIm6gUq(Ly(+hXQt9s3rZpZQ2B`^|r#FUqh)sL+7Su_4_P8`#+LNui
z2i6YKGALx24;XPQu(?!B>_WZ3fJJWMoT!|;qMPk7Vgms(5wd;L3q;RkVayWmEo!^R
z*okV&mGHR(831abbtr1o%DZBU06~1m*j$%!2&hfS{JKxGD%*iza9}8bi!*ZGE)%l&
zBk5$!MnDYKuFC!`*96T@THMc!JbFfQ?`*u6A*8~k6lGsK=}RVW%z8>9b`1AxN=zbP
ztS8<BndHjJ?eQq=u5FP;F{ra+NMr;O%*k=*=l)YSooax@TDG{oBlKCu!FhUpsSKql
z=@R=el9HHg`6@9h)!Etx>O8qD!ZU6KCz&^@Lb8^ZB^nWHqgk?Dpn=H8l{-(l<9C_9
zU09@rPh3&7+1$NL(zDy!#pf`|A_k>B&15@CXCkL`_j8trO@bj5`zs!2o|CS4iBHel
zi*`LHyD=ab2GQc4O^VAduG77w#y7a~E;2cJMF;1sRkhIWh;v~D(OH}Ae7e#pLs$@7
z><XgB?<!q`NJH(Kwi+UD38joXg;0ub0ch;YP?#jnxz}Bmy7L>~6RSf@M2;%kC`~Zf
z@6ituLeHG{ZJIX|2ru{{iCt8c)+(SM7Fp)45}pz+E{`mjmJ(UUO<Yw<&%#Q2rU%h8
zW;;a_94>M=$CN}YBG!i(DOSnhI&fHknxVY<`2TgE%$+3NO_wh}XxND9rp=z8<|4Sm
zA6k-XPL^q|trLhyGu@O6T4cc9{N75KBMC8rzAS>b&jw<)i!m*2ti#&2+0+tgBn!e<
zuPu{p4JtvR(bZI?!&FOTh}aO^Fb4i7{5|-m-w@^@g0eN2$wh3iC86}(1+=|LYERrL
znk?3lGqJZg!E2bsNrHO}@0zaccx#pD!qa5n$thADIF)0=4I{X9+IW1NAgddvbl~%$
zJw6F+BN1{BOC#JG1uqjehk{4EFA@o9(>X98@}HmOmt10R46G$zM|zR9Bsnj)Xs0Ao
zXUaejxXB7mQgwVyIHR;Lj_wE#QA6LWJRLT37b2%A+i9|c;fwY>Lyze{r@=LQ(sy^k
z5#r)pD4Noy5-$ENp#tY@NeF2fQSESo7+rXd9y0Idq&u~rPeLp-8%mDTaZo7yoz}Et
zmk-tHhZrmx5?a&zx4K(Smr1^ju3#1MV{Usz*7dSSE*Y@`+eu$#eQuA)?+%;A!Jr+e
zO0g7zDI97upjb<&=k78cXq-@H)k5*4_dxE!w=T&vbF{!YvZyz0kC}YuDRzisGo2(I
zCi6V3@`@wC8_=0dICn*=w$-ulG4H3;1)1kuyF=(A3+z}JmXh^WQq9-j(Lry1S3>*~
z)GSPtanE8W*W(S>s_ei!*{KaaS4_ceXc()<zjuh>MU6^IQIZjPd$4H8R`WJ3cS9!#
zqD`^m&z3P$bf8b^8@_u8gIfzv(GtO$)aDYXOfnH9?nuIu;&yt6N-^h-N#pH4f+#vs
z{Tn?@G7qVWR^dMM?dXtGV53AXW`<Lb|M8pTo()?TmD~W%lEay4(Zd!}6GB~*ln~Tm
zKI!&lRqr%_(cQFNcSj@S-dO0iJBxZ1J3`!dE~d_6?1ZKaR9oN1^O=ow%Sd9`*B<)s
zG=};tnQe||bsMdNIx*g0J0K+*BZgRxPyAD3dAR7Hz$>j0V!nTjiaCKaiwszU<>zK3
z&Bw<?z!?$tQG^g(JkWlPkbewA(hGYBo+fqgHADJyWPMZNTr7$1(xzK-4k?#CcPJJL
zvHJ-($sZE=4(topV*{^UjdBm2P12@->lo<O!F+&h8fuZw2c$y~_>->FVM70bZ`veS
z!hwR5iKAcD*~EI3dUsik=T@j|OOyA{pg2!22T_>_i;V?5(3uDa_w?u1x1`ZfnF@{3
z?uRh?0v3i!TLssapxw1d#E5aK81ReXGa)h@t$xLMyFrKIVWfn5^lnygq*BvVvDl|3
z4ev!hh?z?1D#3KRbc;Ef#IZRj!b$Ig*pbZY1<#XBa?jRtL4f^EW1WkR21ZQYcD|wa
z_{4<nu4#Uj&DVg5m>uh?7B|NGC^sUDNP@BkXrlVN|H5cDW!*;F6e!0WciDL-r7JdA
zF|`6dY?RwrWh!jj?ko`kQ|)W_gY5j-)`ZS3>t-9HqokiGX*?Co<6|7UgX!kc7S{2r
zNCYWza$Y_vG7z>d0w`)M{Z}EoUZBn*w#J1g8q+=aY96DQCIU=nC8KkU7N^_wYZNrf
z)P_{v&N3CrP>k_J7?hsd@jEVq7{@fSo4_-jj$V}|+!5QYL=Ep&l<uZWJz&J9E;?6~
zC+Z@I)vST8h<yx)j#_Ge608x88=U50EK%nn@P6gz-z*AEXAUr|K$InL?46Ex6s11T
z^6f+H#;Y3x{v~eB><QlMt*?KI8n08~*7%owy&p;eFp^fWaytwHTs78_#5koj5)o`C
zGEtwq?X1bp20Dakj>mPuMM#dxZS+K)*LaV<#WGWl4`L9a+vbea*RN$*)yd=N2FW`q
zxg2rw0&8dNK(I%mRm?J&UvAse6kM*+^ETR%_@I2#`ze;qMy%=$L)m1d0BoeRKmrKR
z=wHoFIyV&SExEJ8=)2<m;N(35EiMRsC<>y`;0$9K2PVF|^H-T6e<XWn7)eXpntDz>
zmu=T6tFeB_;v)&5h|`eBzH5+a6~<qMNRjR>tj<mEF}>UjFH{^t1XI(1OuDjE!R&md
z3lmQ1w%Zf10284xnI2)1*qf>@cM=~YHb?Jkta<plx_|#S-wG^CfSI^LF^)wl8t<`}
zod#R61I&;g`NB{07Tw6SIB&Ws-<?*f5@K`EkW~t)Wg30SjWzIu<nP!`z^N8cejak)
z*2QH_D7r7~+SeGw#yuA&?pjk10j=SKjLl&s3IfJG%{+GxUS&&2;sZ)oExYiny{0bO
zx+MUDrZ!9diE2swY2pKSi&YrltQ!=2uBn&&eWV8X?ajBt)8Q(haRr8pyJp`&mcMiz
z8eiBCW}5_+yQfh@AlW!`D*hV7VrZaaS=V}77(~g_*Fv03uSW<B@V+Oo&s-X;Pc53M
z&P!(5S$2*l7`NUay(98%;>#{_OWZHHJ1SU{(@F;1-Ic!5X4I~*V$tI1hg7bbedbx#
zMM>|uKT-F-gGk6}91<7}{V<zmpx0x}H%<UQy(g!+80~wW`X~Pt`8Xxpa9juUh-0C{
zgpT-`mLkqVv?*p9Nu<h4S`!_0*c*=h7RV^=s1PTxrP)uwTg@$1nlwg~%{Fb+0C}7j
zxiL0rgZ&uL$$)P#oSBAUV`8X>pr>m=CB>IDW~9m(%DZ?P2JQ`uGj}!@k~DUa-W-Z*
zFfeFA70C%!>>rx3Fr)|%lg$?ZCY|yh(SZF;W`P^-hijGgN~68dY<tpK5)?>GP@-gg
zMsG8Fl`IDRTE%5|67O~(ssUy9aJR(zd`YRiazzv+WCU8Wz8J@$MW#vc1<8?NnMpI!
zB`x%o)1%o|woDTi(<}M30ffM%mC_^)H|tXXo+7nT5gw$R@v>eKXiGMk6%d(Gf_-!l
z&6myYwiK9$9VzPCB~`iy(1u0uXb2G?TQU<2pe)&2ld<fHkedw`2FB_8znH8blG4!V
z4ZcYq4EqX5$K|o?JL?YH&wBYZ8m<#1!$#6gKoj&jWP+!9qOHExr)fN2Scz5<w4j;k
zvg`$RQl_lAxAn9he@*GKKrfNENfTU(3~_W}rDT#JezGTeeO+vj%-_&}-uc)2uo1?9
zYjcPtLMeMP-STfu(-<#VGO1xnU?e&S9+L#qRabzFc7YO4aZ#_l5(Z-(Z+SJk0E03l
zl#z@A&-buowZ^)|x@s6jGJ78a9jW$0!hlCI+a$nY@~*Ba23@w`skoTrgw&7!{y-W{
z(;bNu<S|`8MGB85OCI+u%5P#v>1dG*9%h6Vwb<7ulvl%VP}Yy4RoYb-NCDBj-w*oa
z@nrQN4yLD{Q@enOif{)UV~Q?J^AN^B8sLV_8bWk$movyT8r4Z5WQND7&wkk?Y}p!%
zj`O5<gQ83M(9C%NrEN>YSi-)NSa^;tV<d?O52UGf%8{xLs!*xX(ngO7o4B!QX+(LS
zMf=C3fsquCqi30K_VUyAfs(?U&%U@<g!%VYYsg;B7Izw#>zPCXb1gZEq4nt={If^J
zdtia6yV&wy;y<D;(04h+G)fj-!gN}@(^A7l9bF$VHeoxsFD+H`HNC*HJ1_+#N^i2L
zjd&R>%9cbg%i0?ix|mDcl~^=mD_~WL^jMGSupk;Y)G_;oSeznhVvg#!*=kJq!%kVW
zIxX9ZsXkElF?Oz*pQi!TMrxC*iA0Fh(gPz~2T}-s&hH^&q;|%4D^KYUg^S@zuxd%2
zjV=kA8cJze0P0uu=#IXn_ubx();rPz1A(w(7`JvwLRkzVlok{Wl+<!aqWo~&`i*}(
zK(<F6VnMp(*@)XGJ<m>5#4pgu^~{KHhCPcFLuw8sW(Pln{{#xt{D@wnZa{bPO5m`|
zruaa5$4sJ}BG#5)EeMt&&nr#@He#<ZJFi17*hp)Rp^;s`0Fazr0mBTPVE17D%78>^
zJxH>l6s86D*eoWggU#}0^`hXYM6VN&<QDLRSBXS-sH254onbpX$L3xYvfv98FY(#r
zMWcCaDpGjW{(o6}|L{2OyWV$Zyh%49@a&96o3ZM;JKvpMk7PNq){YUTht7;<9XVCV
zt|A*X1h6(z2sEX!TcGstz|LwmkrNqPt^+N<YROJ-3gw}81D6Bbi>2C^^b%-n!Xa?a
zh1zX7ea_)Nb(F#rINZy9eP$)6J(s`kb2g48OS7}z`TYL8KcDaCiz8W~FIyh%9>EG^
zr5pFmI8JQFZN99mi>P<j5sqGOuG4?7Lw8LtV0bqirzHkNDr?Q6M}h%l%oxz66qAK}
z@LVv8Wp?JX(V=#)`nWX;H;<`Kl%hOL_&uybNv}0(Z8o#L9C4qjgh^!2oosR#qUdf^
zvE$mNdV@L=MiI23CzS~MDSr%E;fDTy?jLC`AP>bd+RoNh6TF^&Y5L?JrqdFqgKoQ7
z%ai1)#J4DcyFZ~Gc)=?7tw9rNfotNa>4=%F;A(PVdnOFq%;=__$yNK;Yh=w9UI|?#
z@DXZ>Mcd2-P-#$Glo|^p*kzg3VeB@S*IwWGzX(kvtrk!|Lq(+?GtyVA^%c<?*RxS-
zq=yG;<HQLZDdM>|6o)EERxM!Jjh6LV)na|QaK@8X+BnyyDOgD>s1%6g><5o$Q9~`s
zv^Jw1{2vB~Wx3@}i~bkk1&&2jzNgTid*M6r7rdluUIf5%D}6eL_LS`c(%19mC2>7$
zToYFL)_&j@Yj~!N#1G$S)c|-vyDOX;H7hwZ`?*7#4ZiF?Rs*zicOrs631g(2PQ1EM
z?pBxs;M8F)9j@r0D`&;25C&~TIqmgbGU8k!?su7ONG519^~!9*$_{Y-J>bcvc;=p3
z5$n*B#Xb!-b6-_z9TzUKbc?-pD0Kj5MecFVY!pILEytqnL~Z|G7spmB<2BY4h8fVn
zdz-m!h2Hplh8w^MMCG&+*1pZ%AA0(2?uG(Cu>q&$_8slx*zbo&2;VV?LThM@ug9YS
z?U)vsb_UWi@`nY6_qG%x(dG^xaA&pPvVF-$<HUe6ZGssW1Ua?qu5w!_`wb}7681r=
zw*v@p`Hpz!Q_AC-6*VYn?AtNR`jbzx0`fmS+kh+$W2CLyO=e|P9=1kI?j`O|%*?Iq
zKrrHRCn0+;?{o=ST7){$M^wygX%6>5hp{qY$aH~_wVsuM-J{G8HLaBqdUa3*k^>Sf
z!`*<C5kq1KJ_gSsZQYl$2*QKgd?>HK`A?8h+F**()kfuIhid~jjqC+Fk*hKvsR`S}
zGdl<)k2z!vU!++J5S?<jSN*1{{wUQU40n~eFo>bFQBX|cG^`bCKO-8<!4KCAwCOa$
zc&pWd4;O1qTp<+1Sc{UZkspXoVm^9`;{W!?-ywQp6{T&1|JgHp!4j1Qm>+2XN6^?U
zJmG(CNE)VT^nQxzlxk}62Kt-{&<@36E_gpwro~j%2GH26aq@<3XTAH3uTlHYnfsR+
zLA;Ae&OjrA*hs8(i{CuBV60+>su=AX2oMJaAfo8KkW%~He<0f7gC)P}!{h*;Ae3X1
zbeYr|d&p9IfstULZD}#lO4nT`akyV0dV+P;$D<vs$C$x5H$^y$zOaAop>Wv@r9pUf
zpp$TZ01Zgx(>2MH*Hl%q7c^Vqc@ZIAr4DNp)5TA-wkU0w<)c=&{K~I<vZMpb^^yZg
zrQhpj5Pey%^z}`eE)KvDJ0KYZy;ki0V?ORVmpQ2x6%MS%@LH9*E5~FAUT!Xq4iiI6
z#S>TK3pNLaC2ry}Z>&bB$<Zou;y{)MkgOQQVw;O-vq%Uj5@7&`a#PeFI`SZ}K6{Xx
z+kQwEAcUMT?cSCb^yY$<==Y7GgQkck<P?_oUMm(){i^C?on>=UU8>eU;yo^VdW#H2
zBVf$YQG1leWQ5onWwN*sbJ^OrZdu3)PHs@*L-b~Yl0%)WevYw?I;Sy}2JTyw`_>Bm
zFFkvwsI5#m+|X{pZy9#zvLQmZ879FaWhV7oLHd$`r?^)wS!GCxd5-R(J?lrKIw&5k
zwWxO%+ddS|ga=)Wq(cwh{*}J{V7%qeTVE;PP$-cHd(lhD|9f0VGTTNO2Th)kMJ7Cp
zuzb^1-s}!%)C~2Y2iXpS+BTUSLi03DTG?~4R=AD`kyE3!l3+9Zg@(OjVu|l<(Q!he
zh4#cVVD(~!9<*iPDx1eJ4j`0FtaXu8a!G)VGS*)Wo+c5(3g2S9fB=H`Fc9_{+`6VD
zJ1pVt`0$NL_vYP<lqZA3YZLWken&7!_JqCBhwcZ=KLp_uMG_%J-LPI~$-0Q};hie;
z_zYw5KGdSY_HZl-Llo1H9;YMV02-5Z=?IZ&9_*Utn{{ez9Ygx~#fEHvq-}*!@)1mf
z@)uXg#D=P>AtNv!5y)t+eQ1XvfsLHxlU$X;5jgWM_IFP*4!uUL74Gm@SYZTIBpDRP
zuhC~qzCyn~LDy+UF-Utq^J__8i&IgiNis%xOopDI@&Xg>XAb=Z2FfOV5iTo|^@zf6
zBK8`2h>;<W*OZu~8~lAyiE+pxo6W_3YE~CLS;c~eVnW#<Zx`gS9CjnH*-f@Kh{4Uw
zJhoPjw-e;2Plhrubs5_1lzx<Kw$}Zvxx<gw56?DOFmfPU5;7?u)?&sR3uf2r$oCN}
z43tqEp0aHqisU*yVWq%H1xyes^s3rYWrI+LK=GF5AErR46&cV%%uDdG9W!bb%N!0#
zc{4OQYNW@5UQ{j-5}K-pIv=+N6JkZMb{equd2>@yeM*kwlU;-45%sTzNA1*=MFIt7
zYrL0cNn+7NsZK|LKcWj+X~tgJ<%pyX<MK~So0LdHRm4<+;oc=TKk``5_AE)OBZY?k
zmiz9J861&0(x8yt<G!?iWG`Xm9{#Y)Xpmo(VdTB7YZ%bS>r=D!!;&@<$mJeHp~f!Q
zr~pI0WxtV(?caY@y@CAQqk>LNm5J4|q+S+^Lh&jH41-&im}aPx#UNq;vL|V;|NhX1
zDYYaeqmVsFJ6?msHu-+TH}KT$gk@rIMr)KB_Q;GQx0NAl*SI&D8ijIn;G9kAoswr}
zrO3<}#w13cpk;p99jy&sFEcE-hO~$iLS`5=2vKjvBDnh%RmFj3laPE5cnIc8+?TCY
zyZO*P8*8O8z_#8gn8DW7J{pQ9i8wuK4`NI*9TfgEE^fYqpwdlB*K5rhWttWgXtl;B
zTVvqSG$s|%eJLnrW=ecB%N*!20uykZ2v1aM@R(ATLIiJRl41miPWZ_U$<UBflBG;W
z#PMXWo4@}VQEpUU0880xMsiN4z{BQVmud8wS;MMHJef%VQ&_o+#n52H@58l8MU%v}
zXa%+s%S+BnH3wf>NU4@!S?I&2R)RH_Q-ikSd|PU`rrHPqQYwyULsB;*GKuzw4D2o3
zLO#AlP|v-S_1cASCIi{TnbNFd?UiBl504bKNa<eeln|%)hr@B5HtMMcE@BO=$>>N_
zo#eoQc#Z=P@%Wkfmkl(WA|h>v463szsJx*hz6Lg_Mh0x9ZFNIcvh!dKQeE*-JZ%*>
zz$4(pdwXK&u=({5w{_epV_JJYpYg_cQrNMFT0E^6Qiu@ew6R9EJ+d2s;Y^HrAF*UY
z`i^L9Qb`ml%gn+O8*jg4AIzj$j+iu+=Ik6Pe_pYVM|yzD1}56*F|&<aGE}HS^epUP
z7`#Dc2UZglY+SMa2S47^<)e5e9q4z&w8}Hmj!h!jF9)$8KjK4suYoO`87Hl2!*4P?
z8_Og`c23>!t{ph$(a|s!HCiAr?eMG6v4mOTjH3?5{^PYu&7yHY`u|Hp{LKYu(g%d~
zS9m3K{g@(oLpCEsfd|>JN#A&oB8|`}!&PMq2u&i^4W`O62ZvpnOrc<zyho_XLZyy1
zDhnRe2XDBrd=Nyi!qGqxr;UMQQJtkoB%ta*vSoCD?f9SzBQ*+Hm@lCj##>DLW~9;P
zN9=)RZELE047I7Q^Dm+R<6EMUyDx7-8_w1+YtW_X>w6dqK4QXe*@7!iMJy&uL@3yK
zD_*m<4_4F4S-=+8YbvZyR%d1^mTj|fPuylG^-mYkVtOzwLu&91c+AHWZFE*tPu?~g
z&J>2TEg5p8q+@rON1-DRGHyD6_WI8p&Q@tzGSrOm4l-iqXkR&;+~YEEL>y+8(Tgd_
zqJE1GW_o8RT@%&2q}<+-=!2?4C(r>(CM|~E(s<8+dfLMXlmzJ9Gf;lBW-*Nh>2SRx
z=!87?+lou;012ibZn!jfBLpX=%s}1D0=3tF?{_jEv|)oZMp@G*;ufVZwm%Go&)6Yk
z0~%(p(m9EGcUnWqQ3asDM-tb~xNNX!&A3!_aumBWL*UjpxrKc}BLgk+(4A$h4>6li
ziH+)SLkWrniUs3$#xS(5U^5{q0*O#$YxF;K?{|n@aj8V$B|(d_9oNJM?;bg7G5KMS
zmLY=>Q{K>)n2&~7@Ij(Z<mj}>5z0^Lj<Y66GIO)C{mgNS9+!fo3#>HH#bBmczoJlS
z7lJ8+5PC}}$uCKSp`!c><;uA20o`mWj(<;u50|+f(lL&<NEKp_8OmIWK%(il4P=ra
zWb7}*>D-WL{2p<?QE^rQ^HT(E%>-<?mYwTxm`bfblu&r)xQTmRbh)yYIU5w_mT_cZ
z1RHpuHHa(j3qT~ZjV`>-NT@xuox5fC%do(n$}IK0=PFf3kU;ubXbD1gd7usZlWn^r
z+N@E)ZYt6%Nf;Zg_wf<c$rfg{6<9gKjgZc-#MRZ=JrpF@*mnkWBNrn%;-{rzv$2S_
zfo2<@Qw9SHI+CgzSp1s8fN#?9=6^Vo3FAiB5}fXvp|`Kx%(NvmLpY2T5Hl{7KAuOg
zDi>Fm8F2(_xMSI^R>g=hCoE1jUgNh#A`J4eA>$saa+=%%8V+UkZp`;)DTMGJ+auUN
z1|0ZKaCXkjmgR5aUhVbo9z><#-^L25CbR8~2D+o1SH;F_=7kAYfXX0y&(`a;T5bOg
zPGihwQs8%^v6?qqnLN;##d!$UQOt5mi(#IljH4-CsLe2}6Kzo9=(wF2@E#W>Sd+tG
zVU(;>3ED3_7TJ=Q|Bc`7o%##q=#Iq5=neV~6$e^cCP|OS>bNo^9keS0X%QR9nYv6+
zkR3cYhHKG9kMyTX2WRZonG(hdg@p94xq6K)_G%Z}PvTjzFpi?D)WkM?pp2>;GM>sr
zdSmW8D=cSE;BGj<Ya`#m3UGcp7E$V-$1KdE>|VGp3dIY2yP^;mN~|?9N=v;pn3cNd
z_@F@q)F`&B!(QkXa_khA;u$tx`88?QEgOQj-9Tcq4i-su-!3j<6P0!Z788_TRAdo2
z8L>8R)A<*wo9<;ZiKIhm)g0#7ul}g1Otu$hT!t-eo&SxDq(m-m)~m~$x{r9rJTUWF
zZzc}IAU$e(Z0iDBRk&$JyV6cf<oIDr!8>@$21mSx{NH1vpjsUyz^g#w7MX1gUqODe
zsm&*U4K{0~ER4XZ5J%j1O|6=HM?7}eLqs&B$7eB{nX!>TVxBU+RkMmwbPdv|W8Plw
zniIPi=ftz%gk;7HQh3f)<>Vp~hCD<{iO!(~JqBv1j@m%=2}g{bs-dcxl5Bc#|8IX~
zqh=@j3ws3;>P<Ub8J=k0H`dpuW4lCv#Jcu`5n19jbX{Es*dUxABnkD_$iC=3oNRd-
zC=6AHi3=I{LeDeC{haiJ4dbDqo>UHxhzkU#>gftR(a0UjYk0%52!b#E$MA?4Ga54j
zV3uzhl6C<;2(a3Rr7_2JnNh%W7uX@Y!G(g^AL16W8UjX%?l?&c8)nSDO66v@KvPI`
zJ0Wd>MrYnrX4D4>f~pCQk;xbkEJTBY#%4T=p76ZF`JNnJL#rVHFo8&6k20drpQ<oZ
zU0!S--FAVn5&W`9gCvoyS&<TnX%gok7%*qU-UuDZXvol<%9<MF$tO;$3d4C@aYKb{
z_5l=RzmEVPl;g#KGC5J2|F%n0<+_q1L9Z#6ffd`ZE7D~n#a?!XXD%iqqm({-q`dK8
zZsVIk!r3fX+{5aE$vq<!x6u<Ez_+IcP!e(6FQF|+>2T+UNE1q1H-gD3$V^DT3M>)V
z%t$N1{vpP@_R*Ow+AI~>!rLH9dqo~W{;+U#eNaFQ$q~R+MPxS%7B`<+Ch|wtsLNUs
zL|kCE%C5d)NJ!18KQ!rh6oC}!kX;G9$O~yIc71wguDdr#-pZ6$VNw-k5L*%C2y+M+
zMLHO7MRHyvFe-n=eZ%6YMvBg|T)2x!N`BfS6<9j2;pjA+muA$@Ap_N#%B)Ftg?96+
zUxbm86fzV1U8ICksO89bbFf*He5;QQXyRm|%o>Pj@KoGWHepj31L;_|6l@|!5sBi?
ztQJO1$hKGdihXIdnV-Rm--D!(M#~tPx3_n-JNy(|*g<r%cB?9WTC8&K0ko5U-SfN_
z={2fT2q&$*?tNRpD~Xn%9+z#naE>#9exf~M>)g-781&GaSf^_zvThd_*(PvcQ6Pow
z6&LdEsu9E>do4m7C=B;D`3E=$k1>gZBA}l9J+vmI%>v#YZP%Tj$@EpYeAEOzXNhw1
z$r}ugV$%Vjny8B@=26rT%MJ0e4ke~-XXE6u&he@d4o=1ZsS)#egPc~(p-Hskh>$JA
zG-C7eCHM+9fjCOJbJL_4*)_*7m{}ll4BpE6VALiwIq?v@)h{uIg3&h&<{@}k?V}t<
zmlq>PLJ>i(7C#_FM6z50eF;yA!^$%*gB2&UsEQA-LLYJcS{NP_v)HpzqgkR%zIacT
zF;Zt=LujEE+ZkZuh6%?_`(H*nh;k&Hb!9Wnw}cTle`KpHGjKQdpUE_w3+8o~V6k=|
z#<9}tSVAlitc``Dt>XMw@Ceu^lH$tk2;b!6r0|9o&?CU42kDkkD@f-T=uTv79y(8`
zCF0jpJlH7u%r(MX2}cRFI~`U}#(*|&h~UlFzaX4r`#PzgfTlz{=*6VVR7?Yg^bAwB
ze}T+h&Q509?PF!Kq>)+`(PG#w0nTHDHis2U3uPX7wuA4Sdv=7<@x6eh%Of)S2IZ{?
zfy9!C()a8gMQvFjk1DkcSRty+mP!mfYrJI^Z+`QuJP-+iz$QCf>+TVa;rSyRIxV-7
z+@{B}?C)Nbvxfs$&siK|g4ZCCMhDAm#O2eOcUzD?3s9hCg&2acExSOEU%}Fmbq>pw
znML>(|FVK2`?ADqa2iSVPKnIWrL*D4+v`8~pV1d?>Ecv+TkLy@)pqOMBO?qiqsBO9
zh6aqt1SivLI#+mMAQ0-vnB_Fi7_|>rUVN5)0ZNC1`>(5qRXMzdQy#<;XR+cf146Xa
zM#X7(h5f@AehGWtX0Cto_1=NvQsorz4i7B{RncCNRb{~&c|%X55E}|%v{VRUEXTpG
zT9|3+7K>~dTO}5x6>=)j8Mf3597oE$G9rBxz5n6#nj&+@MBWlW(jM}XP9#Psi?NYW
zERzW1rn_4|yp-7)5y4m4w|CXN%2~>mQzWrRe@!r)tbLsbP2`WhT;#7z(>3;<Xt?G<
zx#I1B-&&CBT03(dR6po^vO25SC}E~Sv?7ezaKP*t%_I&{6a(R2%KV*(5la(M;&rq9
z9ypX40tdW7Bkl*FHvtkU(A+8$i(+e54P-u(yFOs{k?#{>hHMd^LD#hbenYiA*1`#5
zN0(jI1S>k*{EtdI3bKjP%Ci8;2q!kfLg=RPcp{KeR4m^>NrZyP8<r<qVtak*ojujv
z*r$i`I=lMr9dVnOXV*4Ivba#5P-3r)zZ|M0`dj{REz0D$s#=j-$yLBZl*du==}c$=
z@eFnJAtpwPtPi(T716r~@z3(7w@GvsmB2h8u%7G*Kqo{UHjK0XrQeZQOJiF)3X5~A
zw9Gvi+!`@8M`WV|nVf1FSH;}2%aM&vWG4)lbVkJ`p|<PHmj0m9C>~%?F)j?n0E#{9
z%J$_xPQY_Y*>yM%;uuWwhESDM&!mVOT9Xo-G#v@T$r3lrPJ8|JeyY=%b91HFnz$f~
z=a2P`QNbQz{ycWq6Td15o=9hADMm@123KoxWZ3Yvh$gXFN`Kro7qB&t(V?z>78);G
z>K+1CHu&=Z71lUpDOn!jTgJK)>yyyMBf{dh3i*V)nRCORZgBTAHQ_Ef69$DsfoTJ{
zAL}zS^06?{bS}*-v)(?(>VT3=wsw7m0HGHjtROuPMK>^|w{rv;9dL!*0Q+TRyzz>w
zIGSL9{*bF`y`~0RXz`Fi>LJE-L%uo&3?3$tl{3n*eU$SueR<m`uVs4&1#*8i+gnWt
zw`XRg_+dzAkMx_+dV_+ZeZ9lm7^p1aG<@JZ_0x!EhUkWnnQ~ysrL05DqT^~i(glS;
z@%s(73dN{X-%x@=`5>LL2MQj+*jpi0d;MSkrrp!qUbgv$Y0|H3R+x$~a-Z(q*So&g
zPL93PO3KJeS8rI>U<lN61BO(G*0^iYs2en=%bXbIwzORgo{VMW#MR-WSur1?DM|n$
zQX9?`dX<hT=q=G|St(Qx!4);!;HeX3c0VH+c8*Tg@6mTq__YX~9|p3{TtOytn-oJ?
z_gM6%?{I1FXtf@S)^N5=t1Ys5RSK#0EE-EgwG0*&6m$M7ZX(mP%L)U;!PjsU&h<V%
zvw9#mRbU28j$jU1jVd$Po5u0ES9*pIouDwuzQGY_w*&m6+`pw)m=qNf%hwj*O=OPH
z{!PgDdC@vi$SNDDrIJd6j5niEo63&mdx)c8M3X3?lW)ovL)3m}*&SYiScE8;Xm7Lr
zpg~DgjLDpWt7C>FYS<9^>{<LDdAaA=zz1<`ve(TSJZc^5`>-WvC)r{rd)mfIvsYOR
z-yV`O{2F<OBF6A0BX_nQ*|%%5M9L@Z%#s0Q41ObZr&kj{b1(kNC(!YUMX+ug<^u}@
z(+d%FmIWfnvbeXaRqM6C5{oN#Z96VQ(qc^WuD-i*xcBuL7(bp=xFW$Y9lk<}{q6`Q
zup1CD%Vr|_W0-15hB<j4EANpLXVpm4gXAvRhrFp)zQ7<(bXP!B7plFTX0|&<i6pDD
zk-}l2Gh`ui_#5I_laqghC);$14v3&RPL-nsc9;N|4_maKU{`y>3mMUFyzjZbowa+c
z;Sp{JuXlL|uf?Ds!fgdQ!y>^I5@uvGQC`lV67c9)?V{!CRpe2E9f?n}&*v}bxCY<h
zGNPCTG0+izxvBAAdQUbeMq~Dc&gP=)tYP3NXE1n-P2(<-&}0hL6T(cY<m_nGVQCpg
zzz}pw61h17m>hou?MHA$Teh>S7bD(+tDFyl1=*}cWHA|%d=bW8gQ~0_(`=yTEc}*_
zx%t`Om3R-DkOcQNg^cf(z-1Tve<k_oV^Sj;#yj|*C*?CG6=sUtMeCS#!>w5XQuq-M
zXp15q^ONlZpo7#K87sknamE4Bz#*qjMeM@Gk71g4CdE@@qO*WkXeg8LhK)f~TxiHb
zYl;HHt=Rfs-@1!*E31dLX?kn2-;zFn85abYo(PO{mJw!2Z<ZW!Fuff8aI_|kuq)z|
zcyy}uvtE6w8fx??-?Z7C%ti%*QyDL@Bn2Smii=H#fTV&wrDJ6sR?96UOcr^T{0&lP
zrsi!2@|&wY^&CM%oD3FxmsOaw=z-x#5WyQn;W7><j6jgh4wPyD#YsQ*Ncw^Hk$uql
zSq*t{RA8I~UUemME9n5S%M7Hr2uxRj)-5sakcPq_28>tcO>o4d$!n@wBXesDa+I-o
z(`IVl_{}W>QR{^n^QN5riC1|8^k}KiBcwM4-qOTpiet}I1UWcsA$$@8(pXZ2`4u^a
zuS!D^TMpu=h#aCM$pzbGl~_YLT=N{0ppl$o8}fodEN9EuSgGhqCXpl{nHZK>r{oMc
z+TNp_{977WHLX7cz?{MIZ14MCvn-<o`#F$Sdc80?n(T-WLFJEtM!i4PEUy^Eqtc)e
z#uf1`+?ul&j@mETW-6pSR~wjTy!%(mZ?X-*9n2JUC%GR1fk@k?KFd?f9|W}wW^!7Q
z&@q=7wUKZoTd3y$yZ^{H_EtSJ*#mD-+CgzfEE-<|hASaJJ@{m^pM=%Qp_FBkc51A2
zC$>-mO3K9p(cuG-o}K9I+mTA6bUkp!3BVD%(J2@S$6Z$gPL~B_pWg1RkH0he!SfwR
zB(^vU{d=U;zNBuK#w&K<ZA7k&`ModNGJ-f_@exOsgx(7siMlAt$tUh%3tSDvycf7;
zjX68$c&XM8*c88I-!H`z_RGtg=sO_JJx2=xUUNHA0+BMT5R(H}v&in&a)s|=gYZIf
z)mqQe18u@1p=*z-@7_k2XIo|^kiN5n$K?!N`dP<}`@${#hAR)a$$oK$obbYJrSQlQ
z#vNrec&&PHO|j!GtWQQW9(Fue-)kQf0d-2`py!m@&;Fu^Y2lPnx(L9ag6-UDGvv;e
ziMC@&dwm6Rk|&8WDb_80`_k{_vaDOWTbIo~0p*I+koPo43f2}0$%IQFi<m44x99Q0
z{_y+~0T;LA*fxK*&Wr?$SUX^PEj0kH<ucA<9KF{)&2&K^j<PY_0Xz_u{1&;CH2buw
z0CJ)1Q6|4aW>L2d1^Tsr%7&Gq-k5V8oBmD$3icM6rpXor1}lpq_XM3xijIAPL928D
zTaHQM)+AEZk04c6Oq-KICqW1@JRmBBi$GRND|A|anb7<wyddy$r6t<f2)abSjoy^v
zHM|jWE`lKG)aLR&^bc&$5SfEA{Y&N%VzWM`RlRp)#B9{=>-*N_i5-#<UpmI*NHhVU
zVVQS-RAIItTjz@$MVz&aSnP;lCxFh8rKZ|{l(E4(O`sB}xQld-y9AroTs*Znmz#Ke
zG8cZG5o3cO%nUvMKxW7(L-owK<LqR^{M{p-J3@1t1SMhsGRC6WBLc%=$WiJtu_}64
zZn4jD)@53neE@x7e58Qt@D~gYsO$5VF>G?Bs^Vp&@F3#ME6WJ7p4MuVRd?`$#s+6M
zb>r{u+`xuz&3BdtdYM8!(x{CDA##_Ev=Y4rK|qkv@e9@)<c3DY>WCq)79(t<fDE$7
zlD)K2Ngi6MNv(Dl;s6~$^X1A+rZ%HQAI)VbB?%Qv&SJEhBr{ySVGRH1cMO6=9kUJY
zK?KX>NXBlG3q(2?u&hcR0;*+Un&9WO08r;HbGFzFM{!|-qx&QEqpg6!9CgdeA$Cl?
zAcB$MCLrT2aX`CO8Rlh#VJ#WmvMYE}>7?>{zlFHmP}YXZ_O815U(*fWO9m>t&x`I1
zhm(#`|AY-a9`yXTn`HtbaO8H|Ie-hx&zWM`F?=ERL<2Yqod<1+TO|)HlT4|~S`C6R
z^0SlKz0I{reMDZs4TCp`dj>Om)0-6{rhHQ+zPrYw46rC&_9`O6#g<t<Y8n-0*^E%x
zkN}bNIMW)2q{1%oO@<g0zykk4Z<ptVGSP%oPX?b)jM%b6j8qD%jvpyg#+BjJTnuYL
zFEe}F<D5uI_UDwU5Wq^{k6sLmJ>lC8qx|aQ-vR41OY$g)$5f8UdRXn%T$9yhDI=mI
zDotfZQp=(Fuav*SM$R`a0cwHIJ@1}smGjKO-|FO{58BQc`ymiMiVlbYXVl<8?seUe
z9KF}#hvebvGZqUKStDgTR}yW}>8yMvfkTEgZPM{?FVi@EgqWd6MGyq(^{tr|Mp4N@
zftZ1Br6h3}^vQ0`OxZ0Q3>bc}TEBf}rh#ZnUpGfxXH8x`zs;osAFma!sXjs#sAWLK
zjXK0FA_}M}_(H~9Ihy-z8b0;YIua&+6RYPGOnvW;k)X*OMm?M8C1{iM93xa5okGca
zgcAI~b&wZ)oWK^+BzrBYRl~W-*?0!SlEW+?yw3Q25)`%qlIxAoP;c&Afv7in&Xx`E
zJn&{d%q1PM#$}@iIKUSOOTgH3z#CM&`Qfc1jo1~6VOUO=X3jm#){!!Vm_Hs~>`V4%
z<GIh(vOXoo&hmPndZ>l-I6zMggICzsWWN@JB#Vo~O5&~wfM^r6f=&m`%2I($Pyah{
z#9>U*Ehh$FQWs)0Pu$$5K7amCB$!?`9h<GQna;@hQhjAziV!w}gP{_GBhMkSNz8>5
zVfP76QK-Z5FngtQb5pH?5r^#A-%d!QpQX*1gn_{@s#Z}ZK%Fs&81mFTL6papyR^_~
z)+f9@mGPSFW5W*q?B-7Rjgc$c1P2BL-aF#jdvPGNIBlYy1hKrzI8xf)<et&kMUMu#
zIA)JDRVH#!r=H`?4HTKa7CCH><DBp@;=Tx=@VpqV4X(j5WZSLE(j>5?@*o;)Y?>nf
zWDAI}$F+BxdZ4q3cbB=%H96U(KQjAp&{+y4YR;i+ovc8I*%*;f5RJT{Zm@fsAURh#
zaC=2Y##0`7&@K`AQ;9OP(uG>``I`6*Nm?a$<D+{)MrOpdLJPH(?h9mYV~3|0K&a8v
z@lQ?MDegf)5J$@H(x1(o8aITW{gW20nvzZ95dSTv?x3F)lQgM9Akw)5lkp6;j_l+k
zOuobOW_&9X-!Av<goat4H~yc*<QDnF!O5#CWRn<^-&a}Pt&s2LC;m$86%?d=*eB<E
zkU=F^IXF}1s+j#*Jp=)j$B}I~iK`4vCLPPZd!ABN|BmyctB)D<I9GBow-Bejwgt=^
z8l0>t%6P~4WZ1`I@ENya1FnFGJRX5N>_rNRO%Y5{Zh5uWf9O}<c5f&JRYcvR-qy6_
z92ZT@z1WwxJsizP(!j;2Bt%IL9(|vhFlH(T4scquY`dw0%z(xbyQ=*zxpZxKd8Awx
z!OJ$xF$ZOXZ7fY*;^8vMgu&urgjH|zfBhGp(+W;ri<2W^7zd9!T46d(lF;!qGj5D0
z2aSV9q9yoyEx8=;_K$ShGo7}MYik=vqM2o_kav?H7hiHFEGJ*}T_Y~WhB`GmcG}ls
zS3BjnW1+DdTjOZQjZ6OVvVO_(CQ!Q*d*Q}lw4l$2<KO(suW7NYV@zi^Z9EY=`k7!n
zHyp-RKDbLu`EV_r*TK?5$XW`0-3p9@QT}ovk8<T%PcE6)wbZYVf)9jo)o{R6KjL((
zyR;oi!*>cGn3`1>A79W5MLQQPgv9sI-MV?aT8Ov_pC0GZ6bxv*|4xuPOV>hGntULD
zG_v+I4OQZ&muM%JJzdp&?7O?XL<=lmkJ~dzVXuF@V_?6Wpp`i4IH5LWq%dE|r5xbv
zkN8R3NQxc3>?TXwta3CS=e$}mmulT_KK9G<41(R165Wn9lWbB;D|syqGYO*j1B9H-
z9S_F&sSxAaUM!pU^FuB><!MJE4s`J}9@epQCB5{<M}ISbeOywa#>C5wH{YJ!h<Ax2
z3i2H5#xJ-(bmp5vj370*mlm>JoG<c1b+fNro!4Id{#+cUNm_6gsB&N-mQ1_OJe08i
zz*Hm+rjPgu!D4zjT$PKQPsm6DOdY<?kS<gaL{9XG?MKssz0Gl0vF|20VmI60!TjaQ
zR4d3;#vP+RKK|tD#MN}fIqoJiNmBF$Eq5_|O2yU3qu4DR{<N1~UhT$@j!!IYD}KV6
zcSoF`pW=+w|3R;tKhXU4J3*<97eXnojW2vB`m*tAZ<22F2ie!a(0=%{w80f}bB>dm
zKWpYb!)6z63LeBo=iw-Bn_KF6czI~t&Wj3KX>!S?v*B{!<P#DUt)9p8#G^?ep9&;}
zQ0M3MI9b$pI}}vH1>K1YL*|0@tTDFarw5IA#;cB#q3s^7U7l~IX)#})PA@rOe6V92
zTq=eq|3(jNE2p{1guWI1il@d3cO}82MVGsUIV6Pjj3E+L-#8fNydcL%Kgk;^=%0vs
zf`oZ-h_T4WDC?0#Ylr!g85>q=X-ViOVK5bi%extp(Q!^Wn2ZFm3Pb#E_|SQsUeQK6
zXKiz0b0W6JyUcQybIRgaOB$$&anLgDJc`#2TgfS<jk#ey$R}Fi&JZb0{U9|8w;x&4
z0tYSBwB0_2iE^%)zod!_hLg4p`YhT}E>`vY`BZz*Sq+b`+HK?1wh8mC;g?aW-A>xg
zr48qxUdSh?)Ezuf5+FYZ6DzM>@*#ZcbPX(C0n_1X-CW5aV$n*L0YaLB7vut?9m+p6
z2Q3NmUfc5Ju-OTdP%H0fN0PP<<9!tMH~&4%chm6wx^|gME#01nl%?jlr3DMRcF+vR
zou*@JUfb-L_Tdh$UujQydF7RiY92NyL<~Ejl0@@^JfE1Rg9b(baGu96*!jYpfxQ5`
z+M!o-;<HR;d*h2g!O925r|oVoh<zT@PD+t|hju(X<1`Sl;AMNv+B%*;^GPE~OH0=A
zX5=Lfe2k1!_mn1|Xsb1Uc-13Kw{90hp<s-1Q)k$KJbY@~NIf}CDlWck*C)rRYx%|z
zVX{9Trph2riaP=3^wIQsdL??q3HepS|5csLExnA^7w$-r>M)-cnuBoQ5)3gK<3WCP
zUQg4Mi>02aQa<{U<MOO&$xvRKlfrLw2*un>o@Sl0j~g-TWZVHl0oJ6AHOJ?dsJN8O
zMbPns;hM8Jlce2m{^bcckklWD^)v}jL0?adW1?wh5++(%7j@!aDF;a8_=P;3n$Sy8
zj?aI}$}4^+;k$IE%FE)pT~UhCnsTan=Y<$sraLJppNCzK|8-r@3~vEng;O}L$7!LW
z2X~&4`=qI6r<l|`c<MCxgmWap((`ZFhlJ;1J~De9al_(*KCG9FwjL(@`V}2bkivgr
zwe^yIicnrJICrHtKe$y~+W7Pnau0b5ya|65#$%m-?xl&w3Na}fX2jGINK3N?a;v3n
zeh;mgvs==6L(h_hZ6c;I`L|!q^}I}Q#%}9r@YYL*=v>tyw^r9BcF>Z*!C2^aFs=uo
zIj-;R)3>f#rl;9Km}}U<k~yoHq>u`3ir(-ULB}XK;~rAv6~=SW6UMp)Bcb{6e$_VI
zbh(=QYEod}ZR18s-{A^i?|$n4*}_}f^hQ7<d$r*3P2h~u4ZxGz+9C>+PtKgO6L(d9
zki>zGm$7cI<Qr+|Ca$U*R22whP@BMT-Pk?FV29mm*w{^_|0#uryTg%PJ*^5)L`R}R
zr^PR=;W4`v@lLHiV*j@pl!jB$?80q<h)USU5{kLt$~KM(597R(7LD{c20>5V-B!>F
zwIFhGo)#k}5H`wX4kNI5aDH$~6-d8%BzY>RgDNB8F8>Np<4XQyf~8Ahh{M$(ZwQ5}
zrI4OD%jS;5u&4jED4e!}EoN+caoisnLEXS~YW%I$qg*L6Fz<;hRV+l?h%r)CJD0|2
zZH$;>SCe@+;p)rC!vFE}%%w2R0`36SDCBtBFvy=WwcSiCv^3^d*p&2=e$ML~F+qjR
z2D?3;H&WAdd9olEw@IQVTLo*tU}t2WrMr|7UH%PH;K`=*3J+$4uTnBJcBwc`y^ua}
zDS=v=7w#sA_5$yX=iU<tZ&?H@Obh+t8B+_1KJ0k6**2S@9VDyHDKltxu$|F1Bri`P
zFL*e)T(S<YWi%Ed=2%ibUB<STTAd*OLN4K3H^F$O>18g63lKyIRSMJaT6#yOIFMNa
zr-V<0@DPqA@Cy%*BNW8q=eoiPPt#UYZj!x;%g70o9-i_FpdMOyN)ZO(6&vH?7_91a
zXClm{gT$c5d;cjHyf4;G6sB+onv-<hrW2ZIYrIt899D@u&ruk<)3uJ9XNu<?BmzZ<
z`5?F88Orq%mLxA2#!5BLmJN_GCEv4V7EH97TO^{42@V5e@5x=?l?Gdg8stq09#ZEk
zI-Ryd+}a2k*d1=y!0d@V<3ntllrcv->jjtyuaH0Q1vVK&81NJM!`mx3U!+r3vZ`UM
z>F!6vaQfQzFL>tCPg;7v(@adWkrZMlwtpyGGOzaMh;{n?C36uh+?+M*VSLnT?)_xb
z`aI@h@2}2;Kadn3H^Ud=DLbw&^?mbd$bgEu>1fuU8?f_X<<aPT;)Mv3G~0Wx;+xV`
zYeei*@+Q`50T4!Yn?<BK`(%_4-5;Cu)YzK$1#5Qgp!Irmx*9&yS~Oqwp9w#x;+Y|H
zuNNovD1P&!@3QN<S$V(Bm;24M-b9?bQ=GJCH^RD!;??zM%oCK<?oNs$cHBSe-0l9M
z`NggM*7UtkjyT0X>)YD28}{?@p@a42jJa(0Pm?HDIYC(!ZVyxUvUc#aaucs>B(uq!
zlP^sB$*$obU-^1xWb})z$bT~0_DBa2X{-%ScB+S;_(C+W?UC{2WVJp$oa~4OC;jvD
zed~^@Pe1L3?%+t(sl0YW|HjF?8W&AEp>(Hi>RoiYYu{F!o^EPgn{Du2GnrYXJ)k)C
znz=aQ%<VDL<IURE>q&EBZq4MnpX|8J>E@B-g}ZM{U+B{>&vj~kJogJ~a(u26O~-Q`
zBdHjR)^t^+-PB0CmKRMAm0GJ`%dYFRI!T4Ux>K|<OpnhQi<9FYR9t$-Q|Sx8?hVZ(
zFOV9~tj-xKo_p4a=W6Cd|8g6csGc6GhtmtqV7h*PWS{W6kD51~fxo<bXenyE!nBjE
z>ARAFH@0mv3vb!%jyah$U##~(ywIh<{f6T_|FP<Mem3@lkM9Jx`peh)pO3iW*MCy~
z<AoRg_q6fZx${cZ$;7WbqO9&hcu^V8|G26&7rM?x6&;Jy(@}T&Mfa)2N1ol44y`)_
zSH8=itvJX0>4nmW|5>hI_x->4Iq$I5o&NfSasK}JL2oB-dHkVh#e8Vcyb=Azo`+_d
zFT2mx_!19AZ*ALNx7P<RG-l_*=E9XJv+#OsPMOJ-N8`pqJ=VL^f2uWJi9sr!pEjv-
zH_TUKQ{V1%ANi?rbK!*J0bDdEp0Z|==N~@ARabr}gc?_V_)z1;-+4c<Q~h^UC!*43
z=eqg&ifSxqP;8vXs^dfEa^4Gf4&88@kDpa_I-fKbegO)cq<^ez`1O5Nw>ur*ANl8J
z=Gc^IRivBag!8rhe)=k^7oDb8zx_wf>Gi`q?(406Iu85I=~zp<)8^-#=4Dg6V$<7|
z^e>x#x~;#-Aex2={eXay)N@ZbS00T9gegB*-Dx&HS--9O$gcZt>rVgjefpK@Sy00I
z;m1Kwx{u5bAyF>7P+oK!3*9@1jCzi*j~p19e39XS>)W=!aHsFFx=Hx7qLQzAy?3$t
zh1ns4I_HbsfA+lnkGaf?y7qO`u<DUw`LXuyZSM#Uo56J4k4S}fdgU(dN}Nlt+@{qh
zas!MDdTQIFWY;<$+)tO5dCZw+`=tsGzGUf;y7A(n@8aHfG+wC)ohM@emB|<9epgx3
zaYd+I=&h&`<4w;i&xOuKV~7!T=at4l^yvx8H8?LV4%q^)b*G<=_m5Fh9s2VZn{oSk
zX#S!~zqH)6+>;-;qcOrd(m-Utj?o|22k@O*3P~62ff4Zh2k8O5p3J!QLxgGWd(9E&
z%Hac6arz%<+HFpK*=;73oY!v|S005XbvAxAUYxr<@mQyZYpuVejJ6?eo(0V^_-Phm
z;T1gQ-!U4&n5AOghQL>Tj}D97YT(Un+hccV?C=3tgI2CT|F`UQGn=ffFddtA(ujk+
zT?+9P!t{1HO{wNVTifn<KN*|j<0}}-iM`fh^JnYU3IW4FbLXMkJP!EQAWdQFajh{M
z<XuW$TI2DZD)2>EHAdv=E|W#A4(=a@OJ%m<DUBH}>Eyx-Uylst6|VGMd9-@A99H14
zK4;zdgM2-HM|b*iy&oB!$RQF0%;?o|h^L_s7IN7(!*G1Ee4jb~NZ);K811#v{vRB1
z3x}qH$)B$0ys7(iXoA$aG-)?twl@NaHXfIsXta`PLzD4Y8WlJpRHH1xMyp9EI_m-u
zb?@A%O6DjHZC`ILaBB5{b~1Tm+dzD?^Jk6AA<8gezq)`RcJns*XG#Aa9O5MjsU;@H
z{IbI@h<-^0x^^nk+)&$<_UnbG0XLwGLuZ7q*^Hz)P`1X;L>gkY>*>-l>M}!<m!X%}
zZq5=sRuY3yY+*3hb&Q7p%8SV8VwYGGO99Mv<3o3)4ZJz|Oprv*L{9s6C~&B~GHpA@
z^|RzaX5whL0Iis}w|;@kSP5HA$Z1J%?+kJz7B1m4VBD`pge=;VB;0xba!6zmvIbiV
zW1{?BaWEZei&xk3)}K0TA<h%L=HC17zoW6AO+}zscp_gjk0jlt1Kj;lf;BCz>!qe@
z>y<5q>3x1<nz^aZ->+4QxmR0xZO#ZL5DLR7FtV}cYZYa%E>9>_GH@D~D-tO>qFeQO
zqfyn8!CY|K3toRBuVVV#rmKE1rR<a6mn**ZecuedhdM`{*Y@$v{T&?q*t_G$=1-&_
z@?Q#P=1+8g-v4y5`1<r)UG?KL$#4Df4-Vs=ert>`*H_>Ag|T;fL)XLX>pjlN@U5r$
zLG>*s{m|%3;fMFWKK|Cz(L3#Zy!)9J?>^D}5r2i7ee4gfFj4sR{V(xl`{Fmamapf(
zv7Z&lUH<vg+~xjG?{<6l{r7h{Ir%MXxt?6xyv_dXHt9F`dZY7(bN)ko)8a02JGsk0
zXKQ)O&z@+z-@6U(|Jc7=@rSM_>qDCl6@5Sd=AokJvgN$>^aIa%Kk|vYGy)q^;ah*f
zDj3h^e*!t%tg{V5(#2w;W6Y+KZDAe>c3>^RrjkEd#2Mt|8()G=($dWA2v#9ikjIb^
zEiAjvJXx62ePi)^xwORX{;d~M+k3g2-`x6&n7;jzo0f=fnWBI9J9bd@ith@8-0GQv
zL!&`syg2T}P9Dn#j1cODamK3H$m|wkpYV87VB-G04lqv;87a-t8o_Po$H86IsTHj;
zJ`B`DT<xj0q=BF;Hc%xPRh?KrT<o0oR9Luc(b(myMGK527u<Du>9?AJ5lp4P2@Ma-
z2(<WD^*Bv}Tmpe+NS(Tg8=AR->4(k_kAE`EYa{bvzCT~EZXW~m$?`tZg9+<d-McIa
zaY&v>2FNRf7CcI7#HlI)(WXyFenjXVYsd8@{q6sl8`M1^jwC3KcDaz>Z4&sW68xuA
zMECJ|%^jPer4oEL%uwM>Uo_?*U`0p<C3AsSB_6xnF^+V!xaLxC@axX)G3oh1Bg8PY
zxA?rd6vgAY5B>e^;b7A~LTv@`@(eQ~ia8=pht9ROYkpTD=d!Vv=vea7-DbhpadSTX
z8YRQCk3bJz<kGpoV0T-hEgGpRjOWquQy!HqgOzmkF>~NfV$4NVZbjb5$F`*gcvDVm
zx5kn*@jviCmvpDBgOZ;CGPf+}vT4q9K-O-r&rMv{DDkUBqo7{`{o}XJk+AI=Rxx+P
zDj9(n<|cHp%!bISF+iE%Wge}NpEo2S3dCoUMa7q~b<QO*j`8v9k=|A<6`%aTcizvI
zpc%&^m&?Ur33TU+ro9->Eb&Q~eP_&dXTmlGWUbG<qoAAB5y*htn@7SU=4d-<dbSS~
zS@7svEp1seVoo1w*X%-mbiQLcpYXdeOVAF|_Fv7HR+Tz)WTqSCfh3Q&q6hu4&ef-_
zyZmClnv%$m*lOPyUmdsp@$VPNmdODNjxBNzco<5j?U<g{!x8h8bINw4TvYR#>G?RB
z2!GXa>K`?Y?i%bEwU|_ES;{xN=lM2_SLpqqY3OMxPY?yL2Rz4*wLvpC$~VW25DfHH
z-{K+c|IJ(d6Zc@}&!13krxjX9l7z<a#WnB8^qN&nt+(P2ddMHIgdCGK?KVq#62ct>
z$<&X`Yr+}oNYb3lA{a7QNOdhP8SqBl1y+Ctc%?0xrC=5or9?<uP}a6wyOS7NkP`#+
z<>-Q!sP+GQC@^43F=V|PFAy2z?RZF41&}dKtR(<%U%zA*e1nP%#iEk#Yo!i|-b)sV
zEqa#XrQ25SR4raaHdPv^$jLYS1k?p1rzrgRv6VQflg@W)9*C;;jqp3#NO&%AY+asq
zE2c)He?U8^2RY>Y9bH4kAc_Si(qpl21zl-Qpmefp$kS#e0^<1mX;X~iQjHx(R?a(a
zdXp)11C!9hK`ch_)(1Y}SsGA4k+y;^b3e8BCuWQ&@wr>|KC#gN<l$~}%Ax2+W1;*6
zpY8F*sZnS&+5}oS(1M|Yy&eE|LlGCaWcb91sh4!^y;veACbMUf@hjXSS}+esjVQ=H
zX?=C_J4?{gZZ{n#U^#^_N0J+aPY7npCx-=!J5%OvG$C<Jtb&w`c;J$2T;kAPKDS^;
z#w8kYK+Dmy&q8lE_LLVy4@8k;wOGX~9ld~}YEH#AT-WuwIhA@|scHHD=f4LYF<<Ma
zdKc4^O%d#pNw-UAUUf!f0f-h<aHtfXFuOc&V1uTBI%C!`ud+a>OZid0L%kFJ8Yem{
zS+?;QXfr>ICk!WS&+CKq<?K@Ji^*NV!{ZV~aqY&dt;6aPV>tBV;lk2ZTcfPePN1^b
zUmjE$fl*dbr=<derf2TDgYVE_jDP5R!JWgzx2Y%Go-oqO-f-w|akV2Z;^PImo9{1k
zdqIn_<Ao($>=+Ny4#OnOaeI(?2%pnX84M@pU+d5DaIvQNp%$zuZ8r*HDMPx|3m7x_
z>v@)|%^W{w8P&*0eAd)%wyHd{1yb%R?dC^+iKCNwfJ+YKpniaFEaXajEKI;+>)2OF
zz&~VFcndyNzMzyDCA<912jzq8Uvi5$PFz-1&1L)diqR9HHij^z32k;qqWIq5qCE0I
z9^h~~i1T5fn`m)K4@852=Mm}ELauw8tbi9}!02Pp4IW4=fV_fuTTby$zRS(yBm>&Y
z#n)ldU7Z5&otpLPTkjYfM;^Y&?Ni`c4K)&z14Ip{j_X?R9@yH|gOnf9F{=TV`nzp4
z<{GoX)2&uWl7xivXu&uf3ydT%ym^B_NfuC<_7afy{3r{I!BZW|wyI%$Y8zFfEh2OT
zx+Ne;5Ixh;Z7Ymf0J|@QlJb5Q1IHBKw6iB-gb4*RXTd@$y+oc=i>vWv4;)>7g_gLh
z!s4`09G@DVm`QH-AKcyDx<vgy-5MS>r_TWNjOV9-UXcq*2NrtqJd>e$pZWgq#HthC
zzhusXkftBk9pEA2bhh%GGQ({hD}Kqo5hagBjp`BQ|EQ|&Rc>WX?M4H<#oAC~{GjEK
zzE+|KrXTRW$`)(YSSj4Oe7PHqI<v7q_m=0>r=wxgmx)$%Zgn6{-D0%YKd~?IE5&UG
zxcN-<5C8T1>^)&~_+5aSTWNKEK7Ne=AzrHAp*6#;`qDfdiB>x_3Ejk3Kj`!=Io<d_
zrK{VVL!;DxI3@_;>(B8wYJJ%rTiYvBFKbn{#zqDJy`mKG84>{EvB-H~@`=<10(29%
z@W^;&dfb~oS{t7{f5Kbd_tByS?~>|xw0GNZ_!HN^tlTAQcd=~#ZqeGeci-dXvGpAb
zXOl|bsxy!0Oi$SLC9~+{o#M0vG*gFCklCg)7Sh*QoFbXy2-%}f&f>z*+3q}VUpBWp
z^dDLUF68T&-p@Rd+|Uf#uj*5e%U@L=qtFKHR%ucf1dVFe3r6thJ%xPb&NP_=SbJ3Q
z)E}wdz8xs68cdIePdU>+9y<3YmFT?1ek}jF>~C&6chOz{`|6j&<~RF~I&aajdx!+|
zW%}H~U=DdV%w_k`p?>;=-1v8_7tDT|v3}WH?GC&FvN>fw2hg-+3S84qSC8%T&6S_^
z7(w}P{m^-H*v;*1vWpL-YHK@R&wUP(d^Sso%jeXCML`$XplSuuQPMp&J{|9DbtiuV
zxa8R41J{UI9(mR!p|1fwMb@WX|3Rm6(OOo|KQddn;545E697u9pJ}lP;M3~Ytrwp4
zAO33nf8}0JHorP_Bl+{o=Ed6j7cYFyZkpx^=Sz%9F}t7GW=luy6*=dzJKY2vt54O>
zn&1!v!jXr<W(+Rnu!r&Fs$Mh~!mH-h1ptimW@D=U0_6&M2h%=igw@XWSv{Vxrz4)*
zr-B+xk<KSTy7MZP2@f89(F<Rr-0JyVN>eIggGpJtKRV0Id;q40B4x~cC^Ej#T;RO#
zKYy}$4-X$5UK_gTuRFy`XMOImSG{IU@XA-he!aVmB{t%L=0bn?f*J7tK$st(d(X6F
z;q*ZT%cSOZ8qmCSym^`4vgTC1yUg}%SC9E$tLM({abgA$)77m2bwDhFsK$cH##usR
z0nF#{p8>K3oyi4nhS+JpapjT6-GS!pLoK75=Sg2&exE`d!WC7!QXDX50k$ssZ#s57
zxPE_lWag)*5ub%vTb(*<c3IqCyz2$CaY%+^+crxLWo&Yt9qk2u9=0Uup_GhnIvy~m
z>xVe<h{kpfQgZNaXDz5Z1i{!|?211E)>#Nu3jR|t8u8bDUv>Cp8EDmu2jyFLD4Lq(
z!ksEj+mj1(k3{lrcl5K(4skd?y*!t!|Jk9!l<NYwu*=PCEZWdg)1G&3gHVSmdP@6y
z)3lw&A&svky<blX?lR9|IVRM__SZ3c91g7w$gX2R;aN6*PQ_(9wJhVyGyua?)|U~s
zKJ_9XRRlcNI3Ux=K{MGCuwv34CLoXncf!eM-2u>5ZZ$i5%IC1-^0k3?#Cy@J=fJ<Z
zxp$f=_>CQ(HT#=WPU91Vx-`0KZ1Y9{(^Sma0I?|!qn|1dK@3#Wg4=;N_R;kY6vl>a
zBdO;+_iQGMvsYeZNy6LuUM{#;+v3%8!9P|-0^X<E=EdrY*?4hCec0aql3J;Sv3t+x
zK-jtXTlt5=FapI5%|^;Lodvc9H5RTsTGtLSX(}<>dOgt(-Nt4s)7mb!Am5)XIcX_@
z$G}xA?$9B02DQ>k=gc-p<19cflBW^DmW(t;5Vgu(4fe`(3{f0#G~sEc4$)aNyr()8
zIbV%BV69MV5BsQA-0maa@6yN%dN*FN)(?K6fxvSTNxM1DR-h}7PWhnQxnL;*geWCW
z4!Wg;^Zg-C43$ZPC6`BmoV#MEH=w_(D**)EDIh`8c(Ipwy6}ku5{C`bIb`3i(#nd`
z=02^Svl_5{{P12s_@)Pz^nsS@%CgK$Pop3UmArG=Yb>PU;QE7q`09DxE#|dFlrKnD
z%rlxc2oy*xleCF602>L`EaHd69%v;T@A7ISmGOzZPdacH(1GtjB2X}ovyWqmSth^$
z*(>WTC@b#|nR%t+dbibycSLkaeIW81Q8l$*A0PGnRZlBAch<&2Z@uLoS(u}sgTq;D
zj?-M_j05XAdayK>VKEa99$hcy+cTlY1tBo4PoM&LCTju9Bv@~#v(^T#<_7s6%LPX8
z`j6*XU0M-TZBefnDWF?n+-Qss=B%#aSi7E<Y~Cq8>ILx4zSqAUTuo3Yfz<?r5>)M-
zd+*OswQq(t-vC1W-GQU_{~uiKe+W4DZ{Or6>~96<E_(kq#P{y_n74uP{oA+sH-N(E
z0U*Bg8~*tXNG*Ec;z^^Eg?WW|uN{Zkf6P(Q5DwHoWE>g0bmcz~wfJHBoo+*J>4<|>
zZ9SxFAQ3jN`gl(IX+kYk<R3ILf}(_l*T&7+2+5Y$e3X~$ciZ~)L&W60pGk<>dm;B(
zTG@*@5z4mw;M-pR-=Fk;{qtYXF9b$FBs*ejM~L=O@MI=*i-`+@)U?mKrNq^@nRHZ@
z%qK(>*v?=E2F3YHZl6J#%yK-c-$r2gwZOAp1{sM}JMw9gqW8=OBrBY^7WG%g;_>*S
zRo~2qbt4QztI_e@i9W-+#|994<G=kecS%Ti3B$)o#%DF>UACLjPapyPWs4?#`l%e+
zXr3d1l4CwQVNP*6W>^B($_Q`@A2^|`1<2wj$|YgYP=atk5rDTR$G59)j`q?Rswd3q
zsBMe)<x0lQFa8R8PNzZW9HrX~vga|;+jPyd#!Q_dW^l@Hqf^?cep=A<m_YxC)hF~V
z>25o5JK$=P95f!Nq4ZqmD|zS`W&83Ph4F4DBK)s_Y3XjE6}s&$Q0%FpEwk1l3(JR^
z%mE;hZ|mI5^mOxm^y!#MVc9Z|TX$$meVlF2-KNv6)1K6x=fU*FnyaaKeH7FM*Pw+w
zw{~RJf6xyL3ke-~`lz4yqqRk9{&D)n(^fTJpp#Ce>eO)3UiDM3f$?c~%sTHD7ir7<
zfnP!xL5wEIjAO}06UH6hu^2u|)^o@=U+z=yv-;dEN0N53=2RDE60N#q0VoQt7QF1K
zts%Wpiz^mjWiS|xV&ya%uE4bF`L^4!{6s%!xK!ctL!o16?dW5+F}j=foD^yLtd(}6
zuZPhZ5M*kVq9>E|=Chv(yqV6JZq@UJanGG0!qzU?pVSG7OU<+}alu(*XtevQiG^G~
zvBYzY9yb&7ve^wk>fZ+PY&^&DO-bjPQyVOG)<#E%RvooESlg=7BawE>U(|!w$AQ#V
ztW(@svlHJxJ~OY<WfIw8V;3o0G6t3At?|pwkxn?TCer~!-QTe*!(eBZ!I1y<*S6pZ
z()e;3K4s_A?inYs>0JmzkL>Fi^G}KFlH=wt4`?C1uPoMIWZh{JKCxVk9A@M>r6oHo
zj?W~;_n1I|dSPM3od7Rai)PN>cbMM3g5iv&H4by+=tB6VUb$!)V;!Si)(h36Y!CLF
zBvGgAK`!w8#e{5MEgHwmh739%@tm9PBOG&?Ym67-@d@c|Tt!}~0R{PC6Q(em!l30$
zYtPUsU5zOEoV5Z^r-2LE_k71m{Bt_Ko;S5=3<X~<k+hZ(`XOC&+aS<X^ty(27M!1t
zZX1iP;C0r`uV3ITyB!#tfFfL?e+TuiyzJWaT0#uXYSYUY<V%>t<7<RO;1Ekr2xwdi
z^KG!P(50wDZ_0C4j0h)TIr0@9-72<5L&aKldzVPiw*sklRARCoTwlm4+F@$^Uq1)g
zoSbCePTiS7qoJtOrc%vCL9hncogPxI#ac-vE{a>iitvU3x@90aDviC<!6(7a<mZ+-
z!slXER|Q!B5!F0eFAM+l)+)e6-bzCnHWM00ks_pO)!9amYM+%4&A@uX#cH(muCchK
z(g~e>zfp|Nj0P%<oXZYfPI_RR8uF?y`<EcYu;EYi#fIn8vlV;8M&O5>C=D-0EwjCZ
zs+Bu>DLU=AM^^AGT4BxFH{03m{_Da)W6p4$n2##tDawby@Z-5sbCu``<xGtvv65uM
z4af6EW0c-lAMB^3mvyi@m-A=zwi_8*k?HE~(8_OD+H>xgRWb&MWgC}NGEh^OEXK9w
z-L~Psx;L?MGx1nxr{>h!*xIn~vccD%@y1$XKAlGKyZ<8RY@JD(skYTjX(21E+FF0!
z4DR}*o?fDv##z)+M^^)Mo1a|K%KG9Yx=2KtV6n?aa%!lbumq#RhiS_Yy)A_g^&lWH
zeYl!Rf)}l%y3e;7o^-$_N-dV71%tO^c2fpMlVAG}z4INW%dR6%-3@7U<$PP8G2VbP
z<8&k?I;b6D-swa`ZWxU(ghpvbT>{n=q;9x_B@PUi(_ReUa$LuCOM9GCMa?-iP~2-d
zpHXhhEg|R?&&2LN<r`_iKdN%~Muh*#PK)kWx*9u6RwFv7dzKe}>dIY6-H{{|nGA9~
zMOO#nvXUSiH|c2uc0;#0BqppmcG1pXa<(Cjme$>?%pg~sjcVoSKz=UoYTCY+7$9gA
z0Kiz>=%N{QmTdPKR|P7vw!LgQUTAs9R(?KGBhDptYJZ?Qy644!euE!FfRo}~X?iB6
z!8S?f(TKJVMWsfKnr<^iguuPdAvC9<zgw8}lL>zMlvDpbg}9*|^h6muLV(7X93)z+
zE~wCW%27H-Aq}QF8oZ&jA{w2mj(0|!%dbX?HMv``CQkaP<F|1>XZ@qL9&2%O!p5rD
z3_ApBOtkQmq(paVv{KG53HoLoIc<7@8|vm_q+`boI<8bnSLHP{F}^o6__E8xQK#%O
zDUCQd-GI#?W^RXyladju<)p&mlF}-hGrYF(j2j>6RODUi*B)pToyr|FrpDmdDFu|S
zex{fYkU!fg<SA$=oHPv*6$?Cd_n>PR1y}V4k9tsJ?1tH~TFbaVw_~_k0)mapYZDsz
zlope=MX=ydF9C6^$ozmb_D^_WH^nv;d^7%t_fbFBzt=AOoNuqc`DxAEO?O<_4~R+<
z9ZI)j{}Z8OnrTQTI};X{-O_15XP>E;Q7WcbL-k3>QfxE^3aA$@I@);z1`yX(?wZeZ
z53khe%lnrE#u$qn^bpfVo3N9>;p33gHN0T`orAAhSHr6VN6nYF)|+RV&zQwS+qSM!
z0DI7UaBH`joG{<z+`m+uGncN~w7ne!P;~posl1H+)!>YK(rtBiRg+x<#gAHl?O*ke
zI<2zv*{h>_20y;!cqgpA#h>y!A09a7O^znN<^54~wTx7bmTRNCEE#al*sRV)XL6|6
zxjMu=htACE7q0r@e{t8W6Z@W-@qg^khpzcwS-$8Tt0~5G@{WPU5Bt{3YO(WqYjS$g
z{B7%x-FUP(n;c(y&oixkuRoErRC=#+ue)pZ@vD)$YJboQ?^RdFC)GoL@LdmDcZdIz
zduX~_Je2m^KjT1RCx5m0L*sWRNuL=W95oL%okvXuTuj-=kD6bfTy?h|9q~t;FRpoW
z$NY~Jjn5<_LuqYCvS)ShnZDwb^DEXTXH4gWN`BLQr)$q2-S<)d7q_zMpmVI|)c{k^
z?Xiv@wLUsv6o2tO>5gQ=`dKGEx(`d?y{Vk-ObW00-BxmMOCLKuG+~Xu?$!Jqo#DqI
zX?M*(VIORsFaC?IPS{^K&A(30TpLczzf)Izb+LMM+q&Z&w?1a8t5LZ%b22>U{d0Qg
zNH_<C`3%j9;p^i~8x!1RU^Sh90%X4ZSAROQ`WIJCx)!F)t!vJF^QQ({ofGz4XC_H@
z$ikBQ&e3i(-M?%-lib&L-nu_|;hM>BzjoRka+{y_@8L5l9VHEdkIg5Qj@zW=Z-`Gj
z<MH<kznJ~q;r`P@TQB;+mCs7{2!JUKg1n_WRo!+ykv_q1d(%-HRFqD^uRSYE`?NnK
z@7a3ok=wUhuk~=wX3?BpIP^Q_lJghCpqwLzrVjyY9SzM3);Aqz2^8>8w)U?k16MCM
z|MVXBxjl`<KA9|=_kCVnTbTU&`b!qud<SlrAdxTjU#LYNt5000{pCW_t)Jg>@-yMO
z`@$)wvaWce0~RCgXiUN%y7u?Y15Ckv{+Qwf&H>{?t(85)Bk|D1+D|*ve?~jt$d`^c
zpWV4KRCCV1*IL;FM*6#gjXtnaKE7tneY!>y-e-O^qR9_Yyjc757mrT7<#{_F10P)b
zfZBh<*YAy<{mLrvCjcTi+lbmf`9%1=<$M2SOY!hw`-IcY)9^IW?B8xa11c1ZH>U>N
z=0f|r;4}lUtlvGl?a@PED*}JL;S3!5Zbc{3<DhrlN#$-IO)ASZtNVU)|HCgb$bA2s
zj^lo}Y+7XxZgKL!kh;2H(q^>a?*IHKSFD(hH0vF6@?ay4SKg=CD%t((NUd3ozWomi
za=21!%=$yd+&=5%eBbzM*42f{uQP;S0MCVRh}+M7n&Y*Xz0#X@@oS?Bl-dIlYJN4m
z`Q!KSk1=<<^U!LOPT7e=b0D4*fOP%uukUuw^aCO$@X&hRS(dx~X+NWxO?Mr?ao-+A
zlUr3k|2a$dD$9M{=~wKb=#i1LR`<@T{><_WQ0!x_t9&4@i>fpE3hPWFS~VLBaH#CO
z8n5i(j)1o-WqK_KSCj^?T%L4LE`A!^>HxssBav&(R$j6mUbymyp8CQ-ohH*g1Ke??
zb~0@K-A=XtP1~N^%NNI@;qTXuxOe;gNYg?f=vqGt2Ta;<4&6qO(O~YRl}O*=L_fQ6
z_0r7pp<e>Cn@hoVsTz1At_3)2^qZh!d3wKo<GmJCuB<5K(I3a+-Fa{+VM6^EQN*V_
zkJ}elRO%86d+)YZEC9W-qDze8U;Wdn;k$0*<#=ab<7MSr^`}?%Y<E(Yylxjg4!7T4
z^v?EO4sZVF0VbPT&w;KJ8PP)VoS6dP_K&+s^OJC(JH54Ee@?LVtFJUaiBvV{<?_%V
z8X)uKBy=uXnD+b5jQ|l^=ecamxZAS4%CYkDp5ah%|24~nSuRbeWvU@N6wPT*dFS0{
z5>c}g11`CVT-_&EH~xONq7olHu-6JMdKXbs^XpNEcHCDFAkSuvvzwY<FL%~$tMZak
z4?p3mKYAfQz!)DLZnFMdaVa}}unUr^4O~ycX^>Y$=o#cl4S@wW{GZ%m{J*Td4|E&X
zedjwfgk9KGT-=KRbOBKm?!^EaKz~etqzcJ#JOhFjXj3%@qHJ1qQi8G@CC#RyoV0e^
zJ&QXSSbznt2#RW@*j<wpoyu*pwdAxfetXVFq~v3{ab6@j>2uodizPdKZkxVXa@xAx
zo|pF>%5l>)-R(PPnHb_9V1Svqe?PzP@B0Jj1Ftp}Z<HhjK)h53$YMB3E8&FGT#t)Q
zv?H#Ix(OOorxcP*teC*lk4SZB2`d+fnHB}(ck=ik;$R@Ccblj~YGU625v%VJm{gTR
z(nv4Cv&j|3`=3nE0B1vYzeNvzHSq9&CRqd@L?>7dK&KQ(l<PsLGmbfX5>AUC#?y?b
z!)gMB8^RpHEL`Jz2tL3Lbf<Z;1R&hldn&0#H6FJCUu){TfaWi*@r3i;B&{^1h@*#~
zx?$5197cXT!X>UOdi0RtR^H+~Tk%RhbJdiRiRGaMTbRv62<a4Yj))ih*M6%^x)g$>
zLDiC)RHEfe;ea=%oNYkO7{MA*iF84KhmB@G@CI!hF9IMM(`^%f#s|hqjWx=eXq4-k
zg=S)BjAGdr=oOobFet$5L*r1wIweDCl%U`<AeaqMYl)nNm<e#CI!{W<FT8h?r?kn~
zP>tIN&`LT!0vdz8k;+Dbak2(+n|T2Qw3Q95K>#Hsg^CeS1+#=&<5j3qN?bLdGQ}o2
zF>5aA=BQUwFBU(a2gaZy$fDtK<oepSD3o{ti83Y-it1&&Ji|Kb)#JDjy~1LqTMWMQ
z%pXm>@<>>%W7!F+ia20dCT$`yy>)g%)<^>0bi)q;is%~BCOEaNxHt(?t`GX08<E0{
zhZ-D!`XH&84P7xQIevn^S;bVT_7~_yA&TQZZ$)#_wmdOUqwGm7x_Tr$txd{qGK|9o
zAHhpYnI}|#M&+0831YTXFh2ry(?@3cFGoN06Upqq&=~$CrQ!x(@3_IcO0N;m*DOM0
z7+V!O`XWPL`S@c}#ZQwPvdJUSDe@zd$E)<8QPrp32cq}>lW_9i3{@eM%>HZY%YXAh
z{soy`XZ-blN`S>Fh~D6_g#Uc9$cxB*```<${>JwbJNtxI!%roE3*bTg+ET3mzz4q3
z4KyJuAhC18G9CM*egOWj{LyVV;Odvp{QlXO<-g?*zYGP-?;rl~{=bR$-?#Qpf4J+J
zV6!xVWSLUro`8K40rQJsz;!f7ke+1KwVIPMDk+9mlX_;G?D1aa(a&{5n?%h&12tsI
zMlP)jc|f4qu*uWssr9;vUCNMVApd5<HlmN%_ScX$Ry%4gnIpulxR5MS<rQskmWHs&
z3q35N=ks+z_lqdo@79Z^eTrts-RA_vcUpt1-~LutC;-S&3Ls-ovJrJNK7E@66^NBQ
z(_@3PVQhtnNyqKwXn`$*KbX(};3{P#FJ8#k$Z^W~pa2=d=|hVFpj0hJJ?seET1^!S
zH*r0X&!}uG2Ej2^fiBvbbU}s$01@_|9>4anPazX95Di3Dm~G{;gDvm3>vlhYIzEM|
zBy1I2nPYbZjKmD=FadjwnA8mH1=~fJN>>eO=Y*gu@S4;{i*!UCqoZ5(klQ7bMV-!N
z=~-P^AEvL+Ns%btstgPI$Ht@^D$nB0np&2RyGiXVH6c&>!6$!8NteHDaH3r*jbOZ!
zb{&@lqm{Cm6Z1058A@VM^+x4Z#xQe0q~+BHWfyW|S9te9{#c$ibE!9qYFdXF<g6jV
zIm~5UDk7XSq3ZzBV>1{5IA{n`6#J85t*%;G(jBy0v!sPv1|Uq4A8S4ACb~9XTl%}R
zj8rKoLqfWj4Eq9OpyVcD<zg_#5y7G&K~;$v4A)1mby%#6GFw9BhwULqT0+|~wvd-*
z8@3KuU<uW%yRPUu&!WLh-axApUQH};FMN=x_7?yLF$FY9&etyT*#dZPQxnlo$vJ99
zz3_1+o_Vh<?JisnuTixH8=^sKM<LN=&0HK^g4Sh@*#e?O-E3<OkX5TI(_wl`qLoNZ
z)a9i66s{9USl$s^^~WMCJ6RVqW=(WuZ1c1(u+<RJr&-G`uxW#dxYp88CyGy^h_G1B
z?gUH)2nNhP2hdcO&zrKZ(7U+}mx^r<*VCD55v3TIkXMtpY_9V5GMiI6=g%!O9&Or?
zyL^-xIx?mt5}VsoAd$^kHV?rVuh6iXsBqDe4hxm{^KAu|9=GEzzl6Hi35T^hY?{NY
zDs671rL8P&I?N>BowQRz*yV0&?z86v!hD(+ZOU18n9KG)cUX2ryqK9~A$hg#Rc(M2
zVw#nWRMdrQn~Q+Rg1dPX2VTKV6twuxNB%Kk3r@-bavuEJ!skU?7plbrCMUsYaJGar
z!iUtvAlE#ZC<@hU7s+wv3%x<@8#jBKiyH2<^vJ9JpoiNS5W9Q?B(Q3sirp(jN3>NN
ziX_A&n!L*h3s4b|LlbH`UzS#W=f&>;x0a!(dO8Q;mg(5hQVe>dC??p123}(t$h8NQ
zM36gp7y_gc_QNYgN=uD0l?`eMHDPlo)%4jk2oBClVhon7CeYq%{>W_ct1{px?+l9}
zL~?>A658El5_ec=;+?<zb%jeskyfc_Vtx$m=T;elG$2M5%{$?<YYd30#JU3mzsZYq
zziS0+#0{4=Ys!QH77gMHQSoRUQ4`hABSsE)LiM?Cw75p#Rp{?1V+!{P4LO#1ofeeu
z-GT6z5*@xkaCp2q$}N^BWxpSx(i2F)S}XLZi}6&Optynfcx``F>gJaKv6@=9%E=+3
zSY1ZVK5mMhthK_(-~u-+ZF99~V7#f=5wT3*RiYABtGap54AC6NioKh|b2G6*5_#5e
z5hzka*Sl8~3aDOFdyyFrvV&>H7cXL{q%x_Q(t=+Gx+)q8bD?Sl)<et)(IKGxx^&&*
zms#;3>j)r+h_EXlMp13^0>`S(7_`Cm!7nXsy|FY6*HnKEy%t2tGY#AyJ7`RcY1+O5
z%VWb>G87|S#9*nBr>2z_33h;|He<L}EV}H|sT3m!NkeF;kvY?XSb8+m?G|N`;Iev@
zdBCB*!d6j0pJT<AW<5t4Zrq%QXQ>oDNYxMMzV6j;d?xN?utrT6;|E3!w0V;z)NIGE
z21BO$hj6DH32_BqoiSv{Zw(&tV4af!$iq2F*4EgP@*DzEsg6i+jqrtq5IvY*77ar3
zVZt~DN$}#CJeSCK_QERp3_=N1B}4QIcA=xiM-WV-<>P!oSStbn-V|b?Xe=rQQ0}*i
zXOP{ZB)F8eAJMXd9J7KS#6)wjx<pHrSqZ`}(Mnrr<-ptt)xzyVCTGXwSm|P5HR0yJ
zjL?Fjhy;3*f995kw-D4!xSXr=e8P>pFh5qJegF{t?FYZ{Gm6wP#Xwvy{fm!$U7R}_
zs4o#UtYX>Jlr1r1Te-+wb(BH-Z);pPbdk*o3pV*`djF!OSu6Roh|wfmNlV4R1h-Vf
z&-*5~cQi8L8YGm33PWPqtL8##s!0Z4cV}4*Y*cy2F6$+T7;Y?v(3x?k7#8OioMN<^
zwkoPtbTa}au^&!Sm0nb7HbNlIK-vgOK$zJGC~4jBgEAV;fI5?4k{W=jEtgb`8r;H#
zpD-;5Z0Ym`+)c(yo6uk%`vK0=KPt4ELGDLsR%M*%83?I|f<|o+s?Hjx73nYjQ@7SG
zVd~sR=v^GG2tpyE!|@_gCPP)kUG-S;lAOd{eQgDWoO?KkZup=PY>;x0wkIVzfW^Ba
zW!0BF^I0Q;^YsI_>i1^vApyM1x&>VTXXio1>}!toIlo&XcntkWO5l=v!1P7j3)<H7
z%`i0iqzq|iF_SXnRPyw3Q3~mkE=Qa#d791AUi{Lc<mS{(TX>BiuY&MM0JbH>3~5;G
zD5Be5;QsLuwYzI>R~Mb5PZK+q1Mk0;vL!ECEElIpkWSOOv(RaTt6Yf}i%=EGi)S7s
zuM73}bF(ox1Z&S#vgyYK47-vvi1X|*p9}BKdi*YVU4&!#Z1OeQ>HB>!8NM+WJt0mW
z6u-`<;+M_ANxl?)PsDr7-{Gy(oV%ANlh;KLyszVV<4!tq>ENT}GxX(wjh()!<d;%5
zxrYyK-=2BR94sU^CZm11E&OSlOy#%dQg`s%seLWV*B5?|)*RnKb`!<zy0-WUz0^h?
zBEsOGkTMAkf=A^cF6*$2iUx7xV&j;zp0+jAY)h9rJEA+FJ!F>`SK=bKB`?!|A{Xgq
ztWSDl^=ri3yl(+{Ks$K<(N1zL|L~*RFLNi;lU(aAyjUbp72b)8cJ9uN_3*oKv9r#8
zp2sW6NdFzBpXFjIJ4M%CqA2s!-?RC}%jR;jk>imIeX)ZdsR~)IlGwh!@N6uMZzfN!
zgDCeB>Y)^9ReX&erl~3>eZiACvEkmI9tsdoLbQ7vVL;?>;Q!;$-XrLWy(W^D#tSjb
z_#FGox+8#STaGAfV~>j!0z?bDPq0619mh=*Pt6ki`0P=i&*o!S5q3!(<!Lsaj{(qr
z+-JItZ*BxtEg$orvBN*^51$Nr>%Ri5bz5xGmHl`HM5yi+30m(XT#VXNZ2W)!;Y&b)
zZ*6fW4JUhpevhshL_%nNiZO?Tf=N7)ClAsE-YAMGmJMvO5Ah}7n6E$QY#%WpH1+PH
zX9{m}r;|Oy-eqyJNwkXb7xM2G3Jq;lk@{Car1--jC^7%o&)QxD(Y;taB}Px&Ar9w|
zfxH&f@l8%pT={a-As@*dsaG;7fLTU<b#hZ*V~3rcoix7rzrnxq-dO6t^Jl><hpusc
znCzkh|DE$`^T-t^w<&oT>CcgCeNYwd{@T#rLS_-UnqSNvT3D+`PK!T2<@}edd)=eC
z+bh4DZ#(}Fa9rijaW$Bcy#8m8AAq-3jzw|=5mfG+N(pY?12G1|ObtNS9vZnduFeZo
z(}H3R(6xU<7+lMtcZFXlbU~{ZAH2@_CSb)N^3HurF`fYM`h!OS(5!cXYhDA$Strb;
z-0k6a&4TgqBDmJ>k^3r($;SAe^g<urV0S5dk~DCbtTyn6$wd;q|1*BF_d$J}ZlG6P
z%~+S;vHQCppG+<nB5&e~N+dw<c!4>e^N9~Q%IK?DVw94LVJk1b@{KjaY7K%}qK`K5
zFZP+Nfe{Db`4%)hHx~!s>`O>>J{MO(9s4#rcoRrCz0|cN_o4C`dYY;0`3~G)kf}D-
zsbsTF7n4TnI-c+*x05TZCq6)5YZlo;@`x-J&rs02U!FWeou&>XD~y5b>C}$F;z0o{
z=uF;;{MzUq-Mwl%d$M>Z89Ci|y0H8F&>vDV&Nt*2`wmIvqUk&ZKy2hPi+${+9#<Rs
z&7{d@__sGgTPbmToQ}b!8Frm2&*1!8$isRvhdVUjTO9+2##JEhBb@kkC6*$K0(|WZ
z^|3mv_i(O=m1eY19H20s0fp_mLxjdLl%LEWa=l0VP{K=lesvS>N$G(Kjt2m{<0R<^
zBz#mK+lV%QFX^8bJAs(V5!{g52@d?-p+MVqASz`cj)t=pR9H{p6kb|_x2tn^#uaL;
zGI+71B9)lf(EDl3;E3oW!9IemSz|nmWO=em+H<%QVw9kjGM0mic5f0!1*U;Sd6INB
zeIA?MES6;{8|&TO;W)Y+UrV=|XghtPr47tdXjH){AIYQ7`2Gv#XkQFX)8RR*GO!k&
z!MSzfFu#vGzrq`AoZLk&H+P?^<rsnfH0hksP4L&x5j4LkY|@HaVHE7K%iv%C<}E`3
zq+)^}!&8b1GHzlHgwe5L;5T5hCKR1Uzampd5tHSOGU(>GM2n1^6jmjp99eMUk%hd`
z4{F&Qa3|eS5tjC?^F(eCAh-IiRCXVaJPPXvBegrM4E!cu^(zrswTJ$OW0ik~FC;;!
zv0?(@A8jFkg^&5-eA4)X&xwNNk0v4fr-*OwMHeLue}tg8Sp$&IAX+kx64KZzqnU`D
zGC(w3bm&}GD8BU~r=enRAae?h1Lpv7EM%yg(a7?!szEsgE<9lAfsPqc&CwF>@SX?y
za7Rio8+hdYopCj_&CkC7KZzh?JAam%gMMwcCPFvxvk3OGND(Wzn)3o$k6o#DYd0Jk
z`V8&|Dl*r<@{bb|a&X89nS36Lz5aO8uK4DfonpMoQ<`<T5>z7il%pgx-Zvn9b-9x2
z;KL4dp+RH<qsW!|?M6-QWVL7+2004?%n~B2dpbffCL|=I9BTQqPdtdL_Hkl8^ed)S
zsvtrTf`p-o<uRKPN~BZF3di)@#ur-(g!E8#3(d%0zklOA2`wYTrd5?Q6vy2Javx+q
zCua0nsv^moQZG?t*f;`&Dw&Qs3jV4I;mM3A38Z6f2t0Da>rK{|8TLd$meo?v=JE|=
z5k_R-$r=nN*tBO_8a8*>%gZsv!k*ufi^Ouf@J2N(ZP*CX<fufkrYJzJtBPlGP>uMx
z_gGYwWibe?Yok-dniv2VEP|?@l13kE6Q+gAbxq>$Gex9exY)yg(og<~o6Ji|gey86
z*DH_kj_fz1Wha?cXZGRTW_jWgHdey!a6GXCA}<h6l~8$N<}G;oc7Mk041)U}<>KP6
zG47`=tpf9BlDj7DzXtO3L#hAH$EA<0s%!tvp!0tTE&cz0kWcG7SJURVLR-7zOW!<W
ztm5AdC47S%^W7Ut*NuNAbAChVf0}<^{MZcwjDK(B-xq(5|H7B=!>#}jLs2jV`H$Ek
zVW%WexjP3vZJO9XU6B7{^-lDf{|xM!u$eMz{+`NzK9U;!|Cx;5_-5Ef!ES6IZ)k2q
zL5XL9WCG}h#$Uhj3jc-vULIeG8;8MnAJANEw0`W%_J78^{@B+$_r8{}$2OziLE*Ds
z!iB-GD3*B0&hr%R@sx@YG9w{WJs{qOl%x)j>4hdcStOQ;-dO&5E}?44%3R)Rb|HTY
zwTRaiy?WhlOoo;Eb)9EBhS(Jry1##=B^ceTAO%TFH~S0|Jp$6DmJq&P7_A#ZWS6V8
z4lmJns)P8T@Vv9i$DzC#4k9q4)-VEr9&kd1&a5W(!!rU~axbKI^DzDfATlZEInAFn
znE*^P+k^e^s4As{wAUPz=X9jk25MZ(mrN@0dttU=%T#l*Yo#Dh+F4K#Z0>M7q5#HU
z;UA)<hJM*qr6Ox85J4GsuMiuha0y_bY(t}t>$%0uPmuaKRtuX1>|K~=W9PIZWCcMR
zBLPJllW>un;U&-O*6yRKl2+S`Tu&CcpJR>;3yv)j6oC}7`+1r`?Jv;C`TjcQ+1jL?
z(3mJ$U%onwp`wjeMOx%$c_4a$d0VK?qD^uEy%(r}(@@UL+TdQWL({N4F2HE+kj*B5
zI#4JMGQb3`k6(L7^qO)M=!o{1w3SB<dJV`_(s~!*kyzvq7MT}W(RFm+C99WxVvv>1
zE`{kPw4r!*(Wqlxo_=o~_OiZ?>v(r65M>u=T}_Yzlfvs$mG#hV84}H3X-hF%5S~Eu
zonfHBa)HYU+R|!^JWp##6%xR<nl!yOxC$<_i5u7EwkaoF^Dr0bV3wFtvmnpgTnw^x
zzWfZyDUff=`U0$~n2nvO#NemAb8dU+){s}_a%jA=*)ErF<t%!frT{owm)vD6iou9U
zK8~vt2Tc@jAh@V)B{&!5Yz$x;tO5zR0#gnI*gny~hDNa3B25=K?qEVK<jvL@Z08X(
zHlx9om^BM6v22<XVTx=np_ySpO2;7+lV6aUoNyC^YshfbPUJ=O6fL1XZnElraZ@kN
zs&p50q-ykG=oOLFnktXGu!JaJkzGC>Yjuc14=@$gdPGl>rd!B~&SHP;v5hW+y1iA;
znYE(@)}pUVL<NOghdS2tLPpqJ<e>}5p@DfVm@%##K|cIBT*<mS$jp^~FX3V{ii8pG
zY`3Tvk0a%1P?fAe3)xOToVw}c$gC;<!?#r2*MK#QyU?Y;Tz3JQF{MtLst*S6hMMTs
zCZN*vb+Hs3x{g{-t~!&!?MDm6KveSEdgwwfWE645H1s=+Ie1&7oAhF^N*7oMm}4-9
z_Mt-mnvh)0*Qju*9=z{A-ImbMwBhK<5RXA>azgbIK*ZplgRZTb7%LF;r~%M037SZN
z*6_J}cvRQsxrfAe4}BS35(E|USbqq#FroqJ3d94zP%&KAB!&=QB&-xLOq8=yyNmwJ
z@l_}R8EeodQVD{o)^CmeqXJ%;kwsWKD@o0QN2rRv<R9wB0Gq%wK*Ov6vDCU&0*x}I
z50ZhxAoj#l<p{W6LNn*N6~GwcZMfbQ4m$E8ht#)9_)Hv-(NJJKrxHx|r(u;4G)OPk
zk&=IgP_ru15Prq-q+9D1jD*01a7k2jXq-Y^6t%fT7uajB@V1y3*sLZ#PQryq8+yUQ
z$fWxX{A=P9T7eR@0N`;_D{<rE%g7&wNnVEg>vw!wG)OO@UWDf=jwwO0xPQMx!D)gi
zDqUtoQ<Mp6LQjn(24d9t3h%`f*X@RbGazcWQs8XFfRMK<5amFeM`<7sW|d_Z0!>l)
zCeMMNjbLq6lSO2lAeZ3VANx7Gyv+KIx_yBFO<R+Evwcrhwjldn#=xd}I*j+~<Vn19
zYk|YM0T~@ZxTn@I#V~ZR3AY<0J^CPEfK57PceO*T4mNx<8QgCu#6!U-OA?Op0+byC
zHbO>&K}!mi#)K4n(zWnGYW5nK{bCpz)}HZx%7rC}lA7d(0TyOqDXZeU;;k?`Rg-Fr
zSL)0fr=h_nBHpzM?ilUiVJ!lnDrd~+<RXU>J}O-?37&|moGK-Ci2=SWRFFLc)^YWe
zdJ*mbi51u{Io^<|={_ulAm1L=XlTrf!rJD&fBbx+T)N=%R70^KsZhACj8fJh;GKk}
zgtm^)Bz2HgitC)dz-N$6fR>6(LdJ2i@Tvv0KxQt`P!m6UZ@5@PMvK8Yn4E}&t0AHW
z{Edz>0_2EgNGP~fw>^xkc<uMT`BP}jT&kW#$4BEv0NPUw007<71ya}ae$TSeO|r{o
zVhXdNnm6lyIyqWB#s;jfb!wrJY!+$?UCgJ*_?kiI2TN@becY?#1|p#lX%PYgH`Y5I
zQUP$`yus_vIY>j3b`g;g5J-S|n63t~j>0D@YAv{WcpOW7U*C&fj0XbEiw4tAD~U9*
zApS3)UPf1IOSdY~I<cmX-h$5t@AodupKTTTZU10v{8&eAIp5F@bb=vHR6Z)XLO51C
z`ZQjI>p26tYm%t#!7ekg0v!t)Q&U4&vc@|I_o$cw6y*S?IYMIL1&V1wdNs}WboSC0
z%!F7WA>0c8gCbVx$zDV~gXll_$k=<G;=XMr#^{<rj3N5BpUEIR>jx1qI$=zt8q+UQ
zHAN79(mf#W8PpS1dwD^u;}cRSAvF@LO}f!<N%gmqm>V*6+gwI8sHR%CpdXimg?TI!
z(0t-z9~Y27BfSQT0EwsqRLcYdC+y~LN@xkcu^=e}5j2Hou77lAh>*w0udsuiz4G*u
zjKuB7;>CN;k@d7q_LEMe5DPo}*etv-pNciE6OmpP^bXoS&9BgE?!+bZi5F)JW{;Uk
zF3>Q!PRzMOG>zJG>o~iE#x7APesf>U>D!ih^pcz^RKs5+Bz;R}wveZp-SRMPhcCqF
zA$o{+w!PiaHu1y!q+_!BCB~(!qP#F7r85ZX(i6*@hv`6Jnk+|;nQus~$7rAHzLyWa
zi4K^j@ku)|7#KO29ZSFU_5VW+b-Is|2Mh8vHxM0}rXGasse6!Z@uvb-ORy(!f17&S
zr|5fe(Yc68_x3Zn!U6LPpAvsLOJ*~Lm^@0pNDlJ`T&vuv!UE0f8|5LI&zsZacDa)2
zo(!j|;oE6vd+IO93Sa9!OQd5)t8T%2t~z`2O~~u(u!KKq{vK@&zG&h-9sd^;`D&9g
z0uT7A+sNTq^~>EyjZ$N-pxeW^xBJ6u-NB@stke7}@^X37rLB&hzMu;Ze}}ui4S!0=
zpAXqv>OPizgxb*b`0CjKx4O_k{=oPSIBEJ1J?z;JXzOWazd(FGOV{N-f`ytdZe;+b
zcwG$m$bY=?{ritpUq!UK&s%E%wEhcd6VG8EJdB$)>^99T<|E)=)l9Qs;Unft{f7V4
z<Dek2@n!BGwF$+nY}|O=8I#-iuI{AG|L~u0-SxzPKE+;t3y?w@LwZ+4fXwFlBQH=n
zg<-vj?S1lEJ3hC?19^?7{v^CgX5HKARY+#Z0DSbw4p6sN3b)=laThS+rBhSo7x|g|
z%dFG4*!T6Olf1q7yE#yl?Cq4EB9VVc^1~p{@AmPm>xjF;SL&!rzKM9=*5sz7ara-)
zGvf2)Sy035^{3ghukSwPt2~ddg%~kzKh76Gm)0dAX(88Oz4=fH>@M<N%7E4qICuj+
zlYgMuc)PgBA-8RAUD}bfjm0F43Pk+PD*1f!mwxVmcfWhF3B%B}e*OVYSV8tS(I@yZ
zLI79?oG?2iJ3I~)_*`-^7wYnX^YfG*X9L$bIPxIImgzzRkT^a#-qJVaqm>ud0SZ={
z^L<}%I%LNcP9Eh~>Qzpl87yk%jzMvi$V#qnG2dXPIdp(dJt^Ll&QsiXg$Tl;AiIc@
zBLpc*5JFd8h0p2XT;~@+JR$wu0p#>$LtO7>{%MI_-8Pb>@3R3V#n&ad`3Flk83Q_a
zGE0%&@Sg;qGEt_BIDWkt-!&3K#s%nS<vf|DxjQ-7Ue3RFI4QU<dd9#)9}q6~eUYCh
zfVq(?tLQcxc5xceMqbBEv6WjC#QBI^p*lh0JwYiJBT<!+7m_|~mNEA#f+AV}@dU)G
z3@HRe9PYDlDB<a_Y<&qP0GFEf-=_>@#5a973}NoQ!bjL>mzB~>=3;Uv0D&S>={AYq
zAO8>vUqjZ2xeNLE3e|OFh$%}c0vftbKg$}whO9OTqN&`;54lobPma{J)GU^!14nVe
z^lTrPy}+hn;HY42CwYg!HH;igo-S~w55AiN?}mX?{TEDtYg#ra@0Zq6VR!=)edIyd
z*KL4PNZD4U-VN#fc<BHuUrQNTIB}vnuJdXM(6NDJp2inYLf9#x?9h>AICuVX=|emB
z4-oXFS8*?cu+UJr4;Gt#SF&wr9efLdIt(G5lbOZbX7aAU#~%fp9}Od1A&bl>tDOOk
zqd(`D<CG#hDRc8V`3Kv1&G9d(hbG9a@$ioN?k0~{vBAS-%?MlyU5J*m2wgXD{5;W7
zsgk`xS4^b`*T&X8)f@8F(9N{~Z?DcnohsO9GpqS%TlDCuKNQ!u{PqDax*ISLb`uoV
z1a}h!E)V0!ahVVw?_ne&CBY?$0FQ>_cGr>mqb#^dgv!@)ImkL`qa2nR%2`D#vwHR%
zm?qgVcx%kHY5l51wuZdw7WWb}Z_J}D=6nTh%iY}^cv3?TP(fG;J~f%ohvY%z|8Rs7
zN<#rjko4a~l}hpwj0l6HC3J=<cmREsgsw(!gF9=7Sq@gNST^vGjjcK0W>Ts-_+Y;v
zAbm*@-=`PEK3g0QN3Jo`Fp|<)7<eJSyBS&L6FfB~7DRM!k|W*;PJEW8Ft`EahP#$h
z*TXs3Dp29%Qhju^)9qeeaL53<zySIQ&dx`>4w@%q#KQOFs6$8_upS%}(i4i84*2To
zp|J}J#MjEMXo>&(H?6&tSQ=qQsLSdI+Fw(_N_|bOF@mAHe*+c8a{anlpb^~U>~2$s
zo*x9%3ZI0McYDA{b>X_+*#O2~ND+036Ii?=@(B$<V=pyXB%H(n2dzpU7smQV%^r^_
z(Q%mlMLN8#Motq|4mB#xh*PrI@j($fZYWI~jx%i-h^|p~+OQ;f4VL`aB7q5wHl<$h
z8nJLOxTQD&1_kR%IC;{P>8>ziqTaII#e9@qrMydzUv=%K3rWRNJ{m-7>~ecPj0Jx&
zn7$&zWwqepc=Nd(s@cnG0g6TH2v$mHcM6uBN<qnEJqqxGHo4tcL1f50+s0bd#4KmJ
zyH6>p54FePY(U2It14PVLR0lgDQghWZV!0R67}pMKUWXif*6hhqbe+%b?8R0@H)Ov
zcnvVuvz`gHeGE%d9m^RNld4)v(z4u#nUh7?@kvaL{&%nY9#;|*Dr_5S0JK;gj_ZYJ
z&<37?ycS^WQh9X-MPf2GZ0^A~2d~<%{{+*6f0MNK0~6363TtmTi2jqX_D^m&iEcc3
z!;f_1s+H)~^bJGO+r<q>(%Z%R%36GL!;|#(#cMZ?bWr@m4Xy5@`9HmJsGnUu)SpME
z!mAz(pAN5GrL?!_A=ZVX=ygF>^}fK(WW$YvZH+wxnXeC?|Nh3Y_8q<9k~)=JH8}mD
z-uII?J{2zH2R5n2f8l;`{nOu96dSu7D}b%*sK8EuV}F%E^nh9#7S~x>RBKfpQ}MUn
zFguHVbVXo4*rgzvvie_&s-xIR!Wp)cRQmC!usVw2$#;{5>jwl6JF)R4N*e2=Jo4Kc
z`dB#>yuow*$6=>@`^H=FzCZf)0kFlw{zrem`aNL4>c7}M+}NMpc!uW_%GIxTvbo;q
zgxPplQtMmNDM#6-xR;t`^aR$<m?U{?Du1{`Pm+7`W^Z94`36-Fg*_7s>9vc824y`*
zw=gV&&H4gw3E$7SN_-zhs1rrI>pV7Y1ut%N)lQqsrhJM*eZx;wJBdY3JB5r^1NRYN
znZsJ?1W`S>WW8c|-a6izT$zr%QRFBtBkHe}9dCqsv$_D<zWv|-4ENKm4Y-ggp;>ma
z6N4r$*tm>5Kd<D`vuuLvb7x}^Le|~ly^nGB85CxaqL%Nb?FDYY<|()iyX(Ucl6uz7
zKrE!0(tsV<L|6*)G*Nqf=MwA(Ex&Td0rMMDwSpr=J-~xjwTN98cEV<H&4}n2(p26V
zi%krl-+ZAPSFikF`AKIOI|OVLtUp3-A&@F$mKjOzxy<}(Vp&z_7&6Rzu?s^ljaKb8
z=TIvNg0Uolf^9Hj!=Qnym{H%5fN&D3ORc4vG_*hyTB}|xWD@y8j}Lo*tPikdBlI@O
zoAM=f+ZtU!KFiKg7Pyz!IQjn8SWPZdaPJ_RK=hV2G<l9h`5EY7r*%MOXg0C2l3~qy
z5(`3+xGJe_(x5k;^Z83zZFh3Igyk5>{7HO*k-WLX4CBNRdd7i?%*rbiN}I4tmLvXU
z^SKqnCiHf9IlC2n#vTmVO5xGGc~lb*3T=5BUfLpm$R0Uk<n(Muyy8A83WfHyFYoL{
z!l*1M-Ht3_oKn5BK3Hcha_a#kF3LIS+1)<%zXTeuw3c}b!2%RlBGC>s9+IBoXW7~A
zvrP0Dux3Oc41!nuS((5=L&jxbJSjuR+4ClO8@enStl3wWy7Y_+B?cxvL_eA0rzlQx
z8?!`G6?W7cb7|t;$FreVb!cnwnIe#wt>qL!yJ&U6g9W5Kxr~eG-^7k_pr2q@-@fdM
zunG`?-E9#ux^<k!@KMhYZQJXzkG$bl-KTR<zixqtg(kfEb5xqk$g9n9WPNq3d2cI;
zc$2f4L1(T}?Knz33G^xKDkv31uqJQhh>esEy(c*=CuhM<QnksIs9~=NsC1fY&t_xr
zU86jmhm=YD-K2qxcM=#XI@0<i6sWCBkU@?<f$MOOx`o6Lifr_;Z5`Bqf3jLnlM{ty
z4-Olthh3TkNdxz(N?1?a=i1|0Ea0o|^YK~WVt0jG&jF6J3w*6D=Wr|ZxgImFt!KW&
zT{xFP-=>XD48Y!AHUOr3%M-=A*ikUs9ab9k*mR_}$OloPRo#}yS%;c+dx<ZC$+7ny
zoc1A2<8IZO#DouMg{l$7TQ-u0>Pe()tC^tHfpHO(jcruk1GP!0)*27v2LkT6flmup
zRi=%WjrkKb^L*fp{20)#Aj~lYS3#?o7e)jWTG5yadZfhj(COCjr`q6gU8Wzqqsz8?
zX(OO`%bsPD@-1(GjX`nc!=q7-?W=%%95`0a7zkFNI0uCvtW{vE4j<kDqbxLYoq?pG
zVgR=)#DzLTwlcFfHY&RjxHCl|!GXeT;0Lo+V*WHNp+jDypo1esp(-WFwN)6*0_rHg
z!0v@q6f7Au4zVc+B%=Y0)gU_;m_Qk4Ogy!&8rF-Rgua}X5Hg(NrY*2#4q|Wu6!)ne
z)<Nos=)w!<B0&s0K5e%R5u8{CfE`7k`hqd<vtnHMG!9?9$RIN(n2wa`h$8W3Kv1ex
zk<jxKs@E`GNZ@n0FL`pF&T~u-THMEOmX1I{O$E5Z6XY<Q1X>*NF}w-&tfu4$i6{wl
z=zy#(ZwB;6d`58qlfeaX2BT%8WO<Xq`}Y5PTk~NQLW5v50pg01TdK#11eNm@^*#tA
zURs4uO+qyhI;RjTd&+1Tr$J=Gh4dD|GOT-gQSc}zeL5$*l;K=#&vDf9<P>XjPGTh1
zG1KadIYbx?wy-4#q{^xsark=E3gi=A!Xn?Ne{i-LYI1JBqVtg|7Q7S~)#AXI{slyG
zh`^<3;sex48J8K;D*^+xF3-z{T6t1apJ$rrMEki^M(v9>NLw_3;hn&K)Any6B+F+(
z)@r^a5?4rU#x+T*$~*_S%&5=5qLGB%t%imx+*{AAd(hy*XBi`Pbv<(15wPHL0cSan
zYtoAw*T&y7XEUCMFd+DyR6Pn>iRqy>Nxg1_cK}xTB}_zGlmy<G?eGZflQj}5sStV#
zhPD)1)?bwn=8w!~$f05kG3I4py@>@Vm6sZU``-Rg&58Cq9(HXSIHZn?AQNPgW1Pio
ztr_^ocf62%ftwiomD-A)UISshM-m#?FX$>JJw$HAp(4CkSXM=bkLDN7imD344fcKn
zJ!+a&a+uPsA&-Kp7BVBbT!ANZv}9cS<~EdVhK!~ZjIaQ&`?7UnFr7pCOD$rHsxWE<
z<0HT&FfdwFLi1ZjORZOnHYQb7ksj)1H3H~5N`eb<#V$qyICtPe%*cq;DaQ~bZ-dDa
zB;kk(?nxsc6$9BTXtT9qaQHfF!YPHLs#z3HBk0#Ywnx)N=|OEHY=;yYo<yJr>nnIQ
zd9;9}R5Z~UKN_b3nnu;LxLQbKKvhB23ZOe$Fmp#IJ#U6m=u|c}4;WnSjh@wM#6>rn
z(Kl;$$xlyt=RbT^@1-GWo3^c4{yIc@5*~^;E0pX}*gVH?paBRqUHF|Kb^=)l<lcw@
zQ1dL`U4(Ez*@j9{4mdXK;K|dPPG<D(*_`P;9mZ%>AP5J^aC4S>B!pc9){mT!nz+QN
z*F_HKuIlS@N8Rp&?yZi!{6$nNB!TFIHZCMVPlVl{oI5~*o{pR>OG{%{!iCf@4MK&j
z&S8}-O@!$^#4#p-t987Ai5U{z+Fa|VRhiImg=Wljpxf<YbDoXF44BQ$dFK_c?qE%z
zhyK(<?3Ip}Yoa)2*qiBlKPWygosH3{=(pyaWMj8+i2N#Sk!;5HvX&EHE1$lE{QuNA
zotq|6I3GaN89iezaHvbC0od0{DWexiOR7jisaIt5G5%$M?-nA;uL^M*!#;bR&1RnN
z<7v`~QSUHMXAYXDBbB-EzWUGw_A*^>ex112OtRj5XrHaefD3%%h%oJEXanJWl(gyB
z^rL(>6Memr=UYi_Qm%Ew^v^zV5ap~_bmy7ka;*Q@`GUTD^l1NAdGtJ^!&i#S#&e?5
z^UT-oo+Z)G#>cw%Is2Y=#L!gyGjxiw*WIeTlQnEP6@H97#?%u|z57zVN^;X-gQos+
zLF1XDP|voYEdPXThYJO-$2>vG{(^klh5lvFJc8tdHtl3!tLmwp9xhw-ajeFNVTn+c
zg*IR0FVho8KTLP;bB60(UfzuD9$#B*=gBa&=eFAqUF!ywUXEN~=2v-5eV{&SpX=K)
zO@7Ok&%kzZ_*L>aBOmp?Fu4+^4|CW#Ecc&0Xntez-S>VSMh)wH%KS*!H)`1C3yW&d
z2ckJf_xcaGKX^bhgs>M3*g?p=PzMA)&Q@`;Z_%)deZlbnw!9yb;~Sv4<g1nHWX{+B
zj;+gY!^+v`(GU8xc>KXdcmXu9#UE$u@Z#kL7K>2N`7b%-{{x2x9TJDqAYQW@&&F$B
z$KxT{IF`y@gH1|ofkwOAzN<skJmRi8G%SAntRCs2J+piI!=5+rE(*OflD<wscf(F!
za+$52Bbyx1p@9W5c*{eez6<slai(yU+wVa(SZV4X;fIBFB@7wxv0(QCnS(O&wNq7H
zY?^8#2|D?t4}8I9PHe?i%IU1CPkY$VXL47NbbzGt9lIqG@Q+<Hj5reWcaCkSoXP(V
z8CnwAGjrrU-pD@MUAjWgFyCI`ujv^xJU+A`3|;9ieS+@TJ!CDAJ>O43lIz!zg0BM{
zA^xu|JbUK2^EuRp+I_x?B>LA%&J$wC?pI+5@dJL#ASmn+379n&A+MX{DlA?bsD5)u
z8W0sOfXSdj6)0_dIX(dKWmV3v8cp)7s&D06u^aGZ%bLI;cC)QK3$~}5c|bhOUX4=%
zV6uhcH_AFFdI3^P>v3_sJ;!o8;QMn#R!%@L3*0ysL(>1VLI4AIi*u}l<G`C>sC1>S
z4gCSX>Rv9X>vKS`Vm`O$Z+Hs+2+l6BnZu}WMzb#2TY-B362K++5Ux|PB9hmWpPTPQ
z2Dx3?qbyBDY-lsvP6j6dz6n%LxegW{_P>oAd<SUpb{H2ha@y3$x;}iwnhHOPbF2Y9
z?&@7b!uEtD^L?<Th=AzhhUryTme%FtyPL?nhj#TO8JgozGQZSbOpYE;1MHsW$o1Fv
zd>@>Qj*sa;w1Ct=u?pRD|2D`Eca80M&2-+{vm`b<+x5cG{qPh8Gbiav^XtnXwpY&u
z;xXR^xkn!wQeUF)!phXbl2#uGUxnCHvBGuL;0bjeic_B?frR_${!Lc{y(Prgi`uP4
z?nhkbv7+>uF?j<5B(x=qeS;iiFohl^iKH{u4I$}JYLSk%a3do20)SfyJxbeyvRCKz
zi0YS5`s)GsxDKh&;@W_LXyee`+5ug6D@}a3oVd@qIqp<-_?HmdF7HjEpFrd3kQ^>J
z03^6DQTowi4imJAH@FHUk5EFE1_|`wY65k{PN7*gaR#{P-h2{^{Ly9yw|J)=IgO0D
zWj6E{BrX@pLKuFt<E_;jv6klJs>rv{D>yVVC`GoTD^jJ;>*O>?hX_F!YT84FbcXIj
zdmjDThKjg!%K2}I&s2_+>~3Qy7_U5R!v^-}wC@#ewVbduMo}ot9H@k0l#p;ZLK1S6
z#GO-oo)`lTnZV?hTH&Gx)LH|yR%$tX=fWi<A;K((b^riOc2r7aoq#@J=u6o5laFwC
z6`{MMKg@7s*cL*|e8)2DK%tD#nP%B&P9dn}$4bETV_OY0<CnfmH4IX*q;?GLyEs<n
zX#0o_?KVT#%fD-3X;s8kjz3Be))IV_r^2r7_@K2f1w)aruUO9ut3q<1-{ZtT2W0lq
z(Gw&N>Ar-dbi6&Ew4h(fxKnzG_(l^1F*!Z1%@gm~<A&jqTWU78H^<tp+9;#%t4drA
zSDGOx@54aFkxEh_WAStJvv(t|)5Ui3)S`e%6X^2C9u~jzpaq5#gxI@+R0az(b3ccZ
ztL6V>e6gVbB1Fgg)^i}xh*Z(MEcqxaI|NuYV<68+`x@9POb?*j8ZBXQt5{NNd}|Nt
zFK2E>xc*`@n8#uh%T!#y%Mh|yV`Jv1IY2diyCIx>Ra~58S_xhgo^r&cW%uepF!WI>
zhp}?8JzO$K5$rDTr7cBfV2tab(`}Grq>{C5MAQbEjoD1XV_7#p;*S;!q_e3AcC$kr
zVV-MC*Vh{*W(!`)Y<KBUtzq5eed6;RE7G&=L3eT)$w<KoSyzPzl%eSu0?ks=g}zy^
zfgMJ6nSLsWaGYUc`~55|jmqBjzxwRNvI1xY!=n-cNCbKqxjJ)h_b?@PO~~J15((MZ
zBet=bg&uj;$AS1B3K025$IIq~oc89a=fA29h=8O4RfpaLm0HRYVslVvs-p!y1hY8I
zlE_YuX${<YJgKXs7p#c1%X2%G5>DkIrk<CkIA6nbiBeS0<ka8%7nZsA{<x#UC;ulU
zr2aK}{Noj*ev-Sx4FrA0_#gWz`~>q}nE0Ze)z#vU;9gYFdjCKhN^ptr5%g+ttyP<d
z)#_Sv?^oA4_QUF0#{^F9$E$1oOKg1RzkUd-e(an)3t`HXh7ga!{okM@i~?#0Ax90{
z+ZzuhY+@4N8YRUZf!hZpyd~^o?9gY-01z@5uu{SwZ9lWw3SeW6OjqnGJ^yf_a{1bS
z`G?h=i2vgUUszaU^ZfqrOW1LI@E7c2d~J*`(D`Ry?=xfncVD^v7UPXmQ!KAXQK0^H
z=47@qSbbg=xUDn_>1c2Za*(^LqyZ@-`zn9Fdy?!V=}v!(Fvv)sq7snNJAViYh_6%Z
zzWd?sPus4>AdakI9o|k}u?5CtUA8J^2(4hk(AL_j>^_4k=g?0INO5HGcp-XR6ik%=
zY2^w%=J2ffVOO==r2D)+jBs79K%@KJt@^!mD-qp&SQ{l_hJea3TXkCNRR8Zh5{@&x
zqbt4e#bTx-LRxZx)v(Dg!?no@ikX50&N$2bT1`z7903>gAUp720?u0gM!mP+7u{e7
z2d*T+f@rNP(S=S2wP|R-TrjbDOPd^@*^AulAwxe9<;69S3+*za##I-GYD=z$(53SR
zw(s97>_kaNHeLiv@noV)&JZ|AcwQae1;{Aypd~#gNk73tbr5<sf)&R)D#BXJevo-b
zKzs+uDQdm#s=a#FF61WahdENTXm```JjkyF{3Ku#R%irT*pR*Ha>N-=0okxtmyJZp
z;4XM5z_>F|Cu8MOJ}bphhJCwENm|<}*uw?n$8%NQbLI!P(UIkpglK$-Az9C+6WBZ1
z0S`a|Tm6KM#7TR70Y=VZJxmd7T9C4VqU$saxtMM$>rHydK2bC$T_thQghaO=TYRs@
zHH*HDo;TQq-PribHl#{Zpa@D6Rq3(2pM+v~v^?StUeHgsI$6w4HQPlBwp3v4AsU`m
z>)VI=WVvWt<+K+%ed$@<L2O?~J*&K?F^2$|t-!JO;V{rQPd~<iW33g8e~D$Y#cA;|
z^GhaIttagLc8`e73Ya!EVFil&?_&QKoZ$v7#iYQ^`og3X@|8(9$%SjX>JecFo=YNM
z{%r(#PGe)R43PAgfjxPT;iZw^E~0_x@y*ZK?_GLs!iJwhRRV2Y=<fJ>)S<FpS`Oz&
zUr|d^T7kCU;S0t#tYD|i!Dcbfe2uR4q#f*@EwnmlR?|k*4@#a#8cC~~{IDjLJSkGg
zlQqo~Fb(zW^=6N;+3_NU!WZ>4Y$oOk1$oHMZ<G+$we2%3P^Ysj^IDk%+AH0+FHg!X
zCWFoF`OvsAG+st&HM@A+EM<zH>qpAf9DC>IPtB0T+~(z{P;7K$FDlBL=jK@Hgl$f-
zIUqgQShIEqyWLLoQynB~&im#T>DYdE`=m?W8b<N!&A7m)xqX7I|FG;aS_j!><6NvJ
zs(r1bkb`+v=T5msJ^LV-e7h4(*#EI(9-U=LSo}rJb0Gd)URlN(3JcOaYvs+vnHbVo
z*`cZ-cbWC&?K!q>_=yF2HiNKQSIWd91X61lC%3QXmqUgcD#S|CE6tb?k^_8UbPWOL
z>eD(-4!})CS8D+1wvr@B(m{A<73qv2yeNvkB8Debncf^Ovyx|@;i@;!6=9hO%yiKS
z*Q@ba&dj80qHk%vB(F4X=C;LF*i3gfressA3&cMbX{mkEE_ki$Z(p|5i?$uG0%)9T
zY=~fW<V7ejb)Lp*7x|Qs%%KLF9r%P6CO|l>)*%UJu11<242pDpp{^y0U_k+)BOs(n
z8{7~hWXP;Tr*5Hs73dS|M*u5o;=bg)ZmOn(T!6p<g5rG?WT!t+Q;Tga9pIa#s}@7-
z7BEz}Q^1nNaVNN8B#OY$fph>Rq*8FiFKJRVG$AcDgmkCG0u=uV$fkXy2L0&H1$0il
z0)3T*$sFFrOsHi)Afs6OmymNYNtA>{7!8UMyt{bk>(@gVPW`f(7(7c@q9l+|KI$qS
zJ_Quk#Xv%f{1H!Txil|IVT&$kBs0i6w-b5zlp-pn<U$=|f`;^)49}0$prAU9fVDz>
zzg8+(rG%Q*4wiqaIj5jW$el1x{gBT-!JaB+%U$Wm^eDb!uNkcFUr)zE#8bhb6d-K{
zX^FaYcsB{o7!WVw^IDL*SYIX@EOXXy27`w>LOE2x{LB}*3OHSG82JKV;<5*9iHJiD
zH$q`2)Pk2*3pETUF#ADV!B>StAFKE<e<=3-r|-qvQIrCY1f7Ik3IGW!l8mTQ0g6JX
zGNs~VrjrP8D7zRSK66oj4dG18i>5iUVuoxRR1#r`rmZ&Ym<bWRK8>A%ol#-1t#9E*
z2}8=9f%C>2L-Ou{u}VZ1hFJL(c<I367mIDhV#U1qR}o(lk0o(;P;xXm0}TyziV_{)
zv$_LD$A!W@!LSK1(+*}Ikm@{~{S+!Ec#YyS`)`5832Dk=P=^II+<8?!-@QPmdDiCe
zTj8-wtOx>)#7>JBp_}EC9K%>gEYEWwQLJKvANzr&-;}!Bwr}nw(Hsp05d0oOfrl|*
zS`{oB^Y4??SjJok|8R|TUoISF3A>3Xj+zQ6yvMYL17lf0;`4l@!h|)6cAE6<9k3iv
zs1u;c(9C+U1hp*{&IK^G*ZM7Pt609CH6;8Z%=E2FsQ9-pZnT1<m>@7jV15f?xQH-<
zr8zXYfaM~g;qxXch7y&?o?*y9z}dIemcR`np<=+o8R{m1^S^<-3W7^fzQr;-%){;$
z*HxLbkY|Ody{#rYSlx9Yybv`J6GBD-(D6IZKByR=kO&zEWGFZ)X-Kt^MM8Ciw1YN2
z6E~GK6dKwnY)#;r-f~qV?}>y|v$lp64OK>pm=nQS^EDSk&#;XR44NI9HzGizNUZ?I
z_WSMx7El8PRvJ|C1FG_oz^7l+XXg+*kjk?+A&_wyyi|EftyKwdYY@#-ACb1FhKje&
z=<vH$OkV(Q1-7yQp(c>J=yj_M>QxzyFytC86O6koUR2R2pSD?~lr!~Fx>R>~Lge^_
z+shN0OiaS`w*b;?7dVRq{h%{nFNCK|aP+23@!IQOgnR-%TTq_egypGn0AgXK1B6V^
zl1TUd<(J8bR`SCxN)(x4O2`Zch6UHo7HkF9C1G2&v6@*<S?~<?+a?UTFi5I~HR+D=
zG|z!(Ygl;HeDyaqX$i|~W=gr0$}eaFp|Xx?TY3OtE_avP`<v%syRfI*cey`gqrr}C
zrt~?r6x!c;co()-pIBHcSwsKsa$aA%Jlxm+Em=>ZO!Y6#K5$ah>$}~Q!{U<;>SZ0K
zTWRYxL#vZ_(`>z&1#x^kZ*Ou2qx(AINTp*$x^w2U4^P3;H*aJw6_#V^-=*zyIr`gC
zQrco3q8sZ`92q@4yTGS&J(>DRo?hl+gFI+fJA+V6<n*~C_9V4(X7?=X5wa(<?Jtm$
zaHy|!*(Cd`a@+ZS0N;<W=PK+6pSC9n+Y<k?&N|B(o@<m|g;PeOKNhmTHMflQiPO#2
z%J38^FUMqbZhLgh-S&h##ggX=sTH`j_n7S|v7J3Da%5-ySiXDPDIU%l8&?K%NFhUx
zRrs}fPOs0x{vywI?HD@Vzjg(2@OZ<h@?lzt)x)<Y`;bdVoL6!J#u4Gm>=Gl7=N-DO
zlSvn1J1M5(^`@xjp}pdr*dhKD&7a7bk;lw_vXioO>m2(i42I2qvq!X7#9*I!PM$V$
z>92hErXKGDC*bk&kYCJ<1%Q104f6O05B`r2b;tZo>(ULAiOi(isH6+q#-B@q|I*_S
zt=z!N<NJqw6r8;izghUs(Il90>L{4;%l0Fy%ouO6jTH>vXTk@{5|92{IUjtxYGtwd
zk~)luA>S+OK+~vk2Bob366l$4Jf6m$;E<I5r((@B9Ol8z6`z!!AqVeN@3ZZn5Bp`z
z_WUfBU+WoyGMT`LtI$b>q40g+8vw6=!`R=%7s<=bXD?NPUnP6~4tBozLB|0nL~?oG
zx}=}beWvdk!U4W*MBI6CE3*BkAu$%4_Q9@K?0D3xxY;JE%6}Hh<YZ|MjtX-3cL%-`
zb}zr>d^UntM($aGW9qqN_Dw!D43d^9Ri@_qUN(>Y17Co#Ze)<W&7BwS5Op#>*25dG
zpSQ1Z-X_(_+X+02o#-af__bXZ_@>FYbKhOmy#_J#d*azF$R|*<EI}U47z(6aU--*+
zbiF_47YZBGz3J}H-egt8Joyr`p<f!2&M6ev_1{fhO8q0}^}$NtT{m181Z*xE721>Y
zt%pTiR!%{h8$PtqXr2*Rp@NDvrMUw|>+cX?dZ{aLb6_uh?0(?O%BO}jIBJ+_0afKv
zq^?1*YE`Zf`1v0DE1z(4)bi!2S<yH}_B=uxub1r8T$>OXn3{eRIJq(Y$^%8<<?9<$
z^j`8TgQ<dVGuj|y?mK|8^pWWGKmUc%hX-~8BkS~$o22(y$A^oehN{ATK7PapqN~d0
z#@-i+wRbISe(81KU|f=SP%cbcjTI~be>UDrB1!<EF(k3ZOP|MQKlLo?i$Tr#z($II
z%R13hcxms!)M*nX)FY5zdYoIAU>Ov5jw_?ZTvp2saF{`y6rg~R5-WSgAd4*lQ=-V1
z8u{~sa3&buS)q-}si8ol_(yz)W4@IYEBYf#py(ja2f{ynUv;WZlhx`Y4?recydRDd
zCD3Z(3rn%hhoJzrmZSpLhKFybB5A{|brhVl!5DFx6144@Ba*(;G7|n_0nyl-^=oHU
zJ`R?@dRxwz&fAat7U1UC{rpIsGK?dU$3+fn0YIz!DU#$-4mov|y10N)-U679mh^RE
zv}7lo58sz}ou+NFrI&7dW5GF<mX)_&(n4c*X92=XxFCOf?j76#o!cMVsWf^V2!wqP
zSzlhR?iuFNp+LEf@z3dTN#26jFpY#=>Et-j92zMi9UO#uXi2o4SF?x{oQF-xqp&X8
z%FSsy08#l_sBPb@?{1IbH{Q^(a1Rcj0fLXgp4n-pAzvq-^|WKSi3ny8u0WrjFDR&&
zH%`_=Au?3*vkv<ANNA=X<7y)wEWn5QZK|OYx916bH4L<fq1(h=zjW)+{SWBvYu)sb
zJuq|l>>j9iQLU%nr;tz}N1+G30+j+9S&^8=z=D7;#R|?s_r=~&mKj4!;nDwA%du~M
zvm}b~u89RcpjzQK-AB70f^To5g36f&IQ0@(@3B|-8=N>p!oUrfj$_?DFACJx^ES$)
zDu+t52p~AlhT<6k;=T*K^5O&9X!8zq+7co#_E^dH&G_!~;`;7;M@znA!^0_3-kXOG
zpSliDy+Bn*rv`#Xw6XUokm*NIX|W=B0XW(mbr4X~42XfJ1e}vkL?m?iA5E#FFQ$CW
z{AgG(?4X97DKvRH{;OM%BryJq+<Gtxn+;sJ(c}OmmKkxHkuyoRh^U7avN@KLuByn$
zuWtMu_#HbsyiA-^e{=s3`ovZJo$j9R+y>vgx?TK|xSR<Ltx@U-d7=1Ug(^m>u0=2;
z_~pp_#&BxO6Zl=gidV>?I`S?MC(#eN*3qPlycX6*I~k)`=@4c8A)wR<c!!Qa`q;x;
zc-yZ0A{{kTb=;1<5DUvp0E%eq@?-&5<)nbg30ibh2h=9Wc9h!CrH}hY9%KLRVbpee
z?S3tO>5~{{df0cO+Ia;*hwSxFKX_KJ_Ohj+u9kiG9Q>SNbAfX^)e9(>3CPrKh{)l?
z0ww<<EesW(0Q4>_f!g$A8);_LcSI43XZi)%T<oJuwW>_1$T+dFA)=m-Z!nVR8ACdA
zB}n;Sh2TlfLmw^bFt@=puG4Jg!cd1|(+GbRI8!)RhZd4-%M$`d?AgU!o7~p;vaUYA
z@27wBA)QQMBZJa39C~CEIT&no+{f2gvR@hpc80@X@C`Qy(V%J<@|H}hzE$w?qCcw!
z#6=`hmRD!n5YMwA2=Q?gLM_Oj8;E34x&3BeBXOY-!@?hw+TREeI9KGNK@^J9A9Pjy
z@h5C3tS@*7%V?f$hG0Rw;cstSbrrrYFzcew+p06gAAZUHU*}A5>Pz;j6~w6@uNim4
zRN^JnR%?IHXUzBdMb_X={7;?|JAbk{@h5Mf^fOr9{Wx`g-{Rsw53Wny@Rab+$glUd
z<DX7xs{i%zzdtnjNhG3;zt<4>_j>l_pWlqD>}#I!DcavNzw<r>FYdj;z|FTx*FXQQ
zM9|k?{j)EKZ=fbIAYSHp6ndnr2P`B}-i)1c5!+=g<rm&lQZB+RngSnfUoVaShcsa9
z(K5I<fVV2KIT9MkxSc3M#IIQ2|JFVL18l?o8IlG<c>m2IjKLRPi|vg6@FQP0wx>Vx
ziyPnm-CsRVeGTwuqJxo2G52x#CfP4r4gx)KSd<L&OL_Y@!h7YNa1RI}BX>VdtcXM|
zd3u5-a%Nra;oi&i=rWN}K;Lfr1oAcyk*(x_*e^rHNnv8Ys`110{4_Rpa2^K6h3)63
zkX<IjD`u+0Qm;$dW!Fw~SR2@~)2$w+FVPDu8h#b70v_6O8A?EQANIF(doG_>ppHc9
z@+?2H{zJL*%I+!Ha34ScQ`9bKsV$qbex1@GX_MH6ZlA`gHuG%Wb~a+2UN4S$*zb;X
zK~jl4eHFPwDA3e(GEZmn6Mp#~boeVp8|AU2SHoTzi`$Fbb$PMFWCsc9y+pR99_8@r
zY-lH|IY|AmUxu&3h1g8Cw1vcBB)|uQ|B;#T>#3c!Dvz${DGJB8)FASBy}Dysw`L$d
z%X_I`k{dae-Kh$<=6KB=RO{i^Wm`ye;D!NNPIP#<-02?+#n_q%Ob|`gs392Q=cI2F
z>RB;jp9c-py!uhfuv-)viFwH2+*Q+K=+ZS(3d*786)(4WD}1=JvYzW#U;=_RiY@JX
z?w3XpzB_~fSRul?3lRV8lv}#nQ*;geunLjsrxs+iq67VT={Kd8xx&w|Sp*|AAenX;
z85F+<aUIp$6evEL*L66zHB}q!prLgmzNblEoyjuOTaQbAh%A8y>9EK>#Mu@-k*BH8
z6}Fg&Z+OY@n47tLkIg8Zw54fdsY@He77NtdMdOo`r9xX9nbp62c~^%`ji{wIiqLZV
zXOI@GM_Bm+Fl!TcH+6x{$@Mz$YV>I%<lEY^1zu{SQ1TFKsuE_r$ZEGf&u7d|H;nH~
zuryJnH)GlgMf!SU1*Ha!gzVZp%RGx|mH-C`LAHr%ntAdx*G%}iB7rzK5<YI8N1eAB
ziX{coe2<*J<%{}0ITgL<Jlp9GJIi0V^sEgiJ4M@<;_wJYb+6!3DOxeVMjOb0eVP1!
zti26*8`pW~I|Csu>^LcAIE02UCG#8%;34&40s1J+rZEN_NRUm%1Wc*0t0W{%B}z8A
zH5F&q>9$WWz#sxEsun5fR&LylNJ(8Kn{F*7*>$&RE68LkZ=7q<v0G(t_SRC|-t_M7
zjihvYo!#!{{thMQtG)Z&`#cx6KoS@X&YU^tJ@5Iy|M&mCIAQj`ditCd=_d>nx`sX0
z+}Ino{7cE1A>uZ0*e4UQ9gVIjkjk<>Xqo<V<jO=q5+qeUh2dXx?eR_hg)7Nrcf4tT
zY|8dr=IAV{8}S43O2fP~paB7vY73V?bHH9UjmQpRNWbv3Ejxov<H|$hK{)g!^Wxw}
zD?hVpt&{oNr@A%YJS^V~(tGXn3B0ww3Z%UBaNhoKa15Xv-ceVDm*HE^x%U}9<>$s4
ztu1b=L5x6@ld+FoZFnCI5-(VwCgFcD|ApDTAifxxF7_I}Uo6ke_Tuh`;|*(PpwIB1
z3xzxAKwa;)&zi<0Xs{?Wz63_xyy#B9YM(MQ<xrt&=C1rYK@`gw(5JKSF~jNaIcDNR
z!TMDS0H4ZR`Sl<Ce1y?_Py|v4={RxQwC@N&$I7*Za9*n;1K9`Ko^T>i3S&)1h9anw
zw|#~1Gw85hK$hY2iaD&7I}bP&y&J@)6`rJlPc^;rtgCKepPq<#A*r{J6at`wks@Gk
zAcL`spZo17&`M-qc@4@f<A8->;Dq6H2Zx^gq+>67;9w?@A-G$?hP&LKvs1yWV}t2U
z<)V(O<v<JZ3;Yq=>$=Ly?#J`sl6K!YK|M*^6XT}A_79joXhbqztS7YsXmtEAf7s-r
zPBrAk4Tbhq@1hyx*9XGMs_@A5d;evf=#$r{1E2ezVr$zw^#Ty$1tws<*zlsnq5}FW
zav@3UFb04<h>0CUPdzY?S!xwg@*M#4F&A2B400%B6y}3X*B}u_AHe|~iZLVsgTY7%
z>JTn{@H8&Urd}V;YTdZIq%@#ulXgZ|L{P)9HW}7sL@A73c<|JMy9ne|xRckzE~uA1
z7aySF+qluokOr*sqO<S^S`-)ebY?u-0ZqfRy&(`hL$}cPncZX%Q3a1)G=^?a7c6TT
z?zWiWTSNN6qULy7+O+?6@T~TkDE?}c*7XI*V$a5bHET?A{fHFt$jk6b2(owxI<pG)
z9p#zK6(DOxSMJkU>s-wbLj(@s9<$ym?Es<+)bDFvbbK$^i8H3PqJbEBDD*$C_v`%;
zl=zE5LEO0cN?*rb4AAWG!02q$qYF_Y3;P2Cn`^9+m?!B)<lM2@f*`)sM>igEtqY98
zmXI*F!6%i98X+(+_mk!Y@uZnI5|zL<%r5U9&lo2_0;$~2snr{Pa-oXAjSVvEOTifK
zBQ_JaPn+KLKYE{|bs5$wv9ki0)9?2gcL?-*dLElsiWk{UNCZi4l5a6X)L8J`F3}NE
z#a3J17tJBS%P|81?+bi0S{+D`#LSSMh{xs&!~t14Gf3bPbV22va2z!}i1upD@gRPe
z?Sx(cjMxVd9{%8|J4w6O55lY^@5^@98+VTcA@g+}upNXJp={9fF7A;<E``xl$TUNo
znly&KOE9LCvjbikf`ng?TH&ruG(ojQ)P>hg(rsWJV=c<sRv0qehjsJV2ulv_Zt2#F
za5#a_OTS|k3{oe$E1?fJIMRbttu#jpUU@31i-L!CUI<;+<yOG_E_4hE7#fIMw8w#7
zkxEhH!%_;wS{L>J@R((SIRR%nf|iWw3}57Y!+NjoLw70MZ9eZHQ7lbg@tTKke){*B
zYaX`12rGm*9fldUC*VY(v0h()ah*-L2t7jLHX-Z*FUS%~Z-^kWSii_LiSwStu&^Q3
z<BJfZF%)T=pL8M7BpRWuL!O&?X%`$cgd+vl>~)F}B8m@Pzqx+X@g8HeBaG1ScM9Vj
zLBXcS8IyKTmOD(T;+`N_D|)<!zAdT-7sW_3uAI#?xmQqf5*#$`81qB~YBmV1u4|4q
z6JTkz3yjBrk?6%^!FwWZPXu)(XT%EwWru?Go?ral;{SwSYZfB$M{RAr9`t$JeGe0%
zX*d+?BRS2zT#n!;x)IF_DYi?D8Cn;}KYbo|BV?G<U9NeQz+F=ba6mUA?9#YsuwRN;
z@mXORy<Vggi4WBR0zHSjy?6(Hn1Ze&al&_>4uAH;wl|ZtQ{J~sZ}j1w>{_tuCzcy<
zp&KP*ZO>!&Y`W(P;plV5nPAGC73rY`bAx%0d0+9E{aR+{Tdr|zx=8}TB^b-eiMgKh
z{o`F5jkW!~M)_l1?sKUrK5N=N0`u16Rce-Pt-*3n2`27naEABR*hectFY_>KCq5F)
z&Q$F#0-EropF3|9m+eT`cxrX=>t^SI)fr8E*6x1G65p)2YpenI3daxFm9*KKXgcP{
zO`l48SN;3up1JStUoih%Bx>IL8v9sl)NAc_-=Az|lj;42**!W07p?eMJ~(bJ_gCzn
z3x3l(SXm?Ql~>Qt8V`!%r*cnOv*|~XxiP!GVQ2G0-ihATjqWS<`Tp7du4Q|ok=buN
zyJ~fi@0!YzKEe&i8;E?^!6x+TgFIn|Rs(m3RGQTco4eNQ4(l-#j3Y*GFfY0q)u0!0
z>NZ#_FHdw57wyC5`|TY^!;<}g{r==L-Zcm!c*CoMM;64Z>!+McTM|yCu_N_nX8V8t
z)%U;Q)&7++qjZQ30tNey8j!U1HQ4G_?kfOYi||ZWfW|RToij(-TA1n2-eN5uhv{6N
z&2F=6>@#XL1s(rA$&Ey<*Ra`P!;JQ3aanzZiMxQ@RfU3c`k#18l2h!xeekW5uRzu0
zou1+3wO>-2AbWQ?JP)#6==^0vf#|>UMnmzT?-74IOUXJooYddi?dVH;D@pzJf1G*K
zpi<gwceM2@UO5<T&vxsNOjml=v`oMIpGqa`yA@Kjn=&SimQpr04iQ!;_ReRIe}5%w
z{2;98b>lFr@1dmEb9VP~<!ttl@%pZFwx|RrCG=_Y$|71HN_k?f0e?_@G3z~VM!)h{
z*YhDv=9ZGXIQ|_lMBwDvlN2|CXNl}=*MnV=*WV-4UhU=dS8~Mz-V4rL5zz_Am0#;Q
z{%Z9s3a7~xX^;$s@e1boUwe15vio^kFVWE2rQP4_G7biBj>AJfUg;ib8-{2-{-v$J
zEn9nn%FC^zs2i-vnL;m3Lb-Ic!Bd+@{N#ML#dU$hO@mG64v{yB+5*a@^Igfx%Z9BK
zlt&EY8fwD^6xdLT=^+EO$+AuwM9_k-)J#Q0hEHwp@QixSh6LJ-826KpyVPq&mh3O(
zinZ4^rk}SfiD9$|ob>6Gb0(?E^QG5bYZi++^Of~n2-IX!L8~9ysxLiWU1N;6`~H;)
z8~2|GbZT2QTj7zP&nB0h${&EOcX5x*xja}>H;`Z0jY2|lm9K!V0mPLJYw+6uoK!<o
zr=15R-u-?^4XTKp!vB?wZVz7u$h8iLawqiKY3qV{{BfgDeW6d?n-_#!_6_4IaBl8?
zsJjkasrN0=$sg-Jh0@9E_ZAymayQB-V07vE+$-Z1=<`EGQaOfV;?vnXl2c)Y&RT1J
z@)yyB_|7Mtm9NXJGlCW%VyG06kH>(e`LMC{0qV^yWZ}L7rgiJ^ifMBEG;1GBZSW%^
zBZ_a^f}Fcx?1pd((HKaW&7lF3@1%LF{CF1C%|i9_n$!9v<3h5<RdP41=j~#(OR?9B
z)!e=2sm<`7!_xLs5W$1pN*{ankz(YK;lR-S*qOBpn@gh^=;THHl}|;I0L*ZeD->C~
zI|2F`5(#*0H-n0nYX!6!M8!XSzqufst>5U9PjpI42p+fT@_|SR-0byV6ACZ>h?#sM
zFxCjuKK@N(VKet(n9D%|JB)jJ$?|aA0r<H@8=TFpJgYg!9|Ns_{LmVOX<O*0OtAzT
zJx%W}oQa2E(!#h9ex1&D(!ryXX@-%r4<U03918by;;v-nDSEWEca-5${)P#Iemg?V
zmC{H%u5-K9dyjV+bWIDQv9mRo$_KmO;c6R&MyR1OjG7FSho(yNNim;eCZS6WUA~)E
zdpaHfiX*6CAruyGcsj85NEcp^lI8xaW*R5q3U3e~t;<S=J05BEW^*G;tE-Is?vF%J
zSeBK^Gt3+(ohZIVgV)JN%I|#G=q6%jo87y)!*SgaNrXh+!9Z3Mn6}4~%RT}b^V#)?
z8mnTA^jEF@BnnLJI*BT~?=>Sq_gM*&Ylxwmw}#J`h=3R9(-AaAjC%=iI0y%g{QlNe
z1#g~<Mlahr^SCi`_6(!~AY><9HAl{Fy_g-SoKDlsYEFCowF=j5rX$IYxmZW1nXw%W
zJfck>zBbm`f_|ojORq99$&}PCcSRMf*}4>JJ3NO7RggX<=@d`5gUbdnB<Rq-^+rHF
zHaZzW!*(o5<U{4^9c1UG-D3n!`e-gxQJMlm%6b~xarwVc)Yy3E7%m4fl`L{V<;`8@
z$N|bT%9MWWQ>U30Ul1eh!y&YFSz!O^_yadT@i$sW3rkV<4K%lf_o4Mh<4XNxIVhto
zQK7j=Yv}jLyk_UXkXz+NrKhuOItE#*#+5QEmnv^RK(3r)gY;}p6Rc7viuOoDB*(?e
zc4paC!s;`IH)X$I>lTo-+TcL*AHmt|Z18RB76petqwO+FZ1a{P_Ce3P{^%29FQwV(
zC48P*qrk(y;x{8H(3&l3as5K5h0e-?nd^}g9taYMa;P9=MSTwXGm?#(l*{lM#}(GZ
zN7XIpAadL@9u$I!pk)L?ai!He;{i<Q0-@g!ItM4<Aa>7I9<}$epoN49QmLI5P_!aT
zt19&A;*I~gXY7^`a`G13eBZ*#&n@>g(W3w=p342Z+FJ)d`q3%#mb3+WCBO1_OYYy3
z$r$)auJh;oAL(uUIAi*wx3S`d1n2oGShLbG=ErTw`KQiu8!HBb{{IF3{=}BsP1(`B
zCH;|j%WZwoz15c2uN8lcb^TLp>E9_nbn~7!`(n4S;*mx{iCL?iNCB*t7uADpzXttT
z!M$pCsUGlecu|8Mt)6-Cr}IMy8u&Q~9kr*atK;3mjrJ#2j{31D-&^?upBxP2?bjRX
z7xg_Wuc%*0QB>TVA3XphR{psD$$x*Ok@7~1FX|mHU|K=iA$PIUGwnr!rkJv$JJ@9W
zH58cA&dDy6yGbn$myBKo;&H5;F<e5fM&dQIlP5>AF(prn={Z|FVj~t{*u{1u3&%NW
z%ZihDsNCBY!Ibs$$Q&f{k}O77NBrQ6^J@1bNUt5%bGAS29kXElCiXfzXV>ls20Zs7
zP~@V!v&$#SNx_pf?stFb&hh@`Vm7&h4Tsv&*k-WFE&#r2rE)C{f7|jBmlCBb<#9xe
z)4|2Ocfm+pa(0@ocPB2h?QXMmIcCU{1dHM%w^BE2W;_tgiuGArJm8gIyO>2-1DS?#
z!OvE7aofB&V!6{<z*>Zk*`>O+*X%fnXpr+SkO7-(&6?=gHqAv8dK=!;dFwlmM7i6L
zSV0+pqDY<~e<%c_wBvWqz|y_5rx*>%4L%kq;wR}1352as$D}JE)xrjrmEwRfVO0n0
zy`mB*k_tVb2#XZnYn5v5n8+v1SW5zp1_ij5eqBVA2<rvgCz&w_(E&PQHRVO;i0Ny&
z-}}v<wJ)%A7T`xsSIU&bxnKvlw*Bl|Idx#0@oyJ{Rl|B=KjohT%K5>EOX%TPhjN!l
zxt3xx7jtH?BRDMbSU`LY+CyM6oQ?z}hR5wo_Tq(nUoc_JhzMZfb3#u}fCjKDhw(a3
zp3sqeXQ&yO7J8SS3lGXoTL!$a<8}^jx%|7Ud@pTNm1xonfB}HW3V{%wXJQ5m5u>U5
zu0?o}$<gfuRf@{=M9j)dD82-9j%j%=p}~`+NJTL2+I3~ISvZmK3Yv3v7YZTJ{3Vrm
zRIaou<R%2{%5L%MYy=qaq1l;>RuYHcg#C<Y6lb$z4G(Fth)7Dnwc(rp`U9I7N{-M^
zdtvLC)d|T~0Yz?r_BgY>9YE{AST<*^;glJ*!=po^K{L00lVRrkg#DeM2nO!EUCUw4
z3C(_f*u4-T-OJ9ZLcUjHTV}gVAvJ?eiRNbeu;|I!i^NgtReM|6T@dwe1dxQU1{0<`
zrre(S+(GXsfe-j*TY7E#zNR^5>}Ys1*XHFXtj2heZuK4s8aLnkr6ZOXGN<gt@YuF;
zx%^wbGZi<4l@CRq&0Z{V0-ySTJ?Rl9=!Lx82y$Ca`-{QO;#01pcUs=RwO=}F%)Cg|
zKPJ&pca15@>kJQx_?NB5L}Sf+F68CG>Mk@Pf(&4P;#aLp`I&39Gn|H6CE3ZL9pVm*
zn>~%WEkm%nC$0v;7hf&s@-rO}T&o=0{-I7VJ!cuKgXR>Gk_JOw4nX4<8_W6f%*{Xi
zs^+JojMkdHGg1d>8k-GJF~E|6dxnWX-)TJO0LdkblMP^w_<4K6knpB0-wh%vWBy^%
z*$)o6<g_0&-5?-)sgQ>suu0T`EAMpOZLt0OR@LXI`qTiw=mU+76E!;4r=}CpwV>gw
zy1x5+@dXjiATbFNO&kPKmvqhcO}o%rj)lPm^K$6r6MkO=RndfBD{Jxc-67a!n6X1L
zKcs<ek$pM<5x87H(@kn&l8q5?0C|cV%?myC36rmzCK)CO=Vw-#)Yv+iCM}NI7ANu~
zxg0Ug_2}plmT@2XlXoQ)Y|1on$ny|7{)mc}kaSSj3ytxHiDkpin_7bRkTTHXCrrt8
zab;%Q?~a-U-v^+JpKt+;IAcf+Pb1+!WufJ+c}L6{b3gO1K*VJXh^S85N37s5+U`#J
zZ~egAL=rucBYqE5bkJHtHY(|Tk)(H6ot(?p7SWX<btPAL#}2ro!(N-jl|bvMbj-N%
zWtvm~0E^WDB{j>A>*28^Xp1LiLD;~!Lw7wY$i;}}ZjkGX2oF!3!o_ooRae`PI6Z7o
z;WJTejL+N7AOCOf+7zS&SUR`D*G7>fP(B%J-39wmyzw~h4t&+P=ieFj8DF)E>`n+X
zgpf=Np?Rkd8@qBj(5LkoQ{M!x+pn{_BE>OIIm|YM<|F;5s=#7(mORe7#)kWep1qmP
zj~61s#1w^p@k&$_tWvbIJ64K8JKgCTvBj_z4Z|_k$`Il?9bVpF4C;8?s#Ia26zH?Q
zqWXrgcRg*BOFGC*(P9l&LI~Zlv4$2Pp{t|7fO-<52D%|J26gbn+4|8up+=+mgc+g&
z(kExFBU>nMHe7Z7kGrk-oxQqIi1M8TP3VvkCK;|b3r3$8Wq8l%r84~h9O>`C8Gxpn
z7c-H|Rx#?`PTp#=T-}Kp4pQxIzAr^gRjT{LC1n^1n_S`*MC3>^xC7mDm+H`_v&kwf
zCZ%)z3stbgh*sBI#}o*Q8^hStMu0l`I$Uicp}ZK6;nvb42|tEqu8RiHwQ<?jd#eHH
zy5<56q86vKr4?Y7jHMYCLn|q(jS*RpjK8}?h+w}^U{^j3?h}8g&9dkok(&F<Kc{=_
z1(dkCb;K%>ui^(jOk}#XuFn*sK8g}hl;eQV-b!@|0u8Z|a^Q`&*tq!Kkm*&*UQqC(
zt!Q1Ru>tMXiHL^`R>ZKnh)l>Jy~^2STTV&e<n*petg@^P^5u(NB*;dboTk0<3G|+#
z&8$J+`{WInN|fEyd?oqL$xcF!?(;mKTCjQ$62H{rTS(a=$Tddfnvm0wL^Fq&dtmnI
zM}!*5q*z{biHgb~PGw+XHSrMp6p*<3jMO!6R26H4FC7l(&s_SMIon!XEP&qXi71;V
zb&G>p9DJz$L^RNu!EJcJ;U)n=8&OZIGwe#_bi}iQ+8o(_=*osfQl{5fAsgjHCh+ox
zg_^nM_O2rNN|m4`szc$ZB9dZqr!i;9I<*`$t*>|@F*5hy|9Q7nh!Q5jz*r#XaPqBS
zaiq+sROZNAF;Cv2Ma9FY$%Zt>mx1IHP8l=n4ILdJA{9Ou{Qd@BM_<60nJ&gQ^$>c{
ziF6nVssbN1JmZq>QJu$<mT?RQ`ypnSh}e%b4APbv2%n8~?KD1>xZ;gNz3x3>zvw|Y
zcoA5)T&snn0Z?UYcUU*@#HK5?86}sQwS&dL?w$<LfvUpQPMqio6Rk&U+m?FlZ&u1X
zQ3#*$tXi<TF<Qzx_lV3lTL;!>vzeZcylNzNQB8M$0H9*Gri{Fp%@{kskCfbbW5PUo
z(>0#W_6IHf9^8mI@ztaK2XntETdVFrKihxU9P<9exVJH7Pl-S2A>nY%wl$Q_+<4Ek
zpV-{Ec7Ce=Lo)HESIw*+FCG;Cv13hU{@U2N>@Ay9#?#5&t;%faf$pa9Eo<C+sp2)q
zjn-&+7;nHX>8&l+*NsAZ%GNvP=$N+=#Q_98s`k+Ma!?xY3{}FHJ8N27j4p2p(ljpL
zK`)%mR9fFCeo|Qb%pGQDSuS^0U(CGU>s}P`Smp&3laCG={kaD+`Tm}911fl8O6;FK
zES?nZRDLRZ!Zn{I;ymbX?8)6DnpvweJ^R2=HfwE!Zr%N7!SbB<w0Jt(>wZH_bdqys
zV$MoUc<bdi<fG+}ZwF1@vVtaK6c1Y-NNw3e)jnW8x2(`pa4w-<{@raStSGQ^)O`E6
z(xQ>54evh9bFBid(6XW>5Mo){ySE3y6}72lE6wxL=%`8pzo1CZP+!?8vmbt&|2)74
zXBA9+OY9l$^V{|K_9;+%dEW|5{g`?ly!E`Y4}V+l1E5^?-26`s7{I%K$pE=1CG^%_
zUjZw-pK_wl1gos;c5-`V_qs|@s_ahQIA*uLSvd=hv$PxN7>xHA3b98mgYsilvg@<S
zt|<rj;?b|a-=Q4XRH;%~H<g4-nQcC1tO?B>o!y@l=khtLdq1q_9l`D`u!moLxiXrV
z7luqw+3!Txf}lWNc#k4V1I;d^h8~-}xBBakwvV4x`WD?~(J{BIOYyO@#%9pI&wsdR
z(asM}fY)vRzLQ=zb#VSG|25;7;L871o>9Wild1FWgxL30Nrkw?zAxu)e*S+Qnf&Aq
z!!@Fphbw;4s9h@g%Wc$`0UZrLsUJsi_y)f!3EQuq?BX&#kVcRPq@!CWtleME&Ug7f
z;<!O&2`2J#+juL@KC3c3Af*SlJk_j}PNqz7<7b*MZ@Xa!`@5a_lm>CLIt#SUi}y&=
zydVZv1zh81a`{29lisu9nFh?+F6gYSGC&g;U;n&u-N{hN&v<Nf5Q6kgfbv<(NT1pK
z%2fkVjq0Q`a6XUrF`Pu1xo#!478R6MDS<3=!=SHP+{cOn+>DaLeFbt4k1Ld_gl_aM
zt3o3K^sH%YD^}Wv=i`XVbE}JkbcjJcK$OM90f{~VH=_Ywr*KeC_dL=)C1Q}H-WuSs
z7>M%&LTPC~D+W^D=j9+MVYeP4{Qx$70}e_$o0_hkHGaP9ndYNs_uX;WwlZHfBi-M3
zoWUpN&(ubfP~o42rvB*U_(`Q<F_5#;^5#Ql8JRntHcWIkMzxXM_bLsP*kuy2F1Ni(
z#U44<oz~IM7-^UO8(I_6D<Rr|X!L+NI=VIs4#xNNG?dsvoy5ar)9abffuRpHxl53>
zX)l1YW)D2tu6M|eK~h>3AIy;|jbMlcWcnrB%d$mXIovh3E}IA3*p>(399PfoODq_d
zvkM@pvvkwuR<gExV5mBMkIbz#{nUaS+3pTrOq7nvzxdW2yDX1ojAX056?5A2on>Oa
zNNxZkmUPC1M{bfeAoY^xz17PKS8ID~;cyaZvKMy=5I&=#;P}N-bXq?tzux;gOnleg
z?aaA{ZEnk}ZR~}W*Dkj!&ki&imFd-BmqzzIC^v&K%iW*uT7b7}4TAYAy8hX%iVy#I
z#x`d^D08^n&XacS+1>A$u1r6$kU}_TP(lbMTjTIrNBp4u?j2$ui=v?|jqWD0Wt}Dp
zNXk~((T_*fjL}AR4K%z_PtoUJ>8z-o)I13>*f+!7zv^(c-i>tHjGvWEt#d+F{MPS6
zkX|-0WDI=x@TI2=Py#auH;Npj_FRA<3v~?!8NS^}Kj=I?6Pz-(8nk@`H63@~mw|e%
zM-E7@ygW*i1A~!73fIq>0|%^OMZceP<aG6mLfrd@cb4|7P7A}r>*xl#wH%{nln_wi
zf=9Xm`w=xZr~qel2gD%$GfL%+>dO{V@NT3;tRb(}y}vda)i#165Mcif`JYq98w`>p
z6h9SfI!tm2>LwbDa(cR5hY%i9Nd~js0rSKHNw*MBr`jc3AW-E8O|y2k`+SNzmDNcB
zvYE{lY9(`R^7s|M!88N3DeWmjuP-IcE0Yx%-M{yMUi!dxgSl#50Eg8Il=rT9-0b5U
zQ2Z!GFIQINVv2h!u>NZ=cb~&M?f!}Y>?QDJ49IHxd6_Zovr?L0$F3$7PaPr!eS0u~
z45B45yKO6(s+=&A!k8UO>TzNMoshsxvl4VIWJBgx(xZ^|7Be^U6alsv|CYC(R@eJm
zzgQe;|8AqwXB?9wi}grpR9^q|pWzq<-BIN^u`Qth7+mMN{xWW(9O&463t6v^Ng2z}
z6xsa7q#GXFFix%;dHS7D=9-lg%tqq~0{||>VY|S3ij<^I89(roVG7n9W4A@EjRw`n
zG>beF_N=o-J2<CZzJ$W)32BB*kD%}7-#jw*Qb|#e2-=f4Mx86A$V`@!>3?KpbuO%k
zHg~i|ufVnwPl^1cG9>8$_Qx><JaEDfx7eE-auL5xLEGprSZsxZA`rG_J&-BZY%l`E
zm3tbVeL_fNJ+3uGC8rKdA0=O@wk@9^#HUcdPi3SxrxKTb_n<mDf?pR|DZ6{bxeZU#
z(pzlkp4YYk2miEMGU=)yxz`d1E-L{I{3(SiUo&qQaGAgCsb6jhdd%IprMEmWrv#XX
zPzCwsEe+?@E12+KC2nz<uWg@Nk>dDqfEvm&Ky~<Ce%>M>^UIH;-2de>#e1x6EAq{U
z5^G%=boTGT++S3!SviYp74gLImtXkFv%K}AvwZYcTW+7^+W!Eb{tWo^`~I2JNJj+w
zV75z8Y>Zp~GcvmPcU#MuxBQB>_tusg*wNP{Xtl>^WSbJdbPGaeWNONTS9<_lclC%b
zI_#&0319Hv-~5;Vi<dn9vBBfP=0ht0Gw_@GB%e~-hue?a2=?25{_tmf<@_s@9$tIp
z6Z$_=V#juvDEnpKD&IXLyco6O+YpqX35G{pHo(}T5Y+-eN@*0fY-w3nYF9gCzm!W;
z_UmD%o8lu`F&#N6I`su%A1s~}9=qDG+G0;=pnUEwnE7c4jV2Sz3}#G6BK*quN5u@J
z6*3};wR62=4a=_FH>(XGW)W`7Gf2_f$V;>YpI*0fg3AuHm)Hx&QMF+64+v{S1LnyL
z6f$}Zh_(=R*mhk&iq{w^&#=F<%9E89i3s*jEUIpcP!2>=h)Cu%`N;KRnfhFAP8On|
zw(y}n;4AH!@r%7&^&8_%e$)x51eUcgmz$BkAaZ^Di`vUNyhjpMcXq5WAoJT%dqZ#y
za2>-BJJe?g(Lr&ag&6c=4pi>B_t={EE#YltJ?#irGf6y7Ms_q#ik1ZfJL<<B-5qPF
z@^6r6#LyRnHr6P`ya7S9No1n+NZpGBeT^uDuoi-`kpb^g-i_aV-9fA~*1S>rss?#Y
z_iVrQltK6)4E@3^HEH}{#`BMhmVp|%=MPORP>}72Q$WASZfC)LXNu^BcwXjiKkS=m
z9C5q>Jt;{-Y?@EItxkTZxW6&eRlbyTPn%CV1ls#L&|S2?R|8#ZuCkhJ5)aFGv;g{A
zPaWuP>maRayg-=L%^`{_=^49yLu|y>l0F<OSTJ3mG}>M*^h2m%v%O}pXi^@>*MP23
z(jP(|yjtGTNW{QQ+MT@J%(_GROcsG`E+~|`&n<^pEu>i|yoio%^P&wwYAuEJ%uR#!
zNQ!X;5KcZyHjkRWS-#u7E_%H&DZ@7!mB!ljX5cp?RF-=wB_gkU?Va^3*o6;(ec0$D
znt0jMTjavBjV3x{O<C{`Lv_ct?936I$Zjdbazo}>@v!iMrcNX#@P===*7W$rUG`W2
zuHY`p=dH#mf$+(;cgcgru>dOioZXTgGsqFc0R#(-h%b?d1~-Sg%;|^p0ddi(&st8x
zJ}Wl8$K3fMk{uGkDtnVfn9z6G)`_c_@2q?MU;nfC9oj*-iNjZbSVX7SwhEJTGmz)m
z(dkX&0Z{N*^I~su&dR+s+Y3tjqGGIPULaUxl;2}#KIWM(jeCiF@5AOHVb4r7?U@C!
zu_qb1;5^uwEQUKH{TC;9G)W>fgU`>-%>*~3_3|vK!~@=Uf;nm&=27xpE;jW3fayEa
zWfSko2g7=hxYVN|*s}Ag#J@A4s=G}orgHmHFD7{+KO{H1?`u0gIHDp}D%zk~aKOFc
z^3vG^BZ$SCeY3rbGx{PXOzBLZ+Pt2&!fo)vx;|27DI74KLf`y?yD8)Ed{(^C(9?H?
z`Tk;bJ-k*OaBZw;Iw#G(j@xItlgKiIUxxJt@P^yBs*ly0ISO{;z3}081MBMA<(;tk
z!o=N+@plyLs1|@j3mkPK?6w!mu{jOp>`?Q98Th4Td`B!Kz}u>W)nS5KidlbhJkzc?
z@z@C)0dPDZfTI9C6`1!h{1h{FBAC|#OV)w6j!1C!_ECGpg-QlG!!7k9?&=4Xu@8OE
zWo*aq41jtplX7uENSNt}Rd6EpMq~+-9={tP61z=t*K0)`V_#n`QuoZ9RYi;e1hri~
z&)c%$#R#uRwHD-n;{b!OlAqUIjqs5^Pzf~I2br5<ps}DC`ELIzt_&DS8`2M3J^;1f
z?T_yCJ&ctJwp6h8by;iNit*_A9>kJ$f<|$>TsDk56=>R3>FqL&We<imfVkmqHhPyI
z_q-EE2=E&iI(D{0&O{+LyQR=|>7D{Fc)BQHcMBD1)v2Wk9Y=2lm1JL|7}dmdwZUw@
zcj*q#_X#@y^iAuCg`lEW@WDV0pA}PCSxu7wfhzlFKzF}o?k`S9E)emFd(jI{n6P5~
zq`F8CM@~jyyAnGi;CVsz5uYiv%@eZEtTrrHr1Me;5;dWG>-|S%+$`#O5&v}~C()_5
z+(*9sKD`cpS*QV_g3(3!fugZq*MmY&wBXY^kbb1JJt6?g3aPS;eT_hGc3h1zi``}8
zPrD0W7T|s+@ZY$p(5ehfTCpiby^i{-I^(~Mpg$I$3L<(am4>zeW)2CE5GT>JPs_WG
z1%_{ocyU!j*XR?0cg(=NBEMmnJ%+s>sg(;(+$D+L!{#EpV7|-X7P&Md+$m)?`&h8q
zUT-csnuHeCkGqQ4yNCFPyTO)5M$94x*cfRXG{ky69n*SY>z+hJrkM)xT8p+v0UVEL
zhHmDZ>#zK-nzNy{$VhB^?O6kwKfmhn8q<uAj>1xJWsM_Zku(`^%<Q^oxkyt+N%$u>
zNgq*bvgw{QXXJR%DMTEEEi_FeCx`}U{oXP2NeLD9q+l`(vr-^%Q5O1G5U;qJq=N;F
z>ziNrr*+RbVc8@$)LG!!aYXCN*8z>EWqB-c1mZE!d&lwWl`^IONR9D)G>QuSk(~%t
zmTO|0?NyzY$-o>5o}{*l4%01CSfyO43(`SSLkKxijN{4mD@Dvcvlua<bOfJo7`)b}
z|DeVY!2d5ig_oq!>-ZyZvq@Ogo{cb4;D)oHj|E)<_D*KXeFvPj?wC=3QD98~;4`y|
zf{maxml#PE5qVFzX2g*YlUHTCz+jm;vxbP@X=-bvJ&W7ZPf*ve3GDXaBj(Ih<b$j4
zI08}Jj~a`dP~mvk8RI4NvoVk>>N~`YWq_yR)#sJP2qpPFzJJNZNy2Qb@<m~PP;w(=
zzlaX;+!<D&hywcAwYauO7OVCJF@g+Teb&(O8j(nvr4_PF#=HznZOb1ycsT}WFq5K$
zr|WlnZigZNE)0lY@Zj*5M8qSi#ihPu+KeqS@q9P3$$~EIm2C%>eIZ!3a973}i>_Gj
z)zD*n(v3K7eU&|y%Ip{2?QvB<K*pB?Gb`55kpm=+sq94H1kUQf=x&&LVyKcQc)Cd%
z_o2!2q$KwQ1&97h<Nl?08s5Rm@zLPLiXFb@{i)Gyov?>0wvqU_G1}{qsYB4QGSX|b
z*hYHCgwcJ1s%G};Mo-ZjpZ)DE9lW<=CA;UZD+l^tvn#y^&0h?TP855NipmFr^ZnTk
zz02N3BXeUtSaW6D>Qw0)=>x{oKmSy3*GJ}OK4BinPob}C+`BN9&1W;S;;`BLwpb9G
zr-1kW(dJ;w%z^BLNPI1~E$|+;kGfyI)|kpmZz7wR$R5reG<tLS=MFq@abOGN;)4_k
zOrCc;PAi&N5UFcY%(=gteI$IhS;~@EanRdgSlz?Ro>A*eFPHVWz+w5t;2@En1eJe{
zZo9TK_-$u)bt5s`d)V0aRIl;0n{|7ZE#o~RC|uduL9ux{w*_hEgH>;}*E3~Rdbd4o
zjTbrifu2Xr?AAXucBFP0i9hQ-keL(rP{+`FS|-a^%-O+%#{Kg-qi4c!`^B<EAG+GV
z?Wmi|8mF?^pEr+g&i`EMu-P?dt{G^ZOBs&`ry5gKo10Bd^~@QE#p=c(k@o(8%7qUs
z=NnU9dDDGDoR?R{#HnonhW43P|79e>zINt@ZIuiV>k^#h72FzF8a#XDNx|4P8`Pk)
z1n?{Xec#JY)gqh_D?y2_m4_PR!4lfdK+dn1*!bD%k16XGLHf4($0(JPrg}%W@u?L#
zYDyBOS(~f&FG%${P7DqKFb(^fnup`TUv|yIzE=7l%}Nd&e46JcnoCbfzN@vIS^>6K
z!0bVI)Ng+VinN(-;KJGIIq}Qix~nwWf#moKT-pQ{t>i#w+$pIk_xfYq2u1wnF|<6a
zTHD_=bF2+zb=Eor@bbL<z24rw^KJuh2c1&Shf)1?VBV_x=V9h}5m|;xW$^q7@B893
z=rYCP1e9gF`&R{`9giTR{UFd$_3YGYz~gCopMri~&7RNQw9T&5a^0gzkHm7Z!`*r_
zbsB7_lsKPnR_39bW)IFg>r#P3eLeZ;K4&du0=pm0t?Oz{0L`weg0(a^2=f)U^83Hg
zO6q66AP=RSw7al5Omp(TeGs5jVe-adtAwgDc;F0S>{jiHpUm17EyU#_ng5LOH7cG)
zMwSo~>A=U0?0((2nTNs%A9nPECQ#Awze}e91AR)>8Q&M_K_ERvp&mSCltP%DR;eLh
zy|kjXp=wqFFl`=q(SBYu7K}8Q*hp3mu3B1qKA);&?~xK21q`c+c1mfF9BHe|k*yd!
z&T9J%aB=vR$GZlHC|n0U;A9u<;dS!U|2;NRdLvkdHx8e;HcIJkFJ8NX9PM%Y3?16`
zI1TVxr}ErJF}TX_UT$CGHUSEEpUH)u&rN(b6GWDNO`MTIiHe7*0y4Qvdv^o3Lr49x
zxYqoJQ$fPy8c3qi1zLPMeclA>{{5}<UFPu<oHL!1$g6BE3O={?6m0D70}$r{MQ^0g
z3i!4uJrl&$D}Kp@jy=0ZK>j?$EvvZQkDG(~U%q>A2paUE&8^7wXFgfSMxP+A6}D_l
zyaz*{JdSe3gMAzLFktV5Kl|H=#*B1dcin>>i}4mA)Nn}peI7*vSt7qK2hih~mxLlz
zV4(#`s4y?zn>W+*5;21`mGru5z@6>ZV_oYu+ZMrvAu3=l<eaTT!BF*ou?WK$M}-Q5
zWP2k{`i4X>Ac0VWId~PcQVxQ<{~HRN4Q7+viG~*eXw^CQu7?VvDz|{YM%p8zUFQ(!
z0=_nY9Xq(-B|i#&eJ7z4mf?bNE<aRO(?E`l66}ajL9){N#p)o@hF^2eFenvZ4Q%>6
z=6Sku!lG~|<lgi40c%g{UehesQtQAHJ^MV0=63793b8JmG_qpg#iT&YfRT^5#mY!b
zE@YEv#~rZWqSR({L5AJu%`Z{%GA%(}f1mwyz+4#<t!GIyOMX8k1|#Wr4@Rgs7hjOi
z{PE8WRYqw{Yt--7M@D;b(};o$YbZL~Iwq@EF?dgM&Bhu*=tVzi5I(*DeR>7x{FbGH
zDc#@nBjM}4VAws~#Dgek31*ByS81>4U64U`o$=m$s~AE3<^G%*Q5d}0iYOTS%&!QT
zPeJQ0N-#g8l&QB6A_%&#b%|=*0Y|=(l7nUq_~vl(_@`1N1T@s0tT{r96M{id=5zlv
z;#(T=3~tA6C8h^CxE3&@H4K&x#0++hGK_V|SVZLnqCH49d#YsR7-}1jDt(jrY|zSc
z%!uJ)!@eRG3}mDGyqf~5v5~sr=1)7^-4orb;<`feos<N>K1oi%S;j_HtPx=S4oW$-
z6beJB5hQ;IH^8y)M!)>bi4;A~5IAYP$sBUT!Diry2me5asHN?uD)up;xnvXns#Tud
zj@^q#L73@n3n`ueY~E*3=$;X;jk-zQVC1x*4!14|ZI`;vHiT-}sKiUQt{OB!Uu$i|
zTxN@i(?o1@!)H$BM*amopuG`zs|LDiMqgx0a@F;e)PjCOUT5x!1bfMQz}iL%Hj{VW
zaNO^{@{U4O!wt6M{u!aj6Xn;7(Y3bcQSr|k^G2cXvt857QQYcbVh1OU%O({ZtT<e7
z9|?3btV0o%S~{xqID%jx5*{hiI5YtN<5~GU^JP$nS~@YWRDyxMmwchCoPZ5%Z;wZ`
zVVf^Y$E4b5{qY~aD=`f1y<EEWG#&)t)U3Er03QhTpss^L7h=SP%fv}Qo^7qC7%K%s
z90KiRc4EMb?PL+;C>G8Rk<?*B<m`Q9|8mZwVp}W?F_m=|{NjPk1nX`?ELTscrF>B3
zB;`P~fltA!b0aw<Lbk3fuKl0!>^VVU!(XxI%|e6o-(FcSie0ZL!1}X}s^{?WM?dRi
zp0-y2YelDaZ!2%OzmrI;u&F<KOE3dHv@3&Oc^&US32#)~ffX+GXWv%L;3RL^r+*p1
z7#8&DTW5Ku`u*RW_$U~4?X6pC&wq|!h7!&|F=OC%<-%L1q3EE!q7{9cO#Q%5kg4C+
zjQ)O09->hzl<c+c4{HtHmhbqDpOWu*yD{pLc8)inslJ7L$4`LObkkcuY|BrPsR64m
zy4+hf4Lq+r;;}yXZiVPUC`Rf<ct(hl0s^c&-iDC*6HP?+2yDC9EAUX`^!8)rSL=gc
zThX*e#GID{4!8wKzkSf#Kh@W3<+uM*KRK4|yatx7zWesW)g0~m(eD+CTY9H;;DB%w
zcNK^hHZhq1qoHx6r%9a|O##;f-l7v|@Da6{&F>jDo`biy$;n)D#yU-Jy^y5k?KfL!
zWyfDD%d8V*%D&QNoDpQXB3z10onlE-k86`{^k0-Y#2KkysAt?FSc%92p-g8j2{sw#
zGT$+S%`WU$a`AokTWH|E&|BU47oUq2Ced?qA&B{*d6!3Z^Voa5NjPgwfq*j-&Kqqr
z?`3=lznK)wYNrVN5rSuhkwb#YTMgo1ySbXe7Du%VQ<*HD0Eo(w_UtAg6`d4)-aj|{
zQo8GML?L$AZ1EWn)*+j-@@WBrK#BJ0tTPi~*Y~95-uT)MO@tk`h<C4nFg9z+gGRv8
zAM-s5^aNU8hcs5OBOs7+JBtK27*JE!To*_*;Wj!}Jxi)}C?oOM&?>@I$nKIC5kkD)
z?_ZEeS4P5cgMC59r4GR@FezwOhx$kMtT{BhMdr|S_^J>`-SB1Isq6J-V7SG<d#Ian
z6l3q62lg-7qha3^siRR}+hm(#9wcr?VhjPzdZXha0i$`|SYyV!14I=jl3kcX?mTW0
zYYPRf5p}gI&am%wG)?Oh5gEe%D%lb6J9uE4AdlZZt>s8Z*0uZZxkGE}9?b0MkQX_k
zhHwG$sh_YSrE-K#zaItKh`8!hY8hjWq%Tq8i7%dJP3~J&kBrlH$16jMbV8eKqtJ}{
zbrdMMr{+syyjYKTGrE>TSHX_fi_sx=!ST1g@V890z)lRu%p=Jq!@L_Z*G#3TP_BeZ
zc1_&j_|v)<#ADk)W~68~Om0s6jv0V8H`pPN`i`JEqdLg+L(n3?;Z~?8BkK`yM%>|L
zeLfKpBjtEB5hX)D5j(Peo#_)7STsGbsGPRZiu-otuu~wuSa|E&xp-8t;zduN4s0qh
zlw#oDQ0wB~JgrY31;=nZzDeMZX%>k1YmC1O_7QURw4qL~8%(bvbmO@>`hHs!z_lJJ
z<f$^$^xAr9e=t*Y4WAw67_01buH4iayhCz`v;l$?=WVlW6HeL@ggKYN9Eh%RjIKLL
z5O!7l)qfr-KuY$t7OR=Z<*=CS0`+4)wb7pOHO=coaA2h?J-gn}-9V11o5PKQh8F_~
z>qBN0sCc}g(fwnMLXHScJ3_Vu28Q*NVaJN4Y0wJmIwiq0?Y|9bjuWy6;Z~a<jhw2m
ze}1f?Mrfa|z+UZ$Ao)R=K>mT4YJF0HC4DSZQ0o-n0`(XL5!)j(EJEkagnC~PG<1dm
zMNR{szTJeq%L5zZC9n#HD%J-${1@N7o3lD`IwiJZb%8l8hZwl+9dXPf3iLu5o|f2m
z(15y5*qIS>fgrFNo$3K%$Ae+ctSf|(_%J{hy;0a=ofL2Yqal~WBh;?n{~u92ppLX1
zE8M~>e<Yp6DE3zls}o_NV?0i(I%&nY1KUKEC$e%tyvPMB@};)2G6X9x0^LQf|KdyJ
ztlx1f8tFNGfP{rm$29r{r&?5pm13e0ecQGJAgM>4{^tv2z^y5%nW}01>U)90`J<nA
zU7~5~1$3+b@IlS9d_+b9HPKtqz5vc9)|W2w<9Bck^rSkQ3qzIRK<GeGmifC7<w_9G
zRm((yqtueb5bDz%jZhbV-)f9wYu6wCH~jg-hq@XL{D1jSH&9&xC%*lO>swyC^&2M%
zITh&nt;JQn8mxpNRJTh03C+9p8jbnk=Wnftp%xIe;9VXLSIOmG-?E24)N$+r;H66V
zBi5#n>ld6>T~A!7?kMud5Wp#4#-~7aV=Koy#lDEPDRk5j=R0m6ZWbgR^~0C@ZhZZ>
zRvO8~vi21#1CgL0{RLm0@!>YSWbBg$`<Jh(a@HSvk82|;s+qLUkljM+x88F%h0li!
zXh6?s9}C2fKDWIuvhp77q(Ob>{?i>a7krhp9P)8M9C`4)Jg^Q}=y2uQWuJ@`q6N6U
zykT=J*Aj%xtw=pmC;~38yv}=!=Q>@*HFE+Ey8iip631)zeYS$!kWYzuNndS0UyO2X
z-(h%bK`T~>zTwRifr(G?HgjvjS?9Z&wxj%rIzV~-zQ$Go*>QCMo|HPE9?^#03PaW5
zeEE-^-duTGs_T5D%*wR#{n{V@2VFI~kH#4++&{cu7&4j)xbu^@api8^I+zPlH|t6I
z^M|j_auv64A)n?9*XPtpX$G$=Z|q3XBWV<kc#T|QO>H57dikZFGyU-8!dZ2AuyQ!>
z4c|UGTsh0%d%5uRZ@-i4jmJn=*C0(T(1y$M%c>`bRYzceTAV?>dx4$n0H@thT<7Cj
z(ht1x!*~CI&*IPg_(xSalfVDjSH5&dNHgh`K0_#xBh@V>N7>DlKK!Yf@DIOACM!+h
z90gm@!ndc*O3(i9f57Q^#G@VM8~o_O-T4O|%x4@HMNt2LdR+MT>SX*=p|1;Su|xHT
zYmLPD>Uh*s*(54n2jos?YC>RZ`H2<4CPO<S5~$|6I=yN^fvP0sHb-+je{l{{wEkUN
zz0K)-JK9-%d-ANf)!xddZoPfGA+)uwt4SMEqn7`9aPO!gs;}IFl^4|0^*`!<Qrw*I
z*z0}BpWJ@He@!~k9qn-F>6uI6P;5FdUclulUo{#B*o50=c3ts-r*41Xnt$mt+ixz0
z8;Zs7|NBRt49ofOPus)!kYzSN4I!}B3U{?J*bv4!d2DF4ygzYF$jSGGAKULdGJNHK
z+^*;4v0~=@L@0}YMXP@A(RURh1~)zKM=+KFo+U9>%5dtNuxpN%VMuun)|Iq}fRV=9
z)fed!kwRol{^W;7+CTM{ng7X85t&*!-*+ikvVC^K-%uPnR*b(^^skijGpO$!p0RiJ
zHu2`4qcT8_5`w{_<{J5-pg3XmZ+|VbWwAdxbY=VSrSQc|Vf@mJ4KpCb;c<IXO`?nW
z^s<;pxVO%{edxL3rf|bz`0~n`Uv4XTub4R#%sp`X#J}*v6U$pCF5W)zl}kT5IJ<Ii
z*Q-)~rYMiCwD`H=EAQ1c3Irt1k)_u&Ph?Y!i^7D_T{XH*j}TcrGLMRB*di%Q>zg;;
z>t@_jrW_Pcq~4I{<u#d;>&?;0@zS2{-agB!5-$o`d&~Y3d=WF}A|@zPT@kXB=Hz7w
zo1;20=})o;@H`@;<YSqDk^`y8`YfpwazfrO&Bl4onchBHd^25jOSPGj?NbU4=d1aS
zhYeJN&E9!pqDLS+cFg2>7GZb<AC#RVE39RctCu7rmu#R@Dc8-r14Gw@S6q-A<-j%B
zm~-|;_U+l8wm(qxXr;GQ8(zf4nxXhgV<9)tn9AjHW2p^Nrsm|sa)<QB(_pNQqpV&K
zutHF5P#xGjC$qWxM5aoE&&y)Yc|@8Ci?V}f9zPodTENo9vUB~<uJm;*6o?a^7Z~0-
zG#k3*4Mcq$tGi3j5|fOZFd|#AR-Vf;o9ApHrrZ<x!G$cKX=>icoR>ExVD<gvr8@UX
zNA*gpRxJ5t(&xfbtsRi_*M|QPS<i7AAx9#QLZqwy2;`b^kR&*mC(ZmoBl2E3FrVEZ
z?~^HdH*Qrk<4(zbd;q<GHkfe?5$9Ul{cgW*Ka5%l$WCw8uvZ(X#g7|n%tS>PTO(Tu
zOB0xjN6ujFRyqW}?OB73sA~8^&UFgK2|7A+z;Vny{`km6580JY$)D+1!^`13)R^fk
zT;Ck}7Oq$)oQ+a7X#IKTyfp9dok_>RWRf^&(`xp9O*tnM=gr^%qwFI4;<UL(?yJgu
zk1wzrC`DU7&8Xj;+pj@W?_+&WfX{b%1R2e>NR4HU?g)uoYVCwf0d;nyJ#$KCPPo9s
z3<a>x1v2Pp@QxyE?kM#R!^Ndx%dfp$8Vz^BqKzHO9&xDv6-gX0b2&%IfyjN5JHC%h
z-#b_ghXY!f1Y8|BwRwQ1nu(hxcWOe(dViP$GyAO35B+8Jql-&>%bix#59#L<?v95~
z8a`g$vf*`%%f^(U-z)U)$ktU`BM2xn+s>40?LusNR&~N5LmO<Q8bSuwq@GbT?b-xG
z*%2jc`{?$PT`iY-{TP%N*b71HY;Jm<lF@E`Wz_UVh7QQ8lOElk-t(c6qF?ey{R>u~
ze$uE@a1&PXf?Pi#?-Ne?RYpYL0UACc)5Y3ZXUX0>)1li6?Q1XHja&4v!m2@4?KQ?d
z#%hK`Z>LKchasaP3K0<swd6KCWXmRAKthV`<A6w|zAbgfT_2eo*`6}ZJH}hJiyhx<
zL2ub*9}Mc}>{)lCd)Pgh8(0t<a_h_u(p_&BFUsd-v09w;)1y)i26l0{Hj)-gQ*1Ov
zirJ=y*wCx8n&Fc6ES`CMe^}bvUZQ`Q3PJGc_q=15Rf?K6>DawYxpBjE?CvLwtwWW~
zC|lnezczi0x55@Ye%8pa>2nA0Ve3?7ksmYt?UuE@Mm7vok>O!rDQbf?=G<nAMPftF
zL79hPD+eZI+&Ax_m!fMeCW8>cd}>h6cV({0PL6xkFC#k}X4EM>RBN!X-@VAb$bRdO
zCQcf|=PYQ?!LpGxEHcT|1WS4o$m<F#zKRhbSg{W?2|7qcG7R(qBPOXjwUEu2#hje<
zxTlkXa;GE3j$hh~M5R3(1k3GUHb31^)=4JhvV2rc^(s#?#b?r^6TagptBbQ<7lByS
zcgo18s1teK#BvOrm#@k>XM-FcnM_yzBuGb>m|!YyL?NY{-~5}tbCzl|8JSdBH+p6b
zD=}dta+EIH5;s<w44PLbj%6pF#sVM8HoMN61ESfyDuM~oUo<Bs3OVVBc%t^}VFw!i
zl6%e~7S>J%BI~+`a#*NW<z@y!szc|x1C2Rap1xx;Z5B<-vO*oZPmeSu(zFY?%(YZy
z#VY0`hk2sJ0NZCj{?Vn{Vh6jRe6AlHzY}K+L$Jo^UN$<c5DBz;x>hr8E7>h9ZV*;R
z7z_cAX(d8)*iK-|`WD1s6T`a^=~e;{*j#TU<D?_$yVAwcFlb$}pSJ?TJ!dbshhl?G
z9ZQX{?19{bTz`=k`5&ilD!0es+3~%SwP=<8#<DP}3PO;lviX5);=Bwn6zdNt)81b^
zmMK}IMQ`6;Cs-`im?5LXB?=*w+cy*6IBArkWPef~Xq=g6-DC7m8Bj{n9%}Z+im_m*
zsI`L?Z$^v<t+yz?Bc+g2xyB7hxf|r=iK@R7`JU}wx_9qGOXcC(@JW=y+Iq|WP6NSG
z8R?rxBW^IK2Ff~_`J0Thqqwg)I=L^gNBSQBC9irxpfd;?jd?lPI0|pqy`b*VaCQ5>
z1U98KdRp~O%i4R%gWX;(zm;1=3Y|pQWB{Kej)}W!2y7fliE5cvyEcW>hUOs^M0O80
zGmI4&oU0Ivrrzr##q(tQM7>fkc5w9N*2}$LGfL0dCynV&J~`)3V{hg6m=FC2<bq5q
z|3kv{ilnPjt<tDf3C5wT^_>z7C-XAzr(cy3&tow!6srRcgStHI<NY6TKRx=hyR5{Q
zE%k|e8QLAA?y)?tpE8C_om>rA-f`At)E@z<0c_P8vNn&Z&9oGe+@KEKa~=QPSCpCU
z+qYN!aHNbwG2$=vP6l7&;tDU=Q||soQ#Kald*yr0^-tgfF|=J5f{Wwr!-Vlrn>Pkv
z5*V1m%HPY$Z424=D%;FTI$6w&77LLyn36JCUdQXOjMUnX{JWnucNz{8E{XPGaFtHJ
z0rbm4Z4`(E>noeu7Fq@|Htw`{88jH)rjZ|vNE57T;9Bvb^Mq+t9j{faEe1<_+l%Hf
zoP{>lB+2MF3pvfZCZ<e$8Z}RZBhsu+QI86U$WM_+kMbHTsXOq5NEHv{==}|J#lWjr
zKF=HZjFWyGV;qL)JlQe#!9RG1pCDULP&BY(yrGu9d(e<IaEL5MGR<X?4(Qn6a(k9k
zDwOftXg@H57&zL94;_AVu`s$=BGYGjd3Zc{B~UTt=5o9Eg4=a=^GSKXz|Xr#_ZAoA
zP)?5H1u?(XDy?oVqe9N-?7_(3x5W_spPpM8Iga$=W_4jcT`b3ZMD)sKn-%(VUs~nu
z<cq~s<*#8nJdY9FF%oJBs}UTk2R9)wxow24n>XzIbn$F9@Am1*Q$o9d2s#efVqv&;
zspEg$_8)<W466&Xc))!jFB)=O3@pp5DGb0y{$uJ5Kvs{46+aUn+w7aq<_6|d1CcQ(
zLgHMGF~1-)%3xs99mfgMu|OH;GVn{S{ke}sljB~U**0bnD>iy7h6Awx7pU7S(zhZ^
zb0D{3+Edo~FgKW}p|aK#W9-O&ynv#-f8sy}-=<o0_SN?LOMAms@0;GNb&#8Km<2ls
z<RQZxoR_Hsxw+iB)Ot#EEJ$}9KIxt!%ZtR*!-ev^p>tN27_sT%U*rc*iRaA;vB4A^
zsE&Ua)=L`yd(Uqymi7)W_3j<^N_!b4trPAi-s#6fF|N9K3RNgZv=><|5|z}*W=oAg
zJR@9XhBO}jCXn2N!OXShwZ^IJK(IiLS)*v;so#flbib@lq^p_9bnWyR-|ro5AMPCq
zm)b_&4hK0rZw^k$18SUP)b<4igLG5H(TPa}#co~0PGgHwdp1pV_yCI}d_kw5-HhCc
zG&KiJmOdcUA9#5QQ$1YsLr)8)Z~lv?3X>kTM@_{FtIoYfKu~+NSj(zY7{VJh9PV(u
zsI)B@=Qh!)=6Dd!AQqT4!QK-M57J;J^5KceeZ@VQeYH%QD9YZMVZ;B`-YacX&Vk1V
zAs!4|OHIiBtV|Urq=peJZm$+Gev^1ZEH~b87S&|RY~tq4<6~czYFcbuxmivM&uTLL
zfwSrN`FqQX_lr#lrqAF1?vfu0eEu#fFt1iCP4`ts$9gKiJZfxRWvPwINP__coIp|6
zDaKHkap!^a6OC)4D$|V1`zA7@^20QwShDuCMQiURt>iD-Uqeh0QSd`}82N?GQjVpb
zG!M|{IC`5HI-|wXo(XS~fy0^?&RR)<Pu(Zk5uTDRn@2U`F;>N*&;4Pf;qJV=WcQAS
zO9T&te|h71i^By|l<8@*wzDCmr?+$~*L1~fjSQ&W7&Z;8ea1K|AX|x)K1QsW&YpDp
z87ZTgeWM>r*Czae^;&t>9tnfsjevD#)*eJtCTBV+0fTsD0@B%BZ6sY(W_!^Z_ClZ<
zN~YwP7xxq9xrx_zjj<KkS*&J89H&%kq(3m++Pk>O;aIo_?|-*4gZQQvMrGEpk%u!^
zXII8}x4}rK&EXkhMT`r5la1bao0f!VNwUWfX0m~zCL0a0%h_k`+0JfzbjHV7_r0(b
z#e30a7G!XU`nhu8KyCrrdzyg~*@(@U@F&yJG>wj8p)jd7<%kJ-^iK%){*-F*0r{$=
zX3rB0?)2zir5~SI^7p>nB8P;DABOLH-y7al@0=w9?<&^XHha8f;Z;Nz+d_pCsBHi{
z2M7YJQDLauktVCoA?h|k07)`Z<Tg1j<@(08iJQuS-Z7E(_Y~8K$G=dr%A+$&<<rJ4
zyUCQ>=#mec9cW&YX0cJEO~r_iG@XE&8sEM(>9MKB;aQM&E}ygS!xKp@@RU~G0N_D&
zf=z+ns{Y%hz3jUP9FB$_CemH~feY5oEY*L;fr-~JKh;iVEwsuW&v?{Gvkq;Iq$5mG
zM){1vbUTDH(>Zt%tU@kkp7_l=<w-w6qm-dc7mJU(Z+4c-d)r^P0=uO$)tS#Y;3TZ9
z>$)!`WI<IiVwz$feKjxCAU|e#EZbZt(8PdXf_9}yUYBZyW>~o70jD~#Z~LCVI#c_%
zrBN<m5g!t7u-2Zr`4@i<kVx~_vT5j5<}s@_=C~_e%Fe$%;6u_Uh!2phF;i)eaq|wD
zvOZM2CWbH<j7TQZi1gF%PCq{5`|(<tM41*-nf(S{u%40MhWUxR<hVP{Etyi4iak6l
z=#seg$*jhpaW|SNcFt<kctq|r|1lfg5_{dpXZSJ&wPU31*!5%oSxXueo_dn;V%~!_
z%)($*t9^z1aE6OhxC_s~h9Fb-TqDmQ$G^APlCPB)r28@RH97*gW6x)tGg0>A-mn;F
z-_WMQdM0*Ka^D@(xsGuFQk@j(?PgVZ+w|^`f%G%^BJ;UT%2Rb^KUbsNLt+SCsm6fl
z-5V~UM>KuyH-5$&Vhz+VdGzNE!`Ngf^EcAfZ4BwmayAGq&_3TfL%Ip9u@fLmZotUM
zCxgZU(vULEKrpc$ES!<j+Tq79d9CudeEoVasXiEx@Q^eIPpREiV^%U5Q^klk?x}$=
z`l0bOzO%2;4!olJDzd-_QwzEK>HL5@B^`m&&)wSo=3f@~l$HJP{XosH>6;&)8uJoc
zl$F2N@B-ysGbu5E_uv51z1?a<R;>Lx-T|0&Qg4#Tt`_}+&6)FgfgUX^HSvaI>6>#t
zj*4bgj;E7*BvvYDUAa{8!x!<a?8EtF5h1cJM*T*Urn{LrW|_-8r`QXI1oM|bT8*4u
zp%02vUHN1~WX+Az$zZZw$HAAu>lnR+;s(}lF@TS7Q>-sAeX&3EbprA)dMY$pVKoLz
zjB&fm!SHA|T%q<e!8u!hCisMVrQIZBAvxdG_YKS+g~m2y(tBij&qV3*jjbxMjdjJ>
z6E@mk#{S?LHYzE3GPRD$B?c!roFKcoeGjYls9afUM*W=?|6#*pTAxHsOr^((4RUZ<
zp36m8Tkn%YH#72y>UOr+Y(mN`^Gw82ZCLr<fqQTAXS|*B25wpp5Lqv!lCdPvAq{h@
zQ9-Hx?aK%hV%ofl>lcL0`Rsr^5B+rDRBlk}F3zR!Fj>`1y80pKFN+^&w?@N}_72b9
zY1px6g3Wn`E(N<&I@X(w^ZGd_Q*|)S+x=3JRge*M%-Z4Mrt0++{$ykzg2+SvoU(xC
zmmP*=X^+2e??$zmr0Li}%Zh5j{Xe(^(pi$V9r)BpWDRRQ_o55jVash7D~)#oWn$jI
zKfD?&$io0&resHABuoYjW@@AJVfkVDUSSHS&scXajkZ~RI<2Rv>q6fnC9#l#?k&aI
z9F+(eGXt;6#sqL!F}>YaH%+x3HxVDp><boz-M5NX&*HD<QpE$(jDWEf{q3U@;hV|=
zT6;r}Ia_NVaeq*JCpS_pUn}POUQFOJ2$a1#YfykMUA@)yD*xsGX6yZf<2cVd&zT06
zK@>Sb_Y6m^F%08<yJy${K~mGOlnKf!O*eW-P=YJ~LUB<%Zp;~xvTkEv1W4u8-d4rv
zK~FRY!4*lnDyrLDf*+)h=gJQO^5tB0cZmRl34M{z1g)#mWnCK*R(7?yTv?>@2P?I8
zxzE$EvbntjL0L+M#M^H_@AG`0@AG}0w}TDMc8ValenJJ@&C+TG#)~snW$OoThwyVS
zBFf!qhZEe5o+Q092_lt6&ML@TJFi%J4zqz|5`=yz<xjx4grFJvIvIxpyjlUZ!z8Y=
zdX#4VF-MRjPW-Jh?=_89r=FG<m7kf2fr)T>U-&}rdl3$A3%CmVlf5OY{|r~rg~9Vb
zU3@R`Ck7mn4mJSA_R=O&AzV0jwLEDR?`mEG;K}$(SwV)n=bskNBZ=#8+9v{Z^>+Jx
z$bOH>9<3`?22c+z`XsZub(=rb#INde=fGQyk~p9U<Jrh#KXJTfF->lj8~tc(g)<OV
zc4*TLr;iJFc;?ry?Y}Y!rS<V1koxa@x`%v&1Hi!rt>0x-20V*p@m(6DA^o5r8OjFS
zwF+Rr&OK*%&Rv>6+22K)I*O{xSEWrrM`4D|Em0D1ueQU!GdJ7z`{QbASq?rKD{}nK
ziXL6{hhDKl9(zw4p7$$S5g?;;=ZW;PyZLU40ziU+*jXLnv&S6ghZ^!@MXTW!=UB^0
zIQ8%9eEiJK8xM1!BRGni-mgCR`C{<xeAYT^5|tVzbJ$gFo;L!im9lW8Sn?|93QnxW
zY>`=vEv?oqw}_SQ2`~k#v-<O=G-RxOdZKrBr=2kK0jyv_!mMdM3O@mU5sCl=M+S6`
zFO>pyu&y<x1nn~9YefxSu@0$H$R9eS15Ub2*}<iecxET4N3#+7EP(n`e_=cq@MmPV
z&4ZWCgB6)VwZ}1d#hj|--Had@eoc2k0BtWzc?h-FMQ>Rdy85J5*w*E3AOOCE+6#ME
z%kzYpI%&}oJ;^W}3r5xXIy5W^@}Tt%&Upg>&}dLlR8T+ztID(4R_ie2)ie+jlN$2f
zXHq_V=IZ&=I^|y>+mqyrUN`N$*?v5ub#Q|f;_+=V{#`hrF2zh4*6AiLA|AL`%BCbl
z1SiJDulwkWo@nj68bXhLMt`M@iJSrq%y_CkyHn5K%yTb*4DD)H(U1`a2P>BAxr5u_
z%N77o5>h_B?`NKYy?zGB$C%Moh@+ONKgQ6vwZ_qFmon4w=$C(^4YL4Tw3$uQ2X>hq
zmx1o4^^Qpq1o1CXf|cWCf~j0h@`{?#p6-xW09v?Ca=g>^m`zXYP%CV`;2b8g(dC&J
zCz~~E#+zIQ;L;l%^xIPBya@l-+NiGS(KxFI?>h5hCqrVUq{Y)OPP!!^Zuhf!3njQE
zJS`~0_K#Rk;vOmB06p3C$AEEp&g5wV-wefy9lX*G;Omn2**6S=G7*^zdIBY-8_Rr)
z-Ji-GoU-zhoXVPUwblaxSBwKt-xA5E;|&?r6$O=bN#Ba*^(jJY(~aC@G75I;4|Dy?
zO}kAlc0m_ugC5LnT6-!a4Z7rdLFoY2AIL`6^Y2Aj)=jx2O9JAJ5`w+Mj&?XFu=UnV
zxqj-!^E2n<7^b+kPGsuC0GDsieyX^YAB(enU|YyqGn*F*%QCyDIHicZO{zx*$L#}*
zlP(4w2^uSELC+D7r26K&hnk#2FzE5=wX5~+cxwk`<N_5yT6d^?O>(Fp1-8k9q}J4$
z$F;rKsPmwyjnsGY&*q~svYP4wN-)kg?70B)!(!%R)>pZ=X~sQopYbB-c3}=laoP`l
z^H{Ik(Prm4jC6wnWbh!^yA+{do71xx&aO>%YPK*IjK%7Z3avXdZm(8|Vt19=0#)%o
zAzTUAZ00pX5N`BaeUC8@#9r>gzG1s9(AOb#R;!ZXy<kndlkQ|09*$ZLEQ>IQ&d_QO
zmcklrIKx}4yTsc$>AL_;YsUS{X>ThIqFRIlslDI1edA%9*MxPSC5@ovG`LIpTnMLp
zN+bIYB%J*g06xQT#stq-q>tk3jCl2m+tyi!ZQRq-P4CO|<x}TM$EWpGN{vZ^XB8y7
zjK@YZccFr}JL?S7LS`xAl+`_EO@onNEE)A~stQHYX2Brd3L|5>4nf^r_I<phl+K>f
z6jJkr?)vH0wb`5P@hF;z@;wyJ9{h*a*`R20EQ(k)$+CnT^HH@=w@eC+h~gtf>%5+1
zX%+f4F2WM-Er!<t;mT$!nf<R>Te<s0cp`*SOl}CLTAz6T-OF(F&zMl@JOhPhdb_Gr
zqz|J~$9RSfm&#;_8e<`wR)IO~&QMoTt&bejbCxkc#t-nC;V1;9Q{QCaH~1d!n_*U>
z&~zU@*8^UMoK@0c`B^G{v{8Q^;01D-G!H_Hlf{(mrzLrgv2zA%OaXr9yz%Rmq4iv`
zi`O+^s3UF=oe1mG=U91Xr<d*Ny9qy6=z-9qehtAXrSuW5e^zNRqQsMia#S02%YbI4
ztPA*vaf2KSXT35AU<V%$gdY&mUToHcKr1~&#uI?J&PXEv$N$@>sGQo8wB0eqhvzW#
zm(4MVp(({+CYMP1P|be7WA?mGS`;%1U=cQrdqhc)$Pa<8)X*8S6-IUhlHO|nC^Eq-
zuM2Cr$XKi)4JGX!0)1<exf(#lGN6O3FccMTuS>MUZwv1@a@Z`~w@5Gsse-n^fu~%B
zv*fC@cq?vqM_V!3OXvQd|Ld2*vSd92iUfld7sNoqc|zp0au0^nR3i8)&HlzU7$p9L
zRIX#1w(onurV(#c$Bxq_AQ5gbyzlCI7#cWNi0AQ3dD;>!N$X;(dclVs8j4>~rIv9?
zPt3c2<Ced~K`s<dmEBBjCOQ#-&jppN`76pE-O?^s0bJ2koMpRbnwV5__1Z7rY@ZpQ
zT;2*OoUr`wFh}(pa;{18^YjQE+@+eGf!NCO-!RX;z}id=`b}tAY`mzqs~0SL2*1@u
zG8|>f-8kc*O<N_E)*HWN+e!VpxeQXf>BUtjpEV0UR`!}`NpZG>b5v3`!8Qa~P=<@U
zMzf=M`Bgov#s50I45%HpS132EnKSmL_k-^qc*cBIa?t#vY8L>A=cW)L|BFFSi3eo0
zJ((1TgP<;$1)N~fx=!xAHe%~yMYG;|<XQ*?dLdEU`Pp}qv8_B@x^1<YgaUu;kGAe>
zUxAG1N^-0<Tp$+8w^T@hd};nx<zBZ{e{{Wa%z1$;6|U$qAEb9!xmQaDp+m$CAd>js
z_MPQ@;CRg-P^qW3ZdoeGmSFc;D_CR_+(g1aw4=#<!&6<jy{hXmLw3_O=-c7%njDYo
zv*Y|+`kP4WmX&sZY>qx+0s8mwU*rPXjVK(J4zNZbGCL$(53CkUc$RAWAO!wktEn@J
z94c1H&JL;~+m^R~|I4?cfXcPiXR^S)to<mIY{jgZpr$PDpQE`?W)k6nOoi*}DCICJ
z1ucUd)^N66eUgEW<=RXu-nqdD&zWdx4quUp<0oEY4gOH}m^KkJSYox_QCP$Sy^uS#
zw7$w}>49Uk9n(X6cW{2+P6inD2gnXjwb;Y<!%2-QXpDco|JC2Gb!WIKRl#!i(a;{?
zlJUZ@f$S!ARl%U&vEwXC`?>0eEufu4lEL9+$A+j#N6(OsG@?ncQ4*2B@IxLZ;i+EG
zOK*GZB7T=&5c;lw0K6C~P?ZTlm52hMcZ#jp7#`bGh)KX0j%7g4NfmIdBtR7XLc|J^
z<@^7`e;AMoW_;I-IZNEq%-$-i#%j}$!KDMBV1)R%uO+2S?~1*!m}TIewLsn!wR8v~
z;}Vv>?snh9bysk5F?h|hzvJOY*U60UTmF;c=m4o#++Ts>;r&Xih$d8afS*fB*)pmC
z>ZYPXc0~7H0Wv$&T1~FedIt$VGfu{B_w@ao)t@Jk={I|KA#^r4Q>3p_GLyS|r07Ii
z+sj=U!Asn72AZ^9UmRLQa<HyECw5{BiI5kZM>4^?r*P1*t@@Ya_J^cW2>DuXd+W5;
z5@r3tbq9YtbVZ+(^j6givf_yLAV@Q!YrL+il%7B;)pxX24t;ET)Ail51zACaXg@vC
z6Se!etGUPP|H)f<3Qzno!TAlyR08{5VuZwJf(GlRhp>a)+A-&qIEC=Q8*R13*(gtW
z69}@LuzRvqA3w9av$M4{6`kPWVmgU0R{NQ5fYc1Fj>B^v)tq~x36;~ZQJdCLkeR@f
zL#2wkiFIG`m1~t+f~T*P%RJfnaN1Mx4Op;R4-%`MpB(*}2{Z3znc*IQ<|)wdiwd>b
zo0g@;V&SY!D$N)}wftd=!?5Ozu2z`CCw1Ev8~i05)n@*rjt@MuT)Sz1Z;RW3;GFD5
zM*o`jVe>7^w8U-xm+UDr0KQl!gTDnhIICKUVnZ92F}yBNs)Y}BUFFtJuayk^6mzKY
zG0V6Ai=V*<g3uM7b;Hbl#5I#$z?=OLpt$aJoDnE@;syXM^E$(6Obs@t^pPd>HpBAg
z+%ahU$!#ilJ@qru^6td$&Kx%#ny=X}AreAwQM~LAUbcEeG#~n;a8Tql{DZi)gG(18
z7R$x`u9<`3o(goh2CRHWe@X1N7LHq#OLulif0Fi1?~i}LjBqk6U}PTepBHAGd?{<?
zd$9pC05u5)z9~CvwPBV>+OAVDq3sD%BL*!@M=rB0zA!#JQ6HappS0gTL3Hcq7nC~h
zvlwT6YY_J;Wtg&Y(gGutj0g?<03oZGwW$M8G$<}&-qx^B)gSvVZMs*|2Xi4!Z_=J5
zSw8{n*IFX<mXlRrd9uG-QcjpNl_?HPoL7eYh@ui#@epDwORabndDpu6B!2uIVr*0w
zMM@sM+|BmvGPNQ)NJ04Y%WT+dIqenh`&Nni3+JY(%k)eUwZcZG6moGk<N$m#DhF$H
zEr$ZjJZ$!Zf5AN<1ODj)-t$CT6#<ZT$c{N=$AVA6RdRH|=|qJJIR;EG73~IgF(s}+
zR*bLBvc=qvAW$Z*R$)u~!TAcQ0mc4Jca7J_rJ{XYNSFjb2RhOMrg16ZS-3>Of6{Wx
zS__BO>l#r*?OU!jpkfN>j9Oil&U{!3_pl-@a#wg4ge0myL#`0{7%rkE?|1%Vw(voK
z#;gGR;_X;{aUAHNONeOz!E|R8XU84$5L|D-j51nhh&_X<dZHDwUEc7Tj#NZqcD{SH
z-YxiitM~IF-Xq>37Be%0tgHm3&(9{~Yd~cLHBz!DDkK76JkKT-g0&{dy~TDyXEC8w
zN*E&Jv1V_^F>Ex>^rOeWb|=U#D8&I2VOuf#X|qqRg_0?Mcw1s-yd0~*<K#e{Ga6!D
zJj1A3)hrhl^cmO$E8krox52e^+ba70#(NeU@lY1yzN7BZ+pk$Ej);fCdr?GX(HZfU
zfC3PzF{&0D)W-Y$vhY6ehpiT$<{*}=r_p;LMj$kSO1}8Mv9AybR(bi4B63_cbJ+qI
zVNzTyUlQpmxP&>u;vYi$B=G>AQDpqxDCoPlFelLNGH75&D$j4(b7<aLYtC6+*i$2N
zuKCWCK}`Tc@L>A$R?LB}p?J-)xSfbbc?rl8k28cik%h$93_=n{%CY+BmyW!gN9ly)
zy2Kj$HbC9rf{K~X9K><Su}Ts!BwdqLOgWCt&bqE%$U$rtS1Gg;?-70Ng*s#+KBC4R
zE`iy476$;-;9d~Yc;uycP9Y7qH4WpK04Ph<Bq`&)(-kPvmLe%I37L0P5Fma)Hgi%7
zWMz?nQ3m?ne`B3ccT%nLx*Kx67uREC$ilMwXP;G~6O|W#H_qBmbQD2gy)p{%h$0`_
ztb3B^Iu01<+{@?5>0|0b9sJK_ylTra36LbTEb@x3ahPSBcs=-3Nx6COHJ@A67hlk>
zl)=F*>KHhfm(H`aajVe8==LR1zyI0)^H#Ja-k358YKSS*?&ZMCiD&K-yUErk@g-a}
z6B!ocy?EPOjEw=EwJ7aIWmu#j+PNXLAq0KUj{avE7G40htTD|40|vGF?oboM<nAe8
zHo!$vMfNL`ISWpP;YOBFBvilcH{tS+DVA9VwqhTyyGoIoHL#(*4?cXGOJC#xcjb-m
z;!htTw$53%{VD#s5$@-Noqs(2tEEPqX|t%u<Ve$w&sivUE?2#k$}wf$x1bA1?*NEL
z%2bF&ySn$6v${UhiP}BZ&PCgj?BF6~bsX!}${^@(J3U=cs>f%}osVW<8JZ;Fz34Zn
z^%8Sc7n!a<`ihSOhtN61Z#2}$%aT1J2BX4F!)Op}foU&#fAGz$6^*ebqSwKDCT>>B
zmX8V;n`7(wV&kQ=f^E-a7Gu>S_SmBiM?_~9taD+MNyxh*DES*nrLSJ?lYtViQ~qh0
z9k_3PdJeh<jS9bT%W~M+bHGd{!V_VV3o-aWiV(Vb*gBj$rgG5UT%Cw_uy7w&ukO2A
zOcX<o|A-b6E`7l?3h{=?DiN=l0=xFz0%5G(L(~<5;B2ffc?)O=NbU%!p03kgn5T0Y
z6?|th`7Q$s2+<^VqI9JOg06A&vJj3~hExQ2>#SA0uBg={sTt7P7+qY;S<VJU2?<~%
z^BA;Cz#V650_BumabS=C>_nD5wF_J30-K2<mq13m6)BZCub9&bZy+g6;Q<`d3-M8J
zG*)Xlm=9_<+K7T66GRklXKyBxH<KR(GN?0NBzQndIw*}7yACTS-qU34tUz$0Fd2XE
zYb8yrT3V9CwUK@}o#GEcXzV#~hirk=7Euw_j5zmK|CUTx@ZUj!;EGKZ*&?r<-z=3Q
zmm$U`33H6S00HIO9(u3JfHA;>m%r^&z3&c!ovpS#)47qiUxHb>Zc@Wo+H0Xx8o`I<
z$o}AFhWB*KAPFawrDtC}M4Bw}<{k3m;yvwu#6eCEC(p#85JO4!J+7pScF$k@t1PUm
ztB{cZyNaxpJtY^*5ol9M9e$Y)3O6G<%h!R`?DT+MS3`>&o&f_V;MMUG5qtqfFltox
z#A|)yuhH3#8SwuUbp@5M`xbr{FU5bbSd5kUKp++?kiTM-lO>U%w24PEyg@*%>nfLq
zD9WD+JxDl-pFIC_&joh_^Z+8M0~JcKI#)4|Rk9;+NjZiGiu7etBfm(foU01%A-1gY
zOD$}X+;-k?u?&Lw%NqU2QI{m3EK-@m%y@lfdFO)p9K{BVVz+YzqI#*dE_Lfd*mP7G
z11_y;IMx~T;;`nSh`jRA2Lb*&phP&(MTMy%LD;v-2EL~xHI2sk(3<%mxVl6Ax;}Ac
zoB}o}`p_?=RP`#leUW&b#XkhuLzPFQ_*gO?H&U6JH9OSChjU?0diE(4S{F20B0%JZ
zb<bxfoq4TqM|`>-P0X$Z5dkN7FM(8u7jAd1R2K~(25#`KYLY})t?(SiJRPED45U#f
z12`qpAwW2!3%9ZPZBFQ*)?)MS)zzzMwN$o0C2GF*oY9}J!&Da)J5MTs9!;oIs*bPZ
zLhJd;!RJlo;(U^8vqP{u^nGPxe5~CjSNKj94_zh2wT4-^D>nFY`PDMQUkKgRYX|BR
zJrK(Yvs?&U7c6+_8sPUMU$V<1dg698Uw+laF`qhKKb5Mt_6c|D?{TasiG%GI7uT(0
z&Rxf(u7MTt`M+`9FNH$QpCZo+r7j~y><J#Lr}x8u{|n?A&j_mmLuM8>cn_BOdH!ca
z%*g58SAB5@Cbpi6cA4K}FVSuOdW&lk07MAHw6}1(Y4Kyq)T4tPwzxZLf1@vo#!MM<
z>J2D7@Yi8!Fde)J@jL{Y%e#mSI&8W#)CzFaFv{ydXO4w|!wI+bC7l+z!|CfKIiQ3T
zlnkQW`8Tg;$f=<5ZejS`9$$+Cp~&(kQvnU}Ds6nPwM=Y#BL=nkLn9sqB1KU=qY(IY
zlhLW(sE@iHPO$U6Mv(jf><mG_d|Pr3g!W^`U_(~QzL%q~y2qn%2HK?7y$~R}MLWOH
z%8K#;<@~1gLtv)pmgR%Y$_neVdNn~=3yuwNg&>AM`0MORXh@-p`xIft+%>a6PAUc|
zx0lI?vA`<5Lw>}yx!*xGEXru^K=z8?)pwZto0(|&aHri-`q$#(qxSo#cF8`?HZSBN
zT<aRlg&svsx@JnEB$1iT#s@SI&f#K+2vkQ`D&))%aq%`v?hw#7Xt<mPM7yPjZj56R
zL9)dLe)NC*>79Tok^~X#yimc!+33&EY9*Nm&YSdvewK!)xDz>;i%1f2Em>V7j^R<*
z<H)6wwR1JT(KkN3lYBp4KNsV?m*dSU(39XyCUu9QYjS)Ep=FwplzV<!_ky+V1Ohi!
zAU9i36*N9Ld+Nu8#I$oula#+;VE<RagX4LU@|k3dK>lH$^s`~ib{_yQ*b+Z(KB6p|
z!?O7l<l(<L#P4_1-5BF|J<eQE7t{i|(*UQ3%!&O%QLCfqd}Irgoa`hMj2C{6nq<#K
z?}AEjB)|^Ge@6>RCdC^AcL<c23^5L&>2ZJ*wZY`;>W+%<I=6+DAmYPSm5v`Mb+=)B
z5DyE?$1;{~pZ@uiyAcx8ci3TB@Ib{hi>7d>DaaRG%F%20u+L0!p`*>Z?hhfbajZe7
zOFNKMwAF<w2+&4i_fdX!ymk)5=;`;Eth|)<by;)c4Le8H<PDKI^IFd1ct~UluB3SI
zsk}K#(Z?L$A6`Ws=xbH}pgHf(h&7+~)a1=NOJKkt@O1paH(z2Bvw(npMpUBMA#cuQ
zscFcPQ^ODh!UI~%h_u;jw2Ny9E~@MZ8p9PdPXx(KG)cBUE)|#ddpi{GNw?x<$al?H
zuHvRo|A$h0glb%v+iXsTZUkPEA_k>r)=a5`EMnCe9?|_i8c{a66wQRFVW?KSH%>p@
zj=HzVO;M)B-aq}nKFa5XQ;F3E1QimagR7YH7S=3nS6x66Fu-g_gxqpSUndD^#LEzp
zt5mprMmsZ57_$!Cb9JLm5xR2&*0yf{h!}&5!J6i)R6dyAUd$e~hUQ>;j|tEN?uksH
zF8=H|qN#j0vXWp7)2Cb~6ac>DkYgWG@5r7bRxTV6T_a<~CaE{r@Hh6uB${74l<lXa
zDkVOuFQVoKOiBHmbkOPr_@xPUnqk9Yk_V*W9x@%HE;`h^)*YHn_QF;(Bz?WnlOQ(R
zv2USlNtVeKkXW|X{j<8niii0<*fJ=-g+{||NPog5**WUlSu$<wm|C@pzE3jf;PVbO
z8|ST4AGA+@3-deELC~^O2cj&^Kb@^fhY@b$GiDBDj>-<+qu3Q>d%08#7Y&syyA6b5
zP>S>?P=4_!b7I!F2<mf|ra*DT^`0e=@>>5Sxi<cAefFl@!o*C*9=b0+t|G)(T&0hY
z3IVuYL<k{^KZ@(&Ks3+KG|>f?RVrHGrl4o3M+&1zOr;SZhm=a{q=6K?xAm8AN4H;`
zK3AVPe*TmjTq9JXFs@5%O%h_x17}G3Z?Jf)hP~(e?n>#7et@mqp~}IogU@SVBdrGQ
z(?dK~!a!{aJi!CoqlkxerL|t^_sR2*Iotfy;pyf?IIoYRPAIph;jDMa;}^~M5>gu!
z7*&eYB=LuHZpyq3ZR?}uXWcI~0bHkEMCSO3TulmM^?V`+*k6J1fwzB$C*lT6UHYm!
z6QMi?Cwx$!{i_=@5#JD(^}dIJ7We<~s8AVqi1axU2hv~CQjP*S&Ow6~d6#G4yC$3{
zmq@=6-z7PW-?n3iR<3QXPKRS8wdLnG-8%M4&8<U*hK&5pJTFJ8@@?-G5Bh9CjkV}^
z;b;zTqm1MUFz!<?28ykXcstR4-yUQ`RWwQKN*qv86dw*m->dGcWdbTM;ds!vhUji)
zf`^b^uGEF!_y0$1tcWBg%_+&0=Qt4qa~RLG^|?xE3JD|tj^7Xfka@T(I}w`yLgkIc
zO^-R3bZoZnYm35+kAsHdd@j6SW~bG8B%Ie~zXgnh>AYaRl}CpMK6oQGii--RZY!3o
z=rCLZ1x;6M4Q%xyri1t4srY_Qz%c%X1CBq1ozyEMhdEuFu$V9uVG7E4Fu~8Kes@Pi
z_y|vUI9Qb=Ikxzz2~mfyQY0pbK><t&NyST|lR%0rd1-xsQ2S}~29=f=;BdA@Kf}5M
zTQ{gI!)b<uvU8K?deIZ!7|+u>b8?j#qTEex%TPfn2(GK)_1y5~^b9N*SSW;|R#AqU
zP+FEJFtAC)hC$L&lBcvo>>26q0G}0$Ps7iVp^Kd4@BCjFi&ab}da%I>5qm<8niUdg
z3bP_J{3(8>Lme#4e)0-DggYZc@w(+KnuY>$&%0q{b=M#6MYuNp9#igN)|RuykCAS!
z0?^|P`tWXRsdQrG_+u%bl)~@;3znUh97<@~A$3>1Z9#?)U(sjL)d<WkO}DO{USmQ%
zk~l&_?M?4r=H4NS#ZnE(?V6-}yOgttWlUMjnU7~BlF2b3lu<>ae!^NL=S#?@3GmR(
zQrUTnMRY%>!^o%`S1DoaOir{rTYdd}l#;SMr6>nSTV01M{_tJ2-eq6Eg>wy&r11(#
zQw2e<nnW7<BtdS(ye(hq_xq%V7w~}cluv_y+kK>xR5ovVU#l31J|rFl;$jQ9BV;p=
zlDg(gXsXzDR*(5osbvi75}}o5xC=Q6XD|VZ?!?|T<N>nm)141u46sAaM>r6^lRk}Y
z`$EnZ6^y!~oh;4eD6Tck8LU*wS1e=^I7!Fz2nOdpfm?&d)}^Knq*7~zr?0m|S!p*z
zt?)Q^nKh0+nENO&38`kmTTD@uecptBOF5u4v8JD$O%vGOwqNtEoAzjSXw%Ogb}|FB
zFGjscZra^3YyCcP`o>GtG~S3Wd+qDozXk^=ZC&Q3e}&}QG14x>kg6dxP?mtmgJUnF
zF@n!+Xk?)j2^J#Dgwv*|<O=o5B4jSY(*5YmZ{@jM4mUo@?tYqIXH8X{vsi8*j5f#@
z%iwwdh+*!bwmmAWt+f%RJYN=#;-E3nf_8<tNCL{+o%V1{jS=c~*-t;Y4%l*bL9>Gp
zJ$f%}hPrlqnstjk2u#PA9T+QbbiHx}qVO(8v8RQnJ))x{5^5B2k=Z(ww}5;P`oC}s
z1PSi7h)mhD5_4JTCb(cqarkiQlWWOU91D`fq5xk|_{A#WbJJcYfa0F+=>2M3bO@uE
zSqs{y<(TZ)<hd+cBpS;|>{`gru2?WEd=Ipc7F)*;s2Wdd-w6apE{Jl9P9rb~;@Tq?
z=?5pU47Nvy7eQ6FpYCaQPmV`vR@8pb_@6{_mB};AVGf9pn^KR_%3vO(Qxs(#zlLH;
zh{?c)4ga1LI7%qKVUHd6j?$94uyKvCX&p4`XLNj{XJ_kTUr_%Lus+)X{a)n46T8U1
z;?&$S3P`s+Uk(fO2D=dgF1pNxMw9agk5r`W-;3H1`uK|E0EhGoVc|F##&}^y+HmVp
z4^`KT-mgA~%GJ%{C+q_Lg6gF8mOynAV`f}L&E}xu5wRV)fqSmXrJ}3W5b7qdp>`l6
zjmKP#(}dF-x6h2@TKc&f%pxaw+in>{j^5IR`<5mGm79Xtb=lbOiolemsa4DaILAFf
z9KI)!j!KfRl!toMXUiz;OX2gUO(WiCf4e8>&j$l{O~@=#<s6Q}{3XC+MIlhjk`t*+
zZ;|avdOgwZ3rQrH<pO5xe59=*6Y1WXc3RUBb+qI8aHd7!cjjiiwRAVmE^pXb+Kq`l
zgt(E9G{8zBswBi^aC5b^M+A0L{$l=7wT9p*%+V%y+gZ3Y=`?zoMWbh%UQ?xqq@Iz`
z(QkkF@3SXU7!JJ6P(%W9*>9Oaj$Q7O5k94T$qqnQqB09H5P79pK><_K=O(P~TE073
zZO^`&q5geGJ`_{8yGRwU*ySP{;)Tne!Fn~MpusmM&n~!f@YKF@_whWN{yod5;D}3W
zrF@0!5)wSlzBpFS|B1ha+7#zPa$LB~KPLercU3^yi@W0|72G~)axd+DI8NfnQucyl
z)8lSDNllnatvhi0obT2Pku@_c(I#nsuCMTFUr)cibQ#)h8IxF}p-dsnw5Vv5NZ=lm
z)heh~D8tlOa2b)-YfjOy;6K3_hrsXKaIx}WF8e9%k<i;8U4On8C9B}R2El@eCvd5>
zW&R>0g#01}N`Mp@JAOSTcRT7WlR0plEvKcj8jb82B77D(-iL-zq%b>tFp+D4>?MR-
zj&6|Lk*rPA$SyD!G1(_OOWLIrzhf9<YRbnP5du;d6ASQ$QK-2IM7)UGF#uWX$A3;m
zi9$?3K}je<z}-eJ%Sv$#fhqnM>_dE^c}E2|(Jj9e`*ce93+p-b7>AWdqKn1?P9dMC
z!61pjr{g%{?<pE_s4*?S0wa6DU!bmemZg=D8a4OA`x>P#gsg!d#$scs_vux{U}R8V
zC+R<?ek=r{iYB(*Lm@s`L~oX)x=ic9BI3V$?m!R?WI@sd;9|wBwHlS0HKl$^qD>Cr
zQ^#c>;)V2}jmmK07QKAMt^w>8)%#532K9%aNSAA5Q!_is8w40$$3;d2L6MkG>N4sW
zVIB4)d<_v3NYy#=QU=YE-mq+rE1=D{pX76^6$fsGPvX@;)EqiDS#?=1QI2ZD`~Tuo
zKtfDYlyQ$rt%EYN(Qn~-x#o4B`J2?pZKXw+_KC#+TB9}Hv2d24!8;1UEfuecy>PlY
z`Qqe@D6YqEL=!Vn``tWdj1C?xB_$B>5?RSmLzP=iOw>JTh|_k@Q_O=oP62aTU9ymc
z;CSd(oU^W2vgdl3w0_gQU)JZRbt9-x|Ngb<Ws)<p&50nu8XtW5Uu638JcaZNiC!4^
znV&??3P$EFWNIiYn3n2o!GEJfE5KVWwy!%dVB(CRp4hGvA@i0ZxHZC3pH0&NdPl&}
zQiHU?+omhBS_SQcg{50(7zjrNDUvcMKsj|708e31cp-7a0R%}k0>v=<4x|Qs@&)4T
zPK5DUzCV8ZW%}y4-3$zrIt+z(ZkoAD3YD?#j0@Ar86-A{(-8F8XeBf?k7hl*4L@ff
z{I=Unc`}AXP#KwhcOv+F-;#;rkTpAWnU$N);fi%gW7`^Q0Rc~9vF9?fWI0-ZdXg@J
zDJ{*1NCO;Rs1SzUuM*Y`&cxFgNqZ(ek!=v?Q-Arh&zKC)u+N&gDF6{n;HS-zcn+We
zz)u+nH<3e$G-*jFpQ%oKK`s6eG%1dXu$43PiXNMHk9X67kwl{VYrj8k{x$BIgI{<F
z0<kJ7$>43hY91q0inz-=OImL<dIjUNa6CyCG)?}FB;c67>)ch~Qf&;u9ik|PTH`$O
zch^`3`{(`fPr8Y(C-LhdZZ5!Ieirxl2wATs8eGEm6kKMFshv{E<_ElEFYiKXTFB$A
z(HMe;mTB1cW*Fe7&;UtF0Lg~X`A5*Nb?IV6*YeWh5b{Qx@I8*2GN;)`mM(cRR?D`d
z1`|ucp|BS#Ird!_Klagnz`AfStb|j{S81GPc6<C`oGfMF-~Q@jdAb%d7I$A?k|;<+
z-0-UTct~r?<DnUF=u6ftgNdaibzLTZu$VbOhZAD4{ER{A;`g<u^;@ns8c{OYy3s>M
zdy$K~peIBaRQxVc(Xvqk4_~2TGrS4L6vbt)FG!vUBAj=M?pQdq1fyKmDmasM(~$;e
z`NgMQ)}E2z&HIP-hOG2{^3Q*6lA;8Bx0!vEtc2ZG&PFbnsyserNoz3jo$=EWN5Q0c
z@_stBX!rK)3l2E5p^CeD6?efAI_eJ1y9bz{qIYgU*tgHT%S{nc2NWx{VBwS5O{>bH
zzU~uz)Zn%ru#Ow7$*pxSGy((^xN-^*>+HPkP)<2wJ;5PvvhO}Yh{Uk{^h52ar%krP
zW<Hqx+XWRvJwGNkZslP2FcOM7*oqQcNfI~7++v!BjN2*Djpc)u4Etq&Ew>^EUY|QD
zHS_w6uJ?^kJlyVkuVeO+%oci<KDHUrwCIox!XCZsZvr))@QSMfO7r#UazNpPdocPb
z6evjoEG?+fx#v^4R*rNcxGtYLr5h-w`k!Vna}p#(&B@MR-0qo-#)wxjjyx7}FgEXT
zTV#P^;ItwdQEEmW$pn#vav(;|lrbT8?xo7646O*mO~85x+2o!KPYJIxUOc@cxfX-F
zP`x6_l7?)MEq!eRTh;=xwMoVfJZc2Y??M!V4oh}gFUC}66><fjBj>>z4B6@{-~pb|
zI(78g)3eL0TO@4ugWn5#(YWBg!PEU_E*(^{0WMK}b5^?DCd|RpqBleh&zt1@ETX^E
zh!EH!8Dvs3YBO$<P$SMqRXQ=Ck)=D%7gXZdqaRy7{6@cK64n(!5j7lwd*&^ul>s&w
zZ!@&+(1zoq)&ge1I!ph{yuM0_O3oxFU^T&Sr`7D6zk4aqumNC60QyIfBa+7{rxr{(
zXvwABgC;%P5BM8bB9>8v0QW{f8uX}cYKYA><>CbK3;FJI;E{HB(w=y;Z%OSYl9maO
zf|_!)A}jU#sTEUQK+Sm$sDWj>K?W{X_-RTEi-tAYh2x$Q&JVMrBW{lvPx3w8a@!9P
zLF!T~tJ$6VU)j19O<^52Ovgc(V>y+G$!>!HbAiF!JeUYKX+OR1Gi?$8nAr>12iMD7
ztV*XRbPzFafN9;7b|NYbAGRUm+I{bj2M_Z0(j3EW5O$V3-1A)ZN^4BTlj;bwOjy&r
z23;$WIS>Rk@?zMuj#6S<9~o^pN3FpMR;?WADGx1!Vk;8B8?;EA!8yF?{olVOVo&I#
zeC-}gShg^w`^~<FSsDWgraPXxdQkQ|0+j4z(fSS(o2U!42o2jBA?{F<ZK20!SfUx5
z9>sVLfFN8YF~=%)(b)_hJ){&^hMgRe5ee*f%?N^^_j5wyv1T<&f=^*PcZ|$^i&Dun
zra}g9l=1QMX&b_$C+S5Uo@CzWle%_>;`|&*IJQ6vle=e`_Tyty7KV~HL7AoT+3WZ}
zDG&#!UXVeQuj5EaqMg={@v4K6j40njMxNFg@-=z$26&3FMBcL$zTeSwnN~;Vb&JtW
z2w$Z58qMh1sU}+;EyRr=1GQ8HUKX{`&n_4E4bNkRx0~Us`l}jnj@YXx@+iUm?FToU
zOZh0U$h7A6nXoO>Dxp^;NwA2N^p4@O2_K}2oUi5V>v8XgvH4+3TGc%`M^_WFT}sr`
zA<q^?57lRHW^TMG2Xc|tIJ14-8d#Lx-n&k03}PO@*e2wM%u<_fx|2;Y5S|W8D<V=w
zFYOnhbgaw%6Pp63j_7yFd=e@8khCGt{|+v-#~+j!Pd|{QbDw0<8X)_+%s8(ghcm&s
z^MGVv;1_xeVB;A7v0>kB&3mi|{n=>Tl>DO^KBH>~G9M%=Kq$6sMz7guHZW=79c6Ti
zW{iMCR38XK+@8h(_Yz@x^WC7<F`y@B5^!FGzB^nwoFlwQ5WTHi{KlkF(8r~8<7fg(
zw$kF*Q@?wlKmS}HPW~2v<TIl0+c4FxPE{vjAkx0fhR=GGf$-XJws&J0lLoBv6KWWv
zYRf_%?Yo{sVJ9qG2V9CIJvYvD-svksK5u;li#FRScccXr%4B$pxOd2LWqgTu3{1m`
zfEoE|d53K$hNB*U2^rnuGz`9NZBwb>Y59$XPp++A6Xb(SnWWa*9=Bh+pFO#e-$+Sn
z?1Q2d2lNp$U);6gIg9pjVtp^P?qrK)kkq9VHLpM{{bF@7ht3OPWL-PFW6ZJz>vA@n
zJYKVBexv>H<Z`lAyw^vm2e-e71ckz~J$P4v;{?$f<qtwE=uop3q3$(mFi_$aiv%CC
z2PIP<KBjyB71WK}WTfE)na??Z_(NbI7J~G|1~lCt`9mB!B|IE@kWPEBAFbqUq$iIf
ze*hbH5iJ<}AQ+eyGM3VB*QzxANMD#f?As+{U|!QLskO>5`m;lcq7!_-FDT3|BVvEk
zTc*{D%LZ=ith%LfgbBYPxaF{7>{t!Yvtn|5yI@<M^oy9-3UTtALY*+~OEW52#J${l
z{W~8cSuW&RYa!ib8=_Bi%kL04$s4+Asj-JPy<;8Kkg0moILP(TLgLam+*A^<%Zvet
zjH{E^*@VfPQQ=LX7hxTDPdB{p?CIE0Wq7r>WSuy{^Jp`IlhkGj(AEmQEEp0Rlgc2?
zOqDX;ue81IdK$IUx-`37!)<p<7w-@5^_*-36x<M%5F%-eeAzU2)t2ez7_B1AlblVI
z&g7PMCu=VX?aaCtV<8*tnlWUssZmfe7!LI<=__piRv-6RSIFQV*wr%Q?Vy~Dp<HX;
z!f^Kc>xEShnJs6*yz)Sl1S%x>9`i&M&co4oniAHG+jFm~l7vP8l&toP-~RcNQf|r0
z6c`o>Xv%Gv_i`MVr;sO<p7$Sr-rq;V;_APJR5OWJ%y+mt;U+iuu9?0!dY?KZfkE6<
z2~^x{O*g;PEJ-Iovvhh7!$_nPfXf<CA1{4fx)$!J%T{TR?1ki6x+l*|Dd@#IoTC(w
z<QrrZ@b2(FaDCLNwn!KTjkGR6Mer-`dAfgT#sB5<2REqgQ9P337-N!?uiV9zpH!m8
zEnwJUGN7AX<fD&IJMxXN2Tz)Qf2(9*-Wh2PSXL&_Lx0G+1Cs;Y0sAGN5zS(GKbt+z
zf1dhxbf(wGXP_yP8__rV#Gx_V1R1Q47XiA*Q~Hv;6ZcuS{?)Q9lDZ{YvHhodmBwcF
z8vEDGqgtgC(PYmIz`_xp>O@mYoK!9gUtpRUjm`2M1@Kr8zWD1jbA2Pf5R0<o(?A)1
zPU-f@6l-)If8NP|@<eObaJZ;R1ELf#7fIvtdd{=a2cx{R_*6>$mwx?rlLp#Td<(Zw
z7czG1M)Y3iE@0;}q~?mn!CZ6TsC>tQAkw!(s>H{s5;G`@1@6xuN}uTjlONFNK*y~z
z46U%q)v3pn&v=MK&9tN_4;3*oVJjVRw*O3so_pT$j=4WShO-`nNiivxG4|v$;NU~*
zSY_AwMC=P0{?kW0Jya_8aLC3<^6;b96E~%XSFw+P0e2C3%%{JYO(mn}m<)pLO@9kn
zPriF=#pGtd&g-%D#D}dGN-JCSTU0<b8LHSGb=Gri{P~$rTDWH@m_Ns~I>;eN8N9=&
zqxBWP04z!EwN8ooMRuZo=4kp**dHZKd8pch=l=XL%#T~;DV7LUyXBj6IZO`VV?r$v
zOJbfQbBUx6ze+{oc1OhMUhxIkI025gpz6nDmPMI?F<aMWqo|D(!kxkntXmzR5h9V+
zn)acGbk0DlU`Q8JgBcG9&tyQMU@sNZB!<fp;oqLZn<0Q{-6lf}R4KG)*V^!ybT8}>
z(-0yy57eV?=VM;OS$PK{xF!@&X<G)iF{e38vTc-#vshNLblGMsZy<#-t9(=1BTRnI
zQ7Mpmr4}#2jb4Q;&;ftq^fGnsn<wKb(MSPL^)iiiYn2sC><Y+<zW^oQW<Dp%IT)HK
zh=K`oC!gkWYdj`hW8PtWGcOoHFd6@=W!kyZ_W4%ZewZ4Q$mi{z|K%Xp?MnZ=m8YYj
zViu&M;gBlK<+@~+%k%$m=X-BTbf{2kf;E*M?%b%_gX>7=A)*OAd4*UxLwiSvJb{U5
zG1{$@bA3o}Nm7>Xw&dJ8=r6q^R*}~QM<<GA-RM0<UkGnuniK(AkC{MBAs{F-&xm|$
zJ$FczI7j$lW{#B8834s!ZZRZ+F(`d!$l!R4ul?H3MHAe9DTIN*qFobQ#JK<vWzv3K
zqA`_|*^ZU+H0=+eUl5vKs8mx7=FzgCy%V8_3ODG*7Y1=;*?$_t`7$r%zU{qbgA+cY
zKSCfpI&j5HOQXExC&Dg4%=?g#C>9Tol(sEj`U$KSD1yim+NZC}Psd<@!MMHTsXrtx
z3u?UtlPBZPXhi3)$J%xNaSN0GWNO~Gq)46!f*|=|=liQm+tL9;wYqx9vBYffvM{>z
z;ZbSfl1+XDsEJ{*Qg)^(y+a-e@d|lVDf#%9w8N>XOHhGKIFqtgJwzW>bMFS(6_Qi}
zWUSY%A|*zcfJ4%vAOfF>HGxey2UJYsHJX<qro1O#`|q>Q1u;Xv<1LeoXRru4BFKN;
zBv$B2$4m!|l#FXnQ*x9{+!j+HXuxM&Km!jVn$i?ViB6nEDMnE+GR||!C8#J)cF3W2
zIWAH^uTFNLdMHBzoXEe2*F=RpVZEwn$_%rh;amDcqtE3hWHiAFvg#tmb{x0kG@LRq
zLq|v1qEiS-nm1<u89t|eW;xo5WF}qmcSBv0=N6UB0;D6YZ_9l2o|WsH@@1gW<74}$
z*r1rs*LQ3M0|Eyo1!9LHF4`t)6D?tO>+EU3IEELmUOP@AI@6&uyI}v8ZKauG`tcHL
zDqzZhWT%O!PG(Gsu5RD<pD_svAWP)zn%aoN?P{CE-zQqW7QxZPCa9E&8N~2!5*S7O
zL6}2%EtK}3e~em<<bX;pXL(^a)r!JbLb6KRPpU`&zH|_1(>aSuhZ<Z9z5~l9bfc%h
zRqNWfU85dF`TPWx1OU|1)cCu*o$Ml@P%XC>*PQAo+7|>Vn;P&94uNPFjsdj+M*+4H
z8$z(okyxZ!BSVka`ce}M#pZyg*Q}y2efWDO7=fj$|CnhKtUyRkflqNz!ALJ7kebBt
ze{vAk+OtDx0+dLXUu?BObBlMGapl>goB9>sn)l@xU_&RuF$l5qMro!4R@-6TQ^GJH
zZo*PrB)`a;0^>W+YY-7ivGTd_xsXXK$4fKeIh<&%J4!3kEU3cBQAH!su7*HMg++*1
z_;{0%0b)ky803yrkUx@Syf1l^NOyP&u0)_7%|J3$u}bq6p;*30etMkcDR5R)pDH#r
z(5=+2--!1pjV!9{&>V;On3|UwCpr#7*!ff8`RV9<adwCSgq<y##=8HEtP!mq?+p=K
zWkqn-A?0k!!^6UtPsjqxf&|Yom@<qQNE1aTDCOd9h-_*NR{>CaUVmf>|5LJ%V?A3I
zGzic@sk}eM<_xoJqB?I$`1=#TFd=$g$iW6_1Jwpvp*M27{$&dd8w^%yf8Zf`$MtJm
z>x!H8xG>R<@jb7{i$88*Rx6ASaM(T;3FMFrm#LiR08p&{nk9g6Jef>__-vek$#1pH
zutm_4T)%|iDIJ8JJ`$jwCriIyO-GRr5dKGvp)4H(UfH5673lbtGAJvRNbxuV0_z-g
zfr81x{qz6wR+PdfycF35$+J|qKWmz?KwV~+NQ1YOY4_bUt&U7le<`L+c+oDu#>C)Q
z(Y8StBf^q-x<et-O#DbY>Z5W#aU#CqarbX^8Kl9y5Rr5|aa-@P>mUx1u7f71LuX)E
zu$2rq1QZn_MEfWigYyDA(+XQWG!@(0Z0o8l0!lD#AK+iVc;tXgvKWKEoFg@YSEt!X
z0BtSEa?=eCAYHfoQ<nT1W+ue`4?DM+I8E+pRrxi5?6>?4Hxe1$#O!!dpG|6KCJKE&
z>I4kC+wiu%fjE0u`K)J7huf^%<7ksqlGbGw2y@iSi4Zmb7t#3OD?D7qa`+&S(19*f
zkO^pb_E#d&PX3is{`=c$Q=$<21#%^F&;mP7uy_o#AtPAvPyg@%=zw~^GY6f*IfqYV
zcqzP&C^&4!;Gn66PZ86m2@qmG3T{N*Htb>t?&6J@qB8zRuRDj7_NaU|N!>hXYPZ**
za|5zSlm*D^kfp3w{L$yNF49@2%ThSXfb+=QuV33=xuo#>4|CD`uZpR6HQg*ZG#Qdy
z8xUU>oLVqV5bGy~v;X-;RGex2WoUEy1l6T=l#2e412O|%itC9q4^WrEed8#`2d0uS
zx|uF>;U<aO=(=AW95YzXCGB82RPAuEDw7!?NM}5uLCt{??GK~*fHl>(HO_+o#Qrli
z=s(~8&Er2`m+T2t#kO0F>w)i2@rTTU|IaqRN_>`rQ2ORX@WaaK?AOjJ0eVeGV`TSH
zAagC2cR)2)!6vU$8eV>(C5<Ph{TO7j25gt9e|<tN%So5D+Y4D5aM%dP8{PE7c_xG)
z=BI&~Px1f&Usg|fCw+kbwD(_mKRvf6i4p8Kw>ZmqlSdW#cD9$zr(FBV`@(EC>{O(`
zKP{UE2hxNM57!3~t+YW|$SC6uq<gd{!ShHuagqqf5D)7DB^kK84IQ=sRsc@6R`%Xi
zGM`0|9?!=Kpmnb+Q$=8fzSZZ08fwXbM4&UQ4LSS&-u~In-(7zA8FTD1LhJ^Sor3d0
znG`yg3jtW^Walv`X&KbV`(22$(j~S;p0>1!HIN)WuN^)}d6OR#a<Na;sOK#NHO!>m
zNn+;a&vcezWalUbsm<b=Orwa&5JjT8sPUn8qf^b=fvA?;4HUKyWf!;Dk=)P^wW57f
zXva+`)x9v}gEA1fb{rSM{eOaY9{ksTJ&^t(G-3sS(H8z6x>U5xIg1=;+9cEA&GCyJ
zLP<avv<DnoGQEDE;-FUsCTzPWZ@=hs=T9j-t=nIiy*U}tO;q?m96~4Xp6}R0fD7{p
zz>!Pym)!Y7TdYiO#wtMdyfHLoa1&W^zEy2|4B0{q;to*?v)%&}PL}KRm&<3<ukOra
zpBEoV@c?ML%YFx2W*<CYPR3P+;OtWP3CQNn^3k+-rWTntV=?&d1xGwWxo}mVKd=wz
zECko}{0G5Y-irfqZSMoEt9TmUXD!N^=MWlWAXvzoa_@nFuXHvjp_e92h7VDD9-%(D
zA$NyNvgO7zJlaf|Dp>kq`2(4S`=3MZC{~tg#c4KRo5k4YEZ_V^0xs=U`$?rj4v#_d
zJ{Mxf&VZ!#+nP^7_UMxMGI9cV(LmK_|JPXZq>MCG1bowbjC!9Ep?wG+>10V&Za16Z
zvt@w8ISI=GgeKw!q&{jRrk@IV=WtGssl_$cExe8!9p&RPPnp{(_yRd`CFH+-!0X4!
zh%QfLO;R?$Y(51cMA4sw0E!fT8do5{Q?U$b9>>WZT^|`;H;>SOMl%{AkWjcrhZ`e}
zqe;Xy%Y;ElqnURxn5hmz;5)HjUEZjI@UhGd>oS5HG5FGZ(Uo*a;qeBw^Ey}GK1*w%
ziem_KM`r6$Z#WFRTy@Yqm3U<LS4f0T$)`(L7{j6hmUWEYKGwt=Xt4i41u8KRVHIcy
z_W$v&boJ>I4Dc7TeAv=8pCY#gS2_bMAL$7JY6gE+pZWc3r#s0`o1q%d_N6*t(DxNK
zb&d8iX2<_n1@m|qJut7oT4up8UP{(+CrFjAGM`PtEi)8G{30I(8ns}cjt4bB8`H$(
zA^FXvr^5#AW#VC!C~}ylX%lK;Qc~S1kA<QxTVRr~@)tn2+F7?iOhmj7LIVv8NFafR
z-nx;`UpKcTOIzg5x$7hFw-k%EHK<=J0x98Cgu3bb%UEQ+MTfB*1BBCm@G0s_HAxEa
zXY%#Y|Nh^C9pX4p6)0W&Ltz8hRTN2VFhzncUkfoi$%~SfKbD7cqV1V(fA<}Ch#DVd
z_HMw?Z1TM=`;xt6N{>VfKGzymn-=CJ-I-VPz-@pfZzc**Nz*jb+r5CyErw0E20qqS
ziL{GC23h7g2}n^ub(=0ie)#=IzDRIlWqp)rA5Bjj0e%YuhC--O#ux2aFUpo0Bfl~v
zbMcQ`)FRgu7%vASqZa_RYx-HP5-Er<iD_I6Q-3eHOlA4I8+N>52jB64F$@T^v2n|j
zc}fIR)E<YLUt+Vu1~3cj<FZ>c1ave)zl+o(1?n0q!H`)727zdNT8q{VLO7FrR1XI(
z=TBzum|2!d?)vB!Z(X#~``g;vL$+tj71Y_INPw8mv#_p+Gxfx$gj1irn%sD}JriBb
zxBn)eucJ%OE?Qok#iJq(qn8FXGRQCDzgXIY=@Ng@7C3Rs@wH-NvDOqDK~3O}$X#`l
zs8^Vi1f>1^A1%;itnj&9Q)SY*k159cMJhNMY9#C@0|+S4Cl;q!(Ab*EhK^K+?kYjo
z)?R2OO(xSLp3$+GXS}lo+v?!}=s}=VYYx#Kc1&TH!~m+tTJb)o!x9*qS0C+Xl~ObI
z=^4y<LtR35wn$p1Db?aE*vrs1kh4*J?Mc4)XIZ%yg|qx9wh5L0C>Q*^%=tkCVd82_
z@Z(8l8QRD~;I$aHc$*ARiZ?7LUW8$jqATstp<{JVZqv)ZjM}vxecoQK*utPnH$Qj$
z*vIq+-K3(#!(nZL8gN=OsbC<CGBsE6^H&h%!n6)4BzxB2^PIUu;3I>7q;G$lTGY*m
zeXDiu|Jkn%(C!#BpA4lV!wjeJx#lrkF6)Q+$|KS>(2<UJn66@HA0yRY^Qoos1~)7`
zqNgBGzKvaV*Yidlu-p6av-WrA^3}fHs$HcRbV2DVBTq*qC6^;F(#sld&4MdV>+4xg
z4WQ3wEa_1_dKqRCT0?uc#8#<%7^N>f97pYL+9zaALgDv%;b!=f!E}-(bI`cb?QM)h
z^gU2v2QB`X;(f$im`deRA>hu)Y&E7o<%Z`i#67h6YGZ;q@7+WOl>Im@q60U6teT4r
zc%mhJg%?AE!Ipju`U-4$2WIte$}Idv4!wJhl}B>aiEc&5!D&{@TB0V62;RB+du0Z<
zHF-ksgNPYx<J61kt@(qapL#5B4-gMvxe7R0Zi*Pr<}05w^LgbWQ{blQB(t>2RRuzi
zE|CuL6ILo{*{v!gmbuUDh)XUXm1fpz6EhuZ-0$A&%fm1xL^H~o>-qwPU<Cfo9`Aks
zSd|O38*>>7XYhD;Epl;=ILXm9Yt(Ugz76CA!UUK0n$yvk6`pDmm|lu{(GJNZwd9TW
zy5tcRTDyix&JwU}CReBE$E@YDnUay9GmgbY@WWTlm|OY4`r^{yG0n1(8E$R6lhOGD
zJ8_ArP@Q0TYC<SEf`b){#Dm2+#fpE7acvyKv}-14&~14hhrt}uiAF$~8?R1?@O5=%
zL>=)*>Hedm+klOx96s~Swy{&EGi#jL2jkpuw)U4?>xGvof*^2XVj!1ESaPaHy(X6x
zo0?pcIzCJj(-b9<R)vmreWcihg_N2KWTjS!z_|D1{ONxdQ*27=-?q2%f$$ONJhr@;
z0={wB9NyB-6(+i4tDh^^A&ih2rG9QVk^-w_nv9599jW@x*q%d4xJjaNi-t`3sC#W3
zM3QO4lcB_Ts+t|+=t|cWs(w1IOc@$?aE!na7$zH?QOG5Vfu|T-2g9*xa|M}S9S97e
z#ZH8igrWn%joA=Op4|!l%-ng|?gaF6x0uDO7l8>4gs{@}(bQ){1zQ;6?AYTB<G*E0
z7>0~!mqb=yv4-zLo~ZJk1f>0s#-*pnCzyUb9<{mp`TnQ>Y6VC-5EJS?!@nHdO1Z*}
zS;|T%b}4mdh_Q4d(j1OC5ZvM{S_YgDfS7*RZkV_PNI5%xGI);*%&N3ywdk?%y8KH%
z!XomCvWTHrEJu_;av)Rh&eUn_<O?FAxIR*pS{KFDh8`wqstIN`&QJe(oC&u0n`bC2
z#y|OQK1J{pE>x}r!-D6)@KU|b$(ZwB1d2f}6Gp_xA*%y3qnctK$o0x1uC2J9^L<_1
zWZ7iUnpm%*9fZF(W)rf#WW$y*#zL!e{HUuy2RzAP8r)MYN&1LCu!5LUsaq=U!q&)1
z0!8LlxPTHetLZ!@2>$Os*W=RPfFh=sdoT+CEX+qKtT%`CGR=wrIORCx+Rx_*eJt7P
ziPJ)sBpt-4mRckqV<g}vYxVV^u<Vj7<-^E6E>u*H#GUU64^I8X`Pf5E9cK?|VlXj;
z-3FC6!-!B4@sAp0NP$b@MG-TK3}qpE%+Z@x`2Y9OGvheJxYl#g`|PVd%yJdXBVj~<
zy9~$0JebcGauoSZ1}sT1$BweE&Hs#Udht4i1zLBk;*arp9xvXNzNAUbt#LED&8>0y
zH~YRjwL=MmVKF$P%NVP0_-Ig`1WEe3%ma*Bh44VYWY2ukpo~S37+6&+puly%gfVkH
zDaE?bI7-Kka+!&1jf0S5Tntyo{lzyAFmX&}nR<lF=#x#Sqixl64=HNB(<8lE(J*S4
zlD#D!Beo@MD_QgiJl7#7BSV1DqFcEA1NGUV4|*pi?9bT~QwcW}ZF!4X>LFxTkjCyL
zBx@Pdc)}H^5jETl(Aye=6C&?vL9va-uvEKxPbeF47%%Iux_P<mqVJT~I~!r#LA@vQ
z*8Hc~X-ShBG9u{F7;<$Zm(s*OCY?Gt@)ER4o$ONf^%(1vv8BBBRrZY=Jz2uM&NC?C
zJY08u_IKM)N6hSh_j2DvR%j10j90wZyq=8Qq=DoDz}^at@~PuB;&vSiVfPlmjqC=0
zrBrw%8Khp#b&KpYHn^vCNIDY9knrCXM^mSMOp@_?U#kg7DuU~BbkOG5ak~%rjRMoO
zIFQ&!a?QY#a{@3w0^*8d3e1|rp||W~s)0~taGQEP0FQaItp90ldL<q*S)@Cz-SlKI
zmS&Qvwg-R6Dz31cR%@FfR1Fkr3S(Vpz-BMV`xXFhR1azUFf*$@`6#jQ+)qEc(>oq@
zC-K7lv1fYE1uGP2`(TXvW%SCyRjBNOfe%sn45<Q`8VH!dL;!WnjUcS~RB3Ra<?ZrO
z7yXto>0LX$3<|Bk377s1{jkE)yn*_%`o`jRb!d@$KQ$?aeF^tbZfR@2Y;~*i({#q>
zyKhBlK^zio-LV$Z&sn{aF3}Oo3+$aP-!N)OV1VL5k|f@zNACp83t3@gd=SJY@vyI<
zEP7bN{Vhh33wIR@h~XS=p;=*bS;M+DtmNITX|2bm-5{V20!zpD_qj~?x%ggQOk>05
zW(}I{C?OW_66evLIpysXL=VopLSoe+qJj)qjUNElrFE8cq~G@)6JOH;K~p*T`_Bd3
z?A@J-|14r8&VrJhnITBKCJ{8ZW&V;-)d*eF98acF(^iV*$4BW^2Q<?6byy9AYdY}K
z%5U#@o^nkd0GceqK%$gxZObH&7PIbkLpgUjQluWb1gQm0{$k2FiDO1Z0nRVNXsx28
zqr;x@woOgxo;<%Uga$N4CK8K?NQv(E|J?wb;i^gQnPaI9Y=a~(9qf!1v>7Y59CMOv
z8q}6r+E{V8nubFH8e+15+$flAF@u6eg!;|AwNqeJ6J#|+yNYSDgHDkYM#^=%L^2}M
zBB+`Hb_6`;S<*j&?A0%A``ig9v}dp3Dn+s!%baF{$RGdnpRp#gG<rP31S#1;R4e&^
zocl$^aHhw{vNcZd?2w`pXCP~xjXh?<FRYO(BMhK|Cmq1Fk#ckesfYQQaeAVjNlWmH
zK;*ly>5zoxP^$~YnkE-+HL065&*!^K(<H8+05@PBPLg#Z>p|>{GJBUM>ee(c58viP
z;T&*PyaN@S1XO~5_2$o>R2zu;Y)E}rLW;ojO>7XU|1q;NgljXiysZ*~XcB4orvX-+
zeoyMMObB!rG$ZvP^?#i!Fqhl2%NOnMZh?=}5f22urR}Pi3o|lW8&V;2Z=vSP&rq~O
z{ZQ-9fHlQh`IhDKFVwmnb=gM?EtMC8;geF}n`YJt@PAwiHl6$b<i8uhktnQo&LnH<
zXQMw&q<>WQ9O%ZH*<|u3Rvj-8--Zm2qs7uGsO(|3<?bjGUxQ<$KZlZ@)V)~g96pSq
zi(Q3Bq*iJ<ur`Kby)Km<@C3e5Vl%;T)gc<Ln|?p(hjjL0F?8ag90)1Q>8qkLLpQ=a
zw9|je%ya%oEZ1LV$o8mFZ<yJqSZD7~DU=$Qqq4V2?K+6jSYWI)g7KlI9&7ph%)exb
zTZxnqlezp&yFjmsbn3;<DpyFNx+k8jY3&%y7)WKzQtsIg4-z9J<v^W(cw{u5^Y3e%
zIJpuqp6OzzzU5}3I1xr7{^&FBf-I>}kwDLxG3(u6x!|>3OJ%99<ug>jVwxp7*|RZs
z7BT~o^ME9ej6(=X!jODx+4M{>p>Pxl_e+d;LWs<RVOnfCd@uimUE*K~1DYA&(D8rr
zf$DIG)Q&Bt>^N6MMz#N;m~G*2{K+>DoCKtcfj(lIG{?ZhU*=rlpJWShQR%()JzOCY
zycFXgB#qQs+v$~qvarWo+A|`1BF``YX@`+k{pEYO;Cr^m1Sklk7V4{a=p_laaqS2{
zFjRiHEte(9cC0IIP6nP<(7G1@>BFJ%_n(Tk_~bj@*M8F=fh7OA$C)QifzHW*3cFl`
zo34^&;w5ksH74JA=J=bQw_s>%z`)T(AOg8xqD^lX>VqHAmH%EMMhR8D+u4&g8Q=Dc
zb0i69CrH<ni^?ewK2KZ}FFduewCe?`8c;_>JDj7?A>mcIp2GE%qG?y5N@2AOX1)L2
zUtYjX&}oKJU0$}Ju(%=e?;4zxtTr@~m_gw%5aOqYS}n;3rLkG-vJYo+B5VXe{u{G5
z>s-*1d|z%*n(KQXk1Cx;Z$PwErS;Xh%<!{q?O=W$t9E<EPBW1#nyuvw!ofn8j#$Jq
zMy1hYavPKOs32Q;K3bA~R(J)r_y=G5S$bup=`n}sTcECF6lu_cM@y+G`gxEih*0a2
zO|@-lkx4gdhyldf<9ULhHy`m6`{??cSiGG7uKAjc5`U4w6gG)}tD)c;ajcT+rjlGv
zKF6NNmy_?T>y)<sF$#F3FaMv<Wl+|P+YkQfvXn1)Aq65-u-}M=8L`EXrWMYT5=h(I
zV`mmH>curuca@R$mM*Oqt`PidGf1PvQYUWw=w`)!SN3!N_XD|Np#sO~RGlr$RZfT&
zMYlNmbmn8Ry`mT1kN)hgF)EfjayVDmwj7!+O1>Tn!3o5*=^;6(_($)lf6|2qCbo-%
zf-`+|!`zkZUFh>UZjd?1#abr0T8yHd9%$x!F9bcv@%9h=P}XG>oVFr39ZGrEFk$@F
z_i(BIY0=Dwu@={f@i;8>V^#<h*cQ|>#_A_iSW7WpdZ1D>wuR+p)Dz&)iASVOi3U=w
z<iltV-D?I@ZHQfL;U6u^M#~iEqWFE75-<$no=23l`Hdi**$-SiY9d(=AZB4rEs*=I
z=~97W(+r@ON;(2@@NR#e*%EY9LQp45T=ORtLZkSKX51u#lZ9#byoCbP${SGt$Db}0
zwnKBnTo*@8#ySZ(=<7kKZ~5rCUTgde)ZoKnxZmq4PN9v9f!~ja`QjMxV3vDOCN_||
z!>B$)a~H3Mxg)(DL(Ul15Ez<35P9Wpmp&8C@8kw^{@=`#+B$40KoA(nTy4^F&<GX~
zz~G$c)bw`SB;n9K3p^~s`%1B5mAQJnM3Ml-$C!Kh+_cwg=X==Do{aa@@IM+`<wn0O
z7dT!L2*~lGi={B-GwDB<MgX}OlhFmtCAF4VUW>w?%A|Do5IGY?8T3a766&G$1oK>W
z`Xr?hnG&O0S1DQ4M8QUoY*9QeVKd|?X!+UB6*C&(gi(-KRC)~;3Xyi0xln7`X-$)3
z$|uRgm};EQlNzw0pMB#~$oyC<e5uV=TGVFccB~v>Rf2yeQCtYHe?v3%{!Vtt7XV;u
z`w5z5q=wH`sN%YwrkIJ&<ooswz$<T`4y0s>T@U6V(earr<1LNCvBs4UtTe;jPy&R3
zGpi$hhHD+=mJiUFH*iIt(DJePY62t1uyj1V_teJ2C%FF|n!h4r-3t_A`x)_*1+yNU
zlE8%<ptA+r1l->h*p^T;!n>^Jh=|-<M~B3TFc8HAF#F6+1P3?dQdXIX1kJ>a7e<E3
zT+9<Ul**I<&agHh0JIYFWet$PX}~r0zsvqn-D?SGm9FqfFbZ6waOfZX$C(v#%*1oh
z=o`~8D?`U|T@8-@lv&{varpV*n<4>Nyc@^!)$3Z1YGOAPsezVc6<8<L69^!#2A%jG
z{OEJRMxRhMB4l~Rd*D@zFz*eA^)>Zlx&#jJ%Y?5}$0vpLsGSQ2QfS33FHV<z)E~MG
zr&BiM?n8Z4zhM0RCzFUu4*U97hQQo7Wop0#xjB}LmKq^%AuI6<1Bg>p{<2NsjNWzn
zdYI*8P=XdAF&MBJBEOXa9GxIc<O+JvbmRh_3zathVE@`=XDkf_?f{X?ArcTn*;y|9
zmO_sRY1YuBIdA)S6|J{vE$|lQ9{Jo5Z&uj*`=36)a5n&{W-Y=M9&VS~#36Gat9tie
zKS{$Skffr{Bp$`NK!B;B@II_8%j1=v^mQrU4NoQ|G;*N2j53mJgL6lcgzE)?PlhFa
zYKempQ8g1QV$3_!o(`+bF}2BIKO)%_-l0~U4k3*u9>(o0+#fu_I6%p#*+6CqS$TU9
zZ$vAMl=n=SPuj#5*kZ9v7ANIBl1i~FPYoDj_X#N7z0)oFcM`7047N_1ebhFXOwX;!
zsWT$r4vUD^GR{HWlNW)H$aXp4Y?xP~OJ;ByYhVgq`YCJtIK@KnJ@x3PejDKhCyi#}
zv!+O24#GO-tVxBg8N1{~@FQd&_Kyya%;gYBFLR^n$Id-Xfm9kK2MlTsRKnmV(@9E@
zPuLF)8JGk904ICYw+Ht$35<5@pF=ElDiTbEMMl)XQsjrK7EvwrEk1g<@+5^bPSB|+
zIK=%cZmAeX)JZ7nWD@VfUr&N92C@YLskkKT@jbTl5mcz0_Uz+QAQ1$}CcMFZ(*MkX
z2dS;*;J>*$b+sZ_ybqz~*ev@zU*1TPI0&B2W6DHcZoMOLIXwEHQ39k&rvWj)394h3
z5DUI4%;o+ms*-ONnO#8+ql&l5VQ3F<zk$4)L5U@U@<<%*#8~LD+dcA5EK59ndhvu*
z{YNfac&8kax^zl9pGzZiY6KfqxrJsFT>*nPaM)jGHPO&!*)p)vsBPO5UKV|5vai=q
zRapuwHQX{3yW6d}_q)56U{nCV4EyfGeV9inQV|j)@Ai0Kyj(svA@6{n{oKF#1sR1X
zk^W^iR<M5qVM0pL(ps6tk8(~F8=G7b(3JvVc2=a;+-N~5uE_a!HnnDa5c}Fta+L{l
zO-O$2o&kfLP=Jx(W1OsPQ3{pQ4J8`K*?~o8U6FX_nCE%ec?WMF*1zGF+4=6P{Cm5b
z^CbC)_d9Pt#D#;|1vx~LkRIH1wsQ95$ic4ODaTE<2jZBq*rn_OEpF1u@sY2eSTkj!
zk7oQGg%uq8sTTv@dwq7f{pG+47Lk_0aZ@*S)Z(s=Mbk=0hAw@>WwlWuABOVwyKzbj
z3eU#Wap#^THz)k`bMHmOPgJk1cKSg|Oqt|g|0d}d?p|f3;MhCmPnwL-z}>Tz;%qYb
z`s8eUcCoiZEhRHx!Y-T$e?@;Otjq1@e^NVxE6UHJd5B00m#iKOgQZ6ANG3el3>@Pe
zyvSsj;awAqz05#YTEj;jJ8Tg8by#4W+-%5=B6;a$ptkYs7$IOROPLF974Qjtvc-Eg
zDK0CiisvgNB$5b7-XJIQg1LgIaD8Ny`2=bMvUHSN3l^-fJ80A&&T!2X#9*NcZ$rHB
zJc>(a@iU?XcFQ4~CMoDb7WP*W%+b2$w9GXgT-Rk1ka_(<2u$sjkMVAaCdoVAALvgN
zx<S8NWJfurf(<Z|>{*7PN|J%{aw&XfV|-l7@LB%h5l#*^O-{^vox$XKY7;%d_e>sH
zw>{og%$q!{T&!xZ8M-)o1E<Ntq+V!O^@_!8aE3k|u?Amo?r6qLlq2oP0da8(1aIPU
z=l011azF=y4Rg-iW%|M{hxnM<%7Nxf&$D@`r7*wnAwK>l-unX2Tp{mU6rd3=-m_pa
zNN}0t!x@<`!<aU&CKR8+LpAgV{HykBKnvx%gBG`nTL4FfZ$KVKT*S^6;y|k0D4>~F
zU~y%%Vh7P(`|fjk|D)}Pf*=zFiKH8!E&n6n9*2~Yae%B~)y#iZadAiiLRbE8p-~h2
zi$#tmF;U3cLMM%mS-FhGv|Lx~6CpnX{x>s;;Q3vWY6e6x>3nG|S9C)1G72#aowdG=
zBXxsDEo5B5r93|uAq`0=u6C4$Eg6>c3ds{p%ayX?bBXJ2ZDshb^?WoK@?0zejF}cQ
zA#EC}^f6GwoMM~>!I7iFOCM0Cr*Msx*JD;3ubcgpCXl;o$B1+kME?(KZv!32b=`SZ
z6(G7LD@oTwq4m&$sD2NHW&xxmqDd<qPB!jpG^nObMQ8}}z=|RR5NXR^XHC*dj@Gkh
z(yzN(1VqpxXvm@Su>l~^!+7nOWR$GqlidIm8Pl<13$&eRX1!~Yma|SKSyQxUNA{Ub
z_V*f;Ebk<<XV2Lt2?CAks`qi<d-wkD|K7{ld~3xSoqGV%cs;feMC??B3}*oe3L2Lv
z!e^Zm)=;T{HCWORX|wDRy9+4N&t8Wb&6e0W8*W@!qWVK=Zzt!-wQnVp91a}!xFFDe
zhyX%ym+xdLobi2Ml-*#6Mq2zNF(L=~%I^616I4MfhuMtN8Ns&I3igsIa?T_aBFdIe
zX?$-$GX2vy-*J~#!1pSgb6)?(5rYa?Z#Fm+RRfkZ;SKsKmpvJNJzp+YIEj*zyGho`
zfyi=*KKIlnvRWdVQlOLBke)lBo@a(||JfR6LkK(hTj1uPD%Yoo3?m+KM!D8a=k%l5
zI0IwTVC>qd;L4X|^f7aO^^{8R!;&-x)9{M55IBy<Dvx6&5zB@a#L-+LuuFk0L9nw$
zN3b;U19RzC-9J4&@&cl>aqY>+&d1gl1tN0b;H{g347H4ru*^Z$&z%hFkWW&IvjRo9
z);DAsPkn7S8atldABh^G-YMZwqR)lJgwLHST!<Th8kxq!bwEX+#bma8B611}a~&_`
zIlYb3Bhc70oBGQ{Zgr-KZ)DcN>Y>qCc!YD3LPqC6YZf%2m-|MSLp37VHDasz&R)MX
zP<PquS=E3wq8k`Od|!0EW2|8RcAyn){5{EBH~>ia`!gxr=cHp6gNDX3u$Iop0@*TM
z*|KqUzW=dLpB$s!CII6sp6;d%a7d1*$iO^``p;Qo9j<uzAO)>C0tf;er|uk^KYt(K
zaE9Q?xwowOE1})475)p?+fVi4ka}?L*1c9+vD4&tTN&o3{_CRazY@fD_VahR-Od|5
zx&=5@T*lwV<=cyce*geEh~oxT4^N=&41eyKJ{Nv?`cRw4srNs&eDaYBv1Z?7&DjDk
zu#diLc0`0fTkgZMg2<%^K|!|<>4)voe)~1Q?~Q)7Q@X~efoNvn=$6L5tnOj-A^<8V
z1%xboxJ=6I_U9hWw``=tM%V(8XsPIPzw2fy3z*<=SG$lUn~Uf!l-PTQ2$m<t7>B@{
z9VD3AL&sx-w&@`TJ!jBPP(N+6P63-13D@EqQ)_)E)^k&5`DXP{A)^rjFm)vB>$~x<
zyl+24{O){zdwMoH6LSU+8j=pPAEIn=-^&`tU4<0A)BD@g`JG4X(QdtYeC6iXu0K=f
z3|eKKI@UP&St3+#L=(dzs`b64HR;r>%a&aqo7vzQ*+>zdz!i|>?#jRAO7<cS$<0w6
z6U@q#MA`OK|6f+{Ul5DR00!^IZ^;iEVug!V;&!oM2v-jh!KX22)LnTv@r2jdDC5c$
zEB?Y8U5zpNzH-T`*jd%C`qu0AuJ@52xUgl2kZz>vt>aj3E91g}kVWJuRubaZ9_)70
zY0>*{3_5vaTQ;d&{R(XDgy?*1m|3`hP^aK_OmlD^(tlY&6l{9m{S+d$J+ObDv<01p
z0i=OA<*trN4Z?gC+0pk*Q`zAy*V`Tt(#==a#_5mUY)=9*ti!ovYrh>=O#k=0h^%@?
zyBN^u8>5fdjLm?4r!41#;wo>E5p)GR@HW&Lh6ckz@l9!{cVNjSw0m&Aa9Qi)mUuh1
zudUWGoYaloXg6Q&zGMqH+N-h03&QqwjHs(0Uw)x#MZPUDsLpUP%TKT^Is~q{((iTO
zaUB!rBaD5&-JIU2UqquGSw^9<HMB1`MM~$asBeh*jTEhxgtpQAvAe0JO9uJ?J%lsD
z?&je(AGifqbbG-f1aA=<#@jYTF81NPjs_dkdK*jujCbt12lBR;ZHYN)CB`<}j(W<u
z_SgIC%5~~PZOESVx?5ELCENjaiH;G~d7~-%<QS!>9qe_u3s_^kASQC{#_z2grvHt0
z6Ss|U5jd=33gHpwgmx7wj&eMFV>WJ!2eVFt@f*@^e@57;u+DG~g6F(>xkcF@$lpiP
z_w9f8pT!7!dy_eDKVehzFSkfD&_<h4O#F;d>;Af4XOr48#IW~2RCqH=-nQS`NCGvC
zP_N@iJchb$u_dV5#cFe2-smhPKnKwqBrEo1FeWNUSSQ$|-IPcJPHT|#-9#Dk9Sy3m
z9uEd^H^~^rc}w`OYl&iZ6Zm@NdKligytjS%1slMLoChiAPrtHh7<akNh}>m3bZwHk
z{zKv;g5BTdEhwNUY{>L7-z1<=oC1_qiK6W?s?%ig#_!+QAIZJIR?1ZnS`(*PW?7*1
zPoslx1FsmNVu{`G7<>XZ?NHj5uUBf77@doNG~87YiEIa^{;3Z<^2D3_J9*WeYrQKD
z`B0$i1npwl#HDc*ss0U#*Zprvxj>WH_pFeC3D#Xk+75U7zy1beKmA5GmeJ}VryV1s
zRSGwsM$ORRc~&<sQwC=Dew$SQ8GhrCq60R~ea>KJptn(84}^W2InF%g%XIer)a=>#
z#HU(T=n)&_{`{Kb{On&&#u-kh5|x_?H&r&PlufK)rM|!X6Z<>Vs2qv6W)K(j$c_1E
ze}(wP|1^I2B#4&*9qj}GNNtB906KP;u5&E0*KI*a?7C|ouNc@jhW)i5AYvA38Crv-
zMn2CcWEMVWdpotw=0e-!k+JCue6<-b?DlA!KmA`ln!f0hNZM9QU5BAX<NK_{?|8>U
zZ-@d-8$=YS@M&F~trNv)&QIlR0O`guwd4Ngj`<j+I#SN8zYo!wb(;;e8P#79m`&%b
z#J`~&>>J^bwLdcK_t_v3LedCr<4eI_&7%n}|MBIoUKlGg=odD28q{o3fn5JTK9Vy-
zK@KZ2KxemVJB_EYJIK?4)c<(BG8xzk7HuaXbI!G?=5FX~T&-g}R}B8U^CutCF-xQA
zkI%sVLwnCD@0cd{_}PLevnkmnNTld)+lh>gy=(t{FkY|t5CO1$i9r#h#M+U+`p<mi
zJTk*y`eAqZ&wt2*wb(`h5D}rj2+N_iMq>y6Cz_vF3n{^es3|$&wFleoHTKUKa$&o1
z<1cJ(lJ3*XOiB;B@P7eiFy~?Q?jEDzwE2B+4!!+xfxt;XIb^;ot;=jQeQdw`?kj&7
z4fV$5k1+IPNNIPMBsJ;R&nJ$EMF}_-%*emiCD<Klv2B6(<CZ)^dA-z8iO0yv%;4ZC
z6zmlnYxRvQiGO`JJETs|GdXiLEM!NcmDhmhAhhQ%akyXNSl!U9-c$x?c92+Ipkaya
zUjK1Yba6!4Bq(@JHq^Gv-i-#grwFa>AD_D=t~j<DS&Ul)KU}&)p^-7JmVwWXQa6nT
zuEQl<do24XI;P|Frl|^9>EO9sAPp7-e4F@eVkYxc^hBfSIejKRgp~&xLZFWBB-{qX
z6FLOQ<)YtqoU@H9$$p8!6y>i@FYC${;>zGPD4TyAbtCy*c{7>a&IFitmK}h*Z5}ri
z@jS{+W17%F+;g^4Z5xgAQxqIQ(z@(VY=Y=TA-fq?qUDRw(2FDA+-sc%YiD|K%3CUi
zeY+Up2+Y1F#8w~AD+aUna2<olSfHhSYdpM>uH*22>qS~yG&zez*){+<eC~g|iS~dL
z`fmM<ucmCga4B{}fQA)*QFk32Zg?ojVvakn+&G898Hc6R3KgA@`-R}XwU~5VHc8&$
zrZE-<x5?u&1<}XuMm_+ZHx{NhIq6Q(7Gl-VSjd3*T(w#EonaG1RNL3Fmpk~NaXNr(
z{^3oFJQBw%ZNhPZ<%w4tHxV$19YNbb>m3lY;H3<ok8eQPvWc(&iTeRkB2z~@3(MTm
zUbDHkNwPB=dHWRZVu-Oyb&#4&Z?>v4#1y8S)ShkBi?MU<5*ARed@AaQzVDMXaaj*A
z<*XzO?vR<L1yDw>e&y{Jim_hot~SVE`4{aU`@!Uxd~6Z=#FTJ~*PkcE*YqJ3+XXdK
z_mwR{y3*e}@yvyQWIN~OOSL&lSJ<&UY<;dmf~anT9;WOP#&HV9WbJ*Y6vmyfqft==
zI6c>_2|}0%V1r5;_KlUpit6_&rB0q(znbmbkOscq*0!{4Mx6}9`Wi3@R1C&)BR~^8
zfTr1jDYT(-upNgYycB8=gK{U!9w)(xUMdA&_&jJ0m6NgHmlZkr`?fWgNP@boOQgE1
zj7^t1?SXD_ab~9Zyrwcy-)15k+m~48a+IeRz&h<$^v<qZm}W-Z(x9;dVd%>2yua;?
zACEEF_98pgIji&MmIN^kx^S<T_v+pQ;a)FxMjo9BTh#xeB;wBA`%Kb`YBNWCjC30r
zWF5cT@H!D&F+8pJ3s40RM9gs}*a1K6V+-550|>rQD4o?-pQmkV1ipaiB++1uW%%9~
zH?=`L@@EK3w!~J|SBUuPhWfLym}#7qKVF*PcWx{YP8jgziZjxQ2fYfrW~bb9#gO_>
z!KpbKB~AUjCQPwU<MnH6m>zf?Lt>vPA+TDzT9E>Pu(9mH!ddO!t2IJ^HyILD+1nUk
zBGCSR8*U&@OS>!}W3T)1JnTxv@+IMVdwgjRFoH5JJ`_X~qyt}f$=heWrohyl0HtQF
z_2|Vc@iA@5%bY0AmWfh9TDL8WfgOb~RQ)(HNAnJVnPcw<q)FjSTgPYc+kN`ug+BJ3
zvFT{9*T1Ra^s`%9;j3TY+6$47A`FC4U^iIj$z>~blwj!Ys<oq!Xdz;TXv)PQ)`nW5
zzWI{h7u$KNjPI_fk<OSIWv?Ee*&M*3$w(G(>Ttu@!U|Kcc>Iva2}|^I_T%tjZeay(
z4$urqKgfLS(vL%=^(i0V^n>1dIQH9D*`Yab<?T466qz{~K58-DPF>bDAJ-#`qFp$T
z<zqz-);81IUgiv>rwJ856z<gNu?lnhT{HTUIoeA&*LFtFm^_KpyC^xm>-j<+VnnEL
zJcC*@KFE7TRIK1-*#ei@D0l4owx&WyxuE+z{eG?EDMB^SU6297_i#a8!4FYt&nY&5
zEozB#$M-4U=HHM2iMWArGQIXM)N4EQnE)o!zWCJ(6Om~XkSY}VC7-ZQww9sdkpjHs
zf=za!3316|xQyo22<OJ=bSdbpqq5s=02LKStKJ1sYS7%c4Db!UkDcQ7-txJbTUbc2
zAWKV(-)4U(==aA61LzWd2WbM^>#W@_8wg7~OJIen&sB^Ydvj%U_p3{-#}e`>z5J4*
zetho?%-B;yNAz||i&I&M{5e*$x2}6CYsV_IX=)A4W8>QecSnIE`v=6bN?XQpT6oqH
z2pPEcs{QJ~+jDMx3R&%5NA85bV_nR5^?^<YLxjDlkUv(I!9v*V@V(YmY;#J*o<q=z
zr4;PzpV+1dc-u=03C?_xY6WDkE!x--#7ga;)GiAc?pXLT*{U`%(X?=n@<W7x5>$hI
zeO%YK16o?4++Z-aY2n@2SFG?|Tfc;4*`Y>1a3SZc`IzoQinUQL*BEK&+ekAKXbgG`
zD+BtTuxTkuUWhe3G9FHi^p?kLQN9bk{~d%lAI3DQL9|>rqHM_3HgD^YWj+kR?%jvm
z-JS?M&#}*BdKG8-IZL~L^O}9CLKimH?zyKCJ&649vS8|sQX^w%oy`5+wIRzbZ@13l
zVvb*y_=ejX<7Bhwn^HMj3(M{-BjZnxWXGsD*ZcLVd!P9WyFM~AHs@%Ovkg9*O)wPU
zFrF;4ez&kfStF2;X<%%TemgJZ#Kb|#HQA;$+iqNG8Ni!ps$C}69{ZJ&O-c)rIPZ5^
z-Wv_>CRfu#{*Ib&by@4D<qWZ`JBH}8xx)P9tK{f~*5zy8Lv8Gg`zz#Ysmi_b(Y;4|
z*XGs}TXNF!;K^!u%7-Ve^ERu)%c$lND(`f~S{U4xdngzT%s3kvuIj?Qmr!romknEN
z3AKI`)TPlX02ImY@BfY5R6K0SBpH_SZTtx&ngbT5A1H^z4%O7g<J!Z-5-tejvDzF;
z)n>l2+99ug{`HPuv_~GA7g-edK+T%H0!yNSTerDv>lyWt9g45h<(NfVLg4LW<(PU(
zb&`=9h?f-p3OZq5f#gUm|1e$tMf^m#&1@zgbLS;$?D0TOWrlO!4yrAqGc_dO=?%M9
z{R&H@%LN^bZS=kIA&U=5Q6PzN{T!+`)=7o*nw$3jbXaNG3K@I+g@Dq#Pzn2vXuBIZ
zeG~?SI;^7T0bmG^^qRu1UV+(b86<j<Wu(YYj+O@eIKUaSZCb0i-;0&yiKYl!NKAd~
zPcGZ)VvJIoTzVUa46LW@5CKXtHAi3+I$_dk7j>~|W9=bG4ppE^=(<=`P>LHKOP)pl
z=nDC>A3YCj@mkRPWj59+QxuLZmwmO5nAQ9t4ZNBIOt!>!##6k@-YaK192)!PHRv}3
z9<rJaxGLcVBL%!-?)sGzlktNwyEKVPM%!qP_1E_ug!IC31C!iSX(pLeRw;^0SQZ4!
z8NS`oNH$%W8-j7|Qdcv!coF{6KO0G1c(mH8ezVeM6b<!e-R)Ek5E^ARGp+hw#C2A#
z<acjUVSC4B@@Xv(Xn470uDWqe+PhEN?G?c@NonF@2@jR?@|L$}*DG9|<#4pcEI0e7
zyUZD!J#60_T94Hm3~ApZgIbfRM(Z;q-OtU7T|Ny!NeQ(#66_xT*m+`xsmM?f_ZbO~
zFmsX2CDV;22jD8~687x6SkNPONKtA4)e$*mIJ;3-bat&k@a?@C5e4?s`Sw+$9WXq+
zP13pVTUMm)W`RST*yedlbDLCzm6SwW<}CD9C{RQ6Axw_U6GYKcquTBR+tJz={T%QY
zRkUExS4JM0X^rhY4*+zum&_wS-%G?@N)%`Z*mQKa2ytp4)mYPrfHT6zEQi&+Wf0=p
zZ5K3(enEs=tp~rs$y(MhAxERcan{J>!+=J=(^GmOAgEbk#E^`U#eXNQzMTzVC-E7!
zBpit#PXXbX*?Ai{?pwiWMVxjyR=qPkUCu+v3o94yA3q-_Bh{~0*8=*pT^>=h<O3#<
zs`>H4Wo3;GoRS=eb~xL6J<9d6DpDV`c~<mYQFg;a<HUWR8B13Bvz_p}=Ey_9gRk%U
z50f!dfF*N~LzB&v!&9v@>!X(U<a2i8eI{G*3G~=?h7mi3Jsr-i&Gp$>!q=PTl;Lpa
zH9{fU-o3ygI|GWunPjs~JZdw&3cM>dCiJSliV$F5kTqnQ-G{_16ri&Q3Um?zd4}|^
z=2YKZ)Z?;OUM(-{UkSH>FM;ko+DH;>ydnd%TA0-UiY|&ATNTdX-ubR;c5mgh>KgSK
z5KC#X$JxB3&I4)IY%vR*UK+zr^zG2Jc`6NY1NNlcTb19Osa3DpiYLc_Qt8~1tqA5L
zXIt2)>I~eLwt)a^#3^Bhp+nTQA{Y8#-;!^Yb=LoltM;k$tw)|&GcoiuvLr%+`Bw23
zYRs|_jXCJY{O_{0BC;iN0Q+UP-$QO~U?lcEb#d^^*%RP2<-XW9JrSV{U?=cr^i_w5
zPXeH*7(y!X?;<be$PjUhJBm4%WFT9V!={f9y^|<>Ce5mKF)g(K#$X4TPW4Bu=H!K|
znk&g;NU-^><UibN3vE0-4danU5+d0Hodey(m3N5JkiWAV?i(7C#SK}32}$b?O3djq
zlB_;+MB-B}2a>oTEmgTPt}7v1^@x|OrN4PGuI#g@1^KSq*Sqy00v3q8VmMVCy&uX3
zeMdo&aTX1V6V+-wS?Dbx6NCVOcA+3lkyqv!2virWBZFNadgpA49o23b>wavYcvw}m
zXI%gv+M<OV{&X_2A*==>4&e_8fq0~%w%RZ<FyQuaq5>6&@!bGXl(Q$TUNhcHqA@eu
zHPba?+;A(f$2`$NSJ_tcD#nLBs!N@v6~7`l{5y(RL#v|i`JrPQ*ATzxjlM5j>(9zt
zM+gAy#Dx+)`>D5&giJxn#`#LSS54ux%3K*@(;^$-P(T3?`k!X+r>(?CPnjeOkK8AU
z*Krg|8k=^BeD)Tu8?C@fCO_iDOU)@3pK+7ok-pik$U6pU!-W6>J#0m9DdRy8C`iYk
zZVr%Ahw#vjU1SYMLRI#h<}&d@Sjg{Z3tn2W91#`?j@f&@^HUbR1+ci{`|JXM26j;W
z%-5iJSpCnX+9npcWwNvUC<h9W71*Mkn;fmh0{LNScQC#We_3VoURxe(Jjv{f;dU9f
z6?qP4c_^{Sa?>_UtAL#B&$JKzz4HMz=-fKCD%jOsg$&c*@9F$9ORkR%O?c-`3pN@2
zpoAo+4{RmHD^RECLeHDRzO*FQZR*MpaRl%Yd?Ynw7sYc-J6{I;Ax&^xWllx3)t4w9
zqnh!2ALTkIO)@t4YGOv`Mt(jR`4e^%GR;-Vs;z7~85>Z~31lggoB(6i7%7pHGYHAc
ziV!Uddjjn08$S2r%l3Fv`^#fVe>Jsc)~siS5*XM2#UEIpMI~vOxN$`!fa#fvSGpGk
z#X+-G@E@z=4I6G4CthNroYxmOe9yvo#AT$E(<<*Xv6G8uTxZVHX25kgV9+i+{FgyF
zRd)gPZ15a#NzC5w@x!0~!`n(;NqY6TvqA#e7(}*v#^wB~u`nv7eR_L@Du*r|mx7sw
zN1!P3#*&Df$dXhbi*!=e9B*B61i0V9LUi_Vfk{WkW&7h9ypYj|2RhFG(w$~&01k2a
zL#7dTl;-+lp{zKO?Yjv{1OrH}T=X_ivDMQqjmbe56t`K$+~ur>Q)dq^`zrN%tB~vI
z@vL{Z$YOJFBd4^lY=AG{x$kY2^Qg=gjAIb}_PJc5!JUk)W58i(3Rk!P@>~bfJFOLt
zb~Nv&y>!{u<iw1ycgUf8G(3Kh_V@%Ep&eW2TD6zoG0r)c|2JM(9rl-C>~FlIHok%0
z%Qy9Q+tbpkpv>Mt3hnQ?D{W_}`RwO@Eft@)k_>Z4DP!GxAjN6_;WFBNW_;StM<-{f
zy&z?*HBdKA&1+g~+%D`EB|M7k*m#tTu_y+dPJRs`rBp7DMXmBgavt(d9J5XGoEiHN
z7!ID*%;BkFkSfI~UFvKFcF+IN5!=H5e_p@deG^jj#*6uQ%Zq_bcQO!f8BP0Je&jd*
zk5|dPF|5}<r=16UX);xpV{K~9su<<bI36!`R_gKnav^w^=y3_KAFr;*WZX3MH8v1u
zQDxkqv}sA@x;$C;gtiY2D|J6n!#kr&@qjGPKoSX~)xpfId?eW}za%Pu7UdV9P(5_N
zlP}Nt%OW=x?v1OS)7p3LGst4pUku~=)gN`#T}p7ef#K{<oYL-2D{ZCFMc&=YOD<<g
zD#@8)=6kgOTd*_a*L#M-y6ZGO0Tk|(*sJHfVkxDOG9`0f?DWf2p6T2kNz=sg76}Qv
z(t51QFjP$Xcqrn#qPVWE|HI!q<AOXyteMPoxzw3v8;co>bVWW=-E%OUX}T2EybyP$
zgVeD|SO7oc`X#S_#>;OidBdKJa;~ZS6H$eGF4}W9S8G_ooxOC<oi)ajb6r6te=e-!
z=j+Us_vyN)_esOP|3tZ|-3spIYU%ag{PmFSjCI>I9YqMSl>e&x^HNqIqOr@?ry5Sl
zG~8p71lvK=Wp$gnYhZp6B$LI9a<!p2yLBn3UKGyDk(VqgM+51X^i*u*oC~_-OvZbc
z)Jooic$ul9rDm$zh9uh``Js|_2p(S7b78s|79U){rL`&3pkwi^Xa}sAIC#{2$sJLC
zrz}+>yR8l{Na`X5rmw8ftex{D17mBkTgPN0KchS7yAfw2|6);W4zp!S(YSGxn>P0~
z5^ShJw_u!M9xyLgN|i*f1tOi)ScBEhVV)t6h{{XzL4IeDKOa_z08RhkoxdHH$^`<e
zY6*D$v1ktZ7%h5APOXWWJa4+<&RInOP~16gSdGbGT%GrEXbeGFnKDfkL-><PVZMHx
zpv<VST@Fu~NX>T4UDfm95k&}JIwZN(d?pj1wZZ_&q{!!UIF6b_*|Z2&L?*bEa>u;_
z9XWCc&q?;IH_Btx+4#4^%ARtN6y%;lxOb08-1MV+(iM_3`UiuuEp?7DcwSZv5#;L)
z*FPL*lCgN$bS2kAIU*-yym?z(k9XpJ@uHXFCmOkP(&#w~`N}0BRFs`=Bux(jOA^jq
zX^<x1C<&uea&ssiC^!VkXTjah|2)GN7i8&4{Y?2usmqC5nNwHdb8@vP;%K|5$iX34
zM52(nC^T{SSIo}vdnX`_GG9q|HI<n-S9-$O4K+wh-%I9P9dL3bGKohnhD<99FLH~f
zPTLHJhf#IUq@QS5vO&3%b9FKnd68o0cR6J0ZoMof8nIB7VYecaVGV4VXeZ8Ty{w$O
z1C3HtnM<y}{tfo>l&MU{=^pm7<fxzSu7>`&gzMbn=iN%q)tkffqwtAx{&<qqy}H}t
z$mc9dhs%n!Cuy{^1fF=5ln=&b1!V!Qi%<h9LMKa3H0(wAw%AgRhP+ufo+E%O*oJf|
z^33OU#onAd7YDaGIpv8YKyR+QD?&J#lv8mEEPJ-ug=h|GcDL&_jawoSb>%J*Rj?Y>
zJ*x&d&Uus6m3N+qoyNH+DRs`$M8Q#=exl4V{0!?NcDCYDtGmbY@Rs=9$o1O?sSq=N
z8%oE7oHYJuaxAFV5Cqsc%6ba<kmlYTp0jQ)uDWwwRwc1d)0}^RMQ*wvLt&k>UdxLn
z&1fV;+A7p`c~nS9qQdF#?C-636%&I*c_yI+M)&J-qn4OTWWF`tk@ThR1J!H0TLWZa
zmNW}C?{*r6)lK&puUoE5xBCPkjfszyFS?}<eb9wXkVi{G&C+opGOHq8xhO=w(ePxh
z+$ei#QpF7T=oko2qBzXWu^?ySPG{g80*1Z<QpmN#*Wdr=rI;=gvjc6N{F5^**ts~~
z!*Lt$vDAftk!1(m?oXDH1}3|(056uHTc*LQi<H#$hBDe~334**>CilZ6M&}iN|&oN
zK^bR{7q`filfrNz%(q%b<;(1pg<R7!ADGV$Tz~a=pejZL={TWJDJC@zeK<gdiOa|o
zrCvE2Qh^<O$C6+?jpAX+5_%{~CL8$sCz<FJmpZa&w{feV)!iHi8^G#I#vpHdv>T(Q
z@kvJ^2a)rSzmxiq+uv1{JTl(K9N63QM8|3{j*nz8*krGDjr=$nK4x9s%?<S=^S-^v
zadO&4S+z}KKO#{V$5Z^Fp`Fg$L739z<Dq(>_;SN9H`d6}&lEr(5UTWqlA&?J+#wva
z=AJulhOOts0f=4Eue&|5y<3j?Kzr;Ya3(+uQEO2uOxjRWmPKM*$s2X=m^39%LjiH4
zI0v68XE=az8|nz{6Hcy7h<v#br}lCAST*O)dQSYit+JQ%ySv$9>2GDcTDqx{K#D4L
z!kOViksW~1IH@oer6_jojnGGPeJ))Lqws);9$yk6oB|z3<<v?z%LJFEW8sXlTN$T>
zud!qmI_5DHPD@`=A~hIy#*XtI{N{zA>61>7lo-x=26!0rm4(hpik#+rL=RPC?vPJ1
zC2uxnV$uU_Fm=~AcuP&rOK3rp4#WVqWonp%gGHI+a<&$Qrsahq$+_D&@uA`8kKtVC
z?>rw`-Pz<~+3EDT6$h|KTtB~@_HTCL?#}KY4tR9B^NzspsTrUvImEh~N3X6(2duq<
zUF?XG-PKA(`Um;4-X|uaLP#Gk>LfJboXc`gLMI9Flv+S4#MoFPSm2^CZKyn*h|s@<
zY~dAkp7FJ5##8_Oe>@;+_dMX=#}jMjxysM^!NTFV^k^_Y-uhMfjkR?-)YH3e)_S^X
zvb*Zv+<j5@tjDgHzg@KAiM8K|hu38HDbn9mWjr<i$+#%HECJnrU2)dkK{P2@1UV<S
zoy#`Aw(P&MjQ(|3xaIk6wa9E)x?9NSIgqE9Rx-sx|Afx`xd^w#e<m_yJ^ZX*X`ykW
zr;+WVwNosq2SjW4ql2qpjv40h7KNJeRPj={Bu19SuSCTUbMKKKm47+BZ=lxw*hJ5K
z_Z^ZVS$pP>`kAj+r{aHmu;=T^I)$cwBVL=It(oL^g64b=o!SZ3U+kfrix{c8=DCI5
z)=m&Ww5_N-<fCC3&fKn{o<Y<GlDT^YjG5I)9~I3rV!C0zq?FgUUN(JQMY(OdnNZwS
zh<yjd(|-Ac>>Cd5|7dhb?#zDRV73r!nL0f6;=yowDqjhwrcCA)&hTb|)Cm*k4)+m%
zI<Tbvru@pvls>G7F2@u1`b4yk2VL<i)mqRqMc72bm+sb-xzG)Y-hz$)<`)G_Cz~}c
zCeO^g&-OzJYBuPNFE@S~oC4h$WSQoRvVU3SPsskpRMYH#`ic>+<d;Qeq8f3{$wq@O
zWS02OCekbPdvil_zn5GXe;;?-yPw~+#`E^um@k8MdujVa%yWO^DyahYH?BWBK}y>H
zv)_Lzc=X|Jccl6QpSqsUMd$qJ8;?GGSskoSJUp=CCl8<WzdBp<_ohG)&-=6S_=Wsb
zBk8^Z1LLTC_*HSJIAJKoIQP)ZonpDG_0c`ADYZ3DT9hz+?YHG~e^dT+S2jMSk91M<
z=4iB8C?amtq=4xDXt<AjOaAL&xYd7F9o)O3w+?R>C%>SV{jU!Af1XUL{hN;H2dCnh
zv&Ch9<WuU|#-)9=eSKFN5B<&Khs4s*i2S3%i`m_K7p6Ch@0<vCeIyy1xhom{%y&Mm
zkL<Wl?H@cYA6)WZC|v*H|8_d4T|FR+0UeF;*aC*L<&6At<+7>GJ$%z<`EbQ7f%T5Q
z)QVA>dm0bDG}3LxE;>hxIIo_QOG75Tq(^7qvd;&_^eG*Q`k`oI#%7pom6!ddKS3?p
z>e&0XlDJ^7@qL?;KF)geT18QUFQfF_Yf|jrsaq2t+W)B?NBos3JZ!a74^A%=#&qE`
zmY{HQC)Vxf!G#Gq=f52fh^fA5vlgpAeJHg#c*l6x?E3lI2+hBYq2Y+pZ*<=TUrEXf
zcP!aajNPxU)qH=K8253TJO~D~J|iX`uH)797l$N?M|O<PEGpotpfDS!@LUeEXF{GI
zn+f}tb|kb@O5zsI78<peh-wwgpLkaJw@j*jxb@q>R{fO`+k;bT*ExA%JP)rc{zBeM
zM*gm>ud3Sp`6L!!;9&p7KcV#)@_i&H*;@<yu0Q$Z)4{>R9f!@AYN%Le{41tbwR}5w
z&H};0fB2>Zcy)ASu}~S=sSY<b%aK1+x;#-qP#g!L65=#5Pq>;y);~r5QbYTk!9&qg
zGVAG9b=me`df<T%PM<BP+TO*Xqj(!GtJ<gG2-NlwJo}Mg(*QM0Gh^?Ij_3=IR^*W#
z=l7o#z_%0c+w}*sR;hPQtn6LZVgD_I<=xE3x2NLpY;lZbs^9zXer8*3U%&rKf*+tX
z<pcMLbnW3q|2gsqa14M|cZ0ryS`J=i*v&&TBO_*vO21c(w@A7tGi~t2+7j>he`<(N
z7PJ`lG!WlpBQ35|2d6?!oZ6{vX9aU$s7>6zOUrGw8I`@FYF`=j9-MNc!^TD-iiuZ8
z?nN7Yv|>kpVtT7TSF4aw;42{>=>A)FbxnMCt0qH0|BA*%Qc?GG-y-_o-33Lhm(xq4
z`RCk`hpp7V67YqSk1Q##_4fLRN9_B9wU<VH-FkFH4AREY6TY6caf~g366Je<_&M_z
zb^es!Pi_(~q-=y^oke|K){UZMQHu;6-Yi<5CS=mrmu6zGkFu5h%YCIzXNBB~vq+X+
z@~`x9GH=!50x7TLgUa2ilXv;*+LwR6<h{dxf^*d&0<bnycL6y4hdU`fT)}<!+<O@5
z%EP$k9ta-3pa#Dm1pJ^)cf7R25os4s1wyW=B(}IC?Jp^3u@4$o3#WB{Vx}Md-o$P?
zvdgnJQP`*Bv1b%c-bEdr*2{ftL6j0}RnHcd3;RYg-pbwiK?Lw_6o~!T^C9=HFs=_(
z_Xo@51KGc+c`mb0-T5DH9wF?m>C#dRAd;sBqV&q{B%Y`^$<d>W{z#{DAK6`&3lGNe
z8ER3oh3x7GvK@g<Y!jd9`;;bDmA8(z5N$?wvvl&+swZ30bAo{~LCD9ZM`x6BKKn5%
z$QrGI<;n)ysLd?u(wK-GMpcfy0Cj6--+!&sGp96TguCOxD>X71c3%6n3(kJ-g%{R|
zM-W7-x-FEkl$z@ou@F*=LrJ}HPWn0;sU}TPHOqc$#+H2yMK#ji(L`&J40=iZIIw7f
z88-q?Rmo%1z~xeY2;H>ygpM9u^RXmwt;YSI5}F4+?~i=2tj){id|5mhCev!~i7<OS
zs5lSEO0*hOF8}ClPw(X{JRHY9L{wDfpa^N3bMWUFJx;{c7E;F>RW35=HCggWU2Yz?
zCn>-Gxdbmse6i(YOidX_H*0!PnEpmACkn;HsKHpCC~I-jn>3$I>h4k<b)NH)L()%8
z8q?n#PK8pm7RsEB5qCKHbUl9bZvN@Z4Sz!SUOz{@?63dA3-Q$k`Ihc|A)am=j(=tN
zw|3t9O7(|Nmv0a5eP!bH!yo)0pKQH1TFzu%`RJcq;ADPf*9-i&dG33~KaBZ5`Cif9
z;x(Ckm~W;V&&IDmJ$(C5-elU|<hh@`$sc}W<0dcIo2>l5-sFde+c#;wci^9DN&6=M
zOiS)-9!)+R{U8qbruFO5U++E`(6N@LO`rYZFKt6%`0OzMU0HkmW99qX9g0@M2iqMY
zm-6)&z7;k=;?eoh#~mz?N*$dUkTYoi?QFy2m{t4^3kzGpzT!#@rpLeb4@jc@T%4xR
z*Ns1X%t6rV9yj_Am)?W*)xOkz;o={^%#Xh<aZGHyZd}{%@*|thTV5NNUz>h+U2akt
zk`YA1CxTfpCUH1Ue+YcXPX%a{W;TY6>Wvt4d?<fH<;3n#0Y;r5$G}3-u_-Jbb!R(-
zzqirQYoTa@qDJ&T+wiBAkna+UY7xJ9KDw$vq@wZ%uWpAl6CVxk&fZHYp3{1*cd~rt
zXoe#5;cWSQ5M#Za646LeRNmh>onPCj_D+?B|J7wT6s%*cviM@qRDR^PI*$gEF)>Ee
zY{!)soCuqK;`Q(+j4Sow$TcRAVNR*W@jxE|0d%8Wv*BV8MoA`hAh_kep`0Iry!Kgx
zaB{5}eyRLS!~2rh8NtG@4+YnP=zIyA{`vC0I4vuk37LTtz{Jok1!4Sp(|5+h)n2ST
z27A&-XE-hf>@1yxU(UIKjATBQ=+YGCml4N;ymaf+rsO*Hp)luFCL8!yu+OueP_Xa3
zya+u#=WXj-Qn)t;JPE+JZK{#Jzi~X0=|hs33+6AU{f0Xyyer}Zmy)iAIv$4Kn!YJl
z3v=!sA6`SRiftGHaS(ggBu;B+tw0hH7_d*#Q*RbnBUz28v>3Y!8M~3Ba;AJrX{X*%
zkFhJs7nD9FXs50Z&tMNL4cug9A}eOVY;zskI`+Dl5wlZe5W#$Bdd3)6XA3)5!@9fo
z`?ZVo-Z)|{!BUj-J=p#|E+9C(Ao<B6nS-H-5NNcjFjJc@*q61A5xt!26eZCobypw5
zX+76;X$mly69Uh@XgAtbv1&8L%-RHioU!H5l`?TMosJIdPIu2^x8~xY;g$d^t#NGp
zIk(hP1p{Hn3{ug8p{yWKdZ{{IEo_f`nLrl61^%MUxTXg{$Z2<4=iGZEFzW45t|R?~
znM2Ho)6y<tu4KW9a!N0$j6An%Rn|MUnM(;hTUM3T@II3#A@Nf|N@POv918&8{D10y
zA{3Kqw2DEOlr9p?dEPYVdo#9)!!>D+`seq=#U2ZR=TyP3dzd$~cpCvr*QjD1#n5TK
zEtKj5YC*YfxY@G|U6{}nfIAr#3GEWu^4}V-K2PmNj5@icAtoDh9pF^>Dq`IjPh|g0
z8AN?feGQHXp(R?0B4++%JUd^=&omm-&HD4|z#})Y1{^;~O0c$K{I-dou*Twx{;{4U
z4aS~;ml!K9$bbOmDKZyzZ##JVd{FlsUH9s^M?L1zsW;XlCrvCOij_tB(l{*>h`4-0
zugX#|)6w3`-nqbL1Q49yuf*5BPZ<zKGg9qDEOWkvzanIySxy}hC672o_7K8PoqQ_f
zo?w_w_Co?p0e(|=ML8X(a)J*<gRTPyE1fD=n#l7@W?mGNO5IyjW_TVHz6jbFIoknI
zUcak>^6-+I#ONxTJEbb%9EhXA!>ELHP_)skRT(&=ax!-6WdO~3IhC$d0RydfkBnjG
zY>)xi=8OW2sxQ;jW+V3atlipk;zS5w3W~QZ_Igi&z<Ss2dtovT&15W{?R>O}-C~zu
zOsYy+20-U5vKz3M*cSk9X-2y_Z*#<PQMc~M<XBX2%yyY`Q8z&9R-@Aqp;{fB38mvv
zy%sjdo`~zXR43y^juZn`dL{AZ9xv;B=K<-FJLH+a9c_?$$CLp1Bjq|~*0tM(Q&PT5
zi*ks1DYi$LIqWCo(_urq&CEMFE(IBn5|h(z9j7_s$hE8&b{J@JR9`E>hMM(@=t-sB
zyUU_;u3T;m=`X4<1RTK&`LbrGh<iI8dmqqjEe=Y1#tpuD*jOM&yxP!F%?FK^lMSXC
z0h-e&zYIi@8)6)7w|F|!Lb#$=ni)<3lO}Z!pBC-6*jxG*z7=(Ln0UAxd3emCy7DF)
zb+@$Xyb4>_^ItA`l>xVsjyp4*Tx$Kl)_)zl#&=4-bp3P+%De~U)$1PXae@Ui>&=^>
zMZt1Xog&fgkWh;p%BVqmsB*(m4od1IQQgO5koOc=YMOKh!ssaefVbDZ+?c<6v|-ft
zLU>H>b)VgH6L__#IQ|}3`Dx?#NNiQ9m_`QQ`sQdxz8cv%Ky=*9MVO$zoq+l<muOax
z07etDu1G9wlOzcZ$dTPldQn0PlaWi2u0;`m;;|?_Q=48DrT3MysI6Z78GUvu+p4hw
zT<38PUhtgD_dfH_W=Dy1tAO^%p~z`5D0)@d;dh<W67l0;Cg~c&fJXw~G5(Or2KQh!
zvc#L1rXk*a+-sd8lh_~7PfDrn;(!R15U+pnUjac^$L08W7ClqKfyVM>+X1b2V1RDC
zx&#eN-)tdMFlt>u?}1WA3pk@h<Tbrq2N^Y7JP^rt!P+TDWiKIL$jtFz&gH;OKjWH;
z299;ol^^`;j~oz<p=_&@jlVO2t;Uqwkz{G%wE!8L_tQ7~4*&2U+$@rADdSX+VJtYR
z8eF%r5G6k-kNF3n)d?a8IRUhGv^uqqZ9`HZyR(7==vAZLVK=ViJ72sS7sP1rkDnQF
zTixSC)|6DcfMG!VLyRYcY{9`oDR$Ft36qY0_9*0Mx;ZMFL)d#}QRVRSZI4!EL==5#
z#sa;il&Kpr!vscb2TloPCPkM0inBf39NA^T+b#gKdRgCcSLUzO1MFM>(v0-{yj;(m
z=*cNV$+da3CGgIk4DhJyZwD5I;urMBa-i#=bTjhiF4Tg#b<FtRUh7Fi^p(#FH}iyl
zz&|lCzr9Emde0nDx(NUWb?$DQ1xYgdcr$ach{Wf=3y!8|4JT{g^I}#3PaKc76~LDV
z%>nUBWBvXYLwSB+eK~$od}Zgzch{(D7KhVocZud}U@P&ZyU#`6X^>Z?(0f;SS8wL2
z@Y_GwUG92P^nBd^xIglZ-h=YVfa7Rx$~V37Q#7&{?=rpVnwp<))$lU-{y|AU763^1
z_-j4$x->z8&8TLAxv4I3*!K&)u`=sYJ#O-;Vv#a8s0EQ`K|r1a4?ZEY77J`Xuf%ED
z=ty#ANzM8xO%})F(N@u4h?ed#;`Jy4oRi5uwfT^IGW%;gpIEEh4NUr>>3B<=`9$<@
z)Y?5){jcZG?R-G*sXcLc`tb0Ub0=T@vyRO8o8ag_g?CQK8uk~)-eJ?~ftMKgz_~*{
zJ|8v+if>AP@=fH_VyH`9894(MRJToDw7_Wn@utxP#_%p?zePpg`sE0hLboL?M_x|o
z;=L2q_iNM=a8WL7ErfhM`3dM)6N7wm?K=$&xbb{+w>(_ie_Z|htE-~F7fcDr&3|RC
zHhw!GQ_bR>(R0#m9jaE(h?9QnJr(h;p6>M;*r<O+5V|qnrJwixyH#QUNE>{h_lz9=
zp#mNMX!VbYqD^YEcPstno`pNhr*^<RgBn^&foqb8l7cgZ*2L_je?%pO(X>98L<5i$
zQ@cJgH!*YfiiN3WU|W}L)v3cv{Qz|U8C!Qm4?kAE$B!qzyKigXvr7jnM0anUKD@M_
zDyyfH+VVZ+PixSCzwJ9KvC22|*$a<Uc3n^Y_&_ke?9Z*g6hG{@Ub$GSbb&pg`L!mX
z2X?0bmrgvq0<Ia~MAv)>$?=*hI^Aa?ulqF%Go}Q&DtBF%pq@6zQOhm1<V7_)W56?<
zyNL)O>uVh^xSRv4-~zL#DZRb8qn*(QY;n*7OMR9A=Rum(x@Fh*i?TJASEGNoUysdH
zpz<_GbpK4GA2hXXN^TY-wmj4LRCMS5p9$5_G5PRKEmHSC>7S9r*Agmfi-HsKQgvxA
zkX5%ksQq=nQI`IVCO^w&>UNWMxJ5M=4@9nb#DDG;e;Gt`#zIAxo5QKWv(ea0?y3=~
zYbe~HK6GqGms3QoTL^m>xNeIR1gbfhXk+ZuY29(*v3;sF@pt_|&)`&pW6^gWtCY&b
z7>vC8zX5m@<L?8u9-G_$3H{42mY#gNYstS*9jVPQcov<SnCV{f(+qji?UMC}*!9*K
z<;ftg&PoKToI;c^`LZO8*A_A6zg@MN=V;0qS^MN|;((MuK19=8#ZktHV`SBtM}!6-
zCzb8spKAs^OB!F)*JO4Pl#7xVeF-GuiNA~c#%5Z8ox_B8l*XQ+g2Q;^e5e*)D;8Ui
z?tFR6+p@KvRrT6P0D<*kd;|8VcSk?j?as!v5y0m~f3^nb-!Sn(WixSIror8`-y!&y
zw`t-D&|47h=e{ev+4uv1&L-zB>St}@RjrfUjwo>sn?z?_f-hJM;FpN_&@5wJbdU@w
z`)S$={(<a6D@uVM?!On5?p4ByCbr$fQP}?ltsh!h>1&Mbi?2n|Uu@nlu7C7fr=gXb
zxYCVWJo@kf%$?EMZsR^T0bYbmZ<h05o2Wo9`#iu#GNw+Wo6w(}3&_aKTM3ym-DbG}
z(^?B4x{qw+S+oM}AiRh-pcwBD+xBW)U3x>Dp<;w8d!|@>0;+uAnPY_hPk+EOCubTU
z1#Btekfbz)`qpcmS+Xj)a^xoKFXh=b5V=J7ONlIiwOMG=Og{kns6SXv1$TBe!DF*A
z%Mf`d5YorTqKzF^$0Dj0Iz(F>n_284N6@n-j+R+yv<xj>+i!*ptwjU~IT<~5Obm{#
z?EfR-j=Xzc)T-|7G#AKF)llj2eQGqE8YR_uUj6O|@QRE(PH+_P%`F*^X8v5K!&=+R
zOpl(pT@Mad&#3DZRH9jfeW0+rJd152p&h}$n8r7>sIwj4WTkg3YTCz7;Ee?*y8$zT
z=KH7hr?ef#j=iU}!+B4GLsfUxqTa`ysJ5unCw2oCiI>X~1$MPpE&3+BHuN1XuDS{Q
z;u1^MNsg7Rv;Sf%a106kWHjsLfFm2gnO+b@CK<?ktE#w~U|2ekt0F9poU5GxU4GIW
zD`RcwwM5t1s90>6V-7y*4xByiu`;o|?%tGscF9%ZGcJw0_R9R^+6b^Dd7_Ow(#9o+
ztB9M0CEb>rTT4I`1Dtv(yCrd?+0iR=nmIum+;lRpOi05CrxQ%5HbVyl0sxeAtYLvm
zKFJ-9CW`_GA$nso_U@KOan4N$E}CHBn1N5>2ONY%^4X^&3D8->R5ktHgTJ-uKf^6Q
zJoG~RcpK<@A)aa;eeTy!eG0&G;)feB-(UUGU2T}}y>n+Hi}MZNnY4kv;tRD6<nr@>
zxPe@L;s*Tri4FMkhrjU?$mRcZVFUi$KrVN^P`h!HpM*bu^ob4l^G9!DsM8;`)hpWg
z=jP~hhyK$Adx*aQI{yCf?cv~+`1Ri({;lwC`E2~7Pw__nb>P%p?Jli+IBItZ=<=;y
z`bp&S_uI(j%J&9W+V^<<Q|0@wzxb;#+1rHFx@&DI#Hka7((nyfmV+v1-uQ!7Z1rNU
zv%j=oa_w*JH`wGT_2)xNLkz(3D)tYG_y(SN9$fC<Z_C-cZ@d7D-h7qbxXF!Qaice1
z*mwWr%Q)Zr#h=cC=G>C$%-=fPh_Rv#k@%#>$lRK9n^QhnKIYD<cu8q#dfAaEI3jKN
zI`UO0_lV*s4qzJ;a`sm_3}~zgLfDMEIa-aH>f2y0;*=;-9LW@5J~SWKIw$10{3HOF
z$y1OIHl;BYnGap;)Aj1d2VWd2Mt#S3{@&y9?4jsM_4?m^qy&wrgv%z?jMbFE{4k~_
zN2^%y)t*$YVfbW(VNrLRFydiwrL!sYc*`J#85ZTd;w){en-0q@zqg2m*HkV~mpQN;
zS2?-)XwJ)E+?2cuMgfHJgJCpQmCcSlM#a_Mr?z-fu9!q@508a)O9=v~z)0lZUgb9Z
zq6$b@l=wQ=AQjatAOMM33E-JBBL<rTBP@bH8f^!wq#-exvF5}=l)z&JIKt@V_u2Ba
z0TnvRuq1>K<=jXnCO2f6T~LcapoSta-z|-b*81OE-H;jPGkr4z5x_qu<FW_Q$|#AX
zQ%txOjCP?HqKxTtktnP`*rJ#|Rwgj{yxb7m7UBkL%9K-BVh*^aXu77^LEq{?M_i*_
zIZKz`Ik9Qj%`8Zua+8UHJaR7AV0pr9vSR^55Nr+u4+{^w5R8YO&D&e%+<J#iL20cm
zu7sfnF3d;UuX+b&xPvuzB1GW^#FdvDG1uzi<*)qAi!NA_1KrT-k1f(Nv!wjeQ^1V$
zfjS0A*$H_p%Cq6I)(-fQXKA5+%62pt%Ne(59}BLGLa-J=&?Xx@{bEnEOLNdoxNi{<
z$cM-pZ4c^tIKm?4(|3OCr>sSPvU61~_!gsxs}ZEu%r^qH)-zj^_cW$dbIO>WB|_@=
z=tDs<GI<E$JEF?59#J0x;3s@cC$pL|5R5JoC}&+gIJKN4b^nwCqpdRxdv*|6bvl|-
z1pt(U<RgCQiM%&*qSzd}AGT_o%G1*3l0s(ZrcGUyBV#&rT)*_^AXTG?QUdIhl*pPo
z!+h{1EO`!V0fvrdJ=O~xtxmCk{F4rsZw;em`TBO&OPw$rL9jTgkYOwH=MyR}uq8zf
zU{ntHHfJZPlDq!pi!7`rMlv5v98u)WVW^o&-D60FB)Nz&2?&B~R{etWTNZN0UJ|n%
zw9i9?;B2*7pNupE?BqbWI36{qoCnNlSHmhB4A3$B%N1~++;qc<^c;ZkJzsviZ9+PM
zg%C6Q3C-yBl`C$upfb&OODCczc0f2742QVllt#$lqgsH%PaTL5Mrct8q0U6cO{_R#
zr?T_5fLbA}CP*=;yj{=qJExRkk-YcyO-`#bPP-KY8Mf|Yr|=}4u)WaV7{4wreKQTN
zv!ig5a!1yhV{%Oxr1myR1n6x{&Y~+$xTuT;SiDHU!!CJY&dqtOS1*$iAqW^iNFsnB
zoN%-nUi<ytbbo485~)Dy9bj1+1Ip#UY&blUB#@I7423t}?uj$cDDpVy#2`Pb@@2%-
zgZ-7(F$!$Rz=d_XpUAw&58AZK(+Ui6dMON#G6D%HKU?;lF=W*^Owy!p9t>}ujE5>r
zNh|2BAXE(cs4Tg#^1D;)uyt`tMF5JBTM<9|GHf<cQtzN4_KgVqcvY$dChH2oa6;20
zVDj8BP1JDAE%a+h-z+6CEbmC?s6Hl=%m4bP=w`_$o-4&>(Vaq%W~%r##Ls%c7n6P-
z3gns!qI8vf9C{(YXG-KT9a~dmUO~-4iXAFyb=+k$!K5LCddP!O4%@s;)OIaZ9hPL7
zh(R!C7Jy-H?DkhLYrj*4|HC&&<M8}ktqN9a5oB&>fYlPF8Hh=Fj-TQ2erZ5J<W^w(
zQGh_0mTCBIPJuU(=d?VrJgV`zkTv0D?KbV3wiBbe<ZWTi)BCV>jyzMm@?{U;@A);I
zxxZX3zY?93WG2`yl8Q9He)MgQV*`a~q7QaW8%xL-6BgZpRg<SJyu~vu{nC1G*u@Yv
z3$Y=}xC}F?N!7Hf=IO{y7?nvAh6&myd2EvnRbvic2XmWFJX9mxp=|1-Z5IN_9$q(x
z31{p|Zr%EitPFA1btD@T%mD&=OY2Hjw)joD;i_D0XV<<ZoE3!KPc^y7BWf{(p>LcL
z==!zSP6X8Tkp6<dVA3OWi0^{7rje0^r#oHPO2Dg>!{A<aXJQNSXihG67nwY(Em=De
zjYHwKm}|JRK7@WIUe|Q4K&lgeqT%2yBw$`AI-<I-t5%D+zqX6nc>(vkuQnL`>Fqy-
zhs~wtbDA~9$Qt3}nVH8}qSL1C1&PnZlHl1lUdvqo^kO>=nuio!Ud1B=#>+yOG&E;B
zP+~(h2!XW1=d3aU_U*QC(b$kv-TwXJ7lQ5ng@dvd-)35I_ugL(P}2dU_JC5=<id8}
zK$`4{t8ooqR?>Y!-7fBk4vVAeFqNq12NsI?wa8foG5NRVoI)MCV#eg$AsJWKigz}y
z94AeIam8fw<>le0vSI=`JS58(CFPYZC2*OcSUDhG*V)$DsMg33h1cAXmG@{hwv4ki
z(dPHom#3Ormc_}l(ZPcL$e_N0eT|#)vwE;LI5(y<pBKkvJ{r<t{*@2D7Rse9$G`Wn
zTe?!;sU^wbT5IG{I`tldv#>jA!*1q)pYrF1dOms3KhfjEjP-j8LxrB9;<I8&+}3E8
zd;Z(V;F0~VUj}d-lJ`bnX~&~`2jVmG(2%?tw^;$3gQ(Z#NhLCmM9Ez;4CjV)OB*!K
zj~2bmShPKxn}>C)$>)DBxM)njn+4IYKb{36m0Ok%3{G>h9af>aN5{oo%^_j>${$oj
zr`{z`?*4>){`w#P#%eOs=1T%`Rjs+zMg~ha&_SZ=`K}EkHg!C&egVGe8GpJl8_y5j
zi_@Zw8)7QS9_$nQ)n0GEhioYv%L&o=_WOAoyGmLP38ISi1+g+CZ?QNbupo@dbKKXn
zFrvIyKBetNccCY6eBOW$%}EO%LbL?XT7}lqFJ2oyd?2X&QkNL6jf>U^N#yH6Db+ME
z;@Et*Iw(Jw_*-KOeHzP>TuUqk>;wd+(fMwui2fbe_t?^4N3*5%nTJfU>)Yz!o)c>8
zSkkh1;umMTUsES-A@b9ZBT0P?(7775CiK9Pes1uRFk?{|wRCb;|B-~|mjy(8X78u_
zj>?tOGA?I9KH$ssnM*Tdn*pd%>K=b-sO4={o3rI;YrHwTq7KYe|2)Y8ee^-8jf*fi
zM>ZAy)k%QEA=R8(1A&wBNqUvaVesbYoupe#hmAb|KWW_zu5%|bMGY5{WXcEZ0_<@L
z!oQ7TPZOW)fi~9DxMKVi09K9+?KMr9Y3mW7L0DUTZaAnPnjvZyKu-gQKJtvVy;Zx0
z%e+;a2^|A2bhts66<XU?Va#A-UY->2Q?e(aEHbtyNPg++!bnD6?>Vs=IAHh>SK{gf
zQN5H}us|U;5xESw6b$aL0nw7(J!H2c0G?oFmv?vl0g&LLpN^Nh>{Gij^gjt^H+mu%
zv|ttB3r&}5aJm7mwuAFrww5)#u3Y1aV$62YnEr_L*GcYq=obunEH2HAokHY}46X1r
z>kiNzH_EPM`+pOLDT&yROB!y8vIB4fM>a+8eDB-#95nH~e4uySFWJTe#o4F}U^HkD
zO-SFA&W<PAgKl|nB&N67@<_utLjvu`8(<jF{B+IF`4ck$iK6v+!uB&jhropO<sm_A
z2cS^7Om9NPTtybxT^d*(I*f?t;#-O~W|<*B5T(dc)zz}_Xt)JH(V{wxIfTE~*fPp;
zYp?+oR1Y-1R;d-DcYfjRoKaYv-Ennq%tmg<^r%dNRlYH6@;P?{Y@^A@`?E|Oc$b6J
z|3VQLTpTa;37ji%bw95>=XPC8fZl|2Ai9XF+)IOS-rpbvfTxivG3yK6aWaK0$Js_q
zW*sBbpuYuiWGGa9^b2<7ysSgt!y5cP67rjxAxZ`sW#G7@#S6daea>te34B#MZ^_V)
zLX=ApU*rRbpP=i;7mWNW(xJRSvxWg~5!7z?2srCyT$)QlF5FGta2c=rUTI#563Ex{
zB)s?<G|0$NK%08ePeL;5B|zbid|J_+)L;WbE5Q&mS+<vnNDWLiNEU@mofXQ}X-utW
zmuk;ws*UK9Ag##mf`0bWE!ntp?h5S9(nR%Tn5Pa>WkuP_Cv!lO<piEW%}1KSS{q-R
zsrdlgp3Q;cP(=)`ZEK?EZZ-IA<L_DG7`1}D*azNvPV|!`!8={}K9KzVAh)fn`YifA
zIA<9d&Iru{Td{yAb#xfL@a37Z5XYmHegvmA)4-;y+eIwGev;k!hfRNx1c!cTskg5l
z)9-!kr|(;{RM{`aj$9jg0Sh6>K5hWLS%04_XZ;CmnLCbly9|3N#opH(o4G8O3#Bvu
z^IfH-p*i6D60AwEc=BK$O?<HY6!2&?SY~Vs2*j?3W`Zc|!Z^*wC#H9K?8+MF#tiT_
z9kZF2uSF>LK*-Ij#?5Q@wBA(uw02%Pr6*Ngf7@0?zfO4j;Pv@`S4W+|H9F^#GRF;y
zGGLc81BpV9T(6?(`SsYE6@fWya>lQsTpp9h%0imJp=tOq8{h=^4s^r?=ZZ-Xm7+#D
zHIQHSNkH{714_CG)|O6JJqU}-ei6+^Tk7I8%G_#_8x}MA>XJL4JL=cx{%Z2#NXKY3
zhJ74B<gJ1Pz>u6Dwg+Ku4JKsO)k)fI#;!#8^akQMXhF$No-8vLTM;ld2E!`*1xFMo
zopSq|eb60c+G36yM98F$LGER$9C!jRPN~tRRNBKa=ME6q(2gSb?9=rr6Y@`C)ApBN
z``fO``0s({aGk-D1fqMYO`3cQ=-9deI=;y*yz5AtEqR0J_=7lV<9rX@-oJtKJ=Dhe
zR-jGpdCOg%YvX*cM{TC#<_L=726oARZRm0XE&N!!B^zAJ4Ycs*egXjfFQSF^!!+eb
z|M^W|aK5D}Z`|a~4q39~=L$FIpRgote;`e6V5t23)hE1$bK`|Nj{a%Cpu?kv^4idw
z>(-Lnc(s3R-~DG^kRxAv@c;T}e)<35?Kd8H?OnA+Kxtt}Nn~@d8+Za3(<UZ#AZbD_
zN_rZeE_`xLC4t6$oS4$QyhE-=$BMFE4ll`uUQ$UNTmz$5EsA3j`vc2Hm`EqZ{1XZR
zB6DsC=1A7<9PyCwiXa!_I#EW&3kXjE*ECXT&V&jElYdX<mTmDqo+Mj<W)-W>Tk=$w
zVo9ztJiQ=-%c>40u)U3zU=$PzP7F_jF~u@5SWZ~)O;<6x=?K(FV+G7h)PD@_mY3E#
zp79c*t##aRfu!Qf5tSpw3nUHgT>GE@-ZGLLy&7O#K@4(yd?D#6s1;NKq$!`I9I63_
z!i_LXUcHpHhI+jmxhSx%XqCpEVhm<2Zl?Sy{Dtp^9Dv6lc447KZPN@GN94Q$0G}FE
z?%t*cGxDA9O*y@8z!Q)T`kOQH%>WcRekS8a-R+Gh47a!TpEJrkSdsvXn3r|8<YDTB
zcJldQ)uI{>wjOUNOjcaG`~-l3<mGUi<K=kpABYDq$RI;y<<WkEi=@-#Iw(tyh4d0^
zFWVNtLZAU&%CQDNrl=KKK5Ku>xgj6Su?4m-<$WD7%G&v@ZO$=2>7ji&ccTj^E*5bG
z#Hcgx901K&Mja4pZ0kTrg|m=gz44rFJOzwC=AJS)r38XS6A63|9R(DT<HNQ+47TzH
zjhjBMod@sm#BfZcd}`EWZuS$i9d)0dU^-ZyC}ts(=R0eIF5%j+V=`nW3g-M77d8ZW
zfg}4}E{;01Q$G|w<4I5ghp>9OLhPs@K~sGm1~7K3L!PN^t`^NHQ&$~IK$pr`6BCYw
z;wrtYoNNDb*tXcNWB#G=(0>a6*&i!G9a@ZKnmQJeVM1aH9oYG5b=qOA^GO5nHl=vW
z0T5+ytn@ezqk=fKml*?(h5v!Kr8`a2HBJwBi*YhFvj8Ac@<|94z(^%Yh67uL`DY3e
zt0&n}OY9tSY<W&p_p~-PP?7fsT;8u6)$nX9lbq>;@TQO)5=elcfY2)2GUuB47GhDV
z`tcrc8Wu8bOiZb>3Hi~k6P5x96Gj2=H=A|^_$g%9{x%P!fl#U(Lc>Gq?q~y%fMA7~
zI>{W8VL!~rX#k`v=h{;%0b{ovk`T)fe+Dc))&+R4eU9Y}A~Ysx3y<wWJqDftYH^Oy
zD8s@}IsNvz?c$8~|6EL#69w`#5Avbxm5N9Ad4=sTzO;AG^FNid*b_GgQsT}Ti|xWr
zu`p}k=iE$;t1;yO2RP&{u}$Sl{4jNbOjik$2F5{ZtiXcuh5(BtGHbg$kU(C(2*ve^
z>(XF){OknRet6Yl8Z@-M*z7kJC%4b%ZRXfM!7dpaj?NFXgBRVfzsNC+Oc}+OcsEJ7
zj?dAjwxICqj`Y=6cjJJ>W6!I`=s~<fP)H4Eiw;X7sHN-lAQ`^1-~(}r+z<nsA-0wS
zp#3Beucgn55X5pcYI(FLQ{H%atAdnJG?P|@?bYqD4bbJfSwiDhi*!2riyg4O=#AmQ
zZJAE_Y>Ie;Kw{_Gy-v~-7SH09WA(Z0B6g_x#)rPm&1{eC@9Y)r{f7T|gBkSfFRy*(
zm+YjX_uw=^#Cc5nTKmb~*asC#9FUj9VM}fAqa}N%wiGyubqR}7G8<MTFoRfG%vgiD
zENQ+lea<#J(k#0$3rK$Lw*S2zgX7p+xMH-8hT9uj^w$c5AIP-bm=M_jBoecW^^oHN
zWhb5OtYqcizL-yzf!&@J52VC758g)76W$=*5Qv=f)xY){pkI>mSp31ik@6Rg`Thd<
zy1&qxmrYycfV0k+`Lyu|umsaZN(ZOiE_72DtDr3kc4%dL)mr9e`_VMy#-7fPka+DT
z5QRGIy?)=I{S@=XSLO^zk7oJ7D)&p*EZk^wMYL1w1FH)AHl5=JEO1~^`;C3I-{o1%
zC*RXidT(2x&_h}I-m`0+U9^<?qJ|TU|5^463nkL-`Bg-6VO}mACWX?3IR;g4-uFLQ
zlj%MF?0k=Csww}d&v_ekt@%BQ?6y5?J|oU3)fIN9RN;zIK+BmE+231_Vw?x$jvQcg
z`C`D^?J+VWNFp?7FP3-NP<s(_YFdY|HvS=T4nE!?eN|n>+15CuzyAm2k~?ZFTd+Gd
z&tWFTd@yQAg>8J_hcztb?~u1a&#StA&zkHV>X~oFso6D~l2#@?@q47~LSTB`j9DX-
z7%jCs3BwSE+hwLa%`x|TQ%gx5sn0alAkZTVv1bE0sMO|#%_)`9<OGNtHBAqV3+FVX
zm-*?w0vSvTj>=zu=j{L8-q`@jaa0F*X1y{e<Dc90N<JO7G_zWnll&`TKtPChS1bFl
z1v(kWcDV?W45@_TM^5-L0V>`(kL<N9EFIX2iT_T*B*Ko7oFXZR4R<mIhX9sr<k%2{
zB_&X%z|lxmNx29?`CiY=?(FXD|D2J~wN5)d{qy?u>(@Q6U%&1i7kh(b>U5o_Xtr$G
zIwg8BJeH`y+#geIKhBBCLSXYTc6VZX=l*9X<8MK%U$kK(Vp}I36(qp}$&7q`f+-|b
zFu?*>VYZF%IR`#<+Tbc{*5UzcRwBVHG<9pjJdk+06ibZ^opDF%oZQGj>iUfXKU%dt
zVcq$T#Ly~KUx{H(hT~#_Jt&s05qrB^^Q#h*$<yQKtilQ^m0X7Y!)89rnII_8&E(`@
zW+7)_E=j*0ySerG<aK6#XYyxIZ(HK>Ip%pbHb<tFVP%n#shE(t^{g}-=Q8HP{iX>}
z)GX$}r3*7F`p(UvK|MD&xa|!n3=SQByT)PD1J@wh%}VTtd$EEMy4rWnR2za5Hk!Mw
z45TOtQVgH3!>-7ZU3v+_WH1t3wf?P)rI>j!!QZ|>iq2@vbQ$#3Za&#6iD?%j3-o1Z
z7)STQE2lf_c>71;XLF579JS0Wh)tYvGPX*bJg;LlzDg{wP)lIbw0U6GHQZcaY1W;X
zEuqvM(3Ii|1X=ZEuc{@3QcfQfvpBivkgizV1<>qeOE}~-zXXwhf-%NM$FtVtbI(LN
zX%^`%n(UC2er*a$b0uOf*3E;vunbKP{)d_4cWc5lCmx7jk8PT5v!?<ab6EaiKFFMu
z5`|=9PKZC5%rdpd+{#HLSP-D`G1x<I!DX%N_>?0dq0}UpjciA=r<r@uoG^INE~C(Y
zATthHhR#`d8t4{vQ93Z5Ld!%9^@-qW&>%w-kDe&oofBX)Qo^_n?HxKCWQG*xXXuKD
zXR>v7n49v@s39qG-XwYxJ}8W|(#T@gCg5eve;@;eVyG8cJ%MJB>0I5gbOv*c7RkoW
zNo4bB9kNI(n!;n_oMoL%3wa0g+~Ao$_#EG`+Y;Fv=6R@WO4`U5QZi>B)KM)BaELy;
zhl_Mf&QqaTv3}*#q+<yP5+dM;!v-!kl17D<O=1F_rX&o^89@}&Aa;O@fx-(NB?{GX
z=%$&RMw#SOZ7$ML=v?s283UAA;;QIt<RiuLF~h@*X^?0xdN@<RgZgqm3@6B}r<M3%
zP;v?;O2Rc1Z^03<2lyss=F^jRCSe~7*5qp@41uYXFv@(^&p5#ojuQNYSu*A%AJkkj
zIVy%;2hKQIXl*6-l&HClegYIq>&Nmi2ra*BJ>MCW5b!78Y`vd}!4O2y5)0#e$amRb
zv<8-8_|Y@k2r{?@Ghm&yAf|l?6UU6nHwy%0=WH@_(NYaQSs2fv#D9iev^qkWh5_rg
z^otu#K~zNi#a?VF&#{Hr=<9oi2Sjc_BB2<zJaCE*w{PdE`W}(XVFeEAp@V3tK~^iZ
zg>m|jxk~^c!Dz^~NQy(eEwuNWu<#1Wlk1~>%%O|Vi)~SRSQ%im2^2`FAsIw8EWw6#
zEY?^rkmU<WqA6Q3CYWq<?YGR_*fJTCF(;#SM9`JGFBsKFmJF#O7qhjIw6^Cu)-f_D
zZPb`d2>s)x`J^-5`b#{?X0x9mn?Ll)2Lp;4(XoUmYHCcWl!oQq-X>62If9Xx=z2uM
z;_7MC_SRO)5#OlG)35}90PSos>iSw)!}1R7)Iv2Zt%0<mrtyK)T87<>W!TUE#89Fr
zttn15zIc>8B%X>xge~fpa6uE7T6ys)DjM#pxc+$A4|7Q|<@bOmEcD2R6H7%=JKC1E
z9?oR!w$VKxE%a$)a5)=#G|PaQn7f~esflUohAcX#NqQj@Z&?l9Xc9^}MMNVaHHznF
zlEdei{%VG0Nfu-`W?u&9HXi!?5)DHk#B1^-IYghlbF5Woy0a0PBZ-8k=l~dm8)nZr
zMk)HsO#&Ea@FsITP0J>kuBi|a)tTX`b?bG9XENE5YcB0E@-dqgeF~{(-lQAoIy9*f
zQ_R<ys4HY&5}*VopHI3V)dFpOjX6+6A49frlhUwkuteZRI3bey7$TiIPYhD2(R4{0
zAC-xw1g47;)5zttoEs(AE8xq^zuYi><<s*0W_&o2)wTTFR&P$2ma{aqF}3V;b9C+c
zyD|&z%;fhiwUSq4zJF0^`B?hlLbmjQT<){OgMH^MetmwGefQW4sq4~bu`qO1=^a;G
zu{>=b7_{<NW;R|_N|`UeKfC>Nv*SM)o;$kWiN$9xoweDzCw}%F^Dia!hB^5emuL1Z
z-Or-H-qDYh3Nse&EnSztYj*0c{M^#yoE1wF%bwZw(&yqsi!<l$zh!jh^4!_Le!39b
zGYagX52R9e-F2&eUg2`9xGR%h{<VQ$Jf1py&bygiC;oQtXndz-K0bQMzub}CmCid{
zun^mvUp728v~b3xZ8^!@ij&Zm?9V?x8sD5qXWC9zntA29*A?~+Sh3~zTsE5eL1y8M
z;y~(^WbU2Y3)!Wq#QFAl!`d7(f1SNzX6oE@eC5EdA#LGBcIwv8<+T-W8DPcqJtt-V
zEU`~Y-hJexMvc~SxO4R?`7DT|xtT#@vITqLCRNujh*vppBq-|4<dv8p4Cc9_^c=<M
z2ni}|spfqApS)PWTX-1>=&}-q(vDxkl-f<=2IxzkgLPeJsLraXN6`(G>;JBQ29Z>O
z$;OrTOta`x0+??FUrIuGaR)Gfs+>$OfQi?GBQ-42nb<@u-4hL$6lsiZH3zguKLmC_
zu=_cd7Tm~!S*)eAgsO-_ZJ7E=40V>82rMhcfQUy%8rR`*{e+TWlyJ1Ols7bF9De0x
z!YrzR4heY5(fctFlZtsT46+nm8VG3h-;Z>Gs<MVu@-$VzYW48gr(I|urwQp831p1$
z0+~TWYaf;x7$j2FUXlQ|?Dxte)cN%oFB0M5Itk4@P?npEvIxO1Fg%5+dXs<vqo^Vv
zID?Pu`(FL<sbV(<xv4zlK#hwZKt&g0ZsNeo5Ev}63pg2YB@T!R710a{{xaU7>5@On
zr`jZ9kOTEg&(cOMQJZLr3c`beC%I{=ep*qiSN&LdqB|oy*3e3E20TD3Rv`+|mLNtD
zmp&!a#dJEa-?;izDugfuJBdiN#xmF_tc%)$Zxltjbb({Qz9{)s{RM^xN}ga-R3TEj
zqP5_h=IFoy?fN+gT7o2y6fjG2NPw^lFIWKZ0w;p5Jot6vRK3-k7pRI>0fz3ZTI&|c
zH$sBcC!M~e%0Vv1((NW}6eNw?n_NIb1&AYKh0pCOzxt7+=rmDZp7CZOlZB<Bpah~t
zSLvmIczQ1vpmacd*%I=#PHGo@uQ18xB{O0|m-LZeVRK0uQPKmK9w<qKE~+~zIFiH7
zs5r(&pF9w^C_|O39(c4tJxk{<6Uw>bVS`~r-YrT{6c%VcpGY~Xr%RZEEA=zHG1CXC
zg32)EOKV#BL%+U5p$XTCg)d_VwwmPT52(}xH7G-v$|e|k-9`<T6<AU&ic`*`KS9Rf
zwSR8RwCs(HgmRASW~3GlT0jy>pm0>>&=N)hz5nc?#8TQ0)vgW4(pNlsP%x{SYN_QW
z4D2-nVTm3kt&9f*WE}u45**BkB3vq$A<yTw4E@Z*@4H&N5WSp?n!^J_V*^Pn&gIz2
zwbrd5fDRsRmGKU?vVqRpmas0h6r~V9QojoYKL2Mg<tZ`zsI?N)v`qd}OAC)$B#<mZ
zAF-BaOJvbBM-Sis(Q!*Gn>5=hGT~ru&_^FclOqrQXgG{;-8dEBN5z7Fs_UcX5euoB
zKgBua)YQGW#N^&eQ=fDA+Xu03z>Yy@>CeEBV=O(}Vw2#xYuTN{99P?YtG;48%lbE&
zxxQOaVkEhZMARgr;@M;^>r1Xri;71dPh37QX^W`>cL3N-?v;EuD2k)4i!CjaXJQsi
z!?9Z=hI+-ViA0)N9cN~VUWYl_BX{U4=uK=eTr8XU(%O<8pM4GUQ~uWXfh{?dtW0}g
zfkSx~<I)~3_rM;*V4s!f4N66DCj&iQPK!!#OcRqta&pHXF)k0P7<F}`8wJ(eVo>J*
zQttTH7RAQX_g<x;02-8uZyz+V#;G}b3~sSBNA~P-8|^-Tl4G-k(ROT$lVjOzgYEJb
zrE{trB^PyrUzFoQEl}kJHItwOJJMm`B2v?&f-b5uL!l4Tq8~`#xb0+v3F=76W~vR<
z`-&KFQDH?A%Yvf~Hs=v7wn9(<!(dC;fNBFrjU$>Wn5rpKDh(I0GU`fh!BY`Q-WH`n
zX)w1nz3DkjHl*J2KY3fi79L^KAML=4CMS!@cp^LCSff&HO5<Ash)%~Z_28GzB9(@^
z_`EQJi<BZUlqkJYrQlaSuGruhhi`v^L~KNrn^S;VRAoaaDFG@#ed?%jT>@PRD+%~Q
zeOKH@Cq_yZGE1971+^+6EliLM32w1&lY0#`s*f)j)SZw1fUJyWa<P?s-vuIQWWfTP
z9ce*!pfDt0HUj_I$|oSD3Q8&z1>rc|2I2}9?q8AGf~3@+U^fuJ^L5!Z`PqBbiY;id
zr;IoZ%;HFFw(xjyKmYlIIdZ5uSS8C-JURxT$hoT0zR9e00_?jvPb#*)0f%GBsGBr>
ziZVn20t*rYX6(CWhlaNDzfYu+GDM4Fg#jE(nK&c+?B`h=oGtc&GKEAeK)Oo}39T1q
z1Py>ln+vxB7o&0NDH@;Tq)h<QhtyKO<ZK6&Og3mJ{R(?-sCRnzn_jy`ELt!Kuo$t#
zDh5_q7`HV88y%MA(8EAej{RcHx8|dR>l0!Cf^wy$O+iYkOuf)2A<&CrN5w&6!X!pO
z+HjUa3M-nSbW%IGduH8EJ8WMr;)JkQ0=wH9pAh!dT<8`#|Aeq(3`mH@%gXJij0$%~
z;$D0tIM?%*U0uilWlDQRS=#+S?PKWX)0>T>^RQ)G3k)PZS;;gOa4cjqSt>V#GuKFn
z@HyRgc8VRD45{=WMhj#fOU53A0Q#bcU`iM%#>5sRdFcPXE*WJ`nd-kwItPIGFv~|D
zCwo+I2KiM1_=~#8$-?o{;fWGiL*Pp{<tbyVj!Gn%Vgj{0bs{p8*c7m%i|Lt;EMUo6
zv=kx&w-m(X1iTBR0-Kw}Cp~Er64Ha1aH;`JQV4v&izI?i-ecLmcU>Yr*Gc-;uBdA{
zMphoK^F5FRx8nes9ydr;&`Z?#p^*2Zsf6!^R57MD&T~8b0+jeziEiKn9uuB;Ia387
z2o7o5zQ;~-*GXw%zDcyWeUloTs1sujjgwYXDq}CrW0ngmk`|V*goFw-yKW>>l4IrI
zJUc=05}_h(VL5T~VQWU-GP)|Y3)1yoJaMW!$8mW|<{7|r$2Ca-9=y0|y`sGr9;BpN
z@+6t-JkJH&Wk;7dMsaaWgVd8B$X?|#!8cVquT~-vxQ=thxJ~#h#R7g<+fNr7zlKRo
zJlHh->ASR1RX=d2$CL|e8?Yp-<Z>STQ$ME=r4r$XhCT}tS`_NJrV8amX>HzPCzRhh
z@D$wvMJj~+Z-~yt&+T0PjPGsxsSpgLF4Iq2_bI<U1pi8SAaTVTHp;r3tkS>}`#ut@
zW1~v`CO(hl6u~{e#!T+bzipDIMU+%1=$tM0RVr96BbcIr-yerfX@mfYRzFatU8Q*%
zzz7C=jjK3WCU-K^^W&W@uNTSOdo6qX=*CY2{T8vX3jdhZ!!&dh&&_-5sU`6ib!i<W
z8$Tlane&3Pap7nMmQS7c=fx$ocX3#1sgI$LFCLRFgtNIxmfdG)7uu6HUo!>^;<SD<
zkC3URY}&HE6>4@5SWrn^nokXB*>oIn>_WRp49oe*?_}aI+PR6r6Ie)fr*Y++<LQKP
z=&HvJ<YDllGW;RmhS$RnT~0lG=hlZDGA$GFxlE+-^u$ZAQS%9}m0M7Wo05H?3I$0n
zL%&ejhsr@5iw=MChN7w36z*<4qSQc@3}EZec*=mcrL+3|hd9xNDS{$G1(()704hN4
zG)kriiky;hJk8(AE1?SYp(Y(VmuBkoZg`oYf%C~PNQ+6CtqIVu#7fphfAPZ^8x=qy
zcozOrOSKx@C0}QSH>{;*DKhKv<QyWKB(=fL1po~eJ@Zf>GY^;^eiR#DtakGt&@M1I
z4u*CY4&=+qN;bbTt?|k*V#eWbmbyk3_#P^*D3w|&j4g8`4?eY@ce;K|Oi$(&UX`WZ
z!12ZI!Zl01pL%aYZmWyPLi1+M`SP>PqFcmCZ!!Gu329%v^VE_72jNsNtT4X{Q$PLy
z#pYmn9~t(d+@5C{NUx}EaWWQb#^V^uKfO)KbOizhqNMaDB9g8=1yL{A3}E@@?^18-
zNAjS+RZ40vBX)xq+<T%{sw4{Wxflf^1R<|xVxg-FraFR4F{x`4e={?XxP>=Izg7!f
zq?6TeA8z0?xBFUEUJF2ev{1*z#qxq&biEgC&zCyE4hjO$gCu~w>hkcMbMY;{SDr!-
zaYF2p^6@j|dn!*^Az}_F&X!?M$tgB(!WZe)AB;;(M{bQ@UjPQ#g5qC%vI<-Ud82L0
z8s!RWX9o%B6W3>FK{?nJ<Xx(T!}P#+l3H+7P<OmI!w>K1S*~v|*J>-?ex-sL#qS|n
z4tD<edu4ym9<G+`1x9s~Zu+5XmC_YN2v-HodCQx+g5#6R=K&YUyaQFt))izw6RY~&
zw`Mh3fLu9-x+NmlHD-!yp<Fd~_y4j7<_KxeV%r@%Ko7S=fmjuHXe<BoRKi+J2hxGr
zz$DdcID?Ri3#|16%q^}c)lV)~e~EKBx^*0r$ofOTIg39Nc<a$i7dE;ftSVOU0=<A+
z{my{Q5D0I}JLNTP3yXFV(N$>k?&Nxg65%E_GV{@>p8`0uFns6{IPi<QtX|;pmRj5r
zcQ1|I+$(UwJ{<GaF9nP_#fGw>F=y2#Rp0utu^nayCX`bSB)I*zZWD2X3rflo{;%HH
zeRqTGRn9r<A>O4mJXf^_;RkxpT+Msk>zbbxVT|^j@MuG~`fe2UDmDunws!8?W}|dF
zU+(-Xm!+SDy47cf0SnV5ma|J&a-CEvKyU=nr{?={y+6a{scunAZ~8{t%H9gK!X|dq
ztiSJq8%}Pwh82v1GITJv!y0W=&UXIo^HIUlwD30Q4!&4$j&_%|E>~8+;J&sSpe}c9
zfM6Dxi<)FdD`G~o5w9bpQ@g(rHVAbDqnx;FxxEY_;E5WuVq`Q+yu3k%UZtsTTQpZT
z``u(&w}~~(h+Nd2Eiyh#IS0NQQ5^wuG!Fyv%?=e=!=>a7lCC!ODFr@t(t7IPt+8W5
zA@AL7s1EmTaJOL;mP=D?FO)s>!UrSmY^A86^*{ZU$VO?-7-=L~bRh{jiTk>#q*0dF
zgSnlbekAzX!f!T@cfRsp%@YJ;vn`Y&&d}+><h}Wi=3%(Engwz<=CVMdcD>USYnM`f
zx@n5}lxX+qQmg~HqLZZaKHh_VxuyowJ*$QwEnlHnMd8shwV$9$i{uBgEIabQ<(Hm4
zFkPWzAfn=`cZ5DtAKD<KK&jk|7biMbvoKfAvGV<$Xfs>_i<Zig8rl4>#?!g!<7LpT
zJOz*{2newzaQ{o4t*U$*I-38fYO3v#?gFq2s-jDC?%q%Zz4eRiL$ei<<+Kb5p4<83
zwl#Z_1MF~u4U$oLky-_+pLH8ftGu+~t0sL-h8NH8LbX9fLxJx6bqC8+ZZ)NT)lKOm
znAJB8b-pH9@Uz!Gcf7lWSXY~&$$J;0ZlR*Htp)tH_tb_od=J(xv<0+Bw>8Wh76CwS
ztyS=In<S9#25<L4AgGB~vfEyK$QYZt;ET$9s0oBXln<bKDY%lr$^2{OrIpX68=z$O
zVkqHK7h9)wH04p0bK&Mf+Sd8)v&GP%ISf^XIQe5c2i897Qi^OUUe_A^hn{?64?49!
z`dFr5T~Syb&s<vAoF6GIk1y*h$(pdOEx)pmEUqeO7~)n;YA0z*wTOP`$rr+q4h<Ut
zzWZOxUQ?hA)q*qdtL$CftP|g9pB*s56(Bs;Ujxxq6NW>*@rId3yM)JDwt}qJ6GEY;
zoNw(8t#4?cYcVW1He%jO=Y?hr4RoPN6b%yQoZpnU9fU=PgemfcgcIca!)GM6XGL46
zK-}Y6dC_avaM=5=o;t)+E6+RSm{7ijTEnj1=w7Y&ZSR7<MyFhNvTU#J#Ip~gg)1+X
z-}YQMONE7ojF?r)Qk$;QI~tCwa@W4F_pekN*6=+igSxPi+ui){5P^Pg?mzU@B@MIJ
zMF=>7<sRLu1lZ~{{eAb|RvpspP4H15B~bvmGIrX;Jsn6oH6NN>6-b50ZO=4ACp4~%
zUu~@O>7UmIHF>8cq=J4W3u35S?RIw}_p7=UxPaVNKmhAb0fHcJ{JJ;B1OprSgW{5i
z>n_|t>WL4ZqU88MP&2Po&+cb;s5k-cGn@+GXZPL?u#-$d41FN}^XeykUmMSyCXB+7
z@!U)qp4|EF!M0b=xkyf9)){QhY@xPokKEg#nnd`d5RRPYEL+kbCL}me!*F<KEepxj
zGRWuS>V(c$zfv90@~uA(>FUVkWjlCgaGP@rShT7#FZYwxL*2CZgh+>Bzoed@Ou>wH
zJ43d>g{q2X(wsT(JhuKi67E>h!N94;CT4X!3+}mY0=e2b-@o0LS*jx%zqw4TdPW_;
z?E3?>4Bgtnj^t#+oQVIITv<?i<|b_pr0cU~kv<o1u+eVf58LmAYJANpiMnC^RzBap
zDx?fgL92+tLEs0MaoBn=pou@r1cLg@!`&tq+$>kg=j{DW<)wvBbsv73!Q1(!_PMIf
zD!0I@5}osBWA0NT!s)pCM<>Gw9WJ^TQbTG6wU8+vR<dya$P<l#IA`1p?@rykVoj-0
z$!$$#XhT(h`dqyg?!-4=drS!b$HvNgPF-?c`K8^$-NA=+BCKGfv}F^Q3B=Wop3Y+r
zv_BTZ%FW%&f7m=e5G#megF^tkR_&7iesgtz_m*rQVaegab=LYP7y3XAxAcPl-u^R%
zfxu5x@>)@}eHek1&f7V@3MV6h=hEs~+gN^VlP6b8ylrk%0k=`+Y|d{0n<NPC9(^u;
z;MBUNX#}HDcv<Pc@3J2DN7X>@Lfxz&B>Wcl=<U^W$6s}!@~=V3e-+e5{g)n}(>Al6
z6ENbXeWTJbJIAFeN7R<7M=xf@NNASj%hrEr_pxX+t1kIjH>Z;Y;wo0Ddzl_o>PXTm
z0Fucd-<GWFet$bi+N0WjQa-ctKU{Ag!Tz~sz>kA1ZY{5sEbrJ0(c0TTZpB;e$MZFc
zN*Le_i%yjGEpU95Y-U?v5f&Zs2Ry8Z?!u-K>y&QC1I4oXhsQdlOXKv%1I3z{*f%Cj
z!<gTDiY27#AAYzY0Xm5gnOfU3J2JsE(f`QRI$~B-Cs8!r?v~Y)6B}K{O(%73l(t(P
zLMXflx$yWIP#OxU9Z2HgNvC>K+mvEHty!P_{97B}`py~Hp<S?>z@u{vNH9z%9=)@h
z3f1Sy>YS=^+w%H|ZbKp*>W&RbKz)GQq?XeBn6-(WjazDix__T4`gc-Ikt4EopJL~h
zt=(6vHYe4LOv8En>=Uo0V%P6S=g3HPj!MLQg>N*v9ytcddEudG)ab$i(??GT736@2
z$c7Z{&37x9k^D^6klr(LAU36<?vw(bx|1iI<KmpS9+l|Pbv5^#xSpBW1prHzA^|01
z{+@|m=OQwH#R;&TyF1_9*Qh2(<yTUWohrmcBJIuHxVHm4;TA<rRV|gA(W30;(K~(|
zJSw_*+E%esRm)c8wv3-ftR;zR5=>L9h9E6pqo!E)Rnnqs#-aatsb%fjPH;4fu5DMM
zRl=y-x>b2?$AcJrGi~Hjb6*YSInzciYpqw&$fa$LZI$q7?rN=YZ$G|n)Ex5ic4Kbs
z6kaBGB<ASI=YRJdfXSfZyR_%&!XjOB)}H5s>HS$pv>renr))M&u@)4V=CKw8s*65u
zD2A@Gn}e89@Pr>C)A%mOqxtOSy7uoj;J6uqr&Py%>;j**ayibeTo^cxhcO_bIa}`S
zc95*k7v1L;jronKna!@;sV}`*$WuRS7TZ}|bhT7W*1Ou=N8j0Y#P|08q?VB_l1-bq
zble`l_oI(m6N}K=TgK~X7*^Su?fzIqE3ve^Y-d7g@v7LNALSbKXl#(s0Ub9NHi@>2
zX<EoRC!zZ@J4kx$?h`#`&UgHs9`VxgH>XjC)Vet{qw2U3Y!odY+5x_ab>ELSLc8Pe
zp1-+4%$)oGx?=>wGw`K!uH6+L*Li4CbFTX1&a;K)Ky=-6NmM2qj9eeQBea;V0;7}C
z4P9IJY?bv>ZzB7S4h~XoRrQ`(Hc&un&+Mq$^7xoNAKkaI1zNUyuj2Hm4-4rYoj^{J
z(w!}l4U3%Sa@8(5_F`I%K0WUbuvt4^J~hX#s(b1T(WkFKeC*raN$%T{b2rN2>x=g1
zUb#Jg*@4kR1NJ)J*)AHHV13+Qf!I!0tw|G+kSM2#YudUes)WRvqTJWEO=!-!Cp3SD
zfrzfS<irz4qhJTsoGqQ6rrm@95jCbNLFDRwE}x0U9XYGBE1;T`di)%~(1Zw`MX9!o
zswtgswtu@$D>So*wv4q((|)|Lzh$+bzG=$T!9@Efe>a6hq?)9PgcOBKJoH7)<{qS1
zNlu?wc~Z7d-HH?i^6M7Q)Z`AQNSt%+S=wk+(6aiG_x43)r^&bQTd%3I)9k6jkG?^3
zFQ)1VikErEv$`$Ndexqzt_sn~Z`wb#Q-Nt|J^wq^sgFiv$qetTeqZP%n7OW)eBOhn
z^*pS&!Xm{d?j5W~qC1>i82c8qmWr!OtABIlYmpbn+CRv>9*i3z9amgZyYw$zpZ`1L
zd%Ac!pZIchF5fb}I<)zlTThnzoG%a7jm3rfywz6k19J5esemGjhE?w3FLw1g4{!LD
zzdT7D5bOR_l@ojkK{y!g`&UoYZEX!N*3Y2ULsb%LTGt<MzcwVWlC@o*+Zk@$A8R*5
z%XAT{>a#KD{OBY{)4A#wW$cylL;0->kMm#$24!6H)5xi{G($hXG8Ea3lC~S}{A6*v
zNn58=v(37G);eEkil=6kgN<G}Zr?w4)z!-g1U)X#x`gj9wZcs932Wfo?v&j5iQYd3
zehF$?Cn#;s3(YbTo>gPJ8pqS#?PC5|!j;)EElE|3Q4-~SD8rcL6#McLIBM9yA-$9T
z6~oHN&^d*T=}|M$XD!H&nZVO#k&_G67R9(hXuL3#9!P4-?M!?;A)&6bt!y$@G*^|l
zV`nHmsITuUW*$guwxy!S3mSPglrnaDTVkYC8Xe9rimkD%!ZKY;0xW**-pBg-`-~WP
zX8Qum$py)tGvY;EE5>UtsgutD2ph3#c2q;7P5m_I@89LpCzBW2nEY3VI%t~Is_53*
zzmP-@|IY9Y0^=d_Qk>`V$jnA5PGGTb*odk0&N=t_(Y-&TR^arGkq2QKu}(=@OR-WX
Q0J3^@YUg`%jzs4EA4q5Zi2wiq

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/Orbitron.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/Orbitron.sv
deleted file mode 100644
index 5fe19f7a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/Orbitron.sv	
+++ /dev/null
@@ -1,193 +0,0 @@
-//============================================================================
-//  Arcade: Orbitron
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module Orbitron(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"Orbitron;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian orbitron(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,2'b00,m_right,m_left}),
-	.P2_CSJUDLR({1'b0,btn_two_players,m_fire,2'b00,m_up   ,m_down}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-	
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 	
-
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/galaxian.vhd
deleted file mode 100644
index b881e738..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,446 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
-	-- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 014e6f7a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,88 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-library unisim;
-	use unisim.vcomponents.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 596db956..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,74 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '1';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_2P_LE & I_2P_RI &  I_2P_RI  &  I_1P_SH &  I_1P_LE &  I_1P_RI &    I_COIN2 &    I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else I_2P_LE &     "1" & "0"       &  I_1P_SH &  I_1P_LE &  I_1P_RI & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "0000" & W_TABLE & "000";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_video.vhd
deleted file mode 100644
index dbe0d0d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,433 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1K VID-Rom
-	k_rom : entity work.GALAXIAN_1K 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
-	-- 1H VID-Rom
-	h_rom : entity work.GALAXIAN_1H
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/scandoubler.v
deleted file mode 100644
index 2a921604..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,195 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Orbitron_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qpf
deleted file mode 100644
index 02128464..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qpf	
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 21:51:58  January 08, 2018
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "21:51:58  January 08, 2018"
-
-# Revisions
-
-PROJECT_REVISION = "Pisces"
-PROJECT_REVISION = "Catacomb"
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qsf
deleted file mode 100644
index 95b686d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.qsf	
+++ /dev/null
@@ -1,190 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 18:12:35  November 17, 2017
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Galaxian_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY Pisces
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ----------------------
-# start ENTITY(Galaxian)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(Galaxian)
-# --------------------
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Pisces.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.srf
deleted file mode 100644
index 14cddd5e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Pisces.srf	
+++ /dev/null
@@ -1,54 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/README.txt
deleted file mode 100644
index a402af10..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Pisces port to MiST by Gehstock
--- 19 December 2017
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Release/Pisces.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/Release/Pisces.rbf
deleted file mode 100644
index f899cd8789ad82a79acd64c7cc9466f9a3e46802..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 316148
zcmeFa4VWBPdFNX-E}(${y30jxd6*U5!vHM@utXf9OPtU(s<B&myq*C8x*P9$1SAL&
z))x7=Bq4F1nbTH}HA0eCup;pWnRtov<ij@WY~W@C>h&ndiHId)ZhU#N!6rO6Jev<%
z#97Rz@9%%AOX`tFvOe0oBG$3hRdwprIq!MTd*1WD|MOPO6HlBzz2_S){o}X4{_Ssn
ztNZxl-}%mWzxlmyJ^r01zW2npzsuz}zw@2PAOGIBzV)pS{L1Mo`e%RFBQ;6=N1b0x
z=f;7cm-?U1^Umj}`U<4}V}BbbpXY7m`E^oC%JX&9_1PxX)1UJCPj$@O%kS%1wVCJZ
zc(ydCd_N63&+9+cF>f!wuV++Go`0^#yuLF%=I!L=MTb&82lM==I-aV$^7C|Z9m-eU
z$;Ua;vq?G*kyJ)B>8PZ<lT&u*#INq>W%JxTFTc)@{rPHFJjw6rsQXI!`F@hlCrEj|
zuJfckC0%D{*?E3HKlb12KhN*$sQjF!yiC29^7}f9mN$~}d-+lMI@d8z`Mm}yKi5(9
zsEy~5G`E$MmnZRMn4~hdk@U<I$&!?>`?{7KpDtZZ(*4O^QayP}NSE}Ie^M%ul-25`
z{I;I?ENL4_w?xlUFa0s8|GfV?&(DuJ4eLp&vtRzi1KroLND4{nuaffel;vc<qC;o-
zQGM3Aj>=ckx$^R)yqu1_y?lP;{mt9Tk9tNjBDx|{{=DvM4E4P7{)CjvzyXr-`jhhV
zl;^8_exA3dqhugYIbC@lbU*Kh>QnpsNNv&~(&tHeJEuB6Ldx&u?dv#8s`QfDQ4$?G
zDqF|jAuW=sB+;g44wIDsL6Yw2`Y(G)=XuKWbo?t)|Mm1qX%|U6SCTwrXT_puP|}=G
zQhv@4&AEJji66QaPjpn$`KDgVa<aTHk{%}M)=6YctN#A>buHdqMG_sl&eI*eq<qPS
zcq;kN$L>~AJ|9juS03u6ysYZU>3S1M?d3G($D9Tob2@Y$lWr!dO3`r_Nk`SKyu6Jw
zIjZgVkwlNiU9zV(PL)P`DZj5i+(24I(k;=cYsrUnn^OOImNPZ=551J%Q~Pi4ORw#v
zF_KPoOXqp|y<XDw<s=<HP7)vbQ$KH%{}obxU;Noa%CB|Q{8bV?8gr$5-s&h?G(Kui
zN6inBqI;54Ju5j7EqOYfT%2l*)P8?bdrBEa*>9GU{eHTabd~c<EEa8f%6Z;@6#x5^
z?)6{y)1Y&W`${zAc{@mIFQ-ki^*vHfgO0j>s?@JXbe_+Z{Ft|Qs$<?>eqXe!Z+X7h
zB^s2Mr>CMx_w)Aiqt@7bE}YC8wJqJLq;u(ycaZ*uBw5q?tD|HxPmlGIu63H{=SR)4
zd6MeO^E7Y!lkW8=^}YW(qv!-pqFZ$2={I{x*P>A}s(GaLbi9uw+H{^L<w+;yY0U~r
zJX2eF`Y1{IBEQypl+(7-@j=o~lH^nOwLax}%Kr>Wb&AKbNtAw&bm>V+d3n+;(V!$c
zWDkf=tsQ%NDPM=R)+p&-c9#AAZ7-diCpwgVrk7sUm-6=ekD^~G&l4SzeMcNWl388n
zsehiXbT07YYb1?-o<vU{87rRN-AkfF1w_8;QMTw4@B7=!>Cv%2|K#(WhFr~yuel8(
z{h24}RVCSIO3K%@)~dIX%DwdKBwfqy&~YP4H0Y@G7Ltz2QxZM0A9FgyU!CW3BWH%L
zrN4BPJtUo`q`7_>Nw)46NV#3D<H6IUlXd+6M^au+M}Aa${VAs{r%QbQU6RV=ywdt3
zJ}ButPr4Rg`j01{=W-=J<VkZNx6{;jwUyJMd%Di7wBcd#=oKX8X$_WsQ_{Ffg}jQS
zd&>I=Np{NylJ3h^6EBq~8!ew}DyRGzQa?><TS@a(N8Qs=^(%=tN;;SAsH58X?OxLP
zZ;^DAFDBbwN7;$LO450rr|UdP=JF&N%#+$y%IT20({;|%lj%_Z)OMb7x}-DYAM3ci
zm;RLWYrT}`NteC3m&AjAPtq|@x}|f`prmy|N%UqpSzbPN;+4+xqwF%B-$c5Cq<hzq
zl$WoWuOVqYSJE7oogo=GUCN&oKO_f|CCR?l4XrOqx_+vpHB%`sr+TEz^7NlcxxUg-
z`T4xjQGHU<`45nEd?iV;q9i(W)Lhn4dO~?R>RL(X%FC1TG%iY_M}3t2ocrTC=Hrv+
zy@>QuQl77IyOE?kC9Pk&mcEi5t)%mROUkaY-+tYyu~Yl~DQ{0S<tfk8QSB({Tr{Z<
ze@>EI<w@5krz0n&qon?<ej0Qx*~{D4QSB+|TslnhCEY4rqojHN-$}~LldhjCiAViO
zb5?URPik+a^c|AsUjIGW5=txODgR5or1P^${q<cuzsP}$9Jt7VGv$EvpY-Xn^37#%
z^RinjTtp}3edZ2l-Sy?BedlL+`ryvtvwY&z#k+5tIq7D78D@Oa&C_3Yzq3rYpT6)@
z-M!_-&w8pNXMF$3y*%SbpImV8gvH>);(8;h@mqAF(&Tr-<4&IHL!2cZS;e3^6naj8
z>SKCN4_Dd&54Vd$xKio3H|E`a%aD5{f8HHauQJ5*oEL52QAts?E=#-KM3FpIs(v2{
z-h&&5;?VQns0v;^arN#hjd?GI(lqfdpR4-Q>AuvX#H1Y$_LazexvCnk@-rEDO%?EJ
zV<Ub&dT4C?t}!nRXRAMudLvce+xHeK4sUC}+`eqg58HDuAG&<Vt8W~y?xT&#;GTCp
zmr5wo;NVS^)NnS*D!$iLSB@ujNkS|ZRpxy0%=30l=vNQ7D*+GBjW;QlRGUMO{Mqw$
zYar<Ym$QNN(enmB0sh$$)<0?JT=#A1fVxOE|NGg0Qt$Gvb#MLE{Pg^fPggIUHaH*h
zx*z}8`8>Y-*{7?Q%Ud~ztACb+N#!p~H~j~#D(994TG?_EDns6lAJQ5-m~?@zO0_Ys
zd$>KAE~*wpwo({Sby4@r4-BZPjIx1Mc7YD2*0_^BiSy_)V>x#ok1u<)e(W!QYFWm4
zU0l$V4Qw_QkN%#fQivB)8pA8W&sZIJYwQ8*m{-9oC{`!TkT*Ud%X)obDw}y{{XqAZ
zK6qZkvFzbNFIoc=!JGf{xvw+JddS6~=h?~ipYwH(FpR@Gf{}S#J+Y7<dp?<;`Rx}$
z7Q*N`4;fMPdXjj)ncYA9mKKetqv|!sDo0;?U-GdqeD(U5jF0K}%GXXke(S_bqSxN=
z__nvdr`l=VSo>HxeD!C4{8g7%DSPl^;VOI6Iz6-eIQHe_@mnw4$H$I9``CZ8H`VSM
zA5#zC*t>YiHwLyMd)<He+vhBr?!kV8t$Wk@vjg-_Zo1Z=amBZu(|>uk=gaEyZh6HE
z&$fbP<&W1kMt1kF|8CjM^SCJb_q>&vGN3d-Emrrt@7aC!WMwehlb`GU@$Wx5^IUTV
zy&|189d&f(N~!zG&Pv(mmPaoKHqS3w-e)}q1Ds120=jgH{ts#@In?;Qoq-9g7N+xC
zOZq!p`up3s9Grc9Dudkn%-;-5nMdB;<-yvwgEGA9{uRIebncb)kK9?F4@#WX>_yAl
z^ZI>)i<bBJ1!Z~nPYvY0-G6=V=P2^h@BaL`KfmlrD(k-4MSCvGKIe<4VS1l4Ez2JK
z-%r>n4Daq+U$u<T^SU^<US=E0PipuNZ+ueLIcJ<3VJkN$wLhqp(t9RBR4cRdY;y-Z
zlmj(L&$ch8E>AB9CS%^0?tR{=TRO`-NdMr>?jv{0Pd=5gJUDaw83A`+w7Q>>cz5*r
zVTW`(C_5P&6ZrkI`vHaTORD#`ZmE5|9NzGFYwSJMqwo8#Al;M&_I}g>+v6u6$1?o;
z0)2dJNVG3Qy0eQ<Y<<zdl;yy;EeB+F6FQh}4xXjHK1K11;MFM@bIR<C96KdzPH|(<
z92=Oab`k78#fY6cd(dNf;p*!Pm$E^vBz3>^hTl+}+tY4%m%O{bapAsBa8aL}dcLo8
zC-c0Yj+hO?LDb-RhO4aj_|qH1axv0mB|$m2ycHpj(z3cFduNz#{NnJS^yU9L%X>Kz
z+V^q|onFp~j0@!5@`1tb0iGdypSsw9ak{<+PZeCzSLAf3M|LWzZ7^xjW>Ftil7%O~
zCe~Nr^rzjw{>{@DIGekS<-it8?}vZwY??lO*{4s)PT%fR-n~fJQ?lr!0t4pQ;N*3n
zfhHFb?*Z<fT|~Uk*JOTLtz%8_6>akK%d8*!#n)d9@&3k1>hs($>&HI4`vTRLSy<k=
zcWv2|172X3)qP$U7YRFC_B~@bHYhOinYB`$tvIb*e!xODI29W`_(#uPndEcG#e=<Y
zDQgzap+_q|^8Fa#od+1N*rBt|M4SgV(9a+r{`(K_)}nEKCicpYU;3hpfhL0sG`Y~D
z^3GbptoXpw2#~JW-Wg|JB<ze?)hl?BV;4EL5(frsC$H4Rx#e9X>}>fqD2};zO>VkO
z?*KmSF(%%?g1fcj*8T9z*)r|a<p;%1TB!T)-F@nY&i2j#2^+YRLSMfBOzx+T=!;1A
z;E?VM;2VxlnyJ}qd8Kzf{G>bQkdZ}3+;h#qV3Vg~cArDPR(RwBu|`*j%K7ErS%KVh
z%(^fX^$GzuyISYiqZJ;blLJGhE{1lmz~Iwo4SFUGYR|$O_^UV<E@gubRs24(x+R>0
zR&#?I=x5fp+0%g;Kdk{KS~Z>yU*X~_m2Z5yUa3q@zZRXr-R_5eebC#2XVB`I6nT;s
ztDncmq_=(gOqx8iGEXAx%pO~@)S#_}6&pF1%!`DbE!PIgvFONvzeRSoojGOsi^6|O
z)~tL(@qjDeIhWi)vOl`%vJ3NNm*TOv>bstU`(Vkb?Ds)_Kk$OZb}nMw=V{b_U%pNm
z-Tj-FT#PRn+^cC9y0Sc%#bkwN2D!ehU=U@0c)|1Bv3^##diT@+V+DH8G3zP1Y0j$J
zoqy#1IPF<IbE?8C@a$AYpF003dim59^p$u<5O&e*?i=wlJH1e4?4sFyX5-ga%9-70
z<`u1FgSKALATJiq@sXQ$p5LE{=%ak#wzr_r!K7zOXt!4MCn4Ti;h$`LpJmY-tNvL&
zaTat?`K^N>a>XXQH-2?C`Fs9s&THar$$L4z;{EYMue&dK$NUcWLBY-QJKPrq%MWkT
zCj~c~-__sH;o!b0*m?YeJfd$3>iC*?XZDf7S3DlOzpnFrSjog2^(TS8#^2Y;dNc9H
zuiGyUZmOO4-`44$@vLj@{_Ea(@thRH>|d==)v~NJw>Z0BT`^XGsis+Sw&|8VnTynW
zcEu{5nzsDYD&0$ufBjlh|3q4T<ut{Ko2NSKrdPXL;<*T0k+@Sm{G|Nu?|(AOt2d65
z_S8Ldk4S}8_}8Cid!ukdAWrUMf9d{nR7L+EdUm(2zx4D-+!+#@HS@$(y+7o1rWEy4
zck=lY+k=y{&iPtC#Gv+)FMjI#tcT%3HPr_muW;6!In@JjY+&-L7nItkYUr%<zdIsz
zc+pZHT&UYK=0i$aMprafFIwssEp>g&9LM9Ifu(*zrJjxP^vI76op^ACv*HQkafQ1l
zWp(dbe^SnQTpnM&>ji91Yv~o1Y|ku}6)J1b9U-wUQ0B=gH)7+8-!s{7`JopTa|4fu
z^}J{K70>u*t@W(wF;IqU){Hwj=||ebrKW%PRWHaZg^*$_VvGPJXTnomu@N^4y=q;P
zJh&pk<i~l%75_8u(%@wMwCcTkjBBIJx+*0nPnA-3Rcu39MtgRvSE1uT#c%pI|NaYl
z&sYtwBQ(pPk%F;wKPS>V?gtniujF0Mo9r3(O&|X5{LN+XmROJ#D{A~)I#rjmySY=9
zT|M$1eWXHtUv}u#*~@n~d+jWLJiF8Pd*j#(^ic1?V!_noZ1_24(EHP}%KL9DKku$D
z*K56=Wu49YNjXl9$*=o7u;o=`SIwNQ_k8z7JxUzN2p!arQDZbTCmz=Ma-vV%>p#2k
zcb<RzQd3A|i7Gc=kfJy~Aw$ShUkk?{d-BOk-{nS{p*UVu@2odE`6K-l=Xom}yMOr~
zPs;79=R_SR&Q2=5{PK}cIS*f?xoRAZEA)(;r{!QSPw^FR7<NW6r9}euX~ytBoHR`K
z<AT1Njuoyd#_#1m@#Yhg#Znb@Gs3;pHzD(^r#k-GWfc)3`l!wt{kWrK+ns3i$v4dS
z;|-m**5gw7#LqeRntn575KLpJJ}x-5%-oJ?7>aYHdD=R4Gw16)zw+$1DA6D}+D`nc
zA^zu9c0-TBcdHC{zT(eug74*a#b5Nj(pa?crnc95U!$;kW4l#YvuLLZEi`ex(Aw0l
z%(QpJ-n1EucGRrb`b7!_-Wq$rH8HK*u~)24m?3X`V%LP{tuOF*(N{wMN7lNBG;Eb)
zckFRAx?Z&k^-VOde{o^DP2MzAD6hz6%l*r`!n4zqV)#y#a)sXgANQ*Wr9G8*l~bX~
zYs)iKUH|gn9ynFy#|NeRhgWzK_KXtujOf-Ja??dE_7QpdN_!;N{RgjgXpf%Ex=m%%
z48FuwiE8*?lpjy0tNHjq-}Hq%-a*y6XLDM6muFmO-f;JI8o6FV#I-)6$q_%!a&gV?
zpZ0iM&fh<z=U_%1QS!{{0HH?6)P01!$*Ns96HtHrZ(;Tqm*9EGo#T}{9@WU8Xw%Pg
zyMOdmG4gmtmL{Os92UX)Pj_rolY%+tHop6BXWM<f=#fRc7U4LMckYzbs>7MSU9o6%
zw;3)!^kerWU!L3Qb`0J==Qa?oeBHwh{xJPZqSvuwu<h;a80=`>So>JH{O~X8j}et0
ze*JwMRxN&Q-F=CJ+BtrC?pU^A@b<ZE2jTm$5_SySKFGuyv)*uh{r(qdV!9+=o}5nP
zAzn|J>i7O0BJ-3fpP)}s@H7ACB@zyj7RP*~H5D~+^rPg2#hp1?kI!P4wfqNjvUJNg
zm@O`y=udXWVv{K(w|1N;@)R|8|K#&oed?8Cl9A=ll<al0S84B%l|Ak6D<{<}t>4Ef
z>7y*GwO;d8M@Wff6*CVi?vA^e{WN`YyFdADJ&-3?I~OOIz?7p=-KVtE3pziM`bxUY
z?mvD^N7rkeICtmxm2xyQ<6c90`s5m1krOTjnyvemw`G~Gv<MO{q+TCg-!lyuQ@JYC
z9Tm#;qDtq9k!$+Xm%B^%sQa<UIdnp}^Cvj2n3>;i`rTiCua|O}QACB7R$S_{BC@QC
zU&NfrZiY~jogM$p`{8+y+<)Ah&IhxPS9ul3AMBl+)Z-KN|I~|5E_&|Q$KB;~uj2TV
z&xqKk3mSz#J{0GB@-z%3lh|1@=epQS{&Op)&n|dr=4PC4hu!l}L$3!y*TCa;216CK
zIF4nytfvcYuBo%!Oxv!Y;<P7oBAw86-GA+tofEfKI;-?Qs{&8T=sk7)7oL@`Et&eR
z7kcexBsr^t(-jtlUb(EI6ZEb5pR8KA$CFO+1JPvt&h)zaT#p-#Mxo9>D%ZLm&##TS
z5!VYLMvd`y#U86Wm*h2Z?Za}mhQ!UP?_fO870SHf)B2E+!vLuex7Jb#t1TwFYom}9
z$)_0>UIVc`ye!5!z-DNG=3&6c^B|bc$F7KFm1@<`I<7Wdr?3tIBPJot8WAmL-`W4J
zKHPshjoa?}1j<Q~L$MZS`qiu^HDBjzz#fgMlp1a0JJQt<?aG1Zt?xo7!-}c;^ZxA5
zIGX~_&}6p8!+ilFLIXI(N+BO}gMO;thNV?-K~gU)7=e}I@_{&X>;fBsnH7^@Nzk9r
z3juBMYK(8YfBv^_>`j^*Lp(|SVxz-d;S0^?h9-^F{9<6dP(-L$7{?wX7n?ZbIjWr(
z4{61<Q1wlC_ji>;g<g_T&RLdZ9LmRW!;%?{8RJ6^&HO1>w&FVzL-m@f@!d_Y``h{3
zP|(aHF|8PHJ`tCktmSU-EUiN$Kb$nV@3`w37}MiDw?(iL?4g-^Y7Wy>HPq~C;~ql`
zvopiT8Ms!X3@doZ(Ihw$7I_QEEH~%~+4C8_y#|Drhkx-0;G3?qf_WsL>VdEscbbg=
znQENQ6&qU&4bU1eIvF0+8bT;#0b7kRbwji$=PZVKydVGXo<&(r4u{IXX?IB$)nu%9
zIVz)OkQ_gD%pr#+7*N$|sjNvW$N9qr&BR`}bDJa9QLZ{vQO@z+9c5^Qd8Wy<%IGPW
z1;^^<X0u2>W1tSX#=KrD-CJ+SYH-AH4>5-kk{`IC;cywMUaE!Z8^+w!3~+TFALAy|
z$??P0Tv5C5F}~^jF3g_l@{tt*5_DGqb!7F62v>rVVbA{n=C2|`fEJnTsM4nTr^>y%
zpLo9Gc#oyjBg%V8;+caTj$iH;MY2MnJA+)aCKe;m4hCWIGNyF@;L8>I+7md2PD+e%
z1b57-%$n+XFpQx1?ZlLBiCD;_AF7eWyyb#_?xeo?vEzh_sbVYSh$7Xm=|xRWN#vEf
zTCyKl>iX}*Pgy;x)o6F~A6KM7G<+yW5ss6I5_OA!Hg9x6<GQc8K%3;Ca%{0(ifhK7
zM^WifWmz*XMu%}2mTS9_QDiBe-%Udh(DXx+x`=>Q`~#)`zS=__XIc~QS!%(ct?2>G
zqcK`z#;Rjk`*fUU$YD9Mp$KKRE%-b`EmUl2aFHQd6Nmh-(L-s|D%3QqMtZ4I_2VnP
z`JA>!2kxoA<^)XX5K6Jpfw24v0nEy{Uv3@Ha%7o`WRzX8SyWeO_LWBbU2$leYv~!c
z%LO{TuS7>j5Xck%U%K_ZFLY2~c%<zYHvz#qoc8T@*91W3&5MmgR`_66r1fyypKc4w
zohVG#woyi?-e=n_6%x+3(;P#=lew?d+O#kh?KE!&O%$GcUrg)kH?^l2pvs*kZ$t%w
zcJGZ#)rmXTdLxfktHBS<j8N*@%MRFZ#J?xLvt(8Diiu&z*&M0mF}MJ4viXPna*hOu
zJ?<Wa7c(H1VHhbD!q%a9UkL{7WUbSkorY#`lrt9XD{-yvJDT>D9E+Gvq6J~sVZ;yb
z{zTxI0P30p#uB>*R}8x25YRQ1!v`)M%&ekJVt11^^5<ZV9=s>^#es|;2uG{nX7q@-
zlmFwUqon(j|I(Y|88^e|rW=0!YBF;`RC|j7otG9h%%m7i$yKr7&RER2px5*%)N`%E
zh|h$hgPtcoYiiTg#Q)k&tVXUa$us|}AD+N+RnDW%M1vFxX`<3wve&303;Vd?2ErTh
zxr{k@BlptRY|K@FW|;Ey9EHW{kqJO)2+jqcuDJQ{dLc~$)vi*Np&L3_3<qkbpR^?f
zGE!xrop>K_K_jPmuJ*ViCG*OMT}!GVs|w1g&{do*c%0H>@kbR`eA?zD>n6{LXkYeb
zj?B{pg~(IZE!JnSb=vQjxh`0hao$#O?*wIfn6X>ziw!dbIjaLm?Bzr6@k*%wfP4TZ
zF{8TidITS`Wi!@IC>d0R#Y2mb$}KvxP~xOvCL|Jo+@7~%QA~^riyf!EfuJQdfYWg1
zu#*VO_`xD90domWtsY104p_A;Be45{uK+r`h1r^@Mvc2Bs19OX-&~K$M>1m3Qa_X}
zwD1uTw1Dc;ZmxSf#2@toZg7Kjb=QRJpOlhJt>_JZU$_WBpTN^k4M1y(l31WL2-#F+
znB9zZ*9?R!;j-M1WR%1L<Yg8EXd^Sk_*{i@D3s#priBxKmg0>6a$!At+Evm2)BX7S
zo46lHkCx+BD2Iq7S;abL3llPR<fdEm5g47~(Xq7G+c<jksUB}Jv)u8#O43*tvw&*F
zrb-9YY8jU;(KOX6ov9e~d8Ksh&A;es<|#W}V@;Ns!bFzoK%;0GBd)QmBc1qTPU%!&
zMX4YmwR}ak=|hO!<$TJDFH5P({i;tXIEW^Nmz;mC3K*HVUWnr~hUC+WoDI$m;5HdN
z&pouTf!=zdTv$|V*!|AiQkUFAOm`aa(2pn_{$~<)H~)f{Ch802Q{2mX+fUiQ!s})I
zH+AcKrelhmRH6a*kd6+<h`gM17feK9&YEVaw%MRLEVpGIFy_p8r_n9V?26@5SBB`K
zrE~IaYTos4c%f%$35N_qZ8B{+;z?Bea=VHfIZl_n#gg^wd#P@6Z)`9VXHA?gbRwLN
za26)h?IJd%Y#;R>D~NF-(>AfiY`lo$H_PxluF5m~iwEgIfPIsiVv3x^Q9PV5fb(+f
z%Iji=Hx7zZg=sr$I&sVT<-$S|-=S_Mg^DRfha$$V%t(9lRg<(6IrZ=uuNKPDHSwbH
zB@yMC*&X9mFL2|M1wS-K0~<0!7KR>q_poPfjw9p{enmmCF<fkL)l3e>sWoe&N(Zyc
z*rhdb8k<fz@M1=j+O{O-K-}?)wz?S~zK|GJV)}?o*^srvhBO2p4#aY@wLd;<D%mJ6
zR;yK6Y&-#Xy1(*f*k&P9+<-j@Je7E~J<2o}K7jB{@{b-+1*B*8do2lOjWcT*8VzI5
zaz{FyK1XybnFvcF<I1t0dXvX^x`j63j+gLQ(Q-m!VW3r{q~;?v&Kzd^G@v+|ZKRF|
zkZk6v#8hiRB|(TNVw*lJ!b`;HW954HcPSK5u~v;Gp0HsIInqaKB4ZLSffF5dfy@+H
z4ZMT`^#IG>ha^WH(qi4*km_>nQXl`T9xsHBC*Gy%>tGuJV(U#Z&AGx2U=$5^)<nnw
zUP=H@N8MvmHLRI|SR)vT-qveX*D+nwBj#=fj)<8`^vw&ef5{6iMp?>~rMAhK8Z}7u
zAg!kWO%@*4)3i}YAuxmv+)i?txM|#G?n4r0Tg?~0`4?KT3_+QteV3yHsqTO7qtb=y
zr%4m4&}=NX=@4QXGXoI&BMcUdiOYLOxm7BpVZ2C}TWKS3pu&QmdO{kQeHFh_;tVdp
z(7nze&?HfhBo%H9y_@YN@RFo)qG_icQ%hrTE@>u>D7Jp$naM`P#D~+d$8^6gUNZ9x
zo1Q=#j2jf>!n2wf&P&xo;ChEHkX&I5-2FGtu~}nD>ZK``CZxdOHIM^S>Oou_1{Em>
z#Vtww%6L5;uOxxjO5-adl~*k;evWZrX2;IHKx`3Ea-=*pgPL@nRpYmBDxz1&aI>k0
z{CG>nI7sSg&`i=olF{O%SmVs4dw}{pC$CNfB=zK52-TSr3`%mZ8~&rNHHqp0tjW%c
zIE0q2cuC?Gwi>+<n3L{-Ns|(yVp<4M!1P9f$WzjydYFkFGo?5>NmW+&s@;`Bg4iLs
z%oiu{vy$#G35!99ym~2<p2bo&rMDn8W6_A}?{ykwQA*_+3n^p`ltK4vJy4EI(Hnk8
zb^v9p+rLZ23R@p8jw89WT#VPnj)q`;B3lIi8(D}72O|0+f$6PbOn%iLW3Y&y)PjQJ
z8fkBGtLcB{j_1#rg#WBbY+@$ksi`OptZhY6VR5q-{y03m*(CFwxE!>W;xtU{RI-Hd
zmm7`6wQ+J?Y&L8LZ7XyZHgkc5ls7e6>97sWBooXeTA5H*OlnOs)H?tqR)E<Rmuu3v
z%%-ryLcnrW0RxgT5sn_aV?1L-Cry$hB~GycRpmwvwR??$zxP*@w9!u9X>8IdUpbnV
zM@Q42jiZf?ay*QxpEsR|_$KSGPtx=uTmw_w8!xOyKtljO3NWAolbOXxDdcT73rVBq
zgHK=~qrL$vphE&+y0`yG)7g6oMu69f0$3%jv<;VRw$q^>8|{I(6^$nkH%fN1X+?Hx
zyy;Lft1~Wx7<3>m->}##xeYPg8z(Mz8({ZlgGvD-V45;XLh3?Xg&Roo8KxEgXUy=t
zOOHMDn&~tt#-rn<y`yO{e(yxI5C+rxx7n2FF6;eiEJWb2^`>T0oZdLVFHYrMf9M0_
zOQjvPgTvGNuUVSBFZ@D#=J3AKg9|g@0>?(9gTo`oqG&SMURo7Tj?c7Po6?b^?HMz+
zs<eHrsT{3s1xa`e{*Bzbhe!6~m){c`ANLjqy@iN>sP^TOSzn;3k%@c44^eRI9fhgd
z*0=!vf<6ho2U|n+Vbo#(U-%akHyz4-^_zirrl-uBxSSSt#I1O|)K2aK8%TosrYQ>D
zkfMi19yK%V=CNqBRoGs-K1m7=@<^uJaWVoA<=VqbkdwH8FHKPci2#5*4IXw2omec$
zQ;lh$@Ca3T&>gyeUitlTA$;klhgk2H(t2Ymuq-Jy!4I8evc=n}dirpyunPvEsal&3
zr~68iMEtO>9aM!&4&NBrP0jmC2{=bmY`{R+-qO?1rYaz;S%ogh!F62)OJJP(bSF1Q
zIN4WPge*Pd{&|Z>+y2de@$AVfEqXa|{~E(}$F@xxU7-us`&@LeuqN`R7t<nyd7ViF
zR7$Lak1jRl+F}VelXsQCYeEOXtfB>+>o99b8VG&OO2}#+dcY(5N`wW{Gg;agX#T%?
z#dPXn{!YUceiuDcXABER+6e>KD%=wRu~-OL+E+3ML3)+|EH<Sf-3}ZUad0XKCsQY0
zj;m@vq<RPZ004;(6+^QlKFe1THlo8AL?8^5gGULE(rA*l-!<=sUe=y8En=uT>kOT0
zyvbp2J!CM52ZNDh(;|#Ghyb-G?W3j?fCud>9gGU`WKevZUQM@?3_!3R1H+}J*@%zT
zA-({axMg!BffTd=Ik57cZ@h4l`G0UU`v>^72~K3Hd@}GbLt#%n*b%3b0sOM{@q6QB
z7?yYsCiIP#h5e*;=8Fs;dZYo+f<Plha$yRsBNmLj1IL;I>zHFl+DOgLue@+_3h|pt
zkF;l|kN_Nis*``u%B7W}KFq=-D=@|JhcoY{>oZfj=T<5WalY-0o;xCBTqc=*iUpwv
zG5TV)l!mv>>{#4al9FR~A>Yj8?l-p8M~7J?g2kDJ=82hLt{AImzI~-KFi3e++HRP^
zSm2>)8;!ifOu|9??qIPLu#^<yP9no_AsNPS#y^QhdRU3qtadE))ybvHsKWZ4Rgb}^
z`bAu{#SY})Vu+drK&_kq{*wG9{z)^075MIq3ADZB)uSLz(ZJJDjZ>Sx8%4}yohr;G
z_z<IkmmG+BB&s<DyE@32!2(6)@~8^2z!s!n*8~#-_G#(#>W_ZqSr-A4rvylZO=er2
zmbsy&ljHG(r2#7q%RX5~5-H=<%BjLArtq=^_ho70voRQqz_IWBoV(9sr%O+&=R{$(
zemwoVf7N`hr7-pj2*@NalcWKLVPHbTEJYF$92K18>I{p1G21wv-yLE6ZAoM_uJ@4(
z8_Ui%i`XXg1V25*sm7wCS4bI-Gq#NmWv%CGn&QP{pE_DmAL0})Fr{dpi$&Khvrvjh
z3wQ>8eG6hM;$%l-LSluoRN}XS5|Bq*I5Rw>J;!*#=L(1cqniyWp$o2`Or`G3Mp%my
zkT1?~ETNl{)MBG9v4*K!!c%lVr~~n!>F)RGSvg3&*~B{#74f{`hFwVLXNc`ouXSWr
zx-ns{Qn$gw3AKpqiXpe+-(7v4H&!XMy=Fe5O>ovzrUZ*UsR#H60cH4^O}z=+U?@l?
zQr+~5e$pt_{iOcb_&?&lmR|ADT(GM&Hh%S?J@wAmMAw#TX4f0nH+I)nkNc~v>4wSF
z^Xj$IqZ1FGTySw{*ThN%_fD8ympw&|-hAm;&Az(fm0mmk*5getukoI6=`KioL@i%&
z$Fm+WW8vmEvYz}%<LCcmZdIdwp!Cxpjvm=`=Xm4DtyeBai?>gd3nTIHduQ57H>!=5
zUSlczfBeM9cTFr@wlRM7+pi8j_+qa+@v7~$XkpJ!mV;Gy*(2eSH6!Ns_|n_k$^5<J
zxBvLnZy&q5J(fJWdH<`{e?IcZ=B}8#YB5^4eWLj&F2WTh$~Qkz6Y+K=_`!F+Y`omK
zE4lj7m(>a%{Go}3;O>dnflaT*^jl?ZX*JH|$4X1DDJ4@sKG*%FA35c~o%Ibu^wN~2
z3R937HO!!|PYO6;IL^2XAY4s<10JzgUk6ywHfy6LHgT6?9E;GP2U<~#TLrRXi-&-(
zLKd!yU)+M^35SvMAis*xj~aUt>`N9fJ?l03+svbaePV5Zgj#D5GPbrveVQ;Kz@mic
z+4UuSYu<Pu)Fg4J0eg#>9HBRF)*{?;Qt(5;K^%sFR|nbz8Nx_a8#)Tp%fxK`F{xq}
zuL?c~AkRO&t(XF)ZE8$6<k#cKPtk?sK%^Nvxy9VyiNo}8wF)|rF0PH3vWumqcyTwV
z7JX+SV@Wb8?qy7Tjg%@_NxYD(iwzEnc61eYK$DB5y{ugH3a!*E>D@S-o-#(76|AyG
zkj~@lf1iaJ93x@Aj~0wsf*lqtjsAy#1&yh=kg^U^ak>U<&6FQ%BwGx91p5=GfQ5@c
zjo)JYscLDHooqCsL$Oeda-kx01IRW(U$jltYzC4*<y=lCa4X&&n#&|LQ+1xDVDDn#
z?)7XzC7Sux>u3RxrDA*NNLWW9(-|o*cnb#UwE{+=>0|MxCYILm<hpB5h7`+z=a-?t
z0}dHF!-kRNp5e8Wk9@<cqt3M^IVKekMdBnki^F=3p<BY+2lkS`!e}>3_+UT>)KC_X
zE<@0@0!qT*N+(xPYe<<I6`Y8M$8zy(_ox4-N_IpQ9CoW9PP#AwmW9OW^mM&MRzgZs
zc!1QcF$+8lVfetKHe?ymNhn|ispOXf`BXc`17YRM|Ic$Nf>?nF6^B8oWe}&HcNj0X
z#WKars7s4_X!VdT&`tUirtII>{0DrAbg_+I7oi@5?qr<Zb75E_n_<Q&fE6%WgnjAP
zpKa$%C+!qR3royi8pq+WwCDjLDK$%Aw1Pe8oySsGAvA#MC%K|^0C5<g@xaH989MBI
zO<C<VSbC)Wd(CeFf2_a$p6>gvActp3tw6YrCMGD9?DY;(+5r{c6=5J~?Vy8(&Y@0%
z#O{jlSRgxG0B5i?>p}y-8MKY4pa4#k+`xGt1hMzX7l02_T1la?h;8kq;2CZ<(~JXw
zHt>*xlia{mpd!Q;Xv>a4gHV~)dcbdbS#N{Ex~FJOST`%PyM!1D-|{|zJc+<?FGYxG
zvJM)>0t#(PVX6_KxmY8WL^J|+G{sO@#zmcV;?SgR%P{&2hFq<|<X9dRq9uFaYjfGl
zt_lbvB@l@)FeJbbOl$|m?uhDa#7G$BR098cus{H&DXwFXjI3fkticdbWt<1>8+DVR
zgBIHKyx;pXM-hBaC4~T%aIqLjbpg7R=v|Ufn&hBu?xYy^#b{lWB&Z+dTbittq;we%
zi3a@v%jPKL-Zir(p59b}q<SGm8KP{4^`l)L#1xzl05Sq6GO&aW#il+E`%schR|&XC
z<SgWQj3f$q%zB9=y^wHFLeqqK#xBLN2dW5x=8)G(Xe|wl*W4XZ)T>*+xWr_q(b=Tv
zaBBn8bU&6Sy&gPPUDC{9<X9`TKTL+&f~Ry=&1pYP6T178ud5JAVbf&E6r*6W(6PWI
zNownhGj^W%iS$rh9vwf5FS9KHM@zRQc0(z;Dq1YHCE(VS*{o^P_B_DYnrM9qHC;ax
zC*>%$ET6b!@d8>45A6`E2a5}vD7zTJ7;79sT|~_@FIf3%{sLMWWnN}E;l6cwYgiQb
z#?c#I_8k1HXd{3^BTh$0r-s2MMyEE~bn;LH$ELPMn;Q4~8`i3c>!_8*v2$IVETz}Q
z^Q9Uqlwqp}q%DCU6HnXL`0j|(Vc6Lbf$gQ>MZknmD2$FBCrqxkkH0`1X}nN{Iw)r?
z;m$leNN|)8A1dMzBfV|Re6@P4wa`S%3$1(dKkzvra-+jQmL4Ex<pgpEMXY@;pvM7l
z6w2_uZAlW^9Z@1ku2;w%fffoNQ*2}5psxb#slX$g;W*0`G6lY)XIKN{!bhsU=1l4C
zvF89e92^c?4<8m%_m=mMr@L#QB!ukTkgkq49TGTKI%EMzMgiyU1aBI-H%b6q8h4fA
zFKn4uRa&*q0_p6$vzqRi0CLa+K46~8&)*x(q&LTpkB&|XuA<n;%)(gt-Z(?(wpl@R
zc=pHc5MBsOqqr9foCG+8(g%z(D*fj6zS61?JnugV!%}n*kPH|FsK^l}=u0ofhH43D
zX|YUCH-M-PgU1~l_9(p_^y$IQOnOf|lcopaYfGu1m~nx4ljEQo4vCsMjBPWy2|UAZ
z&QQ<Dqshz?WavRyLts$V7ZgQ(JB1Lr=VIRJMB0TF9ccqgxFD=~a5M*+P?)LfaHSEJ
z?@@*Y5$^smUuCczRFxP)OXlFF)LR0kv4T5=L&3IqRg|J;gH{}m8^{JlS`wf&8mx*t
zFcG{;1Xh^-+syUJ44z3k0%)VwKp%Z#s)XXf9-(X~kt`}p7>Y2y5VVygRD?@?3oP_J
zc>lzozW{B<?v%jJO^11Bbt59tnGA}X*xdvhnhe4O#-`W})}Izj4^NJRbv6RKL^a;}
znJLs8V+BB|T0u3N0yqV6qD?v1I=Ca=rkEX;AvguQs?tT;D1bcHi&b%SWSju=O-qR<
zL5x9ZQ|JK4^O9!PGkiuQF_6G8`(enzhDLOW+=IbAaVY>aW<DGn)$oQCq&?$_AL_cW
zG%&9Nu^T%@204<L8I*7%7O&D!gZZf_Lkb`Vv|i}0`fElH%&#>SOdkS$kAmsLDDg*-
z3E{rpHOVBX8+UDMV@mj##`Iu-@$`sEZb(O}uGkHSQMMVRD*=TWF(ZTer8l8~F1NyD
z5GmBMuwljEaum=+43i`5o*3w<`<Fk>60%Wd0(#o5)k{spAWYR`q$BY<tYf&>V5|U!
z)8w<11(mgo4~iVA(a3Ag88`<WvIpFjjfg-*7%|Q=h<2V8g8AXy^wsCGn5dtuN4&{u
z^d>8tXGacc{Vp>jw~pR`_y!D3>rL(Hv@(;vnn@?3i2V^bDN7i3dJ2&OuU!r8aqD6E
z>rE|yiml=nHZ~xjg=vh>lqx5u;N5Mx!&0wB8N`jbMD<Q653^{YGB-7d@uVUF;*+g0
zBrG8YDqO<G0QXB0q9lVdiUJ+Z(3p9@;_sSZ(o~N!pF>&htlcuaqjihg^ne6kZ}>K0
z06gh_;fH72+E)gAMAI|~hGIep`y?uWHMrAEu;SAM%!Nr3t%Dx4b!*Sn7%`j8l<ZM}
zdgc?);{up>I5od_LTXuIQ`R^p9EhEQ7Z?iqrzIK|WcQ4B)9>^HfR825h>v^zmo4s<
z<NfZH<L?}-ZSQ;M_;`%e_7k7?{QQ;*!jvV16k{1TOoO;A$^2nd-OhA&1LqcQO9~i#
z81E6Of?KIlt^k7A{o)U0Wu09ptLluCCR|@~K-1U$;e~A%SJJ^dX_juV#T$s=vD(fo
zABu|)H<(P`lA?Mr!NY}QF}W({t&NS1)GJ>p7@#;hOvmPN*MK7`yD?a0xX@qx{!pkO
z;hwlFvfdVag-kEtBZi=WMJyL}z4*=hNALhrESI$79T-ip{Mf+6kzgZY7My_Tz!j|6
z9jEL46sKw4PneKcyEr|dB8!CF0ClL^db`?jxMLX3JA)ZNKvgLO0DIJ8BzaAqM%6TN
z%kbnMynPr=78vF-n#AH6BnC4ao^TOQV(KqxQV{rrDr75l5uZN+PDwg=>>fromMne~
zgO$ZjU|cfNM&S-XkTclEC<~MVreyuOW@L!obibf5MIaw``|(!OLPvp9+TMrl!|*Ew
zx={xMSir6`=eR+TG*$Bru@(+Og#&bGWC%fNvO}N^b)W*=riCiDB1SDvg(XS~ObL?^
zVIlr%sQVwmj&Uz()1a_e)dWDHsv)^)HYZr*78AjlzVr-rf_n-jxan+OplmEvqP9G`
zM>TeFcTL+)Z1s;jI99vx1+SuT7uEzK<tjcxeB(d72=*F=I87~GwVmQrifUq?CecRt
zVcItANeh$#o*DOXGtIn7hOyv@UTa(_TsJ8Xr;G*x-hnuUV6=^}37jzWCKJcvL*j<$
zR&4l(wGSC01|PcS-TmzVhVDrLeGr3}r^AG7MPdXP6s8pHD=)<$KuDgP1CvtEnrPmX
zwg4&^1l?9PC+iVNdyQCUP^^NQnu2ro0x+$mw`BQ6a5RYm(#Z$`RfY9Kk-^cz;lRnk
zVE1vx$4sYo%Ot+9mQG@$0W1>dzy*3vGiFvSMCJ%(5Y%2DMm>9QA9+TNC(diqM!p8f
z^Dak=AXy~5ITkZFv*<k9fhf8Mf8jau-in15_EbY-L|7ixH@U4qD`F`ktv$2w4PRLZ
zK8{}i6tkBY0^B%H7?NN;Cbt3u5I2~LP%*BkEKce|kz5ZKt3%fO?iQ#`N=ujrL6uV_
zdXySg`ufI(6OR;P1xwPN#S#l(gm_>q+!9}0#}<8h<YH>{ibEZ2lA0<|pe6Z8cu5Kg
zB9U1pGbByvfyWThP!i83!Znf#!o?$SMaqb2&2+%|XWzl~Kzj;Ugaqzs&Z2aLYS9W4
zu#hnoE7JShIfz1F8h}gg1V>&}ByoZTgd705hyp1<CX^b}N=?OZidw5x(V!~1hrq&T
zxo|`RBBE99=q^7|_uwCiE)92GJmIjV<En#CglH?e6d3`Tk*H|6%fU6MNji!$Y_Y{i
zJwR7(#JmO61Ns2fUXWx8g`*ORNMoUj{@~ScT?!D&I6_|22hMsYnfQd3M`2G<`cC14
z458rM^6&=jj;v4iMzUFGQK%dv0o_e}W&WYp^%4r)a4dxWCN<so&gTkIb6imG(qaR^
zkO$fNC~QEsQNQ|MT;c+?T#o}M2VxC`H#@M`a>D#)xe+2Q43)Afpl7`9>tF6B5MYIb
z-b+DZ&_3ud0-$z9gp6X8CW1@d1dug{z(F!qxa}@fovbm;Bq??TRyYM6;;s={Xh5-8
zL_T<J;7-K5I;RqMKrU9q4L;5cA!0!7ns|^2Z3r*{SBj?eb`ap}Qm=QSTmi!BxdTQ(
zm1qTX;N}PPjVL+-#sJ5r8;q5$BsISiCXnK#c9z~K)vY*CB;15`stEv+wgPkoRI7G=
zES-QBL<&PR!@MK~db(0gj=n??8TUjkkqlZQQgZa9hL(AWP_i?(PQVz`R3ZwOA(Pn#
z;g*Krt*cLu(OR>F&{2VbYp{~DWB+<nJus|$JY=n{6KgdY6WcM#f^dInoTcpW+Q=rX
z>^q`XT2N~nW*Sp7jhG>1FL0p~FLXxHTCDK9<7-SSSl@}tL5IzSrTJ1MTnF?{`XABP
z<^cFR${B6Kds2k5u^E6X))9zdss;xTfr2~)+pi?Y-u7p>4jKk_00@>O@Txe9Ti<%f
zVy(=V!03vF4b|PF<*NW<N>`0;n6cMEs6w1&AdLI-n^8To<Y$vkJjL7#Iw6EXv?;N%
z2>05CpkZ|jL><BwnEXWj6pHI&y&JYr<@wzrm(W#Ka!EM+FSd{UY>QDb{4dKtVZG2n
z|4yJZQLwl*J`si03%g>Vw;9uX)X>)_gE@+^%K!BNJ5~P?BUp$Pjvl#xzzEFrzW>*h
z{`ODn8<+5pr*Jmow76-<`U&$Uysf)Fn<lFx7Xako72ILstF{BdELDy+O5hJmiM-t}
zd|>=5rDO5B$>EXC$Y+<5A4o=K7Ks{K6ecrrv@vtI@@SF}Gb1zvpDe{+ED?~k(_C5@
zIl7;SEZ*9ZXDi%izY8&<k)*KA5XPbx!GKHveU7#PeIC8j6<65J$h}rUU*J9NJueq#
z(*2E>GqEu0Hi@%D5lwESLlSsLsiBPy<jD8mX*PG#(0(pT@Vp7k!ea*+p<>_woaj--
zZNcknOTZ~3GikR6<`A)hAMUF)00OzUnOA;18i{2H<G|qE$`yBmh9t;0Cp@S3m=B=h
zSB|}UJKIH@7C}S^DFV$Qq68;<DpAlC!B-$QNhR5sR_+}omZyFfFT@>&R&Jt?QbN8)
zg%!ZU2ISP?@8V2arwPRbVTOU5a1-a3GEIiPydT$ruH)Y?^1uTBAj-iNVN0apC6D;s
zU;RXVBi=TyK@pl#SV$-VYa(bxf!M5OX=CbLhdDW!-bJH=dbSgebQgfg!A2kv-5sgf
z6legGNcf+?6Du62_x=`p2sDNPBK!*%y}1?&V}*>lVRaw}!;jwFW}@z~PYKvzMB9So
zVn7I%OduVH8G@S-k_70Y5gh@}62)LvGwGy7G9iRmws;&Fp~IB@Tnq*&_>su3Y0xul
z0`NUiI)a8HP)~ptKSI1f;h-Dx`6o86l8&ty*w({#;OX^q&zlB2!0V7j0k1?DmRNu;
zeXxVNoD48y#4KbLnjC6)mqc7UXd|qHBU|Ge4#OGI%)voO=z6JRMHMnpx8W1f1cb1P
z!6-?UqP!ppe9&Pm-h->24RQpOlc8P(;1w|mw+nwKB!ufa5Sx)s#9|mM%rJ;xsRTcz
z!j}kxqFTiS9!Zm67drw}1!34H7@<fx?3Xv|Wt$geCt<sKl-wK>VkIeLkU0D3jfEw!
z$OaYE6_&)$k*fihtiwhO3qCpzQ!2r<HWLN7!)<}C2P|f#cTFcjPbO?zvWJhw%6o3u
zSc+TXHB?CiKZ@@{pcBP+fpO`@G(;T>bDQy2eZ4M4pX>rYsW&!8H5yA-2ZYGQA?1hx
zi6PcI(q0=i8Qw|rCP~y{vghhhxXx5z&8TU1BKVv%*G8C;X2>vO%<A!KQfPJrKF%_l
zUbBiBU@pP>0JcG$6Vs*D6L4y8>}|i>y+kLQ5qL{sTf%On=0T`p3%oNL*lh_83(RP3
zjMlL}*Y`}Y^a`P2s^P%GBi>FSc55BWh5I(k4j6zqVCc+acuJSo&D&`+RAiUXB_svf
zy!zI)FZ^E|+w}=>l?(TezdZSC(C@qH63sMc`(-CEuy>-fI&lVNx7X`oPiS16%}5E^
zR3vAp2^B#b<aQFi;k}<E0)SeF^h-KXsjg&Y^(E?DmJs}t(q|4m2V0TNzk)@it&B6<
z!LDdl*DC%2vZfnLtsv=`?45~qQOq6?f`*lgna+L!csl0ZVL#<z>?Q<MJ4*}6A!G&W
z&}X>2xZVe_YcTnURge%H>@N1((a*A(!{V`tf5SF1wxe)~WJ!@9A_@f_FC`vGMuITQ
z9So@)G$P!F;VMJfLM)Cu5<OmGBO8ac>04Y1e6uy|b9*u^7kyLlX^^QU4~}bV=Y1xi
z{MDE4d=UzZ5IpdMjTQzFc(RmMiOHxkEb>+?Au|9D<p@QE(MhM>ms~vJA|tv^m?bKV
ztwQ%&6`0Bv2paNuApqjVM_6hWncFlXPoMG*zSfKiyRT&-WlKKZ-~$sSAP!(1DNQ!s
zX_lbd5GQ~oWtPkmu4rev0e9qsPdC;y2xO=v(Xh74@HPwc{$AeH0yi-Anzj+8Dtc1H
zC}C-8ryC;|b68i!!V~}Ri>Td$RamhBp%9p{<-qgq$3aC2q)1D#kWBgIfUZ$sT>JBS
zXLsCZPu(m2EKZA+Q{ucMtab-SN`u!6Zcv&y$qW$9F(#uph#^sW-G_c0NFPOGODS(1
zZN%xp|0&doRWggaBkOfgd<>WEEcmTGQ3sRWTC9Y0OOg`&GtY`HJ3d|T>+9mwrW*iS
zM2->E4t}L~E*&30f&fP_;i1e8zh;)X42dk)N`)Kk^V4F`!4pU7(S|rMmMLI6Sh&32
zz#DWyg)LqzfX1s61`eFZ;)+>T+RVGa9mh8*2jx9-4_Wdmr5f@L{KGdK)<wtwIG6Q6
zMrtK_P}bs+f|;OHD~XUF%z4@GP4n*&o$fFEnWi4qFd`|oB#$yxv>3?Y)hjHT4zrA^
zq8@nZnQahcs?OK|<^`3_8dAJ>Ip7XL(%><F^+T*t2eOPrR4RcX3!nJ87bf!MJ=p93
zLl$!0Myv;+=`e*Wc&<qu2Z5Iw75i0u*wP!Ohl0tOUIq5rEKLwb(5$jWL9I^Jxd=;P
zh}@)YW+HqVD;L&zPyF2r!4MfdS5y<7sU}s2lz1=Z1gS@ugoZX}8enVzdL#lz(LN0A
zE>ev55dp>20RmUx7u<0OXN>PEm_z`iz3C-<<Ax{)FJY<%2^0(L9A?zoNd&`yq!K9x
z7yARH(hy)<3@6#t35(r7dZ3QV9Y=mq15(6Nv9M9Ed>wh4Z`a3#4tW>=_yd3;LE6MF
zS0TG$ZN!Th=p#nhPg)!CN@o+QOD)qrt`9Hz3t-WTMfJ$hMxXTK76S$1i70dw=z=z5
z@A9PKf3%}7D+`)(NLC7^UTfTEK9P;A?ZvDBI|VDnEeDECKuHaXm8#Z6c%4M_bBblp
zK`k^*)l|V}S&Y<MdQJe~ZfRsJBGSUKw_c_0DRGlj5BNb9^MdIlixU%9^m-fMl*TG$
zy-2Zv98#kj=w_>`gbiU<a<-_|PSv6O>HOVa2Iz5hATPM_IMuxdY3e|PyNl(<Ey=1R
z*ZtqCo@E9G!zfrT;}OiX3OfPjxIo+S1m=@hi^EU9-(&Si5x~S4%q6U$AVKYFt`SKY
zCuD-}GT^A0_<myb8s2;Ys?OAF@S-H4hNxS_UE19BMucR`mF67<$wtOl?MUlryclb#
z``Rlnp)Db`d`ydNxP;E6uo@FMp@I#Niz?MFC*dv@iqXIrr%PfqEjU&QTVgrdY_cJu
zc!dti_7ejYB<FSSYgO2XpvJn0h9ygYS$q?sf#pq|tbShooyn4D;4YW|mK<#+R4~aW
zh4rMTin0TJDYE`)o#0g12*i}U*|~b*rJ+Or0&RZK1=Ioko=psDS6TtXo`sF5OrALa
ztbriX`y&n9CWTPZQxFhnDL9jWy4TQ4)Uz{ZMX@A97O0~p?EdwqW*e=Iwm9`FI8}^q
zuxYw9+1S|NrK2<@9CmLswR`mNj7`{$B5;Nnnxq^nbadgUEiFaBF{O0)@JwTYa4JlP
zR(i*1d3<xyvE_B6ap(R-v9x8BoD{TY6}5xX2QY%KMLu|j;=~RjKO|(Ss$~`Gkp?Dc
zY!`<>YwrF_pRFC}o^B8pTHM%ppcJQ5jnS!14I-;}?`*L&8U@#wbn@YbDXkl2fvWEj
z(I!qNAGQQ0*wRKz?0ma4MO0LA9Z1y?n*<wp_uJQ=#$NVk_A1OrM#Q?9NFKw!8T-P-
zpRq!q>l7LUh5SEnn9eA9)}W^OSlB%F*=rB5sw=FAG44h8*aSZTC`K>bv3UW|b8{p-
zX!Hag<le;tTXUGvX@Dbkfwli&Sk#XHlP|74wBBoZTC#}O>?^Q~Md&qn7^Um4eO8g!
zgvoIq`1T7|jq9`Oz$2~qO>NQ(dN`B!w*5A4_rYNWkXYc6Rd|=J(QyJSCa)o?XU96c
z@8o^y#`FhfaBda5bM0jUgoHo{-x(&TB#QB#Q$<s}nD_3Ewuih`;WmPL{>jDFxR3qh
z_zo?&4gIX}1b7p#zqv2|(4$@e5Y9AaZ*05kxEWr5`STKj197zRO%Kyh3&_H@FlGP&
z9yK`ftI)|AA#8fgv_Cg07|146Bcx>-S5}k@uj19PEF=cl>+v{}-#q2M_G5U?eb|PQ
zZC((f)8GQUs^EIiQVf+sXmpn!A8(S_8$m}~^%kAK?+3kb=ifaat-XoXSf&83Jjg5I
zy@PsWVJHGOx={qs;@~Wrac49^N#bZU3^xd&>NOsw#BQX;7*s}Rh9Y|uUE;c-SF{wR
z0v!$`(nI*qyybxjl#^MaJpMHFc31z#bUFw8poonY4*PV2P98*4B1^nCwsDHk7Q$B=
zle|h65V4Xdmc^T9OzpwpN7T_{am1pN5KES#|BxYuh!!2<moZJq0kJZ^2UtN<m91<r
z-^@tr^F~DUfXq243z9GYjZ$>vho6PQZ#(72ToL{Pey4CPffDtpVGyF}wqCmA4O12n
z35?WfN{a^p_xNBEs!xCjFM|PGgO2c=ATZDcybxGp@fotOH;G3Tc&O1w@ntv&!v@H<
zeaw1aTmJ&UlIcSX9f%8W@j-tIQ3r|O;0sNo(4sgk<_kn&w@-qQX$%XR<j|sZ*X}DR
z?5A}IHcbYuAs`<4aGIS?q?najhhrE4=P<&69UXE83ZglUNb+gQ2cAd$TA*F94s)Az
zDoFq=+m)k-u_7`Qh<F+{(-5f!#>wRPZrlgzw2HFv=1Yzpgp;Zn1f-$>IeM;hh(g_Z
z23s3OWSEb{NTFYge)n@%6M`n>B8H)@MoS;;Y3-TN+x0sZn_EXm2@6X-^)x;Rl^`2U
z!e+EDe#CtPO3Ny*VG?r})ztdx0GZ=cM!cMCXc3TwHIIAPPp!gg;4}mp*aLuAbo$-j
zSSPznE8fA>;DQU80VnDRHe{vae+($gYXN3XAzYiLUY*j3qL3$40&&<o;NijyrEIhg
z0_Y$gA~F?X7qKo84J?u)EWErIWQH_8$G^4YcCJ42e?5oS_)zAoj=ZfWeO}*lHH$fY
zh{MEN;*|q5c|zAG&3g2<zJG)z!@GQn=2_BSKvQ2N(TAM$4J5ForbEr}df<RQ%r8A&
zH)HH_5>v!lVgZFVvm}=b_*?a@d!G&PLoCm-KiK<Naweb5|HQcda29{5_gejp+jUfO
z{oJv0{qp`}N$v7wfB5%W{&?`?%l`21h5`Qd;Qx|^_0%#L>c++XKP6E6itYcaz2CZZ
zV*B`Ye^-&1^b+DMTghXw4Wv?f2^&?Cz!k!UHHR!Zi_WW<D(c)NCvBWD;-uPa>A~+j
zkCRh>?g$O18qY9&=_j5$RY<2XE>gBw-)e2zdM9WIG3W(c2fkjA?j`bKO_WZ?qm5wK
zDEDeffRmDhJ0il2ZG1obNHv2ZM6t%f4h%nha29=bs02n}5f?B^FcT^XX0f0F7f4PR
zbu5#%BC86=7e8U4dV8(-&HwbnY?7N~J@)f3zze>)e6}S430Mit-=u=ImxfeBq&G7b
zSDFauHLTodBN?kU1rfj;1>l8iyo`bZ6#MiQAuJ}Dn3Tnr1RKEk$DA|Fy-v-0!!Hkq
z#Rxkw@jBxP&H}-Bt!D!f5N#430CVB16(BBp-LMq^7Eq04HRW<wv_Y{NFaZ}buyl&O
z?Q#JQ;Gy7Pl^Z~PG5gTCy%k*RCKC(gODH;<?FB(5HP77gMZX>prSGwsMBB_p28CV7
z)C#ty7$zKcsnm?rv?>9CDC+AXA`9RPgHx|DQN*$*s3>ua1kctO2-KQh3Bngex{@t(
z-u%#*nVmDg^dKC?rNnE5b!;(2Sb=);5qE{JvtYgRX_ln8gewc94@ATd+|a<g4lSS8
z7%JC%xQ@15U?W_PDSji7OSI{HB;XE6B?<vgQLiP>`;ZR9>3#S1ui}QGQ}KzD^@;io
zMqw?^E>RNk5)USJeZp5;z;PH`nl29~$%4Ox=~ZWozI-TJ&&GFX6Rlvp8p8`i?W(>@
zfdKLj7=EXRLaiu_%2>>HP(K(l&olK}Snz82cVC_0m5L%Ao(fWneDY1@_oE#*+9kt_
zWyGE*Q(#QkE$qSb2Dc)BP}T90z27(Ycj5#X5v!!UiG__lUq9}oyCP$W<hSK5_=4=>
z;?d~rP)r88o%w+6-q4KDM>Gz_d`L+<w_r2-7*BkmxE8MxY3p7o&Jl%!XTn^x#R4B&
zkYAfr5CIKiB3Ml?km7iV^$E+OgHM=WNSdUBY?dSknQ+dazzh5r7P);os|;22^3)ZV
zKA-KbG!RaJkE?~C9*;)gff51g1cCvUQT6=K-Zp%|95zXl?db%^_ZkRs96|<gF!g;9
zz9B$waiMUA1$OanQx(Y*_9*nx#NHV0)@OD;8?rPZX(iwXtd2Ixp&^@Ce(aQQ5Bq#r
z2Ol4qz^lZ}5^%)qf>1ZH;gMGvL&h!ch+d|yfJQjQSsAip6@U95OZg%qs5SQ)Bris>
zu}I?cgGh0v*P+sRAGrd#6Vhgjd!qWQ{FHg_B_@IW{0{@MBq~YU7r{h4qu*#di;kjk
z-y6dzue^P3`=8gxU8hvcP93!fHPg?L<l*>sG+}C(qJD?5WT4b(M#pk#K!Pa9<cAI1
zQ;-#tf|?dV_w?SUo6YsY7_q<ILtm^=gu5xsVGQA;20_eI*iSoIipZt$gt@R3FNxO)
z>K=H^Bnos9nR0eDR}AOEg%k-0yChw@Z7rxVbNWaBtBbHqAk7UHeq};*2%C(eu9&94
zuV|`dAqiYfxby)U#D#rGF#wPF5Q!wAnl&8mD_;aR(Lbp}IAkldQ#0Q6|Mv?d7R6vT
zaYDx!aLsH8)|XPyo6tikN*WWGma-J+_L@lGA;z`30b8xe@(^*Dc|dH`C3zH=xY+KY
zpYn?1l1-|j9eU-;h-P=9*hh_7lRzrJ2#~-z=qobNRGkt#tYxV<37o@U3Ewn$=9)8V
z3=&>?bcoU-mL~Ml`XnoX0!KPtE6_+WP8|oH(MJ*pLiTo^N~<1OoUoEvBsr0qWppqX
zTxoA#m2x%jiEFbzD5-bIWDScmOcm%I20VA&=8H?hy-0{O!yO?XB0vxx!|#(%SKKhD
zPsoEs&14-x=#RZiOPf9xL8a_BVlSvJ7owz-^+*diT^s|bxYddg?=YQNHCbczcBv|-
zpq4PeYn@vD5%`Znv^qt36h8CeXE}Jb72sD9fycTO9tI#;&pHThX}r!7Dtn`SU<Qn5
zSG1(~oE_1QXmVXlL`$HK)Cm%Lz;C@XSraAAt?|!BaSZ-q6cua?U1MQX*bnhF{vv`0
zXvh|V%wEVOp0$HO2&1a7kz>5dkXQNh`0M3=QNeX$LkEFLw<Wy87)2>yOgu$+4_^~Q
znX{9@3)j5s)hIXK*)he38l@==DdLfeS4F8IGL>1+u2o>y?~Xcr8Om?*Cf_1E0GlO|
zVqJsAL3f<(Vpz-B%H@NBkV};GZcrVVR*&OP#zSFo%Ut-1xbV?mdj1rCg^&Cyh(oS{
zBKc>{K?m+MH+MSC&1@<;<cAls+zzoT;Lx880#d1aVii+NP~cwN%Hw=aJ_7Bm1>=Je
zC*6^m=00H;7fOHe^8g8x!#K5xUfA+pyk#O<3>(3#wl;=WKZL7?huS`16&r!o(b``E
z-XNx;IkRJI6v%~>{r7K7SMzPIn=PMWE_5dKvQbk1D&Y%qq4BYI6WZgx0IiQU<L-k1
zEXD_HNVLcCupZVvK^xUC6F0<eJ{UoGHBmr-FU@-wc?*K~w|MPhE-AdGwj<tGef3r>
zy`2VU)8Ie05E{K~<q>e=d}~D?FmKF=Vv_hw)Mfx4bdNsUgR?E+^_C8TSn)0yutUn$
z1K%ZRGUgCW{~VG*n1};K6a&NVPV-TNlTV(Q$+w3A&C2et47LidulkpNA||Zr>o=}-
zWHI?^rVEl12$7yX1pH9vb3xvNSRfLfVPa_RDuoAQP$OJ!+-^{alpn%AI;_Umux@^C
zG?7wi9%BMH7$yrk5q7i#t_VRos(=*tF(Y{A;3R%vxWh{@?k@k>rQyD@k*${%#%_FY
zXk>GPX9%ETC;@!*MZDfCZW{q-h?O8rhwvj82}`&Hz?Z(ybAmFMc_j7q29>3Es5K~K
z)Btp<pfY-|iPer4kU5y{aIG0dsc-?cEdIO<wSTO}=E&`MA-8<s1sV!?8wVh3X`QzN
z9Z<1Ru#8;!CBbnH76}Bp9BkOqrl}^J2U?+!3*li7jo{9VY>lRZVhYsA7#X$6M@BS`
z;uc~C48>@GjKLoF9Qp1=zKlADo)~+%-W@W{ufO}}ivh*8>BIp?rb9l_LCHu-=nCQa
z!r!L#MxeNjSXt1vupWSzz^)Oho*WI3EBJgg1<Fn6CM<CM5_;m~2)svM3m2Yc6uhF_
zm_)38!k*-T?H{A6F{VJ}>z^CFhZv>fpF)Sr_-`$-%pqNpCLULRXBx;!DKHPxbG6@|
zS#;Tl6R4J)i9G$gmXBno9NE(*>c_!0l+buGKV+p~-GGy74Fmh5tNNmoLrK@h`^I+8
z&-<5u{a1duu1|Fd1`&0o2Jtg6Yw^7Z{3KxG$k9V$mV1t=_F%^c;RNVxq<5~him0nU
zbT#upgEB?k2_(Zf1p&a8s7AvhJ{rSQz>gMI&n<o201dL}e!ap(@z-xQ;uErd(@zYs
zN?T#ts83KAqHDpY0~yK-ad5wkC-z!cNaLy2P{;G$n})^I0vlmJ8~_145G4SEv8OhS
z;%thC)U*sDY&~qDy7|0TM_$gVn2yEc69fngp7_US-5LjQ4(kL!XNc`zqI~!PnSYqI
zfe7LyK(&PZ(!^7!6UE-m5(pZ^44`Wc&*BX+)QixbS>q8?2~y;6DuXM4esVET3h+@O
zYGp~6ChvY~YBu?Mz?x-1&wa@|=6BeeYL6w+HS;@Kx70pfF7t;LTVwCp8a?SREFOnw
zUYhp)#NzKK?oTX!c>PO+7k%@?+23jW=6`tmc2)Du*5x|>V*b|DKYam+2gK;jFL`+e
z_59k)UlV74p)rGcK6&2;$k}t#{`(RK^{jT(eDgzN?>V1Xp&rzey}`Bok4Bz^^zer!
zw~xQ{mxgXv)Pc-EXMH)lRLcQ-=~$hndi+0TA|`!R^A-b`gpGyp0K76X43?8b<>#p~
zH`e>_>wop5dFDz-tv~VsPb5vYQ>N~ogH851lX}n!u8Rqwm;$aa369P#qGpmJp99cT
zIKa+HF^Xb7e1zSK{~9l$9GMEHxTT}_P1a-dgiGwK+9U+dDaGtxPsWWlHkn~Y5UHbm
zZDR%EU?TI1Jl~qB`o!7sK^NTO+RzBg@4Ww($M^iOj7k~uDV#G)NoqW{|5Hpx_Ji>)
z#%1I1=~gz)8{>wJ?nz=HNwU-MT$zFFwzHELEAj;&$eExx6@=kvZpxa)47FP1<ig{_
zn0*Y7Ek6D;@A3%k!BrvD<$+{RlrS{J|0mD_w1YQftA3g$RKuVGhiFHb_psg{D?mS3
z;wy~al#kEEx{6*#65tbm*~vMgWb;0U)SsdNU<FkWoH9f(K{a{oE5EBAE+%(GE&3vS
zAi?6r8V{T7lNh#mi4Tm|)UH8^Ul|`@>yUWE#@;mScpw}`HvDJ-uuE@p)e3X$r+c>T
z40bxMH&^89S3nx*_$z9SxD8VFTKPi|2w4-4fAUB9aFjp-T$&BO-M|OD+HBM^c*VvN
zAJ!>bzTTY#W<!BZP<iO=?h8)C*K+<;g+W2;<}9E9N~31L(Z+yb{76omzz6xNa2eq?
zH7FWe^U2GG;sbxPD{7!-7JOA;_%6ffCL1Sew|TU&c67eliQ1LjqhT8E8lMY8wsm(!
zMD;|ir8`nSN&|;2P!_Ka+xoaZ4YX)#{%pI+Mv$Eo=7dqlj%kdNr)7i?E1I_o+lN?!
z!hKZ~Yz?GgXz?Alhp)9yd~SFuxSEKm#xULHRXdQ6#-UMfiA8!A(QPfo_mBC-D_=Di
zcdWfXITYO-f$Pj~Hit`b+a$H!fK^RD!FeDq&Q7vjJ28C!ZU9O7&E^4K-1%huT1E~u
zXh*4OE(ya|-C2cSZOgDMGSHYj7=wI96-eL!-)&eE-@0Ef8id}D@2Lb0kR9Y!U8!sL
zM<QPj62J~-ihR42fHGbzpf<R@=mR?imH}poL76kKs35=I9s*!w{~oV6q%t8&(mUKE
zW=Ze<HHpq@7Q8Qg_Y!uq7n$3XVR|>LCGyWR3dqw;UK}fg3B(8l0WYB#xr_dFOekE_
z)T>`PI={O{pcHTq3k>*aP;dXB@ZcDkZX%8HoP}XXCje8<&H<gVR9VBApc@~2_X`qe
zCpkfG`W|Ja*(!5~n3McTiL{WC!(IwcAzJ_mnZ~t7AXSA-8}8vb@0D|Lr3w#jj_~(=
zq=Gy>&@_eahxd9n^KEEF8?tV*ZB@5z%p`S<dBs48;}8j8&oOZ!SK@y`?m65Of$ef(
z4u2CgK=t3cKW@hD4J^8trm=Us9_J&yZD!EpZ}~A@IWlRl?N#(goatXmW2mE4pLeV)
zk}Q!6PWMHwTJYw~T-#%8<|tV)tQK?aCa`kVXVN)9%xQh<jt`WM%oHXjJe)s|n|%KS
zO=5953k&S+w8cUfwPhB!7=&v{Y{hU;Gt6wlbI^Hn3+^LyGy+*P5r%CPMWKmw)bK)^
zwc3{U?Q?U;bvSoxja0Y|#nUZ+3f|H&uelfM+H2b0WQ~fveWtz7G~0KYxLxO(9!Mx$
zVrfY-jKV`WpsndQp$AExLkxVLmBy(6uyBK#y>)cov>%`NL#a}PqUl!v8r1xpB&C?H
z+gmBjRSLK9tfHR0j-W_Zs{>R7Z9s~AzbB>Wi1uH_8~%4jsip%1;OKHONp!u&Ao<_>
z$bpTOD;u60J8s|Ro78<p4T1$T;M&9*LSB9WSV8ByDrmkQ-xXKdh4wrY`E%_ygV~<*
z_Rh8E_L0BE4F<EV-BjqMjs%H4&wJ_TpA9%-ic|P<Xe}z!YpO)S!O9S*5`$4%m-PV#
zkerC12wb`qK6o$>mchU~xfjlP)X#zh{i|7Y;|dU|^zla@D^vnUY`fB^73K@5-2_UL
z!tHCAKM)<xnff}$46bEiRBWB_S`{E8Z*>4cH=j!z2$kfJP`LJPdRH-xwx+^f{<)F3
z9Xx3+ytO@6@aF1|{?LoOW*`WZF`8Sm7frmYU1`&g+pTiS<Aq|4m6F+p7YNMZhC@Ac
zGr}~h5Yuk6O{38la|E~vMWnoA1S4Xbg)44&-o!oW?gn9ym;%8fgJ9d+lJ-Kav966G
zUN=ho3?KFTDl!?{=Ps@rUDXE2{m5t?owts!UbE`q2c@k5QhA-1cgFRtMG%{L^Ho#0
z?M{TS-7dFx6LX=z+0b5nr<sdK3TC9xuKbn>_wHR>;H9y4ZQ;&1zKyYO?&hFA?l-rG
zw;nS8=COUr#MPgS-)T_Wlk4KjyW8{Z1F(wE+1vd24TbrnR%)-i1Js9|0{#R;iGEBG
z_eyZsd@{PFV-k}R!@EX1Uf{=wpeZl0W<xR4ckZ^e@jY>2zV?y!zIcRB$KGkS$7}Z9
zew$&JA!cIlBVgI=H*=s&tJ-_#7Jn<=Zsu;QeuVXBWZmBVx0(GTx9@E;ufF<M&kh?C
z8QN2_Rfae&@8!oX)CBPB2mc-sk4I{S#e3r#uOP3rG4NB9J58+IYQifS9Nhn#6E>--
z$JE-cu8^wSKV0~lt3$^ocU7X)JL=qT!s6O%O5DDjv(nD5y<ns>HGzLOIgaxzAN1GS
zz(K3lU56Rk`ugE^Tfsob7VU=pr9Zulz3&Gf_=QDap=)>F%J1j)wnHLyxVOE;OJ(Vu
z)g^s=dSqM5mxKhv+`(o%Utl46YgM$QNcO;(BwSd#@G&5#OKbc2h|s-<z>ya2ZMO@5
zdYPFjY~O2mJM1#TvD&xQN}p^m>@Q`-`5JhezZkZ)QTrrc1=`lWt#B=Ssx{MTU;c^O
z+*jL$A6vHya&~+Pyew(xqv9Y%&hbtjPDLQ!5CW*WzQHHNkG2n41sUv!^{L_VLu|tA
zeBfxxCx!Hd@l||9*}YPh;&!v6(ff`zB8rOVLp=bRNfCKk8_(}=kF1Ti<Jc2jRdA=b
z!4}iJckf;@fAzQ8_r$wV*4y`DCv9)Hd2$XGH}?wwaqpvTje!wfGS;5Er*=E>Mt^b1
z^~vt^jgKi%$kR(&Bc;cgVaMWl?t=p4_@oTy3j}59li%IFj{aZYbA6*Q|LBHauzaK`
z#?J>+;oUT_A>K%_bVU%w|IganK*e=sXQH>tWv84dd2qX0xn_vE?%`5g{)CK)SGAwt
z40SkFT#5o@Qqf`*jaw?05SFFJQiz7>@tf4Wb*ea^3z7-#A-yyc31c<!bGI!*I&@EG
zTA)HM*~mYHc#$5>i=|*i-SMoJ6yir`oXPtRk~^KOet&B{Z1Gc7_ulif&pvy9``i0G
zRfytTH0W?J8hA8eMEWp-C>tf)9)ZwZ#{|gFT^9$0GVZ`y6No;^!Ek4U3Pz8>sObV#
zo-{Fn_9GH~%6?JQOqG7^oOr|hgGu2(<vvt)olP@IZi)JAE-|1yZUG>SP4Y6&+wxiO
z7c}1xINE%o9e=hDEAAZ^;LUQvk9GrLMz|I?MpPOtxYu+gx{n8C%OzG&K*^P#G#n@k
zCg6ZQCY%pJ`N0)uOY!DbUpTsAACOJuwk){=ff1NZh@6H`eGO7G^%#gy*~Q6n{}=w#
z1DR=tIz*t%08<jU2UtOBZc~U3UJ}Ny65Uiret-g1`kyhh^t!-cD`QBOL^XSvn8kyr
z)T=ZD@WI^ywyA(`AcLraB}r*z3$h_)2cX)q)qC;)MdZg8Fanb!60~_(aZMyfj>(T{
zd_<1&i12TXG;FPN;w<@^j_H9w-Om5fZWf13E+Lg~IilE@``n<I=YCYJni0Fju(pLY
zDckYVS@gul{Gh(5UzHeGw$uU<r`ZRD9ou*Cf)??eEoE<L2r)`X6e|x+vd`i+cs$Gv
z$tydFCI)q|tDO>IA}a*(;j`j4BvL%D30YfS85+h_K?xQ=eEXySu$!TVlT25$k%;()
z=z&+Z#=!YSLv6bQmX_jlxXMddblC&NR!eC%uyX-d8bY}%uq2D}oIe1D`>-;jAmH37
zFW-6vwdaIr#(t09n&x#(h>%pGG3}J_2hWKQ?PCIJQ+@{17DW6z=ovz@<Rk{)2PYd-
z^#cK}p@SU35&s|G++ApsOfuxuMHDA*dzS{duVgg_40VwEE`o;mf(x!f)Tg!KZ!Ow{
zy%Ss}h6%L*O69-=k_C*^tK~~R6;nKf7zh|iNLvL=E^#&(ztvz&Li;`?Pz4DK2G(D0
z9{gPaT><SA0FDkTkM0&w-za)6QRJ|I!dG&W0t0-oIbk5Aj_|Qh*(YSd^OA|nN~?hW
zS@xgi1q=^1<<cXTvLHEp#iR*@^---*&tx1GZQIScQc&P)W90xgw&^4Uf!A6%b;2(n
zHw^d+-%DYua|b69+omLDUbiEY6pBh22D~McEfwxSb9-)o<B4YB<FL>`We4YJSZ-32
z$bxeaD?l0u5<=zPgPR4h=k#m=Wg1{W-6I)QK>Go+ZrOO5KFw5NwSzGQTkRsx=sK!p
znf|l318)Kw8JK2rKdZH1BnwYs>y7KM*P$d=eKJ+<sT<BQZS`@9fDJ{C-UGmZAN{ky
z<G|1UeF})xXzokZTUCSpG3FGWi)^ur!haaKkD|@pL(%g8<R(M+Z(`oN$)9dfl>QJu
zcDO$Z|KU^jZ-RDgajt$g6nDQRU;Wa(oBZ+8PxG99(vrFVZ!P&pH@Q~>>2JqqTsCC7
zAAk41vh62E98ACa2JL;T?w)n4z$SztvGp<hwq^d}1NVRV>@)X&nhMI-tbY-g{L~xl
zr+)vx`_=qeZ|?u$7FQq_D2I>xj275dK%R?<s3d$|TT7INwf(f&$Km?H+Tw){(0gSC
zV2&Ibm=7T5fOQmxyREh8GQtLW1oHYHf#sip!wxX454?JK9<cc2JCHL3JXDz4AXt^4
za3jb>s!aM+f)4;K7%qLP155_sATX&=vm0`{OSHfp@s(&Mnu5ThY}Q3#w>(^cp)Ah`
z*pHvmpmh&KnmK$+_z-*?Jw=l-j5e?X06H>J3XWn11tUP#0l<L3?SAPi!rSp;^xu0$
z9tq`Bb8HeNR?{u;t`_hlWb(q#1i!%W1if&Vfdpv&HY8Ah#stIwsark}t)vb`4vIa5
zFcdOz5L;DT1iqwi#_j9_(h<|JPht&&9-h$~B`p9hf{kWzG`<Yj6&k~9zZ6tO#e>Mb
zb*WD^6Y%1EjPDXVcyppJVuLHh$wi4>euz~_ikgP-Geg!~+GarVq}I+nun_bBL{Q<H
z1;cVYfeit2vqiqo4z|er1b`Ga+B@Rm0-pdQ2S_GH%$7q^W@<BPR_JO`94$&zgfk9(
z$55KWS7HKz=cZETL)m)-al7R+*(9PlfC^+)pB7NQ`mC%c<PRd&XJgW^$+UbfP0d_d
zs5PF9H=OY*rW&SUppzMIr^u+7ch_u#=>m@vdJD`2l!-Zj$sD%5AUECqN_&Z~#(vO_
zP6n1KlH^Fj3T%t);`V-#u&ixbkG;KE4m5`KfS?fQTNJ}OaIg~N#qyR2UkLCPz$#%3
ze@1@>6PW-U)VQCTkzsMJ4D+-g$SzaShROWoRG`eEriYwu%d|+@&YG5Zc-Z!rAdrc1
z2Ur0k8A%c6AjHms(9G-s@ovp8GL{IG2Lex8AXUYD36GluP_r!u(`Y-E$aa4|!9DE@
zd;Kx3Ao7~<<@kb?Ex-%IJqz2hyco}Z4j(M?!iTokglh_%#EuqCMkLAVQ2=J!i&`Up
zd<JByOK@_p+vI<Sy$Oje1!qEfw<l%&4|hTE>~&i*v4-vJg67KKu^`~ZjLQ?pGk2f(
z@7RodCFN;w767hgP=h>aUBt43k)**fwf0+Br|_q-kdy*EX@=xJ3&m(6L9fFY)*@Ut
zGXi3c3TRm?!}ORLNF3xE&bbYjE$dO>abuyE!Q1uh0!jx85c&H?U}D%Xl?;F?Bm@EU
z33{?dsetcu>Gv%aiw*(QobRFqkIwWoHv5IL%K(6knkQaG=IKOWkHA;VctkVYS`bt)
zt|tLVLYdhafLPc<LDY~Gf?+I9<Ru|XQQ`+^&+q-&LjV=Gu#oNkp@>W^LQtD<4klZ(
zk7l@s1G*zV#r0t`w0Y3eYG=Jzl4tLE-X&NcUV^)E%mTq0M;K|l@Zvs*ZD6EKoMmn5
z2ZRDKkt)De9E_*(h2O%vZN6roLL<zHC@osKFQOm|w%OMPb*J&R2W<-dJ`B*>$vi4F
zEYYC|zyYpY`gxO?ZjA}U#xj8XgoWnpw}THma=~&eVyP&>vB4w#r=iX~fW)`pgsi|c
zG+Ud6(Eh?Ajp5<cZVC9|Py-c;*iivb8`)7(rKx8Fpl<rC(@ae?@g3~L0>(V+Z<#Fb
z5<bNO$mCd=?SUr2Mm$j0{*1?w;Xo0@?4c!-$~f=^iO`+Z;7TJRBK(;d%&I#BlsNOS
z$W|Ban!*46AO<7|M=sCNrK?sXSPrkIkF{IP0jrPgD(ouo6_Gu{E=^i3qRA~w+w>xA
zB3p?7t>;#W;68R%dn4ep81#5E!<Z_z$)U0}#RPJq1s|4!4do^A;O!EKf#_le91z$1
z<a;}P*g_(72vHtikk3E|9N`$dfImMS2>z;|T6eIVS<~7sP92&x4PojCfA~bk@0!yA
zew&G4=>&fxDRjdI(4sPB5|$Cc(=qlLj11a?y#`gGgeQ2w7Lbx=Y;GQoc@X4L^Y&MN
zCFrC0ELSW!2N|SjaZXPnV+LXfR4t)nj^et`eCj1%uu|6nJLe3a64My$dmlw$#2*DR
zWO~phnEJp61a=P_Rv=^?I1J!eEHMX23>s!)0MI==EofRZn)7epR9aXQ!}HsG7?nIP
z3I^QI@>_uN{Vl*r(TS3P#kj``-eR5zmI4+)1W1?yrkaCT6wv>YX?x^F6OV^i0W|!y
zi8Y5b4;vaAS;Ii(?t!?HW`)iRAkx7pP5IsxoW)8pT@ic1iJA)*l93Tb21us0z+qq|
zzOxbRoxz!a?L+|X1tIGI%7AhE&B%zy%>4WaAzIk99p^Oq9-KjAQA*nsX6E6bRur(0
zg#+YpD;ZL7J80^#pRhJG2Yc-8h5{zWGK>OKf=3vo3Z?snLupI3-_-{!;|N<^T$C@h
zNSJpXi_p&KsE1V!%>lg9lR>Gy#FSkU_}Hf6VUZ~Yf=E;YA_)EGn0eE?%Ooa79TRN=
z={}3_m#l1v5r7cj$$o{~3VH9j2Qcjv=UAk9-ls%_r8p4CjA8rAP%I=8c|&p~B_G&_
z@SYvPcBDZuHT#0T;G@%H8d|2Z@UV9aJ%d8tZ)?to?MV9vQ)El|Lt+g=VRCA~Ji}A7
z7zPP~W+I#Gk109uv-m0xOjvw~T|UF|6GeBj=+5&Aw?pLj@sSDs!Lk-#(5^JO?U4@A
zWk1Q=BiVnG99(NkzHLRrg~+9U#oxMMU5^+)E(YG_r=sCAJ4DN%mL6s;lYvWha~kX8
zEn)Xm{6gSH+l|D6IMp%hRvZwy0Un+_3F{*p7Q>!lMCtOAVXY<-7URL+G56c!C+$qN
ziGAOFBn(vXMY!1KWKnMw_&XO^#lX#nd!Sx^cd|@m7fk#0=lmm0tj*vC)B5;wlhw*w
zMTfX#hKuc1t7w_z9Ri}2pPqQTC;Qc&?c$4pm*)8Oi1}?)2kD#~>KH9#C*3?SQum}i
zJfNkE+4;bH;7IXpdpvt!*wz1~)e`P0V?F$(@N2_Aj7)`FzM~y}Yd-sO^$^Vt2IeOn
zdr^Sf>poy|NvX?feU2H<{DBMyj~qZJwfv+&Z*6S-eL}d^#mVdyxQ%=mI}&(&wq0gk
z5PJ2DJ(;zinA|ZF+I)TEB5yN%xm9MM3}l<Z){67oNW&9sw<t1GTKs&p(1J~TIE}12
z_ic-6J9w8c3g8LggV8l>o=*q1|I`oUJmNBdm-sHPGkiPTOF}wF?ben{!dqr^dFRhS
z&QWn6_*93@85!lqXMuVGSamK+>=b#9)e;N6|0#))Hsjw`{++gC^4=#ubO4Y}>i_xI
zl&*r|i*zyU*Ij^}o*%tM`vN<{UDhq;H@bMAg}leE#HWBHFSvIsD_(c!%;dX8fA)QL
zJ@Fb)s`By<7Eg+f30(c_NG%)QOtT%4Q}(Ydw==cwPJxfitAD87aox7pQ0eNJRV>^-
zQ$EVc$%?MFJB4NIiQhbPhS%IR%`pyG<5c!Hhi68%pL_I_5Hl6IzXeS79d+mq{*bwj
zd?$b6uO}r|p?>WOP{BKsKvjU)n11{7Gb4e~FfhR#>g5@MHcQyzT@c#&*+)jP<N$5v
zEMRc|Yq~jEph%IU%>#`4mOkYL05_WjX5DsyQ{*-iZhH|!rLTi+^lov`g7*6{TfU7t
zSjAhc&eu{bP(WjTP2zU#unI>d%Aj46=;()h8kC?`p|nqSF>~s%9TQ{xwrM7`>Bb$}
zi0K6;_UaTszZs|Td11c#7_d4Zf7x&2ZW-WGr-rM|r^G4v72F>2BM%X;mmyr211Jh8
z3&n~A_6&d?=+B)4za;^zl4(YF7h0K>nL#(6DvZ?mh5(O^F1Ifu%j*>PsaGf8O>9%U
zB03PoHS1VG0*jn?CCvB5F*nWjUeJ!Y*U<K|N4Wq_(ZSyVrZ&XmzIPWeXXJ?s{JP~%
zn65QVcC(S0$IwgwWD=8{nNoSyeD!kx;0PWToFYTRLqhr5u-`s4jBmica==Koh;azt
zp*O&clvBf)Oyw-FIPTp3{MFs8H9?!_Wd2<Tvv{l31qW(rgK?$91=RK4GQ>sGWP4uP
z;LOsZ8?1n=x=%TyvL78#{;fqp-?MHdw%M(gL?=fC>d<pc?X|*;Z2yY|$^o^D8t<FM
zsPCVLM*yb2A*IV6nVBh@Dz!(Z8p}L2-XW;4vWJ^zN}c8z;cOAt0N}w&0*(hjOaW3X
zr08XU`mcy*wcEYFp~w}p+ihi3iBGdP+*_85#UfV@2N@(c&sQ11tB8;Zsn?fHqymfB
zG`k&`WR~4>%c|qY+)q)a{v-Q+@N%(sxPgf{=57`W5)u`d1iWKTRdhwZ$gC&sP6XOT
zNf@053l6g-fpZnG?TiYD^HubLNc<cq-UzT&yIR6{%8<<+S>p@2il#q@Z5(Fy*C4)S
z@>4uFBgnt_qleJ^r8S0nH9k2LIWZ3@fi{XL!}Eoi(vlgpc;X}mU$ieH$nm0O@smI{
z2edUNiLYZ@3m^|n81meSDsd6hw>^#F772d7u`ALxO-_rpnaAX*kRvk$!u=|8sHcDi
z!)84Ra~R~hNofM+FfkIAlr|AUR>;dZDS$eUJPd44ITiLr<)r$ltSaUkHm8{)U=E0q
zP0JcFJv0u^ZPBvSvU7<NbH<JP9I-d24>CSonja|O&3S$c`L%qGZ~G88dQV_n+kU@5
zF*CzI07sW}@Uvv6$q^p|s$Bub!<4CwV!;xKb}4i&_<N9q5nGNcJO*(uzj$OuC{6~;
zQv#1DgcP)A#PjF3NiHYc8ASxlvm)q|MZ4rJ5_LXkYAE3mYzP^Hm(Eywbx-GlnSqSt
z#AFO4MBsdgxhU?8rJQ`R#b5I$MRSIf6m1jqKgF(1k<3g@aA6Az{SZ%-v8o`JR-o*G
zQ4A)MH#7dS1%xVuauNCh1;SPpI4)FjbZt>Cyi2H_BDsPkMVal%@d+&m16D~`Ij@7v
zVG#DR9-KZ=EXYDirqX6Qf3XnZYL5`A5-6+iD#Q9DmGS0;aL5({mVp5aC?tPQM`9bQ
zm%-SE-YvDAp#AXauo}GURyDiQyKy7j@Li0=shGiTIXv(9c;d-|cCkP+*c|!w1-$IO
zZ-o&fmm6w4;vb8|pRsdu+=p$f)&f~DTu??iMc0%aF1FuW2)k$rjRTg=qb5AI#uD5W
zni8MNEZ_&^o)5$Lh0(VK-oi7(jo<?Mc>;*3%reEciD>Mdnn}qol+-|pi*Ed+I{a@o
zty!D-_!k%`eP8`;^JWapLdh`vGPd!r+=oX0@K1k|OL~tP_)i&z_p#9*=i~PP*3Yof
z`vB`bY;+F5q{K$&?qj3>7qI4!KSODU4&Os*Kf^|6P0$Qmexq)Sq}cL>+&zT#pWfxA
z_ARpGXISr#KWobURMOw5ufbh@?MtIuZ82XlwmNhV9R<;H+UWWnnIpv%grTuJHY4K~
z(gSGv9_dAq{vE!89{JtGzl>J_SAzOYqR9X8=RH7Ge#a7#@pa&gk`;jbp)b7UgM&ik
z??3D7-jzS=9lRzVCYymf{p54~|MnLJjw6gvt~{>=7!s%uP0t0argEHu?&mRty%&N%
z--fI{&E|HO!;aXl2VrC@Sn6JI7Z`X@%E>_4q-ml$20Vc>FX8~FH3v+oaa7wjDcF5A
zz~6Ko_Ob$C0yh6}P(=w0-9{!IemXdpTDMVk2gmQ2VZ=W;0FNL4?*D>OW7wMD>*ajF
z8Ib+53uO2*2h~5C%5BBslR#RVkFdf;xJa_v%vgC}WI;J?WgqchauAS<XcNfolgGTl
zf#TyiAD51{6A^Z#&xTtDrx$7o2KrW8Fdc}YW)4XAg9F+uwVVBRL;KG)`y-ZQ`LzKS
zHql-9mYCN`sA(FpGjr28ikl(t5tV^<N&<{+XQDvs)RJ<LsIrD$%Et|$coTusW&|xk
zoCA)GG-0^o5^y~*9SFPkiJ&*=u}Ki5$DN?1NSvu)n_;|dgUETRPb#4lGlM{Nybd_T
z_yP+Hd76O1y!iQ`1$~1|7yNiYi|jHelz!wPqNdKOB`Dhc`(A>uO2%t)C-Z6`Lc*sB
z!X&r}P#-V6UAo2DsPtPw&$uSeo;w@KsD85{@c>Tpg9gh08PXv%&2Yy|NU9!$$L5VN
zOBQ(so^8TELsBlmt9~dqq~O>95i(`er!;f#g3>$_p=u00L?IQP@gh-1dV6Zd2XbAr
z!)@YI+WeV^mB0JEtkAZL1#zE{NkqhdQH2C3WTDJkG6I*&oAI>d3=D=%78I%)2<|Kx
zX2gobM4Qjd>Rz+CZXx`h<8{4u-7hgSLy7AwCNoodivT%7-v#+&Er8qXaI?RrO#~nd
zjxTsl4;nL(wsX}mGoi)Lj@y|#pH?c!qTX*aI|Alx0Es>Uq)k!|_UMO;x(>?s@Nbm`
z1b-+qp1?5pjW-xD4CF{_<)-c&uq!Eo@1&sR3P#Xgk3D5J3m{h^zYE47A6Cr=g5;QC
zrfdSp>~m(NCnG@m^Aj7yOv7^)sC0=x20yG>EHu{G<VBM4c8IbmgLFOlb3o-Y9w-nS
zOBtaxF9cQj(9l0;K9uocw78<jd=Q5SU?i`unZZ@3)ED%$AcYpQ=T#)B5F=$Lyts#%
zc}RIn!aqcj{4Q*j5EL8vQ~<LxWWi_*-u;h9&H}wsI7R~Aw<H<%aHu!=afmsdL~#K;
ze2L&-7nSi1w4ym|C_vKz#9}{%;O_@c<G~69fclgj#1ukKV4X@>UFP@6JkpFuHqWv9
zZeKlwccpaVW0^o7;JzALheM4QY9<1}k+zUCE``iv0y@P_z0jNnSE=a(J|~wIv2igV
z`uoaG{slxBvbh_Wyh6;gwk{v=y|*9067<UPD&d}H)aCO*%(Gr3>}MRvuVBEt&>=vQ
zUVXofWs|`zr7o2KdPK<>x~*f4I1D$JU(Hxj_~!`<-MfpM5riRuE8qSPUk<81f(wim
zZsYTI+@pjD<|XJen|-*Q{A%_oI#WzArA$2kEHy2qgg6h;9QP`qO~dq4OxFu;s7>}0
zE#p&87vv~6n-42Nw97)9Xv}*$X%OX&j~+I+Hk0>g4zUEad6LO`qELIyeiNgBi_v>L
z5?%M&dW8pK!-CwS7#T>JRgeOx*)4v|+OW*bzG&<xWj=Hf$lHFqMErv6qY~G>JRufY
z$nhjvyr$Cdg>AAQ|M0anSpV?nz2AZm!vDvwpilXg0ep(#AEXBA!Xx)b42TanBSs1%
ztzg;|nem5r@E%^Y@!6m!D5ognRg54$cK=JV{jiD@MaK&f<?mncN%B7^&b&m&s|L+@
ziPGXPQHjrnZj{UG{u_9}E}rpG3v^5=P2B$M4J1+ak)YxD><ohC5!JG>u~g%3+lepZ
z=w93o6W8oRq@}C%=P=$-fw*gTDIyLAH7Kt4w-=%0@4aO!rR4LvHxnU@Jf!U62K*VX
zF5g5Mg9q-tiH6?0uEoTyOMp|$d)iwUDn^_UA1>U*A>dg@?Xxm|^<U?=va_Ld<wyiQ
z83Ym18ScYKp*t9{41oY=d{U;Hz1C-=Dtn3-VJ_>6j)O`WdU5}Y$X9`dawT%sx&2=%
zN<fhStvn2wxufef4=K$lqZaqx1tJud&HcB_AbF*~tkxjE--yjp!z<tKGm!~^qBqPZ
z^M9Z%j_H5{Gm)(u5TzaN;<gH(%q2t9&poOrrC(5|@O)#>IBaaZ-*5SKBbbEKkLf=w
z#~58yGAiaYBL@Qy+3F-z8-xM_uMjzY6fa{xw53GhKBj!586OY&q{xGZ0_pnf^@}Pl
zz)Z>4F(SWx;Fod&_bS7`0Mf;jH|T@7cL$!+oJ2F>BIDaR+)$B&0DncMv_Wv?>-$UZ
zU4e#uX!$c<xXl>M&+a61jX?Opw^0k<e$RQB%lBo5*u~Oc(dDJ}v{tIs1iX7ZMGi{_
z<E8}u;avrZQW$rvn$NCne!tZ50=y-26wgik?LS-!O@ue)fWAj2<bZD7H$w_$P7ts1
zFQUJI0o`i2DrFv$i5q-2qH^GVY9-)__eWp(XR`Bhm`!NFdoSY!`Pm@ufXgtLN(rXk
z{@!n(@Bgp9aG!tlmGM~_Lr&OFzk2)SzuwXqQiv5qz%$M{sNda~@_I^Td$*b>&tFu6
z4#p%?pjKZECnzg{x4<snk_JcyB)IOOI-eo{3iCF<1wfkPj-H@S9NXJWy}F)(s5qj{
z-(~+IrvI~L6O_^SpZNvLUP{~6SI~<eK`2c5JPTdHSXuI&t!oLb@sYT<d9!ur^ZMOX
z<PkzsEFC+}R*B(j6})B8E%Fw`lS}78k+!avI>$@TRcLByE&bxa{R?ieVm@}az|rsL
zIXuQUMIyXq?1F4#2X^S@FPA>y=%p9PM9VLehV2tNF*^B?KBFtK_W$=oJhiksO=@H2
z)+08rJqFR(Pbethq)Be95nF0ou!y~%)4f=P*cO$DK_MduSNNf#O=#|2SfK{}ko?1Y
zh?wKLEcwZs@}5wd@vWPp(C7UtgO&Gh`g-dx7_k>qtUlI)jc}E+qI;>xONy>6(I=UF
z_V}ZXT4~7s6Lqzscf0x7htEJ+)ED@2*iHEDWf)~ykS*Mw_2Gt8Q=!_|vPKg>xi#Y5
z97Hkm5oC}YP-}kb)`_*$llMP;t8o9`I8qw--hq!-$d8AsR|&~etlP`HA@$D-)f*rG
z7v#MP>@s1K$gj#NR!<N6szRAr<{USYsn+x%qca{Ij3X!-Wy^t9+Xfcv$<2`ASq*qZ
zxR&jpowT|!RZALD11#CwN*mGxbb!vWq%mYHEU|sX!ce3&(rRN^a9RN>g80>oYV}vU
z_c-i0ou%fddDd@jUe32CYL{axp#p7r5*Yp<pAe_4H8$uXDr?P<Y@=B-MMyQF$H@&s
zx=F?ObO&iQBmHKN(ZLV)q^`Qr0XLcGaIXe-1oF4+7jd?p{rA7NtvS&n5C(JLgPbN8
zQ<h=XGSW)>8hR&K<pztzzMp4%S(IsK%28<&d2P3BPpD`PS9r`?TCdjKthh<$$hT;$
zm+hqS4Mq=Mrj=)C&THowyJkIAxC*BV_^*wE0;m(&sMgb1H>syOme_jVrw;F6{p{nq
zYv%_$?^<tliFvWMyjHNnZifqcjAbsGBtsU7QLW1Fdb{(S=y0m%oi$Q)cs<Xr7Ok{3
zdL~~u18VnzmfJjW1x2}|a#*xY6K2^P<Z)7Kbf#{nsL^1|8H=Qy9rV@Hqn+^qs~e|0
z7Ne`I^bBgL+U|>H_JDJeKtcZ&o$bCrSIAt-7k_9cN$Cy7YHB?_$L6di7FqH=AJ_;4
zIGi=4TLnFJhQ3OYq?XZYU)v^SM`I1_R^0~Yf0g(~Y>Y=Pg?XzO=@W2CZNAgYdeN#B
zsZ(e1y^?-n82yJa#vA#3q{BI6{=U}4-xh6a{M;m%Hy1VaN8AIy*UtIPQFF+tfhabT
zhLA6GoTQBE0ZNjoFVhYhUpESLX(Z{|;Ea~C&49N3mW`v?%whWhxHY6v-I=PqOGpE`
z!H%crLdV&jUhCP_#eq)vQOLQz8fcAd9|VSwJtorx0V8<yr)kA>q>?TI(&SZU#ix0v
z;mF2i+HmBBx5kV4IX=i)z$fy4KoG+!mPrjdR54C=LKMBB@#$9Uz=00u;PJfHLq@bU
z-oqe<N%l6*;@GYYYV$CzBj9c4G|?^4LQ{`7(fU-CVb-UNOjGRON{ZcOi7w7?O29tU
zjhrcsUV|Hnh|(#?Iag{vfij*A#)hgkkVe`-W@$Q<xEsQdPQ)tr(CayBAtP!v0Xzd|
zTL54Lp{dL+ol5SY4aNYa<FvETE{<NtIzDogwTp(2Hz|E((S5f#>5hu7;=GvTOP19m
zY!~Z;m_*m>QluJk*zUBO2M73SdNZF-^wfMKKjx0|Wns>1Z2+HhMeTOB3fYQS&sbe=
zz+0b!$X85|+O*LSnoTYCK5tC1bQOz@v)tWyBDZa~byXJc#JHC|kem4&FsPc(FLu{f
zVznG6cWEk=PFc+-=m$3gdlx~UE-WQ^8;En7T85kt+Y?++J86|3TOq5YiPG3=X#L1O
zR-f-rCz7wlzApyFrr?)u2}sr@B$m0}Ao125Cv<#E2yc+?)HjXLhQljkH~V@PKUy4n
z*Xn_;I0^R1m>5O|zjpg?BfC*r1h6yI8^ZXc!tv>KtC;V4%Jf4<YdUS!C%!?aTMGzX
zU9&C(JTRqB*%!1I%~05U;(^Ap|D&7Mle(LsJ*1X4&=1&3?0D}6WtD|kedmw(s+BH)
zgliWPk#$=K6)>#j1nLWDYW2GDtKIr8XwtfQzD71^zAen&p-#V%G+Ul@mzvzJqV{pI
zN4CxHs*`30t<ozoQ&=aJz40S-z}b^xdEYBHi#=AN&*Ehd=jJuA?8@#`=^!s+g5{-B
zg;tN#_;{*56@Q7u2GWJtbFq4?<&79Uhy@-;q3XyI0*rw&Ts-W#h}D>RxluJ5^jAJ#
zbC;67ic~t3WGxe{AM%x?_2^S!VJV^Yu(rr8klPV)Gcj4++iw^L^a{*W+!TXsgBRX$
zV165)7OZ;SA>I~a{7M)K-fBXu2ND$WqiHo*yM|dy>al{I8#EQK57p=Mn6xTWOdEN#
zD8!qhU2Ff{B@oZ|+rQn7Vw76IkAA^6y-2H!_(aO+t4>0@?__POG|i&jh3n~@hPtPI
ztjZiVW{x5QjiyR!juC8x`YT2~twg^PE2$G?HI+^ur3duU&WIgZ^0$=El|!-1Ds(o&
zI@QLyF|qX!S~<(s$afdduui8w_FQ3ze}fMdTCHeundQ^P94x<KDm$cvRLCEhCF3N$
zlkW_*(u2v~uD%|2u*VF}h@~)Z|J}CI*GgT_$<jZ+^z#wEfNA1pZXTQ}vz{6;a)K_V
zYMLnPrzxX@9Wt!Sq;X`xD#uB+$d^D~QV!(o2X>k#iJG}fx{Xe?iZmF|X5;i?sJ}Ov
zs)B)1*(2&HFR)xP5%s-|L=IF6hTY*gTUxh-9j@ZHpeN!RG!|>hkI`r6E?;AVvGC=3
z+ErL%VHc|XB)D^ajtWdOgk-4d4Rw<`2;KnSm<}E4>&TB`pBfv>?_FeL{FF5)lGadL
zN1*Mx4QHbDkW#?5kMN|a3h#SlAcf(s7)Z_1X;#HTtD%ipEZt?y#Rg)ZFxtS4Btr%W
zwjY^I9;7D8lG(;4+L@}V)Kj$g1l}hR2w&_3T?-9ZkAvR1yTDo_3%dn!UoCL{E>b<d
zp~}5*6;s^D>I-elyq+Phj=h+kVn?hoz7V~JjIcx)Y=ja)2(0&tMp6g)s~{_+o1R~f
z?@b*UbOPPRUz*==S`lZyG|4Z`^I;G|C2!!))vq=CY|b-N#I`|^sim<gqdIUmMQT>b
zdaT<xxESkX&kWGDnhhFX+J@Z&^Slcd(DRx}#?6eUK2^KD%Gfhy)H0n!=g6K=OzjS}
zv!$=lvVF@@Ow|kJSZD}#X_zb(HGY-aQfig?ppvEwU2Ki65yUgQ61Nh!mItk`(ElNL
zuE@vusGCPf)V7Ba<_8*T*4!YfN>ikkgl?o>eYL_{WmeA!<GQ}^u7Kb7X0faI<1-Vj
zkro^vYA$HMH~&BmUXZ-{BmuJ1M5}L-o1~DcZX$<o&{ZSZyERqTDZ>}VtWIc`-Y*=3
zH6l>E=kYZ$MNHMK`OC@+bgrA;rL<Pg*=lUn7+@<jnQCB0n$x8uTUdy6$i!e3C5~(e
zidNrEZ+BC@9!o4SEiTdstNS=T=&a0a2={IAyl4`LenxW0&Nl6n#IErMyGf-ZJGYqs
z=JYr74Rp}C>^$#u&*ZQT_?PD0Z%_Q2iEud|wj-P5t!5M`!#2DqZ4>e#8K5_e^Qnq_
z{sRI}DE)Zs$N&Nal~2U$<IvH&mvf2q0@gjwiZG{CqShQB@jKnAie96Eq>a$5u@ZWm
zJqP14nf|Dl*qy*NY$(#TfZZTsO6vj@x;^iab>m#5E^Tx|vnOUmu^}N|D15^C(ZXL`
zE3OsRtTlJjb+1giEg%W@h*8spkxEGO3RH#)^J#_NHH@Q1N4~#rKCjU}vy#3blI%^Z
ztGF2mbVdH9I}D2JoyY$aVGRVBLAXKA1|b&q5o0>tfKE12GrAtb+CK0+9qe3;$9jrU
z?b>oA5C}l)4y%@|!BC1_(tuM{W$dKyk((hO>{o72?-syXkbnj|nuCOnO%l6t-LKNR
zI~3Lh!`xN`R<T)e8XMqqbRhBlsSPG_{`|E<56cg5Jb=5$P19@Ecq?EAdh2G1cW1uK
z>h3+1>aqqoyaj7%<;Io}cJQUu<@ecO;DreoKPO9X|NEOLUSBQ+xq05i-r)U^Os8vm
z4}Xi!(GA+$Zq%n5(y+$2_OANQtMO4Q>w^Km<cp%lyXJTAV4;~L+*tjs<Avk@F4a3r
zZ=$j3)>ucVE49jC`M0uz|GQDZkKDc@i|&IG$-!hp73M68=cr}69l4>u*xg;Ju8?&4
zHfOZUYNAJ3!>!G@_4V~pm*-v(J<FGR_z>z>0d~^X#Ozj6^@>F-w+3v|w+S(;Uln6c
zt*BfasaUI-5$_84H0wf$HPqVz2mZevDFK}k@E5SNRaiH3<albF!W>VsXOpoCbg{~a
z4aWMWhgc5e?)gBZyc{*t=FM?9{52QoL~1)csT7?vR?^3fl~}U3Wh2H~r(<79Xn~}A
zwLH2JD31gqum{kqjJ`mt3$$XIS+p}2IZFH4W-L~B#CV5xSPdNFh&kD}yd>Qdgr-0-
zG|v*n)b*X{Q3ZAU4K-G5!^v0mxz=811bcGcn%8vHLR9|Mc_33Z2>m&KhNu{8s=tw1
zB_B}2*=h>17`q*}axZ|%1^)fXQh3{?Yam|K5Km*6)T(-IOMHqMl~`NE*Fg_N4&G(-
zmBECy&q6iE=o&J8R2aE7fUwd!d2=0(Crc+f80+Bmmn)K~|1FU#iq>Mb$BM2(y!JsB
zxeL3y#%r1(=s-G4ZV);ps%NKrjAykEj6t{O)i*`tl7Hk8GzjIXRQJx*ySo$7ZOBUW
z%K~Fc#W<}?68Iq9q>Ak}+SyUs!8&3G1HHT@>E_^z<Ul4tww75s7=}AmGo_QpT6HHa
zyIwWbTd|HE{IU^Uhd10A>rW@sKf<O2-QL5Y0$D*Gw1!275}n!`bUI>GL)*^LRn|je
zAFw&TZmie!!2Gm9&BGRyu<E3>EmiZV3C(U+!DU||UI<w|88OH62WNSh_s{gyJ@2mZ
zHCOwTYi&OO(F5FU)$V`OySos<o&~iAdb~8GrAt@gGwNfkK3&hE6S0FI^sbsL$(zg1
z1fmFd=CBssKhRdh=MdnmJqGLhljE>{$hT6n<Rzn(z^?$6=-{{5Kx}1d0NlXcJQohM
zE^LQ^2DO1&m+*+4_sId>fP!Hkn%|}KG+mdjkHIO(!&-<Ah-)ZSFb2a;u}v}r-w$hj
zk%YVr_@$Oqk>GdE-!+^A(Us5|*B)BZ%J<<Q&8+w{ASWkFv-bOS57-Ftf+yk-X!hNt
zu8HnURT;GMI0YRtneJyva_|$%x_GjN;vg1=eg+U(gSriur5u|);Vt`Cqy0YFASCXq
zyct_bp9p;tW6|xO#H@FDA$BQQ$XQ7-eBH)gJS>w~F`Q-Cu`<(0K8`{a@@eqy_yEI3
z0tBS<o#^*dpIUAtY9KearvSU@v~&>8lHEjy9HM94l;!u(#HN$4Ok26VsZ&t?LxS7m
zNV)Jp`F)T5Pm#!i^oI$yEbrM=Wj8rZG5ROy02?s6Qwb^ml^byyO9Wuu4wtU6M+3uX
zpH_C<L?M=!AA|W=Me0-Uk?BzNdTQ37-A3$&kt7!XIu!eomUQ2YM73qGE+G$Pw(hB?
zW%{3zKnezNV#e)=HS~R#Z$jnu&GXF|)Loa=XTfdc`8BHu#SUT|gzzjOXNhi9dP7j{
zl~dw5^1P$Mz<8y5#2FrhbJ+$SBZ@>XXeiND)VcycA7!Yp%ux;ynKrZmt{hB3!cwsW
zeJKWaheh|CuUs)%4{L`1=jpPM1a-iM7eZ=YCN+Oex~-?-2Uf!zsbbO9&@AIgqsoYO
zyRRF`<!Ct!{e6j6gcf@wPjJXaeE_XCQm6loO6%kju6J7ctY-sr9A5a?*Ui_{8wKdQ
zNUIpKkW7lD!AH$u(g;+g(pwGk&vCMtPwb@))>^uU9WswPEj?y*5C=jRwaM)>kMJQ>
z2)WhqAQ+BV#i+6)yb3@zKE?Vv>0wxtQ5Z|H6A+B<^`rFl>0}YQrF_+jl%LV;GLPGc
z9m;%S0X9-+<4#(eu1z<DKA<VuPblnLIbWestDa_&0a8A%z0aP4YLy26qi{SmtMYEQ
zS{uDhDO{LTqQCFE^jZim57|t_UoZ6V4i3`A26&c7<nDxZX`XVBcJ3t&MD<ouZ!OtL
z+C{6`U!$GiE5=}c?^vC-!Nmf|!kguRE^Cd06o3;w-);H@n_+*-N>)jUw-XXS0KlY{
z$t}vLf$P{2JJ7#A*ST7g6wqrTfg-Ihpc*9Dc-TH_oCj(`xxWnE2yM_*XR5(~IoNwQ
z7VDtTCXJRkR<ITzP0W@xKH;iC=R(2jJGx<Fz((U%fp_Nn>ppdy^r7h=1iIZ(cWHu0
z=Uh1rJ>oq9ZCElxNDZbJo0Qb^A**p}jORZ{^(^KWd2R###J=VB$tw#eNRg9?%3aeB
zVGBZ@nvGF`qd!XnQ?Ul48$)x$Xk>>{t)aSsSYxd6h1d^Sy08GVBG-hHmbR@7Wr3jq
z1$v*PLbdu~1^|tuSZtb-YGaNj`K5K9EW*<&GL%&Z+A#!1w4H&rsJqZ@T(2CUsslt|
zu~zgO8+qF4R2}J`d6K~?DU9(;n=o+!vpB7oF8Gk+Qap%6F}#(CQ`L<dXc;}YCl>83
zR`#Tppy88nrY{`}q=!+7c+-5PB*~yOn)@7n64A*%Y?H+7t1Hl|R4a@0lO!(gt*6c1
z31%}k8bEoAA!H*uDMuw?Q|?;v3#laOU4&KD4af1|o^%%rd=N^0a}@TGbV{yj(ZE1C
z7%Lz<BEwcKnPN&Xu#%c_+pStry~zs=#x=v&nFk2bwkh1aI|I#zu&C`$5n?`1RA&Vq
z7KE>gya7vf1;Jr%)T7fmIL=AzQ*yvy{_WFuCklw6Xhjo<!W1!^XDNCEuPGf`Or^R=
zGS+Gw1$GgejK^MJfNd--$B&iwh*P#+YW|6+aHe#vs-l5hH~w`u_N^2(Yhx`Np;$k3
z=t^4pot;PHU+1lCDOreKOW@$)4ix_ax{dG}PDQ{BPe)<7$KkdZpupC;(K)^^)^+65
zk$C6W@SwZNg_HG<NyQEM1zhJnyCsB`*tjaENaB{YNv3u>6`PJ@=&!^D$PC5Fkr^#(
z+mC9ukF|ry1E4AkXVA<5Q+%9;)LA+}DIEx<dSkGF8rBCoyHl}!EXORMxBFbzvqKwp
zZaC;!aIx`e+DUeh+Egcr=X+`O24l7C*@;*`8|XaDS_?QXZ=Y2LYRN_HS}@|vY{Zi2
z-mlUvZ={mkG6z{>tjoOBx1Jarxy7OL-F%O`^r_%^6himgS!|AoGF1^B&cPzl#UZn$
zJAIT#Kgo|AEIMtIfN&#izZ+;NJ%g<tB_vM$@dFFkwVK!9WFa&K$F`otljLwWIYL&Y
zE7*`ug1ydj@g$%UD2f8smAy+VTL_mC(0#&nze#`tc9M$iv@zY+A48WqVqGj5t1?iN
z63`S&oRg&=V8?2xX9@OcX}uc%8&$1k@j1%6$vgaz*}$3>+m{>IvU}+kf1xmkP3WqK
zTp8p~Vxt3n{e}aDL5R{oAcs&H5_GDbpPrxI8;Yvi3nO1QE5$8Q6j^P}x@E!U1ovF~
z)-Og-R#@=&grh<jFOuFV2FIRsrYhCcmPy!}hG9sn)=#o3bZa>ZbkSDZBAc>w-jI`Z
zD$YHoRs6y6>y>l#1f8W1RrT&Px>8UDhk&KGVwtUu3|QNfsDqktQA8F81fi=Clwln|
z<^P}Wd4o<+U{##97cXzb7RMI5*r2oa%_i%l7%GnOcZ*OT!<!tlC~Ro_Q_hM|XP~Oa
zNoWN)VI7to_P_7swE;ex-{j80#<6;*6`MM)dDns$cB<{x73{Wn-0i=40j1K>VLqIa
zK4ox`)<`$jY6y|zTQ<ligmtA^-~^qBpJZ>M%L0>m<-o$5HnKorD_yr6&9jezB&|-+
z>I;o?FkN8PEgJpwZi;q7w{)ckV%JQGIwdXpB0@HA1WGL=53ZpSS(&H4yCPj_0T+d#
zgGhtbL&g@{`Iysg9hy05b&hlan7<{$Sb{(REo~B5g#^K{+n~3LFo$bN%?i0ort|64
zPF|U$RefXb%RO(6@&vRJ%dc7oB42wE7J>}i9DCA_YO(&D@B-jEOESGi9n?i9kpR*M
zsXeSCbTk(2PF1cNP4pYq66+}}XqP-~2W-^ez^2+QhNo0g_B*M=(~(a2nW?!{Aw?3~
zlScFt#yaCMfc#KU3`r>$(8rll7o<QHTX>beccHt=&=J?*8wLJc@lcvZH#qAm1U`6c
zz}?4|p5)OcfwB%bKh@kVPNH#uv(dvTs83RJm^Q?JczDoR@9UurxBARcpg+q!5QW6I
zHSui?FqN&}iKY|=C&R){oW<r}9h#-UF-d$qw3<pGq6Gv4KJ8KZm%KjlCd+BtMguBC
zT@i@AX@^ff7M!Z6`&G62>oMT^)2#YLdbRgN?@g9W9c77W%;QjjM*|#aF#?UF00`jA
zz{$LzF3`Qc24fvVm}U{|rO!-UKJZtp@_$%7zYJL|x^G(1Z5-}M&A6O6IbA7I4b=%R
zZ84PJm^u$sF%KLezh^qplZb|eGpUYY)R4vN`QFMeHJ3~I#Db>6o4HG9ZA||%t(c?a
z6GR6JlyyQKRwvI78TGK>i%TdmnD9U@bvQJzf*v)=6BV=MZxB>5J^||VW!NQmQ?Xv`
z<DD@?Fxdya$&qg);BsSg2w?ADL$U*k&0s$tMMl1D-%)8?;vl+@R;(K^Px2$1g;;w5
zK3;G1`!z3E2nFSPETEx0>B6uy;Z2%K&8&<_gjDF9Dq_x5Ue4>4i%x~MkF<(~(?T1z
zH_J5?<=L)nrvIB#kZ`bl8Wt4snpGjI%7Ae>jgYkQVF(sjEWUa($vZpkC4a6E7(zXN
zz;{`gH^`W%n9|Lf3yo83Zxf6fxrjpWfuaMUMkt#GfF1|a)32`sYK0q``#6HqLlHdI
zhLsKg#FHtVrRZE$Wt}g+O8jF^XFevk-~7je&J4@Wi+R*X3A=CbFuXRj58E?#bA%)y
zm6eNxv>|BJPdD?tweKik|3l)HG7BgkY@70-wuJrzR5^ehcIBOteQcq`KWb))<E?SJ
z$(J!3u@!P2qV~|?<DnDKH7Dq5Y@H1xtQ6Z_j4%{Tc9Bej5=1(11C?kEmDA}RbSJIA
zv^Rtr)71t&E{A3SKL%OS$|VW`8H<zUln_a>A)!k3xnGanRVl`^Zk_cp=O~R2UY;&?
z)eUssrFnjpM<<aFqrJefLEEEd?v?{fY%4lZ=}`3sbZPzhoyMWVtrWN%pU?M%-ka$I
zX9yWMGuqc4k${;LlOH|#-~t1M4E76RYr9DWLSy8naRL%xu!DPO<#84mVEby85jV#v
z%RL21HU?%;6WFz3{5?T{eE+3hXskUT9fMgQJ*irB)dIeUy*2(i9{{W_PY49NC^u6I
zm>7|=M^&{-LL)$VV)=EmhxH#BEKKot;?EY?+irfJyRf9y0dUHRMpM#qN@zEMwybm(
zLmm83Usnpzi9P9~ZtF}XoQDo%{9NT-#baky*`IM;hjiWkej~gXxcVYDX`1q%X;wqR
z;tuRggR)lEPr7^4XkkoW_<b0{-~cQSKUF{pi|trMuJ@!`MqX~LjeNO#?>W7CJv2uf
zQ(bI@sh_Y|JDdujSEr_@Srlg|7NhHt_Zf<kbICeDnxIDmsHy{(o5lxM2_sh8bZQe3
zkW;MZ-2t9hb+tebM`g@4u_B~x1?b0HPpWT7Bl-ijhM3%1Zx4HRZK`KR7i^5@KDKVP
z9k9AE^ioRR{T2eM*g%`1FmwJO@a3tPUcqK*6FqXAZ5XlEQ01OfKU<|uow;so*A~lN
zOB}FwXfiJ)a~uKE2e2OM)x8MXR(KB&q;8~v3-k`q59n%oHMKz#L(`)%3Y!k*+57Aq
z3O%77Jgx<1iJIQik<-+w!0KLnOG~EGRY#sHbbUOy{QblG3JV=#Yp;#~DJb!SlpJ)n
z^oU_rLUVSLNIQAvcz#OM%{zTFuXsmAK5?yB4E)FPC}3Rd=~q@tfCoaOTr{(w?^Xj1
zkYh-uj4Bf2f$eu$EZvzHGIFT64Ltj*mVFAR`JjZ>0{m}xHe4}PN_M2;*Nx-HyJ2_I
z-nq28Cmp?spgh2py8Uv-%J(stcHkLc1%LprFLXmDc2IynMnif=)E4vVx7aG;0d<L9
z=~5JifhYhE1uX=YS)-|(hGH~Iutcgz$8>97KON*B#MWYie2-DjTYC5?A1a<gzU_5H
zhd@3$iE2rIx1)qfj)!vE40_Fq6=H0pV5wlK8Tl0qI6F{f^c#iFL%c3o%x&YN8j~|E
z;S#v}eE3{r*;HfmZ1*PsfZ+eJG_6m8L2;a^N&XDXGS=fR6ri~xJG7;FEdm22hfN#-
z?CN#BKw~MRauJ>EvL*}9>|-5H%g4q*=ZcvwcJN{UC}NypXaKnF?pElb#;YTARu7`b
z&hycY^Ld1@@qcA!&kx72IE!!yA{*ET&f!48+XKD3698$z^RU*0bOsf@dYaYUG#u#i
zmI=x#R#S+Z!Gm63!e{m+t_BiMxx+GQj_P5K_5_(Kh3<$n=)VKqxNgkS^VB@}0m3&Q
zq~{RwwW0*#3j<1Aw_%h3TU9Zjh&46nzy<XQU^DRZ;YpK$%X6HsO~d|NbtSUOuB;{2
z3JCi2i04h&v>HdHYBvytdUA29<*wu8$r>4S7DeTvjGVP%Fy6FUBVEPPYk+(ao4)hf
z9|0}i0wbk4o>5bf!cJPTK~nXpoyOMcPSO~FxL3Xs-vflckSl+o9F&wOine4I!aIP|
zy!@Ebpic!Xa(MexZ!K*%TA@b}PCN)j(z-rMN99Q&k=$Csla;m*DBnR?)9BqQd9ZAn
zRXSLXoF6=I#h>Jd(*3VZAck-`40qvq_q)QMg-imLb20>an811k2uB)VQyQ)D_L^r0
z^W*tQ|BUu@P0OU)D%yJ7?5zkY>F&_9KYtqZZvYuNjEoJFRHY<voT`9K(vkX5e|msE
zbOfN}S`E{n<J_F@D$4yxA_3hr!zL`l*~Wqzn>`*HCx|N!7z5;!UU<8Q(yhk9@9*?c
z1rd$~RGQPEb?of>0_cLKRoioPI@(Et)2xFZ%_G!~!^-Q%VzuJyM*UmJ^+e&(tHSBv
zz^~xnLB+XnSYd9d$AJfdT0*|Vzhm@-p6v;>fyc7*G)R6Cw@=tkn+FB!vd4bpmFx(`
zrA0G4MQU)#iBuzn3b{!>A&AemU}U;N5RsQ?eJr{+p6e+V?A&_fDUOrev8Q>@Hk$8|
zzc79sOFItVYZVA`8&+pMduEjZi3WC6f{l<ZUns}far#pNRV5KWu8r&f1LnFuM+1wr
zlQW~XFy=h7dATqq`0LYai6YuL#>ZS6IvZdC_Uo(zd&I1u2-`>nITLw~MAZ}dao*q8
zW7hK_Ysg~x!bIXqc~&0F_RVC8)x#x3_J-LAsUpPj88u0wSFfa+jGg4*9-~$II-3dl
zIuGFVvjwDR;-Fz{M?9RhFPKxGdxHE<Dl`>sFs6Is)2x$r#qNd-MBiiSXwvAP-mv08
z8F~^+iOInBYlxF-U?Bkj4Z@^Ucc`6eC1j(nz*|;hn~Tm^e$45hW9-yxt2OSRfIkji
zl|<tP1;VXGh?77EiB2lv(@9m5ZkatlJ3Yu7^Z9XS_u-*pA-5s;XgS-#HMy#HXkXgC
z&Boku8&*Yj+^m5)SsSZ0YH8gEWDlmJ6(D|er5BTtj&5{Xm0qBz(S1dr<T4)iK77KQ
zIjecYWqPC9Nlq-%dTcnKq>YZ)a~PR*Kt!>PPS6z)Mq5gxBft!istQfQ0Smxlhksse
zEK#LC-^#{l6{}t~iYTb}`fI*7i@ALuB8^NUv>Sz<L+_58lhW9Nm5hjs1izeAs$J9y
z(O`z1s=gzGV(oBWQEuFy@-tm+#{wvfa;_AxQCF8Y8VEqJ<=ziAZWTFPptZdc18WG~
zOphDDj6$*PE4{1dlQZW4tJo#i*a7>}i`p=J0`JannNv~W%ymycS}mhCQ?Uvew{Bvs
zMr;pFzr0#B0v5Z*j+IM;67{kGfB`oLP;_0_&qef#f^<}wzrn=9>u0x)tgi2S)t%<=
z6$d$jH&$Mgdz8t^u;bk?12zo^hT@wua(Bw9(^iP+afZwfLH0vdx|p179lol`2nSR%
za@Hb%^@hpH)-G_7$RN@A5S4~~`mj1cwy>W_<+c1qJU#?wNMUIoND*x~{?|s|5LYSl
zlwplF7+;UpvRYDo(`aJVpY+n_z~TXX+q(YW;F4boBn$6ZfWZ=v2DXj`8MbAGb5Gfe
zDy{F{qr$9453NEBoP!sf4Tn~lqlg#|ilTc;n0>|E0Ef2N3i)Ch0fNC*rBXg2q&2VB
zv<;r0<!d2rAU`-p_b$I{trZ6O8A$`2L7WJ|fujY`uY5Q)h^QuUNH@uVbxEA{)D7Al
zI%0q=VniG9jYjv0CBKF!5XNLXR=i2hRzO&c+DKIh6b@QXTDpyv<1vH}tBlv0fF4oF
zKf$@o5mdQ7fD$~YMRHyLNWVajVc}s|jCHowd&^>TmzVR0io*lefWT}qG!D-~D6mJ6
z(4-kemnyxOGJs)6Zp9H6h~MhF)wf3btXEdv8U*+BDsLBU^Zbf7E&&+#&PR`+2$}*A
z#W`*YT>S>w?yZ|6k5jYvvT^W)0nQdIFzg3q$5~Gzw{Mw8S-4ySaE_XAI3qhd)u>A2
z3Cx4eR41{%Y?xN>_8aK}t*7w<IOvE6YzM>yw?<~EV;#tTRUXu9Bj~zbF^z<VRXVo_
z4h*e-r^={*XH-buTXbHSgM7e6CNturS#J%2Mu9~FKR|wS+RZLA9BLcP-_67J?>WDY
z?E@$gxFYWsdsvsXDG@)QG=KN!yA$9|!|z#vHzB>-Uc-RpbzV{znv4#XYQ>Z50((N=
z=v+b_<3c&k=53PJiETFS)H2>D&UL4Dkf$NZ1F6MS19=>z1!I8Sg^aNPAX+OH4J4N%
zS~R`zcBzd@5#T>#Tfm7g7t{;t0Ue=P%r3Y+k}146Kv(E`Vv~;L*G7C$5OoMyb-4HW
zjS}_43>uXxmR&t5A$yJI#505ZE`YG)&h*j??rH(i@2lF^P^o_y+fQy&pG6^87mQY<
zNdbDPSfsH=G;%uD*9*-MdWh0ifK*Kho?{3F4+OU1T*RWe%RH%{ZG5Bg!3N_3G3HXS
z8(^4B^g_qRIvAol+k4Z%S=hdW*8C~BJ=bBE$h`!jiRt@D*OzD~STM17_*fx&JP#8k
zmak8|KEwXAHP3rsXC$Jle9(nwdeI#Ak_>oQUOnWj5Skx{Yz}hugAl$wP2Lm`UqFKH
zjO~6AzM7V^Hg|r6gAM!$mz>6EG|T0w*G(HW0Y1>1B$YRf<c&kd*9`_|RIvS#B}>4#
zC=J7`J_};VORz=^y^?f?jDsrhk=QeV?t%o*1K%xwpQA)JR29GjRL?5aDjrpz?%oTp
zFu2a359?X%E=ACzA-$Z3LKgWofvMrGz(=emcxyHoJvre(X~6n7DhNe)8u{&z6KUxQ
z^@A`GAAq<fm*pj0kz*50t_m1Hzmxcb5++R<Zn`OF*jwW?A`CMCBmM@A-9<_a_AJ`a
z$=0o*X|VH_a7wm+yLkYf1DFJS$f?m^uBdsR@H<qkCx_D^gvH=1%CNXqZ;eul<qMWl
z+oOR?V2H}|ZnM(X(z`p=vMp%xVm`jf^GB}HPg$(x*2f49RHfgwK=AGZ3YYgOJmYLZ
z8;w|96^r2Xkt3Va(_Pj|FB}>~+b<91*KT29b#T}*_Z%C^PnJkpZnN(k;)*%MsQl<0
zA!Z4fM?lnlSX%`{KQchaS(h=vo&ko+mvEZ=RUB(6O;(;0vu1^k@JDq)t<FA9DrW(T
zg+Os+y$pJz^IR2^RFXC8juwCgiI{c}_VEP`yBTmh^=WDVkpy(dH=V@>3yek3*VhXJ
z0>~kkQIBYnE#XK$Iqs5+KxEre2oh{9EYbdItBFv-WF9|eKI$>s#S$E-D=(huy7H8J
zT5I0?o69h`Bq6n=2%Rw{UDvv%6oQyjMw~YiY~p*2^ufJ1Y#chAbeoZ}$-xqvQEf!(
zfiZP98nwN>TYBE?r;i(5$YL>`O^&^cR%wCNWj(S{4%EFAdJ$E5k&{$?U2lR3*#wnX
zpKqC5?C;y8`OZQt_FXqw%mSCnBE0{ml^+n2%#0c`W=2B%yGaPsR!#X2YsQ`YtfL+0
zYO)5s*>n*gb+y(ugpG$)xAc~Mr|%U7g@4h`kWdj~tv-S6OZwK%T<W1{GJPmk$70<#
zj90ehaGKq6AgX<gRj-1dr<^6#^oB9rx+?_&%WhIdL0>&eBheAWNcOSFRqayg28z-H
z+bPrEN8lGWW7)6Lr@O0knSfOQn`#Y_EZ%Q673vwUnrSFVd>h21eZ@R`!IiWmSwRIW
z%e)BS5qbguR(A>*abFDrcGe>Q3+sc#yxW7E3v}#C>D+`YR4mV2`_eZag!j3vL{Ldy
z$bic~NB0oG;^5H44kJx-H5Hg(m7qxs1Hmdr6MohP{K_h7+9?^O@|wXFvTnRYz*zLv
zVPRF0KuksQgt`w$)S*5OG7QRLq{xti4tkPDxvh3T-Cc1V1IMOd;dS-RIp9c0;-=Fn
zUau=SW9}*ImN231*Ca?|!`jDu*+hX>!tK#BvNO~b|4M$~JZN_5LwyGa+-@2j;MWoe
za&+)6>&Fx2?XXMBJYV>_XE&FHJ^CDY4AN5oWOhDg)&N3Qr>P7(-Da$H8d3YVq)p}K
zCIagAGg|JJjT!G22sbpEWiNkj=kYpV!B0F?6@o#XCUqN#1~0;?iM`5PaHB!JM&(B>
z>&YVX^<3%M(rV6)uL8fbs?v!W3yxadwa}CN=v!Up>eOpcZ!LYr{3;VD{RIV&eG<na
zRKmILCe@2*{@wHWR;#}+oNpJ=uZ%g9Zil!E?QwMidhyD)%cY~6z4KSUjB|Wp@mSyk
zPMS)yH!e9b)!?!u#z_Y(_5peqp|wPZ^~zxYz%F7=II-neIrvqj;V@VN;VBh7rs~R%
zDlc^N@f0Fmy&?7qi5-EV*@^$I6xf?Ag5;2az#1xQNzBrZ)TA<9UjQP0z`&MFE1KxY
zWTC+<KXG}5yg(b{qp?c>6kCuyX2D<MhzjFO9Do``sV5nk)FYj>vo$-X>YWO+Cv+gX
zccc|t*g{l0Gtp&#@eB}7#25bEBfBvfk_Zns0r?UnI18XB3FrX!{>@O#*a#uUh?d4;
z&s&?8B|}q1Fn$&!oG6BE1U18EW6fWysk$Y#_E5zXt4%e~SvDT(>XnqhG%R8kzXF~5
zCah?-1cN`2WbZ=lBh3$35sr^jD;L$;UkATvoK`M6k>bI-PQE{}Zf?e$Q(_=~!kq^$
z9@WelxHSG;(F|D#8D>C`F{Ffo4DKK(wG|ewvg*fjWh+Qtn1Rt>)c#M--T=C-^Sbk-
zST$v)Zbw8=4Wi{yg~taFBuFA=R4?nzro`ii$0raZWe%fobadPbhDchbOq*qVSg$4(
zo*qF+f+S1j<ggiS8qtuVICdN<jH7fsrzQ+iuuWSIm+R%aI+Iw1WhM2TL@MKvJv!U{
z-AB3Yo~Cn@wIs&p#3J#&_kH)f_kaKY|2;CDA!-r+4?U3m+3kN_!Qba<3_<~FOX@HJ
zuLYr^@gAbPw=Ji(LYo%e)#0%O&Cy-iLyyB32B3N%3!>Pn<vizFG+%S_NmM)Lqe*y^
zWi?>#QzMFJYXY2Auc_w}^KdB8<#^$29prY4S_l%{hU4a5Junk%n^A$_xc!#-qP-Ga
z(LPr^Q?QOW8Bmi$;|__x^e4ESU^i84Cl6^zl359_B%4{yIF#E8zWdz7TL}`Yc6r3#
zXEZht+I0wXHy(bG4M2RVN;?NV0MYf8VbyjrS#LYGr>w))F=Ag%EEUEQURuW4$Gt`G
z+(Zby#UDd-Xg##<{+X7|Gz@kQ@FVMjq>hICi#C!<sYFUeD7wuK8ec+l*x2|uh5n&v
z6|awpkx8BIK(EFY9W#<-Ax(vddf!?}uIN`nv+;{r-xZZzNlfRWG*W?aVD*5J^38R>
zzmeOjl3To%?m4$XFnRzrSC+p15ja!~Aq3z4*^dB_DPx@6$&lklrjv$zz84JJkR1*r
zpaM(Am{|fL$x-x9)kuc`3-)vV9Q5-UkKSaA*I(7Yl5DtUjOwd;vST2&aVuQScs&;L
zpr%TZL?4VYA#nxwSD&wT&O=gVz!WkI8QVTqj11Qp9~2kroaa-^<n1gxbU^1K2$1-0
zg~<6q+z`@L(vYwLw%$@7>H6-$PzRSadb+bfDwnKFr7mb0*s6Iafe<{5ba;Q`9ZD{n
zI^AH~Xz>I+qQ>KDtuu_U*1jXP8%<sJyQ9W~JR6G_ZNE`NHnZWDFLb09*txZ(;a-iL
zv;Hf|+8GUwr(xEqz%^AatMPcM2ob1D#`)6Xxh~1Rliotp0p7wyV2VNwZlpHl)Q+nU
zipC&u@RoXYP&Y1<58rmOv2r#<PdLZ5@Mcy>Twm98I28c@wWHcK>-rG=(xH{)kag@>
zpyU9yPL>XaeAf^CxtG=iVe>y2^fm60ndRU>T1Bl!MIV&F^Z`vlgWIlP)}?y%a!SQ_
zT846pX)0yfSH4ZQ=Be`Be^c|+t`Eq1G?ewNq-sH!4|?A~G!Oa%rIt*2%v+;Ziw;t5
zpiS$-(eUpyL3{-=sxN~rjA!05FD@*r{l;wOwu&Dw&r+-%_F4IC554a6gf%TxrwWa&
z2s<rsQq!KfWzS?P{TZ#*p7<}yz2oM`a;sC`9_b`{oX_}vbmNoU;%rEg<RkDNLJ=LZ
zlfOF|EI>gRN!}bV_L=*P#BzT5nR2mjk*Md)k8|ecHdyEUNKv$>HP8Js(S{Srx;hS6
zoi?yT)ft1_s%m|HL?5&6C!5?=iXN$E<g-g|akFHPuQ%+i-J=Iu45Kr*?PBp_VL5eu
z2!h#hr!SP*l@KJq%b9~_?4-FRCq<U{65rk*G-kBgCF7Q(_w1#68r<Vq&1C17&LKs)
zm~(gYwsPs->`}t;?)0CY`=kQN5$K4gYXJY}=QV2sGs%c<Z&eQi0u1V%Q1yHC)r4_q
zs|A^Bky@><_;M5wZk&t{bpF5tTH^!MhD(|%sAz`<{dhY?&Zy-PUPFQ-+c6iTWgy*}
z2`~{)+ewcvPzfTO$oA_-ht-jYeNZ^&Kl5K?&recw0chFjv{NBXcfz7x&(R0ZZPtdz
zo!Q_=89N(DhU~g?M-Ky}^OTACG4FDbP6#pQ*6%;m=JjHsumuTGsBP3}F~Y%kO5eM&
zsEuflmk=!Ug@&c|lmK!oZnS9pdKl8Qu7X?FZ&s2@sy#|AK^P(TTK*}lu(`Rpb~<S}
zKN9aM@OL7iC*nWtjrjd^0W_oiVupTg-B8Dn09YV8eaVT{oRIB4M=$hxiHg$&3(^7}
zR)Ezv2t3!UCq9}9He?y{oeZ6cyRWBx+*wY5R#L1I+kdxyebk9MZB;p*ML^>PpyIIF
zTh@_Mq`(kkf^DbvDRa3z7Js!HnBS_glynwgR|d(RDnc(A^)?Zsn2bQMT>>j6*hSmd
zUvm80OB3slGTXSl`bBvndQR-ZP12mN^GE!@XP{TN!lX^N9Mk;3S$HH1v<j-dQfkd*
z7gta!rAp)>QplinnbEcw94XPCZPz+y21DEW^+?EfHPnB2qJ@z7Iw)S(sg7-3Q!i7l
z^TYn9zhDSR0<t>*N+tXS$#x};l#9BY3N9PvASp$Y8c7usmz*YR(wVQ}pIy$}1k%5Y
zK8PbNzSb7seV&%yI_)t7Dp3s0HFtB20Y6C0#u9x+aAO|~zf%%IeGcA_9v3!l6!>F<
zy{xr5hi5Y@!D6PA+1PikGkb)hKj+x5^cU?mYXw;5C>0u!u=b?T_b+HmNgNxx&i2Gt
z%oP!L?rF^hE@1p|B%8RAbryd=OCm>ezV*}wUP2Wcm@UXAqS`d}E@@khaI#b1b0IjU
zP8#jS?w6NKV;1y^zS8S7$YT51zRa-Zw{wsoRi64^c(@$8`4iUZHyZnl!IWk8=^c5l
zW}*_8W(^|6chWAhBLGPHOP-`ZU~oVCzvK8uGo!FuxNML0hh#e*FQJ*S=qGWJk-GZ?
zbqay#1j()hOl`?;8`p1UY_ef%JoAJdCke|8We>NC%K>}I*?8;n|Gr^8W-L_)@vvxI
z<!v=5Yw2{o1?R3K37wEPM%O7`myZ<b`~ev(9<4bj3MY)Xpni(SRkIQHMgqxTePzA9
z9<-q7p0e`tw*mTNR6;HrV{=W^M>dXQEa76)4NtF0i)#Y`V}&qXY;q!2nSU`Jx}CFX
zG11Pof;Mt=(00IrB4})31%9mYC0Nk5wVvH`(uod+_S~PHSadSz>#W3|WYuu?Gd?(`
z|K`Q*3J}F{yO}do;}u~uFk?1pk80tR<l;KQ!8(Nela9HUE0tn~6O&lUl0Q5|*rf)C
zVzL{NXKh(eq9hL|<2SYBp8HH<{1fKZ?z-Y7c4l$jIq%y&hkqXh8}P{?zd!u|c*_mL
z(Ea-Gq7yFl42`iRi#Ak>-2L&~G%bgtxgVGM={h^1gOz0aA(kLmiIk);WACGuflZj%
z)0cWL)RdcFRzT&sZRbzD<C1MA)46pc2P-GmPe>Iz9U>SU5}-2ZxvI07krBd!Pw9L5
zR0KLwlNs-OrrVfUPt)m&6=g^Ow#q-u8X*qn(^@1@^n`<9Ej++BNqSec;6CHwWt|r<
zY9edihxi&|Ytj1}GmqptVn7-Q=R5ur$oUaEO%=>ksPWdq0<k1h>?w`Efv9;hk=bP}
zlG|>px|HSb(0VGk%@s(<S2bEBG%udfveLN7)`cGS_07CaLDQ4<z37}yAAWrLA`~t5
z{*Cv0p!!g!r*i_LYBqfxgMOob81+{N_pG@*(3jfNcQzonOOeY+gzShQL>73&@Az6;
zJx!kbi_j{ho#Rh-QRGp`$SvVqqUpT|kTSLQWVzGTX(>j@@%`!DeyTOq3u2Bm{8%Q@
zT4*YSoyhgR2Ir03F*?^5sZ3tXTHH!L?$_qfBsSngIiAd8*tFNan(t_M=*i3nPG+C8
zXV<e68_{NDJF}g>_8X43{T28g{u>Wot0=nNwH#2<(U1rRwE8kHkS^d0<e)}MYr<1u
zeV196KeJP9UyQA&^ED8Xx_o?C=m+m0f%k1X-Eu!?C=&Rdae8-zI7<nuiIz)PJWZ+*
z`I-4@JW8h1uR5X!PN3zXcLHKU&COq~-t=x@&LGjM(}&AYlfxxidZF8<ee8|FXPXu;
zB_>M{A>n(H_Y>)nauHe5B*~+iCYQGE=MHZlKfA;17>Yrj%-EN*O<V}=rR>q{k?AAV
zU#mGp45PD08~6K_^U5cEgOx0FkkCo;&=6ap1&*$v4U8JbRkJb(5&RSTtf!aH@j`)g
zOWt;17l$X_>;ut<Rmcaw|LITF`NN;;4et&D{iU=}`xxpj_%*KFCZ*=r$NCo;PbOIj
z&p1hELtgAUwr!wDN^Y1-ns+R7(^yzYS`k&sPBuPwm}j+)<=pleRX8OMN0hfBziYv}
z0v9yCHs^bcCG%F$iH$lZGZY3qZOr#M(1zEhFK_#B>Qoe#r;t{jf2eAX14r0TPmq~5
zRFdZydgBWQO_Jthv!414;itW?IH*5o@n1R4mfg|IR7z`fI$CH)?!BKU-Q4mZ2p!jU
ztrIj-=DuXucxahI+~`TAoHL`uRMZ}&6E&N?QIv?s)4PG%7*+<u<{do^T!d^Y1@+<>
z)vE6U$Gr6HH{UP$7PIXuq|Hd@QG%@{h-os!20_f5*?#`vk924F)(lw>Y8;$4-YyJT
zM|1Q~kC*;rdes4S@UJ_<vi|OMWGlN^C^GPsEPyUK0x(h02sND514*Odrq0HyUk(-%
z?aR+>ML|yrJ>`XHlJ+<gp~pkhzEJ4ro)#<I*OYAZ!VNcz!9nDAKTh?by8EUMV}?yI
z->14Hwo?AnaP@^)myH*|V|hkLc?wP)1y3q57#g(R-}UTs2}DE1Nvn8-8$U<3MEuEJ
z2vPM&@3hts38@sV5$)VFhm%?)R0aAT8Vc24rwV)-q_4}@e$n~;sUz^>=%_sYc4azN
zBkM%0oepu#uWB<~+H`L&(2+@=)$6Ys%gLfaH+0-s$)aQd*0s{bSE5|^)9hC|T)!4-
z@h2NaO&YkWlE%JZgf)t7g-@wAK~J$_P}Mg3w*4?W=ac@?QRt3oNU-tMUJs%k98(&3
ziJ97S4yaLY-s}&>!7>l=9_M1?S+*E@3j4T?oRnu1q@jL>qge~dw@dFy-qJIJRyf;O
zvg_!W^OU8dxnrk}M}M;I;X|@hi3fl2$U0ykxlH(GlXhqekrsjl<`Z=~-;NJWk{(|_
z+^3r#S=MvLWO1U(nV9x%Nbs|{OO~?sx(4n4&~|G>J3KQfa)up{x4XF-b!Dzl)c`p3
z6^m)#=9+Ey@}!&A(U;>bZhAmNC>EBU+*5`4bb*p65}M6iKQ~@{`==B{>5l9nU!Rq!
zS?`DdiB==`v4>lLJ3zXPO4zWm0bsMHOk}7(d!|eh#M1PXRu=!nJ3IBESAH1J=y`Al
zSsM>1cM;uwA$ZiejLKl6*G`(Tr6d$yy{~*p&tFpPW?#*IuV^p<@Tj-RM^6(78fH4e
z-i8GuM1HRx)5bJ3->Ja*OL|ixosRhkSX16tgi8x%frkYb<z^^{@OCNAm0=ScyE5%B
zW{9p`-SgANt3xQv#S;MNwiJ@3KN@<BCjS9x_W0YV^~ea&+Z)36UDBrQ^s_5Dst2x;
zp6m}!otU~rKlD7#H#DVRePDZnjV=j6Np7QtN)1Z7p4Vt=lXmwSoxvvk5u=WJf||lg
zbF%=(B<OQ&beI7I*8FsBaJrRcY5e}E?p)CFM(qol_Jqi0`TG#!(36o(6w}3tMK9NE
zy0h9{SPFKzMi7(jOa<!vMi@L_>vXb@lsaMAj5J=)>*MkN$I2b*&tmKIS~e#!rwT!L
z(iVCw5l0F@og(3ac0FFoXHKFB&S?F%pOjYmj$qRw!-vpts+Fy}86xj>jrJ4Rkc9+>
zGMu_AKyWqc2lQ~V)=^u@sEa0PozdYO1?QBsZt=YLycafuI4=NHU$sxPii1r3_j~u~
zNN3FWedO=ln#oQCrsi^r=0Ddbs&I=B>rKqnY&-9hh9oR*zQd;U54H22Grt4ckkYfS
z_9wfH9@1Bw2h{#IR$e8DTqZYw3+znOJ!mBX<;oLeoFHo_dAs!mjR4fEWjhZK#(@J<
zgH}_fY)>rY664v$+|enH=PM6O>j`?|lkaYTX_rpRH}N1E=Wi}^(J#R47NUdpM`l+F
zSbdqBet~fN9NFwVl4}OW%dF4IG|BeFtq>PVi>HB`A^dOZ0z=8T_Er*c;mwpH1x6~a
zx*uBp=~flHM=j2I+c}##ww9kKX13*dPd>Wif@i(IPA3cKv0ikxn#XLnc)X-9O252u
zW$`-P=YC~#bVTOj90Ud9#lFcy^1O`*lc=iz=^@gFS~GMmov$7~NDZ>+9G&`_v$=-a
z)aT|V|LG>&KK3zuiL2<Z(yUoMw8c1BQyqL29EkX^`k>Z6YXW7Dq{_wR98MB6jx7uA
zf0tJRuTU6|+XXU}0|#F)gz`K}GpT4KbmX43-i>{!Nxd$mR57-^c*4s_Cl-pGm4>iV
z?STcoGZ1Ytpc0fRkexv*b9LyJUCeww^SpzEdbmV((M66xqmQ^GVM$otNFt?U*FYY4
zA^%a(#+#)UqTk`kY?Gb2m<9WGE@wZinS$!4RzQ=<in3?7TYx;yfyy8(2$VNpF>3Qr
zbK<jFIrV`8gq%_xdKic%m4_`wTipRrf<Ja>_Z-&h?1!5^h{nDapJs&(Ux0m))I&y-
zzGvftN<F;(S+BI-{XbMEYBq6U`|z<xy+3D!zhLY{>tI-ojYSn{yseCp#{CG9oVv#6
z%ljdD?6QuLkRK}LCJ;Q4y_2Cr61b`fb?mCV*V;n9D?hS#g?8;$XU|P1J1;tHh;d?_
zG0hkbnHpX3=84~!@B$P`Y@4XkLR)}TDVHBLP!(tk3Y&p31#eRfPP+G56JJ)lNaCH?
zE(`0hNnQvVMqem+?p~UeO}*iNyK@!-MLqeg-WhBhHD55v<x-JyQQB<xq#5+~n0K~D
zNLicC1NJ+ld;;aXqtkl{kQUSLHp~mfY3B`qhefmYR^g42XO|J}W@bUpa<LQ-JxAlK
zKO4LlvfU(snoP2WzyQZ{M!X8b*<61p@E{m4cZ>xMd(1gigLyv(<*4sRU;adtRx3ai
zf1PZoeoQNnutjuq;p7NosWI&WEv7M}Z(xtKedg#dP0(dpc23mb;$1aqPqemrw9l~7
z!+OJ2J*mZwlX|B%05I=;!W>0&xfNQfcURE^vLnrUQiYe~gc6e;>}~voVIcC3=&2M_
zOp1}zEoWh5=!*IN_1nex`&Y76@NWBa_Tg3m_DD)|qS%rH8seg9)<O~EV*b`yZ6ws{
z00-5D7|yVgy_oHX;__i`s^^sxHAiSPp+mY+`ga(uVXYx5Q^Icp@6;SMW>UgdNz!}~
zKa(CECn`>-x)rD2AdecG@)bMabW2PM9mQQU;!hVfKnkr{R|&PljHt3cYxd;=n~^(H
zif^LdD%>3^K<qqz?EjuIFPS^%Ai&Fv&1PO)DB7`t-Ba#+CT*_fusC?#?ZI?dm$E>g
zRfmL~!j|*cMvJDJ^<$Y-V29ab^_%a;TXS>@`61hWf9kUP{*ZXws{PXqyEu<L7^#1-
zO537c)m@rgDi{J}JF7PnE|K1)==Y5jG4}ZBR$(X2@4{Oz_BmOb$KeHj)|dNk>rBi2
zr$767a+N<$UNB~Yk>FX=7=A)6ko55Yb$Z|<!%*}0kQa4%+t1hRM(>BnU5YZ8b6@gY
z^_L+U^l2nv3q;QSMscBMc(tIqyT3)azJl=Q6%d~i{6O5G$#6$Q*Ga!Cf|Z0I_l0(9
z9rWY}Ll61xb2`o)wO?rkYtHo-g|T$8=3a1p0?^wl;?9ejkvp`(<C)Pzbs(6!4o|ET
zc(@B5Pt4PA%_}zQE<s{R5AlBCF<X5X$-_ON<`yckt+h|<wHM%{l@<KXVeis_TGGAC
z&*+%jM_>1LR(nKX^nf&cX@$Pye<yIG*JD<iqPQA!rr^yjr)G`ojqew)oE1)})kTeM
z^*NJP2QXw>3NgCbnj{PXx67mv1nimmar>rYi#hGewf=7x@kxP!ov;s<vIncUF8|{X
z+SEPVy=`)5hQdbeS2!CdjU+tr`*^fwct^t+kg3Myy-KOXmD29$A}IpD=R!`d7Ee=O
zIEl}p;Fni*`>Otl;RPB3jSkt|+gcx%4$kY|jbq+t5g}F|Jb^2{B()FJPQXSX8_|mn
zRsosCg^0E46pqE8&#Euy#*t!>pdw1N#+~t;^!daB;gA4L27KcJ?@r`-GuT#qWYZ}W
zC^GlX#1qc0#ml7?bust*Q^$NK5BVt-Z~fQmwmucDs0gLERBE-Afr9p9ZT$fQ!+~Dj
zVJ&7w{1bXAbilR?Nvjdedx}dfp;EYQC8Mz&$%&!V9ITQ>Zq3Eh)H`&uCNVqa8sv_s
z?hi+sjQS}fvERX;5Qvy8JNAUrkE<N4h+`D^$B;*kbFaAp9vzoPa|q7LNv*+6a=xnf
zG<>9E+ekl3uF=7ex@`H7?)gqlL!btxv~IoiZ#Tfoq)JYIUE9EmLUD0{!`dVpKly0V
zaFa6*%p+>sEX=+Q-WoESIWMg&(zx9Rn?ZeNs5%E`xGd#g;#UXG>LbDnr?-z{O#xzc
zn+KKh<(NH6D&%IZ#7&8r-~kiw!hs>NiEz#rUR?>kSXeC-!o`uqtwQ`;iRbgnS$Gu}
zbJu}<=&-CIAl!yPAXHoQO1TL&D#4i<7+6L}Qd+yX5?ya~im&G`L9%<DC7SalzR7F^
zsVM(&|0fkM1=fgN8K@L4%@$oHNmeU}gHDB`l*1G_%Yvs%H?@u*k{9Qv`t=EvlF3wJ
z`J7tsa04Vdt9#PI2S2oKqYSXD@YSC8klbxHHWZ8|yE8Wu+Fx|t3!EM5Qg)bJG}j8D
z_|TBG=wtq=s9>)mD>+cfaTgGV*H&<v^@w$SFKMh%V(*S0-dTc<fKtp$qK3VcucBx3
zI;!FI6IGboR~~55YL~T2zaHo{HjGNN!ojL-Gy%dBtEo~G^hL<gtB9f6Nlu<um_O(y
zQUj}+dZ>VY*-OKndZCJdtB^A}=e_<Dr1+cGaYxAOfiG9*uO$f9QrGDhC7C7<b0W{~
zFZ7;!U39%p_7%$K#qq3L`Z$yJQQnF@!@?m*qm8Sf>s`@r2JMG@%Lu!D{jV<G0?QXY
zaBFt6_hr1-e}3fB2F4BXVH+wbn;JAwkQu-WEwBW{6{Hf|b5;d5E${VK%_ph=u&O46
z)p-&t3=O!>amu>)s+L!3kjKN^b-?P;`!Z%rqOET+aRRUo_Xg-ARl?3ByNtjj`#oOM
zb`4%vrDV}#nUs}zf?)7=sF)>D?02XKsR(@ncwe_YP&p1HHFjE)214`W<cwY48te(J
z=+dLug~Q(K&ODw{xox4JWGz}Duo->6zbLHRUUUFv4#+#kP+-(ZqCy0V(LMo6PZ+3I
z$WrtuzQ7D>Ue7cgk$xTkA#n)g!6lf6Nm{k35xK4W?W%c|ksJ&yo9n_}>xVgN#`Eys
zc~iip>*!|if>XL~o-`8AW;;t^)wS@5bu1GpwRSgkXS`}Uo1L^699RK{azr@8p#uV!
zZn#N)C1_0IqfD^FK!dSkV59`A@xfw8X@14Im7Csn-uYp!8h9yvqvccZ{-PBJNR_48
z7NiHDhk{yO*UYU3X3_dTJ3!J{G@6Z<42xjD8|6PXKKVXP;td4Wp6EIvw;;_B!pWli
zbHK%(`t`i|zGVAyYQOp*<Lt9DOKSXBDKkIqL<I|#CX00N+b|=P3ic^LB?IlTCa82B
zmMGV$=lu2KhyT?iAu>Igoy;D(UV;IB2zmbV$={yuD@M0x4<v0mNE?!L!%2Z`L$8eG
zRa6D~H9yQ8tZUNZa!w*bt5j-5X`y++_h~mJNuI~FxAbxf*EoIFNa;{{2plhSdcf#?
zAdtYN06QF>bTuzt*CQ#av`p_nQ)a}<UVj!o@Lq1Am#t;im8MvSC9OUH7QWKfs^f)#
z?A9lf-*z%v?ZnW~z6^XZ1SO@{bMse7mIbX(SMQQmbNWZOfpuYlxkr$aL^@AR<oNNt
zis&ySrH!C^Ohgm|9C^u`NS?Yc=U3wiArdXlUs;4&-!lgr!X?+sm)7G{97wG1fBLic
zf4Akmx_1Nb)xD6s7L;FfMw?R+GY{LUTak#F))9qmUT(XUI4v;|;~t8?gCyjeU_-wf
z_(gB8xXg8nk)we->TMzqZktp*@9Vc0<Hz+eY?dw&=+f}&xXo}(!p%UF=;n4SS~P#)
zLjELc#3Df6iH#k8`&Ch&2v;|Ie)=bK9}0LUH2^>N^3ZS1$#o{Ham#h1lD+_Gt+YHL
zf~5Akt8p_pz(-e<uTsMnR}<E8vPnrK7hkWrjOw`NvV6BY3-Wj3Q1jhZ7USv9ettCk
z#hu?D{eVpn<jbQ2j{@<1kTSWy6c5?s@ITMzx2g@+w0Ev&ZXK*5|2hg=qA7Je6+(9}
zFQyxurkj?YZ9Y<rB;HrI3q`pp<K2m#1ObwGGUgza!QY-d3Yo9Rm$fyn<;Qp!QkA9T
zbqjPc0atfm(28yDd!~c##^o#%JHPqoo80xF1Up^*7q>qtn$fkbaWv%OQXwnCRk4~(
z@)@9CJ!-NyWEI#OQqHfMiJw7Hy4$_+{n0aDiqx?y*487n_omLb>{jwLsylInJz|2d
z0#dg>pkCtwb{Ns&I{>QU>Fws%&b-1SqpZf%lrh2*7JBp-i?inKh4}H*ZN)aXJ3t{R
z3~8&noZf@nE)A8^G;XBUCw$c<zpZD=h#mTkz`*s1UgKD95r-3ULollkr=~kUEg1)K
z=J^Z1LD0Fg7%a&_KuFrZ{Ctdqf-i7PjEMO}YBeY^m!)vmqr8e|QTgt+Mx^$?jrNAW
z6dvTeCC?6o2Reg~Bp+4o!p6&aAg$y16a{waO=<qX8gxGxL5UB?Z{7=Mg#~dBi=KON
z0ffaUK7wV)izaU@kv$C0Ud8g5^;cB@Gak1!9)Zk-Rrn4$>)ErbGr`8H7;Wa*Chtxp
zAAkWsVc8#ee=zmoDR%Q|hVz}S{?VVWn-e1ao!_loI|U=o3DM6gQDa`?ZD2!~y0ax%
zhwjVHYP|cd!o}azet-0Pz3<hX9f0(B&Aet_HC{-v7i2?_4<6Ua2M^-0LR+)X>PRyh
z7eA~tml<?1ynOLX>6I73e`Z8dFRF7EzBY!EMYyesmvd$3#o|RGAt^+T+W@DeoClK)
zx6CAkB6(=In!M@cM~0pZ_NDYjU+**d!=cvfw&@x&wmAT4x2I36n0yq@*vDa0yfV@U
z>?I@=-4Z$pnn`{>u}*wm?i>s?!fvqcemA^V_r2c#HcFhh#(t2cfci7QbA@FwOzSoE
zEd`M8?Xwnvf$6eAJtT1Q2V-+Mo#6)}fz@8)K?&q+2|mY)`C>7@I3kp~k=*S?w$qrB
zPU!6%r$45{gh{*Rs+@DuTQMvS5HljiEeFB!p0@^CooHs~GpCPc+eAR`#yM(3DLZ5*
zHhz+8<j$rzE?zW;W*8qtm>^K3;N721$zHx0yc0B25;Np@+->B%{~KR?5W7pDCs~dG
z*7lKPr`gT7E2l_ApU?9})QH6x!~};P@<A%rG)GrxcHuAZ3lXXNt6=OajIe}8Btc{^
zvX;*~I>w5*&t(r+QP>bNt6bBS27(2R7=v~NI{TZNlSsw`!IJ%OYbIu#6cv>~+$2;V
zP60wl#FQF=mQ?!A9deXI#?Gh^=h6trBaZz_SUqZXm_5eYRf-^piv$zxRqIzdAm132
z<H16_kfL4OX+i^IL1BYMIBCF)B=9c7cgj1NK0tN^$mrX`I&d(0dy#XxQLEc*pS5or
z#gSp|(>G*av4%!RF;ljNz*ba-SzT|E4}hf{(8R>w-^6nGkx|*PWHPhyf?Xm~Y?{Jp
zPC7O$LQfQq10h11|F`VzmNW0}2&^Vt=o^kNNN`zqSAkG50216q*H^Xzt6=sN<tDw$
zaQXSsNZs1yv6fn}5<$6+WF7com`7Bkm{NoZv}8pu@$&1{c-OjQ^=LO8cb-+=iksk=
zs~I(tkT{cAT`)(Uy=_|ErOw<XVMYNoUAFph!UK;ANz{jqqe*(vqBUOBmvsC#tq*J`
zVZHrR*q4d1?Bc1-Q(vq3nv_C90J@>)Hc(VaxD@XOQIvfhs(_?cXHzbviUpzj-IZEf
z36{eR6`0-K-Nh09V{(f3>bOJ0+!}jdNL|oB7?4|udWNS{#GI{(Vo^oYq?gAjy{TxZ
zW<g~m{xUIwwa6<;ufnRmXueVCHb#bD<UT8P6C%n*T9j7+p0KsSug84|gVYGd3+aSS
z%%e_g4#rk9XCbbNfPq}~^O-aIb2I=iXG6ELr;cy?$t&Od^jef4C5ry9EQgzK3Xedn
zWi^``lTE?KOoh$8IQ$Mg0m*}mbA)XnHy|hESI8>3M_G>-lJ1H~iq-HzlAsBksoY3W
z#`_M&iPeQ{uOsUCpg&5|EgLsIN4iO@aBoqGwC^XTi=B%IN)u!kBRT8^tiol7Iicfl
zk9~=dbUF^<IN}T0Fe++66Zo1$8%nd+W0+6asi8AVhOoP?m$0z^$+jC)rzB{~O}g24
z`Qj&NZ{67&qkJ=nKsI`mB*`~91v^B7z0zHJJKI9`22r!yy4$@Wr{ovCqfg2iIXl4j
zOt~v9$vvw9M#*Vg5A%B4JJEOM?iDPW$$Ky@a3BM9e^+N$xR<Fc#r|T^JzfQ_5ECyl
zK80FMK&b?MKk6KH()7xNbQqFu2s~`oqp^}!S>rS3YFjn3EUW+Od!a>gE5tp;akMM2
zVS3gQWjAWvNc5n){D+vqYE)7<C;8cIj5t^7-fOZkOv$|6Q^HwK+<k8G^dGOSg{*_5
zoCAB2SOg{bD3(Lbnld3|0#51Is}m1oIlJe@S@<bgly^8N-{W<-;yC#{!zvO2&W$8)
z!}~Oe8YQc{dvbBof~1HaP#Q;%^hA~L4a5`BuQz&Z(yZn@`lKf{6GKsEp}ZHWpLXV6
zVLcW<oc8kbB){S&JyPA%y<Q4j2^rGRKT6Ggz%GzkxbK1k5*~OoMZ|C~5BG~n719l{
z`tBlzR3VYTHwMG3gsjF{GR;TUYLKwI$-vxj+KZu~=&bJYUQVyW{b3>$#a(36y3M^L
zy<gyzxG^J=dOvY}=yuVJq;8w$8|sac+#(A-xpC+H5<tjww%8`5*JiGfgKN`MbboM^
zGUPM)kr1YB$YJ|~^D9CggUX+qCZ*^(^n)q6P1%Lt|35+W*VaJ_5D~^`q2{DqVR7zL
zl8OP63Y{uMq9&W-S4=7h6>AGYDMK~Z8Ej5HYL4i9A3~35{;fKK<zQMludMsA)TWeS
zPl4I-!Ro(f{6exT39}rM_^@hP;NL06R*ga=HM=+)-;eh3Qt3D_e=D~GDF2%@k<$>3
z?W<rXPib!N+}?H}-;x0j3JNf>XDLK=-ciaF@j3XKmtX9L&2D4$^7ns}V(g#R>5_NL
zUYs@Xi0V$p-Nak&QP$z(I-PXj?rO2WYZ?7AOW`J*B;RKT#Op!IT{BM1<NI6B>-zdw
z0<?Lv_h5AiJQiFGvJ`6qOO0Q>L=#zx?n3*Of%k{Y!yJvyBHJQPoETQea>bwL5XEO*
z-7@G4S_J0C=r55`XnK<#UF&wN+BW*^o#$Sjc5>IVD>&l(B<h|CA--+85xXR$m9-7w
zf)(_ar3&LEaDN0pFeF+?0YZ=vsA6qX{0jNicU#tO5AKe={9#iF9F27?@qt9TyGLJ*
zD`P{VPrVGQKpf40`Lg~rT_3XTwb!w>5USH@lE;VarLRJ;Og*cPt8xxK{Hz1L4g{W7
z70nwcsvu&48EgfByE2Ebhra6I!m@+uQRDW~URdX9Wzjb^_1dR_N4ydv<ZS%G>EHgx
za+HHX5mOQ7;l)v_Ot>V|m7K!O3uP~}D<nePZTa!}(I?*xe1BBRP>D5<l5F=3un}lA
zbM!dkR>Bmw%f(n<q9ZyVB2+@Z53w0u>W#ZcgDXZ><Hh21v1fSJxLsWPD9_8u1tm=!
z=d$Rr_~N+M3OJwf03g45NSGCRvo5Y(gNE>E_n`!A@24FWjn1#+&Y${l$|u4#_QUDw
zFWocu|0%=79~K9F4#nEfzs8nS9p;FEW#QT~@DT2$ad+q9X-TfWKkC+C#LB%Ff-em4
z1ny2h?#vovR>Dg7%F%U~;d}`(?oc&$SK$Z3eLKsfRk8$SkjT}{!W(Ay0t2%W@0V}K
z<J_iPgxQ2u%EgpS6^9Fh$uf-0CUKi<v^^K{Hyy2Z8u$|G(7}~ZDVw-X$NJdRWy%dN
zu*BL<xbffLkV5oM3eijB6BPVSq&@6Km<R$}NmfkZb?2UN&xE89cUyQxYTqN#4i7#`
zdP(&);3nFg#CyruSxj?8FBkPb2Q82y(H6^8NO0S;Unk-AZOZpW0(g&*Pq7rKJbj7T
z;``L(#UA~A22xp(;+Sf6G8Z`#omtqYZA_2E$z`p5@{$&~Kx(KhDfD7z>0x!*5BqlL
z6HANzi5{y2_k>KF7%BCqM9IJUcfUOWIPh_RaBrNSYXDU+awR_K*LWFHbjW?deozwU
zITm-l7WcdNg=~kl+%nk-7x0A?2cAD14h}}#Xjh5#&Svg07ohP+VFyCF_MbrA49}Of
z5CpB9+FINv;2i;C;nmxP0ujtAEWkQ~H4AnJk;v7&W87ogl~|30=#arpHf}n4m;G%U
zgxWT&mBVDBD_QGywuUTw?)0Yx$2<==<@}%hCavjzSP3^gpaN!3xLfjtq+n*tCdgxt
z`yTn?rr38^gt|fU!O`#__k>%JyS10<k=3P!;_#K7tyauSqx*;IohW?IX@Ssif^#{`
zvM0Da??i~a(-WEn!Zc+D-AMk$Lb*6=RV7F&C)5<0Bcdc^F(BPHrPQGDq6G_1V#T<r
zF`s9jy_?S6x#x~uF8SaAXOB)F`E=)r9{SaHE{)GWykXa!b&v$&xXmPzmy&y3gvP}t
z2D%k-a$rOf2zM>kV4AzEz3$}KUrw?TWR(Mg()0|--eNmQ8OP5^9E2pY%Q_0n7kblq
z-&!6)u=LB-*((?~hr<miX8fZ4zWzQ@f;MI(f4c;#H@rx81YR{qdu3}5?gyX(j7|PI
z3B;`#y;^PMxvrT<4%56G=ps}Oo=YIST8yGH_PzG!J?S5ux|3LL_Wk`A?)ey-;0|Rm
zppa-TKdT(%rMWPsM9U=6a_ww$L=u<T)pxfsp8n$}zt_8VZLEcgs~}gB6A0~#{{gR0
zIrE7cP^<RyUIaPp3;!H^S(akc8Oko;Dn17>+w4d*zF54yQ0Pg`F7PjA{Q1;v3lgG2
z^ojQ|=6aG+IS^sc$I*lt6@Xhtlho1(%{K}8dCX3Q>Oz^S$?P9x)iEzS@Q91%3QF?_
zkxvpTB(>ZCK0Ylad809-{JP~28w{R^K~XV{9Sbnz{s&6kus>`*n50cr7i@R}&xU<C
znTvRN+0=nDB(~MuGf}hZ^Tw8Q(JVD)6wl#x{_yWSXqc4@#purb+|ERXz$W)B4_tK6
z%+#gQ2Z5rBw36BSa03q7pin;+dsW)J2G7`jQO6Z4GwO&F-QmiNFXSsx$o6dezjKIY
zH{JM;%iArnphI-wa2sm0wrF(T)Qmda-&olOdFd0(1bWq)_~k0yfIT%Dihm_ZlC8B6
za|X=as=cqkh`0%4<Em6MU!-V*i;uA+eRv;T-umjR{$D_u07Xjz01T9hBZ?7`w-(f;
zT*SfX>zMO;j(lgkV^=sKEjJ^0YhzNYw`tS%Vr1qHyBrKftf8U0(EIFl^e6LJ8(>{t
z6UFyj?52DEx8Iy|=3KYxbg1IMXp$rWRtNyGrjMGvVq`p0>}#&$u=83i-&V>NI-CF=
z7h2Ig9H{*p%`bgyJ98h~#N)*)ipCbZQoZ{mGk!1zQ^HJ8<h4W((QTy>r1>_TiADTl
zy|(0Z%f|X}wnGmuW-~X<!h5;eGUSOK@;_A8Tw;*zXuwU{hbk+i_kVzbuNIi-LjFnp
zCW?c%2F5W!pgH>1qM#{=kaLsP=2M3s_hGoU@m6Sjd!ks87BGRagY<kyjU^2=1%jnI
zz1vX3H#Jq4BE%|X_3t(QxlH$h_PF6ng0E^EHLXe40t;rHUTkahqBEGE^-*m@%k$CN
ziTXmEH?ow7KIi!kP!DQCg(|Qoba7$I>==e48i&a9S`MB|f3A(f9Y|Cfj8&YqEmzUB
zv-k)l8>_+%;lmju?U5mCXCbqz)RXN85I9%;HKf%@O3|U-ioPmth0;0BRUXnR+h%ZF
z*1a4r1c^%R3wB~3w9gnur+aSI=$@yIMnczt;^m&Sv#B?GL~Ci#PS@i0sLdsx;CQ!a
z$!LdBmt-~e^wRLr#}fTcw3znv%t;B&%iE3B{sAIN?QT61c)V9z4=YOVKnqlt>Rjxy
zo6M%{<!6f+o?xAkvoBe2e?`>^QR$Ef_Fp2P3a_rgNLi7PcGI?Nu{>zWoVmd5>>JCi
zBtGPHJxupBeaL?!7r-KgkIF9;%nd?SrO6ho&vSNONa6izh)%bY%MqRKQR5&^d-J<2
zp6_!t2toNx2ufG@{PoqWX+7#g6?FQNe&&VbzmdYMZeCp}RbQV&=`VfmbJc+RQgcQ8
z)ic$)?%!^_sfYI4_bniBeb(3ajLaa+jMI5XJ^>2sU}NlPR9YGaQ5S@Fr8UoN!!^(|
z<~)JlL2l1ZYaU(fyqH8eJy9+WsLB(*TSFa?lZ1a1V&G)$D2Hs;ctJ>*+dL=Dz!JUd
zedg&VXuEyb@+H)8+VP;lWm0T~UMnsHhQCfvDSu!irar34dUiPr>t!w)#b6MM7Bh2M
zFZy^sy%v%j!d|Ug3_z@lnQ4mQTTbEOm2WHhRTiCU%eun(0vwyD5`H}&h>Ne1EE&>c
zosmcm4VN<h+M!VTIlE2R^{;2Q^*eLv3g>5!SH;+Rh;)NclVpMkRYB@e@<H<|=}#X8
zfoRYWXLNtVS!AMbT1tK3f3__aBcXK%JWNTF{;#+?UP~>jf(Z<$RBfMn&j|>dKIUz$
z*<1s9=mSy3<kas+{9cdydBB2PlS;LpvlbYok%8|qe(bA=blY2<gX4fBjPs;bJuzg{
zZQ=6aO;YzHwe85_&O%$rs2#~B$4MQ{O^jvtXO~OwL|0U`Bf_s6Cw|A3up&yLl^N13
zvye1r1dPEFo+Qdt*qJbx^HRPk{x2zWYd@6?Ak0PToQmSMs>3JSXYS5z#U0Vw?z~nV
zoAr`Ek+rcstC*|~HOaG)2_!g!jA6G@XB|^@Lt!iPi8D|cojEyx&@yvOaY07}M9zkT
zB@eH{C<MRl)EQ?#uw_E-BiTJW&%NTC;x1Tx$2vESk_bty=dXVFiI^+Og_FY*HB3Q-
z4PMiN4ug&^1hMqns+zjr)1T{}M3A4DxU%>-Vhujokoy~3vn}gt=XxW4;1H;L_{p`a
z1tHX@R3N3F5hD=BCwrsq_tty|63+u!VTyx&|9YLj&d=<k4IBk$)S1nI#6_}0p(ZB-
z^e~>SddbZXo&vf03|0CJNrr86fI`h$K)Y!F<%~?gh@d@sXL#Jf4D59$)>nMp+1Bc8
zS?AgJ1zi8`p}bEYsMPAeV#JxX7HpU`7@tU%&`j_eNu|_?GiKZ}x;toS!ptb$>+7mP
z9U3k94pq`M`nu8W5j}2WWyn%cev0NWs`um+*&>wA#aO~;p`YG}><IcIZ|J}tJzQ<*
ze*aU>zJ<W5v+(N0ObV)G7}~jG&tolQWwugbkrq&F3Ma|W?&gZRsx2j_olbl*a7m5b
z%w!)b9h<+MV;7c7KeVdsG)nv%fAU5Jr8-N(3~AAd1ui6s;>pGqF4bjiM#rnXMKwZT
zcE+qHjUm`e#PNTw#~t<X7yO^)HPz|y544n&rl~+mp~~%0b<Q_ZW?vQ>_KFpS1w$Y|
zSPf<-(!Vj!g<jRGy;L~75}Y!k`wG$c*34u+wvy{t6U#tFygqvayct)5!+ZTBt-dm_
zWEAqv`DT(Vi|KAn$0kG1IqGOm9ln*F?mV&W{1n{JboH$VmR&wHdBd70rIO$hxL^=B
ziQ~o-@WMKbZWUMtRXB4_{ZcXR-@)?<h#I%yLK4g61~seOMP3>mwaX;5YQAcFDYm{R
z4UcgnW^FE~<2#<mk%fn&wJG6Vbtr!fdy_${XDC&Aukm<(m;s9YCFwtb6}(J#(Z*B&
z<ow*ge)1>jN}dayy%20AW?syU+napG`(UmJ!|(NWPQUyUZbFjYKm5^ewxJGlFq5bP
zXyQz2+cji6XmGoNF#vU*Zckq(@Gq-y8Fb;C_h?^9ZpX!#W(0YNT2A6on72S*66{!P
zH5?DKQe3x&z)W@ggrTF*He(9i(eShyRL88?+s3U$XPd8271P^YqCS(CP!;sLeP(}P
z27~3G_E4)6DA)l{!A@_GNhJ?Q6Av?uYK83i5C79|DfdW<B7D;3uaXpFYo%S)?@Q{+
z-=wh8G?&zvfgj#_I09XWgQ2@Qb5eF5^=%F{aC0_1{VA9NUl3U)DQ;QU%i4V@@i2S{
z|86OUi8N-ETVNLy!`N1@%V&i5E~85QmI=8`i<9W)@g}?I<a3eGes#eadt)UzOjBvu
zDLK)@fdAZXl>}%I4DxSI8n+eNQ-*Er-Is~=nfs2#-Y$(h`*UM3ikFK}s5W~=vg1~*
zfAOC`F`;;4Yf4*eTWk{L+N<0``ZXPS_>YyAG|b-Mn`gIL&ta#A*Oh~1%VuAUaX6Cx
z98cd2ktUq}EE?2L)deE{0S=q#(Ut~U$O!#LCktiKCGN+!j=^QKh|n-a&mw$Z_mpQd
zm)9m83n9H;ctli!gTs-bTSaHERHy5giz}rScqC~^Mq4pBLBk?++5_?lZSE7%TcnN&
zkuFItq4s5tW$ZJ3r3`?!bG&r=#O7&=bRSN-v^swF-)Rxgt%+>K$*rP+`H*1)y(E4m
z<s?aj)uG3}td`F8LHM((JR5Pqo8(pSkVxLn`=0)kI1sc%0`GjRvAr)<|3T2Gb)?ud
zC-W1d)_RP_uP{XpzPxB?JX_Wsz!8Q0S*JG=x5kQnMq@eT8?_g#_T}rMT%fI=tLh{j
z6lT8kUie@LXOfyUz*P^kOYMg)W=gglIS1YEATSi#+OC>Q(XOf2sy7OKb29zEtW@xg
z98xJx?SUCeFgs5OZ#-#`>NMk;qMHVj?2V=bPVE1(vX;W_KP0WdjF#A;n)E?KNVm$|
zGi4%-b0%sS5*<ZkCdG;vpkSKR<T-Hfn&z}^JzY9(+>W98#?l)TS4t}hxXqB74|B6&
z_L8(6uxD1C3JiFutvA`MH)ZN9H4I0W>5Ks%gh{$t)9owH<EO+}MMlcp`0KqJ60X!#
z8dJ;-)BKX?<fX(+DkDIVGVF}0WWFwcG(K_91UZ4%I)xL|&>d<?>jCXkI7~!6Hp!$M
zjAmA0_h5?JEq~f6&K1$G0Vr3o`f!ia)mQbcGIQJUE^(a?4rR6$Bcbw8XnbL(7N;w(
zVpYX?JmOuN0@bd#C>TTqQN%QgwS*R^3}>5c5TxZC7X<i-OI$gH@g)LbD2LZSNm)q_
zPQQ-UrB=ZtXM<5Ud=sWk=m9d`Hw`bh^uH{e{WDMSWO7HZ)}2faGgJqdQ{hu%t~B@A
zD8%Rc7Ux9(jq_y{V!n0Mm-0^&=Fwc1MgZ@TVvmIrU<Xyu9<%jTCLb<mX?-N7K|5Rv
zA?-VOFOqX$wNB}(*%w8hwyi%HjSgOqy}h?Tu}z%XU&E|x^C=f|6wUnQJ^xCgJ`csE
zM&QSTQ8ywQq$V6uk<1q8_lf;UZ}F1uTvGp%XclXUj&4tLva!h74jYdJ$AZg-@_gbw
z=V&|~g@u(>8@GBL4|1=HP3tN|Fk8uN6@Et1=?ERm)G53(6imhULPr-D$d70hzm7`V
z;XI3vJa_;mhxRDgo?V&hG5&I<)z-yCE}IVgWv*XhR8RK2_r#Rg$kM34{Kel+M>$&V
zb4lg&9jSKf^q-?OFzSL#FHUvA6ID#QIqO|9bj*Za@*a=wj`|MGaV}f$$4~Xwm>o6x
zWy3tlYUcS%&3cC!L@7(tg!i3@T`;7tQ3RZtPzq+b_&@nEJDD}UWK@#vj2V?Z2}Toz
zQp1r%tJ(AHey7FgShVNIkQ$%}E>bKDg~&-a*p*G1{+LGASP@C?HDWu|o>eE)l^M+L
z&NGkDC)_I^fF*u0^iYWYo*!NL*EDw6uP&NUQBjZ0nr`uMMx*jh8D@b9&POm;vSS=X
zXTAh8ty3nULa@LSJ=E+w^z^5==)T|kd&bbC^aYuIoElhGFKA;bLj}ajd^K(&<7E*&
zo<l+oI#*43U$LqBq+#fRf?;F}`!ZpxNBL5ruEgN8&t-Gd&cXiD<?M9}2P1+aO@7Q+
z^dP32m442AFqX20`;&nkjBB#`hZY&Kf$VoBaYHCUkJqdbY}ftn(z@+MQH}8Sd@?4}
zVx!C&j_zgDn91d>z@^?w>dV<NY6(<B-k1IFq^rk~B2pzBx6k`(Yfs}VAE~>yw|*cP
z(MOX7z5Oe}9&^k*X+n|Q$~U<LLoyq~Q!iJI3-Kl<@vg%yb)Cm*G9L6;0gtB6;umm5
zmGyotVy%?7n#K8DMVe8Pzw?w?R1eTwSP$?G^n+qm)8wdQ4)x5rtRBf)z0Y9m-e1aM
zVR{38C}EN7h&T6q`qz=kaoUht@alO!NXuJ|uPZB(8dF{ws|~(vn%#;28js|e2tY1P
za)P+iVW$yVLyXA|RkmU>A&S=)BkmMcdv7qxbc9|b@Ofj>;j>{%6y5Aa*Dg{nUN}`M
zhSlKdn7OPoPm-i=H;&mr!P?<IXE1a;@9Qf~W&usd9USFl%w`D46mucXHiUp5(MBD1
z<Q``8sy#O|hofiUB+Qd;zU~vadTv5kg_|D#;`;gZBsCRn^4`SnLs*1iWeIpL_t--;
zfYq4skr`)is($S6vlEmi_jov`u;9{2@cjq<c9}Z5I;n?h9cIUvy+)J_aVgk$?740=
z(XZy__XAaBH}T5(oJXqhO*M83i7}!(&Qzh>X`=i1qAEA;FKjh0>CflKEWDGVF)lQy
z-_RGqm^gaOb*>}q^Zwv3I-OcHg4xxOwXqkLI8$+$*mUaH)W)%FXdO7mp1-7*i%ypH
zoCsl^<k!EWN!zZ;Xr><7L+An=>qw215gz=sqX<<d)?b`ZSJ2#Fr{Tw=CGAa5SNmQ<
z;2MrKT+^1cN`_9P$QN`3PY=;oIchu$53L`!hkmtf9ZJ!XfFFR1_4gW$c~UXJf2K$m
zJ1qJ@3&UHTo@ZwZ#lvvVCdd!7r?L{k33Xd8@B#H8V6)aXN(R`huOa?>q_D|$gaW*|
zOIeyA6^Gpoc@$%Sn^jRI2^NypO5PmO0PX<d{;aV~Ra4Y@2xd<pXpMe@q*qj)zeLdb
zm_~IM;g47oF@9?_HEOadfibmLr`L{;C69K|`$NYcC8R@{@%Rp`+qtZ<C9PVXk1`ix
z4SX2~b;XryP-VpAV+hh<$+0<f+#(VYq^!gWpjX>6ih4yW=&CtbH}q5{Hp<iv9X`N(
z6}?5@=IL$1brs*LKNx`$QH59MM2I0|pbm`$uUcB40s?dgJIvu7#v`hW-b1;pKC;-V
z@`V3P$GR!KtQnR5AQh1sR^Dr=S(+a4m~T@;t^wzj6X4x4ZNfRU&e@Vq|4=)ln41mf
z8CwNabfvnd>@ItEq`2!`;Byv=ky1zY7)4vw2ZQpD>>QVOLuH^q{#eInygxspU3A8s
z3mJy*mLIYnOrXl3$FE!}=|urvhz9-}AO0<wmc&XRm85;3vW-*-arpo<iu6cIe=E6_
zsOh#ad&*;pl~@1AQr7!Ft2MPGyR}I0Dzwp*8X8P-glU0}DH5^n?Eq#I7rp5dxb&xq
zw(blMW77%9q9S88;`;53F_=oQG=@oA%dsNme0I?{4T^oJ#9wwMAoC4TlZg=)2izuX
z+MS0xpV`J(ssZ9>;8l20;QDe>_h*YaxQNa{uDtex+f{6RMS4pmmt~u0l&E9`3pg?L
z1$(qHb167xZrl+%vm*gxuQU(aAT6dILsS8i2h&G9o`&>HOYIG#<v!V;Nv+xJggcPv
z)4HS{+{5rm<{hN*A%Z9VM~rTAsN#GZXMU%4tXD#8IrTZ}xM$Vj{e_!``G|Tw-W^Yq
zB_1!8vOkuXQt=rvsSwdXEzh+fNyb`VKt&SVF@QUw72A;sTyaF(cIbLGRK-S4r_(>1
z`|UPfJuY*o%s6y9maJ3sM>sUmZAIQ%0>>FuzZ?fj{H40phPSj6{Gd=bWxA16+ZHfl
z<G>b8ibi2wBq+Ku;&CTMP`7QU@*Vg+83fG*j#p~0>a_N;?e`fy)>Ls{JmsY4j%DZ9
zM@7z;7Prh04GIQ!>ukqB$_OwAM3MRrWmXDS5&0T;s~@W#ev>i%)mMI9aA55a^;sKg
z8WKXSe!YK7FBv81nZf^8QE{LWZY<-{7DRALnd6Wnjs;D!oj!e!@g%@Qbe@kq3w?!K
z1gnO1xR4!~!h_6medd}}Td&$3_(ZJlnaR|pQlgc<@1$jSWF0hN(lBbM#I{_(x1imk
zr827;W9nk~XWDy+4mJZ@F>##s*^qQ6F1`={+I<mQ=x+ksJ;sX;_G$w%>Ce~;NT}j@
zF5`!3)my(@klHYsl!$j#yP#b#M3LH~y)ZDVw$dzzLfRegCe46QJJEQr_jP!qRF)p7
z#hcby%;Z+!TQq$a7Vve2U%skn@-uJza(>p>wK&mVd>Q9csG!+4$;!9PXy`<Be{F&H
zF{-UPda9WkEO0F}o*B>dhc1yKdY5zP_q+H>Tvx8B=<ok?+xm)%Erb<OeOF=zOR=8R
z%=-+Yr@zgpYO}~&U9=9NUO}s6;S47KSi@?{!2Yw>>|z)WuqdSlfD}1a6}u?ye7(BD
zAFkFLy`F-R>U6e!t`OLv*I9!k5KXqsG=Qbor!t@dSvC^K!lry|V3`a|eVX~@52#gi
zB-gBdBV+D3JF%M0l2JK_s}A?)4y<!7zp{R!uUJ6}(j2PTQu!Gp;IRu7)p|(ZgL*FI
z`1M~Zo;yhbpgdG!=1ELmBH9?N>sh1E7)jAyuT#_ri4EgG!Y@<cbHpJw`~0*!l0Y7#
zhBoe;q!~OigeErsIYZg=L#4+UTI{>WN#kOJ?~;ZLQ1`R9>y4ywOmEWbk{F2fC5xH2
zld!KA1wU5XZcX`^&N5N;qy4{0ypn0<nr!+u4?n|$7PC?F3{XoC@KO7NM^$?Jq9a2@
z#2}E_>-Zkh1~8l=yDu=q)uHM%LaV|$654y;xo;@5pT3usRxvUQ5(I`dSF|zAvGyJR
zdViBqk=;kBh>@;m)L9uqFA7MZT7{mTmDnp@Iu*FFNt>9X&HJ{seZd&e5;Fm5C7tQR
z363~;5~htWYB8ql$_=`54gduZbtu%<OB05yY$5rk#%HtwMB#vEeR_j4=Z#i8<<ooz
zxtl{q{Y)?%Y$VRKFX`7(Tm{kEzVdr|r07lb6Pz*dD^gYCpM;d8!sBZ)sF_mwXADMl
zGrX(Nqsk$Sj%|FC5^pD$$w^lh1-H#oZOK@&Di(?zWou*rlID=>M2w#r1!u6~;UO#4
zbnIy?O^Uhnq0%(f+@W<`0=~b0;Me6eXce3#wts*a;n!<hjO1fUF0Qu9z&|?<tWd+M
zCY5*5d{gr(k7rpe({RDgVSc4}uTRmSLO-%4igmx>OP;4ZjjC6xFWL)5W5N3Z_jah?
zY0BC2`yKsORs?1)#Wh$8k$bu~eOU8r!3)}uRTp<f_ivf~*WTTEotZO>(rt@j%Q(+z
zdLaAr7xVB_h+fR0*RY=r`q_moTHq5}%oSwkf9a73i=ae|(^LBJeW{V;Sa1Pz_yP12
z$}o54wma(en)Vyg?e!4E3Aa)Dy)+1Z?(yhcM}9MDHQ7-{&?bkv6Ho8DK0i#VN$2k|
zNBsTTN^T+I3fRA+EeTz9$rv(tAA_OJ?Cw2JI=v9J=KHCFkj5VR<Wr(q{?P=cPLjv1
z{iePHnI+!3v=+XSXDkm0SxibG+U~!KP7rSDlaSaU*|<^<NH$14_LhkOJa2dR-ztn@
zu(zn8!C3T602H&W53JktLv4+C7U4e>0$N9+OY$X{E&6J~cq8FbcZ)fErE7Qv&dXB!
zN&6iq@jqhsS2p&t`-Y4_YAArdLj^u>Gf$l%$(QLy-Vi71^OCErDJ7r&HTTZB^Yk<+
znSVhd8qX6CuJQBBiUGs;<lJG*@hMylZTDS?;&^`HYrEWBSJfbz1~@t?g@~5eh$ik4
zsHvBV73`#9mpgP14+yxqBJs$_!hMp(-FY3VBm&w6^{UYC3Xxp7I99r%N_4_iqQ6+d
zj4^m42MFwVIp{Lix3cMMkoz`bVRJP!B3%~!%wJ-xn*)|P?_HC`$vWJ)m&pffIv4i9
zcnHktJA}NlE;<G-LL(V5*#x}$HENL*!>%&$?ueLwvnG#xa*c`U3cz{{xs~O)RD=~p
zFtas5p_O|jT24QZV`h<$_mNu%a!=Kx=lgcLOTgt^>_{}x{LLpI8?6==dh+?=WbRF%
z8}G0crGng^)f|eEuWLdB5FuQX9crv<vIAE`L)ic$R!d#E*p<awIl&UAPRSL@3b+i!
zKdbsDENxkYEmz%oQWPbm9a1mvTYG-lip2h3iIf{g0|)C)*5HF=sx!zY7%*5!Wy&t-
zKBBrU1H^1XZ58GWPoMUHM0h-nYyu@8fe*nWE9VgcNH@jNh+ZzwB77>vOF4ROZ~#<>
zVRLk*Lrjyd)M|;uT+x0m6@2<Kb%tMW@6WtzY(m{LH@EGZ)tkNvj=Dxk9y$N(bCP(;
zZ-G!4o^W6`Nel?1iWGud>Yu~_Spzo)+$BHVef|F^02F%mO>H1zN{Hc)ET$31vY84!
z!DOSyy{%quH$dGGgL2A&vi?2x;MyUeH9Sye^YQrIY9zl}h{tCahf3}J5bqE5t2Pj-
ziy?-Z0!WIAUaLK+VX4!qKQ!%h*-QY!i=s6bqu564z3ql~suPC3P|7y@es<|M{t3Mf
zd|cya^HW{Iu;|`Wy#16sx%>F0%RT)SDA{fhl$jT(c@RL3Bwt7ho0Q{KWDUAGNJVUP
za@Auz{RFoQn&&hfFGz&%(g&9yz<-{~=bF?Ts;6<buv#eglwW)mZ-~j<#4^@e2eVRe
zR!xvj1byhTdbvykKzvt?y~gm)fkCS)Bkkc>uO^d0or4#%->lv|EtoU-m7IY8>zmu*
z5V%`F#BQ$mF+vo`t4G~Hl_VUdFgK=hW!DM=mv9VA@~#C<_rE84rU(LI5%Gvd_@+Ma
zh&iIqs<MOvE8cCAMBY;@(!9fe6pBuCMLNiy{`fBpSNljPkdr{&cYC4O&6~IlJ3m*>
z&l;aA9?fmf6_vt&%5{aux<B+7*$CB#YjJqdsifmSZhOWup6;bwe-0ZHYo*90Km;ld
z2yP(QbmLDG*y7wd3Su3|l@gYdcP9V|6?!a1vk_?I<7IGl^S{!4@cmKuGH`{`=;k|3
zp&9XDiEj}Ow^|HR^SV$uUc-;Grx_JOy|r_;*Of>U2uR<$oh}tG(<p*IQWTM@f&wy*
z$EZ3&ZprzXz$dD}jo83e&?)Qj`Tk3%KRBrE?g;G}&1^E460oS~1x}s1EE+Obn;^$w
z-*=&<|I^zbRC$0s${q~Lmc6FC837M38-a{~FTcVH+_?-yEALXVBc>b&k%|)qWM4tH
zibtHSiYA$m$=aFt436)leT;7AL!2QPt{sQ4>PSRF`QjUJqdO5cl(`Fx2{?<<OQmQG
zGSqf)3L*I=qYD@|iGEN!mkoH97%AIf?ZG?JfvG5E!uhEmc#+9V9B^gw&*N#g77X1U
z=^D>RBpRedYnS2&#sJh~cL5X&z{ln!+`S-L1mdohgm8}sWC0+YxjT#qqY^~7xXGX~
z((+B~qD<bQKaY5c;;8;ipNz1RbHJWtvS5ZgWY&0}j{tM?wrO;~+6e}djx8rFrhjcf
znjyiE0uNl(wq3WO3s4^)5!5SCus7HkOruRm{3QC$wr_sg)ny#1{`Y@C{j+ukq+1Ue
z-^No98a`7J&ZfGJz3jgZ5oWCA1F`~afx8wgxm05@3J`?~$^`0lT%#f>Hwqx%mD|7v
zE#Y<VJma`X3)eAf-SPOgq<Qr47hIzRHi6oT*A3C5z_arS4C`C!2(;D1rQB=T;t?#e
z$Om8>G*lj((GCy}`7r=+TCiZZUpxyf5GVi4a(UcYx;mcQrNm%nrTF0~FGH(fme8`=
z?CUx68=RxHoxoQz<FFyY@S2Xelbx`N_!q|YojXB7qWLRO@$W1HN^m?QM6J}E8VO2b
z!9uXWM-(JvOC?Z2FVdxBw5W^*uJBlBe)}HeRk%sPf(clm%Bi*c(LC;yi(9SYcI&wK
z2QqV>#%NoWMkJ&fxS$oNmg_I*qk3|v$qA?d>&(*Ceyf<lji&UIZSTzS+^z({_xNnp
z1T&64esp2RZn>!?!z3$AZPJBMxSAv*h5!Wpo=Cu>3%H0W0Ep(@*r~Xl89VPJ#yo$j
z$GpJJNSlD`y+`MJ##iIk!S(ZurG(;mLdF8hZFO+n0oRk#JqMDUuncBTVww+wIAwvw
zK<&%lk0*{N#&e4~Jb-Rx9UE71$qf%^8u@W>NfX1j;K`X#@PnC5AZ4W@Ss&$B`$deL
zvc65<{Pb7di%~Yg;QuW5;>YSez72H5wag$Al-wBa5RxNV1Ub9zz4$A*W_-8hV<VM+
zC=bF2Iy>cdAvbpN3bBvcC45ESv+i*DlJGs4bdZLwC=rPS$&DQGvEs5xny@&c2ngl8
zdcHWe2szf8EV<M`Dx{}EFv|}Bndkv*rola^xI@Qme<Wn}>Vu_sd#{Ui8kRnnv*&9l
z4=%${aMywV`RK3zQTyHNo&_2pl8H(ZLns<x5eNfo(NIF-ub}(>o7!)D@nicG(nHZY
zb1RMvNQS|8G9OXL^PGrDX9Emlx^IMo$#h#QwvAODL~Dpr<UL4wY%Jg&#phu>q}-88
zusebYRM%Klu2qs7>U~k7iq&TTC%B}h5;ryd+nKdO@ymx-Lj74A=xZAO(cGH;LUzF)
zbo|yoiuS<uJ&?H=cSsUPOq8&sy2%i`+@wG@!X0%I@8B*^gPR=5t>`X*TOu@bCRouh
zh$p)`VUT%PY8T<amySWF0YPCKumoF9pnQK&w7t9#c^$*b>QryYQ83j=j>HN*ij|dd
z>+aaCMAaNO1D*&CjD7aQ^+cl7cv9bU^Q`^wxYMh59X<`~15`G<DA&S=RETbJbfo(E
z531(>L7Oxll7ce?cI7_51jM!TAjN{a0-T3`NDuB(hO#E&bniy8Wl`l2b~@ef!m`rC
zpmAwVDkmD7s(B@P%S%9*12otGXhDuhiX<OGiq_AmutnX%i$K}Dc$t9k#=+a!+@)+!
zsp=I%V;hX*wa?!mq&n~_Ka;tf6_SJ9(LKFqAFA3m?x5v3ZsF0=^U6CeS;tl5{6QVU
z=J~bIIL>Z?E>?d{HXtt`717U{bk<TVfEy6l2kc-u3wK#9eYfQsUt9}|u1+mHfSOky
z;9`)XXN2#X=mao$nQpamHCnWN4x;A(PZI`n{h2T9M3W@%LQaD!9HUyeZ5G0baDv`s
ziE^<ccc~PsNtL)D;SNA!w}YT}8juMIf+wlz&n#)<TG_J95A0mPco65YOWDrs>(gIl
z4W<bPk|S>RMgF>K?&DREyAf9E+CGSrAWEVry8zfkPB6Pr76HBgUE52s2$CerFZV1o
zAomwy7zR^imLgIfv)0qEui93f2t}n{!t<T5e5NlPljMl>0F@pYGXHJ2`6>omBTl)z
zYB_I0IgP=Fkglxrnb1>UuR$1MMkSDC<<Dnk0*o!I3+1d{doH$X5zY|<-G35YGu9Gq
z$>X<w?c>MB8)ZC1r5r*;jdxOTEhkvZ4BcEnxpCnCM~wtdu=eO@gAq|-xu-}$KX@Lc
zp<&XIS$3-FU>w40ZG$-19!Qr1vH@dM22vfU_zID!vj|*d7P_r(CA!Vai&YASv!%B}
zj)T1;c_EcSZKb4!Z)%0Ji5VN1<fMK0R_5@f&}nAEOgXPipL*@ns3G0F;B@t0Jy7{E
zR(2F<e9}Hx2>_4XJyjx^!C7<f2a*`}B;_9DjZ0eKqGfmOkb_7wjIG$(CBUPz00v4&
z`989m$bQH&>F(3VPcR}<F%P5qdfE?e=nkuHbcNjikRg{9X~FR9LO$^-a<t>QvcA7K
zoK0t5%(mvZPw8)j#3kqJaQxhknkH_4El!8_NVbPI&S-{CW<3};bRYVJ-q-%T^Ur%A
zGRgMGP_#g90${Ti2v%6q3jV&VgWQKwHxmck#9(b7upn#M;oX5|5(mOxa)DDY15@H4
zb@SRyFDF5Y4GSs?9-&oTzU|qKzHw<jh+(%Y#0$tFAU|LTFVS<><T~t3VEOPYXAr_u
zdZN{t%a9=g8IU7NV-ePcUdtcZ5YcT<X8KZC!@zjWoY}M$$0Ww+_<AtNn_3g?k|^Hz
zy?_5PY$%oTahqKQ*&Z=Jo*x9DB<Di8V8>bnaKiw=;a$hVwY)%F=A>4LV0O_AZd6uW
zGZGD-cR1HZTUCN{Df0S_jI1Orf}XLtcPC1AR%tCMD46BY>O!%z$eq}@x}YxSSdCZ5
zozTi+36G$TQnalKtE6VZenWKn8|@a>Ku_G#^^y3kd`7@iW;AB%LW|?satV{UteEFd
zeeDzl(;9BD`?Y^kG|SOAM4k!NCh5jv7xg1kl#9U)hwNuJU6iWnE)RzbCI7#yy$y65
z=XowTfJV+ZS8d5D%pIe=3NRc%Ly8h5M)5&?d>YR1Blr;nNlRs1T-Do%Ff3Dw99gRB
z!;|A}FoO@!2XaLHl*y%iy(!5+D&kcVOP9%|dwshk1<A0&_(#j;a<kr6Qe~IP`kqLt
z>Z@kGC;NP$ohEJF<D7H-LsK*W&V2Lzyzlcq&-?s==m&$<fwK`yL;r621`!2OA^8$p
zVgL_xTca=+9d@!q&I#bifRV+aC{RRkDwHah?i6b433)SUO$4TnZKY?b8QP5}{C%FI
z8IC#O*}|ks2Q|1Ed=9}3-jwc6plJSd;e4U$M%rDE&T*xizxon1{gdAlJ%Vbn;%8s@
z^*pKd{QzejeL5xG=(odR8ojOC+jJ{o5MlKJi3<@_K=|Y((aci4sl|>u$K5~CrkYy*
zqdF7c{j`2cPeYd})?@Sw<O!qaNc_+HXYC!yi-XCEsPUj)2pvhe{tdX4!U(r%I<Om(
zJJ&d3+eh4)Y8!bpU8wX!sEJ)~Pqpw6hvov&AGm#(>!GwLIJMX~^RC-JP6&NL20VwS
z-ABvE#`CjWTY+BeTqDAZK2&0$bpb#)Dmyi8rtnY|HSLHCiyvbG3B?vY^Y|ls->{F6
zAI=P-y22O{RtOF>mQHZdY}fUcojODy|6Xr13g6Y=NrM2CZhFMdbY~uaK6xPUsOWnM
z?l<o0DRGUa;{)Y0oDx(f+Egjv6mpv(u7(YB8+(SX8iQ4|-v!CH5A-4-?kfsu0r(pa
z>%ue!s)xHq=?S}gc)-*e7DxZA91+$QT|&Y5K71M)7tn1QMDuf-{>??wr~qgk7U`XS
zSl8vc#dMp2c-Rhi4rVMEY4=||Y(M%@zNuSP9cQll)wB?FSzVxE#2?9s^FIFg2z`b?
z?Fe1oxxh{j0kiPG%GDl~fV7)45h^BR#qJu!(;YBSodHuzkaZb~J^Xlej)Th0FDl5o
zp~OLL4qFr2J!5~uWCRb;)Npv2BYgJ@$M{jYv{FqaU!eomvyIS%jA$!oe8^ud^x`xf
zGv_z6htuw?je=My+7HG=bPIe_5mjdfXCkR#`=2W^uj_|w)sL6}yIJOlu^c~aJhJym
zyBoD>`p3yZ)GGK+f~+t!<Y1NIOqi-~#q{%wC5ByTv2et_!`!yatb2#JXhvQ^SW2Ld
z9mQ>t7|1k;J|ORFQMvy`-EV*}(u9kfGrnY~u*d*d3n_R61QR$y5NMFUI*VSSAkW-=
z?|!L*SqO?Xp7=cG6FF}`t)spkS=>wdq65+8y%V5P_9ecFrbZtn$PC`l-_##CtmF3d
z_>pKP9f``3y9uxqa{<V^E4ZCbu=HX6T%W6-)KqB?#F*PbWK0`&FMDj*IA}Zrg5xIs
z69W}puth6keqBhh0<cPuZXMlxLst=4Y(bjU2BxQQv`Vg|Q|WhO{PZ6{b@;s3H@VQ`
zD_Sc&d?@uB5HcVTEiR&l46a)o1|a(0MO!GsdW}B)ps|A-G;o3u`zOXk;-h4k2JBM9
z^LFHv9lBx+Mu)lvGjAV8wcZg>=tBXd2u>ckGeGsM=r-KsGZ5^+WR4BA!qL5rpieJK
z#i#EuHkzX2V1X4^!6L$PtRmF$P*QO*`NB0j*p|hD@Zk8NjjnNzq$BcyDyTO&6GTOP
zk}YZA7&t$<{TpZyFPZpPhk^sjDNGGKD68qbL9XnD%NEHm#`FJNgc;E@V3iQCsl?jo
zYWRUMLG~?|D{(?9B>5)VGMo!IKKR)Ars}hA>eGSN?RGd0WQ+9(A4hOdx`*i&Z#;2q
ze4si^-EkCq>1eFh-V4SqDAMC(YB`JzR`5Px8+JW?-TtY5W|Ixeu}#C7P5c{l1vNsn
zlwC!S7kC@pJT%-v6rsgbAS!Ls3+PdkhAoWUB<ezg2rr<;BuDHYTso5Y;o`p}#zYBz
zLZk<JD?^0XXMp2`ykOAYL~gvoPS@a~{4yE_fwGXThkXeO-Wq&I>Vv{BHSQj<&+z6F
z>$96D-SN?dEkcAiTs^_jB(_sfacm{)*P{a8g_$S}4qw<h(}vb7efawzPrYz#)PvOs
z{HDF_jRSlqwsTOJjvxDVt7etziog6}@B-b8A%Zu=26plcj>Zadw@UxtvX2&Hwny5r
zAqlREY{cCFn1$2A&-Ws#3)%vzc{tRtuQ!N3Lzs8LL+W`oY=MIjSthGyrO-?Ft(wWh
zKrFjvQIQz;gik8eViZESt@wMa_N<^A5aIz4n!wk&uHP;pC^=jh+}l@pd{AiTyDDsH
zwYpmU5&G2a<Jj7Bw;uSr4$>${YzWWskBMUNcXbT^*7W`v8`U>7KRKwwF%_)i&Pwuc
zmRCR8F?CNE4<g)p!&t-&UbH&{%kd-e9}r{Ejr)P6fL?Pl&~pwlBs??72(;F}hXvkH
zxMP=|=`kk@2Zyy~5-a2{d!680bRFR<6?0M)>>a^oJ1(Xp{@sjF>AXOrnr8GiyEYxS
zx}z&PjJptskFUIN*W=x_zY9P_K~sh5{`Vph0ae?q<G?Z6^c&*-0MF{!hZn(`-wQ)?
z8z+%)PL2P#0%r5l#edN_wO`#FX}Saf_bJ=zv-eFv%dv0y%rcTl0EYQxvNK7LTo*Ad
z1=C8)E`ZCVHW4s~X83`|^Xy3cyY8LE@qu!ta<qyrN0k(APgIc597(si?)sbB_0}}*
zG2FU%W-Du>KORnjrgUJnI^wQePbG1@d(bW2|2(r;gQ5;xS#N>fgUB4UOjj2i4s09Y
z&GD#S+8e=r-t$DwI+Y$RZ7Ri)$g+#*n6Q9Z&5p(3pR@MF8{i7Fy$M5NC*ILvXmrqq
zQDmm;Nc;#nLcT;HizJmger*9g1A!r7GXcK@x>``2{PT;}zV}_ywMh1@vLo!Lw9un1
zS0}v-n&{T=FeZpsu=N0H(uyq+sJg9xYo^eSyjhsn{24zTgMz&qK+9cEv^-)6579$M
z%imr8DjcRRB4L8;2Lu%C^?M8uz0;eFBrXfQ%>Fo>h7*IMi9relO!ZiR6mbBZ&|n>h
z#uM#Z_1)|ih@!giOl=9wMz2I+n2HA$pQCpY36>wEB%dS|ux6+Uc?5)XK0~;=WQ?Ya
zku0(B7Po&<6ivvbyNUkp%EehvIa<AFi0Q}>w1==(K!Qbkx9hrkB|S{HM$xV&l}@6m
z*Vg=71b&kj(8ek-#|{PNG#G&hG~}-@%MY)arEV2|ARu47Arxn=>h<(4Ft}>4U>8<u
zD%}P8Cs^pq$wPr<CWK$8x!F9NYjUPLx2PNSbn874WC(k&U|U7P+ZTWQcOak6!*Ut^
zy+R2C<}D6q)q(m6IeASzuwZxS%g~Od^zLDpn!gLzl71_4I|;ZC<-HshTj3cFf|lqS
zZKE!{X3>D&6l+SWQT`mBS>(Js%ugp$-i0a`t)sP0JhjdRAtP50UX!gZtT|Cx#;i7_
zJvvRO_W3j-?X(?+Kk+VtqVOh`|5vS2&#B+p^|o;>d<HNXbS-=LPS^)BWDA~mfBfsq
z*D*4UgS=0(dbS6~kjbHG!cHCv!?WR>nu)Z^;!UjwNElwJD_GWr@k@W}ee?3`L_~c#
z2=hf$g=csSa7-3i3s$opNrS~QXZ(~!AA>ad6nlbST;z^7Od(_vy{9HLVOAz;3ZMUj
zb<UcaQ6Rf96Q@Z8wq^R$>9mn<PRGs2({L{{o=oJHUjR)3ZJs{L9JT3O`w&E%59sl<
z5y{wF3~ZLWj7}u%@gI&tN|1b%cD)=p6u8@n)C?`?go8*nTz_80(G%Wb<6X^=qd&Hq
zgotyvJ9*F?hKA=dO)gWo2UHPGLtBGr7!j==wNL4KRN(jqD1C>|T&H5DcGJgFtFL0a
z>>BYVCy%2w=x^glK$`mI$qo5657<e>Ga(##2(O?{0!yMfegvv7TezaW^Vl-~R}`Dm
z+l63r+G?6eNBw)3?e}yNhd};@am3a}*3|msSfK0qfLBkEf;ysPiC8NxQl*SRQMjjb
z?v3G<IA4LadNtWyC6+^8htUfdXc~fb2}hoQrRqRlv9SW%OMUtPj*$T~72OAHTK87D
z;*4oI;m6zn9mjU<PrE(=VFw3aKnON<N!p6EzZsNSdk=_$864}&a6$cOt>)BrK{3jI
z)s9@(7c<trcB4NIFpX5ci3ut+fH>Ng>LFlIi<aVura7BHtPr`GLHLuX!h?gog)KcZ
zzL)?ykbE9JmBF)pNPw&J*iz8%M)be3{Ya!oN-#}EK!=*+8SPQ`;v@ueBj~pKJTjN+
z_UA?QS)@sy`pJ4EFGAE<6H7ZaC_x;-*L8Nv-h10ddWMBV=wq4ECI%PVj}&Wa5qOLl
zZE!x_Vr-2+8Gn2SflzLj>)_0Ii*0Z00+Cd3#nl?~w)vV-3Pf<&P^0-k@(XB{W4l{`
zyO|^Q?$Ou0R}dA8rkL<e#l7XZj#gF(C4~fa3(kXx2v7c;-DNXh;9P{%TTpvDHeNtW
zYWSWeMW58|HJZf&Zt=7K?bncdf@FYa4jk1KAG8I>x4r+2=<pxC9zUh`+s1)Fh8-_0
zn@7M-Lm*o8E#Op~#Bp%U)Nmd&hZobEBH_dX=`HDOi69B@%8=&4mN*(;Yzy?(i`qb_
z);Bu1UDZ$<!4eZYmYsyjLcD-{jxNRG-;9HJgd~!KdV*X5!LPl>paLWw)>{uF`qFz2
z7f>A;<thD%a@P-$7rgIzNPNgj@=)WAg<F%jC4ma&u6<_x!xi!5#KX&}ie%V{MZ0Oj
zM!<cYv>RKH^TOeK@SO`}BneM1wy@BR=mM`k>Np!ssL4Q~y{-$p)6HoJH<3OKlFs&M
zpKT32ewa+s1wlZygxhvk48K&vs0dqdLv0e`;Z`~FG&Er>+<kyHy%il~#b+oca36;(
z0#z`83w7odG%FN)zhMY&Sc^NNUn)e7xR(kAB*Rbh44!b+8xM><J1Ttc#EeAU=i)sM
z=8Cv4jLrvTA0+Tia(^1|?_#ubIeiK#bzl4m0*})JAEn(~Jp82{wz<`A*^%C?cf;NO
zNz#Rb?(z5H@vhYjwpO8H632co>>?nw5}7puuEckC`QkIAX~IoZ3ty<d28f{Tz}-vz
zukily<1DpgB}YI=CfGx;1F);ET1MauQvRYI5nSZf#pnyCW@_vo|7fbES&MQ03hxsY
zzG65G>`)tWe)g6hm8~uj2*A-zQ?j}Xd9U4)F>tM|WZ5_cfd;`w0g&f~e_g)$w~@z<
z=J(PzoK3f;)2(8U6rz!SbZeQ}LF*K>UPb>^(Fqh2MgUpRwOkD&MA@kW?QsW^tL6&$
zOpzauRk|a-W&C?Qx#Ep@!#p=!UAw^RZq3667Fej)+{7t>2KR7DF}ff*e0*25+gw5`
zWAuN*&WeslFut_5KVPd~S$Ca%9cZ&yQ*sK7(k~6yw#!+2!ro-S&vftBnx84Uu-N~q
zohdx84y%vA5vO0@1c$!X>j*5D4V-ge<uGxQB=Ia!poF<z4l$+^@-^Rqdf}AaaoApD
zh<@K9Xx>wZTv<G_w4zh6@*3Z&pp_)_Na%Y6V>U;+s{6yhTl{V5VQgP*>6P?~eHS|L
zLSzxT{UXL=j-7k{F3`t%3?ky8FaLk{IOHN`0P}3b&VKW%egjGOEb5#4D>Y(((b*2P
zRFq{%TV;71oDq_T+UH+%FFiw$wBsn*g6FPFj}00_)+?+jFz6w@W3TRHD#}lY|3v&O
zx(X-Wjs*O1;gLvsC|tARRd;h0eK9vP@*)$Rr8y-0LeD2w5L&+KCLY`-UC20LU11+)
zcg{qg*k1r$894LsrgHur5OXN0G~x`WzwPC@=#VwAa!($HYLM5bU1%lgR!ECcZZj^W
z+Ym4so9%<T*x?6^3_DmV;Yoa?Y3WwG+0q%pjds$r%ZRw-3L89gK=ctIpvR)$7}{s3
z=-~qL4fxn^8=u*Q{(h{2vFJ`#`xik)B(D_)*vO^Z^zwiQJ49BwDEE2YIENwSL{U+s
zo@NA@kHGA(3=dR|w&9VPLGt(y;v?=Cd8Eo=*)Ye8KXOb&3Xbzv;8{HUft*u8v~Sie
z>QDow#Yx*{i;C*uy|9WFk#X|LME+m1EKRjFy&WlGivbwgayw(}YX_m?NgFsLLuO|l
zAzGj@(0ITpS|b`YEyQ2~C`W)<>O#tdXAV>07$Bk2(w4=@ZIb+UY0x}cUDDoXNNiAh
z(|}51r@<@@iE#P^eh=EdUP+f*4y5;QL2t|CU3WaUVpA9jvjP}t$LR=rnThJLa2o&F
zmp_R%IhYD3pz+bsWjviN?66x)@#NDP`3oeTA&&>p9wfd{+YSNT{<2HyQ@TE5Y}VTh
zxRk1=KpksGig6G)O#BGForuRD6;juWgS25n^Uy{Q4ZB#*@x7r>ccnIW0Zy4An3D&G
zpQ+5U<@o!BO7eZ0*m5Zk1E#k;5kw>F6`>d_y1E~CC+<y@Lk|2naoxT>Q)olmB*>JJ
zmTQ14aBLPPC%*?F{P%FUi~7s0ukJ%Bq%lydD~SYO7>)s2u@h%(Y!+Zl9U!xDu~)>~
z;8FUK+RnD{NxKy|d-S}nP9TrM0=@yF6WMK}YuR8mPcl}1PDAz2$MW0>JJ1Z+Z-)i?
zY9r!76ixdVn^x=*cH`_|ITBk!<T%0(a2E<94E@8rRtUf{jEY=n3mzhF@P}#bih+J#
zg)0TEA7lV;1bxk8tmmb`UE!i5h_Y(ij}%Cu5QtzYD=h0rBD^`i$>_KD+B4BF62ul6
zSZ=MAcluvp-%MVB_z@7-N^)l<H-y9fs57=bw-6g^LOUCnY(1v8emcF`_@a)c)dUoh
zbhoijFl#p5V8=zPDD0$fC3li;3lB4l=gCm?5S<$<@Uq*Cs*WMbN~B`<yZg?fUo-ku
z_d(nJ3U!Y2)DnW4L4q&1<6_#4DyD>Jt$9%wHSg>C=$G6hI=Vd;U`__6(3#V>;jJ~o
z0n|9051_#S^!veEr;gU4pIn^+MWm!RwcAD$Swwa_VeH!>7FA}*ISoMkqa>c^^`>ja
zAGV*j^_l2a;JIJW_XQ@1^`zbPTtdj=foTpc0J}gv2LgsL+Ixj}^{bnVut+PsmH3@_
zCAot@UY+O@{i(bF+-6^=$^~dc!S7rZb~UiP5jD$ZfAlcmKiFe!W#iE^0A`<d_f{h-
z!>J`<SvcvvI>*re27x(M{-4*Su14(q=%oVjl`h=N_eQbLMBN+4SB-tk>E$>stU~B9
z2t6y6V~q`!Mu@-hk7rk7x`u8<=`AV-vU$d6h0xQ2&=VCNY>@dX1y>6X4W$->&NYtc
zW8lEN+!y>KAb&Ukh1_!y%_o;G9UPu5JYQ*j8BO9=c$J~O28V<bmRX|ZVpPfLF75^}
ze^VM0G`!XL7W8dTP<XbiJ+jodB2RmR-Z8Lxs*}Mvw*7g?pTztc_<cVhbx5mnsC?L>
zWP+wD={@ML-Qn+O|7G200egDw!dnA7aKv@(GFaqG3B*AQ3w>H2dK+~+YR(!)vF!w6
z>E`^k@Ex`G`UA@lK2H|7QHZBnz72S-o05e-uMh3Y01~15DY!vGofd9c#KUR2Vx!6y
zE&L!2x2_}ZAM@1eaSCo4h5Bqv>*bL5vQIUC0&G7Vl7f#SN<Ptc6am8Mz!U}EY!uGK
z6D25sCdhHf;AIPu0u18o#cJNDJ+SJAeLBvZP0`KR9Pv$?0l73eZwO+oFeL5oZ$qt>
zyn?a~LHF~%Km{?FHHpvxVJ6bl;IjUeT}?iOcsGo9lU352+`P0I3u+Y%(^<OARx0T1
z!dI%=G82I&rNW#IXdCbzz10?GD()_OYpHGcu>KxHpOAfXg;XhWU96@t?yYd=*@*#O
z4*}mf?NAZVN0zcKz(KJAi2;(X8u~q(h;4-H)PJITtHrRe7SV~z0?S6A;Sr<jl!&t}
zWCIg;L=DRvVXW}^MQjPDaWuzkJ!yvx`eLOTZ+bM|J$zu8e|@Do!qG_xkzzN-y^zES
zhG170Mf({bc?czITVdoKdqmHqMI-`_X#ehXVUQm43J2%~VRL}_<v4%+r+ze)$SYS}
z;1H<s*vS3V84#!nyY$B)ev3wk^3*?fBb})+gp3yf%(_v8#hcPJF=%WiuQQ?kxQI0q
zm}u-O*I$KZAHDH>IF)_Phg4hNVMk^d-$dJnxwf3SyGT2e&!ATe#QL}>4^>c{$15m^
z2@g`;zp1ACK{oHg8Lh9>b)Kd6K3Ry|VdIf2Ab?Nt;&3&&x&U6eXDNSrYCRg9qG%Pu
zIE1j;9tL!y8`w;G+V#k;_-0ZX`X-Rze<}$@yAB(sz6pZ5_GS_~Z_maDjUL36kGJf=
z*$%|+hBdT+-ZMCUJ0RiHv~cT1b+grhew6kwCCv{N4otEqs*&fa7*+mywd#$g$OTL*
z#IIX1suDE0VQgsUb^n1Y<Zd+DwHKUS1Q#xg?4^YYATKXAVJ)E7M)20-2PJgn!MfQd
z45g!xgyJ5WX7vdhJ=D?14&77yb^lZo+N!hLX??$Iqd$|Kd?$kgxeMhS^0!7mf_Ks-
zAP-H=E67rO8Z6zVR(5)DlM$-e%?~l~$_^~2-@?n6MiN)5%UJ(;%=C+oCYQ8E1*J_m
zjpA@^LN5Uwvs(nZy$Bi}ELb2J9d`AVnMs(O<J5WIL$8v7>a&f=_Oze;Hy^3P!tl5F
zTM%?KVee}4>-}gefUZm`>Z={UERg<SWt42AnaMO0*=1+8kY@7h4|8jw^JKun9RT|R
z#(@W*h9lU2J5JeCUT<|ElZtLZW8ZkHkpE*3lV^lA4x+&U_&kCd=85LD2tlK|YGY1-
zDtje;x5N$(&lN<&+4F_F3>>M`DI!|s)ON99`Y_k(h7W@pi0Rb9{UKLxPq)s9H%HR;
zl-`~0w}(gxfXqh-r4z)DULsf0d*i)Aql*Z_Le(>A3@%*^z~#qRH!1Afg?qdDhQ3|x
z(4moS%cO|gd6&7}!=raEB`z%Ul(+DG-t{s=XQ>gU2zbS04(?<Ro&yl5UAo>f$FM``
zg)OXU#J$8$@7iCWt272WAP$yS@81AP=<4lt|0sn!>K=8+bUk!M7tC*w*VcppZ5hZS
zGaob?7bz928A>0Q%km-NS6H`z*t7SY_;p)!8;=WX(f(vF`8L!n7q!6im>XS<I{<W`
zG6IK&Pz?+CkmM;|&w8n#HQh)Gmx`tLmtfI;q*B{*aVYX+jp!#J9n^1CMetZ6BKT?7
zjdCvpVNdArFt0JacI$aNQ^hWKoPOh3FdY%;fzUEt|C7grDp0^V$lHYH6--vq>ux`o
zH1K&6w9hoC>nP{~!T|GupsXphk)SwzJVDUfNc=H4&v2*!v1kA7DCn*=`Zp0Y9cmxX
z96>=)VV(7Z-bSrXVJzoE=XD_ms?lw6CbnfV<jKX$v*@)R7j#d0y!A%ueI!_O;`Bi|
ziXjAq>>ak#hzLY46C;d}0Nj_u>_%e5MT^%H?l`QPzl7!Jq0I-o<28P5Vq+uHYB3Pg
z^-ms$Mi{9z#$nA84s_39aZ;iRynoh44jM=P`J|vd*2s#WdI@RR@f#nH{tRiD5X1<Y
zln_JI)RCFBJY5WG{2+rwGES1oN2~LK_Y4X7HqC=FEQ|Dhm!MzH+F;yOI^RmaOfVCW
z;~#h*Zv)TE9$2Dti25Axym%+Z5#1YbR6rsfZoQ7()kbV}W}LmDr}WlIw`tg9uf|v(
z@0nx59JlAz^K0`Uc&pU)A=yoIv^s2Je*?`ys3g+~!FP++)F4pD0bTfDD%2FBm5(<B
zZQ#Jy+)6MHY7$u?5EZjYOoLe>l%9!N-$%9$m;?Ai=+*;84Cq~_32a-$d_=(fGPzs0
z)FzY=<kG<;91>w$S$erL!X~{JIl7$GVXG5ZE7BJ5-)*sfipsL--|7m(l3mv$HhC9-
zZP)uOP$T;Z!?QJR*J5*>*dA+h;HYq|3HhN;#BW^_gkUkkPZr^NZ3Uom{wr+=(853)
z_@y<P-`ed%A&liDJ|_;TZ349K_@hgRtjX)v&Ps1R+7(r`I-IOi^;EE4Yksnrk(p=6
ztP9&z*itOMb_v{9q*C$cIr^Y2#n4DqaYD!#Bt$&eiG@bE)!#H@8il7_UAyhN7oT%4
z#CR76_vQYtX+i|D=J)pHZ{Lf0er+2N-4kKIfF2TX<p8D}6-xjM09T7LnAiww{C}|k
zKE6d}%?R+n9~Qhmp%4}N2N1t8n7s&iXXCT+8z8~tDR~Pd3F}CpjHkj>@ZTmyOpcik
z(zBQWLIBX~4Gd$x#PRT9d&g!k-6%an0O?-kN)kCfz@wusct^UwHLXVwk{w2|a!aW&
z>tX=_wU1QBkCr3LG_~{!e|54EoLBMuF%Sab{@?%j7Y+tYg(7Cs4B{WCg3@Qm<~aE8
z@fyW(ZRXadZ_TmiSJ@1OU(Fi-8KVGCFPOB|GXFaid2Nmak`z>tg=@8*pbnr#5Dy?l
z0ok>yM)#bxU#_f>cQeq$Emm-v#9yQRm7{El4)Z0NsUp#EP(s6%PeCBNs3Xj3)9vf&
zRfO<!(aA!e`}nEC<3F4Ms(cgy0cxSW!o3NSFfkJ_4xf6*4<*P43qdeF9W#3hV;~4I
z7y&$iwoHxpyC#hkE8$lW%dZI_J~Vg(%M%_}d+lCOJZ-Svg&ZhDNFHH7TsRQIHef?D
z!>9!d)7a8rLeN)i90`kC77;zbG!`~iLS25GJX5W(3uX-Fz&(Q2RD%S>E*5fy{vnbU
zU!G<aqj1E1WN#nqN<||N)(9!6;9P?b<TV6Qm<gb}zGR~L>)J+8I~0+wnOhLvh`)u!
zD+Zz#9qe7(2x}6E+7Nt9rt8=LQ23d_C>7^n?OX(5r7a3RJ7{2c;`aB*adw122vf;F
z6i}Jy;2vD_x5H_02O<z0i1;t4zhnh)tT-3%#KmYNZ{U45_zGsiF>k>Ivru%{hd@>|
zL)?Om5XS;&u1Jpr@i}q{F!i66Pk)WS&L_Q#E8aDbpBo3n6j-CWewl0l0sMnK0RtiI
z*Vj5{^y6}C?B|+ZS}bI-iHogKY{(z`P+ap<UON<PhRQI{1-uO1Gd4vcn8Wsk0CbW)
zLbE4~{)$)>I2{qSr#2669u&``#sSYH54>x@^Kc+}BlCU*oZ}nD`xP9A7h~S5Tr|JJ
z99qPFjx)h%Jtg1<pwg#|FYw183o|$K$d~x;%V@0gRy9=xHar14<q7NuA9$}XP5y##
zd>6-p(6i_D517wzxJzSFyn`iiCtADk4|d1eNPNt*@xlLexTc>M6GC{J)g&=r6l+dA
z<{J#1Y5+T<o$Me40fLK!f!GNbD+DfDYV+sXB0z&NClDu)XDZ7X5iKB0xU|@tJPtX*
z(sA(iR;x5aNdc<i4lO1W^g=8vtp2v>*dikSrYmvLL<1W_Vf^jHBNag1)vmYLOWKc$
z&_{_b3N`xk=a2Y*-bg`cgHU17Kkzi$iwnReDZJeVgmM-Wq82TZUqLzhp~toe6wiPP
zFXCp5uQ+sSpO+lKt?eL|wO}pu)^`h!3RSd(69py_A=O+#MZidmvpBrp#|1z%Tp6gm
zi-5IyVFIm009A7~$FxR(++ae?=pmG27xgB8n~qGV6$Rci`T%0aEBdh6R!+J3z17ON
zmw&5@0`J!*FycZ%Jy!pzpM3&6@DFxL5iVhqn8*Hzr2%;mVkWq4V<xN_(2MCT?%`KB
zD#RWk8fu6PLL3%CFgOqu=iVK-_Avmc$?gjH7H`o7<Pbe?0^{G~sGbivfAH<d+s0Z?
z2{97DdhFNi-U?zy<4&bImQ1`{sRC4U#}Gd=q~je`b4+IloS)Kxo!aMhBoW|DCVr{|
zAlWor_<_B0eWdWi7pV3!uwr4{1pTO39b&Ki%8!1*1rvK_&admJY5)w+B-XYFEDR%q
zyT|T;A*i)f_*K0A)-2ay9{f)Hy$onx!WT?@4i2K^@e-mk`(ZxcNRrUVsG=>u7lur%
z^>o+f&(#c@Fi<2uTX?^+h)9EAg)G7Ku<gdnWW@uCWMQC+%y<V{8KcGHBBa#1s2sP}
zT51DKd4YdxMl}3wGqE<xkMk4}Et0@zLvPgq5Wj0nLPQUL^(Q}XF@*FXh2$ElDX}qN
zpT<l;9|X~52jg(CHU#)0Vm`#KA9I8F9XMbL-H;H9d^j5*8We+y-LfKDOOUvr+I}CD
z2T@!GQSm5f55cf=EiC+Dp&P<85m7|v9R`Ek+Ol{JYNH#iHxPV)-&>6_#E{rDfgacH
zp~Y_k`fsv<Q=k*8z8L)$YfJppEo^aHadfs9BBxl_9HjPR@HP9|Bo@Y6vz0^d`~ESZ
z6uTu*UVm#1+T35l9#M-Ug@S7B#K3^m(#el`bPCl_O(P<*h}wieuc5Vps0C3N@3;+W
zVO6_o`Ho^Tyvc{~6{pAMov2_6l?X<mA0iPqj_A2^5Mgwszk+l9MhRsWY-p2S*F(a}
z3^5cCULC^0!@6j#fXyLtTb~)#AH;O1f_eMo=+ILhyrezv;vI%|D=!6JYQ%zAi>PlM
z{=J`zC_j*rxnRlE5?bsG_7|~D+z~xj)|w1t5J}WBil3A|u7vRCLBv|C5v&a;$<mk(
z2Mz2HiP?Tp9_<3`h+0|3>H$rcHJFy^3ppQdlC^*a<<5f?%|>3U9Bf5K2|Xe0U+M*V
zpIUmoifZ)hNR}=Dctg!vV8J4-6h3!NC@RgE11*Qym1vbk2KN@O>_;0r#~H_L7$`zd
zhzTL0>hAyf7uDtHy;JnJ=&m@{M1z>bnRr_Uc?ISJ20$ze5lsr9<zuQzkyi<)b<Bn}
ziM^1LA}qr}ECg!DaatGzbq+K`+F7}<fYe$=4?9$05KyLe!)XEMrkD@p@``~g_(BD0
zy2Tp|iOv63c?AR*C>q=)*pDEwhD^f&`xI9%P$rz3m<`A-VGXf)w4)sW)suy{tA%cA
z^~AhBZS2{vVIV{RA!3(XKQ8@32qAjU<Z$k|??h`^{a)nOLRUz{st}vxnvSe?SbTgf
zT`i!jby`?c)C!G#FMxuBB^(+;Bd(z1&X9$^({N(g$$_&$P+GzWAiWl2C7KM}WtR?;
zQYC>kaq#TRmD$9*l^De0=xJI7eNDIor(I;0A%W+=A&yHCM!7G{%`6tS6e4?vmqy&n
zg+7cMJTRe}5S_@1=skmTLi~N}-~RT`HDp3hC)#fK(YvOEq(USX5Sk;5s_l}P6CyLl
zKwy_d^Q?~tF>L<Bnlo%|5D-W0pQ%OFYbnDRLC=-sg4G2sG3X)z^t#6kMY;%G<vI2A
zVE-;rYXri88B?m|{g+=}yt8;2O&Y4NGq_f<+H~N2DdmBbjUHUMcEGpcD86jg58P$O
z!SoN&1@Y;^)9gLw{cZW(Doa)oVjo9#F@3VOKZ;gNpBlRN;)k6l(4*N!`)Pk@F)aoF
z(O!DLfSjN)1=JL;&0~>ch~6vTzVYz}K^SQ77U`8}z60R#ww{5>C;|Z_(6a>FBRWM7
zCeavXd!rSsSB^TO@dy$u*gclI(1r{%0WCrox8QMHKAUW7y#cSoJNBjH9-Z}ut5DcN
zFWR9X9RSSW!0`&v6OcABBhY;H!BW?iOlt4JVeA|St0SXsm4{Y1{|60HLJ_%saA1Bb
z^)Ql~4^xY^BVu#yVTrvF$u@Q}Z0azE6_Y@KP1qd(Hqnne2%F)je)^BlkWC~Puu~TS
zb><84+SXWG6v!<SHp(iB+BFdnEsZe|9!4W@A0`7*EU_oxz(nGoIa0Yn;SqcZF;wE^
z#rON6J35Xo;_fkCK#!FjwRK^dM_pm?uobb79zhV5)>~#qBlaaG0;ur<0Eb73pwod2
z=>=Z5rk`CyUBrC&@(cH(+<x)H!4R#<-p~QJ;BVxaA8rj#?!|Oi+a1M7AaeMa(_zgb
z_XGU32E0Tu*D%j96WS`+BAEf&oM&A;64((C6aX9)NQ8x@!IoWruxt0*po)sX0nx)s
zbawG95!@JYW>UO!3Ek8@egUG6J`m3EK(R1#x~{vT8Bw!eq?}jmsxfYK!&>GEYKb0Y
z-yFX<SOHzHx>^PPeDb*u3_yXsyeESd`U|tdF|jUiG9#@(D1~Pcy#q-hlr>^y)DDU`
zLZ6yY_+#~;00=9Lqs8_hviR?2YPC~*mOX$YlYSd>BH7KbL%fv)Kd9klu;#!W^-y($
zGfPVNsn?QCjK^j~le9LE#F^Qf{5E<}R0g1M>E)0{T&S`fHp{%Cqn#``LaKUQzm5n>
zzn->_xKHcgvABcRUnxfxy(B$Ay_d9e6X#%rTH7YyY*`nT^M2deMq$-;B0#j9Un(xf
zis7%Qz_uhSbP5e&)s+^xDA(yeDQg*!864B={GbGD!3;TJ=$2^!1(Hrg^<MNlr&U;a
zOD$o)6pp&TDHFaY5th)?vnT9xvqKIlYBp7hmOtxj35S&vM%GppyJ+0K^g!01m9?zl
z6J%2ey`Iv*_iU2u{2_l>>Trqemn044nvkDmW$|4HE~WV%Nir(v0Ic-*P9Wv3^K16z
zaJwYAIyyEf67Sd$^3{QKm2tgkwYbjCqBKp+P}Sg)H0Azj+j^tb7ugRWQ&J^Mazg%`
zueE8~QdJYbI>1gD@Z<=X0g8LClL;6bcqO&NlCI;A9exz%C1Rl@2`Wf7EYom^%$WF~
zW?iYn-&sdtQn6%Y<vLfk!_*AVGoriExPK3$&Ox%Fqc!Xc`507f_$wrDvkfT;qCv+7
z{0o0nNkcDG{9Kaos|jAlvc8aC!|0e&xK*~L>;&U=GQ0@zkCep^@cOW^$H*E=NRbNo
znE!sL_A%n~afuki+F$rMJQIv2NGMVZ!H@BfKuW>rsu<?lYw&sEzxb{ANr<hz)z~K9
ziXYw_Ti9b&V2uZ2`aF)cY&h(Q`n9wr-3m@F4cl9YWmz4BG$NQ`3<^82ihMC0QJrbD
zUb3NgLm_%myogw&f}|*h6M9;03D1Cn3la*L8VPrY4Zn{~Q0OFkVk|jK3nWto>g+h0
zhI6D8XepumJB*j&MWW?42xsDDI0`$JZnWXl=<0hIn*Tw6-Tb|swNI*z$<IIY=cD@b
zpL{ri|M-J{`dvuDQ@#0D!;*o?UZ<4WRh5K%@r;83laE>~x}Pzqk-$3H7SN_i9W7bb
z9;aWOr^8MM^GRLYDhHU>fq5@ATQHH-ot&y8DV26fdT1SQmL1(TvgV%zQtpX>c|t?`
z_MDvc?LjIVfQ~9OX_Ih=$tt`-3Bv8e7|pFK`VaoYy&a#Fwi!}MOgbC0u9^8;(+sQ9
z!W}roWJKy1p(w}t@R1!db_>ah%W6i)oG6~MnM9|oa>~^76TGRyF_GL{ZW{0HP#`SB
zu+<H^lKrBlT_5s?sNYqkEX9U$^KYmmCDALH8CuW{TSWI+4W^F}wcBxW>p^De@pViD
zwgn!sWhSLMEi=4s6SG-|+#wg6d<pPQIuy+aIgph(?NSKi5Vkr3{yq537>5(KWQEYz
zz^^${E=D`JZ(BT+*DJh($r7_Eb9j(7wX?}!0|d_FTmp|7ec2_iUbeu~=`iyP0j*0R
zSc14~RqDjj)<UL=HIcOxQw3~XXKW|9)C5t`Sk5^me$gQ_VER=EWg)IsM_sT~rL0dZ
zG8Hb0b=+|3%NEPx3ZiB00Y%FBb299oXH>JOoHtQd@nUrwEJt(d8Uw7}=#eoI@C^1i
z320m#ITu0I@wBRjntfIXr)Y~WOG@E7Wn1fR*Qc6jW(~t*1IAX{u`TK(jeAlRC(8Yf
zjy85GYe8U+Eo+^l+S#UIMuV#2Inx?81;+s5nJo-Cl0!pbM^@R3{l7+3OVt>5#FGJ1
zkoPzZ8RYwx_=#Dcq9;;QRxC74bu<o<h@L%(4{!+&`x(>s*UQu-p53UlKTr*L`ln;2
z8r2M4XWLDuL(y}t9z%fZ55b~O#WmsSn3^ZE#bTrswsWp?nmW>0n4M5Vj$R6Q3!3KX
zYFX3vJ2-l-<owzLfw-Krv<&1t$#t-Nz8c>Na3PT0#p({^A&RE3!R^ikl~mBLMwM50
z>8XaQ(GMeK%&U_DEjMHlO|l${y*;-ss4up&h;cr!Xqr*@IYDh&?kUO-C@MC2&v4p@
zW5rWidyA#CV2&gdb5vi{uA<elnnUj>@7}AfkJ(!Dkee&1A$@(SJz*)qcFnu{;E!=q
zU}M06AvvD%A{n-vPD|-_>SWIeJN0u$n9EX!xzpIDI?PtHMi?%#b#fi^w@W(HHM3c@
zS$hDFlZ|$oLwQNd=4>>#H>12scO2J;MJeescFvCj4{<j3cGkSpq$f;NwL-dnzoJS9
zzxr>~y?&{K%IIT<)l)TbjQSnSO9sQjpne)NNXiCo2hyJJRbQQ9RRiL=Gqlcy5=_U>
zvZ}IRS$J?Xq{|E+j3#>c#kTmbgHdES8(!qon5woWQOVpjiuLSQu}J>9a!<%dEKE#7
z%}&UYG1WNM#E_GdoxH3|9P`nS?n(GS8KY!sFar*IGS-?D8q&puw(C+TWp1O8vNhph
zAZ}^U;43l}mO>jOU7ZSoV=ZO<@HeDV=o|_;2F?n53RlA1PkrHDoI(oLu+?F%$LU>X
z`Y?x8=1L8`9u~J&K-oiR)}nH!#R(h4mIU%lP}b&?QkFTg_~WAIcU=%Cs3PgP-$t;6
z??Q^kLiZvvn8dG<fQyQ=IOGdfwUDf7dPw)b_Idaa1T-f1_&gue`Y1k+Pw-RxMAeok
zbxtIEin`&ayXq=hg7Z1e2*?k!;EqB3N&|yDh~Nyp=cSGVZs=rVR$*CXCTlwPx@LJQ
z>}ZqoTDF<{a;G%Tv!fC2S0^3G&EBVEeNuxGQk9VDD=yT(vAT|C$qpjf9^rETWX>5T
ziB+r2l3XdQ5>Aa-3RstnS)3DYCoCCF)A{{!9#24G9U4dACOIK1V>^1#k9~}pk~!ss
z!oChjvrgqK?)b2|xmwmYZkn8#EW2oW4uUWZ|4d4FG%Ty}PllB2aPG6g4N}&MkvL{y
zQAzL;_Ms57lu&+>hh#OoNO@LCSPHY9dD<b9T_G~aaExfmE=-#SIV(R>)sjBRb2E;P
z_6<5UeH>xnyy?WWJscY)LLr0*2I4lQh;8=-#VmIujD~dczqWRe7%a_{Y#6LkQVArm
z(PNw6$&%JG!*m0>sXRgq#~LOU3y}jj*0T5mvvB&A0-CBPaF&R<AG1h@X`4GHvDOv*
zUPqcz-H@f3ii7y8IIX!{!^OnSVeIt24vxST;W1`m3(h+Aso%ec*&*2q5-Q_*vmy{=
zQeBKXnDIVW+C%Vr^S;D_8Q-8%{I3%<t}r@}9ahACID13py-Xj~-LS6cl8PI|FH`3_
zCaIa@Iurq}S~tvDhpCxn<X$Zoz+}alt2u?cKfW#X)XTV<5GI49A;KUG!7BdRNE+l2
z-QWaeDXY*fu43AXpCcfZRRoCmR&AF|HQR&uwtW(R6jy@P>)1H!LY9dqu42CsKSFG)
zN;m)S-^;G261HeL5jL95vbJ~%T_F{Mk7rD>vn@uMb~?k@X|jrBVFj9)NQj~(t<DI8
zHXmg;73a;Y+B(4@_)$F9X?FcNKR4@?7Ve*NRNQu*x#}3Oj;l`2Q@*jPQqI-lvy^ML
zuF)WGVV|6GivDuowc!qs+o(i~K5_ypTkerDodU8A!e5;nHP_q13?xg+6z3mCJquA^
z9jMLgDND`M3gS~zrP+06DC}3aY1wtsJd6VHxLrR^{(B|ZJ&3=!lr>}86wBVvp?*>{
zKE*I3{8QglI<&w<@>n45Wt<*oR(qZ#o8Klc1=zWXj8%Bo;ru(^0{5yZH8)GQqX73F
zqpS1m7-^Us?D<Z>DD_+_)80VOMOu8DolF+L)3^hQdeiBeq=}PsSE|2}K0Vi{yX@jf
z?kh3tn2|kY4mh)^c3vzy+UVDV-Y0Xb{JJw|4vn(W^QKi+U*t{Ca`n_CTD$zYHq47H
z*O@XGT+)i$tKJ+A&wlRF;e2R9Lonjx{#QO0j&uKmlV#@t{)gJF;L?;uHquuYG<z%%
zhlT0{4OSX+kqogqyN2^!u?f`8x_aptD~3-8au*wqlfwaC8SH1TmIKGhHLH@ei$h5-
zMvjt(75bUs3!h0H3xJpaYK4khvK!2!pMeY(=Y0vi6<_t`R81LEV`JbfsiWIXI6mhR
zvB|M!FE_19VC;I+*ws}w);t!>O;(Hgy4dK~onV!YYdpB>l(0!Q@JVe&EuL1lO^#0I
ziX~SYJ+GM;v=(}I@vrt+ebfeQJ3(xgpCAcvz*#R%gcrnD@rO=mhu)+QRrWYVgAFZw
zk0#t})*Le`+EJ^==$f4D#WkmBPbskWmE~n<K=4urnPAJ%!mF6gYEQ}7iUvL`?K)QC
zv0Twa;h<PHTYmW~!nbQqjAy4E_bOcfO!INKSf=9j_$ppn`&xT%E6D2jd~GAol?^>u
zrY1f=JXe3aDK2%fLEgP!2Ln(97=hHQUu2D}oyAM{<-Y_FmTk74szBv<lWDn1Mg4x`
zYh?d-weXKBo-tkDjT3Q>$z%1OyPF~L>2Q9Pls=c=PfpnR6iFD{J#e&J&T9*#j=x!9
zQQg-*rfXB34_+yjM>p1cI_I~v;A?#Jyc##lT)&`fEj@T^a&lD3O`l}aakwX(m>fO(
z>Eia{3#<1z=Q%e%S3c_T%~tRn-|*tZPX5Kx)X8JKuKescZ$VQuXPRGqbi>t(jPkrM
zG02N=k`lp!!I(eAX4%>Mj%nyfscGL&4v-D#Fp*$8QGF`w!RcqalZei{<QMsmsLUQF
zyBPvgq%#sKdQ<6^>&`7gbW_C*zrlSiuC46;yIAZvFY{n{nvV*b-kp4uTU=?;eJy^N
zd`{gjL1p2pS9#fM@q0>eea`d-IZB;UKOZ$k&AjDIJz9ivWs18kw>5a?+$_G`kwFch
z{^&w4!oYZm<VX0s)RQ~$dkz5^8-N)oEiEC(;w3?lsj&TWcTY88oC^#QTXGY#nzcd<
zW9O2+8#$TN#SDOnQ~HDY0x_ilQZf*e_@zYY(_Grac?)7izk|}N>4PE5bp5Cj`Uaoc
z{#>)tGQ&sDK5b4Vcl#K%k7>ua6g*j#v_vU-LgNYfxqHp0H05UL=)=UmiDa9g;Vs2a
zdcDN@WVssr9Pi{x@K&Xgke{Mv?IJS4HwiA7)_6UXhRTFum{e~kZuq_q8Rr8=cK;bY
zxSfRj0|X03vv7f-@5KHPq=^?X)WAf`{6*~$=jHagvVOIAujGy@$8+a6(#NuwF!b_L
z@IGp?BS5@HmHet#hF&*OO5+Mg%Vg?g$mR>qQwyKi7?AM1s)()f?-I=OmCD^pg{oE`
zK{3J^Ro+N48Q)R0PkW6GYr$%T2Ayf#<CJG(Ua?aB#WL9i?@P>bP>~sZQL|+5=WQqG
z1B&h^R6i;vMF@`#;}6SFQ+W_WtOmcqrRS#k)Tc+CGBHQXo{E8<+8MmY%gC|LVZH~a
zz00L~^*CefoVJf+JhaPa^<yz~;cYqf?;a*uSau-#BH9Wm)$ifmRO;mew0z%FY=iWA
zwZx=;@K;d-tfX&Fu-8aJ?zXy#G-@ghnA~cYoIv-^hq<_FDs9w`62aTRR)&wi2}?Qy
zUP&R}D2zalfzdHm&tE_+;tz(Esgt8HnjCZ7gyA2Rr})%;!69C?r*M#!mVy>se{B^6
z*z(>MeLC5q|DC3}SC9S1#sH;3%P1jGNyuGilk`Q#%lG9G0=!O2)v5ZUjG}GZn3ug3
zU}99QxSTifAOi|b=$OMe<ejb(!Q;bi)+c2c=dz&1c5%rLDdrT{r|PG;##{_FV$EkI
zT+V~|)p*t|dYNJDrj~+TF@Blfa2!+7E|-(Ru#X0(wc}#ZU6zBti<NiyFYoEvfbLE*
zQVu?D4QI<#%}=uC4R2Ih<=~su4Ru_8qf&*~NTKr@hl+w<4aoUaB_vmxWk6k;mc$Fg
za?ny9hAF2kSmVWEe35vwaSf(n+B|FVs|95qm$zMW6D4(uVzRCVN;{k)Hw+&>hF;z<
z@7Y1b!z{7kcQlOA!T0Y;`a*9~pLEnBs+J!N#3Tze#1nBau$GC!j`7e=uRCcXU1Qrw
zhvL?0B;TasPq?lQ1*Wx%mOM$#79aivSqa?q&{se>chnT0`pu$mv#lc+Nh-+gLyqsN
z^YxQ%b{%bb6OsJ15p-%7#;!R-2ub@rI?tyND!CzBF+b(qi%r4v^%%?oV$WB#k})sN
zKP1z0t~kjaB72-;6}v+-*|mi-wY9u#dnY-ynbTM@8YteS;2M#=VCWheH*_dAQ>`f#
z*(^rRY~VQSe8t*laaU85+|P3uJ{LKphbO7>f|Ev0i<T*TGnH^W;{26V@sg}<hUvM#
z{6xd@@7%F)h#s|`?EDW#bVOTzVAgspcZ?l0XRV>!v9EmDJk!vylDeDM_YXPW{I9>?
zio^Aro%qkSg}dXw`&&lKHS6wp=WpR7j$3yN_(Alp#tz2rSUVnAq5n{@e=G0+-u>^>
zc=xgV=gsrOc>620Px*HH?8O;%<Jq6YW-a`e{UrAH;!4EF;Pci#=7Vc#u3bz1m#*d8
zhhM&U-V_(}c@J;*{_$gGt?TYBaS^jt+7%zy`&;5-&|zooVvc@zF*CTcFTIS5Xjpl0
z_AhH6Vj{Q@cVzEg`;3;7@vR?9V%rt*C{jTL<F#*e00W5TW$|O6P69H<4>X*Fc$qF<
zgJ8M_)`{;ZGJRWoga3&f9mgf!(0KU0wYS%P{)=C-{@Ul%e)PfHe(`_*)9-7UgLHGT
zHG49ibQTPi5l3Zt;#rCc+jC8=bOcJO=R{6Y?bu+tXZu7!akK(aoTNHv_k>SsPEQvg
z(a@07hpeBmFr*Eu?nEFv9gfNu>PfXV3V~tqTuY3moZO<;AJgE_2c%;rhHy&F&8S)C
z174Lor}=Y%Ren)xP{sneaKMaA2inIpm3m>Gaf_;XjhU{0Qah!Mo;3gD_K*H^_T;Wt
zw+D!h6(TKIKu-it0^~6-?^!S<V1g+&LV_A)7CJ?sV_uyMe3xj$c`cN-LcVDM$jN&;
zd;C51+C#181z+x(qu5RkND@<l_k`M2%nmIkX+giK?g79j)vVqc6q8{!yB!qCE@P?-
zcoFNyHE%x95F&C&x8zX0S+7`<t#%MaYLKC`Ol9R%$YP2UoaB<L=kM7XXn<DR2Vli<
z0In@$EyV+1<pZ7ooYVnCug6WFdDUgpt^@o^pVXzgRX4mqk--*y$OA|j+lJjx4s07?
zHeR8&8V+u*#W#<fDeM%{OD1}Epey8?50DdqhZ#CFY8LYM69MF$3#~;W7kx?Js1N?b
za_6))rIF+uZ%6->9QsXZirPSjdywjdEefb{*qS#?$3`xXJj>J>@Qsk;=wSz`-;k?g
zKx$Qkpi;n1#ZX3QNcd8KPGiW@p)y6rjou!neu}r$o9)=MKK~!rk<N<Ype~PXr6+6&
zbT#YK7M8+Q6Z>k|2Ut$c4)r)uZpjjIc~y4+xP_Ym{A?3bAUov1jUE`&BBZ6Euo5~2
zvIj6jFD+P#ET{t@SZ4yWiD~#?<n92b*5fFv2O{ktTa;rV%~X}ofBzF|kK8rv<mxvp
zs5u{U@+C{D3!o2~%NizA4#@$73k^Fx;opYMX)aPP_n4!+d0K54cA^ye<<3|6=ysga
z{-9kkqs9d-opqa#B0*Jas#UYW9O5~s5_45kLzMs;dDh}<$2DDZ(C<g%zF0BsJZOOM
zS#Od#9=@p6JDA8>NJ7A#ac5MvEf!UN_J8@4vRyavXkCh;#RJ4cj-wS1QMr;w-y3hi
zE20L`bP`iB*y1A(&{G;4$LP+4lcHaY)xa|gjymAX2&swM1++99PUo`@sl=GHXNkp}
z;xtydbKh!?U1MP<Ts##Eg<+Edd>ShmtzRa!t$d8Jc~h;cYFLxgs@AaT%mnp4EE~4U
z;o?ldLzaizS2yyOljf)X^S!A3INN9)Wx5Z*h$B_7*+B4vu7wy0p!;=NkOH8S*pvmZ
z!pdUOIcgTBAZmI_b$}<>CJQ%(_d!V~1+g#cNd0x)@k#17lL=e}L+GLz2Y`gBKm+$T
zC{EU?Hy2}6=PGx!aSh#SKl|qjKHI7zV8qlZT<Sxif@ljNL~9buev+`<eTF6Pu}v(i
zj<VGoPWYxAEG(6oS~QcFIsgr^dE#KT=VYoEOO6dVUve29IJ`U7fi@;!V~UkA1<<8M
z$*vFin|v)kt%YGL|J2_gNg%j^4jEAWhOE!tv*3hI(uyWEqsP3!RHYe2qDkzxj>JIe
zT!;Qya>oX2)Y*E40a`T?LS+3|@^JR;ROU6tw~5F{5BVKQK%HvV&r~yrKWWlD>Xll^
zfAic5t|#kD%@3+Qq-^zZ%165<0O^@dYb@2FAUv&`3vk9+WCzu<CR?DP04r&3=WubG
zx5vo^Odz4*vZYP6+EW2{icZn%_NZJ%L3LgWjyg(JQ!o3dH{;G%rx>0p>%i~u6=T#6
zg&WNPuAF9NwN7!dUr5DKOZk5vl3ajF4nd_R0O(P!qq5^|$Ho-$0lDvyEylAx=$|JU
zU=FuK!A#BiRB0Oy#tt6#NmgEVoIREl3YaH37AJr`eY6BLzQZ)HaoI%|Ma-ot_QyR;
z!rL&X5Ef}uVc^U$TWVbQAJU<4$pT!FMdP8+X+}HwMb;ztYYD~OlkAj7nd7r^WP(>I
zk7q~+;}z_Nw7M;jg_tsA;HE<k0d|#5GigO{F#=_y6IeeA(rQtrLW@(;(oS{<#cy_L
z$YGeAAwfrX+)<xr`dmb)PS!u>=r{xFxOw|8qFFg>1Zb6<pm}`9Piu6K<!aqL!~u~Z
zJFceo(3IOTj0sIGhQQg$DnX(wNYw%kkD|p*n}uCP>%7NyfP0oTnk{KThDwuG!~vlu
z-1We99Rt@QN$#S0LPL~^vWt6yd(EtDWo0)s<4oaL!j9zJ4O9`O$R`3QCaA|ydB`et
z8-T&H6BO7WQKdS9#e-3%I4yE4thktFuGC>RBTCh@fbq$kc^$y>bWi(KAjC{rGeafK
zMlFu%)KnHj_u;y*y0A>~4RHISjKBw<mqlYWUZ?z|dp){tk{}KPA{7*@y(&Xt#KCm8
zISTNSH5Dj^GnQSD8+Oowxxi>rIl%~t8#94z_?{%H6L!I1e1Xk-=CG$!`TS(o&$9}j
z!o7z8d*XY1+$5eBlY%@fr|>7NwNE-y)<9>o|78Opdx4$4ssVOaou#l3u*}JnWlNqf
zBx8jkt#j<0FDLeVS#$O{lOcuSCKhok4na-tnk{E1_&gq2)?Aou4=FF2VIS%*G>ba?
zJk9bRE@vGBsJKc)_uBI*1bc`9Vf4uTN7WE#JBafl_2sZ-m059>ZRc^a!JYS1PL?$8
zd_|jdJF64Dn(cNw^O#%XlqVDloX9}bBu{DpQX4i<MoCeg3a51MyY#%K17gPUX*l;_
zeMoE@;MasdC}-CLWColZDx+|iRUA&4t9th<Qw|Cmrs;li)EN#Q|FiWr$Qcx~8n2zA
zs7f(;58_grN?9a(9E55M5H*(?@VF!_Q#YhI))YFTIwseP3Woe)T+OVe3V#VEA)mrC
zz-FL^@Lx1*!?C4Es9T`MH_W9tU~SzO0>fVVZ1R)O$=-I_<E)R%@rMGtW6$^V0jC`3
z8Cj|D-oVmaW0e<Q8eCnt%Lj9hJH>0(gx8PG{u{|;XT|IMFB3PaU!lc0?-mbK$DHHz
zJNzrvrPb<bYh3GQXt*@gv%9*I%KgX+OeUS)o^hb0yJu1@-x%(^U5WLZmttfbU~k__
z^)IN+TOOL+N(*z^7kO}wpVQ9L*R(PA^c>Z5FRz?W#i|LDzswhC&R3k^&rPHzU9W77
zr^cMG(aC;oO!J1FaT;tbGfxh(X>+E1w5h4sJnepW&b+4G{x7>wcp#nmyd@Lw(B!P9
zJ;O${9TV=UKFvL9jh@sxSM!vk8R*2)My4)WuG-1Zp{Ldj{wCe=R_DY-wI6E80S<WU
z9KFUYIG59)$;#JMZvspq_QDOmZfddkC*)|?MsqK?9%uG-ww8~M2DmXz$3&?)e2EsH
z)ed`$v8{C1wp7BmGKTP3>(?ZABOePCHS;Cp`M8A94EM@(beiI0<K;l8>^?A8cEaCK
ze}|3*&u`V-7CFdkcr5bKU%+q$dOJXY%dXHE)A0473KC50(i^?+iLY#c8#lnIMy9)q
z)llCLz+VCQ&aq#5Ba+EthG@qZ=Db?sh5v0F7s(s4<h1+2o7Vu^V|)~EokX77Fj-v`
zZ!ASy{>GW(2Ag(9ah*9IbXUy+0j@#0|M;Z_>dGzCPL9v0L9>h`69~=yxBu)1*=wvs
z#_Fwv;p@|qKvw=I+TH)i^mbQ3MaQQPRhG$|dfy6vzfu9N8|SUJCMJNI<c4UMaYPgJ
zQhJu4r_DbQ5?udp`To`W{$7i9m8!vu!7)e<Hd|M{vy}(ipZ7|Y&?+nMZQsMv`H@D$
zs4q_rB+E~<{}zAY-TI5MT)D766JFFe|89PcmipUYhrM2Zsb%Kbd>NM)yyoGz<dwQr
zz+b|Bu~;5&JQ*9~iPme=*F1C5&QEgs)bnMMEN_4AC9aI=s%QF-7DIp6^>)^mxZ(JK
zgr%z4I}il{9|U9Yq}N*s-UrmWk7;?d^ujKg<r}uK-YN}l=UpX>c|*X0IUveE!hN#K
zt)J0GN0|HuFC`!RdOb_Z_@HWn&G5?`ink{k6KB&p@U;yOhRa|kYeW16<DR2je-NnN
zG5X`P>T%}~E$`J~09Tbm)7~2}$3cCsOm{!-;JKdd0<y=;gL#EN%=;-IwS@d&_(vR)
z=+S#mn8jjQ|JlgBS^_YW7e*Pt-W6QHl?O}peXQ4`z?i1$_js3Efx%F<Yng9QdruZh
z<fwDJI?Xy_?DE;qY2(;lRXkR2_jk1IypO3@z0%Ty>++`TR`*9|ikDkU@YebUlina_
z33?%wQOK|7XAHncW^kQ7s^hLfqkirmI0x{oO^FAR2n^%mKQ{*5@7Y0tye2Th$Rfwk
zD`%KZwTl-|H9^+;)Fk4Bm0MHwqcT&0@#T4m09B-y%W#l;g@URnjWf*|Tk2uHqJfrW
zwhf>N9^4#D+Gd5j6;cD}O7(9LUb>I5F8L<sE}q0uCSd>(Nrl-B=kK1MsJ7_-u2Onq
z%qv%4#B;bjlW}kZoh!Vw+JdJsM)sp62_Hj*Hw~CB=u61CvZpmbl7AVxWsH)XS8AB>
zSq{WbQcsQY8I&idCJWR0LFUsa9xtYo3}korbbTR1cbDqjWa)EtsC|HcdYoacOx4HB
zBzTV9B@AOVx=I<wWuRJKqR!~u3Jb2cP)xwEeIM(myfb(UR8-)VcPmT%L{s}QKAj_^
zM9gly>?}Fz4p@f>z-f;SB+rtKF;IBHx(t_DA{thLyYK`^5M_a5v}NYg&)uq0J6o<&
zM@q<}WuCpoInRboQFxdJ4v5+1KBdi3dFuW#K7~vc%}ZVV^}qNvAoj4eoC0<YUeztn
zOUT7@Yz_!XH|^z`nm7Wad%HksfhY!jop>=OQN>1p99%z++t?7i#jq=$y$`Ux_@-R%
z<mUiA2N&=rL^xFMW0z6ac>UG?6TxQ}1_||^dX6opQ0`C2SStbnclR@p?pY}sTtEdx
za&78CGDw&+MO2g@%3UfOtt}HRuc2uSmdTWZiq1?spr(6oc4M*I!El&~hqJ3g#z1ho
z4ezK2>Y5d6V|2wU6Rd(&%4KhwAx;=A->3C*=_X?dAkGTb1v)h?-N5xr_Dv6))LCMx
zeU;GdMzO{p#yz*(j>V4hMEOwg5HAlu2uT1pTl|ZoFNA{@aP65%W@k+UtkIBJBB<Ts
z8cAZAJ7oaM_5D>8A`mws)mMWGCI`UjpSAr4g1G7WTD?%Q)r+fus_U6tH|GM$9+j_>
zR{16)cE`)ikaNxk!0l7@9hpGFPiWA0;u6Xso#py@X1`J8vhIaV8F+ejC-3F-c<xPJ
zwWjLX3oVcE7xi!brbb)*ELqmGF>ZI1v9yA|tb@g<Ue!t&X^P~_y!kBFBnI1nX0w8r
za$$0cOli_*f9ePNkZ+Y)hpe)I2~uo|?vo`eXz@vMV$!BrACl@$8Mhp&uY!dY;{Ym7
z*i-dY2}u#y3^Qt->HZ&8A23@EN3X_GxWzI>4S;R7gSulB{Qo~^?*rY&b>I2UKqF`5
zs2gBB=8jQ51v45kmk=#WwBoW_H^B^s)CCBM5~Fzeylz6$v`edLY$@Ixy|kx0cW^;n
zfJ2dD7%%GQZAlu|gSCodIcg5mx@&@hY*<zz%XPczdwCm4aZ<%6yOC8lPs!$O-*+fG
zf4b?OJr9;a5Cn%ackbWM@B91Sg4&%CHe&xQjAHjGx?o~{%~+>B0__khtlz<MYD&Ho
zSn{=>R))(FT~6`6GzwrM28kFb#%6>}wVO<Ms=1PBH6`z~da1F5!YlM}H@rZNn$AUg
zZF{DMfb3E6yEK&`h<gG=8;E$imvF0G0|n4D1db(5EZAIBI&Kl0$1%IDgBwjX^Fc%4
z&H#S%gz6s^!7yVJ>_M<*=_YAjuT61ZhT&pE1o?mw`pzHTJM8@DRZtAp9C70Rjx~et
zey{H)CjLb-`}cnZEDzY6{q;@144Z#}5`S*{D&PIE2V}i^m;*Yf^Ovm2ww<fE8K4e`
z_sk1jIM8$155s}$vh$N8*+20j%3FJM2N?KHpyHn#>;K;)RQ!{P{ClW)|NdV*Au!^$
z8|i<Nen(eFr+aTak^S}UAEVQ-y#R5>i+wkMoG-IChkhJU^wN9$`)3s0&9CBbpyyTk
zeJr29{=M_jq<Zxc_oB%?bR&3*mNXJjgbxLn#P9+tX}*m0>mF)Jg>D;Q5E9YolPOt(
zj6FgOl1tsB&ENlzqr$8n5I^DV*YjVAKC=4Ay!SQ$&&@})V#8zgco4DN{O<i{{DEKb
z`17K_j!)@r9wrnyRQbJh&k8Hsjy)p6@AAe2ynNIszr{^AtZmxL-3_ok;F{Mc>(oA^
zt8MhHW}<MBi*CK?lx*<Vai`fVpSH6PJFmV&^waKG;5EHskcF@&(=y8DBIy~GdN$Cq
zONB)kQ>t-=7rUu{2Vo}TV=QG}4xpEhsN`WYpHNFRHcE0EHT8cXkG6jZ;~ONg2+JxQ
zcp0e1VMVnK%>znCE=^)(lUtWnxd+POv0k-JubH8`>}@i<ma(xRihHqJpO)i^@NPS<
z<O0i88FW&*C{~bn??0_u9A@eOk2Ygyq%by90!d0LMO7jU;Q|dt2_Og)u00wA?EI_i
zZG$(kL6EM5Q28*s*ATb@dD7{l>l?Vp)q=AXED1|k!t+-ZO>8kzi8<PaK4ccVa~Dwp
zhBw?wHf_>O?*)1Y2PtdQp;X27_*u2W7B-DayeJb33elA6%LF?aK&U&yQnqQDjdrMU
zAoP3Q1tGO$fL=9qeeA)l+gUTmyD5(karA$NbFP8azT)|T%&?o%2>qClswG7$Ki)<{
z5Wj}rR=77zK|bElzyE}hQM}}+V;Eccl<j!g?>MvD&plyy*%dpxLKp$Y(AY39cFHO8
zjCTJDxL^_uP1Qz?qKcJiHzYH&*i-YUv9($?hBU#U=E!u7@p0BhHhmGa%#x-bQ6*!!
zT`K8HwqYY_QXMX_z8>Q=5}4+6>KIz8srkqBEL@5`57D_UGiF&DE4wO(+=U)8h6Aa1
z8P}6u3-%On2+O=6#7`juEuMvnhcLW~8!;_q@`OkT^o${7a2%>73sncedn*F`^Dc5g
zZq1wKqPh9=(90PS0PwaOBs6D@W&Owlyx7DRv2#PY1>NDCO*&p>!M)_>i2FGGykYMb
z8EaO*XNc}BTSv(0mfmO>tWaxfgJ1?bYVN9b=wn{?ihJ2vDX`{Yx4ARuaneBkq+B)l
zFb~3ifwSLjbQfRgVb2p5Fmquff0<G7(JC?cd?(HlU3JxXo|;c%2j_d#OkFS5w)07i
zj{CPJYbLpN{|;$mtjSI{Pyvm0N=3q>6oT(@h6>5|@^XVtI#Zk_#ez-p3k%(aCGuBP
z=@{Z2#wi=5MQcci#Xja;<OvUgqfFhL)U$Fo5*)(Wp?FW%jKRul*h(0jG0G1HM)zR3
zNwjq7Bw1+JI)u4avosBNAhm*<ZpwKRC5BK9@)@A@fmN*$cFIX>ZFvPyiha8GgEn$)
z5aEIUM}}-lP}-tU6SkApp3bi<*w!Gis^Gp1X){{1A0f+}H6TV)Ifhw(4f+OHEtVB-
z4TC178YIb?tWBbiQv3iJgUQ%n$^rL_y5E#ci^#ty$^gyM7NBwL3M9(1TU5Ti>jUVO
zAqED~!^iNS>i7&i--`=RnMeJ*z!l;dA89y_1PT{#>RMsDUP7nq-^U})>|2i7t4fgW
zqO-Lmse>%wQWtV4EOh2R1ksS23saszrGqvQM@)d@&1OiTSop+OHpr=%#16X+X%ELB
zAxUjQ!2%C)?5$O1;0<IMWw-<M8};d<49_vIO$~9r-5ekHWma6@L3_q|MDrr3N1|b8
z8PC9cYjIH+gM3^$uCHd!bbkEC`lRxj!yF&Bm%ag1r5i-Zp)=-i;6`D1KILz4Y}mm`
z?2<)2H6H|?nt?~rCV6-zBS1F@(77Mja>_E-+*7CXZpg+13iQ;X1la_a5ybYv`%$5J
zOOixteL#cfDb$w`-||SkSy?>nLiNy{_>%*_h5-%q9l*Mf=z$0k_;#y~D4W!wEMp`j
zId_~d<m7@Exace5hE^TiL;8$v&GOK!QEPE8sVDJym^->b9I-nqFc-`sg6eU#B2yGV
zFdU|^wJ{@%wpxCfsljZ3TMjPCj@6SZM@Vq(-=4QKiZhf`atg%$ySaNm;S4q&*Mz6}
zw1)8ke1h69S1U>v-EJ4ic*|FPZpBiunLLUbXJK6OoPY<ICif9b0r+JyU<ks2v6Lb{
zYq%P!{X9sigwzUw90mn-*OfFr&kXdzoU%AkP(_A=Zx4LHM$7`yUjyO4xB`1JmCf+L
zoxmhgbNH|Wbs=!3A49MdHFmUUYH{oiG-gVme3Bodn^ZsMvi;Q_H&Z2T>L7v^;ZcZC
z6=~FPk^f?w80Zloh){jXfn+s9_))_diom@enDTEwiKwtmF)zWm%(Tq<cy*3S&T_Q#
z87@@H=IYKS;B+}-o470S;PzPNR$xuC35UFglEAht4+VG&l-;<dkV4wlC0m1Ka*PF_
z(=|}(6C4^^;BY~!TBs(8;{OegSgsRx-XfB%stAetQp1bAPUqTLPIjVMl+O`^eHHNt
z)EOyDsDd+yIhaM^)?yLmVM^>7E6@)!TTZiBbagRgeT1=D+$@X7M7JR2@c_Y7Y2FAR
zUTsr-=(oOXFpy~6LcvpjE-sGl$KvY1?hn!e+LM&I>dA58L}_Kwl%j}9e!NAb6jt4n
zIx!eHofazi)n%xV(FmD^-g%sOCWdaufKph&5c4EolZ?%qXr6#Jh*AqKWVBOPKqVfk
zg5oRY`ZNx^7$OvGjwb$L8?J8Sf-~dA30q6EHOFO+$3+$d7r8DTzYpOLfi}?!(YgzA
zlZH%JAkdHDl+~^JjFpO6?mS(l3_aoEgg~|%0v$1HXp0eY#YY81AW)r0SA(1j#O9bw
z8y;jy1>`!$%0YtO_(>yPb2N7zokiv?jzzhOi27DNRr(|F6qT0QRY&zilE_X{v?6>h
zRD{G3R2mGzSX}SH<#5loIuyE<6cCS}5faDdm#A2*;v%W}3OAM2a3I54ZEK5S_&|9}
z3^{kQ;ZR>81_T)XL9@SG-+<i&CLZ^y-sw4yJH=-jufF9x<xM+t`c4*(JK5YRZ%J3r
z-Owoum1z%KdwAKmohS9@!|Qr_qILG1c5k)t;WvYX*s1JfU1N*++g{#rpZby7RQDFI
zC;sk`RZd)GSM1;;bJhkjFp(Iau=<va+MPq%^&tOsx(Ma_X)@XQ<YNCfjs4;|cehde
zVfkxUPZ}>$QZLa-y>d!4M7hq3b&yTgRd)jR*WwHfPYQW*Xp-+Xj<jpLjecjim!vl>
zvZqeAMkby!I>v*6M&A19?vFUnZli9Id*kfYQ~Hb5=9{k#4Gm_^XJM4ccZpYT2rpTO
zKA^`qw-jy@2=)Hf+#9>Z`Oe4dO@5fZMkg1<5pv%t!?G`<>3v?mXl=)!PVRKsW<9l_
z7vHfAYZo0Hw(r?N@=v?OZ4_(f;CQ~rn55+^{9m-nePof8pYAz+vh}pP#Ym4Fo-|kT
ztgBPWpKO`bAYF+i(D73cA+8Jm9aQW|vWflR4D$0Jucc?&(|6Pj_l_MTEtq-z%hoWg
zxqqf6)>jGgDo7qe^e=+TSpkm7K>;=xY(B9eJS`Rz8~9GK3^mcAi5Q>aJF)91a$+|0
zFgtqD`Ov~Mi*|a1F&9q@Sb%9={7SG5cxyCZfX@#W*-hMBf&9sU%nDffM5KKx*J==n
z-K5S~exC%y9OUI^e?drG|GAv_eKOwmqNv%ET5^d+YdpZ`UpIevSTXvRT!678B(wJ`
zMsMwt+HdoLzPE0FX4{#owC;7i6Paad3^b}>pPXaOX7WJzt=5ULqN(nG91`=^7rYyy
z{m9E-_?O~K<9&T>Z#eL9_h@N<b7!=n#eZ|{p6rm=-Q4jV_-O1u)#GB@>&@15@R#(m
zSKD|vm@+E$!SrnlM>aT9gzbNBv^2_(FIhh_z)H^^v$D^6TkIXzjq2G5kuO8f3zn8r
z0K8xbP!`7_%iD$zcD-w8D?w*1F<Ho+NW3EQO`iFwpy^wld_-Wkz;azA?z*}Lips+*
zx6PxOeL!s2njR?ZUg2Q#og-nkzV|RYU#NvihuF$gSnOI%i2f#id0LQg5zzSSpzsS;
zsb|cEyI@z%E+zR3*8h?CTl>Ldx9t&y+TE`u=B@Z!_9^RnkFk^Wdyz#0OgZXi&-__e
zI@{qH^*VvA2dyt!<ppnlcu-VZQbnbu8*u!sJFg2;L)|IX3!s}P1*tnFf_OCBMt4#W
zLGPNbyZd8WJ9&W|1m?YV*A0Kf+l*q_pcf!MHlXHyEIe`Ueg(qr^$`e$hS=^}NVski
zej0~4*%3T@4u(ww;%Zmbf&t6pO=UXx1aL3k+v+-{wHbWTveEAZu#WV04BBS8X7$6~
z!Fr+Ri@KAx2G6Zv%L28e9zTvDp^_dH^UtLh6UCafqqxunM@x2c=&tHbFu#b<CP)N`
zSD9vn|4w2I#6Ac%<d`Dev2e7)0Zhy4V~?)U`Z3hCD<x<+BCF(no_{7$T56uy2WQ4T
zqL;5{WsuMEiM~kbT<_z(&6Ul492ju_Exk>T9%jzK=rMPL;q7##JH3Z%35o9b#MOst
z9haQFW2kM#%TB{1q;$~>19=7a;`m-ZUnhJXH$omwu7Ni8D3Ei#jB`c7aRe)zdcl|%
z`4bqdq6S^;f<Txn{IJ*`s}LLXF^XYa`|77Mwdn7AUS4VR);yGdYY5lSY$9=r8+#(f
z?gasPa^Xme?6{jt{7CXHs6Zy(A`0tOXfolwVC}>9N_)tr|6uW_6MpS(Z@!OseJ@yx
zT7mHx1I|5|mh%Xe&7T;Dx8?B)O0BQ{y&W<gjfiu;O9|$^o8??0A_~<+Q4#3z>*rjM
zO9;CK1=*IVyT_YqflpT}_9-$eq<{Fo*El;p>=LajXb^D}JR$}lvs%-E<k!X>J3!Us
z2%QXZf9uV8tL+6>O}`+BzG$6+h<0zwB_%^iy9fJbtsQczcJ~=I580o+n8=!n)yq|a
zfdfPI_o8)ERPk$zal%o~1u2CzhUs$sTpr^kAT|pBq9E8`txRyfR6r>WWZC<8t8S+)
zlaB>aY3t{I|3h8dTw0<YSDfBj?=r{Q23HJBs2T$vUw@5KdTmaJ>1?WA*k7|i`|+iF
zz6o{lvUk6Y<_H(v`^1^Y?V4rp>buL0g!#~V!}`i1y>E`4vaB~ehsVym3p9R9%2q03
z;uf9`P|ow8-GQc*u9?NU2ezz4>S|q`_mc8i1%EBiWwd2Z_KHYisUb`_HY5D&f4?^a
zunU%Ac)fh>ut6kgPqS0e`Y|z?ZgwdHPQ7U@i#&Q5R3DOFb5=>m2K1V3^}c1-Iv`o^
zJZ9OCdUG9+xEIvq-gA=GTY&TVPA6)%&5Ft{>9sMdqV88_Txj}_$Cj}!L$Qadi`dW!
z5A*^-h^y_GE>>_RKnHoWsp+Ob2nz|*d3%vn)bms8yhkv%jY4A15Nqn=R-7kP6W>z@
zotwJcK80*H<#ldgj8G+KAK_;Vg*SU+<-OzROs7Ov830~#(ersT#y5-tl-0dgy?UbT
zP#{?@hA=8_hWuC2md{C5bl?rB2r!3pVI`v{EeNlHsih+H*Mb^lG@2gYeyfNNefXs{
zPZ%+5PYe{ye3OAN_q0)ab;$i)3I$^i&p<37q)QEC^_r#{vM3^qWwB#W%>FyMLt_{-
zfr3YvG|alNSa3nC70`AYa&c|OMKD*m!>j=Dk|-+~0cE|BY8t4FGZ2~QN13P~B!);p
zo3K^Hn%5g!MTAR50FfN2nqS$x1`_5|x$7N9Bw_xrchLUFTsgw8`&aSnji2M!he}`m
z#HXhg2R{|*hWFwt<j2qrFaG_|s&4qY6>(hXkhkAee3!0@p)cdbsv3F&jfBisI^F}h
z53S0fx4fr7zHYB7ng2TpGL8hUyb6RPJ@l`ZAfNdaI_8__b5qB>ij{vR&0dv5<7B?{
z>CVNr`ywIp6&IHUI^7?g3~=&IC3F6!k{NpL>;LB4Sa@Jkk4FmAcBBU|n~yMvoFU7@
z6Ip%Q?B=cD1*>LD6xrcHM_?`DM^wthECOb?5nnJEfs7C-h+anjNoiq4umspTrJ!z6
z{0S_wWLGNK3fAJ$W7j*YU+{DjDO)$c^`aHi&mODOc6{RIuS6>lJp9!!@BJux<K~a2
z4}b6x)d|hHE@{|h@y88hR<d$J;ZUUU5P7&mnRd+LtwLgMB|OmD*EMb4SL@i`@d(yj
z(1XRoD{h07=DG?ow$&OAdNlHCF}93Ez|d%YHjJTeM#*{rrRjBx29`Qjb3Dzy8^|D$
zSnaj|j`|>#gI10cN9g$9{JvOVG}B{n{?8{0&$u0SV_$ORaU}I#?|I0VhuQN4vQ$s;
zx;0>fb~|CTEB94tA62$`anD}=J$>xV)7d%uK0C%a7LWUZS9d~i_lTS#`uK{4#j4F+
zg2kVuL4RxcvBi0l;7Vg5(&kxtZGb3pU#zbREt_e=bbxWJBSq0PM_FSAlDa-sd){3z
zjlgQVvE>i;xLU7D9myd)bI8Mj3#sxP%0(!~d6TulV!&QDc*z>HtxXn1CieFGd`-A>
z#LGbh+5ts3Y$gJEJZyL#57i&IDn%TrNU0IbA*;|)(E|}Vz2GJ_NMv0I42yTDDekG=
zNR#qZo-(mOT}G~VM?+7Kx!vCF*p9HBwO{|8doyj=QA{X|Zw0wZVGR~v?{728MJ0TQ
zF#-u1t(adVZ#X}+$`-vC^m1p6dD=2TT<tL<=pJOBFJNt9Vinnj4q4{dlqUgv>yc2+
zuOa2mSh3Hru(%IZZ7a{zj68DJ&mIL8QVl4bajQ(gpk+@o8eiN7?AWab-8u7?-`?U|
z9>(nT4(`NZ=QKpknv+u6>`46H@YfIv@;a$k1+qA7rrf%j0Rx30VG&2)Xv)@BLJ5><
z++rEMiQ8CQw*^uELqV`?M+<&{cjPqI0|UY~2xsdQDl2YDsgk3z;!%MUgT}?O7=p#v
z5LUa!{_u4>@Y>r2_>NlKOQly&7MycNTqO8OV>{`0jPe*OA0;KuWqO=hPqS;YX)?v_
zSGU`3^nn2Jg3}}$xZxY*bk8Qpu=V{c#j0S96y5(Y)QyRDb$O0`OoUe<4Hj1athIF<
zT0mEtWLn`>@q{glL2i&r&EcHQ7(H!Jh#SRiTHBJrt3yT`j2WIvkOg$sP~?+qzyA+@
z(|cqub_>|co$yT>%NP)`QUjX5SJ9q$_$8w}XY77zgI6B+3L-c&l)FGak;`H&=^Et0
zfHljWnmR>}8o`}jZx3ls+R!g68!S}2OMUDG8uK=g=fw)qx_KV@YV32Ob(7Qx-+C2|
z(x{jV2n1O3Na>=|gvlC1MY(PL*@p3l!YBviH>+CmaiT*Mi`I0o>UV2x;<UkDI(94V
zfzCN1I1K3&Oagd?Ob|^?A{s={=#J`OU?8S0<d9sVpbiXS9*d!65%gAI5eQLWtvNqJ
z3^=!07HFa?Wl+Hl3DP*6X&_mA8RP^psIC|)6aT;di?mfkm`9==3bJ{WxS=BhNeR~s
zO7kqIP$6aJu*nphR!|iIX15x)WI3q@9k!5v!Z6a7p=HLUMmurB6{oCh5pXaFRVe^)
zk~yCcCNpJDe0B>$Emh=hXY6e~l18HadQ!^A-~PZbf{ftgh$#|NmLQ^5GuY>}kB)ou
z%<)o9ni(8&kQ5Ise~42EV|qdNkog=#Cin=8b4_)6ApFck!2^&Oh_R!?QPnS*a!Q@)
zkrGm9kb89CO9KHCp^q~y!f#UAMt(pgc5Ue(6vk*2Qv4!qARfae2-3#pfGQ<)k4_tJ
z=mlB4&Wo5`ob$Ge;y5j<#l_?#ow$l5h+K<I5cunx+QPiizpygvwGrsYCaISq>V#Sp
z5GDsKwNaQVh*VLYg;GSAE#T&P+(#7aR<1#zO>qQRYKhB%Gv)@)wa0&Jk8N|rIO5|C
zEn`4D<z!R`b;FmL#8T>TF|O-+DC279hj7in>ET9ev=RAH39(flm-sj|y^IA-(&`?H
zYL48dwxoH-LQD+^uqe+Uoa@IR$!$RVhuA}AJ<n=AJsGu4b;{a1pZ@NQ>od6kmT3e=
zfu0hkFvcm6xL{5o83prla0mHdzzc%k+M;52yXJcVuA-<IjL@xa%C3zVt{>ZItG?``
zUIUQ9noPx)4HP92>KH-jaAZY*t4d;Mfw~hLTj**|#<&!PE`6#d3hPp~4g4)(@FJ*K
zkQk;w5+x}>@L3Doiatu+AgsZD;Z_M_R&HvAUc>eKc9AoF8cRatL<cFxRq;He(gvcL
zsD4xo`4}Uv66#L@Z3d!P3(C%RQL)Ogpkm<`8bPoa7#R^P1QQ}Ah2}O9eEeVC;(DOn
z0L@WVRmv&~4XX3F(wIku517eO;!55!ZKBO0BuU(qSBFB`&BXGPkhG6WmJgZtu&Bfk
zXaHV8)eVeLs6l|*A&F451Sa4qM>kMTAg5^Knh#Z;;i<Xn#n0NfZdheTPA1WOJ>CTy
z4h+f}B`XU_@=!JK8vzr=jgZqr0lZN~>@D^h$tu>cn?+z_qD3c&653%}35EhK*i8aA
zaHSL^Z*Ho9Vl5){gVv7GNs@*g;8|1~1Vw!Lw|_geO>?5RU#EAV2M)oGtCEJ^1aHmQ
z%hg(L!o}^kXOS7{`aEG^mn;?iPYcO2h!Z5o0!cWjhnO~R;+zo>WisYu=p=nyrcuFB
z{1Mc(WqrojgLyyX(O~_l%EZPiPC9n}YwJ@72J;?~0gp9r7D<?a#QGuPS&fBFcuF;6
z6T32o`<B0gdr<a>;!3PgbyEs_3FJOCE$`OhdysNS%wLmYm|h`BXZfzm7=jsVLEmNc
zjT4yi#5^Y`_K=`RI#J<fg9xEx9UGHUqq&`xfiK+RLwcYfhQ5BD`9@Q;8D5?F>bWTY
z!_YA8z$BFlaoJt>NDJ8;=#0ow?yH6)GD?o?qDqlnq6uw_K<3s{Pc74Mj{4SUkdN_s
z!&hhk0wxVb9WJ_cL`~q)AqB2)-Qp*>Y<ZWmDti5ET|@TJLoev|riRX)5>Frnp<4BF
zukxw6@=@%H2e-E{caaY9VK&UN7kK|UUMN2)%74SZHg=W0-0XYXTQW|OFQ3lg&)>h}
z(97d|;%Z}vPCM@|7RrAcUbpFe7x|xRP5P<Yyj?l9@9Y!#w^=O<rE^#}|Cq8TkgrtP
z)&spUY#qd(k!{r!ah620RcZ7TH<#t&`bpR=$uBRBZ>#sS4I=y_BYB)9>z(0vj{mh-
z5{p4`oKa_TQ-^)qTiR7;wkJ1xqThIR-1z2aZTELJwLLz_Wd=8O%JJ?+n61{0oH)d<
z(rsbxH|NUZ0{peCh2{t|USkvE{W<bv_1u4Ll8-e9>W#Oc$6nYu6`nVe`}mXJn;_3P
zr}t55pnQe>G3mSNj_^r6T>J1<tJLx5FJI?}rtD93^%47<qTd8aALDtmbK1ODKr--s
zVRg5*w!#r!{3xxAlqR(mZE%u8EMbla7H%iy1AP3|(<kAjH0_XW@U<NihjZlv#D1uO
zVFPihwE0_X2RUtIf1ewlS$Xc?zt5U=g_m?Jjv~7J%g<Q$LV$=_a@)P(eD?+(kdNWu
zk#xBOiM_nG{hq4m&)<KU9Tmrq-IPg3i{R$j#qPE$-3<V}6y98%0Rmug*3K(G`&BH5
zf6krp8afE5ov{+3c@bgfn!T#g0(VA6O8MDBI#PT^l4xXTAAoY4)bR`AYyePg*R-~t
zXtA8EdUvd@0kh(T*JN1m*N~>a*VB;CFDK>y*g8(xZSQifO(lz;p_}(UCP1GP{dX*L
z%{bpu%Rx(6Q{;T>koUENHEY)s16?n6|F!rk!#);+iK(8-)h#a$ev-UwoYMXu!}y&O
zn_Y7HP=0Cjxx|#QbG%c>KE?xYofzHmcTYWa_QVK_B!v$ew~_yncxKytCAp9E)fYEA
zrK`LqjMJ3X5@D`BT9l7qk12LpFi;%`Jnx<|K1^?Lz9G>AX*StgKinLkOV*&c<~5Vp
z4aqHp4Sl**f4KY|`eTpI-+fp(-QWI=54APn&<p2eV3LTST=djo0692HBLE^tU<)i;
zmWF|ADN(WGd9|55X6*_e^=c27#tBXSy<v1MxwU=#m6n&hY`#OoyxRLl{VjJfQTrXw
z-Em!?c$B_4x_I{hT@d?ksT^w7ej~Xc-ac{r22e`S?871*D<SK@Vn@0E`Ff&wK&aT)
z7c?BH>%3IwI}RE{=XwEf_nz|)7(HR7J_-dU@ISB}8}s7(c;5c%T<(Omg-k(Vtxo@j
z+Mno;$S3AS^9gpi)i3;QJmS>-;s{{l5qzqi;HA}+b(09|`keNtC*CFG^wP`qhxgQX
zc|+j=@j_7VEnNlqJ81mbxf4yR?TvcvVWaeu05%i2$&V6fIp1iq+QZYqbqHF$6FUuY
zRz=9*`2Alp!usM4w68oCR$$LZjLL~I2sl%3ipwa|xO%pB+cYzwV%$k9b&H=?cMOVM
z5P~L6&R@_^LI|IJfq&iePWG7cZPy>(cnORc<{1$MV7(VTAr}sTu!$+|Me{IR3G#jb
z8p{p%*SpgJY{)HZQGBGUQ@;qH{(`&q%z9{*?;2Zj)fsp5Xy#Di2{(Nmrc|A^?wt;<
zC+(v0-2a!tM6d=s-HPM4a@?84L?nlYrWbksiCK}qrBZJ}9E?lIRKcIkNT`bZe9>F$
zo=o7BYF4Q(1`4-qKqxWoKqKo}N9MfrmEz|@VqCbeE_uM4b(2SRi8;N>W4sGVlDIFg
zV|oeUchsf~X^*!n#9Ra#*b8Gf`aH=Fpix~Ao5LZfTF*YW7pM_Yti$Yw=V~FD0V3Qh
z23ldwGLTFVHKF#iCq}1(pziHB%<5tCnS`_hE(MTJ9f8=CO>^jy7mSs33|HbZUQu~)
zww5SEksQF714THQm^gtdIR)H&2&)e-wP+PCd&)4b(fV-pL)xA0Mx{-O3{fBqm7o;v
z;g=X|@%cm$#S!3`X{*ocL|iF0W;X*NPl`u9n8-|6HUe3t7gpAz_D>*`qJ1M=$;AA<
z^&b|%d)uy0Oh9(tUkxI!3BKP#wM3!kYon>UkfuX~^rxt+75_$@@cac%`4LRMaBG^_
zC*+)@y+WlnV?8DsEuxlM)Wr-hn^64dh77dd3T^Z2p)8@uS)~Ujx>KOFhXMlZN;Ll|
zoxpq^Gx?okrZI8QeZfV5;b7m_+`VGrV4y7~VEJ));ZgfVw|<*_7uSQm<gT$7t(tXY
z*4#Y$u^t~c9d&1A|17G%m_RG<;H<tVg&g}<xWKz*e#?`{c|h<5)iiG>$dIQ!#^3bn
zmIk!FTJd`o<1nY>%nzvgx`)!XCRFRw)n98<L5<h@axV%nm|)h0D4k{x?c|tl71TZF
zB(h6@ucd%SgOAYpZD^ZLUTXy#Z%xXZ>7|9e;PhP=_6w!<pS^jjw&@tmbkhNlI%h{5
z_b{73j=Q$`ZArLjn^PfF2C*X$lS4HEZmv~^_N6yo@YM9iz20W1qIV(lq19y%o`V{E
zXUido_XOmn!mV#b78UItN|JM(z-I@A`UvnsLWNquKY$%sv<b9ywyEO{k$Bv-5<_*p
zvzypkp%`(cO|hhN(Na@;)Bb7kJA{UEi*7Nv??4S1gDxYr6d-27pk~5SMNS1H!dI#R
z$YCr1nGRsi@qAFbJ&uKw)J8)~_K1~(1B*KhNwlXr%LayMv%z<QJiH$Z-b^KtRbR(E
zd>fzF+SU_m+JT^X1`SK^E=L|5Gomsv!k|;O0F)8bH80RE4D^WlTBBH6KM$)hhTqU4
z0R15ISF?^fYZ`C42A^t5e3IhtR}?^kWq@i-4j_FVWhJbos`!DZVDJU;cDhsqit!PQ
z&*am&brGg^u3M{^`kzog|Dw~zO^=K(f8sr-4M>asN%8YdyN-9A$Z6xpAj_-T=aThV
zOg(<)Zt*j;94Vhy4Lb&+G^@xX<Dh*bdU4aS;};3_W%kDVz8~+M&HqUG+_8F;Q_knM
z|B@8@N8|dy>T%NVozE5bX9glaIpXGTp3mw$2xmdw+IQuTKLBAGhJyDVPzhnd317a|
z?=>%aogBrwC`z}C9yeJq)}+y_Jf%h-M{Fa_H6^1&de97yEu+>;GtraxC)p20KmVs6
zIPU7h{DqI){6jb2`1xy`gQI@>tPGh;s-Zzp2FC%cmq2R9v38CO6Ie=4Eo#-QY}n}w
z={Gp+nEg>!V|R_(R#xE_X1UrT-6(I`kAB1o-msKAb+oe%5P_aD(tl|;()dy;S?W$A
z`_p7>4HiO1YMa54$jVI9AzvcBRYEY6_3%ELAyoNba0L38i5uU1RzgC)%up;$g5r=i
z4Kdun>L?{+9hBfPXmhNXzd(vvW8Cvc8~AM8CbET8RwA92iByb1@)$r3iB%IH4(<^L
zx~n}!OF<c6v_=Xx7Mokiylyo@tDDB5n?&i;bV<%oS<Bpb;&Obf!F(rXbI8z;83~hS
zTgKjK9O6VCs|2z(R=%*PDSk|{jgMI2gc)dLQHSVf=uWCVb0rWqi+#k7$2enB*&Zzd
z15#nn63|su6Om=aW!8ge7D5R41f*yN&_(2<-7qp57!T*w#W*Hhu{b8kKm6zGB(Dh7
z%QEp$2AL`kt60p^1P7Z!!fKdACW#EaH<p*04X84>!pyh}_0B>)l8tm5TQu4hle*SS
z#7>Md;wzZ1fC0`xrlMHbxTnYPxoLux`2-+|s=O+ph<KdB|IdWvTcqUpcG9pM<}H)(
zork^<pVK9pYDcDYoOZ!p$WcYc0~?T2+>A-tjcf&J(=5X=h4}Z7L%~dg6=PDzDnM4;
zjKVoX=Dm<-MA1<>QdVUt7b85aLeZC!(LG{uT4+EiYRXzcW}0T?5RyURK%EEp^%Z>`
zc5oeIMW}mD$54g1!?6W71bqnu$Q`EZd`!TiawMA*qikdB9@@3N{n#7aF<u~vSpuDR
zMMGM$YmHcL+|tOPI}ziX!Wd<HXbPFXtcQ`sP$tGa>o@1^kagn9<O*wW-w;6JS>%oY
zZMQvT%tT&;5SeOh()6ITRzmm2E1f7ZD|4@1vV+(birN!mXndYr;B~jHsSk4okCAQ|
z|5;<q{RSL1j#%t5jUaU;vA*qMU^00)2p1XeLES1Xnl718^D$`#cf2>U8bG~HY&Ryc
zh6Yk8vyn!jQ+5zTl^8Dra~jY{SFmEF3`zKnJIeBG5ljT@eU4_9k{=Tv^wCHx2hXTW
zPzov&C)}BKU$NRa)Qk!l-Y7Y7wUfmdXbIRz92S-+byyiNbR<^B0CDpJ)kz_UP%&|D
z@o^wH4rqcD>LNl}iD>o<_KJxG0%rV&>02b80q&331KM<?%ma|_5e#QG)JFEf0#~3r
zR6(gGV$vqnN-?-%*clQ_sV+xnB}`k+AndwqV6RC9I#%<jA&^UNnk?!f$~eKOcm_E-
zg4H^MW+6d3`{<^%I53FhGDQLa#Gg`H27+Qz%2n$)7ZgNvO<W_P9Q`#+aG9M_pc(|O
zl2Bk7Ap>D&)J9w#cF^*0HDcaO*=z*Am#M?~*Tjk8x~vMKPty4}72p`@uv_w!c{Wk!
z!RT^9$}03R4)-qFs;|_sn-jW}o-(P=PV@vJ5%9KiQKSoGLvWn+5LlyFb+%X_Pl;vN
z$4WufH*wzZBDbWJb?bzUo(&J&?HMC9b;OCvGM}L+PjJrFA4uPR{DbHS4Oj9Zg_Jxl
zc@ZO5P$W5}5c4XtEgn})d*12SH*Pnm2k2$S>u>^CE?A;yCoI{YrP5Zxq##!{W_sE_
z!z80Mi~dmcP|2hK;zeLEs=<Guik2EG+7R@a2<4!D0kO#+$HwE)2PGte{Q<-~f(5*C
zhEDW&frFMFxJd4s87s;Iwma^<+<vMlcM=5OD7jJ#Tw<04FDuI=NS-2ucd=i~+^{jF
zFQb$-QS5<vXVJV0g{X?YwXMzqD2T!OIry%>PAUtwE<#%{3Ufp(#bQ__e|rI;OEsf_
z=NpQYv0Y`^o3Wt<&VYbQRvJ?G+<G*ou0<O>nH;6USBH6OVqv?{byVlnm%ZJBpqjX7
zZqcsrQ5AB1ligaG<EY>si$EhPVG46M191hlXh*%3-H9GGa)-b6rI!!}6}SfusAN9o
zNX*L$jtlZ#V>|Dtp+~IPveo6p`dTEpLg(`+)|91;S{SPBSb71X>8-kkKGMsm`12C8
zaQ_h!EC!AW2i>)XnBlPFM{5uaXU|dgWz<J_EdW2h^q<yAXsw`jEER|Vj=40T%+Z{{
zE2_j0DGfH9MrLTS8H$D3Oia2{+hb{|vikI3M@FBsI`?AOB%MkpR#xa#W{dzeArh}k
zPDTOF$N8X5W3<Nj4h@b2qgyEt7>g|jVwgoB`{X?GO(Y_@L<&8Wx}lb#?_E{6LO^>?
zPX+DD79BTCsfKg2Ss6Q5fOYU{cNwvnVyqabovM(~^$I~uJC=<~QY!JMO(|vGisBe%
zz6@2lQQ;um(Y*k$UKY`5VXU8_=RYj3PPN#u*JPMR;P;W$h$%XUnFP8J^r&9li9cSj
zVv@;yRx{D0k$iw5tRhbh`T@f=`YMTf9$8DFPb7#m-D5!SZ0VRt2&2Jq@$eH*BAUSj
zOR8aHV=hq+*J2q}RN7U-HXUdnD5to>GD?R4u_VO)O%Fi4P0gw~i+WbwdEOqghaFBh
zyCl9S(&7YyV~E_v&($BJTGN%xDBOcIC<U`I1XW0kpn^1wLt#wHG4#jL1*7yKl0m5(
z(r&}Iae{%bqGP=F)HkG3vuoK1zeU|4UiOwAfOo@sw~_k;F8&**xvvh<E+sc-#9J>q
z{ayX}D#DlNeyh+j9xc8(KF;r~-o>v6+Tr}>+>>MCiLm^K<chPOlo#%-ys-EdoIyyx
zc5G?z&&0bGZzDNDClAdSvqb_fu}ut3gtwFIoDnuiVPWCrs109b{Ow@Q7MIuqNHj|2
zusMLjSb2N32#RZyR`rRVsI?c#QwBm#*tMP(5k4(n3Dza+W^o6^sO;M9EeXyZ_NZXF
zCSjysf30)UEw;Sgt8|thp@paBCL8DO=l#qrn<t0dv0Qe0HTS*3EHCdUyxRGBd))r(
z>fnPvaTljMzHVI1*E{d5hUjc2pQ##Od(pZvRI7f98~4?<$>OI@Om939Y%XnHNPdfc
zotBTYsoLxG$!g(`j3<K;T88<@zvSgjN3lvOUSIOcmm3%9NU@%LS8NB%r2alywjW_f
z+F_rCA52Xw3HEitm#Q^ZDRqk96lH$Ws0t1X*v`9&Hm||G7kdKG8`GDUxs&NJFu8-X
zT*P#5<)!UBbA$41J#wkYo=8CEYwx(+_&V4uB(vbStLd13(^2aH*2TJLKMaF!EV}v2
z?2F<qvUm@?bIFqRAp7#l+W@;4(=a67AifgGZWh>G1d^#q762p#d9c{kRU(3-up++s
zRKEFYKCx=HEMdc7o?QK0M2&CqTzt=>Uja32GX&&RQFD=AI=2S<AlJvX5Vp&^|3@%g
zq3(`@QzybcHYi?(Ha4Pl*oWd!^YLaa0RixqTJmK3kG*F4YsOdS-f5oOf2H_$bJYRQ
ze%d-e{*F7bIlF~?cpNaQtzk^JZrHW_j|}abIEMI-;v~IcH<N$&lrf2D{Pn8w&D{{a
zT5Z@Ab^n_J2E@I!jin{=W6r<uCF4(8H)_pKIXy@CfV;R8;$>vTzt9ae@wB+;)wcDD
zxB5;%%X^VVa$>Ldgjc%iz;?Ko!3^P(;Jc#k?slfxcZ7QX*uvou%IEJwvI;Ma1EFYo
zzzCvl6&H?%b!)kbO!yD~D;2Umc-Gl2CAALzO6x39&iwSP+UR^Zkgt!H>fvs9TMUWR
zW%|y!0$|@C>${u#QDEoCkGk{LXD&Xx9gr}r+(n*pCllxEON)yhl#(3xbg=$tOG*Bn
zk-Rf+UTbe3uwS%d1Dyx3GyQb&`rK0iEMUKZw0e67z~6-2FV2P=6SZKdbi?z`))Dvg
z_nteCOq4_oB<ef^pK8LuAQ4%%0#kx(6~Hu;e`;J1NdLzu-4!X0;jMf}kd8em=imMO
zZ021Lm$t#kb`6SNy9OdW6~dZ>ow@2h=avqIhinCmxE30FKruHC(7*BOqt<|P8Qgjc
z84w3N$V}h(!H~7tgWTI*0xz60UJ=LBZAMM>fJx@zsLUV_I{)g$t{2^!mNj9!QvAyT
zGRv=rxUzpeUHlv;Hros943nJ^X(Xwi_iE2s$q}9cA_`NuHdxKN(wQzhF)m!pu^=R+
z0P6B|2rczt=F;S4%+4(BNwaQEvjsyMaMy!~<-Zp!CMcc<1*Ox$8zIaZ_M97_$U%Wf
zc+tXjL8fe|=|S(6Ryx*yM}Kqw*T~@bgZ!8^ef1Ck9!U0)Bae=qa`mCBkGhMWEYZig
zJxK0^bX6<;#Lb)9q%rZe(T*#R9KaWF$qmL%n%1KD!TyCr=}oV;Pb>Y@w!iQYJHmJ7
zQSf5GJqEcC3};b4TQv`g(N*`5sD66VE+~uz&Fi>H9ssaNL6?6P(E^voQ6-IJIl6a8
zE9zaxKGdsox1QML5ee7Ej`9FhzLzVzcy4hc%OZvl$-5&-ID#Of$&>nJn4*+!%o%;N
zqnGN3+-`RZIWn=iFb`aJB-o6bc7z8|c)FW~23KKEnkE;lrO`!e!<>sUJzxm61X_Ln
zQ8e6oOA9Yk6-wD7+}hznQk;&8c-}fvrT%58&aOI4$v}qfTouBGzdOKsWFc`xz^wq{
zQS8VJPvWEVR;g8$?%MDnR1$koY{24<r)t&)gP&FRh=JX))K$z$Rs>9ZLH?h-;GM9#
zH|X<YrKR@oW5cRT;};)(%1s{(XIEe(!*LOP$po4#9~fT>CKeKYY~b>b^X_I3wiFQF
z4&>IME$xCtb;rSwC~%_4*R~}S97u4$t65e`*;6>oQz!X?msxtM6E+a={!NfNM>}F?
zmDdF@Z+W2wv9+XC)}f6*DW?x&;`rF*UwfWLZ6SFQO(Lz;y!}7wAv+@(u9SXm3@zX|
zYT7qi6$KvOR_`3&-?4f#M)^+MY5oqMxXbRb(r?%oVPwLvskY4z@O@qe>hfL9<RW}G
z;M($;7e|j-*qFVLN2fAC_aYJyyy1aL-?rm({Bf@~X7v7aZ0rl4kNk6X=8;KZ3>3cQ
z;o2Z|PhaQZZq%!R+zqc8efe=S`qGNN(^0aX4_&j8Qd6~7YQb~o%b~Cq$^tk2vUnCY
zGy9ATjDjpaiGx|847+jkbl-FkrGC5PKH+S>BAsvA>N27;mNZT_7|wnTcYQHYxUu58
zR^d>vFb0LZ{kjK6+iO>X28YYXTyGlIGt@#C;t)0c2`}i`@d>XTXM6@$Ip1LjBXn*t
zVOD;Y#CA6Wc!r!0*I(mLomH@-AV--*VJqoUJA^-ZMe0=Mae?7wPo1v@>ELp?vyN(1
zQS<LUcdz7Ss)pkOLnR6&xNKtK5sM;L=Txbe#CXcZT9D6YVIzWF&+(GZC#bXxU4qH2
z3mhF6764OX-sOSb0~_hMYWfaA_D+GsqIn&rhd>`bLp~ZNker+NOPK1WV%j{W;D>*T
zNo`8@p_jwf$=IeOqQy%S$}-QY@IE8U;UrD1gjoV(ja<zR8^DqZf~ugwYecZ$iM*7f
zfa}@S*epr2L&8!p3mpqE;1dY?kkJex99tc{A%Rw-MVG;u)V6w72{mJk8$CV&z}ifq
z(THd<0vrNs5S;b3Q-6J__aad7mEd0w!HhX~C3rmg>U`%Hg~;z~e<4J^sr~({#lfGO
z829|?-c?75RYmhE<^5CVp!FV~ec#;qK==Q7lNM{B#-PP8K?W_pZs9AOGVt}LrScUE
zP8rVuKi~B}FaDVp`5w%kBAaL^qsMQa(D?M=jgqzha_Nl-JP&?~ta@C0_YAByz^}jC
zy9%DS4BeDg+pAs~k;eL0dSyfh8kzd?D{yyy<GxjY=KEJw&9&pJ{>=HeE76tJ|CIjZ
zU%#AENZM8~sRehz3*QDzRg#vaXf&G2YZe%VL4e>K&+#5w(VY(cWj*IUVSBlQ)-C>E
z2i~^vLo@E_(SKw3KKE8%5BGB4bMf47!#br<v!&cy-VVIE`tva_=gfJ1x`%8_AO93-
zB_p~JSy6CreL@=Wm3!$E|14TR{ZBo-2x<R{$112;egB7d-wF-R!%ceb_8~eCX?22P
zQlJe766ZMrf#6_9%#y9TV<F*rXJvUYK16y&V#wMVv~`nfMDIyo6-Tw@?z}03XR3ie
z#@et6SU^~4b`vB`@(fXy2@hwXH&`@7Gq_rjebcTR6ZRU32VrLe9WQi>6tcJRlIACf
zskMkTIfw0N%H%3)@a?H>x{+<WLG{2{Mjox4Qs8EqL2N7I0WxjvdEOpzu%0gDNz9r_
zXJ(Cu#GGZctxvb0%-jwwa2-YvmgGwAatnk6z66lZs>nfDhc$SrEAom3BC9Y{fF7|F
z^n_p`A)Hq;kPm|Y!Zm~hqXPMdi`5C`+R8IqfoYIFiUq&J8OMT@dQeTJ;2GI1(Pi7$
zbQSS64*4+iEo?-WL|{sOJy;v9hY|lZJ`yBV;%_5yqGGo%HFOC|rzhuJh5T%>A_s1&
zrCaEOk_4hhanz97fDcg{{07muzZQzlqM5ky_kR)By?RbChXLs@C@CQ`2dgw=P?GXx
zDp{zi?jA~bM(A9&_t<Qg%X4s8-9G4SBHOh#Z#NILQODfc!<`vB7x48v86y7{F;LsB
z`(Pmm^`vZxj4dZ)pec-c6c;st^2tHuU;^v{voXL1Yy$)EdF`1K!$ew$gQfsGV!?}5
zi0NR7+oy6c`xIzCXyOpZ+0vAz@-}k2YM`toDTO(0oXjPlp7Ax0k}9vr43U?NJqwfv
zXqA%z38(b<`m*dGh+q_8J<V`13MR;aBBYnthsHd++zIg{jz2>fALPXtP+X8uVNe0p
z6GLOb=~`TJ`ME^P+Eb%_4+l+$y>72{?lj`A_kc@?SxCgvYdw~G*>+(wUN*b+ouar%
zG}yBSWHPr^%wru+gycwV0Oqt>@Cy16H=0<!Tc*stngg*O0ygdp>^w{}_R_sEn6=X-
zq9a+w8{!~f#o2bmI9%9=mOn~S569Rtk%n`Fd_skz%Zd$>3v`|M0Rn-}=VOJF)VY<X
z8qjB3NMCjev<~o5zQE^N%Y1{q3)!|tuBr<!`+a78CSV)ozN=J$4|9!W*NNUCo{b=!
z^Tc`$Dr8+;c9LXWITml}e1^2y);1zK?2p>hpZ<Wv<J=tc+=%~30sePknF8~c5Wfw~
zB8_jQ86BuZay(cufOSD=3SbQwt@z-w#Ra5aX8@c%IBl=HXFt<0z8YSD=zj`zK=Kh*
zm3a4Rzk?!Dtr`1=|MgbX5edxHLqozIU1&hu#eId{Isp`<lMWXdA|S(#<lY(V?uh;U
zdWmdj6eAU&7!p)<py=O2fxgK~$Wm23@YmoF8EBPV{4L-e?ld{VL$;Y{8nYaL4tiJ%
z`e3p_Nc`J>@c}fgI1ET7z&;6n+o(U5G>GbkM;p|3m@QzeFGK5(Yd4+yqA|5>!mL=b
zU=oBFZK8%fK^4D@_!nAAHYQ=E5<`tv)5ZgII6!@Xsxp*0ije!VgT23O*i}1&*M9FA
zDXu}1m{s}^ma-En#aZ|uq3DCrCOBt`%Vwy?2eqtX&|G4iNeCWG%;hdNstjx{GlXu?
z5vu;0$a5r=%L`e*Ys7^@drF5m5oPbdH^WyA&_@cGI9ov8gyg)oAkFZU<>-h0x3!&r
z;La8LfWJ^k_~+|F9%fS1ceuD~*lP}ZgfR-;F4Vjd^o1ZhDRTt%!zeJlu2V^RBgNN#
zN>o_WNYPp@V0_tz(*UHHp;8!eINCn0|5Y)I+0heYIoxbt&OIXh*U-pCb>iw#a^pAt
zSKo+H*Ku7p-l8Z13XW~@9mvW9taHN!{DcodwQhSvY0whiPQ3z$JYL#BHBTD?!Ms1_
z_wk8E+X5p;+FM28*i_H3d<Cf|{YY+9e13G_GUcJnGF6>3Ul!S;bH40}8O-buwvbXm
z!$2tPhp()4qy@>7ny3x9f9Uq4NWO}D2QVq2OwggC1N3~xB3)?)cfr9ar)2bLc^Tn1
zZYfeXDmVzdr5ZsP<zcL((1@ZS7Su54t6Pz#2PQG-no{Nk4kF&8JJPp*^dT2+gF07=
zV<=?V=tIZ_hV?G7l#B{)nW4lXxDo|5piK=S9A2#uDTPNHm)bZo`l4msLM0!CUK)3p
zcHL2<;QSdikTOkl$y!EX2&MT5PM}IC(u7ip9nr;vQWSq)TL`}LhpMzm;i!KoF@(}q
zt3-4sqe%mNC@|12522PYCHfXGV1}Ui8*$7g?ZZ9^sBaqRvg`*j>Z^U&7Eq+nMB(YX
zjl;ybh>467%1D^s!@USoOWwy1#!NIm-t<uC(E`zQGiYhpYBM@KDgaVcaNhU<V>l`4
zQh=EQf=bbkaZmUVh$=_0xCpg6vl$E@@B>N8V2|E_BRcG>WlR$!>`^I6*Z$(W62^_9
zg7CFlG;IeFftN`J<LsypO|*hKFQqW6kR$|_aB}zy0K-%%1Tg}@?<;B3Rkgla&cD(O
zP;f5`<uPN9;KU?pH_{F;X7PgDfGQxX7M!T@p@5ppwglp?Pe1f)xJ2lp(ZrM#YA>1+
z#z}u|=tK=Wsx@%9SoZwwK;{yg#QqF4zm4{a=1|hcSc8B9Tc$|ULh*zO2A3e_cLhp%
zPT*>Bi5VMf6VZz<8{IT)w-v$AT3L#j2T&`#<*t|h)7p*D^D2Ey7`C>0<$VyvYJ+{~
zZQLTpM^<bY#g8;8MUKyXb!Spf+9joIZXd$@f(@5)_O=4v<b?x><RUb8nvL+jD$S1Y
z`Ar2gV6*M%qeI09c^YcklVnVcYrXaHm+SXV>5~rIP|wa{vAk)L?>J!(1ho+X0jgHH
z9Y#!u7RwF9E*uPC^rWG-iK|Y}Q*GWMvAw-*E<`4WclwcHf04{OJ6Xr6`T_mw#p{QD
zZ>De4o37%Xd#bQA>>KlT(fg|KxuCd^;wid<tHB?*-?HZ@P1+b`5s;>CdDBB|h?No0
z@2fuGG@y7lvLzecT`|$4H_J+~K}izB%56);UKq*o?c-Yca-dLcD0|H99x7fAmW){W
zYZtFfeEspBq5jhBYYZX!Cwcj!#;aYXT%>iQAC^}4&Oy9u&_iO3O&V=NuD-^0iisWr
zd)C?qmgZh8bQX`!ZQyOy6W+(~`)3}UD0s2zty&_xShm&BJB^QW2CWe$%`sk%GAi*T
zQy5=hx`22-6ht?7vNNh4XfRfS)rhzt@h|!)fU(I|H?qTX2R^<19+*ntbLIN@{^&Vk
z#^n>wr9U?p&C0bu2F&LR<$mghSOEnYz-f-G+nf5Qat~g<Z_FIMMkQPI!$4YUR*n1x
zd-xsKgRf>j?>*&$8342Ng1aqv&l`ya_fvaGi7a-MzChK@fR3g5!&~_@f6Iej@f`#f
zCleWU3%1xY@jF!m`*9_{>yGJ@Cil-Iu|0I@V#t-9;xNyv=NZ5YIPZXSfk)=A-)PU*
zoY$KR-WT2!gWu>s(zalJgZGamou8ZwbF+g*cwC%4u?^zBEzN6u4$hrLK(cSP;2Zi5
zpQ{k(2A|78Ke_igNPs8J!;#PxJK_z5WJ&uHi0U|feoijb6OgCXt;xIlt4G3Ra-NOQ
z9dG>p8aoT&8qh3-o;$MLm9SSEbciMB93c6HA{J-t8k4Zn1<^`z;Kgai;OYQXD6n(g
zqW}{nwO2_t3cXRXJm(|MxkzZ4*zH|nd&Mr#O%IBlV7-?LD5w#!+m5_kr$x(tT`aU9
zo!xf6jN;38T*jt(5ca~{V2lmqu*caX=->fE1vP~Xk^yu>xH~N%f<|gQ-hkmo<Z1h?
zNPV?^UHbY`ZHD(Ai%tyZG32=}K9$-hc)B(Ucwzt&L&wL8z^8|zKa;9~{tgOvk6`)Q
zC(BM1XNckX%mbcuxCzBEAgfk7=SAwkLe2VE59^Jto$rh`ce_+LaXSdhH~IY>CvgOG
zwkcdl{q6`gSru?b?a60b6t}9PUV`LZ#W@MBXx7E+VgyQ52&`A-q5zo!yxZEbSPkYA
z(`BI2f4I1|5S>ZskY|I}!@gmRvH9D%U+Z81B~E=5^QpYTiZxHd6$Wnzrto<$<<z{q
zr@BD(XVzm5ha<o!n4fHir%3XEuHym-VhS!h(}kTChrIrC$&VVZwEEu$hehS;Kc0a$
z8%WY9sp*6IDP9ML<-9_a0s5?nN1ETHoI>dbSrwItKz3e)0RsZ|5f@#A$Um#@I9dI^
zA+B%uTPbVr6Qv$>0lhdW)Na4#lwj}L$M}3VpTgOf#-ZA7z_42Ll|5jZI9p1&m$y&B
z^~7(&ox&gC*hLRjh*D{{mxfHT2Dm5VfUpixri=17o2doyS#JlV@NlB^2J*-6M)OD?
z+gO3+_&jb&exJayE{^-CqO7$k$iJl{BEZcnl6nGr@Fm0q$n@zsM}pmhxb|=Fk@`@1
zD1tE_FSXlmF`3@K7q!Pyc<KT|Jvh@6LHrCp3Q|6@H^+8zQ5ON0ms4<VE`=Bj?ExF!
zd9E?zrNMKvH47HfHE?SwDv0Mf8o*`IGqz(5UNZXjt%q4&f$xPwwI{#c1RTMvpqFEi
z$HtEceV|Dr+K_+`!TcXFL^3LJ3Q?wt`a^fU4YvtYbROOFDI;o{CDlq}L1VO`c3W|R
z7Kn}r)m$l$V9tjq(mpur*FG8TFp0uOs3A`Ozysj5od>+pc~JRb2C5v@anwD&HnKck
zGc9h^YCAr_dm$&bK~l}y!#*}zv{C5bnNsEys<xVvp@cfX1(<(;jz>oD<^n1V&bJDW
zkA$s$I{SedHF3H-J@^i%#u(S{|Ag>u_(DKdLNl#%(H@t11v$eExDuYu)K4^f??+Un
z)QbGl_j<qQWsJu?Wf?tD0}-EX1C0wF{2m_g-~$n*2e96Ec`3Q(d<%VjI@bGUACC=C
z{DO9*DdAG3-WPcnrb%VFqDngP$EoDN?Id2PC4e-geo+E#-z5s_4(u2DZ$7hzV|F@Y
zcuq=&ld%L=iz!=SeM)wr`0-_mJ;zH!VK0kuM`E3dugoWQV_`o<K{V!FsA1Cbyors%
z^kg7IYlz?Sl_-e1YKRGu&3Y7~WHcW@0yN_0FqeoF&6u$xB`)S&E4F98)q!!*uz5n@
zYs<-Jjp#*nbx?FMq7m*?v3$W0mw;1sLU1#IPu&#b;$ygz_$WRGv7>9j=P(UFP8*+t
ztpq;jRz);^vd#|cD22deecDVA47G5yHxy`w70_6nv>_A*K`;MZ(A@V&%+<kCwKjxV
zb#-uUzn=KmaPDWe#h{qK(zf_l2zTF?%0}Sxm$t}@j`5FB>`l|+|Gx*Be9sYLGIBmX
z_QVr6H|u+(ylOKH4KHZ!`@Ry#-!rGU$xeZX_g8LixA#A7PC@>$t3=KIe^24|u0B#w
zlt%L0n~$hsMGr^v@Gn~0Lq2u$p8|1>kfINWz)B&J51t747gds9dSu?&wQcnc9QWoU
zCI8X~{)ulAKYyR2X0I*{R^R#$zniI<r%@FO%!2nF)hJ*{8O#4zaun-C4KsBtrMFUs
z<qL;Hq68!;Ys@jSs7{z0mK0(oEjQ-G`HG%efzh^J_3C6wFT}jGNrDx651Azl5{&@B
zZivS9Z&5l#wfK67RA+ji#f*>Vo)0`Vu8prC^Z;U+oih*rK<YBL>)@0CGFUPwSWw_X
zqqP+pDuiJ`R9Is%yoSv%)SJK)O{iw<TOfssE7ndn%rDVka-~c1+Ps!!VR3cEaa&kC
zXkqjx=~jWxj33oAf<d^ifLem}yiPTBSx+Sl<sbfC*0r^EG2#@h^&lm<Y+zl<w;0x5
z2xeln1G>R5xt9zFy$nQ-XhXj2;(y7S*CM*^gP7t^0U~8BD_G&uyb0}8>L_=;$Dldv
zrTP#p%lxrmo#cN}$188E+t`D3n&H@S!!}FTzw#NZ!~mouCt3)_jj=!~$4~%R*oG%P
zSu*y^Sk+O_bDR|1Aw17^z3n<UlW#3-A9md|3~OCGmRVn)^%1}#9pGJEOa|6tm8SzN
zgALd!AZb1ps`#BX8EhjL<@$3c#@#L%oge%Eh<pF&IIio?v$|NMTQY3}r4~}|VdScZ
zLbK2WMGE357-l!_E)<$Y2qG!C!{KPPG1+QTG;NJ!hH)Iv%(|-ZKo-E3L^80$*!j_b
z+6=5wY>8&PN={Bp(2xz;%1UB5S|xwP6vOe@Ihi#@bG%A+=6FA^0NRR^%*pJWvr_;X
z-Cb3$?z`{4`|ka|`|h)T`}rJRZuDwcu!5BRuK-rsrUig73J!teh<6XtEZJUlkXT=W
zHVOF3j|$xi2_h0fHCh#0Ei)vb=)Bv~&C+*N*al&&@Jt9NKOaO+Zadhi!Q%dLmJ?9H
z_CBoU@O(&&(=9{eZPOIj?)(E<+Io?hh>&zR@V{%(E9YAN5{;M#!6x$`xua8^>=>TU
zltu|fZxsUaa#X={oEgBfV&c!Z)}R**`_{b4a*p}_c(BJSri~;bVwDx=ONGJm{7`wm
zhp1N5m)iD1o~`(tz8SSon=ZrROlZ+!!38h=48e@Xpee7t|I@a}ZC?njQvUo9gN=;3
zQ(X$6wo*Pa*p@z#F8gT}x9pMr-icW)9N7~>a@^wv`5yM@n(7v-HrEH3S%97S(%L)R
zI}6^#zIgk-;g?!};pe6X(_m3lyl(Hi!HZi)=ABQwfc%185A^Cct4{{r1t!>sNxt3V
zCbP5g@Rz(?B%C#DD`-1TZ}qLxlbTgobf@k@wN&zeCm=4B)Mx0C62~wug{SvKdXJyC
z4WvvvQK;laG?@dOApM4>#rB2&34N7#C7zTLZJlWGa4rVrCcK;Q>(KKJ3UzbyC)|mo
zVDzLs8gnkX%ZguqbrpEEQ3a`@qgGOVLaZV-+@3T+@EC(+&Ne2%4Cp?fsmw=^|3&DV
z>%u|Pkj|yr#(u8K3uDuFA*O*>GPH^K^WmK{tf*&qGTRC|h0z=x@H~P3F}X}opE1G6
zC|vEyzsU)y@XqrdL7eE&F4lH2w-IV1G>h7NRKs#pxjsQ|dQ!9xbPOr=QWc2Q5T)9A
z4N%d;pp<5_$`_32)iEzeJX??&UTo)7NF04p2YUM_->kS)J{PbdRKS;}3Ft$;0e&iZ
zj6{R)I1L;#m5VnQ?n8Ld8QNyI%RM!q3B(ng2rRm*W0lin7H1)6_a@Xtnx#At4w++8
ztM!psJF!j-s<;3d262*F#0E}<Y5sj5Skn?^7G*E&O~~{?>>hm9MQO+@G5;%s@98i(
zZh@}>!Vu(ld+06}C?o=1&e0d|_0Nx)vNDE0tZk=#de+((=*QIV7LA&M<}ej^f)oxU
zg~!-wr8)Fq(3&u42-c!MRJisR4@Z5{G2*bQ9j{{4K1&E}4a63kg#c?R8)i(<WGqQ!
zV=SQ0v?(;`grOjKu-VOCSIU&UpHEuebiSP=c20C1oRAWxmBGZiR00Cc4!!gijcP~i
zP?#hWt3=d&<F7s%nOCJROQt7}u9;{izCRkzxl>0IU@!KHJL6hIqjN5RTu5=DAHoUX
z6rgI={xsFIVO1KI*q%ek$d86|ry5J?cBW#|Xh^1~L>Uo;AGzs?Ra0K#<<oMNj9k;X
z6Q1k}QqPzUjIg!%`X|4cZ)(o)tRpLHl^&rBs3S)&;3r031CmirT+N4L-7c&RSZIuZ
zZYg-|r#z-t3`Sk=E}k5>9Xn^oc^=9g+DJMcDyT5_S%ARIn-?I;<$|Z9d-K;Cr?g#C
z%CH*HkpMD*>`^lcpu;kx@i9_E-bF!3i1p(Ey|lYi#hgSvYzfA6GW#$`U|J!r2nEvU
z-36>=#9y;>Y!;wP5)NVaV_BNfV6b<gYI^MHoGa2`qU){ieTcO$4q3N_6sSr<<d3_Q
z<41|>#{5_G+d$vpUP&qxM(-^J5ZK5mcvzoZMjY5!vPm~+>Xaj@fv4|H29t=&!#78l
z?4hQoFOqjUNTZ7(DZeLlpJYYYOl@zPu<BR-%R7@XColp(e5~L#*=TgC+gk+4=2B@e
z-w<lx(zN#pphA|M9IS<?!<0FvJmXEpljuSZsuh`%SYj3$iCwUZIZ`GLy@eAg@}I{-
zo6bqbQ0sV-XhSwC>{icD2dh0x@uSbYr#RzTqoxZ8$}>pgfM|Kl98VdeKB=BixT@kr
z=h5LnUQi262;5th#Vx_8bI!wYDH>r_XaS~Iid^FR6X#>;_FYWVR*WQ8220+))y}m^
zB?pIXk91P`xEcm&IhSf5{OUWuP&nRqXLtwrWZ$W9>f4JK!-tM}6E6@Udh%fT_rkgH
z)>&`CE5C5CG4*Ay;~XC^p7Gf;s)}9=!xQ1uA}=k##_+zOvD;slo$3N{wZV&c4ErYU
zElg|)Cl<r)r|S1Qckb~@i|)k5@PfCnC?0pGx|fE6qo+MVTGxg7)2%pu&I*Upsp7%p
zShc)R=sK7@u_aEK9Naf`e75JM(??IIN98T%OUc}9Yr{*YqlJUpCTi*LAN+Xg{#6)%
z==l8OSAT)<l5hRlEyKU+Z=3kt!kyv7!xzQ|2O3*v4o>|{$av~ad}+^>q~nMlmfd_g
zoa<3*TYNSb2FM@vJy!yxLh<dV_Y}9(U);Cok8g`7oP|Pd$=b0F7<lTrp>yHF!55pg
z;+2uX!tgJ-VO<io6r1U7r=Oohh~jT1t-pwqeP8u{%Qb`Yb5=4m^n@$r;Pk3v)z+0{
z)(OP1@J_2|;7gYN#5(!q`NF-<ME_I8u?s_ASl9ZCs_#BLadwQQPE+l8@Sfjz{`iI6
z2g8^D!#nSg_l=U~;G@<|Fxp5ad3|Ui&ipe4Z)S0@Qyo_*^mL9L+>n^i2L{C-OqpxV
zuH+^kfHNXgCb+kxkW(K_^hI?S#a&5AmFSiBgw>&Y$VEk&c4N6*Rrt+F+d)&ib7%sc
zXL<93Kj&p3xhvS}e7XG43eL(MtSC#ppX+8T9D;d{$J1M?-}=LMv5Z_c;wKjtf=^s0
zV$IqS03n_{bhR*hmpmlv^S;>d5a}~neDU=Z#I(l#Nd$7Wi1gBZ60^k$Pn>Gh7KUC}
z3eKDUv*zThts8FB{3>YycCg>Yo8ed(5AT!ZGu>oC?geJ7c6xy_UfdamDoO5$@uc(S
zlH56Z%4ZKPB9y;W=>Cp>>yuO4jpMz+$lA%J!bqpLd@&^q?P5Cq;?B|U-2Q5MC4B2@
zbL$VR;<1<Rll`@~(r~B$h2DGL`#3o3)?Pv#Mf_VcJC{^|=9}rdonxKq&fn18O`UW8
z(e6Jaa;_B0PObcbv|VLkOXCi!Eto3p2$j6xXl~Rs+CZN=AQ9#U-=!*OQsH92X2-x<
zYWn2!A=zUUTgv)qr@;nW1eZNdG1ROz4W9C{!cnfo-JQ9ut42C=<tuD_cc)usw<*x9
zs#f~=x_p_Gr)$frz6qju|Fd%b=`tb3)x>_4?fQf{B|E)4LvUyRxtY%cdA*!|US2EB
z?Q$OpMDhNm`+`HKyvh0C(463v)V3g@zr+e9h0k@w`H+auNI^&xWy?YyEY2rlvmIF4
z3G3M6wwgu*nhffIlSNYQig+@=^)Dtq(9)PJNkPmzbLOs~{Iuwr7rWHL>3h4i$E_E0
z<txefOWFj94uU<$;^BGmiR3O8;}ickU)uU5Yo8=@#7uz@;b&)N)AFFTGo4MtW1rWK
zo@!VxEaP*}1P3#|%UB!=n0`xbNi-*(hVQfY99*{xdB3tJCABO`ZF22yIdLh_QKZAb
zSVds0SW{G_?Yp<$AA%oQll6f3$S07Xxx3pbuY+U-g}1=X2Dy3zdtY^gL<uV1IDR7p
zE`K1d-e_Ju^d(khkaoiS1{=4Ple-8uPd>h6oR`~Z(y?EWeK)p_Jyr+?kqJ<97j$3x
zpJ309&iz2=HOAvXS<4e<4_3>raUH^6eWn%E3jiLQm}U5>-NDXkgIV6`DqL@?{?$&2
zz|3axw!8;Szt!KfWOsjO3EPX<))OG>-rU{A?s?HprCl|;mS(hFX}T*7roGiqkO5%w
zV909BV=XcO@8e^(_n;7W6ns%0er7Cuxv}~q-E)n{hvM*%@MY(&vYEQ8C-aZtV++mq
zDqcrimZ%{=Lq9u#l$w(8Nsvg;)hIXFX|VBXXE1Ib5D_8VnD1IyUx;$|rr42HZ)<f=
z;DPM|t&T5h0HKw)S_JmBpoLBGyma-w$a0l1ZWVt!(z(K=F-zO(Y5C~cnVdIx?|Z+I
zzw^jrg~R?SpwA~4)KrQ`s+ek+e_-<dbo5NME1h$Y;YQg9=pRz7R2%tC=A#0iF`ML>
zZq`LgmM%>+YnUEe$5SFCM&&u{11YA-f;X}!u<u_SG05=n@eX0N1gJ7~KpK>g?y7c$
z)OIfYX^`gxZ?}ca5;bGM`b7ZaZ6Q-31c5S7px|rY+!m5fw{x4?rOzlHmj78UhF{t7
zp1<mzb0^W@9g|s<T)eL1bfwrz{R9=;h>r&%uJAq3RherCm2mcUlHCFm5RkgP<AMYs
zih+L(KiqFIdEaf=<6*(uH3s4ef&E|ThPHX@yiBM96A(lOCy?*a$-+EfuiQ}`oxK00
z<bi*e0{{1`S}p$N8DR27!fdO*FX7mma-Bxd{O3deeP`dbE38<}fY<_%mY9^d#h&~I
zKO(5qUy_kY>q}qtG!<)F7!r&4zWs(qwuQ%KG}|58ejao83c*Vz-hVvEmPA}2b&|_1
z$SA3TC|cTtj)5Ir@b(r|Hx8{67mE6XG%n*`rC8`P5zktw@kjs5-WOp2Q->tXRD-3H
zW2-h9tuf>N4iOE${c8A(i!-Cp0|}%F>gl@6=;(=TRx(3IJ1$9e2aFzzzu(Bl-GTw$
z>uE=0cKiU;J*tLYwOet*8ZKf1@nMO2iAejQ_Hko$B+j*eO;75jOg^T`zBus&5jgBO
z<=t5L{kLu9rtr+4Ou3sOkv%=jNF>Yse<FPVxBRzbqF+2rNa=EL>P<NFM?tQCH#9X{
zv9q#=TLUvgrR;tCrgAHo=+<*p3h8{0|0+WgJHef+s`%EwIkTLw_ixk=Zuh+9Er+*y
zE8(s2^|GqbkFeEeNVeOT)#yig3_j=n_Rw~*M|9~zA)=YBt?cceID{8qH;d(O*%Ama
zhe*@6y=YyFa`+qW@P(VdeqnLtE!UO+ecaOWZy^AWT6C*DGX<hovwu(i{5yZ*c{e}e
zX8t{gt^fE-<tzT}<9&ng+zxWE5C@e930UkJT2~=DDZVTfQfVuEMT_ycWA+6P4$6uV
zpD6UKTdM_PBDcMJ?F4apc!&DLsY20YyDcL=P0z?B+exRJ6J;kK2T74dx#RLeTgJn>
zFKf+sR6iCR&7TkBu*dQmNh=KZ#hx9uoLu*xe}&c3#zL171h%nx9X(eaVXO%sa#Y%0
zLcKsox47~|K_v$WL<F=I+n_P*em0hilVii|VP)lo)%JqHNRRGHE7q3NkU~G5lQJIj
z^ZsJ1R|J4QXieWD$F;6>z@xwY9wI6Tz+1F%<w1MENjC4{F4k>=e(c2o1#7g1LjI40
zh8BUr25Y^xYZAG(Hz7!O2qZGdPvpQE_QrN1)X2@vwsC<B+3{%3-z$%TCd47VdpJ!4
z+|-fzJu<y^=$Chq`k^|iV3J)jq>?JCHjLhZXDbXp^lH$vx2oX_D<b&QPIw@+nnIZ*
zae=9jNj0HcCv5Ak4_aozIR*Jr(9!&b<5ipGsV#!Y%rHu(+<XE&Fn#^he^DTM1R#RW
zu}sn;Yq7()h^425#`TN3!cREx**(}VBN^ue*O^|FvvshAilv_iJ;fg+4!6>*Y5<#+
z;Pem;qWr@Okvh^gphRqUOG)n97xugAVY6NNR*qcZt(*y>5z{PXLjq&jt}zjq-YWLG
z!qersOf9jsPJW^^feQ|rW5u?9N+h_XWGZI4?o_N#=~3(~u>hD`^eHgi6Y1s<KQwh&
zZ98S)x1aXQR_B7;8_#|37jK1&HH&GeQohV4ZY)Wi_&ow_D+e8-ouK310?BB@fux81
z#`4-%9X*E71X8MUkc6-Rv}ZlXu!dt61Ppoay_L+p+ZRX*LSWTI_m<~{WiMHyUkaa-
z7Y07PhizzUrIS|B(h0%DS#?RzN4(l#Yu+Vq;W!yBh^U-Hf{ITo*T=kIUHjo{)I)Kd
z6|pLgIMNYB{P7wxL7oESV7U(~_uAAPEy@Y-nJ`Rm1#aX^>oU8-#f@r&^j52B)k>P+
z0X6qvRU;vRf<mfb8Hi0Z>v^WnzEk42PwRnYRzsxTWA{ChiV&&8IMj73vK8zC=`I6%
zut0ua0uXj9A_!Qd$3s>tw;4bJaW_m)yAO0x(-JK;?N#$7m1lyC1T;$Ys|U3>nsp{}
zdt=+p*%P_cUIUoklb>F7?V%dPNf10L+yzV-rcg-Si;8~D4)z{W|7{*0H4^Q7fga5+
zh8mG$xd^PXr6ZdX9h48PuB*rhNGj}0KMq}_!{Cc3*OgDM{qWB>vwvm2+OwAU`hm|?
zK|ZZ1nUl;4@%ZcszGAF`PkANeJ2&OzqMSlVV^flY#50E?XBBClIV~#r6KZYvEp|-P
zgDz=l+?o&VJYnMb)MsUMl<GrrH0Q|=p3B=<LrqE8m=A8pRFrz&<}h-N2<58Dtg3W6
zdI9WRLd8IVrC8x1vQ)@JA28rp2{G4k0@!z&5~>v}P!E7lCg=k&YCu;#NwJ0(;`E0<
zSnJybWF@3rvNI?cxyu8dRk>f4LZXXP4<63PjKQ$UW6a_k4v&+9SqQqDQa0P;ZX<}C
znDugLD`)4yZZvIgoY-raaXO`?pB&8F272A!9K7ThQ%2Dk-3LTzSHa4d=8`q`s9*y{
z1Xn@`lu$o)F!zG&phc*$jC7`CVl6_#P0b?-Zw06vP7n!@o&YuEdLs7Ci8x1&g)m~O
z>!*e*Mo=M6^F(2i3L#rOfeMmp0M0U{!YwqWq<*|b8PSfJLQ$GM5;;y&Yt7n5rPSM0
zdIiHKnlys3dGe~a6n&{@lfospVH=lpjT!1DCJR&ze2P?+$ZDgQsIYqOrcQB=Niu}*
zgh&5oKQGEx`;bZz-7=lq?p4(-W=M?~UU;h!gQ4=Vrt;-0??$CcM3yovM0q*xa>_u)
z)FXHZHOk&(52qaxO>j~bqrN%HY5+Qcs+gT4pMlLZEKLQSEOY>+wue1OT>rU$VXyVM
z%4YTi!3$9bti*yKlrAEp?p9CZovKdEABEE;)c9!8h%iV!WF)N`gtFpF+e+O_dV%fD
zr2d}BNC}28!fD+qyzh%SJ8)fa&0_)2vK0%J1VjKS>OJztYeqaDD4KIfp85{q@L&`j
za106p^1a!JR2niXk@y<PbWKF(V2sj9sN&DQ_j2eijGcH8AZcNEu|Uk>NfyRG%f`s$
zKiM0Ho5QI>n9hW)Euj+07O@H`vFnmhPM%9Y0V_?HS1K^;F_91z&Kd@<wJ%}I069g<
zjHyIFKO~NuackDRw`e_KS;K7Sc)9u!Vhbk<uAD6_rNz^)w|+NFr>jFG9`{~I)1txB
z)v4L!P+FdKra$$TC^k-S`q_6>2{@byw#lzvl2_xV97zp71e-igHVde!4MFTs==%`M
zLJjn9CF?m#tXWsbz@-lI!?QAl?MN?pgJgA@IED5XDE+keB>LBraSR-uo|U&*q}U$L
zA7`gc<EYy=yDk}@7~1oMm84xu)@ds_eRPNnFq84;`bX2bLUMejC~lc}YxjoBgqQj9
zSarM0lpniBXMvF`FD!nWat-yTfIBpsM5ho<t^Te2g6zfFpTiR5yR3FE%l=rmyZjyJ
zkOM}&m>5gGN3tezmDG|>oOvf+ir12``hy0Dj|Zdj4br!bmgeGbC_hT=67rSDZ?U#5
z`dtLu1g{6V2NtYuvF_v$n=}4<XP<o5WJeq+jjt03xMOiwT1yLgg3AnP-=7lellzqC
zGdfHj4)gtW<o3B%bqW1@!eR|9$td$>0KqAe(hc42UFil6Y&%a<sJEe^%@4Bver$g5
zn<xL67_$P~623y(%Yl*8GsB(RpN+l$>-IOTq3QXSe~0-b>&{L2X2{Cod*3^HHCQ`2
zzc_l1B}_Y(4t;H?`1y3}m7iZ@?!dWsJ8VVV3G7^ZM1fcIz)26+Uz-GE(bN|jfk=QL
zs$XDb?nxtp5hwA9C)six?j|`!um+N0&vh49mFI3N=7iQx1i)AC&iL1f7CN~-Z@u_@
zFi<!xhdYI0>~+}IzUmDSmq_lA+_BauVP3PrsF8f*nOgh3-*_h2>fCbewGCQ8*ik5}
z@UG2UACxEG#X40Y`84$ffpF*#6`H1cZ8mxlk*5aIcDMHA#47trV&=CB&@2_0Dat@7
zLYw}0$6W>P_Wg9-u_f)d3P+90;l40DFSmE9cKXcyBu`u-5hh`Vsabp@9eAeuGT!~Q
z)9hPzplw0h@xkdh|D|_VzhMwsM<`yf13&`E33Bdd;V}DqX#{{Odl^Ny%sbRG{6pKo
zH7jEs?7rL5jtgz;9O>s6@8<|#n*)K`844VOtyf<BXu9_D_I+XW(X^RSCs(H-bWP2x
zS8`E4n?569Iy|^cX3NntA{kZ5RmB_Dy!fN9*{=rDm|`b5BG(9GJjUb|QD|)f2cz6E
z?0kSSV({LeW{Qg_LI{OG)FV9BVgmT8d6E*}4{xcQ$azn~%JNg)Ov=IERM%M6rV+t-
z|5D^^H`?IWp-h6Jkw%7{cDkp@O3R-2Ygw}E=F&sP^ye4D$A^eKz4iyc8@&;bpln;<
zcctKT#CL$<F`ok(60?(1>?o0A)KFw7uBl-s$|<aic2tP3mdRUr71P6QVRkVdlvTWF
zyLW_qIRyx=j;@WXzNKAY+b?ojPBRsq=1r=}%KYj111cEN%WIz;TYH)2V`n8v0$U|Y
zG#PP!`7TgI#ET{2ekNjyGwM$*1yG#;J2nqgr6K(g!vc3c31Tv2dG4+XQl=|B-Q(ol
zPt1IMNh2pfn7xb|N7<*&NT#Xvbo$KCKbEHX_R{oPgkn1HwfRoYrs=i&p5C>H*aI3f
ztG=$|LX!%31I_YC>}eZH;6a5Mw}@HGXXik-Xsa9wPeDlSLC)nwTa<G#N`w5pqqp8+
zJuch5_qD!BHu4q;eqRlqm#jw)MmvS*JK#Yl(r=I!6Rd2sld94dRCWC*f9=zMP1l;r
z`TT}jVMx+MaX&Mgh9tI%4VLndmeFFu8Xzn-u2%hzh$0&UhvBjk_vWH%NYO`^Shev|
z-W*;cK2#nI0iI4T`mF^yCS8XpJCO@VNmkO2BPJ<+z;$kEROX2iceKmDdh5~OU_1!6
zv#nggkidT~jxF0vsoC+z7m**{F~h^^EHwfYJVtZk`iR%yDfzuIwu4q00+CXyrJ2Rd
zAS;7We=IN55WsXJRy}Z44m^t-E0|rOWvav}udCY=4XCOeCxstAeQTC?Q%ygqMbr&u
z=pI>ycHW-p@*l*92$B2m2bun%LjFdreZJ=(iB$bVg=Cvl{bLLHd!qL~`P4fT)k)rV
zM3_*2>mXB{`U>kY5y>h|ct8HhuCpag!%OxbH5&3`OP3#`^5(0*^P{q=KYI6*Z#*!B
zAAg4kuN=01^W9CNe)Eqaue!yOJvzoFOTn<hLS#s(ooFGf7?H1_5thgC9fJ);VI12F
zxQXY9TEcI&{ZPfj#nRT#<P+=DSgWTje53`SW|Jgy@i?nCuEtAsyE;_Z8#A|UhKQrB
zi{iZ7I_W)qm-FZ!F+La)k>;uP3I#k*X_^QxT#+wVeq&PrUEJYCIlJoVw$KHqDtYG0
zmH!#()r!$$3_H2aAs~kgr&tz@rTwhs0r_KFg2P1b&5Nm3-}<$8sQn($=E~4k2ezNw
z#gK0VC^LSEgiti_;N=6nU3miW#Gu@p;;U~?Y?gX!5?>nw9cQD$QW=xBU1bK_S&oSF
ziF2fuy4v^PJr2I_<#)m~kOw1*$scJEOlZdrQR6BM9Bvze=L{%XHYY^M*(Yg4b>IO*
zq1s-+URe3cF6+Xy_SQ6ws6u=R0vsxO1YSkT<b=&2BK?P7ekXTPId13AGa#HFMg^)M
zfdDiu@^9UnYM5FToph01`40K4_A45w3L2E#)PaN3h8tQcifN*I?8uX2lMBf{JrQO4
zQO-*>?d7k&hgcQdc3QxR9rl9eD$<5ZB}$|CF}6|hK=CVx-`><t6Si*3IzhXdJ%b?1
z$hiXeNzlylLyP6PIGQ#028k%<=LI$a0V0FNLdv37;R;-NcYa^$!!&c}8*6KZtut4X
z_T})UBw$&NDPr9Y%>0yNXb}-1k>6DQVyZEgCpf#}c6O^Vt%&vMLEL7Is+TNSZ2|;I
z?m6#O=PY8ZmRdN5L#M_*mpoww>G^fX3EVMF7HPA`0S!19RS&9d-pq#ibS`>|CAH$8
zf0yAO+(NO9m#)(m{OrSf!z+dcJrgFBER;m66$t9sy2M^$qJV20{`ADO;l8JwE@nMe
zN&*z5g04<E_xTl<>j>kg1sQ+H#h{*L)|3Qcz<|lB=YvdYBGL)OGlf;vs@k;3d7d?u
z?{W<-ov(rw>GT)PJT>N=PTL{jrngXa#8QRsCBAF<ZP(7(w1WP_H`i#YA_PkE0#wO?
zfk!9d@WFw28W@;hlpzK!&w#C96Lqp(XlGZejd)ZDj7)Oc;slN+{yjaILJ=(sJPfem
z7V+Va+lUn2EAUZ<)xc>L`bA)<#1+FbS18vMv3nll7u_q#(Vo>zP*qeSIz`j$w4Arm
zr@72ROH6YbPu3^3pl5rzlv+dr$$&Z5qxZgp|8{JIJ|p#>Xf?h*elcNQk!wHz3Odrs
z<zRbyB@Y&);(3rQJEzuXLU_yTPg5^%&yq=&=PHLe(nZ@>?ExyMxI%;Ro3G@)2s9nq
zG#uWVGK*DJ=(lY%lsmXIwpXEeV>>U&tl6eZVicm5rgcC)nMQ&KMtbD&G!%o-qL@_x
z3?6xHKA|K#CY#=AZQAf`kx%SAC1{T>88*yRfD^A1&h2>Ap|3n`;2?BZ!Gd90dLGQf
zBV2AGpG-J;%{%UOh4Y@BPwiZnH>Kmq?o}wqbdu(xJobSuRC{6`;9R#-W16(M!iAZM
zIc+2~Nt%B0-@IGdu{@MNwU$2Q4kVJ`KlLAeU|on5jwR?@#U?vNkyilS6wu7UW4v4O
zsG`JEpVf1P`mbvl11aSF|8xy0>^+0JBWwr>MN?7A%X*HI5-mlyY4K(CAX1|ORVt(b
z3bGeP30Rj9Q7$zjhkC*`I7;$*L@!F<DKhfOt0WtV6a&=(IL2;&qg8sdY7Ctenu&Ev
zRf?pPPLksxS{lX39Vuq@&78<AL-ZEnVCP6|#ZYDXASZAShJaKGB{QmSpS->{K|Y9E
zW)o4Df2t2KQu@BaavGrs0pk$@5g%1XxCCBG`9LVE&CCOPETt1<(<1LF+qY93I?g6;
zG@`!hpl)`@veR6f(tIT#z&3lWCpKy0K6Rn8bbDL<;{zHTGkW<z(umfl>h$+C(i!#$
z3`S1jj_Mm+6mgn50B68IYGtP}5x|K=l+w0@0Lc8->32-4n(^>)E!<-k<r{G`ZaMqn
z9abw24o<fC7?$$8Q+a^}=Qe1MmrOr2l^#!~*mf*!ZGGO(wZw#{A9tn%8-&NAm=MDL
z-PlT($h+Z5DOfd|CiC9BH#DS8KQ)_bWoM#SPohL0^4itYi9O+^p9iP?d?zW=Y3Gw9
zS~EYF&cR3KGUm_h`;aYzCE{w7spV^X!ttWpsj3VRqcLk}$$!`>wA^MgmGm9GD)osu
zM@}g!ftrq{^GVve?fKO4NCsm);l+?NmmD2R&rbLDpH5re&w3O2>9c8rJqMYsIN^bx
znVwDZ@#1vc>!iAPUX4VaUQVZONyew0XW}qvGbq_>J#Binkl4`MF4}MX!LLPR7L$>?
znuTOw6}R)p<O|!MxCYC6@yWtNXT7JoTOC)#?Op{5kya@IE%Lku@mS?@@5ywUp_K8o
zHI%ji$?~P=3E$#UFMTMEiF%3Y7iulpDQ&Bh^UCUPwwsAW(k{++Qx@O_i{p61pP&a3
z)kTNaik|hxqqpKPw!3|tM%mXrTf3v%vpXYq6pzUh<E(mROKJIfdX*puqL+^5)M)0h
z1a0WE>C@p!Zz?Tc^hgAkvh#UTp1<qs>G{sqD^sth`QsvaB7N4oGDTz)!O~k<<n`OB
z_m|zV@KS%S<!yMV&9*+GdS0@G;H;%E4oKG8BsKhbFd=o}{7c2F&a6s-h-dx`S$@N@
zwOs4z?B77HxwLrwwP}=Sr#q4WEk#MVO}7@Ym5u$JMFeO(s&-ES4I<>~acD04WI+`A
z+$-sobe@gbj-r*ltpuI0uyJa8e(S2_ax(Yp?9|dlbQ6JKY1upJJ)V}!dV3mR$R-5q
zHm!YkG3T|rqXZdzU^VJ=^>l`8OsgQ4C3;KPj!Eg$rqbX^@7wt<bCl2+O|v^yHNLaI
z2}Uhg0WXFLYCy<UF?Z-=D06{F?ujHR=8n!!3j$tJg1iV-O3TxLEM5|SH_ev`L4Gp1
zV5MSm9!!Avv1-a1%^wqK6?0{=3hu0m<^~zt+vx*+@qF+ARHow!M__wT&#>L2NnT+9
z?f0hQv;Q=j9RqKm{{WKm*AC1(K*~&(aE9av1;xtn8Wm1ef{h9}@EB`Oq)#(kKRqY3
zr-jbtpUJoHP80Ij9q&$drN?QaC*xewbudl5cIp8yuz-868@(yEuClqSEi@ST4HnoY
z1Qd}2ZMOA|Je19)J{P9bu>03j@Ba}B=uv2gVRz~lLrF#+3sONli2l&prSdBO&>EUI
z(G_5JoHn^XjU)3r>HM5onV$nP)qg9UA|;^3#xLSC^Qjl5^LITN&(dO(j2zRXFiz2i
z#fdyf%`F%`OaW|lXkgYOw{HXB5VPH*^Qo{6Z<_t<X~yaFaN|}jB-+STlIP~ok6?~8
zE<heogKBdXj#Spe(K=eq&$n-z^t`-eA3f4T&RO<+nN5qz`qUdVDo9W=o0d&4oxhv-
zxMH`;@tG-Wm{e5T=6oinedZRJPB>-ze%1-h-ES(`vVBmCq=*M705juy+8gCU>V>$4
z4@~Cl)xcPvq9ut!oFr~b?KHC-1r}hQDQE}??@v+zw0qP`#?zzo=~gDhGK>hwt9>^z
zLvv2&cBP+zpkgi|hA@3Pp(PbsG+*8d1;XPh@^yYb^~Cg)C-j71I$AZb=l_pGs#Z@s
z?cj<4D~o0WZc90xw8a-c!M-o;Zsh`Xy3Nal&KBUhAm8t@4BUUrT9Q6EmUcNlsY0W)
z@+!8nN|K{YUC$$1?1eI@sr9l170sU1$`{h)S#K^T`NR}LwJtw#B~3kj`uVwc(+zJu
zFQ3+@^Y)dLmd>{aHP7R5&1k+cT8f{a>xigxKpSJjomA>A556bm>wk^hE4K(6fK^Yk
zSO{9bj8WIt*jg+L%oXe+42h$$@CmOt?bEf-FMnGh;|}9@!K+~ZC}1f!#$=c#8Fs}G
z)=RohmU8IYes?v(J2oH_M+!1H2|c=gHP}laBc`T>C3}7uSz`BaYzhq!Ey4<)0$1aR
zfPye8WxC-YVG7f_e4LzsLqy%7(%CYc6l9EAph*(jU}Ya2n_v&gdR2`Cd)i)>sgcrz
z?Zo+aUaAl0Q;pZ}{qej1hu}p2E{kaTJ^ra|dv8nImjxq%`TRK9-v3~nXw!G|iE4t(
z0E;C*J<KhspMw|>Egi6B3YieAFu`nm`vim2Dke@m>ku!(IDq*TdAGEaX_3sWyv&(u
zH6>SaX_T`G6~>)GXw>!Gp-!|-@BJS!)JJtxR3W+L_sW$1|8RWkVZ5raf~XQ1lOYHA
zy^3BbC_Ez*k>Dw%)ValrNU@67=RHf326_lCfSpH$E7Ow&AxM=VnvpIh@pfZx&M69P
z($(A^<MNmB2d;hUSCsLtEPnM*9S*^P0;65#B2_Vafyc#rlX)anlUx+(;8t3ST&8)Y
zo+&MHfZX`Y`y#rqM|hFzOr`kr6l<$8=wznY^sm<X-b&4~Ic?Q_DG%3#1EM*6n?QyH
zOB)~s#h;a*@-%F`jIq><Bf=O5<>QKWm5-JOnm6QX+6T9)Y=#oo0!S^_MFRQ>J-#Ef
z{2|t-kQ_+^-32!gofUl6Bq?7$KCMYdX#Kbk6pk&<UI<=f=A|a%RNAW`r%XEd-1*R(
za&>dc&HIP}r1s>)aSyZxN1&*mfvMUnQk8)Dyj&TaLvbQ38)AaU7Iwo(0}<dk>1-Eu
zk3QvlpkKmfHEoxBzib0ZRMHq0rxX<BCiKKk20hIiv~~4awUDd+F-d_(ZGN%!F0MPV
z4z$e~v|@q0pYSS6d&mvt_oRbl@1N+n=e=>e5qt42?+I!QgB<RW{dcMLl~cMqWM6=V
zri{ttKZuVLgCpSZ*id1o&Ya_!+F>zKqRuiuz6Ss`XCE<BM^1{w%e7;zVZQ&b-=(nl
zkZlNZJW*|tJyl4%z3O+E`;2c7hb*h@o5iC^(%qblZM~fU<FT=df?p7EshyGvWmHsY
zt-OXamXEzsnky3-jFA*2rdle8ka4k{11odrfOzF17PF4_^89M8f@#NrqvmI9iZ>H+
zV{j+=n$(W8_FXD+M+q%Xwtb7bHdQa`ar9t^W?qp!90uFKX@tix+o#7l1av(5!mY|v
zr3jcGPgU7{<3woBRv}3B#W>FHR>57!I0xUW%>4MyC$i_*X1=YsP9O299WALwp-3w4
z-3CswWBuCCzYc*KaVT00fXdQDwUxah10NTkd^CsKm8^K;+|46-%!+DIZ`BtWH7lJc
z`xs`gK#47d!k8Iy;Y-`e`S|yQ)DSjcuK{mVRNHw~4+@qd+seg86tm7NS#l<A2&T(r
zuB^l5k#s;rGqtFs5(Fbc&)hddsWdIug2<`{Rh;FpbD7feR5#|=j&HF^vw-ZYW;w;c
zYj=lWCaPWNOS+&_J4|qSGO<%PgI_2gk9!SHcH!F2x1!acCei9J<}st-oPE{2R9-#f
ze~dex^_8i4`caZ5Q~hZbA9N{|Qc)AD;0maaQZ*k{Px-_V<v<$p%fF}j6y2hY;&$h~
z%bVV#;T!ts7l*(PKU(c;;IE)S7y^w^fK!%LvtT!WGy~04odkP!XXQDK1U;Yvbzlna
z4d<p68UTkpkTyPQ05HT#L<aalJMp~a+SRfW4OoC4ggx|zjEfODLsJ7@D<(lGN=F?^
zlC;>)r_1luSDqT4in_W~Av0iGs)<&PC;v?@GAgH4{Lb<>iWa21WnlXQm$DXIeJ^bS
z;!dQBMHy>|oRTzK)mlnzJ&E{Q{i$}>T4k9BA!m;hm`4Yr4`HkjG4}o~xy{^_-G4_&
zyC^x;_Ns5Zj2;sQgiTzusEV_<T+5=~b~ta^9^viGdeB*x>Ga?SC1hHcaR5FV5ZkBQ
zZ~bo<`LsD~7t}C=A0Mfv0T3LWMaDVBp*X-m3R{2-K}XRPP{N^T$&Ty_HQZ!Jl=rQo
zbR@2ZmKN^ZMtd|y2g4ya(2OzTRh6=uX=Ow6yYeMZ38$BYo|07nK8@}Kqe$47v6n(s
z3xOJ`ce-jme%q24q)MTHbBPxv^G@{Eli$}a%h~G0+3+d0SE<Zb_kib+cwjOnpmGnf
zDd&N-WXJSl;N>-vk<3oLsiAo+OoaWo#cm`OYspHai8%lVhpegISZCg#wLP?!PERaY
zEc#RMEtsek;ZI>C*b{P&)pv%EQdJU0$Y+j-({d`r)2Hm@LVWCYkU@De9NJ;|HP4-F
zPO=ep<a7!?X>H=&2PM73ujOm=h22Bm;T@je(j!N2#m}YjcTzEwCKDce+#k1&ThpXE
zNT;Z=)Wm5yaT<&w>5ua=Iv86v0YHi`4Ex3WDa~F5n~iaTY(jcEmQ*sDIz~~>CTZE7
z^+xf=r=S1Yt&w{*G1Ja^ITgD`oIyFRiZCFxeP*uPai?^gJf)oyo-L4~3c<-M2uDLf
zsMKR+K$<kmL1so52-+z&5}@l?Q;|I^JHW8QCKL{xJIdK~UUfe^z0Ro>zre>hBC~OF
zXigNpd9|xXa@(7Cz6z>Y9>=2-%CD2gr_{C)9%z^_HmL1WwQa=mEG|N%>@>DMMSk=H
zTZi+kl)}Y*E}ow*949B$bl%;Omd~2(?>mX}_lvDPDeFNj>v0x!&7OQB^}rX@Mz+(b
z^QyY%aj!L>T9cnx^4PO{zPwphI<N?X0QUve<2TB0PNjc&uu$xscRw*Ko=N+S3!`ce
zWq*gXJ~JzUx#qfC?ArR&uP5T?{;lTwSrraY1>aXIVd#F)_fb~wbj=g#aV+)^ow>U>
zOP=_lp;$YPzY28(-w=26eS}d1_;{LT=mxxr=DR=h&#2vJa+kqwPOBAm(|Pl;G++66
zic5`zl=b9kba7dDa2%Z}gzc6nMxhU*b3bE)!L%+E9S1<E*#ArkuwoigfzP~8%6HiW
zU%)&UQdKlcwmdGRv%Z>21vC+qG8=@7&uRx)oJX(-1%H4rKmpG48%Qc-g!$rg=}=0~
zU@6R#`2NHou_6vKyCAdc^%O@Ndl$bS@Ka|%Za2M19zC4SFM&23+`1YaKFwwzxiDm-
zjBu1qBvMvj5*T&up|8Qu$2}RA$;y>i%b--~5&9Nk$Z$NH1&D{vbSrkw-A!Bp004rL
z;Ak^kDYPle|F!i4+|Bn4lhf&3x1~@fTz)2Drt=cashedmH)#Zj#B}tu(W82J&?688
zDDKQh?fDcMAy?6Oa;c%9x<l^V$tU7#|M@Nevd4$off@&L?K%^i%yXK@7{y0v`UCuK
z)wMfO9mlfPP5Ga8eFr{`Llu;&pp}y#P+`6d4yc`{YAsd;#y}A5IW!*{5&Ig1K3Zd^
zhMlaj879_3O3`6s6~O=r%YW(@?U?5Da-+I7Y7mR9V0+VI?_H!$I~G$;mQ7zZ9$W3c
z1=fs{khP$uk)cZonI~zz3N@waAX3|lQ2}^>5{^J)7~p(6@z!dGgiec%dU>|zEjnH+
zK{JDwT)*o81{cc_5qR*Hb^u)C7grO`^c{(c$#SP5Xd-g!*fR>e+(iO8^&pT8q$5?M
z-tlxQ4~ClhK!NH__BR2>myh}5F(@}=P6wmWkP&bWPfkA*Xys0TtVhp`snvUgJhhBA
zYB;g4zx?Ny<Jfh<qftX~u24Lq;--k=A+k=6u`m!*y3K0E{51yGT`4HS<Y^2AU<7P{
zF&>`~wF7a4=7P0=Q9weQ<o?>ULKzhL!qSF0p&gQ|M%^<aW^J0@{<g1i#pnPFzzD2s
zzod%5B>L75R!PPmsg^J*IHkm_{0U#pGmlaKMg?>b8S2exl~@QBPQ-v)PT0!;=K`d6
z$g(dCF-4RkuNNxzG)>RS4XQP)5}QYJOy|!zQ(>&Sm<m&h78p=HPl96E-o-zCr(`s^
z3B%|#Qoq489B_@n`zaSAAg4tKEl<*Orl>!|{FoZ=C1xn6Ot2T!{>>mK9-ZeA2*uG@
z2Y+7yUd%D(UJ|WE+;hJ0JOAnb|FvYxsj)s3tKA8neq%xHO0c}E0RO*0icA$#(>b$}
zr0c^g`L#au_vY97+lBnMuWI|rrExxM;O~&EC(AaUB1UQSdipzdj=2xO5{;=Y{Lz#A
z#p)*)D;!3~EggWOk*s{;n=C|x@cTqFlPFeWsTcFlWNT&eI>USQi({?RRT%vh^p^c<
z_GB)58_kWg0bg0_>#l$Ohg?#jrO7>|uKv;Swj^8GcdDJ=e*E}y<$WnhP{*}Td@%Z)
zqg6fjT}wz~Q(+C6#42|Udv)0HF*LhCVwhmh<c81>)SA}OJdB>5aq3&?K^%8-mZaKX
zCA5NriKbn4bYeb)=#nTIKV9S7z#*FL2-a0q#K81Z`&jQJME3{()#_2@V8s>DJ@4Sc
zM|eqID49R=5&Ouna~>2%ajZjaq-U12haG;Ll@?y8LK~$r{s}t5O(s~u)@@9B6<wK`
zxA;vco@qf>W4DEKU&ND9B&l^NS?zsI3-)$=5gAlJj&WWz(vmMv@y3-~1uM0@sz-1R
zI}C()EOf58Dkmr%jKBncs(NY~GmHxJiQ*3FvJ;~sNc!9I^4hhNdnzvBMRrn8Dx{jO
zQoN=tVghD{Jbd=cNv<^GwcH$ekM`oxX=F;CPJ}TE#+626`C%4q+!`h9UytM5V(uIR
z*wNaS2(^fW>oJq#EO13{P^{ML<m`MuLm6uzc7B5FX4w(&8f&r5GYGiHl|~WKqCwY;
zj~ihH@Imr<DhFwfk{87nRkT7W*lbg1)(}Oo{WFPT*yIJ~s265!H`cn`ME7hm7s|+|
zr7A;y1#>2dS@~dkhKQ$<S;r$0KdagOPKYn$R^#gB)R)F+I4`l-m*feV%6Zeq58I0!
z>f)SB>A6)!D6kZ%gm{uL*C(JtuJRBoB`5B7LqE;gUhKX3**^zOfE*iiq)@SjEHEbz
z&Pd`DFkhqYFdY;VWa)}4I?44#ug;8%Zm+T@%sJVy)89*DeY)X`1n=KfjA6W{!AJ~e
z(eHqUK=TMxGmckJD19%?1_32DNMX)wJ5_V&+7th);u%NmR|<<<f>iT#b*NX{G<c2Z
z1W-w(me0UyCDrO!_V6fUZ=lcyB_NT))hbZ)mH%@!63quZTv|nKcq#3i2B?RLPzm)|
z$~cyNY{8ECnAenR<)A*2J=3v1ufa}V&8-t(Cp=7%TnmP%M@9gltb_s@RQ87YMq?)8
z@@H{Cw2EaKf`*TI4>j3;X7CeWA;@TM4zh}Pz7uZdPII%XSgrV?&SwX)1-ys<)G5j-
zx1W#Xis8|hpJDB*T7DEP^MN{fDwG5{W1nsvgn}}us^K%>xs+xXh%l)Pl3=UAWjsc?
zwSL8*&s9Q$RWT`5Vl`KR()TX2HazhkA{<ezFRwxD#yv{480dpI=TJa|``2Z3G-(@b
z@8iXayD{IoQ7&*;qN2j6WW`Wj0w!dKx}C2LZq}K3$@Qy_!ntd|_L5Dr^8MaGdy3j|
zcvcN1m8<A2o+AU<QDxZNz&g@h3GesD!mSvssxSf{-Q5LPt9*1-Bj^Y!d6X>`0)fT8
zpff0e)WXMJ%0N8sU#=r>{_6+#{oMnyv*U|XtEiGXR8NO!o~`wwdX~RbUjZa@%30xn
z`bHfU-Tl#k1Nz4^JQ^euSxx)iJ*#O}zN}b|iZgM2M0~S^W6B`Q6rb#7)<>G0(d<Dm
zBATgEFsjhiwGZZ?HMwOt9~pixA;twGP-h$h-qaaYRv5yhF2jCvs;*5U?=ZH@8Sh4E
z_XvDVE+Mf4@}8Yz7Pnj6?wI+CSTr%{|L)08F-E~;MbB`aOd(oKRJdlc?g2_~=fQvL
z9JL6{uhbYA)j|B0(xaJBAU1HaV!$rNHlo3(hl^+sY#kMhD5si@2+XYOaDt1gN`jPi
zxLktcZuUuBA86VyKLziCplYj$)9#-#%eq!+xElg4-sX`;0W5uwgwgc3iuF-vmIiQZ
zr+hI;{dOMA6NahA&L5wSS8f+AefTYT)HXuOf7^MMyt%crJ`}Iq&*BuQ+xhMHWL2St
zCyB{}6A(JgjsNv;X$ozx^OM)AZ!5y3teYi#_)W!W$vC0O8IPiwoLru?r0MXwxjs$|
z&3+ETe)K(2Wt^~jVjV5u;}a<BTLto?L~{(B3u@3(_H*{VV(qnkU(Vv}2t?2-uXfKt
z$1CETDs${DDS3!ug;MK<pLR&KVdpkE42nE(=Mv&w2|X8hh|@E_=`d^lwtHLLyTpkI
zA}W8H6@1NP2R)j4rR3LBs{6^$+`>~-r$7`H4|wusbuU6ntQyQzU!V6G#igNmqpqgd
zSV_H&lE|c<MeQrRqLlc@-z$xwUAyN=?pZ$gxN<Cab-*3<nF66fO4R__p`P-#V_A-W
z{Kd8Z{b5b*drtX`E-EY;<701vO^WCmS^)jbGEw=QHY5;dK*&Nt7S!ZJOwD2*E|gB`
zyWso1IjvgdCfZuYn&cLIbgk=x&*%{Zq?i5Ubv&3;S()lT$4wdIZLF5ODuWIN!EGsJ
zY-9qg!l2+w7IUWVv2#p9LCQW}`C1XD4rsadH~;rz&h<w1y~1w<&D!DMl5mY}sT}@z
zYe^30r{eDCt*RBi(VZObp6#{F?hXDwJF;@am0;;;?fRnJ==+aJw#)i@N+t*lf%rI4
zPK7%h@29%ACQkQrgEPZFB{ucUIKtf_KXTCBIrjS7A3{jifB!AH4Ss)9Y^ZtJGhUxr
zUD5Xn29ZE)L6_#Y18|!sn7*?0e{w&~;xC_^3y>@FJt8-`DUs8}=C_?(zO(wHbI*3W
zIzn1P@T#t_Zd6GjS4u73JomwE?{sS?8^Olf@QmNZ4ib;cuP({1rIsZpNW|KTFUHP9
z_dauIWA%R)2V%cb=&xOBY+39#hF|yB-n_UnL>TOX<^8lZXmyw3519Y>YyZT&)Z6Is
zZW8eu{${yx@s)6>HI|QG%C8V{syi$9SN)BH4bSygNVrkIqVx;+uw{XDm|MG(yG8$8
zt^ZQPovHQTsQEjCBf+-=<0FAF5(M=i$i!%~aJ=<mU{LI81bsoh(F|PmeYMJq;OJu;
z+6}Jy@k@j5owZH=C4a`>f4J6gdz(QJRE*_IZDAf3$rU#_>mNpEH_P%;=~AiQ^nXVl
z3nmNJgJUn$!x12}J*<Uz`TMJbz%+|aOiX<7DYN+0ZN1N#jrF5v8|VBh{<*+^t;C+R
z12=sC-e9=d+!jDFBxmC|Cf|C9E?pGjl;}--ec%4^1N-Z)TU|L6{cX_;Ifum+F(@{b
z&Xj1T1I?YyBf**A-eBJVo9-1TPgN2NP>hSx1u<~Wzb<@#lRp?d+SuKAq*mKq+jO=5
z^p4TRMLEfiDI~1llTN<%Z~w3&=_9#f&MU^OX`JisIn^kgYLw-bT0Pi*wpMT48*FQi
zx^*#92#laQqVxx*Iq89+NhE_pbDYX<-|4GyIv81|LowUw9T)xqai+9M%$52N3wR6*
zHZ?oJ7|GXFy_k4R<}wBx?4N0DD%}vghzkdTkSl|o?iT;?nw$*R6|AwsgUj^(+55U?
zfcPC`!XwJI*n8bHH#XJ_{z{wN>kZ_>e64n*w!690tp}Ujf?235q8O@qoQ_9qo>Khb
z4pDk7Fn8BD*(CR|scM&rkqzxvgnt26U-w1t$9zg1zF4}^^ar53)^r1ZBv1?=QI$|N
z9T*pVbMEM%zro#D+vbm4F9l(9W8gj%h<XseFg6wxjCj&|EBF$`6WOsWDRXA=7Y8AK
zpmg+1jofs|#ih~_|I@*ypxNBy)*I?6P<69i{fjg|vh8VoyWRccjjkSS4kbwHg0>J|
zX<Q75vyFQi8ycIMb7JFx-XAdkv7^@C3BqBc3yI6xj`Xj(a0ia~*J%y+qPTM4itld`
zBNyGp+M}HtW8vfxHgDVY(hKXx>JtCpi!Z%r<Wi7%2N(cNCv-OnW5B4@Yx}p<s<nD)
zxZbE00!YnTHPSWB>C;75y)?4Bw!eO0|C&C|D4EY1-PU`}h7h%eXo&qskWc@ipwI}Y
zJsD>dfizQPP=uv9UmObV2}X{%jix(%B>32l(FezZg<xczRah4Su|EEsGBPnPiOK$`
z>Zn`%nrKpzyFT#O2M{<MG-=Z1W+k5CurSAkaC;k~xy|2SZ}K}*ul4yzE{x>awhnW|
zobWHZS6s!OQnR+LHnyd)EqJ)OzS;M&+F?H{aaX`lrsK^GirzDBZ%Nz`eqTM<>63Wu
zK=5!-+v4~2kOF$L&TmkKjqm&JYV5{rxN~|J{N7hZp!e+#?yK$F*$fW*<Bi_BV0~>c
zQpiSV`k4C)9oQ7(4J4}GtkTCI5-L#)Fo}7&Q;q%^e;^4iih3g$QyOZ~?=#KuhDKLK
z?3KhPiS7*)F8CY8z-!{FSPV*wwUOP8YSWo@Dpp9xs8;dkHZ|5_K`9%`iYB^~KM^yH
zflC4w2Ej+_2OePz>AT=7MVdVuq)6W=`YtMV_QB>p#mYv7K9o_n{M<yRTMR5VHu?i!
z6C0aj7w8+!M}qB_#3jg}rI!nX!bI=7C}w;r(|^(DveHPc?myx~z@>vmbs=7;j#z8E
z@;`H*wz*KG=UZ$}Z<c58+Hl*3?hVd?v;IAe(I1FlIJi`6HXo^tqB};9_%!Kq*P!9i
zoo3d1l*$?pAQo-4yW!B593x6Fqd5UO%n)(PKXlIT)M|~=uz%!0-QPyD`%Sm$XICmI
z!JSf<_L~>zT`V>3G)gy0?zTpAe{jR!@jLDgpFyG?E{+8C#VQ@><yYUs0@~Sb_T0#k
zoM7v$^K+&%bYQNzsdUbN&A$=2P+dFA#^bfZg`kRTp_5b_XG;Yg^y~#ux*+;41>>da
zh`GBNxNaBitAqt=?2PgOhBkjkWAv)~?S^|r94XO!7n@Dh5r*lRY{1N=nj*YRQF`r)
zd(J=CxFKp{y;5g~Yt5i{%jn31FO7sjJ(T!wZ|(j*o>azgCMU}AocW6Q#l~E-vB~|i
zxD*@~m;AcuuZ!*VQa?h=u|l;CcDND#!0bVBpZl=COH{^7PM^tnYKDX>9x6%%gVn%|
zhQFb?p|-)@RJs^kDAisoHQkM9rc18mhAJaYR&GSUEW-&m>^<jSb=}1SBQvFuy1U=J
zB<k)|eQcq+Fj82D%9540zPfE!FtVkf2IZVpj-N8UJItQ5=H25v#14wS0{tlI4_yjo
zg1#>YTWChmiV=pl6|VQ`{o}&xW1R5E8h+sP8GYlz#q;Cf5?ctgS6?#6m~*8hjx-K1
z(q64yI&h;F?0YzP=!lQrGH!NdE*87Q#?0~<ZMf^{(2q85lxiD;?e*q1`E~bL^XtJ2
zdjd&j!LCB6hUFtiyJiaXM;6ZM#fjN&sK4U8;19@iKAY7ChuxkVwb~>8PL~mtAyo;3
z5_d>rXs+;`-Usiu55k>bchI+6z(_^=icUz9Q^Gme|24n=)BYy0#oZ~+xpn&I$j1Vu
z;<iv2N7hVUSy>eBz|n8JuZaWhCjYQ|!^NhMmk!iRkIF4Ut-08>CwQSg7K|v;t+(#p
zv?~}pS;*`*(`(-)iqDBR8RkA$-3Xs|G<va!^wGlEV6paL6w5aCC`Jclg7I0{zR%<O
z62*S9R*jPdj#_bKwnAA9ivFXYMg-6KXWY@`C~Yq``Wuz<c>86j<qK%X#)e=6L+PBm
zeRt_Yg-c?lHnr%>>d2l}*Sf-5Cbs|M*O*gR24*qWHrbB)``B@_`_}jE;0ZT;@h@xD
z67_66;@{_gIQTF<gwaIFFwa8DA<`Z2c^zo@BS%VgG%EvMvx;6<by~I%ZYmac;9R3q
zJ9Msby-_M(cT4L_4>xPqgJ4HM%8Dl4bGcuvTwXFyG5RQb$yIlVo&NQbcxbmf@`GCN
zXn_5@V})_c5BbWM*F<PWCGJ^0?jE!@IloM2RVwDXs0Dqmsm{6>)MjcsZuY{gAF66J
z#4Ct129dIhAbTHLhRXQ6vpVpE<qnwX8PV4e16SQ2G-yc-B;np$`mor(1z{dN=R+5U
zOLo_aHdv`n<pN&!Cikj)#=WzIN@(og-MlY&r1q#>40{7|u2cd*0{On(YpeGahHqA6
zC{yz5ojV%q*KcSZYP#h@y%cVr2_9{p3$_Hkm}BZ$S+7;~7({#1@KnMPUA6JjK9pt2
zsiILiRFlmKQTEXx>)k{5K>e46xKV2KG0<;wcQzrux}(NmfHW?5rA$RJ#L*NkT59x2
z<E$9O`WY{+cSi<mk2a6&xWc8GhQfNm>5YH$OS^*m$XK4U$Z}C6Kge_9Rk7fgE;9ID
z5?6fL5SxM{wQswfU|^=!h0;_7KpU2+z8(if_=C#Gqw6{WOxoX5Q<|00QeDHb3kA4=
zPJ2~!#6YGmKjweTKTErQXwg@yQi<J4*TuV6v@7G}PQQGyp~lwr&Gqg>SDTlvT$;bM
zRF?}Q79^}i+yAGRwC#>s2Y{k=i0*rpPV4ugaAw5%#`Z=7FKKsk`?;F3QG1|=?Y`-<
z_%DKipItB*qtu{KKQIE-Sbdo_Kn2xB<pkM*ccT9X#Cv?Z^zG6Q8V3$tFE#GNCHk-u
z=%9A5ves2S6+7@_<}#r?xZb6<?isO3d|RpPecRj*ovT4b=ScW~q-iBr$MF|SYpct~
z0sAY(bGHrkqH)$c<C|Q!(_DYxKDTtKQTI0mm;5G<K{FVpx2ZvKr623=F41RFgRi-a
zhFK@x-xDxiDHWboLDR|&<Z2^yTo>X_@h=<egKf3@kO36&PWMLOI}a%n8xN8)HRNni
zl=MyFuz!~B+gN{KTW#cOt?sHzYY)5Y-MAL4Q{}6Dl2MwU{c<H>jX1%)_)X43jydSB
z$415}=+$c<^N;uqw<a?FAZ@S|<I^?~mCeEx)zWy$WqjHtG$l~WomKbR3_JZFgWSe?
zF?yi6gF)5DY4nc<i(r^P9*MD!#;KY;i0qZN1a5Er0AAmE*@y3)U%m`z_<KKdYp@Ja
z?LsBHT{>2j*pH9h*P}za8m1wOnnMLL>QrH4-<px0o`RWm(q$cD<Fe49#s$`ZUk_YN
z(Y_uO4*e65>1Gijtuc<xAhi9vMc;0Jaeuhxg$I`=L#vMSx+j&_#$Cqu<p*kRr9p9e
zdE6g)t%28M?AN!^CmFw1TCQUHI=+$PZZ~@hJ@rzB5k<8;M}>h>jWOea>h!g~dJS;@
zCd5uPTvv1Z3iZZ*e;h+_<U!e|8f~l|E(CEb<>c%8R@2!exR<VVG4SfjbQ{_2R{Tuy
zRBrZe<r0}XHF7w=zwV-$>S!kXw@d~hME4yk;V@P=_H}X6<s@8HMA}fO1auGwpzb@|
z+oPOA9<&Ftk)Sk=zqe1#3MmlLg=)v?_k$TfX!hy*2N|+7*qgNuQv-1Jyx_AMXZMf0
zeafz7^v#}xD-RJ|((t-`eOKub-_87|n>Y7iSoDrJf(lLsgB)B5<6toeB=dle{be>?
z5doKS)rOkm>_UMZz#*xPyYvh!IpsBRz}Jf2r$aj~WW5REfw-t+Sw;XJHJZzHT#W7!
zMP*&=gK91Fw^aeoE*ku>ue(*(Rs0^Wy^;M_+K>KJ3B$KO`j)zo12Tk0g+}U)ZNB4T
z3OP!4xRT#x3F=aQ%m6}C-G9VYgzh(Y<8uA&i&P697Raus*Lc_g&hKq5`>V=u=`wW(
zTiAKl9S`<B;_n|1M((KXhBu3_2XOP3{v(|Pa)7JN#DI?suFVlxINsd9TZxz&MV7lR
zqU1p+)k9{20D)Blj3Nl#NLjWX>5oB)t0dP60$Lk_;ex0JRhlxZHdDkpJnId50@|}@
zcku81Ul`jJO3qGNY+d@mTEsj%u(b@)yw4po`hwl1zEZFTd0Cc*F4N>@Hd`8lN_=HZ
z$^CwfM`Tsu?n<J&C0`#|Y>f2m7W?rlfk;-mC8|K{qxGEiZnLZBFzy!iWpPiU_V9><
z1u3;hCst`yg?f8h{}vO2yNpXL#$ldc?duuD)6Udy_OM9D=^Ui(++n24ae@&ay+J4c
zQ7i63^Hg-FS#7E=6pZM*XvvDAhI_U1zLFrMI{*>#L46+h!sm7`F0fPI<X8|ezxkDI
z?;hDwpx$jW(#zc@&`+1{Amn(hef7r1V5EmOpoJ>gSZp(&PTdBSg}O^rU3E>++^^(J
z$qmB1%w4cC8gf@{KZEDU?gMU<lZxyW)zn29sz(l(x;nET1@^TU_FPf*esC=AGA1#p
zzcv4kE;VO`n6ZbkU<zgg1yV7C!g!;i8bb+&I_SE}{TF>bctyLL`;>g3L^2+58tp@$
z;$b*q2SyZ|-KwLe3NqF0!KPP40eUw2?k;~9y3nOQU+a5dE?AV44=z>ZNWQY<z5mbF
zD9NFlTWB-~G3^U31pz3)#vtI4s<l?6hsLL)HUrvGRlec$Ejw5lv6*OeF$V01t-BBG
zul4u{J5_<d>VgVzmkCAsD}Mbz-|pHYLEkUPN%O(6UCP%OskZ<y^P7eYZ8)d29vOUN
z7qrj!rNPxByGy->YKO|oAQ0(lP;%W0gUvpeGg5D&6qE|eezQkLx<L79eLBNI^^ss?
zO>Z4UW<^CKM6k~7rOv1i`Ww<d^5C7HTepr0(8+qRK)-r@TJI`k(>J0`V*p_Eprb~{
z5A3@SBXz&2@DbW;nLW^>`qwu9L*woUzc64o^m0BUMjO!G3Ig8;fa#8Gsf}DZ5G;=_
zP|Ov;fEre{vmTm`_)2wbN3uE(%Uz2jRy};79xPU4g-`$Vuc-F2B5YzOsf!J2fEVlC
z%|W&AaLq@U`%I$(S#(3z_6h~hp?SJYgAuxBnrnEBqKLRc{j!jC(K{|iJAoS&8t#r7
zeS04ibEsy+_l)#jd@rslh#L)eBsk))Vce`=*uST-P>toJu^3BDe)dsJ@~VRFhzW%0
z+GXKyX;!P-+z~wJ5n#){12@|S!Z^B6&vy#vPT`grfe>NeH&+}(P1`G+$FS;mfFn4=
zGqqmxtnU^sibbEs<A8eBx-yXKrNe@Ly;0OI2II|#Rfl{y*#ED0>>2&~;tLOk0qwZ>
zf^uT_q??j=Rh0*e{|)mt`X+vjs@FhaFnA=`hb4!{P^ZYu(okAvg?n8{y@pI3Kv!fv
zu@8qLs|!?kK(C(D>z@@^%t}|3D5SX`)ZeAc)39^^by-_z1Ms)+qBz$$z+Aw-kx%14
z)q;1^znFV?aB-x*NYc1C-n8>w<R4Pgh!!!>PWN2kM8Ub>LJ&NJ&Z-5Y1z~76B@S`J
zO2>cE?-kWy)j9ig)wU}`Mq8Y~#=tl@bPw=y6H5f(L!Dbb-^NN3?knQU{#Doim|Jf)
zH{!pqcl(yY$$!m8jcH{Wd&z&X`(4%Qc6w#x(0`2$0Yj#!nTN5j_KUjT_y2PBKEQEY
z_nqf(G=b@uNucor%jL2Z^qbc`ga6V9%doh&Hs<k7V+amF7@k7$6rL<JdxjECi3)<{
zx?DLMGaksYLq`%qYrS{7XA*>XUSCqO5r+A5mx>4tWnES|$yl7qx0NePFv8@LOGTlz
zT5jD|<vzbRL)%FM1SL+R`}Obr{(gUdI)i5JO_fqyxkEGYKCyRbD_8(gz?$&~m#kQX
za_%e`OQ+L|(T)O{%Vb~@AG&16Ltjoqs1YjAgM8vGHLgNDbbQ`ym=Qfk-eMl#;Z&Pz
zp9DO10Ly2d{aK_CC6;(4jaI-%@B^$@Xm`Nf&ue=K2kFOJTy)htD$QjtEAKRFQ@l4^
zZKpdrnqDcqgS1)?vaLJD=F4Y-(rS1*b=-RRP92Hwm&ifs{^Y<a*aj+S&ccHKb!zIR
z*tRfMcycmu^zL7M7LBc?t*?I%B%df4olWtGy3~W_76ZfQ9VMC2m}jT*`IpRmP(zU#
z7`_vB!4<f#i7c=<u=G-R!Rkz1`$)9Y(1Z|Pkkq+AXTxMIg?3x0J-Y7yY-wMK>B0LD
zg7^OArw9}zJDcwRgvxpN{W=B{7IlQ@$YLb4#+s$LBscRsrz0oA5CAuJvL_myD{$Z;
zWn&FOZ-JPsiQ-vJVNLf}v86fXc>y7aLbVn|Nk4jVwz5(YU%SX!M3ueyU-l)65+t!A
zjI;Nk@wFB08Nsjc3OvP6cQ^55*;hZrZ4pun7Lb+z4f1uC!?S3gs0y>4U9x<I^Yx>k
z*sPe%kaNJIlu4^}6!?*?k>Vq&oy$+)GE`ga2URh5zxriI>VCE=t^1HK(MwfRtH%pj
zn+cPIAtKdX`aoi=i^dZ4VKLJo0j8{n?+%GjCy(izHaUH?TAz%M+9<};5x2SfR7yi7
zUnK)jI7`-G-m>W4xys7Pb|X=$2!en2(Eovba-k$t!uQ33B#+wpIHyaNq!Ff#4f`<z
zp?tjwi|ly|HHkXJ_2?{D6y^jeysT!&E`)+<f`lh!G0tNU0+Gq-h3_NP&odmY1~vQW
zH&!0t^~co~R=S9)U%C6hSOOVvB=XX@C|F`!nv1c(ENR^Oq0O+K?mY=RM7LK_KcQHl
z4g|%5JD;=KoY=d93DGGRY<e7@19#COJXSU>p>%*3nN)F*nG1F8f(d`MGPlzx-m0SB
z%OJ#5#2+WM4A{}wbEMg%Hu&(!Vn7N;4fYIirzgYOi)MkW)ttf8;$c~R9-JeeAKa2O
z0;Ix^bmBG_kgYB9-)<9SpO+DFCHaijGux=jHOqsv$?{CwbK7;iD|CU2g18tp_5yP+
znN6Uyf#z$vM8tNEOBGAyzG_RLcpRO~K}zR$N8sFL){DwI(0n01yx@W2kCOZ$S=+1z
zPgH|55_0p)Zn=<Q7Wf1gicBzx4?Rq5BZ{?ZT%2`}-g&Y(&1AVO2<p@7PGFv>>gjM&
zAGc++r971*JC8nswa_EV8?ZO@TBM&e#bY3Z&GE`D&T50gv|7D)KlfM9X9W2rXMfc@
zeE7iChYtL<`i=DAf#!xn=Yc@zTs&$0LRd=!3lv#vXWu2B6JLiQI-M*o)IbSRP+f9E
zf*kFD9D%$9Yr#-(7A1OIO)C*;f6)poBJPV@DD6b$@^Bl(Yg@J6kL>eiD4YTFXtSr&
zQ@=ISZa1)<VgvRzF5Y?dOPB9IQT%oWw2|+t*}<z1AL09lg~HHB5Bwmz(E)nEdocCU
zVu0EQ)>^oy_B+gm-M|@vbtX_Ja5ABZW5Q)t-TB^7H=_4VbQaJ{eW0Sz_=MTvY9P7u
zdZFlb1m7h?$b{!dBC=P!>&Z%%g8!Pd(}0~oMh>0?Jeo1j?JiYLy@7PyI#nqhBrVS9
z>6d#R$UKla?jGdILr2yM@*r0q9(s5z`>yxHf?LauT2tp0AuPtdUYpmVcHG0b1taXn
z84@-I>x+11LSzqrRn&KPeLT{bx)#nvL-nEh*$<-Vspxnx8l9lLArw&BPMc$pS2T$H
z>fie{0AsQ|^|Lpk8xbJj)M}ll361<3Zp5eUui2w8(u8m(MfrCgzCDq`JTu!sU3n-y
zmfe#cRoTrbi{qvyO}45{?E`C2+^JFunRU<5n;a0|Q2D!NF}M(*jCm4ZNXNsRF~L6J
zQf1c6kQvp%g;;XMEOgg$88Kr{$t(loq>X@mk9(7502~&mH+#LZG<DeCI`wR;ZONB5
zT7Nh8;RiB(KtBhrcub!?&}_V`{w(*m#yqNWdTJ+_Go%Fc7D^~6!RkV6Cr-<31IM6A
z=HF3C&=&#`f~OiE62Ny4myMLuk{EBt2;?_%7FaF|(n#LNZpU~vT(pRR#`Rev{Xdu-
zTr=T@3C1I-gis^FQ@Uif4N-k9bIO!XzR@NcB0okH_eV1yLQ^=6l1?8U@(yjOhtfkT
zzzmy7Gac93=z42$#6@5y#QnHO;`AzBkiVv~ix@|63`5K#hof?yoUbPCxn#2A@Wv1V
zC^^y@L%p8>T3kdDN?QtFsTrx!NEe@Ar&7A~doxSrv#s{6la<mb+g{n*YPH7x-F?O5
z_ZJWBIY7~P;qt?mv*ke4?^BUC6xl%&VgOAEe8h)%tN?023Ig+FFUmw5abNJs`3P4w
zk}SU*ECFyCS8;e8hV<_k<3Zc!O{E=<gq|ha#7T0_8jpFIm~l*-HG_f*<yyw}0f*Se
zirs4|WLx=KKKI%LJiu3aaL<wZ`1-DjC{i55okUHA*{#?XLLWjt$m-Ckj>o`odXt@S
zW?Da}yrKkQ!XvVyU1z}aS0mBP!<Wo)K+u?!_Krx5u!G2o*kBeaK6HLC&93+$z22BI
zAH=BVNweT@8vlE1+f&syZr-8{Wwu=+&+^VM^hntzG!j%y+-|OF>vm$kZv83_lS3?p
zr{vOT1&9cjqSpX8YSpj^*des$kj+dCt{QQ)5|A5}HW&HMFLc|{Iia5uW+m$MCO}AP
z^D3@A()9bPl$RXLoPrtmzW3keegx*Gy$8}>dVtA!<SOhLb4C|SI0Q+gQ?^&`h@Z**
zvaG)sIE3J+`>z7^@jZ}UQ;+MMUYOMo)mdgSB^>zDelo9zZC|FKdQ<wzsg=E@lWijR
zR!bt~@8A4L2^V$`@XvizHxUFAhJq3JhK<i8v(`l<V&sM9>|g}>77<Z72Uszd9BgNM
zse8}oUs1zEfXZ$fJyBJ7QXXKCTS-5vUiFJER+@-blRkf23(SXNHjiGsl{t0s)_ww(
z2CqTA^Lw8W>HslwyhpK<>f2Ngs`x2wbEYQn6o#Zs^j+-Q>Sg%eZQH7#dO(bztkwrB
z67ENo<vPo7%PPh^W01tYo@rA`qAFk~$AIpPG#|0#!Sz7*76M4Q6;uaT()$v#mD!6z
zu9ds%pJ1B1w}%`r7AAWo%j1sec{O7|s%>vruzuf`!smpk<+^-3$`RZKc*){&`hAyV
zg|#ZS75LtrBR_?8063JUEC8f>N8?nh;|42V#2*%itfTXk>TfP7NtNVqPNvcYa2tFJ
z023k%1lBz=H~sjZ{)}9dEH9Ebv6F4wnZrrI;oG#wRZSpA6vVnc7o!xp2kX476j}Zx
zjvjuN@=ln!AONc(wUr`Q%ld@t`e`(f1T+#rAcAz-5N#RDqaf!+xsC|YC}o~luk}bD
zO<z!R(HXe;(TnX@GpB?u)Dd1>*-!lZ@gXoyfkZBQ{bn^ifR-~}*0x2OqY&n;s<NIG
zNw^33EhkkkJ1KnRr&mcy2DLQ1pAbzV2X_}fO-EWA(zdZG8RBo!cjD|yd@DdN3X@!R
zY9IwC&hW3Oj`KS8B%oa0zrc%b+oe;l+g7QJ8~VGy)Y}rUA-}w*fTp2}>D>Sr<``It
zdeYX2##b#Xl%3`Wd$^oTAOV8h=vj4aE;wU|8}Zy~5|xXlanb}K(*=l_CF$i&3X%DN
zZB03URw5`NHUN~^7MLM51Sf2VOL{&g=6I%7{+P>z+`@Oru*~PqB}=>wE)6YFbBBHP
z8wP#gH^W0Qa$&r(%~J2hy;&eDRLg`fgo-+^m7YMkBg=SlDfbvcK~XG_Kj0hR)C*I&
z*oUia$0o`nCI*&pwDp)~fe*$NDiSQt;Dz#>X|+IVMD3@@4S)Wx_u1Z*Y;oeSKE%2D
zE!7jDa&YpBlUlo2k%#T5tGr(j0DThzili9sh=+hK5c%ku;|XlAks$48Dr@FRs>1+_
zqABm4fi5!z#vcvaHLK6!`+#2Re{Tg;Y{PdYdx|+1@8$n6VefHXa=5XW-chz-{I~6v
z9oMI^uOVC>P2w)f#zGUZAI~dELipx2T{{#II+oIeH~91JbJ%WHJ*GVnv%u61_P1!y
z#Qves=L+(iat$HfK#HXy=Q_3)H_}oSVBhtZ>_L07UCNZ{WG3r(_wcKN@p2phD*uG)
z+ra04QQJxMmH}r0U}9ZdxMOniY#4@H!<UMv$Me&2d!d^UMs__xl9fzWG7FlwP`VJN
z`zWqU{p2ZV_~mqZGxBEW>M(x#k`2H<Cw1+Ve(7_SjFk1^gH!T?Sp1jI&!Uv*oFX_&
zDsTU=5U{F@-_`?5!3B%s(W)9uHn-?f59K#(V7m!wx^TH-?2J#E(fOdFqPymq^_hNG
z00^)%Zzgq|<uQ3!$%Q$=-89RYJ4(H06u)0TgXmW6K(+4Aee+e|q<sxrr0^6>>3i;~
ztWdq9AmEx<^&8wfc+rAOw~Ze|8mfXjHnyM45qrA>0&k~@p#!n~7Es;i_9(Uv6_uQ3
zOca12J!WkU7&_Ku^Au`D4w0_Bn4^K7G3YUzNtOdpme3bK#(c-#ES<X8cF`E-Wb)s<
zm&u$czL1e%?8-w2B!>Cuk*kHnLq9)o)gNr~kmo+odO8@R{s7lMT(#agmVz2{YsRAH
zvrtqIiS>&t-V6rS@a}6T4&no#uJd_{o@OE`@A<%}8TFK&(dP{{oAK#!3s#UkDt1&J
zk71p7>3D%TRbQ1*dxtU#H5yhHgAW2zyJq9_cB!&4RjssJy(i11lQ^u;=l`dF_N~mj
zMe2zJJErZJT5ulYzz=d)et9T28a;(A;T6qWp{tVsLai;DJ|3coUJ!YZY6@|uw8(zU
z6D-UI!m_}nED6I&9t$-?<(?rp9I`Vu+>Wk?>-M~Oh9~TG%Rh&l>aIt)Ccfc@+KAdj
z&mSmtc8%MQQtlN+r7#3Hd1?M4m1h@k0gP5JHX4mD-C6nXF5iEgFJgnM-ryImK79Dd
zZ>Z0uM+%SZ1U+ZxqQUebU83T&{)FWxCgfgfIf3g>x<=~eicesIYjYvntZ<2hXApOe
zL>ZrbBhtIU_2_z}Z!3zb-O|fb+W|TT)xaUHrHeSBKF=`RRzqsUJjKtkU?bj9>PEO^
z$zjCB5R8dnfo0H-l>hj*fA+xNW;$VT`fyquK0++~w}rwZ-%kI|;uiS`HMkq>m@QSW
z`)Ep#!3d}iQ;kHq^|1l45Os??QoxwQAyK#|I9TLLxQ7S`Of78mN;JG~rJ^aO+B0Wo
zsL3IQJz?LsRB!9unDwC&cp7;WSN<aVK!<~Hz)--G2&^!;7~ogb?7?#N4bJBAQxxOA
zo<IMG_w7G^|1m0EJCbnV>cij@V?^>W6owaB;0j@61{dSZAw%AI!4rXFGeo&jOyKFK
z2`;I}(PSTsx|VdGatG0U9M4BmiAO*l&qTu)3=S+6*!sL)vO9X0uW`3}_qeie`9Wff
zXhc1wvO8LB7#1I#i3XO!)o@b(Kh<Y%-n>~{k+WN0y7RGr`A+d6*#v5d4g*Exk6iVR
zyju8J`oN$2EL@<ZY5inCe(g>eLemT6pnB20PzuU|TLCn|{`%+~`W>VcXO3I|v`3D`
z4@e}wrLIRT5*~uvDZsVcA)eQ?BR{n`lm{8I&`#{RXaW}Me2*zDMg42RQ#{C7lnHQ1
z+y@(6u$i8cEmuyq6Geu-Eq?xIj)7t=?>W5OL?&()X3`_+A)S|E`45cFKZyr-dMR8&
zZ_EW*z;<rJ+Ess(Xn<;6RX}M3HU>|h11JxGwa7$sQorhO^xy}|j6_4x5X^w<ipO<y
zk@Uu<J=QkEP8|p}1pP|p-@?817}=s9p9v~k0i{6pf~8tlzx&1Yo2_E+z7qZFZ#{cw
zeGz{|R4zJx|L}KF@|yf_WEUipxgA#p+r~93cGy_R2sW(q{uTvix_DHYPH?)w2N78J
zK(LWnRgVw977e@|y@mrj$@4%gYK^*vvh(1}%`K8zxEOP4L{+w={i0f*4r`yWkEqEO
zJc+q)m!vXu|J|>A{FO|J{tbXk`p!txxqPHYosbj>^@X4za_w%y5q*c-=#%-gy?s6W
zXQ`83my@8Ts0iWB5pga(Jh$h=;nt;)K88%lc48OYS)x`2mH=bjFfHPoY8|_P%U@mh
zR!+WQZ&fcATaDiRU(0_y{UM-Bww<X^bf}LM#&qLdy-HAX$3!7nwUBT$hp6bMO^^6O
zEES65>$qyKO{E^gCz^+CW9wTY=1%y@c@Xs8-j7D3X5d;hiUuG{WpdFOQ{&3hmhwG8
zh&qwAJQwTEX<TynZbx6!$MrNDSPad$z4ArfC_>ZLtxRU$O8MD4M=zqTfrrV1=lAa)
z_)dE2rZQ8TYHG_iFW3)4r1XrP6n%$WLl;^1G7L*50Yw)emN~v7sbST#^_Xx5l`W^q
z%2|qQiXen(?x1^MT&!4dw4iY3iR0czb9aa#zX1orx6S0hyvlAXbsZj>TGfx|kj^ER
zPR6TX$hDHauTacI32x*2&-Qc$d%yRVx*x|8H_!r7vQtms6Qy8TQK!PQu6hiQ0+(6i
z5TThD$m^ipI@pq61K7{!)kwXv8IKSg6CS5(hR7XVoDzPJYf$Nz2NvH9NU9q$d6cFY
zc(B@TuVhXEK|R|dZSl-AuVgC1r!-W0zIeJx5RAB1t$Q^h1QyisDTP9ugFnTxz*B4r
zk5i)Vz;oqz9SU*^@+dj!GE1`0VA_i%@u!G#?lF>VI`ZBlck>WKKCXs>zLaS=TRABD
zuQ5^ni!b$5_8g<W^b5_#7x?-W)4Zxjq7Wo249N3U4e^P=L()bfWi|x<q+@}4L_z_d
zfZ>M5?*r2SPSkOi9mHEx_cUcRrrPogIf33c(0X&hv>67;)G<m1QaTGQ3`*Uw&d;b}
zai*d%Td+^y(BR{l+W!_-AOAw;B;n)9^6bS{qm_T|*Y4Z@yd($qJ7#VEqvpTD0~;=Y
zXwBItRVc|Ub0!9t3sd4XpaBKTQwm#Vl!>BgeY!vn1B5B*CB#wS*&NNJDx5M1H18Tq
zzoGBwXpqjB)B?znTuBs~XaT|3y~p!IdO+>Q=}SS*dSPbC{+lq@rW&(MoZF_=_`N^>
zvUmlKS7z1l{rKv_k_&Xz%muwk$4Npi4ytEJzk(Fa67-{R;WKb1_nR;Tg_6Kn!<)AJ
zL_0i3)se`@k1n0i6KRBRL=CL!X^oLyD4qP~OOFy&yxwl#Y|}m4I<M|?I_w^MfuZ5|
zER?FTx8ONp6Mf!U$pp*P=ycJfIF9fq9FMOqB!cCW1HyU6-^4ffB|Te{2T6&a*s(Lc
z_zZ9;ML2V;qz~SkE8CkZCttsn*>{uaqIVwn;q#ee4R<uZz|lOThsK96)y4}k9ZQzS
z!~OBEvqWfsWk)d3aTJswJovMt%E#scAOd9g4!CoHghO)RJdP}8Uky<ptlo~^wyVT~
z#Nx97q{V$HVHms0rMVhW7ObaM;U9lTCr1LR9k_Yu-zA&Q)UW*&1O^6bw4VFHKH>^$
zBXGy><DGtkIJH+7#?-t12Wdkk@^wXG0`I0i22H}g4~%{19=;+f5=>osC0<dQc3vF9
z>%p9fOT;f!2aDSX3A;R)&r_;Q|IOR#ZS`7IdE4I66i7U2XF?i3$#6^wY=p2wZ=3)T
zHQsVL)w&ivK4gY(8~RaHctTYJK(zC5=KZM(ZKfyRxFz+$yvK0kT94aj-k)<nmHoxY
z^GL>x=o4m3Q{6qVt=H|bUEP)_lj;g#csZU2z-w}+69%sxp5YK}<8)4kZxS?y@qlCC
z7bnbGbli-XCuwy!Mw%fP8>*k&>2j@J(?o6NhukiXT5@awh4^~A$*Dv3i}t3yIa_Ws
z=xg@bua}d&JVM;p#(nPoBu=lZUA?W=?Z9<IXA=2n!W&@8`N(At;8Tb#OBK9=Wuil&
zZ&(AbvM4r6a_>b2&YLDrcHNNZ)0c1nM?&iBxMT$4D-tMA=9~k$AgaksZ7V#*vO6>O
z=kfmQe$NWl`5-}$gbrW2vr~G9u#FC_#+8S7wZoAs>d2Lchrhk}RW;_{Rum15;ram<
zJ{gXMwD}mi(}L~59ukjAB$0dao-X3I-YvC?NULG<KFqErFjm@=JhEeU$$rSON&reT
zL@Z%wH2hk8Y|CubsR_7XsMoi#WfNVv(TRhEE~9D+XQ}?4!d8t%2+~+|8*4IRq>W;_
zJk|!yIr%!Z8<a3%z+TD!(L*2Z)AutdKb<a+pUSQgIQYBzkQoaoq#-Gcnm~+dNgxur
z89^hPphOTmA}g>W3T43uFi&dUL+mhr5owP1B8X4)gZLYO0ivF5d<TS^+7clK5I5Jk
zBh>>mnno(8bJ`E6x&jLFXcWqqPL)?OC*QaUnA~c$UcUcBMX<$gzOQfXqdGl?QkTwN
zFzh8w#(2quAA}~1Vc&a#$3FX}NvpO%DaUb8&qSr9Hz5fr5zY>WdlQ&lyJkl1;G()v
zkF;<U1!7VR!lrPIWi+)nv8W>T_=6h%oea+zd&d5i{hwQt0H3EWS~?~7wi=KACVo8U
ziz$a7Bs4-i0SY<#E}4?MA(qhzp4)XP@~s;i%v)3*DljRQ2u5&Mm_Xek!TGoXB3bII
zs(3cy>O9<!uOQkONR47|__}`cYU(CM@VEAt4<5vu-uwLre){tL^3~tCj~SBWovwUz
zIQzFs`D=B1cCLO#ozQLYa8qguA}G(w;w7iGJf{?3XRpCi!Isp}-q<ESb!RYxsEJG8
zY`tcPP|T?Duj!mRZ_w?u-N;{O^jItbF1k!E*)hRDWrPaDw-t$QQ;5eT$E`#@2N0J3
zh0N(2D;12tt5(0bQ`=Wzf*~*oxdTb;eXDRueM^~*sHI;tmFvU>u^l0Af~M-wgH)6r
zMjfMmV&JlQ1M^}We1O`b6E2az%RJZM4P>3f^wc#w6pqD_Jx8}-yc;i3&yL<HrKoq6
ze5vRLl(1k5B8WrLgVB)2lig6U_Hw$F(;^i%g&@)||LmQQzxpGs%EH9B`^kkEC)7@$
zo=B{8H&z0cbdvps3B`!wf8r%{xsjv-66JA@LHUWwvL4lc3CdSGUc<6Yb7d}HBh;ZF
z%b)*s_-3Un-F22JD4%bp*d!Tk#i#*P)#0I!juc4Tj+oJCSc8PV9ifiTGdqJu4m1w@
z=$u}<g_A*3fCH{Q4T_eF{Hh^74Fn2?Ih-Mr`nKg&9xOkm=-G`1^p3iXvZF!gy4@9s
zX?Pqy!KHGWq9CIhW}-p_IJT-N1&DKMCam2iLm9r@+TL6$XHJ!G?OP$h-@o^df}fhs
zOalx^OX)+Gd2vtSz?H(0-z{AE7i0cTa0ABqAd00a=+oh8yA&>lJu`?E`-Q}~LP6Ot
zpkjq0n^Wh=2q6_UOQ1!;I)|wILDg)sg^mLTDNq;-c0%~^LLDnGX2&T|7_wQ|7MAH+
zV)-S$??h%`Bf0>#!4QH$T8&f`+%VUfB(M=KRqm9hR`%h@-a2@yjVnvq_v_mq0^;zb
zbFguhD?BU}7eC1UaB*(vp)oJy*9RBPPPk=pFV16}Pv~)4o%)^S#gmcsg2ZARM%1Vp
zW?w36>PbZ`m@3V85|{9lNLP1#0C!OxQd4|EX$a8A4i1Jo5sZgpvNNuIsw0$Qu<zN*
zL53TuouIAGUaLPv)y7z~Lmy%MX)OGZJrQr$m&$(`r;024TC`ZF8a&s>8c$~!Wy^yx
z4kA0~T|qeapKUWwBDxV>k1|w<N9VSIaVc2mMvjc40$i>fqo)kvI_XX@r@oLB4vY=2
zVD*yh&6ZjVr=avuU7jL~Kd>9aR8LR?QNzbW-kd{<7|T;9N2Qw?8yPeq;sB~-1i-DT
z&%~|L{yE#CLh2%}4iV(VJOAv|^BL(?CJ%oZ#P$Any!-E@3r{KJLP0Ov^JEOT6^@%6
z5B?T<02aQ7b6}q@Qwh1FHnp7wGoHtup>g{}qjyycY6ZiX4+_z66b!}sDR!6Dza8va
zr(424y6QRIxp*B;#1~)?48e_h%}m`khvLx?jML@stD8SSrdCdY-U#kW_fBKw?mzxq
zLeOu}2Vi68J&jQI@;h@sOh=;tb+{i<9K5gVPtkNX)s|?Qh%Y<}bSC+tW!S!ne-=<?
zH3pqwsKE{5AZ#LGUc5lJgurv6WDr_pJlIm#qCs$tF%_)oQFEp~WREUcm_6K~OjNXt
zC=T?7=*bP@LE)bn6zgbkBHW<>co)Ntt~n83pV_ta08{<jn`$(AzxVq;B~?`bX!O#q
zWqF+J;UlYyLz6>Qc?dBoc4{}=!XJ!dD##hxJR<r>$S1dC>#-<<t3;pgDWyc#Rmskq
z7=@Xk>`zX0D&a?xF;EW#%REa2Jk`2EmtdV{?6@7ySYO=3N%;-TL`UtjkAul!DPo$s
zR`<q&C4~bWXYUwXn5vnXS&8(dEQi(f?(2Q_&byyjUMLpH981w@K1i?WGAV@NptWU}
ztUw>K^HQvgt`#Q_nu#aqiyI+1LuzJAxSL{T3ARP<krr7xP9QE6E^$=O1tIf)F4-rR
z!a00dkOudRXf@}LA;YL8V+O}n_K=ye)?=wQ%l-T2BHLRg9YxJQT|JGDw>~^eJvak4
z?>oGl-cT>NAuOIp$@((tGEM$ZY?=e^Bz)J|O-YmiTHt4=N|;pfQ+m0&>;#9@kLI+-
zcZ*FBOO2=vme>lRPYK@Rl;tEiBX%G;q9h@=1WE7(?cu2hDNn1E%c)|c)o7f5^S<d!
zkymaozPQ;)4kpJ`riqopj|S1Sm%<u8kTkxz0NL3W7B~p~47}`lxB|x5bf47BLPfrD
zFEN$bB?HX0p?3JfVH~x^G5C@u>7#Lc6d1v&TE(RXdd%Z~b6%Z|&FQT=mHVkP>u>7J
zBNWH%D;BM2_3u4<r*US2QDSLc=ACV3n~Mc<@LrJ21ylwU%ca*07Kc<n>J^TX%|x-S
zsey>ZheR!LscL5HrEor)jW|IF$kA&k&e8Ojfr}nDwK=1~sEE_3TkjD0Em+(a5LJ(a
zqq=rSGbbaA%db|y@x>PI&#fu|N~3r0=hyEm?H2d&<jaj@LNjYl;&mDVJv{lkD=h8A
z$lP;+6Ey#h4`RhdLD#thRV;|gD+a$^OP`*X&0Mg6c$D12ynMSrjQz<E<0NNxbZVHI
z=u983?p*XzIixCu7CVx5Okiof>HRctDR55mFa)N#AQ~}`gGJ5ibD23yT^reSIUE__
z6Kn(Dw80<>HCFDh89sOV3#@y&4S|&&u&bsxVCO>*MeND%%N1Z(Zn9}K#i|ie@`y=r
z4ZC2yxV@5EsR%9qCfX-=0|s6G!V3j&;JeB|*GkWb_UFU$TS%zFPwUd%Em^#sSym}h
zKt-wM>AH@bKzhJ4QT}m$YFng+*Z8YM^wZ`X3?Py&$Mez?!HKk1S61~gpl{>1!z*8s
z^zg-7)n_Ldb~XF#=l^Xoee|JB{~oB{pA3@zVl=1BV=zn|Fa}@DJ*QKGPN+D|Pv(@g
z+Cqbld<rd{MH0>fyH!aY7ECtQ^j663=^Ui+QwXPMQqIKi%2{C2$|_P>fy!j&>Rvb(
z`KO+3OV0r^%t*2mi#-x{;8XVRQ4bcp>_dQQ$$EM`0FVRkUJOHF59*fPGxsMwplx}G
zq^GS1*(Q>5JC@*Nf_e$x6qNkQ7WAa5A2K<N_9S5tbup5c5xOzTl57bAO#VA4)_8)*
z6thcHk#yM>Z=GyU9ITLA|I(-+9)fERHtyU1%A&s+J)j0;62(ZYYOk3hlWE?LMK?I1
z6pNKa++8Y?08GLf_&<iNh)a7@+}edJd4Ns38sWL(?t#d@6}4pKOkB$djD>^P;Wr7?
z%lN^s8R;2{=56JYrOyg9^rgAiZ&i@ZgB4;iig&(}f9`AdS%iU*hOfi>hreBTp>SYc
z4fHi%B+?tqWY%n{MG4$b7z$YWEvjRrFwLl>M{1=O_V^OgxR^$Wl*i-%CTytY+iF|&
z9D9vbj*u-V;?9_$!w)Wacj6(Kkbn<9zan+opGI23)0s;~W|p-O+Eex>eM7C6|6uQA
zk=iZhXnBP}b@gH9iYdu*s7O5)Q^!wpdrZavC(gJyS$N5zVM%zB4g}8A686_fvM(&e
zQrjwWDq0y=Niv<(8%3nfBjzX7Bw-~D7K?a<$zBPmgoE7y6D-0gIh8ewQNemAcr58u
z0Z#nQ6(VQ6JotdOvVJZ9H=93YAI$VO_Ne}>chx(zk=DPw$ggA3>+9-tA(+&?^LmmF
zQ5Wxu1-p!}saJ@31cXs~(oo8f!o4QsDoP}X-$V_{1k9R_RJ{;|1%~~^+&h}IImzi3
zCsLviSZ)IUHAyMRgHaF#IdZrs!btfPcPxd;TXX7FinvnZGPLmJzVpvt$sC}P0SN3c
z7UHVfKe)L#xW0tmYLP23EnxjEBx*QAb*|`}j@lK!C+`JKbe32Hk`tKsiR6NIaFEc<
zp<0|Y5{>Egm=q$2qqsiB5wJ$Nb{iK6_Hl_MbUio6n?i{Zgh!7Lyol1QB&XvifsCH0
z)_*her%~$W3To<<B?Y!pCi8skXO7)3Gs<|w`ToN!{b9UN@2lwp6b}sFP+QS$vlZ?{
zv@+bV+x2ZGhJ|crDJ8^4^75}Jzexcm{Jv#&j9G$YD1&b4EqY$G_#l3&i10J57bEgC
zJLYz<9k%Qi{Jm}sAgN0)aH2dYD+VWpaLsmn!ffjEQA{UAlzDOHE8(lvH&&Pmu%G?u
z-M{~PKmT(_J+C2=i@KUF@FRO<i3upV;3<<`3+w63Av|1oa1q3Y7PN^J+X_#^J~$XU
z|DXyMm7<6#C}9>QkHdqxy<Zk@4Lafm-%zccU_As`2zCRYif~7dGr5BF8V&``Oj19?
z>F#_^=gfG>JQa;8svUx=IvVTK#30(cVplTzY_W7OCBfv0;KM~3cG&NI!MjRCc{=+s
zs9sncVji9%CXE?<q0Z<~Vjq!vC92jbZ<l;bWSeu!E&oNmaGKKndGuJ=mvTlxh~AYo
zY(9nQ8#q+K@!-5V6iZV9od&q@X4}AJ2r*h*w2oRvt|FDMZzz0rHAHYPzi`H8iCmai
z^S+sRm3*4~3WHr6FF*8Qlq+o?d-fk*{sL7&gdw8}{xoB8>dElQ5Ia}H0>vdXu#<k#
zY#L=Xj1BRV;-i#E`1OUMcmo|XLOuWq+mNv+fl=Fdz?Kzj{8&R16M(QhSt3u6;PHo;
z?41}Z^gho(o$=h}yH|S4bVrDvGEx5CS6u;UqJNKAC-f~YYj&IAb5A5ekFok<Kv8nt
z+Peu16ZPZVaDgc}5nixZw~op0cMJn#vdPfW1mSkPEp<0#nedoR89WRWfm@v9J^b{Y
zNL>a(o5TwTQ?N`TX*RBqdZxY2+Jh-_px<ZEx79L*vCwI?Q~DKgbP_f$mgv2w^&IQ#
z*1%@+)I0)47*~ouyV6`(lK|R4-0m6?9{kNkRiI+Y<Raxw>Z6i-J%etKT*;JE)&wef
z?Qc^3?v3Difkmac*4*x&l^?}-cib#p)-V6j&%)RJE&}RJ_8CLYFBgNRM)f$`4z)+3
zQMgf*0Eef0n`TF)cUV9~ZXWMO`NAn!wT=pazj`CKmja4(HOBvO4Vd)vqY1n2PY$KM
zsG3XY!Z<F19M|=%Y4{Wc;u+w7O0V1AKia>Si~huz(6Q_%)Zw7H5lL8fbXyZ}8#+^#
z>~&;knCnZ{UX(ciH5GV(R?3&UW3q~2dcKZ7>f9y~fqt|CB^hLxrZ!B$1cy*P%<P)B
zBeo`rgl@P55s)w;HU{w<AW1-~Ud3iIJYi6d<O!<vTpWJZOwoElw*F?Xykw{K{Xdsk
zH8Ps4J1>;7p6nHGaSCu`%^cSY1M6U)GvQ1~a5D~DvSdfN1dR(y5Tl$Lz(O!2h@K=|
zN9Zc8<#1iswIX$!-Q=txD!!23quc5N3~Iw&YGW`tC@LP)#aMDhwrLeL%T!bo-cib&
zfa9MG&sdTZ)jZt;D>TkgB1WlbYhwT1{jW{5rGVq!z|f8KL+RnV8op+RH=>k?U+n`E
zPP%kIq?K*&EMCmRtPJ}ccB7_})GLOyFq9CM!)=PtJW1$mR6US#uM^>F5QyslzBT5Q
z)RLUr*+Pd*<O3K)Jfj=YE|W$l&9QKm#MPK6wl8e|rLDfv;IIHJ<??6#FjcJJpb6!9
z-@)aFvTOGb1glXrBN#B%{l}KfoEoF+B{Y5rIXi~P*|i*AgiyUnF|7tsG4v@qrteUk
zb+cT5Q=MgCY(%A*4cg`@Gcay6(=9Jp(Rxlg<V1SzWV*x@_@LfWOdK&|QQO#o6jAnB
zs;w=oQfx_gckBDDpP^jlCntuU&K|fK<$}l0GM#M18cS_>JPp7V)3c}H6ii`fNu;83
z;tjIuNCuR`M)ewrOI&4g;;EwWcmlYzK;*(nX9Jqk#^MdV%D5ykXk)QpCzTj_7h!ZP
zx9B|z(+%xSySjNN3TR8AfNjgP!?E`JrtBZ800>rEH!aQtUeK=`M-z60&6|<3#grgD
zCA?>QdOMOCf7!OfbKI(>yivZyA<pakTM>GnZID78kx-V=QCX^AiC%k51!*;BCX#-i
znX5~<jWOy(`)EgU(m9HBk~oqCS1Q9;NISXyTQlJ)dkcn6Q5Zor(m(x1C!mp{lF+PK
zpBh19UI7T=(QO5Z@pod*6}VwJiK)pcf0KO{)27CZd0z^TVz@!Yke&Dgiemcl7Is*n
z0K2#Vc%Hqacr<=c5-r)aT5?OadkyOg8m3!ffOq2*;5kK=EgpAbf0fGTy@?Zlai8lK
z1x9Gbs6;q4r>!Z$-&k)8g7iKmhkD(H*e>_{Xrull>T`&dX4h1(V<Ivom|v<wDCc!1
zzGI!}k`m;ZMe>u99zCi9ipU)rD<pTq>-dDZuj6K5$q;C!DgB(WWAQHcJkff;Vn}SW
z?H5-Lo+SB;QvSC;-<x6oU9allfnxIu+v=G%J4waMK;{yjCx2x`xVp@-EU_9j!e9{m
z3%&n_{2a3#@Xv*!;sp|54_}G~+R?z4c~K9qnzy1$z@W!2nTZqzK!Ou@UIJS-&>|_S
z2AZpZpws8t<q`9hnUx9^mdw2oMS!Qs%LgP0@e_kY54`Iw;w#qI;!!(kmv!4!b6&Ta
zRmycb_kgs*1EP8<5(Pw+A)=Os4;qogb0WHR548*nAS^i^Ovc9XC#w(XxNgQxX`G=N
z1$Xkjt9GV|4yQNWus_Zjtef*HGMM8#cIMC5$FxhfF%U+22@(@`D}@PKSzNZdJ5TgT
zaZ5eS5L9mVwn3HE2Y^;>PM^1#HX9CooFEbk<g=#9%CmGbZ))FyhuDx{s8c@Wc(-X*
zl_98La^j$-C?RLgArE1s86+yY7yTka?ati-?x#N9POXQ7vB}{Fl!)fc50<9FQ&iSL
z?-IF682RqdLnwm|(YwP$y@6kecJzg4!+fADRn>3Tt1yRmEVE@&aH*Ye;?$3Q+ERF;
zVmG47qC$mLjnzPt9gW(hHCoI_a%3!6*H2L>Szk2UM4WG9IxN*U&;TWDS$CJ(25F*n
zRQwBu@CI1X8r+ik(?ObY=&db5?2|3Z(i^Q`_|2ay()<78NuopdGm)^6^YII=n>BL`
z8VwM7**iAOUI)x{`^ryl#_F3=<bxiT#PW;!H1f+VRDt7R6;zh6u9!XiL{v*Kq@Pk@
zA(}KG*q9L7=7=vND!C?Dzg&=0@m{4SaYxH=@`!U!VEf3k+C}@>Fh5?F)?kbJNMJxt
zd~IJzgwc~Ot%vp>U@Bhr+v%@LQ{jvXZdg!iu+oZX6FW|?v`pr3ZZ6hZ>O-~82djEg
zX_-MH4GNCQyIkJnAW(f=@bG7tBuje2k}jsB0FGtggkX*k9d22c@ClDjY&8WBBT;rY
zTGZ=iG#s%Nd%Lw{KU4lJ<+ngT#G>t%)CK;N-|21rgDIllPJdVZr?lye5zXln7BBeI
zmVK0xl@YNe_^FQFG1@fdnIy5r0G&}%;^327^%4oh0YY}t8U=z{sn@w?rzl`MVYlk9
z*=bvQEv%4hGDU=@yLy%{K2^unAeBhe9dNpykB(8h`Tw@dUzwrm;tjrUb_U4ozkB1G
zy)B7F`6Ckv(}xk*p@r;!BIBah^%%?^yd7lT4%-%Ms?njMX*#qQF_r3o<s>{)wUdf+
zRpm*p79-SsJh3t`4P1YA-36m}A}SzGs6s527E{+lEZK}XDm&H1lI{r#n;_-We9rhz
z`K2LsrtVRU4GlkSXQn1wEA*F_PF9L;6wcn~{ty;=NZK-Zmx+6lTvkAVU*th<BW<HF
zO(nCXFWFGcreGCP=+t3;RtWr{f>o4Zu@=&iO;1yp>h0=w_Y|Z_n%51wYbH8NXi5f{
z83ZA7k)@-7PWTYx3UM4Cbrh>_HpTFXzPtg<(4;wEjJMR~OpQ#1>HP?B3Tie4d3}U;
zzREr{_FPWOK+&=6L+Q>y(V@_gFOb0u+rhdeObBK4t=z{cI8l~KS$&S|AV!fiPK`*R
z4}{PacFH5JDMgNg6L$kN8R*EO-IY3(@C+H>>jr}^N~dF>+`}5wJPZ)hIS>qz8jj{d
zQUOPIZM^=RLmc)N!Mqxc_vU{IKbwRJuV$jd{K%F2>9<SsVu^uu01<Nxzz%^uZ+G>j
zu$(|F1<Vzy3*#ec1YT+YXEmE7fYcz1zJnEAd<gS53A+b&)vj7MLjZ;_n*s5PXTmb@
zqCp36F?ThrZ^8p4HDk*C*i^?>10a+o@sdaESIlo2IIPv;yCHf${p*QoaaehQh&rH}
zGWYjNG2BuVel4mkyQrlKy|!g{W0J^5@DjeATIL-^o~Na*Ef-ZHIx=xr>qT<=9L{%k
zU=~EgqrI(fsB3jvTB7Lej*&F1FhhKuIB#8CF&rT-N^rBLo=3(nm>tEuU^QBwp<<2>
zM@_SUWS;-T<aEQ*(h4*x`Lh%M>xWAj-erllhg<ST8V{$3?(b7C*$`|r7am*G^y%Vm
zUBb4`7;}{Mcd9}}(I+J+r~Hesby3rrh|~tPG{s2pu6ss2Tow;*u%_tYh@vc4BLU8v
z4p@0rozZZLCFo!m6Yy1}#EHw&wlW5D#bNDwRISTHE`^^B%LUBq>x~AW_TH89_r63u
zx|WeaDqTqDvN?~hY^W5?v34?An6#&3onw44yDWSH&>{E0pYc4>1Nf9A?nn{%G{VK&
zQm-N~jDU448MPOzML9L5>-IPuZ6USAr!N^joG}o(J6%rorzs{^3}51o3pjgWhT@nx
zBLE#EGo{rFYf4%5e|@uSxTUNb`!;1s+xoHX4XW`O{f?$|0B&}klrVFW3QU?qH95+p
ztx)fgN&rB!yKpjIIgBhLL)@pM`V7y3x|7kG;*QH1a*!;VvdxT{i$DSB3}$GImU@iu
zv~KM`SbcpZb(5DVz4zP$-N-31v0?0*4V8q0IQPX|Tp`P7Pq#F3fq|4#Bf^kmPAZdE
z;je<8R+Ev_4>;Kvb=h%|Mlsi@tR`3kmXdW+pNr8V8@wPcAo+;y61}W+_b-_Zqw%%2
zF%0!8F8JoV!{l~XPL>-hRtCX5{n4bmE)VsJ5n7G$7*o6PIC0?AlBJ<$GCs#z#e0V_
zMTEPRGX=+aStXH4g+;@wvQmS7>Np|!j(u?Q#i(+4&$HNkrf)I{4%$!f?2ekx8$A_E
z2)K?Q=+^txgT=$u_=(J){xSXhw=z`8*pnA0_CEcaKUH!*3%`{m`N3xQZby8nwyA7~
znN{N)>#n`V*yX7^LW|>5M7T`AQKdfVX2$gvBjyOjes3w&ydz}+(3R*4<WLnUZ7ng{
zsN+yM@qtNn$e=o*P%F0OCqsI(LZ~!T`LiQsN-tJ`VyI5PDYHWV@w;8bkqK5=D(I6l
z=)g%Fieu|c?vaEaybd+lRau1uSg@q*C@?3=Q)V(3OMRwCn9?a>IG48rDB$Y>k@bRB
z?i5O662%D-Zw@_S2&QHJ`7~cl^oXvr#IUqj1_3C`ROVAHdUIdDdT(*~Y*TGBb;<Zm
zD)xBi#=JRQt)sz?!s_fIH$_Ftp#&sS9_XV!UC=c!7FG1522CU@B~rtY6cDi&CMI=)
z{LF>E47e1|?FO6)H^*ZD&l1Hz7p1Dn%MePRn>xErF7J(7l~d)CjGy6694}r+i+6;L
z5KJ@3nP_@P>lDRFc;HyOsy$A5Yf7%~xWcg|u&w8T?kYCa8>EhtV84&jbFX_Xw4i8A
zDfrr9zbR}X15lZZ7G%R+Qy9<GiDhN@7y<Q$VO~nSBp8mJ;fu1=9iWMqDyJ?MCn~nm
z8SeM>?-5jYmn+(bEcb}?Wjr5h8GvN{*FaTax{i!?fr(cXc{=>bgg+l8YRq($_MQ#^
z*rEC+wgx~O4&K!4yx)gTXBL4HvFY6GvenEB5CJ$xtb^kb^MAH&p2UA7ReWo20-tMd
zqc!<xmr0&Cz*%phm<QTchDbSP90{LjwZkF@{-V>7`Q`4t;m31n+Ei&&sm&8*%mJuM
z@*F+1hDG^_voQGqk5@-U<J*_S5IZBANIdNn(GH4*>Xe9X;_diSIAS`B{jyXSBj7T*
zK!W}M(Oq8H8E7KuNBE;*Y@Z<dWE<FenT@@x9b|`t(xJkGbjqs@x1T#|L+=3b0HQ!F
zp}CM<{)m_*`US)8o*8XW&ZMQw9fT3JCBoR<dJnvZHkmXw@{&2DXTm8|Q|tY*d9KX`
zQJ}>Y%ha#d`9E>h0W4PDF1K#81Z|WC8ydp=YPe858f%;xM^sUUs;O|3M%Yz<N2NFP
zqJ}@E@KZbEBZ9<P&{Zaj2ybK~69j3}7^xb?rU+7ZeJ)<X8%K^9t4S$B<cFWFoL&D;
zi*Zzyn=7eCV&d+}D;+nH+Kp91NS)n<aCkL1S%7ht%4sc03V9xWphGZ>q661dc2oQW
zZy4FAEd?@4!-k|Ty2RvZJIm~xIf`nRwnMa+Ni#y%08GK?c<dd$$;}Z5>1`#)W6cvC
zzsih<PgcB<nNsz2W+>ju9AwGwefObWUfoX5+2DPA9TmjO--uXoieih>ywM8_zU(GU
z+QH9yrTl|GNr=S^>mE_@&P=mL1ReJ;jC3}`6{PZ?#{C5`mnk%=Fb>{|)Xfs}QeQi3
zpkh3GZQXyg-J)Ygrr4)eND}|uSNE2-?forjg`)_{8_V8QIgj}h48~#f6=knf)t34!
z-Cj`9AxuDPm>EwHx-}JBf4+`fEXejjYHrLyj!M>!g0iIxnB7`37iUwU7<$C8bB?If
ziKMD=QaxVKrIX*db?_uz9H|lu!@u~YZ}eW`^}ueFQTFn~W8RWljr6Gc7TTJMTxzHM
z^xJjv3Sk`bJ00f1D$1=TAGxGc+=1npiO|&_b;XI#8NxRQdFcBJmdu4P71j|BDBs=F
z$6$_v@{`%c=n(IHisr+j&FwDCKHF;CT*;ss(cu^G?8s;{_zJr1Va9?lX=w8rwO{nS
zQN>Kf6pSaA?Qpdu$Ot0fHW@IrFo6ij=j^Cl1N-Yfj^$&BTP(435&;mbt7ZTr-FRU7
z?vN@wXV(3b>Q>59HFJ}KYmU4B-(Sw!$zqWP2445Wco46UCg~rsoApSA*VN#6-Cqg;
zLCb!@Bm|fG(aoP%EL;uHi>4W92FFo$AQn;%DO=G%D5Gqbmqn~lb(1a!-=U~dzT$%@
zz`fHpOj~5&i>;U9)=g67D<{E*E;5s1|K05WFd?tST6Wb>2h3ujsjh&C;|5nl#IPn3
zKqLj?+vO14DE3l@FM~=`eMM-%qW<28J$@QRNMXeSy<GRa9_crLSnPgp(#N+&w$@ip
z;_tjpdsd^Aq2uN&`LXwVNGkDCRA{w_X*>_>p){bGM6Y>uTt8?Gd5d}NW0ho=+$M=D
z&Bl2XX|NIQ!5)i0D8@htCAOD3AnG!d3J%#)fkggXz=X;exX^KdFdZjhdmjsOCi2G_
zOclrM<TqO_<}?H4fIT%DfA{b9^u3?SNP7N?m!{q%n?5q9E;Pr}S+yI)WXAPm-OE|H
z$q5}o&jJW!mph78pz{*?fVDcm`5t2{9srEYM{6vhc66yvo&xQ`1M(bjB1VMmEGUAt
zC|FcRhOXn(ht-`wo7-$jO?L&RB!Vj6{r#GNU$j%~5i0u01BHS-+fbBU)J*Y+di*VI
zBkhRSb%jOb8Q1^;cwa{#Ic)S6ll6+kPhHuQQw(!TBP|s$VCVc#E<T}CINx1af{4n?
zCbc*~1$A^$^;D|y>@%(Pqw<2m*Kba^o{83T|N6sD*GL_zV`16~jOfYG`g0LF_MW+6
ztTZ|nX<d-iv2Yr&5hRr@P4Ho)wPB}fu?`DiPKW3WpgPAEvhS>>KbeK!gqPD1^MaJ^
z%YY#;K;FXp?Uf9D95VmuFFu(dpXRz>8T^ViuxKavUNK-hAYkY+8R`{NgSeAV5k)In
z+!=bdu}dXl3VBHx9`1;>BjGujx6a=+tSHayG!CI)p8d~z14&B%>owAbB^2@8mrMKE
z!-J>F?N;yJujD`e#~<q3EqaYEr>#AF`JwkzdU!D+-X_a+!Q5somLgJG9L3moRJbsE
zLSfmJAF0`>xIj0hp=~Q6zKAFlrlT`k5@IQo0g+)8g&rsPaeNxWaTQ11yfjeIM`DSo
zH%&cRV?bSaMwe)ay|~`GIcu5oB)vPrZND}_EhqI7IKohT#E5KT*cKLwvk}Uc<|5|{
zu`+lVKF7gH#<RgfvFM{wG4DdWF8P+%t)PC)zsHxUrAkz6rjsDv?sJE|x*!=|jQCfK
zt6s1Dbg4o{cjc6AA)t(H_`m<pPMm>3_XZm3yUMI7|C+LAFiU+j$>MGoi(R)=_|Fq<
z1`|`6ZLRiGsDyhFK+==>7CU$+Ab${8`x(3*cZRT_s5AJ0wk&J5d39Hr8Q87U)yLuW
z6;`yb*x>cFe>45FCyL*-FGwlU<t%|sqxpqjRH4jhoysJq&0Dd1y`Xc^MQKP>qljwO
zB-fdDi$lqls<Dqg)!fs?M|c^4+7zkchTqm})`Nx0=PnsguM+uO&O+^Qjf6BT5=!u*
zqi0s5;q)b2y9D>nJ@aRCe+<dc8Wg$%XOQJICkV8m;hqH3e^yy-AHmE31@n4ZpQ|e-
zK~Y+9fjp)#+mEz@hh`h0-fKkjm-ax{r3DKyb*?XqSXFX{DVGPTHW!T|7q|##?0H%|
zi_Wk+;gU#Bf)YHyfeh~Pc@w^^?Y6GQFa5{zc%^7tGz6mEfVR&6XK{>P$RsX%jK%W2
z1+oaH{20F+04VKPvL$vd^iUft6VVj~4CDF0I`BE$T;~Vl;Q4nszy)zXqcL?Ua=j&4
zk~oUSkc_d5;dmIvFsPF)2~e7_0<v2!W0F&KQc~vw@omFeh=%LrWSMu@Dj^zDN%;#0
zd))oG4Fm7?W30h;qt;xAUZH2{MSG5X);+KWUc~%p>7zs6F@7iwA9fB|=Q8x67G_lq
zZ&IHd4FK1VSfOi}qAI#0wm6>DXw#d|#Kw{Oc~e!hb+U^T_A?BCQLCAX*!^eO>~F@2
z{S2UPs7CTg@`zDabrw2eS8xi+H)bSR%@A|0oMJQ4DbNoo!Rf`KW5R-kQi$w|WOK;+
zknAkDPXzKnoj|4!&`gFJLhB!!;eJ!VhKL!nL26<?5+FUS&~H&}@ZMiqvw!iw@7=aQ
z^x)i7{vWw-@CEbe+?0A(aqscikE7z#2IPy^MM&mVSd1-Uij7zuO>k|PLM2mf2=K*N
zbk@fHg01l)&Tt0@38;rkg|M!c!f_KOv#_#QSs|b+3>dsa(vTVw37aAll`g1x18`=s
zwks9tbu6Y<b{A*hw?DEhNF@oW?B(q6E*@APPE!^WpOLmc!cue>o;UiYv(5=|{BeQt
zPaF{;q=AC+EmqAfbRzjQkwG#`jh*vUV?SA9F2p_eO7#Ol8vp`j6rxz8HLvLT`|YFc
zQU%bel9F8e-+lI{ZAEegd(sDz`NHAn=YqB3+}T~-w?l5N8V6BK{Q^VOaI!_~%l#!n
zz%tSI8zINpO|rwrWX2(O=mV#qaNUW*kirmyO;u3LVIWsIyu@FV_NZEf_<n}fD}fUn
zPxg~8qo9v}qa%{{4vgEJ31V9#{7C<5`LmWc%2uB(fm_m;_{bmfTJ^s-Bb7z0)xV{}
z9U^O=e57P9G{KfwJ8?!?Z-25EntSYijL(ApPVy&2a#*f70Xz`z7lmL`eLLE&n&H$F
zmjECbT~Xykz-As?*a*RPonOR^=`}3HTy&HXGQI^i)h|8r#tJzxW>?svOf`D*=YIwj
z$yaw$Dy@sEZ;jZsZcmt18?2g`S#wi>OyU`Ja!8O2*8+`7gzLklb`nUXj}AFcd@M-Y
zk>K9s<0EFI<39|->gR=H1$dGm_9&9>#1T`=kX(&{7>&4|Jsv!1PeanTmAv5(Mcc~&
ze!I^_Yu>+3Jiyyvmc<$B*eg&i=3CTKR@bUQQ73vkF7R?v0v%ybasPlLA!vOehAq0K
z9)pDQ4j_n%0u12chap_+j{Z%9f9Qdi8DpwJ&8ECsI8~*|_aIbDU}73y|G)Nhz0I`0
zkuEL*EBffP%BBsdCLpC5b6IEWI~T<PPWog4@WWV7TnjUT@uraJj^;)W<ALQpUI*8M
zsMNTCFh)n?%c5k2>L#vHZ9I_X@2^!}BAZq&SN4{=?_mDDU;apuUIx0ME*F-QL|Tb#
ztS9CXSD&7Z*k~(o67hk6_n6z9@+8He@D81`Q0s|B!*IZ7ok6K1#(UaeASN=VkM0mv
z)QCS7ARUQGsw|$U+2A6}mSXk=jAeTM^%e5mbnur6fD-wy|22&5Mg-2P2N;r?Z6tFl
zK09ZEzPXrbMCsRzo7mF{#*hGZO!ux*c`%3W#kn%5Wsc6KCcy7_u(Idn!D?0w{kVM2
zayqduZ>C&T-enS~N$`LG#Ai+)%RCy15xaToU?x)m#rxC?AF&S*k@eH<lwB*Nk8qhC
zREd_iuk_-WU~d&A;B?A})Zy<z4iTnA05b_sg>6O16D$-3X>^AWM8=|?l@4kBErZ`*
zx&dK{i;8{{KN%Z@v&y(0l7PdyU<lxN>!4;pq!d^9CNsbG9ldgZNhdflbnyT-ekK3%
zfe*>=b*7^xL@XcKh1Nr=vTJ}$RE@Z?v=MGcOOU`ZqnHN8zG~84J4)KLvY-GCBoNmc
zI(Gb+el$0OM+6+R#@{fz)*f<a8PuEv?C{%i5*U~>hE%vli(@r9joJ(6pYb30i!Zis
zS}BN=LJaxy=70DQL#wGnl@Y1wRkk@j2wrb4>FF@IK<}K5pAaibSPexx7gyqHWmyN~
zM~|ja`yfx<HOhwe!=YY3DmF#b@1jiu1eGkMTmcGvLJbG{504i42S#6@!<knE(EIT0
zONV&HZ>5YXZY2_L-bnH0%Kkk(&i?+R8|tRXd1nn9d~7btnd#7v;}W?;W1Pp@2^hFG
znK#vodSkc-MjrWyYZ*(crqd2=wl7*bryexgh=&jo;PR1`kEz|of=@C15xu)zAJ^2D
z+f!eDX<X><j1Cnb@BPPz6UXk?d-lVHYWb7u(5CT>W;RpZR<(p!J_v_Y2MM)McFP7q
z6VNlB#Kh9dW?ctX$9hR5GJ)w=1gaR(QZ<;=C7LDbp3}ol;_-O~bd%l0;4s5Y-a1O%
ztzX?dL-F@PnPXI~^b$Sx-hK3&Bmy%j+0Mja?+|Bu{wgDK=T)sQ-46Y6hrvsUZHF9r
zQ6#g}6Zmxlp&}2XrCAs|-J#Y5N&-1f`tqh3gmQrsVuO>{IRR}1n!Kr&tDph?HF|g!
zO5_CX%ep$q6kfbMi6c|uqkMiL$yM($n%Pn>sPw4u3&!SQv_nuv(Vw>He4tMLSK8`G
zqI-(_A4@OlxuA$kPe@U;9MD$yYy#*~F%UIL9|}|}8t;ri$)X1()0u!$3XFJET_##u
z$ZnV_!#!&A7gv6@a_aTcsn>7X*3DKc@#c4WCNix({L*D~b+N#tj0|N3IzEl>X}oE6
z7=6yIxvgv}7J=<z*2L2+YeBqFPd?<3&lBn~B`3(*QYC&;kxd|)a-WF?&-ZRddTL$`
zrk0line8^I7hW=h)iwoErM+aT#HoAJ`w;54e~+7hy8K<G{#Ho|rp^zHYkYwcg980P
zyqk{8E$>cy1<*s5bu0}=hecnY(q6>2^W7yGFRErJFgx!rX#z>Fq%skVgycdrC!M%s
z7*RyX8zNw5PzAhS_D{C_U$v)1ciiG_@iKJk?(hDvqi|q1p!#GEzc)2N7HvC@dF_R&
z;J4^WxqC+#1aG)3K6hRm<RsR;h65bq)Wt>Ltx|TDjgv@-kP(y9q%13-26!u4(*wy#
z5m@T;Wtd%u(&)m}hzY<swj)XR1=sDiVop_c^c-Fqx}*~xzIpZMgd;d~?<UzFvM}1x
z>rF*C`K&k|jxnytj$><9=?Z<R77%DZXQ+tAvOx;B!<{{5g;K6aS?Z3GVoyybNMnuZ
zgAsJn;VTk}NLbE0;C8Hb-4-(xT}x$!eQuphiA)J?C0e)kPVD_uzNfQ5Nli_pjoBhk
zRNApsCQr0!hbiY`!5O%+WBkkN9mPhEy1z!<Td5reYP66LCD1Wil5$ZhLL(0B;8)6o
zJeI51)M?(aVm*yZfLqZ~2Fv6^dB=cVG@BGTy>AJO$)3`~y-QU`mg_QFCUHxK^M2+N
z-Cs!n-?-tDo_(HhdW-^;_l<c1ONzhZ1O|6j+`Yi8LP<B$Vn`jkqp_`2r3NLGAFJ&M
z1_buHXHX67aRMm~PDo93J}*0@%k!yFZb}{XIg-zR!mB$ndojChY_Fg$jZgi-NA5{s
znPi)~Zh#^vSS@V>AroqBYhG_dv5l+{MdwUAtOmdBK+t@4OL~T<HDmHkNuoFFM5rSi
zdGbBNn*xUn(EW&j`KbJbS-Q}%;a!L~!F`!I*&@l?=C(GotutcBgV+gzyJ_$KyPy1W
z$MH$LVo<uq3wa5L1=b>lr_x_bF%QHSRV-;Qr_D%D8P&wqR$1B2V;j7rRw^@y*Ez+V
z1rMpfwfE4ttynMX)U)o4gj0%~AXWs%jI<H`dq$s@Y;vo$t5bLecCTa#_P+P!f7D%G
zBBxEL;0m-@NE8ifxoUm#G;UWEn=2!=lh_bqi8?eB51IKoFrh4ov*17ucM@&EKChK3
z${9+WQ67wAq5uL&HLMQdoEpIu7;Kdqd~Sp8;AoH=+x++4vwQCtL#dF5$pNsW*ZKmr
zF=zBbR_dUf+b(y7SbUMh)1%@F#X%;DFq%>9q6!gF5hc~n(kMeT5k)!DTk{jAVU9Vi
z%j&)2WM-`>&KT_*UNCW-vvKIc)?%Z?)Z8NPU3lZyyNe_Z0ILE8flc_91UwZFJP?j4
z)mc2Uc%{ogepnJ?IA;XJUN#exEf3rgV9o=0M$VB9>jCw;&k>n>>TiNOBs@(WLQqTh
zG+r{+GN#Qv+28!}&vkcDXJY~L)wnSei(v{H6iIi9Dq$g)6)Iv4BIJ}-S<+sQ86R{S
z1Tw}2f&Dw*?6y#f13yKUJwcOv?5E@;SV4q|#S-ZVXv)o`WSPx0lvu+0(d^k$s?om1
zW+q^LvyEroIbV`6LMLhfJa&DdG>@31gm;9$#9%D*VUx48#T5`+0U5%3I>Tw$B(6Pg
zYfLg$*tZZ+mdr1^1LuZNbI$O0O`arp_oYWJu2jpt;xY;3{{5ZKOMVmJ<<hXFW>wDO
zRq#T!FpkgYN%kAALi^$KxHzBE8<UhYh6)yO4#o`c@h1KEV;{gN6$S(n#Bx0qfKH67
zfX7Icc-USj)qQxP>x|o6#8KB`o6{7PElvHZFg?90mXuhz{Chv#b5C%25QqhgUSfYh
z<rpwQ_W|tS%ob^ryc$rrRv6gqRuq|vK-crudQkUX=-ey53l!@i<&Og9g{L5DT@6c8
z!H@@zkYI3;dX4L!R1LX4RVf!&_D<X#d!`$%$x9kAvo;xnU9ev@;MgV0wxFz>7eS$I
zk~bzBC8O4hr|GKt5sb+GKuBO#PypE5IRZtGOgxn;9Ve?xAB=lTs)kYgtSN9y3Ymbg
z8DiP-M9LJOu&Ae0m(gccS(kYuBSN+?iL3`PPz=Q33E(EY!G2uvWB~gzy>~GXeyDRx
z=OVH8&RyxZeI9rd$77(m87y#4#5q0am2Uo6!uet17ioTj<%m-yw_*tSi-`&D^VSm|
zk-s>oMuKrswLOwVSeUln0Hl(G4@Gf4hO`rjs9}8Q9E^=tmF<wDBWx3L0XHSkPjx@-
z{5EHZ>l?9|1Q*)pT`6|Nu6&uTvMc;(HC%xA=Fy+JCz+6O&GH@YXx`P{4teRjyl#@7
zBs`#u@Q`!TTy-Gzf#TL@lW?sno}hyl01*AJ#2g_DKho+{aMMJvL3s|&8iq0LSiI;b
zv8>R`J;_^Y$)K@w1bYC~=y^b|qiyPtw<F4k{<{3~dbK6<3ED#c#@Czo3Q7{5c}zIo
zC+kLS5Aj}VqDSy$=<K=xNM6YpNu)bLllnrj=%M)J;9~{HlduudPxMmNRU}(Yc<i<%
z;j36<{w7chj3*FVV;bu%4l?EBllHdW`{loIOUG6=afN%6D5SaAN1XMfrr)!ppB+!h
z5L!>OlipFBZb`v(480JF?+zo#Df}s-uH|!0XlP5R?uP=zGX88rqJ#w&b*=V@DOFqU
z&6-Y4&b&KuJ+nttHT9i7r2G~UV3?e=9#eDcAPIqwyT=Af#M#+Dl4WRV%yKEy$IF~h
z72LE-8_}uBWvQ4dBgFhHT?z>TeX%WgxI!Z|2{p<fNHZAPh*A!qD^bDhhHfQfu2rj*
z$bU+I*ii}m@ssMv{fiR95;XWwL5*0CH=c}PGfjtQI+T~$H@;a@9<PWgXfg8uEf{e}
ztd5!!g`e;s$m8B1A>UEFJW8^yOKuRib_u%7awOszHC*b`rZh(=VXM(h*?+3-Y$v?;
z-sjE%<96ai_bfgFu%nr`RjqpjZS&ekH>9{Z&+K3#7o2D=%U<!h@vSTSf#EqI3t*>^
zg_i`FsTTe_GgV$O9%mVvt2hCzhR2;`7?Ko8rs(~Etc;66va37mu~>B(IowDz@}K(W
z`^aulQPaOiUeGjLNHf)9J{rYI2oUMHXv$tdZLzCeru7(ivnrwb`&yS4b-D-4xJx)8
zUx&WpC=8h9oSD`-SPfsHVvK5kJ1M~5y>o<(@hFJEc8vkkG=RiqAL?Or_U}K)g?{0G
zmzRX`IOr(MB7W9}Nlj6jOiL^RPG>RX5HIGQvOrg0R3_3e8)gzW=0^z+{A$HDsBV?A
zS_GP@<3&o49KE=LyaW<c(F3(8T%L{amDon~@~yd@HZp)^lfso}?;QW8<F(7)Wsd|F
zFY*~k;)c_$3wk|Qw=w?U(G=#a1NMvOKsgE_qnwnEWqIWGJ2ENSivthMl|ST*7=Euj
zyiU`gQ2d^6;R`Ihs{9RQHuRP*aE(=4oG!126cF4j7F%%GzdG$Mg-MW|M%_>-0mc%=
zKClCd3SX~l%RFS?n}FWM)8t%m^ty;a$I-z&^UH21?y+>HN8=E{fr74fcV9dN4?wua
zBS`T7$hGi*RA-&4U<PGu(C_zrE5l^cAC0bjfk|gC6tY*;dl3yO!PAOh0%+>B&?^fo
zaAjFo#|tGoOsgc`CE~?Mr9KJYeoQJiyt28a=oVa$2I*MPQ))wBH`mQ>yvwFejl)^a
z;)zX103Kg{F&eln%>+t)pw-dz2JNhs-Szj4c&0Z+KQG_;4}Z-NnxB|fNmbc46@kjE
zg_W43$cQ~3OMcBBOR-+(stUj1$q&1;)PoR_tVIcOaaB%$o6wNt$~M#oB+eME#+w*u
z<<S@$_a+G)lZg`*B0Ic{po*~ay%Fuo$k;K}Q{T~2cYYjW^|U0unzJNOTSZ1#?`>VY
z^WS{GyV(+=BWP?mzI39LPTSCt>t0kW*erh%_de~=vZK4iGX2BPMf9A~a@QZoB>ki(
zHfJK;<LVPBwRC##{4ac{H`DTHJd*)F2Y!PWKny>eCa=!Goe>*s<3T-1=(rA+dWK{Q
zS9K~Ch0h2S%=sD`Jl$*-)B^k$)&xo`b=bW-rIOdCtwmJZzG&1SqX|Qr+o?CT)O%|L
zziZIdGD;qnX>uy@<ytUUS0^;@k2YhwyRCMa2B}u}vj5}{-m*9U;dsiAEgre@FNXZH
z*BE?v_FBNe=p}>q1XoL^Q)dW;)5Z#LMJ0K)_Mq7^hIBc40mdYm>C7U^Lv~L!n~@q^
zXQbgZc_ZjX6x=rTI^F8lPD;bEk-c#e@7fgQS9TOBK#Es_9lahg^Vc$~I-tXz0f6=c
z8@{@0NzXV#!%HAO`Hgpq?-nHu{1a0tf4jg`$_ENV3-72KN?nheA4DPDQ;;fNGB->$
zV!8KLnNU)W2xXn41cDGSV-*M9i}A@FQ(Sgz$ig<%g@~5LaO$?c9<2vcYwD>Gzsb6e
z7OYNa#6Yt$_vG@n%bj3b@g!rxjY#B;Yut`_W<aKR+l-s%V%}sSZxXqgXyso%w{H@?
zF4ID<+@C+PmQM3(#Vz&isI_UJ-20Isp2nb^!)hl)!6T?xG|ZVKBbo*kfvtvTh~Oy+
zkmqw$LX`6TYuJ2Q`A)E2r}K}3tgr?1SaAB;fHk}5sS|Fp$mCEorrnI#VBmH@=Q<4m
z)8>R0B(yX)3=-EpKY!vs|MdQTh|e1qnI3&$&jaairGGoxG$3>EWzWD3E0HZWZehei
z9A_~^jF3Q-Nu-$L8dw6MNO(*9Bw2|pyC3OC1w<+uC`2<PFPY>Sna9h5&+XdS7Dwdy
zod5~7iLC}NsVtH<u&ZxJ^>7sM5NYFFva9-KdP!1^hVXCV%`g3&jO6?A)XCv1pB(z9
z51?SK#WFyZSH|9mThwt+hvzLVv+Sy@T#TVOUc-vY3Pem^5Tgd~1Sn9Tz4=hb62u8x
zLh$9y|DV10fv@Ab?mO>1jg*l>+wYB^(J{=@^9Dm`K#>wjGhRkXo0-7?98!=8GK|YK
zY6QZN!Z>zBW%co@&bFR;xF846qXaQX0(;XMq+kbD^M_KjiP}$E12kk~QziPdN~)$w
zEGbUn{OJl*vx&Od*84s80Tg9hNxIwpbocYg5S;hk%$<ABJ@?#m&-vYR?+_95`zX5L
z&}YYQ3=X~4pN`*_u_IXcLt^2FHc3gzj5F1g&>{1-A_OJmRk3Vg@ml}*haS&ZcQibF
z&sQ+RKagz_amxqZAu@8Xl#Q%zZS$g;_9K1w|Ks$gW3*ZS6TvU0i!#d#a5{{<ADB2i
z(fkczE=tT)0$x!MVJs6o{f`H3Amn#pot_Vxlo{<~Bp69xxVZaqx(q#+5k<4rWWbJo
zhqJk1LYO8bR(hCvm^z!-?Ap#hW53IZn<jpEe4RDmd$W7SKh|$-#A8Cr$I`onmQ0m0
zkN?8H0%f_e&*Y8F0kGaZKRL`x*zRT>^8{-Jc=0`6jWAzE7vjdSUF+k4nh@7eX8BnZ
zU=}6F{qA@{gb~)?6Tuf#mRF{OFWmhCP|%waVn3snYCB#*#23^4@%}yrUs!OMNt6Q^
zsziK-8)dGa`F6~}?&gxU9nS%lVjq7H1%5)NDJF*Yr4yJCJS)9TNW`$Aqlp!bF<^Eg
zoETy{T1Jq~L{gXSHJK}5#;I>_KY+<~eMBbOn{S3^an1G=Dck;hAl~_1`@)Y7-}M4}
zn%>CF)zvxu>bGN}UfExgaTlz8XNcdwj~RX{lQ0AiyEgnbf)8~IK?_p|#0{uw0{i~!
zQV3jF-%9{~@Bz_wuLNvnH-1}sLUzaaq3lBw;h>!vCz?4~_7dc!iq8kv?HXq<<9$G~
zu!J2CKJ)}bMS@SCiC52iD8H5X>W%FsF9my9i#;Cf9v^_j)!_+Z9w*|Egrt@xL^uKJ
zgBBZj02CYp`rn>q*Ac6~kpQnzV2d{4(Z{lzhr4%EU~==gta5NuV-_x_xG=vzp8ZCe
zeQ_A%5vUfD5Y<=zz`PCCuX(KU#N!Y{V6<P>I0y=31Pwx3Yzb;^$WkzZh<Fr<Kn`hM
zOa!K^Qgc7}fiOuo63A$=;i%C4F{qn3Gt8roiX~LbLTDV-l1bfp>5r~Q0d2%l6YkzV
z{X+1;;N)okuCy-hpe=*B(eLy`05U_JP?+3>&xOQsh`3?TA#tne_L|r{xtunhCji8#
zA`wWIWHsA!<2XILQruXV_e(v6&$y9^`o!P9ff}0)B+GZ6b9biag4W1&JJX&^+0YlW
zmN=bVwje)1D=F>|eisNNVDbs+C>yuo+Q6mpokX0qVR}l_e&hx81k?S7F_gic8nsYX
zi7oe!T<QmwA?o+`?1ZG)D%7ff_JA+ulL23RT*$j?H-;@S5bl=kl2i+YPdAc`{2D!x
zz}29|m5HnGLMu%a)Cf8bhru@7ag(CYrb(HuFj6V^@xcT8M)8@08%+wpb_}}~dk9QX
zBJb(d`lauEn__n=%eR8DzE<A}Cd_L$4rf?Igym%0Co(3THjD%zDQvX}x2hqsxB#M3
zGmKADeKRfy<bm*SuLU=z6xx4)JlJuNOa|rt1{?dwgOFT!VF8}jjp5LJ!^ehY;7ARp
zIm!CHPyXGj_lPVGTpGVg_M%S*-X9J<A2xX<)Hw;Spthp-MKAeC3icy#UJDCB<{nWD
zLm~s+6o`_HMLROG8sGVq;PhO&4E{+@u2D=lI-=c3^c%q{?{7$>bf9N$n4KXBBz<0I
zIf_XR8M~ubr?0Q`&Z|~gw)r=?;@<l3-fiQv<Hb*e9}N$W!<Q#g7J+TQPJBMvQ*y2W
zNa6rwC_GV3Su4YXmi7|CVC?O$4O|L#usP+(@Z8<JbsgDaUp5Sx6nykb9tiKww%dL_
z{j-qWtNtt;9(rLI`}HT%31nv~Gw<Sged%Q}Svc4+FW7r)U*9XiL~zptdp8o4w~wfQ
z(=f<g*cCYJ(+%7v#H|<)f&d<(fbN2IVYk*)NhDazg5Z^4ydT`~?jU&o_}~Y_L89P?
z!Sph^jRf0>fOZd1>M-cv%dGJGv%6%tmvjdvLIg-!1tugw5ubk!-7{#po?qL`CVzYP
z_D-~Zq%XJ-+zr(51LFtA8MBVD)z#5)Y=jshWT|eAo>s5P_QZF6EEK;qHSCo8MVoo|
zIsjB((0_M!_p$N2?`F`$#Fw|W!0L?u{sqR_S5PN??+?a#W#r*u@YuT#WJC91s*P?I
z^yy#!R<mt4r^yQedncX`?!P&`B|LMQ2{tOQE8CtiuNUSgaxwhm&x{Ga$Xcym=JI3-
z*U$^;(G)~GtY7!0WL;AwI?2Mi@bqUvy7)Ii;@?PDS=M@cntx~!6ZfioF>4q=c!AsE
z#L1IvpBN6UPK>bpw!f*HFGOr}!frC8U!_Alf5)|+$fro?BfK_o^868AGV|Hs<c>=d
zykUmz2eBT9elgXn=|H&A95k>IRDr;xq!Gf8iG>1VCPt;z?Q2E~WMMJ3;>lfDGbcw*
zzZQ<)bGPi?1B&rPN^W+RNM|>_=~9qKH;<o;cFJat&)@x8hyZ+acpz)9rXnu_d9E<K
z_Ql^sGrno3$D0PR7W+Rt+;?I4ZXoja4-f8Rc4F9VGK@(p*ShmYEp`$L`hszsvxyTD
zp>ZVvon6?)IR9A&eD>71Y52omx%)oMu6@IY01)mQW^>Z6JRsDPQr4p`;z)g#?d;{-
z-Nb|re`sHJAp8)~@;xc@<Z&jEX`g(%>Loth-RtcoLU&K!Bk$Z6^!-v0{C@EM;KLWv
z8-rBLpF{hY$d<#{PRJ}$c?knWx<qs;kP*1vRi7q-={0>pN+fCc;a5TyN%rsf*!YF)
z&=V<UD0AbInQewW*~~F85c%)Z7jMDLz0iLPy|IsKVe{dc?2{%)#6i;f;sXGsn>#tC
zl+7D|PTtIRbO`W(4YHGLhr!+cNVB1?+9`fIc+y0+y~)`84GDZYO&=&d9}^6OH)RXi
zjUlP7%M$d2C<<C1TkK*`lRX@9Q4TS63GTKTJljq5(5JDTly4b(1aK<d#h7t>cmj<J
zmN!g8Z_a6BugF}4c;F}KNXdy4Ax|1%gl%RTAc|N5X?AbK@1Elg4M58`Wgp4{sOctD
z!R{cuIG(-|^41vkI^EZQTXxsE40A;CVn9^u+x{Fp6pPcphEFtM{Cr^NA?_yd*auNR
z8v%!mh1j?<@d4@xlolTy-%cj*yW5g<qg_Eb222s`m<Yg{aU+=1OGELCNFrQj{xz*J
zD{?8FO+&Hr2^USN)n+E|{ou75W3!6KTdfu{-1h|d&|uHUh8Y5z;tHFz8JTgQx(8~v
z$f{P-NN|G-VrqmBV~aK=IGlmEZ*LH6-<#HnLJ&T-x|uX3h1eA+&GvmDvVBdqR=sO4
z<Gbn05?ClnZuy$EeJ(6D+HXE}6E``<-T?hXMiy=qT1UOU>|8U6)Lj?cXtE6LR+;;j
zr}O^Buvm@KvUGQrrR`y<dU^GkWODUT8ry!WVY|wAbBDLpKAgJ#_EzhXM<7&Es<Bde
z8CyjMr7rbkBRXTduIjT?+@7p;u8m*+AAT;}9RXdAX+(w4C4VogdTM<%Sz(uF!`XCu
zSlgB_Bws+pRNWr;?cIlpYrWl`z?x;NH?(^kF%1K((8-ovgjPMP+O^%`wAI;eDH>da
zv-GXB*Y2q$p!FEXc~9=#@(*p*DpvEXr3bA+OZA*=E7eJZYrVd*{e)K=tZ6SQRjvo@
zqh3rYxhi#_y*|qghoe<byRqJrjVv}p#V+S{d)Di;YP#PE-9t%`Tynkrfzk)9!qO~(
ziXnFTQlv|_RIP<(pI%H<6c7J~{&9@j^=<c4HEMydNF^}>OFsGUa=EZlsX-AmQzTYy
z)aN}uC8?sd<64;_kvYE#Ypg6ttI#d1T57dqq?B|Qf6U}Ad=hJ&!_YLw*eySJM%d@u
z^>e^O&{|maO7fAMYATOEtZ}I}v+&tP#@sU_xpF^!!O7~fFQV>=tfDN>y8+wX1kVS7
zJ{HX8XTlDf<}v@fw$(e^)RTL>>C&2HplG%9XL{0ccGrw#AF+ur@5?@{|1g{1x{?j;
zZ?3py&zk4y$+Cr>W(V7Lfa<+D9ln(2eRGFCci*97`hRI`z0cd%e7e<`_ol6KQY>@X
z>sy94pt*nm8sd>A!Vx>k65hMD&znrD^75-c-lhM)#`zQPqL2S|k9dQJSEYxWZyf8l
ze3T}Y&RC0`Y5S&Ty+WQH6?&Q@c09L#ZEKnKv-&1+rkj;DT<IfiU7Z=%XT#-Y+Iy^B
z?(*_ww|KeD(usPm#}Sl#YM<vvR@u)B;Ciaoect09k&1PDwKq7?j;p)c@Ho4akDNQI
z)L^YgTVt)B-1Z3|Y$bN_+Wq&l&pRutSgT+9_Q1RBv{cCSrM;dm5(mdwe<4{)!X(f2
z7y|Bgq=##--|h{zXZc#5(uef4m6fp<x`^}QWZ7`W+HSqwmjtV~mRSm7yK}O2jXoMo
zCedB3vj5RUslzSTv+Ff4qXQSERlGKHCyXj;L9XgIDCE3E(Q01E2vZ|98*#<;ZIy;v
zw+{rJrjwOBt&r~3@|KY1vbfe|8hj#&gOiEsr!t;8y6mAwkX^c&tMVS(*MYU{dO>ld
zt$es$4<qYv{}#HWqLh*zLe*&og<kR0fW131rl?#i{Z>+8S#a#Gl%gUol=+sHo`iC2
z(Z`C?VU-0bh?V9%*e>OVQg{RE&Of%HK12(eBhG8etvfv|X?Egs-CnFAGv-AYr7Ln|
z`oF6$!v9)XTrU~QwHeDx_A2FHFTureRqknedtFs2FHov*GBuXG_kvZ}t=R3#VyViw
z=BhZFBVXD#ovgWu<i*ROR{b*BpHB*>Q7zPJx2HM{yB@W?s1aFI0>@KD9!uBGx74}9
z;uj2!>fw3#9zlh3+E#=2UN}$#v~fDM{<Tn*p57gW(`eV_s5~1?+nRykbUO%JZ8x%Y
z>fV%0C|!-_tPSt%-ML)3EPZTTXn9`WiD*4^)8{i?O*)B&rrn;u;zfud^~^p05qG9-
zMaK`VdBvrr<6eNY>(+VqW(=nbNK-VpcVFaR>#1J5I1kGY|Kb)OmFn9`(Qu@J{XJ1!
zqXnq%bS)b~w&A$2HFn(5z+3hhxLVW@WhWe(wBpKj#6}M-i1Ew7QhwQPI7Oms7?$4d
zPzB7f@%}vJR_eQc?rj5hq_qmh+Kh45?wzx_o<)^+81l-JSmmhS*29$A$(mcpU;MDb
z3PYs7VnH*uc5pCnHbvkK<I&;D+h5_A#!hh|nWk^4{a<L6_)e!Vh{(DnBJt2W-$6Fh
z6K#mD+og`%HNF*LQq`uzT8_*FWnQnfRC_d!?cGb$wbK+p>!DC8)%HUK80n&djM|Qm
z=XOng$qz17uuj7`Znbcelpoqft5!Vm#kaR;o7GgMNYnP3KM`t#>_)AZy;L97B4eSL
z1sr%boZCilX%HEo3ds<fw9ISE*bO1dztoI%sxLL&o;i(km@%-$a3{92XP()zkk6(h
zl1>@=Higj&4X5sSvz`{?fTOTD`BD$^r-e;#;YtlALB8X+t%@%&T6tBnlvPq{psEq4
zaH=A5ety~--ofmjYOw=A0N-0e_$cBMA~D6ol<!+*`!u+<7e$UAIocPtwds!XU(KBN
zW?Gfi*%(+0i&|HYQo%kZC)#`T%sK52M$tg@q;3a0oIytgr$eVY9g<_@*$;giN~p5^
zFxz2MONuLZvu53Io(xsN6{w+B(B*rM@0?TWbQRSKhimlN<*Myd3#aX0FFf|GnX;my
zGqnl}xgwII2BBUh_N8ydc5(S1{Cmv#R$MEZZ9A`fmvW+x>exTaxi@WNBxN-z3mZ&2
zjcQA#9KsQZq<o5#KUejNs%&5IEq(>Y;;uwtdJzqrAl$G2$1>F5rPPPO6qUwK-3#{R
z{LuW8Dsfas_{hCtScF1gNv=lHGb8z0DO%4{ZO;$d4>##F2d%_CnAin<Aj<}wM7c?i
zoxS%sVS2tD6EZdyl0jUHYg099*+cbvZ3-htq^{~1^NQvytaf1u4XD1VU7A|u`ztQA
z3#SbL;kE-)_k%5IPI9jyl~nI9XaL_<JMEp#wX`0rQZHJmmF~Qjp?NvwD~a{)O60|X
zeWxRbA6&Z77H$?TURzs9OXl46Z=hiMg7CCz!N>MOR4sUw-*%#4AxZ`xZMTbdTbjGd
zkk!|J{CCF|!!$k`jV)41N|MF`Io?kEf~WGjkqRzKMW~87Q?|R%?G!$`tg-^czt<_Q
zp@)s-N~#&#++Qe3o~{2IfX=YEFWs@46ECOpFb(r?dM=NhU5E5fhk81EF1oAK=(pqH
z@s5}VjAJKFeNR>odhMzcMb*h_eg=DOrW{!E=pO9{y^>ZuH`7}39`L58%ac{F)9Y02
z`P1|BZM19^U4P-x(s_I)xPEEok#l=b&oxKBU1!PQ+P;G;`v!NkAJgN5gHCi&kEerc
z`t(H7P6qRd{5J0sFKoFn8m<k`r%XQRxfGLrAe*@_olo`ofhMm#?KEfR@?Ckk^V&Y^
z7DV#bqm`o_8;RaM-<}*;tAyruhu%3&B@m1Dr-CY4@+K?hHrg|-uT~FNr`IY!@My1v
zXsn{|`_oYseJ=8&2cnq=0_V|}lgIT+bMW93I(Rv6{leUZXr!u6<_DuP7*A(f`<vNm
zyFGR=oB#CD>#ALcQi6o8{I9<lguIYW>7PB6j+LA|cY84Bxjz$Xl(GyiZEtqtzdIe#
zF*;FItJ)%V1CE}KW-O>_l~~0OlZ>Ws`|ZdHsy3TJ4pe<#(1SD9$dmel>zebjzKub>
zxZrNngN|oTBm1@c(8;$G=h9~{vJ3H$KHH1Eeti0t;00F`tjoHXr89aqojUsHfc?z$
z<vhP7i!OV;;UQjJn4C)`j7s%3TCX(93su#dyp~rpPr9FJoL;KjL1!d-xT<y|1Jydd
zqG~TRdY+tiwwB|N_;TyKt_BtxQ&qKRZdtp%OV!2w7p6N-?}c(^iFvYU$?e@!9?tU;
z<n___?Yx}nNB_m%YY*gy)1}63?|vy=df#oIyd6vF{3llz8ix=5+syf{fAsd{H02GV
zb7^@o)lH{wF=LI9f2>lY)lV<>*$*_%=EY^tYw?n5iz-0;LSrUcYAjSUOO2Ok{YLL|
z)l$Wtn#If01CIBpmNT`~V0fAJ&Y)KxkYv4O<@7!#X=$TRIeuU1+!}liIf<%A`c7&4
zln#SO8i(^}Y0t8rxj;$Lt-mn$a_%s@KIrsbo@)*|xBU5a!gQA86F-xdvuRqMO54XO
zfb!;XUh=X1Q|YtS%Zqbq@5^OU<H4PJgW7i0Yt1ZiIxYFZXQA~m?{igg{@s;?wG|Fh
z&FFx3tJDKD3RX75l(S><`r;7})&?`x(%xGiVNLV1*;n(W_j$ML!-pPy-zoj4iyDCC
z!aG0pT;}v1$wr)BYs7ix*xO#(sqMwIrKdbrrYxoDXys>)n)-OYH{I=>30u97c?}VT
z9CpG_;n6~+W+|FTo(e1Z<tlRAnaFvlWN56G8tx?GA-WN@s4MpWEJ}DiGXRa}s~t79
z|JK@Vl{%bP(fP)Mdf|PszCm7r@C$RFs}>sVgHCT_!dw6FPsfj^iy0@newgO^SvWab
z?cA4Yt)`Cd7_cWF%kiiVwQa?Ah)#^j%^$jX6vmvXAWS_3VLmnmy3sjPK2WvYQ?x#0
zw<+ihQVPM0rRS&H#f6F>zpC2nu4~<E4K422>mANtUkp|IaQZ0Q4!1AB(2LFQ&D8CB
z$o|ClUi+-{?l4bFX4#q!+aOHkZVeOj+4f?#?0z6my{V&-86Aafw0T=~97SOb^-?Kp
zpe^}hl+cwo20ha5LGK>E;b>GUSP;TgFyr(-5>y9r__g$C5HCh*B!VD`ecslrpr*b4
z>Yb`MRxNHnmrl`sIbGt$P|m~WWNco_TJk?mXKXsf6W)<ZaZmAzzNLy6&h%RC8E3t!
zW-2Iiw;@UHr%LAm$Wf5;P|2`nbt-2;1WrhkySF~_Zq<9iYZrmj8<fYhUh8)Kb6Pld
zzt**xucjD6(ah^K)NR%6TJ;V%KX*%fJfQ13=~=HH9IKw)tB+QrL0X^3(ahDz7WEk?
zu4L-~%s(KTW&|sXC)>6kAtWP?>9I%=;UEhoie|ao&mefQZ5Pr{5oPYV=zC$~0w#==
zG$R&_)`}O0`)jx}ViKyS9kp$4#`)TLTQjn@z)NZ|c6VMfw3OSO`dUY6OwmcP29Ta+
z<U48-0!y{5X+c0}lr%<vGvY&xE0>bpdF5)+*y!HYHCwBi-)>n0o!Vej<Ea9nv}1ey
z)35qfXrsM6bb;D6c!-Hrn>@Ipc6~90ISL^+CT?}QtWoeyxnfWt3yt7lnPTTgPI1zU
z7&BDGT|Pz}l&-st(XC~%tqa4)$noa>Wlh;5^LMM=T8&h}C7r0Jd33*Se&0VCOaA@f
zd%~N&Gs#E!?7!c8;r&k}ADTR??}?sBPE4Mi`b6~Eo}L$vzdjXw_(b`$U;4hCJNOvn
z<K>mtALNl8FDK^nX78co_0y8a>z=-6|6iWTF3IG(zi*ex<h$Rq-DJXNH<Rz)$mH8i
zCUf@;{J%)ao2ru@lEL!Th>f>RZPG)J|EIUN>#V-`x_>O~#slkK#OK`a$q$C;6QCm?
zHn=_#h;Y?Ee3=&iWb`z$ggD9F9db$1;eE>M?Zjm=2QK^NpPSnF@n7Kse5+C+79_As
zl{iSa7?7ZNx?|zH=Wz|}gIl^>@x*V$lEkYhZomYZK8MYMzi&wNYh|Q5*n87JbbfHX
zM|U4+xd^`C6C**(>R;6duMyOUtteU+)~I)SE*$YL|Le!Zn2sI7@F_`C0yYmBBja?a
zGLFL5iZ?GM<K}t(4Q0{VgLj~-IFcPraN}T{&s2|355-N0G%U3Wyfcp?-5}#0uLi_6
z_Sy$)>!1H!>}8pUrx@P`_9}hQ#nPL_a*k_40*6omIh+bdlrcZ5(!=A^pwQQF+f(xe
zcqGkM`F+-GNb?+Qm)AtyC$g6k=kP!MmN2JUTD3?Y=O_T3={g|#Fhyo*O&DFrAtLu`
zRtn^Qrjj<_;Hq(wsTfsW@cbl13_uln8K3~|NPv139YFU#^$)g082{=n!bW-Jx2+Nt
zCZv!k52>VN$03(^41+($4-#Y#Pef`)nwno-)AgZ&<K!o1C)Y_}t$)V_xWbyB&&IXb
zuIHI|JYTIJ4_88<x#67QAFMfQP|XtheS?H6oQcHe65h9towlGO(s-`lx={MlEnK|o
zr7CU@H3_JQ=ul4_AnT=xEuuYL913>hb;{13Ot+@8<6)-;$e{gJt*05(bWce8sbx$_
ze3!O5=i61_yY_A`(`woYz;nn@&~@s6&SW1jw-Vv_B%a5sdfP5AsPLAuVa<j0v(sc1
zGa7NGS!6b!MhK|V*By1+jiu7U*ae~69I|7))RBWH#e<coeSQ_rFU^?Nq^Y?xh#$Ip
z2W08O8bdBLuw5!enn!0Em0f`osg5;cL3}A!sWutGFenZ9P0RrEEl^!ZBbie@tljhX
zOcp}BQ+jdJ)CB5dd%sG6F%7+H8N0=xeEbFjbL6@lzH}G<q=;aD5y9L{?Ev<-yZ6=l
zADm^aTK7j;?<JnR-djrw8^}N|?ry5-3PCOet%U&7bLuA{d=_(tpVJPhDq6a7i(0kN
z;yXp*##^9U+3t|pIJ&YFH>=l=J&jBWK&nzxXl(0N9X;aJSeTF=H)sgiA^PMD>!dWq
zPY4m2#m6LbQyYFn)dh-8>ULqe4S<2wPCPZ%SpTQL?T2A#?@p)prMsANNLwir?W=j3
z$1J%{KNs%9;Al<NcG~HHO^&ps@A$ZYRoMofsS4!PIqkGHYSDKl`Bx#rkRa)V3_P)-
z#3&NHNY3;FzR>Ud++P2^%}{Yj&sv$GJ)yby2E<WHPXg1y$kBLv@SEZ)ubQoZp4wv-
zxA9YX$d6jWTCf;Od?`0SB(IEI-1Yx`hidhKnG2SLf(4m_S0|*`y32W9*uW)`1(wVM
zO!!rf2J#erq<qu^qSsZ&E}Uk5AyNxb8^92g6F}RIL#G{Ur&41FlVzPGUNs-v4}J0N
zxy(KBupBgwZ-=x@$HuskO8S*ko?fkVl^_EARn!YpH+R6UC`O<VQW-|J5%)ssh_E9n
zJX_-j&wTz%*9v0a0-qa3=P{omjW6n_+n2Dwx)Mm%A{jJ@krR1Z8b|UBDq>lbnit6s
zUd1-IEWbpC*YrI{KTsp9G2C4yepNme&Zg2f!%i3~U)%YZ&ddXqGstRpkpyWbsOIam
zL+yO&yR-;ZG6&c3#pHJv<l#5>4|1{E-8|?tZ~0F(pV<KzRu;{kqbU!ybc;i6zmGX=
z#TUAEMlGp}tyV>~kR3<iAQ<F^aEP6U?x9IIC})6?SQ2r&sL9O=>-4>U`&-gH6>EC9
z{Xzg(g5dKO)79bhXIAso(Zxl*EBylV%XEVNd^pJ3FZ54{P8qb4PBdRtll%4L{_6Bv
zH922_mQ22=QPd}^>G`VNuG*dbRp;dNH0S+QyDB^Re5L6Zg)_tO<y-CfY5~HQCfk+2
z1a7);4m@a&zRg9lW=`Y*5V<<Nk6G1oi8q$F&mH^8|7|zCm=Y9r=foo3u$yPcbvaRP
zZ|2{b>(=)DBl-5=zTvi6hV9wO173UDISuks0c}8Nr+Q3V%-BFJyq`Q-xsyQZlZZMZ
zf;5AQ&BMg1W%)op5i=#gxaD-KY&CRcu~zzeG}UsG!P~1q<wj2C?e~7_?Ra!{9N2th
z_;ab?HyMtS{>%=0>ct(lH}zXVD4rg)7Y(}?a~xAVhDH1zTx#f2!5>;AeiC&8e&YzL
zBcFwVaTvW89>!d+%zw8Ss9NQI?YV$7o?8iaGlCk4JbvTiVfhbwmp`4W4;<>V<Gn|V
zBZ2y!CnmnqT#bf4PM`qpIl&fFM}H+d)%iaT9onUPkE}g{yZj^Blc}8~E@9voOQ!x`
z$#KI*qcfc$+~@~82c0ifdc>K2ksb?fQ~zpNMMtU!=kYS1n~n}WSJh^m@Q`!U5fC!x
zws$Y<g?Fn5-Y4#9+dvCT)vf2<_f$Lb@<;TahMN7Mex-VH?`IkZ@*UCR+8T*gn(g}i
zdZJQ)FF%mG&wS6f%0}{ZL)O)d5|!JR<=;PnZ@QMnM}K9zjYHUb<f}VFdx%%B$ZIza
zHt^`2-MSs;+L?MCjnaFB7d?(v4^@tuakTiS<um}zy~caRrRQp|Rmq8O3-4>U7v2XL
z0<>CPXtmq^bJ<eV`$(gG_|Sztz4z+HD8lMKd@u(bso?RD{dX_LuMst*!j^m<vZqc?
zw92pC_5QR>lGvRaR#Uwf8WYc~?n_4}J_3U?n@FGq0R!|>Re$kmC!X&l*n7JnQ?(&<
z`g2wNey9U^BEdYQEr2vwj1y|%lgI}SHoT31QTFU7*axCs$bgY%Ah<E4AKilucmUoh
z{w``7Z~aGC)r09xsEN28B8mOFd3<rF&b+2Q`ZI&}RAtljhrbfq;r3rl?Tnb^L;+%`
z)Awmx-!A_5)ST``^*>P2C7gv%!p1X*eFF@D(W?z@(1e0+FJN_<X%*+z)-{!XS?kY+
z7hqi)K-uEVt#qe*^_&KCU{E^VT)!<+?8I)DVN0b0+3`Q&#ToY0ABEa%zyEtP_SB<U
zYqWDdSHp{$E;ChTFO?5h>QogvQ)`rYs`?1yilX1DHg*MQ#F<LP^cQ|J(@{Yb;&<z0
z<m~8M5&&+gacc`G;JFO8fR8+S;hnT%gvWh(ZccfJ4@QpnpgxeV|JpxO;Xvl>PIbwy
z1ol(EBN$To(Ja-m9ge0@t-_nKbTk{#cA|7bP}x!y&+95)V-B;r9casvW$)Nk3l-h@
zd{w7wf)3KkToIj1W73h~;jLh@5no%tv-j%zw63*>7Wa&1McYz`lhS!Mb5sva@k={n
zwsOjNd*->cT!de20_Ps@9GJ+<r?%SRQ1d#~s$(P#u@b2d;P8&DPA_3QYFe<)c1pJX
z(wabexy=9$OOW=duR^x)3HZhUOnjw<87^kz_Kv_Ivd)h#ysv$`2J{-de{nJJpImI$
zZr6`4z0ZYhdTz+>z1*CG0krn|+<oz<QuZ<rL20ILXsM4LICQj{dLaw5{DomVzAv+v
zzo<sPl8&x^6hxC9p3Zs)Rv4oXAFqzmBh=6nZF_V?p<v)pCvq;%1B(c|fHWAcfKrrT
z7RG`A1D<rETif^RsbEFl9`2}BKN!{)qFWyU?s+LWp7|?V+y2W*%X#lVaTqmKy=@it
z%1{Z@l9nEtA6DB(?D8YdXg<sgG$V6?(UVWr5*EF_nA#;hfwI6)lzz}t(=u6HiUB=f
zyNuf-4meVgItwke;PyH@T9f%yU=6Zp^=|e8i<Y%w>o8<-H<h{NV{g|4MEKg`HNqv}
zP3p~?!8Se~rSXf0w&113zttZSvQ;EaTTxpxD0CqleO8-+0e)x<A=oi}HHstHl0g45
zO0>}ur*wIZ3<&~$E$cR;0>m;LbV&8gYuER@@OPg`UTNQJfSd8Q!EyGz|Hb_E)9HJf
z?+3U!GydTd<=Lq_qYL0TAOGd2F1S4}-ueU|+d8iT(-_2q&sW-)ySUAGy9?y}|1cAP
z8-paJhq|@l_u(Z1>o*S&4)G*}zjA=LbU(Wvaz<nnev*6@&_NDx1<qX;(p*sMAN%J%
za>EhVx>q*NVz2#|9;tfuNA0RLOokX>cqHe~WV`c@g(%hYT8FUUXWLnOBE%>ZHw&Wh
zwo5)|y%-U}_`^7iowm?EUDb%+07IzMg|^?i0b_{y>Jy3A6I#B7H=P_LMQm4D;<d-}
zM%MW9-nWNcJ6@~$4tsiz%<<)C^L+aaie(Mdua3(@kVIBkBs4s!+va1Vrj^3pEpBKB
zGqs{kfCD6%;*x&Mj(|k6+6brN^Y6c240q%29;yxD&|&fBEtSt6B8<UGHd}=T%G5Md
z|2QKu2!TYQJqqh|6*%I`i&M<c0vp~Mk*0BBfO40c*yl5)lQq>RzVNMu&5c50z{xie
zXNyc#mh+VZvz~F=8FJ9{G@_(sFfvYr8fjUAI8ahj*DzM|H6s#=Vm4}BAP`^vnQM8d
z1<j)}#hqbhitSEb)JePz?y`@vZLksQj4xQ?IaunY%3?CE<iW1=0n}0em#9Pc5JbUP
z_s{(IH&6|l$0zPh4H619<dh+q3&b#in<tb5!LTkQ+p<F8RDi)A*W3nxzUbxq!GAo*
z6Vyy91fT#`QYHJrS6VrtW3W>kUWw2^S}gza&@P6YT3E8dS=|n&Yz##`8fIlV1fEsj
zpQ;lo-WuVIf&ciPuoRu@Ww0P|r=6Z=hVAQD$(E{Uc%jw7#Hd%T6XkBKe9ECB%+Xhn
z(mLN_HXl!62&27OG-}y;Nw5Nk1j|r6iq~=T2BzC#AuTAZWdt#G6pHz-$_gEBldBi!
zf)4nWMvZqHahXS`m86s-w(oh80B0Q|&ZI1}yi_e!WWaLBAn1XJffjc9C$aKqRE@8#
zXPZhyO9DSOG6F}6NLo-2qyibC8X`L;7JNPWTQP{^=xNC-6hlTDgXA21H$o_hq5Ysp
z3LS&7SyE(j7s!`)6m1kFsiV}UYy}Z6EK)yzpeAkZ>wP1+#;YH&iSwaGV7EnP=d=7$
zD?ArF6+L`eBS)IRD(xn84T!BQDa0xbXIuj}Nn-xf8OWF0SzF3&{^`FVn4uQKEMbm-
zG#MP`m(F2(DcDck1S7HI92qE;7I8+u<oK@4o{49i(RZqBUKM4uRJQSnt8<eUBV8%=
z9&E8|CIZPbgQc~sW9t)7*T%GeETVA|*+-7uu5u><?hLg|0@)x!*GaoU?{d{f4^`v^
zewJZK6M~TAl9pwJlP+Fxk3)oBQXG_z4q^eCVpY0S5MDx%k$I^XF|W^2#}-<y)oBJc
z19}s~VXEdgo58VmEKxbBpV@E>$%0Rj=al7?JuQqB&Sez{WNF3;uqOh_=t&IcdKu%Z
z0%0k^Q4wEBJduo?NT|B!W_R|!Lx&<EI%!G6Cj@xrnwG4CjdwHV0fVE!BGe8*CXW^Z
zcG9M+l7@qzwhHwmLs}+9pb;(eSvl?}?zXuyU~r)2RJcYePBb5b4Dc@YG+)Kg)$%E|
zA!x%?%BU{UN*v~ze37F&xII+9Lxt$1oPBBpqu}{^Ej=ICVh80~N<z&dbA}{j1JzAF
zMY)F#bnxX0W2U4O{*#W$GQo?{s<2j}1~RE0Q9AGgSM^~l2f$!!u9_bL(d7f2h67u*
zR&{GQ0vdH%yR$yF%F;&YMM#~(ivaJX5eVs!UPX<7;&A5M+Lv>C&<IFXlxvlE6pSsx
zo9-crlk9T#oEg<a1sGxEKU^NE*JiUAfJT_5@tLYMBZRas#za!b*ycc)G%NZZ2&U;R
z<V-cGB5aIhxk_xCkW92Y4K=IP&wtL!hcBh+_CqhSK2Wy?Si@Pbv5h5fB*deeI+}k@
zzp$g}^&UF8_^WCDgZ3Xb>0#xHW`NeypfLyYd}o!ffq^tmmOWMDBjxQ?ucuEY^9M?=
zldM%egix9U+p0mr5uD!rdL9)9tOsg2-_{R!50sTZ4KsBN2r}2~Y3^&HZLD~;Ir2Gg
zuwgH2RyJJzqyN><y|lJ?M%Fpz!zWi;=?MaHYLj-k60Y>k<(l`x?$1x<O*d%%uue*L
zE=5VSr`G^cJ5JV~jP~o<t+O5zPA^rhYM|WT?456x{(gP#fpT&hepa2O(sO6w<7{>C
zAmH|Nv{Lm}1Je#MFHUEz0$VPJyv$}KWXep%y2Q>=r}eitz0d#8@2GwzWX3kgyches
zV2uRcXjIc@0$cxVs`S~^#No)LDNxG&+Tb(>mvM->Xb>RdO%h>&5AYaK125*^u8BL1
zsuLyUpD0W0?rISHs5lQ~)9A%?f1qr;v-53<F*u$le$pghgML$-NEpqT^4K<)ymRH3
z)bP1<v<iEVRcE~)m}u$758VBMB;sv4>BsY};5C1L=MUOnTKd_1mmcjrgN&E!>7f?W
z@%|AWV9T2p5X>vpS91q^=a=<-T0YpxdLNrh)(GTTd9K5}{I=$U9re&!4id1oB!M^Y
zTxxG)p8h{nI$QVLGpmCVpffnH*MG_@N1_wuX^@@{$O+!7_=%&{k4Ncq_-ksLJ9sR+
zDN#yr9s)wzv)<t(an^AM|J?^vF7@cc5q*7lI9I!ImTwGOjFzL-?|IjiKfTx*)rS`s
zvv|B4(xRsvg{w<dPP6ZCPO^tkbN3=^r@TAXikA<rfJ5+ZfRk(RQvzHb^DcL)gU&W@
z>Pbz|&Apxd;-gOC!OuS^;Do?v(+++&8IN`l0l)y6+y^6ZBnse@{^ec2pa^Wz1w?*)
zSZBvGwr8@3R#Wv<jyd!DnLYLK^oDpf%N1*;YxK;~iufHp^vl{QpIXy(P)^-CQu%wD
zr?+@)eo(1jt&;l5wZl1~EUg!*&69e+hQ&`wgS=jK4n`IsG!Ni_Qv)Pw24JdUcp{9#
zO|Tk?J6LGk-h})_U7WMlfANpijLqEsXf-t+=Im~<m?>Tkp2m=N{1Wij^E>Q#q#rdW
z3KB#CM?Z;=cd~dtx_Zi~&vn#opG<@-kclDQrVAJ#oQ0l;$|D)9{%ZcDu8vgdV)YoP
z*m>Bte;#C1C?f+IC#ZMty-g4Zv~utFHrJzHW?+zDk<qHp9%b_*n_c@kdG_M=)2!ZM
zVfor{Z*4tG^RlEJhiu3{p4Cs1_wf!)N?<`lUEKOu$LW1oi}9qtRKYV<^%8saP+nmd
zJSdG>5tq?$T!MZWz=0Ya=93&CKa^^(tUaO`fk;}AO?HIVtk3<SO4GP^uVAmV6YrX}
zLy&9?f%?D57+;>%_}H^)3`MX9Y&Jfbv)_YL#*2+@%r0;99_%1pCv$ZcljJ0%`-F0N
zmo;-6rJ|T$1=%q|HcxmJ<I}czMg^*6c-0j#R-|bOH&LI0pjW?F2GN^<VGd+@+!hS5
zU_0C)yS(cwwBgYm>Z#xQ>Rei9C)K=uhwQe6|8AE<->JEgIisss@9L=+G6z8JpmVCT
z)qWP#aI|W}E`X}j_UO~npi_U6gThV`JT_l}(lOe66#!8HyI9)Mw|u508*07T#1n#5
zN3!*IJrWa8Qg7=dt?AK^MWfkWq5aegscZ$WcAW-F0^eF?Z<L|T_Ewa7up|jhxwdOn
z@e+~v#Wg2};HU4`wtM!chHMXT@c6N)WX0ZS_JfG$(}i`mqdND4!u5cCm6-C7Q`TY$
zTY;Kot+E5g>K(H0`8(_$i=WW8GL;=WRLl7ILA#_If}ViS{8Y+_Nb7^aj5eeC1dTQ~
zTtBX}I%IfL$Fy3_{O8shcIRF%M4BrhB-f4OdRNA@UFL$J6c2l)e*%3zT{_-m$;jA@
z=p-KdwIJ9~bC7i!t7>*GTfgh?ja6by1iB#@zO!pkc5h>R7+}#QfX#=uVES;!2C=u4
zE>D*!a!?0wDICF!Ou!A!H$mlU%!`W1MB`wBj^KfdManP_zf?0C#R!rxc0p;d>@Y9v
z<}=^<j=uqE-oTu`IY@)`MbCK4L#!4eP_S_&iI}Gw?lV21d#(GZeE0cZaJ}bp_{r|o
zzveml%hIj?^0vauj$epVr^s-{y<_<l#(kN@;<Cie4=3BvNEorow{eKE%E!<Yt|l@X
zdOAr)?eye92LW?6rVdd*)S<wIOjzN758z;T9kiw}a7HY5cM};_aY%?u{qoQKn(*d4
z3$O&a;5vk|zo`T|QXW4tZe!PHT4r=-EL=$^!356;?FS?R(NXwW;<6S_;^A6gv)~Ah
zSgY|Czh%W50?WF_x>27WzCO-UPsYYfuaqm;;+|dB?N*tca%FL9MnM^FlA!}f6MzGr
z7b{YZ(iNtuVnLahW~H0a3|PxnS>m@yt0*_)8!c@M=Adq2IfRfO3!uSK(tYVNa!C%H
z9;vR&r1Ny*uoxt>SrD-5)w9g5J0lhlPHtzO472=kpbH3huuAhoc#kMd*CO@#e|Zg;
z7-K2fEZoK|D@ke!LK9`HbW`qe6_19-6JJVHfvLc<EYp+{_#4B2jf?|H^YB9!oXJt@
z_q=Mpa02zIXE=&OjB91LF5;u$)Fd=f<_)pbk@}3S)HB{4(X;BYX)`0{vaES1zhGr(
zH!;Cs9Tb$bEK1Il10muxLHHOzH30ALZWamYIbPtX7N-+W11{q3LN%@`UWiu9Tg&2z
zc3F#QyB#YTa#jiAO0?xa44O8QI6eAEuDyD`=&r!>F<sy4JPijZ9ELD6U(lVXX>XXn
z{^H|OYSJxQoJmpSn+FdRmOO%7GyKXOL@<-4LCOX#?lU!ppn~rxx(|mo&zhzyto38>
zH%-B{1didBGzB<Yjhk=O3C<hGYp~(O$d8Kmu~==aWKFY-*W~98Ic8~{DW1@)E_tr>
zGQ<wowbHNtG2G?o-rGpQZz$b3kY{P{#4o82oRoE9<ZtTjzZ1$?tt)5~&q{qak3Zi9
z1y}N;zt*=f%O%O+rY(^y)C>tDzDF7uCE$Z$(cmn)<(e;K(azLLq-8T#9@pmk=YPHC
z8%_w8K?6_O(&*xa#srVhHzifVc@@^v7r}1n)FP=y!$`m%l+fo*Jph3OHj_F?ks@_|
zOAbJ%^*=bob@Erlw22@~X2`juBYSK-IbsuuhMV7TvN)tB8r?-kCHGu67JsRMM=te3
zA3J=a`9ze8Qs|N{y8bnUfhLt6NQT|U;#*?cTrLTO65A!z3YA)Vfjk(CDus2XZ|DTu
z0b;ucB$x_$>dt$v<5H>N75t*Ql!XH1VdPv21NPqFEi#*RACJW{mP4x1J)~i}Jd)~}
zgQ8!3@g2ft$%PzgcWQwoo2u|Bk4xRObYU9W!E=QVY7+HGHieudQ_&0EZyVJYl`0q9
zXMYIs+N6(`AhWA@gcWSq#Z!J+TAGX;zyX>I8p+WB#iF*zOK71)Ih)UC_FdB!I+N}d
zXcXPS524#gj`>cN$P?CPA`B|t(k)Tcqa2b$y-O9nk3&v{6<;2FRDPKQQSCNsNtc$2
zcCV6iGP$QoK4jU`B(@OFa8Ywxq>Xl#GFUyUWK@&Oa>&nFZ{7R2&k(0Mm}$qB^hS<D
zwia}RW(Gc?T|qUBqM+?#uzucUs+YZZ-Wyx#nfL0N*I%L${d+w&0nqh|1??zy<e$OU
z^Co58m~1GJ)Wam?t+nnfFgo{WG#7Bfnr7ezvAul%jYJhu6%7L+5)y`>Mv7J|SO&=T
z@!Zsh+Q(axI69(Z>gv)NPVvHudFESIR{(0+Q^BIQT7IMAANa?LS2X54lw~s8EWI-3
zvIU2b7g5Ko;I+K5mx0*~{6L$1{hzd_lx_60xm}znOY<M^3b3PL&w9)ZF+qT*B&OBI
zA5e%`TWCrxS2lif<;q|E^29T!0C56cRt;FA)w`m!Ji3~VE`3QS1IMZ)In~M6Ks1=J
zV6YkO_zjY&cik6eWi1(98stS|Q|zbee&KjEQr*k$`>g6|Fsohp77-Yu(?RormR8$(
zC+&e%ugrFL$`L$tyOa@bD?tqC;fI6fG;6bY&x|d8QpeLH(aS*S(`4koOb7e<LEHE)
z#xKOxH;%NpuWVWkfRGS5%dm_@*|ICi6wwoUB{^j}kEhO*_{wL!;z)&(#T$GGgy^Ez
z@K{k)s%Mf0B{rL6w!(16dyPQ52wbs<VZuEtL6ArQm(L<c>)*jHmZW^j7XSS?E-3n^
zT+LJ_>KX(DyM%6q4o}o5*Wh9`H4>hH0GTE-y+9a^3NOor2A0D`@5pM>n_w{Vjxip&
z=&fueHXu*L+m^bsbQ#z|pa*m#1mh{5lF;aTe(n0Pyq+JIK3EO`17oOW2BY4fLk1?<
zC~FkMj$1MD2GolhDfKMvrw|)~HhNo$!@`iE5nJmbIX;3K7{hMJx6%_lM2+PZRKC{&
z8evWVwm_`)`Rv-5mKw5!v%)BW`l~67QD<~*#k7J=Ia4SZyJW~LDV}9J<<ypi2Ch3-
zL^9+Gv*#8+wusIGgcntAhCZV_r)2DRiEa@Ruyxko`zN9n74O#JVbN|G4Z0>25XCC?
zEbT9xCr45YK^qs?^!n6Rd{fdo{E1Y+u#28W+r!qwi6wvoU7FkA2&UoD@01C%sXl=B
z58aRRFZHDyO2qHpYSSTbq&X?|)Ey%#p$(2nWAH_M@sj^=AFF*dAKJn<X&V+_Jw~}P
z$cZ$?RKC~%T62f)SXJzCbJ2S)KSF!0X43dv-^OYg8B<J@6u;;j7#2W@cmCKrcw>`1
zL#!J5aLPT-TM*ggN?d!1j2MM8G-=sQp)m5H8t@6n9RUUrMb=hKEtvB|yX0k!n&U!G
zc^=qf?s!jak=v)(VehQ>6oi+}{qV;%{xIMq@{CMtdc~Pi{r10Ni$Wrk3V1hEx)Qqt
z!ma6?Q)?ZyLgm;tV#_kg>)BK-$rNrqJ=R;+qLP@QmU{MhVT1L8??dVvIs4#DCtL0E
zX{UZiM-2frOf~K41~md0U<?4I5b@-8?u;P^bj{|Ou}bu2ha9O-DnrQt+CdSaA;Wg}
zmJ(or3eTsg)UlF#6s;M^G15_~&Hap0vnfnphFD__OQo6-SpbYEiPu1PGAqTnc+28{
zn*}#-TITY9ch$~+{Y<`b!Od&>H+}lxUwRnVUwF*Xg#q3&d3^cr|KwZV{4c&?R?*P<
zm@(||XRjig&5RLRlogH&0!o%$dkylKw{uA;gDiSRqn^ybZMtU$<s04x^Whd=#%4{t
zvi={BeSg;#!L7r;GFBF9M)aE$V2+~U$n><#Jd1Hg*%GkAXhFdyXHfzizWn6WJ?fG5
z%um1Fn2?Nr7|g6~!s`@Q1ACZ1NhWp-2iKrqTPAG4crGRzb1E>^L~Z(*OC+T%WBy?h
zS@qZN%N3J)Rm9Q)$%h{TC%okWA>!)eNlNLQ#xfphYCB2mA)daSCcfQJ^+skTW7$0~
zTo)vhjU)MXXUC5vV`1m_(t&hkTpjk#PsEq<16A{L=Tdd>lissOS9P$rV>L!zclZ0}
zj^wA(ucl@CTo8q8j|KG?F8ya6HK*IxKARqo*4?BEg4L|CO|w+vJB|*gm-2o+xN<3a
z{Pr@<y<M;0Ts5aZH9V5AnbdP+9JxJ9t;R_1n8fMQg|X&GzI1H4>^+wcK9}CXYQ?_F
zTl=l)YX_dfjEQzwH_x>u|8#MO(r)9kFSLooZCz>)ug%3PL3&EB>{kQ(=9<$GKJxD9
zId^r@CupK^v)+|^vyC9!NVu*Wo!V?Vm_Hn`PH=A8x}~wYC^<?(_3l<Wu1Bhb9Noj-
zN<@~LERU)Y&-o?^o#xI*npfv|?XoT#Hzjx65T9(kl)l)ufB3bxY_k928?wC;qKkYX
z#H&2cw7$ha&H?IMCTv7TPXb@c1`|YiLv}Zcq34hs7r?_O*ytuGU$A33KY2(#UXeKE
z`e7n*j2mJyzTz_&0p(J;ks&>TLr(r?$1r!K7i!#0QT_B3lPYM&ue%3TMi=gOzKo<L
zcQ>fVIp)22yl#Tc?)ilHH|6VF;;EaJQ+OL2)Z^F*Sb-r=PL(xD+y_3fZkGBpH&6;n
z177iGTy6tk@I$&K73DC-5+NOooh`1$HgvPA4IJe@gOgsxLC5uRzF<MBXbq}l7W@^p
zQoG*zUmTb0yPe(SC@J3jGuz+{o|mMcY;nX4K`6L#^C><xnftZ+lIuQu?j7WdX<*B3
zMp+?O{I%|3AOrK{M&5LF7W2V#an;CZ1*J!B&*of#dh=8%8IaGN`%R`oK{t0Z&LSu>
zkDyDVN=>;<ig)Wq;fNF&NfJ7)KCb-!+K;@A5geZlrj^THr%cw6F|Y;xz2SBn&0AQe
zV0RGWGNp>dkRiEtbAw>f@ZAGp1peCF3EGqATfF1q2R=#^HIQ#zqM|GjE$w5!Pg+tr
z>|m({EU0gR7U&ms?1?f4+*He=<;{V1MdtMe_ZT(0;tRPfbWzK#i@*H#ZnJiI=P@eC
zbFsY&y^t-9E=CK#x@uc4i?kNf2IL~lLRx{z-smA*<I?(TACiouBwCA6X{?m%rXViH
zTcuet?wRO3DYwTKC-sd(%IVT8r5Z9^$;7wT-}6&(m_*>v3`L+}V=KNm;#R_4fMOwx
zKcq|!ZgH5APre{7g2%r3C@e)^Kq!M~p%wYBz4~r?SE=!#ozi6$qXpliM4W6cm|U>h
zh;Q>SL2>3YsP|;Zj^!`QlB;sZ3G2!Q)u9;S-z;6vZ?&!7nqT|;%?KV$DP1**E2>0C
zab&Sz8&U(dRBmpOu*LdnGb8te4edB@47?<zmr(||1m6w&q!gr_O1eI8KelMA!(XeN
zw&gL&yPGVNu9G1^-Akq^gjZ$-AvZZ_4)PKa)rRzqlp7yXUh}<E0+s<*nVcb4+L)8+
z@bMjB39v>byEi2=>0aQPk3eC5z-JC>!54#Of+=v9V>jsQ#b3MjHqRa0<MpsfnVNpM
z*=flxg5|?r#{!t#jftF~RdN1ge=EMwp)lcBrm|dH=vFq0Da%%it<c<q)@(E5@R<{!
zI4b1hlTyFkGO>cvl~(elY=#IAu%&dT%g4NS>q0A{#1FY&UaTeH#Dgtyqi+|61Kdcg
zBAb?fr{|6WCW+4Utrg=ffI0v`BrC|nNYb20n2d5q5}WS1yGav{;h%JcT~Kf7-{iBg
zE>(IH{R!q5Wdk_2Ec<F+r`6Yb?c2V80oMapkpa-)FoMNw{1@<sNt%YOOP?4{i7?rS
zGSL>nyW&qYDPBA%*90F@)lC2g&_@0crK>QTE_lOcFtQ<xJKOr&pEB)H99i>|%5tZ?
zd&7yw1AFkWcisy=aMKa?OE}f>)_`!5x_3<DI<xQqO1}pPXC-=y4ZnXR19`z$+^v`O
zsiwW#!{=r`ddM!0WDAW(fLr99?PX<M-RZ(Ngn`oEN)bNpMoOTYV}J?w&H)v@M0c44
zxp|58=L>xg{X=>8+qR}aFF-J(84#5?|4(h{eb_T#4VY4bmkxpeVS*))R3|dsK4c?+
z26M1`8^>suA>wk(J{5xL;1<)a=C3>Iz&8$0FdpJn1yy;^`_zu~tECm(@<%ri0X6;D
zR^&*WX#CsV{C~DOlHqZy(Y2{9upTT40?=Kf(Agybuqoq@l@vn2D7#?*nING=WeDhC
z{^*9fTQ+BWd?vG%KsA9|JnrG}?|ALRQ?qOw<NoUg5ld`m0TDw?fLBz<14sc2Sevq6
zO4!FwPyuq?0)L<a#w9+f6VlrtKZXu8fmj>8aJgH&Z^^8|m1DODZUF=tT(b~NHuCeq
zd%w5^<AfG3r$zuAFj#QiM~P$UwM^ZsRkRn^OwkhmFh!sWp*Y8=ES2Y==-xzP2fF;1
z-UuS(LjfoWRTqp-=`Kt~VowoPGvzEpXD?g7w5^vWC#~RX6W_Y6NxrK|U63P^yR<K5
zEi?pD5iWE}stSh$Ez(cHgdxY!Av7Q~03k4>i?476;iKt*<wP6H^q73mK2Qf#!8qVK
zJ81g46Fu|k>)Czmq4K#-Lf`_i9nMhrn0Mr9s#5}_%z97V0VhE4SfY~|tV(3az)VP}
zBAGOW9LRx%XbNjY4%lc0$Vj3)+|Cg=Di{sp<?FPMHvACYNo>=U14~2=1}r%9U)#SQ
z^z8#*7+vjFX1W2IGkUByI5JW+j*k$@@N^fXSp}pKY^(!&r!qhdTg?s&*g4_=DG7=u
z(3nSrOt01KorE6N_RJIfQx^Ang7VNq1f(hX&j3)i5q%(>DIk}#9g-ZcB4&79dgg0u
zhXgbd-RA+~)DqmupBnZg24cjiXIr=lKZWHv@f#p`&k~K2*~=R1skpZZc9#?<kke)_
zixR+ZNNl!TDg6}$Pm`&{moVI?AfZJ9E<~SU<^Nt!{ky@jX`?%VZpH+IF?tj5hR_sZ
zLrBHQbp_a|G1kuE8=yExM5)GGZBdN^a5p2q2z-OqAY{V~cu)*{!v#UE{1uHdjdq+U
zQJgBe=l0s)1atf~f;o)jzs0FLRQ?sn&Bn7YeS*gLtB$U{|5v3_>cEc|YfYdAanq0n
z4A?D#f)K-w1tx#8b*53wh=4C^6G%3Q{9}ij?N18KcL8w_Fk=}>O~l?q+_2EZKgFgD
z{F)vu@BGL120<uFA{DOkMoaS$1++xO=>QZeAKlDk;s&Q+<6&iNNFW?BSXD<}U%~q<
z?;u8m7-(ZS%EOp`n1cp`>Q;n{hCs;$LB=blI-7Nn8c;!VFq;}#Vh7{$nld4dM?0_0
zgb-JG(z}Ji980|G6~HGm<;U2^d_gR3JNnKX8MaXO8@iVgx&=|blHz&ZobgtINUeWi
zZgavFpp5AGjXWS|<J*;-(AvJmm=?2{hs>Dc?p~o^au)kf1>NMZ2XFC5uR*#h!NFX7
z1!j_QOU;4BX6EB*eKjNs=nBc6>H&km&?G2>QhW?3u_Yz@F1y62?bd?QI3m9t)YReM
zdmG>zLkw5M9!@kv71k$X5=*X~oQpn9Un*!6hm3S&f=sPqAQvo^BFq5A-_4S5e1TMt
zIYP_?^I%ca)ad2wOcL%<18E^Sn^HHwn+sh&^HqYST)>6y)vrJMH3<6om%$F;gUJxr
z1SFHZj2!5~7O|4xCe9*TFiz+iqmG-RDQgDg@TCy>YA^!IByTcW|F*xy=hX+*H?jan
z<g$5AzKF02i1Fr{bkn+W5eArJ{dbOag@{KBBtpz%sE?U%l}v;(I**}Ogq03rGT#)a
z0z%D`CNn6O3vw9Q`Sf4B%{yo6K^ktB%mY(*ymK;Puo6uHCxjW2A(u0LnCH#OR1Hz#
zM_09xjU4!){C&qZil&<~my9<=tdA+lBtRRWkGgp!LXynTs7-`HE*L^3yG^l|LLgg{
z^JFbp|EFj81p^FArO`Jbnho-WG4)KB*r4<zlN;HZZqscAaof91qof@S{aq2e_}vnh
z1_cdK0KjaRjl`PZF5~hi@d)3f?5;6M-u!iYi6PN{69#~|cZ(ytTEL%Q`|?L1Xj3hi
zZ>Crp)i9YlA)lOil-{2Rmo^2KB%+fGsS$tT;9NOOgC72gYefpAMr=uB!SWJCj`hDG
z!F3xq&vYT=MBHi92yfsmWXjq(BMXu_P1|KVrF7f$&YQjk+PdN(tp+VuD8N5A-{U5m
z7zlj{lynCkesCC8NUmHbU&E;@HPGw->La9q+JrkIEE{1Rx_cGz6BfzAni6rjH;Ute
zAwzN!+D+b9i`sjB4Kbv-VdNm<P?pKQ=E!q;k5^7MHa0nv#a<b#8Dd@!jt}K`$V^&-
z2fo@I6t#G;OmypE85<LPaG_o3F!7n<=^Eup{m`9o-oyfOUz(&`zw<r*H0qmHgy+&j
zi-cXdCM_)vw;a@2N_HeruVhCk6ex+w9H)OzbFcw7sVX)c!a~8Ko4IG2xI`L6WAoo{
zwahvogQKWOtB7~>{#mt9`V!>W4Q#Nm2B&OsxX~H>!EQ7zQeZr7KKK(WQ5@~Avwg+W
z7Rs;s6B^#QKs}3~Rs^XP-MM7-WLsEABl}o{RwLNf=)GnrTyeid(0b>{+K~OFipYkk
zJ63UT#HDpL`(4!U4Kvnbtg2ArB=Gw7;9`#@is%QKdd8m_x#D8K)N0uSAvXMN%!~@+
zfPlc4veCNKh?LyDDPcb<hw0r)ZobRu9e<t|1cy#S(<b;@_-R97i%dHWoF}akoI2{x
z^eeEu@n^A-#O0usjk}2taTvE#b^SWoTCwZZQ13Sma+L#*G2s0wXWFIzTKQhE5}bM*
zhJ;r!vhO8^g#A+4*g}_Iky3H!h=mYi!UUdTm*Fl+L*NVzF%zC$@u0Y13Vx%&&2Ljq
zq>7_e>A&))-?FWF+U`vx%dYB6*u=qhy==%XmBhNo0`_Uip9yrM(Zw@Dyy#rqZQ{2f
z#8kx>E^%DxpBtr(Ry*3Yg&@$);M2d24ks`IqDd<cvMZLiDlV!7WM(o&NR+}T9ufSM
zZbdZ-GaxKfJal2XISNr{a%^x=itK)clXRjTKeFo`M&l&DiLp?yl0qad%e0)VzCd4q
z5ag!aaQVnWxIUVhdKn&yFD`#_pnNvIN&U>%DJS5?RaMP@{H_~rZ)Qb8o5TE)2QsiR
zfQlhj46u-a>-e?2E6*-zJzzWfFB6iux)6u9^9C(JX@n;tX&?|nwB%!sE<d|xX#^Z$
z|7fNC*M9wLr+AI3Ks~tdo{JaAMC26fD$obd;-ao9R#HgVP6xroS1W0>AEce}X;*;O
zZ5&909~tp(_V!8pvG=f<qL(=X;T`qf@GhYR*H7#$T5J8EEs0Z$?~i%y<001&leu)m
ztCd@X7D&|)lB8QQv;4lr(w3EGBB%xp=)sLEnbR{VL6fH7-<8YakBg1RX?-djD<P<R
zKd=aKm`}MPK^LlPnlD2xOC`j&CLjaZ6i*f_QnXY7KR3e-ik9(Lnbt7*u@hj~M}F3T
zCXv)KNZD{)MgP+~|0WROs*Oy)X&^#ZNdF(4X|wLJe)`8Yzy6h<$zPRX{e!<*<hI1W
z+lU}>?M{7F#&bF+kD^>T(;wuJuefjs$U(3;hI>m~T1HEA*PO)kQ%D}b36F6KlrG<O
z@}F;{K=_$wMbbEQ0rtGvTQ}}2KM5^UIHV{9ZSy+CnD2$0C0`l-pTD58F-#*!H@1ze
zF5s~ZYP&Wc356o@Je3&2Lf{4?H`B@3FZq|8IietH;<&u}le}F4csyo>HWVMU;<+Yf
zm6?&~mLYcbW?|R}#-t@rG81^z4CCD#zwV5`8u2cXv;WG}X|q+y3%)7U;uAL6!e%&N
zm}}CIuQBhwF1O8}k$hSI?=-a((^m5Cv9WRqxacO~8oN+39ufk|6-*#V^-OoqsF*5B
zF@JfvE9HLU;ny%zm!tJdKPu0f`zz$rZ9kW71x&<+Psy-zmYE{*2Iny56r*m;QpgsX
zjDf7&tnrmXHY{k02-H2l&$O>-E|I?&V&6z*OV&~^au9BbQ_6?l5R>vs%5VJgwL{EB
zZDb``Zye;maX_s^3wA}*<Wz{}g_PQ6lB+&Z?nQ0=KOf&<go!hhY<a>{j7#Q7<Tr4L
za!u3VdLpHgO8l;`=Yfc{xkqf|r#J43#Vyy^altR8s^Z~GaLWi0_hJ~cONp?^Y+PcP
zMLS-}<|=YGzlza3%a&Zy42E=%s3Hb*Q}98n$L1GF3Or%ygNZyx*l<(4jYJ-ht}aD<
zlLH^708V=CiQh0O5=Kl8qLsQ;Fi#W~rV8c?d1qXv|3E!R07<34NX}h(GO4dR1vCRt
z)pu3bD;!x_6aWW#mgme_lE$`p#NrJzh)F()&*Yx?y@nD=@=XuZI1k-+Jx?H9%ymf>
zT@OO}Mgityqrps%C+E!kQH`%}#y6D!OM>9b2StFcR11yLO+z#CMMz^2P4|+V6I1A0
z=3BJeWcU5QK!#Tyf^A(N3F*LJF%c6ZGO<ZGI<^afBWu8<7?ulNdFqWK-}u&*^}q8w
zyYUZX3kqQ)UI2v3V{oK<0I+S!hG@Vp#Zd8=9CYpP`X9fQ?x1O9*hkJhb~P~~VZsg3
zO@fb#!^KZd@R+o3c^v-7*U!)$a3xvg2EAmRVJOo2rMPe`plrH>CE@vq-B{uc?rDzf
zX&!8>HfNhMiXos$Pm{e0_BG{}q!S><Z{eE4&9^9-F`@`~>q_w2ci#-#DH)(q#)mj;
zwGw?IsfQ194aZXSY+Xx-+6Q?VSWOnvH2mt(bZSOGcW{NKN(QYuOI|2Xd`{_T-{kOv
zb}c{;KlIyg=RGV?h^|Lsul_^cjrWN7Cr#bj_<z3fChxQN1RZf?^I2GYbxT}Tu9$ZG
zeb*~EKdS}YVh_dhjqlkP_MG1{gn7L4M3xPNNw#PlM&zX=oiAQBj_2r5|5qBNi^s6d
zJ&>_Kq?x?Kd0aAX=S7d0_f>zTi3v;w^;UX*4|9BhebbSyi@D)`!jUTzytb10VWl1j
zVqWLy|A+M7;(Xd{*vIOFW+HB#Ohe(5WVi?!z=Vi{Bw^K`xJfdVmiR}qA;xuuBP8yx
zUna6g9a@8_EZB}OdBvHziWS|jKK_|fzx1l)d9j&@<xF8XO=tw7O=Qys3LdgiLPCIe
zn~9mb;}aKkW7du~#t&le$V5Cf<0Ex<ANYpy<N`0{<<-bc-?@MCQgR~4_t_{HfBT3O
zkQ8tn7sRFDF}w`pqhdjbZp<jvR8<rtK3fcjOeq@<;Ww7JgDNtq`Otf8X3V{wO!Q}+
zS_-BvGmp~uUrOl4GUCXqEbyHRYX}0mwKKE!!ceK8B`!ZK={kbnSeUuOD?8TT-H$2x
zEa?-H(s)9;Is398-9*1K0*z+ajJTde2bg-uY%KLWfZ0khUHIWG3c<9Ha{lZW1Q;-|
z2cJ;fo!vz+XbJEg*MJiuJ$Q;DMYLnx=7VOE`iUb-n?KgHHk<FQ%G<bZTJHPKh=VCO
zhfqvEn7Y7xuF5{je`FCy3ZI=6T@RJQnJ=VfbHgYnd5a3Q)3k*xqgh;DgO*Im{>>AN
zT#)#1=^jd(Cj9dM`L;Kl%j{SL;be&oC?%rRB_%TAQ5ueTeJ+*pZ-uKen~E8TUZDxj
zw`ktkly>N5Ee|0~W$h{|fW%_w;?rAxLZ)YBl0%}{)d0H5#H*utS7dHB5&B1)``wJJ
zjoV3<GHc6SlnVhUJPF`JaXkK()r$h5{MBFkZ!&fIFaJNf<KZ`12miIfS{p`n4;tnh
z4zBsMvJ8_nsc(iJ#-4AI^2(!kejfAu>yH)}vai4R*Z94@=Qo)_m4Zc84azhkW<he5
zxn$7#E@{XHLwk=c1(~TwtkIHD`l{4#P|m0o1hEr+`NZ|JO*D&WKSN@Ra~w(y-!$YE
z7SAH`To>a{ZokEt$nKpOGwV11lF0&s6JwV16c@}jIb%Uk4P)e(f(6%?gGACjt}4Bd
zGR;xc{94@!?)*n^SegUdfs}6|6T_&h={BF~-j%b^{7nuYyBVAD$1D|7!7F8blazn$
zOY7hD86{2*bw^c5f4}OWwy5woN}>iFawg?BKV&}Z*~xd1#ziGbUF5%HwDBQdY4r??
zkmcp2WsD>Aml);PSRw*ncN8cma|Fd}?|pao>n54W#;uJHDa+7z<+E#eZruKckLbPs
zS9@n4D@RoY@Y%<sw2I`tbz5I6ZD%*{k7v;|jUdJ*c6V7qL8J&$5)og}YNCjRh*6`a
z^Xh9UqLxyuiAGw`m=M%H(Zqig+6aPRZ2dr@XbOHLM8VFh@#_y$f9Kwr-MO<fvwL@^
zxb^LQZ+B+yJ#+54=bn4-Ip==t#~=q{CnZU}-Gm7U6$6~fVo{T&9FX3|CjCl9U-*9J
zy^4)9O`nCNK&iaT=*yS7L*zx9Cx28&NlFbIQ}8~HMUaN=A=~Z^7?I*CDJs5-baDeG
zPCY2eh7ZKp!{I2$222!zLk*{o_6jP;q+Bp<h+h5B+3pgUL361!ge$7~%0MH<<_b)W
z0*FQpR6~+=(@4VEjH^^i{-55W9)pH8p&M-op-e}tN0lcn6}5+=pg)sKSkWPD>nfds
z<D5JnL&SktI8Ym#t-%0M51Z818sJhdVXb&fOyNKgQDdHmX&~;%&jUe9@c;TdoeXt{
zSRR7mrO-8)gA%^TYeKmuUcTuZ<dPYX=qYFJH~i>=(5^+IC45Rk)cc?TK*3O?4#B_p
zDyca*=GLVDg^4giYDggzgDk+z1)tQcsAnC5JAxN#)6=f}JOqI*+ezY<NG5g)dCO!f
z9r}#SwgIb1*YC!^tIs{%Huz|M0%;HyJ}75o9F2a)1?TKvb<SOCRR&CGTsq#^Qo|Ih
zH7-R{xpYsd0VB|2C7|bXC+3grDq))zORdosIV=R58rzL8tVX$&_5w$}LSn8{xc>OB
z&cARgeHoyRxL0U`jl0PX6ZCS-A<3476a;i5S<<a0dX>arp~9q#Zh*cUYQ@V7kjsF0
zXKC4FnW0dHLQ;Py#7yy<X%*+_1tZFGWWXq*Zebp3(~w+bii&?YDOt*``bUZL$T0kn
zC>5vvQ|gK-EHN8jU0M67Gudb=W-2_nW=oyf56p#SV&YApOp7hY)CUuh4htEWA{o1(
zUYbGypJbgc(^<@Ppp?%|uofHk7LPV+ELI(_EJO9w5Hb;&ZY6pTPL0e~){MB%ZC(Vq
zm{~|08a9ocm8<j=Vw#YflvxQn&qzOQ0M*|?#m6?ps1d74v~XCMYBM<;gswjR-=Eim
z0?U>$9_UQ5A7o)QO23}mk`aOI^aLboKO!of*Cl+E5dwomd}M|z&1iBleJfaLcRb>3
zSAr&HASM_N9w=0$l7>e<+&B1>s-^7~nYVK>%xHE}DrLE473u(G+CEZRb7J><bfMH_
zXR#&&1E<4*7EVz^<fQrsof9@8_Na<Sj4+vyav4j~O5@3#Ckwb%-y$*zQW3xgb{^ZV
z8`Ka*3B-{E7Fl4J@tK?{&}YGADJ~TwtC0&ZBc<UTKn|P=M{RGGk^m&eEJc9TDifp;
zG}N@N91#R6Ok@TFnD(r5rNK&@RYVG5@gSKnKfU3^Iaq6wi%d1r12$fRZR23;uzL4$
zaEr0ioMMyJt%$blfq^LCSV#LtAUQ`q!v=EeIE>evD82fS=#yT7(TrwM3{5~eMFOtF
zdF&~Dh8Wqn1?Q5(_`@Jh8E{^qWigUt5NjHjb9)!<46M4^+r=!UcHTdWUul%`z^`+|
z@~~o;M}E*kItVr?Ba*cVQ6?xYeF#<`8FVZZ3;E~weze=k#DC}dGlKbVNX}zx^tWP@
ziC?c@cH+WyF4db$U@*G=8zCm7zt7;m_o)LjqJbfMU}Kb12o+-WtnsT@v2X;)QA3sn
zY|CD(E$^=Kk@c#;NU#JA8|WrtY_(ns@8!r5l(kku^iFV&?EdPR%F-jD0ZKl!6dkyR
z@2bYG@Pvs0OzeVU$=1AgoQy^H{OFE6yA(%HD+qnPhqdpD{BS|5puHeu=4)>`?L{n%
zFv(-7gMLV>h5*t%@yfr1FU7B6b;je<pPzklQF>x4C6FWtlzu5S_&@w%YFdDTbo^(j
zP|<|S{;LDMI2zmIy?-r^^1Om<sm?153A5$ofOAaRZ@3~zt1+{bkXB=Qfg>tM)EAu!
zI{&th+A=B~egO)w8dTFc(kaDXcWail-RX5R{pOvVHIP$~)?f@7_Jcr#l84`TcH}9z
z)#x+&{q|Q>%%QgN9WQ{4AuW2F<6jC29jzzfob_*tLt)<wS$qPNR`_;5%5f~wAh-fV
z_NCpls?Fablz}hsfZ3tkus=qeQ8eR07a<e<D%quwQ;2sS9-cmzQYz;ob*l);q$W<t
z?!9NmRCG+>76z<-<vx$UmiAmNyme)Ans#wPtWEGAy3qhfgr$%{txA&ExfbDb|1^PH
zB_-afq`>>DzHefKurTPluqy5se;&RZUWGcD=F-T-I~AsMbKNG#GNgsbx|}o+BffO-
z0;5rgqoftA$|<ky|A^5IGeb5b&KlX_MumC^H3YJ9Ebz3na>~3bO+UV5dlUkvsbEr8
z65Qk7#hr<x&xVoy7q9mWD;6n~z7*jT9^lm|;|8<AI5vOZ-yBpE>5U_6Mv7`T!vyQh
zIoS>V%396xyT>_V<2kjXVZza?O4w{kt~mP3b$lt^xEN)BrsK|k&{V`#9(s?ya(%*b
z^<xB3)qU{)_<{*6jDRQ7E@|_s#abbBj{UM=c1d87?p%5h(8BFVJ2Uf6ek%DZ@!1&x
zitw2UU3}DL2P3)D!>0R<#-PB#Cq>7zUJwVY(X({I=RdE12P}jGg`!Iwd*TrmZgOjd
zbM=cOaqYKwXx0VOGL8xmV-k;dX~h}P`x?BIJ?YCE))eA-c!y<fl&!*a($ti!!|zJT
z2C7|k-!{wU9jW`41}{e;795<A;!PxnU>$}u$kc@x($)+lP0-TuyU!YKZ11$OJrqlI
zMK)Fc$5jiY9-R!BtcTJ~_nFN*3pgtc=a}QX^~0XgH$$7WX+<2H@bp-cg(a3YcFTN%
z8ZNEHalu9q)ZK?2$~V?(xRJL-WLpVcp`6~?^nNtd3rfjVNMvA>p)Qg^7bv&=xxFLf
zHP5PyVLq>7`Xw6F3KEC|o9HfrRBET|;D2bJ39HCbMb@0NBXjQihM!WSwyc0AJ;&b=
z6BCWd6~@V}9cli$Uo<iIeG@klq$h?fJ^@j7v^{*;%TwB`Rb}d8&0RNYmXFROf=1SO
zS&81kADQyYkicKSeh^a?RyBO>XHD|7z`C$*Ms!kctb%{ruiD@hJpoa6HQ^szXJS(t
zQIsSreD}OAxn4CAzO6X7ZJ${a4n2|Eq)pV-){|L^#HY7BZ4!rtpx0A@2N_YgM3?D4
z_*)K|z}o0QRzM?`2BOH487nHCt=}o^GO((l5ylA~dMb<>^>4srKg>O`q}s0EtKX)Z
zDac`BD3_kH8&;g*9xm4BicFbjuQ1T+f4ar6`g`V7gvvn}A=Rcf$6AR3zh-ukX?j9$
z5X8V(A=PJv(SP!_j$zn^=(wsC2$mzuu_ugKCehbL)0V3W(8quG!C$@91YUtfC@~5v
z*I>{xfij*pZ8aGvJz9$*JHdCHxd&gCpaFxihVJB1P*I|1dN%`Zn?zzmL|WTtW}WUg
z%=O+fEXZCg-Gs%YHD~tyPkxH?%2h`m_2at*Pm}M3n~Qt20sL3q(d|6`zZSqe{^w)!
z_&b@$PdS}jOQcmxrXKyBb-wcnlm0*Uc*tII2<OI=QxjtSeVY<udyH!7VY05<42(5q
zM8~HmZ#O_9E>Pmb^#KM**25LQPE55WN+G#<oiTbK6j6=NYK#V-f8CBG(xjInXo*V#
zNRHd^dV{uPpe|!mCO-p`Y$@BuhTFVCJ7uyq+zT^k-gKGYw#UvklrJR}p=j7Tj`>Zk
z`@&uILH;2sM^z`3+64dO&!m6{Xd}Xx0vL&&e*CP+6RIVvViiG}Dvv?eP9vOKpIn@<
z%;7bfYwG>YTVgu3dfN+fh#F3*C?W|*AAg0RL!sO$j{zW>XO?BH&VM>ztJS2gtb)*}
zRSP-c2zP$DoXp@zL0h-gpPgs4e{ZH-W|Bcl3>QVa^_Y1Oy}$KN=exD<TqOEPGbnGW
zVxf{66cZbrze;(=<{x@AV?y9|j*nG3xtuV3?#zgnkJ>+d?#r8H&^L$_QvgaoM{{Mn
zs1!{VDh8PNC?#=@eB9u;0#rDab`35;ocMZ5<XkO2Ly0^vs)%Y0Q}B+5T6+qDcyzUJ
z@?FO4lc16flc5kOl!8{W=sNh1JraWrES-Q*DLR?h5qo4$yo%IdFNnaTX#}GkQvbHi
zZTk8lRCPH$2V$8RC{*uVCrCRlyY*mEyWjqq?ePpa`vEnLU#7x#p?S#RMxUm0?b#;y
z(vf%$vV#*NVHSDSM2XY3*8&`S;Edt4fYr1>*m$hkcGzJ2&pl{p9ASL(TE!^rIvo7T
z5~F|SMLm^F6VzKWML=xA`1M=j;DS+(w@0X5<&c_;Lu5a%yeT`q%T#4r_#gOYm*8E1
zwak_-fU`iV@MgnPW>1?1-zlwK%kA_=QhMOw@!$Tlq*Tkez_9c0&sPz$q#_+WAC?99
za}x|^a|<`^NvGO2B}c-XLFL$B5~do{O@r9^AVY&%mE&XIzP5n&BIbwf5+3VUs)gdi
zpS2l0vm4)_@^s;JDCp^8s6;*CJfZoDD$=frTYyfN+ZOXQ*U1b#@}ahFrLAYT^6b>!
z`hb+R@y}ipb8%(ootZkmb!lu-MkcsQOeRZI*PH)f&JlLTl@8Gx%Tn+S)twZ^q((0o
zju{@*RCaVus20}VW8IWe(GI0Ql{F~||Nk5l%fa7wINR%!!kxruf8_%nT2MY={Kd~C
zxa0d<eV?wnZ{3~W7?`)@<X1r#emS4I5iEn;p`X4A`p!J8h(v?KpMHM0#HQ1^`}s9B
z`a;##%6vD}T|ZyPkF~kedq?-56}`V}you}8zdGW168C$uGH<+={;+m!Y;AoyXy=sa
z&HWn>%DE<4ZGE(T60kD~CPc2tLezN=HX+`=uS3FYSvcg_kYh<47-UVW`V#rj**W`<
z=aZPzTihVCw6_u^yfw)E33AiFw>(+TU0OVSkq<TWP8xcGoc9<t>;r5WH{{rmV+kA>
z<Z&i}+#aKb!f(sCA;<pL9K#P9JKts@`p<1^Ar*eXbabb$|NN9vK3w23;0s(*TJCTl
zN?}ZD^pInztVu~&FdQ4MZ%L7W<md&XGb9(^GWJv~X3s@nWi_JXU%uWOu5ZbGQNNoP
zPfPyqe{3mm8Q_E5qn}bW_w+<wo&V*}hwk&2%za*+-?zuE;Wjebnln9d#;&aNF4I&u
z?TjD)c5@v`moFxQ>8*vIkoI5~YH8s9bMeFN(jdEt&#i-!a$fgT7ddtb(m!Fk9#wWH
zpGr7bzDq(hSgy!gIY%_ROwn$=k#XnOugXZZOzNNi%?uaLrmkj@`@M<CMZc)>TV<=-
zz}Drtbc?D~3!{{>or%>1FUdC10bk;hiy4LJES!BU2+nD`#wF>j$9#6UR_E`T8fxjC
zv~)YgI%||E9r;1~Sx{LoWTnyPdwJRFj_mKrE##>2<nG?ct&jsb<Vxv=gxS_{o*XM3
zT{iroNV^Ic)b2u@Dt0Bwg3hy)rLD^cQ^>~VHy<AE6IF&{Zd$|8kKVuDeyUG$IdvOF
zOUG{?8Lo8cw9+LnbC}<-|Lu*fUc9HH8(XilAM-1DtLUywefA&x@4mTzBq4@8hqiun
zvFd0@QE>IY(E9+Mh^#6GSELF6@;X#Vum!i>DLs8*hc{z|i9EK?Xq-3WjOAhsN^uVU
zR8tlyD5Z!zMM!DgrtLNMUw^9tQoL({+uy0yxc^U_Pp+qe6o!gDp4J=w_ukif==V;w
zf<dIL=wIDx26uNXX1k=CuWZ;GZ)RqC^eIgynlRH#2kki2fV60zHq|7z$D89HJT>b2
zOecEAO4)Vg7N&2^hUk<-G+p}cu@PeKth-z$C9SHu62(E9YD1!G@<kY13~+JQaop_y
z)pexfY^1007S|<myE_XW;QjgwB=2~z{>W5iqPS!6m6g)+3Q1S8M5$UDJpk&9M=zVL
zY%dqCY;3H{dEH^js}qYS%N%#SWAVkKUgf^=D|a~?>uW}cRvBJ4%Hi7wc5SRrRaO*s
z?3&s&`L&9(Y+~d2CC3$H2d>%lg~IHNQ<3g#$6_`)hC!Fb9rX&1HyS^|T?C&F*&Q)^
zJ=I6cf!vP2_X^FR$+|G7ELg{2gX2&Z$J51jnuE|Rz+Pd-ai(~e?1E6|<U@DYD3RXc
zjqqIH{qyb#ll#9$n?b+W`Wf2W@*Wb_#*z*ZagOck0B<B$m1wr2{3n;6%q{#E0s|eY

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/Pisces.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/Pisces.sv
deleted file mode 100644
index 13aa31aa..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/Pisces.sv	
+++ /dev/null
@@ -1,193 +0,0 @@
-//============================================================================
-//  Arcade: Catacomb
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module Pisces
-(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"Pisces;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian catacomb(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,  btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/galaxian.vhd
deleted file mode 100644
index 138d85cb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,448 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-	signal gfx_bank           : std_logic;
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		I_BANK        => gfx_bank,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
--- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
-					when "010" => gfx_bank  <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 5a4d0094..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 01cee00a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,74 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN1    & I_COIN2;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000000";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_video.vhd
deleted file mode 100644
index ec46308a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,433 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-		I_BANK        : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1H VID-Rom
-	k_rom : entity work.GALAXIAN_1H 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => I_BANK & W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
-	-- 1K VID-Rom
-	h_rom : entity work.GALAXIAN_1K
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => I_BANK & W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-	-----------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Pisces_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/README.txt
deleted file mode 100644
index f20f8e06..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: TripleDrawPoker port to MiST by Gehstock
--- 11 Mar 2019
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F1         : Start 2 player
---   SPACE 	: Select
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/Release/TripleDrawPoker.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/Release/TripleDrawPoker.rbf
deleted file mode 100644
index 491c016938e7576248e9390735ca8bebeec2320b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 270641
zcmeFa4}2Wgb>BO?TuEzLwz0!CGKLvycDQDSkoAX<;-F}sy}MjUOByyQnMv4&i78rj
z^pvLh6Q@;^e4?4fKwOxhNGfupv}p{0tiseuMEz-=`jSS31imnd5{Ze@>ZMLC%1NWw
zCec!HV_9~r_x;`30TzD=h@i{VI0ScQ?%#9IJ?GqW&b_ny)?16i9bYx@*I$4A>tFx+
z*{{9vx8L~2H{N>d8*hB`>u-MZYhQcgYu|VS_~x5$zWF~sv3NuO+vi$90JL9qzY1@U
z0+|-H*G|&T=c@LyK>M}5kJ<N0UrBlir~*m4u6kZBsGW95+F$6J^q1tTuKG;UbzLqF
zD&LNS?vwTxx+eW4`KqIKlJvKGP1;-PHR&fQFFXW^3?}L4x-L{+=?TnkL+MJJeXRqR
z0=lLFl@U(53Y0b*;+*ME<tJs6)Fdr=POk0g>Q^*L@^n?cAh|yV=)M9Z>3U8;X#zdR
zckz9apIqDX+V7KmU6r2Tl$0s8Aj#KNxNHNGyyU8M-Rqh_l2-$gdtKFz`nVjBYzvf@
zfar1spfaBYRA&H)0HrHm&*J07;6_0C{Vh;C36y~~ElACR9H6A379`oK^IO0^Kv}|P
zvIYMS(0<?koTMk$1cxnv+HB`P(LnjSb^tb@@d}idK%5eP3J={SSB+Wsx+-0ud!;3y
zv;>c&zeGNg@g{vGSJe@Z2(LVl)K|XdQ1zAeJ3zt%Cjh0jgVGX6(p5gWPx{kUJdi+w
zS270WC*x3i>VFhy0H=UI0Fr(dy1on~c}f4e?g88us2_pw&{fI0{xUEE6ae9-I?n-0
ze*jRPp1;@v-6xQw>H1%R_U9e5;1D313&aocT}Ov-5J)BjN>At^nM>qL^w6_tqN_mn
zyIK&Z#A$yFyaXs~78*O$etZ9V7VZ84AUyP(z|Xfp>EaF1RQ#XJ-Tgo!4~xmli!DgX
zs+|O{TLAT!;FMew9CS_a(7glP1*l2kaTL&1Z7VJ5V<}hleGedfH1Fa)^|27FYeAB)
zG3*A`1IiMfdKQ03w+Y(s<CKAcziL5}r~dc0K~D=jK)1@$eFDGQ0zG#Fx;_Gk4(-rR
z8>Rm#kmQR#4*|)uu99DY@X?$L61mk?xM+UVpRSS*p`twTsp^Ukgi8X8@x?-Or2gAM
z{Rv`>;?FoG{`}1r=qaI>NG#kENNC=E75&>mdF{{bIOtyUJ|7NA+5tfQCAf*Vz6m5a
z=&I*)LAxH&eIhH#HR*4mYtmnmFWfb@BwgeZ4oXYlTsSE|=|8z@jZI`>Hf_|mbf-Y~
z(jT7!{u~gmY5mnzJej~(TA*j$Ch5slGByaPy(CR?+YZWW2aUb`ImT!jC*dtT68Oay
z=vg?5M<qw<PuC{_;imfplqQ{&z;*M0Xr{gr_&gwekvwZXN^qO+`aEzD5PvFP>r;}Z
z^rr!}DH_Wr5nK<fodrruKv}{;AUtFb2v4mY54Rv$hqcxSlo#K{pZ}u;v(to!;Ky39
zp$(G$+pof3kfaF@@xDQh5Am#?6KI#y`R*0`cn#3}Cm?*<(3to3(G~~~6%hJrN6ErZ
zv~TY(!AIBj^x5|b4vCr<T@xEb`ZEFPRe@|YfztJ?wd(tT&KCRvpl8_~y6yyogRX+_
z1$0%KK={ahOz;qWb)U#aLJU1if9WcFNIFd*S$`iOTlbHE#IDx$<RUOz$Nx7#X$c<5
zRsFR?f?I-@=>98!$|SVX`Xf3Bbf18pMVI#L?E8eTM27?<1Bsocv8%5H59R4Ow$iS+
zLNwY4C{1gy^qWBQDi!iUKzU00IY4&HRzUf()kI6B$wo_LP34q+GtiEc`W8rDbyc3O
zYF{AQ2y`#oQCIczg%;@kmjGSmi^;avRd(XP0(76G={W)MTms_31k|@6!9(g!&k0Ru
z<Dv1X?*tOOq%-6n>$<-MzYF~979?rXWuIt)Xz(+Dt_dhh_rgJ-bwVI~<CHipnLE)+
z_sLauneOidt_76$F+gd_nt2VN^;{qsmYpFUSPYW7qKEiEyd>V&x}o(&pyzXe)=WWC
zPVGpSCGZ50=qp{7p2&@^8k0cxR{^?y7a(2{2oGH)%eqQWC{0&A3v{ov1eB(E5eOfR
zQTB7<kL#MuPm=Z?;7TA#*SviaP?|vNm!74sWJe2h|3g6h6o0nsR?VIIZ-=Bm;gmp<
zrmOl9=w3K!41WlSuM*JnY<OW7oCeyH+HugmcrWQ+SM?{*y>yuPOS)CMMj*NW6F_MR
z==oeA8nuIDR<fCZ`kN2fSonryuRTw;gkZijrGKdfx?c{ox3_w~N`X}htWsd96p;Rt
zKAllMm=SKCku}dlepcGkKX0tNw$y6d{W5Q#KX}D5Yb;#6`TaM~$}G)@8PCdG{IU6s
z8M=M(!sp7p@4c6ttH_e`=Z<p8Rp%C5dBhyz!=idE@AKJVSS8@IVv&<TDa~EkBB>)2
zq;1PEP{~t0RdyR0DmOaPxKh=k<ynv3mo`<B`sP}-+%)yM?}#!MjdZBh8F1(piX`9`
zQf(+$&+kk-wq<Qo16NmWJY1kN>%CxFEnD67LTX2Kv}#eJKPqNMbEJMiO%)4#^k=L<
z1uWm|N|o|2dc~ujW!rlSS5>X9LdqKbUK+MP+xS4V!AseV`Ule8X{)reSQw>`{><@D
zy@N(5QsZJ(a_Tr1GB;%f8p;%CNMd4<$gQVDGs`+u(Wfdm+zgfL#eibvLXdv>_ur|k
z6@l~Pv$in^n`ULUXr2d-E6=p&flPbViwCh)^0&{+lJDEdcIT_-D@tw3=J~Z3W|cGQ
zV9BGKr(pAu@p)3;X41vO{<8+Kir6fIobz!e#o9ReoHgeu@YcYE;r@BLT3*scJ<9s>
z#<F1PQtH}Y_&Y)W1xK)?jPo;BW_2->F=k~h^AW_{>@w>tSUmsyf4p?T%;jcW)R-;L
zM_p{_xxf4@*)GO^N1+m?tztz6^p@;EJS%pPvT`2Y3jW8YjCEafA~LNlyMp!fpRd?F
zTPw}ZE60N0^RE{p_VV&pSk9K$`C_GG#NZ6exUuks)nW_lJQJJ0{-!!+NiD&Pu`k!+
z#Pdyj`U~&TqH!UbUi%*V>Midtb{9_fJX!WUeQtO*y3>EMTzGcqKL3$Ud-oed-W`S0
z_x#4mahtL~@WJjg<u~qEomp3JeROB<MO)oV3wLkejr%Lxyk{8U(PI4Y_}zxMi!sg8
z^S<=h<#P%z*~mh9&4A<oJ=K_za6S)z+jTy*XVzUnx?QAdsZg6L*!;8qFm-?4Hw$34
z+;-#W))($yZoPTSn+Q<z4zo)?Z-J#J<|wMj(U<O62C2`{{7NrK=jd(;*(D9GU|BEs
zuk0wLLstS;4e#YsafJlabi7g=YxwMi&WqQFS`mgdx~w_y{VQg7=R3|`zm17lwjI6f
z3M*-N=d2$YT0Yw@R0DQiF~d9GeC4+n>Sy`s7o(t=QN)M^sPt9KTLf9Pyf3)ry?p73
zYp}qqh_*DAU&q<?Kk#-DX|EUCq|JT*rakfe?k{p(aejkKYOj>FVA}g%OtIM~Hj**2
z5Bs&BntnLnyOkd0ir6t4)Ll<#gMDS-e<!|Jm?A4Yl`CfSSk3SJ!opZDH-}NK7>`-=
z#c-C3P*Q%SRua?R3y;blUa_$Dg64ShCm%@gKmY3rGoZCn^Zf1Q#9xTeF;QvQ;{qA<
zQZyH$>3rW6s{!wo3wW2#e(^_U=!jB!#^drHj{mbYD;DtXIQ^@zPz%lrE4A^-E0=xF
zb75QU_b*~oEuq+XUsqc1pEp8D1K&1?t*(^GlrQOeG5Z56XLhfiGg%Td%qa9NI%iT!
zHE;a*jE>LiVWsulsybQLbhOmT-#NougS<dUuNvNRm{ta0uca&sOEi36^WJ%34DY#v
zEzV6^Fa;C3`Os?%W-mKqrB&jx5m>0gDq;&!W})<pnPN*3%!S4^GyU7>NaoCezul*c
z*@%C;W13rUg_(cl_?4i3FdcQ7i}<oqR>R%A_PlC!FN<eZt?n5I&r4^2qR-WtZgX_|
z{Y6hE_zgWe1pWSe&+a$&?Y*NgG4x4)ywkq=w>a6YQ{Wu)jt_FrzIv~ibKe(hb?*gm
zpK-Fg_3-|$E{la0D_lDJFAra&+A<DOEQb6t@>Y0(Sw_$2D7uQ+IS4c-``d<Mt1IQ4
zxnC^dVz!i5PQ|W<yBFhu`SZR-;cjasPj|1rRyqG%E|Piy6u^Zzu(A4D<?3sdZAbFv
zeihUrEIxnMoj<a2r%bF1^;+c;1NZZfP^oX@#L9w=t(>Y*ME?^j@g`&o*KZr^cEPz>
zZpJFbRw*_Q1y)YPX?&H(=ArPSNioH~O^<e$bgcc(_bvN`<w6uKrGE7ALV3$izsQ;S
z@1D)g6kH&rS3}(^7wW!fm3YV5@0(b@6faccBA4!k&|Y5p>f*jUdf}wZ`Nrwxw$N67
zrFm>M(%nYfbKhRfbGaJnKKK01D8Xc|+zFG_NH?l!#aM9ldrZ#Lto=I~>Mo5vyJ~iS
zb;X3pYTL0iKY?I=Phf@$T+Tyt_`#J{m($%Z`HKywt4!ZDf97YWAIx1fewGj|8{Yb#
zbH8_S*^RU+T+H^u+a1%~dMj;|&h6oCrhGdf_H7lRdYgPOtJ*~?mH9j0cX56xjSef$
zBI0>GuB2Gz?tHJlbn)9X+^tDiNp8-+(0Oq(;DrbwUZ7VKnUeD~-si1;;Vk;qlihrQ
z_X?lvmSC<7TmWUcGKj6D-nkIsy)vU*N%F5!Y`JrCu~KZ+=w9wjuBe%^qUvJR=w9|*
z%IGd-=l|C3jx0ZoGp{)wzRfCU|K`<YW4K_2mDcAgwSo3+^L?Z+!94acJTv#JLY7&y
z`CfaOHRc-H3*tfJd-S~)bDV}1>GG|icXz({;U~+l)bDm){Lqu-z4d+NALaGR54}_~
z?^k~4rCoZ#^49QxdBd{vrJvAG=ybl+XI`-!d5z!7(JPj^zEVHym><vCTR#}TWchcm
z5$tjOBG3bsZSiP$-hS*|D<*1fXTTTK6HCs(L<v^-J@qB`y=cLU)pojgErC^vEy_^y
zWUe&D+!d3g)vr65XSx<kTIs1=tgmI|UCfBB9KWvg*PURN%=@L>tLFK#m~X1^x6983
zz&ESrIkP_XYo785R?YJn-o~nVKBX4k{>{a_tiAnF&91r9;g;F$zwPH$#Fk4sD7JFu
z&Z>F7O!BX^y0~bADJ#cgEB&)T3jeJP@TUJt2g&FA<@(sxzw_X`R|acZS!pg@vC01S
zIWWFpgnAjl?D>m+vXHu<jo*L4T#Ni`!|B!d`Sf<c1vb#<{8G<(=@;yZ71OLUeyQiY
zu(|-s?tJl?s=tz2xZM1{Tc;X6-<#_36*xXv(xLqV|Bv6aqTg|UzJr^tzY@NKMrpp7
zr}@KYr&~VXyOqE!!C@u2Y()=jtRj|7(NeD$fMOSBAKba}$1hvzpw3zD0*v~ceJ-iM
zw*;}`l2Dmd=w}CKC7j3Ow^A2rxmYqZul}ATmpx~}Z{;Y@iA;Ne`4J1!?PZpH|8p0w
z3pvjiTr<dJ54Ab+yYn>Gmb9D}n}7bd=lH^XH|@2xz36Qz_2{uhCQf)Qxh*<+;n%-a
zZ#ZfumV?<p|G`D+K<3it;P?-%Iagy#&PQV}5~^_P4AZjwr8ZYO`)j|scv(M4FS#}A
zu3d}$VzmgioYwN6|I0;$J@C?&Tdyw%yT5q%BJQ1-!}pd>x{kAbf3>vOSy1sZn=(Oq
zOZFO~8gKjT>2G~<@tGQ34tqcPP-gMgy2qE%T=Uca=Q&i&a+)ipKJuOC@VC0t%Mj+L
zzj>~)!k9~i=C-Yi7iAixYnBGh|FON4UBWgujSf(5NoB36qC1W)sREMpHX3i<@ccQC
zp}Ofq6$mlVfFQ8`GLEd4&h9_Fr~H>&-e0`NF$YkK8}BveQ9m_!AiC3kvV7~{fuZ~S
zM>;z>k2>UW9`#rBQy*Nma5*#a#sgF}CpS$K@%hu@#y8>vsecC>scbXHYKf;^<7hOM
zZLddvyvRzhH2#|^)%FDqQ)yE-9kAZA;Lcx9&(X9VR)#;-ik6jStOdD0nXa0&v23i8
zigz8Hqg}wQwREabjN8)J_wC<3r@^GJ_-dM3;ulLa-}^&xrCH;PjWi#sO}CviX#!Q#
z$usZ1<HzG?>4G+hsqg!)+G|nQRlw_9@cfNxs5-ltH=WRSJDu3NOHkIMzV^EGm8a+R
z^cHJlPNP!^%^&`ysrz|v%xLG$F^Tq!tZU!Y!cm@))_QQyZFeMXO~u#BpMUb5^R(4I
zQg0bn<%e&bv*sGcP1^I9$;YMC_TQMt8lUF3bI@+q(3)3$W>!jKGSlL8qjSp4pKzBq
zFKeouWW4iNoG-O`>WTT1r_wagx%y@*d)CcsN9N4x^zhWwGTO4N?f+k<KC6THarwiv
zto-&{X9~TLi3Pva2T$INgn9d(N^Jho56@Y1T+c(Zi`!I;PgE%>-ck`Ro!)!tR0pja
z-}3`p8N<RB2wJ|t3$XWR7hUN2(f{K;joEoq_Pub!?1}$oms;St<Mg%^I&|K%tln@s
zV!(Y~J=LAgmBMtlC!_yTx84)IT*3T#+gAVKEpyOuW5QV7nz|s3ZHNqzxI}pLcjl0r
z%B;<h8M|5+-}1WCOK-7x<uA-pMIhr@-JZcNxvKRgLjL%pbBy*;kQ#-`F=8(FdbV^~
zVyo5zbCxZt$0O#NNUFJAQj;%in?p;3k#EW2F-}j6Wed|KHL5~y{mX@Rz!`n_8YU|5
z3-uX?LzfW=zw?JLi|A&a8bR6}w~@C}C?U2sF~Aclx<GOG1<edHvkt0$DW6$rm)*1c
z?i8X&CEq%<mzr<G{m9?<ORF!cwY_(@<c;<=I~U3?8A@k=cGr>%pR*t#;W^5=t&&7>
z>5zNvA1-EpqtBKDU%E20oZ^d?)%J>;t_NAGJG&HhTE^Hcmognw|ExV#t7271t#lMK
z%C$ODR<4vPm%ehXZ$)-)<BRpop`2H|@zg`539r(Oaw9n1TWW{>O_!XA!lqpwxV+@&
z&QxAfxzgU~nuq-SMlZA7dDgc!-4Nx&O_%rsUD<1MlSkFwHPO{I>wSgF-e}+*`46hx
zL|kt8!CR~WXUXNRGX191T=S_fT9N<0TWeR9qwbzC{NSt6*kEt|wk?<4)Mbx&hbzx+
z3m>fPXbfyhU48R`Xn4(@`r3);m)?8K`?*x{#$$Cae@*9>;@N1ko4&Sw!$>~bbladm
zkhQNaQ+PbLr=D9M{Ze?;d+)IuhAPJjFXt!!<pVpLM{l*=)AbLHY)oBMxz0cE&~WPN
z@_;{{+nA;CtDRB%efQs5jJiL2TmGMXs%qclsPwOmR8pHR4G%mym^*yS?nY{)Qh4U*
zwW0Sv3*WuyJTEJA-t7>i5(Y62a?2%Ka+}TTUtF;4@&t)ycC?(&87*Qqu}B&WmyO&H
z-7%vn^WeuzxLJ6Wuyic%`muRD6k0ICr8Q_d@WRo#JG>~1rDN0HS+kP(d+n*_KEaE&
zmkO`_;+!1=)?$ICV!6<~vTLq=CahXUdxGH7+AXDip*FXqoCwx*kdsY1H-C|o=I?)M
zzFf^|3$tZ-D3<kue=?^vAp~-B($AgH{JuHgHV0mDEJk)C|G}~KeD3Bf>q{S+$6Jht
zspggmKe>L6I|fEzD9V}k<nArK;rzi(`VPBUK+p+asWq*hGS$P9p!p~M91J~QyzJrP
z$-u-K1Y4nKT3$k{rL%*dpIyxC1PM*!e3ENOx(vSg<gZ`anBAz{#n#`{fTwO|7oPE)
z<0<#()_0T^@)!4eB_D-4SWkJr@fXLvV#T|v0$H?8<XLay?Z_RDx;yiOb5$e`lA(v2
z_D4O-_0sX*43rmn`183TFwK|#3s@QSw{-b>^v${NZ-5sl8fsg3H_L4^f7jUD01?ed
zRt;v5fQOdCi}60k=bg9BwJPOl#={mJwN~)4M0j~}ZqaFcG=A_M=VGR6DUCM2{u|8r
zTnEgpWU(Z?UhD}%5gcFiHp+265efZe`f*QBzGHzJbP=T7bO}E(@%=n&xm#2(|6zJw
zH__L?a1$+$5io&=_KG!5M38&lAul|v=70am)s3XKeX%8OBn3=rtVL0Q%Yx&7?_J9(
zzgS@$r~pQo31+noDnd{z$P!mLsbrM0)p7cJ=RZ~8R$>jt>J$&&R5-^+DP=XEePC`O
zcDq`MlIEqXL$nmb!N18^ADBI8clw}%TDIM=z<V~a>|0o#LCUsuO(00M^i-1Ykq75l
z*p&%>QxojQjT((Y>p>yLX)2#qrwcdl|FBg|noq7QER>Gv*Q(|?u4zW!#AOpcO<GN=
zs8JEgK=UiJ{DpW-j9EqEEis208oL=i`40aWzlLv0>s~+<%Un@_KQMFfF+#1(kgISo
z;DBK3)&|wqee3F??pm2Y_~q73+hvMOaaxeVWQrRQK1o|KZpl+p{k8sfgP$K1jbUni
zU?d7Wy9sjB?IlGm$kN{GCqI<nI#t3<o=dnsNf|AG7H!%hAoOalpOk64e&n&ak|PXR
z2?VYTPp01M;u3~JRg*&dd@cm}<~9Fip**G2w1%xl5&+xw$0WIRZJzn;tQ7M&H96cE
zQJF$%N{r^KM%vSFW#`G!giO&fNQnY1q#UGZo(fY*%}@Wq)O~UT)ncJhI{@>McA#32
zveX)v#i04Ue}8VaT53&<$z;6znZcqvgzOXr=2mXr@Lh8gTPebohRh_0C&h|tYEdNf
zU;pQ-H4}&f)McP4H6FNa5HwAJ;9~IdPtE;hMeGDNiC7Uli&l+y5rp-zg5A?yD1;g{
z*gCf3hJ`TYz?(vTekh&&eVIKo0c@q;;w^KT(X?k1EvLPLkv&^&LlXWi+_d$xwVBQG
z1Px^0Km|}2C!i!pVN;OgPfzjRVsn<e^Z$Mqw$Z%%Q^);ugkQMEan0_Og|ETRf&EeE
zMC3cxU@CHvFmTTm_U3x66L#fL#j&o7PC$cm>|8zlJ9FI)&+u~WhiY)~OfJH16ly{9
zKhGumsAz&!+>(u?C|9Gl+Meg$HveJI+(eV2Mh)A!Dc76gHE>-FPmaHSVXk!}vpNBg
zTuy`53-(+-rma}Wl1AfekSu#MliQyTzBqR_z^<Kg@$g!6(q4C-`)hx8p<O5@w+_+F
zz7Jk2qBM~0B4s3n00b~oX{>;7IPv+fthI>M{`-G_UW*<lCe|r=iStxDj`%~mr?usT
zoGre4^xD_2h^tt}7n*9QL_|K&PFHL5>Qba^B9hSU360#*OTJg~*H$IL2prmX-b#=C
ztIJp4`aIWLpK}>(ipwR8(%5s0%%76K@*lq=$th*)+^U7epp==LJ1rJJ{K2`oN=aIE
zrRw9!Hw9y>#@x2nuSCl!%}wR5eE2=$Y9MLCJWPMkVp1hQ=eScEh$6~MR>Y*n?|pxA
z*Sa?1>om=<|6)5hZYy9R(p`C~o}Sv2n{EA@&l#~)fw&IYgoqetnl+B1GC~4j)>6vm
zeug$Njnj`qErYgWHOC)IC}mo0nWbhy#DLe5rVcg6jz(;%2Wv{cx&eYUW<;LohW%_P
zVfi_hcFVf<F+SQzrG?husOCb3Z+rk_jLB0VlfHsN+y-qMhrms-%+fAPtsQsLVXU|3
z|Hb95Dd`93Sz~&sb?IC_gqi3W)X{GGXRNcd=oWC=g=`0VL&-Gl)`^J(1rIeCU}>l_
zaD20|o+H!gv`vQ*L<!^BI9}k<G_{O<=2@CRkfKTcgI9NfVOhS7s1)j{(L!QoKz!><
zPfj02FoY46r-9jQ%{_DJvxx|_n}^dSO?T?BY2PGV0q|)-kdi%Wz$Aho5O)=q1--!d
zGP3Prdq$1*#Fh9->_2XkM3=#;c~RD|LflgPX@hCpep1)!5t|WfoQ`S7b7nQqUZX7z
zRg`R+IYX73$En&bT?F*k;^sI#PBO-d$QX~f)oQ-^><3f<6hmFqV0?!;rsNh$b=wkm
z%~z5d82%uEn<ULlRo}bRDy*5ZT+=Z1<1sTlLkHJ1uXX|I##rdVs7WK8z9Wj$cI)Hk
zR3|CeYQUxsLx*<4QY-<Hstv%-<14eLe9@<We)euftKC*VN%hF;NjjctEy<fo(9L&#
zIBCEnGcpO%Oh{y}Ewz<oILr)~JekYvAMjNmg)h2NA29}|H9nwYJT%i`oHyN~Nt}L^
zPD{}66)9@ondsZ8nu=e<pvqV{*`z-G*g>dyFu;VH=~M+FD;&*D^Pm2vJIs_zeaJx$
z;Qp9XF=%ihgn{XV50l=S8#Ftrg-ny!U8r*mE+8P}kE)Aa+IKO>q<848`I(1XEE=~>
zWz?eW7D9S(L%O9QGuEJtHU=9-4(N$LT5GK$sM$39S(l!2)1KpF?y+Z%TGpRY9B=*d
z6<t##00mjjQtswYT?qT2aC3u;^qV1r?prYZ%tX4Jn`07)QZts0GsjY0ASdc{<qFT_
zy4D0|3Wdz3V#<=s5~PkhVL6MlMS%`n7T+p)nXAfH@YqACfyP+Qa;V-to>RV)^VW@R
zww(2HYPwQWMfUe}l^f$;SE_5=bAtL>)6J+&vF-;e>_D&$a}<2`d!;OA;m!{I*(iKL
zgIvr|M{^0oBm?4Va;|f%(d(h7N*F_-OQa#IkE2yNjx(nE3Tr%@t(YE;h~>I8bp4I%
zESuH5?Q!*FS+hH$fhjQ47PpD4F4U1Vy0(X&yS+7|j1#t`7af-4@6omCu7a68NMZ;k
z9OpnQOBXOD8+yhSz^--IeI&=WMORAO7xgu!=vZ#l(;yg*8Cg2t{E2M|{)UNzw!yS|
z9m=-zJUy8*G0PK5gFE=(k-?1S;%63K#`4J<*Fa$)p>zBsicf*Fqrqb`8*Q|0P38uo
zR-#a!3Uzxa5e)3jUre$4ele?dgVZQ9HvPXPqEj7l<3g>jw*T}7A0L^Sr~-XQa_;!`
z%s(^VH@IeWvu@1?T^P#6C^R?R{&FI=`K~pLQ=DuC6A@$Tnh**iQ=YgRjuL7Q8G-zx
zxhUi!jO`NLalh%PE^+SlQNWaTV@F)yL$;?OANL+%+RR4Ls27R2SN@kvwOrCiDKyRV
zFpv#WR%e#Z+Z-`fBX6oOb2Gz7n%x8q!hg*_`0hQ!v)XqjkZ=n}Pl^&BvzPo$Q6V+m
z0SPVlFYeX&iX^t7$eCM{nt$t=i|-40j^4@F<6q!!#Xoq<{O?80-2Zt~FA{x6-IXeE
z35&J=YZD)GfewF0{#b$OZ>4Z=&;HjvR?uJQ)xE(DgB!xanB6sQch%`*Ou7bfW6B<z
zaeTh@>#*uA1{W;gDP5KV%}441ORRt{0`6FcOl9LY@Bt_D%rd7kzCH{m_UNiISb{0i
zeI8J)-I6;Ob6cVO+~<G!GA;tioS@aVF$c*qdYNR`l=9+ojFUh07^oFe-4xxad4bCo
z(tH1w&lUvSA;VRJJ!w1}y=6=Wt)w(&`e#iQ83nXC^{M)FRG^e~<v*<GV(@XNdQgfW
z9t49X0LB_j3hn7nHmGO;-eoySK|M^_*z)r7aC1z>vi-ufmxcV!h25F8qR0e1g@zgp
z=rrECD3_v?6_TXZoifBNq*{msv@hq!DP?*zNXK(ML+upQ?4X#J+S`m?Ee1p<bB$Do
z<CAM#HZ$x)1{Xts4%0`#BH=k5+3SjK8mk(ciA<RY7)dy1mg9HiGd(hInTUG0hWd^l
zY)F+%S6=h2BOsPjSm+w!xDkVh#Cf4LcsNIusN-S3BNOr*S>?`bM?M?b)?hB%Yxgp>
zHP0Fe%W`LJy9Z2(rPgr(z3$X#K^ywUGz$ua4TUh(%LHOYF?4*a0{Rv_gEbz#yXna8
z$eN=cn&=bQHCeGgS>}_0*tQ)MVIw8EDQpP{PJ2PRB=%xRw$sIIjT*v;F+A%de?ub-
zj2TD(3fn4e+)fLji*pS__-+~f?l`u`qf#797Rs`mt5K$`u!bHrb(Zz~4`kz>4%lF>
zLO@3?G;NnMbPx*lGSgs%p&f6Fwous<!gOLSU$P;7G5wp_#kDaH%}?kg0BuY``+b}k
z#-=7C6)C|w#+E1JAj!=o$Zdck#w*x&zcqM!*cv_;^K&h6k@yoE4o+ZzF;R^y`pRPD
z0`4Va7~GJ*uGuitVC9=@E2bLx)Nb9HDxi>1NC+oLn(+v|c=#CGYTWmGdr6eU**;Nw
zg{Yf<@n6M`?Q=!7$h4|uHwNtQUizWjo_dmIt{Qus;G%f~rbtvl)VF`vI}^mFn@OrF
z{6960xPC`=q|Vrq)>@p9R4~`4Pf0pvK#Qx}(`eh37y=>y-4Jwwz@BI6<Oiv)Tz!!$
zJ|KqZeznh(G#}!)s6~!eYLE(*pcMl`f&$H{39hsPxWYUJ$j~F64oG_RrgsEJrYtwd
zfZIxe8MHJ&!6bvExIMW-^wD~93v3SsVZms8F?;Fk2mf|Y7^LFS3t{oP04!&aB+wob
zF>k1A5Ctu%1jaxGl!Z1|>7~cqYfMta)|KCUmpxcWg;B(i)$#}%U1dW65uwCSV3`RV
zL4jE(6mjtO)IoV;HgdhPpK|MiY4yS|B+&Bgx>@VI@q*9B7Q#v7!f^txzM(#D_x4hB
z-Q72&9_(z;hdQ8R%RYe@MwjZ0G>8A(npt46x;3;Zji<ih6&k~v;*@#hMfiHSnA)ln
zH^TFpEy!mF-k|4=72LGm5m|$R#_??a(LWsx<ynePohYPe%rJ(M=0k&!A4DP3n1nKI
zbsU42nEG+jEMkb}uP#>w+WLKkl<(1DoGb=ed-he^!ggNoxF~ZA*YPxl<S*Y{%U*SJ
zG?cw7+SM4y?r3P@BDcJ&VMU+wE8#5->*&7dP=ylCO^u;bk?jm+c_XZQ{QAf}Q@^F*
zo*BGl*ju0LN_%~uDpZd5d>4j(P9COhUFX=5-?zpc^KcqA<X+B&>Cw%2p~e*NegcQ~
zvp86f`$uvShJW)v{+MMQ3?Fk+c6h*uFEkm=8C5ovh3-QR>jxaWqak92_|I934E*7P
z^~b5TA7}S5e~onj6lME+j@&6OxOE}x6;AV*(s;*64ywE${^K6WSKS~V;)PxBv6_yv
zKS%5MT=@6x7|^lSNcyH%b7kU&vc|W0-S?@rAJx9U$9kcm&gFk}r}2C0I4Cfh97(xD
z0ZgHuh0v(i#|&<0^`Eys|DUdKvt4JxREY@?MizwcGP6OS{6Pj~k;+r+&f&?uxk2gC
z>m%zLe<*8zn2#>v6QkGLR^JBAh&(?QaI0^PIHqgE8j8c1LZo{fT6o>^Y;kz$HQ)Rt
z^A@RkVPb}|xM*%m^2CuX!CS9|Bp}@uru<0^tpKXYWs?Uc>O%$J^p8Wkh8$mgF*`k$
z-^;kU@JiTI?`h2{RhV8#=_G`nnr_mMJF>W#cXa~p;1|MW)?JQ}kep!Fj(coe8~@ht
zL&RG%Z86dA8qu2(VLYaskeQCGp_tI7Q)qT`V+bLL|6A5jZR#OOY`@CU9eOoPDa|<;
z-rNXYcf=5e7<|HbhPL#GyE(d9RFSUpZ1^tmh~;lLzxo3uCwnl=Wnmp0z^*lh=D4()
z=Tl&bYO&ydWe;WZ%r2KrnW1cOx`C^F8iqr#M?E7x6mrix4vz0ZtR<SK9pl$iQj^^G
zN}L>kL|-Zof5cyAA=i2>^jj-ww4Q(Ua&(@QQ7MFD7v3qf2eMem{#0R3Dwxt7X%w#n
zX%=G}BQcLowDFr+`A$SkdMV4tCx7r=4<@~A$+o%GBnBb{Wu|@Yc@rbF;;0r^%5vSb
z5dybPQ&Rb@C*JkHe*3b|{BqpU*SPAp){frEjeO)cABlf{4p;U4`47F}o3H&?@5lb_
zneg>)ees8`@i%|G`K$3af0(QJt_<qO-~2&?)8G6-{r2Cnd&4wyYxrnS>xb;-d7<vU
zH!rEXWhV<8N{%{e4?CSsZTcUA7R~-QT%OMF_1E)abN6N^8h)jI*pG(y4h~ly?xl^V
z{4-(N$6IDc+NMaMz;es-i%Eb&a_bvXW}@TZsuzqEba&^I+l{3l4w?p7NdSISogb>L
z<OnlD>vaMzf5+twvvSj-6WU=o)q*J#QZDv)WkkD}OC%G6Mytqqs}n7DkKpgi_p-Zj
zg=7E)6k|~MM69zWNR1bl`^axxYRnQbcuOVGxXiT_>IN_!vLJD`hRq?W&=y0&K)_%n
ziv4UJvjj~_xd5}m4Y3^YQar2dyF{K;{ri81#$%&|)m+vz4NL=8LHlDYNtB@t{ig{`
z1Q5m#R>58fZcb*0!shr-Ut*!uJF><}=*)(3)7qFrPxP8zjH4l%f%yj36(mp%0i9XL
z?+psx8jO_V`SIfItb^OuRGd3f?D07j?HSUE8y0L_-sYFD>A0MMKpZPXjT_p4jMk|b
z;=Z-wKn8j-v4gbjd$^tqYj52uW9&HgsJ*R_u^QdC)n#7S0t_q1&8YV6L8@x~`qK<Y
z)<XyG9|JP8uLZ-m@vz#67xSAeHw|Z$j<h_D6e?M#>K?IC-0AM{aJAN54E-CAbq3LR
z!M$|bV4?7V!dRK$Bu3h{`ZJC*kZS(wkpTW+feb6z6OL80!b1+Yl^Utg92+e)(vjw~
z3^zt@PAgahLY{9sp5qLz;kXyuA!B7$v;sCNL>sf&Bkc0(1(DqAXpD(ZYPBdx^}>X1
z{lS`B7{679uz#I%{A1I5rlO@ND$+tk{XtUbjb6q@MXa2z@q*>W{El1ZbScbW4ykJ@
zuz0K>L)70m*18q@Kl*=NR?65cz|@ZzpJij+mt>-`T3{)YEPGg!r$2E>q_QgM>)8v_
zngYZ5CVD_3c={)5B0o3Q_G@s#-7?3yu(p|zsMHAYg0!z@noz@4(1WO|OUQtsVGY-L
z3_?zW8ei1K-qth%PA!6w@wEakg))-J?+Kf~_-ACP4Yuk-Q_hs-gTaIL6mSn0TcFny
zmoP>LozN3PMS1|)Km@`TGa5znb3YT8#I82lWU4K0G#voNG$)Y8<6jJrKVbh00VCf_
zZwphd$F`UrQA>y~2#06;x3-Fx6pMf^(_k9aql?rcIH(tqW*R7L!{2Udl$lpDH3I!H
zgk~O794OUjSK5q>7PR-leL&kmnxIn5U6gZEw1!&rt;%Sgh*U9CaWgiqVa4GFsidK1
z=RY=FMJ=~X^9JIUp<{d#lckkM9~!z4p<#SAO1Z_f6%2)57?OiO6<}hOY5Us04^I-2
zNvbB-=`om;0O_PTG^-wYs*?auKqXfX5Q3Z<yNen2{kNqmnyqX9C_bB`(1Cb5CX5hP
z>ok}E*usZ25KkFsE5}{aYX!(<um<FV49dmLR4Qh`&ENb>BWIu;yY17B8Hs8&++rE?
zBx!{DDf!(jT6M&@#~;ntf<h)>Ed1kIAwU28Ygbs)A)1)L5PBv|H7)82Sa#qI-D^p-
z^q(@&<r4Z+m&ZS=BYAiOPBz3_j!UXU+!TzYW=uT{L;^m&YA{&Cf)fY9*t=yb8)5NM
z4$3ZF3qDXlnFZk`-C+USy(@EjcQ}-(bVYRSluqBDfg>%ncPZQHmuu)ugB~5KNBRfF
z=^m|KMahD6Z@}&ydd9N53t>GROa({Kmpwf_y`Y3F6$(QUTd<DfR8XG3NVtDnSSW_!
zB^+#d>oV4-P^Pyr^6`l1#kk_w_u9!~(vbSNTe&@^e~GhXfI-_bd-NYq2*u3*ZC<+8
z+Y=nk+rcB9Cd)nA(-j^q_7%cnG?uFcsq1ndeGBhnSHsP{M0j{t=&d`9&EHk#i&xm@
zI*#Yej@=>iQd|mOxuft3zBNZ*Wu<S)4)`g&>NLLh2D1fB@F3@PhH0FUVx{|W?|$5p
z>p%Lwmn;7czrfp{b0Rb+O0h3oOG8m>M>@iH_^9)8^@Cv{vyU>+_UpVtEr-c?DU6;!
zkpVY|ixCJsl7s|M0*#o)+&6BXafamS5&;{(9&#Ax5bMt#?YFiSaZIXR5GP}edN#LX
zxot<Q0nZLe)|Wp2F8n~_^}uX~?)1nX+^GI=-wX=e3KJMN*XkKTHjXW>pT4MseMwy2
zLdxq38J;s*?M`nysw-U`{b#X*u7qtzKW&XxHPtWt%o@}6lt(U?SYDNc0Z`X5n4ab9
z28_>m*<%|hq}W3HsI6`dnhi*tF&K9A)7pz<ibg*TYtd&Z_4FAX#FgGv_`?h-9<3R8
zoS-h_4z*(}RWQ1NB!iO{8WVMh{ccx71?NxWAksqLn$f*+Pge8GA67d|U1-`ugj$oC
z^b}{C%yybWg4R3}=14QkhL9Nx(((V(%r3oDA@;VTp2nm(ymDu(JL8Z-GOD-(@QI}<
zzQ})vN#g0~J953%MKD1_a|;A)(EYG2afEGAYFjbnLLjBeLyZ}(cBQvvi1Ji}F{ZEi
z$KNe7VvcmwYGa#eVN<5%3UeRvA4q&m?H;4BOB{-zXB-sBR|=1;g(~rh*wG%<VUc!I
z+K+X|t2W>BrfTd=SF91!;{y-LhmtZXVfh*7)kR$6`4rKT?xy#AP1*De9~*nT((6X)
zJ(R9=Uvk`w(rz&|@XN&@RVy{1=3BpLUS3r2GtB!@7_f29Sdxw)RdS5jq9ghh9oo8w
zngdznvx30JnhG}`F4}}iM^1OD7ThXJtNHOidVB8}eqsf`ta7&BE5BKOuW_XDdyg*V
zYcpGon6J-_zi2XXp4qWZoaZxxFHZjm{HAffgLBr8z|Z45KN><>(Ko`Gkh}`mGB(#J
zS(A8j>ja<YY#oRAM4B#bGUFe`9+K)Kj1jI9nJi!Mh*@^F`>|a=XE#~BId#+L%nwca
zG{jg<Jzu+>Q*dk%g{4ytOZY?-TKEq_Mnhm#NJ?Vq62%u=%P^-ayT|VE*XW%Tr+2jA
z=)4*+Rgc{_=Uz4nFz5?lk9cZO4{Z(zeAh;|*dCkYxm518ZcdEKuo=YFydspmFko7b
z%@W5dgobb=t4BWR6uX~IYbeUGRCZJg^#ZXb@+nDdKgFsYdZ<=kW`!BGW9O{be(!Qw
z3|MTT_Hx<LHCa`S!A(fRjp~4p$<#*=!k}YV+PLx9+{aZK>(s#3fKEjQM=)6k(p~jT
z_fP@v$-3)D-i0%+U5?JIJ%U5W_JKQAkU{Gbh6hEfx71kU(J_G3>6f59&g7TXDYPzk
z)EbbUKJ2XDm9~OnIE+e7SruzE-<6?65ETnYZ>?|$tK1Vr>FD!Urot^LYd^Sm6HBP4
z4Ey;o3QZ2K@kVfgZ11|>hz*CqLOm=PyRAFLa<7vFnqEfU!%p#_^nf^_A*n~zbcdOW
z<wgYv>A1xIFtrOAi>=?U{FkqG^yWLVgCRSy!*J^$DoFGu?20Kqic=9h12@=v>R!)?
zCdiFDW_C7=6>x|_(}ka@6Q;Tzbi$r6Na@QzotNtcdbgc_<X_@<6^j|S7_HfcU(LpF
zZ%`~^9TnlhT5k{)>R<W3AB3hJvnn$PBJ+xa6O^;;IWPmzyyW-z)(9Ir_H~YPNIS=c
zLb(x!ddrCcTV3hFH13ZmgwpS^h6z~|3QUvd_0XRW0Xc@))x%BA-b*aN+2t13U@m%5
z=62#&8|trrd_6OqCJqCy-WoC<J~sP&I(amKW;OKo)VbKuI0ZpiJ1i4zL0Q1ilo1i|
zwFzm!ZaRYyfswc=NV}OJQ$wh%TPVf*;{I!UQ(lpokg8!{SCRqHyqXOo?N#XrrtQOO
zihhX;(yYytKsdn>hXZFaML;VRWLU|9Vu37XUEIu{<u{-CRns88YGlM*J#_d8K?jS4
z%37lZSGJ<LSL12Ce%G8zU?6G4izro!MqI|jKlf;X_KlFHYc8=_>y!WK3L1xK%q#5~
zu0d~#7-@*er9i1s(SXsUdO%C548iY`kHdqS)3+w-Gq}`aFpMixLrkc`po3I!_K91q
z``HQP8I3R~{rNJCC*Ul492npp%u_0(dPW^!NjU*$GE^{h#7%)(7Wwk1j*O725nM>&
zoba`x-@H^csa|>*Yyej>CLe=X-Wo(g9lI(*1~ev555)b<H72{bftE8?&8wMmPOTf~
z!waM=p1=JHnztdCiLKCF?2QQ}W=WDShY<;Yf&@AYKzt1eq15aVkMKg;^HBw)Gr9mr
zJW9ogS<PShm@1)-v6*$8MBt`8*b=9b=mE)KjHIaVRwZ+5N-D&I6U3xjB|plD3|&QL
z#M!H`h*hyG?(07_EcAV<J0|XAD!R5}m_pSslg|)fEoE_MK;M!8c>Gs7Y629Y1f(*j
zmjb%sNO$x8P8Cxn{SO`9)e2B(k^#6u&ANkVbDm5G?iyF^QZ{7HTN55djMuMFB%iI_
zZf(PBiNqQhb{656iq-t;PsK}?qEWOJh{4(Vg1^nwOZH$6H7zUx#cd6MGV`PVX0fVN
zYNJJJyARcB>P{0MP&Z2Z2Y===mz`@%avU;eaH4N&svVo{`-ry0NCBA9y4Z^p$vIE-
z%%A!uP15TYS%P^CGFBIqT1z0qvOaPZ4l7F`d|{)i2GQe4#D}ub3{mt_hj7$S^g1JH
z-~JGK)E+Iktl`K3CyD6_eM*CLN8tk4!CR<WhBiE2;26~?5#MdzZS}#Z5M5G<MvFC^
zYWw!ewy`{z!S#h=+TQ;7yX#I^I#$qFqLJ{{aD-!Xb~HFvu-Wo2pvnDC|CM^q54~H%
z9=4Xf^=NZ^>B3l{%OeEKN``^N=#kC>13-)m<e`1xFi@7wk^0anXV5#0ny7V$#f-mg
z49Zsy?b=_wrDprv!VTdEj(#AhN9nbg`lIE&)|KOzHliJk!Ia-&HctaK(ZW%i?M6H{
z95my}Kkmyfz%>Dn(d$19OOq~lRusbRV!_1C=MH9#Q|@-MEQ%@+Lhqr*<Grbf?|VI3
z<p0JfC}zT1MI~z$e6Lys%NvTB|7*|Q$kF2KoPFWw23&5(ey_hbH^|m$=RNG&e}cQ*
zvuw0?zixJyOUJx}gHJfA<9<EW_vOL093IEv>-%z{aMZi1EU)LI?>oWQ?_9?T@`i^3
zLr!xkcJA2<Zf(lrA8wA=Z=|qxr*Um+Kk<l%Hu@XCH+RS6&0U{p1bq4HReSNh#y9A^
zx=Ie#%l`P<uCc23kseyLLD$18#!A_2b)yOQhU`d3L&tEy%?C(5<CuNwKB5$eP@gu+
zK?n8>#K2f3a;uClDm0)A!H<+XUXVwabC2HWyGOtO;9z?1Eu~|h?)$fL=|7O_Mk$P6
zFII?=x$<u=ff-_Cn7z<qzq)%+d*Yo0Rwf*9>02|z83^v<UGs=ei9SeQm~+kb_=1}*
zx0E(C!+qMdw|B7JelP?Zk4^VLPVV*l!r*AR1AHI}?c8Y9?%>36kRB~^KzdvB`Zt~k
z3fU330W!#7VSwT*5Bmv%^?jm2F9+*30dyVB=YbvjZUosJ-j-WV$bwW|kVxaoL**ey
zbT!je(Rb2*`hepe&3BcLRd3haSlb@yu`An-UQa+E9XztR>r6g+{j1*@q!jLks5Hr*
zw+Rmr2r@o6=e8}c4@RQ%z9*O<oNW^}2^2~}8S}|ue?<sfg9#3~Fwj8(sXoyJw?ANa
zy5@8=isoGQwy0hRkD6#p)gP@^IO_fAzq(xdYDXg|<k&Me`{v!1T_D4-b~H4XzK%lB
zo<d(7^f1$b!d5h&De}1CioA{XD4s$Au}SD_HW;|)9{us5Y{f1e+t_u9=49K^8*!$I
z5!`V<fdd%JyYENeX%2^Qo<Iw;Aq4@b_3Ywz5a%M+MJJv@UhuHo73Kvpge)2{tHujc
zx6PcHP!J?AJc@vzbkDLEc64)B?%1dQ5pk!z@GilT?lg?yfrLJ`X_Wu-^3JS|Hn578
zYvH&y{SQ^TZF-Fkj3~eq1+dJ^957%9B!ndnRYV2(@0ON0F>IdkcUQ8TU_}KMXaaVJ
zb)wYh_wL`Yha&~i9glp%x=M5NY1{dDbjPLie$<Y(9o^dvEkE*~FY9!8@5I7Gvh7m%
zI5EURYEuzQndTG~fvf=qy^>65zCCv%_RNXM9Zcc$U?d~8j<Se&M7&EFPK==3mDNks
z->xWN5=5Cpm2DjP$()#^Nv|`z4O7?uKOWe_dL(*sx)N6-RJ28>3XHt9hS$qDX&7PE
zh&$!2$R~_X&{O^e0>fAamQ}&zh)$HZrNi6JSNv|P^X@afIT7Z_iNdeFr|mevzh@VI
zU-{0>E&qR$`R$F*-M7j7_QuyfXMTI*KfkTt-uPVW2RyzubY6{s$$J05=RWDr6NyL;
z6%f7PP{FQf#-V}_*A7<Ase%vJ=KC>`<V?YzO}zO)W$w>!JozG1ksZm^U<f<x<Sam=
z5RMTT=P<&9j!l3|F|N_VM(3D~;cNRFAv|wT`LXH41OYB)3X-kJKk1ei$^0Rf#a2yi
z8^M7{z9l9B=jc%lG>+v`aq_=nzV|OQO~fDV`yXw|<`y|Dx0Q8aKVzg#hew*5UJM$W
zotKdt_c0&ej1`Ilz}T4Dq|{OqFtY1laBRWQP4(a}dTzlR!^#tf`BkSYqS=7Jm|2)C
zOkJ#wg4~_Dx2}$2!;%W46k!y(5O(dx!liCl^a}RbPyN5JwX*}}_6|G4tl;igft0}%
zMd8W7OO2#MPiG7rumE*)qMNnKsv<oan6^iRV}{e{VL)F6x@}xn@ZAkK8fk1GzGx3)
z&~t~7j=e-zyua?dA2Zt?WLwthlvvP!my+UQI3uVzNdu2*d!&%&^*5Qx%$*y?!z4S9
zao|<Cix|*eB#kYwy){d7T8dKn+c6eHj`lx{#FfjG=Oo?<=vj5FjmV-$MV-8M>k`tg
z^gtY?@yi(NjGfGqU(TG!GjQ770^z76s90OZ^K5XIiFNQ;vp5Nl>lxki)I0f=AP!+b
zC@Uz7cKo%VY=zuKilZ=0^X^U+oSZ1EFfh=l(ma=r40UW!mEXyxa=Bd75#5jGaffNZ
z%{FhT1?dxce+y=%n`@-mY@Tqc)}D%0W=PU4Rl95rdhD2|!rl`_PLaD_F5~VcF|{Ry
z&yjMg*|5vbRLR<!sp46biAH1?GF+g&#PPgW%4{79BevbGEkkv@aFDN;yI$`<#Q=mz
zwad;zljlNjBG2iVHAInyAumUzqZcACor|zeU+@W(_??`|A0ABE(P&|RfgSr)a6QNP
zhdE`%i2^&gE$r!LkEqMLzS=Wfh$gmHyn8#NLb%xr8BMKt7|sgHwcdZ=77B+Qd>HI|
zPEe*T_w}{?nrTbX;XQn5vt#Y4M>td>fp6`o!7Mm#RzYXbKZG|S(MMNXRe~Mt_oM<i
z(duz(J#wD3QW?d7tl2OFpG*@R%|E*8yq11qK7*-TOlKs~axlW(6cXdBN10t_s}P$g
ztf#yxDup^sr^}`x&6I=Gi4R)-*734a?uDQMaU9U9TETlkxwVWm2Y=iuJ%r)aQQTQ$
zg7FXG7)_1Az{*8I3f_vOZiv7ctpm=mP|e3&8ndlVr|6}^N~y51eu>qQ_N+Zol@>})
zEn8+81X*yAxAoS4c(+wDOecojQ|>@_M06RmIXU7cH;o2W1%dBW_mr)UD(nq8!HW7F
zk^ZQR{-}0j+=r@GR3SJ>!^KR;S9)%-imKY5g}HGUgY<CPAmD23WqLT|9AXDvC}3G2
z_n5{qx3?4yD;Xdsk^@N;tBN+X+|8)IVu}r9{KGtSfPH`D<8e2Wkn;rQ!JY~jlB4<(
zJIm?F1ag^7-+TlF3{ss@7?ve)rV|1wMXOo~(l<&LI!0~{x2CIBZGDx!j7k4ck;a0I
z_0#`C#m^5IjDhBzH#0-?wgt*<+M~*oQUsp)6!96Wz%5KSapw)0Lb;<-Eu#54NDs<h
zhAKL=*pV$;RrZ3i)_Z;4oJbWbOlT{IMp_lD;w`8@eF>_eiD8E*N1r7x6NG7{yP1$)
z?dShJhw7=v)D>=_M9Hf@UdiyKMaLse<zNa$3YIzVz2H%-6tAkXOl%o`%;ZkcKzrtf
zj2mu#$k|@Y2E`na$|_4!3PjbgUEEgfsra<q9DxWrgH?6U{@Zx)M&p4_kS;OM1PtGR
zw1FywgwG^Jx}%t$1b%!;YJT%iF{i5t%UCXoqK>-@W7ySp@kWNF-nXBk8df$P<LE?@
zmHQ4Gd)6u5_<Du3yP~f|BM@y@qm%*tR8(@*f@PTo*ztZ<s~i@(RVq$65dvYdg9-b_
z2P<xvzAkzoVl|N&Z<X)+r&mB+gK~@b78pp3puN^_=xXMK@h~L{?n;FODU-Yxbgb44
zGJ<kknlHGGlS>VxCb;|OuNcY}4VRU|w9IvKKSm!i%jNgU7@m>bpj$aqY|<+|NLeqS
z3QGB%VBB#mhqUFp>lrNIDl(-ktAb}^b$sQXzcKsLa?Gs!cNQR;b#(=Pz-VX2VQuxu
zcBxf5og4Qslf5V5B<I9K+iQ(Ns+EnHCUtL#>xy1#IM8BM%uH4OoTg(y<Stc3&E~Pw
z))0NRlg&`mim7HK1s0tqni;0#$3=eNnIiZxA0@oRn3i@C3!c^3Bv+fC_(GA4WdZCj
zTau7z#+uUZaSKH8e(p-EOp_cM6Me+aZdzQ65>=w)PHL;Wz`G}0tJP|`%yQ{yQ&+1{
z!3#0?tQv*Pj~S>H0MiaS)O6eY;J>hnv$0n5vp_@xL3IODo2OEql_JPLR6SJP0(GEU
zuU(GI@mmRCf922KRd{`G`F&nxZ}qkt@2S4%6*D(AqAmB1oQk$ISklA&yc)gkm0bOv
z+}H;8zpkqMz0b62yiz@N|BbItMpsuVcSW_{=(idJz0sj>X_fr?g8v=4J_2r6RW{w`
zU3H`H6+a&RlQ;fbkws=B3bicZ3bppIyO^@P>m+r1JXk%0kfLZq<|mXz{Ql{jit5~z
zpRRPXhbq0v)Y^7~s`XFhxgSVdmAi^w=Dwd=Q@ru;-s;siZh5HE@nWTVYUJ5dQOBtf
zCmQ4n7)HVeb3IOOW4PsXVQ;6O6#e<ib<x$6(Q~~c1KIGo#)LDo?Ae_6>9Ddlzv;#o
z_ueqMDYNCJ%D~Ka*E|0E3WK>@?cQ}?$@RpAFTJ|5rPc7q6C^r&IdO9)3?JNVuo#^5
z_WH%jRkyw1(e7vZvel0{UAKnO$eHkNr}4PY%g6Xpd=|oS&#Qi{xV>^uac8xkzkGG~
zbNxFfPk!;a(*vg`Z;otig^?%xBWr_kkG%t*sFAPI)oOm{<iybKTL12-99GLGIn-qx
zFxeELu&4j1lyJy#b~QNA7@{J)p<a9>-gVUBL?3>}af~d&s9|vSj#m$@yJ=z{Z}S`=
z4tFqo#=nLmuwCODINb%d{5I$7#o|pBAsOR2*}uDba_4iuRo*_ac^#ZQJi#g0{cF4G
z-Vt`4g{bdstmZS-@=&JCz%u=LV%qH3@!Jg^-yFh=B??U-*{JPMLdyZhVcQpOm?c7w
z#eOJzfU{mKG(?xiHox_U?<sekUFU@R!miVe!~TAC2od|n^xY5M%avCu6_h}AXEh9m
z)(LLNL;El+lwYkM;o#Ph4LwA66#@IGSMJC|#QyBi?r10zo~*)lp+O47+;NZBj-;VE
zi<0foiLwx2SH|_U$Kw0lb&p(V#~K+9ruKz{cRR;&BWM2|E@>y0Yo|ZayYUofb@j4N
z*M_>c#_!%+>3^|0HPt&$G1L9KMaS(Ecjq5=hBrG0{J}NDM?8+HbM&A`W9omXxaF2=
zwZD1=9}X4rJ6SYKj{mq{uX{RYDpGSm2@f)2)hsdHgrUNrQ-0Xtr!DM%v%+^kVDus}
z`^}Es`D*z1rpx%*p2lh1?QnR*;MnGFk2v9ccveA?es>O>e6gClVt;O5xW3mr?u_?9
z^<E<V!tz9MBNJVo=vY_VS>1tV4es%K{oy)U@B-vE$Kl!dgb$f#j)&DA_M?yp6`Tqo
z4X=ut!C_})LVwKnm;d6@iRXyx?+b@sYMARtOilCI!@&1e+J$Fbb?0*@VanalZ7-j$
z=ALvWc+rPf)P^7LJ+hY9XE+xi3EErnyEO?NJF(HrEE&9y4T<)*WG1F3I5Dy2wJqXZ
zp|!Er(1hd5h$%2&NafwL&Zit^_c1;mef5&i=@K!)v~z}(k9qtI+gFOkYl<7ioYflq
zIXO9ScfMLX<=8JYau4_JzupUu@b#eV9ee5Ru<_nXshSCQOje^EljVM=%K6D~_;FuT
z-6r29m=o_#vJFPpAzb23s0o*14ed}2(&wFn(yM=!3b#Jy2))Og>m6F+J+g(A(C(3;
z-IFJG4>0A=mv6349B|e<(ZTQ@=ak>)Z3xFV^ymdSueueDun}cY%}iJ)2L=XqV>E&d
zlN4*8DN2GK92rGihqBS|Ed*-oY3K;gqN7;GqX6%He-4*s@a*Het&h=RC$u>jo^|{Y
zqcC})V}6A>AcX|BlQ*G=4(B6Ydh|iFj;M2x0#sh8zEbfjki1&TqZt}-CzE$5K~6>V
zA6f1|K0?Ezd+G<Ie|*BrfKdWuf#G^&hz)_)*1vOqt~&IFW8Ng=>L2LcuQv{kcpO+X
zT7B!|#hzlUEz7Z#Pxk**{>AF%{K(CX&c+c!Y<*~?R8Ox7!o!h5v054scl2kg*cr&T
z5%FnV$xPP_4fRs~(8Fj`6R<NE5t7i9ZA(+;?ERbX>|FDFx$HdUz>vJF`AjeGCd6Vc
zDX2^){FtduR+(@*kC^B6&dB4v^$?yN&)GffHyLfYF|(tJJg5*jYC2&dn>RPpMxUcC
z#c_y?Uc;kc7#>GKK~@x|%D84jngXz+A0m|DUw`<{L+iG)Ant02zdBF(BjYwokJCHd
zEI6?8z#pJ1KU2(Wf~ynN{@n=ob0<HuZs+7j*;v~X^74|zx{Dby<^8RDE1p@L^3?%n
z*FZRw>CZ6NgJ?>#+5{ZwnnIKXVi!C)RI51;qw0rgW!z8`VKu597llAVt}{mWv0r%i
zmI;=|^|3a(+j+`=qSp(@divO%W7ngEd~dJZB2;0=vXs!toz>r4_pyBcL-|e?v98U%
z@FlOM^x9n;m{)M!O7VQAe>Y1@f2LdwtJv1wh;(Kk6qqE`yG(m9g{EjBeAsJHxF(mA
zF_IzH$SCAxZPbwYySDq?gJ;U8M-IcS`@(SJ8@$2K7Y`3^C=?jH-wjj76y<WtEa3yc
zmw&!|cmC(sp=X_koqdDdKjU|e+1-Q45U6l6sEBGW_wS5`*6ofkIQn;0qcYOm>vuoM
zj&1vDj+5fl0Hj6aJ>U=b_=9Qs<v>HXK^JU8RKaMj^eTo$uIud0Z<aEIZrll`oG)gX
z5}=R4pV%AN4g=Z#T?0eACQoM8=O-|ky9z|Y99ADo|6%2wRa7g4$11AjcRkmiXBosD
zgL15sX>le(%pVC*QJY0O;NYRGH<)JXU{EnRdKLPjQ5(5NE<1!tcjrI4EF380b~T0z
z9PMVkfiF22UI<}kkY(wp_SZ5|SRVR|@~!2MIeWr@a*y{GQiz&fd_wnlUL`Mq-c^gj
z{`|nM0q7Tk!zq6_jS@tBW6ZKp1@s74I1TpI_A50=lZlR$w++&qYqzm9am%;=>&s5Q
z7)=n|XZ^tHBQVT=v{*?(En|VDtvs}QU}$G!YdMSC!1m|Jpy#D}VG{O-&_iiBbw@QE
zx}swpl&wlo4#oP!VnGhl#-$_?-jWU3%QQ-eWdO1K8d;ak#tEqt&LA7KPwjk1c`FV*
zgA0crBtTu~pmROV@(P`3r+@dr$&A&1Z~pdhJyPVn&=@2@K3)h?R%vH-OC_I&P7P_I
z8j=9BVX$O}p^#|cnMuUfk|eNRghMsw4c{Mn%11&#Ca9w-HGLsrFYLXs9G=pBKY7Vu
z?xA)2*`iy|k+Kc4Z(!(HKTG99fijly#L4`+FQS(}n(M6H>%1CPYESjT6=NIFM#fky
z$J~XnxZ_lbm9dK1y)Mt5%RT<>bz{-8aojRzQNj`d_+M139fS3eAW5?p6lH3rgH#yW
z!%sYR*#Uapa<kEZ>-~{i8r}MCB95J+#p_6a-P>E)A->*K8)9{c!u9#}c{?29HO)VS
zA^Tv+-o7!m^QA9+e@jo%Dwm_l9ns01wV_%*k8;JP+RuC$V-}4<lb*2@Yi1!~Vj$@O
ze}s49wIYh`xDn&=4u5P-+W4KQ$u}P9bT{X>%3utBthbREjDwzJ$lHP~P%d{=5xt>x
z&N^pjZT-68!`dhryvJ{h7y42@2Q$s#daxAb%R3^CX`+8%U2Po!3d|R6d(##w1r`HM
z#MEdvX%yOhsqu^-LT?sEhCxBkXurq`CLDxs@G<9!FQg8ZAIl@Mu$avP@q`bFx{s{Y
z5r5CS2I;u2h>;TQ7@3&pe=!R0&VObd@-cFzuH~$2yr)O>2L;ySjPZ8LlRFxk@u6J<
zrThTO?OvZrm4j2Sv#QW6^UA6x??pkcEE;+^O#=uKXd*D8q)grro+oyHzzIM9qnBG-
zb<`w>^bU$IX=a8uh@?~*a{m=k|3d_Z?JmyUgu`Q=Vaq~llwOT?tY)I}kdxmzvIDJ0
z0E#Kw(eN$AS4H?kr^u{^C9`@_9xOl^iGd%+J;M}wZ;ZpN*vSX^#*Y1*lsNmqf9sgc
zcRJ1~-YZ7(+x6an=iS2G^=GQpaH2F)K9;+Vg@)twYdK|e#O`CSM9Y_F=QEQb>SxH=
zIb!uY#MmO)ubN*=b3u``+!Uk)8<vw1a4M?>CG^vN;sJxb1J)&w;+)DLCymxS2k*IT
zd->L|JbWfBpYlKKv#=UdrK<oVLiC>E$BKmJcQq!X{#thH&9#BkoRWnZAn`^YqtJ@k
z@Riu*Muk_`4eY88$?v{`#ldJ8&@hb|Zj@llvKf**Fbo_*G2#%Xs4=x!qsOr+D8Zt}
zG~)xLaE80WzmATM<~s4}4$wE;)e`KO6GuJS3hW`|YdG@o;<JbINDHhXPM~^yd@Tp3
z(AZc5TcBk>uBzO-k;(GJ#N<iQY^WhJ@?X3tBv3CP2nuE)VJY|h4xAQBU^2+1w%7<}
z*~UOaRBmpBU5|HPHgE=N#*WK1KHn%|^WKpV_Pl3`13kr?Dy;m7>SWovE*~9mhB+#Y
zK@Q9IB2}X~u{jdCF+<o5%?OeqhGK_<cPB%og`J8>OwfFUI585riQQ6@j8?=d2*NW&
zi^GGz{m$|v6i9_wOz<97s4RbdF9yEX-b%TO-pFEuJXhX&_qvDjTeVl)l^(?q8_RVc
z;XpZDjYUAwYCk_<I>}PfUq$bVHW-=dLABH7Lm|5o-dIYUml_Wm9}n4Oc7-z&8%AB>
z=|=hXaAd4-?eAVPcqR;GUJa(2KAxLR-y4jpG4Nn<i<d5C%9BI+UA2>6#C(i?H^&h!
zl*X&|Cmb~U_*&kN*<dKcvWHQHlpwfK|G@5nY9ub(_-g&ZIQ9T>V|9(7bYxjhV7^@q
z|B$aZ1Trkz$DGHkvn3Srbz$~ve{@Oblljvlsll<_h)lk&v9;YtHY+3}M(rt<syip6
zq1~rK`n)0E&wiQXj(fvLavU5gaA==W1C`In@UB)f<)NLYP7ds@h1P`O|3R%26h}I{
z>+mMCDyCCtLC%w?eB4LjBQj)-qOa1>5SRZcCq>{PjGQmseQ9;;tzk*uS#S!CFK-E_
zCDt0OOw0z#o`$LeH;*6?L-#uOIuG{_rh^T<2JCyK7pr?Kp5#_m!T`1?mc<U49Z|#y
zc5D|p>4x9nGHE<wNK!A|w!_gE3M8h27HDD3E8`Q+_xwOd^-l>CvHlkn$m(Lxg1`;T
zWVnSH!2GJ7Y^18r(CuN=>B9im<GwMWoTBp5{n-B!7FcblHc;JFt+KfFqx7sOZb7o3
z{~`ujjgHapRy304JQ4_-EQv6@D8IxBoeqqv=-@Tk{^;;JaVN_%rKYu~locItNFpK_
zmcu0WySx<d%duq+Z(%o>Rkl$*xhvXnir@^?D4jyF(hWUoW=LRBfX8X5TiPt`VkrdV
zz-WeeCpe6eiuQ#c`RVM5{BUZhfr9t3u$W-UK9*TW2AP%>fn|>U$9X*#>c_Py+$*L_
zSIaE;F)~Bz^2BHq!WyCd4n&QBptiClXheRs=YqU}hCFYx0}6^pVd$0Y=C+@{&gqZP
z{Iyq67O&Jdq`Qu6X60<Te?3L70}aG(YPF*lN$c-p%`60CJt(%(4g3%t%v~*OX)npX
z+*w1dW~=zr4Ow!-b=0kvAIS-91Zg|q8+88=Q?jwf;XSZ4(Nk`u!Z6~9_U#Luk=H-+
z=f|Bh<+8pHC`3kh&!!K~7-g#;L8%n?R_Kbz5B-%*H1pQb9yIYwdl*aV$XW=YeyiTb
ze5Q;@m4~kAU$-uwUk3*6D<~tg48<}m+$1N7r8(5VaC}gR8S^cUslXe|16WQlgJ;6C
zpC37%zdO&;MX2=g-p74h@Np=Y!>y5VsCleT4(&P>?x+Rj{0+PvbF9!O&sqmQ`J|As
zIN&MHXhi)x8(1hARChFjRTeM4;!iJLFPX>)ZkD-zFOk3y&O$h~5Qy*0LRCAKi;yKa
z$G_?yuyNLvL--zZ&{-&>p6>b)V;0dQB*C!UITFdZ?JD~?<=H)h*Z94T$Jf<LV^L@e
zCpnNlV!1mTWumz|2XLo5vh#%XBzs0@Neb!Q!|*iTpS&7R0co>X$hASo-;MgY*LmrK
z@9D2T$8kHwd<H`=4bK^q4KoH^Q?(|e5^n#*z(js4hdjCpI(W?aQx;0JL#6tsmAw_n
zR?63QPlo;LYFB8{A)<#A(WkN0WJE$P=`j;1gWWWvl2;5O;{;+WiJ+ixfaOP#`UgH}
zZO!Gg4r-%8pKc)qGS!<Z9@||E^NPvm%2m$u4wmml>u@fNQ%!VdL{jeSj#IM#rK%>&
z_*Ey=83M^H3MpnOHfa%7LgUdO;z6>p%;YEw8Fs{?6Hc^0_xWeu@qBr6{-g<G?=KLU
zhqD#U=_`bF1WO@J3p!1}y1SyN|EWAXBGRQ83LE*&7H`}R1}Qi08M9k1Y_&Xz<2=b~
zwX+I8h0Ntfho!}XC@xkka$tm0a$r<E78B<x;4xMwVHytsDJHA|!NLv#b+7%}<yG$a
zMh;Hr_#CC-zm$*sPvjGZ2(jPRJHO|QaMH#NA9vR13pcbxSvzp86+A(T`(emx3EL6l
znP4wm06HR^{>vB?U(4W<{a_~9HyT%hi_CD08MUq5mir#eJbQQkrRcCD2WG<WmQuT(
zy`I<sM5k%3o3Jo@(C3b0%)|qJ=k4{r`UYfWbhA+$<&DLP1ON`1Jh_vNnSsf&_z54?
ze-MfgErM_+UI!~NO0fq<BzMt4w4UZ0qk=o+(>M&|;GYa*^*CLx-|+8`=g&;=-E*%J
zl11J5J^?0PmhK7*9Q0PhmD?&CGl&6h0S;iV)0uGwbB!l>5#U%s?>G0s43vAOSY<h2
zKS;Y6QMo+CQaM>>C9Czq2*U=&Kt^k<g7K@2utG8@cgp8k8$@skCK6&RxnS8C2|3m`
zbjleyyFHSc+l8l$voJF5?W+^=*dS%1plAIV3^bdWgHR~2{1yE#4G>N#7w*Q_*%ywy
z-s^9C7>mi%uBS|Kf52n4&`uF(3``oXJegJW=9UJAq>vPG&7?Eg%(+?FA*_T0XI0-A
z3FXBdBCFPH!Z<I$ec}GifAUzzlX>(pcE-l1d~l4l9#X&nx1=qp+WhWQLwFItU4BUW
zLoYNoBL!V+@ZL5%qZ?Q#X&Ao1MxWU6+{s-dL%V7dX1zjq89tH%c6GHFJ6y6Ov+@J@
z8d>xn#t>RLFoHyQk+*g50S`DI`Kx!y1SuWMognTbUFXJ8uPt62Nv~%6ch<_!rncjk
z9?+|N`}rb(T=xdH#=S~r<82kIT-Ej@E<rY|o)lp){b#5<u^!8l@m7%TgY`dX*x8oV
z2tr15f*fyfoN$^$-&u-snUI$UT@Mw<&c2r}i$YLSB+o|s%JN0oSmosbv~O4-00$~N
zt2b3{s^A5bOIJjb;f`nmGlQrSQ(|mHxZbSfj2ye{ULU1wVgCf4fbVVO-~q9O!PH<X
zvi9vn9wIi+8eguD_rOkL*LS7)a)@!Sn?P<cE!7YX5x=ii|4DiMx&wUG-zn!n??K|v
z?C13r23v*g{B0E!2|8`pss4eT&kgNl%NK_R<`}Nq1kK?pg(O>CWtfUg^fNNRV!N+S
zRvK+01qZNTV2Eg2FYNuu`!Z!h!Ib0My$($2H=l3<E?ODxfZ!(w8pPcd7Gwi(e6x0=
zc?}o+#*P?_#3I@t+96KD#9oL09dDLED>0LyOAWHaVTxzraBlSLFc=gyJAGm!i<l9+
z?G7(|9{k)px2A4FrxNqEd(AE*6l0#mx;}0io+AO#eD$IH_VSqtR<U5bz<Ujj)AHuL
zs(($9<((C3U{?gyWSOF0UuygThEGchC4sRNid1qUjE`L7>n5K;rMZg3APnFJzWRD6
zdl*jddi@tpzfcv=ID}uc(S)v#cf1*@zqN;c^O+qZ9nQMU@q8{rlxehZO)q<OUN=F;
zSVixxP$-|7m@GLv*>tF0!F1f^BhN;ewfruaNqb|`5k~2Tk;Kl}b9hwDqvFxBeK{j~
zklA_l+EjJxW9tgJW2{BTVG20g=v(>0r9Wkdu)?NgN7c#vc9_fKT{$60d7~Tp@C(Pi
zJry)ED`=I&0YlEf&Qs;mKo<RzkjWL7@!zbU+TG?P0RB*Rko|WU%aBX+$lA4|!H*VT
zBfoLWFJH$DogT^E9(Eme2y^Y<+*KIw>9u8nS>2Bp711bVhS+2~HCer>d{epna)=;;
zdz}wo-{vW8xg{-cAS&%1sYWaW*?u{W9tNxsnqH-}o2A85U=8CW!RjtlWJez6vpQIp
zh_}D-J?lHF_d34bi(wCG7JF@drSku?_BK#*T-SYPRZkOYNt85Q=u9dt9H^?Mi4<Eh
ziD}@_ow1MD-BUw0z@Z61w2df~35;kPhkI;^G#xYA?6Ru6M(8mH#)oJN>zuWE23QK&
z$Poz9UT$nh7;+Fn78Qy#9rGl%NkZ~2vx!Uqvi2a36YcN+s%J0&2Bea+jY0QJcXhq@
z?z``P{O^7D8F4>}2L#f%JA&s)sc<mi#=z+9YM@O$L^98}2y!4zcK6Oc0LFXHM7wZ`
zkTd)&Q;oI875b45hnzclo3PSy$oR~SF?KEL0dDer6eS92>&J)BZRj?Y!8I3jKqCj<
z?%_%>k<HMIXtBi3y2Z&i;Yq6UsYS|8YN-j+Z7vIo`(KDatMf)_D}X+m$uZUuon)eb
z#iiKkn-<B83~yoQ+y{Xo2TMYg+<gp<N8I-1;!h4gS$Yu({;l5AZu1z51;-9=+(Z&m
z0Nn_^myeROLZ7G3K2s{bz(%a1HOmt51*Jh3Yg@;WIyC}p@_}=c1UguzQgpJ{vNb6+
zC{{Bw$20S-tx&0e+`x!2tpKcBC3K}_2<JU=@?A6OOFdAkS+>&59i=w60t(0&Bos1=
z81?;ati!3qeWAI#w;xaJOgIY!B=6J?QJr_=jpGjXmX;)H5zY83kOr}liT`YB<>m2!
z&x|u5%LXV)YaqxRVWCwDtIqm17Q*c>+~kZL+dv2xcqKeg!~6pEByNRF?i{TkB60lD
z02}T<H}j?9)R;S$zz21QTpHB7O174}5(~Q`!VfYfK}a!xcFeJK5NdPN9iy>VF9XT5
ztP@mJ1H;fF0RKVOvOeXY4j*&pC@MPQp7alW{r!p%49kyN#GXQiVxG-Y$U!1C2+^5j
zB%|n~q+7(d1nxS`-pvFB(5GBOcF~?z&?Grx4(N7@HM7)YM9i4MrF0YKQidX96>Pu{
z=pDRwCd7ux2`t4lGnxrWha!-1)+~JV`<pjxJ5m}sNpYh6N%i;^P90IH7&t_0&q5Fo
z9ZMTvPEz`dE`dwU=P0L3^+$z=No`_*&!EE2;^N^NFp@Ml1P{T6qKD)Q#9<K{>s#(S
z<bik4z*+!s4}^mcQTduu8Qj?TKeCaK+AILy-UO6c0!`sk7AjL=QZ|gm4?RdN**(|%
zraSW;WWO9iwxAI$JwDc7Ki<uPOECkQ%<qUAZj|4##6rbv$2UU@K{)Ak=$6q={u9P6
z1k%HkG5}nl`{uzKwEM+V-~Iqe@N94`_68oO0m`DOM=LTR(3$Rrn-hT2($}AM-(a2W
zPeuq#V<NHf(X)eKxDq%hejr9SB2gmR!CWv~2rKM|Olp|iCdmalw69|-2e2&FTO%+K
zbZAC$C=YEdoPA}fcz;jje6hkHk53CxgyVs)Hk@znh?@77?o~j`PPMBc@oc3C$yVFb
z!iSHBH)!F5j-F*&lEyOpgOuYEq!Y4Uuz`_c$^H(QLCpK+A*Y;;+?e!9^O*8N{{7z`
zexZb6#ztt&Trm>6E-+9ga#oXq1#ZNCi)KnT17_IV(K>oP@Y&3kqr+ZKX1rLWO|<ca
z$oz`-CHx?(%B(MA4`TVi;ga&a%e|Rg=!O`B!Pq}{vWVb#@DJC0Yw1WyRUsLV2QHSC
zToHhVM0>SY)LMMRg<IU&oxM8HhD)Ui+ZsT0@<o;e17iS2DehZAR+JS4%k#tVnK2fa
z;4!T|Bb>zKh;z_5_C=-t<>@_5oCq+K1AaXSR)b=gF;D|OLrTQSm|HF$3)xqDV6@ux
z!Nrmx77c2ss;CYz^ERSYM&M*=Lm{q(!2lDJNg-cHEP<?qXN0YYDwqnIpn>jDdCb(A
zdwJJQFE-z3?!@9VPMGl(SIZ&zA;Nrt<=ByeFD#>r@DVw%)%nbyovhF!0-q!uxPT_n
zOn#WqA`U+2kXb@FHG@9M+LI|ND3iGkMJQ4uI!I*GV>5R8L43=%-}<xnj67L7C>4mz
zbmqQNr=t88wgH<I$I}(O7un{RnV^FxnK>I92DHCcFOMGIQYXwbZ!!a0`2a%gSUM|Z
z`#=w^ED{uuG<e&HA;~0}MWQ~vlcS>LZU861GBdq_Kzu%--%{K}(HpO#@yZwf;jNoD
z+}8vmz>0T*>gVcZaw^FiVMN?_B8Rd-D#PAOlSEG0I7So>Q_?RVUr$L=6JJn#i``V%
z?`?v|OG&zzvi9UFJu466Dp91UA>GS13PQjtbyP$<)>Ew6HBg2->+kGgHqTw0d3yL}
z*O?Jgp1>ljkT5yR%<EZ#S^y-^x_g`7D6+M+>ldF5M|0Sww(#`f@3ipVF#2bN=`BsV
zy9EUh=c6hI?Qw<JUyc`oQPzyQ_iC>tg^-hkL}zGbSprf(v&<^X<3RCG{;;v+o~7)z
zN*yBv2NG&{YlTH0O-{8RNY8@dN0UFU9Q!UZyibw&^(?ej1b89535qt)f&sNz1z=xo
zY%F8C#6c#b&>ZwhhKg`AnObCNv5}iq5J0EQjKGNN!E5%5e{vJKKXZ@`7zw@5_Xjcx
za1J04f!sb*0)7Chm@6K0yD#;+$Jev(5(6>xSd-0(Tm$HVlo2>zmOT8W80i%urIm*=
zC&r-PkWkpyFcdPLxPvtl5^$NheEPR`Ou5^3_R>!ix-&MEBvfRfYB7#*?%Y{~bQg#i
zh33E1`y9Aue@q)6Fw^tokzk)ImjrfaU7$G6TrHqz%ghiGTA*f+S{_h~DMF=LM)vUT
zIairw#1ED0@Yc@_kq!<02<M`-2-CB=lH&p9r%%)+7b|rRtT$=wUfR)%w)ynWB?7!L
zGw+WZtzw)G?Dpvv-6G@&Go0N$6~Pe+0m|u)G_mEu>QDt{fhfkn<DQ6m3P-evEvlQ6
z=|-&6AGD0O7f+R^@}>XbM^BafBBngM_gE3+_NfSM**~sZ-ZyBMscA2vS9>$s%!0qa
zvHsEU01(7N4U{6gm`p%AU?EVTVl+blqzNv42);2rlRaQME0qBW83+@Km!HB?7Re4`
zEqq6$AKh+}WDI}2wKU{Ry_6!)6MKJBA4iCdahe~NSs<GwPk??28Kw-N_ENbCfW!(q
zLZXgrR>TRZurgVnBWDfACsHU9<wFeo0hEz)TZ{vXun|)YI-2z%MV`?|(AcgKuw0RG
zzd;p|m0%IbBYx65e|6p26KH_hMbOivN*cS5eBa`jUP|M@gIS=yO}>b}L=3BJAE+IW
zv|U&a$yvjU=k6AofJf<p9?{Dl{*b%DpwG-SGdwV>)LA1ol(MbVcG6mMiSz)RC?{Kd
zfJw-XMS7GXi_;IiaMNTSOT;FZ62FK4CJUpHo~|It(9J0ioW~{HN0(ne?e=PQw?D>a
zSQY`9`^$M}<Pe-g4V;A?hCxpZHm)@(@nP5x3B?Z!75hd|mu6q;ysu8{fj<i-=gwTd
z^DD!<mw@R|v{->4r_jsVrojP#JTSL36P3PH+*pDwNk0Z>CBf4-4+3+IRPZ^=mXQ59
zjJ>nF32{9j#-Ujn(W2Cy1Vb2^j{{L4OOHQDfaJqY&UA(~jln_QFn;w$H+k`cY_<J5
z4s5mq0X-z2Qu={)#b9MzSR=hR5)6!bb#y4Ku{V_q?q%kp$eP@cPjJ6T;)Dc38Dv{#
z4-f{)aHwL1pANAo6n~_H5@XmmvgFl7;Y0t@#<=_jz*gcY@xilEogP2}4+*9X_qX|I
z=1<QpmT<c8ozw0S2%q?Vhe|m)bCE2Yr3UPSRGW-8U?rFh6EbVeB$(FV52SlK+;iF_
z&+{+_4*eG7G<!rvra1cHvg>}T^ghSA7ar2zuaeKJ-38cQCj0lWSyxRKJ+g0i?}dw{
z(%p+AkGnlvF-bMsO^^^qEyUTr3UWMd20F>7JEn+rGD}?}9?*2gY0#X}FIWg$>sto-
zf~86P$l<3V`m<n-7N+GDpLLJa@B7{dwp}c_6Z8!@=~?$YmHZXRxRP6@><$PM5t2nR
z&CP5$w&4_MAv(ci4kmHy1aC6WmQ)a>{fN+{K#{T_%M7I??^Eop|Kh8Rx3Gw0C7L9V
z1Ho)9G^T9M^b%Ww<);*76jIs0xaHm*(S3;$KMwKSq{_=eF^el0oa>c{yDBu3Uqm6}
zVBFUvtAP$W4)7CoQjQB3lPYK|RY+~+3bav!9Sh9{F=ogya}tFj5$j1%@Lw#8v4Ju`
zj%jj~6~cqH!6O%#)nQ`rFtulcbUCkm^L-<KRoZ|Kb@;P;o&#*;%PXcJ6VC`-pg8nj
zDgVMt5!)A72d;a^NtvqSog4!)R|R-UOO2@w1)@1h7<2b^4h%YVMG4?@V88-W1BbgZ
zv7s&BmnUQ(LI{||{v(QLefg;ZVhP5?KRm6R9Oi*^ndKP~_bzTbvSHg;=@1|fz+(LX
zsrv+`(Wbh{C?=4uMTkM*bP2<ac{2}VpJG{P0}kZE2n$KBz`PKG2gAjz4Y}6^D^}W)
zb7A6PGTIQzIMKjxm@r1iIOrn@f<~UbtTTCcWQnfWLIAjE9QzS+>nXP_m~P3PCFN~O
zDLc`UwkDx?uVpUiswoqa!z>;|P2L87v4Y7qf<!n&5}j@`XY83nM8A_i|FhvG3=O!(
zB?dUVAVFX4kjG&1DFU%_o<QhgGdWmlc5%BYsZ|}FFX}`Zt~p#WyF~z<aOc4~%r9`3
zkR;8kIL8Q1()`#PDJzIoNG>OH3(qrr8SPr3@EcA_8OQ<e19rc7=|hcImX44!>(1HO
z-AMZmJ3y=`q*K5Lsde`L_F;E1-IG8u>Kx9FCUP)A>QOyP$;VOKeQw9O88$%NjB!i5
zX~K<`J7t>1v4@gOr6TbssaE853`C5VpQBe89SC4k*K3Tb5bkRS^IdwVO<*9U2Wr&U
zo!?R&qS2~S!lqjR#sUCRGriaSI)O_FZAg8<?~Znk`@l%#hROAr+7(SqgTX~hXW0`p
z33&2Ax@cUDo=75fljS@}03&-54X_hWjAGV7K^l{rIpR|j_tqzlA_^nD?@eN$It{b6
zVOG}OY%)Ju?y|qZN6kN1@yNQ)lkj4tllcq8?ubwmi0QB=Nr>1e1;^w)PC1WNDmYVU
z4l=fsu#c%t{thXRhdLP?4JEZSnLgGfOOGy!VCs*iRFj(%--#Ld82^Z^RZ`inoy>i$
zd3Unyi0sECm9%pETgHbx8Mw;A$F#?`CDtNtkIFCM>RC?r+sGi3uZ36}U%-WYIdZ_&
zO&_t%mdF5HG#cI5q(<ImYXrq9CtQ{|{h&9)0IV{!ARk=V*9iE?SON-fA9R^G9XfRB
z>GgY>8{K=gC`rpkx*c6k8I!mSH*KwiJG56ysQ`;-H;_wxPmxtv_St@+000P`3ynI0
z@dO+&*Dh%!fOK;pp;K5I+N(AoCuoBavhoX{p}J)H#S|#}H}jb_BB>8!MWHHu5EK^j
z6L-IRCR$?qO>ATL!IpkiYe6C+Q2sdZ?rsIs&OUGsg3Uhd9&yRyCuNV4mQ}ziXrR=H
zyWvS~(O4oihCVI|6O&Li&L_Mmc4RtbdYITGzaKM=Xr=R+KF1Vp7hHU%F+>VL(49Xz
zghz+oB=Z>Q!^tC9{}6xpvC7s;Q^ey|_n$je+Pjz}3hxN9PJoa}952E|tvoP)BM&(m
zxO;;PDJdt~G|gt+Le$eR7l}5<!h<2}8j}egM2#pIDl~BpQYpUdmM{K?FIs0*DVWGB
zQV)nDCyS%;N)%u@HHSC2Q~6|RmaTGA`-tMskx*Oa#IZ3+_ifJBN~09*o-?WB54=Du
zHxh4&Fj}VrEkTbnc_$N&KeXRNIGNI<SYZ}IPkowA5E6i_cKPB@|2aX2uQ%lpLf2XB
z+f0I5Q#k|+dk4?LK>WNq^~R!N%OstqBS7{FQfl3*=a#jU&O}o}G=cJrQ%<bYP>MFq
z1d3EV4D=PU{D}FQE@xzdP{X0N!yPD|axY%KOkgWHQrb+)06Q=-VC&<@RsDw<WC2w8
zrp$#6bBiSs?I@E2dWL=&pT`$qM*-E^$d}w&5$h9Tj#6T7i)nKhAL>mpJA92EVJ&5x
zWo${~2rz+&V?L37M@Ps|LFySr(WW@AN}QF8m*@WR<_#kt{G^Q4yVIRe8UIvq78>+i
zg)qn6EomJh&-X_M0srr7V)iM=tlk|pkkEM2nb$5UuHMsPFDWvv-Hr;2jSVEh0ha_d
zFokP-smwra)kM>hNDOI_S~4>OR<3f)@f&2yb^#5*B>s<EHkXV{QMQ!X&nQEq8mNGO
zHFu#>VYjVT9qYhC6Oh(9@+Edwy^$o3grFW<2#$A?(a}z)RXJV3T4=Jb26X``GkzmE
z1Z^sL6sxC3ARFG2m7t|cX+XtH2vCDuF<(L#jFj#dyJXfl-KYQZeUpDx!n?%KB-jNA
zM(zrE9$k~>q1-kAH5d?m%EsY#>7nM`i}$g-g)SkyN0Hm(I*kuW$_^WX6?w9M9+*2z
z>@-@0@qxpbLG{oQDGfQXG==+tHn40Itro7POfyY+X4r5EZl4?=LXvxvU-(fH@8@hF
z8NzWvJnsi4@1m8~Dgw~Sd{zWJ`uY*~-VHCZ&Na3q^nB&kD6`8FHxPeFagj;dU0g)3
zVbej3WvhS@Sp2Xqgl$Wu;f^F-L@3OTgp_u|Y*EYtnUz|E@rhvl($5Y*Kt4zs+nGbE
zJhMi$wIV2z4G83@ke^X1T?XTZAw~*^Sr|#e&N!Cag!bB^h%xQh0z_Uxsj$e(<nC98
zFU7-Hl<*t*28UruB!~#9b&J1>5JQ%|4w1;WOn>j-@T(Zw5^r-134;#Hm+4`lIeBV8
zFs#L<8?gt4ylqko?K-Q5^aDZY(S0qhVKYaG=pkw<0=Q$SnE=uDUg%@q(%S>D8=}z-
z`GQb}K7!VQU=`Rgx4ZY?c6L5JU9v&orNk0MEPx*#5m2&BXhfiDH}&8qOiEH9h+_u1
zXj={=504-Mb2K}UP4`!<NnA%GWjT6EdAYQX>%#5y{v5E>OdF^;`Om*`VFN3EXG#Vh
z6&3NHSaLPabI4?uoG12?w4)u-*>rF71$ud)_-R-Bn}FK3;B2u76kQWfqp6UsBrudV
zJkUN{GMjQ3o-FK4J{ayEC}+~%#6c({<i9$~hy3u1S+OYn!U!LN4qV>;&(07Qnm{A5
zr;41-@`7@92MPTFY71{Cwv|y0&&&t23q=Y?;d(Ocg&>+dLH;Kjw9!`)F#weiP(KEk
zPY#w9Suz+D3Nb_36Ft`t7Wd;wv2$+v*6$8EBSa!7Xw<a<qed0~7?mZc$n8YnaCaP#
zC`#{T*QSa!*mw=K`u@)Bg5O_X?IvBW<Z36<jy^WGv}Y(AP})!;vx24$BBG3`xZJ@E
zY{C_WQm{%VP1IFUNs1r?-El?O=wPSeZ723Lr;cm@mP<Hu&mW%$^?_q$FSQ<OnfXuP
zcCu)+GoI8FpG}$|l65eDq9&rq`Id53q9#g_C9nhD!^98J!mC7*)UnWFeg+H$%`gy*
zLBRqSKQ}Ia;zx#GiEOefNEe2gW9BvU<OIvg0D+yJ1dX}3)Wr95m^zX`P|(!;O>%_5
z?{2}@U{73zDvI)Qxd-|gbD8yO<O@B3o0%g4`$$AO%4fz5qf3&DAeJMLE**LNqh!PQ
zWA1S19|;pc35I2I^LIq|1gJE0%L8+Wn26mmZiId6kXU-AexQhCAjoA*zh-s1MTCpN
zqSHuM5Q8HdhsoX4e9$SGotnu^c|a)1A&ep1GI=3FbC6N^NY1BSVA%9STi(Be(jHJv
zTN!YySoxlf9R1ev#$~#dCW`>8DHi^cO`!k@?0ATjbm->g8pgJtj9jpImfrBqnha=R
zWHh}}$Djn(2lANDj03`QrAIs<7L<hfWJ(j#lDX8iXWYjhrQ%5Gn-Bpbi%p&EBw{_0
z6;aJKo~h)TjXZY*R4HxUa8GfP#Ck+3SCO!vrDf%Y*~~zMV5Trh@}c51c*y*PVlX<^
zSX$C-%CW*BLK-IQ0qW5qbqz|1spJkz^C@2loA+WAfY!kXocJs8iKh#(Jmeq%G?oD-
zJMh;7OKkEg;g4WLlL}LdlX*A`np$i|l3B<P`0DN#2#YM8%`ZY50l{*?nIDN~v+T_*
zCM-Q#25bd_5=nWI1kVH%hB98oOBBE;vg`Bm6TgdiaT@!Qk%BgVB;v0)+gXgJLr_OE
z?9cJpFIYOpDpbLbe$gD<tnDAId^K<gf|uwFF*y`VQ#eGseKm6l0YG3v1Qd&vV$!HX
z`ezw02y)>Syg{!Bi2^+RhXXsNriwS~APmqK+<s}Vdn*R9h=>X&GkHr;3ZJvNt}ee*
z3}~IHV4RqsNc${17fBL3YkVy%HK>$%FgRGuoML{Gk{}bXm2{tEh9M(%Dq57n0T@AO
zjW18X_i*X!*>?R|Rv}!)w5VWcW2q8gvMnZOZ{9KWO+roSJ;j(bzPaPt^=Wz(3_po^
zj9o&k^xV>7YGo+^DJmXwV+BBgk3=G|vv}kn2J(!H1fth+WHYY9vZn-ckse=|`O`+8
zLb!@dCWfJm4b;RLWWxaW5Wk$8d;tZC$%nm<NT2nwXW%IrOCdJZFu>Q2bZPkhbKpOC
zxL|LY9htciEJtCkl2Xu$2{Y=?EKd{k=JU-iHYT?Dg(LrXM|(57bAgDHS@DlyBu3c8
z-N$EvH5uMxC3c<S{b1YA`J^Nupoq6IJXXD`0pt_XH1pb!O>cn4#JPw8u3+Y*OfcH`
zFGhx)^{M0%b4kfj#ZQvA{`I?(xkon8<5zoTx<XRELM%6|WA4C^@nxQMfx{?OIg3qF
zwFx>>A)e1C^H{d`r)PJcJBw{gGMq~)mj-X{CSZx?Oq1C<%Rb7SLe1Bq&Lz&)9=J4t
zoSwlCEG2eAgBk6`er#?1f9NlFv|o5B>!m@Qh;9N-!iW@Y4qDNY+0~C1+9L`H`tkhE
zDDB#+vNA`)fXTn4@K=bD@MMKp5*W7f_w>AI7P;v-_q>M5vR?E2!*$#^6Nr5*tfyTu
zk-EO+L2xMcg&;qa+ySQ^>O39dOx&nmQYO1ziFV>Va6HWCl$4Zom_o!d#g#hKq(nsd
zr5VMM%nwTA>|g+bIlCyK0RHn>4n{4kjKYY2{q<@O>T|q$n2|j|9<R&*^9B%L>O^d0
zBxV9A5%LsuOeS~F9YW;n>`~&SPLz;oqo`7_Fs9VzDBIYUiC&Y4IFQ1!#IR(?p)ENF
zOqpchK)9N2vw~L*fXY)>jH4AzI~apm@b5eTI9-zf`Smk)-&^^``xfyx*dmDM!FCu8
z9w}%BV90tKahNP_0r^cGhHM({$3~z)9N_~kJI4{!rp@7KA=s#AW&oxKYg0zO*nfX#
z1rn5%2VKpA9t_}zWhF%b6Z{0oZ`cUr^o#p9<ID+e9n{|HVo3Vn4`eKLM}Z2buPPda
zSkETlUZmO>#}e8BYTL)r4<t*u`tH`f6}j5cfS1k!Y;JgfKg=qAJTyC8H3q{;Mz~&C
zEI%YKVMfAD41}2wJMr>`N9|;e$<R2&PJe{I%l;WaI!q5A)H6`mCLgP016VZ~RF%pj
zo?upSxO&z2PV0PYx`p1At{?m?FILi89}nGvCN6_jV2l6u0f5xw6fE-+3wqxiX}f~v
zGG?lyeB9X~1<cfcEW2RSa^J7zrKZI&!|{bt>O2R&C~CBX;T<DIuVy4N+sp;oi2r-o
zh!KnSl1Ap`A_Y_dWPLE7klfh;&AarO2Nz3=#pLi|8^GzIOLY=MY!z@a#l>*249gI#
zHS+x`;_3!hKTKjLYKIui5B{H<50?f_*Eyk+M7%+6e}FWQ8OYkenA3J{$V>Go?b)kg
zVu?=VZ{P_NkY&3F&nQWWHc@YxI9E4p{>uC*vzz9@*WNdoK3%$Y<eIH);Mh~-BX~9d
z3t7v=;;QrON$>3Bw5Q;1kYLj`6?+k9@7%P28V!kEfZsi4ZS&PG=8H%l05C5%n)TVC
z3Kccqf+3MwN|VNvPt6O%T;`Iu8K)&hub)Fl3egk>6>$lRyd0`IWjc63n|NU~00u{K
zYT5`_35RczkZBM%Go^i+=ZBZfP#%2q$_uUV$By2qA74k^%s4sjYgEL-u5BtaRLm3^
zCSSe<#KY7R1gn=DJ}!J|gZd9_>hn@2*nycO>>59Y2n&Y+HQB|r=*Ciau&G8ANvd&2
zgtHmU)$^3i^R*3P9P6zMOMgv-lmW>~0A2`auciVbV$PH{&!{qJ58ykf0gwBM7W$qR
zBg2FQXNE2COSq9~MT3)$yZ&K14`!66UwxCKB-p}2gA`6oBs=_0z;ZL+!}NE_HlfUx
ziZi7LYBiAB<Li+xT!T&tv<gX2h}iD;!!!&Sh3N;@k}}*czsO<`o8Y+6t{E(RVQ6Ul
zBDrgn5K^rVjsqfRVf}bA@3Ry&>c%S((qK~wBSbj7cr}lhF{8~e_3MXiCQYd#<iY;+
z&|utRM4B}d8)*Lc9#%cBDAJY?7v(X?m9S;@!YYS>hP4lZaSOOGzkp%zoy=7+F7S0N
zBUE%(hMlIL`Ww3`UIp9LA}~7`jKIz&3(Am!Uc{x4$L1#W1Hrh)YdV=bQ(<D*T&!Fl
z%{C)uvFaf%yZ(_$02a#aKl`4^B?O<1r)t(7B|D@im`B4SCWc?eF-fHq54vYK-!~w^
zo|<%>p!G_09{t96<ye|wH`Fx5GS0^h`Ao8hnNE@m5B=$I3W;Mt7n-l(Yp|U~3(!DC
zq6?jmC4Y#Ca$GYWts>d9X`ERj?L~7g0^DHChTPW=n0M49EcVqe-rU?qlT>~7xou~3
z9^6$(rdjZ)X(a71@wO(;>qr}uc<y)&2wUbA7j1hvLM#cGg1NJ4=GI1B45oUGwh^?j
zHi3vw|MCaqQPP}IFPM_q#`Pduj|fRx=I9IJ`;>Z#zrseY`1mM34S-CC^gDy?0eIk5
zX~b{G)P|`LMMCB89JwiDYVN~+FNV$dRrpg&HR~^#q_JHe4+1iisqMmNvN@UC22+ax
z14Gm3+jBD{W)TA|rHS>`$=u=6M7D?(8#5VcsKa2H9b+=Sfej$3M#p?lw@gov_U|mH
z7@T1sYxwf#_o7QwZJ(`1gZ0Wi(Gc8CPB_WY{H6`;F*QrfN=30Sb1Q~4-oQH!O&bfq
z&_z`1$Nt{%74ZbavS@{pn~~vU!?K*j`6hcsEU*l}qxz>A*P;S=5RIfcm1g!t3$g9W
zEEozbKfy1FbQwdv?;G#dc?7EmDQ+DIak<h7p$yPOD6PV7EX~Li^2j)}k=J;6{4kV-
zRTY0FDq#I!{@rH=lX!(+S41)WWcxr04(-Y6B`=sYD><#SS1ruufNzwTvcfr;3R)iH
z@+<V^R{<9n{_TmugsvryOc(=8s7rEOx}ObSr{N*Ad~G1I5W;}RM(Cq|@KCR;l4VX`
zZgTZ&`k}{E&tf2a#jjeK%&l0|u#un~WuD4Hmuo-=ut6PygJ#Uplo5m?_p(PIuz%&T
zcH=M;w=;;sg>U>8nhO)q2x4^ZV3jWOGR&t(N_I6GPqq9sa^j(^R_Py%3u7)JmrU-$
zU>Ri{FpRd+m%%Rr%$Vd1GiP+|%fI-jb+1tcW#sKb?OF{4n^{Q=W>IYSTA*1~<OLxh
zRBmc^d1KkY+dqWv5y*ql&A-e0GW!gjDkq<byhh=g9j?@n!P6iNtC`LePkO$EX=570
zKx9M`ph)2xuO_4tVPM2C)|C6NWb_&X!^kGYVGU{u#*~4f<nY9rZPv+XN@qtG$XFVb
zv{jv6_VAjPqeeEr1BJ6TjfE>q9Fl|YUjD=<$)LE$2rI#kgBhk(PXb^qBq|}Osm+I-
zQFL37yC*RGjRKHSY|LUacFid0tHjB*54kNS4#2C4iX_RGPkdlG&c|AY0P=N=?SwSW
z?txe4kRr<NQkB>Zl4N0vL^SHJRtaD*B3K9%kY<`2Sd)?fH(c8c-vG2pa_4W~)O5FL
zp&_NPG*IdWV&vZal|@1&eGbE|q5854y=JF{$gR<u7R~F*_2#d^6CzsE$4leYm#Osw
zy-~TS7?cB|+SnG-4Lm$JK+XoOD6JqfJJ?r9$iTwyKy<8(i9xRMkP@OX1@GVb(0k8l
z?VyWTjZ#EOX2)c0c|L!VB15t)F_RhzIIWZkZPF4#*|gO`keFVrF^kFqhkaQ$NqXNK
z?{Bi(V%4Yy7Smu<I_4F_{WviP%x6!kNvajnWelrnG^`?PX^n^GN|^j`;fX`<YLX-+
zy|a2u;zWH9PaF@3tzv3rRKZ~E!K2IkfyJPqWh?V-+LLA#cR<P4e+3~tuo+l%MziAl
zYY)<uvDu6Wf3#-2MDHle@$MEua4A(3xskczNOf?{1%c_Q7L5UM`zPMrcm|P+mxCb)
zlVJJIvmQYKvmwGF%$(haL+B37gP^@lj;UHA2&Xl$Y<y;IF85UJuRO$zG^!Z-<^TFK
zkkdGFT6)<S@v9_yvIn@aQmF!lDYa@wk7aKL$iiD$@HZNtc!l8+^GLt&N-kpa2jkNu
zi7DZmWqD&-lMhbaH~BGvvHGggV|;`fq0Yjp##Z__=%#r|S!aOxpb|5e|J|=yFbgiR
zu#vhJHgiam$Ys8pg^bX4vxLW0bWUK~7}x@l1LTkNH?tg(mwC5r`)mnnHs4Xa$mk?X
zoBwyt<l`eiiAXepirRH?m2APDqJ4gpwvz#^0$bgUA-fsT<l~A!tG}v~Dr+gPCmtfh
z@?u$&r?|7$3py<se*9P7Cm`uYZXD4A(+4Fwj66%`mUa#S{AvU9sP^7&kz_=tJ}HM%
zwhRFQJs`#4v1S(((}fc9q6-&Je#SBqBGH{z6b;O41ez3$vX4`e2sm_-DNz+grSnr2
zoeUhRj2eqVCF!x0Gjj@FmvJ)?ilW9~VwQV#<<-oGQmzn;Z<baID}V|5W6n5`p=eZ|
zGGb&{4GL1Tp+!AG>1i86O$?NiaRs`@V}Ltl^AQ^<w7hJtw9jvBxsb~x8zcQhtsxH+
z2S^+yW)q-+41*r4dhj#>kt`}G-1iYC<SSI$*Cxcwwrnj`rZ72HbT7ThxZ=h_TWJ9l
zUQw|9w|=vMmu<tE<aHU1%QPEcQw*2kzKW?b74xPb*1-XWt2)f|o;{_Y4&u(~){3bq
zTW|0%qlXl%v^5thhBZXts+l)G`Ti!pek>Xo{hK+1kS3FQNGchF=U5}WzDaTxMFM8O
z;<7l%Ju;d!AXxz`h;&}ohMvS4MpnoSxnUpBDMDC~g4Ttf^DTUEVRHuFS@HTAg2BKE
z?G;q5rfie&PV&a6FhNrXzd<m~_)ioXpkXoOz=O&lgRA&p<qxgS<O}Kh&y+IT1BfL-
z)T5~T&`VR038)4E#de{a6zhPLfth_zY!e~&HzDekmVzpkTx6(Pi41s+ht>e2MKD_F
zh3|i!$v2{LFj`4Q#$%$8f_2Cx=r%=a?d)Ze<*RNn`6`VxXbHy>nT>N{yozO+*jck}
zD5yn+N5wL@eCgMQQ)7FepF7!*#rXW-Q9wNHU?Fb4FNu?2s1KlRB9<yniTYOboyWjF
zG14Pu%xgVTr9bh(g@5&9JEAG2kr}L#6c_j%<vD=Rn0zFTDpgXZicFaFFo04*=|Hp;
z#;43{@++uHrj})B4*1GwJF`}<Yg|DbMk~%rtQX&SZ!{(QCu`l9VNyY6ya->`7^QY?
zoL0ijp~C-cC#eaFAR&Qz1hfjBF_rL{S48fh@7K4i)B|L{N`V}z=VdGzA02ZVJkl_C
zPV+2B8Cc*9%g&bIQ>@xUzv~Pfxyp>ygd`!g5i7*>^;p(9=8u&pZlz7@xF*)8KKmZl
zvD7;(D*1-}f+CM)peZK;dQhES8MkDKkc9|B&`}Oi23CrdG*~^jyCIQzU1@67FDCw>
zzc1|kiveP%SzTRHdEh;vTX@tdTn?6{q*{PVC8tW3vyilxZh{;W21;$eJR|0&Ys#$U
z)|p?kNRlV+f43YH{bvv|)p){kTje>x)N)vaT@DTMSz2Zqr8x`_Y0c8ynk^az=IPY$
zf4~^?nJuGYCq``<<G|=GbS=)f!q3WfjVF4Xd6J;7vXeTZDG+G0-3vCB6~Rcfb~K+_
zx<+Fxk8b&u#Cq-ummoFXdV1YthKj0!G8z*%e>ohLsjY(4JqdU0Y)lfWgBx@-Fp0g9
z+0-k~!UBPpsCvh?S&?v)N+cl(E+6~^av4>Hb!HG*YTF_%2aKF`ch;fGP7N70s+${O
zVpxf+3n|FeM*rH<g4?7p=jB`7;iXI@;|+(Hjd1CTayD(rK!pe_r?6fVlSZ69gm4o7
zNJfZ(xlp1ZGmO@vt_(E96Y|i#{D(hovFlW-m~=yQJ0abys9pwmt5LE@e8P+hj`Kg(
zCAq27mFbp2wYWe_CL^qg^{R2S=UPJ*0?SA(#`>SON$2T6afiKYs2=bm%C4DY%<QW=
zJX?NEtvbX`4<#-H!OPKetQbZKtiyQ8nbI>f_6WT(@5(g{^j{sn_JLd?RBv)^)3;uD
zk6~);2>Obt$*3|@L;^z+gWM{L7r4Y@i|o7blH>RVTr^|~UTG^Rs3HOxXC(7NBv<)w
zI-rpEwXO5F4nM%&ga*UySI2KQT+QjiwU9lTRAa^VFxeRyk_nxXcy9t2G^VtoI$ONQ
zVSUAwIvpHlMR{9l8sUK=Zf1<Fp{pB&-x$R8511P}P*xcDhg<m6KN7-5R)VpA#)Usf
zL20gamu$Zd#<4~5Az8(9FZWDW`Ak)kDHJ6}!0@0S%nI`XyDK!he1{wL16u$-U^*^*
z^H+xRvgTqG->7T>nP4?0Gn+<afRa1e%%&W1Ot2s!X+IcEMmv5N(QfQNBexac8t}ij
znj3B~8B7N{0r?hw`L&xle}PnHV-!=xXdD5?^E`)3!5ijB#KgbD5}Z|?VzVFequ@od
zTCs^ng8*NVLKzRqUxPOdV`?pG6oZ=(*HFK7$F=4rgS?FE1i<&;A8{^<HpZHC297;a
zxAap}Hd59pO}6wOk+73R!zkhSCCY=b8Lqmp1pskWEn`D)9bhC1#?o3bJ;?5GC7Vds
zT>n6?LVYxj+4p<jkG}VwB6W$FF2SKUq?B^eRGpRm4(z0!O}@u|o1V^kB9=m*vYNvx
zfu;w{qkyc0mNHEt4Ri`j_ijKZX$CA*l@|F_>!yvRyPJc#%ZOAHovxWXI7oh;%pI!4
z*70*^j@8)#f?s7oD9%X>I_F!OzfG{Q6f&5e_Wnq9nEvp@HS}xHx3$Ox0VU!Zy-WXc
z>h<PcTnn+3=@tj8T|alQUjxg&TpXmQ92hl;UZVtPNCJl*nm;^WVPn__S<hCckj`kC
z!c+X$#n;at?`ZbuRCs6bF2uW%dL(ewn<_Oo5GU}K`MS9ShQB04Tr`RPBRY(MF1aLq
zjt1nJ7%Gv}rlc8wI#^v=2k9?1uc|{@wg?eDt;OW%9m#(yzO;AC>&@l<pn7i99}G7b
z(0GDn?HHuIHich1$4AGNra_0q;P8?P_i%P6G+I{jSGt2>R?pTV4>O<*GZZTL^PME1
z+G1_$Vw?Vmk4BGQEd=Nb&ODjU{u_8GoL<51YpD+|9Wshcl`YT>S*k$;<p6O+odJyv
z3qdOSv!)QBD?-PlC1!e;KDYrIiAb_(Z@Ao84G2hBO?%&FkI*CPH2Xvd1mZDnGkE1`
z8yRgD-Ie)TUUs^04FbWSI%CAL&V)bq$IG1&nxzRtPF}}A600oz#5v^_3u57NcVToK
z`*0v5AFXVytZ49o3eRU2i~4C4xS6@N$zyC^_BpX#=29)8I^>gV|5~OFSx8!AS2484
z1hlPUJ)<NkVNKAA`h}>G?lOJBQd3uCR`8l}vzamJ^tY4Qf=uMy;(>gtcj*VOY0(4Y
z15sqFer-i!x@4SQ$~z%f0NWWY|Fg=Z@&#nspi8e_R&T?{C;{vRP9Avql@Cy>?VWjs
zKA`vkf?%w!7B0P(h|_Y?elt}+mGm>YD-wmKGY}*D3EqJ&Ot=w+DwcNo=ikjKOck;5
z^3uA2=z-a^6Voj(B6rLxuUUlQb0)3p?v_cU8Q?r-whVoK*dA$3Nr|(rrX31jH;pg^
zcYPaaC}fbKupf=YeTp50)zj2p%9hq~WZii@)@<{!F$D23GDA#EBSM)OGZJx4VaQsS
z&upQ|-uk!iA)%eR(MAHjO`i<H%X-H!^??kSzuW3vBc%d|eXCiM?C&<YM#3tL0;4aI
z$=L79y;^g*Lmjj$hO(7}Z(U^C3@3>*ZYZHmKAR~wg`v8i{eKiW!9%G6BC`sDK!%a@
z>fOthk(fz28<|?AOPRiSd&>xOTyc1m*_rUQ>JV`lEwi_uJaj9y^tcL--=%KmZR}{*
z`p-<L4*K3GS5rA0FcogkJQ^)JGkxzsEMzrikxB<pbLRG4SR(fnv5!`DE7KsTlL3z!
znWh3JbO^{>2N+#+u|gyUbZvmFgdA#rLiHCTY+8Ulh2IQ2W%n`K)%?nJu=KSL1QMRV
z<aY1U?cZQ~dM1)qv_5kC8m-UeR;q$wa(7e&7AKHSV@1{A^{gqhY>t+Yj?!qEs1S>r
z-ekPBrpRX5q0`K^BK@X(_UC_=@(nuA?TU3|wA(dC8>$)YuigGSLxM`qoJ-60Y|8A+
zuOEn?(-m{FfR0ikD8v+ECK+wJ+#$WP2qBa@f9(TiH^fQ-*<YKxxlBc$t0!<RIb|FN
zizuHx_dRTFQELHUk0ls%Xby^yoNm+zp7EsNb3?%^#L7Ci*3@Ymo7^pAIa|gqZTuH#
zI0;UExQEfWJYTEgOc({2BC**9lbt_uKt3G$IWW1wh^-3#BD#)shm|C8zTz-usz*ek
z^Vd>{zl9ZK^T&3g17Cby3F_!vP)f-JSY-_(05#1ih9(^z6b`8$EUXuUQ(WClvTCpr
zIt+4XxdtTSp-CDLhF=XO*X|C{CFFo8L_Wf$&tsL)At+=38X8%%L$ZQnN)f5%oP_vs
z^zMREV&M!Zg+cpR1(Fz>cF>t@(lYkG@r<d46xcRYqE_yqpUP3~oc<UgFfb$6>JN)E
z1<KK(mzPm@G8ULAW>z8-h81<#Vx7k%fr&6`>6#G%D-P0t)z;!_ScmS&Z{zHPfA}9?
zr$?*p0Yso?;%d7Vy@&{4st~Mfq07#aIgVSzreo-1Xrx3Yv<W~sT5gq*#K+4swx$HY
zMK$$(3>UHa^wNLag{iGBiLD3T(Heb{*NNB<L4k;pVza^1?4ejcj)XG0mxcp5MS1Wq
zagot&>a7VAYgZS)i?^<M2vERoGh5OUs&iiYTOS98dS?KDW$Egi7Vii`n_8>%hI9?N
z!iGQyZNtynGRXSR`XfVtZb+xlvl|E^Q{<E>Fyo~^Kl$>h60*o}5x#{XkrscZxwwt_
z!KsHl{3s8%+}xM2yP3er`HqgzW!-b$h`t-3=y2IUCg3J5{49v@-=I(oE2$y0orxKQ
zcmB^e-^b~)Th+z4btm<u0x4|hV8S|y@f^xJU$-;b6+B^_?(CE;8Jh~R@B+IVB|I4C
zK-i0XYxBGMX1cemVJ`prDNHGGnNen2M2zd19{WH!kreja(c1_daH!*)6s^%Pnl96~
z6Vk-W*~81lDA!69n=z$yM!yX#y|sE~f`<x;P;-O&c%S;k_iikWluoSb)s2=Ssc2MO
zV1N6Z9KTUD!)bX~2d25xm6fDIj)35S-ZKI;w?eSD6QIIQq>s_9=fXpOe3Pt}45=_G
z26ydxQW-1NHMK{3$$1KvRKY?=<+w0@#MM2VeK-Jgv?5W+QT{qbY>2j|Cf4?IL^Q)z
z-&g_NKV24ES5%*-@LJVp^d%NLP%&F?eYw8OokZ?}^ub^fzrzAB-ksro7J%HD6|ORi
zQxmy1e*u?cOo_9UAQ&Ec1VgWUWB`I?OLHxX3Adykxi?0+R*JZfPj|>d62gv9m4IhK
zZi=v5K)+U7o&z&IGplY)FhyL96jN>&*2^!z@Nca6533}`wSr!28Mq)+q?5$z14Ytu
zPgBZCEGAiDSPYZ>d`lY#q=00E3JFtUmLaJwg;bsF)jY2yWljBf_(rrl7=Gcw_k$cN
z&cHoT*Ju?i1Bp(v(hU|YlELy#oyGa>?)grUP&Z&O8ff4G0(A30OVg`?jL^4bJIH=n
zOE{4Fz|^6kk(I{x`_u0OV-yuoTB{=-_b^-Y&$-kkX9dQli}>;Ip#W9m@)47ju_?sa
zJhH{79;iE}OV_9z{i$G<^eheoXAS-Q$7Hw+2vWP2Am;0Iq%QcM>SKG8IdmSO(x5|V
zjc$-+s<@$gk~gRY9r@w9fxTjSf=t3Wzx2`XpDK-&l<zB1Gk;ZZ&5#t1;YtND={T9b
z<?}k+R>U*r69gG7uDm&K3z}s9ftiuFqX%ZC(i`M$5*Yo^dDhiPez_mU;5C!9Jhho^
z4BsE1uyGN~K<ANlogVfKd!2<6P|`1p2TA!FS7oL7x8)Gi5d<Ql=UDiIOE<ZZYyo~)
zN9@5w8uGksDhBWyYGXhWr~3%M9Se0H(CIqvH^40}0dfcJp?{B7%<@*96E+W+8Ddq-
zHo3BXI%_d*Rw_;Y$qts!mv4C&VH!f_lv5`R1zIy!%Tn{W8w(;+fEm6mqAHc^Q1VOl
z$HQmc4$+bT#8lxsQ@2NUfb?wks%MEqg`JjJnEtQTCk#u;Kn3wo9k;)km+HXrFtIBK
z+qE{X=%`R6%3jGl(UJz`*hj?(w#L7KX>wHdE*ZpZn+XJ#f(sDEM1?7{OAAV!i94u?
zcj}DN-%(<Us(t965yC+%uS^?rmi=5~=PrjP6pl|wAD8H3V+k6AAFB8mX_k3Qr1S_Y
zB~~s1DUf?3=|=z-JHjm4)lYCYW<C>$D|h<qgmV<ECrYdd6lUyq%@_knJuu{$Mbg=k
ze#*U4=GUR_qhSbg>ByqB43YwkuAe^`Yc;Dw|FAW9tnQJ1Pt6Yy|D|9429i+mKkafN
z{#ah%SU&?rLI$p6siC?Q#!&%#ihbzBd0gK8orLJKLMNI*7Tq$1G<{+${lC6L)>=eT
zOpUQB{7uEy50yZ6hK+$_vL;!6BuW55C~GpL<8b!iC&b<z!SDswnF}&o#9W6b_e!+9
zJG_CXYj}!vr#<!q0j&t-Q_&6RgD*$8gu%~V`WJs5KT@iIQ;-3ubHR}9<>Nw02l4Gy
z-8rVjFyfP!Rcnqd_u;d3W=yy@Vw+v)_qAH$BK=>PKtraulN)G^Y~6&hSusrLH4nY5
zU|%|S$@xcnnj<N>E@a|odGoRjl{nARGt6Y>t_wWK3_eSMxqFlm5Wj(yGA^pLB$lK*
z44!HPfG8v(AWnippUqodrE*<IGGoYOG=?vJ=lv`>C9W|8CVY+nNIGWy2f5&Cw&vJ0
z<yUG`ys0Qb+-re7uI7*($w{5+rrBDPLJICn&5N_GHZ;1fUr@$G-)1gfY_E_<mHY;>
z(v0eA9&-0B=fH;hyHt8`NiuNjl(I5Q&1f~l&dXC~ItNwM2l}Gg4Xl))-G)v)uI&;M
z9N&l7KoVd2<mY71a@LsCEYc7AXK;Q!9zCMgO!`dWl$$VTC|Od1g9AZgOdoRZBq+(k
zg*bWXd?rqh{1rK=yJT~=h9p92YkPHOWdFc<FL^@B{Rj7!?+Q!T$Y?Rh!c|L*dM1b?
z)%I7J)k_E>ZE?v?T3<fUlO9QvTu~*sN7r!lz8jDSZ(89`B1?bvfA%?EMuG?qPL3Nv
zG%7Y?2_cBC2uJLXy=KakB20&<;??0$by-gtjo=`9w9G`SVi#Jp%0*b7v$bRq3r?1f
zCXI6xzwjgP7npeEfzns7hcg{)GeHuMU7{5__QeoD#~tO(%s>(WHrXRi^O>kweq;I7
zOo~#;P^sys?tGt$dtG^488s@w%!I0Wm<80O`Z=kQI&4P6)rgl_)ckp+ZR<wTWUyK;
zY^YvoQNOJcX$o_iQh1WMRK}9IP9BgN6@mF-wAnA2%{RCc<MlM+t8cuDws^!Z{-<?9
zMpr!`rZF?y=o_(|8R#qrfX0y5=wNwmfV|5st{UVGG>g(~m`udxg<p9-OL<#q@CtR|
zsiqDCrd||QN{Zg1!DYH?kQyv`YtZ;gkK5bVTJVrhDJ?u(U*59r?*`FutB@`=nX4os
z(gUZf{cSK}0~l7wLq1OSHWRN^Abl3v4p(w+z_+crN-;`paszT{HyDaI4){bx<*u4!
zO<LuxrKN~Wu)BIWzPX9Rt_hj78u`%b=7tLw&hLzKiEnz5HmzWglRKQBVlxi~yQ4<M
zwo)&rW*F+`N+Ug5g2W-3u81>As&R0nWF0Pfb{n+Mi4YzUA=GWQ6~qx$9Q!3<?5&i;
za%kj<FBkUSf&o8Fe=Tosci8RG2}NApW)SCSanQ^xQqE$Kz|XWhYjbZ5;<y=d4ZGH2
z3YA&G6e&lAcH{oG)!dVe5DRS8;$nU(e-CLvd|fES4_<*zh3sD3T6d*C5na){9+OA0
zE4|As@+Rf3`OWosC(e0X*Z?i018Gcm^X-0%JG88}N3XCzq0qN}S~sU?0XNF2QS*>V
zz&BPshVx!gDo2+F+?2cV>`?QQw>;h4v}NAaRd0>un@hrh(yq_q#jL>#kXEy@Jq`JY
zoj*`*U&0gXdlUuA?i4=8cZeum8nfAu!sltiewoB4`KgoJMis$kv)yd9ww17)A8JON
z9YFyqvNy<t^yf>?u2wbO^c$6J)2+KIOVPyE2rvtiHj1V&O<({1I`!=Tm&b*l-f4z?
z&CMXhmA7NNIrvyKy6Pc9SFXInbr-(<znm!@u2A5ZVwp}O&sRiRb3>~MHXP<Qhi57j
z-1C#%#)_9?_l{=|SCCPjz@UxP-)mB*a3t^a{i!!vZ#17QP5FEl*EYENp4)FV_C;-W
z`q)zl)Q;VX+I!M=BXXZ?Pn1gO(@`$I^fzCqI89t5JDttBjeN|V)d?7bmpz?9cj$OX
z+j-X+PT2+q7tAIPCBqfpwyc_Wyh$C`B(|-e;PcAfrZ?Ye94ocyr8^a*i4SWIe<UBJ
z!{JTb=!xgiJ1kMI57_!=r4hW#>u^3EE4d82W6$L_RgjEs@OleAqYa)YK;aE-E}bb^
zjin8qy$7={nkvGBXDUs6J8sa9TVXCv?BTSyDXQe#R$Q!<;F*!{wDM8-2fuYVh#iEb
zFsp#v7Ja3WqsLCcYvmG$diAu!egFiGJH>%$G5xmaBg@IPF!+b_jLx1w%CK7iArnk>
z?1^SR@=)Y{*MGWF=_IF1z!yhLagqehyfsDPXNY$DkFBG`I^uw>1|1YkuSo*F0}{kZ
zFOJSm)q-*7Y&NuNtXhh*InQp!_BKD~TjfnT2^xsbRs<%qiR=nJf}UP(!K0r+qu@C7
zMPH}VaP6lGn>aH)=_H*?otK7>y3V9FNY2`BY$u)#0u}Eh`7kLW#2nvihQ*%f&)^#_
zs~oA~*;5JI(GEx8F_Jx;4L@8dZY?!6`)7D@r-~K-xsnxWjR$brJx#32TB+_pqng*u
zcW;{V0|;aXKlpp^a%-s*f#Shqsuzq<>GB^3wc1cUZA2zESKyB!|EHd(BPm@i2dbdB
z;5h6#_gL>a?~$5LwX$f-KUi|2$@)h|DxcdL%uY9lpWK@E$tRxhJ4Z^x>4I-X+kz(_
zYL<_>yZe5eKwQt}G}msfji*o#yitGsU;XUYEC<QkD22I{C1ZD6RDj+$Z}}vpa=Gg}
zPGF^bm~}KPl1bbGy`oJy&u=27L(ADVQ5c@OIhe>bP!+&vei(Tq{KpjiB+&(7Y<qi?
z*2Gbc#v&CZn_Or3@=xAw@rGrcQ5|4aD_||BOkJM?t^&)YWMUA^<*YcNHZ%|cODqP!
zM+*1pQS9fC0v+w1Xysv)I2o$LS$!ltG!Ad7+E9pla=Gf$#LZVe@-Bz#AR{wOwLLW$
zG8w#xr+Ayu4|zVC5w>HQMe?w?9_a$NIV`(VrJVS(DJg+stxOvYz_k+ZR-4g;UN;CX
zZP`fBSdz(W7GO1Qu2zhCqGj+1Vy3jAIn*;G<Q}~0shq0~v+SIvG^mzA&9ds;ZebU)
z$c2`<!0Y<C+I<T{nU>UiaApjrlJlx|xOd9ZVHDZjc`ID`O*R5nisen@5i=S$48w)B
zHowMpfI(tgrBgriURvf>b9PE3Ea8a<Pl*~)-$h1!LGOF!8T%u9gqtxkpn1S7>BLua
zQJB`_1wY_-_BaRDZwD+cGnx7hf+%~j+_-4cn}|><Yk2U`r-4VuVJdM64YO4AW;~?H
zgISVU-{CHhNF57a`}z0pfEIXUy2Xg@uSw@my+!1~j6%22!?bRGgX(55abSDClczGC
zO9M2DYiB;;XaE$}ci$Y)-V6@h$77|aEz{?0Zm--_clHtq|0crHLM4sl8AcfJXPN|v
zqah|J?r6F(R~YDpW528~(dB&^6;jtwUGHg%vrg)g!6RD!1@&opL6`3E4y)H2!tg+}
z<XAC=oxb%o_{NMrLH^p@O*b?&wHakL0`oVchQRdNkQ;7EF!jWX7VChI$~n+ja_Hyz
zGLy=RRGW=A{wZ|GXbs`{NaSEXO`EG}tsCosNr-6G1Cljqm7C_Wb{(y7Zxoi-t#7Y>
zU{8~E1-(ZKBOJ!$;M?p;_$={MPn4nH2e=^xYo*-y21Dji)9Cb{^MF`PeQ3n4mGz~x
zvsj^kvy0@${;JivoXXYHGw!C74jb^%P=P~%fWXh)aq;(`unv~6F-0L-L|LIpSpKT9
zPYr0~I2>Yve~G2((d;vdga*AF;1tCQZJf+0zlrJ4jP|sen<}Hp*j9HVMg41=PVBAH
zPJ-wJ>kZNa&fFMMj_P$NU8lw|PJ#F6i#b?Y3qwEJ(oxvM8Zo~xl{o#&KQsv+(E(3S
zsIjKkETwk#GFEDwa7Ie$f-{m2t9zSGc9t}^j}9?=Alj-X17)*cux;36Wp6INRei5B
znaBQ;yXK9#M}m=gf2QE<pTDc{;pRxYaO%mOy(vm*a<nXEe~JHk%~yLU@}09m>A)Bf
z&W%p%aI0*4W9gaH>IXPGn8P*bo%_khD$)Fys#G=}jUKB!6I6DB4)y;|zY|WDP6V?r
zN6o_c%aq+5UkL6k(TifR0fkVV2r8$8r`Xcr-s8UB`rkRGc42)Zq|{CD;xE2iz3s9f
zQ9CIT9buo)ZH2>BKdXQre~35>1VWwBVd%tLnliv}K#h1Ipp$sK{UT4*96N71deU~x
zKz#uVy02;XYgBHJf+`qfzB)t*ItNn9kk~guWp=hQvZZBx*=Bc?clz@;xs!QdG1hO)
z85A%EFFSiN=Xk3-gI=*Wnizm63;51f5Pnlc-Ap6gw5n&?gR!b(+QhDI)bA}>hFT^y
zDdmeSBpH_y?fO1HkN%=P=nHapmafnZ{TG42_?RsU%ThUR=9sHJi}51wpK@&wZNp8h
zeB4u>`r5Ea!SefBxgAUyf8E`p8PU!AUa4eNd78|J{OPib%4Q`qSu8}=BMN}k%0s2_
zv+toRv8}{9)FTajOFT5!geEhEPeU6-$A}`uXi{CY@(85JfYbVLfNBAIodiPrJ0rws
zzer8zT>mZxZB<8^5VR0;!rrHaF?{MF>-N9@o*fZB9ngT+<UiIRt+J*Cah`FxslJ+^
zRXF{0Mzl~NJsy~qBB&m0oz$;kxFh04-RVc@JFPj5L4DwuU=$u>4!-==n`j+WT{k@-
z5}S=!9Awzk-Bl}FO)F23D>#vkF&xnQyqeYw5Diu-8uA7MH}5b9kiG9~bcwAl@FAuM
z7pViBkGe1l{0I3j-Syo)jL)|jp30h)DBw>fj20!AP0^uZ;dP`Ht<KqOj<rklo+&@v
zQV*s`><Ge?|I3@h8i_&1PX(VfuTvaW1R<IQdWIy~p67E2bZefQv*OhU?rHk`+Q|>N
zkq7@53$EJ$SL6CyQ{VQI#gt#QGWbFL+NCnWKe2DE@S#l?yiSW6=2XOi>f9fD!n$=+
zz^(16dZpYcra{*JP#<f}t}zw2R#0|>Z_@YR3;*N$a3@tYuu&+5lI6GNQ(Yn1Dcv^*
zQ@HJ<1>ezki>_z-5x&)ktivtd;D%O^#sNLhQLH7p6ws3#rs!hIuaF_O8yBa4b5HZT
z6CbSH=I(F)0<W7McVD^VndT?E2h&fTe5Sd#dvNB7@OSr-E;I9BxG*yE>SzAuED|~S
z?TH8H7MzW9Z`Ge^@|yCx?R@8=n|_KnraOn4mp?o4!L4_^+P?hR)(1;>yt@1H{)Zo4
zb(h~iiwu8t{25+W-{g0i?{JgpAL1s@tbLQeHa)o<GN7jz$nMKC0XO^Yul<7`G2`Lo
zjm68qwrjf?PWZn;5{;s@{nFVxp{E`q^bH>@Mm-uRF_{Y>1lSC?9X?erFwVhrY!7B&
zQ5r3;#oM?z@tD3-(Np$dWv=m%)W7awj0Xw2LCap=%YFEtV-5MXx2w|#hh*4Lxg4Hx
zI4!W*!)hHdrBy8F7PcM7dpq7x)63PcIGlRyBb*Sg$Otc?Tv-l{9_O5i#P>)20G-cm
zok%`JIoKMG=bgAq&|tA1q}2T$?GEAjVE^?UulUCE@2|L!DgZ&SyEaD*CF(or{VEk@
zP{&3A!G>$gxZ+VnDz%N^+kt^4`8%9vx2fMvk}VjW?2#uwD_IIZ&I!5RP!Rl7;f|2i
z7Gp2sRb!<7Pd|?>Pp`3*01Yg88t!whwb__;au)F2?LB@P<GXsfX5W`+#KEQmQxq#>
zZz6}u1MO@sh0d7@i+n5HXDM<?IGjg5(vI&ZL9SVkgDyT?9Rb*PtP2bOH?p(LO5_Zm
zX|~Cw*2ppSafEGD4z1%}=eo`MR+(*<*QztLfN7D~#WMwo2%0yy=n8LG-aOsvJF_=A
z!5I=UfPk10p5|`}F!VaPzRwBso;^*=7+`=J^>W(z_TMfHhsBe=)8LE`xUXP!7yKj)
z87kzZxM>Yv7JZV_zW`Io3iohC7DaR$Cw+G_#{v4hCocygctbc2^`MSrzKCO7?&N+I
z)Tf3X1&G*_v}4Ill(Q}iJ=?nQy$UoOIq6&J8AxRX6fo~jC*|pGI9m)Mn5p4}+8+aa
zwaP(~YbZ_{=k|1s(d~_K+E$ma^CGvAyGlf4-tYU~P_1>w4bPNxj%W`X3@X-ZSjgqh
zIt((vl3*P%E2o+;SfW?CAozE0#M4a&Cn7xzX*U7b%-JdumM{+^pq$jp$6966gj;ri
zbLNs<z;-DtV!HBX#}D>)NZY9TL-F$zmk0u<Hn+C}GY6#LIpJKfmmH@dZbo5a+%A5C
zMrGdFO&RGE{>IRqJ&q}1I~0&2G+g&a8Tq5}LZ!AnR}WwOgAZi-cs7T$kKs$0VI*vw
z!yiEw3>QKxg|f5u+z@ku@50=>WJ>E;4c-q@b|d4`mV@U&F}!)wT%^jau!RqmFiGek
zNqDcr?Q^?4!c^;O!FN9xznoI{344J#YxbIj+gN-~lJd8_Ppondp#V0hVRzw*F@1Gh
z4=qFN1F@q{hOW_5Tqxe|Q~Nu~MXVCcs>5N8_UQx;G&Y^2g_q=sGK>xJWpGFU#?-T6
zMmSsN?!bW*l+STnCOHwOz*OJ_iLg{JnC{3$%Tcc|g^Iw*Suda#tqiBR;T|`~A*WS{
z$58D!|HN}FAbE!TomhPz;Un;m<`D@ASFm_MwY_AXFG3#=aF5Z%e$L&~iHBrvLQ5Cs
z%!PcD_f2c^>fms$<;F4Z$$$#2+ka=>NXVIc7Pv@!ghgZ1j#}fp(7~-@vcxP?e$^L-
zdjX3|#2jXTmgbyx^q+?KDqn_$)LG-7dJNstXd(HT;`U45d`+#VgYkIDP{7PGWkw*G
z26d&#(Cm>RAqP0-uDr+Wa#P3z(u4rXv1XVe&t?JF;eI~ROz=s7DmwI?_i|ea2aHHD
zqm{ZinC2p{GsOMqvlcp?<ADe@!_80?-q72z&vr4IHmoBD8)+>5rb*ttaQ6SAg}_5V
z@~UqqUSgkN29t#0a|0Log!HTPhZ;Mhdt#kXdP`;BYzuLV38OYR0YIH+P8d+G&Vcm=
z(}@tVdExi|3q&0<K}>q#+1wLx$ScM+jq7`8%y<+lTQGp$fj>kw=7?LxQqIU%FVSr^
z2KtOo0^h(0Cf;LR82$HFx0Ayk;Ti#TRdX?HMiX=mv5xwY^%j_0;GBD6FFhPML*3%O
zng?!<(Bp6VW+-Fc@-F?G?|bj9#Yf>zKR4^NL+GSV<2KM4vAd?wd|?wUxeoC;Z>VaU
z_B_T2iXs~7&ZLR(8@$0_&3G6q7hBjJ_x>oX5_ei5gEQ9<jFv$tat3^)TUb>N$5D5)
z{;rrC=2p6ZiHK1eXav4P2}tHhYeiG<+3nkZYTd80UB~Vsx6Xt~5OAUzD}hO@`cI=A
zIsqDT&QI(B^)MVJ{&62N#%PU2<ehr}Hy=Su{#qOi)xj}9f?1afC|3)x$jls!ob$Rt
zrxP3p|CMYK)6Dyv6$)H}kjl95u8ZB@qzz1!;qW;k9|`emz{FaeTcH$#J-oHx)aY5<
zVP72_dVs7spR__`En=kRE%*USm&5;<_-<g=xEoTwgDc%(dDFH*U>H9O%kS7shtLoP
z&lmzO;RYxbG=meob-7S3gjJ9e|F$rRN7olPSO;H#k!Jr9r-MJ?fOvFB(qFhTaH~YE
z`Bi`N-|LWa<8?6QuKTi_8RRl+2h?QV*9Cp<#C&BpL4^hO2XFabpN(}M_8;|ZKE;U#
z3)xsaShvPopJ|7uofEh#o1dI{vqidTdWz~-X>c2IX%o0f_1m3Yv#%HD$KuYn{k>^;
z>v!1B5}bOndG18NIKvUZTgv?XQA&q-Z*+F`yz|Mf*~a{sRh|e=1RvgsM|Y2VCZ)oh
zbzn?al7R;2_DAbQdVo(Fg2tS3ZsC`S!fmN>JjWXNq5bIxm)_%~L5-uL@SlqWxc4X0
zV4xJldS?pUh{Mw5s>Vmd#5%yZI3l~xn>%|b_9W0wU|@@+8eDRPf|v^r6uqYjN5KRa
z;0^N5<PIX9ad<f=hWz>>JYF5;KGa{8)5<r^$D$~o_8)rUXWpe66r*#H5<SP-;XdmN
z{Vg0#o7<oCgKuGg<C>nXJB7{2Z1oAZJ=hOEhP8z6gn~YlFmF20^1%A8eJad(N8w6t
z+Zm#xdSB@suD7to(y5a8u})c-4()>D1U~2jo~}IdEp*OqKR9=jN5rQ<jpg|u5utSO
zdK@%+xg9+S<)padLCTEs?sFkX&W>I`AWd*jk}4&Tc?lpD6#(sU4kdOQmxNraetL8X
z@|fn3M_?G?xP~6juV>x$`3hPHjEb|JZG=d_Si11teSm2TqabfN3oye2V?uFr2Y>=|
zCx?FG+jnF-+*Y^BOqrUpG*m+xAs|*2>z8>Ib-~Io_n?jBDj<L+#R{zc7E}UV10D!@
z7ivSd{+MX8{oj1`Cd3Bc!y?6gK&3D@B!Tq<&HT6M5=Xv6cBqdaEI;DHQA`roFtgl?
zJJ+n&kzS2LJl(Nq64RA&@}P~P<-sZv-uwj;A`Vig3?qpO){DQKXYyLo5RB3SFsiaX
zQV(X-S!Suee+cJZ5L@---Y!rY(oaqXUh!l=uC(TZ&Hxiy)kj0OaDfhSFc66z7%hE_
zvueQHNNX^GBDCx`h+6Jqg)tMT2=zjg_^YW=^&mXpr2S$w2Si|{r-F4bWK3tK=t0u2
znX>E`AUG-O^JAiem40}de!{)y=ECYOy4fhugVZ|I`523_Gt(CA5?CLeHq3YiSA>!F
z*E2)Fjg4d!c344du=(JY3y*!-;6-{OF5{%>t@&=V&^R{-T8?50*czaqLXwuqxd`=f
zlE%eXDKn6y#K%sBTwHfq!o{`^S{1m5r=|C&wBUkffic6MAbcga#*BY>8ufKX%2fY9
zRVw^OfdOLX7wW_9BtVxRp2iLhgp_dQi1|K$=Lne^cqPuANud__3dF<+3>ryp@PPwN
z1yAvbF{5jI!mo#?J)0IW{`$m7J^QYU|N8T*fR~Q}yj*rG05F0~{?l)?{z(Rz7_{Tp
z2f)kk|M69j$?phvIU)RI0Ga$whP(X6;3g|*$E~0pm&0Fw@Kyug{J~jsm*3%K<CpmM
zP6KybcbBWs8(}883z*5T2M@oIy!@FPz&Fc%8NU$*G|jg!g&CA|x%#z#@R2HiS10tk
zc=?~VGVG;#!eB3d{ZwoF`8RSM%@V|3^8r<5q3|LPQV)JL<`utc9?W~#Kq1CH^OXHr
zdZM*1`z?FcD&WD5t~@iJ+^CU{E7-DLp1-_;)s%2qe$djY$A$Yp5%)Sn=p6X{4h&5P
zryRp#@6p=abW#r!02w(yDU2Kf{jrS@$xMFXbi&(xzdPM6caog5*=0d<O`Q0pUN9Pr
zb^|yPw*qe$X;}`4m0^{jz2hOg6V_RXRv*R8U|j`v@lU=6y}ajGj_yc^i50+~ma_?w
zkmS->FbxX@zu(|7^*y9cW3gdzd9CzF*!8h>{V@V^KsVlyQXK*x<H}1~JzGOp2RcMX
z=4@=WzK{7tZ%-Au2ty467(xdZe&#Q%@Qw=9abpbs?p^|4g(|){Xi+lj)a#DoUM@nN
zoEdB`ybm^d09si5jn~UWa6EyDnw{Bg1+6&6Qa%HkL2fR~Ocw+Uo5}6_!bMoz5X4XN
zc&PRd{{FimE(<oe6|-p3t;<U9JKg6vkO+W;?{;&|q}*`|VYi61DBx$8AyeO{o`N&$
zcRJ~!KoQ1=7RoPj_8*#JJ5E4EYUR-i%`@*U+|<ZI(WaQMO(@|&MkhGz$AJ0Cx(i?W
zSrlUOxzYi`fY3L!QYhPf-gOsaa4*s%f@HWbVc$VELrC}<3z8T%`9$G}o8mf$37{F7
z1>WeU+-$4R!u6YF_S|jw6XkSk311jmhYnG}meUFz-=vsvn-ZW9#Ip9ObXCg<YhDuk
zzmHzDIPGq3Xru?>M~}JyG<L0<<YtF9*VA+)EY>kE<+N<W=$#Enf5QxMsGpEvS#y#h
z01QX3CZFuYDb{2_ifM&O*b{MPbK1?#F5EIT+RbfGh!>Jp;Da&6^AIOpxTTw841^t-
zwg5+@#(7%dhM|4HhRIFgq2If?3BK3)rONI$r=~yWRw>@^%<fG9W}2_I{ds@xjpRI;
zMMvude^e*(lN{uXRo-p=Q(s2DZ{O9M_q%($xCtXC`Ck}$He7T;eop%Fac87ATIzkL
zlWqyS`_Cs&KH$vm?{<KACj9QaAIyz~AW42QI^C-JOO=GPe?xy^S8XJ}i>ZFPa!ZGc
zYGj|p3%3N7AZ*={j)nW~ae}XY?0u17{R+aN0vEa*wasmH5{?;X+yO;kN=dM=oi_Xu
z<N{8UwI#h!!~Kf)qz({om-BP!^A%j?fT$}s!A)>dU-^sGG$q+FsPB5%2TEzhU3(f{
z^pc5_mEgi(JRsA^nRN=A*h(GPBLzN7=TLay4%RGpLvk?fIherN({XjuD9BNRK(tC~
zrYuj{1;mHlkK`@M0Q{+2HWlC{s}^|AyFnAECeF80mab%-6?nPnCVF(@(o2`*QcmFF
zIHWPCL?`OF88^8%zaUIpg}2>fK5I@3AC6KY&0z*9pUqCfG>Oxpxs*%-5H5S0l9gGH
zq5FC>Co$V%FeFDf773w9vjrdWHt?y}k!*T#+kdsF9f>)wGIGJNV%a$ltQy-b@mR_s
zFc*X9QkWhE0RDqES4#0=9KkdRoR%|}Ytc$H%dQ!#UkP_fYUVY@?M~Xv_eWSxZ3K_K
zJ;)<*W&*p_4%?n{@h>~EU6%#|v_NF#u!2JXWk3<gLmtXRfj+?woZ-u(!6~qZ>6X=U
z!2A6n@20T77cvo0Z-vd~wqP-0jg}c;&f2|eyWN5^NW9Q#A%k{-)!5b4rXO$p-uswB
z5ikKiBhC+9vfK^Cp0oo^;5Nv-3ms7M=Ya20c#xr4ahK@5=N}>9Y$GxAZSY?&`Sl7t
zX2R2aoC{hW;ti?Uv3C=f(6C!Szross`vkU?Isqvc>_tX6^MIJl4Ty<xBN!s(-I@g`
z5`Z|`-r_!sDFUREJdC?Iq(RVfqpIDE)l!@WGadg#sTFvL?og8y2m2Y~eg7FIZk!9_
zWN#;Q8wEf}6hL>Z4%}a`5@9t=98d%~(}j$>h)#wXApEg-Ay2!7^2meFn_hA(ULLW8
zcd1YpLlslP;$E7sx5$3IaNiaSgp;>%Hy9Oib-1vnlZ_IJ0>g4sjZa!hY(|C>3E!Ga
z9Orf`n4lq4b;L3Pf@mu^P(u?avV%xOOKl&*!d_>!80zg?3*c<Hd8j@mDW<dt{IAuo
zMtI=V$K2dQ111Ua1gRCvYq{i8lFEzpwPB$amk8;AO&Bz*)197%WPTF(IoQ{V^KoZ1
z@GpJt%{VBAB)V`FsG86`SU+K|bXOiJ?Ig&E);R{5SkM)=waYcP4Sl?$(JpJ-L(Q+}
z?rCxNyc6ytTe{T@+HN!S(oIj26Joh7h6(jsWVW@iK-PJkE)jt8%jzf%@gLv9mQog?
z4WaQ0m`e{<vOLK}hJgVF^~jU~b_!eSkrxb!X~l(`$f<4fMbC!%kX_%Pld&Jnm+q_-
zVoDu_cw9-qiU8c-OE%T%aNgg<nY7waB!$RoplZZ)XVy6v2D3r2fLNIB5WJWL0S~{O
zoDTiZ!JwN!{ExTV8{4gYA79uNY%Xn|FTHSf>-a-axXllq+BI>a)!sKTJyD%+wkODc
zDOZNdo0cBh^)r=SRr_(LJv|ME1<s_+Lhsragv1Odrcdo$*a}|PI`sK>xwA(JJZvEr
z(%IB|J}gfsv&G)tF2(FQvzLC4!5MSU>A?FmsUeSn$I>Ji>9ru^h`X;7S{rf7z{_SA
z!#&;GP;0gByuYh_2d9yAN7v^axBI&xE3N9+?%!3eENlf@s$n|=5#8fY9G{rzJXL9x
zH?i5Pxw~K4=Ox<1a*KD%@yfKdee{;U+xgwGe0}@S?gxMWW+y)18FL}htX;pu1&dN%
z&GHi~xwinhyEzN#4e9kCSxC1-uh;{4N)!uD=&bJJCnqYKddZ2cwWz(_-`U>w)Cdv7
zs=pY~w}~X>#!u>3r^yq)emrRL_vjE8+xs3yO;&Y>)lZAM(rJJ2mbbohQ@PoDlmt|-
zE01{YV*;vXhr&<0kG6ZKo$up3)75XdU{yW%(q&6AFvG`q>Ie9xNl=;_>IVnQ`_t;t
zU4R_LZ~PrDJy|4o1dt%DB4XR)&xE=5!=L@w<n+d3IC(jGsQPXHktqM+Un=j6ym_~E
z+lld`rTe1vnR;jE5;z7)BSH1$=wcLo=6J0*J(3JP{M6(}eBiB5y8XMxpMG*a;w#6C
z+xf<5^W-#$%?E=|{1Y&cmwW3A&TS!`D|Yz}0B{WFb3CyFkOpf!0D}OQ_gOmqE#pps
zJ=Yc$D*yqUGMmszz#zhx2q@4lw|?ce&^z%^KoZ*t5|Dr!#=AQsz>|Erd4JRzC%I%H
zn0zcsdH$;?8vkN3KJk-f`{AdA8|4sheNu%egcEIlYRu_xss{FFF5UHq^wI(70q`kb
ztk+2fQASAhQ9^0umnc!Ou%!zwR1TCxLRUdatdzcjX=wnz<hJQ6n?DS|24E2aIUGtD
z-~JA`#Foj*iTmBNmm%B`SxNK7yQ7xin(@z-cy%W$hPM46uFMDhh);eFFloGF_t(?Q
zV0<V}7mDjoWPsQc>)-8x9_|7t0!Fb8iJnSKg2r4A_O`GE_@qz;N)l2N+plB$vyYSC
z;tr4sl}b(ql)VzfQvRHq2(J1x+l%6t(T1RtAJ5NxDI!8rhNf*sF+P!}D7wA<gdypP
zz)MeX5wma?8`qGu<%J@j3GQJRB7_A8yYLfVvp{SzYO+BTn2kIlP`1r<Z2V(A97eu~
z8Kn^b{Q>TPYBD4`4B7+XcJ`{lS6rb>L6@eYgJFE)Z&g1QwLWf7{!J8BMa7QoLErMF
zQt2n)*5V|cI9_Z&{FIsWU3Kf@DSR*~>`+r(fzzKt69QRnf<>*@F0ZqyY+(c0f{F*W
zBo-$OAimG2i$h6&6im%}U3i@OwSH5<fR|%QU(;+QK|RYsikYOyYK?y}m`qRHPuf*<
zVsuBuMPxMf1M<;|c~6;XMW?l$L?Cadf4@~-$EWkf?fDp<WWKkrbK*_8*PTm$y#cbJ
z1Nf9Ehnx0M$)uVwivk8=6exqWc?jHVi?AoX1C$N1fG#1aP}`(G2A7|%=TJG=ODCcR
z!vSRyOJOMg1YTV~0v8jVUWqCoSCREF`aiKf5`@6g^6@<V??)F7{&7P{Abew0opw@l
z8T;_DmYP`v3<J8{EBw|6`n1N`mORs*S0dM_{b8jqSyLxLBjLAz>?z#@m$tcm9b`G&
z3a#x=DFJCXzbAnv@D`DaTxt8JT-)UGxb9CZp?JeR$#!HYU8y~}CqdpCP|G>sH+(x5
z#1!DOjxG`|#uiTqND?m?>ihKu0TFBbsCz2dlqkbvsuv`ratWqvqmbR8k$l!}hwkt~
z&23p{mi|B5-Uqsk>%RA#8A1x;I1O<HBV$C7=U!YummnpJ5Tl?xX@a>NQ6rd<L|Aco
zwB3}1Xob;h<4AT~Z%+1g?qDDRCKQph?6Q4*8vue7+EKO^t)_n2z70vyshYaamg2T*
z_U);pD0zN)*^RBJY1-|+?00B8P4ber-LvN*F$IFaVCK&K^ZR{%-{0@r3~d~s9nkVq
zS{%!Bc0D9Tc*jyu3=CI5@8Ic8`MnRl;~4r!cqSp(j>CDy+7Zl@L-EInwIEpd12)*3
zYNfEX6xOH{fmK!>gH8%G0#QX5AI@t6D**IK_%^zR-NKc{gU5*#A$-Ti4kz9*9argf
zI3pwHxTQ<H#Vs1djeX_QcP3u>V2GcNtm&7^{+gWWrv*rFYKIoyk}*yHSb-FRu(xDP
zZ{f5HyWfy8-S;yxrhk?K>7TSvH~iagh@!q(x$T~MNW7`3TKH)RQXj75i)$F{g&%$v
zG%))u`-h($dQbWd4N|Df`XP?;%WJ}{3lH_YCCpko$lrs>;nRNwi1yY&pksQIrHMCK
z8gxwW;UD_X>wHW!c;E(E=#zNB9Q=6?7?*Al={lNbugP+7`_Uipz<7M?5gtKkzxjW6
zhes+HZ@r9vF(`iFW9@q_79RSIN9C=jDm3^Yp#IDq*`8T+69_!v`#0dpEXA?A>iJMQ
z!s@xa3YeEOpA|>}Y{+?R0b2Ge68^Wzb){I4XYg!!CR#^w3ZR4s=SW$k<`00nnWQ8F
z1mn8lhC&;HHJ=@(DcK?7nhmaX%XC7<5h?0LUu9r48KQU^@&N{jb~mk@<|3D5x2L~q
z0T`hQV6*{?KCskm97fR|Q$P_NR6<!tceHMx`ftq$>Jt1%!F&et%0%HF0jGeSk&vr^
z#WdJ?Q`QVe%V9-uwV_}o4p;&k81W65{f;Rz!3qW`ajhyC19ncL21*<tZfuN8Tnmz8
z)Xjf)2R44igb{``gHxC%39I*qu|fa=ObI&l4&y46UuX)6j(8C<PwkT|imVm97T!=<
zVf}ebFpA|6q4a=1%nD1ZRi0hPY=~mEI^EIxXy`H$X>r=N%T3#3MsvuDp><{6J4F8A
zJ?{dV1nWTvKUe7@Ja}5y>IAl|S;d0e=rUPPe|UsdmUT?Dk9M50AO$0GgRqgLW@dzu
zjnxcOF2UpNu3dz&jNM*}%W<jIhS=p`qP|-Sy=cHqm~jpeXJE=(UqLIvJcOs+A*dKZ
zkX%^Z+#X_68(9n9i&x9|x4-pm_|Po4sHCV!*Vik$QyIDwFm)E!IJ*((3+DJm?DbWl
zm;2DXYAN1WCdm~O5DbomQoD8NaO%kXA^}M)n?iYuu93-435&lHOa_%BL4Ine9~2Sj
z(=E>KpMn$Uvx}zVn$0+a+ZVzA^s<H#R}c{isTF%LmTe7~)~$sdO$s4O<9r<Z1J^)5
zRQm9;u%9&-O$OjqR+}p!(m)|8P+^mOlFyT6F>MFi%xRia=DFp3C#aBDaSw=HsQKsN
zAer?cKLs)tsbGGcmP`~|WZB;2-goLgIkYUiSx$zo2mSH;Hco}`>Y(jhv-!6idlmju
z38r_N2H>axqbb_qC6x`%aCZ|8a@lXiBH1&xck4$NwS3lIpgGp#GmyJ!VkRJnsHf)g
zje{!Jpo&B*bk2Ma>7{+CRM}_wj63DWj?4N{_BgZQOjw{df(AjZG6x#67HdbyJV1$y
zh$*vYs46)D$X`*hi*dM<Nk53Niprs6M3pI)A`8A(J~ovbp{iwX5*2l9C5~!9k69n{
z$pIsKCf<a@4%jOm`W%oNJVGYwaFUfB0toobVB7W-^zKxEp4Vq_i{aK_zQLy~o%L1b
z7-(2l?@^Gp(7>=5ivVME%{aj9Iu0gG7h)^}iYK_hF@f)Z!)~D93YmgDvIx<Qnwhi=
z4C80NdgoGp2Ea%Iy&`~d5Fn(wf^4{V@tld#i<wh-3KE1$S#3kqYX*HEelw;B%r4_|
z&@m8zJXnUzTL%SO0EFiE$1S=Hp#f$Qg#%+;dmRZElSruh7#K0A4nRRTP<7Yq60ZgO
z!x&XAvo^b8b|`?r<4Y_h%cy0Q4^=pYn6viR99T3C8qyaAZ{CKv6>6^#e+ixVNC6a5
z<fmW_do?{H;AXiQcw|iX!jFM)TB@QK<%0a}zj{}gu+lL(GWb`_jKM?g3e*(TXd*cY
zGiuPC^*0zxh-KLD9K=i#Gj+^J>1i<weUi4%*BUK5A$--byXRfVR=2_PV+;<G6^9_R
z+TsCoWVq6R+(_7qxa9#wZY{!xO<*B5=KlJYNPydod^CzQ?gh#%Or8aQC5+1G-h_`y
z7MotNZi5GjTFej6ieVxZT8mQn<OnUCG6NQ5t28<s4PI@;qaLRbG)qMD0{#>#qX1pR
z12^yj3L-3<aSxcp#Ash9V*i&r?k|~rI=AE$HTe?J`V2&6K)lck3dV7YNgcCtp(Iq8
z_?A<JJUcgvKGVs3E!nqBcF2<83D(6s0%{}NPE&h~tbhUx;+_BuGA$7t!|aV26|^;i
zE*Abjt54wtYh7rw>B&g!q2K!@{5d5JG^nEcn3gK}5a|$urt}`8Rk-RCp<A&P#B@Pg
zXxN>?7E{^`=vJFZt=^&%!U0@wM8iO`@K2Lk>p(6McK5iC#!y(OfOeV^NlOwF4px+B
zop(Sq*~QR@VEaYG-RM;wbW*@?#V|)_!qTc0?!d?hhn?rcfDH2iEh7=d*M$5E<SnE@
zI34smcM2^F2o`}E;;wxiq8;J6XdVWrr@!{+%c$otXZ9&y?-cxt#O!7zXbKUdO%YO*
zu95RfeqKW>&_vnSy6*sV(~`tU&7tiHMNTp9y<}4$WSzj%YiK;50qObW;gCaN{NdUo
z7=^%b_^$~yu#U)b1kSVfw(osaxAZmI#c+~1VXrG(z>yW#ZO{tFiqTRU=iN05Xy@x7
zULi3@Vpc<+5o_(Y>_xhxQ<|e8t`mNqVM@S(WHw?QGcdjlsfAXqhS1IcNHrD%w3V)T
z`bmn44v6O!uty)Xl)h31GNc)5w!mpJ@)*s4?FgrX1ggr08mu5A=&t!ZqOz+(t2>br
zENc_f1t6Zq{bQVR71`?G;6-E1#Xa?KnPHcpk*$CYINbMc+<}p3fXE`SVPjJ8(E-su
zd|wE@(^G1#n}zW!lU6{mv8Z9#(MAlz&`6;HcGV2Do6yE9NUW~unpFjP2Xyod`&mb~
zDEDQ}iJ}!kfh#HEig4TUg@5zFdREz<e>oe2=r(7bSrnrzNSA3QpWEEV0PfF|`op=a
z{{4*gl0-g-63Dac^QlVg8~(vockv1;48pqUKAOCNmE`FZ1Y?!hilAhRnNOWJk7id$
z)rS>^-7o3jWRRT|*Z`8<^wR_G1Ey$Ix4Jv#5#w_`&d#Rqlb~(1881(#uMG{j#T7@C
zvK`7ci6Ai*Oi3oOuDRu8CL+hOD#NO$IV;jmS`5GbJMXo8IWM+kS=z8Jv)TOS);{(c
ztj>Gcd7*Cj*HzgMdI|kJO^jt<hI%fwNEXSJtb+VGZM0HHa``0LMou3ge*a)yG2`@#
z_yVc-4{pnDBRkA*_;ZAzIQ#+sNr;@w$13OZ9ou{gA+<l6>Ypl}HxZ3V7h4I27!*!<
z2m-cFTIRC6C8eAy3neS>b7gbL!;;jYgB&1KvSg++ke6<jtH6IfeG?W;$PCkMnlW8}
zqN371ja@|y>^O!tT#zaPJ~;XC=@}F>qoZw<I<Jf}EM#f_;e7ZRrM58qdF}0Ie&X$T
ziqwSg=<Wd^Nub0X=7L+qF)sx0b=KHq4ep=q?%|;ySTWpUxUnr>GVzSmxD%Z!BhF9U
zHE@Xdo`U~KRp{N}wOj8V4ndUvbrD-+pdAgJ0<P3EM+s5|e~<NU4*{X*eYiTd(96u1
zo*sQ10PnmBLNs`T+T^Hs%)BFYxprm2UL@yDFvxpjubX*%GW&gV?UP4wxMzCWv6pJ2
z3tNK0*Ue=58HiUx2wAy>swff^sQIfWEBDu*`EK~p7yj|)%>&=2G}3!8sY^1~yn$4D
zXDUbbxWx`7yFi|rPA)flcoO<G1P;p-qPUC#+X?C7p4E^pb`D{?*6TrM64_OyU%k?d
z1>%~r7js9U4uT!Tdt>_+z$X;A8^D-gU|nfYvCbKY^m1l83Gq>=|Kj9i#dgVxSzTo9
zRLGog(ydX}%Ru+W7DV!vnZ!qu6s_^WJnqd9v{DCt%QP1npESo_+&gma0l=gXF1aQt
z259s!ARifImz|KId^%$<I0s<$c5EoV*U(su6ag&5D=4E_c*n_wzyHb*62cb6+#0tn
z)%Z-ldH{A8?`4D7T^;bV>VBDls)dv%bzBAbxry-X4Zp0qp<t7Xx$S1algI}|m&~CG
z8W0>m^JU0FW9jJNs7T|};r&1{aLO+T8U1u;dv)PbGB)Pyb<f>JLfmDYMZ!f;X*r&1
zIfsMFgrk9xwt!y1GY=JEJ*0s4&Zh7JdR6wAUR<@oklvH|-1{StE@oU85UoJUez#G8
z6@^CA70$nnJCpso2z%2-LVFn^cr4(#>706&po_1t-c$%K(avey0yKW?8AcK%0i2aE
zfGul0yrqZ1U>9mQ{ZR*PzCRS~fpDEoVa7GVXv|_~GH>qYk*0I_I8f4lobebGYH0Dp
zK7JHC1fd*Llcsfn-ul?&+IT1}pxhR?-w88F6NtBx8_-R+7Zw?ckl}Q*i)%wb8og{f
zwJAxv-2?1dft%BV&1ps798pb%+tj8n3!AVTYSiz=HVZTc-CU)PV#cbuAH~BSKerQi
z?eT?=p`cQhy^&uE>}G-~;iMh$VSvk!v}Hrag}znf0T!H)fns&Q*`MuCDvn}&5U%ZS
z;Iu=f*&;K-6wI-Ow6Sl2hSE6n@@lk~6##y5sx8Ji&E8PgQIjGwCMYzwfwgRohswZa
zil2EV?9X9iSLHLI1eJQQI9b+kNiO)>!hX`M6(3Yp+(3X&oK-XBA@M1a+j+{7S)<4S
zJE5I(21DbhjK5n9pKc<}8@-`;`vZT3v&@3h8Jy+=PP-RaFMuS(iX9B9%L_3-{9g2i
z71G^KowEs4hww+c4a}h1>!7tPQ9^hxHU@7?r5}gG%|hU5T@WOC0I`b4#r|6Gcqa!%
zBw)A1ce;7B73w)UcrxKIt%$m^=(ISQPPnU{(p?MV4DUmqg*j2Y{jpDvqZ7g~E1;&0
zf}s<t_PP{c@|I%)G#~xX422w9(SusC!V}=Id9A0zF#9v@H_$Vvp7MbMNfaIv6!FSX
z#dF9rT#tT?8F%DP1TnB@Kn?ee><$py#_t<D??Y21(|QlcxzzTo0!G6eLdAmfj~Alj
zYLm%5XqKUzOWCktV)JswtfDcN8er1CRaULk(R{QUsL@goEyD0%kS#`#I<jJp2!Fdt
zK}xmEd}zS}Gk@FH<3*fbF=0Lr=`p$+Cf1R2h+R<7RIDlfge{@CMhdpu8c0MD`<y9<
zK~yLp^F$(*%7P!*$^81*x&TM)hOz1zfl60c>=Hb<Fu4<&J~UV8QJMh+;xWjh(wL9b
zKpx^DfCMZ<qgi3Td>DFFpGgxg8jJ>0xy2N@Wao*(j2S8po185LuyJJ}T;wz?VIk{W
zvcX}?VeV$Qs4cBZOYy+QJ77@n{rEfo+1&Gu^vyqh0T=yWCSJa!-1~*uoBu5A`D1qa
zh7|FqM1)}q=zr^jfOclDgPcM*=!dze;%5BT&LnI}xYgk!>}4>Uwa@^^BP{j1R_=H0
zw>N(v5ygxwz3~Rv&hU=aPyQLtaRBY5@4Vw@Uj6Z}9>R8Se&3H@`|%T4vOoKfc;TME
zduJZ0lk@p1%b~8JSuti{h&Ec(3MFdIH5JcH9%+>b5VFceF(X7CwY4DCN?byb9v$MH
z<Qzeyxk8aBf?i2|bx~yI1(OXXYwI2eZmiH7&YU^oFFyj}^R_0<p6B2|SrxGK3eR72
zj8Lzt9j0&rC}kl~>yZ3m*o7{F&YATxdz*aRtLV^=Azb~eiQsxbARs{g8Mf94#X*54
zIP$qbLE&Jp<W<;Ap?D5CJ_rx52rW-~6xgDK)6ba!$f}5Fb0`qY!YpI@YD47G<#7`E
zq*H^0MfU>rF(pe-jp#`rTBeN&V9bi*w<@0rk;Yc@1oLE6Aq0gRNh;J3kj{12WVEhY
zxQz%EU@KHDjF2Gu4#9xsgZkwt&V>TM21uWQfX7^rVKJ$K%dbl{VVlmlO}08{irr`F
zZr#m6UAZAJ@<Wj|FWXWrE}^{hXf+dn!4z2#*?s%b6^oMRYq5BZ#A`ak{l5d3obvr;
zXzI$!GSVU@ed9C)ke*&?BLFUIk<GTIUG#O~y$uYY0fSo&n4VJ$j6+;UF{E5j)GbJB
z;LE34>A+KlCZ+&_Sp?aG@K>>nL!1G9ChdYsIgbF5#eeXHk7yOlxMUmT4~Di4UM`Mn
zAixZzl?syzb4jC4jqxBc?`q^}h4yeOEvj{kBLwCDhR=~rDC2Cy*G386RT0z^d1r`r
zr0gE4-Bs&Hhr16+nP?;}+p*;)7s|*K?RTtU;ip@C%<80%x^R_QS276JX9L#Z))^bK
za901(-$twzvkpkV%Lmc`h_T0fud-oH!O^!Y5Ius959ipIS}`|QG|)h9n5jcbHu{0_
zwG-T<^t!!%tCO!YXlpItp_;#aY8sM*9h3LP6MVaH$5)&2Jy1mHIL&699Ey;PXxW3j
zZ8vF=@JJw%k!0otQx;F#679!WHr<MkJ(h>q3qDW@@c~(E$$R(z5`<=yLIvVijO@f|
z1-M`__={TIXfOrwJ}22_tbRkU`Y3j_DqwEd?x2euCi!L+VBF}9RLgEaQdgCnD}UJx
za*dDqvSA#puY2ke9Dycv5yi^60QDCjrS#Q0Xi6r0Y+)KfdQ<sYuxz@-+PvAvSWIYH
zh&+;+N;{q_W5D5V|4j@N38@$g!wWh<-Q?)pz!+gS0lCt{FoMz`|KsBr;i92@rejsq
z!m0+qwG6IoumpKog>snb5xi4#(NE#ylT6g3Y^@aGPE0*=jkkz=(a0q^3|~XAAALq=
z31m1z-V_84gDR>jemML!ELwRUcDgzc2If~{C~4WDtWN-1$Q@DEvEm39o6zAg7e6qW
z8oL?d3T42-3TS{4(mTL##Um#02Wvxp1@;xH@y}v{LYm(d53(&V2dFGD_R$DX4hblH
zbjx2sXjoAMG77bbjcl3(*ELCnr#CPpw6P?ry9M6cSl)X(=I4M|0RzIOSd1$M61hB9
zb}+0kZK3Tj8*^naFVH2!S!yqx?#c?}jrDaw8OKJ2;(&Ur0dSRY1-@9Z0;$Qe-y@?G
zZ_h@$r+7mrEzDinSA0+vNk(Me1^){Q!K~1RKs_Mc-4TVwECjkjSpw?n9+DTR^wv9?
z7r|YGr{o8ba*0`nWgxnH24D6c{w40CP~&(_2@NfVHbV|t80;dzz)cX{MrFNnp&Q4*
zAr7hFDiy90aJnIDt0<P2sl^Q$UYaHwD&pYdUYhD&ixW+jaKt)Vr5!I)BY>lT2bu&E
ze8l5`ZLeSb2nwxH%XW=EofizyEu`&MN}(xx#}diFl&i&ZNyLSVJ{Z%q4EbH4sm7#V
z(O(Q^iO59J^O`o8&y0&65i}`jL~zEC9hL*d9O9x}VJOG+oCO;<Si|l1^c*YWLNO{~
zNb8<)PdjQcJIYck!ZHd*XJ$=OuW^lUVji6R9_c1)Mx94A%P~fRi0BlYC@UCR;A+iu
z8MR8OrsOtfx?~pa#MBv}5v^R@72EbRa7S;w=`cJoJs!zM05#DLt`)JuhA7^8=35p7
z?F^&}!Mn84L2t}!ygS;-307qYA(`D$8UP-+KboE9=$c(jV|{W30mpF}a2yN`4*^~T
zD;IdbWDG40v0TW;Tn`lhw&L4>T@3(F)QZz2K7oJ}zwm{3iS8(_l6OM~>lSO27{XdX
zhvgw-<N-SN@B%_&Qzvqzik`^lU(N(hq{&YZp2Xj21mUdR%VVNMx<|Nv@f5;J7EJ>i
zYTKNp_!2i^5a>mKIjnc<9h^;g?=hpWz`&hk2EmM9F<yK85c~jaBF}s^2V4)L9FAms
zxn@G7#t_;IeF=>W1)a3#<0^!3)NW(Rb#P6Px?%m_5s^ZZ?3x`I<B%Qp3&)gR8!LtM
z9BAXQ?m;b3q>$bjo(`n$MQ}i=y|()dPD!B&k;{j(!`f~@JP;HN=-J_!!nZX-#6IOO
z7Z7qCiXh+SflCn3%85o-Dexv#w#wgz(U0>p!{2Od3S0=0qsJk~FmTKLNE0SE3^2^i
z3f2_nGK>XxjNl%b?6rUQl%^P)nb-JCD738To-W3H-i_~VP=n!|EE>@eV3`cKH;JjL
zLV<U|j3c;@-BA<6*Vz*eCntQ-77;WG*X?n8XdMunkIId>a&xSNc@Mn~B_C8+91~Yh
zUhBl06f)=~A<~aAbB;9HR0W-FjBODq1JP)<l_-oRGRH`zlqIS2*{}}d7CAk@t|^|m
zQJJJ4cI($$uLR2?w|fP4%%Mx<Bs(*4@pr`WRB`38i<2vd77{1Q^@D0mLcgdo=cpR{
zv$&g_TrO@m>zCaP;yG6hOifSJ*<S>yNb!cOmUm9a%h}+;<JmvtlS4yihQ!pc2-4Ss
z)&z=!<yZ;RIF^?r?+{rUE9bK`_}g#ZXrgXH_dKb5yq!r#Gk&QZoIxn_3bR)b_NuZu
za-4~Daf)Te;DkO;R!E;+R$EG<vLf7uKafwwqMJrG5C6v_ay~l(q!=7McT-&n(ywIr
zj<G*|>NC6B@ycW;A#OP5QOu?OE$8&meKh$LK;|AH|BU7<?0)wX=A++Lx5oI^co8WE
zLq#LW2ll&v#`8mG6GLS=Jv6mLaJbx?+^q=goTj2kKTpjuIi@v-EFN%fl>aShsvrcM
zmszbG63&AFqDI0DfhZ(Yf`urQ9am@8Fy}L&R5JZ|C{vl2K%8&^kLJz!;UW;*$ZsAx
zY$G26VDv<BuhS-b)n#!L|8Cm&ryUNl%4!jAO~1Ljlg?aqXPx51`7w8Q=dR?2+Szxn
zvC&Ot9S+bDq&^I<;m*bUguNTDgg?`41RqI3Y&oIS&r@5PZ!*&Zw|?DeDx@O<Sz!Ba
zaUw~R&zYlYGfQ8tl@_|Mh$B#3vcDAe?=kUGPslkTpG#JgzAUj`Tq(GfG0hr!_NY1b
z^v8xbjh<8`;MA$=r`>4pQ1$8pUw^Vby3pGu)3HAZAm<xiEZ-LSlVEMd{k2ffhT2l2
zf4*z@qoc{uKn{N2B)fuV$sd|WoO6fB^xf0W;s1I2OUvh-jzc!Zcb;=jR=z$m>Ky(7
z<`@9ezcbC*@<;7F$Y4Kmh(+%xT>i5g?z_8qbNCtTa?u%n3ztHv$8X>G6Ay&zBm%k5
zGvqS5i{zqNl?E79SXV5hVrK{|x2guN3?OKFd*7%J&~O|@nUKHjLNf>QHCzO5yd}%M
zzlzUz6bEGFL{Vmsm{%`#%G0@>H-jL89V?)|lvhXa57d+|KyJoIFNF%Z#F)ERwqup+
z!R<*0=yH!+CgjA(;SRPl!QY+1hvUEI40hO`Z`|2=_aI#Vj~rLc$u*53baNbNQ-*3z
z)j1UE=sLp;{Pp%<e#+8W{r&}tblK`16iB-}ygssM0>2q2$eEgd)CBW8-s<$U;X(mV
z<EYL_AHsMy8+@ep!ejhYc^_~bu<^Ou+<}-AbPXlH_6EG&4=LR=I}w7r>e!3L4qkrY
zoO9qzY;~_>V3Y1HiEAAG;p8Mp<@F!}_<4M_*h%3=6+8VO-na`ivh<?&`B)$iRPBXw
zu?kKEa3$8R0Ei0NGXUWN$nV0$JGHC?yz@#6v@o_1?)idH-a-pyHO?3~hgPc1OrApa
z*RvpF0Hr3|IX1ba3|KYj+eb5;*|kWb)^RX2f{qg$S5RmMFT{C^zR-aba<p;S&zU;~
z;%0kSI}8)QBgmgD??%IuM;zR@BOCWSZgtGD(6>~PKLQAQb|)4nhY<~zu32D}2H^GZ
zSLWY_H2b6+V=3vDSoS$U(lkMWN-qt87y~2iWdZ{P`q@pSN)W0{FR~jI6yjUNTbpIT
z#H4M$$a-^V)hvs>+UdydR|Du>Ux32X7@m{Ws0$k=Nld6`52P_ZKE1xlatPHS1LyGB
z?aw*^k41!-h9EU8a(5u2<bm5*NRUR5^}_(U<KiYZ8J-|*rs@25w_(eGs+U;LqA++0
zb{*EuIRaRjHL8n@<xJY#Kq$>^A|R>2Yt66*fOU2Qz#?w?Q{_Pe;{tt03E;_Dx4Hc#
zd-PJay<th>qKlCLt-XJfxz8yo8}eghx9@X=`I_S-yBa{PZ1j?M-Bx^kBFe-Izve&)
z;ueEY3AC0oy~Zv9xDO)^V)=lo7yic5U#=lIp2`W{1V7gbB^I`>kBcxwl{|wYZ&{i=
zNW04l+4dm(657-(WV&kSg<RK8=!Su_|A9M16(jpb8WAzhdm%DLPtKBBhbp{W_zcI2
zjGo-J*TFFLA%uA0*Iq1g<Yt`^$CZV&>=(WL*bA~VdIBb5m?Z)cXU7SbYgjeb?ZjUJ
zHNkx7(li)X-A4EG46gjkvc?RwW&;KcxHgtVJ+0cYmnY9|0Kq)V!XSh;vf!XtqsGt-
zk*0Ia@3P9Opt|f2bF=Wua75b~c^Q=kM_+UccS^{F%@^*}s+a7dq28(nSA?kmhhHl`
z^54Is5qfI2(SW;=9daQQLd9ZxUSd)5H3c1}u8?v99a~P~d=-z2ASlj(HFi=#J&riZ
ziDM}?YmV^X`f{umDE*p$Pz`sGu@Z;jVrV_bbT8vC2NJn^fh9$UDF}!smOWj?i*Q1V
zk!>ui7b76S3&V(Y14Q7O<>6cQ6H7H{nPa|>nq8S_x+0^92twVdaRl!|m`X=cTM40F
zRLY>ho>(Xuxf<^bpyXWu5vYc^-=!7Fx<w@D3s%e-0D0ZwT^sR^FrT1@Blcv@TtYKo
z9gY^!ja{6PTP*uaSR1@f0$3J<0KviK06?k(bQLhBzjlaTv#<U$m83tPsJ@v|{R>Lj
z{r#Ku@c#aHehP-ZnU?*t_3+-nvYm(iD+$#<TU76dZ>3X1Kl%m@#lJtTBL(DLEAaQ0
z81-lB;Xy}QeM5};^K_)eTbUv(aZL;GA4peN{xVST@bG*1OZZ=?WyUME10}}V=<pZ`
zUsi!RblHuq#%;%ThL-UU-Y{v~&Tbo>7LPS|6aPxM!lC1#eQyOr=%*e~yWset)c&nU
zcp`5-EI1--5AV$<62Gk>jPPVJO10nq*YC(dT$sTwX)}ONy*)YdvY4QOsyvZo*t8L=
zM+R~-j1XRj_1b-uMYov8p%j~w3GoDC5ye?n7!;vqj3*~mPPELP&yz9O(#6!~s@`4e
z+EGil?8;4bL7X3Jr^6C4r9JVPspMG>aoX+{mrfpW82M^Y_NTd-FShIl7GPm#Hm6#U
z4z?!-LoRU^>4Aq;i(0CksQ5?!aovWL4L7D@z<oZ8^pUy>RUS}Hy3omX=OHuGdVIxf
z8BI<4%yN)lz6JJI$*=n;qrcS*dgJwevtzBetbq`q5M$D{oG3()oW*N!{fo%CBpTcb
z?5I&#oy?wcvNR%re?9@m+lh|{rAlW)hE8C$ilr7&P_(9X!{@ge@3*2!e@<+JI>Sim
zW<eU`Ewp)_WZ;6+E55D-;Vch9W5UQhUa97ag)VOyn3zF|;xRz59u#>u6|F9sSKJsX
z$3qGV5o5nuoCq4rQ}BV>@sjhb;OS%j87RCols#%3^3m3V9CCcX-fU|EI1ebLEZk;k
znwsWe)sAal`5l0xIb47`j{-%3mLtG(J){0cilEg*E7l6U6_NB;S(ElngkA@yb+$U(
z7zHTIRoeq)6dxjxZrJb&%YNg6$x?hfXZ0>7Gq3v2LVWjmN8kO5I~mlSdHD2D6K*Bs
z#YKn;C;a@gT&;J?iFwlvwmGf@(PaF=Ajn2?O$wty8-sEzrDO7pWN%+M)C94*=1)y)
zJuRA)jvJ}?v%F62$Kqy<&0!;Ch5a#s<#nq?cLl?j#7wq+8WJsV6x5~{b;w(`!50U3
zhMN!PGZ`37St0Hnbv@S{f*Q)q#^zmfT&lj<CAZ<sWBZ13Q;t`zwOf!KHz=zd$DG+r
zAjQ9JCo|L#Q<jkfDtzs;AA+XBBy+hFEHh6?ZfiVI3aU5!%l>RX6qtJA5=Ka-9}}&*
zD-VS#^ZfH9mv61I%5&L)$;z%gWLWo$sbqvPk*TfbWni%zzN%JQcFw_4a?Ht3HF6^H
z*#0|q&pKOOH65=!nI}6giQ{Y-JBB@<m{jMUGmRGy`a^aH1Cg(aZGG}&x*gBduB%|u
zpO!_&5nY%<;=7wwE$(5(h5K1qSN=asmK`j{R|E^5o?{7;??)1I8aw-(GiDIIHn*Cm
zSHuYv!^!sNpC+#Fr-o|%W1`2fj+$4d>`Tewk+DT?-_dx&%$<m*o*u}~vc`rf#1L}k
zR1O(~=cgtxlGD+k=Rf&23dE@uG8jSlMxBPbHD{U){|PbG_@?W3Djzq7o*M8--y}*Z
z#mRA6r0Whvz0-87$sq1PqqENsP!M*+71(Lir25{!eFx^!ah9nOb0r3FZs~wgOHhte
zA2kCjInifm%v62MU?Oox04=UBp|ygTdorwmg_EJY(#5upX`6k~H>r{lKtaKJx)h>I
z!lF#qri3s19yh$9Xg#uoBwW3y<Gu^vb>1%Fy<7vUM8!TKP9A;d%R!5x;v>^wZ&=7Y
z??di~pb6q$!p3U_(+^`4#V*gV_H)y#K4=5YVE>7-kJwJEO<^CPMgerBP)*)}6&I;K
zx)o{oOjkK1blaL!a3U!FzyX6(x_3+&Kw?za+~x$d<u2BTAAR;+kc!Ia&L}1ID}hnS
z+Ni)BPVHQwPNQTKwpC#pYMA~_TGv$pbrTThsX^=sV+fGS)+~vV@@@tTk`=@k&<IL*
zr`R<gSaA$-0>d*T!$b!RxmKX9+pt;*k3|q+A+N3UEyXgr*a$YP#W(vJ-5iTU4Xlg}
z#5J~v&8V81o+mVA6l#>(zA?idU~vFG+z2=!TV+rhhJ;;gH+g_`%}kqH5tVXW!;8sz
zQg98qjfvrQDYHO2Nnjs}RvxZFR;o0(lvWpJ4O5bR41zoa?f;j5xm2@^K6w?Ds|*76
zgOx7mra1`oOi)D#|1^<`&r5ZVp-;@n4vbVJ$^zDbiKp*K#gTCO$xxpfY-VLg%AhYI
zStX+@mTwqibSb`1R&%Hoi5Bb$?qWu&AJaxn;s5w{4-2z}R(6+S>_;Q-s?Ef3l4d*s
zLA`-iw~%EKy_>y`A{(>Swa&&lPe?R6l`ibV8LVYtH3YrfM;+gv^l_ngV0}o}%B<TM
z3{sTSE6k5T>RRS5pUJX>k&0-%fMA8Y&v(0{t-v}(fMs5RK-<+)5lDY!J~c_X``f3Y
zqT4lQC<Uq3&|GRme>NUByNzE)YZ<`|;|iGy=ta_mov3NJyNE4NFjYj2tcS^~0SRG!
z)Kj*Uk)hSG-Fm2KY&e*e{cR2#x4T#Im1PCHm1XWo_&mqXt+NcSZDTa!a{_2M$s~s6
zf4<*Sa+JP@+)eDM*n1hG$uIjC@BS4*t>xHp(mm>1u@wq>oVjF*0`{7Uf~F5g5zAW_
z;!6NRBhXq)qA<nWK6`~&N6YifG5K%M2y7A!Mt7M%YpzNz3vB)HfV3jK(3bW6%!`AO
zp>j5ibYn?+vj`B(<jn3Bu;DH2<S1^S>Ol7e8G5iUTZjsjFINPW5HX7w3TsnVogx5>
z!REjsWQsz@i?|He%5IalB-z8zu-Iu3nrmH+hjD}6_zcYGNY9)ovl$lw7+2fOEq#bb
zv;>M04upa9C0N{&y4>xl7-9G==RLCf?K3fjBpqD~;+om5cT;A(%nUvYvdR^ZILhn|
zNNT-bZj<S&qD^~<(QVE#wAce|Vl&GaF8e6k20b*B)~s}(_rJCrNlekiJQ<0Q8j5?M
z<{ykT4-OJ>C<~Tc?)g4qi!dV4gCkIQU{w9~BO};SWZY~bMiRp$i$cEC*5mXP0>x%*
z7Ly`L`y1xj6oQNuGsyT6mro&EdVyZ68UWQz`<ja5qIoi4m_7HwLtjCW3G^(Z1=y^B
zcu}7MRcTVF2F=>`(H_00dY(n7)g`G+(I?mpn~|w7>IJ7rUY_WR*A>;x7DU_cp=l&$
z>y&G8WQ)hNZp<LjX$s!IX8DF38RbuBOmCfMXfntV5kNO(OHzo~ny1?yvi=+`)sNOe
z|JY`t6;iqlD+-s7fP;&f61jqg#<hDtd&h>qHm|7VT%#h*@|=18-dSlRl1Io9aHGWy
zIePbO&lh9CA7GAo_vzRl#7d-ZStPQtx$G8^J)avWeLi!jd{*@G)0h2zS-BZp_H*U>
z_Iza}-&iD>*O@H!tdz%w^QGyD<C(@SR;oNT_y_!Y`)>tle2SG*dsyWW=}$b^I8u7W
z{}ee(Q_K0pCDA+diRA7_<v03%ke7|WEwZf=pZ=p^H95J}?YYShp59~j-B7n(R{udx
zHV&zKJC~8_FE-Q1a<Bn5vul~_$Tqsdc;W^>2!GN}zQW#?&)-Xqd}HK1wP)`>&Zf!J
zhy886mC^hYYL0x7JXwzY3JKDGZIbJY%k1}a+4oo8-+p&$_VkgYKMJWYgn7s5xhF81
zGRE-p?$_HlTa&HstKxcazyIhw0v_4xK7Ak9VTFCuzda~3<&5eb>hoVGqBp*We1gc{
zgy?x)lpcMhJel6zpL=wrn1E%TD5nm6XJYvI@@4U{g`)>=_^SuV)Wwo7&wVPtB46V2
zYljZ~gOEY$Npd{hxG)w5^@&KedEdd!NxmpCIya|zc!_gI5f89#ed9xx{kt$Qrd9em
zEX4KE+}#H&)iDMa$NZI0hFhJb_<81upZMv&q1!zP+`L7?XIA(Lu)RgfkZivt#l4D3
zUD<=`i!$`F!(XO1kS&1JFx<C<bi00;bp}3YR$s|<;$WOxLXWo^ghJsj%KLz&@y{Oc
zYV+TRA0^J-1=J77o4+X!92HmH%b5<}Vg8WGB7ikMN_8l#a2g=nKl!r{r$8^W3--~c
zqXZS|s>$crm6|N2?g{m^PY#ClERl;#M;Cr4$S#rxYEOQd887wN->?^AC+Vn<3}|d?
z4Eb)VGjY;iN#4sliRu0)Kh3U?+mQBtnRRxZY#njM+);>OA8*o^>aV-SEddbq>&0Tv
zSzx?-`2}_~?;e$l@|9Ytwnz3(A{+VtxcAWQ643Yk-|aor`;kp#IMRFML^5@u3~_J|
zKH7VB@cSD#^*R#81-|yjWxitWo#aR=|3~TcI@$Xv{pe_(<5&-`G3<vue30zzIWKQI
z=VE>5WqdK;itQ=(9vb{6NJ;O5pZo2|zS&rq1)V+()>})TC$Hy`yG^QN|K>vortF(%
zS-UjY%dX)nw$L?6Z}&nBLPVeer7keg^Xj6!K>ox81D7|IJt&JP=NF>=Gf3;j<wC92
z$#uSn%d6X^HW)bHB71k9^r1a;KPaj{9G1Nwsg8a3aD35>Mc8q;)`!5dPZXgA4JEAx
zsMgocO^RUcI{!TW5Fd~yD_u<oT)pk|-UZ=oC^$sYIzU?TdU#b%2!k(_&&D<Zlgc0L
z|Ago2Cq&YG4yw-sxUr4<1x@OlGF5$*v~$(c7a+ZcJ~#!9GdUB=ZXp}4<9RB`2}D3n
znFUN^&>;_|VYyaIk2m{22{kdh-g@I+_RY$1tY%bP;}>u*M;%<CW6q#lX>|-9dkkB-
zG>*7~Z1DccFF2IEwhI479+>RSAaUQhcQW2ay#W?;Z%MQf6f~)q*@d#NhyCMh%q(JG
zE<D-J)9pj={@*+lZiG%*;8xLIxE_Go3k+L*Y+&~<oH@+~>FE4>DWEF4XGmSa{AHsg
z?&YW8WAzP$MAJ9`J#;i_A9&oeuRL>#nbj-V3(~g<V0d9sMy$vO#Xgo=*K|^GGic|I
zEAMQqa#_UN1W|x??zLdG_*D_?ya4qp^sG?fHt(vs-{Avg<Pmk@MucsTWKp{v-Ujr<
zLxmFQJ@mO}bS<M-i;IYs>`UDPDsczIvDISiN^LZDce}qj24!>dsCnS={(TE+(@5Za
zHkln4I?U3-y_{o1nFXFg|N1@oEFuxwrX<F|;4S31%Ty<Jvh})@JrUf9!?;oCf`F{<
zV(EJ2{&V49Axckusf1!5cC-Iv%bs#jCH4e(_V$-rM~Vv$hSF#KscS7AirZp%2ZxgF
zkDOHYGn0eIbdemog8OmoI<@Cy7R0kRlU&n7vp#%h@8swH%`X-7Y!`)K_d_wLlc{Hq
zvVAoOq4o)uy}U5W;^5?*CYQm%QKzQ^-}-rZifDMrF0oX&DNTVG$OJI^;>M=r7mGce
z4V+FTYO^>x?lT{&-(Pck!;&M}3#A8@)7;SgWhY`P43Hc2avQyV)OkE#UNSk(|6UA_
zK|O^S*OCO!M8(h?$TFvcLv!eqfX$Q137Vc`fACb-J`};_{Czs+^m}5<qSK5Obh<Bg
z7ey07+uUDRqy|U#8kAvx4oiKeB+~3JYW5|Wio0Ky5%jX<ByHvZ!WrosWj*V017t;q
ztI~&#weuAgM7BYo7rRrKXrI^I$Gy_z$>4%qe@)cZBQ8J@HG0MggJo%?yN97Lc_0l(
zwJ)5t5OHY6V8SiSVj%IC*B-e9%i1<eF$_n2AL$_om1xhVI7He-$}Y<vGKv}v=B6Z0
zConBvhqyz<1^PUi8KpxloffXhbGVW%kouVZFro}5ms+94H8-Cay9D@)4Q|{!&DY#w
z?{HzER&K^n-2l@JLs1h_#0S9Yd!?2(#I?ygfx8_zkjYU-|K_{z2vj^U@A6lKdY{z!
zK)!pP4t`VFvofC?H4z;8*MWs_V6Dx9Gmspl!Pcd}lHZrpcps#Gs#h|z*Ad!p)QppK
z*_B8F3|3J(7H3NbcbIni%=@|{s9f6<JZDY>ALiC|C+`$So?*FQnKclAfNY3^Wyh28
zsF=b@!nTG$d{1z=ow7QaT!3wuSp3$pzZ_TbyTQfNvlJf?JFp?lK~)_^8o)2FPmJYa
zSSyd;?b{(ipHOLE3arIElpGJ4h!#lmk}RSr&7hA5`j%B0^7e2QH`|;cl#NjR%P^RX
z4+JTFOF3MDdvMh35I4REHgBJjlHrq)@CKMO!_e+s%>@ieKyU|oA}_Ouwfxm40^KZ_
zP*|YNCAo+G_CLP!sef*XhMy1CA?sP&Xy*U3%6OCbG0y(~!NlJz&;Ta>PY3DzBv|i+
zd*A#5upX8<4a=SW!U_%8ou+u}Urer9<!cN*1nePG$77AL<6lq55BO?ffsL?~O}Jlq
zxY1m9xEFL_#gIEZA9pklGIJ-2_n=eb5qe(XLlj<rto+8)|F@rT2JrAAI0U@ypZjhQ
zCjI5_tT#>A_U3!deI`rPA2tyzBGpGs^6}Wo7(>~m%*WZrt_Cu4py;a8T&_n?tcc22
zg~%+(Jt7+ydIGpj84xIL=4_%ec#7n=nj%l!eDPr>D#Q6~`3vNvGxUM66OIDil7PtA
zphUGOuNy(`0K0<JY`JBBR&`aw%(=8>SUcG%s1T6=sKAa|=~A()cVH_r{?+Gs@~NYy
zxcdjcb|}o1MdiboNC+D9RewBDj&17^jS0W-cvp~^7nKRMO^977s4MG>!VxPtMYc}D
z?yjVOcLMBVykb@+*l;u(L4gv`jO`eLRDem@ea@<zcE1C7fda49bpka?D*ovqF~od2
z>%h5u+UM^_5-*bQL}dsvKMjsCE9#g!dJGq6k27|=^jA%+^^HpZ-IZ80ULluERfPg6
zA2VYtwy8(N8|PyLt|s9iLDWOxlug(zfT$kSr7&jlVZ}g}?$0-<&vp1q7W2Uh1Gt=9
z&8=f8_?CU~R|BB=q(8xyy~q-2D1EDh{>wKor><ujmmUX?tiXF;R~+)I?KsI!q{}@O
z8XWy|9qAJ~jvX6$yNOK7Xu*6{8OzPEqQ5k@k!(NoMD^tygHXLl2VB7m^MLwrV}&to
zqgtd^UwsVXTpc@NiWKv)KjTMvFNYr>*)HCY{&KRi8W$%9cDE^XSOF@#z3lII6O$bE
z8Y6wiC;0-AyT4SXeh%<+i#y``2E(Sd?V%(X@MA!vQ#0_dMiz(YE5~jnKA>S5q>L)&
z>)N;qlK%a15LYnFdTOA*L88ECq9CM@Q^zj02FP%<AaZ8OlVfh>yi12}28`wg*l^8{
zSS`Le04&+(H&Ux8ezQE)ppk828!P%3+>(TdJ*$o_o4KA9(oD#4UZJ*Gi|h)DYIe-o
z7B_8Ic6Yeu9By%!l=HS^%>CZ9p0A*5AQ}1u|9u0S*o3v;CMw|3b%WI@Ew|)`6>#dh
z@wDn^kW<n6z?3-2R#7-LzsH2&u(DwRRqT+z8b>5{I`L-%Ih1{MRAoRwMcXbVJ45A0
zhr8*i>xWE;u4YTSSMtYq4Y7mAA=h_ZmRZd;J{6y`&CUMM95ZRjeX-2R*8MFE)TNP=
ztbc4IW7x?Xw%?}tq0{mF;G|3*%h1!Zcj&RbjPoyTz5UmtO|m!U(}NotD|92dYSWci
zMc-#uTXbWaiW8L0Za+;M#=oLSJDpI_z@?auz#4|v)qp(j>J>@{5Uc4jcSNm&tfBz&
zZPrz4Vssz}5HK*mNfI$Kp<Wyy&X&ZE0bYkTi|4;UzU!|$k=wn<U(b-~iN0ZA|M#O3
z!)cibe1`A<4y^B(+SzlK3gCdFS=E-vZaBoAAWXPsk^K=lRFU^=eJ5&zBDSsFP2u-y
z@pt>?3^ozSBjD7~G4~?$!l0@yY{U$#c}lHERuraUY>&qPiBNcxF~joD!yJeQDph8d
zp$$hUN%B>c)QlgdeMZ3#bbONbqcDP*@iRIS33Th2I)!{gV+ayM@fyENyDQ47`bK7G
zcLQ}{j>4B_OdGW_4XCJ*egWk^g6f7f5o~iogBhyA8QM5gxRe<pT{Yz)28W~yE6^qB
zS?45Pk+A_Y2!kQB9OG?7RnDgI<^Z|fp5ggMAhj_K1&p&D*-Tiz(ZdbQN06?GAAEn(
zyN-32ct$J$IY%=jW#spDp38=)PWJ+4<g{@gQddORvETrvVoH*@bTlQ%J`Wo%D6FD1
zDaEG|O^{Ki2O7`z5ER_*h%q&T%RvQ12Oq(=AbJ4K?(vxMT6u5yLQsgJCU7(`Plfxo
zys@zgYD6-Ol4)WQ(V-RwC0nmmWDNnornG#(-Dm)^rB`0@5Bh0lNH4GjF_th&HHGMF
zkbc$IrRK>+cNup{s=(TbeR@2DmY1Z92b39KEt7&_CU5_z-A&>r!W$p1zov(0<Jb%w
z8<36rxh77$fmfKsQVWS7ft)`~GY2koD}K;IR$0W{gLH$o4bQU2Mg~_)V(msI1avMQ
zdE623(-0A1HpOP#FZ)Kypxekc36ZkhjccSyQl^QBMvH8Mymsyn<8h*GfRLjLi~TmU
zN#lhm;Af#ly_k&@e*nYo8Um51WgnRyP$U2*M<LL_qIMK0lFMiwG*%0^RwB-(z8QB2
zpHw<3H1C0!6@vJ$ilJ|HDEE<UI)IQg=YhXEiLi`G#&=3b(-0M57Eb3wTceoSwODt5
zOx%q?6x6ca^Z3nF>TX2W&{k`EuStX<3bptG#Mlwh<Omqm0<O4nrhMGn3t-n!E?WVl
z(2?Cn7W`Cs`Y<}a*e2?;j#kC2Y?BlF@ueQ*&IY=M1|F)RtNrMix4+lC8{LJ(ajOyc
z@W|T>x(0w8tur0-b1qai<HTIFR9Ffa6}nNw6v-2tMAOEMQdXLB*YK}pyv)~m$5P93
zH+dE6Q|cm+4&xmws^+2HEJoQVG8_7IEZJTRNqM^IcHjD~jrg|kN;iTmTROuII6`}Z
z8EYRgP$Q-ucWZ`=PNPt;2{Cm@UjUskK4{!0Z5dXF*2Hn!O<{oS<JuOED3PUu!uCb3
zakWaW!E3{W!J#f@$@NRj#ey6u7~OMBJ_M)5+<>9W$lK9^r#2AbV{`3plpo$_iVcQ^
z){45w(T#wc(TFz9w_%jwy8#-!3}ojeE!YOokCDjjVFbu8A`+BC2L@O!$t*W^E=aR)
zU4fXtCRFB*VdAojBy3JzE~lI}&%{?a@8jR*7<#wH_FGXc7Gv6m7}|rN92nFF-TI6f
zi`^w)fic>Ji2+xJ*-}H6CZcWQe)j@~OdZLzj0J|o{q2vBb=QvdyQq-Ec8Z-wm^k9|
zS-IqP`*Wyv;<xQoBxU;%>J)Bfmg8cgn~@Sn_i<R)IJxIDdbj>wj0kg_;Oez*YM|N2
zaj#%UGnCrE-h;|o&tOw4WP%k$+lGB>sR1Ej8Bd{8X$Z$hEIXnh_sfbP158j2dl{pN
z>W~<<xr549)_M<~C1yB~eTvU{mtVZIog}e-M8TItW?3NAyKFX=@7|b#F$%jk^Kr5x
zFOaF1`DH9UMz9H*lf(jj?C^CEsm4=d*_-MH6b&T>O>*PdgMLMwF3A!hTg^|H#jeue
z>R9&4JbEoWYV+yaggua#BFn2U>>p#r@@fDy{^`ci$I6vW#RIn{lj4ErQAI+(wsXaO
zwDCHb>Um)0UjH`R{}>b!PghTo@?$dfWZdj)lM(i%;W^pEZZSDDNq6^`wlG(^y(M!`
z?4>`n`(yPS){58$Bevn|=D`jBiehqz;W`(HIMF{tg{qwInT^FZppwP7&sgG8K2d8+
zap-yTrhgqd<7e$sgZ_tOC<Dc&QK928VB;z5T+&G=1Jo`e%^}3<f6Fz>l~0Y8CEF7(
zk(c;{JkE!wDkOVkD)aDITYk`yk1p^Na;vk+eeotsSIfumWe<LSYIA$5d+)K!*_*-Z
zN!GZWy{>Mv;R8n{cH1LEY{#Sbvg_$GAH2=v18uqE2J6`6)ThvGvmhBins|HC{au=+
z_IbD`_G~`_<m3(ft>8?9M6RLmH(v?0+M%@jIK1YgVyxx@fmdst`0-Fc4VO6dtX+v8
z^^if&y2V8Sk3R&|@Od-yAvr%-advm&q<U%+A8=rUE;|6<{c+T<SW{((vhG(pZy;=Z
z=4uVpd*FBo+KaE7;$@I_;^BDsl^JV4e)GrAw#fISU;5tLlB2P^&YRDf_T?BdNB6}l
zNPU?VuTcu!G)huzrM(XWo6TEC8e{YKl%C0j3=K6CG*qQHsq_Q4A@B}M27q9y!#Cq0
z@?OXkA2kPE!19QMQ1&HAp+9jG=nJ5&)3237UG9PXH2|s$NB^RB|AP<7n=v(Xb+YrZ
zP0(qx5LkbBc<=Dp?f(;+;j4q+k0<s{cBI(ZaSms`NnZzQOYK`2Ud;WinZN6?L$?VS
zx&F|h&ZmILFYv|O+jjB$4kfprO0V1`yQtkWU?#4#!GKeQ_a6Gs|7#OhOLLI7-gTrO
zVw<}{#SLm&R)0t-C}lNI2ce{|V_T^Cd&nDAEV6SboFy99LwPx_HfRoiFpqM!;H`%a
zgH;8%GDrg>pi2vf@Eiq#7fpIS=wSVCqtI#y2gi<Ac0M}%rP8|UKMZHa%xVO9`iS!b
zh*`0MHQC;Y*PY=qikm{P3>-fzDXV^2UMPJ(pMN2~NKkKM=grKQj;3Q5IEt^HAHFbo
zmO&!Gx5sxb%7Oj_e#k*)FP6SNxPD(O9&9r2dVQ@@!M<34B-Ohv$HL8z?rN<SvIWrp
z-S@(nMoCZIx|K(bpYW=x3r>ET1;q$%*5UTUAx!RGa9}-UL7uBv!`6odHWcr5dOva^
zzw?#J3q*}B{HD|UAdbwk{^;;S^6YlAXP^uQiI>;zmvs@b4Q^EbK@NxF`klYQlYapy
zzE$>aAof;1s84=k5_NO9n;$vvT#&(X7z!yLTPEq8Jo%^Z8aE5CD)i3lz8s6an}nD0
z<o`hRH!g+j!+C`-Lu3rChB)aX5|EWZ^Vd<}SyQM=JG54sS)!(@4tRzu3W;=ZmKOXQ
zen|k#<F4#?q_)fHEg{>$*f;#KVN?^LVZoC4BZ!3$9*J}Av&#tX-{%}&uO7T0x&F}P
z;?cByQ?|F0^tYX}+xw14Bs)WsAEJH})HqP~6LQP1qNCX@`o^s&xT7(Ew|zDAsSS18
zZEZK9pq`G!?;*Z|*niMKx&#=XB}IU9tI1EAQCVE?wNq9Eu@5Mwn=vp@t(;X8xCKFY
z8%FaU*LT(~96bwejEbs=<lG43F#NjechUY@3Ux_B)SGe3JeRLd!CkzTxllT8ukyj6
zqw>aZ-~-v64e9l853EeQHS61p^7h|--5QOd*JEb5hd|REpUG?8=4dRRFflw1syOxw
zkH43OdT^}CnA?WopblbLbCFSn<Vf^xb;Mmb1W9xxB;;7Pcro%x>8A~uTvr`r*<;}L
z9I|f0D}iqtS+;_NgKzt?#4ulAhJ55?rQ}e0!rXbgEPFCB-e&wE-Z?a=r;R}pP6T>!
zK<0RQQGWY>e+Njl{X=uD&j(fP#|n%-_Ph5G1N{~qb5<){jT!K<G!1>diA}qJxl~X_
zWWZ~OwrG&$P!CuLue;y|9b3S~*~im!urIL3dAnDlIL2r@WmF$44zgrd`T|?bV`}W<
z5+OSj3LgFL&SUF#KEiiklX57&<qhW%-r1g9mTvZ&_Na8tO=OSs!Uzcc^^Zn^XKATc
zvGtSwhOroSbaPdyhW%Jj;-RdbJVN#4W!F?Nrozg%OOUYJKi<My^Pn__Ibw!Ibm3aS
zJLBmmSfRw0Ow|*qmYzY4=qul;8OLe*@pi0pkRyya#<0Z=SarHZ_c{0SAT#Rx3(3es
zlcy%LWxD5Bu^roGqn7c63MK5M82QTCXrRU`DjutvZi}L5x2rCicg@pnW^gZwn6db{
zdT+oO>~iS7SI{-H8=^(bfGw)LHdQkcl~=r+`QkzblcAOmU@B`pb7sYE#{`e}7}Zm(
zXLu|C=I$n}YfCVZwGF64?#!ciOS3bCNZD|@--NusYQG{ou_ebwC5?r$xr^@NESC_d
z<4cPC2mih?UW?xibGc0lvoQvRJ4`k-qdjH<&7BBh0B_*}i@$q(6^$^ETY@SsR)ca|
z^_<0vfj)94UPpqn>rn+_J%hCo)kOx@>S?H+fT|9+mRF06;R)V_Cm`Fv-B6zF%i+CS
z%Aw?Z4Si#I{i<Ldj|6E0VSx|reFy4lgc9ywTu=C?1>Ar9LKp-8FE%uPL%{uC*%ke#
zRN((j4if6oe{!F&U%WTh&q~REd^xyj*?+35(Rm2J|B13{m@~phVBraH^V$QfIsmp-
z@Y~;f<;_2Jn~}mmd_;F#wR6nfX-2E41G^k3#}?gVK{XzC$6S0;b-U2>VVr~y3nRNp
zwY|T0Cyed44i_?M&4X(fKEkhl^AY+tYYzfXF?_(Xf9vtq-`@P#wb?zhb0%%fvc%gP
zSR{3*Us06vhu9H27Tisd(hOa+-ms@C7WJPKIzwHFx}48j72Q;9W~xvFbcT8p3E;CX
z%BIrwS#`v0)2*^H8Kmd)<by@?!zFVQ3p&`zf!5V?><@Vh$kEJgR#3qD^q4-JkLMp7
zVddf6G`#!j5#(MxiR9WUwo-2mWfhb_PJRy;dorax1En1uzKP!>Z+HI3B@~2J5UW^5
zh5CRw=S`&ZzlScxAP=O9QCOq!xO5mc7M}>bxXUR;D~cST=W@8oYsQ3U==l^}jInjB
zazh!@X=R$bjRv1MM*85MOCC9`yO{VhNTq$Wwix&4_>zzkbt@L9C=E9$!<{Lk0-}y#
z*e;=Tch^_$8JT6>4CR>u;prr&Rc3)S-d@-c-B(2lEK;D6D9ls_$tL1C6RvN-X2v`n
zTCwpI!{Qm9X2dM87qa!69o@3q@e{)`v1qR5jw6{>_y^_KjvDP^tj}L}mAJOG&g-C-
zGV9vpnp}(}AuGW?Q5gmqptCf|Mi$A+{-sdJ{<&dnPF0zWXJeO0B`~(3s&7!YvF~uh
z&VL|>S#U=*)i3hO((_CCi*u~-`y!Vyzc!YrDeP@t8wzxE%FXZ?pEI!oNt}#u==*B>
z`?NhG)0Y#w0xP$1=#;ovxfK^P98(vH2a8^unvvk;orTE7h{xF@V%5Ed`W{2)%>l<+
zMzQK4qiC4YZOUtoQD#GJFrrdoQtrL?4ul=Hu)waQu)VAyP(u`)!|GDR?78fAG1bk>
z{%$`u&phW2M!g6!ErxSQSLO}1x?dn8%`Tv9MU$#MV0fy&A)vEy)U}|fKBqiAXjE2Q
z;%1&Ffx4+C{UVzckjlrRqKR}R4siKC3`k84(cB~olme%*=r(8~*MBAPwr5Q!K$9rB
zTZhk=!{+iw(29z}o!)UZP+h_4*auKzU;;2O7-2TH>$<oq=!dhJS}Kyr$4xbCsBkBf
z*sFHjj0V}|4+M#kJog4faglIYTLwTmZvW{S;=Xu3KIw1zjmA+f`khKw{j&d*=uOlw
zj*a8X9}On$pmHW*4%b-8eKcIec0aj)q-Eb1N3-rW?u$Pg$A&{1+rwGS^EbECgzfFw
zRUTrEE|dV<85R*7uT<0#!uqpjqW=S%`hs0;Q7~(iT}0QNK@@=`%im0VM)-1poWK?)
zWas?YATQIGgV4j9>RS;*U96Gf{e%u7?^;jwv&xDS2)g^`#OlUIWXp)iv=h6RO{Z-C
zM^<T(;|%qo&k{TTD2hPJ-EF@6tHYk3F+kW_s96k+;c#H&P(1*<)V1uq_yj?wZqdJ0
z{o_wEe$niXQpQkUGa>YzWn`Ss@lWy^6vn7H0k(ymh;3ib_)HJH*#AS@`-iu2op-*2
zA*3LV+XAC8GDZ{yb2x;C5G9K=qj0rtf*B5Ikb)$VW_<a0^)w<3D~yw@CD+Zm+1>^N
z3?$HksvnVawY}Yzq+wObx*JPTQt!5RD@tUeY}JkJxLxnw-mN7ot#6t(qU+mrbGPmN
zoB>J6X?y?ZeePHWNzAWv-t(UKeb4v2=X?4mmC6RI<ERNJd`g<kbZ`<p!zFt;H&B>0
zFEL%h{&p&eu~JD`b>NIml17GfR-np(bObnw+bVPVv@6$973{s&$Q7-ym5wyEmFoQo
zG7Z77OyBiYk;8bx^^-HSLfJQsQM*#BLX+YLm$aZR=BCnRGaH%VM!T|Tk5(6l7Io#b
z1#)`j`ryQqA}TOv!ksn6cFVqGxx+(MfpR&v=>$Q<*zT2J4}!Z!(7AiTU~g4FR>7EE
z>QPws?{|_2z<YBnkh4{}QJldginkyX`G|C+kc%qAe$@6{mh~u(3DZdBEurPk2*n;*
z&?+qFOZSs(9tB1eb+yOuRA2Y}=nQuu9#CTy&@_@ZRXJgREN91?>WBL7%5XBRu?tjA
zRR#%6FY!`{IZA%B!?xqWdG92A22o{ZU1xB(e%VtTE$BO82L#q?Um*bQT({qAs-zO+
zY+bD-qqdV;Ux^NYNm=fYE*6;`Ejxvg4wiJhCv8RxeKt^GN}be7yqEb{7C8Lp$CN4=
z>lk(;2bPM{6=@+l`rv_zvjkB%ESnpxrb~gc2V-5C@>%W(q5h&F;&)A2sXi7rG}WzH
zZEIhyTAFwKoI0!yQ|-XN(tnV~?9(Z(k@Tuyg~fH1AOT1hHv-Ggs7zL}lNplfa3H5J
zoT11kte<FJ7GQehm<!azpUbgnS53O^3e39^(pEI?HX0qaJL~w$5bnJY_n2^S0oX3V
z7AYdL?sUb}pJ3WL)o&+H+g(9q#{ZH|!;4V{LlqVRRHMa?rVoHy7_wgtE*B~u_?@{f
z8-<)f6t+*4w2@Li{`Tg71(}Ui>7c!s867r7FBoBj!Drf6nMZ6^t3q{QBo2HDxepIE
z5Up+6xt4Qt&<Rj986plY6d?fd6t=-!P?U$fLd<6N&-{+75}lBlVdO4)68vQ%^AbuF
zDWH`om8RUfcSqV`0<;q8Q-B)TOHA|$fqGWd{Z#-&O?9kXR1vU6xR!PznOofWygT1-
zrPW*&{JT49D*LO`!b?w7PZ+Jf%(QE3`#n}76lNm(-4oVezaZz@{Gtclo-ZhXr^w`W
z{H@}qBVMKI|K+i+oN6<%q^9q;G1ZZ@O3F`!(!ptj6sdS+NoSfvVX!k43ko!p5|BJU
zIb2mMk?n=ot5a1a7g%L~5`Ciy)LKg)vW5uyAU1THA_7B@IwIB?E>zRg>4-9@R%A%F
zUhXEQ{tFVTn-L|=l7^T}EcRs}7&q=RN&d&u*&y;lFdYR{?4mSjH62|nxSjLPL8E0l
zuEM$+OX0GEI(wRUe%yFcYm84bY2u6qnt`H5wc2UjahU*n2Dp`J9v+mmqDqMcDwV1#
z($U9XeQ#CSiUgQtOFOa3lq=9mCe3{2c&L+FSG(k{fwMZQq4is+=~2D=<CfxH(jFq?
zw4zltH5V&JU2T^WKh1nVvRI8cGp1XvPFK`nOZ6-6n<5dd2X3s1ghB8<NQ@&cXg?5t
zdTLM^)z2%uwW11ucUERdRl3CTadz0NsCN7+({NRHz2Ee|#7rE;jIv8CB`!W<=Cs&;
z%O8xeK3N@#HMMHh6_f<e&LKLZ`%SlqxMv+{3|x$>Ji(i-Xhkidi`j*rOFt$6|L4p!
z$-y(%t7gYB&7b*B;lTj!yvZJT!65CQT|Ik=Bk!yB+FK3n%a_@j9;T`5&CECK4^O^c
zua=){)_+Go+O>6Jo3Xg#`{Lq&{)D*ru-g4=?tS9s!sq%7kmZ@b=qrqXvFh8HLE6i<
zpPzFV?Ro$<YmXmsd)~73LACi8{Uf{WBL_ZOOxi5hS}dd<n%?DXd&u6?H&XqYepx?O
z)~<D)w_6&!w3VwfkGSJ#>YO$BUAHR$y@jf3WS%-7ISV1K_S^qS&0HYvU_zeZ^(i)v
zfaUg<Wi;hFE>WZXlLL0Q%i2Rxnjf%cu4tM0L9zL8Fq7$@PTicl87wfj{<VqArA<~%
zE4$m=C+_nOm0x_!JUgDbV12hW@9z01wGqeqPVAg1on<3}@zksC6HorIpkL{qoH^ir
z>l^#VgKhe^&hL5S%FU?@Ms?9X>Tb1ucRV#=?Q*w`GY!AT+LgRwelplKc;tbHZdRXT
z|H(Q1TVH2Y;7J|E*x|m35&t=7)=XE$Y0rIF^jRYpytj&5X8o?GCB=uy61;?D60ulf
za0aNj4K{~}^U4R<bW38>4v286%HWo(Lv9atT_e|eILyet=&dAXXQvkaj0h93d0uV^
zQ}b6jL^>aYLPRHj%aXTU4R0%iw>22^h4dkkc_h47?$~x&A8viPk2f8{o`>l42CXQs
zZ?lKYT4IGp<O5xw_>Cwjbz208^Eq=?kh%z0#>vdMMn3i=xsK<KfEGJ)b1oZ<`CPH_
zmZ7!C<%G`ng#CM)K3U%K$s^Tc#?XA9%*QU>xCgYk@o7k!$;U2!-#u00!B2nE-T5=k
z@vq$Hex*163w!>9xL`bJS=~2kYy%}8`y8PCqnSDJ@jpKhLffs+%>Pf%%Uo{P_!A3=
zT4LMcKJVQ9yY>6Z5ClA6wv@dN`%@j(CcMwrH}sY_jUBU>U<~*sRLt-~r>=V!txWIf
zk;MR{(a9#?(e<Ho2kcGyP^<Kb?7C4|-5Q)5J5|dxc4F}AG0E)FWCLVy>4r_B=h#=2
z`os3D*rc^yuK_;oU==@!w#X*vxj1f)H6C}r(MJ+#-fNL{{qk2@Wm2}k(mB6jY2u%E
ztK~f-@u!TDd8<BI?um|`%g=jKzIg$Zy+lf6EB_zL)*B&e=Zu#tV`YonPFNt|-FSF&
zN3r$sdf`Ry>^;f@?#>Pm_!bp|QrBsL9_?c1EpLza*jt}`Yc|mZKel08W*WmI^NbaV
zza}6=890WSCMq^fTJdR<t>(lnu;C}Yvt(gw7u>It)cb-=(XIc`0`{!G>CTJMEJC=S
z6mr+ip6z{LYBSB;yLXB_Tq!Jf%Mcpzu-Eyl$p4{x+RaUt9$qq>2i(4%Wv|#3xT>2S
zFFRXGsr&UV^_H&ZThNl^Nq~LO^R&^%1Mb6zBl#$Vx5XB0xA0~oI=6DjYaP&bB?f7j
z`=SS{A>X$G2Zv%Dui+R-a2|}oKGCRa)kpleI{LH;HANS+%j9wc61s34kG$F-O?i~;
zW)jMcrME2-bGzO-P?q`Z+e<q)Ocp!U-MZ;gGsEb<=&Jr_J+S|c-*AI5GGQS{z6SfW
z*7f3$^<d+xEeI9zx>ilR?Yf0gXgH$E&dzafm}~Rb$|JH05pS>+&PL?*mUmEJ^hTnC
z%bxSt6Q8)-vg{hW>;ZskGaXhpQyyoa1BF}IpOy1gXT$(l-x(6eN&UT+zvzxL(>`!)
zAh1#&HY{>S;S(8FlkSN1;5jmPORe7I=l5I`!Wq(TRLNTMMw^fJvlihR69gz!V^4X@
z$I0s!WIMlc(Q5&An`{rb^tS75Ibb;P%La4!S*_V}QX7nbZ0Xq&(T_2>=t;!5KoY+L
zUCHdw3%c1V9s4@V;-F`?bL4{WAlb+<rd<Z!S>ePay--$^OqMaSO`ARb{YNw74WItd
zl_2liq4!)69osE1+{BBSs`}Ly<NVZ^{n&cPWCELI;NxX-c?A)Jwabgg@`0m$W$1Nt
zxlkaE`&Kl!Udi9|teaIgO3r*PV6=?trz68Hh^Ad86g+s(rj<Qj_N~1iBy2j$dV;hn
zXR43*6?K%EvP4c3gFrlB$#ib+FwNXULyE+%*D(inTFb%nayAiXeXu#3D2!NR-mI|c
z9y<qt?CX<USej3amb&}xmxeBs);mHw=<SJGzt-A9_W$SIUnv=m*$LayF~gg#jbGdC
zJ*-a_^MOBB%(p&{o?CvehrfU9tjTQ0NOZ4r$P1!**(Td=GOaEPJ1cU}nuMAGBqEfz
zI{3<s7~Ih!OB%YF)r?okGN&A3{p<Y~H4*9R8wYU?p!Qa06MKS6hyR#G+Jh7ana5-H
zR#%AfqqS1in#!_0oe|Xgyxb2*uBF}o`fpnzClmLld<EU2Yvd;;Y-P8nyfhRgn!Xe~
zwmvLnz*ot)J<r~|OMTwy6UPRmDNzAM`cqd7zgRs*2{LBFP+uyMq0+?^LdvoSys6IW
zpxRxo)!p;%U~IG7J>FQ{TDD)xmR)f8&oou<0juI<<pKx{&-BbA*M|;2XO2EGZX6V%
zIu?8?%JQL13qIywOq*jF*JvIZf%I9abONYnBNGrLI>XgW;%(vW6wJkDv`c~5neYNJ
z9<ViO!tvaXo%x9`k^U#CNlaFef&*5ZST|Tx=y;C>q(8GPGk|<3830WCg#l$_AR^&r
zr`_Z``(W5t1Ez%+u8)Y)0v@pju;n=eT7A(WQ~HcI!YZiKTxHnNON%3FG6=%!+TPai
zhNHPx^_CUX83CUluEV#o+Z~MUP`N~LulnP^@ZNuj^m&zC<emTDsh0nq4fCA#hIxa3
z&xU!&$KR=o$4GvDR}S<K@5rPkDmm`F17oz6d8fT$-an8@{i6?&Y|mk0IOCJ{Gf1TV
zeltxnGy{(cgBu27@<Sf-D~=%iT=_!*%On>>0e6$Xvfw~vK0)5c&HGu03YD<A@+VJN
z{?@OBcgqiF?YFgG=#Y0Dk`Xa2?*##Ae@((6zqmYz7+#iu@9)d5>;AF{kY$5Ncav${
zk$kN{vh03;=2<fn3z`cX#Q;&Oa2vgLpFqEiXVqqPyt=J$)XAEfd#3Qo!%em@nmJ|H
zp6I!p9llVwQ9EsHo;nIWLdTXaySAXuJZE)2RCuB2U(bs#jvv(_HLy0HFQ}XB!8vVu
zK#cSjj`pWoZVx%M^R7|op7KXJRgt~ULWNTWWpbM_UGX8qxT2>HZ?4V_Haq*QtS^Ka
znCn02ef4KY)Pb4%$u;X149RAkpEQ82dax6=AUW4`Y$oboubQe=i4-jHx_>&`*E8=1
zGgD+Z!Pwhp=STswTMt<NcDp`LaIXa;UrVV?-FlChSvRtw$2n7gvz;spGJ-+E)?I>9
z(28fyl3Z-tPox8<VLj`np-vVD7#vruE;TL4Ew7sE-H(0#ec)Z`USm$C`bGkP&5T{D
z4m1~xT0->M2W>0DBISXUYdj?walKY0+lZAX{;RH)DAkn{14qO$a^$iPHOx6A>Q|$g
zNmAN|CW6<4$Z=<fVeVnU?Q~LXV5wC{y3chp=bWc(_A(PBXf`9{BZEMZ`#iu1bj~XJ
z0qiEN{=vgOFzTXZEGVx30y$O36CGmIZjM)d#e~#31t`kyeF1r=g!?RrX5k(G7pep>
zzAJiyUKeb%U*BAxNsu4z&9T*{t~#PCHdA*m0xjB8!G6?6EmW#vOgK=2EXc(JKP{Xd
zf4sVNat~la+3bm!A9Z^cMb;108Lx3bOmFjU8E{lKgGDQO6P(X|NJP_fU5qjP!-u2$
z-DAJXYH!e1wt{zs??#oM^AoPUA@*e;%+6khUWu4s+OX=hOmllb!(cX98m(6P285Am
zc-2!0K!<=8#_E9PYL(MWi1^=iqD^x`WG0Ad99-E6FQ@jHHFb|2FFA@JA)#7YU>KB)
zR!W16s6Rs+kx|>J4j#GEzu&V47sSY+QuXc2pOc``))YDE)QiNYcq}<hR?Jt(WEXD<
zQmD6TJ-q{+V_B}~ydu(L)gIq1iL56Uv`vNPNzHGLZ3AgY_gbzse2Nr|LguyLmDU^8
z1+j~@HqCV-ef9wo)~5|~c%sTEl8h$EBuZUnbNaa(ru7Y1JZfs)4+(9H!@k>YY1H<M
z-?V+O&nta}TCk(vDAKJ(YrK2&xUiqt<)$v{AQ%@P5`PIK()rdKKR-*(XICscR<%jO
z)y@nw$EwMwf5iOd1sm)Rw&ewl(e9V0{NrLu)^T=f2jNxzDG<bOS(l4}sCh$+_HO%u
z>X)DCuT4EW6dUZmZf54pUHWme<l38rrDfjq*AHE@4?HP~Pk8f#+1`;JmMfRHO=wKd
zZ4!>QtG}m4gqFPFB>SyTiFvp0vBZm(^(8MC1suH3KV^v%fiZl;t@l~G%<OYrDT~bP
z4j{K3<>^h{rm{HlpRk?M_=?R{OdWWXKMP+g#<l63V<!c2^vDPVGxh8_J$|El-8F^E
z>UE)%(h+;gU|EA-b)uqjDl-s2>|2pX>g+-|#~e(AfHAw!Ur`0r;Hh~FI2c>)YW84N
zeOUEuS17YiT5Gw35wECz`hTvtps2R-Xe?ce?3gzFVx+HGPJlgWG4uIqbqwSf4rozT
z7p<3qa&^dN0SZO4;2>Y@j(T>F87W45+qX0}`s7l_ubdv~%ZZ3rgH5ALVzh=*SBvVP
znhkun5PiyaTwinCqb4|<uTFz=yCadAUON{=#K?S?D?aw;Ki-pwR(uuA8UzQ7-=1-%
zi8?EIBND6OYZf3wY1Q+TMdONN`;n(RBQQSgkcq9s88uyg)_p{UokKAJfbUkstV1$#
zI_h*<V*$Ur@hEk0<7&l^$$?V93>OPoDlGUnfGL$+RYiCe0NvbVDh=0kB(QTa6CAft
z^0AVo=K5x|kQ#R(o$sHFNBvpHDV%U2NT|X{bgEQYENs`o7xOV!F+JP6R(2E+Myt>h
zl|amSEousHNgbNkpi}`&m74(Osu8UxP&<9cidy6GXvKWxd+UNK?<RcpXF8wIVwX%Q
z3<2w}srEo}m5XU}I~s14og*VKlz^UJ(haX~c*4yFRphr0&a7x5x9Bw?tk5xUMzIVC
ztts0{Wy#9TEDuM9%fb=Lbj68!+jMOJwnX7>x8l)3d~l^#Oe?UN=<ehHmot^<isXEi
z@p>*1ljvPC5;vY!jr}KmHi-*rG8GjP6%|0*x?<UGjm3!*FIB0V7Z-3$T24PS7A`AE
zE_uF#HbyJzL3hHk)9x=>apoAnv0lvvEzRk1E@lJy`r5iQP85E3em6bKw4%cNH^&sv
zyCC<p+NbAK$o5R9*G_ljD3F;3Mr6xF*T>h*Y(VXyKyhM6!3Wc3HM+n0yeL=aAn|wY
z8PgBkjZx#Er^ZFe5ydFPk=2M&l+-*y#Mw^;4CjOxKCK(+4n?czlJ(s^AfjCsx=~p-
zxIFi{idth5(nz0@Q!A#mK@|d4FD-6&pxELv8N+9UufSZB?JW!$D%(|x3V9}6>{rM)
zS4_=eRf5tYNy9=I+DIg=nk2uo!5+1b&%@JSAbTfTC`LUd?%kA%Cni90Ju+n8{&kCM
z*d&%1oSL#REc|k@;6yJpH(Az+q}7?IX{2>8Y9F-d%ms}Ua$|cL&NW4u1p~LDFTgzJ
zRHG+6;V2JOsb=Myo|21sT3;^E`mE$#g{dx8V)u&MqeYc&?KD;d53XqT51#G-ASRz#
z3ryQj7XFK`evo<zku)Q<NP@~(=}3W{e~1_r@7ifs@iea@+?LhMTsAxx(l8N3{mGmj
zMBE&62#T@jRcg^0Gvis5d?@fqH$Gv>9OH`5?w5XKmuWF2C0J4x^f5nB=@^WfUzmLF
z)2>>ns{2_0SM8AVISUE<#DLLsW1~bCDHZwpxki5hUTD|Aq^2(yn)&JKC7b;;NS2=x
z%!b+rV*a#UYTooN>z*;ZD2mV6-u8iE%*&LYi`A1>V*ReE&VEtT13iec8jL;f*DIvF
zr_P!fB-cP83TZuXmoFaDM@hY9&5NzZBYqAGvLTXVx_pb4b_)^7StB`>n7F9=Y28Xp
zxXxB9$E0lTa~O_=@q$x7t@}vppb_<)oOV^X0V^d=!tcL*+;`cTic|o5Fi{A41;L4B
zi7i$-uXfElU8k7~BJ=!;-r4I8m_o^AB80!rw_jWTi+x{wWxn(BKz6G7diA<rO4NRa
ztxcy-9#3cs=0-tKeQIDw;mf84YX?)w#!D>vlL27!av_uLe`?b-)7n$@PwV5xw()KH
z;KFAfs2&+SY99CAaG1({L(J(1SU>03H>y@<9`=g8)$e+*v`$X%8r)^=F75fr<K8Jf
zU%e@w@g|!s^SJB3Jl*QwJ+jMssB!bGe<W|+^xo1A9P#cO?6;0(j%19jV(@EXdB8i?
z_tc)`$jidNY0YZ|FMHjbAOF-Gxv$1YU1MwCE^~|i@C|EDFZ2Yb^}<iSeRN{KCXR@M
z<{5}rO4Zj-Ua+U;l2?r{F4*s{zTelAOhg8ot8#;e_nWq?u1|n7?cY}`2brt((3{nZ
z(<cXp3ZGf@9y*u&OnKp@LgdQl`t8q&b6V+hPdxQ@fkkM8o3E78edSLlf49r?-CfQm
zu}wejp5FJ+BC4YwI53!Gb>8R1%RP}EKXY@)yx%)MbrH?#w7xs_wnygkQ=j=`r#1D-
zPRrdowA<aI^@!8`oeNg>`jk7bCofD?-zq^bG;&IG)-Pnr*0zb%O{ZmTv0$J{O<n-l
zCc82PgGdCf62BrjN;=8(9wRr5-_MwQ%7krLubGi|z|0RB;MEyE*fDTrge_C9>!&4n
ze#|53x}ByyweT&;HKJ{mdD=%D$)$Z2NV|WBq|%loCE++882k=YJNYX4+%i!+)5-wj
z@&ht$616|PqrmTassnbCxr7|2Z*?CFKY6yy*#`S-f75f(dFxG3RdQ253f)FTf{f?7
z$WN|~&2+w{k%>L{j_B-!YvX@8eWC=M$5O`SUpBhF=SsGO*#y8NX{5(}^P)E1I3{yF
ze`aQU=Dq`q4)FAUJm5-1d>=Wb_0Jdo+-u$c&6(rD;?3-X*B)3LVXHtBUg%}r7`!Mx
zXBXb~h8`Pl{QlpRhc>=#*h@bwmv;Vl2(}mV7qy%IvRBwU)Y`C@HH5|I@81gs1pu}?
zIrLklvl}+09xsy}J6?Xg4BPXDd)_)QbYH@EUMXGBmb4-LqV^}|A@`<xws-LVwB9b=
z-1&xc$h}bd#=skn^IN6)&f;~iwfXUL>r!LSvWpyPBq1PMFTAqh&_E0d4A9GWIy=qd
zegfiQ=i%%u^8oc5nxOt%Znf+XWZeVgbWH1PeFQq|y_V#jesk#T&?W;oxVQep!k#_l
z)EA9og~!fz)_=J;a?zeo6dr?c#aS47_|?W`@+Mp5pgwZeYmR+?kNYqRwdfg}j6KD@
zUMtaDV9!Nu(SNLZ-5fjcSY~-+^0Px*I)zMb9=}<0-x>m2PFUL{%e6Pio_tTZHwkWx
z9vCz_H|bn^VCN%F8N@ev69D@0JwHCW!K}YIH+FxgWFhWWTUM&qxaY5g$ySQSGw%iS
z{>nXb320>+_i1V>p~+-aAoER<gXTbX{9I?tIhwHcdKYC1`O<4c7q#oY^BFe<uKe_U
zG;{qO_Ib#59x6WX?Nr^7%qy)!LuX6%!b5K7Wqauz*XzFNk2OC%wB`OL#KMrcpD$9)
znFK@`7dDO+XU*NovLIo7d1z=PTE35F{iu=u10hqxz2Rz*ShP~r-XVr3kC>gUOzLIp
z(9jMzt@Xr3kvXrAS*5-IYsbObvjR$FQ<9X7+vW!oJI8Ghx&*TaWXdt)`coz|C39vv
z@k=6A8xs}SSh^+Uh!2a&F(ZCq9G;b{X6Lhs1)9+K!Q$I)Id#&gH_mn*Gky;y=#GMN
zWNIs@v*K(i=U#O$l2f{5T+mo*=4H<t%LUKjdS10`=u0gxyP$KOmSU=53o&QDPpgf2
z`6!vlmJ5T3;~B|QLxU}?2T~5PUEkw&pY0qRvmUFS*GU04fAGKm_$DpEUX4f`7}vMn
zzagmKb;5Y&PX*1R*n$5+6Z+^eaE0;43qnNVuQXn<d(q1J1-G@~c-8&92ReJRbT$Jw
z_T7C4z0)4opLc_^eM>(-a!#b)FilDH@%$FApbYnmnTTv(-FUlP?u7hbiT4k^?wg>4
zC-rYGZYdeNllfCZ%ReF6KUjkx{PA+9MXwVV`pzaCh053ibnsH&;2|#AIc~uOFLudf
z<v;m%vm~j*-(y&&2&@k?c@r=Bual0D8oM{Ewz?)0*+=I54+v4etKz6ObRykRJ8;>n
z^6_$1naU1LUac^Vkqpo}cx&=+du|q>O#|l6|9iLP1?8^R&n73&&GOp=9t%@vMRI4s
z%W3Dl{c{0fhuOvA?EIHp*i0U`F1mB~=L5C@wEnrbWe3Qad*6^4te$4+?4w-rY+|#=
zEXAdv?pL2&Z^gAY;iHhOBIDx2q)E>w{Ab=r0(~xpL9n0GYM>cVl^CY!&rDf`qrx(^
z?1SezVVTSSLAhU>iHMi%$fGSL*|vDyhn+r}*|cW8Te`8wGjq_OZ16`*rtjQm>8FhP
zKF{_)I|9Uih?x*`Y2s-ZXq>2>fB1l#d(y2|)k3E~R{qrd*eGeuwL?RCaKr3%(_`gN
zdL>wmoGfYCj=AaiT%qbtn_U_y&DiPDJ~p9AFvjhUT3teIZ9SZ(I!epDWK{GU)xmK=
zN&31~3$GBokXdhaof5B`3x~~}&MQy`RUI%Z$sJPen*Z6r+B!HLfN3QQueoPM{qrL~
zK5GB^FV1T9pRT&bqNCKcc~}AS#I61IX!)~4uH*{WiW5W1)<wm8z?;souY#L$m<srf
z2Xm8I0(R(yOe;HQlGWYOpXfH(Xz@}i=#9VjSj@Is71!8FvLO_tfw|>pbFb*9h4M+E
zoN#xte1D!D6k`L)jqHLGtGr?@40X<HFO{VIs1MbiO<3ify~g6F)*nqYFM6uKr)e9t
zsl`Hea59tbFuU2pezP}e?|-r)SH!p)DeaY$L(YD)NdLI3cSW-=2hK$i^_Z3UXW9LY
zep}QW{|0+4B_L-3LMMYScd`V?C)DB@lT{0#Bw+H)N>?KV7b+B%@OuThnZ~EqOFypS
z&8#%rU#O6(3yt`I@SJ4w$Zlt3un=UTCk|vI9<Wi-wp_NCPd2Tnw_C!>qfF&^k3QS4
zY;{Q$=l?E2{`l{>=>>T<kn|^7kM;H=Keylcvyf(+`FIIoKV`hS;~(S#xf8+On!Wxm
zLXrOuF!*g&l7IX|{_Q{hA=mv^R<qwh;_pZoXB)<r^=n(x4O3=J$wMP62;%RUl4fF=
z0UjeGc?A3qOeBBEb+UIJf<M4TK$E~q7+Wy9Gi9O;X;rpz{M8@hG%!<mjr{R<5BX-n
z!zCd9_aAA7jP2t?ANjF{Q7idDrOE<Fcs(HHGhQ^H1T|*-4Fw}RZYRxgKT~K_J4~ay
zI+oo-qRBX^rpLsAx059|={{8`IT~z!!SiqUr^F6+<?eg-uv4z4pVf;yjPzkKZ<&Qm
z?74ogmKfMLco}%#-mT5dxld&C;>o@<&{g;sJaI)gwpxSNhs-Am!40TKgz20r1Us#&
z`G_OBqpl0fAY_iGtyz7<oKL!g@A>P`unTK}HPDxhrZzwZI_o};bixn8Hb;<31cBc7
z{u(``p^`OibXHl0ItQ^&_WXF?q~Xs9-#0HCJKmh{s=g=JI8b%`>@$#gMl!MOgnlV?
z&^m4S$&qV9Xe4cyD)*Dnx83eh`+!d)yY$Hi$V4fm#21aMcLw%vvIiMDxXMpkrP*;M
zdD^1MT3y<Qo?j<UWJ&Xq`#sW@>0Xn}QMD7`tLl(3=)Rb8Rcl%dO<1{ky@y~b(_^aS
zg^4ZNK$q>qIWW1)szqHAX1gQ)Xq7x6%jv5`4uUv5<yu3h?Cw*pCWfpjr{{8czkA6O
zMF_tmkhQeB(wz}aOe%<`{FqO=_=tHnnG4>U{2l{WbG$k#7q(P;WiI=J=7xC`M?3xg
zTGpwOOQmRnscdboDEvgJtV|^{su+%VL0oji)lP750X6ZB;FOj*<y~UskoPT1d-d|d
z#>`|83_Dk?&DGa~XU!m03hWo`fLwsfo)DH82Gq3Dr*wD7wyNvggCz_c=wCXiUb29#
zY~?rqPyr)fNc^sb1?*AH_*LVCZRe&pz>6YGlEc~bDUy!VB58;0#+eTC&6*}G2!`UM
z=d=^D^{qbN%$_t{GKU>;%Cfr!tGNq2-_Z8xgN|xePU-0}c%axoUJ{<Wm1<zFo9VX<
zQ6M$kvAV2?%N#(u8qASf8?>A+EUq^yKcl^3%xUIUjai(eQ0HE%mBhV$z&~l{Pfu3;
zmqisvW}70Sb&4t9!B1S8xTNi$vTNpLJ?_Q!59ZWM_HH8p{1LqaL#GOx-E2a;aXI)4
z;a!2Ow0SbSxH#Bn4EOCx_CK|`lNpzJ?cg+E380zfinF?4oWEVqTrAAFmFK$B%c5vx
zgO2IhuI_aN7(hpvmh-V+`ti7SN;58z4_B?$09)#b$L4D1S-)3RgHCnhcf=!RWlrl>
zGh#|ucHef<qxSUnOKio@PQ3xtq4j`TSF66+F=(1KQzS~}NU18O;rCk54krI2+cm8}
zYCc@@`*!FJx4)lTQl-w)?tzS|vFz#N<a=bJuzqbkt$EJ${>5G6yELHtUE1)Mo@7!l
zwWDMV2b(YIhj*0I2V7^vdSyGrBcc+qO>$=oqUw|JtrBM8l`&P_5laX~^kEYR`sh5E
zF2LNHDl7%+36jATF}$p?JQ4!B^Oi3hO9cvIEkL}gl4w}XltiUvc7n!jFAOvHHF5*o
zDh*y$TpzdeKvf<eUr+gyq`*5Y(y;9l8g@Y2EX}MIcS>`Wh`1!QK8C%DwcjKU)%0@)
z#n4_LJWyV+B5_sAT-65R(SwthS%~Q$>?22StFCMxf$z79p*baL!dD?jAdxst*z9=9
zwMSh8klHh}QsulhukUy5$yqbK-nnl|wUk^06~i~=66&RdQUklUG62rA;D)y41L7$j
zrE}ocDEbLa=35RRMD|%(AXSq5OGE@ft>judj)UpO$#kzbV?{v<7ns@tcEmf7Jnboy
zLsqp~_FgZzPn6zku;e7dBFGBd5{j`ga>5*dCV>pztM*JU-KW`EjTj2%a8?6|6JC(h
z?@nt2R@$#Zg(SFCxCJuqOXe=?MA9ji+)gK2R6WOSI)N{=DDxIMkJ-OnCi%z|$4E!q
zR8(;_*PeBR*bz;aT_vX${&oUqmyR$)AnCpDQLR4Edy!-f4fGdo%%%(#HBLKYG<-W9
z5wOfKgF-)}+@psTmyJT*27M9S-No=3idR>Q33a&YQwAZ7v}Ktp25)<r?F#V4QRG$9
zZ_ORc#r%66KM~n(CJ1=qCn0546LvgNh$NCmL^^GSq9_V>geHK5ENGszb4*slLS<iK
zi&@q86jzbuQ3lmZD6S0#Tzp2PMZ~ED^>tZ^qXOrOR8Yl`(UQ})Tj{V(>+zT0n=t#a
zw}75X!sbN^Jk5#yiCn}|g20!rP1CaJla?cA_b4_m6Uc**AjkHs=QLLd76%+uz%^Wx
z+IjX%;LS=!@E*A2JJK|tB3w5etwht&&Zzl=p9B4l5NqD+Ox5UwGQ%5ApbmbsfuEV5
z@+pOb|MKF2dsWY<#E_J^?s-v!A-r5v))bMr9_3@}SU_#w0t`zhMb%8T(sD$BxAIP%
zmww?)G*^h|(tkvFGt58RAWrW$GO9ku9ydais%hp_d?7k73%jT)=@LSmQIVM0tk%8=
zK}Jm3(a_weSJ1rpBHUIfO^+>fFS3fv-S5VQsVd^70+ZeQeO7N+Cd~U5s=%sW_Ct(P
z9o9h4{EwW&v{RZ(eKRK<lNxWgN$g_N^N3kt;RV+zarkH|ta_1EQrJrX_V0?Lvg&Jn
z#aT4$x|Br4S{yLqtR-_i%VEbVhpaExt)SG%qmY&ln03;q>c7~kWFl!Tc2ZP)UzOZ;
z?CgSbt5g~M@V9b8PEjdv;asxGw6Bd@zGPi$qU4muXZeHmb<a^xgfm&`Q?7DC6WtUv
z{hWSDPe-L@;Ik<=$sGkHt&XT}!P0;GPk%zmNeAic{zfeZ#hdHEnH153OG3{{CGrsh
zt2&~_Xd$-|$|6B?veC+-7jLm5*Nf%6*9uJcC1dgEr$_{U$?aqKrR;Z{?VeI_Sa%S0
zfWfJ-v^gEjZy{|I`;o}dTmSMeUocOa!Anp&^=95HXlRy#=pVE{pwZq7z4und^-~MI
zeKVKY6Hl0z`vwLw4HLkjQ!w$1DPPdMym&AuK4Dv@dU_%|{%i0>yLMSL|H2U0US`ri
z6GR009l;SdfAuGKr+&A8_`_bZJh)rCHucEsFhN-b=XmK+x2IlR(6{NG3#=?8W*z?e
zLu5aDwFBNBi-F?2>l%}GIulgY($1DOn3*4^1>?~JRuFmQAu+W4(L*N^8%w<(FmIU#
zyx_@0y>BM^jLwdOiGhTE?+rlrdl$_9FLt`ae_<M#-tKzI$Ib>u<{WXMFmE6<#d%=f
zQI5Eo=~`Ws9KnZ~v}>JLbUE=~YiZq2*wLBm{^65P4o9!}-zjj$`Ih^ncgi|mBFVKJ
zq%LF@`iqyxf7;ru4PTxZyy9Ky`VDVh{}!XlY;+P;CXx{YBW5t)FZ+5yFneQVK()Sb
z^=|Fry*FyThW-IFV-!yIe$?>6-i$g7Af_Wf#*BM~I~ji1b`1q5)11vqBDU}<=9tW|
z4%+atFSDi@lx|2G%?tK*CowNre$&%p>&k*N@<z=$4eAu8WT%|d7QL{YFKuTZaU4dG
z$qCrHwItcq^WvDqqWfmu5%A=*$yCJ7cKHmZ%$1Lf{4JC1d|C95ed4d)vq}4K<hbul
zCN^BKVPSs%1~NBiGT_On2mjTF&kI+)nmFZ-&TZDTZ=QSRd*ff}tdF0YH5G{^v$me)
z<p3eQ+Q$!wjdQ(AKV42apD(^+Sz8X(A3jIIZr``ROjh=}M13TheZ_NtWyc%r;8%a`
z`(p=2c*NM_LvL#dd+F!JMRCJCRJ^-8`ndPDuy%g!^zukyYXJ3!{^;}NnS=-6xNK}B
z$+9IJ9;QVe@;iV@;S2Hdy6E+W=kMQTxW(t$?r^Ympmtt&&SiFfO_y8=$N%{5RKi&v
zutyUgfI2Sm0TN$hDSzzC_lT<FM3UOSH>+~@$$ujTHl^x!&CDf&gEnjetfen#V!ki$
zvOD6^p0f#msqF3?9Jif5tNs;of5%BsjFJu<qUmJEwz~ScMdr7{7oOkv4KbhaywS#|
zy+`2epgv%NFJB$oGb=aMBQN;8e$pF1Qe_7?7%W&kLv>)z$VYQG-FczG3Uk9*fK&Op
zGX^Kf;2#XNyyGQxG;yzpyp%WvANg``?=gV6l<z#)+n0*yw)Na(0)&6;XlIq=@8|9s
zpz-Te#3BU}g2%iLhxgS-b$7D)fD0C$_#uMk!Z~xa@!Z{HwfbyVxtKpqw*7<UA+kXC
zWY~Ta1ZDi(-ZHy6y<uKwqwi&7Q@vGwL3dh!w!0D!P(f$6H`~kDdbX5`kd?jP%K*c=
z(<uiGI|JVz*{15I<OAg`-dBHVoz<I}6QhaDR5eZoB#xHIjcMJclb914T<PM$hS@o9
z`p?}(AjITG!!qkJYfECMruS*1%`Wynpql`7lQ7G0O8ags7qzo);et?oON?6i>R4lG
zTxR>q9R!87*Sc74F%hr_<Z(mKSOA|wONej#FMCn3^z&XoFM(YL4g;`R@d7NUTA`HH
z$eqrf*CUFv)fsua{*jzE2nafwNMzLn+fX9(xdhYvhQ7^Ip81s4H=6jT&;rNIEW4kp
zvp6r!=|X9o`%3V6PZqaXDdbFY3!9*xQ~c*PiW^QuS_%rK<{x%R3f{0dL~eZWD2xqG
zRCzpj)tgVGqol@X$n(y_HtjR{0ixd=!8bk}M1W{fmaIx7!W+Hp1$_>F5{G(>lTxf-
zaNnCt(7_0Ia*>oH=LMXOS>~Iqu9GHdu+KmUvnhqjQE3`YRhTe|vQgqN<ma(WAdz=0
z(lO(?b2LifaCK^`!Xu_EB|lygfd>p8c=>s8#0NHfv)pg(?6}W@<^>kz_zw4&P1efs
zs!BgauOV*+n$5R_;?W+A`ot!Eq;(({%~svAb<4kz)5swv>Rg5ZEZ3*y?(Z};U5606
z^TYmJ;=>PaNWli*Cy=|`&e1YS0jD;S$2tF&5awvnV^gn`dW_95)%y7N%ycMP>jir}
zD0k2I=1b-7L?N|<icET==k5zGqT4-V4Kwxf^J8bbqxpx*-O%5Bdm%D1(O6=OPttyj
zSr#+gvMl8RZ%|DKhXH6uqWNfLyzCafur=B;O`#C`q7M3if6s$pnuC}FEq&d5`SXSk
z3AM_U5R!E?l^klwz1@?2In`w2LCc?lc-p8Ax?0uQ)Q~k%w+;B#7A;vAPj;95I@#*A
z2xK0QSzCru&MV)0k)-4|iKS97;xHzITSGEW>m!|!k*M<7vXU=*;&rb_jC-VZ=l6L^
ze&T@p_`i#_BtH|u)vTFwpEYyy!i3#Ic}_Fk%ZC-;>{bIsv22@4dR=5AO?7I8(<Mza
zy8`EO)0|Dr*#nDM4VT>dF=51?bQ2}NEV`Y-ix~@2k;;_0=NA>fs~J4vd#=CWxih^R
zhb%ubWOhZe)mFmml4<9|ht*=tc8XE9L<^#2=hk<&NY-gJhkK0ZG`J7IJqH&12rkoC
zUz!ArRnm+^1O}xdRI(@d^;4E>G=zIKutnfhoEWBRn^7mjc}Fboi_nqg$en1fA}Tgi
z7Q`Bh=^!#3l{wEjp8#6v&Je0zT678GgMzE{l=Z*e@ed|Jzq7K%;*Tal|2|&!wVhw*
z$EM~F2EHzNF#`GX1|9^4j<2`#m%r4`U;e8vxgXGXyf*ox4_OKya&hG$7uyfnDVaj#
zLw;nR#ve(?e&!Q@m)QFGAFO6lbFX~J+GdYGJbPy*^*e?77uct9lYOjy=TmO)_9y{q
z>I2rgmIeK#FDq<Y#8HvNmHbRYF}wC(&4=>>FxBKgPWtjXQ(~;MAxz5&z720{Bd#=P
z1?^VSa}eHyk0qd!{~(tB>&x<P88RzgB_@B!BWT~<{zHC-<A>XSwtsWiz6fLP@UKt&
z>fT6YForJ8!abKZBQIzd5~7sQlD_IUT?h_XQmYi5#$`ivjgXk7MXw}S)EcYw>9q|L
z)~uOcNG8vjJtr-%0u5Z&ov!+hF?`DCdfF*H+B0vaYlBhKGP*8n<68i7N<&rlCG|~f
z&K<0NqwJgJds0?(QW@@i#2v3#ouaz#b<Yi=X(9X_=C_|^SGE{tkNpj+5gqtrK->$e
zm?NwBl5O|_Lk_=(;YF7k<f5L}6%Bx6dJU(XYgE5u`EzE^20gmX*h5-@&B)1$)T5hC
zW3w4_tC|7D<yOtQ1%Me})Fz#tATrxkD5{g1_VB!0fOjHYcKZ4l1(irzN*|5_&S=W-
z7Fm(a(2;S!AvDryv`9J;QLd0RC()rn-?grrYE49D*xWioC`%tzl>vsUX;6i@+I7|L
z@^)GzmKO#C@D7{B&r#!&CKHiHg)wbpb#^Q};IhEopL5c4E?oGYOQM@HuAL}5MhRHO
z+U9=sXHXEwULcbY;b5h3r#aIR5kOZ)znv^%mXxHBZ^V2CMNY%f;V#eFCRvgl;*v<K
zp7we`vR69dIUpMGn7hmL$p@rTzF@!%NZ~VX<U+KGHNf{oGtmNRP=ES=q}BM{ybbXu
z`&q34mxvQv++XFU_90c)Q+O#QBw<W(_&dh{O)4d#2v4ex=dg_#661rf2&@zsKon(G
zuc$)#&3hDO*s-UoFj7;E6ql0Jn2cu3NN3`-Rv|@{496FAm43%^dteuOijj*Jyo%Of
zxJk39JK*ND%nJp_rjEHlO{)P5rZiidEC`P*f5IZ@PqlOl+(Hq^AbrZy3QEe04zDle
zRO3Ut@3Mvi)wGnHal=%*C`OY00BB^ITeLbz1E&ZcjA8J?YGj5L4ME<xi#Kb)I2E5U
zdqqH;nN~A~(Ql+lC8o{`@j!@(t&sI@F6dtHkd@H&fnqQtY0V*Q)Vllo2P5&II@hJ8
zt9~SH`hAwRoe<y`(v0LVAL#@LyDz1?axili{w8G{S`_};kI(}@7vqauG)<$c1b|9X
zXNx>#zvpuWo0mkT=+hBx*5#M9`h`Z+sxTj*SaB++n8BO~WM#Xj=5wwZCrg|LRmtcF
z#)%gIxKMbCls3t(Ww1sQZr6)ug!Kq={$Ut^D=pBrh?0t4vU0H<tj%Yh!X?B>Mu{FO
zcp6ldV*K{+-&Ki{E+40hSlCBdJeww^P=X$!kapXMuooj=Lvb7nZKZ|kP<qnv(~tPM
zC{S;%k!VDOk_MW&#GNN$hV_7ihk5_J&-W_#A(aok=zyoR;!+Wn+}*yEBej%&aUe+`
zKShB(fxOBHb@J+nwS9O}!hB7kKpuDr7ssPKGn6|WSy66%sY-F>VZvpNekfYnQO$t7
zd@By;02PpJ6F!;OhF9{`MdaoCVf%((Df<VdF>&IBXwsuNO8Al-{n5Vl-~Ki8Ci2dl
z$}4;mUjj0Gg51e;LT$f;B9l~&yu5&y$Qmm3D0T*v2ksW0CA*tKXUtu+B6I>O<!Nxq
z@~y|62wuwTV}H3`UiJ4JKKIIp-g)p;iWENg&aYQ~$2k1dfE3Egv7)B{%3)D_p17*I
zT)|^xBj8QF)f?o`)juj>+f^dD=&kABv^c@7L4sFk7U`tQcBvy4Pn6%sO)lnZ%nMIM
z0?dW#(CBh?PEgwI0jIb&4Nek|$*&ErMz>Zk->&~=US2>tC=VMan&oi}nB@a^HF9cP
zQgLhKOteo{9N}GX=?cNEfJb9dX#s3lLfkVac;%0t+^(m|e3s7@kzD3oXW4XI(Y~s`
zj{=6`;D_mia<}-^YyTQna!oXqh{p>-!NPl@;eB`)O4#mg@;-SA1^AV(#n}>x+sQ+*
zf{-8*`Hh^X?8*a$y>hC!KKXo^3s?vfiyty6e%vdCHQyc_Z=Y}Ql{J?jXTALZ!y1y6
zR|el)J@4=W$B4=o0J-K?@BhVsGE7pzTfdi7e2O89yxN3{N2_2&>onc!_iK$6gl)KT
z_1d?g%~)&hA&MYY8nCkbH>_Qz%ILL>aTTk39l!3D1sHE|3r*KPLEvvFFUjr}UcW1W
z8WLHzw|igvo-q%-QAZ8f@Yv<-?x3QE?c*K&5{n7B9jBl`{J0HeVsiwKj#_+2Dg)b2
z(GWgnZ{y2gSBk>ERYL*sb|A$e&(c<@h?2W~mWmXmEFDiiIsVIf3M0X@DHb<NQOnbI
zcyliLtH(Q}ba=gz=%lJ?&PxR+rGDjGUK+~Gt8$HxT|vGTa%b9oBxiA5DBljHa*|dF
zdyc(&@vW|xrP1L)Y#bF@L9xPr;orCd`3+C?+CRe2wGYaC=Mi3X>&bs@g^%=^Oy{{q
zI)Okqy42kIDMS~hDKNXScEm|S&oeimVE3H0Zxzo|yhX02v+?E1t31#7qko3j!ZPzU
z<&&~O9xBD=2*YbbbJ}6HC!gmi&K-{pt74B5M1&{9n;2?^&v(2J4ZrXG;=bf*Q&>aZ
z0qX&eeftgug@NFkjp9H+^yMFwnKYYB`~8WXRWotE@ATm64SRymOj~=4uL&#qKqDA@
zs(CdSY@GbNw}}7uTiBmG@uJ}vh3kpx6N$M__@lSD|Kv&Yt&#((dSmG7;i0z{$)EXq
z%C+&v>Mbvb({AQMDc}b0>fw)l{jQuUwIrv~hx|C^l4S_A$_7(ypKzoxefNn_RpL>!
zEgr*prXxP>uwC}({lZ1BZ=XQpL|STGMnw0XidjP^OD~CjuRH2&^@6R<D_4W~)usWJ
zcaXmBGaXb*OlbrC9~1|Cx1@Iuy;|yD?2Zn;<`%E6T$}qzE?r;?i9REd@dsZvOKe*$
zpPKp6D~)Tt|Hw-_dc<K@oNhn!?O*vrOhmx`V)epg!w;1LRr7KaeAf3h^4`8ieP5Ai
z5QfEi!9cNB4kEI8V-8G9rVASIzmi=ET(k0TrT0j~Sbwc?-dHdINRlrabBW|@jb8Ym
z6Y_uLw{jR-%Je~hw7)ju6hxMXf6^aukV2Q&b!K>r6N|yp<hA<7eZhiXj|G1Hc7aHz
zly_8CixB4ik{+{KBEMavTr8j(#u<uyp3(rHUiZzHDPg-r6l$%5%16mE@!j$N_G1d<
zs9~w3gXf5Q6UfPN{L!MnB;U+)k)U6foxgqLVz~kg9%KN`C1(8d#(5)AFl^qCGR+kM
z`Pk=5qG6slu5-~QC<Fo@It2Mn?Og?l5J7w*i2AarsOpMja=Jc&Z1~@pEG!i#8~I`^
zzi}fk^|@}f9OyA&yaD6uCR%|<A5Ca8f2YQfXp-(}(56S_>o>7tmZhtS)zYj!tYWTw
zseSB2?+J@j=f1kJ(h>xgUY_*~f#c`zu5UzRkjt7xaKzZVpdza)D}0>)VU}svmzSni
z8VN}Tihs<IFDI=(Y)d6978gmsvU+H;I<(UAPwBVyCRkMqCx?OcVx#hldclkN0j_8D
zB#)pd0U9cw5z2+1$ur>-!xF8P22JxR4F!;m*o)Gj^Pr`xB}%O*mn;>UEL)fdEdTjo
zStc3hw^b&mgDHCPi9)_GaW!AmH%>GOOm53AtQ22VOq6B8NG%vMj#Si830LYIK!R~e
zb|!=qHj?kpMC9A<P+Uf9p_2K_zmz4W<B4>X)!v=cQCuZ2RXJE(nrtjh6uc$5fr%9P
z+JTr>x{_=ngahsqR_cy71woFRDko)6a^Cc(d=??RhWfNi!!2vgB#RpUZ+!F5m<*>t
zb@{%wRPc6j&)Yaz$W2~FRTdq2p1hFTO5-EJCeOVt1+fXKw_BZW_`BUp@bsgNrc^7b
zzBNvnzS(|hDs-b^&DzFcHj#?#O`*Fqsw~QCL2_Q$r5EYPSeeGszQx=|*y@m6&@QQb
zhOeMZg>zuz{_(I&OMM9S^j(dBV);Rn62QmPE>p5CnNWy#NQOPfWLwQ8{`RNV%eaBt
zR$k^g`KaRri}hH3;@Z+=k)R5xNrk$7(5`2Yhg1=kB^@$e!vIOK`2MQwQTZ9)obr>g
z`kV00Hn2S51*_+kwoF2a{%!roc}b`%w}pbr#wTc!t9e8+d39kS&#vFHAKjLTLcwKc
zpsqM@q>hc3=A|u>RXy<Kv)P=84YcqTGqQ~7RWnG903(>rUp__VNoYuEopwEQm^Wv1
zkrJWAUa++BZe+XKrQ{{#g36Nx`D!$k?Vb3qhFY$cV8xP#>Z$~n*lfdS`jlZM_G`a}
zMRADEm`xo2pz2GvCC#A>fjPW*l)*8~C6mPkBu&vmn|Fshq+W6OV`$3INKE;)P!jK!
z08iycIJ6<lVS}P+pUt~CR^HDKBh3Tw4$FtnQ>oDg-l5$mB_Js6y!0{Gq(5HB!GDY@
z+-X~7)a~Q&q%(G&GR~3i#AMf80+R3W6`_Hz$GC!yf&rUBL}M%sVloC-e1}d_irIv5
z>%a~QL4i@ZRhyY-z6?&ixG~WT>iZU*ye>Nk$69Bl#5526<cN=$vF!{IINvS-HBxXH
zjR?kT0V_%y9Ak~3Eb<)|lwp=BwRkzdi1k9(<Za<WJ9rKTVqsyyK@s<17s6P(eO8+D
z(FVpbtQxO?`zX}w)w*$(NBPZ@2G&Fx?*vUOo5(cR`imSy;o^AzM^4ezr5?~~tGeiU
z(tI}Q4Wq>+exp4KkXPR}oS~=X>00t!!axqPXQOBB>dV*z<~gb!&<F>OX}^As_MUy0
z@I$rrBii0)e~jiQoWLo!r8`RX9X$QrOR!$o3%nj#Q^HW*Z4nTY(G<+<P7|&t(IA>K
zG%zblhW4Q(G9s0I<cLpTk9No_R(mPW;VY?_#^d+g<s-5?jgEBg(b0ee7rfV`^hK*0
zD&J3`VgX>yO9<?`&kCDkhE&IJ5Gl`(Hc-JBI4&Fip?{lTh2>zoVtKNCNZV}Odgf2%
zC{Xsom4?sb#`$MVUiBB2cyWEg%W<o0n$<gH>tmFtFbNt*d@zoHEBG@UCZUj$VARmC
z4A*@#@mhnRua}zgx;x&F8v58r<758?8%Ko6e=D6lhv*$AKM^Q(eX_Zv?<;_45!|e_
zjVuMaU2ph=a(*Q6<F?6zR(m&sLRf?ra@PXdzm|aPG&IGlol`zQ+HKyy{09w0C42X(
z;(PQv>9z@E3dO>{U=ivqUO`)~RUh4=x5}>1NP}IvDVVHWx-DB&Bwh$@GAjxF06Sg4
zKBOWk6ivQa9&|%i|45^K{BPC~?V?z>qXq_#jyLN0@#q5Hx+p_$ntJu%<@iMcG^9J_
zV^k14!_$>VOM~E7uCq!n0qq!<5Z6QizE|%KT@b>c&;82_ZDSs`Wq6+0AHDY`1FwE}
z{_Y?QEm6v~dx>pn0t}r}w=t`RugNA~ZF9V-5@;9#gX+p1To_Z|X=-SUFnIEpANd7o
zYfvC+(mqCM@6qPyHCWJS@<M*&1lEJJ+BH*0jb#TnBRQM3=~RGYRopl+86||l$}uBZ
zFs>SO1ulMfPm|pY6SaJH0`Gxq#M-UAo>(!5ah36zx40xnVbTiI;H$-x`WDc&XmQ+o
z&15);nMt<`AZsAc(94oCGD8BB4R+*1z1A)O!KOrpcFWojzMRgx^6a=5Mb!e|Ta>N_
zgH1m`7w)JzGc`<99Ay(}uq~pWP}M`R;hHHV&!VT*Uo@tCzZOBWq*q%J4wqGEYRulP
zU;6{u-1K9dNL#FA%H+eEBklUWtF-un3^vw0F*oD-rIAC?;)GNO<xmb2vI-Q2-bzNu
zB(6#qTL;@m%Wuo2?QdoiKXpb18q&et?&0#)ylN8XOxP7HN#7>hC9D}A$O3y8m%}1f
zPfIh;2B@L6T)Dz0Fqw%YCmW2O81GWFutTky0j@$8QW8X<|Kq(1?M;iXIalByPe#9m
zrG3}<5qNooAe(&c5?Kb&iUK=v3>Yx#M`-Ysc~u-Cr-+*eur7u@Mswe(4cHlkq-h^I
zdN);UyNwlHL(y~5oZ;=e28#>%sJbWXylQ)7&3uGTN0QCTJvj4r|B~UqEMNT$-40iO
z-f#vC{-A;cck;&YNQWIm`^5KD3cq>)FA&}`M3k|1!CAzz1~RO=Q`|WUG1_1f19ygT
zmA!h!q(}|G{$Wrm(xTQI2|GeZT<P}VJK$CRBWWgx5!&y>f;(}&xUW#3xVp5j>E$=Z
zq+Y$NOUdhJKrQLeD}6zJBS&#TGcoN4^rONVBZqHK%lEY(%qJQ~OW*1q#)x2}rB4pe
zF+SI$N?b4OYb-_SQ0=~Phen~yU_{*8q;YDI6U@1<8n199fQOVF$v%Y3j09Xqhrc6K
zLe#P=rTpv3bvy{l&6SRn!&}go2++VyCKmJF#5Kpmc*)wX)hyI?zNllIoC0!W$F&(^
zGmOHT#)h@w67alm$iqnDT;dY@J`ytCZsUqnWO{}1N5A!6*+(eL9X(o>#LG({=^C01
zOyMo&rD?k}cB7Ze8*341<S<M$X-rmk#W}|f8II?qiJ!r!(e-e(^df|DyBTCCL%S@$
z@hLgT<ocEH9Yj?Yf%tiGAy_I-Tw7cMCAnKVcjU3wh!P4=43bCj&qN0i2KX|KV5NUa
zHQ<p1j|c$cbDYcQ=v+bDuQ^ddy)c-XOMLrp?<V5l4kUPoag*&5TJvJQFzLw*r6wAK
zfn6&G-EFk79W#|^P>4WQO1i1=JVO`^W+T#MI8K23a)Y1JvLgB0MUVj(p~Ui@??{)%
z!&b*?QYpY^q}CUU7}t%(ea)N{6ZKv_P$E_-pmj5N6!ZZq9Zc9tOVgETrzQ?%JLWA&
z##UnYI}{-V^-{}oo3XCplj+j!>W5er3fUe^N{0sg-~|g|sI%txq<v?Wni4Q0Nb8=Y
zD4OhF?fOf@h27`d;Aq0<{8%IOss5dgEgbR~>E+A!NNXugmppQeWE~kpgCH&u!xKi*
zOQj(RPs=ON8Z6ukU@tY<;l>&@Ng+c~+QJP-B8(qpCLfmIwFc{>XL@1!qYu8z8W2;`
zBFCS9p9~4ZkUM;Zj3{KM#E@e3V)?s6VYC}y)d_^fXzL}J&qx_GLr%ztgVT0F>9!0v
z(|jvcH7R@Mou|1-YAx3O@vT25yEs)^HAf+2={bvdHoz9**ok6%UwagBM*(PLKZi~5
z{R9)y&KbFL%ZkYlT~?68@xl}|<u~~!jXhnUT{b>t-L*6#`J<<?Nz!TDf%Pze7-bAE
zd&R`nMaB`Kj)bkc_5c}#F-YuX9AVPeH98xZD1J8GRsysdFN|Q~Hm4;vg)PSTuPO--
zVrGi4Dq?)~*WX9`^Ab6EDGv`9z!282?`tmjgmr`$XcVPfQvy^5>9TO?yn*takUaRS
zh7K1f)sH4u*c*_~8TnR|qg^nbFFS-BQY`lq+O(sKwa&$Kj0b{}FXCT|o)^{}Q+fN%
zI0OD>T;RXlpk^rt4I^=x$G7!Q_EqYk5x*};DOZT7rLb3qm$H7+S|F(9#1{yRW$3on
z`8)}uIEX&PiKz!2kIe=s#qIb8bQVLDBF)6-b^w{xdLcm!0c^Mpr-0p+BbC)tN=2HV
zN<{ni)hGiNLi1JE=P~U<XP-d05|)-?4&`^d!u*DP+hmN=i3uH~;o^|>04S!i(j)NJ
z0K9^>z&A-th-R(XI$kRUVBGr1@8IZp1IA><+JIEZkpsAR=m}&X8+OGzV<`%Y#PKo=
zhyi0rGpIyXlnmjp#co5BLrH!F$E3%XW_In}n0l)2FZb?{kf7Arm8PVd%OMMUQy~tI
zIMU%1&kCy*exQx<*d~cXDH2$fE@V}C0i?sh)X~HV<8^wNTwy?^8Q-iP@(+}PYJYp<
zdk~ZKF+^zcz_k!=I22`x*9U~NG$;Lk^;X8n42Z&bOb#02WYDbE2Zdl0J+h5Bh?yx=
zSlQdPCB~*NT>nfo^zCZ_JCDYudj?>TPn6*;;Q8^YYj2d%7j4S^FNCo^Dz(yAq$e{Z
z7G*F%fTf1+Ek|Z|bR}>j0?k{$^#rAsin$uuP(cR&`wGEmb1{xLp`UT`b{%;?<9u3E
zAz%q{Ml@#CJcncEKn}rE5iAF}jp!DIkTShPuP|bC?aHD5o7y6?_KYrdB94eM@e|}@
z@ku7dCX0M`JEm1IoC<!a*^ALaWkETma^kz&V#Log4v%4)!AgOjdTChcJE;1ayl5QR
zy#D!#2)$R@$+d_W@QXn>(+9!mVt$gA41*||cdbJKGazrMN*VfrzcA329fq2;pHJt&
zCKY156p&&8A4-Hn@nqDrS^(*8<(PKMVJr=uV70s8J#~~TAH#$dmY8BH%4U`k)7p^>
zH(}F&73njWO==+pztZ4Xby`V!3r1z(xOj%&<rR16cDp|_p|G)Cd#RPkAbbT=l5zPD
zsTBMr=D317N{-et9J-?nauf}1YA^Lh_;^mly<$^{H;GCZH6-65)*T3EE;TfSa`4}p
z2+(vHMSkQPI2zfpS9`AX91K%%-20mT(!K_X3}FkcI9FK)8Bfq2H4Hd4Yx;?+VYp6I
zAC^#>$IuAX@E)5aKGsG<5W<=PkQZ`!8YsNZkV|4<vJY{PE&vEN;rV#b{6v9?o4hWK
zBpoX}FF)jOfQq;$l)CwH0|+#1;#Cy`!61gKU8jJEhYo^+z=?$BWK9Vx)L(h&e_Pka
z%+{n&0F4GL#g+`++bG8tfUoZgpy}X@P371V2oCM8;g`eqMWtln!m+#0*KuS|;~*zW
zDHXJRR{Cu-)c?p27CU^YegshAIo3qTs$*J#fhMkvdP_{}0e|0ad1)gUEE?^JF{yzB
z$nDP5emuj-aO#wJskzKs4;d08KSCpfmk~1DE(O+zQhoFt89+-{)P9W|u<|d4^oyRe
z#CVeagnF*T7Tg|2JBXal?K6-{hoB55Z>9dBX{<9>f?Y^~LCPsJIc#osgjFFS2Kfb=
z3u`xRivq5^A@nRVg4ZV(7o8={Emq)NFd!vBEKLalo}d&mkd$5uVYgcVjU~QEt_c}o
z5JJPMA)De|@C-u=hE~R{`~Nr$;-$@Mi-verDgmtzEX9P-HTon5Qg+eROK4+>9b7`d
zaw2Btyb%ckAARB<2NU8l8kGWyQ1?WPjPh`jLfV}6OZWuTNH3euNq`mOztYG#IS1qM
zE`k_ivWT+ryDvZ1?xX7XSzI|_0dkYRY}K?OL#~$IvOxmzB-0+)#yj7MCl2M5S{{2U
z#F9f(*?zPP+C94dLLJfL>grL#MpTU_-tlhQ0&8jGSd%vMF95u>J4bj4Fho4YAm6VY
z!ja*3@w{stj<AiVA+qJJPsl0q+dVqec>wpTi%SewX!5()#xvn#!!Cl5uhZgkZki7{
zw-k;CDk}m-B!NUoQ<!|v4cRSytn%%*^JYbR>7T5Z!M*H6?Mk6+VZA{?3;BIlbF2)b
zY45N#ggsbO@DMpl!q%__upGCcPFVhx-h{~wFJX=nh(S&ZGGdTcUpn`-gU%wO_4|J3
zC-AiRu$3ldg}Vd}q_ttwfUEf1#RZ8R$RKs~2s13$h_9CrgE`KaFP$$z`0A*A6qLb;
zp>9$>!~+`royEtL@wUD(g5&*jiQoRGcZJitK<VKN(C*Og5Z+9Bvb!&lbWCShiSsBz
zPU3^H`WeGG$Z(KGpKM5jB2^2&v+@S%p>Vp=*7@wGjCzK@(+F!CkJM-pLwo!Reoxx`
z)jk&vnn%4+Mr`}821@`KOaNiQ*SchAbNHq{0Llzt5ccXoI`IlG45cLFVgz$S0>U``
z6oPPKjA=p}yedafJy`~S`9J@6{3+UvZm&o|8eT$4^nbMJ`1K-aR<qrm*0i6Iiv$CS
zZJ61(O2B>+om#V~vQYtqlSbhwLk`)F_%iO3W@lAIl%j&p$ZyT%@4t#0<B6+cCccb%
zOrJzSqw^al7qKUI8h(b@F*)w3nb&#1F`kY^m+i~bR>u+yfzj0$Sw1aaP7&Bb2wkKE
z1gEz}K#{S!$G<8yP?}C@F4~%a<K;i4e)kfyKfc3wMj9Wax^^>GO`1JlrbB7iH;v(h
zj67D<9LG=aCpCoujYg1o+?UZQO~ln}51|?od`m4aU&i}MD5QPJ$eQ41!5_W4z%&?e
zBCn$ax2<jnUIlWnaFhfHEH4%~M4wmtIpD@<L(b61po1&q0D}>}$-gx<B;=;+BDlS+
zyJThxE_0;>Ouu>1(UL~9@0!1482ZYDL|Z)n4|DGyAIEv$cg_q}%-Uuh>~M{aVTPJ{
zu!ILoN+MUX4q+O5cezwoFk+FglJFc}Ou}+bRgx-lud(A-FWy-UB(Q=kinSX#O=AFp
z9Jz5LN_Jbf>8l15@T#V2BdPY)N&BiK+PS)I8iTYhR(x%J@6R*)V?Zi#o4-0(?2q~J
z{P_O<ex7HZQ6rU{(%vAr09n)YdE9KaWj*N4&atkKu}Ljk4S22%SCgG$-M>}L@uzCN
z5h&{dbQm3IIVk^Z8`OfC8E_Oe8TMaRiw?e=l(<#oA*??TM3NOO`Ip9gBO&TxNzeNj
zcqNBdqCBKL76I<BmbS-hBw$Q!>DzXTSUAU+Tg7y^tt}9{W6W;Cr1m3YwNCnlG%SmD
zL8^xyjWQR2d+~Z2i2gGRH6Scw?CU<l4lGP&^mMh|5LqMv7w`+yQb6&yCtcX#f&>8j
z$H)Mo=bg_g^u*DpeHDTH78C)OTXvJN*JO{LRdMvP*GFPCTCspPM#z*=XI3~z{N6Mo
z8uH}+-2`64_{yd|g<}DjAum#oi>-oK*Ov}DAZe6UN&*(b)-VL3kaY~f6E$&4c3k8E
z;JXqS0trHPoOj3+bS{7C%Wzx9y`QlPuVnmhi@6RL3&&tU!Mc1I^!}yR4iSZY5urn>
z<OqQ+kv*wizXqxD@udrLj+%1zRB#_wc$r3AC487fCwTwo-)#Hd&o^ySt;nDH5xu>q
zS{F4Rk|NcZerQO0h?V3!akK<B*rEo*jWUA$^oCNoAjJq1Aix|4V<3hPPOyX!!?1y8
z|4T+uEKt^0>kB0Z;MN+ycy3e906C=0oD@Jn)DYZAV~-C73Urybi=stx`8}$MZ^U?t
z&osLWqZeryYv_=LNJQ@2zXeP|aY$K`U5OPS4%(}EQd`IHiNwDgChqASmlz6eeBRpD
zeE=9ybf1P^tw-)-*jBFSx27X9B{VvN)yguE9qs^20O{`i>u*Mw6h#aM6bcM#fNZo0
z3sT~NJ3;dmnDjb_D55#E>6|1n#V^)Lcokn{C!km?d`*60Bj7^_OEwK4?~X}B9e;aI
ziz{esRx%7=e6F#XE|v?M$s)fH!<-vNcKI#OBLgfS!wihC0+h1Hra?XOquI^|#{>e{
znOWKNJq$;#_YNWO_AmaP;!s7EeMc-KNa_=`3k;YQ!0!d^4wVp1BXWG64%q}4#uIK*
za7fv`-lL$*2a|yohNzM0A_ihW96D@4IRE|kd+02h)~C9i`Eg7EIJe!DcQ=$6=k*`c
z52>D)PL-I*?S@p+3vg+c0~!EQj|Ftm3C#!^3LA$2a92w|{0>Uc*k(_f(0m1;$G6Dy
z?_`ecsoCV%UdbDp*5|cMAOv7xnY;1&rx7ToykJ}Ur6Za0xwu?d5tZUI3FB)@Zu$i<
zbVno{Z2yCw&c-Vcqm11O_%(J`o(1hWwY*rKZOH|oY{S~+BXAbDQF;ZO2hPKCa6LUk
zXtVPd@i_@oBp)FH*4*b%tXAaF+ZaB;4&n2E{0<w;3Bu7PqubDc!BWCF{Bw)#y^PG#
zecF(-IszQXX=s5z24V|vfhODQA$z^pISkVA4U&TwmdMJfCmWBpC+Mv=<0HKMcmAEg
z3j)7>Iz{g_3&0`eAnZN4)ewZ)cS*X`dUX1@K+wn#?A<)x%NjHKrh#cT=%Z|t1c6nP
z$+#FTP}GB!wxJ$&Zomgw06EX?+Q$)53_5{z&&oG6^`vnOtmiqrpC%$Q3)}|Dsw3O%
zxD67pK>rByR!em|`=!?ou@wIf<hH<w8nRGKq?Cio(Kc>Eq}ez9_V=T5q|^f<kbh7)
z$=9=s)Q#aSwvZ`_0cG|p7fTR*Mh4@gfxS6NoFzjb_nV!A^}_ppkpu+PN45ccA~XI{
zlYT)R2tdftx%{@@Kox}DOWL(D8$?67cczWSJC~V(xtp0O*8S{|1&oCvZJGWDk}+cK
zM~H)%RM?AyXgA5X0u!*AhcNxLgZX*5$y_ofGGxO^?>UQX+h+7UknC>Z_|_(f{wNR}
z9~d7RFaRjkQl<)kc>zAaj8Y6W@PK`Nlyf*qj6Cil3yfSb)PO{y5Ccv?G5N#J<@3J`
zlEI5jr7{DPsTr-k45JhOZyhT#nrti2SwECV*uyfwr^4K1S>9fXHn8mC0<MDm1WA2F
zo$s9@UJbdxRf+^&dgtzJcJ`3QEv#>LX9N?`7J)#?g(M1?^!}zaU#N5A31HoHgBS=f
z!yd#uGGFIqt1Pd9y<!kk<w1%=hn3TNQDCL?(vP^3MWUgeYZC&iX>S0JTdmE6bPU@@
z^$N9mo8t9F`nSN09}vhB9K$q75c{g85KTjCATuYHSUQGu^?`(OMo~bt>X$@(;J}RQ
z|6jQQaT!AQB);J|y2U`Mm>y>)Dyo<RVCAl8Hoao5m#=wQ82oX!ld)JBj7Fq!jdxS=
z1K0!2OtN#$Rb_vZa=^CBKk<31kJ7j7kVU{-ty4@t-Fxaeyb#t|reeq=o!6U~A`Ftr
z6|y-!xCdJFDnYK&RKq$v2V-;^rzc3JzgYxf-2Lu<1%AqGVy}8EGBMB=vxAtkLOwtY
zCPz5P6Kw%ZeF#{_6zmVeKEM<)_}gc(Tn5p}S)S-@Gm#?8tR@l7>Q}AN5)eDu`8K9y
zA+3rk>_OQ;^iLyr*dmgU#XH-AlMw+WKZDJhCo1q2+4$K6ag0Du$rzx(Mi6z~7wA25
znI5Ow1};+(0Q`zBKl=p+LaDr8xZDvr=rK)yT{=b@bmwz8<lP+JDS={fs@Vg{B1kY&
zFDSyb&9l)V_A_KfrWj~i&T?nx?Yxr9|B}c@0d>|VD4qe2<Q}spp9S}3HaKcFRJtC=
z10H>5ZLvb49yb}wmEYq1tcyV<@bBj(Dx7G5pEv!5H{nJ(r58%sSO=4P{JD$m*6vO2
z@j<BRNPpuydnnUS<#iXx=`_mF_q&!M7)~F5hYpbL%N7xLU{!`Prbxl{zdNr^_Vawg
z9Sj}Py?823x3)Ixq}eDFuYT3IXarIO$Fy)Od4E5q!0IUSQY7ljd8h1*VEb?Vj4~7@
z>3zS-ZGaX}t?#~gib^g@G^IyFd!lPk)7APkf>gA#X|v))4x!SlnIJuXfLVT$VS1Py
zhq82z9$vouz5ySx;tY%;Lqv3^Gznmf@e3JHo5b`l#Pg{WD6De)dcfU!J)$X`pp&|x
zp;3H5GZbKGPe!t<mGN!g`?nDtVY5AMDr81>nQC@wi{aQd<7W*}%zl!oD=q3sjjX_c
z<Ae@m=hBJ3)f8E%na3h$s5a3%BRd%H9cQT|*>0|Szh7W1(6%CDo%I`liRIZKxU)q#
zQ3pn1>obE(EfwGc#p1h}V-(p@Z|Xux`jVq$I?=$U61N4}aVF~6DhDQ>qO2)b&UMrM
ze~uc&seUt<>!&c{IFZCDCQ~;q0=MQz5WxsQQ>|ZA=>pT>F6LoiAMv|{=oiSenRcpa
z-gcs+D3QZFdyUB4`Te^Tr1v3BM``^ia3W+_Iz9`s(dN4hqg;M}LvQN@Ozs$PqQEj9
zx-4^Lx1Nv@Vbjovl|zEFkqs+Fi5<4A<8~5g_tIY)feiS|o?f8f8niAK7|6YN=W{7j
zo3Ua@V!w7;f&!CAlP40l3s!uPwBGv3Ve*3QE#l&JCm0jbcyZ4|#(&&jzbG3}*)iTP
zJ@;nC<Vu|EK}8evTsrtH5^4>4x{343Nj0a_ERe(m=n}ZDf#p%m)RRnU3axmQLzgwk
zj@hRT^5sbcF?KeBrUm|Y-~L7`b3ICP=W?sQ7sJZ*^4W_R^;6c_6IkRl3!y~&p)8U6
znM98g8`w~Uf%eJC=rDmK?%oDmLjq{xKmZl4|7(8^({E$vevT!VBGaDf*J45D)}rOZ
z%E@7<T{m1Y{SmUJR>%+oD+B@^Ib#t-4=Zd(vJewd+sZ+o2M%6TvtsW1_exrHQC|`i
zPw+Yxw6GWqDxPd(A#mtBx=%3+h*?RuT4jV#Z~OTJ29p8_BnaqGT#zniW=RZ0??DSJ
z#NmdQf9XG3uR6#uxS^y_4|cama!*3%O$bC0!<;_Lv*asA@8%}1gm08<i-j_3=VIKz
zJag|Iz72mg#65Kq!Dr|`eEn`{Xl<C@`^0TDG(8808X$U*1RdaG&@x>v(sMdu_7O;o
z!^Obb4K8toEZ{37msaia(RAN%a;_znJz@OvL%-02fwRVBGRPe@sN<GWEKEWh(|9Mt
z3sTmsD&EC0*n)Hu%xNGeVx1h!^KgtsP6{=^SZWk3yGsy>;CEK_PF)!6yeV*BhcYcZ
zm3%w~ym(CFO=OVwiqOIKs@HL${eu#FDyK;(vKh=V5#)$+VzW`qtIva?xt%Xvk+5IQ
zC~QRUrF%fKuNHvqTXoS%!BD^Z)_O}!{`A^juiZP_^YD9LuRVYg(pn<_1~Xuo&eq~N
zb@{g7Zy*;jkFYQ~DvNnu+j~N|1arbsok(MCg8sdlef_83^g2XxTFgTtHzGN17lFz_
z4DG}y(I(qcRb>mecR@$^@<CPo;8^LA+9{!iXLg#(wWm>DZs+BHy7oF!&14ZwI|L$I
zJq6RY#5X2q4L97bljgZk%5zPFNNGu@hr7QgQ=k0$>#&TRwI@NS8m<PHOQ5M?#G#JS
zuq>dVHkk1zh)>2-j!Vs$-=yEY=JjZJ6>;K$58{BmeXhmLG%aSR1rTTxXP1lMU>QFd
z-LvzU`lKQt#LCNT@hx|D@A&Ub+GS<3Uz#Go5|tPczyg+G-b?V)^ENtxLU0$DHMz80
z%><RQe%7ej85F&;`ybnPy`%q?Pi~)<B4U&_H<QiL0$~dla?mmei~L*gCY4(DHk&2m
zd+jK}4!Y}vkKO#n{)tr3=ayv`zhGAb*&NoPb19>rBK0q|BQRI*<lvM4`uqB)hzrLM
z0(wxtliNKCqkGE*f}b2UPy$=_z*E?36B1?iza9@Bd}LVqP}Z_Z6aBvIkp1E5-}Bp(
zmsp{#zmb1h+q2aGl*RlYLVRlLpTQ?7E^m2Bv6%$gcGZc!Ywo@8`*T-2EE-T;Joy}>
zZ3O)-+#Ir!Oa7oPq9Rx#uRfAc)q*4_xX3rhmc2d0GI0H^&O9yx-~tfZ(iVYup&^?u
zaB6UdbW<@i8()ST<(G^NJyb5eQy#c@`_jAnMc_3H#JP0_Et!Mc#!_z{XSo6NVJLg_
zOQfQvKFDCN#wySkWq8Ew*Vb_x308lj27<Uc^U#O{xmm4^E6|tRWw65rak`slST!xN
zS1=fZ9t}I#FW7l$v%l00yI2xOF?-6m*Rh}s@TSN+$8-z$P`>U3&!bULiI5vJ2N|!a
zWBZ+dG^kBqMq4Q7$ysi)+}pm>CVWsh*L{FaLU&?ViX2`@r^I-)G1uq*;g?_0V}|-0
z@@ky|-icvs5d{j<y8iL(UIi<xd43>R8oJe)V&CBG-k0rn{d#T}`5oC+8GMrI?d`qX
zVq#;bd`@8_YFaF;7=`X{v?ptlwYEc9>>vLpi~VnW9xDLIj_zLM9uDS$1#K-kV)deT
zj!j!26!@8<;~ecZ%UI#9W(wwrn_c(v?Rlm*gnOr20Rb6;R*KAr?X~7eIiuD0e!c1w
z=UF43<5KVNcc<Un`^E=YM7Cj~ws>tJWmwcf4PvvkB6-oVTCOs#@}1iC<b6E+puf>{
zCV}s@Zh*m3auh4FgVL4oOO`AThI@OV1k9F9!=iyr=okFbxAVI|g_)EK7Eb_;x*lU%
zt_FmLm!V}s0H71>$dgahAx!1e{NAjV@BZzaztFOF$LL3U(<adtrx-REZd&gw!plw$
zi7tgl&FN=uXTKM}`kwwb3>6EKFuSi+W^x0-gd#X7gDvfE;-;-zPCIY*=n;x%tz_Qb
zXV-0i^tbv2@JVFAJKE7sTK1+WA*+Mq2&m@dtF)aPy?q_}ynSltS<)S%UK+>Wun4QT
zneOg5p9V_>AlyzDo1Jv;-_0ojRAJN9!@Z}r6tvhOKt#iq&?{9IS4K9AVs?}&C&E#P
zWN$?p_PBTH_CLQZ*E9{aAt}h}?!{m?wW%KYoBpP<dL>GH;f2cXZ}f{UBT%AQo)Eng
zZaR_kw9I402~ymt<*h|cDSN%@<eNA}GEGyIpXS7ZW~zG5v0cpi*>6kl^LIXV-Ea?4
z59kwRY-%*`)Y2jo`w08=Htd8PFZEfC<w#!KY+JG_WsRh2IT_08*?!l9!wOk|&2F2E
zjF+%##U|)Eh9d((a;NbXvp?98shCbAkj$DmJeZxe{kfbM);ez*9iV3yXIXqnsr-(J
zPNfq?SpShzP}v^Nl?~02wcm{GAIs|xdyg-*Kpaj!E2D0Kg4{*YP>3NXB}wd;VeiVJ
zVwp2*=>`X~FE=%Jum?x4_=&|W=*nUX(N#q`8q58X>MOh!pw}-=#(_>yk;2pA{{HcA
z{^NX(0Ltzh-)h*xiLE6*Sxx=ZMG)00p5!D0{2UjlZiv3aKK3qq=@N!=uo0@ZFyV|=
ztDfbIJGP#|g^)z@Z10$-`8y;{SbeWDap<aTdo0g=4k}DtETT=x@#XCM@Cw@tP358C
z{k^sqDp*sqWcRMx{`s+;J1}mx2Fo4fC@1&wSbrAQU;m|CU=K&WH|qtei2ah;L5sf^
z>mU9<bBPt5vUgFic8u7*BZTJ|{Q`C7m3Ixg#v1mV81{+tvB{jDRFo<&LSQ7AKc~-D
zkl?7w%}H}lPh?1Q0a8}>h39g@gx%7H!)P-J5@)|@El92?0WQjU;E#rY2O@@0$b*5j
z(1&aFV*6kHe!nYxGQ*QivmEt#vBfBFW`6qT^pMk@U82<f0Xuqud`U>Ca=5$q?Ok`f
z!+kwyBxP=M>lE`UT3h&y9d|LvZ=%qIidRt#ZDc3i%RIqA2>OLze=x@nWu9b<<PA)k
z;FhIRvkcc#s+78afeN%PKzV|;;Su~7WU~a#5xRfj_Ag%Qf3*RO>QaTwj$oP!nAk--
zUDu`&!!o7n@@JSEJM2X_`=w-Em66OWX@7tJ^V=Wkf3x)g2+%oOTX1StNpV5R#L&3g
zL{z^Ou?{YU(9lmIpRC?hV$NCHKXBLJTwJAK4vRTz*6A#(-Y8CPXuND#q;3@@1XJGK
z-{4S|EFpU~8XXE`@09H)Zt9;*cSuvQmP7%>;XIUn@y^+vpUfrFGVBl%b37y`dPTTl
z=?NcY-*U&Y@^AWf-pW8HD$>{^6G`-9CW+!##W;DbLCUP5fp!!RvHFcwh3dN`MPN&R
zfA90<-!A0#kQf)3s6zS2&<mz)1h_TH+wdI4{}6}j1cnawTf?LTNq#P8YkMbb|JYXt
zr;;P-zC3P9BvabdG^w@?r1C}`-B&IT0p(PNt%j!ZKzKVu;q~%>=O4=ZO&}b*>{x3v
zX|)zx3>7IVlREY``XGo+rUpyU->Z4qv_^8GSZ%Po_htK|KbzY{&ZJ2$v$JjH8MJk;
z4gN{h49-z6u*dc`5lSBN23U_HVk8u^dDNg`{fl4P%JF9u_Gq0K1%kw%Xs>K1^cWI|
zUO+V(t^UaO^$SurVG`oN&K+u(opIsqxdq3Wx$ZPjx4jZMaHTetT4C;&22HYvB4=o9
zUIo`AiD*~uNbjocU%tD4J)f94Qh$jT%EKBbRtiLneC99ZM^}m8a{4P_R_XL2Z~pqV
z{NB6swFoq9X)(U`CX`CB3RpZuG-t?^*3e|cLYaAvJtC$Q3**7ZwSw^cM{>-8WVl^+
zkbNo$9<UNxY0J+7g<nI)WQTk24}53%QznLl0|g-_YjX?Tv$F5`SXDa0KH81|4=+SH
z;DIcr7?C^BJLO#;%%%NGpnzA!2#DV*ZrY)U9bP|?Za|kEhM8;-8m1N$xVDPz-~HoZ
zd*}#OEPFMCjb-)ippwpp1GIQ3%)=6{`nK`+^E<4G+#>pB&fzFied%;AmFp`3ZOqv#
zwcW~49tZCiy8VlPrT>*r5lC~$H7N3&k|S%x2khkx8(QZ*jG|kVnscrqnJxB?ujeo}
zI1D_GK=0KukqRK>G<q9tr*wr|`O+1aq1>`s65amE{m+*l%Rxpop0u^WN<J5Z*^|q1
zz}T9+Hc4~{fFv*d68KaMhQ=dc;{Daz_D}ypewSt*EfKQNP(r0sG*=BA7AO4@IBSCm
zY8&c?n4^eA8qWLcVV?gek9jh+R{oGBK#sM!qo8q-yPM@sxi%NXNh54pB_0f$A$Z4H
zL2GlbbyCj9eh7~BHycYhTgT8oyzjGH^7ix!i#=?97P2TnAqF2_3)SRluqWBw`~4#O
zpWA=@w*FT>wM-q5n3NB!gqcR|^dja7%H%Y`rd)K<V%$S@v-PO+a=S8=S8wnCKl14+
zkv;?@UIqqbdARl_K^U|fl1Ls8FOJD8W?^fuJatDcqVH%8{2g|-cgDY&8&-|JW8Uqm
zLBU>z>KQ*{`9FE=oE67&Dfs853WvgnLc&ogj^(So$*|<?+mpY!BSg|9tvVAd0Tgi~
z%bJs*P7N6%OkEa1aYKH$jUX&P6%Ag!{p@UhkFsOAb@;P|Uu<nkV3q9WS|`c2LvnV+
zV{o-~9Tpj}JsNhkf5sjAas~lqf-5lg<nk6dxF&gUStfe@3!n}j1WGBG$?2!nJ8&~3
z2M*=LC%bU_UoQ_zK*cdV$F~yJr$lp?69#@2(dDFDM3WtmF_Ur*83EI*Bnl(Rv2IZK
z$3CAkL7>(I=BywCg4Kd}<Q)>DJmqMzXot><^FxZ#0!8BlPpbb~2YlgcZy406Wj&yr
zR`Qk*ECz~Xao^A<*C#~|G}+z@pdpa{mN|cUq`Zvwj&48l@&0*y)&YK7!ES62h1)wz
zbClsYQ5F^f>CIh(uuJqU$8x)~uiL-$<>5Z=+97By)8#f}6oUTXN>1IxT8g5jc(7di
z(SIl^GD`G!RBj7@`A2i4k^@$%qyg27+#<BeEz?VchC8&H!lgLFrr7}_MVG@}y>HvU
z(9Q2t;UM5`nUc0$g;LxdoB<z^U0IQxQHu>_=%2OHgR^^Ip1(gA*yGWh7MIWJ4wqoI
zC8H(tG`PrW0Hw2s0{goK$51E3^*xR1ALxH>|I|<Pzw)U>65G5*&I;zsDtyloM_TKY
zi*0GF9H@GN&Pwfin-o*K<=!L>xWE3P{^uX(!mv7Hl86<Z*wVzhQ?pyLR6|nRz+GW4
zY9RlW(-MVwic{&{Rc4}B(KlCfu{}P(Ij$?XIeTd{1C*`Y3|emEGBs9Y8thecYqd~P
zk>h5sj=z}eoko%*0xW^bs%->j1rdgJ4+;}OY`lpwsul@zpDJ`()=yfC&4Ipo#`b&k
zONGJdc36xRKrb=|s$6A}8=x-Am<+4S0&<9iroxUqD_|%VECZG0MTgDED%k#oArCa}
zgRjBJV9L0QPgA?MNXYDsQ#re#IF{C1N2*>7n#x`}u4>eObuve_-dR8N1B25wnuzg~
z9b4pnDoh*kj*aSbK19KWNGnsU8V6TraU;zlQq1k{9l!C_!HIT$tKzB#l6C4i7LcVD
zk<fA>S0Ijs_Uc}Cdey&Nqfp4Xrl`=0Yx?u)>vNpa90I6ETFG!m3!P#<{$3kV^h?7+
zT2PM2Nz#T?500=ODayd|YpVJ6pYNZC)zT!CdVxTf+s?OaI%-v9a0YC!YTP%MnXvT_
z>nIJhe9AuU`!!X5>GL^@%8YGs>dxgY@a$vUY@&G>l#x?Y8_`(B+kr;OP1}(;dpBFZ
z5&h4fyPOMkR0)xlhM!ni0N75G7^ETjl)2|)ppy;^`2_Qj9h+mlPGs=Ft^FEBKL+ri
zp$OPINy?+}_9_}lxNJ@=r#!T<R<ErSSKswNEH?YL{VzW>+=YAtaA9UGr8Y0JNEYd?
zH3`Eq1p#11W!i?)KxSpHQG$!HN0F}K&-RCJ7}kW5;I52ORz!YIxq)z1xlok9e~y$^
zZixsuCv_M*d3o9d^<>Vkspk5BmmB<qJzC*QfoSVg`{JF?X$f$#Ax{bMg-ZH8$PJd*
z%G4JW5n12Cz8?9`>@W|I&ZgDaBBYH;vCnQ2-!ErU*6*3(4p_+_&DUT5K+llFuN}Ml
zhyU~A{cn6)AQES&{Dj3g+YIhnJwfS*G}N#+)~ILYb~^F_3oYWdGuyQF+;mGWXap)|
z{F}#%U(~oK>z}fAJYtUF$<<~x%8o`!)<x3ZrfgZrhfLDz+1Q)@Am<P*1vSk@a2ivZ
z8;rHg9_wi@m-h=5Dk#mhGHy9EI3fok8>n3R+EiluA4h{T1sz+7$5bqy;@J?`b*6If
zhHyJu$}ekXk^3E?4HBx_tjw!%*C^P}ZRUoLh$#e!>-Mu_yMgkU!^krDP;!T5%3KK6
z^%|X3Ju**fo1EvcAKAA%{!`8d;vI=%G#`H!Oz-0C?kx<IE*)Ma*$_h@pWJXR)<+06
zN=hV$X?~pmWBUVN92S#FqfKR73L{`MT4&47>x_J*6iIqcwSqwVWk@vGq}rCe*LujG
zo6L!$9;bn#U9`9KwlB5_&!{#VUFsK!KBLxlx70gVq7BRtUMiH)88o7Q<uC5(f8$eA
z1hwunRWVcWBCD6!o5(3Qm#&~p^g831_%dXS>d30f`ge6@+sh9OE7OxotoRFeP^Nw|
z1>dq<leHa^%Sr&^ucB#5-p`9)+BhPeyL$WSso|c1?Bl_Xon%3XliV6C!wThwb!Fm)
za9GhFQfr6g@4#DnHQf7&Jl279D1JXi8pU85HGvjkQ6bxqSaeI`VQ~nxf3Vr%44X#D
zI1Vr9op62I9h{11k?G(+Xtfz`(x4r9jve40UI;UkI1w!644C3v8?jrAFCUfmO5gsW
z-yGJ1dI`&J$i8n~R5lG{j!oKWIcTpi9O5x;IfrQ#3|A^cm6OeWO}~3MS5sy+5Dv8U
zS!kzcmz1;B1ad+l@u$(eP(6u@Rqb9e=(4n#=t~HqOy{ut?AyD}=1>nIU`zwlqe>v4
z23fHoTaX9xOY{eu0s*T@P&9vl3M52ABz7bd{R=<+D>>olO{6<krXs*~rt<K}0&A)=
z^VGY@rf^hFozmT5E^I5YomU&shMY|GuHF91seaY?Uu%RVjoc1;43cViS4o7l4C)Nd
zl+O101rLWYkW?Jy%6ND!LcV?G{GbSnuWNiwISM1YR7UDx?~;N>c`jIyq&AGzaK8;7
zl}AvQI6G`xuZEX@AU7q7;X*4b)K$LoxlKZl2I!lW2ATQZ2Kgk4h>i`Ra%Ez{Bqz2u
zn}hW)>3v>k<czRYGsy{Z!OA`tB`9s{V=_4zTuXOQw#<Cw)!NP_mXu(|Ue69+|5tM+
zATx}azO^o%eC{H*`!ECmx2RpxJ~-Fbu6}6GP)P6xMHv`HT~;@S?CiDl`M;OLG<07Z
zE2NwvHG*qxLEF$%!j-EE>yaswh0{gnA(7=E<aNYM4h*Q#uk2*bRV#^A*K88IC{F_v
zzz=my8aL=$W=1G6Bj;d0(jo20Mlh-K8Zp@p{`s&4l7FOMZx_ihp(f!E9aR5hk%#Id
zre!<Psi9O-l=53Bs;()9%@L(n&&wa)0jKouOMdQR`OarIxlv9AN@WijC&MI!p1?q4
zg|CDD(Qj!BN=S=_dwW%F2Vcr{E~6ywM!3yZPc&^XDVvnzgmsm8flSMXB(s!M>*(T6
zZ{Dlrjt>`x^(mgS^u%t7bx@Ko3h}Hn84^u_s<kjO#KY?~4hH+^H1%CITcCf|cYkK5
z-l>Z?IE4seA2+@sD=J>h=wD>#xLDn%KH4H-%28D0wWBiX{x!O={jq$uhV!;2Q#S0`
zW8CeD%`9ttojUVu>QOSA^pc1A1V>;p$#CQ?1}*G;*}mb&N4YE3iz3wZT=|AF_xz-O
z<ZuhO7dBY0nLD^gi$R0c@d&V4WV&(G)uoKp=?9tqrmkRNpq8F%-niY1<HR_VcQv_L
zx%KsgM}_koT<+yH&r}*bvbN53ukQP7g$K3rFcxm`Rbl&!b?-EFa&K0p9yHNgp5DGy
zrd$q&E)O6lh_G=ErbT0YPS%J<BYcLElB6}79<A_@_r#0CXUZ%H(P+hS$9N5{-~RD;
zI?<?i99%XCj&YNN7x8o%uVNRNY3whs#0nKVqjzsQ&PI9bP?<qUwuWL%x{$i`5t4Au
ztjpub4^@tOU<bFv;UneQ2G2YWmGqi`K)hjE2A}h;Z@r<114KN+US&nhT`o`>>kVmf
z1A1hK#)+gkI5d+At#x|JD|Jjq*HR{f6WYtR{gs~{LJYR(QLp7VV_WJ#eiH&i$%q`i
z;}XEL!QuY7YEia5`Aru^P(aRuGlCoZgPVS(a@;uko8Eq}QZL_99xZQ`e}pxfSR2w$
zS$77Bf#VEcljSRvMGm+Xx{x9x%Wel_p;~DKv(gIumr>I+S@4pD^YOyS_*yhw^T!R6
zLhtOgy7j9C1mZZ~JfHKa{RaLSKevDU#8p=!s=Y0Bc)B{@hkMv@wRO8nHJ^O<_dAtE
z!|K4M@_g5=IF&Iv;h&D;N@ccWF8gN8t9RY8)~;mMjiXyDkCY>PS+LnyXtefj1r?;H
zJX^XmHMgGuN-FQ(OqS=;+q;cI(l}H`gW^^_b)B*Dx*w00Z)vrU`h|xo@$87m<B!)W
zrsc;la-$rgn720z&XcWO&Ovv=tq0y}-4o9`?&!(1QgLqZZ+Gj4W&2{M6?(U}nyq$W
z-2X%+8LPNSD?lr`_pSbkGMsBYpL&xF9h_`q02(ZF5i?2^6gOMv?sooJt(^L|7m)36
zq+XzQ;joT#x)FM@bJTOT7vJY_PkE4<(JuG(b|P=W+wkMcp>ii`qGQhOej)LlDem_5
zJqMNH;d6|ERvL6-y465!P_wgcr|U9d#7EzX^>r=i5==X{yUq4dZzGPU(ZyDn)GFbG
zCsjC#NEI5P`_h;A;e>wNj9Cfgc-x5?ABvrL%nhG0w6ETsJJ|716XQFqR?LHeI-7C4
z5p;~(3SD(zH1N#x-4llO3<Kk=L_9*h;hWa!M$~pDY3^NJr@G3)*qQNyxY>EkcWR-#
z(rm}?dh45=&NIPym$RBN%NSrj%Vx~wK2;gKLo|a`EW6(H*^w!a1@sZNpiw{Q8U#a<
z|Jmq7_jt8(usffa^|Zb0nH3~)s&K$h8Vkl-{$QngrW;S*WrEOKJ|Fx3$*|ByT0?U`
zlGSu33aa47`zbhzut!yw9v*Yizqh*FXWn(4gI<TmrJ?bn@u!2PXIGI)O?bF$77P!^
zs5nO><RhNznsmQ+)_-HN?mq-2k`V(<XM(%B;cBx{yLIo=m5T38pYBfbbSyLOVZ2tF
ztPnD3778m(r?b{<*RFr^`#O#G4;sHz_v)!RldwwM-iBOlX)G~O;#L9^SaqwnSU}Qq
zs*Pgn-BBaPqIhO@K3VboW9_(Bb|!asc8yN^w{Mnb_pJM^gMQJEr<V_#VEM3bVsm?q
z7VyxeIC*>XJ(bGYGg0%P+bQ_tYt3NVOhqF<)?D8V;_7;3qY{rTy?WwPj-QTAc_k`0
z$%4y+1wVzDhW_DF=ytrY`-rS@e7u71VaJ|g%e2C-+i8}I4IimPINKrq;+2MnKy;$j
zXkQ#{$7RRN9IiySy96+&n_L!DoMsTza9{24QpJ5nR%LGcufG#wMX6J9WQ|#@C|Gu#
zxSl-XhrV&c3H)We;NIF|-78EHYstBzk0LmJ=&@P=b`>vpyxT$#oY|xle4^rXx(zSh
zpL*u3*J&;_y~ZevP9zpxFYfpiH|!QB(`NkYPyPd2A==^637(+Ns%<8AIx@@D)MT|e
zE_0$r$1|M7G8>&*;F!8;`o-Yx)<$`p1|i2C&WCjM_F6M^r_#g=y>Jo(PdCDD>U9d+
z(QTcs=}s8eIHQs0_%Uh}x?yBIRM0Ug7OBhr`jR_3O@Xo0F&RfTSqCPGoU@NdNi_OI
zv{3TeFe3C!=e%($G5A1t(d?>s@Asn67#?90IpJFKK=aW2s41L|oX)G~pL4pUPUF$3
zdg4#HPHB|?ARa54vFH&__JV*G$iSrPvpE+>W)#t*4d$R1Y*g#s0l)s+W~CByPDn?c
z>2a^wFjIy7UcFH7x<S;bbRUbHb0(^LqupdZ+P{X)pYh^<@GmyNasp>^$$hKmbVlOX
zF-|#EWg;2jP6XAUEUyaxA<vs3gs7GZ?Fp~rR-CYa_QvhG+RG8vgVn~*H*Z^N2J_wa
z{%4!-2~MYHUr9^NH&R#-nd*8uJWOAvDrYL~w)1n}esi!AmEID2EG5CptU+nIwD)j4
z>QeJ)<aRu<2bN-484!?}kVAf?Oks#ZG+9(5VTpl8(|ixAFH}l#`b@KNbSn-M&uKO%
z3PCtgN#5eaVV;cZg!7S!{<o>}q39tV+|+$h%ik4QE~H#%F(1Din6zHpi0CK`Ph%oQ
zKbpkk+*+(?*gOfnqaH0H6f}{!y-<yiqp17L9H(~*Jh$b%f6h4duGjJB&3w>4SSc6B
zSZ2KftM)a+Xnvx;R;dKR)Z^v&rIYjvPFEw-q$6=coqN?+$ERbJ*r`GIx|h(Fqvn-{
zA3qZ~Sk~A{4#g}YTwcNt6?sfp;chrits5~>4bJW)no})wDsGq-f-1(f<2ECw*|`o)
z4qyFm?_iBvG^V~8Bqqg@1syo*kGZEgEdDl$v~VXe4Y|EL53edtbao{4{OLF%z~@bn
zmt%}y2}e+Y5L$#4<hb5!dJgeJ2M17zkdi2h{Yo9*^tKm5_c-$mHc=<=4|h+)g}YAK
zDRFT}7M`Fp<`Iq|juks!YQ`hj1>bqTG7>|&x)-JugQ6h}?grkiynO4OPQ97>-hww(
zpi*RX`s5)$qPcvXsuU{o6HncITj>#=$JuaA{cyy3Fj|D<Xesuba-G^)w~9r$WXtp~
z>if5whG%%ZiE4zN5&|kTlJJh_FZ;V#U(!oEG`DHaHJi{iTyNTQoO@jV=YI4}rhH@R
z?D^7i;|+hlTl>^AKlq@Z)(;<^bW7>jYQ$QDrHB2)hpUZJlo*d?FZ|^RgZM;UpT(k`
zb@V!3?9MMh=*oC4o*pZ-;^5^*bEf&lc-=qvThk^@s!w4wf2|p_kcZ^(5#vuEe5JcO
zH+!YroO#iFeeLV!uFw2PGu}VHctdUc%f>y}dgenj$;k8#A3FGf{nHcX|2D@indnNb
zIrFVr^Lg|5EmL<*%zx~2jp(QS$x`X|e-@R>`=T35e?D0lNy>YkiAraizZ)Em{Bxzf
zXZ*LmQu19wkm-f5b)!dOCx|OGBf3sD@9rM$HlL}y+>A`^;P{7v%ID+gvB;m@G-h8s
zdD}g={pDc#>=olDr<2;xf1@%{2!G40+;UIknzP;LnIopUzx?&|vT6R*C9`$g(fRu)
zx?gCXNpGrbwyUrDRl_nXH_VMsez<AMb7p3(IrXY<ZfyD&{PeHRt=%$r$GhG%-u_f{
zBg+nz-#Xvr?E?!*=S;Hrsi?~PBT+Rf1*?0;+WO|k53&~Ar7jEZVnR9-d*beyB#Ck4
zBz1B1aJdreB>mqQESxa$<jM98&FNc%ljd}i+<lMRS!1!p$`OteWIP>5FI3hm)z#7s
z&G(t+m(BV+j<`28XI4we4f7vm5lK$w=QZz5d&SI^hxR&eIpaUvjZTzm)fbmaFO=3M
zN~Zi!T)r_HpL^oA!_k4i;xD#W%|Bf#{lFrNTy)l0I6JOh34+Q2vskQ5td&05zT%hS
z#rE2s^@Ym$=HlGXnCg{B{l!bo>I<`_gHKO?zT7A-f2jOEQ+p^rcwh5r^Q~a|El14$
z7nbIhZZHQvTxnh~4>X=OpD{;oe<qE`=ANjUSE9zp3;TkZFPPR>|Dg2r-0v^UefBRm
z-(HTljX7}h!Kg4*IbjaWn>(gnsk~}fP&#_5d5d{)VxNE8_?p>nHjljez;n(h55w)O
znZ@?y!%@`-D!72YFK$Lh)=G;fOX@|rOs7^13)h)=yy1HXOKZ{id!LBdyZAn%<teLX
zE?#`GMJaP}6}BxF49If&z?lygj{nU5^R@94@qRB}eB(!n#y${5X8h=!iR;ZZQ@s?O
zsLaf<&f|NU2PV(X-L?Pexx;bgJ<T={$BpJdginhOOj3zCaMzJnqRY)@9PjfhE2c8D
zKKZ~*c%roDMb=I(uNWHp1JU@1^FZ>+&zd81ON&1kjW4)wp)+q`9i;fkh_g&z!YgrH
ziPVj?QcBT#>K~~T()}lI+X(jm9m9GqjonAS);Q6sf8&)CcO75ijETke`%DDuCf~Qq
z@%LfEs`F7a;XM>YQ_$h^ZMU^~R8VW87T*<Jh>u>Xe4)vTFx#ei;O#X2Kx=9}+UM`5
zy7AT4#F`<RhVloRpT0B_2A8L&lTLST=`E`_A8~=$&c4l5M;8AXR+z=G)NFHPq+`~Q
zC{ur$B6wrxfl`{>(e%;}{tBwAX4mf6Jdv*Kd3VW4HzVg_i)Ni5{@H)tcUC6G8^p0A
z=gje?$ES_+L9=dBXkA&Jdt$$rF8;?#`gm#aSra*7<9zd;E=hQ`d8v|mm6eu1cIlSN
z(>IMAFHNrQ3Etv9-1W-UwVLB>MC0Bkzu~V<`1MueR6VV56<56#BVXgJ7^I$OR@RGC
zYqfpBsCgwR6<F~P*sl^L#|kX3yEyK_->J2RQ(cP!#LAiQ7K;<zwNfkU(B8DM@}oD#
zmD_x8@gJGB!;XPx)$XO}OeI2!4<jmZ-4`vd{D+cL{(*?q?aJi`x{Jk94B_gD`^kS8
ztxeF9dP3s}6RDx<!S`y@_v%j@Z!vhSQmOkik{I-OJ2WR+F}FpIHH#|~>8Q8ZHkATC
z*Y}Pz{I0k7M&zx*)7`@J@v+v^#&0)u3Jr@-M+8+!=gj(^eOQrd+Jp?xn{@t&^OnYH
zDJXBpaot_^7+oXIU7U{m;CRV6@Y#c@gmZMPIcFxk%6{Lg++-+RaNP%g^0w!fPIM0#
z|Kh1F&9Hp1^gF93nB4O9XsUGbiAr?*iQ8&Co&-J8r8VO`e#AJBeWJ-DTHC0?Qgq~7
z_^RT8GArUeG0`PX@jYpgl=jektPEnmxpMRG*NdfhPW$DRngb!@<4ank=aY|qfc(Tg
z^+eXl6u#2Rqkh*k=lr;S#Tb^*nm-;t{=Sx3eDSxLQ~F%kJk{C`g4PEM%cXX=QQV(&
zT_TLB6mwC3aej$5diC))KfLgvz<YklJ<zJoE!7vkg@vp*=bB;3GaL8wWu}mJD&FXo
z8-9#1$t<{?krh8k%hSYejYo0k<<4e`h>=#$C(cASDk0(fOY=!()Gtm|JQT9@{CsR`
zLD-#7!fx}8=YqxgO7P%BT8@&%waS5pb6~!9+%%1ULwdlN<A!9f^f%`T7NTGbmfx0K
zcg~P~R7S#ee<N)>&1Q`}%Gv((^y#zZw{~6oUz#kIAzG;#H6Hmul>pH_^=O1=I-NMM
z)a^`oW#U*bnc9^m;e2v7NL}l_HUcacp^Sgr*K$X69NC;*BIQ`|&$T;lgcG81wd1we
zIXJoN+<bsY#m)`?*NpM@cfIt6X0sZ-V7^|yl3sth@t=>rt%5&o{4Af79|^vE>lYdy
zSa>MCH~vE7%)&#9AB#UTHulw%uPvH;&Ln^LpZ>(bDj!GrcxCgok8?@&mBx4Ud1LT!
z<F)%$#%sa)z0>(Z9-e#cfqAZeXz~5=8ijrIA75Pa$G&>x3w-Qb{wC-0nd<XW_i~Wl
zd*lm^`EFL)Ew_HP{o4J_x0P?D2^8{5^5UP`6x*bHQ*3Gf-TjgKrX}%uuRG0|D}UpM
zL(NZRj7v!f0kM*(-WHO{u>KuECV6+m0SYSgUIm@e!HOwp(lU90;3-xY^~N3z9DZ{t
zX8>H;&@?E&n|oGNcvf~@2ennQkL=yXsren(d{>Zaw@?4)J66y0M40qke0Huo7P~A4
zUo0)3>2{JwVjhIT8qxmgZcsflak_iZtB@|n%iZ(-)O~*8;0M;mjCr9w-%Y2YXQpoq
zZZMNyG^M5aW~FuRmZ;J`Sa^GL%3b)a>cPfeZ_Rw8Le@EHj9EL%$67Qq-vBf`(e#73
zedz9Rtz4}{DFD*>ITl%d4~gqaV}2&7HN(ft?Xa>?`9$=w1-F(GqAx#VswJMKc$_RP
zb;=7zmuz}C4Vo4uu@kYyhkUcYFy;p}?3<}{x@Syf@fkzPvFmo<i`(Za!Sn6MqA9m&
zI+KxikY<@(rdnAWJNi_!fxeD}Yt0LBrQ%I4B?Z#xu;SkC`Dyr>@~HRja@_9F*!1Zy
zy&-JafgXZy0`_tcuS9;h83)H>hehqXWUS3@3HYKJdsB)IgY?kB{lOEEba~Y$R-A7-
z=lq~@TN^)U>c#zUTu&;d;}Xcb5sDjx4O|#9GLsZK*PV`LkfWKzGc#_dyWWUrNXMPZ
zr&BK^<vQKPQO4kv{KY2{L+&@qqvpw&qg9|igMBbbQsvPTqs4`WI~F`ToyH458PIgH
z`2@fW$@?VPpNZU+2;o2~L$BsEoiOnf3OnJ%u8tdybig|+k=G=X{GGFJw2S?+3xJ5E
zoTfV=Ju^aX5`Y*Yf+#E%c`djJ046;<A9VI0+d;?o0F~RpqjASuHjGmkCkhOaK^*xQ
zH)vc~83U6ksATM%@nWYPkAL~^zxi}`G)_EnVsdp~LwAflP+72n2y}3;Eb!~blO(J$
zPu-eMsGKLd-5&cuYh+Z2iN7#E0eS<a&Erj;QqVP}B6bz6Qesyn0lUrsRTWa71mJx_
z5^QpH|AN=9RtoKJKIeu<0q@YW;H+t|x-*mq-#P2IzX8vKP9^b@l_)VA@i={a56|&3
z6G>EBnlLvrw&33waP7iEH>t%zJTc#mk9HS)^EXaD?m_=Ltf-j_5GNXkYlr>Xxv>^N
z+jHq7vkWX$+<heDmB%6kG%QqIGyRciCuqiV+duNZIJlCK47h%G7q<|E#vAwIWmY*=
zLhDQ?G0$C)IE4|}W(TZr8nY6TdV=x9=8*5CQ5z1q2G(PU{3=X=NM7JKxxSuy^tWvb
z3!LWmzdb^!kN_(B={W&Sc4P=cCZr1aaS?*h1q-U;okPC}yh(l(o{8XJ!Guw{yGeu3
znvu%sh=4BIU^Fi6`mq~6a?){{DXbXpro<AAb|I*Km_8P5|K?AGWZa481V|HAfTjV`
z-`!1|V4*;39N<E5fxyI_s8K|ABUgwuqa8jCP0d-c8A2g&QAmfPqh;f5x8idZIz8?&
zP#3yrw`-g^b~xMLzMp2uyV4Vk1pfkisWfrwvFFD;$zU23W&;oyTm^k}0+WP^fe{Hp
z4hEc7>K-lSDg$;O^D8tFxZ--HlceZ2U5)*A2RIM;o{8M%OMhWEy1(EW#~+Q2Tt{j)
z2r+mTMA9{Ce>y2G#^Nvpz(YomexURq?Tj$smhj$j7gi%Y2hiOFwh`v>f{~q7yZkMX
zY8RV9&=p}!AlTl@w?6f=luOqbX5eHbC3Ja?IxQ$}Oq1XP>Cg#}fJ1yn?<fzd0G^m6
zs2f*KkMtjT2$MaYp0Wy$LV8ETss&DsQ7EqLR0`%@mx~ygsOz0$H-H+DS{?8bU9j~a
zbZ70b0v7|Y;)bY;OECeZ7<jqsvA%e$8q^{k>`cJ$W(b>_u|bcKU`PNf7+#6DfAe!r
zf^pNyYJhvz=lKrCwUeU~uEu00&Lk+1;h{T73}^Yb(j8}dgO!Ub!69&8LSL?Lc0B}u
zHjMysHdS2Qbo@D>@etiG&i3-ZSOK)+G33o9bM)@+24s{3`f=Agq_LjZPdm@V)3U%G
zorI`<93dwLzMX}$q7X)OM4V{AA^kLCs+CQqsm&37bPx(auV(Xif?c5*L2x9IY3Mx|
zL6I1yX@{Lr4WnX8=lVK!b;)?_I18mPuri&oz*q5C7H(8R9#o^$YpTA$nWvv<6ob#+
z_Fp>Ck?f@ur&xtYb%~;BdWZ&fbO!XNzu<)YQp;B&hKs@p^l$X;iPISO#0f`e{G?~1
z3dhk7-o<0_o=(|rnz;PZ^qUB|)szkw<JizEXW5O<qEjim>}9Fmef4&d2b?%K-i|x!
z#iSl|9@%h1Nm$tBohuN1%HZ9bhIaa1!^b$alPr$*xuQX4pNPPnyvg?631L?pk3Hcp
zJmv${JQyvr-Z-+ECdQ0+SEGgIQVqW{u@)t%9$`}p4o#Z`1nJi4fcNPI_r}0flPHNi
z;H1xzZ;qcgpSzTJ2cplRiD831=HNp2d~MPstA3?JxU!HKLGaE>)2RV7;RK`myQ^p7
z@ijjPVlzEnS*y(N{r1HlUh&Uf>LzEp)2W$^4^K}%8;{ZA<?fm8_|x%flq@&nuO;5T
zcpoiUIMYqym?u6jJQZ|n@xo>>85HC6baw?n#AjGyK3O=kP>WNuK#j@58rW>{Z1-?=
zdO4Zv29ZCJ5T=<}u@NFa)_o;1-Do12z!t~8x!Y;ZVNZf;g}9=Ny{RT{ZTh4MR*qKF
ziTkfCx5LJgFg1WRzX({?1J%wX<R<;MD)D`=1Y)LBc@{xT6Q?JMewPtd<MvL(n+tmr
zNGG6eqS|$Bd9NgMON_2*XVgdNC~>?2(4%Xh=`FRDCN@=j*|9$Xmy1?gI++L_%&vN-
z)PCFkzk8tLR?oABv+F--9%4!E;FHCDtPuQOp27ZbbSAAn?f(%_Z}G_If2Hw_<{O1f
z@jtQb3ZQe3{HvuC$p)*8SG&z4?dsFDU*gp1zqs^r^Y7eDt>cfC0IXh#PLS5_Un40#
z8|~NAP@@AkgR=SSrD)~mcfU2dA!TAhob2=09W-vGHNMCF$rIxvD>v`+o0K_1m50;z
zjq8}M>eJIa$E9W7R%%u+{nzXK6{F{=IX9AkgRMHk$(Gg*kJD@FH$G1kTQl@+1=}67
z7w7}1GCY$wN1h5w#UnfsV`XB&UEySW2G70sqbbvM513jKMLcyNI#6;tQOP^<wW!hU
zHk#hcQ3DHtEPv)O?GykBIVgFiQ1xaCpdT!=-DFqwkH#M0;S=^@D?EYVy-Oj_)&PN_
zQR6T2+$SDBvdC}HGB6pKN(5{kUhp)cG`^?(ggLV3<Wd#5%Bc~R%9~v<YsNWn^YJGt
ztn+)~iAoih?e0Hss?DZ%gmm0HZm=YwH&a<R&dj=yQ9Z-&p3jsRM+GwKy3Kf{RlV}m
zQ!Aw|Pb0@|t?a>ktNO=)91)Aq5>Mm`yDr?tl7(PUdS)BoS6W@$LlC`o^8*RN6F!&B
ztGZ_3>jV&3<#bZ10Q|Ayx{0b@6jc{WfIr903PTizig&HFXchGU#*|iC_v`{Ca!l2@
z?fB*Lx_N2&%|W;pIaTAWl(J^=94v#+My8)IK8>n^&RHgceHQ6Y2d-8xiEDr`oC@tH
zN}M|GzT9P?CaH{nEqQO;xi4sY?2{NG6??`@0+WEt#@z`ZQmVW2$jHhG&^si=pAqpY
zo^wx%7{=kc`4=X1`SV0el*ZUbVZO(Sn!z|zIuX(=FcyTu2V*;&Br9etD0XNH&!&*z
ztxP1N&Ef?=8ad>n9zx-G45b<W8j5<P;h7^%Pqc`gIW+4nlu^UyuC^Rn;H=!`gjmPw
zrPbYz5wk>29E<@o4sl9!zKHBs5n9Tq5-9@4fdH-?=23H@@ZvQVJWo45;)L~e9_|9n
zA21IZ;N$~`m*?XB-4jcd{fO8~RH+;=b-yO8X385E`$V6abd?Gf6eB<P6!7&cEnKrx
zz4EKSLr`s1Yh|LIcyMFFWdzC@f1zE3AS=i;ZMqN}ccoTeJ*+PCl;;EU^#Ia56}<55
z6CkB&wc99Oh=E9J=Ar4dg2L_pypP}<K-}j+5^2+m^Tqm{F?FDHY^<3^^SrFWhzb#`
zUBN8U3ZzBc-?{StefBg=h~!yo<Rwuw5{@KODb4VM*&+y6km5~=48{|$3~SS53M_5O
zG@ngT%g$PqCWzO5&)ILh^;-_b>HamQx=gxJ$D1vVccByyjdIMiztV8_rWO1vKvq&Q
z-YljEGNq``%zE>iCyHZ?qR2+0F!f}@jR~@*?&pDbUP^lr5}bi^V~{Z8#F-v#lQ|JN
zPgNKJ-AGpmOt?J6bQ7!YX(tnCp?_|kp+;b;`^mF$PwD=yTm^L+=%I>$=A2N-9d(3!
zfASCAu`j<<sL_2Ewi0Oc;(rHx^<-@a^0a;p^7Nh09DSRRr$7FiLY`iWKl!mKKrlZ0
z_|;c{iQ*?~fA8Y!0a)vO0P8!zVOIlKe<BJ7=w-1dJ~I>yIE)S*+gZqK@#_F`A6y&&
za?P2wxvK!Id+mfW#5_q6b!{7jiTv&)AQ(mw4e3KbR>)p)hK>D%jf4AmLTL~WR)hSe
zk`SnMR{6>KZK+NNwQ#=spWfKDm-41CwZD-k@YTNY!6n-2NT|X?-nh16_vPMfAm}{*
zj|xj0@wtFmBgDU|&R=lH&B$0xN<_Urfoe?h8^;So(!LGyliFF2FvgiaOYB30=%w`2
zsRRICASYzbkryLkNYK&q6`FH57zNJ3pX<0y_O{2@$L?{72N5=>T4<MU_$@lajD!Vm
z`Ah@H2#iA1X*;4h35vzZKY`am&lvQR1jL)XJBfYL^JyaDm^>r)Urs!qfH2urC%x5R
zDz*A6BpL*g#Qi6$Od>I+vL2m$pNF5AcIr{V`L%mH34uM{kvN^0IqlS9GE=355#e)c
zrj<Q+aoEqNz)(pbScvD~i6Jhw!X@B64SIq@C+<|P3ww_@_1^JnBn<^eKbnTXABLN-
za`{_NajCNm)j}S4A$XxfWQ$w`phLvphNOoafC#&Dn8%1A4PAF~sh7t1HL`Ul5s@&c
zA?}_}@~39IW4Z<02mO_21zWh=X!6Ond87kdAfdWP8;JUOCzyxA(|lv&h;sZyGR5G;
zvLREY1bjZtmZ$<2ke_g&fl4s9V}K*6DaO(fxH>Cij{nVHc>@nxat;M&ImJz>lztgs
znGr#FC-O#Pyd{jmAUT~VN<6Y{ni(To&S>nVLG5MixSnl@iKb08G72eB8~CumbP!T_
zlQN5!EM60~XhgSro%7=_b`mq+^@HVR`_UMX>@3movODgDI3zvb2+V|YCq}TMo^yIZ
z2vV3Zzl~@1brT%(A)2(}(>d%SGT13pQP?<vJYW?G!8#R!8G7-_4^{2sjS1(w3lFUM
z?^}z=FT&MZ;^~>y=8U=WGZiK=#jXIg&Yq&A0uqY45<rohmlYf_fD<?LtS_(Q%_!+|
z{2nuOg{(Mp7olF8YhsX3bOm8UB#65m^PfJ^!BjvTvfxgGi%rL^S&@MB5;Q(|_eliN
zU|L`y9GfT7N8*uXB#zlC5mbsApb%{U*X!u0z3Oh<TL*QW@j7YO`}FT#M@3>ws;Url
zhlr9lxeVLEguW$_+p#rwymv=riF8r2jJl&dzD>J{PS}tn*GXV2vbe%LZfNYr?dJA}
ze+oKbBy<j?hI9=6g|HC4u*QHQxzs-mYg9X>(WcS36fpacCQxC7X~3&;Ejq+Wp_GPS
z9HA>TWBZ?c(|M3~b8>bC$Jj!e073&@R3W&Ga$qR~-GsvA>h&V@q9_$+->IYt*;N#M
z!~$tAjB1C4^7fSnFd<X{odHizCus-b&>z`!x})!s1*9AsB8*7U#OZDgB<ERdR4o>|
zQd3R*s}F|Hf~~2r(j>^6pKAhJA{|FCFL#tdJZJ|t+*La}BS@v_Xs9LIBxy0~|DeAT
z(Ex|I!Om&~<wOE3-xT;e&NS*N>gXTl@{2DVc=#_}2MiCP`3cHny^`2OZQ_lXEs!Bi
zoOGd46j&n$6F@*k9&n^QpuZWF%%K^t$wwEd1BKw=_7D9kIF`&I8w~EiYyS1S6Tv^s
z4tsgfsoEe52*?JK#4mQ+f3?9eO*sg8ypGHVRq0@-;*Gz${~y}Zc)p!V?V$UPuBUQ=
zL;9tv5CCY2?jf(hHJDJ52G7CP?b@>S<}`I7#W%SqNemWhqzUt`T>L|6ET#Dn!%veG
zyVLJf$JT+l;Y)|1V*~i$cD$qmf<efZ$WB0QSzAs)9*xK#SOYkn%A{}8VI(<156cf9
z_`ZzOAZ=MR(62~c(FXnLV!XlpXYf_Z3P)heNC(7^AN<p5af)ur8t9T{TLfuBF(<t8
z>pzJ79tW{=mP>%wJhhG69T))!qro;2F)xV{=+p>h7@ojGa-5DWm4YSnTk)+tm3J-b
zY{ttqo}6iz!nF`3JZ7&pS;T*jdjY14af?|0#6?)WD!jtNuVeq(Rc5qy%<7pV>sWH8
z(N2f=KhCi7nJ0g5SJx*vtc`&eJ{qLN1|5Q8$Y^bT2=xhR3AWGyoD{^wla`9(K2K<`
z0ZE-*IFn3IKEdpz=xd2k7Vp-j?!*TYTIU%vO)3k-yyi2NRSksgIG!qTI-D`4P)!Xf
zS7rY?!*4Um>X<*nWQeA5e)c;nI3O9Zgw|yL*kcqm|3bz_I;&Bq%S<YT@Agf0U2~rr
zOV+?U(={gm+aVWGbe?4Z3gbl>#<)^aG={OvF380ITXiByxvmW=)8Vl5w*7b9iM%|F
z#ZlKEEPXP*RC;0Qy-N;o$OZp#649e?m|cq83vrhkZ-!D`*I}BJ(>W18kY4cr9tcbL
z)UTXan$;uPNB}`7jyzThqpr(G$?RiVsM!#-;_q?}ePSb>b}mehq@-u7t&i>sW(r6A
z=u&CXGu7L?3na)tHU9ZethRt(R!cMMcRhIc<#c_XXPRC4Hy?IZObs}I{JX=51CQn7
zd5kW}En<r<3RN-WqDoBHP&OyvL}wo<FpmVq#;zzWU)zJetn49?4M1*6q<6#|bSNBg
zfD>r^%zBGJlf;;qp+JU9d_=7QE%C`m*T6@9K7ErCZy*A0spdhOD<v#9&um5`NT}&O
zWs{_HnWH9Y59R8)ae`8~!%wi0Qv1%@&Df6>VK5Ar9GL*sLV3{El^X6+;DEY9@P%aY
zxiTNBAokxT2<4}++%JCRy6_3}K$mGci#&;we3CKcl@eI2rWy6x(g87XY0UWQ%~{Rk
zg0MCi{)Rki8*~9~aGWEnoa90lfg239Sbul~bJksLRl6kI(3v+i<u)3%u-dw3eF7%l
zGZ{6KE5H05t{4ZTU_uN?z+&;|xLpl90$I>5Fbot&(}{Y`kjXoOkR1WmgG_*9k3mB2
z;b8RYo!Hn$OjogJl&M~W#Hb<eJpem^Le6+0T$`uOGoR7yEA`ZX{x$E}1=;WY%J+jL
zj6f3FVS`hSaxNQPwV29)Gc*<~2bgYT5tQI)aiunnV{}Mlm@&tsF@bF$F~|!Th&&7~
zP{3QssuX@U?9#*<X_~+$)bIM=2Wnc2vW4Cla)D$tp7Y!e6TFTr&>7ev0kuL(_Yj`i
zVsQmDlsYX-VhIbAs=~`LgKoqJJdJn3wYZ%e4t)`}239r$6@E&nNv9%65MqZ2jqtT6
zKl<inxB8)&@+g-9^J$`M_W~mAY>=usM~(uP&<?ep=|SLT%;^D*TAA3uD$OmWD?HW~
zxP+_I&QtN+Qkj;R;DT9)D`fmwOj9q?uYi^qw>-0p#++-49Pim$nb5FS3})21a?h<i
zOcYF9p)SqP6&K7d!l+Fm9Z8|YBLJ@;C<GpzS}!GOSo$g_BZPjMIPz*tv<ecnus{yr
z&lb@SVpBYlB9pSl7tY~<L*XSOp$Cp3!1-T)<n-ANrplf}_jT)mBF|Z}n@)rAS@}4%
z2nRe>F>Yw+76v(-PdX^jN*_jn<5QpEa_|;UfvrI{Tza2iZ#}xaQemc#=Y-9rO2OHC
z<yU|Idr#mIcJVzX@cc$^0*`=?YyuB31hZz={|9CP4W`}*u}~rD&RIbJLsN;4*{MV~
zwjVzBS`Ul)j%ES9vz?W)kIz09b8*f8$v6W*F245h<_-Xai)OA|dNeFb9f^7p#faG!
z;zx&n&^k%&G#@@VFNOAJn+h!SS7cv)Ya$p*fRJzB%!un~N)XpCfAX(6+yf)4Y9%Ru
z&G-6_Sm~<#_WUpZIcyrEz>I+}Fx=0BK8deLG6-)G5zH>*HAs|@8}2Ux`XhW!;)Uo;
zqGTwkB}vM(1BZLqf(19U39^HuCU6Jo8z(X#w?OiED-+Uz`rJ>vXeOd=cXGjd>y?>R
z#Fzm&{&c^AXb?sVkP49|b0vtybaEdb&!rxNMlqw;3j~WGHcXca_bmCvjtjj*uAm~K
zUcW{xcE4vcwQ90Pl0_*q-6%2)h;794q-{@rPz*|w&Lh(#bHssCC={5^qC*6ghAKIO
zQ@J-u`$MzpbDx~jAk2->5p|TqA`K1ncxj}I=#`S#-F8;Gq;AobfBW+)TbC)NQ@Qp8
znLNHJ<5DcTz*Hax(2_zx!VVxqe-x9Jm{SFjvz*OdfvVcRViyg~(Y^`qoBwsh&RbFG
zGN(2UwteD<-KfVl0eFIDco@2fvqWq*?LhJA1e?lKsZ?XUX$}^yzjL?50Ux5Ki&NCV
zH}RCO>Ou#AF9Ayc9!f)o7=6ZD$GeP^7m+u{MD0~LgGAB2>gf;zWc6`<Vh5H-y+6D}
z2e5+VOkqQ}B@*;969WpV8vbc8p{~ymK6yQJl$a^xldi5r<o1k9`)8wwo9mbh0nkAm
zjabbE_#)H}nLXAug_S0KI|Pq3p~HZ27-hcSzQoxPT%uRndLQ<?y4uNhJEuj%V6tdx
z@JmX5A;3y9P|R^;Pt<_*NCF=rzYsi}%9p-)9ZVF6hZ{h^^~7H~D%rLh(p_|Tq2J47
zWz>O>B;B-qw*G)rFiXney4PklgmE^Mrw{<@Bm}7DI5#0Rf(67MXh#CbZ}G{tUUM=y
z<|iF=l*3YSe)FDKhGg^&-6Z5VIGT=~?s7PkDt8Kq_Q#&+k%2>!%BwapiTMluS#bJk
zxC)9!YakwROW0kA08Fi5i8xRRqM<M%pMGwC^FvNoUwWGg8*G}#m}V_?g-8Hu`H%?C
zrKgin+DRFrIwU3G>0O5?X|DxD%G<5qwY%vw0!-&gA~_spJ+gacz%V@x5>eZz1=}zn
zDkbH-)L34G3|tk{nb3_b*QpXK@aZxObx_b%TegQQ1gHoxK=`;(6Jem8%31|Gk!5o{
zOxC1)m=jeObEWpOZGYvC?2F#R9z!|Y-(W_PeWyYGl5%Nn!oDbnMorUd?ZIU5j|nju
z&z(R2hms$=L9R^Dhh)hP=zU=XaWazAINiWSSfFHwfuSOc-BTZ?OSNtPufNtWd+^yW
z(bkFm;GS;55uM0GbO^xI8v2ibV~=PmJcaCHujsDh`Yuk~+jv7)dovcwL~=Altg{^y
zB#F_BE0E|!*Bjaeb4_Bf@>Vz~Nu*HIt(AfHl)z10zmZ>WD-^9&yEd_3#WRCSyH+CE
zx8cUc6v#Ur(R&E0?V~;Hw6xj&FCPdq{#bF*dI8joLF!Pftpnotej-gB;|9n_0%m7y
z0uWG<A2y$eP^{5Mh2kb_(Mn`$N{f}N3!agU6ZJt$7e>MbQfFhZZxSkqS$_C8c2SXS
zKX3ATs#_LZK1lUCv?K{O821p8z`%W6o5uB<WmAIZzF{U_Fg6`%qRA>#QEI{@1dZ3I
zv_lIb30G~JX()n4R5wE>f)L>3lb_zT)T0yp%3k_yg~5LIcIuE20b*CMiFt07;AW81
zNwShn*RWs#?ke}fKyv=o2SzXd*dMHvlu<+6PKlH}@iGXY-~>mDvvGvWVh|G#gY^3)
zGsf|U#(@Y5&iGTGaLNA3y&hC@1DalYxJzPpWMVEc<+IHqcLPQ1X6n~Sg^m_)Ovfjf
zW3s2tyn~UI3C37URX>_9jeAvZjJsG4G`a1vI9qh8=NVsFGtQAK|CVkmd1Szpe>l$@
zuQ0*|I5bH@AkvVO!<&G7Nu%%NawIs+ikVvqA2TV^OscYSGdD$%pd2B$Be%>FH;?Qe
zE7woUtj6od3TfIEEm+&HTuq>&kX#N8LmYT<A(b-vuJlr=s4_k3#%U^T-t$nLI0Snm
z<a$c~Z05%#L$V_>Fr=QU=>ez-(Gi?o!9MD&?H~Ufb0=)g9a}72Rd1Q^r}}thO;{-<
zw#QTora*rYDyA&dSRID(C+4siY6cV_tq+-tAPB_vhfoU5=C-7;n;8xA$ny5|ogB3r
zZKFslahBddD^>|fB)NfA$G|c0D4Kb|VDLoX=sukz6PmL*&U67g`vfrKX4}`0=@d{?
z-66_QLho2AtH03r%HBSWsZr#x?3J29Z?z$epaJ)dyaF`GQ@KIBn9rg?i^Rbf$cUo`
zI8PuG<N*>=tg#Hl^B@KKr+V#%<kc(R{Ff9=2UJmCoFHk&JOs$nJrg8=Bo??T`k-&z
zby9@0Fce~i?_Ej=LZG)m0&3;}5+%ffDlDI<P_5v_@vi55`@b*`hB-d;g*&Vc(=ifA
zxVH&(16><<I><u@%BTotb1D^*5-dKu>^zXLOn_EgB*@V!SP3)?xSXOlQuy0h+p`bJ
zmiW0Vd&VijFo@|+vEV?L#Mr@S&}QddKZ&7)z#TNFjyDYx<}{!?OjSUXfd<q7mhD-M
zu>R+o=oI-jApoJGKqDfadV+wF#NY1{EzTAZSrTqU7b+SZQ#K7bsIp_km-waD_ubDY
z)FsU)yde*_$3vTjOCB6ur_Qj8BCSEAPzz-y*tDb^+hGW$>9Iv0WWG}F--fT;mE!_$
zu!C6>95)~s5GBRr)i3}1zxchg@$Y>*%^;EP-%j&qNu>X0D1==6>bq&u-y3*XN$a1o
zA%Nd&D}U+U+!}=6>uebRr*5CF?q14H(3uiTMTLW{!_cI5+R#vH9Y#!aCQQU8fW{Md
z62p)>;Ic;uAOo;^f~PJ*k0VDyxWJ>Z(o4sBtH!D9j$DUCa<CmDhLOj2$VXV7qDU=(
zQAvjYj~Um|h=YFXWEnJDpf$}Miq@~~U;jq0q+ZMOL=3Z16LixSfU#hg4fW_RqsgwK
z6GC%5Nkp?X)`0m>D3>UO!5L@!9Tn<{yG5r*DI4$gYJ8oKhQnW-6{3cJw-p%3X>dc_
zXr&OA3(ZDYF1wwwTOKXk_Ubo&*h$Tv&0E^b-O|m~%FO1k)HhkO<&Gfnp6}kWT#i4R
zHl9tx%YNhRcyX(-=auH8bLr?)LG#k$GwDXDGGp#bS54=I?mKjDVe3)<`MIyOADynp
zwbG604JVz_bmcwqzVcG}pxHevH9EQYiKT_>ZaB6tH7|GF((G$KcR%hiA2dI<v~+ZH
za$jpZZ2&?}y<@$6_B<<_d@4BCWIj|Wt!=FDU;3jj|L=^al|J){W_lrsUX1TfXWu{t
zG<!34rfx}fP2kT4#Ty#4ZzOu7DK{k*_pMQL{@OF=98SEcw6(4xX>;58A3JZUv1yuq
zu4)w+Jmqga?xbU`3f%s~ue=Vc{*1dm_Ll3o62wezY?86z*4gnZ+b>bgrKl?d6|-Mr
zXZwrKp%t!*8ywQN>?Kv%S;w$8M3?kahZR2a3Q6(p#@@QS{RcnVksH#Qc2)zd-etvF
ze-SFYyLyXz^(hCC<LX2cHXl&i*hOzxS?6!Pnq5Ylc^$$`*ph5kL_4gC>I@bE>2GS8
z0(?t~EL~#~hj#e1n~Yf{ka0P`^kDxIK1pl_8@1bCeC9S?raf}3Y&5eo!oJ)|vGdYv
zC?Q)$1^ZR?+OvlhfX-<P;n&VBJ4GduUGO91+a10JlkAr0-I}oMcXmSm`|wi*u<2?x
z(NkG_f4k|2S&tZ#1Z*YovboT(ZT8#nXa6F7Y7pA~9vqfPz`9OCUgA3M|DoNX#dIXI
z`E9_coOI@ohcGgut@f%w>Iq$JqhH?sE5HDGa;iJornA^M@#;;*_0H>v$ec2`Z2PC5
zB&guF3ud3`eh*zsFFKsUe^%PyWE~uC91pXSvJ-e$|LK)j{G}hYWo6oGFB;H^)^P3X
zZCsa~#rxn3CmI#~{%^3@B#AbSOp`>HhgX+!%??iLa8h1M2)X$k>7ArDaJK*2N1>?B
z5@l7ft+`*6`quxhQ-)jCK;=opeSCvW&d2YB_4ZCm+S)&=lJx&4m1hrTC+H-r+HhY4
z4M}Oj#^rxfgI5w%QFYl?+f#jA*4fz(mC@hSXEx60cv)xko^{~fsbZIzZ_FTKjYAej
zRz$2btu+zhxEODZirBXFi|l`Pk|>IjOc#i<F(l%yrk&9N(1Rp#nf<`fm0!Mo@0;w}
zoBbYerf^VMP+nYX>rh+u<?0Q66AWxwX~7aspm=JgFHFZUu+$H>|MK;nVtpDhL7DaH
zP@3`*Tbwc=n;r>e$daO~tD#I+FEyZ}j7Ln<>Gq}2oLfdO|34pR9?mxskZQ&uN2i*P
z#5{7u6d1|7kXp>Zd5|?#xSpABrO~KKf}ndf_PZGbAZ@csz=VU?$u1NcQDiVPSOu;S
zYmV%Ro+(X}5>jr(4G*UqDUEpWW=%>BFaNg>5{1Eimgz<sBoiH*PIIZ!jm(H>bTmr`
zDevmdCZPg8$Q79p5V@kfQhj^iZA6tI9>*U=<d$6$MXj_hm8ML%qu@<|Kri)G%4tb<
zRV7rfgp_hATb}|n#0y;jUk+#K`1Sj~KP<kisR!Ab#N?#vPp>u9H>ir*ZLL?;V}DY7
zCe$`bg^7;Mf^~sXW$uA+-~V-jVjz>m+9eu7TG}fQlp|}FT5FqqO&xSahwQduq#;nk
zfoyh8!p)SGxZD5XC#9s&$}XO(;bD=i=NWZ%MiBdXO%0T(N^C8bE24C^u|IT~tt%^~
zqEov}HOKmVRK}k>xp!IqgCayoH2{**YJe&(5<jJK6whn}#;3tNzDp%c7;qsK63Tqv
zCPz2O=jnkgPltaF&`{m1upuL-e>$tAm!%>&Wit(_4Yo?8L}*iAJ^cT-cQr6}6;=4Y
zvcU4|?z)t15qfvo#6pFt5D7n#*QJ$;)waP{F<_}NF@az~6Ac*XedSda1qoUT3TX=k
z(*&eYA!-a1444o#U6eFP&{l#98t7dOKT7KQeP?Fw&wKa2JNLc2>|6HDzJ2%JnKNh3
zIrDSRnKLtwvY-J@i<qpS75@kma7f3}jc%f(KRkjFEG5K7${B!>&&reXv5a_@0<VHA
z&;`F)mHOH4(+>JJ*O_x_1-k@rC>b5^cx68s(oTmxEcO}#qD4J{J}oOj0cAKvGZ+-N
zKPGRGy6e27YBmeVkr&qM^XpEjQ0w#M%!?^P^5{yvQ{YkV6j=23rs%GP=Rg0S+rM-f
zwi^VS7M_kCx`87uaB>Iz<q8L$_nz9l9@QKPW_U$ohFZ#}uqj8t*w)d;(6b?DlLr-H
zg8#2o=9bqo+GtAf(8RLBali1oc{VEBdPRUu@4^G(^j8cGiSh8RgguKf3q5lX7CT(P
zcniAB0aqY-=w1F2p43+Ije;P8TAm|Z$+LU`CoE;&@-+?t2o)F>FfoV>{@;!Ta=Z#u
zw9X<IB{_W?UItuRRSZA|?>;<sz^1GO74K~MHKsoJdQky%;$4jbNFe^vfffac*Z>?t
z0t}#vFIFo5@Uka<7vc~^{<8BR+V!Fp&><EHi2?}HWpH;mAez8}s8;&FlLNxpsRbeM
zKvV!Eu}BB~F@iY)sQ_X<=n#C676@Gf+6Ko)p`B74a4uPZWaJ5mrNMxJ0^-5LC}?nl
zT4}9BOa+OW5z2zPLJuFzu#duU+;_tv8UtxZXdnR%A*GUW0R<`qj;y>o&TCs_NF=EN
zwJIg;o7yIDDg>aDoKqG<yv5p9$6x#x+!?kQ%hK5-<YK<SyW}>{3W!f0yMcn{6c(WN
zzIvDjtLUo}3bO`p03bKY_BC<9D`Hsvy(6mY@rFlyHAX2S2!jxkBaiY$39`ik!~>K_
zQEu>shOuu?sS2Gz_TlKkAk51<SD}ta0wK!cKjf%dlCD*Nqj@?0XWl>#{$xQsqehtA
z0?>GXh5u44F2rUi7;q*&eXy$dI-DvZ+4vHngavv5KYd%SEkTgjsschI<_wq;AQT>E
zODYnhmZ+9g`~WP~<dsf2-!vrE@g;>dz>ta%P#_fFUP*8P(5;|Nq2(gd@t-+S8fQv-
zM^@yk4f3kdLmJ=ZKquu3Mqu^7cD6EGWJIYjJIm4`S(=h4Pzseiqa6XKbTZV^KaR%l
zJ@I!O(5UcJJ3P2wL+K0JH`}9Bj84-KgBAL&Wk5w49tJJ?g4x(SNE(kEV3GUM`&<lR
zvaZa*h6<UHQnCfr<QN~^>4#Vuco6)+UI9kn#52Z0V3l#4*$_mZM}oieYOi}eR8o|o
zKE%eB9}Bh5NQAtplLA!8=N0Pvpwby7Qj*-O?mg1s;!(_wuNXaM{>ZbVBiiB;H*Gg&
z!{BIwLy)iAUh%uSi-x)uEW&aNSWYmR(K3*TV}M7X<PDE-jbkrtuI;@}&vtC{<rocT
z_u$CgAE8CIV5Q^I{|l2$FuNsx<2Rft6c-pmFi&WqIKV)S9+e;$2p%7BBPLFab7^@1
z0yAQ0K=RBIYUEVPAMP#rcYR+<;E#~ABnDb2NY<tSh7Ep1NHs;^5fTPosTa}pS%^ey
zN`Y$L?T5J_o<E>lTLPe&K^MWgk=(H_ZH<v$AY*a3WdJmJR|)<8&Yw%H7L>YI-{4(%
z!L=@+yMO|8Nzwsk*nLnUkg^n^Z{IT%J!&(k1!8e^9q6Gjp{0qP1A7y1bYU_WGJ#qU
zBijG^^=eqsq9<k)3~4L*=}7}#fF>~j9K@41f*5<1B{JS$wi~FqgA(LN?HZQAWeVU}
zJ4#t177j;kA<%}lE7p~=TVQcO<Qxmi#<W5?Y_t#%lji;KsA@$TUxpP$&!)UDNx316
zMj9kpg>+H7T<A=p;jD8pt(3|4`eUdHc#NSam&IcpH{T*8Cl*0REUH<1Z<Q~VK2!F3
zblW~G`T&3a7dJ*co}X&=0Ks-}R$eGa8Ma7Cg2(d@7~{gXh;$x3s`4#@>eC-K#KfRA
zS@gI_=h?L?@-vaB2)+4C)Yur7GTLQ!*#G{nQ8X8-P%;M=<X}H%aFfaN_yW?2((}9$
zAwP`1<_?y6cU*IjyrO{x%MS%n{L7$^$I4VM+8I*4uv`~Y06@Ow#~fz()`$kSNWc;X
z(RF&pAYqYN2kLlyCnMrgbY#3kez23wD-qP?HrX0nQ8mQo;h*N!fOFkS3bUS)1~?Lu
zh!ep-@yuX`woZFa$d(vI!BDy2P%+@F`=>%3Wp)uDl4{AI^B^%WiU!NJ=<*3Kb$rPa
zp%$KF3|Btc2g<E3O#D?Li;`Fe6pwI06Zs^SC9Kr|xr$}odHlC8L24Xfxr?ncjwk*E
zY*M@M-=RV%LR=V$Tj!UbAaG*@gop$XB~Q|1RdW%U3XucOu1gMbp&trKaZ)2V>TX#z
zs0_wK6Ldf@DU`N|%f36nrEH|f%pv1#0=fw_)=C9PfeRnV6Pz=6tbDh$aP8rSb*05h
zV&gB(JLen(qtMFPBlrvkDPYIHO*EHWGL4q05u2!W7aj^!^re}YJXgiAr`QIq1J3G?
zA8aN?DtRy|Tgc>4k|f?sCtOYi0GG034Md|WYuAIgJP{a;ErC`FE<2<@@8Y1L+Y1u>
zDLnY5Q6%FedbqIfAAgbyDyve{Ra@3oy$+&o5yTe4l}3^Laqfvj3FciY)ZPB~GOT$R
z-ZYLNlB#WEm8m>5DF#6a@)2kl5j9IkdldpuuHS#Rr|lsuZqo*sX1(Es+K>5g9IXFv
zPJQoZ4}n=;#m2JH68Em&9C)EpO`gX7C!9<V#}(`-sNATFxfNv&4Pei#F_-3Zj|a~}
z=v(*55iDKV5OhP?1+8j}PA?k0R`6wT7fzu;`{(}|@5w4&ZIoMr4Utk7eIfKTh_8gR
zF3_cElz<<%gzDGs4*#|Lo%I?sFA;4&1+j_dC`yF^2!(EW3sX~PvtmK`cbq?+C)6tg
z3s$kooq2^}0gU((KA^Y(o%nZH-O3K~7oMun*b}Xg(Mr&$IR`;epaAfpigU)!ngxOL
zy$ph@yxIgo!+{X;C51{n%!x?GfAuSvJi<|4wFZw;0RR!0G|BeC6IF;-)CIA6VVckz
zh4RGb@&t?6`|_bAmwqW@xkMaD79}7vJw>2VBN!$l+9Dco_CIi#_>NS1wNmS%$|^zp
zLulG-Dv*-L&diOgv~m<1DhX>QzB?<yb#$ll`dkp4O`dwRQyaRD;)hJ-b7BRqqb~%m
zqia{<6_!&A0(^4V@k#rRnT)~2mS;K3k3DRZk7ykDSO%p;3NYH1YJe(hpYzT#rAh#s
zZC{L+>WPM`;=Gc-7%PXAW}+8d#i0|Q`1aSqE#W43a-4JTjQsSg0ZO>`)Y*kZ0&dml
zpmU6^4wiK#;7E;fOTo{7Mqu_`Zdb3hq|r{+Xd;Y`oqMFS7}2PQd_f^YcQ;5S`@A=!
z26aA+gpOgGxLTYi%_*Ef1~&0dFu`BGQZ^NvXRE7Z=O7$w9emvN+Zf}FvIsyGV^L@E
zZ`>Q(9B6?F+_4HoRYgO_2NewMOlK{ZF4<{=B?^NVzYE<CSP)CSj~#?Vx&azHC%83H
zSyxX`pdu(lg)bt3<DSmSpOo%V+c7~^4xjvuCzwdvt7I1bFr08i33&y+)8WKvCQ$2O
zP=YiV&V5Di=Q9yDS5#-nASetO@85e(j#c}rEN~}o#Q;l)+qvOm^6s%AO2fb;q5Xl4
zAFxDlkItt4Xp@TZtN{CWpItXfW)-818JHThIM{CRktKHl>CU_l&5~DA7OF_P2UWy;
zWNg6jpgtO?XMD{&d>_$Li!5Gi!rtiPdba^(ZlDj~(<8g{yeD};59YliILF_4JVK<^
zE$Bnfhbe&%#3M>BuR8euzTDi}Ud01|ded|Nx@Ay#R>A)OmonrFAdV~J3=$9>8AkiB
zeD=_M=$ILO3ktL1RI_i;qsPAbLSBrZiN=l^Hg*4xAiQ}`UW6b`d$fp#%}vM^-UXMx
z?aQ1=U_=w@JoR=I!L9jx_i}HR{Bluf5zM>raB5Vjz)aHvV6~uhyug0K7wsoOA^wVp
zpXQ7Mm$KtESpc?haM7S<K-mg$4$9*n9F4d`cnV5Wzo*oq69VPR(k@)%zk~!k#QK+z
z3PF<K4zb?=CT*_aSO4zE%-WoWa7?TO5c7k(_>I5hY!8hy7K~C7i>!TMS3#dZ;3O93
zOE~W1v1feyWfI@`%aG<pUN&fG640X2X-rtX+bqg4F_D*S5Eb48tSXfY31y6GA%V{F
zGpz*}VokZL|K<7=K$~c_ugC^68>TtJSOZ4%=E}16J#}Puk(Ln6Q|9SLVXiFDUw)Tm
zxfWnkUjZpZb_h!mOltHDk{G)~6S_&LgCy$)<14?JD&5=(GpIUp%O*KPM`FoxNssMF
zEL}FqDKkc5c}?MDaY2(TE!;fSnotUDGo~(6_|F|(9^Z6p?o6o}iWGnU+Br>3KBkej
z_u<1i0Z>TjdG<kW#iOezvUEA!j~|&fYa+||o39i?wIC_7f@s2YhLl`&1Cg~bkCvgU
z`p3v=pp&BrPb%{M<)^&oc4!vjW)F90F5jNpbCTLJn;%)}b*&Bl-tBdhXSFca&%LjG
z#~L;OOrna3{?ls$n3ivf9ywbk$ROwtW+Y*IZD)zOwe!%nOx3}iac5mr(-G|~v8I`-
z&Dh+OY%Lc342cz`8(}rw!>z4QiP8uzi)&;4@%Kk@w{{Pa6{ey)2j&*z6Svac*WO~c
z^2$a&MYqD@Dto33D7Eh8v_-I}&77dC@f(E5l|0kj>ijj3>(fssVIJIH{YuBZy`~cV
zvDN0!H_aXf+In2gCf^cbO0<e{#MPcg=R<GgUgeX93a4wYOiha?48|Xmp8S(fONwqT
zZc4;&Luxw{R@m#b-+$>D8)4YNw6n<UIIw`S?@AWPAhE&}^z!(Nxz{eHli1dj6{DeZ
zzeDfD1Mki(`UWapee15D0Xq838B``!kDk8B6E>?IH$_JjwlV=;$hNs)v)bg$q8B}p
z;uSXY*VH6>+WV+D%>qZDul-})D%P}eGvkZa1~Ln@1;`{!&Vskl_NBlDyKKwNhAXZv
z;athGYsjUIu_a{RvTZ6Xu55|*kInA1*laOHA>P$S7A-jIz9_<YoPcx1PqK=$PcMov
z*+qQCllBEShAfwQe>VGFn?>(+$KN`$F+q7!i;^kJ%pB@+5H@25lrq$rX}A<+QrEcv
zd1n?qYZg66XUYK0KL!k^W1P6BI3H~9+GBF9pKYK<m2n#GgQusHZJz>62oIfKm>E*&
zxas7t%yib97|{9BuRWbY7qEYId+M%Dh^&Fm?r(cNU7&eWP??>H^n5~_;`X0TY+DjW
zRoLHT>v>COE=U2Fg}Dp3o~M|3bdc9sj4pM=A-%8)y7H$p!|0#BI(jRoIb^Konb>f2
zXBK_-^JhJR9}PO;rv1sY=!JE)qSrPSH;X>DLlolR4baL>6AEWyaiXJ-&CX>!BqB1A
zMG+?W3f2UaL1HLv<+|_U_VxYBY+@_S1$h_#_kF>At2gc3E?VU+%wKSW4H36`*C8yg
z1lw6+P_sIFMT@n?@-~lD_;w!XrmuQFsg!r7(A#+mJ+-I3r>29`xy<t-N|{g&k*~dN
zR`}53U7nGyfx|&j;lF-si{wPI=Mh;XTjFgVE)x+%BRhmerD1d5k(iB?qA(qaMWtbL
zU$n%yI^1jZ?Br>`Pt->8RxmSW1fIUD#3z;V&g6O4<hfNhvH_YgUCl-qRxs@;G0p*h
z>ozL}GJ&{+<Dpf7|FZQ-^mWe_xA1AQ#4juAGey$~V8;uA$QprJrIE{`9Aurd7Og}c
z11efUj3ICGL0ah8p7!lZg)~^<(qFc!I4>;sGIbPmF6DEJTA10{B-;AI^vOQSWzsbC
z^7wPV?@XY-YZK@^UN=w2&6p9MIO&K&7Y;W0GON#)SFszeM-j&O+wKh?TD>by8Niy-
z9r@PnH>5qU$QmLmj>}@VJ2kNeJ)O^Xl~}oSMaLVGUTsM!?OK(^IVow=`<n{ejOi5C
zlSD^fJEyocgxt*phks{@OULR@>go;RFbbgIw62XO9;i6!J2|O|C6)|lQcFiLmd7{G
z@95}RI(i<px<MO6Ql1|ZY>Wx1XwzO%mb%lXC%JTV#LQ+;2k_q4c*t_Q+95OM*oC@w
z*K|a?R%LttVo}rLuFY8Fc+oTdxhFfb=rTGLrZseC(OcKsCwmrs^3Fr=-+$w*&O(>0
zg)W8o6ge;!e!%W~V-~&koe_I(*Y|hfIwGeK9GAatuESz;lX~sxN>1_*Tofj_Ev~)y
zmtW=d6lDtfkH4rW>%)|T4ryGNbX*rj?xVL`Hmjc#t41T6xOXXa|Dx-nS!IGT8j<VX
zzu~4_@F8#lul{{|!gQRK5w?+Nbkcn}p@p3L*5n-Y<7GCq^cJmJgMZ+JBqo}Rn+^j<
z_OiBgktwN+{e5!Q;$)8+3GGx@RG(b^J5Ft`;*xT)G6$J(Qr8gPqtepkoJeVOAXXZB
zFp^XN>@LEfHH3!cnm*ulIepHk+l5HCdt^R35>ggEb#%pXHtZa!4*hDNZ$tNrq5e5T
zz`p{Xk8*$4Rus3S>w@ag`oYqQ#Y;z=xh2FZ63YYK!-EbpE$Q-x?&)1I>MR{Oc^0B2
z{emuUu(Wk_>B#({xup%G^GAp89dc$5EIqy7+1l%@SiE(~<}FUe8N$F{SuyIB6jFR^
zUPd@AyA%$IAVF>x;kyFP<X3ybBt$voZj|Wwb53!FnJ`QqmDtpf0bU#ryb*;If-BGr
zLj^|m`6vk@(t)MBqg{yfx|h02!2W{GCb{+Nbm*Tgb6KSMTe!y2GIs_+ZB>q%1e<HQ
N6o>MEGiRc(@P8dxr`7-f

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qpf
deleted file mode 100644
index 38d5967a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 21:51:58  January 08, 2018
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "21:51:58  January 08, 2018"
-
-# Revisions
-
-PROJECT_REVISION = "TripleDrawPoker"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qsf
deleted file mode 100644
index 5c521181..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.qsf	
+++ /dev/null
@@ -1,184 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 18:15:04  March 11, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		TripleDrawPoker_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/TripleDrawPoker_MiST.sv
-set_global_assignment -name VHDL_FILE rtl/tripledrawpoker.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/sprom.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY TripleDrawPoker_MiST
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ----------------------------------
-# start ENTITY(TripleDrawPoker_MiST)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(TripleDrawPoker_MiST)
-# --------------------------------
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.srf
deleted file mode 100644
index 14cddd5e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/TripleDrawPoker.srf	
+++ /dev/null
@@ -1,54 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.bin b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.bin
deleted file mode 100644
index cb5d4b67eb286c6fcbabe95af88222cf88558211..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 32
lcmX@W{-1$?{r>?5d-eki;`Rp^jsvj;5Zj9%U||1o006pW3wr<n

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.hex b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.hex
deleted file mode 100644
index a53b54df..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/col.hex	
+++ /dev/null
@@ -1,3 +0,0 @@
-:10000000C007FF000007FFC0003F07C000173FC048
-:1000100000C73FC000383FC0003F17C00007F8C00E
-:00000001FF
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.bin b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.bin
deleted file mode 100644
index df3101123398452fb2dfeb46b02c0df5a223964b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2048
zcmeHIy^7mF5FTUjHpXgo;CP#R2n7TScQ0Z{q0W&=5gli|HdnYyT0f5OQmDKKa3ctK
z%Tqc*gf`!<<g+a+*a=ChY_po5Z~ip1LsXqkmpNQWt)<`&>vpodD2hBw)B0mQuk^Z|
z8ep&ax}rK=qH!2cCqZ@3B++mLLri}B5QSk#%S35C^AEv4`F6cH3?ric0PsYoX<3$O
zs$oh>#+o3=x7)2!kOx7a6b&4l!2o*mb(+PK31E{6`6I1$6WmI>Z}09R_=kRy82<{#
zd?v~A6ac?aJT#3e-Wz;T>X#&8OsT}-7XSRIe`3Ix|C;5;p^f7i5$BvCY0hlLmnfg)
zC-4@=sP^w$|4|g(OEDru|Dwyw>W}mh|8$3s(GoSjXz|xz2_X=>Fy$jEweUPo0FOGM
zP-R28h3pS~Ks-o*V9ZB58ZA@h)4$(>Cm|&o$oSR{Q^+3a`<{Bf$UE8>{qhd|+=at0
zX~y2qrg1o??{+NO{2lYgQz--1>w&w@3c-6l7DzcAb5UgLW7WSx?dI5ae~uok=eab)
zj3Iuwy>{K}o5kYB+_w*pPlxo=W5uuKM2kfg<?B5sviSD*;9N@k_u}{P|IU6hz9wBo
zvd`ySWbOEKs9%*g<Jr@k<AHzUQl7i6n`h>Exw^V?4P&)h;pW_RhYqs}UY4T!|DQiv
z0kzp|V9@TX^cx;C>?`*9)kR~ESxqBU%B&EBs}{v>q3rgeW9>M*Jq5eg<fWbS1CxWY
AMF0Q*

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.hex b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.hex
deleted file mode 100644
index 98be5089..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/h.hex	
+++ /dev/null
@@ -1,129 +0,0 @@
-:1000000000000000000000000103070F1F3F7FFFFA
-:10001000FF7F3F1F0F070301F0F8FCFCFCF8F0E046
-:10002000E0F0F8FCFCFCF8F0C080000000000000EC
-:10003000030100000000000000000000000080C07C
-:10004000000000000000010300006070787C6E6713
-:1000500000006070787C7E7F00001C1E1F0F070769
-:100060007F7773717070700087C7E7FFFF7E3C0079
-:100070000000000000000000000000000000000080
-:100080000000000000000000000000000000000070
-:10009000000018387870707100000C0E0F0707C749
-:1000A000FFE0E0FEFEFEE0E0FF07077F7F7F07073F
-:1000B0000000000000000000000000000000000040
-:1000C000FFE0E0E6E6E6E7E7FF0707676767E7E7E1
-:1000D000000E0F0F0F0F0E0E00000080C0E0F07832
-:1000E0006E6E7F7F7F6E6E003C1EFFFFFF00000084
-:1000F0000000000000000000000000000000000000
-:1001000000000000000000000000000000000000EF
-:1001100000001839797971710000FFFFFFC7C7C768
-:10012000FFE0E0E7E7E7E7FFC7C7C7C7C78700000B
-:1001300000000000000000000000000000000000BF
-:10014000FF0707FFFFFFFFFF0000000000000000A7
-:1001500000001F3F7F7B71710000FCFEFFEFC7C7EF
-:100160000707E7E7C70F1FFFC7C7C7C7CF8E0C003A
-:10017000000000000000000000000000000000007F
-:10018000E0E0E7E7E3F0F8FF000000000000000017
-:10019000000000000060787E00001F1F1F07070797
-:1001A0007F1F07010000000087E7FFFF7F1F00009F
-:1001B000000000000000000000000000000000003F
-:1001C000000000000000000000000000000000002F
-:1001D00000001E3F7F7B717100003CFEFFEFC7C730
-:1001E0007171717B7F3F1E00C7C7C7EFFFFE3C00E8
-:1001F00000000000000000000000000000000000FF
-:1002000000000000000000000000000000000000EE
-:10021000000018387971717100007CFEFFEFC7C7CC
-:10022000717171787F3F1F00C7C7C7EFFFFEFC00E9
-:1002300000000000000000000000000000000000BE
-:1002400000000000000000000000000000000000AE
-:10025000003F3F3F00001F3F00FFFFFF0000FEFF89
-:100260003F3838383F3F1F00FF070707FFFFFE00FA
-:10027000000000000000000000000000000000007E
-:10028000000000000000000000000000000000006E
-:10029000000C1C3C383838380000000707070707F7
-:1002A0003C3F1F0F0000000007FFFFFF0707000093
-:1002B000000000000000000000000000000000003E
-:1002C000000000000000000000000000000000002E
-:1002D00000003F7F7F7870700000FEFFFF0F07E790
-:1002E000717B7F7F3F1E3C38E7CFFFFFFE000000A1
-:1002F00000000000000000000000000000000000FE
-:1003000000000000000000000000000000000000ED
-:1003100000607F7F7F6301030003FFFFFFC3E0F006
-:10032000076F7E7C78706000FB3F1F0F07030000A3
-:1003300000000000000000000000000000000000BD
-:1003400000000000000000000000000000000000AD
-:10035000607C7F7F67070606000000C0F0FC3F1F3F
-:10036000060607677F7F7C601F3FFCF0C00000002F
-:10037000000000000000000000000000000000007D
-:10038000000000000000000000000000000000006D
-:10039000000000000000000000000000000000005D
-:1003A000000000000000000000000000000000004D
-:1003B000000000000000000000000000000000003D
-:1003C000000000000000000000000000000000002D
-:1003D0000103070F1F3F7FFF0080C0E0F0F8FCFE25
-:1003E000FF7F3F1F0F070301FEFCF8F0E0C0800015
-:1003F00083432418182442818142241818244383FB
-:10040000C1C2241818244281814224181824C2C170
-:100410008142241818244281814224181800008146
-:1004200081000000000000818100000000000081C8
-:100430008000001818244281C080000000000000E5
-:1004400003010000000000000000000000000000A8
-:10045000000000000000000000000000000000009C
-:10046000000000000000000000000000000080C04C
-:100470000000000000000103C08000000000000038
-:100480000301000000000000000000000000000068
-:10049000000000000000000000000000000000005C
-:1004A000000000000000000000000000000000004C
-:1004B000000000000000000000000000000000003C
-:1004C000000000000000000000000000000080C0EC
-:1004D0000000000000000103C080000000000000D8
-:1004E0000301000000000000000000000000000008
-:1004F00000000000000000000000000000000000FC
-:1005000000000000000000000000000000000000EB
-:100510000000000000000000C0800000000000009B
-:100520000301000000000000C08000000000000087
-:10053000030100000000000000000000000080C077
-:1005400000000000000001030000000000000000A7
-:10055000000000000000000000000000000000009B
-:100560000000000000000000C0800000000000004B
-:100570000301000000000000000000000000000077
-:10058000000000000000000000000000000000006B
-:10059000000000000000000000000000000000005B
-:1005A000000000000000000000000000000000004B
-:1005B000000000000000000000000000000000003B
-:1005C000000000000000000000000000000080C0EB
-:1005D000000000000000010300000000000080C0D7
-:1005E00000000000000001031F1F03070F1D18007B
-:1005F000F8F8181818F8F000001F1F191919181822
-:1006000000F8F89898981818001F1F18181C0F0762
-:1006100000F8F8181838F0E0FFFFFFFFFFFFFFFFBA
-:10062000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDA
-:10063000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCA
-:10064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA
-:10065000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAA
-:10066000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A
-:10067000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8A
-:10068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A
-:10069000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6A
-:1006A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A
-:1006B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4A
-:1006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A
-:1006D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2A
-:1006E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A
-:1006F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0A
-:10070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9
-:10071000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9
-:10072000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9
-:10073000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC9
-:10074000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9
-:10075000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA9
-:10076000FFFFFFFFFFFFFFFFFFFFE7DBDBDBFFFF1D
-:10077000FFE0E0E6E6E6E0F1FF0707676767078F5F
-:10078000FFFFFFFFFFFFFFFFFFE0E0E6E6E6E7E732
-:10079000FF0707676767E7E7FFFFFFE0E0FFFFFF8F
-:1007A000FFE7E70707E7E7FFFFE0E0E7E7E3F0F849
-:1007B000FF0707E7E7C70F1FFFE0E0FEFEFEE0E0F0
-:1007C000FF0F07676767070FFFE0E0E7E7E7E7FF6F
-:1007D000FF0707FFFFFFFFFF000000000000000011
-:1007E0000000000000000000000000000000000009
-:1007F00000000000000000000000000000000000F9
-:00000001FF
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/k.bin b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/k.bin
deleted file mode 100644
index d462deb714b6a12735dbf9fce107166b2bb6ef06..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2048
zcmah~J&WU36qQgwU9_bJ0{RP6st6eN2kiDK!c;bFm2|@twuCpU9g?-;B4CpYVhLNM
za1p{3AqZ;_M1)~6%T$Y5@*F2t6|fN@Phk7z+-J>X>|%AnetJ6hocp2oLA0~&S}sN6
zX_}XarCe_<(=ZIva-8a+a(mAZg+aGJAmY*Yh~_g0N$>ery)X>v)U`FuPr<Ll^DGF%
z9#OFZ-Ay7#*LBA+O6hr?ltlZu<~T=3N4Bj=IT#FVn^sHMYK1_ZhGPZ&K4|?ur87;_
zIQu%B@?W1l>mfe;UDt)a4dX}GJ!OFdTuL}9*9u1$pEBRjwFj;%rER;*nZfkq&kOMP
zahCtc3X=bExI}>uKOrRgC*+o+o}zu8;3wF7@mUo=Rq=bh-cv7`5%eEuI`_X0&oh*d
z{JXdO0866c8{pUANs@4l+&&^*OR_9Wz{mGNqjaJ=yqKq;WC#R?lqr@Yo{786U!Ur5
zN<0q>h+}I@X`_0SpJw*4iVlGqJi>bUZo8&60)FgR@@u~vgb{t9wgu=lc+~a0fh<dS
zHY_6%Whn=q*NsGCSPiDv;Mjyoa^h-g^_o~i?g?IqrOunN(IM<oadNEi#^ZqT;}e06
zrW?WI2JqW`e8;c$^DVy>Pn*qY+-&Z~)?$CYsNO4FYoDDxJo}{Ge$;&Or1_}*X}kRp
ze;V_#Jh$7e5M-L2PRBH9De^qWx3Wx(rUe{hPQXz$ujV|TFD0gVo>>m<{O85aKbzd?
zS!S!%QhZuVrSCLYMCtGOFBS^~FxemDK|GqzfvbFgL!VRNM35X(s12v|?k6k+>#cV2
zOsubcJ>|~@SM?sITNV5#?F!~jsSYADRWXv|{I;mvG((ikQ^a&a2%<(68#SUgA;;iQ
zoD!GBE#OwLaVyw_SeL6gr_*r4jD2yy|G{%G5k!#>`**+IbQs6+kPnPs{4xH&Js*um
zFMpzU7nhfp{%<tNZr;B0f2TL!VE)B~(*ADT#22ssT9tI|v)?rpFTp!cDS-Rin}GN=
zzu)Ok$wwHDqu$3c`TxK+8-<U4_>%m8*>E0G?8o?@MC0)|x*|WC<Tpe3V+td`$R~N>
zlV9Q?@+*Dl{tcTIJRiLtey`>)P{*`?`D%1NrOjsJ<40E!RG_=cqH&b1FrPr@isIq5
ziUZj&FG`9pUcCD8XU;^Khhu^br_Fuys>$8!G;YJ<6!#hKE9XPpXSlEAXSX_s_Zaw&
rgUeX6ZCoKo26%i?nBeh+B7mxU5oa9hEO+<RAi*ICs%}*AYlr^;emnM0

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/k.hex b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/k.hex
deleted file mode 100644
index d907b9db..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/k.hex	
+++ /dev/null
@@ -1,129 +0,0 @@
-:10000000FFFFFFFFFFFFFFFFFEFCF8F0E0C08000F6
-:100010000080C0E0F0F8FCFE0F07030303070F1F8A
-:100020001F0F07030303070FFFFFFFFFFFFFFFFF84
-:10003000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD0
-:10004000FFFFFFFFFFFFFFFFFFFF9F8F8783919859
-:10005000FFFF9F8F87838180FFFFE3E1E0F0F8F8E7
-:1000600080888C8E8F8F8FFF783818000081C3FFB7
-:10007000FFFF9F8F87838180FFFFE3E1E0F0F8F8C7
-:1000800080888C8E8F8F8FFF783818000081C3FF97
-:10009000FFFFE7C7878F8F8EFFFFF3F1F0F8F83887
-:1000A000C09F1F0101011F1F03F9F8808080F8F82D
-:1000B000FFFFE7C7878F8F8EFFFFF3F1F0F8F83867
-:1000C000001F1F191919181800F8F898989818188F
-:1000D000FFF1F0F0F0F0F1F1FFFFFF7F3F1F0F871E
-:1000E00091918080809191FFC3E1000000FFFFFFAC
-:1000F000FFF1F0F0F0F0F1F1FFFFFF7F3F1F0F87FE
-:1001000091918080809191FFC3E1000000FFFFFF8B
-:10011000FFFFE7C686868E8EFFFF00000038383866
-:10012000001F1F1818181800383838383878FFFFA3
-:10013000FFFFE7C686868E8EFFFF00000038383846
-:1001400000F8F80000000000383838383878FFFF31
-:10015000FFFFE0C080848E8EFFFF0301001038385F
-:10016000F8F8181838F0E103383838383071F3FFF0
-:10017000FFFFE0C080848E8EFFFF0301001038383F
-:100180001F1F18181C0F87C0383838383071F3FF1C
-:10019000FFFFFFFFFF9F8781FFFFE0E0E0F8F8F837
-:1001A00080E0F8FEFFFFFFFF7818000080E0FFFF0F
-:1001B000FFFFFFFFFF9F8781FFFFE0E0E0F8F8F817
-:1001C00080E0F8FEFFFFFFFF7818000080E0FFFFEF
-:1001D000FFFFE1C080848E8EFFFFC301001038381E
-:1001E0008E8E8E8480C0E1FF383838100001C3FF46
-:1001F000FFFFE1C080848E8EFFFFC30100103838FE
-:100200008E8E8E8480C0E1FF383838100001C3FF25
-:10021000FFFFE7C7868E8E8EFFFF83010010383800
-:100220008E8E8E8780C0E0FF38383810000103FFC3
-:10023000FFFFE7C7868E8E8EFFFF830100103838E0
-:100240008E8E8E8780C0E0FF38383810000103FFA3
-:10025000FFC0C0C0FFFFE0C0FF000000FFFF0100C3
-:10026000C0C7C7C7C0C0E0FF00F8F8F8000001FF32
-:10027000FFC0C0C0FFFFE0C0FF000000FFFF0100A3
-:10028000C0C7C7C7C0C0E0FF00F8F8F8000001FF12
-:10029000FFF3E3C3C7C7C7C7FFFFFFF8F8F8F8F8D5
-:1002A000C3C0E0F0FFFFFFFFF8000000F8F8FFFF19
-:1002B000FFF3E3C3C7C7C7C7FFFFFFF8F8F8F8F8B5
-:1002C000C3C0E0F0FFFFFFFFF8000000F8F8FFFFF9
-:1002D000FFFFC08080878F8FFFFF010000F0F818BC
-:1002E0008E848080C0E1C3C71830000001FFFFFF8B
-:1002F000FFFFC08080878F8FFFFF010000F0F8189C
-:100300008E848080C0E1C3C71830000001FFFFFF6A
-:10031000FF9F8080809CFEFCFFFC0000003C1F0FC4
-:10032000F8908183878F9FFF04C0E0F0F8FCFFFF07
-:10033000FF9F8080809CFEFCFFFC0000003C1F0FA4
-:10034000F8908183878F9FFF04C0E0F0F8FCFFFFE7
-:100350009F83808098F8F9F9FFFFFF3F0F03C0E00B
-:10036000F9F9F8988080839FE0C0030F3FFFFFFFFB
-:100370009F83808098F8F9F9FFFFFF3F0F03C0E0EB
-:10038000F9F9F8988080839FE0C0030F3FFFFFFFDB
-:10039000F0E0C0C0C0603800FF7F3F1F0F070301BF
-:1003A000003860C0C0C0E0F00103070F1F3F7FFFAF
-:1003B000F8F0E0E060303800FF7F3F3F4F870301F7
-:1003C00000383060E0E0F0F80103874F3F3F7FFFE7
-:1003D000FEFCF8F0E0C08000FF7F3F1F0F07030125
-:1003E0000080C0E0F0F8FCFE0103070F1F3F7FFF15
-:1003F00067BDDB6666DBBD6666BDDB6666DBBD676B
-:10040000E6BDDB6666DBBD6666BDDB6666DBBDE65C
-:1004100066BDDB6666DBBD6666BDDB66007E7A7A3E
-:10042000427A5A7E7E4E666A6A664E7E5E7E7E4264
-:100430007E5E7E0066DBBD66FFE0E0FEFEFEE0E085
-:10044000FF07077F7F7F0707FFF0E0E7E7E7E0F0C0
-:10045000FF0F07E7E7E7070FFFE0E0E7E7E7E7FF62
-:10046000FF0707FFFFFFFFFFE0E0E7E7E3F0F8FF2C
-:100470000707E7E7C70F1FFFFFF0E0E7E7E7E3F352
-:10048000FF0F07E7E7E7C7CFFFE0E0FEFEFEE0E093
-:10049000FF0F07676767070FFFE0E0FFFCF8E0E08A
-:1004A000FF07071F3FFF0707FFF0E0E7E7E7E3F37A
-:1004B000FF0F07E7E7E7C7CFFFE0E0E6E6E6E7E79D
-:1004C000FF0707676767E7E7FFE0E0E7E7E7E7FFC2
-:1004D000FF0707FFFFFFFFFFFFE3E3E6E6E6E0F0CD
-:1004E000FF0F07676767C7CFFFFFFFE0E0FFFFFF72
-:1004F000FFE7E70707E7E7FFE0E0FEFEFEE0E0FFDB
-:100500000F07676767070FFFE0E0FFFCF8E0E0FF19
-:1005100007071F3FFF0707FFFFE0E0E7E7E3F0F80B
-:10052000FF0707E7E7C70F1FFFE0E0E6E6E6E0F1B9
-:10053000FF0707676767078FFFFFFFE0E0FFFFFF29
-:10054000FFE7E70707E7E7FFFFE0E0E7E7E7E7E7C1
-:10055000FF0707FFFFFFFFFFF0E0E7E7E7E3F3FF39
-:100560000F07E7E7E7C7CFFFFFFFF0E0E7E7E7E4C4
-:10057000FFFF0F07E7E7E7E7E0F0FFE0E0FEFEFE42
-:10058000C7CFFF0F07676767E0E0FFE0E0FFFFFE10
-:10059000070FFF07078F1F3FFFFFE0E0FFE0E0E6E8
-:1005A0001F8F0707FF070767E6E6E0F1FFE0E0E7D8
-:1005B0006767078FFF0707FFE7E7E7FFE0E0E6E68B
-:1005C000FFFFFFFF07076767E6E7E7FFFFFFFFFFA4
-:1005D00067E7E7FFFFFFFFFFE0E0FCF9F1E3E7FF7C
-:1005E00007073F1F8FC7E7FFE0E0FCF8F0E2E7FFF7
-:1005F0000707E7E7E7070FFFFFE0E0E6E6E6E7E7E4
-:10060000FF0707676767E7E7FFE0E0E7E7E3F0F882
-:10061000FF0707E7E7C70F1FFFC399BDBDBD99C31C
-:10062000FFFFFFBB81BFFFFFFF9B89ADADADA1B356
-:10063000FFDD9DB5B5B581C9FFCFC7D3D9DD81DF5A
-:10064000FFD195B5B5B585CFFFC391B5B5B585CF0C
-:10065000FFFDBD9DCDE5F1F9FFCB81B5B5B581CBF2
-:10066000FFF3A1ADADAD89C3FF87D3D9DDD9D38762
-:10067000FF81B5B5B5B581CBFFC399BDBDBD99DBD4
-:10068000FF81BDBDBDBD99C3FF81B5B5B5B5BDBDCC
-:10069000FF81F5F5F5F5FDFDFFC399BDBDADA98B56
-:1006A000FF81F7F7F7F7F781FFFFFFBD81BDFFFF80
-:1006B000FFCF9FBFBFBF9FC1FF819FCFE7D399BD32
-:1006C000FF81BFBFBFBFBFBFFF81F3E7CFE7F381AC
-:1006D000FF81F9F3E7CF9F81FFC399BDBDBD99C3EA
-:1006E000FF81EDEDEDEDE1F3FFC399BDADCD99A334
-:1006F000FF81EDEDED8DA1B3FFDB91B5A5AD89DBFC
-:10070000FFFDFDFD81FDFDFDFFC19FBFBFBF9FC17F
-:10071000FFF1C79FBF9FC7F1FFC19FCFE7CF9FC129
-:10072000FFBD99CBE7D399BDFFF9F3E78FE7F3F965
-:10073000FFBD9D8DA5B1B9BDFFFFFFFFFFFFFFFF0F
-:100740008000000000000000010000000000000028
-:100750000000000000000080000000000000000118
-:100760000000000000000000C3BD7E7E7E7EBDC391
-:10077000C09F1F1919191F0E03F9F8989898F8705F
-:10078000FFFFFFFFFFFFFFFF001F1F1919191818B8
-:1007900000F8F898989818180000001F1F0080C0F3
-:1007A000001818F8F8181903C09F1F18181C0F0715
-:1007B00003F9F8181838F0E0001F1F0101011F1F8E
-:1007C00000F0F8989898F8F0001F1F18181898C0B3
-:1007D00000F8F80000000103000000000000000025
-:1007E0000000000000000000000000000000000009
-:1007F00000000000000000000000000000000000F9
-:00000001FF
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/prog.bin b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/prog.bin
deleted file mode 100644
index fbda5f654aacc86289b48b10d478bcb22825c5d3..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 12288
zcmdsdd3+PsweTJ7lD8RKGLkX&9gmms0vLmh;@I*Cyar==BQ{N`$(}T6AxTr&5EM#E
zvove-nlyQ@DM=cfq-{*nh0vxBhRQ{lNpKR=_G>nWNI-<C1qcX<?03#cUI_I2z4yK4
zk8kYJ+<VV*?>*<-bM8GeV^=OB)q6J*zc;Lj-+LR`x~`bX_V_0KJI7i_eWK`h3+$Jp
zzF&>r3y=!yWpyM{<|N|i-u$?caDTBjm2}x`!Z(B~gQ4MLz5DzlULA26gGT4v!nA&>
zV$byq43GNu<{7d*!VT+=xrKy1>j--;G%)Im@DEG;_lZ>_zd??jl5aIJM8grOPu^%s
zPD!9&uxI2_z5Ibnepn+f(8*s~<UJ};Z`aBL2CG{Bz2R8cnm*!>_=kBF*~AlKD<gb8
zu>~vXN%@t;(c$tMDPW*F`4yG;*FO0rMjj_2U&IeX3^OX?bOB|b7ievaUQ@3lZ)5Ro
zg~I@Q1c1)+D<qyFHh0gX70BMLz_j$J{E^iO@QA+;!TsU_e3VXMjYLMha)DZYLL9($
zPcKab&{XR|Za`tf?j0WKb1L+7ceLeXWYo#k6F`<Nx`+*@A1A-dhCqOkQ6DJCrJJ<I
z$rc05NbXG55&3&2aXdbOrmlmQKid5Os*xX2v0rTBYowvTy3i(&vOf%!@=7V7o>0>y
zPe2kYM!1J1xlTQ7Etz2G0#BfLqL}6lZ6ERS)za8i`;!?JBY$bwFvxbG2vrU$Y8Xm-
z<O6X7!}9f-(5NpgZ!m~vKX&sC8Yj1^D(U&5fLxV68uFohxoQbvSBfcV6HnPSLvLC6
zp(ct?+t9<F08>$ywmGj@<#;OD)%R##UC-<94H$5qINE9ndu2qeXX2@1)U&5oR3BpU
z+|X}%wbZ*C!J2)_(DwB$^?6-TtOHFab_W=$?G9+Dda0G^>lyHc`%0=M2Pod;P|<jJ
zP<5X*$-#gWp{#LetSX10q(*Y+pe`DK&za3og*hk!96A95!qWDkS7L%3@`&-3FgU$V
zB^Sn7wK@ir1OxM;MWK<vU>8=pK$KuiL1;9Badpe@s|Un6urm0!l8r`O2+$e?84t)W
z&Kr(ue-8||zj&c{#2*Ac5&wYE1-#OOI$|^mO+qcFg2quBr`K#~Un38w<#*W8;en7(
zS##mA>EXO&b&7B}=kT6=>e11=P?%9rBB@IQ8;$q6YQ2GRS9f51*FcZR4zhVJZy*Wk
zNm!2$jMw!9k_MT)K+=xnffRw=-!stLt>^?ra3&^--+}Ub#UfC0T_S-648yW{VUS;)
z85pu{AfEjc7=(O$rL;uwR7_OZ)5}P-kTO*;MGICt)8|I@S4w?uA@&D?g*ti{0fh!u
z><fEQEcOw99W*`LFHnO57Ocj8nkEQJ#S7vBsQ-p_LHU!oQDMNU;f%z_zNH8(4D<qs
zxel<Sw8B>i2G~y(OuyH)Q!dhGPFz=fZWk`4k%D>&2IC0Hk83v$+PXHpRpu_d10?MS
zKv|hkCP2{}UbccGWXRr==_*zSZNdB<dsb`F;f1|-Ev(zL(4__iJ2=0wm^nN;lroe&
zWEnD7?%ALnN*|gB8uf>RK)*9HO1yK=(^`-Numzg{t1<@Bq8Jm=$Sa9GaRg^JoIp>q
z;~MJ%ZCv-O;@lCxf9=iCF1Kixtr+G3!B`kH7LL6>I*i2N>&AA-ar!q0x|K<J3l1a)
z3u+|*p-IAYU<Hp|RV&FaYN-)j*<2f-!}?U#Hm|8?zEsPf>v&S%PZxlVLyOMD-9UPp
zc8Oekg1ExQhQXHuyzgzRC}h=2ysAE{UfO$Fht7S_01!sYShencS|YHYC(tv!G=O|n
z<hB`fxmIg!a?h%lrNS_*PX7Cy%nbwvfL(9y?5F1P?|1H^iTu`1>}r_=U0LS>MEA|U
zBY+%bsWi(9i>RmZI$qGkTU9?0Fw}gGlJJI63Z!x8*s|y(?Yf!1zMM3=QHg+pn2csK
zPdfXK=nQvlz7Zzim>jEfJE;6eBYN#SO!8<Ndg_#TI)YR{!4pYG`;IuiEa4?bdI^>I
zEJ?@q9Vsc191|r=Bu9M7VhM2pk&`;X<BshBl=QJ}|A~K3veFfmbfn3V{+P%ORSi{@
zrSlren5bEAtfXI*mq@)-T~aLZi=`$<{9|GwAjI?8l5xEtfE!l~wVZU1b@Wo^yYf4F
zd6bDdb%@aN<9fMFCHoBW@ie)`0P{pyj@5Ww8((|Yweh)E2Ylt_Qdc=y+fh<3l~+h|
zt)ZksD!&ZdZt5txOe()zX}cVS$d`h&Ro!xGoEYypv)MiIY;jhF+nNCjG;OGV=x%DB
zP}vhF_+nFh`BJGuRF^E3z+13#PcMiGoV#{?$QO1@D$jDe)GOL1SUY=&EwM|x9UA!U
zD^aiYRYJiB40`uf0t1HxRiFU?Myj5B@4a_RM|W=z<$A@dHw>QZa1=wJOAuFC9lc@$
zHh91-M%&7x)$t^_#Hq%7`A(ylY)!z&RGUR$y$Uaiyy$7GzOSFE!PH^Np}X+9`m7oO
z_ebY@&^kuEt~zBP8x9#dMuNPF$hT@Y4HgH7fqv6(L=79TCTK+yg2BiR#J#C(t8fDR
zYsoH%5luX4zKvs=nMpM)?i+EnBHyrg$c}%aXXrBg6TdqG1kp`iSbilgluG=o-NHQj
z#b^e#v8RU1d1+7+s1Tcyk_Not?wy%i22&Sy^z6*MXYgEC_aIx>GswEYLPOyVPx#k$
z4^?d)1vmP7v27z%d$78zI042bKamI{D1=K0Rnm6`LNFZA7!%W&@&qdj`M@9`Y#Z^R
z+UHRD9E>mQucXENhzabcW4k~t8@5wR1`*(qj6Yl|ftZrPSjRFZt;bRsYbbTnI>!Ia
z1Ux!`#yYf_8Z;8zl@QZ`FAHp;9i9xXj)2}Zp)S^fL0Z-2WPM!^pBVR-ZHhA_(q=}b
zF%TpqYhmjHgz#j5aBL+EU%$RY7n?z>sL}58dvELsoJ&etcUNwwyQql$0yU~M<aT<X
z=xqc~p`*76LKNf;ugfL*%-=1_PQWv?j#@_onH6=Zoq`9+D!M!YeKLD;*cu<u>nP7e
zx#Ggy5I6_4?fLmbm*by}lbUUyWl*Fis_qMw>qe=gk@W2nvtJi^KOhc!{Ud4IYsvR?
z6*J~EH%B3Sq_D>!N+!@xV^-sJ@o%KnYP4da5+FZF+b;AIxcbKGrtL1DNk}n5pfv^5
zyenS5oG7%K%7o7Nq=eJ)H?I|H3t_ip>kjBET$u|i?&<2r$t6|PL1jyaHNHD)nHq#c
zunt%O_>U*!e-;0y_z&W7pebpoWHp>Wrj64VZG|EGz3vJdN)w#-DW%!(O-XZa8l-r9
zVNWZ7<5Tz_PXd1B4893mi)!AyAvb0E_!7xo==kz+_!<9^+Xqh3BlPbB3{k-lb)G?$
z+o~z_l$L@sRu&E-3P|GP=`^+xm*&PphAz{P8;LY-tG>`P_@#Rg;$W0+!(hfjx1ct;
zg*a2d4zqO&cPQGKEy|}8rbW3T@%e=K#8AS2PLyB)F)?^z3;aSEngW|~YWyMzrqI6|
zr~SlkWxwT%fy$Riu0hpM)xJ8w=mK~L%)DO^HQ>K|8~ZoVvpt7Y5U_M42mqredA*PV
zKfasS;tV@L>H0yC1^5f0De6wX+?SM8SLjhDjd5@T?At6o{ge|thu=6X(728LR1Y4*
zss&%d!r~6{yyQ8gaS!Ujw*dhJud&yK+i>;5-YKg~l7E{F`}(E%4kCAQktHhmjw0Bp
z!7+#~ma`W`&q!31f6oI}-W=JO#5b|>NlhXH2P(u$kZsCS3oQpZB|@VwZA;=<D`QNB
zZ6j~#<d!EfMGP?O31m)WQgvF28)<QqMUTM<${5AwRT?cgjhVZ;rmdl_i8eZywb6#A
z<&>w3F0(JDm%N(mT}?HVE-AKCx^#)1E-foAp|s7})b6Cq8=bB2>uhYORcPDmT`Qe!
z)VZo1p6w0GquejameN{RD|N11)mF2zrm3B}ni^OC6GUuoZ*6F9tfAGd&JNn_T2a#q
zZ6Io0w}V9G1~PEr)aUk8u&1V)cW9=XHPAecLS!;Y(%0B0ShZOK7Rzd=lP+thqa6)R
zO$t+Jy!g6Q?-yhJhg*~-l^_~G^NTfL9S)6rdmLZQaS~-1GiX+)<%)^CNbikqc;#Ij
zV<g56gWVm|4I2)1cfjeIW;y1|=W}scBgz1K02{TAZfKN`rYYJVu!fzDjkLXCWeu%w
zsH>-K%U!KCZRm9?#l-Rlr3n=+f|DB_i14rkeQ-y&!A6^ZlH<l-WEdS9+fO;}9ATJr
zC@Wl>T@6j`ZOx6&)gU*;M56PLwX}D*umeVe<CZ!YMmt3aY6HuZKjTnKvZA62_AKfq
zfj`IXtK>Dw`*?e@qN%yb*~yHtUP7(0ST@(wSzXpSVM?wmFReJFslJc~21Tc7aCi_v
z)G!#xP*@<*!0`_xbM+#_Bu|Z%|2JqbFpLcvtYgg}wYI7L+uEJ2?a`J+6im6~0sv0E
z`D4yNU@!E65v&ko<|F%#b{-{1$&oRLRI{$VfAS9gd7p3p(1BQ^{MOqChu?Yky^%wI
z`Rm{Q&)?tw;KPqT9{uF-r~bgkl-`s-q`aMSIOS|goH^6H*j#76%Dm2ekNHXSV=07e
zOnEiMoAS4mu@uH^G3T2r%`N8Z%{}Ia%+Hz+o6njVOOj=tCErqNsj{?LuCm->*=YHp
z<zFqou<W$#wY+Wlvw6h4%lr%Tn7P4nt)(UX$R)0p^vzqgd~XX}_k4fr5Af;PvgPg;
zoA#Tx>d7tNB2fDFdOcZp8<tG*dJ>m_r9@Uwk~l0SSLjJfC6-bpJ(=UgQd+v6%$<j&
z45}xYJeINmPsqViF5u<mW2pez3g=^K0kkb#gr$-tda}3_OJ#OFS$Y|k$^q|kr4I+-
zRVjTetJag{H3+S(*OR&iEM3v4Co5KBsi|2{TrF5?ZP$~wRam;RQ%^cpW9e&O*ORN(
zVCfrc^`z@+EM0S*o?Lr9mTtI7Pj0-Kw4^Bty!|^wcgLNESna#rMCb0Asxc~}Q){Mb
z8}1^yjhhTDwtMgY;Y0U5@ZiHOHnTOm*kTilT5Ly;AOGyw@#Ddk{6`*p{Kro|_2`fO
z<%yp>-I5ROQ3%5LfBosto_*-wp4s-?!!0~QkObOo&p-LtQ$PR7kDi{z#}*Eq{rt?y
zbLU&Q7oP0h{*xD5xTA<4Y~fCXPW|KL>6S&m>U;Iqzumd(l^w7B=6A3EzGacpSCl7m
zUG&KPFTM2Sk9!||;N_Qp^2Cc5!TA?{__JU9Vf%yIe)+})qv5rGd~-mr>)*Y{FuUDv
z30RI<PFc=ac;>T{hR2?I_N7;M4fuu`%RCKd<MT^#jYf~GIjQp1sdB2C&rAh}#F0m*
zmgw@<n(Bu3utSSEG_9y|m`bj|{1{T2z=sC;&Q$P1a8mtxDx-yGB^^^77-=R%2_<20
zL$}At?o>IL3PlLUoz@rw1_0c+f&VFVng%_}!>JL^QuNw8Q)hWW@O;Z^+S;SOh0=Ow
zQ#HC*89e7AJ-R^d<F!!_7(4Tzw}s5>w{wZW9ev%QlD8VCHo^$f5t}aCK`^nc^umBy
zso>VYt%sY1o5C%@y&i4^;)LZzRu?e4Juc!Ym@raRBIyBkOaUCebcB1<z_-lVdpS{E
zIp>o(j4_eFZqAeto1G09QDYalvRU=T)Kv>naz#T^HNe~2Tb&R?+M}qojjP(~r^smS
zDhM<6E(qz^wB*us3Q4PLwX=~<QNuvGcX<y8R)$H05iyCxSm!Xnc6^`$X5sIdFz)Y~
z!?RY{ckb<)WBmKPgp5@gFK6g7Z_0cpvzq>q`r(kw=X7peS4Kk7<AlS=J-Q9&4hPR@
z%#3mbWlZTG1%?=fpq{m?PAj{u4slC|z@AZLj$lunl76H~ufmx|E{%7PSH(FKiDC+0
zOu7Tbut84Ry3WDg(*>|;B6*v}q21bbsKTz!wlW*nWjz2nlh`Q-U}IN3AU!$O3dzLi
zNjsYE$9D&?iz|6h0wY8dz~n4H$EH{=1m=jX65#X`S<oOe$hM;mC_2B4mw#!EtS`Z!
zdaW%eb7`El*`a0bOq2In#dI0qG)<nLCO?Y#9`UnE`l+J=w+Dc)<jkTHOAwQJ=tWfX
z`ZTV&o?%R&3jQG*ClW?89rfGmYv>iO)orl3TS39hX>CJm4PCaXy&bjyP3;hgSG!iV
z(k2YdtJ)fx>SD&>q)jy)vvwcTHUov_uBN(HXZxx~*fP4B+7u43b8JJLnP5L_U*Xkh
z66tMh1cnd025;EpW*9~>WmxvGnj^nkB5EV0ORRYjPl^05CI@*9<j^(`<OC#<vL$AV
z$i{g`xjWN7DpoU(q~Y3AL;aDokL;&FaMlyfWy`B;YU}D7u2|8yvdPul(%RO(>dKDJ
z)nB9FSD=SdQ5PvK?X%jjiw{g9Czm1rNLi^_2s;d0IzpgcpOGwtRl2aMYWKn_$L57q
zmGHbA>Pz8X2=z>O5;(Q50FMRvILN;;lcanF<cT1E%w;&kX(_y8F4#TI<X1?gp$SHu
zGuJzUr}O-k)wf)O3F5IG!;n4>rKF@((zi#4drC-mcZu$%q!Rs2kgAQ(OuzVVVfw;!
zFmG3{2%duUQY|kyt)+a1Q|UUcu7}f*{$jn2J%3x!I!8?F3EmX#(YB_&5ITaBjynhg
zS`rk%8h!p=QR7OpCc>+fNzta)>+!&x7Jwk0t{g`b`YL*wbZW4(UQu5u@_@@JxM>P5
ze{SwyW}^eHN;B%~XmpkpQi~}*EpM@-p>53#>)dz$;GxH#`q>LF_x*b38*lC%+%F$|
zXENx)41oOH+}jK9D0ByXvHH+dU9kwcV=mW*nf*J2+fms?>+ksOBtp~(`PMAR+N-a*
z)-waTZx-m9Yp=V07U=m|pzE%`;l^2@{#l?KZoKJc1q8C)NfRA<?D3;n2osyP+@o};
zLdfT{Adm@E01N_>=gkcNnXNy#w_gG25Hx=_=v%km^39uXQh*u+UNH;Uf78w1yyez!
zC_pU&Z=4N$Fv`-1fX%Z2+n#;y`JcbAy;mVKAoQ78(BADY{QUXnp4~QyYY&bb5Oe`!
z_biOl;n0Z_;|Go&^MCTmr@Nz%Pd?fG;Q@tV9HO6$p)(l-)pOv;(PLit^KbQsP67F;
zaCrRP;qdX{8H((Ts5qF4|2xGrC+~^l!4siy_*Ce`<L}P!xpj)q{Qnm|)7){KGfW4j
zm|pi^W*VFP4DWfFv59y8ckv!R_VIA&)JzX|PxbKNe{T=UR6?ghGd&%f>S^2mOivg0
zcomIF?>GOmJzk`?_oh1D_rKEdW5Y*K%rT#%tg$wJ#(^9>aQtle^vQ!KP6Uq~ITnQF
zdGhqg!ymr&@WGP@PmZ5Fcy{D$_-uHbjWrw`A0Hb3$M`#sj(>RK0-W&K;}0G<eLRLf
zescW83BY{|ANM~qDZkIl8Cml3EO~pDygN(&FiQ?*$>*}<x3gqckOe{6rANvxgD*D9
z;l3R13VesmTm~-@V|z252HtMCyn-JdyCB0=ku0#MM+Z{aqtRUzY~so)6(ZQkdEoW2
zP6J8m@m*BMo(0IHk~u>ph}zNJp4^iKhy6I%C_j?rVBo}H)M+Xv5{u)Y4pgTBHAaO!
zE9{bX6*DgOjPfP~vQAnT4o1`o>{$o1Q_0Ii2L(n*=v*P}6yqjT4nkE9CgLu@*FP$y
zRRb6*tg5H0I;ciGjtYt}wNj~!Rx~qo2?|%p(IAp`ioz7}#8CBcR)P7!j$co0u_*!x
z%q7l|fDfdD`~!qvZ%nrE>a(9R@sKTzz1s=H)`dSPaGwf{naE;+>?(lI4jz&sWo4if
z3GT&k*Ah4$!Jbl(?<<hU3*?O=)$xB2<bM>x#<Jo@NN?U1`F2?m{kxn~q$tO9MYcQp
z=h?&A6WN714cY7A&R%ft#SAj_M@bgRhK=m!f;u}Pdrmf=U6_4ND22N!n=nblm_ag$
z#7>v&)1|f3rTeB!JFr9vPeg?xiwHzi@Ulq`5qH3AYf#DWsv_<x{6dIdLb9%w_-|!r
z-6_F*VgD9_^dN9pqVx&Kstb{?mH4N#v)q?Jwga-}Lgecu{?FN2J(oaU3&@5Gk#Cgv
z)7e=YFM)g?AhQ=D-z@QbPS&PNAn$<l0RQzI?rI5MzQcj{h8*tBXfaY&MIxR$#kQQ2
zINP>)cqW<BL&hu(0B$DeeG+Aa<_RasKi!uTJrLs#`VV<gt60pSMezO{ZY+l}Oj*sv
z2J(K+KQ|DKDVNPP<;LYU6Oj~vA%t_z<b-obuA+RA<P%9zc>yUT(tSQ0mf|yT96!wk
zGn4n{@;$lS_j0F40Hz89L$jSS*ZkS$x<2=kqmh4|i>H2+35-dd2V=@>CJRWBGN$`;
z!#R)VqHQc73u8knBJ*KLAaPhzTp?smS4v8HA$HV@wFdcF&A3Xz^s0!wdVyku^An*{
zST?Rel6Ve0(CMB)mHgfU@p!~NKQsW}Fj)-vz8ic7kyG;UNuy6BE6jr|FDyjF0Z&&p
z8C8)h;+Y?yyRiRd#3s(wX~6BXU+~|_<HTl$F~B)Veqf$5)9RJ&YasVLpyuxapu{k7
z2)uQkbrjO!w9(bpj?Ze>s%4Ee)p*uaj6qC^@%B52PJ`dKu;)h=e$Wo-E#p9ptMxO5
zCOQzsox@=qSm^PUiBUP(DrA@terX;aM;Y;goG>&+)51w2q=grY`}i&~nidxGL?*so
zik%5tYn;^=ygb0vZ<Xj08MeN7<^)ME!ow3L;@)y0E~beUT%2)jg_xw9jGgjSIuco5
zizhpfhI~$h_dD{B^U)_Rn|_mXwSe`KsrrUUtrI-()K`h%nIXZnDF<;9<$K|Tis>ZB
zb$B4}&KL1?4`$8~>lqXtZ_7^*jl7VL=koda+_~7fT#*}&K6=f}an>mrEVHZ>mcbIZ
z?QlC`Mc2U%o?v}R#Jv<OGi!|mzg!bKi8AmQV3(NNx;j-cVwinYp^BcVUSQ9|;!-K$
z&W{lTUulizIaClR_((pdE`V%HEO?NT`=!|{5vMz~4l84k<4is*MI~xr_<-3f!D9r2
z2OP&w72Q#ky<jc4f^1?eFcp{!6rYew@?r}Row}sB_c9o~WCwYTa9xsjY{vkc>?L@>
zVg~n#hjoZkrUG!?z*rG$7kt0MdIX)yFC=R9@84Ar#?(&;Ueyk#aU$zyk3}td1V8LL
z9E9{vj1WSFH$CE6d~a7Od`Smie1+ttMHtfI1&+6Xvr>jh!Mw>|3pkc#7^{+%fN`|d
zG}bI{r_1YI4a;Mhk$;v(xgdivm+z9MlNgl!HO;gdFgTkd?j@mN-v+&1557Svw0;JL
z1&_lUv4xSJD75|+0Pq;b2`9mj?YR?LhG^|-Mr*2goiaW0yM^=&oY-XBJam?z(1?4n
zl?SXz4Pa@EmAfd@{S_=gQH&3G+UEgRhjGGGT!ct@Gpvx06@Z7db`C-DQBbr8aBQ&R
zCtx7LA#FvSN6$ta#16Zq=te50F-+i;T63c7&Ot;gviPMH=5${HaE6qK!xV9sIwm7-
zJ7^W=$TaT;nS+P?z=(?or;Q)tEx5#IcxFhOL_gV6zQ6<R3h)7*9zMW(PnjI-ocRp2
z7y0ob$f<$}^&9LOJek71H+uoN1$)K*=ZhR@=6eqnMLeoN(w;*_<@dvvBKxED@ja)N
zx@!MvfU5ysJ|E$l{pIubZpPvn2B`Ue6v@Zt^XfTr|9p9MddP>lULQhL0ENT!`CLAE
zKBA<~N0jdX3a0)pN&$a0M@$JpE}CgBoeGz)D_kA{E(9sQN_7!i704OK@PtDBv_kzd
zQvU}Bfogy+pp~3<@Rn-^97fnGLCC=ivsY`{;p3a*F{wvUF@^+}tr!J7<ASJvRN%4i
zNS`!4GxZ@UJstawG`6VAACm6H*us?(Nc7-3!E`>xM)Yj%1@g89@<jSnpjURyRp{g3
z<e<|g*;N=R&naM7?$KyH17*vUXzfo=%m9CtK+g;8XUeV`W{7b;in*p8IEC$&OGWkM
zln{G3I#qD(D<xebe6x_io-bG<!AFE^;5*>x5&*r-x~gK=<YcUHckDS;1;C^NgkOM7
QR=qj-rUHZd{|DE<1KehbMF0Q*

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/prog.hex b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/prog.hex
deleted file mode 100644
index 01a4e165..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/prog.hex	
+++ /dev/null
@@ -1,769 +0,0 @@
-:10000000ED56310044C37B00E5C5F5040CC3710017
-:10001000856F3001247EC9FFE5B7ED52E1C928287C
-:10002000E5772310FCE1C9ADE187856F303C1839D5
-:100030004700FD36410028E1C3290BD5F5BE300548
-:1000400016005F1919235E2356EBF1D1E9A7C8E525
-:10005000D5C506004F09EB09411B2B1ABE20021023
-:10006000F879C1D1E1C9C32708247E23666FE977F7
-:10007000230DC26F0010F8F1C1E1C9FD218E4021AE
-:1000800084001804CDBC00E9F3CD6C0A0100041112
-:100090000040AFCD7B0A12130D20FB10F6CD3507C3
-:1000A000CDDD02CD8E04CD2E06CDFC15CDC20228AD
-:1000B000073805CDC1081803CDBA08E9F5181CD5D5
-:1000C000E5FDE5D12102007D21000019360021481F
-:1000D0000019EB3D20F2CDAE0EE1D13A4540E608E5
-:1000E0002006CDAE0228D8AFCDA901CDF000F1C9D0
-:1000F000FDE5E5D5C5F5010200414FFDE5D1AFC5F0
-:1001000021020019010704480600CF21020019CF7F
-:1001100021480019EBC110E7FDE5D1413A4A4021E1
-:100120000100197779903C210000197721480019C6
-:10013000EB0520E8CDDF1841FDE5D1FDE5AF21015C
-:100140000019BE282E210100193579903C210000AC
-:100150001977D5FDE1C5CD2A03CD9628C12101002F
-:10016000197EA7200E79903CD5FDE1C5CD2A03CD9F
-:10017000D011C121480019EB10C3D1D5AF412101E5
-:100180000019BE20C021480019EB10F2FDE1411119
-:10019000480079903CCD1506FD1910F6CD350BCDF4
-:1001A000D310F1C1D1E1FDE1C9E5C5F54F06FF1856
-:1001B0000BCD1508CDAE02CD58120600CD810A2810
-:1001C000F00C0D20166FCDAE02BD38E5CD150845FB
-:1001D000CD8F0210FB7D214540CBE66FF17DC1E163
-:1001E000C9E5F52145403A3D40E603FE03200F7E78
-:1001F000E640283CD5118E40CD4703D11832FE0190
-:10020000202E7EE630FE302027CBA6D5C5214440E7
-:10021000ED5BCA12010201CDFC087AC610573A45BF
-:1002200040E6023E20280401200079CDCC0BC1D14C
-:10023000CD6504F1E1C9F5CD7A082814E5214540E2
-:10024000CB5E200BCD52023D20FACBE6CD3F1CE128
-:10025000F1C9E5D5C5F5114440214540CB562813D9
-:100260001AFE993804CBCE1821CB4E2004CBCE18E1
-:1002700019CB8E7EE6013C471A802730023E991248
-:100280004FAF90274779B8D4C108F1C1D1E1C9E592
-:10029000F52144403A4540E60128057EFE993003A9
-:1002A000CDBA087EA72803D6012777F1E1C93A44E1
-:1002B00040A7C03A4540E604C83A4540E602C8AF08
-:1002C00037C9C54F3A454047E608200E78E6012079
-:1002D0000578E6042003371801AF79C1C9F5AF32BC
-:1002E00044403E01CDF00A3E02200CCDF00A20032E
-:1002F000AF180F3E01180BCDF00A20043E0418027F
-:100300003E083245403E06CDF00A28083A4540F600
-:1003100080324540F1C9E5214540CBE6CBEEE1C94D
-:10032000E5214540CBA6CBAEE1C9E5F5214540CB63
-:100330007E280C3DE60128070602CD2B0B1805068A
-:1003400001CD350BF1E1C9C50102004121000019C1
-:100350007EA7282F3D4FD5C521020019EB010200D1
-:100360000901070478CDDC03C12817C5060021CE9A
-:100370001209097E23666F010704EBCDFC08C1CD8D
-:10038000A81DD121480019EB10C2C1C9F5BE302FFC
-:10039000C5D5E5EB210000FDE5C1094F7EA7281C6E
-:1003A000EB06000909234E2346110200FDE5E11981
-:1003B0001107047A545DCDC103CDD210E1D1C1F152
-:1003C000C9A7C8E5D5C5F5F50A8E2712031323E39F
-:1003D00025E3C2C803E1E17CC1D1E1C9A7C8E5D5E5
-:1003E000C5F50E00471ABE282E0CC54F46C5E6F0CF
-:1003F0004F78E6F0B9C1792810C610274FC5E60F2F
-:100400004F78E60FB9C179280CE6F04779E60FC6B8
-:100410000127E60FB012C1132310CA79C1A778C112
-:10042000D1E1C9E5214540CBF6E1C9E5214540CB05
-:10043000B6E1C9F5A7282CE5D5C5470E00218E40A9
-:1004400011020019C5EB060021CE1209097E2366B0
-:100450006F010704EBCDFC0811480019C10C10E432
-:10046000C1D1E1F1C9213D4034237E3CFE3C381C22
-:100470003600237E3CFE3C38133600237E3CFE3C97
-:10048000380A3600237E3CFE183801AF77C9E5F5FF
-:10049000213D40AF772377237723772377F1E1C995
-:1004A000213D40235E2356237E23666F3A3D40C99B
-:1004B000F5C54F7EA72838D5E547237E23A1BE2367
-:1004C0002008235E235623231809BE201A23232342
-:1004D0005E235623C54E2346237E23E5666FEBCD70
-:1004E000E20BE123C118041109001910CEE1D1C1BA
-:1004F000F1C9F57EA72823C5D5E547232323235E2D
-:100500002356232323C54E2346237E23E5666FEB24
-:10051000CDE20BE1C110E4E1D1C1F1C9E5C54FB7AE
-:10052000CD2C051FFE6430F8B9C1E1C9E5D52A48D4
-:10053000405E23563EF1CD93057BC6195F7ACE36D9
-:10054000772B73D1E1C9E52A48403636233623E1BB
-:10055000C9E5C5F5424B110000CB38791F4F300378
-:10056000EB19EB29B0C25905F1C1E1C9F5C57C2FE2
-:10057000477D2F4F032100003E11E5093001E3E1E3
-:10058000CB13CB12CB15CB143DC27A05CB1CCB1DA4
-:10059000C1F1C9E5F5EB110000B71F3003EB19EB12
-:1005A00029B7C29A05F1E1C9E5C5F5FDE5C121020A
-:1005B0000009EB01070478010A0004CD4D00380E54
-:1005C000D511090019D10D20F210F004182E050BD9
-:1005D00078B1281BD5E5E56069110900CD510542C8
-:1005E0004BD121090019092BEB092BEDB8E1D1EB17
-:1005F000010704480600EDB0CD0B07BFC178C1E18B
-:10060000C9E5D5C52ACC12EB2A4640010704CDFC2A
-:1006100008C1D1E1C9D5C5F5ED5B4640CDA805209F
-:1006200009CD2A03CD1B19CD0B07F1C1D1C9E5D5E1
-:10063000C5F521044801FC03CDF906210048BE2080
-:100640002E010200210448060A116600794EB928DD
-:10065000110C0D284B1910F5010004210048AFCFF3
-:10066000182823224640210248224840C3F406AFFE
-:10067000CD7B0AC608210048010501180577BE2078
-:10068000322310F90D20F6A720E6210448010200CC
-:100690007123224640210248224840CD4605184E8B
-:1006A0007723224640210248224840CD3616CD0B02
-:1006B000071841218458016600CDF9060102002186
-:1006C0008058BE20143A8458B9200E2185582246FD
-:1006D00040214240224840181B218058066AAFE75B
-:1006E0002184587123224640214240224840CD3681
-:1006F00016CD0B07F1C1D1E1C9E5C53EA5040C1823
-:100700000286230D20FB10F9C1E1C9E5C5F52A4693
-:100710004001004CB7ED4221044801FC033806219A
-:100720008458016600CDF90601FCFF0977F1C1E1AB
-:10073000C92A4640C9E5C5F5010480210058AFE744
-:1007400006087C80670D20F63EFFED47773E20CD02
-:10075000BD09CD350BCD730ACDE11ACD1508CD13EA
-:100760000C20D5F1C1E1C9E5C5F52100400620AF57
-:10077000E73EFC3221403E1C322040212240061040
-:10078000AFE73232403EFE3234403E0C323340F16D
-:10079000C1E1C9210040114058012000EDB02122E3
-:1007A000401CEDA01CEDA01CEDA01CEDA01CEDA0BC
-:1007B0001CEDA01CEDA01CEDA01CEDA01CEDA01CD0
-:1007C000EDA01CEDA01CEDA01CEDA01CEDA01C7E5E
-:1007D00012C9E5C5F521204006004E3E1C912811A6
-:1007E000CB3FCB3F361C210440090E0470093D204D
-:1007F000FB3A3240A720033230402133404E3E0CBA
-:1008000091280ECB3F360C212440097023233D2034
-:10081000FAF1C1E1C9F53A0078ED57A7200176CD8C
-:10082000D207CDE101F1C9E5D5C5F5CD6C0ACD936F
-:1008300007CD3602CDC908CDEC1ACD5108CD730ACB
-:10084000F1C1D1E1ED45C54F7BB2A14F7BA2B1C152
-:10085000C93A3A405F3A006057323A403A3C40CD9C
-:100860004608323C403A39405F3A006857323940D6
-:100870003A3B40CD4608323B40C9E5C521354001F1
-:10088000000278CD160B280C7EF68077FEA1302270
-:100890003C77181E7EA7281ACBBECB7F2014FE0201
-:1008A000380EFE21300A0C3A37403C2803323740DC
-:1008B00036002310CD79A7C1E1C9F5AF320570F13B
-:1008C000C9F53EFF320570F1C93A3840A72819FE34
-:1008D000103810D610323840C03E04323840AF32A3
-:1008E0000360C93D323840C93A3740A7C83D323766
-:1008F000403E403238403EFF320360C9E5D5C5F581
-:1009000079878787825778A7792011A728617AC6C7
-:10091000F8573E30CDCC0B0D2855183EA728497A04
-:10092000C6F8577EE60FC630CDCC0B0D283A7AC6F6
-:10093000F8577EE6F00F0F0F0F280FC630CDCC0B07
-:100940000D2829CD75092812180DCD7509280FC657
-:1009500030CDCC0B0D28152310C57AC6F8573E2094
-:10096000CDCC0B0D20F41807AFBE20032310F9C126
-:1009700078C1D1E1C9E5C54FAF180423BE200210EC
-:10098000FA79C1E1C9E5D5C54F4787878782577A8C
-:10099000D60857D5EB210A00CD6C057DC630EBD1CA
-:1009A000CDCC0B7DB4280410E6180D05280A7AD6A4
-:1009B00008573E20CDCC0BBF79C1D1E1C9E5D5C5E3
-:1009C000F521B2124F0600094E210050711101505D
-:1009D00001FF03EDB0CD6707F1C1D1E1C9E5D5F560
-:1009E000C5CB38CB38CB38287ECB39CB39CB39285F
-:1009F00076D521B212856F3001247EF5CDAE0BF194
-:100A00001600E55977231D20FBE11E201910F3D1B4
-:100A10003A2140C604E63C284E0F0FC1C5F578B711
-:100A20001F82C6162F5779B71F83C6F85F78C61086
-:100A30004779C6104F210040F1F57A96E56F78CBE3
-:100A40003F85E1232323B830197B96E56F79CB3FAF
-:100A500085E1B9300DE5D5C5CD960EC1D1E12B2B81
-:100A60002B2B23F13D20D2C1F1D1E1C9F5AF3201E9
-:100A700070F1C9F53EFF320170F1C9F53A0078F125
-:100A8000C93A3B40E60120093A3B40E602C83E0233
-:100A9000C93E01C9F5E53D203021D50A3A3C405711
-:100AA000A62320157AA620151E00237AA62012233D
-:100AB0007AA620111600E1F1C91E0118ED1EFF18DB
-:100AC000E9160118F116FF18ED21D90A3A3B4057F3
-:100AD0003A3C4018CB80200804402008043D2808F8
-:100AE0003A3B40E6103E02C93A3C40E6103E01C99E
-:100AF000E5C5F5E6074FFE0330053A006818033AEE
-:100B000000704779210E0BD7A0C178C1E1C9004020
-:100B10008001020408003D28083A0060E6023E0217
-:100B2000C93A0060E6013E01C9ED4DF5AF320770EC
-:100B3000320670F1C9F53EFF320770320670F1C916
-:100B40000405C8E5C56779E6F80F0F6F7C2658776E
-:100B50002C2C10FBC1E1C9E5E6F80F0F6F26587E7B
-:100B6000E1C9E5C54C210058062071232310FBC1C3
-:100B7000E1C9E5C5F56F26002901DB15097E23666D
-:100B80006F7ECB6F2018D5E61F3C471658237EE6B4
-:100B9000F80F0F3C5F7EE6071210F2D1180CE60743
-:100BA0000620210158772C2C10FBF1C1E1C97AE60F
-:100BB000F86F2600542929CB3BCB3BCB3B19114086
-:100BC0005019C9E5D5CDAE0B7ED1E1C9E5D5F521EA
-:100BD000B212856F3001247EF5CDAE0BF177F1D1E5
-:100BE000E1C9E5D5C5F5AFB92824B82821E5CDAED2
-:100BF0000BD1C5E5D51A11B212835F3001141A77F3
-:100C000011200019D11310ECE123C10D20E4F1C132
-:100C1000D1E1C9E5D5C54F21BC1A460405280E23EC
-:100C20005E235623DD1AA623BE00000000AFED4769
-:100C300079C1D1E1C9E5D5C5F529010D13094E23C7
-:100C4000460AE603214F0CCD3B00F1C1D1E1C904B6
-:100C50003D0D580C0F0DF40C696023462BCB7E28FC
-:100C60001978E6073C4F1F2F3C835F78E6F80F0F9B
-:100C70000F3C471F2F3C8257180C78CB38CB38CB12
-:100C80003804E6073C4F7E23E5E6180F0F0FEF9779
-:100C90000CAD0CC40CDD0CCDAE0BD1131A160059E3
-:100CA000E577231D20FBE11E201910F3C9CDAE0B03
-:100CB000D1131A112000E5C5773C1910FBC1E123BF
-:100CC0000D20F3C9CDAE0BD1E5C5131A777DC62033
-:100CD0006F30012410F4C1E1230D20ECC9CDAE0B1F
-:100CE000D1131A11E0FFE5C5773D1910FBC1E123CF
-:100CF0000D20F3C90ACB7F20021D1DCB772001AF49
-:100D0000213240772B3EFC93772B3EF09277C9211E
-:100D100033407E23BEC80ACB7F28021D1DCB772817
-:100D2000067EC6027718042B7E3535212240856F5A
-:100D30003001243EF09277233EFC9377C921204076
-:100D40007E23BEC80ACB7F28097AD608577BD608EF
-:100D50005F0ACB7728067EC6047718072B7EC6FC71
-:100D600077C604210040856F3001247AC61E2F7794
-:100D700023030A77230B0AE6380F0F0F772373C973
-:100D8000E5D5C5F529010D13094E23460AE60321D1
-:100D90009A0DCD3B00F1C1D1E1C9044B0EA30D0C5E
-:100DA0000EF10D696023462BCB7E281978E6073CAF
-:100DB0004F1F2F3C835F78E6F80F0F0F3C471F2F24
-:100DC0003C8257180C78CB38CB38CB3804E6073C3C
-:100DD0004F21B2127DC6206F3001247EF5CDAE0BBF
-:100DE000F1160059E577231D20FBE11E201910F3B1
-:100DF000C90AE68028021D1D2131403EFC93BEC079
-:100E00002B3EF09296C07723772377C90AE6802895
-:100E1000021D1D3A34404FC602CB3FC8473EFC93EB
-:100E20005F3EF09257212240BE2328042310F9C9C7
-:100E30007BBE7A20F779D6023234400600EB2122BD
-:100E400040097E127023137E1270C969607AC61E33
-:100E50002F57CB7E2807C608577BC6F85F234E3A2C
-:100E60002140C604E6FCC80F0F472B7EE6380F0F63
-:100E70000FF52100407ABE23201579BE2011237E74
-:100E8000E3BCE323200B7BBE2007CD960E18052381
-:100E9000232310E1F1C9EB2121407ED60477C60758
-:100EA0004F0600210040090E04EDB82371C9E5C5C5
-:100EB000F5210000225F40CDB5123E01CD37293E1D
-:100EC00000CD5811FD3402CD732CCD2C05CDAE02D2
-:100ED0002033CD242ECD1508CDAE022028CDBA2149
-:100EE0003E01CD2717CD090F214E10CDF2040E0182
-:100EF000CDD310CDAE02200DCD1910CDAE02200500
-:100F00000E01CDD011F1C1E1C9E5D5C5F521530FD1
-:100F1000111018010916CDE20B21155811430F01CC
-:100F20002C01CD150879E61FFE1F20031A1377CD7B
-:100F3000AE0220050B78B120E9CDB5123601F1C122
-:100F4000D1E1C90204050102040501020405010200
-:100F500004050144455349474E204C414253204922
-:100F60004E432021203139383320202020202020DA
-:100F70002020202020202020202020202020205041
-:100F8000484F4E4520203430382020373438203721
-:100F9000363032202053414E544120434C4152417F
-:100FA0002043414C4946202020202054484F4D41A9
-:100FB00053204155544F4D415449435320494E43CA
-:100FC0002020202020202020202020202020202021
-:100FD0002020202020202020464F5220414D5553D4
-:100FE000454D454E54204F4E4C5920202020202066
-:100FF00020202020202020202020202020202020F1
-:101000002020202020545249504C45204452415722
-:1010100020504F4B4552202020E5C5F506783E0074
-:10102000214E10CDF204CD15084FCDAE02201B7914
-:101030003C10F306783E00214E10CDB004CD1508CB
-:101040004FCDAE022004793C10F0F1C1E1C9011F7F
-:10105000000F5A10961003144020202042452041D2
-:10106000204249472057494E4E45522020202020FB
-:101070002020202020202020202020202020202070
-:10108000202020545249504C452044524157205072
-:101090004F4B45522020202020202020202020209F
-:1010A0002020202020202020202020202020202040
-:1010B0002020202020202020202020202020202030
-:1010C0002020202020202020202020202020202020
-:1010D0002020C9E5D5C5F50D28083E01CD3304CD46
-:1010E00058113E04CD720B2144111140200101140E
-:1010F000CDE20B0605113000CD3107C5010704CD47
-:10110000FC08CDB911010900097AC6785701070416
-:10111000CDFC08CDB9117AD67857CD810A20223E70
-:101120002DCDFA267BD6085F01090009C110CCCD70
-:10113000810A20053E78CDFA26CDE81AF1C1D1E129
-:10114000C9C118F5414C4C2054494D4520484947E8
-:10115000482053434F524553E5D5C5F53D280E3A37
-:101160008C40FE02202CFDE5E1114800191102001F
-:101170001901070411E8A0CDFC0821971111F0A86E
-:10118000010106CDE20B219D1111F80001011CCDDA
-:10119000E20BF1C1D1E1C9504F494E5453504C417B
-:1011A000594552204F4E45202020202020202050FD
-:1011B0004C415945522054574FE5D5C5F50104001F
-:1011C000097AC64057010105CDE20BF1C1D1E1C951
-:1011D000E5C5F5CDB512CDEA1106783E00CDB004D7
-:1011E000CD15083C10F7F1C1E1C90D21F811C83D3A
-:1011F000210412C8213812C9011F000F1B1224122A
-:1012000001094840011F000F101224120114482048
-:10121000504C41594552204F4E452047414D4520A5
-:101220004F56455220202020202020202020202002
-:101230002020202020202020011F000F44122412F3
-:1012400001144820504C415945522054574F2047D3
-:10125000414D45204F564552E5D5C5F504052803B7
-:10126000CDB5120C0D2015FE012011218A12114856
-:1012700028010112CDE20BF1C1D1E1C9219C12116B
-:101280004808010119CDE20B18ED50524553532087
-:10129000504C415945522053544152545052455399
-:1012A000532031204F52203220504C41594552207A
-:1012B0005354415254D5C5F50150E01108003E2069
-:1012C000CDDD09CD1508F1C1D1C900C8E858E80045
-:1012D000E800E7ED00000000000000000000000052
-:1012E0000000C3C4C5C6C7C8C9CACBCC0000000033
-:1012F000000000CDCECFD0D1D2D3D4D5D6D7D8D937
-:10130000DADBDCDDDEDFE0E1E2E3E4E5E67B13A748
-:1013100013BB13CF13E313F7130B141F143314472A
-:10132000145B146F1483149714911300007B13B192
-:1013300013C513D913ED130114151429143D1451B9
-:1013400014651479148D14A114E314F71401150F06
-:10135000151D15291535153F1553155B156B157B97
-:10136000158B159B15AB15B715C315CF15C714D520
-:1013700014B914AB14ED1449156315511CE7E7E7D4
-:10138000E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7E7ED
-:10139000E7511C8082828182828282838485868258
-:1013A0008282827E82827F5119056A6C07006B6D92
-:1013B000005119056E7007006F71005119050A0C74
-:1013C00007000B0D005119050E1007000F110051F9
-:1013D0001905123C0700133D00511905164007007E
-:1013E0001741005119051A1C07001B1D0051190552
-:1013F0001E2007001F2100511905223C070023254C
-:1014000000511905264007002729005119052A3CDB
-:1014100007002B2D005119052E4007002F310051D8
-:1014200019053234070033350051190536380700E5
-:101430003739005119053A3C07003B3D0051190569
-:101440003E4007003F410051190542440700434513
-:1014500000511905464807004749005119054A4CF3
-:1014600007004B4D005119054E5007004F510051D8
-:1014700019055254070053550051190556580700D5
-:101480005759005119055A5C07005B5D0051190559
-:101490005E6007005F6100511905626407006365C3
-:1014A0000051190566680700676900511A000000BD
-:1014B000000072740006737508511A0000000000E5
-:1014C00076780006777908511A00000000000102C2
-:1014D0000006030408511A00000000007A7C000690
-:1014E0007B7D08511987898B8D888A8C8E511914C0
-:1014F0001824301519282C5119E8ECECEAE9ECEC29
-:10150000EB51298F919395979990929496989A512F
-:1015100029E8ECECECECEAE9ECECECECEB51219B8F
-:101520009D9FA18D9C9EA0A28E5121E8ECECECEA3F
-:10153000E9ECECECEB5119A3979199A498929A518C
-:1015400019E8ECECEAE9ECECEB5119F5F1F7F9F6F6
-:10155000F2F8FA5111A597A7A698A85111E8ECEA5C
-:10156000E9ECEB5111EEF1F3EFF2F45131ADAFB123
-:10157000B3B5B7B9AEB0B2B4B6B8BA5131E8ECEC65
-:10158000ECECECEAE9ECECECECECEB51318F89A9FA
-:10159000A99795A7908AAAAA9896A85131E8ECEC49
-:1015A000ECECECEAE9ECECECECECEB5121A58B9FDC
-:1015B000ABBBA68CA0ACBC5121E8ECECECEAE9ECAE
-:1015C000ECECEB512105BDBFC10706BEC0C20851FE
-:1015D00021E8ECECECEAE9ECECECEBE515E615E9DE
-:1015E00015F315F6152101EAF2089199A1A9B1B9EF
-:1015F000C1C9D101151D041119212935E5D5C5F53C
-:101600003E20CDBD09CD2516CD6116CD1603211F77
-:1016100016010106110090CDE20BF1C1D1E1C943E1
-:101620005245444954F53E05CDF00A3E0528023E98
-:101630000A324A40F1C9E5D5C5F53E0ACD3107EB7E
-:10164000215816010400EDB0215C16010500EDB033
-:101650003D20EDF1C1D1E1C900500000504F4B4594
-:1016600052F53E00CD720BCD7716CDEB163E00CD78
-:101670002717CD5818F1C9E5D5C5F53E01CD720B38
-:1016800011F008219D1601011ACDE20BCDD116FDF6
-:101690007E37CD3304CDB716F1C1D1E1C9504F49E2
-:1016A0004E5453202020424553542047414D45205D
-:1016B000202048414E4453E5D5C5CD0106CD310724
-:1016C0000104000911E060010105CDE20BC1D1E187
-:1016D000C9E5D5F5FDE5E1110100196E26002311DC
-:1016E000E8B83E02CD8509F1D1E1C9E5D5C5F5FDE2
-:1016F000E5E11106001906243E00772310FCF1C134
-:10170000D1E1C90100000002000000040000000750
-:1017100000000010000000200000004000000070E9
-:1017200000000000020000E5D5C5F5CD31184F3EA0
-:1017300002CD720BFD7E2AFE0920020E0079FDE526
-:10174000E1012A00094E0600119008215117C33B00
-:1017500000025617E21701090E216417CDE20BF1C2
-:10176000C1D1E1C950414952202020202020202011
-:1017700020203220504149522020202020202020AB
-:1017800033204F462041204B494E442020205354C3
-:10179000524149474854202020202020464C555390
-:1017A0004820202020202020202046554C4C204836
-:1017B0004F5553452020202034204F462041204BB8
-:1017C000494E442020205354524149474854204612
-:1017D0004C555348524F59414C20464C5553482084
-:1017E000202021641778B9C5CC231801010ECDE261
-:1017F0000B010E0009473E08835F78C13CFE0920BB
-:10180000E579FE09CA5F17211018CD3B00C35F17A9
-:1018100009DB1D0D1E551EAA1E061F681FD21F4480
-:1018200020BD20E5F57987212558856F3600F1E147
-:10183000C9E5D5C5F53E091190A0FDE5E101060019
-:1018400009010704CDFC08473E08835F78010400C6
-:101850003D20EDF1C1D1E1C9E5D5C5F5FDE5E101D9
-:101860002B00091160100605CD77183E28825723FA
-:1018700010F6F1C1D1E1C9E5D5C5F57E47E60F4FB8
-:1018800078E6200FB16F2600CD350C3E00B1281749
-:10189000FE0E281321300078E6300F0F0F0F856FF2
-:1018A0003E10835FCD350CF1C1D1E1C9E5D5C5F559
-:1018B000CDA0043E05855FD63C38032418017B6F1C
-:1018C000228A40F1C1D1E1C9E5D5C5F5CDA004ED2D
-:1018D0005B8A4097ED523801AFC178C1D1E1C9FDB3
-:1018E000E5E5D5C5F5CDFC15CD150879328C40CD93
-:1018F000EB16FDE5E111020019EB211719010400B7
-:10190000EDB0114800FD193DCD150820E2CD2304AE
-:10191000F1C1D1E1FDE1C910000000E5D5C5F5CD6B
-:101920003921CDAC18FD7032CDB512CD6319EBCD98
-:10193000111A1118503E0501751ACDC818281CCD72
-:101940003921CD201ACD2D1ACD901ACD150828EAAF
-:101950003D20E43E3CCDFA26CDB512CD0B07F1C1BA
-:10196000D1E1C9E5D5C5F50D281221FD193D2803A2
-:1019700021071A11504801010ACDE20B218D1911DE
-:10198000280001041CCDE20BF1C1D1E1C954484546
-:10199000204A4F59535449434B20414E4420464915
-:1019A000524520425554544F4E454E5445522059AD
-:1019B0004F5552204E414D45205553494E4720200A
-:1019C000202020202041204E4557204849474820CC
-:1019D00053434F524520202020202020202020202B
-:1019E00020434F4E47524154554C4154494F4E535A
-:1019F00020594F55525320495320202020504C410C
-:101A0000594552204F4E45504C415945522054574C
-:101A10004FE5C506040E207110FDCD0B07C1E1C9CD
-:101A2000C5F50A77010101CDE20BF1C1C9E5D5F594
-:101A30003E00FDB6342805FD35341827FD7E32CD35
-:101A4000940A3E00B2281CCD531DCDAC18CD0B0717
-:101A5000FD3634141528100BC5E111751ADF30035B
-:101A6000018F1AF1D1E1C903C5E1118F1ADF38F3F3
-:101A700001751A18EE4142434445464748494A4BCE
-:101A80004C4D4E4F505152535455565758595A2059
-:101A9000C5F53E00FDB6352806FD3535AF1819FDF4
-:101AA0007E32CDDD0A2811CD361DCDAC18FD363580
-:101AB0001423F53E088257F1C178C1C909002F00EF
-:101AC00000402F3F3FC02F3F3E802F3F3DC02F3F64
-:101AD0003B402F3F37402F3F2F802F3F1F402F3F4E
-:101AE00000F5AF324B40F1C9CDE11AC9F5C501FF90
-:101AF000003A4B40A72838D5E5111E41F51A1321AD
-:101B00003E1BCD3B00201F214B4035F1FE01281725
-:101B10001BC5D56F260029294D446B62232323233F
-:101B2000EDB0D1C11804F11313133D20CFE1D179E9
-:101B3000320078783206680F320768C1F1C90C1F8D
-:101B40001C1F1C1F1C1F1C1F1C1F1C1F1C1F1C1FBD
-:101B50001C1F1C2F1C2F1CD5C5F54FA7280BFD7E65
-:101B600000A720052123411835211E413A4B40A7EB
-:101B7000280B4779110400BE30071910FA71EB18D1
-:101B800017281A79EB68260029294D44195D542B32
-:101B9000131313EDB82377EB214B4034EB23F1C142
-:101BA000D1C9E5A728044F1A180E131AFEFF2819E9
-:101BB000070707E6073C4F1AE61F21001C856F3018
-:101BC00001240DAF3C794E0603E1C9E5A728073D86
-:101BD00028214F1A1811131AFEFF281A070707E6C3
-:101BE0000721F81BD74F1AE61F21001C856F300113
-:101BF00024794E060204E1C9574C41362B20150AC0
-:101C00000C1A27333E49535D666F777F868D939913
-:101C10009FA5AAAFB3B7BCBFC3C6CACDD0D2FFEB96
-:101C20007E235E2356CDA21B722B732B77EBC9EB61
-:101C30007E235E2356CDCB1B722B732B77EBC9E52E
-:101C4000D5F53E00CD571B11531C3600237323726C
-:101C5000F1D1E1C92C7073B5FFE5D5F53E03CD5741
-:101C60001B116D1C360023732372F1D1E1C9606131
-:101C700062637EFFE5D5F53E03CD571B11881C3608
-:101C80000023732372F1D1E1C9626364657EFFE5CD
-:101C9000D5F53E03CD571B11A31C360023732372C9
-:101CA000F1D1E1C9646566677EFFE5D5F53E03CDF8
-:101CB000571B11BE1C360023732372F1D1E1C96694
-:101CC0006768697EFFE5D5F53A4B40B7200E3E07C1
-:101CD000CD571B11DF1C360023732372F1D1E1C9EC
-:101CE000FE808283FFE5D5F53E02CD571B11F91C1E
-:101CF000360023732372F1D1E1C9403E40FFE5D5A0
-:101D0000F53E01CD571B11121D360023732372F1CE
-:101D1000D1E1C99E858687BEFFE5D5F53E06CD5744
-:101D20001B112D1D360023732372F1D1E1C99E6D65
-:101D30006C6B6A6968FFE5D5F53E04CD571B114A07
-:101D40001D360023732372F1D1E1C9BE68696A6B45
-:101D50006C5EFFE5D5F53E05CD571B11671D3600BE
-:101D600023732372F1D1E1C9BE8CBEFFE5D5F53EE8
-:101D700009CD571B11801D360023732372F1D1E169
-:101D8000C9A0A1A2A3A4A5A6A7FFE5D5F53E08CDAD
-:101D9000571B119E1D360023732372F1D1E1C9A791
-:101DA000A6A5A4A3A2A1A0FFC9E5D5F5CDE81A3E3A
-:101DB0000ACD571B11C01D360023732372F1D1E1E8
-:101DC000C9F4F5F1EEEEF0CCE8E9E5E2E2E4C0E8D2
-:101DD000E9E5E2E2E4E2E2C0DECCFFE5D5F53E0B68
-:101DE000CD571B11F21D360023732372011E00F123
-:101DF000D1E1C9CCE7E8E9C5E9C5E9E585E5F1F355
-:101E0000F4F5F1F3F5F5F0D3D1F5ECD1FFE5D5F527
-:101E10003E0BCD571B11241E360023732372013C49
-:101E200000F1D1E1C9CCE7E8E9C5E9C5E9E585E517
-:101E3000F1F3F4F5F1F3F5F5F0D3D1F5ECD1E7E8F2
-:101E4000E9C5E9C5E9E585C5EEECEBEEF1F5F5F39D
-:101E5000F1EE93D3FFE5D5F53E0BCD571B116C1E6C
-:101E6000360023732372012D00F1D1E1C9CCE7E8DC
-:101E7000E9C5E9C5E9E585E5F1F3F4F5F1F3F5F533
-:101E8000F0D3D1F5ECD1E7E8E9C5E9C5E9E585C5C9
-:101E9000EEECEBEEF1F5F5F3F1EE93D3E7E8E9C5FF
-:101EA000E9C5E9E585E5F1F3F4FFE5D5F53E0BCDB0
-:101EB000571B11C11E360023732372016400F1D138
-:101EC000E1C9CCE7E8E9C5E9C5E9E585E5F1F3F461
-:101ED000F5F1F3F5F5F0D3D1F5ECD1E7E8E9C5E993
-:101EE000C5E9E585C5EEECEBEEF1F5F5F3F1EE9322
-:101EF000D3E7E8E9C5E9C5E9E585E5F1F3F4F5F1EE
-:101F0000F3F5F5F0D3FFE5D5F53E0BCD571B111DCD
-:101F10001F360023732372017800F1D1E1C9CCE7A9
-:101F2000E8E9C5E9C5E9E585E5F1F3F4F5F1F3F58F
-:101F3000F5F0D3D1F5ECD1E7E8E9C5E9C5E9E585E8
-:101F4000C5EEECEBEEF1F5F5F3F1EE93D3E7E8E94E
-:101F5000C5E9C5E9E585E5F1F3F4F5F1F3F5F5F04B
-:101F6000D3D1E9E0D1F1F3FFE5D5F53E0BCD571B19
-:101F7000117F1F360023732372018C00F1D1E1C958
-:101F8000CCE7E8E9C5E9C5E9E585E5F1F3F4F5F164
-:101F9000F3F5F5F0D3D1F5ECD1E7E8E9C5E9C5E90A
-:101FA000E585C5EEECEBEEF1F5F5F3F1EE93D3E755
-:101FB000E8E9C5E9C5E9E585E5F1F3F4F5F1F3F5FF
-:101FC000F5F0D3D1E9E0D1F1F3F5F1F3F5F5F1F363
-:101FD000F1FFE5D5F53E0BCD571B11E91F36002368
-:101FE00073237201A000F1D1E1C9CCE7E8E9C5E9AA
-:101FF000C5E9E585E5F1F3F4F5F1F3F5F5F0D3D1B5
-:10200000F5ECD1E7E8E9C5E9C5E9E585C5EEECEB16
-:10201000EEF1F5F5F3F1EE93D3E7E8E9C5E9C5E9AB
-:10202000E585E5F1F3F4F5F1F3F5F5F0D3D1E9E069
-:10203000D1F1F3F5F1F3F5F5F1F3F1F5F1F3F5F590
-:10204000F1F3F1FFE5D5F53E0BCD571B115B2036C3
-:10205000002373237201B400F1D1E1C9CCE7E8E9B0
-:10206000C5E9C5E9E585E5F1F3F4F5F1F3F5F5F03A
-:10207000D3D1F5ECD1E7E8E9C5E9C5E9E585C5EED9
-:10208000ECEBEEF1F5F5F3F1EE93D3E7E8E9C5E912
-:10209000C5E9E585E5F1F3F4F5F1F3F5F5F0D3D114
-:1020A000E9E0D1F1F3F5F1F3F5F5F1F3F1F5F1F341
-:1020B000F5F5F1F3F1F5F1F3F5F5F0D3FFE5D5F52D
-:1020C0003E0BCD571B11D42036002373237201C859
-:1020D00000F1D1E1C9CCE7E8E9C5E9C5E9E585E565
-:1020E000F1F3F4F5F1F3F5F5F0D3D1F5ECD1E7E840
-:1020F000E9C5E9C5E9E585C5EEECEBEEF1F5F5F3EB
-:10210000F1EE93D3E7E8E9C5E9C5E9E585E5F1F343
-:10211000F4F5F1F3F5F5F0D3D1E9E0D1F1F3F5F110
-:10212000F3F5F5F1F3F1F5F1F3F5F5F1F3F1F5F17F
-:10213000F3F5F5F0D391D1E7FFE5D5F53A4B40B78C
-:10214000200E3E0BCD571B115321360023732372F3
-:10215000F1D1E1C9D0CCECF7F5F4F2D0EEEEEBE939
-:10216000E7E9EBEEEEF0F2F4D58EDECE8ED0F2D0D3
-:10217000F2F0F2D0F7D5F7F5F7F5F010CE8ED0F2F9
-:10218000D0F2F0D0F0F0CBF0EFF0D290F0DEEECE67
-:102190008ED0F2D0F2F0F2D0F7D5F7F5F5F7EC8C5F
-:1021A000CCF4ECF7D5F7F5F7F5F0F0F2F0EEEED071
-:1021B000F0F0CEF0EEEED0899EFFCDDC21CD1E22D8
-:1021C000CD4322CDA622CDC022CDDE22CDEB22CD25
-:1021D000F822CDCF22CD1023CD2323C9E5D5C5F5D7
-:1021E000FD363900FD363A00FD363B00FD363C0039
-:1021F000FDE5E101390009EBFDE5E1012B000906F0
-:10220000047EE60F4FC523E57EE60FB920031A3C96
-:10221000122310F4E1C11310E8F1C1D1E1C9E5C501
-:10222000F5FD363D00FDE5E1012B00097EE6F04FAE
-:102230000604237EE6F0B9200610F7FD363DFFF1D7
-:10224000C1E1C9E5C5F5FD363E00FDE5E1012B0024
-:1022500009CD7922FE01200B3E02CD8F223E0128BE
-:10226000023E0906043CFE0E300BCD8F22200610E4
-:10227000F4FD363EFFF1C1E1C9E5C57EE60F4F062C
-:1022800004237EE60FB930014F10F679C1E1C9E5AC
-:10229000C5F506054F7EE60FB928062310F73E0167
-:1022A000B7C178C1E1C9F5FD362A093E01CD4A23FF
-:1022B000B7280BFE023E0020023E01FD772AF1C93D
-:1022C000F53E02CD4A23B72804FD362A02F1C9F5AE
-:1022D0003E03CD4A23B72804FD362A06F1C9F5FD91
-:1022E0007E3E3C2004FD362A03F1C9F5FD7E3D3CCF
-:1022F0002004FD362A04F1C9F53E02CD4A23B72851
-:102300000D3E01CD4A23FE022004FD362A05F1C907
-:10231000F5FD7E3E3C200AFD7E3D3C2004FD362A34
-:1023200007F1C9E5C5F5FD7E2AFE072019FDE5E1A7
-:10233000012B00093E01CD8F22200B3E0DCD8F22B7
-:102340002004FD362A08F1C1E1C9E5C5FDE5E1013A
-:10235000390009010004BE20010C2310F979C1E104
-:10236000C9E5D5C5F5CDAC1821D02311E42301145E
-:1023700000CD282ACD4F2A3E08328D40FD3636004A
-:10238000FD364000FD363300FD3646003E00CDC828
-:10239000182823CD882ACDF02ACD7B28200621BB02
-:1023A00023CDEF2BCD15083C67CD2C057CFD6E367B
-:1023B0002C20DBCD252CF1C1D1E1C90A4A24772498
-:1023C000A424D124FE242B25492470254924242E1D
-:1023D000F8A81E001E001E001E001E002000220085
-:1023E00024000000F92303240D24172421242B2486
-:1023F000F8233524F8233F2400010F00091E001F95
-:10240000004010010F00091E001F004038010F009E
-:10241000091E001F004060010F00091E001F004040
-:1024200088010F00091E001F0040B0010F000920A5
-:102430000021002810010F0009220023002860015C
-:102440000F00092400250028B0C9E5F53E01FDB6BE
-:102450003FFD773FFD364100213400226140216D70
-:1024600024227540CD4F2ACD361DF1E1C9010F0060
-:102470000934001F004010E5F53E02FDB63FFD7730
-:102480003FFD364100213400226340219A24227707
-:1024900040CD4F2ACD361DF1E1C9010F00093400AE
-:1024A0001F004038E5F53E04FDB63FFD773FFD36A1
-:1024B000410021340022654021C724227940CD4FBC
-:1024C0002ACD361DF1E1C9010F000934001F00407B
-:1024D00060E5F53E08FDB63FFD773FFD3641002142
-:1024E000340022674021F424227B40CD4F2ACD3690
-:1024F0001DF1E1C9010F000934001F004088E5F516
-:102500003E10FDB63FFD773FFD36410021340022ED
-:102510006940212125227D40CD4F2ACD361DF1E194
-:10252000C9010F000934001F0040B0E5D5C5215C8A
-:1025300025116140010A00EDB021662511754001A9
-:102540000A00EDB0FD363F00FD7E473C2004FD361D
-:1025500041FFCD4F2ACD531DC1D1E1C91E001E0040
-:102560001E001E001E00F92303240D24172421241D
-:10257000FD363F1FFD3636FFFD364100C9F5FD7EB5
-:102580002AFE09C48825F1C9E5D5C5F5CDAC18CD1D
-:10259000BB27FD363600FD363301FD36460021E50A
-:1025A0002511ED25010800CD282ACD4F2A3E00CD6A
-:1025B000C8182823CD882ACDF02ACD7B28200621D3
-:1025C000DC25CDEF2BCD15083C67CD2C057CFD6EB1
-:1025D000362C20DBCD252CF1C1D1E1C9040A26100F
-:1025E000260A260B26500028002A000000F525F6B2
-:1025F00025F525002600010F000928002900403894
-:10260000010F00092A002B004088C9FD3636FFC99A
-:10261000E5D5C5F5CDAC18CD9D26CD252CCDCA264A
-:10262000217926118126010800CD282ACD4F2AFDC7
-:10263000363301FD363600FD3646003E00CDC81863
-:102640002829CD882ACDF02ACD7B28200621702686
-:10265000CDEF2BCD15083C67CD2C057CFD6E362CBF
-:1026600020DBCD252CCDB326CD5818F1C1D1E1C941
-:10267000040A2603270A260B2750002E002C0000F0
-:1026800000F5258926F5259326010F00092E002F38
-:10269000004038010F00092C002D004088E5D5C509
-:1026A000FDE5E1112B0019114D40010500EDB0C110
-:1026B000D1E1C9E5D5C5FDE5E1112B0019EB214DAF
-:1026C00040010500EDB0C1D1E1C9C5F5FD7E3FFD7A
-:1026D000363F00CD592EFD773FFD362D0ECD5818D3
-:1026E000CD2C054FE60F28F8FE0E30F479E63FCDED
-:1026F000D42E28ECFD772DF1C1C9F5CD15083D206C
-:10270000FAF1C9F53E00CD1327F1C9F53E20CD13EE
-:1027100027F1C9F5CD5818CD2B273E78CD882ACD85
-:1027200015083D20F7FD3636FFF1C9E5D5C5F54F53
-:10273000FD7E2DE620B9FDE5E111420019281B06BA
-:102740000436002310FB217427112850010108CD05
-:10275000E20BCD8A1DF1C1D1E1C9444D545D3E0467
-:10276000CDC103217C2711284001010BCDE20BCD07
-:102770006C1D18E157494E204C4F535457494E2079
-:10278000444F55424C4544E5D5C5F5FD7E2AFE092A
-:102790002813FDE5E111420019E53E000604BE23C1
-:1027A000200810FAE1F1C1D1E1C9FDE5E101020023
-:1027B00009C1545D3E04CDC10318EAE5D5C5F5FD58
-:1027C000E5E111420019EBFDE5E101060009FD7E9E
-:1027D0002A07074F060009010400EDB0F1C1D1E15D
-:1027E000C9E5C5F5CDA91DCDB512CD012806783EA8
-:1027F00000CDB004CD15083C10F7CDB512F1C1E104
-:10280000C90D210F28C83D213328C8215F28C901DF
-:102810001F000F1B282728010C4840504C415945E8
-:1028200052205245414459202020202020202020A1
-:10283000202020011F000F3F284F28011048305052
-:102840004C41594552204F4E452052454144592054
-:102850002020202020202020202020202020200197
-:102860001F000F6B284F2801104830504C4159452C
-:10287000522054574F205245414459C5F5FD7E46DC
-:102880003C280F06FFFD7E32CDDD0A28020600FD42
-:102890007046C178C1C9D5C5F5CDF828CD3729CD49
-:1028A0009529CDC8182842CDBA213E01CD2717CD94
-:1028B0006123CDC8182832CDBA213E01CD27177A21
-:1028C000FD464104FD364700FD36410028E13E014A
-:1028D000CD2717CD7D25CDC818280ECD8727FD7EA5
-:1028E00037CD33043E64CDFA26CD78292804F1C1D2
-:1028F000D1C9FD36010018F6E5D5C5F52119290D18
-:1029000028092123293D2803212D2911F8480101F7
-:102910000ACDE20BF1C1D1E1C920202020202020E6
-:10292000202020504C41594552204F4E45504C419B
-:102930005945522054574FE5D5C5FD363500FD3673
-:102940003400FD363800FD3641FFFD3647FFFD36C9
-:102950003F00FD7032FD7737214D40225D40214D13
-:1029600040114E40010A003600EDB0CD592ECD3356
-:1029700004CD6116C1D1E1C9E5C5F5FDE5E101026E
-:1029800000093E000604BE20072310FAFD3633027C
-:10299000C178C1E1C9E5F5CDAC18CD732CCDE127E7
-:1029A0003E02328D4021FD2911032A010600CD2867
-:1029B0002ACD4F2A3E00328940FD363301FD36369E
-:1029C00000FD364600CDC8182829CD882ACDF02A2A
-:1029D000CD3D2ACD7B28200621F629CDEF2B67CDD2
-:1029E0002C057CCD15083CCD7829FD6E362C20D5E4
-:1029F000CD252CF1E1C903F32C732C242E60002685
-:102A0000002400092A0A2A142A00010F00092600BE
-:102A100027004038010F0009240025004060010F05
-:102A20000009360036004038E5D5C5D5115F40C5F0
-:102A3000EDB0C1E1117540EDB0C1D1E1C9E5F53EA0
-:102A400000FDB6352006210A2A227740F1E1C9E5CA
-:102A5000D5C5F5215F401140107E230602E5230E07
-:102A60000507DC7C2AF53E288257F10D20F3D11AA8
-:102A7000112810E510E9E1F1C1D1E1C9D55E235675
-:102A800023E3EBCD350CE1C9E5D5C5F5217540CD86
-:102A9000C51CFD7E33875F1600197E23666FF1CD5E
-:102AA000372CF53E03CD720B21C52A1118200101E8
-:102AB00013CDE20B21D82A111010010118CDE20B21
-:102AC000F1C1D1E1C953454C4543542043484F49D6
-:102AD0004345205553494E474A4F59535449434B58
-:102AE00020414E44204649524520425554544F4EB1
-:102AF000D5F53E00FDB6342805FD3534181B215FA1
-:102B000040FD7E32CD940A3E00B22010B3201F1843
-:102B100008CD4F2A3E14FD7734F1D1C97A07380722
-:102B20003E00CD402B18EA3E01CD402B18E37B0739
-:102B300038073E01CD962B18D83E00CD962B18D1E4
-:102B4000E5D5C5F50FFD7E333826FE0501000538B5
-:102B50000301050A3CB8200179CDD32B20F6CDE83E
-:102B60001ACD191DFD364600CDAC18FD773318215E
-:102B7000FE0501FF0438030104093DB9200178CDA9
-:102B8000D32B20F6CDE81ACD191DFD364600FD7772
-:102B900033F1C1D1E1C9C5F50F381DFD7E333E09C2
-:102BA000FE0A302CCDD32B2027CDE81ACD191DFDE0
-:102BB000364600FD77331818FD7E33D6053811CD23
-:102BC000D32B200CCDE81ACD191DCDAC18FD7733D1
-:102BD000F1C1C9E5C5F5FE05380323D6053C477E9E
-:102BE0000710FD3E0038023E01B7C178C1E1C9E5DA
-:102BF000F53E00FDB6352805FD35351825FD7E323C
-:102C0000CDDD0A3E002818CDE81ACDAC183E00CD27
-:102C1000882AFD7E33CD3B003E0AFD77353EFFFD21
-:102C20007738F1E1C9D5C5F50150C01110103E202B
-:102C3000CDDD09F1C1D1C9E5D5C5F54F7EA7282E57
-:102C400047237E23A1BE232008235E235623231877
-:102C500009BE20142323235E2356237E23E5666FBB
-:102C6000EBCD350CE12318041107001910D4F1C184
-:102C7000D1E1C9E5D5F5211E2A227740CD932CCD8F
-:102C800031183E00FDBE083804F1D1E1C9F1D1E1AF
-:102C9000C3242EF5FD7E383CCAA32C3E0032894069
-:102CA000C3D62CFD7E02E60FC2D62C3A8940E6013F
-:102CB000CAD62CFD7E02E6F0C2F42C3A8940E60228
-:102CC000CAF42CFD7E03E60FC23A2D3A8940E60491
-:102CD000CA3A2DC3802D3A8940F60132894021EF4E
-:102CE0002CCDE92D210317CDBE2DCD591CF1C901E5
-:102CF000000000C93A8940F6023289403E0ACDFA06
-:102D00002621122DCDE92D21162DCDBE2DCD741CE1
-:102D1000F1C9100000001000000020000000400079
-:102D2000000070000000000100000002000000042C
-:102D3000000000070000002000003A8940F604323D
-:102D400089403E0ACDFA2621582DCDE92D215C2D52
-:102D5000CDBE2DCD8F1CF1C9000100000001000087
-:102D60000002000000040000000700000010000046
-:102D70000020000000400000007000000000020081
-:102D80003E0ACDFA2621962DCDE92D219A2DCDBED4
-:102D90002DCDAA1CF1C90010000000100000002079
-:102DA0000000004000000070000000000100000072
-:102DB0000200000004000000070000002000E5D52C
-:102DC000C5F5E5FDE5E111060019EB6B62C13E09B1
-:102DD000F53E04CDC10303030303232323235D54E2
-:102DE000F13D20ECF1C1D1E1C9E5D5C5F5E5FDE541
-:102DF000E101020009EB424BE13E04CD092EFD7ECC
-:102E000037CD3304F1C1D1E1C9A7C8E5D5C5F5F582
-:102E1000970A9E2712031323E325E320F4E1E17CC4
-:102E2000C1D1E1C9E5D5C5F5215F403A8D40874F55
-:102E3000060009113500732372CD4F2A3E00CD27BD
-:102E400017FD3636FFCD592ECD772ECDA02ECDFED7
-:102E50001CCD5818F1C1D1E1C9E5C5F5FD7E3FFD96
-:102E6000E5E1012B000906050F380236002310F8B2
-:102E7000CD5818F1C1E1C9E5C5F5FD7E3FFDE5E19D
-:102E8000012B000906050F3810360ECD5818CDE578
-:102E90001C0E1ECD15080D20FA2310EAF1C1E1C960
-:102EA000E5D5C5F5FD7E3FFDE5E1012B00095D544B
-:102EB00006050FF53815CD2C054FE60F28F8FE0E48
-:102EC00030F479E63FCDD42E28EC1213F110E3F163
-:102ED000C1D1E1C9E5C5F5214D40060EBE23280D3F
-:102EE00010FA2A5D407723225D403E01B7C178C1C8
-:102EF000E1C9000000000000000000000000000028
-:102F00003F3F3F3F3F3F3F3FFFFF3F3F3F3F3F3F51
-:102F10003F7F3F3F3F3F3F3F3F3F3F3F3F3F3F3F81
-:102F20007FFFFF3FFFFFFF3F3F3FFFFFFF7F3F3F31
-:102F3000FF3FBFFFBF3F3F3F3F3FFFFFFFFFFFFFA1
-:102F4000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF91
-:102F5000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF81
-:102F6000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF71
-:102F7000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF61
-:102F8000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF51
-:102F9000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF41
-:102FA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF31
-:102FB000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF21
-:102FC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF11
-:102FD000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF01
-:102FE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1
-:102FF000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE1
-:00000001FF
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/swap.exe b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/ROM/swap.exe
deleted file mode 100644
index 206d6afc43d2925b9d69ab4e689781962e7b5b03..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 57344
zcmeFae|%KcnLmCfbCcX8lgt1K1PwCCsA$ke14<mw31mW0f)heAL`VWF(2ycxaxb8p
z;G{QWb91;#cWu{pZC5_nE^Xazx3w;9ttJdjz@LCtskq(Pvi7DIHA+kdiQMn|Id>)m
zf9!WZ-`9Ts6JB@jx#!1op7WgNJm)#jdCp1YoqGhQAP6EJ%MyeGc+<ZC|NZZOhLD^y
z^Vd1TQyDMKI^bCT(yUcYn_IoxTJHI3%lf;$cdg&L^&Z*#Hygbz%2w~@t=_Ubs=asL
zvti?P+1Z)C1n8$m-@0_@+dr>JKCJuMiVyJpFHild;$ys9yPv6en|~juIE42PwY?Q%
zc>m~^dn-P|d+6K0sCXIgpCbPmy#E#N5AnWf&r=-E%FTB*5$t43LP0@T?hu6o|7MgV
z;|2t`Bg>H{2oc0=vt!e*#oL2t4}AyhFusXS^e_1q1c#l5IHDu}pmJ20zsFw`DLnqD
zAcQC|Bna^w3j8nq+k<+5$`}2+PTsgvM&f_nhabW#l6d2l{O1*fb=S3QSTC;^gn5J;
zU|yg>G8d;t;5s{-@JuP<AIDRac;l7)7Z8M=>sne{?m`4_>ktA|_fb3({ssPL>^7mq
zm%%S7@FfMlq`;RH_>ux&Qs7Gpd`W>XDexr)zNEmH6!^cT04wu}9j9qI8|_gt)x%cD
zA^M2vyL}Sg`YNAL6<TS$FijBDLoU6{Cp6KLx9QQx145`-u=2!j2880CM5#S{s%zL5
zpQ|>^f&eJH8U1F2ti0hp0l`cu?g@m9`|<^WDF7!%N7xDZ8dff%?#ozO$ap1>@X*Rd
z#jV~V$eB$!LVCoA=c2%N5yeN?dG&}@+*AGGPe+dxo@K|_C_C3Xm~!R^?0NNV=b0yr
zT^v!7y;N;X0xhbIzp*148|v4@_UzfyY&DtR2nZYY5}`sHv@7Uc1$@u4o1!D~Eqb{G
zY`cIhaJmLDSF$uTAsvxph~&7UK}MDhw$@0o1O4d)sM%%wBfi-X8mGxVDLT?$<^%SE
zAP1}2TA#PNzZ_H*g#L1g7VE}lB%;A-N>21-vbh<E({5t@YZ@Eaa-X<C%cc_QA<sck
zK!mHfM@wh@jSUwiplSS{-7vKBsxEX;qJ15wskZ7GH1iqX90ZHs^?%~-Jc1B=%r_S=
z|9`kUe~q`c#phwg+LJynMSdjDxQHIvh{<Snu$PTrQr<$Xklp0}sK1lvw(w8Bs${FE
z%wRcHhKN@9e@9)JQ*vFhY1d8pbWei8a_!D+zK->xJ3qF&^DysDeYr2c%2;p-O2ySf
z5+R+7npv@aj{|)(ORtqyj`vnJVr=ZDAx}TI#-Kwor=mcjLp%qNB1A_t8)f;*nnZtS
z<&yCqlM{V0Ir^@gW3yg6;)w6G;=XhtK|J*(D?uR6GP5ow(Kr%+hnmK@A_~SHM*>`7
z*Pntc@(pNYZUT*}Bwth|ahXa4iXKnm^Dda0@Tmp{KI(&;jP5bZ0=u!@zI;RwpC=fj
z;}Fq`n0~^)TK2)`GxW{qFMt^-^GOalqt>{_{$_m*V7m(dz*!r>Sr?C=j??Q<6YKPC
z!>hWc_#~TC>o>KvJ`eaQU(VDkr79~=+7l4M+GD<*$mBQWt4r!dWhSc;RvIVJDt}B1
zV%V3|j}LnXVp))eeGf=fRD~fZ0)!g3+?`}~gXqcyb$o&5%#|Un%;z<tEi?pK+?WdF
ziQFCxLa+Z!Unj5BAzvBR8pI@x--Rg(wWcYP{pXVO)e%SZ^`Ggo5d{E`l8{5&kO&Fr
zA+8Knf#6-h0<a@^r5MN2nQVxq`D1dX+Cx%=8jOafvzLq-bT!6qKD*BU0%%eoXBdkS
z1rp_>8J<LC{+PS-Pv<QQsB-`bF_i5;lVI#ykVs@5d<Fr(*$C3s&<LQK*i*hXqDqec
z1v%X~g`jpBI^jC-nv4%VJg4cw3F3_g%S*;zKS71NeOr)cBJa>QcnAIc-Ou#5dfHPB
zSyEDbQfu>h{O5pDE>KyTY;?`DD2$!}@#Y%clYx{$0uk-@n|)=zIVtYW-ywshNNhe$
z41iECVzNjF?J!xqj?VO$A~h5=o5vi8&SK~*ITeZQ1Y3nZm^VciZ{#yj91tKwg93!;
zh`iYzxQAfBj9RkDZldl){0xBduy#RTo{_?iO`J1Wn=cogFptkwA}dN1@Paj|Z}jDt
zrsxY7e@>Z?icfN0IaiN9e#N+#7+|e$F2qYQsKF-^>KK{=h#t`qwB0Aj^Yj%o91@-T
z1@p^Kz-ypct?_^C0I)A;WU+?i;8qV69F#CFF`mQvE-5???<;8Q7r+cBVXm+Pjm13;
zF_zxgFhNFuwqkc?<ZNk6PUP&JJ2JX^#f+W-(G<JOd}8G6`W9E@?EO2^6VZ{gMJ>o&
zvLm(UZLzzz`!)xaM3y^|<yhpeH>Dh$PzDiUib$4;3>KyIqG3|^(UIfT-P6w>OnI|w
zI-jP;1<v?<c2dK9M*T59r#*%Nq{bb!VRz@>r&2J*{ctw|kV6NMRBVAcU2L1EJ>z?l
z##)<CB6h{-U57zSQ7Kim<1z(2SEiKJHu?TfKrr4JA(<*6tA`C4O#q6ZWHj0Vmr+aA
z^kIJ9?ISG41@3-)#2}NF>z%&G(dR2eO(I^X#REn_Q<wKS2$ajn1q4h^ce{Bvqw<CR
z{sdM|d6NDJFU}6HG_tTS0WRxdvabxv)wM1FLdK^EeH6<rdB)cX=8`W#m5(40YFb4t
z@YyXGyor=JG{e}304f~AxS+9EhOtN$5*!f~?&gK7*kR+lz>F$H77v<|PZDos2w9(@
zDvf^}wJgASio<bT1Sb_zG=$0lq$UAmybi*3Zc>n5mBo>oTLsJtj5=Tz?Lly^`;nM&
z4)b>BNq1)_=!SZhe-6HBsAsud&$}o~$X--WQL>)rGEol+i!xtmWr!+EG$Y;cowF=N
z6d`$C)k=0aksujac0xW90uvH4j1NENCDs{rzz{`4M#v5nCCHd%+=>X`{3sN*Pt!OD
zIG5QtmwX!MEYN0Q66Y+!nTs9Y+7KsD0yVd>jWAf{TZqbiE74Vn1dkE6QCn*~i!MUy
z!URT>jensC%#kaNC2@%PPTy{U=a>^hY(>>d<1|oK57D6T84<g5AW=HSxCaqv&tcbR
z+mnm-1nl-~28hq}!GdIa{29DG3s6IT$haF2d0#J}zINklLSL`@oO<#u^tI#j>ZwT9
z^Qy!fMl8FbY9(q*_VrX_!CBsO6-Zh=p-ZP3GwlTG>v<Cr@{Ke*VYP8LxDc>57#r+B
zMS?b$7}Yj^J_%O-bYIT^&I@eXRHB6!(dH8L^_(QmGYMzAugfm#>&uKzbQjQ?gUY=V
z`g*4EHA-0SE93eG0&@}=%`$qaYgZw=5ys%Z(APfd>xJm+pMml0zV;d<Do}dfcweiC
zAOQt@nnG39@7a)l)E)hPVl)^V?ED^Mjh!#I-v7!PIn`(brDz^upC<{MPCO1#^qmj5
zf<dwoluF3T#)ghVTw0DxdOPrczY^;Jg8^=>vC|INI(KqX!;B%;u&ZlXk^em<y`i|L
z9_noLT}5iZT9=1Ml*|UcETAteTdSizVI`ZTHIANG({L%zkF}`cYFslR+YC}$Le{G+
zhsCR`SN(DJ%Jvj?m{f)v*&migPj1iO#4g#yu2cI`)PpIT{Qsfk@%SBvKi)bEuoBf5
z_cU%|<>%M1!^J(D*y8gIg}sDF@o|5=agF<12OHQy`W~ke=tHyG2jNdGB)ym>5(`Ny
zx!UT15T;pbVtJy6dKxncC=wkBUs!!($yQ~<_|)qAeu9!%eb4Zr+08;z1WeHEY^ESW
zky;R9m2WMJV}8wNH$VfKxTyaa06x2@pM3#r5}+dqFhBr@ROq_0FW22^VyLO-q4oa>
z0ccq3s*U*=Ip}n7u$LLlLREE580zIVE6)oAqdo4<24pS4g4-QkMTN?I>xxhI8eFHu
z2wdmxJW5Rvs+&n*6g55he*yyO(J*GPSoaIPhBR_?<k%H(h!8s7reF0?Zt;lzjPxO(
z>05l)0^-`@<IY%jZqdr7Cs4X3QF@iHsrU#?CFQy}Mg3ihdfwB$yvQ0ornk8rZAUu(
zLcsJg`Py*PV<<(d1gaCu6f&<sY5^S|8q|F4%33w%vGNLdgXDI#%~x=(vK{r3QoJtU
z??pR2?yoO^Vh@(chuLLq(;k2XkU33V2+)!XunF!ez=iJF428tX%Lhbcnj0eRhrrhu
zi_r5RXP7O@#kciFt@Q>Ll6+LGQ4f{HsI?(u8gilT0_3bRGi!|W&z1rkto{rGoQ2^2
zECXDQ*aTnIHf;mG#<q94)`gmjdw8|rdejX26xl33mu0{IxuE+YYLYCw=!;nP4fcpH
zK)i7R3ysfmZQ18Srui!Y`SZB;4J>rdS>VKZ?#@Dzcb|Z3FQ+n(`O2sbMjNrc%xQ=|
z@Ub{CZx|hsWZXxQ4UFq^M;}56mIn-ha&(|)WgoOXK^Jcc8R20NsxJiq@~gU_SLwO8
ztTYxUBC!w->8@L<jO!B-m_=6dVqQdWmR1jWRYQ=oE0oIQ;>27+=BeU$JN`@zy8Rjy
z(C0OnBIrLC^?1~tlqy<e&okaU!+WW#Z0>@f-)#9K7;j#pd4$s{-%Pu<pCey4FoYg`
z^I>2)N1hGl@qk0-*h8x0PgGUa%BErJ{8p2|x=>#(EN@>SY{0TbHa^V)X>Wn*DvYwk
zfVdV!DpIaW)a*agniW}i%gu6Xx&KVdM+qobB06vIS*(@A#+}4&7zbe9m1dyn8LHFz
zE7d86jYWw>HlO&PvRJRzSg((dfsRAOfw8cWi;PIFwKMWem}nOwk;Lf*u?K1DMC50=
zelD7PG1uSEk&tYzPgFE6?)SjN3Ol0lAb>%P8{i&ca58?HGn+&qCGxAH7tszEA=mW!
z6$r*580%t96m8`Vp)t{(b{JNF2`Le)VW-u0NvI7gVsVdIZz+;34A>Ba)s1S8(>G=m
zpgbF^4L4gz-lSdy8A(>&xg3&mIh#KRA?tORM02dyuON>xD7)zq(s4q@9jFB>(bLGH
zZ;YcwK-o437oYT-yw=9raE<W@D$(17lrYx^*-)MTOkGkZ$^wjPjEH8drn<W8GApkr
zS@j}b^&7nEH$GkUYh*UTTvxvab=HPAK_q(E2b)yODNn_3CjZUC%orw%@(+=lVwLnw
z{b`wkS%8l$WfIuNwMn~W^u(n-n_v+%T}XA(<l({>pGhTwh<Mu5Ea;U(mf`}D46IND
zJvh{~=TXRWBaH}H<^zj-pl)&rFo06|{<K_(VqynL&W->#K~7^ZmsE*lU~>t`ZIl9z
zZGKCyHGYDRI@|b`fW|6BZH34Jk_}dh_Sirt0z%Va-z%4r)g{s-w%rBpOoy162WmEO
zPB`slL8;bKJX+Auf&+SR0PX1yo?eWa`-7*@4G)BjZ=f|8l~&~`HndY>!GVZZFtd>t
zmKUQ2Ht#w@@<<F!DjFMLR;VM`ReM*1|EkgHF|B?~nT3kj(FOVP1KhIE28+R+52QwV
zy<M4$7hIzJ)%+^>%~4%l-E2KehCL9qHe~oFgOITLdSRVg5H{|DHP9cc(}H92HOL$e
zaSpAu=2KP1C{mFXype4wW7I242$?#37%yRs4GiiU8`d0&H9Potx(fO0Y+T8b6?CaR
zE`Z*^W}x)~b8gtj-@v=x#qJtocaK>ER30{$)pg$xebzwYMXjv@2-{Af1>^m}v8Jm@
zN#fkWQ8DTX0T&C1zE4=CODh%a+^jyXIX7s$$^>xET_WI(0UHddP>44t7u}TLwzX4u
zOSNDwim+fV`>%StJ9DWO8&3<YQqqFMNa+s_O}{1}1hmRHHEl1oNDH3Uqo>igb^|RX
zzY3s@v`c~EVHP}{Xm{@sf;k3=ki6D5kF`yr2I0*){sg)P)J{}959q2JPk?FO`VjT8
zU_RIhMYZ557AydFv7i_AsvCy{b>lFeIG!<NA3B8W+Qwn+?syWr6MFQ-IClNP7r_nG
zcUtf$3xZK!(}PDt__m6yyq)Oxx;k~^i-OudCdkvq`;OJ07$>Wl!Gb4}o%tf?05pu~
zOFS76)qzdm88@))5BR9EX2)u?5_Zv`%i2a1MdSIe-F_bAB>26}aEMTM`UE8lEQby<
z-X&uyu}lH`n%BB3AK*|aClt6uZFdP_)-JIfF4pK_eK3HcXWB}j+$yQYY})3i^sLau
zr%RTrqAsfKss0LSS1KjDsMX+|;1~)Koc8BgaEw*vmTT9u%6!e?U+UT+`iHis8Yibi
z9*IvkHUI)R{>2yV7T0j?daMxQ8^dE2)^YX3L0}(D%i?IM2yIT_Dj(>9T>wm$9xden
zCOjbqf+5NiYChj2&V}{gnvYnRy{@1aQoL-n#J0JBsC=DY_W9&F`n>JT^$QJFGp)j<
zw*5jBl*vsFP?(kdLNWp<X07^#WX3i;Oj8=k7$6fX?%BZjZdb>BB2}b#Se1*dbd^*|
zN-D=KR$cX*h5G`6nVAR>yWcKpOGNE!t~wI_FJANyZ6}Hs_h8@f!=ILp{^5@9pzD(l
zf4X!*x=gcR3hN(h<lGKRcRplv)AG=#w>NBax3<x+@??n5;^W<~X?c%={n%k!lhLvt
z!B_9wlJj{jdk+N-&%WJwLr8X94oL%zMrtlFzKfQEW5)#J_L(3+-Zntnci?TvuZ+tC
zVP60xjGtpD8pB`(V>9+i_wGmBz9;b$vgSXImo@(}%JpAdX`mq%GPcrwYVb6ZScX<P
z5UMh600Tg{F(9lA80(O%E~-GO6s*^aW}{*f*6R>xA_dIK3xS@<e<4#=GLs*Hx<sy>
zKsNSb)gtoXg)%0!<aP{F_*(jjI(U5R>B7V8P}ITR1~vgP6oY*J+1rHgmB2BNf^{tW
zNxawxg&(SYqQ9@9_2!jEAClD`58B9cPxEn(0M#5ZJ9}X^CG4Z0-m@vXt4p(?V4~F=
zYAQh#?MbK`;)5pey3rFAF}_eW=D<c1?WyCXmF(tx<6TVudpR<ySKxtt1c48PO=^jt
zm!`;>o0umM*c3gkj1=}Bi&w<@9dp1QY?&B6BBxgwJ78_7i_yIOXVf@8Z=ZpACNXb=
z^;CP34L3`5&laJy-ac^V2bd%vHZYR);4s8H)QD5)Co8WF1a54gDTWVNhB066Vhx`C
zUw3z&K}YQmxT7Y$9r9FllPK)>xI0hco2`(1=d~OSnaf?2pl);tzV}@zn||bSAXd4&
z<NVMQ0YR2J&U=1<L6uc)EV!DJM1iI;I0p^cG+OSG9AS9_lm~W8VO+0pXgO>}{<5eA
zrDK;T9I7^^T*Z4u3%bl=ta9Y3EXH2wji;(_&tzis@c}eXJZz>OC_-H$0nsaGH>Y5Q
zZIn{yLbETIx+|qF$;@qbU>mBDK=#;409n%RYLwH|6)vv{X)N(&iYd9gz#o>9gb3|8
zU6F!C6ogT`t9Yb)=F-lSnlh{@r?qyMyK^`Vw5S{^K5j~QG399S@sgU;?%i)8K61|6
zHYIXy=L0$JXJg$F>I-$iO<Jq_+0MQYK6~S$8c)YW<Nn5XQNZ#=U$_aGpyg>bFKRU>
zw3-2}=9E@5rq#SPxDz=5NHx5&Up1WawW=Y>Gb<|O$@p?d>yWHgj!A<dJ0K1&wF8d9
zTM&p;jztFN+c7DFb1CNBHOg!~=m{Ag;S0Qq8Pu&$wzG(%C-6B)@)-)4``H(CF`}21
z9yJHGnxVmWAwQ}3WxV*)$>Kw9{Z*t8{)5jWpo<!nL@_NmG<bj)S|(o?IoBk6Bj>ir
zlOyMLxTB9#eB~$7;6L!PW1hi>?0|PLN=digsN_Z-aLiM3mM%rU2<Sez1qoWsQI_5G
z&zQ|?-f}-38!0PwMC9pu@HF^a0--|21IX1q6Kt>)WhN$ULIR=(ufUr~8vm;M;R5us
z8sF&FzYX?Q<Ez~d6W_Z#cT&8u#NGK%_yo1L;n|`ZE_Za$DF~ZJgJVUKB2ojGGQ=m<
zXE8P(;FNg`@F|B!s$++t61h9iV>XH&Q8HL|1OgCIP+$-xzzyN`7187F&e!m@NnL=7
zpGPPVF#nR!NFp&Wx;LQz_5h}P|MOaV+^xTYl2B<te_`+#ekNjL*Gp)~exnG8g!CvC
z4H@~#F*S^J+711|6NG?ywQAfc-=G>9^6x6#od)6tB{a}D0RwJb7cbf$9Hy)`97vSG
zzkoKpp_pokgXCf?7$B<Vjs!oE<Z15bgkuKR1cwvN9Q-9wbK_goa-<IK!{^?%eV{}z
z9vXZIz!g{I+*g%!w2G>N0%j>MVq;pPz!0m5Yn2CB0E+4})WeAu>A?dqF@^p)02iMz
z7|lA~iJ+{UtF{kee>RcH%3F&Jbp(BKbYw#GDjv<rdaaU;j&$h1{S^oW3Wtq*uR!Yu
z$AF7!Y<71NkyRtr-T8e4K&DQ5$yGD}J3m303dH>z&w~+3t}gw-*FbH-TuAbK@F~RD
zz0ccR8BcV(EJYRwvNK?QP}n>8FfTSFp%_Z1<24c-i-7i+@&viQJNQ~(@UKN;71m3j
zp3oIE&5A@0DkJ;RgcNf=@0Ux_gGlq%$r+ni<>^hDWTxV+Nr_$`oK5`!wgPzU0U_@v
z5g9`TLg8Jc)S0DJTAqd90B0p^%uu}hxt{NsR~WQASLgos9`nQT43hEByx@TGPxLN6
zPAT%G(c=$HYlF*G>!i^W>T&oijJ`>fW*@`aGsHfodKIVo7pT=kLVHG{_e~Lc%P8y1
z>Q@jt1y=iaK93Dql|#{<2hu1-_OsydcUFeNwOX)8t2t!MM2}g@A$CHI6<JD8xYqa{
z&Ftq&sGeO;XZ>p|7`H0pUHRrO0k9As!8qzq!2(8}&MM=Pk|G6|D%r>sz;~ac2uW)D
z3Bes528~$#*hnlOUpdn6kkil=*P6K_F*{gjW{kvA<SfK`(LLx$aO6Ota;i`n9*Mb>
z$q6A;+w3*SUr5C!803{6{3}=Gp;z5t$Bx7>d`4p8gc3!@e*qjysO@hFa;e%rEbOAT
zV?n3yv^Fv462LheT4I#U2Hi0jcio^@p2kW`;_=1_yEN;+18qBM<|R<ElwnJW8^5+w
z(OIHA5zBiMrP^Kg%!fHIItAM=(EXr0ABioyAt21WJ|NtT=RrKb#q&EnALG%H2CV|C
zPivXDGlxy;4oY1qmc#vYkC{b?8C}@d#d0bRa2_R9m8|-hCDh0GeuIZ&x@#5;m-)5O
z9`o_!8c#yDLUOCOSa5%!rabUx?7EPfn~TM6uMJ0gc3lZGOaV%H+|Q<k%TcNzWGIPZ
zw^Fg#?I`vqQvJ!wp$Z}sAW{+^5|qf&IIBv2BXJX@q9IkaOo4ZueCOV-fdHlmr!uwH
zxZ9?7t$bt1*iGR&^JaJjC|8o#iyj;c)fzu2qJDE>%{PgrCNd8U+EJ#v7E9duod9R$
zMWBkos)3aRZMR5fv;G7a7aU~KS}8o*i?J-o?rukEXOHZ+Ka~%d<JZ>t^Shi!)gi0+
zpxP_`NN_khWP_ECA=~WEQ}QK0!hjIu9K4`~r<gD4_gOHf+;`rT^!q+Bo%(%asKAwg
zKfQZWY3FfyL)WyWi7MVRQ?+SozsT!hjzmpt(s*5OBmcb45&5dogS@86^yXFdYtv{|
z*BIMm2l|$#2;(1(v93g_HQ#tCVA~w2jkGLi^N9mHF6WDe0z`qGm8m5FC3|>Wtk{nG
zV{uQ6_eL!`T%s<?^Uq&*G$8D_wbr;2l7J?qc@3E1Qxw`hfdNaF^lfhSogvfN>}l}N
zf8q!-&t!errwJMV@D&^EWhVUk6lb%eLG7cw6MCtWdWpCJOShxn{DP%h0n|k--HNS}
zMa!`UQp&@yHLa;`I*bC`+EfdR<!(SCbhH_i$Gkiou5LPn43sADG??*eE=Z;H6i}h0
zJ$DzTK{Cu3-$zOvRJPo`luGTJVJQW$t=Q?d;l>6u_(zn5(~3L#DhJ|Kq`gfjqy@d<
zu$`R+eYAd22c!U4)N9*bu}M*X%KxA4&c{$pYai3aOKp4YmJcyIZZy~-E%+8D56hea
zlLIaN;QrFiV_5yElJ>XcP1Tn2mR$pEU`e=WbR`<glgO@NlY$Lt$_f9de8WgETa*JO
z?FH`6pQB>GQt-fKcGEsx1bc4Lhmi%odK(Wz{T|=ug<yh73>1P2ny@h+z=km4{FYWf
zz;T{Dj&t!zieRYyKjo)tQ3;kt!1@AeK=?7>6NU{t95&NzWNNFMyyz6(Dl!-Iz3a|<
zA!u0N;1+tVf;|HQCVIS9zs-UL7E`<wU>__4Yn{PIgOXZ^<QO|h>;&18AAZi8`uEdI
zZo!h7VJgRx1WTGt@=SG?D9HDy?FE9ex!HpG6dd3(axhjf9hkN1E|(yOIu_j3diQ`b
zw`6DT_N!P$0b3?P6Pw|Fy2iJXkW>onf?yz5$T|j7nmN;sw-n!mB!lz-q;e}#!rGRP
zwPS?Ld@uyZEhzJCSncHdOU1TS<85dt)g&2zL-i+`aG5)LE6rrPJWi#yWLK_IrS1au
zx3l@%z<ALScju)@-Yesy*@2nc(-%DLFeFGtnz>+?Vt`r#C}#;7g5n`4SsY5Lad#q>
zR-%;Zj*?=A9Pa301X%l!9yGZ01%IRI`Nk0JkI)R^#}^#)2MxE%sDS^0Hviv>5A0w|
zVCR$A63A#w^}DbjEnoqcz7xWqV&c1ITH6b(n`p}NQ?p2zE0;h&fLJUE#vgdwsvK5>
z5~k*1;emsu&r(i<sHnP{7n(RKYmH2Bje2M<khFqhYAknfGngfU&XqGk3u9d>4QxKS
zQY4{IkocPY!r%rNYCAgd_k$VG|7m)vQWueZ5&}e?l`M3j1R>wcEjR^0zLm8X=+L=o
zhDy@tMZO!B3q6Tw6mPx5e@ojE|1R-?TgWD`!qYn-I(u2gFxV<Ba-Sq9S2jD;o*}y`
zh)76|i>vc;TFs?q_T`#Cf}O#h+FfiZ6fF6+$WBSnLy}xdvo%{G`g>)M+AG0p<hywZ
zPPlv|4Hl%4bV(+k)m%n~2z<g@cz=qVF_NCbH+UeaVe(8!W#fyavdfmrtX^WRlBS$u
z?H<39E7xGrwky@YgP55-<j7XWmSX4*5t6PZ+Ec5>{wJ0=TyR{1-Zd~$z!C$I$3;iG
zhkybiip_%@J7xY*YbArgM2SSQfC=_6m7SQl215Xej#JycLN%)|;3fu4a9|sBiDdj8
zCm)z<u7FR)88)4kGS@i&7swXy#Emw&!$v9zn{u(q-o}^{(3VP8E2I}X!@~hh;jA(j
ztw|4uj5d@9d-0)-Ni6<F<Vs9p+_e50yl(5?BJ0qKF|G0h%cfzhVS^@{hA=FEFn4N;
zC=$kG&5o=eOUPi(y#?To+*+d#m17*js*X(>qMfl2$g$vSpCT5~xM`fm8($NeEo^s%
zjK2($#t0kgD{%M*I<RX8PiW<^te@J)s}BzBBa}LB<<jsf^#RC^Ssf4Ll4Mo#OX}ZJ
zrj*pbCg&Kb7z?4W@d1cTcFPH!qfA$KqSTa*opz~AbtlH5Nb?1H&7S%_fA<Abf0D^6
zJ**V`<L*>Y0WrF}^J@sPQm7#A&UF;5ap`RyY@dt?BMwO}g9ybWxjo--6cS35tq9qg
z9bqGDJmxYgSe}o=7?rs+RG_mU28uxXphQVZ?ns(LUI}&ttk!(vm)9g=odPup)^p=A
z#}Q*~&qcPdF^E{wt9Rv!?&!1BCFz8~QwXVjQmy$9>aKjOd~B%7%|`t=l-&uqUrofw
zy8x5QQ1u@pv91ne)@=CZCS!IoUoByCee$b<T7D~ifld7*X`);JlO6dp1I#aMFvt=%
z;@BlLXC_m=Ga=;-N=Y?BpaUP37Z1P0bU#RQhTVtW&+kLNwMME!khH~1`BX|qjY-r~
zRo1qAV=F59oEnOI76e`HZ}pH^7?e>B)M|+<rp&>rL}y?0cw07`cLQc-=E`wC@9b?L
zZJ+OzsHes1D%#lLTY{*%27?!437de%E{qu{g-7A~`ycg)t6^rxSsLt0>aR#GtTNUj
zM|~Z33SEh&75(>3qn7M#!!SVurzS_~Q8PV3BTD9D6TpQ*C)@{Yf>rzvpgythe+G3G
zgx21t-sYK8tfNid$1$K>_%U8arA-oj3iSCLKB4BsxKDr#FJ?>)#HtiQ`>HMjQj|wP
z$8IcHbQsN2CLsZO<s;C`U>Vwj7giK5NLd^j&=ws+maZ8+lyM=q#Dff%+cy7N{oXPE
zP|Fm4UIlom?}>iCKhXMaL(^PB%120nPr=ts3n-$9BCz{GWA@}4>{p^{jiZ76Le$&{
zgFT|KMdfORiy!JDxP7AeE}yZWZ%W2|^d=M^cPCAm*w>1}895I@^<1jrQrAgn>gvI4
z9^r6zj-WD@{UY$!DlyBrG#-ZOO+70mG@xwn69Iwc`S9yJR_lMhJx`yvtnipV@0UN@
z2Vz`_QSG`-8O6$X{#@i)^boF1!A^WCeW(C$Zd<fxLR1Gu)i3(ygs4u6x^2<lPl$?A
z)J==@2~l6CDBmJz>EqxZq^L=Y{*IzD?HaogWpPBBCF|8XjR)%*Oo^HfSI0UGh<(&v
znB~n3QqA)o1!XaZLCF?b_8eeclD8i%t35!!GPM?Mr7%X6zpqs+@hBhZu4N6nOQ%?W
zFGb0)#mC?>P%>jbI1xT7sm2hvoz16Rv0|$`?dF&~dEp}2v9#9s>Lm2AE~hz6Ll=Kb
zJQp&Ske4ZWl4$eyqXYzahLQSTv>CIAAS{?Em(+xfYf+LJb-~E3i{#5|j2sjqr-C$|
z{dLHay0CSlkv@a~*rLw)$%2{6k$Q_GVRXKaXl(|8(=Kal=udqDm^x7V8k&h9t1iO+
z24Mf}QRKCc090FfkAY5mX}eFGe*p39JX|7DSUjow!Ry7S1T@&hSS40?UD(<KB6N-^
z-+u-eO2$0GFqt2!p)Nicstp@Ba)?r7ZmrPxE@5NCKH4V4+6#zbc>r$!>^{%JoaCXs
zlYWjh2~`Vg-kYE~!zdqFaJf>}9dZOBA73tC4LiaW?x&BBe7*D)Y^}*Ii_Y7nb$hy|
zmIrwF_dIOA%s<4)l|nfIC=ZxRcuXo!?)C)SPro^$P6U$Lo!@m?Ico9B8K@;A@^Oap
zV&`$iSz(ezM~rN;p!ekqSeCgv2hg%^59Ljzd}Nm8@wBv<h&-#wwNm<nH17(<CnF2i
zDq>)XIZ7zag+)-g0_*?wd@THSIxg2k4n<@KO{WHp1sh4&CCYa{a!{+uKW4I5Z>Pg{
zO9+v^w6*1y<96jtw+DFMrnct`N+zLlD^QVdCRZx?I%J$ap^0fWeQeseClJsHs#%V}
z;A+TP-bxV6atuzRPfK>f(F%P8Rgi3MRaJXmdnrJkQ`as8%hZO8PZp09gHe@Y?w5T=
zhIF7D)LL_nmA3%7SloZk-T7C<*l8&U4Pva@)`kuQz(X#(yu0%tzBiRz#`@$OY;u<5
zD`)N3hlPD?5iOyQ#jC3W)zzWe>T2@(v*6i?qii?S7$@PRNkgX0=aFYuSJ#9fV|~bF
z!7)q8!H36Kiv?aCKfSfq=Yh}B6NFyOtR~CIa{oCJ8A*)gg$rh~emOI+AYVC0KO=?x
z0cO+~GOFRj8H<V$Gph!+V+ZyuG1<T*^Ed(Qquo1l_#zt>_h=4twc9AMi(+XnHD78t
z-X>(`)AnS4>f;!EUNl{QkZ9*0YP}>v`=vQnUwLZgUdjV)DV5U9Kf(JD8`62tpsr1r
zu@-|He}|&bPRmFg`xS+Y^d|9uAQ33N;JUUHHdHd7>S$m2+!Fw1<MShsgKS?5RJ(pH
zUGL)6_qOIo)}eaI>I<Z1GB@^CI(m8Kr)V+DA+`O+Ok+G$48GY_&YW2F%Qtpc3M0J^
z`MQx_Ny!412Y@AJv&&dNd*#zxvMfu(&a2Q>AubK7G0}g%?bpR8?Zz%VVd?WuD3#HZ
zedS_@lG;47+RS9J3T}Yv`3QiYB2vfUiY-qA;S<%k`1Y)J3w3B(WQ7<o-DK~}L{KtC
z{6?0j=bUZ-2$uyA!^-;^fKX4Va3$swa5GJNR$dR$wqrr%ok}jNSO~o?+u7S)aY<KB
zci_^latEK256qn`2uAcjaq1!3gwawR>gVrAKz}RmNkBlmFHwKH6KN^RB=xsj5J+u-
zcD#Bp1s$nJUjsih?eSoeXxa&_$;vy#3)wE<#V2*0GA#HW{mN6i9ShgDNel0PK%DFC
za+EHZuDokQXr3BsT8HAsHP>=B1h-3ein&aWZh%Jtm-C^7oL}%giqduZ{Q{_zgl#jb
zH)O2BY*AN-BaXK;&kY$5(jo(+OfCwr!<Z#<A|-xB?3!+Jj6Q76#3J}AdpMvE<Qbs8
zoDZ|2JcW!1#-o57X&+0ggBh{MiCLhyr&%DAZ4>!wxF6|3#~$TG*hltm`9|aKQ362r
zku_b(Zi+iW^VhS0gqca5oNstA$DqmXq=kGxiethiE%n9PB{vkUUQ$$qxkf!LVP#)4
zMm|tMX*9r{irmq!qqF#S5o|kfdx&dG##pP1{jEeEL+f?dcD3zc*wuoyHTu^))~bia
z`UXJA>XD0gE<~<sqvRy5RYj!MRvTOShlFBq)GB*eGCn{A6Cc)=xKLI?0VJ_`51V@r
zpk8=)a?c?%kAOE@)y8#pdE37|=>%0nD+G2mD=i4IQk+!ENMwRX(cTKor9|CqP~aMM
z(W-qAy~?bnF#tE<T_fy00bxvwC1{h}TgFI1EO#&LIQ;~ekkv@VM-Bv_8u>kP7RGt$
zqNDg|`2hYSz3({v-=-vYv;bL?m0{l(Fi>H3qC$7)8;I!mm}+%*et=&+x)$ALvmN#>
zxPE~GQxfq_--5<%_^}?TtFxoRA^o>h#JCb7D}c?Oh1;*TQ$ofRL_rtfAXUTP>~zMP
zHUL7{$N)1!>(`^}FtVB|IMn}ohsGmCz=~mve>9cx)He`eJza)2*?B_7?-0}E@#65K
z4W)qRn+Dw-=C?+Zc4%~7fJ|368V|y#ScgFKuq}bWuLWQ@7_CUrqL~+5hS>(D*W0Om
zgAouMHVE2GCLR7wQv3!tBQm)^<c^XsD7Mt|1MY9U3gS_=g&8Py0!syV=RYDUv0bqo
zmW<kPwLw0jwt4Z!S_3XMAWt3U>TAiqv}CNp-`A4D`a)3Jnl6V`%6K0H1W<OO+HeCd
zl(wj)K#}<3y$coxxLI&u!v;|jTvgbZ4sZZeZ5#$f=ycJO%B+jQAoapt)d>)WASpA{
zMYMN=&GuU3IyjKgA|{%No)}z5EZ9G|1}}_ecXToZ&JV!hV`RHzZ>#Vvm;`x#PrMa$
zaf2k0X&aV#*u#aT6@+?>6N<KKT3564z3+>(djJd9m@x?pFYpP5K`JO{-ViokrGhrm
z+)q1UvrNzoK*Pojvp}^((T&K+35Mf3K=@O8Je*ETJ_}*UdjZ018-ke&^ZDlx#~mFb
z31<_?-T6K~YK;sa%!wqTPV*M{2!bZF|6fRr0X8*B=<HhKcNqVGp&TS##MZZ=zL6NM
zr73YbEJ?M-YiT@_EV1%2cy*WyYR#)itj;89P3k;RIWw1NKwFcN`)L8hGACWsl(*~w
zz^xP)e)ysbl56xJL^jsYEahg0a$RPReC5sSq4s8;l4rmf@#fMLWjZ1!-Mk*=d+Zjf
z2gS@&%5jFfRAPHB?Kw6Oh%syQAov38)19&yKn6=uU|{qh29Y4|-^Az~8={XR_IZMR
z1h9M6-V}4UZC6Q4?0V#Ki(O9AVwXDj(R(m2yamog({e+`JJW1pWI!{dSW@HYh+0!w
zElth?Xy!hOk6H8SWyf%%V6~qsP_^OKRyZpU^`1>t-<hc|)JboH6lLy_vg<{M4Bzqj
zb3n_uRY%L{2!uDrqhQ_v<uo7ThIXN?yi+u6PQZ_iHofR%0pS4*aktCVt7zi$vh>J?
zBJmTwtVo3RnyX&X2}n>PlK`;*MwgRB>NuT?MJNVxwLhCQ9vn$m?*lF2Qt|<5W5BY2
zJIE21&TatQ57R*yIcQnpfp?46KBS}<_Y6|pey{9mP6<~T64(+P!JN)MY(7QYoxNxV
z3{zADe!%UL`@z2;MvtC8hxxB^tgzDMuk^HDjUep&-5HUyIN)Ffhx&x<Ko_>V4(s2d
zoQ2QBWCeWNUL<+XW3UDthUB%s!Xf6g<`s>fv{?er21hXN?{CY(BC{~)@&`RF-NkSe
zK%6_ufI>;TBsVsvt}Y2m%JK^o+D8-{j39$eVr=Y~{d(nan4HdO=wGM=poh^SC<*32
zU&#Cz4UBJGLEW*4IY&UafDFX~Yt>8KoiAY!+jSM725k{lW=<^(4t-%?;haM10C<Y4
zLB=Fn8DQ3jX;>@8u?%&YOX@GpCl$$@gbz_K%|!yDXb8YstgaUY4IZhmPurZ>LR$yy
zusSdkyvSUf5xdJUx-gvfMo0!U<1kZ$l74{pjLkHEUwb<1+eazQ*y4VX8n$o4Q5qR_
z%B*IwR+~?0#xE{PkeV+s{I3C5s1T$zuskZFiIdbGFNX3Wa<*#wYw_`44N&4i_My#k
z37<?R4$+DMjf7KAhNbp;7k8Wu`~XE>Yls<xSHdE`sD~I^P8~drdTlf4xPT%0B-{~l
zZFh%2(%m5yR1yArpNAXZ^Wggtx?hl|;Fa)sDCJ%hg}pJo^gO}mp-;v`<N`r)WV#@`
zuaZ&^-{jSVqcRz;Q?5-NXDwkzNwcF%T3sK*<ud9<n5Jk(%ts~&R9CYjWbX*iZ$eD+
z3=#ZGY0aK(GY#1dF@)<cZZNh_%Y6A+JxV^Xpld-q#m7fKz+Pn;+%i63ubQP0J+NGo
zcRa-%8$5RM*k6yG$U347kDh@q)drj;JdBjw(RZB3T5|lzw?k@4_apCi$BN?PI4-m1
zpl94my_&Kns^b88bx_q&*+ICnhIn;!YL1S^NuR3jFsjS_CVo7Lx?HF$2X#r?r9$9-
zDJ~DfTf*Bl`X=1H-V~_vrU1mu1r37yD55?4)`F|Z;TqIeuULf-LA_!%y_y~SLU?Q0
z<jv8aT7h4T5n**~FD2`)$X+T6r)*gAh%jPd$kl=E29MB^uJ+`b21W^A8^DT=<pJ##
zmBJ2nUhNwzywBD9zMH+W`G|-SqVIN;0W%HWyE)6SzSSzn+|hTCz;dtG3$E8{hFLBA
zZ{w_Hc;ui%t9L28dOsF#Q$N0SyR-S$JK61`|8@u<^<!`AWxoN25%&D6roKEy9DQ}x
z+5=_hGn6^NVAgbVmVVm+&oG|+*nvYRfE;O*qfUej#R|l9(z{w>YeZ+|uy&`2jUph$
z5LhW`h(C5w{q=G6&p>O~9i`Q2p%RBfSnoNp`BqJF-QM8;BaVpw(Fsq(V}L;g{jVeD
zb^n|4UEpeVujs#5QUdBZZ)*W<`$X6auf8|>`YaikFL#Q{m4w;#*l)RgfG6|Br)<0_
zonwA4Fb60Je(H2ujDy7{hqeNHqSTyv93B~lb=3c+yR!q8kf-$8W1{XlhMSR)O9Oxv
zq6Pri170C1>$*Wc5VWh(eZIE~;npi6?QXboj?))dWlSIc(#sB%W#pSz^Gu!#WTsqo
zBEHGHE%NGL^-hj>h6huMmZp^zVcT%Xg2{Xo>3fO$$jI^*VVJ!fUu^zsdoatt?RHkU
zej`K#$nXHPzbf1Z#M60^1ni8E#6J@y10MB>F6vzyE(>_hS1hqJRCpryEfJIqb)9&g
z$EZ8u6Slb;V*@9hUguFb0d!%gM1Tb6dX~p|UX1h(;M_mYSa?`pKIwFoUXhEfK%X0!
z2PI73RyK_ie=4<UyQtnR<?`XehZJ&Xi>P_~C^e}-s;6@&)KOili;=Lt@avQro<9}S
z)VGH)M0(GP%ha>p_8j$P>(%$vN;rck!zPrw0Z6stkyj0JjSt56($Hn_r_t)A*6A1`
z%s;y_KKp#uD{$e6<@)Q#kkIlMyp{Xdn|}BiNv(MoWlKdi^Bw;Qr4E@|C#io6cLND=
z$Z5Vy<*rPY%jRi3|9i-vV=SPtdm@SrYe~+nHr~W%9lPD5IpF1?F0i=D<3^-5gJZeG
z!#wK8aJV0nbJ^}a)Mu=1PgxS*o0uK7t!#Epe6})7dt-V<S=Q@J8CIsTZ+0R-6dxpF
zT4d*Emt?&m4>A}do-ejOC18fxa=?8V_dM9uG<#7=WAsQ{>an+%nxm|8n5{Z1vdlsZ
zj}PD=-FseKp`O2W7sN~h?#1ZLhL~cviT>LpWxZ;7+Y9Xh@XD(u1cu(W01`*5KRtVG
zSDA+Ayjxj7tH#RHv$D+V^*fTXCy`g*&Dj$|YWjIMiYZx%%(sht#IoBYc0W#o#Rcs?
z5w)`WCG9@R-AO`*Fm3w)<M#vYeo?zk(r}{mHc_jR64-6%UY;hZ=P`b>+OIy}8)?rH
zx)7se(OzDJz5MF?8UFDg@X2WFDl@+_A!D|_Vt{8r&c7wGs6WH8MRY<6W!wbMTo~`N
zv`lUJq%o42aroamkLfEM6m`QG`iJF2kLdR~v|E%*{4<EzmC1nR=VMn%Ps}%n(IkDb
z$OnQw1hQ$ifd$<1_bNqtnHIu$!!aQmeBq=midMk>etErWPfdIxOO&R3O@~S`he;Sk
zb^(1}hm}Wjp1)r!_uw=s+%>!;P%vS^#(6lA;(}|}b~tTJa0!L4!!&h;WNEi(yF@FM
z#x*PVz<x_-gSlw}Vh)xGb}u{*q~ep&9`Mru_90lT`PR)nG{xPicNXzE4q`7LX*hw{
zBi#n_oNE?)|KfJu=i<6)6G^xPE>M6ZjOan^?g{!o(BG%<f4pO%zSN^u#4WY!Gz5*M
zca7oI9~c|L3nc6s!&a46A@)ZML{MZZP1$<IkpKDZ{j_m(hbuJ>9>z8;vO&w$Z*yrC
z5{{;-8@^vAXwQ6~248pilJ3Ljdpmm|db(CDQJfh&MJ{78GyQe+_^gn`Vi$y#3yp{K
zFtxwk#oo}jO)JFVy;2XHHhcf-X3u|S2;MQa%#Xq4VQWh;W=bH4#@r7z0xRs;xTAL<
z;QWLCjQimrLSPMB;N6PRxIL};);hddqv&sxlnRK!)|rX<9L%TV4}8#!zlUc0LSTg%
z-v_z)nH-OCc`{+rze55@4YU6pB71-a8MgQfUv^ZE(GgSkLq7&hSUXN#x_T|~4t@Fc
zW2(hfk49EMtQX)GI}bDkDqru>>ToVmWOX7=C*s#%Cn;;Ym#2%67G0H7Xf90`TW3Yu
zr;N{~TzFtE)ywvj*;IbT#AJ&Mo{1uZ&!e3jb3`YnJP$Mz8k}V}U<hf;9W)H#)Kc!y
z7LRFVH^c{*f{0jPF2T#K-%J#(cU=w07^An3>1&HINIlS~NYEhyvW`@$1~{RkE27kH
zWh@~Cc>*Zpze7@%LbN1xt(T!p$!ST-=UmXWRwOB}L-L?wK0|gGi$VDvP&+u~cR&k)
zx&pr+9Cr0wRO<z4_qRk?BK7ScxRg-+K;eY6<Jw9Zr!Z+N6GWVpQF4L8FB6540dz=8
zInq?_6ZHgzS4^NVP9QtAviva^y*bybi}w5os|&hURY`v~g0MNG$?N^JYR!ho$&&79
zVAqmxxgc*47O*1+<DI+n_n>jJ2o}ZVx-?edclLWyf&LZo2MD%*NV!a1L?Jkv?4!53
zsFQyc?4!4tr={(s0InR+=2HNUXj+l}4VZcb{h>zzM=Q_O;jpyArS0<ICW7L3e??~G
z;^XQk9{2YS-ZuN#Z9&Zgc|aRcp9msM1b>Dq6gHM}%N|bfd7Lp^Uvz2Y;W)}!xbRU+
z?_Vko;iIFUkT&1Kw%k=*dZC<^M><=_dBRoxw0ph1cV}-0B?>^?+C{MSbp$g6%w^&}
z3MD{z@y&8z9MmM1Mp|lxI8i#owLF`5h%Jh-(BM=E!z&f^rOA>j49|MJg76z*=vFwU
z5#~w>i*aSrS?=MKhjEDThAn8O>b9)xQ!f!I$uKAS`?ou_T`njYRwXP39VRteeIGs|
z?LQ|G!CuDQ9`aoEKKT2=BU3N+-breXYcWyuV@}cc?YDv>q;w}|ou4C#D?_m~bw3<J
z6z450_QYQk;cD6Q{!-8ORDWr13r_g@pO<ek-`nq2u4hBP2CoPm?^qD;{tsKc@N9A6
z&?fnB9^TaPwlGxKtK}3PY{1Dzy-bp@3544o$+r&X!omtq?^#^ue3+KGF89-u9G=K5
zI7AXb`U4`dg)+@brKYQk=+_IYs>gT&CKvnG1e|8awj}x{%xXzzv(MzQU6TG#KIqH(
z3;R?fzc&u6ugiJRe-;L-)|;6dijDt;wo6JH#qD|3P?LX!7C=YF9H-Dipixx&6A<`>
z#mluEwzVLfOkLs8cj0z{xF2WF##)Q%!qB$q1T422Hq<erc^ur8fYlKk<Nebw`P<_y
z$89J#`Z?Ni-ry3@8XLoC!__mjUDDtj6y_rh`<)NKbtp}Jz=bn#>{dSx3%&u0m<DU)
zK7#BFixrNl@8$QNclN&Ha_;b`ehYh#?PH#H+T9^9+Xa^VKAMDSeZZd6L-4JRC)A5R
zck}=NV)QHVT7%rEpr#TXj<Xkb73mnaHDi&kVPvuNkf?>meoY;Nu{o)~ly?rN4xA3H
z$}#12Z4os>{{|7>f4J49mRNEs63q|&hcE4!-K#C7&A6^|No$m@c3xeMYqQcMoo|6_
zIp#cL9*lzE?yFgar>joVS524rsM99#S_@x=PU(L7)vH7KdIxcwz3-l|b<><*gE=3o
zS6m3Ie}@Ev|3j=(SU;^RX6fRzu4(>QYr137)m5UIK{hnKRMH#}9)m9<vvV|po4&D=
zqR;c-x}GK7`JE?~B8;8Yj)sUIzMf0U%~Ah{tt<S&F(nl<go$a(RZ`<}fBicsPSbJB
zOm#nf#>pWlQp<1kdnNy9>n>fK>JLh-+q=^`dz1hmHaJ!j#4DBr%u&6-<Ht%Tqwqs*
zIsvs2yI0b#@4{V2l6j;5VC$5tVQZ~%wajB@%%9?<lyk`ZXT4ymUG5;tl_twkgSw`|
z5%OzC+_2mi_FhaQ5D2qvt^4Urx{H9M5cp@Qr#B9JZLZ$dpTB)Fygv#LccnPokf${I
z%yq3B5vR{f(N#{<p&d24I0^1knQ(w1N0?!MpR%|+nA?@Yoc^Ob3UT+tRmr@qxwyZx
zctM(y9*8VV6XdhF9|29g3$$M%Y0kpRTvTMA$^ehr>h@`ja&Ung_HofV3X7zibhCwb
zXaizh{K?y3%SPO)3sY9?;<Oh(FAetfbr;2t8y69PT`0^gLQn(Yj?>GIIs5$Qw@Vmv
zU*8F48|~-&8o9WzSN)R{PIWC;pZS61`_|!mAe8%mO^NED*y2(LoX*2Iv^}sDGqO)V
zf#f}Such}8;tCK5;F*1_JFP3dyWG*W)X`m@0<c|6Q`A1E+RuT%I1XH2b|Ej%<)Ewl
z`cnvnACBkRW5X*)j-`~cdprf@pF@35;&}qkV|X6Hvl~w*o;EzJ?4eUy*~6#sHt;s^
zK8^Qjyoc}}!h0C+VZ7sb$MJ?P_b|M^bTnIV4msmVN?6q30X(Pi2-^TVC^g_-i#^oZ
ziDA3ti5TE`5j8-HWL{mqp6lcZ`ui@>Kl_t2KNv&3>+VG@*61HVWe<XYmF$nRc7GI7
ze>4FX<e<!Zb|U;Jo*q2i<<8m1x|TXu0Pr0|xu++9CA<>p7y9VE6!m>h{oNCC?wODe
z*rRoczIxB8zE3^s{`#E|^Akz{b}o=9z~jR+7tcIA3-OfU3F85s3qa=ryz}wKX@`e$
z@rE_{ArIa#(>~<F8wS~jB)oAv;UN)k+}JX)Uu^np1H7Ghy6`+ku#^2#?nLV+^aKA!
zYbW#p+J-!K+(rG?oN4U+Ph7)0)kuZ@QCHXOH15X+0k^T{WBo<DCS4dj<Uln)|7ECz
zIECLylOwKVI^*uFrO@#M2QX`t6v-`WPtoE<`=2L&1UjpOeYvJRnD^<Fnh!af1I0ac
z&jnsVRJ-BOIKVSM`LQ;m>?oWT9(*6H7-@e`aCg%BO0Rssdr~J3&;Jx3?x#yF_`vxO
zy1()Fl&g#T0S3(XE`U7q6Mf!FEc|-k5r3?I|1dCuh-NRybGxe?whtoCsDAA4-;s+M
zvit9Th78gk0uz8P_EBkRq(o3&qxm)l!{(US(hHKpkrizQ=0a#6wch9>#GZZzWuNon
z`v*U$+ef(nz^nm)`z&}~RDemK*4r3LfkhTdz&pd(jklfo0#Gwen?V&6_i$)G`N>br
z?2;Kn5T7{8@DK_ZKgSPj1x_s6$CWwt3d#Yho>x5msT3vztt(b>Qh#!B<Z2!{rnvdx
zzzf;A{&wvXkb3gvsv*kLR3lq<Rq!J$2Sh0Bu>+I&uL#$H*nvqD4mSsINQ3tudM$x8
zr^`NS1*Zhs(3sfB#I6pGBiF*lLZq9(3R8(`diasauFllc&;$e6&L8d$e%KeKFE7rx
z-c%jdYtCSv!))pA-7y0u(Pwzp(gR-nV}HQtJo6Lw0{wA^A1_|qz1YIke6(>5u2YMi
z#wEtqeCijwYTAti*xFFD!`PEU$`T@QuHR0r9Z$v;GgQbJ{vEoI^5E|wd^%5)0Mkn%
z-;2nn9$JfoiaJ%fiA};@f;`pkdQbNwsZ>eVo&Z{J7K|KBkv(>jmy!V6{Bz`SN)!U6
zr69m_=CTA;)OcyjbTxkGj@%@y!x7wZ*2N*sRO9Pgrl|4zcjP3&9gYlo&4DB^fO;1G
zE$Sk2e};9e`4eL<YOCu{r3m5`zESo6b-s*mhwS;B`O<@U$Y*JXJzws|=N>P9mgCum
z=YKR`5^%`X@w^Ec{Hghpa((`MnJE80GQ5T7H9RlkIfUmKJWt_y5)b6;|H6F9DPd8A
zJ$MT66yX_{%m2U4mwR@i7JI%7AovCI<)gp_{Xv=c>__-8o*_KRdG0gwCFT5|&6gZz
z63+On^54yu3D{+*VmY2wc-G?CfM*LH8P7NHpkMwM=1Z!KS&!p)Kb`}4UZj}+mHCpK
zKIkwAe+)=Pa#XVSBwf{XAsyK)rS6&f4u^(oOBT^SvSSzgw`0u`JS|-`$>Lrje#H$U
zyTwu*&xW#`+I?BMc{FnFT9i`K)XLlxGc|IqP)S2PqF@b$31|0ij9!{eJ5?U=xgWkC
zfo7!DDZa?LA{m!#crt;Mc|&*F!ku#V!qq$qGF&ic!a!P5=~1R3qcWMNiwjpPQg?%+
zoa&&>p5vp6=Q%nXNta{T$YVjY%LR`DqdAKspS72+=jj%=sRM8YfQ!+yFQ|h><_*cV
zX2HSw)`?j+F>%}Meq_Ck-`^7kez-VC9lVKLOm1XK9Ici7%5Y0APQ@f}fN`0KfTf1}
zUtzxcK*J6wOeOF|$sgPRsf>eiSg^t_Np8y?INGP7dtn)%9xy9Mdc_0C^ng-;tzYF9
z^=+Ig?ZBo76o(xdxT<9?j`wcAY9yHJus858M+z3{*!VIh0dnN+l#xGNdSvtuPP*O)
zz*EVhkb?XvaJ&k}=@uoR6F1>%LdKjFZ9&3kYvOuDUu><3C2o7rH~28);SXO()$By?
z0Nsd}@UwzPFRrfqgM6&>h+LI$y?Qt6M3}{T|Lm#FI>9oZqnjYGoEa^C0ebpb^#hA8
zg?Od751v=B&EQ@LrQiyFJ;bZ@awt;AJJeF;P($My@+w(8w%~+(Bj(ii7rZ531wV?v
zz>f=2d5C%oQE7;J&HQ#lqm40c4sQhFi$AenWAvhSk+COSUE4j0E<}YwwYmFV2kwWs
z1Al1={teyf<qM8-kXhYn6wJhY{87Ui+~^*oh#|$)cUj%*Q&8EQ?li1`77Qqdx=Wov
zBENeRyh#ut|EKwHuq~}=>^?a7DrRhbsfCXi>!)8nUsc15{^u*%A83U)THJ%b_w)zn
z3+z00q|f}YyWA>1a`RGahbW87mW>``y=!RU!q3tSLra2fb#c?r;4X?=g`gGDF$ejp
zZ2nq=o1Q>)m@cE;M>*wC(<637Q-t38;)t|f-#3QWUJ9err&>p8KT^)wOR<PZt)>`=
zhWz9M2X2A}#SIoSGd__yY<jxF*zCH$wi@lhH7KKfv<4;WD(R4=%01>RP_8R|=`#5W
zQ0ZzrT`{@tgR}R4cFNgy2Bdxkr%Pax^PtHwd!;2$rlRi7ZU9ZJz238nZb8EB%ExOO
zPyp9>@Owa($^U9!1(KG$3S=sdE!o$O{1Lr97hQc>;wliAeHDn(r%f~SarZJ*T!eD$
zTbL0Ni;r`d#XZa9O!^yRID@bZ!~D-qC7Q$$JVV*C$<^w>&#+?fOR^W{lEqx;w0xkR
zozgNxJ?q<%Zx7LIv?9jD-#>+{`^axD)^YY3#I;QBIQu-_b}o{0+j0DiGT@JOp#-X_
zwO#4Ltu+(8=oXH9(WP^rIEQ=_8QLJlY@h6z#XW_GWzRBMTBb}1H4mFosQDw)8EPJ}
z@|F|#q^qtX_&k1*hu8$)uGWH2Id+Y}vCE;0y|R-DvCne`BwmLpLxSwXO_&2=EV_1F
ze0K@=uidda>65Hn0`cch<#(i97cx=?AR)<HR#|RBT};7FseL8N<iwRIoj4|KXSlT%
zhw~B}leCk`{eOK)x717F{|lc>GT}@&8FwNL8+`78Ga>$P9B%b7PlE^_;o4nivDHw*
zz0P)(?cHz`pv0eHSbSw9;8Nx6knuRy11dZzaqdn%pW8N#=dtGf%-8{0%|Gf?-_L|{
zKZnuw48gaJ`tYO0pAq{e`m+u(#%u%#qf|^54Y85(>;Ozn+dam&P{HVlI{c*tZlH!G
z5tgRnlVQ5&fc^+v<ZOy^)21KckCI)F8wBZY!l<?D%5aFvcD&9VB>nwL4zll$$T_}G
zaABaCPWK3^FW@9TE=z{bUK;<)NjR*K@XN;%83(FP!uir}dF6zbFJKjzo>aLAXMQ{m
z#T_!P!=%JXFk^{%3B?M^l#$*PIR{Sji6kW@E1o35FL*%~gH02(SQBebG1{LbvpJU}
z+>s0HjrnP*J-6Ub52_!FE!U3z0j-s#!eb-=l#khA%s9B?0WS|;&%^o!@gk?4`3cRN
z$a5R=a7ln)k@FtuFsvVU;??0Pr}beeZbOq7Qs^4hNR#s`WWJS5b1IuJVG(nHe$07n
zzDOVRV_wDPyXb>{%uB+?E0lSggi&6HsdK(SY4oF>cX0oWpHRn+DCsald=$g^9Ncy3
zKa2egD+_&Xk=xP?eq8hl`W5_Vl`@t$_X%<&qu<>qt<^}}HjlJ9d%cKc+5E8VVSjJ?
zWqNJ^tH|7M@w2j*3+h4FGG!D!>?Ke+<0n;Lhk}-axd7D?kD=Zvs)hS}s8Vbs;mj)4
zhQBL7>`y*w$&;#2?!z2opH!Xt>65CdB_UB6zWAsr#qqPM811;Sp$9X~=Uy30b{K7=
zu{Rf_qKmMVTXbC33QKA&zj_EpmH-AWh8k`FH)l{<t$pPX=ASa2;_iGI#A!}hy^mm!
zK=9!{Wk5>h*K6B%`EUn%oXqEC2LA~KxZUOv1WM}j$8Q(P#{oU=a*Ml|C)_TSZ{IG2
z>m_mW=q{LH^o3X@+BXYL{;_>a5AN4|3mSy67|UX8QJ7hD=7%mA!l6VunT|hBceSMq
z!0(=1dT|aMmtFAt;sFvdxv(dZi#4^Dtm68{7e95s1PF=iQn-I-HU4%aoTlRI-Mjyl
zH|2i!!#|{e;T`-w-q=3sI7f@&_Blz#6|U0NMigmafTWVUS{+EimJ+#be~sml;tRzr
z4!8QlBW3s#WjIc?F%y^dNnQ0B%_(L^WMhWVMfWMJ)+@2Oi^J^BDtM7fp@i9hP&2-T
zEA(;43p(saps<qWemXd2X5;r0_tWrA7?84hlUpJ<%TnR6uLZzG&-S9>-^EfBe`X4s
zW`s^J43keE8!4-GL>dU2^FmkUSXb~98=Fsn8*MV{mAHk5&e{_;V`K;E;(b7u#-tpH
zx&J+wIXmdWMJ^DTQdoTj^3JtCz$L7C^L|yHS8MzWEF87?gNP-d8A;4tL`>RmYfnXf
zb24t%L5s3N#{Qq9d7BEL<M-43@(|)AR{Y%IzI73tP>+(k{hwwgyqrhMj=|IZijeU_
z9HI^ESHW5KQ@-?*xdXU8v6BlvM1PF`6;k}gJ^v!|ly|ESQn&WA(a-wHle@P=-W)c*
ziaNLeUZ`5Qaz@2Dzp0R_Aw=T<m|-j>9Q?nllMBN5>pC_*xi&tTwl6s|z<Te7jeWS}
zjydbduOEK|NY1D+uAyu1%)BpF3GioQ?eh(wtt!vhFUixb?UJ$c-(WiG*yI{L2jeIl
z7_qrlF5(Ue>xwO?87!@~dorO1U{|+24ZWCYrqXU7_j-qQmQ)@rL$C_9uXSqAg@+5>
zSAsuus7QT|YfDG}2$=}Ub(Zz<^&RVDZ}Nb8E`#Bk???=H&_rTIUDHdWBRk&2?(MSf
zY2A*lNnPp7mio`Oe2BRRzRmEe3>giNqmi)#>%I+d{O|6ytO+_Tj9^gN2czExVYt05
zWEAn-$*;@pvRzcR;o`CcM%N#w@<CpnwueK;&_7Xay8Z|y%tgY19x6PG7uG9{!F<Y0
zc=hp|40pp1ILOz5Q>9WI9Q_vlTE&4ll`>KN1awi~T8x3g-y?^vucqMhJh+a6&mqX7
zyAcc-%{J`l2L847qOTPfeFgZJuJ0reZ5-O86ug%Q_fv2a57OuxT*K?Ip{6BDc2dG(
zp63Y)-o%4jC^&aQ_BXyygkcGkj_@yC-$U6_d5I?}`0*puw8ts<J`c80@Dzf{k`E_J
zZli=3cphr=U=I&AQSg@t9w_<;5b(#q5zO}Gzb`59B?Z2uz?T&Gk^&Pc@W?+3LjHFJ
z;Tk-P@vOwN36G2?f@e3LNAdg+&(nBb#PcUSi*XM4PCPkK%g4Sa2wuET<NX$%XYo9R
z=XpGj;_1S(A5RhLT8L)_p0#+I@wDOT!Xp6Y6L>#`=P;hP@Wk=tppH3shVh)jBjb4x
z&$sbBf#+#F&*NzV{GE7G@ObcChG#CG1$b)l&_C<}Mxcg9((&MC`A8ZbiXTJWnW&5Z
zgVOPht6(?8zy50j!bv<8h`aSG0iH}(*+G{c|3}6@FYdETMgV3SEl@myGfhZK@rc1-
zFqQtzFA_qO$vbC3Xmz?I+*DK)4gnLdm$V*1TGzA=|KPi^Z72Ro$RVT)l7yFp|MV%$
z5w;47um%6GrXs?et;&`yc94J558-{>9}r&0L*WM(!s?HQ!p{W)!Vx^leDn@34$w=O
zy*MCTi-+<lWdY$nJoJyg-#~a^!Z*eLOE5q$;X8PL4-e&|Z)bUcUc&o`JA<dOaq03q
z7MCt>tO%Bd8moiLgG*Kg%LK$%R@W|BxoToOm1|M9%A4=r=-t@Ta!-pFe_agw4y%^m
zQC)4v(5FznY{k+EpF-Ikm8Hv8T!>kDW6=!@vNNysDqGk8&6bT``5y1)t()b|>$hya
zf1|f)<N9qJj6nHrqI_HLk-ZzY-lKfA$=kYZ{aqWqn^5<bdv<J|P;kAx`JSy8%H8;d
z<yz$p|4q61RBoHnveCPJbBnC3-{Re*Y`u$Md+%DmWecx>@S699@Eh;hx^d@b`77&X
zdU<7P;y7N{mr%J2?Y?K*MgYENYwJCr!-kF9H{UfOZ-Pb}cW&Ewm%MQUr_2Q^LKfUu
zbUmk!f*KQf?pC(Qo8_jKjq5jnLU(=b)A_%cE{Q@L*30XGZg%GSzu9_E%iSQrww8Oo
z+Oqy`ue`D4?#){-rgIT*&*%2f#;u^>JzMYI`2Vzb{;_doR~<j&1a{ZXwsAov+bzvY
zN>pdNb)C#Eg^0G}jO`|><8|%W=?X-4;(5=Wb}}=1Gmc|~7H1o27a`j82WY1t*k7~}
zTA`IFr8E?!u!RDF4JuOe!^yh*kQNC_HVe|OS{gpz``+`6V<#K_L4tkv<vZuzbIv{Y
z+;i`{@7<R-<4Oa2_}b_Cv!-q#oSv0pJ&AAMPQ@uGS81*??bWKKO2bV9I7Po0#dBY2
zDy-J4LBpFY)iqT4cfZ>kizn!C=}=e*=QU?LnUo28Q1f<6XXj|tsa;HA>+S8epGkUI
zDKNWdD<7{^=PDmC`;gxlF4P<SOo1c*Xtg$5bG)d0pj0VV=WL%}uNS8M-PNQ0He2_@
z?9Sd|xvZ9>^D}!qXYT__-qR6PJ~=0qKg)Bf_M|oJrR#XAdnM*QbOSq^SPR>e?DSp7
zQ{A76d0HE#vv8eGVnaSIJ(_cCsMgYxH_@}lqIIS#rguSQU-g!5QZI*|(uZUEU|YRS
z?2*<=^6L|^ehsQV9F6O}ll<sS>OB|NI~CXab12sy`@5LF7}I}?>GxuK$1mqt^UZz~
zs`Y*|RF6&WfvUb}SIpl4m7dD?$21RpGvyH|?}gceF<<m8F<*9yltsgsE<pAFF24f(
zG3c*DH$k6_<)Uwk`FF>9DnA?ZzY2W^<!?YYL(j&1(Je6_vOG5xTb1SG(_Cwn6yKT0
zbIRJ;nD-dvD~~&t`}pqXAt$&OXtsE7<+{C||72Kf<86iaujs9n()*p2_dDOr?5(iy
zYAN@N1O8O#Yn^0VY>35Ys1(*4L#49cZ}!*intLnDn$J4T5&vkcxIM#~HpHFDXrVDP
z!fHp|cUZn$t^0clm15bq``4B0jj-%jki2Q#fw0u@)rP&lV~op+%i8-a&ow3z^xJ!6
zQ|qK#Ub&O&*r)5z?)iqlzj~ll^z$=?&@$_i?EdPq-2NpqT;<X_6#Bk>cyMfFa5z~%
z|18tKvi^R@T)h@@9SHhuVtjBc(RyHbuzzBIQaaEv)+kR@<_L~m(CVG99zIOBhD#MX
z`bqgY>4$Z$=iEEnAXjLv1XC>F*4HssDAoPJqf>rO*L$<CX7+F|;vBOtxqN?_fw0BQ
zaDHE*Hr~LSX<~G#y?lU?=-3}$D*eQ`-JzEAvth{SCCrN*6O|bk^5Sx<M3>>_zF7ME
zs>Ru|i+wy!UpIL(*t)VtKGgf|Pj4VOV0X#V>MC~k+I;+fykp#NL~|iu<#NiIFWvD*
zF`gjSqp~K#{`s13K_o43zf{{>399|JOPt92s0vYfyLfGWOcuhD?v48GQ<B7^GRQUb
zD=yXpK9jIIZ(nw$XttTX+%Xy5m$_m2nv;$B(YXAHD~)p#Y4#QM;fCS;HA&_FsBSD2
z@9!pdBUARR%-;I$LeWkB(MD)zqq0r_742`La=u#hUHJt!*GAQS`%C5f^P^@%>e&N>
z`;;G7UPIqsEQXqJ_98RCz|3?vDn#g{ylRVbNj0JoR-Dl&ujDXRe`G`D+4_w7vU@fN
znA&TtswwaPas+;FTW;C?%e^`NCykd6XW2JSw)j7Qm!#il<L9fj`LHxS)9`wxwtGAK
z`ugtm#tK1D@Y!&TvE?e3ydLiI8-?5v|HyprRQ2$7?>*lBnNofE#-D7!vNKl*{d>I!
z{rZ+ITWox;P}^Oq?D3C!J9_)Po<u>F56!=B6E>kc=3RGo4upkik2TOMhSi$an9=_4
zsK@s1P^sbt%xdip8}i0K%GOAlQmXiKk#w$9E_;W3kINlbqaqtgC$H-+KB$(9et2i+
zot+O*C!Aw-rz2H%GFYIax-NKSE)4k5)*rRnD=+ToVP|&44;!-TxHz?awXR%Ut&4?~
zy7xGvyk_0fWk>1yi-A?9@9CA@RqA5$FR~u(gYt#SyBau1Z(PK-u?DEJ<^y`Bc9ri1
zVh<^-M6^+@dS$j=J_G9YY^&>0g}Z=zTIRIxa+)${+oG+R?P3Ng?HC%eZM{1`Di1_a
zv0ch+>%9*+#(_du!OAXg55aVv9b#9?-u<v&yq67q(W?et=ucI{qTAaATx^QiVcqqn
zX8fs-*JlrJ+2U%y-`n<4W>&sXo|-MYfffhdo=@laq;DVWpFGHz9&`^Ta*o;l+{Y>L
zF~swaOj3Zh*Ke@M9xSnfQ(ZrH_Q%+MHnyKs5x+hC9M4dMAL1vvyJEqQlV2a_d5*Q5
z|5ftZHz<9wE&r*uJh#QmI@~rd=Reby|7=@cdn@fp7zX#QhP!vCu#vKo_7VT_xoE%g
zO{n%OzX_H8QK<BWq2188L*D{@^|Lwq5$GA{Cg|s&cR|Zg?JMqs-VOc!XLvsw`u9*x
zu;-!LaDNH<3(#kv--kW{)rR5(bm44{9Q#dZrhOnbI`)bW`QEOwLP$Y!Ax&unZZ!gj
zj^%7EgkQ{=VCJnldU&!M9jj%lIeR##Zgw2E)yGQxW7aw{c56qwg-5J)bZ~~;%8}If
zZZ(i^5IudxUwAx*)>ow~^#A2INDR_$rV&UZkVYVlKpKHG0%-)&2&556BalWQjX)ZK
zGy-V^(g>sxNF$I&AdNs8fiwbX1kwnk5lADDMj(wq8iD`s5zxB<OKmSHWjgfJuDtui
zi&+mnGXKbyH~?RGG0HsoI}tth+e>;i%5o1cIC>KOuRnd^X)hA5`aJf7h?R@!AKapT
zf2{vy^j~=DpPqV~{qs{VJ@vCUw*T;xuEs}rq3t6Ve*S`I2QPf=!p_zD-#T}B={2(*
z4=0{QDhkD0LGo@E&APnahts=cm^J<C*bf7}i>7zi^j#SRO;kKly`Lso7f58XtGc54
z9*x@2Yh&Vd1HHQ@h_ASde}7!=kIVVEJPK8vv6w#|Q(mcd_8)|*?Q+aN4D~<_=$*F^
z$XE44{wx6bd@QDqKqdbKko-81Kc5EM!EeRoC!zB98KCyQ2&DIiK>qzLko?;~@=XLq
z@yP(a&ncRwGy-V^-Uty`XIf8tSZ>|~-2>J7_fWL_kV{gBTNijIcR_2%iR<KAGd5*x
z;pBCEttOJ4UW31p1^gVcl__K5zqFD`DdN9+1ODx5<Ujeo%k3?NlmA7(+7`33T!pr_
z#MbvR-#b+2<8+7ZwE=Jt<m~|)u^mowcHMo@NgGEpX@jiq<7h}O%@G?Suk^L`|4s{P
zFljWR?{!kXv)CqyS=LAU8SFJ!{Y!k;e;R8gt`I(!D;8K4#SKoU&ywRl+fCk(zl*wg
zbPjV3DNvrrn*t@@nI9t`a1<!ZqKD@tN@XiT@8sIzqg!z8?Lw-28BYqvU#&!T1be+U
z<?PGg2e?{fmi-$*qmER5*QixOuj1Mrw>fOo@KQb6gC4Vnw3Dk>tNtYX5DTq(J7`UP
z)Tf~Ildet0qT%!_&c{|SZ`9Vu?47hVOr2?0Ls6>HA9*{?U)yS6do|DFJjin`Rithf
zJCD9Zqah!MxO2!b2O`_*v*MVHqe{_;tmSL3i%v9NQC~-~Q)Pr^iEU%Wc&=4n?e}sA
zl;M{q+Us2(-6Xcs|3$mU`CD@lEx57M%=4Is^Nffht$UNC2Oi#NtQENmxgwgHnW39Q
z2izzZDbJzf*-tat9(}Gjy%F1Q?`?~gz8%n-1D^5icG{b9*5upG<8GXvI$tKSA1?dX
zI#bMk!kuONk;;QQ;}G>PnVV+Mt?$8x2XY|e?gUw!baJkl77!v>ScnLpWbO3n({_6C
zv|ahDFW4Er+S~*I$bxHUuJN~?;eh~T0ZMkQ2_G~;0J4CJb}fJpnjipKfHAw4g%6q_
z09il-c7|_0G(iBefL}|){25H0p<0A26i4`n3^YLivH%9Yzz0nbfGj`>U*Ll#2tXE4
z5ntegCI~<lV2sw`b2LE!vVaEg2@Yt20AvA;;tzb#1Odnb96<yhG(iBefCB!&2Tc%w
zEI<K&;DaUzKo(F5f8YZh0muRj;Sb({CI~<lU>twogC+<-7SJI6zz0nbfGofXs=x<L
z5P&QogFo;=69ga&5aJJf=Lvj{ET97Z5Gl|E0muT3;17Jz1Odnb4C4=c&;$X<0vf{~
z_@D^_kOeq^DfplX0+0oK;17Hk75Gpc2=E1S(X`VP!w;GTniiS@8g43T2sK<98V!R&
zPQiszVN-|{4nB|pbxU24yK+r#s7aYqRjG=_H=e;M@VnqKFb5{U0N|?qdg4o$Y+_=<
z=H})c1_lOf>(;H--Q9h?CA;#yYxc|&PjDVDU|XFP;XHCBolh#NbjzvJr7o8?M5$F*
zvdfn*cXoa|PUp^@+pu9-?u6~~wZ&mle{J#QM2@&iySgYP#=|g{BSvAlbvdSl)Y*69
zmO@<JNhOcPD8%NY+Nw;F)P1a!$F-e2){5&#=G)|nmADI?m&40)JWl5#dhXoSt5=-^
zof5a?i5lWqj`-3lxx`6*#FrBD32n){BwkZ~-nHK)@nTdjCKRrozk2?>Htt6KON)z6
zvN*DAUgB8Zb!jnDSR7fFOZ<v{Uq%L;7$GUH@5HY}V(aR{yc1u%7|A1XBF8`?c5>(1
zE3YKxX`m~vt@>A2iKRf(7fG+h9i#TL^|-zhBTw3noyY$TG9QUu{qyZ@OP+`?zNY%>
zcdN4G8#Y8IRaaNseVG4S>DrR5V-?8grk)3C>)3nTc7?}8OHi=xbQ>1Xc|9chOVk62
ztvAEp41NjF<ZbS|K>E;q%0}RUjIHO>?V}uB{jp%izqRgD{wM3)sZ-BkB(wR<^Eqhu
z<}(8-cHj2=0OcJUZQ%GG_YmpPMnr43qo9XME9l0J)<D0zd*f}Ym+3xnd|&~3*9jG^
zyLsX<h;^OPf*-B7JcD`_=<inl15|$k@C9KC{9}Y~`~}Z5A2s_9^6zXW|3R}Qw@hbv
cp5=Koz}=j7fb11<K{3<*uS1QbX*mM_4Q7Xkb^rhX

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/TripleDrawPoker_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/TripleDrawPoker_MiST.sv
deleted file mode 100644
index 214a4eff..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/TripleDrawPoker_MiST.sv	
+++ /dev/null
@@ -1,192 +0,0 @@
-//============================================================================
-//  Arcade: Catacomb
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module TripleDrawPoker_MiST(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"TriDraPo;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-tripledrawpoker tripledrawpoker(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,1'b0,m_left,m_right,m_fire,m_down,1'b0,m_up}),
-	.P2_CSJUDLR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,btn_two_players,btn_one_player}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 5a4d0094..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index 7a26ee8e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,83 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-	
-		crom : entity work.sprom
-	generic map (
-		init_file  => "./ROM/col.hex",
-		widthad_a  => 5,
-		width_a  => 8)
-	port map (
-		address => W_6M_DO(6 downto 2),
-		clock  => I_CLK_12M,
-		q => W_COL_ROM_DO
-	);	
-
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 841b2407..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,86 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_UP    : in  std_logic;   --  active high
-	I_1P_DW    : in  std_logic;   --  active high
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & "0" & I_1P_DW &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2 & I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010000" & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-	
-
-
---	W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_1P_DW & W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_1P_UP & I_COIN1;
---	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01"              & "0" &  "0" &  "0" & "0" & I_2P_START & I_1P_START;
---	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
---	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-	
---	W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
---	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
---	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
---	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_video.vhd
deleted file mode 100644
index 30030bb2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,440 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-		I_BANK        : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	k_rom : entity work.sprom
-	generic map (
-		init_file  => "./ROM/h.hex",
-		widthad_a  => 11,
-		width_a  => 8)
-	port map (
-		address => W_O_OBJ_ROM_A,
-		clock  => I_CLK_12M,
-		q => W_1K_D
-	);
-	
-	h_rom : entity work.sprom
-	generic map (
-		init_file  => "./ROM/k.hex",
-		widthad_a  => 11,
-		width_a  => 8)
-	port map (
-		address => W_O_OBJ_ROM_A,
-		clock  => I_CLK_12M,
-		q => W_1H_D
-	);	
-
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-	-----------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sprom.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sprom.vhd
deleted file mode 100644
index a81ac959..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/sprom.vhd	
+++ /dev/null
@@ -1,82 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY sprom IS
-	GENERIC
-	(
-		init_file		  : string := "";
-		widthad_a		  : natural;
-		width_a			  : natural := 8;
-    outdata_reg_a : string := "UNREGISTERED"
-	);
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-		clock		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
-	);
-END sprom;
-
-
-ARCHITECTURE SYN OF sprom IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-
-
-
-	COMPONENT altsyncram
-	GENERIC (
-		address_aclr_a		: STRING;
-		clock_enable_input_a		: STRING;
-		clock_enable_output_a		: STRING;
-		init_file		: STRING;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		numwords_a		: NATURAL;
-		operation_mode		: STRING;
-		outdata_aclr_a		: STRING;
-		outdata_reg_a		: STRING;
-		widthad_a		: NATURAL;
-		width_a		: NATURAL;
-		width_byteena_a		: NATURAL
-	);
-	PORT (
-			clock0	: IN STD_LOGIC ;
-			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	q    <= sub_wire0(width_a-1 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_aclr_a => "NONE",
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => init_file,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**widthad_a,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => outdata_reg_a,
-		widthad_a => widthad_a,
-		width_a => width_a,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		clock0 => clock,
-		address_a => address,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/tripledrawpoker.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/tripledrawpoker.vhd
deleted file mode 100644
index 327691de..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/tripledrawpoker.vhd	
+++ /dev/null
@@ -1,447 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA TripleDrawPoker
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity tripledrawpoker is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(7 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(7 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of tripledrawpoker is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-	signal gfx_bank           : std_logic;
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		I_BANK        => gfx_bank,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
--- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(7),
-		I_COIN2       => P1_CSJUDLR(6),
-		I_1P_START    => P2_CSJUDLR(0),
-		I_2P_START    => P2_CSJUDLR(1),
-		I_1P_SH       => P1_CSJUDLR(3),
---		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_UP	   => P1_CSJUDLR(0),
---		I_2P_UP	   => P2_CSJUDLR(3),
-		I_1P_DW       => P1_CSJUDLR(2),
---		I_2P_DW       => P2_CSJUDLR(2),
-		I_1P_LE       => P1_CSJUDLR(5),
---		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(4),
---		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.sprom
-	generic map (
-		init_file  => "./ROM/prog.hex",
-		widthad_a  => 14,
-		width_a  => 8)
-	port map (
-		address => W_A(13 downto 0),
-		clock  => W_CLK_12M,
-		q => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
-					when "010" => gfx_bank  <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/TripleDrawPoker_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/README.txt
deleted file mode 100644
index d6655423..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/README.txt	
+++ /dev/null
@@ -1,24 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Uniwars port to MiST by Gehstock
--- 19 June 2019
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Release/Uniwars.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Release/Uniwars.rbf
deleted file mode 100644
index d116f76ae2a09807726380ee10da01ea97cc68cf..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 310852
zcmeFa4}2WebuWHrJT?n;lDXs2dc0BWozbjW$u?NRCJwI&Gox9vc0||}E3*&>EMuo6
zO$w%v=GXUmWk;F?Imp4HCXc*FgXI`X+9ZHWU-N$b6N|`=X=$-3{C-aQ`oQE*lTTmD
z+N7yV{_wtMW=C3yUH!2|>lPi`J9qA%bI(2Z+;h)4_wM?QH>QS<|8oGZ{q(ihUw^%F
z=3jpP^Pio0<ELl-<)?4F{`${<_OqY;{LIhJocRUHzOrO$ME~JS8K4BHeNuWJ&W;08
z6>3{YdFS#Zd@(@nv$l`P>8P(L-vYRRD4(A6K3gC>wGiQN^o;t8%Bd~&8RgS+wlq-v
zS{f)F;cxVe`ish`4dIFM&-NMNo9Q#^C#p|$5JYP*%AfAps6ORKFc}BsQ{LofA7BxH
zo+5zi5KZ(XpuEWtmW+Q=c~m#bjq;-R=vkXj{Sr^2GI~-uL6m+BKxqdM<<olvlt)1C
zVJb{V<<YaYtTr8$)06TenxZ;Z6{2!_5-pnnQCak)d`i<Zf~YJDh|=^VJk-ZU09xAw
zlotW<Wif#2d<H;mx&S_a@~NEONsgz2jQ}doRDtkBU;`FZL6`&_Kw0G~M8(wRn}B-&
zR7CWQR^iV9wdvaTC_j2eG;{(8XRZ7Z52&1;GC%>)cnK&kf-ooiBswS+J!#C8rYGeS
zP@3{0puC8VsK01^MB|P6ik{SlWQ6Ea0a1G@r#Yndl=l~aNCplAD6bYMFM=qa>PP9Q
zKYEf3L=e#xje*LeaS%T0e?MRVa1`)7AnK>l^JPF(7WGfhZGdDIs2>8NgPxR4&o2W8
z0Xl$aqc+b1DF3qnDx>%RRRu~%5arSHe*<dYbCX~%fOt+o@(`wEnP?!OH9<i65kF|n
zMeB?BLGQ#9dJ<5&ScNbr%=<Rr1b~Vrk&z?(wf)mO@$Q!aL<hY`@K6;fpJao0O7b7g
z-Q9p_JxsM$UZ_G;m+(Y%bpxosh^FWn(Lm3L4oYi)+W>@;=r{<VC*h{NsE?UEsqfnX
zL=Vk7$sYC52%4)9mD3ou0+s`)i0Gtuk`K~t1hwffr>pB9s}Pk@|J!SzqY4Iql2k<L
z2)<ecdT#^J^HBitp%!X+L;2qYMCHVveSqklp0s`mh#s1Af@s~+lW3v&q5kMe>w`$4
zGLlnjOL9Q8L@<?HG@2vozZR%Jf{>!{Gt3D;|Evo17V(Q%OteK1@x1m){I3Nnt9`Gf
zfzmYZ^=OFl_5i5Ah&Ga~UjQN+=t=L>L9HI4bhK8YXVhP#XVhO*PPEh5qI_Z((Li|-
zOh*%yNBu`n+GC@&Fqt>hH|b6SN|XM$8SwW2k~P|Y=}9sf!H=sz@05)4qbIGgegNT%
z@@U=G0+rPQjlK3gq-dNbqMPW5;CHJ)??fZXD6J#vkDgBfh&D<`KzXE-B3N4oh-cJS
z1P=p9UqtV;A4Rm)dp-xa4?yxs<+MLVd6fTk0O2GalTAW!8DPmIpu7mEh-e@nI>;U%
zI%)5CunN&WOnVIhm4&JB^B<}(IgjWd`1LBZ)IijK?UU#yi1LUIlKp@<e2~o2djz%X
zv|gHmAFl#v{v#lIYRIUYe7p)o2UQ^Q2@hoxeZ>3P{vvwlS(`sO9nlb}dE#qigOL7=
zfb=Q>*=PimPw%u>Z2`oq@C5+9lifkj0)S|sCqWN@o|H#G^pO1+(LwyBbhI`iX3#t7
zFM5(aL^_Rt*7`C4*}5+RBD<QNN2Y+uI{y0r%8TfTp44A0M6^Y85#PT8pgIw+X#XKT
z5KuY-dMCcrJ}0LmxgtJ9Kx-hf(`f9}S40Pu(R*m6EnZAKS_z;$+Ji~I5zxGn3Rw-H
zGRpfrfb5n{04gV2jd)3UWTQoEjp|W;9#BgY^-VzQm7Y{aPr^??ydj`8*^cz2ety3S
zl>QQcp5%*>ZBI|K6aO24(or70M?f+c0m)zl)Hgvy2dO)Hk9azn4jLcz9YI7F=?wCZ
z>3MGz{u1!ts}SXpF1xl0#Dm`k&@%!mqBPM!K>Gv%(HrK3dC}YvuP7Zo$u6Vxt$<4b
zRCYCh@}fQS5&-Sz1hj_9&LA0>3Zk~e50V3tC6ayGH)ww$p!ey3_Dq7P9^oNf7Qr6?
zB7H?q%8%9!J!wn?lwJj(=fwb$6#}Azp0t+fNqU0v=t=Jcl%~80D39iafaswylKmX{
z<MfQ?C(3&lU<Dw`r+K>xKzRhTf6+VXE3%^rD19R!d<#Eobt}ys^<N87e?(IRQ64?1
z9|B4fO*DqT0gzlpK<|^`*d#a(sLiUSfzl*<QUCO${s<^dI*jCtbSvo^0$TTf2cWzN
z=zTgM9@PS^Sz4PBP=ECRhY3HUwO3n4wgf@FJj#Em3Y4A=)Z&{@&vRg&1M?i1DF;aZ
zkv^SJzceA-JfW!0i#jRq>kkFiT}`fAlb&Vrx%(E+vPI+SmFx183atq-<4J{6zgB)W
zLAOs`dAicOnifu1Wya-i9_5UizPaMu6Q&_POkB^ZX?)6osFd*OFqA}KiAdQDS+Z0T
z6&47PWl%e6oE(tQct956O1UO8*yDGJL6fL`@N`*HM0=!VUt&Na6V?f^w;NR=Na{kO
zMsh3e|0(GL+fRKTGj^!U3{=f=#w=CZZ)gh3NSh_p$hldEB?L<?fEs2gR10l_3MJzJ
zXRf`*aoR+nj~{ZR{aj(}hLpgP!vjTUgOLzQ>7ub8ZQYC_wu#jE*59WEh<aI~&EbSN
zTxCgtm1rzuKw}~)CLSgG1Y#OvdmZ|u#sf(Sjr+_Js@Zx;eEF|`iHha~&T~PVlQA+j
z_bXtYu$gn<Z7gHKN}f5V#%f-=^<7aqP=3+NSv_xUyXdUi)ob)Np38ddm_gn=$7aB!
z302-U97~dgFc+X!UU_CN@Ps(#cgxxG5*+KBZJS2*tyBN&R~wbhKL5O?Y+&}|soz3A
z{#9B^3VaZ5z$by1(JHaE{$W3;pA_JO=#D2c(;>6EGu9QZyjeG>{O8Zsr{HXI=X#yZ
znF!wY2N#~rc<Qz}-<3HWRttg=x?5GTATRb@GQa-&WW7NcS>PW-6j@ag&o#61$FI|-
z@m8Q-dn$Rn<0<=qqO9qBw`tJlx{j_hcRTM^JGP#=XZy$Xk@8LH194@|H$S|(O-J1$
z2bAUhtsAJ##HaC!edg}-x4Cf)v>Q+Rx26x8290oY_2u3FJZC#HtGws;>#m2h%7mtv
zGhNAko;WKS>Nc8d6;`*Cv&oz%Y_?o`+i+~Iwn<C4^b2ogTzj??SX2LPGnX}EKDXpt
zaSWkl#y%O`!Z|mBqShd6t^}5`m!7<6uJ#d2;8%VThRs`VbgS&v?@~u|19NSU&Y8vV
zw({ZM3Ii6lF^R}I+U|9m!=R@{ShwsPGnc$8u(tz)+BOU_!CSro)AT7@|3>+)^rLZQ
z>zT6gasBx1e*$|Obzyv;49shD^3w>d@bk2}ArkEq?CtR7(5`^FbF;jm;pPSrus~Im
z!Z^V>qEzYJkH7k*nuE!6z&NK{3?Zw0ZsZ)unbdTyHc~=6*SdNVsljn9oxPsL5zC72
zq1_z8EQcA)f5WaTpZmz<GCH5Ph+KDa$+Yj4JO6CjIy0^S(U`N{lD+r8&$!=dEB<?u
z*=YyUsKP9ztPz?pf3B_4se7A6DMmSWGIpNFaON(o-6#&uzW(=fvH=DYIM)I=XY)L7
zd7q;>{_oQAwuZkkAMl>TfVcYGpDvoQqMp_g`PKX9#`GqN_>Vp_W5TAbICEQJ+)lF_
zVXbVsrcu%C^Jh-k^tk6*S5M#L3~S62HbX{@RU?j3@M11tKIA=nF3$0?oHMJ3%}QZU
zH*QGT`AgYcZzXTJ;cW?(jUSqh<ufmzV-cKJCo^X~)vWGW=NKri+x#uPX+pHu?e!cp
zLG*mgd+dHUarvBJPE{{L9&@cN&uMVujps~>SqO(-`Qn@&6O2=NuBka2B?zhNovBHh
z{KdaUwJVnmH7Xj<pHpPxXs1s7tFvrsa>h$R*xcDf^YQL+#?B};Bk7+JCR93~Wo)Kn
zn6}>eyOA7w96I~0ziGnW7T3GqUQYZu+NyP%|9iB$ty8~w#eBT`pQlxVGp%5q`rOdm
z?e1>_vm1<^-;!r4T~WPxjzyf9>617%AMTzhw}N`-vyjc5ik%O4&q^qQ%HhfBTORIa
zZ;yK>Z>KwJ=Xj%}Zu5Va*G$;_1@Hg(7raSXhB1oS>)3iN&gUJu9=&Im_jU=YogH`T
zwVLNxJ+4fZH_x%DxKpoeo@4d6GF9H(bL=g)xPveK{J+bm8q@5`=AHwy>%UQL^;mrV
zmrTyvUoxRts~cZG$ISWrC7WS#H(C?3&Yxh6>a%SArmN3)eg1-3qG(*5-`X_mA7E(k
zT|eAhc;b8Glm%axtJ`t-W4CpSYBP`h@NM`Tt#6v_T8>PYt~{EWP-RY$O~5?cm-BUZ
zqgx4c79V|EeF<u|5>UVX1jSgt%FJ^ymveP&!RCKLaOQlEYR><JAc^x_iQxPllXJCf
z-_koKv}@E2v7ck6dd1@To85EwYbLdN{G808K*?1e_(EyUzRmsCey5WDGla8+d;W}>
zXWMpiyUOV8le5nLea_9uDTg^jKP4E>XIG#7s3y0Zc9fPdxk;mUlU4rZ@7SEp=COy)
zL8>OvIG3j1+bT#kiH~RbI<1h+0`FW-C0z=fMc30*oy$?Gw=O$BBcbxCEhFH=TO9Ew
zPM^=eWipK<%(&PRK6#!B;9M@V>en&O(O9k9{H?uXf_bdl>p5nskN@t1dAob=BHrh_
zvYfFxn7ZQh`^zkh$Q8dl>ri|{>fQof(Xg*s6@ajFaZRdyk=;(m5S4+^S@k|;<>@DL
z%H|Ua=VqAE|7v&aQ|G5-%-h`)CVeI^b1Y;t>2gMO=I!nov8lFFV0ZfszEtU1vHBLd
z96QS<x8C>8+TPD8J=fdAoSmV)Z7z622;LmuhRoElZf9BbCS90ii#J^sX-o%@-#r&Z
z*6p%#(+{@UKf-^VbBT73{YgAmep-9s@~7;Z`}YJt=iS@CC-^<@_=zI@pm(qL75aa4
z@Cbg<d*sY#(S&}{o1T|w_k}<4z4D9}{0}?-4v{#U>AwYf75~RhI2vd3Y5&`Ex723*
z+pKbJ%)3<kQlo@!{8FQmno2WFPPho(;JOK8-b8E-yZ`!MixX>}!`oad&T}ATV$*rT
zCh}wYxAU4~b9IW$-cJ7!-Sl%llN#r%g??WDg36r9>s<Z^JB<FLwzIUh5l?*6|ARS=
zO+Rm-&t!Sk);XV-+FNQvzop3M4fLn%e;rrhtvArkV7XXtwz-o6oAy4-q-K?_BMoij
z+EqEDG)(kK=)-2pbgfDB#~`xpD?fbiSYCs~%%jGY-zYc0aTeL<vx+*4;nZ((UYo-8
zNj{6*xt_{7vw7xi^x4kl98YEP&H8n=6jkfbIHoca{21k&$r#zyGwE|ib)YZidMBxS
zd*!TS<qfU(Q$P8^j7B)4N^>lQ^H;}b#PzXCkU}y+-hA_8F0AWHlk%1#-!_18)Qy6l
z>v*hFUr5h~(Q8fx-eN1g`m0!UR$mJwJ#`_ndFvK3cIno+`;Y3Y-^iKN(*z5AQrT3m
zkNe|a$ZY)W&Pf>DN$=5X<yU&6<heiRS`nW+MO6&*gw2+f^BkM!SRD?W=N{_0?%542
zfm8Y4sKbl1%$i?Wvt?Xej!m<DH|*oqp9l@hW?N8yH8k34r@{Wj*QfbU2T8ais7*(C
zwa?0@HrKw^NtcAAK8_Ihrb1cy&P{bt)MhCPtsOuZctkpUt*tYj{^one)Adv1@ymd&
zsgPA}e7-)8@!WB2<9YQ{mA0?dFF2drx`NvPQIaNODmp9g|5SsfXORucl8p@GD!LkZ
zn2IdaRx5XYYZ@A=$Ve<G8GJNu^3ut7G%gHE0&XD{KBuPduJpobu+6-<{)(S@`w2Ct
z6%QpT(En#lzO@FPVZBDHYyzI~mzREW;dGIza3ujNp<^YF&^H3>)H7dhR5l?W(~uMb
zN~c<=?8?tb(~w641rT{iVYC6#34PVPSjX+@zAB-GvJnu7qz0DOAefx2_`g@0dRc&L
zrD6KjF~S4n34uPR0RF~bUH~8T?BZ%Ao$F8YG&`&~dmY9)V_h*eO)&1%p7%{b4HfMt
z@<SjN*StpAwa-`i)C@u0{Ty5fAfXH3OY~NYW;|W_{!gciuqA|XluCjGYf7<FD?j<2
zar|{tASn?{8*l+=*6P-aGVlA^G^5_nG52E_lOQ;1+TeLp&$JlBmbApNn+8NSz(v`W
zA3RK<4H}P{#(S&8*kKAO&_4`r?6=Yq0)&Qzbs@c|ToOo_*m!n56j!#-?D}fS8}Tvc
zzz-FLwLtwU$_zUA%CG&0kG)+x-96aWf5Q{<6V1tKBr=pPNXpcP36-m#{R%y119rp8
zm6I){2Bf{owvM)ohRB$F>crEHODC3S!MB;FR1KAuM*p4Z6ds9%#aS0F{am1r>XwC>
z*!FeoIibQzdf2p)hF#FG$s0e74wy(2)PwOo5DPcJ)@a0(UwO|T)k9K~r)ipkKiEr3
zpbP&r=&urJZcHTmhhMEhP&Y|<f&vgp2@u*CuDP~>z|=GuL(pinQQc#YPWJ`#s<AT-
zQ6avs9~=+YMm<b=P9$gwuCdA=et%Ni$**V)&LzRT04o`IQz2xpJ|j(|2LhWcU>+<T
zOh$?J_=ccXTK}YBVORjdXs-y!3eqGkjoV!M>(dx{G*BQ&5?w?g#ysVa@A+Wk&cc#v
za|mG7Af2K?WpL>frD0KMx>rXzC2j23jnVRLh!w-cUxEOYlEfT0g34>zX{I;A)d)jP
zzIAGN8v7k`SDgfqroefDCKxBT2Gv-yvhUGp2&73MOeD~lT66)-a125LA461|uulDG
z8vTM9QSc9HtE7A6T`3?OA5djet(VIBk2Knvs{NC905cf4sS6f9!_Qg@C#2;kZx*dt
z_y~#ieTV&oC#=;J9}B4@z!K%ga=w9St97Z>7iQ)u6sOy>VJ4RXQykVVW)Uh~7m^s?
zRK{*)JAUY9N(h&KxC&_L!or^lA^WY3)A$S2nhg994fqj~h^$6n33q*X8l{4!8V!`N
z1muy$Uuuk!t$DanZ`J&O9(>T41Dp_(DP`?TFIHPNew0F;7ixm3^Z-!2`ocRW`v!G=
zfD#-A%r?~}lGQXV;fC(T7>de=z6Kc%STwamk{t2D$Dl44U=8bNGXsC&zy9&e`~@N(
zi&%@tXw{L(R!4wkF-9y+<eR9pPOWL0Ke0d86Z^mvB#E7RpQ9T1dC%9TvuA>OGy6b1
zZD7ipCC?k*DoJlnSzA8-&(j!{K}fEOBiQGr#P`xO)0maXF?yzF-4iz<sM%)>u>F0^
zz#o875~t|j#yw@*f*%qj=yRLPSW@*RCY!G0Fvm_x+$pJoDogH5zqQax^Im67mMznr
z?S9vV>S{x}MjJ`9)^)zR`~Gg$rNu7gqX(I<@JsxL^&IW6?<q5=I8%f{y;XMCMOIp%
zevb`bxTM!xtA9cDlZOs`*ErI*)L%YijjZehxt@5eZ{47pZk2YQ(tK~P(-m9J2Rqs;
zy1$RT?|X*3-G6Xm)#}JvNBx)il27yW^Y+nA$qvI@q4Yj7(7NCgMvuBw+hqHvjqEoz
z4W+Tyc5Toiyt=Z&Il4*PyJV%f@iW@f?eUfBkA0nOxU_G5K!mqvUq2smmY3P!&B|dv
z{x#*t&wPA}Ih$qCSUh>c7e#B4z-S_&55)^94aOANQ;p!){;*NWr2N249+%%qrQvJk
z(g&)9O+g>gLL`QpBup}TX#kZoGdM<ql?W8U)(xCf8h3DY6Aii=&mJ3OkO;{fFRe{g
zR$o>7+9*vU4seZOu3NLR{r0-~HJMcvG!;!z?U$EB6HEgk^9frCa{%h5K>YanX}!om
z^8zO@5hCDg43@Csh6Rm_qmuA6q(tHp_!*4_nJHI3KmMEeQTqwcAnwYlF^6!}Q!Nel
z>QARZ7-A2Y1`?AL!)XkaUw*uCVYMVgPzqeEX)0elJaq+fddAinrbLGwnVgEg4{S|N
zy%|#L07KxW5h_?-4T-Q$K03Vsk`@S2lE_RUeF##0`>&^^kDNR@P=cr^00vi2fj`-h
zM#h>?9Vtvvj3S!Vq>%Iwq9fshK1BzFIG`Ijb>QXSf7gItCx1K(oE!T)GZ%6{myi2o
zUeI~rOujIgd~%=A^%&RKz1)hyzagr*5g%@6is?L|Oz%Pt!GKSm>ifkw)pb*JMgl*F
zJScK~@T8+1a3}DF>Nde_ekCwy8kABt9a{y*B=Ca6cQ`+k)d&(o<y(I{y&p+V9{f?-
zAp=sWr)n4VFz@GTWz#3>mDJ<`5ik-XNGQmu4Ew05GCBF&52rf-53rB}SsgMlcnbAb
z`QQIExsOTj<C9b^AT~6fB=q-q{sIzX5HNPuRNueSx?;rAI1~txNwqcBdJt@=U%z^c
zg}Q(0L&^d@^(JR+2K`p?G$0W-%V+3N>LWgQOAaNmTVv`5(rv9ixIax7xBvg=qd$pb
zsehYaW2tikeA7$Q=<TXBg7wpaRyjUR)Nfi8H5I1yCLsyqR8ib8sdEYYN_~Lf^T#`9
zVAMp-v5zJNJ9?}0tlX>D$*s+*8ic_elE9EIQEa@n#(0{3Ao0G-YfKuf?Rs|l`1nH2
zLprT4D6F!v_E=ty1?Xr&hd|1smK?m7urtJ^>RwNnt9{fEUAcWzwLKnk%wxVc{ys)>
zRV$W)FUR5qqaP!*S~fNija42!J%*!7A7Mt4XsqSJxOoUWLIuhahtsXuVRP*M<8}(V
zx$;Bf^Bqzd;R5P0vO!2lOG!WqQ-lW~qK`}oN{3BLxA#gx@iZURL5B8IP}h1>J0Pyy
z@fVX3dFaRw!gG^L!gmYg1*0A-j{2gEYkoLBWK!OQiI_-fV4j2+6wpAib|yk8WI;8v
z;;))mOm7h<iCmHs%uLntgegP%88~VQn~1>@?z?;9tuP{zu*zCMZ}3J2BCv#W5}+lV
zL|n2;cu=kO<Bff_$2S4e5Hl))1tFky6-j^xWYTLi<;092KdfAN?a?qX{uv+w+A)N|
z;tnoLg;XZP1ruVyXTaZ54O6eIl_JPGiF<_44<;+@joJiUL;~7`&?ZAPRDu^hd<$w<
zp8B(}Rq#m@UL`P?A}=ZnXN5ki(;l*vRt~5SPIiJsRKN1M9Z_<^)6&NH3A#uEAOIkX
zSU?=5Bk2&5(V7}>Z=L$pXUE?>5~nc&Ly;OQtqyqX9f`^Eimb|Y_>b2j@R$cKMicM*
zo)0}0*fOX==XFVs954Vmu7U6ZCuk1}DVx&cpuX|Jn&S#f%f>u(K-vkb3qegQ8}q~N
zlF)PHwi3~xGH^uby{c)G)NO#Am_?OBxbN2^UIL{S8~Y0-So218$%l&m5|78<z-5vK
zd|<)U7F7F?PaeMz0+Gb@$hrd~&>XwemKz{hP6~q)oR{#J3wHCpT!RHh)WSva7O=P>
zt+Exi*2gKB5J_2xbNQQY%B}d}*eI)nu=4m|DT_Q3GRlDqe*w_}5={|VtkpGuXIM@-
z_+R!;jB60NIKVIn{4FDeXE}xeg~LKsGSmrEfDBU$G=cXr5#a>v$CU9I50+7gKIj=A
zUXY+E1Y3fOXh5rlcuDMQ39WrWWTmtA_bVec8lbCw1d@mkaGr#Sd@Z<a7(#R}FBnGP
z*^zfw{TE^Qt0hsY!4r#AC#nN1kRM#|^8&jBG!xlDK1L99Uo(zhTr!T(!xYjif+;Ly
z`8c!D9yswy9Ki}8g!mg+W)ZsZeqrz#Wnl^b;v2+iGz-p#d^(hpkJ2ipe~{Xkn)bkW
zoP{OHCji#4Ac-R;x~4dTQ>-sMRNDnmVTFx#F~}h`Y8ptZn7}10iHM>kIskEpsZ$@B
z5up?B{yq1li$bcVamz{=0x)1@(OSia<rz@&dmV^RwTnRR-|XC}m;Tec;xByQDf^Ya
zUBM4SZtn|zCvx58C$eYmcHXUCjvt1+XFGlva!>iD^nrN%#Bct|kpoKn#1&8Bv3&5=
z4Nuv@FDl~sN*@CAw<58<FZ`j%xkK`~e=SPz!;rzxT{@e?(ct~z$EJ1QF^M5yl0%rV
ztI*_D!8-M+pGN6(e~z6J1SS;3IRq>CY3p#0BC){s5Yj^%GIoA_NX5xsRGVayUTQM<
z!;jXQK2c3eic+<;!!3W}jX4@|&8XQM|0BXjN@|=?yoB~-P(8eOMp@W&&;{Pd=}ZD8
zX+wHOP<inEQ4%;YU|KB!c(n0XH~)Z;03-EGI0ynf5&G)b;|6UL&>sKgmf&hOrN>Q^
z!%@?!u|^xRpS06xQu1s>6mTOQ_fN1zV_$?`q}EWmWXe)^N=an02>l54TluShs3HM3
zU|xhaTaXnPtrnSaXjMWmQj=rKU_jSy9>e6J3rr*Zg&qX%B<f%WLvNKvg%f@lB~Z(y
zQ+cSpKsI1mAVvSSdDddsNH7KH{(0CX_G_qZGzDlrMnFP>E=e$u4Osz$f;cmfqMD9Z
zRATIn=5ZGxXk8LQ!l|b*peFc76bA`<34qv6bd%De&k*U?M`^)fDnqUis(=|j&8`f(
z$7VSkQBX*X2(bppgAY`X;N{<|Zoxt2AlHq`f+u<*W)d9$Y7Um*gZ3SKjDtlHub|+K
zzVUn?y!AauOBT~+#pEnJWEgWbl#XMl+HW*?EhQ?!x7>9q)|0lVF&!C?e_BXpvtvdv
zF(WV>f{zFjAqa*uMqicskda}o(h}UZq8CML7QWIJv?e?jI7!VR3W2akeT1WD;rPcm
zLeo<M5<n>s#vmEKpZeQ85?(Oy!1<__g}sC?6m}yIjNzISAW3`$kgG>e6Qh@%K3g;u
zW{D>LGM&i|9P;NbA=3=v8?-|wArR#uH}Dx0h52C;3y{Q#{#hc+8K#*t@QL?i-iV7i
z14}fA1VsJTN3kq{3=rZAlC>Y8mCDeB=no;tqhu>rKqRQg5H!}}*$@hieCn5WUKE(K
zL@|g8a0hV+s$GS>)d`E<@dU+zuS1J4gruM&*AmfrQh4IjJNrVZ4^aX;WQ{6PKM@21
zfF4UW6-5(QWi|003}$$m#2w-ltE8iw!Bq(kh^~?i9K=@WA?m<OLbVV@A=9eb0R<*;
zA*e#tf}!2|{a9Z>A2{qm%VANVS>Qu~UQ(@unErW#I%yoH$!QN?QwfG25Keo5249B?
zfxU%`dMm^Pt&MiYOnSDcw+PK#q$;PLe*`NK`yDMmbO==;Yv=^(H0UE5Pf(b|FtB&^
zdQi})P!jrSR8Ufg{{`nsI`wEW)6^i2G-RdKHaySXuFJ*<H=*o3;hLQn4EPvFZoms{
z*K*`y1^NK%YJ$&2zG<-WChZsuM1_=DFnWj<lsM^e^r)2b24t50g1IR%q2~>lw_MZ`
zlu+bd_t4i%m16^ei?tixSHIM%YB6%6P=Kx#Ut|7|p$?+#p1}AGzHbEd<ue#AT59)s
zTz8HSEMRoa(5zlF+^Z#QIzqCPzG2?fVW=Bq<rN(jTt!Um^1F>SK5Th?t+rh8bvP2I
z{_rn|r{p71$AEwUN(4M6siY!0DG82>g6?wz$@~CI?9$K`Ts58K3F1PAz9m`;OxJ{N
zcN?(g6E?&?rSxGc;*Nr)^+&f5?#O=vx9K(L0-Owp@B>Ez7|H2Sf|qhkDWj`<yzuyn
zL=?LY(PWYMo1h{`z2Plq=-VK~rVdv9#)lc!S}?Y;;RW4cXart>92IGN<h_(*;Htp(
z1QrpAQm83`Sq3}tE*}Wak2EtSYO<IVbf!Kr{{R1xbO33zt`J`fHff+wQXip*6m%D<
z=zwKRCzhF*4(pIYEOV3t+)UwPxuO#X(f_Yzs69qe9Z1v%4I<d9P-?}9BZ0d~wIW}O
zvIu~M=@<h96dM#YTmn<1lQgj93iZY+r?!UkAF#}4)!DJgi-ueT{$1EHxDRxg2SQ5o
zgmXDM@f$my3uXo%&LKs&@j=59NyS2Ap;yN4a-svPa@K<`+v}i@>bIag5+=AhUf|x*
zmzvN|>7*yneb>O7R1+=e5B?GLAGRX-ED8E5j$w5q`UM&pkfy}aaVLg>`xtt~`#Gir
zTTy_&8^iL*>0{55w(&``g&hav_~eukR`M*-PfZcSg&~lOLo`Ss_J4BAg6~=B<gH<s
z@^w^y{Q7s`XGf_sawO41?HGfJhz`=|nk3C%C>BvJQ^L!Wa0)Gm8`e;&zePxi45wYT
zm^{9n+GIss-23h3^YLhl{<DIAlmBR-&e2x%e*|Dd0h_BkE~c<9_z;OPz-CTs2D?~b
zPcmA|H0yzbpx)O>n!G+>{bPn^0hQC;B?t^@Cx{n40M!SP6ea^|KvS?$gAxc>)jh=4
zhe{Adxet~Bg%*Q2t`3!^Ci(EsfdUjo_z8I^bif;Ve?S2I<YiJK$p^^z#E1#dp)8VK
zwV=l}n7YWrmWP5$^PUhBRjUq~2(G4sB)wM0LP-MZC8QV&-6KrYNf<9xS>^BJl#!(m
zfDgNd%mHwPR32FcSjbGZ(o#QsA6Nlob}5H7tnfi`+sIzc58{+$exNJv?o$;dG)q&W
zrvu~Oz?_8{f{rg8dIyk!LJ9w}0<&2<r$KST!d8(LObFj3FwaKXb}7g51vgC5n<8T~
z2l$&n3>Z$KA{NLBStoD^PLevScAyDt1Tt8*FT{9!=F-ODd$4zqa0TD7;VvfIwa#7}
zJlD2)IiHQXHgG}}z~;e#@I!2h>mp!niF?)6LUKg0E}}Di@=_t6ieh4}Ds8P8fDM*e
zv5`zRD`b`lvY_Tv7HkQ)Y@(uL%$G|O<tBwuOOj39K8pWp1Wfk#Hg`eFU^aU&bjqI4
z4+RT)NVGs52*Ey!H1?emECAHI>6Ukr<kAdfVl0ntxa^`607t-%o*Fn@mPq0jyWsL#
ztt(&@$pVqGkL{*+5-#i%;R*<3jM`p#6+8*IY-<v>Li|(lXB>hvO$)6p6k$R%2s+uq
zdvF;wAe{ODkt7Zg=t$6P(O@cn@|RJz2i5=&<bc4(a3ZWEpj9bOI<d9Xf8bk(I5Bpt
zOY{*g$Xq%JcMx#XjiPHwnOIp;EeZ2Xc`kiGe9?z$amlr~s=C}=DCgBq&$D}Nk7%_O
z+YTzy3z<CVjhX{34HHpFh`Hyt@|afM?s>WgA%KbMJ^b#A)|NpIXwCVUOiL?f(ZFM_
ztD-$v1LhQAT*n{^F8WYQg1uLDH5+=3yD`iP_)>O9)#`er4n^3qDRGTrD#r{V)dwS2
zGp(Xwq8mj_Ibz8c9{(ivBMhnF7v!v)FS@?P1@4Y|jOT1u?(s(~H>+xr>w`ENh#V*o
zN{pfl_*29%c~sS0j1vNgD6HgfvZZG+d~dI|SHqNIQG|arEE!XK?_XQCCa4)ZPl9b_
zB~|6n4W6p17&sQKFWa1hD9@5CTe4J$8df-Z&(JLrS&B<84yRQgf@OoPvg!++T*A$3
zvN8hz8)5v3a#m~=?)rtDw*gQCGBvO*O|md^LMG;8X@Qk)!A0YOt6~R$>a{qRRE9YY
zw1v%NAG*$$vzR{&H7$@RP(X$NvL<gp_&0XY^Kvj=5j(o(^><=WuH>N_1Rjh7<(M_!
z#~Scex+?&jl8uE`8d6IbxQDff4>C|}+s8c8U%Ucb@Hg(bqPZF_n6_G2JpzuKR+|v-
zBf+%|ohz}*A8kSh5D_}Dr+Ff+7^n;g0YW3_mU;z#`h;YMD%-VOKkUacQ2-}e5p}nh
zDZ1RpDRid8@U%pjyD?UI@>ymP7i}mdeznAMYJqc}AL1E%p}dT11)JwoTXi#bVP7U|
zy8_EWj|wW-i@Gwddeh8d<Xw5+9-&!~++$h613kXwO3-AONKkJL2)^Pe7(-U{u~o{V
zX_j9re3nKP!^!}LJPif7Jr2z11)9oN*{HS9RSTF<YoTmoIN&foG#83N@ntuQ6)R!0
zfso*z?y^B!q6s5_Z7mzUI%ZY(E028H%B%Z^Ug*i@y{4_%f}bh+8Lg+dFJI=xk&zzF
z&6oG7Jfm&(GPa$uujbc#nW9%v)pC=o7Wb)51&FrY1F0%x+Ibvxq%PZsG{tw=SRS^m
zZEA-Wb@6Ju@tC6c!A9uWn*^=DUC~WD)1k%}tx>k=yL)y2%R^9%n(}eoU!!>1BTp;$
z=%(d3oBu*vli0(ryh^&ZShO=2_GpDoT(y=Je0NCokNc`!c4N6RZ;E+r#CFT>)-0DZ
znJx(%%i<BY3Cc^AxZ1_naZcL-2XXmqS35M8vbH&XhqlAsqq_abf}DX$4g0w%cvuqV
zYERGmNj|D*UqqRv#5ZXDuvwHnO25~h__98v^baAw+@Y1l%A-Fz>|+~qGd%ofvvSiy
zzs&J3cnYIOIL{XLalc$pqYqW0Qj7kUb(?#=wq2_JQ<$wOF8-BOU$=vQ2kD3^u1ec%
z`>+--tb~ZI)Zk!hikIr^^*neY`L_Lhx%P;d==Jb1%u|r9R0qH7)x~asv!0Z2wc1mF
z#=FW<(><Am<&JFT0jFGan}lx^KmVR`uB&M)&$&H$?v<N&@>0H_;>2_)Z3(8Mwn{xc
zZsN&({J0&<Y<+gE)@jEQ#|QJS^`Pd;#j88F^W93;JpS0OF83+rpES+On7jP!Q9p4?
zZO$zAuCepJm9{&S+`*mdAuZp!vRm2Rot9r2-j$85%HQYZ2lT|LhZ5y)JCE@_iANHL
zw3E869pFs~@r}Dg%N6XNCIO_%u9WM^2)UuWReZ2X@XMP7zeiw&CgDg|6EC`%h42Xd
z94UsTf~zP^TqqY@sF*$4Rkn?|jpU8E30~~V_{RtGqe;(RoUpSoEz=dNsH%<cv?$#J
zBdNY8HC{Ay&odRz+t2qX!*IIt2SB5iC|{H~35|4G)5=-p^sC=vO)e}La1LC?!doa`
zpUDkm3S2IJUX_csnsf1D740S=BZ01R@fnphaqOv?{m?FCDtG4H+`uM5&Sno{27OnF
zYh9A!yZiYlb{wy?tGUpH4bduo*~|@$>|C^5JE*tV#dNAeDQ9Dek;E{truAb3`2q3`
zb+4?5*S*5-&ImS^OCf^|mNoVCuze7N0vI=-TE#q((<FF3T(H2nqs)JCD`${kD__vG
zCdi{#UThUW15T>Z$w|-F4)S<0i&Nhb8_qbCKcZ8GEVDt_Kq@XC)LT($bKi(oRutIb
zU>WAMkKO0lIHy^zd8&S0Kf{6;>5+V|$+fcu*D7Xugq+qSlr>BgtU<Ra&#gjU%?;#L
zxfv?n1M^r0Q^+&Em*)&Jx1VDtRIvXb{E{iU2_du9RdQV}tSdXgk@=j>rTv`k=BgrQ
zwtRFyKgg^b3>dc<MZOPY4Rc8EWBE3n$=w5GO*x%eVYxlvjw)naTNq)vt{%Z!Cgo0m
zkg_evl3Zv~bAv9owz}ATe3#{*@>oxKnCB2gE4oRF&|F0pD$Io^H0*BqQM;5MMYtiB
z$h(=?%XZ!^_3A0HTr_*vYO<nal@5fhU)K3W2nbkC3`-XA7OHY<;a!-xa&a(|=eRD=
zqvi)jAt4;PB441V;5A)nxvr2?u>`;r4i-seSnxUUsb^tAXd33;k;SlUX=Md5#N}F9
zlj7N;OHz`N_Gno76kmMK%XeWP@s3;sp<S$_+Gf%BWe4#UAM6nm$J6;Vf<cP%AkGz5
zT>7q2Rn8VwzT4JR4oSj+cb<X>V9klF22NR7ke4sz!J>go*~!`x`=rZMdq3}rDSk%U
z=0PF^{Nu3-^h6;I5?#FJ2R<g{AclJe*(gM=8847%UR-$_BClTeK+cf02OT!d%r$p|
zF4%Y$qK;-I|6WVO+L1JDg=!iW4f~kn$<i@92!obkSdp1gjbG%j61K*2*-<vie2DNM
zrVeH(j?_KZ%0B2&aO~(Hi#MY&c4=7ouzQAe#4l-#shFni@k<DFD1(9yt9HeI74B{(
zL(3Ba-S3HDLw2Z>cyQQ<urzb4OYpHVU{O?6f0|VO16Q#E*OV?TRQn?~3|zX_Xt`dC
zEhX)J8)*ZeD3Z+}N4vDb%EQ3060~-teW?97c%k_w^T7;%7*kb(zN*+8=3_3?e?671
zN5Ma-KFFhk-+?^r8RTM-e^MU;dzgHIqz79dtV4Gr$ekzuS9`*Q-b1ismQb~`C$-x4
zcqs-=<GV7BE=ahsEO~GU4=WFU$>x<~Igi0A^{flIr9;$pJEp}Yk3lyBYf{%e<gzZo
z#v;hXbmqbAzS!G61oKnzlL8!D?8`$GH&R$rnxA^`2cW|BZ7VqBfe#Z4uCNekUJ!&J
zbDvxleA>u~u_QbY`Z_rE$JkmplgySS9ln6F7B+ahf&~MM3!H`DfEtz4S>kgL?!u@{
z1f*d|Ba6m_{Sy{4Jj0k=fDgY95my?N0Lv(t8q`C40e&YX2#a<UhMoMN)&d?8F#>jQ
zn436=^OVZKpTjr@wJPQ|mqyA{<08gEc_N~eCIS)&bwEYK1p`8Vn*&C>IS}gEWwBrM
zw6cUfUD4KZPowaGB_VQRBm4yGy+wfW!`3RhDfr=og*ZcpZ}xcn9Ud3}7X^$Y%?yT6
zk9h0FD2Z~QXWn5=)_9B}3-I_vqJx2a9I;rUEN-(I(@O$EE35=@@^rQvj7XAXsVpfy
zxBZ<%vVigWm;zOU9|OA;eivbfcLP-LGEo<YDA^Kx2;U!UH{p(SNf^^^yO{NL-|(~y
z`5_>O8@N;rmJs<}aMgPI6su1-h^<V~1_dqA$I}#Y!#p^Z|8y5k<tXTbTGNDeJoOBR
zeWf;O_Jy$FUCD(zWUHR5<GjbEs0jRfCNFHWvyxJl3?Dv#h=4>V$E^jv0jnm-6Ipnx
zj%a#*2?H2}D8fH0*?l<nBu<w`V1M^vX6-Z2eFUSz9Kn-XoYU2^P(X-+3n~eRtGeho
zm(|g8j5to25Dv*siUDGJ1B*>KS-O^UEG33fFe<V{R<aQ!pvXAjny2201UZ;KO9_y6
z2uPL|1l1?!lO&uHL<s!t!#Ed{eN2vxGHe_0pOX+M_~sNApfQz%q@Y7>pnse#qUEdK
zp}9nFz6DG=W*xPdA9R3(rQ&=5u>p#k3TY6HxwhfG_UdVb+2EcNt-XX9RjPnD#A7J%
zTH+^OkGZa!aW;Qw<7UT=gMZymnHdpe_sXv0KwuQL+sr7c+7w@CV%_OF_{8m;@1_>&
zyoE1O7G*?NPja6x#y$iZ48}%Vw$n09lje|PHiA1=S8%NEoAUiQr?&f!BL;(cG-VvR
z%S!eKA0~Z;U`fas%tb~)Py#YaG@GUgHd>+%vP`yGz}nm-*gzwu!3snXSqEmHLRqle
zV`*gsgu*h3YvMtydj<1{ks{=J7(dja<19}cw1q1#5p4L!eg+}Mb!D&?zB0lv2sqlr
zVEFg2F)8eUBr<FimLQ1AXj<RhZBPhFk+hv6EHYUdL1+mHiZ0;@53?x+bBTQ)^9>4p
zd@$=l<yXEW=RJ9uEpVn|xoc7$A|qo}!n{Wf4*iXM#3WDwuUxh%3ZQjC5U@s6X@{Ls
z-F3~F0E8hl)paEq&T%2@B6#7dbPR;fNV}1?#QlZSFQQ{ajV%$89our;ZmhT+z6-_S
zg2Ac;wx+UD4ysj=R4~`pZC%sR0v@@ow}^_11&Ae<?oiy_y$CCtY&0ou60z11KS>9w
zA3Y`o6SGZ13aE774GApREVtSchmpZ;wvG{BB&L(5qcwpbhfT`QrWPfbVp<DUl?2tQ
zGxxAbW6<S`KzmAjWSy3}n>(AuN5o-S#DH3aH8=|wl)cJfMOI?oZxsninIhe?N)b2A
zrG-$9MO+hI?6SHkJ3`0^UB0_dFp$kW*P~E_VaT!FxJ6}KqLEwz@sc5l9@D*kLBa0A
zJY8Fhg_7?>p0Zj{Do=h1LBSqP)OiZtoGkXr3mB67FzpD`iHH)Z*bPM$Qy9vU0?{F@
zo$Q4%fVnW4OT7Pt;9{Cw+_yoVwGXa5MvtY5XfE^)8bBlL7IZLo-50Kf3|fI)+K8-h
zwHv{~l#sG*8}|`pMZ&sd0blWHiRHYCjZuOOAlxEq83&Rgt|rQ$vU6=X#>DtBXSsv4
zw7iTK)8&|nrtmqi;JXdX0<@66>cemw3hL<k8#e9iEOwN)s5^@*a}K|=TTR9Dc7_)^
zdK7-0(d2YG-F8ZJdsB;Co>Doq1($m5-V|?A7s|^&_wG!)!dvq8S5zYtiyu&W@45MM
z^M1wFM|8WjJ)Uxn`#XN9^Je#JE4kt{Z`MBU-0W=KY+5gDwl{9w{C{}!4bBne!~uTG
z@U~$u6&n-|nqCVp_F2lOm5+OCG!r_($fvzE%O1b%UG@X2`ko%!Zj#D{_<BclF$TY>
zU>9UN)6<!9Z4j%s+dFoUAntH=8wVkF#)<b}bI6GLQu|r~(b47RZu^kh?R0iD$2UG@
z@MqOdc=^X2=ezdv=4I=?)2@EQ6Z{szUTgH<Z+`4)^<!S%aG%|!etWf$ah_kz3#$(*
z`aM`oUljUzF)d%Ac)Akr(Dat$eZ6|z7*ST|)5^ggov;w^u?m-0|E*-@o{L!_&mLL2
zFxNqu%-tzkg>~F_cPa=QiI#eS)g<M%=W#n@i4a#8QJ4pI&(1z^kGk^!SKOUA?{_~5
z+rOB#+ivz!anmWbrH$q4_i!4&Qyk1^cN+GIY@WOXBm4(ru-I1W^>E)~EGnc?ROr?>
zu(C5-e*L}tFwWV9rcar!*In4T(7djYZ*{x>xM$&2Y5smcx1)(G#T}`4=G+}|epE5n
z3r#zWl&2K7ShsKbh}-HGN1GO2^QHWuHU7)P`46=rwzDJkn9+Y)i|aBX6bE>2=gJ=|
zJaMg=il5dJ-}Ez2Dc7alol<A<u}huLbnp1yawXgST^$bK>XhUkxxrEH@gDe1V>^Ne
z-2<kAtNg8qCk^Y$H3NAA-$=f1IBz_G=urLuLK8O_`jvmNDC0^91!v$8XSxyT*wVwA
z?1i~RlVGmDc1g}ni8=6CwAChfzJ-sbz-`Ieaus{=BW^DJy+Xc%AR0Te<wI=;F3ZFh
z-K!rFuTY9zdMo_Wo5A;E+r>TFk=Paec^84bLxy-wZ~h-~F(RXO4=iu))!|4(2Y4w%
z&krCXgIggQX#5Pj4?&^>JPr~OFT#b1lfy#gy?-SaGN9{DiWe<ikm)vctNRXws#KO)
zA(&7&nT?PNgV~uyKKADY&?yLEWLTz$XqCWHu=UUPUv{;+Q(V4b`EuPVrgvz$9T`c1
z($TDg?PjL1(ds_1%E*DWqL~saYGQ|uIFUv^ztMVpKrktZ!x=|JFu=gKCk|S;c7f<&
zA|>8;FU}f-%$6O94{f=O?Lc7Xj-I6=mYsQI%NDD<1@SCwj)<&SD$jPWObOU$a!V0d
za;+P_-?PwvDkU7;xj3;)RSy~;&@$NrhJU26QrBEvXQ`ER=c0QfHm#749|9j)F1r&^
zksT(yd9!s0UT{F1mJshn3^QSGPSB+jQ>X7ze{H3OgP~#<g+SJGr+7;y?iAmLpkDzo
z!6zZUygj!A^NsbNbDQE$)&UD`#E%LL0Zi+L9qlg<3+$Sc`B4bJnSA9W2Oa*-M>#n7
zlrqds7cq%)tj)RMqqf!k*eU}b(B|@)W-YY{F}BpAc=iUP6*H~txNdSvL%j8H0%N)%
z9n3Oal41Y&FhYJVgwL^KJ=bx$VCcF0ofqUXnT6(ywq&OA3QH|uy}IlwLT)2xHi*4b
zLb>GaEPw(fm0yzU%1CY9&=L2xe~_Cx!eAR$aRy2eO-f0K3hg(%%p&Y#2rM1l&rJm3
zp4};xvs*seYR6KF=%xAuTv5W5Cg4w48U>l?7SHL|?qfX*%f-j;EFjQ(gR?$AaO4I=
zg38^$0Ws{cx_6`mvmJ6+XaQBSm?_vP1oT-(l`JeSS~CNgX2j}lP;y^><jV%pc)<9;
zhWk$DcdRn}%nd79W|3}~2>2oB_R(I5Vw;#7WG0A1cvdRM)+)<23sZ{OZW%^&F_9lI
zDRybVT*0QUltJW!e{RLN=V!3;GF_tgU4)qmkVN~xz}0{`stLIQ^C5;V0xPDCweN}Y
zg4~H#^l^&~gnP=Y-27Fe&B==Q^}nX6nfUVqys#aMO-VYc=;MlwwJ4WfgVT7X9b_-t
ze9<75s3)vT^x>9{C$yRZV<<j|5Q~YMHkB=i6J-S$fU;<#x6A^DptyCTif|Ha%*<8?
zvndS<F3x|`In!mMt&*S03jVWM0hjV#_H4=fhAj>5Qk$_-?_g%S1>X>t65KJJqj2+d
zT;9WhIlNnFYs+ha8;_er3Qliu;YI<OgPej+l}(zpRmIk^#Ip-=&QkqiF2&scN6IPe
z*mg~zJq5n*I<8@nVs}YHFRCAtthg_%xrZFkQCt$s86|8NmWybWz0E7{+qli!k#tUc
ze86xDtC=6{B$;445oHQDVfP@0`6ftPb9YJ4(~g2gZ&V&S`EMU@`YNvU;M*0i)AJJT
zKKu1Y&!;;+uj0N)5bA&()(EuZ0o_RBPomEgleiB6{{l8_8uhD}1frHD2qmmm9d)$I
z-`0H385IKmAgX9ml&Tt%nN$>2ne?puf3KrAIBK|@k<q&Sl)D(-G}-c=N6w}dn39N^
zNw8T1yL6c@#0P}5mM(d^h-lhA7+MNL6kcJS?W!*uLn=AE@*PUxA+!o5x{iUN(Xh~a
zPXD`$;iY@9kbx9dJ)Pfr!C#*t;32S4@*Ql8TmUqa(|s_b;TU>*)c^-vL$^zaJGa<0
zTFXH5q<|jKPvA9%-LS_$^)58Ssr(3|fgu)879#$lFB%!ZlN|}YQ{+yD`G?E-xWtWX
z5^yIFQGzNcfitqCbP9^B!pA{H6C^}XLeE$J50R;vw5UTRqgkiA2xt19?e8F;&%quE
zZ_FWY#l>KGHl};b_eNOhX%*+T*{qb&veLzztxd>kn)}<0c=~=QQ8>nmV!TJ)tH8Lw
zO&PGUcemJS&k(fTy0BkSHk3pyZ6^BK@ooBN?#7HO<eDDF9hzGx?!t_mhFA>P==wfR
zh;hpSa*~55V%r!dja=`xSL5yg4hF%Dq!TlDBWwZI_;guiz)_vF$o8ttU};b+4=4i7
zQ4*X=YyPp%EN1*_D0&FTVb$wW)eV}=T}>^T%S0S^x)|Fc^z5N$1gpUHp`7Q9x^yGN
z8)bX-OVqrUvA5#9`57UX2JNlFReiqZrw<O=ec~`(@eyr(u-Cu^pH0HWUYo#vS4SYK
z&wH9f_`H(70P&Cmy0!{8F)H~h=`M{&w@GYwk1E@-rFL1ze0s7P+uc24%Y}8|z8lM2
z=;iK**O`>cf|tRWkyGyVJYSO^!=WQvZn}PI=hF!X7fsmZlAH29!5Y=}D!ZRdk065R
zyLwW`X<f_`J?&T<qMJ%mA4!zF&J790^Y?0AsYMvX9Ig1<i*VJ5qytmoGe2p=w+_~+
zj+yn!kZWWkLk;dv;JZ97OUto-LxeEekkYJ3q8*of&u)cgpwkJl2{YuuN>WM!#)@y}
z>A=D&4}BgBi#AQ>mV{=U3?b8!*0$PA-h_S-!%{Yh@TRj+N2*v-5jfFUr!9GhRoBFs
zGIf*?%_LSqR*Y}B;xOb}!2y!Ih=KDaty*14m-{dn9|{P3zVtU2CdGaz1GuOj?x$(E
zc8!}{kS-TX*2Rs4s!rm#^8wMq62e(0Na0e>p?)M90l1@wL!e<WR-)*GVZj+JiSmG0
zIdmlgC<vTjp(3)C^O_Ln6&S)&9=vaEH)YiY`aWOhSaq@u9~J)~jJiCe@a7>!?ku#l
z<%i+WtCH4y2rF5WM-6m?n>}k23QJq-nl!5q0htp@A3_VIzU_!2_z=Z|<k4%%UgOHq
zckI^=lZ->LfV(7NrC`)Df>m^Z1e}3Upr^33RFkDN4?|jO>@_ae%mcdIfymK4N?NZN
zift!#!GtL3*iv~(Y!(gN{eZWwn!eG$AW6(E8HR{1RtvhJzWiWJ#vLJCdlA@Pa6#5=
zRp4kr$_QZ!*dwH&JstNPAY$5HZUMt4&yfrddf~8QnmfQ>io`7APvc%3xSx{rglJ*T
z_Ui~O19271$}K;#1bKvWi`xTv)Wj_wj)>azg37rnb8H67V(JSB@(8j-;)N$&U{d9@
z1A()d9(Rk|G4r>zATGfQ2pW1xA)`p9W@F^?K2zV3!=Bc@*1&ZZ5iAS;TB3FOk9U#U
z4|Opc0!1b?RFj0Stz(4Ng~Qf`o}O~@eF$(D5OK#nPc9`rx>ksLWw?Ho_C(TVp2AG9
zV28ZjDTxN+gL~<6C8CTAn1Rk%I-SO+j!?|4e?+l34?QVZq1g3ku>>(=$1SF<&1hwT
z&G;t^xb4zs$A);5lGm5z^`!=4yK=wn32CNfVx7u>E|xn?9pu~4vL<{<joWKDOJkOR
z10CaZ0J}mOhrZ$yt-r+BG6=umVtdj?C^Y2BbQ4Knh~((<g=`pT5F{fW@ol<%zp~aq
za1!!>5kmG3c8V@D5FH|pX@YJEE%zI0i-LG-EV;ceZRsM8y1Ubcu77FBNOH)vEWY~6
zg&5s#sQGqW>BE`k2v@aZS$l-XIUFj;AUHrfhwl<2=)!=~B|y2*7Y;1Z_H1Yx4YyPM
zv}f-Yl<Tnv;r^D_uC6pitzYoWPUC4@-Lk}OxM`ykb4l<3^69_1Do6yH4hKsZIE2QM
za1|~G;xje^UbrPtb}q#1;<B72Si+aR?kq&5bS>77ezmb9W3)GSiSN}F)ppmc1RG7c
zu-y_<e{N(t%yh3y)Z=>QGNBnG!K6WnLWbC_w=dep)uCm$B&)_TVT!Vc+xPIEG#};L
zI4&40v6t~?ZfAL3Q8OHrEOVB;BjXf)lc##1NYwn0+M4hFJntRizoW$MVP)CP%F@my
zmtFq2a%!crMEOZtv3KWJ?lIRN(hjXWp8dwsxT`;@K5um9Z`rXMhH`H8)l2O7^QQgc
z%HH1e8ojgEG0S&zMY%!0S5IA*Uf!~euhr?U(}T)AhEeXbTWl;;MQ_<<oc^=KS}3^<
zQ0bO#`vUmBTljq5>$jy&UNk*R7~*Bz6VSS~UQajSE~T2cq&?HkIbd+l{X9OT#QDI`
zl8cr9d6M71^m6{4j$ysE+ce`(^NaQSlwIomYW(sI*9>*US6`+Y%2mpy%i=p<>ENGM
z@@X}5g{r5HnEJ|s-f3L6GSh3T7whE(-pdETCqqm=Zy<{6DMrE&AL$cJy1ZA}_d+QP
zO>E;9$q=XCSI%o35vT`o)Q!Mt3fY{;5b`P)FXwP8mgEO;rVZZ{p)obj;I$|zG|zV|
zJD@13-`3mk9i_CP?d)smykliwuUCFyB?{b42Rf8g{2;1`h>=~gUqPTO4HqE4GGRQe
z?!<QzE{5EnFi>}|-X>5GzwdyOYlFvvzx?q_E>xP}Uh$>4<iv4PV(2QT`K0G;Z9?2;
zSEkssDxb(V<!>8IJX6N^z69%rC4M<^nNmLS7{6927k_ls_SEr#?w<9kbGu#4AO!Y5
z*PEyIX%CE)bLmI^&^WX~$ed6PX}g-cFTa?#b(=d+x3{+`Js-W43kN@`w|xh9p8hG7
zYCWQS@49QRcx_M_et#KPNItNBD1D8d|H+lgEB()ZB7ggpN}p5Q@qV7jx2C$4d)v$3
z>7Y2s#*@mSjtd^SsNyTbmmIv}e$88Dc&5L~Fw9g($M2rRknlZh+<rR6@vRel$v0ol
zEBEpj^G&#4a-^uTM>N6T*TiGI$u15c;N-3E=H+bnN9AJvPE{=1xDwQ(qQxUZBH#7m
z7Y*&|_|ENk|4V*nhmO(Q`DDizTQVD;=85j>@7jK-0};QguW=6G*46`CoGWhEy8ja{
z*ywo-^c6k7bCt3C*R{gMtBm{ly1VXtuYxdNnuf#6uNnHP%M!Ld++My&$K?j)KudqV
zZI#g`nkBJxdiw`T97m71BP(+~KU#WH%Rk^I^CL~E{J;ZOFErN|IZlNHYl%~QY(2kr
zpj_13z08*Fa#2rRP}Z(5$aJ;nUcNpnTy^r!FBysBJMz8F+r8z>*T)yQcYcw#i79*q
zsOkF7RhM~9KXAl*hVQ&_;}uV9>z9cK9}us=KoJVOT3dfGAbtHGC<ylWxPH{SUJ)Po
zfpWkA+4#2E4T!WQ9PJ{Y!-RDk=@rUi<?cLJ5;pd(6<j!iYiRfKrY>nPe|=LqKTvRU
zkG11s*s>-8`cKPt3b}T6<VKUZsRiYthpSnSH9f-p)Usjz<^1Uth$w06?`#>-mN%z<
zMX|P+SMp&a<07t_zU1Onm-#Q;)P10Rwf&K%w(Y|QaU1A+`6Zf}d2z`rST8%T<+<<f
zEI<wrgp6z7(n0xAJ)OfXv3~o%8Op&&ph?X(!|CoYu3xCgy`C)i9^E25A|>qNQ8zK9
zHEr^Tx$0WV2Vq#VT<?0GbuPdN+I@t1%Eb(Y7V}_s`+6Nyq^MT+`<fs**Xr86ya0Jg
z?*NhB&bU&%g`#`~=!EApxaOw#bk}L;g=t(3{8Za%ZNt^^JM^@fI>@bybmibB#;O)g
zZ9C9zVrPYP@8_wDw79q*M$C%$!PIQ>IIcU<rM%JoJl9O$!y8eR+(TgMgSg*+A!3+0
zldl&LYe%drg`OY0b748wgWG~j#pMZ4&5fo64MDD^k@N?7lXywmZi1}4nY$rg{E(6#
z$Rk#juuWcUr~7|Ri(c;KO}O)??5d>GX3y^;aE1MJ$rn2mnSxjl3`1{w4GIjBVVWf)
zZ&ZHxgZ-R0?ZOoW4jmWUhIkh4UA>6QYW`@3Ze|_rLA+|WnmhVp1~F+DS42D8t)h<G
zaGRyv9ZgF`T(B#;u7YrKzlzoPz&mh9apwj2sp{oDTa?}TA2hwV1h*ImcB)G8BLzM8
z9<(feYrTGQIRE+e!ol^|L;LJle;rTn&gWMs-2(^LLn(kAvQzZdfxi!2m@eP&dw~@H
zo}M1eLzJ)h4s<R8;o4fG<(HP@ir4O4T9M;IKdxS8y$<aN?xAP)ZOjcEd5?7LTd~~e
zi_38R&cwyhl;hdT0=BbXEH4wS&!b8?;qTH;oY0_mwmyXrnaRs%)aIQ_{stE>oBG=|
ze_gtaWw0o>>|@}=`@ruL*T-^$O$)3Wm$Vv6@iGJjyLuLsasBJ|bdkSD*OUhyyg4^u
z(#68#n+N)KX^1Xk$)?0B5O+;K{F)Hg1ac`LWJfc@dcWQ5w`(ta%*57#>$ZOi2LxW2
zhwF;;t0r<+8HO-Lw!8-lwsoS2%Mzz}Ti!3M?Cm?^_<eR<71@R>><#8#jly{&w$^|A
z>DX=fQmhr*t38u<aTPb)$Fmo;KCK;0_VWiFatcpmQHXxv7QFn`3w#6=;B4V=5nsqF
z!(e_N+<&?p##CGtTS5XlDB!>+*OAT@*NfKBRm?2u#~lsZsMyvEM*;pxA4X&sF5iHY
z0gZhu*!kEeV(fcjo4s{q+Q=E{Hd|dpm)ut4n|O;5;M0$9AHbf6?bA>78KT*I`|Gju
z?I&55;dfpB(B6Lk!}giGJKw$T@^6Jd4zsj>Px-F&_v5=bekG=C{2E{CedU`UUVRBY
zJL$P%<jiL&*vD7cVPaW`!Cd(-gz_o-=HK4q-<p2P-qjxb&J1CoADVe3j=N#N1g;XI
zwv)h9=WBV#|1Pvw=`(QFgI7v<HScgz)AF#AhFt@;<71h)O~K>ckW$LSl(*A^sT!5?
zWbb&uNWJu*7v2pkduo6U{U#X4QBzcT>a~&<9@^_x%!QZ7Js00?!p$JK;WP-G6#MW^
zh81hEZAnboMxTf);5HD9OH;v(DcB6$E_uCPQef{^k_djqg_K0*Kk#8&fK!8S^&Ez4
z3Im(JA7O3?IDot!d^N;(5&c6DP_n@#9XFXdB0iRj9oqL1u?I0kiY4t9N2nFhlms`x
zy_dU2N!Z3gk!A!X&F~y3d_mtQW0gPnF?E7}B5R7F6Zi)R0f2mt4@6*4qUiWG3-00I
zpdIlQ319L+c*#b%X&<9IXt*(j3utimiCl35Zd|vZ2ZZBd$pwnv4_}+92Gc8_d<-*H
z5?K-swWzrozR-sl2@ojWVLK(_(ryfaucVZevPlWw0qhj;6_{?@K`U#4Yc~0ajg=e^
zcNZ*pi1%_#1?pR&OM(v5z$}7)h|@^ck6Txw)RhdDg|o`CUFLR`t+m;<K6rxQg$)Jb
zv(*?UGD{8-tm7^Vhx<*KfCRT8@HH7^2VXqHCjumhFQ6?3gFht!NZ$CQ0DQK>lIFrC
z7*ui73+dal_-0nKv^I_}`OCcMZ1ZrfjTyeIBi3VX6j++uHf|TLU#VV*AeuX*U~ss)
zZZN)~ERwf++j7CPT=3pnj9wUd^te9-vrX(&MBMejLUE<|kDt8}UzJoYc4#bJuthZ&
zZkLwKXRVPe8wNMCwsni*piUO|NN|}CHyV?6tPCf?2T!a%gjxFyc)GY0CK{|Xtb6P>
z^A@{gAJCKKn722(8<&QZgRImiK$J0e2pgbsi}=R6MXZGHHkA~}19Yb=1Q)F^<p_k?
zK$!IPeQ=W)oLcM(aSgY1Lhvy+G|k{97MoqoBz_ZkhYbeC>JF37w4MSQ0TYmfJCD16
zBzEb3$Rx(a{FQy^B@j<)r>OXfZyNK6A^9x^btcCQW+Aq!^&0|>RE}kFg^7N+#Xp<|
z4iKCMZ<FGUci_WBzrixVZ4`(r;RFf+q6Y$K4T3-pQ3~=&&<RS2C&W6KjX=YGwJ-Qu
zmpq^&WFHpe(_|07|6TZ&B@yHT5%<w$@b%V`>nlT$2~%*034WJgAi{(yxD`!jOfG%}
z0+Cd(Bxnp`BybXd0T57HOVcf=uYRF~2D|StY3XpR(vk?l+p9CH#gtkgp1|s;Oy8R|
zN)k2S{E99i%Qy@LkugLpPmj<WF5xBN*U{o&lB=;~pRiU1J|!Hn%bbVv2z5g+HYp<5
z2?a<(!PpYfv4)(isiB8fkrlZmZu5<j8{1|uwqMm*NjD8g>PLV0s*)&c2v^&PAq5>K
z6-h@h6RIcZaU1xN6i|{B{gjma@gDrdxdnpjLULk3fDpunh=UgXq;_|G_m^lY!srzG
z0eelnWx;LWs@9fu1a%lB(b?vp5V<s`Mv3mLg;MK9RjDu3#q`|PB|-~ZCf06@8$fM3
zmXH)Xp-x3F+3rG-qcg;e1kEy}C5DLqCCtQkd9(65D#NJ&x=jj)73vbL0<8`Kp+f`_
zO3jcA1HZWla<K{#K>F|=Oq`n(5Ej;zVW2e~bF+jRPxvwD2oiYOPPoAh1n!)5QCU**
zvL1uf;yZ1c-p$(<ByGbzfY^A@6xcDNVaq1HPr&cd11(ff?1KZ~8Y$^hJ--7HMF<p1
z1<MYbjf4{nnj~6SxVeW9Xv>ncR!`$zo@hqQ0s}*^unfc1Pj!j8Sj=dNxvzZti}Y)b
z<a}V^@6tU3oZR@^4$Qi>{xw-mbabbTFVqATe8%Cz8KhV5hmf<Yve(c>^WaAylf&5J
z`BD;IbK@Zg)LoUPQeFNu?mtV(;U&<cr*ypyn{iNqxO*!dJCHkpi1tgL6G-2IhhQQI
zG$f3fCdL7S5anbgMF-KQ1L|wD$7%<YPqT$1Gc2qK2~A=kf44o2^LnHb9v1sBx-inK
zTohf6awqud4X}WzZRq3)&|flNAdTQqoBcc;mL&V`r~bQQ5RQpW_J;X52^>I$TVMDk
zpBmC{R9eS*A8@X5S|#RWyUzGNkWr~TKs;051D;fi8I`i6gwmu~s+OYmG2<!XXi&<?
z;>Y$;+myy}7}JFwgKk$YuClT;q=OpTc#|F2g|@kJ+LuBeZ$}fNnb?DDC_G~QGLS;7
zXX$WFK*qpKEQuP<1GjbN{^x)bx%fow#*l4XG+t79aTTsYKnNhwFwSu9hiE+RvLY%9
zJ-eyh?UdMI1ZicQKb1UTuf9YX(hbJ;LOLyJ6Kzu@By_u$r7<;@BkE8RHe$-)3FHCI
z`uh4r<jW#+q2XToW&HRzb|x@a3kQ(&SBeHEh&fI`SeRQfgV8yqV5k@@O=U?89^>?n
zr(U}5qNT>A@qM~se$@S_d6m1yac=Xo8~kq$bZx+Cn&#b$U}5tsyzh2C+=95>D(8K7
z=%=^a%M9lg_vqalPmlU_o2bk6^iqCBpU$5&_H{;m{F?uXTg+>^P8g<i)qvmm>A|CZ
zXKc5}zlI~Qqk7#YADW^`_GCoY6UIJg<)Q6<NYxswS-ID6U<n;?AsBQ7NoUvs1Y=1`
zv<!8sLTM!g$~GZrIH~m@eI6`0afy!U-4@`aWj=<I8OdtN6N$y<#-Z)*nvI?N9Qg&u
zJv#V}qrQA}P#c85og7)FF4OyYud*R^yk&bl9o2ovS?jME^`G4^*cJ1h9T?I2VXZwh
zqAzQiY2`s-=7<Nq``bG-zS3LrykXq!82bWxA961JHK}Wtx~_S-wmYx=4qrO-zz_LJ
z-piMrTB1~zC{1?0LoM|1g{duOYRh-anv>m{Ej`)XYa^60aE~`Q+`dA2o}XIA-`$bW
z|3*Kg3@usFa=*T!<MjXK=?#F}xXv^|f@VBSMw9S8G{6P~QhKkuL6D*-HAq^NV%h9w
zHwDSih-g9x%;Gr)L^z%)-^Qez8BcBYMol&%(1b<?Ep6zFeKsl4rO9PxOgVMsshO=Y
zC?KXM^2MM%bIPsvV$ycTvo&=SO0He!YPWLVW3Eo5Rd$&G(cSO;|M!32_y3RcF6Zo3
zg%$2+s^-M%RytvSSgOcl<%@3H4HCRl5=|rBWRWubv9PZ!EA7D_SDdUF?`#=H$*qFV
zYVu-3$Ck-MT<%`ukmq~Nme{w<T+S+36F1Ovoc2z`fMR@D-g4b7SC=oZ`|JS;@1Aoz
zNs%ncA@DD9guo;^Jd&d6vng8}O^<@&DmqESmhO0HIu;jGo|eBLM=w?`(;cFB=;1ZC
zrc~&|Y+JdjC=bUMc}KK^^>M9*sfA2mF;laO>D#xb<(h0iD`!i=){Abj#Fhy%3^YJo
za^8T|&>qdGpA^kZ%|<`z?UaRH>N}-rc`4@2Ez0y5yT%Uq53oZFx9b4!<Lby=H5yHG
z)hImHV~y3U+Pi4`O`_?p_@vu8^r!zr^ITP`j+M%(l6MKM2}JrjVP7W!hiImA{_I)R
z&{{O-mu}I-*nt`vug@4;xV8mSt_<y)Gk?w411>IaAItlL)BTR3@8yTgyx9}yg`hbq
zPvnu~(zkC-OD{=?(7?~H5=>D;c3@iC!at@}NI&uEM2|6+us|$H=;(gZEmw!4*%Cti
z(6MVYd|yv9?=tzf`Aihf__S9~NG-)k%L(HI6mKw4;k!S2^jETkk59del@8)>guvYT
ztK?{dlN2OJI(|NIHm{;x-I=n(38}S?TRb3z83P;KiOv{Ze@OS|sd7#^MBdP6lv_%G
z&(1{S(SjqsKXnr5U2Xfo^No4lJbY=;%H~`&jq)xQbht*T=~!?gj+vGg2~H&4v0Ay2
z+;S_}1Q*>-c+?jtkH>qqlpI&_OcYKXOS5PuKgK_$6NzHFWKSlCuSl0&JnrBZfA9}&
z|6(i?c@CVdzan2GxR#*qm%CFO`e{5c5|Erc_K&?sE#j%zt=0&Mv=&1<M_C660BaBl
zbha_x|1dWlf6VVFnEBPLP4Lx;5<rhJV%#bFFz9Xg1_4UM@Iy>fY{UDct%8*4TQw(3
zhVgFX78ubOk#7)0@BNBSd*DuKYwlC0+R{^MA*-szWNZB;$vQ2)E6-s`%->u5=JOHz
z3fQ#Lj!Z5RPmbhB2SlnvB<0r!2L0nX7-FY#s&QRQB-0!A9{Dz!f-bvmm2|`|>FpF`
z5dD}=L*+ggk8Z{{l{gP=8Z$~pwF(*TsZ%aml`mAVfDm1<nPH8571rk<7<)}T2ghP8
zr!w}bjP~!UU7C)30O}A+J6st;8jTNKz`(GP=H6MyJn1~4Iipi>jDE!`O40|lRN^H0
z7ngkIx_AHS5Jv8J^SR2)B#?UXGBLJ@QSk@22r<X`fOdjp@~Rz7&lb!~((<Yp%!74=
z$RhuM%-@aaKZx(`j}3iY=_POUJ4A1f@8jk_JTVg;wX94Hfveh7wbdO-J^^KX1O0LP
z-3CwbgS3l@i*QVA3#l2~;yKMpSk<DHO#}xdthqIu%Sh+qG1@b`6X)G)bYv6pOPS%0
zb;!h8g~w%5U9Kl4t$Ma3cS`n>94u9b{_a0~6=NVSx))sprKRGdFTN}jf+wS-XfQ>g
z8?iBRHkgSP($PY;M@xIQlqj!B<nxH^y67AW?C9imD9(ZHe(2`xAnRY@QQL(jU^tw8
z&b8{YgwW`^`!O*F-j3ZT0T~<50;}l>?73Jmi~wBB)`B&u6Q<<_0`5EJmERb;Mvh(6
z5w6G~b_->XW#p`>LNL9eu0DnrOl}zTH15(oc9J}|^B;>Bwv1^hTk?V%p(`&z^$uZZ
zg%ihxFv12i2F%O3;bwNdYM_<ej-ZnaIq(%%S(N?D{gIobLZim}ey6`3&fIvk!D;gp
zwr=`4xT@Vt@_bbSOO6MEFjB;z6l9VeN|kAfp>k~4%1ljJQ=b%11t&erIxW9#JVI<F
zoETmrm#*nU;YF(88&OxAo!zuHP18}WDb+T^Nei*>qCpKbHGc8azV{N-(v`?1frs4S
z&j~IA6dlxJNgEj_gMsu3MBLG|sZN1$GoF@fk&!joNK`|Fht|kFru)y6JUi|`LI)R>
zkOPBCl+yc|mhJJ1lL^n7t454@gxGAUEJkdJ`FnAZ4>e1oK{SwYrtPsYJg4{pvh-49
z0iwob@P%beMPS@$KFGUq3EgqzjuU1#cSduC%(|9csYj&A4f&mEsdt&oBQ5Sof7AAX
zg^t2tid;P@|208QM0VHi`KgkMvp|ZTO`X#aZk^GB>6o@Px#3-kgtw|#_hFyhc{KXs
zQLMps(#Q632u_FeO@^#^P&ugD4HKd?o@MbACJV`lD<JXEo_R?gE6uq+s?AW`Eo56}
zOBT{$#?;cUX`^x?osg4NtaG{TGuMBEH-%^8@ncmeP{R~Y;~9<*gRoiH!)k_&pGCAY
zf-#01ZT&ybLxC>O`HFWiQ3%kK=qfov22=fk6cR_FVA3>x$;#?zB$2?}qM)@T)482c
zC_=vo=^Z4PqX$^DN`|Y7c8*4`aP9s!YqEEBB4H;cz0;Cg28!^0n_%I(kkvzMjiTCY
zORH1bD9ra0uT6PlRz2~OWCU9mkN^-&*u~j7wyeKJ6@jm2`8Ia>Qw~Q4Qwz@Z)zL({
zhStxTgcjhiF8`+IO9o7oOLFn&q11~cWEeRjv+ij!t_SG&2pM+rmKKCB7;DPz&AAA=
zzDp#WpM9OIli>zuMg#s6?L2QDS!8fIs+x1ds(D5cgF%Y&vq%DSEL9SDTUn!G_zv2n
z($-WPo^IBxr)$MlV}YD-&mbn_87=T0U%2^s-d#aVJH)Y|)Gls)D}RDBXuH>K6LOd>
zTYnoNpJ0B#g}XO5-?MUV{aHDdD!oAP>9<IVw6jCHF@un6q-Fvsm8k|k)SqeLbh+(A
zOP5Y!?ctDDU*sBZhdf78N_3n&=&<&92Pgh@m7yoknT7Nwmt5a`6|MGnN(LGb_ZxW@
zG$HdkrcrRzF)Z+i(_<OMbglj%T1eb-MfQ%-8wBWJo13ONi<k_TL?L5YELTX+uHJ8_
zZx^K)MxvaoAXq?MJ#^)Ft>Ax)0Dd65dM;{qwUa`&L3EK?5YXG4*NU*<mxfzTQ~~B>
z62DA+53zP4?_+V^&hY*wk~PiKLA*keoY<;Ua^2@6Z^<5>R0X3$nSmzTS7A8;Ljw?G
z;ZM5k71K$GkiEX2Vi#k{EU@UCvcm6!&f2u!^c>3=!)y+(hRvIZcnvG%%?ZRa^qb0;
zT{{^wvT{3iVBpsw{N0XBO$M-UCA2LJj-N#;n#$oXwK!=NF(b<Uu|%H13<oxS^hNn)
zq>M<FKjc41;PBvs_ZSENkC@L3*&kwvIHv57AIp%EeJ=W{fiMoz|3AHPJDu0kqd<LH
zrVrb^Eu9pr;RA32ZC}W-OG8bsa`q5qod`kEn_Q&Bf+e9?cucJUSXn@Qx2GksB!f5f
zLm&Tc(s)KnAPgTRS49wNN1;K8Kg9>>xT1?a9Pm4)T4-KY>#fCBt5Z4w&urPK=>GS~
zIO)M;U_IX5(5L;tO#w2^{zywHz>KB|Vccpde&AJPYaVxho`BCmTT8D<)`&l<)?5IF
zK;Cp#K6UbTx?HvDEtq3M=XJR+_Iix@!VSKqR545X0FOo2vDwAXbK9KAqs*ART^+OL
zEAo3KMAQHE^D(P4avBFG7KccaAK8}l`yOV~)F6P=0m+Bg71G{nB3m}vKJ<1X67Uc3
zKqzwWX!jLFQ9Txk^FDfzAEB&I88ptG<q&g&&J(%eNzdDb#tUSQ3;~a#2_XjX`ZyC&
zRGqTZQ}{>K(m!EZIw^{ZTK#hg(5jpRU{K<*x#pg0ESy)u%*^vH9-UFsd4*;yjb@^&
zlO>F7DaxN<GLW}G&=c~X>gaYm>6<rBJ{poL5m<A`3$(+Jr_nz+PVLl`RR~%^^d+ZD
z=thZE<uc2;`zq)Bk$a4U?i)hkKsy!Iy{KsafDXT?*`i)AOmNE^+i-*Gmg|FI*ekv%
zGav0WxNjFRajP(zL8?)$x;c5f4sS;Cr(~omyBIUO!1#h5c4u>35s6UkU5^@1IZxQw
z)tM)NcWSkI>m}(V(o)$-#J1eK(Ql6>jnjDCcS@=GN<h>S0i7IS+6-_sBdP#Q%m7%@
z5Is=O)J{tlqDD#%$K~=(S*a2@Rv#h<`=j@m5<RaN?j}QlFp8~&2<!n&|CCt!UDiO+
z2HHxCV{82OD)7JYI7THabG<mar#_je$wqw%PYhF5vZdFdz=v1#19~ve9>M~|YaZce
zcs_4TS%#<GZzr=g`%VJ&!wvEg63#Dvwx`X@xnnXU*i;DHoFGOH=<Pa62(F=Qm|}$t
z0{`k`CBw3>NMgnl)}I_+J9?9i1Bl<%S+K&SNI%HUF8(+Tq%0LdUo$6eAl+t5fK5$v
zzWu&p3?-^gMR6kFE3%($;?{~MVosD?18C!C2KgLAS71JLKbl<}qWkaBxOSKFE=4n&
zr|cG>X)`@q{0bHY927UmY3Uv2oAd4aW@{5bybSBvMVFu&g1(7g&^FEn9X~mXoK~PT
z!@=_>_n;6!m~6<tedKPe`v)YnNoYeEK`iKs52n~bF7=>FumG!=7Mv`3HE+KT(<#y?
z#8aw<v6hh2(8jH**Ne_dJ(>1urz4jQa-Ed%i(|kQ7gqF`5~uP5iwI4qa+|SjfIqO1
z`abcBY0I-vl2(HoV$yT)i@*6bL=8|d(}YwAe81#<KJ8EWHHQSoNh*L?iE+h+Qzk~m
z+0vVmA%EtwHIn!5n<W)CB-W6>og6_nJ1+9F6Bv(kWT1lcm#Z|9w7@I}LGj_^H+{s6
zncbzmdoNML;cYWf&D<^MF#4j}1aR(h8eUPlxH3ZNrT`Opqsv6CWaaA4w&h_3NG&G~
zx#auTL(PwnGj6I}CIFp*#G?cs{s7V7#~T>SpG|!WOVk|AtZ2bx%Y`ad4Jx1coGZ1H
z=$izPe1#K$!1xgwZE#0HW?=s#&lN_k=3+RU%$C5aUdXw40d5oO`?qLsRfM5oWId^6
zY!ri;4BN_jG^iqFmzG)Zv)N@X$KQ${AO|T!*5*hVu`UypLR->7cb#E>H{z{HTWJ3k
zfwcPH#}XI`hnopY&5MBs(1cF>6~EjeHW`}s@>YPRpHOp%UVk{27)zqxc0|CCSYs(q
zqkkQ0j_5iVkicE4w8sORdYln|o+HxR4qrvN<9eQf(N&ESK=T5Yr5pBzmq{;5g+mC}
zNE_y8TE*?eM#=UttC-$^`R6U^Ru%jBqI)Sew>7&c^YFDe3Wn|(+C01tpnWFKX&O)0
zKIJ5fa`yJ=$kWmdcrG#1<?@Z@x^<@{3__Pe#gjlVvY)&`MV=myYa{;jxhX8c9Q)MF
zZrD=RLL`%dy&yqDbb(d&`g^L3>|>iWM+P3|)ND}m$I46;$sM=DYpS(n6YdBA5`ipK
zS|+bkB6JX3KrWX9Ig`8Y*;e|towy<yptHnX&AGAgHAcgbh?`=)=C(<tjA^%Ma^^E6
zHRJ*y<hNZE=&0-Oy}db>45mwH6`T&`K+WtU(_{_%VJ``u_m7i6N)I^aNveQdjL!oD
zqgSh0?^ICqok0jgVFHiPJr=t>dyVe%vp4jc{9{~6CnM1mJs33};W@NcXFjPXObjWh
z(K80z!JPo-K7g>wF6P)Rs@17s)Nf#D)K8ri132K0l`}lULp%!8QgiHZJlGslm35xH
ztE$|xgQFPGm~cINvi!Q7vg9yut^DnaXyJQWE)n_B(97h76fPn_jJtj^h}4D)`Nr8m
z#uQ=MTgF|j<CdYqx&taiF6YRl*!M|a>=mjbu-+r=kTM;=rg!iFw&Ei1Sy#_B8=xP5
zSp5A&Yh6OGeFTKcB`g`wyTE*E?`~{GvbI11YMFc?v$BfYWu=qGe9G#StDr-+fCtXG
z3-O_zxn(N%f*rs}etaF^_UBRc1Xsa_CPa3x+D{?BfxrVpN$%9YhVeK6Q<%O_-XlK$
zF7oa|@xy=vwGo(d?F?4)Q~^(DRD_h<_J>vqc=<^e>)ypp2yOYREJo=OqT+%Orcj%K
zrA*H@VTL1O=gAcKSsGrGNl6zYmee+EMC7mgajP`EcS}x_Meb@r8WyougcBLz99tfv
zo2$InoZ)%X#+pU_Hp&F3bx%i57_xz@_R(+ur{BXIUM~npFil#)e>F%07tu)%lEHIC
z8%f2d&~;nLJOPwB`6JB2v(w4bk<-%Yh=D~)Bk#NGdJF_xr#{$xyq|>@m4I`u0~y9-
zmWEc`Y^mk~(|cjizjy(L@GzjK*XjSq*ocVKtVtOFS~F)9Eh}r)CF!ZECx@9XAKNS~
z$K@VeMfVnityEQ<{K-6?pM?)HoRHGB3xMU87dAd~eeLK#O_vcRE><p9+R3HR)rLT{
zfgB6IK(NYm%^5kHKDYZY1Wj@Z52J2b&qO|`H9&KraQt#;Cid653xy@V7v9w^vPox@
z9n|x889PbSc@%6tE|!f~#b$m+l9!O5He?T}6O%K=VE|*?PVZtP6uekt==!SfIb$HC
zh!)c~W$w}&bm-VL<^DJ@0alk4JCk>wP;Du_UNF&;6}e-9`K+RQ3<Sjc2fum?l^Ot^
z42(K#;9@$68Z<`k0|s&IbfJ(IHTi6=2Kv)R+_2NN6F@u0v+_Gf%Zu_0EAf!7AL11n
zh{N)ZI>}trj&s$v%=BwxH)=&GTLU2|m)B&hF4U+#8pgBfq!&b?B;Wy1GoXm`Nii(%
zvFekzY3&j4|Ka=O@Nztc8FaLJlRE&l2UY$p{;hl=jr8)9RVRi>mH^9h(MU4E?E!lH
z)#~rQ<9l5uF|aWtG>tXpdt4vTMx40j%$&vkaIi&2?aZt;S*xd$b*!^zq#sMJK(|EK
zJJ|ePu;keL<T#f)l;g?~8k%8q4ml1P1Z%pcVPZzYN|uZgILK)kaklA#i%LTf%xD6}
z>b1Z;fWfE%QcYSH4f}7U3b<Ba*4b<E81LEU>r~_8;Fo*(rj<9*tv5OmL%G^wTR)Ce
zB<y!Nc!OR3^OkB*dJw01z_p3i2tf2s!Xh98fvHf`sKfW?v>;}BfFCjH-<1&g=Y5Zp
z_PHVKb%-+L5UKj3Rd!s7zJJ~ca1b$Im$JO6*aEHn(r+tbF=uKSIC+;oLm5odqjs7P
zr#(pO#mQvd`Y^E;S%w=O^gZq_>yzWOhfmWPdXw%@kqf#V6J)WLju!4WR)fjO@>|kR
zflKgo<vAq#o&Wg*`~qYDj!c4o;1-{i4Z!pUZ{XErU@(QCOpW^uWUxX8WTIy$EJ*^p
zi@OTbdR8tsLNBlmz1@F29-gM>Avke|4(!8jF|AQRdqCV%FdfvdNGI21zzV_c2IV(l
z=Y+9V1GgtWB9I6OfxHOG6F*$8TZwe?q+lqo6X57_e(qAt?YXaKcA18AKwiiUCN@i)
zgR!!u%!(jdu@g^A3#3yL7lr^cw^R6hSQ?N%a;u@MkIr9xHUy4iA7PF7GyxIm9~?2x
zlGKz2XpOj>XfBGK?87N3#m`(U1M|<>M>L1F6Wj=Xm+=lpx_F2BRGzE3f*C%Qu(GA+
z<x5g0Xjt)e(M6N}JkV{Eifb}W4EzMpu~6KYtJzuLVi=WiDIT=1nb@5YMcGIn0;PyA
zuC3!1nEbSA*&x+GVma%$oRa;4mor2qiwPR?7yo#*ZL0dN?9Guo^C)5Fe3E<+>#RRG
z9tYiNr4b09C}3$sK#XI{ZPbFOxJz54dbBe}7AQ2co9qn*O`@CqH`%5#!^Vvc7Sl}0
zv94>*4?WZi-s1-R`%k(U-sYkvhOgy<udR6s{D^I}SgZ0Wsl~7^8#%)k;05~dc*&i2
zmvzuPY?&SAV|iP8fESQiv`G37AuT1-iIJRp3uJcZ(7!&{3`!BC&K!z=fa6yILJxp*
z#>1rGkP!5-b&Z0V^$f!}nM#yVMs~^{RkkXu@!}3)dl8978cKuCutlZ^#4|w#SBITh
z&uVI_KO+ICf$Rer4E=JysBfU-1BnAYBBFY39r@Z${)>^TmH~%1WQ1U+v;c4FN6I-C
zhOQs8@C0%e^3QA``}c-{1#wye45|Q?yXBpKd*yM1;@xqFo<$woAz!Uv(rGuA67l0K
zlYntHg;GHUu0}RNUMN@XXE52I%#6}jg#)Mhm)YR9vP1msx^$c$;VLoIwq`qwg@m!A
zMiS+_5i=4A5aGTsFz|1Ao+e0#C{=`<<h=H&V~*V}0{Y+DGC&G70A(w3e1R|cX^(=v
zehA<d1X%O%qS_ZNj5=z;Suao%^%p`rbi;B3xD+E_?``GVo~(MoY$?(}{Qdb-3hb36
z_2$I&7!K8p%vl>76HyqtL##TMu&p;G(8h<+_qlIwok)GUf1HruG|~P3y9yf|XGR~0
zN!y7slzbesIufmKNh8?oze1D9FouIL15~qM+@xKMYs-&4XViglKeW(QN5z3f^LdxM
z`*F-=yf?=fcyncjBP`@Z8H0y{6ouJ3D6O%>5!086_Y3)VFCwmHOZ3VsZfd?G^nD_?
zRs7*pd~jTm$lx~usa#G~YegqEY)x8KgNll>lgNi-d#S$y9l4VRcc?#bp1n`k`Ct?c
zUzi<cx+<Q&fKbz@9Duh3@wvNRdqH>tZcW*ipyD$YW2=x*e|vXvcQ7gzOj>MYNIvHK
zRXqN{Hd})--Skx6Ji~=R2@>fsZnxAe)TpT%qF`(pn0)8lvu%({=v<BzzkGFw;E#@Z
zL`N`pYh=VucY!I*@aycl2eJ0U+o?niLkh!<$_w40hTyisi+=UN9UZcy>C6z$hDX!a
zHS^RS8#als3u*_oEq)J0ZMDS=5t@RQBQRrTTRYW>WeO47I#ZnnZWZ)s*ng+wvK0j-
z745ynqb6VH));6Jl#)@)7JJ&lK=bQRF4p9ozW<J`Eg|f=O<+YD*cbT2G&F`d3<~aG
z3qxSTD`Nm-SP`94@QPGMe2&aEcd)&Fx>q^G&eJ#iKBSq!P2C}CRD!fO@tl?|S;dGn
zBnhSi(HtG*VoQS<QG>fF<Nh2ZF^H#iXQPN@Vc(AYl-QFV3SHDXbKA3PL(RwLuK5r6
z!{{62T-gTheL9L#1kgSGnSltIJdKZTcwU&qcHS<(N<f@$;7A5{nmqdARdD9`lC>&C
zJqEDYZy6#>SpuR4@g{cbT*|^2lTQ59K5Dk^rR{$IG~eWIoRC8tihmsWze#gmTW*uH
zAgVA78JALo%$30QhB+2H0=XXhIt}h1r#XMA79*31;)fgXZ@6K>EiVw6gZgw=*s(dp
zg9kXj35x1H75aD@BJLg+eA{HHcESk$Selk&0#pCu5g+0Rj`|J$nuLN4REL2ImQ$|}
z&%qD%LQv5_yI{{ATNz6jMpBnSqx(Sigi@i<y>1e!vN#K;{Ck<|$0Net<_NJWR4eT(
zMOogE-tmQj4j1r6af%uK<F1HQcv~zfL$$&A2*M<py$y5%o_kHgh0KX+7eV(<X@!JQ
zQHAyR0liZ|MSN-hUM*PZQL#=QL)D6ikVa)FeNZx<bRoiAKJYuT97J>&E4`SSmm(GM
zSdOqRy^GL6b38tf){&3_P;E*lEeyhV+kj6un3ap&JF(aTA^ZHwT0F;(D}9Qt<>F|j
zV``3hHbg!<yHWq(w$B4w*$N>IY0TZ-;BC7egwdcVq+csctboLH>n}wtoDf$EZVWYn
zbjvFbh?4LEI^3S&GpZFFmD00N11F(VMbefS4lcN>oiBbLw;5R*HNvx@M=L@f07%5H
zohJP#L;P&e1O|chW{oC*?5tYtBnWByw*0ibK|(V}zbrjZf>qpH?H&i=I>Q1L+&9E#
zJe3|7lZWQPop|pdf1tRM0We@q6ZIfy!@NC8kz3s1$(lDJ^hpm4`K8z~r!)sOEZ(yW
zhPz7voA;jCY!#3v&4Qz@-j6Ef-CZ2@E=qM$+L_`Qobj$K0(9|Nu%B1I2oXt?>pH5!
zE&xP9onS*ad1jAB9^-W@l1-kL<{Q=;rgXoz)FA!xMcPALVD_Fh-tZeK*0Ta;^K3lI
zrlueqm7404wITxg2t!=QdMUzu1TX0{QaE5#8!#l66#g~y_eBeH>L<N<BmwXuz+XeL
zVvH+TR{dNCE>!z?l7nBu3YUU3b80vZ3S>>n8HOO&!mJ^E<#G3?1SS#^_>)j2Q~_0X
zkV>jzj3a00wvmb26h0M`n!sPkU||BO=_Etf-wpw`Z^z!=X1*SW>gvPvrb?%IGYa%f
zk1$l8md+UNnglE)W|V`%mz#jl@*-o1x&-LihG>BRl3jOQ*oVVwV%zHS@SW1K(xa^K
zZXHk^O4kghv?l66jtgP6diFL1%>nr|_FJ*_qWgFM<x8DX+hhq^<%`B0m%NB#0w0e`
zx*qUp<Kt<P!?3SeriCTUA4&XJsz4{sRf=1cb=FR!zM%tL*0zzEG;^HpgE#{cp<n_H
z6<h7}2I7a{>vOI<2igclV2;U;?`Azi!xe!0(X!vuAUhhv=(-lQmHS@lCJrW`J<Ck)
zHP*R$kViKy)0vt=A*VUB!x+Y3eE_L`NP4e?7TZJL`Dziwba4p@6X;`!{D6@Cq``gA
z)+KdJLH5Ota5X1Ut6pd%g#48%y@j&xC1Z`;(mPO;4s@Rfli0z!xZg<?nk~%|Ft8}6
zH^4{%qoL}36E6~@dZC%^_u&aN89;(Lt7w9ZGHe90X=&1<WgjSrN-WIoi>}k&b4s*X
zeG8Mrr1a=m->N0l{jmgi=$Nl~gZ;&Scnjo+JhpULz7!f>CWmRa4;9-mO-BWVkpE=W
zF~K;N>UTB-ZWp#S6yVjNtHz)AOCR}1^6}32!+?v&!6RvD@~0*k7%*;d5^<!++W_EC
zOJ$%yEFW=j)~f`{2J~Ueu*AGJs|xkWup^V!h$#0&rRVm=did;0KiZrR#t$g~Y<)c1
zd^(D^Yq48gyQK*ECNZ)miAs;o@2K8k`E|S&j=ILY&-($v(E@u(zwy3KQvFb4a9)F9
zX`>kgf}XLB;+}fsDfoi0@q?+#_g}b7*_MCH|1nvM-;6_v8;>92&0X}Hln(NOGdlK!
zp^0DUo@`jYpJC}djawl`guvP-_5eydJN<-~0rRdscD;syaFZMF;wU4OY*+`h_~h)|
z%^0fh@HSJn**bzN(kSl*iCFj}j>Uve2G+{jW7tUvc?J2iB7gJ0{*H^R(m>8%ARQq;
zJ|-w05~%n){rmJ3)y6Rh?d<5VFm`o*r8rrx6|Y2so{nlwzFe7>|9O%AN%xlDAyT}P
zbaH==cksb!#XrcRs9~HZ3X>~Er(_`UNq1^`#JlJY$G}#@JdB)oh=EN+(nFX9sHi~&
zskylENzhNa?9StK_SqHxv1R4h3RgC{9*1B6dL$oBN4w0iDB@FQy@*r+p~*4^Broji
zl+V0!|46C^7oDiW(E41IfvEPucgF(f{V9LIpE3Zi3Qiu|s&6&3;X!G4h4)0-F9@Lr
z=K1Uv*(PvpcGB2ErGo{w=!_aTufnQ=;C_7-q)57ijlC0*%Qz{Fxh}vMWnHYBAn@S3
z*&c-=0eZK$7{(&P<Lr!xpM*1Tdv+NvQuan18t;|@{SvtwPy!1W&vN3rio89RcsD}N
zxEO`8h4;OD{%da=_7@U*L`!Ii0L9tF4nX8~7?21%o6fam@|Jx+PDGHCi4T%FqdJ!=
zb&^;|cd?2{8~T{U<H3~vp6<jW`58;axD*?_u4X1IIXM&wz9iVqxtt3{R=$9TBJ_OB
zqEZoN@%^M_xE@Zk2`))scAj)E&h^O)90cMz@4=Ici9}&pD&z$@GLfj(Cle4K<#)tN
znp@WYYUisX6=@F9>dK{%RQxqgnUlJ6q|>k6H$3iubASpyH8#6CDiYEasXidV@B}MM
z*}NmCLi>oDC(6gna2P&4X`cygDnO2wjn;e(v#sRhvk?zL77?QCb1}CC_kTCpIVeAa
zLB}jano+g3*vT3e222!Ur^DhEe^nXkS=L!M8Ynas%dV*)1t&^%L9pBZO+rU>8Qd^_
z{@>h#R*)^t`!2d(d!<8uaT%CHKg3eHKIkYIWO;U^33oHIqB&)w$%0?&go~(vMHF*8
zU^nd3J9UX@Io3tBO$z)xI8wnT&s%DnEGLtbCCu@bU9rPqO4wheY`+2V(L%(}V2elX
zY~BEAa3^V`E%1Ff8!zrHP)Ie~Y?*2|<IO!Lr_b;|QbBhX?jL)u4yL#0twpvB9d0fV
zisU!@zV@!<?JBk}!L{iYzkHZLdeWTu5q;24K&>;8cc(N^F&Lr<U*F^IBLv*<bm(aJ
zKH85VyP$4pwZE%h63}Tt`eST?W@c#<=5T9Kj>yuI>|S)|SXHD5-2CuwcL0{e6e{N_
zRV@Z5p#n`N-!_8Zjl@uLF2xpj9~`c}p$qN|I144uM>ePOAl^aRW_|>U-pZDXQ|`!`
zyt|5aqUT`5t$HrXZnS-u+%<y7z}Qi62Ecve1Sid4GUp0v9XngD!*tatovcWBf|why
zgy!z(j?N%c3+n@dS+B#RcbV4is1TbGrg5a3Ta>_R(BOArD;koApL7q4hDX;o+>9!4
z%EnMq2_*%(v!4de$(Gsxz}c%xjPFObj`#7$`IHeA(lV?KMsXBBQnS^RB_3<jw~q;@
zqagT7kSB@>vO$8NP@kp-D4{XSV1{7>l_k?P<1HNXf;}JypOyca><q;q=&TX{8d>bW
zFhj_Bo})+5%FU->@)(`y5j;~JC)dp*xqT+Y_$DySaoU7x2pmUH6jvx6JgjK|D&d}Z
zSH^t)5_K=n>R@J9cn`;v3ci0`wN4813W*NU*KWZjPPz1T+1;6$9<#~@BIqSjgjy7e
zOv5yfrA>jnb(opHVSmT6oTy=7_$z)_qRnGuKyW<d<eS}b@~WbC=^b=mJkAC;{SJ+i
zG)MWwwXlOh5pMOgj7KVx`<%~1SBNk!cZvUxYOVzY97Yc~vsDc{5^f*FX6YH+c|hsK
zSkDV`e7|eX8r!^?PmNF$9CZ4%)rlV>%%bo~E)W~je1)fTf&Ip5#y!Qt@072=V|o>J
zLx7Nqf8aRiqd};B_zw6bJUP!r_-!qIh@ljnupkCo!<Fu+Y&6gr61vCfKz~EQ{_TfK
z2|F4-X2F8{SDQ#!;P~b+BBm^Y9FF5e8>D9De|ssa@Cfe`iq7`xL=Un$?v;nNdB$Y|
z6W)x)WAgrG-m92kM{jb|Y|&;^@Cq2vj(>ofk~+X}1GEo{#lIpgMe9ykSYV9CQmPVo
zRL1#e4Ys9M{70CWNIW>6(j-9LDG#c2&2{Y$F{8wAgRK!?XZOn?PQq(?l?FGtvBOvt
zmtm%&ieutxJPoilTdVIWsyX*GD(s6Or5_i@GX#;3KrlZoDt0^^0|XR8O}UuafYjq1
zh93+>FNDEZ@Xgqw+~dwJaye|$O&;e5qo9PbT0t*VmutY@$;gk0{U&Bp(U1Q6YuIKB
z<Z0mw^<IHWAFP7$pY|ixgEq4<7{tlv)azO+1QqWjN)LAq@pyiVjFUb&Vpetk#~|s#
zn~Kxl1%uI`W5>RgXJb(tG<l0_ROfx2Am^dNfKMtWZr~*491|?D+SD{W>OiB-X;~BJ
zktHKnB&Z_bjpi%Rbk~s=z-201jG>4Sriwlw6AO+=3*qGxY&xTQn|O$Jmmpl|-~J_-
zNzz(`CE<k>6j%uRAe`F96>Z!fFvbI#z%+%-_dZRW+EbLJ7BDb4Y%Nuy5o1~D)A#x5
zx_{sZe@}6kdZ8KSZ%k%(I0y+(gi?CZ#Vvv({#7(v;G=f|{;5+2$Uz&znMNl}4@o!i
zxeV_7H0S|iDb^X2=T?xN;jsls0<One<f4porgEC|lfuLgLH|h~BvAOB26WNE7ViAV
z&Zgj-5hhwFLerrQa#=i$9O+HPHI$AH3OX8)n$=wHdcoN)rf*kW&o%0Rv%s4#$D(&g
zr5gx|?DSI^RNA64*bhk4v#6+3SYW976S(p{$()NjhE$6B5l|Ct^I_C?I4#04K}{Bf
zY~idhs}9xGxRt75P5GXWU5d$+4{=<3EY>|sZ*mIR7}3EoYlc_FM=`t;f=q^%e}nxm
zm&PEX)`uX6R`3ad&)dmSCR}vm{Q>bE_zsZ0J&Ilx*kY{rZW}Olz*T*vLk~O}`T>Y1
zDRk364m`R8uNTr$RV5E&6|*+T2+j>a=Hi`_@1)4A3uHetgx?D?2WA-HU0Z-8qXqoS
z1cVfX-RC1#6+;eV*D!juxhJpCFy5&PP~4o|oSNaIz{I1}L?Ke#bFwOxb$Eo)#1Z`B
z)IUBidAD@gyM&@*DbOG(a$$|6_)#N82Lhn5MLfY`v>#g;Mv@f9^E4RHri+4bJNjmK
za|cKTKSl=a_}PPZxiYA;vlYe}xYl&(`q*v5oyV2{*n>O;@8JGjn-uU22knXIGp5?j
zc6t^Q{xOTWwK!#5z=OI79t=&F-EYLnOuV@Zd!h^ekOCA6kg=MD<2vB(PoOhULap+J
zJoF2GUmYpLyXZ!CLh|=r)TPg(K0<Q<F_5hhb<dJ-;P<6XfZarT174Cu%EF>R!FET6
z4gZzd%@ULWw$FdgFEsN`umu2WGu-qxRc^LS6((ji8cDXG^sRxV!}e~2wec;g3L7m_
zHdZ`P77$dQ_7&8i)?CACV9h@1&a>$lSY<Z5%~4<<;(1hhxSo^f;z>t=z;SD}%to~c
zq2n?nX8C7;-@<|a#ea<+#)c6aGWh6Hd!-1)70Y*cyr1ddXblkLn&6U5vonk4i=w4A
zJP=p&jd}WLB{<Doh~0<SIeJK+X2w0nj-cj_(0<SbNIdoI3QVNMI~zL4IXLjqR)OaO
zs{Cn6xiB_sRA|6vPJ^FoRk$T;#ScYBOd{{!fX%k2xrfh)FEAcA1xpLVV%rP~BzRhl
zqO)FwliL!6e;vCD)cU@w_f-LL@o!hYU%86vdM_bkO3<94hJgkvTo85{EPsEgdhi;+
z`BMdT^}5_3=gH6I8C-GrCb_G`QM&1Ie;4m#(FR>d*I3k~FtoP<c2w(G)QAJp<F1RN
zUzY$4$2bHPT|^~(!~DST*=)eWRi{(~k&o<d4ao@c5cK9}T|OJ%<!_pM*EzQbxCL<a
z*!5y3%6s%lK~Ab~z`_CnX6_%`KJdt7soanoFQQ`oxs3V^8y}AR88QxPaKy=-Jv$0O
zozCOtC2{<rH#~sd7EIi6<FTvqA5eV$4z7Nk^zo46e_Fwl>H&3yeehW6x^1<-=T#!N
ztFqwq%M1-^m=Rf_sK2mZ;IV*h3*oqs@$AH7x521+rz7}y^DbywM2qHdbJGC^JEdq~
z=*9GLRgFGj;uYpp!4!8WYrPAs(HVIJn!&E58~kGAuQ2J7iaBOa5>%~k;V-6*a|KRG
zAiF_2O7FjpeUBhqvj=2)%O~ywX_Rh~Ej$EyuinKw`v=d(2M)#K%3jWaRZR8zr`gY3
zJ6ke<bO$0>(ZVW;AtX)veTdPhI8dacb-_$H+%T%ucO}=l<qI2kN)YkqW}B&^bB&+l
zz1vt_QOsmR1h89h_CdnTg40bla4ap(F~u<Rfghpk&7LfwUP7>MLbmG=u6foV#yDDB
zsP+vhfI=5!1Pah(w(Qz1L9ZeSekT<8^-*@|sPqtnpnsePZ~C|RB0D;x&}lZ!1~{`J
zDH%9^23If7rE2&UFt4GeD<ei>=LvFzX@Gm!DTVZUL7u=q%qC7pMo@DIdd=(Ep7o*S
zog$&|=qya0Q&@}un$Gt=J(Wq+TWjx1n1&_<1FyXEfByJz<aDIC0X4DJdpT4QIz~J3
zPgCR*VSHh#1V1S^kXhYN0G)~!KqnRpKHAbnGIzH-6uHI@v*T1*!6S(-@&Pq+Q!&vR
z0s_Hyp2H4rb#LXWsMXPYB$OYyNz9EC-U@sph~Wndqoe8GqVVJhNDBk>g=I1~7a!X1
zqRHwS3vPqjQRupQC=dT!6qKU;*ft<01llhm(wV9YZbz8jKK_%hh7HJ_a2dco>5>q_
zS}%bhqhnGck@Pmf(APBQGrSb_^0V+x3+4oVtcFYy&xWQMDyVkq7v)n|f7D3%^*;5R
zd8AVuFtD<UG>QdPtp=aMO%?`3SU_c*n%&?S8q+*wOo@#S)|0b3JR{Ir>=p#l3)P|W
z3U`ljUrz-r3-8Tirj%_x!ST~t`Zce3DxC!9?gk~*Cv=imzWsaj1k#E?5c4Vb>Z1g-
z8_J_Kx&tkkK`GM%sHik-NiDsy+Tyx(>55#d$Djd`m%+U)!2!}qdQ5YgufzNhO_^3Z
z$ED{AkNpr=AWL#gnB#QZX29PjSsq>o7?|EQPy&-bfnbfTy8^PwL(qW+k2XYisC*a0
zUwN3hGk6w<ejA7RcAkE&M$t$k<Ut!A;)H>|82Mx+0!gJb^vCP3M}*594odmzQPAi?
zBon_*+gX1~83T;B5U(t)1<`S(E+GWJ8-bJsU&Iz<{PRPu6WWWOR>^-3F7}5MaG`$f
zJUgO=(BNhZBY-n&p#7!#j-V|N!r{rK2wL4xE%AR*<+s4yDvv_XFzl8S#_JJZF!7no
z=eXN^Oym*l?_D3&BizCTPmQg7>Lh?_Jg72{AXp(b!QgSP=kvqT2!ULJKEUD~$bCrJ
z`1(5h2nW%s1bS+4Bojc82vRBN+z@44Tged3k2v(szfCJc5p%ge{t)e84{pZIt@w=c
zzJ!&JCI>s)yLt+EE3(H!N<hbF0%bXE0tCkQZVJg8TC>FpFowyA<m5)xZb9XY&g4ev
zd<;P=>_Zu;!jgW7Z*ub|>eJB-&;ZY=#Y_VE)=I8LFmL-w_i?Q8SN`e#N8s)TLGNCX
z$l(w$d^<t?78n8UHO85pVq>FFg0d^ip6k^=uzd6+I<CVhc`qv(U?KuL3S~jR?_t;`
z2R}$T8kV|+UqxwFNX?}+iChtLp0VMZ+Q5!8xLHvc0m&gY^DQCA<JN9K2o>NA9pQ8+
z*0T~H>b^zg;XGHPd9%wr0oo-qs!jZvTL)swCX;J2Kut-oQ~+JQ|3}-9bP^QgMUYO#
z#*6TrOVUvvS|i(1(C^7vftfW^PV-{+b`4g=i-sLDN-VYX5=h&<@pkxE(MCxIj<e`3
zrm~(zKp}KfIM>zH#2!1b6v0t%X#b8G_}iuXQ>ZNt;4n9Mh0|Cfpn9Cwv<Z&Wd+iN5
zI0c<+&gXW<;`7Zsw%;#s$s%USX`?Fe0b)&Ns*Vm!qz=qdH_lXjSW$CmdV6H=dlnr3
zC)}n>1a8C16{vd^BB5^yI^}>qmdDU-ZfDRMoZT4PK$A`lp&Cp4GMVZ2g;(O?I8?YX
zE~$ezxx+#xTpmaY!(p@tO_qe;rV{`wj4}tC`#qlGV4e+1(L_F~NuwyJ#Nulyrb|WX
zL(2vIj2#zVmt`;|(-@Z7NxPI+xjGd)kr&qhVjF+U&{-|{^N0kCFFau2=)V1}-+L!l
zt)p$M`0G#zQ1MX$C+A_m($L|j7)jykrSF(6Fsx5_tB&Pb*1Nb0xk@2fgx@bU&&|G}
zFVlw=a}C2H<7id8$u=ExP$^L73HFJ)dP>eFK}A7gM+2fKvdC^PlUPc~<YU;e&9;;-
zuY#nn)@mmV7;hvGRJczBs(HRbUxzA2QJ<s#V~U>xN|u77&MCui(OZBv5I8&Fi2bKO
z`c(u~B|Z~cz2{Q$CGuj51hLq)Tj<_QvB6X-705i%=2&WR;)Y@GL7T^xQ59wA0<g?7
zdpQ<(QQzx_Y<yma!W%~e&<=-oJTM6;1WgVq29=$fz?X;R+8m(9u3Qs?(}F324bspK
z015=$0sg?fSWHUK;3NnfjaBku^YjKk#u?s<b#HTX8<yo6{*M+OJ2$4Z%xjwShwv{Z
z?dxDXBw>}4=kIMEIUK2pbDG5vgzWrPaM94+E2K-uEL8zb#>dY}<0gDQ&N@awV4WB5
z)bMH{x+6Vz$h@+b@8uzPjaEq~Scj*TExxJ5)xCfwsIW~l%j>OG_cm%oS&+b>u{{^|
z)h6r{l(|Ns84i?a;jtUV-$&yroE8@i?-qKx*W{1q;ImkX$Kfn#R-?@*N|JH)kZGo)
zIW6-O?UYl3py<7mN(8S6d{VrjKm5P9&Y?az4Idl&i7V5gJM(B*#}@#~CP&gTsDsJV
zXANc`1x;b9CNim2|64f+?;F4tp!QI7jol03;y*^@epuPzWG`#)*N@Jy87574<@1)s
zaID2T4EcKwN9Gao+E9}SyO}0-6^Qkg;k3!L?4PY#_;gT$;DZp&T*Zx8@w3^RF(mda
zZp>a&&}p{9?PpXl?WQ2w|FdP(lhR9=L~s)P629;KBKo{^Qgl~rRdSUpfzX$ONGD2{
zj<oKFn{|X3X%l5O_%;Y?UOn=l9E>D}<l>8Z`wK6}_A24`30i}`P9NAI%5fHZ7y-vI
zzCru2(1cCrMr|0BvIk$fK#Zt+P&2mfPOnil9Q7j{+_3qM-N3=vV>PrPTY3cO9h(^d
zMV5Q6am=ARpr{;N*$4nIOu2Ab0QN%ztxtOO4>xe2*Br1GR@dDJzIZQz*n!)HDH|>k
zF5urL6g>h$1w4fRzCo1nfOpMfe^^K5Y$b7A`8!asu}r0XFKm+8b#x&2k)yL9AI&$!
zV2%#0PYZygoXSltucA8wE+DTyRrNeUlZblJC-3*6^lfwUW8j5^+sx^8k>^lWP9{$x
zsU#B5%JLVn7>&uiySW$e@qp;6j`pdKz+<dQ_iO3v=*fi9&>oVKl?aF`5P$#rR5Ril
z5X5KjMWkSAA;C3}5#7X(V+7T}*>l*Qnjput444HME`gJ~svQnkTUwwmyuonT+C%X}
zyR%jvq&L|*p9FV}kmJmPt_9{wB=;cRfMqNq!MkW@LU?R$65gvRbqZp@YxV4tb?lWy
zwr0TvgF*)&_Sx8m9A5FuqVKAg(A^^b5q=^c6|(v$TBXq0@70hE;UtA3ir%xo`sMFH
z;yUS@+mYe1ZM+EmK#CX+5BN=?Af(TJ2f}6=Xgl*~*KLFvn9;r)k))d36nK_A8~gQ9
zJ#yaz$nt&u&iFwEro(uLGQf$Q&O<|RerRFpg#8i%->yJ`WhttwCAmrD7^>is5Ss5-
z@o+Tfdm7rW>yzdB<n5o5+c2{rpL*roZ1K&ZW%??j{SNy3Q{v&wZsr%&q^Nk%y>opv
zT}BN*PcY`zpz=Ig>Hf`^z(V1$7L>a~IG+Ky>kznIE!B?((|jP+WkVQ^7CI+BGazny
zwiw=l{D(0G#Xr$gOZ)tH8G&z4->VOF#<jalIe@0FK7PV{nr8s9%&F_eQ{ZN>7b+6&
zU=jQZb+OKN*<*|~v&QgKQO&d->(c}}6e2WwM}?Oerfz--iuyI)GZK&YDqvdFXvR8c
zTESp?TXVMS5?uMuz>^#Xu%EBS_BqW6g<&xWCz4tU8q**kW&bof1*XZ2-=9(j&7gz=
zHIug;&()fN96XCs*c0BA5hv!`XOC4_&p1()YJWQ(&T;hYABmsUyK+DqQ`ZH0&5D60
zkil%hRipkzhk<a)Kr)#D;mQ~rvjn|ji~*V45Iqdom{+8>>#$Ah=-P)f2K~PWxw6Q+
zQ4c($B4mtBc}+GtE3AYyAVK?DAVX)4e(kc+sQFL?fmke}v<jjEnn9nbDg{#GDS+ZB
zJ1AvtXcH*2vgLQyz=a!vYA?Fe`WC%KAT;OjQ}K@e_WpnqkKW__Gy^(;Sf#SnmZmD=
zY!H|mjxJ385_AgOxoyzp5#@1%dbJGTZL(TKw+8?T9I$h<{uo;UA&c(=5Ih(8VU$N^
zPK7_APptx!7q7_jBjgc`Vt!TsyL(?6aS3!PsIPLMvE)MjKw*Mu7yubUa2`i72MlJ8
z(j<miAbBs4B$;yIwRnZ}cXu4!M`qzlysPt0db~dXP)|qBYevfy6E71J1>Ck49FN*`
z0VCv$W(E*%w_xj8cIKD%sfn`qw>{{LH)t6-iq9|N1S_;PVjn3pFi@&Ui;tUji)v54
zR>Ll}6E(;qDX;0W>$+=?{x0-aItPB!4W{HulZ;;fqbaVB=>um|pv_0k;ONA*RZl0-
zA1j(|-gW^zp>73#?%pDu#D9(aijvT{KA5KmL1;J5#krbOA*VDMmPb2<q6myepic|q
zq39Asu)+l(?5GA?b$SF$v8-q0DFe;sII!pje7LiV{8y9<y^TUBKVvo<f{co)!$~Qf
z463?>HkTXh7wVVaHp1ZJ(X2qONJ2Xf?Z6nkMz=^qNr7ZEQz_W0EKAGeKPftYUxXlO
z-Hw2w74>krO0G^H{cE;O&iVKG-(YtMJ>U<;6`)7%pupP8zXLEFo$~4?tg7`$D@0*9
zHigv@Qz>z$)~J|^fH`d<5RRg-+WvH6-Ge+bS*zl>4k0b{+>H&vU8NuEr`;9)z$Tw<
zKB)Goe*o8>;H4kyxo*_0NiS(!k!X2MM$_*XfAJf<pQzoDc0&O3*$P%KE{NxJWtygV
z03p~!CTuALo!V+PR)wIPEz4(IA5sElLA<~&&$4U%?KHg3<DFEg@P|P_DcXNw>JgOf
zQ24iV+63TmwuU_ojq_)M@dzT<ff9yOS2(V)MevQ)S8!m6LN_B43Oqu$FG;9@z=^nC
z=g=H2%_`U82l!i9YXFsSxxxdaemjp;g|2c>EjlG6$2+&l9&tjFH}tb;YY@K<V_87o
zlyj9x3d};#Xz(q<42Pf}8)ad$5T$djE#r<aNmY0UG2Ke0FP<k~K+oID_xV%g=v{DK
z@pj-!p*Z}LGt)I{W>kF8Piz!wRY)cucqnRpXevXRM@n1X<<SL#-xW?Y%gk)AI-fzg
zPu7gf*bDEVXz?xR@xItR0x&L0QEpQACZ~McgwgI9p3WDbVo!WFmMreM-9W)5?|S-R
zu=>SwUmJ0S2`Ko59J)+WatNV#4Z&D}N0GLfa3~UT0tFuu?PU3SJ%Sr~=e91}7Ao|O
z?iZ%Jmtf-k*uU&Q#_kdQxEQ>3Q0a1_|Da-@i*y7xNl{K-k<S=a&~iqrpzr39SwvkQ
zY(@t|GeD)3`DNkMWYW&o>SB8v&qScRc%8AiYm~>rE3^xs-!G=YbZ_Uus6N6us7rV~
z5)Sru3C<*t6cTJ&*cNN@z0WeQlG|IjtTh~F0##)R6Oq~>NQB6y0+*kzjh`dmNpl=U
ztOc__w6Nwkq;NIzG<G>|gWR)8VCU`B`<VZI<pqjXceD^6R1U>w)J86@0ys8bpDIq4
zp@_XCQv}_&gdhQJNHou|gA~{woQsOnFQ*t*Y}iEZm(sW2Hfng3Wqii)vT|u?ZgvGm
z(*6ta->$z{Z(Mx}slsewpJul$uWEl#`>iYu>{@Jn_>aF*eMI>F%3GBN>XV-n$N>H=
zLh=L>;VuLiPX$o$gZX9JsR^$wU4r_LCyjazt@{-WFJklex*4oNTXd~|hTlVHF@x#z
z0GHD3W|wIP!9AwGrv>37wp-*8==y?^zUZR!Go0e`u*jLB0nCEu7-JCXz-P63Z^|1H
z&==cpX~-Q4FVpT>U>VjUN<QlmK7vwPMWX5hZ(ee3%<7S)&!Jn2V6pGt?g0jHVOf5X
zTnzzf1`z)Iu#KY}gCLPIEJJIVQtMg4Q364g-jxt1ghNzrcfY^b(G7Z%gQeWZr{gb>
z{zY~qek4Bl01j0;foE%Gyh36WmO@kkCyWs&I)Gh=;Vy&8qZ<b+PlE=4vOlKUX0x4M
z|I~aeQG^Qxuv~)gN+etiBkCJk;K!C(&ou=FP@kA`w3#<Qzyvr%2|);`Q@|LgY-*D6
zD#3%j`}u!<+z@LBuoE?x*jQ2p!fIHD4y}!(`ZXUhcK_rGVVX>%VDCg$63+X`4yN<P
z0y{BObg>xpIVydf9Yp!89+?T8MJVGrc*S~FotjtNb79LBcW~GK2V5`*G~=T(N;DM1
z_*A%Y>7NwMQCO<sOF?7BqyRueC?p?>EzpH{c%?rkU${rP3JV5L&ZrLn*-dGdoQYX&
zz&Bpb-7je51@@;KU%CYq2~|x@mtPJQ-yzWB5zfi9f1QRwG@<6yzBCB&qy=~U#&TT-
zSHJNy!@xa&9`Gdb-;0qSu)Poi<Drqe{`f!#E-BU({|0@SJ9#V(kRmslu!%3h8!~US
ziuNKgU{wThd??N!8s@?9B9N?TCT>|0zH?)$O1&TgK632*eR1?0#(9w6#MdU?v}f}P
zu@Oc!2z<q_fcvx(XmP6Ux+?$msrxX@3sDt>0KP(xlKC|Pd22Aw`g2g-C>c)`Mj_Eb
zIR^<ZB@-Xk;3|I}j|h}<WZS>#j>`{`2n=?#E8gJ`Hi)Aiq2G1R9*im!1G89xw$|ES
zl0On!B5cOLLJyA^O(D)BMm+$+2HDRBhho@S?>dTf>yC%kZWrM35>^a<A-14k8kyX~
zZ((afeaZ9QO)JiUrfm~>LW?9|+PWg2G}35|fFI%V*4L6%`6R+Ya31lyxI1$RGmFks
z1Uk6r#N?=EEY{qorxFpA9=FLIkEp^X^@@;?y8F={=6{3S_49#!OlPsLa~|+%;xnpa
z>)J%jD^9|4;Q26HM2u#9UPkbS*8o5Zi;gh^)sRps3+a+(C6n+-o+RnAyC2gPwr8&i
z+tICf5Xyz0#<_xi(0muV++dSU|41FHp-<&X1mS)OHn)rJH!IDLkYoj@T8w8SfjdhL
zs9|B>V4PxfA9M?>hOyDzUl%Q8V%jL0KA^t^Mc;7)k4K(&`C=%P_wQ9OEu>3%nE6oh
zD1lq*3A&eS63v)kh{wuyOOj+gxA>$`lU%5KuM%{sr?Av;B_IXCL7_Xq0)c=dLuyqt
zcgpkALmNX2h}ZFB+w5alMRL6NCK#wi3_s~HGov{TZC2|>)vKq=@GqBr9+ucI?(SIt
z%ZwEu?15qwp?i@?VHm3T8l5J<4CYA69)l7Gg(x^F`Up2L^b_<If$X^CUsm=lo|kp<
z5E!+F(oDXtXzyeEs50mTPODL1$k9DxNe}D=R6Ai$k@o{NU~v2*o{Y+nrr;fiX{10g
zz^n+Lqi7^XeT)+-=eFiHOLNyaAL{OpBUo?aQf^`oCGSSnZy|O<wy_f#cyi@*?Xs~Z
zt%(LUM7N#4I4s);-<N?}BU=QrNhr1jxR6q4r$6Wygjzh1Rt*q&*s)a&Zinjd5ZW+D
zkQ$M+D))4(w)qzr-%F03=U8(=lk70QFYZ{=+}eG#*FW)wv({<p0yxZzE_M%ovF`#S
z+{Z9K!4wpsok(Oh(0yDg{#a_%a;}Sg_9}3~wSED*d3cBOSCLg6{;Mb#eM_TS@+<aa
z61heU>x8*Mj{RSM^j;Dh6pX=KV+m=e-F+G86HW@WxINg=b$=kmn#K?X!29Iw-*+~U
z;nTHu8i_5}=e4!IGPg-?hD;wwG>kx;;nQpcrkj&9`~hg#qs^aYPYq+5U(#5Dl^x3m
ztE^3MwoCy7!5FH}LV7fZ0u)VQyW9Z!(oW*MnGJbCxjakJ>vK#;gULbuz$|Tk&oXCF
zd_s;$&m!%%LN`DfY#>Hca6xzfw-Fp*Uu9da_*x4Y74qUV5hS|YyW^+rm=21m5NENa
z(H1@$260=AWNR)O;@`$e1y7P!-0eAY=P23h53le;;31CpcLDjJ$@MPlvaf>wilTVQ
zMpqvzS=D0JnoD7cx?U3%K@E5tuh^Y?DSE3#)G(b->ZeX6ao*Frk+%(S+;A{sjOv|I
zf2_xMOhGXLA(pQIYU5FXh61ikZ>!g<D65O*3I-w^M#F_WfA3V{0-jG$7{cY3<-i6J
zGdqME5nG3TOme&7U_i1Mnh90ID`LtWwB_3v1%vUKC<q!$_qx0HEgDt5gM@Cfk9i6t
z4%S(}ew^)d=r_PhVz+mG70?3Cw$CMrzU>OAjyQzzksmQkI{=txT1!qmD*Us>ipU0$
zgi0P1WK8GK0xP>K3PpSab$x)V;MTxB0;5Balw0bOJXzb{u*e=7TpIe<{~HHRZHS?C
zfuT?U*<deu9ot10(-uWVoYR`2e_mh4^G#q5lnwL?j_(KTrC9~#c)X{<x0O`9i=%B{
zXn!e;^2AQaX$deF32-*=Mg-KuKr!K;1&;}oL`8*%S*gP&I+}u+e9n%bA19Koi4Guv
zS?8f$urdWDLVFhJAq9?QI2Ht}zHQD#^Be`b>VZi@&G5X0j1Hw2oon-VkL59V21PNT
zO(*dpMow%RILEqlX%Ox2ke;RrI65sor8$Y=Y_e{(p1}i|M{)SimBxI$doTFsI64^j
zDeF{Ms$igw#uZrZ#>||Z`H6QO8_fg!9gyBa77&>LboU%cXd1-eEMXoqSZ)^&yryOI
zHM<419lTQr6qwrl#!ws;>k176ejbDYYY{^yX1Fx~`1Ax;XTj;y5Y`M#M^2_{c;6=P
zn`gcT$>3f5A`Hk4LBpn<B%+Ii17IyW_%$1F-b8@!bWRm9E_RobzXSH;S90i;inFwD
zaV_+Qev_@C#+~N(NIwEk{~^R_a5!f{f+2uJt)duDSaR!@+&ba|bHRKN!v!eVPnuQB
zGJuc)D1T{yRIQ<97~|f^CwPXByU`nbp}%JqG-@A>DRaWWghLCb;35J)ltTi|mcjAE
zJtA5||L%YKDhk{^5T#N}z&F{FurGvjWN;DVp5c^9@!`<`aGsc|F$!r7s=U-v)+3K&
ztzE3}J`{j)J&OF4*R`EE<n?}d*caKq1F{kJpw{9<+4byJx3)VB)pdmp-?v|=4>^WH
zj+)?g?k}KNlqR1OglKl74o|`fS6Dre)h`X95Si^CI<`VVRUE6tv7kkm&RfvX(KP~H
z5wEi97!`=Q#nY0gg17L>pZ(4K3j`)S5Qn&TDMac8;$KFv4q#m25f<<bl2m}$!8C}r
zOwT748WJ|DBUMSvlet(43ghb~((Zpq?*YPF!+<@dOSE`s+psRFSQx`upy~}wey#>T
zsaBx1#8A$ZDl#6>ejiYqh}RmT8-}l{pE^A?lp>ZJ#6T_|Jk1NrLVSVZkh30!*>oQx
zvI+e;pO58itT))a&51vRrKo00p8!LnK@3Rc5B}ZLFh7abVkz(}Shu|hZbC^9Z1QQ$
z-ET9%g#+k-J*$Ti7V(%iWSA&mpq3-ku@_?({gK%`IZ8K`bMQFEwSEZJJPL9^%j8|?
zlPI+C@q=0H2=rBpYD5gp#MCk|{jdv&T1<x;g`0Vb6(+y8+5&mmD6d7<q(*tmWh9oH
z>w&Fz8CF}q!|{@bQ0ZWsYE-hUAf^ZZWzpPIPkS=bZv~+QUcsL&wji94zm>^`4EIk3
zzm&)!pNik6r1}R)+D2EUiRFFW&Ymjn5p$g%H$=^hCcK?)93Luf!d}|Pde4i|83);e
z<_v6EJo-!*BoKjLpJOg~ggc2!#1=#kXc!mGH5e`f;cJs)7d3%Zgf2a5TQV#W^5h1D
zrZZJUMf(5p^!~wZ+-I6605b|Ft4!F9Ce)-LO5a8|1X8kOfRarsw#5b;6l7B|0YMC{
z<@pSlR6N<)i%B`N&fUyLO*SmjqQ-_SPvnYoHYqXX%VsyG<Uc%hQ+EapCiFzUn6&Cf
zsdZICS;=~GSC>edy2{ke?cC?3GAApU@r-_;(cka;<9VL<c?Gc9lRA?*!1ydZQ^rK@
zNn9urv<D_9Y#=%ZJ_s(GVA6n<IggXH?o(R-_NSlIX}YgZE70RMEqGPK2jgJ?cc}3F
zh-3?Wxx%4As1#(Z)fjG~%bx^`#<*cCam(J;bAFE&rO=~AWyUOBqdRrRRmIw?PiB%|
z10fj8Zlcx+NPQi~W7_fsbH)|e2dL2%2NI#$LH`InLzSG6=lSXgmY@5K4!m`#DuS7A
zo~nJW8^~wFMm}Rjx+by4F54ns-s7~3H9fNt$jJkr0x`9BD%_qnLchcZzxJxwUuiU^
z_i6;YjHu#qY1NL660dT_AOEU&L&{M&4!wOffKHme)t36MwXL%YWsvyDKcaWlGJDym
zl2QjJCM(%wY*TJ1xzL{9Ox?JTufB$AmXKVh|3M+IC`*}O3V|RHy|d-AQaIpJ0bMoB
z58yQX#JqLJvJT9{N~m4fZmJ!X?7%sOjK;|CPWDOu)DiDgokwT>;r0*hkMe3U&UaO2
zic?9t!{b%0>h#Tk){a){<Fwh_+`uv7BaPhfN({^%`&HC}>F;&EenX!~%fQ#=%y_1z
zZL{L^j+qJdX?D$;u!jWXDgGxFh{)CTdZ&4aAjIL(cl%NpK!s$Trrgj8T810-U>PzL
zKYC&Z#m>eYZi;8=>FL5XUa56y;VLu=-=L23VhrgswtzvCP}Lp4@FD}G481jRmeQvt
zx;QASt=g-@zL>61o3>)zk<l_y14;9~T%muI@7XC;%CLRR0#;|$UB&wx!S1{IOW3z!
zYqkh3Tu7vUr!0i0UB#U_542-cInDeA^SSt_Pgg?DP%aL$Vh~CImu_1a__0V1e0J#9
za|;G`$qh=1a{Ybzh;ru6B)Tr94@}LG<(^i%UD7P}s1!br<NQs?iWQR!#Yu0uY5A&w
zWQJA&-<JPt;?yc57NWLkeWu1dm2uyOfeE}d^k_DFG&kzHWBi@ylLE3C6E2dE*{|Go
zwD$UKGrb)eO22{q%wp!UDt5Q_{X~(~!IeBbi>t>mKYx$bhT%?>F_grN5E8m|lM^Aq
zj;F$I!eKt9No2P^`kcl%a<@4^YS_DV|BA`cBRWLe6V?^|a)uH;m7>FfQ1)E!rcE)z
zMWR(`=pm@9zj&<WdPBNYiLRJVRNDj*3GdQg*7s{ii3(bY9EkclTl~K5HR{XPy>Sz|
zmv8SSkUO+>&v$;t-qo$qty(I%DzLM{^2aJ<qHA`<fxG_xdbP=i6!FXT4T<!QGO>=X
z8z-_`;*hn`+fiQ)CHY&1S12onnI2?-<vDZ<{53PRp8J2FGS74$n9rDrlbPFkCNYPk
zC40>~XVYfIhTtUo1?b-~jtp1)530Yv`u+Ea<vFrNQ2qIZ^v2Y7^zH~HE|8>Iv{5XX
zC_9kSOrANS_$>jQzH9hA)k@nLExD3<N&7UKP&bse)V=>4&$UHNdDX*w%qFKeUmgBB
zmv~_LJYU{bNV!-ulJsVuB->uoH(r#W_Q^66T0=MMUW2cF1?P2l7G?GG!r#qIcAM>q
zsc2;P)1p1*s#-6sorr)=_bbON4m5xR{OWllq*I^$=l_invH$|dUG>Y_d4ekMXs-&l
zqVdv?7LSz@P)~MwY@lcbQk)&xfT+RArYV&kG~bx)PH&IaR1`V}nO^rE)tN0OlFvDt
z97v^MYvK3+I=u@>f2A1SQ1YJkgB{cis;2J<w@|0jHAwe3WQ#jBlWOKjzP)a63Vem+
z{fz3G!+2gX*|%;Hhp1Jb${xy&5q_wIz3lKaUT!!)*!ZbN18lZaH~h!HcvCwP58!4y
z+BC*>3zT=QenIWS+AC@sX{VrlvwtW_eCS`!ZmyPQMJ7+-L{Ia&`}-ahFSczFu1M>S
zLeQ)AgtZo3(<_<WYGuNT0EY*TZVrqLd}#WEvlNhTX)`F=1sy?KT_NsK3sDJWd8n~S
z3tCOSZ`rBwj<NB2c%XAV{(*~$t~<bS6EgcKa|3%}@!W4zDp@ZFv2w}A5r<)Ov2)`X
zh->)lt&_&vaTjuh3z;^zbAey45yH4tz^0O&7~8U(LOLh(`xw~SGJ}g%j|t$PxeQDB
z%4aqTkfg|>7s}V$xE3#F*3*cO_J_MTB+hd@oo72HGjHG})k|8gnFE3hMJLz#imyV|
zb-+2BW^`1%Z;=SMKU(rQ7HA9~r*IRJ`z8N2D!p#{i|+RI#2mtaT}u67xk=Kd`750m
zYcE<=NXio4fD8{jhB^<hVeixTaNxrzvb5`dn%9ZSLtqp9a~_V8cp0(G6>zv28YO^s
zEg*Mh{Ec8H8!d>I!PL3Vc6AZVq-`#GFFLW?3MIyxKH;qPA;0IrV1|gfz3*UuqU-lj
zMu=$mluxjb|DUwxaun&#MWukhNa^Z_hK_)n<VoKE<Zzj(m9EK8X<)#-rP`Bb_E7d4
zU_w&);udZ4jRQOeHB-RAVCMGEcRm~U-o=%SQAAQit;&=mO$HGv3V5Ahw}EIub3lFl
zn+5|=+*$u4wp$#kgGck0+q%==Goy>@W5FtD1hy-m!<ev&#T<YT-GH(iWqLs`e%{m%
zxj!XUa#|4a({h~h$wsg&FigBISDL|&C-da^z%ygC^4v9_mL|Co1G_Fp+plD<SaWH8
zhn2l-qkwS?1J4m$zY!ER7+Jutvt`=9^;am8f)88_g^++8{<(>bEDrEW-v%RbG{YeI
zF$D7^uGjG&I$z=NZH#Yp#9`k8U-Vedr`l@iJsK-F?g!ao=B0}UDzjbJziDBOQ~~m=
zLZ9b@4`HH%cCt2clSxYeRi#|g6v>Lz69Tp~^!|?0--0E|0sM2bVJtJK4<O%@IZIKY
z9hgr$H>~i^gxz({de(l&qCp*tHC=K>f+_{iv+>co>(46p`G42EBTerdRL9LfibL!p
zdOO<9WWVDUtdb)FwkFuo&sv~YOd76Frd8SJ47IHh0;5N@19uV`6)mV_CeemB-HnP>
zOe(5Y%+<L?@#%H9%y0}2oMI9xwY90xZK@FY)&X#E#11SkxEqg5K{#&k6k^*HehD|a
z19RO6uITEbYMIR9J<9A#zY{C=m&-RXFB<kfV(BZtc*_0#zyI#D$Z{lo62@pwuV0|I
zscWZd`oq9m8iMwr96XztJ+~JhrD&}KkM|)e{b(A9Vw>9X%6Ike;uyF!8XZ@cGq(V`
zqs8dXO!DtqGcpR9%j&E>;&`@PC+49aKcn%Jkjt3u-DB1w_iL<l!o^Rtohvkg9P5Hi
z?mibs!X)(@I!iIrJun|l={<>y)+xT&N|rBxH8o5JAqGEd9xii=A@gF>xBvb}ZzC)C
ziA*=I*T%KO1@jF8f={j2J+9x0YWlwYZqdyh^I$Q?vXpKk160bxD;VKXOV``J2PV?f
z6ZIF><!)@vGt8_hwI8gTH8oklTQ4{CgSjeB#sfaKx3qzQD3J*Sp!QPbadSKZIT!oa
zG%j?@^d4B<qFZ~{6z$`pc{v4$f<4_uT^LZJI01qG?pr%SRa7aH0R+-$LK{86m-NB9
zFLg)zooh>P8+F4+@qS@Dr~BvAHAEI$NmEgp2EDcK9&LZAwYBJ#M{PmyJBX9OxG$ks
zb$cP8Ti2s&W_CR~-`$}xWTb6LckAybzHFtBjVr9Vlj>5=#Fz)`p=p0L;IN_ydXJMA
zepVP)DU4+FtCuElWO@PBeai*I!@(E&YIT}Ww?4I$nu5)nLnNUtYNvRlWYJ3ggKb;V
zt>=oDoPLxv!Lm5hKBgf^(A)3CcK?zj1HNSX-|<h^&R5GCgr4arwpz$6v39JKQ#mG^
zO21w>jvVAFikA<mq+p~4l6no1;#U0){ff}z?NDyX)y&CE1YOa*HB!V77rA0-a+!I<
z&4a-Qz?X|i-qzvCX`M(>a;G*N4u}j4!z2YK>My>v(9r}IH7m9`g;}(>T&i0pru8XI
z=BMV<d#nRB$Vwr1-?K4irvgqo#a}Pu+Q~8U>QFA`CCz^?_1|_!&R`8lOl3X$%cfzN
z)OxCQqa9Rs>6?bo2c;i7!#~I&CS?Sz?8g4a5QC=e{>cabo}iGpqRp$V-LRYK^lts*
z=#mo`EQcjjsDvloDuvZqRIiUwEemT<g{<5F134|)#_T%8us1l03DDpA0rK5}QTHdr
z#CE=e#0^Z^+vhB{Z$)>d6IVz^T|kreKUfxJQi*ql_~{Ed4_}u7(ojQ&Q`>Jp_`u7E
zi>WHy!fW5D8CCIV*#efglR`q=1K6wJ94d_R*V>>TKU9*{JmZ>Iho(T3^)3MFYirYs
z+9HS^oOz5;{vbDNZzhsF>8w^V)?kvJGT#x$_dM5N%%5_MA~VdB@wO;rrN|tYtQ&Fh
zO9R>KcRA$w<;}riT12BAzkOsH!I=cDyM^&9U36mOa_z+8gl#umuoHvXTwE6kuqact
ze=_1|GONuUJ->K5a>(VcnOa0-N_nKs!ux@^Y-29377ZD#ntp6&sI1)ez^@O^E;q%f
z=LxtS=JuNYeCI!=(|E2$*YzujqsX<sY$cWw*tRUHa|ybYY;LHr0Cu0x8xI+|I5m%s
zF9DJ>ARrr8UaI)giBYCQoET<&64YA6rg2JiPq7r@-#P0*MRnFPR_avI>brrHXUTIm
zmHCFb=3d<6E9)`!pZ(<*I*b5+p;^j>R$0Ci_xZkVYdX?jVc`mHYk!u0VN%U`oS$AP
zGU!wJroV-I_twly(JSd&>2&+81R-Ku`pc@7_Y+^U&e_LCD`PPuJF?qBmE_{@LR|3?
zWaD9r$p!;s(qEhyBU22G+PUNN0mz(dnz`m6fT)~fqt%?1m;g2Yowad!b_){zXGw${
zAWFw8M3n}})e*yV5v;wO`o+O!s8=7m&l(1PX{~J)Vq80_r$hVHbFGCw&M33n3(dF>
zg-A#ggt&^<{FCVm3e;w6qAeYbmDBeo4rZ`R-5<M_hzwTj!50^fuPkrQO)DfD#@oDS
z`dJY!>Q4~^Evb4u>K>0$<b_`qU(Cguau<-lfE>`NZ=4Kx*J%4i^_1F~5Kk<4*UMlU
z3@3#=rWWy|V=L9j%D|!_;Mi<<%D?^0m+y;Hlfh5`6>1u;*IOADn?Q-FyXdvtg6mQ%
zl;(-~AR^u;E34kdguzVBME_S?qvTFA+O7kw;7+F>On<7MQwK8@>tSb`v&9mpCen>{
zsp_GCtX|8{Y43-Ls6hMDNAuT#$kEucyBc=f%Qea4mAafK^Zc)$cmzd!dgPbSo;2T0
zUF<$E>EG6^7;ZGctx48g!IINvB?X?nfulp?gIb)t$7(skV&T=6RE?!mXiSEu+rs)U
zkv9?y6jk^BEd{P8vQ~S!_}Q|F{;26APhf%G;kN3`l^*MTt*elDB-&boirZqfaZ96X
z1fYK4@E|vwVhVZ|@O?9cn2$C0A8H^RICp8-h+x)9QlRr4{5q){jWOjyDfp@814p*|
zYt#1t+nKwfk1%kS);V<|V!#NLX@m{$-{CGUm|wp-4peL_wBmE=m;TEa=?8*S?&@pq
zYHgM457w%6Bi9_)`*i5>W5&=ZHA9l6Z3~-GCi;PgI^;9}ZJgAQdF2Y@ymL`}*r+z{
zWLQ#kkO{2SLgY|3DU7YH{F}?AVA&|G#Ef^CrkCi!08mP_B@W;;SytNg9LTnTt_S0V
z>QE!74paW&l`r$Myi$LCa^C7`pPZr#L^bG4SZkIwxnzGWTOMP8bQxd~bi=#u71&Zk
zj!nI^=S!~sIN&y)6g1haNx*K^F7levl&XDjN_>+t=Vqg98fXNAvtACXU8KXeOx0S~
zzH6nRZP|3UsAt#GH$XcauaE#esMvTFF7%5t;tK9AlqdwW9zNnCSylPIp!=XmitZ>k
zL|t!>`gMPKWPtPb9R8)^7GIn`JvkLIyFN`^)KW3-5;&UotljTnNk3LhHFAXLMjRcd
zw9D{L_En0sz@G}gK8`PB+^uV|upI9w#`Mrh`wK^pl`2ek_j_Z*(+fkivGVObrnx>u
z_qLSmciygDQMXjOeO}wy-MOaDSvW8{f2ODg#R8(=%$9(B;up+1<s**-!b$;7JPj$t
zXHwo3EiaVg^eN}~3%zKd^VbKoPZ|ZPky)i`sjga&bt-`YfZiE#mXduukex$qof?H3
zHiq+ks|_u_F`Mv<*FVo233#hAMDyCVwzG(|{c%p(V8Y(#6eo;h*`egv5atArid?^R
z6}-43&R7T8zP4&EYD;j*+x3sNby~fn2<f-zt*aTv8`PHK7S#LwHnCye^ZC8ZT$AFa
zm`miS3-JQxkd4^zf*vjT(2wU95NM%3T)}gH_7)~w<M`AOvtX9Z_KRAk=Mnur<l6UI
zzpMzzmE$x!`bfnCokg8006YCY(dPg8kjZx84_>O>(%OP;ZEt8Q%(hXQ*6vmWT1D%*
z61riIw}Tt8Tkn0{90=oG_fgwzvvcNYJ(gCWLc6s67p+!k1cbxei^Nw3;bRD(7KZr?
zOVcz{?_l9L%j=<->Fp8r#nI2vkK4A>r0_(?fBJ8GM`lBZT(REXfL68kr~OmbMg72<
z1>c7$-Mp2OVGVa@C1-5%$_qNKde<qz+6w_a<Dz-%|NZY;dW;=F1hIk^w1xqG(`u)R
zhWA4%y4>d+?4!QP^Lej0rTvW&zR!GC!;n#%)3<Avsq9nRts?Ev4aUgt#r47?Jrp0M
zT!BNXj{4OUMTQh@*J(bnGlUjZt8gtLnvtxI5fH_|Tm0JDz&}iSqYwhX@yD6fIHMhy
zOCMOI(nXsm8m1%|5W&zUkv?fx86gME$0eAx4Db^A?-CC`Yuuzrr;NL97W`=8wbu|Z
zw8+(uGOf7ZEA3QeD5USBUZ3@<rJ%PdM@7&5H<3E0GJDdDL4iDM<A6E(J+1fbtweIt
ztS%t>qXOt<cZoa+NGcte6l(S#wplnro3S7=hjrKjV4W0dSI5n!I+vyFbL=Otn5a-w
zmI?iArEpjID{@AqY%@LNFlDs7`J;x<!yo2?u<f$v@kjpXcdV^iL2XvkqS{|;n(Hp=
zF5jAA?C&r1yJbM0(md#4z1Mul)NBg4_@cSg$<<d=H5_o&D#^gFWYjjN^?V}7eU9)}
zK4Tze+P|9S%QDH*TK@X9r2BTirlYM_=oFAFl$|F7-{<S8<Ch>dii;Rs%R1wZRElmc
zv={a%HVGYJW#6$`CRg%QuERL)`IMQBMLfjHKEi-A>4X1$q~$ywI>Xc7Arx0NmsFF+
z8Kw{U1gK-~7${u7(=;aOz$`Imk^ji6Z3I{)YQLwV(TQjzHl8?{&>2WA?q^2H7O{fm
zhF)gH5Mh<m3&BbVR*O0fWQ_KP){O(393307FJ0Pr&7TD8f)eWN2$&A0-04Z*uQQRU
z?vL~$Pxu<0JE)2=l)MC~)bdYpgV`8=>el^JFXMa6$!Ia3m}Z6=A-$Ge(h}kH{^EFn
zR_#RZkadYz8n~`E1x|p1yv}^`7VS*tC9RBlEQ;++87mST)AZyxb!A^Ai$1cq{mHjr
z@XgJq-M&SGfj=%t%?#<i^O~vmX7xy!azEEkQ^F*n=QjGr4T(^wWx66~)DD%!YjrO1
zo&{=SLoXm;rWt$D1G8q8CzCY2pjNlP^;Nb(eTXojnkuleAskO@C_na}j79*V*t@}%
zBU7Jn8H<yWV)KAnch?0E>(E}R-BzmYVxsNSD7|La4e-V8y=ne$5RPkXOZ~DnXb}`6
zDrjLlbUOZaTr%R6;)07{<UQS{bfJajV|gMGsEj?iXAX#W#YYo+Ef|kWrkbi_ypv|w
zx*czb@OzZ&L*Bmy8Q>0)qbL0w_DaJ67(DBIPTjJ*UXFhh@Kse;&9Y{^=4#q1=d`V$
z?`JFyabjt#tk`pd(!?V^tQ?8IUk7g`tmn(MEzvz%2Hd9m5p8c`N!yj?zp=MKuAgvH
z+o?m;sB*mHlXAg>DavKeQ7U{&qgIB~lD)`~OGU{ZqFP>VUS><&%Go$<Q@a#~rkR?;
z=NMs1JM*0^_@>Rl*KKztd&C0Y@WzUhx#KGY!=@wV&s?8@?pYuEk*;ek(;B#)a5+y*
zzxvlaS8GkP_hCiAC)&U1n-M_V6S+-J9%k3@*i5|quGHnKroPt}tEEx%Q7&ipXo*{T
zA~}(`p-(P32VpY$n}B1MhbsZ1(5rC<wn^{8JJSDzS$V9J3mvGAe!TvvRInJuHVF{w
z?RZV7JUxE_p?s#jJ3|j_L2oZvqn=xq1uu1*kZ{%YV<7DEsb#kHO!|NA{``Pz&taNo
zY-3+1pc>YTf_Em+u|)5&TZ_d(DXK|`PU$VDL-b4^q64anrHop=u<GAZsXgFc_b;Zw
zc3QyuMOc9v(s(!-;tNz&#G}gqtYAxsDsb=!r10V|M^3Kq&?I<dnZUz}T$-6BnlVlp
zp%fDf7tg<SUuUPSH8o+)%XdX)cjhf;l(%!pa+-2OCoX|=F%`+nLH~yIan`^6`Zs7~
zm|kNNi##%8PI2fuwDivOy-~_9_CN3cs#}0W@C2e9UIN85a0os`?ZrgB)~UU^_+S*e
zK6+V=TlI`{E-~1>`<%l3yqH9<+jSEaU~_{SoK7x<i=9heG*7K7V8XP{)p5Mi35Tx?
zSHrR6UvK2hft5IfJDLxQTYyqB2|5wsQaa}ntR<PSV%PdJ6l|b;rMDXOT$7i3$nfAq
zs8dt7wEtbkm&cjnG}~f@*9-~9VA6^yaZQh6NdlhB7BRlTBwKu7$B9Y?s8QAJF}LfN
z+v*w<a=&BRq`N~s$f4M$+A0;7#dA#y$3Ls11I+s$h-WJA261my9tH>O9h&qmycHNs
z469IZ;s534-i<3awK}a|FloQ07>-lzT*1!l{r2HX7G@`_mLDzUmq`c9aqqkk7l=So
z-~P>)WE~b$i20ec23s0sraa96_QM)mYw(BB3l3>0XB3xyg@n%=nO>HLFZM%?KB9KZ
zOsDoJHgKpIa16ZKwr<wLbg!keKXwpa<|5@w%g04(<hy6%Q+3?mo@Ko9d2XkuUEXA>
zPR^L1w~kcn6{lF?Dy%GH9eXx@*0{PDClK)DtntjendY}xyR>Jm$;(!DAMD4@N{ay5
zZ_z|BZv@_dlYMl4J7d1z-ulHpNT+Go+&=->Vp%4a=avR1!Qet)v<N-JGl^9eqL)#>
zLA&Eo-}XMw?BWI0^{Ku{p4lR3Z0q}p1VZh7+Z^j_<QQ9(1Lw)<M%~|#r%L@8OqEfO
zf-wOFVnK#>hd-JYk52DW_4rB^7fBxe11UiuA_R<{PbAH^q6hf(T${|!#O}y$EJN)-
zvkZvaewG%|yXGZd<`^fD5d{diOQ$%Ye(&?zgJ$cyvhIbG2JvR4TV1_aJXTN+F*K(e
z*)RC+M~!qm7vEj>Py1(kw6-#cQeAaj(ch2WYkfJ9eBVMyh|LP1<B7pvJBZGyCSkG)
zjh{)-rNiqbB7l$WsOhLj<sC)%<NL|xm*%RFZYW}}ntg~_=|DjT<a93fSP-S3Qhlyk
zix~>zmI+47izi0;%BqjDq@(wIe5SxC@&)qQt>3Da=Zrr$XkKTvVcw5##8;u25Y?ph
z2jB||)^n}ekS#Yg%Vq{Y#9T_*WqCb<BtM~}jn}p&x+b(@=E3(Z;R>uRMXkUGg*w-V
zpW&J=uOPs`N}0=66S4gEl^=E}@AVC;K#f5!Wt}**S*Z~k7>|3+<_=!Y9uw=EDIcLh
zCes<&NfhgZ_NcgU7s+aDbJdXO2f8#1@?)C6{XhQIo2(jQ{`R}tt1E5rp>ta6Dk_L^
z&BBhSwU913{Rq6lt@#p>TH*s+kF)RwrH;lV$s%nO$MSZ!j-Ih~O<U7N)0^0i;lB$l
zh!F$x*uACMSx%@xvxwQ)6`>Q(%Blr8U7&QT4UpFCuZlm&4Q$Q@s{?iXUnsm&L6>Fu
z^FRqpm`hAfE>YmyeY_8LEDl)<#G(KvO0VpTInaBl?FatY^f<@#Y=86-H6MZ-JQG>a
z7^S>d`?YK<W*jHnT*vT@90y>yQ60s^f{A?UtN8llMCvt41}$~aszejx+DUcP!UAH#
z`IV)^lnn*$0%1dTc0LsMWSx*M9)Gid7W6B~b!4Tc+v{y|)jDU%b*n4!_uYp?tK%~E
z%GeSs$1mz{reQ#rEH!Z3#^{sz#+!qcsxdMP#{0NCPQe6fL)Cic%q$Z=ug7KW3c;*x
zTU*Q@*I=JHo7z3;eftXu&FvkclD&i{C+e$#s~SVbQjdOgf$%xr!!lExn(trjE~k^L
z-TJ3EUOiyB9)W7)g=)6BIxsvShSt<2GKY_Sq9SEdne9~?m@=)GM-dqF;>QuclD%5~
z6k3Vz_9fq+NWpl{%&{7++d>!zRIz5Q$-EpB4IGkOKX}D5W7`|+SzZU(shP2N|C>$n
zcq@EuK0Y#Sg=t@px-84Zi2-^e(OPgZy+S>UzYQu$kM9|;Fj43T#fm6fq2CjoL=Vem
z^#t+n<L*qNbzJGCaw1}nMXJSlpT6CjSv1{YxC)5@Q>1G-*t>Z$1j_u;95SVH1IH_a
z(?R`%RnYhk;Q&Nt{Sw~h9AqXIEq?tJuc#|B*bk}($&;!!Q3MAAtDtsM{JBs0sek`T
zOB0F!1PSXk{8H;$$i$u~x{YcOI~gsV!*|>9zEbQ80+0AN=m{^O2;~2mf~R?PPQ|Z)
zjKmNj?*CN4vCNV>R-p1~vYq2EB4;LRuE-Pxo34@YqCjLOcy~C2P!HUV5Rr>PqKtU;
zoQ%=gE+d7r)<o*vl&@5DvJRDYD)LnJ-%wy?88gk6ouQS%fn~e|sLeRG!_$vD&4=9F
zEGILzS}SNQT0jDUw1W~0(6Y6da6YHe!;I#zRC_VUO))-UqO)B0SxrySt`=U)oO(KX
zP~FPt=F162lu+SBb>tnmUS0ABnIB-#svZ1fMqUJ!hSa}`zUp6WmShCRY9V};er;Fd
zpi>zBqwN$mpQNL+Jykp<U@pi<dlM|TWZ3VNAbd+UkQ0`vPtIPFQ!iwE?2}oN%bb?_
zZ8QR-hKG>JHGZwo)~ejHx=&BHW?ijt?3;|KV9>d6+^V+_vT4Qug0^cD53aEJ>6LUx
zdP~CW9Jf|gC9_4}s~3&&B(ewVQUKpgO<x^eIin5E;#{*%amyg0z()dAvZ08IT=ja)
z!H_eDUR;p!0=?8>ZC{))tWC|SDYP8c97uWWvd)meJjlPz6b$c&%nx8WJiqKU)f)mI
zy}v<SpEbYzy)V*X%XdLIn|2Qajc^Y%+J`ig78IHIvwzKYm;?CnSaHc;h5@f5bBXs}
zr&V}E&r-*vV_F(P_cm*%*2?mvMQeiS0lKM2SeeoYg22BDqeR(=rjPtGOdIP167NDk
z848U_fms2Ey)+7llFMJuuL7l#i}<q7rVwFGUDOy@+@%s4Bfzw>MOlx=#Nw!(YcIW3
z-3)09cM8o`Wor7Z^v{0W3|z(Dc-~ZOxYl~O8Ks`qS!WG^>&j--K5akgjPu<;He9LZ
zHz2~YI|X3-lD6)znw4|k&7^2+fG&4tScJ9zV?}aHp10glHC7s3Xa=nbrq*5Zq$G6U
zZy#=1L!K9#RN<D0=Y_~K$+6;ZNS9cx<@@HeI>0cJe8w-6@Ak}hvkO2^pq84Pq+0$f
z``+ZvO4;ehbbgq*?rG4D_Em}!MyEmA-uUL1pmoSR#;Y}aND)JZffA|C04(v9IeLs~
zMc3iX>DkSUovipBGH)SB*Lp3j-e9=oV{MiBnFBs{G?|YQ*jy%#sDEee%!a78-<so$
zUJrcjAL8<r%e$EY1TZ^EG}uE9W<5n9u(_X?Y~QbLCYEU;<)5Kk{CIlFG&2V%jm7lC
zN>C|Dy0J;e?7+zNM}piR0M6L+@y|rveCyxu!CK~m(L24$Aeh!BHGrWEx((hx#q%)-
zP}t}n?i!_P8qAx0aCS59XUuPJ(FwS#+Pt-uB$!={o=Z5{zCz`zda4(5w$fV*1DlC9
zL_j^5qTK)$Cug1lRiqDA@?)^yWjbICCmqkFAsb*Boyb*A`|Wqk6jtskl1bdrGdBG=
zp7iIFfGJ+tmimpD>^<(55frE}$M??1KWs7WvLC!&sBO`LHi+}I)&}3RzoHB=n9vGk
zYOxbJuIx>piMGbfx(ni?o7>tLQ~TJQ*ENexf0K6r8$L#GoZhA$08qk)u$qN#Up8f8
zM#g)=DS;Zy(91gSfbW+6&}-sz1z=A&SBwmtW!9EcK1F&By23jq>lqd51f3kU{<OG}
zB!>ek&<3wz_N?K3K)Q$N{>8xO_!k`epQ*KuYi1a_wY3)QbPGgd@O;Z{9ZHrraBONG
z6Q!r=@lB;@k)yXd+YT&g{4VXDtxWFR3u3I)PCYsS9|yP%t&Zc0lq5c<H~^oQ3@}Av
zR7n2d!jL?S(TRDZ3&pPo^<~q<qUMqYX(lvAYATaD5FyXwTCHjp5yv`|J(3hqY$M6#
z*@3_SYy1L<-oN!He+@)u9HIrSndhepuT{&M$pT=a3IbzB5szwP#-`rl3uR|mMu7d(
z?$t$u@9AvYcAw2f)8u(g^<<pO(R<=Wb+1z3`a~AcqRE9k8yEfR>qsFx44#1kj5|&T
z_NGQdB=12Wr3kzpI87r5-){VkNkTb=7ey+00fVA9)4O!mxlTqpvy9N$yJQEdBvgCs
z(aiy@!daHpA98=@YrNmox3@OeWASMX8|U+6yzQFnrgfUhzCvc7bCmnQ?<9Q{lcUSh
z=?pMo?frCv$}&3IK4QJLrN`#*wCvf(V_-JB&6ZY@jB+BVHdlwQ`d4e1Y~ivdzA>P{
z;FKWW!s?fmjjq=dn<5aa<wp_cyVXyaTALj=7~3KqU?*NPO$H4*U(wA2k;FL*n6K0?
zedNdw27?^qu}4h6zQ;GJASqh@?{8x)sS4B2np7*?acJai8m+`m^kzr({e|vh$NE%`
zYN7c3+@mq^>KvX$M-YxR^JX+4m{<QE2~>O$%Mc)o^aJUKF2i3Z-{*RePqN4D1!#Iq
zee!{1M?R#alQ#h@cS08JmUfcv7~}%9kJ+^sk%HA_?GvyoYp<omV}Ax}C}J;{o!>D>
zJGsZ&vDTkKMyHo<(m_F+`jmuf!(LeLNd5DbKYlL`1?IZp*8pE#e^IZC%#oc*iL}eC
z1qUEo3>Ln^v8fO8ZBQDp+>^Q>Xdl<+K*-={wJn5Qd=2&}w>ukA%J%1~199`Zw<v}z
zg5^u`0#?etH(7eV(MWRR-CR=$E%5P43PayJ3`t^;yE&3P#7TyDEo`Kybtqj}gWMTO
z^{si*g8@$ueIEp>H0$D<l$MKvPfSPZ8~M*KGZe&Z-D&2IYTMc<ib*BWvN9;i_Y(lz
zs7K(ZU$7`dTsL=ZC2i!ML*ub}VNtu&h99gIUt-7h4s<6^Be}TO>eV-mIztU?7P<Nq
zFi22^IMq?H`_!;X*7Wg%lpv{|s&e=*s~&;|Z-BDa02y;H^iZ`<PR^yfto20Mq6kBW
z+WTw3&O_E91acFsqPL7G`4QvUI4e7*Z)ICioEd}-GhgtlPqb~55yTj*q*E6)U`BbZ
zXfJHnVfEJ}ZO=3w|Nmgbu{2&W&!&TIXjUmkU&-uVS68|-mi@4`|5aP#h)JRN7R>=y
zXSOgPra~0Qa4Z3WGhPJG0sK-KOpYO3A}~Ffs{V0rJOHLj$7i*akIBrbNt(#L301f3
zgl-kRJ<K*E%(ipGH$a{O7lN$44wysbaBJIlo<+EXivtcmX)Ip3{RG#==xU}QV;}S@
z`!}^hlEO4O!(C2smT9&62Z~xvob|WywVj^4{}y5ehN`~|z1)5>Q-B8FWwi=C4ijp*
zy~lrp*fq#)h6KLJm04kP=V@OkBU%tSX`mM2kfPY_mn>fy8@>@Vs^+zP&B&dP`=^l5
zMGk;gWc2$h>i)|XxZ7TseRnTvn9<R}Un>VAsCfPpZ`DKP6@>ozPnrg}nmF*1@?NE(
zG+*JFR#9|6R7fOvtUl@Wb2;IDv&A1cm~S8q2xjW=78HD9Li5Zy?X`<(tL?I7UC~y%
zp;rmbx;g|HD+CGtKQF?kQ21eez)*n?1QTm!7L`FLsgnt6wv7*l2o{)va=y}pQ3tvM
zl(Z)IQc9yKR&YRqG4XSNQ-Zoj9kIt^O;A9?!9vONg>a&X>=C0_R-mt){?g%cog*C^
zrsAKbFpbx>xOPX6-mCSJ_lDeY#B5pSpHM~x%cvs_wqEopYQDC%+YhR@*(??5y4?MK
zG*-i-Y>VDaBU`eNpK?NnCNBkS^!khn<ENS=8{ZFnrahe7B2*#^Zu~^A*-yp+Dt~5q
zAV0ivH61@h@p2dcE(1&GDej%j)xyq25|CoKQub*b?X9S<DGN#ejEG8{reb*fnJ;>|
zPp0Lo!@tI;{=98m@IJQR)peWXDUNbEYNlkaU2jLvc9ki4!j8_tJzc|fL+weuvZ!5F
z^U(u0P@pCf?sx*rCQDg=k+gb;l0kViKvV1e#MKWGbAgKKgC&8+Dt~w){%~$u)@dR^
zf4vcS%h&R#uH6|3LB_cKE~VtifnVBCt(JGhM*71zWH#5{Ulj34fEJ3dB#`Cw?N8fV
z@Rknn7Uo}nUfaMgAo<48?_ovO=N7t4tr5l?xV=NnmlEBX`=gT$#~0hyv@04gcJzjI
zC!-(K6yNvMWd((itytWO(ha|Q+zTy_%$lGiOj8V#Lv<|7m`4V`AQ)I2;eHx}Y+141
znaEbkFAsa98_XcV`+e&k41c=x$#WL&G+j$c>)E8y<WN^0N9+U|4FN3GB{2py)%%gd
znAEk`HRJr7A|!H_X!ad$jjKh{AtH`5WHo#W0aS=O_Y7kb=GY!#d&O31jLXPOAJGnK
z<-~oW@`ILpILY(`@ocQ0+EQXDui-Q(5vV14gK(&mIkr&9<FJtaIKs`<q9=961!g1r
z6y^79#h;zegfJcNRFl+}*1+W?y9T6;tJ~EkP8JPyqYqs+c-W`^@$<_;O`tbkdf`Gf
zO!^<hSsKt)5AD~H@{SeftHsG&v-dJ<SKM}VaA%pzY^!y)&nFn>uqwJbXyKRRtUf)V
zzNwHWj>666@Fm5A%J=IzlNLUtx6ssS`lJ+<$cu(XX}Ey*fs$QMCJJ4-LRcv5u)sdf
ziP4gktW>-{tYk*HLe@=U&Oo&}x6ja_+QJ8)X+A=V<h7!g4EOpqt#>Umu0O3>dA+1R
z$N-xrKvngTyz5qxfHMa6p4tKovprhTqHEg6iSA5C_amyihyZb*XzZ;p{|gnLJKoi(
z`*nue!jv8@c}P0SVYpnm))f~k0!dI~Xz`lpcyiu8qb`G3=IlhuoSwIKT-GO*&p;@V
z{8=00tEB6p>*)eDqxJuD!v-E7XNC5ycmDi7`pdwal7)5wO``n6mmgbGkVLKv|EFA6
z`qCc+p6geebT0mkTGuk>=}GXr4wYQA=$FT%S9k@84=2=k(h_JDpLYk322=_xn3^_m
z899yj@Tsu<haZEZ=qG8V<3rghYoqe4CjSX0Bm_(5)>Cilh+M;1Bk+@QUQ{e-i_5-)
zhh&}Bs&70Fq2I3kzUvHbz1){DG8VH<A2j2{qt@~0Z9U44uZRkbfhQolQ_IJH<Fh&(
zRg>hfDYRp?&aPK_*x*1LO4$@&%&Z|F-(`_A+(U#LX4jmNX}jLY(I4&;zgC(ON$Sl$
z=)*>9<q#Y;fhmF|@{3%)ThB93!6l};Sdn@UQuwsh9%dzl>WX-M1l5v<bWnyZyytNs
zknhq=J)UHtC}k|~0BN3S$gp~AArV{E!gN*^)ANT0M}@=Hk7Ek&&4!<izs2XjUYlrR
zbXAU$4pq1NQ~g#nz1>=3Brvg*gcnAN6Uh~CEMS_9_^G=2h%|@KKsam|T1wfAN=gDz
zwuOQOI#tGz8g3mGg9y=of<yQ({VYi8fv}muCh9ht?JQZ`nXqJI2)n+#5<M~c>joH_
zVe~Qf$*Q99PyQACPaL^io@KR#8iJHXE&Mw)Dd@g3A$HO1mouE@r8vWHNkj_JzkL8K
z0LFdNT%B1`UES&U9ocrc7f(MYdz;C*<RLv#VOe1R(Dw&Fb6d=717Vlnd7reoW=lqw
zDVPwagu9Foi}Tb78XpA(Mt*DY02zcR`6HpOa^hb6%8Nj!N&B2dl;&elAu<1to6t;|
z5(}LmyJLU<jsMj0f5LUAn6fCqBZjdp+Q||nq!U0Vv67P`^*f&4U&N=t{eTO=J27>h
zbZz=d=c@Lp&eYufN3DY>!;6`RiY{(&c8(GI(hCdlPF2Iq=SO|6Y!HJ#CFY!Bp_4Qr
zS!!2ls$9<Bi_Q>6hnu}R7%L;+)AuBsGhGU!({mY8`>7?iQA{$->N=&RI(mcQJa|@(
zkcvwmcl4I~4{sYTvu{0StogJrXGJ>jwD!<yl-k8s`_Z&k2FX=JNfoLZ7t9ZhLv@M2
z&Du-n)@Dxjtn1_HnwIK-oXD<2%=3k51)8bIC8u3C`RfMEo4htMuT%pt!tLNYrnKw)
z@QS>PA?|wb$N<gARpT(?)4M_(Uw=0>Ifws2csD?!y}Ouw9K?t?$qaY{$ZDD8$8%Z^
z=2zOAAN~Fdj0uU{r>*r{+Rtk>2~S(Kr!>5sj#3pKJ;_QPk2{|2&Gs9#;ImKpA95_t
zXs=#>ZLM~)XI!ZzbnlO7+nDydY%R$FUgz(NWp$%?smk(iAX<UiiGWDAq}>w>Tb&N1
z<8EgNFz*ykNaa3sV}U%x2tY94yPmMw%p=b0Q&vO=TU*Mo8IsBF6A60nUh^xZt5tyM
zYqNq&qbX*~QAf{@{==8_BZezvv$>`As@#tl;>ZV-f%ie0i37*|s*xToOMM5@?h@-7
z?je`A*j{goHTQg%-XL>O6<C?A_M$BQUBc?pw|GFjw!eT;*X99f_2My9m=vI47Hlht
zZ{y^G@r|;hk}FvbNKJWc<S!lOY4W*i)8n#)2GS2Y;v8CrH(6yUQQh2aMV^wf1EVTR
z!MCb3Qw(BVXM;Rz1H`-zo!amJ=C4}V5jd^CUIw;l7SL&@0!m4w_s3ep-Y6GLEquWZ
zK3Yl3_8KBy^;>OeGs%Lg9^mtxnf*1E&^&Z5vEMH`l(o1zzJNa?dxwD+sX8f$fS1Em
zwj#Vc1;s$J&JEFX^k<8o(clf#8$Q#CFt}mg4{+YIdJ>k8fc-M<#vZ$G-a15h<2)|s
z`!RS}{v@vo9vI36j>u{MM}O7)KH7D1;M5}h2DtCIrYI3;2YON6#R^Y51UpLENgH|s
ziECfk6?2@p=4U$Ld$d-qp4r>I7=4=ZJW0#3yXbDoK3%kWVVQ%L&DDY3+H)HUO-l6G
zw2*PJ8z3lD=)4ZL4^lsIwvO+%p&+XsCHJU5rQGR^$!?7|6OUL}DcU<NOL-|pTi$Ow
z1KB47!1Svhnox4@^9?b(czgJN*-;1%hXMc7n${-3Vof_ptN=c-*{{tgHjbf{TrpW?
z?J{N7hjFAlF1`~$-`C9>lNmbU-c_~UUC_S_pannrAZpd6q#{6oKMk(94K|}9KMQzv
zA1g%BNZswvNostsEU=00HKEH4A6|@uQ2FJ_`|yyQoX0Ye^(Lv&<Rz<*&3?+QJ2Lb?
zJpF;|#jj1f2zDO-?H6AXsFPC1XCYbZ6JS5v>HWqDo`{9_QNS9bgF+Caom<A@KX<+1
zBmU%hv8_9)t)#bV_b;*-bQ|QuR@Hsdf{5E*p(a#B(!o@9NB~6^6dm?~n5JZd9q=Ec
zZ4%Z0|6WN@Mz|<1aObLwdD2|CACe4M(U3Sjsk1b-XLpvm5ba~{3lkPG+TqD*`rAhu
zoJbZS42X&dRD0^y&yr~GmXZ3r41gZxb?}$jEOKBPv}BC&A{d@Fv&2yG_&O|->A?%|
zN)dFmT1VQ3rZ0AHL%W2GbB|5!YY!ray5S@F4my~r;vL`!B?B}-?f@l%UqvWG$Y)~)
zL+!(lE|26PMK=;N+e2i&HE~hx@FR?OWHG7W*OtVeDZZ)hHC*}#aIPu*Bp9Ch_8z>1
znVna{8@{@Vc)L|z1U`p!6#Li;qVI!s1DWtpcHLlM>B#I6v%|pZ4a!+F&Zf3K$eQ!C
zP@(OsiIY(6YPWScvE=Nn$Y(5C{z5+iHz${yZr2pI;~4ayxg$(HG9i7@#?KsW1(}><
z`?oFlFTBjSiG=kT=5)Jwcav7lN}vu_OY%bQB^M&Z9qRX7S9w+5OH+s8^4RDmI#U1j
z!rN>Nk!3?PNUxL9H$-><S5hbzm>4W7Esc<bn$==m;mANWKhhwnxuk;*^YwJ<Z0957
zk1cxqa`cK$l>S)DV8^>;VcrNnWeinrI>S~q-{e<~5*eL`3X_5v&rRzICEXq*82Q7Z
z*{9nWnk9-Z5A=Y3Qk=|k3)L&;0n5VQswRQ=oNQn0%-D}tXxpG^nH6VefZ^GT2Acti
zT1S5T(LlILD`uSK3vY`u&&uE*sBa%yDB~EZ!=kNmhS1gLtMNFTh76s4M$J#v&z{5Q
zQ~#63#1ONfYL_my?)R$Xr&cj*{128j)*mZb%f&}!=oX`u*G*3>38^QfgB4GfMIlDO
zvnaRZ<y4&GwoMyOWoza?2}m}xcmNQ(qN%RP0qI^-z@+Dp5w(a^b~#_X>N5WFr!Gxg
z**Aap?SK8z08A(MM!AO%|Gh>DA+V%cRRyZxC^x3CzmyzAhWO;9Uk|7@^Ik&=n(8yP
zH)>0!jN44EX%Xj+mWZEAB-paI$KL-OO113ZB}G8Z*Q@69#;EUtn`z*Fl$qQJwef=v
zoYw-p2qw2@;VUHog6XqH{c0fq?bcKGrzYoBm(T2{JVyf0XV>{N>7{bGj#Tv$4K;P>
zA(sRqN2_Q1FPfN^q#g>+vy!mQ{1e2eF_$H!Wf;+Jt=Bt7Q_YjaN-wGgfR7Bd0jWy$
zgm@9}3su(R>pB30#lC7#k%z5q40N?lBxFcWHGcKzlhS8YujgIHn|(@bT9H$WIxrkR
z*d?iGk~}~mVNuQ+hg`rUbSFSpvj2p8b5Zr|Rf+H(bgH|o#9B6EGw(8{_j|?wY(x_?
zT^LWw<^cJJG5`O%_A<&!N*BKFCoWVGJ8A_+SkowET^vHy{t|Pn{i>yZXmZY{(ZgIZ
zIOMmyYr@jCB~$Oy9Kr|Re?z;INH`P9jaKw;(T?exkOe*}CljdeD!3StjEfqeA=EN=
z8!Lf*M@jKikwtr<W28ZLJPWPzlmJ4sS7eop-hv}{Bta?Huyd?515@Z)2D2OSz{OVs
z;aJ=K+mrvy<ww*Vo-O;(qQR?z@^omFv3iT1jTH{jG7vf#;b9lHH<dPASpISI@H6`N
zFxF+1?P>kNvc4_xKw1szj0`~&NQ82OxrIp3zzx(hF&=~>Va^tNcT-_EcNc_r;M{Ue
z;^x(k)()M2Jk~InlJA|qF^M6Gnd<4ZATaSgu~et{qgxRP;b4>$ThpA4#W-P^iV5Hd
z#O}ZRaqc<L(d(dZXF+^x-!oq$xiBN7?$cW7b_*23t%7s%;i@1p%{~B2fbn1frf!Rt
z9M*acq}4XaR2@S%YAzH|8LbcgjZ%bt=;la(j)OOi#x4y4|0W2wwNq`h>!bK^$WC`W
zsIc)Gfoxt8S$D$}Rob(u)MYbbePk7_9-D);6Y0dh<ROcFqbU3#vad2#j#3n9y+LfC
z0DMdP#eWWq-~xHaX`d$Xdu_ayjl+c^nu`yI^<3`Q*BlXbWmRw!lw&yW_VMIkM8rLk
z(RNIWR+-Hs$-^dE@r?C=o;pTv+5}bL-t65>RmUrrVXP@Pr2(J3N5d=5Uw8A1N0bC1
zQss3A8+F!IQQWeH9aQ1Ho|$=lCV`09LIZq}A!+fZUc<TLX`a8|7z%zh{7e8Q?^Zt}
zaYDC?<_5&~%N?w85f6Y3k*o2N=DHZ-$hs(<#Z5HWdOuXr4fYRkKRsM)<9Tkt7HuY5
z)8galdb%xpQsilgbHEUGX}hI^FL-g@XT1R@a#&^<X2W__27^FS(Abe#xVKz-Z;%RS
z0Np@PWoOlOik8`WD!|Ip>IwDiN~CsK>RwPi4?zn~F9dc()AGEJ`)+=kPoMhdpM36!
zAq8YL6|P>tFwW6pGP$mA7aXV%bx7S2u;fu_H>a2<bd|1(t!L1?u9eTdaqfmz)IhyY
zW|pk(A~sSFWVGBkwhE(TLz7&~fQ&i~MoVa{rm(mN%fj`1Nw;mFCH~N%6JtfZupHUz
zI$IsN%5aZMRLD;k*{*yhYNeP}w`@IWMRuRFJ)2)YxKwwjaUiz<=>s5Ow99l?Kl#EL
zKDS(8WNCOO&1hJ90tjVqYkE4(Jvo{i^i+$~NLf@pj4Wb>S_dBBJLu3}sVmG+(~NyG
zlw40FwAJ(kjqkBS%2T$24#@&m1RpXuH_knjxf31;jeWQik3zXAqb{F~#<zIWZVWc6
z-Y0o2--DGW8oPUVZN85meR%ggHFYHms@0Sm8tonaA(5xfAmD)TMs)A`jQjhMcUrDu
zjKFQYKFz|v>y$lOJ60*IA=I{{#i8uz(PPIB!4C6B<VKQ>Wu!)>M#GE2i);DSw!YL-
zI+bMRKC?&fcB5szH9Da*3LKXtR(z`p0VXmOCdKa>XcK=WiSf6r(>8R7Unbx$;RN2T
z_-j_yK+sXpO5ebde@U+K#(&9P73R*O{LV*+X{RFg=n>l{LFP&)oMGE}l6=H2?nQ=b
zBp{2Y@fmIJ2cI|DSA1Pg9wXV*$J@*efCB81-Hg;@04;qS>#>cWxze8M5P<hp-n2|4
z{yAU^pZ7aj>k6Oxz%8X=a=9;_Nk~oBsx8XB0fAf)uejM>!^BPBYz_i3$E0DG-s@k2
z+D3XAwHcL_@p;@}4*5UZI6DF$B$$N8g1UzuVTZ*e*<*B*6tFf>@L-TL23F8n5BQ5r
zCX;Ta@0?GB4!Qo6)~tQUuf0LZT+obN8idalfG_mJ_#=orf>+L!f`y?5K%`VnJQ7-s
zAU>h30&NJGx2~^RWnE8`{AJYE{-}~|LJlqK&+;SrftuNSfu1i2O)2TZ#4rUBYt}1E
zSOfbiO*&1v{ATa4YrJmGgg=^|yxfDbYsZa*TTw~yyM&(Qa}@1S>Rl5QJ|4$Q+yj3!
zd#``L`LLgk(;Ll>YdtLW#^E8pj{Mn(J*^qWKIf~Y9H*iL=f&Rnfx5eVtx=$RNXLD2
zVC+E&&s;IHw^X`kXF_dP^9gIexOcy2Cqa6-=a<B_8{d!>U8;WC(14lokd1T@{7zyS
z^*$ZgSp3PQpx5vo641y5HW69w3=fg&`c&Q19!XIjW9H^1K>~Q#VOkxNXBY@-aT<BJ
zs-D`j=ui5PM#OGu^uw&}4aZ2!Ok|I1a(A@WW5@VBW89t6Xx*Wvtnw<zyM{OI{#>*A
zE~L8%W2(E7ZjENB!k)DX1x!q{y)^b_a|;%>BKwxJOnn7}N3Ac(5}GPBn56)hYJY4f
zxuCaGfG$G_vhGAc_9>-_{|I)F33t+ps6*L%lL|N^>#}sD+LRl?spL81p*SgjiWpXp
z4SJ$K(OK3Oz5A2aJ`IMcXZ!ki8*-xfyZT)R7GR_yKcTCS0OBzbssYBQYFdw#Hn*e?
zS~T?5nkp8`s<+9>wm;fb-F()d*Sq@^oGCt?LIL?NojrK92hBF}f`b*pNN}}=YUr@f
zk8n>4wmQ4S&XCko7Dw6|l$$y@S?BXFziym0L<=H-uKC;TETccf7Zos`yUo-BeFsA#
zHJ$a*pc1WL#Ukzm7s6wJg|JTq<67jdd9p8rT>lc6Vo5Qgi6Q%`2~6oKnVmXG(&}5b
zZ6-Qz)<IHPIX<(R$59jjVM>+#&<-VHXI4#aq((ry6U_fQGMC#lvxwlvXaSG8+;cAF
zTY4sQzcrUgbxmf^+aw0!sZt9R_Gkm~P{uHl5`yx4_RfDuhdd0hp7Ey&{woFlHBIx&
zq8tfJ^Vr&_g_(5MBQ4D>%{#PbxboZ2oom}s)~sELWC1nGy-M4{<}6D?17rsPd)4N8
z-4C%Ln!prd+T`w!L13-osBPmx#%wId+YN=@v_h~@G+a9(eAlD)AZ2k!_Q_dtpT|4-
zNI<d~v5Nk?S6Xh?g~yp<W`H*DLfaHXjk^x`SBNt9!=%|!&EPK!s#re2g+S=G1Nouu
zx_;qCG=m6Kp@*=XbJ2rZgxv(&lE?O`J_<0~RzVdG0g)i}w@=O2Vj^qcGs`>{v38@D
zs+1Mlx0WW9C!tg*gazmB2!(oQ*6=1U?gnzW(Yp~e@I;gWH$G{=W`%FCI7%8oYJ}mL
zR`bD)gFX(u*g6r_HO=j7EoFOS*?32BrFZi{m@*sK{0z$eDigc~Ejg#}%Ir*cWFCe@
zOK(#n*|Md|6!jx727wQh`#R@uCOiw?7i*@0WxVh1506w$H?Egnm_w*5h(x~Z&QhBI
zl~@>@sin**`PONYMkzz-MoNF_Y;3u>wo>D0h;~>86neh#;1}L6c+y*NWrtCUO@-US
z50<qD==!3qv`MX{q*FrM*w1{1fn5z0G&KC|B14h0OX~Ewp6E$6mytP>%=YvW#d%^&
zwsjx7_CmShB>he!K)k^lrcV}rjB!!^5&4BJ3*QO)eEp-B{D4ynJKa||r#60`QOOJV
z4<x44D>{#4TYHj+WfljR3uNA>qUOH&5SS=KR%L(eoul0^o4G%gjQ{{lC_Y}RQ96xB
zBM&GnNs731OAgD95ur<?>k9+){G7q}*XxC#mjR%d_HO4=dMocBal>-;i-gUcA}LvQ
zIYOg@FZ}BG^q^ObU&~W=#Hk+cZa5G`c!N05O~Dhv#yI1014dp%7&Mz3#?)I}&o+d{
zQZMvOeLDFHzvW`o%$Sc@*6s=(w%$NRE(Z<p@Dgch;B{074B%6sNre8!KZX56oCOo;
z=K|x309BkEh&JV%lzbonjXQ?#98>uHE?^#OY6wa$b_O`rxwkqyg_YCe^$hE&_D@;G
z^!~cil0_@zEqo!=dwm7i1FVP^Kr$7tNI>^p{38O@yJ*(Ndve_d<7OjQ>(%S%en?e3
zkNoE)A1x`dX&$A-#WWDhWr4x;HP)>qdAo$irh0>>o=R$f-)Hpkd%&kCz&_jllq-f+
z>%InO5uDX@M%LJ7OU<Hqcd=t-ceFfO9%PRoOUpb_*E8n9G4;QvML#7YkRKo9*r`m$
zYJCN;LDR?WVnsoUy=b$avFR$Py~$mr%G3Rg3La)e{Kv&jPXc#;_Q~CsXu1bBM)G+q
z01)}fv_gVkiph05MmS__)i+_;!fqiHC_cl}1k1sqvFa(%Jc`~ozROlWae);L*y-9?
z?UmJ;8ZxsDLV8hOC3DN%V#FQfa8QPIE$9QL7vCpZU%qjf)XHq1yxe&Quyt#<>?6S8
z+KLvngZPmDYpX!H4YxMdfo)bUZ+g$T_c12H2PK$IfyyVuzn@wPT_Y&D!}Lzh*vv^{
zhFn$v-6zk~@>U|Ho0uKODwd5upxsp*JyaRZp<5xaEu-L=CE4Ne1O_bgHwS<8c}i;W
zXOMTS$#V26t5;#o`R4((moFbfQFg}=nOU<CV()jh84jf#Jyi9xTD?=-K3Oyom`0Ck
zINfVkun@?eV^<am^FfQzkLfuUf>KbyvlEp?`s@2d<c%MAQ&jFEC}R};;1Er@0B?-0
zNXWu1PlXbfE&izf=aLy))WOObK?9LvhlmFRf>-oh`tiT{+~Y3Ueg~uDL;?X3ws599
zG+R{HmeyL@>3~ezPI0$W%nRmlHqJ364xZKEc;2P-*w{HxPP}Z{_hM4Bmbk2n79ZUn
z8&2JHNhw!BF)?an@Q}Aagyv|Ow1pd+6r`rzs0=)m3(vsN(&1b~`Uhztp|%d9rTFFd
zPp*RlI~c>;T-+uqiH-G*ELaAb83>1F-QRz0y=5Qq;FmCaI2t}t6S15)x-JrMV<+{#
zg1*lK3&Q`-Dp#{+lN(Ur>!!cmr}&sGV81I5QdSRZokjH^<)GbG+}Uenv+c(#fe*NG
z*60;~1$h#58g#aQFfrurQ=vJsab;|?mtz3qf+02>R9b$wh&H>dKI>z&S4AtiW)b?D
zo-Wd&)2<-WULGDei<zycwJ?Zn{?Xqx|HPF|)O=Zm+IKW0a>TG`A<<b#Xc~1X9A#GI
z2n%{KKbQ~s&{RPSJ%}N46YRQmt-DACosEEJB+2M4!(D!_(LAFu(M4ViPK9OB;lv*R
zcu=*XZM%HtW?EjafxYW$AdP#=Taa*elF{3Zz_vR}`(EVIU_Ah7;`ub9s9d-K`nP}n
zB^;;N{#euar2HJr@GpAn(I}<gxXKl+u?S12h_~_&zc8#Bz2Q@c1kz4l1fiE@w;ZQu
zmLEd7-9064GlxWAoO@-gMWQP$73jf6&7EA>R3$4lE$=hlHaAX6&mMD%skY2sE1lV`
zSd5aflF!-aZGIOdMm9vO_Zl1y#Fb%v$M|>d@hNRg^NBXTUrp1}gNkVhW8XdlFA>By
zHv1d75+T;|@c-pU6tHh!OEz0jEfInynmnoJdh`5fmby+pAZe}NV_e-q!9r!{aS|Fv
z3^x{2$3)fYQfxrGVLeR~o5Uf6pBeiIf*pqf5a8RDuNG`F^t&hKLKK)LqIH)aVW(g@
zn#TBpdyK~!^+vrx%j<1IcMmv(-gx6jmS12G@@vAjt$MS3Cdvmu`Z^p1Z=7mqLym^&
z8PL>;T$36beiV!+H!vKaE+e-{D5FKN0zPKidW2t}&LmLh?96)q#&X9HbcwnS=I@#Z
zDvhOp`Mcl#0KpQm2o`OoriBc(p{z~A32Wm-4DdN;laf!`Yfvh3cwKltgW)cn5T9Um
zpv7{@P-q7)#Mh)|JLM7+A|d6Dfi?pxGQj69Gs)2W7!5@%g%!gE9+`)UMRt&vAi-ju
z)OLVYMzHP{yvH=&ss7vl@e54FQnsy5BmM@H!F+@K!X4UOfSW^2a5OQP977R89~~Qj
zsh|)*GmnZ%pQ*8i<dIZxpNgJS(e=b?ccO0`QEOtG-FMqcI=YO!ABPA*Zqo>!H5lB+
z{GP^#B3G(`jgml0&(WNR#fqZuaj{s+H~5wwGVV%PDFu3_?xX;`Hhy&m^D?A=$)zNS
zik$Mn8}%w%PQ1GB9jY@`0<y`ni}^5^4+2XTT!_sQl*6iI^)%KzKq-2(Z<DiWR5@OA
zwLL#zHt#6=z8}j!aiI&x9t|8-U(~MXi_tq8)?N=@#*UG!mV-U98w>d-^Et#ZpETU_
zMisd=(*V3yF<9b<oa{|DZ-a)0h?$FfX#Y$qXp;rF7Dt-tWD*s-3MI5XW*reg7{H~3
zBuoh4tA=|dzVWA~zWbY(xq?7CzVQZ;+25hy7zjmK2}aas+ELqX(TCXQV46(~M6Lq(
z@$NwEzNfxZo4JS}B+8noz4(89N&)Shw93W!ZR~T|x@+Z{7ubS8bHSoQiolj<_{Mu+
z8+R%vBN9dzK>_c%!t>O*YF^#*ro#SxtYDp2srJd+8LZ><(2g6~%QifL(FDW#n<~z%
z==nVNeGQwYTZzWYX5WUdRDrDt0fRBCJO(<a?ljpwS}3=ca$J6DpZJrL)scpzjQEth
zn}d58o84FCS2JLqiEdH*QJrQfvjy3c0t>z$%BzaiTz(x@Ry!0P#TZnaV2>ig+=wue
z;rVJ&MclkpeX@Z(VC8BJGH0V`W>TOhGfN$Y4gX~;+(RyQcqQ4Cw3_nhz?S@vYbdet
zA>z+%_itTr-!r^w-prd%_!8zc8{cX8#mv6vT91u64Bf-|&pJc!8uIf)qp?h88op5d
z$5iTU>Xpk%XDx9h(OT5mq(h<6>h(vI9nd{;f~bCLaaK3Ur;}xG(h0&a%HJ%|BlrXN
zq_>nTm&=qT^9x_0WD}N|c8giNyZ`BV$zL+r`fxGRKF3e(5rjn98&r6E@ZTrG4qs|`
z9x0Tuirgo&+O+#t`bXdTB92@%HvwsABPE3mr;-k}6rr?9=S`y=fn{&_YVd)-Xs9sA
z&d)DE<B2&l%-nY6)}pO?8cu$Y`Poe^dMV{Zq>lzH1g3STHEhP;)Wn08vsJ`LiW0d6
zKB6?~V6xMo!}ORJ#*T01V&V+y){7dY{+hK8hn>t=&syF)$)YFmzTZ{35m2pb%*<c9
z8#+>Nl*4{QxFGq5O;FcoHm-T>mb{yzsM7jGK2#_$(FbMhI<&M6_o{Z&#on6m(|SR*
zKF`S6x^_kD%O2J5P3&Wpp|{O)2eTjoUeGIBKdHa~Jm7ly7qSy?f}g;P$WMr=5V*9D
z5J1C(t)R|^5jh|$DWChErDy1X`bmH=dILHYk7U^6L3N1dD0xTXvKT_>Ea+iYUao&}
zIndrQ!_tT$J$aR<Kuv0QXrU14@|ZnZcA(XBSu7y)h9|2&9%Ipv$&Ty}70-^Vb^QiS
zlDkfqL%^b}Y&}>(#>+PQ>TwI>82C({#y}A(M@yG7^Ixh4-i`Eo%uRbup<uy_Lx(i#
zs2}A~W|mTSD`*}A5=K3qEutwPED*Nls-ohh)4`c0^t*pM{1ihj)2{hhjfDKf1tY43
zAJ%QWm<68Se>7T3GvY(?AGShnOMorwAwG!@q^03O@Y?MjI_2%m!)0P0CvIz)!>y&)
z(nT$v+4*$D$wtbA+Q5C;WRTw#f|wRbBrAM(Oe<h~LVV0dD8A+Tj}@(jVXJq9dw+pc
z{k~dc5A;j^Ih6gp`JKW@iV1x(lKeCKCKi!nAYwz6vV(}D-WXVnQ}PSuON)K^M9XHj
zJj0#5I?jmls|Ci!SrxF8D$>}0v;e)RxFk!q@<OM=a7DidHH`U}F<0u`n%N$`*sX8P
zSZ%PqdsNpAJ)_zP!aFTR<$;T9wK;(Ek}egf(LWX5v1*O$w>O3rK+c+4VhBE*;@925
z#xes@Iub3}iqM5P3AX4yJ+{OjwL4?=USo0!RB8-vfPfdGlY|(xkr(Pu`EQ)~Vu&CU
zqd0zIM%V<n1)DBBWII_mLII}&r`Z)_jk@WYK?k#Aw-sML>FU$y<@A+=bz4u6xprZ(
z3)g$Y%2*-AJDddJfalm~^Eae7Jz(o*h&U=*N+EuzVLi8HBr9{pO~gYWIYxseOffgs
z)6;%iheTYpl+VsL@sxK3z2;yIqQimqz3FP_S(NF|rGGRXeoWAC_}8%P4QU_OEjASh
zdsXCmGY$nda!ED#8_oKF_}(IMnVp<Z%V<hsUT@8Gi|lmC>RdwHzf(RxGU&j6+f>9`
zDiV$e-8`MC0!QM2kOL(X@E>~f8@Z7cqQM7czz<L)c*I)I0iQ|gxhR8trzUUPq<l#=
zUdzbW>s2nsb*Zod3_5&jq;LPvpZ6R5>3p-Vi!T(C?=8R)4{MMh;JrtmK33`<D`h#g
zqmWDRRbCb3;2nc~Nw1>}OCkP_9+*hqwzQ|15u^3Z6jgM>dQNEFY{YpqKajtQ+K3l1
z8%A@l>Qb!BhPOo>z}NN!i<Ap7zkFO$zW33}A|yJ=MjWK17-Kpy(_{8@3O=K=9`R2j
za*hB7hAMW80O-Nhb$8L=nqkCke&gDgrd%`5a>sG)TiO#oZ7@gbV~b*1qT;av4BUy_
z&<W8}KG|@=tkEa{@69N8we9J1XU(mu>z=N~?zK!EB?zx%tx{}l<Lsguie)!R&KwCa
z2I9pCPPM_PofgAuJtSN;Ee^dyHrwP%2e4fH4J2HZ38sg@j^x+#HFTKwvyn5c%XC#u
zXZo60e8Zv|B|$g2fR31$R^tz0CdJ<&4%zU1x9+ratkM`=pTUIyD#<WFvg^`MamKoj
z6~49+xr&oj26LGKtAA(?tk?Ofb$oU1AcvAAQgtnPONU(4>0C+n+b1TRYfl#$mL}$j
z8G%QQH0@2v?;~E)io$!)+M9w;@abGkmC)QgI?`ylD{S(8V(*?*2=jP_zeVJ23$3or
zCF!M-fAR;H20fy}vkYUwZp?&()b`Vnfx7vDfQV)rY;_y-$fD+EPewCQK~(m0xo8S2
zPXEY!LpmDpZg{QrjRML%!+!49uC!gzKGt4IxA%RlE+@_<w1b(oz6xvV=-K=GM_%AG
zu=y#^+LhI5VKZ1zFE*A_LcHDm5n}&bc4$<zx&u%oL2eoz0$*?6pPIa=SmHz|VGfDu
zTK=17K?Ao@rqL-Zj9gt7u6yN!)y8VTZ>yU<|9t0jNIm^i!Oh9h#tx8|vXSc7{Lx7*
zbt?E=Hb!Y3+L6iTXM*$j-uxw(PF#Q42wC}=rm3)*FqFDx?8Am)vgwSSZ)vtdddU6%
zsC)nLIF9p7u)5KdhK%A&)$|M-Lx}Dw^ni^aDPe{H4bgGb)#w2S5GBok05zgz8Gs3!
zQS4Zh#l-PtS5t!?5wJiDpvXi{oHGD|3hlLHi>91xl6wMBWF#lrGbu|6*L(X|WMrTB
z;+!d3$;#e5@x3*alFR09_m8{#;~K!spr^aKeth-gd%ySl%7OKu-Y^98Rt&Phw+6sb
z<|ObWbgz0tG)#D+LE94k9+S9Mc<*oB3?#}uu1ENgb;QD)iyUq`ByDbv>dfkTJo2r&
zRYuz7&GH+)ToBSU1K}BzCgZDN^tiyZx~I|RPK3dnNfw#s1ST?GHznyxKucalphn{0
zHi9%f62vA^t~L0R(f)bSY5HMEYVg1@=N)3#;l#?kY-62IWY`nAo)yViiv$UOUY6UB
z`JOXBQsE&%Y+f>aEJ`Lwat5V<f=*CKU9iYc7DaM6K`@!Z_JP@*bO{u>(dJ7x#G}26
zxc0ZN1f%63K~`b5z+w9&I2XDWM??nH1yY4Bn&cKG_1Gdwl!Fi@l5koqx~(S#W`HN*
zY(!!t165QP5w(n8Ns{(0$;7q4_z}*;u1VnMO<d0;+e3Ygz6a-9pNQSXO@IbB&f%26
z<*noG<dHTKzj2BrEqn+P@wNZ*L|}LH`!V*DKjSpS5-VoU(ML9g`2(4h_*33(zbp=T
zVRs}Vt-b)FiIZ?Y@G<%?*-q-O?By`^VSAI;ekLr2TRbo1o%SHSxGePGr+pRAYaWTF
z!Eq<AgfNBQh2mmTL{d>O8tX%?YPKV06Xu#&XiTE=abONf+TfPqX^A^u{n@wk{r~*!
z+I`h`5<%Mp<#%cXCu0JU!SPPTy>s0=@BdhP@0`%@*Iw_f)ARl}8Vg{PsDO?f1b)&y
zOU;dP6K@x<OoWf}Pl|s2nlMV)C^r1$<;;0MuAk-B(WrYZER$6k1^(-i8OEXQ$6;Me
zBV>Qqj5!O!t?zg04EpGY&}ue#(H1Veh>&Sh)rHZ?C%7jZeC-j(gM*i~YD?coRP~R)
zxPioe5+dp+J3?yK%|%AK>_$;+vxpmca>nvP71up8Djp#7)Q$)hB<_)2xRlh{jG;#W
zbTRU<hfdLjE?n^tcT{(cx|u{9LeOvl4hbKc1pDS+4>V{zQg)t@Y5~>IFgsBVy)@h?
zX-dGCM8&B_oC^O(PZ2+;*&;C8t=ZnN943u!&x*^tz4EXTCT-t>-h9lTRmZ$}zi#RZ
zz$>~!42OcIx#D=^-1kUePNUWdgG<sj!$)Mim|3WVdDg0gXs*$qMgLFcelFs!vaQvK
z%u6S%M;009u0;kD3xxDw$yGLEZ#uG?(p274)_?(dSS{DBLFq*Xgo6UVL^)^Bg*mLP
zx_h>v6N%WXH$v3Q<7T}r+3IG#PZ|K&$bZQIWm^}b3#Y8k-poBTFm~HvlMXpjBA%&=
zTM|YBZl!EHk+cR27z{&FrpX!jpGY2Av&Upo8mc9Q0X5=<<gjCUb4(m#u7N>jkuNf*
zHP~Q*g)ssR6#;X{=z8r3LrJS*L!<_*c^PgF@3K3Z(YoDsu-3jbDCx|jWx7@l2^qAl
zz>FU*7ZC9<Q%;17_Fy7TDXU!Wu#OKNFIP!9IU_7O3IlQjO`IGmJBeJ`G4nJlidbF}
z!9^aCfU$1l=q;E(v?Tbl0mqkyB#*shI6*8uV?I)H`Zt_-ZPw_xbc!47ZZ<$i*CGIW
zJ>}W3p<AN77MCwJ&e!TuB9sW=)@xVnua;!usEmdiBOUi}u`$eBS`xJ2sen-|7MJ*V
z=T4J#R{inNsW(2+oAAdQ9K*8}k1LnX2*aOu1Y@&d0!!<>QJ1H~YZtzUaW9%SFr3G(
z(QVjiVW@2gT%D}(7}J}?5KxaGfpfjIZYP{^N#uMqj<}q3E;fhFv_<?F?Xppi^qvn#
zhA!Wzh@{EjxI%jTz`{sBlORpzqtm(*jjn_oVlj=uwSDb>{uxFXroIsJ6PL-XfsV5l
zL87KD2xM80_jqvv$VbvgaiiqHD!Ss^gHa$YH%$0|#F5E8rU<mqxrnM^$Y90<Acd^^
z0(VWm_IE7_lLSx&YSD>YZpet(q-iA+cnFe60?BnF>XheDbb$DlsMvKgZ=q+SQ;^t6
zf(7Ozyln<-B+A7w)UQw)+`GGh5rGIr@KAiv#}9jNrqE@K3Gcu>!@lX6d6qN>49T5x
z&Ps+^hi%A3%#xJk>~+U^ATbREwi)Zr5+xhv9FlK0^&E^mpow|iM5Q2?cy1jTT@@s7
zAZ`Xnts{d{=iu7p>x6<oU?6C=#Y+&sP+_jMh$_3b5eAyxm@z>wI0e_fBoh{iIA6l7
z(lojpX>R8TnxjX4&mL!iL2}ff$Lq%N<c#5p1`mZvxJOhRyDXu)4a~Y&iL@qG`&zmS
zlI>LESOpeSPe=!7U#roW1ee;i_E=~k<OCfb869jjhL4h3y6%&qKB+&U5-_I5f}o5}
zj3rH-ny%?^gaxY06|Bvii^9lVFa57DWQ;1;pdtKJsX=Hmu@-PU(KJyln7_<`YKbwE
zI$<11EA5#i8HM2pZ;o(<NXbMXD`}I7G}5o9&~o)P4B1W`NrWPV>M5f=(uPAR>?p{%
z40=6G&O?v<(z_rqyl1f4P_~&oHi9V{Ip@3MN}lju=$=W0YVrcq6`miI+hh<TgonL>
zCn<Hf1=ebNRV58{bxtcPnM&9c|7ii}LPyrEsm$?4ouL>w>R1w>9)-O2`MXd#llBSo
zcrZv&Q2n!7KEJ}yZG&w2Sa~HdT?@@U6wXEmJw+mYzqdNvQ%-`_AmLzM?SU8(ZYSGl
zkg%PF<a!KHbyPS(*b7`+Ul3|%0)#^>l3Y__cz0g=p;6&=)Uc=5P_BV)ig#2f#EF``
z*OMqImUTGQi5e$l3*>y88P!ec*<3I4^a4V!-LP71!?iy5oS4J>#t2Tjh7@}Yw_y<S
zm8<XK*vq6>ViE|$z|sY%BMoa?gs~W_Xcr4)yF8C#B`Kx|J;jo!j`xV>EKWHM;QnKv
zGKotSH5?CJ5{r4)jGZXfm_WG_u6m9uEngs4e&nCuBI1wjcx>PLv`JI4A+d5L6}}o)
zcm>gFG4Oav3oYrDNr=|Ok+R5YsFy>55m*Bj@l**@bwXDGS`PJ(a*#SrD6E$mjGoEX
zuNN?MK|QG9#I>y-wpZKxF0<-#csP7&&(g<2FU*Z@nX8J2!=Jgk-5nLX7rGxE+>rZZ
z7(P9iyB{R*C<Ow#J!MYhM!RCZ)W;H)V%>_khMV%0d@#j^j`4}^my08Qsk*geq$r<b
zqn#J??2w?6u5tSF<~&%qcQhzw(C$>C-|wF`yQjm%cISx59BgovbH3l0SOSJoBn~`g
zoce;jhn~055f+*1u7=xlKYe+q%FkBQ{qmmnz0sk)y~6|1K<HV6O5T!ukxsuJ9~vI9
zPmWHj<0l^t`y+eM>m4i%*))1$)Tub#qm5*lLIypo^;O+c*q{1kc~kqSzgt_ryYKEy
zpX)qv4$HYTTjS{(qYFv;Jf)e`AqTqx@T7RTA&mLFTlF)SV?lpi)Z#5_puprT^{8N7
z%Pg2H+CmBkE3V&Q@RBkrMTB$NK9DLom%CQr&|d4hhhmprfrxR|xcYJ!2AA^|{ygiV
zxbYW#EDV#E!~r{bnR`}Px3-5Nl!}ma^h$!1EF?*$QkdQBxe)xc1<vu8=TiIF5JA9j
zGV)l10%`1pm?P>cKH0}X%$E2P3lf+{uv1Qve)$uttn?srcJmL~Z%TR5dm{?(gw>dT
zB-~n>9k?Fu=0{oc1L^M3nXkP0O4WMd^gZSGHG_XB%lAoj;GTQmCxgEmh~8Ve`29C_
zN1LL!xjZ<0+<)~=8E%a*O!4OTUw<=<dgh*pZjWwhzFCfb8Mobjeq~TK_oa5EF8kHO
zZCs@RV!a!1T=P@%5^Y!u?-jegHdpQ69)H!T=J^vM&_2ncv(3pZ14pTTp%h-48TnGl
zY<_Cbo;V6k=dSkEIR7<Ueo4&!$hJ#!=lspt(sA*XUwGHu*ikrj)OlfP>}#QQ;SUCT
zN1V!m+wHhocz0w^suRHAo3%gR5>-y$*=w84(cNJ%`k^rRJ2|)sHj+0>gYS)+HGgY#
zJN(Y?{@{U?D8O>`CuJ1JQeW{_qDuM6=&XE3ME4ACJ@ABR?qheH@mZqpS>LR{mXKD!
zMt_Y{Y-e^-?Aq%;R|V9KNjqewI)Xva^B4+ry7UZk@dFg7_EHZFi4i0D<<97Wm1TB(
z#@V}P>hbIS+aI>=Ht+?$7ri+kg9rP{&D!a&hGR3Y{<IXrspHi$O7hm-!$Vf{Ejfh9
zSl@|at8}JxJgj`_<GpW&vRVG#qj*y*_k_by&CzA4%*o*TJ>gwZ@K!jy6@CUEj9<5(
z5%QO!tp{%NOEuPUwGoyXUNDt#?pHqBZZ`Lyw6k*mQ?49N<U<$%;}zHRdf+S)!#!oD
z>99wf+MKLc1xg{<g^onA5{V~L7Y4<dA17F8BN$2#?#07iJbY-tXeRI}`gkvPny=dF
zb>7q`b{pRCC{2#CjdpT$=SI6Scdz|A0@nO}B=3>PCj={QJ}X<9C-<(LjjWY>hKH@v
zTTyw_V8#2T=%J{#(j(&d8s~9Eko1p0i#F{pqq0y4YR_^Q*p|5nSXi!!Zf(Xyp5cx-
z)9ipHFd{h<?wt9?8%{@zSQXfME)reeU#l|lZ~nboEpX?_r9*Nb3VZt9kFJ!Q=Ke`=
z+>&Qlb*4nEZEr+!*z#7$g`W%$4O_@B3g>Yf8$;M}Oe*I~8?h{4%!-p{CEaCshmAN&
z%JQh>!G7d)goz|KgVQ2!rq?6R3zmV65F0lK&Y9vN9}EoMti3o?6s#0uB+45kzjr38
zS0m}i5x;iz)k>5`K!d04?oq@F?K_F=IhjVa5N(BU%`VdBPln16+h*;LcyRshJ;T<u
zfkEP>(P$M}nZbf;4C^qg5;A5b&w~fr+m}U@h6zSV?DFZCMpL)>O%rSJoHFZXGkcwL
z2y~xu(Koa>&xVL*<cB7rXsnd*kRL>>61kyyw+91j^~KVPD9Y%o{nZ1d#`Q1$?ln7e
zVYG#bZocn;UHSg)(I{<}!^dgu@Kl>KHZ}%p;o-4#FtX5RTzGISZInhg-f3GG9_&q5
zXD$p^Q)mH?$Hz-IW22<X>F<sVf=kH(@^&l>dH67gmtyIGY6`w_rF+iuGycfwq-nn!
zu;a)KO+kh~-Dj*k_x@C{|BD>-nymt~S%CmXD>($S^8F}>7}ztnw=QpfKWv!1Q=Ft^
z*I&u%`TTMrTaEJ9o&I~*s-d{^aSN7i^9Z<>9}DZ%m%whAQs&s$N8D<4JAz-N?;9lV
zYm#VeUGTuKlI8<ra3l5*Ky^mtFf^pA5xMZc45GSTkCK<apQyZa0v;r#2M*neQSZY3
z-R)=my>nC6lZ}y?oG~5JCDE+SY@eu{e$K3%{xWvF%x(}X+((24W<J>%7!m$lxUc9}
z;5O@%tzoNwI;*jtm3Cs+fa6{7?{AKZ{Pq9*zVWrGkRyzZF<adhfl%bb?LlDU+somK
z4O6@oZ=WNG7D8SxnL&p&TP@3==GPg#dwKA=!Ju|7O1`MCh)GHN##-}OxW%3g8=s2H
zNhbj?HFjw^A!0Ij3@Tu!!B}i(CmUE7&sbP-?U`wW55&Tc-N{DmUjLJSaH~+4a`2(?
zf<z8$0#4=;jnpI`O^{Ps=cr&2g@1doG9}#>mO9%XCs@YA1cyb4kxLoDG<sLf>9%4;
zGM8(Pk`5pNe~u=6hXmzOyT4MF4vT&<Hh{#$F0SsdL^O4df93Ct%qzceR$gr!a$eba
zR!%m4Q+{k<Q}51yUw-THaFe}p`e^ep|9hE3^m6U3rub#LQGNM^_iw}Io$AX2`u*K&
zZ+&K9lZOxT#)tOL%eNlKnXVtV#~<%MD?jwq(fH&3S$U{{6pl>(G8{K`N)Ju663XKZ
z>Ey4hz4d#zDSt)&M8DtWJSl(jj85e(XXWF&kjnJY6`jh&$tOpU%0q83A0Ln*mbv_?
zKfZ7sQ6DewI;-C|&;1Zj)gR&;AF@y0$k3MM8y|YNoP0Y+#c%5zJ#>iODBF#s&WL}?
z(r3cqWu1<{(#p|WkB7t8vso;sp{g2zfmQuD+P(D)wbcM9f|WB~SFsb03<HIgF$n>o
z09;()cu}G;iOq)aL(=-=9r&*o`e&OSd?C3ETr~poyKa2^a;$*ofoZ_AxAhxb`QR-`
zQ6GwsK&SrSIB<zRS}2fSZR2P`$TvQ=UO#{4T_7sj@m+kjx2&MwjfUr025i@R?6v6$
z1jB&at4-n1-#kCmG@~KRtI+_wQv4E=iLw_3)ah`rt7t7&aYd>pL;C^wS`>aVw9a=$
zRyCQp!pW^-)lVk69FuQrQ?7wph#TRHc`<E@X>JnM<FmR^N3F<nj$eO-`5)>Ok?>cc
z6~49dMt#jrMh6FCm9)Z2c-}R3t3A<+PT(mEAn{OS<ZNrmv*x2DLSX;|1U$YT%@YUx
zlFSX-3E#DFD@c6KEhNQ+8S^6|F!R+0nKOXN1pYBGtr`;wEi!GO7XfIOjyG$#$FkYR
z^ToO_>yy(Thw|VWZfwsO4%ld{^fcY#IdYuNR<YU6Iu)roI}z@&?7&hzWfJocI@v;5
zD*RBX%0aqpm(%B?IA=ve!nBocT#OXD4G`%EW`W5Dz%tjYL!$>jOoJF=Rjk@t`ym<g
zwMTBwn7uGm;p$n7c`*714s?1IKwr`a3W<xM?J^^#z($b{jt@~Yu#)9<oUo=DgG?3|
z96l$_N<+<=9QG4a;ZLhsNWql)C2JCm8K^s-PXLUr8=$f!Z<5g0rmdtEL+p|paB-mF
z8qYPR6&0H6hBHv|p!b33=HOK+gRRu1R0c_|&y=|VOLtuvKGaR$Rc+WnblP}=3s_Ic
zc{j93#a|&m9NzGk(9bb4%@iV63J%vJFS(v5MLlTLx~@Vk@?KyfI%JrLkX@7#a0IYX
z8dWjoc@)lGwPoeNWB|o@y1KNQja8Swz=X@&rW<A+mL@os1M6Sp%+F|~NGK#MlUert
zBkKW$L|bTJZ!<PQ{kp^ypnhy?l00oUjfzHbaDC^Rgm|fWIUU9Ji}sw=X;r*g+ol-U
zABf7akuhu{C5DG?5SsS(26Vs@Y3CR#Y@-ff(PBl2*+Q`hLZ1bRn|Hd4PDV^Lz~Tak
z*5!}Hf<!~6D_G+5E9(NQ1)vFnP}+)9VboD%ebl7^)R%;d$PF;1NLP<dV1`5up<=KF
zg9g?xcqGkPZoJko>S1FUdN>M<VAc(^3ov5{HBP|zLEe3G0~w-#iITCQYc&dh1jb~6
zsQIvNRM1WsaIj!|+76+K_k=^X6Tw~(Wv!$x?kESqpemh}PJksp<56VEHCzGHYD>0|
ztA-(5W4u8`aEsQzh<a`KW>k_@kum82cEmO82uwi(`<O_}fl0=7Z^n^Cq3fP8s`G_e
z5ABZzQ-rLtqZ)AI951l(O&dW%&9itGVg~dIUkMV&<lf)DCCTizh)<ckQUvZ62pYok
z4D8Le0{-kJj>8L#UL*sZ(i=1g3~UDi@L%D^WCE*`^rljX{^P)2FhODZ=S|adk{Yu~
zo)biDX<+Aq@SH9ARD*@ljM2Pl3kWslDRa9x&(CAmuu3DU3_tdxfof(T0pu2q2ZWRn
z(0}Lc6@_+KvjLw`r|OrSY?;yh>XgX?6XRKXWO$JOU=mq0)1i@+U>fVjhTzA*j9472
zlcvkHO2v4P$TTJ~l7UzZ&=nvauEPLAn#Om&)3yRsQo@m9P#OT3u{3A(s$-AZr;H^#
zhrVkTP~o(R_Jri14Nxb@609xYF6m`M(ri+o9*rP@4CNBQV$JR)gt7+GjFk>Sqb6g)
zfv4&LEqTiYjBvGBOk8`V8yx76tqZ6gtOCOh3|M+13K1*=g2M^qGDxI>dfMpe_#au0
zu%Ze8-Bp(`{CW7S8y_vdLdH3YUN_l*5o1qq)?xe9+TGv-c$_8YF}7cs_ihi(YAH-x
z07y{|v_D!8E^NplbRTL|j-f3Ry~<X=n^BuVNg6h=juEGYRpLTyHf{q3R=6XfR%xs|
zN|K?2{-VJZrkYQR#E=BI1d)?UE^*JrzUA@KyZ?8T5WeV6A%I#B;ItvFI_}6}yiA&C
z!VwP86ve?TH832Sb&MT22;5zbbQp%{m#q%ddNkJbiCLMz{tKbWW?2ZvaE}0T12Y1z
zz^F6_+IE}-bO1(PWGVEA+u6+oh#-0lhQ?{kl;diADek0+z$lfaZ=rH)wnUYvCi2;;
zcD!?(AW6|`2CPs~Xk^xJ;{x@}V@0~0vKayU<p2)#rCtz4Ci&^#ysPsdCB1stOMu}P
zT2+S*cjJiBhcIO5W&@xLx;!*uxq_nNe$QKRRv^=%xlK+>(+<Lh3`N86@IZ1vdNJC0
z8%IYCH+TXyg@Mw3?D)+9^)OsSr6P4PU_eYT=vLIKOs-$SvneMlT3mw!>?29KK8JQj
za{7Vj)~!VliiMg;I>r{xR(%%?n91pB(=}s-+M=G>WydB{bBxUZ_?<S9i=_F@?+i}*
zd*#?8CAxQ{TB@>KidTiRJw*|ji^=jO=Mt+<=jg5N?>{yc(!GqroeaKlmvZ+{H}@+0
zSp~|ZT4-M4k(9qC!}WIcEOuNRc!*2pR(sPmkqk$A7jkkqtaZlS^8T%AS{rUgvR_ze
z@4UpR^X=u6h#S*5mhHcdWv+w1JE{7&skN?;j%;h5@7j58+sEJwF!zXaKpgEl5^nd8
zirEo={HpglnD(OwSI$>H_4!}Ei*CHH>p=QEEzxw^$Qd5%P02&Fd?@W4sydIbG|FMG
zZ{DZS8PZ{*Z~w&W=~^B_l4H(q-=z>z&j3xf+Ng+hn5{mO9`Tbm<t9125ly+|onX~`
zX2kbAIGL2oBYwQ3a{K)+T~hqg^0{4`MSt$P4=&f2Xw8p(^`%L<yHiE~saie~?p}JS
zXuq^K-t4`=hepb?MSprSe10<g?ud7{kVD~L#3NUqzfK=tji)vl(G+6MjP9hYBEWpC
zb|OlC8Q!YuRBB!P<pCNzu&ad)#%d}hom!E`Drd&cOP!WpqC-d0xS@U%(6P*5R1icg
zH}o~CE^GNZ5@I?vOp`3vxZ2p^<OHbU9zc`wM})K4Z;p29&k`>WNfDn~7UKMOkx*Aq
zD^IaQN6ou4hxak(-U;xGjJq@TcCb^$B+c$UJ>|XOWYeYR*qaV}u9kjy?z$YhwHfUH
z+Ph(B?b{E9ekQ#m)qFAQ6`Hj#bZUg}vmYO|n)~;ZPJ~UiH@p@*xo;07=BiiI3(mIc
zB^qa|GG!cPlw(i(qTsW8yZeq|J{(MRkIgi*%k%|5_w7)Jd2(5KWO=JN+V3ImKHNr+
zu`I1l-j0nXN?;8(cSZ9f&HbmRtQY*|PsB<-to<_7@6x_=cwLz)vd3OdWJY#!7Qv06
za=^<d3B2Rg2N+3HD;^t7S7!diwhiyOw?Y|=FaQ+I+I>_j!zdF5^LryeEMvDCD;GYH
z8CQMnOLX^@!yDM{iLrqzsv1p64F>!OPRA+-?x)kN77^|^p)saK8lPes@}vy}mEq$J
zY+!@j&A3L1t$-sIO(4!vDe|f_rydL|Gr2z$B4jrOnP)_-7R6US`LnxudLLt@(PEzw
z!R3}4QyKHZ&#_8+%xLca4qgBWkqZwj09r|=knjCb&S;iXsWQ+ImHu%UlJxpu|9?CL
zN4JqX`j+Sm6W<-7$obR=Tof-nn8^X`>AjQ6GTa+8wf^2tZq$(()IB(KEv)v_o!Xym
z5j&<MTJub^%*@i@*BSU~rO^YO2zmkx1D+KK<A!)9E2q9LOj$ZBSnd0zuZ!z%<m!ix
z&}mQ*1puHB=77qFyNwg~@2<?edUss)`>J;3^pnRUqtx+5tn>h)v7ih`lo%TW%%uN7
z+UALBDOqFbQ_xYm=|#UfR9|Be1=Fo63xSims$@;9Iwu%*GJtwe`}86WSfhIS)Qphf
z86gHj;6=^EB0aFEap#ZbP}6IYZL8)dg8j>R0S-7wV4zQ5ZH&aF)b-E&yGnE@t>nI`
zLd6?9k#Yd<R%oBmtbM~~&5?iGx2_ou8Knm|rD4qKGb)dw{$j6C@jW1WUl@a!ER-y-
zkOq<q_l_mJ9s)(GZ{rz9j(mu$!0iJ#Auy%kBK*Hx<a7PJbJosQPkVXsR~V8zulxO=
zTR_6ixvF=7SE8Y1R+;nja^xWD7~qz9VPtSCqH%wi2M>n)m)@7OM;Vh-*bB3?g-dgh
zmPQ$<grLxa0z9=2UWlX=nL)TW6)@=MMhkA4;>~iq;WgWz!Q4a1;SG*=n3`URj?Bnh
zn+i<TTQ|}M+%NwPVSP8`U>W`vRm94@iUs^5KKg|}J@V27C#A=^jI1Y@<P2Kf=c4(*
zN0C1(Z(i8v<<C5Wc(Z*Wh>g_(DS-#7jM7b@)UK<P((BZPv4H>~Ta7rKZ9|;?8Kv=O
zz?f)$m9FjJh)@n>>iwmM!6L;bLrbr2gpiILK)-3$eiehvOy9E%aRt!n;5*oU5+hZW
zLJ0l{Q$ybXDu4g!e4|sc#u81wj9@ih=Q$toz3}1o$uq_2YJ3;s?TvJGSt^$`OZ)fm
zytyczY=j%~*W=VUsxWIzfoB1}XJuc1Wt4Xtr4xfNJ|L$zAgx-eKzcdA4%k5bWVN$}
z1jZL0j8>hapIM}Lcf5KFw*09^Hny_r7%RcC=>dxEFu?P*Hx-V;Kfaj7Q@UdVdt_cb
zln9&+VzcA<;~37LY_y^F`hglYM`p0wqp7xrzVlU2n0pc;X$21eVm`1a{^JX)9kR}$
zwn<kRHi&p6+8&WpwgvQ#lmMT>P&SHihk(x%O8^3_{h}Au&Pg`6Hs@YK3|<$zf>^T)
zc7)|9m*EnJuOUdG$W+cTk8q^IVju99J2}nj=QJ}sP*C#)b)F8fGQaquk6pV&*uel=
zifcRb<1b=%igGDsOktMV=?7z50O{Rf#Q=!Dd<1A;Q6qkOT7xX)QW8j^iD{6`4-j0j
z{Rn0^X#Y9D)aci(d9ByiR)G0Xo8v!<$Qi&3@x7iG=V-Yxp_-#ReFRE1Gv(uh_;ykT
zmnRcJ$7jq~`Y@cG=kNLYxcr+I8h1p4f?n4rTNoj*xE7)}(ZU9w$^72|dKwo5pmzfn
z1fX{V7JSRO0So^BFOmNXFfjhM+tS9c$^=gPUmxK+C#d~TKUxcuSQqP~4*7H&q5+f%
zv37|AU{IfW`%PbAKbdXQ@BjS33K%L9j`+sgjc<duQ~l@H{`3F7dF5yCQXbjO0T4js
z7wv9o#!<-tYK8)o*vv>+j$N?LtQZPHIY~1Kg81t+0WJyfhrou)mNY1Qf=Sv^<5-J3
z4x)BZvCQV-xMhONpt*TLqQ{R*4VpO51D{O-WeLI!$sgCIR-xlbbVI;Ntkd8Do{Y*+
z5lMRH3RI7{rI?hF=^*ivOw2>eB%}&10G<kltsUW+010fTUM>3~@C>5$BRrHS&oxU8
zz2`<92$xnCuXUV26;oY*E-)=TQ#X++F=sR^yT_q`?~$@!Kg)(6A+!$(h8zl+v=ku)
z(hfwzB7i3VP!R6ISrd8T9J&?SO<M7sf!c@8&3&jCK8gRjon$<t%c|q@q+<rSw{Dc7
z*vD2cN^E+h8`%_~wb6jXCV&kZDUiI5PAM1qQ-Tlpcr;=G7g%N#dvomktX~{g!LRjO
ztN_XwS_9C<<p%4=Mz+wYTCgs%j=Y3+g53FocY$hy^now%I*LHXp`Ef=5%35k%b@)D
zLEh0gTARfIt%xe4UBJGHM4;?1aiC%kV<&2ut+;XHm$=kxBhDg=bRD~9hracvKlmB2
zGVlQsq&U+hbwJfnq|7!-JWm%tM$RS`gRD3t8~SS$1>?;2r$5AAqoFdW0LKjv+{=ue
zmmTq;&S_QfUl7}{TSuFMqX_Eo51ey|Jjk3iANh77ooBF3HQ4o^e$I&ofGWbWm0Xt`
zVNck!bj)#jum>+oP_oCEEo7s>%Dh;{P~MgV3#-$XCW5l^Htx7rs5Q?z1Qh400=Wyo
zC88I@9zB5U$PICSCs$!YFZl%n+Y<p56AE56$kDd80WRaUuB43-m9z1%$Ifh!>al~U
z6nrgE<h3%8C|w=IS#>xAXewQ*L3>zq2%Zm8451KeN&;L4qbKKd5}SWO+--Nk7T}se
zyx@-x3#c+&iwr5F=))e0LxQChz4e7n?pjNWr%A&L3Y3;i=E^GA4>kq^I3mm_v`3N~
zJ*a%lO+X@8NLWWh2nZ|~wa6t<UeSbhpJgWU(&KOCzo<qUKIB~&lab9DKWicx0u)Ij
z<@fy*P2ft}Fjml2O@IfjZvpX03_`(%LaWFX+yx;)!CYaWX7LrSMH}KQ%u)DOe?mvp
zs6#yj%%gzp@_NG@FjVr2xYz8J%(Fc}UbL5#COIHox8S@&FQgK;vg3u=Q(mv+O#lbA
zX}+!MFDNe<E+-&^fF%ZGD8n^?=U_#EbPTf$hL(qIktzf5954|_8sJDw4tOdvY;tV#
zZt*yW=*U9=#VqMbAZ}cdDRZLoke|Ht#4XV(^CAxs(e3ai4IvnuU|jJ?r4tx?C0CL#
zmt%DWFLa-p0ixbe!fCgnX3pT?U722&Di#EgiuxMQHdH8|1`KV^`^k{Q4xz_x$tsNs
zi0RdGr@>SO@C=|4G;&#!)npPY>*(4a-5Cr-6pYs(Lbbud0Du|epd#dc;I$ZxrKK>I
zqs0wyfPjRg4Dwa@9PzBlGD4ccRgSIvOcVg1iID!YOoV?7Gzs$Cg2y7gZIC0I(F{0K
z+I_5oB~Q%*n1&?(Vf1xkO9bgflT|@_w}SP@*GibnB2DtD2J0w-q|a7uNr6>X0M&q{
zhAg1rVWKBJDawi9<DB{qcZI2BuIQ01p@+bcvr=2Q0!O2$Zo%etgS@?JLDWw4F0g46
z-}(D@A(u%rr>T+|GZ(gTK0Sd9a$ZVw%Jnh)Pm?#<eU}>uKgJJGAZGjd0;*S13b}4z
zHbRVmK;aG8xK|H7lQm&Bf=pvPBn-6%_}o2&5fA7yPG}fgkJAB6`WFA!mq0-zIS}iD
zj1_UIolbB;uDqc~4^NN=8;khFxM~5dh**uDMaUwI7;U^C-`5eC(1O*kKj&024JfgM
z8r7oK!xV;;r1cG|W9_dx`aC*#kmxqA-To$KEDR?|nqa?az{RLyVR(S|B0Y1O5;CYD
zUEG670%TIa+KhLbPNnGSr9;4_!2)!?d1sYp5{h<R#v0$}n1ITE#^R+oIdU%OXUUO9
z59<U$6SZ4wpxj6)v{~ZX?|lQa0RR)th$P81T9v9qCt!#yVXg>N_2mE)cEOgxx(LHm
zg((bb($H{RVDJtTyTGC*GZa9$nc)k*9b^4VJ#?;Q!`Nor4P`TClCS^{6lj7VmaPvh
zswb>CR?~jvukS)XwXjBFB|VKL%~7<6olI29kpe##OuvN~g9wC-X+dilMt8RLqbD%h
zctbEDR)x!6?nEWdR>dNlMV!>Nd}hNoL*E?(m4KvS#W8EBx9v)La#l}P2ln<>bM(HQ
z^j|UiBL(~L$i#ulWc#5E-TO@Dj$7@G6DLNW&yC&n`#c4l?|)+H2bz5&aDl(N@caBX
z`Q54Jq11kr`v5z2%*nC#k*z0Qb{5*H-N!B=;AW@xn7<^bdJ1t@IenQm8j~y?US(Gb
z=dfG2Jjwbqf7Li7ob}V!J*Vr@{>h~y13RyXiB7h3l#Nf^%~s;=9lt9-YT#`TwU0Z`
zUy9|v@|Cr3RLj$}V|1m2$m>}rgCPT*|8*#4zy8);vdT-JpmtTJNAWvB3z3v}vlJaW
zp6P3EUdmOsr)&1Jw>s(l{i7GE^5<!^SK7@-JF45qYUfJ#FO{5O_&id44Q}Q)Xh5;^
zXogc+pgW6&_9ETLX$IUzzrs@!DSIA!qCHxC(-y_2;G=uSnN&R;&d1rI;#2M0`79ky
zWIQ_j(3*VR%am*0^a4{$FRf+P;LdGiHk_>bo>I*a`yp&djtzG`vJF7ucgD<UDy1Y)
zzf~JrQ8Z<;(Zgn@R;xPksg3J0wOw?4?YlRwh>t*-mzT@comxj~$ePoKE3r5Q@aF)x
zHCW$M;0acD+}e8G1p8y(Q-vZ_#3erZuS9;JcE48FPW^sv85^6u_tu>L$8->CA;7LS
zU9c=wTL9oxOLO`^VSzy{Pg+RemhlEaLi+h%SXUZ7flZJ{=oaju*SFCa`<1SJEW39q
zx9&-PsC0j6tMtzH8Q=Uu^^5OoUhCNW-CNH%#+!XQl6&7Hz@jeHK7oHu92A?e<xYBk
z0X)RtJf41*l^E@O_PB9t3}#m+e`1H1{)ynbPSSLdLmf}u&X#wi&D*I0`9W;m(R`$I
zN^G5II&Xokbp1FxalKRR`qpXboN+E4kXiPYotXmd51<J4xqY9=AxcN77P6z+!O>`|
z+*Sqo=7rPE%VEO1@Gf=W^=sf0?VsH7#*+s~shY}G55V!YUhT^n2PQaJOMM)E(;p}~
z@pB^^L0$Z9`WmmE$pK}|+|+!lqvNo3@nAJWVh<dt6BO+NQdWf*;OUvevO+GUDim;%
z*Y_>3>MC?G)q}EUM;_fOwie>CcsaF_yPR4sO7Bj#oSLTD24)Ph+4c~3VSg8#UJsCI
z+3~n>0q*haySG$kU<|kd2xuw=bZYJZfAZjl(rB)aBh$87+V_c^AtTO8;Z4oj?~I+I
zE6;sk3`og<abaIn$kNeA(#CE%mfAbBmfM$7%?(*vyQ7buajGh9AYcTdk}zxyNqXT8
z-ax=5wv0e4op7xVM|kJSqL*Bz7wMTIfKMxX&be@%W5)o$ddDV_e?FVra1DXXc=MC?
zz5^sK+2@?*z7NAS9bC*O=voO8PpUt_v{d<$L>zjntGs`bfADiw>5&-tOojEq&Jhd(
zrmF&RbDU_*Grs%&`|8!t7RLGE5tfzMl;q+|)sLiQd7l85qXBScqG60+B!z4GQm|*j
z6*&_kQw{)CR5|bNY~yH$(&5hORBeyH3sV0VDZoYhQ*LL~=h-)G?58w>SV}>;Hi#I+
z)q}aSm{QJjK5LY$=Ez*m0%@)i=WNrPvd{U=j+_4G$zXIUhYm1eR}LJ$j{<aCgqQRP
z!tgyX#wy3tfUbKB*E+Hn_JG}1>Z2gTej+VvD^p`BxHk(PpBUM}fyK3_vA#+b0Qn<&
zarzUTEjX+X=XT^xukYlJz{Dx<BVl(~`)q!B2kzMVfgE-)&Ms|X#m(7Mz-EER3$Fg%
z<|#{gQ)k%~MIQ(e(XJU;2&9Dy-^>n70c!s=2b+$R25*`j@uqJ2{4bc%D0fPOKw`#h
za)6|(IUYBirmVeR!h#fx9s`aEIMwSj;tTsetmn_#0tJ+*D1bRm(kWvzORHs(1)hj3
zrc-8xZbhz1fI#cb+Gp!P13$SXhgS3u>HjLP=IaJ0FRXzG>(sn%Svwd3HQQ{9>Pu4h
zlE|ujng<!jM0bOGgnjR~P;<~%4vgJgIZ(PUm9#TvX<%cc8jZ5JkOQ~v3pw<MFZLO-
z7qP`*!l|7vtwZP&C;{j@t{f>MU)d_)ae$M6JkiKH8-jRWWlD}<g(J37wJ1O*{@amM
zKHR^<1*xnOB~8F|N%)|X(#Rydu4(PV*er;`p_z4<ii3SyVx~l5KnpM4xo%|?9wt~q
zuM0+ja~<k4$sJ&DlZzuxTW0h(Xs{<`0A+QW(0Jnt>raAdK0kmVn_Qf9V5{MPyxe69
zb`-K4Dj4OI>b5Emr498vO{}&+EnS(qX-?L_%PW^uSRVDVoIV`}Ba=Y09!gYZCP+L1
z9sSyS{&P^)dW)1;-}p(e&toK%CC*131L0Q9*CPb9E}5{nCV@#pQ^=Ho(}7xmy?+3x
zVKvLi#nd#QLUFNEnDdi}G)2_RP(zwp%Za645dudf!SOJ_igS;4Nr<DsvG~V7-1hhb
z8R|q+8o8sG#->gCuo;j3T8wtC2AB6I-0EfuN0m6rVfe;$hZ$^oz^Ng{JAfx*?gGB&
zQpOQ>V-fZ#q{C^kQtS_KIq*bL+2xB2$_qB9=>T&9XB^Av3Gm-XclN_-r6(=*i!m_2
zj1?b!oSeU40ts~ymTs-^-^2J$Jm&v@fbng|^x9(ny+Ji$ue!|s1%dFbw+V!ABZY^0
zFV}ty0-=4MI@<i8zns~v8HC$!OTR-!)Xcx<WQ(xZ|F_b+7gT0IjnB!+#@ocdotMi$
z)}+RrEhgeah_Kj7r^O(|q^}8txO-01{aUzXIDEC026%^8f9vK3q(L8btZ-Y0`_6~A
z|A*=Wy#VWGNC7m9uH#&*15r!UA8K9ukGH;k$GiVtgHt`;I|=+(?=8GapOg3t4E@?V
zf)*U0VH`Z~#y|K#1pcm_`+D6OwYO2IY9NbV^58-;-h{0qrni<m;59mL$8rb&3jzbZ
z1jj169z2YYA+&2yUO<3<XM)bc=gbK^l|jaj(GqwnYpRs0^)B*<X@oW0x41GK-o+#U
zw8}9ozaxc(w97dlEznMs9|bc;Y7K6us0Z(d??cGn7^;L77_3r8EEA3aRK>I`*8>al
zjEMAfr$M^KlAiU@ag^~0t<&$~QP|+e0$}hta}>*U@L62L#`hJ5e%EDUw2ajvsBjU~
zuO8$gljt<aG(#MHXbA=^{m>yde~iR-@}>$dA$(v#lo|^_tYk$&!RfJ&N6O9_JlYdk
zN$9N{xB+e~V@HjcIB>sndhjR}v0zP*_>hvk)Vaplz=RU;HKpM>76ofICczBj21hf1
zdH^-v<p3`d&~nB(Jf(%Ko57Es=}WTMfGq(8CD!jbupnW_4+V1u3V<QTz(aC$y&scK
z?V!ogj{77cE)vnH%pD8VWyM~f?3`fT$|UEV2b2hnY=iwNFL6^8y{u@<^OOKuVz|74
zcFP;{9HgrRm^gvPMi*T3r|k)e*vk!rNd?wQ>lrTE9CYQtO2=!OXBMEHIM+LtY*a3`
zmH;+`c1;1e+1Tl>@j1ik5DOF=v>f9K;ZyT?n&I^DK$s+QO}E7_bK&;ot|9Cz=bhpl
zfICnMGuSG1nTy!}N^RJTu=P(5p4My>oc=n{5*`O!6EzeWGNN|ep1}wl;R#+4DmepT
zn_CC{cvc{WcV-Px!X1T-5V4Ig@@9(mJ8RiTY>r^VMlnw_g|uiFjlEz9tlB%lDcNH#
za!^;ag{Qt&fMYOYbK<Hp>y2=kjW^uJ<Wv5v`R+G>do?BErv*`YG*4y=cG5SJ{r#DS
z?5CLtJ{O&%vp|^?jt@z~dpw6A7z!)P4cbpjWz@jT6%`^%Cg>zxYut{}0M3^_G>r~r
zvaaY^K9Lf8CZ<KsD-?3Iva?zE#m>$NHSbAG9{pn4=yB>tgqlE9Aiu}=2%EK>MIOB9
zY|i`F%J&2DRuJqM%0C0LMKBw7Pf%D4P@wx^c|Hfsb*2IJRzY^q9b!9AXVwrr0oAJD
zqYq%x?_UM3%alL>AHxS6!c}J*f!#r2L_-Jh>qb^^-qw}qY=c@)0!ZSmf2_wB1k{IU
z0epBG4+hJOCII2A)LDYzMo*&8;$49@34zr^7Q_Oud6BBRS(kpb;Y%k<a%{$ukcc;`
z*5KRGFp|*>JZfR}sJEe;w+`VVA8{<=&EHssH>nGWq;1$l5@_fjIA8$<V0}uAzfwN~
za0JRA%LXu34JzP#qs3igfd<!DT^b0YY$^ft07%!YY7L*LLKIZaFeE`j4TRpt$YcLu
z9qN~YxoT{a#(d^{4=`1v2NoqjeoVg6&&&Hg4>;j@TY7Q}ho!>+zpFzTpOvC2usqq0
zB`Qv?_&{PXih}F!DFlL|-{35A+=gmg5ym3&bQ3BXDTAPwsH2ivN4?QTJmGg<zYjA^
z2B;MnYikUt;fZE4zU0Yjmq)ydf{qH=Hxh3H_Eu7eDvG9o*CY^K&ql-0x*=i|V_wkD
zVVI~N^IG6-VCdG@i0Eq)g~GE<*F<0oRD^59u0EA~BmP5z-iLufJ77DAo3Msu1zaKO
z2I8J83SzUNg^t)4!8*2qlL4D1z@Ny9O}{L>i#k^2BsL$CYGl%HH$@I$oq+2|RWOc$
zfEF1UY8V1;`2wXznA;`RqCZ1gV4S4i{Bt8ywISiX5~`4rST9DBjxz8=Y`~Ale;#D7
z0a$0&M^W0M8Jmtu@CR8EyES273O%0Dqwq8I-2xLptH&Eh5O?j?qNCKfL>~dz?S>}C
zqPJ@t;-SOYAp0P?nP7a+`zkQ6{o1RxODzD_oFuypFdHFLTNK7X4J=`tA`lA1e1UwC
zPH6-)N}{p|WUPKpxDE9D>4uhTK<Xr#??vM17I>0IsFE0p@l^D*RugccO#Z=zcVPwr
z*2g_KB%8^}CAsRjG&DJ4MNm#TSX!P(Aif@+=y({GF+<_=t(aOUnWl{p=qc!^B(omt
zfc_2xtz4(7jr8j$N1*be8@LjJroq@C0R$GNo4+(M7iVBH!#R#T_GsV?Untj*`W%52
zLktZM%-$5R>;w<a^}~b^6Yn<WT?p5^#w?zM>D>poi}K*6)_u5D4;#9Jxw@2}zdi^%
zXHur6CWT|-_u3_$Kr|hYEz^4_M`wNeRtS?qF(C|}H5BH0l?Onsl0`oTi07Ia`e{>i
zngW)Jf@^TZ3Na$?V|;~RyT~!xU0~7xWISUAdTp?kU3;m7ZUL^4&WNV}TX#Fj7&y6U
z%Zd$$TuGB_K(X;oNFm7$6gHE{7|jB1BB*o^OiMTkFwYI4H3SU_gI`x$FWO=p!#)xf
z!3^iR@Q@D-m6)wD@)PpGKikb|fu<%36kyc1x(`t{!CxP`bgr5!?acw^tlpa0T`2W$
z%mE6kmi9`}lt#Dw4mMAmC>7H{)<-8wAL85Oq~hswELBL|>QuO$dp_Hn`5)-H)JDFt
zS=^S|)_Dfe$G3>j71)=>QPK6+VnW@{ukywtsV_3Vlv`$gUj0b0O+0rFv8<fjF>Hk1
zKV^Q5UF>SR3#&BD8*@+TaY-#WuQhbYRrn1hrV9wTCQP9!Vq5q|$G^3mv@MPFAh!Oa
zh1`0X>q1QV_sA`DZ^7A13+dmL?^&`pDqw(Vdc1wAYEM+ROi)=JpkrO_bds-l;DxqN
z(BvKM&FU_7>X1{&rk(sJc6AOEo#xB_GAk@~4S%XI$(@Z2wPS+sR$urLRzyXSEi(8O
zZ!<g3uw$%KrLcWkH#QwqT(zN#&T)>#CL*3PCVF6aRb-Yu&3#O5tK!<8PPdA&JTv+$
z(A|se+?Z<cYVELosXFY`#wPHMl$roms9!c2nb8cu#ZrnJxrQu*R>+!EA(H$bQs;;|
zwMl>6)!yO+PBx~i0&ZMDmHT(rW^?B#NP(9T5|-6l-!G?F?ik+%WgRfM{sWSaFqf*n
zR3KOffPkS{B~a0nKMiN_F6e0fKfDNB1GKnrUa217t4?2)Rn+cqJDnRjJk^V!p}Wu9
zTdUsK*nMob-}mQD_zoTp>1D4fa|VEoy&K^zI>D2O*vm9jIFP!^Cyv|QZ#voMhWQ(x
zbDsOQ^e>&R7Vczc`Ww|}0YSZdx|&J>_DP>i<@cW6G6^2d-+nM$?%d1<-vmYQ6Ar)4
z+x5tC^R|^;SEaPi^bZVvPGry7B~O`)1)qux77y8%{X^xMGvelEB7Y{X&g_}_7WVMU
zV{0)956*@>Q@s9r|9X*v?sG2|Dd6~}_i83zEn=$q;IBB@>Puh<EsQk{MNy)un*nf~
zMJU56tygoJhc+_P%d@=NPU7Z%>O9G1H3dxZv+rS9P`$o(JA<F%%0(s`RqRClHD|A1
zS_aK>rfX?Oas}+3($~9|A@j>(*CCr_mT8H3qG&G)fv|*m9wrt!ma5a#H&ydAmK=HU
z2}E_yi?-L;^?nEV*!5o>T%=<**hY6}5bzQ{&=)mpPXRrGm*C#iR=_5a&9>3Kp+*9K
zhL!gH3e8?RP~F&vMv(|EDK+H70d@BF!sKnU&Dp*hZt|bYo&?O7J_%3-Xx?i}0BX7N
zuI-@xpnS35e=9DhvNYCSmIvf6?O?o%*<Tk8I_h-_X6405<iancZU_ijED)SMzf6xP
zc<b^biWK2Ez2nFdL~#2V&@+t}uH@Q)p1d1W&v@$V0KTe!(D%DED<ic;)9e}W!QPt#
z(6f(bCnow*ZJRSW#NybO!a`;%MI_jI6|pk1k}d-w%P~acW6!-8JHKO+M=0lPbq8cA
z9NCd?D-EKG#}02<DP-lN9so=^5;|T|Ov>EX1w6SU_>`6`zY-yo7glA<1qi|nK;D_f
z9Y+zjAKM$l**I%F>|Z`@q^^IX1RmZP1<?%vYnpNi4^<k!`hnKg*?Wvi-(drUxe*Ff
zGIMxP0pc`v%R|~nRuVv&M%sidQ5&Sq{q5M5IeQ|jnU=pTcAaB=U(^1rN3-cAopZp=
zg$oY~IO)9lm{`Ux<(^PgZ0mvT%J;HeS0uz@E#tXYCB}82gd!$cV=;v-S}+qXQnHAt
zF5k8&jx@YnQGD~tE!pbm!wv%B(q<x8g<~{gkR$-jMQK#(ie^v>$OL?<M>zy%0PD;#
z3I}8(DIg?vHwOd`@7NOwxK;m_CQa_}wX3Wdn4%)GOQ{QcmgzLOj=YjyELJ|Um`b)~
zzh)c2oSDUaN&J$P#l)Y5A6;!`QDASW#T{f3h$WP0`0Ijb=l_SN$=I0A$V+Jr1EP<`
z9>*i^2fff<qD~rawBXdC`bP%S;4dR{rF|O_LvwE`Yb4F|z}J`oMxO^x=Qd!PXqi8%
zhvi~t^YUp(3fiiH%`MHbU(FpCm9hIq{B6}=?K*{V<_c)9(M`LsackGI&`#wTCeRVl
zPcez+kqdl6Kg_?3SjJ)(#KDJflP3|zT$(@qx)~?2O|~=<p)hw0TLjiJelu~HndwWR
z1%|@qYT2lC(Q$<w*ma{fjZs{gHew!iTVAe>yzg;J`r3l>IZpbps@z{lbF;L-D`Pp}
zx`6)<-*19G2t$FHA30xY=nNW*MTl$O1eAwY)%}c6808*uUW^wDM-;HgnCPv$YvS6y
z9}LPit-;F|n4wd%5vjqkf~N<a<WN(diva|UFDc%m34&OvFL5Y(4!}zX3wMBuu^(*c
z1RoGkp+FB&B79R|)$vMbB_q$=Gh;?k=Q6^fqWehEAK^U)^a!d1_>2O&-t?vNOyhab
z3fCM3NYL{)NAT{b^D3-et$8muE#z3I6P(!XRwqg3@+Tc2i(Nn=OYneU`W?7M4oGAg
zdXq*OP506xj)Bh3Clx>;aNw!am{33&<Dg;8Pv$X0nr!>yE|$XJ64s%18nEO-?qInF
zw5Z5xOyar-6XT6!<NDMi|2<$4j>Z440*g<8iTJ6%f7O4Y1?9bZ#)nfeIEcA_&OzMU
zaw`5O4&rGz6;B^M@!08BUVePTGx;yy|296kU3(^f2KW5)L^K&v6B+Mlc_zQZhWu|M
zrT>CHcn|;lBe$Rq1BkLdv~CE$Je(o_sH;F{z_MW+l?!zT%hffEZu*D7HlIGoG(AUO
z-Ovl&8*i>|mK#U1JTuw2cJR%&|NWP5>c*)SaY297ce?M~{m$jk5dP_i$+ho23Joq}
zdlK;vF~(qrN&tT2nwJN)DBiL_<`y!p0wn`hfEny-kx6*56Q2)cSyEqyMhB<;9uui)
z(8Dw{7BshMD4Pqm<BD_KUGVD1^8R+J_tyz}?d^7cLdp!-0(!L%grVP=Ynykn&<FCE
zD_QnfZ!umG?Aq@a^in^LHD{0J8VYp5KzBUN3`hWQa$#nG-`8o|bDu36ph0z5WV=jG
zEG*QQI2>!o)qFo$g>S73g}37vPLa7V1d{}_R>Q#lRHm<Mg1O5aki;xPdTMV=e~y*=
zee%Q7&(&qW4MZ)m$WSF<ZaAn-&q*gdRX>;AWAuQ+aA36z&EH`wnd4>h4WMsEoS89P
zZgyF(Q6V~oYM6czY|C0~V^FX2b95;DGf@}3bGj`mowFG<hzaCD6Y@ai>UT}(Wjo7W
z<0Rk1d1x~6yYJPkKPPtMMvQ25ma1FM9&D!$iVtwp*X(y1cNKzDM;q0ZRp+Wv@Pj39
zV}oYy0ExrShI|?8Rz4B7PfBq<h^4i2<|#y?USwhbD-pN{h=K<YOaPmK*!mdC(K!02
zZtlGaX=5OOJZtT!OxOs-2iqHV@CFv{01ik8)DFy}AneHiHTDD)?!+o02)Sn9o3x1W
zL;)#?02Y9khxl*aO=P~T!J#7bO;oEdoO(lxywAX%6>ZM7H=ie{Nu^fHh(O7$*tKeR
zAzU#cfg+4ty=@X(Zs5S90nR{Ss~d1uL9goRclny{%(8`U(O%?Fsh1rQK1;8nF{A@-
z&QP&1&<Q9uVteEnXPNi2gXN+aFb8kRimRb9(D+c871}n1Dg=rn1S*2T1C`|scI}a0
zuPe!ARK5ixe-Z>*$b{~$+Tj9n40bpeNVt&Hmt>ER0QJ-GH)7e>mFc9~AaveD!|oA^
z`tGxQ&8t^so<B>`T@Yv(Y2<+&bHg7HZSw$n{H%%4v(SU<rfc}x&)JW%LWxd8xaPed
zyGiT+cr*^(y^&qB&hepcpesX*H{uxjZ>*fMs82w$T#je!x<+I`hXKp1n~}cR0bu7q
zyNBGlmc|)e-3xq@SE?ak_jrvb2)J=*d&s30F?}FCEhB-YpItY^tf5>3Pt{-J-#X(a
zV#fxkh+*X4U;{>=p$mc@psN#~e58TTIw_xA+yAHaZi7jr0hdf*ne_<_jwp#fTv0%>
zu8AT+@Nqq+M~I?pga8;628JOs!0bwA@H8yq1mKh8O6w8&1<j{3<<tQ->ZgA2m78af
zFcQ~z*9~h7FjQ0;z8*H%C-p^cjPGzKJ|ejgQPPC#S;J;(DI7F9Ch(sDNN|sd3e&e@
zc&aaRWY1_-9#$Fpbp4I7LnPUcF$0J;u(5szb<}zk@(kz=K^!Icg^S=yf&&2kb`BsQ
zQb6YPlj-az6cm4Y*;7Ko3Rx!OgKS8FY=%AvvDBX5coKvIbzO8#S8>iya>(JscWeOS
z0#gA>r!*$#pu?hgWnIQqpdn>6u6eKye&&otCbcgoQJ8LA1B-+?bWT!_8x|BQJXecC
z(h{!FLZQpW(0V97!RQOSi0QWd$y4jV%EGvWfdS|BfwC(j(4`6Ks$AtA68)4?>Mnq9
zw8U3A%8%fd?s3Rq9RTNf-|v4SgoI&zr6Eb2M(TkjNc|*7Oat^n)LRPRHS&SVxqF9;
zl7XZL+mwDJa)x7`GW`!m1#X7rNkR^Wh-@e3yx6k<2#VXvttJgDHDpRPgq^gaF3zk0
z4ANl?>;Wbtc>h{LSE>TE2;5O0u7QgFW^;Y42Y>W9JWT1Hf@kS=(gQ_oxN(~XQ|l0N
zP0%fCcpgV!$T<_s3R__kjI6o^94+)re3LhPbZQ?RoU|r<){m1e=f=acDEW*olzyI0
zL?5;WvfC*bd1^|FP@STFfw~DTF*r~!U02jfs9-X{tlE;YY;1ltLW(*pUzCA01a<Bz
z(*>hYcRqdB^`qT4K4FQX5Lef2C8kYuNyLBzskyaGprAJ=)dI)4GO~u=;5HC6a9AMx
zB!r5L54dd%UAyin%L&eVt$Z_GG&}-rR~LY%Z=c!#>jQfnBelZA>v$4tJ<p~+)Jee(
zh29;YTd@or@aPQ3NazaK@E`={{J{XRceMC90%2H?6FqK-V$vJ1$hg#Pfdlh7-nB5)
zukW12Sb{+1Y7QHr;vJTAILIW3M!8Y3O0H4Ifn^GYxDzsKU$J3sQ)dy}PPJda7Y7td
ztf{zSwo&XC_45bIx0UCf2?s9^oyUGz2RFv~*Xj4dS0u2tO%hg}gLg4Mdu()%ft8ID
z`u$?yYPit52OB~ei!6(Y#K%O-^71rum$;J!xP<KHFTH17eE~&&0$~HD6>_WK2B7z4
z!<RajV1ny6K&%*<vR-a^;GjcO#@tz8b53%C-sa@bf;y6j4-$Az%n465?3uHOW;A`^
z-17_N`{ECO&Kr6~p7+`<x!D`aDYX`5!zlg@JL4_!fi-*RnCA}_dl@SNcdNGvft-OM
z?-v0tGl6*!K{KxZSqg~rT)}DRNDM91D^{3l>YlMk*<$2qJB$9yuF2For{iq(WNI-Q
zUMkr1p(%9)>J&rFZm|knwhZ;FJS@!eLsuJYW~B=uxXyasD>EbIp{|<-k9+wpc{T^|
z?KN2PGIp$AV7A9vF$;%?_+-j$Eb;o=;G72Nl#UGe&R_QWVSjOfWP$4t?d7N_2xmSt
z`^_wbN|pu9?w<3266|yVaFxQo0$RzXpL%A8zR;nI?|~9*Z>6(U3KrP)Imh0Et)>-r
z5OD4(KlFFl?23lFUT-uCa?|7!#k7B3&Q{f?$xm*pmNtp4g0-KWSP=uWE8p9-Oz(~!
z`nqq<t#kp+aT_m3)rjp%8JQ)zD0W@td<7&v2Rxj++7XZI^bWQto)8F>whJzIU-|6K
zpEk&5RJL+7OCO*LfHg?_B6T&Di~@6j_XRip57yp4Jg)1!@4WY7L_@Zd;M}<w-Wh=8
zoHG~j1w_-FA*GJcCYgINpau{n0}z#k6}JW;TBfzBSCpK@O}5RPI~O7lf)NJ<9cry-
zje#JAX_JPe6|cL`_6a~!Te+*$qM~$_r|nabRud=PHYB4o&h|(4b3pn>5+}QV>_`MK
zzwSLh-gD0Te&6r=zB@&;Q{R&<F$o1{?HN}T=k(d%cOCcact^MoH}+TEiH)Npql;-J
z?73Kev9$25pw8fgzx`jv>aP3W)%(=Q!tt@U##C2)7?|&P9iVNx9uE(i=7t7Y^GCWs
zD#{qhv=CHnUAYS;og27YEnGif4PUzUKHq9#DmS_b;bh2D<iet<)<mWUdK<OpASB(4
znEHu>Vx((=By&QH{E6?Mg=N1y^?ctGBc-Wxh*27js17*7fi&Kedl#b7!_kk3k?F<w
zv7hv3&V43&Y;fv`H&UAO06L2ss-R7C*F^lJO2}_Vt<H_|a944Ad}$uD%z+FR;aDTQ
zzm9Hs{mW)mF_IQVML<=|-ei6h3`|qAi`TG5CO#`VB}8{X*gpgMx#YPmL}cW*NQL{x
z;>AX0Sa<5-bIB!NzeT?9g~pbono>P;%7690);~!M@R&@l9(ix<=!o5zcv-jz!H$Q#
z#_-GHfoLpa26U}-`_8lvb!*MEPg!cDtN7-B{J{UjMA9;CfiW`OMmu333-$!FZud$}
z;jLn1T3HF{2Z$s<&)u-zgeY`P)H!_3N!>k6!L7L8c{S5W^=Ia0ChHGOH}$)&Q_z_L
zxg;N|H=T#-jj&*wxgIlnEKON2nX`u0FuQ<DY}d*z-WvZmYqtlA>1>kP&>SFU1Y?SD
z5H`ZrmZ@!(N07})(KrF3LcHOk7_rY%HMiD1!ippP4J(|PR$y7ScyiEw^sV~(0XLhj
zmzYG5nd9}0da51-31^`Zxa}UR5rl{lpjNrPX10Ip#=kqmVY;2}gU#KD7`j?O<v<Aw
zpkRCXOs!M0){dB%SB}P6y$}K~5ld|lII5Ixv5T3SBJ#axPQT;5C(289{MbT-WInbq
zbp*Pn@DE+{b`(1Gi4Aq5Zhra`X^JSBX0h6e97Z&zU>Dbw5gc>4sekYZqk%VVCe^US
z0H}C!81@A%z)B@tmT7u8n%E(VnbR@lx5DDpuXTfhv!-+GPz#Gk#IoIcQOK_Tjk4QI
z9!SD=&yG^+T4daJ>L0WotP?ap5uh@de91L!<Yj2Xn5^8!_~l56z4SpaLbhYm$UDtI
z(l=9P7K!O@%5nrYxE2+_zkFf{;K;e6QC;4;LQbIu-VePN`0lJ*)!uz`t(tz(^&Td;
zMVx)S;`bk%D>$!BBwdZT76uvaUUX_&by+4IAE)|eO25(MXxDH2$qz1*UmO!1&q%jd
zMIhbNF+;UUD}nRi=kzdJdA{Gp-wW+gC;*Z3#*A;LO~>?vyxN9s*Px52O1^t|Z^j)D
zHUJwqI<4WzOS@{igg(P{QM=Su%Fx$L=*NvcZ@v?~{Ufi8Ur)ZB@{Z`%2T6JNHYx8W
zzVQFb4kNqVZH^hNuw<KJX42+;mtsbixW7O#yL9X?CA<4>Z0r~Aq?UW|3%4O9F8|EI
z?WTOOZYXcxI`QOZyxSqRpYgUSZ+rLg9Io1>;5NV&Jh+|f?!E6&-uP=9oif??TBlaG
z^X8dY-J$P=+r9&FZ71LRh3Us`XS#doPIIOw)`zxD9>jLr@+oQ-5GtIp4p`mTg|Yej
z7?Z)HsZ_8MHt~+(KnzEdm`oY9V=*bMydas6Er1^d2aNRo8Ee~cH0C=($;oWkAWi4S
zv#;ZJHLvk7OXV*;{@jbVrQptIP(Z%@$Z~mRnn&~2@9im~(k^Se=X{Eo)w<If<?MiR
zkdo${*gq3PVIsUbs07VU0Nc#%(K-%U9U70Yy5y&UnsfW+8ik}1w$o;1AT1tm-0QE7
zt{<#K`#iLnVrIA_3z-K;o0;Ku;1bhzxT|P46WNi)lC-O8*v1rPyeN<2hF|}O?*s9o
zb@3wpgBFI7QQfd)ba@7YYdX%^RKf6%p)$K}e;cnu({5rWe8>&4U&BL7j$%Q<^%;%+
zmY+tdw(8X%5I_N$N`*9jO{a3WWY;oPOeWLwi39{iRSi_qbfCvL>favufuv~TKeaUq
znw6R%>6VzMxb)d6TdY-+|GdZ!;jnY@8vtOx-)LPDmn0=K{7|=-jqkF1)~n6A6S9lA
zxNdBa9mAOh#<uFBum@NR_d{Pld0Tf!SyWJqZuVbo8c(xHF|?*Pp(?N|8Fr7`x{MZW
z`xO`dQMTJ>)iz;`#kKB&y4WCc9+1KH(-~{<yqhn*iyOkfmb8zh`B-$f#1Vh|U`XfH
zTKuu}vvr+r%vpo!yLDyjL+R5Y_J_I@%tcJWc9+Pc6qFnQ5~bLm-u%S-lAbuQiwH*(
zJ0e0iNm0Xn3}TF8Yg%FI29)fnU}g$(6cU}+U5u|MTf)+7l6JaT$M289HBzN^WbNXL
z{|?bw!}ZG{8&$=azbu*uWfNP<DP}YC*s5wRP;T8tG@k0a%O#hOK`02<VixA~e(;!O
z<WFDIE09zuz7d6IeDFM3Qk;^`w3`-_a-;QmV-8YBZNREj`W?5b(m}Zr4t`B$=T<y3
zDu<6I;p`#hAA2Y|_Q2W3#FyO6J;CTL)i|69^}c#_@Pk$r>~s_YCg&3*wl%q|<hl&2
z!)fVqP*IiQt({R|#^P8)^O_{6)BX}}?Ino>`u=dFKP{G9x>K#>7XOAwJyl39`YY8X
zX}9FYLBl~h4XP+ptGX$R2aXMdS|@|fX)*4e^B;;pu%x`UqC5CUy?tUW#<M<M@#E8h
zwv?xaU-gS)2*@cfuSzT4Vfo_RrVRU0)Ye0_VyO>T)qndppiFMhxorcL!^>bjwG3#D
zj*;K+t4yL83^8C0IkeJ`Dc3^=FQe-<Ba9V8btu|ap29c94$|7F*~7tTw`$gh47QlY
zOEO_I!K@vRQtdqG4nsLBBp+znanJkz{##fHY+rz_hB_g^0J)9d>{>Q>A`3yY2JHJN
zuTfMPjrm@5FympFh2f#bUh~z__?%x?MY}enJuRfNEmJN;WavDi#`s!w^s8z(VT0}=
zy9t09u_I^_#u5h1*gnw>Y}2Cw8VXMH5JO;aXA_FenAH4>Aw<;Ezza?6aI4L^*o5cH
z71)B{V%dt;n`XO%-Oc23$X47iXcOxMG|>vxb3ge}XI8Qgm_16HO&NYtH_u(+iqo>-
z>b3}LwsAh>on4^|z92%2pmo<;9u2SR`J6bBYX)8P8ixhNb96GFTFq8!_XXsBURsp`
z;_aY4o{(THm+AHH6#~YIw<^MX<PEHNSeKDi3vPY+Op|-VKW!R=+;kn{mf4*&twj4>
zck@~)Ku=(pB2*lJD-;X0YB*1<E*<uqYcxw;G0WHTVw4cBK}dbmuGygnuy0kkqEedy
z3&CM8spsrZ{IGM5PdB;6ozti(0qk`Q=v3pU@x*blG$*6Egx}Ue6yhnE6{3-*4bguv
z+9zsy$Gm0Dig=#A#zOhVf)t=Hp(WfpKOhS9tjfGQ6$z1tLkmdJwEy(|mNXa{`vwNI
zk+ALE0m!P1%Lj0Uy~ggbL(wBEV(@Oa&)p;&=%URX!U<UqKdGC+b-f~$-{*NX$<2@#
z{;znho-W#1N9>jm#p;Y~-pMo17HS$>Ks~%M^iLT8jCdPwNKrGo+#CV*7ulAE7<9ol
zh)I?O14beZdSw;cWzQ-kmqJOYH$+Rj=~^(+iPyXdz&AH-D9_3UuSDtz53I|Tu5AwJ
z{Src09;D5t2~56<Kt=ZlAN|Gm*Bp~ofs32PO4B$VH0{I9$qF%THAkB=y`s@++@#x0
zXRtfe6A=pzY_pkRxElR~%9%~9qDzy;Ir{kJvIy6>+^}7R92Z(&&;Otm@Q!)UGE=NI
zaaZUDo1tH2JTOa|tXkN?yiG3vun~RO7gEQax$UOV1oL=dg+*Z6gILiTirSgiHv`pl
z>KFc97bkoX4k1_;4+DE@=C6BKSQSc~203!r$9csT`=xHDS-an6OG8qd4q8*Zq%u9-
zF=MgjPT13AUl3N<;0OTGFB)J~IZ?Rg0=rtb|8K@OhdyN)NZi~FWrtteb6hrtS(Vr9
ztafTb#sFN(QayPnQiC=)rZr!5nt}3cU8(RaZK=R11`7Qtk(nMzGtHx!iDxk>*qZoZ
z^?deU|Ip7zs$8J-X%Uy-qU3;w!pkZ=hF=hu%nNg^7tV-%BD*C-|0Qvqnu=NF>QZ87
z<z;zhUOfMFbqamIzb*5R>oZ$Wp>Kwwxf1s4YptXDg@e&>`X%v1@}xdEmH(uBNWUlx
zs)L8Rb;$PPz5$Wti%+;a^_i7%FBkE|rC@mC6xU_;l88lgQI-QQdr4l6R^%g>gj2!2
zZjZZHg26xj!iP8rgmY5EE|>7#StSg#-xAbxT+&yyxJZT$0!RrJ%_dn`eJexRma?;#
z<)pqK)XLDHKSX)P>~Zmx{Jg%e0Rz1w^Oug5!;|sDVWri3?Cc(WX=WuVtTsNE|E1AN
z;nI|PcI9*X8mb5sw>sCzuSV^`s?5jQEz@3kMdAr5Rzy9Y$*#(5iy~sOGGM9E_-MR8
z7`$?D@V$rUic|RB??z}i<?!I4Pq8cCCYa6md5|t|`v<M|z5INOvmtIvMJOyUrwi1|
zAPVUA&x;r`Zu2@!{Kn60gKP(%Yq`H1KP(FF`S~ZM1XOdEz@_4D{NGML%h>#QI_&09
zb{iL?!Pv`$^^Ym%(Afdy9^nsfSD@-qc;{dK*4QW4#0E*~0ID@8+DXw?xr=_byY_Sg
z&Op>%fTXtYT1p(*lo+n~2G{EHFtJt7O(~yiW#x6~OWsa*__{nk{w*o*dBy^7yR<sh
z-nS9@z1ZX@%YN@KtC8DCn>yw1^hP!gES#?wUJ~sm4X<rY-SbRAZVZkbSbgWvKQ560
zbVS{Z8pHpo%8BK|JDC#M7fWJvo=y2dH8L;7gCK5h@2|`C(&+d_dA{TpFIAuR>a^`?
zYCezL`qq7G(7R5G7M)tMFZiO{#KD<~zyRM)m$umKQ2bd!AqKZurvusH#O}Si2t}vM
zAWXmvb}#Sq9`U1UU6`JjNZ#KO<T0yl&B1cnC4sbtgHCyMr~5N6i8vhI5#z~Od!k~H
zixG9rdl$l5==R#MXx2(2PTeiI^^FpMs45AvYq@Vk>m?dMt25Np09Q)id_A*!Wx&0z
zuPt$ybra3W6cE<8je(}k<39f2NUjTOIAPd_6Q}pMyjiV+SwNied%^R%ylu{zp-)Zb
zpG*^br+Y#J=2Cn>H}>q5+0X!wz6px;S%Vam0Cbz!aQ%2!<okQP3<&9Vi`f(Wv5fCu
zkcple^M*^&&4Gbo9Wg3ZikpKk{ua<8WFekpzCQCqciOE@yFukrLyKU<+3h*%U7e@V
zloUsia^4VcE@Fh;V0e}I7%u}}{*mu{`wTa;_m}I8bCd3gJjh{hryMRUnkH-YGZ{1>
z5H`KtUd|~0;V65Bl+xf?eU<ITPT~l7^pDNFJ~gl*eIu!^Y2WR(CRgiIM}}`bylTXQ
zvE>{El#9Au{!v>SgU2-p?c@?5U9FRK#ZHnP?~_%F4_uTcR+J#t5^o#s9RkxtF7$dC
zP)voBVuW7Bg$;q9+~=JdUpVEzL&8J<P&*2Ju_x#FA|(6Y&AB;B4f^#Thl(j~1|~>(
zir{IV0YU3qR}aC3e8Y_Gn?Lr0g~+|++bDMzd>};)f()j}Zn8kpf#(OMfk(U0=>+sh
zAUc~2heXfYXGsgpdX*r~;;E|tT2yoz@d*@<jEC>J*M{5)MUcUrcQ>P*UWMbvo~7@i
zZ)_Mb?Kv8cIO52N6CvZo#R5sIk?H!HB3)xW{Gxjot-7v3HsP<mv;EtgotR{kW?j|n
zw1x&Ms1(Af%iXNraZQst*@bR_IzZ~4=UNnE5&0cyZ>O|08fGR%5o#N|h_lo4M!@`g
zuX!78L9Rx_FAAE>!n-Ju2GQTi8q|`C)nMmZ!{v1O3vY$JR)HFZG#Uomjel_oHv1bS
zOfmnU32QGr!GR08tA{NBa@T%|b_a)yOh3d+0H%o^|J*!GGM~y9ha0RqD}6&ah2zmy
z<UbW%6@lHqDyf+xo!<7mwbK)j38z5+@RDpm@x(fkwiupb1Q{)_P_k7)M(y}9x)1gR
zYU)}eb6bc7M44asQ)1DM;hl|GAdQaH82U5~!%@7pT*Sm3nb#T{pvjyVoUexN9ML+<
zdSixmg_X1z``z&gEDpm8QN{J6)=+?N0^-Zz?qO}Hk-mOMCqgDRns%)tF@5|CrJxnr
zuDjT5*~)*Nv&nwrf3b57R7~y#-5*N>q8RF*dn#?xdP&3~!emY>^d}G0f~c<hQyh97
zmyd|ys2d))!Sfp7vQ3cUW>j@GwK$2rb(ez7W@>HgF&8<OdO8r%IDSHu+FCot?WZ;u
z@>tA3C{8`<zxD5L2A}`)buPA3+T8~I{sLZie%%ns{<l}ZHzX7&?XLp;zVLl7LVW69
zzR0(uQ~x4z`1$X^kKc<No;5+P+ZVYMeosvbxM$y=j7A%8BZu*xJIEoyvJY$rxn4hX
z+%sLe9^bwYh#_IF@78Z)e(%=r#JO$+U;l%L&|bGSMjK^un~jE|dHbPJ`OKR}KKN@b
z27-Z<)|P{}|F<n+{?d+B#JC2Lv8<R&U~R=F?vljzDr0`3tExKWDe^j>{2^BM_VtV0
z_x6J~?mSF8zW34O%6R%MB#J%j`#rw?tM4C@;-4EsRr~1@1Shcs3n*vjsC3<echo9V
zGM!LY<qt}GNy(MQV~J`veBc~Bgj-d2k5=<1vXK3+KdZkw)anfQJ#roI)E5qVv3f4o
zhTj8;tELmkH8bpijchWwJ~!C$ih&*=bzclatx_-AhueYgjT<nuYZTGUrI!OWxEdTz
zMmOBU?zJV{;B+BvMhy(dqA^=Erraqn)eVjE&k%Ctrp5YsR6<wZC+&PkDy_1Y(MKz@
zS+InqQM*}sTpJeFeY(p4O$y>trQ#jqNQA-><~n2+i{zTz9k?Q_Vk|Is(y<~2@YdOX
z(4(djGf?=uefSpMDh0l`L{pdZ{%KyYRX@yhzl}v?ExqiiVoI>pa>uPMt0=s_pyEb&
zf>6Mw9agPuI`1t#-RLU1rWS2hb*)7eUkrO!Dcy=UJNA!-YqDY~Ftef^%_eTtbVg+*
zfYmUV84Tv*aCcCt4{sg3@w4Y@-J_f=wYyVYSlRA~N34xaIrMTc>D37?y07gGqN%rt
z9TfTmXN*7im2j@L?DRI?*0$@d7VVrpd*VZ`Upp7>bJyfANkSqAeqIGwfIM1Mf><bB
zmepa58>|f<J}tqFb-%e4M2A<ro*~SpHQAh+8Fl<Y*czix|LhNtpUuSr#O@Jbbq!>X
z^h}|au?_8aHt}1DQWU8k4D6a{`_)4z=Q=ZzQZM=ZoGBZeZ#gg6dbVA(0e3`eMedZl
zKy`y)$#G?YpsaX3AfgHztOQiZ!8UGO9jdxNMCs#yhWV*M0=+P=dhUkv57uS8YMAOx
z@-ek8268SQ)9#|&5?{TJ$FZ;yhD)sj2QBZh1T^5sKAoH-3HMUTTlz92vZb#cUzX~t
z(%+wd;%(nKBfgnj!@&NqKU9{5N+~>%Bl;RbaM<M+23r+$p`rQC{`-+2K$DCW)kiOT
z(Q3-hKpE}J1LN^|H!37{c;ov2UYv_}5lnl~C(vp?{Kw_FXs=E6<SpW!yIjr--9L4?
zed-`+?;IfX>AkHKu=Ip$T@VLDZ`sM31c65ZTfHHe1TT)BE;CO%^)OIPs45z#P6OC;
z=-F6H+>nH)yZcyjVU=p$mHibFVlsK-2i&MuU#&b9gzaFz82@U}99#+X;L&6b%Qffd
zPyGawaN09?AxqFE8D-ty<q<7z?Y){#>xER?DOtLLjBa+RqPM6W7l^VJR>VCrJPjb{
zd*OYHE+qlz^(oY<)ZXjhJ+R?wb`>wh2jsSWMu7%ts+=@SmpT0mXwl=SA)vr(Qn}yy
z)EsxlqSxDdq+zWzfmgxrnjIjsQ7vNjy3^DMHHAX0+2pk7XJHiSH%D=g)Y7RD4uViN
z=Bo&->q`(9pc59E3bC@gVR^gbFc1ljQ>Vp!{i(efYzAq>eXJYDf7%*NqPsPLqoVhm
zcQ}f>t626Z3nVzP*yF>v;eRF6Y|Fl?bpuc#mfDKLK8f(NXVb5ceVEWnI+$rf6{@XA
z{1uKlO{Zo<kK+9RZ=KnhV)gaHxUkzp;_9k+8wWL8vftDHHNSTeSk*9=V6~aPLuqN<
zWi?Qo=2?PAlim=QDTFdW_-6V9OHip|-PM(7ITDM`ej)SrjN#?>NEMW%V-_Y`3<`<i
zF2PmoH(33ssfOKMn3wfG``7j?NH5++4k6bcv&Za6)NA(G-6Vos@pcDck9Rd)_lj<&
zxC6KwmVyTEqGI`+zThXNqatfI$!vzyknxu9E!n`=t~c9TvqkABwl_0ZgnpPvWh({@
zB4!cBEM!Q7m{@of7M)3V>DKT3J(^4rX3@w9jzn`h_5?CQ9A~Fzr@UQWEvQFZ1A`1s
zGoAx`md>fEeWE{V=kpn2iW)dm8%+vbulk41sh;<r5W!|Bl_BmGnLSlJp%qhPv^-w$
zLAY!Ef{U0&^t}JZuZ{Ms`t_;Pgxg9IK4dn%C_9w`NG@bJ(ZM{XM1;?-=b(&Y@&<em
ziE%ya&|(ZuR*cU_MaPYyF2xjt-rp!DmxO}!I^_6jzq@<hii^Qr+-D6zfro0QAJ~da
zC`IxfE;$cTOs(79d+SsGst0fn8q*kI-7abYVgFIy#<6c*sXsuPvecdx4N><`!$Y!N
z%4ox1-o~bD-KVFPqv)D&yncpu2>-#4NvWM#&pX82Xn^|}uNG;QY1+(z301I=UM>vA
zZ^i)Mmu3Cz3*fBK<oIXA9)~#ZpF@<${EGZAmdyn1+Vb<68B_2bAT`<1z_lIQno9*u
zXE%$wd6bDoHnmf=8b<oKAzjB7#||J<qj?&PN6t?lg7l|(%RKg*bgpE7a6ur<T|Aep
z7wj1EYjc|dZ^hDO!c0~{`$a2Li@KGV5cbKrhDw3GHS-HHZe?xb(@Kn#L3^ZEAx;2n
z;QI(^MmsueTT#(<e(k{>3BY`Y800b3GsBtmU^`hoHY*8)n$Hdg7d^*d%}7I!%&^di
zr(EpNEuy0VCuNxS!~makBsK+r>0|?`0!(#snYsmG*t3?5GsSe=s@+WbYq1$`{?#(|
znrGKY9I2P>CZMDJal1Yly*@X+UkW}i!m#IBQn$19EwS8=Xw;$#0x5;C3p-MRqvPVU
z=Bkp88al6n9%r7rMGXAN+zzX&$>G`kYpw2Q9~b(Ez532AZ#C^b;?>9P6H$GacjaTz
zRWJJORlE0SbT#MOW^s*Qi+S_W&y`mnI&`#Ne`xOT)Yc*0+Ih^?dy*^p)#t?EH}s*4
zGuPQcf4_A_TxeWN=TGE+&nsP-=^I`Cr2E9VV^2JP|GppZ^OoGO{mAa{g`X;4p2|Wv
z_xhq;5YS>Tzd<0JJKY@oB}TFWBRtFnD}g_r$azs&Du+9h?272`>hT)qs^nyF{*fG*
zIrznoesF51?(H8xE@p@#>YbbF4WiF_ez~`OMjY>*i9B&NFFxJgsk7}}V^_z^a`!;?
zO901me&5vZh>ML|(i<dg!G6E6dVjvPGL^kI-zS&avUO%E*SOz*{@`5Sz-L5X)R%ky
z-S%qvc~Oq?PXpy$FRvb_Rlcu2B0ev7N7**0l^U)m^^2n3j-D>Cxt2QKaLQ7G<7ivO
zj`Y=i;++50N3^=HBXOS)c;k;cY9o>#Qor`e%;G_jYA*|^ort4)L<aRK^RH+Eakmrm
z<v!kz?MJd>^Ybn5m8tn;;Vo~qT+!S0Hl8;~<q6)LzKvb-6U&FBJyBn968|_Z7QYo;
z<XcNy5%di|yi6sAZ3OfXhNX;JiHyn-NF_!5+_eB*Jyce;Vw`300L3{ueBAfXaT23g
z^mO;rrzw@a`E<QF^}E>IC$`3@XOT|r6z-!(<D4PG&Gfn_I{)WeNA8IxpC5Zkz{vaB
z0tFd<!aaH5A@5P($&vWIDEiFYsqi=Zd*3V1g=ZJv?fqlmhTnHz{^^B6hpc?f_vWIJ
zr<cz~`(7Hp4n?eQ5IAbr_#W@bB1pq9%)#K{cu)3^tJU7?!N%07FxWG={x@>&O|Z|W
z3DPaSEFSdZJx3PTMLh9kKZ(xIbAh!|$QFM<3?3B*TzOocxH9(ZmH*`X@c0HUtU^+x
zw8xRx$%}7~?N!%1Qyj<t^#>oA^T=lt9T)a*vi(cDNLbrd4?J(-;}N*W@AMM&=`Vat
z6pr_Q{P}!x%ku!dl4rbk>+kOTsc>d_s?Spk;g08Y_FHoj=9__73SHUv0N&!yMb~mK
zm-X2{oiiBA9`BXty{cajH|5-kWMSgB#2;0w!Dm34x!IEkpWOb^$YpnD@MO{v@lFFW
z#uLbzp%JbrHX#^jQ8Qi*Mp{$Ly`74QW9&l=c|Tg{ZcW!ybs~9{IN4jDy7<P?DcNlI
z6O=wv2Xm~CrER}=S4te{>yK*tw?B4-nCIt-P5$j~y6feKydw|^>yI+N&yg$e;pk`9
z>64++eMT09&&$Kkq2p3sT|6Gmh;X@6e=@N5cvqr@w-=|%C9v>;<LYKu?YT4!;B`~Y
z-Sf<C%=g3baH{oZBfT!xO!TT%F~xPA=6ZI_<Dfqngzl?v6J2{!y!vsWu$2JN7f+YR
zG9l8F`{auH$p7^N{-<W7e|V~HO?tZs*o*w-=uyvyLio4IJv{aHqjyc7^Gp%te*-8-
z20t*Y7sVK;a2PJk^zISAq<}V$6zpBmW3T$XGI4fAdvZH+Z;N-mfNX~OhofP8!aE**
zjznWWOzyhH^56U$&$S#m1dTHP5%=@c281u@t7>E3^>;<tz}fCe@%Fq}BPGsiKRUdg
z^%wq25Fjy&pO_}HS2T^NCC*ry%y$OPsz3ar5BS8yF1&^UGP!u9SCi+}fAt~Te{{-Q
z6VVYO-~|D^g7|G}(}=?8d(jw8bHtwP%c{v#h^t~lozQ1L?G{>B&mDC~p7Gz-?}B`u
zM6fmv4YxXV4+fvMd$+=#o6itDzc{gq7#A<Ocl82m_FhyQ!hb`gC=VS`gl&oQ*3czk
zy+x|xE*$QZQoW0;eRf#aYaBM$r7i!}k4zrz&9Xyer~^_aBsp>?+jS6Iw?<e$k<t3N
zS6`L*{)Wq5_FeM&UWl|ETg3oLTV!Q?Zv5_%Z|FI%PgT>ioukE0T|C#ig$K1b9g2L{
z!auANC%kYe0{D&WO^QA@r91-IiqbUF;_zg@03a_!8wxPh2t5-|CUFG*yrRDF^x~LT
zQGfW#2T26*07WqjGTCdt`td15qh9C7Dq!iOQ&f~A&taxEMGxxX<Q33aab$|T0nxNI
zu~A>>esbf9R#cV#JF6Rqp7Os*8SKo`Rlzpp8Zs`7Ns?}+&W{F1+`=ezqc=qF)zT}|
zFNt28jpzPX<}-*!f9k}X_~;;3ak`Epf)=<GAqnhP|8*U3j`qI#E6T*!rU>WQ;q=Y7
zx*xbUkOhi;AhP^1xR+qR2G=B5+V!|e&9)AMGS^`N8b1Mg?EBvF(nl88j&Ay=N8NY4
z3;_GJ`Uh(>`H7d^bOO$3@5(&YUMhVt85k$l#o0fK<G2uA1wh?<Gmc_w&yjw35Vh{%
z9agiesq8V$YB?Abr(Pf0G5LCt`XG}GhZ^(FEA^_kq4pg5p`0Ug@WINykruD&lS$u)
zPv}oZ+<hx8%E+#!daaBy<W8imF0Y{6#Uv5`L<Q?YXPq}1-PN>}Q7L+^SK6`BkhO_+
zsrLS%uG8_n`{B`f_ePX9!r}%2>c*G{^j{;m<fXD3Mb+9{qdU;i)n=-~h%oxGMoJ!o
zf%MjiZ_F-w6j{VJAjf%K(;&NccGQFkeVj2{#o709MlE**O}_5srNMXwF4LYD4Qv&e
z`oI9oeZj15WRE7Uwa=7QIhgD2-#D0_o_o^vh5~E{b1j3|-lojkRt06TsgzBD6CGL~
zr<jT{J!{TK`?|hcLHNtBjL#?E4_P&_xs?4Kz8$0cs>!tbtD~P-z7wOnC%pr%LdrCZ
z%CDHq7)IrTcfi$e(=wlY@-HXt`}J4(@|_%l+ckfu{#sflDFn?$&VFL(`ysS{HOza5
zAo|x~#dlglE$wZ9_B-hVH-f)&Y_<{Azx|(8J4j$+w@F#qjcuN8VSXr0sZv;g>52Ms
zaHY{oUuj&^!A3-J*o}B1c{g33jvFSZ9CmBQ&=D*+F2LyEk99T+baGbUod*$2<}c8O
zhTrhNweJsjQp2>o{XoBOZhymApuEKM?>@G-AC&6tS7IjkyN~*J{=D&C-y3l#AsIkV
zTeK&k47Y4UU$Sd<6MjQir6{i@GEpk|Deo(x*BKp;7GLsOHyhGB>E3r0@yol7pR!LM
zE2^w)VLFADT7J>pEvqh7uk6$>s6@+u>AoZjpLcgFYeG8v+`{h$V6F?!8K>Bpo^MJm
z+p<p<=Hb$90vGk13x>BmlE)P1<Gr@{xwChV0{3F6X@4QL`4B!sx2YoA1vrCZ2WbVP
zayN!uv-g`x276=rbMY}Kc;x)*cjDmzduO@^y~bCD98pZJtwi1Ma>9x`O>oY|DQ9}<
zs4Niex8@EV4U}t$dCpo~l=wirJ{L7}B9SkW=7r#6-L-71pLgE)@(&sO(-@zGxca)m
z97S^xvvC+Z)!iTHic$~Cp1U#LmZML*0I+ho?faG0(`c?WdaQJZo*qly5$Z))tPt8l
z>rkAupv2_JJ#}6#JK?b~?8WDpbYcvqrX%_*fdY;J?YVpqdtBA2)AE)75fpekn6H^=
zZGVWF45P(18J|r2VJ$kA4BNw7VJi{G(oO$9mCmK!gbuEVCZ!0a-w+kXxpZA8^KKLL
zZqik9@GHue@_t?Bh-`|vQoVOYREt0%@IX=Eio|DeYb-`~q^*XV+mQQ60GO-<P<e~w
zlM2J>8^8B2X5}~o2(!v<n(8lxp=O0kq#po+@%_{N#x4(;Gfn}2_s~09UBNvUy0MjC
zh^hR+M8RRL0EZE@s+95@IrX^OFIhCJyax`?7Dk7Q-~e%|sA3J^(gHOPf$8?+6!`j>
zqg}X|NWNcegT@7Lg`t%Bv+bPN+mTwNCuL<+UJjSnW!ef>{Jrb3+q&XUT+>&k#7TGh
zzAc$gl1~yX-IoiO)a7!DORCX5uvM8Qk&dfMZPzbJHRm=T7yI0Ck{XuXJo`TE;Vu`}
zB}3{~Mm3@w4VL9QNqQM(C5W18wSe^Yk?qQ<Hg3F-2DN!zG{7nq-3SKjrNQYqc*XLT
zhj=?JQuz&Ebdz#<`BKByPb|9khiXX@q~1T@A}JFaPNhODv8xM#Q(^QAiHaAKZz#K{
zMOQ9(+CA@9_ENjbZIxb>XOMeUkzfoe^alTy2rE{!Y!9cSTX@{!gzSb~K@q@M->cT;
zVdq9a`HYth1XaWft_@OQ<D0cvK;-dKWiO@9b9{F;fmFxI1UtxLzTJS8L0{YKLawv|
zCJ}fcaoy*nL$<jRCMTC*D+4DS#hVV*u&JG*8vqJai}M7f#o^cg;|}mHtB1gqh>PD1
z@CHNKJ?%AV4GCv-7cgUOG1GK<78zN@OZkN06~S~s%iwMfk{L*Wu5L-s-z)KL?oDi@
z4zX)!Broa6P^`Jf3^i?-J=F^+ys>E4NvzrgRlWDaJ&OFt^m=>4HFcCWf$X<;SrxW2
z%`QLnbx$_|hPK&$l?R6$x3%G!MOCvi1A{3m05!z=v6~dDM&i?@7<^69^{oKSrOHbT
zxIwfYl-B=|t@%^{$`MNfqXtGbg!c@Ud?h!~8WJ)PIp{GCBaQc`BP$4dbAYX?nQ4H?
zfg@Q}wOKCNus&UD&{5J-7Sy?1!#H^JwqWY~{&{URw<JJbG#mGFzJNbkH&&kwisKF|
zgl&KO(3p)ZW*jCUDfb+A7{^)D-cPMmM-$g*4kgnIkgk2A2ujCd6r-_r1S7{WWOe~C
zsqUg((^{`1GrY{qux#T@*pty=q$kq{+#9d_WYd;@%}WLOCH9*zZ_Aw}_#e=$7=3LB
z2H!%o=y?09%MQHl6h|_bKON?sqD&ITm02rt>3u8$gG?d-l>ebh&}l(5y6&px6OdAN
zmDA#aa9kh1bk9~GERA!f<rHr{{Rh@;1n^~F*`C%~H{cnqx4nvCXbw;D#M*?o%WpsI
zJ4mt!n_*xS6^8@2bX5(c6upe`0RQKf$`Lr?*p~q44EH_XC8E$hGe@1xv<)J;?3nr&
zfA_yPtI3Qs$^#<BpR;V-2$IS>Js_8cC(PTS!bO)cP+t=-tbqn;5UCRQV$nuwfCsbM
zar4fa%j^~tJSG*$h_$IkZ+A^Z<cMhE+nbA2bmJrc4Y@L{X5-%06QC9}(1^9^kug$?
zY6&#RsYVbM&zXre&tRv*9TY&a!K7?z-6e-<7E4?@Svu8(s!Q8rj2)zeRmTEBwaHjF
ze)--SqvBhUxl+r%eMO-*4Ub|_Ivn~i2hDqyHIL;s0pJERss<uz1$0dDWe5^Qz;}ZY
zB5SJPnyVloMIG5JGWLHbLdN3M`Qn80^R{K6XY`#W9e~bCC+WzF^g{0)*Y=d=AaJ1y
zcPTs+nvXQO1>Nh>iKZd@UFEUvnSJOwJg+gy7Dpqtrc(9E2A(^v&cn6FZhrlr)-nT}
z*+?mELO8TJ=hy}K$Hjr&S%GO7Hin6xzMEkPRWVap^VBqsLY57;Cc;MI?ci2xZYgp$
z%U+Z9gEPvq?z6eO=X?AhwS{q|Ft|;3@z&95@C#o3m*i}edjZ0-e{?I?2&H6F^<gQ?
zzIa}PxE>QP9FY0zWP)CoB-1R<YNh>sQ5DbI7TS7tZB&udUTXMrDxBUu7dQBUn)X%6
zy2?iDvM9=xJ)CQ076LGxd`GHQV(6Zw1LZHsJ`%M+9d^s2Pr@L6QM#2~VYVW(XUe+=
z`YZV}kDtj;NBPRVyQ)2zC1)I0sv0}?=AYG_O*i+!Vw9QPA`mrobBi!bYu&TDwIz0$
zx^&BJv8%dA-;#d*x_DYPe!pFj&yTjn@^$^DUjgbHgo%n*k-Y^^rHuRaH{4E8eR57b
zU75+k99OZu53b1^hwSVD)zl>!CtHRTkJGg*g`1tvdMXdk+0EL02-T0v-SRY@uJrz5
z<ez!GjlJbQUvkEflh?O`(Uss+2iCMn|A%248TWy!n{!%IH<%O+*R-K(0%WS;QuMss
zS3N1bJ~?>KZ$94A>hF+IP@DP;7+nM6{NOO$o%M>_cyisn{bLR38ZLFI{*JuB-b!W;
z18M?wlDg^+?K968yuOm*e)2)MpYRw_NI$l2aJ{pv!-bnN7`CIL6NST5I9zW1{XZlB
z;coK0^+)hSXX@|hsU?D(Vg23Y>ldh6?3=jEuai~ma0st4Bom4deH8pmpiUaFse2~~
z=-KYaUh${S!Lobge7sK%L3`W-M)P3)hBOt4`#&o$R+G8aJ-H2Fo{QymMbV7D10#<}
z3dPDjYW+YE6B_-Dsq?#D`sh$}9c{$kCr_6AUVyq%!3KMDih4UTy0@c91z3(An7-$6
z0|l!6>B2YNe@N}y3nBacx*Yp>z49BscGqY`wC2}DAQlO#KFPUbLQm-yYY(`H^0A9V
zqE0SymjiC^mOPPw!S11!>nUPDtKmX;9rQLl3s4NU2SX2j;V&Omrmh2Vso3nLcJ$=S
zS$ZSasa>)n3#0R@Ur)<j3TVX8?Q*elwmSs356YyP)J(iB`bs28gu~gT)}%)itO$o8
zDE{_;Kyf(R7;vl>ePCQ)g$?(Sp&$6DoKo^ReX(C;^km&P-JtPgAtP<LyU?)d1@MHB
z<PD5WOAIaX%|)lTbAU1zW>QT14xG@vf>9HlCkzXczZ{5!J)J{v4<oyF(<LNY%38Zb
zc0(J&<cmU*43Bhw3OM5$Kxx75UuWXVRQq9wbk~}w-30Kap92Ghw*T9I7wGpa1W{lq
zO4yENPKB>#hHriDr)Q%Fj!Ce;h;)Tx0YzuGW0q-r1dzD^FA}QZ!k+@OD!cc1^}M(s
zjYQ3eT?QKNer#asTz@jP_zsldN$8_5(+)_N2MUHK3Ycd^j2@6=jxIo>kkkn_eQ+;G
zr9?%I*aPcoO~Cr&v)T3Rq{y!;Yma#GfPn(RuzJ8}Cx4Smipl3a8V>+u(fq?5^>csZ
z9F9nncR0$BQwrO0dz=k{lXjENkyLftTwlZ4G>qJZZ~4AyChv`0sxm&UsdGh`jl<3=
zEJ}&Ez%_i*G`)l5*n=Gv$d6<@(xSDq?mZ=o#7Cv|l0{NK)|FTBp*<Hg+`z<{MO2D_
zdB>%JNRJ0E9Z1hIr!<*{tA+0E+nBg^^^bmGKj`vvny3t91yW~oYSBW%i#AntghgIN
zKeBxfym)%Chu4O?EI5ob$nHfWKt!|duE-+fcTGS96812*O%f3iJ|)B9t{y!nt>GAd
z8!6=A2eS=W5J5TJj=;($Dc_^(iskq`pyAo)S&SU{lZ%A2|A+tllt+=2vBMca<}nh6
zl9!ObXb@I8W-W?p1hJD@?1{AVl(^`3S-KZxp*P|_y%K@tF8o9Gpmf%bqu4)#3NzrU
zh@_23Y_IGZs6dQGjuJ8FGI)cw-`kd<wUdAmI~pXlKy>v{hkS>8dLeI5zE1g_3^j`z
znO}Wr@`{#|hY6COtWPf1^dk(J_2~?!?BVVr>$K+MAqH)M2B96W>Pd0`4)?6>7p_iq
zgBhz766Pdk=wvzX1OqLn_qSklyOc4>O)D$+CO&hxo={7;pa~vw>aa&hKDbCrPAzkC
zGgXUQW0_x#H@9Qxxsl7K@JU0K^a#!dfAmQ3)K&#z(-Ub|@9SQZs5U^6PZ}!e!zqaY
zH-b%{ydDKi7_x7UI`_bbP($|VQNUx&+c)Mz8ik64>YimEg>$Jn`Ks<4ZpP|Y&SKHA
z!1~a#KXTG}w&4^}XCfL~;x~vVI?)yyr<m0}z=;CG1RY&*FZcAk)m(RJq_o#?tD6Il
zX*XogqP<P_G-HV8cbnDeF#=e_d@~Q9;M32_Dc^#piAo1gGqE@2f1C@x3nt!Y;;O$N
zn0N;Syd73;K*aB5NB%`D5mw}U@<oFsg5doQA>Q#9yqzW*`uy+ajtc`ys?P{Yi2So3
z-@DKJ9yP!BY-bJ(_~TCb;=H+n$@=%FcZ!mnxm^SKczL^)$Y;du2yI$sYLX0pZ-ee6
zAS8$2zCTw4`P;bzhhB;9#ChN8*PY5Hd$+IhiREo{^Lx0O6o@m>XgqQ2W4nT9y(5h=
zaKxELs=xCeR`x=sMzF433opY3>LIBdORPJ$q*q}x><&+{a6Qqy3_v`K29(5DdOT^y
zZ30jRbyv?e*$Of|(rNy|qfscMMvvCZEPsTkn7Dw8AG8+geq+Y}A3pIuqvaY!+Cpr)
zQIPrfS3b~Wzx&|&w;w4txbwL2uXdd_wMBYRiXs0sZ7f$&UyR^yN;_>{^fAK~w!B`N
zU#V@ltdLpl=e|~by(AA{VlL?8zKrhn536;z=yoIq?`5clRS*MdA(&Mxy=qo0&Lvg1
zIs;iyyC)?H{gXsz;0=JC$*K#;Q5j}j_{A9buRBAnH^<-n)w_nYX-|!2!99R4xfPgn
ze^}WU{1t<)RnuHGgsQjXw49cGrhIHoR#J}s3sRS5aV|zJS5{AA*n$uhu>?VxiY$mU
zH)U9CE+z0*nTqaZb~%}>6U|#s*QH;rR8I%XiR=n>LD`BN{g(QuzSa95to>~EBqxe6
zaWs~9(@y&}*esz7jEfp%BFqq#z|}(cYhA?^tlX%(g<X${os%8;JX@F!i;_vzPPi#u
z(i1sKEC4z+ZD@4{+Cec^m^nT6tP3L3T#2A8Bwb5M_pm+Gb>p>%nDxdXXd8Y*9=01W
z;+HZO!MnP@9*Ph*ArYqN{4+&t{V`|1@3)BX683UOiUqsh)$_XAdNz?-W>hXamvoMm
zl2tdA*>=S*30n{ulu%IefA!+-BKQ&zky6=fzIL>~Df-=(?jp|vPG1=@VGb}-Emq<6
zhchMu4YKBvt<zYW;Mdu-l}7zx8klifC(%XJ)A)&`=2ro>d{g*^&P}{1Yt^cvcyQsM
zUvpyBbb=f-wpJ86ZvAw$<YuxvAYwMlWvh6=ult^W5N|O=7(q6`Zzxa}lK32O#OMkc
z^^$doi}1z^N7)^l=@Gr!+-eM6VdoRIY6JR{f3AP|AjV}eqjd4JLHKy<@Z5>nM013Z
z>M79nNlEBjvgI#-b*R7MpUCxj)nbw+3|dV+LjjO5-S=3ymlUk>batOV6g{4U4Cn{5
zvf64_Gy&VmH-w{7w;G237_4)-W#_i!-$W#UWE2~KPMpEahSlsy>kt10M)sDMJM3o`
z?AF=PPf1Lum#_F^>?UeSvty@(fs>@t?sYc%c{8nD6e~<<<R25yiOZtrbN*aA>_5|s
z$*0cbz3g1}Mi?E#RHSGgpGqq7_456$Pm-wRr^B~~9?)}QZ}L98P=2KrVv1_1)#EMp
zn`VR+RXYzxStX+Qt3Z#TZb@_Mu#!(7YuyU}zGbzog^cGeV}8L!gIsDhD}!M}lqI(!
z3zeP2iP^N21_Wcpxy`q9!pqpl1TA7A!+B{N0%7QE7BKMH<9HbJnY@M_$=ON>qMA>N
z1U|65!UvxKCh+LCAo|Gl33qoFGH#KSf*Me>8)jFewFSs6Ng+vubdJ|ghyByz{kCdb
zBmj%!a4n*CskEp?LwC#m__~CkIp2&~g2*N7&dSsEph~0U<FqZ`vK3oQwdsH}EC(0k
zuBN@|aYlm<rrP4hAhQ~bq~!n=fnd)jX%x~7jj^zwCLnl;y<ku+<yS7mfYQX2^v}oa
z9J*PKObjpHJs@N29hnfz+a#iw?aQ*(B+V(=1|TUjBnIekzjb)8)%zNu8P;jOzkLtj
zigdpq7+>IWh*3)5Mmx=VHxb;mMb~e1r>)WOGN^i9Ur*I>!5duaGC=z>*z>Z6i2fmB
z#H}paiG!99)+C!G-PI0&hLr<>^xS^Cj@AQYTeQ``J=m2C;cV)DgWFh|5A_p$Q==UW
zh6zQ+;ovViHM8ldyv>GY?dPO<!;j*I`&y`HJIZzUuAm_*t4NYp1~8~OM7ua(Hq<tP
zMVe^4Wdq3DwWCIf#AzJcKl<2RZ-llXoSFyG^lg^$YP%S9)6P7_^<L;&Wo(qPP9F3P
zx@`HiyIb}tslX}qHnSGMb;$)Yw01`vD-=g}YPd$&TA6gZj_w33l(%a(YMDv(x2dcf
z6T1RYvvn=1+Y57)e4)Y*p~5bPO=`ia(5FSQ%j+k)+G$Svt3^%7%w?Z=*qeT&d$a)G
zGh<?skwjhQ`UOW*1P`u!H7H!BGXsr9SF*v^BCx?O(=!>9EWu1Tka+Ei8gzc{nW$@W
z$l`uLf-Dlgl@@WQ8+dcgHAg;_P>MWl4}KxuY82mx)0<(7G(q#+&YRUl3gmQG|8~@U
z%*#*?O<QneI;R6=S-r$La}Fc_O_+(P`*a!NVs99Mi)tdADOR=_(I!AMgP*A?!(5xw
z%>^5Joz{bmMP`}qz6P;T*?O`NdZ{;v_hWOoHZS6Gqj_223?eMv-rE-31~rI4dN5I@
zo4g#b{WvQ@+F4gk`$qK}H6Kz5m7p^8qd`q3QO!5EqEr;g;$6d11amivPKpeH-MKw>
zA@=WHN^JCO=>Re&cB+P)H+;lV1Vsmj271@50qqdi7bUMMKWF1)#Ook2GK`5}S-<g5
z<KsGZq}7f#g@!}AUzogyh6avlmLB@F=&yI=rt}^j${lBLR4%gNXr7b!b};5s&)eiL
zr=@I>b+QQ&U#J}Dd%%^VXp3sqtr<xH<H|~g7GFt5cs=%@PZPkqR?0L&H4g;!+Rb^^
zBz;G(FJ`orHptt8OdGL=gUp`kM|TtPN3urhYq{Oz5HSPK_y*wD^J3Pml|x7uc4L;W
zDDNP}-Jim-(B0$OgEk&I3Yp{IPK<!?zDW$6*i{a1=cx^Q<=5Zzqew*KKk3=tDPg6v
zaJr&%RQeGfYryLl`L|(W_Z~AL;A`&l^JlWhLjb#Q`SbVR_Z46LdbkztL9xhvP8@6P
zOm_K|T>h%QT+Kb7f1z|eb^7(n{d<88H@x(PxGHn!<x>1~`COR$w91RJC|oXY9;o!|
zdAE9y$~E)u--^pJPaQ94>e(}3v4i>mcNRNaFLaO_&+pfl281jnCDmn>o>B45`Y#;J
zw)0;S?%nBRg!844Sz67vjspq`NyxiCA@XIvofUeneKP8wbMKqeXTG678@9t$aU#3)
zjCjoiE2&oL8w70ZsxDm|e?&hgE`_h=U$`=~JM6!%EBU38{T%6v->k07GvZunsgge_
z+ZX(&{mT9Qy>H9Um$TlS8)QvN<K#ejZ&~b(9-J#>w@TSKl4T(VZEn079F~^}T$gMY
zvUS~^gJ+ww@3V7SstyRFo{K;1eOS%@&)}NbElzq7HR=~57G7{vFNltp`&>g1r+F&M
zqJx~msK~wT8zKdeqzNu3v~kdfWBQGjdp`DoI03<KGdn4?Y&e~d^CiOpy-nWa;}AQi
zD*5?DdwGM4@|}hD+><gAo$2quoLTp!YzI)L!Z&%5;6DJ*Q8af$Cv_LL8K7-RvPtt4
zUC;cZm~;NtpSV!Mew<W;P_cFr1k!tRY6^h!(8JMl`jO|oiMJ?daKU|a@wxQ9D008P
zbZzymsq-c?;rNqZt`aKx_vB6T^G*cR!8k=EY4%IiNA$!MQ(9p$yIwva7yh2SsD5m5
z;rDYdANXfW&#k^EUmD5!|3qF2ojt3s0B=>P2Xd<d-;mhza^HdHl1Do7BSOshKbrfp
zYhX<XYtFqlOR_+56&IptGWC^#HZ?=;{lAqQX$c6Mgucu2NH(f#1BX?1Qy}^RH9ZVJ
zvz+qYhRND@@<5H4_0b<w_muwgf#%f30Rw`N^v>>kG$nK4hB%w=)WHS8R{H9FWUjk7
zenb??{=_SDFPA4pIC9+ork8FbT0c^Lu4O+NT=d;<x+-ogt{>R#_x>p{>uvuzZ&ku`
zGsy37=^8=l*IU!!y|+qoU#Krs4pcQ2JWhpY|H=H9D;;qN7*q+~RFhfL@X7K3rDyN`
zQpw<Aya(yeMT@4Mi)%njpB92y3JEqS1DKSg2LMc)st;UJw@!Sv30<%y0n4bf!6cGj
zbRw8q>g_zL2`Zjq0$+)O4jjR{?1;YlM7j-IpH$$8uV9NTUN}x#$T~2j25CFsFAO<=
zQe>F~i#4+*N#fZih2%Tl5m9?geFQ9Up|Cw~al_HUo`b0a1{TK^83vI2tc4%X7DlHJ
zP$k7i$?n;bBVBcD4v_hUyP>VpIlv-FpzB#vsRdYg=vMEq6y=Oq)||TDp56rl&+7(j
zA0xIM6!!L<M4pxq@nAZZYaP(UzWPo#)uQjSBlbj4_MejSvcC$TciB(->LVBZiw){!
z@AgIidgVfNM5GJuA4w{KkXwm)89)pCgM%BKpYe1#RDlTnT6X;aK-D&yN@FKQ7HyQg
zgZx(8sW-tx4eo2;!!FAJ!)ni;e4sEzS#lrnZ?gWBFn~HhqxS|BV9#G@jI%;O#0<iU
zJD?SH)Q^y?fhZP2tpCmw0QL<+=G>8|{RW)r;kbdXK%cz|8P=r9w9E%@`GtF@-B1Uj
zH4RQUSsh+~qDSZ`=2`)1Hb<ww!WXAY_jbyLq-ynEEO!ir0A$cLv)PK;5>yZw!f`+h
zyG81x0d;GBt2tF3ka);Ae@&~cv&4EV5avznxNlJ0!kk6~q0*oc&|I(Y(GjO8@W*H~
zfuQ&dQ6ZY6VvX^M)O37I4oqhUyFC=idj#0;9`{nbqnBn{Wm2gk*OTY(wHe=gJ2(o=
z{0Tz2*G$+4pCQ@BPM4IJYl;l7XvE=1BYWsg{|7fFLGID*V8!;DeoZY2w`I;q_B-JL
z>ymegO~A`K3*A408i8+=h<7b&Gp6%mCcjn!VJBP6K1u4)N3z4r{G|h8=KO%;_D&xl
z$)rbpnJ>wNA*7}`$pyN4+sG@BF0JXK;tNU^8p13HG>tVw4A{&36Z7I)pV(*jOpBE9
zC7T<`r8UO!ZeQP@;mIbRTn~7`Xfgt-tftbU@9`FTfr(Q$yjc=XFkqX0FmR@19UOAJ
zflF~l3<X^SuJgvz=g<RYwb=sjW*Ek9sn&s0)Fj*;4kj5Q*#Kx$T1?gjWu3QbzQb~X
zDujBhWBdyQtJ^&tv2>O46e3;A(xQ_BTZ2oLO$`-I%ApHt<3lwKZn?n4nn~0>DCcFc
zhDxMN%1NuIJsP5lx`#3O7o0*oQz8v_0wV+2fey9}d&1Dr-NQf;Cdn7RhCkfs{``yy
zx%0$wlreo*Q$$j6s!{TqDt)gl@T5U~Qxo<Mq>HiY<wwbW34elc_)&-|wu$BEG&3J0
z@tPrcVp9O7_VB8KVZA)o*@6M@Fr}1=u;{jrJ_<qGwe~2UKw-NdKPQU@jBVmuzxBmm
zyIqFmBgyw<yBz)gWX5lYn{!Zprxr5s=^bw7|JQ7n|9{Xb|N55vl?2Z{bxOJX^<`yZ
zf<a)3hA-Wz4^6G-udja~*){=LNIY&Mmq;NGV;#oDZKx9_<!fOp=2xTp5Mgkz@brdG
z^+16?2AuRX!MxTa><(kS7*!r{0H)G*-YEX&Ii>5YKl__dxc~gam`;`zn;+&==1~MZ
zv+CP_e$S6P@1o1|(06X~#sBn!<M)ek-S$PgMdjKm_?%9k^GGkpvhbGY1Yy5Bae+s~
zU$CMz5KLHUG+Nieg0;^17tw&hfU(I6u|09Aaml|-b--w`ONErII2Y<Au*q4f{%Q?6
zDCBH51d#EYEzI4d%WuV?aG;)0Gm>krfG2jJ{Hi3Za8BmZHyaK~GKuZ}aOLoN{Bw`*
zI4rQ9LVF<tZqn6a#S*V8x`9^m?%k}AnWAkir1LGv*mb|#Z7p03QypadtkW*Wuk|lu
zk5hs|JuZPE^r-DF%d*L!SroDEG8y72;A;aAEGwu*1kZx(m?cdfeG)lUnzqKu3#+BO
zCT{)o84#Z06vlCe8oNzR{BtTGw)Bg}5SP?Bf^l^bUDsZ=m##FHDpdgHR4k|VsWRd0
zOR^+&@F8cS3wsw)V3c%Gndmi$2E=OWc+Ryd)EID7B}cY=8zvG^8l(+E6)U0NU)qw^
zY^kmet2o^Xv9I@e?vFm<1e=dtfj$#yEXSCAtL2>o7i{>=h2F5^EqmP$Ln}y^>i$1(
zs6z)E%W@-#-S}jz`+_Dlke9n=^fB<xoZf204I=WND5X@r5B#IR_L->Q^w@`;#yzs(
z_IFLJs8II2KMDsz`>;q#LuHyLK{L-|(3K)Tbq3#$k<9|Q@hhj0#RjYky}QBI?k{Ap
zc+)gzZ}rTiYg7mBro5h~Ce!rr^*At;(Pj9OEDdX^5|T;l72nZtk}6}}<K;#n?oLm-
z9s%a9vGX1gw(<0GobIq1Zn#N0)M80H3gVcP8YE_*;#W7rg1aad3HRT-1$tF1ho^(w
zIZ|u>gGXv{AO<(0O)u5B1(v)p`rsjo5^Xk8cjBU7C&6L^lYPc5#Eoz2gXrY(@|X9f
zFT3%>e(RF}D662G!298__f4I`70xZTes^JgIubLdrm=JvlK5)t&=U)Kd11^Cg8Gct
zh?=YO(_v1W5AJc*hg!beAGl<^9hd9w@X(eg2f~hf(jBe%>skecm=esP#xu4%$Wg=8
z|FeI7*E^-mE<Zi#rL8NCh}3ErOfhS-(Ri(z`--1A={;QC-Ea#mNg&)P^gp8O-}39D
zZnryrTy{^CIZl$6lpji3TQhs)rN)8q)YK_)-)l4dQ|UN-ahKJ;oLkH-ChDik=iTMI
zo^Q*UuyImWncZbAzmckP*pyw=?Zyx@$Ufjl5vDISpOq=Cu;5}-UMM8;j0cij^{kKl
zqGPcKkQEL216AO(+k&vAp>$`mnPR3`A#Q#tQ%_CZmuag7Oije9$&sKTQ$wb0+7nuL
zWCMXnn+qxdFKT6)3OGtSwJNIu)8F82AuDLpzu+5~gzVEjJ3!H7GfssQHo`yr_dnpq
z`w5n4W+L6fPf+Xc*2S*DP<%6O=?D+trf3GXtCr_t4ZM2HPu(T*u|BSw_Aa*)#?8wO
zG4@&zTck5p)>^b*G-6Fs3*{|36e41)m@hg@9SIIcyajcLtXer_tK|d_-@x}VtBG!O
z!?iFSwcq%cA6RoaV?lUy>aCJel4apG*kCa7fvFf{)zTTbazjoUShHT9=#CVRXI9zu
z3A;GYW<Ok)iMrgN``)n4wr4=gCM7aRM$wJ(34&Yfw)(gH3aA*Bh<M*;+Fp0|eB%Sa
zMxZ@;@HZ%A5!z`l-kjO7mQ7?f5Run7(m3N1%KF6JBs|^<o1%Mg=(7!-c?Te+AJuVl
zs<Dk3$_DYb6Z*1X=ted7^lG+=IgZ8Y2&4*33j*#-xZ#4So-VN$Jh;v*g`<!vw}Seg
zJ#)9&azWhtGxQ%Y{8bGox6p~|#mIirE}|DT(ip1ka0U!<Pr{iNu6grC)s;5L!Y<;I
z#B}Fs`qjvsk%q1ajS)1C1RHXH)MEq2iPHgxRvqQ0T%$tNW-sVExh^+zho{}Ae!>~B
zKO|C07wOo=TjVcofst|o)Ea&?cjeHQF)}v8X5A0#pm&^Db*(a{v0^c^yo2+T{kfQl
z$^DW-tc$vvJMe3p!xf=+YD|goWDin0T-yxMreHjjH5e%E$bY-*A-g}SOH+yj?jbnz
z0+>;4DT8WOvsY(bYc)SFb|%(XIZvogvlA>wcJVSf5X(_@ncul~zJ~?$Id`7hIfj;R
z9Ie8SaaZU-O0oT41VXt}lB}SPSY}t0ut;~1kL+B=f@K?LZv5j{YQQvh-SfG0w5aV>
z7bI^LsBn^Hco$lNThwZrire*#(Iw9Z<;}1I8^UGSv=!m!`7S@d(s1*c-o;lyTY+E2
zeL~;Wuo(0#>`)uImY4%5AEaAxEIE)7Jv(?};ZWM^M03CK)7?D|rBI?pU_!H)$#KcJ
z09Wb?;p!F#W12Y7+X+$0ugIoKRJx7X<9>kvs4bi(p%pjz5OZV}0y!kCNr|*DLpc_r
zA6Zr@!Ut#+r5n%i4c=_b7;j5TJN*8)NG*_QG(>Z?emX2Xn`Zd4-VHcybObkj8275X
zKLm#LRSeuorh*lj_IXXa{|Nnp>5@1QOtZSpns$kS7p}9PAc+;6G_@3u6$>4#8)xWV
zDk_znzx~BYHK|f?@$Mq4h6TtHqtC^;)YUAYU16A|c6XRfJn6(~V>wCN;R4vIpQ>!&
zw#n|<C}b2$KghFWL-a$>oD$e2*o7oH;G;dZ@<dP*BC)N3yL-UuiU7jM%AA^wqN45n
z+!x2AdepEH`4sEIh@I7MAF}louO_OZm?ZWzNydx1WQWrg&(qTon%U6kN}IksEYXV?
z=O*BL&Tg`B<K|sv<YOk*NTdYQWNL8Ef!KnGXEVQID@#B1hYw!v4f<s?*T(na!QV)i
zuKF6UU|#%Y-hJUG8xlAma-Z|ArO`EU`C}6$x%KHU$QQ~VULBnCzTo9<N`JE&Kk+rO
z^V$4-Z-G^!`+J`!5NCI^Gx5m2B+B`Mx?F}Cx|(<Omu32sbK$e=(FHNBIqCE@<TIaW
zwH0lGs%G0$IWf0W{8%|65vLNY!hyCpY`fX%t(VH8|7JEgD0=;yt}GAcZw4Z3R|XG;
z>T!KFxI8#EGyQYF_fR~g7S0yhtE>9?|A)1=0gmH5?>uLQBL;DpEV`!$Xn-Jz_wAm+
z5E4IT0GJ>xn$wLQa410%rUAmRmbQfvAgf%PvjEDDFS~oe40<duqE-S#$MV`<5g?UQ
z?dCQjt-A7V-CYP8+%Q>YR{-UWe3vSVw6gKtB^#2~=9sNybH8Uu<zqK>bysymh@?1Q
zZ@>L~{-6Kzyg@~#e=f}0u=6i<G?wgd%otsi@RrI?7*QU5{>F4z&@Y>flh5X-jmLNY
zTl37{J9BEqe=#%sT4hK1+0MeJUpA^K-Q_kGZnUlVG&Jos=A&wAJALpMrfyh2iV9QN
z?@q0l+xsK?En|9VN4fK6svkTdss-`pS5;D;TB?}aEq>b8jMhG*$FTcqOFGzLerr}&
z8f}9e56v29jOSl44opE|xojI>tgGrmjv{k*dhO$F<Ng;vNSZSO)mAV*wXQP;semM+
z6@Hr}xqQ#IYJ$`XUfa0fUCcf0MM6(m*ccbK3|;tdPXWC4p11BHuktFjT6lrCNH6_M
z$L^uEDZ&i~g5InPQ24g@<s72`xA(swh;3&`OS75+d=2INI7$1Jmxm8a+rDk~8?nr*
z21gCsonx;N(*Pf@82zNq86aH~;0>fU3+vdMSyn$R#e>Xt5IiGx`hxeNVYDhzj-WXA
zSownawtf59v9!vcc^$0p*I?$QL0t=_<gT_42L~I2!6&CcS+7-&|Kk6c3jt}p)0GYg
zsM9;m)CcCp!Y|n0_0Crhedo;WW941pKkWlt+2KJr9e&Sv-iFQxxVyQyxd{3upEGu<
z{8_Kl`?T?e;ly6`U@Eq~`qmjbWxe%S7ii&&saxK$y;IOTKd$N(BdfxU<F6Rs|7ZF+
z`xhUB;rQU#PW$^0b1HT8<Uif#zsV`Mr*-d5uM+9O^JksUJ-zi<CE&E{TAYe;7uU((
zx~UaBF#6tE9I|2C-}W94z^AP3&%CG}vu;gI>BiMk^@V!v3GSLs^qvn+g|)p?zgYKb
zOpUx-=Jcdh<J)B*xI0|SthdrP|GY=9`pY$Nve_J1XRyoq6ZR?ht43#PB>)NmeWhJJ
zm1Hs@g+O|&^MZat-%W3tSd<6za+q`H*bho?fWrRP@iVkw_y4@xIhM;@_ccfMM$Ec-
zj`}?C?0eTo-AwA7!KQ-i{g{JPq}FG64>TrUVyq%te%7d+4d#uN>E1BlYF=I#Tm0Pk
zhf`B8>MOrjVqhyr0C~~Z?oN5na$kYYoHg$Y=lkBb+<LvT^tgAZ&iI6B*pDF8+{dGk
zbp4oggf}6<&Nwi3;yEtEKbybhdE0}*(fnbRE1t{erf1F@qm#$aBhYC$wl(9ij9kL9
zuvdfTJz+TJBIk;mch3L2;`s5{3nZ#Gee(vv?~PjAgSGmzggy4@4cnrKnyQDvsG%Eo
zgXZn{OsVTvQ!)6)jZ^0{5KPtnW1M5fAcaDw!9x3_ue$3)oBI&I1=sbiNAV+1t9}qO
zz94<ou~(*IWk#i5V$lH9+n*_nsy?0A58gwJEhr>#vyQHO(mCWk`7e9S=dAJ5uoPm2
zC}Z6G?9WbrX@a2u&_$DsJ~difz%{+|hWUL#-#DiT4)h~Q6M|%I%YJGQH0=i;n9t`X
zuch9u^d!2Y%Bj6mPrhn@ZE+PIsUll4Un(=Fa|ME{=OGD?d_bXrjhkwFxt?GW!qiKH
z^Puctr#faGiob7awPB1KF@_CT=Mg4BQ>in#0HC(#I`Q<sbP`Qy?=+yY*;ZBwcS?7j
zw8Cje3K<#mPUb&Rlrg;T+7%ATe%!N|_R6kT7Ck`MZGg&;SfFsJWVGKa#D*EDS^CgZ
zFXbA8UVA$(ZFJE(<W0WDw9j~VRA2MjDfd`uP}DE1rix2S)&*+jQv+HF7$3UQcQ#0?
z_%L&ZpYy<ff!!JOwrM7cOS(8dy}MQ!{L%x=B`EE;k@UB0qlUOW>E|@HBqfA#ee1}t
zjQ-`Gr#U!Iz6^_3e#033c8tC?q?20#wPBZOVpU3CBEh`&xVN2yuH5E!cmD38VZ_;O
z_p9-a=M@_TOMTUN-`r~QGC%gn+q2(ajQdn<j7QEt-@2mD8jqauOjE{cB<)Ae3#I#U
z=8nMPy`Z!onui>Jd>USH=_fsIcjen(3^f+u`+uHs55c`<dcYt4{<cHS9p97#p!WQW
z(RF66PGWtE2I6h;-3^=7AKRTQ#?9!&pck{+E#~?qUo=WdTGteyFR%IOCp{VHnd6?&
ztWOjYS-ng_tH)V&KE_ahw>&rTiVt-B$lD(OdWG1A^SFk}7p8ty6)!sVE!KlN=as%*
zDE>(n+P~5G^UQRPLYn%bk49XLC@F<+&cMD|%b0UHyPSCWPk$<^y=4>k(7aA`@-!TA
z1RCru6^KW>b}ZRu*Kkp1ecK*(>%`J494py5H&|Z$RYr!r=2Np<aI>}BW%@~9G-}=7
zvrm0sLP?IjT#t7@KL{Lqr~)nM9W(1Nmg!OiV>MSeZR8;T11-76Zeh+k;bIOF9_Jdx
zsk4~#=*qEpu5(jz)ngU^t$+V>0`%5e8PZ4eV3%RBkQf|HlCVW5?3ywLX$NV+LE;jb
zfV#b(`shl3)DSrL;8)`>dEJQ<T}q3?j4To<>X?_j4i*Fwj2|^t+sI7l&yN|!t6nN8
zKrzgM8NMdZP}QR`*XtIPn0T)4jk{fQ*Zr#ZN3d7_HW2t%{)>+Gd(i8j-EYzVyZ259
z`pcQ4ADvbtR9HCx8+e!_hCVs~`~Mkw{mT#eFPX6aZ$4z~{!0F~qquwO_fKCsdVeXx
zr=`#Tqv@wjLhbLu>%E6-U(|ALlK=R<F{=D|kCzLfHgnqzyjDVD9`YN>g=93ePA6(H
zTK+D%@_#hg?F64Flk#>$H>}AZgs7NX2Xm8OvF^yd|0@$Ec{!LuGUnByz*}G{irwNy
zwN`LsjBpUuinE#f)Y;}olRn8?Bq`!8_y6gy|4{>Q{A-UUSUoRE>%9m0!w>)A6E!vE
z!LO^)p5Iaf!Hk=)s@cJH;LNr`23o&XZYzH}_kN9|lXJbvh3s;!v^ZVM4d>SE)Qb1w
z)Tx_Zy;iM%>x}V9W-NseR3D1JXuY4Vzu~@Ool0b1%Ppkt=8ULp4nJGlnFEfAM|+KL
zT9@E6*==>D5(T^Us~*za&B{)#C_V25arh0nOM1b$sx_RSg#xF7{Q7@LP)Y~>vdRC!
zTu;ZDu1dycp8`+t9w#YVh@VnkITtK`weZk-t~*7FTV@v-W$c*@4K0K5o-tqaPyNVJ
z5l~dFV>!n>#TK*6T^r=oAiI{0cLTl7$4!tZyR}ZrMdCldCHIs$UvRDN1;Z{=Iem$q
z>p=#j#`RyEZt<cu4bd6;oLQr;gjsQGNP_)J`I230BtD+2*K6k#fP|v&`>ekZ3{t}V
z8l>#6PSp!h`n5clQHyr^fR(ydzt9EZ`F<_&s#71YM>VlqIrE!S+~2{6R+aGUUU6gO
zqB<6Ps#Z|laZQgo9qvpMi0L*v8oIN|S(Y4612`1bM(XkXkC1T!I+ttlONJb>8iRjR
ze707zV@eXiQ;GQ`a%<L@N(!bWX>x1JBk|bqiYmrsl5%W!VxD1`WW#WnUg4J<zuYqK
zC3E1;eIS;c&v1e94ooZvqT+kM_%TxYA~_<T!*~%zukk!sxe>f(S)<+%Cd&J;lH=T{
z;-Izu6tpVkB5~cI8*r&GLJS9hu!UNYa{94WN_t>qE!}e2^g_0}@kP>mKE8g|j`3G&
z(}@S|FMj`l`8Y?>#=DcXS1DR2=8fEV9X;#F+oi>PnnPsFGslqbq1(o@F6XtjEOmyQ
zI1%s8d;7?!%Y47Ft@cW;?Z=!~UTkSoA%b6CnNqC<FXyI!q*S>G>})@~5Fga7$%0#~
z*6kskU?-N^C>PH6_MMikuwPVm_MhfjgO<~Oy7wV==`jvtO~%ez<=O&A*uGZwi}rU7
z>rLy~s5UuQD|cq&L({d|i(c)O^8S(2H39+({AKBy-4X-3jaTR6q3*s+NgxK3TPKG(
zp*$%%M6Zn#FQ2Xf4xjhB3xhB%kboAt%ezm3xveO3{>OC)#`8Dzl;6Fu@IdUBPX2W4
zopKyIPoW6`sR2iV`5*-j{|G(H1)qSe$9DTIwfXp2IZ2wcTE$+7KrOgz6&L_?FBi7s
zQ+57by4B0QIgFr=Eg)Rozw9LDYY*t>{s6Mu{EE*j%C)i&yo+f(6)d`m2<)tvH2YX!
z4^Gzhm*+)7l61{#Xk#mY5N^zd8W@XcR?azz?l0Mqimykk1Pb2df&hj|*2TiP<?|H+
z4VdddBel!9Vq#vIOtnb<@Z^?zh7sikt0;q8bSo?8o_ThjYwWEt7?QWOJsYV@%y;ev
zuo5r{&TkcS%~hdptUOkJ3N7Jl{Q0f6G}YDsNcc|SGs?DIvO04Kju`*kYu(9t>~NVy
zA+7R&#2PymS26GbkgYPymB%HM*OYhbWcOEP!}*@(tIIK(bAsmkqZqZS_)rVaEy_i@
zwgSCF){7s`y~~^TmsyxtaV0BY2oQ(G$J}!Fuuc}4p2$wJzM2{)%;F=02>(F!aeukk
z0<`LtqeQvp)5y<v?RVuv<dOZ@qFslsm}n%53I0F2b$X;5S9Cf#A3>7k6S>Dgw_vv;
zaWx-sI#STGCaaLA-p|ky#QWwsKQ#6VpX>)UHUrz>Cc9N6F0C7P$d+)i^Ppng%4<14
zsxN^TbssB#_^tnz=j0py+JpCZ^S=L2k9*g$?*r~^^Q|>D=>FsWXUXE4OV)fd67bg^
z{7dtJ&_vCpz#xzpwCXrJIDgmv`+NrUE;x}MuPti6Vn0|tM{nYIV^YK=pNS%yiUIz=
zMPN<&_gGXLtpSkLJl??!Yo6c^4kx{CKG#<48c*<n_ugR!^DX8VKlM|*w;Rl}RhcVP
zMv6LE4df+{F2-8TMXQYT^LAsw<o&MiKEekypH$^j$(q-EE31Sn8hc0utJ5%<qqic_
z>IOHy`Bu%z0WsH+&!rdk-jlUh5SV}59*-SsZeN6cbjLyVfmxu{vl${10%Eed*d;HP
zf`F=I)62zxcYqM{cW`>c(#3@9-oJqn?~C(94pRPWh;xi9x%H1PFv7STqel_HG^<wF
zAg}7~@xY?@M^8M9?s1?g+bzm=@A;VfxOwp3)0Ge#x*LhepBi7}ju2%3<qL+Fhvc5{
z_U<$C{$jGISMn4;<RAyLyR6^#S?17t0m~;1h}CbMZ*PhSH??&|?j!dOWOHay#WAof
znuX8H9?KIS-J-I19PZ5D{MWzzwXylzhhL|yQH&(X2XA?cC3HvYYzq4Yyb+IeufY>S
zZ66HywoCGlsB2S5$&LQT8~(<>lflGd|A?0_*4d5umKT19e%X2M4<A{C8l_{gck~%v
zbSZiQKCk~&6!Aa8V1oPg1(Oy-c~+JpPtOO!gPG@c#4M;`iCAopPofqZVXwKrQKQ9o
zi}f2Su0DEx_uH4*eGWzi4vCWtvgW^dvZcXIZQkxBEM@E=KA|bt5hm-bq!&vp>k{kW
zHt}2S{)>$&;_;U+mP6*7Tb$>`O+8!mFjV_(Hx~Qi|N1k$N8T$k_*W11ulWEJXBW8=
zKH_ga{_B516l1aa3t#A_qQl>0rgj83fT5L)%_imY6T6c<M-)Gwz=FqW1T>zvmWO4J
zaQo%5KR+E5F&7aEJzrxw^_uEp0suZpWfD%Z=q3XUpDfh2X>HBTs|E7l1cg8&>3O$y
z|1a}=zFbRF2xAf<5DUf8GGBxd%g|EB5y$zr<_bT$gzo0Wi86}AK-Ks{`IJ~U)G6fG
zgb!^h#QT%K{+zl~^_W;t4W@_Zf_Jr>Jh~VSedYAkXsG2>&G;_d;_?lnKF872wrM=*
zAAJ7)8*T<yzdC$pJ=){@&qd|I=r<Qf2BTMS055_MTRT;*-8fWN#sz(5s9o=CJEOGw
zc=Y$4b)Oh{@Bi;FA#2_}tsfkQeaKhb{k=Z4(U`^u2D%^b)^d#CmhO>wYy2$|h@!Tp
zs(<z5&__=)NaU|QS>^g;wO6bf!b+$P$sgnG`cG+jXIPgf-{SOw=I6$=Yw~0)tCKJP
z#?QFJOVwbHKZJ#O*ALz+KYV(mrS{Tk3T9MvzvV$2v5jnP%si5*w&gy0@wfc_(Vq3_
zrS<P!jauKky692G?!K|KraGJjx{n7lw}<pIHNR@@9)4H%ukTI{z2}cyZNB>IM<4yS
zzPS3)i+?+kkLJav<)hc^-2G2hI}25ov0M%IJ<Dr9{NbOqTDa+UPBY5Ok1^nfsewu=
zZ@ER&42Lrl)l%pOoU7xN5Z@Ry>D02?q0Z`zm)8e3jm=b8*rC+ZVb&`piWB9a!3dEP
zQ3=9CZRy~vOC8(I?VyOejEj9k*NsX(eZ7w_xRP-~zZ4FuOxuKC3)a?JN6HW{UQ{nK
zV(J{@(Xdy&b)Cosy#==v1c4P;C(2jG%dygAgt@<a<^PHW^J>j#hsV!(ZL<br!}ge?
zed)2(z>rtbrO++41=g@X9yAy4fk0vRyY48}wQ2ZqwMX^moMk6fzpOI}cc#q>CZa3j
z`~<ai6DEb)IF&cP_GY2;T%q$e2ma2QPxtkhR)6+W<C##;SQCDx%@3nSaAKrnO-7O}
zgCl|Zt~kBtATqB|>epKDb@#f*3a(cQl3r^P#GY%2)*ANYV&lDk{&S^u%R@tD{cBWG
z^C>kD8tE~x(8B0Y#^*aiy55r|P7U+W|C{DbK=hl8-11YG;S*m}tD1=`cN{%6V~)G6
z<Ev3=@^pz6t#^6MeQW$_$HCXlaA{X+!?>8w8%LazW~e$gojXb&T-CXU!e=}+T6Hsz
zjGS1Et_1Qf<Gsa=#X@fH;GtEMA39fi^(v6If5&wnbF;xXLa^2tFJG~&ZLM+{cYo&_
zt&tI7X66;$3`W<KddP#W%3Tf}BQxx`vHDUX@aT=_y||O@dY75Vddi&Dn>y_4(E~rx
z&c4EBm7kj7wuM0^^x3AhTFH(o(P=eR+itvWEURzi4UXhn)BBWs{+x4CT~CFT_9}0A
zW~QxeqKfF*+=^qoDSmndS?bMml!|o6a<R0aj_9x{3`J{lglo7OL=Aw0+P<&+OewIU
zrZlm9!)`Zr80k>=TT0~z%u01CGZCN#UeV(6(SulVO=T6MX{;1`-&5G3JL;PTqV);g
zwXAyd3>CCes53iHTw5#AUcGJ&)oy?;etYoi&}+YqGHe<@N=-TY@*4$zqfjqsm7Do;
zc3hXnb*s<2uF#YnaI*PTsyX4JB#_(+Xro+3F8gl4Rj`m&{<|_+UcbVy))R}hM)~f|
z|J?d+Ah!ao=-_6U49qphl;t)>%9pFKCIVGV%G*mxRHB1LBSCd@RvAwh(%w%T-4*70
zm(>A(W_%c}&zR#k8<W=>lSuiy!IA}1+xDk+#|z7iAK2cF)D823al4QjIGMVhuW#zA
zZVju!R0fB4;`EghR~u~C2o1E&%Xn#UVTCc~Tac&(cVn;noEwN}Si$6Jc=K0I1XqG>
zjTZj;>oZ#e-iDvMZ<JE;;?Nj+I_hPD@n=wq8MCR__~vAc{tKlvr?aJ}Or06ix3uc#
z|8}VK1XnQZDFPwDX)Mz^^0CuCv$NynC4a;Ik?}p_lSYr~N$pgbHN_a_IXw|%thO*{
zZJW5<m|SnzBje>`M&!|}_}=1bVc}c>euJJ*V45zY4MQf&50dK*uC!~C9gP*s?>&<g
zmn%%DHtvAUv_8k%(w_+(D-dHkk)2|Hum$`SnLDz{k(Nx0>b<B7`XPok>zjo+bz3{!
znQV_gU7FxpCvKL?Cr&r4u0?oIM%$Fp=B=rZuV{0R?ooU6$IV2C*_TQ8XR)Z6uv+pT
znT#+oBQ>_L2ItsWz$o#X(y`ogu9XZtgr{7dyn5wCnfCh;neo~Ae@f79Llx;T45r|w
z{ZOZUGcj77X3yDsl1YhfEGxUgl4a4cOnhM3aS!NSx}bLXelSs0nF)P<JzB?N)3a@V
zYi;+LUCYSWE(C1DSnA6xo9M@3-B)nNLJ#>W1ryUH|M8K@b#PNERyKUPy@N0aa}Wo0
zulC<|{baEzB`4O`OKkE;vebeLc<^^ylaMpI^2RGh3XGh_;)1f&sB&8k?tA!5W*o+y
zC;DDONG`F2Id#JfX(;HDz0TYy+|hV}T}<QLp?0`4<I^~Str=A5iWrgoR;RjQY<%M<
z2i4bp&~YPm)BI8DCuU)%(UZ?q3K_2wekOC+EhT5hvzf$tWBeNLS})0xa04&umj+*y
z#;0=%YDn&Vf7$hp`X!5V45BNjH?AxhtPw>1a5C<BLp2F6#g`FhR@B4B7KWbTekYzO
zO-u)#!sMVQviCXI{@M60cK;@qutV)C6jbIqSCHGQXToXGR}K!CyxN$&TC%Nv(bkuZ
z4f`Z@d+geweEx`IY&uI$dRe6}s>^N$OG2f58lhQhYI)SkU|I7N$8b|Z$L4fGOI(#P
z4!P_HzF1FkUNWi1iEE{i@yLsc_T7bFDF!ZAZA$oHr)qg)kJ&a>$QYrS@x9QUnc%1D
z3Kl^CQLHfdDQ$4fs=lc7X5XB1QC(DF-@%J&&KVz`nHa{CY3{;ROj~Irp!#C&1Rbr`
znI{_GrTg^33(g$PCF$$=(AbeJ`NI?Lw42$9Fv|@H`mJtkt-cJ#b`GIO{Br~o+2`G9
zf5;4iWKll(TEp5_vXJ}9#Yb<nvQf|q3??9?Yu=jCwyBj-DPS`P#*Dl-6An*hEX-Pf
z|Kd(0xrFqFLBHE3XWGvx|9a{o4%Kmw=rF(EdD^tb@om#Muq#AD<I&Mt+m9i^yks;s
z><xQiVd18lE!-iZ*wp5%6MB_2R#0N0QC-8Y){t1<LtngoYB_f*wHP0SONpb`x%oLR
zVw8K}1+_K#{3QNsa<TQhzxx2^z(nxhNS6sBc260ZN`Al?bByU=Iy2$AGiIV`@)0As
z17a|H=hOu}u&NdwuIjyb<S@0XaMKK@vg6gv@I-a==6a*tWn1q?8xf4mDdXF_zixbO
zcK3yRZ6*Invj^ujRXFUhOT0Dx3%X=Z_+Exvhoy?vg3`NUHKTVHO{mSxFcLeIqj}|6
z)j!HLc%HXjDvuD$l>&OZTkrOjitEfThcRZcK-<`DY*Cr9RNAX}n9XNqFq=vO2n+_=
z{FYiKieTiR6Y7V|ij%&n3FWYu#3$H%cPjHZ5lsW@w%%o*<`jaC_NDe$)1SukZWwor
z{4RZikZ3l~u&zRAa22yX++|T^YvOWg1o`MXQ6`2^-m|sSK0O+}TPW!vM?sEgEGddi
zh>Oqa>VifFMf&dGFK}Z-j+(F`jK?-+5rw)qk)4^CCS(xniFy)-zGIli1%*v)H`BKr
zZKa6;PU`D@h!BeH&t>Im-6@rsJbi_q@sZNILB0!3exdeqZ8rDb;<61tVjp~#eX5W;
zfRV0NAJw1INcT7nKxc49BH(t=-(|~y_^<Gu@8s&|^dQcQC`ga^N%35xK~cV9ajk(H
z?UGRLYMP61YXm}Vv~`L#nl=5Qp-{uaNMtP36G<id4T{9$_e5z2m(h*^Z8weGnlE3~
zJz8acWQNtx`zW*5I*elSgB5-^V9h(llisL@b{ENUEnnDu!8A1CLcz^^*~PDi+0ul2
zzQN72N0L~^soH6{L5y0akJMQ>=g?FI|F7x?nt0Na3pjCgEvUgEM-v)%U;5u-ase2j
zrsrcSXJ!aJ$fqk$&xDv$H?!46k(+nI1GKrQ>huYQMjsAu%sF5Zn&N&jMPwb;_%p5J
zgaOyC5d0(`v*2UU+eowD>-A-$<JJ83)GlXArDpTkfH_^QX5XC-{ZS&(P_N6ohzQut
zCCurpZQsoenhb;BfOZihE#?&DhuFu$-;6H?Yo%>??8U~9Qy-Ji$F$mww3jz5)9z6Z
zD}!4gc>#t_e5~b%SRyhTiKn}&CQVx6)|Q*0=q^2nf!uVKRoBgG=x2tvx(Zq4hu4o7
zui1>@J3Uq3#hFXr$zRN0phdCQKoIlfb?HBG38wjP>&%1(3R;(Mv1_ODcH`Mvw3iXT
zt4=S_096Mf>Odb$cw!WB$9%fHcCAJn`rY>)keiLhTWJqcVcy)GH#3QJs4@i8C4YQa
zxuaA}?&&h>jw;hUysQkOq`rc3E;@5g{W6+ExD<$1ezsh~<BYFgd3Rkc5yBB8rtOXk
zMnQGlPMP)r)lR<Qq%Z4Zo6q>e0lCoV%?8QbWWZaZyakV(w=gM!y=U4X31%#J$<>d!
zESc;Qr%bRXg39+0DlYP~uj{8k8&ysCk@Hh(PYS<JL^P)Iqe?_6oSte1(wJ1qEom=Z
z!z6WtTnTYxSlFu$;Go;hBf3tWBdIhSi{Oo18NXIrd(M7S^m&PX=@-ndO?yr4H1_6u
znCCWY=1pf=t9?50MGXmKW-CdNKRVJFU%X;%`^_5B1tPeRI0awpoFeH;a3ctiNKTSm
z%_y2*ZpPD%mLDE?AOJPCOv7N*LwDS%Xg0VwRM8Nt%w#D+>MxHZtd<;$&3f^tB;6yY
zNuR{U9`O^?3R_h2t??1Bk!&QXW|_4V1QtfB^e9Iu<Dz3470)OQ`vG!8Jh8?ldJU@|
zM*Mz8P1Aj=R~1$6y7oUru=*t?YYl9I2Qi*qBregd^+CWYc&}+(lSk~C8S5L6Xs$>M
znn{4|HXk$;v)F;ENob$l;z-I8YBj29`fENfm%=CT=+XJK*{7X?4u-HT<8Em<)Z#dr
z5JoJf2`%|8Yq^*~@@tZ7G3hv#TkTIamm;pTqFjR>(hP9`pBhu@9;gP6&?Sj?7AM+{
z!N{g=E2q7%M`g%{mNAu~j%Dtx=oLAVy`Wf8heonZF+^j>(_xlqlR({_#w(Bp#O6ht
z_(d-ucy=jbRhSN*BXs4?O78z}U*2kZ1ee`$Mm{n0$?RcOjxpdJces8PWW<~RkQ3-;
zZ<sQ8v}4&p{Z6V^RoeSLyO|wMxaTv{JyUEEi5+}}DPDUy?a7;C1`r9H5u%6#|H?gD
z%_c^lDdEcfZKZ9cXT1{P-C6ZY?nQ?g7lm%D7#Uoz=DZnn{zSCSfA~zipg=fB{&gZ4
zGI&R~VJJ@-cTB^XHBGO1Cs`y3f*Yf-Ab}J#Lrp5pv`Lj93h6QTnVSM}Ty(J82{y5a
z#X>_{PJ8dwDobBq{x-LM2T}e$GjDvt$s4<Ls6GS5Cz!F4Q_2lmd2!eC1YHbzeZN-7
zy{J1^36wk4ifU$@-V?q~pe3@_k@AS-5j;MByBp8c9fwcF{+j(gc{k(X_Qp%Y6F4(d
zmfn;wBS)Nchm3hnEjezQw&=s^;G8q7zU039`LLQXP5;R^8?p=C7>?NBJkhhirrgZ+
z0%Hdr_SdpQD9MaJ;g053)`O@NJZv5Hb_%;3!*qzo-~^Vn2JW@j%?<g1WsPH&#3m6d
zoxsk<V!IyxnKm|;D!Ex~`svPlYK<0H!?I;AX<XAWG*f%im_?EMB*p0|WT(u1g|Kkc
z{JhpID%2~D1TPKRrq?1`h<>XhistLJQ19N*Obu6@s~Sl7LT1tX#@1rX`cbbf$;Lia
z)4G5&=GY!~mxb?jkNU^vT=pIvV!6o@f%pkBHQC?K{rR@DOpZJ&9Scmu_LxQ5BVP_W
zlp426ZFs2AFQPN@U=S9(3KE1_HK#WW%xLzqvsYiz*+j+<S6xN1>5@R&uP8%|g;8-p
z%$$Lc-=8+VM5f_~&rFv>4K@<l@2|xH&E(ec>7GXv=EVqIc%bR?)dpnJ^Tzvz0pi2*
zI*lnsVm;(1EZ0?JM45!>=V(BlUc1OB$u-~}op@-|Vc6A_-m5wi%}p#OP^g#}J8e{I
z9mY4H=^+Oi(=-~6XOg4AOb`%!(-+6>L`5ma_d<PR{=L{7)SJ%_VqPFh{{F(xo;Bv<
zJB>8NbA#)v7^uM(x7FWzoZHZ52KVH!=&fj`9PLo4Wv9m+*l<>LI}73tZxD%?iA-2m
z=cyR5QS*}4G#_B2mA>?><9V!YW_UPsy^L)I!Rh!DHS|?XqC9jqNJ_2%)+GT$$p*NL
z&EJ{+W~?=ecU4HVIsb=`bPQd|_opj)BaiLDP`lF-pUZZ|a$R#u@_m0+k*w*BzGao~
z*i3CQl)^`wNYNAIAxZCa{G|@MpBih1mBlwzFlzjk8JjB|mvokhv+B8?WSYdKR<lfJ
zpY4O@*B$S!`f?*Bk>Iz0@I&H|*sa&kaSiNi(Gy=17W%nIB%`61;hU@MWOE0LwYjFd
z?vi8C_Uk=rkK^1ltL6?jAbiqEw>VkPU@7@5CK{0w@`*%}L*(ieKbRsW@iRojIF+vP
zbp)NYMNs7uly|UgG0YIkjU50-hzN`LoR|N}1A#1zTM;wJkkextucC^EDL#%KOw2cz
z6O;5zyjT}b*fA@q9^GC@S5k!6ZYy>k7^ZpISj6Ajy;pwaG54YI33E@1gikA#@z-_9
z8Wwmkj7ItP6RZW=3v0-ol?eekk|+s0ld`2Jc<uyR8bzP_#}pqskv${5L}ktxb&8>3
zWVRl+{G{A4wt_}71F77h_Tu>3X)nRT_n7?*G|g}ot18BKh;rukDh6WLRl>maVP-P*
z%kJkiiH-KS4a8?%R#XX|STmA*q_oHhHjAiXKqQ2LqZ~*q$!6qs{r1+F$A~_QAI2mb
zUe$0@&D>TS><CuD7hIu<Wg4t(yB2_iFEw`P14xvS9;#r$6R~EH5S%7UK5g7qyLT90
zH+Qi9wC~TEL)XpC!p*|X@Q$mG>ggb07q^0+pqvp}InO~B^P;kcbfTCnq8luZh)Y(P
z6m03%VaA^|_m2FVQ)pdF!iI$Pe5)lf5g=M~^Uzl;FmV<hEH$TJb$008n|ia5=t_|G
z#A0tGP}ok;(xw2g)rRLM+~+i?YIeG+M*~Fy6_mDlk6A${WPolhp9@Y#<VSshja#qP
zB#se?KKJz}<X$vQ31IdGy86>|CiY~E5F|C=87Wi5$xqzhy-|uIP2WZ~&pr;!=`ksn
zTvpj1iN{N6|DLszE3u0t(g2s69dn37yD?DBr%xJV`2oVV<CXjr_-rQ3PO0WCMHg5N
zAQIQcCX#{Xa(mt0i*AS@1D;|pB&$ahKKC0BoJF%O8pqH9m8qx!CMAtMJ(?va(I2U9
zj7(t@mMlx#qlx+p1C_q^!eKU5O?fVlkG7GbcgQ8+N{o26s`mhF6O?C9>Y-VcB&t;z
zJN!SqC@7t=p0k(|CiNyB0!`<7tNvTA_A!LpM$0wK3pOy8`_2ERm^^Dd#qHTJyjkWj
z#M`h|Dc|#riYB8`t;h!=!Hc=q+-1vPkS+G*l7JO7zTxE*`xi0)Po?_QlBo~P>D83#
zQPv(}nlKzsCvj8OgpM_1zil9dZ{_M+4lS(qolUWIy@}x1WxOp<vnUZkzKo^qGCn3{
z?xGhj#x0eXn@mt{s2SfU^U!kB@U7`3b&HU_cTVdtb)c{v95%g~0ta$%m}XdSIwxFV
zO!5|N5Wlg9z%Y){wQ0`j8!Ql<suTv(Gm}xK1*3aK6qy_^Mph0gp1=lz+Ah1A#g&o~
zDI^BE8RE{J-x{DLZH$G1A09U|bHJ8uWG2RzQSB02tB>|>z6zp{3Y#KEac<3d2$38J
z`;3ef+S$Zut~42YYKdhoWsgl6*(pP{RXEv9)i<l5HPc2bz%-XW491SDhw$}s{brq3
zma{23R0<NZ<ZihxhDItncx5p)w=VpeM1O6b2Lk2MH|eqiDpNAr<*p%s%}r!$a`P7j
zz3H3N3t=AMPwyrODky5~&5(7T&3Hvgu?9=)d;;@*fNjigro+$AO!z@&{NKBg*pSDp
z(%ZCtbk}s9t(#}gw<eJbB$mRifX-vLxyh0p+&PgGY~D&!(n;T-tJ27u1G7dYl}>pk
z<_-4?s!<d}h?MR!3y7QiYBw=~sHu5bJzOp9(q>#MHc+C(Ah!M#XUT&gFN8HCg*X~N
zG0nr+%w2j@5v`B!s}h5cKQlF@xPgu28e$t|nRF2EB=9@ykgM!<J??|VE)vLK2czeP
zU?)&L$A>WwF5yZIq2C?NsMrkQ(7heJgkoqGC(G=mx|rXiQU%?^Ek{Y^?z;Cj+7wiv
znLedVCsb*YXi?(qhmM<RGsm9^nhOJGh#&Qk{j)L#4yax3E%xOVwvj!PyjW5wvC^^M
zIQT$Qk6W=WhVAZ2St(2m=pi+41Pc*t>MlE;zF{Un+WB#_VTya~Jg8kpy@_|lY)-kY
zVh<=)*-N`I(^Lx|x|ymJdQzG1DXXVY`hGJP2Dbnc#j>rHl4}tJqZbzJQ@9b1WyD+P
zdfo4LOV7KAAIrlS7D=4%SB94!U>~27_>XQL6gSjX5rm36ULkXrz2qJ?9|Q*5HOjJA
zjTZKkjvUdO;GoLb%U*H=6RP<t%b;<#!&G(Om)ga3)1TEh%sXy&hN#HrsxZc-VBNZx
zxrqgw*P_d3bv6lN3sM#!vaNVKad!)U%!hU@v5UC7fdoFDC8<%zb+K{xoE@p%CY+<R
zH)S5Inwe#F1e~?&j_&zP=2O+9RgaY+4^r3R4&m`SpwQ;<j=7#f|2_&c4gj{i<%nO<
zGXO@w6{NwWnzHdZjk4tQe1bop@^fM_1Dr@}Ff!6y-@p3`yGQFS;nohLbxcEQFcZ_>
zm#pz=0X{^PMOCbH&G+({x{f)=A9DsMyD2p=tG-_eKmYkE0POII)i;2U%Si?)n<gAw
zIIY^&Sj)_q>AH^pZfVYW-lcp(p?>G&vkkD?6YGyzLpQvsnt155&4tdZ1gU-1*Ag)V
zwT3mhNP;A_@YpYvlN7zEx-oo*0N9yg5*gVH@k>=rvz_RdY`NewWIUK^!`M_|-bg=P
zc!;`*LsX!p<d#8vw&BVwOzz;0+|oBL@X96QIf1zG_o}`6>6_I#@KsRyXFM0P$F>KI
zS&-SPxmCuMGH?D6&W~kM*7SkI2&<bhg?uLX_Os_%E_#hm6NttHNNOFbfH0uqO$*eN
z$71}feooOGxa4HK+f=m=m`AWaJJdmuS)$kb;z$t@$pCMX?4=J1iAsl4rQpkMFg%_u
z`aYW5%+XfmKI2w&H+&HNgkQL49a%hvU36Psb!+Z_CUA-wI4kspq;SkUjQh%?HB9>_
z=%02oNhP<OEhik1jF=%?05gZNJG}6)8j#?{NY82CC$eu#M8SHr&Ix)~?a><QWE+O~
zLN!)6oJx=7G3kZFNb+X{tEQlvG26n3D8JPrnTnl`N4<5>c23^`B}o7|_)Y6L8bl(f
z(sh3KcXx?e($ND_L?A-7sh^$1w)pqeI)_%11|yIi1*Zo$-3Kh<PZcCBKwI@+*~uJc
z(ntv<$LPl)7Irx4>qsa#bT~Xs`Pj{n&k+>fQydvb1j2{E+3$+#u^>UkilR5~|HU?O
zgjgKx4*AZ*8yaI_4pqY9RyOaxe~G0f88$i+9ie6$(N99E(s(t<aPMxqnUR2BNjBk9
z$9z4tWOU%6c5f)-ByD;<)nXf@7LRh;Wr<!G3Vp^R3$%+ruG5~W_zmj~J79#20Rv8K
zvmW!<TDC5V-FoyNuxX5W093YZ;zQCplYG${kQ^#tABiw{Sa2|?|L;|D)2fAmFu%un
zsz8Bp)AP}*%rG(UwkSqY^onXV1SrcNykE-N;p{4G=EL+Z%_mL?kf7KhF)kkNPXdR*
zn4YiKQ4|OOM6U>7lf!^@Wbdf{|L0_9-WqBaEw>XIcik{<bJPtrd)1R~&$oeX5;A(n
zho*2#(<R}Fh<B3hkBN<Du%%vxMv~psp?NUOA9fCedov>hUDS2}gP*)9<zrYx-|f1=
zh<cg<8}Hd09UIgluNxc2PgH(~I^gv59m&t7_@a|~BfM#DR_AnJC4%37^0(JZlOv7E
z=uzWnt#s9HyvE$}Qx|dzD<&GI<W%#UzB%n5^(n5vBx*>>eLRBOAfR{@d;LHBRFk&Z
zYIw>cuym-<<p-?F(b4IQxpmZ+-3Ndq%2qc`daSe8G39!%v%3H~F?5qnt%Ce#-+&fc
zYkiXmWStzq>7)QF5%+xSt16HC!rf-mUve;N!&J0CtEWrj*F3@{fPBMZs-Zd9t#ll_
zkc*AfHv{d<-g}KMa&XCPW4HdvKW=92SV<#qv>KZQM8raA=oTkPmk@(WBA^Sn&W2GC
z#lhWGO{#!6&UWEc2yic<(iEnZPoz<6e6bkkxS}nz+(VJsY3AE?U#N`3%J_RkEx^lJ
z%JczYIZ?q&cCN9QM~+twU7$Tj*YCJ4>XsCRBV1yYh)T;Z&3#PLJ<DQX-Y&W~p%s{J
ze=L)na*1An7Q$+bSOj^-FSgSHvmLE3Fnq7Q&`y*VPIX8ezEz!9Z?qKcMLw#NGPCvZ
zcz5k4tRD=U^9c<)X;w<VP(A9;zzY#_)zyHz+DKlq*38D@5;N-ZF^!u7_i>kT3_;KZ
zVd=!x;7XUpRpX-m%{IU-EWd4aK@BOemwEVs1DIL@F+WI<Dr2rOFP6~_52V{1BC<PR
z?sc~7-TI=&-4+u7QpDP1f_Cktj`XL$k*;)DX%xfQXH@zQU{Fy!63Wo1424-VH0(t`
zLB=@L{t}1J*d#wGc&`a@qmOEKl8iUF0!eCgy;kbN1@ykoM%k>=NL2`%l<;kg{{A$%
zML_kNpp7_;M~8{T>1GN^<euG7n}nDbRp=bfen$Ngc@YT8Xr20F`HEaUZ9(tZf_Mmd
zM9NJ7ZWPuIhN&auB<*3l`57&BP8Y0d_{2zwdO3Wu*4OOrg*b4o%w!>%)XNw%x%~B7
zL;%y+Mm%M={BioHC7Nl)Pj|<OQh;yRRq;dlQA#fN*egu|$ic^AD%eHE@(%0lO<iBs
zJDk>hc4l~7PrIY##y0WQ*vMLxJ9XL4bzV?~eBN0mrg2QXfpgsYk~<EhKkZII{NWd7
ztL5cd&0LHhB50O1VsyED?7R^5nj}l6;Iu@y4*qMZ^0IYj4Ob~skzq?D-wIwO52ML~
zU}G*qg}}PO<l80j+dgpos=1qz7XerHd}b>Kbb-&=sa}E?lfXVJ_kEpskQs6A&ucOx
ziu{?0Usa5f_8JIEqrB)4A}ftcAdb=_1$T%bRlsd%fhdwxMdt7P(Ju;Ro}|(OS8H7|
z59ANzQ6zo@+99l;k$99{Y$b%s&fdc${S@WSfw2M+{tg0WpL`n(+CxM6_6Qg@6>=^T
z322Jak1uwWZ7k^Bi5^hDDk0SLC<gMXM}q5t-E&G^ofI%3u4`3yo5Axg(kW=3geRbZ
z<-3eV6M(1{bch-i%$WXugS2gHDM3nshTM<ljV{WE35nm`9&-;iC<6d!b|ntzEdGe_
z$-M`#fzpy26-e~KmgwpilE?6jluC8x$zZ*yAF&uQ6W&CUA_DqeebFu4OUs+!6&loZ
z`nlhHvKX<novh3zFW=6wT?QWvKD31uTH$bOl59r|CfWt3ZUZ7F*1B&_UsvW>zW)ff
z+1f$*fkZ+UI2y@m$@V*_P5W|3>R+h5+Ma@+0Z9XRXlQD#w5F#79?G1^W=>GC5%*r|
z3dC%F{LO-<xon|{wV^(}7|x+8bdgvQG%i5OlTqv9oj>@jKwF&#1C(lBoXyG*zNbUO
z%0o$$SfDAHtt9dk4EJbDJrwpGDG-NX7+7Z_A_^7L+q`NLejXKV0VrkSqkd~UB&sl*
zLH)hPq~Lr<1z|x)4&AHVqt%l8?svtE2P|HKQOVNZ{#q0Lg!6aFc*pSYJNa~iw5`=(
zNqC+6sgdBs`W2O~3j8vs5HT_%!YCC3LZD93x^BN;i_;%`HkIq#@<}62rVkUTuYK<L
z^QxdTlw_doP9t06>)z<P_X3AM<zC9^7v*j%y|C&)x2gJ1_^Vo0M|w__Ct;rG%O9MP
z&JzQah(u!)HA!X0)U-8&pChMaZ)EEz$w~N>zJbw$WnL}dN*-dRsXbY1L;~cAYLp3A
z0hQ%~1r0-D30{ao4|Ad13I%eqruJkN0qFFMO%@E<w)C0>|3KQ%n)W6}$bsX@Vu}y|
zo8*nU87t)luRn~5WEV%7)xyQ+Rlk)7{mujuzFDTkvf^-B4f1s2-}Hu4g^Gl_tZ|EH
z5z-(S4uVdWxNSXVzq1%;bjGU}RjMV&{NhUCNMQ~`5axF{^3pb8xld*@oowheQCXxH
zG~sNYCQ&yzwRoPG=-mK92v!H`A-P*5GTWNO+`j&=emamU3yufac9dGIIhG>dOjTw;
zK~>2&w>B{x@s5J3vDg)G8K^R9064?R?VfYfpVB2z?ADLrI5_*Gb<*zg)iU$sOho&D
zrfi%#oJo)Oz|^yb?eMp+B(Dg3^u9;+N{H%H3z`ANK<EO1=pf7X1VRjMrG6uI6M&f)
zejgatlRKaCX2C9j-UOV<4-7rf3b_EF2NQ(Z05D6&x-YX(&`Uwn`v*?KjybF)b*FaZ
zZ$-b#W}--Qb;*j1LHku$f4eb!bGp7n5l)e^IPFj)2gaYFf)jJ!m|!hd3;Q)6r-^yB
zaOzxN?@C^S1v_ZcJONySRkl(#WT62;`K|x{KOuvyc>{~I-^lm(_rvK$yN^@eaMkED
z*vfmsn-q>E@5w>vUnX<+R3cL?80jx-f+tLuPd|8I;}mIH7ZKgPLw%c<b6Jx333EWh
zn7xoCFP<JH7N5`!(UQ@~gEw0jo6d-aM0Z{5RejXo>k_<4rW9Bht96uV^MCj`Stt{%
z1*mb`!oECg@swA|DzPA?<UOm7Hg)(LMwMB}DV7J)MLGw9m}xijPZJzLP009@QLQ1{
zf4Z``uyM-Vr~%dUq3R(6m{ez$#a2A;WF>%`E?GY33yzO4)iFN0_|9VD^ny;DH2{_L
z{AD*g?KcrG93}TYpwwTZdF$)qCdr+OM*N{lpDJRkagcm+;xD13jyjCYIklp*7l1?h
zwiCBgl{?vSF{?vYf@Uxq6rN9m)*$=>LMipI_jEq%;q<N2and_4Gwx5hK{N_s%6q~y
zlJm8?7U#$oV)k<L7<6Dms13MB!EGpNU!l+Hm;S*P%#IOfbWQQHIcjG7AuufiNKO^E
zViV~BXQp2+HK!<HYkz|<?65ve%oyfJ*%d4ozMcZ5=f-I~Bgb#Ls*2GuXQJq-!+M7v
z*nB!MGhLktv*IS-km3$v6pKa|^+MCIYkG-^)^bo(h&#pbm$r?LVB=%&9}%-iIzg0f
z5CAFF54HgEh2xPRgC}Fq`a)wrsLKKF7K+32bdQ<m6iI?li7J~fis@LldBK725ITa$
z`OAP4CHMe=QUa5U4gjTV76KQ9Ki~J8To3_{P$9`2SkJ9*)QaoYS;OwEsd(EBn8P~_
zcywMh4-zv(4DH6Ir!kZyu0=jCy>wquM5}Q-l%c``F!7vD9L{1>g&8w(*^>w|y0YE{
zfost2xNYRfO70kHN1kp7y)R#JjwmU!qdV>4Kh&7QiC{FF`4|>+a*>i$E#l16wcOx>
zs>gd5pl?I4dQ|tCNm+Pt5|N0mw9xqiU-if5rQCwz7+r)!IE=h<2gZgf9>oP!N(%19
zgVSiHC`pmF10=R<_poN@UXMPa=k)mT&+DhnHi(i>_6kDRRc?Woz{JUBRSI(PcC*7A
z3SnS9WWpmmYGMZcVasX}((Ja!x{fk*Am_E5t|OK>A;3;#RFBNLFq8xuE72!F24GEI
zLrAem-+vsGZeA(_u~^&XRF45UZ%oQ8=n$9<8ayo`LmUAvI!DCQjFZq27jgodR|r!X
zA&a;gpl%{Ns-Y{6ud^?u*SexpmDj$V|N8RRF6;)9BC1R6)3e5$0jmM5XW&!mBf1HJ
zK2r*R)s2wJ_2T$qD-DDNLXxv7vtUa4w%3K(;$yx+>(HzQteLeMk1tOD9Ymlghz|Rm
z@lzE|UL2a~^wES!@<(NZcZ^NrqB2)B2SCg@1S9xJJ*!?NFFNWUg{xNz>sOw<x)wE(
zjcAHJIrBB|({`74!}Km_?|Uf{?6E>um>zf@`fA1;p8RF*OH_jh#<su`f3|)qK@=|p
zr<i^eBv0rfF;InaX}sLpWsP)gi;8zMf5ClkMav{g_RTHnu>u3J@q*KVnnv(>NWM`}
zRG2$J7BY2`xD1l1B>)ML4k)*7?TrLrO|jfEF9&YH*2v%xvZj&R@RrrA=VC*vzaRFt
z24Han%Pquq1SIuDcT@cXkBEe|#js#7WYM25{<CfJ&6K&t%x6G9sX4N9Diiok`bt&q
zWb+3Bc!jibR^1>6-l6*ZO~XH@i_H>hk)^5W^8p3<kA9@>rSXGrgx{dUfaw>eFXdn#
zy244fLc)%vpTJ;Mn^>n^A}*PS41O-fk9kNzh^;4rv$!VAf@GImP!mV`;%7c4>jnKr
zJjp5HETl5+$1!`)kRt#jeRR|D@YsS2s(ul;hA=)e=ge}13mKe0m-+q-w@BVF^Vxs&
z#*<Krg%nvM=Ci(4HFqsj7`_3r>%i`ycrM}Bz;&pbU;1(u+AORd;#3wC%~~ILaI0W1
zcS6DHUE#!~!TC7;;4;SHQEJ-4B({=79jMNWd+#qB2$J0*yBVs?S<?aVIvGyri}m9{
znR890BuGK<9k$H5<2V90;4+R>t5tF|`3Wzt%OfCKi_Uz@|E=9tt~;Uf2dHu7({qk>
z{OQkEOIv4vZ$V4hL7SM0mKEDR%gpHBb1<Ch3jlr6`j(I~B5(v^Auz%p{e9V8<P?Rc
z@|%WXTqtfCzzR(B#Rw}8(K-TGn1Y+Q{`3VE7GeWF*wJ1`_erWWQJv<M>#R<Ab1fvq
zlB6X#%s|kU4P*0UXpB+E^jr_Tln|LX-t$=A;MqcN?OXwLSw<ee6KM3FO({u*MnX8a
zf=~Y)yeVZ&!y|-%xKb&^GF#JIkynEE&=*`Ev(42|SisMd8DC(Tcz-RRebzszXZ82c
zrYs&#Fx?ZVNpNBvxuub+Jb9{p`D=_LBz-1L(3v45hT=8cGTy)B_V}Ks=y6K2n#U|@
z{}Mf1=^H$>uwoGUF{}A9L4X#w5OC*NGYiM@y>n86fM(nyH3mTOR@xxV0sbX{{-Zp_
zWK$tA^Q+nb6oKfO9ZMbHn*lis7Zrd*f)Z3hNoqnUd4@>f2Us><2}>za95eg7LNIp%
z{&62Wkd*LP0%O9IRa5tF;hwXp@B4%)BPQV}d@&(7^JnZ)Y(M4)D+=pOwGJgP?c>KQ
zfd~47o@V8yH?06y(g6;3ufl2U(^Yd12C7QCCPr!pU1R?+`*axK>Sj*-BXFkX50EbH
z5b%XgeQk1)a3tZFm-SwJ9Y?Q_-lXvapRZ<!S@dWX8#6LRaD`f#C{+QG=snkW2%BIE
zk5uBnd#(tNo|Ld3pY%X;V<n;lD8VhYnjS^{7`Y_oK#;+v_2L3ZbivKDQu_zX$eI`7
zt?t7k+yKs5)~;OO46H1nVvk>A>Ch9g3$LX=y|iODg)~A!m?NT)gg*o3*vTCkIMzv*
z@R~?hqz=m-i9yik=q<{#>fUn(rN8;QpUh$jM9t*3h&lMB1&OamiMrVGcxGtJ013co
zWwc7A0bVB3BM+(LO<~;e;F4ZtzDK#Fmx?U_owJvq0n8=<T>|qO;UQ%*u?GKp)AiT=
ziYXN;jP9)S9~JR}2Q;Be$!Va+GZtqeh((yMFTmqmIA?NPY<Hc$L$Yh?aw0q;x~w$z
z=<o3xgRc!icm~E)YuJ}=<Ea@Uzhbj>2+<YU&aUW=0u+n_k=k{&DXqI|Pv!}jN7<RS
z;Y8GU^2hW5A?0GVtQ|QcJ*e<bJp}5PbheTwu&7K;D;)P|mFr)(+OV%or{Km94)(4f
z41<(Up7M!h+=N7w)TB^!*7(+^unc4Xt#~nKG$nOV3MRA?kW|Zu$+N}yF5Eyn{RC+b
z&ibbGL8$yEB%*x?m>XnNWj=;pp<ZM)S-d|YjgIBXzRc8h2ZHnQ@uBHy0P(G^+#I{v
zmm~+J=IEc9CjqGXUhb$bRtmMk{G%<m4)2lg##TvX2f9g~_GfH=$wFp)>35Ki;=!#J
z?wOQfB$sX{z&^+Z?sX(snRC9RzV8$?_isA$+0|)Yf8Y2=>ANbI{w^>t?E;i~mr=)p
z1Bdsd8mk<r9;HRX0`LJgYLyOG)@EZ|7Zz$Y?)f0Jpv2H>(^}!Duom}pg&qCe)#Og-
zyW-n!7&i<kn->iEbsK@*rz(90iK}Uq#xs})T2BHGmv~>%5Eh{lQzTK#F#YvreokXW
zcjL&8Xbq{eihscGy%`Y6U0c8Mhu*C9XG})BEB&i4*KRCqE`BHf9r>nRsoRFRmqNtA
zth#RamvwfW`Z{i#5u=%jYXQZc#;+M|cf0PrvBt?`AHSQkJ2^~fMc6PnomCAP=BO{$
zxEM^XuLJ%{bCxvC-rch)z%L#AbQJG2+W12ALHR?Nnm+Sh2BZ@rm?}Z1YFg6fZ?RTn
zR^&+TkxnD)eNIoIN0V6{txA_wY2u&P=+>iW*#?Eqb47CAQ{jdBC-d#8UB=1$?R=pp
ze<VLk)sPC)f$EU?Wj#?vowC1gKY48paHC-Z(9sapeB;aY)xJZksY9y_NIgfGQTNwL
zG7)=k^mL8xoh!5xu9d89vA16QJCZa>k88Z6>1oowF-G|}Rh;m?H112RF+GX_XlnI5
zur_Ue37Bz2kh!#=VF&473lEd(W`=`_%TeaU)u^%U7=6)ewzLLu@So}sn0ZzivwEyA
zpE6G>%GRZiXSwc~@chi=YUD-1V_l^WEvv-5ym`>$6&Uq;epPM-R3f)`&P_@-7UN!&
zCjt3Tx!j(O;s+i)e4};4*pNGKZ#NEey3!PlenVr`(W)wq>zO1L2bU@iULYqJEM$?J
zO#!1nHnXrwko0uM-#U7;<d2N6k6s(8jFh&$TwCKFY%I-o{9s8wz4`h1ovFjA_PmgW
zhdyPoDH63j;y;OHx^m5Kd}!Gv#4*}wpT0Ag8w7#s++xzIh#hXy`%rXA`yhfx>rshh
zpd<oyHTSutkC72~swo4CMhtK5j~Sqa?KJI`d{7g79CwaqV#O6Lc5NP=COk=9hJ>S!
zf30W8#A})3dmG{DrXcj&=EAJ~6@J|?q%ZkqieLP>3ZyI4C)%QRFT2O+DlJY_Yqcxm
zIDy}>e$zYZeeZ&uw-;7aCk9?<i2~p!dZkUp(?ZdrNJG!H)O75YTOa=2*0(JXH}g3|
zA$2IicKq+GdD0|<)#;!zL=hBKnDNE%-_rxm2HmSt^<|YMGrtVK<EF{DgSj0lGp$S5
zgy4kxfmidce5-5i3FgQ!SQIt*rh0wh;_izFFXqoVhtBCw(w)99byEtd4@#OB-svI4
z8l^oy%7nkn5CiEas_nGbm__<>&A3bNbUt@T)f{oMHDD}>W#(Kihe~cuq7CT|x_U+0
zv+dV%-~7%cF0Zq;0*R?@$-vdF7zb~2E(3TyA$WRxikQ~-Al7fi+coh)qYLHUp`J2z
zW}`q#ZXPH+baQTwqJDK|7#VrI{5X-!B2nK<oP)Pi>&ta~hvL~ubvv(8H~Th>xjyPI
z?V2h#z#63u68Ta&tizpIU%yrn-4MZIxbe$19LFIMEGEy#Ml`%a80OJEp+Yr+Cdqnn
z?uDO5U?eiDF>fWkWU#J^!Vf#?3gjewuqVQcR*M&oS(g;t3ZYFE;DqX3`i@rVKCs{n
z9TEbExlDr+ugTnicU}W3Ub>?IZ+8JDU39$bd1<Mkw@ddeQ=yp|_X%q5*YTx(#7wo^
z(3@sAL7dGH#*wO@%O;!RKxBhp<2Z_U|K0F@>rq2!0-du4<RS(NuNm&nlyWFi&?V$i
zs-3aujF;-F<e^kw?!ld@Rs057Wmv#j=!Z8^5c-ZwpK(90XUu?U>h_8CwJTi@ceOPw
z>kCWm#>-1LP5R7srB<9nE6yI%x#1-C>i2bMJ>iGbeAP2EX80`72<G_VuAN=qLkL9>
zPodYRzLQ(c=Y;Z?V`f&b|F#<v8YMmS2(e*`1`wW@@w?x=0V-RZ;%HxQ%1F<eG$>If
zR{aBUD(_V#x}gd3rQ?jzhmvy`X*_ZwJ+!P3n1mSd1Nh+(BroBPM)%0qYfQ<WwSQn2
za?HeMkE8@!O|=_GsK;FwXI{u0oXdt;rni^?vq`qMb(@S^d{LdcXxGtc`e|0hwhF6q
z2qlo05Qci<9N5<yk8H9j{q{~cXgdUu@&FanOwCA-dE?@RN$R#rG$9s=i63t%Q(acl
zB~YObe?(u_58ZK8d$`9H78v=}$mC5-WE4Hcky&eY=TaWcYW~Wnmq=F%S(6Tp$1)m#
z4s%DJ!IM#I@ZP$y-UTBgBHUb{V;$%(rgb*?s2*a&$3@OZ%J3VaC^moRD_;;-K>bRj
z1~<Uk6?3l(BJ0kmah&2B0Iw#zy4Q~Z&4K*LNbGGUC5TPtI#0u3;IF&Q<8Bt8NBQTC
zL<4Zg`=I8bekkr5V=`_oU&q(vcbO+?6YWt4Po@gaJ1C6yem<)Mf|`;)`DSVI8pgfU
zHE0bjF$vX<URc-*jhH+YOSy%lwiF3T1N(D@ZsRNC(ORhmw?L!R)!dP{lS8mz*NjxW
zJ04SR+Dr^2$gp~pTQaS-d*EuZRyBJ;9M+WO(5DWb)<@;4YuWt;xECQc?JkqDdu@S8
znD_81+S<DOcm|w+*9~k`=2U-=Od6U2<X-{ZJ3*VhIV3O7y=6l!lP-iD+}kGjHy+e#
zYimKnVy+$3;n#o8d(`k~A;V$W82z>t!-4CWr^+*?0xM0Fst8rH>|wK?lD4)L<eNIr
zUTlUxr`J^OLH)3QQa!H>lr7^AW9*78jYZ?nEVk*EZM4nWwF`sG#&$(fcPBL5BO=|K
zbiuw`3TJwNf`(`O&-OMtX@U(VN8X8y|H-EIa;jjTTFM=AR-NuG9D=TcC;ZJocDmSA
zrU?`Z!z7GSWc<{ft|#t!FA;NC#MX9UCT-{y4u)XT0Ysj0<9HDIYRdIg3@diO+6z^;
z3$*P)tq8PL-=@BZ+?U>VaPCw%l$S|1wq2PFerwi>F4(o(HfHkc9LsuAt>n+<dw*h@
zj*1J7H$0w_DvQEtoo_r&&wTl@uHUhqSX;7Qkm@DGSjv{&l3|@w0J7kNV3{$=h)-Ny
zhuR};DwB(+E~a6qfifE%geXhk)3~iY1f+XX?U;MYttmqq467LuIEjIpnLA1=T;psF
ze6yktt5n$MghH`W1Qx>pMM?4tIBO%pHBR$d>)6rp?cKY~+q+?Hb({kPamMt=;oZ!V
zEF7Oz!%(sK0-}k4IF11o?*Yr9=P%Uv4xU=gOQpl;J|}g}GuRwlgP<%V_ah_Q0s(sN
z?j3*18_6>$pfhjCoT0Nc#pP2w%>zcC7b?~7G5?~fO2bfx@4=5nuQ@FMiCPoCmAQ<)
z+@W&^3J(K<jJhtB*aq@sm7_|q)4s(KXf#z>UFSIV_JZ-Mv(G_+b)Lj=Y%IOhGhG@E
z#_KoU*g08VTYJn}YwP+$jytz+4d$X3HQ`3*7RrbTEOc|WO>zw_z{HPS0Z*3x^iy~K
zyH}C&q(nhX2|y>v3N{P*6mhgambU<Y(A&1*W^1TGD@38iytq%nnRI_<!=UAg6#Xza
z<)XtB44@PIn+H;Cx4ckWFur0Bc6@!|CF2EyP<}A=9W$R28pf<MmTEW0$OyyiOyF+~
zMwt&qdqiV#ZtzXLu#y)vL5S(|2@uf{odEeLCgIxBI9(3bVz{W+cQMcKp0O`3QM8M(
zbtJW}YV}QMi69CRbz%!rI2-B?RnrMgi1QSjrV5!~aY=zCnJ1LEw$5D7=HnHE-rlFp
zt|8?Q&FUKk2#FhEX#Kpare>`0U*QJ4QrCJHV6>pjy>%ziy+D!nEK20kRV}7n@-5nD
z*F8QomivvHEj0ItZO?;x+~(8yZx6dn1G+Ls`!Xdj@I&U04WlAb6#|(gG$5L3HyMRi
z&~U&H6li`b6xTCYjy6AusU=wntgH6>Ugh*o`zd0AuY;leM4>?&{Q8cwW*jyc<-`5?
z%?#mpbtbX?2I(0i46a={F><<c`h^<i`p0xp#OHy?ActRavq=CDFm&*rtIZ(^S8MCo
zcRES$xc`Rpe~}H^1)HQ2({+`YcGEOG5ss~{P;y{nky<fX25^a*UIFJ1oWS_0p*c<2
zOHXBF%&@l*U#J;x!i%xHZl-*x|Ao?Qy<rlz3GA32=*f&{GeG4ljd0|O)m5Gb_-HYu
zh7WhBa8}2JOf2@GwTr~jVyM#yQP{1k&i#nK=||httTAOc1oTE|N}FP;ay)d^OsGBT
zHGCrQ1N1SbR@7-+SQcu|!A*s!Tf;;;S<{q0S+_A!ZY?jW3pC--sNZ>k>0_r>)F;))
zr;J^ynkR-yZKU8k=Li0ya)ZxTl{*z&3Cp!Lq?GplwHgPuW3MmTdQ~y-n3I#Ab7>Kf
zlKvVY7wcbRL`~DAfA51!))O8UkQk$BNf2#hWrz82C3V2)hewu4%p}OK7=nSI$S*;l
zEK*t+a3DI&?Q{A+K~KdFh=Kt?WtHHUOLj+tM$0wEEOc?cf&H?vmjC!#$KW6nFFsLt
zXsNH=NrkCBPLByC3jrhDiDo8$Icm^GSo*zy(Q8vR#6HRjuN;9V<&^5mO<a?Sz}`;>
ziQxlz6~eNy9pC{D1)}b)$@(8O4$e}v9W7+G6p;z3P;YGp?lHm5z$b+ooefR?q{^xw
z_Rgt_LuZxn(uzrY-h0hRnHN-_+Fsc1?9%wVUEo;K5$KOeOAK+q1PP63h7eE2Ipoe`
zI)u5H5ZgDO$dx`IWe=KL#_tIEy^&Kt{Nm3J8O#@ow-c?HjN!8SZkxsd)dmqh9aiX5
z!y|@Sydsta2{UqxR+By^atNnt4!|6w|0-P%wc|rms;&@dv|6aftesQ&j_vBz0wKV5
zXS+J0s!nRQ?>gPu*)j9P=5W=AN&@;}61p^)gxH9TE=k{N3k925gGQmdmeBM5Jy8(>
zA<dPaB%*>m{S*Rhb{p(OJ8liDTQCnO#{>EBwot~NNz9n{ryt8X;9zUw_0d=IH0j3B
zsA!_EAU$}#Z?*^{3{Hh{n;`xh7pcx}SA9=A?P`~kaI-%ugw|sMD@ze*3J2J-7OZ(O
z7GaW3NM)O9tFBl5V<e`8;U2dv@M;0CVmIzS@;2yOXYB@<fDC^lfx}4CPnm)S63=Jo
zoYyXv1HTfpo>PKTr!X4NDZjSq+@u6B=lsM0UnLD~^Z#$w-aa~x>pb(UZnhLyk)5vU
z>Sh51DBRoCjRM54ZV(nkTUJ-0nrh0Bjc$T8B{LQQfwr>At_4U=oJn?#YBVCif+7K;
zVrgy11Vm*OPiAaV&Kb|-?3hh~37u$<1<09I&T+;frOY^Ub~YrHJ)_LotoQd8D1T)3
z&uxGpB@`OBZr%HSJn!>9H|(+j@dYxQU3PL&{u%ZBH0JKGIcD|bhw9K;24_^R)Q85!
zLI2E|`A@B1ByX)At69)|&O-tMw=ARl!+_ycoMK;KZ^@pS*RUH-@H*@Fy!Ur^zhAH%
zf6Hd$(YK6h+p_wnF?i<ThhWO8kn})vr?QZV#{)Wi1I#vjsSHvZ<^B1_Lr0F>Q#`5(
zNA7LB)T(rUKjhFI_&sRm@TS|%ubMsB50E8f)b^_7%-!%hdx+xi(nn79^#v#m6^?r^
zlG!6m^lEpTfySimI51Jk1DH~f;X}Fs&L>72*%{H?<8I`#c|!3ooc#bnJ0F(04|pTp
zuqpx3b3=^<L>YDnMoLM9rEM6{)I|aVysA%k&*(?h3f{e^*i$HJH~|gUU7hbv%_@Zx
z$UWy|N~-q-Ren<oJoylMQ{|z*G~syU&~0#zT?sEb-9M;JqgRHmNdooNt|$qy3`S}w
zIZPT!0iuuyy)M2QPd%^|k0%5|>P*0EK_O=-;X=Kkb%bpNYnv2P{7WYl_$+R`*oMb6
zqn9OfW;N%@!$vUc)uZ~whDQJHSna#hj$~Bzg)S`UZRGnU#ARMCoh=bM?V8R^mtHq%
zCEuMto}{l3zy3FkKZg{*bP=7UDFDWWv4y8ln~3IC2SF<IX+@b}zw49tV`5;@%O}i-
z(W)r?a0v82fB3cVnr$D#b`y^SMYiK*W4={F9Kjqb@83T*GU2)y6G|?!Vr0okTdql=
z?g9*q{EB{4_9gxgRCGo|%OVY)N{?SU-%W9d4Yc80GdnY{3_Ax_2fNN%Z{;`i3?5eO
zcK7D^=44sSRQ343oPXfb#SQ?di(4X$ttW?{0$e_e+>!%(nU$Xm?+LgKg6Y=!7;9#U
z4gzi}UNrCi-Zu!b<A8iC%Y7Q_!Y%E#`cy@zg=SV@HxeYChddEMQ7%v*Cnf3^cc0Jq
zZw?YORn3P2a2MZQuN=G7T2H5DMKEor`pR1th`M^G1k|}F(_?m>)027+A9V^llhpCY
zrYe#jkNS`MTZr`~Z{D+B8iaTabI+qvGkOllf?@;ykC1S^nqsxni}!b*zjb8U9wA7{
ziQn&>;NYe%|D5H|;Q2*3z$O7r@c?lC5}xu5UNdRU@CeEjq+xNMl+P(X?ABgSp<Yaa
zUQW^iu^xkqANNa~T)+uz<vX9hW~$rRwXCci`484Jcb6K#2QbcIboGr-6~b}%B)Q#A
zmecs9=;CAchn@Lhu;jTq36GP|U2)wcc~5Yk>r>`$wOgz>b~*6^on(^SJ$_r-M(dBw
zX66XW=@9Lf&gAXNED_>D0vOkB3~XU)F`K46Ksud71yO@^P%0}X?=E9RAu~avB4DiG
z6Kmlkj@Kp%hp^rG!OIzZ%<cIub(V@CMYG}=eIJ|`3B?<M-}dK^kB-*YBa{KVHW!kM
z$*$Erxw1S2FD#0N2H_JLLZGR@MQE<Rd->l>76Diks~+M>DN1G!g9H1SdY-t2ej=ab
zEY6=8v?wA-IU(*)-$TV@Mkjmn_J=gq$peG~@$i*9HP5&Sj|ixNrJd(XozFjG?tm_#
z_U0$_u0&xber(y#0rVBZ;OJB#NnR6O4DB1@!;35Ex1rD#+nzlx>m`l>Vuzcm2tPIY
z-~Q1Ekrpe#@GWf##SU&*@Xa%UNm(uLPgKXTl{QsE@DA1uev0y>l&frAC~N+`-AW5T
z1VTBOIzn#+U=jHYqo3*yf2m36QtG~(c}q={aw0xSb3}%`ukg8FcNsTX2(;DKeAs<!
zRK0aedKk$`20x5qBh^&+6+TIj%se09Xm+hz*8Q=Cr#3s#qow3+($cYAG#mMhn-1}?
zem!u>hGDKM_Ppe8Qh>$UH?g9ud!Enhr2x#UpA}SgnRg$1kIcozW9!_(tLD0>i+wFR
z+YjCHHasomDfr)J?(iT4k^10nipjy}iZHl}&|4-Z)?4eujqO;jI2InZF3BxW5FrCK
z_zgUOm?46eX%x;2B##As_lFOpTPAt8CECvpYd*hGu9wn>^LELeV)~^be=s2C=R=GR
z4N1@%BXBqJ&qfBO(A~P(jK@#uihxj7CRHy71kTF6RGNE1FXmrSA2F|5($br;N_y|)
zirbHbMaVW`J6$9Oi`JjETOtxz@&*Qnhe5kuusjWXQCx@I;!EU6MVpA7el3xpCA#^?
z#{`l<Y;pqCQZ!=Q@eVBulr(6DG`dcm1gB2&$YS7ty((QFG1n#lbBFRMw1Q14gc1c)
zQ9BAj!>#-io#EvtJ3-F%6Ub<vH3u^X>cj~{=Tsx}+l}zoKzql<_qhcuNH@(sX}g8U
z-nF=C$w8vd(WKD5!BpT21R&@IF~a)AlsGRD8UD)$(_13LIbxVNqU@||5@S^|rR(D0
zIKRL>d2@mAT0lQ=9Ll=Py~vad2Cw8vOr*+8FnsqU0RU{Fqk7_PGDvZdwp3udh#KDQ
zbe?@<@mzmB4yUdST4*KH({|XD#+#nPFRM?Is{nc9|IW-GNBfg@`TOkI1ZshAEL``T
zxk#;2Ga!cJPUKOr6!2Ln-Y$S=toyOf@Ruxjl%yWkc^(GHA&K9}HXg857bLd|)^jpR
zj(cMtlTZRI66jEP2LA8KZ}p1Zr8|SiipWmdAc1G*MTQVF#Cp9P`G33o=<s*dljZ?5
zGs{-~EaxQ;=7%0D?C-mWqC1oG_B?W#7inbLQW@s3)P<LaS^k>39Tfy!T?a*yrR1|w
zP^GLfopj>{|44uY0E5V|6{}Tagr-d>9dM=^W;jJV2)KSxrKMm4Re47FZAG-UgQAQ6
zFm4xi27wU$+0;C#MENHJ%5?aYb_A@^H9@#}TZSsbWuTCqO66WJ&y?Z!O_F$L{}}qr
zROqG;KCoUr{whi74?-D*b-K(K`5?~R<Bm2POuEb**fmo^=DHrW__*y`x3H*$+us8?
zfL#afh2fsHG8rF=7s;8MPD(8rk1O2%WlSf#7lwZ~xHCR?7jX}JV3H6&OcipCCPpOW
z#lVppE`GNk&egK&JPU5uQ$_?!yL<9|GlwQ8L8}YnlVp?kQfMM*U=#p;7lvu+o=x^9
z^@$+VBRp>g-CA$al5#wR=+J8Y_|w}^1MU@16<hw!X)CCcm(qP|06$axX02F3+{O@F
zOdES0tTNfzv-xE9@Su1t7z^UV0)naWaKf+rtjzE#$Ii~Z<9Ul}6|MQf@?N3^);+bt
z>^u3sBjZ)LKO%*wtBo~m2{;@#Z1vLr`J5a^xXQ#IfL%%32YU{q&7>oY$zqS@`EUBs
z-p#x$5dse<6Uz*<WE}IunCJaN^hS<pj9_>&q=qjhOK>wonmA3s=z%2dAG`Ck^AUCS
zsM{eU=`!{E@Z`||6?K50pAi~f?tEssAGv=F{*L^IN`==m)9RYWXS}2PzKPKnA`CHA
zF3wR}WTZb)8tz)-9%d7waQ<3Ihaq_eqL_r&Wa#TWgy@I=(=WxhTmmJ)=3qE8Z4?>7
ze1`%bq{CuFjWASkxXk!pGiQ`^v54cP_?lnI-%*yf?Ym*zfUG|RZ2@fy9}O662PD+d
za7$?TD<cyt-6NMRf4SUO-kmADUOtDnGc(uwT<Xrj#DrhyCY&exOYs0EqBooQRftSw
z&c29*L|puScthYeL}*y-ja?(W5OLB6&m?21=eB8s8g}v^@LCf}m9jx*#1v-#LAw6*
z6iXSeO|1;DX1mp^wN(Nyb?=}HC!;b#fqsZghq8w%5K)bfMpUytZ*z<uvsv=KY(2kh
z?y%le>K)6>O<0xdd6Ywcy~z5Z+9Ws`MLTk-_cVryA5G+q)SOCS^v6T#u4Dm`uV1vC
zTVujsNAy(qOIrfN5{FU2>oNNjF09~FyC2$yxjAUxT&2ZQ>^<v8vX!LtQ`z2-WxWpC
zMJIE1q&|sJ4GW<ieC+tbI>Wxtxlf>T>)CI2TAhDr4$C<U)=rBXg97^r8v$%G0t!q-
z7p?i!`M5qdwty;fG~3KabS0vfLUvT4t!OlsAq=armhh(!i&<Avi1hJDbu3M(n;7lz
zpa{l|JruHfr~HXR5~skBxmz1ELw~J^_2pr-mWj@3C!!Ktyp}JDD>yoJ(mHx&eVr!?
zQip)2({*|In%R%6@Cw`8G_z7A)4)Nb>VWNZo*$kro^@ID2T4=HLgNZisU+R@rS9{N
z)!ON`mXhELbRAIZ3rCoG97sy6B^Noz$+23ZyYS@<ZX({gmA09UKL`Dp%m{XK#M(9m
z`w-(zK!U~GdI!2FsM-h<FGHAstWbFd;A7}zwK*ZK|Df-?%qOX<VEXsjuRs%+c2M-6
z|EuS&_nX-b;J&?z`{*m}%oh>HvVt@Ep5QZVW87^RJRnK$MOuW%!&f4;u~1)l(tE18
z?4e0)omLo9B#Q7@u^GW(;UFT=ok$|jy_av|r`Ysc(NAZrE}Ucoqwce92$4>D7=x7D
zNi1PiNeHro)7oy~Z~MS02R8@FR=nb2Q|h@V$EW_k)P?`*`HiUD-}wTX7V5G-Ydxy{
zhsxN}!#(P^xCufNWRl;O88}|^E6gm1EIb}9tqhCr0&u2U9Nz%TI2~df$XBSQjN`f_
zcrGW$<PMyi8L3E4wolrkQ$<G<Z!EI&L4{}|ei9fl=xX3on-JC|XK7fw8d_@I>ByQ!
zivxoNynKPkhllZ=!0@!Q@!adqjQ6(|gpk$2z4`oEYbG<3Cwx;wzo&+hg`?Qe3Xg%Q
z#Yj+bwH6897Ukd(#xI;`Z<f`BC?+NG$~a7^V+&Od9T|(m{~temYpgE}!h_fmHV89H
zhKLCjA%&a6!a;0MVas>pr;YSkl@$L)xLLdg5ZHjyb*D}aHgUfcyF)7pv4>Br)(vgp
z9w+-ov^H1<c-Uh(^uzSvKFIBQ)F%RLknl+~9FZE@=&ZlCXbb;{gZhfzDyou5wy#2j
zrWr$ThML5k5E}JM;U444U>q#8zVLr<yP+;@ra7fAvmw<d3qu48#~-J==crC6(<$OM
zc>?r?T~M-+qyjZGsXa;9wW6(U!=EV<tX3uFz912<@bX9R>$Vo<sOYbHJ>Hiw{4dj~
zRk}@Wl&3QrLTlwWX=EL%5Cf`5i>(_!cdWLAE^&@Hr}k}+W-N=N#Z@o+TI9mxZB3dZ
zIFPs+uHy6EzxhZyC7Z!d&_6~sljCdp;tJ2<j2Sxvf@8{Em?$QSJkpl4Yfx>!Y)OC7
zoz^Dwi7U{A5xd=^b_IkZT<;RTu(5weVR*W8*&~}-D<K(vMNMa}mtge>J$ZWoOq=3q
zO!);8DS;nGtB*Mg5<r{Jc~7IKL<mhBD&S{o1X+8YfjFmEqxmhcXujjKK_cv>e4ofl
z#A59;3)2}upL%&{8=)vJYJzGYZZCe(+2NN|aaj#8k9gM2av-xyV8QmBP@$@FhD+dI
zl(zm_+A|+EpM<o+1-$t+Q)R&7K6pK&Z`<mf8r<~xAyt4obn_I^LO7pl`_zgObE_0#
zBR!{;UIl;9s8kafkOo)a3;7q1kD?erCeymwdRw4Onfyf7%ve5+tJ`oEFi<K<zQ{MF
zvPP-I%uw?ohUh`@gbs~OOY@&ew;-SKWn@B=RyV~d3UDYQQp2JKr?UT-D)hi`I(f8s
zG6;l#B#K86Dm8Tmog~eoLIpuc6N|z$mnH+rSHE+BeiO_%{-0N&p+vrj21xmJ77gF>
z8~HvHPOlLyQuGI9X)+)&5nSXI=2L>xq}sX;HiU-Uuutzw7M5vR+w`q$NE)lEJQwUS
zu?B&*7WN?(1cBz)H2aH4l0o5Jh3CweuYPn-Z(RGxFsdBbhncCD?<k=rN-!K}v8Wyk
zTLX5GVF*@pRVfTho#EV3hPkG0E3fGx>0@_YF062-=|&5@V3v&B{Hl8P8XY|7Mrb!P
zP3%TbSYHF6=IE!DTOD6J^ESE0dX+O{rTo&BjOG;C%eF3_vfc_iQbr5!e~dyqTmd|1
z$JgFXJc5V~Ko}#X>Lq{Wb0s2|0_Q_zY}{Fe-YsY{go|vi^XfGQB6VM(eC}2yyPxNb
z*(LabFiG1nHz)frT~g1lI0F|--EFH|93>G^;dP3>v_cRj1i^R_8;v6mZ@s5oeK>06
zYCoE5EIgs%Zi20s>3>+$!ion|Bz}S011#w?<adAf*<PjCO?C5xX<PfO!UQR`sJYtp
zF+GKJPW<TOurM~sY$X6yo_Re}Do|F}B-HljbkbGse8c0up!sr|E*Kjd4ErnC>ubtl
zL2cJyVHe!c9RW!?*tqcG1247KvExhA_8Ie@=tR^THJRSz0UZ+~JxxUn&xhs)1`Ko!
z5z49qbNkS5_fGiu5oBQ#kFX$fK&hMslwl?r^)$5__1;3XdAhiAF=7zRb-rO1`R5%p
zN7zTqU)O;JB`JC_*{a-XSp+_D3%aR0pP`7yp3}=2c<5B(SM=CKH5c+cK6S6Kb;6Me
zpBav)+0*cO%BS<jdDkBxAHxrW^wKK3-a<qc^saUHy~$7-%Wa9Iq6Dfih~x<0d~nFD
z`y{q5ReKlnF4?EJZv+{N6C^*fw<gQ`sgb`{4*sJsxZJ|Qj`@(b_H~iaT}re}*!r0j
zGkXn_!IqFR{Ln^e^U>=CnxVz>6~;fU3gP&ASbf!=f6PvG$xjU+eAWvX1&^;6Lpwrq
zJ7U3z?pAArwT>`G{%$wxj>lLxp)B`6TNuj}MjCm0%p8)oeIcVvZV|mC@D`Im^Tv##
zAl4`ky#nD^dwVC(DH4I=QDHcLEcgKXBOdhA>e*r0dL?_0*&n>3K71iB-g>vX$J$-&
zn<PRx*;rF=6KCL8Sf#XhCT62%LL=0<P3yR>jtoJih79gHIG#wcd;!rIE|bvPG;Nm#
z9-yJhHi(SylXHk(#O6y*q$KF3nwvcfraxqEls5-Atw!Az?WKTf*@dx(!+CU?m?XJ(
zD0GrRXP5JZ*C9sD<Us?pH?lcN_bhA~JfDvR0Gax2+j*PA7vWxtCM8A|yH*S-$KV7w
zJAK_J`G;B5VSMjeheSv$TP7FH*t(L<HWDNh1}ep#$2L;5sQ564E+|a(K!Y|nQ4App
zy<3yxn*p>D37HPkR#HI&n3eU^$`xzFA@}KihSsP$YX`Ez>-tJSCO~KsA|Ikd_IwNZ
z4HRZ(n^99yB0mt}v(`|6yeBB)25<#qSddY4@>?zAwVg~F`yS~KnN*W75R~dL#~g(0
zudRwGmN(LY-&R*eIJm@_YVjavl6{j}DP_2o)GTp$1U@eBLsex(u{7?|nN7A=a771?
zDLQ+mCaNC;&s|>!3Juxn1{0_a3PFtV%>dUh6<`EIrW(ZtNGmjVcC<d*`HL7)yTU_H
zFgjs+;P1>5jYfeuEZhjEovsLWCQW*K@R2<fqDm;m$RI6Ko;WWIEbk*XO2PRp>jkTG
zxiqkme;J_>2wO;V)f@SVlSe1r31CwECDXIc{P0==z?n@Daghv)Re%G3>-rd@WYbsP
zedQ11=SUR7{MkymE@C?>oAlL5><+$CmZVX+3@llU2-X?j&^ww~{lhcN(*2wHGNpZ2
zX3;lDQK_GkTLLOe2c(U@;ci`6p>OU&F}zEEMpuEb{Pui93iYG&`yC3~f<sE_J1(eI
z&u9rp(u6sq1m;mYgvWIC-+eKi0^4JS^MDg9LCR2#60Hezzu~KBgJp=Id7OQd6hs?j
zINu<)E^L;lr(PiTrJx4n=T<}?fp_vJ08&1ppedAdkDAjN(1ddK@I#r#J@-s<;YsF6
z$2fECV$2edy!r{U2W@l-@>m=XA$Y{WCoA=Mh^+&jg=YC?ChjgAGi?T%#l+N0)NSYm
z*%~FkUgpw_E~qU1j~8(1eOm1TMCs!!j7cj~mewP9zId}}AKd-K9MZ(xHlNd~j)?gX
zZF<Er#vbdlUz1XW6Z6)wnn3Os?GDh)q;x*RBVdCkM@bWi0N5@ya9yUHQ&(8z>35@l
zF0)|UbUcwOQ^?L*^30L@lzJq8<lETzG>je{C~VMO`2xhRGQsI~?O_6-FO0eItTUO2
zIIO_pv2t{#n7L_dLkHNO-BeL?7KbGj{VB?XOk|albhdaIfX}LzK6qLE0ydHpQw<=?
zhpBq?U;hqIl9pm$!Z;eTguS?b$P!mnNaN^l=xx)be+6gbC;EeD7*&yOz&$bWoGBNH
ztyvV@L%brb?nzdpbofi`b!V_q67LG)wL|x~_s=NT8VBgr7aId@0F0<T=kqL?Ns7F@
zG_mJa);eDExd%$(X~uc=yWfZ>5m^R#Jhb}+NqS{aeUF1Z#fFvd&j!ol+HLLjmDBz-
z5pptH(lX6eHovS{o<lD=hsvBSp@5-2Bm@@?nz$>ur^t~AAqG6mr9yU1sx3BZkyE3f
z;`AyWb*MckIG|1pusz1`ptqzu{?Dd7JSq#4K7qut67wa~g=tY~6vy6+%M<WefMMI}
zgwD$@0z?Cnbd@IyfH*YC;AHwv5Wh2hc9F#}sqy;~ENwzFuRr==0H^xXga!I?bdiY}
zZO_$_N$rTFWt@G|+gzj0$yPzv0;w007hkSJ+2~f|>JJ`_=Z^?cWLyi$QlU|z8y6T2
zb0QNYlOG$rPPPV{<u1K{%tGgY;&R^Jg>eelCh7QS^?A(Kbcrx|d!|QqH8dO^4;`6_
z`rUXTz>~=d<@#G)iO2)62It@ed&Ksn)8TzCjs+Jkw!4im3<yq|h1&78ja%r#VRB!S
zb!ZB#%~H(o&t~mUkR6@`S&D~fbOy0DfRqr(pUvCZo}lrizTo4HMjw<_FyS-v4ZyKW
zQLESYIQ+sGAQ5{(yM;~qN2k?BNd(g#Y^)G~qX%T!_m0=v^R@Nvk&@ja;*-V5jIycW
zU$I??kJ}Oa%^Gh>KWNL?`}e;{^v!w9rZ|Z0%AvUm3rXr`j=+tgo)Y|2gdv{H3~Ab3
z+P+KeVK&jLFPiP*Sio=hSqlF|g5gQ?$^OSV@IC`;OgV6`$Of%JO%Xa(wZ?-pp@fj*
zEgxze>vO<bXePUq$|npx7Shm2`*jKxD_qaT?%0|}pZ&8N=U&8y(iR~bh2l!45TX?x
zNA*a)%fmM}Vthyf<9&JExv3E*Qg>d#7xi%=y%P+U>$a#l)MDXNBdU2eU&eQ5%Xy~Y
z?wN-9=!{F`dXfV)sU>5rFWCfbxSMTp0EE_(^Z~JgB#gUw>{9jkC2YS~z(@YYFR&;`
zgOLkxu42-W`XJC6+;4Mo7O4aaRk&=tc4*qkNF}6GoZTZDI(L^f(h8;ylH^iJ!c^{u
zgflim9E4<^&7UhTqe-cY5@bvUztSj9(IIuTI3*KCvP<j8=e-4(cRc#uRY}+VQQVgB
z9f`sD1c{#S_|=cb@@Y8)IK)9F;Dd3pY{nm{7g79Tkn#BJ>{$R2LT~b`A>A-{D_cOf
zyRFUe962%<&I_Sbl)o&FSVx1)%mfWM9N4y@*9RMB7A;?LH>9A(FIC4E#%hNW4AJo{
zYPtr&CM)!GEL|au$|$*V)DothX}<aoeT<+xify@gGIlzZxNU{NOfa|`<9m%J7RtFz
z9(2Y!Y<b{mdAGYU`HA2@_vAQt!gb&SJfT<-nYy`Uk~AU2HuNYP=rGfm{SDVgIKcM{
z{8l+RkMWVb1No8T8}$8FF_LU@u{y14O(?6M{U184UWN5xSkRualYjui`8S7-WIxB*
zkIIkpc8R<I`xsnhRhpyFT_4I|ZM?#|D||j2;?WCWSU;zS+-#c5>_8uS6jG%GXl$D!
z<9&srlm5ipL_ky;MlabTXYE)IIriB=43S9Ei7_G|mlO?*lAMzNV7TA=_czIm%GnH<
zC1qQ8h|G#vvWH-%+)UKVDkBk<1xs_qS=e1tX49}Qh#dMGnE}hkv&g=o&*G<|$eoWW
z=U?}qRf($t-AoXR*!JF;;4;bc(WwbV2+!6{Lz4b}%kMbvLFJ-z4vLxD)=S>YKqao^
z+dOZ={MO!&v5>@lCuCYp`h58-EBcKxzbf7gvL@}$NvpFNOjC={)RQEEk(igAiv;D2
zmR%#T0xz>uOsl-xAWTuv$-%~8Pkv~le!Z`Vs2C+z0YWf~@=S>)lj0t6J)D;lFmACv
ztQ!e@nZtkh1yOmEG?&4dg-w$(nMrK1tpx2Qhpwo^*&)A_>?=keX;qbz5J9bA0&xWJ
zIjl=T5Z=j3K;wMvR;iRG=%K!{634vVE7tzq8S1K5;jQwF9(lH?anVx43W&P-XSje6
z@-`|Qt6HO(i!%pMlC~0_G6&&=qa8+T?>+IYb5=_NfD6iXW+Yh>r|7=7p}UhXm5S`D
zB83_9Gf{`VqWO|cO9;tYkk^}5;LE6J#+uQa05;kyND*$gj!UzwZy+peUA$N5@YG^!
zNVkLUha8#6cVtC@(qeTC;~T&Keu29TGMS3GX>Bld*$j<@<K|EZ^Dn^5#8W5iQ~9M*
z>RrwkFTm{O6iGeu_sZQXN1TiYZ@Yz${X`4d>1}Qscv-RO$PP2F4{n;)biOgs<5G`@
z2@_5f8drFXOXj+Lp5%Ftx3o%GT6+28YC2GU?7P>&i}-`O#W(*{#4<!EN6K-#5@4={
zq!L?5i$aAm1otA;mn~5Sk5eMC9~`p1qJ}0c`r%Z8cFjtVTHosCCt2v0<Pl8E-AxZN
z?!DQ_e*$n(s7BllXK*l!#JJE8@O_lbH3r9E#f4&Xgd<0g%U7g#zSsW6L#8b<4>u%`
zsWH_}(!#P;VtW*L5_ka^6TG*~zmJ1?nv@0%m1vbfJ73(SV{Ov<Fv#Xbcl+cNSt&U0
zu`7UpQWt)%`#$I58z9v$nO`nFvt0TzEUz7dh<(jyOE2S>?8j_G5(`lBj~*;M&}_A!
z*3Ey#fw%bN7A?Qz47@!2La9r!6e4y}Y>8wG2~JeQ$Q{2FaWz1F`rTh$H$**+y(FI{
zfbC>~%BM9oc5rM8VS3J#l)0{$<OsAIOXqQ=QR3hpD?@w0qb^=XS~jYUua7N|>2)Pq
zr$JAlC<u;Ey3DTYD^v39Yiw^YB_y{8yTY62IZ)Aw?nB}dtR({2>Pq5-VqOjcMN|r5
z*b3f)%YE>L_v6(J%fP6q?u7KcW&p9-NhIJ&=C{HW+Xx=S=3T^72#fQLL6@E!eY?g+
zY0}$?!p#L1P1J%LGuv3;V4*hlf%A?L|7x?2GMjlUSNNKkOkklfWdAW?7{pYpc}x>N
z@ssorm3z1KUI8lr>|jDe*?n9`s!-|p?2h+||E(xy@+`K=43cUHq@Zxnys2<7H;(8w
z*D;$i+{+wxk3aGt-hy)GXMnKszumlEbc^F53;34#Ti(+>R?(VN3PJxk_n;&aR?~`2
zHhn>%We-XcRvQarFcpx+a<+7jb?=&~`8{6c3@{e2Tcg&+?(roe<M3jKarN7WWV|MI
z8M_<A<OHM45EW(3kvi9-$wWUi&Au|R08^Q!wxFKVjB=Rc%JzbE_fgaU@F03h2e)AM
zs;OD?jpzLP7j$Io$Yjnz1j^h7@*yzHXV_xIMB$6U&Qyymk!Rbnlz6=9oJJ>+CqDqV
zAr_2LR_GD&tAMbAzCLybH{gshi)7zytP<RoB)-xuq<ky^dzBZN_&H^n%6h0w_%^hm
zs2a^&FQ|`d+Ma@-_5d;a62CBgiE};~4viD%Op7`>s`F)4x=WYtyk2mRP_yG%@&nz+
z)+2haXtZ5SlnL>XNF2Zt5V|207HmCnr*>;K#kmRC1X7HNlx*=d-L>Guacs1o_81e`
zicnD0s7RaSk%P4Y4$+ovZNT;!I+wSW<=6;>1`iY19wZWW$pwgz1bcF7&#C2}PAH)n
zfDQA`<egwdgoQnQN7^o=fuoZg-xi1L1Pc|>I$rS{eW2N7tQi0Byo<R_Nw_7{0m#Fm
zb=;g5tz$wZhH32N9H&wrF*`)&5nljbkfL~}BLzq-RZ=Kap*e;p%yVoC2)p|baNwBR
zV)|pT<I1#I@8s|$+&}(*KZzgtCD-3$LC|sq!aCX2z@-xdVL%sJj&a(;fU(U%E+wI4
z=po-3ZSnLa_%OV^|AMT-II-o~E6CRFHn*3ygIx}0iIQ-mh_uAXFEc79!|s5yMw#Fd
znw59ZEnc3<6VjcaP*HT<DVz?l1nva>!!$>ouPBIWI98`<ZL-@oCwTC8(8IxV7eedU
z0xn=(6pshco;$q-TQ{2`HJg-iLQbZlLB%$O;_=Qu;fc!96bGd$Fa(W4rmoX*)n&_X
zWB=a7g9>KBtO)i3Cw6ZcNR50Uj-s|4ykr#eqE~-^VOn3%rNPESo%F08oiZd^&&kxp
zagpK8Vs+#!B61BH%Vazx5`166Vv1Oq+YG8OCs;6<C{pxJaSBmj5)munVN43q(alqG
z695~MmKE789IvavD}jgh(9ZsjDrB!|u>2`iCF_15KtS%|b54{)G*RA{53BQRskz2!
zMRkO!8pMQyL!US@J%!B#cl(_e8|&*xKBRKTmJG*wLbECn8)Ht%F=Y3M9&XBST^xmw
z3VG<*Qo6%?>Ih0m6#^1ob(IFjG8@o(kYI^dC8K4$ZFL&w35GC)tM9j_72^Mc;CSG}
zs<JiX0tL(_c?QKg82?Z`b7VSiThvK_u>yPwzn*vE94u0CjnU!Dp({5Yt_0l@u5-cv
z`Zu&_P+77vP@rj)Sf)dT!^JXSLnU+Q6JmfUG@MM{m`Qt|f&-BR%c9&ixQF_}&^f(1
z-KY-<qlEIibMW9eF8T*Gv&JksxnVOSDk>(TttMStIsZ}J&T~RmVPhPp-k6;5->zbQ
zkH7lbs2RS&@exa_Dnh*r_NruQ5*6PU>md@-9dCs=@>i?iHt0{%l7D^lUvdjneepn2
zqNp6sLwnZoX;17NCWmh`+u*<hU@`&)!T02VG0-)baD!K@Bozt)jg=c;X+sL7M#KW`
zpDY*PyX_yGVcD#x`-;FPL@rnj_5>TmFl2cO$<3qWv!*@t7qIAjkI9u<3I}<8l6WMZ
zT8Pbd&WFpNJ6tY-7Y#K6+mwmLmuVceJP5<1+Qecg0i~feDT4pm75q8XwNFn~p+Qs0
zf?v95J`B>j1gmoy86S`?q<jWuEO00rI`%|)k1#XflhYgA@W$3J-nv*1?`bb4mLRxA
z#LIfPcN@9efVRFLZrLkC=9E5!@%5-R-{F0!YQO@>u|R<1Kr<^=24ie(t5^q_rLAcq
zX%QPa(ByEAq1S=d;Drsk_21I4j5Q5IFUk_NEP<`T)g=}+b~RTJ@C<VHj0-278+u?s
zut~Ou&o<V*N$J|>ukg?s=|{YJ$HGWJxRf#W?|8d(;)Iz~2@JO+juK~(a1n9DAx4Fy
z;T#W&#ZHvVgC2S(FRSbh@-SBuO0#QdQs9*`7Rz4bWy)q|8Q_|FTBr5;Lo<cP6gxVH
z<A%00CV>!;>C^PMNzqi+VKXV3qHhNQ@tW-F8`t2t|BS(nnO01vv&PD_FYV_Pn2@2l
z)tun>c*II1A+Sw6$p^xK4QMQRjnFcMGtSWU)s!1XtxC%bonfb!D*Ezv>scwLZ#O^0
zsqz#yr?Ei0)%a%vwr~}Ph&l*!R}DKN$G``kCSD>NXGsb^C?o{Dfj^(B!joWWec@Pa
zbjT93{tQhq`&oUw5u#!K$#Bb_fEP$mDfFgdowkkQJ5)ig)80Las)}V>=nUx=yzv@^
zv~>=mck0g-{f=+)14Emdu6L9ek!QcBL0ybe3=FVjxb8=z3DGqkTNt3*cpw%wp5vZ-
zH^Uj%6&4DPhS`J(9T~<C|Kxr6LxzZEXvM#fDa086VGbZxm_5eJL=#NPVNrIrqzZFn
z2=&3@;fDE1s$@|AB}fK)G&{ifS#vyXp&8?|OB)$LrmS`3BphS#nSiJQaE)#JQPY@>
zsOHEv##GKG;Y>~i@$?a+RRMtgdCH6b%Ut}s4a41SVO31ti%fu36%a&V3xsX}kS7(}
zWf+fx$QTka!k1zLF(#IRk#6~JV!p$kB}>u43}m1F24ZKMrAFz<V;I6h?jZecFCGLf
z<H=Pzp7hclNE*lmsP7~0DYgx{RT#GXkVaD?#tSpjYl~^I<V((<H2Gy&NF@nXKnkXi
zgPkj`QV=BG0<Due4RA9$S$steU5+cRqh+BtR2x$#8%-idW(5D5dcs6?;HhPJYb)<K
zoc<{-i?``V%ZCRCH|SF|hgJ$hgt#X|E7!QdkF^C+v16{$G!1c!!d+X_Wh|t1Mk680
z`d=3$ld_Lf8*gD{AkaROKxpd_<`G&0Ts{6)^v-5xfGNjDD8n9PEYKlkc(O`(5!h^)
zn|#cWaFAIFJ!TKG(ZQqoaASP8TRccH@l305ubk8>Z@z5P^DG~8%fnA(4)7}`)d$O&
z9eKKpAcR`=k%t;Z3Xe58lDXqP`%s$!ops`m;T7izRMkpWx!k2mENPkvMywQl{X(s1
zVdEtpe$Lx_=%!d%FunmWrn97g8AWBBK*SxFW0WWq6P)F?ZURftrezMBDD_Ed`q|e@
zG@O$Q2?@l#JD8k=SwNzD^4KIbCOQqj+jhRYv9QWr>@dGXd(WLa%*<fv4%L_6b-hdr
z;BDpLA<ibAK{_WS5Un0#@z&<Qf+EMO%ZO0XwZ2-KOFV&?8roPGGc3hGzzVksq|hs9
zRUyIBwGhhT?X;i$=YRHeJaOC)zlg`PlaEZv%1@|1GElb=9trq8Q&q@zjetiZSc_Oy
zj{ub*Fw>-xMwOi2#PS}9w|BX>1&|eBrqLQQg|}m4w!gdFeQ3FRF`nqo!8<$OGT%aT
zZ`wSYnX%4hu4ib-*sd%0RB6%Skhha5{3=bQ%iZ_ci_142=@SaA$u2&%%CF`<qZqr4
zG$mv{AcW3$9}gp5i`W0n@i+Zd^P{rP_{=1}Y5Hbjx8+(w*0xRd3vo8PTk;m}!6R*v
zk}Ml#qXY&)2*#?jH{C{nxeRWd@9Hp|P!5|uVVc|LI;}g=YshDsZJkf3-THi-2L*2R
zmcl3n!btMA*(+p}FJYNy$!tjgJ=U{;d%_K;G=h2l@wsii3CF<N_b}}{WS~1tn7bJ(
zLnBCb<cK+qvrEP%kT<j`uF!_gRyaqZD)BuuXXYJxW`RB{mFDPjJs+fuQ7BfvkvrDe
z)1NK%?<ko&N|`l=9rL)dhX;EKzcD!x7HHr)rsu__AwzGbM8u_uvDR^jGpk7#BqgYJ
z#Ft2nV|ahz%d8^(#+U7;0VI@u#X>5Iwyphz6qs$CV=;sZ_cyCI%^*R@IC6M!=x}+U
zK}=)cCy5Ieeys8J$T%;j;CA^Q@-C6JYI=6Aq`Q4usfoez#b5Z0hQGqeF4d1Uu25%>
zk09W1rZ=J5Na)3Zw4A4^k)o9@GvYH$x8&IJ$9Qew`s6Pg)+{*1@|I%AotL2?X6`7d
zF^jTD3b&D_B1o7R(-owjNgA`{7)B5LY_HyA863v>0!7elD8WR*x;GV7=)z!fzl}uT
zuv%QpeAB!}hrKCHp<>jt^~2p7+2w;&sm6<|6%M{~!W^~jg{xHZB(2$U*Ir1rz(&Fk
z(gG@@7ehaLefjaq8I!JJS+^5rg|^C^9}o!mK~SGe3)WId%H*;fgbqtozG+@ptlTkZ
zSVPka%1Gyx^5*!aTZS4icBRmO%QH$F`f0Oez4;8iK&5W15clR2=h`G~hxJEw;n%fo
z<-(mun*?9;gt2nshO>u$7N7y53#t=0^4TJh8-^cuCBZPW{LA=mPF=-j#6wnHruLJt
zg)EYmlSwz8UqfPCk#+^A>ZXWfeHfEb2DiFh7nchYxK>xOaOYDF)-P50LvxR}kAqVV
zj9j;@U00OFYCoGV7dVUrUGnh@>cvJl7SEZS)ivKy9>BmIfGLDO=ipkJCjD?dee6||
zF+esV@~<Wk*svwx>7glJnaXTu<S6AqLaZq}E13XeV2kmZy<#<!Qb!Jg*DdO!^v1tl
zZXhWRMN6%7P#3FK3VE%Z^tDl&CIB#(IYsdroF4X;s1n@Y2<c!93eM4H)vnpM?zF>0
zDCx~6yg5Ny<amH)(g$iG&;@3>kvTl+{pyE708bFP&{;wcu)1uPti9^8Dp?h3nF%?H
z213KuniZA$Wt4^eh>)@XCj2si++>*+h+U9&sh()gcY1F||JJ0fs_yJ80k)Wr>MLfw
zyi=#?sG00>KPP2JMDYG#j5g^7S(36^u?FSS>a+sAB8419>mg1XTE;~r%w)){)rVjD
zsf|4gZO|quvC~n#G?>_5fK7=O7^gqPvudA!MI|sn_A=OIp6x3=V651U?78CPr0=Tr
zv6rH_um@a5=(Z)U@Im<MyEEO_E&K}X_F@|jQ8k6w!@7HB4DQWob4zLGq2|Cjk2fXL
zk=&6S?Gbm&4qy=^&+=~no)`m8YNNLutyfm-WjdiJ;))$P<CZ3cY%JQ%*jFri>U_*>
zaU%m{DouAWUsL+Uxx5hY`iY_aE9VM~vFrU%o!?RFBPA;9`L@12&ztPgyPBJy4&pHN
zZFfE?3lcwI%+uhA0UO-<)Lk#czmcH}5Mxwt#e+z{wb<N`5B<{4xHBBHt3)%-evN(z
z6R#9xO_r_@i(FPYFVqEguvcd_Dglh2Dhp#b51lJEf|F8g`ILUq=`arQ9$iqgy^mlv
zK2j29B>&QT5ysg=d4V;LT(kxy`2vP4;55&Zw-i2R*XYpSY5OCI$D`f}tXTY#)3U@q
z(4mhB=EkJyPe?Kh{7LT{KfGD|n@x{Gtl6~N!bIdr)YG!ztRTE$eho8&N0Xyl#R?+`
zj-+$>4uXLpuq6niHu)O3Xpm~%Fuwobl=k%RQL)<9j?9Pjfn{~zoW7!gn%z(Gu!sqZ
zU~_8TPR)<94rIP(yqAQ_Fpys>-<WQ1bj79p2zxeGyVybI#KSSXzx#*xg<>qWVjz?(
zU`1ICWzgdiP~Ii>w=9+knW@Qu<J2ygCi&cdN7)==x=Rl>tj9EsW|faMz6i^O*(Pd;
zpqpg|&fSTMraD(Tr#Qkx4|25}19&}Oe2{2KKa?!cfwD8W<sw-q1(rt~=Oxu*VQbA4
z^IWwE*~0<A-AOUY;Aj&lNwKf{uNQ!kjo1oblfx<pFDt)nDJgYHq!WXlYy&bQs?j{N
zD;9@-9xe^x1NztW9g`VU1Auncq?|Ns;`xEYzU{mv%i7yo);k6v@8-8a`hn}(9k||y
z(SSBp7_~UejTRNA8FNexK_(d~c1`xo`HpgO9*Om>NFHoWvGL|d-p}-kbOy3VKn^Nl
zDJT0VVNW8PV@bn8kLNfJn?b{5g$ie3CBOf}GrF7?JJP=ymWz3)wr{(b<fk#ozN~5V
zr5N&Xyr}okYN5%^O87)vyXH_zp<diWOko9G2Stj6@CI9lxfoc1Xd{a`(vcvKIwr8B
zNsE9Vx2E{iFvhtT)?hawt63s*xn^ZhQjVt=!>lTTEHlYZD+<8_Ni$>BL6S;lmSbxO
zg@H})wceXv<J3-;FeXKehAez62RgBwp_sp-&&40C<p(D<ihG5|+kPR*5t_56n_wkx
zF37|hFePztDQ;kW%Wg|XI(vPjC=zKFM?G@HD(G#A$n3CH86mSOaHbXww3Z-NEa3{M
zJAf^Ru05>=u@#Mcf08cqPmE{jD4v=s9A7K^yfpGWw9~khViQ6UlZ^1kP7vU`V`mUW
zUavUcZ~1?3!vzA+0~wWFQi;v*Sj$IyfhMEcc-TS-`5QeqhdXWB0DM2fD|a$t^l+?v
z0+PI$O+nR~LRAX}sARI-mYGRvFuML3oylZO%C4$HA(ttAdt#mQR4%@1UmOq7&7%jt
z^DEQNcY*ACOkmBr>WWI1;*}jgSs><{tacq;Ypt)(ztO6X?i7Vu|3{Jk`K_}z6ZG=%
z1f?hhrJo|==qLbgNaJT~{*w2--~E6ks>ezZmjRN|gwU|mew+2dIW}&UF5)=y<fhFG
z+Do&^+jSqFIS=WBQvt{6J}g!n&`QzGrjzLVwbD;ik6BaFq@4r2;1)rA@@U}izpI!X
zFMzJ<YH}5vu9iO4{kU(<ofXAnwW?&Pf}PDKIi-g&01Furmc!{jUV}Ua;#_|Jmg;4~
z;=W?hOLV#VRE`i5ZZvP3qFYC(wgg>#F^m)N|Mn?5wt+H=Bad?4-(9XL7fMoo!GGKT
zCpyQSUoyW&qu$rd>m_q1OE_A~(CP-dUu@@#e>pNkaw<HrdxcZBMEl?<4X)7*jbr55
z(Y@p@R@DJ+Mv$1|x^U;i@s>y&Uz8TBSEClmT(o%QzkYybd=|-0vwOmHDv7RTX)?_x
zNH`ik%e6p=O(wiWq32FGw8*5En-?=%>TDodQ8+TL3gZXekY&BzY5{pV#JK2PcJ`FM
zMiO4?ek=2ec#-R6SVwzHctJ45&4<eBexS>saqwh!qq$Dve5pIUFJ3qAA~FBe+*;W?
zFoz%4bCfSJeWGwITry!b%jGo~XY%sC^V`3KZAd3zswZ|O95~;lA>V}Y3*${oL?xUA
z))g=`ou`-tDkzYe%)}nxW?Byn;y#X83%QiRf7K%_@pf3`Km$0mVQATM3c~fgdeAE8
z`+}2H8(mjCAD=B}NxwyD7hy}W%6YsArtYH}l!o1D+_=hUeeV<Rhv!q;3N|ug;z~3*
zBLPa)zmf^+wvYBHtsAg-C<n&OdQTUl!1vEmQ65>*bf!F`Xm&r@C{D0BFTZI06D4EB
z^X`1U^rZ|5>C5J$r6w`+9T+`1DYLI}oUU|<L}~tmqbVeT$7lm6b#KYbFC#I!IOuiJ
z2FJ;BdQJn)2)mg(V7YU>=tQPsh0EwWzwwJ0!+j=sNdo-B%8`o<QDDVTeL5~~33gHO
zOR&c%SfXN~v4YtQ1?T*xPKGjbno}@;B4HeTDSF(RpB_$pu&v5{phI?^qF3X{5VpXT
zP9a*RNSdPb0$VdPJls2{w^`+0Mp$)|Qd7He0Rwg3-Fd$l=(ze~c1DoxIm#mt_9K{G
z0lrfTGc7b0gA>-J4<yTyU@f2ny6XZMOW*O$kzkyQ*9*rku*iO@QVbNiET5*a-zG_=
zrz8k5OH*&3ggz1auzz0VG;~xik@XhSEU+Sw=X$Ks+A=B-dc4n?zkp#rZN6#xD&BEj
z{+g+ffrEN?66BUd&7G2M7C-%Og1wgs>&1;sGQ=w^1C|)E%qR8#DD-m>Nk!B<|8t_m
z8_U<6{ym-Ds~M-<Ig#(-xPTc-{ge}|8FwSlBwH1jsGmZv^7zuvND@C4fhHf|JSa7{
zWiUoAxSE(v$dK)5y<NQ(jBZ{OiGSGhOCvO4MJmyoFsNiS6pz~cTr!QBCYFqE{%OW7
z1tdOA|FFdpB<yX7B+h3w!1qzty<GSiN#dOfj~h(tQt1xOk-Qw?Y<=!A&Dp9jRNVO-
zB-f~2o$^PNN^~XnInX?ky-D5M2#Ywe6f9Wud_~}-ZA4f9=jYN}I`lY`NC}=YZ6yiT
zjH$6n<$`?ql$%n%ytev}w;17o-$O~WluZs?D8e|>lzM{J*xFBJh`;Hmvrd!GRmGX9
zkU-0OOVaN$ba?v6v<ePdsaAWQeg;}DqVwINHa};6+gWiIIjj}YGtRkAhQ7w_w%Q@$
z@^RyLTkP-k`~TI}h*`EO;*e@tz#Cd6@FX{%q_B*OngHwmiRdufirJlpvk3Fg9@-$(
z?aL133oIb6oEp0{wp2aE8E(LOeC~7hn5Q`&`Yvm4emXNr`9==#?$?{ajLW_#9Q}in
z5B#Tfp74FnllD&M&@`g{2+a<d-ZrEYBc+<aDl}fPb6Ej6ch-#*K{{IV&w2lGq7tGr
zB&%LVy^Ie;ZH}&%q#LSmiqlhwj6!^&6z@6(1!SH9R?g+i^gHO{LoAK`#X1UlTNnSV
z&hS_23(n$YN!I<zQsGe{nQ?sPQ6GOiLAN0#5ya5e!`6N1t2vwtxr7KREMOL;&_JX}
zEI2e*aH4aq_M`3(<kszxctuzuzHR2#%zVkhKCts#s@0*imf<GwBOB(VoZUopylc`z
zM3r2^1AkSRW77Xh7w2Y1p;LWZ6!_J~bJ76CK~aMcdS6#pR6X+{O0gO1nSA{&Tp}F0
z3#%`3VBTotv~$jnVmV>QD?TT_twgnxAj2OG1oUA!5H2{*t<Zi&OZf5<1vZ2<;)R?e
zy_01Dy~?0J1z{-!?SB$r02z>ctSGc)6roX>+zEG^CnT4TyRjYICO;u7f1cI`(NTST
z`Ag>G%THO;&b1OasVI}|v@&O@yL1Qb!uTN_ggK#r_@r?5t)gD`i1U&)x60{i0N-py
z36A6{>7%EM2eFNIx?^l1`tctmw`?#eh%hZl>Pa!>kCkFe3lhLfI>ydX2bKXADSVTN
z$ProZD0c+-q7SRsnDobfswE7Mk5zw7m5S|B5xuHy^k|cL%&046^4kK7DWEcNZw>V#
zIY7j3wXiB!%m}lI$}Qd*-~4fuOXZeYG|Uo2pkhO-+wAqfz71qhRz)vhwyfpb&Hf2R
zMjBQQBHWR)gCGT<B<r{W3ox!Zk~GC|MqUn~x=pjDIZ!FwgRm#b_xi~i?&hbO!V&7F
z%c7b%7d>Njx6MMEnwB+GuV+(uktwO)a4Z3eleEfj$q8RV0b`r!Mi{f?BH~O!x$2?_
zLCIwle?&}p=0D$ZT0r9{F`L){(<uRs2LF^vlAFR8^V3O5UBuL7={JaxU7c^}J$Mo(
z8Q(HfxJLQJy7^?#ff@GcHxfBv7{<6BvEX+Qv1Vd}V=Af~Wc1Z>{i4;ydY-pkKNYd#
zGzn7ztE|H!J5OZDWVz4Vc8y2<)W5yuJ%xC@2CoSv8xPVD72fe;8ioaXP_P@xp)V*-
zr;0OD`3qipNs@S$2u1_$m4tNk^}R^M{<Av5o##5Q_oH#0=ks>ehi1c0&=x_NH>}3^
zC<&hHPSNx${ZF+hVv`L!bIac1Iqw|$_6XF(9p1#r)peJUts)&hENK3cO^K2I;OE~{
z6DCYnTi!c@44U^rjZqng??yBje~_Y>@Y4C*p-&)#*k={rDo;|qybd=8j<yRqJNzdK
z!aLQTJG<YqUMcM<^_2HmyWTNbQJb*MHR<kuuRjx{b4M=}9{76o*b;H?0-;7ueDTti
z<_d)i4!5G0MgI1HXz!6q)K)@BiY21zT>0bMk%pJPQ{=o}!!05qOu01y7sXH&7|+bT
z<gAjhvLsX#v^9JU?d1a^q<(3*ViS|U@#C{ma`-iK(CjJaHV3bv*CmRwgVyKrJV7Zc
zr`UcivbByDhaGsW#iTb2Jpw+0MU6~ye#$h&@G`P@Klp=v0()WNNTjS2*q{6~<)cI)
zRZXUE_N(kV)+95^Y)a436~@*Une;MxSM2&c;s=Vsh4TSM&G&he$0H;woy+D78lB}G
zs*J9*Xzx<hS%I_HU*?247AbtaqXVn)BX*v%<rzni7$|{}G7$hFRL952W;n@$XEiwS
zvWfio!Y}+Toi@JJD=95eMu~n$Z6?!j0^M|u#VHeY0|Aim4TYr%i+R+RcvAF<@Hx!p
zdpg0^dGsgrGb-~=M)&3K;8-W&e$3=I4wu!P0Dp#2u<cRSI~WlAioT_lcyJ(*;+PpF
zV5vB~_>wlgec#@D%a%V*WXuRuvvOD)F3(va1mHm?lo_?NB*akPOr4RF)@7L4N7d_Q
za5movLYf1doAD{pWm<(7Rdg0G{`rS8-4O3_C3TBT`hwQG%8+>O(PSeh8-GwZ_MhV5
zpo%^)FvL<m&V<SbB!dF~;e|jakQ%us4R%D7HSx<GOV=0Q9Sb=NS?n)}W>*v~n^xy^
z2BRmy&y)&XtgxhTakZLUVp^@r&2N^k0AYe&HE1C}^6NSm<bqn`i$5m~Oh|Rsi&l|F
z-7XQ(;KtxIQ@cWOQBs@<r3##o`v4;DXaYNsb^s$#x}Nba4L>0nU0zGoL;MC@r+{Qn
zOfRxM*kDA)_z%$q{^8vFx0;Wv3dap6)L5A<m7D@aAx0^%-g$&E90U+sCM&We4;mnq
zFBVVgd=h3y^5^7$Eeca2o?W1Kl%@pvoHn!6un<LSR>zU40p92i=geW}Y3~3IPLOWN
zJzrq^BQ59AX;(?1<vt1#HEcs|=(zf4pWTWvaTOLcN>e%TnJl!meIK-#Xre%XMzt31
zRg8sF`><Zli)O-|QVIEtPLCfXVsF%1(YzoflE%#ch?<{y+w!KlVZOsZ<jW4xz1k_K
zi?j<B{F>`lKjpp1!MO9(#Jhiuziwy&KcVMd7%UIyZ62oAE4JhaajXJrLTG}?61mh~
z2h~`JmaY%p{}VOfF1(!BUiWsh7ghrZ?1XVLNCLUY^1yotxt#Wes|wd9)U><!L$6@*
zlloV6UqD3Rj!piI3h=UXTl8}2y1Em!fAp#3er_MUJ=0H3+4DYp-7QGqM3Bq^f8dYi
z5iIL~2GAxa;=#YM@Xj#OPA_{eD5S9A_sZ+z0c%BoW1tDS6)4s3X#sEikraa&zKYmW
z#LCddiET+vwJ|{%S}7Mx7w^nz0kYrwpc0K?F9t~ZfzqnJfNLkz+wTbhqpMTibLXBC
zwFds|)$i!cU4z>PrI)$X(+3LAqay@w=#ci&@Npk@0*k!%c@X;;;%DiI6tFRR!9Aqm
zK@s6_rN17IiICpH`AhrkLxNiHlHmEYS-8R~XUwGW1kLPF1GIvufVjB?N|QwGgYdsV
zG)m%G-|QoN5<*^R{EYH1%mn8*hp+WB<=5dkorS0{SrQR%^k4g|zTnUbUbq?r5A1pI
zQ>0WVKq26U;P2c9Ai(3zr<&)Sxg>C6FS|0n7Qw(#k}uhvqY|i!%l@~y_hf$wJ5~`>
zJfYmYnWT&kzNxE8q8(W@>A2GXo&}9aoSKv$gne~5Lw$`JkRALtV!wCpR69%Z=Qcw9
z%caRd6uaGYy{~%kU~u%)O0nfGI<ML-8HM#EMc(Ebafx!ev<6dVep4ZkH@Rwip3IeJ
z5q-zKd15iu+u9!-Y%SY{Q!^G*2RkhDU`K!AUVmG_Ajg{2*J_1dYf*)8-9+FSEyLOw
zIL5Dpeo8+);JWPIOPs*EKAPw~<=wj$Xi64(Hb{BtGeNJNY#IHD^m?=PI~_)GAzAij
zJ5H$CZKG@67n?7wF7b=f*Zcnvr?syJb&xp0?zP{ym`FDh%B(R>=)_p*T9Wyq%<5&_
zRPW7J?<szVG5V*)S}ii7aFjF4L&HOIYM_;J9k1ruC$N~ksg`jDZ2!FFc<!0miHLb^
z;_Q7It5q&F%VA32c_`fsJAyzhxfmhqN#B}J7)BJ-_!+0i2L8FCv>VnIPSp;%{FaK+
zsq@O49|-_V617TVpWAEOUMdO$!W+L<2orO5!d6cQK{~m+noiCBK`@t6@~{uR<Sc!@
z>2-KUbGE~n?daDXy_TD_3LUNdwcq?*b{}MK$yg9qOObOY1Gkd$dlMnk&1y>+nUrl%
zlUFC)I4m(DexNsTtY%gc=>#rT{y$5KLLj8Mgi}cxvrUTHO=A=-jh3InF<$-s&lyHb
ze$X&xQ^pCN8dH4ZMVTp4Nf?30cVc_o+WN+6B~R2a0{J2iC6WQn21y>7+={Uv-!N_)
zcwd?Z9T4g{vhve*(CFUpn;FXR$^LO&+vR>=Pq9~h4tJVpBkTtErxgKOIj8+hY2st5
z2<LMu*Q0~}Q$c@<A2}%0%+y#*;vS<#bY(Sm_??gcsXDmq@9}%|u2kMG2l;V5nu1nJ
zb2s4!D$t?;H>qaJnmj+>{NkTCcU@{OG<P@ML(jDiIj35Oex(*IA`+PMu1((`kNp3a
zFJH*s^fT|nEU`^~?lsH8`q|fw|K@@Jlh-U0YdrGNn;IWC?PJczoXFo7Mo;)B=5rm7
zj1Lo!m}YqC*vD;u<@38vIj!2qqsP3d@ZNUlEVbI^V&IKO-TI8mgBeW~U@9B;mug+%
zvYUUlwrYo7aBq3s>soV*m(13^<#6^}Dxs{}$KA-K>fi@w?$zJYsnh$Z^xPYzu7=*@
z>JiQ98<8<rvVPBtE?B35X!8pTYfarh?M)sUD7C(*`lC`)cirNB;ol^Kpt4+RrK3}n
zg<6*Tbj@=D<B$(a>NzKfX5HzBzZL4YLp{-&O`LCRk1~waI_>XDb$!cpsls9Tek~a&
zd!JjIG0H(D(cQYK)@^p|O6>ZUnR?i=dsDT8H}A6^m~8c`VhRp&2ZH7u(X2B6L)0<s
zcuiwrR=2ei9f|^X_>AQ@yS)EyLI2j3*>*OHtbO*}xSQ^1ETy6x7A$wj?D(Vh@n4&s
zO6J?n)1ztZcha$owT@uSNjFW;e4m>2>6z@!))vfNsq^FB({9m2h0X76d;5aklYXzc
zO^1~)YJIaIrNq~2L2|C`_Ht^xm#`|yVf|f4cf91B&<jqNhyPW2G12<*e|aBUel~F;
zY8g>Fbs{pB1ikf~#l&2qWjPqaL+p9w*SzGS*@5V=N>n;*qpO)bt=wF#3pKlmCf4FP
zH`me9v+9Bz%b<HB-`m!kY(>401A9RMA-!0O+s;31S9pk?VR_#9@&HK>=+A>+e_uNE
zzu%hh*D1Z^I!;8r39~h~Es9!;iKsQZ;=ER~Ix5bk?xkd|_8hmPMruxC2~cqXF>tP#
zvpSYr11ix9dzY<Qf1z!*`q+TFXL!K;x^gjR-fW%QHoEk)UU$^ohOLxAbR|KxxNYHN
z8xl;WF(bpdAFZd-qvm7IlwVy)JkNSb50f?KIN&Cl^D!&)ZgNor9!0&r^F~c&B#3Ww
zFoo&RAZ0CS-)s8A4!}gC_2zOwJD2%JP)EAg$0#{x=FFPA+*w}K32+TgP)MU|Yb>tr
zKX0~%4O0)#P3C7++p@G?vi*)?N71u7oIOr)VO4olo}B21Ke#0m`FeW%;fS=1Xuz2>
z!w+N>w#0nc4^3xo!aP{>C>3yG&RFX%M0#Ed_Jxb(?rxIi^G;B6PBe21C64p57n!Oj
zMgTciM|#}yK7FDU)#ifQG0zH=)o0Q*al7UCj@6!BV-cq>m93FP*P1oDqNCY{^Shqs
zmYexRzu)`|YiSulvag1J<PDnMT*5sx>F=6TEQKig@$cVCr}m+nDyhiAqpsVn?!*{d
zAev2dCL*iS;hWw*r{dl`a%#AG$&`m+%+ip?O3}T^xul^zoP}4p;M}7k%WZjGfo_%^
z&Uar-_9xCGmu6XeLZ|qgGZrD2#N>@62IxD{i`z05yU1%9dJmyMlknr}z$aM2t3(k~
zzQJlInoxcR4NHry1lepa9C19C^JX)_VS&2kE+fRcsLn72PxuWAs>B{qvNf6tSc?vR
zZ~mr0Rb0yEtuRXVx``7+*b52vW-GU5HPf}kLOQrL8u7<lmKhO#g(uWV!rJG6f_`qB
zOR|0<3R{dO5zQxO>yF`vHePX`v(KJQ%yTvkl2Mh8Ls4thpEVcQ1q(qf!Q~STk7XU%
zk>S@W&4_5ic*F^lC?xw%2LX^KtF3fI!$y&xNsdu>Uh4RrW)ib-Fl89$-K)=k%`lx_
z?wq-f49Aa*i1=0N_NSG_rnMe7&zDY^6`Hi|F)nI>(b`2UgKc_?Km$5RjCnK!rp;P1
zy=?7DLLY^LZX2D-ZzejM$rGfFy$QNq7n9$#R`NzMBK%qIr<Yh0wqE_h%eK?3Fxv_H
z1UYYHz|Frkn)R_R%1;>M=Q${yo+-m_rCEOoDaxi3S=!L-qOaB<;dgHg*B!g%*@Z+d
z$-<|$yks_cY|0gCLT}wNmDwB2En5SZb)w}kU9$;=3Y7C=0%m~nTImkgi2mY_D?T$K
z@lJ;w`n}6cN&?)JsEo5M4o$3hU-84|IEbZfR&GKY!imm1l|^xly^+R<@?$MyH#=F>
zNwm``5MVml?RP-jNO-nRC(bL^MNiJn(FTy&uqG^JGDPT;8if{2kMY;0QOVYBvi;o2
zD3>r!_&nC}r_HCGmTk07wd?EYggrWGYF#nMyO$<bWVQ^;uO^;$Dqhm)PIT*pwZD?6
zn)}TYR@Ab32Q533Fwn<rN+e})%9QCkwwZgwiMAQaFy)Pn9GkPEG3LahU;FcW5)MU6
zX3qDk%s=yN6Xwwy6G3V-dXq*}Nh~&#5!)+3DMF%e`UARkKCzhW3>48d5#O-lyf*7K
z3k%<?lC$!w_jS(t!K!uMI&B#!3>n{gS_3WNl}KJIEJ#EBKjYku<%hBo(+L8*MU(o)
zY@48vcxyHh8k)(qj9G@&Ybl0cux=xi`z<QZ#;oNf^eOQ>P8PpIw8@?HCRJsdMB<&=
zq69jdOeaj5m6(&{K;p+oZXy%nxAAJ(Eo01%h)!4lD)CK6qZjM*wgzFUgibVan0^N~
ziubKBdlp1k&oGHR4ZA-A>o6$gI^1?Eopdq@3fWG=8fy+0qG^-xw>MEqsz*Nj0j^J{
z9B#;XCNbyR9Z1$0__4NQbSG_HmClq})U-T5aSGi%4BmN#cjR(|LejjQw4V0HJcfmB
zjAq&H`%FiHNA9t>;bO$E@w_bX^PBuJhKtxa&(KV=@tyzu{UP%NKL!)C#KWd)T_KU_
zh_W43zis33Djg$9$BFPoY5cme*jCJntxuJEFPOSJdCJH>yb>oBO8b5-!IQh7bh<=)
zg@KJCH%Txx_CVW2O@hOg2pvvaEvlj&-_Xfi^`e>a&HL>mm$Ih)47iqa|HN|cujeP~
z*-Pe}KkXc`Gs=9pzTID5Y-ckQhqwD*+3+Xp&xZ9wk6WLJ9yiTmM`S<m*P|XM<3Fnm
zZ5EeHrr8|{xS2U;UNGlo4opx#FOL50xyxp=H0-?Ch;EB6l)MjFo%R0CS6F<Wy|;7)
zSFk<Gl`?#0Cp9WQ{g!o^hKk3{vI{%L%$A+bXksw?aP%#EXmU9-Q?5tl-NS0vgkB0R
z@lXp7{IhRHiSgX$?ZiE%e-Fp;CSVdo)nli^@!W7WS7Ku!%y??9-rgQ{woBzNTTi+>
z(6eiIe<^s<{jz%HnsSz`VJFI%&Tl&H{`GpKziioy&y=2To82Y#Bzi8L$({5<TGO2k
z=h@%u+1Zc4?dpnS6+Z9H3}3VQGb{P5b5@Z!?BnzvE<9^anz?*kS*5$2J78m?Y_UuS
z!N1BsV(CP2Qk8q0)!Yo&<^H+X^MmHDiMiaBW;795JGJY!Tt_|lC%@2DGb4X|Jd+r$
z+qmD#v19cU(R`Mx=1smt^Z^}nOb!b<)p?~k?Tn*Y(tOgcE|)$?n0q;@JLZYVzF#Mw
zRs+gMy!R(x_BfBP7G5?doAaM4cRn;1^=Wyh&Na)Lm&?or{#AG;KX6&q%Oxk*D4Tn@
z)n}9*lgl6Bpj6AgOAky$w)_m=7~n$w*;Uux6V@0mhCe_4PV%E>_E2J{g9Ha1`hMGC
z;YNp_%g*~VhYl?VOZBhX)<{Rsy!E|yJ)2!sJ}l<03$~eQd)4D+ZnbPyt~tZc))G6d
zFSU+58?;(`)PZ+MYHka@Znj!!uO8V;E6)Cc|Hf#YD(BAOXCHu*A057P@LaiVed!dM
zu-1Q2^_O&4sWtTa$V=v!+UGchd#?>UV<087=#pd(FPN3pQnryPKfb!1TGZ{2K4E4-
z?+?8E6@R1tb^UmB8sezgdTrsFW2yYL!9T2wSFbwG_oM|is;0V7!S1l;>OZipF8_VK
z^*5?#IFQPG#5v|?&wBoNb&q<gX^tQ1-K^C^vn$!VvA}+8+0~m`t<JSfuJ%`c(?7PH
zg_>+4mvU@@rmkbJUbW1RIP(pCyV-hn!#r1hNIiSZ%&(a*Cap1~;k(d1Zt`^UR~>Jx
zbcZ$2teahHgM`lY(%se?w8}b%KJ9eo-!S!+sQ!GBZvXniz#6C37A);|s4x6!YNuUI
z%{#Rtauc_iB?oK&m-nf}G6M^boH6G+dg}|>n+}YOk9S^)Ug<t^MnBbTw5rwB@;sH)
z>@fg0lm8h-o%)<({)3_gz*$&RW9FNY-!*ro+4w((rb}&azP4tje?@n#n$Lb)CA;ch
z%&+C0lI`Uh8Fk*uj&NMLJ4D-{+M5YF+<p+$!a0kJ|H@o5cXs_T?|b0#YW?d&sH(h3
zHO!^Am#FXhccb)U5jS05w^>}r&GS43$C<yMTEBm+YWO^Z$oO8{tge>)teP2iZk6ZI
z7`4rv9x>T5C(FW|zkhsy@Q0u^>TH_FI-!ofV47LB&P%Fzx!HJ0^^}So-?aQ=!*}IR
zo2LenZq&b)w+b*A8=47V_{7?Um-9&uMUl#3nR=m{XZVcUdeRzdtFFVIl%cLVUGDAr
zzzC02Kj}P0F!j`b*+wsOqB?%WZdJ#tHuNs1a*XlU7mmy`1k<*F!=H-kOLo_sUxK7&
zv*i9?+TI2_j_bPftSUfq(V^|GLK7*qIds(n1V6SUnrO=04%QiWHJWx)rbh%s&oH)U
z1c1&gN12H}?Cdz+%&J~>wb*SmO^}jedhKi)5be-f+oEWB#`*9uKuK%n#94jBi8*s}
zHYBw<@t*Mq1Z%yFHyQ2k7C>2&<;-OEY)b?h-SzR_efQmW@BjYqs~vhzaLG?6T~x4r
z&`a#wryX+<Y+2@_GF$BO5;?xJ!IU1?=E;9HvgP?|we3bh8ya*vbzRY7QxYC4vB*@o
z-o9~4T_4Q?Cr0&Y^-gb>uK7#e)8iGNyLO8cmm`m<%~#j6v_WmX-e0P;xz%6%(wp}0
z*#aG7Ps3wd#J}`BH;fM+@ci1;fxcJVld&@qk0v;H-c$SEmpm6wz0YbNIPhkrcm^Q-
z^1`X^t<z5JBp$~Wy;Lbp9WT=ARWv9ji54IH?%TbkUG1idyjlMSjtOiwaX}Wf>7k2c
zDWaI?&Ka6D(i#|LD*Swf=bNG3G9msaHNnsS<?V*z%bL?4IYrL){m-5$PBn_{E5)r_
z-siOs_V#?1$F{WHl9}35q-1XD03fn=-~hEHTcW8a-Z#jug>R2a&t_8xc0_>E%wUd2
z<vn|U_jX`(U|$a|!Inkd{h$8QNKdkpXM^~lr{@*A`13<YOxwM|+kg74m6F{K>`@a<
z%(0T$RC;^K)cEy_BegXpqTO}<q9Wn8#FO2~5ZiAzj9kZRPk+3eK6`rV;Soh|$~UNE
ztse%#8MXGumoKhNH5mGNuSg%>9q;)Hc(q$Bjl|UYWP2W%#NB#d!`c^Iv;RP`_Q3;I
zyTQb1^i`p0oT5iXj+!mk4|Z4?jvnn-vi9#r41kT@wRc84s!wjNmh78L4qGxtwXdpc
z3n$3ocpsz(Y&Vr*RG0xbs4`mIr`h*&7E@-)I}?pzWjfZWuN^I``t-xm#YOL7HE~-9
zy7+a!Dv=v*mQ^$LgDaMK+86G1e1SsS<1qD7zc~mUKj=<(#QV$4_QA|}rJ)Pwn_vm7
zM42gHZk-F@n1|1HhMEvzJvQoZKchw+Lvo<wK-KpN`V!9xi6lma!(Ves_V&TyI#A=j
z06lVQZlp%7r^=h}V@<_T4rG^h;}ovR+7H(8=)G_yLnehqpZ9#ZvVOoon`;+;VK7V5
zS@Xe8Dk~^!s>f=0JPMd{$}Z}f7dZ=uh~<LiBP@ahaKp_ZW8chmj#I*828yhq&Eu10
zdm&QGZBLQPDi9KlZe6=~>rDK;+ul6Nf*k)Vevf@Lcwu<*%{TA9(ERJ)tiQRq`@+G$
z{^Z;pv*zf7x9iLAy1RJcV_$pna(&i(aq<H<y~p3y`$6@Ec$7C8Z}yJfnm!+7cTRjI
zo=cC#S3dWi^$Xp%aiJq~^TWeebo+L_G`vlJ@f#nwkrkW^-8k=W`+{6ZmoLRvJ~1iH
z;q?0^KRr5jB{+5G?>@HoQ0r)Rr+#ejZ0l(I-p_w-c$jvz746Eea>+b9@s%f+^5%Rc
z<~OZ*EWS)*PTe{2Sl*Z)-?!eYA4{*^+B!CU<;dI}m(1FFYlbg;><^w?Q~vOkGR-Mp
zTDkIx`Yri&^r?-;)Ni@`YxaG`qC5Nq;U|wK1;_0~M*i~}urM2g;regc#<L-DpE&7F
zw?-5x0Si<g4*lhz85~@)%qc@$P;<<FMI7LFV>wt}K_nhB3VVG$0Pr%5DH|2V&$r&O
z{yjfqIc(!ENlT)#SO3CD$;+(&%6}4GU430WN&a4a>vXXLA`$>{9f==b2^u{!9(dgt
z64Oes&+A0uO3p{ao3dc?_|1Opuo>=<0=v*uv#qXo5^UUW7f%K~&z(6wtm_@awKQyz
zXhDyddX-)9qNoz|jt9-|@v5r$L(gRFq7x2vV*3ao>qslsesx^+D#|C5>;xk`Frs_E
z);qi};PPJb&gr*$UpO1oPy5@K{L$oiWxLbzpTF;;mi7sDg5!mtsPWebvVkbTb*j%0
z2!6=KhKFBf`<t!1tBub`wV>&i?g^Nu2`;`-!&GeONyFX%kLs!H_}Izove54w-%3Cg
z6vl5HBUBH(yS&3G;cI4<oCUw|aKxPUw=eoS7&@zMPmeP2U@V1t>Qw^k&R-^k^8rA!
zh2neR`q`Nm^vtfH2l5gW4x1-@9uR$sA5%@@|G^+@**;NFHhkJ2)^-?SAAmpEudNmc
z3IoWnsUGxNN=5QjFzf;?aO-d=Sd4mU8WG7ZMxlTBxbE4H_|dG_I~Vm%lrx?nH~`+4
zI<5NJQ#U8^x0?0C29gP}zHCoqdZ4x_qfhL;vsmdxT>jn0iZePMt`Oh>4`~zGW+C9=
zH#Sd!al3YR#M#~K_>T5J9}zw)vr<|nBi((R;M%rYwpURLAcnLs#7K5$x%gHe@({>t
z5LojO&t-AGe&U*j8Ky5u3}WvG-vn`X!5}QluW1k5lgHbmz9wKJeivkxm^1_+=*Gc~
zgT`N|f_P=29ndTt5@KeV>e)N}ovL-b5+u`pbtf>bL5x880vfg!qi)K5YA%}>A>hP#
zYmZ!5D8@Us2ARJQtXOb^;D^bB#*HtzD7FpJQ_XqsLx9=G?OFpUc32<hA%KFj_u`HX
z76UALa;ue9GA^D0y&Da@5q;Qq0W8uv)4jB0kDl@U3+d2Tfn3I%lJA1>Ac@e_U8~AN
zHj66rhvp1m@Hlzy2xUK`Bm4VrXEYavp)CbK#0`MTY=Nz`fEdlwS&Vc}`HY<L_bmA<
zZ*4K7e8`DgD;eKgCN#wKK)DwAQ@gsiUiEw9TKDEs0D)ui38v=Z7L(fV9cm5p5Os5+
zs{AaRPW@3`x}18mG$u(Oe@EANO?MbPxin`oon^^f<oD7M6&(jS8;O^q)!%Mg!Ay)*
z!LDT7Q7lkqMVSEvq(j)QS{Cyd1@w!@;w|gKNzM3L{@yfVpar7oMv8U<{g^&^f*AZ(
z2s#2{TU;Y!)@6EfAhXJd+YgpUce1mQTK%)%wQ9k17BEa^Mx>I}0?g-yrnku&?%1(!
z#XyUUJ#FX=6x;=|MwSH#)U`2tIw;gTbE(!fC-b?0Y5OOut$LN!PXm|u1y$E80gzqk
z+>KcRmg5`r*fLdPjYP~eE7)g`-eN!Ui<^Q;$1*W>_&p~^^8pOSUSm$9I09*t4KJj>
z{0nJ*IACQVn>_cxY4!p_VOp4N%T>Ri?J>olzJN-k3$4WA2ijk?G8HPr<hE9SWq!ug
zNap~WSfK}Iv~Jz~5L}2RvZT;-y2vH+G^+H|R{%F+=o5s&FS;0>5NDThOPO?X4z1;O
zGH@6v$V>L>Q}3wJxQ1EqcnAa6lb*?fV}WE!<FJ4nE?84YdVupeHAq0_%65j>_#|}L
zb!>4br+9t>opt1Xk7N-R&SaKSfwpG+vBRyT9x-#3q>qZLcl>QJD}o-l9(gUY#eN2e
z9AusWCPXy!2?z><F0d1gM5u}97Bq!tVi*ce2Hp=&tux}-6OiYUakWKHD&Gz((E@O0
z*8$1x9rp@0TZi&DxQC*fGc3TXCqGa?pfs_ulNB6%>bS^-Z-;@;88|^a4TDs0(dp2(
zL>4HtjJB2xe`4^NNaF=Alyx?|gJfxkbj|DtG^;(Q>#|9K&bgY196M@mbpD%rt%l_#
zgeW;6CUW!&9lKyeS98CByYOO!8EY9%>7mS}kUn7Wl60Ci&$7nIcWg&1!$s%`e1JHZ
zF0|9Pq!=rF{#U=v0@E;i?0t4^)b7RP!YrmMtwH&@ZD=E9hCGv@<~*6tmcp?6E+dJ0
z@ZqSX_oqRW)a|jAsA%bSRQH;4^i~t^ZFcHz(I4Bidxh190XrFl{*@p6IZ%CV@IV37
zosIZ7+ACVaO!permo&eoTP$p-X5LFKl`EjbAnLxrl(|x2!bxleL6NP0EPim!W#HMJ
zdWLv52t6*#XQ0c9>9lt8cb1FRa<SmX4bXZz68yZRi$X?H1TUSexyvNtawJ$j;tR{t
z%hkle3hB&PYFLjb2aDp4pxtDhK;%(D(*q*i-LcU>#6to?S!5bhyMRYC_WYYayWX&x
z9qf(mtaj2PPsX50B4mb8SbE4Nr(m%N8^y)B0^3zoWdsa_X$_z^Wf6SsaEcc|D;{)4
zi)zHgv8{@=MJxjiZPQtvtQhSNy0b<V6;zMf>B#a|&)>c51qYU|d#{(px7{6h_@d2|
z*9}kQkHs^EfVFo9t6pGb!2uZ$e1<*4w?v&Y3?{Q0PqRZ%Ll(LpL5#g<P6R63{Z&1c
z8Wl#yX+3A=(%x)(B$@|2=%#o3=S$o4?p-`l-QPOy-CSCW0`D`?+=<qq`*#Fo@Rk)_
zyi4Qhb-#Swv*w3Pz_lRS(nO918%kziSM{do_RqZDj|)}r$;jSgrZV!O?x$ju@&Rm<
zVR00HvK7%PoS_WfMGv2)iOFg4IdfB{Z^Axg7{-nn0lsJXiqu@1Wm$PPE!8^@`GMjx
z;fI5B!8T=vvGZD5>~E<Xb59h^raP;x)~+gr1%c6ci0WLm`l(sa)7GRr)50B6YP^~}
zu6yGnGw~i`uOs{<K%6RGH)~9?0e7}-0V(;*5MTu^d0UseTA3Vh^`9l*tp9VVkt^A{
z%z{6cngo;+kW)S!2Bq?;NZfc^*+4#TCUk2N-i-xK0Z`pwn>KvJx4KLVz(ueA#Lh&v
zCS>zQue;~h2i{xUQoKZ?KnI|SWe@7QneKYaz>f>l^WKA-{BLyH7pC;0mxYE*#xvMD
zLz%~Zqqbo$t<m}!{{d3q<5@-}R^halEI|NZdqME}vTqmLE}{03Ox;i~P3dU$GybW4
z4-efq^?9~j3`VzH!6^y0TpF57yD{|#6GPEu<VX3!ls-ZYx&Lp2sZYJdPuCs@ynUy4
z9isu-$=FYZdH2JA{oS3#_qpu<L|k7x7;gg_=~&r=du{*0O(kHt2RHF7dv5RHmRhI*
zMz$TeB{G@7F*8^%77EzYo;7jEU{=D1D4y$BzyV-QdYj*V{lw+P_+eEYuKzz#RI7uj
z29#&&Y`-@_V%BBDl|olA<1VKhlO5OraoS{%u(|P4bnpAGeQy!K)OfMo@P_3pYs)4~
zR06uTiRYp>ZShSlN{MI)F@Hu&z?W<b_XBvQ4+4nIksVmsc*BuzZafQa;7)+!E|#6(
z`je_+KKoUopQtED;T+Agw@vJ_&8}zKpI4<dAhxeYsr>qdNC91S`iu%irkkRt(l<_y
zx2e2hd!a&<Hx6kW&+)oXSqKuK4O{e4JZzU+du|CO&0B|sK}y@W4s2JIH_*0Lu`zk$
zK$<C%u@<9h_LaaX030e-BiTH|Vz+D(eY(uZ2$(0onzjrX7)rf4w03UI0=jK~u(4&T
zv)>z*?_F@M>*SckJLpNPwg6nZcqA>vBnxZFV|Wp4j&ET+0d&ZJ+Uy8q`jz={To8aG
z&CQjSMWvPC!QX{Dy<Z?^F9ZH61fp{Tq}w$)fd>Uq`xJXZfk8=&0l`kIfGcXiF!kSh
zwF8Z!X?Waknek?jM4`~9gV)gpB!;3{Y%nbOJy|g`0{|^s3zV2L2#lqfslmP^G{>JG
zGL~>#Ee)i~u#7Tr(`fn<+d;A!2T-*4sIE8f=HY_`ol)O=@bhTugB|B+0EU&VH;m`J
zsIPz5ErH9g23uJ-bE%<6{uWxd#SRK~u4n8CCs8l*5$W+Of6)?0w82SK-7P<dm8X7E
z`J!P!s_<4n3p8jx`+EwBvCD>I<mm=xO9W8JMT-9ZZh!n}@E{f2CZ_&nx+9}{S!QUx
zc|zSgw|U#vJ%eUjk!)Up!K^KgTOiI0bsDgoq2R2sj3Lk~5R`@PZyzi$G55I_ja^P@
z5n?K*cKB%EHO)h`?5wieC+mVh^VR50_w{$3`pUzqe6IBNvyp<nP(Flz0!oO;Pu6Ad
zY|*iOfc7FT=BQOQqw4Elbe}NR%2c7cwZU@MT#SbCl0of8ac}&6F3~5xMsgenl8mTb
ztcv8epCYM9e7TQAiLEAZ?@lmjhh5*)Of;ZJ;^qZ48ci+r{in|bX}umSMW;sTm%_L!
zziHP_tI)oou7WM!k>tid$W+x&)T|Nr@WtP9fb23;07L=cL>3-+-gZJFR@{B!gOLLl
zZ-msbnafv-g*py{e-!POlxXg|Yb9A^Wo;j;yIKvO&$K{xk;;D%YxnGYEh<)rgOjon
z6t|BmTPp^F_>`RudPJb+4a491hhLeJRNS|A3kG*2zH|JsILFSmKNf?XJ$SEvId=B#
zmk_ud@|t{0wt=1P73?g#6A&#2@;0!uEBD=!BZ2~*fe7X}o*-v`$|`kX;<0rA4!kYD
z$b>W`M+0Ad5kUh%0i`M1wBU+Mpn~OBwB^SF0=^0i1e_EwkTz|AfzqM;Du97k9()N5
z6iD&*9&PCTpnOU$^5ZXo-Q`#yf8VY*qt47{yfwiIt~zb_Z26>;pvSVHd+;N5#A~fN
z*E<o;WvX!hLx3P`690H5sH(g;R-9^zc^s`)PkcI*aEeb}^A%nFG@s9M>PxSUwru>J
zf6x0n{Y~4ly?AYZZtQ=cS3+!g3tLXON(S<<!BlOXH7n@8530e3reO>r95D{=o=t?s
ze};Tha9uRA=+EOTCD`#+G!3_E_<~;aS?&8i4q^2!t<r(;5c>*`q|fnSW^I;rkl}P4
zua?q9pE*+<?p!vGYR$I%Z91rGI0c>i_r7>#U@zo4!njz)KF@owOu}R|1gtaWGt3fJ
zYJnM;cCh2RW-tLD^0EG*gnTWqfpX;3E@->D5Jb3C0Bo&+1V)B$gtE~0tJ;skxs=M8
z70xq}X*r6nE2waeo-uw&4PcVTIs>1~tZk##<lRO0fsBi{46v4+8GHxU!mVx?!5*P*
znG7zW1Qx+RRp?+Bq>tAGLoJgYN-a1`Ixtmc6>+rXtEA;*5)c<0RXP#utP)0O#0(KL
z!ehpz!|CoBC+kPlxNGZOSI+&@+F+yRQh@?I#y}ay1Z%_t%d$LrY|W<0CFAUopgLO)
z3a1JE#6W=cf*veJTs};JQx}4kpZbnqfbiyI517C|tUwmE-%1C9QDb_(oB4&#3D8!2
zWQ$^IO|+01e>WYjghNfe_P?`bv23LWETKikahmgmH;gqQ^&U)z?3%(wv1ic<dSmq_
zo1LYI(^F$BA~Ygn+$<tBCCxKxz<MiVn6gd-JQ0&-SXq`qZf$WHcvQ-Qn#c^R)~+0S
zI|Xef+v5g3PT=karI2B9dr{nU=TXdHj9p34(&6B+>7rLbpcXVCK*t6?HU=oBr6%D@
z#_UNnIy2%YwqK5Q9fBY5NcuQFb?WK+H4mOM&+x7e!#a%o!)XvIfaR2;{R;cDFlQpr
zGhA9=vGn$Dz3yUM$A71cvAMOA#zDuU`nV3V$5=u7Zmj@p&93+}aX0=D!quu}X9c#H
zu9}`>g5_$~f_KnEf+I`}%*e1yi5!qm0CU_g+sXZbzdLoRUodm67Cm2vQmWOPnSDl&
zosPN>$vG{q0eBOF(}6YnW<CmA4szlFbYr+Z2eZV<;!rV@LXrW7`9i2qWY0JQ6PQ8=
z`daP0m?Een>(&AbVuB=nhT$i7>#NX2c8G3bnDj-kNHJfSoMhk(M-02@Iq0<|)8pRV
zZ=8t<15j+FfKmsLY{e4M<YB_Fz?E8Ynh^?ak%11Gomys*HLS<wf$6azH?WIpZa)eg
zziOgFXK-E+U4J;mIcISr*!Ht!W|iC$+X--j;Q{?CTzF1QX>Cw`aCw>_I96yY-v`X-
zI2K5LCmIm&085P65db|_%xo#{wMug-RyiAS%uduVacXu_?>J&yAszEQ^D?*ZdbQNB
z3akLN3<ngfRV<Ofw8$3N=b?ynKwUfQlY_IZaG=82$VxDx?9j1h)Qp)?nNl+t3KNWG
z)>u=gj=)xkPLQ^pj82jQ4Kv@xCOH<Rlh#}RjdkB3IY^*F32CXa;M!3Xi7@kNi7gN)
zm09S>efggMN3G90tW`CA0?Y)(2cJnI5N44eO=GNSx(~vlr1F#~nS-Dd-u3I($fVEq
z#S{^mkbuN7GV^!lT0*-L8jPJzq@%WAT$&UEf<h*N)l;-<$O-Lmg#j)!L9lVYeI4dk
zLzCcwAudKqgU=K&s;S3wkG_9nXzvA>U<{EvRzsL_45ralOM%>XB@W^XC-8N(Yy(jm
zyMoMGIDDfP^7QE*C|6qV)YZA*dbtBD71P;DZ0sQ&BR2v5lhN*B<efNAO*jo}xD)dP
zRn|B}GVIENjpN6;$#}lDg4+aw$Rv(sqyaP?@v&&oXJcWbTbz*17-<e04lrgJHk8l=
z9yD6R=Qe0xw!Y-A{_@wb!VTAoxdCvs+$^+3V=Y7l3YYjK{7$oZ8-~YbC~+1jZOz>U
z6a-=^sSBRX6Aq{`tp;c&+RFI1h!MCG&0`?Bp1~^PaBll^YoEY%`Dk;iTtGZJgGhu=
zjp7?1q$>UL$&=6$D`PU%*aY0MB9L{NcKo4zCDSJ1@`>oMyl83*PZ)_Rz1sSIVK8GV
zd4mk9D~K97Aub-q@cLz4@JK~i;fPJ53sIurKB|uX8Y-G>5IJPe5>|rnP;$Dg6QeMJ
zah6CoIMx|vC|9Mq3%cj1nx@;j%cLyc{>Rs_s&Y?(J^8`RjsfvS4s-=rUWb$5XCW6#
z1ZmbGt>>Fi%_(B+s6}Q90oKSKV2IHD6Q~*~8i%73>?vc31;xIg6lITzd3)2|8$VFY
zdiE1F9e4Ood)g>`3Kn?Df0C|j#Xxfm-?^X*YBMHV;bFvBw|cTdu<b{*gnLq6(UmIu
z`K7G^lzEXAGBOXX_?6wk9VQsAA6|r8UOO9{sJ=Dr?b6+Iy89<-Y95l57=9H9&&g_5
z32G+;JPHuOZq#}l-WrRO)56IrahuszP-#W+^Z)Vxo@r9tyzfS@c(cG`0aysn%IV=B
z><n-({4V&}ipE1?oBk-)75K|1gYu(6{UpnE61CV8kHOdBVx;`}=pwn#D0N0oRJ(I*
zATVM_rL$^0*gld*=KhJJcy&Ac?up=S27GM{9FcYfUDCOk+I>1=O)%w^Kv!5WSjv*w
zl&YIK1MeTRnL7XIpRPhA8tg#?Y}76g{cJ#CL@QU}vHZ6#kHnqJ=}&Mm!OsNaN?23*
z$GXJK;wYOMQns}LpRQIm&diS-5mrWyq74Thmvdfru`taK0TJm#CKMi_{2-X@oF!k(
zZ6o`-wIBc4nPR+o-uvUA;THzMK0Kf>(1vg}sxM5Jh`n#^PIdMX&8n7T5$cDqtd0gD
z;V9@D{5jV@wiumKH{8t;t68v|O^n!TewUv;-HGf7FZKpcZK?8v6~Szx8=@moD?6)x
z$BQEMRCg+UTm9qy!Ib*Pm`YRNEB_?LF>FJB%s9#8{=3{8W=niCvFm|sU-`=cZ>!*Q
zxM(+x6J|qfY7Xx236>*hkD%<~qG#6aowhE5X<{6o>D(qDPa6PaTM)v`3#TbNN^Q+P
z<Mz|!AJjAr8xN>50b>i!Vsb;kjj0sAQV@I=RO+@)gyDL+BcM|z(4l2af5aD*tG~+v
z%z&0C>&4T*_D1&SwAi1u6N4;;muS}z6BB3$loMc}jj6LRaTL|^zz1*x3m<}T9_)@k
zCLZ#_C7?37E!zX=_AN{BZbxCEon{9zz;_5pr>#?`D4)IFE#XVe4`KdzI%VHGVyr5@
zi~w0&!Z7V=&|k!xN)c@VDjf9XX30aqa^#qZzuTR3Aeru%KC92O9R#vSC(2VDdLCG1
zpTN6hb0s<kyDpqQJz83%DOURqMfk2S(hyy~?Q}bJ+5yX8SuTOGTF~6rU>-x8#m+a1
z)r5wqn*D>r4sY754=iFRkBpsb9p(3NS)(xVJ2l!4SF5~+FGgj@X(p-M-$9anHPN#B
zRIzYE*=fJtuZ)5z#;+&((96D6o<5zG9f*7`C`*~WI=rx=dH$ATwQP;TAYmZpT^y`3
zQ2-KmYcKvgDmiG9g~nI{v04EdgeqYk18#}oWos31CGnU5#yTviGRk>lq=U&CHa21$
zqpAhJtV0<r2{!f#X*UB$FhzlBjuC7NRF=b@KzhnX;Qb-2ajr6%r9b^g7I~6EjJ9=A
z)Yzxp=obqeaF*B<Sx99~C_4rZSX#zcfL~Yycy~zS{VJTC7E)*X$E>dc^f5e;!cJZP
zFi&9as{}=1fuyB^LlyWrF6%VQ7SlW8()!LndE=huV4*okcmrxfb`$t_JIj&4;8q#8
z2P6qm0q7tFzDO_$tf?YM+5jc*po*&dE87R!SCoqOcfg0J`z|{--A9@ZjL+J^a4>!}
zpk^FX#$De&SnDi#%RPpOot$A=Sa<#skCm@Aw+?3QL6Gen&T=c*tCMwEzg9BwSa?TR
zY+;LdqQhO(=$7j4_G=Nytl39NVJHC%*P@{{vq<n5^Q|8)MgBKs3PLwYu+la<jHGMq
z`^CzBvJP9=O;&nPB-{!$bC*+Pt4Ed`%AgyFiK-V?*Bbp6E1n&d(6s~3s1>XMJDF=4
zkTt`Sy!{lbKR6UON8S>h;+{YT)mfsHcd}k)Qp}ir7-5!h!b>?_kg&<Xg^$M9V)ggQ
zrRD2o3Ln<~`4=IjO}_d1myy!GwL6D>9)JV(3fQOp3fO0Zy0wlS<rvZiku1lKGKgfa
zi5>l&7rE`zIRQ-gV*)^BcmBf9YzZ_pXk@PihP}i_+d$NQ{J9M_T277I0K){vdab4a
zU*(9}%c*E52kv{I$X;H;JQEM<>WfH)w-}(8y%bLT>#ghA8cY6%cQ%7vU;k4aL9wQU
z@da{jZibOG`G3S<&^q7wiA~HDxmLDu!Q9z>jrSWL<-Y>v%gg`%$@{N=c3|&zL*&oH
zxcvq`)gZAs3wD=n$|8e1hTWp(&L=pr1PbWz*$O~tH2_KS$Fy<kp<TsCB2`@So7xOe
zuZh3X#lzKM7EPYVsj2vpwr;}BhRNht3g`7qir2y>1LPw|qM`HRziPN`E#r6Y$0yaQ
z+O4}4?=8RohP^S5(F`DTOxhVt9o#}ypaBwB!3+rjS%`NKA^s08trhy(Y2v-e0<;(v
z-0lEkBP=I!t_JWwFds8f!jJ?d=44HS`e5^YQ#hO&fM~oevfn(XL1E<<qt!3H4^|X2
zgk6AU>V%^L=Pg4CbB!#&+_a^PZMrED-<UhB<7$wDN=!c@8R`&vidY$T799e&V^j}^
z&W$i&)Qu*ZbbIVpV@4cnXH{J3No@nOR7y@jaCR4%cc*@yC@>j07i2s2Z$IV6JByjw
zpY6|<HTxS70PNIQ332&>HcnOv6Pef<H~{D(h8yo56o+~t05cni1A(bv`=!)?x>$Z9
zco0ZeMB}oc1p=m-_HecwV_GA-G#<A|c^Nbar+n7XmB{c=u4s`nTIxsd_{#*wei#v5
z^lWO4ZGcIPlWvjaW<)APaY=+5-o;hquvwhsVcI&|GCOsJrGVI#VIlA%u!6uvNJ7-Y
zGX_A}3Hg9@)`R?TBS=JXLbJpwq3EE@rPb1Zx3jo!ww{I4&7QySa0&;e#Usbyxc6ij
zi0KV(cy+fcxKLsqXZTfozFIqvvmU{i#GUthb$z_rLJO-ismipU9EuWW9u}GqDWY`1
zx~W?Gj#0{_pijgAU9}V?D_WC*aC^A#%CDd^r~~(yXNLF?(gZic(Y0FXkAC%2{b=92
z4x6|e5p5qA)d0<6Pa7hHod7LWq^^b!uSnzzItkd25tx(#{n!;sGgA04lS>gmRX`Cs
zn5!yP*7+wAC<2MW8X)BxrVLL=OjheW6cK)vDHkNL;1>nag!ak@#SNG%pwA4h!*;s?
zG4KzfH_0p+$CyCxL#Q0Y04`9$oMnPzIA{;UgZ}r@#fa0<DePEcj8l#x8@xpeaR9@x
z4T<nIFU6Z=G15eP;M$<6O@h@3bU@Z^iF0tf4yE_ry9ui{3Eb=-HaSwm+_3vxVP8z<
zQ5s{$T;`9sLyQ<`Uef`?fvv!W6hac?r@NlpWe-X$O~}NAYayyZm+TBoM8T7)gxt^X
z4S>T$wgp~|4|V%(*9PyYC%`;J%o5wK1Omd~{Q)x2XKtP)SOo=m#OFlQi5PH@T#Ji@
zxITDf($kP>1OlMx*;tMqk$~b$Oba!^d@2XM_q!G-4c<Rw55WJO(jSW-T8>NbHNmH)
zji4pTK$t26u$4w!B4qAxzHF$Mm5swy0Hler38f|LVIV%S@-q>*7VSe`Rjvv08T9r9
z7hc>Hc4t#rBH%$$bZJq<7&>eKhGA07Gp@`yiM<SxI^K$n>F7rSH5kKsLjnxVDsupU
z5&#Ha=&0^uO)OYu?6^yUfYuqHk}Bil>aETP?y-;y7-EkBw20;T*~6<qY8)U0TQmvn
zutU5eEOio*n<2uH#v^!!Vp(&0kr{SM#?Y*vA_E14MqJGZL0`o@HsAI)KS!~3z5sHN
z#86xtRqcoostQMmi{$`J#tr9E&IifBEf0E5Mlz&_n)o2~T@^X>Ts8nBR7qelpgw?E
zb~qsSWKteZ(OmQ$2RYNX|JIujDR7i10-~_7=wM|T^Cly(hlpya-T<7|t^<XY^$4tw
zMh%37U6ulN6XmG|I%2J$c_M{e3sEx-j*q<uxEw%55pAw?#)Qs`|NeCxD?>TvQu+x!
z3cHO1Xjoya;7s6v*3)dHFMdYogtn+Ao+A^LhzRjGGU~J$#-3c&;O663@HrR&AUu<b
zG0NDacmzFr+eh9MAX`)*lta-RhK{p%mIkfhdNYV<8Kq<rXg`}t!L;O_iSfzFU`+yH
z-X-TyJL74m#by+d4KmD8jH!TxfrUX5wMCZz|LlujeM3q!p={4F!~oKwMlx9#LnE!=
zw)tCv-7aP)iP57jI}X&EfUwL$))90{G<-$FamJCiG8R;sE*5YV>kIet!#RYM_yT=}
z@$<JAt;y+3*gy2m0&WeM7U+@{8b%f!#Y{oqvswHQ8>moq4Bt43Qk&^2Eeg;qLI0TM
z3!2el;>wf|{U|9W5xOA5#?)al>A_ppe*L@Q$<c3mf%aG<S$<ZkJB3Y!0oaDXf);#z
zGue5L#fIeyM<wf-I`_V80G8MW0|;~Xcd&76sQ0KgshTzY$oF?QPZQjV2<BQi6MY`F
zU|N?<3N@>DE*Lwn`QJ)fiyY*u9@7m3PEt6R)A&1NW{ioVkr)h(?HFZ&OVRlqv}fxJ
zzj8a)bwx8EX!m?nzySb^JkMKM$NU{Z_fmSCg#tR<4uBHKWid-;W`Yu7$TFxMv}d*-
z25$>`4@JJ&ty?3Dz;+a->S{Hc_gl}VWM^8B2P}>3Mlv7CiAo18V6Zx7AKqLGrwAS`
zO;9bbD!k%HiSZ#WKaM`&q_X<?Z261GSn?kYE~lgBM_)MG$3NY{ei|s!%h4`!_v;^&
z@ofS2UP7q4c6GOWbFd?LR}Okz{Xuvou7f~XqacLt`hh|f+d#Tr@$RK7f{V2b=|o??
z1~`+ea(B5_e&<ZuXC8~!UYHEy%{hf=WbAwpf;T*<FME#$w{;Ycq=^P^n40%8HF5W6
z+#P7u6b%$~O5g$Z(X;eFta@trnGTTawvv#+rXkGm_@k$~_Ks6PIBk7a%kiy4W|Rle
zoD2Gu@-*bdW9Bw+jBS3se4;)N&@=M*L2$KpQ*f^uKSt#G(;ZZB9;)szsDx@OfVB@3
z0lTH~Ui<v137A#oRFIl^$p4jN&t4k<SO_Xba8F?x@4Pk~Auy!A2dz$V0&5dZVk;VT
zgpL3EBRpOVnvgJ!G<%Qf2~Qdip$aa~E+6cG*t`#!gl&PfHvL^xLINFWkTcd14#^Ur
zG4C`;NMG%!%4sCzF5-t%AqsOzcezdlfe4V%Q7xWaBp}j!1%&IJ$6yOnxOz5Vxv=!n
zY6f8})2r+&rOHD@@_)jvAk^s5hJn7S3ixvj8|To1Bc`t|(ov;bNLIH4AVDx4mNiwn
zY+{~}qO<-kfC~6YQ=KHIy;*I&6wT95ctadcd*=~BU(q;V8Q>}#G>SXl)}h#w<9K)x
zK+r?nbz<mr<Bk_DKbS<P)eh(+PlG7v-fb|qXrxGgg1<{2<^d0)9ay`I7&mJo;+g`8
zidYdHTj#E`!<;tx<%C&@P?r=k6+&E_5+R!D)<pciNECzw`2vwp(_4mt<OauD;Bp(S
z{4l%hm6Z%7ekr6PX-4&8@l@lf4-Q!6vsFk&So)(?!P9sg7lH;oLvQYpx*w1!p(Qa|
zpeEAebv75Hcv~k6X{O+7B3<4bYt>yglfg*_-W28H!7O|%2o|bh(J%6}C&<fBcaR>@
zm@KjsOmhAG9Yx8a=uyaSc8iTWezf&ZIc7&yFgq9FBdA!qElfp(B5koHCd6Z;$Dv~A
zgl3lY$9alM-YVd6rZ2K&A5^%Giz9T&#!ldv;oYE&Llh@1dI?ESBq^Lod}!7in<u(6
zn?VB+sU`=o*tq2*-?-Mgi{cVm)2IG;k^~DX3M4w=BugXkAWF}oJV;7_JGlccEZtRw
z)8dl~Wsi#$gn`F%<gyT7I7E#Auec#QY(jdBSn8mhF?Dx}7tecEL-F<$t-&!C<oZk?
zD)z`94T2DnGm^=BByBg%KqgZKtP44F!y{%NKLPt>aRl`w(}0%%WW0TpDKUKEd}nEh
zZ--s(!(!KNE{<~}KqL&1tJ)VBb=xXk%11mI$XSpQ!NC8@?8JGRwOeqvo=v5Qeer%*
z;)LV`14U(O$;mV`F55mj3C6{(v~vWgD)L-hH|U6>UNl%y`Uz@<FBX7lIrvq=4o~n2
zB$LC2D5-Ns4O%D_*@IcU7myHSFD%EJjq4dK)bVdGNY2;*5gLtYJ$AEuUy#kEEgK9N
zZ>wp<dsvtweq*yPoC7=r{9^)UYo=8*BbX}aZl4nauON}(e27n?$ExIR?PO#?IAX3W
z1l#Z92dLTwI<DBGOW-y3@v<e~k{>i<=!!%-E5LhPmIXvsiw_mQ_N5$wTQ3V0;OnC>
z%Kkp!*-K2aybAL*m}K=&OKs_uBX``fURw$WOlmM+4xWLPt<%xI@-r{;Q*^Xfl$EZN
z+FqMTmN)6uL^9}TFOk|_(G;M!vXrK-6UnGVJvI84vCa1liVyZ$FSJs^9(ge<t!VwN
zxVDx!nGCvoBY(9VgXft^yuz#ahxspgyZ(W^!$DvF_3EGNw~$M{_G|UI?aNsMHy-a0
zzsA5}VQPl>;5o@B?vOl6;qa4WR{|IK3d~EKQrIEH8?Z+R%1A}1Dy*KGSX4nANI%b{
z3#0@w0C?bftfS6p3vk0M;za|i;dWN4U8q2Hw@Q&mnT%uI^&UCxPEO^-TH+squQ1|5
zDi*gFtrQ@Kc#}*hffAW_OstJ-ZP*<Xl_lYcYeb8zWDyX@BKoA9Q9}!mumQ)nOV*aC
zLl{@Ua};aWs)AMxWCnOmsT7Q&zWUh15_xbuMJaWXfi5uu!Jkk7kfe~fd4c)oQ6(Ub
zL&Ylwk64jNe_2d#!R7cer5S`uhQzi+D%dB<XImzWfJtWfrHFnxgNbFE!dIWc8iYC}
zwil}<uk{c=fBPCgVk^G-sk{jX`LCD_#_R9+%d01B;c3k@j(ytRYX7|P#)_|h+MKE%
z^`}oh@#KoCUko6Z{fFjg^SJt6qjvs*VfUuywrqJ^9Y4P90SZt~Om#n`>id4~fiI}R
zTX9R&j^?{NPx~k8Ui<t5e)h$<<W`T=<BKbsV7s1}+;Iyu*1aE#&oyrtEq;8~kA7)Q
z?R&gwPSgwMKjWL5_I9=vv%Tsb?|fFa^)EJ0-Lm-B;QHy4|FUy(^w!eiX#MH*L!CV<
zquU3&E4{A0{Rx&>tuC%y(Fa$*{`*!|xb&W9(!nz(I+wnyv#Izm=NhXSB>jcD++(`!
z?hD+vc~6`o*70^^H#M#6qWWC6Z&UF`X+1&M_M5X}_e7l}Y|DPdfjoYCw*6BFPO~?`
z#sznB!R^=VH)H4he|-Ld8lsasTQ?yNt|$ivkNQuv3CxEs)-R-kFMjstt`5!r=ijUU
zWJ*Am&^Szg)Ldl{x_D2n3eHYK8s88jLTlqs%smkz(*>Z@WCjaDd}JK_5OyWA0WU1}
zpR<*Ls?mawz`Pxx*l@{LwZTBm0JRb>a<Wsw4*1~<|LU-yI54GZhcP_-FX)>NVcZe!
z00#=02<*V(t^%b5z53yl=`0wlEjA%B23{pW6Ooxkkk=bv@sJ5b=x>41p#2{4r3Z%$
ztXKfEg!uqU$;@5-&I-pEkOV+ixF+<fMU@cceL$JeK8XS|3zA*r$fDMP<v>(O1vx>n
zmZSi<D}g_tP1l}>Ggt-E7O)q~AomhjLlRI3LJd^<K$JXu%ETlYkb)0Sfi_|;OR0%y
zQS;cpaLdL97R#h$3Ruxr&^l*Rw%o6?wHG~X*;N23-jWP~5Er{$z#qRCNmOj$kGMz(
zTg8mYEHe1(KnszsS&VQPfsdHL@X3f;0ZxIkun;`>9miDSccku5ulhemAYu}+MwnDw
zA3-7*WgKtJq=i|@zsJ(#NAVFaM49k87l96vzZH-~KtjAGffM8)hB+F1%b&gp&7o)+
z`CLpvM=<aZAyF>CAv;tKS^(aZnU=sqz5!;SQ~W?J$N*Y`RoRB-ab<vfAi)7d2+|um
zpyUiR=nr?|6sMY?jEwO|{}$lM6?;ncHUOW&R7>;3-qN(p&~zMI0V2sC$SGVq^a6)7
zNV9NH0dCfFNSJe^gPKcs@_y5+0V`Pjw||PEb~305tdtq6M2Jf*(6X3!2i03o*rccv
zxFW97ve1vhhy?~^!7UZMSwJMjN@=&0<%yh;EXba$tR&%q1msf@#{8dIAIAq3v<s`B
zM+>@VR63VJkQ6Z23ZW{~5ymSS$oER6G0rfMCS%GpW1g`5f@N|CnF%30DOm~<uZc@3
zqM`L1OGCI=&Hn8_xRzs>Uz|;|5(i9x=F(^@lLHlnuKdpXnY9E-E_6V=QB^Sw3CJmy
z1D%stqZS-a!O2p^Tr|S8qvwf3BNAe?$W~k@w38RE{6WZtcWTrKY?g*eeLQI!(r;lp
zKn*?!9K%Oe4a70BD`<#iIK>apL6AytNqQ>KXBI+05?vHfn=Fs&Itpya&WNatEmB2H
zqENxbPrg1}(efoeEDai=S>1Z4!dO#94|+&pxg0$Qs7~P~ih)zzOLJ96FGW>oJ1o==
zy2m7h!z;s>kSWTCE+u0EV2J;~pUvjCKP281cjH@bfyn$0=}3#dgf_(GCO#1dCO8a)
z4WcNr4+Njo$bZoeascEJ9oUk72e(3w6{SHokjI(bc>bcppt^~@x>n*ghB|b}v&4%`
zBBab+aBTR31|dx5*MPWE3M!QdKmf$`muSA}M+gd=RY{bA+H7GZ<un;Q#L8)jUAOMs
z^SYEzQB2M?+G1?4PMMlZjxqlXg|W)xn$g49O9)F1u?&vP$q)z+xzfN)5^wS82#y=6
zNF*hjRttd3D_=(v<l`6r)2BFJ6bu#RMA|8>30acJ%PQsxAagh%qGtV&>5|WKD0z8;
z2j${&cza6B9jcnJ@X3iO@{}oo){<VKmz=zM!?(iikAv{}=gIWyG4}c8p)Ks;$`%-;
z7Y2HljCzO!lwmO-$BUYp%6v42e+sZiG!wBvkU+Ye&ZgweSYUW`pjMNDLsoJgV}VTt
z+yrtfEaz%<n=X7OUC|JC&yw8ReID49aM@SYG0Ghj+wGnQ&jUl`Laj(Fd6nV=CID$h
z6WO7GviI*lNvOsutRhgymL#FFY70Unxn>_kb@Ho01=w@!Jg_lz$#LECQSy`&p~{9y
zHjil#z1@e?jLcbfMl(73B#J3lW|JY;A9GdflHk8E{~}q37Nc$~YrWsy#o!)i(IQmD
zOD3h=T4Eeo6k*IS(x7VD43zB(=~J>0NtC@{j`R&6g8b{+f;p}OhZ&5yp;v*9es=LS
z2zwjYrTWRiKAf|khC_2yGXF6#YmA;?jRu{_Z}}6LQ>cG0{S$6&5}BLhcfOMXJ$Y!g
z1q_)9kkwViqZ&j=ost4m^=n{6TD`m5KF_WM01d)FYJoOHg6jxqiHB8MC)Ek;SiYy%
zJby}HO&)Lzd;xK4K-hgfyTs2eIV9>R5X=1H|2VIS<CO2zAKnF61m+~?$WB=k=Qsxn
zm`A}YxM<lCkn^ni95_em%MXBxmRt7D>q@u?{l@!WP=B4+pgjOX0{VdGP_cO$qyu0K
z`kf$kz$O{{>w4DwE@B(EKLqjI4wr^n03!koavBF;#TLih9MkJpgiHo=GF7s>9v9@}
zKrihQDwYC50<wfH)!%ijCEOv7;BUd0U?oBR?6dP0Jif*)FZ}Q~`W~3Dz(6_DLqc3Y
zu)HR)nxkaY@&QxfTeJZzq4}jT!4ObX0EQ@ghH+w!!U}pOn4NW`#r>&VWEU<l$3#gB
z9l<vz2Erv=p|YS*h(lO(m;+kp2*$TW{jmUotWjWG^6!?>7ruR?z>-pltObXXPYsPQ
zK+8GBaX+`D5RoEVyb&^8vbG4$hbH47ltHYJoeV$yU)FGvxuw9Nm>Vu*K|hoGUq&ee
zGsX)?-5%#Q0#t#{A~KpxqatfvWTi{R!FxY+P5!B3P=Ra(5@UP4g8*=Bl_vUGW8j7;
zeZ^@&-MCL*9mN<6#{)8HUy&OW0-GRjz_hTkas(NPiH8d6DuAzGh*X86AR;s_qk1%u
z-<VdG68<mo#je~hDA~!kPC=;_bRoPfE#j6#1$Tn>ptA^-LQ2*&x{90eJV7-53zrBL
zq|>Mz96?6lGWjHcz=<K;qAa9Pn_U~FE3`yD#(x3vK9X7!BLM2mNJL7nlojG?fWFxb
z*QNgekss$lczg7)tyQi_cflf|4Sm)+wm{T~=9~mPa+GM%vmNf+0}ba4&Smo{p+%yS
z{K#1Dpj`?^%={W4;9<EBQ70bvPWVnofYoz_!B<&g2WwU%8e{DG@BEL5TXuu6tlHvu
ziBz7ziI)v#-GS&QtE|Xf0U(o1G&u%M@X4~YOrUBpO4bgUF~lBd5u`YlepqqR=A$_Y
zmnE#`3h%eX;1^}^IZt+fW2A*ihzpER2Jbvz_gF4W2)eH}@J1lIYw?`SKAobzGUx!=
z0Catz#-@2(ngr69VH?V7r3dN^4!(X7a9C@8yoS%gDh3$H$CSJR1}e#l+nV*4|H(4}
zY?2uWKog+_Ed#ekc3%#T78|R-|9dkXT7QxI;x^)6gw8@;Wo83b<V}q%2bu_e84j>x
zW&n<8Zy&=KW2<xGGc<&?LyR^~c2g*Q5C-qF^JM{a6c`c$%@Y2x1d4D10VavaEYMu+
z`%0!!8m^IyzVJ^z_n*TXuU4*Jd9Vy(__Dp@{@x(p&!XAAtmG8tVZQ&|2IKE%l$^eb
zt9R2zORmq6LO|2?i^!&WSJrE3Ukx|@q$RH?etoUI=hp7{Scop=FRF~z9kPwTU-1jA
zf7y$_#P5}GCVzz(j*ZtNQ*XTb76+DB&EX$P`%|xkFJAM-bZ44~56A1p-?+BpQ?o(*
zKB+u5Ub2WZvRvIGU;})2;vqOwB$X6dW=alYqW6KSQGP3G4Fwcr)HR_eTL&wGY(jZr
zF(R)7ItET^6|Y7ar$S&^>%=<3NCo{Uz^B2@TJ)<`XvSt_7AsmBe*Q22uLQzt%40WX
z&Pf3Xo@~~pp+vn6Wm#1s1xyfNAsiWqB^f{2bB(kB@Z(8Tm3k>b_`7CYuvu&ra)b*=
zsm5YND1q4>gPMp9#&?AY1jgYccBSHzdx=^rJpTC>=hhns1zO=MnKl-aQr48v#(gKx
z9nPjqM@smxKgTuvvuX(a-qa5pLN7dQBtk$(vv=TJ`*)ZqGHMY-fzSsxT*5~nASrMO
z;2c?@QP=^(696PUN`JNdFF4Aq09Ph;d5#>;wUL0BK8Z7F<>7d45IeYqo~8(lkg#Qp
ziKKsexFcKmA*^8%d!%uQX$_NFhN2?8Dw|Lu>qQaqmP8X+Fy9c{NdP-Bxcb-}1MO)$
z?KwP$q$As55c=wH&Y&sS8F<x(z?x0Kw7~&4gxeXy@rezg=1IPTF%gkrq#`13v{SCk
zG8@U-hWydG$PPy^l>yyhaMVTLu3BgQ`sWx=m96ZoW@8;%fc&YzBZL8NaETqb12hA6
zD|Ashg2&oPx(bnG%oS#$33j_#l^CWM)jLCiinGI`HntKrDx3MCmPu-md$JgTGg0}=
zR#7OT!vM0>z@HP;*$)@}IqUm>lPDOLAaI%}CIeDqBez-MJwh-DDz%PLD02f+D<I6A
zVH+PH?2~}zhI`u;l6MjAekDN!hzU@Nc?_w7Fhf@=v__#e)esD7fY=ZaKJ+@#I4d8+
z2OorJ0CdK$fOe!Sm0<Nt_ve@aj*meVLR+{X0hcsPGxBUjtU_j(%p&<Lr}l`!Ko8L}
zVprbcRVgZb(Mb!{%N-0m9|(qn*$MC=(I*h!>Meg5E=3syt0an9v}K0isDS=B3vi7D
zAg3CyAMp?a0}5Ct(j>^ncNihoOMoz9HxZbHj)oFV*}FSVvWq(t%yAh(Ii!}@@Qus_
z+CX()Go<WeO%N;egBPXmnW338sbCS7U@p7>?wAp9`56~<E|heF^o03@Ot6#OmMcg^
zET{sD6Izy#V*oT+_iYdfTadl;^d^RM2K&Y^<k2#&sv@vG51|ODisQk(41qVZpWa7?
zVKh{!F`Riz@}GPGzCrR(+7{9rESJb2BFC5mP|UWuWbMSEP$4gtSp`lqEQ4_Z+kyHr
zP>7FMjzJBX!eVTajV`o+7wAJqZ8-ot#nui3k%_dpDu{yky;e|_Xj{rh1#@Kd<cnnR
zFYbI37!dWNTr6YUaMiI&Fb{DZjFbc*#GYe8>;Wx?Z`)<rx46`9P9VJGKFE>+Vp=H8
zq0`Kebs!BCS$a!#3jLP--84b|N4C1v{Y_@ME=WeDh8hdGi_9v1B2Cg1X=+LNNY;p!
zR?iSWC)oCoXGLh1ib5wx8j==B3DO3fVVLl986sZEVnpXcfx-BadE(spo7eDpEy&`m
z4nfMYDqNT;jEjlmgkA4B!bD{IFb>N?MGBa839yJm5mm;9og%Horqj%b5YT})MC39&
zGCP<LAw3UA>|^f+F6A1?FJXw6X$ilfF)I*e2!@yuu8RKK7_tSjXhR*S;M8V1%(lc)
z6)j4V!;6S*K~r3fdQy<=V3jy8pMz*BOVx_}6*}+y9xDu@7cVvOPF7{X5loLkFib!}
z$^{@Ll?NoPSc({>6eB|&6#~v`C=6m^DYR;*BNELF1TR7bQPe<cc}x<`8q`3pYxPH8
zEWI8jU*R+^g|4wk(L|yy`2Z6@el4Wy#4WP*L_z9Q41f>-oejU342VsF-OBnA!lmV4
zKqW_vDHoS<mwWS~`7G2}*HQazZ@#vHgi#LeAuFQTC|UY&gy|g@!OS9mX^W^UfD(g<
zco;({l&FD`ib$Do9F<_$M8I%(Q0n|vDfbHD#bX_~k6FFHy*%pocvit<K?U%LO(egp
zkAwcqvJJvRes?iyRW#|-9$$730S9*vwMtH9_`HTDuL|FRS;y>Ls8Z+9TZ+JsT8jct
zB_l%`7e8#NMNnaOW2g=vhK6kM6O?rzt5o%F$n1C=Y%0i$Q(3sEWhgNZ!KSyt*1u>V
zO0pXo9Quf9iYrn*_>ZdfThrHnTpg;j@HM*UZVZmp0mR7tR>r6sU@FcU;Ic9OsE&43
zS%E>#*a@xD^#hs)S#TK4Yo!XjwvGRMq21jdbki?Gd5hF@>8z=;l9O+8=n0eqlbMWF
z(@2g3mGi4TTR<!ro--|^3a~Pw%q%QD$g0$hs)*YHc+MC(nfilsdb(eKBy~&fX+97%
zD*g#1Bmu{qF%T18;=#R)_{NTE!em(IyyfW9%YI-tgqZg-CLOsN@m<zyOJDX|Syj;A
zmyjpomG$>&evCOa`bXbfF7CPUa(Ykj!N$Z16s5FQ1u3dSZG+RPMo-LH;o4_{Y)3Zn
zWdTAeJOKct0SIOU77;juxBaqr$qXdVoW8r+IZ<CHuf4m|7Es9$`j5!*$67;fWrqL*
z6(~?$3Q{%b#W*0B+WyN1;*gZ2?l@H?)CIG$VSWKwUCx8%=h*L!2U|>o!3+sI?@Z+z
zgpL#UWN__HOKqJg#X7xg78~#XKh&Eh3GvetTLrY3eqv8{wh9a)95@Mbak6}&{3rkc
zXgdm6B1fKR<Sy$B`$oxb^&QPdS)m7-Qo3IPV=x0>NKzm~902)lX}o2FN7`D;={{%$
z=tGdLQbb_m3{RZJwG(88(*<VG{FCroC5Qpgqp|v<-&iOn2RkdtSv}nVHQ`GOUSB0J
zSg#z;kh@~$$|p3{t*Orrz0}y)33M|+J+>0g8D`@!?Got;@`BSQXI6pUgx;lSU4ZP*
z1hkDCfEie;)oRzqtT2E;68U#(!Uz5s0kA(};CfLs`sj7$RO7GSHxs|RS#}zGMxFf)
z$ZJ>~4(ri=Z~<u`V2y9^OcxMAat~04h3iCffJco|g0+Ll2&aumm}k{l^U9id&g9~Q
zo^^<F<$TjCq5r{6L=glM+m!+90D!RHe<vrNl~y2gEwO<hBQGDS9NO`R4;R(Fzc;Y0
z7|QNV7`Xinb`lk|2hfi;lI=?_b7inB&LMNRG%k1{efEx|JUkUog~YOhzG2`;_(ott
zVTFMt=12H6eyC?dlnhhc`YNIU9&rfSn2;hT^biq@Q#=Z55N*OMwY61m-us`fon$FE
zTa?o7>4t3k7SfIg3LAcFUjLdqmrK-QQ_Z`$OEQS4TL@@_$QWNim=GFhRR!;r_e&ni
zMy)ZAcPC|luJw0GfiudBOkvO=5-q681RSi2VPG-s;F50hmKR=p=C0y_#{SNe2jrpa
z4VIvboL*t)A2Mgq@&tDQ;y(i0nMK0qwj>jY2XiFU>N9+-J_VPiiB6I7q7?Uj8IfH%
zk|z{aDW67XdDc6XvydI3W#$jg&`M}`iJ(mr_XvWmr9_=f$aE)5Uih2Y{ZE9>p21|Q
zfqz%zJbHVwPHLk+6zqdo$ynqhIFf~BrzkNudbNGbF^Y;#<R!~9m7{>WSymL2(FaVs
zVU9Nl0AvQ4lqse?0`?E;hKS@I{MtUopJ@3?CbN#K?C${7t`&c4nF!f|43iOW3F?Gu
z-%!sXK{kBL0XA%h0w>}bQMl#4dqW+UYYt?K1znLm6ZpxpYKsx8s%(Fz;A<p!dw6m9
zf+4*uf&4nw_RI;vfC0`(?}}Ic)Ydm<EDKl;3Zz*Kiq(t-LH2v&50;{%j0bL=u%DN)
zFBemrtu|}s5DNoA7uBhm(H7;a)LTfGStbS2VvP}+9ar)f=0fhjk_l}<Y(I9t51vIg
z1*NiuXvgv(1+3z65e1(beQL)hc3P7s49HGvvcDNmPgt+$yt47IgDXc~xkuWQugPp%
ze@MY=(c^xK+4fT#t^L=~<9;^B?(f->S9Ir<?6_0Hj(g<0P9uKlKXI#G>xIY2E6IQI
zMly{r{|}>&cky@q$0-ywn78eH!)smszv?rHIeq*{6I5%BjtvF^j)3<vBQ7tMS1j{{
z-vkp?XhA9UEZ`>`1#+$;-m|TL6;Ofv+kAw}PYgmf%%#S(Lddol^`j8=Qi6Z*Y|Y4K
zMrnoD0)y-!K_KwwjVK^4bhJcdd)?ZX58-v=0~;J{JZr*NqAik(1A>Nti!bw4Lg8e{
zHdEwP!Ng=&337wv_=rn+;Ux1s*904E(;!$jnK=FO*h?Z2f?!CgVPsNql4T$gdiKss
zJk<cet2W4;#aZq`3*!E)TSP@6k$wb}&?N}Ty=Y=9&MZ)Cl;R1KBhT?IR=hm!E3;55
zJ9MzSOeb;b6^kqxbF%dK;LItuk22U4>(>AE8tx^fN-%Di&BQ5O%T9=g3r)=eVsz-R
zQLtDOjGIvPC?k?aa~a`sFv;1~W!B8Jglr+(#pwz;Q#gJY4NIPaK=~w9&SdTg>1GVe
z9A0xcp#0jE|LstrF-Y4RRt!s5Bqtn2LYfR|0sO?6Hu<<aV%P;vXctzk*}><gD?+UT
zToYCa99^?erDI531R&~7fPw3?C|`=Q6Y<qL&aDq!TWG*$n2D`P!}`P}smtSLbYFTK
zIy3AH!xI(&f4cY){fI5nu!;tK0wrK`J6r9n!YTlrQtTAtqHxHDx|kXp)i~j!nyqOg
z`T#YOyPB+Le9#q+4yD&@BP2N7m7`}-3CLfYGbPf7ey|K@xdjwyg?^K4vPH1QHcuc_
zIQkitIJQuTDH(NPHZ2K!L!}v^BuD}dJu&nOKM^|9#i~N^p=&G|RaBJ@);cY!L@As?
zzbmq58w;zrZsvdfXNYqYy*CIRiRRB{U`%Dx06sFA31bjqTM!-~FF+u)$LUdIMu?Gz
z&{C6?IGl{^X#pSZB=F>_uFOup2_0aQ)%j|&GD<{P+pJMorVLxd8NLc55CsmT2#CRw
zg1Qz5p)0I>B@)6MA^|QTCKF2ZfHaTzbY-axlUvM3{K#3fGzU}w1O}at*v;(|-xJuN
zusMs_>rL(f>(_HL<`OEywBf!I$gXR#%m<k!{4GEfaE&xyzU(vBbc~N_F+#^FMGwY_
zi5&|F(|Y>o8z|fDMN>^~wpH!}h>f~HZEy`Y6B&T8q89Y2aM&=MAxs_9Qv#W+XahVa
zle;VM7>FQ}W?mxkkbi{8+(MeR2s1VnJOuM3A6xgXTobwtdO)miP)F_xmrF7fViu|j
zZ``2ya2rHtbGb1O=z4|;!)43`01oQrHv)1ra%TXloG{285CDx~CSWzuDC=!Mqynfm
zh-~snEM_Dh5%`G=ai&`*wBfrI+K8oNG|aF&j5cJurA;>G#sDNCToMbkL?kXlE3d>>
z^brluEfe2d{MU}PVp&g6k}r4y5DpY4F;KEY9<V4Ni!BgoCKpa%8aTc#r8%I2G_ZSo
z0LY!8hCGZK!~v1e4eS`<JLhoU8D^RcH15+PW2sjE_}3_U+=?s%21+DH!?1$%PIl3w
zQNX+MAr?@KQkJ1B0`VBZ^_d!i(BW4ZllKYZWT`NU@NpuC>+vG{&p2o57e6H1(d8oG
zau6%YOv@W-508V9L+P7LK^h|;qJwPm=orlvFe%~?8BsrsmK3lf)*h;x3zVPOM7jgt
z(RuOaH_4DALm}7k6{C-N;Il;j$_0R>as=M=nYIJT5F`V-!k4+#<ZV}QJr(0mI-oKY
zxe3B#jn!snRpNKL`^eXvlnSRokq#z=wS&`VpfI@xLK9gaw2Kz7o^XKRtx#bY5Ua=5
zEF?=PGGt2T1)w4p28b6rl{ZrJp6iKO!%1BG+#m8Tv}=Rhx4^TuMT$%mB%w(U_4092
z7FJ7Gu$;?JmRU?it^%YfSU5sbFVaP>&;PV2pFAj+pjezFGv8nR%qKzsm2cWdVwp1x
zdFyz9k;N9|8@`e_0EKDgBqwa@SO<;~IfhJj5c65FV9&C_KKl_s=WDXZ<~H4hsuo=`
zm0&j~>ap+O2Y1<RfMQxkv_*wGpo*-TstPJd&8A?ws6&ONk{8Pib)S%cZNFNM#6EOe
zBhKxg90+!9ot$c7xHrelE5jNJBa4=C-GDam2X86ORH{<#QP`m|uza4e$68*OVs?T;
z6@ajGYgd)s#&DrHh+WX29}5)K9isivwpdCduE|ylcm^<^kQ7P4A-swTwvZ7=OL2YF
zP9`Xuw2_Wz5u`FHefKS28Y~5}LD^vKU~^AKKLtQ~^}ie;%E6<I@76&kIVOjp0Kl#y
zPT)g71u?NiL!ts|l28IAlHkPFY8_&_3O})W=O0U9s6-rVM?SDxEM_}{J%fJx0-K@~
z;1u!TQFsKyA8WeXpCC*wJ=(JYbD*w3K!N~5yg7NH18Ir9&UJlpT*Ar{JBQ5)Tjf31
zEkhlT^*X}|v`Vn3V=0AUEkD0Bc<$v0FzRgO-vtz#dG869PnCcz49-S*ty(RCabckP
zBlGHbzBQV$j`}<&;M*NS%E#S(rz5tE0{<DvU~>0IzW2|?Fg`hGHTDeV8(kTx^&@x`
z+0yn!L6HDrj<p0i=NY7eMF<>1tBf6j4U{Da2H_~#RGJdi3w>o|9_UIAEYn+6GC(^c
zK0FcXK@0c-vS&Yh9ndQZO)d&{!o7&S1;)tQdE?5JDo(qwJKn=KxIC(p5SK4835b@-
zWdU)}(t{l(`?no417VJZxzap#P$Qhj)n(i9QVz`YRZEIlcj&BN;bSSQoS-cVzyu18
z42hmlOlYtqS|+896PH_)=r(0@GJ*sAyTnobh}oHr*cV%WBGTS-)BZ-<_r4KZ`_IRe
za(eEW03rw%A|!{fBSQ=j;Ye{H(LNf0_++nlSvdqCA_xYL;SoINL~<agxHo+s&e&&}
z(40rKFLk_J6TLeMX7Y50v5*by=RMOOAw^HG0rmt-5zY}Sn%h^me{Rs<GdS<XVz)7E
zn6iVNQ1*YsI4K`B>k7^#0#jCr&jlVtn9?u`N=3jI!5q06^_+_l{w-qy?599;u9kF?
z?6ZNL5~ySD1R0T>Pb2^eyJ=y^-3rt{j-_lE0j$04BQj)`s95eqvpfJF!6S3R%Pg*9
zs<{9z$huT0kX#x%Vhp`PtF}So5^kH%d`D*NoX>5j-lYhVZ_!Z00=rHeDh-%~zx(5W
zdSaF*=)2%7ef8Ua^``v|Q6LMvC0`AA*A<@*k>Iw_oJ$bo8L)iYF2P4c8Uq<Ow-f+{
z<U>LNm<c$x$dDftKex5W1HIw!MAVsoQdSIx3C^GY?&r@Jg&)UfeRb=@*Y4RY4=V^7
zao-cp5-xL{ra(v%PXj;-3C*h-l%9lYMSLstA!AoQu+UioOu$Y;xvpKTvNoAB>T{HO
z3V)9ROAs`f6B)P=Gf$9L3Pzhofb9^JcY7v}nkZa2Pq`(aX3wVXH(Wb)ob>16n9V$S
z_BW100{aOk^n3=etf2|<JTD5(+|X~b4iodhGLn?)K1NRoLr4+-+JHttM}U)O)aWFn
z1sF!MT8ji38Yoj5iBnuDiJX0y0$jw*uteVa3HLrX!KU*B-a(9SlLYEIZwf&N6i5;k
zVw4Hp30(L@ju>H?*uaK(4k<=@{g8`rT%}ku5OfFx2}2D*E0Ow0))Xn`gc^m(rUg=m
zNf*GE82o(%036FP$=YoPUiL)ISCvk#Z^Hl5p7pOH5UoFVl2gjBd<y1&34!P*&(i$=
zgAcVqWs=@p`Oi_AUfGh@*t=});eQjJED~lnaN?O*|HUs+Z6<g2(*GN0ikoDueq#C+
z7m_*pcfZWv@%3AdkdTrXBOr$=o}~DNk{^bv!wg=G)=ME+E+Yqf0>L`M@(=42%o3f(
z5=rE77@Hz~n&gN{zcL$863kSTvK>_v5gDM-?3AKNkg;I~o7C!oWbL!Rk{HLDgyWdR
z?5rWc1K0rWE?g2EP9A|o&RBv|7r24=fM@{gGlu65e8fSv{FA7m<p2<IOcz3Z#3xC_
zi5TmQ`6ON_-U&`-kesa#CK1cSx;!9JBV@Tbz!$zbOb9F!H)gVCz*e{^w3-Id95U|#
zW0ErpNTTxyTsxP00?r^40#V_uW5WTX$bAxVem%a1t~6p(8zl}+xN3ga_+`U249FpV
zJI9H9_#KLunb;w|w4b%?7G5X3b_oDh1T-PwB;rpDoirTE=fuo+{osvO@B~ew4<U6*
zE`cK~8JnwPncS{j3xdstzS4p`P!JCtt0;>f?jv_CXf}Z3p4dsQA<Ps(+GHS*0McL!
z0F@}?X%p42{4Mwe+w3>?HJfw{#uH&82m1@f1$MY0Kr|ASHRQ5~4VRWyCa8)PM#zBX
z6AsW$@w=%V>e}KuCj{ZNjzHGJ(WTE)rN+bM5Uy;IFAoqcTzP)QYOKWZA9@XWuH`r5
zW@EFJ#digR(y`j+*s}I=2X<}`pjIU~&V0<+0H}%NSwe}gXa>J<8<4I6Ndh=X40X7?
z1#2Qz#;`J^pl8@yVI*wRtEY~^BOXLFrrl_6ZVy^kV}Fw?<{LWmXtsbYlk!1CcJx&u
ze}pQ-%q&`l93nS0s1%<j>+w(C4i4aOW{`dH2Ttuk1}JA$xH&=-4Y$OaBhLJq68f4f
ziDrRAxT2iOHMt9lZK1Tw9B#BF(89VRaSbk&peFLT3e*9;w#W$l$NyfMxJNGAkZ4{A
zUA*vnB$DQeA}DSkdM|(R!W87cxd2lg-2tXTGE|1}Nf#rLzZf}k_We^d7po;h!j0mB
zpp*zfqHUQ1j56B1ap7DKr8%PhbO(%sgLrHy99^cG#Kg43NDsNO+y!DzYOlWMxRuJ&
zUI9mO*k(+_pmNO8QDSor6ZC}_F@8QOqU<6Q#K9YGgmmSST${mWwx1;7g9SkEF*y>~
z;^sj>3+*wp_BYQF=H>&vE)8KeaWiZgab_VHG$;_a5ut3L5KPJ3NMH~1u8BF3*@TLB
znX&vK?cs$aLIbXx@K3#E7arctd}9Pa%X>qSgl{br4b!F}BO@Y|FX+Lt^eML(s8!xc
zIT0%~oGVYRdss%MT4>W$#KDju&SM|k%<+M>hi#SDXDxz2v1@>^SPR+|JRz5E0XNC;
z$=Q7R(u<{ma2vBoJ4CT_F^bH&MVJT3G%j(z|2{c`H6Twf@;0swVx{Gpc@GL?f#oH)
zT7SuHL_OG1TuiZuOAf|9vC#%*imu6lrn~|MN|?!`h<?N2UNRCmW}|j@Wh+l}z+sZ6
zFhnAhOcn@KOYV}<7rCV2JtKj8V~I{k7daBf2qy^!8rs}j;9EH<ajYNw{_9d6Bg`@K
zg7xO|ohT;XKQ4O)Fch?xvt?Gwn4=8qx8odWwDcj@D8A+LGMIeKAM3g)_t3TH|A#HL
z(G|Jl0*f${mUe>a1`Qz7!A5@X249N(;DmS`?+Q7JR&X$S>!Sy`e#^OhybiMRj@!%_
z>EKfzd);r2f-B$5cP&rP#>V2AQeJa2yLg(}6%y&-+|6vI7}`&uf!Q9moidqEts$KX
zkr=BHP(u>2yfXaanKFEQ4NhYs!?K=bBuxaVVJ#WPaG~vHxMRE~EF5MS>OpHtYA)r;
z*%~%XF!ucK{FUV&i8+6&Y1-NB3Xoa@U_aQ33IC8`KJb4JoA=EX);)_OOe@~kd<U=y
zReYK3VNcVzIWVrM2#w<pR(INqv)~(WRLH)dquGpMvEfsQbJ!Ec1#rnon{Z;hj(}4c
z^x21e@ESD|tqm{s@u2aLvm7#!OjMA`h9&EeM-F>zd>`i^$oeO;Qj^t^mdO7bjj}-o
z^2@yRJHjH8EaPe%Eni+egEu)`f{I_acHpmS2cB4E!_5N?b}gG~1l_5Xch`$Yt8F%&
z|5)=tWBX%-DtktshmZqaLNs%p#~kIS9NoHSbgC2NF*b~x#c^ZZ7!6XVu`^qiaFqx7
z@vDU1u>46`*Wx&V_FQ(xKSdDt=x5^dnLMCxo;|qT)+OYNZ7$iMFUPCo-{IXX)Fo^S
zC<EC?3<fuaJu`@aOKZay#3IL*d2;hzK`?k%a1h7hpfEDN36fXK?%uj}^O>Sex8#_8
zgX<0nYD?Hi!*ZSh_yyC1w_H@}qR6YTfs?Ra3cx~g7;>U<`KJIUgxblH1kmi*P0oAw
zwJ|~EAIU@bzR5jk-;*pTo6iJO4Pjvfx5iUFE4F%5QV!FIO8|@_i+nnX>D>4upFR0|
zzJqlkO%YqqeZ>GUx4JfbWLO6L-^Vj=e>JdIAO1@1BmZxE=N}`-dDih+XVW;up?k+V
zI-4|^J1%JLv~rC~Vv4Hlo!7{5)5dNgiAqyDfN0f_UJ!pY2t;=5ae67P>a<C*1d3e}
zpg>zE&`JoB)JBdPXxz9Epi)!CLPDTYnz>M=sTyHE-{*a2cJ^-XZg+1k-PHT~JUjFL
zc;4rI-sgSZ=Y8I1-igbjr*`n#%#QL$BFsbwrrz5at-rTHo8uj^x_Zyf;EL*w@<A+f
zWjxn{Ak^F>;K*qPi49^K%Cr^x0}_kK5P78}20htD|FbM$Rk_}Nn$Q+$HF@x4y?mB)
z0JNAqG_?*V3=pw)%V4o_oB|D<DfSfezdSb70vD(U(7Z=v6s8A48m!9I1=O!6mluP;
zS+en?Gw(4r;5U4X7qia2>4K?X6ywe*M2y<c6vk77wR3R#@(7yC#uDwQ((5$A^ky0;
z5b9GZR=);TA=NXIh0<t%=TcyF0R>88zOe)Gb;5jzt!Ue}(csE|T!UK+^teG}y<x}0
zn7Zf#-KH0M0{hFJQ|16e)1OvKqaimH5kS?4)QaRVdQi2biZt9~BPh=tJWCD>@)nZq
zKyOpQdl-Ad((c(f_`P@BSzQ<GSVtw|tZEHH>~3tLnp1p6FnF@M&LV<)_cW$-=s2_J
z;pq_Y8&B%RDOp=2(3uFMHOw{fCRhg(!qaS$qMK>fv|TQl9duebmN#nG_>;iL2zlny
z7ac+YmKhGgCHNc%#msw{6PnN##AD4;BOrxlAPjWm5)IV6e1e`;t@`L86c0g2vl!Ze
ztok^*Fcn*oh|dn<G6KE_O3Afz`|b^pWZ*nr;-x9+o0vl)-ilbe&t#qnNi#*PwPTpZ
zMh(8%D(G7pti_G9F-Q_xX+B5m<t$ARbWRJ}25?LiHhhE}ivn3EF8`~?F8HDNr?h#6
zWd12DaV;qXNV|WEo!)fgXD+?R4o`1%x|T6c<o_9iFMmn>S71%Kv7q6`QG9UjKQ`ox
z)?u-(!z4qTAf8LZl{a57iv~4%is%qUBaWkesM~C^NHIYZL9LZUlA_0~F3A|eEr?MB
zG=ob=$+8EAmcT+2eIX(uVpgUQssgi$cA=2taG|usa01uk(cmXu{M-LT%p4xmA}L0F
zs-Vnh9odYS2+50x0C;FsqRQ#?Re%7EQd)T<lsF0-rj?jxbt`pN${UX$Ii^_hvmM87
z;)@?V4b~cgfJBkQfrT$+&F(?Rl+3Z&ku5#dLLsW~wF4YQOyttqn8rgVU`uVKwWw$z
zD;mCyM7zMOMzh(k4c_-|guh!wScOg>7GVGAZgq8%-aqTX5P(QiG1@gKLE;FK(U^(r
z{^DZG*y_8q4pBroX<RP2w&WrpZvH7qerArz!j>$=yTWRp1>5><<C8R{^-B$MSClEj
zP!Y{*$G_-Zrz-1Mn3SjLw-~|=7Q$<zhQ84O8C423SMuH=<z@r!-6M6V6x8R6ekl71
zU0<)gII^9X3`?zZ(`FNiKql3N45F1J&PBMg?miTBEPem`E&IhyM*FypIM{8?sg&#G
zur#GKa>hX@UP$rt&@!+FfkY5+tk@JYef*V+EJ2n(Q~})!L!*~sTz{u96+w`!o)@y(
zqKOyY{$ukJ`+vkWt^dOFOWwWy!ue5sKMxV>m2?A6F|l~25S`E%(0}+`>X6%O(yQ$f
zLcL_2+w<XG3AK3sAp<W?o6afi6w8EEduAyQ^CTRPmN^%#C=Lp_{XkpZ&`D?y(4=n~
z#SD@Qvcsh*x#%F+a+^G7($GDMz65Bcfm<8}lfU`7;6ydDNSz0-naoX{XgsngqdzH*
z;PH{;BFYlnjs?CHgpp=V9}FLv7+G+YnCFsD+Vs|7MrD?>?@Y>x($8_4<AF`(%!TF;
z39$?WdRq#TL~7ycs>gneHihEC8m^T5<im!Q(B^$zwPG~pN^LqviQ6dRzlLVElCjx{
z`cO*7L0#pg{<-Q@`J1g-Or0T{GQr(fvrU3VP&N~{&SQ%x0YnUb6<iVc%E=h-Qs8Q!
z6Td>IaXB*BWKR14P7w>5_tiw4!fuPS2BPZy+u3<d?)owrBK}M105;{U8&KwGFKRLp
zCdJah3LI3*xOi3SsHXh`ORT9YX5Os{wjqU8Z3uyF!3^3F7FM(J0>iK-3G=8v8snhR
zi3ZB?gc%{J1tVUlCRJYk>L*lvz3gC$&MN6ZVU-j#^(+O9+m&D?4O2b2>=viys~)xq
zYQfBwi%`)~#v;~x;7S4hLly1asSvf`sb)8xSy0f`qgenk{uG1+(3@!gv>uaE^4+cV
zN!eJZL@XS}4uhd`lgl;LSk{9QkGp{3mrS8n5wImiR17d?ybtNleK4F10GlykmTvsk
z1z-d%E0cntHAKYj1L#L6Uz#(-rmD}BM-kRjol02aTF?*C?jFw2dzBP{k8AbW{cGwk
zZ+(AA#W0E%5-ulI)O2c_jbO6!KBAZwP(~0NOYosRq|j|JgOpbOT)|PKVm5pG%@xc6
zkh}qSHozbfyu`C_1DUDbV;G83h6E$56)ag~6l^fDbrDXAoO`lmR~aUY*^{}f3U>xE
z6f`JlX?3=B`27CWI>lP#YvKpQ=xc3H#ZBJ*pQ!A7`7QdQIRgM%0L5noHj&g6vkcRn
ztBllE)vc^b)Rrbz5|^)83icjB6&B*)#v^+`Y$CF-Wi>{y=ve$K$riE(G!P=yxMgr~
z410I`X6SEZv`h8wZI{?cZLr5CTw|^FjOwz_NTvx<6;bhQCNZ7_FE-K<ec0Yfgj=be
zSG&RUFx(f>58;}i794%z((Sw!EmL<ib!zJRh}}<C$hdmM`0Vgbgf=R0dqhT1AMkLl
z<nTmnf0~{oTTD)?TW!S%dr+U}Tekr%Ecrkc=Ymdc8yh{qo3;9MOgtJsG|n4$qxT<u
z>UG;MX82J{rEzHM<=kSmp3=@TpVtNy6>}N`G~-|lZPKpAX3nNUz<;$3dp&J5w*gwL
zU2kHW<BZQHgh9ebA~%d~U;ANjBCh!q3M>+F`~&aV!);d{y!Z-^U8h;`!D{C7Xbvx&
zrNR*@*rddk`t!DY7U#gV_R1<i6`-m=b%npR8zt&bUVbf;fAk1*MQt-}p8KO;KU|F~
zcVR0yc;xbM<dz6;!h1ROe$QtPl(E#8g6(5ZVRWY}Vk~x}2QlYG`Yy%Scu%}OQQmZ6
z@W}o0d)!#U-s!CKO^og%yzYu)0U0JSH#_q^QUh}=U3P3l{*w`hfsNmW@%{_=rEPrl
zep&D9Yxz_~TnobA{I^T&xGhK=M|`y*!e+>QfT>T0Pq{YXc?U)~0xANk%M^*-m;Qzd
z$3`T}c+eP;A=ule)n{^^GDE$-fcpD*G{TI3whdeE0o4)8IZU<bJzF4Jy<9_BfC}M5
ztd@*J%+eC?s*@ha#tU3=8;_wz1--znH+_SInT+in*b*n@$#9%(zxmk6ezWB2Jw%uy
z!eWoR7LIkGNg15U)J#UP8Z79cuTbq1NcxtmLKtxeD+(PlDoAL7##=!yoGRV=#vu5J
ztP|u6%}ES5O8fY!ooEJ8B|dm%lNMugj?@&@z%Ta%Kj%V1>Nd-|V!?vB)$cS=yWZ~H
zygw=>yB-pCB;3e?Stus2B!?PD$EihZN&pR4LSaZ|;cm^bu2U`4PGhWFt&=6qL`!4t
z2|OryKKkVA0~&-3<x9DA4s}q1;S!vgRZm2!j+WiY_PlEt8wP3-j6$;Ui>l>Mtm7{H
z(l8iWd=!>&!_+ZwW2gm}+$eJ391z>rK#fS79wtfdbPyOZP16pcM%AOg2j0OW(=-wn
zH0qMUTwQ`?n2THjkLgWHv^VN#@=wdRjpKa$6Wig|v8S<G%QyAd1R3tQg-eXFr=jAq
z*fF+X$B)VWBPuuH@_O`J$f$sqFJaD;kX-7VwW%JVxU0rd+3o2v_7K5^f7KeA-{EPI
zM7V55@&v&*uB)$uxlW96lC&K1eucTJa%5UEgk0JLlvXHzJ;akBU}vXEW@onz2vJR6
zC>^r|O!J^e88uUA{uE+~kB>^W@qK|<v%|g!+xUS}^@UvnX&nC|Z;`q~$KG<y*LSY!
zYou*v`VPkNqu=fBb;>psNNkV=i3U?axK__Sd&&MRMbTwAqwlcylWUG#KY|lfRBx17
z#vt}#6}=_LD>lG2oe+NIMK?1PGelq<H<QB}aHNz7Mk0<TvJi@e;O!9A89iQugeVwG
zpA>yV?dp@^ebrEA;|9Bj0vSXMSC>zNgfUlVFP|3ir{S$Yg#iHVR&jc^0n{uB09BCt
zg!wFuCBOR9$SpaK*k+Wiiz;QQz<`d)%T*>@!DpTq7;6sz!9so}<|#&_v<6XX6Pd(+
zQV7%%AFlo36S`LrTma^R>#Gz=L(}1lB=K{c5)GVBpmeh5CI`b62Vx3`4j@HUI1F4i
zmE>7zDV2B}tGZNomA{V<5x?Y35mhlGNt(_t?X;dVj6I3z=BApR!}9}|^DJ;k2tcq%
z;a*gbzKqunbx7!g3_<0T7M3JP)P?fuFoprH@w;&d*(@Y4o%VNvYQb7BE(AIehEEF}
zVCm0wgX&S`?cwZJHVy=Z{{|)l4Lt3jq`@O=#tMfz2#TFOMC!@GzV666PkAc!ff|e-
zxJn0AXeHXc1CaKZBemsglKspdWJd^ET-se|b5K0W^0~y;Rb>@4Q&CIgAGyEv+Mp#W
zwALYxR*M?C7eNV>cNnQ_nnIj@m!g~nCAS`rey^OR00+-5Pu*Am#jhT4I%w&XX2eFa
z5aXgjX2J8DdteMa{<G;Vze3VCI>lG10P+oFfC?|)-cZBXuv9f^4a9u-9>r$?%_6b~
zD9Qxw`YWFw3{yyHAu+GSfTI$z$@-_$wDea%J+L&Y!*33+3|J8C{gc<t%bTJ|w5Mf@
z{KTch%Z*O;JkZ*59KHL(R?o|uOfA*AOaqB7vPWO3L&^~lY6>w8f)rOh(|8|}4Zoe<
zs*m!$t=_U;10jzgSwT(6HODnOC`HA&pm7k@!aDihE1|mFg}NMUwSaT0;<&>8FN=OX
zD?^AtkvJis`i7C4d1wOF0M*r@bLfb|L6LN2RXF-4w~y$aAP8Hp<_a3Iwo`yDVj4oA
zf^7ZGsV-3@*aS#~%a^>uN}<7(K|}x9;mtZBdG2?ct>(aK=^sl|)#v`K8jZQ80n*Ka
zKjmR)XMcKDc>WruP$+>aJ3fsfI{6E0H~k_jo-fZHe2Na2yo^z_58*cQ08UlBKcy95
z*;at^fp>*NE&e_|j%Su7ZhSO$>qGpk9q^6bb!&8z7uI4{m}^lx1w0r%{<i#P9IvNo
zxj@5&9e2FTqV<rT0;%h!#Y<1u1Fyk4uN)t(JY*2JSnugMc)pP{Uu)vl@{8p`wj_b7
z^q4|cNb-Qi99OGK&P7IBphH_yZS`kmg5XR4cWKz_B^WrXKpE7U)P~~=0K%#QRaMcd
zl{Jx>ReZi+%WvfP3|jDwc9u2N<rk%XO_gT1U$`d}u7<u_%P3x?1M^&MLGseLmB=o(
zPGj}LOyO5-S(0ubfgm$h03Ld_g(84<vC2e9-uH^T(G}B?T5t5WWg7Icm8}v5&VCJ~
zJ)3r81E8ry$U&M9N$mjqBs|(S!Xhdm9x`^?34_>vtwIJZcFqc5lMby%6Wno>vx^t#
z<j>!juYvP@cswD2=c6O4fNSNGgs&11B}pWlr~|gxG-<$Smy5>(l|jWCj1~dLWxw(V
z>+Wf92H^1|q6%r3T42fbi94(3M6BVgH60DNWt3ZZ@y3<(pxemiFkpQtuO%was@ih@
zMMI~f%f9~BFR;A2;?N5n)>Swi<>olgX#M^?|7c#8^$W$7V>h}<pL=~k%#Z~!lK9cM
z*vD$}CUA8(Viv8({gcmi{0DHO4>}t)y?5Z8B11tRLimpPR{zr=km-Hk?@w>F7-8ju
zpTIS*`_O`rM&#fy?X{t~_g&uQgS^(x6iPq8=icUgDq6UBD6PhK4>p+|Z)MIkxIZ-a
zj&)|2zS{iFhgz8FE(Nln-R;>rKka?a_rSu^CTlyFS}gV(?j_;&<b{yi(-(P4{<)ui
zTLc)J?_tKGi{$Axx|;m^KXjXS`F!ne0n6uKD#w8PwJe2t4{1=WFhO3Qd+zogs$M4R
zKw~z$4D#J2%Vaci?z2*1a%+ic*`9N%J~PY61d5VdLg)<-)Z^ZZ@M1e#HrL+O9cta=
zDtfdP#fbINmIv2$(}1q>46+=cOQo^2>Gi2{-BGRYI%~3?EymX>@a4Y1ay}hfz=xjg
z)6*#N?kg_SyIzd>s8La&NHHC-638U0*so*AslXl6Ewaw27<uMHEgQy)^`Du?0ofJ=
zavqjl;Z^}q@=d?#U=aI3E^f4tNv?WF>tQ8#BHJUsl-o0#*S@Y`*T>2(pBj3mC$Djp
z2*ww!B{}_Ti>CFQkWODwcO{+kz+!omSKhN&(jxKo)|%3CSkrypb5FDwcah><M;AGN
zRnJ_OGp%)vLg$P{A{L~b*}1CTVt?cjGgdqEubr3Cz0u0$9!QGWfW6~${j{fJnabQv
zCowf@x3&<4d`TU?8qR&C))9@qA_sMNoHqjHwX008D&|8?oi9Lc|7CYx+UjfSUUpPC
z?6og3qMaoluDhzG2_O`E4_P5*qspT-KN%skb0*F#&+_0iEl!i$`#&#1-3sQK-Focp
z?wON0eYm%x3v#b~qLhYiftz>Ys9IDQ)EQ#HG`pOa*CP+4U9s{$5MK<<Up>)r<wGe~
z-H$x?o60}4p-{7ExR`||N7&_WO`tvVc+2p!e37MdRKE84SI44m3jEwl|Ftway`&b+
zhDC{#;Lg8p&Gx-Cs8ilS9=NNj?5-+szJG2`44s^Ly0-eWvhA>!aPHub58YvYXznmg
z?1UZk*Raie*rx4j(6to&&wZd-h@2MGGsjbvM_3W2?AqTYd3je41#4N}D7({5HAUgv
zu6ZupZP|KzSc!<TnKobDnVSluf3On7@;KRj(X-8h3i^#0BGxPAh7=o8tOErGT3j$^
zy(*^kV07l=gE2KM=%L}TT|km$BA}Rb9UNa*LDAi7hmO2Pfe%&m<y7=#SgZTwfflRX
zH)ENct0A1U1YU7SZvDFz!^i-vMk_PmE4djW)+_af6dO{k0|kcCx&u*`j1t9$+WCO(
zJmz|AkOkdPJNNI+=3ZT8T`|<ohuZlnPeko@@tn9={`SW2%s&NV`7(>;=&hBleTw<;
zoWJ$n|90=8&QI<9obClINOeZ}<jI{2Qu>Y<Bq5wR1*tX3?>yFbqZSk_x|K!kNS{CN
zcrECXz9Wk6%f1oG6*SI0b6KH&DLL>fyoF+gFs!vQx#8!F+ld|dpN|ez^gt?lScFMQ
zd~*K0iaylQ7wG8qxo7`r=#2iVIiuI-K6PJV12;(C@R!9())h`0t>UXP<!bo$8B+J<
zks$fd2m6H4p;+3?dJ(ety4wfq<;TpSC%I{W73&VY(qB~Cm;IG)D^)MuabH`+iXI9?
zZ0JYTb5HcPtX~4W*7eD!PA-w7$E2e8!j$xx4ZYYKmd12sX8k%O;_4sma{f4?pFhif
zO{L9JCwJ_X`o668(Jrg!iC&+3ur^fEms8TiB9t(bY}IET?_?KV)XKV)IGhZUYrfws
z3^mz5+CpDQc?f5(N`-!^AGd+-?cvsc=`H_Kxr>_GR7YVGxPT226BT+1gG#aU<^+ab
zI&0~?gW8ocsw|CpFR4YgvO2S2Fy9}1RnK%8Y)ACM)P|uQedUV#YI~y3J4rp~tFqG7
zMfHVy*9@IqmUDI~WLHtryzn!3XM33=mddNw@Rv&ODQ%#Y*Lq2d^&-MEALAIDqJVvM
zy*?(~7Un(X(&qW$RNU*mxeUi|#~4vi$a*vC2H@gIyV5Uw`{Ma8NOyQ&x^qpF3!?X)
zcA838s4Xbnia?IC=KB5vS<FOs*Uyc>ed#;?AflddTZDYcrfVG@9JdrM=<Qxml$Gl2
zpSHd|uw2<?J7@2DMu7{tv!K$b9)D+Ue|?W77R}x)&Fsk3*owYTvUHeQIysnmsEC85
zLdZ`zetpqCG(B<I;!RE7b&kZ?GE_41EtY=~ZY8_ejBw@p?m5j0EOC(>GD*khU+7H}
z26d~Zrc#VpLubl^;KNR9?Bnd=elks`fOlfyZ?2tI<o+-Q4*8SmZ^OE~Ygac8P3-53
zozYd(_l*NDSWn5uRIqtXu)A@rQJdh?Qaj?wG9LpX)`d8#kFIHs@0s1*2x=1>O9$6B
zCm)^&;>ePZHS{^EkIqiU6MsCidv<pJ&gso-_C--+JD<4$SouBAKE?;ALVa&XU;N90
zYf4y#j?HrG95<J)F=>LJee$v47wdy1$!Fi`=rcJj+Kj81+Za`=ny%HYQzv3F^O3?J
zs8N>ce3;h9Rc6aXHrMWi<aJV#s~=30SN>b%qBWbPR*u%tVAeYg=Xd37FCglr_T0%=
JHk>Og{6D(NHrN0F

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qpf
deleted file mode 100644
index a0bc9d80..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 21:51:58  January 08, 2018
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "21:51:58  January 08, 2018"
-
-# Revisions
-
-PROJECT_REVISION = "Uniwars"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qsf
deleted file mode 100644
index a25c482a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.qsf	
+++ /dev/null
@@ -1,190 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 18:12:35  November 17, 2017
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Uniwars_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY Uniwars
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ----------------------
-# start ENTITY(Uniwars)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(Uniwars)
-# --------------------
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Uniwars.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.srf
deleted file mode 100644
index 14cddd5e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/Uniwars.srf	
+++ /dev/null
@@ -1,54 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/Uniwars.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/Uniwars.sv
deleted file mode 100644
index 6b534bfd..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/Uniwars.sv	
+++ /dev/null
@@ -1,193 +0,0 @@
-//============================================================================
-//  Arcade: Catacomb
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module Uniwars
-(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"Uniwars;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian catacomb(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,  btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/galaxian.vhd
deleted file mode 100644
index 138d85cb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,448 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-	signal gfx_bank           : std_logic;
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		I_BANK        => gfx_bank,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
--- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
-					when "010" => gfx_bank  <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 5a4d0094..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 01cee00a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,74 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN1    & I_COIN2;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000000";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_video.vhd
deleted file mode 100644
index ec46308a..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,433 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-		I_BANK        : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1H VID-Rom
-	k_rom : entity work.GALAXIAN_1H 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => I_BANK & W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
-	-- 1K VID-Rom
-	h_rom : entity work.GALAXIAN_1K
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => I_BANK & W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-	-----------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Uniwars_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/README.txt
deleted file mode 100644
index d9a15ff7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/README.txt	
+++ /dev/null
@@ -1,23 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: Victory port to MiST by Gehstock
--- 10 Mai 2019
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   F2         : Coin + Start 2 players
---   F1         : Coin + Start 1 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Release/Victory.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Release/Victory.rbf
deleted file mode 100644
index 7a0e9b1de5261b3cf0f61e36fb10782a868881b0..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 305269
zcmeFa4}28YbuWHr87E_xB)j9adcCG(c39J4{SRcCr|{BvXLbZ5A=^Mmq9*y&g80)q
zZt}x+()axO=Xvhzl^BTy1W{78O_N1d5;bva?7FYCuYH!VT+4~`j9tHeXnyUBar|1|
zpVkX;Tavi(`<_`1tc3o;(uV^Fv@>)6o_p@O=bm%!ncX+voEz@_=Lo*{!|(m@hd(%R
z>eL%=yzwt@{@~ObZ@&4%AAbM)|MLAePQ7vJ)Q^7fgCD%MVeW>0>~k5w2h?Bb{xX~!
z1=LBXuN|kI&z0KK0QJ}UKBnKteZ}bofD4Gz=}OOw1!|`r;`V2|#{I?lRG0dU)9Jcc
z9H@Lf4s;*4Kif6#FV3er)J~j!uGhG|g<j)+;_`$CLA(az^!cu{m8bL=rnf=qls5eu
z0Nw_mYXU%J2q(G{P}+2;<(&DX{J3nK8mGn2@wGmk`X!pgd32?Gg7|&}K=%$HPN(M>
zD2;%gYj?H#I6uDD=hffG`E;f97^k>QVG`nex)Lt!fH*I{Qaat!HHJ9P1H|`qrFN)~
zs{pjN2`DWFqRUbMmFWXeoeqEmP&(z)Gx70UupU79t&>3Q#9#xKOoB2EQUFToo`g7?
z>O2G337{;(XM7U=98iB>{~V{s*BFN)fZD9*KcWHU(=`du0W@9$N{gYEQu`!4=q|p}
znCYIblukhRlokV}#dyU1#p@#;Z`@aWr8>kTgjX66*Qb1%L#j_{-vGosFbbfwdZ4rz
z;&dt>-^cyYm3SbA7_WE?lpl|S+N1s}fDkYNco7iyGu!oLK%5u%PuDJhF$vTU0pUSc
zN~Y^0fHEKpAl#_Va{x-;1E4&5{_9Dg`xxRhy8d@S{qv@2&<`M*6A(Yt?vhEufq>Qo
z0j0<Epfwk-FQNxM6HVw!K=+-KP)n($eH(BTKv~n!*hKBu_fOA6yY~SI4|<N_3zI<U
z#2Z9Y;{SN=dI0fym}{-PGzoE8YA42P3xN8Iaf+`o4s?z2pnDFu4?s;49>V~-Qrnak
z_py*G_5A>V@S%Ap-lINdgJqKt=hGNI23QWDEW(qXi9blT5!Bz;QaU>RVG`mz>VJD3
zG*5yFpj*nK`xt(I66iS(pzBuvM2C8)rwygQ3W)QGJ_CUGnXa^c2?!sWbAou?(v@(b
z`Jw*kO6!AAp*-SKs!M!8xWq6QU(7Z~)PFrte*`s*YM-@~+UI|n1bT|;MI<KNVu)#8
ze<k|Y1Lf5}*W*C<H19Lv5U1@1P=7IQ#9KcC#5mBEp67#lIYRgGT8Xc5f3scV{^ESX
zoyHcY6S)WnN{eAWoG3r;Kfcl)8?S}ww4uI9b`sD%$&Zf%{tiIAM*A;ai6>)teG=%I
zZsYX$N^7hHp!VW4TDSE;dG$bJuYay#bOtBFoA8L?tCK*_gd_1Ntt0A>u1^36H@c63
z(nu!7uzCg{no(add<j7EB7Ua*D8_B3>+^uU0OC)|r~N5Tqx2^M)F#oGbP|GF0as50
zN{fNA2nPbfgY*HyllG3mNr?Ah+G_|XuXb1a{NIx>J&o`n`1B;KsDrrw`YYj25T_9y
z#QPC)_#mF8=NRhO=}h<J{CEvO^B)7@Q-{Wkw~tN&;XwrmeQJl22|uEJeSa}NbgfUH
zejnoyi+Q4Jtb>sJjDh4T0qJN2lupmISA7W3Gznh>&@<^BblnOd9Oz2$K>%GTjezhW
z{V~Ra=u7wU+K7ok&m_O-O8OAVGy+=d*8)h_{cnI+ucqtMbHH>N|F-~2i}8rB)L%Ws
zxW#x8-G2{2Wnx;<{zG&ip!*o;ndnk~oqiwl711FES_843Mq{VGVmv61o@-j#(xpVB
zl>kbkJ(%Ph0nICkkQ)J%M`^zaAibpxK>4Jr5iKc=bhLP_Q8`NA45-J6`X-?DN>|FG
zE45ERv>~8-(jDna{d|2A=>B&BbR}DibbGpzp7>h;x{uT7IR@gn7>EaBpuP!WJV@Np
zb4=6ec+mK$?-*jdNM?|IOxInL@J+yPPePnVvg`wsKs5L)fUYr67TpsL1hh{O5WcmP
zT3S4JL@T<FucVjJ{SLq_0Lr@^Kxy%wc{70aa{^k!q-PKh%mr~>q6hH-@e=Vq?Hjbe
z5YY2{Kzk-ZT#niySr)?|0AhJXS4xl94P9wW1ayA`fUZ9cAYLILJm^YmnXV)!D2=Z4
zOhEUP76YZxybusRG)B^&V|$#g@%+ST?*hCV5U10;-36dD0@}amndBAe(FAn=^MKk@
z?XzCC(%e!1^$_<*IK>dB(UtlkpnJlJ#_$&a;;R_wc{&`K1}^~Wlj?Dxd*Z#gf4WkC
z1awa_jQERWE6ExHTK9hgptKn1c|IT-)dQ_rTAMLYe=`A27T%z>SD#0^1i?&cl>VJb
zp!>x@eS4ShFH_($1uj!yp%ftbNAh$^d4Gz#c}ms{59w)XPktfN?&?zAy8A`mKEHSA
zB5TZEy!zqI(=rQFe8$r<=YFidF-5k|U3k9ShpxF|z9I|GKYNr5u6lOC#v{hzA111M
zX$zmph*f-iIt)266cV_z8IqE!pU_#vKn0WPQDq}kQ8`Q|U`n|;X0k^gN<>xS`q9;8
zMgsM5pOh*?BS~s?3iNM5kr<4uQilS2ertm3jI~n(H#zI~WziYC2AH}w%LiFylUs2a
zO0>$HT1g@GdTJ_{#Yd~kd@8^!GouvJFPXVvlj(X__6C<_vI?tw5Dn{n;q`Kbspw&F
zeIlP=g{`@41%0%t2S0u#8bJ{c7v`j><JuxK6z0=VP6G{zn3zap1PalNv3`d>sd8wj
zs2t>c6tlB_;^qJP6O`2uI6pqC8v|ieb*3-P^T4t3OnV;4)K~rSL<~$h1#U@SEW&IW
zX4Sh>QxH9`hquC9M#AsBM!6$@)p^yguY7(2qrN5FzZJ+o4dul@zJ)1Pzmv{0@M`#1
z^ORUb_P;J){68F}p)G<ca}`ZjUwL+}{Ke({>(YM_xLwSM1&bKRoJ9*K{`!~ZEU>6d
zknG~cEL_x3<|v$e;rD4N>Au2JCX5o88LL#bT8_%7k^!S2nRP^h<s4G1i&{r*<t@5G
z^;h@IfyN@U8qLlPo9O%gfQ*;Mz{S4*LHrlM7&U`yk}b%LJ)guUzy2-|56s9S0~xHy
zCOPqZ6RZFE2efHih^AMcFkWbW!XDD~n~K-vO!{2g+;OVMxh~!Ou~R#@-<uulzRMbF
z(r<d^qc`TWDEst~zFh8Tp*mBq<}3E8o{P7-c?7tdhvg1yIA_ub+b18c`{#!3$gKKP
zUvJC;qE;X&8YU~*zhoMUSi>5-*d;|{2HI$$-x#dW$|ZwXqqfO{a?2Mlq+|O$X7-Yq
z%k!Yo)T)i5Smd4hR1}6YwS#kg0%8qe*vLy??fCHG&V}Z}I`#K`$Zni&J&Q74P^#<i
zm<x}^<uz)esaM*u8ZtR(>(Y`Y=c!=NSpBlreOc?iD7Ees7B@?t_%~l&oTQqibaaYX
zy|+<Y3^uIl*Y?lS*Eu9NTE3nG3Nu%kg4pzUhncHPPd!ts`h`E6o_P+>1^68R)i=I-
z4wYxAauE)55>sH-IP?17{Pry4KZoQgBs+)t^;IqzBeqd`4`bhXtfA+VjpMP4ax;mT
zEpp*paLt>sC;zVIC$H!5bG>i$%4pa;Us8u>7s7K4r!+Cej7s@=CPJqtL35t1%v8N_
z;Hk_0?gsk1)6f6e+ZH4m&W_-lq1tQje`muS-jj!eGxTx}NsE<Yxw-nNK0G{E_Tusy
zr^P_cee{~kp3VPP<gfXa7T5b6r5mYsUs7A;95h`-)?x+5oK0gc8>V+(jx(8))H7uk
zl+<kx<1qiN6=(tn`n~&R8qT?;U6v<{rdw@me(R~;80ZB;`m*Z%&x_`wSt~ShS0Hc9
zkB8<xE4e76wj$>&vf#`{@9+!mc)o&{5u1-f)AJimv4;7m*kynB^tqbnxzSTOPj?H?
zzL*hf9KXVM?l;VLeB@DjJ#CiwkOoGeToTdUmjg}C*PVPp15HSf%;c{=&&0xsUs-oq
z>293TT{!XieHWp$BzJT2#H0U<xTrDEC`~zX`~T9<HU=qbrBR4cTNm@5O!zehE*Xk7
z%13%>ZIu@#lQmApF8F|QA#{MixOg#ZoZ|hj6ykk}1e#n*M*Icx8`Ijn0NOFTaB(K=
z>UTviR7P)1+NMeGSgv>q?;bv3XP@eR$ofi?{;^Zt=Dpb$9{5wdP>Hg5yYg5R$(@^i
zHEXX~UZmB{1mQmAh05B)<M&5FJPVPl^OtFGv|!_8Wz9)3{{R+J;>TVejowB&@|TSX
z{EWh~KQ%U;umy4&Wv8bu==qQSWkJOjROkY0-4P|vZIln)oLJBZ7E<WPo?{~-T;RD}
z2%%>#a~ZLj=`wrjMNY9x)Y%<LvmMtqEcmdXe5$dbFS9e$B6BW)z<lfJ+@RS7Li)0=
zyK%nmi`LbeJn^Bkw7x|y!@A-Z`HoPB>3Q5<0I_o(*wj_Mj948p7IaG#yX@&+5UJuq
z7c-Mxy#C~i7qiBBZ!UYfvHdk{qA#iUL@tm9OET-N<?6otO672_kzXNLcVc<|-vZ9=
z`kz<6RRX)+c)wo!^}gd5%daC$!~L>#F^wSeK3)nGyQKV6^UnB!3S6{0e0s;V7w6X|
zQ>@~GNV}jyja-(g9npK{m#DLw$lXY8P9JHyI2rIlI1n$8YK$p)Yw7cs1H17p-q$tG
z*?o};ON37+?|*b*->@>T7^hh5*Y3S^WW~G$Sx|vSZhVat`xipGE{GuW7P?p|c1dlN
z^Ul(O3S6vHd69~1(Db4;2clC`Im`Q$qM*(ELS<4r$0|GazH>nwwva-N7Ml%ocwaK1
z-C%;Vz0%;B8MNj_7QHL0EV9N~Ccx}?pz)qYAUR`~)w_;&*?*58&AFNHv_FOG$_M#N
z?|H)hcxiVO=e@18I|}q}I@(E*-rL0Q(J$!W5`}t?o!Wyc6zWaaoB7^a?Dxu3Jo;^&
zw_qbqJN+QgYtYMUqjB0#%5OJrsa@n>%eoLbwtzAhcEhEWc8*Y8_3Am+oT1u<9pwxi
zE;Q*fVhg2ITn-d#+#0|9btf@d7kF*7X0*U==P!0KBi1;6ZS>cjK$DsA>%Gre3x`wl
ztY5~Abo~?mbbS6vTxf|#OU*`wx3Np*7cIdz=dX#+tmIy!U(m+8LNM8kJ)iB5U!<Mz
zX7@XrUV8r%_A9~tkzT$%h}878?>Xw>#~-gtzXy6be&2GN*d6`AWz*4Lp*Jy`j;@P-
z;j;YN<S$&(^_Ad6O)cLZ)b#YXU?b4WBWuHHuZ;%JcaFTHVN0#izvtkCr5gj6-_T^t
zT@)#+#fRrAZ_kx^R$leXKYv!*IVUuFr#WXtrdPa}5i=ULlrHP%)8~Dj=SHi+7p=H%
z9FJYpejcbGGe)gk_MgwQ5N6K4bOOc~sk<&hBYx{T(9^H=CN68}XAF)Dtf8O#FF(xm
z+dT)jzKcw^hQQ)~s%NfmzS!}`+h@UQaawTH$U{5cHA`cQPj0j_uy_n+sc{*xSqL+0
z@@0z6N}5?RE>mn4!pxd{0VuWzwPG<v-~G$8N!(cnH*3ZP81<}uEh^*34zcOGdhPkm
z4=alzOI&#RjvPH#AG#*aKmY6eE*5ebFA(nfiz#11mOL*P$z8iHzkRkqx=$9He=Zl^
zUZWRg!(17cj&-~6$(pBRqvx_={<3p7o@N>`*#F|itf6LI;qr+#@pPkR`_lPpaxl*2
zBW=izRVrhn<UPb+;lvlM%OR(A5wsUL<h1Ua7-~{n%p}Ygns(dIE@`M}U1-1amYZ?Y
zrS*3%P;Ea{SB)5VDlG6TEnt2URC}MU-OTt|NUO|Fsx~WNkt_(l^YC1ny6rNw1`O@_
z8Z#y>jYs#)K_+13Mhz`+%<QiJIG+JCFJfm9fAjyF<F&zsViY%b*O%vfn`4sxwb90P
zX1!KVeRq~TLW|~rvN01j&F=h@!K$D6t66tgphoT0+N8_;NT#drzH1f)(GYm94kp{J
zOF8Sd`U^iiD{Y1Z;FVP8Z|-2<6*E+xl4M8I;m+R{)>q%G!5I-gwRUm4FvffIp((_v
z!>U#v4FO!N+XYVS;qC=mW0M?M*W+2Yg~wi;Yk8rC$w4k~tY2I*i&j@qF+jKAx@tki
zi1AT_BvQ`8YFa|!#NlsGONt+ps7;ef=z)YTnze2G$6t-Ealx6czxaKB7D*LT4lTR(
zng262QlFN3(|Z^8h`Ga6Ke#rRwp!Ifv)k`r;RH}*T2*0>GrKjXbZmBK2~JfwOJ*IB
zU^%DXVXUZiXsi|jd*`psG76F#n_T9iGgrj|XsuCt@=}lZ^!w_vZ%$8&pIbq3G`JP*
z5`|l7dD^Y&CiD^)nf3aeU!FBCK8Y4c5<$KJXLLZV&EI4}d46ElZ%D53EE=VT=mA~K
z3(p^#RjNnSL>n=8ECfMTec{>J`UELys7cTg6r9A8o?7uYA5{P79#ThUjR@V8wrHMS
zS|807n1vNUC?EXAkTX?>o;ldGI`sKDdnj}#u*mFB(8?Z_B)lZrU4)N($F>E$iRP}V
zwGUn{aIl4MtE_-!z-Se)Xk4?Ap>X2o*IYIY&fPS?ypl)-nHLI$7an=XLd#OQ>F)Na
zb#J@(9pTiJGfyt0e!NKH>zUjc?@~|Nvz}WgYXWD+dQ%f8m2k#(IN-Zk;EaqoBP&>L
zmcmhT^?8RGiNFjkme&lhw>ej7<dIl|OoKWY{ll}v@Xuz3YDCh`!57G<3W{BL{p%)^
zdTQlMf!d!kbL%Gt3S*{Im8o)~-zj?gtW{TxN>SDAj;jh*>X>tMvRrs&`jck*^;)?g
z-Mjxo_Kf8g+TP6N4(j8>K<{Ph_O^dqssq!nq!U%)mA-rZJ(4XO`%3Zpqv_s6HSnJD
z#;me>#CflNM1RTqM9|ExId1<}rf?{`mapI5ZDzKoKH1{-9p0CB_#1&+^u&JWh_^4)
z#Z9dpE!H}vyf1aLJm4G=%Ff*O7I$FxkW)O)MZ*4+SM22FEdlHJlyGj^{M=74{hH$r
zZ`ZE9JGeu4boUD{Soxok%dV7dkN2z{?ncA?{5dPN?;{^;)2ycK;qvc!){dK|9G}cH
ze{*No%uhOjiLI(L<qKOS@z?lNtzDieP`jH}vHI<QH@(D}=NgyNCug=>$Fq|~e1&dK
zvp)6`g;hVW`Ah>-?+WQine9e<)Rqoaf!K8_Ov8^dtIe-YmXTA-;t378QDTJMLaYMD
z?s#&t8F5x~Qxc%!O?jU2q59?5W=yBV1yr9}x4L6Cjh4#U(dx!!f$;Kwm{kWtOQcuT
zrj$MxfNC|oiv=@xP1A^0qJ~^3-=u%n+Mc<5Efrc?2_kJqhz1$i1T$vOnD|q#%$Q7x
zaZ3f#ONo;6W5*u)a>U*<v`M6kST~{?O-s#=oS|ra(%w(bDhZ%4MeY<DHWnH^)YqKt
ze#bw~=A((nR~soBLzDB*@snSD=PWZEV}O<>*X;b3RN=&b8;|SFbgdUD3mNW1+pd}&
zJG<bfBij*9ha~PWT9}pYR2RfdSQJit;(?jckw#W1W`-<CY7x=}pOMkDkcO-88=KXT
zBo%7%KV~St#my|3)RI%Uq;7dynb(-S<}*20=&qV8x&satBdkdn5Xnw=9LA2`pI*E*
zx#N~u<5pm!5NAQ*sI9IA*nBjQ>L*{Qjq2=A7*mt74s%GYBVm5#WqXING-gr0A`=gc
zOKe7e3o)gzn>{o!+xm)@0j$!R<l6*yK-9(AW0{(A->=QC2xH0C28qT%(}j)su3wx(
z#uLj%!$s2zSzwrypZ?(7#+^vGn2Vb*K`yK;I4V#)sdBWwK=bjwXWuSClR4}`qC@Q{
z2d!?BXrA<p1vX#($v5VFPqN^O1c)+eosthnq8H!B%3Ej;cW=3DJ)Vd47;`zTpm<xJ
zx=5x!eW_zMEg>$6DO@PP*FU@UNRD(HEH}Byk>FoCzu-yz-fgq=PHTyDq0?Yf+w(y6
znJ>>;0=qbN@}*Fcu}UIUVFtDQtlCfhQ=NrN3N|gMNpQO&6+y2(k~oXN*yc<o)pWzU
z8c}}rV|9Li8s=#@V-C1AS$jI?bc3f;PT!0!JADiH<(YfjxvSG8WhW~~!=`*76t_3i
z?C-fgItHeaf<9u1AJEQZ^?0X=OPqZ*z<zg}I^Evc1s0id@ZT<>8Zj!TYoEm%k!E>1
zd$yY|rBClEXEkY~5{7zaPG)PQmQEvm^p9uNQqNRIo7nFc!h3svbIxzkJfr9ms`Ej*
z`u%(7D^tslwCVYZzWn6u2Sf#~)k!CecYgS}Ib6i^*PdG9_J5lCJmo1ORShNV#tVSk
ze*ZL!oK-qnyd+m9r(z+Ky5n=R>qSuqB-$q@^t4DhtLHc&eOEX;dXu6!Vq>uK0w$t*
zqBm~&>}#~f$V~uy0X$4cLO2^byWG^2!ilf{<J6QhPrxW<wuoVH#xzOEGi7GDtL_?^
zAvH<@dXWf><^%(e%!Anq$LYxvnVT3!H}^Z2_rosO@?0wngES0-=$HwgcqKFG=9D&D
zo#iYE!giMLM)`;L#|TWnLVtaFDIMI{(WXT-o?q0WQ1$+S=}pDYXtG<Q11947nz6K?
zCLewO)GZ}$4_6#fh0#G6u>+}t3xb03U$@U*5W@yj0L6tEEm1SoUwdNq=3oodMj5Rn
ze9VvJ>REX!I_;u^G&)O)#=M{g*<J5hB7x!@YCE<337lNnunRCz5G%Ipr$E((>eYR>
zktiZXW40RIu)YV@1C0)j$%19z!ty{@0^8R7=RWMsRaebB1_Y6Tu|{QN8O%4}sS#(#
z#@~MV70vlx(VU&lPv?L!7XXD5?|XFt#ikaSuEkQW4_3;t>R&!TwP^H2>_R&a)(BQ~
z1k<+1TrIWkvzC%Pk^Sqs#Q3(>;1t2&#(8I73AIVM<#*#9H~KC2I61nKJcwiiuG3^g
zHYyM+%Jfh>TT7n&oqbr$0>f7@K#f)&aMS6dz&-A1Oy`m#pEK9b3Pn#!gc?Bdq6wG8
zK${W;G$72v1(s+9|2btCN^`Bh`#yUG8Z6Ma;xeK0f~AyG_Xs_S#&OSdiACny9y!%C
z>VgQ(DpVJp*mlRh^k^FAR%2;HF>KXH$y9Eet?Q#{%h%JuhNDYg(RCeHL$Um<q8o|Z
zo`$xY)CBFI1xqNRR}oUsNO6ROf<j2?r#zLn*=bMHeW65N@Ryw|`lo(fyD2@Mc6G+v
zgiz2Z*Rh2)Nud-)!m?d%P%=71{}>*+)OAB)cmB_}8#a+q=Xz79pcADF+p4ed5*j9=
zf)2^Ge9RS_JjS`J!>r*(N-d%>=nFO|-J}*A6+@-+9CS>|H96O$CuS^R5s9J>{X}&O
zVv!1igaPl3+D~dIk1->8DX{QujlO3=cR8j7XX6+SHH^6;MnPKihr&4pgSJo&X$ENE
zV`O-EW&hj#RINFhKV%AOI^q*t(T0n`M}YcK0+4|yMh?J^8c9T_RE8NL7<Iz-_C#!q
zY@G>TDTK(w1QHPTNzYZ$7e$WI1r0@vt)D&-Mkips1bs#jl>*P0?9uO`WnyE4DpF&<
z(wo8rFw8!{=C+{5aFP{0MxW7?Q#L9=af&=m$y|cQizb<$(2XS~?yTxRE@J`J!^{}M
zMzg@5x*6qBr%4wp2BN{HnxHgVC%Rx9=&nW-PI&t%mC^x*qFc<e`~>ywJIYu8hJhJr
z;?bb5lodh50a8NX9F$fkW-wGRpF}QBX9TW_s%}A|mP=v@PZ(j;-=qdgTtr-o(V(O1
zp-;0Y!Ow!N*=id2YTks%q%6(46o!qZNi!HJ@5vnMvLZg{;Eu)vM;{p4UlM(Soodaa
zPz0utU~hgAo(7-lNlK$02ziVGiT!wl7>TAd>V`Us#Rp0zRkYwIY~11oc>6(u`(}_Z
zO<Dl#*Ox^NVv-HTNP#cWC`YT3@Q?yMLL}_t0{l+CXtV&JD=mEDCAv2fe#Ac38RRV#
zGZg>iqkn=+G@W!^&7}{5M*|`3g)F!oH`>~08jBA3Xj&?WCxb2u9faB@9h$m~`l&Gh
z9-^X@+FW%WF)XD7;@2oANp@kPv8d@E<~o`b9g?xh9ju8xv|MYVHXbl=GKb;S0GWBP
zgHOGJU72ao@E-WfD`>`v6qF^I-p>n>NT+2%LdnMJz|>FfBvBV2Pg69<lmkj(nlSB?
z<B7;lhr0|5`0ar~!rIU7<9;?Pvbai}m$nHmd&hXm9^``eX4mlY7>6JfvSc6iQrw+L
zyW<^*XG`-APz^1?xrWF;74*Xgj%w(Hg-)q3p8YwjQXP8$0Fwj4=tf{Fre#^WpRm9Z
zX2QJvM_586vLH=MSs}71j@^Zel1L45y;teALr@y>F{KHii;m4+@qRAXq<hz-v68Tr
z(6&x}Q&eCR^?$c*>$IH}Q(*TZ#%MFMn6SGXqP=Y_(P=K5Enl%nCZtRQSeSo*XGJhh
zJf6jFk<xe*pZcfEQS1Sb|GcTQ!`~)ER1l3*tI))wur_GpAW9VAhCV<ZKLLS>bAYr;
z6N{-O8Havr|F1py%~h3@d|4dB&U_?P^yU0>)+?z4Sy4&t&1TgbHt&Uy%A6?k?g^RH
z4)Oyjwwv!o;qD1uNp*LAYlD;S-4gm^y3@ZUqp-lY6t*j+w`!TqZYxZ|&2C1yW^JxX
zBwB}4O%J$el2uasN5QjxGuLI_1Z|JFir$<un+{}|-ejsbd|YSw#|M;-KB43vw;oPO
zmQgY%f9C)9mDNxsx;6hXu2fPxg*1Rq<^*=oO`$}3B~{Qe;8wa5u<*LI4CWPRWfUJJ
zv7Rd_IuFUD((*tGQV6JEE-?8PRuKMgat*>Ex?g8170?Nnyr~#NDQ4Z$wj=`#cBRm;
z0Te(A&?&Pyocxg8TCy`FoObiwP!-Vq=CF0?rVxCOj?Q3FO{b%{yh^Hd5)s&DSYr^}
zCg&CW!K9K0u-QTr;w--cqs7eW{?H0mS;Ndn$FAf-7X;O&&_5<NqkT|_(CF?A8UBpT
zAx6)d28l30HcE>KK{Bk8(p^HQRm~{iRC>lSR)$CkjU@ihY+o#ye4_p{N~M__!GTo8
zG&6Sg<j;S^S6&vVg!;=NAZ$%1viE{rQc#HKKBEvVq-4FD$6MtZE)B(v78*@SM@l_I
zhNPNFZH1MG`LRK)(R9W1m3)HR6uFouG3V3Ax+S0uGxLz)#>p>&p#_aE6LACP0>fsQ
za4Nb9#K3gY;QcH(k&H1c1J}mDaSMGZI$Z?WU2GRRcp^DWtYGI&J3Vabq=8^xjaDis
zw1$BPi25eRbh7xcuiVFv3uP0?T;;r5(}@@DPIOA+$97AC6Z!(S7}=_dRuA2|28>uR
z;$vxBec6s!F^TcIF2^*06SiVfTHRq#%|DS&yZHbGhfTf_6xrnRbrA=nD5eDD%MYbE
zi>B;A%0F2y7PL)aNx=$cJ4Hc!nse<)m>P6Qo^)uKR@Ou+7wOgMOo9$A?N8O>Ksz-3
zPJ1)DUe198nvbTs^*}abt7zZ-6xJ`ur=yiM=~g+E+A!8SY-a8!#mWY;(-~q8z2Cv8
zSw}bos%LD>J+pRfftB3kY5kZOn|oqANTl>T;O9yTy@Egn&8eQ;y0rzj{f>^EbWB1s
zXS|$(VvWC6R|<3yC^od`n_QI8^$w0SV+_0qR<*HAvV{X#TCx33UMLk5(6DCxj|(gv
z<Hh$~^?9hTG;+Nlmar}%R;f+cxsG}o?jc4=eJK-t(v~i;#W_H%F6^_gHEj{^#P5Vz
z1r0k1$6i<GT!@6J^vy)!#Q2XEd#HC;dFF3GZJYKDs2i`VeFJLyZ@-1UMs<eoSGsMV
z8i2;9K}L6^XcsiwZSC~1jV2LqfeUua)A!isv9Cuu-|4EPOHPIKfBx*$1UzBB>VP^T
z&RYmnzj%YMp)f=ku(K4XxUiB09(2e%CZSR%myQ!NK*xnj1^WVehz&6Zyn%hBpMdwE
zMf;*TT_6!;>87C=Sdo!FLW0dt7^xF~19ud(K`c^+BtZy9{os+25jqB48SU335|%G+
zY|@JDNfMwpO9u)J%OVkpOJq_3Z1?QWH|X3BZIj-HR4CBYToUUbg#L@swT|d)EFK2R
zjsxX_gi@*&qLCR2R4K^B4#h_O$e4usL5)-(BW;KcpjQ3!e`3ZJ1&w22t${sBmLp7P
zA<GIjDA11-cl0J*XkuM9x=m`Zru~G8)g7V<5Ga|}0++RAvAEHCi`lk9DdfTfI`5Y#
zrH?{<z*dINU~wa1G6MyL#=rFJJ85_k6s$3fKids4sglir=?g$DX!8((tJ4zAy1XAo
zGlnk`rY}-5tNPi}5-VUvXlurj)nP<65>XhepP-AM%?jKYCyu|#{3}35*im2y#xY2K
z2kD8ro`gtYW&F5GD18Nk<m`x4`k{Z96c?Io8Z)H3fu2cNtO>mA3e&R9u&C(!b>Tze
zn%j#Ifnj#Z>a+=80JK%cE&5};l7)l7LW|WN0U=i2CeW|DnwQ47EO;>IBrpFgmr$UY
z=*z*U@F7ntX{<@rZJ-9Z2L1r6faG08eVk_;bu@=DEpcDA6K$r_loO^xd~1lIteIE3
z+F5An&`Uu`1tG&|kaJV7WSfm8{!o^^`+s0rWHIN)8qP;OP)WWl@vJj1;J*3|#emQy
zGX&~)+ZybHGUDvEgbjle+*8rv(*+qYsDj$eB-%EaA1F1!5KS?<G$P-Kk*GfYJj3jf
zA)Bmu4h)Zj_6DXc#Wn0P0*V5;Nib6p7*L>F(2NgbF%61>k_4kUe~AyLhGJQSJ{Df0
zlBER#Vh4(K+k38J5{;lWbR|JG>_y2Do0d%k(70#?7GN#c5->hmYgiG6qoOnBTFAgM
z#0A|)f4~CzJ(L*s=qG-H`9k%OAuv(6VsB*5a<7ylQf4tv<o1CMOriw!QmS6jrN4w(
zwrx0Jf|(_yg|c9+8A}WiXk88_$t05k^)XxKfh<NubrtK;o8Mu0nx7i%gg61O`dI~Q
z0o_O%kY4a6V9r5fh*l1;<s4(jDlMqc={Uz~(1P$QYQ{7*I566*D+3n_S%B1yXb@Ua
z*2qSbH4-ov4fAle`UYORE3|kNB%aMF(iz3N*IB!`!cUE)Aq7}Fy6X}yhrQ&Fr3)}Y
zVX#0Ov+d&HoZYcMt=o9rS{RnHI`k7kUStzkFBp$$`$`{{gaO7A0b0S-7`XTXN<{Ss
zpCCtppGzO|Y)dWWaw;$std!Q0nq%a0xwV~<6fJ0?7ZoBf_T|X@9?b!H#`<6kH;?85
z;>y0F+?O_lGi=!w_{Rn@qp74hF?DjauwU$E0<HsUNI<rb6oV5=^+CGYtb>nS5xqMG
z9J2|33>-(}(D!Gol%?5rfGr|0fJ~qVJY*Hi+HYY+Vu(<X&=bs8RKp5nul)!I>4XCM
z0%eIAVGv`&`U!u?b7(MdCPZbLR8VIL^<<4&yN8PjW^vL^P~A5*+=Q&TfXP9-U>t)8
zX%bc-W}^B}Eno$Qq%tEufar#%BvcFq(nw$zDtI2;gUkjGVQoezAqWuu8rP&J38rH~
zz`=?BRV}_^HdnIbtb+W4-^Bt3kPs#~pSbh+_hMAZL2uLpn|Qt)@C3TXqR<^bH|BME
zo`*+SP`g!Ef>(61?P1iz>WB1#^k`B$60WNU#+CYNIhy9haE&xKqNhOliW*d`z*sY2
za20|Dq6l&xBPMPlt|^>&@5d+mTJ0ICtfaeO-7>?)+IKJ#1Jj80q1Hr-&dGl)QGsJ|
zlG<svX+{`|D??_6B%Z@c;A0;Owa^Yxj7S<$$70}J@XKqzdKDA>UT1m0!(x{?c|Atk
zn|oCZbV@iF#F+P?!OmUjEf59k4{^1V_x?<08LT12PP@3-le^RMDWyY<rMcT?uf^8Y
zsx|Ay6{2*^-k-*{;h1izG?>%<-wnj_T+3H-`*Z6K<wo?4S>9~r!>ig>?8^-mgFnex
z32QXBKac6lCNi|`W*{(h%Mgi-nO#vzSj|@YU!FBIcwoF;_WDrf2DtQ`-Y=)|A=DCt
zaPQsH>HQq<9q)8{um7^W#dAc-=G<DtZ|AF*mG><ZyVL#Y;u@@E-R{D_+j-l*T-#@J
z#lMiBO?PZBw(ZZY9M2U$Ykf0Y<Z7@dhXwxmSDk(7_sfoUwSsN%kJnnI6-&(gs+M7R
zYHW81+k<WlW%bNZ7IGB(Cp3YKxgvW&&ny0l?8y&)*4GL=%(=C{;dB!Z>4O|7mfQwX
z*FLf$H-6fO;@NPdc&##Pr=!0$>4MxgW?T7f_T-1@+AZ&ykO6l05i6e^lN+PYz9F*2
z^^6ss{us%c9q*Mb&9E|%1AimdF*Z&RI{Gu4l<Tt3msD6r<QZ@>>7$_--nyHAZp696
zhX2HC|KP}aZPn|X`?)o8r@UjlpYN2(k(BhvoL6?k*@Dt=%^VXSz_I&seS_ONumz4z
zEzI1%>|<{JaSo%gb?G{NtGg};U^p&s`LJiEGbhXCjbF<Y%|Dfg%&(?;?snGwfmCiD
z&fhw)F+`=u(l1DB=+=#cZCd`YwAVeHN}0<Jtf`pr!{i=s?pDmqtplTSolp+8tgyBG
zD=EeL(z92=PTa>Ut^{5fMYp9&QQ3-Zr88_FP8|tzYEw82!?9i6Dc}f6!geITO=k#d
zlYME!^8(A<%4BV82u5|@Ne{2sD>l1*a2y<O&o2qT_BB0oAlw+h`C;l$NX;z%u?&Yy
zyND0BXSkWX7LY1dOGYs*xF)U!M%W&i_0xwL+bK%fVK*7(u2(AVUXjv1LXLsQxUK1h
z5f=vgdJU$n=U_URB*M1BV5Rj<q8m1C<yM`oyIO^kP~}$ZXQaxzz2P<fNU&}w)$@ex
z8%i0$b`KW%Q?dj2FCTC*0u{8wz6l3G#e^Uqx>|?m#pA<~!$iryl6||O;YbH@0u_6w
zK+{-RUd>ZwsrPvn++&BloT|6WCpfvZK(zy@ZWQnCgn1qr`$z>rhD;DeVBD?hx(E1!
z@+DW}&rH}l5BJDse_|L*#O#=W?ft4ZV&eBFY&E~#3-b{9WTQh9iI9sBLk|^`rK`_<
z6g}(|-6O8Yye&djwqiEm&45QM^Fjz|@fa}cy&ry^jL3mYOG-h5lWUVZ$_2TR3@GVY
z2zT%e{gDHC-3e~lw@d#-7#2se2j%g0OKDx3%LnkKg&RY&`HShmeA&CwypIN8VLpM0
zF?1`GWM*bc@Nld^Q}A;bC!0#Zu6vL>*d90pbS4$%KpHq&jNw$p^}57fnWMY=c!&{#
z**4KElcdLSBk&>*hqdkl@M9oc!8BXd`&zVC%<6G(MCX;SVOop#c%W>eXE?O1zCmf>
z1?Ya+BeP4OYXu2^2-E66oWeN*IiN5D8KwHIpF&qzFdC~|Q?f&O1#7<o4nWP*C4(cz
zP(1Rdzy$@XXOy?9QLMO4IDxx{Qa*<2>+Z0=+u9g1{dup`wN}fJ-zQ&n`mi%M%hueG
zxxsTy{dVbA%sah7nNNU4X%gXsV<urj8+iWYueQP&503T~uM^%k`0c<p@K`v><E~~1
zT8`w*!Hj_>X{%eK_j7gES2{E(8)lPc6;zYMN4zuW;u-V)uoD~l!5*o!4d(JFWC8;#
zzeTpn;4uk2p$3`-0c85OW6DguBLs7G3GC}9*Z-N15qh40ULxQk@vrE23Q!u*6BJug
zEr5hxaJvt~5@4$&Hq$5yqmnHvzOKSWYl2(1TFF<PAkn|Rk_v9l>7&xJ;Pwfe_enEz
zI9;?7F2rjZ%PhfG;h62T!^V8~hpy^@%8UQl0HjzpoWoY2HgUMZlC%?a+$ilq&*>7L
z113g6IDyhFNe(Unz2Id6o*;)QBQZV%<Ey!gx9DMCkQIl5ujqwg%N&)^jLqd`+c+#)
zeoPiIdW_V{EB)JR@*fn#<2FI++jl;rP&5a;ISc(soIiUyatOWtw3R=0QT$}(2R?dJ
zgvkf4yMFE;&s_C{UH1!|-=FpioV7-_O#8{oE$t_lj~L*{(}2C9CXAyLoaB(-7WdHw
zo)uV-IQpIh@B!HBG=TX|!$Y^$J)BOR`38NS0eAAYh6Q*G$}yZMk6jh&d_5!#`V`cu
zfZ+<|IMNbf=m1~}*iu08N#dllEfqp(v+13mfi%=sN#TMBAHezlezHYjZWpi4nQL->
zbK1`ymX?w5vqFI-0oB=G5txV*=ubh>W>=s5$X}4Zg7zmes2C2SAV`3KL#}@$z`cS1
z2&qJdDd+t;prA4dHwR_HlZ`8^R9gonTQ!@FmT>|GB?X3~FO=pA<-!C;G3!Zw6>A!?
zd+7`c;+=XW6DMiWAvldvL<5B*C&^U|Ri|;%q*yK;$wAwP$ij;dZitu(){kN89f4_X
zbD%i~S=yw@0w97zoMOyrvUsXZ$1rt5cm<psqepZJWgCGbWvoiz4wo3tJCZHSHpwP6
z=}Cdm3-a8KnQcQ^+qTO~R`R>YDpv9EBk*%rZjjU}`w<)g<vg(LetA#|Q#^Jf9BUT5
z9k7MTy_C%Y9m2wZQ~&Yn>7*8q0zR<>2n-E{4&(LGK2K*31d0M<WR&Xxqy`}m3pi<A
z$@;B~CRX#&kRIVi*euaD7=~AHTuQB2g}ZGNa{!+L^bLSXl?w`cs8{6_&f&qn5=~bn
zVT;4$!f~f8+#{O?J@{;3k?TShQ(8%RPTL@!g6##h!Nugu!lATQ46Yu(aZma^+R9GP
z75Ps%dveLav~3j=V}>%A%n58=z5AEJJQ^?#WOq7llNx|%Kt_;#V!+mgdutTV`Y%1R
zG>y<2oViNOG}N*byaN?bo+Esx04Ix|l@hZLb{9-^+3<8g%^ibQC&yVaXpvT%5{M+v
zB}!|^@*B<REfryi?Hl!$X6*lvge_bz;!xd%1B#o1i{cV)CUXaLLqNY!m<}dfZt0fw
zr9WGeLXZ#69T_+@;&W`FdI6_OARaLvP=v9jU<A>IVlo^M(9Xh;Xebq^g~VP+5TKtA
zCl4kLna~Jefg;B=6zjEiEJbiy(#4jI1Auk~H9{;IsNm{hlxDP|qO)xYt}yIeOO6?i
zmK@IZqljWvvJeV-|1cbp9if25yJWR&(rgR8Q2B(b!>>hnKxcyqxZ_5Iuj30<fIm;d
zd6mpzsWaxQhKd@|H?2T4&<JS6tr(wX>mjh{#~k%bA7!Bz876EW2nkG_3kK9>GYX?c
zl!1kfsXg+&x9POJNFopz@NGH{-6#feAJ1q3qjd?!L$9Hqz(9Ph?J5@ffu)#bD}3+B
zatXUOV8#j)s^hca9xLSGPzcAxl~@Herw0b;C(taW>kBHbz|O-TIz{iKWx#cYz7=vQ
zu@Y%z3|<~cDGlr&m@CowJ%Jo=a+k7V!nQh;Hp|XoK8N7u%4P#|iOE<C(B;wm8wos`
zMvzF~HvmsIyaiIKzEp){sFC+-i?5VaBm<RR@C+6kW&wHzScN2FXfYE8zE!-}k^Ryw
z>Z%{y+YUKJg0>ADZTU6HN#m%=LEQO6C47R{IEDs-`oyOt1r3d+v98gsukj!-v`iR!
zp%w&q&f{YChL+HV%)I8qzA##Ha6hlk1^D^}6tDuF4Rv{45ElfsPa}b`R=55N=!Urx
z4*K&|4}9quQt@<upX<;e0^{WILD<;@hu;-6Ada#y2|&)6kj6b;(0f#d!Ie69D}n|W
z!jBnRyDVQD@jZ)p2)he0C8h(;r65sVu?P2Hek9ZR1L1>gsA}G5G<O(6D8hd3YatNu
zwQ`7MwOdx;n!~|?Xd0l?53Di`{$W%!VWP7zli&!8!Km?p|J3plVwdW=&tYUyXM)mw
z#ersuAybiPX_KQ}qescg32?gs70iI62z{i}x#Nxv*J?&vsli1-7*pIGDS_yi$`Jg<
zjrhn&cv*dw!HMLd6DZ6!3>(iyl1nohbP3Gcez-Er7UF+cz(N~~+MuqBT48_(bOvw2
z?ODk}IhV{v1^_-2EIS~ME)AtQz2nnZNg5auU2)QYu@gALgLH!=N8pTyIyFaXK@FO6
z5CN-0qf=TvYH3@@d%SzXJRE>HFMv948POMWgaHVRZ^FO?VSEM#X+XMRjtvEc*h8fy
zkW)E~k7vd`&rmuA-0yn3$PL>W+1;%m=yFS^hp7~ZtQj<VC&K=)S3DMqean`IA_xn7
z5bi2-ByW9N9^xZ<c~y`f3X)-%y(dIrH^1t!bjv_TcBBML$$Wf&(B>T)eyqj%ZaBm<
zEo;M;!KN?^Z5TMg4IL5QG%XWOnU$MAh8gvGWlrY0rCjSll6Hb1I*vzlr&kW!zS!3Z
z+rZmJ>xWpXZ(rztLhMQR9S}{Sr?q(;*p1yBntf)X)cb9D0En&(2gBZbzOg}U5bksL
zI@s^c=HiO4S<7=kkcXz(6o&t{rDeG_k_i&UAhndJ78x6PL{rcn2mIjOeE+}0mXQ@X
z)gMm7%?JwsQbLCv5d9f)n@#sN5Yt0)`B)(wN3{<U+vS$ff>g9_=DP$ow3UOnUwPDP
zfeN@Ajv-U0&)7)>x6c7ls`-ar2@Z%LV+QY)uq<%kjClbb3a!6{za3rzlU;lAS5`ti
z%e~@&OJO*j@^d5Wn+{}!r+2UO4(dO{ce(BAH?Q60c07{mO^vv{$81~Ml@hHv#3=cx
zL%mk}K5JJP9vQiR!W(dQrQAC`?U@ikJ8X9uAvCXe$0tV2%=ZQd;q^Ie^{oo^Q{D0_
zcc*q+&wHnabJlYG`SS7hKWTpZ2JcR1XwAlJM`h-~wJ1D9u7v!_mX@Azna6A(Wli)7
zN9McPtbAPGi7<_g*S_qab>$$1>g0zI)plalGG9rC2VAFHb3T&N+H?1FFC4a$8jh@n
zac(8xClbP0op#!v;Hgd*TcTcqUtIKt2sa8to3$ZoMY~UKE$7Y0Wha_VJu}uZV(v17
z(DJ$59PXUB8G#5dJa=e#=vKY0CAV$~`ABw7<b&pc+r#`TCGfE{^AE_^C8CU$faGw2
z7$yRF@-XOcWd~CU)(jWJZCihWBV;L~z!~Fx<PW*hE?)@Ad_*kKF|kdytFoNS9TWD5
zi<l<ISq=q^v{Y{dYiT6(UwE!XZVKB%L}0Mn<<sP)BDyuhC1dTjL|~R86cC@Y6AqfZ
zd7>QNp36U+y3;$9``Q|~i&A~Z;Hb$wCi$?rSKKO#+7Wjo#PWy342T;;aBjf?LP01H
zuH+XnUi@rAXUi$bXjAAQXsg?T)nUmGh7ze|75byYfhTJncD=IARVj^QVk`^_En#5X
zU;aPd2ttLt4IW5b0U=GZ#~n7;o#ebH_ke|gnX=<SIgB#TZG<zcXSlECjU&RP_CFKm
z6MH1)!t6MX^QBW#LL35DAGsJ$e&|*>W`^L-L9|MxnWyt7|GLLOtPq%+v5&Z#=L6N@
zlr%tGUmSzDP^8Bka6}WnfeXqQIlho{LQ2-<^=aK4r0urMSAZBOuvZ-OtQW(_L(LT5
zl87o3&wvvwUOY7{^@H*rhx~!5;At)MT~9N2276?m6$BX03P>z?Pb`GPRBnYRg?DL*
z5iBuI{-?FRa*!*=*3cMsMa9+8BLbMPA?YQsFb+^XUH72&xi~Uj!^1#_95r5WEog%w
zb~WsSzAi^h{>+$tB-|cCO$-Z1Cm=7@$PHfJOg$m5f`1FMkMJfx(KZrdVn9S}OJ*g7
ziN@>_(q?oxvEzxiA%g8_m{mbj2f=omLl2)|zjn9<;q^Ku?#Eh!Z_ZLN^Py@xUYQ(*
z<gBwF3_}ZC8}?bK*Q0hnD7S*@Kyi23L<~}1?;P&{^%8+qGA*t9!O)Y5Z-u6wNy(8l
z%s;@pZyZ7xQVzUuyWAt$25`v{oIG}G`GDpWjyiI265nE)G1r_u`QdjoVTSzNOQGVy
z?>1^@C;%y=Ak=0jeDB~RMB5-kIE8X<Yl!$c1Z(-5A=NqgqV%2NFHLZGIT?1n+vOPB
zFwurp^z>SJBorf|B|E6x(U7bDpu<*6czZGr_u5uw^SE8;bc-5q&1pM>g4hzmFP2em
z*bWD2VpLYH24N*zmsP4w{~ICahd2TdL?u;*hfMdhq&MhfQiIqDo+JM?8+Y(V0agkV
zvIi;{!mvM)Q`|O9;_C@IWMV_;S_sTdU_p<DTP<=q-E=n#VA_sJ(+tO~yuB><O5mhr
zqK(UDi~M80vT7y7d<i95pp7<Zk>B<^_q-Dufr8z}&#9w!i%uI7{BZ`Ntd>IIg_{a$
z9~2^NL}~b*0>r-_3RJyUL#Lxyz>cM@91+3GfzY~w?z?%*s3fn{4PHKL=d@91MuCsT
z&cdLg8<Wl{6Om2W6w!i-9R~_Nt3Gh=VndbS2daBvzj$5k*Nt(#nbU7Hf8e^@%2Tx;
zZT@&^x7=Y(aR;56<_@}Xns@8^S|ey}jz&)Vl%`;Ujw8nu98^;=dG8Z8Fd5iUb4-2i
zp;cdLYQj%Y&xnaL%`xS)@Ba}=jMG56F+rr!;z}kIUGQ1Eg)tmGQECl9aU%K|_|Aj$
zZf^lge+r<CtWPlO9;p4<;K^Q<CBa(g9~!4O>I%rBQEms|wL(sXO$5(^*C}Du!(s@M
zgFF<(;6l=YZa+T=n}CP#dvw7(5e8!Q`uUzTH~kPnF^NN64zrA4g#wc;i69Hu4*3IF
zNE!>iPG5oHPHJEB#DDpH44Z--vE#sQky~K*+5t|GZLbR(k?exQ02{ok!yFON14x60
z?Hxj?jr24INefqp1-&R?vr2~I_Yr&wi$_MbGMNk!*}2ui*ljmlfzTTccN9hqcSP2v
z4|u_J1o0VJA)!b~tO58Yk`tIKj27t%6j8GmBMC8*m6{1_%qpccy$!oah=8JmArfOy
z!u@>0K&wy`mAoh^(NLjGXG|b%vAdeyiD;0thaI&Hr-(}q1_`UsgI}b8^N#X1w_t5U
zpo%5}93aDkfwzr9k;*Bfyhjx#M_tV{lOwR-xhx%XuJu9(#we(VNFRHp%Et@Z*lPIg
z;Ib>(lKf+)fpboZZ>(fX0%|wE?blU3*{3jU`OJk-ke+0ic4mlu&}scE^b$A*`n2sr
zIW=rN@J%>3F%+1_Fm2ez(k6LCYEX44w!vkkR0{&_w?VYRuiv!Q+hVyeoK0!Lsh5OL
z>K<FC!~b2`<Y3Me2-S72)W7o^Z);M)Nx~J~I3l(~8xar~8^~g%wQ|<JN0yZjsco$|
zGAd{YL{1J$nB_FjrEKa(L~m{rWswS<0nGbVr6uEXou|6I)qCGSK|1i!xAbV4guf3*
z4ITPt(#K`i$!!~39h%*_TXV^~(XEjv9Zt8vPuII-S9UdTQ%XyUAk;qN#K(TMAX66H
zm))x9&1P-9JW#OIejar7eje_NWO%*eACpSh<5?PaO9>wyTv<|*Y0jTWBS<YQNINa}
zr){jEPH7q|N&?}c@EXEaO5vQlNzE%gIi->{Exm1D+LkWMAJ9b`91rjS!i~GevdsKr
z-~)s(LDB!Xu&V!%PJ$5>1Jehlg4quCFKAvGd=qguqD8PM5H15RFIFhS09|Ya&1n~h
zsuH%Jk&+6GU1XUcs4pDV(mR&GT^orb=p~4i%fO%@yJE~@cRqk#5SvDtpQ3jO<`I7!
zfD;uFB&?D)4#6kGy8_qH(7<TAkiOd!aBPwWBCy;nA2uGm+{XS;Hw!Ik=7%C-`=zmn
zWAJu_t6St`G1*EDac{VVb4>&%i_00r8+qy?d4?kvI+BAkNU$DoDtu2QAt4&z4aIWD
zyS?y5FGC#*RxMsu0@7%!5Cu>nf(2eFh{`S;CIMhOF<8YWbHDU=3Xuf1F42rtumFrJ
zKvZ93wX*VgjT@GRKEb}w4K%pY$XkODO+Qf#H4Cxz=x8ho(V*rr+{l{)B<P3=C=&J{
zTlJ;??r-yYQ<hY?<4Qx7g>a4M)4N)PYz{tY@M=Fi7pMZmRfe=jhoGrmLU0HV^@4;C
z(GGzDL?Y-!qlc6c{t^o-3SE`-P}hX8%&tHR3u2f{3!<!`mB+I3OP#1@z<uF4EOg4`
zXW*KVwyuC*Xq+3+8ZcxJ{owt>HL`%Pza9zaO4foS!$^dNiLo+#^HDN{tb&jf<-{0-
zB5&d1sRZiwTSA!7Cg80hw--o((SK*l5)jMtsT1G=DeaGVMz6Yl#AbUs4M;K%vmj{J
zZSV*7Ktlm<t9Ji@J_gT)xk13E%HXEQ%QAR}5lbKHBNzo-mc-jbn0kgKKwd)To7w0|
zukL%C7zPYZw1@Oz4yGY;WcrB61oGenxNZw7*Z2E4WB{TVn-RHlF#!dvYe6F<DoB@B
zm4M5S_{@g@MgNR7Lk;c*?gY^m4$%$Qj`UTjSFqMJ#EW2hAPLHvzb`bdB&SceJ07wC
z!)3{Va=}$$MWU|DpzkNF4)bshC^1n0*@=&kh4;*EjT~p};D=R&gjy=t3$mAq(J)ME
zFE&|G6jhJr!25~?(WG^RAx~?A=y`Ndpa_D&+{{F}Uv@cRkK{QB9@%yeMh78In8TTj
z&RPfyL_T6FwjtzFk%s9&lq95XHXA4Z^aP>fIi7#F^umeu@Sd<w^+UiTGLw_)F1tN^
zq?;KM-rRCH0l9BnIbPv|b~FX#g6qrTg9Y7kAA(s^nv26Dmn0YDE;TL8XxU&I;Pt}@
zNfsb%ZO6v9yYQBQ%7Qs4j*Y3d0ih{h32E*34)T|Ur@|3+i1QIz>P9bS*w;i?5QJ?C
zv=9hX02+)A%xpYa5d)z&W>&Jg;b1#OEM(%f-+5cdSQ-(18F__Xl&W9;JrS0-h3$i3
z*gG<oDgRE`dkv1V{*cROkCwyV?A&FS4{=Kg%i$mML*bf1{!Ot<JoOlFk-fjUtTgzA
z<>CIp5IRtY^{mu8?rG~8PcI){={_gN;RUhX-qa_<-hJ2rI<i@1HSMjYC0$s^2r|P<
zx7x~ZTL}c}g8CK0LA%^4Ou*;!9ypTVhi%fz9}iZZTK3OI3wNdCcvxR+J*R!dYi|kn
z_gDjASUS`>(RsA=1kVk0dcFUn`w-8`-B0t<&xXmCuskA4-oRil++o02>-8XUc8ON&
z0F*iL?6QsGIWdv$@@_^9T3dLpbEo)-w>u3LM~Lq9XZTtUiz$UDUJsji@Ad%iz=7kM
zUP8pMhZlWuoMdIit-Ph#xH>em+sV(BaWuV|!-XPFe(aYkq7~b^$f^CV)1>v`aJ|<W
zp$}~C6NfpDs~p~R2#(1EqKqJ`U4kL+j0Y{g3yUQ7kJ&9U`l#p~Ez)=qUbGg(VimCj
zIjo;<l_InJ&5($u9J5T2_CcOjrLen1w>D~t=xm+htV|Q0wyXm0o22V?+3#$78@}5E
zj;D;uZ+BVh-n*|UKM;<DPWS&Rhl5TpTubebq`rA=_i^`;RQGZDh`TG*7sUjXuhd1~
z?}i8yx?lXC_KDQ)mc0{jZ|u#U@XCAS4V!n0y%UF|w((kcK2o>KXC@Bv#|HjtTwC{P
z2@i;Vv$b)sV}yd3zICVLktvE7=<e@WN^j6@9yiv6-N&7;nQ++cw>GAL?2F@@UA;Fz
zT*}@cm30uHwC;O6vs30DZ~k-MjkukY67eZcXd(x8w)tHs+t2^)JM30SD_`Yzx+?1%
zNsFB!u<srT`?S3x`-n&H!u1X#Txf6j2;S%lDbT4G^dOJQx8Q$(5#IBv2hU+o2k5+a
zf;?BSi1+rcLfZ0yK5e(P(__2Ly%XU`^RCp>X;qhq?@7U!?^YpQHo1B8WIAnZ3GLQl
z(?sMH#)DU^67c#__>j5oY7H(!irztd4#L*Wy``(Q>h>*oN3>}q<>1iG>DEHM8}eu*
zH43!5ADn<M16~ZAb9(%@R;gkS_S2q`Fq3+)+#(Tuw7I+y=MP2bvb*_4#1i4XKf(5f
zM_o7y2L?K{y}_r;G$zE#?2$x(*1tv;UcAE_XHQeu%hPxRPvYC^mmW+jn1QWs{s9Z2
zXc6WJO<7Vg*Xe{c{1Tb(L64zGq@AT*_<X4CUCYxO;Q7fMa3L(Wh83?JZVMo{8E$$I
zv+t1(-0qdbE|B~45u7)B-g2C=Z3;2}M<xadfB5@~T4`UoO)IC;IUH+dvM)TRv5g@@
zUbuR*)y;=*g)6tHEk`U>PNbqY$`HSUg$Id#r>%fPU{US1;30vp7(PdnQ)E;T-oYUg
z9-t^r3<@BeG0Wj?d*H=)BG8G}K)ZUMtL_!bH-=rvek5t)aQjHA_k`!+Rl(yj%qh-&
z{1k@V4X+U}l{727=TD_px<7mb(GH{VSh0ihK?xo}99-tJ5`Ja*e0ba&xs^-AE#Xy4
z_-*I_GY|VQcs#9u9V#YvX5bDaUknxaVEo`PHxR#xgakt@VfCXA;M)?gIagiR%P8Ma
zyDiPz1a8P2c<!*V2H5GlCcrD3!rg<6g?y(#^v^a?8VN`FP6Utf@;11oK!0{*q8AP^
zuUFe!ItG`{aW5P(<<k=H1au<)5bv$+6fU%bA^5(qj7%|xHe2P3P`V0Q1)0EKGjU9n
zN3<Iuw;L+pqqi>EfOV$B8ORL;<0*l6UkLi`2}5@H8!C6a<Z*;I>VuAPEX46maFCBl
z7e9S)yG$N+y<GN%@`Tj8Jw)Y&yU8c)ZVER{VDVYj(~pF{JxD}_vzSq|Sj7~~Dk`SL
z(%K&2wO0#g%<vPHHj}TDysBHmZoJG#kJxH=2C`yq=sPm5VAExA_Kw<?ud#!Hnh{Hl
zG3l_roZ1sgHH2Ls;O)uoMB6=xNNYQ~9t8YWc>~D2TN;}u0)}_&y0P)$xPeL0BN76w
z;Uzq5zDHo+(l-+LuLSzie1HXVvnA5dOS#@X=zvtfzC*i@)1uME5fC%~%7040!9^}B
zdNB^30D%|j%4!BdvkoZ;jxV5{!^}-v(CZ}n>4iGbp+TkEB)e6!=&5-dyCVN20(Pa%
z;Sa-WnWNH3*p}J4EHocj29peNeFi!2v`UsAG;<{-a>J4S!K#1!ZkXU&<WzIDJ$8E$
zk$f)s&6);7>`zC%rP2PRE)StQ<8}Fz6=q-X9+cwaIL<6;ddHz2brd}}O-LUHHf(ta
zjRg+0FlYhNu#4;g>~I>06DG)fgAq0am%vIbZIObD=rOo2X%m9d!`ZS|KBOV+>vbEh
zv7Pp($f@-pf9XAuJ1TaJeeNM^(jAq*7jCs@K6+z*F7MjL(~hyWbMUTBy6EQiuFdQi
zL!G(9zNY*6^1I+=`;|AIwsz_G8lQip>+<qz)~j+zUoKzEKjG1vjl(-e{?I#l!>fhp
zwLb8&0p%b1;UwUW3?zmm(&nXLpuM0g$ZL~+311r&c0t-Gib=Y|_kPfK&hQCKNcsm$
zOZFb--6#J2Ul?)AXe_EgZKIvpq1OFmehyX+9VpizdFo?jD6C*30r!%Wu+~u;;U59a
zQ3qD3pPk@1Vn!}bEjjCf($j(WzaS}L&H#V6Ys`g4k2hk9Lg{kgf3mgYVV!0D?a-`Y
zg2QyZr)0q(!zxtpoh(5X5x*>lyhQT;k+*RPQ%S<$NNNzI8ZWeP#EUT22}NAjOG?1l
z7<fDs)GcBv$*4wSc0VUfpHlQ9nnU@dmPMyVGcpm&f>T*(;f)1o=7GY>*TZsJ0aw6k
z3%%;qa2tx-3{hX6Wy9Y{q`;h%#yqTfUdD^QA;#Mqz@(7W9EcE&7020Ve$=8jGi+-t
zjXGu)vz9>A4GPNUz)yg<x=fl7YGf`T*Rra=@m1C&ZPid6mtj2;JCv@3Kc$SX`9b^1
zL`XKG^l?tO77@v+D7JweR(l;+aJfnLdtjU+GJ*5>4u#?U5D<*vMUE~TE-xEYP=O`r
z4nJSuLp0%gI;_yxhnL=z*M{GT7y(a4U&CWFfic&3(E}nKsjwv^WV~c9rJBGCbE-Io
zCi~&J(!n9<m)z?{F6aaf2%_?c8j`peHXAH>vKONvpx;w>T*ICfu%6p(3*(X@cB{1I
zYM<AnzLEEPwlKDOl!S;9Vzz$C-PNBIqaF*27F?Y4>R8zx9I)*>U{n;e4FT)j2Rkuo
zrDbkKOBn*W<3RcjoMqx&&L*;vY1E3*fk|2o#~nruhh;EmD0@Grkc$N9!+j&0COE>^
zMtM1#&0fK}Y@lvr;Q|&gfZ<z&j|vtT)?7jBRxx=9(-Y$x0vlAtW+P>ggtDOe3Va9(
zIi7*KZonmXh+~`J&4T9@V;_G1q8aAndvYo5$&o9FW6(L+3fHm?eFl93YReE7r;9Ha
zgw&-pQ#$Ps!iI{ajIdzFwqO!e$5#w&DoDd@faMT7hxY^okspHKp%<6Jo^<H}-!lRq
z13Gd@ZlJs#BCri>6ll_y6hw8q;p-$6q=_;{8vS;II#>xvD}kfHw1|(i&>D7dhAjiA
zSUjU^)&EE#HPmuX6k7)8Ga8cgJxx(+Gz4@z2}uk@xVCNC;0}qV93bqFSzQCn7Pu4t
z!AsOTe4E<d?yG9q#7zKRApA~4MrA=SVokhgf+7l1EE~dJ5X(a^x`AV(!jLj*$dc|j
z-chyLVRURHTtC?E=<Jq_Z$lAmdkCZ<!AJeUtAv4ILfoX<hZblg@Rh(4cF~}(*cjD*
z63q~Ft04sO?O2>o(j0I3DXfSCI7qkEu3%j*3f<EEHkt>te;Ac84icz7^#balqK`os
z_w=Gk48_OnqDOR(<Suw+=&dXVh+z>czzBj6gF&!mQGw^Ll*MZstSy&dcjWNSSheFf
zsDpC^zn;2`-S;&d;(*l&eBcToBE^O1d(Yx~@Fsx|+@l*RMg<F0z@AKEgGhSq*XfJ#
zK@OQRk#C}T9CaduA0^wMD$7m6L_7F;lqkc1hK6c3Dj-8(CFj7+tccQB7@-E~fT_wR
zptqPRq$aiHk)o2!o%p$KEL<0_ZNSf%GOsycqC2-4)r;DOkojpWLfcTV8PsPMS|qiB
z?V}(qWG2^GsOc*?C$~Zcs`p9aFo7XpsPz@8RgYE>gm|d$eLafiidQvI_KCybu&uEe
zoahl%AohU}k&24esOKUHW$l>gRIs4Zu)#}jF1r%iGK!8t`tkd-7!}K{f7}7NiZIa8
zPG^{u8oiUjlGC!s%gFYyxt+;{z>I1eBKw$xX@Rccd%(#Qt>x5D>aZ2MvLC87f81N@
zQS$|<Rlm$xuab=>lBj=rRwBtp(@Uwckaxi%L{C~y5J0u`)1?vcia||JH4WVg68?!p
z_NFig;((>n7Owjs`RMGNEDCtx@ETG<plfL0wKpTk)`0bc(!B{OkZv<}gmxg}LYPU6
zEvuEMGl<*K4m5Ef^!guNvnik!VP~=QPh~M=c9V01i_M(OK;Rx_qJH6p)R2ib%_oT5
z9TB+;m<%{G&(4KYC9cY`+eKAf<Auq(XL4^_3wh6?size&O453gzt5zeUMJBQ4NNTu
zeIq&+au8HDHIY$ZOGLAQ)dOcSG9s>e=<k-I$<t61skKM6R09y=G!!s6V(-W=O*}Up
z9{MOsK*7Lq8A*VenC<sGFb~Yc0E?3XeZfN16++6S>Z|^hhKE{o!WNAc0oS?%=OFA}
z8@qJGAS7%c8>79!GD1tM4nLj5Fed>!Pkc*P6vQ@9$}!FFBnSq>E*b#jJt<^#@<$U3
ztIhV~(I#L2`p?~$J-OY!)^vWsy?gxw?n`D)-4M#+gRp6fTCczsZgcNgDtI7uU<KDx
zH#qP8%w&bXbtih(pB$GrIgVU>mHQ;TfX{^R2lg-HVpmFv^zy9rlc{w<Huab}Q2a^r
zmZpKMdG{UillSEA>^N%X+y`f`qTJxDy4$>Ay%kkB_4U65OAxQv##&P5iq|6S1c!Bu
zT@7}La*CRR`4Ow7z%&TZa5cEjP$5-U%gIWhXsyz9XJwsk51wE{z1eiC-*pPx)2r6M
zWUj@JP~f|3<Z~_M4oy54+AYvAjtS-3Y$>%(Z&~(I_7|G0-1>dnF{by8uTqOg9XOkx
z!uM@WlzExHHEE0=>7Ao6f)J_Y-KR_Ur<!?crFhDIcieP%)8XP5oYnHCaoI658s3d7
zdmM9Mdw2^W@%q0%mDJ$DASOb1@UYvSQ^Sq&plki<_=tOZxHo*=8+V>-L4;8cUb<D9
z5ZsR?lTjTwP1@y+;Uk`V$M_z%1Mz2eTMIlz!T!vu1F1~*Knel>SOD!`#_P_G({4Qi
zhwOO!jWUN=y4@lE_qBw5o#CdCRMjYemtuIepbst>YeXI{9}g!&S>e055T)#~n;?Bq
z0P#k^Q^FC~uC^Z<*NVg8H-^W{4|;f|a)LZ|eOeFncD!wkRe1n!EpKU8E3!D?ZtU3T
z_Q~?FTak$A8VU9Nv<J{@4|q9x_=BApYBPkl?;FF<wLj9)J1|i~3|&d<)q1$s8A8{k
z1%`nPkGEUajgOSut+f-SwG*Px8X3&=9)JKePJFhRp<EK>sjSy7)%LZnw{hZdG55L~
zA`&lrj(fvl$3$3y+XYG}^M|q7;c!5P;fQ;9BIvvE5qCoeTvzbCaX0XZgm@)UF@|kw
zZA6BL|1Vo_102_t<@Yr_t=-lvXGTP|v`v_+ZPYevTM6tPxmY$-R_&@A59CFoNl09(
zjA5y=ql6V>V#QNRSTUx;%JgeofVUqW0ZT!RTQs8ulV;qsk<7|L%9vW(BSMeTV-G}S
zyi5gCt60(ocAzrt5gj_gq*Si_{<lGmMicNuA82&nd+z!8pZ_`cyjrKuBBB*nn{~Tx
zn?IvSF`Q>is$XNqq)|6b)5x)-#bC45_M#phfFfmd%U^jW3$IEP^ZPMXGvV67+v~|)
zb3U1M+uS}(ZUl5He&pV8R}Q|(co({QGpoTVuN|FaqC6V(cI%z3lSyPpp0>?O^U`pc
zBj<GmoqM4X4iB)SQkm1}#<jJ0bI~@DW*CM|E00AaWZQZ_o2|NPugii>%O38!IoEEt
z3rt?4EpO_BUwI}_aM76~B3{l<nN=691(We7ftlYh<-2afm7OzfvJ`k-oagHJnbLg8
z+5>5AEgid@j9o`=R0bAGyOn`gnJ>p6EfzVr`rH|=wVPGmHEyCAu50JkEWNdJRE)ei
zAfQI6q$Nh|#C1~>t(&!YZkx)?G7F7gY|R_SgWWszenvEek2MIihTP3qb|STt=GbX_
z!7c~oyJ_3iyKX5TQ=#R)x~`TO?T43dB<^x@?7mHwlH);?1PiBwB|F|J1kuAo!y$*p
zdIvLSZ0VtDqhnol(=>aWY(k&u|Kd>4eVKaYl#EcOPMS7*YiVRl^nFI%wwpUxpe=5y
z_oYCAMtV|ZZ`eAd^~icMaz8N_;@06ES9r;|$L&&K?%@xisA=fu{yNCbV7YdSbx~GW
zGpQRZkJ|Q7`3VXJx?eU(d*g6PU)fa?t-0nST^qVZ7j2-PnC*i@*XsOl4$(v%q<Yz;
zi#FbNX3x2ZWOSYa$G`{w*~4Liy38xZ2I*kz)#_OMbn^DPeaX9}J0^cNMNd;Mf5P!8
zl|Y=QtF>$+&ZTa$o=zg$9_Q|sR`@M5XJT0hOI;ft4%s=(y;)78a%{V<$pLfl{j^zc
zBtK{jT8S-n?AO!kT$Z)E?!hK!@z~yz_qdoC;y337gsYO}QJYStz3a(ZGUYyX=3?TK
zMNYg>mmP)S4eSUYXNEebktO;Om7O_j>bpUC<Y+Ka$aknFMBLKGe01jMXPyJCvV_g3
zjPrcN&9a$!sr%=grc@1YSa#)7$6{>K;26D#kmisne?ydd;rCwp8mCSMkLv`Z6ifUJ
zI=7L?jy8{5x;EWzI_iRGcVd?t1Or2i<s48ldSt#cZfaTFQYp33j_D*-R~c(_6ZYX|
zQz(XWA1akNd5e4wq?yfTSlf2FWtJK?FFbJWoFD$v+L120fj~L(z<A|gI}bnZ7FlKM
z$9S7x{}&7dd%;;Xq4~8UE8DRXopjQST~Bu03vp{?8Y8VN<twir{!xMW${0wFb#UnF
z>7mYeF<S$aPNui*#9oqA>Kj2PnF4Ao+_(0G9sAhO;o{TJ%qe;2;#yiQ=2&#pMrd<0
zE_Aq2{|lE>lRkHX)UCQ+nIl_v>*lNtFQV5=?N;~DG9_ZG!3RJ6f4{~+Gq@6gQ0}Sw
z{RZ}~v1t+|TNh2sV65gt(|zsnm`hTqEO4wgf3=eNFqjRF+LLxF*bD5~-C#7S?P$F#
zwtnrE*X^YNJb-=;5MD5@D$xrOrY>D*n}rR^{j9~!mA!#sDzcQ!s*PNEtzPRUC(W{5
zH@kM$p${!yeDKo8jzxpIzJL2yE0qd1rZtnc*=+s1y%TH)=aW0Zo(-nb>3IHJa3|TW
zPX{MfrY62)ugB61n#(wORJd9z*|XF_PFO}K+~+6EUVzBY1<3liIl-T)%F8Q^gdHR|
zC=7++k*kklpO{rSSL>SIj{P)cedo=#R(FwKt&~$Bx$FN9GYxcxq;VBfjiW8IWa9da
zqaw)b+jEpP!<P%QxV3|O&s};J&hD8)VcPLi*+!P-oebXIF+24gb3d?C_4`5mj=jKY
zkEb_}+KCN2yRvck%0cxCXEMbr&)1H~7i$le_&XJB1zf=}wRKxKYRB)}l_|3w{J`oM
z8iY8s{>T6zXw}wosp+jHC*6hkg1z9vMMt31nXq)LeGo}FxROFbGewQ0{)?vdbb8Uz
zls(OBxeY>TF{GgRcwza%K&T%hL?}(*s#_;0mbwI}t~r@5$17>iY&h^y7&8pBpufm^
zxOIbb14cxhIu2`X%a{t)vo~#fDgUa5s8Q)W*ckTjwn_lO)2?BXB|IOFFLG#)&*;(0
zMlRB?a=8uo0jVt#)Gy&MhwuIR`m@H`P@^z;Sr+(}1pszURB|J`@i_pP)6(3P0tS6(
zXh2h0NKuE52)Q7Eqd{}hHt0(MuYs8q4Ver<#0EGpi-W+d>=<O00fiB?$}k1~3lYd6
z>vvLfoqE(k<kw9nm@DU+E*gH~+QGrc%J=^Iaf$)}d!UfQHZRX+HihPTo%(H#hnqE~
zP<9W$4x${?xwE)IP#;E!m+7XxZo)x=Q*F)VqHY0@=)JLrHMSI@io}Ty+Kb2zxQ5Fi
z#{D(Q8U%7XHudO?&m@AZv5|K1+M&VXm4g@mpGRI`=Ak2DBrR@89q>QtMAuDpgGm>C
z8kmb_G5HXO2ta&%WvM+EhA#rtgs3v7h*{cE*><;r`rY7eJw6+Z%TDd2n|Q@eJjoa<
zz$}6chp*_;Rgo>2wAPKQ;IC-bl`*j<3M!S%`KTr0g(U-fs;dFf7{`j*&I3(9ZhZ$s
zS`MEq%<pX<eKvSDR-_Xo!nffSK@F}sma^<%ipYJ(tk~q%jEQ#51ZQsNkn9l4cn%Mm
zZFKEweA}M1x9w6=I~(*JLxnjs++PM<@LD3Xsa*}!u7rRs<-BsIz8Ex@-L4!%OuwC9
zH)uerR|Nz~6{=CGv}UWlQCAIl!IE2cS6*9k7h0OUGhe><-~S^|)%b+Lpt1I-jV>p^
zf(WdGOWp`(+*`ZGeLV3k9H^HyMiQ3hC1|2)50%)h=Z<yUCK8_x>TSEUGWIPqNo)p7
z2=EMtSI14J5o3_K&0ZNeI*Oak%^^ch8c|yo%xV?z^?QV5r5pEnd8u^Qnba+~kJ%(0
zvcuuM;lHj~0!Ug8*~e&paI9k{?$$Sw`Z>Gj%yMvGDQ=lgdm-2$S`LDHV1f7m)R?ak
zqS=zY9ZUtg<}&^dzlC$2bd&AE#1maiQI0^<Wb+L*mEb5GKr*g|J;Z#0Uw~ScY;ZsO
zDcSzIJ9gFf*6Jj2Bb^x6w&dc6<9iM{)1oo=@&{iH0-+15n2m~{Ri*X7ttat%Fmldr
zyVGXUEnJUxN&M?S(?cRGE#@KO>x>UJEIQ(vwKB3P?*u#b89<RqZT(w@m#|4e<<J5#
zvh=26dgTMrN=n2Yb&t&SSId&+Wg!T8CvX)eT%B7B=0->`N9iH>4vlZ~#_avp-+d+k
zSXgCBO3zUL#)^&BgPmYKn5j>>7u<5No}}?xX5FUwsqiUI8W|%r;hd|d8QEiP+;y&g
z*92$l)sw+(%X(McrE>Wi0~{I<)P*6gJQ0RDJTGFB$+W@rD-?7A56Ksw&8O=HysUg+
zGor^p{w$fR%K|UBOCN=^?G)+S!5{v!U%f$;hBiWj2?e&4os7*Gz%7ktgS`}&QHcv%
zc5J3HMJHOZvQZ#BXUKegj_hjXZg8v<ECuQ2N&EIWd)AEYnm1N<%?~VY1=gRuEwooL
z)naL+YkTDLHCm;DYUo-HF=2A3gAP{CqFP;5>Wtqz;F>W?v%sHAH`*6k^Rpb&-tYbw
z&(_Ba?BZGHQ3YVL(XlnUvfu}9+uJE2GMKc<j~oMVrrc|Q0t$?bQW+?mk<n!vBUx;2
z#w;Z#ft$fOpvbIUw{45Rcxr_qJY<%Gs4?e42x<~dlFeE-z))pP)-5Qa&a)I*y*~uM
zY9c6}<+|$t$+cwM#hcu;BH~JeTlYTr-+{-#KB-Y7TLk)(Y^+<-#{*ODj?~vCxQY#u
z@_Q?8u6yu9e4{QQ;%+<7anUtX+X&jWGQsdIeyv+u9zhe`wJ;jM#d)?F-h}scE_KZ+
zL3fU(zEFQHx+Vm}1IUS^TD53|1t%~>E}UCoxJH|Nm>{`&@RQ+x^~h;^1J03>H%FFT
z4TJ}6$JDweKJCJZ)ZJjJQN$|4!J!IQM!^PL8tyz_%VHl<c`Z0rx?4vn<QMwBVeHVl
zbb<ASNcRldlZnX99FeZnHcenU`~kmbozRu{!3tk;4S30F6Ha1tv)2uXGtDNd@x*Il
z^}_HEfB!21wQpZQ_HaRd^+4+0?!>{uG|efM<i_7#x%3mu9Xu2a3mcrS&36K-7dr8&
z`lm@U72Ho?Ze(ZUJIKFV7`k>)P}2JaT;CC{WXOZaF>uE2o9-e8gn{=J!9Uie=ogDq
z>c$ahV2$9MERsGi#`8jxyY2_=kKKfsA;SN=KYS)Q?fRs#G~T4ExJY!;lG4p*7cRqt
z)o%c!H9-SG`BWb<AdNV!_J9r}BX@(B>I*@zV?LhPHRUG;iVBDPsSX`^sA}*}T55v8
zOsj*DZMa;BYf!9sU}>0*T<Dqsyi}VFdjN}b?)8FYWC-=z?;g#LpSBgfT#Q45xXD5Z
z<bik@z`oftBzDPLxv}mm$6Kf?H&*0I3kpSOYZZ5#j->!}Ab)8W%nyz@ZpK&g<40E}
z4>EEOMG$oB<cHK9Ug8#~X*L_BKHG!=JwOuD2+-EPI`EGkco4;j<D=*;rZ~fSwAq}X
zI<NipKYO-bxk2^9r=s#^B=(u5Bt02mx-5HaCcWj_`N89|GA&#1w!n(3=Ib_EfopvG
zegc*lOA;3B6OBoC+)QlbalWLZ9!fmgCyPcL{p>E+TqR@)k2gIYmk!H26tkHOLhHa!
zZIO=xI2L2&Ac}*F0u(~!gty<g_Q+wiq;lFQ8b(y3Idp6-o+!U>XWgthnk>b)X2|VC
z!)5H;Fcu#Y*l_g1N^z(D_D=AUsgIz_N|aVeKJuer9}v6X+Q1Ou8!3ata;sq5pto+i
zd_37R!E4{4$)jdivfh(L15?+MUTI_vj|Yg@<tC_OEl7ComBL@((rGrNB*2oTnsS55
zq{7_Y`t{&$u$QE4jyN}y{s<7>u9Nj<VzOw$LG8$qhl(}}F|!mbK}RhmcwyG9^f@YY
z+~h0LWl~YV=Je3j3d)2Zh&c2E3U)*g0$n@<uE7A&&quTf;Q{b*BbRALaV}ahRn+2w
zi{EfsHA>Q!FaGu4c;p3p!xEi+gcMCt@+iWtnTfTn6J|NSkA9e^<AqLp$ui<#kPEVU
zqzEcvuL_ugfNXik)J30-nRChM0L^IIOKnC$D{=sU!uisXBiUld!j3uQl4-@$o-D!7
zA$0KCy!4c#wtc0>5gstTGBjIPYex5B>K_MXa!>V*!W)H;e){La@qnM9k5f8AOxJEF
zZF3TUTwl0j?}$R5R8?RhyChuS8lVAG3Gu*C_z)&Z)_~8h-A@R5<4H315(y~SzHKME
zhbCK1y->4r2Fav?Qv_nSS;X6tLmLBaM!z^BlpXRVjNqls*2wWdc!B)gy2;M7asj-J
z_O14XFn-RdVfB6$aBnH^>7>x_EYn$SbIff7-2_@_&)9FKa||0<vUU!?3$mw@RJ@Wu
zbq2k{$jV(z@uXcy0#iRr?mT1o*_GiZt<U%sdFbxOJ5`&eiFZtD<xx|;;9AqJg=+Vg
zZB@H^z_c_vNe%b7mbUD5mm@STy1}LP;vs_c%Z1!O{^!ysPDV;a^uu>d+O$$zPs;ZL
zu*Gt)Vwd6@3xGE}g=%me3i6sZk0Q*esXCb8(S*+8b~4ru(ufaY7{)-;yF0p7R-ZG2
zReVy(t;K1xvF`G1Li7e^y@>JY3!g!#C+m!eHze_gVT$=~p>?h0+3z3zwLb@^qAT(o
z1xv*ANS11@v=#Jbg12YWX@eqcfFLW)Dc8@H0JktBM|{FcVhnS;6x>d3Cntj*@ekHv
z*5>moc5F0XR3^x7hOP#+E91QLY7AIYkN~o^*6c+GJ=p$5m%*YNS}yB#jogAUyRP-I
z+osDDt6My{{P9Ecr-KmU%BM*Uy0(k9%jZXDgJXDYE*2)Yx^A-YiNz>D?R-4YwIs*A
zX2)_Tg5Dm7KanJpF=BVbkx%j~(rf}W0lm<$15Dkh!LH+I<F2ihFMH26L#(!Q;4RTl
z-Ue_Gpoz#@ao4qVV{vBNM90yB6h*#me&g>9+&rC(^KZF6<OjnO%~(lVJ6qpGYUYBS
z&nNL)Zo`&;mM?^~BvVR2Wl54A9kL~K=cpytcfdXda$dZZWj=%54%|0_rV1?pu;)z8
z)1IaggWXFGZ?WKZT@LraXCo;N7w?qi-nENjl2%mVx>8jc*|K}8@H)-Q^LvFp#Qg4^
zfgrHrvH|guFb2BjATe$Sy{%+HN-=g8SB!scPqlu)lXnD%bfFMF`xK6-U}0+A@p@${
zc-q!Q(M{vn7VZQunn@o)z|XMKgg(P{E`$sVgh6#|JPSX#EXdi<`{mhK0)Ewh9q6s4
zy|P_Fk4ME?&21E}h#Gus+C8?t^Cg;@sbmQf<I*_ul7)qi@b<jvMYD{5N|Yzvu*V&g
zAWNp;X2T<Zu{G)*L`jUTchob@WX_g~QtlE?xJZ;93OmnN2TjIdgZS+-2OkpfU5lw`
zpJCw#DMtjp#HA`g+quhHD6>P_Gy+!2KYr@VL7?sgeR=~lTrHC1Ur#8!Bqx)pc+ap-
z^x;+?yU$v#1X006T*Ct>-D;4*e@q6obKsj3Nwqc|pcfJMQ=7_*Q1t>i0f?zV8Kv5k
zPc_(C3naYl;Krc)e6$cX;xQY`Oo-0ZUZV0*vuGFP=bEi+2VW(<m<j*1MGq_qRi8{j
z$pYC@$1#n<Mo?(3P@bUz27{(DEA>H^IXE~yO>TtJtXkqwcPs6!86&~1x}h$!x(Ffz
ztakMvU}Kmt$a^_0qf@WqbKz2OSKfJLP$j-b#7xHax+xt^V^1I#E`8LZ`mASh-D~|f
zj~qT7!w*T*<(T<s%sopOolM3cB4cvSxzbB+ZrAJ@vvX^-ka-L)O_}fXU;)Hjh2;RF
zT(|9@=aPhjFXy6bE%$1MEDwh;Je&pb0E9EmO|Y;5o?-J*8Ar+?a*X}Bi^i4txJK8W
zH2g}J95U^;qwb+h@!;Nn^?Q%hxjB&`3u;(Qs+NsN4(jy|nui?8R;F!O+*nB|W67Fm
z<tXyLq@$2wxs!IXj+S)lX%JD?AY@%>dj?Wes)y<jmf5JwnfBlkHf!aVoPdq%d&$0H
zatNCgTza;X^scAtX5FOdZ~Ibtqdicp>{h;1sod}_mKa<oXk@E~X)(l|i4{A(S2q{H
zC|i5Z)>BKh?eOBEBG(=Uu%XrbbdAUch#6PzV<)#JE+>;(N!i@D`Kii1yE4(YBM)}R
z*}T5%v|s{34eaLP8Ap&|Qn}&~k%%SNMoQ%OrP5goWaOI=gu4K+kHSj%jl#Wu^E1d(
z+ymq(;=(pq@M_TL22{TygTj}$++5B@GocFC-lu}7!mD`{gynW@3MVTBcmU=$*K|YI
z#Ql<e(iVFr^mU6(X*qGIQ64Gh9Iw*K^ih~t#u3KqP)w;Y`ti1VwK+tR_sK_pLb0-6
zXJc6w6Q>?TlvM0qvoi2j*Dg7dRQ}J6b~rTrk*bzB^7*UeyhNU|>$ue|jAnBc7M&lw
zbfry(gTDlV4ZxUQJt&oPHCRX6%YD;1Dnh&)BJ>MXF2)yIl%v|}VOsV8B*<!;00%Sl
z2g6^<09tbx4BE(E#Ov0}uDokT%DXBB&Xo*gI+W?-Z3L%hyTKhu(O?8hXX~yeiYAFh
zvbCIRTnpQmt{fC;pavxRiBgUg%k9RSiwVmrq6U4*6(K6*<>?r(<lr?~-L3+C^U}B6
z<D?gZgFkHlYUryF3S8_)5V_>#2l#c}x-U&9_Jj)?ICaYBN?&j~Lsu#kDuW`J4g^pY
zf<bxSK584~?jd&xuSA_)hzBS_ROJXc4Y%p4>89CS;%M+XWEBs(lB%d@m!vVe>t@}k
zX~z6lGujQihd2g1ckj>N=AH?9M~FmSR|C_?vTJ_VC$~01<@7L6<095vITRntDf1R2
z=Bk!pBl@>yi=YcIai^Y+@zw~t9X*WA%YPOI`;7}Fxn`OxAUvs2cH)KdC_3n!oYzBg
zJFStjW(Ez6t{wWi3k&v>TYnQuD__rvGxUbR>6(6uL4C`-AG}ZU9KR=wKNU<T?{U%O
zsGX|J=C4yMlP(sA<(_@f^<;94YE*(y&s(Zwi5=SsF!MXeSY*r;{WB0(oIQ+qrY2?s
z*Xe*COJ>=rJ}&^jO~y1wYUQDb;D~2FrJy)fuwW0Rdnu+K<<SVQYJH2JQi17UVehxc
z+09`JtYS=MQ2y|0Nx~vtU|nrX?JN1TPT1T_EG59Y5GeDRrf$6v15AAIL~#pe9>Taj
z3`kYXRQ>&+tAu4Gs2^rKr-O-m_&DnF;8jilB;%7%K1*ksM&%@Jo!0t<=?M4zz4W(&
z^^~$WimC&d<Q8ya{QntkrM=jCyr4|rVqp%4^&k8zoy+Nd1O`LO>M{nJ+^=AYqF*w#
zbtk@qyeav;3lGi;@7c?5Jv>wa1t8_H#K@<rbiA$?O$FD3v*vg(32{C_{=h-5+dT?@
z6Qe7{4{lq~uD7ZtoCcSx)5vY57tO_VnFTItGaJAxSbqer*eTh{v&lVDW{YthIurkA
z*;h5#QS0LnkoXvXz_%N3@VK_*W{%!d6^OE!DkoZhAvl3zp=3dDA~>=29@Q451fRzJ
zqHF$m`WBB#CVQvGN)_ew8T}Y1l6oy$w>#XAn=~hbu@n&;H<c;#TrkE%MRZSOC@hJm
zV1XTgU7fQ@<M&;XE`z<rfXt=*<FgIPO0ca6KN*wC>>0Nl`^xPFN9FcKxDqagvX_g6
z|MK7P%)P_9)rUuvhbNq|BI>9Cf5>XKey(A&@tt4;Iosp6-s*Ru4SK*u{nj4CRA2#v
z<NTVUl)po*+*3Z4vAz5X<$SU?AVpD%rqfYxkaN9mTDuDgw#y$<7>~;fskfJ(pA8s@
zuLDtRf%x%Vr(T*qNZx4kTBRHC!o9!6M)C)Eq5&?~5D@Y1b!y_+%85Xhan63aWiCRd
zZcWPq_F&KsA0SW0?_?STM_CD5pTS5d?@!e!G6YA1bey*+D40*|k=d~ec`D)eQ+Tv2
zo|!P1HkTX<=GS%6iM3W$S)?B)VrBNg*J3H#qw<7TyBoh0$LIMjB*rqA-n-a|jxPM2
z^)KJVCIsXk^j(!oR&ty&pW0-~+zCFl!Bl!bHW$&f?PM=TQ%>Z^?<7yfLzKmITUOb{
zG=nIm(kJ=$Qo@F80yArm2V-Z0Nrxji4y`x^LB3Lv>kV<yW_pl-jsDxzG@~r0!fy#$
z#kx`c7USYK<g1G^8RBdamYRSjb6K`~skF=IRZkX{3UrD5*u6~6|K8(r03NE!UeNt4
zzk>&z2&Xxdaj#|U{e`-k6pmM>(kJ6ae?tlkX8H{AgYakTVnBn*ttFV3$>3NXmjN4!
zL;glk!LG;`1{zlb&S%xSh9%tIwVxsgvP}pT@myGn_sQO)DLfam5c551T4G8svRgXq
zoV0PH@R9qD{>`(C-`@SojmmhAa*1r-W);w+<!1>kyLEM9yq`$JI4h#e&2u(?E`QqI
z8s=D9!^8<t|IkB27QiuU6MHg1Id_8Hzy>e|mGS)g%7#6ZrGh5BAt=WC%OT;usN@;K
zN*rtx`R9G1)y2|!pV9cx02}08HsC|&2F&t%v5SXLKRGRUyHj5dGj_jSr<et<fL40l
zEvlR+&9YlDP20-3q22JQc9Cj??v1W8y_AjsG^tiP0PM?Edo=4i`l?=G7^hfK*yr#{
zzIuvko{hRmjo*Yd3clPOP<Y<=Dbkg|q>WB$_|-Hxrd&fst<{55r@opY!lCkjSy39k
ziGqb$*HbbaRu`C!S{T}GJyk#<$hK8FKQeq|m=g4AN)(OYVflaqWLZs81A;icjrs@w
zp?(xdl_od?kLcI4&vB|CvKe_krUu)^lABFB3FwGrO3l!{C;wEPp?!rHpKEZ92u<;%
z-n<PXlOis#(NJZy%^h95h?t9MU+^{<Pz>4A-Ey0$5Q>X@C1jYzA+Jur%QC1ZbRVSl
z7Q!7t9stJv`sCv!uNvf5x@u}UWD8E~7MNXwwf>_CvS`+3t!N5wOe8<vnQoDpo;RZ=
zN^wA|?It9kZ#zL8gN13e*EVd<@z&9r_0gNpEHp1&<8p!;^4XstG5n7ql|X1k-n9$-
zFY`Hk30re1M93Pgj4c!c!<yVu;gY5*4c+@2zo!cuYPDlo!0SdQ;iyZcGA>?uo*}`G
zx~<n~If3kHscb<SDt?kJm*Z{{ArKYFNIL3WIvcsnrHH{a;d%QIY@U{5)0!*Wa@o25
zqO>fTVhOBBIvXpDQvhiK&z%V8sXza<O68_FUmatHz##Y~Ux*j1Pu0%@?t=02F_Smz
z;|kUAk}FfVih*y+or0Ugu=6PUp*smTs(TbCp!}xl2kM0Y8m*nDXzwNu@j}j*SY5Os
zu#+|@HaqeXZc#y+7=a7@5JxJT-Dkvv>7dZ~RvPcv`zBR#<eG)(hT~H6;M_-lDVurb
z0bAXNC+v;Vm|0Dl&7~ByZF_h#(y4*h+lxFh6>K51glQU3C@*I@DB;XfJX4Qm5X-9(
z{!!Px3WXXVWHpcvC@B%l)}(>@{Xni6llF36Njt%2Z3M91Y`;2mMTS3g?_d5ly{TeH
zlm?&|#9NGm)Mzce4f<V7SQz$E7`o-=o}j--)uBe`bggux#HI=Rwp?1PN75nQc(sLj
zLXGiO<THq+e4rPvB~gi{b=(b$+COb+Z3igGXOZo*_@?7jFO{!p*MooXC-8RMuk!{A
z=ZpyG+rb2VR_rC!j#y9^+OCBy!q1lQZ?Lnrrh*RT3zUyQfK@;+${FM1rs=1q$0I>N
z6fK|@k=AG0SCqTTx=k`W*q(Y%y1eEx(Y1Dg+;Fh)N$I!9)(bg2i3MTtKAd0{dKD9+
zf>b}Iw0JGHJ}Vw1>-0_zy=`21PMkEt%0@J>A23ZLw<$t<*kdUS7XIV;D$=4@iebp3
z^)LejT72M36lzIHJ6KIDMQb7qNUK(Kjl2b@@Kg6INDC#yXgNsP4&p$?92;^bzT;NX
zNZzDz1^sP-E###sPUfK|vo$!OXf3FU914^-W-fIPy-EZl-cg|%JVnDaCv2LVlyK^%
zLDkGX@FvnveVPPDSfF}K`x6;59;I>ZAWHhL|2ytcdv78QE0#FPYLiduY=K4S5OeV;
zap6Ncc85c*Z}`@^=gwR`-O&0SWihxQIxG1ha$Lu3EG-M30{yK~77;+Gs{Xl_HaA7W
zv3wM5KV~6zTnbn_rO7Pmjc~%KKZCF@!34bg;+Ie}54SxQB52ucjpUC5O)*P5mqk{%
z)}e2?ut?VgqY8-)tK(oY?HSbD%OT^M<K$LdW4M0-PSp<{&vhl>*gFB9atmbDE0>U<
z7S<^58z$bq>S}InYm<|%<w&U|v{#!TjN-i)*VG;%7sIQ)FVxF98{6dF-qziVkzfO_
zUTBi1KkOf9kCQWnGsDOYg0rdeIIL)uHzl=hU*d+V%IDM)1gl*SXW@$IINyJ8mOe7T
z-*jSp9xxr!vWz&RD{WCj!{Hl$CmVWhgPROuwUHL|5aNe?aJ#hfv_@V+$2iTfjb7Ri
z@PTgQ2oxJo-ewKc!c%%L<f7r$Ft_L-HTs3`LAnQvW#>lF#sj>ZuEb3L98rHSOsN>A
zQQwr@@o=l{p)LgnJodfamM+y`qQ23HAmh(yGd1!CCppY;bD>bqMZ4~x8|Ey1gTQms
z1<WMV%K=krWxDMTIAqa%1=|!SqqtK&bL0pTMTRaHDK^myh52H@3Z-a2p)`xq#T-jD
zTC1zhkW(9qL*9e$-To@cIhg>+NC!z^&b$durX?>Cm+>i4sQ!-gO}``oycRTX<68r=
z&jyi|dIXyeXnP`0pgHH9rG7$Dn=CU>R;0v~R#}(~+N??Yhn1Mg<q@~>6U8pRV#!cD
zAT#rY-&sQ9gUn2@NL&V@QsA|lt98WQ+ZD&B&f58YeWlQ%@7L2AqBLIKBbpKX<ec$Y
zC|k*n#DZ^0?Jk^*nd`(c9Tq6{>+o)(g7LlvV<lpvEvVflp+5%^gnMnh+MvKGqd&v<
znN;l}M9B|tsqx974}CdXfG&a{RJcYNLfK_OW5~Ju#KVJ)d#^k}(wNHtr34MCcuJp6
z+z;r&B9}+Z^<{VoGL-m7PU5eea6mm?4m%#scbJrp40eJ~Nf^ziK|&h9)sW-$9?g@y
zoK%Z!W@X~aA#v%R$grglW$mVzX1%xT8wKsTbk}DbbP>#ec;Q+4@|9V6bxhEGyK2l5
zk#(N@Sea(4ODhVc?RJ3z@$WpAyCK=aA+wVPAvVj&A19ZJ?$)V5_1QyKIevJ?NQ)?K
zGhj1pgu|SC_EZ&pRIWH_qMiDuK`@E?A(uB3j+f^rt~r3ZkOd*rh|7bl#n>>VYW230
zl8l^XQS;cmPCwVDFdK+Ili38+k@S**E!!0rp+Z7|H`u}4@QWnA%YWmc@qAuu7X?YE
z0!Tn|!6HB+?x3l3tDlfm=nzP6^=b8O`;^O2+gGwjD=LbVWtS6&#R-kA2WvDT^~F!B
zbuPcM@+t%_&XoW#+<8=GI^0)vbt?*JZE}lBm{^V4AXtSbQ9g5>jWU5%9aCC9g@aT`
zV#B!`ZF&kQ#9Rpf-m9n(@%^*%XeL9cQaquzQqI7=6ECX_nBJ1fK{(1#!3Mrt5l>Nj
z=nRI67O92qvTvF>5lpZNgaC0eL$W?qIaFe=%E|a!5xNsZG@em@r&NvdwBbR-p0wHy
zt?(do-$)e$gwC9jugKk{GlQ*M*GBlU_N5nPnuS7IxDbB#fB4c(oDR8|(lNQIBEABJ
zh71ua0`ZeTbMT+j$vXy#lj-I!w*bl%74h4vmFb~QMJh`{4-X^y2+WKJ+ND3A?LY#c
zRBUJB$H+&mn%a~8iPx#3DT$bIdgt9av(56@5PKo%<!?;F|Hi#xa;S-{x=BT<>SAr>
zJcox2(t<{@(_f>y`NhJ!pNe{fL=E+e4IzwbRZEd|LXG(C(Kjd~pGw;?rP?3E4Yfmm
zMUB86hW!-yLsU_F!NmJAp$~P3En-Y3EcKt2{PBsVpfREV`m8?3T^ovq_#K?QiFM7$
z%%yHwIz}*Iu@B6=AvRQ}MAWLya5VuY#q6Kw#X{?&R-b{uRKk1z*W@Dsp^Esf)_K7q
zu_82A1(PYtj^jEGIJ#)rA0CU%%&zRXC!GqEgoVLrdG|Lt5E>PBbc^ML?d2f7wu3JH
z;gDqE!;Dqq0vo%4+p7ZLjA8xtwAM9t898mFI*n!L%KlUym^$r}`ifl1#+^iA^MYNB
zV}FDszpuA1kW9TvkNVU96mx+JQogS~7K|N>m%U=|=n0VuI}l}Q(SCVdvAcI{`*1@*
z3Is=~J>Ms{5@MH~sAE$Tm+5MOr_1l~;&XOAuj>i^KHR}+dKyga083jlZ%UCy(^&T2
za-TZ{v>n_FqOB@#!?HYKY~YA>UW;zA?X3zTMa=0B|LoUp1}}Ic^UbsDL14IVz#M^;
z%0dJuvvu0!rp$D5(^Ggd|I2F5d7KMoxKcQ`Dx}+o=oMPz!+OA;p!h1sM8EDw={&qP
zbFp~6EM+LX`uv#=l|*ZaYFW<3#SmP}L=ky2OaPY4N9?}Ecsmxa=UmTby#!`4E}0Bn
zQSFq5U^U_U4%<I`;>%$WYG{H=P_i=}>*i`&qa^1Yc)EGqg%$4U;k|L+#6gb4mZ%z#
z)Hp)I+7>t{rMN`9n#Zh|IO%3_n2>>rQ+H~*-b_q5c#~#Y)W~<0$kj-Nglc<hq(-KA
zlw-)P9*Ulz=Xmgg>euG8bp0w!@LC$6v#DB-jQJ4bZyP3v#;)6Les9$A{4JF{mAC_e
zXupxSSc_qSYB{pldIxOtT2y`*$IEM|iXloCMliEQm#aoE#Z}ApnlU($wsnaQL1@NB
zEk`auFhG{1Yw$Wg7hXO1cmDyGZ3w*co)a&My)g~$PIt{QI;nM|tV>T8x$vv}J)qUm
zWK1yPLMy5nk${72dn1Q!ISXfSDfcQKkujP&@Ivi~ya?c?V_Xkfq{ca_yd6nw{Pt@@
zZftTbUbQBLelx3RELsf00U{6G``wd|m;=N$j#9)WtMf9!QcWjN>rgAly$!zN0#}1c
zj1eAL_!&kS)5t(iZ8wR!$wWCGiJhY+d+i`k6DPq_Z?C27S<F@e*T}!VnL%nxh^FkL
zAx9;{AXmo;LeiBE^tcFAD(hV$rDDaG|I>jCg7epG;mGw~wH@Qqq((lul`7<RtQJSM
zQkZ)ptkAxo&u(-oXV8CADJsUBq*9xka<c%7@X9N%0%K7*xUw??yx&ON4e-LN@dEgj
zrIpb+4pkUbssYzP7ZaohaY0bM6<$-Rb7=V9|M;JXeSw_h<)q?B*(QOjuWgZWnI$vd
zHZ;BRnXk7)Rf>l}-9rP@)ib<p<`@abZ5x&1gpd~0fc-89OF<DDR+T@#3z84VWME69
zkzHpK=bFV`M1$#Rc~ZJeF{c31N!~7Zg17lF{wwOf2A;u5|McTu!6dM9u`m)fACzs7
z{`8m!kkT==9diZRQ86BKg`FEuUhc0_6j7BpjcB@d0$!t6o`GE0<kIzwxx^;4K3*f`
z^Z?XG-Fnp<Te!&@Nkjz?d^lB87jPT7ImbN`1Bs4RQ!D=14O88JF?{bo&(5E=H?>Mp
zAZUc%7P_(-t<$);8Qr%K+vkirT;F1v?_>8ZzR?$BSq8fV8l94_yB=`w`gSsw1e5h%
z5;OyF(WI+i;khqdFJRTh;m&E;^-ciLiPL6OI%?b^m1F8+*b6hLeIh0PrJ7-pWDA>{
zX3^A+ruecM#}(1n+jAd>Zxn8jef{NMlfCpw!#?0B>8*h%<Pcm=clT2>cQ#lkxLtG2
zz3y=8l)43G0712@;|(%9dR!t)XAk`;2OMg5%?W}Qp);v|4a(`zaSUMzI4*WAi6Wxi
zrysCXGS^IV)fo}Vyp$Eg=MJ)2@Xd?Al3{uM8c`M|IdEglZvHUXW*F*)pvN_L<HB8>
z`+%+$cuc|#uR(l?1v70D32hIR=SEg9$JvFsCf)g>rm@H?`&}aC19<(B9XBHKM-DOM
zPZJO&ly3M;t)IF?jgE$lEU*dTJoLmcSDl8!d#|2kB9U}cG2Y8u``w&0o7L(B`HN|F
z;weBYm%T6TwtgV4b#4Iu9KT4JBtwayvMSs`lNi=ohpm7Q@YvUI+}te!QYq1o@^D?;
zvd$s6e)@nt^R?z8{)Rn)oT}0YQ5cMTpW`R5v|y-pviNJ>rzG!cWL1;csqO7q!`f`>
zXz_D5^5YxrP*DzF?2m0I>yLt~`f?etotb8{Ik<W#Logv1x$-=6DP|oMNY^#1>0Fks
zSe`qmFd|>=X%b1!@$MM1PS(=g<1V$l=nwwRU-_!fKR8<t?>rx8s>e#kLKG++M{ZC{
zIM5au9L3~=l*ciY;yfoC;H=+f6Y@OG8lD&)^HTUk3&_-m*|n<`88mXihRKD?rL!c&
zaB|H)Tf)+i8Y)t4LK(pqio8Q73#^ZOn}xy;fB!2g6yt3$3N;;7O}&%^R1;h@161P1
z>n`wvu+2p8{yYjq6Iv=n_>z-JP~WY0QZ_$=+jdbdf-&J%Y0<Awtsf0`0R}LeY44@D
zwqrp!U3|7fc6>2^hu0WYbmTE-T+Dmv`~H$I*Yf_}L3JRB{8IYjp`~)A(scm9*vR$d
zZhWr3VRq}=cG^@H=!cBoY7O5|ixkBua**0X3TC`zwMlwTmdkq&=OWBnC(PZPBV=n?
zqt<u|xpB3KjElq*eVUgD%R`7|vdhiQRoq-J2UT&1MmYKF!uS8rFWne_fsQ>wF+U;?
zuS6y@=GN`m`oxZT!TQGe3jOB+*$Iu&Pqw)=Ph$#LfF<&d-06?5TP_L2we=v&h&ocL
ziS6KL)DV@Q6CLUFs^Dd@%$(B0&FH$Zw9n}7N~C)a*f75kr%sT&EvDDCt7&u?P!rG5
zA+2BS#|sx)Em}7;-s6v-%LJ$;cwLJwS&Syz%N=7(cSP22==ia7v<)6Q(VlZy3pJ+(
z>P*C>-ek}%lSVP_n=@zz;F~L4B~v4$ZbKgF9E1rh()Cq`=v=E;Q?ZUXnqp2XWE(!J
zb%L~tyGn_b^&Vk{Q5Tn<2;nZS9Q=MS7d(@b&9fnEOZvCcu2~CU<F{@bEsytOeYu5=
zcmU+h^3+PE;SOXGjZOk}-@!lI(ZFpk@NeBV7FERC@axO~t?MZUQmu8}<|<ca+%vK(
zKRpD;#>a7pfDp^~d*yO&6N_&~1DCF;+4su9-}~rm0dU%<ddQp;SHi}tcfmEA0AaUm
zabb4O<=XZwh7FJxpl3WTh6Cgg5AcE!w^C@)?YIS;O4NeM1{jL_AEpx>3=5o%8)ea+
zy_^7bu8Au0B~#`rM(*|AS{hM6pj}lrQK|P|Irzb~hn~sf23eYPk-Z>0e8O&kr|Ioj
zI9aZ}ijFJ4yt3i=2^*5uV$Evh$^!I>_>iixW)A@*qFp1GcBLK3SISuE+F{hBaq@GB
zufEy9*+se7Att{<1rfvtaP<x(=Ng5a!rZHuIM>1_cm8=s)oMY0B!?NZK;29%uEjW!
zC5Xnwq;3>}!JO1hn8*~;1kB-0*GdDKVw+bclcrgz9;1&uN^L|F8@>`Ij#$70&`yCw
z(q@CT6NC-a<y^<bGz*uVM6$0?me0-NfSNRHt(!bC3yOs@8V`ItNIOvdcZnyDutwPi
zr$oTYp5$b!OO{O?qX9Rp8R`^my8Pz2Z!K`mqs6#D%}Z%JD6Y{{xVE(k{KD-}Ub{vi
z5%{nB16(3GqU<EAXn{)<W7x47y>Or2R+V+tZbk&Uku{fDmA9nbx~)55pH%<;BZ0u7
zf}MJMNK)BMxkSJH-QcoKNP&$eU5xFTa(el#C%|j{>$8JH^H(3GVWpO(h(g0i6GFJh
z+0v&^4pSkq!XaY3!^2lkgHmXhay1%O<5d%ny4J3)xkPHT2tzo3FBU!*zik>FGP^X&
zHCx1-Ib{;By&4vVDtmu<&==ct`~YE+LL$P+RGPIUm?(Kt`C`J&*_8Ghg7M%WWlrCD
zFfcvMm1JD5qvsaX8<Z%P00@}zG~AzO0I0b#&ftJ-1H&FE#RsBJJ#}%e$%)S8gcxud
z7$h+{h+NFS;?;p}xyZGyz4EH^!+Yr;_ZQcvpS(}fW-z$7*KPSIpmZ|0?cO6*f%J8Y
zZY;G!m8Wqs9JcR|7&rxPz!EnsU21FT#2U|3a1+erS;{}dB$;6j3u*eo6kys@MonU)
zq3wZ`48iAc9Xdhzn-U%ea6^tveAeY^<QPUjXkQ8cs4)CWq44d0f)x81JVsWu+121p
zJCTdHc09rm4~PPqnm}{tCl&U>92uYYiA0zoODic%dopQVC7rBqPEr+~aHH1IhwFe4
z<jX3@AGu20B5!D>(FiDat7Y?LRg_w}<{TgH0V3s!3|^rKy}y=Z8h8=r@eDEjp^$m+
zQQ!l5K|sN-5xGpES{t?eu8-Q2?j6hOrifH;+R1RCjU>5)C5=<I&PkCr8-q6Lu30c)
zuP0fwvzdvWaPo_IZT$KWqey&o?#AxxrW)xAKxUzzXUaEb(P_lkNeL4{&*GWBuCB!<
zak@D0?Sl`8h)_sEFbr+<<PfuMpeOz)=$QDtgP*D_FeVD4m>6|K#63*g-x7qKf_|^X
zxwLoL)>bU2jIY8a_k>DT%KgdS^4#P`DPp28jjoQiS#H6*R+mV{R{CEQH8`VYO?|M*
zrs<V)_}7C3P+;=Vy|X_6>uA7-2eRy^Y7BOeM)cL!@s4h;bceYAq3O1$UxjL<<fF~t
znJh1q_h$EY>_B7>OtQRaBae4P-+dN94yZH$2fgVz*^~t|TV=<YM7bg+jcUn81?mY?
z!n!n2ISO1f5TQ}(%m4OoeU0py<lZ|V#b$|-`U?K$C<O7uU8rG}c`=wU8aL1_d@sR^
zV>W_gYPqiRo2-^#&Za;BBIvN(R{4oCf>iNmpm0hIB>|W|$C}-B*By_lzy_N>ThSaP
ziIR0<G%0h#;BVMUjr75_haM(WvDSP4@rWO*CzWJt4e3UsgLx1a0)r&uRw;Gb{lsWn
zRy{2Af+{|GhE^Wolc>v4@e$nOK$J9Dh<)NWVhq$83@gJSn{;!Nt_SK+2+ZvtF#^=K
z__#IWsy$4aXw${Tw<9L=q4PucntxTp^dKT+&#VXxXvWCz(`eluIBv!EPR7ZNg%$g~
z`zyLeMe8jOrahQ3T=7sZbL^yJ^$EZSm)Tr1dc|gNH`oeI>jlIL?c{nnqF`;^*>YVM
zP2j)Cm#q&RT4T1Tm9w%<D24-S$vC9mcXEOcuEQ;H%AB<~795m!sP%OlVEs=g30cdo
znQ`+}-gp=dg}p_xO?AtJ51j!>*xh=XEF~1G)?B^ZvBz-Xc${35+KzHUto{hk#6Z^)
zya=rj2x-f>lcEo2T$3Y~Z$#2q9l^Y5q7jIN&694)5r%T$P3Q#iVE^zt0E*9YKLjJJ
z&NvA>V_YzqEF^%j(`I5O#r?R2vqUH&ylx-?m~4mHTI?&SrAgXso`lTm5_ckm!p)vb
zn7-nAIKcQsiK`Q!3C(J4*N&#g$_#4DA-aYBO0k42lSgsjHjZfyD#|%Bn@wi@hl5{z
z*4_kr0L%6P1;$EwnE+QKXIe7vQAC62A61y4PWmH`fI=8fk4x(q10PTBn{&0NZFC^5
zPLwySdon*6R^Y?+nnLj*_0CWQCA%NFOssSv+jzhxlKoW4u4%S~f3xg1ms#ZAQi}_k
zg~8w4dpH~?d&V=$f724Dv$mQZ!bFaV@_p+|50louC2qz|g)k7z<dC)ER<4d0EduOu
zx)=>64J+Ry#JFp%F>oyXJCII#`f4VFq9NScXzH4O1oVnhys-6br;iqrF!of-k>2#y
z>ZzEM)z?r*w0iJ|f0n&@I;r%1w_hfviSKy^3SQN2%HR}hDco$SKU*^^UZ|@|MT74*
z5<zf?Jl>~KV$PI5$+|ke0^iq7Y1hy>%U#4oO{;ply*wRb4Dk`SLsv{~04AAU!icUH
z7wx$FlzmXEekZMJjSHWn=8<6^GwOr7WJyQ`>YiE_)}+?kWtv+)Zv9NdTRcBMzc+Q3
z^2y;W(a9eHuFVvI9fp2$tKI;W9=6^!7Xnos-Z843+|P3(;K{@4oos;2Ne>@AGaOPM
zR)K{dpeoE?6p@Yw_1Qpu0=`#ZW#zaTYYjB|dD_)HL|hTp9T%UfKt~l3&%+w$Dbg+a
zSlI_iUgX|M8BBnKtd(}+*;Ew=ZAzCSXxpZaqN;=b{)2z^E99{I2PUYWCGC60&r4EG
z-Anm?62C`-Ttd@c`W|H}l^%b#690%uqw^}lsX_O{ZtNFf=)qU{n&VL|`xsTa{lRB!
zYO2D_0-pzj1JgBo1Z#|Bo*cpw%ezB63cK=^tGQJF3W)Z<@xKZ-UMomh>P@3+UCcMt
zHq4*)VtauSk?N_wQuLeiIjN$!M+FuMkf15KtCQQ`5@0#$Y<=6zCg<#V+UwD^smjk7
z9zjoOn8EusvZR6ytsm8+`bbrkdTelbhkGg1YQ0kHZ_OB2vl@L(ygr+n%^H4Z7M!ww
zPAX)zcKs>*{GgCE@h(jv3wCr{@S^E&rGHA4hFe@dW-s%5|KYz?nfnEYuUFN97%4fN
z4JPeUfGes{@pbQGQ0sO#E!<@=DYxl?=_K6Lh)6k0okwLE0j5L4bg;$goJ8*^tXoY2
zAJYwv+5EbFGS4RDNx9-p^D*Hrt>u_}l(-mMI_Z{UxLP{-a^xC>C#=BxN&G^#T8k;9
zM6_$|SPH=@o%pJ8(eeFJ$n3dM^evp){mOhkkaHzya3Vx)KH{XdVJFk2WHP|qDWaL9
zc8g+g{w$+<c#H?OqmpQ$cm(C-o(El{J9UN@-bN#PNx<wvf`}L;<>s*aXr!erh4@0L
zfb6@$ic*v*CaRKC^SA%Snc=aeQ{`AgA<a^{WKO0FsZ-+qk-u@m1>eHn->N*Lxdl+F
zQlxA#n>mKhH4`&+u%100%N~<4F3)nSe;1#mo=egX{5@ZTn6CDDGU#6h*f9*b2yO=^
zfMNn4wjZ}VVG5ZKhsrt&g;U%ZLZIYQ@g~uBDZOao7YL`JrArZCjNCo2^0r`1GX+{%
z_4v}<vFkW7nh@HL8N&nZfA3%WYv7)hQ{xXQObH{P0MA5_#Cii&o%daH5#^q>@6%P_
zP4)U=y80lm)gs>LjGsd6a#R#YX+PNJ8U!VL9I>}-Ipy(l`8&Z=JV=*(ifBwUrA9<Q
zj}SJ5=O%s8+wPn?3Ve;U?Hg4-XW951`V(mwv}v>xe~Kx{2Vg%A%WhR>eG@$e*21@c
zmwpur*c^oZhy&#a8T-XW=2*Gl!hITkIS=VnOeCBj<ZMt55zpwAXu44%gJM2Lok6~J
zsv35pyu)?z@fB=*jC(1Q?J>Zg@2;l_&J3Q)RN=pXU#Q4!#-AKxa6n<#p-BB{M1tAM
z?>T0jG`pY#o7y>=H??^0pj$7xmS^)Yf_MJ(S)O5{=Y+`HR<X^XKAJ2X4UQeP6rTAR
zO=r*$jCFg9Osqgu<O2Ysy#1B&s(FSUY0Twzz}4+wVuajs$Bf!w;-iTtS4dGr4oLSJ
zSD)vKGocN>f_Y)KZBClGEl0Efq3_$T-q;}g3>X>9?WCw1H_pNqyIX8GFO>mdHvG-z
zm$}zN!qYceDbY@_kpMH|`q6-HY<v$EAmWs9BB?!&gJ7BwZY0x~$5+)E(fPE+W>RFG
z+FD8t)kYr^q0knPhtI+RU=@6VBirE{3#0C&JWaT;;lP;>lpZyas!&6r#Et)FKX_Gw
zefbLBt}yt?H+FH9FNiMX5Ap@iRKFRh<3jqbo{RBw0rx}*(YTuUJ??xFrC08+T&5?8
zr(sdxq_8?1!i;t_IO1d?n6Vwuo`P*0uTKQRFZ>U>BDf^Ca=gORioi}}L_=5eV7$K1
z(M8i4og_7({=F*oF>opAfzC^L8v;h?jBk1Xe9#<}8Xo?~YveZ<!&t)wxtv4@`0j5=
z@7dElwF%)C%U3oXbI|JC_evQ;qNyJAaL`3lZ|4_)gFLQJv?2PC8JZ^mDE^IQVd5<_
zzU{<LaFoqeKvZr08Pj}Xw5%9r&s_Bb*G3NXx|V*_8ly<i8U$S^_x;c3{65P7BR0BQ
z(Wo<v_K!$XsVH?1hVa+Vv4js!<<NAkTDm6Y0{X&o1wEZi-9*=ogSZG=GwF?hr$zq6
zZZN}~eqxcN_!0)m`9gwiP!K3lPJ(vNP2~7F#=U?$h`Q!Xmc-0Lhd^>TLrtiaYvm$e
zBK7KxzVKB8RM&gxcxi-ESR>cwDUfs#4*c|={93;STd1FE839R^hp|$d*f_BZlEME%
zfT<|JbKt)>ih7XEvpmsLmWF4T1j0;84L;XQtBz$j*Yy`CFqdI<xMz7sXzqaEXj*uq
z9AnjYoy<w=_bRO_&}OEwrj&q3ZaQ*YYT$qAl5TE^P{Qf+S~VO6>VKlcNTXNjRRNL7
z_He@KyA~ujWnRudeHaH!UV=q1LE`FjQsqv+(dC5KXF!blE18kOTlpW_4!*&Uwly0Q
zAX6w_&GT7Si2@*hWXs5<rUEe@bbir)_ca++=sG7fS3jAe!ct;g=-PI#wBx<@KH!|+
z`#(;wtHbr2$1?Doea}fy?*lN|DxF?idwi<D#u&fTpI<e>#YdWeN3|(}OpURb85(TK
z9<XfnUSa20CyFg_rUYU9PVk*P`GG15h=fM#Ari1^HFa>SREg9releZ*afZJiOoZth
zDcV465s?;?oL6hzL<J2n8smPP<K>0j);E0np6)<?aEq4VM5T6`lJuh@%;nl=X)Dy?
zbYS&6$vJ=3<#_rIeQS!E$*6A(@NQ>-RGVHN1B_Nipq62_p@2IIaw9R&uBOaSf}iCz
z*kE{AiCq}l&huxGJtUDyO*8Vtf^jqtZqh-?{DRvdkH8Z^!|;b(=_I&l8EVp>td47g
zNt+%*%kPl*{Qdt)O?(GDOQV3r4DSaZ+BYX6@)KL{SarR59i*>${C@uOTbkq@lFPw%
zJWuz!@aDGK5(99vI!w81o9KV3WsDo1oEM|MxN)SCDyaL+ymyWaQx}U_uL;8e3Gj|m
zK?3V9We37?4LJeI{i%`08sTYwyajs5=(X~BoSMjf`p&Q31i(YzeMYkM1<&1XL-ul_
zuT4Y<5+5BNiH|Z-ZaNY+-hxe)9<o@1GFnozGD<Q5;1S22@Q?gi-a@&7Iuw=nJO#F9
zbGQv4Dw{(?D19l<?~y8)ejd|5v|m<45FwFF-la=txKq>br>VCtl(pSnm<3{UT)J0$
z^e-w&Jph-F%b;;4L;j+i$G67y<6trytHTeU@!ozY`*E@n5BTACp?K2TJm<_#wz*IJ
zzU-2=I<vtHYoSD+_~ZrqxR8rgDf1bcpQp#HQAYfBv#I&Zci59REFG8bNPnh;J`RAQ
z9n2k>dNEMajRN-Fi?VJ~ANog?p3d*x{NRz(!42RC8&%Mh@&+!LpgO^nw&ZSdzivW>
zyJf>gVLMqEe>&EqER~i{SEr3i&?75BjbW1sgTmm`=~CYA-=v=SNl++xPp(`q)J?O7
zCB>#F8)w2lazs3S=UBh)jrp9vpLr>Wt;MDX7gwEI=T--byFowi*Fl*KmYd)E_x|a#
zCYe_yOTCsjdE7zPkPBP8aMa#r?a6f9dMOxZq><<vuxhTL$_j6Urz%nmsMfM4X}-2(
zIw1D(ow{cF-L?VG7wNqAJxUkg4(^)au+Ln1lrWjDl6FQs;e%VS>Dyc&)=Z-o#Fvtt
zez3vyQ7=llr%}D_-lom<Z9LhMi+34|*GdZvO?<o%-}}e^_8Iysbz=_@r-%s3uAu~}
z7SYyv(mqCAiho27Gg+wb<qNG4E?}SmU*WTzD%B$m*X5=J_qh{wx8v0yB2C@cnF_3y
zG)Kk2VWuz_yqis{y>chHjk=sPK6_NY?0l}~q31qaqV%)sR>fcmFIirh@>^F_(}I0$
zCVaf`_-oGw73Kr@T{rN<7FR;+k|o1T$u<+N%KI%GO%@Kng!G{^Z2Q*0Go!xxhc=TU
zP(H7^Nd{yv=4~U<Jhb}JL`Hxcm@I(%en6Y6&H#hPT^0R|4FX`3TG(2uiUO*$e*j*0
z`gsE4!IWzhXUKNq-eu-tQEFlsdg~R6AR*7VZQX1C_OoU@f0#}8EtoBkdmzW4QiHco
z;&;trg37!{qW__J*&ZGVHQ$f2B_W{?u^Mpt=*<N80h8nPu>+etDWek2Owf1jdF_EB
zzjRL}pyXu1+~C%<mnFkjw*r}@Y7Ig}pVbf*Ggd*~kiZ7XJKxx~%w*b#vLKTt!h7+*
z|40^Zik&MVT9w*-D1NKbyp69>M;r_V3Nc<VbWMERLfTB2$f3xLC45NzEJV7t-PEO-
z>j`t8(YXQz2u4dxwtSKxX)E|kh(cYoE^PJ!NEQaZ;6TGB%KTu>vN?(<8RC4k8L6>*
zu48dStu8%Wt)Hp2V(11A^Sl4<S3y8GLirb;kx>JLk|11}9cJNk<g>x)<h}Sb{%$`C
z;MG^AZoP82FsN2y_!6#{6@laR^W+JN(6g-kj#wfeGW<<@x`=-qypksZ^k2^ydR!C7
z+S~+SJfoItR8q*I-}9{U*ZyxAAwExM1%@QI#64{-8N~pl)dC}A3$Hy+s^BL}Y`d5L
z+h1c(e(q_%MVgMdERD`eUG`wJ6ql0zrGNdulsimBsr-q&?)}rk%XlSx%d}>x^P$W<
z;kgUR6q_4k=;B>K*$M!Sb798Pu6b(3bK7K`gJ-UcQ`X1Hbkp7e6S25;bKdwp&GO)x
zFVe3Dfb2^{Ybh#qju-SLu;}6qcT1x_#8l4j{e{0qL^~Z*;P5WkHz31b`Pq+*z9l-t
zVZ7s(g_?M10X`ONMN0Qpe_Sp-Ial)2L)pd-v8;{rCG}$;X9JKTKQZaZ>=f8{$)c6}
z!8D<h1ol%nZT4S|JC;zzEdpa&8qA|yE+#Sn0ns{yPoB}B6t9|{>+x`++DppD{5^tw
z7K5IiHcrz&hGE)$|NOvsAQl4;#m|x!Wuc+uB&93Txle=O#MaGeGk%9ytqU#Wn&a0m
z4-Ce7n1OCZ)0}CCvwS9_Fqxy{k(HgaQ&fI57h%O>@p4xmF~FKVg<wTRy48S$1+Pk>
zGRhGmpk+8Fh7D;hi_zZtTIZMLX$_ZVqB8uF*H8xQ@Hzx=NR#_`u7rOc!~gn0A0i?R
zOrJBQ5rb7=4B861A`p=P=mCj3Dzl$KCqFo>rXV;<>QQXy>iCega0{9gWN{jG+*N!c
znMeZs2cbr`^$Hin#~zm3h4ml0`utE<5r^)XtzO4|XwS2wmk0{n&ITSqAtPk=L=2P_
zahyOz8ba+_aywlH+ZmZ$KTCO15HUpS08$qVkH4fW<uu%SF4Xz5DH`8Fb|9wr_j44M
z2|&C9&y5jn`%(oL&Zg3h!^m3K|J7=RI*CgCkc$=MH9i3&{%|(yiT>`>>6%l>g)ga|
z?zXAf?95d%$Hs_@*9-)#R(sB9lnl~WPKEwGI4e#JC4xK&usyfA$xU~@rL*mW%DLU}
zCl2~afc|3PH|OBRg{YKKD!iL2{tj6u60ZPj{Y3rdw&@#FKPNNW<SCvMhg=Hj(?gJT
z!FId?s)|AB->xUvA7|D-UA~>SV}MB&V{wtVJB%q?blrsPYcqx!5r##fybt>&wjVuZ
zaa4=x(rqp|-D%OWYVVNB`&|0A_Vt_9hrGMP5aFpZ4Pj+fiS}=BBnb}he7tSWC#REl
zSsls+Aiwp-<pEv56~`%Q6H^3mIS}m}pQ3~fAFgz?|3ms7Lt7?s51?d^)d-<Lc`}ct
zOE-JvU{4jN2U}Ve0N_6!oRjCHymi!Q*Ka~#@!gAt{p+l@nRqheUp&k8sUQE})Mb(z
z<R_sr6hSa)F9f00KpkyCPHXF2JWDmBKTZpSuY70a>B|(G&^_?487hf?lkesSG=ocr
zg{#;=_4M<~O{UC``9DwPQ9HaugJ*4B5$m!FbxyT>7uuG%jmVXnP{jDcj#QM<mlN~P
zErYw3LWWdzANvC&UY93F_2ewR{~sOTsBY@IyNn9kts33!lF;QXytKD&&cfR2c{)lq
zrYf`c>B|LAC{i30d0Q)SP=E#f0$@z>2BSF4{q1b~J7h{GeK7zA<awTV<mG4GCS@^E
z>it@aKdWDgOJvB**;{p7dEF#E#*?4-CnOn+y6=gTTMji|=iaw}Lr&r_$pO2;M`Y={
zgcc77KZ#B$NXWc6qisa5ilCBQ6`c;nLd#g6E>LD`B*h$q&IYTKH3f+#QB9fYU|h0M
zk_?R@GG3tH4C-Tw9ZT~ebKJ2B<?s6jk7Yd2x4vHx3?d{$&KPjsR_(68tJF`naDIi>
zxAuX9qSN-bgoY{>rSo17Q<8hYHS~9c=OewXi*rKW4_x_Af*&VOUDg#ba$?O1<X#V5
zKK+#6lOI!*ZNQ<%lULF?K;7{QD4H54<wKPWo+F1;yiLV{)ke;$xF@UFSEP_&_1VU-
zT7-u|IC^M1meF@`7&;#B%r6!e3$acKz2ly!_>0pqjJwCOD%z?MMi59yO<WW1ZPxQL
zC&1KVcK23RP8_}k6WLZqAbvW$@+fU4f~G2epmIv5xw}`;d2vh%w)gTJ?^s!81Wax4
zWQo2<ro;~@=xtFx+b`Vq(|iK%XFKvPywOi_k{%d4ipzJ&(!D$Bdp#Tk<M%<Xhy~p%
z6yE!<Rcs&6>713SWs2EaiQ_@M=K}!=mU-SX+X=Q?p-TEUWxf%dIQ$kjCPcF0#0D9K
zMyjKH4U57<Xmbj{!Pu^^^m@<H7fPN0#bgO)Mjp9B>u`w!pcET$0&WRjOb)ugGmha4
zDL=sp`=F!Um>&I<&;xgz_x_qBzw8d~3X=Qii%UQFJpi8)AOIiRQsBsZ7--0ov`EW4
zr(sXaBKnf|<P4$G0DM0>RPZCksFgq;&(DX_C(exU#9zYXA{mb+_1Q#MVLdNn7%Zmw
zF)Dn*l|MJsIS9kWy(OBrYh`I6m+;el-J18P@3TYmm;%I7$~JPfZa~L@3L%ty`%(ZV
zwU^p*6(Td>p8j~)tD;)aJs@ddTu7d1b0YEfRabg+o@3YQ;&-K_d2YSOy0H9M+vh%w
zBLh5;jccbq2>8GFQO@jX?UWPKu7Hua#1)XQjH|(=%}4!(SiddGJiQs;>&{9gemqA3
zp!E4|3B}VU<C@@E&Q^tanV-DIJYkB#0vayno%+2I(rp^+1<!>-vXtaB_7QImz3l&S
zKG2@n=J@-#bWipjzwx6(y5!r?jWQk%q?TOcPs#^25mun8vHCesq@a-oEMQ%eI2h`?
zx)@AH3;PO)+T{_~-8#u4;i!G=on^7@FV+}Up@SgI$-9(aVk`R!h&9Ozenj5wvkgyr
z-uxFjDK#wh`_jOe`lzfwAaD9gJc6m@+}1Rgv-@{URaIRPkt0;WVIe_ZH)Uu<ouJLn
z1}6e)-1~?^Hic(j!L$2@HL6Hp3EE{>lgMFNz4BS|Rl<*ijzxjDfk8h%C#20M(19#2
zBsKK5D2I&oQcjdUvJi9u;Pa&CPsbkictS|nUoVwukP&GS7(Lcc{7I(LJGdwWu7Q>)
zpOh?r_{NZbD5Hp}0=@f;d}w5eQG64x7tAK&J2lf%{VVc=0<%gzh}L8sxWlV?4M}Z~
z>>~Q^R@zTq&!t+al<Jopp|r2jjcE_v>a8(1#fO2u6rdbj{Ic^<*6;3L^?{O}j_V6!
z_=-1CJwXTDogCTmt#|Pi3Znb-?Nmv?L43r0Gg*k&BfPsu6odug5beF*7O23rYdaFu
zYqT2Ch=6am_8}<*NfdNpZNyK|z>irOiA-v4=I7_+>q<!5|3J{=e(oxDR%}oH(ucTh
zO+xRx2qE<4@S}H`1(1yQA2uNHN7UkSb{`A)JYp(&pV1g{^GwZ>TYq`wex8<`et$M)
z96AbUkd$A?m9Qb7VW58%^2Pok`G7SABdQ3;QIS*e{16;9?eKJ}GXfzM_W2x*t90rY
zyoAT3M0$!oG?n{smCE<|n9Y3mHc#x6qwp|&@%!@XRF_GqfV7?yEs-XAbwT#pmz_#p
zU|z#{oCKk`|2V~2d-*UuAT*}J(n8K%t%#p1?g%xpGeEh14nLvNGbg2RAV~o+Xl+wL
zfgc)JJ&gyn9b2UdzPRRmg^EVvKHuVd!#>-YVlh|_+oDcX*95PA`b+#49Ff0hFCJV#
z1wFtZ7JvV*;x6)s{b&HplFkQklR7@s@y6Il4xuiJ;v%vqVD0C8$y+q&(LTs&4RxNw
zaYB(Y5RF(RoD}d696M81y+>qAY>4c#vav#b2=A*yF3?(1p-&e@ED3=3M;)Zzs<zQZ
z>bAdlVlu3(TK1Z>N5Y@_9L&2w>IiDtQLvI-{q#p)y$KS`sD~JL){uWjgO7QuQa~ln
zkSM+<P7gFC%R=~-dpN)Wcrp6I#MKSb6^WP8E2MNdO+Tk}YzxWAqCigfS1e^{MJaWU
z00SSQeVk8X06El{Ii{2frQ&oX{4b`xNR6*XHiEtc2r_P!hx(*gpbrF;=w5ECHiDN4
z-}nuWZE2v=5vkXnq+E;eDTJIdoXb1VNEA3UiVnMH5N1K->OnO#G%N;Hgq{$+2SoR-
zkD!zQYk3#FlTwfGFxFV3HFU9#BkkKg5z6BFOf2;|XZ9oM7dOMI^p!?#&5@@tpB>{%
zy<Yl)7ZT8OJUOHfRKBY8FG9f*WUC0bzW~*Q>r=`3`W{u`{!Bfs?HoqrhiZ^>2qt=5
zghp{5e$KMoBu`i1FK<BlhaBe7mEr*Poea|pIT7K#CWX+b<i~oF7qK`U%`ZDVw!u#@
z=F3G+4d1F+T}(aJ;N|VlWhobVZsIu8{(T`%YK8}*LkYzQaKU&23;}0%Uj-|LCE+#<
zD}5s#_Tzk&=hif!u+BO1L)t#T{QcnRMCF!#IFcnYbtCH=aT^+EOu?kV^@)fNBgS4N
zaB3qe7=AIuh1$dYR!MMO^G%Q8d2#;%NSKT&ThcGw_93-W-pFt-02stZ)PWXw0)^eE
zEJ&dgVnt}JA6^*%b^L~=M$y&Y7^Wi|<V3@!hu?}pgdfh8vA+;2^5EWv=y}CnI7Wd6
zKH*A5GzktM)<3pRrk>VXjvoY9miUV<K#mt~g%N<x;n3yII7BI?;?ROuH&Myo{-3|X
z2aZEg_6-J?s3BNB>XXmnuxXkE))6Al$4FWZ;Kbn@8o7qGkfqkRtD=ji0&~pq#y*6@
z&1eE4A>YnV@OC^d_bA~&Z3h_&DQHa<OQE$msoplKBSLzCXILa!X1?I0m4onQbpt_g
z$<J?5{LyxvYR3;={=qlC%w8({Pj5lU=q7nB3bxG&dHACYUET~aWBq-#!TjR^OEefL
z@H0>k_%gzapskNOaAwI^njitcf9V+WPga!E(oD@Q2>>U3eBAei>_Jm-OTK$Rs`fb(
z;C%QDHm)zVkaJO~w-)#$i6<>;?<#rErS1MnUI_o-_dUbUNH0JSN`NnWlVzxEjrwys
zpC<KpJ>9xL(p#V#&&=y#Mc6ulUXBc(CwL%}!564?f>V`?7f*3wMf0!Ky51N#V|iS-
zgW!Qd=ugQxZ~7|ZXZrr4hH-}aZD|d1&B%d{<ikDK(J{7L6)ep^IAi-yfTfzW#x}go
z6tm2YPJSL_k}02>a~yt*3#kA;dGv5Y&)sHa+>|N78YJwxpFqLva~j;}4M64W%@<!#
z%!>32jAM9ajeJunN5QM9BI&*__A>tEUWvYbF%7e}wpF{UK|*~f-q*<1{&Trx{@?!x
zP+Pv=SbO2-s`@zkP#CQ2!SvQ%-OQ8GcnIJ@Ksp*{NbHnT(?ZQTaxhdUILJP+$~oc)
zsQhvyN`qv6eFp#-=U5s8Meas09pyl?r)xOg%^FTaH0idYr8c;KI_L^-kB0GV6De2%
zyuOV__A_^Rw2S*Gh8)`b?Dzm1x&fss^Tc67o3I!k`cX7g=7r=PO*`@igQ$t{=|(*8
zrZ0+#`tH*icyqsO$S{6Jv<v-??9Zp|L|v=zj#|tGM3eE)x0L=6FP$rOQ=*`d%)Z!v
zc}Hj(Jq~o5rlRY-$LNP8spmmMZikCgBlSPLPoO!CHETOupD0lh6aG+`kq4-6gFP?u
zKLkB>I>#rbZXAk3(OSgv&S^wIk%sTH17eL&>+A$EQ#QmN_Vc<?vIMzjK7}U|YI4ll
zR_qU9pPzyg?f-ZGT)gRnq=~MUTd7p|qOH$4@jl@Vozmjva9SIGQ*8H5`Y}b0D9#i$
z)mo-33LhB*XoNM1Is3&UN&0CG^al6<q93i5!Ys<^Q#d3*Yf+++Y5SRhkTc`7#`7h}
z13Z~pfK@3*ap+ugn=ptHZNF}$e<OYSf|l(&0FIIAjIj?hAQ{fW`!UdV%V)AuGkS4m
ze(k2fjJ}M=b2<ZL>?itDgN?l>tAjDUjJfl1UCk;m_k3wab}<_Wu8=?^*ohF0Rd+H+
zq)fmc%ZU|2=I}s~I@5Dp)R7PHwYpkA%_08FN)!hFe~AO{&IB^iGA94uaZ)k)Wa>=e
zf^^Iu@ON+ZaaqRaqE!fkZ?ZDPFN#|KFsGAu?8StLC<LIjo#yG2-iv$xk7x2*U^mnO
zMJNQx*o@aNK{B}$V455Z&aZX^ozeA6^#w`124mhw%A;SPKgd}1)d^HUW*-s7IDE1v
z3s5Tuz1n6AvXl@0H;<G3XB7Df_#9xEV6tBaDyBV1(WrR|bSmf_KG5F;4vcU_Xi54T
z_DZI`j6rh=1$im(mv_m0hQKIXMACFst_Tt&KdbUcwMO?Je%BW-mI89&LMtsSHr_JA
zE~$5QUwG~J|D~@8`7Jc~04!Z94tt&W0xLM5EE6^HI>l-*6+AJ%fdvT~G*~iAoC-+9
zl4J_rQN`lEtCD@_d!~@p2Y93h1~0iaiuoz{3-zEs!mAS+|3%^&Zw;K>B*msn80;y?
zB6q+`^;Bsek+j{tzxc-j#{M(#y^5zmLuFFl(v^Ljlfz0L#76IbAM650PmQ3e7JXk-
z(0W;TV(DPkHZXbxSxU!VNPXPJ#D1q@W7^vRZ<8A$UB3<Ri8olU<oqAWsex+H1jRM~
z+8T7meoGqPB+h@%OYhy8(l!q35~Wn6k>w0&Dd5xlCcd9^p<xdSK4v>9?5h*r%`=1W
zfb814-T#lYw}Ecsy6;2>&?p(HY6FZX>=nW&n9)cc!g5T~jDx6dgBc8^Aq88ctfWjf
z-I9uurF-&fEAiW-^m#XP2N%=@2uUQ%cwyIVNSaPyS4}NP-DSG%DM>>KtjO_4)ARIl
zauUgL_bF|5BdOkfN?%_4e*b~w*iO%$cg}+(h#xb9`|<z${XZ_K2+{!uDu9dd6p++a
zBq9KAf>#Wqi$jM%m{vgSTaZty)Zsr8E^`5YNJ=4ee{&X{iNr=1Oim=_oQH;sx9?|U
zY?2R2qN@I}j)h;jKJ|G_rMm>#fhFizY|yB%oInn->;=If%u_!GroYf4SA|%X64Iy|
z9h8EmV^F^FE_RBLZYp}9f)BT_F(lx?PzEwgiqv<6jJ1#3I}(aSUNKGsLIw-)Xi!(|
zNfC9C|8a9dZ`zg`GSHolT<$0kiXm(zZP>x1kF(!x5N1)ry|L>Bu7v_3){PMh@Om5(
z-V2YoLcD;CRjm6w5!-Vn*~CNvHdYxpXn+DZBBpo(cT;^%2VSSVDr^lDV(fQO14LTw
zb)?=7*I`AHxWd-Zw)`Rp2zeM2y%4snqgzrOE$vtVBzAFhhrAz|oD{Xf?fl3Ge)%k{
z6-v|tzD|UO(cw&ym;uPhClBOxAB=yzg@M*z#Lm!all)~J##gC28({+SQXuU>o*=J*
z7I_KS;+TKp1@Mb;|GF@dwQbY31%e=3<hkY2y*Hdg$YAUY4YeG+O)-+*Ay^5Ow(BUA
zqHG14J1(Uetw<LeL@6(Ep#G}>0V!4r3<hF}O00xWe9(eQ@o9({XZxWNTript_9w=Z
zA&ST8hPZ3mf=>zv8W3hN<^$^(>I3Cp(4?4BXUiZ1DD4(^bQ<=-IEJRHqdUhG;!h{h
zjD*x8@ijc-H)t(JHDmAvu5pv{qhlceMT+Uimp7(oAGwiCLGI)i?j!pc#wwTxPr;0c
zd}2f?28J+tqM!B{Y%tP~)L1#rd)eQ96v!HqBf;DBs_amM0<8naPxd4x2ur5;8GnDQ
zjc8sdC;ce`^}sdbG6K92VumarQiG(%fy>mtP3jIg6(n~tq!pxl#v|)YkybDk4eK;J
z5ABu7g1NC-xbZY%adB1!fn~7%k8Hwbt;OSu<zpOfz;QmLIpfujxubmniDa}}XJg37
zcnINooeqnNllS6r9)JSH0>HYAMK;0fVjs?*22XW14H2RJL#O9ElLBIfjs`GlkmsMl
z+=h3d&_Q&Di`ftzlI(kXB0^_ska}nVJ&Xt*JR92Tcs1f1^6ZhLF>)4X7N36(g6|Vp
zJF=ZaWFjjaCk1{Yh!In19X)>m!PJ}JCL}@~KnN#kOnL$e6_f`T4P@I%s(aX{JSAem
zIQa@m?btUL7G3ACc+=crawIC%G~i%Sy_0+tyUq}N|C0Gk>Jj0^dVBa^f<e(*?qg&-
z(`1hRw-^cli(sQ;Ax^FU#22WL7M^$m2K0-lMt>ut9YSmjo=_|%f*7SM5dab&PDYXe
zXds=vPU;9`NgMZnz@A3oC31g25+))hG(gOU+Re4=7bG3)Md}5M{r2bw)|ZN~HE;dg
zWkTNp0n!$dy@@QpnA#{c8iw-=RNm(zb1^;?hXe#9cn9<%Kb}@QxZWy#Q$iv66yv_(
z*|#wjxX&SgvzP?|gv2`;hZrbK3Wx@?iVYpiiO>MpoDdNq$JjvGvW93UqVI7%^$jR2
zCbGAR2hu0l`~Ws563zltI6c&k&D0z4Y@VICA?--w{nccQIO7o@Gq4|_rz(a7fd^)w
zeSz0i|0c?uu*Qfa#sUoX@Qv93Zl<mAO5hmm39j|A5fpSo$YX!0lSM(lLB=esDtL4t
zPOO*;R}ePw8>>w$6Juh(2x>y!$1k9>w2R~ikfGPPx>3Hr3KAn94O;0v8pMH1B!<73
z3|tQU0rkhqCHB0~YS(`lY;!X;1S^d*$~w*f<W-DObuwKr(+(T}g@khkTXDJ;$PA`9
z2@}MxK`~Sz2uwghww^>0B7tEyTNxAa@OZB}<007%ecw^Az;v1cxTdBOK-G>(l5Utz
zQ;Hu&qbMNo&r76?NWOJ4N}*m5ks{efdXg;Z*F}kP;RrRRT5322adk@;g%XHw0(&9t
z0$G6DKw+eoaa)T-I6{Xotvm1rw#*&#iwGK;@IDd55()Cv<#KENoHj+hbIFV&emF`&
z>$e&|9aAo=A#6htwhrRl;WO|~I(Bhl-06LP^DeA5l76)~=NDoVY8;ji21Zsjfyj_x
zv8M+5!o>FnpNEk95V;88Y0PEOSF#;1hqQ1fuLX(}_hCz7%bGlD!T>;NuznPP6IqNm
z_HJ(Ynvi3pD1W{uv6bK16(lr*W&B!Pe%7Wr;4-oh*5a1I9RYCib5J@h_l5}%-G;0@
z023V~3>yRbfcb`S8ic|3zyWceg$tMl(<$zxP>KpLT1@^hO_)py63`HAEhI_6TY||H
zYaN_YI3U3PKxi>}Xl}}1m-R^uE3TjF?8*w@<hN`{DBunvo<UAUX;@OdekY#zrt7O6
zV+Ydgf{KMhz=_rjaw*2oI*~F!lLUm5+C&zge-qXq$NurPcrMtKSS*7AFbm=rqDjba
zSmfQ<Rs4i@hD;&a7Xq3v51gC@#|K^3(6)+{Kjw0iy6DWc8ykZi0>98i@N^VwQmcsI
z+hpfJI^VqhL%6<kQW=!Y_4oZ2^yNV)BzQcS4`NOD+ldDfMA0HJ9|y^mfY6f1@FJ8T
z#liNkou<rD><tEoXe=W<up`f5=8#Q*trbP$nhx`m(mHAk7+5i6mg`xSY$_DtNF=V{
zP<qlYB+h;@4oG$oy_)3i!2tL+ls{GY2_iB~cqO*2X#pUZf3QS>0GIZKj7n0ptsAS1
z;KcVpEl3HY5Iby?o6*fUX)it{6%Y-1W+*BG??ZCYM#g-Pd%<Y%t7CxX=7cD=K`*%B
zpi32am_x42j{$~LddE#0;1`nifC0u6LN$DS*CYvL8hq?1HRK}@8BqP0OJyYkGHX#>
zlL!q>Es-Bd-Y`W0T0|~r;Sp2W4IhEzE5ZO<&|#LY#~s6v6fxXJG=@C^X_oQ;IVm-a
zj2XJ)<}6U&s0<_0f|%K^`fF%z(b<uI+2EuJ(5wLiM#HH7N0AN@*^LbPcvmi0@m~kd
z{J;CifAfI_aU}$OVRezJ4<f;EFqJ_#11-vWg)oA%(@BT8=kaf`Sho_GE1=6-Em$_>
zLzC<9z1Sv0iWN8oQY?0?_r-bEAjcrPQITE%$T)1b3F0`2xpXZ3>MyW;JP)MuQ3L*v
ze*5#}Fr<+Fi2t;412FsTzq?_K(Pog1qz(fzgX<}XNzjhI1()qbSm~7G`b~=bp@+!e
z-Q7AED?T>`Vj?8T-HM5cA|F5v#l8~UxY&HTamN5KSuhn4Kr9tr=$a6~uB2lNI{jhD
zh<ST-2`d`E2&=Jo-N<ZxJ?L1}6kZZ><PZCC<TnT^AEdp&L_!<ecq6BJkaP)o(y>9g
zzl1ObNuzic&?XebAh?18W$}<9fN29`Clppc;2z?2vc*0IUsOPu#5#p?v+x%_$qj~$
zZIHLSn{U$b)WFa`C(gH_6oHY)R77bETM0kt;IJqE5$S|r^SHYNBoAVdtsCr$-GKQ;
zTL4&@Ch-CW1p+}@c%31WFy;(wANZR@61V_dPNLxqNecR&e7Ts<Z-AFb1XsQ6a&S(b
zDh;0xphx0S#fIUVKroCGvbV$9Dnd!lO-O^>QH=b?rLo<0>oA0_p$Zy5SP5GI^AYMW
z7W+OK!zD6?1>DOHmJFpZNVp$GEGbpk21k%+>xd}KnP?E|y@($XSR2QaNPS?sB-F{Y
z4MIAjSwVpj)%wT%XkvH%?WkXDI;tR~W}P<T$6%oEAhjCvgN#C=I8Fi}IZgQf1At#!
zQ0g&Sh5;d=30W7ADy_kXU^le@y8@j9(*j|Nxfh8)v2Q{>kbu_GxO|#)EQbi1*<WIZ
zF{^kJI$6^l=<-JLc2>m^TeTm<rs{BYtTSL-y;c7Kfxt^WhgK<d5=;=qBx4C(N`u9z
zSd-BFAJn#hiqNSFQE&(*3_b|y!=b1kT4@yi{_~XMgSo_@MeGQRyFo{towjicL;!A}
z+2TKXBLOP_dBPka*+e|yLg!)EP<qFau3bat)sDu-dJ;(kN`0Hfi}6zpEnKj35Hx5r
z@`lHY>w&veC#%$P2lIfYc>WS40M-jIoM~K?r>;<<I?=FCbOAe&Qfn!%jMxFw6U4OL
zouZ=<_A5+8Yy~CO;+ohR*<YeO_ZH}h41jn$aNLQ2b43;+LM<T*7Z5Q;tGr2K2tf<n
zk+Q!q8;mG^4O7<?Bs9j^WY8|LAb_<y3)c$U(LwvZ^p^-1x7-2}ygK#>DGL~j1WsVo
z;1McMM@i~&EG%3rQe+@FR8Ym6f}BCff7tj$hQ5G~q#4XZRMC%ayn(UfSyX_~qeUHD
z5Ks`AM>GWt>`j<(hpVw4SRQBz)U6{712`-WtlYf5K`C+7ST-GJU%C}q+dmuEBLWa3
zvcf+&Q&8P48Ul1NtV0w`;lCGXRQqwZHn9a#E1<#@80?g~Lpj74JeV0*pnN!19E3vP
zNeFqnF3dudpTj6XS{AA~vs>i)8)St^{9@Q16h#IRA?G!`2c6;qVxjnQ6iU%5AX}R_
z<i-EC@htH+gc|j6!YqK&cM>FGn}{rTYR3ca0G-v(#>TfW1|O#eVwj1dj0K*K{Ki;6
z681%C1w@+*2|*-C_ByeLOSxB|DM)5SQawmcEh3?RG)5+gYY`xND}O@^*=o3@)&Yb%
z-AYB=vj^A3*T>a`B(dCjENQ{tcwq+vZ&eU157|@#m!rb};qyp80%3fj6Xe2NVhM%J
zNjP+#Hy-l@)*Vg;O(NJ=A~GTd0w)n`fV+vDC{Ty<<j$cntQR}9u~|nH_4f3MHxMnA
zY>rkyCd&6fOBnpkbfY+`ef{MjaCWzf-10a`7rUe$K5>6Qwg2DqNiM<U=p0GZIo%CB
zfgK<%K^;1=PM9)A4t;<-fT@zGg2Mz|6U$@Jqk-rt(0iP1jqD^ULbrkaY^iA%V}2m&
zh)uw^Z$cIlil86JC=yU@=;}AF1vre^bQ1JFOi8c4%L`bZn2rErgy7Hb_-9%WFhe9c
zgBJlclFkOyi0ltEHbaveo)DZYA)u%gVaLiDNnYS+a(j(4t(ITJb3sA49wmoE)C_=Z
zj<HN-V@yc_z|-JjthvY(rNY4~3Y{S)JJbY{xG9$qnZ&NGpRCUZ)1Y_)x=ypWfFTyK
zWAa;f#bi{7Hwibw!GgUE>rKLi0}&B9lqi}4r9n)Md619P*R4~6Av`2hm3<sAD7X*u
zh~O%6c{|~*5+W*;J5G`SEm3e|5l!>~C_u>KmM2Gb#S5DfhZRCg5XeR@X$-NwjW0-R
zz?x`6L_t`g2MDDkk?jli#*`Y!vVP;wpMG`opkE3AU{M$XJ`8{bA{DYkF$@e31Oxn&
zQgiTqyM7jDrV-%LDpR)%WW$rA#1~z3(<7RBjnoFQ6*k1*^ALL9f=)4`6OdJq00Q24
z2NX9kC9-R!L}^_ct)LIab_Iqw31!%s5r%~=!k|cv!^enC5ywWcBw2(vW{)((p$n4g
zqR|ZCj{ii*Ag+<Liq!yAEsm@qZAO>}Y*fTZ05AZM>*Q7szJ}tGZQaOf1)xoN`ly{j
zIy)2xHn2sgY745vZ*^iSVDlSd7o=vOTnqVMgqC71=vai)0HHyoj6J!I79mbR?r=N}
zdM9%M(g7(GZGsn0wZ8FlY>_0^*V!dNSES5I`2OJ65PksUqi`YUz938CRC0Fqp(8{r
zyV_)yP}TsU^T<lYLB#1(I5#WKWyNvabiNuG4e}cPN$ey6lEk5LJ{nvR)nad6N8u3S
z4#=pEd!d=UB6cKDbP!Q~G!)5=5rT3qkb%;f3vmyLQtZrf%ZtduI*&eF)Ibb@d2C5s
z7)TCmT=;V>?w{kM=LC2kGzJPIU5+7RZ;;4BB!3>JNhgeQw2sznr;X2x?o(;XHU>@*
zmouS5Z2$!#$V|jWfY6Ad+~Mmj>Ip?`bip6>_n|<8w1|EHebAIBbhL|PH&GXyj_(Hx
zyfX`wW@8#1OFdTW>i`u?IG%=nJ`F15olD6eiEBq1+X@F;*hFN5Ll**7Ca;OS=*u*i
zct`fOVpRx%3=cLY7Xt~CWt4Rz8Jr3nbuUyYD+xo7iK%rDGNtzWHWq{UzH<xe+FeSp
zLOXCw-P}Pqc~eB^w1qZkAFKl82CPrP_qPXA;adu17Gd-1dq_xN`#O@Fst~XOIP8vr
zuin@F&a*x;i%<d+w@^nt6`<>TQNlb3(-)<rv@i7+>kmOsAOWOfzz&^1-EEpwstK)V
zavO9~ARmJqr<U07f2QR6B=TV5&|IJyQFw}JWI4epumVU?0P8#<zm474(@979MJHAe
zv%}hJ)))M9pf8y2v0)FX2O0#P$hHCEoq!DMI(qLraTufz@x>__m+&sYW3R<F5_B5|
z^ICABg?Rdn)FQG54P*aW9s-%FlK?+Mw=gu!Bfpi1Yl^JJ66{NgjzEjz4xkFSCpbM%
z(*XGbgg-##4H04L9YB<mYX`EZzrpHnP!>eJT|XrN);EzgaVF?A4d4|Vc!C*JDLXpP
zUi>auyK88}M52r40lDR&gHmUCCxgLOo$^26O$c&ivABk@xBV@qlPgOy7&%ff%rJH2
zeUK=aqBg}vWK2Pn5j28sne%7F*XKz+LdT=Hc`OS(2_(_cWVs>BW8{R?5Ou>>Ki7=J
z;7}rd)JDHA90pgv7ykr6;LB71!l>yDR3pUItxt`>rX$4|+v|uNP&A+eo<WO1T7f{|
zjYIV2TZ50+Vf7;9N!~cRH*gRMwgSDS$#=vgXcNHYt&U3$6O(2V?<ckhfl~AYDdJ>Z
zfTC30-H9PI#X^0U=sh5(_NHpA=VNvz=^L|bJR3~NtJTpyw+&vxWPtZV?I3RgJ`9NK
z7&@|i_=_9PQrkupzEMvc1^WTY!i?Z}kViq$ok0|dH6)l;9K((T2mSM3uR|B0C!dKR
zB8rH7^asE_m=LxBQ68`s2vCTk1aAz{L7il^po@b+-WQqiDEk20LukpYM!}7k&!;ZS
zK*R3PQ99sV&^bM{^A{(1IQEt|E~S_}@T$dGNG}S6%(Cx)AFWwX!a{r6Y4e4YflwX9
z8U`+OfY>h|!YrT(E|lmD(nWqxcex7oLib5D>q$_ZIi=EL5@g+A{5ZB23jW>}CA5%N
z7<2mGU>o)m$NoT(#FN29$oeP0YEnkWB_SV32)-$?kO@e+fOu|)z=qX!4UQEORy!pg
zLB|t=y~3Ucp;aa^o#X5a_ijAvcXxxt;=UThBzO(4`0NaL;|#HjAi$^iy%zg~U%TKx
z&z`HoPC;=w_2^o7H_qCMtrP@)VGqQ%dkYg-Mzp%s@k2^zsQJhM`t4I^f9h65Q5_|e
z$P120+CC^jEN_v$*b-1M1sO3JGE+3Fn`oos3~3$Y-N%=IodrkH$M`s_U*cE){1!q&
zw+Lu<+!@mrbeny_uV3&FLzSJU*0}!R_Q@ddADVA<a~2=G9plp3<&S_QsYT^IEog9`
zteXo^=^#PYai+*R5k<6U1vQ0aogkV8;Y;!ggCD^Zpc6#J!N4&zsDKV@KvF?g$-1=b
zZPMjN9>fF%e!9^y<KYpa$mW|=m3NkICA<WKx7DBxItl>WfE+;7EofSt%sJVvfainz
zgS~6;10iimOvRm6p_f5#AU@LAgs}+JL6LoO0zX+1Kb<!kLu67>`8WmQpf*Dx!4t!d
zR-v&&e;<byc@z3cEJ|j)(ncyez=#{|Oxh&PsvXpDI!$Ma#tltA`YXHz`XeI-S|dvs
zi??T4e%p83HM9>18nQMiIZi}ucMg|B2NS4bh#4pfZ+NnV{=)5AyR{E3J!`<y;J)2B
zYApeh0mW>@YC~SaT8~g?OmC2~_@wv+k%~C<Ie6afnk`nytwjSxs^^96dG%*sP_PT+
z>47kS)j{mQ9hTlVP%bbD<={|zuNr@zO*3SeP&FV7X?&=Pzd*?AIP?T33n8BZ6;lgR
z;v$@!2on|mAnws@Nr|<VRC*<Ju?!rno6@m?Nc7T2k*4yL2qpw;WPe0A{$W0)b}R*$
zOSnqK90V%9_o49TeDFe0wSOigA95N-y%8t6gJr<|0nQyI*1<CDgPq@m&pf=Ph<;`b
z<hcytxkR4ibE3^$=Ydp4pzv~2&S3T8CiCEr_!B`g#DF!4j~{5)v?>nC;m83hU;SDg
z6F_P)mg{DS7#)<(t+bFCSIGy%w38sG{nfAIh%pwYu0!!72RDujp>#pR?$~IuDWp=A
zvd1)uW1v^?PP4#HO5{HY(XG*-7C`j)EbI*hmT1Z9_%yWq5FicEXw}340+1d2>iRbn
zUqK}bEaebB1-9L{FPG%uAUY3F=5R1|A<#}3nM-SZ5VOG5voNa;#69`<ycV?4r8dGT
z2gpI7LyV#+6|94kCT|Q5%!K?I7%y~c2?CpeMkg1JV{AZSJFGyGaUnQI$G!;I9roSW
zcsgr?#6j2fPyHrU{lprjV{nlDSF+EyKxtynYe0slTiz6tn*K);q?Vb$K{}w5&T)UJ
zc*1!BhAI&zMT&^B&;WhIMmKNxLYRrNPAPMU>0d-FNdw&MXa!;c+RXSbBIH{l32Su=
zGz4F4%n`4D`)&m|Y$sq(Oo>YaFWT2`<Dl^YzkamDoKJ`<6SHV*+MO|71nLn-4FPcA
znV?^AB3dan{B!iJrqt5QILUx&m5F=l9|3ECmK?_sWQi)-H%>CR`G}~7_BA!J+#1H3
zZIPjARxztt_Jw^(PL)MeG)^0e7Y5f32S7H1N6}F4?$%VJF5S{q(ZER%@d1U<I%C6e
zD^nOYwj`7>3h?n#I!}QwO<FN*M;1>^D5&$68ng&%!{amdZqRgRwQxTU<ihs0qo_&}
z;Oh+zvPob6@%K}do<_}TZ?Fn28O-_GXG*yB+-v8N7F+$XA6y9FoKBKfM+bZk&4%&-
z(6ER0JGIFY+|hG5P{S{s67bb)O(stm)Uyc#1V7N?nLE@_U1&#21aT%qz`Ym^y(lgx
z06BOFdtz@(-wy5#j<<(NL{F`tF*9UAc=bI;DRBYq*R|Nb%|dZQiumYH?FT-*jC^no
zec+ptU4+7?lK?ps7wR#V2RkMdR!#;(V!nl)J$E_Ku+gQ(YBt_b>i-TEO>XtN0t*QW
z;shEBfm6W=Zzeg&5U_D9=IXVeDTV$RYo@D-E9=Kn0hRNmI?drhJZcDjmNm7cA%IkU
z4NDvh$tK&@SOfpWz8t(#m_~!dWkBd<p!zjOg3@6_3&bkm^<d#Zn}A{<V8A30#|jR2
z#2$01f`nM_7%vX`H{!QJO$+5yTk9G+db!uV<LDtd2tSm}Boa3myMi<Pn*J~vN8%`1
zh_yA@n8J}gjJg~_SfOVTsreA{b)SH{2p|hKo6{CG`KVDtqud1j0saDn75oSbU|Dj=
zSuU#%+JeRHhv{=bh%lrnW&-vT(ToH+&jLh5^MwEX??-&GM&}d6R%oay$~oza&-lT&
zOULTd0zguL!_HuHXVHfQoXJA*q>HUN*8n^Dh?^~+U%waR17yK??D9|#<PmWvh803&
zU<I@+=&G(!Th2+^K8!|)_+zjsF~o?xS}8E>>8)~(za$saKe_%c4z8qL_aw=Xvj!bU
z#|#VsCIs#TtCQMHx9iVM26CI|!s$zNC=YQQ`iR&&!1&@`5&2PVMM#vCw1zJS&SkW@
zFID4{eF5!|9*CU`>@H{>PM;HihaE6#6ffBun+Y$S<V#*o`_rO|E1I)<1dINT(<({k
zc-@eT7>Zqa@eJ}F4vQBdo11mPak7as!Jm(N(BhfdWyF7x&>BT2M1(^FR$Az~%9bUX
zip>vQLPa$(C3YMN)QqKv<7kkvStwf^!BQi%J|;85XX!C8N01VVXMing)l1xTHOB5p
z{}P09>~i80$u99dw|1rl;sL7CJ|?Pay-|;%%os>sL5~Pz-Qsg`Iw!p%q}&d#;NpFh
zg)W9J!**K{i?jQ-l0rw+7wkz2G*qFZB>FOGVpUe*V0JoWVl4<m>O6}y6@4la+UJ8A
zP$YIq>t)oWarQTrDny0jgA7^%i|8bTm))3EeP8iGB0<!uCm8l2g*g+zcrVM~(t2H+
z0c57Ksl#qzfQ`GUE!jjtAo%X8S>nOax3wXz`7ZgNu#CFI#xb`rFO-OmuT-vVd){`l
zuA_QIUsJ|0Qd|ZER!ynnff5E%4Vj^4WdaWik(lEJSn)!s?T1=uObS2M5_&1ERtz-O
z@Us|v5DaO`a1T?%Mc0=FRo7QVK`Ur826Ka$iWH@A{omz7^W7Q;k7iBRZ+ByyiK-eV
z#=x^UqEO*`988X2RJyk=@EE2??maRZ!nuO<y9he1n!s;W1=%&GR?>z76-E_ivA|s4
z?d?{0FM4O$U^-j#3x@*<li|wi|4DJfL`uto5pTTUgHEY<3>H1+&(4oa^!Zpn(a9CV
znkXq`Cl=Ik+z%qZ`6__&3Tk11p8mg$DVRrr9*&vCFEj#q+lyll5zK$%h3(DKXDu+H
zE9AQ3ZeK~+*a5`$V#77OHnuWj+(XB`>78SDA>eQeP$2xxo)=R9riRc&7eQCJ@so5N
zC>T@B+K>~X{90>Lme}2*J{cSfpc@K79zqLgd<wD(aKO!gUu^k%)OIuk!@6NS^3Z&q
zbx9XMrjrPv*-~oC7=Xep`G=88AbQ1A{CVf0Ot|%>f3x9@$^8HQ;>vHLcleuLy27#A
zZ+T()utM?62eo#-3X^ZXrl3)}W#{#$VoPeEi@9uK4=QZKUGAhi%o9>S!Co2ze;~MR
z+to!j&UqlXG6Qx_C>(-4=ss#_B7nRVqqZ^<L^BSuMhA?tJK&#mHBmgYwklVRlu%KJ
z=u}ldpDKx@!(EZdB}8$8mwL=YZszY?i4S~KC=ZHB=_(8QJ%LkQi`@VGIf_8BaglYk
z>=vBp=V5T0j*Wr6!2z3ww5}Ln!VeRn>oAq4CIfxk$8schXl_fo7UZ7ow(RG@0il-h
z17SlJc`1=_T`ZB3R!V7K)%{F_iaeq(CBIj=<Id2vqfzL0se{@Ceg<n-SLSp)3kAi6
z;IKeAQ}F{GM9+1wYgQE*ZBVPH1Bf-()!l;D>!%uqHxfV_i^QOOCD<fV!rYQ#qR-~;
zs-4oD&};Z&MGwR{&+IanxSVRquH|{DyhMvIg4lplO{@1lui)Z%1AV1njpF0NL|KL2
z4P*k0r|9E+&JWWD^S7kLs1OiW*>&uclUd5lDVDpYjJtZ5R-4^bO5^kz+tI=VWI``<
z7?|oAr`=s>W*Fm=CR2~~M|F`em^Kx(E6NJ{!l&OE6u}><Ed@HuW4SBPVIY79Q%+@8
z&m!AzG=kg|N<G1G(u`W))a9@(u#bn*^G4U?T6I(?j?aDZe#7mmCoOj`S6m2;YO<Wr
zovw$SdBgGXg~MM7%%=g*aH3dVT4JpC?&%&U$_AusK$nWnR}Dz#E9`;nyl<vh-T)y&
zXU%6)NnY>*)EtQcG=N=WVV@2%z|vyOYp!11G#(6U+4O+Hhx%C80DGR6Xf1PScxuuE
zrS{u{(wj$}#*pi1pib_~)m?hd9bmmI)gH)bUD}$vlc}rCs`;F(@mXV<Eg-T|g<;y;
z@X6{-<IL|cv8128_D+`4AJ>C>f;C9HWt|t(4u3c6W=0UDCwW!vY6MQ!T*Idw7mDF<
z#&=v0(9qRHSEC-zvLV=tYeMAKgjGTl`g?bYo$Nbej+N8xqkDojq?=W+llhAt?5gVa
z;winH2y%=1ety{RDnW<Us}r6m$@B`I&E-1Uc@*1@UOvq{)|jjJ35)47MtMW@lSh78
z@5LXlO9fLyrN?qnt0#mabdhq@5S>F94!%U?+n56-r6@B7l8$vu%VL(V^s>QVzz&8J
zT>+bC7Q~BhWj9nOB2PJiZ<q9f*q}K41h%>|fYpLYSCX&+7MY`LmkA5-d1CH;_i4U@
zxPzNgb#5y|khhTOY=;Jg#gmFlV%3D;N@)?FVRZ&21a$||y@+|&lTNG+z@&6Vn8pVx
zEaf|fT1)s!n9Qb~WJTo=HlmzxC>FF+d+^M!C@FO{5Xv$>w~!2xbfpTN8o7ecVx7ba
z4X7%SfZ{b1DF~Js0kscp$G>GN!_j~Y(@ZTMin594p*pQSusqm!YfM1Nxdo~98VHLh
zz2FH}km>v~H1A+TWS{*Ye(DCW<w8HQ6Cu6}p}wjc^&T~-uLbx90|?0g_l+@8Pph%5
z!K|UEY(6J+*C|GaTtW8K#kFKM%0&rmMbS(;m{|eFMMb4`K=uSlO$qf68`?3iesVFJ
z_O<1aKr!8v7U(I>CZSbLq+nLTI0!V{71bdgY^Fsnd~h6r8?Fd`w4u7=7|eK3=$;&c
z*j5xvC&|eaCp<I+asYclkkqV%K9s~R+lfq)q(+lg@rrO1qk8R=KU@tsOv{wcV0*wv
zBykpdS4v?s87EkHw_t23kdb;gz~-j{HB7>q19NA!UMCt4Dykn^(sI?vpW0G{5Hm5v
zoMUOqoTEE44j!v0s}NX-^rDfr`zQAov;g*NNtgz_(T)K9s0W%-JmF;x*hX9_$RTZ2
zD&s-XnGB*{5&4Sihf@2pT}zhpu<4^>o;p;@f&<gOn3syuA4)4RV@FO@?H7s<ipLVy
zbPToH{}&*t>;@-m@#Ox#O{WqmOZe@va?1zAzGIE8GT{lu3zX2$<N@ZP!x94tLR|YH
z8YxR3t|G@Qd?g!24JTzMpNkGj-I8V9&@upki=k#M=vm8a+m0`YQMht`lLCo)QCc1>
zBFP;HR7J_iD49+6=dRAa0<utPKe&SNB(W(1o~o|*!ivg*`k*bkY%+nOUa9kO$+E6Y
z<oKH5o-p7aCwOmN_^jM8szZ)6r8^H{++56ZQ=4k?xm-_X*~w~_UzE@(S@3f~b2-nN
zNeN>%+#D(Y{BM&);Y>;C+KfjWs#LiO%Mu1$N*f2mDG`rmgg%883=>`W>A?WECM*ow
za+R#5YmOzmUUQQI!ou{Z@&%J~z!^h{$nup{L+Pdbab<y~puG6+5&;x1cV_~yuHgu<
z7p4jD2(vw4dWs3M0*_@Kj6jhtG`K#)qOb>Yu9;^uQYx$l-eq|wK9+HxNf(!sJ5{H!
zrJ{xnps4WSv__~&A#;J2i8L8v*dn<4zC#KdLqH#kt#H7R>PQ3vABntxgOF(#lxcEu
za5>Ch6$2qQ0#k;Ou8E<o4(u7366*p^LsG%ldPb9OM$>07F=2t3@D$olSTrggbY=4I
z!#=|sn)g3>#y4BRCqZfTf#Kmr1NjS{x5&j<*`D`;C+x}@HZWZO0OD}R50rhx6*&|f
zuRmI!g28)11OpOUVG2>}M<804nf|Rz@$ZY1#p2($?_7TFv{*m&y!ZMtJ7G_kg<fBi
zd!udkT?2Q2S@aM5MxAA>WUkLHe#;s9A*_J)?*7$*wWV##Xr273hu->2rQ9c@j9y22
z|Dv<4o{xmmWe=;<(U;qg&z;n-_Wej%JaB&t*+A76GN(MH{3-s##_evy3lqVPJPUe*
z%3LtU`5xI91RVZZ%1IxU1NEx2!eqPg{3Lg)?lK>OF#xAufBy6UTQMG+pElXh^iP@1
zk1sDh_t(M8;zQlX=gX(%rKs_Em)I(Pr?%v0<c6INpXQra_UX;y;^NL`v=9x|f>XN4
ztamR-y=W!%<Hmz>o;|lt6ZJW(M~9;7<w!ck*Ztea-FpJBJ{k<!K5O`%&V%6z&KC^9
zDdEi)Z@kSj{gmB;ZG${~`jvx~!P^mr^Wd3|f5n8)wjma{q;C^@11ER28{Zs?Ucmb&
z%aqp0x-Q5Sv7~pk#XiTvdktTY$r9c0P3hz=xq0F2KF#ocEIN+cj^rD12~odSWYfvL
z@sUlKf=vcc<{5`O^0Qb&XC?jW?B@OM=;7P^OyXAiHg}cnnDa8D)mwMo?oOMPV9v9T
zi5c&r81OPzA7{4@-{ETrop^Z<_!ka_iaRuBk*lI*PP3PJv$hS9m4A>p2I|tHxobuL
z?_^!-(_6WGhK-eS&*r~2k9MxPe)b|xFllaozw=`I^J4kV>eb`otHP*%O<o?}d^}S;
zmAmcGF+d@?+!2J*bItyJ@>n~k%geH9J=kcA-PauFML7{%ahxxH!tX{a_x5$$&K+nT
zYYm>!KO#r`+@13UwKCSux~~OI>q_JCLG{C5dFTF#(LKY<>B_f#Z^QvuleV*eBS#(6
zLur_Iz`_qsF3uwP`sCu87i2D(FGrX+qCR>BQRWQ#crIXiiwI%hztezNun5TMsHQRd
z#%w)jU7JUOfHvL#;?VOV_iA*lE{2+S<_?r(0fWdLkdb2@XHjm+I!oJ^1~i(BtftH*
zYt^Q8EIKJSVMb@Q%vF|u5mUt-XAxaHyJdHjc)u7qe^z5I7A5&&Rm)u4^Q#3NbnGUB
z3dII8ZcP|tO*6Amxq?Q<In3>t@GhD!H-&27VXN^@DI;<rT^TzcPvD5eX=f)n2V_5i
z^N<5=ygGQw+I=VTfh_Ud$Nb#7vtM5Dv3hkOGcMNN8Ikho&Bypc4$rZ6KQT)qr{N!$
zZZ3J2*5gi$@fo3Io=Cg2R-^s`{IC)Ktfte*m#lr&@Y=)oC^iw?9ft?J)R@(?oaQ_F
z4@{>E&mKr%@a&{8meQHgr_B-h6@d$pq|l=RctW6#o_V!i2aZpR1lpqa6SAh!*3`!Y
zw!ko^#G&Y<dw-BS6jkO$F49+oCZ?t3RJ17ficCZfo|Ick|B-Q$7TMBr5yuxuZNjO6
zC(HM>2SFm&W&Iv|_Y-M<5KA{I2bb^M#uhB4vW5941SWDq3_fZ7;NNaU<lbNQ^%*Y^
zmAn^>$R2Tqx!T7+LOhY!)AXNVM*!CXq6ZRzsSMA12(v=<Pp7fa%K0WR`v_3vR72oU
z5gg~t_e*E#mg3N|g^<vX0!JTf4>fPe;G82NA^n;-v0grHEnwA0Fp0h?)Nxw+V@+vU
z^j2}2@+EmFzz)+CYMbNtW_m%&oDL$!jIoG-_T`dwvi+3IUEA4s(D)yF{Ne9NH&QFX
z=3%u`TgGAF6@BU5ME16+EGyszB>B8zshLqpsvKBgqQcb5WgO%(B1;<Vkq70n45LRy
zZqC`4mW2y-m<?cnNC(cFGZQr{GMi6ZXlHrnf^<SDm-=gc!kH0Kc1~cl&xmFX^!}p6
zstwvukY~3nY$q^u$$GI08hho{jrNXbJ=?wJdAIp>_q#jiy+Zu;bQ-@nFe-^T7q5E3
zZT?6TSE`k3USJmVxp=){SdRIr3oXP9DmV#9s~oM5`8rZ{G85HrN-J{&Dbp9xFLB6z
z*6~(^ldMaPSDd8MR2C%csxt6;T6rz2DaA1mFXd<{l*B<_f=kjM&?`cm5DVLpO(?<q
zIQL@N`qRO8Et?**dk{&pdu-Ld-OYRjYl?N`ApDbyFI#Hi6;GqJEqvEf3Fo8dOjSH~
z&>um3{DDAysT8OcL<wJN;|M;ej1ieJwfd}#6n@YVSuOQ?<WppA6-zKQ8Dw8U&d-8A
z9)z<ZQcA&M-%CEWd&KWiNBjuQW7mW;;=2ph;N4=u+V5()Ydt-RQci!u_84q%Ba?)!
z(gS;0DdjyjVkx#wF@D%+Q$9~-wL-&7!6fdwfJQQfQ`U&6*m}O(hirR6Lh>?U<hL<+
z*G#!>U0Ja7%*#REW*LU`H<*ZN^%%@3MAVJ^bo#hlFqzu}U?fnvpG_zZ9+p(D?09^f
zXN5ZtcthIisylp$1G|xGs1_~+KqG8b1fJjk9u#GYdvMu=ybbna#IU(+8zgP+(pp|z
zjMfCc1j}1;FI>;a(o2m!cyk<UO)ThsQM1mYk1Q57bO+$W@gxke9)YJy2S%ER;L>$p
zyZY1d!T(x(kNtjj%>7@Ae_-!C%D!{g85in#{(<HhccOf}@`axNIEmwgD!=VKi~s-R
zo4;L$lD@F}&(1<i*ME}#@1vxrub;T@Jv-jdPP*5p@U)%RnRp<7W+;BlQ#T&t+<44W
zOI=+Te(x`EJDzgp?6c0Lwd*HvQ~Z>8DD;$l7|YL}A~2YtcrebFarfBuiuF4*mVdPi
zR=}SW@!y*t@-Ga<{p9p<@j%ZR_kNm@^W{e#={)5ADjsrs?tcC!_x-C~Pt!xZ;iog(
z#7~@MtjS6DAEyos|KmsQvb`PNK`XV#Pwq(Wh(?!2tOxa^sn{cy*pci(5Nv`YIt61m
zrIn5t8bD}1I2P>XDIdmts$}@8@1}el7J5+NSAu>Cn@_`6DT+%ey$<j}4v+#a<%1%4
z$Y{^w68E@>Qr|%zHXr8obAf?6(?A^&r8(mh*DwDSJ`HyB%@<kT|FaiF8@<L|;J$c)
z+28W=zf^kXSP-N(S3F-Lcsg!Ye9b(d!<h=x4Yt^WT;P15o4P4@!HFih5C!94P#*Fb
zQ>$RmZq7wrE2x=h7I;Q|6A#zzwIQ=<xF_Amn5gHCnQp(7aDigyt9RN_R=3xTV*f62
zkCSWf0?{I;N+K1u_QPmGE;zFMw3!dJoNShBOA)INHS$}p{dPGtefZf0j8I8+Pm1gS
zyg#N?XPFMDTL1-3X;v19o$AB6)C!kn0$k4@Vc_XvT9p<~3AGA`J!QIkAu5jw#4FPe
z83<4WmDjw>5$~6ZTTNIvh16-B%E4nQCT0w!>}twRr##_?i6~>W9em~&c5H^TYw~43
zrOmKaUFn4hN+>0-BBz2SQ!Hsxic1;0t2~dS;8o@pTGAh1<AS+a@OK28x+Pu3>gUgy
zntu<=rt?Nh1ss8(kbW`Xi#sea4nmr-^92~qN;c;@i#^sHa0y34U~VB|(rP$3lJ;50
zy!Kzd652*Gz37^r?pBgEHqI6hJF^+lW2$D)?68R}%|z{Rb1w(h!5x7z)FEHpR`-3;
z(*1&+$fq>Sw`k27_Sy_{i%Wd3e9&kc#k8C?s-BHtK-W=bPeh0oI%3)hEi>Y-6D2G*
zQ?JiP*-_A`Bd0HUJyL7xc`MaF&&qNrc@b9p9Un}lXTO=QrUPIqfan1t0oGuFnb_gj
z2Z;f=30D#@83?mTTGth#3k*_rMIxIlpdYJNwG!D4!U0w%{fg~sk=5l-y2x%tOgIrH
zdY$aEB9U_XY-Z^eOBtF2<)MSGfCCletM??f+J|4Rx|!hKXg=*%k}pLG(PgEB(j5CB
z=eO(S!}gxfrrQBX{B}JX<h#b#Y6)vx?yb6hamA47Zq_ndt2ob~>IU@$)+*{ZDlH+!
z+FkZh(KNeSM$tp(q8X#2>eZLUQ|5UOP?9C0UI02umrPFUS<lY1?M~W|$tWX(*9{rv
zG=~AJx2EP<G^Z@^q3gr{dfa4pn8pQ>X2~7wyH4VEW-re$lN|+W8Ev1aKJufq(HJW*
zIj8rS=_C%<a7*~CX#nS4jw{TBQc-7|qAtxf^trN1&XTU@hq!)JNGsx;r(X+r8k92&
zI3Av1Wncv)KAT^)9q`XC947zR&f`}9K5TTcdR4dYa?<^FF8zrhT+_ovUH41L{%7Xb
z+0HGj^7?s8NvDA4fcaXA+m+N=D)20qZA~gXt82ZwTSXFzgytE-R$^e;2xmb8%|nnc
zOgPfYnkEOZxuBQRs+F2|vV9JNN>;LmOkf15q$MD$EJb;cSpdz$BwNty(4;cotD_ZU
zgSloQshB;99u?}-MC@v^r+1WBHx@KNF<E?$QcmzL%`Z<3ffiCu5_q3t4Ix@_9{`9j
zX{7?8`4)EykZTICj0MwifY&IITQ%1QI0Z1LF)P~z6rwOIrH0VH`c74MKb-qzn?N9Q
z2Xp##CKl25#c`EdBD+a1$N_&axgD}fxG*)GFl}ojx&W-ZN(jM#DW%vJ%nkNF;!m!E
zh>N9Tbts+_I$V!{g+{&oika2b1*n(MQvt)U!u7w-D0<2Pd#Oq&RB7|<FXJ)0mJJ5U
zvnO!mfTu*@=YonTlS*0zziwr*5-zY+ZPft(6%JQ{{4`_<!RRCuf&@8knak+Q8C{XG
zU&*>!DjE6qgDh!<&Mm6a0#@_VPdAF<n6=l&^LA*;4C2o=PtAH@XnZ9h@n8xmg7by~
zI}=TC&LE)URw1E<;v%69C~SJZfq9PwYi`P*@DxQ}vzu2P!po<@s9<I6cJBZ_VS!tK
zn6fzVJb3rfy_!j(4{ecR<5Iime1~gBq|AnDueZ)4u}dxnh^mA@=MY9^J~AO7+Yr((
zV3CrTFjIhPHFS&uLWU{NFli=1U&>>EyOgk&J}^1%az5^wm}eH)BOViO&L)&EZT}?~
zs@C*<Wh&Bob~F(|r~JKLyB<d*hVyRC9M%*7sxl`TJH_WnhJ}c|!K6mKsURS)m6VUE
zy4elnV_>nYLQ_w*^%>FQ9*z`Ic!!dmWgH>MB^^{j)_|g4`Tk!iCXiKm*cPj>0P6?K
z<My7U*&6`$3=lKlQd8$bRbbUqs>BW>ype7ba0n;FOtNfJDRI7tC{xJ=xC}ENS|64o
zNT38P++i>c5%Da@h8}L{-MKRvCbBXu5_Qsa&j0lX3an!#)$j7G2((@)fGZ+Ms-&<z
z@TsFP$;Avb7}idct5Qcu6t;yJ(wd4Mg_~ue+fdnv;MwE?$MQu!TQFxFhlN<#q$2Z5
z7D%^}+3e>M;1`OFUnw0bI0u&$TM>RC5h$61mNEh_n=fV)QyT7zvWd>}!FI(oT@vi7
zl4Yu|_&b4FZjuatvd(?bGH^w)-2yhmCKhG+CR|T1KMNQclTdrb4?e$TD(My+b-SVV
z$|)^~A~Oq!yb-ORbZj<h6#Ci$wD1?%0@m1R=A#IZZd9I-$6Q$j=OAH|XA?kAizZX$
zGoV}m4?G0Z!bWJ&PWzA+3_hY|p)xL6c3?D0bEi$fwgtEpGuN})PW52vS4?;TrU!`k
zlPYm_;gA@K3doj&I8Sg7%mr^KOke|}kg1q>anc2uMqmVNfS>Z0S+)wN1))>2?Z&x<
z-GyY$JLAwVnFvgQXtUk~9uANkD**JBrL_Mr)EoVuru&>22<ij=9`Vqgrl^UA*FG_f
zPMGzFBS3k`F7~Pqub&(H1LKLmWnXL`bLtPTujtF&x3`A@$5rKSDa&nRs==n@L=`!o
z&(A+M8I<K@8)2GJ5lL1v`!M=7y@c$eQogZ|Pf17SyN9+ri^$$J`x@_;bIOc-zs&x5
z^O7geIho&Ez8qEWk8*ONCTwL~nx9$H_eN7r!pZSy$z00x+u$o$OhfKi_r7nW9`X)2
zT_4{icCd$oM+O(G`Ji@&UA8AHe;oX}Z0mALo*!;MrIyW0@{7Ux_C}OBH3sQ7*DLG4
z6IHk7>(8%=j1yo_tBr2?{G;;xA}hZfAX{KATA3?GD>nbSSY#!sHTLqMmxXJbF@gbO
zt(<(CH}&cyN4#oP)}JzUnXlH?9ILi8CmXjrcZmsC*xQ^TchbptOtXt~>@n*Jvp+wV
z-83ienskR;<Mo%1hhvrpOz(Ej6P54pwEYXR8F-b3yu-15Y{57`zP>)rs{<~pV>i47
zegZz?G>^t3*xo3Zi4fW=YUluqO9_HC5S7X}8fai4jmwaTgKT;9DFcLR!etfg7$=Mt
zm!=KPik-?u4tEl787p$+_6=4x4PC??CMp1BiwS2p^231gxZ#BBrhnpYxu<I|@9|SF
z-}2CXiR0|I4~lvAhw|?(8?Uqc7ytPDZ3j=9N8Cqw&y(r*8R~<NH_-4)uU!^*d%U(-
zQbf(U>NqDF7~XG*T)=-A1mco;#Q%;D2V82?TSM)!YSWrdN42KKrXK|+#O@J*z5cox
zbuIR}U$#e^!z;^wt}mxwY&*%Qa@nh0t3MuD(|7KBbP8_&d}G&&ML1>muDn%0@WLHV
zz&}_2A0o<mpY>PlKi3Ce`Em1Uy_P67&3);bhWpZW0Kju~jO=r>*-I_)I%D6w^kL(5
z*DZW^&+F+?eX3dd_`8E^Yis&4@6PMO!^|pU4Rrcm_QT6{RG>x?P)>kggEndt{F0NN
zZ0`>UK&d;<EL3`rwtG8JDr?Hoa>=4LZ9*&6<<j;FVs*Ll%fKX`zSFH}*0JiKm~&2u
zy=^@2<iwFF`?TX7*yEJF1BV}E7o1>c@`U)R&Fo{%y<SSqHSatzKe%k^C+4HvXPwK{
zMDE(Ve?5E2x6iPN#q9&$h}eJl^;^>V2?-#WNALa`thEyy2fT^*b#FPz*W6(>I#COd
zIJaeCRyi46gJjDjA{x71M6zIFZvY@KM6Ix^Ej+5^B21#cwuqUG0K_yGq^`@_(w$}C
z$WzPPQ8aa3Ea#FH%{eInf?Js%4t>nOl4mFHzd9wH>LKS-_Otm{oiX1;{f^vm###by
z_f=cDwYlF*DhuY%Cu1FIFIac{?mN*3zzJSDeA=^B`+xlp9s_!|oPIAKZW`Ozd-;1L
zyTUoZZJu8Aseh0+tUmS>!H>YUk5IW@m~IK2F-#SE3+X5#U^_IMmR<uo3SbgMhSam&
zPu$`IuVXkryO!aY%f2P1zt{#YS!r6<H`j30?mi<5uZhNqXglH<^%GIgtI<Ey>$gcW
zbEJM|iY48lX8NU1H){Zga{4kB$d%!oJi)J=dm=k(2bH7U|Kz%0_2vhj^!4MYWAH22
zIX`#GuUtqw+LfVd(90fO_7~6sXP1hC0_Cwq2{#tdAr+Hol>lAY81eZ<ZZ;(#W#wXk
zIp|331f!rPu4xrSb9-S~X835ZFVgFa@~g|>+v-tUBxoM>BSOtRk=`3D^bzh4Fn<YH
z+{N+}@>51~Dj2Zzi{4UtM*bTQ%6Tz8sK#$rRl67@*uB1o!m}eTS1XV030TDe%W!S@
z3|pkNuGw2qTQ+YLuFIOYAW@f_>CwuF)yPa5yA5OzIW<{=6fYu^l5$^)2vIIe*jQP7
zpGnk^(VjcP96I!OR3ZQm5<<<Mvt$Bky~fxd&6&ApokLDf)11EZM5KUpBNrPe_gUZt
z1dNi|rSxN)a!YqUwkbT+R{r_NoA$3=_5C1&0>@!+vhu!z%cv#+7i32JY<)WYtE^9d
z(5-@Wj=(v&EStV^uC8V_jR1K^UTlWP<bx$R0m8|g7Hxs(ldBPq2@7Ixkc*CpgMKbq
zYRcW);n5`)mKLzKpyLs_-+MX@B-^?s8-r>A8)u#5um0#`pEiNV|KrqD&$WEMg8$9R
zWqEySYP)p_Xsh;2bR9gRWM3s(jnViQL=HhAg12+m>i_;C$9%S{8UB#V6CXL^E~X2M
zHYW2v1DV3_<=q1B?gzU;8Sg!AT#+)^4m=Ub+Rr#<Lg7Yc`>b#?2?>N2h5qVGf%c3+
zRIs%Dp1P0sp<vm{mGffvQlER!Nxe3_WM$9~W#?f;L4LMu@7{2{o{J8g-y2xZ7-J=e
zeG3GF^5Mfrr<Sdg(SgICI(9(rpB(%2LVBMBzH2`KFxgra;j?1QU$FMcvIgl=m;RMM
ztF30dK;M<VPiL;ty(6)Qm)-l!?c9C2U+}ek=?7W6qR3Q|Q2CeS2Bq+jKyst6^1%z9
z%7L_$;5=B4;FeQHR)dwcf8VLVtFO%4d8KCx-$%(3oLw!8E-36)N15`H*3>#|uqlfr
z0jZ`gSkC5xy*ZMO15*i!5ze*OKRPaLG>dAn8NVPW*>JLYIaa|nRaBiVF9o}V3(Y*v
zYql?)7^#NlH5}A4hAWW@_yhj7LYlXZf2h2bFg+((9w@AWk3=jUu(bwHAsOpj4$nU;
ztqle?Jjr_mq^qu%G<X0|3|*@6$I-a^UyEPzuh|68?gOw2c=kV@aX;68A-Fy@{0GKe
zKrxRU0u)N{>|1fw4m$g~+d*gFz*T>a&JxHg9&m1=v;QA()#BSB-VfbCir@N>pWXy#
zZ;!!Q!ixzg{xg@tx<AREabJzD#`v&H(JTUt2kxTzc<*`Be7=bJJn|--_;2EeI8W|~
zVd4YRF*=Jin6~fSI0Yoq^_NGif@Y5_rC{C{l7IvN)h2;@jQ~M_m&x>!$>Tr39oKNa
zAG|JdBH#ikZVAi*I)g;&`~;{h{h8!kbp9wXv~f9h6o2VQm8<PyeD#~(JbVK`>@6>H
zSUN8_29R`b|Gjhb*AM*rp-3CN5cL7DDzHPm);BEnTwWXt#w(ofO1ssbvGU^YyS2aN
z@<}lla`<u_sH58jj1IYuc~nHsGK**DSjxeHAG)>bM2b~rm)$wr-^*DQIfAOio<HQe
z!1<hBr=ad!HcQ;BT08ac1Qu|i?df?qPE$^_0jO+Wefyl<vnI{1hHh>5Sk$ktTDzTR
z?X6cI`(!G4IHkj&6+LSV_~)_oE>pdiO&h#7ZSaxZ<-=(kBwPUQi8Q4dHe-|$UEP}S
zMMXu`2asA0z7Evvq^o;Xz_gAZE*e$rQz;Pwm)U@>AV|N0bG|pSP(75;XKbY2Df%`E
zp9$L(T1ngLN%$9^d>6`n_$bF7XODV;9FS{D%1jT}?w4LFkY^h`m0dl3x-@{lBnnzp
zYw!@wFr3IV*HKrM=*2?8wa}HKry`frc`m`>&hhAFk#yNm8t6qqEtN+D81`e<P;w!Y
zO%`wI7tb`3Gx|M_<L<y3U6Oh~>oMo7LFUctN+}op(ihHeR0KDCb8BL?X!i!9;ITxS
z@w&k-@I`(L#0d_L*FsOzce18Q@YdjDfV?C=lt{@)OTlNmWUku|M=E7FtZsAA^CC*O
zS$2&%;RFXtkOdALCJ=RUmh#A8YjDYB;a~)mk6=TQ7LJv)y0nZnXJwMefcewon^AEw
z!tJ$@^|e)<jj(d!u+Z()XR+(42C}}>>vD(1(?@k=xoXN?j_E#RIB9W9-q_i2TwGGz
z$hziPm>%=|I;EZVI~=Kp%nF2VIdF9`+^l8ljtNg%mm9*wf?n{Gq5BRyuPgO(WN}N=
zyJX*}p@*8Cy~VmZ@Or^?1D1ZTerx*of{$3c`o@IOH5PqDZ=}1Dw+AoWB95iYN778Y
zot@G$TE!|l=9*JB=K%YTujT#c`s(iU{mxo3oo7{5_seN%-trCm*5b|<+quH530~8U
zrp|JG$Tn#^4h$mG>FuwZk*7K`vY673GE*Kk^>J^PxmAu$BDf<mx;Sd*f!G}m^7Rc{
zp^%t`U>k(~9Y1@go=1g-`|Eyh=D5DAkL@_Bf1G!1KCW-=OCNJt&loR%UcWprVIo3Y
zZJN(aEtxL~BwV<k$O(t_>-r=032Y+UX6Nm}$!HphYh9V(jBhRKL+NNk6`4nlJMOW&
znx?4o1j}1pPLiV%Hi~BR&Kw|QYt69ydg7_%jQ?Q2n(G4?XwT^NId;OjOYMm~tBg6`
zx;Cxn-OQ_Q6g}-YU)Tnhp9A(lrGdgl7F3?nmw0&*UP+>#-PYqQm^NrZ>jj&zuETKr
z?iz54u2x1mh?#W#aZ6EF?Oq3ny3hrLCb)?aZnza$)2f?2>Zr=Nr;I_GIbCgQr&{M$
zb%SLA%>?$4{K;Rc*(9u0!!9r@{aJn31@O*C(Vv4?l7%@Y$2oyAb&0e?U71qx2}prM
zs3!?N(ZfUhB1cxNRob9i<E~O))FB2GL=E)p27=b>6JVhkz2HgLN%X)#1Gtg2!QNeU
zuB$~r2IJQB6CtqSv^rQ*k=UHk#@#~XCZKMWTfnqox8@^THkYXQ5r^o(cv31Kaa<5~
z)zuCupGi2FGf;<QK}L`Y&IX1i@s7^0Ff;_kdB#sFG%Ric)FBk8kmO39@kpkBu&Abl
zpdpWApbC=cR<Vfg65mQ4tn4b_N&E_;CWWAdBXlIktu7%Nq%ahh0RzR*D34d)%j?My
zkz52qvJp@u3x6C|NFuv$2;VBTi3r<lXAVU@fa9-z_T$*-!OcdmE4tFZBVKY62ly)r
zvw<OpXMm6eLK#ka3hYgukFsgG=`*^<atXZ`u_a8_uP5!Dz!rUlyP*d}!2%H}1wyRr
z5Im69R?0{g4x19gP%O%<R+ODy?vPZz^#1^T57WS%LsP3IwrlTYg*9Ye1c`weuJpLx
zZW7`qL(IYqM{S^_kYzbjSEX)-huqb!AvXsl0r96eKmfxYK;dCBi@e-0!NVofaZv71
z0Qn`NS~81|4JR=Koi6=-`v*^LRJzo%JrH<aI`dk7ASkzk>EM>bVmlCWX`mQe4N|$f
zxiJWGbpevm0lhk6mH8q!n=c3txM4E8DVubV;c69BcNMBu7Yk$`gggPt0Fa0~EW{$f
zPX$a9q^L+Zk+mndsdO35#njP%+Gs1=6Nb5is|1naG6k9U;igm{I+NHKdT2Vca@<07
z5dx>M93+B-D$-${Ri|zq@~oXcM0m%30DVzHFv@lWhz*y4G@$arBqUlSF)Gc>0;&G?
z=0HiK1j1xIYi=wgQ(luH{j)(q5bQIaRra*;sECa+l~txh3^;v4*|iB`9FKPfQF;bI
z9&3$i0Oo_<0T_o^W-Ps;AS|*|3w71UKJXq7DGB(+U;W`PA?k_f*cNw}(Si&Xrc%}l
z5yBjpBBG=P#J9<~s<}wxV0BH}MIDg^)(hYtY4D(b6hA>O`PomFeGpPMLC`SR2PEYv
z?gC>wwiE&*aMG+BJGEdc&*&Q5$m%aC*#SSRa_DBIW|~{PQ*NSLGrZX_QGi~BMI9k1
ztFR|k-m9njoveN#*u2Jlwo{vtJA-*EwR3|dl##%}y3*Fh+lz6BX3`ClHkK$Z=z<lJ
zS+~MxqXfb_SJQ|h7n4{1^Osi*-BYR?2Q}YIM}hZX`m&s00dgUig*_ISxK%ETtg2KK
zyD%D?i4lR^a-}~D_U&rxS%iB*5DKE2ptU4+3F~FLNEZOVL3Gf{N48>txOXKXUv_Cj
z(i6$3w_*M1>13(TsD5$mEAFG|yeqbOW50TQdhJ%Hda8SxPj{Dt#x0LrllpP}_$|V`
z&Dg%9vDLgCMbccHvTvU(w;I`5XP1ZG59_sRvHQZV;JowHtGu1x=CFHY=Cf1MT<kIT
zJN(t6wo@NlE+2{<*Kwy!t821o>HRIlEUz-VZt+DkJi-M2>u0{zHJ`UKo((t4*%?h>
zZQM^g)y>DeoR*q2t(<(WA7Z*|((OOI?diMn);7Do?tEChBXy|twSlp389yA@|HCte
z@&3OEo(iV<6Ms3hvc5Qf>yF3G+1WDd8~b>(a?8d$PX`|ghSSMEwgK_Zuts&g!Rn2H
zUDnH!j%zd>zMs#redXL~%lVqoj*#xtcw&3Mb=QA!4>;52v<|(r^OX7At2|k-%|%{(
zTDNkpxa3+BF2kDmNW_N1)a9#QqLlnhWG4NZ>0UFMz0TB8XTWLc$K3LV@^@L2&p$o!
z$0&>W(4nEJ=3;Fk*uV81`YyPQaMK9Go!>Kz?9?V@&c^S+ReKQd_t2do*edZud!D_t
zv}}uVLf=W*vt=G$f_rNn;+zs&p?>#r-bB;3I=*!WqgNx8Bq8h15TDB<q_xfAQO+Ed
z4%!1m$UVU=Facp9^AMcl^h1|ak48(#N~&2v%aCe=1lf#(FEU5V`1xZ<kiGVeJbZt5
zXc$0e<@@~)>F9Knxz#|<>900_=f~+M`;M*L$}%5ddw#^^>nwAoR=+y0dp`0K^^-!X
zI5)#W2NCVKQ+ZnUT+QcyOWao5F)HgT(Te3+NObiw=E@TA8242#`A3<lC9Arozh)Hz
zd(j#i^>;sU=er-WeL#w@3t@GA7A>}()i++T?ab*qP}w_=GyfUqkUO|+?LN>R-1&rM
z)0g*6>^)>u?`uC0G%b72&usg)LxpR$z55^LVZXg3e;SF~tm(dO#sim~&$8=se$cr3
zvyWVyxVm@mhYkCPap0rf>e=sq^sqs|;~ma`o>}8}&tt<Tm_DNS*ydHw>uIKIM*)LR
zINO)4iWBtf$D(Oz-bPTOp}!){F)Npho?c3KeKuNhG85*Lf9GvJ*)xIA*4~L_U{Jo|
zx}AK{%q;-7M(eQc0nQ=-z55@!yIo{9EFhV*XUQ5oXj!{&G4w<HY(B~*-JEqm4gw9e
z(DT-MzkOwX{wI<p_odCA=<2)-U-`>-9e%(EidAWM|Ehf_a$-Mdf5=Ds(8#;(-6Pfa
zIgfiI96rW}aZ~2Va3(n|zjCTan3s_-&rd!zYMIBKX}Kdho&TI1wh~igR=6f}PwSMb
z*IdHBX3X2HRk@ulZAa!bhW4_bUbc=q*n?Yk--p!H(R#K#T3-Niltt?BLi%jCn(H@^
zFMHq=?i}%V^ur#|pJnOSqv*CfD@-g|_TN5k>H3qqtt+DIg&Oi6)4wLo-B;%u*=xV?
z-PCKl&Ug>8eD`npX>s<S_U`#LA1RN+&C!>hS}Cg)_I2*K|Hz}-7Ep&)SZ{m!uIuaT
zw*f0{u0)z;pNRCzg&$vb(4$KNg4HRjn#smehK`@Q&6<(hS1b$2-;O9k@~jIi-F4%{
zSAb-dPx!zX+k<vu1WD@Xm-4c7)tm<`Zz)~**PqTM?LlLy|M1{DwlV*K$rUh%zt^)W
zAAfqU$Bt(zD^~J&?eIeXHse$8AiP`*ifh07f$V7C2aqj(YV@PS>e+|=4|?cbJbWsx
zKQ589IwpZrqx)~OiR{NcF1Ytz)bg)IJ<E1w1zJ#qqw*9Jm-x#~HgD--UxayR&3H0B
zN&f}Rs6Ugq?f+%$eW2So&U?|_CE~!Un_!1acnQ%oX0RX!ASnuv?7(XNV3(i-(UL{b
zip#idLc+33J9)L`<hE*hdV(1&s09g0BrQ91k|qR1DUhz?TC9>Px#<f@D+%NJCYF-+
zDS4--mh84}Zr+K+xH(E*-|hP?9pCz<>1kmZAOR5AnfYes`+nc=`wgoEOTYt%b349^
zD+cNL8Lw2x1FK9jJ-85qSAr-%n`^*G7g%H<r$G|vwbyutRPu{c49Iio68g(03C~Rh
z`DdS+G8_7_JP5Y8-o8x!OZ<R1d?mKs9`<^T6W}l&b$Vb?xAGpnl235Z(dRP*J~O#@
ze=A`AL!i+UxxikoB8&%vGp2qs{~W37hu188!KB;Rh7~10pdE=&_HqKt)edY9ZWhxj
zZv+mP!3S5r4vuo62Fh;^Di4ae%LXw+<)Hu_&RGl(?$;+c{?eY>H2flE!_5U9YFwU2
zXN;pjoOgN4^lwiD2S*;dL*0Gx{W;K?_rL!h8z;dRc~4tqG}XU-9+RT2JWktwE=8o!
z{N%ZKT|dTOv*sQ1sO;~3w{vZNs-K(kY7>TZmjA??dUOIJg4f-teG|d(W%tJ7V$zwL
z?9T_SlV4%lKKt^sW`hhGX?Co933e;BL5qym2Ejnx>+WEM7k%s(wt{Gj?=`@r-JdJn
zd*Hz^8#yp|C*y<n9iU?01i;-$3toanJ@nvW>PQ5{+3TO_Jo%2u_2Zx2mp32hH#$1@
z<@x%<gV_)6yxp+IZN2THr?!3!h_Bb3>A7P@+@3*ZNADXT!`t3v09^lzqj#uNSPWv;
z6>rUn1wK0$Cs*ZJZ<NJo-HZP@If1^*gMp47Y#c~B>yt-!f%;rT`d}abz?p^gB3(%1
znv&AKCF<k^8itp?{#DimwmTAm048?<LLa;(dhdZak@x0sSIEVmVD8|e$A&K?0@j0H
zVvW|9iYA`_yGTRd+fmVy>(J?4pZuw!?^Mmf0o5*a>SlG#ju0~?viY-Ri|QzJ4ww;?
z!k9|ZcQ#9c<W$g(6PlX{xF@wSaWd?xSOyF3gPQQUvAHNh34sj1?$^{P%Pzbp7k*~c
zaexeM=UE5u>v4F+$*|<W5E|Xf&$C8sF~rmb_P#^!oD4dqK%EOnxRyFu-(JF_?gikm
zEno0I%je+6wJj)P#r`VdWu{W*&J?lVYRfK1bU21Y|3L^OBnx>PC4o?&H+_0-Nm3DH
z2-?Cy00vljRLav?aEqJ7Cmw^EA*rf_Io>lvr+0yUd+(e0t`E&_&~JU-?3>8!lb<;K
zugEOOsvkPC#KBe__)u-B`3C28@r+Nu9oW41><0bz-pz}r-XPA}AAXbbIt|WibA$8h
zW3&HQz2wtx=QilKjfjuUp0m%8&c!#e*~Le9ocnjN*(+k5|2tswx&H*h`=!gHKl@k2
z`Yj0WKYg7~`#3Rw)x|ZrKTe*@U!C%CVlaR2zs;KbUYBj`1TkU*){V=98~j@t*S;Wu
z*L3q?=5_Os%*c`eEVl8_-h+oGj{+%`N)7Q1Ktnr6LKh6sDp4YT+&b(G=8YWKxynio
z&u#qYKeOH1_;Fy(e`gnXxBg4Og!gpp>A;I%@#5bRcVGBzFcpM#8@D&%V@3H_34&j|
zf^qjFpf`St`jO2q-%9ZJm21V3Qc(2eD`b=pn#c8FQAS-vaaJDB&AyB(>uw$Y!iR`@
z(w8Wm)DjjDI}=(2Q)M86mB3bWi+9v?bGz*WUTwv|lp)s)Cc<AeiCd=w7v21MV^fap
zna#aekl|YdGs|<CE-uH%BV9!R#J?-Hm`PDjfU{E45bSeN{WF6(w=BaMjj+|s5=qYT
zB$aidB<p;ETMLN<0?<dhcG^y`?usmm%|k$p@`!5|O!&4ANCcy}Qf>wO!}NmX%!X`A
z8KBO9it1_TbQ!mlRzX_3CA8ml=M^5xb&Tet>eALsRNAg9)jUaaikJx@r&8L6*f*zy
zfi;OP?`e~CdA28FwiKI)GF8?}>y<w)#dUsxjfr~5HdE#>5085leLq+Xv@jz2^lE_&
zM_i~66h-_s5fqD2XF|xq;N;V$EZ=O8*>c8ODUFM*20c6wYsp0B2xOTwd&Wq*v+!ix
zu3$~;3N90r;<@HDadD!YG^0Xlobe18B4}C`KsrJP5M;GblQMIG_fnO5+}QWeZ#O=0
z!Ms>cDV82Lckk3*YS_Dxx;TsQYM#*Ux*Ic0evmj5Tuz%fAM6ocJ15x+&(*4$c>%2b
z+*a2dbn<N65{quHYGwA0?73PcdnQ&9q!Q^L^d0P41Ik#sBK1u*rftcC#|P|N#zw%o
zKAr^lUf|I>l}b9~t(k<UC2J&PigC(V?oTh=gcFPQsBXxy>^Z-5w=`>7Ih59#N-q`2
zUSN+#FzTX!9o6*jHY?Tx0+4VNT3tCI2kLUHoVG&2mz`dN-GTR2sn9xm7c8aAo9vzC
z#I32IHBTik@-;_<NRAO;h)P*g!nM|0e5}FIDF7dSDZfIlJ@moo!QHvhcZYL&klwLs
z&UV}JP0JC(4W|sF42MHclh0E(aYv*qQiRILYr^C7ESn#iS~bh9uX_eab?yboHMrok
zO$I-LJQ>-ul8+rS4#|9j+$j%^98XT>C#H_%5)FeT5toA$6Pxcvuo%(Y<f~_%G|S93
zCnT?_M|p(IgOS>+Cer*PY3?qN3S$)HbYL{K7<fs1EaGtlx^o?-{fVExV_Ql$2OcMx
z$dO!J%hfJUZj0=pdK#JmE6{TRb|}i@^_nP1G4rWCEy`4#;<&o(s>k;nOi!$ky-?-w
zQV~)eA1{3XP&C5EtswHyP6nLJ0<Fk#&)(09cCWhIZW7+bA3%WXy0ri+J#8ZBea@i+
zXpUPW>0Fc|G#rd<&yZb=n37Yn`vDsPr4z+;Pf)bthqin@@`uKl9?Cg+695YX$PHX1
ziYjG)W%CiF=!#iWL&1-rQ?chFbAt3zFegj1M#jv#s}VM1l!!*GM=-l72J>42E5%MM
zdvOU;FagpbI6z!d1tydR*b*fH(79B_W87Sj_H(T_A%}o4$ue_`Roe_8^8}F=Gd~ad
zB+6vmy4R(FDkwc4g#xv*;)49!tGZZ4G`EjqA*PlDBvw*O4%dTGbPP{1z!rJ1a?zQp
zG6No7HaHAEi1v~T1q<DX1fvL;LG(0<56MLW|L@1F4j_xbcDjOgj3NVs3ssG0VEtBT
zzXbS<w`Uvhvu!jHgh%ZAApW`vw|tIY#R}xyF^L(6X=jO23lPimTsVO#%LxL4VsJ4u
z%Vxlgy`x>BH6$WY5y1EYpgl%=+3Vl@vcIE<td`|MbuEBnF_;M44a`N57=_ROb%VQ2
z?=Gp#`&__~C%}vIn6(Tnku{g)%QQ&Gs1ifnMQDO$=Vgy2h{!gr64Iet0jSO-Yuch>
z16rEWu;gk9N6Y36%RJ|*l3)Agk1fDqH5K~zY82y$GI!)vy%3o-OS5`OwQ3abUv>>P
zp%Ub;b#ygk9e6vyOjo!u8zgyTyPQ$R6V|LV6|+9glqtgYcqouY?lfyIO&Mv~S6o<?
zOl*Y~ft#J<Tft%k<i!|3&Zrt=>;Yz#gv_+v{#%${u)>lGjYy=t#wd>UptAy%dReuc
znRn++@HT`;`OQ+6A!@MI%?6fTF9+cQB%5+eu1HBTh?rRJVGvg+1tYa0Taegk7kY)y
z%dSnh$)H=ElO;9>`Y3qKsO*tUqQkY2Mgha+rnKf#PTx0i)6S;hU_K1Xux5g8Yo@Tq
z@O;n!I1e7G<`11uVFt-P2QZlIrg?~rmed5El3wWrJ{}6h1Ng{(t}2v!B~>X4EP&nM
zn_u8)zkuwMlv1GpjHPS<*9BXt5%tuuq5gjexQYXF(@oQWd90%91fU{H<#3_Yr@Ff(
z+f!#cY&Sb$V{nul4D|wt*Clng7o>KS1uTa<sCF~O)Dk-&l_+d9uS{$tBmhDBBM=SJ
ztr&!?=7XWp>%a3&G%2daH~G^C`*De?6d8uC1Ta0)EImRo@kOCg*DLMz5<&P`Ag|lm
zTu|BT5nDzzr*}h303O%~pCXrG(@|#)UqCJEvAnjGm!($HvUw6P8yI>}jx_FZn?2Sw
z2O{(5zV?pzCV-+OxQJ|X5MVW?gX_)c%1k@lsXCzRt)73O%Ge4Pj9@kcFw$N2awR8+
zUAksz+3na+fz0;|r1R*f=<1qjjajUZ`@~rgoH4{M2!{(23lq8@v4=UvaM`#2%iC)R
z4E*uzt$Nj)OA~wn*mZoOy*BS<Rj^*oU};{uWl%<yn%6W<5IVC)V1Nrdkk$6++NlFE
ziQG^qFx9YRwsCmDHK$ah=9z~f<x!1c<w)SuZx#wjAqnp9gIk#w)iPd*kH&NG2(P`c
zx=c#0p_vq5dOSEY6{R4R-;6vOz<&=V1R&m-3s@3zQK~J^3Cz=FuMb&X+{#p=8^#t1
zM&QfI81(ZTt2fAKGBC+GC@3D%wIIkexLD@VV6V1ea<F?ah=&3oQ!|vXe)u=7e9Us;
zGt>&nut|QvANHzudF4@7{X=<PrslopWNNzhum|~_YWZ7U;tE%%#UxKbx^dnE?PX7X
zQLIeQg|*Jf-8bKDy3gAmo6jAf<%8~$xrUhIWyd^c=Do{}bxYdGLl0fG4~?+;O5_sz
zQIh@!=}(?DU-i=7w|V*F>C9AjbDDgRm**ZimF7JYtl#46Y^p5DyjLzxop8?ci8Ez>
z*}35|Od`3!yO{inEF%9+CRZ0H7ZXRjzI1MqHO<M_UHx+h-$BbKjp`kd@Fi}`S#n}l
zPv~TVACZf4c{X~8d`d)7(@~-#<vq1JSDrPe>QIvsLHtxX@U4LqBtB~Vaz1f6KVCg-
zlfN{d+KxJ$N2<N!&mZQwf%*AK{@SUvhbC98zt@hE=KbCet%rMlPrkh9or4Vh7VpTV
z4>sh{{E_sX&d2#WTt26t9cr$!W31`M(55YD8c*|b@yz5X&mHDdqA8nG@&yTz7%s+X
zvv<N-`t8U!+^$BQ-OW3#eNU+XF)x6kRsetm5D}`jJ`SuyXJO;vQ(*meMox415+{Mv
zbb2R(kW%mFFN?D#(6RY>2}uT=Sp<;>pDX<4ePz3w1gF^ZP<dMO!!&nN79q&+Xz$_y
zw&%t-oS|6xM#CAZQ?I}G)P3Q3)NvQZ7vvP~Pd30gyfNhr-O0WF=AzX#>Pg-;KMyq9
z=Pn=dH6IYAG5`OFPcs$|fM<EdJ~RoOI+AhucM3OklAWIA<C8eNV`#k<gxcHrYwQp?
zYrfLFte^K0r&`-tXfi}@_1gLMTI7yP1N^!d`LEuB-Z|Gd1)k}3(E5kHquxec{cq;C
zxW1l4EF)uAC=K)!B88oRl($V47yxb~eC#z`!z*;WnMAd-+dpwW-C$;a@3}NU>-E*u
zejS8BxrKdv-6Y@k&MdL}y#Crb_AL7*?{@olo?(;c<-1w3;oal(JT%Reo>;Z$#T)D~
zalSE1jzHnze52_jonB9ItBg%8x%xVTSS#S`<dV56C%*y^cnT7ovHpJuLL)Y39zp5l
zOP)$h09%Q={$yevwa2r;$cp*&dC}Cv_s78Qxip0;`}SwdIrJ2;x@i+^)+69e4_e|U
z?&PGb>w8^PNz($L^lf2BHuZhu7p-8@**Vo<z@#qZ67o{6nd?a>i@bl!xsj8p-g(yZ
z`;mIBncVO7$umctIj5&9d8v7s)f&v}Z9bHAnjU3Sz{D?kh`uT4p*LisM~{N8sL=#q
zK$<|l;meXYwoNVpwUyp;e+ci&7ojMiyu+7kmR1a`#j0P~e@LA62*{Y;w*+wM!dFtH
z^HcRw-Lx=-SG=1QXpIA@J?NfuL8#t4xfhJf;T+y+W0;axu{oLhb|0F0H}eUf=x{#x
zdhQ#KOoDxQU`KhJ_w(la2`(DK((=q1wp9)_*|L)e^fvQ74`H~hn6`+&N;(=~)(PH=
zVtViQl07<jea=;mGX7O!C0Tv;VX%g;@(JEel8vXQ&eN;=eq8}9OeorOt8RLea}cI~
z7t$(g-t8ui^XL=CSpDSY@^z1#3`WN}t@?uNVk$^-Q<!A(!yfQepqk3?QCMLNJZ9pf
zbWh73Gz9jC#TuC4Ij8G!_hXYtCCC>Hxgzf=g2*|QB<G!Hp5<1zl|01`H>aL?NJ)5F
z<p&If@mA=P2W!#*n0pPV6GR=Sk<2=1VO@{$2Ad>O1HpJR>;L)NO|UVKU@vX+m%9ZW
z)X_xHJnWTL%#&*Z$Fvxc>mCYe>Q!$B$ZsMjd`4=i@ZthY><IYJbsd5k3eAy-4&-m&
z+C;vG?N~p4e9F8Eor=}Zz(8`B4>aE&IpKX982-zEU>6?(D6Uj~J~h<?35(HYOs;yz
z7SB5Yt0%{gN#NJRO{g!N@s!C%1Lu}<X32&>%CM?V0$OmYcLiO9wLZDt^FkE!q=vI!
zG^Onc^0LRd`X^OLZnxDvQa)I1dXJfqJ2_m17E%*zlL}M~U6~zSo5D=_=4&22k1N#P
z4=q6ueZMo|1(Ww4D3N?~Pl*Am?aA%1mn5$2Ip@?L924VM-$t5!QweK?$4yOqzS;9o
zX${o}ppnCR^4b<&!?aj-pJhE**d$-@dYZWC5Y#^)4FSgaQUAI<?^@zrV{oCcUAKvG
zF3C&!W!+pi&D-a}3RflzP^B)+BSfeKO;m=?E0qb@zbL#o6*T|*(YrnB6X6T|!Tme4
zBS|`ZA$}*jW*A7|;7bn-AJ_$14kqteHJ4?`xeNm1jr>~d7Mz9dCfy=Gyhzzm8AnFT
zxt}GqV@-3;R|@$73y$&bB#kzc*>x$Wf>vC6IRU2X(K#=ALYFW7^*bwYohUB4H!rl?
z%9!(q#94WZbvruvrSHSRR$K}1yabqY^hJY{${~3ZwuHnj*2$j&FInuHR60pFS9V>Y
z=opF|i2GomG-1MQmK(!3=vZ25^Vs6zg<<c=w=p@9vT#hTGRos~45o%G6U?SRGY|iy
z&+p%PM~SB!O5Y@1&?f`e3~v%?k*VO}^9ps4)F*~c0Km5AVZ#8+%~>OQ(a!rkhu(Ir
znwnRt6#S3ffRhIuW7XW{JsdDk7V~4G@2DL)=<P2m;fzc;DEpPFgNe{>_`DD3q71E)
z1-78?38I)fSTg4svt}58XJ#1*&Eg47_Bg;LIj#(mSJWAj+Ps}y|LWh2i9Gn37Bs-)
z(w_Iap>OmUBIGI<#BPFn_L^I&3vehnf{7BuFi`y_Vgf-p7{d90x$KrG_2iY6U{vcy
z;J63W*{Gbz48_DD5bwl!boZK+?4=@nym-T6Zp;JD0_6^jqU%ixZ4aiB(vxQ;c%6IT
z0%DhadBqothz9qa*cATWdwq`X!40Z$QToCVzr@geWcpW#Fuck0{SQ&#p||pU-wGvn
z@_!@c@E`M*f1xVT++aWdvkxKz*M9x$pgsGt61Tg*ARX_1gLHiUO<?=(Uo`0#B<fE-
z^2om>QGf9lq~pamNXO358=t{nHP(OU_Yq92AOsdvK>h)7mlD0mRG3><i{hCLJ_+I}
z*Fy-0AOjhN5{PK1PIW+u@dG{1YOG;p=kv}o&pX0F$+Yl86xWYA;KAc>5Nt&o)DMfU
zoj#8HH*Rm@$Z!7sD<7k{l#Sa)Eb!L1U|K3)d$xtf0NR*6G~^lj$DoKAF6vgLAiHOe
z=pFj_EE#5pX)UEMy75sC%{Bp<v}G=!<_9%?@S>xr@-RPQn|o}W%fa*)dIy<qoFcog
zGV6S9HJ?1^&TfyseQO6BTIC=zR?D*-DU|AXIjVI!Y-laV!@;mulrd)$V;8J!5Ew+%
z3Cyq(@mLZuq2#MY#;?s?%4)(jn5DS6ni^FfBUAdP+MyBvj5ek&L%<)$45$)ClD?XT
ztm+(tl3U3J(D#{MFor-iMrb!OU~NC1S+JFu`UqtjYBCY|0w$_yk$|tSs8QhaS_}`S
z5|e=vYeBMLo=q_2bM1}>JPbU~5Z|tcO<k(pde)xMht1<1!Y*LG_35`o08lJ@?sQz~
z%A2wULAjf48s>}%aMTC~qG~k7GIY@S23aYd{<I~K*<^{ppr=9AE>l*kE(336nwGS%
z)6D1i7H9@AmRv){EFTQU5%X!V9@~T`jmibWfHZ^*)}TKY@61}`;;5-?bwW;Yr3AdN
zS6#46D(OAz8z$(6Zkx}$EC&FsFxxd>%oKAoUNk72Uh#bL8UXd^INeiZV~J@pO>#h@
z7}WW)JOz%43nV$qi-Nc@dXhM0D(OzZ-*hJ8#e-o^M%+m)ruM34j`K)f>)m8APD+B6
zHA&1Lf8(aGZfnXjYJ~tHGO6N*S4~Wpav>?)MXRET=he|N%Z)nWCWTSQ?vkc-W;k?<
zSNM~G44(nW+-L%1>M|_1D1~EkHdaOgZlcrxoX7>^aWo6!e@&Z@oR;7hJ4G2Xa;qj=
zCQ2jPj^&(0SAlpXG3C&EUpxQnPa{I2s-QIPsi&!cb9Mx+)yX^_p944>UyT4ofa?}J
zP&aX5!eu<V14P`Xb3N9ed9F$S&U0=#)GI!k*2+2>O1qr3rMt<F?bZ>C56Rfgkg`SJ
zl~WV728|Re&zaKRG?Gak5YvuZJ!SCs=DQn&cb88&=F|$yRlYF?s%kXiZnNep;H;(@
zMvnmxf~v>=ahuUcdMjW$4h5MNzIif82gIzengD8=D44Cb_Dq4=11j>E=KN4U3zXY-
zfb{l~n>%mJ4Rz&5t;l;L1KwODohWc?{+Q*k;y{mejWi?QliPp90N#W)MH=J?W94F*
z-<M%`PRMlaiqOi9u-V%fi98})o?~{Gw}LcG6@ZBAmH%>*O))V^0n)`XAVvc?-xJgR
z_K$BNN?61C2f-LiK=2_Pbh3F>nI*Hgim1IQH=rgV7n9d$?R%)WQQM8t$#6h%|6Y@f
zlGA9IthuJKoz2LR8H?pgDib9&!koOPVFKWP;Hy}2H8Cb>WEBpGr6lJqrZ|$9Fsn;i
zn(t}hj~?Ht(LR3;xKYh;du?W0DJ-HC)$tJXEvX*xS{hF8#!`*6AXvbGn#d5OR!|aR
zl^l(ht_bIrDjanQS#2J1HZ72u(S+8^bX<rlnbjgt*Wdz|1RFRik)_5WZI-rKy+UAh
zE!pc&eWA2AngtCRUmJzDgnrJdSb0NT4px?cGEov>Jo0>rAhlqZbWQ>PKmnGg9j2VH
z0%0=%h}s9FlyIIiEIv(|Wx@<5Argv2SP&YaZ~}rdgLh!7VCa=kOa?vR!+?X;#b`ho
zCd4rFmWgqoz>M)q^qgtDMgmb|0wm!WVs$CR++{KLt@3_uinS@JRb_w!M9h1hrkvhp
zQcD3j9rz#$&M1jVp>yU0;jenK4{2=BTp18QW&^;_DYyc~e&1i9{WKOZOPFvW+p~lD
zc9F8(IOcA_r208CG_FV08JvHj3+RGqvmF^PZ+22*xE(a0@0Lw71{4+I1y`iX^HtTY
zwfNl-4UjUW^a0_sVDkiEI}osv#$7+lhHqbx_&yRKSnH4U`^}{@*up?6#vhFf$QJ2w
z=V>!9@&>>|0|#Chp(}EhD;Dv#`cFisMv?ce==7?yVhuYy7hZ)Xjsv--)m$womYGss
zW!Rj8J%;Hhc7DNGbV5@p2V<&WBSG60>@yrf!AeMKIc4kd4~6~bdiA`9IRMmBWJf`~
zb||&XQVzu<iW?08LiH9go0VvtRAB&sh|NOTo;JcV@R;cqJuXF5kgHUxB@Jw98~~9g
z`81NO(T1a7(@?Tr%1p};w>95ZLfTlKLRm?|&$#_r<Xv5Xaj1~X48px?sKw3BLsnnO
zwp3KbP*Bj(p{v<ZE_SmEI5p?EJG(VMR$gAIfg|fn=IR;ZA5bxiG@oIPy36K~v=0Vn
zVFF<=csINh%8C@}6AeJ8@?kRUC<<ff5}4x&Sh_zQl&GpWu!krXF1l4usOWU$6m(2!
zHI|n`%LCQTW!G{(i5@_<gUH7$!I#2^Mzv}TwLi!-AyHITql}?bOZnu@R8S;VoB&{a
zj16>!m2BYJxku5JZYh<=5%eK^Y*yP)AI6osNT^`P->SPEsx1`+>zGAZ%sMniN&A^2
zfz<`qjz^d{L+4gi9@R)fwcuhzX+9scUE6<y|Ifc&`|%_?oT+h*64>ij#0NMP1Yb{u
z-ZT`dmq@#g89%GHLtv_^mQkam>#80C)F@_4He+)R3t1|1?Q(@N7wINf!8O5LAo~FE
zY@qurjV~%;<6gDK9OU8}bc{ujVdE?p4PLwbgZ^kt5<feFw&FhwjAPYu+V(L$i?WH(
zxbZR!pfoT+T%)Uq^lP?fRZrN3e902z86%hW!ojS@sE^?z8#f^dPpGA<E*QKxZw=<;
zdyfD>vCCtz%_1AZl>w|WTuEO4ZW_aTk*$m_K1NoZ#fl@}X5K0uYuzNa7TlUzZCf`T
z_dRB4cd9jXQOvftUa*H|>3#N>?b(aum^0h4#r!1w%ngye|NPT)=F|4y2>buD%_Eby
zRz7WhZt!ulc%id*=c~nw`B%4$KmQ`=#%5pd=ohTocX;)Z1UrQYUVcE9Q}9S%D=*S}
zuz&ylJg@y3r<J-P*vp8l&|Y@hti2%FGg6S%#pn-N%3`~vHYpur&W+5u3<^h{@`=@3
zQ0&)xA>xJCAT1cV)ujn4o{aQ9sh@toC|@jJY+R%l$VeDXBJZQQ79-}<2oCF&f_YDS
zbt(V2dC**`c2^_m&)%o!_56z2QPlUgM~bt@a^E$th)eJOqtTTxImYNJnfU#OL={E#
z_M!RQYXg_1v)U_q;19?}tnp=uJ*T{GvWE^Cs}oxy;t0DRVPyk8%Pca{m}^VN=tQ-4
z^IldH3~RY~f$iSJqL-{7)<HjUvioO$@p)tf%)|9QiTa@eGsF222A?E8M>->wU;^a5
zldV96N0Y6Kzzuh#s<e=9Uo{Vlj_rjmED7fdcuO^N3UZ1groLlbRAwm{lDJPEJU(i+
zgG}r*ib=1pkXKewYf??QnLAAsm|qd_-iu;`!h90%+4aVc0znzE5It>hm__M<a+Oc5
zAOuRPFm9EDxeU^l|67BE7U`dULW}HfqC7s5?-{J*FEId-dfQd@x?@M~t*3h49~nPx
zME=P%JB~YK-|1PW?*i#074rl@p*wya1Ch=&H|K6QKr?LSHV*;}r;kn?B3Hy&@BH)U
z(*ICD_^q>aiTss!UG9E#<P_kxi)UV^f4Adt@8{k<Q1W%|d-ahonfJc-;3)t)l}$UA
zGWS+#zYZPF*b=*19|uND{x45I^H5~T8(;jrMSiS)Fn^{i=@b`}sObiUwI?<W$;dcx
zwtG+So$Lhn^G98$($+ohmc^c8#C~<?3>ye;0k81F2Hxu)ttEk`LSNv=f2l?4xza(i
z=>q(SbX)HNN^KV{I-CK28LU;iZj%moL(SJ|_p8`VoUca<+kOK;Az&lp^@5$8!{e)M
z{{<Y_UB#aFPp57_zgEtpk=55CXLRH`eiV5&J^6#Puha45rH@>;o?+%bYBzH4HNQjk
zrSvM_+wtI+($DkI61uGQJjw^Bb-{Lg)I2oQ>`MN`z*Rj08~FGeO}3IhH8bI0@~RwZ
zg7g_X*1X|P0-|+RyLPlpzB+{D!%=sO1u|*_f)<mD5Glx^#GD0ptmpoDK_3bL!tS<)
zJ?mZD-v?BE%oh+n-@o0W1%X2SoiXboPXU>%j7|XxCh?_ML*HuOW7kGJG*U-L@EbdG
z_b=*;x5<x}XT3AYi_Pn~qnn?__3p@b8&H?MagRrnWIuc4DgN~!t&Y4HPp79-l_6R1
z7P}e;+zKkcZ$NsLMJ_cjPMu??SY+1eaUyD;vycL&`xqZ>KF2VyyYdO22kd^B^|Wqv
z?@n^)0i3rQ4B^F+n{ksY<=P9aGP=I^*n++QcQQYOGv6<7J2$eZFFQT^BZUMVs_5<T
zNDPM@uE&s8^IXG()&5ybD}mTuCO2%mHE!R?<p`;qT|HMUipjj72fzJK55;#pZ+0J#
zSt+l34~<;03l9ywTE1=?gEw{M@6Sc9NZVmoM1gN%j~Jt1+Af(FljqnZtl~%>Mpy6>
z$DJK5eNM8gSdSAj3Pw8^tdG|^(&*e5A6_CVjuB#zVLp?DPfL7x;aT@?Zy|*vDX)J1
zor*6|ECRynb7Ju7O16L2WLpqey$)2hp0IrD++0>e_6^?-7juUtX5R<xFti~0^PFDs
zKr0Vtgbvl<?{pybgvPv&G-A{3JHg9Lg{^bN*LmjHc!Bw92ku@s@{>$vanS$NGuVy5
zSe8h(RDwG$d5}@}#UR|oDS%iH9TWF*3Ta-HGwR3=#MDa0>PeMM$c}(4oz%86o(nN>
zGWlLt`SD-8UBcuF-cI0&&2H;Gx`1aXZr^UH!Y~E&cgzZsg^>bFDTYyL>b__M(8i&~
z{U!j?2JX38FNi<!0sXy|jzA|M+r{+Wr$inl2y+V$T{|w(uN*wvG*Wbf$HDps=o<we
zALqSTu|RTQM;=-gjsp<6PLo9m7u)j8tZcMG)z-P1_YKNY0L<E@@x0BM%w2o;`+bEO
z%$3DlCBHr}@IC{IyZ9yaGus|=3s2)9*(Y4<p!suPNEpkf<3i2)4ES3On69VauIHM5
zB5IJF>+je;LXHXsPWk#@uKhtS`}2W;2fD7i$NPV@y~y|NzOmDdt@F%xpgjRuiW~0H
zy_2yKZ!xYxcerstDUEP^PA<7h`tY!ze_^O+XGBe$a~4w|fTy_?Cm5H#wFmDc*~<?t
zrPYBO7SQxZ`HjXR&~E^@(9P&`DZv?U?nY)~im!j;Qnm^IJx6iOHZG^F;92+BJbT@?
zk?gyOLg}6ybdSA1%>{>>A=Mp5x}oA3qTm@j)oZzdo&&@DJs8ue^YR^w{h4Q81flt>
z7bdT}lmE}^&`tYZ%S<WzcISyi8U=J^eKegYg7nd|Q-K1;%hq;ZY55xizK*!Hs6PXJ
z8LNoRGd#k`VKMmEzwc>-_aV!&*X_^W)O&q$a<9cY3GnNE{Lo~;+_yHG<9>oB$N%&d
z_^U#lF~g(jRyA8sg={r!7Sd!`fP>bDvTw*%hVnjx+d7^p(^n08&~u(lhx1xY+Gm+N
zPAw(8>fR++h=o`=;l>K61hi%d1DlyyyvK1xkMoE#?>Nv2?sc)bPqtK#7kNdaz?|J(
z&B0kVY~>QF-FJY8E?7zqd_I(Ic32In@E;S<JCwNZ;|>!}1j46zCt64<%aeFQ_rvrM
z@Ns3#<ijACD0c<2x==gJ04O<NGAk%-Euoe%<L}fn4#4XL^3o%ax;&|k2@0I@Wke|I
zn3)NA{_8&f8ERi}*5TJGO8@V+e9+xc86G`6=*w7a$>VY0)7#&hKbG6jeZUX<Z-5qj
zMSKt1zRBtEeH#kFBlo?b5d3$)QX%*kI>YBTbcWyLOZ(!!zXF{8C57Ps7*_t@KIE4q
zkN+3K{qKRw&c7;iR5z44o_cDdJ#V30^Tm@JylrRbhZ`(szPQ*Q{x!!eZ6EE6l&nB$
z(V!(Or$vsNt{CaVg6$}yU?VAh*`^53o5Ug5VE8=96O-md<(Tt_?tK0p4nX;y#pm<E
zoGrR8=O4Ggh&i0wn=fC;i$P!0B8U))xm%4lq8Q-=2PH(<(O?N=Y2+KC4IzC(iubvH
z31H{|8~BhkZitcIxQ+cH0NQv8QWL*;`d2*QtKM?^Te`Dl3(mS$7e(AWFK62qg;iBE
zahx}|24XWc>!9-WnP$v}#4Sy+s??s#rxW+w)q7GP(zeT2M8mMk=Xi=wUN+n-P9S1k
z6leM9YI1ya?#>Hydrm~GP_Of<cXo)5+flWLBBewK;O7~zmf5Rv+%>o4dmEH1|1}PH
zdyI|An3f!O%&!;4f!gzg+)XpP7>g`1(EyUbc_vN9P|WD2E%u2I-A(Nu0N+7~2O^Is
z;keKSKnBp?#;G7UE@}-hD~FmyNmHt;W?0g82j@f8spW!J?X?9;<J4@MXaW?G11<Ka
zv>B^L+$)o+9m;1I*_s}cGpJ1EggInLq|-`oY657+vYDwB%L9-ZFw6^_5Sw&%WihdM
zl&PgvHiP}+YybBUdyS}3Rn!p{KW&rz{alFyq^}@2RpJwZT4GTMl+w4<0{3wJ9-8;q
zP6*GkT+={}f@htzZpoK$^pqb^(O1P+h*kqJa+)0GQRK!@%5o=UBxuV5EUr3hj!8u0
zWrm1^KBM(&B&t=I&BobshDBw0)=G1Tb+Gaiq(t~%J8b<!Pe*m>syK5CRr5CVID=vc
zmHFl-tcj=9&fR5=nPaVjv}?R8AD>N>Z{BNGt+PD1#k<X@P3T)h=^vrj)hae~#GVL%
zJ-JBoC3SozQ(^&dRFiKrhZyZf|CR#i7HblPT32mgQ@P}dwQS7o5jbOqL*YP1Q${cT
z%^5xQ<%ap4U7K1XD>_aYEvZ!st|;^g1Qp`6ih)c4xQnV$t(BOgW;Dfz(C6L@+N3Kq
zxje3Pi554?sH6?E^eqz6*a9eA(*%627D&Zn6cxszT9o;Eo^corkOjp*c#)Nu(50W-
zp{xs#re(5yXIp0V)&u%j)m7YD3P+*^LpR6Qz!9$Lo6Im7Wo4QfEvcn+N_X2w1natN
z$hL8B*!8Bid%GvR-=fu~Xg^Qg3G<W?19eel3HB`x9KVyf(Nkmy9xidu5+;`Nb;Iwl
zK%<xxZ_iLZkxf&;2Yt-s-=e|!0h9@}*pZ2W<VrXP4r>Eva?gDX1t*V_u9lueZ2kJ#
zWqlbm_|S+DRj@6}DyXH)R6r9M;v{CrtPXVuF->kG8B+Z-TBp;-g{?!=wD$g$Slvi?
zYdhwq=5~`#K6Tc-=d~9Orq>D!bSVSwGygE}`x3W-e|t6aD#S2iNEFPF3`U2WMG#sU
zOQ?YIV~slY!#jDAm7t{&CixsWWUXT2C3TBIs$w*=Tb@aDU0~@<QUoGb*^S@apH;0}
zsatVKJF-5|5&^7;N_3${-*&5jK6I1`M$@`-!4lE8ktk|gkr3d}Qh*KvGQA~Fof4b`
z7HA@<AY&Fp#-k)OAfsVv5v^BcnHl6FkYIrj1yvzeiO~gwLMYFJ8ywRTGR^W)x_+VP
zqmNrr8HR12R@{vR)^$TILYX%WEX3(iB`@3~InSYEF`N~N(`i-Zn>6GH#-d$|KV{LV
zM#qv^E{J(j!}6ezEe-&-DDXE8Iua^&h>|{GbNT?8qD&9Sl4e5Vs#JyvQtuP@zujl@
zD_|4jA*!0~QV)t!yXWr-?hL?QWCSD}hLFx$JQvogTy}X)zAXu~t%Wlb0eB=RY=4b2
z$7Z)eD*_7<G#r?zFE|-|a7hD7WCi>mp^5-nGwL<)&HUQMcV$7@_Ui|5BH%`f6bVEf
z&xFl2D9Qx01%U#F%Mcix%|}%}hJjU#<os&QbfAn4M;I$PLEg)nNryIBPD1OFb(&UK
z3~(X?0EhAf4bXE)stQ26tOjhb1PBaU5ISj(_R{Pougw{<Q+jDd@6*984Xx+`1rAs>
zjgl>Fhw6@|bFgbs7be!GDLKUffl7wz6i9rcw>;f*I9Ayq+dD;LT1^ryM3`o>t>FFi
zB4IZ>Lj6$yVzvO0^Fe@T*bx*~QaRL0(6Nq_BK<#oN5q7mwXC~3uvI&VE1@Daqr->N
zbtqGer%L0*$ch&1vix|670t1E<<N7^svOf7{LgbU)fKajh(g28iS!nhC8Z=?dO^Y%
zl!Oo2`I;1fw($cl1~;bU658jk|C(Wj?bQg7LA2fn8x8l}cD@~?RFdIgkELmsq^&`n
zm|H1}Qjgx0G(4<KPS9J}?%gW0@b|EaMcKH(p=tqSt<beYj%+2Q;lzZaC9tdksP-=i
z+Xm42(y9Rv)mKP~Xf*WtiH@;Z8ZF@Kv#K(TeZbrboKn$oDflGeg6~~y!|Dfax4_6{
zHJ*_kMw8>j?5S!{QM@&Uf;f+MMkHo05L$u$Mh?sOi!zv-XfYCvQ8gP-Y&M|AG=BTf
zcLL)LAr%_JC9Mzw>NaTfijG+bUnH!WcdANM8o^RdjgFgKy6re|Q(GYLXo+GyCmp8s
z_>6Q_i3Rdt=+Z122;6ro>IHDa7b|{dU(Ml){V&GCZ?bE@Rae|LFqTsxT%1CUD45FV
zJ>@vbsyaGx49S!-p<3i7y~bt*lGoXcZnQgSPZS_4@*P>ZNVBUB{t!2oyo-d9tHxKN
zL!;CQD9V_P;YD8(C4&xDl)pW@M@1sNgfc5t;CJ}*E~wf94cFU?B$|fke3$B0RGqn^
zoYM8AIk2M7=xj`XiR5&I1~N*=spWZDO_&ymK49@YcCX$=itiY+@U7@<46jf9MxUuX
z9LV8&u;bdwV_nzRZ0s!2lm|z#0~d`^rHWpW0^?mf2sg2}WkcK_*{gss7PxzUOpm%)
z*<{q0Fjm||&?_nnc2p~23r{cL%cClcC#tcihH!#s{GTwr;l4$+-Ky<(b?M^Ae(iRC
zu-!S>Ix*{3?6vl@;qRjs35%dw9tWMbV0PFAvs;vBH*am9ou(-xKC5rhpBUFS(<5}&
zcw~IGJ<ac*5XZtdbbhPbS%0tn#KhCBKS-RN_`W#roG3pYE|hEadb&#e@}i623Ddrb
ze&M~&<b6Yp@jha9(?<?6Hp#TaT)L0sS#Nxa71*KfIO(P#)MP193TqiS3x|#3D9PTU
zjTV(s+hHdxb2qWNZt6>YZt<3mRC|1$^tEnR^yO9qJ8NIN-q$YPV~SRNMNgFvnkn6=
zrXsbo?PQkTIUDQx3i8#*^x|CWi0JqU*PqzV-Rg>7{;n9;$uV=_`(nvlZx+J4SIUof
zmfM-QDrq&*#9_Biu=hu?*PfA&bak@(Hf<T{S}j_mCHpE{ak?7x&SKn3?q{7W%nlMZ
z%M=&^$p+x#5EhoY3nLj2lwyk88RV&#EEPGeZ$ju`Nw3vK980V{tNTiM6&)ale<$9!
zYxRG6f+l^y`KsJz8tuT2?b+0w^Bz*JBj#pQHWhq;`LK^UCu85w9LJk!6LiHYj&*`|
zg=|pJG{J|AwT?0~0>33mRXFzrsB^{qJBm|>OrKnaiGkks--Cw|j!5uxNE`2c<NcfI
zqtovsZLP0}EA_%Q3UuJ{R={V~ZU%C1N^jc+GUO+ZKSxgLPZnCq-R)oeexV7tRc||M
zK2PrWN~{5R>El1;T(mEK^u3wQUh-A_r2a|o+3}u_c9O%NIkS}hscC-g{Hu{u+xF3m
zUw+j&v+c8>QvzP5P#I-Aequ(fp5hkhdWx^6|Gs>0qMyA^3K6^E^n5hTtfllW;NHL@
z_wiY$-+2bGL+^Gr-D(~67|XJl)LCqV9_UbWzw5*tw%zKvH=^HZvAf$}b~pj_Jq-eQ
z$r%AZ?r(SeT6P3dr$^@Etth}y+abB3`Dk(Fe$?=b!qY}%h1}5s&?9q)poR7%V}(>d
zX>2pw>JJ^0t7gaI13Pf?T^^8oW^(<+13TXSNvQqmm7h-!ojJAbC^>RB1XriqQOxtH
ze?-%c$rC!=@f7c!b#{EwEbu-jax!I2?5L<5Q1z^nXW>iixRZ2N9gwu>6*x|s6=Pa_
zDNVHph$P!tOdH&8F~31OFoqFgSWIFqu+q1${<_yj9zYpiTon~<vtC703SQetD~NgE
zdPlz45*epYe!yoHTX)o9VgSe5u2TwaQg7##TVD}%@7oeN+};~b`Tn~8C)L|T1i0cc
z_l5(K>&5>Th=6YgtjZS#2IDw!I@i-R4K%L5_x$6?18|5bN7P4_9*=>8x(%FLkfE<q
zy4^`fR-8m5WkC^GYBP*Om;}@vBdiUsGH5mIX;2csU_tzz7400`5mOoVkoCirQvP0D
zgoAB%9>>Mmqh5T8fbj_eD+UIaZW<H}&@&hpo4^6G;`Nw<_j2ot=5-G(iM`+R9{EbK
z<%oA%eMepYoO`}_W}Ep142a%2f7oMDH7W7NexR$X9MJr#eB??QtypY>rFGpe{8oh1
z5ER$Dt(dFzTGF}7=i$e4ZY`hzJ8#PV^#Q3ZTin0=NKECt)5!51LWMWe@+bc@JCXuX
z$ZSKw=tuQ&5yD_R-9|5Z1zj<p1bbEB+SSTvds{sPlzUr@Z%8y(g0~uB(eNBH?A;#r
zPUy2+>Oi;u+~{e51A6#)tg)>oI0nJj%C;uSDqpCj-<xsaWT=lIGREO>V^*xu3KpqF
zp}=A#8q|WA1sn#2@WGrmY%Qb+l#3lF0AED2lUhU%?098dXX}rDIy=JJQpgs@3%amo
zd<z=(4alsRc{M!p1Sl+RK0N(oJ8kG~E40(B+Gp)kY*<frHN4V(?=Yv4Mg8!6Tb&)Q
zf8NVyN2*F0Law;lYne=VPUg$nl=tVRYUOc;Ve)NC+A4KvC98q>#Dsw`#foX!C8iDr
zXx2(Yc@oZq6;Y$i2{6`aC>Y2=xqjuh{mu=WqbXX+-_PFT<DU03S{eN^GI?f5#q6cS
z{N!)7hDIr6%4Sx*<f(ckc#nPG6-YXNdo@;BnR;L6SDlt4)y-$J>v#WUe@By=pLb(&
zZvKb|PzQ|jsh&Nt{T`Uyxft?kfLce)g<KKtmD-bwbva8;Zvfqk#cl!O%20&{o(>Cb
z#H>N04gNK2Z1YV!79PR<HrR}fK0j*|a#6^w<k+LLZ(sZ(%-h|52P}e9NQjIOeps}%
zYD%9y+`OY@tp0@>ut!q1^ZFH`kLtXp<~QfWw0HFRo&y589q9}OKIefLYyD~St1Gx)
zGwD?iPL3X|G^;%qhQ8-r;g{Ls{=?!WvUos&qKcZZa4^#WWzRFYlFFHjv>JoSfDVFm
zfExcKBZIGZb@j9k=N`pwr`!9SM(Z-NH;+RHV8?Z%Bd6T04^FP9J`lBapt0cDsBM5o
zc~*VNE0}%un1Ba;q@u%kliD*j(a)P|F^R9-?uw&!qN|wMJk(<m*)zl+TWt(Q==Fg~
znVCZe+HhgvAXCloi|cW0lH({W61(Ui147~BIeE#LEgNaeN}h-fI-jRW{d+~J+5L{I
zjd!`_6_;hghAWE#VQE}mioeqhL6{3jtpVr)>%I=UPar%BLh72UgXFH)k@?47o5Dg^
zLuMLZoe4ufYS_HX#a63>xHV7VMuyR&KHfacGD^Ixp(=8w$Oz!#Ww?-d2%B0|Eg`hZ
z4GIRW4zQp7AOi=|5rn22QWwkgL)YK_)LW>-yEmxAcYpc~ao;z^ihmW)_T1OsPze5C
zxT^hc6@tI?hC=Xh=tuZK@%X>NRYCdPIKK@-7|AyTF|0QPG4Mp!jW_g$-=eGWpT&t6
zfB8_m|GaFnGqk}y{>4dhz`2Lk_g{x!o{!|s(S~qEcO9oWv8bRbIvoFeXByB@6vRzH
zY@Sx)sPL0mjYTcftg#@g=FjIrgnTwXZMoI8eEEO`OiW4;SFmKm8NwoCHLSeS^grn>
zH~&Kw<6n*d=f$AG)qcxsevtT!F!6tT_LqOz_`|n8`H8=ON4E8lc~Or0K{u`Gp8|kO
zZK#Z01dZw<(^t&)vyNJ`)7(ss(~fZ|{GxjCAjbkyK1QMQan{6^bJNj`c^mI|5{~yY
zIr>1RcDUR<Po~mcBr#n#SvkosOSuh@lS#@gJaSXAPAIk}!tc~#?1^G;gG>y)!mdzM
z#iUse4vu2#0pdfrawI=vfXX%6$s%k7lrGL=Ei4!PZhZZtN3857LPMLR1bx@UxmvVr
zubClT6}q`S5^ycobi%7TE0qHRIL-XDD4mOJZ*FCn{I&~pg@rgI?L?7AoZu3_$CG6!
zcnJ-dl8Y0^qGvhPl6C5%$BYlP&^#6qY@W(<jvBU77Wkbkl+!p=gVi{=ONeH1C3O8W
z|BRTtGHVj_Xi0@ks|_X6BSs1020+`|IHg)ziRbf8bR=b9jcgsM0p#d4ys4FD$Ae^x
z4R@68aOK-#4e<awpXTZuQ)-SMEZ50Q21&^oaFj|?jafQdP4i^s5|bK_%PBhUWHoT_
z5(R`^_SPJ(5Fs>=YuUiSi1nd6-l1TDJxCCD>NOSVhhd2l2DgGhumYwr1{;M45pN0N
z0;~LG&*xCZM_tES)&-x0(lJxJ+x_UxGb3rEIp>Mpb36u5$yXhA^5C47#0g?T6Ea_t
zl9eruVb_!`RLSiI@9KasA9mbTgS-k`jY_=6S*D`}EF>`zN{s7@WnfJ<$AqHehj1>i
zHDi;-imoAYEMHn2$@}rlwEONd2w!`grX}9v)*zX%Qc9aVOy5ls$G3xwDV;r9Bq)U!
z{WXxDv@r;=Lf}9{&I=QAfhcJ*pcc!JdagOEz+Iv$xYMkxqT&7#bQV$}3GH8|Z=Qvp
z){!zmuxkZ5sSM9et%-|y8;m;Ly~xY<3IGw4pZF9TXZ`Ge9C{&U^3#QUmgn^DRlzST
z(D0!peY_VuXbT{otUfEes(qj?c<DFH>Ntc)cvYr3=-L?o&#^jSZ}^5LHn;Sh+JMTt
zB_+G$E*iec7FL(BNbU@Dxh;P9!vr!JR^)M0*o>_|`F}2hMoo@5Fn3y251OURi4|kU
z>=3h=>O9C?p`Bn}{FOXN&a;d5+?Vz|Kbmg3hl`-K*oVjsC`;%cw_l}@POgKEYd>}1
z$$eDjy|i;QvJ4B~myictZN)CnH5EHKUWU|?jyW;M2gEAzrDqVFAy<$TOr9{Z;Bhkz
zSSc<}3u83yriodL+)Z-5vgpjDGj_5`(#%d$i|KOd&bNmdRS#QH4LCU&#E!H}5FjX7
z9MERj24s6{dYV~#yjWmLPJmXaiKq=-afeg8rd`<0Ee+csC;@4*S7t%C#Sy||K(eVD
zrHNKoqstH>aR6s9A=H6DLc`ox7%;Oa#fD<!3QFfFv#?;Nl>q^ER!sX&XF!QkwG5>O
zWy;=U9ER_K2?1qu;6A`gkly%Se!QF`IjXp^@r0lq7a&_YV=em%7C8ODG9_018mulV
zgL?)R;nE#}U2&i(*bjVI4dwf&fY3NlgRGXB2MkhD=QwmL9Sijm4A|TH|JdwnsZ?;a
zmNM1^TQ7<ltcUfi)}iafTd}av3y2(;$~Xg4v#Mj7=5EV#5JBs(U*vi{8x&V%IbXtt
zkuFiDQD`qqKzUtBCe!9JQz)cW6_%rR=zv`c;?krE_zUd7ul?pt!xRxfII;$urwsko
zV92;-N}W_Ew*x=hx_zZ-E@YD9Ytc=UIE-vQE9a~|nlrZhZkZduD^nvoa0u^ltgZG-
zmb!(I!4a6H!l{)lqNB%R{5ht^9LLdm;gq2pfL7y3L;GQb_5dN^AZ0+lEyXmSej9hG
z`Zs?TrO4<&5mV3Tq+JEm0(+ecgqA4r6;F;a(;XxFa2<$YJh(?om2fWQ;Z_nUGONvS
zw0j_Z0v&6BeI;pYCsa=TZIdbJTYMj&H7hEl+N<U0jFqz=5EmVwRQ6U}s|{#skKUl!
zw|&ie2dKsX8e@8}in3hStBDWz3RNhy?(~kkF0BPY3a!h@SsW<WO*(?Nc~9KXz0zzt
zx4hQ+nz5?uI@8$<^^9X?Lx3yVf-RhdPzej)c7aA|S@l79q$7Z)0trVW9|I<>0Qd0s
zbyU79$f!VUCFaP-|ECJv*D9%&;>ESF47T$R7-Oj{aglEd=cO%+)Y?Voc{SL+28dr&
zp3*P0>sRx$i(@OX*LDW?sM)}R&4mTa2txIRL#H2Tr-eRoeP9sE9a>5CF*+rOU*Sjt
z1yYC|#YG@s{OJo{f;1K|T8LKYrlfA12PdH(t^qzmt&E&npP~?lZiD%jE}B|*0_TC=
zin0f7In||wHFqp$WVOfm0a2394{b-TFiaLlwk-M+MB@~~$+(*IGRtcCM$Fw7VgoTx
z1Cd3e!<ZpT7Z6nX;}rUVsb*Wyz!tV3K!0H4o=}XO0&+6YWzgLQ9G&Dbi$b1D(UU%;
z%`+p2Fc+w0!y*V*<Bk@EWt7wzmJpYi<E*9`O%Q@aDMlizW&Ie)&IN3Ucw;A3LI;Wi
zm?^oOeK)zb>wb`tmCx%HEd;y4yD6s7GO4Q8R@2h0Ig8WiS>gm!fLZrwwtwaxp}E*o
zpX#d9E{UA6HihG+l@bbg6^czr*|_;m+SrCa55GZ)u@SI9c55_j1n}|87+WQ(Yu~y4
z4(U@tLfW!KuX?uulAanDy5)Mtu(=&Iz77rQwfuRI-KEQ}%~Purajz6xuxj)0%{%E?
zVy!xjooW{<_cvwJh9xZziJj6oEis058EFXB2iFhBn3WXh|2NVi%7PD(ub?Xk<$kl5
z>8{hm>ER@d1QRMMf>|7Gm7_3<C?sWM_yfDm%vM3#a&}%FoA*ci17>*1$Q2A`4;xwA
z{`EmN&TPe6$t|-i$!SSWWeY=kF6t*=&>8;Ic|V*1E8hWr8I`j}37v&OQf!5SNKNhj
z9|b10IKe*Bhq92VROGh#9y4}`O#Q4JsqOxmG`=sI<`?E#FBiWo^rFzat6!M?<nI4r
zw*FE2mDU@Qf8-xC7tOm)zsLK$c`SWse(uYkr{?5Wf8%4V7v9ww+Z=99yT9Z8c-wqD
zaV7Tz(?86o7n5hZGEW_5$@$)gSF8bfg6y8No_Rp@(D+*VIVOs%7c0x1@_|^mL2-x)
z5Tx!HNw95zH?PtLwYWvXjN}fCCs&Lu1|L{5kY~A@bON)N&$HbF$Gi3dfg*cJcsu(r
z?O3|^*Nw+aKaIQ+c~a_s6q$Q^+B|(Z`DGL7m2R(pWxh5n;#!|PoH6hCl<syXj#R#|
zG<VzFohy3(N@nUvxjgmp@)DTCEcr8!P1h?woiO^ZFWIdzC_m-sx2@PKR}VIi(?@w)
zf0jg6*@Z57m9HDj{D@}lejEkhg07}}uh6Rkr+rfv6IZC#PjS*ohMQKppRz&{%W*{N
z;I^Bgv|)GKy9-Y4&a}0s4pPRhSW-OE^&E%@+l{V3XnT0To--a8_~~8HK8d$<n&rY<
z)h^_?uX%y{Bd)Jzk<36JYIKKgc6$GiX>X(fB0oX>pw55nLiKH?9em_Nrz8;Q(LV;B
zY(E)Kj*Ivw<38Ov-F}9IFL!~lI&MFBh9y60?(f>cM)KX<XFN0HAVt5Qnk+Ta<Rly;
zMA1q77?*f14rL4c1Y}dj2KINE5$CvtkAL&7uKS_$ev7vj?FaGx@cyp$^)s(6=q?a6
zB%n1b{!uV+4_1H9WVe2VADxEmr*0ko%u&%(=#2DdF7IsW-+`=epBuSy`swoRP~N@D
z|FHZspq=HPeCD(7k=?Dw<kjZS%Cf(;k^WrMyG&jc*DHs6iatiY@3(K%Y0tr9_3P!;
zPYf-lj?s&;*XbZXcKT<NJ7Y_kS7^aO1^-XXjs=wNzi6X${od*|qMOkBeTC9R*7JaA
z;SJl|mz^^)i}tYcRq%&>E+<gu7)XLv&$i^q_^x7H^#PYikq*4>>orFT2a*lCFJWJG
znrv{VoCD10>s<`ytm~B|;9B5@_Q<w(=`S_yD>`uM!_97=0D3I5R>s58s_`<tF2$pH
z53gDDnmK<A{!1DX6R(l0<?p`uuz5QHh4e6Jft$&6?5KyoK4-p?zag*gc-!FXRP4at
z^}f!ofXht!?Drf1nKaV-8OTOQ3a5DbJ6G%_sC~Q&05?)-cC$pCRwfvY04gP@_ukR6
zfE_OmvMJceK$dWiVRsxK3WHncTsqKbHFNtMwhG)NIgZJS7q!i3D5O!@pkZD2_A70u
z&n%?cRO^m(tFQaup<SPA9x9U&@00n>Uc~-N8KMKEa{m-1$4-Bs3*6)r`uogz`rgcc
z?|c{U_uF@L>OFGDiB#o>*1H||um0&OYW388BWJc9rhjnY6FZx%_n^K000la|vKnik
zDMgIc$ZHs;Vc?e+y%r0?zEObuXi~Y*gx)a)d)uNh4K0%J1mZA2S{gY(mBGiYb7`i3
z%vy|fk_VwrO+#t6gY16@uRg~lBw*e3FRv+}FDcplNbIhH=gG&+|DU$Ek8k5T&qQaS
zkvdY;T+C=h9YQjN84RTXNLeIBr-<UjnBj;T!n7nZikETQl%!>ccAZ}($GcUNKX%UG
zkU9Xt&#*46x-mh+4(uq2rKr11nl>a&Cy1)pmh0VRdwaK%?6yj7?u}%-x$<p(+xrYD
zCvKB=@BQPBC=dkZ<9vTS@AE$I$vhFq$j(}c#(J!s)=DSusXh}SV}-8(YojOWfXXHo
zZ^95c5lr)X%NVelx_jv-{?44Mi=CzEa>}{3<61+Yw>lr$HJdN6V4ZClFOf*bJEuMx
z1`X&p^sqkk9;j6yr6N*|-j^_-I3fs1z1KB$;WK7a8+p}@5F2s}s-6tQ2R5X7kC`ds
z<F0o7)S+3W^*EU)VP|Uv>$f`6re3E7h$^p8Ze1zg807~&az<GPb4e^Yr0!pu-jmzc
z%U>C~1c$wmmDZbW%0ysiwX5{TSnhWoJ7)wphS|2>)Kcst#huPvE9tzU>#?_Z;h>9Q
z0ZJ@0h*qZ@*pPb7s|BH%3;L2_%hClHFMw+#5J1id`%*?lYpHY4oeZd(qv3224!pI?
z+#fmO`aNzUv_3UKd%)IHy{<lM9FSf;{ecEmIZm$WcCV6g9#zEvs>YGwt7)jJST#x}
zU}-tY)}NwmRyjpSPAACe6M!9h-n`@MdM__{bFC8;nr$(u(Dz`{6n|51A&vhHh9p&~
zmxjrRabre1uxoDL_{al~8~s&a(7>Ys{{hIxKHR`!RMFwcfzAM$z8-?b0vi4~<LP}+
zITy^&n5uBV9Mm6p-3_inzyqyJIO6KUJ(_S=aZ~i;NK%7(WQ%YIG!su%8)02qX<gAt
zFW)*vGbcy?F~?9n`8!0oF(~r>NK!7o_Q;2!knviZjAUOs*6xr`Jag=G>kdP_NY`&H
zzVw}El;$g1yR-jla;P~Os`!it`eo}cJ7wz?izAR?uK_>cUFaED@(pi_IVzT&dIrA)
z6h6@Hdkrua%w4JqN&1x2`=Aaf2N)ZAI`vmww3h?Y_0ktIv7Rj;iEsV5LQD<9DMQ3s
zpj*XZ??%o(VricMOL=U3t2lv3a_}^rRlmD9A{NB}fhqTDm1F9GKc#2f%cS%jay@wQ
z*O%j$96;QK66nP>SvY-?u{m|TD6FF987B}Y9bp*A%F+m2w0jJQYhYPpVU?e8sez4%
zkc9s7y)O9Ai0G<5AY}k8q6`1yJU|huwl*#jwG|%gh(;Gvo}jbJfvFBPQ*Xli8*=e!
zmW(v;)}%UQw_4<g;YaSVlOIZJ4}NHn*uU*yf4|K=tnTXgp<8wKM|PtHs%LtfBuo|-
zX2$r{z;>qK#AYPdO*)ntH;hY;HMhlVF;c*)=e9&6u)07v{?WAR?soL(OlPJSYw|rT
zVc18px9qJ%gGaSq48=db*^kW$tlxl{%na{qv;01wZe#Q#US?%~C>S-OfOZ@L+aoHx
zCWkEeF6D<v{r!|eNaKiif@FTbLugdjFPu^YAw#5ikAa9)A+SvoVq+-W0s68pJ|f3O
zAM-p`--w_S=pAk@;?An-B(Qw3%ZPN#C|)*z)#6>>`rywcF+LOuNUR3qyA`zV=TzT+
zH3;9og=_y}<h%DPVysCtuZGY2|K}!ujNJUIG5G#PO8$5arU#zA3b6OSCx=lnpZfd;
zzyLbHKx_lx%8w&leG99=bI9!xf>hPw!L5J3nB&!0Y?A;p$gY|x_(rf!Fd!uvF+y*B
zK#$=ixCJoC_m1#>;mZA$f7tlmNB`RI_e0fjKobIe|0n<Ks_O@T_XTB0(O7~y4mRjy
zN+3@F#FiC!@K4nz7nSMsHeIO`PZ_FEx;!&TfvzQiXg}R%4egokev;?5Tq~a=7nIx5
zhl5LmzIDm6#@f;!9)A9ry{RkaUs#En);z_nF9*ZzRpaTq=k&x;3&h407SmvZ#@`0d
z*q`=HEbk-t0TC<ej<HT3Eb5WyGMQ~x?N}r}r=};{z{?Aa*PPr5bxuzj)cCl5Sdr^O
zZbhOMl*GKQBtfYaVHgv01GJ9hWo<@_D+W!-R*O#cU3|*3hDv+fdw6!hCZjpa>Kasx
z?K2;`21N^m*L`+SkGD;ahvGId)2m?rkkIyrH0Cxn4Z365$yiU@V5|C0WP!wuB~%q~
z%wbbh5iAX0D5^`f{4Z#r!^GMkdaRpwb^I@&;jnOT8<i$OYwaRpgB4W*eX&(dQt^~}
zJ4UbkYvdS(la7#R<HeFQ4QAAtNZlp6Sjt0d;srGT>%00NcF_%W(<KYCIKjRcsFg%7
z8+j4%+%Y4M%@Pw}5x5WL7J#vsY5IW8VsIF8fy;siiVp4rFhXO(V}9$d&DMglrDq1)
zO1Hi(2HKe-^R4oBJBkQCx{ggO_M$6+SWmbkGAs13hTgFit*9CmRMuM5CBO^%qcPs=
z!DdR;7ORm<{d!z%@eq?P$ZU$+NT`KUXjAig1dyB|=5VKwWW1E-V3v&q2q>4iiBLLU
zMPMQo;XNL&i?=Enxf9CY9?QU9M-xz{P~rnDQ^P%7TIa2(;&D>8@_HM^@U@tUEcA^;
zXdUnv#<>_`dyQgS4xKPgsi8-J78_L5(^fhLD9X@jS&x?;%fM75#M6*PU&7oGpDSY#
zs9L2EKLp)37BcnxDeGhZ{RN^<DPu~{!S<QOQyK#)TDJpbh-~Fk^+!l?3VN<kC8#Ov
zIG@vVXQ`7{b4V2WP|jBQ6-7;J_c^xQudA>~Di-MS5bUU`MO|;T7+Xl?=d_G*RyAnu
zji9WNBu$(kaJ>2u#Ae2qz`-{Lz;m`D)(aNJl$k37S{S6~)WB%zvxHo3Q(J;6y+$*p
zfv2APmF7jKC?=F-8w5_qw(K~7$VQg{0p3RH+!_IyH-AMRQnFKII@j9f`X5&Nl~k+w
zz_f?dSpo6>-~ih@P|(lL1dAMt`Euh9eW?$DSPko?M;AKdrS4rpH|F9dT}AQgIWb&M
z2RU6VKndNjiZo%Rj5l<{D5Ko1RL`8+CBmj;HycwXw>k_X=m;Fce6h~zH`?N6puF|>
zGeUDa+&BbZmmoeO9igNX3^@`jZ6Ub`Bo5G*{77B~mZ`E)EW!XS1FW3Yl42jo<$}-|
zI<&z+0sP+Zb)DkbI?!T2f&f%#dxZ$Fu(o~!z#JO=WrIdaz}bTckX&<J0G}cs&S(=I
zo7#opz%J`v)GOJLLDhlp_46W_(86R8i`Z76x-=!)a6*_RbYXaMrb(Y<ew8xAP!Lm+
zPZ{dnAh2GPAO~k)!5Gp;1b@ToKn*QrCt?PEqyecfQ)20Ed<u9}T(^xNk~wcs+Ylj%
zbv^qaau<?OLu~-k;=zuRk#!ImnQoV0mN5k_bJXyF@5@F3!#N~opuLOrRFox`jf`om
zk84sKBM=2vhOdLLK_hZ+_z^}==)0N{mU`j1Z-Lwq7vm9MH1xg8n>7%nG@29f?Qq25
zv<N*_O)GBBmP$L|*2qc8x2T6^Yw~KNTuj^X4OJm<wx}|93_Qb#SM`(`VL@CD;*ybp
zKqtmJsB<jL35f{z<rG{R;Cw3YF&5f@B}QVshA$pB0w_h1R{^088pqorjgf`6>x)ka
z;S4GjZLWd8X?BW^Z*t`J)qsi_;9nUBaNt>8@?e-qMw*6Nf*qSuiac^DXoF~u!;`;H
z4KrT0W1E`2rC`A@D-+g$(XWpgFJuRH0U5$5iFzqDsis-jvTDFGk<=jr!;-IW0;v`f
z+<qhhPA#+{tgn6fS5e+HN>L8C@ynK3CBcYQ$`{-D(w3nr)Q{9mjj~|{LplwfrIItd
z16<wNv@<>=)B-Zzx}!X_Mbxsgwd5F%&;$!8aMW4KXZ1O2+Lw9Mn1huYu0{n~ww@P*
zkwGi4MvRR@NiA6%5OpSEnnH7++mTFQ2h(c&|K9c|;j%)nS8TvJXrpl66a}Y+=ot<I
zM7s$BbE~(b6lh9IN7|XT>czH0Ri(ca-@q+mDVP*SBF+n5056h4LKF&1z&hn6R9=Xq
zhwd0cTu#zR;I{>-jXusxaak>)9U**M0J#ZcZW`KIXV%9h=&C@5+cD(2O$t%smVAUp
z+Z@<xi~yZ(h_&biNINM-DOE9pNyXVAs_{K~L{)N;_@aka>gzL3!bJOQB0~kHkL&uJ
zC&V{_>)dai^QA(aLFNdG!&rgp3z+ZfYevMfGIKhFbPbe?uA_K_wuJakJ3ff2)6jK5
zB5nY!M{~%IqeM}nHQKI$=#FKXEyf4*P8qfv3zLH;_p7Gh)W2yA>81ngk~U~S&Y2j|
zO?ntZQ`Uvs)n{?{4CVyg!9N%n(6bGow-}akf$WE#eUoq_#G)wr)^bdXic<pAoRgv_
zOgcX3C{bC-QS@Um2B)${YhBWDu1%K`#=e@t%m#gHkX91Ut32A8Xtti{YEiZf?g}P@
zIhcJQer#ZwxWwBmI*T1V(uY*&(?U83hZP;&cOz;fQKd+eFTxmRVCwS~MCKX$;D{Kv
zBbuO)?RE=i*xeRkQ-eDOrEwj)+Oag921p<zmz~0SZ@}nn4D7Z6Z#U#*;B7_rs+uwK
zrhX@Ba)^_h3bJ#yk98@=BgnGwW{cCjF`x^E8jWOe8(MAjv0LQ+bU^ql#&RysBE2va
zhYQyrGnEvyFWBhIiUReSL7?6m(^y8%h>6WY7}6FrOr_rL(_^xh@?<nf4|Dw_EX^5P
zG~w!yiD2+Ek61=y+A^s*4r6?Unkf|W@c^MEoQS#`tpEig8XQFtx8?wUWBh|KW1t6O
z9L*d!_w~=JaR^e>*<bKJ8Z+y@V1GsV$YR~iz)PH5dZ;vBKl0(l+xW;s#cljM?{48A
zUHQ-Y7BN3msz1r6=<fRZ&j)9x-kR38?fK3n<Kj}`ogn?Stv6L8`_15)r7y*H=6=eR
z?RUc8r!>Cr_WVcge7Q;c@V&<ApQu+RnqM4rzUbWUlnQf;yR9=#-pRqG($}m@)?#}8
zE9&jRg!%Q8ea3W+nA0DFtnsu8vi)0gYIS$=i^jNGYMiS~Cm%`$$sg)JH1rkYhd_?6
zrOM?dlC<)vF9(TrA2QAwt;XY#I-?vU-!QDJy76_Rr0!P#se99oDVsf|OZzUVm(s`R
zZR+)35ArLP`x<>fsh?4bPfpEDZC%mZpV&7*>ldN^^@WG>TTV_nWx6$O?9_j>D^2TH
zf*ZEgF!vwk^u5hjn%_vz^)^{Ir|aG=tJ`CHt#`_5!@%z0z53rxUow7VeJNf1dkbge
z&J`aEjD6>tyxnGlwc8lAp8lqB;`CDAg|`iFuVt2p`jdqlfpNQP)?L++;^bHLy$SYJ
zwP|4Y9@rlBmY@;HWSQ(o;Ld<2-fatlxk5SEZ7sCzCv8Ua(`xD=!$@2;^u@V!V%lg5
z{^sx2#XJx&ay@NZ5D%g8>mXu=0Qd>ALeh{TBNJMhdTcDWr3lq$g<hekT0K>!yXV0S
z`#QN9bZp-RAbc;P009YK({Uc7cdh!-l6eZ)bI*(0n?bE^3&RA(z{z_UTx|RTzbT|-
zo4ZyJc+W|_k(=hbQ`swY8Vv1c>r{}0dsT=AucF`p-fvy;vkL<wKr$1#lXHO4aS6`D
zB_U+K`ttnG-i3co>mREC8-CZeRUp+{&O1lB`BA%R>!|V+AKJBd>y!n})J5tvz`q?r
zq>-oYyxBq3!^xf}x~+0O2RNR-YF*lLGokN)QQf=aozL3Wc`R{rUu&vY-{b7vx_;|h
zZ@k#_V1v5z$(!YJ@+U<7ljZIIXX?@7N&D^l8&hwW0;tvwLfhlzEHnp#bL5(3y%9Lx
zxlkEmJHpRF<>Ms(;q8C+Xy;rp^-aLP$$8^>0|_wpI?o%0-wTX$<bG=;3_{f~otQ_x
z(&|1Soqa|lwSkx`&E;ZY9(?oJ=Z(9Ge!IDUKu@NDN<*|7(Cv%Ud*P1yyT2K~qG^k$
z)L(1grqHq2uW3!%7%2>y_dzJ3)pj5X-KTgAxnHE@$d<Sm>{RF48iG6C*7el=`fV?6
zH?8559dCd3#K+RZ-yAHmtLd9BUTNAF>#5%kFgtd~{MD}-uYTiv;;V@-o}MVqJAw07
zumqp~tNc0s@PD$fNjCOJnhM}u=H{VK@hebJP9?5br2rV2VO@sD&cn~{16{geq+>TA
z%o}OuRVWWPMq+bZpH%{gJU6J5SeQ%(7Q!q}8*L-%90<|gv@ucmfC_Pjvhr)~pt)9&
zwH`pSwWgl1jyYqO6o}$RZ}JOwY2i)o5Y-a!U+1k{0H*g?Y3H3k)$QZ_<clXhE{25d
z^XmFPu<qLbXU;o>jPkG2{Y&KK+Rm7@2)1{{O}$YCG5X<Wq2t|j@!`l9ODJ9gsv^zv
z#?=69cRgm`<iW%L>Cs;)RG+tA2*OB~x3K=#j4JSW63iN>k;6nJ7!ML<1#l}Dd6T7+
zpehtB!$G!;(?b^O?rEYMB!IExw?46n1X*@Pzts9phYe{PWu`Z}Vw~xL&TO8U@GcP9
zPV2E35ur}+0qqDR^pxRk$=x7)XS!-yWBBz`+lCTz;m}e-+WHL&gmjeG&+VgAcWE1j
zSGJhu4Wbs#m_qRIy?nGZ9z6UZtKWj=!5B|ej}D`kH=iHez*9!V1Zv(G03d|6@zeZ}
zBb?p{i96It+kSd7hzP0Y4Zq4m3E-wGz&qWa0xv$%{EYyjvg5fXV{gYgaF+43kJ_zJ
z$hfV;%a{3h;0<5n7Jq<lBio4Z6hVq0PxD0lMhPy^dYN!&ekc>wcROC(Teks4zuffc
zHJNlfHbr;FzWOM5?{s@L^_q3|!c2z+RhY!cmE;dh1Vlv74ieAqo3NmoZcv0#>`udW
zQsBZV-t-_yZT57~l-i#VlXKwfH!UaT+QxzP0so~XV<8xsQ&IqT`>oqS114yOYBMSi
zj9?f-(4t=e(BAAt_P-cb(_Z>PG(^IFtsQC<$2*<|6uESSQzyED&LupxV+BEBp82Gr
zLXBA=%`3)D9g%m&3R}PK+{;Ji9gCGYY!bK8?OzRpHxeatl7hbZDnD=UDo;I=9=x2K
z51t&{f3=EoW`&#1lF>H&O)RUb$H*-A#U`G7eqY8gu3D?IH1WkCA;sPe`x0_X9pr-V
zHO?84c-6RUVZ$o;<&rK0roLbIU>W*Js1`!5+jgivbJOl<a!KGdxzOw86}Rpry+Nt)
zRQj*CoPmCesOGpF?^Cwwi@{x5aYNALe&nE4NH2M@OUV_r2nIY)EygAohAm_GuR?Vk
z7z%s1b2<Oq#RNLm#B*JdQDcI8kukJzbj||0K7@OCDxx=W;IDwv$JHQNF-&xSK4O%O
z!VvmM^R*O=C3<xZi`k|EY6io~9B(F(!nH6?AH?r1^40_2Uy}w210No;JH`C9J1eG;
zHKiv@j__1_d#<1UMxO!%fXmSPmQ%J<cE<>sV%C`BJF4aa7*5wY{V-Ej3bHUZ?(Dxp
zdkRSV#;n-`sHa%wdc4D-kr#pu&@qv)-F|gYZVRv@<EAr9b)Q<i9LhNx^rm5;{F@$5
zMf^Eqf%#>gkT2)EB1S>J-o6`RF>oSqC_K*~+~ZJqF%ZOr86oS~3@kfj&zOcl*FdfG
z;)^lUN}HyYH@vcGoZ>K*(*cq+*ZI5X;&6%?_OuauvEU>k(|$x~i*51BSb%3EF;TbT
zGFccg+L~npTyhwi6~GNS4<5dlr27pcUcxF9om2&Tle8cfvuyaVh%HU@=i!*FM8E*w
zVj~bl&ae?LMr-nf<}}T$WC<<Pk=2Dkumx}Tl6E^qZwB^uO}!p;Aadx9oRihXj|{~x
z?bm>~eC0dJWm?KQMje!T#886zI2dTSZv?hh#9HxSKqv(ICHOz8BLVCRyDh*Eh@gVN
z^655M+|w#g0ByjDFp@$Z+aghL%=-+$@0qj82ku>Ck^lR?*MYWQ4IW$l{YLH`FBJLc
zx`H>W?Cl0`Ra@gdt&o2cD+d|<{V?~xkf5%f8ycWr`7T64@T=q3_pE70Z(qZ?JN^(l
zXW_+n<Bd0QAbj&P?Ehm(141j-y_c4{mCyYtVDejO`P6D?#kt;3v9-{O|FA|w|L19O
zenAfVmxzT_o)0<g?-L98!MY{EbMWI+1g?}FA;!eG<O4Af{75`7rbFx;8&cRXDAYVa
zYw|aN{O6D=B3tHxz)&yz7B~@3pEJXI{p^U(p%$?h4kbY>d4cZTzxmd86s(!|9qi}t
zu^(SORv-D^$JW{#?AvgJ93}w40)QIh`j<Z9%R)QMGqrj(PZ16U3Ib0LU{9pxs6N0O
zylvEPg`#3L_H2^uo&(s{dBHlR<<31@R*R%W@^2_^nnMDRK9Eb5^)?7*660heWCMbt
zp3AjcmxF(=9?Lb~-`G2<&9(zGx)Sc#>|7Z{*(BXH7ox@U<X&D5tyS2~oee;&g*CQ0
zp+BvwO==s^J~cYsmP8Pfr&S}FSZ64w{#Wd#5f)Ei@Yi)7uZ1e#AeJHRYW~1Rkno<?
zM!WzXJ@mO=LaSDukhHZ!;tbGeJh-BYO?F)blyD3@fN=qgut{suQfF<NYBT`S<r8$H
z0aaSK&6`#=h2bGLgg(LaNxcb_GXDz*F^FCsv}tWf^QK(lMG#IPkb6Tt>f17XQe+I<
z*d2`kyXf!|si$CKv7D@Sn+Ogf!@(P#?K>$qq~7Lf4U*Z=OaRavj}-qF7&{g$u*c*Y
z*>3EvbshZ2I;KC`8_9}U+y`6QzB+3TD7y!90D)2fNel5@K=nZsTYwWF@0m_e(Q6Ep
zh><ZwL%9CvH+@ZC)U;@;7nL~x2<(2h0Z~%7h_NBIeaF*uxlgV0<jGiG>}5jlR7aY8
zZwh|l8P8SZ7?XEk0LjYzwlfE)!Os7^!z4cv3)(&Ebc6G!Z;Ybp$DcR3!yIn}&f7MJ
zlkEvuC5upFg|~na>6?xjV#(mML1=wSB4*KzKmBP&w-wQ$8L^X#K=7x*iP!SV087~+
zW+8MbmXy)ts0U2erI`|RN_<gmz-VRXnMf>>8<tx_H}q~gU>ksEQUlEDq7jQ+4#YZm
zV*ryEOTcEQApypNDNY!Gh>%9E`WPr9korXY5JLpUde^!2`D03*uINXB2RkK3qG=8*
z0@Y3_YNtpWy!tzc(uqJJ&}^_NK-x=0ETYyZ!%rw-5UbEWpq0nyYe0I=!><Hx#UJxL
zhtwfNc$;^K#J5&MKsrTXe1S7TT(9<yl=@W18z<;i`6W0;gsgHKv2Jr^7-Z6rJB8qZ
z#SPA?0Z;Lg5i12h{`3ZKM<X7{ww62wVe^VwS5jzBRD(LDk4)w5dF3(ms0iV3NoYdm
zp=RUtl<SD+qIc)O=~Y<%Au0&db$TmFh(ouN%c*Bz+wi=c$<T*BR1_KMS|sFEc9!sR
zdxJ@=%M`tKPD8>CwfLd7nA{PWold&e6v>NfH$qM6Ado+iw%Q={GaDm3xoFJC^JOb1
zPyDxE5u%X#0Cvq-KOS2r?f|u!L0z?ofhfeX*wZ3qIaqffhJX_w&5^O_6a%o00BKQK
zMFU3%>I(F-+Cjzs0LG*?ABzOwsLB$Q7btxGkxyT-bV_kgpi!zJO#DP@frJ7A7edF?
zge!cWih&x+TZ{n2_d)*00Qf@qC36Lzi80lxmjpH)UyQ+6h52$F_6~6go}<vpK`L{L
z96tYn4rAAP(grJ_EPx3vz`P?b0F$d?1To^}@<KpN15jpB{@S4rhJ(502}plvj74-x
zv3Y$OLwYm(M`+x!kyuCxhr<I>EvrM!mrUaM(i}t9Aask*owd0`P>ZJ6zl3X1hN1j~
z71tvnfR6rzkxY2?Wf|eZM4YS!_;$-83W;f%lA^|js4x@9q@>k6feGlKak~U@e3t<$
zi&H6M>KYSakP5YayHGW_9As@+6>R7nfsX45dSk?-2o4)bAV5bv1pgc-qH{pNiHIOf
zG<{G3V=!vV3PA}9r)NNujf>%ULOntC5C#p!hx!L_7>W-0B2Z_#pygo`p+e?Z&@H+F
zWH}^%&apz4c6S2xfK;Hn<I0TZpa<Xvs}Cer9MG*ksOpF3HhA?cWKs)Ceg@bg@2v6M
zB6=>sZ1{~RBF0+Ef(6fU98V|?u+^E>xwpau$H_^~;7M2!1+;>0Ik3^<L;)cX{VlRD
z4MJ*Wk<)v)&Kuu?81z`sPa6UVz5?|Ps?}!1Fcg|az4=-~etaot2;d%T{m0&e;)18%
z<{?pR*=AY!1yUR<Yuw=)uQ#W9JTI@&idU4fqJJ@L6KL>+y1pJpP0;Zv1X()dOp!u*
z%FReoY1&VRAyhhG(~v*LQxa7JI|}$e=+><=>E}Sh<4MSsbI@t^K<Aj+<XKcti^>;r
zs3j8eO$fm|UZjL$X(CW~m7tXfv)ZH=kWq%Z&5F#UXnxr|y+afDkQ0+V0Szl+!$dU2
zQB}+mZr23n%Yh|0`feiwf-f8bcIyiTG(*cQs1bj08r<Fm!w`hu`rke%d_fHF2pAQS
z0BzW%EqAdLc3~<wG^{T{fY>8m3sMY!<Y17<)Y3w632BqF$VW{Zk%N9OCUr-K(Vzqr
zK)`|*I5fQT1Zqn7D3n#P@Vq8nNQuVvd(H^zt5gb;De+8|EcI(>0T>TeCGWvDLVD5k
zaUIh2U%5#6a%Q=R_faOf(PIvl^DdejlKZ^q%&LZgc?bal*ELk*AUTBnDr~{CXq?eV
zD87upg-qo7vu!Pljz{Z{vD-Yyb51GFB=<UH8YWlpwy?$-a!T_YB`$fLmK>k)1Sjm3
zXpa4qd#qOg=)Xa5rsEaWmr~N*CN_wZEKWEqP284+7>p&BzDcm-s@k`N_<mf#0%>wO
zo_a2gcn7dewoIp!o2G-re6Seodi!sl1=$|uRWAlPCgGQtv578`tuhAGs?9wz>Ge7+
zE|Hw1ddQNmqutq>#h+p74=F_$l)UIie7Y|1#b`TX1xxXVu&>``Js3pIC2clrbRO_~
zAsIleNKT>h0zo*3HsXt>fAeBq`=Xs){G_9Fev)*016qR(c;D(C8XH|4@A(uzbz5wx
zK41H!H>PYG&b4~u;BXBLAEL3!u+z`-q~=jtm&Qz4tZK!-b<g$<4c}YU`1b~QZ{W4K
z&S+okSodKz$NpT)mg~MsoOJi%j#Eyzv8;9c(3xj?i9J5Up8b}Yr+4%Ec{0fFRu82c
ztkL$<gM3^oypg4xeorf|SkruXsZ=*db0>of<hdUt=ZG1z=4j#Rpvl?|;Qj?z29rO~
z3t!etj|ZQho(r_QW<KCKhsbT-j0W-FG|8P`gdpn-4?e|TD_-O0m7ynM*NSvm8Kn(8
z*IHk9mXK247W1q(Rl3Y{x}#L<oJR;UPmMk4VWs+bt#716y3(ZP+*g{RFU}n8`cZHe
zKJ)Afe<0_$EFVeR<0cs;YS-Q8wLXuhyR50=XzX0)ooTEVb3a_PzD24HB|h?|`B47L
z)4RRm$zZ1VrDQ`eGJkrGq<(Mud9qh8Sk>~l(Ok6>O{CYT3qCwo-JSYaaQdA3x#{2|
z!R^7bZ{7Q$Sx8RXSj^y+4cD;UM3ksPC4AlPWx?O3TR2|rEi8Q94jOmK+cHB`&%rg=
z#nAAi)tBMd-HHY_rN&MW1k@oNm-w45KcSs3f~z!Ok9(jh=}JZ4Rnrcz#9!3X6{2=S
zv3G!W&$9q<dDRNz8`iMlqiGJmE$nO05<uGtHpV^;pHk4oQ{n5+LFzpLcDSL-G!Ss$
z)jxZk*1!EsMBO%Xo83VAwU{(Ul%3l8?fl_oJGO48cIE&G*Nc=l^{_wCfQ5FHx^^CA
zWu>+QsL2nCn}_*x7w?lu;mjvkef8yrp0V`zi-qde;Z$?UArr+)Hv;?}^1Rvl@7A*C
ziI_bDbWxdwj!3-n+2h0SFxJo$yXwueY7d^X%nm!#PV7YS%*E8Be1%u89xvX>vgfUH
zGvBKThpY3!yrEv>mt1*xC3(&2Q%75Y*6(Xj9RS$RB1E1Hmi7|cf5rNN6&8EU0I-#~
z@%3%~CFL=@tW4V8uzZ`nbL;w1sDnJCAlTiRt*7X1_@@qEn}JMqY(T52r-z``Tv4V0
zOAV(>SyQWW?>@!im958%n`58g0ajKMyyC?~0JF=;;48HXFi9maK9(l4yHgSG;ZQ{S
zuv^)RV1|dg&zS0A?`DMoDSqYRU%PV#a|VquKG7|uuG%+TmSrdSfA6ds5D`WMv>tvY
z4eB8f;ncadrxlL4f3a4CH3OI%*`JgBbxjyWg4A2xpPyB>X}8&@DBY%k!&$O#Q+!@g
zasc4zeP>Az06pAn`$Z?ym*1u#K3-wjo~`$s30fwo5srygm+yO>pWr85<dm<t92qK}
zQPe|T*1Vz3AdhbBl3T8MqpjqS>lpSu?tO_zk!OJS2R&qLt6I2enxQt!1bf}(k<RL_
zBmCv%S)==;EA?Od%t%7@dfn@w#9PhtDo(o&2y>tCJoxub9Kj!Z41Is13dVsmXaNnB
zt&e_gR=FU>?0K6V<r#hbDb!OBXjU|Kz_P4M9Ej~AL^_Cv;F48$mR{h%^kUVbBcKJ=
z@#@8FSsCMpyQ|0#mtW<@=5i?6eO9Y>Tl?Rz%NHN6Y<a=0I7R1}n;MzpvpvWlGQI&q
zzcJ{5RDTqw%zQL#brr)d0GIrJ(8R4*-IHua4Z}Q=Ie3Bv`_~19!nzj%R7!Mi9|vpH
z*r;2RL8|w`I7OkA6=$19hp%ZBNFhV0w|H~WzHe0mg~!D0#jU#dN8V12>Ece!EKfOE
zmnWG-vy~po9W=0eiXQaOd)#~25$<KrD6euR9kws=Gj43%g)@Ud*D46|Q&Aws1KK@_
zonYulDHZQQvmU8dQDmNxx=|{1$mDb$l->Lywj~FLW|c`^Am@l(O~pj?9K%c^KMfGa
zHJU-r?FTLBivC1kOn^YHuVzDF!*UF(l-OBb_3lFj9;doEPH%(TJd~=W!bxb4Z3I0y
zE`^#L9t+|}`9Tb5C@LnA_~x*SNH5Hk-E3vwteg6dHS2<}C+!yxyPHw+H{In_<Upkm
z6JM?!boK*3pVPlsnpl>M*t^TjzrlmU9w416Tq|lp=-vPvSrs9Wk&5gIcqk-q%o;o?
zTY>3cNdj_iGM+ju#V#qYBXWzl-Q6liZzu{HJok>1G$2+)V!e%m_Tla%o1?#Hiv|80
z%53QZKMFDXq8IiNOM`zyp?SEBR#ZI7(SMPGYAq(BPn4%>-u@*G<AUHzHu|@nie!tG
z)xJ=a3e^G%{_yfokG*N3E}c~GMRXDO1?^qe%}NLPJtI1WK6Mpluz>3nRv2}bKOaO2
zSS8OUOwhd-@EKm3c<Qaw*Dh0WR`HK2B%?#><TBxJ5mKCAgn~S!H*>boV#mbpC+%5&
ziVI)lDEESla_8K1k%1lTX{FHT3WsZuBAMlZ(7l<Q=2Gf@>@)<YXus)VqKO<@%+4Xi
zDl%dUO~~Ra%Re>E%rzIru;B1AMyJJhmtA3u9UQ_MNF3vPC`ic>p=r<n(P4q<si1@a
z+Cbc3tuVg5XT7Ru*giv_FZ6<8on;*!!*uvBRZ|zi^!M(xk0Y9r7^4zcb>=ehr94!z
ztvp=vy^=FY96@z`(ewHjG0f>$a>8_wtJw~*yDK(KBkF?Z#nyELuWulZllDz?AS^pc
zCV`z2zDIiylU0Ru6Jv2YZY&Z%xL+6k$=y7{O({n)b)ymoC?6@CjAF*tr}#%aVGIvg
zc*)14YBE~}I|mzrtgh7TYyzj_j(CbA)Er^aGFUh<i#Fn&30CG9N&A-NK<s722AYrA
z)*?J76BG!r<w$Xg?}oZDq9sD*4AgdnIeZrTrB#^O=(plmVYLb(;XHiqcmFNE_P;<|
zf&AuIk>7_x<hS`f36WK}70Mw$lMs0}ln|LeZ~yiv!X8`a?T1EJf#1g;haSnW@$f^x
z>?WxYv;76B=?{ly_OVKMlYty=@_xPQuRZ!c^tj<nh#IeIh@}76UXw)mW=KDOKa#zM
z9>4nsgAZeo^e+h8w{%tBBWycACv5M1>w{Q90~-!sgb?bLv7|=3e&0{@b@)=quX;l~
z!&kpuJyjL*Z~(_)cPp+W*dWoa{W}=oO?a=!>Up<b{^@Jj7_9Dp-upD%Md7&h<h4Im
zU&Ad#xaA3VKL6TrIVP3r2Pm9UG}cJ0R*wMB(dwXUO&2@V20ORdnvpB4AQG>z=#9*K
z)T=?qRI$zzzA>-O;}Sw+R!sqV!#;|>VwMNubM$W88Olkym#pF!+CxDN)ha#>ze9jg
zu_4>C`l(agFxqGAuTZ~68YACx_>$GN1;pU~a=#v5N5D9Yiv|VLQJmE$jk?J7!T$kt
z07SZs3{r5^lNm4pLV)Y+h)^aVWMQW@#0m-^Y``Y?F0WwcRR91csE%I&lQYmIt4*EN
znQ$3CP$BY?Pb|V;Idn&-@+8!RsNB!=Bf#P;Qbc5@NDO3Jpq~-MFF-&UUGP7v!fQJA
z*1x+5;BizZfbMjFz8GqEfD^fKII*bIRW)C%FfWcV1~H2eJrQSW5WAi7E+fpj$oV!<
zp5vN1?ZtCq&{Z)##~9Ui0fviH?4P@hX_uwGr-5XNwq;gr-^6ApHJ~$i3NM%dXmg?f
z`y`Tuq{Y`6LRGlF`!QdmM{|tkM1-^_DzHqu!U(JD(OOttTRpw3zfQjaAY^2zII<L&
zd8<|&wThNCu=tQ&+A(U|-4?<z(eLRLc38S_G%gF>(2(8A*QaK*+gaCu!@6wAt&?Jg
zw)`8PVsX8!k<mRt5dY7tQR-~h4$P6_v}rTeT>~%y(7j6s3X{_}#`Q!9@1|qCHSllj
ze{d4RETy<w?{qdDVQjz*LqWMv)^6)tVCo*1Izk;6FFUJ^oJ2LR&&$%~9bFp*zy+iW
z;D}0^C;;Ihx6YD$U=fopp$yyHDzP)0TgdEmw5so_>NGY;!4n5ZSA{@@YIXE_En0_Y
z*jSi=VjviX1t+HacOHjO)=bZI-8?8=`W`R3L|nSe5<ON<T&`av=AqK74Qb+z+70;}
zAF6hxIroa3mw3@a95|M{vaIl-TBkL$<9i;bi(Dm>+NT(DMW>!r)$C$-j8)9;E4Fpk
z6m7d}2F!0D?-$Q{$+UL7Ps;DKto*i0V{!ViQ?{D>u+=f><n(i9T6@);LL^SQFZ4L4
z<)j~JYm2W_V{_>SV<cjIzRfq46$n}ORVY)Vr%UQ7y$)iKuM?50b&siw%HvB<Bqf@c
zR}|APgKmt8a41j#(G?ao?CZKV`yQ#q>e>la4^r3d(ix4|U7K0H)SaEyMl7X|<=_$D
zS9fi3PAyV;g0N#Wrz~q$w@&SMEUiO_^oP2n`DHys>|3?id3CTW7Wu070?a!!g4M6y
za?Vogf|U2xKbXK=WERCx7i1!JL%c{CRW!M731btG-3Um2QJESUiScDsa0Lu9C$xDF
zZtM0W`c#HV!aW{fAK2O<D`LTZ0>XPZ>kAnPfHN>;L4~%76c|E>9+|~mL-^AW{_rp2
z)G3G=Adzt5NXG;_Y5-g1+fnXxfD;~~Qk+PD?|{DbFc+6)WF2C#3tAj^7HHrn=#Y(W
z6_uP!QM2?`E$Y>nZFB^(YPbe)CtSe<fH3!WprHLl&F}-UiRvaNHd6LC)s0?!02;)e
ztTrRX^&%{H>K;W|W_?lF?A3(up>cfMZ&QKsJmP;wds!R?U6}U_M5n-*7eC6}C;`9=
z8Bhyn(@5waWY0jCLak7gK@1ym15?GwvKbxWVTNIfg!Z=gR^Oir3u>ovAaW!a#<KJf
zX$)LLa&%wpJZfmnIdV1L&RPQ2?Dly`hzr|_jq*crs=khe!z>M=5(df<*|P;ZELSl9
zG3wd)zo4P0tz!#8Msl0Qk-|oOBr=yoL})o<{FUh#i-rLJP&G#)c=O}Wt{3z=S&0T3
zWQ1VW(H>%PP`}v@I}O3QMx&zn63nhp>6YSH)Aaex9E<cPITV{h7?k)XMU`ZjC%tf#
zl(^vX?iq$zq1&Wl%wj{H;Wt}TR*SVK@VO!(1SKGABakh;a?w(|mP|v<h&yjaiX!zu
zAP^{NDYXPbLWgX|J|4ipp>IS}b>di!duSLEUGP}Z<q`|HP?S8^gR+}A?$vPydl^>1
zH0GLl3}GR-8;4alNa>sI#(OL*M-06_Aco8nLH(R=Km{o&C)NR@6#Oa{2H)PX-f^5v
z(wuSpW2RH`0<UnTUg`@lukCoCaoj;%svaoVNPV39<{2#~k0R`f6AvF7z%-*nZ9U6%
zscW9O7`^QfEss_i2;tOEdnGn9L|Zr<ndC#fPQt<uAvlZFyEx~LL`*u;W{pHRpBBu(
zOo>8=F=tuv=RkV7{$dX6hB{k}OPHkvH*r)wg;|ncW(vFu#7_AT>8}X0!)Wpz3b7aC
z3VJIlN98VrNH7-zk3>yjYzA=5)S5sc`GHwfFvz@M6hi|_XnjFT4Ud)?L73IQ-6>@d
zeIpGplRCjL+-%~w8p|Zng|LVv(<1?mw}-H+Zyj?xtz$3&Fy=U{)3e;7ZJDNtk1*u{
zZYADk-{r8o!NMmvy-^91!!8&=r>khVJ}kOsJR$`4f|=0<bts8IWHG+!`p3VCubOo?
zQmI=pz>qhAd0S+YFITo4O%5wdN@HXsv=xLM)wHGJF<3XyJzMaM77QT}ZdTDXGQ6bm
zenug}F596yN?eRCdqM1&?ff~@8@*l=fgFO!LEWb|lNUlQZ`IgkWao%4x{Yuax_<U9
z!SjTtHFSA6h_G4qs>vyAc^UADFv@MjvM5su{Ed8;QDCj$pToWsM`d9pMB=8%XKgP_
z5KhXKd{*(Cs7$(N$h|cpctz7ZN2Xm^$jms5m62wdbNnYhuj-c#5ROoVNyFNN*1}WX
zrI$kk67X!#XL2*Aeb9W8i+xM=axJ=va+=Fm`bxaJvgo6QacoM|5bDl_rW0(EHfBsz
zAj;o$c&W6&$O5KK?gX53mXmNNpKt8rU6g~f4&^zMsqu*6i=e+}UN=P$xv>NhjKe?u
zpyQl*2Y39nXF3NN?L0@`Y+lSZ1WOG|h2_#m`;t}_0-*LEUv0ce`|e!-m8}5XW{SI6
zvN|)eq#i20OiFN!^bXBDJ~Z5WNMno^tuD_q>6AB8oxzB4g;hyi#qK4S5y+IA-exa2
z-F~rq-YsJ-bDsZx(dqt%*ILUhUM#k{#R{;uuH@COk@8|+*B_|6N6X*q3x0cgk5T&C
z&{8mAE%LoX!RLZtAUi)DOz#Qi8aLeEcCLx+zh+m<DG-6R#B)|^DE8x@Y;e52blKbT
zm^V=A94fOz>S*6M49s^pyXo)pCpW6O<X=K}d!9UI_mNg@i{2V!lh3gHPf5_B|1H%#
zi`_vc+=1b~Tpm<}W~??4SfZWe^~W^pbuYQzJviJKTH$B4*{<cB*l~u9+TCYta;TIq
zd8GsC+Dh&s&(C=G)-LvTe_wm{eC2iT%i4JNc-^=<8vN+ttG5^HD!F`Z`jpqeN2gOy
zJUe%8|1~H1aF%z27am+m3}w^SEQscJPd{IV;p`PnR?nEPV+p^fqnFV=4mPs+n~-SK
zFL^glt^Q>JeE!OJw-irkEBo7R$cOwG6<?;~j#IorSiyAH!0J9Pgsl6#uGLrUd&gXd
z9L(pBxukAK^9-qbonddDn{s<u{w%{uD}ZNLe^tZXb3V=b@KH0k+2JJ(#Xs-PLL|k;
zIjgjzlOuEbt`+b1MuNl_umS$(AarxpGCD%p>oUC`AkG#0Bm)-BgZf9S>lYkdHScPl
zaTa2Soa86?HtTmDe9WP}j~w>C<-A_i&+z2Y>RosKG_Yd>)#lefE>ApnvvVY&RZA~l
zNCE|XrA8|Ud>u-`J@-8S$X4r>+R0_MsJ?PhPD+Qnf!3ClSw;?biJp28*bTs5a*r$c
zIREVM{INH+cS!m`r3Nfhy|Chz)YuJona9q~-0-~G^%?C@%}Kq@X6^xiXq-U=EdZOZ
zJviSM`J?eq5AIbi@vGiVXtcIA4|E^So*s-{u}<zX4S5esk5B(LpG=2t{ta^pSQ!%k
z@nauYa4u83w+&&!s(YM7h`{1rz3UGS{q7_Ba5WU8_+0Mo4tV76ZFk{}|L%7XR<Jzv
z@>1eWdP2jfGYl-+1weQ)YqA@xc-WQI17~;`_NxXo+Cz{@`y0%fA@{&~P*K!_7(AUY
z{$%$x0KGt&FF+Ywf8DM2#BMCRL97+%ttkPbc9*^V#);($^iJ}h_JB_9wwes%B?wpm
z&p9wX*R*Alr6THq$6?`|O&s*xl<^ntidixYU;fBHBH)|$C>bgzW*k<TJ&KIn!<<(i
zIoWx>mqA0I`d|J=tti8PrJuK@)7QY%W@Yl7HfMN+SC<_iZ@_kXx(l-U(obFHk(a{!
z9Co=p>w4s{{Tz4Hdo%!5?yPdF)~47YH;a0|hZQQyabD#F7;b=C1}N`de{#nKv(i?$
z!Q6)*1NHp`GmW4Icreyu21oe!3lPECH_1Y5{RI0E=2!$v?2=>q*fHJW-1yXQ&MM93
zo3sZ!WBB(0XhMX;`<?;NckpNvKw8}5o_lugkXYxOd!3WLXH1iF%eAO947RU>P;8qW
zdf=y6IH-qfvU+{lT@oB0iWIhg$-U$P5k{p5@k-AGU1WE6XB&~eFcY#$0XIT{*YmQ{
zE4AwKQ2c~jIYz!1e0s=V3c~8xf5lrl1`UaxYo9UquY;8VYkTu|5OEwd&ylx+P^+ZR
zM6LA`>&Jiks|yZLOC`%BvvJzV4Ort#`jP4d67&EqWZxz?ZCf4wT=r&%eHmdX#}Ti>
zQHxlV6{_xi2M9L-wYpyZ3YU-Y(Qc@W-1Iz8od9Z=HTAL!OTs0-F^lMp-Bsm!k>9-x
z6VD~itDgXI7B->_m5VB(gQDm0?B;Y~V^+GSt^gU5M}szFfsLF~m7$@%p*FS$Q@|C_
zXyGIjykT8K3B1VehR>UP{f_?u2VZfkF2ynSiO{|n;~*7kT#ngSOQy`WnW6FI=5n_K
zt^x~J_t`V{7=cMef{Dk$YKdnVb^{X>Pd_bZp@yBGby<N(>hO;M&ayEc+_(OC*h{jN
zi=nPM>LFN~O-v(1-{WfJ)r+OTioR);)FWo{`LOw?^b>3Y!prr#wy|G9+xO+`<eIS7
z^tZJqB{R|PP!PJ^CKyku@Hyy}PVpdSKS~KiM7}g5gtF!imYSoi$<3hc3$@sK>Oh;+
z;@Y*)XaT<p3Ee_cPk)j-v!$#hA(#m0&@~30@;F2AP>dsrj}|}M9jun{EaCnfl(2_u
zY7h?~qhcTQgu_EC4_5ab4{ZZsEC0!^ieMsMnAZ)Z@{Zbw!1;Ci^BK=L%0Xt$M1*z=
zGCO=T<%l%6@M18ljD1JoajDp6Wzr;Yu$3G3fQoJbMS>OPgEPu3&&mrdAg8M#0$nhr
z)0Pa1G6)fecbsV#e32)m3>a~tu(h?hp9jt?$F3+4+#QHhcs>Y3L@3>$9`u6C`XY<>
zx&vScH<WBFv?snDQHLXxHY(7)j0jpRQo*jU<Xk6ePa`cWUm3Ag6K07#!m(<ej}<Z9
z!6Kk8OgeE}o>jVu6lDy$2$0#wI;q>EZ6Wn>0PD+zVwXu3Db}$$et%71?m#TDPP0Z8
zKZ5lc7NHB^X@x7~r6+B)H{r*BxS@_?0HBx@7aS+FsirHYf6aoBaUS6MWNito?mNTz
z7BekjBZh>G0{q1+%jihCy-xPBA_a;}O-b!;W}*!U25+$;XS)3+skDQ$S_c$aV)<rF
z;W!00UCSt1RnwqgBHs?V5DOHO-D!)#plg8rJ%Z(G0h%R7$uz)B27lM$0kvxSm-7Ag
z|FKE{hU5p3++8QhJ9Qn~Z_$5Oq2zZ%HR=$0P0rPU{rjz#e#ZW7SY!XH4I%rtYYo2z
zg8a+y+nev*#9F(_fBEG%2|?gK_B%j@uLkd|y?G<|x`%ZOl5+E(v!d6S$i2UWiToax
z3{d%>rRDKoWFr4UhTzY-ifXT6$pEn{<{zCD0C29MwrCG);4Sv^G~8W9B|GYB%mQM0
zkPEz{OA`Dvh7s59lw7Y<lRUh2Y}a!I8+Hi*$^z^Vw&dFqPU;Xd8km^jPk0G{1V5rZ
z^?zaC8XkDqtphjwg(HI`z5f97_!kbS_6nD8-W?&-tTT>U(Z0D5)w#o&*G$pPiRBkm
zbIL$ihM=D&zXuGbKYzsQj>I(=_#<I)TE-5NOyjp!c!oM0(#FKjBAQl?-&t~UKqu8)
zMeoIhT|oYFQeAcNzUlV1{S4quARt<t1+bZtItGJF0)Rup(1UVJbqq+>bo@E*u#_8p
zB@;WQN#`XvPe-9d+!HiPnHdsw1{q9C&lA={n$aa!<3It%&wwn;IrTRZVbm^6kzmk{
znj3{8XM8=S#2=<iERi}CvlFM!=v_2OED{@=Vk@T)()c2PKtl|fNC0aF12siACW7bn
z7e;8wB-h`*S72%=+>!YlWFAyuxI?enFrtYzh-8!+VyNK|0HtW*uQCnM84qZLAi5WJ
zeIb31`E;0AFjb-0JV;_#0dyU7kPsQz*`OVTj8T%~mKo>}Bn1d!2o0b<LEv^DV%EX`
zm<W6pUi85<sBzX)yEmd>u;q7-ct_Z7h=BOYGQd#OpXI3FtYPa3&KKb8sK=!i7Yz{<
zXq(<m<KSx^h%|>pT?%?{r)z2wjUHnlzhP6Ik*P~v8`u`8gc9{_))NkVRvbf^Q*vD!
zP@7<@yBIa5EOPxPZwf*YLn0VjXzK!A<6wn0uC_f>SVS7|b;^!(0dd0#%nsY212!68
zhX%~z2z&-mN{A0&%|y|@!8EopK>LxX8Hr+0<KR`IC4Vh|s0bRJ;HZnjb6u8a+Q(?8
zwuwfq+#@y!ham9@8SG~PJpv7f$n~Im4~Y{kJrl3r+)1=Zxf_+>AF~%++cPq<oyU$B
z?B@eAcPXqmq-95#-#V<A5XrvB1i6{`EYe-4wKIPJQ&3SaQ=^VY)E~bc0gjN_1b9#o
zY}SoH3=$x?7zfBUEX7$M7uY3i+QH(!*JFa&0p1)#<>pWn-4Wf5K0*%`ooJsID`EL&
z>PJB)7D!i)Qqk#+nNmswfFH9ytf^MUt!c#Nq^oSFkTX!k3@I+|YG<*uW(&H_U-{oR
z2pDM?P*(izKy9Ox!v}fc=zz*Nf?{<soeAL=Y*z%Ia)BDtHh>1TTgSY_00*&I+ws@M
z4GY#0;61oTnAI89<aQiYkr45^^I1uVON;pC2m=tuqG&5&<qCo0%eE<?C7~R>Bq(pP
zfGJaeygLf5hY6V-k^pKgCdzh@g^7ct0U_3bObdX10X?E7Elahrv{Hoyt>3YuniN$T
z2rkI7h)jfOC+Hy=d0Jpcm=HH)ub<-C7`;N8v4llI8~A~Ew&uv;0|=TZ8gg7m3d2<5
zj)++%h4*nndu(W=1Lg-~pCEkg4zxr-qhX=Bc$bOLjI7&cToT+&fI8+v9ZDe_k5Qty
zHcU}?bl^K5H%IdDD}(Rj_{#?3Bca{_ui;+O_2ti?223-mZU~FkM#5ad)x&$3lVPW6
z)@0#8WU^Cmqpob*T+jtC8fn~sd1QgR=r6#S(Ls2J#E}#?gvqjaFdpWmQG!va1&s?E
z12it2asBM?BMIPy+UR%405C3;<)*M}nu5MsMqR`?hXR&dR2iNY#YhmvI$0E`9kO3>
zXCCGw<I140h6RKJ17_To>~2`s70W|6mynY0V=aB_(D6IW@6V60JaL3~65Q24kfQKC
z{yVGhZoRBcm#cq#?Fv|*;St_$_3$M#tmNogy4F7H1Wy*pWAghRhzH=NK0ySN%-Vz3
z&P7$n<-Koi)RA2zB}4QG?iW74Lw0=Wh=o!MX|2Pm9`QwlC13pp7^Ws?BD_UIjVT72
z{H-rQV2;XxV56Z5QQXR3RM)OxURb#tyPu~zHsW1e#7a*www4VcW4LWNsY5>Kp<?Az
zcqD*&T;8jsB1nswkc1X?oS{%jujK<AeD6!dQhoooGF|;LBd^{!F23(lM*wsz1TET^
ze{Z$$LZloAS{JH66Y(-gG)Gs$_z=nxhsBFJ0iTxRybS8|*5Sr)y~TN9)51#z2@8+w
zJ0Cs5hj%!V9lwJ4mMYs+BtK)Eckq1&wpc<`?c+Ykvt<R<bwV$<g(cnO3dr4fSa7|3
z7*A7UiiR-E_})O@9W>uN0Z)b#ZGaORV1yxSCkSTex%ciLXVTgUul%hS3DbA04&JLy
z<QAVsO;JF>Bi#nlg{~nqhME4^$<6w$kKw@-woZGs9&ryJ;4sb(KlU%ZvMEd|J`yww
zx0-fb=+L;xVq{p3Mr;}rqf&;Vbj>6N7U3RT*oc_)Q8nWFBD#2Zm4L6*)vJUf9DjD<
zS*zDT#c=HsA$*AYH=o?h!Z!phCUZ%dL)s@-i)|q+HX+l8i`{?g%LRnK5wzQMREH3T
zrN=<~^DAL{fH=zPm;NQ=oiHP--$q>*H_k}kzJ2prK?uTD12@o-xQvN$>ew&+7-QpF
zxvaK++dyfrp6!Nbhs)8mqGxL#hkZi0>rd8)9G{;bYk!1o6AcWNh$9ox*S^n4t5vo3
z$Lj0q$~Sx$*2b;ldfRs){t+%k7z@|fw+{3#$MktA2rxJS?4oGv`r1_h)+2f|m%C()
za*MbEi<Iyx_$c^c1IK~_1;Sj0uhi9cFW_?zBcUf<|FbU$rup7O@Y@X2KF}y(Jaxl?
zDa`lUVY&l?t|JqnjS~-{tCI$%LOcS=4Rg2p==ghiaqWqHAKYf_t((yev(tUhJm~Im
zoa4+(v+r^cbg>|$qY9&1gKlk8_QPa&)|lyd?}9_@ks<SN_ljYHPWb=z66qjk9Vd%5
z)`5k~|GTIBTbGDUPV$)1)QQl<NY>4v5%j6B589@Kd6FJynC4&!MxR6zF`aNkZDH^G
zPF)S8zD1AVq64@N<8ydj3!|v3_pXaetCzw2iKf+oL2m6Tn2p14uD{)x8Pt-UuMf7n
zNy*;hvOUEYYb;tT0&ieg+fO1~q_T^?*m2w7gVe#PBP+(8%SowY#pzyg(#39>UgXdb
zv1PR=*6TTCKuzEIy8d9DWp+*t@;yr(PdY7Z&oaAs>s<Rz+!w>)t#fz${M^s{&(8Il
zca1p4%phMq^P_i1<(E)EXyz4A8?n7YWP9mCwY$K6#Q&O~_smE57|&U}#!qqDPbX+A
z!Gb)d>+9oY#hv9fFK{lLx#%6LVNo;2=_ms7K;w0F9&m8CxXI*N%>#e+8mqD*C>|VB
z1{V7Q#eBSaWX}NjbT3qvvp*^#1&ojL+({587~rq?S#l$>^+@*tB4wcYhcS{#@rvu4
zRoFT!-gs@y8(ntBk;Z(L6t2*}M4M7^VYnVA-hIIAvH($$wnC+bFmcWj8|9N6h;Cts
z=dd#f`<>5lN>*~R+^TrlDyVVCSizFVd62P?1A;9PY<Z?6KryT06^ds(JT?C#KF`xg
z>R4$s9|R4Exp|FVng5`Dpu3M_H5`tt;jNp^YB5`N@wkcNd9T@9!9}zAFY;4h@mv8{
z0t%0M89rNOB{nSirU}nKkT%&6E574#+<q85lHw3&QKV$`mV!51%T_RiuJCJ|pX442
zl#ldrhDi!f^iYZ6k6B?CWMn2=ExyciIB6IqI{O4bt}&usSKq;!6zkM*3<Di>HT&KL
z>;Q{$=gpco!De`|FN{uCiY=BVI8*={aNRIRN_|>!ovh@+N>`Ax&0$Mn->ShPgLGFh
zk77%(x+_4{&bmIU)(X{&g)_zR+GzKoS{@Et)(~m~yfG9L22nJEtQj5^FjkS^<wLcX
z@%%UOcs9<9XT$vEloDZw2Y%H)@EdFxvFyXq9pk5odSg6Z<=(hAQJnEm1oPZNsl3a{
zsDkoQfS-Zx8hgf89S7~2Rf-oZFsmQ)YPC}!_j9On;Pn(|VPjm~D|kqSwK-l{9v)(&
zY=T=W+(X7t0W`YWs2yjmfW29-aHdu`!$+(>UX*hdxT>RIa4T}C`*Yt1K=h!|K8~dN
zO!8S}IVhZQFM#;`GCx(Mym%7rpum5SKT#r8g$={A7aS!o3oP10`(7%X=|-X9l3A8}
z1b0Sb4RUDzVb%q-)i~Q6_L*kOOnX^$PCChRH9mq45;i=vmDS?{tSc8PZssJHThK4P
zYH7q;gnrua&Bq_gxW7>ZNhWNlKkNEv0%yDeXSLb{pYehs@|2SoN~iMlGMXxpk;GW#
zXju7KJijQ{yuzEjvU~yek8|rJ$M#G>1%<HyB@`1*L-n)Gp)?75hx6eY`d+x&!t4oE
z50uQ>0g$A~*cp`Z7&`JP{GXjFJx<U7A=de|heY>CIP7ApiE?z&uAtyu0KLC>0ZWMq
zG`=BR0r*=TIm!EY<|g8+%J4Fch27diaayosaPN@kb%Ny0FpTAJ+As*bXo9O{<v4(l
zk?(5vQt^@E1Up~Df)EYk{~_xQfF!xj`@UIfKsKqRc)K|wjTH#aCIeTaG7^Cjl3G@f
z@NP19dTei&cknSepOElSLY0>(#3XD)T9%p8OwZfB*FAl^0*yiq&MatG8Q6_z5|foH
z*V2Yf-qZkYj@L&?VWNwpSb%j&2C0jPt70lg7cJ)Zf4xV^mEi#rc{AOw-}}D*_y7Li
z_g-hrC=CJPan*bx<Re(SWO6oYzUemIH=O$}4OP8fx_bAQe&O8uiTbvNdHnTuJ9D_d
zjm=iMW+u5@KkL2MyX(S~2jhjDZh^T!z4AIU)dtR79OZ?b;Ig%W%L2E}0DI(w)kN{=
zUC<$KXPbHddE0&m04gz8T$`!#zEmMu1ptnRcJbV98U87^+%3MmgMVzM-wBuVyMO)q
ziIW#{7QgbQn3bq!!F~x&Zj^iWWRWwQLl=JSwIOJ_s^LDtVYH}C2j}C_8CKYW!GK{2
z^bh!_Jzx!3K!+7#2LMYApVJbQuG}XC#JK2&>jA52;9#cSi;ta&@0g4>1a@-#(3DqL
zq+Qo7(rZlBgL66~mp=9Hec+75B5Vg#^?22e2`FY(IOA@Xgn>>B#%jpfJpB>p6acTk
z2Lvpy^i~hfvswF$p#leFjn`*b<=0IfnxV5P8w~+0?2%Q&v-BO;Z1P+iW%oL3ob+-R
z2rG4CZ?E<CEQ*@roXOqHT`gs1*?Mi<>Nlww-Cg}RPF=7!a05k-+CG^Lfiib(YDn?z
z{D%V9r;I#nJGeIQVXRlf@WCxskj{wx)0ajkF9C)&s)LHa)r-7$aBd_1dOP$;)x*Ms
znwo!dPd96|K>DxpwI35?4|)C_R{m75jVso=byi`LC=86&W9}WdIt5>N?6EhN(%*Bd
z=iR^aYbVx06>J>uQrKwf5ixO!Nb#n<lJ`dyRt>*KjOpw3tYB4l0S!}O#(;))!p@F7
z9=i!<vuXQ=5T60^Tt{G}In#wbsM)w#9KF3&-ZN;W7|V{}{RC;*u_w~f(#5LSx=PR*
z+u5OG!PyaaZ8aFMUErng3p)#)GqSIq=NN?LrY_$Gh~q`TNR(x9x3YtG(ybwH2({kP
zIAUS+c?@@-;1!LHNs`%UeZySEBu_<-6&51-nH48d6rE(vR$+j+si6fT+j6W~;*#wE
z=l~Kb(2ScDNkF5~5$n5w5$@SFm-5X$_hAysW&3^@{^YHobNYtHE6~%&?Ym^(0n5an
zO+}$(d6#-#FU;>-?85%XpKiAsBfdF{2n3s!7bOGp_BZ80ePG^4BVCL8YX~OT2|&=y
z2?Y6T{r!D1!2FMKmGLwl6JH6$Cf3Z#3i~(0-S7%rpUoI|+yCwfBCJq{%m4p>5A(@x
z+aJq>A2$5<s>=>^5pTj+C`URpsL?+9=%d`wuXm>eA=brwE^vn9P`?0$G<`D8SpTst
zXInUAvEFalxtqIa?p(=}ko6xko?1pJHlG!F9u1*U*kR$)SKUsb8`~?rpOhas(|HCm
zaY8^?>tbt)(y~qbuCQ$}3donJEc|qtjXAw<h6@kke7*gp5X-o5>Gd=G0xM<0Yo`ix
zwagUIaQ~bw%@`pg*0%Dt=|;9-v8S^!NPQ;<f%W7@4p&W@xA;1=gjH#j09oH##IXC_
zaAg%9^~t|cKYa%1l}r1XP{p_1hJ8UU7jce5dexZSG{|mX6lss6lN{p|kgY!OG-xu#
z+>aoYv!XNTY_FMZJU%Tv1MFeLI6k73o<1&E^s+lz=lNT~_AT~xFtb3D_cy-9hiH=(
zb{6GxEP|`-DoPMq9{cQJNEiOXXa3|Pr!K-0xG-ymuMtw?(RAXGXL_>~QxHUiuE3H+
zWLS}2_kh>coL||tb&>$;*Q^3?xn{~9ub9HaH;Dk%^7_cbC@c<{<3u;jhDk>`*s!T=
zLSnb4iB+-?7mfi>CNapHX|Q}HJK$Y&;Wxr}S3bhTiU&(5*3)T8u>%k=BCzgknR^TX
zPR;BlE1$jPUI-~uvU@dPWk_m9XZ(ajHfpuTuH7cQhY=xD!0RQf8tDwM%tdWRAa=2f
zhGuq%ne?$xzQyGGc{(0!)M928(YMqH4m*_xq^p~-fBRsuw0HNzXD$F|GFsW!vAb$X
zn6br@kplWwMjO6^Ux$!4=2ku9knl@ZLuu=0#X2~2#qI?3>K8y1b4GN%e>uj<|HzlV
zQ?gCGaM)}^5v4kOgP5yNxo=7))Mel?n4Ihm2kzQ=m(nj&`^@(iwl8!z0tMKWd)3>u
zZU9@KMYjPZGq7zy!1dg<x%*$}>-vtY012emd~`vp8wD;4W{eRsy6J4P<FG@#MVQ~U
zin!f+(jbc6CjE=o%svz%iuhX@a;;HUNJzQ?Yjed8a_9s0Id=>4p1pszC|}aR@K7Kb
z%&cp%JF_~@NyHn7elhPE{d-$OSto<rUurB+5x4}AE!&wThZ*zWB}Xfoz;XGxThraS
zKiw;ewAgz|%!o@v=SVpqGl9!yhYqMzBr;5R_c+cGkie>lAhbj0amK`C9E$!JJbxIT
zI*fm2yHmFabAG+?q-LGPVfU3=C%_mp$hq_uwgfkT{A@?3Wu<7d-Pcc2qVY>wlsJAo
zF0<$Je2gXc6iZ;Xnl4Yc^sk0%7A1e@&K8&tp<#zF0A$#OY#7tAlVmahcepF@`-<Dc
zzSbZz3w_=h?&t|RXK(1)6bN*%olnz7dB%y<q@*vpu*j8g7499q4r;K(F=F%%b1Kq8
z2=%TDSrl{3tT|pc@soz>(t`~g0l!M(n6hSl-?kggDBxhBE4Cknn|uMUuA-2P*iUR;
zm`sp+bau;_TX5N1E*NlZ_#x&7c{2At{Vz|cHXQn}hf(4EaYXda@~Hu#+{9aGcJR_8
zq_Z#4#Ys9tHcQ&QeDUJ4cfA|}&ezLy3T?)v#Udgm%~M0h!6hdoeYq=5{<6Db_g#PJ
z`kMD+$gR*OwoTUpKP(UhAv$EJGN^->zSjRr7;c5(z1FXu>zrYF@ou?*C&_{-xqUo7
zBDQRJvA{=xzU#f4lFBMcR4X@?to91qX8C%n?(b+7(e1#x?+|d1R;cv~P{1l&Yu`2^
z+R_}nVb^7Ih)$A#cSNcxws!5JLUfr;%@t`45)uYOP7CS>kFWvflb`!o=gdj3)Ycj@
z0o@lHkTXwbx9ty&=xizd<%-MRc!{51=`9lg$iO(OYX9Rh8h!_Z8Fdg(%x+1h$Gf#5
zKna<ROqM|krQ_UzyD$K-l7PwbW`*N%P;0RQroZa~hcmIlL-}Yl3<tx<xgF~teD4)<
zgZc>w7T<$a2>LDAGl8<RTZ&+j%Y&uaXJISpDo(Y;T&@74Co8&OV2?OVAN$LKD_Yre
zh*V*<Kn9lqyMlH(kpNVOaP1Th5<)dOV5aX!8Y~$UEAq1>Xw7Fd;l@4o1_vfVvVJ3F
zCh4>Dd29`7#IM~nDGAV~WQ-vu#~9tgtFO7M8Y7Fy3@(MH@hCDD@&(S*#@Sl#4jBo#
zmfzyS<dC%pM)0LsYw;Ao$u3PzUf&QwMXvdZ0-MrYrL}J7o-<d=oG*b+d+wXV8%)Z(
z<ah7?7tIsvi!d)Aak(czqH!)};~bT5J^v{=>19QldwMOe=ctsW6<po}Fc@WtIC#lP
z7p<{m36Y~pqTvE!4-Si*w3GZzhsFgZggUs?L~>tmxfMW>{#14bX}!vLp)Wypi_u~t
zL(nlqXt6(e{zDXP0`fwZ0kCGwqp6o>x^t3&3l8e;#R2ySYQlMkDg>O?Sou{#D9<MB
zGqaI}p&WIi=Uwj#18y)*mR_Wfh4PaybtR5T68mFEOquNA)^jB<K56KA9gQFHDFKlY
z!jMsl*@SNm_)q`c9+3}SGW_;G`q*~;Ex8|*3S;%|QO{gHGA`@fB7F&n0Ef;!_C*G~
z6y$I}vFc^Be_^GmNR;fC*`mpsFT0ra?QJ_3pt-=%h?TgfSgQOaFt$DD%$QJ|l4tUH
zqwWZz@fkb$y~(C!k7wAK^E4^)&|28bSMUD%FSEPx2CCTc3@}aD0xaD)NE+FB8kIPF
zZ+Pw5l+F^~mlF2rWh2KrSgMQ$Wv(&q@a?0)I&$j3r8w=7VTgU|!4=8$Ps~X6ZJCjb
zx!*KrHyy5@mW~X^-`r0rH*b#1S*uPEyUL>#TGHXy9?@AT%lXo+<&U1JpOKww4uFcv
z2ucLH>FoI&(qI!I6b>8aUl|U=WpA?~9d-K`F0E<|itjVf$6aRup3fh5c>x8In(0>w
z7ZZv#13WD+&8~?r2!aAIiiZ*B<B4?VZjmPtzAiywFAs0IdyZ*Ji&tfO5WfE1*Z#t(
zPIv*!;^~eF3q~skn<gj|yXGo@`es>H92H(YBuP=U0_14rSV0~*ID_(m^dSPCkET*S
zC(=vOEdmW@g%62M;zS;-J4!WY;|}5jt=9f4xCW#C*P<3ilVlSAj!I)lWqRqskR#U4
zVS{)7pF1Zyi%<uDRoIwiZsHNsdsN=Hgw#D&=~@d93R;l~dk6$8qtkMq7P{+%=``Ee
zPrr0TPNr6%AY@|Rx?nXvQ)YMENq5_V?bt|;s3^v%d6k{;IM%WFM1gHmR}~Vj4p-*v
zSLL)yC9gmJ<8y3$Gl&`0Wkpe)i;UP`vg5_KH<qMkd2RR!cx_m_#D%LrEjvDnM~0^w
zb>0?kQ6rG8lBH>oU}w#7Jpd+y+{gty#^P3dOJ;X`9bHYq4z4o0lOy;LA@fKy>8cy%
zfkiERzim%kRDMfEgJ1GPByb>{LqFPy5^NBr!_qVEVfL;Qt0EZm7YGK_U0(lqjGo+z
z5HTPNH_c#uj}u0ANH0Jm7M0OxK!Rdjxf|uAtE3^LqjWTNCn6p#TO+!0f571W^V86}
z@3OIMJ42t^b&l6YrJr^olF!xfpZ?Oh^(nIsZSbh5pLun)%nFl~iMIq_G?4g^1+NVu
z6EGGI&j=ldKcH*9erAOLRWq&&(ma>9$?ufDsmnY8Xb?G>V=l_%VkNcT<)9F``kL!1
zmpNvw^{$HugBs<Y`@Va!95^X{{6j2&fl4pNV2{3j&Y%{uaNyT5!tPt~!MKII>B$u^
zrk^(E=~s9S<?6GrCf8eCUF|hT7oJ8WYM=&#b%cfW!L)zfg*bcfGQ?DL#9xyl?Zm~b
zLNrI#=dzFnpj3ISM>x-!tNB%kiC|gA<Sif}!F*9QrKoP3dvAWbc4o1rdI7ElbKw({
zF4;+T#8Zm8`uydw@A90ycuWxzYSqQRw7@{e$Pm@nZ@L+s<%Z2@%12@Qh;Ll64h}#J
zf@Bsj-MeN3K(f7L4}(k+&Oh^C^2^E8x7^4W<MQBYNe0G3^@?HmWf}?XCwD)1>fv?l
zRX|sf7yPj;$e2az8sG#M!*jVerLEp+h^|(CxpoPaQv7c*CIwFj8j~~t0dlD-J`L)E
ze^e5!%j#JGo;EH}s&E9D9mY~Ium*gdoOP6A#ZofAYCN<G)IsU&yrUWOQ@=t3grHc!
zS|bu_a`?miI3zSuHu*_fGK&}St9fs02&N*q!3WsT+gp(CN_d?`MaNLJ_-Z+~f}s46
z#{$oB7hRa8uM-8M!qz6chR5k~kN_G_$(~Rggw;8QbuFWpR@##ZVT}U|6AXITFF3uN
zZ{>IY^Pf;KxFDXX>-w+>4vbiL)@FZtlN19O@PW(qHdCpe???$^uU+rpbo}T7%TJ_f
zvmZ(te3D#t*-#z>Z^fHxoQzb>fi<o)@sT43+gaoBvB16%fMJkB%bsvO|C#LP*xoKC
zl18_gCiW<}<Q2myq6ikB{BHu(73FSRywS9l__A+Fh@$)s&iHcKuErY8(=Fw?1THl~
z^dPU`g<@Q>o)y!}AVY@?PhakJ5j7Y^fcKG?vRX`TqbRZeMdAe<b<O#*g8Q=bBlVo1
z8f&a<ZH$TRnt@5{*(Lz?wIQkf@;4s+*>fGbixfMmDG-B;knP~G)19qySe{}IdRatm
zGbOX4U`H(m0z=Ih^^)hpqp+HyGr4Kv+ZH;qiMQy08rDisRneEWaftz>j!Ykzf4jiz
z2oV@<pznx?wcA7?N>zlF@4Knl4pMHMuD-{%(^H#0`-MOG&|7u1+Q2^-)(Qe*g6*up
z0HNDIbcRXF`3;6nb$e@g5enl?7Un~m{W@nt35jjlz%8aFxJa<Qs!Wa?1*_G>%DOOH
zOsm_<i*>RMW0F2Ny{42=)Kw^{z}_rm`OKDTwHr(*%P+Y(TBQQ~g9m@^tqUEmlY6qM
z;kKFoq~xJT<xOt=a)~QIw48ev2_dCwbX5xL%0hQ^f!F;pvC`i0i)k#iJiboI;sJNS
z4MB^5lTl~@qGZZd5)+%bwR0J*%Qu;9BNvl5>eDS85s0-qMF9k9K;b9vtv<o#(F0y=
z`x*Pew>lw#z)Ot{53Yn~<Kv-IY)(hkQv<j1UV4{|a;Z`V79g_w=PxZ#Hzv=v(fBCF
zc-Pm=m3+Ho$ll>uv?_ybFt;pSfGmmDanmS?05)#n$81hwtQ91&1afbYV(gG4k=->i
zskB&nWwW<(gS!uw{^75lcxHNr;v|8V2lO^ni=%+`FM*r1uyBuo>r&&wzrfJ`LW2f^
zl?Ql5HckdlE=gpkH<6O2SMuLg^;#h*z{juyMhbq#aHy_ZOmEvi1h5aCTXTZqO1?hM
z4{Y6Noah*B2lPsnf8!xF0Z`ERtv!06Bq1<N{1(F9t=GVA7ZA`dGCCy7J%{8$Wx;Ke
z9`HYUo&DfUMY!7SNhTym(V1cfW1E|jg_K27xe5g_e};$T-DvT12N-L*K-v^QrXP;G
z<7R$_xD*5)vq3*DIjpZkG#1pMyS%!ynO=p+F8|;M!Ksr<D>SW=$2$b~62v`19FisE
zIkQ=~m3jICTEUVsuf_tKwqyfbx*(%D%3AKom<@*=4mA{CXcIfB`|nhed#lx~a}MU4
z<uTgIgMc|NdmXO<kIube<>P70?6Yf-T~Sg{Y)Toi$NN?;p6EOS-5`PIA$|HG5LK(p
z6oUuG+>j87Tcky(LZW&emLC-8k|vOgg_j;cSgW^5!;;LwDJ@dDq-0hmB1kC7_e2qI
zt8zBzQ9YAhVsceVZ2y*~oq-cj<d_6<J`)7MaZXuesN(6s<qyq!C~DNY@VDkiZxAEy
z7eZ<bfQf6h3f8)#RE%<>B^^x>4O0|2C?aG5DHbdn@d_Qqlxggm<7rmUUqr2U?d%Y4
z(T@rz5~$c(NsFp3LC{)@S@fjo-)5mPV#GLa#4^gt+1nC;nB&>_Xm;JaSklcQD&EW2
zuw>ecR_^}y*Uy>hY5a&kI0zqL&o#!DLd+JRvdMhOk%##U@CBdha**7?Qf;{%uRdDe
zNAq#;lG}8wylnb&7eEOzZ>$)-pJ0qla(Ur+n8Ixjjk8F@7<)wOfSdETGTiD9X3YP~
z0vm$b5l<9G#Y^_u!BV=A-%WoX;ZRsstsK}(%878F<#lfPeaG>RfLT}!uMx0Q->pSE
zN@GED2Cd_ZP1iJtKg@r+#@WaF!UkCakL|xi4iFWv1=Bbb;%;v`w@Wdx(pNlq0Aaa9
zH-_8vubYvrB1Br~AlEQoy0>-XRGnQ(LUMvHay+$k77FgRVR-f#w|6Pw?-6yCg!mZv
zwV?cfx;GtG2*wsrKs=`th^b#AItXMKqm(YhBdoC78n3sJ_mK%l;7ftAW|5B{e5G6G
z#x{1UyyVhg^O1#cLnMa7YoVlSYd>@8BWF4tkFh9~{G?lFoMVT79kp-Lpwn;OX4S(2
zIs65;CZ(wgWV8}2nTsoGK(ktQ(Z%QTm}es1_Lx?b0A`C}DExb#$d}e9Z%5Btz&=Td
zx`ZffjY;)WUh7hsg&((PoA&ISPL0w(^?>q=rYPtAalxnlXSBl$c@K-KX{j*om^3J-
z^KR~ZN5Pxe={BRt+`H*tcH8bWI6zg4v$h_!s|#%c2-@LnY$m;T<W2wwIWg*nF2<~4
z#aRTM=XrW=gXv7Hx(LL}q*L8DP{m~cXuK|O9#PgseXv;YHi6TrirjyRd0O6k`2(jr
zZ)vQ@x(KF4oXH_<d|A?w*Ev&c^_$_r68bGOtk3eL)#jrZ*c1_q8@1!Da&B3@0kF>|
zLjEnyKprDGzCpmLyKD>G?8{j5AjSDSo8s>)hXSwS0&``wvvFrIJzKbbICsUX*WOK^
z?eWHoyMOuuxp)nt#9S~=aSu~YNEBOc(_J<FQBF*QRu@PI)ZUiKX}xrSB-ePfPJup|
zBuqO2WZz~23U%%zI(N*+TPQ~@=Ez4p&v`L`(80riRcIVyzSR;mnEb4uY}9N%S?<}n
z4e~k9HF)*4@N4QX8Z3R`Gau}Az-t9*g~uu;HTfMb!-5>CYX^tS^DTFXdib9E3M5=L
z8I_Lt&C?Q&_*Eo^Fg_}GO-A9Clu&(k3BLm4d&(R@PP~lal(T5;W*q+H+CI0df-nM0
zB`{dBdBdX%$*^fAi8#mk)o(mBcxapI!PW5F|IyFfm_k7rg9unx_M<5#8)TK;?2h%u
zORwP;-Uh#*LU++sYL}C%QSojzrPEq?4VW`B)H+Q3W{DB+K?rDe@e|^0v|bgzU>1t4
z$=OYtKBed=YYQlP96QgkWyDQb0ttR?r*zCU_JcYL&T_;iENrj$Y;W%kT1`%3ZjyN9
z(eNvEo{gssH~<}>V+R%MyT{BeU-VQYTbA&3@Nqi2C<PFA^{C8s)*+PfswPY-@f1nY
zDn{DSY#{!U?i2RvuHTX-g8uBGNzqx}$%j1_$xg^D1KT;Fo~!s;y9AbdNB`s$E#v?X
zpj#!M7(YLvOUX-7s?lFJWHB0TF?@}c8E`&u4@m1SG!D*R8i|(4G)5%z#NH7)Bu701
z0Glq;&+re4f0a)uM+HwvrqEKLO`V%O+R!oV$2}d=ur<jVcO12%@j9@QD?#KHaSl<G
zfJTsH4B=1y*N@#`w;Be`)qOHyOp@h`Nr^SPCyzT2-NBHxNok$%z6ZV09K$(T4bv?M
z?o`;Hw@|lq3u{D@W4V}K*bisYv^?;P*Dq5#nLE*$RME*-47|g$1i5mEGHY$RnrgeS
zv1AZtuQE{rwci_l?DQE9Zy=s~r>6RiS~qer4V~ko4YNlXtn7<2Z5JVmr0TZ!g#}R?
zHf(|cmVDCUr-<?;Kw*ZC)-&J8!zwrGat^pvu?|*E-v&;$3n$CF%=D9ID4gn((QX+7
zX16W)Yv(zavH26|pyXT3(RuerPg1|hd3<KHqIIKAZ3g;7Das8Jeh<HEZn*L+%_aQ>
zN#WY6v0}GhKdn-SX_s*e=Nxx>6mSA?DoD6}MHL}v{ww$xR+8PZ&y&N;@vk@`u?UTf
z*87;xcG?a4({j5@hQ5trYt!#C%w<k7SbgEwK1>+&0)%9suFp)`?Ic4b%4m}{>KYnX
z*;z8&xu@i88FiWdb9zg{<)@$Km?tH3af|$#JYD=QI3)l^w^whoOiJ}f6)tqin0jSt
z;upc)<OH*;_$M#qJ1`HoUut5<2<oHG6$_lv1Hp+AaCnrL6Njsdr?3E}Qu+;3%Px)X
z=qP~*y)B~HT36=dmS4jgmS`(cNn};-)sCgq)#H|nT21#n>ovB%T)OG}`5Q!8>)lrF
z#r!UsYz(Fw*W0s4ZU+X$X+%OH5KL(=)~n#>Kyo{K(_A<6{1(8H4rxSxZAcGtxO_GI
z<oX97?N}_c;Fp8BAXs(tR_XRgd|iJX$lD`HbGVhdJjg!<k^H>NX|dRWL_44Nwwbgi
zOWf;m4Tb0TXzu5rS#J|4OyVXRYX93Ru`YDdp2{M=KIze`CR#aykFDP<W0LMGJU=j(
zt-g^y5<Xbc<#6|zUp#d|3NvKXBcr!OWj(}~DOv5*mmZs?N@E4G1yJUh1KQnk_uxDo
zTu-Zx0*50=@b}qscEhEct{>1i4at=Q$;H4mG!_?;uC-`gX?ry+=|?ER(#?+n^cd(y
zc0w#qGEV!4UEgtYrWtG)EU7}feUC%HIW9c>&>0$Oy_)7zOQ;J2DRQ&#+HE;Tulo1!
z+8p=n`Q{izF<K88^+|6>ae*RXCbKzxD;Vi50=Rl8gFZ_w*zsA9rW#9it!5P6a!>><
zdPBh%`|(Bzg=NBGRDR7jM*+4cJXztE^Eu6)PXJ}%m)y_3)p=O;C$F^#QCQ~vPBt#h
zu0d@s<4sR@-cT18=N>9Zgfw%JPC|I#y{$1RbDrO!v%F8>4&Fgaps@s2B7_3+yAj~Q
zx>+`m+@_CJB`5WWfDRRmX_$QKAa1FD2E<b6s3%z{4BH_S3z7WEFZ|pM1YL-OO!$5V
z96KLQ;&m~Gr=0ccNB*1M60=`HcHRno*Z=aR<|>O!brFD|J@s~ey|imQA`ab;$kW&#
zT+M7<x+7s?JY^~-8&c}j(Xi_>76E=CC(;o1nOgrxgnhIwG>;wzC8{9|mcS;_2e$Ft
zoqwq|m7`ROit#mBpj(M^DQr)bH|c?+cYADBNDtK9p{x=eniIxZX}Oi1v|~0Z*e{oJ
z$>I9GCWBZ^0K$&j{NB6OQT~*<Y#kK%&^fXTk5hiuApUtoaxsYmFEMb5uz1xDsObRw
z=?iB*+B?IkH#}oy51I=7!SFfHWkSo|R!OP~KjX@8EbWGS*bztpCGGa;m}9UiNAi;<
zqEnK!=611nC6_|OqVKRTT4>olzN+uUqZWvXP6jp$e0qlsX(0quSVr|t>YDkaJ$ZZ6
z#w`FdNzxAwmZ<-q2duvR3m@6W;fRSWj7RT!w@xLdJ(&d?1dW%OB|qHgy&knlsZW(f
zT)Y@VCGk!q5f{7YtFGu!ipVw{4jw2GmJTZ30=p&*Ipw(7kEQkum|8JTyp5sq&7bPk
z`Z{03)oV7nS`HX2_?Jb`66%&VdxK}rnNAP?2$V&6OXCU0cE6nE(e3<#+p}L6i^MFW
z?@~CyX0FOlwO@UO(LP;GZ4)9lF*i%fH|1WwsY*f(vK??)WkcF!#bw2*NzULT@$+tA
zanGL3;ENGy95k5$_}Rs9;%Je7M)^&r>LJm92m;`ID}0xhX&`5__mjW*u`@($A4R#o
z()dxwxtSf6vm;bcsbzka$%_EP-ZEKSC<%Q9+8)1t=4pCCrn4Zy0gpD^*`PlJ36Ye@
zkVy-xQ8(%g+s+&XN;Avv<R^VmqHqnAMXb0QFbK$p7?b6>of<&Ow$>wJ7m#8E6@#VT
z&WFy~(^O~V8GKoxxr~FX$oDPW7aBn}uVi8PwcVk{>a%&OzbmUvT0Xl>8(5toY_RXh
zq9X$>jG|zf<(A_9Toml%iD-I+aJHUOVn|Y?awMb?7UOvjC_!4Cz<R%Gq9@B9+Qnh`
z;UwfmWZ(PY1E-$xDLmH{L)I`k^=uJCGiHW+htVBwjNbDqIp#M*wl5GaXu$O|N^>gA
z460MCGa1h8fvwk_DS;`perhT_H>Sx*X)Pk<j4&Cc=^5cRzToJ3-gONK2ZagL2|W#e
zAU%MRV`A-8TQ|DJL$rOegp%_<b*bJvqeww$^8@Aw1Xy(*?5~pqWzRW0@~ILz5Ba5d
zh{iewe3^i81#F<XiVjsYy#~l?32S3*>yUb&A^VCMVGFzTu?-52b+z3L>Q!d)il&<j
z^9BwOQTNdC!t%vBtpZFKTLm%Q&76ct{XJyL!#(if@i6?W|J#YhGb~%B6Lc+xixA`L
zFg1G<^SN$l1r}G!=y`&x6Oz?v;~T8Ex5aO3%y7awXH69WTTgL)*T<1?BIa07g(s;M
zm|1jV(&S=&!)ze9PX>bEp{~t?$$ctKq27%uJ*s_{Jr#D4XU>tut-SG2W8q5gk?^;E
zf5CT}U~qy#E>3M38eXU~Y|lPvpb*qal9lf=$!f60im~2<rHk$O;51QAl1Ua7*4%Wv
zrZ-@k2o2ageL>!amDHnoQ(`U2+Gf<105zLxlKB{b1gq%UdQF|E#5PdmO+!`_uelUo
zON*DnuW6t}xqC1E9gaq3B7C2PBtBVFn<?8jLQ*Aq@g|5ytXVZYCGQs{TyUxhZw_L#
zxZ8B*z!7J%smY(BwHGN_0f3oh%4!YRc*6#gE9nrk3IJH?T)npEs+%%FGGH|^8B><P
z!^`DWmoucp@V(x5S<V|F2PD3?&^fV=mHDgUA1W>?S;%L$FaU`I_)<x=LX+j);T5W!
zUg^8i6G7up?t=~o{EjR%KZdm%-m%3Z;6@Y|iLpKmH>jEyWsJm38}Xn+hQ)zP`I^Hc
z@fs4wW7Gwmo6W^6P?L+)gI@n4b9Bp5Vefyj$Jw0WAN@i7tqW6j4#7hO5MDi>x{4-s
zHcCL3O<A`zuLtrrFP@1nK|7#6k{!S^0$c!IXYi!6A*w@z*p`8m1WWZQ5`!=f3y#PT
zx*VL%-+#k#QAuD*#6;qNu`V40bTSq=*>kx{<}4_h<PNdn%k;4R;ghsjtaDY|Ot7mg
z%34T((h?_~Z!n#0inAnQ8l-LnHWH#<ZxxDj{%P3^J1zEe@-}C`uk|hD?b)UyGbeS>
zv|-o^5i}E$J523a9_Ml97f&F8(*pdt$sO5P5nF+BK*xqk9m)2bF~8=t=W+WmeBl=t
zZ$Q<tG_{`d(<b;!q)1%c3dD4rk~mqrTYZ-nL$(g(a7y%P<`=Yn^wIkMbi#6E1q64!
zzu2D&Ra1(W00X}6*@!@r_=7-FCT2FbYcBq=%C}X$o0o`4%l2rdNd|1<oGp|r@7vrt
z$?g%PRz4lVCAsw@;eY&ZQw8!>0toxDZ-{SXmi3)%l)f812hFyjCQSO(5M76-qd$aD
zJo@}aK&sw`myJtC1o7OIi;~n63XU6_#fLyLOV!ZDW0#LR8)n8>Y@fs*?cL|RvPY3p
zx-f#Id&j<6(o1I5&@DI*cZXzS3R;w=|G|f;5}(!#Q@c`}^O250ljBfv+r%4LY;MpS
z4y&C<Jg4gKtKeC;e(6|+$bt#>M@qEmNaV=aIeHM|;F4asQE!6`nHYb>WX$a*rlBsl
zUdoWDI$|AC?YjDshYL{J&LYH!e(Q&&W<i4(W~)yCsqAwh6#U_<bUi{l_^o2TFy7P>
zSI+9CXxEc$;god*;cKCklSc@2eOg??<%{v?w9*6Vn#}ZU1g*jZeVYx=ho!<*eW+7(
zVM6wuQXe#yoTy><a%^85kf_6E#QRRD`EE~WHGw0|p+~oANr_}6>8Bkg5(3A||L5Ok
z!`2y1iOPh2rsH}XExIgtC-+-3+|Cxx&GS-kTO)EXW{5j=fz^XE;*GLp0CaAjEHATr
z?4sL&(DX5AVuHMy@rp0<7=?4#1p(9@GIzRavO_-N?b4$Lw4M#e$Z>SOxd>h9kZ%@_
zJuFLm={LjELvH@1AAN)e6m|C%e2~hE1I@xZs2YfDdigCbP8k*)C!j;twzmXvv=JOE
zJ&j>&HEl!6rp-Hi5znGpWpF}*m=KO@8qCyXEchMwoNaq~lF<<8#IOZd6$PR%3q=lR
zZudKSs3DG;7cULB{cgk4^MCk(8z-KTE%g+bu_et0q2Sn-=Z@?kZO(!5HGcbw+FnF}
z5Y$kv$&Nn$wCLC@0KtyRc6ZFiZ+3A<Ys?7-;ftye8leybm;NRT{~6c~m#t}EQx6xC
z)xZdd9o~p1C^8sCzTx^q(XTb<@V$BOE37R(Gz@?6*w5au@;?4Z%-3de?1H?&nPf(b
zL>PEYB74ktQ1_HEuZ8NGL63O)BGt7<fCi>06-l$seQ-<<y;H&0FkU4x7(4hqotPQx
z-7>)jW=ew3_9KWeP^dWWzoR&f&Mr>j{}?vb$tW`S#!J^=@86&R)W7>*N4^zG5_ZMf
zxDCLJV;4u0o9IPsG4c#ZB8s+1D%)UZFNhHuj<4xDhkg?0BbUU`HK1ZAP^8$tkF`)6
zzGKIoEXb$sEDN@UnX?$&kB$AuI000!wDjxPBhg_}WwD=d(0gU>7IHO|?ER$=Y|{g!
z#p4MDZm^#wJcQ<;#Hcr1><&&&1`%dAkPg{pdyL51{m0%7@R+j;in4nr|2kr%3y4y;
za1^ZKK4tV6p@LG9MS+_^g0>9l8RomQNwnqOy1B=P+J5P0idt1UliTbu6|d&s8nVrw
zZh-&kPjp6~H+t-dh^O>dm_o;5{$hD(imIK2@>c#MVjUej9v}!F3;Vo7kwQ>OZ+bHy
zAMJAK=96Msbhlil(gQEoFoZfpQimF;5VPl|<-n3}$mu8}GFF@&{s;5$MhpZV#VwSO
zbC7C95Kv<H-Qj}~0WW<2m;d=WLldtiSiUU0thFmkP$!lkZ91`D1Pm)pxFW;d)rE`f
zlpv197*{hImvo)S--r8%>AM^%qH$CM;i&*M*NtEdGhBF&1*9jS0QVBnAVqQyGqPR4
zhHM9Hr<P2c7cwWlK%iM!-E=4+E4{m&e{tes=QO{<=RC4BHEePnbOy&Tq)8~rAHYUl
zxfimx<9Ihc91{j`K?h~Tr0zCi9HjNF=W_bxL18xQoMI{z$9(uD=uz2<$KvPl^Lbkb
zRIDlVgQr3$d7Y11JRm(g!9Lj&O(J<Ij2t}lwb#H1amD}i|2@ZsWDu<yFtZG?1%b%I
z*SAU)NJRGvTFqFKZ8WO$_!4Jn0>M2jNI@6sL-9=QsWaJJ09;YC$K5mrS(>H*p{0zA
zsWY?#L4;&M!1b4%V3^19{=)=xREt~Zu^={W<t22-@?5kCa01ac!lir9Z=C3a$W-Vk
zTwP^2el>;Tvdxc3y5~+tQ?5O9;jlWbfa0AFS5T$sQC_%)DA|OzHCrv3dPT=7E|Cx#
zHNC#G0KdSS<55od=8wsSip)?P$8rPP47ln+z{V=G=x}QVY<tz{$O`G45DNE*`$qTz
zEwky}-~QVtF3`#qDC8)5@H@EH2vq{N-k{51Fg-;)AGn5Z?R7d1Mv)F>ZFB}GCe*0i
z2MEv4Msv$osq7Dx5!X~&XPUVl#469w_y{q1n^ci!>+@2pxdO1N<xCjQ#e?}lL#j{)
z_^WeLvi4B_$saa-V)wZ}{Xoawko;cdOAXM_+L0?MN353wjeOAYAe=^Q^hK*8Zzc`p
zz&RbSV3xT_nIs5AQwT6BO0>yPQYy6I8Z)5r5{onz+$W}!DnBxossVpb3A(ExaqDBo
zsIMg;u_dp%V@KfsRi54s9(tvCDCAt}rO&*)c%$QqafQTH7FwHhxv(v{GhK-IJad+<
zN(Tgn)r^Q4Bdi^qzKEOfhp=dB%<vT}9wz4R3<%qUqA-vu>LQK@`%^;!-@*~N;7&vb
zL7?ou;+NnWsN?akux*@jL&2l>4eFd35+HK$;R?j^E$~Navn;{ZWx~+CN!-%@L?j7c
zOD-IgnDUWYQny2VdSU;3{QBqFr`jgMSP@LIR`yCNzmb}wTD-iTOESA9CK-d(8>Myq
zI<d=Tfm6(8tTKek3Ti~(2x)FJr{Ux_vz5?X@e+L|WF4z_pLiInsoIkLVsz^`bJOJz
z+x!oy$ufd1hnYGA7o6<0_Ivae8VeWOmzr>y!e+(#B(BpwRhFDeqaHl!oILn8j6~Q#
z^urj7vdu7VyY=Y%lH~bbsKeQ-98_Q64<HgSSSSW!m-(?F12E-qfc2%Q>@>-}_N7yu
zb;Hj*2_+5*bzrli8|c@>;m~0PhuF@$?uFr6C^o5ig`B;9zB(NWG{YX7tvPuZXvT2i
zz(bb@%v&Yv;XPa!4X4QC5t-ebZDrfoi9DYF!jlC&n@3;SEmcWevdAax_;&tgdD}i!
z66e<7?Y+C&r;t-s`Q#Ua?K<X8vX5Ut2-<qyU_VFmaU>hsSV=`$0zr^z|K|&8JyW$G
zohn==oqxLRc}F$|tZe+8yGdY-Z}GGQURRK(V{VfAd^*4Hcmx=8OY&yvth|HgW8&m+
zjV9Jpn?RS_GphL|JGR(`mX`hjOI|EQ6v$r+KUIF<1R#uSD9rIAzer^UfI_?oMK7CU
z<^2Fn7#Lc}Mb%*K8uH5OHUYuxm$+P3l=))HvoXyD_(v+h0!rkQY3yUhhBP~Q$9)yk
z*>$Jp+Jes%iw!FliunK|`yf-Pd>q=9k^pXVxr3LeYm+dPNL4@h9>p%E0S}SeF=UYm
z&=<m1QXo_}t>-hzwfA~|8I6J@PzWqmxqrTzVas|DZ9!tNx4Fq+Gs1yr7-Y5bJgy3=
zPf-HxB#T;g95aI@t42vhL4J2^&YG`j8*`q>hQ<aFC>8y==&lv$YE1HtaQT;So?Act
zmiHFVuLKl)a&~4wL(EO%%i<NC*iVJSe%$oYk#wxC_Etwrm+D<Qxy!Oa(h+wqI)H)*
z{kTS>>0>l)k|dL`6i487hk`e)!pQTxS`G`S$aZQCE`w6UjhSRM3lWXDPF4_>_vw+L
zYRkJye&c~t;iAI1Pg_xrbYV_;nZ}ZhzVE)Sp>jY)y0ay<-fQpM?7c;w;Lu@P2L%d4
zB0MYdjk1?MS?)RzW{r@`&5sAtv`RQ|Q{sKZX2SJ61lllS$WpY%ok^wq3hVAL4sebv
zl*p08-Bft!u~Uq2#2yM%b&ixe__>~rX(JK!@lmNty^I60tB!U+%a||@&gXGk2>AR$
z2O6+xls5@CEojK>l57CR_%>bw#bQB2Qcxc^)DEq@Kq>0_OpR-Oy9H<>+{u7!B5SWe
zTc~Z(y-Dey9hrw+*Dqd87-^5D```P=i0~a*Ju~c0xZd8E4bgo=txcx`joF3Il^>Jr
z$)P5Hu1RKrS4hKr5YS5P>$sCgcPz(NF?Cm5mqFoBK#&j2kRJg=N%)M%bU(1=>0u9S
zp7@9-3a0!AaD($%{!jbu=(aU;CkPz$XgW{<K=$}o-aZkWX2_ue4|q?O<l(#p7tE+!
zD}ES;!QS>SrjiDP6i<+ZQj$41xw7h!MGm!&1_`oJ$=WI0?+R|6mw)aDGhMcgq#Fh8
zQ*-J(hovceg&yM}hKqLm*{}&rc|0x+sV$pcMHl;^MEJE==DpMIrSN-y`eE9r6!&Z1
z9%#-A$m)>i@>>$MF*dR~0wwAXd7Vx|((_`+wJ?4F&ciM%2ZW;Qa1Ifb38_&#B|**v
zBCgCtLl4G3?6qSsWfF5BRw<c?&Y>s*z^IVRE@WY(YO{bcPT|-`%%)IWqOaT2hB%O#
zDZTCP@9duFJp7DsQ8<1qXp%1N=jDcqbWLr3?mNe30e14O`b}A&8;tFANY|J8D_F~t
zsMmxv7=$+Na)_xSrfAffzJ?_@G=egjxSMX!;g~HJJlKwaK@Zy8n2_fec#KvC5Q2jo
z<)Eq}`E$V(KQg?wq~a|jz8luggeNf#Z&5M~9+fm7t_K+T4oQS#8OMOv==r7}Up}B`
zs0%Ar6^tKI8!6UJnd^iF%v-IsWSlB2`Z^q6+3!FcI9LO0fsrtlcE&Y(ITig#5B9HT
zc+**gMMo`8Rij9?<&BdR?6bspdVdfb%0I4g_8`Z0_>@-ydBOs^tU0&0XuH<V0o8mS
zWWdm3xG}p+msb`V4{&5#Krpi|d$F9`R*R{#;2XnK^u^SOO3+7gzalrb&*36xgH)~&
z&7J6n2MVTFVzF~TgcKssdY^?=*$wL6KkruP0{mA$Pb2GF0b&M=2B8oDk%aOF7FHN0
z^8Ncp%+=jx-0r-i7sX3!bRDcVIkTzD-b)H)Gs-To7WIXa>SrZ5*#jmp23aN-MX@S~
z`-F{M$ikj|#-))VjmI#&d|xG0d{JMwlLU>8I&f*y=ehM&mTTo6=J*0?nf<lJZE7Ci
zOC{Ab@FMaZ*WgJZru5%>bxkFYCEQSFd#V7YGm8zx7z)(1EgTN>%$ic~9v625W_8Gg
ztXIsK2P;JJ_+IHaRSdU8o?(vpn%72-gCcVbT~3lrW#+tY6QKQDVbLQjbJ*%9K6V2W
zP;UjJ)v|GG^k;babXFMRGP|F2;X_{O^KPnb=2G$D#;Zi-0}hxv&Ga&mSv@`~_ngHy
zVK@bs()22Fv0f-yIDCO09hFxx+7zga0uIb#S^alp{g9EoB(4NG_K7qEH{zKO!*`JZ
zRcfJe=k9;<Zz2p!2b77)9pvjVyI&ilqfGTDjs{TZS|ewEg}BU~X#UMX4!nYytdg=G
z;fuI@)HVcJ3L{TyQ%{E16U~i}Mwmlg#_Nr&xj31P4Mx^kW3Qg*E~up3TKBKe0T~c)
z1Rs!Pb&iDOML^gM!fT(6-dLjP;oHBq&^z-mo>8G0z~hsote9q`z_(Pd8>k`hB2)B`
zF0cKN+X3~NZj<S)ck8V3c*=HnI`|yfLXgh=QA6Gm5H7f2K%W&GW@#9iVA}!TfySX_
z$!YvYs!$fWqTDrbfGD`a6X(Se^SW&g5hMPCcTZfLZqu|HU|f27|3^y4*s^;YE2ZCH
z%8%%^O?SyTt9}D|gGJ9&6!$-|IR!RLlY9T`Zno)iW{hK8d325B__|nxWzO0O6)G_K
zc8=@9z)}t=sSYjFcYRQ<IUd&~W&<<4ZRhTmqWoakf5Y`fY{Pf{0bOc!0c6GOh{<h3
zr!8xO<RsfQ@g~<kq#+QdHVh*~%QdQsIwNIOr|1H_v`8MoklvxtnSRx|Fu+?X=A~tB
z)HT1*0-}MWI-U*LM5-4KUz3u3JXT|XPJoQ=Sx#ue?4<{9i}Srg)Y<I4|B2U6T(D<k
zJja<v9m-lV5u$Z@X{t;^59qqjrre=A>y?(7Fue5W16?`%n5s>Zg`}Wx@i{lhagF0H
zHOZAMf;ja$%+}m2+qG0t&p417TLA3*#8yj-NtHOl4Dpz0+LjcqO;o|k)^M|z^YXyE
z@BUZXLm<9^v5Q)F$(N(CDQ{vzf7apinCRq|Ha+Pm-Bof>aKRw5va6kk8<Q7o86!DF
zxJ!4iQVdxpzyUV3%h<YlR<OvuT#vL}@Kt?@SSm)u2db{Q1$47$s3<Z-jhd$sB$i!e
zcmK-o^AZi2fLM<F0Sp`E4R2+Ls-{))V63b3DBtHrhF>Lc7u$^olyb2QJ{g*%BX~V5
zhHf1qPUWybV$;?W5*1c;?o82veMpq<^>HH$$}zA0VcP9X?QIk2kMT5~r#W;fGaL5R
zbGUu)pZ>iQlo2ric%1jmE>WkRjgQKBRJmrpsow-c5q88K%>YG=)A8v1asw4gJqGJ6
zTE5tR`xXmp3UrP&@jJmidlzc)qLN1pyUb~GyM@z4xPHLqjjFm2xOxBPQX~^zg^)~{
z?@%yL4^o|^-0S_~7kL$n44jom)*;*kNzCy!lMNbkOtOQSrljz_ui#Tv9zi>}4xH+a
zat9Pm-OgIM;ix;A2=CkUWKQ8$t4Y7N&Uq-ac^)n15XlrhEy6Q=l;>V}T#Ys0TO3u;
zK3jm%4IVW6VrpR_=UzS6@xhg1n`jyf&eQI9e4ayYl5d$??oDZ+5@t!w_EdEam5S=9
zXKGl`+)LbJ-^KwdAjq9P2?ylxAKq!lvf|dhN(gXPJt*E!N*zS-GGTycCmJW7JjgeM
zA~HH_={Xu>r#d#A#R1z`XOu6}?@~>*zwy-1Zg&DAI7x(fEoq`s2y|0CwmKrQrIs$X
zx;aGcRHtKAWjD?qTR1);C4w$FGdpto9gJELf7|!)z`H7ilRo|?33<|Ox!d_xNne*E
zxO-~geOb5GU_FaT5KbWwf9Pz$Y-YXaaL54;=iU4N@)PGez9z#ovS<zcf=^-K1yWPc
zO>L~O2|;8dgVG%m%KKH8su=>xGo3he2CNI{yl$S$`$Mv335}X!4@U+Mut-E)6+NtZ
z-8^Y*myHe-J%zvesLmFTk76X#4x6VyY^qT2LH`kAhB(!~_z7Jb;*=0et%uBz<9CGW
zGv6XtH5&DqR<`0O$<PKpi~#z*yt4f$SqaRHWrTlszG3bl&!{a4o`}!*7^(@wBq^+x
zv#D#xKQ3t`Agp*5oFGsogjFJ`BF*T?nB2Y$fCUH(>70bnGuqzg{?<o(_6$53v;s7|
z;V9V~JK{%V@8n9#c*~$~)*GUcVYJH1avhZ;K@!V-{lbbS!m@BPq=WJLhMB2dK1eqS
zwl<Oc<p(6|tpd3%NnsGwOHTQ7JHSSe;&x;@Kc!#TdXjNeaR&E$d(8}T;n#^n)cZM0
zd$2?k(dTY2oIVq-Ga<rR%F%Q$=bQxX$_)YnorAeAN`VRr&N?owCk`X*`aIt)EXl<*
z#?&Ji&zCg_HuJ9$55YoKngU3zR>pwU#Fb~E)k?tAXw%VZKwben$k{wGaCj*Y2QfwL
zrAWYPab)YtQuG22!9SA^p6Q&_aRnflCYgz-gC<yEPDRlS><olh<0`M(E9qdV>XgG2
zko@BjM}F~%7O{m{^N!AiO*?Y=(rpJM%LH>TLSkgGY8eQvw6uX!3GDjK5@nM`c-$$8
z#3U=Zy+ShptSEK(L3)9?t?kmb@XA`)vyX&-^glj8{q?lSy(db50u5;VYlfaoQFTY`
zOU>29PxqL59)`$jl?~UHFS5%N_1P{Gq4HVtw&eiD*28*0yv?DA;uzvbuw`#IFa(rb
zVl#=aNo8^uU7sf$IIi!X&sz_-KmIeerANT^85>QEcBuIugxRyb*Fs*%i`y@M>cxd#
zhgCe@*Ufg;EPyplP*9=Iej_Ik6kg-(SE^VTG(Tf2XKnvHth_-!)y|@v!y&Nfc0U(w
zaehBHoW=Ls;9GDpCzj3T{h8#wLpLP)Hk27^otf@qBrcRsmf5&e(}je{UF8v<-PE2C
zY0dxLgS>fxV_(oEyu1KnDpyZpY*GsKNb+gly)jf@ZFNc!Y;g(R_yE0g?8l2DBoQkA
z3}H0ItTDu(!CK4OM8YHhj2#1rqv*)oH2HHDJi#|<?}qv?R^^aL?-)DZ0;l|Dt1Ee4
zunL1=#vy5L;XzjUd!P6SmT^N{4D^V80h?MFg2uRP2;Hc5;~G!~Ad$>WN2}@Zgaw+r
zv_pqX5^$f5^UIbDbRc@wYv4?bg;|qxXx7jxeHu;_@%1q6O}*;83#xg+x3y@3`5^PS
zNgO?&pC#29&}2*E`)o?j5R~z^|958AZyN!<8E}o2Ww7M+K&yd~|2aF3xNdb|{1d*<
zPx{TrV^}#uUd&vxmAi-oDIGN*_+GXKy^|HQ?_9wauiwub(=t}yEBt{8P&LSdTIF^1
zS~r*#IhK19b(x5`W9BTdI=gp3Rp9CUfj!shC|6b_s=!#6Uc3*hzKOiAD7TH<xqCyn
zkvjga=p`zE@aGl2nPZwnOLAcCKr-=~OK~O=HNvsas(o0NUf6}eCfGUtv=d!7KoJQ~
z2I)W%z7G{}vuWF4<9Yk+no7*-sN5YUuMMyD7JA=!j>Bp?3OByyBvWfJUUfczQ6?R8
zKpS3>_4Im+C&E+ef@!R-f@|#ETqb1TXo&e$L7t8MkOv$M3aMUx=9U}>)1()=5$qrB
zmS^2_Ik-m(#^JkkE{L--O?(e6POivqd9Yj!w>->{^Lz(kk8trs__@gkZk&ehdAU-*
z0etFRj!ZzoUjGi(t@kkCWW`V?5UhDofh}-&*>Yn9n$cin(Ms58dXqV(Mz&KpQiqIy
zB?Xoh_8sAXqXSeYS>5fL^m-X+vm)csP`AD6>8+c2!eeL%Br!$A^P32E2o>LSWRd`p
zLcrhsZ$Es-3#GnI0-!`|Yfo66wu=>y)nVi_Nj6|m@X~8ed?PzUrmEsYzl#HQr?#X+
zxSMizjDRBW2@-z|SWm?#cEO}Q<GN^a0TSO8{0S|;cHExfeavJ9d|)(1;JSkV{9?Jq
z2uv_|=(QmNmjsx5zw)J1os%b}8w(h?EP$f!>hZc(j-7t$fyMr4IeS++sV@@f2wb3n
z;?>3W(*hIfe$jZExlY0M@O?L6EVf2MqX^Fg01Y|fMhEWC!(*~}ioLAqtXq8M7<EbF
zNYhz{cX+>xc5nJL{W~sw>>%9U1nrsOFa3(ngg&iEFH6#Z`A}LH;WmsnPZ2yN_`LB@
zuA|G?JLH=kv}J@{T3QbLtfZvS0jWCq8dJoybvOB!zo@W5S8X)w=-U~D>dU1nZOCHL
zA?AtNB-+hnd25hzWZOww*&4PJKWWlUw#U-@GVDJg@o{_p>+-d?;1F1n(lEu(X5~U-
z(cpPbI85s~-rh^H_vndw0(6kRu-p{^)~E%)i{-2^-Dikhi0ABAB5{g92Aqk($S-JN
zZ<mgcLE|{?H1lOutXNsH+>(r~&W_*0WJ;RGCjGv%B8Up{=^GD`SS~Z*zx&7aGo3|z
z1B)QUH0rem3zxZ8Fq5FHVmv&88BRT`>@CA7p_J;0f<fRQ9XyRqU^77kX>fkkw3(AW
zzk8e#KbO^d!}{9oj0Gn*!z8}X%=)H_L<jKd&U{Hyg(jK&h6$cz0#Ne#p+oBb7DqX(
zBJI*r8{V7zK(9c0Sg}F|$9REAOdn@W7&I@;u+UZUlMEXA!tkQ=`@3mm2hx^S9)11e
zU>Y~7yBWw5+cz=MMc1Eu6XorM$_5y&cF^ZsbiFKh?iq8{InadEG%8)+;|W&b89wGS
zE5tEkFp*6zhNT6iNN`>Y`wwZ8?$z*n|5vcxxu|pQi5o->0!C#NiFdxU{w&$`$|gR$
zH5`U?Q+d6CndUf{3m1K=*rM~GMYp;}laUWW8%a03Z}<u1qNJyjgy_{SZ<_v=!5SzA
z(A;FS5Pm5bt|y7g<9&McW=Q}dB$Mqa-_zN!yl4u0#0USw@1E<NGXBTRH8iEJX?FBS
z+qMIR@?Kk(+z)(oth!*R0xgHM0e>E<8`pWh7N>L6=!46XZKc6FUjfD-nV?(mlFwq|
zEFba05jFd~8|QIH?PX`vx5j$d#+GFnXbMPWBqi$^RV(~%#~cp7*n8y`3CC%7_m_U2
z<DzcB-;beQQZFZpBnje%@a3edAej?_)SZe|kZedNSu&TJyljYolb|k+%h<9%vh@tB
z4P4OP=bvBh0T}cAop#9{DRDJAh0TVMt^s1Q6qmv8Dk^iWW5mEVNBLyNz41H0b-?vE
z-L?0~rkG?lcYf}#sTaTFgOo>QK%d|wJ+eh60e7}*B{_r^CwW8>N@upRJ%gjf4o<Jw
z)$MxC8Lc^eaG6RQSjA3=kM(gsHO*<@tQ;S}kmAyM)>@xic69D30>hNn6n7LN6>$8g
zbj&okam2bvx$J>Iq|LpRm%?9vos)Mi05W`0s(|7Fb3#nOy~lRLSLL}dX-DC{mT!R<
z)uFh(g|HScs5xrilCBYSX1An~L)oyOHK&dS97J<~AT{c^S>W6ZPW~LiVRXxta;sB}
zm7z*<=0f+YD$H+0!pBPuoYw4$ySDnp^g*|f-tGT$p~W*ipw}_Fb#MPxtIXc1?5ISU
zn(S&83f%SuPR~>uaL9QvY^7d)n(w1DVsLbHvd`g;b?^^i3wQz2R>yznNI6^20=`5(
z{ME9sXA5#wrnQ2%DzWx1OeK@8?=XrDo=KaE=HwcVX2|?os^~oEe(!(ynch@@NLuG7
zLJg6m%Q2Gc$ZbGb)lKGeR}MtMfLBg4XH<bmM0>CEc4p=lG^SQdi{EuqYFkDgz}1uy
z`KeXR2aI_W+2X9Zj*KOv^i2fLZ+-IU1VHJ$4sM)D6Uz_HA*(y2b29tN5QV8v=fLaq
z{}SqyFmqudk~~N?GaYP5nb!U^fm?Z3?;+dkEl6;sw5=VT2ZG_I)eh-J7CB~fNE0Uk
zUNdqcL<RtdN9XkZIuAhro6Mfi`#O#l@kk_vGakhhxwYU_AHZpRG-C`enmLRDTToeJ
zfQUELtA(unNx#k!8w6&}t(XdyJMA)AE$TH;;lVUPHS8ZZbWw|kwo|_BF3{?r{j$c)
z5P3=CcFoyaj#fOtOm@)6c_Ba=iN=8Mj10iXYg}G5p4a4uEOVd(S`@Z?06zu@m=ccW
z+)kjbQ46-J1(Ea~Wcc3spJ9f1M6AJg1Tg@aLt&_{o0$iP)M_qJA<>Fdp!MusXHSPK
zuP>>o#JEH=JMK*027x43A}>W$(EtYlL)$3da#;%lYiTbFu&UAOqWA$=YARpjn@}&o
zg3DMDE2nvf*F9Y;@$zSTyqoIo^MB(+$aZ8E=mhSKI>A|^<(Qb;IhD~|s6gxQwM|UU
zZ|kgj9rT)n)q@Kw^){m|sUOV(mT{5}-F6g0VUcWoRL05{v!avmvW7kl<M5L0O_%aS
zY9~~aw8sR^>~z99OmSI4D<>7&9b(Q^cdhp=`cXGwG2eV0-lG#dQC#$R3W<aZG{+=%
z5q%C{1x$vlh%#CwQeFdi@SfCQdT9ZN)2xK4(F#zKcFt{!%hO6r?7|s*tZWe3u*E3o
z@|vgUHZ-@FVUk1&*{X)@=hbUdn3bX+#&1*MypB(zSCf+m9%ohW{^R%P6u=FMY#wr(
zC?%$y6{T)4XRO2W9fj7O!+N$uPTT;>yBsC9%=&^ml|;>#2kQt~a4*)FhJHXn`o1UD
zP(QlYaQDKTS~F=tO1S30L=GtrJZZo0WLP&P>@kNk<ZmJ`wQb`b8QgHCK=fcqU-;BV
zJJg0T*{Yui4`Z6>@ffYUeY2tUpT>e|3RaYc9n~0rGA4ikE*MI~PjjahqK3(|M>U=T
zsR7)a&ALngGfQkB;3dSdDHk_7GNDf&Guo;`gD*-STdeMlDNx2x?cgbMC0D?M8Y);z
zQ6eic_x|RO>1RNZ084areglw!OdkF$I896S5&s6wSKgy`p)^CgrgfwV9kj~OJ3L<$
zNe+5DK)wl3AR~OhiidmorPggNI#_sK_NQ);QwiWq;Z4XOIXUyMk8`}62%A+CzPcJP
z5Z}2=cPEJ>ulBh0%O7}4X?(z<RVFJ^Bydb-g)MjWco3J;DLYR&Bp1bxGK+)<AeRjn
z7cT-I4fZcg&8(>n7XcJ1r{I8x)v9)5XaaDXl+^jmjKqRBVdQur?1L0wOPJtoTUZNd
zSjPrOZO9@kzNKS2@}U17FC~E2==jd?2gL_ZpE>yq9gTWKu#u>qJHY`BasK>6Nl*oi
za0m}elv&l!po6_VP5=DUz_X?6C*NP65m`${3qoSzEHkd|ogEHfq;{@P;!VrkzAY_G
zU1;nOVYHRQco$RLmx>bOir35AsOI7cbi)l&oDEChA@2VCkJt@>#e1&c(=1jFrYvK7
zn~f)CCbY#ZIKu-&@Wl&?^<<lvFB^J&XTiuqIoStIm+QJw&On?%Y*c(u8H=Y9Bpzk0
ze9gJqPSDdac$GlmQwkX^HV6(e#R)u^N7{89bTAw|)Oc0GDUi@Pgx5R+fE~B{8Brm5
zdPaRXDR)b?HMFHZa1%~=W^;FcLF&2>zifxp?A99=8em(c8LX#Bd_C6>GTgmtla>Ml
zg|`-ihV{d4`Yd@ZjrfjK%POxU@j)U1IgilGI{lM=*S`A5q9yiWUHM>*k_~=EeTfgz
zhz%*usco1I1*K+F^)@xj!tFE-1jjQgkFJ89c2eRqO^!Bcb3{?C$H;V3CXi6ncFt&n
z_ER(z%0T(+%8~qibT5d-=x7E&7M+{}r+0$H<?p(MQ^9Zjt)DyfFmB{4uzEzr)QA_Z
zxLijhK51eN3zpGiGns?sfvAX53t^isX$ax0fVZ{A>#j#U+jrX#BSx*|MXjngMs`1+
z)cBvD(^iu{ai72Oi;o==U`nFWY&50KdSug(hj$sl*lc~`XFF&p-cFc!C7>ER^EG1Y
zo`1(srPC$Sz}QF*cBsm~O!JyLF-2t1*3cNVSIR^LN3v_KsBu99c*d5-eiU;KjctO!
zfT~DcHEpC=ERS#a@U+;Jy?zw<08l$|?_d3e8W-|z%!NcUkxOQ@J>K+ef01axb0!Lx
zB!P^qLGWRbco0?`yHMLx^rYxh4O13~FeA`rjcZ0mi{s#1`HRK@oY~OH78p3x1X}4Q
z!hqy6>}=H8K!2JuZ%OSnssX3&eLdEBsJ?>?+~!`y4>vB6!qlbDYfqFZ!xtULQ7Pww
zB60C$UN%hb;)R`piz}whp34bpdJZlwwMsMw*rGHTIrVw*=eCvkGQz|roYfC>vaBA4
zoZ+6(BX;0tE^+|tW=}_)U+#VHzx+_Ib8NiwQ;d_wM|j!Du+tNj#h<K51$Rgz0p}_*
zft+k^>w26iVHq$cr@)chHiH}__@Cy_n@OYIPITk3b|G24p;J?%Q@@x#AGGVU05FjU
z!9av2p?`huZywe<r`2&Kj{?n6g^Lnw_E9?TWhINr`m>c&KA=>&#@3d2+X6FV%Uh?J
zF$|$mIw)~vM4C*Tfd9@Rh0{#sr$*@QLi=?5rvWv~{4#>a{oA6?#N_?-8r6rppLq2|
zo!jteaur!khk?_>X=iHMdl}fpZeckP2)2%SnnMEtU*lpmQNE*WWHl@}RwkVCq0+Aq
zKG0}IkSyCe8IbCgE@}8$j>lZ9PfIh`Fp-EgqK0z;r#w8gTzh};Zz0FZXhAV-2E>4Y
zD}Bs6TTU-Q%ZZSzH*2GPH55}+rK$n3hR3k&WR|P8bZF{rz`n%u5`W|pSf_q@e54Vy
z_ubiuoyROLX@&nnWm`O2n^4Wdcjpe7xa@t$?F8BCvyStae=u4&(eZPOx%eq-65tKg
z34XR^crRHMyNgstg>KO6E;M?;g`SrIPl>G&ie%ZZXKSDwVH0HZoP@jjXC>`Su%FR-
zIUq9bFh$HP!)M7oXkg5G(MzY4?en78fWbrX8w>Uef3zUj-~;%0qbL4nt;N#pde~6A
z_8JMMvVsaWFhw+J&2UL?H{sg3vn8vk2$|$Or>vd=s({6nlf-1DvBqXWMwrVrD$PY@
z^|=3xt(A10f+*l9TLVq-{(FC)e(b7M1N6c2S;?_s$h6K-;#F#$M#zmSib<BmymVHF
zt%Iw;z6iwFoB&&CX=By!DH#P>D(1x!GgmM{+yTipj{=t2_XBAT7{E-G4B88F5F!9a
zI9PGvYFM+sF<R_&ZumxEO;=a*P8b*OognH!2Bphm`rGb}@HM473YFS9(Bsx9!Q6V*
zqR+zZPy37SFrggb###$Um{OJrVqi$|2=>K#!v^9}3|=MBuC2>I$UmS)ib;gELrfp?
zRD1sqeuv*nsROJ1nEV@TxC#fF{TLnFzd3{;;(Wwhy6hFT235qTbz1yB%>#gTi<jO^
zE#VpFkofCqR{*zcCk)tJb{nQkHqr<Z&n}Ox3O}aY0q#xOeL`TWcy<kL(p!H2hkuQ$
z=)>wUTSbMsw-N5cLVI{wK!KM|#nN;txBw7wMBf3+S9JJ)F)Y?xqv6x7*Az3yC22+C
z+T;tYm8ORezpEa6oWph*$b|pSUnhK%AW_?R(tnMAF_;Fk=l}Oz17U89ebGU-=~xGk
z={0;k#(Wz&vdai_D%RtXZy)N4LNF3W+O6-i5<Gi`ZpzT9gC-46BJ?Q7t6=G>8<*Id
z>RpV6vFK@jXZ8MQSoQjTsZMp;dC)#9^T7>_NS1GWW9cmc7&?k=j4T&hr!j%yV0P8a
z7{0=Yz+l{jDe;7a8xh{B;rh|wjgf**L(@A8XcEw9YPE0wHaYggi$JiE9eS|9|06tL
zT;gu@c>0YX(Yt!{yY{iG?g;m%UFG28-U$|A593akO-)zJeojaY2H?N84tkAOGv+`s
zuwWM)fNK?Uj)7yZH83Xg_gDbdaa2+sz*zb~JEgoJ4I>U2b0^l=h4!h>enbK+zfh3F
zrkE2frkqTqp0SdbS;!$T(|%8#HS96+JxeNxDQUfQ@cA|c)v>EWPYJzaQFF7&I8cOr
z4b(FyE~_#)%qg+ym=~rSpJ9{CNS@c7wYspdS{Jt=md&o4ua-jG^d+}K8AGqD|E;%w
z2DO;?RC_ii=Aj>HZ|o6UC}D=YkS)Ij8`HrpKN>Pxf27D05Je4k`4Xz87##8xB7S_w
zT`w<yd2qc91}6a)Nr2VT1bEYLk*u`p8Or>o(AuWpXcQtF_(f#}T+M;}<xO%3S{QLZ
z5^P-X(?d?PTwb}G+@L4y2EeS<@PpNr9p?zmY>p13?R^6R0qC~>lC~_X(Su?oZ%bl+
zWe%?|U0QuzM9pPH8B*87a-<E78Ky?wz&MyfrjH>LPP;+YDqNYh(D3JO&R=7WmmM%h
z{FV)Rn}sOjI0Q=Vmm6V<mmQlplO8Y6{lY6BKE(m!z@MO<;LHJ3xI{iFa{)|_La6pN
z9XrHPMSc^P+QPgwoafkXe`07m8y`VOI3|VmXRFYflk<B8N1j7Gv`j<II~6Edzw9U<
zfLlhP747$@cFRL6p3|U%xNRIu3(X`Eyv!rBSfBdQhmc!xC2ZIbSLO+24>>c<sI5Bg
z<noM|eWDWGj^!3I2T3j~2YS~tP_4Ob!@v!z%u)~_$XfMpKHP`trHa>%@gaQd9cjYK
zvPn*J3Q@SD9<9=nxSmF1oDsxjUPX|K!nfxxeUIIz?B${)kl+2Qe@qUGK2SXhp~x?d
z_zn*(cEx^R3fa&Exu13>3L<p89za2r$y<kdKd51oQBNW9vxnD=-cUuY<^I_szNnyU
zx7&?+t)$T$c%p|X<fyIw8Z+bie*DMZ^G}Rv;Hepw!{E|GI-!Sjr>(4!d+R^_yMO0T
zPZ*VKWFyB$%_Fnw>!fz&uDQy8e)|5}>U}D*Yw1Qh5^f>9c#-md&CQ%VeLbW7DrOYS
zJaR$51T_N7rO^u*^UT=-oF}Zeui#o+Ol40e2QXB=;$sx#FrxaBzm1K|IQxkCHpFF?
zX90=pFa32&Hg%oUB_HG$0wF?co1Muz_afgCV1UE-0fR?`k5f><`=}|fm|4)C%((C4
zWr8S6l)#^=tAVif#PODhB#svMIQHZg5<qmUQpwW&sw#T}Nyb=2&KXxn*w7kpfI2`_
zLnpAGGao(8o4-6;tZ=7JAi~tl25kvo8lWPnNN@KLsIfhjK2DDiKm_4}H&$5+wqSxC
zxtnGu*t0;^MY%q<$@xbbEV&Z3bz)prmuQPWM`V23R-&(ZmEC6p$g5Cp7!jQrbEj8j
zZE9gSI4F#kND992+X2E>M{XhDk;U=@gpk5Hqm=mNQir^T{s?S8r++qH*)7uwchh@2
z@?bJMD$Us<mziPY!icI=<rlUVN3bivD#&>rzJi5hEW`cpXl?W%_#DXt=JYu9^=^-g
z5Yfk0KaFmETHUVyq|Lb;Y_WzpG7o=lQQGBfv|eWNVRTew%3GX^?l%Ef1}owFJ`x{v
zE<O6F2hco|-J14U-W1K|h8-7N_S++mZ_rSN(X7WLl!Z0lK?T8!)1a4N+-hP_JnYuJ
zAtp)8>n)fw0-tvB!wNQuGHS}a``Yj5U3(b1X8CxUdH#sptJDEAX|v=PG~GE)fFD*b
z+ioDr>cfK66LG_FC!uyKLb&7izw-a6MqKF&?19D?prIviS%KA1`Y0fdSg$;#`hcdQ
zMnyh(dlOUK1Ib|p_uLRfy~4pDFEPLW_us?AI82xn+jEHfMlUGNEXNR(q&)uZ@GKzG
zH=NLqmlwl@-QMWJPru(TK}~dl5(FvXM@B$PZi6)ua%H51hB_>P_<_=#c$jB<v-saJ
zYh$Y5aP3JJwVpCmPG7{Xt|I>xGV-wZ{`_Cj`Fw#m??X6O^N*Qim=BxsbiR(6`Q+b4
z&%(2!YO7>#m5}&=zFIni&BSibNhMIJ=FsJWQT|nBFvQuezh)^(;;5a`7E77Wc{oKg
z(fIH~KBUI{kNah;Z47whAy%k;{;Th~XI*|euz&P_d<+V?u3Ux(_X~oj@wA5MaL3Z(
zWDd(so(|{im8=F`Ep({xm`Jkfw&Nz&1yFmF-OgLL?V5qdz)k=#9Dz$R(i-6g{>sFc
zS>W2Z7jsFD>)*CaJOyS69$Aai+pT5qxAG&5WUw^M)EdRXET8)04|S-nQlOAwYmPuz
zGAe?>k?eHPnP4&eYDo6RyIxKyyJW}9QlmFI-C!ZXBr~(l`Awhc*NHv!#{|kP`QulJ
zDkYV|R$l4|)4lwn%ZaCf-Qix`Qgu9iz#z>s|5%JYWthJSRq4HA2%GQ!v;XXbT#gHB
zR`|3~mKdVoe`qp605+l)0|i+h^OwzXgZRqh$8=aLo!Bs`YD3PrP3|vAgnNs60qoS2
zVXYJwiI%;Te-JX%gMhE`hsl<eb8pr?nb0+JhkZ|MdeEwW$7$NhIRD~5I>qKJeKd`_
z^S;AF$;`!NIx}1VE(5XoX?h2mA$qm}B%%v%@hQ2j??PvddQ73u0?73Dts*)p6|s^)
zF~=+-9@pQCRj#X9sw6r=Jgz&7F2PeIsajRexj(pbitt%It_M%U6jM~fjS09EbQE&4
zBBT|C_bRJ9gIVTbU*|wl5_#qRrp)iSQRgf~LPRjt^3_zJ0B4lzNMqn@ih0g#&z)m}
znZpdFwAwJO!~j3S_l`7=Z<bb$z32F9@e%-7<8+nw-)E=L@o|vw63sP}9g7)Y8ju4@
zOPHegK06_{c%6?o#Ts^aO!s|a*}=az99z8HHVi@?V^}xzPKzia)sRQTZp=Z`lXk{A
zD1d3IxkOCl$t&Q*9soWBQ}S{KslbIvK33@EznBBBoB9nflcdYf>z@lrv3LTOWISY+
z?W%}@_{HrnlhnC|`<6uh>WCY;3m{wD0n46Py?Rp1F1u9iZ8|Z4q%Ct-j{~3^6R&i?
z;{fD9llFwhf&sN#a;?D-**sl%fA@#%594X{JY9JUw6Rg0agqiSy7j;;<b9PP>|#N6
zUmpi->btJX`&x-8>Im{)!bO@G9Mekn8~E2M|E6=?;uIb%W2sgvCt&IE*|)O3!DD5l
zWiH$a9u)fj{7e+-IGbb-SR;=V_d9s-EsQ}kMT3R5fo(^pD>Pch3{=EnC&kQDd}o_Y
zR0-@qC(s@Xq%fl{zJc7-92=W9{m}tgL`LXkPx+#}ahd^>W5@UUtrtm6OK#~_zTyJf
zk>3CJf3<21^3q^e917GR-yh{VslsO>n+)*(Bk%pA<hZW;&Z=fXD$tNMU2IN@Z3M0=
zG?1DRBm)rQ9V3+0U1&gs(TF5qQXV6YHK1rOWLqoJaW-79lhmtzGkD$8Ab<(1Z6b2i
zGa4!l8jeYZK7lv#3Ns$btuf3WGHv7dY$C#85-3q@kXANyejM-TRznhP$4SnK|JZZ3
zf$5p)se1L^efQlT-*@kQ_+y<@q$(DKqgI*d3SnsN^jT6j4ZF%sB?;GB6$lpW&l0iV
zxtezIm_Ri9dJYk(ten*&e=P*dNTMObSJSj}jpT7Sj`=>*Q{!>F;m5D*;|~x_Q2^fJ
zCb60ZT{sP~aZT)x!qE`l4y2LwNvw(#x)4pZg`qGjg~-yck#59-z?8{}0~}3mf=8#<
zQ5~zAO*N!Fl*1ect|)pZ?85*B(UZ?zps*)kHjN;=*>>Bi?7#VyUw$BMNUT<Yz2e5o
z3&aZeYkeA>Jd{GA*Z?LT_JHDxErN_d1enILWFO4LKQ0Fe7ykJIq9Y%HxMbTnkPcP_
zz4~#JKoF*YUqy%l{}r??*c<*%AsxobYvwgAu`Q%ZqOm$BB^yqw@A}d^n_~`TLLfKP
zE5?(W&Sm7$#x%*RKs0Gv`uI4_zZGTj`xS;F6D<0s$Og>z_y!}kZ%Fbj<n!$oxuT1i
z#T=hA3&zkC0x)(*h=gz;WJZ`d*tVp4>jWJ~UTt*>-_!Nq|Dks_$dbZXWYz*YC^z(x
z==dB(0?lQE)?nP`W5ie&+$X!@%q^=!mN&z1f(*(b=}kErjA9hRgmug$cq|aG7@{$S
zgA{G<Bhz|7AvZ?=1Z07Xj!fGosxn!JxxUDed0KU+jOm0QGaRy|^nbi}><62LOc{x1
z2faR=UY&srUnqF6o5Hqorlrg_W~%TYas^*;*cWC^^KMM(L0G6W#axVzM3kLeC)<V(
zU<?o*fys<gE(qL_te|T$Ven`NdkZN!Pf+$LBV1@aiE#e?*AS|O`^DVKOI#`R<=4#r
zEm8L(SOn%xAMepAf}*U<7V;J{AxRMl6nLWG8j={x2hJ*9;&21<^2kiPLoBWsrFlCl
zVsv+!4~2ce4cG5ua|=^`icaO$oci<^->w>hivd<5%!7i>U81-ts49?AalXJjwCb3z
zwjW38Noi$VYt{t005boYx!O~EtvfZ8niyvhWn{B{!;+Mc<V;M@G+~SvQUt%q^u4@m
zOiewSPN5n9H}KN0ZNk=a?6T>&0-P+tJK^hxK3s2Zm*DB!2%b!T0j5Z9;!TadZSVP-
zsJ=EQdUe@@Uj!o;4aWK9v(ryKNU%3{2|)R#JIB`ZMtUEQFSZs6kQ25p+#Zrr42yyw
zsyBzJSRAP3;+XrJFdsC6eG9);_!uifa4p(8ZD>vB7=TZ9mL<T7!b%UH2XY~JQ~aNi
zO-6sMbeM}-u}N0oP--`Hr1?cyL#)*n`)soN7htbS8P{SN5W$Fex_1aV!Wsm4#Wwn8
zlMpv$Vt^MN(>XAlN9~KDf=T6$Jg>s&fdil}kI#%t=r4ZjrvPoHOm(>}eMRWJ_|xv%
zVPOIO%fuD5;D!WIi;&PS(CCHX2%I&Y8_?P3_>isu16Y1440r8vEW|lIN!E`H(=#a+
z$fF3ywwN-Ks47li;J{qcUBUPFyh1@7*-Tov9e&J(Z-wKC1r>pkK9Q~;iLV(H;DV7d
z>pO~n{#SnXZEJ_O7v3eEW)UE=60_cc$Fa0uLyk-J(k=`EKXy2mu6Nx~0*%8iaIr^G
zBpm)Jg}GQ4>2OHQ$(5Ae%%|d&(r2WR=sRh)PecZ@HbnRq(4fShDYl&yQf{<xu+GH>
zgoQDK0Ep1|?4lk>IcS~B7Rw7#f{kj`-Piwhg6b9^t{}BMq0ruNJJPH>Ep_=g&v-!?
zITj5>{v(E?6dwWNRmIW3_@Ja+Z;HU!VD=HQ=o%s(F>+<PX)svb5L?S|&GzdQ!(u9~
z8)l<;>Zm|=p(fzrfdM7bgw>srDl}4d0>#{GeU<nikFzz;`2YBb*cx52pTz+xG+41z
zrw1ZYHgSLo3vC3}vi9JO0ty#oi|A95n`W!?g-~qDzVQrh2J}T_Dtz<Xmi|a;Vq-FW
zj%=v)38{A5F+9Pw;`<0QQnZ<{iImy>Pea`8pB_RbW<aq0GNGJ2@TB_O+bQkBYL;k9
zp@rne*9@_YCV7D<ddV#nzb3fZ<{MeCh<&y~Kr+NQ8k)|kvBZXIVR{VA{J@aaBw=}@
zn1^p&a!Sv~<bsI*Gb+MaP*>JEBD7d-g^_vLVDfBsDNf6hz?myLe3mN2WMtdpY;lag
z`D0&1PaTHW<X(|2q7r1Wb_Q7H-OWcNT|kQ5NaR;MP)`7c6K+<pGQl6z9!L`@%eSgG
zUDTVzy}+IGDVE9<I)LOGR&$}(rX4h8z{caXO^DAGqVzcnj#XDIp+H2M(4b}@*kwxW
zkPt4(E)tzU0DXfB{6D>79j5jZTP>sbND+f*blqY9cN&OKLM*6NP(X<0;>X&;zjA(B
zQP6>^9{MTHpJJ70_Re*ZbA+W>GcD>7FwI8fJ9CE!q{G5#auuA+8rIv|bXv7hZlitP
z+uGAH;z_<{YLqAG`1Ibpc=T}sPo=c_ub(K^8bFco!-$E5@4JJv;~EjY5@%I-7@XML
zWjbJ7$!l_Du@#lH3v){NCw9#jZ;Ev|gdFT36!4+IS0dIRf31d?;Ud}fVl4Q5H;uc1
z;ebTN^AfiMF>E3E21tMYZ!Ai(w{G8La#8q1bV|Hz_4S2c9&0)*<lDB8EVbf48x6oF
zfGe{33OhW`U1s7W>|a#hhmEDjqBkV3sra9;6Sq1Xb}KLrl$npO80o#_W6g?;543O^
z*Crj)g~|^Y)8aY=3fqpOZ9S+)uPux9gUr6HUoaHx8g8Oz(gCrkJ9@3Hl!3b9zi$3Q
z-N7Uzgj#0r8$A%VWE&Ef7@EmLWx34DQNgCjJCiC`kNYMJ!MvVoo_I>ONW^$TQ?FZj
zm*pbIw98?jE#ZuUJCFtN&$q6ti$?|pY0|ie6!du^1>t(9@KEsL<#+*h!iK$qCC@>s
z`~FX<)GvXkqwYcpdG=*-8n1P52vN_J)cG28?iEM)AYD`g79j|+U(Qw^I#DZ<vWTDP
z;BKHAB-HV9B11%owp}`0tg8_@0#=p<7!FjGiiqvv_dJfw5aG!h9hv4CI&?FRaYZ0^
zE=Wz!_!p@?D~F)W56XYXP@rNvrHaJ3V)}|Mi<0idT|z4)5|I>B(H$fTa;T1+r8X)q
z$u@}Bzng?(QBr!^g$s#fT1>l-bkCrkF=6ElTWnmc??U(_(*xbtc}Jr})7CX+^$8gh
z&y^W2)FSJXr=kP&X1s@3F4Mh2cEuv7@=Z}5i{*dt*JLJS*2D}S+5Vcf2mYz^CsI*#
z9k@~;K0{~Qa_}1#8x{%klMtWGg28Mx>AGQLa!^x;=jV_MN8vUB<dWhVLJmKbrckq!
zx^hGn?p7g1L~kJW`ZJpYDb6j+b6qH;sYqZh%HGBe9{US_?~cP9e2$89M>>?dEZRly
z=OF!sF_8*8f<pJC%;;(G5s7N{c}Zo0UAvr&p)vdGN5qnNQ`kU>YM`hct&SF)7}vKi
z%a5GW^sAK$>oNwBe316GoRBrS-a*Y1&V+rLcdi@PZ=a+(weQcVzxi+3muC}DI7}u(
zw4;o1gYE+E4t-a;N^*rLi&0%)5o*MviUm=q(#~KemC;e;kjP12Iw5^zJqTgpEzv?|
z6Xw2Y2o<~nt7g(>(NQieyxC&0BGxeD1b6PfU<gFxn2YWZJnGrr4Rf;XkH@6A{pJ5m
zZKcL2UkiC6FKqqwd{fLt)G|i97)p!AEJ0i)$-6`k7JI#73eTf7Zm;-}IeH{bMcU6|
z61usd7ARdbM$xQ(>m?9%p;xT2LI?|?cx5hDJLn_(=!;E>XwTK6-yW1(h|)E5z{f9*
zRVviK9BoZ7O4-KCx$ISg;c+{vUJkW|k&p+H(T@oX-->E;xLB_448;s+ea*~5Hkb8&
z+oBZN_|0ordyjNGVs~D}a6sr6HfMh%zroX{MN<F}Lh;rBX1Z=}8Z|U?O1Hz8r?)mX
zl*P~)yLO7n*dPEdW<ipii7K8Nj###H=}A&nBp_3Y!%<-&BW9EmP^0<VG)&z(J_eE@
z&u~R$ZbfPV+Y}N8Wxxej(H~em1XLi#af)$-Ms^va2~en5>-rk&^vqByP+T|s|0NTG
zH~ToTfB(0~wpX@Ug&8$c+^Yy3@?g5%uNeRhXetW^2DnJ%hip3*^+`w#vpI70xJ(*8
zxd6tR>OF+Yx0qEdL>ayipqN+8;uOL^nu4~9u)<MdD44~Nr+6_w@>!DUsg%tx6do#C
z*>dP|m6iN^f0MI78$g6IQ{U2HvRokm`ipT<Yk0^kAc!s*D0#jB@1+E;Emb~>S#yvY
z#1M5ar0tngX5OSO>kEp>+)7VmT{SZ-iri!mn(j9K20>+u7Hu)wCt^5=>B|OdP81hb
z3SZq8B%R{KG0uTO<Hnr1`yaP7HrCJ`x6NZFE1i~#y%<EGL<OVXWGV`1i4FZ;k+n@W
zg}B6h>fnmz$7>mIJ!|2<;eG6$obJMi6lWJXFmh4Q2-0OKPB6MMdz{tBnIe>r;hIq{
zhfo+`WO@J|!=jcn1=%ZNWQ28IJf*tqYz@kv_$M}b6>AboFT{}bA^%z0I3bW2StFdo
z0iOl7)$1I6Q_Aar56%+g=#jHR_0ZymZD}s>V)w@ljKE~7&XkBxEok&eyl7oqqt%%q
z$wKX(A+TLCY~;9>f?*I?80Q<bN0hUe^5_mRFE1)t)NMH8Bfqz0o?s<Ww_;HMabu9y
zC@8}oNdX%p4BFqc5aa~jeF$e9cs~$x<{>%)F0%^KOElMO-PhQR|C%l+(=vrxgejol
zZIS=hOF><Tj%HV+*h$5G{w8a%5Rjb!4-V%Q#?7Hf@05y`oaW`}_Uk`#gUx5mu%hLW
zBO(L?9ANaw`ypHm{JN+4CYBXUj2m*^f0eP4dxx(^t<#YWh79X)JRc0fzwROtR6bxb
zrX4eZ!pX$qEyN-nVHZ3da1Dm^JP|5Fu93zc1)~y@zMdpsOkoIA{Y~SN!q)Dt`I5zU
z-v^5QQGs?xW>VoaNtCPU$dWVjx6`d!I6hJVmv98J!HR^SZ1q7x5yYNJIL*!FAk36b
zWZ1exY(QFMqJ_n98*g86+N6Tozhs73SA}R`rH>e9ID*G6Q-pj-MPE^^H_5nLG}x&x
z%ceXU>6Ooq>e#WA3o3AHpMK)`6kBFz^}WL`bd}sR`r4kyvXIKe7&9DngOvcb)W=Bz
zD2wGBE0OtB7@@CB*GTJr^9rntltpifn(0L;)IxNA%dTcpkxL>F3)~RNi5<uPyn9mw
zyb!nXwFlA-Rs^#qln^r>+#H3nD!|@Pv-g|}ST|)%Z{cyD&1VRUaVz!L=I3j6aY`EQ
zIJ_%GWMP0I(2)T$L^Ozm#GsXHGGb0=sBdZ%!O}6atZyGv7u+_fSDPkt1N3{^zBd)r
zq$?*m<PzNj8@&I0-wuxRg8%{Fa2#Y#*=a%?;6UM|Z%9N68-y2cAWm*q4CU<bV)}Q<
z^iRjG_=v5Wn&8#PO>7K?s>~o?vIf9(#qSzjG-yu4A!5|a*~^7X!90#M1d-PWT$bwP
znKl!d#j+na?mpu`OO?|b|H^GN8+BX;uE#p$76aTm=z@)jr|=rCEI|8{(3CY*Z4^E)
zR)GpvD^%Va<~e9^lDq(L@t?4d6e|+XTQV-igbTpDZ(nlcrc{|&?2g@()xw|2$m9wp
zP?oZgM&@v4*nI?2%8u@7)AOG2TV<xj|E~8@1Z*3#PRq1fkWy5w9DTEXAGkNgo|q$X
zK_uextS}3{1#;RKEP?$4d7*0u8k6$cV)IPO!Gdf+8zd)vK{wFupSY^E@y&}Ekyxc8
zhNH`fz<h{-c+ETmLXV-<ib<VCMlOPdJ^WKp{z9^A9f-JoXVa?baIKLYNWzq}>+1({
zD^(NC%2e8DE@<}y6OFMFbUIv`(RRZMhRumnaV-rhPT!yT9yTK#EP>`BXJ%iMLskRV
zT5y79>WtTVm7{CADYM31PSeUs#$YeHe&Ktq!|q&dta+!^tjBIW!7i$l8b_Sj^r-LD
zJtuR*X6Vn@O)G4Wk<n<@=9=|VY8uuPNu%zU(uS4!tBR+oF{e(%#vwbc^MGO}v+j(!
zO`h2tt8DO{2hxL$uY}*8T6%A~YbvR;&0T4hsN=Y|xyu<VHLYgm>~z&jF^aTdI`)if
zJrFf4zh3%aWv`b_>4sGc96dHuOKSv0`3|kK0vj_8?Q1im9Zj1Xhqg9mQXSjYn3K-P
zB{EonGH<PayzYp&v#gM>ddafDECSb98y1wyY@SgrS@mSSnHHV3*6Q#O(P?&Oa|0YI
zL&#jYn(y)%@N@D^6SF2Il0e=1ceAvM?Z|sV^Sm0|)4Uys!kpfIayp8R5Jemm%~)e>
zu)18$tu#)p%F&Ap={%Qxe(7yZrL|TdE>^8x3U`%i&F0RH<j8}`&Icc^eNZ3m>6ugM
zO!~->>sV2~@7MO&d+c4M2a?*6->TIr5AHrxd;Z9j&YO)x{zexm1+Ktl#Y^av&Kzhq
za5`u1)rW?<c_^Muftq|mAW2MDDukw$1I<GRn(53V&17b#azG!7(+vVx>*<?+{fBS&
z`Oo3o-?@9spJ?SandH+EV)~X3_$(VyTYehRQ!f1G>z4mqX0sEWygRYZ`L*%g&Gfm7
zpWD`2xNACb|59xZ`+lvOcst|Aa$TuJ?()^~Rj-jg;$5wo#`yN*k-xFLtCXfk($d(2
zHKk5784VorO0&^CdUwTb)GLp$_$;42sKfEw{APACZKROyk+tNgeYD|J5Aazn)^>Ji
zwb3~2X5|aD*l+yNPrbuyu8u{OQoZy*l#D%|Gm!a2rcBknE8eN)Mr|SWoMt#S<z>fK
z@<Zmq8f#nqrCQK<xR$AXX+1B^{6sZMVn+wgjBV|x!SKzxh7M!Eafjnv+18}5o37Uk
z9Cc_|$?i^_R?RrG{jkwuhsHX3&w<K!n|r?gg?|eD%DPfYz-FDbxyDtm?##G{r#u~|
zVaL|N0kYB4t`h)fHqRks%C96|<wE6wn#QQz-}LV51deVf&VRjj-dD-d@_|Zn)wgEc
z=8@Pw<Ysni9k-fUxmK?AV&$D~%r%&>qjqD=IZB7~VkSS*`L?V~7*WuWavoX39lx%X
zot0TwEDS#!x0@c@f+Vvj2I{Ad)oj~-bFM*!R}FVKO=Z=4T5iDR=&I0>Yc1nNmKEf7
zwx63VNw$ftC}V|pk#v!b>W}`x3z>a<lzi22>#?nkrxV{A=gErAm6lCXxaa38I4=>@
zp*_QqctlH<r<$`0`@E&LjyqP|YE)`vciz!D!6qGN)Xlm4kgdHIQc1;Q4nq<wExv<$
zf|bw<R34TNn(*n+vR?duwsBHqgIGOfF)FRv<vsRQU(*r%ENi@UK{bP224Z>V^w=rY
z2;7D@4tI6SP4`@L%#ZD(<$-^$V(qPU*DCY$q-$&4I*F&4*$<@k-UY9lLz+m(=W1id
z=D&^uRk9+lYkP4kDosrdJYQSyKk$weqfP5wZq2Xz+CJ0NGsfP~-mj%v=dId4-|RZo
zP!yB;a@?5ewo6AGoX0dgQ)%FM)`scWu<41RTe<eBYmHjN8Pj%sP&<0Sx4z^gP4Y^$
z<+Ty6JDMM?9962kQJGnb=hmzZ<|6a`Re!v8s^RBVx>JqH1CMPbWlx%|{cyMYkr_8|
z=%wW&MGrHJb!c)m4Z?EA@samAe}=VYpdFe^S%+#mw85+z@PKUvcOz517SC?7OxULq
zkqcL-K-szW&uzE-yrXQcBrEHjw)(!l^{+4S_j=;i#@wUK#Dcch(9cIhSisCRRA}us
zVfr@sY78Zc<gdC7dgH>E&7fQ<9kPiMn%8CLkPe+}pRXbAxJIb@^#eXyv*{nQ2U$5T
zdG*@XD-BC8=zRy2jw92Yv9rk7L3I6Nccz?hpo_TbRMf)P;zm)Vo(`gf$9pll8QX_H
z5hN&AD8I=D2Q1wfi%Wg1x4L6l0U9fA&M=4>rAi95!>24LWyO$~Fqyby`RDvNc>N#z
zRA2|XVz?>S7dK4X)kz+-4f`&2OyObHCKR&g<w1POw~Rmb$XbT!<HIJ?jUP<)nTod|
zW~6%+tfb;X%t9#1H~g(RW|;^1=Zx_Ko*S|}pg5$@cB<T+4FB-C7ZC~a(W|P~aQ(nx
zb;n}Yi6WL)7RI65x@Xu6;$7_LGN%t{FW6^%YwT3oM}oLKmeVeshIO@4+(G_skLx7X
zC}a9X4EPM2$8Ei}{pG7^_7uh{8L^?u!4|ofx0X4fD{!y+0a_jpAk`|#kGKow@DyRL
z=>k?YQr6ENBrnGap7MizB3<%@xNP>BGrDW9_x-tc4^gZ<sF%}>b<S9MFR<Cq@u9bC
zGGhm-Q_7Gnkrn^ZildLDuC6v?tk+%J^0C2%_287sF-ZA@Q_0tlw^o&(Bwv;zgs0MH
z(zqPg92L~UP=&n|iQBK_eLu+$J))8zWDllhL&#T+&Er)cmOkw6NEuwh;Ioo+$+vo_
zmE1=H=LcQz8!zgFZ~n{UbK1iKvWRua;DHoJishCemHEv|by|&=wes78O4{_3whQx-
z^9_?Wip^*iC2cD!2(b#WY_9tLv|6q_kor~>xJ8;P02iIg>Bz;Bl?S*y`K_P*b-6g<
zEpxPi0a(zqBc>5^lPzn0Y}VZdrs2K*!o4%en6sAwV0JQZwr}{{T{2vexpg<;`P`}d
zeh%NU)5&1?AP!2F_xqD0o<!@#%MCu2_UlXo#Ic5>haOVSCy6xiFf=)adFz<d=*=_u
zrfPUIuHR^6_MD<sKclHSskqGIIRk1Zjmev}5_5);d+RqYWvW&SwUcSh*1pPER?Pj?
zbhiD7S!`TQdnrcNma5+H2_AIE9#3n7^wACA-6Uu)H|Ekqm2H9DBGxP1mcaLZEYXQq
z{pR%fv~9C^HLKwjUBlT!`nsyi9|ac3tzKWzxopH>LG;E&cpm<bolI5YigDA{2GY+c
zlb%bx^y)C%HVjy24yk74uG3wv%sBOJfxbJogPMGrHNo>OG#v<Dd|k&xD(bC4+x7IE
zSu%JkP`9yHn;wIQpJa(yUe343dg(W|RBK;IkGJQ)kR~bd2PaPHVO2lh1Ma(^+F$Z#
zFFtP`>C&TgalZX8^zv+H_2}la=6O@wbGT=8^@=~({>k3;@l$8KMMBbkiF}I98@ku~
zfL4o*U)kp`s#!g5mgmRiz%?J#OD#1hs^lHL=Snl2U-R$tzod{f=lyQ^rW#Zj97ZrY
ziZ$tZIU6^znz-Tvwk-AdXJCWsWE`8P{r>Wx6AhNmUVnS%fbU(Mr4E9V^yh!e#Gjju
zKc=5ZueaJ1@HMTEo7Ru3<e6EB5}&!OrUwdapxY%>s`cdc51iRye&urGh3$ua_}8n?
zH}AQk!)NvU*UTgHi<RnybY|b|;?aw*HF~cc`kMO5>(BdB7gXN(<d3UE;f)49=)HdT
zdoCQkw+Dc*^i1Uxc|~3){H4n0%=wMY@-+agC|cMsN57}{guigA-D@FI+jiBccv-=V
zJp^~Wb8_P6@`3-A8+TR-Nb2q*<5*`n=<Pu|eM6mR@B0x<8_N2$_iP(SmiRl&BJb4!
z7eDLsuH{M&3(z0@W8V&O%bATs-N!1u^oYK(_GXvrj5iu@YVLd8*M|t@>V6=_@tr>)
zHS*8sLxalr_2HEE$9v|Gd5n3`H`JAG?Sj8UA9cE+9cwPaJqP)aYjWTF#+P+)S><t5
zjm?TzjR)ax|6fvef&!wehqGmD!@C9xJC5y$36t)A-LIbQ#=V4trw01b?oIt#^D;*`
zvH7EjiE-J9-CS)Dmk?fV=<iSOzwg?yv+57DKC)UKf8(0|ke>KDhplbA+1&8hp3|4h
zFQ$KJt|isiwLVOVqw<SK|4?i1rEB~yb*3Ns$y)Pe^G4Tv09F4Vt})<u9cwR}!?opm
zl<}%BU(@>K=Iq9p8yqwDr`+VtUr~d6NBK-FL6YMux^u<blAG$Y7wnnAdzU(Hd!?-7
zgW<qLKlBS$SJ!SR#jb>|Et~1pyQ`r)P5;g!M}U<!-TCVrzED1E+LxRCCpXQ5U~B1o
z>`w1`dFFAwdib3F;Lxug+xS3Ay~UR|{?mr8+S5+;^$V33IacH4=9{{i==+ZzYd&Dk
zm=6^LI{ZqLQ^eJ=^yr|;w+%jhsyu(456LC>JAXJcV;z>VVU`81jeRB;pOms|OqHKA
zWV;`kJcurtXtLCaU!VCusM)|qu4EQiDOa7C-)E+c!w_Vfj5YfJU{bB71{+|!Y9MDG
zqzMTMdz#mq%)&H8{y=*F%xb0eSoiA)_3{TcUTBiml?JbWs`BDSceQ+f`iD(?lV3f0
zKhRS52~8!>V`QYwKi+*)GMPRwJiJ;C9@mb5l8e3jQ{&v<_<^QnO&({~xQCLIh9b=K
z0BT^sgK}nK&Kj%Q9XGDV?!m|mqK`y(1W>n1x&p(PuGyWzF{+?XJ77vgAe=ROTq5UE
z>oog^UUlMf6Mgy;C3X(@U-;?f>S6UO*PE9Q`}e1G$oD?9amXDvj&FW-*e~B|>g1*7
z|E3*vru#wS)_ouH-l7uN0nIx<`%LtQ^h?IhmU~~==HK5q*36*sOOVH<kMtYZ*aD*j
zT?^22lhF!{HJPXO*`I}RSXVWN-8CH!(B1o}hex?yGX`*HtRr#lF~GF6e?Cu09i&nn
z*&oCZ1L2xYJ-?4dag5VdrMMp4w+AzE**`NwJ^KE&6k*(PAMO5l%5ij>0{<_j?up8E
zCY4JqSfzi@S&h<ERhzjSFv${YK?MjK^N!HSvUM<|c$pjT=Z~-c_B*rMYB@tw)@nD*
zpm~BK{SKQGxkY(R4F>qCd3`tpe>~tLt{$X&omdi!%?Z2HYl1v-s0MvxfaJ%*-!l}4
zA(FRh6GwJM%UK($<DOQBE2~WcIddF{N5S;W*{(!|(-)mH0zOBZGjS+y%u;u9#aNRo
zjPmn8@($wM84Rap4w~s+V<@!26aBNAl=1Sk<53i~NzVu^pEq5&-JB>0Ie1Y2I{kI>
zj#~|{X>NZ^zt&|A(?N=PX#KibsGSGMdcd@dOYIJb!_ORl$m1O=J5F#RBznMLU<fIM
zYF^;REU(ag=9N2iig%4^<8@PY2c}u~O0MnhwpZ2KhShC5o(`OTn!RjTYykSFwpTr1
zU~J>u>2Dlzu5MreBz4Ht%d^G-{i-UT^5ec~`1)Mp)4lnjw)PTEm0H*wtoQAvgq>yH
z#qYTHmKAk{@2t<Sf16hIQ;Hr}ZFNMIv>9_J9L12jYhB#v^r~;|?WI}6P#;NQTKamz
zVVLcg(`{Ejby{0pY8*CPT;#pJuEg_hW`lZKSG#}##Ok&kf(V0rjc2z~6*V|m_*{Y^
zzg(W-%Isl<8*6>%uf6k=rnZ5R+O^Y!`0nKc+N6osh9se?Ipf0(G};vw9ebNe*Uppf
zdH#-)d7?3$^q9JeW@NrMT=%^hK$}*qPb#Jk0l<~Hujl-!+bW66#*OI98Fx<Q*$qXj
z7(4-P)PmZnVkS#kV#a3NNfn!DofIQ}-Tubzd*>Se_Rx3K-s7Kce4OvQANODR?&ljH
zZJoLBiTL@($<~>l`8)Av$H%YFzBwQL=t=eSzxr4AO!Dmz-_Wm5aLXhLR=&T-Kihb7
zLE3oJ*Poaw8qv2Kng4TZWJh{t{v+`UJ^HE7ePM;5wu8^}?T5O*&jVME@6hu7cXO1z
z^x)xq)TIO8eLa11A^DEVcQcOD4>OMcQX@OMzaOs_!}*8F^r#Jf|M;&3a2BsN3?WAQ
zTV7(Vk2yFamcrpx800vysxI-yKtk?O2RN?ouyQho&#65mj5>NrQ;}s=e&PE^t@G)~
zz2JxP?Q8z)-vV0rV=tP!)!v;=gpD+|mD2qRo{-WwN~W*K-NZp?X`Pzo2CSgROIB5*
zCoONm-POYuS8FXNJD<KwpX;^US--QUyA21-uF>1x4Z**r{KnjxcNKrjYaj5(E(|ZO
z%vz1EJ@2#<r~R-wl)BwesXMT<gY%U^wG@P{Tt&HAQT_0)H-6_wf(9G7AP0U>F=Yxh
zS8!8$lyaq)R-E7q*kdsvwjw+dg7EyY*_0kVn?Ad4>)fiw{v*m-X?SxDN?N(9A#M_c
z&vRoP!uQY(jiB_^UVloE1TQOjOI9Q9$59?kyz$EWaqh<4T`8cUXW^1(=kb!t<|M$^
zMv{Z+QMT6~JD3KJ*K%J`f%r~F&^z5J8?(hTQA1M{N$a}Hd8eK?KI68VrY3GrqrDo=
zTJ^Zm4NHDINm=tac(Rq_HLh@cV6+o>EyBl)Z=G&g+Z%DMax}#|(prtD$aZiTXoh#I
zw4ZwkTcTqGmU@b63tWQdsO~vg_VyBa)bf{tt=<ri*|M?((9j+u_FsGcUQrT}zw&Tk
zcT4a=479P|^MiMl;F8P^JUfp3rD*Esega?wR$v!YRfx*Z=23pSj+|hZVac0zll(*A
z7A<!Hu7n`?dbTwO^pxg8EsDZ<Op``=(ZG2>IL|0c^d^tg(q3`Qag&9OW2-s{{YkS^
z+5Ir`qUW-9iG-;R_?Q|$r2sP9PP;tia|}XlYi_m5ejJ82PJGw3j&~e@8n)8|DUsL~
z#MRPwmCrLswYac^fme?A*nzEh68K4|j%kmYWB$}RfDAYG)Wdsc)$SAwi?QPsFNfLB
z#Z!P9o;8)Nhx>y&JIh}5zAsu$P0tk=(^be>jW1M`6+m|{Xb?h>kKsbHRfe<O1C=Nn
z`UeK<WiF04FdclL8oD7_h)CsKHb}s@QDKNPSPR{~mDmH3)BenIhzE`jq?QS84wsiE
z?VuHYCbWW5JC8~q`B$aDkzT;b;<sCZbJT@N_g2tzh2|Iaq<r{QU5zu_T5Nzt;Ais!
zYVJ171Un)zOFO(&MfU;Y+PvLi1*}Ex^!ju_*u~!MT2EB63l*Nm<9w+w8#J3PXgz<l
z@(uwhe69?N(-e(cJgAOqj*KHj+;@+%CbAG?vcgSh#MtS3FX@vxd~4W7fDKt!*8aez
zhk0oVq&o(OE<LoZ!p#=Gx(;AQmY-!l3CAIMMC7rmWZZmdo(BddBZIy6RkZX=Mk#}p
zYl0F#1$GQrYFnK<=yxe7(cGs$_H9&;t2qgv14|En9e4BKQiBCJ9ezv;w3A@t&ETg)
z?Sz&RPu>+E6^*zGxs!TIV0h_*R(6z5+g9JR+6YN(ATR5*O{Wu=OpnDi**14h0!{^Q
zT)$#@aF|UWS-^vaeg^)or|A&c(r}M6KM5lQtFN-$1poo7fJf|12086oL!Pc+opjVj
zI@D3{ZBY=FtgErdSR+W7xlv{V5kY}D-+X?;VLc+3j<_wS1@7kOIpC79*8K$GWRWU(
z)dZ&uqzm9A>{$?B_DF059C>q0TQ>|%Ojbi|S3ymK9?)pnI9%C%dz!NyZ{pa^EfohQ
zaw&5Wy0K*~d0w9dbZgHZ;BHxUP{lQvh0;tKDCRVK)`yWvJzNHxG+&Iv?Nh^QOa~RX
zY!kXCX4+27akC?}0^_i)Ad{bKl{uvHs@BKMETA=ee8X6`qvudy1fmb9G|D8#a4>Yo
zph1N0{(+$8aBu3R<7P|R0^>xIWlB4#O54ySbNaB3ppx5$86tXB6Y)U-AlWWoZ`A;C
zb`35d+pK_rww05SU)Kd0h2H)gqHQVoIj<hyIoV(qEwGm?QX%B;$3cFl6$SQpefDiE
zu6<;Icfq9FP6|M1b%{FQr-V$0+I%ei<KDbjIT);<Issu0&-efgZWeE4{t)i#FinBZ
z)lKBIHOM1ll()!Q306XQ1NP5Ko#&Rn9dac!?v1&KlG+x*vGg3fL7#LJfTciH2&6}J
z!Tgp+k<?@Kt2AciOsqA_55*FkQ`GNGSWmrF);g{DQC8xI%<jjKxN7o}Z+-sQ+x_ej
zC2~lw0mm8Cz3R>G?XhTvS;g(os@&^rIpQY6cFK<5tj@;=spWO-juP1@_^J*O>w!zZ
z1H@+PqH&O{Dyumr$agQ)wnVHglqyWgqSzWN)154jOR#7^uKfG|o!td}q@ZEX%7`Mm
z%3c>yd`z=j1+N6H-r8r9TdqpxsF?=?=B#s=43RnQ9+zk5bNm953;ece=iLF~1*~RD
z{^C<$%ydfD92PtvY+lOplF5{EA%dU1jl#BiM~ZH$4Abs~wEKm$db!cj_fj<A7tKbm
zJ+WrI?o&sr8)@rVwi(_%-(6ixcbNP9;|pdg{qhcKGqk^lVlQM>Q7c>!ydT2nvi)A?
zsS8vm$lEu&%SV?8G|8`b!mSr;su6z=nc`}&eMv2<6nrpQn!Yl4<ZN|i*TrbhWd2tM
ztxl=E9v>W{=O>qm6!r&CtCjFd6h)mpU&%WqjCyZs`<oB_7TKrmU0;}O1JN_vop9L8
z_YO~7;TRvgJ#qeeo5K4lJUPFZE-LE#Ovj3%otO0D8XxG^w${Yw7-1`Za+tRU^Eokl
z2Tb~e?<Iiw?d8<u(_ig|XPz|dI*bkIC~T~%kC=;2w>Cv3&!iiE$@e}?bjvSZd2PP4
z>#1qb(b`Ab?=d=_Jh`}Iu;lms&kkC7FE>lRnT$<%$7DQM?&O_8YiWOVMcrEamx01<
zYN;Cj>uLoL2T$mm?}EbN5dGIc!4WjbdqQw1dr`&prlyyH-vIV*gNQL$U@sRC5Lb#2
z{Q_;g{RZ538*`j~E)H*)ReYO8z`or8fK%VyGZ|*dAf61>H{UR?suKke$lG|>3#Z@V
zA92t4l+dkQH_PnIeuw$p?O*rf&R_#TrTT(7cU&!A+uXB{(_8KX<?8jGFw@Wb%jN|G
z#sW^5R-4z&rH$&(_&;kVZ&qG04+A7Nqb|@K@uiP-2hEwwWuOt)zjy-~S3cXG*mI1~
zFXy!S3+6}DXZ?Jz@u**5dCm*N^}YH`%5%t!bPw)a9wrfi_xmG1kIt#666c+#%eBP3
z>zLOWMBX8H=IQ9-vKfoNYRpPh<;qX|8yma<n2-9ivnByj>(pK`A&1`hXN+|#9j5fU
z>r|iZ4Rp3_ic1+Pg>R^yb`#Vy0Tvw05U*vE+(D%NYO@+XI|M>3clOZi#rA5G@Fzj!
z08%bD&-lO^V0UR%nLXiSDX@|ifi!yLo~>Y%p`3wm?h4|;U4F;hiRf5n{a!L4O=auF
z#XGH(fYoUdc;eME2+!r_X_W(*QcK$8j}rX3YQ}hLR$m7=0W2A&^m7_Ct<Ch@J!{re
z{RHH8&X~+z>~88~CP_h5_Gsw0+GNN>I?5HRhhH@`(^3FL9>~bN3w(BlSU2W#!9Dny
z^5*J~oX)|7-QBQayn?G$rB>?T>4PifJS*js5m6D~IfE#e7(|oLm6dz{Pi*O@&-i6G
z)$;?06q?J&l-aD&cc5fg>a<Q?Rr^wK!?rj@&KU>*NVYKOrWk`Y@-tZYr@@eB@<2+N
zl%Gi*rf@TM^5g-Ig9DV4uO`UNqyFGpve!@eG1)KFh05GnT>{n-h-^Ri<p=HlWFQD?
z2e5^n_RCMGTfaC2aRkC#Z33on045Vm!oXk#E@-1lsp8-;;kDX62HUJEH(4xa+g>uH
zRs#FPgNNo%flA`^^sh-Kchx=%Kl{~7JeLkGfIP7R49ijjCiXEj`r3aqg~ni95&U~?
zx>hn6VoY|wocH%-gQ#kor#q#7)W65{BmT0_@3?;yeLIy#KvA3Qz`d#(gN^hITd362
z6(n>U%}?uwaHVi>e}*|#{bL^U3Z6$@FOWEYo)lRsoikQ*W*98@IxrOT-h31_^Prh$
z-ifO>C$`WJDs0(jn3w8=J6S@jxEX*PTTT$s?6)RMNbZ$#map6c6dD2L-Bq=3J@UiU
zX(@w+R@|goc896X*U2sc8f3#}$oAWyX|ceTiUo!6tz0p&qYxElwY)&j!K_}@mkptS
zRTU%Rp3Iy~ph-Ah5#{O#eW95}q;$W0S_|x*_IFm7Wvna-D@OxALC(>DzU>UmO4$Q1
z$H)O+7POILfZZ4W!#1{0ID1FibammBKmC2+lGW$^^X6SC!Qb&Vede0Q=`T*#1+w+>
zmpD!&NpyX=2J{Kq*`t>jOEY_fa!z%PUo!gV=Kz>j8`EzC5N`M2!G6=4*;ZXXp9jCI
zY=FB=#lQjV4q8m;#A+D;w>*P9>Hru%!6XyWd+V=%5hI4+ma-d^Q}vm0%Vj4&K|FXf
zrUoFN)Lk~>iG>aZl}s+kT!9i*YIWDd3JMxH<5)--$d#$8oqJk^!9IY&n@t4kNj<qh
z4a$D#XY0OI{kw5}d7qD{DW6L~*z+j9s$;@;_G`pi{FTp@#!ammi}GSGOBXPn+o?5s
z&}pQ#^qCD-tjlf|A5Z!DRljYVasQ^jdH@9nHprD$dr#M%*`vV&**U$+5qhy!v9S&K
z;W-mH(ir>oA>H>nwOSIhD)U%Cy$~!CtS^q#mHe}Kv2nDfgFJR8Z}7(zP}(2+?LQ0a
z`}2qC{+oc|_Z5KQ;oE@WYysE(bIwV;-IcQs-p1*E=38Lj@e$Z}9Gp(TKJSNagMI(*
zzaQ-T&2J)x-vaxdcnjF~`xh{||64B{g}_k(<_RW>E75#>(r&ssl~7FH-ue>1)w=aN
zZ(<AosTX`&I0}F24~4h;r$7D1C!hYnon{W$nr8;#vwmv+vcIH#EO6a^io^9l*?Txy
zfc#f|J$A)+O#tH47mm?7a05l6bv0IYSE&MSQ@|Qjkq7~Fh;foN*Ol0>$dBq%aoYxV
zSe%+X9}|GKf-6RRL>NVR3kPLtzt!{NyWVIYg9cU=AQUkw*rEUqAmxg3F~q!M$16(%
zXW$SM72vSgaG<C;MDSgPM+(LcHmUFwym4m^z!G#W-|9t?U@WZ(LE`pX_z6WG(xe?R
zfLw*q8^7_-Eub3#lV%%T(lBB>a~N^=fKQ~FmCHor__q4If7R5<MWU$eHjsWD5HjHt
znSjAhY#ZPS0dSxhKqz(}I8tKe@CP(M26?^|>&(Tx4r~)yQ5;vJlHU(wi{C!|FSg-k
zZW(jfLfx1n9?$ncz|P&H6~T0p;s>nfx1CpUj}z^wu6dtd?+QBM>wW`|AODb{Wjq+v
zhZr=j7tj#382P6nueG1>5H{198z>#nS1XPQeWYC?1+&uo-}^SJ)sS<eGRMO+gse*Z
z@;cEPIXDeWiNi>Uh7q2|kA>=x$cE)O3m_6`GYdnYq=0}p<c!-g>O9zryF0cm71-I%
zC|9M3!=TV+S&19JlD^$)S9s#KF>{i0T5O*katJ#1C7JBZUdo7M(82lCT7bRUCY<s+
zO(FwvKz)^M@p9j^h1d=DBm64ye-!JaM`5EUc`qbjbkvG}Jl+vUt&++Vj|Z%+u7p$j
zr@Z|Eze?|+QdWA;U(IYHq8jXT;J52~>U0@zuv~$M&cVx$&P;<KtzOqYCn)9-6WWOv
zn6NP*fU95e&;S{cd*Tc4#b#+R<knWg0M)K2)D8Dw++dwR@+{2h;Z7D?o+;eKP(>wB
znNOT}Clm)lt2?lnuH*3|6Y!XQm*0D!iuBZ|VjTxCwy->}j6Eop)=8EFAUUK1ipFK;
zUbxW?D72E7BDoOOE79$bOui$iaWflddTbk?13xm$SwRJbCmU?Favr6utbz-yO>&&!
z;id-;3zg@w(nSCT%Z;cX${M4Iwms&;&iodtNw-=Wiy74&K`FoWKmE<j5jGL2RCiQe
z;?DV%Cg3R;tnO+STToLrl!u7~!}1j!W(AAr1Bte>lZN|PK@GPP0S9IgEK;;t?03+o
z(yN<qKOX2ZXq!%wIY!eCA)TwQ`YCa;+l1~q+Y;3Hlm`TjSRHi}lhDZYgnD;-d2JS5
zY1+y_Savpes~eYwBO7QS15vNLlLBimxOtTGcedxUoy&f9M--H-U;Y>rBStgD!8&Cm
zt(TYX>LEtgYsw)<B(-+PXFG<e47={OX;FE3M!I%8Rt<qG(8Ct$nNBeyPMU48ICx4~
z{n@%3Tgl#-K|+67GdxrV52`?PZFPO$t$Y3%%U2zCsVQd@V>Nx#gxzJZE_eOQT3ang
zcLx{x8hba}W(e(Rvz5d$bKnRzKnsXTXGl;;llL1ZTsAS!8-wWg&ZV%!fp{?o33!iL
z3GU2t8=r`Wcfu9q3}j*{yZ)`ewHusGxJAz?rrKzv1v6R!G6kz-2cDoVm%r>adCp2U
zHUO4v^5()wF6FVP#FF=qwjMD7+XZd#zb#<$TbI10z<nl;*W_yCC&R{)+z*oo4*$&A
zEwf3xR?~Dm-AlA4Qi8~fy1O?8%*9rAy94F5wl45f;2d$+VWR$gzv3TB2YQy}lCP&$
zplg~CrsMEUwiW-HD6m>h4XW^cFt2Tp#yjJ4CMWWsmsjI9OZQF$*C4ODQ8kK7w|?)v
z0CKL3nXe21ZKZtCL!<%IY1MBkx9ZSwwq;~p%Q~|3I>VL^8Hi8xB3zF2WJ0dSb7~68
zEp<>yNChivv5KR-gxYxHOAB0YsUUO^Pf8)7Df~a*v6EnJcw7jC#K_76$gI0t2x>0^
z1aksBYj#WVH(oFZy2%BT<UPnEgW&0wq`!WU+Yxgi?I0#x#`B3+wr2W#nkhP*?HZ<L
zRzeCW)*2h^_Jt`w8Rlu`DAjersq|)JP?_s`fZU+7wYU;*_(|ZdqrEdGW8IscKs~W=
zf~{=2OgG{!=q&gs`irq}hE+}7$V7lE*(ESME4afjYj*wh$`1(qmkOj`1@DHj0MD@-
z;5?=f-ITd0dwQGpCZQi7=fh$9Nf1C}kq!wS6(qI?T56fLPC<ZMKuW|S7&1XQA<*=(
zJSxPDpEKur&-f+9WFSAGw-w2B5?b~Xf2A~A-I#5!R)|u%kS<pAVp@Go{}LzO_O2hf
zY1BJ<q~`MJTI&(L*!V5L@9QT9vnOt<=hK_r<@xSqJ)BmxPo*Coraxr<KGn=uXBFXe
zU!6Dleb;xSt$(3bE7O;BXLWwPs`vbSV>;x-V34$nwM&)ue69BLjm7jn#@@Pg^vIRo
zs(;+89=PtKsk)y%8ZE~0LNC^PSzy%xb)*K91J$Eg!_(nsma3CGSG;IHe%Ph3nlHE5
zKHL6=_iy_CaeuLLWKbcPFI}#*=D*r4Um2e7z2LvV=WNN2U-2(*?>=d`hz-@&`%<+T
zE?2zP=ltz4$mQzx^uvS3=Gt&^`(ir1tT&0uU-X}tUGE%VIE$4X>H78ci?uyJU#UJn
zT%M<HLjL8Y&5+F2GgQQDTzpNLql2T6>)AAZL@hSDd!F@I{Cv7SGnn@ePQ|MAqw2E*
zZ+CjiEVU<BCj3qm4wk@I0qn(AdfK0CmzE|cqBs8i;l3iwp$PR;613MIyyd+B-u86)
zw5AEbGc~<TsKW-RTj4;x6#*Rm{8k)L5Iw(o^Y%?-*%C=uyxo4pA8&lh#ETxcu*3f>
zw$Z~m(BDT}stE7vta#k{jkk;+aIKaVKUCd&-uTq#ERvLKC)G5LzTe05ziV*ceaFtk
z-NCgJkNHpQXS@r3r@QS}O>*A`P}o-iHAs~`sX;%^wwJqAiNKiv!ud`kv4Pd^15!Es
zboUu={`Fy+J$qrfIYUSrzzESLoAFQjgD2NdRC+z2lq+qyp?$~Z<?@;8IyhYyK<9G#
z*X~Kc^qw`R@P?P}Gs(fv0MP85@A=vCzVg$l`VBK!sUC_hKmD%9s^Q@2>OZ<*zegV|
zb=<}GUTh4a_@aIAjT=8jO%MW|fIQ|gc?KBiElxu(PtiGouJrl?2JEYQoiYKSFI`}#
z^Mqe2Q>{G<gz}OxdtSjg1@#(E6QTwV0i*_a)ATPc4+RJFH@i&$z-tzfP=s9&AN7+y
zfqqo6?_B20JhCavPk?udWH`9fo!lP-zkoyZ4WN)2fIgYYr<s(eSKbS#gZXptGv{&r
z{eJXM%OsW7LRBNk=VkMliFNr+V}>XG2HDT<IdX;}&}ntVIE&@`1eLiYn8$)3k?G(X
zx%)#PvDz^z!5sE-;snp4SS0nj30!klU*_9AR1uST+rT_<kG~4i+6_T}+RG3bOlhMy
zE#BeWc+w?^wyIShW*V@-m!nJ~Atwi65I?;WSgl_URseuj_EonMe`w$O$In}v4xM*Y
zl6YM}DUORBq*lw7kjIWG`v6_fm~B8Y30%~6H07HgQm0Y##E1@NPR!f*b70xEef~7q
znLtw2HuDDpUFk9G=KK@@<pGJFTW!osWE;miQR0>}%u^b?VW=))e)O|Z2b6~pFVLzE
zj~-x9;5C7&Oh!?NhZK~0mH5-|{q~@SMVSB{HYw-_D*BqDyF>841qn*jo7;e|0GYZe
zhm|gtPq#O_4;tO6f$GxbX<ep(mP27=%0CY`w|S{`R=qhKCTvX%nzu}EecE}#Y_2xF
z1px|=@gq^4gjDJdah%?1ep>AH!TjRx*W>u&ggbvl!bI6eghzWoes^>Rli<k!fP`eN
z>=aBe2V`saqmO(N1FPov5PF_a2~*ou9;7E8GHn`oJ(W*mC%b8=A9x8uflcjc!u0X;
zewin0I2BXYaLBOZ`Eb!0f7&3F(j>TquhXe9u3>dco)_zYOcR1WiMs<F-r=`F{;nlw
zbI-M)?r8-tH_}1A-+DSHICAA6C?)o3f4{IpZhil!tt3_0A^pR^i8G0(hbN#Nx!Hh{
zEDTvH(@u-(ALWaeHn>tia(1&|;m6HjBcVoPIbin@s2038SZ>Se>)$g>AAtBxmc%B&
z8#(v&$3X=f=wzCu&?<$lQbR~^dk`H&uI!F4ULsJEaw_F`K90)+qRs^mtA<!0!Aj)y
zqw0zQvbKKq9|5Ma&1r-2&H2-jjePQZN$|3)x*0Th2e7m|;bI(~@sYq)GNLQfiAx}4
zK2fuWf&^;y*pQ7w?wpmNJGeig?7jgAtEm8hbHb^rJ?stKrxEO-TP2!zcVzO(oKQBa
z5^IpaX9z6J<6w=nF*{o`LCIv#{rh(c#38|bmZ`*bf?e$iz2+mo^fi~LCa3Ps;nfoy
znyFMJZk}2bHGD{G#^s!EfJ9VC7!o>%3z9B}5+*d^_?fY1ux_$7t^k!J4XRX$Gn0P?
z7?2baZpH#47$>*B^RL}W$REfa-i>TsjgUP?=WC+=98A;T<#Z2^h*5HknOf!OIFn8{
ziYvXgA;M3t^bA{E*SWM%g=^T!qyu21K~7{Z@qr&L)Mp6NM|jo{CkmRb5waPrqxfo(
zY*xL;N3j+0f8`?n4@3b9f*ZzQv@sZ@sJE-(C;rK{@mIcAV&)zzBL5!Fi$K8t?ufYp
ziTfW7yZir6Bew$p---#|KX^xu&HHD+>SBn)bN^kh%KLxno&T*1>*8$unXe3kmlqO)
z*LUuAh6w>=c%FE2(;-n&dsE*NWCARre#O|F?VB3O(~<LGx)T1u($sznUmn90OihJO
z6%0Jja8+7%U{6b|NRN+gPg&li9UH>4Ov242<z1zvzMTK+Tl=jb3Zqht+cS3KQ{RRw
z95^5z;$Q_^G=1ailLF1-F%aVAR&bA4d%n&P6juezi-Wt(Rx7RZd)p?ma0G)e5<iGc
zBQ9xx$=F&9V-i%Ax1aa~5=12gW51Q(YJAq}ZUO7T^6v%nB(^qG7vMl@^lQK<TxG*4
zYv3k^QsOTAFa)*abuv@&6+#ULVuXG;X1H)YkR#mk34HXR95+lU-wla4ZU8C=>^xe5
zDg|WcT91C^+v%K>6t^m(gUPMs7f1ktm4I>qJLtN5xOj|Ak;Jda9Wq}948jKmj0OHj
z>_vIXAM3^4C_33_F|Cj_Vt5k6755==X21H;cUTHkk*Fe9(G)(VHEx*Ykt0iV4M_hM
znNWdLCFxCa4WWF7A19O~21x>TBrDn9O@L+|@*g;pZxMmsK9R~%&0@RCo@7%soC->}
z{_WoqI9K74iX)eWOb?lD3Q&t6#sWi16_F%+{RhZUV{(DKeF`Yh-&PU)%~F6G63PY`
zC;;JH%k$bhcZT+NyK(p7mN&U}fD@i$ByqMD;Wq;_#ukqc>|62gSjYKZcQft-88mFr
zDFwdNh6e@BO3o30lztKW1V0?a3=f`<K1s1PwX3$;0NU$UnAvexV<fdhNlqhMvlj>8
zoh^F`&IJ+xdP6;g%Zli@YN?39VHnWp*6TkP;6fAL$e?(>ouDiPG=R<U%Au=FC+HY#
zR3~UmYVJ!Y5u=qqz^@R#NKXV}g<rq{<zW#TB@9dZBVw~`Kqv^rra<FwGfkYj$Yf@?
z`U1WH0yAZS4XhoU(g5eMQ|9`tt(1K%L6~`BaX0X}tTZ@1Jf-&Y1Fwv>iwTig7m#=)
zlp^cJ19yV53HR`ch^w|+@5xG~-vW{YAb#rw1d)KD$aNwPGQPz72Q-8|W3CIh-0&VK
zmv<B*>FnVfKm1AV0Po-s_OSu1s#*@n&Qj7Mm{BEO>m5sb!9^_vtVEr+VCz!KicE4i
zjTRj%NXcOZFO(?dVzF>C8D!5|Ud+txodRQIi-M<lg5nj}S`_*5*}rvX;L6AVNgNX(
z5J3EuLxUjijMEwOP0eYMNUQR+1Ka_uMNlh%9S^6fte_}>@7z!48JB16Hg^EN#&9PL
zO-vN)k^W@RfU#F@{pP=6J_7(74QTX?sSVAvJDtWTc|$ft1)&ogAQ!)TFST$$NXS`q
zAlDLN2owLpEC|ms0MaTJAIQ+ylq`Z!cyk{Tk@1y+#K^?OQC6~41aas9TvSL8-+KQm
z1fQ`|9MuW$p~p;%8b>rRm)fGXkDF;{2bQ?ordP&*RtkeA*4%t`p#7XBW0adI9xKdD
zU@C)S1Hndx#0m_S=Vbuz^aD=L!wAqaib_^|>z=;{mniO%g_H-zHxm*c$6nJF|8vxA
zL7V~@al1mMLT0)~Q_PqAM3%LzX&%5+y;x`V-Z)n5@5H4^v<+N|6kt|ki@hae!TXb~
za<i~2r{V~@%dlvV2LQKPes$Gni!0YlRcFp*cy6-(Tq|vb4o_xnN`AV$7?D4z><Ib@
zBr8oye;8eq*)p^HZzcasKB>F2nW=3{*iEpqEpr+QgKH*wJ%E?yG?DU>q#4kyy(wT}
zs%FhBqrCkX;U4KQ^pTecXF^};6vFwAtbkwPr;pU=9V5|B3S^{6JRPPT-E>W^TV^9o
z+ZR$ycuJq(=C)l!VLenTJKINTo1k3cNWs=DRJ&+6p2AwFyUc;#$`LX^kWjBQ25=S!
zJM&g4f?pYJ$*R2gW0)Ks8f47vSLmtVLxj=YF;M7bmDG)ss6f?F9|$z&&!{cH*)4u&
zGXdf-dBr0GnNHbo;hEK_;Y*A*vlc|lAzYJ(c8tuChralo+d4Mrl;@@GNA!oU_|H>i
zwEfHe<+YUhpzUkM0Jbe|Z-34_?_Zd0vt>7=4sVCTtyheGO;a>ax1LXb$^2saOFq@4
zR`u-STGDx5!rrvGPSn}13$q`-saAD*Vz3rGHQ#Py>~uMB0Nq%Q?fR7H3loMRdzlz3
z;{)uL*003vyWCd(a4V8M5VqB(rsAo{i>I<Xtf^=+j3Nx;?Qi_-BJzP{ab$`a2`An+
zyR@jsZ)z97O?9_2X-T4{%U9AtW&O)v?ksPwUg&i%nAV1A*M8A&#+NFc`F+Fo>e0>t
zqw|g)G+OO_X}fYteK?+Y_ovd<Q@W$}5nB}=m0(w>nMs&C>Fa1#)oz%76o=twyd5#y
zVEAK8am$XXIpbIi`Htq^Pk*bC%GC-MQ50oi>EplER~9>QB9h(;tR(~$jBqkimTJyh
za%d&PmbipJ0jqh0?!07fqi`n`8Mke5c-fxF3HqWXvNz<5FituwQj1>=5poUlyYw)7
zI9J(6TWCR_a05@=i$C@iMfN?<U3+`AflKU*v%B0pzF59%@WS@hefYWQnd<4Tnb-h{
z*|Y6~r0Q*K^m`H)v{>$Zm4lP0EKX$DVIYIe!Lc3wlkva2`(^WGJm6|$rJGMURKTr1
zcEP=G!)rfA*o@cts@4)&HW8!w00(|1PF^-8YlnBleb=%1)O|+Vz-@$yMR;|S&rSUS
zh{vIx-@ogux+`2ScaM`T`nzGc8Udc!{qTeS)m3byr5IIM1vmS#Jw#0{5;#Q#Z~eUg
zEG!Mmfyq=PUsAoeUnYmt0j_W`|A_kPIDkSqnX3!t^4;_9^x*ER64<nH4uC?Fuc`Mq
z)vyNYS2k?q(cxm19Rs})Cz(SlsNk8cycb9OAV~m`6`#%T0M<H2<j!5l8fbl&g+>Hh
zh(K^a(4x=(m3I>2<@TFAt#<c-6BWvB5S%2Pj{&m)7$jEBqF10F5VaWyQUiLRDYFN}
zb8Y%J2^u9*XRqnFw}yh$5${EcArWt0KCS8MdC~#^3yUp6b_HHG*aS9da6!ono|`&`
zR}LIjwz6Y}u(9IDYRis+n8ait80wAxyn@!S`^|a`*47_R@AJ=))hRUzs%iiU1BXhg
zPW4iXZc7CH0=8MCirhosWUH0TwSZ}=_7MplBX5@;b|e522v0~TK|~ZXatT@#%}VLr
z_d*^Xz8~Q{Wr2f$3&{s4fPij7)2JT4v2mA}t{JfvL^#Ii9kPL?L!^7=#5OgpMRT8!
z?Bb>Fw6g#)=IGE5t3{KZC=15&P$mG|CV}x>B<dcDbH+o*9U~r0WM|dZq(DL)TlLFG
zaACg~+Q~72lYbD$=nrVv7ryN8qsOB?j(+sZGZ-{>@SxFIWdOp*2`DP>7#p}!0@#v-
zsa#BnumpfPjm}r=C*Zb0cN%IjON6U(-q7lX6@UaTYoJ5WPKzTd2+^d-8H|R#MQS|S
zhOjcYh$+iT*&B37RtT|SSqb2UcSs0^1?m2me=VfyH?>Yq00YBdsy_pJVIg$fZX<Tu
z17KfZVJlC@*vLB$XgHv-PQDI=ZmhE$s7K<4B<}_x0sX8846wkScbOBP8h0KsalTej
z^$yrclyn@)swjXMNJD@4A6vKH_&6i55`UiAu%1|(PSU}QCBanFgPBMDA(qkRHh?*j
zCkfKqAk?qUQ4J`qj+6Bg>&$SyYR|-4shF+*v`@hbJ10?B-N96yOE9gj;!!d;iTf)1
zzc5k^2!-SbLhvPe>dk=hVhTyx=cgYcNkxmLq1wX+4r|@-ty>tDU`UuUZaN3BXfySd
z7%u}Widpo5r!d6;r&>kcCPq{xCSf^f^ne44_DS%H5-e~F=nw}4zAob20-z}ix<Hms
zKf4ug8!gZk?8yU~dssjsg32a9m4@qe@FYi4O(p!y>DmH4$=^{D07{2sY1s;r1>3wc
z8vuNXPdr~=<ySEoPpZ1w$yAW$ia}zX(U~nez}k%+*)6+M`|IkXvP)u3EC7#1YXo~^
z3`}xG1jO`_``-TlV~A--{3ml}lj#)?#0;oulro!4zwy3%0_O40d`YerFLA=KzJ%BR
z^h-XCzwvSX_5GAl`!iqSbNz|ef8ism_Kj<9{fEDiNwkfyUBFu#J07HCjJ*mxURWaV
z2Wla8w7zOI3-~I+dQR!_VFl9>afac~>H-;|CMxD97AuWJRzjdIE?+#C<B8<^;y~2L
zem}+_iwpdt{0rafunKru;i&c%z;2(OGS=g5TXpa|ecz!%8Fn>sDb11pB2VNZ1(V`k
zW@sn=3Lr!jlejVf9{ya&&pEa$3lsnVXZ*E}h#r_5bBxVu7QKSnY*LHOO{a04a`^!B
z7*B?@ukP9fp1^}fgJXn3E$M8q4~T(Ct@AO~H!EMiq)Wg)p)E;>j5}lWU%_XMf;cxN
z2unYT&qv>jU;flv!;*i++vvxJcqY`{v=S-XSaHTExf42Lc4f>t^7VsPShnSp>$}`@
zjp#nF`&wgb<-RC+siI0dhr=(WFXvy*YpI^FfBx{bN!5tUH<Hvn_kH1!hZkl_+mA+P
zzFhfgUV0|4G}Ut*ZB7oom%M*!w#Lof_m*e=-lX*xXURoaxZ_j9-HU1CL*+PG=&k<>
zdlPrgtPQ>7-4C6)(27dx@7_qBOsv1?w~~joUtjy|k=pgjQ8(Us?`q}Lgfl<9(6T4K
zaDg~KYlnXKZ1j~ME0MT#a{Aq=^&Nh+=ain=TG<mh_xo$HHE}>!+Dpf+8Q=Y`^2RC*
zQGSo+!h1s6{>F7c`dl}EKAzZeRjXTGW9Cj8ypdc7doM?|Bf|^zwJ5oz%P~Q~hi3h^
zG+1|Ou=^(){9_OH&maH6Z>y*F_tMu#g?Ij(Ubnvg80-lSB&+-O;+EAoVlHrlu3ZO1
z;R6h9+v?gm=#DBFR2UognN<Tz#z6^Fq3Bm8j@oFc^3BTL_<>(5I1>p{v|EoG1jmi~
z&zdS07h!eW!!NXqUXmY29~6NyvY=pURzEH+_yn4Wt1^2(fz#k5|L}hvwNJNX7}l6+
znBoC}Xl<4f7;!9};&+<OWt^-4p3TE~JkJ0SiLxYS=?5h)q|pF1S%57(N0v|UyFU%1
zOSc8lq$TM$m#)#dbB4>c&JA_jl-;t?nnZ!}cise(1G)kk=QI34F4w^_j&00FIe$bZ
zfOUZ2GB}8gFD<{t-mSYo0}5!-FntpUh%py*5j<O9RU@lihFiQe8%6veL9o)R(Z|J)
zGArDT=4SQBa&cC=^+Lihpv|ZO`X!%3CvG+JQyxf|CKOXel<qek%_A8B|HSt%q!-vU
z13<vhyv!9}#R%x|AHA0(*>Aq+G@KGN94>)0o@CLAQjruvnir-)T7mF}_87KEai6qW
zh<p%Cd&FGdXzy=7D^rWHLoE#;ul7)K?}8zn2OPql>xivHULs+hl;!FWPZZldLA?xB
z`j(g<1D-)Qm>Nce<pKo)o+e|l+2TiB+cCy4l*7G|xnaBGKRbau6KZ+vV1PMM9%l_1
zY-KKy_0nMGf|y!bEqVDIOtF<d=3qjhd_yVl1#8h<U`JEM;(*&|oU!r9KKl((!P=Eu
z5B;wNaiD~!M#Qi*VhqHEhtp96JTzk^65}MyYGJ?fFrEP_&Tb*<5uW0AUUfWAnWPrq
zvO5HV&PtOZzp#3(&%eB_=$Hcab`A6yBXBEcpFmM|$}<^UlDWlL0%QS4tdOBw$0PAf
zl@r(V1%9NA-snNRLpZ)XF_ocR5Qb<P#&#S1vaGY8=D9NekefA{xe(a57ScGjxjW!j
z*-?Sqg|k8<GKRYFN->yhwC*N}m9-g>gnWWZ5cpPH02!=X2fvp)G>;Hf8T`NPoePj$
zM|Fnptd_9Guif!_GZtXq87nXnIL0Cs6gxz-Ya4GF3L6N<Jd7-p5FSNjhY(y4@Z8-I
z9%1<*aE!_>thInD6JsP3Dm<!Ol6fkaLINs45<mtj6ptd@#k@iY&i9|bGjs3EojWty
zk-d)hYBkfhAE!^B?mm6a>C-)IOc_scuOw6v{pT<(kI_K^6=H_1PL#`c=xC0N>l9|9
zQkXeb23Km~57crV3<$~*$a{x=^LRyylVD$^l-1|v8$%F!)JcY~Yp~N+4IhaSfYl>@
zVgp*;oyUs|2X^YRCPKZvUprwAm@?(l0M5T7@Ko>HNrTGMWo}9Uiu%4zB@*{FQQ2v*
zN`y#YbpQ-^^$pTffNX7`;t`*YC#g_b{O$L^i8M2U!w6>UW3*C*eVMA6c#H<>!K>U5
zBLVX{g|#n3jo?5=>OiCA-On+wXhunCGA!rv;g`<!$7(@P;qGZ4D-z~#I6uY;HkvUs
z6(?pfy3>=)z=gs)xN?qPPTYAazW}q7pQglow5`0B6EJmRImOBs9s+CY8*o}<qpyyo
zomtDx8KMO@T&&NpFUurVDi)u~0<o?*KY}7~N70`zy|0KrKUt~Dn>_Q^^wu~>p=(pG
z3APpSHR2{$1~J@w{uA}@1o-t$al_!+V!e1wEkKvtylwtZsQz8=@(bm)XVtfJx8@wj
zegfR{DS6h;1%}Q$K3?C!aAMC;mNa?-octiSe*OB@rBz@BPlPtRizRG+t4qb*#dRQ7
zVvmZUz#Q52zA?Iz@@CwcLqVLYa5a%Lp^b5+4!>@UAq+dYhlO9%s~2?(PyFa;;NdF>
zSAI=>zs`$#<hcsd_-1rR8M&iB8O5A}#I#(G9Suz>`TwQ~WgTC<^C}F>vt#+K-+&_9
zCW;ua^7XOzf2zJ#o@Dj03%2dA9pZ-1n+mt$0YN7&?40vXD*tHWj<e9exBlipeQ*8`
zg8JCOZ4(E`_-}G1;kvo2>*82)@0uu`io3_y12{cAZF+UizsGE1vPTr&hd0eLy|Z`Y
zxqQd^3C@UOcbYC?4SS<kUVYZh56rw1iwVC2K+F8a5C0=$5vxJ9_yP`-&6aV1sr%TD
zSmQB+F{oFMVTZxi;K^KrISG^2!UVV5;tW^wuI02J_MT&Kf7<E!^)fJ+K#%}CLotVC
z2AdYV=Im9>(uIk2(#r8!AyPP=jzJ9b#NG)_$T0XrAp*Tu<6h3?UN}Fiy<o#cp_YXm
z)JtTU-(#wC4wd^{g(@Ny)`mm;>Ioag?;N`^!0TlJw^MNq=8~)to_;!4W)PhM@e1o+
zB#@<5SmdBbk$CME>4=(l@K)9+R)0DjL4Pa5s?LyM*?54nkGiPU^Dr?~Fu`Hb^r!EX
zYZUn~^3l&!YxOI@X*9`&S{#|r^e@uGx)Is=OIWmWn6SVG8`0?|D$yMa6O-YZPs36I
zj}_~B%v-D^kX-8tj%m6>t$N1}5C;JxJ&tVH${^9NF-l;zgKT5fZDXwCd5%R>60?#l
zXtc`sj|`AFA7lIx3E*n$=5l60lSRn5U%|WgmFfcczJ|gN7z6N6pMI8kunc*L)lyv8
zhBb^f?k!*lyJKRWC5_!fS}o&~=%*v7Pzt9t!E+;kF3{?YU9iL`2xvNXDn+vB{Mos}
zl!jw4)lLTur(smdP-0}>af;gQ-&r5m=!dn|nVSp@mB9?_hDDv<7*TKAIsnGhfCUeF
zyXLCq>h80oLYAvJbx6TG?d;JSt*z#~V1H1qQKyGVhq3p(vFg>(u{K8yNW2f=QWVVL
z%aogY+N^F4KXiaq-P<nryt;><HjYiJPhxDWT?5?x_`OkC%{yD{-NzPXM_q54L53{t
z*Lrq&0G4|$q;g~Rg-S328f%Z^zMTC0eKmh`P-6oeOBTz(Sgrn~`YPG2*Nz4h{-QcG
zkKv}uF%9@wZgO=V;*-ky2;R9eOP>w8$uc%k6+=_LPgSwhdExi3y4-jr5GsY&6u7X1
z8IKEC04#Dba<*$%wHj!zfSYh&lU2L*tSnb5Y)bG+#B}BaJv_OAneH|0XcEDu#vDUr
z_OFUkInOAz$?;ES1KaEnVAnT~e+*ldlGmT5A7;#UTw?r;vuox=75ZEHin=}iw7rM_
z`}dyH^WvEX36Dz>vZpfQZF<GyBxmXX8Q1M`;DB49%3LM>&LTHU<s^Nw=RdbolH}#}
z`CtcptR|%q4&c?Q0lyelsLa-9H<aZU0s07yJ_1RNkzCbgr0Q9ht9d1ItXl8S73Z-~
zGIc#NOzgV%1ZtpxwE({0?XP>m0$wdn9xLD}upce49w0mc1$Bc=2z^cy5CVEc9;VR9
z19Q`|zy=(5!Kfp_7&4WlhIzZDj%5NOW__cERVjb-T+NJ3;87L#*q#gCMdMMyiX1_!
zY+$3@6gej8<=|E0ciu+e6|@>9i6*nV5+Jo|#(3UBQFgA<8gv)#4rgZg5@=Zk-~M%K
z20cD-x3X4(==2z<fdqCqpRgU7o`r^@Tn#0R5^5y?)Pw-Rh+a^nlbx$YkWjr`VGf5V
zT=Vr@fUiZaCbflp`jG*nk_u26pR{a0QV%w?nwlV`azAJ7NUG7@QH7>ftDydh)UEQY
zcE)w{;n(i+$%z!SL-Y=6xbx5sXo}cM<{D#omOTQj3+znuu%U`fBD-A;7ncC20edE*
zHFBzvhzfXDwJdIg#6PQ>S!8j0D2LCv1`1182w=*&@dM7208dHfMSL9_XPdS%djN*C
z16@Uj8HERWtt9d~<+cUL#XtuL5;slqHX!knh&UP)=K`E6l<G4;We*G|u++K=$pfYI
z1R!Pf!Hmk_lmFMKC723B$meJzHUNuLv8t3J`pZ#M?_P<Ke!~x)L!KEK)D7xv<(D&o
zecLKVBdE@FC+I+f=rjhL;lStxGUqQ@c_;ze`2`Yr<&SErxr3iP#vwv8<QOIB_McX0
z7jq4%YJ*zkGNJ%CE-2Da5k@K@fL7ez8So?C#$P>wf+{Idh|fS_(VD>^dl~UE&tTi(
zTR;MV$XBOX)<pYi&bh3SqK9dx@x;Rjqn*{_$fl1S3o#h~H3kq#0uXT4Zbt$0G5FHC
z3~?MVbm5$u;j8If_NHNlEqof|oa;4#wH9h}E1)mW+n`|iTUQvrkQ#vQi{8ZC*U52J
zT7wF+w9eO_x~H|BagAm+D>u$Mk#HjoXc8Sr`ovL^=2;y^zcQ7D&)p}ANO4sPhU|cM
zN|PfHXChvQhRgVvksZX<l?oa_zgQ%Xg$*!i(Zd)ntzRfsb02;$`mnJ|(MluTY=+c8
zJz{2ntc*>SgB+Ep3mQ)qUJT?0TpNcr11(15&(D>(Wo#R2KNct>AHGfSLRCSsu+#`p
zTL4uP)!{2t>o~E{7C~G-<>fKp>Hxy|a{2Y&(&(lvM{0>tH9%A|73;~;!;8)&=C})t
zVTJFD+C&XL+>T6C?hq0{f{;vOENZAM6yfucf$83wK&gxObIG8ZE9)1y3O|BW1qU7D
zXf&KO7r>Fx@?l_R+$D>(S1S)C`QzPvdfq}&t=aeV<1CFfh}#GpXaX4CLR_F$$eFN8
zTSOpx)L?$Y#kaw$-ZNHDvjl>N(XLNggKJD7{Pr&xEgRTNKvzG2KJ$#i6#itK>DxYm
z7ZHF0+<bJ+{}h+rG1hQsqp6o;@YVdO1^DFD=CL3YIQiulgW~3ZRe}|KUT$5*oF8bs
z$u6MPQX>(@2z%7MXofnZ4Y=~GG(SJTYX7|px^WU*SXFTCgaK3av}(i|b$;RiKfp+G
zF~<(*W|o2qh|W)A_z3V?0efs7+?gO`U>3}+o!pgx5d$T49$5kpWcR42zzfpIE(y{B
zL6-#miORE&lP@jgOXctjf4qR}4K{&VP;ILE4L_O2H$VSlIlM;1)TMRvpaDtyE>4eG
z4m8F_7BxTd=T$YzqCdI{K5SNlvnCdb`|e(quhsFC!^d}FVyb}q%5`V)LviJqn_j4W
z{m<989^jl<VS0>{WxB&#Z1Bp$rQ1qV_p!NuD#vU%godtje__9_D$k*i5nVuq<G!4G
z3NHvsQ}+~J1f)~*GkfzNKu40LfEoS_8QJ;WRpwlNqBIrYkwTW6UWiG!w!h|8KeAy}
zO?UAul>Re^eIdZd!SpMXE^d;Nj!2u)Q&IJGhMZ`w0*A^A69MZ&6%`WQ9?cYG7GE25
z^nz%|T}b2*Aj&}t<`aKFrzAQXBY+`X@VI};!&<PB>+?tePrxx^m>5)4z@vskAHp6t
zn1ZxUYDZBF1W~s!@Cx)(3j{daGR+SVnx@*Q*0=z0)k`onaMWVKgXcu4JX!slhfd_^
zicgEt<;1O&24Q(q8%1Fn4A&>(;<|Bu$KjN;_2UH!26Q+KjCVCvJj1oL#nj|XvVbQ>
zzLGn9>k~*PqcT$)=m&tNhCB_YV)+nBq~0pqK0gdDwG>=(G)^Rge3TJMm}7#WR2u2%
zZ-9L<4H+wp-pJNe?QOc`1hreR;ik}lo`GY6sg`#6w2aHxV@@UV%l5c-39<o++L!@~
zQvZNAt)(`C!UZ_gZs2IS+7zxnnTiQ*9YefxkI$gDMbR!M6Z@`tdkb`-v2sI7Lqn~)
zhiHLO4_gtTs7K#I(69*4`2ysDeKS~Ul>mL^ChjJ}Li;>5NwTyS?aJ&OOlgu>7!FuB
ziosTMn$9|(WGSf9K8#W8FnJ?bs><RSSf2OO^N)vSvi}xvDFGEh<WLioM5?v{jaguX
zSN2Q!xswCig+f6+sDWGw__;)@i-`+3{kN)0uuaq2LEEdAHV6KQ7w&$LVm0*g3Chc3
zgE_{@E#o;gd^$D*bZQJGL_Qstt0Ce>`Cx5LVu^C-dkXIB0fJ()z+lvK3<`d9AIWOJ
zaV<XZ7=hT7&B=X6>U#}~aIU;@{=^i${kG(Rqu0Hz>lNM0=d93BFiAUb^tEH@M-w?r
zJh7M72V$Uln#Gmw=0iiC`;t+ET6t1JcYiY$nFiM-J02Fxni_oad*z}`66}LbX(Tsk
zb?lTOL`z!+B>}2!!$}zLbWUS1?vQ=_iJb*bav<{*0wii8wdT8(pJ`IooZwq}nn$#s
zTPVT|f>M6*&3}zzg6awb6T2mkW+_!fA~73Oj<rkj(L4ZX5D2Y^83|(R@r#U0w&HyF
zP03$XUSEFx4@^D>vYhf&9wrd*L7mJ$;t}QYM(^!8I2bMTCr}EQaOej}8d?QajKUzO
z?J&Lt#U40i!8`Os*Rw9F(nyQ42y<2CWN1ZFUzBEF>gg6liweK;-FS|+uu7Zchb%}p
zc!ICTpxPKnz_+x+zdFXgQ$Jumz|cSb%qt1ah_$hiS?~>{DA;;#{Pq)CFNCTio;OV=
zy1`aOIyH$^sQS<rnV+EQfB<=|7Qob=zktANh_I3Z<6ZY;#kQVuE2vOaqA<{A8EBd(
z@KuX2U=cY)Qw@Yx$xWY(cT^OQkYgbO*~}|6?L}gvK#&P^={bxldbL7^>c-cvvYfGx
z%4p-o0ddsB0PdoV3?QZ(c%o`ZFbZ3ShdyvZqkQMLI!jM0dn`{B3E0?k+7*v))EtX#
z3pR_Oqc)I=Q8Q87Pd?jLIPDdHO_&PXNY$4{7~m2Rw>;_iG#G7h&N2YSm@=Bb_6W(E
z&7nl@w>>}c+WulqYeuS<qMmBT#RGf)HbKyMl7=wv4R~OMSwRS?fsO#t*i4iPzwz3{
zd-6q85|jvnz&KFKmX2)r#!LJRB$M#<#z<y9x|#@A=o4NOAoiS|GGE#uspUpH0>Eit
zDoBB`>{x;D_RBJm6fSyz;XY&rMA0+u3`y0=^3`L#u>X<^W6!=<J}&mw7R2xZhk#K4
z9P5b?Rg<;cRtl_U3`sp;PZ$GwfTAfgO`IO#XCJJ_-`lD%v=s+K;uD_4QC<7fmSt@#
zoVpp49Btu??^L6;(r8cCtCU9Bn=xI>Mw3>b@!||(>zZrvaYLy&_fmGEu&~Q=)hhNn
z5<Tx+xkgjh7#a@Rvp2q$E2GCcVBT|Kl6xmx;}j=^Q_)!Xy9j+t{N_y<Qw?wSv*q#P
z8=p8Df9(jXObfE@kv8b6BuDf{Rq@grXLA|jhnxo4dTksfB`V5L6!wm93T(5dT!!$Q
z{~E6(H4F^382EZXk+U;ycUNHTY$!c!iOr8)n>rSTW|~L`Qv7NDxR61Q#)`!VPn%Nh
zkT1G9V}TGfqp2_iQ3xSG5e!$AnqzE9j4J+w-}{o%7>TC2u<OY#io?U!K<PVZex|oz
zeh^hvfewREFV{1e;zC_$C^k4GNwu^jMH?#%-}1qp^|0~TtQ|D>qvKv&uLLioIU4AJ
zIq*BC<?0|)s|2k&{FW2n(W^1>N+{9*L<Qh?NJ9~>s2vZcFuD_25>@Q`=Z9^-@;di>
zP3!dimfwDs`;NFd_2>H5)u}(9F0ZqnY`QJ-KYwo9Pd458QT^`I@P4wX>s_!Zj_@a)
z<3q@94;;9`D>Y~|+M-dZxuIc_@;v*cDUr=6_k+C6*S3I0ckA(UUihg$t-5MVtZSu3
zA-96t{drN0=8Z6O*a=Tz9--~vzbBGF+*<->1q39sMxs!Z)>zI&0Klo73-adh+Vi2u
zxe6^uA0Mo7E|>Z08D%4o4y!XhkOWed?A>_i7B#BE&zNdUS@J=R6_lt5hV3-F+(v;$
zK`;E+Da~+Nz?G+rU?wwQN4NN7>?T}|5>F}qCdq&$kGnBgx}&kA6}<(Ubso)TOgjou
zA2rJ#EVY4drYIm`PLTOTYT!F?dK^$lk^i34?3~wavnZ#R)@^ORr3YxHQLTk#BOfvC
zkymapzsN?8wr>mtLeLgYO43IX4fH^1Lp6GhmkYm&D{R&im7#n@GuLfSz4O{sR(5!v
zwjm1|g>9pfJakNZ`-EuQ6aMlk-dtN;{MFO|P!n=3hzwfmGj$9J>h)Nm$?$DIioJFO
z9a^r4Ivv=~YA5tawDh(?8*cfF4mimOb&m$4$(+D2r~=ibYkTX%nfD|?w7p4Mj|y9g
zn~_lrb5xRMB7+xx@|SHelCLyMl1%iONNY#V67Rk>ktglN%^h0lAUCoYxJ0ig<=~p*
zvN~J#9%YL(3bog$$T)Yc)+azC5-6)zS-kJ77U=Tf@(LZ@#ln}E2$62gDBij|QF`y&
zAD@LL{E^>zW8eVFTCKGWIUO?|h%#2K@j}!ETCgYgymqwp))7KUp$tO@{Y1(M$d02M
zG1x^ID2+~}u}ZCy$ZW91fE+&m_<HQMEeMXyznGGuI4X_SHLZc}HPLtDi`Q&by)7-I
ztMal{`U!;j^w{&{DhhScP^R&M9cRyKa$DZEwq^nppBiGKYSG@TcXByZe_4FRwQbFa
zze?s61Y}j!1C1m+YIjP4ute6DOf7}OjfDt8c=B`{R$Dj%BPm;hMuP;`RLSiO9M}8A
zno6Lgc<Jz#pJ%Z&he)Kk7;rw^A7C6LYl0KvTaYWcJr`uy_uPh*=pmreQzFqEI7ES^
z9{H8>6}?#$BJ?d;It-8^pizSXsDUlz$e~LF0rDxj`Gl{{vVKH;17e!<8h=qifEjjT
zz=mrRpaS99FIQ?cm!Y~`T$hH-QCH1GqXR2=w1-1sjXSI25aSL7h)OJfBRYJ`yL(pA
z+&;4D*i<NzYD245uxUU)bnR$Qb;S$TjzW<`=yf*FrI~=ScBiDth*%LgcCd30ud@-8
zhd=zV=`2gx@VPMKhh0&7hWA6YoeIl$zjACAm)B@(J&n<6L$ej#3{|eWnv*~ok49|Y
z&%xh4p)t48%0$Qr7mWy+#w7}x%%QoVg!ZX3zIfSd(qJ{T4okxqPa6VEX6@B<Yik51
z{K?I3^rwRrkjA6+8-&2yMAiVYvUB+&b9n!3qe#|wd)r*z4s^eLI15NCEgf7dU7_&H
z&q_uN@)jqB0ekUFI*L!bn1<ZlSP2yC@U!MM_Fa<2ANXX3Q8byg=bIgA?UAe1o*3zD
z->;+KjSqHMmn)-|%g-e<w?K7tWHV!U*E!Abk^|SA{P0q(Z-iG6>zh<j#$`^iR6#%s
zLZ_*5kgTV@Da%|i7!CWG_I*QK=G_ssBinq~yRjFY(#FBsi-?ak<c9XN_V))iH~Mm^
zXaV`MURxbt)nd0oB`%%B!%91C(}=$GjHk8O>}D=KuuL>N<2mgmjh1%LBuT~;(e7EI
zl<>b=CW=(bbze+UVDBsT#x12-N)$wVJ>pT;lk9=4oQNN9+n${vmTH|4d+!KddC35+
zj0SKQGSbYAQ(4NR4K!IYnostO2&c}^Ql2%R046&d0;HKjn}AaTlVNFFYC;q#%!HB2
z(Q%=xOQG;fS9M8IG!|KzaM)j#OP4HySaC4kIJbz5f}5WDdl{)D*$$zT$Z31~mV0~I
z@FUrpO{_mmFi&()J1|Dy)jK*P6ERMG?=nadIf1t8<!v$XR~hLvGaCPanLT2>$!i`O
zjYDV))3Z{d-E6Cgjy=)b^N9>y4&J1FcjzXE0_$>(L^?TpI93)vxW(_z8l8$H^@z^J
z^TF)9VBMpu!!6INb_a@Sp!o;n*jpQslCR@eef~s<6!S=!F`olWdh`q3(Xs=s!-=8h
zyb)yofe?1&T`msW@nq;)uHAmP_!60Hx;?VEVQrF~iCS#qTLvy??dw*^;=^Y>n2}B+
zod<%T%dRJ@6t&1|l=bX=t&T=_ePp&5B#k-QC_!2k$Q+vWOkTORxzeWO121fchN)6r
zfG*8^Hhn+KWJvoBQGu`>{thEvC-5`x>d@$7nGA{<Pu*<5DC=fkEKf)9%ui`hMOL(?
z1GY2LvBH>`T-&;n5yCwK+ZlrDBF+_P4&thiG~YD}ByDk9zLe`(MY6;IlK3W0uJ**=
z+4T0qfW$2Mup`*~mIVt&!v2`rfXd>Ala|p>z@BSA0XrT21g!fJ*H_J7|1ka-ZKpl&
zXSILt7+FUeQCYlYN7f7<3~u=3yQ<8zZjY7|Sbk$CjcmqbyJc7U;s<WaN>*jS<WG`=
zCZNV=#`Dy#Wh5Fb)+1Prwj_BBa7KynLz^>Fqa??<dUFTwqH}r(N3_sk1P8aNm0kHY
zn|t}8vajPrwwUuncbJ==l`R2BC9NZRH}|Ix_G+!cGwL}KcE`*Mzwz9R)bymTof}^N
ziS!cfvArAF)1V3xk<pkh`!lO_drk58Et`+^GiI4(b(6t@J&+7P{k}NxwlH!Iw3iwZ
zJ@E7%0DrnML+jE;qRLCIl;nph(F2_4{rD@5%Co;gtjFx9e7N>y8Bl1eZPR6BNhF0&
z`OCz6`b(2~J<z-8b6MN*AZFze?X^XY=xj_X8)o?D`_gfWVzt#S|6}n@lgTY2vxpb|
z?#CJ9PiTraxea{{ZVPJTrib=*<#`!?pi(>J!YpTIc?a;W81v@BO)6U@@!s?FYI6j4
zHco;{<B#??f&?<3%l<=DYpDqBqJGoQdFvIp3P9t}*V)dL%#8GzXH$0k(x5bXeK{CJ
zeR%ReWZ=ZIU^<`^>!qhS-`O723E%#^44@M1C6cprOIt9{<33b}@H21EGH}>f5Qc&&
zz-;0>KjaKlJnzhXS$^IIln(<M^`j{!nJ^zZwbwFf4#={1fTG9&e3Q&Gz#iI|rH{xr
z!cLFC2<2-LX%pFV+1nTJ<8eLI2b1mP%j`s<?Ky^apVs&AsUH!is^)sx>$#>|=)1g}
z(i~w#C;W(0Rf_NvU*Jln9_ZJkJ;;f`#xWmqRYv)lp|U=zD4p|&=nk8<@0R=WM?cG@
z*?2F1blNV@=KH&Ii%w^_V(vy$B9cc)uULvl!AyonL4--l!Oa_2pE#E>Y+bizW{4&3
zJ&SG`(!<6~7LR6#xj(l;I~gLg>N9_lrN2iF)gZQ+;sV_Ph9AGKd!lI`Zo;`$4pe)H
zapC$OB;ZxEEF!(M8t=5bG7NcE53&(WWPuQBy`FI9hC~*>6FJEqPLv~OFPN8oFaa**
zrAhu~ASIKFI(&VGeCe|E!lwoM$9r1grG^IB4eTlNdVlq%EObmDx78vhnr9RUFMM^@
zVoXUVi)VmnB~^0QUfO!=2(=L(`Q8xi$k&WG`0lJVor&ti7cg{ydJK_+yR+OKoX~6_
z^dW^>0(I7N+W%w?I3|2VJqzJ0+XFu@d~?hBCAD4zX0fFnXf=wy`?xHIu6b%pH6Lv~
z(*Th8p1gN9@t%B<fR*Uap1m8^PxjTAE)VF5V_H+~tS<Rn>$?=7G2eN0hP>v^cSr{@
z@f`^Ql;sg^ZpK}Kq8MKA)@lZ#ku)h1g0sF{Oa?@6{L8<6JcFU1?FH!$k%FM9h<q67
z7294|A3#00=Qp_wgpjf&$h+xeGBU4Oqg5NtAs35we<Y^qRGxB3GPW6IqqlpR@ap+2
zW(0m1rT7yBv85hJl52AB&$3vEj`eBd${@O-mf36|hOc;)s_*is)j*T#(pdbm$f#U5
zo}RTrn;kCN=!n4fT2#Y*t5s)}4(}@8<GE~S8~1Bd-CTrICG&I`7ya;f(JHfqPA;}w
ze$(Nk0yuQ*<9Y%g-#H^fN6H3`#Z!~}T>9Hb@V>R{5m5zR{`7U5gS*e=>pS=T`UbWS
z+&RX^HbVP3#_}V0j`3Aj(|3J5He-6^d*GagT491jBDX)9c=amD_l8Y7o+*6khpINY
z;*s&N7_jDW#3nM<%8EGR#NjVzF-C)Yo*=rt?fBNY?N(TZ#)r6~zxdzxHr`XeXN_u|
z#7NET?cJEItE89ejGfRGQQ_yG-I;QvF#`y-nN^ra)s|C^Yx*ulfoL!^qcedd6A$g~
zR7;XM`hOd?TcG;Eo+uDCvl-n;?&CYWGyC{yA0S#;hSi-wtmNLXqXl@Wp&=sX4ZAa!
z+O}r-Wr>)L$v52HL~_Z2<=B<B3LKislEDUR_r#Wyk7NDmSGG^T|D=Dfp<n)BF!Zu=
z53zqHy**P|cJ3@RI?^6H3`Md*s#rXL1f8C>9}k^A4C#*y@RU0jpZM?^%$K$4p5IF7
zm@`Kjkywe0IUXq_%7r%{iCmLj;rQYu_eCj7MGG*8UVM~DmX3V?u|wp+E8<T7WRG$t
zM*qO2+X@W3E3>S*ZB=K!R&r<FK0JA6S(7Z24ud2PyDtZ+J2UUHL`+J1c*_g?OiN8>
zvto&6AUJsMs(LJLNx|_ie^`d;$GC)UtHZEZig)Ed4Ncl#*2@;-Cfl;!hbMcwgdd)q
zKdQicyVxAD`2Wz>6ILYjmYYwCb4~WInGMLz4&Rftr!^QbR`2RixHOwho_EGO2dh0R
z_wW`rbdWdPoK@9eX~RQ|MN&VXKCGuFVuRSyH=cXqu<&}ATRDizxpB{MwpT=|hqo^W
z=$sYA1|XJYU7^?`O|cdEe1)G3ItE3tqbfo_dVw!Tj~85Ep7QJee+Os1o?_Sl<NC3>
z5S0g@QCrq89!<l(f8>rO;cbtMM|m50I$s~FW2}=B{l=_NtY1ns@~u#;L5Y69mo>$3
zQ|RM#YyWrOG!Mjf6xniP#?jw?X&L2P)+8OUE#0#(XYpgjy`|G5AIF>(<9RRRdH3Ny
zV9E*)7?5Dg)eJFAqdxvb;maD%MKSseVlR&s^THc0jK3}|eAM~*AolWjQ^M=-kH0Q0
zOe_5%?L&E!;dlRKY1qU|A9ec2D;p%dg4h7mGMB+&x_PsZ3}?U^lR5a&755f;bJ#<A
zSne&49gn$3uZjEUVLo}$8IOuzlIi2#m!Y_^r~9`Iz>KrAPHs8nm|;y^e%a|Ben@6W
zj~oYw1Zu@yU~odN=x&43Y`IeGv2&nn&>riWf4O$$@azK;gmD`0N`ZkBh9yllPN)xz
zK(_)bM?{S>8q&jB=vO54r5_x9^m?FI7H==FxVXfwmr1=FemM3DP2I_Z_x5!~cQ*!@
zh=&bShbC4}{ABsLpgS}2TkYPLM9Yu(Wmqel5ICBG#nKMy?)mCa&p8}1wL1#7k>BKl
zj!gYV?D^dCbU~jyG`tHOj_M%mm(Z#Cj^^l3t+3z7VIrpA^60nT-uc=_fA0brIb`d}
zNFFR{m?X2?23Fi$WRV}5*znldmwWX3x%B>J_9MO6aq_3zMphhMdO5lbOCR<si{E_x
zVC*w1H*8?Vik?NFj<k-&sN9jI|A_GKKA6lrRAAiLH<|=*Z`x36Jr}2_FWgjx{xH?&
zZJ`ZVsg*^E;nu7lD{MgM^E*XQnNBO3Y*~sQkZb3U@3O-E-rSj1lf~H`-@BgKlzWcU
z|E5*JHPcOCt;iz`#m4Q@^cvM4{{GGVqj6r>tbWdt_PlL?TWh*QbJgs6+0i*C;*|Za
zP3fHwUT}BsO#SAFPk~aug}UW?<vHC_29J*;){~i?mpW~&Qk$Ay_?#i%gjy8vwWE-%
zGNPdMYE?mh#Bs~<QN{BFUeWWX;guzD@f)$#Q7`Y+{ZS(Qu^C#Z{AYgVgn*w4`p8VJ
z^r=Fgp9(5Xo>Btn#jt?N<mdv`oj-bEtu$B6U3}i`jJG;RtgD6luGbVj6*_;kTG~Cq
z)#tM_>qd0hxSk6~tHs<xeRif?TAkZkFW1++zvN97X8&l?TbS@JK5yat+joI!37#HY
zT(9OFP(F<rkB`piPLf%!#Azm2V4BZ>mbKlYOcYlvQ==E2a)!4?S=XqIP=d#?4cg*W
zX`4V;B}%H1xtgPRnVKL`^r&{fK1yVDY}R)K4xe^=BYElH@zJ(aXfX!4R8Yfrcv?C}
Y5rjt##p;7Jxsprf4(~tZp`kth2RCmQ>i_@%

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qpf
deleted file mode 100644
index 31a2bd33..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 14:59:16  November 16, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "14:59:16  November 16, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "Victory"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qsf
deleted file mode 100644
index d4441ceb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.qsf	
+++ /dev/null
@@ -1,188 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2014 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-# Date created = 23:19:48  May 18, 2019
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Victory_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/Victory_MiST.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/prog.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/k_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/h_rom.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/col.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY Victory_MiST
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# --------------------------
-# start ENTITY(Victory_MiST)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(Victory_MiST)
-# ------------------------
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.srf
deleted file mode 100644
index 14cddd5e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/Victory.srf	
+++ /dev/null
@@ -1,54 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/Victory_MiST.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/Victory_MiST.sv
deleted file mode 100644
index 8f93252c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/Victory_MiST.sv	
+++ /dev/null
@@ -1,189 +0,0 @@
-//============================================================================
-//  Arcade: Victory
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module Victory_MiST(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"Victory;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.21.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian galaxian
-(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b0,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-wire m_up     = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 	
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/galaxian.vhd
deleted file mode 100644
index ff7dc99b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,411 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-	
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(10 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-	
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP
-	);
-
-	-- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_1P_UP       => P1_CSJUDLR(3),
-		I_1P_DN       => P1_CSJUDLR(2),
-		I_2P_UP       => P2_CSJUDLR(3),
-		I_2P_DN       => P2_CSJUDLR(2),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.prog
-	port map (
-		clk  => W_CLK_12M,
-		addr => W_A(13 downto 0),
-		data => W_CPU_ROM_DO
-	);
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 346b85ee..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,215 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));--0x4000, 0x43ff
-	O_WDR_OE      <= not W_8N_Q(7);--7800
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);--7000
-	O_SW0_OE      <= not W_8N_Q(4);--6800
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);--4000
-
-	O_PITCH       <= not W_8M_Q(7);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);--4000
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index ca6808bf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(10 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(11,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 5a4d0094..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index ba7e38b1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
-
-
-	crom : entity work.col
-	port map (
-		clk  => I_CLK_12M,
-		addr => W_6M_DO(6 downto 2),
-		data => W_COL_ROM_DO
-	);
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 8c2df5c1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_1P_UP    : in  std_logic;   --  active high
-	I_1P_DN    : in  std_logic;   --  active high	
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_2P_UP    : in  std_logic;   --  active high
-	I_2P_DN    : in  std_logic;   --  active high	
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_2P_UP &  I_1P_DN &  I_1P_SH &  I_1P_RI & I_1P_LE & I_2P_DN & I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "00" & I_COIN2 &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000100";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_video.vhd
deleted file mode 100644
index 252930ba..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,431 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-	
-	h_rom : entity work.h_rom
-	port map (
-		clk  => I_CLK_12M,
-		addr => W_O_OBJ_ROM_A,
-		data => W_1H_D
-	);
-	
-	k_rom : entity work.k_rom
-	port map (
-		clk  => I_CLK_12M,
-		addr => W_O_OBJ_ROM_A,
-		data => W_1K_D
-	);
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.qip b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.qip
deleted file mode 100644
index 48665362..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.qip	
+++ /dev/null
@@ -1,4 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sprom.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sprom.vhd
deleted file mode 100644
index a81ac959..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/sprom.vhd	
+++ /dev/null
@@ -1,82 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY sprom IS
-	GENERIC
-	(
-		init_file		  : string := "";
-		widthad_a		  : natural;
-		width_a			  : natural := 8;
-    outdata_reg_a : string := "UNREGISTERED"
-	);
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-		clock		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
-	);
-END sprom;
-
-
-ARCHITECTURE SYN OF sprom IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-
-
-
-	COMPONENT altsyncram
-	GENERIC (
-		address_aclr_a		: STRING;
-		clock_enable_input_a		: STRING;
-		clock_enable_output_a		: STRING;
-		init_file		: STRING;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		numwords_a		: NATURAL;
-		operation_mode		: STRING;
-		outdata_aclr_a		: STRING;
-		outdata_reg_a		: STRING;
-		widthad_a		: NATURAL;
-		width_a		: NATURAL;
-		width_byteena_a		: NATURAL
-	);
-	PORT (
-			clock0	: IN STD_LOGIC ;
-			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	q    <= sub_wire0(width_a-1 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_aclr_a => "NONE",
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => init_file,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**widthad_a,
-		operation_mode => "ROM",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => outdata_reg_a,
-		widthad_a => widthad_a,
-		width_a => width_a,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		clock0 => clock,
-		address_a => address,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/Victory_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/README.txt b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/README.txt
deleted file mode 100644
index 9d75bb33..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/README.txt	
+++ /dev/null
@@ -1,26 +0,0 @@
----------------------------------------------------------------------------------
--- 
--- Arcade: War of the Bugs port to MiST by Gehstock
--- 3 Januar 2018
--- 
----------------------------------------------------------------------------------
--- A simulation model of Galaxian hardware
--- Copyright(c) 2004 Katsumi Degawa
----------------------------------------------------------------------------------
--- 
--- Only controls and OSD are rotated on Video output.
--- 
--- 
--- Keyboard inputs :
---
---   ESC        : Coin
---   F1         : Start 1 player
---   F2         : Start 2 player
---   SPACE 	: Fire
---   ARROW KEYS : Movements
---
--- Joystick support.
--- 
----------------------------------------------------------------------------------
-
-ToDo: Fix long Compilation Time
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/Release/WarOfTheBugs.rbf b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/Release/WarOfTheBugs.rbf
deleted file mode 100644
index 9fd06bf9e6b8898f55067b010260a2e1d525018c..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 346666
zcmeFa4RjpGbtc-~Xwk5u*fYh}q%-Ey-8F?#V+c~@5aFBP=~+`f4R8R0CIB%Gj-q1|
z5U9|M6^WEL(Q*9Z?wN)NgkT6#jGvPAO8^Lw<iw6BiuTD%vd;hn+LR@)eyr^3_&701
z(~h%A)*#KqisGO5-5#_BP#{H$$UbGGOHOxn{ocBD>(;%usvAH4@#SIn_ape;zkKgs
zUVU}$pa1!XKm6e<|MD+C_~#$t@dy9>!&m<K2e16#l^?zO>Z_kDT)v|J<x>@a4_J7o
z@Z0d_D4@^7!qRcvwcM$`dceZ_!Zt1r$8E*&MSus0<LOS%R|{0nLWt|X)IDx5PN%Ze
zW*krVtHpuxFT{buas8LN$L+=GREFw_<KOH(uJ20kaXWE-!h;~5gK_*D-7l4&;$yhD
z4vMF^i|-Y{3IN?T0OcW^=uSX!7eg)OwJW8^dE?kPE`E;h3*)I>qDh=acS<LS!;b+d
z>;mF=dX9nO2<W*Ms)gh9_`Wc0VK`2wJH^L1#d(VJ5U10faOnWVY4M%nDNOem;<Pd#
z4%40Lp*F4u(A*}VxEP2oHvlNlZvm)GCm;k+Jf+h!@$u!L4M6Fw^FZ~)AOUsrpk4$?
z07VVXL!3-yz696@pd`X)b{@V6SQuXT9LLA^7>5#o>RiZwL<35vdjh}!)L#OMi=h@%
zyAmE0itp5C3e%n92`Ef)F;HBLN8DaKKjQwzZN+ygLp(xw8GyJvrPCNvd5ZfoAm)K7
z0L3i?ii;tRr~Gj^ZjbK712M#S#eJakxF1v>wLb<J0-OZA2#DLc)cq77PK(>8`woCL
z57Z6;;X!wbru%0ABLEvfxKWvB0Tln+07|3hug?R8V~FGE{?~wo&s`V6D1c~AK>Sb(
zB@%=K0nG^lijV0*b1t4=L=So<n$Vqq!oBlQi>bwZ4e&C6k}g7{i|Sw4K0OodZUGP;
z^c=&d=7HjgH;AUh|MA#80Ep+q<>tyu^AP8ydSbkK0MuTLQ+$tcpnHr5g-yV{0IHJk
zm;}(B>ZZ83jVrlR+j{|o4~;wV9<^~PSTzrEI`!cWz-j;`5uWr+{6VsfU}3lx)7kky
z<{?g__WKt=ejYf0f|Nwz82)4)=s5?V`y&9N!$Md{8;U;*h|`HaM*#6N-D&<35I!{K
z1o6D3JK;j(L+#O><_DodX~d^gmiT~hiQ#g5aj7w)_7?)RM^MA4cCE$KuK({m&{Iq=
zA~E3>Lrn99ccTA7ptOb03vr+@jr&qK#Bm1z)Lx7m@z#$3F%ER6=Qo0da)iS1T#4^-
zdzZS$?ZxSYJM}G&Cvp)E6c@uA;Y8_i`|+LD*my2nOdD#OWG4ZINq*c3_!|K68m+%{
zC!UPq!aUG31>^YmPIIgZp!(uCnzsvq(iQ^sec^Krqt|dEya|sO9-RkzCLD=JX&zB~
zbUzLt+$bCa#gR;kVf_+7G^4g+_yYjRi};z=qZqfP?#}@Z0*F5;oz|x~j^e)npgM`h
zq>~VA1gyLWC@uy{A{+<^57Gw+Pg*-3numBDrnQEE(rTgF_3!54;yA*C;J$gtEP%NE
zg?GZAAdVwEi1#Dpa3P+h=NJ~w)1|`X{P-?_#y<waX8{^Z1|OdX!h<pp`cw}^6MjVd
zh3&=o(0yV2#o-u-Sj-b$V;zL#XAC4)2}nmHpm=(wwdw<a)I9t?fSyV3p!;?J;XrqS
zUjWdZ;s^*I(jQ|yh`tn#=SEBndM5crchZMQrV-Fw|5*U(x_=3X^=i7GxC~q@<G&4{
zxEPQ4PVFs(7`GTNqWfn7lqaSYtv^Hu0t&}K&qSAn_lv_ZUlAQ*pg9ohY1DUWE5?J;
z=((n)-EafZC<~xCT7yZx5zx4j2x$UP8pZuCfb^Dj0Hu?zMzo|j($V6%M)@ed8?X>3
zYMX%OE8QuL?o>Yk(T0G+q&w1`+WF&opzx;wbSGPkbbGp!p7?tJ3deEu90T!O48(&m
zP}>AC9whGQIi~5wcu@bS?HFRbNM?|IO!xis@C@KT%|jeVvh22bAR0UfpnD9IL}9{#
zfYu2D!nYPvi;KsOXhq@pPI?)I?*ZHlptP+3ii_9GbpTq=31|+Jo<TftIf%;=J%|s8
zmx%Xi-Jtb_fS%t7Xw4*u^HDt{%VKyE5X&pNQ+zyc=uUkipzs<1-ERUAuMiL(bf>vY
zcajqnM|XNApfJV7KyfrK1cVRuk@V--9;bUeK5^W;0q+IG@icB90#F<QtzYy^@{06m
z0t$Z+P<yIf7s^%|J8FL+#O)DIF~o6nr*;S^OgK>=z6v0|ih-UlhUYJW7XS;R7UDo*
z;=Q<ix>I`u6ebx){6(^rWDNn$`@aHETnzO5MnE)L2sCGDZpJ|EEd@US(A-;?M!E#S
zQgIajjd`H()xg5~-VVP_fww8}HU+Mf0wn)Po-WGoFLF08N?PK<xG3%mpNh1*1+m_O
z@Kpw%J9xuYmbi5GxnJzQD6zQ6XM9oO<savMut>IFKJy!;e&WXK-YClzr@y|JS6uY<
z8J8b16aHbMdf9MrO+>8X<LW9%iJ_<=Bo#y@bYEji#6U$(<*2YVq@(aqLW3#g356?<
ze?p6j#O0&Ar&t=wBb*3z1(hVI)<rPdgDf#vwz>cX<+<&e$rPo7Dp>2b9kS7waw9PH
zq>`)HYL_?WDag?p3Vkez*aoUf*toRnicc97ho{w|@e&u4Tw!d7y~b10wyKQ%0xD*|
zHPjGhxXOkq4O&i9ira-fhBjLDqj$a&l^{zQH^og-!?j6fsftfs`3X>$h>3|rRz)S6
zDaxozS1LSY=_p(gKC(&M*G~PHpQ5B?fwwrHElVF2W%(z-|8j^eU`OiPoO`j9y@npY
z1;~F<_vSlu>SuoXO>~O{-4gHzAA9!_v2QMF;k1mT!JDh5R%-5%iEAmoxa^x7%m2wF
zTa5B$pB63_uVtM3^!HzTxYp2{BiYieE@X_Qb6iF2+lXBSv7)TYO|i<=B5;ZPMfK+2
z|JPKpFVXCkL@zhVuB6Q?%CpRfS@l=c>J?-%p8L-$t{~f$Wr4tW>tc3wChFxnocxF1
zLb3(jKViFprU;kx=Td!VZB!T*pd^Q}0`sF$SJsD9VN}~y7f`<NH_JB8%5n?y<s0b#
z?LS?P*jJaf%=7H(8oylb8e*iHL{=>LLYZd^<r*XB{`^&H7`jCfyjU~k<~i|NBfs#+
z@1{lLU!&@k?`CUD?-4osh5T{JIbAbPh4(nerTx_4C!9x8?2cCk`EL7#y?=3Hf+6oO
zHRVprS011;7v1^l@Seh3wm8=aci#ER18xVOK@TTI?cvy-h`5(ynk!HH#uL|HdFD6B
z2}!Yhvhw-Imo{MD0EZ=$ms^A_*~nE!*1RmgQIqgjS$3)H3H9g)mPP0%QF}t2d!Q3{
z3SR|W?4JEe(QlY<#)SPz@kN2<AI##_aoQ!b&;50D_Hq%nZ~6gpf7w<_WA4n;ZyJ%;
z6?}^?m9NA1O+_p}m%S-878i=<*WJ^LBd_IYnTK+D7&hwVbI0q3uBB%S%O+m<6OxR}
zre0rCAD{b;-(J}6wS<f6-0nlyQo-V~Z%dQK^tghj+T6HC9ec^*Z!6w!E8faw6mQxF
z;Fsf2+GAS`fBl~2)4Xe5ipBNQ(;K4o`XY$=!j@}M{VpQIdskk0W!4*Mb&uC}!e75t
zyRaYL!iV{=SRzjO>oUa_UpF#K<y{!JWM!ZD?6UgS7Pfb7;bm4Bt__)mrI#DA%EHR8
zC4BFbw8OqU@Rn3cscUa##Fj@Xje7YX{&;!Dk!k_ME*p<sZZWxPj4_tWx0ckrIRB<J
z@8v&;v0UT)?`!|;U&DC}zcl8<l1lkCMnb12L353@ELq%Wx#4Y>_wu>Ci|4-nD_1QP
zserSnlso@)>qp-?v?$>k9_Aet*HD9{zgGAj_O90+t~$gQm$(|ud%on7nr)Q!e?7Xm
za(Y@?bEY$ubm(v~ERNZBIC>Rhah9bUm&ioF#jq%5&iKv6sn_zf+*;|i;IgRfTN$xs
zQ`p{idoLRED|uLMMSi(dALUI;?InA?oXYpIW42t&Nl{JS`Y_4Pe|7acsXYGux9(d7
zZ_AS<=fEW+Yiq-js^~RF{_8rv(V=U^Z^`1M+0!YL=rGB91Seg*IZwwj-ectNcx7Mz
zZhLz0L(W8st^E?tn$Wov96YIcxG%o*Gto(uw`y_zJaAuh)@1(SJ<EI0_zG49U%MoK
zE=-s!e{s2-6-gy=?nB!aR(@^at5LD6%l5XYDyIxOIJ>}A?I+#KmbonMr+)jbE3Ge!
z_{E8fH1~@V?YXa%E{eK_$Ez95H)`f;m8`|)&f?k=+IMex$Kt4Kcp}WMU~*nr3vYYA
zuZ&Kw<@*1V$zH=^iO^dav1Q{|@}e)7?yV?4OoNV>JSnnlD*3;Uqu&3nEcqq1&})qR
zH>r6Wk3U-Xw&#2K-q$ql`Pp~Av9w(JUBlNe3Ui%zFPG|#gT~RDF|TjrO~qXCYPIzH
zwu{^R!ijg9icoAv*<mY+U84@1)inn*P0LF_Tsglu-MaASEfiPN=4*zIO&<_=17Oh!
zoW;WfL;!#Fi?!P5iPb7plx(fS#rZF4f^b}%A*#^7Fnf!o!J4*ttw2%pHADc*OZPX*
zi3+*ZpHcj<!l{H}am}$bM{%Ov6JMLl9ir&?d{eQ8<ihU^)LLA8MYBGy;G+ZBgrVYo
zMT={|^W4`Tu4T99Y3e9>jL!mV>0-1O?haT1ecOSk;A`{MBRuzyYjHK_>xfXUwQ>0?
zD&D~rr(DYwu|Qn*gRWK4ESKZ+3z{fWQ;IE=lqP^`4If5m#%!~w9aF&<Be=!uER9=Q
zTH{Q~sU~N<P%uFVY68Fa4r^9@LQCZNP3V!5V2Ey_uT{)<_hKq6Xo4|RkPB3v_v=s}
zJ{7^nY&3;|0^xB}{C?w9;T^z%vwqHn(uj(iv_!-hHjpk-Ltq(8B|crU7oeww&oeWI
zE6PQAYTU=sfThp<-G1Cb7YCe%3o1lM<8h>lm*zi91$C%^>3~gawSZcHel(y6Dvp2Q
zFYw}><7-Y4tQbWhfD8**B#OTHQmdDP#vr^;e8Q}NYkAH<8bVqr`xm^IC?F7n>YOMR
z-$B+WvIdK1SR6~ls)cJP5zSCXg!Rw--$aJm$oh!m8CT=B0=9{U(wZ;$T2+ffghP#G
z=Btj9-BZupQ1LaJu*7Gw#VAJz{~4%V#7M>nMdPx#LSjox1zVv1Xd6F_VTA@{9*XBW
z`V|^5LRtZP5XC4BDC0_F7txZUUI(ZSg%-d()^mUR^A^5}+|Qf(c^3aU(;8g2pYPyk
ziQ8+rNNIM_bv2u)0=6R7Gf~^?0kJ0YGZmh(Cv5KEU(ODA)mHrqf7s61T=nq@K*%f*
zfoEss<G)vD@ycFa>ETT-Bu@|T;`egC7a5wgoA?w@0Ts>0cUb6CELITMfgQ2_>zf8<
zroteSasjt7efflKWiZpY!z|A06wagG`+E69KX~_$&$R}i5&bk}EfOty;N4v5ivFVk
zd<n*+uf8nR7Ns#CzRKvwH9u2_oKCLxvozF?V%%?*U+GlFcurfN&&@EghVvWy@#^U)
z&$;ySX~Qu-!8bSBYr~>ugFk2wA+09)sz4h{rY`$>s{h0hwezuLTFp(Yq#mki%^c&=
z3$NU4vM2ePJ59wY)vpVqLAUg6!`CUk>rQY-*lW0A+X`<4iwa@qKw_nVMZBrt!#DV^
zq?hb=Isi-32XCB08l=TnbBM3GX;lIhOIOrsWz4(v5T>n@;F?&^d68*z`0_S2W%E<E
zWSU550?mU50+rfY64K*Ike}zqlVdy$VvcQas9|oR;ao)>!*HTb&{!$o<Iy`j4V4Kl
z#26Ro$x-kyrU$;lQ%RydG#0gI+0-6dU8+U&4T-slBrWaeTZ<hHsRJs4ImS567GHBa
zF8t;nVML2Pd<`fm8nrHN7xNJ*i!_=|)F91r0L|u0P?GRK52;7Fhm+_<o`ddV+{aXj
zI#+A1T>jxB_zVyR$iaGp_7p+bCD2gHWoR4hN|Xet7|Jg_YLvppcuSqHrBw$H)D*rg
zWN~0nTj>?Y3NM&nM@Oj%i@T^?P^UP^Tmil8NWh>GU!_hh0hoTE3x>yOL8laJVx?l5
z)`Xpodqia%Wp3g*v{I~0&{Eh?r7qy@>;|q)JwOX6I)fJIC0t)cyrL}is;tR6>(S5{
zI))V$B3LsVnu$u|1CX6lVQqEr#f9FlQKLYt7*JQ}t={L|dWxf1^Nrv2t%+V@0i%El
zMqLa`?Y&?O!#5tez7h$N3DyNs*Ohl5NstFZ%;D@KV9A=?0)i@vLqJ^WwPN3%4l(kv
zJV8&)d@<nYAsg+7tl_Wq>G*%v-!|5k@0ilkXF3JVzSn_Oo7Jz2M+BdbJoWK+<?5A$
ztI;H}1vr!YBwa}Xz?A^pxa0&P^@UhJf=F_J#pa>u2B)TH5<eC-$e~EW%-49?D(7n;
z+`)&K2J^MfJ=s>P3%CJY(j#oNALGfay7`i?-R4Uo!hs41K*Uclj-K@&zxdNkS<fN?
z2wfo3KCuo!kVF8{8-2blq5@G(;&X0tK23$ap(@BduhbAhK*0G6B*&5e2VwNN2z&*4
zQ=6O+AT=OVEc`G-@ot-+)N!OqP$a+)w3^})Jw?rvZ;*O4WuuWF-H9ig>P8GHw`hpe
zs|ex+BSJ{=YFHzMo-I|eGIgdIiDiqBh0cJAQ2|x%lRo?1pO4gG)J|Q7iHmr($kn)h
zibpw=!AIYi;<!b~DO8Sy2r`4pIMx{(dQ&CPxRMp9*Kr)v(kvK#6)dbM{o^~3k-%dS
z1*7mN>70NX;t1dq&$yNd%?RQI?)O7vMQn@=R53MLn*?+6cIsEeaJ5p@xp^Qg=f@%H
zH$~TmrIvw|15_jN!&Cr2%$HN<&c9F#5`qirj?*LR(Sx_cEzk3euUP?_uAxP=rF44Y
z_y-&v<+%q}pmiiTP+0}ZU0?$;$3=(|lBnxZ&FIGt*C%_7Dxw(x{S|A9jsF%FN(R-D
zG-{|;1s`;#E?_afaO3@`6>N8uX*Lrmv&L2|$))B`gW$xS$cj3tFtD)!YG?4EP|{#5
zENsx3EH!TheB3rMkca@W3-dM&aE(+A$_52en;ZIhsG2~>R%}AkHch2b&8V=DfG@>Z
z$!5b#9WkV2oi;iwX;Pt%QibVIh`p%uWR>xP4{H{BB9OCGOG6dvn2mW5krnMx9_3UT
zUlatB+NYqcs|k*d*z4I8OH>ZC^~@Y)5gO<jE%?+$lbDnP7f(q{62&a^7hGXM-KS20
z!qlEgS;%nUHhLD(6I{?i-6Q}Ha77g7pAZqT5see7M<ZZLV4_&#HXfoT@Pr!C5JS~8
z<05KMEIn$<fA}*6c0VkCRN53sZ7f0@QW;sn6N>?@foNn0Q@a*=PSxQ`54hw&ujmPN
zgAeAu@-m);f>~@OwJDa;AX|~I)>^H0LPz3<>v|(0l6olsV^S>W3{eLZ*%+ofj9k*3
zxn-*y4Rde<{i7~e=eInG{s-f>fQ?R=5v?&GeqE{}HH1*PNB<NL6?dvian{J{9?#<g
z<VD@_JX8`@1mrEvgp;ApqKSeFX=iAVDnXn09sBsZI8}&lSrXbG`psAdmm;_As4<8S
zAX&n2;6^z|4KJb*Om{*qf{04-Lo^oD8O0wM0s>R42@^Bj15Mp*;A*Opfm{|-_<#sw
zsmh(UWp~pUkg2!9NDY8+owl4cFyfK;W~I!7VzuamqLgSBeAL*&ase5IppeOOww=lF
zDzN35Oodl7)d>cr8Fi6$W>?jGZrtW+SfHRbO)^XC-}ak7U0^0NQ~jiZ3zmT)vxiqO
zWl^cDY+yIpEH5Jb2rc`NAyeTYqjbpd$Og1F7$^+n))|{bCdeSY#4CAYosl=erKlq_
z&R8C(WjJc&ysBaX^1Nel)v8k%8l^-V7=Z`KVCG8yd;bbj%w!D}D8~h;mL`6%EPc?1
zeq)R^;6tWl5rZA15!QaXrAk66WrPz9mr9?M4o`%UWr{MfcB#x8sgbdYIhjXOeg%Sw
z;yGvnZovOBvF+<RF+z)G+8Oo6JYStm*B#B5V3nS=CF4&VkuxD%jpe3~d>s%YEU`hX
z8n+W+pIy=$g{o{Zr^2yh>m<*;=)q1+7R5L>TPO1^EA2DMpw7C}c6nonlnmueXW$ou
z#Q-Y?Z7KyagX?nIYUVnPx<A430jD92<c6d4-+Jr@=<i)Tqa}_pTlR2RZvu7)%&M^@
z%9_H4g=T|7c<l0EW?5>h?yFc{m2EPqpOW34lU6-nYn@yf8J3uY6B|IJya~%s<*;uZ
zWPpiDG$jWa@P{b_qK|<{6R>?>`akO#bdfySf?#5MEJ<olI!J0Pjh|^-(=}O{M$=4@
zEZvQd#i|~RG;^!b8crnJ35gAc2TK;VTb-pUEgaNfSSP6uFxg-ez<?s5WT|67f@86&
z;b74Ey!)T-|CFzy9duXAJe(9ZGlf{Q!6d`dhKZy!b#oho6n(^2VP0!Eo-9r#O$oU{
z7WSNBfJsu@y<B9$%drh0n3Ag-Bg5O8*a#ylgCWU4JP>n0#sDke$06BCuE68Wi{sum
z{^H%38|oTfbSJPRii`>$gRS_d?If!NH55P@bOc@Lim*sbCeso;>tkpzZoE_FNO7D*
zh}M8Z3vhtfmHJzuIRh_16+Ei><13MjG4PQO&zJ+4&5n}0z&?k{K{^=afjY{HkfV^t
zcKS521<d4AH6ezu=TYAo)QT<-%c;2q%{_%-Fr|m?=!ikT^Qaj1ECxQHha3$A2Fgb#
z(0vdH6e0eCF-^@M`?Krd85vJTz7;HuzKX?CG2#7)n4v*SgBxrjfZ6JS9n!YMM~1sR
z2BsQMO0cQS@eN=LVj*e;tN=<|kQl%My|1Va@}fD6DgxX`7z~Q}0Kl~H&wd-aw_+25
z&1nuze$=(PxdK}`vL<M;R6N5e>SS;yLKQZ&=Q%CXK!+U@#F#g_Nlil`EZShWJgrzJ
zF9vWPFjT0{o4@G#kN*c0g(5gr5h!WH`qmW%Ry@4<<P#@65bsfI^Jct<;sv0AXbadu
zFPjQ6_=FgKh%bQ6DIWH&f-LCQg)e`XcqEBkiH1r>Z7yIn;%Z|U$-)<0U}=MckP(^W
zcB8;N+>ZcH$U=0mCJc3F2V|j{2zecHU`CJjldz*496S^o-ilR6egyP0N`~tJsS1h1
z^CLIEeK>J>4<{1WUK(iZFAbLZTDqkxbIFa!>r)XC@js@4-;cRgjA|)D?t{NPBtv`0
z)RJH=$)m^lW{3eTgh?}w5~4>-bCb8WMOnnWTBx8_j!Y2rwel#5M`Ctg1JjY&FkeBG
zfi76&!C9!l#nwqJ)~ba1bGKfPhbXg63Zn^ZBa;(NDD!XQL^zL;LR8cvy9G6&WlU<C
zFf~Bajvs(Ykw8CX?mIVOG1HVrEhd1*umc8>O{Owc2H}s2fVN`UR04BfQgt$t@RZ_2
zsb-NR6@edBPmO=~cQE6jkRZ~AeMykeY(EdrV4y~*;{)%gI;sGd1evSzK-JrbgFFg!
ziYsd99IO%qQFT^#t@F1&3glJ00UA*kuaTK7sx_=ptyxx7j_5*dTLFp^Dw3XnekAE2
zcQHoP1Z)yCXQ^X$tp|`hG@JkGX0(QaCcFr+mSaj{aA|BEi8KIA7OK@#q_07jCPe`C
zn>+9b>O0&&!)+Vl7gnJ!b#uz_E6mfeAUaqn(SWBs{&k!g#AX<3i5aF&!AeaiBSS=Z
zR0YKz%>u&&TA?PPniEbwn2JaP86<T|K(T0>5XPJ`_x{gDRm3$@v8c#=$=WlnSkUHE
zsIpoaAPKQn%i{5f%c6(5)zLe9R)u6TR+w6j+O<~AJl}z1@P8f<@>PMU<z%@E9D%T6
zP6<#!lJulpQ$pGIaVts{mgbBy9|ygaBG+sz2tR437)lV3R)UECi^A3Yc`Q)}Vj=1&
zGq(a{l#+Z$^V0(8_~(E7PNmYIHL14a6sGdR++jCWN~BKBFf-T3d4tP|q>c0ag4*6L
z!Qki_7JZMStxgRrqLNYOK=aD`Jb<ajZJ5j&FJQdD%vK#Yr<%tYxnA(Us9V}y!G%vX
zAQchhnJRJ@y@n5wv8<M{Z52aKyhD-)w3e0)-xNlImt2@>1|}c%Oe5Zdp$V4epgsCc
zqQrMW1kcxC7octgraa~5U;ioQ2X-ZZDMdt4K{4`m_-YY)IFXx45C4Bc8`$E+bC#Bd
zwWZ`?6v3K;VFD|N6~-_l5ettstbicslgKTFq|ud@3+(*!@B3rSRCLS{$_|_SR4`z{
zcQ~+N+BJqSJ5`SchyV^U3^7I@chcU13idG3TXX^iDF?2|-5JObsDmQ-@vL5U%I~ed
z(>erSgHv=XP@$268Y~r(OaTT^F{ronKk6m*6EQyl#3MT%fd~w<D4y4@ARiovXV#5j
ziWh-A%^=d=aA=|tss%PZ=BtD{!gffdq$=b^v50Kzg<~BSsDbK7gjEN96C2;e2(T_y
zN2c_Wn$@!*^~Xa`Eesh1w&TwI$E{X9R3xGJFJL!}s94ne0J?{zrg#v5@R<8Hn3=ec
zc^)eg-8mGqqV6fh0XL#410P~WqJ0I!<zo%2Xy$su*9tg)qK^u{Qi1GHB=$j``!47M
zUIGzJ*hi7}29p4TXWJyGBXZE(ogXY@Boaa9+NhmExKRv&Pf_g}E)EC=&2jFRMyzL8
zlX^2hZSxt<o9@iyx_JuIYi&L^4MR2v&cLgcnaOAQeazKZ1MlYMO*RpimE?dlQ#xC3
z$j&}#LGM(g<b_hd+sWN<M!<0Hce9gl=U}#uvwXggvma(@Y~*6&xJtKx+Z-E5n0Z{=
zVsj4;ugpfl<$AHh&B7l5t9nLAM`n)*r}Gi9>YqOUv%YlsS9yQN!REGLxjnoeCeqFJ
z1f!n<w*x+LYH#2-+laR_8zMghO%luAV3hD1HQJ|*QgT2t8k&SBc)q#QZ5CMrK`pC0
z9E7uM+var)2SvzI<asEUr~wY!ypi=ppDguB(<?TMcJvS9J0*(7fXn5W;2-K;kuGaF
zXtUTq;)OgJ`_J<UAP~hx7c%v0Ka9w0_CD->$P=)QlY<X{yZC9+iL7~)kFEVhcdUJx
z68Q^`px4p>sl9f@Q8^G3zw&#;Cw@;e6R>q;K0n1oCbMz_zbTp4*6=kMY)G%!g9Y>4
z5oX`){!wx@i#CnPJ88m(`GsZy7r||??xxvhuk|>C2Y^1h?D>`3JSC^emI>M^PTKDH
z25Tap;*-4bI#_YY^GDc+gn<JSTS;R&=BnM2uNvRbIxAXAdG9D+VO8?@Of%|GBrLBU
z&vm}>x9><xHnFmcH)4Y~myzx<Hl7p?+3&7<7<;Ab`6=+UnW(_lgULvi_jt0^5UOm2
z?Fo5>X)v}CCLe^Z)(R&@ov&io5{5sFXAXxSZI6<10D}|e{zRq~2AhSM*cw*5y-r91
z6brRhBh(c4@lEdp+48WAU9B<W!sS!j-+efVy?*c@CJfAA=y=h*Yc+HxB};54^AFQY
zS`(}&Dz1mBcnf?ESbWkzKpi8a6aEONrK(~*=8#+kDbuPfftIb?y_UMxj|$Q`y3ie-
zV`7r8{>)giVxvt4RB{i)8fR(AaY%q%6M60@D_Rpa;iJJr(`Gv9!6864DHaX-LpR{E
zI_bbl*J16#$cEBfr;zdOkpJF6D97O};lNaGCz=)~Ig_n=mxpAK1Oe$NZT9*9{XJvJ
zM1@O8KCvd#Qb*on4s#L?bI_!RW4J}40;`;?aR?i<Z+aLT26qYBqd<m(pD^OBURcpQ
zh+quBL<T*f_8EdSST(*OSAgmHLATdFu@T5mZorBTyBv7J%6B;asL%QTexD*N4SLqG
zJXpnUR1*_qQrki}1+WV<8=xuMHYh+#Qma9163M_W4_vp>6B=;A#6~1+?};R4j!)+W
zfRYcZbPS3oEb$)CQ;rJ$a1wlGCytAVQLysExuJBNDb*`>zDTDq)-xQu$c!fwhanwJ
z_zmCyvp@+<e)vD&=}r<sK#O$J5CP5g1V#k>>HsqwuMi}_$Q6Sn79I-h@B<|pD7XbI
z@*>oEeiAc?ccW>r5u|uRFK+jICc-cN60MRjeMdQLdyWMaW;bL-%^ojmq)aG@?KN*f
z8ycPpi6%a%iE+YqHY%jjSf4CD9YT2^p9$%GRH;z_!I<)4NGJ|d-hzCAUk9Awy!YW7
znDC($sD6M=dxhKpAlg*OiyBd#s0}Z`0;d7Z7v!!`Zo(2d%-Wd%%&<C)1x$7<FO8Tv
z(OCgn=#?+L?_CuI0u{J4RJhtu&8TZ3S+O+_uPUVD+6N#=W1$M|368OVLx*P`;Ve-R
z#A;0>O4LCeE|5r78XtkClv6v0ViAjBj~pbZpbo;6%Oh>51yZ$hh{S5q&>>adZ-3?7
z+x~;^TlF-=%K;1iDner3LS3p_;-)KsFT8rgkSNlTJsa6AD&>>DtJw5R`znYlVmX6b
zkE>P%86=mH0vTENl*dOTI1hi53>tG#fuN)(g=1N@jC1>c1Ikx|*HIMeit5L;R=uQH
z0&o%)vZAR#lOu|aG}9<7q2E%?oZ{*7-Zj@-YQlAK93Vb(l+cP^bl#8<s!d~oEjc`p
zoq%2>b*c+XcCB(;BO8r*%%hkh<Sqab)7L-oK6nvn2XH-BRb^B-(l6=Q@1ok~!LJ43
zH6z~%0c3v!QFBN}NlWX2mIVFPQlsi2$i1?qmEBwW>JjFoeoGkp4H}_l`?#dA_YqM_
zqB2?w2yj+as9i4AVOxg;?y`6Uvp+Jc6kaBhKu4QJb#Mh)$mZaWrhVb}X*bkKxp0YW
zG`LV~h$DZcuGoaB9l0_Pm`5K{1^c~t5)$=8681&y4M4Vgw7~`q52%|~pu!U%d4!wo
z0`FZG7vTkvjm{I2jgfF?7?L4$r?|w{gJ9$Yp!)ra3fmQFunXZ;aL9DR4xW#dl8jHN
z%1~U8ZA1PPx1sAg`BBf(T+0wTgpgAxsS5V5e63uB&Id6y*W5=mL-j-&kHSg;&jtk|
zPC@591y!P7Q-%b#mTJ?Vy~7>tA)yFu75_9Mx20PXwu4Po3no44!}!U$fA}O-MZ9mR
z2!Q)-umq4NnNL7XBLWZf>|q9hCn!w$b7~QGAkgtEy5qy)tfX|`opg~Cd`2TY_g*wD
zsM0RJ!xkuoOdt|Am8lnS-vUeYfxuE>Vd0*@=NqYZWCFl(iwixL@pt+nG|*AS?!YRo
z%?<BTiiAMX_4J$MXcnz0U4m>XoFZntqFP!B8>Hx-=1d82CBo|k{1~t!r-ZM<`T;gR
z4NRaGu(~OH%*_R%=Kq{PTOgNN3^hlBYMP~k?e6{Mcct^JkteZ2OwleRj6Iwfu*Pkh
zjHxl(Qg_HEtkZ79uVhdL0R|R0V~3EOP;?Mc$sA&y^be;LDQ%}SkF8KFPyDn*QYV{q
zxwGErm0nISyNc7(0kV`~y=t6ue}Kv7j=+7P7PTE*xhbmB<FK`KMKn#brkNB7>J>FO
z`4q2H>g~3Q{oHnvQ6|KM7p~Ng8VvHn0n3!o9^Cch2gO_}VRLp?Fu_a-W-@!q;BSnz
zRNOL>*Lxs9n<w-iZz*eB*@Sfyrxw^&oNh7mO@|CqnrI&ulDZYUG>|U{uQx27Hxjf*
zZoyzu+d&H&aT6Bfr~q@p>1gIV)keq>GZRe`g-_vd2?w1(TntS=kl-*4b;og?4qnkZ
zDis!9xaSp11rZdxsm_G^!dE-hlnzB4&R!xSSPMgpbQ3B+S#Op`&OTDMk%pnQ7z8Hx
z!LqrE8054xaJNbts*8xoR|9Kc+uAx?fxu9d9a8CvQZP@U#KOQ*C5D`YFdYE^vq}hZ
zmpr-@_96j~oN0{Ar~!K7)U0o766ZzWks5bR?s=evct9)XbcGuIgU#1rrZuWf=q2#m
z(I+Kgs;x7Qa@Dpp1zr?X2#EX&ejkhh%o3B_x)w2j!aUQHHn<y87=4kLsJ?3Hr4{9J
zQOB-{UWTj<RL>7}IRz}0Q{MTrHs~P~^wLH*J-bu$AVly)auzHNE}9ln%63e#c1?~N
zB_=TSm>d-eF)cc!I4pL^DIu}>gc$=Vh@}SxJI0rI#+x*(5WML6NzlP_A&1(4snYJA
zYu^hhAI8vRHRj+10p=6OP~pUS#^Fts8D4r(U_fyS3lvB90b{nLj^RI#q?WI)!%T+D
z7lVnF1DSwxNrTe~%*xHk^Jf<PI>!<-0-fT@T|yjtamCHtzAs-n2Cs(Qs5SLv+BY`0
z9yUJwMCwfc6Gml2v$@4y!&dWkDL5q36KsoJ$|QT-JA)^=9ZZYTVNt3aGV)tkC#KAi
z=5<EtVH{$3(m34AQ_Vs-YUG=7Z|7?1w9Ffu5Y*c3U~j4)vp6sARGrcj2II#>QUsOY
zu)%VD5IP$f?@;@Bd-hS+Y!^2kF?Mx~iw}6=xZQL6jMrWf4}9L^;;@HFFyXdOxSi)c
z`{1v<vymUhVS@l}+B4ifY_#|HHA(N=ZnwLJWrZ8c8KX4K%%;OeDNyfaSxix=vQkM6
zl)x>WIPs8^$H|-Vppl(5N|gXdG}`;zLVHy<8=aZcvXU3=hYho7V{=OP(B*+KyA-(m
zNrUNWo_VktXOuQg+EXkyp7Kgzeqb-Vy&@WLqQZ3HA@SJm;9D*RMz)FUgz&X3Vn<u~
zyX&s2sqE0>HS7SEwr7FV-8c^sIWf9<J2Y|9=~LUef*&^Z$dMt<JbqBbk^0(2$zh^6
zbQz-)667<nOU47Xd`VPnmGau{2t+yPB5)?+5UA*elg)Xr9gdR_fB43e@N*saxK>8W
z5hUZR1ozsH%k!`Nc#7FDB^!=0nCGLc(0!A8b27Ni+sxBXv9<ws&EB-y$oCv!Gn45<
zhOjLd=CHjdGdLj8?Tu}`u^C&bzSgwI!}<ODa9)77Y&bF%<~x&<yyXSTl26OY42Rn~
z-(A8Pij@~|kfzDr?yc!du`{j)U&>=EQEqI*HYq3Ips@DM81Bc$S9X`aogBBNgWd2x
zPd5HxvSU)L4?E7b{R#J4v5ep-KRfPC_J8P(ccqh@OL$OnnrO_h?L4El9?RlrJ2t5|
zvW6Gk3FvEMe6^vRf=eUA)mFiK;4CPR1t={EjL78Nf<1dB4;KaAPblgw(?%`ZWU|H8
zVeiY$E=+HyMYTC?_KzoV2;!V!jNz#ao4qxh>}E&FF(JqD*spKl_F1o@josz6hLFzv
zycoXp<?BFbpw*;0TpVSADl<X1Sj*So906~cNZy;BB>#Yebq5LsPKZdo2$R0x`DiW2
zGg5EiGMuoP5}gL&_#?ou*&&b9U<!@39v6(OTd~U7@QXMgDy(Rx=O#9qZm#0${plXB
z4IYASuVbP=VN7mdZo6(xdR(?m-ldEUz`5hDTUP`pq)YBG2x_<=nRgg24zXq>gWG1(
zPHDgF;<XUlE^L;zvJK>f+`&c$d}unxnGQsZWfGH+PEk}#MTNgg`V4ew=@E2*!}H)E
zS|_mG4_5)si@?E!b0sA>Ske!JkdxdBE1Ijwv7a$LyaZ5|Ijy`~^EyF8H^;Vbced?*
zC)|tZV`IgI8q__26IfnDGh;F<GU`3#!qw7W6-lkQ!eKzgX{E+Xx`~zFG@tjtzOsa6
zDq+AK0iM&-hmF=ro}gTy7<tmhl2amGNuC#ijxXd*I51Wl>*+X0#|r80h0{t;Ck6k*
zWI{Zg?D(iBH1H<4QmjxqDm|EO=b!!=3?QU07*ku%pc*lGvy0<6@WM@Gn&cUGVgru2
zjBPY+yXe8*C*KVW1&=YH0#6pC!VWkN#xgkQ;+XBKUrmY%O@0kTSuf}~2_1LgKo$;`
zvAicDHq>RAJIG=Bm3?s0W1T3&6-CCx?iF2L?$|HA14ld3L^fcRc0a%~fjrFDtV|~d
z+?I!vb6G(%CBK#2q+62URn5dX8_n}q8lfsBPs;%m#*o0v1ZR>4ow^fK-jSXOMjOMF
z7)zdV;asveyOf1*HK3SFuyUP+DIz9QEm$dACvl=kj%C>B0QV;ca@uBZH#FWAtsnKm
z3y;uwV_0lC)rMe%XQdHy`#2{r24^@<C9zVP${53n>>(AWP(Qo^!_4UHL_$x%dx7&f
z(9~SGf>@Wp+Y>7iGeSX0`1qU@RIOrIk&_;Hsuik@1@{MP>~w@C`>}pQ+J54TIu5a@
z@UX#VDIUtRRxJ}beLR0Ugt`Px0-7Tfc1aE%_;Ij;!@mQ>{AmN`hQ#TTv_@uLqi#aw
zm<o~NlJQhfqSrdgi6gGb%J3lpmr%pPU3UN550wUuGbnov6&wpmISS;uJaSjf{quZ3
z+&3vh+W`TOLm?CBy{)zenVMUiaz#r9j==OupK^i<dJgWPeB>qyaX{oQ=!!T#64eu;
zYH})-J1R0-D7MN1^LAkq;KM>Yiglv13FLr?b+In3I{&%NZ@Yq)?<h&}+$Rr#ZInd4
z0($}hpDvdM%CiF+^a5}fm%01XijqgNr8a2x0JO=-{!Hkp6|6DREPa*1{|w!g>`j=7
z6gg!??ZRZGlgjW0L+?eFsqG51dtXC~5bXd9TLnD%jZgkm5xXoL77m@|gq@zyp#uZ#
zQe;;k#C)4-K!FG#^T;BFE=vk6Fs`{<ymUq9X8UzTZ0ONhD*$E@wPKws{CV_%DD=Pr
zLKM;kS;2%1D#A7DI}9Y~dC`jvXp+E!=5AXsE?~bA_$op^bZk<Laik&S+Rd-xU}%*&
zcrTBy=Q1Ntvep6%*TQmQ#d;qH)=e~3Y&LOxAIiP1gb*n80gwbSu*kWXtMGt8IRq+}
zTXxGjYB$$|5ZGo9;g2HR=nOtAXVf_YxlWt&UwGm=#S{tVULS(~825xO%>fj}1}a8O
z*-=?9B=YsZv{C|O2#{v!!h@d-zQWd%a2FLrwToM7VZEX7q83=%j@hC<6k?stiy&#S
zdLrSJU}bYZbKO&Y?>6mC^_e~VddvM&7+A%g@~7pOalC<fVJi#?*wGnR8!(kAhYlrJ
zNhgV}Dxor3PB<FGx>qhTPZLrk^ubvu(@Oh{2_poCzUQkYR|_py97gaV;0nJX<0C4t
zQ--zn8H1mysLDMbx*h`Drjcx@H;0p<X6~q%urgD6qTE!8xM4>n^c<@>*HtDj%c!Bq
z;pwskQ@Jz1$|lV!TQMsehHzT8tVoE){kFfi`TBe?g<b4UYy|iZgn7Z?Nl@fqXzX&c
zHxxDp+&tix>ezmJjCn939T#U^UjFn?fw0)rMh_(s9z&>vAy@+(#eJ<<d&SOE)|<mZ
zg(c?05!6L|sSaS25<}xm8Buv4hgItC7)=h4i;QEKtMzo8NhLO$`@53~j$r8d5_6$J
zXo*Ti>L5EBMeE2rqLr1<Pof?`XrY_Fnh>_@x!(4QpDc%}z#5V$IF3z)e6X?O;T>T3
zh~Pp3u4TmpOP2kL%9Xia`Aua9+6An~SQ<dZ-^*a>I*p(rJiGN$!A1qP+j^(qw)4;*
z{3mY#2mxe#_>$_2x-Z>ICU2l7xMX&~Oj5ko`Y=%+ZZ-Y7U%@nn&%%U*$P7R63!3P1
zibGNhv&;;;1^AD_JnVC2>ZC{wx%KTcToD7FS#)eZP}w29_dEA`<?Uh4J5t`^KCKNJ
zW*FEr1H;K7easDeWml8p3A9-34Y7K|W5b43Az17EhGuf`2e4O4s&&XK)k%vr3lq%G
z+v~>QTYAt4M};X5exubj3~$!xQxYAt^uFA|Fd<m6-!A3h!!WmU@@p`!r0<YK0q=M@
zZ%DSj*|P00-y3plMKxP(6E<p2=QpwZ!>Vm>>aTK~uP?Os@$4=h@-5gc4^o&jBhw}e
zr^BbWhtq8ZuPm#5;c72+(vU&e>FL8qoDuz5Z5rx9m6d<?mB0IxGMY*;gOMJHp$kX3
zXgz6;z-Q-VrX4eEv^8f7V_mLys-kA~a0G^K=vgzSH+)#Y!M>vcheDgsvid2h!GWR3
zV4n*gW4#|tJBfl}D;Z2T56%fT;KD<ojp3lRatbpDj;FAS6EqeZQdxVlUb*!Z6?_F4
zo`IUk@`HM+IW=YA%)Rjtkb}P>XfW!F24+KRJ$Y^*+ljY2dqN0E7P_)j*Ew!aIX8`q
zrk*fNoy?|O_lpL%4&}p6ZL71E`O~!NI>BswhN7ziKZdBz7L-A+-U*?=x$nnzx|(p3
zBjm4<z3aTr3x9eCv@~hX+M%6td);u>QoZ&dslyus;nAt(8#f5@N+*tZ-d1Ow>86Cy
zyxm%nW(I1_o(%)F6S|J0<(j>$spCA<z<L33X)3Ky+?h92XJ_5|#C8bt(A+WYg~j?&
zZzNDl*OlPYK7td}O5!1N+Vt`65gzBZJ&aA2V7#b@0px%xiw|M8c*+3QvINuD8zNQD
zY01LY-oS96kJ*@XBVk2@-$^M4#quhM(GVX42;fy?5>vfiY2w<bV9tK%u>FZyZ&;i1
z6kqpzRv(T@R(522pzj(hF@EoVf7hrnshE>W(Q{U6VqXa@H_4abXv8dEYkHFc_x0tG
z6<GUR);0t$jGD*dV`(E05x&=KO03Po8G#TeB}1mu4A(QT(>%M&%_JfB62`1owJVVK
zC(D@YkZ3`>3c2FoH4R_m(0||i?n2(l1^pEq47BQ;@o}a2QbpV6-V18hhd1+Sr!iSS
z%y8`CZc{=`j6A^VN5Vs8GsKEMoOH(RQ3yo2y?oFOZWMC6V-Bm6vZ|)ofUWF<4VfyJ
z2Tp^JEop|yq3U7LP|;*KqK#-Rp&q&&s)=8Kp7!>-uIY#2thWoRZQHs2|ASUo53^qB
z8#QdRn$(6Xha47Q%}kg_FhtLHs8y*an$*!%MXaN~YN;~tS771A8dl^QhZMHdKABy?
zmBASvX5mWnY(*LHEUh>Rhqks)hK?L&p*Fn1v*5K368bQxTr3#DdgsT#rrl(3v-7Jy
z+~cg~Cth^i+sl7zKPW!E$1s1ijvZhJ<#{Gr>r*3r)w|i|hs~RV!|c(_X8SWUY%?#}
zebbp2!VSiLcZ)kR*;9Q&oUVw^nc^Rt%cVoRp4uRCPZ)Ru=z#Im!$!6Gx$?&QR}1t0
z_j#qynX}^N%4v5`c1G;{4&P&Zt$ZJQvD}?4ofGC7c2B^LoBWV-Pvx9QXCD#=*y`L-
z*27zGcUpP!zdo?xmXzaeFPDyYZYXSeDcocP`{Yv}Eo=|>$<pbW<VSZkcRrQ;Q)ir2
z?<_sTs`*uUnKeGOYFltbY;FJ0Fa6X_d^6wt@KeXu?ZJyc)x2}FJe<oGMArlDhs58$
zxUOGr3l2ALEj0F5+V^gHh~HGn?sd)^&fU)1>{h<nZnBeZLA2el`GMS#rmfD_vU|Y$
zz-+nn;76W*QcR2I%l+<C-!sL2V}B|4b9a2OspH9yJhA;u>1^wH(Yrdgj#cjytdQN8
zDV;O<=FC%jSbyK9y|?t+``qxUuR8ZN?=2i|7Wu|}!OJ|gsXCo%e?jz*Kf`j#-tg)E
z@aY@BBlF%fvid@K&-TZR&B49KF4_8+F<shYHk;X@3~P3tR;`V<JiT{dS6kc5?Kh;h
zXCY|z$(@z{O0ctXXLS%hyi{))PQ1Qg5J!>vf<OFZbR{?59qY*Rwo@C~V;Ykp+golA
zQ37r@$~&;TFCg0trRn-mxdYcvb<!0%&Q$i8XbWZHR@mT6*`MU@-5r(8QT^YdrsnaI
zRHA*dc@td?s``=Cd;>3+aY$;unN^<wj<S7HP+!Q~cgycu^7@t+9+SuN>|`2ForA$`
z<G<YBa5}i{*{#_%$%Eq?Ja0|uKzirjyAvC?m<?Z^%$+k=f9v;owa?zU3T%hdGd)9F
z&COoR_sqhLyV~BLJWx3C@qx)3spuBo_|j0f2h;z_k?Hcf*_J)V9nU6S_PWDe2djI{
zJKQxHsEL_xR(p2dd7dQ;18YUg9&>N!s^jb*&Gd;s<CQ((?Ul7*dXJGh&W{z&8L8GA
z4iwte^qI<wBd5K|pWDCjckUlJn|xu&{Y?MvGvj-_lVVM`*>;E5@?`kJ&{=l~Q{vei
zd&Mxeg_HbX^{e5u*YZ#Q<#Th`70OK5Us>I^hVQEk-tO85%)t)|b};B3X-!Qe;oAzQ
z(|`DCR;2fu<+OI<1G8{?8Xw?YL#^e>Hs1OvujRaH!a)K5-r#p!QSJ8D!4#KpgtCL-
zq?_(}cE872d!N^Fp<tfqxr=9ehwSt*^R`(W4}#lgTmP~AInx}xUxc?k_N|X*#d$M5
zc$l+oeciixF1fvJ4L=z4oK&*C&u;cU_PN4s<?`)D@3S3Y(0wvHxna2bq-;4IbPx5n
ze9tfjKhqEQ>p9Qc{ZEC$w!oge>(;&%txQa;#74}p+p#G>Qu<(<8Mf+~B-V@#!KByH
zGt@A_TfVny^-dGMCu66+Klv3L)v2<-_rm_FS56->TVL@8KK3~?34dI=yK@WFoi^u@
ze6@SX$yIHAzx^e<b%Ix!aV+0GG|&n^+S#?)%wE$xj)v38_woGT?R*WoWOtv;Ol(BY
zJanr1;3~`Q9cdFk(>u~S*<JjLfr(!~V1}}#FW3y)u;CYmMCGeP-C>Rgpx#}Tub6G&
zh3|c;OJwSE=U1hVa<_MA=j28{Sl)#3N@A=rUf{#MW=~tYR_*4E{Dr1&y!zH>w;DY|
zC(2>ibFy=C<$eYwV65Ly!p&!%D2ol|@MIRO^-8&O3_10d^Tz51?O>(n?``{F6@2i(
zc=E)LxLA|ipOo8NzSq3{{cA;j-}o43P2Il=|Ku^F+ruaUS==h@NJRd@0ngo^Z2f`o
ztnQOudXHJ?v}mAqKeBRL0FP*TuhH!74yy=m`~LNC{PSs3tl`1n^=mfnw+A~I_)30c
zf*&wXpi}3eT7t1stcB;drUn|d&3yxQ>SgS8?yJbn9tOkP>X`=v^;ZX4UK)Z=keMHG
zTfkT&qH@kK2Zt(P5BS&K=NwqwkO!}y(AKQnhw(SN2C|>$w+#*Ma&xE0yYE`VyB<5r
zCpM%Q+~z%^^)TOWKb_R~^Xd0{Ex%J3{CiIvGG{xp-wLpU0)99>Yl!hASiLQMMs`2T
z@fx0&yI>Z!nyunkLE9#~`y0=j4t$`j+=Fo+xou#;lFdA`(yT9pgJ<0dd!!p%V6DdI
zIfwI|^#_4Wm@jz(hbC`GA2N~Uk)2f>@l1xZoU!+pLC%A-m|2IYKl}3s$0Z8xYIr2?
z46YXHXtq&3v1*bjrHPFP%!WVXTI=>_;f7zGYGCaCRX1=x_z~}8*M%LEt;68ufu7+c
z-26GWcUCF~%D%gO#D$07-#)Z?+AY7gtZqr}WI!?5%&RUt&So3|eZgC^aTrHDGlSQA
zg~8h^yyeBt?vb(N>XedxAyh}56DPgg6Q+b9KW=uP{8e$gVL}Br1Gu;MnB~W?Um)Rc
zOWVLdv(MhiC-`8m2WS6dM{)48xQQLW1k7R6XM%-FUY<D4Co<wFKT|!t$~y{OYx1t)
z+lIW`XU$p5=pB*F+=f9|iF)B{En^SH%Y`qFyx@uR8~ci#I-G}e@N10YjX8!xtM!dK
z8}R#rwV}gDl0y|)Z?nKZVg|mQeAx(@IRs6%QD7YKj_-7c6{(a2HV<KY$koSK0PnBt
zEyKk*#@OJeTvV@waC3%@+`Zljo=M6nC{*=rgKimakq>8GM^`!@gC_4wQ#S`^z2}YV
zLKy$h*PLRYNy{}K>W6iL!*#ByL1(73Lp;E1dN3{5z~Qe<Jqx9{2<2KSz%79?qg)B#
zU6s6eGIW#x)-nte)6&y8S(k9&vVREnj)xO~^a>;j;<R_;@9lWHZ+`7QQ%Uw_3s@I-
zR__dgySa(8a#$OCcT23_pMAhFQ`?)cvQF1lZgIBKjg{NJt-Mus^wY}SpDG_|L)L&6
z;gdw5RJ5W_w<B+~ZjW?h-Ok`r#ibSLWw>Hfy*X^Ry|BBUl!8b<$eu!WBRqo!WJjr&
z8n}~`0)z6Ksh7(-$E7Lkn+_uF0J|_|6}x!nAN-Fy<Uf?&6RqEO<DR|Wd}-5hd1v)N
zc#m^j_EirIe!{`h|8nmugB*&+XX)<@;8w!z^z<vgjUu_zGP<ub4@Q4sKxAJr!+Q$<
zCM$74oz>xY9a3nhH*UxI@M{)0X?b97;a_otdxXH(aIxqDAb-q~K-OTnmSRPYof=Yq
zFrW^#<2f;ute-Xqd9oe{n>9Jo*9S|xq0%RdD{zv)P9$~sU9utUVzu8<QuS6H-n@f<
z?K%Z#6N<3H>txXwQUm4%9{hjBQ0ij6!9562J+0@1gusbTyu;;;;GV5l_*6g6_OxpO
zbGH5B^-~61j|{G!=gYRdzDW~PLTNCMFsBh8t!q+6kxPwE&*+^x>}EYsFsVZFSivUr
zdWZs^ui_lr^=4OjL>*BRI(!1d0p2ud)T+XkIxHtl<{b7dom9QEV@PpAU-tve><G@E
z{BLlO22H9R79G`=Y!*iz5+YD-g?UB&DK)DnZ1{JIkI`|w(SnClbg)8I-#da9by1SK
zrP^CfI7~yUuBc02RR$Oi1OX`=W=ZQT;2w^GIBhzbtl~u#H_YQ*oKV&u{ayH3O<-0O
zeRcwU<nW6-bqN={ZK8m|lKA2903Bxoj-zFG)<C;5oWVE*n>WaAFVVomEndgzEjO+x
z7I2L`xPH>9@SuXhWlDMO6Wey6wnurfz{fke78HB=w8CYPs~N6QIeQXPS0_5TQ~_=C
zprECK(C{mxGvF~NKpl{n0S3Xe47_TI6{uAUk?hx*g8Z_cQ<}!x)S-IoUte!3q1~uW
zakw?jBDQ+C18g0iX(X^kvA5!H@X&N($i6P};hYMHUJ5I73mx=E4Xji2_MWdvIJdvU
zRSuSCMGbufUJ=jZD<zE&1X?1TG2pOu+1y`#+NuP}=3GV<zPr(E<T7paPblk*>_bL2
zlw~#~>r)lggU``A;<z&Orl2E-d`he?4~Bb8-JdZ=bmmPJaOw;%5e{z>pYCy$Q8S&D
z?=r)}NHRQRmbxoll`;14v}vw(9Kq?`wZPIHzOEdUv41x*gS}bq4!FN!42BPKKM!{#
zTT!|#%r+Zc;p3HeU<Ua(a|y?vVk>q+@53IQt5rEYIvBwKD-Ve2bg1wO;6-(YA*hZE
zxNtp=fe3;mUOyjJ151|SH{yY<!41dpQn=3z5;kTDF08g84W3dZtL=b$K`ouT>wOr|
zVJ%d;?2wzG$5EAkNCe0)Kv(!Iv-J=YaATQp{#$x6#8{;2(O%vWlZq0+hX(hMrFkB*
zhf3APi*f6l12|rJqwbdAd@g~P8bTvXYE_L_RnMl6rRe|gB}?P28cqT`7(Bs3F~+j>
z)-*Y3K?m^Epgz^<b(MQCzJAiIpT#_=hmgT8rd*F5l!RvKo)X|~jtz9wDC7)G=tBnp
z>OKgdamDH>J88Var4svEt{#44_+6PZf$R3e!Cu^6Nribs4BT7rnvJ4Rt24$vo)R3V
zgVyt-?6AluhBi9eLQPusj0iS^qh&bdq-LA&{z9lcU&da56tZ{57FM3Y3x(GUy4)bE
zdxNv7^=xOoeXlc%*DJI}ysR=~C|k=Mg0HHc&}4OksIJtD?+S~W{k)j4#b|SwJLH51
zGuMZi-kFl@#jGd16@`zkgM*13cA%5Yjw@Xq#U@DGDl`$ZyuQ4jwc`^MEDSM(Bj?IS
z@gc$QniL&eFXbI*9^oK|zPFk?!^!$lr?spPb2V{NjM-Me$`$sIGg=;b2~*-3DIb;j
z!CBWU>Yu^;0~Ik)X}`}nX^gar8PDdPb^fk3m|O{?zM-DC_PgzBtE)S$_hbLL^?tb5
zY^P!9Fg8MRaDaA&T_Ie(;cW4SlAiUvA@^A)am119%wm1m>3W{H@odOt`6aif+?mfm
zTao4s#d>RHede$bsZc(I<GWjID|rMjy9E4scf#<>5JpqEGLCK*%1(QwQgeChSZ|c)
zymvF%Wao|jEFt<!LDB4iJWut`m^e&*RH*yeNKk5VSnd$^x2jy{F8G^e!(iHcHVgu-
zu-;+P^dV-z>7!2jG#8G*Cc!K#dOf>v5<3x2i?A`6;qYO$?`0jXp|$q+51;6fp1^L@
zj9b2Qr)Zr?D?wM27koPTTis4ue<=6y;u&Ed?rislX1#mf|Bh6fhporrS*cYaqSrxu
z7t5HT__toPIuMo^?hr3gfo@n%4C4myeR)JzxYZww8az?&S*&8Kkd{>rFQ}v)Doj&H
z6kXHpb*%0X-_+3(W_>WI-6XA_E04pmKgsV@S99-PM}O`+DrY+azQet#5;hbJ3vcbf
z>c)$7>kVclvuY-ZBPd0oH3pbgEQIjg&%$B80WW>PqQ)9e8(dRDA)jSu(lkt?9%3R?
zg1|I~D=X`LImr@^)GV)}+9I(F;w4emM$~H3p*<!prpyj}1?cPVgdTl_70WBIOv!4}
zaCP!$V=J$s?YFV<!z7$@?a3qMcFj^PIYisE7HWXW1cd`j4FeL1eitk(c}Bx=OB({s
zW}$^ok&cl<UN%c`D)V-|<bruYs0sNQSvln4cx9P;iC13z6Vw8sql68v7AnPpd9SG#
zG5+SPVcz5_>m3{ND`?j^mS`+z77I5B56Z--5w-_MjB-=Z6ZQ!&Y*LFI-j|Km-d(aY
z>2VusiIeJS%6b!aYkx@&z9{4^Vo)E>8%`GEq6jR~_yiE-Ay!80O8M$s=Tlv-$OY`>
z&~2-SEdbH}S&mJXrof%SPD>DiD{*!Mk~dJY+r!W|9>TT-$w2t>tvf4NEhHrPDO<y)
zES6LTZr%|LXS4t_y&bzrYYk;s90pIb&H<d1^LCU{-*K<QmuC9>J@`h|E-~N_c#cSW
zj(6eJULmUI*Ricm>T69aou2;es$Hec@B+^cep|xWe#I2)jOY02>7I_Y>z;mL_hA?T
z&TY=Y{tZo^#i`8p2gO$No9DMXPkmpM_qCM{-?Go$T-{tfU_2xD8wcGBy9_$CdD=}j
zea~=G18yNqH*bH29S~1Xi!E-)v8LnR#?=SJqx^ul+u7GY*?t=jb{5RW`wIUg7@W(e
zC4X_<R~`4bk!RI!@@erm_V7lYZ|9kO%X5&?r5V2Yk^QNACN7xS&Dkx+T6dq^oH-z#
zvwzKLZuYj=&+);%{J)BR(Q)4C*_u1Zr;V?;@&jiE&aL95C!2n*Jb2-ozb+oByyzSf
z-+Zv?rim}{eY|?ODeVgB>~Vfg^o09ac0hLS<umKP#1Gngo&JaS@zu^V>^a+g#2&Nn
z;p&zKrP}Y7^0$<_!{8aYE!^;t&W0zAnP&b}U$C_>d`#F{^;^>~mAlK&Fl?cv^S5la
zpL($HH@un`2U4XcSMB95?NSdI?fJr5XAP@P*rofL(9%qGLt!6Y@~vz-+_cVYIwt!1
zvxWR0_jK&xUvv5&II#WZiL>?v(fib2J|gyH^M!xt8EL*{wsbDrvvt>_?qv1z?)kji
z&QdRmZ^;X7>?7Y_<!;`W`ZzW@|DaJ_9qz20`H5S%uK*wI&I&xiOS^TaYi?Z;nXK^C
z!mlf-i0p`*$1vt<?&jJxaAB@alQ($Ysk^h%Ux9D>${MNpwC{Gwd3?9q0Uz~C*~oi*
zH`$K07CzfX#_r3xNqCN@zcoSrV`QcNz{zp`v%hz*(ev%hVdpEWTR)#a=Dc`Th7<YU
zxnJyMhYFL~&*ys{`_gRbSpJLY6CcOBvd@?eukgvjS61)b!~?I@oY=V9*y4TclMa1R
zE8Tq}dp1d)=Pf*a&P;y^$J6rPH{rCL-0-Dgd|RvA8?3ML(_y&D+!o*)Yy0^yUIsl_
z?Rk1LUo~BTt1jE})yMXDx4;GbndArEmSZE`kKODJeRZ<?BiL%g$-Y11FAkkISJ`-r
z_dx0+lXm*HZ{2g(M|*<X9&4IN4(<-&ufFc)$w{93UYLG#a@|=5=h2_?W9B#eUYI@Z
zo(;~gTJ?S}|M&*Az58tAF$YLCq|Q6ei4VHD+lC|@h5LdNuX6a!)7{Um!#Au_y`RZU
z*n>SdN7C9ey9T?;@Ga+u$GzPb9B0-)2VL0usM$NT)ysVk&g5GJUMHOrxs~;0R_cD%
z!8`Q3aH5pSuA$J*oOcQ*R^xr%=`DQC#?>a=%`G$OK{Wjoxesyf^Tg_jjqrmWHE$c(
z>_I1K@$8nmwuu{4y|XxK=<N#vxWiIs#C8`aXwSJF{ptIRwx&nm``zXp?>|=fo?&kB
z%4@fE4Or*NW$k5H?^zH(*ZrNHJlT78T{d&f>@IJ1^Kf0=pA|hrcH_j#6FpgU%#@82
z_G+U|%sSJp{~vpA1Kq}T--!-JV+C>5mKcxODOP1M7nk4=q&^5SDyoxBFc%l#5Q0dN
zQXD=Vzm$X^nO0=Wk`-6==Czo?1qF(bC9$lk&GSh~8kT8CjxCyXwOMbMq##F*?dZd5
zs%EpTCDVzLxQ!&MUNt9g`+h^&NlyFr?CZXsJ@1`Y_yZ(}`Mz`K-rv_>ypIdInXlH*
zRF1FN?*K42>ie?Y%-vLWm};F7WWZvXF}=g#hO-gKV}oA0p9JUhDwMBbC-n-Q3<KEx
zTsnBMY^@`~x2Ae_hRJCSt)?MfuTPSdW@#;tHf`D&rf2js+VL+m=m1I8)(hXHt}!6O
z#{ul8USY>$G~3P&d6zA%yzsKWbGL|$>eWU7FTL;a=;?UfQMK4}w$Vde&-?_M-!=M~
zKLsW?++zZ@ZqQ1fB+;Ce(k26Q8~7k-0woTXz^^yx!1;osy67YT<Fk`75aDV)Ulueb
zaNbY!u+`?7daq^nWE+nMioRVrXlJc#HGF8IXQ~sBWDtgGpvm8CA?r5fsWB3xyCBpz
z87Ct7yL_5G9XO-U><QQaDB}%kSH_5{`!Xi@hx@M@vHA}f-?2A-N(<1L@7$g0-5#Ef
zUs&j2b$wHo9<}^oK&Lx$Eu`K)0qgOUhhRt5J{-~c_k76v-k@<K`WC;ytLcL#4^8WV
zWtp0OW-q0HvF)r}>Z_m?f(I$v!A)<ZOaduu9_@My8rcXrv&?IUb2NOR+_SKrm?f|i
zEcm`2w6;}o-loEn;SIrU?WEvA{SD^1i6d!)ocUUMhKNmhG_&3@{mf-Py+^ZWsC#81
zuq7Qec4ww@$HN_0-ZhUK9l*3(@*_sKa{<!NsiO&S7-W4Q1!*FhZCgBrECMHWlSaZl
z<&<6p2k;()sMfE(2~nmV?8%R>Ik=obb1QgMK4VuuQ}Q!apatGj?|pN)ryS}PRtUOx
zv0Kvw>pNjwH_g)Lh%s#4B#~gCk4x2Uo73x9-(*+@@3oc$FXVe7WWQ7Y6V972mU~;f
z^E0`Row+~XVu{joB(vYw4e>6ZSViAIaWIq9zdmrrog_OiY#(FshUJ}N`nErHpGOb?
zkFUd3mXQoGHxO>q^E}$7i*Zu4(D;Hq<x*KLVRF)gyJCZ8MaMkw{P)3BR8v8p1ZX%;
zO;PJ$(KR}R2>9I}h5q;hwB6v+5mM@!CO1tTjEmO*juPOSUPp>MRt&5=t&6Znio9w@
z*FeP%T)yLqeZJgFAK+2+oVk2U3Sj(tk~ym5in|vc*4!n<F&1Q-c_z|BQ`)r7ZgXya
z`nNw`wa{x}NDUo+z;<M4o0EQsL><5!2SuSxpEHR763j!w$Kz6Jf<mh%kN{rqxB8t$
zRV{|8%J9IP6b<;H{MqI(y)Ob3SyAVJe81t>Hv(=lAhB_*g3pROc`XB+bRZ`+FBK1^
z@s$;Vk$MoTr2hU0lR6dX{V}44Kd&G!X1qzCXF%$q!1ba%E56kx^a9W{BqkaiF>auz
zQdGgoYz6aRjIyDQsQ9Fcrw*>u+F|d{VJx1wZ0j<xCR13z3knt$ShZXLU<Y8jkqdbR
z7L*fbnZ)_^FMPWHwVyuXfdCKa-Xp#U$XGk>(Yzj{{`8Rd6x{*vUpx&6xR!F~LBU#h
z%9k_|-ejj7*sk*l{n+-XWeW@svL+PF-jjW9@yTB7fstboTn_Zb&<7qPM3ff6Xm8Cp
zB}mZdivq!3j<H6Yj%WHx-Pty&VNV`P0$j$JAgA70;2;Qz`pbhJ6+Cywd!Ww^;CUV>
zSLv#++*N<+Q!|$LboXH8oV(uw%G|#8vJGtYUukOrE2D_*fOBxMif#Sn$6q<)9oD+V
zGPac;0YqNJWAT2~y>SOs&bfDB=Kl|_1hDcVSndsXyraSI-BZ8lqN&|^86W-dKlWbm
z{nhXM;+;h~-n=Hfh|6K-`QZvNb6R|bK799n@puxTMwnwQzEr6U@ZipZAx!J8zxU+=
zgl+~zI6_U?z2?RoQO%f18V3!`cF<EwY9r8HtWn?|(fb|58t97YMbj1xp9)aG@C}4i
zYKb`wGbu@}i(#6Igt0pLMNPIWYc<R1fP@T=`5WdlkC3wjv!yzJScWZe2{zkuKuQ4L
z#tl~nUKUp&M1x?l5t$JXE`hG`P8$G0K*q%9WL(+d;FA^)rr*-*n6g@pD9BYp-yj*y
z0UT%+lX;__%bjo=iS3r~;DW>OCM(U(XiP8SCPsJE32B>p{ja|+RSX%2Z=eTA$%!24
zHwsJ0ETT&dL#pd-#e{F84SQ9>ABh7a2IA_V1QX<z)EC0xn<=JhniAP;<Io}4#Yyos
zP}udFeF+^<HY+fV*+9`Sk>{!MfNLJitD#A=?kv=D5&?uzf9l&lj;$aiL_i%Tbm1w1
z0SnTC@30=nd>fNy+D~!71!^!qX013WLT~gt(KZ6#l$@}E$pdVzB`|G0mM{$}OCIE`
zj-w;BBmj4;72rIVU^pFDjd4JP1tsOm#rm1A{1O)TI|;~&6S85M0!;&+Q|dGjT>PCD
zL1!qD`o$(BL9XiHyfcU?xxX5k=fYatD?t0I5ps@txlWSNsL8f18C}|t>sc&AqdI}*
z_%IsAYTz3&KCTUyeb*mVp%IkTDk;jqH=O1kNY8+C8<;j5x)Vg0=4P}ZM`i#UyccHc
zPQtVRNZM4I<-%~pEHBECa@H;L1ag>g!?%LlA(YHn2K=0TG&C?+S4l;DSh3aY8#d(7
zm!R&-D#1%`d2Y~JaVg}^>5l{y$ACey;xj514a*>r9l4P@Y_r>73ZXx*IZ`X&8dX@Y
zxdHnaO%QInNktsgq|_i^<wQ;g`mF)o3Zkp$k($}LwA1$$tAQ4+y8)wy6>~ok&Atdk
znZEvFwSJ6}u<QOxd6ccEYG#rZ-I-v#3p3FtV`~e$pPbY(*0l%Ss@h^a!OeP}v#}1}
zi<<JnxBY0Lzv^2&830xsKqJ(t_#C}akqiSiC6JeXG<*S`6VSB7nH_fytH5y3f`HBd
zrQ#|e4bw>YOR{7L&?O=0MkS}9s5#~V+k8Dm3r6cmn4k~*i1(JxJ$e^Jic~GhM5PW?
zji3l{x)KT$&1lqsJ0$cBMFo1|kfp5Fn6yES`aIK2tFxpC8~`|Wzq4A8BCtW$ZQMQ3
z-8s_mfD0pl7w>8ipl#L@RIV(Mroux?XSs@P;39Kewg!H^V_gV0175l`Y*Ak!P>~JL
z9<n4HGz#L|XnS?kY~1qbAkc>)Lk2IvG6`34I1W8D9}NW*hFGwI{GeKcKDi*LxqjAk
z>|-@ul*7Kt{PMzpt2YB~%MmUaUW@y^-}H@J`pUl5YA5NXMRkm-HPN4(Rp-zZSmAr7
zNt+%q+cZa*N%&t?@{k@OITod{){FteZ%wRMAEQ_26tUJEqpjhk@W~vZS)~`K%O7q|
zI&gho5|h@}fw=}4%~xnE+O6IdgQc;!o|?4Q)7Qq#QqJLr_<TI=w=F?SGiE!6qYG!4
zxM*LXpU_HdaB{E^*EYmhsxQ*|v8XmpkBC*Kam{eA4wCYed-|GttF&o0;x>^wTM-7Q
z;tIO5enaXcP;M%a1p5+9aU$e~#uENnI&AG*&SdnoNo!1B4Yoy=oZ=BZ!euhdj}21W
z7Iw3eRu~;d){?4>XpT+}lm4d)e4e9^8dhkhEQQzTg>v2+A3My^Ed*^paZJ`c$~|kd
z<0$_z=nGek;@WH|tjd7Y3<(e{U`*qRK9P_c{jCP>=}zC908$|<Z)Z%Rx%3WKVEh%5
znJLCKgqqO|tP)mZFU6=2c(5WETA@j#2@3n=FiS@sRTblHx}<K@WVw*W?oMuHA*JpT
zEr&bk($*{G8)KO*qe2Z`G5kc2-VXnI!Izj<tBw^p>&2NFtv;(VsU9}<VmM&ukPY1H
zW{KmYXuD3KsyPYn|DpC3tq$IE$#NPMwMcKkhHwe?_KYv$-Ze~_mUnV$?}Lh1-72Jx
ziPcmpSa-v}61tBj<(ic?l{2a)7lh_I&1E^XtZ+m{7x;;xFDZ6*tvzV1x}fN+)zTEB
zio1PnwvXzP1-S!kfC4>q1ayfMa>E=rC7u<X+8B3g-0UP)4d&RQFUW4$H0#q7dFu_q
z1=lX_;F_jQSxt`RwEB{UFMS}Oril!I7LfsRVl#Lr;KCeZbw^4~#`~>828wg3B$R?&
zD9OWje>!?Mgi^RYku|4~GfcMX%p5}(5F!YLn>KxBUD<VATqM_BI^KRTrmu!ANVf|<
zQMnhIkV%7~mrBTk{jOaYl8Z2ysdSW%C+jww){E3BStP(+#Rj3#DggPr?V8ldiGt1~
z>!YgKhmOjXNOmw6lJE1sZQpHy!$7`;gK>z(mR}{-S*r4_mMVNw0#AQ#Rob+=%~aSb
z)Gz4Kyv`E`H)~22g^^hTr-p2Ua>j}5A;Y*8Omh$ym^kBxGpnA*fO|C`0ZOMIWB09t
ztK&h-9MKM_%D7?IO=&7C<|tTG#*+0_eMn)urthAY4ih1a2*x&b;3ifX43F}Dch=-h
zVYM<3`(di=^@Jj<$s{3;ux6jpcq-SXp7s$|PYiVsT<nYWz21qkR*+6l@LzvXjA;oK
z?i#1AYNY%Vg*oVsUv1yWz`pok$&+kz$iFe;LaC0didmWuEg{Yj(qsDyoY%x}z3~eM
zl{y0ononm~#`UkWbsonP590+<cOMaTkpNR_QbLDI#m59M$V9{$QzgMdGBNP%P1t^k
zIu3AsB_>JfDF}JU3V3V`Qu+jm8LJs-mcw#md%3yRJKkrY8+b}FH@YiqBjkRTBs(F`
z#v|fKhc-+L@>2AQv)OK%yOK|3wCr9etw!~ybI!Z5xKj*2YUap(BY8w09&nnkIO;xa
z&}x2kts67HqQ1~LpMQo7uQi7s&EH;5in}xIpWDw@RbR^As3$A?Vx2E(SJPL-`;p$)
zX>_7DbLCZMlC7dA`KY?Sv3tmv(di|#edi1G;^3qDO|CaRojsYsKjebBiS|N%y!_4B
zh<5rCxgsu_S6ttTJ@{7q>qbXY2aV3GJlS=+;ap?R&E$?BqA_!%amDiWV_$E5?N-Eo
zA@ze5SF^^yr$^eKsQ>Q1_*K3&+!c+^WN$upV14fsZ2gM$LtBsA$uHj8XWy#YpT5}P
zHe%9Me^A{&aJu(uhr6?_^&GjO(+7+*7fma+{QJ|U@sfE3j1T5oO<}32_|zQT`jnw!
zcZzEs8)<x}X4+e1sL1bs#(H63ue~=tO>d;v?N6SLwT>8v(kGYidF<+3q;21by1(Of
z_SoM0as%s=O&#m&_wxswXV~{hWbgJt>z%gyA9#8{J$)wF;o`KnE$=)@cQ4PCPTxDK
zHHBltTLIIb)b^-1soF)uFE7VN>Z2VrdDEs3L|WH;an(Yb7Toujy{*w(z13B%S8Zc`
z)mSxn<!^u%u3f42w)DQhPm;OgtuNQE?s$5>iDZ6IJC%Ku-+t*ozYR;m9a-@<_kRF^
z&g5L@j(i#5@*+0=GyU@5496t%j!ybJtsV|-J$PqR_%5~u%-YjEf3)D_PleAr78k^<
z7*pK8_M}4f`05?$)Xy)7d7Y=2-UZ#1nmvY8$qPGP!4}o$7u7`-Z`$Wg10gP&gqZ)7
zsM5b#ljxlcPqv-A5{Sk2yKgq+L8SCO-;rxPsk1FPv$W2Rj`jlVBLmU*pHwM=CQ0f(
z52pi|+h|V5d&K8?c(+*&R6jFv&!7D`#~OM@jM^$*1+tpHO@UuG=m+@&K(L?eDL*XC
z{d0!^*FjX8uB0ztYfFd!ynGQnS?~|zf7bdf_0P(^3*l+DFtIzklQlo4|3KVI=Y#J*
zsb446e&fw7w1{uzd*(AY<MB7O2l6dV;?4REEVxkY*|uusUiGBDsk)1Nt@nGz?iwN+
zEVcW@tvprN>nCap`k`z4=4mY6-T8N~R-#q)+}!W*YR9j&C-Bf-C~hj#7BbxXUaG2&
zgcr8WsJr#P6Zw`lCxv5xJX+oM7^#MbdnUuAr<(dQSvL<C(A8qE=;G1da$Plb$hG>?
zE!Idt?39bvd(7=AS0ADq%TSf(;y`9$Jl7uJJ6_fw)ecnYaBpQ5pNai#+&uHUY`XW4
z^`2`hNlOP#3l}|8&s00O4&*lMCUd+cvJR)Zn^z-I2%G^aQpkF<9lZH(F(i9gywdx(
zx(-Y?SPfXAt;RRSs<beA4m4Md4Z-d#RF`e*|7};=Sa<Wuv98*Vn;oAzPj4_5KE9@7
zz<`3;?WHsvi=Ww&2h^7OT_TpuA*Vq&TPN2zr75VMd!v9*J9|hpW~LrbD-~6*28K6P
z9^k<?{W?nrfwY4Dzv^7LHj@^rKMI1wDjiQp@7c^DjDM>-Kz9IWoJvo#Hgn+t-eMhc
ztmjBen<}!z%87?~9QdpWthIheK2wD*7&pX7tYS@*1teq6s0&Wdi7vLKT|YA&`Pv?3
zeYun1-p>L~UgsRKcU094!3TCidi%kAt%Z>FdN-en{D*Z=@P31$k?fz#W5>^I0o-qH
zs%=w>JtsPtuGhv1nsjCy*&I=5pP_f;p||o#8o8-0Z`7tuc^qol&FNm~mdA($_4aQ4
za`_hFhxO7FRYwB*7h0H!2Jo1EZSF!^!2O@6E%y#DX&hw^r1!Dm9x>il|Lr08|L20j
zjJ590h~u!<SWu~7tlda+Gumr6PWO6%=kYgMK2zyg*u`RAvZO-K(VbjxP*+hw-YGk;
z<Ra5!f0uSaja2ThM!J9R7wf-EtK?I9YWXz5B?*p^gJvo-qXzn>Rz{#3*Zsj{uZ{Kz
zartDpL7f{9H`H^}6U1*DCBw4i`2rTU#d@98-uz5V?JH;9$w2x$%sr`J5mgpHxSU6i
z6X3Zo$KSeklF?DHFRW#6F}a72_KpNfpCT<^sPxpJ+iwW2s*dq>fY)0{JpU%oRE_n4
z3<_83uiaog%=_LLXjudObxSt*2l|;@Bv{%lC|QDgl5n*ZtPRBN=7T$%$(peZhzL1d
zd9|8*U|at{dXgV<-M}b``14WHJNTk%_3_5(*gc*YKhU73ZUQ#(roLyqAde*}ZI6D<
zImy~{Q3ls$S>*d5v1y5w{9L`xK^$Fm96Cv|0Mw1n0I8~}w5#^L@nH2c;>;_I*7O(Y
zG}&A(UFP7kcH6zo-0#pZS(1S_f@c8lI^h{|)D+2T(yUR#d69jIh5YNb8ZTU%i3nd;
zrX?ReeW2TJom|6L426%ked#y(j^0ns*3&2)4A2`bq=ahA0Lf<~Erye7r@`DrX@-#B
zM<pK|PcQ|DeM9{?83~s@$yb}An=31EeZdoaYdd)=;AGu<E-&07d4SaB@iz1k&*e-Y
z3Bwm^19@{;W-T4g!d6iQvoMqUL*3!QVh_3=VA<nqXsv|?nM>E28+2}r5Mi`v!#%B8
z0c+rfq2SO-;a^AEDmfjt##l!)8((vjoC0kG;(?s|KYSu|T;%}C`9QpmLo7#`J;pG(
zB^NMz%KAcV*<szW#*ygaA}>NX<4icsbgR<}Lo~{Da3`u%je--PRaMFu@^V3Z<C?%T
z4{Blz<qnE*wQ?lG68a={3Q8s5&#*rG38dX(K7I@{W0Msw>{u2Za1KyKgj-#F;pWz>
z8-+Jp2cnnQ3_~oY>xXk*&K*)hq1F}>d4$1dCiM;Xnwy*PyVL>|UOqG@3WlNR_1P-M
zj{pcHEw~o5fQqkKp>xu#07y~jsd`u!X7nLh8<d)nQ0U<Y^dKhizz@o{9r9oQ^Iz*9
zUg6=W9)vxq0*yA;>U}X2&)p3K0%`j}%I<iZ7BTYr%~7Nq-5)XGpi(mPI>rW=3oNg;
z*V~sOiz5T?Y+N3MI{mVJf|A;qNeWy>@#N5pkNBSs3X(W2+a~Kb+7AMXKMRxw=jHh!
zto+hSk3cxaS>;1QyJwLCcS^U0lAc7o+pK!S0fc0%coj<-bFVIHjUO<*am2nM9K?QW
zz1?M;Ge7n(nEB5rfd3w5jyc=^lUL%#cNVKV{KIts#QaAu0J0vSRsKhR_~{1)`TFf0
zwEQ;GP{PPx0ZtlNhS?GHt%h7!LiK3iA~Af;0JbgDMmxS?YI>+@4ErD`s#?g6vFB|O
zUJ@N3_lbf1!g=a0qu9$pE0w?_8AJd>qlGp?3t<2;S!7#bT?U9U<*35T7DQXKrYnJ-
zw0l+7sBBQDp3ssD8B5b{{NP?%m^PK7p&lbuuQ*{z_%Q8DqA-_fLcE;R33I*5@rRks
z5PqO?n@DMYy`2{Yx#+a9@qt2))GJ;3#zAD8L+x$Za8p0YR;t3OKpH03yK?wlVxfE#
zeVZMz)w+2*RVD@nl(e0i2V&*IB+$M-HRBryO(1{DUa9e<^6T?UK|T;mwscwp>WEWm
z*11QZ+=UFP*%vaP^@YYtmG)aeHR^2`pw(QRlIZhP>`XU{>bzaY;@qMo!Z5M-Ch^1t
zj0uRw0D-qBry!ej_DO_H;Zu$T0enapQKE`&83&l~OMhu&qXj6N@#e{uKYE1}I6(lF
zd#?{aB_I9mr|)+@VL$y{Dk%7OSDXK%PlmCAI~0r8-F?W%eDufvoA3YWPw>SM;BV}p
z-zvx-t`EnW!72;?y?wm1^Y+g+wz!X9|Fk4+gw&4!cmmjml{s;qu!)a55?ZXP)X97!
zt$KT0*QcRE2C#jcbR}L;aI&af0Af%NNT7zCB2W8gCI~TrPs_w2=31h#g5#pG7kwVI
z0A~|O0yBp~b0={^yn_Kktl)M^m~x#zBzxQZ=?)f{Qt-h50I$JEpA~%dfC14w06`GM
zH{o0q+#K;vZ4%$}_6V$nFXW;KOk?AnrMxf>?`26;;)_4w1L{!}k`#~t;@}-JRqxk2
zdGXT^za|myP(jrwAtH0^De+{}ct`EYPyG-_D<hxgqus@VfIHCYaLUkrQhx6jNPaD>
z04iKXV%XP^a~GDzAyXfk0oH|}cA?-S=Cuk?OfIP5!d(mpXiNP1z&@<wpXv2`_ulo-
zv?hd)e75JGZC%p8?ASl`T>iiOjNxWYIJhkiGaQ%~NALAhUh}>aVx~wK-{CLbfB%%P
z{`wbCFzTP__5Ys+JbR}@yK~;^a1s8&%Oj$_j|w04W9TID^13zR{oswh!To)>pnbjJ
z@9`9bf*aotS<3|2Y4l!;i+~W3B*(y4A$^7b9P_-SY558IU3?Z&xq`8Vm;K^pIGgBx
z3kEjg{T}k6S`vb#uq84JO8}^BMJ3lSe6irG1Gb61iQfbHx8L;GD6}i@kP;yBILCV{
z2W5%ga`8Ar*iVmNhZ%^%poIN_#VaKD8;cFldoo}VykMomfBlwp?)0+79q=}dt{Ukt
zIp#g~ygfsA4uhHz^4NMjpnOmoVFHQh3LFvm6{-`?)&1<w!yJc%Go>3~vk+3Xcubvg
zO2+)96RVbt^)5WDx)RD+pALN7lqeyIy9paNs9w#?;mm~~F2Hh0$b&%ORttzE!g2Jo
z#oa9|0j;%^%;MSIiHA^?3EOkdN#hhUf9xubj^iG~d8kuJ0tP-Q1lIKc5`G2!$#4E|
zI1Q{Cl0|lofSWgs2z3y+SwPsJi&2WB7&_cHNN)Fe$M4rM$s%<Gqltp>;RJwgpprCz
z&0+S8eL_8Fl%SHOel^K$u^6K+5D8_69O{c&vb~yNKmO>MUq(E)tLEH(H`zF<RuggN
zrP&}E3q^5ViYYjV7QG}3gY*@AI07eRSbnKMgdAFGt4Qpgjlf%FvQmuWuxz=YAQDNh
z2OlC!p-av@KE=y&FgEZuZJ5|}xmi;}0M4&rFuC0Ifq~|%0K`BcmVtN^r{K!Q3Y=vm
zVJ%5)Cg3S$j4HV(<XmZZQiZy#B6pcKMx7bo>b0sKghi(}vs$J02owjB2>FHsW9mxX
zP(wMV;9#O>4u;o|sN!%4|HJZ#R!WN_=G$Pl-Z!=FRqbu_85T7rOxqxxOIuTZQ?J~*
z`779OkD;^8kf9`Mrd2@`MSV2fR56Czr8#i7DNRTmEf8%yVS>Hc=6ETNW?=$;4U~>T
zX_f>UNXSt8Y$W&yg37Z@4-FBQjG8>e%Ce11MGz7xNrn_s%mZ@W-GwFp>C**SpdCnR
zUPx7pX&7jsSu}Cj038eW8E#~bT|=W45=;2QiUf<K<KTWYl{%uRIzE&@<Ik#Sml$*6
zg&#rze<25YE9Z_=JA?@=nUw0p5dQqv_k_US`Mf5o;(8g9g9R#>2;mY)yr4+Agy(ZZ
z8ZID&#i3P>OWcw$Vep})V%0t)CKbH<gEX_8fqq36n5Nic9P$@`ziY+Gm#Cs687zd6
zd_j%dzxQh$az5fuVx|Q-QlIV&3+gkN6w=C$Y=`8=9I2CY&4``PN6MPa`?+da1#Zsk
zIEASxwW3rMi*$;JZ@5u?BicF7k{2iExj@$wTq+8q8bm&-FdOeqYENngm@#HGYCs2T
zWlL)Iv`OfVBJKqsFbA}VCTixqnlvv3?^a#aJOP@PVO7gxnrhUwqY)9rW7V~rq4Z2<
z$w6*IeMCiC9i+2-?LIx1sylGOqzZbsLXN6w|9vp293usEDud0M?k_B9u+@y=n<HdD
zl)-ek7B9&0&QGA!Se~f4XB`xr&%3jI(>&ZbVAWSy^HM!hGuJyP$Q>DDrY+77joL{P
z&|LP0RlNBJ$j@h8$mmL!#r!_Dnzfb;QJmYnI7>wUaMh3+_)68p{lK>RjMXHPcUQ07
z$XIa5x4zyIq$29qYDR9n(de^-nrtKy@1J0%kJhDmju|{@4PK$ctR3gDnAFbd1xxH!
zWBPgf(vVO}2#d0ZMPu3V-KSA=SWMV%EUbiAv_5NIUQf$7fI;)X&CI9JIq76GAr5_;
zGtQMFZ#R=QGdtkC;rL3&t&*zSaWhqRoQtltQy@cbt!{PTwCehD{cL+7?DIUR2T8$4
zs|U5&`nR7_`W)VxXZm(d>RW4U59B{lALIK;YrDCc;VQAgzN8#MsrBMKkDGKf;UA$*
z_7KD_R_Jcn*G%Hmjq%0?+zf}TUpD)>L~xmhpfOAMS4TN71cJv1ywOY$?h={P!z8JZ
zZH@u)9L1!l9U>c3XDs9_MfcPww<;YXWhzdA@~o(81te+D)hYWq7%Gt4jblhGPhmBO
ztVx;}gA*6NE@^-3WGk?}T=}{%Stjh>70i*!UcvmMv}kG-Wy2pzO{6GuhtPu2Ye#!>
zPU93kNTeccp@~Vg-yQb7_S-~7C*AD&R@(h;LMA}|Fq`pYIe0h|)jUiKKC|@_g_up%
z+%d-KMrOAbA<I!+g|_+%N^4qfGEAt18eNPVxaIV7+&Y+;)y542l2|;XR%_Qk`_+vs
zAs<$YA}7q}Ic`p+k>Jira0O2n7E;hR9FC&LB_W@!V-+|=M>i8X^E<eSbLOy*j5D)B
zdyxSrsc<Yae~2BZnQyyd!6BAE6j3aJ>{`HkPiT>Hpr$#eBP49FasXaNe}Xz1rverV
z%KOBx|7+h6I*n<4EGrQ~i?TF9lfqT=PCdP)Qem)ur$s}^yHOyHvT`#nl(s+zpg+7<
zF_WXDlld#PplVc<!koFE2bE+%HX20_6ncT0KHTOd?u7%yq86Rg>ew+jX9dS+2_@U%
z7Z6i8i00sUA~qv6*YeN8912C2(^~SEt#H}+9e(2*tuJcxn)+I!Y!qS9%^8(RE#zB!
zO$<0l?F;1rHX0CEP{Rn!>pAR29XI6!H&cGJ<$|1=8bG{a0#z2o(pFyxCmmufDuvQ9
z+bi^7GBYjXNiQ+Rq`^8rLNgWH?k}gQQZLHK?ef`Bm3EcO@#vI#z%`zXM~|81&lay&
z)!<FqyWaRpGP2e#&hKcT>*;-u@w3ZMze`WrHwU%vH9o90v_^Km^V-6ddA(zDgt4Y)
zHuOEexyk(=?Sfja@@Mv*48Kk6(>J611hg^FbTof~vme`9cWIC9MsoA@XU$L9#W8(X
z@fPCiMtb8-C2@{4p3I$8*X}V^U455cA?<_vBZtVlMy>VX<>%;xmHcB`ZU2$6T`U^e
zj5mAF5$A)=X7RB-r=km`J)fN3eAS&v@7X)q*l|4hmblSJtnc5%GrsqAYyYb5XGitq
zoc6<~|1{f_WDWH7VuSg_C)ZD`y!6^*>}&Q#_nn1*!>`u97P*p*-TGkWs|(`Cd3~gM
zPQCTNu1MspAF}So-0AN%?I)qD&dpe6f5(qVkNrTYOC4#<jWoW_id#>wjkTW1%_o1K
zgr^7Fc=&y)c0^ipMm>3S-$K>Bk0c*kdGmhKU5fQR@XVXN>JPQx9($VR(~%k7U85Jb
zzq_8Uoow&R?CHH)jlmd4S#JY-y>V6U3Z16(v4?ZvWbD2d@;x+pL|c_>{GcJX9Yq<R
zG@Hm{SLZ)*-!qND52C%S+i15N<p#!fRR=mAvA<PC?Z*A=b@suu$n)W<=s1!5{*J(A
z`*kPzeLHeu>~%dlqmQj?IFS5FMtoJhc=M~951DGdyGtwnxO(Yrt1ki=9{O(J<PrVy
z&vEC@L!Pwz|HAdP$epW=lZ(_jQ2c+yxl=IbCE+Q-%{yFu#skSO17Sx`xCr}yxV@jZ
znV|y0&u{MzGQY^uf9KAE4|#k67NmC~)IjoIwvVNu4)C&0ye-ann><@vznE}xhphk6
zhxjuh0~a;h>roBz?|)|r%vT_s-$WIGZ<Q~W2Pi1#@E<%JX#lUfY3gD2_<zxZ9W~gh
zb{~S$p$pkk=ggkTRq3yy0zuD?7B)g!VI2c66+FUPwmBPgtL3+`<iTCrZ>gvjSxL|A
z*=D56)9Rm>FPJlts@mP$<379)oz`!pvn_n&9z8w9M~pLl*ziGfLqijun}G+@tL~j>
z%RjswVNKXNp7cd)2M@mV<P~v?2&4%0d^6mxcNksv;BZf^6Qw9eHLz<VfzM8D{jT=3
z@!l!-x!tWsKGTv^*Vn$fu<m4KH@n8B)_nQs3vZmjMuS(bA;;_7@UykYKlrsD^;_GH
zg1NrAykSMUWqXtzm{EU2PhE^?F}?cvNXwp)fCFdA9{p7I7BbJ4JX38+gRN`S$U6oq
zBs><sy}Th)1#SOE<ICzov4<yTST*2~$K_gdvhARr{xQhU$-uMKJbY0d)fTG1$f~(R
z&Xp^>)6`XOvGk5-j8wY187{u{WCsja&iFn1Cni9-%?H!v<8WI&eS*j9Cbz@ecZFjn
zVDC9p+%z@b1BcPB%!x;XfuD$K?2vOqh;LHR-xsFFa?y9pD<`VkgD;8yh3?p+-`1b(
zu%ow{UtX>87V7K-Wt>@X*&uC6fxbP_JjR@Aat6X2*tcl#>O@bau^O)LbBWpEbXR8x
zoku0r?ZvM<tz)?4NO)`cZ8P;UtKRFJF=zJBo{AZ-Sl3u&z(75wiNJp9S!0@L%l47*
znaBCdY!obHzPfirO+B0s8;FtL(|{2TJFGW;imaPc4^isAb0sh&CIa9_*P7=X&m*<*
zjZ}5(NO-88d_mtQelqlG=9z%?Re?yeZu>j@IgqRDx$V(+uHCM|)%4QX7299B{iJxJ
z7X9F_{;IHhs7m3nI?1Y$I(;Vh8~T|%57u;KWEBIZcUhix-QM!kU&~eR(NE*kdG*EI
zE!})m?_x%@cMA0IbbM1eEYR4>+h_I^d+aC@!LD!T=S^Q!us!J$>EP-5RkWQ97f+^V
za=qo$mh`$mhu-7?4!<G-y4G&woi2O4>n5WJlxsq|R`{H8!{(tShgn7aB40Y}mE`#B
zNG#jO&zF1N*u`e{R0FkS8If(bIE`+dSYg}Im&EOFrkjr&;6LD}FLyS6@ayN!Q(u^D
zYTdxXM@{7OwWLPEscBy2xRg`tdCN9Xx}T)Mdv5ct!Y1?SQ@Kgw++1Lq91pkpTDC((
zVIv3b5*$ts@#t8*^hJJD)#tX)#GVS2mLXIPnSE)><Q<U<Q#Z2NmVDwW4sw6->qZl_
zBW4MgQ=Kt4RhxMDF6;C89Zg7g*`rTqYG|(d1oRs8M>QpQ&kPqI!2Y=t*KvecP__KA
zxw~?aSFPfWa%I(acd3<qZVl8GKgs9Uy=4wmQFx=fdEb0Bz0Uo2qH?u(u>v_w8s%y`
z1_sPS4vVu)m58SN7Q&9Q7j@sZY4u)I1bS5O&6=?~zxnlv79Osmn8J>BlhYO=QundJ
zlI?mackktfU>jT(y;$y<+6Ezh8_UhA)p3YprgIRAWUKi@uH41Y%Y2!&1XRB5crQ++
z9ibOY%RLSw9qN#f`rb%}$hfzs<LX)742$Omz9qG<ymX823HQO{dvVP((R)sbR~DWl
z!zVM4*W4UCdT!8M8ayjnA_vV9Ond+Prj0cJVmzj$VmZn7Ho`l23lCcBc<>MPxp6~W
zfpq;D&!u_h;x}dphB__0{+ON~C6(SOs8`0~R^u3|hVJF<Og&>lkfB$*ncHg?Y2@P6
z?ygDRKR{RO8<sbF5`)s`A}tYg6=r&^nwZQ7-*GGoG0{{m3IWnnl%N&MvszOg&Fgev
zjBVu545&kQZwZ*Eazl}x%2z3jr>U7dbPPT2pq~9ZG1NlW$=&uVxoYf9{eXG%^tU&{
z!tFY9EG&FBBhDwq$H2_@@CPxj18c8lmu(cC)pXQCrZI1>QoU{nX)DDgr3LyjLr0J!
z1uuj1Yz61`3cALcVT!rVc7%G>Ed0;er6G{xFr1LS&*wrtIXnuj%emGe-}8)-8be`R
ziiMnlZ={@ZmXueSPZ&LRiyfNd$yRw4H<e1f0tt1p;s$halO&P&A;b3uSO~dqz@7x^
zlY;f}82Lpw*C<$=F#UeSHCYlWPpFBEf`_UEi9o6hK>_~rQ8RJB7EcJ5`atJXQ`+ed
zwXuSAKLMnLi3iw8tlhD?gpM^xZnh%7;Xe!t-jfp)lvVdEJ9>Wv%smWb-jmsRh{ZjV
zc`}oP+0S#LZ71S+wwR;l5$pALp83v)gAAzra9SR$!e6q&i$-%c<aQW=V_-DP7*iM*
zm}g$YI=v<PNQUIBZ7{O+*jQq%e?>Awd=D}B;XKk`JkOJ!Rv?2#tovK>U8hrc`{iY}
zA>Xa4owqO7SKHO$%Y;M%r-nS80A$nkmvf67`MO8=H&mWrxKM|zxacx|>s9$*82|s-
zjK2ls5v_OeRRCmVEdHJV=mLZeuYiYdV>bE^Uf!$<v;CiY;Wt;hUV37-I$n>E6o$B!
z9gb6!=M0dkaFbd3b{LOZX>m!RD3}cVBI#_NZ&a*VjSG>DA%aPTWtLDUULQwTdx=jn
z@}ROI2-ucwv~!2poX+bmi#8qLE7$8$l28mxQqb(CWHtVhWF5ALmypIUvb<4KQKzg{
zAn>UUnOd3bHfw}R>l-D0Hn8fCeu=Nvt*21$NO_w1O{3;Gq7EANrvgixm$2|wt4?N4
zv(HAd)1@I`>ve`|@1w+*R@BPJ>dG-4h^2FQkV>L|;6C{^<+Zux(j$7_nPpYPOhIf=
zu!4Tcf`%P4T)^7N9zjw$ZZs}yT?1dV>7vNfsOw}fD>`qg{;)4m?NooGHza3(&eu&D
z(Ib5m(m+Ix)F3@ioTVb_SkRTNm7AH`4q^O0xBz5ss`YuR9{_#SG33s73?_`+B$9Ys
z<0v|DN8;lQy<1{gzw057`mAjsjcHbO=qwdshwSd7c@ZhIoI`+;8>^{gM-=rnA_9IB
zm5O}Z)6`eE`OUBgh5`#UQBc$(H64X11&N?SPYYdTTr~(&fQNW(0G9*UIYwk5ACk{j
zle!wF*YM}Tf)?^+4B*-ZL|9TpRx!8E8HKXk2*-jr49G9EnHG>Ahd7~fsK<;IXwEJG
zPm<1yUzW&0m`jYqkrTv+19bA_Fcl$-631|qP!eBiH4ICxTEIvZXBEY+2#)rP${HZ#
zNt+!;bsl4uyObAnUe3E{EES&v)I1~yJsYH(;8U6l5K|YA2xMuFYj6$nQ8Q_k?<FOL
zu+T#IV<BS{Ve5|&Y?kzbSLs}E2s*ohif2oBTbPj9c3Lk>C}3X4g0zS|Hzzazyu#|0
zz)SG#QYuxbrW}T)4_aA&xz5ZFfj%iZsvJVxyy24afZ7B+*Rn*$XU`dqE|nBy`&XUN
zoZV{7bJ0~_Xmt%)+V#?1tgysnG;@{Bz^VwND2jtOp10?~=Y#^bE0!eolAkc52Uq%>
zs8hN~l;Qw;$V^@|eU>xp1^8I?`!s!;p!~S4ia<MmQ6qn#f4`R=%3rLKD;zz)JJ;JE
zuBfl{^$MpfxmM^m2#;J8wdi`c*+p*Hv(NTzV7cUzX148dc7AfKyr*(?FxQdv)td*3
zlNasbk4>6Rk?NBGj?((|$G%+Pj&Ix=XB;GzFi1j)9`WpG1s_m%8+JDe5X+RpFb|fM
zS%BT(A)E=^*WhJ@67MHccs@GIGT?I-sE_wW{AEcB5gF|gs7=9?VO_D&Oi6UASA~$G
z->@_D<_MK=OD!3v`gQf+NV61un{6M?5F=|$SW=_EAfp-#_y#JZFtG;R&OnYx5XRJ|
zJl_%;bz&**1buY`;ABl7(O&a0*yr?68=yi5l%OoQK)m2|S8@tfcg*5&vP%2iekk<H
zedtDK%fuv70ajBZ1Tn@d-zpFvejpmEq4}s(L<<J1CQ0WhRVUFVfg_@qty5)C0+2Zp
z{Okt^WdRH%d;!_3&;x1ULMjZYNv_FQVrin67Iv#jvzw=H+saOtDB;b52+QKL?FHXi
zgj9xdqF@T4amDWbSH4C78_tB)s64GLaKbVk<ETQ%CqjE;5hD;&)5q-KQc^cKSCO5h
zY?jzDvo<_%M%{8zD9IihIzKiLlb)Kach<K%p|;J&oY6d!zRE`#>dQXG^_t#!goHQS
zbNY+6Z#dRF800anxH~A;xXm|$yj;?j83&Z=QSF#pM4*A%dhKjraJX(=S)?xG7U!)4
zwrBz=xb^pg_RuHIL;IKL;Wz>C?4-fx;hZ85q$%%|#F9GM!AMJ5sq&V_6`T=L;2Hww
zs(1>GFc2mJ!2@RrvTfD!J#xZzhm?dI*_YeL#?&E&Rsuw>`1Rx1DEvTjfy?wottw~-
z68`55vRZw_oUf_P<tpnaXJt~Da?~<v->hck$W^Pnle>jwTK3fMeSB66De=%KH&*C}
z!ATbQSyOVzL~GLTY=_B|IU#7hq%Ih~xLj0*eZ`tKXIhq;Pm*@?G&l1u3vCt=d7~f}
z&u^q@j%OA#OnglI>0G4fY&KhwpFggnLQ#%n9I-$|D|wPt7KkH6#kd%)hyhkP&0IT3
z=SizEL$tHZmiANA(e3|OlQYv~3=x-Zub4H#H`a-1P2PaO<Ip|d&_YWq{FKUS6q>VE
zHrdXbxNT+|^HvMBTQuA}HVL^#u2IL$)TQ#~?arP~s+@NzO_$-4dSJLyVX9FaWaZFq
zI%ru&oq02gN4Z?Kva&fv>MoIEG@eir3d{Q7!_CaM&oX`7J<NE&Wvw@pcxJH|44)O6
zi%J%QS<C?c#!)#Kcejr<o+XJ%Bb0Py^I7n)%qmQCUs^b_Ss69q=O!h>!Iq*1OPwE`
ziIe1D_M|QyoqpZYanS1wUPn_Jl5vw6%#{)_>21bIz|>VLBer?iXL0GbMm}yJ4rs$5
zuxppb?BOCGwe@CAz^kr^)~nob9LksVQ*>QvB)J;=?Ucu>Czin^j2OXXc-rXdL}G!7
zrzj<G&*MO8zvCR2t<XI%VxuQ<%~>G@mDQ-!BNwu?JkZKTr@tn-DoHECCPRYf4`vN2
zhiX~(k3Rd$jHXm2p=zjUDu;Yw8Ml7a@tH=|d#Hr9h_ZTlsMkeDnqoPF_6y|l1?6T1
zV-4#Hp40OTEHXb8rS3G((K^L)I%DNTTu99rKbT=oj}g&rl+9_7bLt8+S&4BIvnta%
zRm(Y{BeYKVi$^H9<G59jNm86FPXx&$*W?41R<5a84!PMIh6d_H1*1KHvu)AXBN&kQ
z)hrkc9Ah0-wXrzqH#SnvOG<W0go^-QuHa#)RgGq*@%B77B3V90T*+D;IV{juT4te5
z%beDSt+I7&QsQ_*RM;qGoouw)rN)b!-R9v5T3Omqj+0jIuME3B-8`{m+@%Fpw*F#a
z3DNCl=PDT(O6!AE$5W;L7(2u*l-giwzf&+=rHLS#U>CWo=%cMi^u()3qIK+wVZFhH
zR1gZ7e?-&b`4V!+yt+PUga&K3IX#FXyXFuYN0u#zPGE(4JTBDn0k^5l-61+?zuie4
z82{XYlM!b%Vjqy5aZ0lj!W=Dp^6cSi#=P~;4<4Dn8Xo)N_pc)8jXp!?n#juRGfjGF
z6a(X*)RXk3>bLCO?Xa@V1&gsQk?4Q1V-2}C$s4sjUyp46?)HJkwKuis>uUI|2ns5h
z4+FmJo|taGg~@-{@@_$v41a=V0}GJ>t0nn*`v}XmsGp;|A`^y{yv6Dx)3j!9<(F1|
zU`MuJ6gN3({UM`c?7@@j^vYA}o^q|y`S0|LLu)qg4{sUWVjk@MU2$;jhVm{WHuFub
zDYdHhX!!%}2kRSG<enhkB*&iLb8u$Y)CXnt%b9Q7;8U;1yN$oGZfj=ezkl-PIu<-O
z*j=5EW-gN2@$S~s3%gntc#N;zn|t|<r>w4O_m^%>2hT_H;mEc8MRTSvmffFDpEBFy
zIU{Yhbsh9#@Ql;#?a8;Q^6>8ZeffE{`0|#U*%<Qgr}^%^S91$S&RBTu3;BI$XZcsV
zowb`EaP+3R`@{l23HKMhZ0DTQ?aS-8h{Dy$fioL=gO9cE+Z*Gn!nd+yIL4!!qv^-<
zw^?iY10L&mc7I+R${Rgwq`7<Onmw---^pDmUEGm(UWhn1qiV<TgZ1mxhhi&-)*p>7
z&`06WyE2d`L*FGk2Uc!*Z+A7<eBg@xiL)I~Y}=zNDCzR}=yMHgZ|UseVDP3&UXA?j
zp2uFfYPIiO`Rc*%b`Q@i?2gZf@19-SAU?w3Ba1jZe%o4fRxsf35ZV9KrPmkz#{m8c
zFN9_h0Pq+Ca6M~3a_KD=LHUSjScE$~+<sv0``-UO#31ML#s7Ocei}Q7ePGb!?=mOr
z#X+$ihCb){^v^cfQ2Cx|e(2HrX;cfzdX_ye8GV&!@I!=+@c4!g7k~DZ8b*+wXYs>`
z7caO5nt$L9p2rWRQT`;gk;A4!hBvh~zP#sU^I{f}St?3$Jeyk;xS_`p^hR6O?4Ri1
z1dp7?$4M2~-tNq`^j8CiuH3M@T5`jCw8z*wQtT1wmt#Yyj+}1^!|wNAxAV^hf=kxt
zAAi>v;Mr;QW8Djz)4@l@ZQEWc&gU<<2)Nszt`gN8iUYu}w^h8Uui|vl_{?^)3SCp_
ztcZTb?5G?c+q3cN3LZOGZnLu|V%^5?3{_(0fxqM5j3Qp{+=IV5+4#2ko6Hzd?>&`6
z${l;};aAiPQzvWJGU#(APR^go54|tc@B$pbN54hr%kdjxtoyxcWPh={bAYeARm#6T
zaDy|zsqUt!tuq8`wI1L&2!fQUEpz(9s@%)H7t3C$*sT*!-^}Hs>}nO5-MN9DS6g!N
z4kI%|t`;v0wx#V#Z?-E<bOcGMzyrJJmhU=No(1L7%N(XZrzL{2GQlpJL^tJE<!5p=
zlds^>QIl?9%_O;<8XK#-qLaJDA$zJ!N<Z%E8o#HW#mKs3?+?Q6JA?Zey=Cg%gPoI+
z)gu46@xE|}rdjHCrLuAe)e;Vs%kGtllkO+Iq9<KIjRId*S8+6~Zrf-@X4Y%p&z{Kr
z(NQ_yEM|1|$#e^MQh&;4$XFbhxep$vX?3lBrqzANut3~hFn6<4xk&F|dYZrq$h?v!
zy;Y-S`^GoA($P6U{<QgB_`ACK<QlzHCF=%^{nZv04O}j_d-YcIq*$7Cs=2zo>B;S8
zX$NoFu0G+iSv~db^mMPaPkd6W3tXO8kb$U+jCe`w%fo9r^jNx`d@BCs`mUjtoY`$&
zqp$2i%-#WWruSWEqWsNjOMck7W*^wCpK@>4C^GXf9S{G-!((jSMgBWApp!Q$T3XyR
zzIZ-A(Ap9y_FmhNMus5(#F^YlBv@-#ou2Bd$V_a=V`u;)2Oi&!d^I+;{SoaiakA8%
zhWC}JU34ZVdhHGAxbAp-mR@_9=0s@<Nyt4lBVLNz;Yp)%fzilYd83*x`5yw`6zMyg
znr0|;vmz~3SDB-+M=E_7L47ZevMN303ROy9g&!_>W#Dq;M1H?x8RNuFRe!~N(R~v3
zxhDjCo}Vqn#rmnB)8_u*ITZK+gR$=Yu^}&ujZXaA4LlPw)vi=-)dO-WPjkZ;=>;lA
z%^Fq$Tpe!F0Vnn2NV)|eF9Pe<z2o$_yVBKr8r0I)*zq;zt{^p%puvL8AxK6125U(Z
za0V}vKhdrG(qYG{a`dzz`0#4D4@+n5FqvL{#Lh%ektn^^E8>x!Oqc9GO;^+B7Y3<;
zFgLh&)qNuFU5VWpyn%<o8Q87;*K&od`~9(9JFB@7WaX{OPo>GwS~QP7df*h|@jA|S
zeYfQ^NJQM3iNojhHw)`f)(D=xs?pIoQp>G7DZan+L}X;m`d?lDM(%~lk9Amv-4O4b
z<5AvsqB}npi}sXPuolfJ)gSM`kZZTDUgQy<N8-es##7{YOtr~*jw2GOOZlq0v5I?)
z_LMi!b)$Mor`F?{%`BR{ZNs8xj-#T8&oC>9sCD7?I|?xRkgY2lr^a`SgO%r|)Y6s%
zQt39cTll(Z(en*h^Rm17G+8L#ERUYGqZjkn=qWHMF`(8JU+H#UZ21G-`D)b^#y85n
zCT(^%@ps1v>9CWnSDlx{uU5&YA6(i!up6k_@cYYyU1@Z{GDq%Y^6o892U6sC6ReCB
z31^RNr$y@&qsd8-FG1Xf;dvN4tBjnvA32=*8TEK-qhKhQ{z-^0)8$FxWM*>827OyO
zVqgzhl~7m)6ZhqfXmSr|rMkUhntZ05oSF>wm=ASzx+seE91p&)9pi@HZT01H#rG?^
z6(+rTG`;=K{=ss~=0_?EY2+Ual#eSXoEokaItZ{Rc+i@WckJ(*W;NDP-XN~u+M8Iu
zbR)Nrwk`~x*3A02wF9-4m#UK5pl8d%IFcP#YX!1L>!Z1qI&T%0KUHM5!V+UFG(bCD
z7~Pgd+q5|r9GIX+qTMSAa-LT6<jm$+W~pOlEdA8+h&%yE^59TmU|_!qliPA2-TnB1
zCTY9wG)~aOKJHrO+e2I*hi^#DnsV9LL2`3ak?2bI-vgoWbebRw9Ip&ZzjK&*f$Xya
z^BzVP3ZUbG{)ODdusj7b_7+TJQEsK+v!x9>3on((N*p266BATwhR2X4fM0ZpkQ|b$
zw&@Hh1p`$hMLWjvlLjWECTu27_5_nqh_lR4+4K6h{~BR>B=36T1~0=7!+`KTmt$3m
z=RX7kzD4GsaoWRwF7H@G=-+i+&@f8G_LKt1)5Dv#R>vakh{?-mJR<hP@dC_~uYv%W
zy8=jG4D@?r45sr9Xw(>CBt0`?hnd3w<MSwdeF5nKSnu;g8TZQEz9(dqPuVBngDu`z
z3<BW0Fjk0VZ@V5nk-aS#TU<^*{0+zvj0-tGh86n`ET-#qn7C9Uj%OBJ^%wqsp$`6M
zQwNwK{q*IbdEP{O@fBLcggtNz;qU;pK71AMF&ssUuMfW*`slCMZ~y0lKG{BO-5uI%
zYFWQw09ml05A|hp4uK|)Jf-HyMriYxY=j)<j~qi+mr#&OA5ru~d7>RQJwkoM$VHM8
zY*08>XV`+IFn)~SR`J1mZK?%V#*`M&(WoT>O@wLpFqc%}uIvp?8J)(`7TRh|xVWc;
zMen`wAI^o;Tu}v3IMylwM7Qe)X@vO9CPykPc`7Fml_g13(u2$|9Klg<0&!vzq|?}l
zpgxC4bxKpC7*-C)kqeeM>*AQ9=mTsGz`+70fq;6+&I}Y02X`1UXT>d)nNsgwr3QdP
zq!`(cfc0xnId!To*92*dqv+*oB1KF98?6?!l!1#8xj>H)SRy51RZY^sLUO_#LqQrH
z5p}?e4F@Ov`F4q`Z%<lWC<z96T*6<sT=<3|qz6zSfI|+>xqVV0=N8D4^9%uj>j#>R
z;b$pf7KwhG7RZn<Xy5wRn*cBXsy3x4U_<X8TumI(fBR)Y>xkpTzc@FG|D=_W5&}F!
z6$_w{g&$d+0j$NR)hT>e$(Jw#18jvY{i?xoBKvWzl_=fFJ(Zf<g*H6eD`j<mgO$Cz
zk(q%j?6RvI4iK6?JC>Lu?7BeY*<qHnkC@GO%?jtbiZ5b){~X^_X2*)Ymc{k?R*Dt&
z_5WHzrhnl0C0BXTG3MQL`QzG7qTLb!Q(9ps`}Fhfz2&P+_pb`ns@^xfg}j3z!nQ9A
zhVT8^H-|^rcmRj>55Jic<=Mbaa_@rf$f-+iyD0tKarvV^I{}H@(5b{+gjwDA=J^l5
z=<RTzO}+naJ3Sb9+dEU|rhnnTeWCt|e_1pSg{(4_>--z-=9FwPU?qwG<QDKVxL@u9
zQQl<uf}BuCsYf{kU5d6buer6ekWi#qA|;f<{E#bgG>rt<AsOC5s}3a)aBnHNN0GS(
zQb^(l6e<-ofA{vg3bF}H1h2RTlCGc?SWO8LP*B<g;Ylh1lpdA~Sb>BZH`oyFEP#F_
z<eSwjG*gDwCW*OvB6AQ+j*k)VZ%JT1e#ogk!$^V{eiy902HJky0R9L-zMt7Iy!DF(
zxd3@?R&mHiQ(dq-iBe$xK0RG_l)@754y#FDNU_J;5v{m7qq2nQU|G^EWV7I7@Mg#$
zPY6atc6riu(M=Q$csjv`;V4^u{4ky65^&4aBBUw>U&>vEt#fz_3d$Sqt?Ca~6VH50
zQCLT~KCDzXf~q~_drd8CwyiXwBh#&fa7NRPWRS!+Y*O$IkLrjoaF1Y!5xSC|(}S^G
zfjCE~=%RIJ+eN`z))dCb!|5nHb;q>ADB``I4U-r{p|^=l%(jSbHo2jbef~mijEoz}
zK_;Dj%3az;Bd!w@&6Fx;;`X{9W1mcf8*=y}(EHD7xEe@G0H1;!0}Nhhr@%A8mqwu{
zQEa1<fNY}Emo+SRsfl33PJCx$RVwIm0@Pta78J%-S$fXkUJ_nW)?JSt@z#`aCtVcX
z@-`<O{RMbJ(COlZOI-+fmjYa$#BsesvH(+=Kp`r0PD&iDAjHeq1&p_Z>4bb<^&xPK
zK5l?j4Uu`YESY#~s*~+P3~XpwPN@Dm#aMh~{r#W+656x`VnGJQBqzZbV6&{~Ym~F-
z#n69Y!Mm|3YzKWgo-ii%!6J2KA$J%y&}IWgv24GP07YX>MS{-G!iZ6N5ny=MAA%R6
z(7FVhaBYU5)Y}UiLQ1QmHwn=+Pf?UcMuNMkCr{eG&NW&zKsMzDVVIx@GaJg$RQagZ
zVsyH$yTIm{#S^2{v^rd*PZKLX_$FZQ724r_O}w7bOI7f;mCd$UiUi93RYtA0+FbXZ
zbrs=a(&t>j`kP6-)!EF3v*KOD-m6}6EA!=YGXUn%<SAD}nQM1o>#2$pWnfFt^$P>`
z8^-Xr@SOcfYq$J_DssfM4<iOdYK7wlKJ?|bKO1<(Y}aXVX{nvlPM?K2!(4SgPsxqt
zC8C-z>CxUAeA8J1I>*&)|FG{x5|As(YWuLwnsRR_YLjJ);bo6#$ISEQr1ctDnyS_4
zA_4uFUDwK%;gFL#VTtki)Bh)XZy(*pb=ZjxMzDgoN=uB!=oD31%*7=%1VKrJ7zNAb
zcrh0j;1GmFkyczD)z2j%h=yg^vS`K8^Yh7K1_KflK~Z8@m(6ip5rS#jmJ>^1v|4XA
z6)8xjW4W>vH>=l|vuiPoqkPpCt-6Xg+rA%Uw{^C=`~KN~-a8K`C$va>4({B0=l5x1
zwe`A4@wkIXLvtQ#63tP^`O(Z@=$}5uH062fhNL|;88*%W*fqjJbczWjv2vD`$Rsfc
zD~TFn?BtMK8g5}R_grc%GCK8IoTZ)=(es*^r2Zk$t$J*&{1)Z5sKXCHiUG-$5mKND
z%8YlcKAS)rT6mpmyv-e|uvoCML+9p+HGAz$gApiG0`YljZCNj5Z1Q{G$~i*t1x?%j
zll*8~!m#hy7$0PFNq2%@CoOyfG80v4J&!cZ%6)MSj74L{4%rK|PDz8sY+!d1(=-~c
zXr??xMpall?2dlgBOxi24bw-nU{WVaMPXhVsz5HGJv=*6Dty7RHc4BhAsOe_DdtX7
zeH$U8GJQ%sX0)SvaV_}+rDIC!mEwShe2!<xRKM@wO)>inwZ8UwABMj<#^CD~VZ@-D
zG@=Jw+bN-DkK#e-o)PghOJ|8*%P52rgYh`3k~4ZzcWUR-OfY%g#3af_FpKl^J;vFP
z8SrS`<mD;x-cw3z>KGlF4|#S_l<`fFo({6tTEKai4_DKNscDRuIDDp%P7*2?EfYGD
zQ;hVHq((V)Vk#-#Z2gZQdsTZCBuk_WO+>4N`j+jQjj5=@lHIl+dj(lB_z}ryR^Z>E
zf=T<-sOy+yz#w2m$+RxTsKdyl7%5Q9+^Z!U{eM1J5pzUlgN<#ADZWfibp3!97UpZs
zd}VBGEJmZ2lUu}hNYpItz3=bGmdnJXw5!#y<6^-{4Udy=l8J|=S)Z+G912dTR|0f5
z7vd3FN+Sc9C}!LxfZ1}KB~c@TEhQ!}>J;olcd#g(#scOu9k87GwEgg#hL*W&*E*NL
z3FduH70nT)pB9RO)Mrr5*Fo0^(VKHWIo8}rClqjaddV?@Il@q@eO8*(s*teww0eCp
zSMsQ&`Q0xt%&`qwI1toUM5w9Y@YjaZ2~crT3B#J_oIcWOAgNmO_Gl{=JLd+Ym6~7d
zFp4*j2W;nxYKIuQHfBvL&6A^aq?JCuBlwIl5-yGuZPP*`kd~WOSw7#e%Bzs#k8~F^
zrWASKSMCs0g2s7X#0KC9>%f}0>MWu_VxpAx!zB}Skt2q$s$pykwn;HV7Gt8o1eBJk
zg!sa;PpoSN-kEdZC54y>Zif!Q1v5fP3#oI({HyB-d|igE<CNfU^N5s=^2h|^HjNS|
zYg9$goMc_MoYt3b(!*)*&8#%?cZRfcFgwVTZ3kZ^k9fMQ{k^T*_Eq-Zw?dVz%8Tf^
z3C)L^d%CR4*>?i!m%?X~^Bd;Jbr>q-0d{X|{WoF<TCZjwrxT&|<@yczlN-L3I+t2s
z>9}mK3@EP#Jd5kvt#cDv^WOF{%ngydlZmO&xrKr8*yO;#sU3sc!hEaI*&q0J=m7h2
z7K}&m)>Fpe`yObxIDg;h&coT@*XZj~>HWY&>2%;1<%&GA<e!sI)4vM+eW~a0fi87#
za-aEg^~tBLKe8^7Np1a)>$UoK+Q-JKUG^=7cNLe+Gl4&w=v2n+QKhN(%-*LL*-q;+
z{jYRFYnpthxpO$R`Sh*Vo;lF2JfqV#dnN7Nb0aI=Z4A?PlAu3^tSb0LX+<_(+aHKL
z*=}x7I#o~W=ab*OFCBOzUHYt%Y(cG9;UWFrOn>;28u+(+uc`86;@PzSjr7G+=xXw^
zm*q+267&JF&5?5xDSeE^K6~&HDIc!C$XlP-bs(J%yiOld&;5|2{U}3U_1{ke2j%c$
z{?E8Jysb3r)rVPWC1q{ZhPC$NqpdIM!~S-)Jvgd1eEZ(3^hccsD%sthSMK|3?Evk`
zj;p7%`I+IyZFc@G<K(*Z`Pfgn_L>~KrcF0~|Ebb*>Z5~$oNP`9Blg$j`sFV5gtXL2
zV=Hp%SdE5R0v3iJ|H6~;&(zG-k8%({uJHNAZP8?nR`~=s6Zix-^9fSt*B|-DuRXHk
zpV^?AALDj}VrTX?!BSIoUfuH%!BXoDsuj-G9$R0#-)(}W#?1WVJHBe18KN2RGF>%O
z$H(+c^TKUc2R>NsVH@$V-~E`M0Z(ApTpizOin131<5ujabS?~bW*Oz@O}`DI;wKve
zaAnkM=a(`wpRKf4NmIIB8r#-1;C;U&C6?HR<L*n#6*9WE<1#e=6I$2&jRbn=$53Gu
zn+w0MX@BwpoEd+sL<(u%v}=5NKM$QE$eioqHxvB5NpJopS&qbiP^l#HkI6T=(UbsC
zDaR}Qqhw5upC0_2_9q_>R5!}!Bk{L*dH4AAjcN%b&wreS7v!+rHaL03TIMI##(RE_
z2Ar-3Z&Xtt1xnt1{6u_%_J$0p^k)0_tggg$c~047bf%la^-@>rAf1!`Rsm12=S28b
zZ5!LjLWA;Y_B0!rpX{m>XWZ=uLj2nIedjY2h6L|sWh1Q&1o0Yk;phB?1-A2!!U|7#
zJqDUaAdL22s@w!!17sQ9E0xXT{WlWH###&f!yKlK?&7}8BpYE@5*7dG<^m+ycN72>
ze{tM&KS?WyHcAa$E?%=M3FTFD?;Jtmw45ksMv2tUlZoEa!@P0X3KzTf&as-;;#W3(
z;tz}QUf%YY@?m0OD^3znsAbYQ^)ATWHW)hg?fo{fZ%jVbo=tDi&i{2_PKqrSI~U(9
zUcNY6^yby8Ja}#ThGp$D%BW&*Y)zk)4wc?<-<XsS^F8IYuNtsJtlYgb+C%(vk#jg5
zj6yGtk$-ij!KuX42$n0F?JPV#eR)GG1mY^>C-hqX<rnN3|5iCxNuwIQneCxH6kLde
z#;Nley7R3fO2T>DQ!om!^4f9pa^)t^)T}zk=hBsy{AI0@M(_E4hIqio<cmBD!-#i|
z{HeD0Ok$RM42^;-;lR|>=DUm6jjyB8Y=81jsoi)tQ?!>FPulcK@%_?QJ3`|5$N6Nq
z?b>XlYM?dhFIiB0qZAZDdRX7JFBj)o(%GfX78?Vxo3_2j>YxAa3HImDtfE#^LK~h2
zUy%;>WbtL+6GY@=qH#wNeM~#QS9HI{VRXUQEL-<z8|ft8?DT#x6{KF;i^ldI9<TM9
zf5-u?N7hyoMsx`_`0YgkJ;SzSM@22&NP@?4m*$iB|M(y;^TJiTpC`XxWV5{Kp77A$
zFAVhzBQ1^7J!SXn#bf?At*5E?htv8YD?HhJ2zvj^nd_-p^v-uZf1R%h_LSl?HQ0Ri
zF!${*{`?V_6hBdZRJmnYO@VMB45_AMHKJ*$%eYbH_(zxilXWKs{`l$N3eAIn977W<
zBtqIU8w~bnTVY@*^e*o`)w8M^vn1oMS*2z{dWFoWvHk4s^n0?WIRW}rxf|^@JwM;Z
znqs4B96l6XilfBGo9Imu?^hHI^7L8nMjIA{u6Z4lfWJ$f=1u9*&0VIul0kJw(;tGz
zIMlr0cf=>b#-1r+ERf;ppW#G~)Z;*9y<i&OC<evYPxj6x^6%SU-MH7Oo&PYw{f|Ws
z79TMntUpv-m3M)KVdbhatZt+bHhG$=sxsA;Ig#koyZDLBH@@;45{Rc!Y1C~nY_ggt
zik5y5sN7X>J(7^nC__kP`4LKLXQqE9tXI+Nl;KU8ajP2;cDB%aLih6C(t4V7_h!2i
zGyU+!xZ2ciGElRQynu+wOJ;X9d(7Q1Ll7cpvtGOZ?fk;fMhY*|G5c*(KZw&BX_v)~
z#_ZZ-oP?#HE$*3F`_*m&?$^9#JfBKBGdQiSdyI{|2>;FtXL>$`87KLIf6Qz6XUUtS
z6-Qlq8KS?=lz&D_=@rtobro%ZZ@eC#jg4Uw+;%`Qe$FY}76UNZD9Cigv3!>vNW*D_
zc*r(!z0D-rpM+~C+syauD8_p-{^M!^)*X9(1M@zmn6Q`?uAJaB=4~Tw6PPTsZ7Z_W
zp2_CjA!;#c4irx47Q4_Sk11y7Z15fPq+KkB$Gq1zGICAbZ+w-3^i|+pL%wZdCb8v~
z{Z)*%5hm6$R@2&di}FF6R$8RjkYM|sqJ%1k+6EPuzd|~H=kNma9+ijYi1YQ|8LF^<
z`0QtFdIUZJ;vCU;5FhLiw!WS)I6$0s!DG7@t3Dv0#MW7`$JlKxC~?GM@VF`B4%<_W
zRO)@?m;|y$?bD4c7z)H%=t602gyEX$;d5Dl6exLXwENBH*Z3~8BFP(srp?@vHD9c;
zG)eRetz6Kvo<)0zQ1=<D;`S70Lqans4#{=~`{(szVNa{A{l5FtHoz%C;lRBbOkB&u
zYl8UO4)Lt5*3gYQQK_?ZC$XcZC`4V26d=X?1r#)_R!WXs4eo)PKAI2L0F&AuiPQ|U
zh(<`M=mfHLOe#42V$@u1aseOBw?;_KGIG`uE~+-|*ZF(@<p;I!M-5$9SkIR%_f>2@
z!iBe5KjL)A9vC$m1GsF*82rem@sDxMNSUuCMm|{EG}MS7^`4K*jB0z7+a40^Gir`g
z`z0G21wK-tq>B43DEXrwJ+v9Rky?3?o?KO!vnw9_V`_lh-kpF^%Yr|;rephI_s=8P
zF>Q_6__3fIfy)%Sk$sAtu5ml?o*XTL6Y4h`PE~7roAer`-fqOsX1>_2X=G&9NUnUV
z+^7E{_PZbLs_?TGMTrWfn*L;;HmBqH3jYQh91kj#3IyAvmtOs&+rHHpeq5Wsbr=u1
zy-~XT6dzS4(ZH>bI+Xrj_#_`~+}{1fes9J8YoM6_i*E1z-ix(ovIQWq0?@60d|KdC
zHB1y&kF{SrKK^wLDYI*Ltlgp?-8lym1UG<QwObCqd^>q(?FxD%%$hZO6Y;nb$jEJF
z+H}wqr7e_HWV=Dr%hKC?T34E4-d46vG1uEbPCL{!2Jd~XtP?5KuNNp2k+JbZ`<fZn
zd^}KLZLQ!&ZIK1%rL(+2qC0FOx>$*84-!vB?{KJg@d(ZKD=9yP8pFljq@rDLMi1E5
zq!!5Puv`@FY28N$*-5gODeHBliMV>)e_ptA8?^&>R*q;5$PbVx?1O|W+F2#$FjTad
z=gb|{7-Jw|sIIAZ;ObR(LEzaFm7S)NTQVn7$7Bf?zQefu411iAW-5wT<_orW(q7M_
zFIe`-?=WYF9<<U%^upjdORuN_e!-Sloy^v)>EW3y&S~8uZ)-L^uIC8EkEL?#Avpwk
zOug~M9|?xv8KkW}xhrf!F|*Il%V2RW%}9xX35|Fs(QGY;iLU^mJ7ec6>TxHa9wlGy
zXt4R3t(vLbi%ypMOpsf5s1X~s%=sO(FA;*MGq<|ezeJo#1WnWf-Q_7qXb4Xt*lKZB
z(1WHkyT@Vr2r<jaf<>ofTbq(B5J5is71d@=p{Jv0W$b_bV^_|p;c6X`3~r9A`Pwk>
z-p&>@q$3IjL!D*<LJ`7X2>S|3&XQdU1gE*x#P2-IVitUG72x(h@B&2uA7U*ENWjD`
zY(hp1H*^T((M#tBbKrn@+mIgpqC?YgKkc<siUnWAb|VMa)+g4Uj*OUOHPjYV2#6Kb
zN9P>T2o{8q?%S0(Q9~nQ)XwM)(B|WXj-au6t7hZ1HX!c8X$K4!UaDAv@H1KxbLN!c
zvF;GwHi<*cQJacFY}uGG(d-_)nY}1v@rlE9#E;Mpejd@J_}K9E^{FN@ouEh+QRs6v
zNo&L(x@O>Sph~X60ppSdC#4qa4@5=sHhhJMQz<sdJlA6gaq$??YjiQ=(-etWO9%2D
zUCd`xDdyCr*VU*f41!G%jIVR=B7?H|J*jj|+FtgNd9?jFl)LTdp_ZN_Zb8!lww`0?
zFE$#g$%L~`tiA}Dz;7UgnFXqbjwU-sOO^v{+fiO(Y0G#tyYweZ$au8LNv5iUL>%Vu
zy7c&0J@tfPr7dP3>Nj7vaI%6hNVX`$8mfN$IOL5Lb66Wo&ue*tt>rq;%^inKC7b%8
zxs;!ZAVW#puw&!Uw2D??ZKzOAHYpKiTQSEUf9Xz`LI4EeyS9YJRed^qmo8Y7Mz9VM
z2HZ?xImv}X!~nkvf)02bb<sJ862|F818xy9o)-gRpUTgAdnG|FOI8%@gMhFjlDmxD
znc{T7E^9tf8nXms*1$fZZK9*}h(>%S32F}0@~ymE_OaXfq!=cK<-~nrqKQn)MMCXH
z2Zy>l=ddA7mhUvdX@Kr9Oz;v$!<|%*Qd7k`U$iQ!Kyx@5bOvcgPSRW>Lk>Zh@JXVn
zsktiepjJlTRM}G0C>3*`5)3`(s1Ya|6RTLCrD}b)fOa9j16v=QA34)$7(9n)+34rl
zyxhPnye)-uN|5{_B&StR*kDJrwSd9!VFS)utlL@JCU%dh*jrqZiK-sOtf86YdAUvl
zd}oZwx?(FRcF8*+9<OI8D!)#}KAN+fW^V4^uR%*u$j0FWhnBiR<tans4<6+{6oT58
zvr&AORrj2ggunz3a3Z<-m3mg6QWPZ-IK|ji+o5xFIAClsibs`v+G@86Z#1XnZIFnC
zMs^s_SLL5{4+$^zbhd7t>Xb`iS`r`pip&~;W?S9XPv#ebcTMux4Fpqlw!UG7o~j&4
zb*hVo&$)PgJ&n$4Z)dz$%R@Fh$e1B+U{U)A<u{5R?Yh16U$=>Y9U4y<a(1ClCz_pO
z67q_0G@}6RgAPQg=2S6UY9R<2BQfW8OZ7Q&V#!RKez6n%eKpY6@UyVdtWC2<XQMrl
zJeECS-a(CW$C{#GKHF*t{z>~VlZM2c!bBtHid&c=j>vs_NB<$oW9za@w-Sg8=Z*74
ztSCyq?(3D`eB@4_gXGfGs1RI5`|qG$rw>V|7T3&HW~drtp^7dfUNP`x+eY0YRd_ES
znU>AGQ^@9Yml^`M$$JHXYcNmvRwta?Bsr0n?qq^$=d7$rw4AwE%q?hwc1D1I>Wf8Z
zMmtRLzuccrU3@AWEt|)nik)SB>=@H#ZdPv|k+-vw+CN?A+Jq{pdgI<5wlwlRqpat#
zz^?OX{z>hG+tqLPry!p9>kEO4-Pu@=_9o+5vR$ia?bgfmB-QWBR;aGC0XEgD#|LHN
zBuAv&r!+067JDr-=Qyk=CDoCJg#oAPCTd*`j!3gopr{^Xx8MsmQeP>?oE=)3DY2sa
zY2`)Lzewt4S)PQA{-GsRjL@yxrr!774`FU)w%EtCnwWs%<kbaZ6JmglP~8L>M__7x
zev)tE>JeVg8^mkK@l($^OQ1-Y;oD(p@iGFeGHko8$CYBQ;fwEuv5pP_G&TxV1OX9|
zMP2t&&e;yj6gHZ?Vw4>7n-m+{actj5aN=}ittfR$@Gt)Uzq=#UkKhM#@hItVGS)FE
zH=q@2o~me+hoL5jswBx;?YT-<<v96@gf}~aNvtSId!H5bl)9=f2G5)7EraBApbPFr
zT63CHgh0i$RaJU~+Z`Ms?K^BrJHo`Q<Pq-9CSlIlg1>Q{>(L@xQzgE~6(=tc!%`i7
z!YQBBl8f?2D&7y@(fFT30OEHVCJ!JzDmW<_v`@zn@=fgUsg?-qg9VxPh|}y4F(*Qd
zfh`<nN6myWET~_%^jVLt=JcNuo!!|mMVe@%dO#MF`XNVdio){f4I8G~_*ov0umqk#
zEqyxIV@0zuSY>cD;dA6pA9X-5l5^!<y!hU_-$s=ayt6y|$*aWdXfc%Oy)d8lSt)%=
zE?oh=9b1H}Mp8qBo|2r}G1+H_jr;`Bn7-c5ua3DzB1IUSj+%cpBOr#cWaki<$aDm3
znV*iiRLw&js3A-1$F#l?P!k#3^0|6g&H;g-;_}_GNy?wp(3)hnEat3fP#g=&<Uf3I
zjhbtfJDeI*lkT8cM|$k2%iN@~Iz>s_(IN@g!`*53+8Aw-#*B%raYAe5g4rRrdMLPH
zqf^=>VRM4XTElS>NKwdXv02J}M88h83HzA&HZ6v)CKk%MSvt$iS@=%Y>~$HlO4&O{
zk+g$lJoFSj%#;nRm~t(4WO(dX-+qL~7d$6^99w?pa&|L<6bJrBm!8lTKL6VJo#VT1
zQsvwYs{G_f2noOVz9E%<tX|kVDm6!5ltu=%3s0W6mgqG)s4STuD2YyWEHTbkJjS-j
z4>Pf0b-Bwt(0c$>;<@9hHYVq<fK(zU*9|lzzp^vA(rP5rB=rH=F>poumiAWp8XrtA
zrI-1Y^s+TK^sSk<_WVeFi+&;0IoDqN{sB0@4hPTul^wo+eD@Wt-}(kUnY!^E)^+^n
zkF-=edt>kaC3<gA5cMwo_oWZ0)ipcu<m-*EcXsL{`*##??U+sN`-T_Zk*}`UT36w#
zwEk}{X+N%<gW;_HM3elC@!*#xSGZJPy`=sp`<5LU?(CYnQtkjkLADzDHgD*H@j4y&
zdc$b{Hm~jHcdjpAQsI;tm17ff$5LRLwjU2vdmd4qJ%vv@DxC=Yh%Bq`0NVdCsizO1
zW;?7rFw}N4$c7v0*bA|NGeI{!rL1^hl={;rn_~Bqx+mmW^#K}dNc%_W^MSCDWF+Hf
z<5}`GsTs1>70l>=BhR*Fr|+GK{Y>4mq2Ed#J+b~==R}kK4*i>W+Y{s2r9<<T=g1>N
zfyGMxn@^vLT<1r3+;9J<&=a@9iMH#ng(Jhp0~<#toATqCCGsPCCCKVSKc*ktw6=6L
zF7ZEGT0g&awo}fhQ~&0|Z+LcmB4+B7u}?J_XYKm;WA_L9*u?=$$NVp97md<wjNreM
z7gc*;`kx>83HyiV<5sBKkF0ece}Y>8)=(>Vdgvo&;*-viXCcn4U3h<VrP}q0E7ckf
z@Q`uaI)ZqJ8h-Fe=g3PJ{(FH_AT<6daOz9*+cUdQp#A*S`DAN&l$_X~sI=d${Z;G0
z`nzg@QyT)w_BI}$?5S50XENo@uRfnxVzX=O<*f#?rre=<D6hx!*HDr}^{dx!B>2w1
zD&F(#K>DuHmiX!P=`?I3fJi}2bhC#u-WyLV4Yx>D>U5()2#Rvl#n(VPz~G6dT^qE}
zG;f>J1`A&%D?Q!lYTB24Vb`#_t<)I=FXFvaMcR|}>TF>pZMQwP?pG{9Mq7q%R+E5*
zml_XN>AW`f%uwZl{P$kF&N5(C3bV^i-Ju&7?bIpq{o;+o7Z1&ZUu_(=QE??*n!S};
zOv<;gLtJ#;t<~F|{E3_Y<qv?y#w!D(1kU$4?DiJ%HJw)O2{l%}fD)d)r0GjQf`KL7
zNU}i1??q{nwW8Gjf`N`uAj2QdkN5BAt49eM(RVKAyMGSFzjPF=0wGNgjJov=)O+0B
zo?#Mb|2@EQ_Z#0PGn>&@5S)v&DAfOs)ie7LZ~E-G6}B^tcf?<*ywE>x_80ZwlDeO*
z5E_(}S<?2{)5Q}5iub{cHf)anL@9IJzqGLDS>VxG?me$;1;7*-*<U(i&u$)9FVB3N
z&bU20XZO%u>Ui<nK!w{MJbb}F7`bH^7m_#M)!*(%xDyA?zPpux8aT-5-$o)FaD6xG
zk^Y_pb`tjvPEdOHA&$T2pb;k9OJmy_t$r2vp>0<xHyGQ4s-l~m_l!mC2dFgC&G*ca
z^U6F&QqcZnX{M#{Axk!KY5oo47}<*RCOG3akq>l1D||VDmWs#hwnWnoV8$s}jecnA
z%Z#7`&j3$UCIyjrPb$A0s*>P}EyEHcEj|Uvd`ug&4p-a$PKj^>R;SCwEPdiiv8DKR
zJGdadYtK~<^{eBRR>02}zrkmj^vqKmQ!s@LPA;b^iFg06&vdEqI0Z(@@O(3GWJc<A
z8a-R*2U!`PI-W^4-K+49vRfKCz$^ZG?|Qq5kn_DY??BmojE*UVClZxRT`%{}xX=Fp
zUvpK7_Y5>4n#dU*bw5z;V$h72Cev+8^EXm(W)ZHY+oY?+PV~-h<xO!ret)26yVg-T
z@Fq@KinOc5{cyi%?lb8M@sv}I1W801yiv+iH*F9O!IfgsU-|8zqyYwp&B^^}@um&b
z*SqUxCgZ(kx|Q<gH|k%y*p!KMHJ$<RyP`z8=CAFTO<Y?0TORbep)0FPN9*H+w%ne<
zXjJ38`~`fBJuKPY%i|T0KK(Yrq6&v9WP57swx)pOo#y`25#4wS$NK!O1Z#V?rSN4=
ze`Gq6t3jt^8A9VOU!3Ilz;@Gs=6Nzj%4<8_4W|eiqNu+DCrxNyW^Pb?wW#jA<9zwh
zK}1d2hbxiFa3)O(-WL)<SWFi9o{BoO%p+t>$s}hp8?>>*MTApbDY~RFWw^MfMkXqk
zif1aIwx(~`B_R1NV3R6-1jKo^{$+AT9lAn8;Yh4Mwddy0JCDjcGJd&NOIRqj`uhZL
zTJP;Kz*M4Fs_+!ux!ysvQcJQc;iMaF85vhP)bqqDyOWc|yCQqk?ZxxPB-x<R2YAwL
zfSS5obcaAUN{N*Wl8p*?h6_J90WQ#*XWA&tGl8ZAvZO$x1do&P+3OrcSa;~5*|ur-
z;nE=&hI(Vbag2JqLwh5{`_0LJ$7c!Y>IawP-%%X0Du0;2W?V&n=+)vZLH%^6rkTyf
zhn7gaH;*^;J?+M!)SjVhdW#)QTi*F<@`D$@_GYF#v!|+fyc29h0{u6q+_N`c?jAPd
z_otgOV*p~z=O_;9n6$p)``+H}P^}`0%%$Z;$VW%Sj=AupRtv1cX{x~m2HMamnRH)b
zhK#yj<Zyp&UWWoarPCdP#caRwA!o*jv~H$hOdB%FT#3IjG~?dB*g1=3s5uiJlNy3E
zYhORwWkg8ZaiyIHt$y<`_lv{YU)G3`a~cH|^xd)_GXbWgAX`Zs>Pj49A0`bv4m@X4
zLztS>#Vau5nFd|?juA}}eo&cY+8DyNpHLkS*C6qGIrA8k312r7C9bAj1U0L~R#`NK
zwb4DrQFPjHoI*S65zWTcW~1#?QXn~=HngB_kZL4<l(CZA5Z^S6lPqm+vX!%T6Z&Rq
zPW`>JT;b0xChc7#?Qo!s>&Pt`vmT_aT5%n&*?AD9RgE+5N3Ak!=;N89rBAV>SQT)s
zA3XKvziHPkC}*)D7Hlee7ZjlpUJ{6KX$lG?XEbPYSBEp`KuXmPcu6vhnDCNB6Skw-
zCR!C&K~2mw^&G^DHB!UoLdO(~T2&53<MwP$wCkj-(dZmmr3<>8&A9+3QPp(9$pQ!_
zM6Og!r+HWw{^E%{J?mz`QtAD-i3sd0{P!4JV@a_v8AxMWQ7e`DNLOKwU8rqgYMY9F
zlWIX+5)m*7g~=L~V15*0g@q5nT@McFQ%Sf`@CbAcy;0kKpqJ;^#~U9vEUB$E!)q+L
z%j8Y9ZHsxEdMFItR#nW>;Iw&3qZMRQbsBhVe!pF&(8@H`HY_7oWqTJ$Sv#GqIb9#h
zB4lf*GgKoyLiV-!-VIDC9mM^E?lX2(efR(P%>VC3`G0bwXtnF5|KaVns`h{Q*I)mG
z{1^ZEQ~&&IHR54Jb=H1-#8wDG4lwLLF%kd{ae)e4_Md(S+^lwE5HsI~sB8bgU*G%I
z_k`HI#&L~nog(tB9<8K`hDS-%3g?KPfeh)0LLk!RaRPBM%Xe$~5mqOj_4Ep*1%ugn
z$VBb3M0|3uQOOhMd&qm3Qp{4?hKLPRf@gsxEsC)En6;m34iY}5nbeGm03$mlDKU7|
zl}YML?0iuGsJ-Y*xJ;nQfbpEn{jce#&dR2)s#3tR+)pU2)F*qnET)mfr2AHlIL0Ic
zIadO$MMewL+W|C(5gKiB;Zc4_>=3zWzUDsU4EaxzWiu>!vbJHzER$HeMOKfYAqu!F
zgnzSU9WI+yx2EcL#pqBS67(-jgw4g8UJ#(6eUnkAa#qV}&W*qK8ImK?eOMEE8;a}6
zwDdMbRtLnFz6GcNO-*}=F`eSrAbs@+_gMB(DW|H=yfbKLVgapRSA<9oIWvwV;C@pb
zp#bbqzjesjSmim<E21>eqp5^Ap#P>CFsvcPE>G0@uXN?*j0t3>!eUMwB_T(80SN#(
zdw0qS!;DRYs8JM6R%gW!vVrPz6BqfSL?kHWYwgWB2dkw3PUrgdoS3P7{aTJsq6FU9
zL~Vg(irmAU9B6$MK$aT9+w-xB4jiF6<V&?dwGAK-LkwO7mLu}ATlA?dT=+)hGrWU?
zA1+AQm{&}R2zV0CQYiqMSTO<`^6y2#CuIrXNkPYp)-8JKiei*Sl)5#>5f8=|L12~c
zS#wNQ{lL{sUDts!*qE)OcE7&e@UblO%_~gziz8Bn@_eMCQC*N~wPiv>MvqFaMDbSm
zNtmW&r6?A}juwTaBxI6oaU#lG(gDaB=u$W)`An!!i4X&{MRiwA);X_GVrK+uk2vBk
zMpLbFz%|T-j-JYP+n~La>I{IlyOnXD1MdjP+`Q*5#RWi}r}|Bw%qBEFtyvw1m<W6;
zs|0L*MTd-aWS+C)pSON0tpQju(Pt_>>LL1lj4C~E>tddmmVBm0)<m)O>EX~A+x=Px
zfOIDv<0EN&Pka<Qsgj8b2gxs0*jB@&v1yO?rm>kM4(^ei_<RuaJV&(+#>F_Wo|vDS
zRk<YAt%)xh%^Wtc!PiW{lLrIzD_P?;*|jwryq>3JRYJfyLE6w6MI>pQ&)zg=hiM17
z*`ekL#&4a5FBz`Q1`tj!Q-=WmiSVc<x^u7q5E8$$Mw%M<euX14YOk__xksH*k4Q?7
z2CTjWhDIovHmw5BcVPJy1fMKw$3B{SKzbaqs2C7+pNMxV=A0M}Xa3b4wUGgeOW=&8
zOuS+pCIljKe6O{+jgzV%P>uoqwuL_mik-rD6$S)+L}>(vp_zzX%j4bY?5x4fsNtM1
zEzq1}(>frJhHsT(`<)$5A!606D0zYcyqY#XCDD~DYw-?psx0PMnyGjTqHRk#Cz58O
zmP1bhXv9Q`6Gj(o8=D7sRO)1xUqmDxPdFt)@>L#irc~3?cUY>OkX^PHhYspv!N;9`
zziF-R07(*%r?Lj~xJp(_1Wqk`l|*t50&-7CQCqWa-g_%IDd&zVydY{FcKAR<H+3!D
ztD7m&FydC43O!WYl%Nt1i3W{1^~54=SA{0MFYd)urmBQ)X0+}q69+iq7EkkzaKctY
z>A0>6A^Mh)(Sah{V>I<#>&WM_-nT4U6(2lmH1Z3HeBP1N4Qr)`NKLjfOb=bdl2X#D
z$|;GC%5RpP%`8OZw0$_t@pFoeMufj;Oh~j>;~`5Vv<@_sPZvYPbaX5bSc7~H6OHgP
z={EzCCS8G?p5(s(m>Dy8OsosOrG*vJ*sAytLWT?1K#wIgI*&VFq-H_7&)~ujS4W+7
zYY@|CPTOkEX++obL*(qlyvj!_+&5JLJs5-ArNa^9A~ytizH9t9kHxsOo#glwNodY#
zsn1@I)*BK2oG$=UW!nPDRXqt&+ZMsNMW+ypQF$)x#Q1he8_g@Uif%hcZrR2M=i3y_
zb&@UWxTDWen+64d#k!5%l}}|(lLl-#*v-7_T)D+1DB5kK!TL;6FFKA$<WL1wLAm83
z{ovpqA8Dn%fig2Tu()OStJID%G39=e73UT6%^;So<G{MN2Px@QslreJk$2{F!?1Ti
zTLtP3-*xe*VJjg_B+WaFUf!E3tm<H*GAcD5MVq5!Sh|b8t;?$g!DF$nQh#0~jps8R
z2^TjbjSG{^qJ8XVQr)t;lyr2IwJ}1Bhp(reT7JpaLiPqI13Sb&{&&AA<io@cETkYo
zCk3Fv3Rf_Xb1dCvyKPsf9gi5M(uqi@gCxtNkx(K+r>i+x(H7*i#~H9xkrS4Oj^3FH
zh#d={=Nd%tz_-sO*>#qdj`Aa|2n|z4t`KvHI4Ixi9M%0>q#XPxyBBw43~$8P<DQZX
zXn>CCv`1xZli{P&>-x0zg0J7WbmCJ~Xr~6YA1RS{Sg{101(wxgXeZ27dX8er5wsW<
zdTj8a&z~?D@&U`b>2V@dGR;Sb+XZz}PTX$yEo3o5j7K&3O2~G;%^f;yIaZa`8;up+
z(9iNL0+V3_f^j3|6pRVAsj*K#6i}^Mt)5%W2BtH`qF4$0F`50t*Ez<Q9mDv*%oY_#
zM1^pH5zXfi;K=IbnlKi?%yBQ#@1!{i%$eSZvxJK8p;OD|?GzKGVbr;j;x@90*B#_V
zv6B*<_7yXR=@AQgRl-07Rgqf_kASn!7&fA^k^w(Dp@l3{42fPsMcu4_{8)2Gz;=3V
z(F80a8R)W*4^i_in}MVO5wd%OlDsy}mzaIos!9o`#)6sYq?pLSd(%Z%Va0!obq~ep
z1&S{j<rIOk96Xwuk6*Ph+%&3eg4Jq1E~c(A)s1|};eO)fHes6BP}PoT0H}<BlaTj_
z5mjCxoEOuFMidLVRTxKRPz#>a)K;ahID35Lno`hi$;HD;Uj2ssZ?xa2Tc9?t!U@n(
z4Z$hqgKtkad@5*;8p%OLjgC{dW-?$9C5IgqvFlLn?RFg7G{+{^N9u@*Rd$uFmz*B#
zCn<GPHK1or$#Z)pemUuO!WZavhHyn{cC4bD7j~qF^+RcWz13$9C5*jR)V1D>p^?L-
zcbFo#-}{3F+NEvTasJf0InUC-e7a+hWr$~`m##O*Jalh&r9IGP&e8cu$7Nd9(X8@#
zT15iYbGwHL@jsS+M?KYgK)Kly++cLZUP^2WY+zeSej&5*_?*(}9qX|l|3Ka|9IMyz
zE3)=b&(5X9bi;G&wT;%b{w+_A?bxT5Tbl<`D^lqA2Ycklf3UD6)y&3OOE~`yAKZqN
z&&R(V`diPQLaWjN<X`z&L#h8qk$Pj}^g!XIR?n}zw6ni=qy9lgd5<a&%(PeHOV)Cr
z<;ktLx?Y&OxWD>c&r{cp8`9#&RLhBxYwCw~PbcKcx9)u*yp4pGD(|;iiB~F@>9mw+
z-LpRbx-#1E+Rbl%jdl@pP`lS|lAG98))C&bk$hJ1uWsm}WAcNi`1fYQt(|J8)NZX`
z-!|tx)pI474vb1KHZ<=XI4F_7OH1wRht*Lz9Q&L$PSe)5@NgjixgGaD1sQ06p`FAd
z2ivXrP`dwhn!kzWj?WqEXS!(kzH@V))&oYD`hjfx@N=oyy>ytJ3u|5G6=VOv&a4e8
z=S%WzOrIz1$Ghms&o8t7>Ck5t&!X~ZWUlq5Otgp8PR}K3-AIyi@_#DRzq_AwtauZb
z=(WnMvT<a|IO#e4-5*-FimmnJ@Z;O){g!sT;gpnKepUVc=~By|s22`Ax%Az+$z{{~
zt0%wvwq8>l{tLUqZeS{(jIg>Iyj@=Lu}|V9R=Y6&$S0A%jK>H5TNWdYYx9p;j9()o
zHdKHC)IzM55SLMVg8%lB2($k0KJvZ||NN5w6q{AEW`Kd1VYjd7YsD8JB+lS^?bj_9
z|3qZ`qs8KOhSd-62l(Cvq5in_O?f{H3}4AWO}(W}+K<8<_h`%c6*AEDrF!ph6}dkb
zyx*|rGBe?>#%aEx3dORaol+i?2ibSXQXX3JhZ&04-|#}?|8JFhUg}J2bi*VOzXHiT
z{`jg*prBQ|=_4706YXaortRS6+3s@kv^EHr#I`0nZUPBxtUNGmz2SWTDDiOqu9bnr
z`nyW(RwmQ5wjLcA8)#!yd7wH#_dh*o{FI;A9N%FDPeqXBQ?(Chx0HIIta|Xu&--~(
zBGCJbT^GAY)x(E3CW{A@rHg0muQJaQ-<`SM21aCKrD}WkKmB3q0yZm%<+4A|M%8DE
z$=Ue$AAAbgLFw`QsdbkbAYDz1KgmuH-qa!j^uFg8(oKWgOF)_la8br$AR#F7WiHR|
zH_F62A#Y3UxfzMn!>%z$2CTyAgmWBa7!NZ5hTYZm0fbGRzsk#`blI95&|WqWP6RRo
zV&;l_uZp|gQ|ii80Fa;mJOi-ab1`o3HqS5f)n+`)08jqHcz|!8{RXWBr1SSPzql2K
z5=L*VLwtQxVmsZINdDVM_j0q{3*4``GC=p#P~64q$wOB6^^L|Fq;hH6xbe${gny{)
ze#mHi$9&&j*U61PUi({J>SZ{f=O4)U7qmieCio?-cTx9u7tdc9@ZM1kI4dt14-G)8
z{p>5m-Zec;{WI<^bw2}e9s&LcRr=L|IcY9}{twauOnEL`vv%C12xpUa%_U}9O8b*%
z(&X}D|FVB(v-cW8qE0D;%FaX(GVa7_1{pVkdbl#bH-NH<YM>&OF294As>`#NAs!Ut
z6^{Hej7=uhdzx7mHjpnT=EBqdq3>8{7(ZyA$;`Ht`isXT`f4gzS$pEPFJZi+5eY!w
zqj(%2i+Io2#hbfX?wV1dCFC+~<n(c^ce$B2eIZh<lX^3$(}R#9#=w5`6d&Q<ZmrS?
zkA%ku{|a8yk90GI9wUXDume3l8jiy+;|J070c=2-f`N~!jCsdWU5uPlkmr?XgNx=D
z%s;c%yPs`Ik6Sm^)yM5gZTo=Vf6s{r_)giyfmiFkUDH1@oFV-M@}BH%C<naK%|yZ<
zKo5%w27*1oX1+k?H|{O{$W(7p($rIOpC|?&Qw|<_Wub&ZjY?x#8lQfUqU%JzmYrh<
zlv}0A3+i0Twbc`%OJ?o-tRzNyO5nJFT=!BHU+%tvQ}|#C*aV=x&s9j9<!EBzy-@Qr
zFH4+GSELgy3C+x?$v=&phasZrE|5}Rr~W@x;!ne6px)rd)(lYBVY?}Tt_<(iq`wmG
z()aU8Ru7BPgEpd;ZY2^;Jz8ab#{XBS^=M~Lcnp{$RQj&H%q&a@70vs-Wk+zv9q+-n
zI=cDQYr7{I2*1TdTU9AcUFfY>#;@O6s_YpsON$lny!XdHZ?0+>e-l9HE7vk7(8|)d
z*oc$ub!8!W^V-@+<s~kkQo3iGxuz9PF%WPC2`7#{*Ha^zAVmW1O_ur4Iq!)|;_Ykm
z2H3Rz_DqmEaLy6D^p$ig3G^;+O&HsGJRAm56C$e~sBGYx$CAq}=PxFk5@%)Tp6bze
zzO7~=x~TSU&<d_5**<?_VCNT=UZiAUme|HS6E%7)C==bgg`D+->~}0sNXD=Qk;(0R
zykBvqmb$BZXSV>L#b?Q1#x;8z!uJe&^?32%!XybJ;xFX%esgNkHvaWb@5K3;m}BLZ
zb~R2fXz?E2^oOIWo@sKAoBH=Nrv{O}g|8FT;~`Ljh*~QKD}F^yYp`R}m54TCQjdY;
ztL~9|vhhlMq<eYb^dLM;7cpOI`}qptVa1PJ_DYvMmj>O16RutxX-T}S^=R?d@JP>I
z#KtP~smfiTJPdjidM6O4iP=mo;VW5L8&7j%bgd`L8$HUecmiWhy~P%qc6bij&kQxS
z)EL#^tXg=Yc!h<|VS)`>3sd7Z4ZJT;bQvWitc^_B!Ij_tqeqdgrrCTKY9?TAj~)%f
z<B+PzxBsQaD7$L7`pjvjd7g%FC1jt{YDw>f9b2?0BEG;xIL$W_zOs9-OW|Wc(R->5
z&^bZn4}-vN%TdV4O|4S2T%-IS99o65rr%7tg247@3_cATwtyTEcDew-JZ}0O#dLIX
zAgJCbS^&l`8z3P{SiEn@hdZ1vE1K&+hdymHVk)|-%o}GFDn~rV4#tFLl;4;{*k%hR
zg&Ycb@=<35qyvhRHQ`N$Yg3nSQM1B|3Ve#?*g7oN1!yRvM~QGuwqGXHbl>SE^CjO=
zq-%M8GaDAvlH*t`3L$KiI!b2{_7=6BXRD+S5N2Gl`JycR{#(CQtJJ_VP1d#+j@{)}
z9GF(EZn5?$3n&?}n^~-8q1XeGpkII92|i+X8Q1TZA)kVY2s;w67q^LpTCAoA$Ea}z
zI<Jp*J?W6GzZI%bQpICRSS$bmZ4ZFFD7=Ms4BU5Xn&71q#Kr>%tF>bgj=Q3&ggWhE
z{lN-F^j5&R1?ggF`M{RNVrh>tH{=9E^6iiID_TWL)dUx0$;4l^;L&0&6zdz8o&O)F
zAwC?6{qF5u+z|U+dCM*Bf9?dSZ9MDkU$ahp>v^9G5ZnKfn|$d%tY&y7PzOMjajSD~
zzx@-iSM8V4+AB#2U&2pcO>36}{0kffx2O|$k%VCFU&ig<09zD{C}0fS*O7B}mXBHb
z06bu{kDH@XK(QqwB0<okqH+Q{c;8#rDM>`771z{dLI=~WQobkPbE3vK(&1ndO!R^s
zGA-H<oPRs*O?v~DWVcAV-giNJ6iu6K1fj?GYSU_AQtHrwo{2);Y7{t_%~T6aY6yaA
zEi&G4-C9hSUWp*g2HAp8bo$cl;+bN>p(e=-+Q_<JzOitO=^;GuF=G;Fz2r0t-6XYw
zeEbxebyPDcYRy`s1BGgeYowaS5>XfNNQTexvSvDZ1PWt7(XkboItVc7sezB%2^6{Q
zHV;&_f*j!iQ5w~`R#@$+S}_L^O8SDVY-b_Se_bD%44ji_nnNk5=E*z7Wn_9yK{f1i
zNt-NlBtYaP;ykkW-ogJ+w;P@?Ip_q<kRzB9>MS4!I(W~Pdyg?rV&VwGi^Rrx8gjlt
zHnFqX_60N)C_q1{InR*Zl_<*2js=<@+HK|KW!|sXIm4P?r_5QfWvAp((xza(W~mIA
zq$puFQ^Pr3JE|Qb%F~)fwKVI~wkAVmsZ)xX?&3qNW7f<&gy3wb?$!_f1i-Eh_M(I^
znjTweEU01(Ag*vWC^P`!LyWfwKvtq&G3r9N1TOm(HP|YdBfw-E`*nOQU$;d@HY0*s
zHM?yE1W8VJ<}gYmy>5~h10Y;n1H~bio)18NE^2iyGqC0eiD==HBdz2}?P$EW_s@h4
z%(pr(1`Jz7!Dro6&_whY=_f}#@!}mpM~6G2?INZ#Pt+@f^)f1$aZMMgfGTAp3J}|u
z);k=;ueQk2`Umh8OYJ6tztnciJ4ELpY({($M!lI6DZ28s5r*DSP2%|M&4vz$_@~yQ
zOno8~NF-O5k`4)#0&E{y(}#iQJYs0N-AAIu%R#q+awtWr3(I!tF0yt>2cx1ZK89S3
z33^0&86=Xa0#XO)o&W`-0p^$5{a&%dv3_^RsRcCsH;?HU^~3C7kCJLpUPG3OOOWae
zDsCkKaU^+*Ysm>)XsdFefMk@QBRDnd>7{20Ns18-aMN+bgGYRKyw}}AHTSckXSe?>
z)dZn${v!3ClN+WWG1BcTX{(wY$ve&(BSXZ&qd2HNq_<l7fNM6O`DHrIbc74_T4R*k
zw&|&;Q2n(9-DR~Jc~0%@S)b<f0eiq2RYUtxEohXglSZCgwp|U%;<}Nr(%5Zasn$Ao
zDy*T5A{`Q>;s{-u58rpzh|SAd<n$s9?w`V%B$Hr+^_*HpT2Lobll?r#i(g6Y+vU7H
zPr=YY0NBBfQuEJX;>!IADw3VLP~##x#EQTX(&2X6!iZmw$N>wr?aDczBN(9Ivtn+i
zP{KV7=F(w`8Lc&7VX)RYZOy>^mvhC47@))gl1F^HTvqYa(KFw{nfx|W*Mj7!6Qjl&
zQYRuvKfu?(2~z9n5IB647QbGmwgc}d>N+p#89ZISe;O)q!DQG+l&nGK+OCD1M(WeT
z5Hun_yr-IY*K%l>R~K@t^9~@^#7jgpVmLtqX)|_lUIV1)4D0`~SjSeWZnSUI8Lmxo
zqpCXWj%%g`_0kmEXd_9b&KAL|Z35aF5*zi^=nPVfqFZuO0iGFDfLE!`gn+nfg6IWK
zp%OD&tdhxHN(AwKn-pS4ox&Bi4e*>9P9w@JHrVS-?9~-x(^PJLUC!aPRoh{teNJY)
zT@=}WIUdbGX|YACQUU3QSOzj0kD?v;U@v#60-+=YzNSgmQkgQYP5B;Ob9Pt@p}GtU
z6enbap=beXL5p$ck=CFbAm;A#M$G1PFE<-ruw$!1C^?RWUbZo-o6RiMZ{yvwD@C&^
zSU$rLd6c<4E@g<jXv`3|h<-B*XDqGD%=3LMpK6jVKXVErlc_2|aoZr9h+PWHBe+Vb
z3$vWwD*G&a8i^W>qHU<_%efuesGg8)dmbxegC<*m@7Y-fW}Jv=pVb0dH+GU7v~21)
zWRWw)v}MH!BM$Fr?PM`<g<P$ab>??9={&)*27Q5NQ`5GRa1P-=yy23^7~G*P7+KIy
z<_PKMb*Owc=T+?=zVWFXwMmuONl~>cahJqY+lR5M<!$w(rZed+EIX+Q4^qG#;H0xP
zA&$q=dD8Wu&0HNr-OMn~W>faOX6UMZujWijAkfY!nord;9bnR0F`ZCL+@u*>l@dQA
z&sw_4{BU#}N$@7R-tH?NpR@Gh$%Qa0l4A1c(D9)un7J)0(aJ8A=Z{?Au{EVzt>3Mq
z{c0$VBt*H)c+A}0Z-6M3^BEoKO})5cVB!X2R4Va|UC;f~^kJjUzy>v=kC>M=N#>%|
zF9^*FS_ZX1(&cxYl}La%xyhqbQq@2Mc+~*>y*HMN6xETVNQ+WvomE!SepL$7i5V@D
zE)YjJnbo7^SV`u}nm~Hdd&)jaY`^%TvbBi(2Wu(Wsx&6G;s@V2Bw!$drsCYm8RG(d
zgVn9k6)aZUK`SN0#ug{jM^>u|<vwaECYxuJfg9MW2~td+T8A~B@)K02v9uZBkpPPk
zuJw-`HZUROE!RZB853DY(RNN)?W$l%9l_sO))y(AJ!bYz$NJ5rUe;{lF^nRS7Yv`A
z9TE<i4oDaZBaYI|8(tp?Ym{8$4K9-k%iArQOIrdwDRm+_qAAT3BuunQw-Xb~r^}4~
zrf#QJY4N1f<HY60By_zhKie8AST^?JILGqE)d_{PVr-?#ig&`;WQ|OKDAf<DtntnU
z(yHa1jWS|~WP9~OI~giEe8j=}IOaziB~o%#(z0budGE`w(Wq!*+vXETRZta24Id$n
zv#p*m_37zhhWQg9zgY+NViN@^h)ldYBnVafBFtplVe%1#7$z{z`UTx)!DUl%aT;_n
zq0y~`v8Ff6$pwiA9cO8-+X(5{hNL9>sC>lkScS<vEyTt4;yf;)g!eSA|M7ozM0#V>
z{he|F^g&tHkMD0It+M0+055f@EwJfIvDLJ9jD#k&-uYO<lHai^(mB!J%Fl&4&Zd-u
zCDQ(MG|LiMqzoj^q}7TP$eOH4PMZ3ZN3wCI+L-iuQx6uWdh2cE7)#1CM#^7ROy7bX
zyrVCPVse}?jqhvri$-8?5q`@lqu5Y<o<-E6(6(57N|TCrxwL~Lq-=RhE^Tq$twWd3
zG9Gf`%bYM8C&GfzkVGOKwphaq_MNlxb`lkH?kfg$L>Xu?`7Mhcjg;V6HL=8?SjMhr
zWL^;R@*0fAX&pJNs$iS8kW*?aoG`^9ixULaPL5fz1uHkjX$MZ}D07~bKw?Vm8s$Yj
z)5jNt-#`ADhgoO;OP+e8$usbSnRj?NJu3OH1g=dd=DY`t^mJe@@Rsqdb?Nyoa+0=q
z)?awHVX*fK;?O!9_NgBjtsDKz`u79tPm?e1nBezr$*i~5m+z<RN&cJki#w)zhxyMy
zlf>qf1FecZ5kB|5<QHjKdfs}>_`dzO1|3mP1)ilpeBYZv92MOnZ{&mWPx)h+;@??4
zV;3$=+M~@~hyK>6c<(NDdQY`)*pS-0GMOD|?H%@a*+2WmN`>9~Li65l^K5hMYlkn`
ze@*w6#`!BlOPLS(3uvhry0Iv~8cO~7%y|4(Ycck}PhK(p{f@t$`B%&98%B1Jzr4Fs
z8Sgj{ekT*I++E#wJhJ@yy4UkvPaV9vx-;4FL8xaNy+ksJhM)4mf%Jg>a9g~Wy{c}L
zwycDt*k?DqmY&xe-Ws~H;fo+x%1mj`|7d}>H*_SH`1_t<>@gsDq@5PF@E@x^`NvuZ
zQ__<=Pirk3_R(GXxv;!JevY?W<Na4Er;L+ISstSgo-`hNGR@ipsmD^MjIcbON%Jwf
zYf?*G*Pm#;8p<||8*`<JsdK@rcKY?xr|gqE+6Fos-!6m?c0OBA?*F<pk@23f$k!6D
zHfFb4-@U?qHIYpnyz+|tE6LbkKSxKK_nD_^G~IZ|f_E(Q@^_ZaQ{Gmk`QXqi^s|Q>
zFP`=u97Ia%+^88F7<xD4{Fmh(kuA4r4yX=4;nH~aG_Uau!5XpgkxS!aV&vCYijN=o
zYn00WBzkHq+X<tE{NP9Y2K*DZyE#7T)A-0}F?RcUxKz6yt_39Ej<<~#HJ&3-i+1>^
z<6~d&Bd5ktja&IRMCyO))F|Ap27m2So-5@!2Iv<O`=$p*u3SV&PI%P+g+cO;d=i?N
zjp<W^Xa|3_+HorUs(1HLW%H|zFR=}k;FXm744I33k9U{%Jgyk`4m9m5T}h!Pell{`
z<AKL}jz$Ux19Lq;R`;h6CDOEOOlh|pXEt{|zd!j?cBtp)CPH4M%+{n@AGtJtgR@2v
z1+bOP|68g3k&SnmC<CE35b8_(Ol1Q3RSy`CRNKB;>ZjY5!(EF9?Kw6VL1}VgTksw0
z{nA8x%CBEtzHy<tb7t*b*3aGMO7ZYt+D)G;?BN?KO+EAyzX`eSCDfDLBDVLN#a~(}
z7)??)78aXW{_@B#t9IL4|8Qq!Uk1?Qn9|9EuxX&P1j#?&540lYr_w}f%?XR>FD~>1
z)+gHLy~DO2Lht_l$-C2%=RyK$F|WG;U;=U19>_F(uI(P4LG!trhEAo2YXu<)ZaGcK
zg7@XL)sy`(Z7i$pdKYg^dk5DoCYs2bhFW=`?VI+&L`BYbUkuQ@4%*91qz_lSwmHp&
zW__>p%Zpf0mO4<*3h34NKf$bM+WZ4Ng1|q2>5k6g#zZ-8L*821Tp0%zJtK{IpQ|(l
zNLTho;;<$?<9VpmSaEl~_Dh@Z`QXc6>+A2zINM@(vnGJ32Qa{cYk$D(S`&7^_qUBX
zOk&#uTJXxOeujXA+<hVw24<QbRWDt;%qD^N_k<osL3nBH0XFnmCI00A;L|F2BY#ML
zhSZwV!)b4K_Pj^r=<Nu<hoB`1sXNA))@Aetn&M;Fu57T|KBuIv8)#=fb>UXI5=1w3
z8*5vcoEide<ljH!9QD8P)vX-ZbyxAsLglfx9@?2wjv<|EX0ykYDlT}3i(T75rL-i2
zW&fqwpIl#8R`>q0S|tFtxANfJ=1(i=nF!!`mAa{6S04f;;pbZu{=0f-JIPLPPwSjx
zQrug14^JCGdqHX5)|3dwGMPrW4KB@h!z5v!_nb~2h!_Jr2}&XUIGc$p(OM5qOJXAv
zE2z&1Ab)DvN#JZ~8mQN5-zo(^a3)dV!{!^s<|=fQg{P}K%kB=CGQgp%*V+?sIqWyk
zML}LIHl9iU-^{%YbQ{-oCq973D&i<DI36PtE~{dOLud%n`k)yF)%qlu;R86NAd#Y3
z6@Qo8h%hA6juTmo;;25^e=y(!2})4(5!KaZ-Hk}YiZ)d~%&@MS`fLdau<444Ek&F4
z$>yvrnMu{u-AJ;MW!jwP|GNW#qVv(+?)HDq&Y>s*GxI*~_q+GKd-+YCH6Klny<+Y?
z2QN<7{uhhyoitCCd!1pU@3EQGs@U1$U1J;h`d%%2rHFhQZ!5|kyB#@v-q)9SK}$PZ
z8e%O!{>OilIU2VPJEKkCjTbGWvJU|yRQ(vx+t`>VG&B0`JW_ABZ!eojsJ5OCv3v`0
z%CDzRZPeGNk0ZCz#lpqiZsGR_k>Ki3B#nGWa&mqhYuk=f4se3tBn^-0SElybs2GVF
zH1Xb|_6FYkARslx!m|B*yjU$Xf7ZH!)?Q=l5STckM;fmfx4utjT<B!h=1U8nw$SFi
z$8VL(HU|6jqa#}Gwe<e%DK#=4(mfONed|tlHeO6zvku^-LN@y`y>Y5xt!^Mmocz~|
zCpY%B-e5e8v`Qy>&sY<CqM=z-+Za|qYCXCL&e9uaA`P>a9#fR(JI*QQI(>7OJ&!Hy
z&Nd`?Yk0}rm7i9rl93fgF?Zy&vX@wV^B+YP^#|{aoz<S#?)ITfNKQG0o#S@zDXrT?
z;cSha)I+{LR1nc(Yo;5*sriSnW6?aN-(w%w8_!E09dFBrrKDjXX#8M0)v;CnXt~Wo
z%vt&KvToV)*(Y1Zuxe6=?a--s;|-o?D2j4r{%p2zw_=DdjjY8vs<%1EX$PzD=KSfz
z$Pb@b6*$H+$SVg~gmh2~Ytx%eMSgzZ9$y!Z+&T>V>j#RDXk7#O=AwEikXw^YncL!;
z^9|);hVkm#Seq7!y%@)CXC6A9Qk+n+!-=gsB~5}#HSHU6ZaU=0d^#>Ppe)F^)i`~h
zR%}bOvBGow^mKB<xvuMA$5-;R(+5h*VZEqHuS~woaWZTAeOqu~DX=6fsycbBu$F~$
z+x71DUbeq5Q(o8bTH%@%-fnzl{&M{E#`a;oH*_Q4bf~w@(qgmaGog<0)AQlWcfW_S
zM!`oP!`|T@jspVs7d!n)O_A6mB8SWWP+8ztjGfLdoQyWG=hsqfr_25njBfr&QHmbW
zv{D(_GjvNU_rPV(OapGSNJoF5)tkq;7;|<Ur^8<RqJBn0Q-)MXYR&q`QCh^{=RN8=
zC4Ydc*^&LdcjqI#S2vHJ3wsWoJ12bUMQbN=OIS~{l#%c9?NNRs)+lnn4#$DeEn{n>
zB5{O1q?WwsY~w;s&WFs^7B`XM<OEcP#T>6d!4dyFc3a)Bxvh*fjO!0MmgQ&T;!c)S
zqR&}g$7r;``eM;EqVo$X_N(%9dCPzsaU_BX6^`+^+MpPQ=SV8-DKcRJTcTT6M{%Iq
z=<;d5_2j#snkS23!gQlPur~NZV>#47Ns-BtLiVkYWs|)kp>zj+f7A-5kUNU9Payzu
zPGK$B_Tki{AUMBKje@j1?*=vUnswRW-tw;O)oeqaQ}!v<aLo)e5}4;(Y-^5x#Kw6F
z<Nk73EpaLi0uuz~!ap^xao0SVLu{$r=v5o`k3Xa1osXt0+Oa`#5Uc$R%qT=!u9(So
z^70qD4IG?O(CmlvtNw2cg8ZqO%2tz6-Hu-%gVls<W&PoYTc@!b<;fQ+WF2mv#eZuG
zKa9+pZu|oOR}D4%@v9oS;#{hw!}`kT%2v+Qtvv*bmaV-HJ^P+47C-;XS4IWh{>tl>
zVK-{wIuFT#D9F`g7%IL&Yy;5@527ImZ<zQ)5Y#9=Q@souet)_$T&s3*Bu^iM@G2wK
z)cP-ZdwtuKuPUi*c#&nLo2bQnXTQyiwyvP#q_Sqf?$ld5jP?8hR7h+wL>;^Tkf!NS
z$h6y=i{_3IhdDY|aTuT>yGcta%7CV>v*NSb##DGp3Y>+P&Ko~Iph$;peY^b`)^pl+
z%%_mhq~%1X;TT#}pJzL}nrE$)<v8Z!S@s%N@7wPn2i!@uLqnLBYX?%QmKl5Q#MSAf
zVOzn@nSdeRxRnly2Zz;+wrO`EbkWWpmBOrnPY)Y{zfo^svzF8$Igu&H_NT52nq(&<
zCR~X{gA1Hb9>wC_)FdZ*jJ2!d&uJT_Ugx-u{O)F(dXOKqSkD08rUcXW5qsBJ2G|CW
z5klG8VYLq1_j3QNeE+!Jc&>f7a>BNv^R^P0R;PFJZ5`9<L*B+|c`}kO9?<1Q<^2*b
z6tn9u`UGJUawRCLa={wIc`U<GEu}+)?<8|aC^DiK^epqD!;8k9-_Uxp11WpQ*Nyil
z6WmH^f`!sU8?@ioTOCzDriIyNBdEzESyKvi;NUA~lJhx!U|tD)Q0aE=<-L>HQJ#n1
zK@8hwbH#1#9ef=7BhTj@kLF*U(cl>B5;M(tRorw=%XpqTp@k!znOmJ#v6D2aC{20m
zu2OHd!OoYI%$-a_P8(^gL3<($x9hHmJYXG^g?Ojli}Db{SlQA91^!1z(Ji6(jyG^X
zMU&tqSJm&CNX`_T&0onE`A&}H9G;!_q*t~4N*S`(Hpji00I2Mg&T^qtwzpxi;3;U?
zqlTY%v|~>uHseR^b%P0xlniEHVYS|4?bm!EuQ7+@+|0p#&N+nz&&iWs<V~>@<-ru6
z<Y^swjZ9y3B+H^wr`*posA6M_igdDtA5^t5F51!|x%twF=x6foSYQ<@)|Ugkz(1Q`
z=;FJ~mQFq6;gbzw@W2)8hGcWCAj_dCy-{Q#J83QOcNM(c>2>(DgaCV>+<us;i%>B}
zM9JpYUl0*qmXwif4wYmy^(sp_++hJFe`g}qrOe52{MhlEhFnPV_M>bIX@tpKgUyP1
zOWq?KVn_~TJ+6pOEbnQ(vvHBbA%<f&%GL*!ZL-uOr(1d)6K2b#+1aFy@jEuz>@v<n
zd2t}Mhy$OAFDh%hCdEl<upOK5Sf3+Hr%f1Eye&1RIcD!AzDhE_s$8;%vnbpcN9CTp
z)bsE7p5l9Ytd2yNxlwl7rF><#^tVOH5rFdvGdRFoC3%My@TH@l!%lAR+7{c-2ke)}
z2W)$buJosNW(!lY5<oeFIX%Fx@n-@~>!qw?a`h5#-m8@5ud<sVFw@7i6X7>nkK25m
z{YLivXuA~&t~flC+O8LsmV7Cl_@cgPB>QsftYxLGb;-n(Ir-Fy#6DzdDV&BBDEz?c
z;m=6xaCo)3Y;4okHJx9yj(236zkmc>`QQ7ks92IR4F<xi-W;WiLmX?;tFa@Rv;n!H
zBsiymSIEa6oH8;H<G`7yXG|LhQ0!jM7C9)3$jXDHRElB=Z*bMK#fgqUmS#L!j~7QQ
z?+W^`Q^Ifgj4^M2y9wFJGu{o7FjtU_*Z*KuvlnqE!AQ2374n;9y-Gx=NIum<U@_{`
zgODB?^3wY<+YKQG*EoVcIoa^Osx{=d>%pvcv`LEcJ5l|14u=pz8j7LwJ0X}i^dg{*
z7?j^qj@yWJILyjqJ(_d+q^==(O=I>ML%SDYBhATrg;$=rQ^!UPsX<h)%;~S%DThW$
z(Q+*+mn6qBbojVsMSRs><XUzYj}DGV{yg?yEP!?-%RwgHj7Q3t2!n(yIUc$P=TQ^{
z6FDy;Ar_Lo_TI2{JortVe~qT&y@=gL7Cvi@>8<-@JDq1zFpR8Mb~MlQPC1v3XHFn%
z&20YGC$u>|p=~tm%(RZ<E&~Qa)_#^hW(2dtR$N3F7ZuqCwUMA`J~XQ71D4<N`p+Tb
z(^`l1+v`IfJ|{($fvk!^Hyo55S_=wB8OSYV8p3}}ERG?_$;K?%8)t(?e=iPK%wI(w
z2C21dXD-{mIYf74Z$5GKoB$iK$n8gc84uDqaUnmCj4<mrt%`QAz-5eUgtIwDDNju!
zBzA4oVJEIF2{=Anu&levtOa3m5XVmV*Ri+8wxj`gk&mP`6EP1}d|bChYZPRk@{7AR
z+vcS2$bf3}99P(}!}{=)ZnUOYCY{xu5slz+J!)~};n}HX91!n`bVl(x?Z=cumSZfK
z@iL-Tg7&m@>mPo!VKgclBdHCRT`cHj%aWM7mK$@Ou@Qapc{`PD8+H!rEs+6dOuu0@
zH5LPZvrjT)UyE<iAF+$w+=;Wh%8JQ%T+YT&tK5jsHwN}gyg`du_G+^bpS7`denX=*
z*(Ljo!awBoQs!=i)5jVpz4=%Ve@b_P9%oKBCsV332i?-M$h|2X^J_mR8EJ(4bUWmo
z<LscUU6T0E8a;y3+$ja*-ArE-GNEU!wOm4WKF>PDF<DV+o>J#@DW&@h-Zs^*?d#Bv
zclLZ6=g3fgA#3FaxWPDk#+%EQ^+Z|s9~-<klq>62K{HV=nzbIYds@nJkIzDGC&R1Q
zQhY}7&gmJSaIcnlQAd*QclYH}Etg*Ojx`%I2h@}qKKi-vz7wZx-8!frxY~L(zi(dC
zLSdzBe1;vk`BxV*8+SA}C|-m!5!Y66psI_BQ6%&~2bZ>O39-Dj3fw=2vl<z88bQU3
zSQxZU!kI5*pvb}=Yb2r}Oqi0e6;sh|3mUTEiG(^vqzs&)ym=!-0QEU`Ok2ZFj<x8+
zmLTM<9$%Lc$(tv$Cmkj4g!4x^=EGJ$71Dh;j3V^h`oMmj2@x;``>LcJlO3eS#Az<k
zuN+f0Sg0x#=a=jv&XP*{c?~f#D`d!u<YR#o3<oHu1G=q*QG-E5f+!KWpn4cWtBu~R
z%8>&qL{Z6{G&L^cz7vy@T31?4(3XuJp7-b>QPmuY<ptJ^3~*9G+^GsD;i*OJp(OKH
zProNKV@vX2%3*#SA<{g}W*+^*ko07*SwZ)3Au0y<F-7+*N>YypN1E`{?6o*H;f(1b
z3{ESP#;0H>59_k5drw-<lrd&$UMp`2!T)R^PuT{8$FJq5EK9Lo6d$(~8C5teXQz{4
zz(S9>LC?p1*UwL6<gE9rc2=ASnf;p7&hlyX4Rw4NYCj_NTY4kn@%m0{PEvB3YWXx)
z@P>S**`s<jF!!+tLl#7DW=7xGiF3U@CSzPIF^E4Yk$abLSoa8-tkUE=sryAHbeM%<
zc*C%}!w#lc%x791PT!clU*69mO(j!Ng43p<OVa~g$aog|$(D=4fWE<&c4{Y0jag;s
z*-%<%J-XwGGgt&6O;7P2PjfnD<+N3S6q|C?M5ksWlBNfDWNqwfDVWn{M?tofW44M=
z@4ZSgcv(AYw1oAedeHZHRvEOU;Jef=J}ukGkQJD2*`y7lVvhD^DILlj8)-bNbmpD*
zYYv~)ZQ09qYDPXdZB07&8%kq7ZK7VY*!Avh*YrN*bV_XtzkKo3CnJ}PnZ&4eb$G^p
zAlx@~%ItOynqOGE@FQtk_t@6RrhW2^(fRw2e4^u1j~*LYucfEACcn|~Sj)GxeUZ!4
zKeqLU_8OhmBcrL=#?e%A`oh4G_`Lzvb)U4hglZO-N8UEr`A??4iwqs1*Rr3G_E}4f
zY!Bb79UoY0?%FSPrmcxIGHL0(+dlY;wl4{jul<jc`FsDv?z2t%Mlahl`jz=hkN&}1
zqw>uWd40=Faz@@a@Tuh0m-aW#bS`0Q(OyI&I-2@&($}>U_L}0s{THSVKJxO#b?-m1
z<=I2ouJ`}o;8b5e`wu+);MbL}+u7!+;WfqBHS6f$f6%uC8fT2}or`>Gn?4cP^IPKX
zC-#jFp14028F;fpe<_3mC2JEK^?P@8l?Pu6o!@7iGrFCwhaNf<*qYj+eu3={r`5x0
z?O|0}`(n5DLDoIpvrl?r<Z@Bo$8dZkfkarU)js?^^Uc^l8glG4dwctir5(l>LNBRj
zhR526b1#JscJ_rf>RYAW(az6B_KY8W?3K_k-`cwkbqNpRz+rJXf1znl{)RrV&G?dB
z`b_(0BI`eL>;CKobrT$S&rS!{mu_mk-4oqf$NKjB1{e0~qxzF0SFg^pj?+&Si(NOf
zyU%ZIyfEI)&-{aIU1;pfKG*c5yz~P!{zLT#<&SUHkeSQiYqcjX8z|t=)Kv@|96A3-
zkB!~@*7tY*Q|Cf{WqPZ12z}s0NiWvIzx+hW|Ljd#MZ0gdz?X5cTJ58+S{41ZYN3#7
zW~>)$*|^}F2>cXlZ(7K&Jjg;PPu_7Jg=%*E+<6ovw{ZOch|f^X4kW2?SMU^W+4CdM
z*1$&-ZMzTN*RAe)Ub>t=x29!gbaCwN8@sK0&Bh1#9;CP0t;SKLqV407{Sm9<0`}Uk
zj~Bjm`Ucz9e9UOPVX@{8q*2kIjK5ai7;pQXgZJI@!F1qgBsLnK9sM?rY0$fS4>tU;
zJew{eCDq2>^_H<+N7g89CUQ(Jbi&iy^;2Y);R7Sxto26`<#&FXW@~X6hDrmpy|;aD
z;-`AC?SVCoTjw8+H*PFYZYv+_E?bi~`BQ7lNb5Cm1rd&}$xGxbG&kSKjdv&3H=x|d
zPg%M5ZAI$CafR8AJNw?+$BP?ZLA>Xh_2s)?X}!_=SEyxtwdW`0#G~JLzIOa?*qMia
z_7_N*bi<0bv5B!YftF3yL^k)GQ1O!o@2fm%bqv7ceCE;TQ(ejVZVR=AOK~K-I<Mr;
zrVx2iZ}e_cH;>_5!KNj7O-qsCP|2fuTgwNH$|%dyj`;tE;_S~h<ghD$<00wU7j~c0
za^J~!TFM&vmGZ1L{s7yf%i05v#b-vX<mo-ExK^rsis|}|0`E(mYT&VJaBitL&TZ?9
zPj@(ntWZ(f8kk5opW4`GoMl+By)>nV;q_c7KRGe5z);NO75iHHEH<iN$bVUnoVmfX
z4;f!mZrFBMe_JkW{Y?0(gj`eKEcbqY?3_$x4?g|ed-{e;@W+mQR(`CQ4i7ADwX{vi
zg8tye{PyA=s|eNlg04yXdw;C64jeEEkHaI*;v<bIb=OQP^Z+WDH)jV5_ganL&JQep
zgf%<nE!yaw8?lteQhcq2IMuVrgp<2}8zNWASG5^~vT}tNvjatx`mp{iB4IOqTf>Ai
z{%w6zhf=v_<%gX;<)su0Q*dA=bxJ~cm~Gpd5urF9KLygUIv9%ZjTavZpW|D3vM_A_
z_uXxqq;DXD(zK>OoIr_^jfd3+U*l*#x$b1g_$^-Uor&CdT1JuM^?&{w<`&k9g7bl^
z=pCat-BtXgkxPW=EDfRuA<kJO_u%wL(>OUY!FzGG1Z6l{vscxNyJeigYQjkz!R$^;
zI7oCYUPLlE5VnS#LuRLLyh_#O@4m+MQyqc$Y|5+0idG}G^`q)_Zbw`dP;P=<=ULQi
z*`7B~;qbs7{j7!32z27-R5Ox{+LF@7)UiuvrWnFh-^h2Je&Aqp?7$0Bt|2|r`aK7J
z`|xSdQ~U9A(qZ*ETf_;NHTRB(i(0oG=UJ?SliDBu#mNRb8g)}Kwl?<6S}b|(k=c$@
z8)Hvfwo{BfrSTZ@KJjPwX~l*^(lZ$0+e+hMHk+E>sCRX0ub#Pxm%Xtah^%dXpvc<H
z#s)fVpenhDu1x|MeJI+FV`irxo!<D8Q&~5?aVtUu2nfDu?v0<a9DObJGab&FOE7PF
z!y>Ao14iYoMX=3_XLlFX$9uo7Wi6cO(Ze^7A48%h?OP+;ceh?evbR3_%=Uv?DPH^?
zsnpHdIygAzbi<*>E%ufJjhEnxo4)Tt!+$iUwF4uGFtRJ1_$KfD_M>;Lk<z{T0Q+eC
z(OF|azZYi#VmGaLvshfO9UI8O)7NP3w@z7M>pKS!l!8*$Pa)Hv-IhWoz{g_Gr!MEc
zY07e!JI#_#?58Q#`Uyo@w59=`XRoqT_n|`l7g=ON{b3meXC6qmU~~RW1@&ckdXHWl
zMyRyUep(tcrD?0tJbgOcuz%aNI0xU_c4kIyxZjGzP!!`PGEZOBxjfIevY=;u;tZQq
zjWZoN->IU6K;%aZoM{)KhhNT5W3Nf?)v;7hPcgmzGpqVk4>HWX;vis@j;5Gx#J*{@
z4LY$iI6eeSs&DXgJd6x+Hu%tR@u+sID$aRL-oW{w_(V2l&x}rMl}pxf3&&~NpYPyQ
zX+CnOv9u0BAOpi}ODT^hkS%OfzO3o&+Li4roX$G%b{>zEdQS{Y?&VjlafER`Q_O7V
zYb}FMa03CHZRd>e*ZBX#RAfy<evNfTsgLEw3;EBm-j;?m!$HC=NL%;D)N|wDjodNY
z*nEk-Hh#h~x{P*YH!GKoPyh9=1y&p3?Rt;?qQZ3H)lJ1t#b1=yD9$5dbd?rZvR}0N
z^Nvt%(aNX^p&f<`59cXZ=Yv*qzE#JsM^^EcCUI^Yu1_J*q_Jxzw&I~Id#5$lWq-CK
zkoO5kQo>X-2R=B0E6-*Td}tZhJ+T=pdq)i0Ki4ZoU2+U8MO#;0x2-JF7O&RwV@B3&
z_k~96Z20EpgL6#@QGxHo3g7v-<#>af*+|@sE)%{eElV{1s-_numO&wnnB!$FqW^e2
zYMs@1!#v07By3b)FtJbD5DovVrh4TF&u-H+p>>s%)jH<J1qaJ=>;+VsId3qygFudK
z=Or(Szh}69M*=Q7Y#+rQuI%;qPDGPhZz}6<{GjN_E-yBW#Gau8A|KVls(IY4u0i&S
z^Q9Nbj2LR~%?_77YFP-`$-Gwl<5eoo?rVqbpqy~e=wR)F=u_APd~u*eE9#uimf+Az
ztDbgpixB`RC!dmeZg#wgY9H|~L{oaH`nySy0%c8Mmv^1QV%e+N67M>#2TtVoM0j(F
ztdCkEEF6nDTlV5D970*c|CUl`1zzBY@SvU;VrUb{jQuZLzT@Bj^70+0e@P9H2Y#Uj
zNXt5f!Y&V>j>xaB0rHc7s*uQ+|5pl$tT7JdK5YDwAP#^^n{8HxUoQME9ALkAkz34l
zjNvyn2g3P8zp!wveRMzll3%ZU$Loe&;8TM?Pk=A+=P!8d+$)2yqJWyazj$F&H7*-|
zMF$>8;ngt@a-oZ*V&QpY*Wq_7isl*fYLn+=LyM1eX<NER<5Q}`jpxE@Oyla5YLuKY
zXV~mWa&;1(a!Khx!g)b!Ogl*-$UPlvu(8gXwjB6dx>~X^-Elk*p2l_yMKe1>@Pvy!
z-ri|B1b&0dJHB5&p&;YEFrqbfbfVgM@LXqjN=;2#rEH=s2Tz0pMcMqV?5)I&%u5*g
z*!LLr!mKee8#PDQg6FVD+z5ISI`fR_4ic-(VH2k6WrBo_;k;GNdKyKEMG<pQ0w<K9
z1Ufz`?MUmrci5SYQe(<e{Kq?u;A36N*wg^a0A4-bg!eN#^7rL;8?+;TQZ32h){DBO
zYud5)(ELEghm1-~Nqqwkb4R~oSb9UJ{mSb;RSzFGN@IVhA#2V^R#GMrJLpn<@exbw
zIH-<xgiW9POviwY1%Ba}!N(d#%uLSX?3}=OdptqyKARy2^${vi?O$}B&{)_?rL$pH
z@JMDLYmZn$*d*u)_JGiZ^f1h?TUlSihchg)w6hn-9lEAftv73%7Aqd>Hk^oUHQwAK
zMQ0_^FFGS5Jb6$(DLahCA)g!}s;em92`WPBnrm5vtbKmlEA%-coYhEaql$=COFEVT
z*(17^D(K#*qQPI>1FBI2A<tCwgwDFuY*xFe!(R|LbdNHp1dEbAqGh~2y58a`WOZx@
ze#=63oaj>ff&d4HVC(Q$3th6|=|DFLPexP&h8Xe&k68)Ja2yLR75|BN@F;dF`&Tn$
zb2mDZQNuBP!cO?V&S9^%P}0qus0scghYSw+!m3Bmq9WVLthgAGjaZ(~+c_>OnPzi!
zFt4w|K4UAAZ46C6f`b8{{>NW8B@Bey+q8n(;vFbEQk;)_oFlTI->F6{C4~J0(Y#u+
z-&)0Sh9&5cdhS8w#g`GKF%e?_aorf^N0`~0;!!at70Lh?cN~3#yxxIJ5iYZYb4=Gl
z@(}lT+Ln_HU@tP@Q*6Njg}YC%jNZaEG3fBm;t0dL=Zy8nueDiohSha!5T19B>a=(>
zYb8B*7xo``6HccRAJL>yRYC1mRB@DBO4_UKqB$2DYe-s}2Jckb(HLl;kr|h5=gRr=
z{x#_y&qq{iy|vvsqVG;;k4VFf`g8Le4F{?D8}>(LpArk_<bsxR4yV%1k%Q`EcZ{BS
zj*Tih=Lj62@(vF~675sA))+`<$HpG!Mwokd7+(ws!`HHFvx4xK6Wy9u$lM7TWC+c=
zI2VbYFnT;4whHen3NmNR(*qf=1rL@frbyDEKKDs8=ovv791Ri9sE(T(;;tM-#(x9l
zN7bWp#)D@Co-viPikOf31ggEGIT=qB9(pb0b3Q+Rr>!8>j-V3RLZDa%NK}h*-7EBZ
z{8_9yQ6n6r>>QF3qR=es4Z3*V%IcngIAL;q3%K7eu@gEG_#Y~H1Pe6m8`e&ssJ+)v
zgIS!$Kz>2QU;;iNn&p~zGOJC4^F%GHMZGEbVe{s#_HPMMLo_)hjZ12bX{wY#`nQaF
zOet`0=q{<(@<b(v4ce%CFMFMg*KvXp;(t)piZ9HE<0x)Ep+>zUut6F`aJXYSjuDHn
zjJ7eH*=`$AThq&t;kd3IN7b^-4m)FV6-zrdr`W;lDkZ7GQ#oP)zPG;o-3$`-ZO__<
zFlX2T!wIhWrl8k+B*l;D(Gw|T77`yqIdVD8;%Nkv&5RiH_3><3ZWcMqX(FCO1V^?q
z$1Rk&whGcQrtXZNxx=)0uOz_+jA~*=wCsEJb+U3Km9{K)Bn@&cc$M-_R<inS7*)(N
zf{R&Ev9*NQo0W9L96tQV-k#ysF0WK>xyr25Qa5nMcB)8XIIDY5N>O8)rz0KEhRq-y
zdeRT7p}W%TkQMaoz+pEYHp|imJuT_cV@h$MwAs`H<wgZ{D-uRn_F9wXF~zzU(ExlX
z8QQiE>;)K`Q98nbNA*lv)p|T_CX%|z;(55gO&-PB|Li6oD{aUZL}w=(>+GDwY3M?O
z{VDEQe~;K68p~Ol<BfZpbLXr?*|N8eSUM_yjODaDPy%JN-6=_hSawh!D8RT1c*jI5
zsH-iWz&TmnreqqHl=uZxGNCxEg>tH_b~Sk8O+M3~kd?Bf1WlZo3VL<O5=DYHej`d=
zS%%ts%r5Lr`!sw7$8O`ivBv0~R!!-^v=j8&THzdY+xT61%gByg|HgmzKLx+9t#xzt
zkx{l^pJ5lX+V(7JRx=!<YVJOvWd_<&?Ix>sXluus;cssCwk(1&Otq)MI}tKDcG0(%
z8>P@`Q&23!(3-^nW8R(3MyA2Xl${Q$$&|Yqk~||q#wGQWveoUJlmwHrk&K<sb6-@C
zAXaev^vj+|P+dLt+lurtj(t%M%F=&$gn7-6NvW}8x?eOi#~8CSoe?WFXBazm|2ey0
z*-6d~DdNA2cp+$>&<Y-fuWM>XbqbR1$na(5bx_bI5mke)G91QH*0QJ=AIWyGF$9An
ztk+!RcNp<-wxkE4rDS9*6fKxePBH`MfwaL!E-S+W>p0(o5W8a^G^Lksef|SDVqusW
z6nBY=&JhI%CSrLnx2Sv*$q@t#25i;ueaMt8*%C8aRuVH33T!d46<brx7R?(qymMMt
z8THi}ObM^4YX~A}f`EKps-NRndlS|p%$i^(%d;{4Zsuctune;l)0#_j*5zCOSszk`
zIv7K+Ys3)}4LXts3yiE8Z%~%K1&<}@key}3ypa%rwSqmPvhC9j%Do-R8_qOxyIr*$
z^|<neic;(GjwBoNShi$aEm}jnXRKjSll8QYx@pJ5Onn1^P61?*-#7w6mCk1~MvBkz
ztkvr^56C*GCFsq5W$&-Giy0mA=b>>~8cD&+{|1vzY~ESwKR34Bme!706RIW|M?(5G
zeLuFJt!mE>APkn`EfS($BU~ysX0zv{GN0>s-1epuo~XCqPI!1uoNSPiSss;(lG)?w
z@$B;TASQ?Gmx6JmiDBa#e=2X}PjW<h&B-YxZ;x~x@SYqq4Rf<`j+^23X-ixG$-6Sh
ztQuG~H7O|vScfusRCyL>^fctJlT?jIy;fLX%%*_~E64#7$?8h+AoM_&m*FIgW@-+k
zcCeI=bCi*iyjH7d+G+hH)~zUlGRbF9hRad9j$78txopGngah5IPg_cq+lBm8cAfmi
z^ox0IXV+;7hmRcTWTWtgX-qi*?#ut%34Kdf=vH84V)wSj9sh6oNn>Ap|Nhx+sPZlC
zSM~)?H2uxZA+0<2=4?}kasKVF-1qE^@_hUIAN-*GCxJEXhqdoHGaY;;^gZ*^_$A}2
zv+4eqLKpNO>e`RCNn1MCzlrJ{JHBJ@-E{WBOW{9DUnyO(-)_>@eC+%uN54OXGjqnp
z@c)oU_Gr6aTA%unKCmXWM*rKurlqiSDDaZ@_@mQ-Kasv9@AyZ#w|gp=cAmJUNe89L
zuNg<>!${d;e4)8#cp}#kiQn2SjsA(+GrHqu8lw69aduEOUzX0aY->N<^@36^jLj-b
zaG`8n+SU|0p`5>Bj$|)%{{HFS`;vv3rs<}>!pHYN$G#ZY{DSf9aNpRi6X|vN_1oh!
z{Ntnh<nQRyoq>O3VHW#)yR+|^eS@zRubS)!!~2XUlHVUcD!+U~(VfHTy`4W8o-t5{
ze8)BY%Jk8}FO42F5s6*gb&3DzK@@<9pmfIt{Y&vJ^50o~{AQrndiYtr`wNH=%qFgs
z&dIN+mke0SsUOSX4V&BaE$R=o#q+ls^}d!FJ#9Yx?BV!DJ-zGYTUI*)U7PiNgQG*|
zlIIt%>{Dhp&mtxgLTQr6^p~D^F#A3Aobs^KSG;=emOjw+2~<$s`e0YfC*=G-dmme}
z<?|od|CBMCzig|2a{xOJ*Yu5@P{#h;9{$XQ<c=4NT@!_mCufIlmW}ft*!Nc(_g!du
zVr25*gR!OQ2Yy8sErbV<ed1RZ4gV4a5q>d^7NwP_R_6G{(8aUx0sQYBGoe-M&%cSa
zeJE-7xKWF<910JILslFzIaGG5c}&uJw{*7PE_)H<K(?^MCZ*82`p{j0fo$_MrN6PB
z9~jI}qL{~h>y(RoQj7N>v;Q~s*1w+G$kyp?134rN!p`om9lydCt-=HC_x9RYTo#)<
zj5W$|^9PJWfwipFOb%~}H&r5w>-AF)AI9O3x2zfI6Uvk9R+=@weZ2A6rPQKwp<&nQ
z^yGlP>kK<QW?kB?znQ&sdLwqF7q-W`QJfs*K+g2B*@4~a1dkoJ#!A~-i_I_P4;L?6
zXEtsPAl(hlcx?^DPoxfZd;_lb;;uu+)~4R#69=Ww&!0`dC11`T<6HF2-#R_KFg~lr
z&o10rEJwQb+t=b>-uR016UHH`dzKh-|3@N+oh8mU-yDB4dR6D&&YzRoSX;ax!B4w4
zl3Z+`9r#nF;Z`cN`I!cum{t!dUrFza^Se*8aIxVV67onDJGw6FMGKDR^rQQbk138f
zjO~lv>9%{E#lCn*-Okt>Q=X6PmJoK?9e&f<Yke`b`2pSRy`@AZu569B>4%_rQ9N9^
z%!&<sao6($4rLq)m!y}<+gN`-zBzSWmM2(S3Pn&5nn@j0w=`hZ?2u8~!Y~ITH_!X?
zUoG+(<!GTRKafA1NXHwUl5Hs$j(#)Id#bt5zQ)?0k33iSbKZXQFFx)slUMVB{93&Y
z)H4#?6p6iNbq>In%s<9jpI5dgjLi=ixgV#~o4tBls_};0h`ncxu(=LO6Kc2Kyvaby
zczxh4t8Ked`L14!IoNoCf)u3?FG<gywX$!^jpbf=uO%dxI;g#LB^`$Q_{>Mx=s`_r
zlacf1Nqst|R7R}LU8B}dcc&XimHqY?^|`<<gl>+?!_B8UDks>;<N({kq%fh#_7}hZ
z<f_;U#V<DVzWLKyxTNGx$2Y(I^wY1D4gEQJiIv0JP5J3=rv30q*t3b&-D80#EHRX1
zyJl01S(8l<;=E2@dPW;>*sqI$ug7nt=)A_^qS%o>tjpO;`Y>w?tuq>rvPYjVZ21)X
zU?f-^%-KGKaJCl=t^MM**|h$Ep*K%Azr6j+;Zyg;o?!6mBLUGS4Jp0$#}OPE>$()5
zm5wW=_37Dx<4Vrg_>lS~1cCbVsP<xXt0q!w&B)HIHIVNaW?EP}%TRfK?CnA!-<x(~
zi`$C3UoBrlv?X_~tcUN;7q#$n@-QFqGt@P|*(CQ3oeq8Z2hktL<92vd-V{edtZQ)R
ze=ri8X9Kz9TfN5z0!hm7cHiViw$_SFIPH9uUeH6ImE+HAI0+WGq*21Wfor=?$zZ=U
zk}4Ip8*O^q?@n&#J(P~ilWM$}H@|N2kIVn<uk`6=R4M5#s(n)%<Gn1o@UY$%0HvgH
z2EoiF3yDw;S(ucGsa>dN5pjA&B$xUj(?du)_ApM&;B1dM%#41{a0;W4Kh01n<;=E7
zE>hU4qjtoLw~9QH8{v;mH=qBB&5g$U<Zfb1V{4)7bn0h~Vr)0F3Rlge3@OkI)W*b_
zlI?oD7|SKg_v#N$HB{zxkm~RjJ>o|hl>1_5d&SLHOmiHZ+_)BNoyxZ9-#MIpAl;{n
zNQiY)-`%z=pj@-Gb4um7u1G~gn^4~@rj^FM>=Zlfd|Vl_!lOp=Ej=~1U2iY4f*CqC
zAXO6jn`)`ItGKaXdK)3E;u&*bclefK9Beqbdm?N0@G0%UelF%lP&HhW@;KhM`HJ%#
zzm_l{IIPV_^M~i#^(#H6nKd^0^wTW-<9~N<E?`@HQth-bG34mORvP(v3F+j1z-BwX
zkFZWmbiTll4NO7l8{NEYbf!8Ido4Z_*{k&GtGN2$vvlsNZ96hr;W*g)CmZh9r8QEe
z{ZxluY~}-RO{tH|1K0)?c?{HsLoSe;(xiC~Xyc`|Oj2U=dSln6MY=bp7WG&4y$Kyh
z;-pR5tJuL3?ljC;aa0+Ppak$zktd~>jRSW~EUW|6cuIQ7-c~r-uw^n{L`9{~<ooQR
z_Tj>+fZ~M>1}EXL;4~F=si?LMN@gqf1i5<AKCL6Gm2GsC&0g%E!j54dDBiiBuiZYP
zY7>t0$oO7G@hY!c`Rqn{N+<`BiZ2FjxjnxNafR4ISF4p|HqKgeGns-neSRE8fOV0>
zlaa}Ku(O7ZJKmE9BFOo(*^u`TT;<pz8O)x@8*_PKoziWZy*Gb$BYKw&qaTKDG<OF>
z-9jwT$35G)0AI)I;IN94wD4=#Y)Tcj=>luBGM<y_tG#&*<@k^}L2XM#MO8rn&XGps
z#uPkezDGnsQxItARxNF(18aZMlet6S90{|sijr-^c4K%J7FKJL(9Z=&%3kj^cb2xI
z1gqla-dsnirBD|mcew*a!<E-Uq1{dnnY$2Vh?_W#;by!l9dd0A%JmsiUelq<JqSB=
z&{>ZZs>W)M4g-R2^Z@CJoW~44Z2p}^r(LL*qj79gKuWUS)EL`EHBV}GNy_b`OGmj5
z$ZLsLw4#L5A*n2bVS)Gr42uqw2!{s^hDFb*07WQt>ovQ6Jfu{(K%s^;$aIDO@W`S(
z^EvPTjYmCx^(hTRP=0xo;Gc8U<5xEFOF|8Or{6<Pv44?E-t)e9WkI^AwxM~1C>I5x
zq1y0C*YoE73Yz#@5KzW;#id2P)lb-d?f&70H&ArJ&3$$KPm>wL@{MIR?@mV$5+?Ew
zag8(haZ??w9SS_^xnUD|$3Je1ExKfQ1M8Ts-+@)EN5N|Sq$MDMd}ee&Y_^cvXvE>d
zNYqy_`8{GZ?`eVSSb_7w=@O$S26<R6FtJN>Y~z~a?a23f?PM^k{~iyDT3-0<t>Z@p
zxCt?xfY<K{a1T=AxZ^k}!Hhd(?u4^YRghn3E0R=*L2tL(2wwxZGUySE=rp(+PUkJA
ze^thFzSAh-J58f;Y~a{et7bPUDx6NX*mX|nZ7>2NGc+e_pDr97X&j&Q+L18_`#m}H
z<gE?L>m2LxjOKL=Cz?%7pm=nDHl?V7`c>BD&7@T1m=QDqwY(iaQjjAnd(@lp2pbsU
zJJ?gYD(Wq0t5nVJc+9jFwNV1tkFbFUZkQG^+Nqy3<9X49k0dx~V_##?E7(Smd##?o
zjd_JFI#R>`-G`9Y$?v}C!-h_PC4|5bN@>^7>I6L*Z$^Z>-hoTj!QK+|4Ae(`$Uh}a
z8V+qs7laL<keJ~~$TsfTTF}FTmMxx`#6EcB8Uyx(uj~+oDAIce9WP=eJ^`abhzc=*
zF)yQ*yr?<i#<hrC(3N0!dHhdHQ5%s7-9w;9`VDjhitEYJ=p@5-EF!}wa07>m9rb0L
zQH5)4>EFL5NE|z<WxVCkRH8I1lF+v10CZ>`)xS~g9ppOc_4`UuR0Y*0Jq%F_+~Z}O
z3lM~?ghWXcJ`r*tKrW$jD?%PP5@ebgG@IhWiI+vVY~bHj*=pe{|8U1nJqp)QlwJ`s
zj-z=|J_9or1vBQ&5}4pB70@(BdPg(h(1-*xfjN{3=<&85V>k+LA#0d}lwdAM4Y;E`
zL2S6xHenz~ZAXH$IHUP+ibVP<j@)$+KH*)zKJ#MGqoQ$>ddPT>7y>G;_<ev$6a%SU
z1VQ-W1qve7#%B^~;5JYy0Fc15mjI8nVQ54#=rg_imoL5>Q$TCDf?h?T!CBZaEb7o&
zS+@md3mFgHHzY>`77^0Zja~<iEgFjZD*Vjo2O|z@h(7_k_!HC8yl7hxKGgVb0sgou
zZQ;NARULtVS~cYHM@SP1=hUbMD4XUEk&3}rhY#|Br1Az4juEWPJ;%{$5NCP2JhmHR
z#gv4;Kk~UDQJVZaE&>wf4L>%%<||=_&)^LoJ+OS4co@#P>gVg9`&sQq73oCSxEM{a
zei2AHeZZS8<g3r%!#mogCvcg2zV>T6{XxTYAE-V~tuTBI-f_tb-_l2SGS%-9_@MXP
zZs`A&^EAKkW%}x0=KAzKi2VHgWxk`opTArC3<!YftHWG=<S+jX_`@%fTv35V-NKzN
zJcH+ODg=Saq@w{88sM>k;~qH9G{M(G|IdFfM0F3))$j|CM|JG25pq6ICQb-6X!lHk
zOEorQiD>exND2pK06IF^fFTStguNJq-Ug_4`L^VV1TYf1>HN|+bK*bQECL*V=ldn7
zCZs`yt+-rl6P|zWT1iZV-Rr;oSN>!HO-h)If3J$k2zs0*BXnU^3&<t&1iF9Xt`MAR
z049F<yFdnRL+QU)0w|&>7Ze+C)*M4~07PMZ_g#d<pa;+V9IRb#`~^Jza~^$t^ScNt
zkiSt9&oHH7Dxfz4Oa?u|07j-n%yo_)`)5A-VHGZFG^7AF(Tfe!82zi-EI|$yDcXtx
zazchCFaM^B$qV;dL<e)#$^W0ediX!B`u`PffXBbgb^Uj@L)w^_`8zJt&kzFV+<7NO
zqC$wk$vU`w;Z+doJ0Fb7vdG>Tsh%Oe{pkPxUl`@%>dln-KFvz8bbORu)^xEu&%5>)
z=6RQI(rGx0dhPa=hU{p=RI?&Av{}EsulB-KHa{M}Sw{X}>v3*J_)GajgdahUViXZ|
z<Ta}C-iFOtwc$DKc-MQi^?~Cm5+v})M)bY}av}fAcH(KXTGJXFIc^tA-@Ol}H-sRH
zFM%LYeF;prLN>Zzquv-$;5Wbybp|v^W;*}V$Ah40-Maq3m!m1UHGVnO$y!D8UN*<i
z&vXBLAsSJ5u%sMm=ujF$PS-^>6)^Pp(G<Hk-u1M#f!|x^3z0&?=Pda6nCX)Wp7*I^
z4Z~7I{!MMSW7XO$w~Ae_S&8|=|6!wZTFTHZcbMhYTaOGz2N|fUcEy-zA}KlIM7cq`
zlpD-f26-i!&$&N<9ImK5$Z!cI9!n$!?Fv3}&SC2Tc(@n?K{HwQ_1l%ff{A+&oH?6B
zfO|X2L{_dO=W~f6&P$GeD37;azyH_KsaSo4+Q2TAK^7BBPDNxG&mfN>NhYo;JK#1R
zU^26ZFuH>2<irx#g6GJf!39<3-fl|H$A%VS$%S%E9)u*Svlzx;GK{RBm2#+$>+_2k
z!{-m(fj;X)0HvT?79GOe=W{~~PASLaCS(Gv_TUZ?kDwX!G*~uWDOP<M<HiK=vdLpU
zR(4`c5jiZL+N=GT5Qa#@PjZKqApF1jm+x8GH68$4%SifC0elA&6~d5H#X%LwegGYB
z0A@pW$*lNL(564n0f0J~srM*jLj|X@n#WdGL^J2h0e*D=;lBF=OxU@hd9xJ5?nznk
z`Ik<W`hnc~h10EQDJH^iQK$?p<m@391KxQ3eoU4zSJuRa00<rv$*{<~b|s$h*E%8O
z$qG;<CjdW;(cv{(!Rw;H0EJjnB9Tmh1fup*V(SVc3vIZhz--_;W)GEPO46ms8Xgdn
z6|o~k%q8U2Ic77^n$M{Z0Dv|HUdrJW6PQlKk}i;zN!2f+N0XO{7IK(Ffk<fS6^=IR
z6O4*r35I$>)U}O(JBuYT|78GR5rSEwT?RUd4V5c{W!wZd+y;o)foc$u&4zd`VY4QY
z-d-lun2g~Q+A0Y<VK;%md31mGyZTqKq)W^0Tb#SP!e6ICAlT(rAS5@Kpn<TmiH*Wo
z@z?Mi!vqO{7<d67P6Ab=jq56efzrS$WsJW91eIe$43k84f$OJ!>L=9HE>Hoe6*DMT
zh#wXzO<0gRbh!^;v?ee~Ge=Vkz~&$a3YPCj8AgV&;q@dh=ZJO{(Aw?$U^N;jK_)ho
z$kF}Pj&ogosGr>?1)?T26dfw$h5#<W3j=bm`fSk(5MBbDhw?y0KR0n3R9^*#ODJL#
z+zbLrfRG6+kV|!B5Htzbcmku~EGp95`=@;1vSmmRXJQ<fY8jL5N4^W1MP067h=Pf3
z`xlsrsYaV{&N@k(uIK`ka32^dV@QMZoPlD1t2!wWtzv=%UsfvRY?N?=_RlRn_%)Kp
z%L8E45X1@y#E%DSQehbaE)g(R0ijlCpmNh-9>W6%VE;H>e&7)lM{KVo6D3wMb08<&
zt<Qlv!vymz2VmzQU!V*yrhIPc;%|~oQoG=EaM9tykb?_AE<~7h!ozJMEIR=qHUtr4
zmrIa9%lDyl0PB7b1a6lxz9tM9!yxHV1sBAsh}mGI^EsKApZQUGLQ$5qJYKF3gG4<j
zb&yyHWZ^&_M*(vBRG%@v5o6FuP3Qyt6~LiRlypgrEFfq_5MP<zX&QvcO#mqZeX2`K
zaG+^2f0F`WK#Dab0944Sr_;-$fSX2i1tm3u8My;+yQ>Xl89|JgL4ZskDq1OMi4}1{
zmtg>`BKl>(vW^wvQerYJQe9p|TGBQNbg+yLAb{}Uic{wPL71qbobE*##vB`5Fe{KS
zP}TrsohtD-A!D#W9aoYIz*Q_+Ale5Ast-YzxKs~h0LlxMp+W@+1sMa>ANnuvrkO8;
z0)T)kgbkJ<3OGi+d;{YLm7uGpr0wL`YL**h)E?1Z9X!M!CQ&C~SfJmSt^jA1+Xy2|
z1tV=50+Qw{O?X!XfSlaYAN=4Q(h7h9E0cu6l<)((thNC12dWt`&~IbVr3yHJ6GWEn
z6PGUCZe)89`Uui!h}4G5LC`GKfw(G3Fdbma$;nMN=+ozX`UjpB_>77!K2dBBMgy8~
zZHL-0pxntq5{XM8a-rmNA`w48u}pJ>5r6_51hI@{DY2$ONNu{fI|gJw04#|?fTwcK
zwbCjg(26#eHtiruRKHwf0-qgp<diD%5X1(q>TO6p1|5jzZAhKL`J9rFn=sG1h6V;n
z_JhHOY-%7UE0_uhv-UdhDWVA&YM_fGXbAEG?_bZ4*SmNBXC#U_gvAgy!9&aUi1cWl
zv6^0K8e%ySLICEZ`%Dyu8XjOVNPQcC1ou)?B=*RGfQ$GEyb*<ZC8~k2fTaPOieJC-
z$E29*UAY1a*vIjB%$Mx86&g%%nZU#VWw1#T!!E-rK5FxHg(6_m&vH<L00@YSuvJ5-
zUj%=^iot#K=r;VX{`wuAV;UryF?A?FyhwH(p`kuHx<}K5{nB56?t-;q17PsG)cYXH
zBta$S$OJ3%98(7Kyy`kYD}Vv?2Velhok4yKCi=m>=;~+py&EH`_u~p4x2YkFz%Dr@
zfP=*L?a9<J4#j9E=gYa(a7tsf<hDSwGlf`_Jp^+DT3E4(3n5DDt~*!7#cT||f=9q0
z@G!iBsN3=YpoO6-04<@v3}}$Wfk6Y3brvPF73=}B2lIowkb0Pm3F@9`9@vhF03uXV
zGU1fLLf}pMRUIGnn}~@g^Ce6TAa;c4(hq+hROH^KUokKyNY=?gijW*Dn>D_w%Q_Om
zc%%uZ0YnH7SP4EzplbU_E=0Tw0*0n8SCY0FgE$4As`AC1J>wiQS_W`kEwl8%EAONP
z;EHT>5tb|#0Cd&HhR0&yM3_bpjETVn;kz~{yaS}s7bQOgwE`(ERtReNR~s55&CWnS
zu+bo)!RayFq-U1?)jG`Qw(6$8O|!quqarjTsf_wXyaX~dbE`@Af(yw^tKEbeCBaFH
zIU?Rd4k@fEq(*Nq%3Kzc0ap-VG64eU$5S+huUxCQLX80%WG*OJP9zJZstjKiNEjT(
zfR1Q&1{IOO99aoVn>v_az|sTCYRsSlivW@jHgm0g7*Rx`F<(Ui{3}gE<(vZI;J<gV
zK1Fm-G(;13IRHyX8qzZT!UK+_QYD#SAdOOgp^A5U+ht%_rh_(v#EmsIF%e=iS_cpT
zxCGJzR}3vcg%MzuKKExU6%%0|^8>TFveq`M&;kEchfi|M&zO=x^Fs;lkSz~WrPhOs
zL)ec9sWBKKSj}L);$H!Nkd@zEWe{NJD+vaJ2juZT$}7kpu!FnFwO^s0A@7=MG`I|2
zh!K$SJmehNO3*r>14sf0Uw4p1A~X_!5Yj$5AH&kPTyX_RT}EIWWaVH*1tS2qkXc6K
z{I_0s_ewEDEGGJyO<n*n3?9K%LlU))+YpdB!k~;}hgime@@h;@<N-97`{%K^2B9TD
z5M<WWG=d9d1h60<Kwwc?B}9Fne;c8Y`UQYMV3%XCU&`fj4z^6Cj>a0EqqLC3G6J}a
zC7C}#5~hx766BzU=nzdlmuOl|maR+Y_3?=`JWvT}AL1UXz9B3Ko$KG6eun{#S(q3}
z8JR}_P}0h<PpXsvPQnO92I8O3DQqy`4}-I|wg(EyHfCs%=-(AXF&G&DKwVcr>OvB5
z0c3<3FhCY#arXTEJC-soEus&o8kkxOIoLYb2|-sCOmJ9N&1TZ-FpX=16)jcoyS5sv
zF~}fDV4rJzV2rmd7#GE4)hFPCz=Edif{A~6@Hgss0I(q`8Lj+?Vqq6LBz~4}yS4|}
zyjXvO5a9zLa<7{vGy#ZF&?ao#icL!lV#pc<iG%=FR6j%yzUUxXwERD<lmj9t5Gu2R
z#V>UZYEBTGYCkoCfU1BzVQ`3{J1C$*grI2<?ieAlT{^{L4{$DkScsO;0QFTv2BFIh
zADJ%Sh{DNce6>795?5s6&@h0A91b|tuuvl=ng+NYz`+nJ(401e5(pbiSs#Qu20!Fk
z4hwwFO~^~!r=RK*;75R!<QK@rhN^{ME;d+j;0f6Cl{?8BRllMl9xFlX!p49ql0}+G
z4c=fYa4Z0Um2Ei&q6QG^a?_=ESpEb==ya$q5mZ!nGeF`qfrbQTfHmtY!=m8-<=<l1
zw{;I`Rzew2kpnRTo=vs_f5<YdiL0?Rz|<2>cru3t3l_*|vj!*hPJ$h#A8bfK3#fta
zTVdEh?!&ME+hbKQU$JqNh+cQN^ZA$Fv%<{)J&NXG-N4`k+e1dW&PT+rT_6E>SWSs#
zoaDpWKt#qQ+^G(Mm=>dig8~Z+^Z+M;KpMJw7lsGaJA=(bb{}k$1ON@ScKGkTE36}G
zohDkMpa95@6ukRWZG@tfKrsUx3;lL~*~FNtcQ6AIn~>ZXA(lraSoE}%uH7X<1)|-y
zpmXH}Sk7_!Kd=J%E}=4$C=COH=B<dNmFpo0a%EvB2;2(L2`2m=%W*aW3D)Y+8hHQ(
z_UAnGpi4K^&Z%M2DiAcTdQ2{uWfKkW{PsInDVUp|G$R3rRuSO9syK{-?9c`*u_SZb
zSSXcEFqp3{?=W}B2o_7u_mg3lz*wL)>kL9f4K0v|C>mP8@K*~EoqeJA0L-`Po`46`
zLs&to+BqL7hug$Q7BmT}q4|ok8VUhq1`l6dQo76~(9#-I1J&%xYjjd=orE=T5C1V#
z>fn684X-fp-uK{LD;CGDLl*=B(*XJovX)i~?p19BoPsex=PpzdO$qp}pix2UHJvPC
zIfE|9T*wVBaIzsuC@+&9^bDzOkP>7R7!iISBFvoc^FLd?g8Q+2HKR?dX}sj;r0K7q
zJ%9js28Y20YQh>GCbAE*w=N4|e!_c;_h3AN$(1B<j1k<HgCfRnLJsG!iUS}D4)uTs
z4u9`1^tg-(*rVi@qy-Jg184??FB36H30;&i1vEh}XXxabkRvK2&IM011Qx*hkRR^w
zm*D`eMvGA~2ksn9l!4;GGQgNydgfjT*%icq2O%h!9}R$<30hS+)CNKXO;)H0MgzGh
zO>kCL;pxr-f(9=`cPgv<6D7!_DmJi&sPO~wiY((8+Yk(C45f_Mef(cvToLSdl`F(H
zEtoOi7!)Xm0C858=nxImeH2VGl&HYB1*k!&)>jL78`QcQa4di)N<>RQK7d^ZB(Vf|
zjo1}4#j(!l()%vdQGox!YY<hW^<eCSqZTm8N*$PWs;fE<VCUJ%g%WrRZmVkhXn<e<
ziiMUTV3Xn+O1RqL9pVf`OMu5(3(|@c4I>VJ*mwsrTrVIIgNq746IPiEiy9<IvXO^l
zHH7X0V4c7$A+(m~O3Vps2znEY4gE|)8|Dgls}2m(b3zFa!!(Byv}_{AdVP~Ox=fXT
z2w++^1;_^AJSV%-sR}RxHhx4<U4`h`U2%|Ns*4AARR`UahvDu3SvHt+S$05akYvu0
zTAhdTbS+-ui|haW#g%IZ;0qA-<J|<tPy$YCkOVAhWJSv}P#w9pF;y~Wpa*di;HZw2
zR0~Xh@FqwKz;K`n$(*X)$3zGeG12KqA0+7r&S;^Jd0?be+o0tesTxMA9?~R_E~><V
z`POIbG9np|HW(Y`4YW|rECV93L?<mFul5fiUuadqfyr@UQ3hmzYM@{Vtr!f(_WGaP
z$?ARM5sbty!czq#kVlu{30!qefKFW?5H{dj;6UN>sEDi}fN-Y_oz4kV@N87O76cLv
z_zIw>7yBXQ5?J^zedwc*M9bY{Z~*aOndB|j;s`Xk7DgQb?z$i*+e3(ZniUKL0*HoI
zn;xqUj%+<(8x{&RRTUf%-PKO2Lo|Ur2QAnY_@iigOMm~qmDB)8xyBB>gP0WKIcleR
zxoiP~2cQ5&PL#q*plw%r)Wiokf^4lQgi8*VUNS*W)ptBV>JX5QDI&+8U>))-po^uS
zKvWXH)GqQ1LovmOP{3Sh4vPiMuTGpb1;s>+h%6d%#=^nqDxaEiCrJhuwUVIqbOk71
zUO@;nMv)ei4D5|=Awl`a()GTHU<6DBU6PDRz^tJ~6eyN{YEyMZK0wE8P&TNG)m;Tx
zdw@(yW5C?S%Wz;OVhTbCE2s%HNKauc3u;&mqQJJm#ZS<di~1Nach_Gg0-&S~Dj<sL
z<vu~wLSZF<5XwX>!CT}S!c}BrdKeNp%WWt_vU%X_>aPbt+~LtOj$;)KOu2$dxc)%$
z9SCrV2))o6idy6FUalM-0nkL42fD$5)j~_;8nt4;c-{m9K`6rLLi^B#w-vfOI07Gs
zQ2{oGqOw6u05-vQ?J({yg8}%1aDsVFE1>y`O9XhRM$-T_b;bJ2Fp?1Gu|aSEG~9Z%
zbrcLgzyTH#v<&RD62?i|3Zk?s<lPk#Ba?5a0JV*P5ih|2%PpN+gjrh01xXro16YWF
z9a)mM2Z+aT*ENg)&a$gM!I{_wTkU~NOc{&|3l>bL3_?iK0P2oCGKqjkP<sKrmth6N
zC-_<sn--RP2b@7EKtqLi9(F+qqTUtKbpb>yKo_mTu;QMFr`ku{PYSdKDxxNg6Uu%b
z(iOCfC?I~jL#fdWCV`&7jpT91eF)N$L)O7p8htAz6)i>Jq~v8DgOdX`D{KjXyUuh(
zljseB7zSH+HB1DktQsUqP7-OD4rlHyGq&1YOx+$PkuC{9f(8f=i~%$1zBc#UIzBK}
z*YqXU0Q_&O|GE`J{3l`$2AnOxJ9G|ng&{yvZNlY#__WAf=YWP?ixwKoy-V7PQ0hP=
zlXr#I;DADI=?i~Y9{~QRenG)>1KtI!EfB?nJm&5r(7nJaP)0!(a0px}v`ipySDPTJ
zz$4%b`mz9@JIEH0s0nm%F3AsYCz>CcCoYf43AoCZ{(jRtAVE=M(o29}iNd$!9IK9Y
z8KUHtV-Q8O<0gUV7@?#3Odaotg#(blbrgmQ0AIi&f}W^}SVAWhCxx5fwZ#&pL@g|>
z{SyLI9U`t-1}?D?Jf{~R%Bm~mS|e56=}J`CLgZZoYB6`;@?r)q5O67(gt@^2Bkh53
z53pYwB{{ws9DZ1&!^Mx?GtiLN-uyLSdYMs{c@(Q)aHtzCdB;rg9q11dI|=_@e<FuL
z`BsLOK@QcqLL?=y*d|#5R$gWzi~)>@-5l^)fteBT5rObMJ3N3-9S{&$q*z?lLENao
zpA2tCjkd55M5iQDX_rz(P6D@3KDQT~E)#-Bz*`WD<nDzfLX-)~RV6KmCE%M@Dex^0
z6<~=IZC_7)a)psk%G2dEhZx<prLe@tw(Ppt1L+bEVG)q%x2sDg+^PwsDruYW4@0CP
z)QYG~6ZY4TYOTEwk^&^7Ft(Z)#UPtRY^r$Zb)aw=4(>$2@9qd3?6xWc-*i<01zH7z
zLNtRYO^TVqDT1p$Kq5$5Dy=p_x3G4|_Qt#Q{vjk_t3kz(aYYcS(95sc?};w=4@?pi
z0B;C9=nh~49$z$rt2zV<Yk<oTt$?gUbc5W^G|AicJ8%i13V#R;rUl{~Oa?&k)kqSy
z8p$dw)?hk=Y!M!;lH2v(hsh*dCJFigpc20jBSJAQ4}yd{fC+?S@e5-CU@f5+I2o2Z
zaS5tFUqJwq7KH#cjFozf5=~;Ju(E(G8zL8Qb8o-?tvhe`PvXSw+bOw96qLoO6?9Z%
zPZ|P%!CdWtNkGMrd5FL2WCw9Y!5s)Y01`^OkP{)Tz`fORk~o8Q1iBUg?g|D2k&A2T
z{)H8uAgp#sE|T^FYq?7|iUZyDtddxFEl$@H0?moVHpWn;e9R55zgW@+UzRG^dRD?d
z@MZY{N+3v}X*^ekEI?=+<dnPi-S?~<0W2?y?|{3Snh?u!AZ6Y`+JH9j1YaU3a~>#7
zR83IAdL1KVJpy3>1wj+`G_`?YE|VvTXcsA1=Ysm+afDY44Pd9s7Ful82?IPp*egQ?
z@G^F^z&aofS*CLe=fix7t<GVW9TxQoZjuUFUX4>POn?ArYQn2I@B!Ro0DD!Bp=Hpg
zNUGZ1OjH3gxqguk{pPO&ShvXo&%nh4O-j9C^40Kl4X@NcytPoH^Zk$pHvF^@1GuW4
zK+Hf@nqY9n2g^o;W+$qukrjFY?E_X=!NNTW+b7|QyQPZ<S4b;x1s;PogawF=fEWY7
zLJVE)0@%ZF`#GE?m?oG2x)4|<IMmcB`Jm7UJf;98wq};#kA~)`!-?7xVgxvdnF>?L
z`RrW3M_;l2qL2tw7*@FRu>@k^CV4hoZmv(%WmC)m3J!wTmxI9u^@S*Ub&%wQ#T+mN
z2mvUEGRPRrLc*lZV<M0db@j6=+c^V|Q5(KbKkQwp#;VlAKzAStxV->g;%WD)QVzg@
zFJT=ZWC$Gs#a<@2A-b#gCA$kk%#-6Db})kINT@)%)p!XIBV`5)Et!CMf)z#?XwSWN
z=GRvag>X+C2}8`)eZOE`5QU=c605*@i^w?~xR?>9z054+-hc*4(l#v!;31on3$-5h
zCb&Z*17JC9`Gt2H5CrO%?tkkYy2RBLpgeG!>pTad+^a@|<j+R9$sxxcyocE8iEEhz
zVXj8u5GymF0>ePe4tJ|>VjYX&L4ITX0Wc0B>MnwC{_@W;sydTWBuNAj1GxBsX8_Bs
z71Zg@fDA=W{#RHv6+Gp`qg6m-*PbhufF=Lx3by`0^nfT3cCN}a;$V<2$O-}xfxl9j
zJa+t*O?N`U)rSDFN79+ti};zg!!4s4do#$6g&~8L9L!Cd5a6pXFJRx2!R?0+i|jw>
zS#(W`tY)nf$J3mnSU!Ug5)=qS(@W>h5ZBlH2M1yn#GWMX$c%Kin7I0(It}O#fC-jk
zj<!ESPmxHxy<eB)5b12tELl$w?r7a{`KQ_k=~;-fGByceiwC@qKH<N<cjXZ9F6IG&
zhdE+3Ldz`TXjh=sh#u?=K;j7izg!_<TEWD?zx7}hR*U`Uvx#K-AUyr<Uc4G4@G^!3
zJ(_?56R{>I&E~wm--l7x!9d%Nsb^lo!rqNz!FN>^5;byixnZ#2#}2OwOy#nP=;|`2
zfC|_w;9A@*0fG+p8c;ByN(nT2niW``5C-TGD*=YDFReI&;hO3M2rR$KAT_M^uo<Ry
zx#I*eL4c6k6C2?Xg~k%Svb-3jt)c{a3gN_t7U&1Q1A4u-TBSE-P$Z-uI1!2mlB`7H
ze(7U>NcgLR0=fl)AHZgqiM#g;K0#^+u&>J?vL^^&3JFzmenHcbyLeeWfOJ6?5R?_0
z0&f)v?lMf972E^mfd(*L5eUVG8vIG>7%+W()4Ns>D0vAmD~NfA=o}UT5i9txHePqm
zun)lF;E+-YOp72>l|wNV{7@%NVkHS50E4rL1p93hjC2?qgs7Y^gK(gVn_x>X4OQ@7
z9UwwfB-je1#ujqGi>u8@Q`RL78G$B`g80lbDOv0~SeB9`-{5`p5r}d_^Erg)Ztr}8
z_M+~Y31Lo)O4!tXm^J?&dv6~d$9>-S&aOuCDrRk9v_{4VO79Mb&=9035{4C&&2@GL
zv)}++5+Ka@;P~*w1PswIYuP3x`|vux)z0F#<U(8uB2DM==Bfz^uNBypV~b`SHuY_^
z)Ix$R*b)`RReRi8WN4dpotTsr6>*gKexBJEf@$wxz5m>E?g}Ca%*^lQdHFuCzrpz!
zNYI)-f++G_;vz=Qu5`V&tTYaw&e&4n@KG^Px<(%w`qO}E*2864Asw-z0#&l&EU(#^
z0I6|c!KkGy>AdV3Knllf<tKl26QiU7GBP@N^7z8?wNzL3$W+&b9J({fXbqPc3ywnz
zrvwj5^%JA)1|EuFAv4Ru5*d-p=t#?;2->-T?P3>!9I+q`eb;~Ri`6+y5gN3h1{xy8
z^2NsaG>C;|!CG(?um-U4z{FE%_60`IW=Pl8=^^sV{FGbke8iR@XBm3L1#Kau$n(m3
z{$_RRPAWKj5rv}5td<2Zd6Sm)i%2obfEr^o5k?@pVJ{e5SX|swtK!0fml)~Dq}Er@
zdRV-uf0!L#t}6WQOmOW_V-T$=3rtWq38*#+$P&&tNCB%GGl*qn7;)_A@9at}Ml}bP
z*tiadkcUvQ?q&QSlvZ@Ic@_EyiLyBO#En@pcWsoAf|YBR#BXT{BpMT?Kn4D!RYZ(y
zt-gxpLWB=O9kvIU0(ckzX##8JNb1~&*DOT5J`k1ee-YY-USqw*9?~<oEN!=hqB@AV
z^4(Lb{e5v@5N<F=((g+MhRAF~7C>BGD4`^$wr0^J=x2JqnrkF}L}F`bJ_|q+A&ALo
z;#MHdv%--m?Gh}C=~+fOk%^HDv|BVk!g4kXf?yr9Q5cH91vLa&o4&HJmBsMqcn<Wy
zTKiQzmX;|eT_xno_&KsPG(Z+*nx>tP;wm<Z&`=`P$tNRG@7Z%(wAscogdsSBdxJ%S
zVTsYOr3iI{6w%zochZ~;sR&slEfp1UqUTWw;TO0BC*T_F6!>a!3kL<Ug_xyUE$ip@
zE`<m&*6rToZ)a02N{H@_qIcxQkP9#Z@o!?J*k@5kEbbyG43r01IdX#n)}I%-Y$Fef
z42;&oMY?Lp^fqCd=b|-`P#2j`t^o`EDmeWw$~@L$28s%$ao|LO1rH<b6s|WJ5i!AS
zBQ=vlWP+RyqtK4#(H}A5Brj_|*<R&Ro9AjveIb${DefR9i1A4-NQalY-n+U8DvH8B
z@Tx_w`I6k>O-X>ul0U<N;M(%&5@f~CX*vopLM$|BOwQ0p;t)@A#t^BlzX(54ivfYf
zRBr(}R(C!71+jUJkNB*z%sTec&&QRB%=HnNU6?6ls;oHXrVmA#s2S@Eoy8`JrY!MS
zfKJKmt@M#BPmFzyIuN9auBy569XGk4F~3NHT8si@aTs+HN|Ek0{RdGkMrO07xXolZ
z*0kDXGbF)?8dXvHQPzkzCazK|?Jo)kehc+U*HJzO+?4vWweM(B08zuXFr|n<mdJz5
z2u7DNB1wp_9-tR=AW2K<G{~;upP(s5v2F=O-bAjz;vzsez6>%XMC4n-5apkM1`M&B
zk`n&~C!afh^K-WZ;Ej>kDoRxo9U{X0M;!*@)76QAyCtv%^(75-(}1JuK%ks}V6hY^
z<%U(R6qZ%O=&&Xd2hk-U1VKK0;5J~l^^qO%zmM*aO~U1p9AWgSZ(4>B%uRA0ZW%m`
zu46mv1BiZ#Pl$LI1q%Zun%)##NtuiFlD&}*fYK0zKrV6peM_wcM2A4R3EAX^2&aG&
z+&Sr2Z6;A89~Sw9T~&-Ei4R=zrhX#*D2RY9>_j?pk`)o@Xdqn#Wb8u9{(DIogte;J
zzF%Jw61Ub-w+wzVk>U7Yt?oYnstqroaTRWk*4QEkArTz(9N}rI5R2f$aV)5{7e#>9
zSke0Ute*uiD9R(^S8t@``5*lDudL!motBU@N*xNY;}*#r^40Q3L@b445Q#{3ZyBi*
z^VPJGV(i5Usp3)8FdIw>Eyb=hR*J3y8CCuONbsk~ZLo`9{-+o^*8D^Qheiu*lmA~#
zCaMh4<cAm^xXM{gPC9~n%OPrwOIP15R$2r`EHK7HB5g#2xTm=TNi48_DnW9zZHcQS
z_8`^u>hNmZCIZ&QI1*RxCAcD?Apg9Hnyu@}gxFRl5^ab$(wGS~gA$OUjeJ@*LIpXC
z!A2UiWCo%2Xi%jCt|ZOJ*qPFMesfiSFT@i4#03X)@U*3cM+m{EzT4;qHp9$a_`u`1
zsX0CJ2%6*;^%8>Ql6YVE8*+SA(wOz@5v<`WqI#6!@R~Snfoqzjr>w~gg1E>-%aYWn
z!VBy%(1i(T<;xf!C9R5w0mK88a^4T|s!u^E&t?4T1Q!LpLntX)+F+PanH{1uG<sv3
zz-joka`~@sO<hLY5UxRqGI9qPi&)+?V~i0kBpJ|GDR!R;BtC2q0<mQudk6@NL<)O2
zDU5jH@HB6rV=VFy6|T<S928k2zTek|B}j5xv=C>M7Cdp=B1l<Y6o2C8Du^+o8wfm?
zBk+<!3SZFxNK@q0h;@^QcQ5rZlG{+Cxd@?zz<3Qh74gexv5^c!Bv&7P>Yc0HEBGT*
z;c;`j%p^G?AxI<_lKqdS(p^am<g#oAL})CdUU1R;>S!(!QOOFlq!KE^OcGlm0*vqx
z4zyhudB-Yw&>%B1f$|`+QF)j`Fni)trxOpN9vHD|aeSH1EsB7sAd73rEN3>NfCWx2
zVYV|}ImCtQ^`}KvxJ({E`cD`E{en}>@Zrbft5^YoAUcSCxhR$u;!14Nl*-0c*TrjE
zr12bOhcpdFut0Hm>M=7wh5-xwR>w8_Lo4|sncJJAt9?&Ek%Yayc<k+5Xo-T5C+f-P
z>_Hc+MEk|9sqe9Q5u1W&vrrN@EUhUAtcQmQU9lFb#x_RLd@&1kIT0}s5JlIqu-U-W
zCGMjz{jn(-xU~fIT1bsb;+-PbB$@adxaAYwBpq2WtA<KeG1OeIN}%0j6eJU!@E19x
zn<arG>1xPHy0j%LLRB~-i4?e923~M<$(Z)O1qE*s10x8=A=45AqtL>NIwf#@<Qge-
z=p=p;jFkjYW2+Imv0o*fuy8AbH4#UlDJ%3s@Y5=`h_DI4giK-hPrtjG3}WZe1-h^n
z@o1nc>k@Hk5;HnaWTN!+Tu{0Qy6VZch(M8diy$DtT<5EX%Rn|C0ya{X&>K}^eIkiK
zERAaj6bkce|9}#-c+t`+ggOYZ(KV>dB37+KSdpP&xm;7Dxsd#~TyL;k#0`EEj}!?n
z7ZD3_!f`RVqrOlWO#>-!VIbzh2bX6vEB_{7-srmgAw<E3VJ4d3gv%~#XlVta9kH`i
z)axD*)fy3prb)uIB6$+^;A;4_?A~QLj@YW0L1dVo1^s=n96z)sqbJndBe$)JfuV{(
z699$z!|6aMS|L{ygoDJn1Q&G|@h)c)_~FqWSihh&fVK#RQ=*g~Fahw|&?+J+G*i-A
zwX8o*6wiUx@zTHi9q~3BpN!}Px<!;Cng{#|KsU)4)zZX85jo&oGa3YOOa!j}xUjTM
zva&gR#c_hJYLRDKue@MD2^i4;iRN;uN+cB|Uibw``{oBG!vl`XN>eNrl{U{tkPodI
zB3Zv>4Tqfk(PcRr8|h?A;DmTo;w80>Ya^?S<fs`EiaABU$VT}H(;|AY7!B~Xw_>aE
zV^9+17VDAAt%2B$Q|%2(*00JP97&RI1f1%t!`=%8VJNXbC;P~)BSqvO>O6n~0=7b5
zd{M<(ArT4N&Pmj~Nd(b`X!b=}IW8y3FY&$kw1^<W&ePDJrWuK$>(V4QsQNfyQ=}H7
z<Z}rvdD|-2LXarBERw)NBliwJ6{T1NE2C`f^&k9))xI2nfUuDzU?zkXljWn|O@L}%
z?Mg`6cTcHGXC3<AR0&on6A@tmOaYdJECwpkT7<w&Ryx_S<zPq@v$d^k{P8UrLa|Qh
zx4g7KClP<stF99@YN`?MB~;LZ4g~4`k9gi%hJ<5mg5^VV0cuHLqZ;+QB7%q|(5ZIG
zhlWrvl#44begPk^$rpHwWoDt0-HMJ@vJ|<$&fEHB9qmGFkPD8jL=e;vTPPuhtOoHQ
ze37g@1QDOLKD<x~mMYdMp#~@`Aa(tl&#uNOxd~cCaR^Ejp~I>KSL<?7(pHpzN<akg
zbTg`xmUA&#_?kI^V@kYDayG3yo{u02KL#ck1cKJc<e4jDNz6%;7E#hcLP&HK-&))r
z=+I2HwXPQVMf5Bgzttr_-5^vQsQ_&8KCny}pIme%rKv>G<A`?#k%TCV<GC6Mi{i=$
ze!kjl0w!X*s^p#!4AHn2E9#d-^GCs;H6k;S%r^B`1Yf>z<`tSnE&v0Cgf@YW6^c25
zR(qFg?12&wDEn8R<>xmkAcCDl=<9@*G+mT5WssZW)bD}bOIdy_S!mj1AOxT(l*E8W
z>kvOI%yz9I!gN&@sX%gXxkda`O0pc!!;9FPt5r31{a3$riwQ+App}3H{_!$4K+vm2
zk$Sd{z>Y*W%O*cc>k81rsv1NQdaxtzz=fCA@m!J64(SotsIy%VMJx<x1Je>NG}V6X
zQIM!96)20K5|u+~vx{Jplte_3`Vh_QZc#9&hAI+Rb9@!Tw{B>#hN1y!{l&dZNn%V4
zWz(yX8w8(uI}F}YAfbx-#5ZmppJEk}9m6yeCZLVFyhTGkb)rKjHVPanG8^>J=@2R*
zr-7nvh}VZWyFx`_Lm~@Y;m<VIhcvT!j4tYlb4~q(*cSM|-toR$r31`?7KEOJ%7S43
zC`ZIB;#x_JQWF1+QIZLqnx?gmcp-b=%Spc?c4Q4$4ZZ8jV2dn7&*=4}BvCw}l2TvW
za63|PlN)kRG&RA*o*Yb(@tL7%A{y5tH(6Xuoy1JbltsQVI|Zk@q(aA;2+A9xs4Z3r
zrQkIi0F6embrGwJhrPEU1*?`JJ_7~{w?%-s8T8d*Q>e!Oz_$nl^{$)?FW60emNq>~
z1K>|AA(yO?;x_>>5m_`oa;OXJ5i0Q3271bM!sj1+@tvz8F3?1#N0f0<srQkS@R8i;
z6OGZl0l}x-ETG2hbfh%4DfKu~2tp(?ft^LFkc$=-L>lqyXfwfK@keV#>Ffn9M$Yj%
zxaNoDa1$aY)*KBLdtRqiYn=KW6x6A%i2DOUaHE^zAjXNov;0b=uC4@};GR}Ugo(i8
zfJ7yqJOPr1>(iF_gWq}ks<woBd=58jaw~E{23SNPT45xi1iiG+;hUBg#idUG*e#S2
zlc4+9&zzVR%Cfw$O^$EYNrWg1Ux`@}u_|78^gMN@fBL_ya%*s(CEkKnOQJe*cud;o
z@JUuf5Ed2#i;2utWy!?PO-?h1BsF+kECQ!iBrnD?qa7e7vP4DPD`(<K=fe};&hzK5
z0Fq5E2r!7W(G|Xk-;rA*L09yN?!Xs;mAcOi*(B=5D!N3XTb+(9h{w6dPZaS>;SpOv
zR>=9(S3#y6UdZ!%bCU5PE1M8edCwE83*f>o)+*+STNlUC96aGVCkXh!G%>4dm<>+S
z6yH==P9HJ9=o|8dCUoIKP*8z@O*R0~a2F0}m~GMz803|seU!yo6p;PX@TzKx%pmnZ
z(S+vVQHgKxuv}6H$vw-2jZ7n<YyDv)gW-K(BILak2nkXar5{nO`r0wUg8p=9a;;XB
z-dhBC<@B%rBX6#bhmjj4>WJ1yJCZ+}2py$gMAd4GFjmBYYvN8dXYxgupaq2!ZmQv)
z3am9k^N3G^eAIGl1Of6Y8pZJ8pZ#upl}fZlu8!oE1;@#jN-!a6+4SfdH>eDoRs=(s
zRA|v)HFAX=Rg1hQjP0WRL}M(kAqlcPU>`o?k!B??z`ZUPA3l+|DUT7o@Q{Hf0Cs6n
ztPwp+O;M=NFZo4QzXbG9bSOoKiR&!E2p|v=P5QvIxKqp;(Mf#EXcP<~bchfwJI-Bb
zDRmEC@b}v`;O(~LLd;ErVAxDNOQBtpo(N_AGWj+?x{M<o#a)d!AECt}Bewh$OJ-tV
zBYLxzn?4`ZK)z^7+yj}B-K_9?ymZfhTJ1o9#ln>urkNxj3LqHKdLaVR#TR7`B8er0
z4;>d~)j0y!g&JgQv@EV`7snyj2-AgUd}Mz-%feAlAP5H@g<=68{=%KBG(_S<!kuwW
zn6Md~+q$igfudpR*Ku(;R8^~+3UIQ)vdAsbYoqkF5z_1-Kes48e#@wfZ-ITOp<*By
znol+Y6{Cgh#GN;zPr-+14UuGXY$L1*qw4d^^YXu#v!IG@$U6-p2PIk_G6@lQIzv)g
z+zQHA<tXjb5KIx<s4xqQsW*bexDYI&ZRPxcfI~D2e;_z=n-8xf+yF6<VgVkZL{rE`
zDp)GoL#A#Kg(s29ew){Y=-4gk7+=ng=i1i5GUT%9$H9#VP|+Pqiuea+PR__`e{kQO
zjN4p@q-RAD^r9#Ts4EqVrdUO<!P7-3G&qj8j)4=`p+#{lok$d}wLAx!@M`~-Yb_Q-
zoHUN{VAb|6V|s{F)%90jg-WgYktoT*L4_)T1nDP8($r95PiCjx6@`Epa^fNj0a!pY
zD^nLq61r3nYNIs<Cgx}@kC+h(L53(#0TD{r9IlU-=H9w9)1pB%4RoMYAQD}&iH+hC
zqSsJ#S&5KJs4-e569^PFEd!v;Rq|4bT&zz^lW?Ia(a0nK4LTvV`29E_#C{1HWrC4a
zdO@wPq2PGqlrjho>H;ZriV)p5$@vBZ*QmITL^h>>ErJYUTJZOgwHhfRJm!{RfdJzF
z5&suSbl^lS;)Vjl|F*EodEkyHPY-*=bs~R)T(brFYEqzaiyQ~l7A3EsXPO7Qm>#X6
zIa|C2IVFKSMIn9z9O@wHB0D@vx)PWW`V?2@{sPCX#Ro(Ip(TqUd|2iV!V|XN+-d8w
zw#X7-21?3CxVxddh#Nmfe1R1aC?Fl*fpO}~5E2u~GB(z=23PRt@ayM(|820fDUWPL
zfDDe-|CWW;znYUoKW7Z`wK_RCIU54M8&@M6O~fMgHn*s^5si|ti3S%bfe}&YPpOOr
zR<lt!@bI;_p{lJFppB?a4Icu5Llo)=*;pSGBCesYyG>qQWilA1moT(}ka!T-L?{Ei
z@*wy}CbSg~BS<2PavYdwcL|^ek&t3Fa`2ATO;boZUve-VCnl=wahGrwVQ84W`W^I$
zW3N~$@_?KmDfO+wR5pRy?#%&h#poq}kw!E<2y)E`ERGUuCAkl_MN|&ob2_nVA(7xi
z3c??FAkq2iw+zY<e36R9spY-4!l?$Sqa$ftClCji2!o4VYdFK!EPFGq%*(Uo;+i&H
z)f3IMOO^j(HAdIpKESWSMe@Z~!ic&gG#zTW8IKTCu{>I;;Tocr3PMG^0utzsL5-kq
zaSf#|;6XLB$*h3j5|0n9q&=le2NV?k^!UG8odkl2vO`WZNG(eeTXluJDbV#BP#7+D
zB}QwsFg1KQSitH=eS||^Pg*4d$h%~kS5ejoRPYiBIx>mu8ZEOj{pYv%EW$(K5~Cmk
z;tkg|p$Ul*lZ62#-&MpNI0Q&XqyK@uA;gl{S@QAi-~-A=M9~mqKoOI|fG(RVQ$r`L
z4FBNN?KiUw89}WmmZ*{rj8-D)mS(gPnLakh+pmb<>GZBfMyWAD)HWzcLfuwgR0v*V
z3Ft754c_PiAHEn0$#O4JO5-})Tbb$-quW>|$jiS`1nkZtrgM>w{RR<Qs?fM)jao$O
zMwg2ms1qS*iU|8;AEc!4v=GHC39-7QH^n5H4sleYB$DxR>03q2R_52<G*8$DUC0R!
zr3)+9b!#6=BS%csivi2#s4d?N9T7rEO)`osHmASn>XTH1NKw;v@pPmNdlcq_qkfED
zcTGR}=q;}tm0bwPw?&!i?3yapxXI1tHE}9AOURWdjBhoH61n&Y1SkE+C9V?ZR)nY_
zsr76UNEP{`ECPG23$Xvw*Kfiy14zjR>?M2)aAgD$A|u!U*ZO4`zQ!$5Ho!KJ5$BG&
zF0yh|W3&WVg*9xUpH1+1OB;v+#p+1slVnseeSr48*H*u_B?@hQao1{CC(<zt*eZ>S
zqKmdju!WIDsCBfyKDWH314(Yv7twVI34I(aK`JVZbvXm^cpAQg$$V8u>F{NBzr|TC
zw<(DYznSt5AJnO+i^ah7)%PcGts~NiT?h}km?SuDSOs|&?(r;32Mj~rxW|*tGw@u-
zPr|KR953Uu5}0O1&%XADu~osG*cIGW>X?!bmIhTw#i!|q;RP}aMKjbSq95)7mPP#0
zXoZ4CtboB;guDP0KMn1>iP&NReXdAH7Unrug~meP|K)|qhilRSNviuAVt25RHPPXw
zAT}=6GSXFmX>@DA3ffSAm>HNBy6=@KaEQ@Z0fewlLnKUU|F|szwu|tArzs|zzq%Td
zkt`?yUn2O_tBfRHO<2NqBM0<_<CGIb@kZIEj)*IY`iNmAAkHO7hDES_Qw-p?Y%Oc%
zbo7Lfm}jqldI^uSxp^5w_t`V^Q}}AON;akt9>ay28)fX#Vi~%Lc<fH#K{n6%79;^l
zX?1eLm}qj=&T(KYt->J!!dAxLFW}LdzAi-)(IW$x4yiCkp9YU37UK_5{R~4oILPwJ
zZ?2J#>|E4WI#^(F64D5iiik9BK!<oyiTDAys5t>DWK{j~y}z=`CWw#$K@bpc04?Pm
zPBK5wGzO7a0>6S<zT{aTFjLpn5d7hS_!*0|^y6UH&8k31eSxAQ2p4W64!ihibr_uc
z!aupWfGD9*&&lFQ<7?ybin8#jFF^QT7XW%wNV0`sL7NDA{W6P(2vTbxNX7@2cM6fP
zT(tpYK=hb~IMf6^qimT8-buZ>`4I_Xb6KI&GFD#~kPuL4ZnJ)wA~?LvA<I5sE59$G
zxy?uhQ8c=#YS}2Qf$9q{>NAMnE0jRg2=OIAMMZwuuQ%t1l~74sH+D|uMB#f$VXCpk
z$ZVq={3qTA>O?8Cp<sNAoQdGFCgjYdM~;$c(|OH6J6*&raymKOE6Sxlb^qH|O&y^u
zUK2(PcaY+i#z>I{wl-M5MVHC3wU`B*!8-K`y4gH^Jyqo{@>>ij8AKaz2#;hBcnW@k
z68K|_CdMMv_T95e{}F(Q#d?Glkl~i{i)6Cdz#=Q64~!*BOb^}bq>o6${K*`qnEXeP
zNQLO6388{0!c8h}k&hq&^&&R%mrva;0?{G@-$b4-NQ@*i2|%%01nU^VsS@7Pw!ElA
z4pYY#H8u%uKx9`kueoBNFG>wa%%s3xM5PQ*2u=x&_mW0NfT-g^DeaH`-Kuk{;y>XJ
zD54aATGfPXV$_>ZTwkU5Uo4Q6C8?mMj)-WXB~c!SJmxs;5F#Lj4Tpedqu~K*+D%30
zB}VzP&%a|;LQQVqe;zN1B~Xfg0~hkCQ@e44uZ7%+Ifd{IDUjrg<PNpbB|-T`)<RyO
z*;4~j!2^^~=cNe3MX~7s@ju@sqT5n~x^VkZxd9U3HMBU?@W&+K0`Wr0Un~L-4JDAF
z1zi9mxR($lt_yIYp~0d&5(C3Ow3qk~OBU^G?h}!AGz39>F2NeeBMTLv5D=(uo=K2H
z4mN?6;AL(NK-eIzToQ)^{avIb*T-FpTtev9B%IDh<+qv?xqyb(B7dcbDg56gdTfz^
z6^Kg)k13jp*^maUDBafZN(3h)#l>B6o*Pz>uLe!z!xRWL8%<!vWijZUtiI_JqGkj>
zI?@XJ5guM}F@NXk&=4X@Q9@)NGGLM9@mAl2C;__c(!E;j$^|;70>l*7=N1@{Ye+><
zt<@Hxq!`Nj)a;4}S$37EVF_;%b`rJyp!b&kI&ru7KWf^j;gLuA4Dm#o3edO#eWv3H
zo#wq4&DL;nqv8J^=pv#)!!{Nbx;0lPJmnVLK@8=d91%FRck-wg-kxdE9yJ!URKN|O
zLmr8}pur98t6#)dlY>z~n{<TpCh&#@kgyo(L#4%$gl&Ncfaq=$LLmX$lMX;)XEAd$
zG0H88>x;ieK+zCDO`1}poLLP!f;5pclWuDHM7Lnj#Um6cMgP%b+H&hEC^Uxmf<#%W
z8D#Kv3e8Om1U^uSg7svl2?-FKtS$=h%fhXVo`{76r{W4>M`3PrVnI>~Q}&eEH$6^7
z6D{?NB(iQj@iK9@OX6q(KrIt40TJTEzNHAWyvQ4ZYGP!RdbG4!{Gq(?0CPgrfL{-e
z=+QX!JvJ`yQ9dFn=W8U{fb=(7l`?_?SR95%hUw-~EJ|*Gj}7{X1`AjamvF~k#7uOO
zA?W*Er3r9EbU{Flo>WZ7QZ*`ZCK_7Uy3Q~Nz3>ELHWdw86Mwl-07--ALTHiWx-CF*
zBSi(~NU*>R5nU)XUizKy2@_kQz$oaH5|NEu!(8i%Fhhitcj3s{0Y3@}aQYfBfB-Os
zh*1s4aG8LfO-3D(4ZMT`f^iBGpy)b<Q7EMTY|m}0lz}x0CqSaTC1g5)5)z`woeird
zc*8C7>jUT&<=5I^fw|gTC2JI8f;?kTOOV2^Mvc$)>u5uLky&&kkkp#sPBiw14<{sW
zX^kVbMWlxXU~mv=Ukt=e(b7fg*${w4wTY{wViS$SkfKb2T9C_K6yYsOrm$r=B7tEO
zV&<}9m<cl(3z>h|zkO9Axo$d92o4GXsSF|;m9K{KHEtk@AT_VDLd;qR-w<hFy0$2m
zH&~=Ohl|qo(?kX_su3~x2f9<Pv0zR6KmYy~(};t_E__#916n2P$%?vCQ0td#f)#YC
zl0fCxvGHk`Y$QrDq*45hGy*;VYfW5JNnzGUkQ>lD`gw>z;KpLT+hOIxQ{uQb`5>6+
z`)efc0FCPYas8TfeoB7{*+P0*aReE9RaOi&l2`xJ@KMG05H^b{G}b3UJPIM}5p-Bu
zWE4mRc3g0Nr8zZ!gZ&5_+DsgY&aCcRYKkNCVEx+kdi)^B(a=^+NDMh46WAb$TvX?#
z1mTLx;1Ee#4MZi_^S`UzoE$1djuGRbsK6Hiid0Q+VoE(?pw$}E1k(B=1@>qFU%1QA
zaDW8yXqou~LKW$RXc!jJBIt>-Kp}1=#VpiF{OsX4KWu%VI~U~&uu+p^f6=Egh$br_
z;fPTo!qx%ArfVV=n{8+C86hwBQS4sBaYfx_c~P$zxzH%`Tv?mEMe-P#rAY?}uuV(%
zDrcpBiQkt86D3=Sw^>XyxFJX;6U%0D<Y}mufg{*oCT{?tcp>7yRD}SfLK$AJ9{#Vf
zRoi9^xJv734c2g)8LJq5noO@>cd@vV3aRpK%N;^ab<up@I$jjfV5<<c$+dbSnxF6}
z2+IPii{c>g`R7BcEHb8xXUPx1bJ9#9Z5FNfTs5xwoam7}lNznL@_e0VqC0{=f?HU9
za@m-4Awg3z*qAtMq=#sAk}MUwYbJz$`S0%_IoJHiMi{C_eo5TYW`VakRpYWBO3oha
zB!|^_GUBA*<K6&`!XrcqBU1#BN4G#TxCd=WJ#ZeCzQTsf|1T$b7Coqcux6q?=r}kD
zmvUA4d3~c|Cb31lFl|pxi_S!mpFj|zCm9>EGgOeMk~{E~E3UbM3(@6hT+%Cx>?!9%
zzNQe2pIyxYk!>7Cu@Xx55ZNoCbYle~#k@R&1YXE1=J4#AZlO55I&|lK=yJ5AYp+D!
zEFhX(li7I?4q@K-RE2WtYyZdF*lYa`{$yr!iy<UcEtZVP3IT4o9F5Bu1z94$O^3Qw
z6ISI(NRy@NDEQ6<<YJm`KyzSR;z%$dqUa?>)UG&a)S5ridZ2-QgFf{xESaH6zi3*)
zLr@Gp<H-<})-M9e;+I5WgeWcv`6`*YX8I71U3MS2gz`Q+mMF^c@Ljjxx_$9lBivh(
zHZ*ZUZth*OKiEs6S!QD5<~s=39U_4l;k*&OLN%doQ!k)M^cZXApW?*T^?tnc;!kcl
zoyh889vnw5kvm@7FP|m>BT$x<8s!*T{xMEmX_7u8l&AHGmnwrT*hiVZVGZg9L%rTZ
zLnv6qedM$9SBF+veAX|(lVxdO0}{Kqh7k8AW=B`uOpb&sh%cTjklqAzU*c<te`u1D
zR>Yf&jzEWP!R*GPV$ndvYo*o4WJRTrX;GD;?45-$2&`=ieEmA2OG%rzFF^z<T{jJm
zwEt<O<Mz}f%42cOtt0Tda2*=Z>{<l08Iq>A_Z@D@dlZ78a9mgv07LI0SZ-_%9O5Fs
z(xWC+i3n7mmjUWgFscGmqevH3X?Zy^F6M@PM2~{HS=o5v`VYo$jR08UC>|{jF4CpF
zD8Ds=Z`eW|)EdSZO@%;+2ALQ^{JO|P7j`G>z$+Hns$XuhruA%%XKPtrJt6ks2mfW&
z3vhTChot^8Ov*Pd=~f{?!(_o0Y8C<_ypN3dB%*FZ+ZbFVjaktqS_QkP5Rz<YM2Nz9
zc~_HMmWTIp2(*6r=<oB>n+hL!b07e|HdZB+x1uzqy6)*o>OzCaAWhfJ-(!KmvUI@-
z+z3RD3=1>?j_TY&mZ1$#Np+cMgkOHb=kVXJ4tl@~YyoeUl)=StMM*a{-<&@RAfYXh
z00GgWF78Q#@DXK&^tej+kJ9!+qK>)QY$RGYpQU=a$SFa^!w)~)!Z{Hih$pWdz~Hi0
zfRWEl`H8OT9EK8mEoqUcv8^t)ObpzJsg>Y*DY{(G@6@jo{X!j3K=Rv-tV;d*!=GHW
z0ydAY1B{|3^5!zpYZlOCzO0K_2{Xy`gaWXrCHlA>kXLS&;g^VZz}kjjNU4!01&9}=
z<(>?)Y)<>L_B&ZPWN3Vv-b4*d<yh>R=Ht=xXc`@JG#4mIaJ1?x;${g>QFs|&s&Ahv
z3=F<y>8%lp_yI!xvX7X6S>vTY`1YMZU26&87UL=T#Xd+9;bq-hXlxWGUvfvduTjZL
z7O9%=oyo|#05L%X@5})OKu*6ZkxoMhvFI{5(Wb0bG@HlCL4F$ttGR%>i2I!0kRuut
z)$pVRSyzcMAty^Gl2FP8^q8Q|g@|n^8L$>zB~M**71^uC^+>Vs;2;e<qaBZOWM<`)
zU-(DpgCt{+00*eEw8&dNc%Y?$kc#UVL^^!|S5_|qUT2hGj|i|X?|RYIC>JBc60J_2
z5;{Yc=99FU-uJ~-#aJw{4kM#!Icq1qVG-g-?uO7uloJxm|9C7pXd~yA>XZ}dMtd0o
z;}SqP-W$>){Qu}tR;PaT?^|S#47O;IIAZuIjY16qQl9|ci8Y4gkPe%LPt)8tZWQX(
zCQnFsCxym(5v`#d^+(ZbA^Xj%hyPlBX?08T>IN4F4E+$ox0=OTqab<skE}>+nAnn*
zITpo{v1-vpc7a9^ey>{mfB)>tr;n{>JUbBbiWkh#qctH9pE`ZmIE1Zf{v!HK8B%Ox
z%LyXFkTi(=?gGRb^r^Z+8u>&|H%7(*l^A$Qibv7KpUuQp!#)8ncv=%0;^}3H-)>61
zycdr6T$lHE@EYcjWi{E(?5vthtq4RFOBF4<fmn^_2pDK{51UtiGkp6k`lb_vfqSE<
zByA%Q?G}9lw?PwnO6j5<tx3kUK@?dpUD*%>NL%vJHpSJO$|hGMazV7lqbo&e1X*S3
zgjG0ENJfTk6}Lq*T+I3<iFKsiBmoxRJVPuR09jFG!5U;rgt7tFb;8{GI7h1LWLf$A
z@2x(#3DhI^Koa|t!-Rmhd^H${x%LSMkZ9heoJ&x9Z>DrIx)>Z0F!)Ulmwe3Xi;yhZ
zxzME+5lwsegTJ!csTWnp*#sa%h6jwHX(L{bE&&1@;>7;DL^Sn9HNAEz7rBv7xi?pB
zBdDscx@qSTVk8Ots=+jVGb%}Nxnt#T*WN;TF$fr3BC}-#vbKujc)8$PLVPdkJGgX8
zUUArjU$O@b9$C?4_#dTF_`YcenOw9kij(TkD)obZzPc$i(p*wB@C&L%ah$BLF##b7
z+NTy70*s}t0}X;SeDJ7IGRaXDBhy2rZPmq_k4Xi+D8Cj)`@upC#pECL56hvbBM1?#
zo>+!pS3Y%oLFeHpL1qNgk%l%iR1(8S*dAdlQBCAJHG#1{E}pm;26@8|kwmtCbtJ){
zk>-LN2n??#U{Ni<OfKRI)nouU5Fc5)=8}*=MHLKpJGr+8QC3k3V}K+JR@9$tTwU4o
zT@j$xrXy)!LY!T>RVXWiGy`DNPZDcb8&m*zr3qGRH5dWuU_SDVK|s-hDx)^*9jyn&
z86$T?<n3zO$ac!}4B7ZdXvkvNLKHVIQn?rDz??QP9o38EwJ6cf-kJoKE$xevzBmhA
zQcfdbr(<Y&xUSxf2MKUm53c;yHsN6FBi71~U_t5xyz*06-3(j>9sm)hlhqR=@L_CK
zf0}*6>IhWf^%^Cx#MI5J^=IX0NNClsUtal(|JD|7<MdRtg!(EOjqpMKja?yMSP#%3
z52~K=8#>c0-^hKV0k<Z6?rX$yIE|XN`42TM%|p7ZF1mp26TOiC04RpzZ}~(i6TklN
z=uWvYql0J7A*06y?qywnP<#7&ZjcYzlR8f@<c%M(&W7@d@6ucmKVzZtfr8QvC3m~c
zhwIO(x$ms5szrCR67FhkHX1+%X^s}%#P_n|TR&9z^-#Os{nJ~2%y<9&y|Or^R^5nQ
zTlHQ2pYjvV+wFfxbEl0va2iOMM3&-a8iQ*nHcnjx2{65Jv;3SN^8jfDwzX<ff@`Up
zP<vEL-IKie!2j&O9)8#DEZJ&sAl)1;A8$xY;|GnUs7zclguMBfrrlhHFL$Nt$NW+;
z&AIpA#BDbf_w#Yh@$Kl!mZa7lH?`btnxE1`4zno)()8k~nBS&iD&y%^M#XGlI+YgU
z<AiHzemCDLpON$Nf|ZZwbwtYID>U7<LR`6;X1YOUWun0ROsH9zXb~#vhof%*zTsPN
zTZXhhhJd9bouUk>n8~FiQz5y&E~;Q@hVKX|7)a<5X7qeq<=Ydkq3sL*)BlwjQz_Of
z0=6m6Oc~vX_S6|qYbo1JX!%4cp7G=Pn3ihS^RZMsG%|6O(KTg5p-jTC(rVu$NH{*Y
zs9C{H)wlF~yiLW8wq%^4PiwxXJ^a)i8w%}9w$P${&Pn!}Dpg1qm|JP~*hGHDu-~S+
zX)UwlIH{On8SH2{W_ZfjWwCs7NH@=JOs0CRk6V+zHk;lQ4mySSnWT9{SK82IVdjID
zHk8oJZbyIG>6s`FyGubXZmEK)EzF#CJV)i%dx;=FclWx&>tEfrCFy#hr`jAV9SbuZ
ziR`qy&)bsp9e4lhfzcn9CobB>SFCv2%Q&hKheMAAj~VyJ1ME<sEXPu_%6@O)1?J4{
zZ8bm4jN89EZs(Q;jTxgbO%l!ZOZoR1=B&5ix=t{ln<@Qi+aqV94TQT@Vdy@4N5RQY
zc!O$2#qwwE+~<?lz976<dicfdlkR|f+VRkfeEN%C@swFTn>l40Vm!;|htrd`I_hnD
z#&-MD8dy4G#ZzhJPEI_{;*9KRGf?I(D@YZT-jQ_LjU#=|hC`d;ySm(5|K3-7H`=N^
zSqQi6Iavs1)3KS8=J9SMIOesLj_8&(yS{y?%g7({OXvDZ@j|%SPxYGlSiaYHUcP3P
zdJaDo3k)sg($SKB+R!v@VT<h;;nP7|!Y=Pd)b^<md0L+swY4q&U;^`aEpQ*7HfNHh
z%Y|Y(9q*t%P|Xzz`e1P6hIvs_N6zPBrjcIDy2E_?QnKIgbZjd;nY1+L{!-lQxR6Zb
zlhfIO$x>%Q#U7n<Os{Rp^e_XS5srN4pLnk3v;|K5F%KEf)Ep~+(ngDp*;dDNA%%$X
z$#{u2y_DDCfb#v}SXoc457VfH(u}tL<WTtTxHi$|+}S}zXf|fH*$x_%_g)F&TDcuX
zNKTh}mIAHh>?>$_-7~cOZZ-Frw`r=)j_NRY2%;k)N&vRH>*AUx(;Dcct<o{gH1e?&
z0|5an#?mt-J!9XVnNMZ{`ws1lVVSA8)d3n<g?K8F*PT>c+s6=3n~XB4z4*R6^D*=t
zkcaAymKVFo*487ToO|LWr>>TXqo0}|q|E7p7V<E=jF|($l;;GDtGAT`r{L-VKrtG)
zn%0$$0YEJDv83kL2C8;GX69}1c(TyutkKHx)a#QKMAJ%Z?s7aFin*ql3uFD3d7rMq
zZ|$WZ-gbwZ@%*?=LSoX-=sUf(WMXEI<+x9K;o88<#T_EAuzY*By6ERF59r2Fs6Xa)
z#%tkDC%8Kt-{IKKhU&EMKbkX!P8G`j)#axUfU;N4mfgf)DeELc2kAOF6EpXz$4q|)
z%B+uv*MGG5l2vH;O1BNi*Ch+_;kY-d*4o8nzZ1?p74-H$e`1eW4#$Ey*LupIa83VM
z^5}ZM+t^d_cXmGWK2vr0&Q|j~Nbtwc!X!sa8HcREnu)i4&$?ram40mUkyC|_j9aCh
zg`?A(Pivn#cg;Ip*l_<5)qNp3{mAh`n+netPF&PV?n`RHR6|q#koy}+cYt4OkaN%b
zhQB6%#c$V*Znf3UCVD0e_cwp`jvn8B!?W)#Oj+HDaNWt_%|K+*@_KQ_Q@wrn$G5Aq
zR%ne_Q)#P5O<Ad;(tDIXaAI(s{@AYGlwnts-KIXUzTlVo?$g`}?e3!CyK3SkD;^l$
z7PHf~+keH#=+*URJh<D|9OQ5|J`>L$vHI*bCpMXShi|qmDbJa9X3us$>JP_*1BqP8
z?o$_kcH|E2=s@NnZ_VB6x^G%{*Jd8{ylH!1A-J~?D^I3Vw{M8sy`u%sT^Ac0JyMQ6
z&wCm&33)?UN100RG25B_V`JVkHmR*<Z^~*v<!d>8rm!d2z9DS8;P;mdZ@@D2nRsf!
zNLiP?aNZpCcG>e@VQdDg>f4~C9lF<4`>VkPv+&P?Gf6_M%ygl2=9D$l@61eH{BNCh
zUiZ@(-S^k)MSZ5d&q!<Cdd5M$gUPg}tSwfM84L`+ptl)Dpqu-#YS_X;+_zHkOx#oH
zZr$-d<)2h;K4}dnYnxJL;rZaPVD?l=-J`xZWeuN00yiti8k+QG>~keFaxgdTVPu@{
zM9Ed%iL$?7Y%lC`R0`|yTB%+C#GW&5Z#q;1u~Z=jr1+YNp>yn*ffcrKb>ahQ&+<CW
z^T}5>g?hEyIGuD;VQ=RS_p)hcYSXi-J-NpU{MY;w(~srcUVAoPewXeBkDPD}^D(;V
z*Tn!D!_#JBA<2t2HRaCgT4<zVI|@UEJAyD33$QFDl`!+}O66Z?lAaUl!BlX@9SZHR
z&$Q0iI3}IC`83Z2j(2A4jIl4&oG`CqTHesR6DoJn?Dk8ODs$Qyom5*4jGXQ4Q%`r=
zs-TV(%v!0Mx^t)H?zlK`(mrZ;8in4%%w2YDooAiEbDDM9o%HQSYRXN;!b0byn~P6t
z#tv+h9n-Ea&?GVCPuoE{-M!%1n>}NLf67xG=I?n`!%yGir_<}LvBDRt#_ai?t)4Uf
zWg~vvn6Z>~`v!aKu)WL7$A>3Fv$D@$-|wk=oK0^twRGFn`E<?H%DPgUAAfp0pItK3
zftC-G39u2IG@Y5)^Q^uQ3p$O2_K0<2%5X}KHeN2=URX%oXP0^^N34tUo5On-Zr6;b
zld}U0w*1c7tC_&l@#FYoHm>DxV@AC;rH<$#?I15mp40Q~g_s=<yDDa++Ao?m7`w%O
z%n0vxwKJyEQPS7NQ#Bl>?n&Pm^<aPw&bSO?>p*QPZshfR*1p}`S5Ad*e5AZ(Z1~2u
z!I8onz20YDIr2*7<>?;{-stcKzIWt&aKi}ZrX~iyn!NYOQ=2Ydyx}CfFLX|+f1P|W
z{XJ)5X59^I?eVew-#@ZAxWnC*d|>?fH`aP{-lun6QLlFoKY7r9wdbj>S2kU$s7vbH
zrW=Eu$CBH_=WisPuX&&D{r2R}&d!G>|D*FpU>);DDwEG_=<Vyde73J^=kV~$-Rezy
z_`dH|u5OyVI`sYNHy-ys_$~j!@VSLQwhudRBzs=meAZig<v(wp>%Lq(bl^(%7n_au
zmp|#;KRJ><zvr6s<Lm`x|Jzc{-WeSCw;zAzzCFhFqPP9%={LV09PB&&<O|`WzwyL{
zoblwu>{fGg`PeD$+mrjs`CXNruRiL0@AQ+qW<UJwogeuVyYKyX5B_Xj#h$bJroK8k
z_=Yh&_(q3!Ecu<W5m2$`;6vv&y{~W1y%Jur-q_;|zMiw%E*fjC7p?oZ@BHlA$sGe9
zI^>_s{doN+lJ~zJ*!O=nIJD>RuyNQo-}I7eoo8;0^#mQKljTF*y;FCmcUfcmFL*y6
z>p42`(eR@)>#tZ_`|iE6)&DDFt@BaKzuW4~{-W0V=KQHYOn<j?aK$&aAHVzC-#pzn
z`}&oxH{W`HVbeFJPxRc~J(vAc>xQH5ok!t6_KWV$;}!M7Ju@qTJw2D5AK%qCczS$j
zJ*(Z3eAJoqCoVp7@WLy>Uq5@H?|d-7{+NBtTl?{6rxuS5teyJGm+ZOWKfW+EGnYNL
zaP=2!I$r6n*qhCx?gQTNWTD7+efNzAd@~X9&3s44crY|?bi8`tyw6|bJ-Ecxzw(Cp
zw>(%rXv$yRH=n2^d19w^fX9=S)^o4+RP5+M9(V7bzxBC~%p6yrba?R9VC9I%lgCwk
z%5T+VW_k2-_3)$fjNoz~tDSQ%sA$$5!SF|Bil=;8?RoWttab-egvV<;xI3JU9zC67
zxoZ{oUMW0fUQp-V*MIl@ZEyIwo)4CGcI7JfAG3C@&Dq~DcYkTby4rrjbh2-DcOUqm
z<K@m7=go<V*YjYx^JTB+FE8I19zO6*^BJSIanjs=_5pw02TITHo*b^Uf8igd2JcSJ
zg=7BE{QHg@+kJoI?v6u){r0v8AMd&9{ZadI^M~)ZW-q(DYwHTTuioQtTzA|lPfQ(}
zJ#_r1pI8~&U4C6Xx;@y~x3=@yn!Ry%@%82J-s^p(edNnGJnvqw=kur5U$B0+e{IJ{
zuWj7laro4${*x2kuhyRO7e3u#{?M!K?q6J~O>KMK>>N0yHo7wtxt&v;-zZP0UA4}i
zo5`Wd<gxdT1ph@X*v_$cm$tq6<GWv*xZ(Th<IaoWCA%_N9RKOy{GPd)50vbUzcm-`
zw(p%hIR-U*=HFXf@x6QfO7C2{-6(wI^6_0(kNc+Q5BHhN?Er6>{t&$yLIZzu_hhHr
zr62E{t370?OQjRu#_s-+iG#a--`aLA>GpbS&Bf1n`pnqW(D}(Xo&N8r5&N_^7alCX
zb<rO`8jdVE^Hy=CHas%i?HcF2?w_mEKeP%j+tu2}sg9MBITBR5XN>9Kv%5<*CLAsG
zJUJ2ie`I$aG*1Vc?QJ(q^LQ}a{h;}3&aR|)s_**2TJw>2SEhc@_s+G(J)YHh>1x&Q
zIp>U3?ytNr%zn=AJ}AGJ<+K0IG>dlOggIO3HjbNL>Y2Z5dwQ<cXZ5^1H8Hhuzd3UD
zpjWYuJH^j>=e!?=yB9{L`aFYl*v3!K>@NGx?4{cIDRt#+sGhj%JIQ<P^Va;jtkG)~
zOE-M4=S|0{jZB@lE{6w8zqoiYt&Y6u57Mcy*?!vi;XinlPWQ0)r<2_m)dS@N_KD<n
ze`ELTM0HnfT4lfQS3c;3Llw6pPz&AV-KFh;bF6)?{FXiSm^rv$_pa@#PIiW0&JACk
z`OA`9@kjpdog?XkgZ7@%bLp>7zTr5<;U}z_-Ofk-jqjQZ-TSN!4^nf<&2Lqo^v_Q|
z(Z0!b=8c^lyS(Xb&luaMobruia!4Otc)<TqGI-TG<rU4(*?osXY;pFA_r%t@FlHH>
zZtU8%p}?KK(|IX($=7?lw|sBo*3JEM(}xGGgQj!M?l;P@9ajHKl{cPMMu%rrtfAeT
zCXL)>$Emaz7yRK<PVM6GXUxQ~nh3vMdE&jt+KX>glu=yC`DgB$y-d*h`NzNG_gLxl
z!k{{S`pDU-7k_yBPUCK<6FzyvADk9;_~*Ry=9t<wxbB3Rz1ZFPrfF7p+5~fz^MiJK
z&};RKIS+Un_xG;FnS9p#j+r{-P`?;E8fJe23)SMZ_aUD2^-TwJ)_nWi*$LHSU;60;
z8#|Hot<K%*V->4BRvv++f9xD8KUBMKZ1%FV^z87}@SyT5TZ`w)Zz<L3{lxCG_D!#^
z?B8}};*wX{zuBBw@O$EmKlLjgEt*O7KJ)t2)t+^`%SUXabbBc`pPrpiPUqJ0G4}XH
zvvlBm|K(Y?Vtsh?8b94rY2UeaWU69WBzQOO?jBcDfpOioI^RH0uX@1P!Qr?$yW8rS
z@7<Xkw&#2Ok4|m0j)s+;zEup~@_b`1Y`?}1%e!+<&m^r@_6JJ4c5U~2{xW@O-mYw&
zxn$Y%clp_Fi|u!hmBLTj_Kym?7luxID*NWeXNRHW3#A;q{Or;<=O1yW?VckClMfXt
zzGXkEylvlj{BTVj8Cx#&JZJ`frCobuesZl@TyRX|x#dp~FrN-4dy6n}W<zEFTJvbB
zF!?*b_L6<j>;9%$?F=^BqxL=iI(T<==#<g9+xDl6yv|@-ulcn~vb#O8q40qx=lqJ_
zb9v$^<n+j;@<G31jjD-s(Y(rZ@b9PI{1h_dD{HsfG3ek(P8zc}0^jO2{f%C@c*s-m
zdSTP~$%pz6moE5^kC{h4k=u6rBSB?d$7df|n6~E9X<I$0UcTbQcXoWY)^pKZ`}knR
z&X|?Y95;)f^X)#<9SKUDZ$DD8u9s_m@2u+-4xK)nE9;MZ**}1GJ!*ct;?Mp4+p~Ku
zt25?$#JzU=D}Cy=T6bY!Jop&0ecabx8ZKeUYQsTKwQESl-Fv*r9@iwAPj=oGI!1^2
zs%KlV9kx|DPEu_t$h)~GtkKdvo-<cyH!b&Y=^-^^?RE;ov6lw#D4tyMQkQ+lo(~5S
zneSVAd3O*DpEN_)Ypc1Aw!_iF4a!Qd(RQif_}X&dSZhxYIDVqwjr{5zPlozhM+^Gx
zd@S<?tF6y64fmd@ylYpi%Cb|4DaTNG-SqMV_!*BGQe@aRkk2!oR*tql@wD0IjR$AE
zax5Quq`ngQnyEH=ra5HC)jhR*Op)iXtXS!3GF7wjF4euel!{-sYR*hrS@GP0tqtf7
ziO15AKKGYzuVv@$PvJzUi)Qf^yJFur9^B&&e}vkoHE5ppdfZogPT4)_>XFoB^#RYb
zI=&y>x~Cgs-u`Mg^ew*9SFsHqo;Nb526+Hi#hMJi`mBe?vD0&U+^#2V(|Eu;!%a9V
z;%2CU;dPh9+vthqP7hk@tA&9l4deKcVe3lu@DV%>_bugl-7AFSxDdO8frY-_;+|x`
zYI+$PRP4AK5boB_7;DSnaN%-wK^%;&W?@(Qliy5qyz>6@?v(=m(S7IL$pZe>z_0b)
z7kN0pmb~xP@s*>K;^`DW?BHX)`q^(SimS8jJb$e%|E&MKD;|sdeWh^2RG;J@lZ82V
z<;edh2f=6Sx$Ley>Omjb4d0I}{1ehq|L=T~pM3Y7WOk#$GO?6Plpa-ZNV~-}a(kqg
z<tL3>Bn`%gbd}^h`N$o7QlzH61nC=jTuK!WAA9FuZ!&c<2uVeSFBRg-uq>6bVphJI
z8;)mAj@#tq3U<4m1{%m6Y%x0S$g41>`pLa(ACGG(_i&#VU#|~bvM)NyBzvtw-}iSV
zyOrKX6~T2TwG4$Cyj{!DJZq;J?otH;Xl)>^szl6QDnTfjzw5@oyP7G)oS-)2`U&?j
zD-*Lc(jswf*y@fEt?DGtmEmigHjd3&UZ2qxA2$uHHy>|1)Em!}D^~Y;cchhJ121a8
zqCDo`;}54p-PTHv+4+;}H8P-@)9*OenLf*X&0pBWie4LT*URxOe$b(tTass->u19}
zwe|#+w}djn{z@+yS}WDwMTW#9U14kc(kX+~qLzy}DQ+Z@7~AKiZLLFh;fvp`J`kjc
zhc!xpQyySK)>EZ*@_o{7p=tIOQ}Koal}dQM#Nt~@u*H4j%HQR~lYt^(G3@zH?B29D
zrDi6o<#v50+^tAsSx(2aZ3cvcLE0f%OvZ!*5gq2VZ`@tj?04Ads;NTNz2ulZvHME5
z1?!&iwd1}UhWBjR@Wl;A=)T~FLAczW?CaNzvfCfD#oeJVx?Tpr8t@a|@HYRxzCbgE
z5~Whf+S$LQuRI-2pGgPPooYUC9?`@8aOc-jN=<k>?DdcAaU5Scvwp(21_~;kch3dw
zrvq<`6(SeX<lrc3p1FAHL}zVW^Q)ehU$3XXgf#kLdgciOiELX4Pw$&jfv3Gjm#-aD
zsW3*7+w+3_E5Tr(mr_4;_54%;UtF)I^nIb%TP7%aU-FSXLC_g5y=Uz^3}+^L!8Bej
z_?F?szWiIkY|WhcNOeG;O;?jvM`D&R?6T!2K3HC)oS?}IpORgN9a3SY^OSkVP&KJO
zC~pOF;_KsUsioKl1KoRJEC|&z=dAGUr#oH=4*JfN>R98hb!K#PIi`wn)5zV{=BsW?
z`Tf&_&ZPf@Qd3!T$mw$)DOBxahUz)1X3`yw^@O|2e01tVrT(QYX6DsDA^kdY)()Js
zBXUvGw1MiLElEe4DeWnA8gVmY_IY^<VkVs-=gi*jd@S4V47DfPmV)w$eq%$?AXs_I
z@(U-)UVeRQ!e4wji07?|nXj9*<l0Hq?ZjqWv)`PpCBx1>y!{i-J~w~gnDhQ+Z}w$p
ze?e`Tp1t2So>wQPcZ5bcKJ$^m9pU_D-*I;JcQ15w?g`9P`h;C5b+5ej_wdm-QJJR$
z3I$p}e^9oIYZ(z@`sPFH%z*QBlB^G$Ba3g4>RA`FC7Gv`me(b9=BEvS$x!>kd@MzE
zEEg~LlBg|oSG%@Qb0NX+8ILK4yjpm>W(HQ?x$*8pXV!~VT`whtTul2^@}l2HnLz+f
zrSx(PyRO+Pt))p>(L~<c8Sk{?z7bTcp3qHfPP(qvUBX0>YfZ)TF%Qp8)1G!5M>8!$
zY2al>e=Ha(Ty&_I<Vh<P;;sfO=ku?>*r92Y`M5=WFB35RKG$haEsdQ?k6N3kN5r+E
zs!j4<uVoxw+%=<T9Nl-*`GbyS6~LKXyKVcEp3{~r#h*Q&w8sj{6kaNAj4C{wATE4%
z!Oe^pRHh&QN5#xBt$f1HEjR%w#-gpOj*16Hm*4oVmvTFm@u477vvX55GgqZVqnY4?
z`zbkHr!?2f#LaydEBhb!y88z;wbRqQ?nK&|iSuA}@}+`*+Iz{Kx!67J_?y;MlHs~N
zM~>O1XKwi2&ZU_?Uv06KpPNsX?!NftgWd&-X;bPkZ)0+}*UyL4Zq9_MxRy^pkqnWe
zD_(526es^Vxa3R@CoE4H*Z*$Y=#`V<`bu)$L(WBKol0Mv)HWnP=XmzifYYIq5AB%>
zgKjTTt~s4aeP+;#Tj^QL>Kg<HH`N?3G=@$(>j&c<_H8q}txpB_ji>In2lVdJNyl>Y
zS3EsXhO?#CkwA?Lg;REST!jPgo?7bGQ#5z^Wg4BrwyBxtPnFnCb?CH@H)psSg-LgS
z>dQXAyFa-z4F3LT-nNu(rC)Na4y!NlvOTA~;G;7sce*f^e^)K&JlA9Y?ykqiKINZF
zj@d>q6H{5k@y5HK_PxxM)iFiS|6%7;a>%n{-3i0xKb4E;{6g}S?|#aO8-dR+BO{q@
zOr;UJU|nB-#~qeKKHReqaHlk>6?zg+mu9TQaIa$ymQ>+niGpLIG!ypw)@$qD?)yC$
z@r>?La#>@ZNmHRd<V>YU9c>fIx=UVo((bfQ8Tqi*Go()LS%2D4vtOXS<ZwBR_nXd!
znpM^Vd#H9GbJEXymW@?55>KnP<b_fdYZt1a=~6x&TIrINFpa|6U}@-tdB%C<A?MV1
z`SwnyuPZzWcBt9dW5K>qji2c&%*@8_(`#Dz%fWZFC7txaq@2CmVy0rVdqhILw%>5H
zOdk+pn$AAYqI8wIO)8}MI~=nd5A*R&@$e-T@1d%W?h5FaT*CwhEW{ucSNjT?(nVhz
zKdv0N{H&dt1S3%Q0^Yw<)U`)KJvEgrP3FTwuOFK8Ke#k#Z5<1`=e?&rpWZe<VQj(p
zdlby5F9x7XvL_jzov>%y@i{tm%`3ahU9L~&__zTSDBHBlaVLAupLF-R?ols1>W$6z
z(e#_L;-PYfwo(xqsH_iWW6$U_`oL9ukkf6aN?EBqnA4OBjIx?6rKSbv0u99;j+gRQ
zqWnhp$MXg6gUVl5vk6$z-lYFn;JW3iSB`g1hPJ=y$V7TFm@W9V!GS_jaiY}MGAag|
z?NgdFk(my){DiOh`9AaMTzTF*<85&)jzXxQ^pz=JOF4c0ZM}xm>0B6e?lejTD!D18
zoc^S{BN%dO$z%3F`>7<p$G{h+1`1wKau?RSU$-}%!joHG^REu4Ht91{o}Gz*sj#(U
zbkba37<2H8D2%#yr?(jCj$bisN(!30(RGc>Q=`Grfi};H4Y-qM+jN6g1%S4OCpp`j
z#Fcab-c%JoB!5>>3(~-;X;C%vd!`CK>3F_Rm4=-Yek$Sg^jGHRLn|L5bt*Bm5Dv{J
zpIr#AIV0xF+vAqqZ-%|u1ux|-IaZ(zrS})KZikYJbDNV^!ED@2S;=^i$FSO&N^%g_
zs?YaEgV&T*Bj4q9R^0K>=(L|o+SCSqOL_Z>hOyT7*ZOS>$<)?lKD{;R26^kD<fJv0
z@+xVh)xH|Qk|W4O54}gJaI3#C=bv`A1S6$_LEj-G&FUjPf%Uhh{ebn{y64vIvOiiF
zJT<k;{;y+4Kl)_N-(}AEm%K~CrQy#UK5w2(_TPJ1?b*Elv;FfO>EG@?ZjBTVZR`8Y
zx@vFk>X%ODj;(*d+qLOmd;5P>-T%Yqr~GFQ25%&tIq!`QXLEAsBNw-Sap&ZS`nj=x
z#6CIx#aDX%W{>m0p*jC`t7DhF!x(z#{jb}>3&#G3y2-#lbEUTR<8y;IEbsWKa7VI#
zF8h=6Q_~ZL7t-5j=7I@z_eZl==F{iLFaGtw-|a8`c;hbH+@ZeP^}@wZm^+Nk{#@>2
z>G?m&UCS<<oeK`C(_Q;lrcaF&-f~`f=G><LRju>|FLWFYj-4Dl9n8M#!rp7k=em|E
z13w$Q@U8R7x02V6?tIaB>-|+bJGs4M@}tKO&E4<)BIth3TD$p~gZ7p5)cw!d=5+St
zrlZ+sE~y)4_Y28QzuxuS-JP%WT(J%w{-FKB`Y*osp}W&lAD@_-v;HQqzh+&n9kM6)
z&#j;Q;Yj+S;C%9Y?#8%%Y;5F9SG-f3HYcB3x5NDxefNIkjhu0O?1L+v-bnHFp0Tx4
ze`V}gKXi8B?myfyusu8kbNV*z>U!oI!8eR&PyK$-;rD%R;LrT@UDpcXf0^w)u=c==
z^~Cz$wjO!PzA^8Q_4FmbeZ_mLGXBEA4)55eubf|g>hW(LzMy(f54<lo@Ec3pkCYEr
z`Zvw|-5%$@Z=F8Bw|9KD@L=D<JwLjz>Fn8oCyorA|BdNy|Gpibe$9QA5c~hJo)Bf|
zSJe|*b%AC<;npWfK!2=WP>^7`NFrb&{OVwo+W)F2;eDeLLEb<f+!>WHs0L6IIDaI1
zaL07(!Q;<H4}MvK(W(TaMBL|9y_|5`r}%MPN(54j;4eaR6+O#eQ9;4qv5CoNqlYh)
zqkvXw5cOIF6@~Zz&Gn>_?K;>0U~*;9?+uT4`kfd1-}S`cz3=*C^R@>DHxA65-5R(X
zKQMRp#&GW5!R`ki|4?Cb#VY>irBl|itvi$13*JR%?(Aj1uh&|Zq;u!)vprXnuarKp
zy#Ji_@0|%nHR9iwF8%c>tN%G?{ZIUbt=p?3mA=W@`SxAAHg+GKsSSSf(3Qf)t}}Pf
z6~>P5@RGA1D3AE_6HM%nc;|Y*V7};_pDY|Kzg((a?R?!lefQOk-N!8B(PeV^&$-+E
z&hyUe>eP4D@b^l0ef7vLxBOt~>aNP6wTAa-g>uF<|Em9$tvlYmEBM6Ko<CQY)q;1d
zz4LGVr2{_-Z>Z$6m34E!`u36ZrCOi2?dM&c<d?nI9cS^a!NHC1I%X{ne$#k})H9_7
zpX}PJ{`_6WANmK>&rRd&mi>Vz?=N?MKDo=cj-_|5-RW=S6tTZ?pksXb{>q+X?b&62
z-LIR~p?T}*+2>TS?V$OgubjDSr}<oE!xLL~wC^C{ci*_$>3d;OA3Ju};yJIv(bi?Z
z({4X(SJoY;a<I}p)$@_?Yw&E_m9u~Q?4wTphEfzCKEPuKIu=SJIkwY#Mh&Zj<;q`w
z_A_*-|B-U$!mYWH+#iwlt_H&uW2E%AxupY4dHUOx!S_2a4n0*{7<|taQtrDaH+Ijw
zp6nVtXBp$U2Rx&HvAdF;-F>awe$M>5O=>xPaMvD>O2vPiuXx*Dws$Y}6#m>kI0#3m
z+6<obl<RIBW2^t!*D1g(kND@uzSJIOE9s64zLcQM*Ms4873;<DhCh7Z32UE!V1Kx?
zYu8}UDW_PLJ!b#mVr`tiAngRt;n6>HVgD1oo1O~P6YGwZe(bMftXggI*t!>=U+{yu
zf^jvcD8n2%t+YqWJIdR-Cjx3Iy&(A;eub@9DgPKl|HfY!+;;BNR@HMQyiqbyjyJww
zzLvgBRB>$U;*x(LX`c7bTU-0HZ+f0_G+g}A{@&i1c42Vw)la-JIc3hJcRQ0#@pFS0
ztjf9_?b-9z6}JA=pdx|l!t1foYyZOkkiFaAF*w~Zu136h3kp2?z|^*9%wSz*-SR>I
zEBiaG@ciVDgfLST-zk<<Jp6WfDqOr4RNmXcODfFb^v8Gjo$ob|`Id9^?7dGy<)0^$
zBe^H-x$r^rFf=S)C|#&6ysK^8|IkC`iYo8$5Bx>xL^(Hatu<>qmO4qy2M6xBUQ>9e
z7yKvv`=+bkU3~3t@7$i=Ip`SAg&TPjks7FMFMnWam*4qm&PsS6`V%u|vFRVzKIzY=
zkF^i}DOH5;7(Y$Ur*|fIc^kdCnH$N@O?_UE_x-8!hdx+Z{5?N7)?V9ma!e_BblkZA
zalglyR`6!KyS;M2`aETaW9g96+0jCA$#;$!#cum**uFf~>6_Euw)T};u;GbyYmLDL
zZ`<Xwhrj(tQ$5i>D}!@0m(&D_bmv-b;WNj!9=V!(a`)HO^sdjoQo2-IQl0bdGnI1Z
zIdeiCm~S5$x?EfEdcJu2+Y8>&@Objur8oM1o0jekz0O+WZhQD@VJx`6GSRPXuy<c`
zHd<zp6n^@CLP>YJf*gK)_w+_f8}Zd=99rlO)SSi6BfVxesZN<{*W||gjH<gYz0u$B
zgjF2-if3*o51#Hx@1BYVMz}4QpP|1e+*s>8VHVG;CkJQSo%wa<&e8++w%yLXs^S~R
zAAj!ZhIy;=tm>Ix_golwv&Pjx{qLr`qxQ6Uyu9Nlo$Dq_I~MxYAR02?emuxOrT#-u
znd%+-a>?o+DWxm^Kf5h^Xz&grd*u9Nhk1Cgvb}$5u;PxE@Ac0c?;5Xl>oZ$(_g8xD
zCo6+JubYP7qfREN8B}_=pY_)DIg8`|MyjLs8GqL8w>Lg0@y)0F3x4-*XITHb>3)mC
z)@#0QT=%_oy^edvMuX3L<-aKHE-!4;Yuy#A6V0g@$2-fa^4{;1=AQhPHJ{$mevxX)
z&eEV#*0tctt;gQ$?kJ6$kCq1Jd&8j>+wKjws}aAF4jZiU9qYuY9pxT>;k0kfWpArx
z3s!vMjNu2v^X;RCV-$Tm7JlrG$GpLc_0mrqy+f(OWcZlXJ?(C=D@MLzsi`jV<S*Ie
z#>0>4M%po-Rvsn&?$l)HJ7PcWNi(m~?bl513m=*9P~iqWV-*Ho4ocnl>yFv+Wbhh!
zKJ$#yj;oz+znbkQ*|wqEGaV~_yr!iR`0hDVy?*>E|FE@w`gK)udX$07u?;F7498#c
zC;$YWiHA%>v6<?#w4{?E6xu)qBp=HqGBrX=4z|-2qxabH!SG1T$poh-%`o&HGnWap
z?#X$UI^#)5)<0BoCJQRrpLvr0+zs{#(=D|vEn60E2B3Ypbp7{|`<|znAxgyKC6wF8
zyD{<p0|WgX=D0mM8hq@?MEIo+=~S3rgG2Gd0_2$(z6dp_Hf%PF$tR?t;en_mv2zl?
zpm=J(sl*AfXo}dxgY}*We2;l!hEh5%K{zC3iHDAaRDgB_2h#4TLCg5~<91K%o*H-M
zrk&x!M0H1S#>nA#6x#VCT~#BHy`yy6pQJ!>;YfFURyr<Vk-4^f3@%d_0D7f^;k3Ui
z{o#do{{Iz*n+22qafP8kaQ#2|X;cf6_j+rhk=iawYd`6qo1gsZZ*Klr%johANxxL|
z4~;-EAERxTkF-1IU!VE?e5o+yQdR3dZK}34{-$b=kx9(lHtU8Y0`v{KYivyCP6R4n
zFs2FyEqlr&dz|5*s-{e|MAM$JT*r>j(gvL1%_=&5g(f|{6NT>hV}9o3o<sjPd+#6J
z#(AIl4n|`Ib=58~Mz9lHEf@3hCG-lUC6S`NxVk<r=EX~J2!f(WD=LqV*Goc>%rL5B
zDT=H0$!Rfzm*hYMO-i9%HpknN49qa8l3EJuYI}2Ak%D3>mSaniTkYO#YspHgwBA&b
z)m~*cyL+Eu(l%{x_m6w_&*JD%{DHyDyz~D2e4p?0<`?>vVXRPVrs9;eVV$4JyQ&gh
z;*7_Fq!+Qs+!EHfv6R`n_ak=FN<~WQxy{fW5@m~vZbd0srm8qQa!qR7qIILR!r~kd
z1uJt`^EXIWoVX@&C1o{DRA}bkTMcG{74<p0AW%*L($wN;l;@z}Q@X~6K)%^Tw6t+J
zPS+?&BdVBlw`y6ei*2qWBD%dz1vr!jLWQmslr7<wz<l~al!z8@rE$a!qJ)HlaTVMn
zRB%YV57^a5D9A)etID~E;n;q9f&%D7SbT^h^eVA3kFQ3I3<<<HB3S|Nw)9eCz%E6W
zXc9uYjLMFiYTUc~O(QO03`9b+LS}<awlVDA*p5^_P&T#KbPdXIskM}m5@KJfGv%DE
zCp?W{$s8zILDqG_#xt`sZl60URj5?Wx_!>JjIB1asNn@f^@hv@t6a;Up{7gKOmwX{
zC`-YCiU!)TBVx$ZV2`vV=Su3FSY49J?U&wAjI!mOfMO9MN)}QRsA_&KTCZ}Y`AEu#
z51LZZN>US1q*aXwBMV{=g(AQXl@*mt(>-#~GxN?2HKLk;j$6?OK-U9?;p75oSrii{
zi%RX>X5<67#1Nct18VqwOmzJ0x}2`v{?%C}hRm$Gkw$kv%^aC!xDd#f)rzT6AaI;s
z2ixWs3B<BX5md*dre~Z?FyAqYz|9PkB`p@2G3GlSWTDwew%v9rSM6guLTZ_?U`QS~
zZG%tSqIAPLNqL)o-fg8JDy6d+K}w~aGhNaOvH0<q?3nP1a-cNcDq_`d4lB36{`8z>
zH)i=>Cei6{rB_J1ktv$Q(&OfSc>n`aS*p#H#_3D+J!iqRsv95P+oCG=Apeq@J3)zM
z6_TbCsD!=41)x()XC+g;sNNPN>z&toyyl29mP%F0bz9Y)Y6rC5O746v-`LWa8SWsm
zn>%Dd@7HG?V=NWv9-3n;M;`GqYpfcEJUSNf91>n*<-|_<2MrthDIOp}_^cEr;Ri{4
zg<Q~mEvHG8k_;$T6$DHP6^N36(Y=Py8UiYQ!$qZ4(w=JiOi32O`|*Rp$($}jMc4nM
zqMQ?cw^ERPccVMXH2oi^HYse6|JOM2Kg=?ae84y|Y2qT-Z0Q8~7Uw8Uur?dN!FBq{
z3UWhCgCe0E!E}N}A@IRIJw3eStjy?!;S#AJyjI#UhNe?i@!)fTX^~)R`GILnC6;1p
zI#~Gp>x@0f+VUtZ7cleuCi%+Gm8fQo@?cuH+7{E|io)Un+(cD!mBv-;oT1lB?gOU6
z5p|$MMM?ls9NK2+3A$p$9bRx17Sqxx%qFC+e_qvVx`V!yMrkmHycMMHK+A8U!w@m`
zI6;GV49Cr>aYyAz$Nil3_IHAzMJl$6TSRNg8bq^Ow322^C*;)&6m0(-gEW1##?5A~
zn0w@&RVDdAr+G<BELn+E3(8g~>Eq|yn*eHsklGeUWWQst#wyMV_4G#iu_sq~*_)+Z
z^AXVxNbC)Y?RG%u)mGjqb=l?43{R&Nuc9IE1MOErG~sA^X`W^`8PUj{@BOg!KCx;;
zdNlHRA&s6Ca9u}`ic0yVNSA5Rq4HqHP_~nz0F4y3Xz3{KrwZHp89mseBd$E3r%s?b
zvh^fOAs$UN-o;l*_69k@fY_T<u*ipb&YopmH|P<Ms$N+ztt8xMn%r!`%>9tMtCy0q
zp1VWlQ(m@iyk^W`Em{g%nO2)P6(<l|mg45>{1}2zFEDv>nElC*{#jD16692d2)WyW
zF2n3H8{68l#!*%?x45s76(dLL#yj#0?H!*NhDEJd(b+-LOXepuX`AoJ2XtMO)mLT5
zk~v|8Hs&|PA3DRrPyyDnL1yGn>fI49Q=4J&SDnm?Hy1(An%-2dxw$2GAg;}Ev>@hc
zHcS4@ITj1L@t@&Jd?Hw?GS{rh^1c7_7`1f0Y?2LZ&uW7(qd)J=XLmovNL%_bp?3tQ
zjd#WZ9l@52{I*@bVv}WCzt3A5El&^T!)wQ;sZwf1bl=9Rhi~j6LnwI5uoxucRkh$m
zZ?S-Gk!fEk6ZQ@eLgO1UT<cPej4rEf#&CQ&!n`}Sd~fxtG(CPPg~>Rpj<sRNyFj`l
zM%rd~|ELF%0xkP83l*~%(<vpe?-)cgsqq~}$4UD=!MRvjn-m<H8Yhk>MEz(&L2}2Q
zh=gYChZ&D+JU1jT=7p#_h7?*^iJX-I7m-0jbM%U~c*~&=Hu7M3KX?39OCa;AJ*uU>
z<)xu4amKu1IcF(xV>aS(=y8gp@q3qg;wOlp(Vy?oA4`_nBlzU@2<8EUCh`vyB-xM*
zX``}BMfj%RkYp?J(9i)AIqLWP88xn!_$)2yK?cqGDzT@z86sS6Ah>oBZynI>#>@am
z6e|Af`dH0!l{tIRN*{|XHB|ySrU1IGG}ur9B-ZR$Fs&u%hPST-(&|=3ZjzJ+s9i&B
zk)T5q+~f+Hao`;y9dVMT)lkujhl9LSl!_B~+YC%UEWC9(1$6}BHoYV?^Bhk@z2x_a
z{jT*%H_b`AG+$))Sn!g^hF8iu8|rY=Qra|7!Z1pVeM=DpNr_%jh4XK|y1}+4BBhf&
zD{Lu_5vKEcPB+EFEWun?{Dxt-LGo=l#;dB19K*e?k<Dr2JbRGGi?u;(+zP#{??^?T
zH>f4rS%O@k<@rcMOK#qTPDw@u{@t?bwEVz3;J(JjnB+Gt-9tx(A%85u<C2=V^+C%m
zX>-PcZX1<g=}XH{T9H9-?V{t#3LgILEx$`GP8|!iLd6sdGoHAKq1NPaBywPoAn`V#
zaE|)b?+67COq+<1lJHQLA%+>9JZBinoMobJU$^>ExaeW;dy(nnxwdmuD7$Gn;kxRJ
zbj;R5SOWIjY@v`-b1njim|T|3k3|?_e)qq;?VZE{+B4kQI92#=<2`B@{&QiX{~6iX
z*8WTOSF*8tiGe@2wtQpTQ*WB%nV#4L-JZFZ+;_3v&R$zM@ZGoR`>XeM>n*R-rr&M2
zSvzv{e!_lu+hq3Aa>JF8TGQkC&e6XxuiEwD@hxvR9XT32&ySIV-x$wKnB_-~Jsg`N
z@7i~A?bQ!OTW`}1>q?>RvtPKU=Pwn$cko-grs(^{4~@cZ`6=)4Hy6y`vbN8k8F*pl
z?B-oxpQLX_F18NjhQ@d6-4DOL^@jYf$MqLU%l{SmtbX>{`$gl;`Fc0YoE?aLz`yix
zuXkZ>Vj%NjN`CX?D--h*PIqd;*!A_<*9Ugl&l(faiN|{7>CFc_PmX*d+c`cZ$jsMQ
zf8q4cZi_xmdRXU{x5?r5Bl(jplY~9<#cg}v*pk^>%ir0Td^6M8G}8K5Tjs-}{<!!e
zpVX^=NQ$(9^wNdsr^xl<kzyh9#+E~;>CrYivu(@4?xFFHPmPjai>$m_qmT1my0dux
zbJUNgaMnO4+WCYz(f`GRIN#p2NGI*iM3*1CchGo#wOvjXPaZnonth|Ova`Rz?R<EO
z{(0u=*ig1%sneM#R}K$E+Vk0Aw`I9{BvlyQ&JX23Ikv@mbl1^?v*O@zzVcaPW?+(@
z|N13st@>4a*G=z{Q{`hR`tQA(TRG%7<?#=_$i!;*^*=LDt&SX9M)uR|Pn}`+uDw3!
zXB@1r%M-PqBoF}GUro@WpLp;O0|kH>(eG>ncpv)zK9K%{K!I52{gdmU|CQZXLH|vz
z!zX^~jQ7USg@X3~(z+h+uWA3fw9h{hYP_E;F7du~`5IQ?|MOTu<<#E`70f&9EBC|3
zGI9^D{2xCL*#8QjXziW9T&!(D^1<fL;#TeB|GkjiZGmrPm-U<Thi!YAd}O<zi90i~
z@!G@nUA_>OMz4VwpDIi|G<r6>e56L+ihc@Ian<<vscb`d!dwAYYkLNSJTY@*-0ZkV
zY3$A`#<<+hzuMRn`)<oJTL^d78qXL{6tgw6eB}eA0K|SR)%VQ7r~4|OuKq`S)-SR*
z>OHdg$fPk|&r2Mgy<d>AJMxvkSgV0;bq;U8xeSUs?)8eLq4M48Y`2&D3_CV?>RY?}
zfE+)_Ej}@B_Eyi<ey{C|;ctS$o_^)9eM@XR^UC*SjhE+7?9Pw)BIdK=Z1~F1#-7N5
zGe`w6-Wb|aZ03{f!mVPh6Ii*8KW7A?>V~)&AbDryaQ64XSF4warZ?zAIp9Z2-ZN5&
zvW$%NiyYD$9_oMu9f1tdvfMw`cZuz~vUDeFKPz^9%{Xi?B@pk>f4g2Qq#7c-vs-UC
zpNjxpo?-mIAXDQr+l-Fq>ss~lrDKVO{Q!7~8Ibad-2<QHQ_Cdr>DgOC$~zJFnL~{;
ztmhS^A&5!##@aVeJu=buhPPYx!vXDkwP&2SF$YY#&Z(^40CE1o=VpI&shX>q$G=pE
zoSOBn4CUFIKS&=G&0;duIn?ne)af5U?cWz2SlTYMa-ZB@Sl0J>qqB5ye!IALP^2b}
z-x7_qZ#YZHklD1DoiHaGdWBZ$ztvTHreYnU%^e7)tcm6)^b0;VoCxDMDvZi$TZ?@<
zayOe#E}GG!T%AnyTCJReDL2$UjYNREtKWFC-RK<d6uX}ACaXO%22FYXkQj8vYt8(&
zjJ=grI_hJMH_M;%zE!sozp3SOr&EZT<W7D3wyZu|+_hr#RF8kT(HZytjQNG^)xr}W
z>%24^TR8D8i3c)eT^B8Xbwx}^I@!qL&MDKXWh*K|VISSbMhCbZwNC-48Xa_jR1WVx
z1+Dk|9gYx3_(H$eNbW|WJy~9D+uX5;nIdmKpm*2{q8z?Q3or12YI1>uzD4!QP_5a2
zw$UwOIQeaX5J7a!_>`!L2~tC(>C@FGKG;r|MC^`teCu-CV)(^sPi@!x&b-LT(?+0i
zp>e8mC-<#p0OMn0ZRGZ5Be#^DWU{;d<Y~mhJQR!Bcd0uMUHaGueCeU+{k63}OU#FJ
znm*~hl~2kAFB8P+Hv{v{;6^{O%wIQ-M826#zRWtV;bFdHAV&d6eDun}GySOde$|3B
zzt3yt$(7jdoEhVPmA4xgb$xdhSs#}VA!ml~q0ba|z3T;fP*j!hO@Qie7}ho<#hyTI
zKVq<27PsIhq$CeVinJLk_+F<kJIy){7I(d#>Ob|3#lDH~8?0OGqK752u%?{rb*vrA
zL$o<drtE*qf4@*e2y1)sF&=Z-DKhT%diU!x_J`h`D&j!Ae7M?9lXA#AzJRQZiTpzB
zp<&5x&!Qp>w;A~wj~+9S^pLz~u(|Mlr1Idt_9hyO?uBc`Wqq-gZlR`Mnfc4asdp`e
z9dl%(KHo@>fWI#k+ZrO-MP7b_ehRH@)ZRxMuXr0W?RxqHeujK8ECeYJAud=BBTpoM
zxk?w?dWXzfVq2=yF>|C}(B^->jm4J)?2@_*DZSH1GN#d4&r<U`UFKuf3*Q3WI&|xh
zhs&F~_(NGo-cG0O<;=?>C32U&p|!7ykw5gpw{ot#vX*20o*dbDaup#Fqf?BW^b@J-
zyRElPH4|v&F)Wa3+0aougI62zSY9*wiam+uXAovXbK5m!W{~N0#p_$zs=Z;pQB2kv
zdx!eyNW0N{eT6p{lKgS8>vvh-T9&-)g_jCjA2m7#MDntCS<Hy!Nh3!WTi=tkhBE0C
zX60*<)7e^abfA{4JrT8U2>Q`u-rXV@(FbG_;f-EAMZ-aav8Ert^G!Y+b8guwj{Gj;
zTXN*4Tkuw2W8{`#b)(x`c=CB;*!yZNcEbrI*$H$<T+iI`s>xdG@lWKFkzs3X<gZ@&
zSlU=brVe;~$TiiYITF4`<N-%~VxxRGTTs3-RtjWl2@*9D3Ej{zZPi0hwZ~L}_4~sj
zz9LG2N$5+gk{W#w?hYmgFL%po<jI}J*lGcj=2<@>LYmi$LBl9BdEGg?iV3O9l8!;O
zOSZGqaJxYrgUvRP<t50m@>Nxo7If(n#l8KXU<jhfX;KNqPq4J(29(fQLait5lA7NH
z6jD==p<W4OH6!h)d#I6K#_ZUSAz=OrL;?sl2$g1&qbhC6Rt>*flMG7NF&LhdoS@Fq
z^U(I_@ma2v9z=2jspqw{4;ODg{U3i4H5jr!f%dwdHh`~>)~NjP+{E^Ye#^3Op+^||
zi4cJlRuBa6rT$oLFCaOL<n|+>vc1-h0KzbWPqSGl2)=?@2_gr>rzoj^-=EE_U>dZb
zk6W0NAl!h13gyvz$WPes_;V7z9t>F2<s^D6^YSnP4h`P=jAUq~7Za1e&V|IGzLo*+
zzAvp@0mmLs97Im!*rFbtUBeYRlXY&yQl3Ah@h~0nBOJ$<ts}pO4A6hdRQT(}i=RyO
z{x(wq%8t=oJctG3|B~13fAL%R93!pbD`4K=efd!V0NtPb5{t25h-*I%82sHg{?t$Q
za~Cx)WYpOKZr52C)@59&g|I>|spp+Aqp*Zv0;VQvK0q^K4a56f<N^?>4c(uW4RWiZ
zRmGS%Ie^6Tm}ZrVJSu{r0R~~~Mlfj+#qwA|-c_iMRj{22C<$Re(SE?=&cLOD)RXh9
z5@AJ$#}~WEs5EDV=NLl2{gpqCYsyyLc(9~`t>J>P8f8{orHZ+Or&Td%T4_yI7A%J$
z!sS2+8EQ95nlfJwP()4!0eGy0y{U)kEF`=DMYAo3gXk7Ybe;dB0W(mn<64xl2$LW4
z)RW1Gy=2EtYSo<EOYLb@TID_t%B0V*RGhQD3|y5=lXqm<Vj3BAMVCq_sI~0?u<VF5
z0(kbPZ8<~vG!G3I?Dzxl<cUO7!2eDM4hcK-_(tRriTnv)VI0x`;&7$*4k1e_h-&;W
z6P`(6AJHP`sU50Cb_f?JHGTNN1ODyTfg>CT=ZpJKn7LTf`=N?TL6j^grWHVU{1}4$
z(HzjVDtF{VY9VURLix@;iJ&WvhdGL-q%A5np2T-ZCQwLd7@Er+HcSE>r7HlEUx_#;
z<^Q<xK#50!^J)F2Q?MLUq&G>uyvhb0a2v%j;PZjFiy9wYIi#S=++iTcWd%}j35hMJ
ztz(x~B8Ebp`4DKeA%|RqP|*1g3x~zc092?tfp*nqN8&fdiii#itBb00di89+P*%vZ
zVO!rk<XMOm>+bEPKfrYxd)+-PRvF1MLQ0$n9HOL^h;fX#z&jx?utUWCaxl_$8=bdw
zlxR??1Z?(Pg!RcZzX51k-k{7y$|@PO^z`grM*%Md2!e24vxhU<up)39$k^ywGAnDI
zW0xH{CWpdfFgQMEKjb9uf4z?m4>Se0l*t8k*dPjpEOiBzHGU{b2_4IfU3WXwMs<q=
z{fAzZd<W%e8TPmwvXoFn?#~eB5Ph3HXSRjP=Di3n<^i>h;65$Hy+$P9$xGo`gQd?3
zJy>=ZFsyvk6Vf)8o<wrVBYDF+P6G7?mUlBZxXh+fUB~x>zqv-K4K3#8zgDt(@GG$0
zvg4>khKg_vhA>hhYLhz;Y6HJ87DC_!o?xhVA<ZH&6;&c`ene^VQ)tq`L2A>qkIqrS
zI_0QJ;+nDpi5n`k_UxltJgJId8FO_xMi2%vj?=(<u-p2VZ5+s)k<b`g=Xy$1ZQ4NN
z++*)?CF+I}ml~7!NIe;F^w6vUOBdKH!IIx}%#XV}7&wz=h&dgDaUQ>p29eOn)D&V&
zan&KvtF9=X&ZilEVoGI|l6~k;Nh$EFV?WO^C=01mXnw7{=9Elyc;|GU9*&f>p+>=j
z#Hw40uoI{d1ho#gsW3gR7SNN(coZ20r7-<y5M4t^+hIh5P)b9?0MRXh?U*U3ryi%8
zTa^JzS1Mr`2Bm|p47F$gv8AieZwhg{$T{J3T2xi;z~@LI`71=*Lj1UawvF$IakDhT
zltKKx1R*Rs0!(&L3UD)4th8o5M}rA1AK~h@C|VVbM|4#=q{SaG`u8l@JD5(RD!f)k
zrB-%6O|MBBEYVjZ=g{E^MaC`3TTp@7?Y;kbj*DbCX+?;BjH=f6)kEe?)XeC7uMKw`
zGaT{4sKpjyfRWW=<pNF9x~NDpYRVbA6s?)(Shm_`6MKTAH?yB~7kT^_A+V3@DHc_S
zo{R8VRsjXG+gh9n{swjUIB_z_qd|ZtBJ|nK<slx*2QSJ%x#O0#nFUXFZHgY9@wBoT
z$k17NJm6aAH!lk!estlp>zN@3ivke4sa=?PZHw4<#$IL03d`J-`kLYJ#5LK<xNS9E
zvjdY9l4VO~?@?pUI>*Gtf)#hwv^HQHQSUQG(GeL-?(Zn~A<u3t0*wjgnHlqe{15;>
zM#PdCu;LgGph0$3YuYOrGDzIT2vc2=tSs<c+pt^KgW~g&sij%#7n*tsR!d#9TxL`s
zAT9KPdG>|Yy^Sk*T90bcU|XinEFQYDP#7v8@pwle+76XRI+!gwR+R0P5|JZ&8U!~}
z)BD?YV7h3d7_~u@(zM!vsw@zt9CRH*2b=WF1O1peA3PH|XzFd{dD9}<O_ttm&DHcB
zk@6?I${UjQQaQT>E^ByZE4x;r50VDC@bXh~^ZhSQ##?C{q%a*GG1Vy%Fi~X#0(pRQ
zR$S#oK{PD(4MeEXei4YUO9y#qmH`BxFzj3aA-S85b}E1-IB!1VTqv0F6Z}izl<uTw
z`aiMCOPbPbnaU9UT0vYmVtbTm<-iJtRSX;GdW{rM2pKS(+1Gx51Jj?&uC;^UGZF|<
z4Gk<RiA5|G?L<+M6psu2jh^<<ycxWHEa@<gcCY6UGel!Xx6u*~=H0+Fx~~I4XNMhP
zeg3h;w#!rv%^2|kyI>Qy8c0B|V{aQU$a72^qijic(Evr_N6&v(F>MNwfY6J)6p-i;
z6bpA}ls2NXPzW1PUSm`%wTrIERoPB4fx-95qA06Lm_J&UWiuhRa3MJ9x*`JvK>$TT
zCJ#apw5`e5%WO*-bWx=cGqJic#u!JDOKDmC(Fp9K`UStV5U~qYD`-dlf<4ew=aya-
z{r1D;9s4R1B%B)<wrOPuA8T>TnYQiG=&`)JkGw-7faZ=2{n(omXH7@2-Wqh`VWx_>
zs_$Uau;@{mq)G&)9fOzyB!a>s7+f@^P$ESk6}=QJ%^1Y+%C1-%g-GH(xnPlx1u}t-
zB}bA!`CQP}og6=zO3%`GBl5u@*o&Vr+(2c#;KbArp{8jD1f&WG1{nyVI2gZ)Gj5gq
z`higbmlY2<p<&6Za3SItXh~y0(V3MDYb8|*B&20Blxv*m)~u3|fyX7Dzt<gED;b(C
zJq*wZDHo3M<h=c>Kgisr{L$j8J>>1i_NP9zu$(`_|GS--u-^YL$)}2UHuH;rY4Ckl
z7yd{tZ@x?6o^jWXPMJ3fH|5S_Ehp{j-9&%>N|HWbSfvjinX>M-+vBh+x+-69sc-Ie
zmh)eu_01QL+BdC(*<N`jRj0|*#u-{%Z8+4E8d*tg8yN5CI&k65NCWLU(9t`FrO-m(
zaL4TMmW9!ykDqLR<_n$X8>aC_;}pH_T(RL!1ml&v$$g#jEBnSfD&K87lPa$C&bR0P
zJo-uNVZDLE$nC?(@XC4p6#*|Jdn)^Hk6pDV5%cKvUjEK+um)M4eWiEw<kc71n=?<d
z30gg4U$M_t@6OWm|L*FSZ+86Nr4O&sH=`5ty|edbPSS4veEVm62EN$XQCR4tIXDQl
zy`4DBo*y_PPK(3QLdT~l@)pXc>2>q&u>M9<v~BN^XZ7+8dZy(%{jf!UzCaU?(y8qH
z&{Vdyc>d<9)@{AnKGCmV{0!nkj}G%UqYbp&W_0%>^dNQ&mw$&nVqZjOysOs#G@Xc!
zXSc<Q+0@7ucf$O0eOn~)>`>)|@!R|+-Cv&KL#vrD=)cV$p)JoFGj`i=^{@Q4b&o|S
zqWfRM$8KL8$~4%|x986nWWIIpn{N55M(1exKD>oq{$uvSeQ8YbTa`0U-LI$KJpadR
z!m6G$s{ekr{eJnwz0MCJ$+O-98=0>y-v9Vl|1rY94(fl2kNiDFKR`W}(Er(A4Znks
zfG<ewTIcj#waBAzAzDAI%U{(>KUdyfHzb<1eJR~VKR5v0zaLK6o8Sp!Ad$i$2e3T%
z*Xz*e{f&tceuWd^7@Ww37m@29gG1qc<l6}SBkKS9|4jW~qrdf?J;ffo`QViM?VFGQ
zZeedh{ePPEUq~G7zhk7VZt>(*c32#v%Vf(?y#tU4Miq9x%J1cOH$y~EKP4fi-Wk<i
zh+M0m5PGF=vNu}{SNktLE0TX@#NMb+7bcAhKPna(G_5zqSHo{@o?3^TqFO5^u3hRY
zJ}G96Ch{Rmz4SPFI9z$6K5~+bj);!sws%?hzZB_fui%W^v&lP~V?BH%dMwhv*mx#Y
z9um85x+gc!`PM%ddUt;idDpvJt?m}d@6O-3<hfhl_29cv-}N<V-4dJLUip3%BKe&S
zGo97sqsH5n)ACf~zxlzYhR82vw*qdyJ>Pe*@p(4z0o-xOWa`4^#l7V|Z%a{!O^2<G
zzF>b@q>OA#os6w)U1;2MkZenJnHt!+ZA>y}w-|6P+%F0^tMthvMDczEVqxdFGbO3p
zcZug{zvvXV4ffXNrYJWC4yMZex0>2fSRXVKoFWeWZ|sxelf;+^mtnvYZrGe#E@+(=
zg^AH*1Y&R5e<@cJmHvEpH3tE>=Y6AAEZ?bmo%TTNj#%pzwZ@6?Zae9IZT5$DKDXG|
z6Y0LRd#L=OQH6}0{K3(UMKJ<jp$0VSMY8g6wh{Rawfr(aZS>WKp6tXHIMCt8w#aVy
zqZoH=-l!cqoR2NELL6)+Z>(6DlE_YBkGocvH2b{XY^?wmjGJ8u3s~|%KE9MSI=*uW
zV6-Q~?Z;U!w4)r5RM!WJW@D?-@f)NWwOMrXL6d(<XmUy}6LNU-J-F|XJ+y=B-jGOY
z7i<cAUG=&}?tu$8#X@GvIqeMy;&fi>I@M~(<YM@ZF64PEwl+k%*Ew#lcRe5cH{%cX
z=;qdCb~y5am;n~<c$zlvWTW>ufAV*XKH9@$+8pr{3efg;%5j<8c<C}*<_kM_WRtJ6
zyPJ(}k*u@PSHzQMxQNx*s8<7~MHWHpdN^reX9Gk_vG9*z1;49b^a^^H85i>E=m0x#
z2Df-i(Jwqonj6O*%hJc^zmiMRKp9%(5Bh4&2lbA<1+pviSyX$1q=B4Y-`3cvz0Qj=
zxAc4(JUaGJ%J%e1tIgPCWNoey{!emv!u<SwS^wY2_LYwu>MH`d_QZ0_<PW|6`fkx2
zEn7dzislX^E&MUBb%I$ZB!5A)P<Ke$$mc0GE{1oAksD>C7>|5|T{t9i?|S`JJ7$4B
zixE`R>KuXS9ub#h0L8Hw9=%%CNG}2(wXD%;6>~?KtuO1at132!9Z4I%?S%(K+mv~|
zhN>C0&k%CC<#JAH2nn`9_TR9%Q{=wq_Dd`FuJ;g_{F4`q@wFcmUnn}BU`FPU-8N~+
zx$u<tLs3O!r`y;qhbwnpi6H)Pw^&v>=#BEX?XdeOyUj)0=zx4!Y=v7@Hgd-3t8Sw)
zkZN~ZF;+fd=d>Q<gBjjNO#+Z^<uEO_;O3gC^~J)6c*ypk#Lr5?uX(kEVO^wJ$5DZ3
z-sO7VK{H|7uj^lUh+55IRNorfGK{I1F<9%SXnVWu=AuzQ)lOnVCQXvd^0Gj^hrW}&
z=-IiC4)_t6BgXw|)kE4v&)T0Ywv9Vg>V}WnO9zwZBY9eTsCuU^Za?(Fo?^%Akk_9Y
z5{+%FhFclSJjoGRxXE`RDzl9aI@!lKP*w1@p}&0-nthXUBv<qpbEK+vX^&!tSBvPf
zo3dC~F0`R}A&&Poq(2mlH^aNd96@q1Vi#{k4oK)Zx1KaQ@@?oy<bjvl%GM^PPv(9}
z#2iFTxIP)}v6BhMI*DLH>@apVsEUC}c08z$9`kMqVqRZclSt7?)q8EER|QZLCL?bP
zZ-Myf6_duxmt^A3<!CxaA7#^mRRbm?;<1@F-P&4%@O5iV*Yg^YlVgoAUIyNm@Oci^
zureuW`h}+=Y)?L}3jbXqNBEj#hQJevR()gUMNtjgSV1(wil>J*>r#9oVO?W%<2wki
zrDst-QQK8RS|uDbkPKolIod9X(mX=2$bSd(!2C5COf%0N>aucon=Yq4h&iGCkRU0M
zVWnxo49#X)n!15}%K`yruvG$M04vCqj(J+KAhSo70CmmlNIbqcBukkfVaUJ7q&*T-
z-@`OFxOF3P{LcY|NIDF24=}Ql6?~0Zw(~i|b(Po1m_JdTlnm;)KB*}7?O%CnaK#^*
z`|KV+>h7!d{h|C(xgYv_!K3y}!GJShyYNvuqlJ~P_|pb>b-_B??xHtcYepED0c@5V
zgg<3)w)!00#tiqGjr;?P53Y1U%{*=mp^P2O6Uw7|A7z*(3>o?;OoWD<hdC-UKD??%
zXLgr{oC9ig$e)jFGX!QL=b+Y?>gY@nlbA{QNi1b&*ScGb=vtj4xe$hf<c4!r{us}v
z<ZkmfzxT8MgxUWma{Zf;yB#sCBmaNDu-^Tt*X{OS{;8kvE!L|4@Wp@XSL^KkCqLUi
z^?QHqsoZw|TU-SowG<(Zc}UN}k6^<AGzO#aJ@6~B{hbyphyhs;wlxmWCNTpLu_@SM
zq7vAOO~W;aN~Ho@Zbw)a5Np`ww%Di$9^a_&Qqk_Wa*kSBWfd)_7Fhh(ecBGQkjk3<
zl`U}<I|N`Y3x|#rW&<Ux%l*JWNVU-#4MUSo9DE1ws8G;hKn`3O_!108VAQO@;Jk+Q
zWq=C{7}`|Q8%Y{w&?qk(a7A?(&;lU=&h0@NhXHL`>n%K}IO!m`v__|qxFhh<cA5eN
zYH2mC;-@HJo8u`;8lO+lmL30IL&FZ`;G}SB2Q5$l$>(&G2;zo*8I}N2x|S@#6^>m&
zvcVitW4LyF#x3uJ{TD02IV!6E+zyshvs{)DtweB(c&g5Hp%EGHIBPmkf^QMlveN(<
zD^lv*t~lzk5=X%V6o&mOgM*ghB!U?=ZjPb|Y|tAbowy1o9%at)42P6p!cJ7e2=j3J
zJZElP`puUR_Sk?6M1q6VAdSZvZ~`hyoM_6l?T{#QREdNK5tJE(4*b}nUtOe=hWmk?
zmI0gsqC6=bj*KRhvXQfDkpYDa59{R`P<lOr)PTm-nu1ctS>u{fQPVeH{keEO@-*{5
zSwESIf#}Tv@CikaqwuB+iqA0>8Qx*oj>Hw=Sz`O4sNp$v+hKD}ad;E>++o5@@5P#5
zk%?de#r7(yN=ZV6ms#^G&~An(tem&pff8|5whg^HX9S+$L7OWBdQw~X&6$6eQ>y`@
z>{mgFiN?`dq-DodRGD}LqIW!5q<26xD%DH?Zd96Mz(|@YRk}fm104`x({ly~c8CY$
z4jVQq`Z+O-0*Y_oEEjNW$PVXX$2GQ8AdZqmH4h^HDG-0~_Mcu?La3ms0xpcVt9S<Z
z#>V%6qblGxUZ_d&KuNXzN94Z{+QmBo$ze#Rur!_qLcArls-YQu!R5G1!0dG<rFiN4
z?aQT&_^5M!6~+q|B=`iJ5$6=Bl_+VO!L%Od^Ya&c*?DOLfIHd&-lvyLM|0M{$2%DF
zpNIeQcnE6GGKT@a>*CsOZ~5O#LH_}vo@%*1$#KQFY(>dputZ|S`sMicI?AO0&aXQ*
z?h&^kEd@b7|H{{|H{C95)CC8wUTRD$Y2AqUn4XIIq?CdlXrQ7z{2xl}G^GhXyns(O
z!FtAdfe=_hYnjmi8RWccNQl&2#KJZgf+Lh7yEIF7!6ZCXk4U3es%7T^tD(i1j!ftE
zEUJ_Y%P<p55vLLu5b*HnShAq|4Co;(CgE`>CL_b6bjDUHgaxWaZ_YNlP8wt0JhK-D
zUAwBr12+F=0NupR-N6Dg<24#u;w|Q46b>`^d;=&+*-hdUv)iVv&c>*QNWdY*K8JWg
zsY9E7N)B*5#fs4MlpP;(Y!Ta-DLZ2)gwxH@y=20$_sX_EHrk%rVeFu!qQ*aBJm;q!
zAu1rP=xkouEgdl^N{KGIA_w9Y=E-b{uXc?UGK!lg_gj7iy|%0b_?Lw0OmhddzzB{;
zU|=hf7C&W8V{xUo>CqMo&lB`d$%KzZ*ry}GkayYE%IY~P<6J|l4A>psUWo_mZ<}BZ
zD0WFB=Wy-ArG#doa(r_hfjHtSRrY13WNd~dnAJWYJuePp8RvHW-%Urk#dp|dLLIg;
zv{B0z#b`8@wFD94iRiNJXjMEcWm@c!AdI$SoyYvF5Bn%tp-qSw#7!EAGL7q8Cw81@
zg)Xu}b3+|G1Kro&IC}15dxH&t?Ooaqn{`>m4(vE)h)wcQ+mrLM`~^rYLcua^YD^&q
z$aNh(D%-t<?2>c)x8IJx7)DM?P%4<=l{5@=EU)^FCLgf4NYf&!T3KrOz(599;TOJ@
ztyzeIEEi#p2rsi4<n_>%3IzMAgBWHh5<K@<cVwXS0D2ZwH&{G5aH;k*hLK2#2IJ0t
zNWGD;#iWg)jvsgDk$C3zIzOjVrchSmOYPB^#${SQU^vtER+p1HXZ@8iN-?;gBgDs8
z>)uygz?wnd76m<r-^S2wbOq38@;cK>jvGiRR^D+P6=0t`ylVrBHY1^04{2Sl0nunu
z%VV+{(sD}>PTbg+#gb?TAs8u0=uzA33M9=0dKAn95)7jyf<B%<$P&A(`Q1kpO$Xzs
z#*f62t`jJKjbg09h%shTEcYUhQ7GA&zA29Qdrrl&3f%&66#lX{E_4wJidBKhf{APz
zd4{q;UJvrodt3jt(x^!!qwOUSgxf9#6J^}w(M{4UUnP&QmcS`-$SEP6O*$bMAHQP{
zS%?ZC@`o`9(YZ>K9;}#}tZYbL7cSh6C}UlYN=o4+GgWanq?pnXWFh2PkoXGq(QgU!
zfmEepdaX;`RVwP-aLEk}^5YK$vo%)IT=MoMO`PL{=p}h~q{%lJ8ZA1f0+)PFpFpia
zC#TO@@qlu!g-ASY!y16mPziS%SL3dx3`^UIYaMWy!!EuSo)J+FY7=yaun=$~wIRk5
zw7^M*&X390M6gTkdWbH#Rw|>O-&krJFy{IVZ%0ewEOVmw=>JW3UFC<f#}}-pUFS=8
ziM{RVZQ{4HhhI1u>9KnTh9~#+4DXI~VC&ZHg`>s$`oYf8?TOZbE%Uu{#Q-^O-P@mU
zdn)@Q2>W~NmF%tT9ct%K8#7Ne*prd-zmuPDDt|N;amG9Lowe`m1>$sat;gOR>U59A
z&WQP@i?5oM)9o|EyJ^?5z2C{d?-VceI_(1!?Ulcb3}3vya?)sMDK{<l@ADo>O>lT*
z!O~(l(<(B58L^RcKW|<-YG0K{hmW=|y;}Z%>`3S2xOlVa((e>ci~l;qCTBXGmzU-H
z{4+<-rix>gU#<=3o?a?Hw%mQJ0pj!<U$v+5ZI^x_E6(iI+Y0h=d+ZFG8QzkZEIbZN
zobk?!;cIfJzAf9p$9boN1t4s0Yvy>Oe2?{aj&|$imuxF%zWh{q#^9B9kvV#7X73~l
z?);3+%kRpgM`sNuvl7{NG{TM^U9zgJc6n!{bNu2$Q#WrAy>9!l?0thyaoNtQ%Lace
zHEz9Qn@3rDWRhka()gEv`Mf(*ZcCBO!A!Zajdn-77I;@t2pem+aeicCbRsvEHxG#N
zvz=~tWUM}O{6;rj>X-eGrjB)&D_<Cz*!&{ReP5ikziP~m=gWV5?7;^4OB{^0d>sm%
zgaMBk-=+Q&KPCB&U}*>ASDy^~hVecVM%W$;HdxeS#VB!VNUHp=K6VyZw~a<57H<N9
zKCBF(kXpIuANS)mUipOhF%kAL@=wU~-%8T|20i0!kyC$j(BJav_D5%Zjg`MPgo%uK
z**@zd>$Sf_kv*L4IxHLgMIsUh?A+ZyyMH?(54;$;=2>Uj;ErI-MJLR6j~%=jc_~%j
zeX!Yr=fk=i!3(<|I~e=4e1YG}vOAH@<MrH(kv}Y!pwIT9+DETl0@e)=j3$a7g_OE3
zUMS3W)~#k=6bfvWY<*?)mN?Z~xs%V2yq?+_>8-=U*xm0yFM5Wp!VtglarRPsao=_4
z3Gr+(_Pu%EdbznjcD;TRn$tJD>P^11vnNvL<s*?|y?{*?bF~gYXtM^@_^)|Cs5kUg
zzu^5qywF*wk1gxZ8~5wt%cmMMKeS;Sv+KjEmxF@6vHRD1tF?nu&il^y^GgSw{e|~T
zh|wDhZiDe6Zx&^KS8!+*J8p{F-fEwi>(uKaJ<tM^_alZ4UfN*1A(iehm~Fvnh~#S`
z^dli&*w9gf7(9%xvGKl39rUt?<a)j0NJ!<49#NQsRm`w6<*W$M%?na~m@+PGip__u
zuEmTFmlm?eK3FpyKG(Vj3geyKVSvVysjhjETW0-`au=t{=RJsnI{=S=a5Gj5_pZ%K
zJ$Aazs0+Rhn|pa(wt(-$kYwbqQmL2M>bZN>U)%v>o8&iGWggxiqz3S~f0BtUuq=Ud
z$_&UpE@zaXa9j0eF|vS!fKgA24T;=7FM3sIp_;E4wJwQ42Lv+qs8P3W8@T;k4Yo9v
zCr@tffosJTfyYFX8DQRW|0NF01NznBtn_9VL`Z8hV5Pp!>2O;eks7uyzzELECn6cT
z*Sl~^97|1l$Cs?~9nV{=!KVE_hLUlo8|F8)woyPp!MZ=TmXs$X1gZ_GiP?P1y}P&O
z!k@zRSFU)z^7c{ePXTr(t?i;_jXR?^1zcysfQ#w-c0Ng9a`ReYOg|-TqdS}hhVMgN
zR3O_06VKK@iXXdbTgrX)4(*-lUI9%t@)qpm6ZTtnZV~cWJb~0h_k|e2ChvP;f#E)}
zwp$o6>mDuU8pFdpnK78lgFN<aVb#d4g|J18Sf9vU_4@O9`a7&~O~hU@rq-4Y+V6;A
zo`SJYJ$DKrQaQ5N=<fD#lJ1Y;W)D`*%x*nZ*nalsuyFyTwpYEAhP@S>{~Yw`uD(~~
zw0b9PPN3wU5=>rP-!NcH4H1Yp!*fD!0JfK%7Fr=v8SOTS+mAhBpbd_EG2F2UMknL-
zIRXtmr1IhV$YMB#j^<GiB9Vj)IaAwN$<%}nr+4uJb{P;Eb;`Muw>x=ibj^m5NJQqy
znF!R;W8W5GU*qmT^}gR*^KIeZk|SUKW!){!hdcAgkBG8b0cjgE-|%WaCB~))M&oJ8
z?jC#dIoW@ZPr1;MYoxZnwwGPlO!_=HEHyvUU<ivmm;a9fZJ?1Z?sRZRu@#XHb_))e
zoT;^AnIu<six>XX>C4A2dx!I0tu>16O{;*sY7a!rc0&rTwG5p}4BXDIf+&LgB6lpL
zN4_OE8Am)@7o%+Kq~9oBXO{(91rk51vOV=8aw(pK3s2r#GGFsh1$Xs%J@uYC{u^Z*
zyAFFES&76KADVK0z0N-mIgZ%s_mjN2I6*>Z3X6^C*q|?d?TEjh1NQs9R=tXtj{GeF
z%chkKt%YMI>O6$t=q^%X1hzBlChr&WwVl{2n>vWi!9ZDJuL}$FZd9TyOm&<g2caXq
zN&^?Zj@v2st#$Gz7sJ?!>!gvt$&r{oh3+M_2T`mH+AM%_#;g^q{c9Qdhu(QFzto55
zOZArU<Y{@!_5z)@MGy{=N^jR`dx@vIKh_B;I4k!F_L~<19RnmM3{ScNGd<t|z;>O~
zqrt5h-Et9HaNy`p+9H#Ao`w<oxZ^`iN73thbEMDipaf1M#(RR|jSxYDendARw^~VB
zn$h-7q(&uR=tk?4ytE>$^jfu$48$=8a*i=FSV%r(Q0`re$c#;wT6OUW84#-sgjjKh
z(<#YHuqnCQ-!|x&aDa9<2(xV2Nb2T31fz_clkqS(*d{CvfSQ%GlfjYGS!{`><T2Zn
zszm-F{G_2eNY9&TsyT8i7AlsK-&C?Zmjezv0U#$siLj8jF*L&mowRmN&goK?3Z5cS
zt^Vad-*D*~tx-~Td@q+-WQ*{tI%?%8+~57pUq0c_0@?+@?Fa<c2nlnLSpl*0`nTv|
zd@Xj5l|w<TPXT6l`kD<H2}Wwjqoc2^&jTzB{f_Urf_XwJvHt#o1Cz!m$^;nM_NNIL
z+3^Np;UJh_uE&m1-Epcyx#BCZF)vKX5%Yxi$>C%mzn%~_S%(?FJYEA<{yIke<h+yd
z?oRrSdH<xp{zvuKHTw3y_!+Fe{@1*2|6<=?e~?e`)?aC#r2hEZQUFWd_)mVouRu0`
z{0AlO{_Stqe?`{6az*)z3DrKwu~;)ACs!FZN3dbvX@(5uP*pEr31lO(1f5k}6D1OW
zo~|EM4y#mn<AxrLmsO=3yHh%BM<lIbpTo4!;(!Sp&b45ER<@q+3Md?c%X2nj7ElO-
zgk=bY18lHMBT5!z^11$>Q4$Xd@p91gYVkli=qOIe)uevp9PUO*<HBJYQ=P}cyMzX&
zuB1T?(Ma|B9+1X!#xzBssgyB-gB*W32eJ(WtSc9BAv>sUxUW$Pw5@Q)cveyq#LTuC
zFoq}v|LDKH=7LAWp&M$Xyx&e6ZN@YS!K0m^Nc~$+yEBmzpjSy9bQG)zL0`}l81L{v
z9E<8G<*HOBz?$L@SXfP4B^Xt~yTrl*J+glMv|XCPE-Xm?55{pLZW`S~34yLZS^0=B
z?81FWY@cWbq<=@CX^?{ksn6boGP+`uswUGwnvh+m>+1&5iX<fC2C(yL$UEN;-W12q
zmP|=wqg8zCvqA9c_(91_2@+ThLB5D^Rhw*(r40-w1RG1Plu~`}FMl?}w0MVT_e>pn
zS_6scN+L+4g{?AmsIR~P016-t*7P)kHZ^aEy`WWbsiq;1ROTYn*d`^9eE$Om%-t=+
zpaFE#xD!+g`x2X`xRaztSPTL$kV-pt(~`J4_|K%7ZD`)PNL{&I{41YDNy~u>KY&N+
zC{^9#h7UdVlC*8BLa`8lz$EH~?UVz~pm3zHoX|~ZGpitWQi1PF0QpF=-thumdotc<
z>lNIu3P8506hIZlrjrQVLU!lQXGp5FX{8R&8(8+e7@6yjtDwVLGPn<H@b**xqeT1c
zcesl<1dQ2@lcI))VTd?}`jaGnf`zzh3iBMr`4xXt>IMe(O|a834;H{fm`oWKdittW
zUFD*S2Vp`|I!xL8x|8u7Z?N^MHs~7h;IuIE3pBpLP&{EFx4EInKzH0BZ;De&xFpuB
zbaB&V=ibtO@TH%$0L)qp%g6LUcWCf&HI6#sH}!S$>Nq9N8X<jzEDnIyXKkuca!d<V
z6u=EoAIzVsZKaKhLIh81{G3<XSOV?^_GP7e|KV3aGz6T8z+gCC|J*bu3D;ttMhQ-Y
zx`}^2L&R7A8)2ZDScAOOsBr*hs|2#d;=r1?o)WLYI~wITU4<1;9^nc?@TB7|JRP7d
zwC{hpUZR0%!se*5hYq4`0woJx0*XDSLpNSjL?#RybhyY{!Dx_Ys9Lv((=|_t&(1Z8
zcdA1o$^t@`tTouM<HHvq+>DdJaTH9+FB(g9!Js5i3RE^Ghg_j3H<;qY$d#slmaa2&
z67Q_4N{k10!1#DnBJ)8v`fXU8ATl;&;VCBr+ia&>cOX+N1riz-AfwP54D$Yj2Pw9Q
zK}sE>MQ+0=1Jz%vO4pHrD)uF)Xa=;Q$4X8;GB98}uL%&@3MwHS@TWaL1wtC5K**&4
z>>Z4_Yu>9pG`;W+Ke0JfPbeL$BT=4P^*yv4qL$P&SBHTUd6F)GUA-pMto9@n!|*Av
zWku_bMr{_R?RM2shr4-MEo%kB1xW^oLgu0pTLjpwyc4$B@Liv8CuP+cbjNv=s>C1@
zku;1CrCCFQ$=2$;B_{Zbk>jg$q03Yk_6<vj^kjl+N4$eYOS}@f|3_O&Rkz)4psdKO
z$_jOuDHW$>g&I=m*#5S%q0*WP=|O8wcj84?<T*Q!D2rZ_WfhMJw@l&%r_Dh?g*zNm
zA^~c*UYn|cjEX=A(5gYwLH48yte9iL_v9__3z5OGlCk8j=E(#7uNg}=rdjbo?(A&M
zb-((X=OQ_W5ba@R?I7=Q?UIFkk_}P~SZGLkV}^51|JAXaB`*_bXLW=w`3^yZ$UI<G
z9+-wDNQ@)<g1<(cusjhlQdyY&@$w9<oVL~eY&)J<VOzw9dy#3I>|<Lnn*?*mSdi67
zDX@F9kd}xCt7hY{%&)8|L~<$L>r!{q75Lu<wtxEPnHAOcFvMLb+Cts|%KdQ+1~F0#
zQdvxI6{O0P9<T=bL%~ddSY_ApijIR_H)kT2m6m~Y#Lo`_5OyTS+%&U1e?UhYRYD%T
zYe)%}LFjiqG`ayGeZ@{{fAX$|65i?{a$`$Pr2U@U&va2(7V#boX<Y%oC1X^!9IJr;
zVId@8o1ts0L{xO#L`8T33S1J$QyDBfN@<bD)j=1vs<ICvm?YgwR<62|BsOi6GSQB(
z-O2=K@nJr8&DQe43A-G0#r98js3tZCHL$4+PKOAOUJXQ53m;mKBbHp!tR8&Wc{~6|
z@%N7(mPw!Y#{>O@lYZ+_crvN|gcO9nW4JK5GH8*`vh$>hzAQv7O_6DhSit3WNY*_(
zDu<(r#nqB)A~dR6gYK{Xr=N{S9u(aSZ3tYe&+Sl!lg=6TFp*BR4^jyhHNF+|6C5~4
z1hh)wVJbvf7>^mm?+W3&#*o;>y8?B>=OTlWkG9)&g-=+eqEsrhZVRjdO7aBakapI?
zxGa5i&KW7&+76l3E~)uowM|Z0OA$6_jf>p*h$|5Lu*-IF^I!blgT)v>LuZWY0~45a
zz2^#Q9dbxj*X8GE$vHu{Ix0uyeb+wO{#r3mZZ{5U@ivMM3T7$0Q|N+G<3=oo5dorb
zMLE9_^DU#~#}X8Qkx@sufW2pF*f3-Ra~y0<Aip53Y9OZ9WEXm@0Y*^yx{xtY=sKl)
z7u`VD-OMEI-8w_}_t|e+<NM32^uWka&wzOUvfbKn@o@VZ>>>FIi#}y<F{8)yy{@^<
zXzt%$KeBJc-M07Oy+l9Xe&f4hsGj+diO#VE$ZF=<&Ao2Z=#V)7y=?2D%r7Hrx3gS*
zy?y4faXt}!+<x4yw$kxTx0!GA_kHhSJp;RGH}7HD53pfF&71(>5z(`@I|j@=NyU_P
zhK?@uPneaWJJH|3j^y8!H^qF^0Lhg@qZhAA_YAv^4bwYE$9pCQx*a&EcioV8mLd~d
zr@GE~rzsG2Z?#pzW#x<g^~(FJ?ES8VhVGWkjSCQQPi2m=!+-QMTdc;zkDakkY<_&K
z6M}5^ywSG#{f{s97#FT!sJO~9YnwaW3G+?!)X@C+P^U8r-)nQ9g#F3CGM>K|Ay3m@
z(wZ+X?`>l%=kE^C^Iu~_?)i>Q<yZCH?9KKLObf=v^8<3Csr;u-;@dXFVM(*8kq!x2
zHup-%0_sMkb)Z+8r&+rZKiN{&KPwpdn%#PA0xL%Ii&nS(TG8C^_9y8hEf)*f3B7#!
zQ0tFA-~QBY<N4v9ZeuFfni}suf41e3nKv_CEjy1*G-Xp?pW=^1p4@e>o4x6FH@&#I
z{5vi8Mj!u)$oY;TVc~<t;(-O9OhZxRjMfR(iK8?AYVp;R>t7e}b>;j1`qB3=@l$XC
zsBsY1rGJkzTR3P^tQ(kA{P(Y{V7ZA!?7GAm|NVH$xxeiAaN6*GicPPtPS=ldF0P-+
zHw|qyete>T+~54~u<0re{A)Jt@3jiolE(radl#F@lymvgFl}z!#(Inc3r|dy``*f|
zhJkNDh#R3dPAs>5#^`6w#CU_5+ioTg8^4mR9W1{;WSu%_bU?h>DBp_A?Vn6t-X<Et
zu_xBDwIfsWhx7Jw+s8c!oJF#2olb)rUP>+-tC8$dVi&ew6m*460!=?ZRql75^$*R!
z(<5_4ERp6X#+|op@VAda-uKnk1|uh5XRSDpPPE0swa#tqE$onpB>d6d><8gxL;q1-
z?&>&l={~JtpH&z-AOi5VXWbGn-jSPkd)O%THzMEil1GiyW(ZdP;7dOPbMGv)o;N^^
zO>kSQ`J=IiHf`<mE_^^v>Xq=1-~({j$T5iH7JPx^Y3%+OyFyREm>Yzq15P6S!s4-q
z0HQ%ftBb#kT~PP>`!gQS`-grTMqzeg*BQgAE`qA(aPSi{2P%3A2n{gFv14^(lz~aX
zHKLc3ouFvQpLeLX1Ku7F<xSs~#X*)nbkscei(cgxAXThyt^3rjrasxVg#BBq^<J>$
z3D_f#)E;{InkV7@P}yDgeOQ1ZPKhs)cZ&9z!uK2)S<q&Z7^pX$DO`8^@}^m}<Qe^Q
z5JuL*Fe%yUs+7QOdh?&w;dIdPhX;{yK7a-{$&}cI)CIt{k5>YP7~Cp4YNi~=%I#~$
zbx9N7#?Bjwwywa)qp2QX_#|NZnw|RwjH1C8ttE(u4Qq)cj~D}0wth&BGCW5O@^Ff@
zN^n8|*b6oBLgZ`}cFBE}Aus3tq6ZTizC_;fQWC1zYApc+ko(drq{eF1+}L4b$>YEI
z(t};Ujx7Mg8i6PNCCEuXlNvZwgi-f}Vba_d9jIEd@Bp)7`hYu3-d<VB4<|nzc^%I6
z*g76Q>~4R4PQ>~=VORRra`YLe!>;L-m3%Lk0Mt1x`OrW;N3ap9o%^1Ha)Anw_>}OG
z33FNuj2ft;8_+b`DyKyan*xl>+{Q`c4J_yaxf*YPyGt*A&sO-8huJOrtXS%ZuF2iS
z7+H~D{xY@<e$#i^(e(;Y?uVPbO0Br-iuj?B!=uNl_v_Bcy{G>ubTqplVk@vo$6l9+
z@#wqy*C=jJCeG;J_WITmwTGNnUr5x5ZYJHf$e-3(s^hL7XMuHmrj~U&g0XukhFwbO
z1*2n$?m7ziS__vCi?cxalLlw8&tX$f(bk3FOkvmI%_+gw3$pgF$^jeag+28{Ai8tJ
zxkwipp}ii#Vyuo*0BJq=cnbBl0JE3i$Y+cc8u3y`xmEV=Ua|ncyWw>G&3gjTnH77k
zb#mrg-bk(S#RyN{bnb56yt|$}`lX+X?#lwG)w2<G56_JTI&^hZ+XWT;2b^443jZE;
z&+APoqIVSK2)%CI$%?tK<RcsB#0z7YS44jUyk*=`D?%GjV~bjK5=eK|uyTt!yz>``
zo<Zt?XYKl8*qO7SV;u?GHsuh_CRebFFvn9zzzD7zbA^evac8bLY6nNQoRr<(YsO*k
zJ7VGBsJ)r0Z{>3@o`kywoR(&)J!?sN!**)f=Qdvzo2K-iJC|)1j)b0|*7X0f_wLbg
zT=$vatzwaGF-qK3D6}tIFje=W02Z2%2tbg6aQ&z%RD%Tw644Okv}KJ2K#<HZvL(`w
zD4NZtZuM=lK!OrLL0(F6CIHk_AgvNh4DHo;d`<ugjA>aJleDs<&BPN?p)<<EG07;2
z)+c+s-vw#sadP%GIs4Z(*$?!i>ehY#zTfxze)B!>S?qZLQ?Y<2{&m+IITW1D%vZuj
z>)L=q(F@PDkI4Q;I6W$d8<03DM~y(P!AT=eL-cyr+F&X$R5&faIAu{p4wObEoF}<m
z(PL(=AN~~e;Y>gqt$FxAjzW^1!~3<&dv*s*V%lAJFyGnu`B|L76bIfJSej4@CK6vv
zIe=_%%6E%*GBCVP$VC}SC_P2tufOJ3-61|11Tcya;uw`{t(BOJ#M?usQX13?Z^j<H
zr(;7vLBTODqbrxp9A>%59@3+bKxRBK01T4=(ur89Tpk5j#%80CuLJ<NCJVXklXN!r
zMzVD{l_qI0<4UG^eRa$lcMb2NULBs)cfvyM7h^K?qQt?FX){3XRlNX6nyvy)z4?!Q
zu)qn_v_YHj#jA9M1Cqv`jt(C~i1fg6$YnBxjkswz8wM7c#O^ujFc3<=B14k!Q0?w%
zFlgjsu>saW$0k?|!(OWQW1}6$gh2FGqP*CJ&xX`*c=!<8#sjd_jfd%mLe&L__+U^@
zk-^kH01Y!RiAPWx1xL3}t}p$;n?q1!Z`nju_ENQ<R!(13NUuavQ3Xa%VYwH-u<nUg
z>-?MX3?5rL<;3dxSMdw?Vru3fU9MpK^#%VLPkDHKy<bPKDfEmdL~?DlpE0vWZ_g3A
zivo;>A3ENvK<i)JgUq~Y#ltz2mdMPv6wtj6NGmB3#Z~@MxBkWdUlQaexmdmRy^zWm
zv#$R3F#i6FPS|AsIye9F7w6QG6iTGbH}!zdb?t^utPreg0CisT)knck@ak*d#kX(+
zMsxLMkuTr0A+NuxMI5_?9wfAc;S2!=7e8jaXyryQIBZyH+>@iU)As5h)*2YD2<;6-
z2&wJWKID}GLTY+ur{-tCrXZH!K$IXi;PxP$Cf^X}BgHW_5`5^SuU27KF0`e!XuewI
z=PfSd=J)>n(l`U2TGS7ua~!mwn!2_zl+_ZvNBAKub1TuO7j4j_Mq%nkbQ8>5-en_1
z)gZz*1i-LzPWa0#pPLa(2cQVMGUkD^XgL@z2<b=gaet<hMAQvn1F6bkYH@OD$KMnA
zh|EP&NCjbeqzA~h2jmY#FI6TRaj%Z<2m~yEjSEPEtN<A!v}oDOLF8vas?in=U(cr-
zQ7MsQM9DmIQHF|74Bj6Is}2X&nj6$dk<n~gG}tqS??rEZLXlL*z-fhfnb%AZ!2wbQ
z0thfmHIqn%SBn|Y>~L*ET14iFBQytm<AAJzcB$T9fWr(py($hbq@j)y3Vh4Ob+AMu
zGW0@U;|hc)m+n5|Yg^15=z(5A{Q^BFA86iL8dimgQkb|ZA5Q`3p`lV`$PwCnX3Jnu
zm5vrnpOfY>%)$!Ykg73+4z4&31HeA9v-Ck`TH`EnJ)^J7^I8om!v)Nj-(xy)$(QL*
z+p{Jnc42#_V)5GCmc$0yx1~alnDZzH#07wQnnKKO5hF2p;no&hay_UZHu?_0tL78}
z{ymXbqD!b2!hyUC4NyET-J7*wt9y_YfELOGqp@RH3yiZBDkhOcB1y}780Ynmet6d^
z8Vus^8~q8B5%AMEc+$YJ+RY%<eF~V{CbNuxARB?Wgm&ca{H|$HY4QIsw$>~zz?z$N
zq3MzYxqh893c(R2{i{jz8-!2?;Sx)@;HT_cj)vZ(>?<L_9u@S>rNyvkoO{kjIB;Tq
zkT3L(r{8)SwV<FP;O}Tt3Wuqd=m?_$@}wmJ90aIe%_9GXqTT?phf{1^5UJ9J=5y_a
z$EG!`J6M0zBl<c<oF3c?>|JL#C-+m!&GGhJtKu^Qpq#e!{Ck7DZFIC8CWfocFNh5u
zXdcqrI1c)HSEkxEvcP<eNEvP!bT4Ri0JcJd;}$p?nh3B5&}DTGbht5y2>TWoskL$=
z0eKJ9Yi5wX<cfJiG8N!NL8A4pcN!ePGZP(8939BS;KWhqD4hq$PEeVgVCKQibu>rE
zu)~jL6hy7!hcxab8+Xd^5We9vR15UKlMNU)G5L+BHu**!*qc^&HPojl2vhT8n)7@O
zlafyAT0Jla2Xn&3@!?wt#zO!47XI=LI^;(fF!&%K>!$`GouFw8YFyPIhMm+@6(4qs
zYo6szXV*(_h077XhZHh2&O(6sH_wAN4{vaCdE2~x#q`fGpoZFt_m)svz)h=Luu)<d
z(u`>h)O?RQJ{QrMIdgEe<%5*olFreVeax_Zy;CD?Eg?30B=RLdc2t9cmK=0Q<pxM@
zK^OM~22$*&6RarRqu5>S1(rC)L&peRFUG*S@$2t{yJb8uBlH(kgrmu)&A6M6rz@T<
zrBi`l!W8xvOd!Gzgz8OaI{j+kQ8Ssd1QUapGB@GO4ujqcsR<Cfr-9Wmv^o`NlhH-O
z#rBB=VOXPaO@~wqd^L5wJqLm@vcKx>o-{t)$gi2xCRIX2Rq9wY*X4;1q^d>V68el-
zw2%hXE^;#yaAfJoT&j_J^G^@XVO*g%Qg4O94;DoemTv>#gEBolPgq-GbOwSx;~-Dx
zbgB=f?j|pplqBJ69@OYIgvBLnIjP*rw}Sr58Kk3&J$>O5cSjRu^r}|K<;^`oIW}`5
z?+ILyRntvkK^GiPs<zQhnMicm{y8em<}5`@#6GL6lYpUj1Q=oHY}ala&sa)W%{2(=
z5Sm<cA}{c?xZXo+me;O{R=68}@Y~m;3u%$SZ#_b7FVQ_L&nCeIYPPS<`$3HUWe;kg
zk^^C-I!24%i;2v_%w`&SI!`eftly+iJwh$bj>`=cx-K+FA~a%ys(8Yfmuzs(r&pfX
zg7xI;Pf%Jc4JzUW<Aqol_@=LQpo0bI2bPI(&53_L&<MI7D<E?NrV-4AIFCA&1$0+6
zsLlncvJUMOOCp_EZHR<$q!yy@quY@i5BIapU8?>Poj59B1Sb=^z2fDsOV)vJ>IX)%
zL7GFfr5~TMQRD8!M1+BMFaU2oz(R~sM-!$c8s79XOojx!@3;+WQDmi*&(VZ4<4#VJ
zP<Pxvbx(yNWCNGC|3O~Pxfr!D7HoBuVixX?gz0cgX+G2Opk|jqSOGzJp~mm99BWT%
z!Y_<Ph14;rL9_^*ee?&4b+@KX!z+v#r!cul&Zg<yo@v3l!*My(1J^tj6$AD}H^v}V
z+c{n{e(CdF^U>g4E&Y|j)wxILe9JVJqhs_2R=Y5_WIfGW89Undr7MgU2Ist<dC_vp
zw3^?f0lkab_3q+)p}Eg0e8?_5-LjSa*=4)q#eFSvAG~eV{IFZNT;xZZPJgx~e7rK*
zU)j5hMXy$3xf(#vUYHP)htqW$o{6j*j^i3q46@dgx1R9kypP1&S?!B^+E49&f?t$>
zQky?!?Qk#D`F~1#`gWxI`cCovU+CMr)hjjF&Wp!S#FNiXH`>Nq4~Ol08np{2-ktb{
zz010--qW&nu(B#2*#a!oLTYc;jr<Nr&BGSbj80eRG{=c=`#H0|+TA{3ZaGKQ`dzPB
z&5zOm%0MtZ%+Ht??h`%kH=1r|V`5j+5%&&Ox=cC${NCWWH5T4q;r-^(7G#TPxqg>`
z(@(&;i68*{7tS1FA7+r404d?#URs4FhP;zMc<iy~=X>bEw)55}y@Pz{7K(`IQ$6AS
zXRnO%+H-9?8)4_4!nKCj*!|B=)+cM9I`E?-@7pQ^4@4z+HZjq()11ORVY*bQ(hNGr
zVEWWG^<XYqR<pT^%qeC7S4^Qg7_{JR=%B(P8&tq7AX!!^ZAm9qzo*l}SbMU5)VksW
zi(~=|B6dpu=#H~ku&Vaa^L(9r%z@U@cRYj^i<=-Cy(j=bpIav#i;i_`48f=;7+X~q
zLpQxCyusb^Ol}Zi{!8XJ1Gkc4y?x5lr~8-r&afwb$pX`lwxpk(shY#fO<U<xNI+by
z%r##S=a$WVW+m&an4qZE9|M1FYhU?elL(Ff##;Xg>s?xW;29({-E#ajC^S?1cy4;t
zZY-FvMRAtjrw(KZ1h)@&lj1p#AvcPdduc`+_P{00PV@mx;0J5<D`B{O;$S+1DCg1q
z^XVspVt@MF-2ie*C#?4koS4*idE2AUT<od87Y-?<S?fjj!CL(u-uidn{f#a=dWmXf
z1IP%)-9ZpI&^z-@bIB~ke`bND`;=B}%9&nKvqhoW!+^K6S#N{b*mj#WW8NDvQGO>p
z3MjPl`nIsotwWyr^u1@CReQ}jCo56DdZsKv2dw8*YCg4aESQL+lK7jM-V!TnXS45k
zmvIFHo*NJS4eb+$p!I74jQLw?$<m1)DD^f5MwVLvs*Yw)G*0s8xaGDYi{NtWN&dG7
z&&=A*^;5LpG)A&uB&#DYM15I-mRd7omFb%qBGhpSi{?{UNt-Jm9Uq~$jy6fzcEVbv
zr>pJT&7wILZAbFO)AvSQwEPNB(+X$B%PrRTa^Sg^ttInYCJr57=Z{Hg0id36R&hly
zQ6MEx2n{O=P@Bg>#7FVB+>?|4HN7i4b&s*Y_s&yNYTXB1cFC-NEkyFT#&5dYr*3Fn
z2_Z|%&v9hX`)<>MxhpQ6&n7UPz+t%$@u#v5n+*4w87wleRIh_ha~}I@)L<dhgzK2q
z2Hf@Kdz5B|EV~z2<xg+tJKu&L1%ma@R6y#b<R!a;t$J(#Sza(_P;8=nrC=S`a~7a7
z<bx26ZSZ7<r^41}yXB$fa?$i8kR@-YUTZ}BNRjcKX|Oz5N`s>y-@k32<deTk?*0lp
zpS^5X#!Oj{zhZU+8Jwl_O&G=TH1<y7gX|Gn-Le4S(QFn=W^>R@U#yt6s8>y(O6BX%
zW|co`eh#x1cqO#_5x4XwEcmt7v+q<MUoeM*0-v+dXW(57a$wrR&?FRkP6#)(Q0ra~
zWC1`PPa9#K!i51=W+h9v2ekg@{HxYR>Gc%$Lx8w}76OXf`o!Y7rTNK{9#1}z28Vj_
z_%r>L=q-WLN7%JM0*}-JZ>a}0jKbBc$8O-fh>F6i1!gsC)2p=2+EA}{1FjsKVuf7!
zBuAHdxeb{>G2Zv}<aK;7gPn*~uA<aY1YS%LL0GHEy<iHMN9$vXQ|Ilp|7&4mN{IL#
z2&K!%LrUD%4^%Vmb)GBrPVNk`NqZ#TIa%VO(SF-IqB|VA(t7VB_SoGYM52|--OXCP
z+WY~trjx^F^FAg3#{V*UcZMpS5Y1Y#W>(D72H)HxZoSJAjpomyYnMMc)vEo$UAJuS
z&YxybSGe`D_O?@2^RKlQS1smT2++r^!N33<ZlJR1v_?=5Y62jb^3l`80t&vQz*w7}
z36*3?7PhJxNA)>abdA=ul7ZiEZY}<1qm}E<3A&#yN3AE0zkluS0O}g1J!8^U*c9S?
zW`2{E7|5P}b&FZjjz}_7q1e_F*X^bw{AW$M*7jsie()APV*aXSSj~4ekq^s6z~};>
z#-Kr<D5VHm&H?m8f5QQ!@cbN~nP9O8iw}liZ*fDC27vx7;-7)Rc9bLBHS~o0?$f_K
zB26M9wQraH98*!bKPR>3GmM|b@tdh8QC7`v#wbHH)EuaPpvbLYuXPr{VqRZk%9?Y8
zh9V?E46R{8UWXw7;v4q5TAMCc1PUh?LM)kzDGO!_gbc@p?3C~B_`>)!7QKl88~nhr
zViD3DmN@Zqn+mas);m%M%$QSmbVi-R#03kucE5;RwGbjvAy&KqixY?+6RS|KE6`0q
zDv@sq<Y+1EKK#xCrn$b{osn4jggTa2>W0J|=&WyIrRxzb;MWR7v7iN@dAz>B4Zn!Z
zJ&@rr1Ez~ik`KS4|EtLxEWwrfaNo&ba_NcSy#xI>^lp3hh<w;P8B9ETr2eZOJe_Y=
z->dVzkW&7}Cpyu!6jFDE1IqjXeg$=7sh+QJpqc9DZu@&zkEaqluOFuNFB}Hd^;`X)
z=!AB|dynHcaDJ{o-(0+QkZtL;!rTUd<pbdjHVU;~m~Ci-`@FZ?ua@TKtEG9H|2V-k
z3In`wN2;y~FFx}f2fOlrbOTIcn|W+htgH75CnL-@ZQsP-X2tSNyn}r&I?+G70UlA7
zcbj?uQUyzL9VYzM7TA0LaLa=Z`44{qP5dV|56saYe~5GZi?>Vv<~s?PbLKIW5?vkN
z0dtj`01&yIr$8xSEC?IW%i2t^2^+o<?D~=l^tfT85HJcO;67No6Kr%PPM2VU6WGjy
z%LprXVKrR|acvSasVlV5S@UM3j8bDzXrlRt_qD;e5)|-`EtE~-!dSIzqE3lpL-aG~
zwn%+Sd=3EAby6TK6y!407NR*_Xnn$>OJEr*^G9I3DRYk}IO%+vyc`C)vk@OO_rzB0
z356wL41V<Hp8+tM-{_m*Qv$EUrTRd&2$QxWMuj?UgnJ<d;v!&z`A}8E-(aK(A1)fu
zcp<b3j18x9G!Ji3GO8@8A)&rdh~s4&bR*ILine}<?u}pnDH}%nItdg*5r>i$6)27x
zZO%nq&4BZQz*LPi4fC-A^AWZ)>9Tkjgk*e`!N_!BU;*H$X*lr+cfBr-vw|9nYi=_{
z5^W|4)4jJWEwGgI0eggR-s5LiCKgBByiqd&J^?VgPIU``-e$qf!Ubchf)%<p(4yIq
z%xjRipz%QNApSrRF@yO!js~mVhqZ^d90o8T;m|@36WuqGjnF)FMmwoH3xnD4vrS}p
zA|>A*%{6a|WTy!<BxngT4Q7IZXDl(oU_g%m6Ws{Qt|{y`NfettHt%!fIAF(k#ux~u
zgck;A&wQ?~(;hMt#AhH!k5<TAmhNFo4XPqa-~yfX4avw$RQF!BP5{F^W;?wem!(K&
zx4Sb|?vMXYcda?!sz`gnB~Xnwbtr6@B7dlxnN8f%w)K!UGd{}L$%6$h@`GnWF>Mgr
zzc;pKY1h7vAha})_;oiA;~t0t4=|}>`Hl>qPYTftocx0n>8iEjWX+3s8!s5OxgnlU
z*LK2mjo0`+N3GD?&idN3o>GSvl#pBiO1BSQ`RrHFmo(Qr2!fjKstykrkC-DuKuS9R
zol&d5Ep^jJ)IKEdHIPUN{g_U=*O3f-Sq9cO0|R;nK2{gBl*2SEEsiCz5_OFha(xKa
zO|@FI)K)URQ7>=N$v_e89{%k+)HE`OJ21?4odT+++@>B#*gb(H3{D8)x<FS6WCx&T
ziEASg5Gj_#NX<jO0Wu!4q2YT@YYMg-4=}8~=UdZ#*7cpK-l6mHcGMG@<s{lO3yP!h
z>0iM&Fn<{sDuOYP;%Oee5r6|86WwPPIz~J~eG5ohjsOe{4Id5Xt`u;_1VFpw=;J7c
znVa{a_yMG8TiS0V!oXpn)thJ-^mu^d;#Byne*`9W4zL)&0vBjVKG$VorXn^(x$*!R
zG>lK_kGU9mHKT@YGDw2A#eIDd&Jc~HzJb(SnFd&5dP2|{Y;`c;fLR9aqSZ&OX)AXY
zwUgP8#=5UxqP+1aywas}-hut2)|5+=#>6btRRjqxee@zZP!Hk<g+w%;f;9Y$X>A}5
zn_JB5fZn1mf$p*y`?@;nv`L41JBZA#US|UUFJln=G-J)zC#2deFicRGhol@wDH(Jy
z;Ay7)01vH@IT~hz0PK0dPuK-FtoTmbwZ+3*f0{5gMVkPlu%*ez@sMXCWC1b|Hnz1V
z2{9$e$2h2M=RY2=43j*_>4G>L3z$J;iMmDDKKvB|GXM^)rZ<0$C%R)`LyHYcZOQeL
z^p*&YpPtE^JXRBKu#7CIx)uE3iT9h-%wK1Ux!EmPE4G*v-N?t;1jBjNGzg?NuVD)x
zfyo+;xiQ=e)b0pAG@O@mHNr+NZ$Z#Nkx?Z=E$q0L&P)hs(O~bKaP2enV|`pa5~s|p
zrZWtp<xDb-2R*GWs^vD_YJVHr#FK5sQ{4Mx8*ph;1_mwyogVdtB4FwxE`U4JohR`i
z_HoHrFcQ>sw7zEy4909@0qZH$f!CW2I{wF0uS(3&)qu?sh+9|#F|KF9E`*!~qn^dB
zv!P%{Yozk3K{qB!^e4KF023#PFpwS1Maw~y7A@$TLXAR{!o*Z4F(m+BPXNDbG>)<6
z5Z?{r9QJAjFECJEwaj3dT3_}Zxe;z61Xz$TCK8GY@t&BWOOV~CG(QSAMy?I2cB*w1
z@e8$Pq5G(&BXC&ct?Sn&uy*-T&KwUstR3j?0fF*>eSKMvut!uw6f2L5XGsBeAkp<v
zNHp|KwgbXVT!W$dXY`xE3m-|Xt)5!mBtjK_cxStl3lunq;fq9qSd+{-+s`%AD#N_y
z(>Tca%KIi*5Togb4Trhifja;iD8cHvhH^?(Gw5iTdLnea)}!H`IQFaDsu`CoPhBkP
zf%BD+PwSEo9}QVluG&B7GzJ-9t!X$6a<AeQt(kpWD717sG$#P&srFQu9x%_r03-Q%
zw=L908e+uC+r75v7i=}UJ;+C31-tknx+s>r9FE1o<sc3$9laH^R{l)rp!?@qv0ZSP
zIa$MAm@in){wwc0aCh$;;tun-%=vQM-C|E`i{glB9yGrMEBA;6gK3V*m-A-Tstc|o
zs`hs#Q&Y4Zi=T?dhQwOs_?mlg;P~e{tq(plzxEex?JwW6-`iJdxi<_@u4tER>$P7;
z*Nr~4*hQ^zk$==G1#!Gb9ApPsA;Uf%#Csl%gLrg7^n7jy>)G>sFN6&K!k)ft4UK-;
zUA<@jZ?<hMAwp)6m9N<0&EZxK$pCKMbA^Z2%*Dm$!ru&@y)a-FK6%d%PC<*CZd=_F
zAba}OwerM;!a2d_=r(vVCj~?)SLl=H(h8k3o2&Fz`f*{iynZ~`V;$l1`A6fU!}X{I
zqCoeG3G|x!nEXoQ0u-db8LWQHe$;ZGf}+GgFSS;KGO}P}J7>K*0skQK@do(27VM;$
z-)g8f<eBZ~=i{T^M~1fYTH)=qw;Fcr3%%~4`rF88u|xFk>EXrmp*(7N+pY0!#VdRi
zRNoiVTPKTu8uYsTJ)Pg!@m5fESLio_z=vf7!{<8ODJ&_4`_)ZNUcF;KBSivZE0j;!
zQGl;<3DnT9RuwN(+<?{pOT)=Ta7U;@Ct*v~$J(!2QHV{yb}(gaDHKs*lva8b2~>fF
zcZ5Uu#!Xir0Uv@~jAQ=R0B9Jy1du~~{n!v5txpfZ2E)<k*+-9U+8tEhz4d}Xw13-Y
zo4`zJDSx3!+1cCp4ij<uwE2W}flbJltgldwb;(=*^JuPK{heEpHs_uuF~YYq#Bf)5
zhg}`s(S9;~Bhx=MwY|Omm|`GyjAh?gyI<~~dGz)lhIM2v`_x5vj`l@|Ko2|}D<pAi
z&>B>ycZCIL*_Q8(TF-g=5Z~T$+!PPEFH593whpe=U*w0IMt;vbLLUlFT8PR$Li^`O
z51VtPwcrU6zA&);t|t~5Sfcx0icWGl;a!@%SnNNaH69dh2p;3eWb5zz51a3>?=C=w
zajPazf9&Uh;kfY7J~e6q_sPhS;_-XTk>$EJ;?*lAcbP34j$YrKuf8}0CYKiujb`OP
ziuC&af&Ji_*7pbR*u1h#tcUi6HeWP>Q&wdgu(4cGXf9}fQ66%buPb1Sz6x}fk4`Oc
zemfKbhQ8>X1`BQ`SdND7&g#qIW1pwF1SB#bT(_IyK!bIHv$?kyVz!{%^y{T7lRcMg
z6djzv-4k$Dj{f{hG}x>_%crboff@q0+-kKAY4xF;f6rVJT9z5>i1@DSBiU&<G!Mvu
zYBs3X|M0KgXm+7pbSEqBv;X7pg85LT9rC~cj3U4K`U9H~N)3#~2eGTNmf(s2S1g#{
z5Kxe>M2y$Y&&)-oUa$Ni73!WekZr?zZn6%?B~`3aA&i~i!0mmm=Mjh|(5;qp<xeVS
zqkZz{o2DykZFe>K)v1q~ICR!_6o6ShXgY<>{fu@i@S_*lNY>T__9v^;D&NlQxi-tH
zo_XM_A;R(BXg`SzQB#noAO4kcal=iw@38gXr{61Zt!yiy2J9V!4jgy5ED>j}`cDRg
z2jq^1S<eA2vg@5thPBFaG%Jijz?0YaOvR|Qp~jdc<9mKd)%}E9daj!e*}S&SmaUzO
z07PtPYdZh1c8A@|DDnty1ZB94sYNotlmWvg&7x0L&3yGqBHLn(G@H3L?4K;NDz_`Z
z?emRLl>eT&c_@-beFw$y<?!rq<&^WXts&9iOaS&5cG#z{2V_+?ple#sK?~18q%`m^
zpwDVlk7h^g?a`hmQtO>5*#>^raj*sN`Cq_x<t3F7?}g}Wb}l<P`5ZWsP%+l6cxZoL
zO!eQWZ!X)K+{H}4dhzocWnK5HaOGhZ3Pyn)BCcz>zC}Y1_w_Adb=fBMrHH({3xpBR
ze=KZ<oC|B3XLQ$v*Nqjcjl0-Jm1BjJqqGXGm8T&wSGfoTH%AAxg{C_Sti;dDMM!Fl
zu0f0%*qCbPk}FLQv^B)9KbYV{gr!5V7rPNW>!r8t_upYR-)+*)%I9y@PJi;3ZWWc~
zwxdn7`4c^@sAlKfa^)~O$LJCpS#G<>^4vD7sk#ghal`{iUaz`sCqldW{SWtVpAya0
zihnfx=ope|oj)-jB8lSzMSfwTJ7m@{pyo2z3S}4F9DM@SJr*T+>0)GB-w41WJ{JLW
zeRFL!+EW{ihUG<I1(+P5x7!BT(OYV*bw_*M&(b$Dqo**MaR~cuYPjrozXC9EW0!ra
zc7zs2KS10zEV|82H4Ttg<M>^sfBqDP<5810SU$GCW2V7qlkI=Z@<zHJw%tv4pR)}2
z%e|iqw8lrrT14=LJ9G5nr&QvB6<GF#973Q_&Cn+4Fl5>0+Hmd>IKb$xRZ^-v1RwnA
z`3O2D!Kt95ReLGiPw6XM2G2wg$90FlKG_~xIV!tCy2>8u(`4C@Fek8?5Ng}kVE}?y
zhZnIVVRzb*YKbv!-{1;tM{v4`ycKx{Ol!5-q;6i1#`^ro4(S^q^kYL~MUsO7im(=7
zSGNhG4tW|cx>7DM{5tQtTE-KNz*-mDrS6Z6pTXYj8YVc)@(5eau%c;*j0fUV*SNw<
z30O;5GRp#@r_m%9!znV|TgJk5q^|sEs|lEj>w>E5;G%M**$5C)!e<?F-3#|7x+3;Z
zh1^?dH-(!F{Krms(9ZVAR_!LFIm<zz)w&7cKh{mZ7nZc=T^z$jL~?ZbjW@=F?*o+E
zjm7Yd+ujY__DAu2GWdT5=>4mpg8$zgq;wc?=VO0=+B>X}#dp>7KP04mJbWU$%1K;q
zxIgIFbhM@0ya|=q)NJd8rhOKSZ~Q-H{w$-d*wNw>YlQ#!pV_vdO=rH|w*C(<7;)D>
z>skK<pJC(sPi|@_eC-A{%GLj1@o<;|`}xr2M{oG?r)o?6fA=N`I^xxv12cRU*1*-<
zBj1gVieW7hmF6fKEcBWn2LLREEkUgolU^rm(qd})a7(VN%K>DF>WkZoq9=%@-JC;I
z*=Tca?j;(@DAnR^b<sz}itStTGy)9@h}-A5Jr(qux)?U2d3U&VA_#gMqb<syyKK2&
zyv4|pai-K2)p}#$P9v$70Zxc!{_c4ld9lQZJpyl9ph4<FGXt16z(Vty1E@~sfrADH
z$#V-E0nILh36|f|hms(YuaE;J6ObkVH3fdbu28m^f+Jwx#7TwmwU8GFkfFnka{XzP
zg#`l$+DJ^vef^Oh`9{SzU<RwE0Q5zzf(B}x%;QXE2+<8$Lu~&*HHG5^{2`!&XM%7&
zke;0NrrbG|PzveYRxlxeU`a2A=9(QaQ=$%f-Qf+dH_0Z?t-z2($pZ2%;H|YuKJJQ8
z%*O7tZHIj!A>aCqJSq!zyut8Ai@<$i&Y19TSa~o-2=@N08wgFOt0C`EVGAH(TP9lE
zM!A7`(^0f3IQfGm81t4N-4px9u=bGXw#Eabn8E+9C^7nF#TAgTMCXt~@|iT~E6#A)
z0B>UnvC*Aj%uoE;`>a_D##~V!4AQwVZo;er<r@U20@cX~L=0wOV6RvsaRHcENUSXp
z+%{=M?OY7J$7xS>Y7HE-+(9dcTr`R9jxU1oX@Ei>>7-{k*b`XElL+%8kp(kxyyiJv
z$0<^j$wMG0U+}z3e_A8aux9#eJ!fN(aX>s&r6^9Ca!7->mE@Z=x6AY^JTcEhVBNL3
zYtSPDWQ4|b<m6$7n;4VrnQpxWQG&@4E~Zad2H|YAQO-q(jd*Cz&U0<B$6hVW+vELW
z&~WA=#Kra`hNG__FcCmr#XGPk4Py%gbw{5*!!P|Od&Q(8-)rWdV&xM-pfkrj)nt{r
zP1<EOjqa4DueTtCvtRdzwg6}JBXC#3&8`57FUX<^NU?)$biQDvW@xmH!tB>qtbEjG
zBUZVuwY$)%Gh`9Nd{WkXwz@sV9-H>}L^B2-h8^#%Qm=3S!C+eRO4<yNS%^pwvN#S(
z=9M#FcQjxKQLD~Ghk6CZ4)ZOwh>bJgc!ZHWIJpAquPkaY>{gQrd`EwYOH`#!Kt{}4
z$U-V3WVM0=BokUW)rT>GjHeh$B3!T%cS0l_4n-UjckWzy?qVJT-U!-)V5-^IyMS^7
zzje%WM|Gg=dO>3*@vj?Mgd<`WR=ysn5s4va4I#{vG2c*w4YVbkpr57PU{ZU4Cb^>_
zp1|`QJy3%e!N@+^gCvt7h?_q2&9Cfv9Ow*~i}*DXyn$Vt3JoQy;Yk)u;Dn3nM0sm7
zj^764i+m`sfqb4q8RB*wMM1AyBZL7-MVDd#Id+JY3v(?B6TJr*oU_CLeqbNw3U!iJ
zgoqpWy|Y{M4fQKvwifrTV9w0zE$~sUz-xkra1&|xlTi$ZM+BwQTv$FA3ydxj&;)(0
z5tNs~pccD?H>i1SXS@i38?|l=G#)C>#=&NiPbZeFfirG6jx<hmsNb8CK#bx;dS7A;
zEmgyzlxxX@l7~PsfANmI3#uuFu`T9hYhY<}j+whPs~iRThyRlJR*p%$VxUKa&KM&T
z<_aC5qlxBNh6B<i*yq3*q4#c6`p`Z%H<5>aq!=0MD$v37Nf&J0Kq7PCL<Df{PJ|m{
z{QzJ_phhq{<F57%X(6>QJ@7X`)goUr@ueix%sN6To`yG`b?9J#D%TIle|cb!4rDq6
zY6u6}0)iOgmc4;!%?g1-aW?`M1*`=#XO8r%8c#$86Eo0G{E;9h6W;QOOmvArV%vNB
z`)F*#1nT93lZGQ8IU#~dfH1`IAe?)eIUCdiR1Xq&u7S=yGbT=lxtoRu1tvslmiy?z
zsB9Vh)r;Xo5al-ow5A2%kmv^)*;YeSqSPtV7zZysjv}W~caZ*)YtYu<F~Cro9(F+`
zND05x|LfR8+RZf3eS>zH5`5=0(2}b}N!!=Z%X0}XI*inn%8yxbE@Yz&lWCy(%=%p|
zIGq@dKEJ@3;Fca>U{m0eduoDd1WF~K@IEWzr9@XXFv6>so~qcEy$&*OIfbBnIP6VA
zyKpYdQyd2!Nr@R^YQ><79-%=jdYh!PQP3`1#E=ru<TiAYS~sHedcdFbATo``hBz!R
zCJ=+e6>_LV((wcqAkA8G7G5rdiK|}<AHbRn7hZtHT7mqDc^ycq1oJLVk5#$mjx8yG
zTsZbv748d}w+%R;A`ViwRtAA)#r2J~S=t|hYo2aU++BergKiR>_xMC`*dD~DBLhPx
zpPf90SgRzx&N0yC6SfFHzeO(XyVuFdr-MhmfbL=FG&R(TUB|q`!z$za$)0X_n)aB)
zbtNX7(AS0y;ctvy1!0tu0b`312tc@K6wq*N1KlU@g=itQTcZ9vMyTT&A!azt1u?3#
zXp|UBnXy-kvGRm7;#R9|-xoIf=$W{wuI-^hx;Q*E{sw{iG8J+<4}pYS9ucjZ0yO*w
z>606Ubj;KsK|R8tz={H=%=&@|M@3%mfYbD-XAMt=Z=DLfQ|Qinrg@K(GQEW9+0(r=
z$vK;c(kn0Tw)?$_H=2Tu;JO06Clxc=T)R0~^~Bs$=c%>VYD=v%-VyUlqaAY2!W{5F
zx<|sf=WSZ`J{YZiGy0==tUB<<1-lROl6O?6PussfHgwsF51RAevTwEz2E%PH_r4KN
zLaw^^4sRy>J=%XR{!Rl>+3O#grLUfk?-zwHdei&tGa!+y(emU4r1<KX4B1xqCi<y#
z_=}yx7o!v2$>IA44!d9II}_JlM=o%Fpp>S^-My@R+gJMlF4RvTp6b2*#fCd1PO*>H
zHg5@nEy0(V968$dzph5P>7Fek;*tq&XN!4V?XqWXTat4l)PBl(+BEIndjFHbzaQ)P
zfE=KY#<#@b!RTxp6}}V=nw5C^<ZuOj=rHad5H|$<tE1m)D<Z;wtp5)@cG<ID4Tg}*
zSH<CPb*<VeZS;wkz>k@yqOcB$9;4Q?`+DYk+S~t{7p9-=+?~FR+6Zg64L{h@x93iJ
zCp}DW&JNGVdqt4F(kEZ>>ZOD2J6`Tvwo4Bj*!!}#c>L&RtivJy=#KYgc2h)S7{=m(
z?m*6wnNixj)B{$fS-K!9eOu69>6Rr+0_@XzO(|~b$M?^KAxyyN>O<kN*tU^zI_ihX
zb|h$$>q@HYifh-vQAMm=XIIu$F#IAO6(dODuT?Lig?rn9fCdi$BUMtZLws~S9v*Tf
zLtw)qwB1U8hN>{Nqw&xS>#usO$JO7(H~BofZ%H4nAcf8xZT_2XRzFj0z8qAjbIP2q
zWOm2I;s>O?eLrY?i@a;5`7%4c^DYlezQd*hMjJQU?=}T;W-)?K>cO||dG8M%+m$xV
z=6iz}QR%zq%k&%1ADq9lUOYFo@6Hzi#qFM$SlesA*Rr+Ey(>FX40hHk-`~Ys&Sj&^
z4=h3M@}OL}zkbha$>kYKWFyPS4)m%eTbKCn+q)yTeiZS(?o_RL`SGol>F;FAGedvE
zF2~smU$Z`kUb6gG#X0-V_%qm2t)7VwHx)Y?lUwN%*_p8Qum9a-mtDS$efRIT1UFiv
z+3B(J&{I@$I(=7WQt;!N8LP~Fz{*o|@s^P-&5Pzp_pOL*zR@0Q5=ZDzWLDP(PKIOI
z-Ms<ZYBi0Ofw0|uPk#|O(AR#>4aP2ZG|a($17GA%q_v8x1TX9Nws%}c*!8_(Yb6sm
zyRD-hL5iDdCo7sXG=M9XTD6Y1Yolv-L>7ktq=9(ntT-W_$d+F(9yhTiJM`j!67oD8
z?QOquEIS;Ro@;&PLbe<ozU9z6u6?ERm%8k`1Gdi|v)8Yw<#HuBD1_5ZWiLG_o(dK%
zMB$cn`P9oSwQ>vV*F@h7f)ChYA!@O!f7zxk$sX%CiTKTp#eKuS6xQeH@qgQoWB&KC
zwbV0Mc~EIXZneutc}WMZ`4O+&(qoCTv7JL5v@Es813)3Ghe&yBfcF4+;@)WlC5PVW
zKZ+1;9e9n(G)g?6u-uds7tic%M^vo`<<;z!%x&CqNI)@kG3&Ii{CD48u@5v)2<QXy
zdR#5v*gS<xVFAXCY-Sis$C^Rk>SiVVD<3zDT5}WN-{pviAzLed?7<<3u-><S!5p*S
zVwHkTJI@_^!*uu2PaZ%XE6bS_yC&LPH2c;@Yq2urCY6VFaNw)=M#W(CkOESNa!3>u
zd40Qra)XaVyCQ-saCwNh(^oPTolNPG?1g0rIP615v#gm04C)sj+?hUqX6Rz=N_K3>
z`0jJ#fqkRxnpJZo8@amx(M{wxq7`$eZrZ9Hn}3<%TFx*};t~+0AnG349PFHOyxtBk
zg>V_jyA9ygy%R-oZgC9iq4utetaQb;r&{MJEd!ogn*!8Xwoig)_>y}9^GmkS3K*{d
znrlq)kmHHQi&t7OVhm40Ex@AaPYlAeLy9{o6b%((s5P)1q0p)N)UiXI7i*I&yfppg
zS^H8D$lq@v0E6>rDaGjhI4fDzEZN{-^QHKCIn=&3k~QxO)D_}{W!)cp0OGnESLo}#
zWi=#B^AQ_KQZ|&0!>zPz-0THq`LcJ{>r=&-sWyd3Ism+PWr3o5E;|}qXtI*<y%xxy
zf-!nW#3^{ll_MCsUgKw<5DYyRS)hQahkM)q`dBvPHhK;TX=lRt#hquPp!_o3XWtt%
z&p{WWjPXN?`)Ev=)*PVQ1dlQ?nmK8hbF>jtH1ZY#U#e5vrnX12`Sa25gbnlD-5ZOQ
z?g!es>8%#8tPLCuXYFln>sP(|0~b?IxjMQ17T~_%EJI7-X6STaPge&qdE^jNH7zve
z?Or_>NjH2mY6M&90svz4`NxaTBG1@zhU!*NXMt)*#mmRCJI|Ds_%qMHJ_O-_`eyc{
z-`cQiH8AP!04(Y#xd0?!%d<_;1)BwoXEV?#v4#|LMfiHF9*|c!StVRFzY~Vl=YRHd
ztWf><O^`D#emMMa;9m(2GXKB8ogjm~ZU>g3QQiUiYiKRCPW6IqJc{gh1R>*vdrGVr
z{NbJ)C`No-bn*H-!5qMC4L<vU#apdI%V&z(p<^M6ekjxH2z7QZXU7i53;f?@&RFK_
z_kD8n)|SY&`YSe!SJOqI`>5@#A}_iNLaznv6T};!^Q=wFD?dnH_kq~B5=cVmm$j98
zlL0#c>S|ztm<I91BvPB0V3<mn1uzI1L<E=<NH>Ld33NEly!Hs}PYxRIxOf7=Gmyk5
zg5L(emG|QN55$_RX~0pc))s}G_DRvK10=wP&EqR|wE!;?32H*t3*4kBQlg~Z2(7>)
z`OAhp0>MNqy-LBf1z5?KBL7i1C1)z@D{O4{A%@00HVG`26mVVRf`NsUPC`xqYv^pG
zoRTdKR|-d;oh&gSmn<LqA8>~N@5Z4M=)3>t_x}s@&KskDg1~mHGc*6Ur+&=L#E<_)
zO67kec>2TN1{AD9)qnULUVz-$czEYJ7TkE)dpEElSTy?H!O73qyRH&52lm--KKAv~
zZ--Y)bNf0?6c{pIfG3I<>QL)E(Ov(X;&~f*rU#XSRxv!GE~}0Mug^~c!%G)YQ(GH9
zK;*~O@_=_;dE3ch!#(0gH-#gxEFEM|15g66g8=TpgEDrot&d?^!feB?8$`&IFS+e0
zPxo^?^nfBZ=5jBZK#mRU{sAo5hHoS=#ncgwX6dnX{Z5>$FPqu9oTba0c%S)%I`*}j
zzkVim^)F97C7P|y#T;zw)eT11y1klcIA~%d*WSk2)Tg*9vv2pC(JDwf*&=I?jQj=&
z213_t%LD`MXfZ5I0JQ|4)CO+s5->9SP=9EQxm$usSXyV(i)<}Ci;O0{WjB0rW3ka2
zk9gCjUWYVgWFZUTh#UkwGvd-Bz&4DTIjFR2RzN}sEJTN-M!UQW7BA>aU@I+Ek@WrO
zXu}g*|EoQ23WqmE8q~1mis>+o<tyovi{bcDV%miE!qx>TC$G2V?idVNlOaa)dg#KT
zQi0n(XGwvyC~w9=AvRX5npU6hWn@o&jDs$xll}`_t7#-ajVUEa(0m}Yi03^E6Dxo;
zoGagb*;fPlRzxx;jDb1{P>qn4EeaI?(t@+<q(OX;C}3i9%{-e<v3Mn(g;?9bT9`EY
zhm9j}ma4D0@@lnPMcqX^s4!f_8407Gop4#E(OEC0ir?d3@A6}cJbsMJk8b(tL31%!
zYuW@B?4S`MgGk-X6)~+$2nT64&N2fwwTTabq<6(u=);&hq=h6LH<c=yM}`*N6;}YX
zFpIR)u=t=JP}(Jx1I`;x0}1j-$<_KKCkO^d2wbwvGMS~>p)`Yxz+0*JLKxnWd0y?9
zcj<#S%*H4&3x-@4y#t@VDDz$q;Rzyi=7&nAbu{#Iaq90;LAlee28s?aV;}-*=0hvw
z7@D5E6d_X!Z<pHb3>81rH1AUCS!ut}ol_nlVz&_{s5E;pt!+-+MXQGJ6APG3s#H$}
zgIn8Lke7Buvr&tXa|je^tvFL_(`DUkeM9za5i1sC4(_DSUu2tRL!Zut#I#zp=3I3)
z2Cotpw)8`p8}OjxYet=d!QQ7OgCB{exm;p5xe$(I=|ngj_Vik}83kiOrT97+9uli|
zG{lxz+&68lx(mo=_L^9vkJGe0^QNaWk7XNr-l}>3Azrc%7^S)FaC+%y?@2aTv|V5I
zT;u`rt7+mg4ZiB5A4j+nob7e(A;a0!QAwqg<gHY5HntiPtgaS0SM1>Dxz;*wjdr9P
zm~>;;zrLfJi^(7wkfsZd19*wha0B`%d7G9jB64`r5hv`NOS2)d%%ZK5yr7W<RuXJ!
zKBaL_Z8Kj8zkOu`)CVUZ3uxtDG{&JUFr)d`p^bo*fyV_jM@b-Jz8C_^gJ|U(X$y6<
z4_=cs1WD?9;H>C3(D?vHqEW%ya;9~_=7IqDP1Ze)*%B#ot!UJcJ)T^8ZU(?FhG?6P
znFOroWD+_PpoD6!uK{XTLjm0a0~p7&K_YMhXs}Apbu>m|7pIZL!R1<%qYxJNKt%Lf
zg&rhg3HzBLPlCU;kaB{Lz06^9GK)Cb@y*>#$AK}MsJRbu<_Sgx_JYir;`z;@uH(G1
zMdol!(t3&$bvBfa;iBjYVtUn_KroI;5-OlaUH&YNM4?XVqQqcsa*`@6#90dOYr1Ym
zOEv*%a<#V9Osz@5a6NF1EGn=uS)XKmyaENzi{J*9LaE>!E|Ah9q9rG!1fgzxsg%pQ
z;)McM2t?wl@LnSO1%SF_Gft1Pk&F&$4x)c7KyU_X_WSpPJP4Xpz6bpLB-KD}PFB}F
zOzO0*!kGaZsp|*kiZCK90hFwSa4BoI<#3fzg0%o|hXBI%Kx@DO_@$3S7c&i$%^~53
zbO=Gf821jPI&qLi)%x;}eyS_LgbDOCSTE8-!0_`Q-!MM`I1AK3SKR|s3ed{8pbW{&
z-YL(&9^HKUfOa5FC1CUhW+38r^+sSML)+GYSVxGApjMXXVNxq;eU3hmTae_^zde$G
z4X+dAwsEA6RfzbwR>CaDh#|*mpp~$<N}>$jJTk7hgO6Al#uB2T(Yjbue1r4^a51#c
z0VJnwGB5&kNrwq74if2M9>tZTk#He?Zb-BECH5a3q^d$C;v!Ig39vWZ&}DF2hcML(
z>1c|O3DFG4<N^&6;@hgV9UZc*zGTzJ09FX~ruzBY3+u_SBuR8Xw*Ud7-G9GfetpI#
zL)t*DN?!~z8@?M*C$II|t0(rk##X?z1>Y2yDxMH02nff>d(C~)I<(p|BW;fHFs`Il
zi4z(FvMuL@3Coep$?-G+P?u&!Jwsb0IpCf2txurU`?Y{YzR_Wn3`Qh)SGaZz_gGyS
z_AHnwV@$TVdR%3KBp#WTaFAME-^dpXF_AZhSEGJ`{;vT~4LlNgWTDpwhc-)ip9duh
z$L)@fA=UyrpM@48#7jqV2_^z)klL_q*3W}ep?+260MSJQU^}l)M?#knj&~Eh#@Yhs
z3?i@Lb@AMS0kUhNJMw^Potk#kQzKJVR1JUomtT7rLuob={c09dH%Oy{a=YF#vD1sC
zIWhbkc4D&TM(9(G8La~<2@+?5WHgw_Ni8+|=EtWYnqlft1Tiqj@L{;69Mq@7vz)UL
zC!En^lsC*m0vMQ(KmPPj#ZPKGr_vXpb$qN4NxQ@H`u7OJpnc+ir-9WU5-tc#HwNOq
zA)LM=Iu^@eyDyfr@$@`BoA!cVDW(;z@o3DG{ytCsPp+)nukdcKHX)uplO6cWgMG9(
z+0jGy4|coOFR(3XFmM0DlTlxfh@M$Wz5Tr8{#AHgGUGNF-~0RlUdr@C^0=EUogb>z
zH_eDPd0f&J^H;yG+aE(nWn4}pIVKC6lBJ;IWjdD5*!s*|NLvwYXUy2AVr-qDo14J|
z8px*H8P}C|I$!uEE{DD&&7nP_c0m}=cGH=84`G!Zg;$EvD|F3!{-`HDcC@e1m&t9}
z%!#6V0>+FL2KQ@Do2Y;a<n}+wCtJ1c9iBDBmwIpC1F7{xvLUDWi9Oj@z3FtZ@!Dcg
zJKiyU!gJ+wZG0wcKya@q(|**y$!cjtKo5VR;rhT1CxnRaG`D)NTaagP)QU~g=^9q2
zArjX}(8AfZJ2Eu{eX$xr*JzqB=$W=x(KKTv<GIlL5wG4Wkw_vwHnn%#L^QZGYDKq~
zO5JeVmhKPwmDX0U+jSdOw&3zha7iZ1aX6bD;seL<z(wba)&aWQ;8|SaDU{WayD-=E
zH?Q@QJ7XlJxk3@ke{$4*GrBx5z_wCT(K5#}d1tsiIw(Lf9~x`wn%N%Rxi*sB8Dc;J
zAQIc$?SVW(5qLY6nLGF!*1RWnO+mzR^K3X191E>)Pgj<1T3exQUz_|Y)f(XGy(9L8
zJy!iq3G(N&{O-@SkK&IwKC%C8roCi=aJ6IT1@oB-Z)@CAynNsQI}8G3`NasP|3be<
zp~AOl-jMzI8M6-%z*6aZj5T<NappBh!w)wYf~~#7tuVGB0(dBQX{IF!79+m3h${=D
z>R;}T<je3mskm%+dxQ%BoV2z0<;Ixl|1d@{IeDT1kLQrlh%M2H#cIg4Au-u#ek9I;
z;C39*p^ZD^kUqg)j^$Eor_$9t3{9j4FO5F5unR(<4>{+ueey)u_$+ij`S#BiMj!m`
zM)3jz(ebnP-%7c_J1fs^k9KZYD3jZVi~6DEY}CSqlpfoJP~d0HLod!)WJo^yboi3@
z?9;Ek$h~K-yY%oRN#xsNG1@zzF2UGJ-65ot3UHceBy%n-ULG21)*9f<;R2*V79zjY
zh-7^UpSnX5SGj+nQ33OA#oEzu5#efq`6thL7o=S3K|Oef`9Ze8>(z_SEnXRvjIZ*g
zehbN&xck7{@e6z_^0i#H3%ld&z^J<;!l||7fFAcOWML5~MwUHh99mx9x#7@@XBNzb
zsnX)pacQaNndi@xHWjr?|KS#5hX>Qch<krfl;1_)I&6aei=g;-&?wj>s*aU^4<Yk#
zxdDD8s$bm{GH`?$+2QtvBU$IkQ4<+`3h&7I5X9T14#PT*_;bzOJ|GHJ&cIu3I}tv|
zPT$KB&_8qY<aW5M5F=kc`P?!;%k3q0>A->Q?OtIFSBv)-+C9=&T+HIC!jX6hUF#44
zu@^I?t?2d~%6U7Nve%%Lso8J+@9&34@APO$Mh1rLYQ`223Sp^(WA9?=zJ)zuo~AY^
zlp`5Bkbv75k;fOLQ52OFoJR8n?E3b;k?o_egh1`q7&6}9HT-Ew#c42|;iN1pl3{<U
zvE+nZ8Q22=af+3e=91^QBR4FpVJSUycP3we5Wyj@0kE_Jp;0|9=_DS>7NXz%^Y>eh
z47P3>SuV?<x}0b(Bj6JQgC%Y~N9slF8~n`xy1?KBDLKAp01M_5i!Tou{tJ<FZW-iN
zuXH~{FDSig#i+^hrqX4PmT!|z<u4x|Sn4Oc!zJ|EfngA5A!b$nSTqEY%LfdaCYxrl
zJAQ3BATKNh3Ta0d=mgXXB~f5_QitGXgbopX@<}3M=n=$U<yLhW3|$N=)E&r~0GxrH
zTF0qgA60~26d282--~7v^-<17mUp=Gp>#37pzaA6%a~G*U^Js2c$bI5?Ng=jit0HS
zg+SssBq~1%Ku(lD`5;pd2=IOvg0`ou2kiC$$Fp`%R3<yxgDc?xE9pt2XC=a*a~dX1
zUg$1@x7l4>oLN9Ype2hd07W}QUMzJ*?{<90r=F~wDWBj_RV;3jb?{65q7DIxPNQ*r
zv;T*$p|-&eFh;TtAYC4s;fG-`6jr?s*QUq9w-zfr#0ZQ!U5s4A|5|9!gN!9X5hUgZ
zgkDCX&-@z$2BwU_KOg4kR2wj_i3`7oz$Fb*am5WQL9takwA7S876MDW-dd3%#ZbH;
zgrTbW+fzR?Ght(Mf;<jYG9aF9k}zc&c2OfMYD=c}=ScwPzX;>lARVp|#^lbm7~IqY
zr)XHhkmjYpm@HXu*xCKH6p{mEdsx!2j$DZP<j&MI9<d{XXNlA@@)pf>Ckwq-xPeX3
zFk~LE9r7gk{;1j*!Q>{sCJFQ@vBMe0Zc6Ps0Vse))`EQzU_(Q~`GCdj`t{{b#w);9
zRuC|b1+xrJr{M%JBl3zk8YMhL*}>k4`^e(~#MZcxb-4POkVAZv>u?;$VUn}Ieg109
z_Z1h>kDu<pG1}k$*g7xsvps+Ke-<OXgI|T>w*Rw;?W;^i75M%C6o~srVc-8P2dMzf
zTaO+8zc|R=tB~OGHAwJ;r>^I|8T@)i1$(c@j)w@{xO_F{d-r44dCq0Gdf4p@#+F1I
zA6tSZ3~=VpS!pE|{-iw4$9m*(y<-Y(gzacUwCQb|aliJD5%(<Lc=a!Yjg0aU?)~_)
zZTMrPJ!<1e!_42*2Dl={XX@PyC*oFzGUp<NBLUX|X*tW$*$f+JEA<X7GM-UuspW^K
z+tzo+%F4L*LOr1qUAx6Ue(?{_?zNY&r_d3v-r{x85U>BZc{6edHA3<8DT$*Z)_B-l
z9*(GQ6L>@q9!sY+myCh|7%9auSQYRWbWAY|A!>V&y<oG4TroYv8+^SntP$RyZpbjN
za}tcE!*hTY0vMwXAa7WVh+<rz;mrWZkQCkJNl$O0B}aoFtX&W3wOFDEAa*4f5F23f
z>#gdd5@m!jl-4(}aff~7`jf6@<$0=w<F%xlM}vC5PQwoK&G0&(hpu)g)ZH3*6Ep?(
zgWy{L2rxf9C4lyfdr@W_lt3rdy;15B=kGrC4x%Ptq#!lX#?V;<XbM2koWRZ=`04<*
z{-J=#0$s4Nw!vHkOn`dN1Av&MQC|5uk;H%mC@2Sr(TV8oVAc)uZmPjvV|tv&T%c;b
z2j4)Q4<l`Rsy{LPGvNwyS4TO%0v}6)VAUmXZ`?S$Da`Azh;e){U&%^_s+WFFS{W_^
z2%$^_gIzqi%Ug2vcBFjro@F2pDOM8<MFPA?AgnPFoaJV6-T|qlPA+u>Ll{K145h6E
z&<xjrv*`RczP@Q#2dd}!o*|O!BN?ZHIT7HxOyGLZSHv)*dZ!U~SvU$QpNe7HrJ(dk
zhD^#vGN)KU=pnf*M2n@C15<oZvm)Ve4f1Ys0?n1KOZ%nL0s1-)1jo1(1!v_ZITH6z
ziCHfWw}}OrA$0h_lI>2jH`0jTW_3WM{H!#XC90D2i(}UGay-pIdla)7abW{$$paZI
zN=J(CrBg94Nd0CM%L48~J(%f^gh4$X(}l%&82B)hkVThg@!>hzm9=uz$90()7n$?R
z*_3czwU6;>k>=1c-i^@)YI?&)7`E%KNSHfkw~D5tT=>~yK)AouR-0f$n!6Ik<0<q;
z9QJe!BYhetnaSn#kEH&2rjc1ULr4fu^x)XB)vOwbQ3Y0mW~S!&)>YdZ)}G6eq_!y1
zX>dXp)0w5z;TOExh6T3Z=FvaBTsF<!^qqamSiLr4ogNVK5&pg2ks?A$@C>2jWn{%e
zhopy09m0YuF4_o9avjz*&=9e%Wf(#Uf{ikTxd1#sH$vA}2Td@tbNKRqsX76hjJo0h
zY3Xg=6bqAX{C3?ik7p?@8m{9SwVoLB4OS8d#{oB*xR@F;oPl{5vRToNT#Pf^9HCi>
z76gYoF{Y6BDbZd@G;#>q4`5$Lh-AoRa>dJj)O;O^g75o=6+PmGbTdkfqt=YPGWkPv
zHT2w&2uDj(%tbD~n)Ic<jvpKguwKK@g3${*!~xi*&Z}pKAOdKwP`F=BT&}tV49b|?
z_vBCG`+zV=tDOs~eohVKjS}()ZWt4^6#x^A@)>|1DNJUCeu2g7>rqI6qot1KOuK9v
z3_U`sGk~v2;%UC&8|09N&MzHgTqFqXR`U}fmu@UT0@g7C0;Z&qk*-vY9TYFdUXw&c
znPs`mxjs7}ah148Vs*@0z$?|kFx<mrna*SqSxsV@;d9}@f=>Zd;O03w>SRj8LLIRu
z!M1{AFa5>O5Gh07&Vi(BjK|>!;3DOmkf9@K51IzkFZyUY4jMLQ*G!cJ?SiUyFpRyG
z_|yU|p2^-kg+L<fKn}ssH4y<VGKyKITv_BOzB`@0jE<BhsJcWSR@ZZ>dl-+n<#loO
z1t7g^FEC&K^IIO(_Rnvq&#OHU&w1mKXAIJ>Y7lMpla&qbBvcya5Oqr2Fp~+?6TV|O
zn1|JwaY5_v5E7tsuEWJR?6tS>^X#Rgxj4Z0@s`OYc6r#8kuHg!PNT~v%OZa)!zVcA
zwGZ$-Z6rn(6#>CX^~pF3QGBl-qt+0pk^n*VS-u08dEh4pQ)RL4`!x+^$0|Yct)nLF
zkOMrzeio;DNdh7RFY)S!9qL19@`TvT6Vji%JwwVh0S(0neG86XlQ%Q;$)N}hxc)JE
z!uoF!-hJ&e_0t8$*N=>?fFS9D`1ara3~?e{9!xEiW_^E|5i~~^&XN&dA<^lzckvQ$
zUaM)$o;5u|CF69!sqvuZDh+j}-b5|>#vgxZgMbMVIk4_zejfut3$CNE183`hGs2+B
zSF`bGFsD8z<_9cXJpG4{!6c1O<4{NpPu72oXo5+%!$_Fup1(ul6xGbPUBm#U@XW3M
z8lR(b99<n97gWC<i^uE#`RbJs=2KJ<&X3ZeSzH)V1XYXv@{ivpfR~*NekV8>)%%5?
zwAM632g20y<L{%xpi4Lz>e0#V_%3$mA-t046LTIOPJ|LgcpSw{vzubf$qVWuVPP^-
zt(&+P!9RcugbY$6UZ^CUhA&c7Oo!@q>SqL#3rU~B`Fw$L(Cq=<TmJwbI<Nf7Pf0u{
zs^;tuvc335$9zcK{3)rbCYE(H9IP4QpEH-*mEE9feOT2?_J6SU{!wyV*L`PAt0Xna
zq14kUjmmJFoGCWPO^5;k7_pHY%j)W><`jgYF@z_Z&Qb3QfVo~;kt~Ygu6c6gu&d{_
zSRfmRKbCs}TUwJuxC-NSERm8oRGe67s5)xJqmbg^X0fpyiHu^=juXOMouk=xR@%?^
zRrkz*_WrTwY!d`Pc1_iL_uc!w-}~de>KhitIY0d}VAbE>x@F$+FCtYj86rc<wR0SQ
z^J7GHj`RN3`*MKB-q?Q0$t$;W2Vrq#nO0)e*m`y2^8_h}@}^dH{O^0JrG1=WGv|<4
zcAjFeQ?sd~CS2doD&(K_|CbhuRX|FaX3FJX_&ND9eVUA-_$;~TW|qxBfRXZPK>%m}
zr?|{|qS;^f{Q1E4b#c_96`22LQoNj|!EC)!+;ms7Miw8<I3xqLU>qpg@?10EyXaz+
z9cz>yWweZRt~Xbuj3a``&^*sfjJ*rwkp<EJl=?^Er|T~~&6%ijg3Kqq$z@I;2Fs+H
zMI~^7V`f(8|AI{YBmDoR^OpoR5AhEn*c{)0u=qwDx7yEQDsK${Ye`@5Klxqyhnn<n
z{2lkb!EK9AEC==5qhF}6(Vft$ukpg^`-c;=iU;sh&Sguz8<rdIUHI$$<%KT>Ppr;<
z;%Cjr?yjFmE(i7KUK1ZRU(0y4t$#LMc!4B*{OUsg-i4=c@~em5*ZOPsEx&mtq}}JW
zX!7aX-^>k<xo77`@ci~Ewby1pvhe@?N4|i7R-Qj&if7#R04v~Pvz6#Vgw>`84dynN
zBISd31{kvtcs2gZzdIFh%7l69>YrOG{pfoFh{%e5u#5$B!u*d=q@;F4$RQ=<o8K|b
zGu|z?zjEeCbc-9lKQiacS0|=&d6JE?P4=t~=YC{)bK!LLsP|*RFQhG9`@R0{tDkKh
zH1E&N*3n^7PPhKTwKp#R{9>bi`(tOK+wMM+-{P)bZY8hh(~DnCkFwK)<iq0&hy8_>
z^sC{G%V%`?bFKgPd*9$UrUSVcoN0ia(@Ssr?lo&+q}XGsC`~%I!Z2!+3mlCGUacEP
zW6lf6bhaPKw|&cG@vuVbI_)Tmyp74YGZ{y28jeyR+zkAz-|v?i<S_RKXId-uGp(@g
z=IuC%yQW<ZQN)9dG|;EPKNss^QpEx&LJl^D<E{yFvz{6A-8=8`+*QC;3e2an5k*ee
z?q)eJ=k89z)zcxTKo<Y#JQRH*#?7GIaojPq{DtF<xH3<c=wRc)zMe-2<uo_gVC+To
zux!MGjjeIb_iCJve6+E7xM45p1^o*_av^A}mcq!SoaQi$D&544JB-Ra@WFR;@}nIW
z6u62P<FOi>WX5?GyatA2722fClrE%`vHUR7(mz~BM`;wbT_<gKCOPLlj*Ln9*vInQ
zQ~X1<v(XkYYDR1%PNJ@%{M*SM?5Fz~76P+keXVt-b)X)Ev<r5J=_pSJ-6&kA<lo#r
z`QcOHp7B}aS&t%Ka01Rm>A0I$`I-&vFZc_7CfKqfX8eo}A~R+VQR14E{!0#bTPg)a
zp27aofqE2#T+;3g2OATFYQhmK&gkwYyx>#XA6y86r1eA{QM98CE*p+vv}2C`_d6Ls
z@%c05Mc0bXDjRDNp+hcrOj+}-F*}MkjN#nlL;hKmth&#_md3^HA~PCvxn?rh$T?e@
zPSZhovq}b8YKCa|6Y<<pUu&&LPP5ic+BIIO3v`>6PPSPJ_%O^1LDXOgJk)kL=)^g*
zZI{hBrp0pmZ{309w5C;|IYm7N=xrbvexXru#Gxdg^1UN9j!{YJpydz^tbt#1`(!)1
z&<e;$`C?8V=q3@4qhinAwh{_32imw&tLGDDgQ{CyUn%b|?Ju$R`}@JAdONRkFUchv
z`<=v$(ssh3KmPWw{(TKlvZK|-%BIacBKCT_qrpak`9<MygfdgF-8WrW)E$#R@6sqA
zY{bmO#Y$O^%~nGSwZAY_<Z`0bI#ORpw32aWi)8*FK{~v}ofS@{2pS)z(eJn1wzrXw
z<EX|3S`mBM_J{t;K`*50%cHGrSl#3C61bbPj%XG(&8r@&rkWaNV$FvyBla|LAV(Hq
zv4hC3alZe`-F+<?7~8Anb>`saW3<ShH*IwaAlRdgl+il^k#DzJ&jg5{$_ql<n4m8?
zN>gSXvN!(vJ60Etkes!?aVj>KK~+4xh<P+ZvwS=lV=kZ##NkfXT1N~z#>SF}c}j(i
z9hTMfhRpQ~_11lLtDm`S8oA|R1wi4jYbobb!O~1M+fURnLhN}E$6an^n6Z<7=64Tj
zWJp4aCon;K5pI;H>&a-8S2psCK6Q_(zllL`ZaXZ^<LkEPMTy@*Udf=Fq!FSKkg!Ng
zr3MCZAy^^%zH(okl|rzf4M0MJI19z6lg%_v3;OL=^-J|?#2ssljA?{9XSWM=KJtON
zwXkhvH}egVi!z~9mAE@>C!j?xg(G~mo?)2}(zEL8w6UtViyg$gRa$sb=BYey24aly
znP9CY$VMPut&<>?iUkWJ`<6{uxU<T6GFoe46#0N#h9kQyH6Y;1dq2)zh$9@OxW{ZA
zd;kgqAbVhnR~|>v#0MuioM`Vbu^u^sL7ae8N!P6BU;%hh#w-|T&w>i0z%Ha)h>@(o
z7+V_2fY1glv22!$1wRMsr~@7m>@)2ef8bzfn&flag?9;cSw0rqF0<?sz`(dsSKeGu
z^W3wcyez0<t=F0nZE;rM2K(ru(erGagM}0h7Ei&62s{p3WY|$|ZJk5hgvclYouq-r
zmAuv}A>)W*q~F;Z<s;&)@?iTzKXoc>*9&VEYm}cAP@r<n2+fK>?WjHBkn2a%$NWtO
zCEt&`z!w9@0(tDmAQq4`L9LMqQ|;|K|KKpkEY)#R5s>30ona0Hq$y)HE9#j?Y7(6=
z2<wo^p~mBl48X$xMktJV;191~jOsfEQXmSC#!9fwT7<HuZEv1XV=%#n?FSQaK~FT_
z1HeKvu6gB=V+Qv(;-e&qw5}{#zyEk$hNj_hEn*bWw-(g5gW|VihwI1`1>*M<_{34j
zcy9c~dCX!eI@xV8EJPx(V;<ZML53IxZ?;K^XbM*+UpGJSH-_uOJj5ng1u$$!*%%bg
z6LUba%%^KnxSNdtT0IqgD`d;MvjRBtoUghD$Q*l2vFUIB;XlEAG!6T~yGncFSnw=<
zkQ*hcX5S&hw$D2j#|aw5pt%2l|ISi-K}A!L=ivXxX*wFzIyeRm!d^G!ThbRuVAtgM
zWDqdMN$WN*-1yE#&n}w{^o437Nfj?~^|#2&c~1(bdR@+*^Q~4b3pbh=qXSS4_|?gq
zHIyu4WzB<qc+p-nv)Cpeat7FAf(c>e5CY^>7Aj9IS3Y5_)kIlS4n`PnY^4KN1htcW
z>veZ64DG`0@%3C7Ht}nnOlytrH>}=cJANMcC5Z*?Mfk`?7==_BMQEIKCH@QUv})Zc
z&&DftVYUgn&*vbH<Eq(2`%fZ7^lTnlQ{&bo_1V<2{ky-&k@{DGMunA<!FMJGRl@ch
z3LfNj<n8qj&}(TNOEQnRn_UwL_vHo6E@;4_5wvtH*SK)?-9+5o!DWf@6}a(Q>*eUp
zdR;<p*OG1w`iWzpGUfCOzw+)yURr7~SI8lzr0ZNPDQ!ow{@x`cZGj`5F0p{4$rbYU
ztk~87UzwUV8i#F`QEHkAEsO@i>X{bLU6<NsV`~Sa3N8Yv$mbVVA;Jp^9`2|E2TT)k
zPF#?;YjF)5i?^ee^$T+QRyL9jxZt_?kisu876wWS=+Lf<?9^JjWbAKbZNJvt8l_kt
zHgU=#YRNvdL2LBM2tB|>+vOLh<MZHNmee><zoWhiQQFAaQnX=mWDW^RE8BmkeYL}~
z>jsd!=pHi$rpLVL0BEDRhZmW$X_I?f2=Q1n>?h4fDF|soX)16UfFgEa1+bL}r^H)R
z2{;6r(<l`_$}V>u2l@s=aj0R|hAzdOT#O<vrytpxo3bU5%wlY4k{l&Y9Dy04s-*H+
z-wfaCtJZBCgen8dkn~a8OKL0&sW+B)*P#aZ{9v`jtt#CZztD+8m{8O11E+R?zr9pH
zP(K!wfQbl_0q*!42?hs)h_}D@W2{k#&e@EM_>i2I0<a1z3kJF2Ma0Hg%s7OHMb8Vf
zwE-ln#X{7eL8G*yWflHzPF+x;S1aFX-CM7hWJZW=l8!we{z7XbX0%sHSL(sNbw+~W
zf{?=j0?%=owX#XSlD~5r<`k|$xgQA-WecGW65--qqt#`Oqy$gwhx@Rw5Y|d3Zq}ep
z5MZ;?m`0>rBCtkv<FckY_PP<UE<Yb^LXwHSM1t9hodhj#L~6vpcyAa8=Mg&Q#fPrL
zV>)C*kQmRzPPrc%DLf9HHZNBXCw}u;VlI$aSS+pz(ahJGJOMDH=7|i<0>2))!WoJI
ztTB>nl8q(<h9x^l@w7$gXnFGf(ur2p)v$G86pi6TSTol>aKE(RFDzz=F_e*rqK}V-
zt3-m9c~Ht)DAH&WJLB=9dF}@YZ;g@1JOIY9rUX-PlJqatCD@SY*t)iO9Pt-MVSjPb
z;*@~!XRvfKTH&59!KfL}W3{;P;<}&uI%5wl|FuXb;Snau4A&D`1d$6Mwg*KVQCc^2
zFu@IubHMXv7=c0la^Q@raR+W5M>sP0OAlG(Jc_zE%oBc67<1!9>ry=cHN-lAX&y0F
zP|MW=fBTPrjd}#QD-A1F6buwG2U3}{SN<Bj-5<Uxp%tW8@w66}^%fa)+kQOHR?Ti4
z4$7>>=Dm%h63A{qh$Wn91=7kykIukBLV8q-53T#V2E9MPPoNHhVK|;#PHNW0HNHhJ
zb#(PGxu46*b%%s`3Np9IJ*}mM2eXc1HckZ*T${u1lz{T_ic+<udm9bw0A@kI)iLDc
zh9le~$lb9V1an2CQiH;)><^x=AFc;hbDFh;6ip{0{FYDIHrod|5O?M&tT%I|VMr5J
z%L>G!LBvTt{!r)So!v`Wcpx8<IaV_ojhS1GB!9Z+$pKLqj~2t^2;EMegSH828)=su
znh47*O59(4CJ_JQxt$zQV^<)wvT6?;FXM9e1lQv01()LdmicyqFp0)-x?}(zg%CWw
zQ0RqCoRJzDl*g=}-<8vlzTVS-g0qUd!Ao>JV6h{Rn=H|AEDsSnfQOk)2Hgk_)<v2T
z4hkvnhXq779)I%7@2b8<h+HT~1QH=Y!cecak=bw}T^{X;CYXiI$SG9o!exE(ge)J6
z{TAXEtkmzV3rCTR5`1u%Tu)D(CAkeOM@sqaR`6OYIB6*e0VURx5WlC!dFiWfmus`E
z1;<t-cwE$xJGTAKWMpZ3y6FApf@Ln%ng77ah(t1Jp)gs6PBQLnjU)a>yolQ`Tu1Tv
zrvl`t*pmSg|4k%ykXSUVK%TPfdnR>s<F1ypHzG3%O`OP)utI5b`}}`Fw#U*xF)S^&
zEJDEnj6Tmv4@5by?c_*F-dpLP6*y|el{vIyMSB@;hu=cbCk<?NpcjC3O6G;DM5-=B
zB*#1Mu!tn#cxlkxP;H{J+3*_CF&qjv5c+HkwU8B(8|FWZr<tfd+zOBsETZ0C;z1Z!
zPp4l!omQ)hcc<3J;RCU%XhRp2iOF!Q5H)TL^c0y_ay`T>>nKe*YD2-I0kO=f{>sj`
z%pLI{0)Q1ik`LUpGT$t}@%!&af_phZQy7E639--;QaD~GhY*NSah&B<%%G`JA+p?t
zvgta$E>8`RNU?r5mQ^DAa2<*ReU&EQ6POjIyKB4$>g{I&YaJ1sftW;=h9fRke%lL4
z)UlOu7qb;cgIP6K!ERE!&#P_wKCgm0N|TUZo#u?m+Oq7Nv>!6(6h4<RHpLLT%Ou!7
zz}Q03Jo3Q=#x>xB<t$97S0bk!lvX&`4MTHrhe^AWMB`fQDlK#QoEwE#qqN8%lFr-Q
zFzF80^J@E3-h>XPInErh-ngg%2=XDD9`RQ<H;S<E01yBcRk>E##Z;B{zt++}K~)Qg
zZ1s~+6TC!RZZJT5aS((n3R)vSf%Ty&NrD?~zWy)Y)x3InmAK(L7*WEzlFaIzc{RO(
zLn0nYNgYq!h)sb~Tw}4?u4%d>6uk^^uqNfr;HqT*%TbXF00yW9bd#}C`1Ie~T!m%T
zrD-CHj1?x!6q+_L28nz(9CNH)_T<064#$d%7qsxt%wA<#0~VRJ4j0)_;UD$WO=wt=
zz?DTiEGht5tIZD}*%=yNkh(yz7#RWNq^U*&kI~_;ksboJse>gjPyejs#2Q*M)9faA
zU^oLZET@C*fA$G-vb%w<9T?VOqkCW!mmzFg^p5yf$Y?*y8){XrkT#IUi|lnx;yFe~
z^4KuXfq#GFei<x<0s6woqTEqu#UgT0j0>fQj!Eb7ftw|kAH1=;O1AGit$;)nVQCf(
zx?~U$4EXut$FE(yE3_=ViZ`|&9*%)w!-}2&(f0f~@5S)d@Xu;2GLt8(UZ$Qcb}v|Q
zbk70VsATMuNK4a~tmV>E!Ds1SL9C*N5KqLM6CaPshuc`sCfXPXF+e(G0qa*z0q)#p
zMY!q{pDSsA;s>(cX;}cJVt{2bFmXEzzvM0J81qG5{K6kfz5~RNKv)bWiMzn!xSWz&
zrTj?$aoYZ8K4Yp_2Z(uAghUzuY|koT1e1VFBW@f<LGod>RiV{7*}eop<Ej&xDcPS7
z-*ykjST6BshKLvyZnJ<=ophYkw!Cm{wD^LrlZ9Cu^v~8;z*MWw<US*yFViT8CN*Y1
zu^5Yo3<Ery4R#Rqh$H}ChGYIFThizt5`ohTO1(?<_A60|JCb?pX7ILlM6f09JJ|mG
z#;Fi8PyWz)GyIv70SpjbCC<V}ns0cUBd<*m!bw4$>>U0KLsHj*GDdFG?@plkBU41G
zjYs;2t-seG3+4)jz(iL|P1j&oEZ_iZAy>-|Vrk+`f;}Y2Qp3K-HF9xWD?Vh*iNEnS
z)Q}j7-V_^gN7mhYSW+$CNTShKUkwk{Qp)SR^FceEW#Sd#nL_;eQ8Y-b=z697&o@}D
z{g{Y;1DmPTF;!x1s12IPj1`2C25kV%B}y2GPJ~xjC0E<sT8ALR84&f2|Lrxziqraq
zRX@T=VFIBS0a`wuc<J#4^0S+aXjlEP30;!JIQb#z5z3Axy@EZwMfF~5A+rPZwU&&y
zCdz_ZCF5FBV;~IjLHzF??R&f~ClA0d8^lNTf#se@$>Z(Kzj4s3N`kCyAwVrJ@^RMV
zQ50^4_i={T4cG`c(U_^9?2-q|EW2B|Y%pw=o3CRcPqAcdIfaY7);e6bN~Oq=e8Ff;
zW`R|uj6r3Js}LY+8YV55+d-3J0a0YL^yZPje_i!zy`#Eg>w0F8Bm|GVQ0<P|7kun@
z(Vys$0U0n$Yw<wF!At>45oZV&2&g?feKE~l&D#;8;2aL4=kpg1c-^CS7wgALqPpn7
zxC|Liy!q6mKm3jB+n~!HwIh!Poq@5S2N}yTxZnSt$D#Du;JnY__X`;cs6ZHm1k*y!
z^~QEWGDak=Nb!^&>F-s))+<Wmtx<!Aev#XUXA;^%T@abI+T;?f0NOPiP&B2+Ivm3@
ztc!W_Pu_Oy&PY8hEU9InNJCUzNxsN`B^r4l*%oxvq+A2wXiUfrQBB(Ab`o<I7)hnZ
z@T5X9g})_-(3c-(CGltC(daq<`sE=T16BU!s#5f59g+vx!h^xzz!Acwa(ed7fBb=F
zRA>6qF^m)p0pDD%g+Hl=^9SaW9;ubn<U~<4j!nQrXy6uVY(lZdV)Ba=P?%OOXK!+L
z0Wb5mD+w>B(sZ#NAXXwnNRlfeKx!08EeU=(;8?}aV<)xDP&;~j2AzcCk+O@8PyA`A
zeV<1k;?kV6v`lnS6zUL{H=mE8?10$aQ0%)?ld4e%VWF(p5?_+(2KaN71MmkHQq|mf
z;?m)|YAqs=VElwMMoN5XJtUAuu|i&Wt<_-pLJG+!9T61fi|Ti>%JzGHNfn;uIYuNb
z)sUoFpodQzMVp9mBVW8L9XC#=WC~6*Fw5=ig$lD+fwqtH#WF{f1o6ZQ5PFu`1yExw
z07lm$jv!+rL#O&6?@J!p2LPpE`}-uN`Yn|#1$v6bXk$bFjq{cJuR%7hjZ#@6#)iLy
z#3He7Y|ymoDjNnbbD&vKLAS|m#Wny2EEDR$TtrCZ$E7umB@IRBM5jrPC+A<TL_7JY
zPE2XkX`0eni)YN|>qsCYut&9c!uHlLlh$WZtQsSAM!X)e6l3a=>=+I|<&pN_WK339
z;Gn^_36&$P&zN>M&S|5+rx63_gfRhatmF_Y8$%S-=hZouv0cup<n{E7X7r^xN`xs9
zcdlm<w3+{4Wzopjw=0ARTvYfXvh~(ac8xRcP6z<V!=6g<@(S^FuOcMD<e*-lcOI_W
z37Zx5Z(vTGs}i;EtHT2@#)!2X)XKs}eb^`gN$Qm%Vi#F%gtf|7z`n8KROylJ|LObd
z(XnL>hz2v}F7eCzP|YVp$3i7mP9oo*Wc&-yD)GQ|7Gu#NEQwW^Shqpqi25c1VpNSD
zwZX87%u~7(WM%rWjLu4w*CUY#n_Kj7zA_9NApXrSU-Vdj=|_sd)Z8X32uh+|8>T{v
zvST|;K_kEjo*t>UgaVf5<EFr>2m7p$V5Y?y%KH$IGD4-diJ0v2@PH=yES8B9WNsWT
z<MH^LkG$_4Z5Qa_0th^^$CF5~<U+JcUI!{+i@3N>KeHnRFkK>Az8a03CiehZ<JbG8
zB`XCv8A)Cks9zJ4Ydmp0;r&T=o=a7!bhE=a2AwTbme7gjhx-@b#?MV9!9cJY*|y?|
zcJzeTRzoz4Aeg~P@Qpe^6rG`FQLRRfidI9$(1Vd%JSOX-5h%hy1CS=a&NTpL?hq`s
zwBTCI^_U~Zd6oq#E_vV&ud(h#Pvc?8fH7z~MlKMNg<tV`6_Ip_t~ow7>LquQqdt(T
zCbuf5s!Osg&M8co0pZ9{FNk<&i<z@yjk6~7vxU!N;`wOcnlVwLj2)rg^U-U0b3}++
zV0HA-v@O<Epl$|*K36+7^0DVVR}jlf_CS+VRBVf9lPDXU$Hg~nWG}>!x6*Z5<$+K^
z`4pgV(lF2|2GwhsmL$&&RO`vnJ0t^lyYaW#6&EQpW7}CZ0c$$09v0>FC%h7I&hi94
znL?SYUdg?-U39Kvlm=8-RXJ~oE))l2RTf2cz-~<I8XkMBRGc4Q&R))1nU3hdM?t{>
z7u18OQi;a6P4LEwbl7qK>U9dW>|)7EtwbxJ_q?@&@|q$sv$=3T9Z@uo%1;5zFf`=2
zMXLhON?;~T)Jcgx9cbD`+8)SnGAvg$<{Sx7sF0xza8eF_Oa`<9aPv)yDvR!cQ_5Cs
zuQvE8M2N#A9MR(tq^w$Nk*^OIqx(rXaaKM~6VQ{-<QD=OOFQ5XhRy<r4^87-hC&DX
z&$LdoN=ix~1@X@uN*#qvo?nccQPa~IoM{F3)VV}3BO~k#N2Ab&G@b0%AGzp7SU60h
zXLXkGE4l2EKj3x~?_o~ItN}EJ?NeN0uM!pEegsJD4mLPyG+1DC_T`LoDEJ3x19P-4
ztS$6n&{gx1vLVe(SrV(^njg4?C2DDtHr%d_FGt0H<rkaM7Hzu``$3mba7MmvLhck&
zM;M;-j@`Kv!0QSbfhNaTD!xjtmie?v-zx`MvI@nZgd3D(bPwt?5$SQYp}>s>FW}E0
zZFmTZSBR6`Y&J$<e$BNO@O_e6E|o$=U^_#k;F7}nWYp~BQA(A4^Uh4_gcDarOZueh
zGsr-&i3w9^MWl#QiG`v;1HfsLt6HtHH1vci$J6fSs>E6s%(O%;UW)FmGjKZSw$Orh
z>~EM6q~KI%N&T6^BmR-!0)NqjFd9)w*fJy*y~dr{gDLb7ns131KExH~&{{OYgG6LF
zai1u!^oh2fwN`QxNec8PGzv+MV+_+ER8)%LI7_5AXriLu3W_~i&#45YMUa%HSAIWu
zDGEJpzO-v14Y%dBnx8PWv3K{VeRsOpIHcSLN^G?WOqL)kvGSxoC%TA3lx?b%v=H7S
zSaDaYLL*^GPB_sq>qZz3)m9g|GLskUZKaRU5}6B~eVBQUount8ygnjS6BgP*p>>D}
zWaH<fF~DDIf62Qu<Av|MDvzU2=wp$_F>b3)B#z0oVC17vI*w~BgM@{OM~OTN_cLuE
z$`y|L<wqO1UZEF>dTQrnjIaZh?{a(^t~Fsy>Dk9Ww{(azcp&$nfvuWqSl0CLC1ke3
zDz9B~NOsQwmZ*W%f0~t)q%`eLLSTrP_^8s2lV?N?O&?hjHm2%2FeCm4L%zGeQZ7Po
zVve;IR5t>UDfiBUDm;@G0;<hNe_ISXU8a}<7@*=jR1OLR8%1OjHzL3NJ<mHuL*rtZ
zj#>p~T4VVLfX77RZtje2AL_9G8bK|z9;>5q%Vq2=FbGf1fH-d~%VOLdrd6hauf*yR
z4be_((P`a)0{FZxEyF^x)O_OE>yprA`S@kQT+UASL>OdfqOq$6oJGH}Fw-a$7{fy;
zK_E1E3($}XYk8=gT9qRGie=(<d`^s{x(PIq0)+*z!<=z5o(AvbLQ)~_3%4R|Aj6`o
zUi|0R^Ir^TrcuC-RdOcE+HBRn;4OS7okLE(4@0!R4k4ii;+X`CZo9lrN0bSIP2vjR
z&{0Wef9p&2mJrMxF>TE(9m!HfT^YDkO5jA`fhpkWxMVUKV=}dJC423~ccM&t^+~~E
z+pTmbq(@m}(q$>{U&&IsKdnYt*MgvA+@LC1KyD>2WASN6spzmkixilx!w9y}E2u|G
zlL)Y+n3~||Obd;ITcT36&IBD`vVQr8-=TAC^^ms@1xK5D%K}Xh6h#8Zp#)HeWFfDS
zFXJth&-th6Pyq0GTU+7z@UhV07>Py*jus>{d^x*Bjx!(<bb6QS$NDAFb3zG_3K~Z@
z3|KZij41?yO+{>%$k;MA!4sU;UPiz*wmr~a{;iANqHBxFzEsPqI~c?25Pi`4G4T;C
zwi=>@_ItdLmIs1PE~<ip;v~xKy)9O!pnGrwh~vN|sw(P_xW#i?IIZ8sItB&!m@pj?
z4Ev%yTFCMP5p1N;Da0hRDkQ}sp>hmA-&**T=RLasmNyV67cg9Gle^Kqim4Aecnu-c
zG~`$!mDGQ}US%NAA_BL(0yNk}*ZqylnWQ9rI@3DUqDQhugKgYSJU3_QaECt=bCNRo
zmKi<?5G5KG+5t2$h#|dC^p}a~TAOV0ozy`5651OR?v$0fW}J8yGWK%K8cI!Jb|->8
z8L=W#s^T(${6V`?ZZsy@ATCFgXN<}cx44U_ltmjsla-CNe-~+*oD3POPp)AQQ?NmO
zrnz2lPCUhPE99O=mGap${R0gQt_M-Gfue>aKov4mw}7iL-bOHFFpQ|z%Ig8^jgBe2
z#`}%oO*!E_rH0?r`vW}>xKxhU`Z}Z|3A;Jb#kd>slHM$wz`_|fM1Vo_HHG1gNje&n
z8<&T*yqZ<uqsLee7nhYLk#W<nh2<0P_eh+QmXruJC(7kxMbctUh-a|<gZD0tJTzDX
zkwdi^3IQ%IJIT!*J{~L^9`YASeu#X_y{(fwL^@>v8>B(!lQP*pGWOUF)<f!@G7;l#
z`vktZBtQ#nf-X~wIXhDxRcv558+nshJ70(J%He+S|9VHX2vM54Hv2HFg87*yHyfh_
zp$W}!8R4Y`JD)0h<VugX%(z=Le+X<-gu{9SU^O8bIzgI@;0|;ng2lCgLg0|2?ni~l
z)F4tE4I=UhER5NAZIx4wr8MC1l9i2?v|ybR)p?WJ{oefMY4werBd@HBY_=-Y&I;TV
zn|=m}ktJE5ZmvN*d<a%?%A%9&FeG8j(7?5;WP_~syb=-flk$(CYb2(r6LXQ)eEYGJ
zU+`WHpYzlWI#-l-RA<DhSrO1tDO+W?CWFt`esAFh@9TU?C4(M0HSMbqgiLMaTWJpI
zWrQ(}kT3MYa@hk#<{OA6&8J_7>m<&|Ks9+$9}Eg#49c6~g@E8s2|+FlxJ+fs$LrEW
zT9Tk+q~VBKG1~IQ#slZBJHBwD7&b#7ajf<g%>n6x<&r=Invt3rruo-ZnWWVPtvl*d
zu-Apf*wJ+ql(FQ{L23!m*|>c60*C5A)KNaA+NMLX$y{fhwJgJofkNwl&uMbcs|A(M
zY~1(Oztaj@ZiI#qD`oftI1+$b$?pByH9YyaeY~V?2aeziGjSO=1wW$Q&-(j#$?OR-
zO&nZ4_tJE~3)fq9Xeu)S5{p&CdWq8o>jxSPgu#-$*Y7}XP+G0J>xdV^0bY!Kia3S<
z<F)CuiYx6DQCQ4^F|v46fDLS226pz%FaFVve(VU^N*n(v<;4<mDq^DwXQ<VvGCX42
zPT3*0$>0INshp)D1Tv6CVh;e0))06{_UKF}rm~*qHqW#;8y)M41`!_+7^g?wiNMGf
zQHr*mJ~NbtthGQ+fjKBc!xFT$i*+<Uzx>YQ3)NKyKniv?^g`5Pw=QuRWbIt-5wz%=
znXcGW(QD6;ZI;5phVgmv`c{*o9|IXO3RM!NAJm!%9~-KEQALDKQ1&5RoFwzuv~haR
zH=b`4S6WTd>~yk}&_SVLK7gUoY3Z{ILB#6wAAkFa@XtK2&<}!ObfwS`U_hcqimVRN
zQttC=+WXbEaD%^ZM8<tOaB>J-Dd!lq%LAgb&Q_b0tnIB%WnwGS_J2DbhOg~x2oMqk
zZ-7!@@@l{1j6bF+LKvXgOw}&Ty>-%=s0fKPV3Vj7YD~6e_~tL&|J1_b5l_P{Y!PEy
zmMJo137gs~xvy?~uJ)pp_H+KL>8orDS+s5Fvx^zF(q+o0XEetXR+3?fIj!;l0%shO
zHDj?7r!B<p{{clda4RE}%Xuj)<SmP}qt=zIOI^*GVK~CL>DL##fI_{w@Z=TGyTL1<
zL%_FeRaF`y`5|slFEe>Qz8t+8o=yQjpVtDgM^5cYQf&JAn4yIlxdTA2%Rndyfz${^
z$|^+LQIiAp)#uri$xwifajmAEf%uf+Yf@}L2g|k7+iw;7wbq#yT1vZvUxVPls3b-u
zoZeh}_#Q7Rc2+H?%iIF>&^Um9l4UgQ60e-AJs6&#iT>;-eYAvA=O13Mh;36nXb9d3
zTNE_#2hkU4;NiWE7p%HU&Qt-d7{j&JDlxe98Px;&EOo-$sX}SjLv#RfAE-B0P!466
z#^s!BCoQ73*8jnC1g4>KC*l@D4Izz7E)Q^~n+gW&&(goJHJm9SfS_d{66CVg+xlJ6
z5(f)_lAxgC*tl;3;EJ!4c=#XyC=Yjs(~Z5DAYuSxkZXD1SKoG=BgzRT$=)lqCI+cs
zQbwqV5NkQ&aj1NDNK0&sF)}EY*n%9wRT2{aOUOu{BNBHGG*-@I`4SajBl8cA^A9y}
zK|oFejWs($bu|*O$yH^U0Ah(-d%RA+4U-|bgfYUIeRc(T=bEoXmb@`ID<u|5-7c&t
z%>kn@GRCP)%NY22d>l)G58sH>v8r5{4e7{PB3)l9VHXmU<G%?!%P?yeE!Ev|*pf5X
zkW^l0PA-w4F;`C9x%A0m`-q4lYQv?1Du~69R0l=dJG{+Tx#uC-05m{Kg`^}?vS*+w
zBi;g_DBtj(=};_Jnr)T4P^kT-)xfexRuOE%|Hoqm7FJno$s1wH&arqpt3{8P2IV5I
z97ZF1rN8~7f5$13@ERgHN0Hq~ae9;7Bq<p%RqHjIFS2l1?40{BKF-Z0d9Bv+LK-$P
z1Y;Q?wXJbdCb4cLB|Z)KfkdtM+z@i+G<2xfz%e)eyt@`sch}sP=0F0}8|H`(A}c_Q
zkmO_GTDrtrMf~$nxdL3EAr>^`Y=I00xCQQxDRPfkC~&v>0xn!?Rs6<ZRtwZcugiqI
zgL&W}A#|cm9jz)!r$}0G9m$k6q9-(>Ja8%NaGozWy!rZK9{OGCfZ4Ou=n~{Xr$|8A
z6%`d<GIm^rWlcC~sgUFt>pu1xhbY+98j}=*7Ml@e)g9wRTO-2JCP^vwQsfx5NXh^9
z$ERk^lrxQDCFCii8cjZ=J<o<Da<pLuWl|fNk=>zGN+FV8P!<Zun`3k9iS`bd#>zHu
zX&sUU9;wyIC<vm83bs^O$0!zU6gEI$hIlb)(+s7Gy=76pF2dcc@c@9$r0@OAL67Ya
z(+`mi!fJX+R7N=sN=R2?SuRo^B{mU`AW@jlpU^^vhMZ>Ngo6s`s8G@Q+ZMvo9?dP3
zyyp%@jgBsBB2+8t?pBI2rdPJUc1oq=tDs7OgoIn0=WpQFTF9PM8Yiq`SvQngUu#uW
z3s@eF1Pk1eR?2%D+72rPu`0Dc5Nnbjl3|kxCd+Gb!%8#$IDR&uHHNH4DOf_Rm+EMr
zmSDpGLn`iyfLKd?GJY4clfW!qfy@Yu(J{VMdoUA~?NYsOP}4;es^&mkQ`+~<Sm{Ef
zwfActgWZiqSZHuTTKd7BgvHOImx$aQkU*jaMgI$dIl@l==A|V%i;4Mrh-`O*C%tZj
ziYRFNavpxkd(PuE<qz|=F<$<oF1u<0?VzYI3-qOH7GAGi6vQD_)QfG3f-L#9se0iA
zC4xAyTFY=kDdV7lUU6l~0#@)iG!PG_I7rntNdsIfzwuvR&)+m3TNeaU<*P`4Y@vcm
zv_hhg#!S8RCHJ@K0F{u)aCo%tvYHg^>|MAqgJJXr;zlZrBprfQ_F0uYtW<F@i6tv8
zcrio<_ptrUzx#F=;^_8bmM~lLRsOPunB&bu-uS3urGiyjTeP6%$QZdAcE$>CB&>wM
zhOR4gi+`txMc8q;zQW`qm@1iOQI{}Ba%CmUq*+f{-Rd8Pcse2K#9~qg+!%5~Jtdj#
zhyP0g1v^cCQzpmCBU?v9xhM1rwtx;6rpUL%dwCkMgO9JNqVOQeytqNAV9-EVi6QU}
z%9!gj`&lV1#H|Tjfp<ll<@TR^3w@GGseZ`CR(+LmqNSC5(UxC55mF99iHcqT{l$_-
z)|lLdN=%wFary{_VqMSP+pvg*p7c4bfj<Z^>kz9z*Mku1xiz^`2z>7D7v67%SBbix
z6)$_*F3s&J%<A*4H?CzH;*Okfe?)KC{g&2;+2lIdV}}mdd_Gl;*d4<=@g;U-Q;k!`
zL&+l2s!VgtHZzDXe!*HF<Og7p?<8KKo0fKc7nm(S_%CMXgsAP(=9Q=Zk5o`j{78;|
zEj$5mE<fj|%L^~~;QCZnEGY|zg5v?n`B3@>5y}p^oWk&S#H20YE9ftU4@ec*lgkDR
zsKx(Tt1ASx|7FTjT&Dy9mr|QCx?W(l{oX}w+L?)pE!|iSDNkr74hRqD6NyeaCZgsh
z?C>LxIU?UO&t!BeN?}`)g)(bgq78!yeO&^5`0I>=3iS~ev^vkDffN>ZTz=!Hub*|Y
zF7K6<D}3loprYseuZ6t+i%kW*xle~&P`TcrRv;kD3lB2DG=43ikOI0614WmGKJD=J
zh&`NAMB5Hd&rg9=W#!2CNNeSl=(Sdrdm@ARv6@qeZULApPyRz(jkP{2FpwXOpyx`>
zrzAHi@=)rVk|S9rzp(A@Bp*|CjL4W_o726{+(%JAzpLL&=gYLk7LXSpCe^aUuIZ-E
zsIsvY$(xcg+WyLS?(x7Vi|JEYfd}?cV{%ulEM2Pf<$ay-@daP>s=S9WST7{TVAfHB
zsNF3%1BrN2I&T%#T5E-*j2a$>18TykBHRe@c#92kxXJN=15HM0TfJa0d!p#Frt$L4
zA0u<A&s0{f1ya$pRM0<CUS_H}a`;*belCe?R0q^#YLub0H$cob^d5I6<M~R0V<kMY
zB(z}*^RoY_OtRLc;FxgoHaGs(N9U<%6dP5<t%^ZdhKE37*z&nrq<n(UJ2-DpUmi!|
z?C2EPJr`An^dcviElRwRtA5^Cd6uww3h44}oMN!bwjNY)(3v29CnT<d6lxFEU(hM8
zV=A;WsiC<$iN<R0;k1a~{Z~|n?Ns#}t10%O;^3HApTaKt4hiITpqW_!CW7s7fR~JE
zZpk=ly10QX6ty$PqDT>$BFsW7o0ur#6AWX*V~=}p<VrOSw*OXV>2!Ftyd-yt)>Vop
zrHOj(2LJeiZ<NJ4#Q7gP;v!Gz3f!r9Ql!TUao=&7i1{xQRtw2`F}v5Kw}^^|#|i=w
z*Nlf^fFzA<iWQVmYb`ItW0KA7zbOXj&O{}B29x02FahZoX%|A?LK2F5G%5x|9Tr*z
zQHEoRX6geD@il1|#5gAXN3n_K0LxPC_uQKsV&0>{JUo`HLE->q@%GDqeoDo%CES{g
z1EpDLI&x>$q!;qR9}E{>A3eP=L|p3k<aLZnpIDlpySgX=SO5bjO(ccDsxD`(*Wpup
zHS0pqzN^Kl`%**{Uwo*O7y!QPTn+9>>q3Aiv1{}JfLAV9&}y7FzW5HRnYO6Gq$Do=
zOWYshhHX-}<}zt{EKS-<oXL>9qI(6skBH^4_^Cvxi$bkXE%9~aDxJqQSR)M}BPbU#
z<K|S&*w&&91m9oz^Y03?P%X}Z+W~l1Mvj|jQ)QrJ6p_}mM^in$usEU9c}HUMIdb2=
zyKZvXh58`Qp3Kxwd^Hbk-A4uv{if)U8_KN{NCtGdiQR~ZimqB6vqTgdBewt%@mTvB
zycIqC;XivP3%OTXs6YIk_E3|r=ddwNb}B2yvj}5c1{sHA)S1i*yJ@HDMZ6yY;q=0z
zh25N-IBpqux6}(+313jyc^Lo)){qdA-#+o9?*K?x2moH|!40rKRsobClA6@M79M+g
zfvsX0O=D+y2aJU^@<6!NFb~PbvG$nWyfc_IhL->;waHLFOsYZ!gptBupu{zNq&#z@
zWe?NRqvZJ2X^*Z`&r8yfv8L%)zFWo$G#2|oW_CTwRQ=$knbsJeCcD!2GAWP%l0h<#
z8BbuIqDlpf<EW+mEFs-mNezY{Ay3V1W|6WCYU-)1M4dB*KRoeA@1pqoR?aC+Rx-Pd
z`EDd<4}nZye~ez08~owv)P~7ZI>ofmA5<r0@L0Qcempu2llPKNvb|ylWO>;aB^xqO
z>KuDR{im8UB~zE+=8~5npKd>rB7~J%-@*3JTn2V_<fTWefD+NtPaQgB0chlz<?~oG
z8|%<Z1Il%`#$`Au%54g970?FkF@|~Ke6WWlD@0{WO3Yt2kCtQ7+*KQ#P5Pt1jW!gk
z#qa2|Ooo<siZbc&&Lnw^GDOM-O|}dxqYs4X7)=I=o{=Ua0F_Jde1$w^)lF;>2WYYZ
z9~4xDdK!-u84)=R7<Y%G=see$MmnUKOhGBZfJPV1b2p&br-N&Zsi#-YZjpr9Gdjx&
zm_tGaNxXo51){wf8d+mr&nxU_q9Kc$kR%`=ovI5=ENs?X<ceTpWD8QwD81D+0$o&5
z`hi=<6IyV8@u6#~)vNuSG@nHRU@*AcUww7-O|~nmVpdJ}u%~s&o7j<PXaePvV@ksm
zl0LE8bTxr`t#vXYJs@*QSiUx_Tc;mDY0~s6ZPGzVRY51_YcK24Z{e4({NO);Av==7
z@X!__Idpi7Es`RzK+#kZ5s)p@@#l%V8J6q{EuXS>o1?=)snm+Yr|Xay1*;<rw?A*I
zPoPm*>a3o<PNar_7d~TqXJ$jd+)yk;G{ENAGW`uw=*OO`J?EoHbYpSWmNw{#y%g;;
zW3mA@wgux^Q=%8ENa9RENoUPak(L@Ub6F04Gne90o4VNG-H*~DVrs=*G+@B(0GyHZ
z`(J&S%XS5$Jd_Ye0))>H0`HtAWThg-Rzp1=4|=RqoQ<84AO;oX`A{%;8%`}LYH3h6
z22@<+7AeE12_TI531Ma@`{CL(RSG(LNjSG-rDYPV%@!w9MtAb^^4|liVN0*3r_;S`
ziPb`P(*a3adxi+-xM|mi(!p=xmLv=C><p4)DzRevpIEZ1(!gh03C<rN0j(y@ZqD+=
zIpa*7PaL|gxr0QEk6Z@&%j6<i_=wCFlM$xO<iYsSZ+8%hc<PTDCJQ^T--{L4$caFQ
z2-c7dgt%G#Va?^IWbnW~Ia@M}lmu<ae)-o?B1VBzwSE=U<T?TgJZ3u1YvBzw&XId~
zfu4sUZEA`Y7^<`#5`scPe>3PxRIxt);ed3xnu+z%K^mf`%w@p9T~^<W@EB03Nh1xY
z>{C!!r>l?grMaT541Cl2r6>OOJ9m>P#RFy6IN2?O@V2Z{hzu6<lc#UGM7@ZXEIK&=
zAd36o?X7H3M;4SV=pImxOci9K^R{i03z!f&Co*#>jYxXN03mZ+(TmqF-Ul&y3z3AC
zplB=$#yTAQ!DQh-dz6hwzIv}7Uf6_s?{XvP7)l%xr(z=&oi2$Y4}7LivHL1=bfA8)
z9tgd}rtv2T7)vk@_OFUjax!!*v{Li~?4}zd16;!A7w5tELJj0nv_fE}HqGEA?Pe21
zRmeihfGPk-at%^(dS&4fh)cq^0)--QI{-T!3AV6({Ws4lZlN@bXuTW;{W*q*DO{le
zsdf#MWgJs_gpL#;#F*CK+*=Fp@b-}@*Is(|qfN<?MuP^j$A=6n`}-lK?AcO@dP<I(
z2KWW|Jvzxk?&J~>(OhFT$?^(?us;nL2Sgp3_IHKi>)E%ze+@;|*~iY=X`>givw0>3
zQtb-F6?!*gMu}+<{%JD1+T|iL{Q%q@e5UrvnRGN1O%riV*W!0RQWh?z1VgbHM)HN9
zvnOv5gzQ#Wuy9Kl?cNmJNys4wn<LAK;MCNlcGH!JSTPIss-xPXyiHFPd&k%_`_{sp
z-Mm^wb6i@6)Y{Jv5t_fiF+iK81}RIMuvC5XE>bHMB0I`J<q<3j4WM-Q!B4W9GdVe0
zSpFL?MF(3nYKsMCY?rbZAZ7%uJY7s-m-+*JQPA?~w=4u6SQsN4LQ*3NQG9km2xQ@d
z7ZU^B$a1V6?Y;7Y8`RD<8$uBRktWoYTZ1QRyg3z{;uw{;Fd`S5re0t;cNU_X(Bg(h
z4yZ6+2;NGGEGH6XNln=74XPtlxXif*8S_jHg%)MdSMEqUy1Ug@e#~QbSAO=F_D~`P
ztym8}Z4Aj!H>ll%qlDvBp9-=slVX2myOR)$MarT<n|9Dj2*O@E)QT96?lTqhb}|4m
zUi6K))~EevJ*Si`g-jpF=2q{F2-5b{fdT7cS}w9;N`s%SRY%o_>1{--XmTp*c1m5!
zPKZ|s2}y3KHNj$bI&9HWLF8r0ql%X5IAB`_(<D3?&r2*!EajME><xoc_WMAc(&lO@
z3h@&I1d%XY=nN*4-gxru6}7Avxn1H71yX1nssggp8LQ%-vP1U6&!IDzWm5?kcm}bi
zkZPt;g|r>|4Xo)we4zURc0iQWJ@*iOcG+;HHVTsK^NxBKe(mpym=urT5~?Kf{%{P=
z(i^;z9I9=RqTCl|bJWbiq2j<`RV}zx84s=EAs#k0P3lkD)nhxlrmQH3UMtEn1;+<#
z41;1@k4TYKB$v>VhBvl6u_&<0Xbh8!x7YrSaCtT=#;vHih{5wQYeI7|u?0w4sEGzm
zs@H(@5YsVr6x5rgm|?Vj8Z4Bq;LapR6h>Ff^bqvr7EYRzNsKT_U5Lx`xBrJPe><e^
zw5v#rN%-nYJGe|pe2@1rdZ5UPREN`pF?Op?-~-Rnu|Z?P5LMv@RNexc8&OV;M5Rt`
zp!nMY(m7%hPX(;{ZiSrNgZ<5&3LT(CM5m<2FrxQdbw+CG0P|q`g@1rkFX{tD2?LX3
zeOP)-crqYACYmo~npNSDhnx+pDP{FAFZJDVJ*Q|*?M{Z(w80#qqYg1c*j8(m&+V1$
zddj-Novckf(2d6|9wE)7aa-#;8)naFl67pTKTyWC?j3&nJL#R~21^3YVS2>=w6$pb
zx{{O(BZegBVeXKl96Wm!PkK4JRM%zJlDiX_*T5Pb`ZQ%pl_%;<4UZ2)wh=WHq0A`F
zxzj4_@EH4H#hIZM6XbPEA|r#VWM?4(zGv;)WF~PcSQ_w7T9yX9;_D*Vr3L{k$Kx)$
z>}2^<FNuP<s1w#fM<os2>@LAn)u-@@&&=(kFO+f;zD`?pn6@2>2sbqfDiLNaT#Sxd
zdi0hCmEuYwqZ&EXd_c1^Uas6Q*xX)JqU%!bi@0bMQORL&BhF8O1#rp_+BWMVxT8*A
z6<s`N!DK8z%*Uh<$@($M)2!fLP>>B1u%X99q0uN$iA&5>j@B4Bq7QQ+vB>5|nB=Y=
zNe<{Vl?(-qGR^|~Sdc<ktQA_+BuSnc%n4@)r{K#gKlWwLy1I%I2;umJ6QMjMub7M$
zk0@<PVv;o59{k4n+9-G)>`vy#m>+bYZ1x|9C}D9k!vmb@)N0u*TN>taRmJA&dr9De
z;DYe|!OIaXXrc@#W{ei&q}VEhn6AA4k5HhgK1q97cK)5`=#E6^Hn<^E+|efm96I4~
zoqhx}LNnk3DzQw(s8B)$iY|@X17%pI_BK^19wc?79tAM3PvDtM2{8?}7r#h`Vm654
zE)=|SrNyCn1jr0wRtHts#5j1o+vZRco#$dtkDR$%4S|1w2M$`>h;;%FKRQ)wK!$G#
zni<(vjyq0mPPDT9oBtzopN)V=z-&16lH?s3I2n<kc9$>n0L_CtLEgC$>!0f-AJh0<
z3Zp>)7?=aZfgT=POqwD+`eGl@$sIghZ16yM!5bfXo6g0MyWcS@ho{(6fnfH8f63ZN
zuQE8h{3@*{JFUS*la9S*=#WGPFNv{<ZdhL0B4O5h_2q<4@(2W-bToh+^hrRzbmTyv
zG<I=V06w2G5*8>GM1aDeWDGe~r7COQ{|E0Ti#?N;rNf9LDGx*ow#GKWAip$Scj!8v
z$(DK5CYNvsqm4hN{D{@GB~INOx95O+^7wN3_7VIy;hy&J+7<zRo;U|fyY0`f6Ti7?
z7&y_)Hg6K?ByDo<c0cy)PN<D6mE;_$Ok6PSWD-4rv%QJ3rE;M}ts|D7h)f+r#a9T5
zUzp@PKQyS#b1M=C+rRnIy<AZa2guE-56MY)C$Mf9rIft5i<A${=J`om`9Zq!E!Epw
zB0+}ugqS8<M#C3O)&8*175lM15v{Rj>rg%U$ot>57G8}pM1)cXfuey6tWVl^sS%Wv
zEIlP}(HiD~_%&EaMFO>P$LJ!;{%{bS6(W;j1#$I?4)p>DNWmG|>PpRmVO$RI@H;?5
z_CrjOWl0gU)h@D)%%20C{#|L0>k<ySAwg6w_EjslJvvpaEbL?>%g(Hsai&T}T3@gu
zL82GMl2}>GJm^^>a-x4mR<wf>$XSX>Aqs?m`{Lwm_WJu@-c7=QcPN(*rbZ7iR6h|m
z*)FqPnG+weO5}2sjYlQWyy8oYha`s5St{NP1Qs{|+qE$rp_YqvKqce(3PqJ%gHQkA
zzup_DN*yfDlQrf!r29s8oHOew;zDJ@cpQM1(}7B8u~P#=<49)UnpHO;YpdeGj8axW
ze9~{?*}y1);E3Tr`~mW0SD}m@C3jJTmf}9|9<8O-v&$;$4-1DhEtY|U3Ya2*nUF4K
zM-T2nr+w|ew~<|~Ec>6YlWY|#uyawG+Xn0lx2e!#M`40Xa^WtHUWeyw5%!YG%{lVC
z{J~#CDR#}<E;oyc4(PG;T;&ja;e@doLz@zViwt#pPJ+k>nD|ZtgJ6$k7Layh5S3($
z-t@&!7Yiw8L0686plqlC&6|V`)b=0$x4R%$(0AY?DI35ZOo!l7*-^t`@qFZ>A+)Ir
z@^yyi9KpqQ)=AnDh3J_!Cr0dK6mhkmslv-*xkeX^B4m}IyBgyg59)<!(+~4NU+Hgy
zuWjMN#_SlY;eV$pY0U;9nRX`&AutIQPyl2X->jyAv&KM{*+BvanxZuHMGh?wQ9{d^
z!F}~NegD_?q?(#80|bI-TO@EG9O%YG28z&jgvl)IjnI0ckWet-0%0~(v6DcF7$LSG
zDKQGW#<NAV_9y}qj=Ra2bU?xS&6Sm(-ZKoW9n<6Av1*&Bqt7N`F^QRJvdC~hpb|!}
zy%wF=?y_K{Q_Hl=nF}B|U0M$*D|=deTX2LZ$LKjojOH2)1AU0M5B*d@zOf(8MC6)*
z2t3tyxpmI}>Nj)x7sz&9rZeVF_C%%B0~HkD03*_k@=08sU^PvWf(;Hc+9?R0B-IY*
zF=I|hT#p7Ws%fKdf?it>sBktQC2{1q6@i&3{*{}41$Sa)S_~&@%ivr<oKmX}=-^oh
zg@0!ek;~V_@CZz#VxHcY**8QQ@O^qK2lP!-N|`TobEX`!d{(kXuR18fPQ3Ak;ndeF
zt9MQto9!@^t!BB`b8SuHBwkO-HMKFm6Aqx*@c;{^lY;~rKs9Z@VKps}Fk^~1DvGMX
z1GuynZg0*N{5%UQ);vku5gWbPSBHAPxbQCYW`_tM6p>h#XDi1ZwQmmngg@@sd-13c
zBbIa2(Xc6xf}z<5*}MrhHUNrX5bTa2yx%Eg32lXFH4X@z&lTe7r=R?tw<96@<NT%t
zllNiM9!@g3Jh?OSzd`E(n}=22OI7F7mRBs9IpN>%er*UFc&7~{(?i2{3Vi*?>kTG|
zO2YsV4u41k_(eKvnuMU)*-jfwq$fc=dRA-8S5`lY;AR6u#n9Kt84bFu5dt8OkC9Iy
zj0M(sbf0pHl9ADfLKYC8RS1S3l|Q3dRv^cCWm;CWQ_Eoyu{!*X;I~bru@O&4I_P|4
z4^t9YOW#}zVPHuzCKEFQ0h}sxCG8jiM)>B`AY%qGW!LIw<EOPWc!;P>0#XMo%#2&Y
zXDu`hy;nv_T=E+r1=;IQy#F10mZ^Xd7tKaz0Yp?9^U9{eQl?3wm^Wx6JfjSR5dTht
z9kRfzF-pk)>m<Y(DvF^c5{JbY!Z*edX_tIi7}AZDUpMKM|M<;4?w|FLVTC#Z0JV<4
zzWhxNg4xF#FBTdj;A2|CBWkwz0nC^%f&{e7DaX$QLoqY`TNLmN8xTQP>wXA2kPvO}
zBpVx#&MJ5^At`Wo!ucu$H}ixnAN&({k5Hs7vQ<bhju?C<UKWJ#E1h~;RKR68B=3E;
z1qnQXrJ40es1RxV_*g$gK1>BYBU)5oFCeAW#|h;mfe;~8EuzRDuDyHL+ct5A7U0ol
zfdNi2LI-y_(UcyF-F0XKV&}77#5(nYc6`ji7CbR*y(FRd6ich&b54Zbh}LGyEV{y?
z54Qi0@m>wp$W($Kt%EhzkB|Tmo)xBG5uLXi5$({t4_MGtF;h_KC%(_*x&>e{efHFd
z&^BmU-XvV&r<HY<@^1g?acieba}K|7E-VTEV#yP2iN2@<B>Z&W!t1GeE@!1V?8sh6
z`3?$gOA%g~@^`8&f3$hyUG#ap&H)kF6ah!%@W@n|p7d;$Ez&_zmTNvy$7i~DD8L<u
zin_`a2ui>Awq5iPd@wAe#>!$7fSa{-{bx3F6|AqWA`7sEPmZ~b0ylVhp*_qJ;KRBR
z1C?2QJ>_w;C=CT-Nh07sZEuifNC()uQ`vqYxrg;AIt7HGb|V>UjqBnkxDkmBliyLR
z9$&Zv>bfsIo!V}JSr;$%jL{mNtM(xlf%tdQ2p&N|HqP1UbzVBt;!3#92#X{ajWUBS
zoa1yrNtd0bxc&5mBeQjQs5a>tqfQ-Bru@$&r$SNq-EvPDDI^3$V8Fb;0rQ<Q5ysBN
za47^4ftgsJzAltS7^81#-{5%tA$<nq&89alzH4&k3&}m;97UlZCIEW<8}B@JIy`2(
z;q=mZpHi=qu3DBH2{5a%cb<0VuOFh4Nx!q&ot64kmlqq7t@`2|NY8eMV@w!HrKZx*
zX~=>bDol2Z#&L2_MIr$=fVo2|A%(cZ)E*>_tT?`nYr-I~(~c>{BlsFC>om7-yRkyC
zRjDs=q#h5pR?i>_LUf3hc`$6>I`^Q?wvc)i2i{oQMhA%&&_0iyNOZ(I?5sC|mCN+|
zoTN72yC}!VhEtYIk+1KS=uqbw4kZx^$FzbmJ9#nZ4PMK=yJ|8<xm-~w^q8b3!K$7#
z^AFPpr2}`&4y$MYCr3$8^y&Jrt|IGne<VWEm{~zGkj`|N(r_FME{E1V8j4dQZxQKx
zUYjS5nXa*_F#=Qvq{3P(ui_e%Z2B0vIb8tswJ}}U8Vz=omx{;OpVcJ-QPHZ1QRq|L
z-<mVyfOQf=M(YU<8I1eH8*ZdyVH~ZD4%q>YL@l9?B#Y!IhhGa9>nM#f3UpG)!fee+
ztsl5`9)p~elFt=8GaTuR_MH?x&76UxZN*Xw^*<zJ3u#~+TNtrN1(S!8qB;7F6{|{h
zSq-#18qcS+9#;JAhyEjNpJ*+bV+SdoZD}eB#EldGl?Wp^MA>8C@*$s7cNn3ML$#YE
zWpiPUVPSNYgf|oPNUP2c=vOmLpHc=5Xu4`F9!R8;_&O{DL$~_`3rh$Zs5<AVTnMy-
z2J@Ymv75KWz3rvx5C4V4F<Z_eX28A_mS8b?q=v<vJhWCDy&&IVMgs&cyJKZ%{A>C(
zwSVq_9|u&0tGc;@H$5m1#X$fA{zmC&+xw?`!Y0`l3z-X$NarziG;Rhb(r2+IGop+I
zB^|hJpD3JX7s_J4N4_XCBiFkmpu{%jD!#W8br4oe$zsc-LNsFI2U^$Ilf^k=L%S|?
z{DP&R&}g#6JZ{}2r$=pVI%IWt(Wn-)I21u>2}|L5oZ}}Kf;4tt0$_R11vassVCS(e
z6*0z7gV>}zgw{)>u5|nd`twS3QoI+M1&-Fp{$q8J4)cj8=P9wS0)1>WCRVeR!6L}j
zs<8szD;!qxosf(Py&g7)rZzN{JdlOO5z>uhrd+fVbf(~Sz#h5}O4`C03V*`xUjtgC
zNK~%*UHlwH>IIjqN3l4`k+&SUL)H;bFq9l=;I{!><%K_f2QkU)!xFOo&?Xm8Otu3&
zM+v5J91VEjJSQZHb_@tWV3l~@sk14*)!E1-lgTu})3k`Q3<fh|!YFQcOQ}<CK<_Xd
zV6gqgf9^QQhUM#}tdJJbf}^a+meI`V@Hjixik5~${_bWZG@jQ-CG-!BQV!B)FK8$0
zJ>C#;rG{av(DrXZv|4o`%km?FV=h%+0qeLj!5X15_T-QRDpN(%-O+&FtCUiy;sfX3
z{xzJ|Oh8&TC3~dpA*`G@b=HE0>VfHq22*7lNSh=J>wu0!K<$qg7ZAIMwdU52xPT_d
z8Lo#-M6ZZ4Cg%q?!02^>N#FQ;?@&wZ62~9_hDeD34;2CqSw|X9Yaa{uP4{7i&#L!a
zt)BABGFz@3PzQ)4cGeFYE_0~IH2=E8OCm5+IIKdH&IDwhg$X_!Z0>2NW+SrQ1{o^f
zNaP`XN2##p?f?Cc4|?|1u)7O{4p^QGY67vH{2ShM!`Q<MXO}spb!VhnNyI}@gelJt
zXm%KY9(GT`)dSToC<;<8bvro=Fx#-8`gNJ|`c?Z1*apQ(FNoA77=fM+5T}7^-2Wpq
z7VWGjWL@l)qVkw+@{BUUYoM7Zet}+A8Cli!35=76B13sv{$skVAg7F#t;BSg=aMtu
z&+d=#c^G!H#j5fv*Pfxl_QyW(C>>14mRZfY9qf`yaWghj5i*jkY}`3qJg>@~DmGfv
z;*<qB1F}QF0=YubSpHfb#Emng%JnH(8U=eg9<1of+~jb$tvw$4!G0>=0%0LT8XT+2
z<mZXWm7|5VSgNtT`VX3~M7skNa26gPaZzH>NWXfgQDX@29Ec}{n^b3ru4<A2VoeCW
zVd>xv8+Zczv;%NipT?PZx(NFcl?U-vO(l|)sxdC$twAqe0G#9E6Cy!&qK5`X{jER0
z7OkI2R~d2yjM(6P7!<<imY8H=a22Jf<zq7fjtKBp(pK5mVr6GvL+&97d~KZ`!=8Rm
zs|T?Z87&+><rY*jF2D45=e3~Ik0rjqngD?bNhVn4)az+afSe4q15rH1|5VSX=?)-;
z$IFjzNqO}>!{iA&p{z1RBq8N>ge7@XXTX)s2R`291q*xV6VJqO5Cbi*<YnUak=k0i
z8E*Tw6|8B=H%lb)ZGBGUj>{yN)XqnAiRJRH534dg3!74&<Kj;?Fwpzbjh(PGOWzf=
zsl_`M7{3o*5gMrM9kP_>`@akXtjZNb?uu<#OjJvatI#nJ^TSViU-E2EBc(<No{goz
zGb>3nhnt`>8Je8}8Uv0^s=lt5EHE~ULe!m;OYA{ozbpwYTGYf!A;Ksvy8zWxyN5gB
z1awY%6t&5vlT)J-DW1)CwMYI*Z(%p77coLnkcx)b0asA(F`jLfyTTnav^?cU=P9~H
zh6F#VG*tpy4r3DrWSrzX=&VoiokC5Qk{v}V&?DiMn4Af){ehpOqsXuv_QU$EGeWGG
zB1(h?Z+XW?-ZZzXE0h;j*>62pU7A(_9emQ)iLUzS3UC`~fLiq0!49pDLmV8MXb;!s
z3cAm979_b%{>CK*z->SNlaG3fPjK*y0wth`KQUmTnf_fjL^$*na%Q~W3pq==7*v6m
za^>35LbnYiM>&A0)$D#v-fBR-fg#g0!I?g?YW@*xYDA5;EEgtAw-&@jd}0J29c+K~
z=2M|wgAFUvuyjnJP=(dD&ei1n?Ujh5fyBMRL|sExi@!?6u|c_Kv=XMn@k6LOf+6iG
z{Y8n2f}^_5jt2z=hXdN34HL7@;!BOrH8^<nf_{L}O6OOe;g6OZ8YiMS!ZQ?soNIjR
zyRIZZ`)C#QWR?&P&g3fdGbmt<;a+T9$bb~Kg%HEc+WBq6u)eeHq6vp_uujFt-dJZX
ziw<(K2?|D#j_ToT@B01Tf_pV<;`!FwuypKP{;dCq&QG$hE~H5W;-Cmc%d3kxe2`J_
z+5q*RlAq!ntT(CTTL}ey&7A`e9<8Ij$}y6(cj)f1!okmSr9FhGhehghsg6k!R{{Y9
zNBqIhP`m16xBb0$QVpAZWMTZv+zm#?pY$>fF_l?;+Byz+4XehvVk1-otlrIKSm&dH
ziWHsB2zR&55jTO6;Fq=A7~@SN?Nh$e|EofyUD~9)xPnNRXEzBpVaiGSF7_J#C0p37
zRSJ*r^IM#UhVx-cciX0Yk;@`U!QY~_R-k!}6c@S`x2UTPUY8@2Aklc8Gl8Gwdv&{#
zAEBoN7o{DhZ~S~|Exdv4a=aZu9<~Q6FgpF4n>^%?K{x*T>GTc~{FF<LWA&V+WF`_O
zspT=t!XIQU<haGD8&!LjGlnKRlc#kQSqUvMeg4269_$Z!LkGT=b6o=7taGG}v(d>-
ztYMqtoy)>BZv4R8aBc<?z_2iWl*d*A(DImyb2!eu>Kz)q8oO-aO3sLj00g~6Hsm%s
zqK+<+P4!pu^Jo+RL2Xlpq8JoQ(l7f4F7hb-k`4xywR;dHLxLHEk=y?GiBqA@{s*Dh
zU7;G8S_`bn&7)3vwE9U-mFFZy$p}uR!7>mOn8PWMVn!X0m*q)5I(HW)LIrF|CrcF<
zp$kX|0f_{hZ}3)^9#jeyCpuVbq1F!gtn+bMy#aG$qv8E`U%R^CGA6lWP0pewa)hBJ
zZ9E++ZeJ5p^sh1;p=wjRpE7(F24V)pbSXdDpk;9Pd*VHtYh$eTd$Lb<$0f6o<>r{T
zD`&*_<tP8hUHneSboVGw;c|&F@IQ(7gdkq#@38ekSZQA^BjKTDIqscEtUF=UWme(A
zerh$g1Wva|`CF4Evnhr|P={8K0anyB(;fQ55FsD#ltcK4H4;)nT=k!Rf{hY_a0j&p
zcx>TH_Fv&V5)=i^8A*AVhMB65KoU<T0svu9HymF&=cKKNt*4`tOIPq#7s`B0A9I(G
zU|b~Mrs~63lmy2(lu@#^fh(W+0p}AHDoO-}ZWOeHWyM2rn$FonwY4zytBbse8J~hM
zHC`4F--@#zE5l0d-oCzJMMtA9p&Zaz8k~!Z&<<qTPNt2idZ7!4H`<pftq5<N$~<{=
z(uS%;F{%Ibrzj0tV_#<>AFqrZs;Z(;#F@ZAMb#Oc=U7lAXESw>OVT;8cwR#)rix9l
zSW+IRM?Q)0dxO#||9^<bC4|as5vMo|xCC0rG13&QHzlzMhKyqR;%~lF+bDDjSXD_<
zEL`4G{=r2qDh4I2(qmS8iYP?dBLPDGT*OQ>Lu$Py=k}GIre57Bs)o@h&85;naTU6O
z^>EP?eAH8qd;$(CKGSMH1D#Xl0(evl3@JDY2(R4;<-b~g7#Vs4Jjv1WnjPRr(=T?2
z;7u?t!aRCrCY%lsh7NhRvqCsN#kbI7fRMcNJkQXs3w7($!w5`T3awUEwWM{nC`Y@_
zx4)!g1vqV&wJJb|$747A64ht^^+R6jle(##SNoGy8`hGMu#Z@IE;a~Y4qCPbohhjf
zNtW8|51^&GNEr#yAFh&s;+VF|r5Wr<wE#J$lY{bVIy1V4EosNzuEy9M?LizuLX^Nh
zdyT2Ho<IT<$KkP>bbZkiLXMw9-09j_DumKt8t4Ulu_$Hke2eGM;xI?7jVvO=>@reX
zSn=Lu;NQG_=RMx{U>AE}M*<OU+a^eW?${?iQ((=m&$6S5AgEvt#?7MO2hEbz7U>K*
zbk4PADjHHeu=yHzv4B$H{bf!yoZ*f(@RpFF1}8Ch*-_iprfjZ!?IYJS@IBB&;Nyus
z5_0le+Z^)HdaD;&TGAwfW=gPFj{JZ-YL=;gP9cXFPO};f7!=`#{aQ=4M|rR)Xc`Df
zLQD*$W}Vl!{<O?dCn&|P`V`iMUZd@Tg&W8MgiBZ+pwpWI6NW{?5#FKvh99W`N8YH9
z$HE(7V5%`xm=0o5v|`{U1S_1v2P#cH)(U9Sw3o2#@}hZ2_t^H0KeL39lSZ1Vs!b(m
z)j;^DtvyEJLAx!_YL2>GSpR6uiT%(&MW%YK5@4&t;Lsf|kiifI=v$Or-^!*-JyJAw
zidY<W!p)JOlU~{XgGUQ6;Xq^&QoUXe(oTwoF+?N&=9yQ+Z}N@_oAO9?jb*MpQdgi~
zKxAm+3VKD$kQm^m_*Eo6V6n>kNE`L<^h#q4{V-q>-kejKAZAo*j#U|#U>B{1uqVu9
zObLGY^0BwsXX>{imt~z8IwCqDO>)Pak^Y#+i9SRf#Z}+~Ct-r=tPN%ZTU4JIDx(?^
zThQQ)j1$Y(-x@k`T$eE}EumD)UYBZUwnu|#oIgbzt^6X41uoQ`7-BiLUDO`dLDy~(
z0#V3cMuAw>BKUHPF%syV2tVm<d&(i{O=KL-$9U!6#Eqnba-Nv<fE8vae011^!T>v3
z4MrW{doC56u$S<WzLIUshAY7|T^5~asbq;rnG9tnn^iWqU3&NG0u+*mDo|UtyFhq6
zlh^V<mRQq`h*!RlC})_kH~Utp;`Mjf2oWe6XhCuv?12<$FWPj)86Rl@m3tBp6>0@#
z0KF&BJmFNzK4j9DR_wMZkf7#7>)v`Df2pIRL<@mbY3AAI&s@VOLI!C=VFp@gCPPq9
z99IcCl5Z;V<X8sl1q;=btuUPmdDt=-z&oDk*6wj&1q0KPYq_bFi%T)zl$Rar8UhPG
z6R6Eu%vv-v;GedcW>?Andh9hQ<MLUR2mZV3*TRI5Sf<NAz`IsZ33bHB2odESyq%Q&
zqP&CgF?`XZ{EJHRv0R6p93<l4aJ*QA-bO@ouCf0leYp0JshvW8iR-5RC?nL(L%DRL
zfhlSabgsCL^%NG$Yf(Uvn;gFR!TY6+rVyGPA)^$oq6KmZ8lOPmE(*sSrv^daqYIh_
zT7_U(IU-1@A#WEBHj&?~tjAxAVhkk#0vJ3iVXM7TWNKH2IFPm09rnZq&QMST2S<*S
zX|d{LFWxp^P4<is|A@ORM9A<&d{mBkMp@Q$u6UOvT5FHdhFwL3n>iUq4!t3#;5r9c
zxy`9&6##UguA)8H6@F`W;nF3gJg4g$9K*9(3&9z8CwU%<h%`>@=k3vKqSBavX4cF?
zA^-t`jj-m#dnJF)E8-gT)0(hi5_Ojh0EGcZ#uWt>{+l_|1KYsK?=SUUj;gM<O~f45
zL-lGvL}o7;#Mm!kMXyAA1}{Ve+yq!$1rDmBTwHeJnd^9^;B06r(1;Z<B7Q?^;>S|F
zrx$*Y-O4f<R(}U%h=?3=Wm|+yZN)SUtjS58r1Nx8r+vE!rlE^?7#^IwKlju6+k;|@
z;q|D1wp<nerkB9$?KMxncuh5;t-!ZYA?<H+5mQa0Em<U2oeDHfT5l(z*(@mT+(pgB
z@*Fx6IoHxzYT-tDB_cv<v*uDAT4eM*t3vGUBK|TMGDHOhL!^vH0g7L|t26}>uiX4!
z9mJOdVyvNFbZC76A_5t(dnDB+5W9i%tdFw`j(tnYw^=Z@Su16lNiteBv>S&9>_$4e
zM@~t<4`oC;8a#K?15~hN5vRja^{RzyQiOzByKM#f{_Fn>FPwKp1_4%p3dSV7<$Ddx
zi|z`Qu9Z(fKKx;!g{LT^kZVA;2hq?2@o+%xQE{Iw88Mn5U_1nw#Z`!lMdZ58K6)n}
zf&+sfw}2-)VnlcGv06o4c7JxQ)OYq_!05V04qzx~omCALk7%U%7-Wz6cA$2volQeK
z-*QW+{fOVx=QT}5>RZ7M4}~J~W*!<p`CrbJ;~%tyZT55prc!DaRRJGrz4Hyg1io^F
z7;!M!Yb82Jhgk-MtF_;eQrZ2EsLTE=lYl7jy}re;D6fS4?315+JCfhIyXMT(3Ko_F
zk-I5rrRt$OF3%%j<P%r&;qJ^`AAU?jMhEP?BO`S{u+y(KYt~p7=*O8mDR6s(|NC&y
zZQWj8zKIt>g!O%QC60-24$8~*elH~=GL55o{PZmwjf?%(q+jhHD<7;Lj8D~#^S;!t
z*ZrlpXJO-^e;v5D$K|Tu%2u;1TW(}-@2-B}?|(LJW${C$eWj&R^}NAHrTt^sc@OJJ
zo$5heUDKOuI8iU7DIs;f^;;#U=f!~+mzS5q@~v*OVcbVs1T9M(w^%RVLR?xJekY#u
zqg&kGM&EHBuikRL^;E}kmi}eEzT|#ruE!hMvj%Cxen~$wM@p10=X}E=aGT}Q3Z+iK
z)bBf)<8TM(#n<O=KN7cI3fy|UT)pV^Z=IOzr9S<k)xLAf(LP?)Ip#iimlHply+6*J
ztY2->@iMIY4U?AZ)zxdFem#EQXmzf|**=Y<=Ak*~L*<rZmN;j|IkWWc>~ky|8P27-
zrK3;u!~W7FBQ0^w*}0{1uhh#3ZbpE`8=t01RN>urz<sre9NgA2QqGn#g{7LxvU89S
z&UIq`y}fj-+^o-S^4=+hbe*1!-j>SoqbBS%bhVlT`G$9XVth<i8>sq~a&vq0pE?oC
zz*o+4>^NEGTymCgM@o*ZS|c*Aw7i^EO3p+2pG~*Qos8&3&-C5KQoW)7U2!EliIy*x
zGSt86_VB9Q<8ObQp0Cs~sab41Mj^2OzXpRtty}9yT8Q@2rPeK<x>UO5zDwR+@u$6d
zcK3u7ziFQL{acpP@In~h-0I)gx?t+J-ugl-yY)ZwLr>(#?vAt7iFfP;UWLrbJn1mJ
zJ7rIa-|3wBP*CrG4j%GQz444`#m7Etj-5BzvDd@bL#QKhICr=7V<`>#{opqm4+V{K
zKRXqN$0jC>jvXB`P?N6xik;5?FTXwTp112hC`p|^QpdgzRsUy6lH+5AZ~unyiVxTH
zN=}nZK=IKfJ#?Y?1TX#jR&d1YJ=R)Ya2|<>k8ZvYR?eSXHrXA#Y^D>vA0t`*@n=kb
z>F#=V>s|3bZuR5aOPi-N|8diIdfCL>erfST;p3fK{;cI6ul=|=eT#XnzkE12cBtPo
zrRpuq!Cdv^Pnz@^XJ35O`<d3FyY%$aPo>qP3ysa2+Ob<Hp-fB5Pgf5+`>zRo=T!P>
z_jrS#FT2>k=fl^Y8hO<xoaW=6^O#h$clk&|Q9<k0)Ag77N6b>TTm}YD)q9OOlT}Q;
z9JLm|RISJTxlf;YCR)nomgf4YQ)yJ6_If|Q9E_^YvGVHX&2zn{{iUbFM_PxL`)8NS
zPDTquugq^xEiaXlxzMT1tu8z(O>FedSN@TEi`zWkI_>c)HZ%8V^`;kEbLlPbc`Yq3
z2S+{>eze}q%0t&Nx4O4_Pqc2z%#rHmLgSfqy-w#@mh{W@pY>nr|8_KYu;t%0Y1~ph
z((gUf@T)gL{uawgKP_iMrNbQ7llA|q>6Q1J3tk#FDy5789Q1lW;Vtd&pPh3y({k7=
z_k!}Vg*X4od8gGgW6!zO?F7wo4@~2wk;&XjWBIP9ho$4DS-$0FgZ=Q<BU-0>Ub#2d
zM=gR)Wb)B$E^w;xQl1a%bNe!4yK--IKFxZ83;3|K^{ig)#R1lkojsji%>2qjboBcm
zvoZ`1%{3d>Iwyzy|MSB)RwCn-m*`%P-J73n#k>k@v0V3C&MA_-kRjft(=0K#zDN6Z
z^IAX#-iBa<>OTsq?$Mips_N3=!@ZJ!F{|@>$=;!Tn@{)${q&}CkR0-texhMEPX~)&
z&hpY+dNvDAH?ro1#%5MBi>0Sc@4Wx*3wTNMfpMkbZr0yp-hTVZ_}I;*GYBV``*d)K
zL+9s`x!W%{9`g^%V9%yGiaS?trJD?C5V$>)E?)xxmYkdZ`^M`0(Pd|;KKEO<e>9!D
z&^hS$H|K_rWw*YXjpCm?8f~7wkfqQ156#_l=E7nl-S>Py%wFZri`nVSe0qOye|9)K
zn;w09c(#;Qm;Yzq>Hm7;;%}Ifjr5IQxc)sS!>U<z)7x)%<11OUW&WGSgW>-}+WW`H
zaa?zT-Hox-W@vl5Fq$oo@PWH)8pFZ>B!MB1nIONW8x5)nK@tFQ6GZWy0f@92#j!=&
zxl?laBwal<WDhwM0hmq@uP+&lAQ@6*i)0i>@y8ouKro`bR75h)hM&D8CTV%2-H$IJ
zY1vDAbC>%TD0{i<T>iNsIUEdTx~pEjdiCD-ed|?jFRzM8Dt3oo48;VO$I0%n$B{kj
znO61X@RGk4j>prucJ4~-{uHg7rO50}`sv~%mam87!*Po*Zb`=2;G!%0yD!k*SlnDA
zRF3(4aIv)T;Bsj?M$r5d+~38Q_^z*UKG>?y_>PouEKj(vB|QmQe`S?+uS8C~7NbIz
z{Uu@?JruV@)C#AQmmYtgwo0}24NCjEUnATY57&=TD3youp#CTmv84`zKopgpZ3AD!
zI+jqMI9Md2r()hQ&ZB+7oKM_Q;qcgT`hdbKH`uV>&0NC7n4ukJ;Zx-pM*#+A{VXC9
zo5Mgw$eV=r&G<1p^Q>1Xg~Sgvd4&5>f|+(779?L=(vU@wy0$v${cga@mUe{Cg$b56
zYP$Bj?puVmKOD1SO0xx+Q8D2fs^p#IY<Chng{q?qo+L0xQ0IJNnLz{Vnb7DqUps0<
zCUZoACTEy)z|C>f4$mjQKm6{Dlir5_&A~EG#(B^SUB-H>H}pw2#7uJ!VAiG0r+Hj4
zd~J?0%-^($s+IgObBa!o>gEn_r7;s7nD8JTgZ6j&%tCB#4`l?*G|pa+_BoNhsA)wf
zHkuB+2|lN$?eG6TI8(rpj%?s;O^F2{wDoBu%k@gE%sE~-Asq;{kk93`1*-X&YNqCl
z$53qa3V#MDvrmWKWu5{v$;ewKMAEA}AZbTf@Zr>Pkxfk7V>%jFF%J7a#+CfRNiDX0
z6V5^1#axL~nEwvGgmoO>^Ig&;LYq|6XCuF$I$;}W<4NB@g3v`X@Tj|HE|p}tm$V#*
zgm6UiGfrieM>9^AwM!&2BJ^Q8hREEgZuU`@PHrEWs8F~BRm;Rhc*U&58><|o=Y@t;
zm!(xSFiPROu?sYZ*<K092nuJ#*G8{7v4umWOIW5C<up)B7zy$)pO#z;4`}XTvq|MR
zcbBL6!ooPya_Enpz=9@mEJ)RSgS}5yplRxXo&xWj7Pwc5q4kKl42o>Y#<E*^$~PV4
z)MCIcGKRSoav9cGPiWF?H${`i_F$;h^&~Q3Iql^A1_sm7N-W~U$g)z=m2((uSc((>
zbdQW&W++~S=3>Q$zQPSEg?zVxB|i#QTu4WaP1I>b_d?uhz{2*dz;&S^AqoBdol{qZ
znKRFme)o9N_9ZUk(!*;>!Jtl5jNh+Dv^t6Fvb^CiTr7fPI4bn7d=`5%(~BV%6E%_&
zQk|Qe%T>y-;4qf9!0@D79;8mR{7f%xB;v)4VsRj<4{cl&80$T8dXWeM7cxD|rlk}5
zWHD_x+BhdNQr;YPp`)_Eth2!Llb9JSx$!sW@h*Cn5<autlx>W&{&y+C!qbJ8;ofs<
zxv`}lK@&n(bKEAGX1<-GHq!xiAsuB#%V8z4(0)5G0tan(HEorbv79Hijx_^!AQ9UC
zuP$NE;0KxZFY^Fx#v>A*ftiC5hI_hEwgsKpXsXt9G=lZgwdX_bpo0=K8Dd$*5>n*7
z)uL}!HfDhAH{5=1(8JsW43amC$|hjF`gaF3ZSH^)sHRnB-Dso4j;k7{t*SfN8`X0w
z;U<?g1;**H(Q7Vi)f8lm$C`tHAPKR(*-O+F#^XEbH(0HR=b7bi(yB(H6pcl-Ym;!K
z=a}3Yu1<|hU+WFl!o2HtFt>3jhH-M;{*GQJ1+S@1SkdBA_i5xB&+AcQogejkNFpz@
zU*OAZJ3G%tlgmYR+W&>Py3UESrS@>S|6P%@6xT1sD_%eUvVY+CVy#4vxZ%LmRzkY3
z$Neico;4!gUN|~PoxI07wzm%OD9`5OUP8|>QDX6S4rgf#UtGZCk~hEi8AKHR!`${Z
z?e@!IUQV|B9)A|(t12l?I)9L%y=^kt=X|aw@{%B)r+pc52;%lhZfB?!Q#s>!D~p)%
zSWE^c#ddMPA+WDEClfLmF828>yW-{Z`^4lHk=q+rd)rC2ym-P*+M`cD7FOqTyWWbw
zxwNm=J)7G%oL`xFevtG$#h&19e>(@iUiOsBi`Dv1l#0%E?&wV9&+z%UdYbimv%Q4W
z+2;g#<k#;>q|d}w->;d!qMo)hcb#8k%dDIDJj`BZ?y{AeV56<h+`Nwj!;7h$Gw(lP
zXrq8_mhU6NePYS-d2v6k(Imfp-XD!;L{Hozq^IRla@2K=aMbC*KWpW{=*&``C)dO!
z-VZ$I^S)o)cs@pQw-5VIw8#;shg^^2r(#?~MELhYJhPPWz7k1zu_KC?1RMpDdn!&^
zq`EXlet*xqw9#d@yxo17WWrm!clQOgDW@-Z*sGaaTqie?6b*S|`DK6EdZc&a=)>zn
z)ti2J3di}4rgArFt}p1@kE00PzMwHt|Cqo1zGp4zJn<hLvGPJ+>6nGf#w*Nw*#Fp@
z=_?EvdhUDi(Z1cZ@oRpGpzbT}!GGmXKgDkO9&IKLJ<(W6dQ(p)NBK=jKJRapH)yW*
z89#T8-#+|wA0zb%mcPmQ(eK4^9vhM!)@>axH(wY})|#IHoqdH3?P!Rx73&y1mZaa}
z^%Zt3UtdaYobH4F>~2SdDBS(K{K^?WGnu$seJ7_E4e_ww7pUGiqsw_z9uHHB^&Q;6
z2^_b4|A}l!TEQ_3eIzHuqulNLFpUAec9TC}bBe~P*?XRjW2bn%*E{1sXC2{3SAt`#
zUmxHuNCqq0`KH<{$x0F)&wc)AA1Fe*!{tsQN2Rze<rAr8?J9qZQ=>-XHm~8cD~T#r
znG{=t0^3lICFs&I>*+YZ!T>msZRfORz~tz1P`S0+&!^C)(Y?u4H*+~bKdRT<mworr
ziq#5+E+^;)!EX*xbGy6zVc|M{9W7iQIU&4FPaJVpSkb?=hSYiOEqp6=^Z<8Q?DXwE
zAr2<3;1u^;fq#s-xK%B@#Q<m|)6UlLD2!}Syv#i_r#~cF#V5#xCEGcjOaS#Y<BQ47
zBw<7TTZx$)4wII37_U~z(G`aBn@7!m=+^C(fH#BDl)HVO8UiSgx`FRI*cP?ID&G%B
z`+~~kQ7GkAnbIEi9caMl%d@+u61R6`D%lt+Yl`)KI9hq3cpWpTFF{U0y{+|AjLO2(
z@#uFcZQNd4b3p9#{oZ|XZHhT4>99b?fd*Y$dBsn;TX1J~L_CbUUFA<5&cactg#_Nj
zcw(<u0JWNylz09;oyel`bd3A>G}QlQKX4*{lJ%yp2Fn44L-WUzCd0Zwnr!G93$Bnx
zyU85WqGd~a>{(0nkd~E1q77xclq?0smeoz1rq#XB(_$xtcqKOBgvnEwV&lo^7Xo<#
zvh&_TD>uv0RPh$2H4_5F_t-ddPQ(V(iubUIM0|m1adXG?N|TMp+R>?2vvjzn=BxH~
zca!FGx2J^jU3{z=Aw!3X2HFWr1l`(^Q{$)Q4$>*)I%+w#Y}IltE9Y%$TCsMupBhI*
zlVQ?P1A1+pVQ9o*V>A;Q>97SIcKbdyn!%wR{P~p&>DwXJeFqA?5<Kx7ZUp<g7Q0R*
z7kl9=%+Q)UL>~ksTmW;;yjEPGB);(nF+2}Ad2r~k_8J&@5MC512ff5ImN~GqTC6^?
z(nH7;o|G6MbUi+5_AezzS5WpgZT#Ls;tV~5pU~EoxB9!l5v+aRhbpLv2a7h5)V_56
zPyM|~eDp;NzZvaYA5Tum<ski*OcmME1%S3jUGFu=SKMBs_SM+Akw8YvwVbj1EH##2
zS}}(n2LLVQSIvL;(mfL19h$6FgaNqs6_%3Ng>w99C0IBc<H;#@T}-SvRMs9NJm=+%
zXwldD677iisM$=m;6hI)g6B>rP{0kFiMi`;&qz#z?S<!pS^_)pC4U(LKC%8{z@QO9
z(O*H)OlqvgF|tWL^K5)2k54W7xrvn}XME-OVLXZE4%vh<)9}V~KdlLf6v+oI(`&d|
z!@9y;fSr}|Puo7-q}7NI<%xZ4uL(mjizr9yb<YvkcG}XRv}b`0%`VL`LVH+>xKpKZ
zl53G>jO}o@V}G)n96cG^Z5hQPRdjf=Oo-#qq<4`}w@2jR>XOD4CN02^@`AaVG|cEH
zVwe(c{_LOs*kRKq<|+kfwUcAed+$MHxQZ~*Q9cs9%W>G4o+=zas`W|_ydKw-0D%zC
zq%hRl&QaqcGt!H`jWA%$1l;PwiButJ#msOC4-r?4j8(~P9iu@>W#)ILz5i?Yes>!^
z;{6K#FFZxRw(D(g=dLRu7R&oHyRJ;#J~I2nj5z-35Ajwud*#>v@h`brPaplot;K8Y
z+fP4we^2q6cl+t#`+K&5*n0c0y2x!RKVE*>d%Sx5<i~qo_GYTbYrn;x!?&ltS7W%?
z=U@HBesz&y{HHF0@4RynG~}I&Yzyza*tzR=C_m1BaFs6}KwD}b>OF)1KmS+1*ne#D
z=dKLBeU9IKoi99!4o#`AKe*AD<#!q*Kfa<ab7J!LktbA_YN|`!e4{nj#O0xv&$UQ*
z;~)6)Mwh<ek6w>&q9=UW{rGq8jnm;!D22q~=Haqf7LJg9-;Aa$WkWx4ge#p|%6^y6
zc<6^4x)sH}CO}|BPziwFqnU6q*^*S(!@8e45Lfrc0vAK9?N~;rCb(9d3Bqxfj*W`Z
zW4NpbgYGID#&VaLGr^uj=4O(mSt|3D-&H=Ydib7tRuPa2H6qM7Ogs!YG+TMjFdVk7
z^yu!#0K-pX2orSmuJWxBteD#B|K9xVZ0dpK(TU}nPp|u51A-8m%S1wZ(q+^nNFR`C
z78KoCSN4qhAwU`=2Yhtah$}0?t_y1u0chcPY>g1vQ(BD5{t1@qw?f2d62~kij-T`_
zk?Kw=-0Hhd`TAi$C1`_9IgC5YMBAF9{br8Cd0TS&2&L(GksK|>1LWwZNUw3!y7Ym2
zSY<JkZ7Jw*_I^_=iC$)=b%oYTt(kHCX}Mh2Mb2z`kb;QZu(&MdV&ckZDKkKci`2JE
zw<JxTm#Hk%w*-)Z4Q!T9YCzFysXh;ZRP15&#0L^UgM@qGtU$1nB`W|V;=HjylcW|e
z<w&o2RR1r38~rNE-8|>Ht}7x#Xn-ZPY~miIn0>o9I~5a-{y3{l^5Y<c6`0RF10P8U
zgXs|^<Tec%>5|uXAS1v?#hjx8QS6xL&=4>8n&?n69mg&oh}|ghf#pTq;<`f|>ZD`B
z%!@G=x}W`1Ol4P6#L=4eypArp7*Eb>3t*MViu4HAM~o^0M4I+Zz!xOYG+Q;qK`a;U
zGFAZq%aXuG*t!$5gVe}7`|{Pdi60qToGj4NS?Oxa2*ZK(M~;q&h?q44aUAUYE4|RU
z8$a=9ilYduK<x1;5Nv2=w4q&s2?U0kg9eF$iW(UP<`0lD*oL-g<QN&?O^8XOS=X>9
zT7fM*oEt-VOn@+*;!cN0!LHJ&)6mmplEy7J!hH#yXTY{@u~5^pgrm5tJ<07$NHzgJ
zg-UaU>S%NLis^W0$^gSR2ROufRUrR~k7d`&w8})wV;b!p3?k3$A(<62Rh{6j^pE6c
z^Y<OK=mL3`b^MalS9xBiuCP0texdghzCbIR5MBdee!sz(uf6e|ciS$o8fseb_6~??
zCyR4;PAANnl=USd#52!i8?X|3Oh@O5h(R?)0bAt*9d+wVG|kQQBq!BtaeMLkrx;_e
zk%VN|sUz5N;@7XmOWta7jGP)}AdnF9!i@Mm)>xzYOKisN_tp^OXJ?;p9AdLeh<uMd
z#`CD+j#A~r$1GNN78vb6%QaGzXIPTg2U^9Nc=v~X67U#9K<pb8Q-L!Y$tE3Hk_=N5
zkfIwv#6p>pCkeqSW2QH+sz{GPww`7q0v<N)K@1dx3bYF+)9aD*E}&+0xQGR_`v8j^
z2O1C=kpc5$8=B)&dgJx~s`<EPl&ajL#Z;@#Cxi<?R^WQt2-KY!Ve5b-a0XNuPuAZ}
zyA$oO=}H9kEP2W@7Utq%T_QhW5Z`T>ZbO#fanpW4L)7mvwlDc{M;|6_#dMLQgN*l#
z8pi}QhVWipi#8GM=$VYMcH>V*Y=e+AP2Fc|)mV2y-e+l&0=yx0n9LBkClCV2ge${X
ziDN(%yh-f1U7ExH70z_@$aWm-P0w)C1lb~Yayh+_(*g-jj_5HcDQjAvLtUvw|K2rd
zJr-!dtutT5MOgvRexw8aaG*hu4sRH+kGL6rhna#a>*_B|bb$$@aHXi*@eEt_Yc0QG
zR1%jlqd<*m7Ns;;0$WeVXig!~Ir6%Z;ozF5kdz}a#>K%+|N6k4aj-1|cffA}FzRl<
zfiB!xCOA+V{3>l!QZ|~2rGsMZT^NtNE(SJ`9J|8>wnN~E0I`KSxR903Ba5j^s(18%
zc>TRvL`G9-1{g@aduL$*euUQ=N3Yc9G&)CV1!vt5ur|<WvtT@+7)&}TK!}{B7kG(0
zV=zn&S%G}yw9uTaiJ1%RN>@*qy*j|5C!f0)y;6<U7-bA^>-fG4pdIhv2}>eYPjrik
zv<pikBLG)bCw7ojRf47s54-CC)-B}VxDNO(lE$Xys#)XWS1j)vFe11eiwLZRrhVmW
zpcqIA-9%5y5Y{+D7F!dNOYB8M9Aii~Qo0^tFf<4b__3zh*BK@`Y&zglqkhtt8c=hn
zBY?U}iFTtU7!Q0cf`*|dm;_36?Bj3WtFD7pWR>CPjYluU;YRbg6vdR)w0>P;=HbF{
z1#!nL%w8n**}Q{14sANPBJe2L%_|{v<|GYa0+**zlh{v;9)>RxC(ZP6<{|>e+JxJF
zrT89TqyRwCDm25@7{(BSB}PU4gdf$qvLW4meU+epYET{KPmwS}!!giQ1Hm9gXoaQF
zRs1MR9Le`P%D^-`Mo*1j{sP{>Z`Dm~-3I>0wF(-fB!DaOekDN1j&%)_7XFa|h}?mg
zNWWfH($Qou7C~qzzP)jiNUeElu(?u7C<)Ut+duYhbvZN_4~8Mf$2abX$)aB2f!mKW
zK%Hop5wVWKrhb>D8YzvHoT6Us$eLASHSGOntRso%BNeIjU_OEQucQwVRnSz`C_}q3
z^IhB?J82qg#Z}gS76YQW{Z)fw2c>48Wd&9O1g@3PX|N6Tv~Ls)$OSfNOdocb!%mZ!
zUFJ6_>z~OF@GUNYGuA=Mb#|SBHi*NP^{r)5opl<WZ;4VFHK*q%VfyzwHQy9-bgBL+
zBmh^b;4bI=@V!9XV!inV#(LwJOfg8~LkrLjq>h)m88iwLhH}U0bx1r2qFEuCt!~AC
zqwG_>!u(Axua_9~NmNWVH7AO$i&bPWSFXo;Z+wfeRo)-R_mupeSvXW~(`_7H<Mjpp
z%wYMLQ)oFfcZjah{uvSWoc9Y;@v<xE2{ys&r|I=2e+{~+w6mA#Zh<Y7Sg*l2Op|SV
z<&Q90!c)5KK)NJ~f#or+hK|T*4MgvVU+}j$8{=azK#T#5CeB#w=)9;e^CEm?&Mp>~
zcMj=&K3q5s7hkAYMew0(!dh|hvSwg2z}8WJTe&*HNMVuo#Q0SRw1JA~nuE*$acn~Y
zi|H6QILe5Azx(z3HvtO(mbKsQJP*K;P>W@99mO-uV{&1VA~2^9(%Sdga`AF9ar6}b
zhGXGy0@`n#DNQES0Upsg$a<Cr5%*tQaojWP=M#;*QMXzx6yni)&y+i&GjxrdBG?r%
z5e)q??ferznCG(C+I>8CMDji#A1ktNOImx&e{qMxI=V@IIXDsDqB(^9i0B_<eb%<}
zJj-569!;7%sLzM~&aq;4NRsRR3qTa0ae!Nz4}9gT9l)Rl-Thxw-@_s`<d;}ZAa~YH
zBDQ3qGlU>+Z|yiD#Hq4R0CSL2Y%)ooA>S@@JnQI&LPe5h9sxF_HgR;DYfr44;={x!
zAOJU{d?Z*t_%jr#25OF`5cLb}J6hS7^MG1p5BVFoZ;x?|0j=n>gk(<cQGgnj28hD3
zu)aBfUldhsnWgp7mw)`-T63@#E&zr(MOt}9mji4NI}-_-dI~LtckMdGLzH_hplvPd
zMAgSL@QNHh)69=2jy-X-7^9^xpy$rjcrtMux$Hw^e0i&1!Jbl}Aqt!;8tIi;G)8LO
zBz-x#E<Dm=ZqJ!gM`Z!$GGjzkBXRIG^YM!zA9@?Lm^S)m@yBcvKo#(BS1E`K><aq<
z0A4e_29F9-g>G0TKriQF(uNYTTId@m;$h!_5Zy>`mVh}D;7l#{B+U_+DJZ!RPOfu`
zhYoZYCM*p_J0fIQ1g?d&S_<DVifG7=A;X;(KsZPQ*h<Gbinet)kzqp~OTpj&1#BP~
zoM|u(Dp;JGpk^}s<8*wb7bA-Xx|otKDu=@IYU(3OFPk{&T#pXY9E^ukH(bQH4+KNM
z!&iMUm}}QrtVZ)VU5X%9+|Gq39=nq(+6jmkO{oxdWn1T0F+sW3i|`eWw-VOdzt#fh
zv125AJvIhN(P&y))6u|kY$6CcgYi^Uh$4eDG&iSLAabYAg0*+m47Kq#nmZj=h;Kd+
z_}gfd!7$+)8u$`5ps8?VN`CKhX`G=9b}c+pdKB&G-Oy~!Hga%U#ufWpLwS*nv3vVV
zA4Cgs-&g`{eufW2B|D45q%{a_P|_?g_zx7YWfc<H044h;m{TEV2*&FSdB$?xJ^*bR
zuyHuRM}+nyHJ#irLH9RA0ALd{sYgizmky*xj+1AB`PCkK0jYzP+9r~nb;DY?sfoNQ
zVEdZM0mG{HDfk@3PQ2Km;lDhxA#a|!r<-a+6TD}EZ7WxB`+Q}|V%ks#Mn#JNP~pQw
z0FwnY>FDr4(KzDn?CVqwR+F|DFy<5nY3b5=6Zj!4Th4&)yB8BAQ~>Y3weuuYlM+J!
zV0vr?>4f9C<BhxmKe6)pK%kl>O%*#0^D{BjI@0@QZJ0Z4D{hUo)DN-BkG|dizaqF0
zI*>qH&*ZRf!#P3P6PQ#M8V?^%Ot8rFTZD|4D29q=>EbM{19J7g+R)?@1Z-v(;fPB7
z&GcDW9H2WR=6pq!Rlt@u?cj_@vOuePUa!nEtnZ)>Qus(?6bpmaz%0<%2QH^nA`<S2
zUJ(YC?B0|HJdLx8QK4uQ#alg9#4Pwl#jx8l(zT*zVg)eJ(K5S8qyf)H^ro^V7)ZzE
zD4P``^3MBy!vao+Sy&Mrc%Jj&QG7IEa5$yLv>Puybk)23Gk@e=Zyf}l_Of?~{rblL
zpD6u@AL44?`<+>=P(Q@g{_VLI$!<Vd#}o)ve%k}4<=y_m1~_-Z`~Gvo|K@IBZTW6U
z4B*w&Z6Isc#H}KrwPPfEyLbm%`@X`$?!M0L=k5S>KfuIJ{<rHq2P_QO*v54(|N1|k
z<7f!~7cn{jed;=U0Q9|st^E+_Q<wP>pbwB55H<;f?H!!YAHDUR`!uZ(A7X3n7RK>6
zkN5!=3cGROCl__CLN`?~B3Ro6d^Y%80|=N9D{!nEcFTd>;RX5?3H=g?-LwkAY^a+9
z6~l<L`fQ%}BwmYbWvtJ^Rd^vTVK!+6IMfK09=<ome|Wfe{@ZwF>KUF$C4<1?uJ_-0
zsosM@Ru9;Bm`wb5*XKUIUr!Kzc5{R?bwiPV9N%m>-W8q)F{ex={3!&4Zsb@`5vXB?
z+5iE!(dXNgBg&@luFVSg#V%Y#F2_nGxR$JUi2#5S-Xh&~-UTrnk&%=25qQk8@+z65
zFTzwqH7ka&nZb&1WL&LZ7_1^<$6(rl_uu+Izo2>OC1@iWW(OMV=-~$V0)O34bm3qL
zu)sCZjx!*BW1BLS18Bv(Vics$yS*LN1xim9@v(Vcy-D~8TS6qP+cSa!6>vaQz$hwo
zD8zOq7`aGPJ*HzG^&2z>VHhH1?Ca0G&(?v#_$Eq|f@`An&Y~S&xtRCs*g`Wasz%L#
z#i;674?xv15T}7*;!!h;_*`?w&=;Z=Oy-nq6{*;hp;kGt1Y`)YP$B7nR2n*N4!{R@
z3shJGzn8&NmyDKtr~8e$j3&k$l7c2xC&G09%votW9(BE)l&Rxf3^J1F;5J3Wp;_0{
zTqk>Uku^!s(3Q}}z<RBuST1(*Ms=-RlX@MsH#!r~6nqYx*s@SjrDk6aotc<2a5xe}
zd%xp>H7@{;2reRo-I0^>KeTeM7T}l$C9yKE1?~b(r{-J{crZc_<Mkdd<px?bgS!X9
zYm%au66uo}%!j}vlEd1^dKw%5))7yFRh&*d%n-wijJYzMUc;5+$33Ps2udT+oNFZ{
z8ASapr|DEhtZTM_R1<xG+B1^>!{2vkK_SWK1*VyI7TCiet(>HE-J>3@2a8m8yB-<w
zGiHGgQYJku8l<I2c%P(FClaT^BKoLg%xO=u>WnCHQQ!+*Maa}6tL3Uy=HLMsveeD7
zhns-kg>7PFY}jOVV9X#5AkJ65c+|!MS}+Bbq+n9JO{rf`ef`yxMpwBEq$svAc<Vuh
zJHihe{+nwvLRJ}TcZt$3VLs99PZ8|1D3@`*YA7F~k!8XVVyDqgJ`CDVHEyHMKy6Y6
ze5?b&t`k5y^EpEM5%lL}8}ZFdO!l1SGY&t(J_|4^8%kI!CbwJ60-ZBQwSL#Jl4nQ}
zrC6PL>boF&&e5s|ivx`6G>y-OKl{Wz(PgO%F^<zek*|>(fXQdMrx0JVu4O@+p;{W7
zL#Wu}1zZo9%*q*9lVK*j%t=U$jR`%_&^iQl>QoTQ;JHCA96vS&xyN$Gk|qQ|kw{{|
z>TE{TaYHOTqB;|6K!kD&+zCH0iy4C{&jOfCYI~-p4g0A|iatrPOi|A!NEw;10w|n9
z<%oI(i?@{qusZb_7bsPwOw%Eo<e?2+26922LJE@;F0T%jQreVaTENI^**G|=!%W~2
z4c|WgXSM<VTm$eX2l}Z};TVhXfsGczWOtBS@Kp+pt?Qm*>A*u!Oh$dfo+_{axPnR`
zVjaaMB5aORo2gwgw*wXgKpuh`1(pE19-swo*fWmMFk^1~^dMIA6!!N816>Vc4!arB
z8P`MoW=?Ptv9Cy!n#73Uo3IL5wV%WDDx0BfAZw~Yf}f$D>jvnvhzJ}VopXH7IuvFs
zSp+XoL+>jlmU{>e)<zS5_g}y+mcxVndr0734q2?%*+i(-PEvs-roaz!IqPfFp0)~O
z#VXi6pH6u~!4jy$p=kOZOtOM0BG?i2HcDtXV}o2lbTE`!IWh$PF;VqsnU*8RQMx7>
znZ`xPk<9D|zJBkVn>B^>;Mp43(;r}21TJ4u7mtkT_8vW*LZYvV8Ly)}LxLwQ5UN&=
zM>Q5rh7t{sbsgmu@PZ@zh?_&*(3FNA#qfpL#=v5f+FWb;;>LHTAS(PtL6s2dggAti
zG8ppGssg_%Db%sWzMN29LR7Hp=RjL&p;w30acPNVm0{fgBM@3mfS=)AMy0J9I31U(
z5U_-#fvRzULPGl|ZopW<L};GWq&LS=%}qn2q!L%4L8iDOHtOKv>LMs?v?)lthPq0C
z%c}>|l$GyFDHs>uBb2LetKT(n6Ll#rsQ@MVrP6!G)-siphu>l4gUXFrG*J7i3Eout
z0bF(+&%n0O3+%rDN+&R((I^NI7s6+_-GO;AkDkG8!E%f|5K%dCtd|f%+RP>}R!9q0
zuB@dXBNxWS?GS)Q_sm0RkWV%hvG^>lxI*9KpzoNRI#jjp0PMrwk<Ar}>p;91h6vIz
zrlFE(FNRGmoocBq0p!7sIMOf#<VwNh*6Oj5PSkSy-P?_HDjGJisY|dx39%6aTOD(B
z%vpln_9;*8_yW6JEA8>h8F11u0=T2Z75ScdJnxyrYail-5z=g+@D+CnE#Npm#51J?
zVvQaGKSbJaV_=c4u~9WD^Ttc>qkLFrrKklOY<jc(cpSk|4*=5+bZM~6IBGbtkb*#G
zaG;ziMj&x1)0@#H$ku~xP;aQdV>kvlCI=`#mI=Zs-a|%>VdjJ9iK#OUqcevA`1;EG
z_V|0{5sx%J)h|ZQyB7}eAPmYo8<#>OctAWz>f|J^&Q@3Xo^OZ}t#*d4P76D`UOVJc
znB(jLj}-RGU|p>w68l&x*ioOM*zJd+VJMi7TI2zys(>m>Sp~XU9HgXrkOpNJ);RkL
z^;cA$Xh)f{Mtm*S;Xz@^F9YYsO5BO1RbWFaw&=ub<)U@IET^h}Nx$2>#s1I!AjPGQ
z43CuE;6dlLgY->*u<NyU=C#fYs-`Yv&hF?J7sD8<&XTi@2K9sP`3z1&&PpA}BYY6V
zJ&Hz;O@y?zPP^UX8TlmNNsstJ<$!-t5}Z2YOomkulF@#a4pUe?7z_*kWkVPD^{VrH
z8!a(bErGB945<T~8ZP5JMFYP1Otso_M1whcy{*o9Z+I(CF3#t#iP>u7kGc5nAAa~o
z=A?%U9PvC}m<qk}uBmW11^{=`WjH_Yq+3K9eGeiY3X)y6YjbhN8!^?VhkSgRLfGCk
zHoq@p0Uz4~q#@kHCZ!12dK)_*A@hxYn(zQH;V;m>=wOD1_;?p8QNT)Gk5P_vHm>XC
zT_yvbqVBSBD|{HSByNx(yn!FJ4HW2?XKvm1lNW=Db&#Z9?;2TlYF8Q)0ZM62ygm|$
z$qOT?6H5oj%svkrQ%9CN-@qXsV=q|vWa?P{5zkBIE?t-a3+2iM9pt5nkq7)tcX{N4
z!4S~7S0(Del7F3?`<4$PQ{78e*y~;A`b+!~Z(^ODh;Mdvjkr7bL%1s`PShXpyRL~2
z#&ExopJ6T_uF{FbTZxBo3!nnn;&H1CN?<dOGa#Cs$97oLimjxA^ds^Vd0X+I20mLm
zFE65vATsIb5$IFycmD2wyXv8hlPKQ<uFU4#H9@9=+(zH(-UkD~L+iGJ2LkqLTPt>W
zO)EPU6v<R$1kMTeEMl+l$Z|>6{?P?YbneS;i?u~C^a)f_;X@O_h<m7v54f}OxxGQD
z1gwdO8gF%KYzVjuS3_4=?tHa<2cANS0@zd3sz*1lHkAcDwdk5q4F(LWA$1CBp|`@e
zf$W$1$gkbVWIVKF9h4t5zM1z%Qnm1ciymTN#?L?C4}Dv8J9jDcQbXU)WJXdKF&s>u
z!&`|yl4?w>H}ehaZ5LpY+~y7`I0!A@8}M9bisvxA@^XUbWhZBhK;jbbLpwlDN?MBC
z$=O4h8jv?&Ko^l^+km$^Plyg%b*%;H2bVj90+IyeJd@xH_(gPG2$6c@Z{O9OIlRo^
zV$@L33=~%%mEpv&fvVlAH&X#bg<d}Z|DHj}cm@AG7y;UVlvT5o4bf<Trw_8BKcsq-
zK}+2Dx~KEH>ZWRSG9s&w;tALj68I+|L!JY@j&lf-V<>@#?LfPa#7Bf}pq)V6BG}6u
zY;5rx>cv42{jt)6ebQpNnaq<r-kS}U+0RfJ5tPTt{Y5f?a~4dmc!o}_1D6^(;DfP>
z=;J|aWOMFx29VezfTj&J9(B;pZ3gg!ZlWC*nidMK1UXCfZ#?9H`%=dc)J-N>O6&<>
ztpHh@gJ~1D0O)gu;t9s_O!+!4rvSwKv67YpYR_`&X!{~N3(dgpVGOCl`c9R<A@nD1
z{ZlKQS!TITY{?F(dq`EBgrtL@cwJc7H$Dza0zt5$>z-;*cP7xfyWY`iT=jyMg9Mf=
z$h{IQTZ*VQ!j18O;Rs?ITup!vbUa}&jOZ4_z(EHD$`zv12-}n>XW&p05FfiC<8nn^
z3nk8!r;WS%#qWLs9Qs`-79(RI?noL=oo_PjAy+L^pz|RnREs^FrdlX{6ep~No3(R6
z3I&ZYTCE);DL&Kzgwksc4iQihB_HZEIbcW*;;NOj2J2{_rivTEje$>Y8)yZH_E?RY
z&`QY_%zJFdaT?D4)+0YAHC{^r7=Y`P;SDI0*5?<osE<KTSW@9hp_Lj&*f9c61L6gU
zwheM8&hTz^s{S48RDdW6nmdYKxHOo<&|q?(VucoPTeb=*sFit0SKtCrF(6^-SJ*vp
zOUBSo4nUpS^6k$~Rj6D;(QkK+t_Q`L*u#b{D@<uyF=0m#_?>TX1iEU0w@C=!ZZCp^
zROO_PqD@k?8y=+rD_wvGfq<c?N6+9+h`*F}^d818LS~F5%vZ+?rJusl!Acm|<jgk^
zJPLlz1-KSA-~^8CA72mOcX%^b&KA5&F(NuP7M9+_dcbM+3a-($84)m+8%~4B1Ah+d
z#<YNBq*gf(UlehNdP1<Nr9(g(pzERG>YFGbfTd3PIMEu_$^|o1#!G$9SA#vKE`r-C
z_^>kbA<*v>TkUT8-8;m&A5z}_zln42fP3FpEIdV=`~G2Et8h2_ZiDa!P_FkKaPQL!
zm3!&XmjO2Z5Zn9yKg++n>oRxI?>5@<Lu_v=BH{l5Al$gv4@rDKdJ#pwQ@H1e$?t8n
z<$t6CzJm}J??MQFGdCSVBknvng&T;70?A|q4)8_cgG+FI+(HWa4WAzGsClJTQd+R_
z6*WIL-bGY_S85CpBW)nd>NlB3&TfQu>NR}njsO1TC${lxXw45F9IwJ3ys`aP@69C#
z-7rYt%E-#*EDp;7(ndH`7IEN19Kf0<CDO{fQyvTCNO(S@;dn_jZ_ION1pIBhtb4$1
zNZD??sI3f77X*g7<LHbARI58n;9|_gsF$RdvDZeXli?LdVmH^4gIu%49p*s!1{9uN
zhrii)hS)p36ZdVR17N!{e{(uTh7GULLdFk4cn}me!-?_$Y@<Q&1;>;?A`6I&2aivA
z;?^QW+a#-9Y4ahzM@MK5GHNBoY#};Sfj<ZUfr$wyLyuq}H8Qjlo+3<MXacRnsDxi{
znD&GS5Mu+Ot87N09krvK6Gjotl5H6&gJC^~z%hlehCm!}^*s;qHrF99Y)r>?{I9xj
zPc_+e>ak^3y+ug0p=T*KBsQw*bGTS8hTn(4J+8*HF;x<ab%LdjrOm2BgoV=vmvM@G
z<zKxgn*!4g@$bm_^12p`A#yG4(Rm;c*)9UE0p>h|ctfrt8Vo9M^%pa*!QLt$1tCFU
z5s>B>G2#9$W%v0&rXY319=1`E50X57^toT=BV1>;(cYFRTB)j0jS&-SavN5%RpkGD
z@aO=O3SClp>iwH5nSFvmWhvk_uZ&WAuoJ)(Uqd971$UILX4(jafSX{0E_!d#Fg1{=
z>u{0-ld4c$ikV>)%K;d`2Hff;>FV}imn73MtLu4TNyI4YT?_~&k*km#qV+*qeO#!U
zm7@jVvGpZ~RRI8a+QYnZ`&)myn(<a?j`?F<>zr1C^_^bX^XjwSRk7xZ>{FRCLe}Fu
zM-Bjf!fEsXa{x`A%%oA^WJ-F{drhY(<>Y0<WS%}C+F5CRawk-MY-XwL1#r9d@h}^v
zfVaq9rq@$;34g{JK3Q%!{+qr4s8v0fNoM_3On8x716hX7l||7?W@07_NLCe)okc9N
zkg1dpRBk`}o7h=>E%s1EDI75+U`??Ow<_)4<e6y{X&pO==8DGSBB+<TP#`S($xONH
zh}R$~VGp{9+-5vE4$zSNJLjz9o$Pwhsas__h7idqWtxu1QQc_sgT(cK8Uw(W+kDjj
zjPjo8fS#u-+oPyW)g5#^Jm!L%*FaqA{HGcL(-(g3)fjN0EY8!yfm&7Z$ymdbIdc0r
zSc+UlG%~Wz1Dy=vhbZh5Q-Y!_2M`Yu&>#yQIuL*eiZXJ(i>%vL&~=i^%E>NK#N^hQ
zXJg5n!EQpLl?g&^ACxmu)Y-IWEAFj;S*x>7Gfp3f1-t_a?2t&Jpoyn&<s0r!042~Q
zwSI%~-UY>hg?tDT@B&tI2i7P6dea6VT~}p1u&PD^q#^^@3-;_+P<+?7fgSKD;BX-#
zoz&!B2uaI9mnZ;nNwr}|0NW_SGb!UHQ6>RiJFpThIZr;{5k&a1L{7(xpp-zT089WW
zi8_NIwT`~0R4iYCjRX)l4AWu*5`pp>D884nb=VESo34T`h+Kvpj)cwtP|8rDHKW)r
zkA(L^<RuDCQc$A&+0VSEf^JCM4j+MWP-qT%ta;fKs*QMf4HpImQNuDqf<Q=QdiPkc
zf}hNUu}3#!;ZGZ@=%9<$#G!nyB<(8LcCdquPLoD)+;V`0lu@2Qm&)6ans)VL9YKsW
zDF7~vwFkx%PEQ(h7*L&JSZ7jzXw(2Gf-3@|uZ13mN)i@{4o_V5y)tk%X6<uOsM28`
zIGcHE->hgDE(1(r=VATedmu4@i)c3CYxuE}=vwB+pZ@}q17-uJ9q%Ym1xOZL(J+u&
zP;tFfa52;c0jicRXC!)$g$eD$%*5w;6`53gBnwlFwqZ?3bO$X2!h@fx&<<fG0`?vO
z3#<U>pj4FbPiYr`DE`v@@5RcjngkXeOuL6wVl|V+uwfi<Wr#SN!g2zvwwzHZ51_O`
z$rjAdoCNo1h5-d1fIY{!*&R3=o~w<kO@c&9gmvF!AnhS5eI6oH53E0{JbgR39|Ia_
zT3dMm5pY1j1Q<ok185DjSwTpcZW)d4!Q$shRj?6*H|&QgR&@k&(^zGt#;_8AujMcB
z^;1ClVA`>a0XbAq8y?X3IgV}CYH&aDQFH?WhwkDZmv}3{$Dk*ek<fnJkw92AAc#R3
z_a#9^>H-E^DIk8i3a%bH1WQEestYSmHg1OtpzW)mEi)i&iRv-hq&-px6_MHC<w6#Y
zhVh5~Dt8C!Q!zd48;1~K|0HGt?vFjO;d%xkHtq`3Y@*nP$y{59Lm>pymMiCXx?q+#
za3a8<Gqi}c(MJw_LO0Yyh!1?_-WV4jGqlP94?4^OES446Jf%XZ$ij5N$}Z4FeCh}^
zMa>!vT7<M*IkTD(at{+{VaTVkHWh&tsc-|EfO7^g83SX&D>MO^gaH#GayrlokopDY
zn3nnJ6_iv81KfMV?}G>erG?}*sF3P5q~IaTHUq1XKA#y6)f>!f2*X2~zYMOnp^YS-
zVS{ix&kKkTF0=Ve<va!vLj#V2UWJB4Iy4D(4U%T)!z#V8{qLtySMa#&wTJyKsHjTk
z48RXVMlgFo;4eMvARC(*!|KefK<e2tXv-2Sb?UVVtZS%pLD~<93s%Uja#y4DQ@dV9
zMcTTv!{vKAwmhEwawfLQ*p#rP1;>U0P9u%KXx*ah1Qx#iU&6Ob&oa?b;4LB>3>$ro
zQZ<hRY=J*s709^4qd^uN1X2m`Kl11lePrPtFPMWCf7FL1Q<E9^;u>dXEt>L>LaffH
zgv?oIJ|oXsPXT2eGs!?#yFN%!2{qf*@8I`U$H9;8g!)+d0nxbTi$8=FDty+>PRS!I
z$X?*pPtiT_EqA>o*nAl|N%^=_oo#O|54S+8f<K`HRl_PM6_m)aC)lGL8<jEjSanCa
z>4@qeKjutBIe=8p#8v0kZ#=Pz<b|J+D(r-^aVCY$z?6DGh(JMgbw^*tb>RWtfdx0P
z!MmRBe69=iMi1ib2DM`+1IY18XdQ;A6yzv+e}Mf>9pJ@-nW^F!-k9nKWAF}6*mMfi
zEbjsk(#<yrgEbRz%|=U9Ymn%|wzBli^+Q0SU<+>HwC$339VMIV)=#^cV}orRSnzF1
zUX@;N&qTw^%_OyC#X5)63xSfDC&YZl!wRAu5r6p`ZqQa$-!HBlL<z9IiN?eQ?3YdS
zBzLJXalXhd0fPjK>~v-#z|P-uj|D^D01<v<p9RmS<tU7=c!qo}nOL`PF6Me(VJoHM
zbfo_bH<}EbHxuw)Loc1EK3Zp4Z0kdS{wN15So(SOI(P81Q_0v$UZGSurk^S+5bopm
zLF}i>oeJv%Ttnd9cmRjG+(#47Bed=1CM3`aYi|Ros;lB=7xl)IJrh9$%nwM*1rGp{
z34kXVNxgxrWe#xWx#SF09k@Yp)S#Cu@z=Y1mIqM+EdV^S+{cE1RYln6J@GA!%NtA9
zfACvq)49VftFi*pq`+odjD~`;03iWY!%sw!^9aDUjmB5=zy^=N+7xe<pQ-E(u2vtF
z0nmdGvD110j$sIp4{WP3*YOmrqnKG;wao<Z&v-KCq0HiD3K=|!a+@RAVu;}Y8VW3N
zd4t6@(Kz=a0~Q=WqK9yXl0A7L05*n0KCpF>L8=MpQUH^(Q%9SFjfro81gYOZ0^cm2
z;fnXB+325a?l_^)HAi8#3{hCQuCNoJD906y`1>!s2jzvs%3Ey(8>0w5ZA{4Es+b4^
zPzHkla3&fKT=53&3L-B^)!u4*06i6Gcy2Rjdh#HuMK9yrEkIW_$p4M@#05|jJ#g=c
ziA|z2d_&&XkmEN_fE)+Oj{v1cSi^SEbMHk7S4B76z_8F_g%hJ2SRnv>fj`#Jo1_7F
zrwotnQ#5m<`r))XD<xnkv?ulT0FIYL&T6>?5*XwwZ41B_5L@sO(RZ{FV-4vli6W6X
zfiJb`xiR-NFh25nX5>YdJCo5thdiCJQUxH)%T_mddakf2z{*;}6vTItqbW#kfYCYB
z0WKRL-X;S=S6nNrU8F2W04zG_0|Oe41R@k1M*K>mpZdx7D2;wJz^ZS<_CcE^>o{i)
zF>5ohS&fcBm#{>gGqrQD{y>lum1zLJhE^+SPD2A}Hy~%|sFfQ3D3ljKlcPJ}(?v*N
zY{DmV4Ew`}bj-RK*&NjrtJ(<-k-(%h#rkY@LS>PtZ-TA@VycNT|IB-HI%bdpuyFGn
zM1mQC5&8{R0j9v<hpHY>R5%Yf>@ar?Xgy?jULoA5ij9?SWb+)n5@brP5b?kY)~RC*
zWeJ%^a~^!jK8BK_M#Z?up=nMXa)UxdG1?Lv+R(640YG$0D;0+od$476ngT#mG}R5^
z{?@CT*ERL~i{Pm$es4Ik1jcf(r`0(g{L=CcaxUXqz`bzlLv(4~O3`y&__vv88Q{WR
z)52#gI3Ym$nhcRak*JU*2G|H^8RfvRF0UT84YWaliM9?XQfX@_6nxmU=6oQRkk*)@
z`H5y{Ry7ms#}nJ%i!g2gtC0t8^m;Up@ymd`J%$B`cv~@5MlgLYBHU2r;87-9JBQNO
zFizt#!-eNTI46Cgc|hzuigYmCdggiBKExs;dd1K{+;ib}ZIzLZ#vu%rU;s27K%9;T
zS}*}}xC|dFH!F^VLX<UGxnc2zGSV>L7Sjn<tVs8?ihyTCv5y(fOIyMjhMuULI}kp+
zst5$xwzaq$2|18IW#nP8%XUd%7*}K6D`x>MN`b`m;;affjvwaGN2BPO9I+P%&kzxo
zf*0kSKP@zN5y&KxUg|0Hfq#2%_G>@$vUfecLo=L>H+J#<GrM;;wz^{X?w8M<;Xi`e
zZEV2(7ce{Ehbwmje}9F&zjs~a&KBVR2K+tu--D3y&K6(*ejC6a2#>vL*X>J(6yx!q
z0U<Zw&>!7N`~wj3)BnOw;_pB0{|Lcw@{ese*#X>RM3Qh81Lde=xPp}OlhjL9MHB-$
zg967I_&h2F4kr={i-FWJqzDK$KBm5R=OF+A<0I-y2$*mFA3wG6HvHuPp|*OBiE#Jh
zod9LSp}+h6jTYe=xYpf||M^OE03k~y97};M(xpl;SFVJ*Y|L{4bpgo@E;nug`qyG6
zXdu~)@Tu)pOhjz~!r-bG9%$F~G5tXYl?5}oNtwnP&JA+aF{axHCd#XTS#;7+AQ@O$
zFglSBE=>#Rd)_W1pdy78r=d?*?FG=i5U^0$n2FOjzxkj&E2c4#+VIrD(o$z-p#}`x
z?-=or)`t2cyg|rAMsNx@((D&9>2Mv8Wm}WL@VXj$UBvj~p)#cm%8)L6FNBU-sYyKS
zK|wmamf~qlFGvw?!c445U>BH3k%254xG$*6rTzH*Kui<^Akf+X36U1Yl4Lujt_a?%
ziL6N73eIN`*#(h<5D1b5GlGCm2AT*>4I70_e@7ve27m)hk%>dpjddZwP(s*h$9bo^
z<bZ#J*jnJYDWLgvlE6C#>zPSJBxo3FU3s@p{~X3Tj!dm+-Wl^d`f&F+-u?QWp;lU`
z{%F&I<|~c#fp%a$LS*cu(mH}*|8IJ1QGHZYFUKRP`=q}6t>L$v*+GU{qcQo<@4tD}
zi!*#=D(r2qcl#H~$;E8A&W8t`ZK%|==pASNsMBU&+xp6bl03rOY}M=ei6j$#B(BN!
zn`HNS@3_RCg5rYJ-N1H&Kl!xZ&(<<>_a**f%$}a`(_dR-Pa%Q7J8aW2u7BQZ^m?-7
z-k02_PZd%>?zzoOVU2&X@t=bFY<U}_-uAXTMK2!CG``^<5EtY1lfaby^YU|oyzz_o
zO3nJ>XD77}B+g}iKqjmA^<NM4N2oARoB_S~rA%YKK`u_7OtPDgIgN$;a*KXYSp1(v
zfl2PaJ~ZrJ1D25bmGE#V7IxR<B?MDfh&&+1N_2R^`k4lDF`d?V_Axs4?o2;R;mW?*
zyHnQ0!eknGn2WjfMY7FJ?-kqROG4`J*WC}FUtYEP*}H!D(RtpRLQk#v(ZBB18@{t9
zw~Ob<8y|S@-Glf4>-CMFpKw<}MH`z3>gq|&Ti1rMqxb>AM#?zCg^qwz8CeI~?I64E
zk|RE;r2;P)0JwmoIKr3v^#Ht7IB{}%?KNPBt8ResvNMH+CBWMh#Xhr1?4{f%sbLGC
z0+{6K6;hx(ixgB@Y-mD)%`Bk{MPaDe5mQn7(4QEd4d7BELK}%aqn28S-(ma6xQ*$B
z6evU^hIA3r3ojCmPCX#)^MF7+2IB3L^pkuU+#bRR3`?Se017B;#Q|iFw5zYkQe@ia
z;uxv;X4ZTlF3uATjRm9!gSv{+lpSC^v(s$Ji#}O;Zx70EgNgylnyBo|tYa$hv-9pq
zaxfFZ!yp&sZ2NeourqVq-E)v<!tT8xCOq&_8i@7m$ucleWUFBrqeJ{;e{hy{v`-;^
z-W3Lul2-m27RmvZE^H4w;is_B!ahC3d3ICfGb#!98r%rM=&)XfJ*#&B6>yL%XaXEP
zOYQIc*T?L~{p=<IiiFe<*T1&VwMPewbxhxLDV%Vz#Gkc*>P9+7ZFt5T$Cfuhd5c}`
z9x1RQE7W(`GEeviGw0!ZXUzt}={E4!5zuNb%UQ2J$h|TDfU^gAiR=K7l2ZA?j0Z%3
zgRzNizq;4ZkGrr%TB8F<BJ3YP6?U2$(I0ZJTyETSLGvp1I32QZ`w!lV4AFx_=2I0D
zyxJ6eu*iayqniTFX29Zk9w<iD8rwYGR-j`6u48)HiEvc5mS5Y6>@XN`88h$b%UXmP
zn$o0J9ahK}z{)a`Jp(|8stR?9uyaU@5G25f3Ufx9-+J}WAYMIK9|@7<k=`&s5wNv9
zfJ{2@#$hY9QGE|3mNkeRK2duF35=a|1h9=(2S6$UEvj}V#AObe42rDXfio%@F@q*3
zI=DA{vpaLpfjMvJHYjJZkczOAB(`4JwFw3ohS|fGavht1BWnusOQ-N5=r2+N`#kg)
zJ3rkB8624Kf|=$d<={KY_+p{~I|jl}A}<AS69!)8varIS<0eRoxFtvgz`ZGNQ<c%x
zZu~A{j=&YzhO`{?<94pN_NwFBdf`ofMp4hVJVRyx-Id&n@j@4}29bA#bvWSZ_n^Wu
z^-9<T>h*f5wj&GY$u@G4c_`^jn6aJd0Cof4ZF6c*#4sB~9B~5It6Q?_r=&KG&_w}M
z0NOBxJg(cm(I4xMcA&3Q8$M6L?ge<3!h$!jQ+PsifbNn2TU@B?ry_ykFq?s1XG|8P
zL2erX8jFk(!JZt<b0fV8Xe%%=!f>l?)Pe1gpYt__gH4dmhqr@&3TFmA50Z?q4Oaqz
zI(g&evsn8G=j(vKOxwdu=X2PL9rTka<o!9{Gn?0-An^<mQ-#ev$wGF94zOOxb5gQj
zTFcp!YtLI<JByVRc6+C^${`*b)p@d?fM{m~1b8FSz>6j4GY*;ud>I)u0PJW5#@%tX
z9O_y?H5I=9TfeHKEP>GE0HbqRCxA;9ISaH1n`lT|cLJxdSGws;Y>fLD;Q_X1!u6OS
z&v;Wl?`^v_IqG=vWXy+W;=I9}Uj}&(2}rNnf%$0UC*wSsjB!#YpImeD&P*FEPzJJM
z<goo;A<TG0v5p*W-T27=ZR>kHpX=#OBix&6rFUkqQDNRC<NixbcX{Q!E9^rkAK<#M
zd5VDxZhS;i8ZbiZll1KjL-goEt0Tv7vIK>txF}^R$P{M~Z)Dxcn55UaKw$}_Yc>)j
zM8aKyY%oHCF}H%P=LWs;g};LXl%9;WG?GKQ<MgBmLJG8t_X>-oW|+g66Q~L12{MyS
zECW(Tsz5_&b;<15iw802*gdF;p0x~2{mZ083n^`e_9UnqngY`UMD{s^PT20E!83-D
zQpj@!n|R;;#RK-5I}Jq6<WCZ*j&?=*kk(^xyAkGV<DsnwNJqrl9&9y-i4M6@?Z9R5
zeU?tK0)qjn`1FaG0a(XOWP1c@K(D+sSZ~19?N4E*LG1Wz!`$FW>xV1KcbVYO-ulXE
z+hoWFk`%gU>!LIQ#wNG{s5=P|c^c{WCwZze<&LeDkm18-Fmsx1%QUPo?r?fQCe2jV
zIQ;N6o?b^W+Z3|rI&gc>aA6^)+;JEM%hk1ZfGuHY0E#dugZGS{@95QwaE-0RyY$oV
zW-w(2TmZ-ycF!1KN5CrCGt08lA*n*6%?OOrD$+985VV+4+v*>5Rx{Wv&XiVoCEH6q
z$^DcEscP%AVaTy1vdV)2&^k|Lh_43RQKN^C!@)+mmpkE$N<9d);>Js_+KW41`$IY#
zZ)I@ap1(YbwJDs4U-K5T{A|nloX?JDy4h=b?YC*~e9qh2HGIgODsIby4f>5krLNJP
zthR4>*U4;Qkvwl1Tj_Q%QHRBRxp<n*)0wf(Qg`l5{~*~)AD>`FG2tKaUNrJ-c6PXw
zL#5fRWX~sZXSgTN?rc07R@>R?q+9R&+Gt15pOfzXhe$Sl+=~o2{n4zb6JY2e&~<ES
zC(#<&mFOsPbDFX<{Mr%{2D90h{^%Z7ycGULI0!oR<>C(7lOg|p)OvVl_b-$E;n)H1
zNd9&5Ks@|-HSe6x`N_4J*xJdq`=`4P@ls}sQy`fG&d4j>rJvg3ea_qB)E{MMKe6j6
zw@lyMM)%L=-(Z88E%_t)eK&G$)p-0bMy)HeJ9d6PlRs44Sp->ljgi;d^dn1!!okcH
z|1>>Aug_Zlm}TU3a=}?3pD$E9KSLkLZ_8vy>7RAgcThDkfrvNsIm*l6KGZD+Uk-sU
z*3|I2SX0H%t8e#bo8k^%wx{KQFuNbXb!~4!;oQH%5Ns>P?2LH!w>O^G@Z3I!4RYDN
zg$<7F{+LaMBk|+afBq{!z`Q@W4d{G!?{n{bXEw&ifqPH=bGNzkozCnBx1HiM-u`$E
z45i2itS%koIPd1tqFq4EAIH<bA!Jz*YW4fw54>^j_&RXWk)LBu6}#g1DH`AYkIbSJ
zB|rC@?#WW^&=|O+eV;htOnmE?+0Z8%kG;^>da~<--#SHaX2|{*0j*7bYvj3n@p8jk
zV8{8t{-nE?;JY6T`gR=8J+MCVGW#pV0CjIJ(%P5U3p-w2`sSCJ@yN`?Zs#~X_t?HX
z_R_xIHB<aHFMs;i3vXK37~gmVSaUadKyh+Qze?%P1-VZoQ!B-z-|p%j$+p-d&cuJr
zPbP1)k-}C~LjGw!Yt{Yp*rcuqxn{58*P;gCtMzBGseZ?aC2V@P+Qj9xw}d|Vvwwci
zc)*X9fOnTzr3<Jg3chV@y8YJv!UT@U35cvc;TOTFT-oj$I8~>)<D(P1i?=}BT$=bW
z0KCcb`v5m94(hpobPKsp;7Gei{CINZTzAWQJ@@PZf9M-C8y}pV*`GQh*7x57fpoEF
zu#bMXb42Xh|3wht@Ktv_dG>?5a}&!~)n@paiG9wo{1~2VPjvzA96{5@6R-}y#MIVg
zAf8Llf>*hspw@4rlIW&mgWY7A)n1```0DFgfa;3;-2cMnP!{bukd439lLffWTA;3;
zM_t6JeILh7YLCT?cV}w9$LJ%T75i6SL_x$B1CaTta_!;lbukgRcWAoh6OJ|M6ZH6n
zK30Md`q+(3c7OI3FFyh)<ROi7UCRL9CsszjNPv?5EjvS;2}Rt!wlooJL*HsIFx0#3
zG4VYGkD?-C01R1CfOVB$*r1%&9y<!~a7lMS!ln*#);){>9rpj~poU_56Bisc$vm}Z
z``iZ$&iI@AQ|VwCc=E(P=t!yGdV!UXS?9osodmi044;Jugma*P+){Utp8FW<{RUD7
zMeN-l!>ttzO&__Y-T(s0PgMQA`?PaiC8TmXr#_5hwa#S?1(!nC|9&RtO|m?A-<fYx
z10-;a$}3$u$C*38l@$v87W#{w^@<A(T~m1k5>F(KQ&jaWWYrUI|M4@nwakt=-8caY
zvt(stfvAS>&l=t%vu8>>D281rr#lRMjktYmyrHVpy8D+|{Z=NsugNN{!4qQAJw<dm
z@-orSq1-A`85qb;Y^~?WCd9o)1!W-sxW<N?UnmRkOwWx$ZvwmHn_cW|?%5X@l06tV
z%$gYso7*1*)~^ylNCYUlE|{=ag|4NQ7T}FO<W>6^nB6y8*8vst#!X6kjH*x15DY=>
zu@5`i7R)kj7!v*JSPKK;ZK~{DX?A`TTgx{H;83QqGo^_Hd)_^Bn<`)Mpd$Vvz2c_X
zb!VdJkVn9b&XJJBM$ZBW!H6|Sut^_FvI6z7JKcKIb*^Hk?EnR(8N-G+4+U$Ph8_FF
zxC$V@#h}_i&-?LmM_mv9>FB*V5By@(^DyeZ|3#uNyN&=E8YKl}la1rdr8UHhmA(5o
z4*EMo{T#v8x7Ogf$3C1FUbwtN9pQ)V{_wcm9?Z7RZj`GqTsPku9O+h9B(djX54$^(
zBH{tRVvM-$9NbwCMIcaV006g=>Ho{#`#{HWU1y$Eg*J`QOwwI!_f|Rxr|b1Yv(Nx3
zqKR-ij5p~j6vzeyN&v*s;%GcEx(O<bEN>`U$tc-u+^@Qt1jMFA!i-nz@yP&CQ=uJs
zB5`ORZ#KIDK+vWpj4d)sqRq@sNLqG0i8GcsoUAfCC*I!!DaZ08vzeUiIeX4-*#d#?
z`t$15tM~5x?svZn5!b(sg{A{N5}nkN{y{Gbw~?~zN*VY4-uEI3073aiWY+pqNzyu~
z@GT<q@*Rw(>}2G5_Kx<VP)bw~eN!XpNIP$7pu~{~z$7-$EePW?vEYfJjEefnZX8at
z7jx)iB8gV16ZajTJa6Py+lD-B1K_*bH$pC>vVq<MqGwTM*c)80cUPuFuD0Y7Ldh-s
ze5EQ&TE{O4i5G>y;K>9j{G=PlHT5{DqteS>i&LBM{vf?+g@*71ptwh{8DQt|>p=vX
ze!o~rcc3d7BnY)lKYu8a>HfjkcU=|s6<oi~P#f>AgjSI}P;cJfB2=6sHJSLK^!nYb
z*_Xgfdu7atxS`5)k*^!Ke}8sn-Vn+KU7to`=HQ;P-Fmfv7(wgoqargsM%ec=$AJgP
zOYz59XPc7+uQ*wiSe3nMxcft-VLkgOFJv)iedhQgnI)S==KXl$rdE!bU^#WF&3x)L
z$r;s8$-3%YkRtQiV{@XeZh|xSTA;6xeqz^31LM!oDKm-+2G=wtoaGe2HFt4z(_aVe
z|M@$GIsX#c#~^s^Z4pc4H+lQxZ}RV56-$1pM{i4N{wM05|BsyHcWD7i27kkr+zSt&
z?YW^dswv9fA!G1PVE;cH55|razb67LGD1w>jqNXCbgHZ11nUp)enxs8)!Fo?-`<(;
zS_yU6QpT>P|9KKPI}uI^4*qX`Qy+bI<7>UK%Xe+x#&o~)b3W8GPPTi;ZG8FVD+zK6
zU_;u8*1F@rJb5JaXD5#5Cadb|8r;qgq0I7BdA%od#jaQ-;N6?2#7On2^lR0vcW|X&
z4QlEY&n71uZsjE$Ht4;3UXA^d<MvwXho7?lSWU5ixj1q}oCs9g?Ci{*Dm82VB?jsG
zeeNw)D#fn2Z`FP+O4$qP?ZR(PRd>mibXyF1ec<L-Jjk-HW#>y}{1>zDV@_}NDKR%F
z?B4Fh^bg$r)BgjKtexna4BP|G4zf2}2_FZ)opPKbfgwYc{Df?~sk0^A+xYTYTCK;!
zOCWu|>t(`&YZ=e2ulmDvcQ^{3O~(y?O*rFQ6HT)f&Y7o+IL`C`j`WH!4lh~4d)f69
z`<0SO%Y(Zz6M#Mn)E%jVq_qB8+;o*?XP^apYR&d?%KXFQTSiUQ#JyYvLu~qXX!Uk`
zc|Q?1&8tK-y4$IPaeM24-Lc)u5z+9c;aYEbr3xC?wnnXy&GUjYI%4!p`ct-jR>sdg
zVeggatbv7rk-4q0@2u^t*dFD!>E+i%O@Un$7sOF}POYYw`rM$WTa21H%533`E8znC
zQ8~csGyAN*;8~IC1D9^hMqmDl8G4x~J?VC}L~z#j?N8NkbtqXPXI6&+3zZt^dfBi3
zMmi7+Jpi)J)N9p;Afv?<YN0q@+b<9OmOGFC;5p)wdBAf=&6S>pKTGw!guz_sn#xnY
zO}agNC<^92*R@DEsGU0N73S8ejQ?2lsU<&m87{4py9RN()Mt{kxor1JaVwJ68z1;(
zM(u>Bz@I}E`n3_~lLMSlGtUGt31q%Z7z+E5>h@+Ov0kxy!|LYMctxt5xr-Lsf)wNA
z9huD$t+Jd<c*LJqrdlVm0&|LS+gK>$*aI9ova(s=;Yy>4QktK$Zb%otXt5SBcb|3K
zz!N|Ico&jR1*m2_#X>sV@4{W4_h;AQVQbu;tF7iJS<*gZhrU1VuSq6g<?k4%=qk@a
zwtH1h#Ml>QuRQNULW-hbIxcL=B(}-kEy<_6aJ?r~!)NSq()^t*P0LqBx3)~W`P>@V
zWzMZNZO~?jR~NG3S?R@ck8sa=cy0D2Q`pG)e0`bNEWk)H6_v_6t7DP4{Q#wB#JGFG
ziHMNB9;wxyc>D=xRuvA)aEDXoJ@*UU<CaabE02D(3yPDmYBZm44z13s$?C53Df=p5
z@)OR-`DQ2VL>}Y`e|7XB*2y(*c%e8y86``lLQl_HW?<DR?4>snUgITu%`Smq1KQ^f
z)ktd<TaSqOgxCBy=YnKh4umLz6t`XXf5-v?ll+}`qajhsE|eM<Jat=KOj=N^dyLBG
zk<HfSzn6UDQyTz=a?S0-mBgyi@Vj@VPm_k=dy`ccW-rsB{i3JTlHD+8qFKYB>n+y?
zeHKvDapuj8sJW$fq_%=VHN@7rh%kh=QjJ*vbEbDxYOP!W3PY-LRdbO~J4YY+-bP@9
zU&FIBj0rgc!*h!f#&)bS3l3-vY<vcBX#9|q>oR<e5Ty}YFe(Y0Z%UtuMm=bl;lP?V
z0?Zn^Gr~^BAeVZL&`Jt!E4BveMDMJo)oZ;V0%bWjWS2CI(bU4UY~)jdZoB=P|L2S^
z$4zhC^!-YL`-Fc9i*jH!4TxprzyZfKC<QlZVvVKR*wLetER?Zsh#X{Nuo%?~<--;L
zsEUrrA?Z!73g{K<5I08pw&rst0*FE&S`?(Ng5ku(IN$iit&L;Crog!08+5-2)EKrA
zd3F8XC+*E}gx7n6;-E0xCC}L|UMX4?4=az*=}P8?xE2emZN01(B*E^c9p40*BevR5
z!!R-Icv48m9#G7lE4D8UM|x_7DIU<#Ge+yT$V*D4KR@s;L$&SprkpkVa(pJ-_qlW|
z3s(58(eKMK$vdl+&9Tf_pjeggEaNR_ipl^{QXpw>URj7!ggPFiz_Ai!a7$~PDI<~d
zpDnK1!^7QWxgr=gPRnX2RAd;l#tHghzyi&xSZYPYx$tQ-7q5;5#-7A3S+T0GcyUyy
zk&)LWA<_G9{ov2hoq1&m=n_Elp`y%cWeZ{tb|xfJ%ag7=!fXQ3b%j(7OEtJYz&eTC
zXr#=p`p)R};6mEo93l|oYy8-ok9-l3zamdNxnYpY<|d=xPKu%Gyf2x#MokTNzl6Si
zU?&f<Zy7u~_(xxq6M^G{a2n&kQ$=Os>q>Mr+^FUsB@5d)Jp|`<zhXKBU<^Yb5fu~8
zpJlx={S~jF!O`SedQa6s5yBXEOH%E3_eVxfOhsrnSg%AMBf>&vgph5sv7DZXA1zmN
z`@Ge3*o=eogw{q^SqxyfEL822fM@p6X{$QF?!56Yf7Gx;L(C?LDWZbI1QHX{+9r)k
z`;3HgPFSXLR)5Cb?~;u*IV{X%;v8%ln8$R&gg`hbIaNPx*A!10iu;OaOo>7m1k-`r
zLC!Hh=u{g)V&7b=6EqUyMu?Z^IrH0NlYn3P0WZc(%0|{3PyK$QCP0i;NJ$tgj+>^t
zNYipb5R~cnT4;<1S71{ke8QN7s$NMLJJWa;tO<>vxDmv-nl^HSwji+rX%h=KZ9(d{
z3w57eX*xk@!bT-BtJrp4GL9oc9HnqTltQTFcmB~oJzdDzpHHKql(c>-h)m*uYtFbZ
zLk0XzLM2g-eZseo_(<1ygXP953$c2Ehp5o)or&1#X)`wL6~OQg&@mhayeE1Nn#B=i
z5N^<-19gb3Jk<cS7Wg?uSd9zu(rx<I`>4<8e9%@X;@0_^4tLwZRnJ(V7%&Tr6&i(f
z$yvn$4aZAh=f=vA7AX;iKvdaFj^Q%B-y5GgasbwGSZ2o6?%SNTVz1b$s1(nJgxTDx
zGiDl%V{%TVhW5oHQ1;5LL{r`J?QS^mr|s&@svr1oJp2*EkFh_!hDA5v0bhdpRE9@i
z>DVJ=A!Lq3Sa7j5>-mb)`Z=aPIQ(jrbR&@>si()0WDs$0&jhA|o;1R}vqqt{<9D|b
ztAfz3<jILRpn}^>n4C)#(g|q23H4&toT58nQ}kJ?s($)g57hnbwanL67ka{T@i8&?
zJH=}QgYP?SUwtzxp9yZ>s!@Ee9_{QYyia)N&N?sGf<G1OSN*el=C6CJL;KbG_T^JD
zTap>)N%>lJ)t*1&jjxqYrS0Mq^78|$a(q>yP$iw!=9!+$xBRs|530I4AofQ)_O!1B
zx6{SK7mCDi{q6pCmDxP7bxzeHf?a#c#pdqvrTi15WwrCEw?r13_0m}LYtifRl6+9b
zyAOuj{Rc8l|C7_(21*CK-vYgU5VSb9cRGdmy>C_1+oPY|Gw{>m=5WXTiGizk9xTh}
z*9mR6{eM-pKOqXQjqNT!xIEbNE49_$SF81#SA!>qy7$EY4&|xdC!L}40dL*&Px#vg
ze(J+R!BcYXcjC27^4apd8gx#jbG2sc$#k)H>3(;#9&M95)Bc`#_xnx_eKC)0Nb?Zk
z<;VSe$&P<g>|Z`nZyvMXAE{RCKke5QD1T{wa=Dbh4T1a_w^ZKYlz!FDmTZ-^zpjS7
zd0CH(wG+SQpY=}oZJJVj#(&+vb^NAZ8mhD}IP%tUw-$fM+cvHWv(4ewSK^!g^6&%i
zYu_3Cxf}lUqfBsL^hb{0!;|lU*V>;3y&ly+kMMK9TGG7ho{vI6^AA6*DQgF%CTdTH
zS{!17+<id9+n0g5HT{r3&~&(>e`<C&2chb~K?MXQt{jd&T)ulDwL@^w25<Y^)A};!
zG(4`p8leL*xlEe&pflQ$pncUbeaL7hoteJ!Q_p8WKJQ)Ve!c&Eho7szT^-X``q0=I
zm->OT;n=Yw-+Lf4^1kRq^YX#j{N&tkZ#$g1KKIa{{$%~W)ERH&3o`Hjd`Omle_cax
zACgDs9(lU>={!jC6)>ccsj%;Mxja(6NWrP8bpXxh27mV#3kU7_sjG)S4#sn7<4~}*
zf4wideHX}10l%%gdp}Gqa9!8t@+0;9OWyStChPsciIX4t$$Ia#x#1Gv(>{$yXU}~?
z0Af!q_b=~Va7N(PK9`cB^%joe^M_imePb}#3rzl}`vKlh4vzfCec@h?`QrM6!9s9C
zjr_Am_ul?w_SfRq_kB9`jQ{2X<NdRx2mLpLef^J~a%cw<7QcMvXgX7Zx4fQ<rozLU
z_D(+TLS6+GjZ);^1GWEbA#vHM2gTv^zy$~1>g#~F4^>CdM?H|9?cXXu_bSuh7=d>U
zGF`m2H2I~Gj`;GDR*gljA#=_;xf>jGy$Gs&uz+OesZ6iMoyx<Ry3zppO*pB5?xgWg
zcFtW7qMK@RoB}yn{}bXxXEMywvsWJoe*TbZJ-g3^n|-MB4`NuvYtG2UM~_d=J=2Lh
z;(&8se6fDE{Kmcq`e$1J!Nm)Yyk}r?wpfDyJ?l2Pv-B}<`URd)YWf>H3)x`$ssM<R
zKLx&c4)NC8>1|)7bJ_2CSoH``?DWuZ$btg5XAKEvESy#3IY4;7bU-8B*>m0CquUOD
zU-lReauM({aZ+6Vi2$JufZF90Fe?n<91l45vJag<M~yb;G8b4%N#0Tr(S7~(iK~>+
zIz_&~zJ74}k?EiW82qG6@Z|^h0r|dJ9qTJ_kp~`lO#Jh7>T|*G&As_UJqN-!vT@~D
zB-Xt3MGCz?9KJHgYBxCtmtvyrLsx12nUF=x6~*A-1E8X_gi;u)2g95d(yM9E!TW?Q
ze1;|>E$8!u5byx?&&hFD7~D%5c5e?zt?XT}d5tJEWh0R6!64s@wC&wpp~wRYax16o
z5A7R!b#7`lf6@M`M)jA|POInnACAKVGP|1XjW)@?i*+&8d9V}5=vv$-JMx4&kUsdv
zp1D_Mb-3e%I+Y&D9P_H^r!wGL({)6H>GLRX{#CdvlxCrC;Qjt(Ee4V32OB5a;+}$4
zz7cvzq8=jqqRH_Bfdxf4$*b4`MT;v$3%cMuUt6D~&Q)}o^Y7Mo1)MFZg%um8vZ`Mo
zu1u&xOJTt1R{jMMoKGRx+CA2Jh$p1uTIYv5!=!TDFJ_b^m^&5|5IHvf!oJdjwVR=g
z-bAcJ-ubW2=Ta9%@KoA?eBc(lE<YT)afr^uy6?qQFG^a);SfC$2Fo+7vkVlON25hn
z$g;>yw#iN!UKWP8cdcgx?A_mVwETG|6%#Ib-JMahy>>wN<exy!gX|jOGFn}BDdiR;
zmloT^a`In`tOtU}rsgKX{xlH_N~jTNNvZII!dVHbUi@OP>1f!Qg&z9M0n=X;O;hr?
zVYk09n@?5Wl6b)_((QB@pk;R#1EBxx@Ig^rKzGFCy}gWV8o;+1gX9l7{>IB8i6dkQ
zGj&|A!V9ns3g$Gi2o+4#iAbDx`>fbo)VjZPI<mfbXc0V<;JP>)RCJN5VDIog6sJdS
z1;QLjRHnoSg9-1xPTCrI<kn->0o!+Ps8lEX(f_*gehGnmWLcE4K`Kr7PepPyp514(
zHqR)eX$4e##wZaRbJ5;N0GTTFS#o5-M!S`eO#P6Rx&D|F1;i`G>pt=$DG=@%HL(YF
zdv8gg?SQ67F+#q<kgn5_i=uU13<ZvQAOK|U{n)X}MJW;^XE#p9ZJj#aFO9<s0K0O`
zQn}ZUyereQ=|uDXlurjUhU4BPmxTxd`{{j*Q>}_IUY02ABy?~!x?c4+K|W2R@G?Es
zcgblvAIBQ|DS}Uj>w)u1-ASDAzZ!{Px(bu5igGa~WN#tmjGuE=>op;O^(npMEN{*H
zLDh+d14l58I%{4hxopc_XqNAL?!EK=9|s~;eU+kWotCp~x2{(mam;x*?%T92+p+{g
z)3^Wq&Po-Qu#z_-pz?C5b#RDb@TvgG1}k^$Sx?xX0jY99%ik|5PdN!3lY}QKY8a3T
z_B<M#8rYr#3U5U4WiT$;BaHH0z0JG{WX>*i#mD1w7R6>b%{0zkqa)j?x%g1@O1dK}
zaVKM+t_wT7A0Kx71?hyNiK73>kRp)2KX&_nj{k}pRvRK3Z*#`qu0Hiw3s*omFWxO-
zCI9mz_`4;nzI~Ga+Y(lVx4vBm>$_X>SBqcVtAq8n=I?hG)B5g{{M9XaCsO_vNcru(
z4;wxRc$feP;WteoQ@DZ}p~me}vAPSGvrj_B6ETDwc4Z&9J_oDpY=C-zCvN;=CFgut
zJa<nKZ{)wS=f+O={p9!PUA|+}{?bOCCjSEKutA(jRB&E4w*LfC5BWHUKd83`|Gx2|
z^&3I=XtX;Gbfzlfzu<*)lX35Vlw?R%9gy+%;L!Sb-JMsvWek-@`kD2iOtsttOul+<
zwz*%OAVL;q-XF|&&HL#ASFL)K9fGnK4c}Vx6Dy?|cjPJ0PX9sV9vgbAN2tsd012S;
z1;;6G7hZ42hR1r+U2h7MPr+zQy>rWQR~0=V>k>HSz9Z@Z2Lv;FJ#MDTRe>8Z-A-Li
zJG;_Oe(H#G(%pLd$$!+aM#u#pwjfwO9>mV<%8(Ja(J%MML9$bcQP&RFot-_Io-593
zD^Uxd@q;Zy!9Z!8qh5SQJJn9%)qzx5-tVpsqq%Vu5!lt%kk>o|!KPgcO66VPdp?Re
z8roJPSJJ{h?JX_(UZ5WlWg_2nWV6@u+DmS6y{um7imRfs4yNW59N~9=>0E`$K6M8%
zSH~IB1b4G}W`LZ!?(kCcr8KOZr8cj88?CuY;&eK+-;hq`>yasXtBF&Y*1A_2Paqat
z#%<0+$@IG7(9Kwd1=-7sy_Qv(M8@jOm!wCPqR3w65fl)p%@2B`etgEZn|Zt1T`t8L
zd6qz?3Ua~w(z%3RLR#)>WKy~$SY65<zukA-aM6Wqu6oJt7F@&X`+CSz20Vu{tFbf$
z?WJ;Dkg1C2A6avatNv!8{OkfrY1No9V;>>iz<ChoTkIF$N!3}^>nRsEzp><kamTLC
z*&_R=yXadp6kA)chi#DpAX3$QJy720O&_QZbTbkl0=asKpwh7)dbh_K=MI~UUP!(n
zXj{!+Apk1(i#T`5lev0xydGTg*P*52xJt;Tqvo!3^9ecSg^g6%h9cW7yyVb8b3JV%
z*%>_{$k8_PE;t#Sz6Odeew?ywN~pxlgLZtH$L8fN<O#cV%^GA2QD-gtBt>}EsIXk1
z$DsP-hrgfF%k}2GyLGl{yb^1LJm+c;5$U1RLyfNlgG0}`I%U@pCx#0Wp6X7=1KJp#
z^1fk;@Km}p{E~CMI`vqA?2`C1>E<<7AK8wsMRxi>dIz`r<FLRi0#<v%XT^Z&*z=~e
z)x6a-+h$Fca|(W5dBDo6U~_Y@c%oh^Sf$x{|MSj}Sam4ZcOe~3Mny~mh+baSYDR%|
z#I}Rt>qoZikUM0iPFixf#W(uS44g`by@~mkLSfDyTAF{!yLo(7qP8JS4ExN-)8*Xm
z_wA3w%k`)k+)@ieR|nIl(xtZlR92oD8d$R1FUd3M9bWMzr!+9T(|JX5QDXxVI3-_R
zlj|?LXAWlUwu*KSl_}-;LBw@ZkEy16$@vra)bgIlK5MH*SLCse^9ynXK5ae_TM5Qx
zWa=u6<_YP2$ZH-OT98FI61C`!`8`GjN-t9;q%M#m!`)TR#42hc6(Y^XDuw8bMu|wj
zHGXCQh!LKrU64!k-XWLw)sN$_&kUWyoYjXedPA8MZ`oBQmQx73rJ7O6>3A7>qe-Kv
z_F}h5_^Y{Lqf7ZmoglGp7&BteYy^?;wD-nu&nEY+Lokf}N@CU-sfJ%*ZU7~ZSCQe-
zb27R72g+gc@yKXLW(J)b)oCSwt(fIYUWh^45a{9@mCkszdtFt^jzjjPwZbq2UhlS@
zQtVX<kwy4)r8*HHZA10}(>G=gFr->YgKHb#iV_2n6+!~ktBMh?KOh^X%++ECB7##u
z{44}LilqQzt5kzTC5C9uN`QbViaW6dW!dtbm(7)fpsw?Xq{J*FL=lqW3F^Y5-oV5V
zvKJx()Wl*)XT=)WJF%xq9qy@T70ny}ofTH(<e2MkWI}`$Yx^q79+?DYR+wmGOcDbX
z2vSrD1N$-Wc_qOk2k4)!dIdUF8m{AuxD7cN_;$0#tm)r|AO`CgM}e$>ypaLK{-poa
z09wE*C<~`t*!-e{g+u61#0_<4eyMS*s!$Q?>3%UICX2KH(9=$?i)3&xny5Mlgw`xq
zZq5wDVc`a(UDjPXqf6z2@YUG#eN<;lBzF*kAU$cog>5V>oj?JNqS0j(Hhap**P;fK
zzeR!o`RktUttULIVfwL)sixj|LUBK~lm*B61l0rsXHOxsC2X3ZkhbS~zAM-hdT=J8
zS1!XRoO9MAkt`Flj-}Q_BUKel-*KO{J!tp@X@(JTrUkLvqzaxhZ^e{b%&iga0MS(H
zbb41B&Md#%?k=K1rVPUjL$Vsi<_Et19$T<BG=h*RV9|x~92>Fj1h*orSI`34;(K{p
zc5yCa#`Tl-79tk@glEhIL|DMd;qZ=J@sKly{#$D@Eh}(uZ>bSzrJAXThw2D^G+a<+
z&+h4VmZXylBBY^qJ+;fb@A`WfZV-Zb7gT5yi41(tGIphR+9+{z6r%f}oWsfzwwHv=
z5eJfYkD_L0(+t}<_OV`xeHsX87{*RAY6^rp4C6GVj&fG)A}7T&K>FP3O&E+B;9>&_
zlh`*pxuCn5xbNR?8Mi9cO$~d_ibKcs9d~vnV6fSqN^TxCE8!-W){mQl>yU{+PC~3q
zkMWaJF3MKcs2Nt`l+Db5nZ~^`STMQ>E$P?}zX|gFJmL=2yf?hi*3~%nb*q1T2oZ3j
z6<Im-_lQBwJ?9#>7v?NpR~<-U`C^2nA$-r9I=IW}nr1E_*rMOlWIJHD9L|(7Y$Q%t
znyiX&tpbYqy%DPaW=U70oQUlvZCx$tJic7YvFys7wV%mB*B=%@2#apgYOBG4*b76(
zXFXUUxaFOawx}H<xyTCj9W!AN4;2L|QY6j_*|38|(R7l849>fLIcLTV(i*z4-HnoA
z6WB3wBG1E|2wI6&%)-hzG0OgFR85v1FAe3$$q8N$gF6d7Id>{59E_Md<}6>2H$&vC
z8Pyv)XQf+7<oxurX{h7=ye%#6p8S<ew`}@WoJak_874HelE!5APZQ*$HWPv>jQ3Uv
z>jYz>&^-?u%z)9nX!F>8YT!T($(bZ@&=jM1=guc*#vZp19+@4sf2=4^_^mZ>hc_``
z|Ek@)MhOo<ZEktTwgXPz^@z3ddZ9G*jo?dZ0@(jLt`A=t4ik&$rWJy4Z_f*d{QXON
zh=MSQh2y`GUMPQ=c%b_++ujogXPtt)<p=9B9$xJssid{w;BlSE6IMa*!p;UyF+H_J
zUBu1ZUbzJ?jkKKk;JocU7!kKK?SZIvtArKYUbC;RmD{W3(usUoZ4b&bE@pE0W7U)C
z=AB>r^Bewx{M0pB|H>=H>(#oLAaq~%4~x}--aqKPBx|eV!IP!4A_U?O&Sd`-CY(Qe
z>v2E0;33>vru;$%_1-yQ$;`9fa7~Sa;6LMA!)Nw5`<r_{?(G-Zwaom7)5Rq{S)>bB
z2U^HB2QhIj`-FScDV3YM_h#m9Dn!;^xEV3ob-WCS^evX$PdM{u$`ldRCHLk(EY{0;
z|LN3RO_atLs6?764;8LgSF^?1@=2FNS7jSZr(C(3zWPVeow>sx-141_>F+?efxli2
z@omrj9zVZ$7kkDr-+-$>s^RK%#{~yP|G1il_0|Hg0uLVt4~J{^Ho#q5U4{7Ik3<~M
zla6V1I{r!%4U~H{Yn<nMzis3#YyjJuXYE53f7WS0`_|{)fWY7RgY#;__wq*bM>~aY
z{#L>t*)}!zMR(+LrCZVUZ%l@u%F$FWsPaqBL*Mx6`UN{Uwt;5{a^x=xa_@)1v-{2q
zXw_c;Dg>u}RD-1>aWpmS0&|w%`()us8zB4_3KzxH`7f>?ko}X{$uIRnik*W+dOrVU
ze{$c8p4O{v0|o-iX%OAv@`w(+_bCxvn+yIJfT$%B{dL({Oi@VfN^Bs1Y9I!S#>e%!
zpu2zT$<pusLSf%E1aE77`Z9k1hfk)?eItl2v?rgwFX(<|b@HSARAB?~vfpxg9t`F0
ze$L#Mo^>a#^a_MI9tYzD-wk^=%}>t$WZi95Ukxq!Rir;2lD$C;E0!IsZ5dF%a4}y5
z1?u1ZOw&A^wk{79`bDb>bPb&L)t<ub9%reyv-LqW`K3jTTZbC$ZcF3xPwaaG+*Wg;
zr@ft`_z?QB!;g4qRV)q~-bqpEJ`q(e&<LlyPb1ccH-V?l^-^rfc@4|u++PSNg40h!
z*1dA>^TMtkj1ZKbTMdtV<WIJYglV*GXGaPg7{YB;{^0~AxE>R3<zQHun(d9J&L@|5
zZ?i|vLgA*X_lOwjnON|oF3{0s32XZG{X(eAz<60dxGm)hMDM)}fVqa2fH;{SdH7Mp
zMJTU!veeq_#;woe`^;-5Z#4O|3k7MBc@+UzRKR^3&T;SZR^+i?2m#!I%MA^|!Z?26
zgUE4YrC8Z^d8c)M3fznmb!k+K?}Qf@Q^)E2P<q9w5I1Ww43ph?tK}q&5ePODpI)Ta
zmMGq;O$t}Rq847bSZYxtZGs@%aw#Tc0ct+7Pm`$6gF!zsmxE&r3J>)iIptaR$GjHx
zdR5E0AU3pbvRzcCPj&<F!p+sSxR!}T2=C-zYg?L;IPx&hEV1{Y^ZxxpoLGWlGkN4P
zoMYiKd-?J0U%Y^d#Pj;)xXL>c!?5o!O~~HQ*(B^T7!1IA$kn}{FKCMPq?g~w9*Dpf
zCm%IhVXT3~{=sb5;e@*Ul#t7*^&(mvU;TQ38lWreQ9=(K!Mo89D0=yk;HWp<>6JCr
zVZhKia|(fAUbxs@EM=iUQ%}s&O3CmL=5h<=Szn8gbOr%l{fYCw=bXwStaYr%j+e!N
zuX*P;{hMK@@Z;@wA0X$fHT|eKDZqV&m?*eya9!2<B&@=21YDlgeV&5Un;xMyVzMIy
zk(=Fn&5=zLR}KhoqFS_U>4Tka-uuuM9SLDfeGc&4&ujwBp*nQ;ePWrPMblkORV>0!
z9oj7oE%So`;>P~0Cbg4r!3z&l-;lkDWLXqRgW^;YrngcZ@fWZQQBp`4z1(5jJ?)JA
ztVn=ki<=aet9jdW#k7t70<wn@t$qtuG?mSWFp!D{WSj?(j)JM<z43J~#ULK=GZqYL
zVEf%LT_!rcoqVQh+m;l4u)&J~Wew#yXSt+V);A#5qxe2&PRz;P<<$HzmD0@14?oKL
zPEdqzzgF|)xuSJ>svs&Bt-kU=82skbU6}c@VY-ZcWq0FvRX<-iZnicX<8#Xb=60qB
z#CV+)QZ6+F)O<iNjKco9kgW?s1Zy94D>k4AjR%*`Ljnf@mk_RX)`)FsJrtWrihLYV
z97z0ql&H*toa<gK4il(Av#0l;+g&3EAJxBpNQ*0-dw8F*<G4%ZGM7~BXeqq$zrAOj
zZhlB6;cGP~<8+_p`z~5T{Q&_rBsaax6(T}@+FQ2$uUbE*b&Kuv=WH=Go9-ii799WQ
zj(@hE4W?wHYsYavnSPoC6NKO<MKQ7u*0Yg4ZTAl{3c%j`cv)Ou7q+_+=b&-pr9wkr
z<mGacVoHus<rLCuzUjXj#KBmGg?q>G#<BEt!4o4rR<rJp$~*sZb!Hyqq?wB0xAsQ)
zt<#xu#(534YZCdCij})opR*<kxxk6^(y9}M{ZMr&Pphv0C68K}*EH0OYhlF=9r^`q
zrYVuqWOt7;0e#Qg6B=aJD$QgN2Hil_<TfD@J(2eK0G2|*Vi7e@q2&XOiO8@-#M1af
zFY(vWu|ZgWFumus>9<bQPi8Xw`*!8C9jv{73qJN^k5LuwZ9ewBs&E%C|Ba~Be;qR%
zA~r4g>^(mAXD9D6!#_KDj~V{iyUg&95C5Q6j`{PC-@Tu2*QdM7$9`u^sNlANnFj>Q
z-vs4Gulc|IL=F$?9v?eShKXJ2kaq;p$uPmEnre+8YnTWdCWbJ^a1sp`{>E$7hhZ86
z1wg0a{|!7OJ_aSxAMh7v;qaXG<G;TNI~@<@uix&T>>c0hOXoOAj^i{mac`>v!rcD*
zzjLGhJ=pM2RGih(n!k#{+d3wn9Xd6%x@}-|)rRvK+YUI>ljMx=NkFFB@6HF#<H5Og
zxjN!F2jhYIDn=`Y`JS`cT_x{R3sfm;x-~JrU>82_j2;^zYwmp_RNK6M@+TuG--Yuo
zXoJHiS*jnp^IOZXRF%7AQ{H`vweC3)t$C#r{_vS<V^#&*P+oA6=e0|PvIF-g!3v_r
zjv)aS{NaypdeDs`J0VogQX#qTBtTpZj;tPVZn)7Z@JejASMAkpa&&9FmR|i-Jz9~Y
zW;;lCzwDN%iCr7kQtF8EHA~0}x^5Jl725`OZi`nvAI%qU2ln;NwjFJ)0;$4Iv(Zc7
zCt!vR6>*RAc_-~5L}(Y*DWdg6kO<Iv&Ijr9Zm#YZ&7ETv8L0((Up2n-@ax7%_bXLj
znj>?m_z7=lAe7q%S_{&--))rAiU_CON)O>Dk-?33b*ccRJXBz}o-box5o78znM<z4
z=D<Qv-;z5IhU&R51hekEi>o!?1qR$$!hxT+o)Kn4DIYjy7wJomw?fP*{j5hG<}PR0
zwQ|ZVkq1KkYoqt;VUQ4CMhPCLHo7LvP$1CcSW2@snHsg@zCb4$8R17}>tOYiNLKA?
zDJ?VMf@XtycHZpm?h`>^X~agnAnN`w^9c45^uh*)z5%>biMpJ8R12Iw<)0NV2JRhO
zyyD6C3VV6DVdjRTnp=HFS|WsPT@UugLuoj>Kk~nW5R$~JnkHq_yW3}+zTgM0IE~?H
zAT1>Ckv&^TH<#VA5EWs1mG1Fjq9SRO<?#)k#p#g^2=6hGfu_Zy9R#ragx9h<8ZCc?
zqEafth0R9#n?)N*4$#J0*s!Jq;FXg%r|dlz`Vt5yRK=pZ=mv{^azTh0_094o5br4u
zw<jRRr~EC?opD?h&znv2r2TK|kv$(Rc&Bvaq^RodHh9tb$(Ymxm75GYI^$mExFZEF
zo3fUiPc7SV-i4Ir+wsoqp0xqc#OK_+YwiGHM1nQS1JT>rNC~nL3efZs4j5SmV(wkG
z2UfFHhQbc}F<0fS(tx_@#`5E(8-6ro52VBB(P2^g$p2^!SOXx13lznO>4ewDw!Rjh
z$>y%bAKOd$n!NJ1dC#TJyDxkU2a)1LQO)m-O9OE)L0J`F3dRvLI_vbxOG7q<a+!qQ
zypncK+c#9HXMf}sp7o%U%@5MgDXVbB+2gq%E8|zriH{-nkQKY>y)p_O#t}5t?P1pp
zi>{ST52&TgHaY(s`k%t?>?B>VYL5z_h1);ZWTs-4jB3cWY}8bu>UXuAb{Mp=D(oSd
z*vSdAk^pOr8$mUsKH^z96QR$5%0bhtfDg^6@vWP4Rya!6L62=K1wyaK<O0A<&a4R7
z`QU+0iOh$6Q1fp9fiXn_tmGo0tlw<EOXhg9l2D1MaK`zBJ;MHOW6(w&&}8&j#sRP;
zrrX#L+os=2sM7E%HP2_%Oq1BTBnu%3=Snh`?WSM$FgM$FH;`b{T6CdB^M;y@Gk~Z8
zw8nH|CIpXkjGzFv!|U>xTD0r*o*{m%#E$t?fKse65hZ&p6;sOEQ!{}NiyGtyu-M*m
z4qJexP}NnhEe-2M33LbU0+6TGnhhZu7V)%(%biDg*D`#7GTzLb<%6OzBe*&~$D%ah
z9liA~!&t(y0M7)$r>^B3FqanobzE;xTGq*JOEH=FVFMDX2{MHUR|t>-a0msIS4Q`W
z2b|}cxf-AyEpc;#YqIqT!CT(w_`(G}Yb0`!8@uZGyBb!8$s&<UeCz2=ETg>bzFx7Y
zxkXZn)}DTyC>_}n$ROHUs28bc0LF$gbM+uLD({ov!?IH1oN8B^$84}17#j6tbm{A6
zq9_qmtZHyN*u~qa+a$O?@LIMbk=cFYM}BC98iVbqD+iw5wkmV(RMi{BZiI_^Bx*##
zES4W)&cIiVE+q9$n(gG2RjK>R&<*2=E~jXQ@Mt%lB$yxvG(ao`Fl5n0s-<H$dR;3p
zj6e)X>xk#>vUxO(c+*c`dKWq&C?>CXP<lDC=s#<R70TOtpqa5smeP%g{?m&$ni^KJ
zO1Q{1xkVN&RB*L=?-{{}WC&m%FyT@Gz{<O+h`}JeoEaFqrn6Q<YhW<$EIp}2ruhAD
z(mqsNVaa1*Vjqq;QixPS@kTDXj3Of|0;fB-L8PaXk@}q^7^l}+CUmR9u;ScYbDIE$
z)ve2!`l<0>gMSQgeIv)?77QMv(PcPqTwNf%$;fM@x;63Fjj3qT9n$6JT|MLgl?}%1
zBy^CR%SpKBu<UXsn!*Ois(1(CTk8mpn*_VHj38qLM&5LdNBJrcxqN~>AX}(}@vWca
z_8CJBGY0kKaHoMfglE7^HwxB(c{(j}RtY}3lf2?36T_Bf^?C)1Ph%z?Vk};;nMIY{
z(kOB*$CERBMYNH->P-s<4mDj8JoGXH$;olCyF=Rg^1klKaL&;`KDjqA4TRS4=`vVU
zjZ+(sQZ?)=-i$ITx<pIZ@DmRBIz85ix`fv2NGAq@IZ8cBB<(rS+a*eUe#Bd&`&EZ&
zDD&2BRF1et&JF}EHbr$M_2sAE1+d>8H>`#~XBu%VkrA@MV<~56Cwe8)aHcT)_T7OJ
z^W+#YMVD1D>DA%*MD!AOyCJ`wTcWW-<ah?29pt1r4c;9v;)*FD3C1!x(Z^Mc$ba_h
zx$h~@|4z}2)t)0hWC1OKK*6-09i`E0F;HN0{5t=*Vi-xN;9tnX9yvNFgqOw0Q(kj$
zsO+^@iO@Nske>D1C2u{aTsyA2H-t&=?JdVn{G7NRlw{My9CI_jj{DPGLbRygEh;9n
ze%J0($`$S)_)@)I?DzxndEcnY;;J{6C#lzc-IagjK0idog1jll+}>rsp8m+sY+*8K
z50()~74zmERR1VA^73l-r2R5+{^6*uL`hpIwcygn(nWPkxXVcXkrcIG4Ws6L>5MZ_
zQ)<3c^qYh4+rLCyr>5?AokAqKcG_ju)aF9Dgn8nhO8=^j^hI7R2%e+3LFwS4TGq>6
zLEIFohEBJN&J7vcf@4*CTQD_MiJH$77LGb{%zZsC*Gl%Tl3m){87g*y?DGKA|K$6!
z)r}f&E<$HcTx%+>O+*)Wt%dIh?-)S!E+V?hZ$7A#_67C6prst3SYO!7-#8!|Oe?s_
zwl>x@)Y~+(^~eFUC6cuPyl#Bs;t-nm{`1N6wX2VaNOguvjZT^!GB}t;_e>Q5N}H>@
z>{7Dt{`G_IH^;gRfR?3{b&6_2*_+YUzTgZ=|K#w0ab5I(I7@x1(u4Enj@UVw`s(wP
zZF;cgKfRm>CM&hBI3u0i08#V%gUq$LE}6gPJrPca{U6Ru&%(}p+W&R28Hm6;nUWpK
z#Vw%|@JtlI>YBHIL~Mt**_FRwf5mm>1-k=4Dqf2HHNtbUXn)=HH-p&RCok3|<iNe>
z-1puR>wZ}RV6GF2zhEaC^1@kjXJ@a80zkGFk0r88;o@;7B%qU{UbQ>>QrSoOc4Bsy
zGm_Z*T#6rXK)LufTT^90Rwc~4$?%mqYowFftBaL^+kpgK@%LUkKe=x)C6@{bn!l)F
zjs~grC1gG(3P^4=eMb{WPit1DnOjb|)Mc6yltl|7am)3sy<c&c!t8O_f}MX*xg|RX
zD{J6Nz<rCe$O9B3Cfuy*AnH5T$$zlEn99*+5JR<?LY&r^2ydv#aB+8Q`f+#fCHvgw
z?3AaOuo~nR4aAfoBu|8UpW7YNZloB%ye8NE?4hM|Ti^>uz<1dc5(#Fn5P&ktWibIQ
z^`vNxS<fgxAS*ow7AW9K12Ng?An3oi*|ARGL3p*_bvoz|jr@fYlbcbcaj5cw9xjDr
z9q#sx$3ME5ijwD3?k>;RsDK8w<AT_&`*?D01OhRPz{qD12ngGp80##dMGbcE?V`DM
zYYIrK+PxRB5)f&^bHU_Xm&el^0g4c2XC$16?zNRWF>^w<)ir6VO&|1HdzVr>f<9qY
zQDw-dE&ULfEsL9U$C`^G$0z`PGymzTrD0nduPU8Xy9*4k8-!^c#C2o~^z1okriatZ
zyZ8G^G3WpSjC2N1mUsjet!gncjxxB9K!a9qW+)r(#_)wqO3#x6fXyYf?wB4zO|u_z
zXC4&wMU)f(MQ26sVvvBCxhVP{#o$^D`*=|LOT#Tb$3v%u#(lltlQp53Vgz<lO-=SS
z_tz0t4q<^#ht&8(CuC3_jsX{Im?}ohg<WK#fs0cU<GzqCfaQ5g<GBXI&1~Fcd<r`H
zg8dv?(Jb(Jy)w_ZZf@A}AoSBve>r?ChF?GSF1dKHVm-EL5u0zUBRL0E;s)rvtjTMn
z62JA|8^#S5v{tvxu&to>&Ew6|aUT~j)D{G|+oOHD>s%KYvtezh%V60_O}DOg1~XFy
zw*vDYFb)FfvYSl-h60H$3rYL(Q(mt%;ccg94GD6%!OV8S1{WC#Ldw2407eXr-UZv}
zWq86Be`9Q{FL5-upz$`u=*Bva(s6%s6Gb>28;rRMKqtin5nkwQg<1_d354fQ6^hIG
z%r=XAaFQL&;IwBDR5-nliGbeQ5hIq)Yb%f|f&Zl4@d*gyuxdXhDu_$)05wFq<9H5O
z)5s8=?vou`?g;4kCWz=V$|3d2^-sropJIgI2C?LhFy8p)3%OLcJz(bQDr}hPvMzbp
zH#|MpA5i_UMcUVnwhO8ct;EekMH2JFXuea5&FIB|+Yx%LskU2Li`{IO>&`4m(GKw7
zdAg{J*?m?L5coxrNJhdO_e7JTd)VJz#>z*5)t~n!?Eab~Whv9m<?Og2ZieXV@}%RS
z%7P$1@DtyAoU*izW3_dnSh}19mZXlIMo!?c&PBe{W}Vv7U|GVVkMr~z#SVZRpS`ya
z03_f7R5a2@S(9*UbQL+h{`7V1iX~pDL(J&4M9eGgD&RP?I_8=^F+e~7r`c(Aq%pn)
zpUz=nq72@j{`P;ulD(6;i}<~DeC%xmQ)7?6^a1ZL6&U^&0A^jE<ZS@+H$X1`Diri>
z?D3td6n_nXc@KO1Ea&<!5R?FreMd{~qM-Mn)Vlzt7L2|NVDk3|e%Fe4nb~4yvklYv
z?w=bUg?E4Vv2pJ@BG~wt@`g6`H(ac{-*5c9y9-vTk^UoXWU@8%JYj4cpns|Gr-mi@
zoa4W}VRF8`>7&1E1Ew~NZ~dHE^jH8DI7vuV@X`z<!1z<OC{{ol-TU1*Myu)46KP<t
z&>OzsOi_`nZLNFzqnSt-DDj>U)q~Z_MQ@N=U2}fqTPu4HV2;{-aAyitX;Ee#635d@
zr*?0ku(%73=LzbM9}<naD3DxAHh;N&hG3a{b6KT4wKe*spt<C}V3mq){rF-qZ@>AG
zGp8lS_i$vz@w{cL5vQC1e#xvmc06D;7M%Db8RUTWnwoH8xM{68zKSnL{+u{dL~YCu
zp++sbXb%|@#iU5N(Dp_!%&3=Q+UIO-uj0S62k@wIlo`w}<%K}J5j8z$#uXjW=c;QY
zXF5A=PX?lR24)jhdhXGv`jM9sxnK@J=!74G1`aRV2Ixc_C%aFj6&_(J%=9cn#cVG?
zl4+AT`6=9p1WdPtk?%U4R=BSAb8fwviCupIDl01O-Co1@mfQv<r(DQH4L9;JbRn~|
zin+~%)=Y)1JB$I|SoTl2#$p;A2R+i#7`J2p+CO`b$l-e$jZ`--u=fABtFoa=F*WiG
zFcK5UMCDA%eBl^toz9JsxZ**yG5~*^7Z_4>_-P77nG~1CK_!c)V#yi(13V_s1Fb2x
zb_W9ApDzvZzc^IK)PM=&j`lHZ6+@1~N)TE$#$H2D`?&W28f-L(Wy<JtEeLK1s#;>h
z&uv&6EwRN6W0w7;0bS8$|8E_kjau?iSIujH$l_?RgDUzIfXC~M@o;$@rp8)g>O4h+
zVe}hN@O)uH1e&i!tgy^=Mjx2aB3*kLK;!N`IY}#TVlaYW7{KX9V7LOL!8QuFf9Pa`
z4wc*sXcP>f>FNus+?{>EDTL`O*~)^0f8krww|$6Nw1~dNKaB-9tw^9H-9MKCZOSb;
zxhEXS1q8mH#?q-zU;!ft<wh2gg<gWL0c6pA1UHi?nh`26yxU7x`9yCx)EjR(y{7xv
z=SgV@l7?wlm^<I-Q$67r^bXjE-pgRMF?{~jzq9eu>rIbbzOapF`rpmnNRDbM%!iRH
zPG4lwK7Z8A1l{u{iwR#EDmlOe#WhH}ftAH4m<JyHF2IUn;Bl_r(C8q3EO(WQ%p5nx
zZse^4yE0rkln0(@h}(t#p#Rc$!K2dCqhG3Y&$v(mtcpdVKS%MEY3LE4>0oS#%<7hN
z*v3iewtIJ*^mLaRcBuFA5T(Xr58wF33;NH$o9!d-1;P6}+EDNQJ314m`TraCU)q=d
zFYht^ekex&>3|#4g^u+rq6a!Q@ZEaAE4<VC_1<`u{-(SBy`OnENBrGv{~sH``T?-r
zn>ydwg^)%zHvOeu^}b`<n8LsPcWk`!()V)?;9EVlRXobCG?2SyRm)k-fI<sa@JO`<
zxQlEVJRcsq6PJ?_X^c6O^@_!*azxncGkLx>i~*P6g5@$&Fsj&tCTKL*PH@6+zWSbx
zRx4Vy<!&32m=7Bl(lrJ#O7x=4H=LP`kkH+|HVn{vzbokO0F`&YpnRZi9)W@G5B&PO
z4O`1TaH6;Ggyolfjg4JdDLE}FJghn?6rO1ucS@B<&*iHMw~^Pgy4^|?tjG1$2N=T}
zH?oTx(b0N7%Mvld6K`1m>v&Eny(S?Eqj1wm0AZ~|g``Qq$iTj_VCZ_WA(ModbPPx|
zl~q`95H&`nQ+P8GxRO`-G{l&A##d;4H4x@^Ste}!o6|CbGln>H8FUvdq1;Ak&8l~#
z!Qxd5h>#~5FWuQ<48TD5iH@+C(>{F4^H>h7R5{B~yF4P|1j%Stj^rTGM7-Ug`hd~M
zBe7(uf<P_YPA*djBuZI=Ok$E^i2A!2VMt1{NEW(xk$OL~?0e%E(cx~$B^PTdXC`f{
zD#T)dxmT~+-~2b5Y-gLuc=|c$DPhB#b3o7OFoutZ8ln`K>=mGD3rg#PSJ+Gj71|#T
zS=WIfwl`Nur@A5Bo5HQ5$5<B{m>d=A42d={QoNE=HvAWE#pbZ6H@)IH%tD?-)YYaj
z)$O8~C`!vKm5qHkrhoE_!~mfudmBnCTBe$kE~24h=sJ%}WBZhDE<jpFTfS|<nNdzN
zx&*$zTBZ+kZXQK5W6Xsp;)?dAQe5T{m2${pLT4iw=M~S|xk0faL)$poBZ$WT3Os*}
zxIzS2qELXcs&@X6OA?46Ei`K#6JH+qJ|aXLwt^l*L=LPRDRuy^*bVeoBjBwnVFt%^
z358j(Be3d#L2{-%>FP0I7%R4ca*bhBdC(BGjqn6m3Bz;V^ySJBF=}BNxkO)Auhm$V
z_PlF~8$Yq7s4#R?1Cu?c?NB1Tv618TY*^F<NaU;}9Aw3Z4J;PkQCFBb6MYk54KQWg
zAkbkf>HtAx!k=R(Yx9&mkeoIBFgC7N=3!eHj5&ryGLW&b&xYPl|HBc>-)M203$X_m
z)+V$geC=bA&BCU*NA8K>#D<^9MRK>4^&Bm%0dBdffP>R^>sW6ho!~OeU<92i-9f|D
zJ_d)f<;*Yti!R>Cpj+#)#|<+_wFpHt2tG-XKo?hHh+!K7M@T~0RFN!DR0v&vJuq?C
z=w$|M#hM7bP>F_x=Y<;*aw41j1m=`&)ss*_l5;;?%}GtbU`TZbNAgX^hu60(y*K`+
z&o_iNdvm4&%;9?)7i$cOqX}QSIZSWT<OBikwQ`?p&Im;2>&=Y-nN$sTt?b3ZO`_S<
zxgktqU8mDIs}DafoC%o4#?sxRR>-wCeCRNb0Q!Jw)VcpKUA*|g@6EgbKx7>7UWx5>
z?RPMhTKd+wEgk<h<a_|8BXt=PQ@@{LCX#W(szk>G08pV@sHA5Rn&KEeZTk3iL<>_v
zApC=3KKg<)bDVBYOnLdCv@^a|H`I=)2?U9H0}|LD-J~iPfA{;0X5MNt-w;P5Eh^`#
z$byl_pyNFgJaxK*_9nY&xbvdTND|EUOjS*@;RfA2WdCJK;m$-k2ql>WJtdPU7J&kJ
zVC5?kiNiiCsICn07Uaz7u`W?9af3Ox<_GbwVTL4y=t?Gp{!B-Doq1&y&5{mfHQla7
zd@2Tus=&BVI6x3)3_3<MToHJIXH_5#nEnaj$K&Ll91N0{zbjo?Pva3MhOJ71PT{(k
zJ7+{IeMH%Ur^2wM<jPx_$MtMSyiK2z`%{=cij_-=oP~F1Fuj_DuNk0pMaRI|L;6d9
z!8v*Pu1FUzs6um)BuKAF&v1oN4LQBS<)w*1E(Y*ov5o1k#2fpbUny~!DlY;dM$Q7M
zfpyHvb!q1X;5gP#vBbIq(<Nu_>DH}d4<mPGXjd9u3$uwmYAIpcxx8iMtcKaA)_G5O
zW(n3S!#HB>l~PEn%y$X##=rlZk+<4`$3ya(re69L4}c5N{>&BT09_x0p{}pSRhT%}
zSmgMQ$%e!Qu3SklRr#mWGXaTN%qPi&PhHcvQSt(x7YX$6{$B1_R%b>UDhys1GBF;A
zI8i<LhhOOOo#r4*l?X=%rC8Bk<UB>@8!Wd<QR#=%3kDYdLR?_Dp-{&z#Tsw1<X-r_
z(WR2#z~v^3D3^+azgY^tkmCXLNkz?p=1@R*mMFP?U)ps!PmsNl;F+}DSO5N&;Sw~G
znkrFQJ-WIe=LgI4IK^(^>xwex<x)c|lnd3bGt=mNH;+mHtZ~g?v)psVb4r!hqSazE
zf58zohD^CMFh~)ID8FVC`+L(7<#{FCl2@9q<%esv)ppH)+?=m9hYtnA*W%r!+0kXz
zomIIfdd?o6lI5@5tOZ-zXQg`h7o5cW*|Adxr{>RAcOIPf8_{RwlgDm-ZSW~wN*A_X
z-*f4_9Y+`KKT9)n?R&HI2R8`QIVDkI%^i75l4ZH(vCxq~;=bfWu2^<Us<hM5kxOJW
z?U{(dEGuJWuX)QA*F5DeyLNubg%{XV&03@io|{*<ZLv-4Azx8E=ZdB^pRW%;h%D%=
zzs=iomfX)X(%&;APul)Kp11TQC~$ruJwLT`)LxhUz4ONo{_*kJ>Yup#s@120*N(Wd
z6pWj>uLUoahN{gUK62~<`~Gxcd6;r#&-ufH<>0q|_=aD7S`%CwWQ+9ZpyqdGi+~gF
zCB*3!Z>rQBk!MqfKiN}}D*_(uY*1wRvCUc1andD^Xb<s2o7Ama1Xwoq%s*7!&}5?i
zW2Q=~itFnioC%KPMpnt)(gU@zdUPs1id2KD2C+I)XL-5?HGu1XMk^6yUgZxCUY0bW
z`h)UY+uuF1Z&?rn*^71wvCySbN@SGfA?Y6INGM4Ao1b)6Iz&UTP{56R@zC5U$KAUu
zQu$-{(%_3?L9`x=PY3YspGJi|w$FV%`1D}bUl7H*+q)MyCVNZA3HrD0o%&EAI8$!@
z1#0?J=YyTH|4>UOKNOF(AMwWLj-~f?Gz-1ccdR^pzL(qwG4lR>u;(YgI{dZtXPt+x
zelYBZBfc-ZDBgWvI2#mipS7Qf@6=y+9)A;cl7b3Hexn|j(*7fVcK<(|n3XyxXo{Vl
zPcj1>gGJ$-P%WZIUAhJ>#BHLPz&MN0Wr)rpn?qd#9cLi8R!W{1+;Oi*UIo%fL;`(V
z5VBbi#$tY_H!vxjy;F}%W8^=OvI&EId26TjZvznoMeEBqClUAdN9^l!!z4dMQ{jEo
zSKubb@0-0i6;`K%{(L2rOR4+9*Y_2kaE?`xB2Q($CZ**=Gk+;P7#9ER!HW}N@3LUl
z+=(y|VNsPcTM*e17T?>Y3(+EeLITA!$qA<MqGOUl5TK)@vq`FtF#+nFg(b0)JvX;J
zXiK+vOUKEwmUPK{SxyzF;=^g%=|NbBlkXj#{*o?N+UsnH3I#+DD>m6V-*~Zp!3!Rl
zb)Si>?X&rJ$=OE|zHh&{FWnim@9Plkd;HCP`|>f>WBU?eICf|2{mCaItJu{bNn-@*
zpDs!P%<(|y==g~_9qZH4Dnx7e_XZ0~bu$!yNlRO6%zIvGB3j%^9t~z266>g*S8Pft
zpSFur>#$q=PZC0%p7Zu@bv`Go6KaXT**Vfld{TtyDNjBaQW-Y55XR?HBflp*d$Ob_
zE~O4#oE1KKJTiNz_TX%sAg|)0h;I6R>(74n8%NWLeo?qW0aR~<imas=ZAo!$&eW=1
zSb^kxY!r4acF7_y2alQTCyO?tN#E)=1}5o!_C{DtuWvf&iuev>sh~>xTHmN^Rrofl
zTG8aEb+$}pGs^jwKOu_8(jhTD==qbg`QMuhj!?;W?*4G>AIx>`uNS-gMG{$jZs<g3
zj4G<tya+-O)zt&x*zNLzl}-8@Lil0%B#qFk&I#369z^VkvCMTD&AH`#r6hEK`k04m
zDdE$8LI?(tct#<D`asQ?w)!b3!`VCR6cD3Ab;xPGAc}dP{JB(evmX43;?%5Byrm`|
z?R(Oju0AL)+Fg~;O(kxSJz`a)c_Z8;gT<7cr>ZZ4?=Pj77`Y$&fn=I-h1r21moDIo
z=qi5j;^4#_8A6LFJjJ@F8oYa?LG;=YVNZrYr#B)dNZAWhymCHeW%EAY*d<XEzOAK{
zY_AnS<k<IdTk$q`&gpk%o88Ll*X`>>%KZz1M+Bij9St-~VdUZ2{`Y37!k}wpP|ShE
z6|!`?w#NqLvI9OMDQn`&NaF9Ed3VPp4rw?O;fu~gb7|@qx4g(ig~((MU(t=V8IIk0
z_%=-1tMfb_np3?c5udK_h1Afx60;<eg{#xb>@}z3lGHL~_eFjt6I9Oz#fQAsZ_wNm
zOP^`Gx>APCY+>B+%|^|K>R~UD*YdOdgT`SB8iZtynBn2XD|Ih+C-+q;`9OSHS5m+8
z(0Iiry&pza!>la10OOR0CRp1|E!{=RYOlZ)ot#T9K!_z0obDqhC|ZD+-nU5+_PshM
zx+J^xl3n2to@kPmGk7`ptS!v#^%*tt8d-Og3C+gCYjNMQ9lG9%Gm^fgcBgCZMD?&0
zk34p;Z<D`6_F0tqH4X;}d9_>@vyEjDOKc1CsQjMHctl|LMl@OVy*;`}t}`bvW$JpF
z(kULSa50=7^qgV3-vT2)6roE5smCCMnuNlWp(o9Tz`dr#GvDX^Q04u!v`*K_4zYBW
z2%><ii}pIFF<8yQQNZ=|7#AueP6vV*E6eAOFEre1QYJF*mw{-V4Igm-n_t$k)_+1u
z@<u&gS$N8M^>g<WiOyg2YfUQZewUcg4o>u$;eR-QFveRS{o5%L{XR!;oMgv;{v<#0
zUD`-}-&x!Di*KLgZcFYd5`C0^|0->yvv+Izp8BPa+&#%XS)=bN5F9+Rk#ItY_3k-P
zB)a<N*qE5^nqjMd(^l(-X}<Bt#t#g2M&E`VZR8m5%prgICBNmA`;PzJ`?m7tU;N`-
zcg1?gzW4s9-~r#;6#wG3eAgE8H@5scw~zknD?!o4bnaHG@D*cwh8#K^7v#5}C7!bC
zG+pduL<m&exQ_4W%@1a0SU=%04!`Er4oMu0UFD`aBl2RkRGLqXZQdTa+t=o`c7?ch
zWHp@$!q@$JGw%-C#cRvU_EJvVg6dc<Tur-SOi>}(TTbtAX5=m>Bf7Fyd(GJ%EW!dP
z+vEz|@*&k3!|#3bSAG<3qZxB+F_3~?sS^=)45}D+IcgrMa@dWC6bQ=|N1ez&qH=00
zfuTzG4iN*fXf_@Vw2fGu7N-jgbo(e&A#>Pjnq}h!27eA7eQx(a(vso4Me2T)+>m}Z
zr(SZ_9tm+W?7qA_eths)<=ONN|MlR`S3f8V>v;dRsyJJA;cB*p3c8O9g1!Jv+7Wx%
ziaofeal=kQrZM1~QVg@p;C)q2GME#;<0;?jB)wHzNQaDzAhAc5?9<t8(oGgEm=x#H
zMF?r|k#^nR2@}<A;yuR3m^Hu*3O^YSN?FDmFKi{`rFHbXS$Gu)rw)^CK%Qktk0=&f
z4cEpcvm^3zBGp%m?4|_?nN=nBwh6pH5i!%wM5+X@u{_}V<5#GeAeX4#if~)d?KYw%
z+grhjE+M(0M(x+);HjbM>U3E71rfw`-)Y6QAduKZcEj2;C*d8(?gjb8qlwg^t|pOP
zA>u|9;7{jJxnX3J*uIjA)AOPpmFPnKwa!+1+$3PP)bPC^$_M{KkWmqNT-DX5RnXlV
zz6C!PpkW@u+5&MxF%AIG7eHHa?d{}0TESv^Ad-~-i=m7t!^IJ`29DR=z_tJ0vG2Es
zX+zWRZVF*1+R)z3re*Ut^4No^T`6w9$uJT|Nf7KWSUZV6f6Aw{T;^HN-t(+CzvK$G
zj5y;7@P<C&)}lQ)SY-JL|8eES!<JKMUvSoBbI?OT--5szS<Xtv5lge`fM>t_MBzL|
z1xB7eCdI-~j0g@&6C2(t=tX|X-`*?i`wqNYRIFiDi{4vBvVLomBoYQ$TkQrvBu~UW
zq%w2vp-59-L`Fue^q*SwnoxpQoTb8CZHd$vD9tZ{OfR{H-3Q-Emt#v-uSg|$E34Hb
z&6ZqpM@7w#1?*hN6(hF*h8;VLe+MC6Tt&DTXxy<iFzQg<Fqb%KKaLg*sfV|Mc(62T
zZ4bl;Ww~|xhkpV#8Dc=N*<DWp8W?Tn3lIU~yp2JP)I(<%=;kPC7@`Tj2s7BsJ!iX+
zu!|-(Id~p~MV>pMSp<Jhl9CW@eOf8OVFtad%`5Hs@AAAyJ%pkScQ_GxWf6ZszK1qv
z=9HOMnk@mw*W)rA8m>}${O4+V8f^N6HyrQ(BJOR#<G9ZI-kHIMK^Vr~8I0B=1fg~g
zW|zYyND(WP+49kC=FHBL3lX#c2vSkii2(?(C^@bq+O>6kbCaFfSrIV7h=k~t?e%>O
zK#;<?N-fiho3y?O7XmFfm9Irgah3GL5-lfc>t0c`;;Ly=-``ovvYkZvXrJfal>jbw
z=i_|5=gfKk=l}lSQDEFS-8mhDpsHz7G=VvI=<9ol=}1Nr&{tNSt`_B|6V2*3$Y&Sk
zB_F$!p7ObjTXg53tCb@n!(6nKkk8V;`?FQL4M>JY1Ct=nz<DrJ){{)$f_nK?7kGs2
zb_$^8dX?ywin<M~JWUCrHDab+fO$!2kx|zo4%Wq}e=OXQFjYfKYY0?cbXAj=!VEL|
zflTq}L1Rkhb+cI4v$m_pPnyOfjAhHrxdxjZx`=^G&kMn_Bp+7^@rcoCQSiCTPlISU
zH%<kZ6AB~s3~0NW`QyN_A}5!I&>4dHWGM`i%t>dwp4&VcXOF~Ms1O$>kX!WZ5d;c<
z=4<bIX};{gC&_n>SSV1jxN!A`CG`aaPs%3Bom$?F4G^DL`&9r@zJ+W_yn%iaYCx~j
z5Fsfmie{kk0EP<w2FL^rg$?gEgxW&#OPRVqU<mjA(C811hA#Sz-C|VKceyT++w}p%
z+S$sa#jF4Q-u#$VyOg%gNXwpf7fA0Jw@o6uPCLP=LCXx<Y>fHr#0#TgutewC(TI7X
z1pswxJPmsRF6k^Ed)0Ec40$7ucq9FS@FX@!8qza_sI68<UI{bey>@+BDuim;1?B`c
zU7M!!-E`H<|1=}zs&hQ6_vmrXH0kgKBRfe+^nh;9){i8#gi_qp@<@*~bhZp2h)}79
z7!+E+i)b8epp0F(UM>TayTV_3%482rtKe@}(~d)D$!$%uN1FLB)TjFwpuVSrWYqGs
z#^tq{=x5&ik;W-A=#V#rwjlKrF7}wyxf?_n!8NDo_ys)oJX8rRjyYFP-9@+Sq@q?i
zJ9)Oa>1dLItjU<xh?od9A2=FQj6Fk%(PIc__SZGF{utMY6RbC^e;!KX;M4X``Etr4
z+p*a#2{2@tkp~w3M{?51I=-S0DHBG7zkyL`0|pYS0qjAnvdB{w7$D0*Aen5DkSUv!
zUEKxXABgq*AOxVsDG1=SM>er7e<NfA$4Rr7{HVJz>uN4c7eCT|={sAc76I!=#lOQI
zmqG`#rh4$G!49{DC0MM*mbaj5?)eH1CZrp%a6DypG7`&Bnl>7VP}L+AqYYU1g-M}u
zDZW`38vJbj2&C6D=`99}k9(sOfYY54#SGUEKRvkZm%Zzm2k3V+6v&|Epo^r%K3To4
zn@0jo?TlO_rGQSyLAPMJ0Ki3iV1u;G!>-Y!2n#v`A|*WpGi)_kvU<mpUSMCz=y2~+
z6^-QqiZZS(6SKjhz23-Zw~zs2%_2-riYtHX>r?m_l*nc_q2qlvd~|?lL6l0qi@L^|
zh}i`tD0YRWVWToMoKeC@DV_RX0O{7)1<XWj|6m}h!|0CZ>V)dl)BYW+)1!%nL&h9;
z%q{n({e>RNs}<Le=9A2)fAR3^D^_ms<{gjham?#p91j1zB{#2Mq*rqfniaq2fr^Zu
zkC)6(mCfd$dENY}ov9x$tHjalc@?)7*DL#Gk_D??;gdD^bFB9l+Lhep<f8wLWXyj8
zE@Q873abP}E)JIV0BZuul9!|Td`hOZ->{RXE24HJ9`1iWxy{e{Y_%M6MfGC+ly}Ig
zl%o$?xh2p4U}){0Dc>l(!LaxAy*DNoS63_x`1;1Aa1)?uC~hpW4>)kH-dru5yrVf&
zJT9wGJ^JIG^`4c*=bb^nSRdSJZZ9l8;zOUBj`x_k%HSh2r&KY{T|X1Yi__+UC|4Gm
zt5&%*$gYMcb~lrmCJeTCVOsd{!qX`G9C4dB`8ZC-6X3=d#h|~V-=f%$h~j*Yb7XZP
z^so9>JS<;{%g$G<#U<~s-(2st7Q2r1`zJ)z9P)<4r#vD#<eu@P2gT2eFARD6K7M2W
z>3Z{G@<)#N=!5r)=I4AGZl-lkTr91~JH<a6ANR|}&lGMIb369G^3dmszw4L18;5>;
zds=%0R0{EV`+D$Je&5xJIBA`7>4CR@ldaV;`5;y--A)_{4B+nXhmm|Ac+E{R-;&Q2
zAGCwHzKzbtZ(*(~I0ccQYiD#0mQq2l_@TKMiff*TJ`~>4-}9nC&K`jTJh%?1`yz4p
zAg{Ya6@^j&b9EIK+xcDiN*atm_ENL!r5@0d+y7|LT<CFUKxnFCrbT+w;n!Vv*VwW6
zI{xkbTsroT-gkBoRLMUFN|ypuB0sTzCRrR4y_cI~zgi4mM^<JJTFv*SPl}H^w|qwI
zN4)se@DrEavE)fdj<4>#3Om)?)xVI)a`}XF>R`CrTtqs33pb0%Aw6++t+Z-=)klT+
zGv-(NY6I4rzz!ge2VdS1eLQ^em5U#Es{EZw<+`KdYA6x&27>w6_TFY@*If^<d@e+u
z{K}`C)|)dM{`S7P-<tV?^RzYh&&3}km(tgxu=JgO^8WKy?KVOo>MH_Om<#6LQW-+q
z4m*}0E@x43pa0~Grg1F(<n=2(U@c5We)@21o)h8ZS+Df8Pjm#};AH^-x7>3Axf})G
zrrI(0v2K;a6XB$0m$wrT$a4u;XpMg$JNZPx03L1K0(`d8GEfR>rK<vkx{Lnn2f|%5
z&GCV|XLs2ElslgaC+1sk3bE^B3S*>1x1<kUBr)u+4~Sb=2<Tb0YF{fp75+g}DP-&_
ze)hj?8@=1!juw1$gB4CjV>~X%m*}hr=hROsI4f8&oln+R2CbC1G93u}vZ{%(_M}C8
zj#IW;-Tmjp_<X7W(Sp)ap=XWlBvD0qy9|B{$fqRFy*a`jJa^Y%d;yUgkl<vOAUnlp
zgf&V`(|D9W=aBW2O3cI;HV*8%d%qFhNk!(@-lLE{v47lu?Ukoy*g^<*McKYm=5Vg?
z_<`etCvwrwH|`$N?tbu!?;N&o|0aN4EqdKFmCE+$DKkHI3fQaVT(39fn5m>=TJr!{
zjqp`A4gf3NosxB|(03AhfpAC5Awed9=n0D?Z(af1e|(-jivSSW>E2}qYsjMz$T2#<
z(w_)|W6HG&U^NkG#Gps_UQWi-gI)!LIunMys9NtD!!_W7Z;rh8z7Y5>_A(F4vA?%-
zwH$n5<_rFZor!Rlck9`%?e=wlzyD=|hHBqLr6#)l4bwcqbDR=e$Ia`8b!9}zuxMO!
zUP0mv83jnYga!2wD{>q#a+iqHypiq{OHS*IKwE}5BI2H?0@VS9GC<Zw7Y~NJ%+XZh
zllK!P*P^>f3L!l~`_IG@^_f%-JT>#U**fCwih|!4t2GRDe)Xp3o?R<G=U<#3n(?Us
zQ85aIoY{5Yc)#=B1Eufm=zD2es@bxy_UkVBhoe3sU6##7DOb!zbCZpE;N93Pbx{tu
zrDkFfltsUuCG^V^tkFwtmWGgWPV}xU_c(=f;?lg)0J10IWO3Y|TQh_410^FueSWKN
zkxJDsUD{+d%>a;BvH$S6nDTZ_XdUB^3+HAm(C*%@uWleQGdBNgx9pnPPwMBi@w%Pc
zxi;JTI&!t8bK+gw?Y}=^EsoE>q!gSSoxawb)7LSmubV{qCU9d@t_%Xb0P>>U2ZT=S
z(|&+cs~aJD5%|I=^ctg|P}(`zJ3AB7GJvX8_?{b#tEPT}_8*NjVq>(&5U>fhsX;us
z@!kVFC+2IL2N)Lz&V`w^8@-{KUh}N5y!VE8Q%g30dT)F7n`_Z1sPBOjq@Xz%?Gk_T
ziI-j;%Uw6fn6`V?QCQNCB}fDrw#Jr~merq|bXIyaI#Nqf#z~k-g8F!wNThKAjnG*u
z7{R5Ge9ZFzrc8zfC<IHw@m#GnUheIhy-_4OI|^Gob=>cC``JabrL+@%e9Kz#;iPBM
z+exSFuI`%6z9?+tNwMWh7}oc9{XBqh&%yR%^U2u8@LH5!_|$=&SAX;O8s>fhUx;;*
zNstOSjDZKZ20uZ!ehQXvL$n=jU)^wtr*Zey?*#3!*0N#!OsEw^(zA)R=IRIuY+VK-
zV7Bq{J(EW(PJ508O>|E>?#HCLxU}gQO3??GXVjZ5ovy4&{LDi9jMGYz>(HssP3|eK
z^{3zRGg09oL6S^3R{*VV9RJ$XLhY36<R)yBPikx@2XX&c=MiiF&BsyDixc@`-C;#V
z>dv$gR-6L+mrAET9Yqg6CNm6f)#E%%OCYog4$gi8u-D@&oJpqpAVyqVh_U+4hj?H+
zmJ<Cz@&n8lxcC7l^-}qQw`P~mSN-&SsIcwF39aGH?k@o_J3euwJJ$f^3dz-v-|z#F
z@1dXkt3ba0Gy3swiwynMF7l@#-#-OD|J5!+BG<c`C*Dzn{w)Oi8u+XhAY`BYLCE)+
z=YeIrQ^*OdhyRinuHHMnKzgoy_4WV#oez4ali&XQt!uEPzxKNS#clJo=>&g2E~2f@
z+J0flBrwq(cbcIdAQlBjik$=yL}4u)tvuxz-uYh3FKkv85_WHVWGyOyglx-*2F_BY
z(pcKA<-E37=%<*&T?64JqgZ%y7<Ny-mUu~~s^@=XU{z9|<F=D;mL2Ostshd#UV9;4
z4?lZ)*jz94;CRQlC+UKI-q%{E{FWZGz6>02TLou<OyIzzMq?2EBnS#25Drutym<VS
zeAr#+)}9N2sj&QH#f6~aci5xTxQcl_pV2~+yt*I}dI$orxMJUFh*0AR<=21aWAD<^
z;E3d6l4sUl=j8QJ?TU5Qj23%8d*Ko~TI6W%!k`NE*0V-ahOZ{mi2#SfE7AckxCIUq
zjbTxsszEq8j&T*<7fs<e1_8I1*@E^p{CNj=S&`6G&pSH-I8NG@_Vu23iQp7TJ|PL^
z^@c&F<egR}*KH$;<CIJnm=aerLcZ8=pIhyD6A%75A#tGN{Ir{v;h&{}Av{eipyEDH
zbYFMYK0*N(^@^3M-sCAwL168Hup13PR`Wr2{(#_i8oNm>%i`G`&<ln&p!iAe|Ll*L
zz7NDe%ng)Cx*Dv6>wwHa?2M2N>c*awH;sD>B1T_ojp@Xik|2ao2BkVDhVz6Q3EaFc
zP;uzeuo^z)LI5WDvVsHAVbX;V8h&5sT=|2sy>8%!N0Pl@LR^-eRaE3b=2-E&y45)4
zLuayUM(hq4-o6)CS6x>tghFo;ta(4%V-1}!nrzavl4P0?#DOHH+4kCLGoep$!(VmR
zo!~4EFh$5Gm%SMm^=Q2u-{`LUfC72b*x~yAlh#nV;)2WdgO+^y*AKVLqyF`{g(6-E
zGmX&MWQKO)mTO4JHPjS-Y0mHR5raWJC2HUlveHCf&RnX1Gr~J;87bP>?7J-*R0g=s
z@liO^(~7gu_7rEhywY$JM19=&E>V)Vtb=YmEv#S_mRw=FZF%u?4=Ez(vHoCvpI<br
zgURBmRqa_)*f&9_3x<f!J3f&w`N8Y6PD-D~z#JN_?@2m<y#bw`=QFk!usN`Rm}yCA
zy=i$7X7Wa0&=(aAi=0XtO?QbYgQvEoO|i8iw8o6cyC8NC_ipjjXar8-fvHu3ZkiHa
zRt5`2Tvm~!V{Abv91p4$Axz}P<-#Rh;eS3@3&>|)&mnV4WEVSLim2QMsLjuaz;FR(
zwE3OM`hyNa_{I(yKt-Af8Pzft(b{jFZRj4CWh*5B;Jn5i1p|#633Ha(Pcc}osZcS3
zwWwP|7wTj1m6U3h3FtGpPcx-m@@^N?1@@~z5iA-bXX8j=mfcp_{rbPx^Gjs+OsyeO
z7Ysi#q%E4MmC4#eLsCAC>WwGNAzM}r+3vr{^Kq6PAGRP|rAE}$7hVQL5hr2KTluE`
zsHCp6m5jJ=ZPSaN9B?gfkcf%BAgm3&$~cW4^y-<Dz)#(%yU<44p$b7$O?T3CYH%*T
z@iB%)k8?4W-GGVadlGZBZkgAMSe~_d%(|<aJz~(k-iR3;tPnGpu4`;~qX`;5nkX34
zSd70QT#&>5I5B<IJTZzWm<06~BF@8_Wx8}Cjp?lXoY2$rV5{UqqQMJ>lJ1Aa<HWZ3
zSHF?hMb<S0q(!9GLDzhRAqBdYA4?->Ks6;r9Z*536+Au4FAcOKID$()J7ZO%<65cV
zUVsL+FkUCMN+xO~{2IB0^r^3bN*@4MJzt!fnR4@ncb;j4$(1h5Lk!4Ec3>#wFaDC2
zZ~IzX<9J8g>n^sz=(6*%7~GkicQNCJMg1`SLMD<7GfR*U!%AJP?Vc26;+`{_R<OrI
z7xi(vuS}F%q`A9ol7UVK<o(nNeF-98#f(Z`Ks32k!D6xOhQVeG^NE{$vc6mVz26Hm
zq$$bl1yZwW-6PWR9`L%0D{ecM*@B4gN_>YPwaAZaX9QV0@SM_ESDP6;t^}(w>|@a~
zrY(T)mI3l+S<!gvl5AWuxcr^0)pjHVxg8b$jI0zk{ahy1s=D9L9zi}4ZNe|-rEguP
zQ`vddwe$6z`Y*lmqrP+AYsARIVd`eLNy5rH+r|k;seuEqm^Y-<G@0G9K#=M|TA6_!
zWVH75B5iuV2SeD>4mJUm6H<B*M+t8k8t<}84>IGThm~pw<!@!sh?}gEPU$t;yDUWG
zjgNdsE9&;B6VzUC^wUB2OC~5`L;sY)f;G?u_a9iX;%Jm0?r>5(foUx$%^PSRlaL9s
z4-Of{gmNO#52HS7<axR{t&HYY8YGX&8d<ea!NVC;d~|w-#I*)Tby2avIR1&LdZ15?
z#c9k?%j=OdVHU5G*U6vAW$aUVIa$xuv8(}B!EExDPT6=*=`f3nCH#P>8X{ZH6Q*fq
zrUN09GWnR4u-UVE_8}`ou-D1j2@v$YEyv_Nk_4gmhH{|ndBGMOM3-G>7ABaZn-c0T
ziblV_!_C#def#WrGp~~_v#w7>cATB4+gQPnUsgDDAc2<iZX1%DfoNnVoB8>5+-RxI
z(sjX$!kCp_K3Vs)c05&O%Ye+nJjpbINh&;(eV2u0wwsK`ivI6vu^33`iQtIP+<wO5
zfj9r@KfAJKioUV>btK=k$og|#{f`{4-A-G--gnd;`l(yvRrja7_s28qKkJMP{x8?J
z{o=*?Omp80?A{JfhfVpnZvIfIIv&am>&uT=2i<7lb*r>^YCj1`hk9ooU9i5E5XA92
zrAlkPwC@E^p7W+x_We$!fUHPwy&g^u%x+k-r3Z%Yt&Xf(x5m_@cyuT{Q{K~Co00qe
z&5;L&W~%P3tEWiq*?Y9uJGtlC*RA5dH+kakSaIBPzl;1w?|M1+A6#+D>OCsL{f@QM
zg3M&Cm-pOx$AjU2{jagT$DFeMrF(er_l|o1$iHwg{f4>Tw`k7F);HsId%Ju1`quB(
zpLd?0Y@^)mO!wT7Ok0WryM16`n&ikwoi}`YNAg+Mnho9dZo4-ePj|Qjuak$|ZJq7~
zwe<(CI-(6L=ktzr)bhXWIgdh`y3ajY`KW)?H(KJ7pSWGYy4BvdX8Gt3iG`y>n>Q~C
z^NcudRoCrD%avSam%Feuun4IQFg3ZY^u%4R^(*X7_YbVN(1_N-Z`FUt+&z|mqnkV+
z!gXt}b)#$Sa7!;IZ}iTHhyU<Lx2N{?%1QeHNVX$`-uh$#Wc7!BE0ng~Mm@$(J7=&N
z9nB?fb)pDjTmO*Y_*j9hllKmbnfNh4SzJ<uw$9;BatA@i(fZu#p!%I~?H7vbhz>qm
z{|8=a1yvP3c;646;&o0*fQbv7(eXr0#k!p=fej<j!z~NRWvlZRCEV~Qz4!m(PXv=n
zAjkYkpyo@_*u;CR<KlNe;zey=URMY|KJuRsCjP@%A1i%((E+7>j0BT??b101KGzd~
zk>7?+^?1Mk#Ml9ZZC36UH<~MMOX+=&`Nt3*mLNH+hrvvHAA3`*l?*@xs~&E9IJxcB
z!nraq<_TxE|HJ;|my2IAPxu%9n1wMwZT*YhIq@CnZ8>sw?i@=-d=$vn!~%&s)Bej%
zvR}f>ePS$9*ytzsb5Gc|irAVX`hM4kLB!AoIdpyDQg{|waZ)*217it_$5)-+UD3y1
z_=7D`7BB?aoapx7HD?ksOOD?Do^d~|p^47Pw}t{081n`QY=_JiV9|=1=SI)8r~AeD
zD|4Aec_%_aPV1k00^yHZ=7hEKLFjy>eFeJpP_CXP7i2$jBf^ioT{o#zl@M>Q7K^+3
zkHxYCAlkY!?1i}Yk5!_~^^$nhoKwj#FLZMr(GBMWaNk)iH#rY+Lx)xR*k?qk%k59b
z`~ny%dBSfyd!x4&{o8w&%`3p>)r`4lTz9*9EP;#I7_&!&HF>(G0|H(buREW7lS3|!
zj4hS~AmWpi*ZX>F#c@Q}i{y|TaQj!x3vYNu^zl<th(7O+eTEFU;W(1;V)R+~vf-9&
zeL`Rx<KLR|o}V92k$3qPZTYBq;nfg!XFT@A9MDaize~EyH`VS4$sFma^PE+(W}=%)
z0!v((SfweYR?Gd{iF503-J+<W1Jdwc^6aa(m$KgcYLC?7==L$QRo~`}+6Tu=R(&KB
zfATj9M*PX&bP?YnTkEPBWFC&EW4Tk+z*rbNGTp07It(m&O?cm|2muWk>G4IzU6iig
z^o%SRi{qP7C76g@3NU})%o2sx57DBvI}VUl&_K+6J>P?(HGuBo?6SBp;kk<j$X7))
zlob6c1YBld{H8UppXNvF2U2Uh>VCc26$S42hJF1Kn6=5kDcAZkC!C4v3QNxK{wG*H
zBxS3_pZrz0uziz@N{YRfCf|1YJk{@E?<r>%^fIpfvA~>;#Uzpc%pnon2{_x+nmpiZ
zwM=pHh(gvvvhiAzvxQ7+@`<~V*`gYBl5yb|i)+FvtcvVpSR&si+pP;$v?}7(_NU6<
zh$TxZo=F0I7{<59kU*BkwQ@AQ;c-@J#&vIb<EMTbwVmeY`o?Nvbn`lMx=9sA?b`ut
zI{<TQ#M4^~v_Wkf>Q-VZ&KhfT=PXzDK5nKLK3=qpR`;ks{XsG6D^wqNKdO1w<g*17
zxueH>u>D!B_O%ZPWY}K{`K&j&yduwv;O9p2fW$=WF(E+0UL?6eZ&!g8N=5AKD0Ov1
zLUGZBx>ioNq{RQD8#mr93C0>T{R<OgH}t%Y-y|DjFOIB=^tvBwj77JnJ(Ff>wS1w^
zH`uh$o{_WcA+>VF*V!t$BP0vx9E|j|l!SMN_pAy}5#Q6ty2S|2R%-<06J39?5dK`K
zk(dDSbL9WAC4`y)&S^CUFV9d{F9GI9UcUhYH60cGu?`K0%$(iJZm-_B&0iLQQXbNF
ze&q2VO--LMEWi=<(K<_<*5C9>--yjqp;{`c?EyrvB#De_$))+RP0v+4c)Pb+zoV!m
zisHhMAix{Fs6{PDE?+ZZi`<*mf_T+@(u1uJBpa|(bYih&Y^1JrFrG80WJ6|pb*~T$
zv(iC#TQGeF+IYSsa#iCJFuP#ffcid5OP}=^`kA7sPgK&Z%Tjq)h&W~274Zlw8&rmH
zXj_K6&_#G^(CYFcw`rc4(F&7cu>O#+9IvqsTx`WINHd`Fsd5&D^pjz>?yOno)5eU1
zFF?N3LBi=;-9a}T1a#WbO@~t6XtoIo$|fN)`o<2ge(SGn%Z-@vw6w1W!j4Xvq7}tr
zY?7zssPn&iq#Yej+>4WEIuF(ca47^ZJB5hL^O610vXAZtJCG+2sOMZN!WVBrOWFBl
z5x%eUU{oS|(VS7NPvlTNQu^*G*+g+0{ouuW=M#Od^E~zZk~!&}=g5RXSMD4M)Hb6%
z1`A~OLqN6YAaZ@fY3lyh?|k=PL7@HKzk)K6ye0?)+BuUvEL9FprHcOM_f_8ioQwSW
z1>nxb*D6oFC9VF{_b&3o(&~TaBG;tVzsT82pZ$9mksa)m0{l=({`jquyn{y4TNn8u
zd80RfP~Pa%|ANKxU-)XUPS!OA0N?`gdh3tQ`vz`E=gr%{_THQS%Pz>V*RJ&TN$>RL
zvm<&5aCP2%v5w5;SbE+Gpad<*O|vzG&}@!GXHD}r;4BKfK@X1}RaPRv2YVxU8*oXw
z7aoBnRY98=N`c+qjP-#fKSofe&aMEgG8}!pTM#xxPZ!qhCq1`q1Dk5FH>`YDw!7&X
z5C>P>-q3G5X%i>P$xp<ueZEV>OFNiEjLmWu@n<V9adOkV9>)t^AcVM)4cSdYW$R}=
zJRZob%Pv9HF!)Mt(sc2b!4KennOniQ@I{7`F;Ik@A!8|!k!`qmi!^%|SX@4FU8Xbu
zqqu1_gwT7VSHHDY1Wu%=KT}Bnj8k{ygYLXx(IE3mSj-`(9XAmGuGS`z51>{2ACRXR
zgs7^^{v_53E~o2U_<C9sK~d%j2}s48d^60*?2re}fitfIivmn`rTDv~veUKi9?F~-
zd>l0l(cn?97;>o=xdBZ?dI_tlldfZuqg}_}YfE>-OY_Ds$mDav&~^*o6&~QI<)tWL
z(AwSb=0Z3#%!%484qL<Mkc(V=T21(kxXU|V@$rs{rhMZUKSxI)V+GU!0@+Q&fsJ|j
z826T|u`^1{dEmz(pc^MQq4AKmFCWL#i6*V{0{54@NPNdMo0>%F=V@X98_msb!2%sv
zT=>!hz<b#Y)Un(t53Kn=0-hIEUGk)PR2VVuQ>gs1D;p?r{h%AL=xJLU2*U@<TLa)A
zcoX%0GYY%KUhgEl0C#8XE{UC1v8!+fD=}P421Nz>#9Fgmj2k*GxE3S^b-_6Wcc#N>
zcf&&3-8cq63lNZi)HnVQs@cUcvZ=>1*mRueps6jK>WiI&2{g1~eg5KlmmCqOHN?k6
z>%jasqydSo_bj-{8Ec_>#9em(j+wT7FFJ0Cf-j8$&`C$_hs9HIHCB-4h`Dv)uB3w6
zoM)ub^&rK#I7#RmQ`9tlNDt;+S15_2#vrwGQ8^ag)h~S}4`ixoc`!FBMb^121i}=t
z2;Qr<CMjY`DtdgP%(@AvR<`NAA(+6*x<E}pc(HJ-%hLjX1w#dhy(Uc2nHTc#*=eWP
zRe+Rs<3D*fs@OdF=y+^%TEZ1bxv=|EqTes-M1iNEpDD%+Ur&F`XtsHP!LwyUax|Ih
z*RYJB4k)TkC9&FZD#-*)SOB6!pi2j=33hvYYb%D3^9}Y*=oVm7VN}8^k9>x|kdlf>
zAHX&X-w@~1pjj{@Js{duHmpoT-$7HdX~B*^MvonNY@Fm7xwHm%l`%;Ol`u#U#ncjr
z%Fx2VOLfLM*NKflsBx#|ul|d#EW6H5*MPjyR5D}zdexQlG#43h8i`TsuA=hPJrFuC
zkb(m2IUvVbQEgthRQ9~Rks?4n<;H?)<}!X86foAlypE%Zlr;rmgC(1xz)}R6h(7}_
z%tXZZ3jnw-{$vPTdEpIDOX-ZgmF(6UmmUy$)-!?oB!J4c;jXG7Mo!t;*`(%=*W+9!
zH!Cc%7mG0_<ZQ-S81$`3L|GO|#b`2ALWvcn?H~}Ja-9fsFH5?cf3wC8aMW^t*Jzlg
zU}Wx5A>yvQ;S>~w)za+nwZFTCX%u}g@<4T8Fh~|rhjTjUWuql~MY??MH_R=dOss6l
z`(~4vVaaKXU5>P9c8?0BFtY5a1JNG#iM~DWfwERXjUufPQt?6tF_AnVa*!^0R6a_9
zS&3-ywJEkayzK(AHE@*@Ccp93pU^xHxVPKgxs-F8I#VBVj&Z+E8Afl(E)_L*I%*5a
zR8Bjmbcou}5xGr9iNf)lMm99E_e!s3c*mr4qtTS{5^iCvob=qtoeeUOBVFmq^InVW
zf<elB9IOiw6_6H*JehZm`wkB?eHlReJXR>nk>pn|)zu`3!8Mfi*3PKWl&te?0rlh|
z6590)nl$@v2Bj#uW#F_)0O=76T$Agl=?CK@W;LR_11itp;=@K9^QchYam<xZ|E%U>
zT|C(GP)a$I8U@`!#B-w&s|};jNYiH#-V8EU;7QBjBtTPeZH>7-il6g!FUu${MpnjC
zUqz<{G}#~{C5`Rx_LKyHr{&#vrL#b=>c6zMl?)VJT%WPjl$$v=S@JsdT;NfeHKr0R
z*y^iZEg0w7bTZ;#!mmy8RBTEiZwU?SE?4(r<odka)_D4a?Ka0fCf9!2EN?`O%R(9+
zPlZt7s7xsoiRn$NCUK%OaSP)=pQFC$-hhhN)~ykC;WS`$Zx%D{A9UEw7?=q`%b`XX
zQ_`c!W8t*~0OY8*Ce91dzb=}RR^ZW*B~<}Cw!=^<^W45FMB=h-#nU+7DSy%OOe?Y@
z8-V*Xir?&Cs`OBimHiU!g1+0M?+V6!Yb^l4WJ_UoSa)Y*xfl+}31AE@u<Y(x$quaN
z4~L%!*@7Y2`83k?CiJ;!43RFINM+R>3xymW^lIbYUN0px`j#5@2<EE+Np_}dhETdh
z*OxI+%^l_Dy+(G(?vG(y-_No_%Kq56@(+K?+b1w_fbOEd<m|HUx_Ehdg_!VM|5!p&
zKd%&DESdFfFU2D4`;>oovdh)(IqF?nyNOh`&7;NN5D!$uhwb07YG-=qUR+(V+(Yid
z=bcNd)h)Y=WV_ts-1ESI@l3xbKWIJnLVB)moonno>V16ZO>57?)8{<%sQo+kx8h4;
z-8+~#&d8EIz1u$qhPL7!vJf1P3gJX?WV|@C<V6QXb%scMP0HQk88Kp12_o6~ZCijO
z0=4h9tb_ft`$T!Daf&_JD=&Y{bD+xZv9{yA@Ar4CHr<<YJ0Ea9YM;rSuy^+S!oEu1
zz9D<JU7MVdJKXeykc9&uAK-TWeaV<NJT4B4f${WLW)6#o#RIl6chnhQD?TWA?pqrW
zmJ8uNCqC}(Sc$fm4)#0ue9pU=d~U#e(GR!0Jn-^L@_aa$`}e2p9kDlH6#q?qdb+YZ
zH(RuglKYKt(B5P33%?|OekK(C;g*q^u=pkWZsEz<=$jTIofYSbu&c2pK5xzRS1*sp
zi6m)Ex$(wl{~$jmUP=b>1&a<`7?4W5vhSmoynl=d93(POkfo$DDo$}OQOwq2W#6AV
zT!EJNN^%o|Tu!&YsXVi{&ZzyFGk_J8NWj>P6sfBKR5+{Z`U-9ps@2MPeWM_*BDi)O
z{v`a@YnSBk8a3B{();fp)rbur+z#lATsr6^e)@-IZZx5sUijl8Kpw#42*9Lu`}~EG
z%rj?KMz&tK^FIhcpYgSRAg!MZmA1fPYZmCttd3jTD{FJ!*x6&zlh(n>S8AN`*dL2E
z|KaJev+i*Q$ZrX#s?D)kP{HKH_PH;J{;^*xe#Zg^tz8b6gm(}?Zdd5djUTvwaqFJ7
z-sdB8O>jIXu8P?w%d6tBRX`5;_Kz0tu>1?ZKXXomGtrac84GYpX$H7AhMyRlEvzXp
z@|ETOpEQ?ud^PFz3fASgZCzuJqOZLmZ4V^y)%(P?WO=UwdE9wqnz_IoJwoVtb&Ef$
zE>a4u$8Yk}LXM=6i-Z+JRa@>s^7!WtjLt)n1vni`1lbF}AjapvV%KuC#f6_Mx-q|0
z20p1>AS!BnW*S~4s>ab8qXqawx+G#lQQDa;0406YTN2rbjI84a3Pf8cAZBux*#CK3
zceUl2@BZw&y)12ZqBpDfub_-4oVB?k2;&oIER+}ZqBrJ~j_!Wv&efg9g-Q14yjpJc
zro-E(pPLWi+zC;$Rn+t=SuqxYc0S_FfreO*`C@G3LT?i0p!!Xw)D6t&=RUwC?mPg_
z3%tl`=t0lx0v&=u00;@T#P3K|pteQTqV^An{g2$ywYf}oBC>*su(I7EKz&5VG9q-a
zjpdme|K!KBKrRGx1E%`R<))lCke!U~Mus77k0kQWFKL7ij()4Q&7nnh36-cX`&79(
zKChy?<#xqGjMjRZW1DVi-FmFoXiX&jhO9w(Bon1VFK6eFs*1MI+PAWfzHr7Xbro_&
zd<7CKf)sk#7zNJwqu$(_Akm&NdPK4!(dSMV5fOL&vV{Z#LE{91uN439TQs+E)VWij
zX@F2iZG@-?^CKQY>Y$j$;@IM}mimwwKLfZ`$m}2Al;YteJV1M@^Y8qC+ae3CivC}#
zWsa?o74s`rZHqWKJ=;&`k^f?RZP^mD5y10>e-|3TFL)VmT0(lpvs>=3*+U|j06`C+
zd78AlR{I^{^7vG+F^c_p8B!q`sfHCdRJM9<{?fceivp`HB{C{PQ~s1kv191EkJ(#B
zSNo0D`#?XnC;g*#=B31<CF9v?v=&ArR_lx7W+4OIt8L%@*w&Y%?8MpE>NaI<^_4Ap
zY*XU!ZyDXp8xkP4TZ`nfz^ZEuRWfvL@jX|&@DcFP8iCyIApxptfu#xSRw)gV1Bhpi
z<Ryc|(2gZ7B5PWcM+#eFZ^ujtQm;?nkVf$_E_GH(iA05S0*rB<8`Z~W*vphzwhKNZ
zT*lX0{}W>m6*9+Sn)E`L6IX3}Rvb%WZ&}pdYXo<M4Y|asT4=Q`q!Ke~8MFo1;E3E^
z3@w_kOsfSCdPcB;`^gpsI}8{Nej`I=kQ@N5mGh+1(au*|bpXGKA(BkVexrR)su#9s
zzm{qjpjd3w&ao+nc(H`E8W)<0K42LH^%De8u(voTQZ1U+w)ZJG^Fn6149hjL37gm@
zwCJA4%UL7XOf_(jjX4A7z!?o0LQp5O@AEXcs6f7DYj@hvYZ;Nsysq6>`;kS{XhOFt
z>BQ*P>ZinLiXWEl3SWwKITdrixP>31Ra$nY$?~PdZhJp_&+*Cdq%$qEo4?!$w>75Y
z+LEX=%}f)1(rvz7i8mrG-kA!W<dXBo2no?(xa1Soqczg)jGzg>=4wKmXFUk~%7XZf
zxfiBlui;9AsK7#^kCG^|yTH=~+NqqpS4+VM1N$KW$D*G$*>H1O6QsMWPwcCttrvs<
z!Mul5kbZt9-kthlbdN7K3PzfXkSpL}H50cchAQcELKx9KTbSHEV|Ti2f$IlckSwYV
z^;j!Mh1iI2L#`c@x)*1<d5S6YGL;<Nxaz(7XGGUu*!LIHDF0`;nE$0E04IO#?HK;Q
zmJq-vzb8rX$sfMRUnm5ycHdvZ3RTtlZ26s0$=5!bp-<oG)#!L6dgmYIkt@II2O&k4
z@ZWohYj3XnU(bH;lmE$ovG*%?Y=C(*;4a}Nq3ju}07d1cuH`Q!I1NFxS<z02)&~+7
z(59iM{sQ`yd6(@l2zN%o*kyT7+SUxV3ku;8h-)g2o3zjaMUpLso09+_f?D*01>j?m
zGcBP?uCF`=H?O<HgJx*H_W5@!rE|sIg1r+%q68HI#c+OA=h?j=09{&m-ViPugpHpk
zhAfMCT&!W<U1G#yR3S^YR{?1$VB>k3kyccyc90@LC1^R2D4%~^!eCuZjr6KHIO{+B
z(?2>D(~1;~vT&BFe5Y_EA5$r$T3{1gDsRAhar`N;Gv%H~F09Z7^?+cdgCsf`U=W`N
zgrD`6Y=Q!DV$?Mia)b9_Xv#5@1}%NV7v2RZNA=o4Msd&<&4_?MN{|*ZGA|4e8p&S~
zP*a9enYe;XEiw2*<4-<Tuc?qX$}qUafIbyMQqAje-q0lOCjf)E|COKUv;b9l%M%1c
z4l=2hMhkkZ&h?1r<^o)k7ngbKMJsh~rE07`>YU9VlyI+yS(23EiKha-0$_r#r}Wnr
z%*_2A=Q#VWC><e+JEaDmD!vvqI8t);$n6xJ`ef*LRSVcJ3LjMkhyw$vRAdo1&IeI8
z!?v60FaK;7_w~6HARue(wVh_$*O;N<x9R|(Igj5{;KfQND6ii?RF6a~SbdC!THu)(
z{CF*nm3(NY5OBueTaqNxZU6^}Mq+i-?Lsv&T9<B6Ao3YoU9zI`lP}P8>V*x#SOpl<
zY;~ALg?u+v-;CCIFTi<}e-ALLKI2BJ-#RU&{*45PggTvvj;576-%yILzShl1aTL+D
zp=%>C7#Nty+o%MW0JssYEe#m3(Mff_8dx9-G;0cim&fE3d{faH%*(1jIxjv`?@~uL
z^a!hM=wH45-F!eSxxzT;5`aI-0anGYm?Kr$RP!UTLjfao=-Y+oD}eO8F6bmKn+L8?
zsE3lzv_Z>DG`+ZT=PzUTe5z^=wJbFw=u9#1)W2?ETri#y0iaXMa0N&N2Eh++)NK_=
z$B%;TqK3{xP+C$0^^2+^%rro*6kS?leC5||O@dTJFMagK^6F-Qr_@}jeDFUns*ug(
zF}mkcB-WL&VPWL+G(3ELnOEO-3drqLV*(55d6~&$GQ2nPI<O-RO3H+MV&vkhU;914
z7Y<AL;Re_0hnc1X26IU!kXdRVgDBh(nidFZ!jZgv`&Cpe))`SuOBqcvY9gR8?vK8t
z7UeS9tsnT2ew`$#+&P=-2vJ7taAaZ<X$SSFPG6+Hm$nps>G^DLQk1F@819sio^(Aa
z*>z=0!?xf0H4N%WmOE0`!8XrjA}f-zs!MGo(Vg6BK7r|&haROGqhWv*l5NR)!@LpO
z1=3gTpgOlx4=tA11`9tw*t!yXsh2g-Y1E{vWkDQOU9mIuYOvx5&js63Ad*xJ(vu#k
zB)~~2OGB3obgyg+IwQaCT^acdz2B{N8fa6Q&9pLL^jwCw{Lr4+OvK0vjB8ft23vT;
zt+F6Uq)(=%ktX4s2AM`#O|F3*4Z(-IR%Y5-<T=yVp1kkf4Ru-WuSRb}=K##UJILgX
z>}g+BGdmEbhB~^)4^`7hM;A6aR+2Y@D1%KDnGrh1r3{QiJHsZ@qGhJA#?}A)0h;Wj
zV!;NUx)(RlI)g(C9J`K%k9q;OU=%28rwUlQ76o>y8ee^&u35}r`~i;)_4C$?Hx1Ro
zzw(b8X4pA0lF^9b&Sq-!(&@7SsUv5@XD>_h(x^>K%ap4}E^Q-$PCSrEjDp6*C!pNw
z#eAWI%0sp#q(n`wFzsmUYyWFf-H<H@>0l!N&%-AzPsN@y_D<WFP~5f&(2JTE>$<AK
zR4A%O)EF1T<2*yg>*O!X4*5|vd?94^mer%4LFl48J#0+7bKxBxEL^HM97a(@A)|;A
za+hdd+HA_xLx-#!s9?2iPsv^&t>}=;_q|It(3c`z=R9{>M#CaW!r5>{&uw@)Z^^69
zNcq}R!>cfOi3$K&m00y&EIij8S<O>@xlGKQAIGWz*5c;)L!!|8pa_=+3KNgF3tt-u
zhq#k0SQBB<02dz)K`0O8uq98;J8C>BQ`-xaD5EFs1P<a*Y0xV>!+Lel9v<{Y3<_%(
zXR9Onu#CX9M_`3Y&P{|WTv$A9S1-$%u)KF@<m#i>EyrxzcOoYkl6h&Ti1PJ;Ubgx&
zEvI{Q^8&J!q4HYsz2*{D>vKlhdS4NMW1=X6r#yoCVBQ&EM_@}vFj2${1ZHA=ZfDg0
zr#<H9wN6SuMN9yRYVgCiX@AvDU62+dk`DJ4jF7iZ<=^YC{+C~$atpmEh+FZ3zHHtO
z|88Y4s%2UqkC0YtO+KqV-96HMVS+f@+QbIsx%0sOCI4GvGkE>&yJrd)=f|TD75l?-
z1fOP0;cKBNr-k)YNDzU^*||Q&hAEdWMS97&eKxfHT9oms-qMU#^UCS@bpP{_1SSI4
zNb_TnEI${SX?&X`^WVy#j7nVgNh`x8_NFg|XU(ci%g#ZW`qn{-JNn%}**aia=TMkn
zLp)C}AngX?Q?HQ&<yoff(Z$xhAhl-8nVcz!@mFg@Kni!y5Tp0+W(9PiHT>_pk}!mq
zLXQV`%(wyQP-#3`<_o3`ZCR8!3}jf8UY3yl67{>GtFNQpN3EI?K#Vk8V;<TyCdB=0
zXRr2KwM?gc;<x`}H#y2Kvww&xa&N2(2*d%<gVWfDeU6S$MyP};{aZflqw8NOY-u?|
z9^eYhGGn%o8emN{{Hz;<TLRmo_n8Y>#;AQQKMTI2H=edBm^l&A;Sn?KicrNFqYl_b
zHX>ANm5jQuQ%1~8=@DC&uKvU0jcFDytpDO=fcc0J+)lGerXW=y2DmCyT*!ewVQ{mq
z8_b3xSQGweI4v}G47O;6EkTrm>Cj-*A1^=Bu6S5z)JSv~d9<xV6RQ7fYvuj7VSJ9_
zMMV*4Rn1d{8j)UdF_IaCPfAyR#?2F^x`;olnlsZYGnksAAT2;3`q59uqfV*F!v+ju
zj6OT3(5DHoGBA|jYoI@Yq89-~DT`BZ1s1Q$1yI6NUQCT>8IWPQ=T=D{nTJfOeb}yL
zf{DnXc+80%bI9wel=;=pch5z1*NDt~_wgS?kd*9%oe7>AL5EwEXfM96Q@Up_U}dy}
z8oSeOU_f7-V>^rIr7FW+Z<UOK&~lL|VUXOk)6N<<vtY>~6E3DCS7habmg1u~eXp6a
zm^2rmJPd}_eobW;`mLKA%BVn$(sbG6IYkz|tfShN>e5*1@i;mkC{CGu8q1E1xHc>N
z;FT~5$7f~0Q_Kj$918)a1i+e%pvS9;!R?`Gq2Ec@4U?eOid6BIdoU+gk5n(iV8g_;
z(mC7AR5&nGIb=%luiqDt5OYC)j@@F-=DF;owbP+02g=-1+o0OZ<w%)^jh*+?U%O`1
z%KSNC71m{`>+*<Y^aQcsLA5gzzzQ3g7ed!IB#%tY2=3Sf$>6X{u%N7GjC7Zn{YCF|
zteQ-F|MOkSmhqmz#z1?t(Ro;4MD(N#;WQ4qYX+gMnrE|#Oe^hVNve%hM6ktW5ug^u
zT0qH3R;Sj|Bi+oILb3?*5(E;vY?duxLo6xIr}?IypJpMS%ZQ)(g?ImhNzq{V>HMm(
z{FY8|`hc2YH3dRR#&ZUzU{Tsz(x}!1GKCO#fURJu?Z%18fUB_LTjh8^n4r~oSl^>&
za&qN?>S$AKHGwx005ra?Sk#)zGmmG^1K+3#e1o5C=Bxi~+y9R=u(x0iAdx?p!S&~J
z$sQh8!MrcWmp=Z(6t2JCRo)@t9s#&a)jz}od+k_Pf+1XcrF1!_LKq1TG%}sfBs>p^
z#ZgLfhL*<wfA9r|A^B4u{ovQHUEldK{=v__|Nb35{{8_!{O-zs`^83gX9-CW<1|}`
z$AzIxCTaG?IzEk-wjv{2->Pk-$P%gLDr;l~)i8WnS)+%iR=T_ZPFU|6QWHU@^MOJ-
zvUnm<wK**{magKrn{U;MGR8!`a=mOfehITLpYSigue~G+@7y5BGz=&N>UzpgXN+||
zk_}xQrfv{yQ%Yrs&*``nS8w{ee5|(9`8{u>Cml(fPbO+b#-Vka91SU_P?3mjZa!i~
zJf5m+sl~b~t{RKX9#rM67e{GSD|_1GBS*V(-@_DCjU?r{;OyqQbKQYF;;KgLhE&!x
zQbiI=jhHbGFM|be-pUNCiYs7Ay;v@}GS&GOXPlXVwj=4ywH3Vjnx`oh_?eGw<s<G9
z#T1kBt5<Br4I`B_Hk;@Qc3^QW7mQ9*#$1S3+WDCBNy$3|sz5Rt22d5Z(YZ|AX&qY?
z<;r^>)UvF>z&mW8xhIXSrk-jh%sb{U73_~MhOh*nMFRp1n1vp}*|WN%#`imtRXuqx
z*c7EOgm^|cL8{o;0-P4!zTJ}d`Bf-GX;ANr{8NwxJrK4yN<q;^gig^^H>a&k8uX#{
zm`2CKG?G=B+2GSa&7DpZqo;4gG^teW+E9VUG~Y>^QADGI*JY?B$3xIXR4s)Q6d#k?
zmG%FwEDJsa?e9)8G1C|+xJFeu`803G`~YhxK%`ob-|CBNzi2J`O?{QuQ;}jmv|QZz
z%^{7Lp3=ViZ{O|GYxQjk@d@b4YnQ>5#X@nP;R!h!CJ;r}EI@WT6*rr{QYOa>88IG3
zs+xp+bw?>N+I%Y1BiaSvax{ScE0=~;)w7ZB>dGL3ZXVk-bRk?cxFgq&geqYyRTpbb
z^`VB1&}Qn*TODC_KD~x2&;+=qPPh7=zKgHC@He!Rc2vj&8BhXTw3<O46FaTyZ3@Sx
zOh&c5Ol8`!qs}nE9uZPxa4x%XV--MB5Ry)EiurR+V)=>sF`8^R3n46(WOX6wVsI|`
z=^{~t%EnUCqA%g32vFIs*WR<GQ}_U1pF*W6uqJ|rv#~N|TxDe1u!M#_+=Zt<6|!;B
z4eo<orwtt5Oso(vQsONTX9tn;3<4MM!X9)oBbE)GhjHh5bZV8nx;Ty~V<3KTuazC~
zA)$<VO`YepmyJH|L`UK&SN%a5#9F`rq{^+#F&WVg5mTH~f<6k*GqUik>zOEurdVs{
zr5CqB)+i`r62u03fjpUN3yD?VbTl?%I(?y~qzO_5$kreH>b7*w7_Aq!Lb}11o3m^?
zx&`oXJe8wDYZ+1^IzQpDsbhn<*sxT$WiuNZBMFWe=>h4Cy<SBEfvP(?6KR?@!Vw$e
zV1Tu)Di}z%<4s$$3C75$4a;}orRmxEeqc4a5}5nblT~KIofwY7zNmJfV!2bo|6nCi
zcL{gwn$e^qVTN;Xe&e2Qyf+L^nYBWqJIvom)ACFvyix)bF)Zq@=2IRTjd0%Zzx(BF
zd<uf?F(yYth$Wh<WhqG9Fa>d$%8=pJcOO>Sa+uy|MUIDZYl!mzw~{UvbaIB@1eHQ*
zC6bbB$3D}x&{!)ej6W94kv`|q!%zJuVw*j6S;a{T2vV1Uh2kWJz$;dd3T;Ya85A|3
zfGJa0qd&G3pf31BA?s=ij1%Ly8$syB)GcPkM(F8m4>0Mo3B@ESh#mm1SFe9{Z(e>v
z$H^%~r>&`WkSSy|w_(nkgk-x6rG4Ibm^IM$+ZM&rmxxS+j;$=4ysq)IJV^pmy{c0~
zL0X>ja5Z(~LFW)@HdthXzHG$##5Fw=te~pH3XS0Qf?Ol5qBc%oM}~FCaSe;g#5cS@
zBMX@waxe4a7S%Da%ra3q6A3dgHNH0Wpq{{IAVT0NV7-j&(+UwBnTey$=Xsq)Vo>+2
zy4`J|R2uLA!JPHL@h{d{v63Phd!+L)dyVyr5gbYKS1<qTlQ|Tn=8i}e_q_9g+{{Y0
zcU)w1|1P|kUaSw=A9DWCtvTD-a}Qydli`E3^y#9xt!eq;7ab#4vE{yvzMOsJ=`<I8
z(Q6Ml#j{rHBlhOal@YOGEv);^b|o%Oq$Ab&=j-cz8^h|5_oeZ|O!(#Y(89~>ZKrq1
z*;u?R(f+v{z8t!DRZAD^BAE#v4%^;wmke95SIN6eeA?xBCfQd<h_;^y(^r$WFGQtx
zm1HAH*?<3kJrsVRJvSrWM|B+Fu^A^CJ(9g6&28B2T;D8CaJ-hzIkPfuWj1K7x)+Yr
zXJreNaN}uf({9Z^-LBqNAE6^F&eQVe<;cr&Mz&_F&we9p4-`M*ZF(agu58#y2oBnO
zcR3uaobcocPi!CX_w?;S<bZS=4{#XZ*NFI>ZM|Xp!((atgm==G?5~nUB`rykI#m`_
z+MIK~RFf?05kx(#qT^rv8#|}KZISr_#F<N6c2+e|o~gJK&Iwg1eQaycx2+jYJdPq}
zCgp*XUc-tM-R)Y;Cv2i=WKlX{p2vaDQcC35DU2pt<wofo$T0*x4-58ofAH`QOGy!+
zNLDskmw#5Rj}u~Fr2J?~&aZdo?w6*={(um+2kabL)b?C18JoL1EX3Bt2iz0A2P3?_
z0TKaZp79_1eLx!IwlbyW7~kRYd-4pBLv#Eq2SXe2sKZ|GH{1uJ`E%B<m|D5oy(ird
ziy&%DOCplo6ShPNmiz&|EAH)HxZ=t~qTD(fA<ec6$*gCKYd3v$VQhX+>VL(N<Yd`y
zZ<LNYN2J_;)PFGrpZP}fwgs`>JU-a!-oM^^;4D&SX!r~Ns|zM6Q^?`&pQ{Ktf3-qR
zhy2xN{<kZ(HJ3xZ3%Fp`1)G7NkOP3}%P`xL{J=3zI2X264qNg$b}}=*tfg>bKqqwS
z@u(?Bpe>9=)ugEte~1IVoo52kv9b|n@Zlv9k<lSRRALEf>aqDEx#B5IX)L<1t@I74
z`wu77y$1RvIN2|w)<-HD=v+!Aj85w)!mT1mrZ2NRUA#1}mv5N<iCg8E&@OCOY!4j&
zJMhshg(@wRtbwa20kluJ_dDB|7z>tg;ce|vB6^m%ux;6l4u<4Oksdi$;<0D*kD4ui
zwM?0o%UICrprcqtt!*Wmhf@I37DrZZYIWoKKg-HM$=!Y1M%Ej`EoHu`Iu_-}BZ|Lp
z+dT9Ypt4KzN-QkR8)<{+GUU@@#Lyh=?$+pR^xXXPv`1{)0oow)P*|Xuw^;*n3p!wD
zm(6F|t!?FlaxMd*p(G4hhH*qQ9}G)q<JD$EC6RaGX0Nx45(`QDowKQP`Bq5<OXJVV
z^08Pd^rPs>$wde`=8>=hqsNLabnl<xoAP$MF_WkU>hH>vBWSgMkyya}><0^C!?F(L
z28MY!p2jS$`(Q90VZ5~i;H;sW*6t8)Fgg3&JQy3{yo#VUukfWzZ>Shw&LoiD`yy*}
zQ{f|&m0kp!;1?l#3fs9A)7eiB7tySO2t;c)k-!B>Gfx<`FM2ADRZc{NNwRqRFtM7x
zLRZ$rvF5S1yq}~X#LTq1pTvAhpi9)Aa81<)nDQ#|z5c4J5tS*s#SMS5E%NdY*b`!O
zeiY>{%Gc_irq89dU@B{Vj6KF>aoG0U);zX+A=9``nKA);kD7EN`GiPJLKxw)ser;B
z48qE;2@ys6AMIxea#GDE&#H?K6O)-=wGP{{sL1GwUqO2>Y8cD?gbiZ|E!whIX98Jf
z4cs8g5zFAl@UE`@x7|ooB3NhJDiGO&csjW@OMvn%2BEYV#?16J`|X{Ua(NJl*XUJ%
zDwSQksd?L`q*f)-CHHtjBi~C|D+!&YtE4d85TKutqB5{V!>c0Q>v0;SF%wj~XL0OV
zQK~BHT>r6ljYi*Sm~}uaGR0xJZmT;VIy7q5Cz%gLJ{C8weqm**-5#Ak)~4h2X$J{S
zsE#f6Yo7~K2%pPlZ~GyX4>P5g+hd}k60gv$0Czw+DMkCxY{_^oS{2Q9+R5j)A(>8>
zE!hzAeG?UJScH@F_iR}li~P~~k#44=I6u=SWW&y|p=t$j6Zs}+OEY<*IK$196k}%h
z{<cHm9PO9B_2aBv99J!yP?6Cf8i)7}0oglPM5X)>%7{szn;Vxa8;Wz9?tI*}K#n0B
zu^L1wi^U~6IkCaoRPM|mr|hU~zO1-ZqJmViUu~lStXy|>X&^0MV=+q<rFP$^x03h+
zK9KrBt2vr$8f;0V@jX193c1X4GazUg0mF(UdDLgLUW@U20LQc}{L0Og@JVR0{K_BY
zk#!k}EA1cWpnjc_X3u;8>Mc(#gIjhUZ|X?D^SC00vN7EZV)Pna0zsk9B1*T(8mk+J
z5}mKc)hE92|0(_GuPI9RS6~jkoe||P$wTsvqI5sRrV9V8C|&yd^ncu08siXPFo;#U
zW;f4LUn8tk4GX}4x4y?9-hTIvZ&>PH`~RyuwqhRtBd_n}Dejz$gCcqJ(vB^->1m|g
z0%g|OZTLd2wX)HUo(^r+`>AYe@uJYvw5gmNfhU<glEisTdRP)F$rAW`#Sy?p895bZ
zGs+QEu23GwT>}*IbNFEmnbBVRqaOi^>J*>aciuSeB7;bg3@8A;M|YER)VX-kzyl|3
z;2d1H?^T)0Mtr9lk17BpXl#SG0kEX{>&nI7R_Muy9=%ncMKd!MdwAD%0wYHD;T1V{
zCRVf#Lhl$ll-b80bkZ;ao=}%~t2SUPf+lh#{#S%|s|C82r(_L14>&+&qIvzk8;B4g
zOf-WF0X_u;A({OlLnz-6#~YBKVMsh;KlF_bs3It3#LU2*wP0Q~C{80#iel)faH<pd
zh~04<U#pxr@2RS4-lrG0P+QsnUlTxyxr2{Y1CMr!%tf!gIxX0ZU#<>R{=0JbSe%m~
zC849TnI3iH&P%~cj#dWd8B4V%zf$W`VLnm;9;#^xvRZbrOMFXOg_}{4DsN+v3ciO(
zQ}(z_fD6Yf1@K7~V9{hHBB8NxhE&q!z^lw^nz~mxNW1oW4PATbj}IHeteM(K4#mT<
z&iUj&n29Y57f=9;ffM;DPIlIwcSFb7bi_i89l~KnwmTC*GDo&a#EZD=3x-_KHz;ou
zD<CBBWrmc}IMzKJqTxO3AWGP*h}q^Q%ns^O)_097#h<3*T^-a8RDv?)4R{=R1H>!p
zG&pvb;@G7Wy~AP2Q%c3oF__1xHDgy&Y)-`XRBNc}gU2aT=N+sX!9oA<H*kEX)K}_Q
zO2$6~)~Ua+1&YBX0TZFWC90#+xKnLzz&#tFIQ0x?s!rBY?j%&fXjx@fdY(+p4Lt>S
z`uZc%h+KMBUIXz^*4MFGbyl`dnOCfBP*6Nr-ji*+TQHc^Rk?%unioXB48xw=aE=d<
z1gB8oOlLSMQ1&1n-v1N4!OZ=rp{omFpn1!gsM8qKe!)VFL3J~GHbCT|0;~uDtZ;0j
zpOHEYyy-N07R|+;)aV^gtrWnR2|;E_HXRKcwIj(Q5&;`~QSkHQ<`M%kPWSo?H_<s$
z$!I;UzxE$~jPwX`s+bbMHIb#zMfEJEpBgS8i<&|i3!vkgjA<GcO4Ntd5RFC=GlC=z
z?y{?34TsbjZlVV%W0VL}K+(On7@iIxITHWE`H?1l|D<>QtwtH0LSf`*sv|<8juEbL
ziO3?rcBTm&0;=t*sA#HAf6$LqOGlMXA7%iv*$Q=Wk$;)N^8D?_SUj<$Q*p`=b_hJ@
zHk~(+Oq@&&_y<G_s1ZZv<EZ;!l5aj@=LXu9_P_Yesdz7$!XYNA){mOpw(T>EG|bdY
z=}x6@N6Ua1s*XeHKw-Wa4&@a981lBM%XW-5r6r-8l1G~C4#T>(uY1@$(}&(C%ptm~
zX?cQR=poNiOQgU~Utf5AG|hr!W@4r|jDaE$Al9Uv0MXRNHEp9aHxrerZsyaVW!gjJ
z6Y06IO171wavthRMXUIZB=ohMZ+k?oB}T+ygkdi!nhbWSfoG{#c;oL^h2hb)j5D8(
z<(ny_+R)rLh<(&^Tmf}QW_%^8NCEPuH_fSV<m7ypni(4|IAMk-Rnd#BXg=KLJV`z(
z#+Vgsi_nAHV4ff{nNc7B*l9RrJ^9N|{dl%FquNmoR!wfG;_=GkXBi4IW6V3K&+%}{
z^M|@|Pu=Go&oc_E>{3}<Nv~wj3;-R9Ml&|ZJ~K#iol4*k4@yP2o)p^O{%Y2H#KVxt
z@licz&#a3mK<3KR%ll3<%@Bg-64<8}k0kNcIx`eA9P2z61WpA_Dr8?H<3>Y_)wSX9
zjCXQCO-T&Jo4hy}@`R?fMO6^ont@L=n#Rhi;(*LCQCsZw7$UK}a&Mc3vNJtmsF?#Y
zpcQd9wKJlso!u5)tGq~+3LJ`sT8vp{;=KcWPFXBwTxD9@u&$~>-&ezo+Q;cUK_tg4
zS~j}_%!{44_q_Gy)mOaA%e%`(aGdsVg4SJiS`Nz>QhrZ|!?)F|FRzozp~u<um`LJh
z<F=PB7$>~*^o`NlAah15^K2ZZOEww_{n9hNo;7!5m9)5zkW9!DzNogH!~WCNo9)PY
z`l{_$kJ^=?e`#$W$lZMN@HyZ8od1CHk;>4`Up{ABLqmrv!*@MBG99+%mwSf%TjM3C
zYW{qT1e^18+bjP|>tSh~8E9B%NV~RV590xeFT3TD8$Nbmec$#yBZIl^-XS-Fj&zfK
z$ST?!wk$q1@UmR84>k{3(U)&>iklwb=5%w9-JFga{V#{^%ZdAdADtm|*g1}BU1r&>
zp7Qfg+m&N--zKwev=4~dYIenClxv5a_JU3jgxqkVg?3+a@a70;Y$4qAYoID}A&jCS
z|I4Q;R`JEUIO?EAFw|EyHwO;6ZF$)L@}+cXpf!=!&VbF=oPU#+2YP41L)Kxxy;#2a
zuz%~GA6L<K9gIpuk`x_~mK1!2tN2!a2nA1#5J86ohKnGuLO!AI#tl|Dl2nIi_$AYE
zOzI+Mk+#+SMRHAmC^*FV{i$3N-@76g>s#d4JE3TRZXE!P--uw(6ZN?WL#zX~trh<1
z2LX`^Uj*U#wqwI|N<gn3?YZtF-mKZ%11TgovoU<m+UG!y@t;{}on75eGSKD0k+BW`
zM5P5FkzCru3w$^pmj}b`<^o!Sy|?+#5KVg&zs|F&KQ>Q#O6LjmZc?<*PC3i{r9|)j
zoNvvAeTsY~D+3QiH+xEatdk7&^B`U$X9vG3@p+F!W7#O3s}O0p)_+`(>zW|8-~9#e
z6*IP;5WOg<9e6c7C;s;Qh3+RmWp1wZe%OBBqJP|!Df()+)uVgAbIWg@x95lmdcf{W
znM2$$=qawrJZxRSx$aS!U2%=;9@1=b*&WuYRE-4k7rLoY59oqJbqwOcaMOnkLZ?sl
z)y@j$vPFD1t#{?7sJ3Q;2=Ti$xhZ`dbv%2b>j1;zF;XzR4m$V}3A6j~ufuJ<uls&m
zl85k%Uh;A*KgEPEpAb~DL9AULH&qB+@lCsLdB^`beZL*<6KSr`>#&si_je$MXaqQ6
za#5*>)qsu&$pd&aFZ6+QRCQ37c3zAx=CATZ&|1!HSRUOhdQG|E^~QRmjr!awil~H|
zQX29^jg5ek)j_Awn7Xj((Vk9C9jc(ErM?T>${csXKgN_sELUd#^YcIu97%NC%kkLe
zAtjFW|CV?D!Ev1DecxTI<+BZ|cgquIea6sxFIMOhVi@AY*k{C1?!8-x2kK}7q|&f)
zrY0d;rCi4{CA)QI+;VqsVID%T6e*@v$DSC3QHRs9Vu@lLWyUk+fxw6wA<@s7s!b-A
zX{UBOo)JW=uKL5Hex5zhregiDWaqCeiTkm)`|kTb@6YG^exK(70#X=6;B@GW0{PK`
z*Ma!$xcu$q=k(Mtb$9om9Y9F~6CKKA|6Py|s`_F}VLJ%(2P_K!2q{3w@$U*Q4vzb3
zH&_%Qo*}}~*uWhr#iCPN_F1+aD^dY$t=Dq%R6rTtoAZF5#09AJlOg{1X9D#kv?q`f
z*SN_&uFc8L3i#9yt8jPRba{KdO7?K~HPw=enjtc?dPK+ARoa3Zrdl1oF$a)$PMxhH
zVn30bH|UyJH`=wq#WLhLm|bU>xeZ_*4<N`^n6@nlA1e-reGC|oHTIMpqQintDMBr0
zAdumfoY2OPrJs(v<DaOPlBqdFh$K78dAvK-BFj6A8Z>nUd=ipfSi)ZP;(Q@bLoK(b
z(hz&MPJ_KqD!l70jABH2sjd5)&tHD0KA>)@Qv4$cd^XGs^Vp@DVP&!f%rn&@tOKs(
z6o^+kU)IE_eL98gw0q9L^+c*8OGkZLcu1^fsBoE_=NY#MWZ^FmFhdhMBHrmEwhU_8
z+Z;)r76F6R_XlyRt2YTi3&OV=R_8Q5eqitN7T8kAbWdkxZh<XM+!NY6p8CsojMu*c
zTsS(Yan;oc0d8knFwvG92`=;+3t|Tf91eQyV);jd7LKF>RpnI>W}Lh6n#V-5uKMJq
zk>O*KFHeW|7`8bq4r$;nuoj~KK|Q%qLKd@a!+l~%SbcP=HGiW+GYKA#5kY-0Jsb2%
zBbzyhC7t-?Q-Xx4+8MQVFrMEqZd0yS*!<RK?DX^#9o^4hkx%z@YB2#!)b0+Lk%E)_
zB>U>ywI(#kcz-Z*caa9aCyb=q#*Mw8d6h{q-h;~LbyF~PZ=sSJC2=VY(Q*=URLsEM
zJT<LS048UZ@~4pgTzf>@gkOnuuqBu*;!VqzJ(D|ZRDma&68Qtne9$OS(>pHjzFf;i
zG_NX~qXMZx24lQ6qIE!x1rN${Oi$IhO}?2%W(WO<<rNBVE!DXq@d^RRHu)IS8F(*a
zb;06$9Gx4T2}3E1m_aF^8;rOh<UW<B*^T4|u&u)-QigzOVR=zjoQT~HZmLul{0n;7
z{#f9ZIToY>e8EIxt}`4UL+liozY}IS5JM)n@fd4M0Ji3-+ub}vOgRexF)#>@D=`|`
zrsQRc4WA0}oB}X5JeN;3A=G8l8o`6Dv@5K#eMvsOe8aIf1Ed`)J`0!YQoR?^m)%i3
zgT1JIKBU=)UC9e>dZ(P)-t#c_zVPmCnTxUag@?91yZ5Cd)1NGEkA>28>E_o+EMs-O
zMpWLP4-NbKg4Aw5g+|B1bNvu12zp(pujX09@57uG61$cC!4n8%Y5w{LKtS*R+I@c|
zI`FF;>uS3!-`BMQSpvV>k+C?|e^{&BmeGwsk0O{Kk?xrHNYKw^iZR(#A?;smPtb|l
z^?vjxP^`ey_C44s#jN0QI?~41hfa-JP-upfgLz-{3{l@To6a%H2dzBfEgzt-v3fW5
zh4J%$^G-N3xwbeBN+VE5_Uz~MauBn*pSK~G6icW#U|x1)v7QqW5XnL!!EN=h==+8!
zp+?Owld$NU9B?S)VRT!R3=gv-vS6gUs_(>wbWVOpaCDWqa%PGq5K(q9P&Vb#Mpcys
zzKT(!LSqgvjHukG_9)NX#d1Z`rd&MMvnn3nYVS1oNWZ7s+qDDX+VY19M}S}?T@)Rg
zJ2@C*gie<o=qZ#92$8~MxQS#jpF5v@_mEug7I}^!JEScYB5XQ0`jPW7!zgpT<~;gV
zCfQj*<WONm=asaixyf6QhyDWhK?*4uLa`(<&jh~-c}ALzSL8l5wq|?~7zLPo7CvL_
zE4QsoFlm??o=BI(oIGnOKGGVHD2f=Pm~cxVC7|Nc3Z$T9x1VQ4sK6}2!Kpyj2%XCh
zTuqJ<ByjSCI8PsW@n8KK#b+xrN=&K?WYqyL5JQw&NNF@NlV?KOiewc1qB&?AjDaFF
zbXJ!6$dEDH0fI}x{DsUj+yqHt+*JYjaC3P(g7ZXfEWDYS-u}8#F_xpt-#Z{u@1YJ@
z{vp?_MDj8d3JTaOV;WPxSv?{&3P!q8_p>|+i~_OAg%mxzy_W`rvpX4+$+Cy)ErO%b
zOX@US7{2{-2NWclxxxLC0%DQk&?5Os36v+5<<wjsI4b6W8O4Vy<IsyO)cf4ppZ&39
zM8W!z<Pba+p|V=xW{qac8_??kX?${pASzs!lJ_)&LJSphKacI_p|LaxK}2K`u1PNR
zE^psH>9@?;K5CTAMrLG+MdEA&KYZkto2XMG)<!o5{;@-DleQYrbKU5K4+auM1eu>W
z!OiD;cux-%kJ(E?37=qPna*Ir)}-X)IZelioZPOzz4rQms*)y8ndmr$Ec+8y9vseU
z@lS9U=1OoQmL?7mN@M}A2*lvld^1vUEHZUwQBFBu0kWZ*Zqqe8j8qr1*P{3l1NGzC
zRM7T<{?Z4o-2%=AX9%U-*oYHlQ{du!de%3?Ic1&qH8vKG6cMlnmrE%RP+|}WFKFn5
zZwz#-YFf?PvsNpaN^9v<8jN=~*qY!F;&5NPYCJcKI|0`8DkVk^RRa45e+9!fkd7b@
z-cnPwUi{7vjB=UMQB)!*V4mmLwXF2unjwV-gAC~vh$f`5@53B$U(7xy`+p2N>|pR{
z%^S9YKzX_YYRIe|21(%*=Aw3F0^7{#bjWJOz=ssxqN_{7#<xD(X9Te)eUny!6e+J2
z1`UfU0e2k77lG4p`p^4}jTzubjuA7{7gW%JB3lo7n8jMw8t>r^1|R;62q``sSnW%3
zl9bzD#wr>IJ1`Nk{8sKQ<$X!Dl#Eu9Ih!(BEB0PIeLbeiEwBv=3?yq_d6R}poi>oV
zGzy=MmJ1e@0cvM8*yFXOrF27@Ht%U<jpw>-aFkEberc98cTXanug?vNj>9dppC3M*
z)G!_tfg@QNMTZ$o4bKsohbb?7v3l=P50VE@CFR`!Oa4OHh*Vi2AuC@6**E111{AWM
zOM#yHSsBs;$2-b=w0!wbKQ<3Q#(1lgs<YisTycTkMra^tGSYRFjx~UUis5<rN=?^m
zAcEkv7@9D94fKl}J`6W&cH0d1bro#Jnhn@{zQ{sw*2<=&AeLU*CPGpK@<<Qm-7pT{
z_O^07Tue-!F{fdT>HK0jXh96GO9I2T($pLOL#;G5F4G2Jc}{uti@us?%970@WU{r$
z`Xui=DLlo7MQg#FQ?scob2Lq^X6tUq1=3{Uq)jl>1)l%Z?rVRg_;?w%RH?d=;RD9V
zZNz>uw-%k~Y%#gFcuV<6eHE5qpe9rWS6(VnPo?bsBnq>>JdhCT_V6j6|LOvaRibC$
z?<$zM5%a*tQ_Xv~LAp9!1}B<W+BR`=+i|@+eKbB)J>~DL?n*|v=)%3l3r~YCwH09r
zj%GmH>V6%h%dBsAg5DFe$DivC#shxEKZXh6QZV7TpC*LSbh13zgvoW%pGc-Z|Je0g
z!oy3~{^NtYaK8`u6sf10$x_j2jpBo|QVoOIM1Qpm7Jm<+t?IrtYc-r_@k(Q<Px-8c
z!q!Q@ZK=p=R|w!zQjCuSzMfP2W9H%E%@s&^GY52cd;DBo9|RB!StR@Msw!0RwTgM=
zrP%SmTu!&gjY~LFnFUL};OirL;t*D0>bRcn?sUO70xsB|ga~uy)BfJ(&O+EAf<bWm
zOF`KB;p`)8#q?u;z_Q=QLL^mtz`at0Fd{2`bOv5k8VQ00>Z$|Wz5`|PVHg0WCR^`V
zA7(G2VEmM0c55mTUJF0NF}n&KTfaW;3V<h<AJHT$5n(gzt$F3~>zRPbB4AoSkUqTB
z`@;A7-(1dZESAf&cMaMl=RWvIXR90jwV+kI=THv)n-|rlx9MSfd*`|Oe^O|>i4&f|
zuGsIxmTW;yDF9sDtJm)e)05LPka|j$Q(Rdd$08C>P62NCU0pd&b%tXw%(nR(3#C2b
z_Bzhz4>eoo)c*p%A&+N4(6%g&;hJg{-|@RNN^#{#SC5@#3={zEw>|+-SL%ZUMuf$i
zi8ye>-7$c~NF|N8EW$=w$sH}!(3|gazaRSFyF^gX@iClrt=J>D=$+3#8Gu8R;ZENv
z=~KRRmT~F|KmtyXT?<oym6l!m>oBpx;gl$*%s?<dZUN?UwlnR5C1|#?7dHgp4yD2=
z9}*XSxS=f3NF=_h&{a^)(G8EPN4lX{^UdVMK5f+_&f<%{4~BO}RgbyL;$bR<T6A%y
zA6HExF?Uy({^+Iu^Qj`Pf;I-rtcr8$rXUVWCIqZ8YX#><Pj~cZeP%QvLFH{S4RwmD
zfVGrx0#h{He5d${-`(kssER;aCGcB7w}*t<bR0JvHqizK7e_%yP~l?;=PTcUmBtDo
zp2<0Ia)Ro1?JYo|1I|gKh0*cceBrtJLcvLaMx5pk>VOC6*u{RK;mte8+*W$I`cLNz
zpFgXXT%3zvV%sjbsTxP-%4SF<x3Zbs-08C|9fk_~NMF@&4H5Wwib%%o6jSC-S4*w~
zAp2nK^57uImT4SmyBceiMFI$b9=6SiBm<p<7&T@Qfpml0oo9Dg&5B)UFoGOL7(YWj
zroi3C?soUCHY{m}ldI!7@g)|u4~5rn8`-zt-vnR@E?wWtZF_*KraF3faYIcAOTeMK
z>Y^jnXw$VtTuY?A?2g;U$~hK_El%5|A@T`IVqwW>5SDe;DK3^NXbFgxzT%AgG+J>R
zU#7_ca!jQ}p(qyd$S({=q&h!(ygjw70o$P5f{uYU3GTE|;QDkKmrl3BB0A}A4@Z7<
z@3WZYDwx`=1KXBlmeirZ(F35lG1!9*GOsb0(vU-BiWQ>Nzoo~0YdI2B>Bfyb8XX?i
z-VoG2NQp&Td?w|e2^H?h!V0d#wh))aHO7E^XzzeLu<G_D5b~<Qig3Gx`UT_C9sh1U
zStz8eXECG1x6{1(_kZ(1(Hyyy+%=d3KAp)0@0XytdqaqlpYv1PbM=o{OnXxG(Sj1t
z5hmwdL2lfRHNg(<^A$*6g_yDdft>8hE#Q_5qY@%m(#YEYlRJH7Y_9`2h5o%@d<0M!
z570HRz_sIazB00V*%KNch{|#}HZ;X-BFJ)31H0YmYDv4k<6r*PyJ1!zV}l%iqH7-k
z8G<=!)t<R|IO8G0&B9VuE$g5L3dRC^@>bbO&EHoyQmBM;-PDi~pfVuq_&Lpf_N~Q|
z5<uPz@9>9Atx^ml8S7b^MojV}OFU|555Q1g=vgW5pBQM4$4@o`#(o>9m$pzg>)-k(
z{b{$15kDb9VWhi+ZjF@rfbvakoJX}nmtiru49JPn8C$^k#vQ2@2jXJCp7V4LP>R*i
zWGc8BZm(E$&0I`Xjg1nt0<1*DJ1;yniXy*)fr(bZHj^{k4c8`~+!vQK5X_8J0}L!%
zklx`d6Rbq+M@1Mc!Nm$xf#Mm|<ECqBw!%&_+0XQ%GK339Rj|W!Pyr4E+7cKI$dDKL
zgjDv&+CXkNJP5E7%^)z)wjKf|@lu6w*2*D!uP%@KaQVmw-V6YCwGXP-bsq%^_V?!v
z>z7PNgIE6S*o!Lx3`eo2{5$bYkNSUAp)%#bSc67z^^tvNuvkCR^><+svS?<*7M&8R
z0rpNpL6ZX<!1Q9kPPCsFp80)m{ocQuuw43jM}T{tzkB@V2e0Yy)MXU1I1nWp&7MWA
zl4rpo<A~E(v`UoYe6ty%8UWt1;C<9g*<cp^Acm8Lkq&CPS8&}bA=SC-fnYR{c1|%w
z;fNXM-26e7jNYj06uxxgUA0cb2CSuwf->;jni%_u4kHg$@`5-3jFmi`s9xe9Uf?dy
z&XrAhb6|wAeCNX1{Ye~<!}UXa9i4ZL55Fh^73c~DG>-TaB#gvbau4N#E+mgm6-5vu
zKLf3g2goJ7VX49<5I3~UKrT~8K~XW{vrA08u*PtWhEPeIwLiL5pnzIVhIt*Qc`Q^g
zdI6LPa{&dq2fIZ{+fL&UH7tXGLM#=z1LDAdFmEKyh*B|4M51{`b&AS4B$$K$VdR7T
zY@$Gw`^>#r(*bbcM;oD#H$l^Co3kXOe3=*}zsv$ZZD*VYis_?@<wz-LiUbS~6aWr{
z9AEpdR?J=S1wt~5os9vNEktvq2ta?FOJNI8L)1%*-bL62tdANH>qt~lK)5LKJW>B5
zfxM(3-tH7B({ytDLFf>_VQ#T4Mg7*nchqdnfwq);A}v4Yo46GZ!dbSewc%bTY#3-h
z4J?ps&=tH`#8wE9V9+|Hx5$$iY9;Gv{iqPNDu4n6E13au=%exZK-$-RFix0;GgLG(
zje*?P9s#H{E-;3p&Uq#^A){~vYEZMOjtr3G0;Wigb+(**<bjYUuCz|Rwl!lo9lR$$
zPI#2-aPsz=9cr$l?+3Ak3LH=(qb9Qfq6|@vY4n~&6##%`2cG2x93vf4pxuBwn=#)I
z9rcA!Qz-(M^0Q!Ak3aja-ba2+yTy42wb)>MwmAzNWASkA1GD0J+?U;o%eR2ckP$#G
zUNXUDLZLHcSM)^01J+*nB=t<KQt7m^8R{{H(ut)-1|vzm;(=*zGqSQ~&BIzU;YUeg
z&7`rF%Dfm(EcuUK(g_p|Cn%%JTB5z`VZ8D%Zz5=eC^wKMXgS~)4!WOVG>wn`+B@*C
z?b?w^2Bgc#A_9<(p<>mlL2jZpTlHne7P7gD%Y2Il5Ulddm>!4<U;tH7atexB89g-W
z!;PH*HbLb{Ok|*AOtMnc(Afga8iP%Q+Ck@uKkrM?OFdHoM4;>E{lwZ=-x>_t5I@o`
z;*=g7pbnEx3XSaiX3CCjoz#iQ4mxRy9XCyx5u8(Yio86F@A4~Wq&^Tl#3G})>peL&
z9&A7tX4{{rpbZ#9;vUZt@ER)ANX!py79zoPJ%~^Ua1Yc-or~l}{(<?`?Qp{CiWi=k
z%~T=3fiAjEjE9qQ%(epib#`<TFKB8Xqqz}rHfXC+Vt$mVCpo2J>^kGa_k%f!<14n!
zL_+C4?dfJe@Jo{lGHMrnhIc59wOo)I9;`JHdrYNeBWXlP0Y-Z_4(7`s){GAlVK{4;
zu^1T3Mf~?HV>(#-$gkIYRj#L|(e8_2ua=y&(BD9FFiL8JkExiYl-gPhX3cH}MA0rd
z5TOD0Y3pWZxHC#8X@Dx^a}{i?70F5|sL515Q+o-;V(uz|o>=WfVZ}&RV@C0tUplo%
z<`$}!yvt}$3w0PPc;|&?W(@bInt@wWN$A@~3~5pNpP<aKk#zufxoslj$aH6)Ok)%7
zvlYd1Ky!7W=gs14jV?o!VTouvo4)YbgI>LrmfPhee>lXxiPaW#B|E50#K{oQS8cNe
z($sKH`Gji)ZDMo{Bg@glMZaG4$q8YeG4sXg5)ugYR(}SCVaBe6H6K(+XQe0SlDTj=
zJfLIb#ULvrMLuHT5UYenb93&_-EZ^CNJ|<ZP%FX;#}C$FEM~plvoMmKO5J?O7(!yi
zWMzoA!Q(>XydRktC|?*AI#N)g-nbDK%8nPCs*Pt684$P~Y4lR3&M$r7?Sy;WQe<^m
zQt`ANp|mH8_#r&$&$Y|<79Xvz`bTsFa~gs{29*Jja{5_gDZozh(aN@9dlDbpwhT>O
zKe|6T<_|-I!sQiFWrB&@>NCr%W#Qj3rC(UuOxHQ-w>DfX#;~zIR3!!hxPm`@fe_@E
zAfn9Oi#;NFsZ8u|5YXqgwwhb=-Bz~>CJW8$v;&AX$A4@cXRY>-RXtiBDW8^#3U=&I
z4u0#vwXL#4@C6mjR(uF(3I38!4c_8R-1{LlfJV71i6084ngge*7fuAuV-6$U6V1Mf
z6Pvdb8=!c@%a{Ny*S_egM^6S@iml5&Ot;6JR%LTAcOkfNGC0yey_z`dPo=jw%eOe)
z)w}$vzte5ho1cig$LsnV?$U?a7Y2_yJGpW0WH1L<-nM4^r_$;Ak$UM;oTy~FzOU<e
zv^b~TpuJRK;7%uSaup4X&Kaiz!Pobmb<Yj<4**gDJ&mVosdyE642bHB>&Vy0p(6N5
zW?0g$13T?*_RJtNTgacHU(iw*$<qv<g6u`IVk>#&<)Z%7Ivp)jHBcW&F@wrtF-y#H
z0rsLGuT|K+7YwcU>-r}}r$wh3c01>$E*HLSfC=6BxHc;&#aM^!9&gl7k3v++j4QYJ
zo8G>X8@b$ZXE0&Jers8c{1CIjuc`p&J0-YMgW-H-s<8x=wTk|Zd1do+{yB+Zx$=p6
zHM5so9C@&);Q;^@h|%Go>z!7AF&K`t_dKfLknI6)5byIx(g!MkTv&lK^4NRu%!PSi
zf9XUKGyz@F`%VH0CUl4Qih*S{R%1^Fqs`!kJsa7R8+{ypOzX^z?WxWKuF@T}^Bw-V
z+pk4izSRDX01Vi4jt%VrE`nq;GE~5kRRNtA3oRHUyTcf_+n^0&ee$foaOVp*1z<EL
zn2<6h*5i%oOh49`IcEhR2bBDHyys%?(&$8$bHH7Y=PKyI)mbn*e776(g_U5TOe&Xy
zYMbdmYbbMg!#*ApMym}$3of0;nyziC(gk;>Bh(kdpT*_H@T32%Zx=YlbM2>>0d*8G
zn_wXjViw`xAye$&I>D!eXEXNnMN^3yxiAVCc?lG4eso|jv(@Cqu#!LLOUAz{fJ>}O
z^=7&-#HHW@E9~~IG#7_JMX^O(WH1-N%LN%RqPXA-jR_ORhg|akf{%{-C#o>bI?#cp
z;}{?%1<3>B6LU*QNmaD?xwEeM@&9&1|1Le6g4lG&VN`_z4k1H5l9Z?Bg6c-tEXOb(
z!#H&TfFo4T0U?4_Mu`?DW-EluE16)Y3skxb+67h<oAbC3pTd_E>?({vFU}9O_fR-@
zxy2d;A{)S42~c$i5q?{n=!x7mOjy!%e*$+4V>-|VEkFz%4rpzJ5J_j0c!_rL@O@f6
z|H*exm{h}qm~v9@FpO@>T!hgu3Ig&ldg_b5<OuxmNgT)}@C5A<3kU~SV2Kl^+6BsV
zCs)ZL@C46<LzLjlD+sin=OP6b<Q|E2SfUAx;h4R%P&P;qe$&{AqNhx7Lg&`-xx{4J
z7(3)PX}MxpS->L(I2a-qWV3DVSUm8he}2sXtvMbdufSU_u@}TOSqM}D?+jyCyn)dm
z_JkgY3}%()JavFoCFr`Z@kmG}sYI%HvZLfyd}-@>+<dW{dm0N!JAQzbgW19wH4tmY
z9v`j+$I6Txx0pUy?VHE))4&Xn`>Dqp`BG{$b5&ymAgeyTs}1wvc)QR~2Pfz#$aJvs
zyYl7&^tmgoMQ0;nFhS4Q3G&pJ3kKaAVPdHK?WDnl;CRE>fEJ42k61I8Of~kxU@;V)
zBs5L@?k@!(wIIxP2|MA&f`Ycxrs!qxH-Z^LKU}7-x$L_Oy)tx;V<>IRAW&q3)CZaY
zs30|~+I+onK!B*JPW|9tqAGPUbCt$P=Max>w+fAtt@-=vpn;&?&d!u2Y|;?go-q$T
zM}r$bJxc7BLhcSAQ)J!BjhX5EhE$q2jgpo$W)@5AYtrvGT{DRfv-5Kp=B#uQ&@l#t
zSnz7v{h=UN6u58<R@X2KE3QJ|^P@n(H@Qa(P4)cJKU!uf5t%I0<AlCGXKuPisQE1@
zW}+2E4y*(eh1de9!e64ndIEh0on4f-HtS~$Li7FN4&F&qRXsn)x<#Nd)2Ooe63EQh
z<eMpX@f=yZteyR{eH{wH<_-L{Y6aF;=+#MjMCT?lR+!=^K?$)9yOfwrN=^7&DSM?5
z$1p6l@SVoYW^n}*PzIc(0-W_60o<;zHxR$|5-p1<VPFs_O$Gs*Ck@ewnW;7nPsfp(
zmW#-$l}6J^+`Rb(y?Qky_P%gBIii2>4T42pTIYmi7*gZC*Mk7R^l$gP_xdd`OJDl@
zp7;90FTo7^V1|jEx^vSxy}y0z4-aqp%D}+0d;fROFZ+M~$ghy8`}goBKomFse2D~E
zBCmmoy^o>`Iqlp;FXZII=O%i=FK_umFZkt-FBIP|#I%op{52zJzKW}{Ex+M)3QcTi
zM6<{aLcXIGd8QD#L@$^3{jn?xvbWv|&S7`SXN1pHvdHBCQpkY;tpBHJaLB68VQ;-0
zvxqA`{<poe*-yXV%i3>GJpf_C0v-+ZKD~7iga<D=w(R~&lf5;CxDn3SX}&);;y4dh
zAqpxg$&z^CML8TO?oBflp916qcrlqar5hHmSkO559@D@*tc`F}Rc6d3P=WQH?+%$Q
zlZAC?Ytg5$U1Glposv$)w(u#~86ae0l`Kk&q-nv?u+enb)3oChamlKjr8!-RmAz8u
z`2c3bX&#7~ONRV7`;vRYm%rI>WCf%?(8|t}HuZ!mV2E!cDoXSq{^+(Gn7fRSN3rEW
z)fd%~8o~II_pO*Dg<8-PxtC!8m`y<NNX7_;1mo}{a8yV=yG!yX+0;@B#u7>C%Aso*
zOACeu)kLn7^E^e~5iu4oDQe(WhC@;AiLoU*i1DQ}Z{yX_Y}W(TkcHlXm^dgsc@hvY
zVoZ|E$dj`pl!sGf8P2jJdyd!BW|5Wm!WV`_lpt2*0$hT7`IX{}oOra7yE5h(I#wiL
zqX230M3IqaX2_991dARMQ`U^pl;s?=qsXLw*B-871RI;(WhyWp$f4aDmC!5ryHmr!
z{fCQlUFik0W;_o3=m3f+oT5n~L?`D_sJBQQj7~5xp5uTsL8#)Aco|dIHV9Xm#%T1M
zjp=txccy2>&rkOoun}TW<am@El!hB99ByYa7@9QJ1(UsNPwG08odojC?&%36^E4@i
zmV>R8U;n?nV{jz6u?IeYNu}H-Hd6F=<n6foG@0i&xubU<wM^AZl}I(DF`p!3aWoyL
zh|u6QCbMJ$39jia)PYn(mVIQ;v!ouKmgepn9Wbj*NgnmQBRS6wdL-{8CuyVKNNtev
z`T+_++CM%^-lT%)@-RAh2nYC{Eb=Hz_BG%&s|Vp=%?T(am5~uo=2XmzB)*MewM<W1
zlQ{2}oJ#7RDXrdk?j+gAHy8e|0%`O-iDw*SM8G5(Zi#1w(DzJEN?tXhg7j5y_6yjN
zwL8h78qO*5u0&|rUv_y4lt`V=%7cg?dC+mb_xstNQ#i7}&VXQeN>zeNn-{)tLV1nA
zf}@3OA!5gjHom}plxM;ceo+iYf)vOhIi&&gKFb4nIDg2L37eIb;BV)H`pv<MOP7I|
z#9<SBJe?X?wuQ^#GKj2K7b{0leSnZ;8u!H^$$>jSDHTYY#!b0+5_OADF;|S%q^0x>
z*06)r)V@?9qe(}kBl4)d)Y<`{+w0p%F$Y5|6CHUYuiS7zOFlWW@d~&`Xg?W-E;WWg
z1?rL!+Ms@<eP!q<Bu{20AWq?B{p$3)y=16<24AEK5%jicC=C@r%9ThOCb<L0%7{Ql
zJV~n+TU`Fjd7B0*BRXZVwcy`bVF1$Pp}p}89I){HA6q2nS&V<wx*Rd<ZUzQy5Tmjc
zSvmsrGLe-6NJbK1p8*i7O#{dPSKA0ws`h~g7~VqJ)4n-i3xX>J<6UGY8J64{!Slai
zf|u58ya8|ZTM)AZLrCPG72^UIKm*zrvSQG{4-r_E9`+Np<TC*=KBvqB!?ygx-dIKT
zkWGZJwL4v{hX<CzMr`e?>o9cm`C=FjgvH!41DiZPc4jphHyLE4_v|>?y#0mC|ACFp
zx=&qzO`R`xaU@5Jp;i*Xi;YJi=FMpUERWtnXJLAz?jvhizGP%RxDsJRuDK#A_kp>J
zCwhkof)U39#S%XbQn6BSB0m4-@0pF;8c?sEYAUO7qu;2X^9!eNC|Eu@xIKyaKkOb%
zM)oJ|rNC{_R?XQ_zaf6VwkL4Ezv}4B-`Q|$o3GicV726_r2q(M75`ope}WGcAEZjd
zp{nQYR&sLl@O_(ytDA!fC7i5<a&SSN7$j`6G!eXKHfVQSC6Kjj1>EP(#jx4vpKADw
zGkj*?c;WJU{>1Bk2!HU${JDF#DGlwbu{-U?%Z>WB&EpRTQ|VDh{?AP(AWcW=8q{U3
z4D7Qj*<Wux=y&}RjaP@OW;Yz}pRktcUj5!uz;gLOq8m&8`OP>2Xi>R=9`46awo?td
zGDZY$cOZz*7K!ESHt?qD#bsKOGh5~u6}gJP3>s-ZC<G^~5J^jCgVWa^b&mS~W@w)t
z?<nGR1q#pg82I4a9nupxlDxz;RQ_0#tI1T}OQ2M2dKXg@qX4B@>x5d-oby7=l7yOE
zDwo5PsQn}v(qcW#HUO?Gpk!u$Q6bINm8?T#T^SpoGV%_MAiC6k(2dXO%MX3<330-H
zysP~$W5fn}Fbilj+t*6IQ{EqLuW$NFAyp#}eNh85!6#Y`+Czd(On0%U+q>$0r@i~w
zaK^+6MlKPK@N@pDdb-lIFSy^YzcXH0RE%<Qtj8c%p;zuchQF@>Mn`Qr96qP)m8xHQ
z@RYdjs&0?R``d-Ef9_DR<?H5NfQ0LUONB1Id#w3@W6$J1l{PP?0zv=|n2c@5+#QRJ
zmy7*+UZHW1@B}UPXjmPVr@|KC$;@Ae3peHiwWkBnf<o_=b#U1Y9?{_#o-QA%qUEA{
zPhg`tMV9hSh#HRg`-xY4wL4^QbcTECAW)M~V<x$T;ANlo0ckRiQ=Mc_v+M1r{Xfk8
z`TJZkc#7HNH6}YTqc`SkxePKX^?8@#4Z-4pkB+hyK&ey;)f3B3=rV`c@Np(P+v}wU
z*v**J%n9QqYNO#l-7NTL1IMl&9jajlnS*CSxp(?lYGD*koz(X(L#5F)BeDq91}%DJ
zZ<x6?*ZdfIVslk_tPl$}Hv8ZpTNW`0C9d1P9W!TP=Y(gbETg~*hT2#yl^5%e|97)d
z&Y|AVGbv)VNs7Q|m;wR@E&FS(u(r^Fz2t|kaG~M?&f1rOzyNsWo%iGZ96neMU=W6l
zxTmvIG)gim4Yszo6;kwZKLLq=a+N2ZvBGwLq-{bgYV}Vt;Scn)K?v}ade~nXGr0&j
z0C{3`nH%dfjwhGmu0HtuZ}$O}fO)O7{KP4y8I8?l<4U`D^%D$i11Q|c)SQ>F@D2nD
z+a2O_mg$ElLc9rNdp%XE)^Cja)^do^CR{i0nc9K6G0qeZY8X?{k$VTVCpc98VO*QX
zSlqd?o;R4~$r>0If?!S%Ff;al)F^p^Sm9(&9QV_-W^&FXri<W$gm&zU6d$}js~Y$S
zNXF7z1MQ6lA#jL|ZEa-5p(qY{cTs^;No(|WvkG8@2mZ;(NRa;e$W>+4oG*modH0qA
z6#T`40RfymL09P*@&{pwg&t7FMz=olqnrQBWEw3fusx6V{zC%5H5V~I92d6VX}VVl
zK#_o!F4!mE!9q?K!Y4X-bko?VuH;6Z?o7=Qn_x~;_bX7=FfPnwtkRYKd@-%lQ>j!<
z<I~hBq(4R`KnKI4X@h>@8SG&fW6>B>UIAIRA~^=jQXy-4c}Pb9Eb$Ki#ot{;9kTSi
zz%)nNlf}~Aay#y$zES|wF;{b#k_LqHi!diWg0*E*uuF%6z2GQx7|Gl{(~JUexPT`n
zJ6(V$_*AGmBYo_lj>i@&k2}cLNYYKCLxX!$uR931G?2smFb8VeJY5#q;nxaTKG9_Q
zVOTcu9slyzORSHDVvcWuizEcYL!nRx5}^;Vv#8+^#3u6;k2`oJCyX#+DI{*cY>e}0
zaJb=;>sc&7J!c(KM8T}(@Udm!tBOgy#<sZewI9FZ-+{d3fg!>OW?d|HVeoG6@C7(J
zmU?yeChBggq+rM+D;bx7@i0kXM#!yDXZf@F9X3}F;gJ-sk=X_h`mmY0k?ub)LWJ10
zFUF&ns1=)V(-lj}-85!B7o>6X!{z7y<Za?ceoEX(KJ)cI)q?HZIeKp5w)QcBWhPz^
zmN}Z)`~A-;0AK-kzOWANeB=u~aOcn0Q#q5RGIRLM*AHfp%9*pg-~Y%*=gtOVHz@Cd
z?=*fEnjtrW7QF$~#Dw_l*jsW)|3<Flf2W5L1^>~1{{Ou@VZFtA06q?DWtLd$|7E%r
z2U_P@;NqG9*)s56^`GH4TZ&4H;Sd;z1rVP+NlZS_v3u$wP39w~vlH3Mb^X&@ep~xy
zGh!7=)$7`Q_>y6Z6I(VGnrxnthpbhLx+d8}r3kS4<7(;Hta!7h3TFZ&NIpZzOu3TH
zW0tjK7rT>4N>X_FfAmWNoW{=&7?r1UqW=+gg0qar+|6&iMC|`>^;yR9G?w=)_vLg1
zJ0cJ<gk;1{Ip>+=m<LCgCT8lwN5A+kxsspd2Q(1I6JVp%%+AWa@+c$qEVS^f0KFf2
zubNXlQe7dw#F9J6AN;y@{~z+2W#j5Q-rDE2-7n|YbM)2{xcaWOg_mn)uUJ=~ev6+E
zUni6xl0*Lo7R%}l$<82_s}H1|9ho#^UQ_BIf<xgkB#I1sQj=@sSCrMY`#;B*^?J$f
z{h1f)_h-(%)`^$z&xTtjNFWLELnTL+n^(C*s!i}WX80>l;8JFo^-6&HA+5qV{E4e;
zCHs|S!W$jRqmwes(<(XSSsW>U9z*!;y==<YU*yQLz4oOmV*f>wTEF-3bs0YR=2DUl
z`O2dw!utDy{#TxVYu}`&8Q!)}|Kx5&`1;4s=IE8zJ8Q+4II~_Wul()JeCw6dc=>}8
zBQZN_SGScbC*Rcj;b*eG_VeBIM(yxduUij7$rzS3=ASRwSHJ4cfAN!IzWN1k;w*ax
zZ{q4VxHN0E>*YH|pL_kI*CSu^n#g?qrC&<3&7L6T%<SjysY|Q%<z%moWWAQmX4$z?
zkIXTcrKU9ZgoaeVlF6n(HMzQ+OuUqIxPGnv1ByHu+z`$wJT&Cu>+2`Vq-R{moh<ZF
zSlGS{1Bs9@p87Viy*b-E(zxbWQF*F^J_QP4qN(_cO4b~5%!jfz`Gbz1s)fR2r;{}6
zBNmIm5a0z&Z`}T!XTAYM?pfsXDt70UqIh;>8j<~zK{ZRWH;0m8&wAx}oK;&YYnipL
zez+$ezb>*V%YD5GQA!o{O3hp$=Q&a?j!beKa4(NrKk7`(UI*Wk2(0N@+4XBT{Lz)4
qfAROXG(^6}V}JR*;58ofW>5da%vk5mh^c12^6It6-t+P=?fC!Q0=DP?

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qpf b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qpf
deleted file mode 100644
index 323e0052..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qpf	
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 14:59:16  November 16, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.1"
-DATE = "14:59:16  November 16, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "WarOfTheBugs"
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qsf b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qsf
deleted file mode 100644
index 07be9d62..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.qsf	
+++ /dev/null
@@ -1,190 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
-# Date created = 18:12:35  November 17, 2017
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		Galaxian_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_7 -to LED
-set_location_assignment PIN_54 -to CLOCK_27
-set_location_assignment PIN_144 -to VGA_R[5]
-set_location_assignment PIN_143 -to VGA_R[4]
-set_location_assignment PIN_142 -to VGA_R[3]
-set_location_assignment PIN_141 -to VGA_R[2]
-set_location_assignment PIN_137 -to VGA_R[1]
-set_location_assignment PIN_135 -to VGA_R[0]
-set_location_assignment PIN_133 -to VGA_B[5]
-set_location_assignment PIN_132 -to VGA_B[4]
-set_location_assignment PIN_125 -to VGA_B[3]
-set_location_assignment PIN_121 -to VGA_B[2]
-set_location_assignment PIN_120 -to VGA_B[1]
-set_location_assignment PIN_115 -to VGA_B[0]
-set_location_assignment PIN_114 -to VGA_G[5]
-set_location_assignment PIN_113 -to VGA_G[4]
-set_location_assignment PIN_112 -to VGA_G[3]
-set_location_assignment PIN_111 -to VGA_G[2]
-set_location_assignment PIN_110 -to VGA_G[1]
-set_location_assignment PIN_106 -to VGA_G[0]
-set_location_assignment PIN_136 -to VGA_VS
-set_location_assignment PIN_119 -to VGA_HS
-set_location_assignment PIN_65 -to AUDIO_L
-set_location_assignment PIN_80 -to AUDIO_R
-set_location_assignment PIN_105 -to SPI_DO
-set_location_assignment PIN_88 -to SPI_DI
-set_location_assignment PIN_126 -to SPI_SCK
-set_location_assignment PIN_127 -to SPI_SS2
-set_location_assignment PIN_91 -to SPI_SS3
-set_location_assignment PIN_13 -to CONF_DATA0
-set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
-
-# Classic Timing Assignments
-# ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone III"
-set_global_assignment -name TOP_LEVEL_ENTITY WarOfTheBugs
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-set_global_assignment -name SAVE_DISK_SPACE OFF
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
-set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name DEVICE EP3C25E144C8
-set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
-set_global_assignment -name ENABLE_NCE_PIN OFF
-set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-
-# Power Estimation Assignments
-# ============================
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-# Advanced I/O Timing Assignments
-# ===============================
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-# ----------------------
-# start ENTITY(Galaxian)
-
-	# start DESIGN_PARTITION(Top)
-	# ---------------------------
-
-		# Incremental Compilation Assignments
-		# ===================================
-
-	# end DESIGN_PARTITION(Top)
-	# -------------------------
-
-# end ENTITY(Galaxian)
-# --------------------
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/WarOfTheBugs.sv
-set_global_assignment -name VHDL_FILE rtl/galaxian.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_vco.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_b.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_sound_a.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_missile.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
-set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
-set_global_assignment -name VHDL_FILE rtl/sine_package.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM_0.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_6L.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1K.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GALAXIAN_1H.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_HIT.vhd
-set_global_assignment -name VHDL_FILE rtl/ROM/GAL_FIR.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/spram.vhd
-set_global_assignment -name VHDL_FILE rtl/dpram.vhd
-set_global_assignment -name VHDL_FILE rtl/pll.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
-set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
-set_global_assignment -name VERILOG_FILE rtl/osd.v
-set_global_assignment -name VERILOG_FILE rtl/mist_io.v
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
-set_global_assignment -name VHDL_FILE rtl/dac.vhd
-set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.srf b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.srf
deleted file mode 100644
index 14cddd5e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/WarOfTheBugs.srf	
+++ /dev/null
@@ -1,54 +0,0 @@
-{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "Clock multiplexers are found and protected" {  } {  } 0 19016 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169177 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169203 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/clean.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/clean.bat
deleted file mode 100644
index b3b7c3b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/clean.bat	
+++ /dev/null
@@ -1,37 +0,0 @@
-@echo off
-del /s *.bak
-del /s *.orig
-del /s *.rej
-del /s *~
-rmdir /s /q db
-rmdir /s /q incremental_db
-rmdir /s /q output_files
-rmdir /s /q simulation
-rmdir /s /q greybox_tmp
-rmdir /s /q hc_output
-rmdir /s /q .qsys_edit
-rmdir /s /q hps_isw_handoff
-rmdir /s /q sys\.qsys_edit
-rmdir /s /q sys\vip
-cd sys
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-cd ..
-for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
-del build_id.v
-del c5_pin_model_dump.txt
-del PLLJ_PLLSPE_INFO.txt
-del /s *.qws
-del /s *.ppf
-del /s *.ddb
-del /s *.csv
-del /s *.cmp
-del /s *.sip
-del /s *.spd
-del /s *.bsf
-del /s *.f
-del /s *.sopcinfo
-del /s *.xml
-del /s new_rtl_netlist
-del /s old_rtl_netlist
-
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd
deleted file mode 100644
index 5aff2022..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_FIR.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_FIR is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_FIR is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"AC",X"68",X"72",X"C7",X"93",X"3F",X"80",X"C8",X"5C",X"A1",X"22",X"90",X"B9",X"8A",X"41",X"62",
-		X"C2",X"A1",X"40",X"6A",X"C9",X"7F",X"64",X"3C",X"BC",X"AD",X"5B",X"4C",X"D4",X"62",X"3D",X"D3",
-		X"7F",X"31",X"A3",X"BE",X"5D",X"49",X"C7",X"7D",X"28",X"C0",X"A1",X"7A",X"7D",X"2B",X"C9",X"91",
-		X"80",X"6B",X"39",X"95",X"BA",X"91",X"27",X"C1",X"91",X"7E",X"6D",X"31",X"C0",X"A4",X"7C",X"7B",
-		X"37",X"80",X"CB",X"7E",X"88",X"64",X"40",X"8F",X"C3",X"83",X"83",X"68",X"36",X"D0",X"8C",X"29",
-		X"B4",X"B1",X"52",X"4B",X"E9",X"3E",X"74",X"C4",X"73",X"81",X"2B",X"AD",X"B9",X"4E",X"4B",X"CB",
-		X"91",X"76",X"33",X"B6",X"A5",X"6E",X"4A",X"63",X"D7",X"7C",X"3E",X"7E",X"DE",X"45",X"67",X"C1",
-		X"84",X"2D",X"A8",X"A9",X"20",X"AC",X"B5",X"7E",X"47",X"5F",X"DD",X"6E",X"44",X"BD",X"97",X"22",
-		X"AE",X"A4",X"25",X"CB",X"93",X"77",X"3C",X"78",X"CB",X"83",X"29",X"B3",X"AB",X"7D",X"5D",X"44",
-		X"A4",X"BC",X"79",X"8C",X"3A",X"76",X"CF",X"78",X"44",X"6B",X"D9",X"6B",X"3B",X"9A",X"CC",X"26",
-		X"A4",X"A3",X"1D",X"BA",X"A9",X"83",X"71",X"3A",X"8B",X"CC",X"6A",X"3E",X"E5",X"28",X"A4",X"A3",
-		X"1E",X"C9",X"9C",X"78",X"32",X"94",X"C4",X"74",X"88",X"2A",X"A2",X"BC",X"1A",X"E2",X"4B",X"86",
-		X"B3",X"72",X"48",X"68",X"D2",X"83",X"32",X"A4",X"B2",X"73",X"4E",X"5A",X"C8",X"9C",X"2C",X"90",
-		X"C1",X"7B",X"5E",X"41",X"CC",X"99",X"6F",X"3A",X"8B",X"C9",X"7A",X"84",X"23",X"BC",X"9D",X"33",
-		X"CC",X"82",X"24",X"D7",X"6C",X"47",X"D1",X"87",X"5C",X"41",X"C5",X"9F",X"71",X"35",X"A8",X"B9",
-		X"67",X"4F",X"5F",X"CE",X"8A",X"43",X"C6",X"80",X"54",X"4A",X"B1",X"AE",X"87",X"50",X"4F",X"C6",
-		X"9F",X"55",X"45",X"BB",X"AC",X"5C",X"41",X"A9",X"BE",X"5C",X"4C",X"72",X"D4",X"71",X"42",X"DA",
-		X"20",X"CF",X"6C",X"3D",X"D5",X"8A",X"78",X"39",X"7B",X"BF",X"99",X"75",X"37",X"99",X"C7",X"28",
-		X"7B",X"C3",X"91",X"58",X"46",X"9D",X"BB",X"88",X"60",X"40",X"9A",X"BB",X"8C",X"3B",X"6A",X"BA",
-		X"AC",X"31",X"7F",X"C8",X"2F",X"78",X"DC",X"33",X"AE",X"80",X"34",X"EE",X"38",X"74",X"D5",X"1F",
-		X"98",X"BA",X"82",X"58",X"4A",X"D6",X"86",X"56",X"49",X"F0",X"34",X"73",X"BD",X"9A",X"43",X"67",
-		X"C3",X"8D",X"2E",X"8B",X"B9",X"40",X"C6",X"33",X"B7",X"A5",X"27",X"8A",X"BA",X"42",X"BF",X"8A",
-		X"3A",X"6F",X"D1",X"5C",X"41",X"DF",X"6A",X"42",X"C3",X"A4",X"33",X"80",X"CC",X"5C",X"43",X"89",
-		X"BE",X"96",X"53",X"4E",X"8D",X"D4",X"2E",X"BD",X"56",X"6C",X"DA",X"53",X"47",X"9C",X"C8",X"2A",
-		X"75",X"B3",X"B0",X"2F",X"80",X"CA",X"2B",X"81",X"CD",X"35",X"7E",X"CE",X"32",X"81",X"CD",X"74",
-		X"40",X"74",X"D8",X"4E",X"58",X"D3",X"85",X"4D",X"53",X"AE",X"B8",X"61",X"3D",X"9F",X"C3",X"30",
-		X"86",X"D0",X"5E",X"47",X"7D",X"C6",X"91",X"4E",X"4E",X"A9",X"B9",X"6D",X"34",X"9F",X"B7",X"3F",
-		X"C6",X"7A",X"37",X"81",X"C5",X"8C",X"33",X"88",X"D3",X"44",X"59",X"82",X"C8",X"88",X"42",X"61",
-		X"AF",X"A2",X"44",X"D9",X"48",X"52",X"89",X"BC",X"99",X"2E",X"7E",X"B4",X"38",X"B7",X"9E",X"20",
-		X"E4",X"56",X"63",X"D9",X"56",X"43",X"B1",X"B8",X"37",X"6B",X"D3",X"6D",X"31",X"C8",X"65",X"8D",
-		X"B9",X"0B",X"BA",X"86",X"4D",X"D7",X"4E",X"4B",X"E7",X"3C",X"95",X"AD",X"1D",X"D8",X"72",X"35",
-		X"B4",X"A5",X"2F",X"B3",X"B6",X"44",X"57",X"93",X"CB",X"67",X"3F",X"A1",X"C7",X"21",X"89",X"9C",
-		X"5A",X"D8",X"20",X"A3",X"BA",X"25",X"89",X"AD",X"37",X"D8",X"5D",X"53",X"DC",X"77",X"43",X"70",
-		X"E1",X"46",X"59",X"83",X"CC",X"6E",X"37",X"E7",X"56",X"4E",X"86",X"D3",X"27",X"9E",X"AA",X"44",
-		X"C0",X"19",X"E9",X"54",X"63",X"DB",X"51",X"4D",X"88",X"CF",X"30",X"91",X"C5",X"66",X"35",X"C1",
-		X"9C",X"33",X"79",X"A7",X"BA",X"53",X"41",X"DD",X"4B",X"73",X"D2",X"25",X"7F",X"BB",X"9D",X"37",
-		X"68",X"A9",X"BD",X"3B",X"5C",X"CF",X"61",X"47",X"C9",X"9E",X"47",X"55",X"AF",X"96",X"5D",X"D0",
-		X"28",X"7E",X"D3",X"48",X"51",X"C7",X"95",X"21",X"BB",X"A6",X"3A",X"67",X"C3",X"81",X"37",X"DE",
-		X"7D",X"3F",X"72",X"AA",X"B4",X"15",X"DC",X"6C",X"47",X"D2",X"71",X"28",X"EB",X"2E",X"9F",X"93",
-		X"6C",X"9C",X"37",X"DB",X"43",X"AC",X"37",X"D3",X"4F",X"AC",X"8D",X"1B",X"DF",X"7E",X"46",X"6B",
-		X"BA",X"A5",X"35",X"73",X"CB",X"41",X"7E",X"C8",X"1D",X"D3",X"60",X"5F",X"DB",X"44",X"57",X"C2",
-		X"A2",X"41",X"5B",X"AE",X"96",X"5E",X"CC",X"10",X"CF",X"83",X"31",X"DF",X"59",X"46",X"CC",X"87",
-		X"28",X"D7",X"84",X"3D",X"7A",X"DD",X"3A",X"7B",X"C8",X"36",X"66",X"C8",X"60",X"9A",X"8F",X"29",
-		X"A8",X"B3",X"83",X"1F",X"D6",X"81",X"33",X"C4",X"82",X"2A",X"D4",X"6B",X"70",X"CA",X"1B",X"A9",
-		X"AB",X"22",X"AE",X"9E",X"49",X"D3",X"45",X"5A",X"A1",X"BB",X"70",X"27",X"E9",X"49",X"72",X"CC",
-		X"38",X"67",X"B6",X"AD",X"41",X"57",X"B7",X"8C",X"39",X"E4",X"70",X"4B",X"63",X"C7",X"52",X"AE",
-		X"8A",X"36",X"8A",X"BB",X"8E",X"2F",X"87",X"AB",X"B2",X"2D",X"72",X"94",X"CD",X"39",X"67",X"D9",
-		X"2B",X"86",X"C8",X"50",X"4D",X"BC",X"A1",X"3F",X"6B",X"BC",X"7C",X"48",X"E0",X"20",X"BA",X"83",
-		X"43",X"D4",X"26",X"BD",X"A2",X"3E",X"6C",X"CA",X"8A",X"38",X"7B",X"AF",X"AE",X"23",X"91",X"C0",
-		X"37",X"76",X"A3",X"C2",X"39",X"63",X"D9",X"48",X"5A",X"93",X"C9",X"43",X"62",X"90",X"B1",X"37",
-		X"D1",X"53",X"74",X"B1",X"37",X"F6",X"23",X"82",X"C3",X"52",X"4A",X"BB",X"75",X"95",X"88",X"3D",
-		X"90",X"C3",X"76",X"3B",X"87",X"A9",X"70",X"A6",X"61",X"4F",X"AE",X"B6",X"50",X"4B",X"E2",X"4A",
-		X"63",X"DC",X"3E",X"63",X"92",X"CC",X"4F",X"4D",X"E3",X"4A",X"5B",X"89",X"D0",X"47",X"5E",X"90",
-		X"D0",X"49",X"5B",X"7E",X"C6",X"76",X"3E",X"8C",X"AA",X"A4",X"15",X"CD",X"89",X"43",X"80",X"BD",
-		X"65",X"A8",X"3D",X"8E",X"CF",X"0B",X"C0",X"8E",X"46",X"76",X"C9",X"7A",X"3E",X"88",X"AA",X"A8",
-		X"18",X"BF",X"9C",X"2E",X"C3",X"85",X"2B",X"DC",X"6C",X"45",X"DB",X"4B",X"5F",X"92",X"AD",X"3D",
-		X"C3",X"4F",X"86",X"A6",X"75",X"81",X"36",X"E7",X"37",X"A6",X"7D",X"A5",X"5A",X"58",X"D8",X"4E",
-		X"56",X"AB",X"8E",X"49",X"DD",X"68",X"40",X"8A",X"B0",X"53",X"C3",X"4F",X"60",X"92",X"C6",X"51",
-		X"54",X"9A",X"C5",X"55",X"4D",X"93",X"C2",X"70",X"2F",X"E3",X"50",X"5B",X"8D",X"AF",X"48",X"AA",
-		X"81",X"98",X"4C",X"65",X"C1",X"66",X"BB",X"23",X"B0",X"9B",X"39",X"83",X"A4",X"B3",X"1A",X"B0",
-		X"9D",X"31",X"C3",X"8E",X"2B",X"E2",X"54",X"5A",X"DC",X"32",X"86",X"CA",X"14",X"C9",X"83",X"43",
-		X"83",X"AD",X"A6",X"15",X"DA",X"6D",X"4C",X"87",X"AF",X"63",X"B9",X"3A",X"8C",X"C5",X"0D",X"CC",
-		X"79",X"58",X"74",X"C9",X"7D",X"42",X"7C",X"B7",X"5C",X"A9",X"7B",X"41",X"93",X"B6",X"81",X"32",
-		X"9D",X"92",X"6B",X"87",X"9D",X"94",X"4A",X"6C",X"B7",X"A4",X"1B",X"BD",X"88",X"4D",X"7D",X"BD",
-		X"4D",X"99",X"8A",X"51",X"CF",X"1B",X"F2",X"56",X"5A",X"72",X"C3",X"4B",X"BE",X"63",X"52",X"E1",
-		X"2F",X"77",X"91",X"93",X"52",X"C0",X"37",X"E1",X"53",X"5A",X"DA",X"35",X"77",X"85",X"D5",X"39",
-		X"6D",X"80",X"D3",X"50",X"58",X"D3",X"2D",X"9A",X"B2",X"23",X"BC",X"8C",X"52",X"71",X"C1",X"8D",
-		X"3E",X"76",X"B3",X"6F",X"6D",X"A1",X"49",X"C9",X"2E",X"D1",X"38",X"C6",X"55",X"8B",X"7C",X"86",
-		X"B2",X"33",X"7E",X"AD",X"99",X"3C",X"80",X"A3",X"6E",X"88",X"98",X"50",X"AA",X"79",X"99",X"27",
-		X"FB",X"1D",X"AE",X"63",X"8F",X"94",X"51",X"B0",X"4A",X"AD",X"86",X"8B",X"39",X"EA",X"1B",X"AB",
-		X"9A",X"4C",X"73",X"B8",X"9A",X"3A",X"76",X"AC",X"64",X"88",X"8B",X"6D",X"A6",X"71",X"97",X"40",
-		X"8C",X"B5",X"4A",X"A0",X"68",X"86",X"8C",X"98",X"69",X"59",X"DE",X"1F",X"AB",X"A0",X"36",X"A8",
-		X"A7",X"28",X"E0",X"58",X"59",X"CE",X"37",X"82",X"C8",X"2E",X"A4",X"5A",X"AF",X"62",X"8E",X"C2",
-		X"2D",X"79",X"91",X"C2",X"2A",X"96",X"77",X"8A",X"99",X"8E",X"3D",X"C7",X"61",X"57",X"9D",X"A3",
-		X"44",X"DE",X"34",X"88",X"B1",X"37",X"89",X"A3",X"B3",X"15",X"CB",X"73",X"43",X"BA",X"8D",X"47",
-		X"9D",X"6F",X"C9",X"15",X"D1",X"72",X"53",X"CA",X"48",X"6B",X"9B",X"89",X"6A",X"A0",X"57",X"BE",
-		X"45",X"9C",X"A5",X"5E",X"54",X"CA",X"63",X"52",X"E1",X"25",X"AE",X"93",X"35",X"E5",X"2A",X"A5",
-		X"97",X"40",X"8A",X"9A",X"73",X"81",X"8E",X"57",X"CC",X"68",X"67",X"5D",X"C5",X"94",X"43",X"6E",
-		X"AA",X"A8",X"30",X"9D",X"6E",X"B3",X"6B",X"4B",X"AB",X"79",X"90",X"93",X"50",X"89",X"81",X"8A",
-		X"A4",X"42",X"9B",X"7F",X"67",X"9F",X"A8",X"48",X"80",X"BA",X"23",X"C5",X"6A",X"5E",X"91",X"99",
-		X"62",X"9A",X"91",X"6A",X"5A",X"D9",X"3D",X"81",X"B2",X"34",X"C5",X"7A",X"3F",X"BB",X"90",X"3D",
-		X"D0",X"50",X"65",X"95",X"94",X"63",X"C6",X"2D",X"A6",X"91",X"3D",X"CA",X"5F",X"66",X"91",X"97",
-		X"A6",X"35",X"A6",X"97",X"2E",X"D9",X"41",X"8F",X"A4",X"3E",X"A2",X"B0",X"2E",X"B5",X"7A",X"55",
-		X"C9",X"3F",X"84",X"C3",X"42",X"8A",X"72",X"9F",X"65",X"95",X"72",X"84",X"8A",X"58",X"C6",X"73",
-		X"47",X"D9",X"35",X"90",X"9F",X"4D",X"80",X"A8",X"A1",X"30",X"8F",X"8B",X"C5",X"18",X"B5",X"70",
-		X"65",X"B0",X"5D",X"93",X"93",X"7B",X"48",X"CB",X"52",X"7D",X"B0",X"3D",X"98",X"BA",X"2E",X"AD",
-		X"86",X"4A",X"BD",X"6E",X"4C",X"DA",X"53",X"78",X"77",X"96",X"75",X"83",X"82",X"82",X"A5",X"3D",
-		X"86",X"A2",X"A7",X"31",X"8B",X"8E",X"C3",X"20",X"AA",X"92",X"3A",X"C0",X"87",X"51",X"77",X"AD",
-		X"62",X"B9",X"4F",X"7F",X"BC",X"1E",X"BF",X"7E",X"51",X"C3",X"50",X"72",X"C0",X"49",X"8A",X"81",
-		X"72",X"AA",X"7B",X"55",X"8C",X"83",X"CA",X"2B",X"97",X"9C",X"4B",X"86",X"9F",X"B0",X"14",X"EA",
-		X"3C",X"8A",X"9B",X"51",X"C2",X"25",X"C7",X"70",X"5F",X"AF",X"52",X"C6",X"29",X"B8",X"7F",X"5F",
-		X"A3",X"5C",X"CB",X"26",X"AE",X"8B",X"3C",X"D6",X"48",X"8A",X"74",X"A2",X"8D",X"3F",X"D3",X"2A",
-		X"B9",X"7B",X"4D",X"A6",X"69",X"B6",X"6E",X"56",X"8A",X"A1",X"64",X"C3",X"28",X"B2",X"7D",X"60",
-		X"A6",X"58",X"D4",X"11",X"D1",X"5C",X"7A",X"A8",X"42",X"96",X"C7",X"27",X"A9",X"90",X"44",X"89",
-		X"9F",X"69",X"90",X"A7",X"25",X"DB",X"46",X"7C",X"B7",X"42",X"9A",X"6E",X"99",X"8C",X"81",X"41",
-		X"C7",X"7A",X"58",X"8D",X"83",X"B2",X"29",X"C1",X"6E",X"52",X"DA",X"44",X"83",X"B6",X"2A",X"C4",
-		X"41",X"A6",X"7A",X"76",X"98",X"5B",X"B6",X"86",X"42",X"A2",X"8A",X"4B",X"95",X"97",X"65",X"B7",
-		X"56",X"6C",X"D2",X"1E",X"B6",X"94",X"36",X"DD",X"38",X"96",X"7B",X"70",X"9E",X"95",X"59",X"77",
-		X"82",X"8D",X"7C",X"78",X"DC",X"01",X"CD",X"70",X"5D",X"76",X"B4",X"91",X"35",X"BD",X"48",X"D3",
-		X"36",X"8E",X"B7",X"2C",X"BE",X"49",X"CA",X"4C",X"72",X"CB",X"29",X"B9",X"82",X"3B",X"CC",X"71",
-		X"4B",X"D1",X"4F",X"6A",X"8D",X"C9",X"46",X"6A",X"CA",X"28",X"99",X"A9",X"61",X"59",X"AA",X"78",
-		X"8F",X"98",X"35",X"CE",X"64",X"58",X"95",X"A7",X"49",X"AC",X"57",X"9B",X"7C",X"70",X"DE",X"14",
-		X"A9",X"A3",X"3F",X"7B",X"C9",X"57",X"5F",X"D6",X"17",X"C5",X"7D",X"58",X"9E",X"71",X"B8",X"3D",
-		X"72",X"A7",X"6C",X"A7",X"80",X"3A",X"E5",X"22",X"A5",X"61",X"B6",X"86",X"38",X"D9",X"56",X"57",
-		X"9A",X"8E",X"64",X"97",X"96",X"7D",X"45",X"CC",X"5D",X"5A",X"A8",X"AA",X"3C",X"7E",X"97",X"C1",
-		X"22",X"9B",X"A7",X"45",X"7F",X"A1",X"B4",X"1D",X"BB",X"51",X"B9",X"7A",X"45",X"91",X"A5",X"67",
-		X"B8",X"34",X"9E",X"A8",X"35",X"88",X"B0",X"54",X"A8",X"8C",X"31",X"E7",X"41",X"6A",X"C7",X"41",
-		X"85",X"BA",X"2D",X"B1",X"A0",X"35",X"90",X"9F",X"75",X"A0",X"5D",X"52",X"CA",X"59",X"84",X"9A",
-		X"52",X"B2",X"66",X"AF",X"43",X"6E",X"BC",X"59",X"89",X"95",X"8B",X"74",X"44",X"AE",X"85",X"96",
-		X"7B",X"4A",X"8B",X"BD",X"7E",X"2F",X"D2",X"68",X"4D",X"D9",X"41",X"6F",X"CA",X"4D",X"62",X"A0",
-		X"B7",X"3C",X"76",X"D1",X"2E",X"98",X"B1",X"2A",X"BB",X"8D",X"2F",X"E2",X"4A",X"6C",X"C4",X"49",
-		X"64",X"A5",X"88",X"80",X"9E",X"2A",X"DD",X"59",X"54",X"CE",X"60",X"54",X"9E",X"9D",X"42",X"BF",
-		X"92",X"34",X"98",X"B7",X"40",X"77",X"9F",X"BC",X"28",X"93",X"B8",X"44",X"67",X"A7",X"AC",X"41",
-		X"6F",X"9F",X"91",X"50",X"C4",X"37",X"B1",X"7A",X"5B",X"DD",X"4C",X"58",X"C6",X"5D",X"51",X"BA",
-		X"82",X"47",X"D6",X"6B",X"45",X"AC",X"60",X"C5",X"3D",X"7D",X"CA",X"33",X"8D",X"AE",X"42",X"88",
-		X"CB",X"4F",X"5D",X"84",X"C3",X"31",X"B4",X"6B",X"6C",X"AD",X"73",X"AB",X"23",X"D5",X"6B",X"43",
-		X"D1",X"6A",X"47",X"CB",X"4B",X"77",X"C4",X"2B",X"BC",X"94",X"35",X"C6",X"77",X"3E",X"9E",X"94",
-		X"77",X"A5",X"43",X"7C",X"99",X"BD",X"3A",X"79",X"C8",X"2B",X"B8",X"83",X"37",X"D2",X"77",X"4F",
-		X"78",X"BD",X"43",X"AC",X"80",X"66",X"C8",X"28",X"89",X"A3",X"AF",X"2A",X"92",X"B9",X"3D",X"80",
-		X"CC",X"27",X"9A",X"B0",X"48",X"66",X"AD",X"8D",X"44",X"D0",X"6A",X"44",X"AA",X"87",X"6B",X"C7",
-		X"25",X"A3",X"AB",X"41",X"70",X"AD",X"71",X"9C",X"74",X"45",X"C9",X"91",X"51",X"5D",X"D9",X"4E",
-		X"62",X"C7",X"61",X"4C",X"A4",X"97",X"78",X"95",X"3D",X"9E",X"A8",X"30",X"D4",X"4B",X"81",X"B2",
-		X"33",X"C5",X"65",X"A4",X"63",X"4E",X"A8",X"98",X"5F",X"C0",X"30",X"96",X"B5",X"3D",X"75",X"B2",
-		X"92",X"31",X"B1",X"A5",X"33",X"A4",X"AD",X"43",X"68",X"B4",X"7A",X"51",X"DB",X"45",X"74",X"C9",
-		X"2D",X"95",X"AD",X"3B",X"8E",X"A9",X"3D",X"C0",X"70",X"62",X"D5",X"27",X"A7",X"9E",X"3F",X"7C",
-		X"BC",X"50",X"A4",X"8E",X"34",X"A3",X"A1",X"4E",X"99",X"BC",X"35",X"7B",X"BD",X"67",X"45",X"AA",
-		X"94",X"62",X"C1",X"3E",X"74",X"CB",X"41",X"74",X"A3",X"50",X"B6",X"9F",X"47",X"68",X"A6",X"AF",
-		X"4A",X"62",X"94",X"AC",X"3F",X"AD",X"A9",X"3F",X"72",X"8A",X"C7",X"54",X"5E",X"7A",X"C0",X"80",
-		X"4D",X"6B",X"B7",X"71",X"86",X"9F",X"2C",X"DC",X"60",X"59",X"79",X"BB",X"7C",X"40",X"A8",X"AC",
-		X"63",X"48",X"D4",X"67",X"56",X"79",X"B8",X"8D",X"38",X"BE",X"7E",X"3C",X"B0",X"97",X"54",X"C2",
-		X"37",X"98",X"B4",X"32",X"90",X"B9",X"4F",X"5E",X"B2",X"A0",X"34",X"9F",X"A3",X"35",X"AD",X"9B",
-		X"38",X"BB",X"97",X"4E",X"64",X"A4",X"94",X"53",X"D0",X"45",X"6A",X"C2",X"6E",X"42",X"CC",X"77",
-		X"52",X"73",X"BB",X"61",X"89",X"B2",X"2D",X"9C",X"B4",X"43",X"77",X"C5",X"57",X"59",X"93",X"A6",
-		X"5B",X"B6",X"50",X"63",X"BE",X"8D",X"4D",X"6A",X"A2",X"AA",X"6F",X"3F",X"C2",X"86",X"4B",X"75",
-		X"BD",X"76",X"4B",X"D2",X"5A",X"5A",X"8A",X"BF",X"5B",X"56",X"B3",X"9F",X"4E",X"66",X"C4",X"5D",
-		X"51",X"C0",X"68",X"70",X"C1",X"3E",X"75",X"BB",X"50",X"A6",X"88",X"3A",X"AB",X"A4",X"79",X"3A",
-		X"BC",X"8E",X"4A",X"74",X"B7",X"82",X"42",X"D2",X"5F",X"5A",X"7F",X"B4",X"8D",X"41",X"86",X"C0",
-		X"55",X"5F",X"C0",X"44",X"96",X"B6",X"5A",X"5A",X"84",X"BD",X"78",X"52",X"6C",X"BA",X"82",X"41",
-		X"BD",X"83",X"3E",X"A9",X"91",X"56",X"CA",X"38",X"95",X"AA",X"39",X"8B",X"AE",X"4D",X"8C",X"AC",
-		X"35",X"BC",X"79",X"52",X"C1",X"5A",X"80",X"C2",X"41",X"73",X"A8",X"4C",X"B1",X"9C",X"63",X"4F",
-		X"BB",X"8B",X"4B",X"70",X"B2",X"7F",X"46",X"D3",X"48",X"A3",X"94",X"3D",X"94",X"B6",X"52",X"61",
-		X"BD",X"49",X"91",X"B9",X"58",X"61",X"77",X"BD",X"4D",X"A9",X"84",X"43",X"CF",X"6A",X"58",X"74",
-		X"C2",X"57",X"93",X"61",X"84",X"BB",X"2E",X"B6",X"86",X"4B",X"C7",X"71",X"54",X"76",X"AF",X"73",
-		X"5D",X"D2",X"40",X"85",X"B7",X"59",X"5A",X"94",X"AF",X"40",X"9D",X"A1",X"32",X"BD",X"71",X"72",
-		X"BC",X"51",X"60",X"97",X"AC",X"7F",X"47",X"8D",X"B7",X"57",X"5B",X"C1",X"7B",X"52",X"73",X"AB",
-		X"8B",X"44",X"C1",X"82",X"42",X"BD",X"75",X"4B",X"B0",X"9D",X"6A",X"50",X"8A",X"AD",X"8E",X"53",
-		X"65",X"9C",X"AE",X"65",X"51",X"AF",X"99",X"43",X"80",X"B4",X"7E",X"3D",X"B9",X"6B",X"66",X"C2",
-		X"45",X"B4",X"81",X"50",X"72",X"BC",X"6E",X"4E",X"BA",X"7A",X"4A",X"C1",X"6F",X"5A",X"BB",X"89",
-		X"5C",X"5E",X"9B",X"AF",X"5E",X"5C",X"CA",X"43",X"87",X"B0",X"41",X"85",X"BA",X"4D",X"77",X"BA",
-		X"76",X"4A",X"A7",X"9D",X"54",X"61",X"AA",X"9C",X"47",X"7B",X"B2",X"8B",X"51",X"6C",X"9A",X"A4",
-		X"42",X"A4",X"A6",X"3A",X"A5",X"97",X"3F",X"9E",X"A7",X"78",X"4E",X"7F",X"B1",X"8A",X"58",X"64",
-		X"B8",X"88",X"48",X"87",X"B5",X"6E",X"49",X"BE",X"59",X"93",X"A5",X"46",X"74",X"9E",X"A3",X"35",
-		X"C2",X"72",X"55",X"C2",X"5B",X"60",X"B9",X"79",X"48",X"C8",X"57",X"84",X"B1",X"4B",X"6C",X"97",
-		X"AC",X"3F",X"8C",X"AF",X"47",X"AF",X"89",X"4A",X"7D",X"A4",X"9E",X"4F",X"6A",X"B1",X"8E",X"45",
-		X"88",X"B2",X"70",X"4B",X"A7",X"9C",X"41",X"AD",X"96",X"49",X"7B",X"B6",X"77",X"4B",X"B4",X"8D",
-		X"56",X"67",X"A2",X"A0",X"3E",X"B2",X"84",X"45",X"AC",X"9A",X"78",X"44",X"B1",X"80",X"52",X"C9",
-		X"4B",X"7E",X"B7",X"3C",X"A1",X"99",X"40",X"9F",X"A3",X"7C",X"4C",X"8A",X"B0",X"76",X"4C",X"9D",
-		X"A6",X"3F",X"9C",X"A5",X"5E",X"5C",X"B7",X"85",X"4E",X"7E",X"B4",X"6A",X"56",X"CD",X"4B",X"99",
-		X"6F",X"69",X"C4",X"45",X"89",X"B2",X"60",X"60",X"7F",X"BB",X"57",X"6E",X"B4",X"84",X"66",X"59",
-		X"BD",X"4A",X"9F",X"A0",X"5B",X"5F",X"A1",X"A4",X"65",X"57",X"94",X"A3",X"8E",X"46",X"8A",X"9B",
-		X"58",X"B7",X"78",X"4C",X"9B",X"A1",X"40",X"AF",X"87",X"42",X"B4",X"80",X"5E",X"BB",X"4B",X"7D",
-		X"BB",X"42",X"95",X"A1",X"42",X"AA",X"98",X"59",X"64",X"A4",X"A0",X"5F",X"5D",X"9C",X"A7",X"66",
-		X"57",X"A0",X"A4",X"5E",X"61",X"8A",X"B4",X"4D",X"92",X"A5",X"55",X"68",X"8F",X"B1",X"55",X"6C",
-		X"BE",X"51",X"88",X"A6",X"36",X"C2",X"6C",X"60",X"B2",X"84",X"4D",X"84",X"A8",X"4A",X"A5",X"9E",
-		X"60",X"5D",X"AD",X"92",X"76",X"4E",X"94",X"A8",X"72",X"4C",X"B0",X"7A",X"57",X"B8",X"85",X"72",
-		X"51",X"C2",X"59",X"6C",X"B1",X"86",X"69",X"5A",X"92",X"A9",X"7B",X"50",X"8B",X"B3",X"41",X"AD",
-		X"6F",X"61",X"B7",X"82",X"6E",X"55",X"A0",X"9F",X"4B",X"87",X"B1",X"52",X"9B",X"96",X"59",X"68",
-		X"B7",X"55",X"85",X"B1",X"64",X"65",X"70",X"BB",X"6A",X"5F",X"B0",X"8A",X"76",X"55",X"82",X"AE",
-		X"82",X"5F",X"66",X"A1",X"9C",X"48",X"B7",X"67",X"60",X"B8",X"76",X"4D",X"B7",X"76",X"62",X"B1",
-		X"7C",X"55",X"84",X"AD",X"77",X"55",X"8B",X"AC",X"40",X"9A",X"A1",X"75",X"57",X"7D",X"A6",X"91",
-		X"75",X"5C",X"74",X"AE",X"7D",X"52",X"C1",X"58",X"74",X"B7",X"45",X"95",X"A1",X"70",X"57",X"89",
-		X"AA",X"81",X"5B",X"6D",X"9F",X"9E",X"6F",X"57",X"AB",X"8E",X"63",X"5E",X"B0",X"80",X"4E",X"B1",
-		X"88",X"4C",X"9E",X"9A",X"46",X"98",X"A4",X"6C",X"55",X"B0",X"84",X"56",X"B8",X"48",X"92",X"A3",
-		X"7D",X"69",X"5C",X"A6",X"98",X"51",X"83",X"B5",X"4C",X"8E",X"A3",X"69",X"5E",X"80",X"AF",X"6B",
-		X"5B",X"B3",X"7C",X"52",X"B1",X"88",X"81",X"50",X"88",X"A7",X"83",X"54",X"82",X"AB",X"46",X"9F",
-		X"9F",X"4B",X"94",X"9F",X"42",X"A8",X"92",X"84",X"59",X"77",X"B3",X"46",X"A5",X"8C",X"4A",X"AE",
-		X"8A",X"59",X"A9",X"82",X"67",X"60",X"99",X"9F",X"81",X"6A",X"5B",X"BF",X"4F",X"9C",X"82",X"54",
-		X"BA",X"75",X"55",X"A7",X"8A",X"4B",X"A4",X"96",X"82",X"61",X"67",X"9A",X"9E",X"4D",X"8A",X"A7",
-		X"7F",X"73",X"52",X"BB",X"60",X"73",X"AC",X"83",X"73",X"59",X"89",X"A4",X"88",X"50",X"95",X"A2",
-		X"67",X"63",X"7D",X"B0",X"72",X"59",X"A9",X"8F",X"50",X"87",X"AC",X"47",X"9C",X"97",X"7B",X"53",
-		X"92",X"A0",X"7B",X"5B",X"7F",X"B1",X"49",X"8D",X"A4",X"7B",X"66",X"62",X"B4",X"76",X"66",X"AA",
-		X"81",X"62",X"6D",X"AF",X"80",X"6D",X"5C",X"97",X"9C",X"86",X"69",X"60",X"AE",X"80",X"4E",X"B9",
-		X"66",X"6D",X"AA",X"83",X"64",X"69",X"AD",X"86",X"6B",X"60",X"8C",X"AA",X"65",X"66",X"AF",X"80",
-		X"51",X"9A",X"9B",X"7B",X"72",X"57",X"A5",X"92",X"87",X"67",X"66",X"86",X"B2",X"58",X"8E",X"8B",
-		X"5F",X"B0",X"71",X"6B",X"63",X"A7",X"8F",X"85",X"67",X"63",X"B2",X"61",X"6F",X"AE",X"81",X"7F",
-		X"4E",X"A4",X"8D",X"51",X"9F",X"99",X"73",X"62",X"75",X"B6",X"66",X"79",X"9F",X"50",X"B7",X"4C",
-		X"8E",X"9E",X"7D",X"5C",X"7F",X"AF",X"4B",X"8D",X"A1",X"7D",X"65",X"66",X"AE",X"7B",X"62",X"AD",
-		X"7B",X"6C",X"5F",X"A8",X"8D",X"84",X"66",X"65",X"A7",X"8D",X"75",X"58",X"9F",X"97",X"74",X"60",
-		X"79",X"A4",X"8E",X"6A",X"5F",X"A7",X"8D",X"53",X"A7",X"87",X"73",X"57",X"B1",X"74",X"68",X"AD",
-		X"48",X"A0",X"94",X"81",X"6D",X"5F",X"94",X"9C",X"85",X"6D",X"5F",X"97",X"9D",X"78",X"5B",X"87",
-		X"AA",X"5E",X"6C",X"A6",X"8A",X"7A",X"5D",X"7B",X"9E",X"96",X"59",X"7D",X"AB",X"4C",X"98",X"95",
-		X"4B",X"A5",X"8B",X"55",X"A5",X"8D",X"71",X"60",X"84",X"A4",X"84",X"7F",X"5A",X"82",X"AB",X"5B",
-		X"78",X"B2",X"5B",X"7F",X"A2",X"4D",X"94",X"A2",X"51",X"98",X"93",X"78",X"57",X"9B",X"95",X"7D",
-		X"57",X"90",X"9D",X"53",X"A2",X"8D",X"6C",X"65",X"81",X"AD",X"68",X"71",X"A9",X"53",X"A4",X"82",
-		X"7A",X"55",X"A4",X"88",X"53",X"A5",X"8D",X"7F",X"6A",X"63",X"A7",X"87",X"59",X"A5",X"8A",X"77",
-		X"61",X"7B",X"AD",X"73",X"6B",X"A1",X"7F",X"6F",X"60",X"B2",X"6C",X"66",X"AA",X"82",X"81",X"5E",
-		X"75",X"9D",X"92",X"7D",X"6C",X"63",X"B0",X"73",X"60",X"A8",X"86",X"80",X"62",X"71",X"99",X"9A",
-		X"50",X"97",X"92",X"51",X"9D",X"96",X"51",X"A5",X"79",X"5D",X"AA",X"85",X"80",X"64",X"6D",X"AB",
-		X"77",X"64",X"A9",X"82",X"77",X"5F",X"85",X"A1",X"85",X"7F",X"5B",X"88",X"A4",X"4E",X"95",X"98",
-		X"81",X"69",X"69",X"B1",X"55",X"90",X"99",X"4F",X"A7",X"7E",X"59",X"AA",X"7C",X"5B",X"9E",X"92",
-		X"7E",X"70",X"5F",X"A1",X"8F",X"85",X"5F",X"78",X"A6",X"7F",X"77",X"5A",X"A0",X"87",X"58",X"A0",
-		X"93",X"59",X"97",X"94",X"5B",X"76",X"9F",X"8E",X"63",X"72",X"AC",X"57",X"81",X"A6",X"66",X"68",
-		X"A7",X"83",X"5C",X"A7",X"80",X"7A",X"59",X"97",X"9A",X"5D",X"7A",X"AD",X"66",X"72",X"A1",X"80",
-		X"70",X"62",X"A7",X"85",X"7B",X"5F",X"7E",X"9D",X"8E",X"73",X"5F",X"93",X"9D",X"63",X"6D",X"AA",
-		X"7B",X"89",X"5B",X"7F",X"A0",X"84",X"64",X"78",X"A5",X"7A",X"75",X"5E",X"9C",X"93",X"7F",X"7C",
-		X"58",X"A0",X"8D",X"80",X"61",X"77",X"9D",X"91",X"65",X"71",X"A4",X"80",X"76",X"5E",X"A4",X"89",
-		X"7C",X"62",X"78",X"9D",X"8D",X"7D",X"6C",X"68",X"B0",X"69",X"78",X"A3",X"54",X"9F",X"8A",X"79",
-		X"63",X"7A",X"9E",X"8D",X"64",X"71",X"AD",X"6D",X"6D",X"9D",X"86",X"6F",X"68",X"82",X"A8",X"6A",
-		X"74",X"A2",X"7A",X"73",X"61",X"B1",X"66",X"73",X"A8",X"5C",X"7D",X"A7",X"6C",X"6C",X"AA",X"56",
-		X"97",X"89",X"55",X"A7",X"85",X"85",X"6E",X"66",X"A6",X"82",X"82",X"5F",X"81",X"A5",X"55",X"8A",
-		X"9C",X"7C",X"81",X"5B",X"8A",X"9F",X"5E",X"7E",X"A9",X"5D",X"79",X"9E",X"87",X"61",X"76",X"9E",
-		X"8C",X"65",X"72",X"A2",X"83",X"78",X"60",X"A2",X"86",X"7C",X"5E",X"9B",X"8C",X"56",X"AD",X"66",
-		X"71",X"A3",X"81",X"82",X"66",X"74",X"AE",X"5E",X"82",X"9B",X"58",X"8E",X"9E",X"63",X"72",X"A1",
-		X"84",X"72",X"62",X"9F",X"8B",X"81",X"73",X"65",X"89",X"9D",X"7F",X"84",X"5E",X"84",X"9E",X"7C",
-		X"7B",X"5E",X"8B",X"96",X"8C",X"56",X"96",X"90",X"80",X"66",X"74",X"9A",X"92",X"61",X"78",X"9E",
-		X"87",X"69",X"72",X"A2",X"7F",X"76",X"63",X"8B",X"9A",X"83",X"5B",X"8F",X"98",X"7B",X"7F",X"5B",
-		X"92",X"98",X"5A",X"9D",X"86",X"81",X"62",X"80",X"A0",X"7B",X"76",X"61",X"9A",X"91",X"80",X"7B",
-		X"5E",X"91",X"96",X"7F",X"6E",X"69",X"99",X"94",X"64",X"75",X"A6",X"74",X"64",X"8F",X"9D",X"65",
-		X"72",X"A1",X"83",X"74",X"62",X"9F",X"89",X"82",X"72",X"67",X"88",X"9D",X"7A",X"62",X"AC",X"5A",
-		X"8F",X"90",X"7F",X"6E",X"6B",X"8E",X"9D",X"61",X"86",X"9B",X"56",X"9D",X"88",X"7C",X"64",X"7B",
-		X"99",X"8E",X"5E",X"7F",X"9F",X"7F",X"83",X"63",X"7D",X"A5",X"6A",X"6C",X"99",X"8F",X"57",X"A1",
-		X"7C",X"68",X"9C",X"86",X"6B",X"72",X"A2",X"7B",X"81",X"5C",X"98",X"90",X"77",X"61",X"A5",X"71",
-		X"6B",X"A0",X"87",X"73",X"68",X"A2",X"80",X"80",X"63",X"7D",X"9E",X"81",X"60",X"A2",X"77",X"69",
-		X"A8",X"6B",X"6D",X"9D",X"83",X"7E",X"65",X"7C",X"9D",X"86",X"62",X"80",X"A1",X"6F",X"68",X"A0",
-		X"83",X"84",X"6C",X"6E",X"92",X"9A",X"5D",X"8C",X"8F",X"5F",X"A1",X"7F",X"7F",X"65",X"7B",X"98",
-		X"8C",X"61",X"7C",X"A1",X"78",X"66",X"A3",X"68",X"75",X"A3",X"7A",X"87",X"69",X"70",X"8E",X"97",
-		X"7C",X"62",X"93",X"90",X"79",X"6B",X"74",X"A0",X"83",X"63",X"87",X"9E",X"6D",X"70",X"A1",X"60",
-		X"8E",X"91",X"7A",X"73",X"68",X"97",X"8E",X"84",X"73",X"68",X"8D",X"9A",X"75",X"66",X"9E",X"7F",
-		X"60",X"9A",X"8E",X"61",X"8D",X"92",X"57",X"96",X"8E",X"81",X"79",X"65",X"9C",X"87",X"7A",X"67",
-		X"80",X"9E",X"7D",X"85",X"64",X"7B",X"9B",X"85",X"72",X"68",X"98",X"8F",X"74",X"66",X"9A",X"89",
-		X"5D",X"8D",X"96",X"7C",X"60",X"A1",X"7C",X"69",X"9D",X"81",X"78",X"65",X"A2",X"78",X"69",X"A8",
-		X"62",X"83",X"95",X"7E",X"76",X"67",X"8B",X"97",X"7B",X"61",X"A7",X"6B",X"76",X"9C",X"7F",X"77",
-		X"66",X"91",X"95",X"77",X"64",X"98",X"8E",X"64",X"7B",X"9D",X"7F",X"61",X"94",X"8F",X"7C",X"66",
-		X"82",X"9D",X"7A",X"87",X"66",X"7A",X"A0",X"6E",X"6D",X"A0",X"7F",X"84",X"71",X"6B",X"9E",X"83",
-		X"7E",X"62",X"90",X"92",X"7B",X"79",X"62",X"A4",X"79",X"70",X"99",X"84",X"62",X"8B",X"92",X"7F",
-		X"74",X"6B",X"8A",X"99",X"75",X"68",X"99",X"8C",X"68",X"77",X"9D",X"7D",X"83",X"6F",X"6D",X"91",
-		X"91",X"83",X"6F",X"6E",X"99",X"8C",X"69",X"76",X"9F",X"79",X"68",X"A1",X"70",X"6D",X"9B",X"86",
-		X"60",X"9C",X"7C",X"6A",X"9F",X"7B",X"84",X"65",X"81",X"A0",X"61",X"89",X"91",X"7D",X"7B",X"65",
-		X"8D",X"95",X"7E",X"83",X"70",X"6D",X"A3",X"73",X"70",X"A1",X"67",X"7F",X"9C",X"5A",X"98",X"7F",
-		X"6B",X"A0",X"78",X"87",X"60",X"8A",X"95",X"7C",X"81",X"61",X"94",X"8E",X"7F",X"7A",X"67",X"88",
-		X"93",X"88",X"6F",X"71",X"A0",X"67",X"78",X"98",X"88",X"6D",X"72",X"9E",X"7E",X"83",X"78",X"67",
-		X"8D",X"92",X"82",X"63",X"8F",X"8F",X"7D",X"7A",X"66",X"8F",X"93",X"7B",X"66",X"A3",X"6B",X"7B",
-		X"97",X"7E",X"74",X"6B",X"9B",X"86",X"7F",X"80",X"66",X"82",X"95",X"87",X"62",X"88",X"95",X"7D",
-		X"82",X"6B",X"77",X"99",X"86",X"66",X"91",X"8C",X"74",X"6C",X"98",X"85",X"7B",X"66",X"97",X"87",
-		X"80",X"74",X"6D",X"8C",X"96",X"73",X"70",X"A1",X"64",X"7A",X"93",X"8D",X"64",X"80",X"96",X"82",
-		X"6F",X"71",X"99",X"87",X"65",X"82",X"98",X"7F",X"82",X"71",X"6F",X"92",X"8D",X"83",X"6E",X"73",
-		X"95",X"8C",X"6E",X"74",X"9A",X"7E",X"82",X"69",X"7E",X"9F",X"62",X"88",X"91",X"64",X"8F",X"8F",
-		X"65",X"7E",X"96",X"83",X"63",X"8D",X"90",X"7F",X"7D",X"67",X"98",X"85",X"7E",X"66",X"92",X"8B",
-		X"7C",X"6C",X"7C",X"9B",X"7C",X"69",X"94",X"86",X"7F",X"72",X"6F",X"8F",X"91",X"78",X"68",X"97",
-		X"89",X"7B",X"67",X"97",X"86",X"80",X"74",X"6C",X"94",X"8C",X"7E",X"82",X"6B",X"7C",X"9F",X"67",
-		X"82",X"96",X"6A",X"77",X"9A",X"7E",X"83",X"78",X"69",X"98",X"86",X"81",X"74",X"6D",X"8C",X"91",
-		X"81",X"7A",X"69",X"99",X"80",X"65",X"90",X"8F",X"7D",X"66",X"96",X"87",X"7F",X"67",X"8D",X"8F",
-		X"61",X"98",X"7F",X"67",X"8E",X"90",X"7D",X"82",X"69",X"7D",X"96",X"86",X"6A",X"7D",X"9D",X"6F",
-		X"76",X"99",X"6E",X"71",X"99",X"83",X"83",X"71",X"71",X"8F",X"91",X"71",X"72",X"9A",X"7D",X"84",
-		X"6A",X"7A",X"8C",X"94",X"6B",X"7D",X"94",X"7F",X"6D",X"79",X"97",X"84",X"67",X"85",X"93",X"81",
-		X"73",X"74",X"9B",X"7A",X"84",X"68",X"80",X"97",X"7E",X"83",X"69",X"82",X"99",X"69",X"82",X"97",
-		X"65",X"87",X"91",X"63",X"93",X"86",X"7F",X"76",X"6C",X"94",X"89",X"82",X"6D",X"78",X"96",X"86",
-		X"69",X"80",X"97",X"79",X"6D",X"97",X"7D",X"6A",X"9A",X"76",X"6D",X"98",X"83",X"81",X"7D",X"6C",
-		X"80",X"93",X"87",X"65",X"96",X"83",X"81",X"78",X"6B",X"99",X"82",X"82",X"73",X"70",X"91",X"8D",
-		X"7C",X"84",X"69",X"80",X"97",X"7B",X"85",X"6C",X"79",X"92",X"8B",X"73",X"71",X"9B",X"75",X"6E",
-		X"91",X"8E",X"70",X"73",X"97",X"84",X"6B",X"80",X"98",X"77",X"70",X"95",X"7F",X"67",X"93",X"89",
-		X"7F",X"7E",X"6B",X"83",X"95",X"7F",X"82",X"78",X"6C",X"98",X"83",X"81",X"79",X"6B",X"96",X"84",
-		X"67",X"95",X"84",X"68",X"8E",X"8F",X"71",X"72",X"8F",X"8F",X"6B",X"80",X"93",X"7A",X"6B",X"91",
-		X"87",X"65",X"90",X"8D",X"74",X"6E",X"93",X"89",X"7D",X"82",X"6B",X"7E",X"93",X"87",X"6B",X"7F",
-		X"97",X"7A",X"86",X"6B",X"7E",X"95",X"7D",X"83",X"71",X"74",X"93",X"88",X"7F",X"7E",X"69",X"96",
-		X"83",X"81",X"79",X"6C",X"8B",X"90",X"7D",X"83",X"77",X"6E",X"8A",X"92",X"77",X"71",X"98",X"78",
-		X"6F",X"9B",X"6E",X"7D",X"94",X"7A",X"83",X"65",X"93",X"88",X"81",X"78",X"6F",X"86",X"96",X"71",
-		X"79",X"94",X"7D",X"80",X"6C",X"7E",X"91",X"87",X"7E",X"80",X"6B",X"80",X"8F",X"8B",X"6B",X"7D",
-		X"95",X"7D",X"83",X"72",X"73",X"92",X"88",X"80",X"6E",X"7C",X"95",X"80",X"6D",X"7F",X"95",X"7D",
-		X"83",X"77",X"6E",X"92",X"88",X"7F",X"6F",X"7A",X"96",X"7F",X"6E",X"80",X"99",X"6B",X"7F",X"90",
-		X"80",X"75",X"72",X"94",X"87",X"75",X"72",X"99",X"78",X"6F",X"8C",X"8F",X"6C",X"7C",X"92",X"80",
-		X"78",X"6E",X"90",X"8C",X"72",X"73",X"96",X"81",X"81",X"6D",X"7F",X"95",X"7D",X"83",X"7B",X"6E",
-		X"83",X"93",X"7E",X"83",X"6A",X"88",X"90",X"66",X"8C",X"8D",X"69",X"86",X"92",X"7B",X"85",X"70",
-		X"76",X"8D",X"8E",X"70",X"78",X"96",X"7C",X"85",X"6F",X"79",X"98",X"74",X"71",X"90",X"89",X"7C",
-		X"83",X"6B",X"83",X"91",X"80",X"80",X"70",X"79",X"90",X"88",X"7E",X"81",X"6E",X"7D",X"98",X"71",
-		X"7B",X"93",X"7A",X"85",X"6B",X"80",X"92",X"81",X"80",X"71",X"79",X"99",X"74",X"78",X"93",X"7C",
-		X"83",X"70",X"78",X"8D",X"8B",X"7E",X"80",X"6C",X"82",X"90",X"84",X"6A",X"8B",X"8C",X"7D",X"81",
-		X"6B",X"8B",X"8F",X"6D",X"82",X"92",X"6C",X"7F",X"94",X"72",X"74",X"91",X"86",X"6D",X"82",X"93",
-		X"69",X"82",X"91",X"80",X"6E",X"81",X"94",X"77",X"73",X"93",X"7C",X"6F",X"97",X"78",X"71",X"8B",
-		X"8F",X"6C",X"82",X"8E",X"7D",X"81",X"6F",X"7C",X"8F",X"87",X"7E",X"80",X"6E",X"7E",X"8E",X"8A",
-		X"70",X"78",X"95",X"7D",X"84",X"78",X"71",X"87",X"91",X"79",X"70",X"91",X"85",X"7C",X"6F",X"8B",
-		X"8C",X"67",X"90",X"82",X"6F",X"91",X"84",X"76",X"72",X"8D",X"8D",X"70",X"7D",X"93",X"6F",X"7D",
-		X"95",X"68",X"88",X"8B",X"80",X"78",X"73",X"96",X"7D",X"84",X"73",X"75",X"93",X"83",X"81",X"77",
-		X"72",X"8E",X"8A",X"7E",X"80",X"6D",X"8C",X"8C",X"6A",X"83",X"8F",X"81",X"6D",X"85",X"8F",X"7E",
-		X"6D",X"88",X"8D",X"7F",X"6F",X"82",X"91",X"7D",X"6F",X"85",X"8F",X"7D",X"7D",X"6D",X"90",X"88",
-		X"7C",X"6E",X"94",X"80",X"70",X"8E",X"87",X"76",X"74",X"92",X"81",X"7D",X"6D",X"8F",X"87",X"7F",
-		X"71",X"7C",X"92",X"81",X"73",X"7A",X"95",X"7C",X"84",X"7B",X"6F",X"8D",X"8A",X"7B",X"71",X"82",
-		X"92",X"79",X"73",X"91",X"7E",X"6D",X"8D",X"89",X"7D",X"83",X"6D",X"84",X"8F",X"7D",X"83",X"70",
-		X"7B",X"8B",X"8B",X"7B",X"85",X"71",X"7A",X"93",X"7E",X"82",X"75",X"75",X"89",X"8D",X"7D",X"6D",
-		X"90",X"85",X"81",X"79",X"71",X"8D",X"8A",X"79",X"72",X"91",X"83",X"7D",X"6F",X"86",X"8E",X"7D",
-		X"70",X"85",X"90",X"7A",X"86",X"74",X"76",X"91",X"82",X"81",X"79",X"72",X"87",X"8D",X"80",X"6D",
-		X"86",X"8E",X"7E",X"82",X"76",X"74",X"89",X"8B",X"82",X"72",X"7F",X"94",X"6F",X"80",X"8D",X"7E",
-		X"73",X"7B",X"92",X"7F",X"71",X"8A",X"89",X"6A",X"89",X"8B",X"81",X"71",X"7F",X"91",X"7C",X"84",
-		X"79",X"72",X"8D",X"89",X"6C",X"8C",X"86",X"7F",X"7C",X"71",X"83",X"8D",X"83",X"7E",X"81",X"6E",
-		X"83",X"8D",X"85",X"71",X"7C",X"91",X"7E",X"82",X"7D",X"70",X"88",X"8D",X"7D",X"83",X"6E",X"84",
-		X"8F",X"7C",X"83",X"70",X"7E",X"90",X"7F",X"82",X"76",X"76",X"93",X"7E",X"83",X"7A",X"72",X"8D",
-		X"89",X"76",X"75",X"92",X"7F",X"83",X"76",X"76",X"92",X"7F",X"6F",X"8A",X"8A",X"7D",X"72",X"83",
-		X"90",X"79",X"75",X"8A",X"87",X"6B",X"89",X"89",X"7F",X"7F",X"71",X"81",X"93",X"70",X"7E",X"8E",
-		X"80",X"79",X"73",X"8E",X"88",X"79",X"72",X"8E",X"86",X"7B",X"72",X"8E",X"85",X"6E",X"8E",X"84",
-		X"6F",X"85",X"8E",X"78",X"74",X"91",X"7C",X"71",X"94",X"7A",X"73",X"8A",X"8C",X"76",X"76",X"8F",
-		X"84",X"7D",X"83",X"6E",X"86",X"8B",X"81",X"71",X"83",X"8D",X"7E",X"78",X"75",X"92",X"81",X"81",
-		X"7D",X"72",X"82",X"8E",X"80",X"80",X"7E",X"70",X"85",X"8C",X"83",X"70",X"80",X"8E",X"7F",X"72",
-		X"81",X"90",X"7A",X"86",X"72",X"7D",X"90",X"77",X"74",X"8C",X"88",X"7D",X"83",X"75",X"78",X"8C",
-		X"88",X"7D",X"83",X"74",X"79",X"8F",X"83",X"6F",X"87",X"8C",X"79",X"73",X"8A",X"89",X"7D",X"83",
-		X"76",X"76",X"8C",X"87",X"7F",X"7D",X"70",X"8C",X"87",X"80",X"71",X"84",X"8D",X"7C",X"73",X"8C",
-		X"83",X"6E",X"89",X"8A",X"7C",X"73",X"90",X"7E",X"83",X"70",X"84",X"8C",X"7E",X"78",X"78",X"93",
-		X"7A",X"73",X"8A",X"89",X"7C",X"84",X"77",X"76",X"90",X"81",X"81",X"7A",X"73",X"8B",X"89",X"71",
-		X"7E",X"8F",X"7E",X"71",X"8B",X"86",X"7F",X"7E",X"70",X"8D",X"87",X"72",X"7D",X"8E",X"82",X"73",
-		X"7E",X"8F",X"7F",X"82",X"7D",X"72",X"88",X"8C",X"6F",X"86",X"89",X"7D",X"81",X"70",X"83",X"8C",
-		X"82",X"70",X"83",X"8C",X"81",X"72",X"80",X"8E",X"7D",X"83",X"7A",X"74",X"86",X"8C",X"7C",X"72",
-		X"87",X"8B",X"7D",X"83",X"78",X"76",X"8F",X"82",X"71",X"8D",X"82",X"80",X"7E",X"72",X"83",X"8D",
-		X"7E",X"83",X"74",X"7E",X"8F",X"7B",X"85",X"74",X"7B",X"8F",X"7F",X"81",X"7B",X"73",X"87",X"8A",
-		X"80",X"72",X"8B",X"84",X"7E",X"80",X"70",X"8B",X"87",X"7E",X"82",X"73",X"7D",X"8C",X"86",X"77",
-		X"79",X"91",X"79",X"77",X"90",X"7A",X"77",X"90",X"79",X"75",X"8B",X"87",X"77",X"79",X"91",X"74",
-		X"7D",X"8C",X"7F",X"72",X"85",X"8B",X"7D",X"72",X"87",X"89",X"7F",X"7B",X"74",X"8D",X"86",X"76",
-		X"7A",X"91",X"74",X"7A",X"8B",X"86",X"78",X"77",X"8E",X"82",X"7F",X"81",X"73",X"7E",X"8C",X"84",
-		X"76",X"7B",X"91",X"77",X"77",X"8A",X"87",X"76",X"79",X"8B",X"86",X"75",X"7B",X"8B",X"85",X"72",
-		X"83",X"89",X"7E",X"7E",X"73",X"8F",X"80",X"73",X"83",X"8D",X"7D",X"84",X"73",X"7E",X"8B",X"84",
-		X"74",X"7D",X"8C",X"82",X"74",X"7F",X"8D",X"80",X"7B",X"74",X"8D",X"84",X"79",X"76",X"8F",X"80",
-		X"82",X"72",X"85",X"8A",X"7C",X"82",X"71",X"85",X"8A",X"7F",X"81",X"76",X"7B",X"8F",X"7F",X"83",
-		X"75",X"7B",X"89",X"89",X"73",X"81",X"8B",X"7C",X"84",X"74",X"7D",X"8C",X"81",X"71",X"89",X"87",
-		X"80",X"72",X"88",X"87",X"7F",X"75",X"82",X"8C",X"7B",X"84",X"73",X"7F",X"8E",X"7A",X"76",X"8D",
-		X"81",X"7E",X"74",X"8C",X"84",X"71",X"85",X"8A",X"7E",X"74",X"86",X"8A",X"7B",X"75",X"8A",X"85",
-		X"71",X"8B",X"83",X"73",X"89",X"85",X"7B",X"75",X"87",X"8A",X"79",X"76",X"8C",X"83",X"7F",X"80",
-		X"73",X"81",X"89",X"86",X"73",X"7D",X"8B",X"84",X"7A",X"76",X"8C",X"83",X"7F",X"75",X"81",X"8D",
-		X"7D",X"84",X"77",X"7A",X"8E",X"7B",X"75",X"8D",X"80",X"81",X"7B",X"75",X"8C",X"84",X"7F",X"73",
-		X"87",X"88",X"7D",X"82",X"75",X"7D",X"8D",X"7F",X"74",X"8D",X"7E",X"75",X"8D",X"7E",X"74",X"88",
-		X"88",X"7A",X"78",X"8D",X"7C",X"75",X"87",X"89",X"7A",X"76",X"88",X"89",X"77",X"7A",X"8E",X"7C",
-		X"74",X"8A",X"85",X"7E",X"82",X"76",X"7B",X"89",X"87",X"72",X"88",X"85",X"7E",X"81",X"74",X"7F",
-		X"88",X"87",X"75",X"7E",X"8E",X"77",X"79",X"8A",X"85",X"77",X"7A",X"8B",X"83",X"76",X"7F",X"8C",
-		X"73",X"7E",X"8B",X"82",X"75",X"7E",X"8C",X"7F",X"77",X"7C",X"8D",X"80",X"75",X"86",X"87",X"73",
-		X"7F",X"8B",X"80",X"7F",X"74",X"89",X"85",X"72",X"89",X"85",X"73",X"88",X"85",X"7D",X"82",X"71",
-		X"8A",X"84",X"83",X"74",X"82",X"89",X"81",X"78",X"7D",X"8C",X"7F",X"7C",X"76",X"8A",X"86",X"7B",
-		X"77",X"8C",X"81",X"80",X"7E",X"74",X"86",X"88",X"82",X"7A",X"78",X"8B",X"83",X"7E",X"82",X"77",
-		X"7B",X"88",X"87",X"7A",X"77",X"86",X"89",X"78",X"7A",X"8C",X"7F",X"81",X"79",X"78",X"87",X"87",
-		X"81",X"76",X"80",X"8D",X"74",X"81",X"89",X"7D",X"83",X"76",X"7D",X"8B",X"81",X"73",X"87",X"88",
-		X"7D",X"76",X"8D",X"7D",X"77",X"8A",X"82",X"7A",X"78",X"89",X"86",X"76",X"7C",X"8B",X"81",X"7D",
-		X"75",X"8B",X"82",X"74",X"8A",X"82",X"74",X"8B",X"81",X"80",X"7E",X"75",X"85",X"8A",X"77",X"7B",
-		X"8A",X"83",X"77",X"7C",X"8B",X"81",X"77",X"7D",X"8D",X"7D",X"83",X"7A",X"78",X"89",X"86",X"7D",
-		X"83",X"79",X"79",X"8A",X"84",X"75",X"80",X"8A",X"80",X"7B",X"78",X"8E",X"7C",X"78",X"8B",X"7F",
-		X"81",X"7C",X"76",X"86",X"87",X"80",X"74",X"85",X"88",X"7B",X"76",X"8C",X"81",X"82",X"78",X"7C",
-		X"8A",X"80",X"7B",X"78",X"8C",X"80",X"7E",X"75",X"87",X"87",X"7D",X"76",X"86",X"88",X"7B",X"77",
-		X"87",X"87",X"79",X"7A",X"8C",X"7B",X"78",X"8C",X"80",X"81",X"7D",X"76",X"85",X"88",X"80",X"7E",
-		X"76",X"86",X"88",X"7D",X"76",X"84",X"89",X"7B",X"79",X"89",X"81",X"80",X"7B",X"77",X"89",X"84",
-		X"80",X"7F",X"75",X"88",X"84",X"7F",X"77",X"7F",X"8B",X"80",X"78",X"7E",X"8C",X"7B",X"79",X"88",
-		X"83",X"77",X"7F",X"8C",X"76",X"7F",X"89",X"7F",X"78",X"7C",X"8B",X"81",X"76",X"83",X"8A",X"74",
-		X"83",X"88",X"75",X"82",X"89",X"74",X"81",X"89",X"7D",X"83",X"77",X"7C",X"8C",X"7E",X"76",X"88",
-		X"86",X"7E",X"83",X"7A",X"79",X"83",X"89",X"7F",X"76",X"88",X"85",X"74",X"84",X"89",X"75",X"82",
-		X"88",X"7D",X"83",X"75",X"80",X"88",X"82",X"7A",X"7B",X"8B",X"7E",X"82",X"7B",X"78",X"88",X"86",
-		X"76",X"83",X"88",X"74",X"83",X"88",X"7E",X"76",X"85",X"87",X"7E",X"82",X"7C",X"78",X"83",X"87",
-		X"83",X"76",X"80",X"89",X"80",X"77",X"81",X"8A",X"7E",X"81",X"7E",X"77",X"81",X"89",X"81",X"78",
-		X"7C",X"8B",X"80",X"82",X"74",X"86",X"85",X"80",X"77",X"82",X"88",X"7F",X"7A",X"7B",X"8C",X"7E",
-		X"82",X"7B",X"78",X"87",X"86",X"7E",X"82",X"76",X"81",X"8A",X"7A",X"79",X"87",X"86",X"7A",X"79",
-		X"89",X"83",X"7F",X"81",X"76",X"83",X"89",X"78",X"7C",X"89",X"82",X"78",X"7C",X"8B",X"7F",X"81",
-		X"7C",X"77",X"87",X"85",X"7E",X"81",X"77",X"7E",X"8A",X"80",X"81",X"7F",X"77",X"81",X"89",X"80",
-		X"80",X"7F",X"76",X"84",X"88",X"7E",X"82",X"79",X"7B",X"87",X"86",X"7C",X"79",X"88",X"83",X"76",
-		X"81",X"88",X"80",X"77",X"81",X"89",X"7D",X"78",X"86",X"84",X"76",X"81",X"88",X"80",X"77",X"85",
-		X"86",X"76",X"7E",X"89",X"81",X"78",X"7F",X"8A",X"7E",X"78",X"89",X"81",X"80",X"7E",X"77",X"82",
-		X"87",X"82",X"7F",X"81",X"78",X"7D",X"88",X"83",X"7F",X"77",X"86",X"85",X"7E",X"82",X"76",X"80",
-		X"88",X"82",X"7E",X"77",X"86",X"85",X"7F",X"77",X"86",X"85",X"7F",X"78",X"81",X"8A",X"75",X"83",
-		X"87",X"77",X"7F",X"8A",X"79",X"7B",X"88",X"84",X"76",X"84",X"85",X"7E",X"78",X"82",X"88",X"7F",
-		X"78",X"84",X"87",X"76",X"7F",X"88",X"82",X"7E",X"82",X"77",X"7F",X"89",X"7E",X"82",X"7B",X"7A",
-		X"87",X"85",X"76",X"81",X"88",X"80",X"77",X"81",X"88",X"7E",X"82",X"7E",X"78",X"82",X"87",X"81",
-		X"77",X"80",X"88",X"7F",X"78",X"81",X"89",X"7E",X"82",X"7E",X"78",X"82",X"88",X"81",X"78",X"7F",
-		X"89",X"7E",X"82",X"7E",X"78",X"83",X"88",X"7A",X"7B",X"88",X"81",X"7E",X"77",X"87",X"84",X"7F",
-		X"78",X"82",X"89",X"75",X"84",X"85",X"7F",X"81",X"78",X"7E",X"8A",X"7E",X"79",X"89",X"80",X"81",
-		X"7D",X"78",X"85",X"86",X"81",X"76",X"86",X"84",X"80",X"79",X"7E",X"88",X"81",X"79",X"7D",X"8A",
-		X"7E",X"82",X"7E",X"7A",X"7D",X"88",X"82",X"81",X"79",X"7F",X"8A",X"79",X"7B",X"88",X"82",X"7F",
-		X"7F",X"77",X"85",X"86",X"7F",X"78",X"82",X"88",X"7F",X"82",X"7B",X"7A",X"86",X"85",X"7F",X"81",
-		X"77",X"82",X"87",X"80",X"78",X"83",X"86",X"7D",X"83",X"77",X"81",X"88",X"7F",X"82",X"7B",X"7A",
-		X"88",X"83",X"77",X"83",X"87",X"78",X"7E",X"88",X"80",X"80",X"7F",X"79",X"7D",X"87",X"83",X"80",
-		X"77",X"83",X"85",X"7F",X"7A",X"7C",X"89",X"81",X"7A",X"7D",X"8A",X"7A",X"7B",X"86",X"84",X"7A",
-		X"7C",X"89",X"7F",X"82",X"7C",X"7A",X"88",X"81",X"77",X"85",X"86",X"77",X"84",X"85",X"77",X"81",
-		X"88",X"78",X"7D",X"87",X"82",X"78",X"81",X"87",X"7A",X"7C",X"89",X"7D",X"79",X"87",X"83",X"7A",
-		X"7C",X"88",X"82",X"7A",X"7D",X"88",X"80",X"78",X"86",X"83",X"76",X"84",X"86",X"7E",X"78",X"86",
-		X"83",X"7E",X"81",X"77",X"81",X"86",X"83",X"79",X"7E",X"88",X"7F",X"81",X"7D",X"79",X"86",X"84",
-		X"7E",X"82",X"77",X"81",X"86",X"82",X"78",X"82",X"86",X"80",X"7D",X"7A",X"89",X"80",X"7F",X"78",
-		X"88",X"81",X"78",X"87",X"81",X"7F",X"81",X"78",X"82",X"88",X"79",X"7F",X"88",X"7B",X"7B",X"85",
-		X"85",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"79",X"84",X"85",X"80",X"80",X"78",X"86",X"84",X"77",
-		X"81",X"87",X"7E",X"82",X"7A",X"7D",X"89",X"7E",X"82",X"7D",X"7A",X"82",X"87",X"7F",X"81",X"7F",
-		X"79",X"83",X"87",X"7A",X"7C",X"87",X"81",X"7E",X"79",X"85",X"85",X"7E",X"79",X"84",X"86",X"79",
-		X"7E",X"88",X"7B",X"7B",X"86",X"83",X"7F",X"82",X"79",X"7E",X"87",X"81",X"7D",X"79",X"86",X"84",
-		X"7F",X"79",X"84",X"85",X"77",X"85",X"84",X"7F",X"81",X"7A",X"7D",X"86",X"83",X"7E",X"82",X"7B",
-		X"7C",X"87",X"81",X"78",X"81",X"86",X"7F",X"79",X"82",X"86",X"7E",X"79",X"81",X"87",X"7E",X"79",
-		X"87",X"82",X"7F",X"80",X"78",X"84",X"85",X"7C",X"7B",X"87",X"81",X"80",X"78",X"86",X"83",X"80",
-		X"7B",X"7C",X"88",X"81",X"7C",X"7C",X"89",X"7B",X"7B",X"85",X"84",X"7B",X"7B",X"85",X"84",X"7C",
-		X"7A",X"86",X"84",X"7C",X"7B",X"87",X"82",X"7F",X"79",X"85",X"84",X"78",X"84",X"84",X"7A",X"7E",
-		X"87",X"81",X"7A",X"81",X"86",X"7A",X"7C",X"87",X"81",X"7F",X"81",X"7A",X"7F",X"88",X"7E",X"7A",
-		X"85",X"83",X"7A",X"7E",X"88",X"7B",X"7D",X"88",X"7D",X"7B",X"87",X"80",X"79",X"84",X"84",X"7E",
-		X"82",X"79",X"7F",X"87",X"80",X"80",X"79",X"83",X"86",X"7F",X"79",X"83",X"85",X"78",X"80",X"87",
-		X"7F",X"81",X"7A",X"7F",X"88",X"7A",X"7E",X"87",X"7F",X"81",X"7D",X"7A",X"84",X"85",X"7F",X"79",
-		X"81",X"87",X"7E",X"82",X"7B",X"7E",X"87",X"7E",X"79",X"84",X"85",X"7E",X"82",X"7C",X"7B",X"84",
-		X"86",X"78",X"83",X"84",X"80",X"7A",X"7E",X"86",X"82",X"7A",X"7E",X"87",X"81",X"7A",X"7F",X"87",
-		X"80",X"7E",X"79",X"86",X"83",X"7F",X"81",X"79",X"81",X"86",X"7E",X"82",X"7B",X"7D",X"87",X"80",
-		X"81",X"7F",X"7A",X"81",X"87",X"7C",X"7B",X"86",X"82",X"7C",X"7B",X"86",X"83",X"7D",X"7A",X"88",
-		X"7E",X"7B",X"85",X"82",X"7B",X"7D",X"87",X"80",X"7E",X"7A",X"85",X"84",X"7E",X"7A",X"85",X"84",
-		X"7E",X"7A",X"84",X"84",X"7E",X"82",X"79",X"80",X"86",X"7E",X"7A",X"85",X"83",X"7F",X"80",X"79",
-		X"85",X"84",X"79",X"82",X"86",X"79",X"81",X"86",X"7B",X"7D",X"87",X"7F",X"79",X"86",X"81",X"79",
-		X"85",X"83",X"79",X"82",X"85",X"78",X"82",X"85",X"7F",X"81",X"7B",X"7D",X"87",X"80",X"80",X"7F",
-		X"7A",X"83",X"86",X"7B",X"7D",X"86",X"81",X"7B",X"7D",X"86",X"82",X"7C",X"7D",X"88",X"7D",X"7B",
-		X"83",X"85",X"7E",X"7A",X"83",X"85",X"7C",X"7C",X"86",X"80",X"7F",X"7A",X"85",X"83",X"79",X"85",
-		X"83",X"7A",X"81",X"86",X"79",X"80",X"85",X"81",X"7E",X"7B",X"87",X"80",X"81",X"7E",X"7B",X"83",
-		X"86",X"79",X"81",X"84",X"80",X"7B",X"80",X"86",X"7F",X"7D",X"7D",X"88",X"7E",X"82",X"7C",X"7C",
-		X"85",X"83",X"79",X"81",X"86",X"7F",X"7A",X"82",X"86",X"79",X"80",X"85",X"81",X"7A",X"7F",X"86",
-		X"81",X"7B",X"7E",X"87",X"7F",X"80",X"80",X"7B",X"80",X"87",X"7E",X"7A",X"85",X"83",X"7F",X"7A",
-		X"84",X"84",X"7F",X"7C",X"7E",X"87",X"7E",X"82",X"7D",X"7B",X"85",X"81",X"7F",X"7A",X"85",X"82",
-		X"7F",X"7B",X"80",X"86",X"80",X"7B",X"80",X"86",X"7F",X"80",X"80",X"7A",X"81",X"85",X"7F",X"7A",
-		X"82",X"85",X"80",X"7B",X"81",X"86",X"7C",X"7C",X"86",X"81",X"81",X"7C",X"7E",X"86",X"7F",X"80",
-		X"79",X"84",X"84",X"7F",X"80",X"7F",X"7A",X"83",X"84",X"7F",X"81",X"7B",X"7E",X"83",X"85",X"7D",
-		X"7C",X"86",X"81",X"7A",X"81",X"85",X"7F",X"7B",X"84",X"82",X"7F",X"81",X"7A",X"80",X"85",X"81",
-		X"7F",X"81",X"7D",X"7C",X"84",X"84",X"7F",X"7A",X"82",X"85",X"7F",X"81",X"7F",X"7A",X"84",X"83",
-		X"7F",X"80",X"7A",X"81",X"85",X"80",X"80",X"7D",X"7C",X"86",X"81",X"80",X"80",X"7A",X"85",X"82",
-		X"7F",X"81",X"7B",X"7E",X"85",X"82",X"7F",X"81",X"7B",X"7F",X"84",X"83",X"7C",X"7D",X"85",X"82",
-		X"7C",X"7E",X"86",X"7D",X"7C",X"85",X"82",X"7F",X"81",X"7E",X"7B",X"84",X"83",X"81",X"7C",X"7D",
-		X"87",X"7C",X"7E",X"86",X"7F",X"7B",X"86",X"80",X"81",X"7C",X"7E",X"86",X"7F",X"7B",X"83",X"84",
-		X"7F",X"80",X"7A",X"81",X"85",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"7E",X"7C",X"87",X"7E",X"7C",
-		X"85",X"80",X"7B",X"84",X"82",X"79",X"82",X"84",X"81",X"7A",X"81",X"85",X"80",X"7F",X"7B",X"86",
-		X"81",X"7A",X"83",X"84",X"7F",X"81",X"7F",X"7B",X"82",X"85",X"7B",X"7D",X"85",X"81",X"7F",X"81",
-		X"7D",X"7C",X"85",X"82",X"80",X"7A",X"83",X"83",X"80",X"7D",X"7D",X"86",X"80",X"7F",X"7B",X"84",
-		X"83",X"7F",X"81",X"7E",X"7C",X"83",X"84",X"7B",X"81",X"85",X"7C",X"7E",X"86",X"7C",X"7D",X"84",
-		X"84",X"7C",X"7E",X"85",X"80",X"7C",X"7D",X"85",X"81",X"7F",X"81",X"7C",X"7F",X"86",X"7F",X"81",
-		X"7F",X"7B",X"84",X"83",X"7C",X"7F",X"86",X"7B",X"7E",X"84",X"82",X"7D",X"7D",X"85",X"80",X"7F",
-		X"7B",X"86",X"80",X"80",X"7F",X"7B",X"82",X"85",X"7B",X"80",X"84",X"80",X"7D",X"7D",X"85",X"82",
-		X"7D",X"7D",X"85",X"81",X"7D",X"7D",X"84",X"82",X"7D",X"7E",X"86",X"7D",X"7C",X"84",X"82",X"7B",
-		X"80",X"85",X"7F",X"80",X"80",X"7B",X"81",X"85",X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"7B",
-		X"81",X"84",X"7F",X"7B",X"83",X"83",X"7F",X"81",X"7B",X"80",X"83",X"83",X"7D",X"7C",X"85",X"81",
-		X"7F",X"81",X"7D",X"7D",X"83",X"83",X"80",X"7B",X"83",X"83",X"80",X"7B",X"81",X"84",X"80",X"7C",
-		X"80",X"85",X"7B",X"7E",X"84",X"82",X"7F",X"82",X"7C",X"7E",X"85",X"80",X"80",X"7B",X"83",X"84",
-		X"7A",X"83",X"82",X"80",X"7C",X"81",X"85",X"7B",X"7F",X"84",X"80",X"7F",X"81",X"7C",X"7F",X"85",
-		X"7E",X"7C",X"83",X"84",X"7F",X"81",X"7B",X"80",X"84",X"7F",X"81",X"7D",X"7C",X"83",X"83",X"80",
-		X"7B",X"80",X"84",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",X"7C",X"81",X"85",X"7B",X"7F",X"85",
-		X"7F",X"81",X"7D",X"7D",X"82",X"84",X"80",X"80",X"80",X"7B",X"82",X"83",X"7F",X"81",X"7D",X"7D",
-		X"85",X"80",X"80",X"80",X"7C",X"80",X"85",X"80",X"80",X"7F",X"7C",X"85",X"81",X"7B",X"82",X"83",
-		X"7A",X"82",X"83",X"7F",X"81",X"7B",X"80",X"85",X"7F",X"7C",X"84",X"82",X"7B",X"80",X"84",X"81",
-		X"7C",X"7F",X"85",X"7F",X"82",X"7D",X"7E",X"85",X"80",X"7B",X"82",X"83",X"7F",X"80",X"7B",X"85",
-		X"81",X"7B",X"81",X"84",X"80",X"7C",X"83",X"82",X"7B",X"80",X"84",X"80",X"81",X"7C",X"81",X"85",
-		X"7B",X"7F",X"85",X"7D",X"7D",X"84",X"81",X"80",X"81",X"7E",X"7C",X"83",X"83",X"7F",X"7C",X"81",
-		X"84",X"7F",X"81",X"7C",X"7F",X"85",X"7F",X"7C",X"82",X"83",X"7E",X"7C",X"82",X"84",X"7F",X"81",
-		X"7F",X"7C",X"81",X"84",X"80",X"80",X"81",X"7C",X"80",X"85",X"7F",X"7C",X"84",X"80",X"81",X"7C",
-		X"7F",X"84",X"81",X"7E",X"7D",X"84",X"82",X"7D",X"7D",X"84",X"81",X"7E",X"7C",X"84",X"81",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"7C",X"82",X"83",X"7F",X"7C",X"81",X"84",X"7F",X"81",X"7F",
-		X"7C",X"80",X"83",X"82",X"7D",X"7E",X"84",X"81",X"7F",X"81",X"7C",X"80",X"84",X"81",X"7D",X"7E",
-		X"84",X"80",X"7F",X"7C",X"83",X"83",X"7E",X"7D",X"84",X"81",X"7B",X"82",X"83",X"7F",X"7C",X"81",
-		X"83",X"80",X"7C",X"81",X"84",X"7F",X"80",X"80",X"7C",X"81",X"84",X"7D",X"7D",X"83",X"82",X"7F",
-		X"81",X"7D",X"7D",X"82",X"83",X"80",X"80",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"84",X"81",
-		X"7F",X"80",X"7B",X"82",X"83",X"80",X"7E",X"7D",X"85",X"80",X"80",X"7F",X"7C",X"83",X"82",X"7C",
-		X"81",X"84",X"7C",X"80",X"84",X"7D",X"7E",X"85",X"7F",X"7C",X"83",X"82",X"7F",X"81",X"7C",X"81",
-		X"84",X"80",X"80",X"80",X"7D",X"7F",X"83",X"82",X"7C",X"81",X"83",X"7F",X"81",X"7C",X"7F",X"83",
-		X"81",X"7F",X"81",X"7D",X"7E",X"85",X"80",X"80",X"7F",X"7C",X"82",X"83",X"7D",X"7E",X"83",X"82",
-		X"7E",X"7D",X"84",X"81",X"80",X"80",X"7C",X"81",X"84",X"80",X"81",X"7E",X"7D",X"84",X"82",X"7C",
-		X"82",X"83",X"7C",X"7F",X"84",X"80",X"80",X"81",X"7D",X"7E",X"83",X"82",X"80",X"80",X"7C",X"82",
-		X"83",X"7C",X"80",X"84",X"7D",X"7D",X"84",X"80",X"81",X"7C",X"82",X"83",X"7F",X"7E",X"7E",X"84",
-		X"80",X"80",X"80",X"7D",X"7E",X"85",X"80",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7F",X"7C",X"82",
-		X"83",X"7B",X"80",X"83",X"80",X"7D",X"7E",X"84",X"80",X"80",X"80",X"7D",X"7F",X"84",X"7F",X"7C",
-		X"84",X"81",X"80",X"7C",X"83",X"82",X"7C",X"82",X"82",X"7C",X"80",X"84",X"7D",X"7E",X"84",X"80",
-		X"80",X"80",X"7C",X"83",X"82",X"80",X"7E",X"7E",X"85",X"7E",X"7D",X"82",X"83",X"7E",X"7D",X"83",
-		X"80",X"7C",X"83",X"81",X"7C",X"83",X"81",X"80",X"80",X"7C",X"7F",X"82",X"82",X"7E",X"7D",X"83",
-		X"82",X"7E",X"7D",X"83",X"82",X"7E",X"7E",X"84",X"7F",X"7C",X"84",X"80",X"7C",X"83",X"81",X"7F",
-		X"80",X"7C",X"81",X"83",X"80",X"7F",X"7D",X"83",X"81",X"7C",X"81",X"83",X"7B",X"82",X"82",X"7F",
-		X"80",X"7C",X"82",X"82",X"80",X"7D",X"82",X"83",X"7B",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",
-		X"7D",X"80",X"84",X"7F",X"81",X"7F",X"7D",X"82",X"83",X"80",X"7C",X"81",X"83",X"7F",X"7D",X"81",
-		X"84",X"7D",X"7F",X"84",X"7F",X"7D",X"84",X"80",X"81",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7E",
-		X"82",X"83",X"7F",X"81",X"7D",X"7F",X"83",X"81",X"7D",X"7F",X"84",X"80",X"7C",X"83",X"81",X"7C",
-		X"82",X"82",X"7C",X"80",X"83",X"80",X"80",X"80",X"7D",X"7E",X"83",X"81",X"80",X"80",X"7F",X"7D",
-		X"82",X"83",X"80",X"80",X"80",X"7C",X"81",X"83",X"7F",X"81",X"7E",X"7D",X"82",X"82",X"80",X"7E",
-		X"7D",X"84",X"81",X"80",X"80",X"7D",X"80",X"84",X"7E",X"7E",X"83",X"81",X"7F",X"7D",X"82",X"82",
-		X"7E",X"7E",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"7D",X"82",X"83",X"7F",X"7D",X"83",X"81",X"7C",
-		X"82",X"81",X"7F",X"81",X"7D",X"80",X"83",X"7F",X"7D",X"83",X"81",X"7F",X"81",X"7C",X"81",X"83",
-		X"7F",X"80",X"7F",X"7D",X"82",X"82",X"80",X"7D",X"80",X"83",X"80",X"7D",X"82",X"82",X"7F",X"81",
-		X"7D",X"7F",X"82",X"82",X"7D",X"81",X"83",X"7F",X"81",X"7D",X"7E",X"84",X"7F",X"7D",X"83",X"80",
-		X"7D",X"83",X"81",X"80",X"7E",X"7E",X"84",X"7E",X"7E",X"82",X"81",X"7D",X"80",X"83",X"81",X"7E",
-		X"7E",X"83",X"81",X"7D",X"80",X"83",X"7E",X"7E",X"83",X"81",X"80",X"80",X"7C",X"82",X"82",X"7E",
-		X"7E",X"83",X"81",X"7E",X"7E",X"83",X"80",X"80",X"7F",X"7D",X"83",X"80",X"80",X"7D",X"83",X"81",
-		X"80",X"7D",X"80",X"83",X"7F",X"81",X"7E",X"7F",X"83",X"7F",X"7D",X"83",X"80",X"7C",X"83",X"81",
-		X"7D",X"82",X"82",X"7C",X"81",X"82",X"80",X"7E",X"7F",X"83",X"81",X"7E",X"7F",X"83",X"80",X"80",
-		X"81",X"7D",X"7F",X"83",X"81",X"7D",X"80",X"83",X"80",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"7F",
-		X"83",X"80",X"7D",X"83",X"80",X"7F",X"7D",X"83",X"81",X"80",X"80",X"7D",X"81",X"83",X"80",X"7D",
-		X"83",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",
-		X"80",X"81",X"7E",X"7E",X"82",X"82",X"7F",X"7D",X"82",X"82",X"7C",X"81",X"82",X"81",X"7D",X"81",
-		X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"81",X"7E",X"7E",
-		X"83",X"81",X"7F",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",X"82",X"7E",X"7E",X"83",
-		X"80",X"80",X"7E",X"7E",X"83",X"81",X"7F",X"7E",X"83",X"7F",X"7E",X"83",X"80",X"7D",X"81",X"83",
-		X"7F",X"80",X"80",X"7D",X"80",X"83",X"7D",X"7F",X"83",X"80",X"81",X"7E",X"7E",X"83",X"80",X"80",
-		X"80",X"7D",X"80",X"82",X"82",X"7D",X"80",X"82",X"80",X"7E",X"7E",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",X"7D",X"82",X"82",X"7F",X"81",X"7F",X"7E",X"82",X"81",
-		X"7D",X"81",X"82",X"7F",X"81",X"7D",X"80",X"82",X"81",X"7E",X"7F",X"83",X"81",X"7E",X"7E",X"83",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"7F",X"7D",X"81",X"83",X"7F",
-		X"7E",X"82",X"81",X"7D",X"81",X"82",X"7F",X"81",X"7D",X"81",X"82",X"7F",X"80",X"7E",X"7E",X"82",
-		X"82",X"80",X"80",X"7D",X"81",X"83",X"7E",X"7E",X"82",X"82",X"7E",X"7F",X"83",X"7F",X"7D",X"82",
-		X"82",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"80",X"82",X"80",X"7E",X"80",X"83",X"80",
-		X"7F",X"7E",X"83",X"81",X"80",X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"83",X"7F",
-		X"7E",X"83",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"80",X"7D",X"80",X"82",
-		X"80",X"7D",X"81",X"82",X"80",X"80",X"80",X"7D",X"80",X"82",X"80",X"7F",X"7E",X"83",X"7F",X"7E",
-		X"83",X"80",X"80",X"80",X"7D",X"81",X"82",X"81",X"7D",X"81",X"81",X"80",X"7E",X"7F",X"83",X"80",
-		X"7F",X"7E",X"83",X"80",X"80",X"80",X"7F",X"7E",X"82",X"82",X"80",X"80",X"80",X"7D",X"81",X"82",
-		X"7D",X"80",X"83",X"7F",X"7E",X"82",X"81",X"7D",X"80",X"82",X"80",X"7D",X"81",X"81",X"80",X"7D",
-		X"81",X"82",X"80",X"7E",X"7F",X"83",X"80",X"80",X"80",X"7E",X"7F",X"82",X"82",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"82",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",
-		X"81",X"7E",X"81",X"82",X"7F",X"81",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"80",X"82",X"81",
-		X"7E",X"80",X"82",X"7F",X"81",X"7E",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",X"80",X"82",X"80",
-		X"80",X"80",X"7D",X"82",X"81",X"80",X"80",X"7E",X"7F",X"82",X"81",X"80",X"80",X"7D",X"82",X"81",
-		X"7F",X"81",X"7E",X"7F",X"82",X"80",X"7D",X"81",X"82",X"80",X"7D",X"81",X"82",X"7F",X"80",X"7D",
-		X"81",X"82",X"7D",X"80",X"82",X"80",X"7E",X"81",X"82",X"7D",X"81",X"81",X"80",X"7D",X"81",X"82",
-		X"7F",X"80",X"7E",X"7F",X"82",X"81",X"7F",X"81",X"7D",X"81",X"82",X"7E",X"7F",X"82",X"81",X"7E",
-		X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",X"81",X"82",X"80",X"80",X"80",X"7E",
-		X"7F",X"82",X"81",X"7E",X"81",X"82",X"7E",X"7F",X"82",X"80",X"80",X"7E",X"81",X"82",X"7F",X"80",
-		X"7E",X"80",X"81",X"82",X"7F",X"7E",X"82",X"81",X"7F",X"81",X"7F",X"7E",X"82",X"81",X"7E",X"80",
-		X"82",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"83",X"7F",X"7E",X"82",X"81",X"80",X"80",X"7F",X"7E",
-		X"82",X"81",X"80",X"7E",X"7F",X"82",X"81",X"7E",X"7F",X"82",X"80",X"7F",X"7F",X"83",X"7E",X"7F",
-		X"82",X"80",X"7F",X"7E",X"82",X"81",X"7F",X"7E",X"82",X"81",X"80",X"7E",X"81",X"81",X"80",X"7E",
-		X"80",X"82",X"80",X"7F",X"7E",X"83",X"80",X"80",X"80",X"7E",X"81",X"82",X"80",X"7E",X"7F",X"82",
-		X"80",X"7E",X"80",X"82",X"7E",X"7F",X"82",X"81",X"7F",X"7F",X"83",X"7E",X"7F",X"82",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd
deleted file mode 100644
index 7d2fd29c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/GAL_HIT.vhd	
+++ /dev/null
@@ -1,534 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all,ieee.numeric_std.all;
-
-entity GAL_HIT is
-port (
-	clk  : in  std_logic;
-	addr : in  std_logic_vector(12 downto 0);
-	data : out std_logic_vector(7 downto 0)
-);
-end entity;
-
-architecture prom of GAL_HIT is
-	type rom is array(0 to  8191) of std_logic_vector(7 downto 0);
-	signal rom_data: rom := (
-		X"65",X"75",X"88",X"90",X"93",X"9B",X"A3",X"A3",X"A3",X"A6",X"9E",X"9B",X"9B",X"A3",X"AB",X"B6",
-		X"B9",X"B9",X"BE",X"B9",X"AE",X"A6",X"9E",X"98",X"88",X"78",X"68",X"65",X"65",X"65",X"62",X"68",
-		X"68",X"65",X"5D",X"52",X"47",X"47",X"4A",X"4D",X"4D",X"4D",X"52",X"65",X"7D",X"88",X"90",X"9B",
-		X"A3",X"AE",X"AE",X"AB",X"AB",X"9E",X"98",X"88",X"70",X"52",X"37",X"1F",X"17",X"1F",X"27",X"3A",
-		X"5A",X"68",X"78",X"83",X"93",X"A3",X"AB",X"AE",X"A3",X"93",X"88",X"88",X"83",X"88",X"8B",X"88",
-		X"78",X"62",X"4A",X"42",X"3A",X"42",X"4D",X"55",X"65",X"78",X"83",X"8B",X"93",X"90",X"88",X"88",
-		X"98",X"A6",X"A6",X"AB",X"9E",X"8B",X"7D",X"68",X"70",X"88",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"DC",X"9B",X"4D",X"14",X"01",X"04",X"2F",X"52",X"5D",X"68",X"78",X"80",X"78",X"70",
-		X"5D",X"47",X"32",X"1F",X"14",X"09",X"11",X"1C",X"32",X"52",X"83",X"B9",X"D1",X"C9",X"AB",X"8B",
-		X"70",X"68",X"75",X"78",X"80",X"8B",X"8B",X"98",X"AB",X"BE",X"C1",X"AB",X"83",X"5D",X"3A",X"17",
-		X"11",X"17",X"27",X"3A",X"65",X"90",X"AE",X"B6",X"9B",X"78",X"55",X"4A",X"4D",X"5A",X"5D",X"52",
-		X"4A",X"4A",X"52",X"78",X"AB",X"D4",X"FC",X"FC",X"F7",X"E9",X"E1",X"D1",X"C9",X"BE",X"AB",X"90",
-		X"52",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"2F",X"4A",X"52",X"47",X"47",X"62",X"70",X"7D",
-		X"7D",X"78",X"7D",X"90",X"B3",X"CE",X"EC",X"FC",X"FC",X"FC",X"FC",X"F4",X"E9",X"F4",X"FC",X"FC",
-		X"FC",X"FC",X"CE",X"98",X"65",X"2C",X"01",X"01",X"01",X"01",X"01",X"32",X"6D",X"7D",X"68",X"4A",
-		X"27",X"11",X"1C",X"3A",X"4D",X"62",X"68",X"65",X"68",X"70",X"80",X"9B",X"D1",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"A3",X"75",X"55",X"62",X"80",X"A3",X"BE",X"CE",X"C1",X"90",X"4A",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"88",X"C9",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",
-		X"B6",X"90",X"68",X"3F",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1F",X"83",X"BE",X"D1",X"CE",
-		X"D4",X"F4",X"FC",X"FC",X"FC",X"F7",X"D1",X"CE",X"DC",X"F7",X"FC",X"FC",X"FC",X"FC",X"D1",X"8B",
-		X"68",X"68",X"88",X"A6",X"C1",X"D9",X"D4",X"BE",X"A3",X"88",X"75",X"68",X"62",X"5D",X"62",X"68",
-		X"6D",X"78",X"75",X"55",X"2C",X"11",X"11",X"2F",X"55",X"75",X"83",X"93",X"9E",X"B9",X"E9",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"BE",X"68",X"32",X"11",X"17",X"32",X"52",X"7D",
-		X"AE",X"E1",X"F7",X"E1",X"A3",X"62",X"17",X"01",X"01",X"01",X"01",X"01",X"1C",X"4D",X"7D",X"90",
-		X"9B",X"A6",X"B6",X"BE",X"A6",X"70",X"37",X"14",X"14",X"1C",X"14",X"1C",X"2F",X"3A",X"3A",X"3A",
-		X"4A",X"52",X"4A",X"47",X"3A",X"24",X"11",X"14",X"27",X"3A",X"65",X"9E",X"D4",X"FC",X"FC",X"F7",
-		X"D4",X"AB",X"93",X"93",X"93",X"83",X"68",X"4D",X"37",X"37",X"5D",X"9B",X"EC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"CE",X"AB",X"93",X"7D",X"65",X"65",X"75",X"88",X"93",X"98",X"98",X"93",
-		X"93",X"90",X"93",X"8B",X"90",X"90",X"90",X"8B",X"8B",X"90",X"8B",X"90",X"90",X"90",X"90",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"88",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"78",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"75",X"78",X"75",X"70",X"75",X"75",X"75",X"75",X"70",X"6D",X"68",X"6D",X"70",X"6D",
-		X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"6D",X"70",X"70",X"70",X"75",X"75",X"75",X"75",
-		X"75",X"70",X"62",X"4D",X"4D",X"4D",X"47",X"4A",X"68",X"98",X"B6",X"B3",X"9B",X"78",X"5A",X"3F",
-		X"32",X"2F",X"32",X"3F",X"5A",X"90",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"E9",X"90",X"4D",X"3A",
-		X"47",X"5D",X"5D",X"4D",X"3A",X"27",X"1C",X"14",X"11",X"0C",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"4A",X"9E",X"F7",X"FC",X"FC",X"FC",X"FC",X"EC",X"E4",X"E4",X"D1",X"AB",X"80",X"62",X"47",
-		X"37",X"2F",X"2C",X"24",X"04",X"01",X"24",X"52",X"70",X"70",X"62",X"4D",X"3F",X"37",X"37",X"3A",
-		X"4D",X"62",X"78",X"93",X"AE",X"D1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"B6",X"68",
-		X"2C",X"01",X"01",X"01",X"01",X"01",X"01",X"09",X"47",X"65",X"68",X"68",X"62",X"5A",X"52",X"4D",
-		X"52",X"4D",X"52",X"52",X"5A",X"5D",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"65",X"37",X"1C",
-		X"09",X"09",X"1C",X"32",X"4D",X"70",X"93",X"AB",X"C9",X"D9",X"E9",X"EF",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"F7",X"6D",X"0C",X"01",X"01",X"01",X"01",X"01",X"17",X"62",X"83",X"78",
-		X"5A",X"37",X"14",X"04",X"01",X"01",X"01",X"01",X"04",X"11",X"1C",X"1C",X"01",X"01",X"0C",X"3F",
-		X"6D",X"7D",X"78",X"68",X"65",X"83",X"B3",X"E1",X"F4",X"E4",X"C6",X"A3",X"8B",X"75",X"68",X"65",
-		X"5D",X"62",X"65",X"62",X"5A",X"3F",X"27",X"17",X"1F",X"5A",X"9E",X"CE",X"D4",X"C9",X"AE",X"A6",
-		X"AE",X"AB",X"9B",X"83",X"80",X"98",X"9B",X"9B",X"9B",X"B6",X"D9",X"E4",X"E1",X"DC",X"E1",X"D4",
-		X"B3",X"83",X"5A",X"3A",X"1F",X"11",X"0C",X"11",X"14",X"1C",X"1F",X"2C",X"2C",X"1F",X"27",X"32",
-		X"3F",X"5D",X"83",X"9B",X"93",X"93",X"88",X"7D",X"7D",X"75",X"70",X"70",X"6D",X"68",X"68",X"68",
-		X"5A",X"5A",X"75",X"88",X"93",X"93",X"90",X"90",X"88",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"80",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",X"83",X"83",X"80",X"80",
-		X"80",X"7D",X"7D",X"70",X"70",X"6D",X"75",X"83",X"90",X"93",X"90",X"88",X"88",X"80",X"78",X"7D",
-		X"70",X"68",X"70",X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"75",X"70",X"68",X"4D",X"3A",
-		X"4A",X"70",X"93",X"A3",X"B6",X"B9",X"B3",X"A3",X"90",X"80",X"75",X"70",X"68",X"68",X"68",X"65",
-		X"68",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"75",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"70",X"55",X"37",X"1F",X"24",X"47",X"68",X"7D",X"88",X"8B",
-		X"88",X"88",X"88",X"8B",X"AB",X"CE",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"C9",X"AB",X"80",X"5A",
-		X"4A",X"47",X"37",X"2C",X"32",X"4D",X"70",X"78",X"7D",X"8B",X"90",X"88",X"68",X"4A",X"2C",X"1C",
-		X"11",X"09",X"01",X"01",X"01",X"01",X"14",X"27",X"47",X"70",X"AE",X"E1",X"F4",X"E4",X"D1",X"AE",
-		X"93",X"80",X"70",X"68",X"62",X"62",X"65",X"68",X"6D",X"75",X"78",X"78",X"65",X"4A",X"4D",X"5A",
-		X"62",X"65",X"68",X"88",X"B9",X"EC",X"FC",X"F4",X"D1",X"B6",X"B3",X"AE",X"A3",X"98",X"A3",X"C6",
-		X"D9",X"D4",X"D4",X"E1",X"E1",X"C9",X"9E",X"78",X"62",X"3F",X"32",X"2C",X"27",X"2C",X"32",X"37",
-		X"3F",X"47",X"4A",X"52",X"55",X"5A",X"5D",X"5D",X"5A",X"3F",X"27",X"14",X"11",X"14",X"24",X"4A",
-		X"80",X"A6",X"BE",X"C6",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"DC",X"BE",X"AB",X"8B",
-		X"5D",X"2F",X"14",X"01",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"70",X"6D",X"5D",X"4D",
-		X"4D",X"68",X"9B",X"BE",X"C9",X"B9",X"B3",X"AB",X"9B",X"A3",X"B3",X"C6",X"D1",X"B6",X"8B",X"52",
-		X"1C",X"11",X"11",X"14",X"37",X"62",X"90",X"9E",X"9B",X"83",X"75",X"5D",X"47",X"32",X"2F",X"24",
-		X"17",X"11",X"11",X"17",X"27",X"5D",X"A3",X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"EF",X"CE",
-		X"9B",X"7D",X"68",X"62",X"62",X"7D",X"98",X"9E",X"93",X"7D",X"6D",X"5D",X"55",X"52",X"52",X"52",
-		X"55",X"55",X"5D",X"62",X"65",X"68",X"6D",X"70",X"75",X"7D",X"78",X"7D",X"80",X"83",X"78",X"62",
-		X"3A",X"27",X"14",X"17",X"27",X"3F",X"5A",X"78",X"98",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",
-		X"04",X"01",X"01",X"01",X"01",X"01",X"11",X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",
-		X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",
-		X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",
-		X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",
-		X"88",X"75",X"52",X"37",X"1F",X"1C",X"27",X"37",X"4D",X"68",X"83",X"AE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D1",X"9B",X"65",X"42",X"3A",X"52",X"80",X"AE",X"D4",X"E9",X"E4",X"C6",
-		X"80",X"3A",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"32",X"88",X"C6",X"F7",X"FC",
-		X"E4",X"CE",X"B9",X"A3",X"80",X"62",X"47",X"37",X"2F",X"2C",X"2F",X"37",X"3F",X"3A",X"32",X"3A",
-		X"37",X"32",X"37",X"3A",X"52",X"7D",X"B3",X"DC",X"E4",X"E1",X"D1",X"D1",X"E1",X"FC",X"FC",X"FC",
-		X"FC",X"F4",X"CE",X"A3",X"83",X"75",X"7D",X"83",X"83",X"88",X"98",X"A6",X"A6",X"98",X"88",X"75",
-		X"68",X"5D",X"5A",X"5A",X"5A",X"62",X"65",X"68",X"6D",X"70",X"75",X"75",X"75",X"7D",X"83",X"83",
-		X"80",X"75",X"68",X"70",X"80",X"8B",X"93",X"98",X"98",X"90",X"90",X"8B",X"90",X"98",X"A3",X"AE",
-		X"B6",X"C9",X"C9",X"C1",X"B3",X"A3",X"98",X"8B",X"78",X"75",X"70",X"6D",X"65",X"68",X"70",X"80",
-		X"83",X"83",X"88",X"8B",X"83",X"78",X"68",X"5D",X"52",X"42",X"2C",X"27",X"2C",X"3A",X"47",X"42",
-		X"42",X"52",X"70",X"8B",X"A6",X"AB",X"A3",X"9E",X"9E",X"B3",X"B9",X"B9",X"BE",X"BE",X"B9",X"A3",
-		X"88",X"68",X"5D",X"5A",X"5A",X"52",X"52",X"68",X"70",X"65",X"62",X"62",X"68",X"7D",X"8B",X"8B",
-		X"83",X"75",X"65",X"68",X"75",X"80",X"9B",X"C1",X"EC",X"FC",X"FC",X"F7",X"EF",X"E9",X"D1",X"A3",
-		X"78",X"5D",X"42",X"2C",X"14",X"0C",X"09",X"0C",X"0C",X"17",X"2C",X"47",X"62",X"75",X"75",X"68",
-		X"62",X"52",X"4A",X"4A",X"42",X"3F",X"4A",X"55",X"68",X"90",X"A3",X"B9",X"C6",X"CE",X"E4",X"FC",
-		X"FC",X"EC",X"E9",X"E9",X"DC",X"C1",X"B3",X"A6",X"98",X"75",X"52",X"3A",X"2C",X"1C",X"11",X"01",
-		X"0C",X"1F",X"37",X"52",X"70",X"78",X"78",X"68",X"62",X"62",X"75",X"98",X"B6",X"BE",X"B3",X"AB",
-		X"A6",X"9B",X"9E",X"AE",X"B9",X"C1",X"AE",X"90",X"5D",X"32",X"2C",X"27",X"2C",X"3F",X"62",X"83",
-		X"93",X"90",X"88",X"80",X"70",X"5D",X"52",X"47",X"3A",X"2F",X"24",X"1F",X"2C",X"3A",X"68",X"A3",
-		X"D4",X"F4",X"FC",X"FC",X"F4",X"E9",X"E9",X"DC",X"B9",X"90",X"78",X"68",X"5D",X"62",X"7D",X"93",
-		X"9B",X"90",X"7D",X"70",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5A",X"5D",X"65",X"68",X"68",X"70",
-		X"70",X"75",X"78",X"78",X"7D",X"80",X"80",X"78",X"65",X"3F",X"27",X"17",X"1C",X"2C",X"3F",X"5D",
-		X"78",X"93",X"AE",X"C6",X"DC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"F7",X"A6",X"80",X"70",
-		X"62",X"65",X"7D",X"98",X"A6",X"9B",X"80",X"62",X"32",X"04",X"01",X"01",X"01",X"01",X"01",X"11",
-		X"3A",X"5D",X"83",X"98",X"93",X"88",X"83",X"88",X"78",X"5D",X"4A",X"37",X"2C",X"24",X"27",X"24",
-		X"17",X"14",X"32",X"5D",X"80",X"90",X"90",X"93",X"93",X"93",X"90",X"8B",X"8B",X"8B",X"8B",X"90",
-		X"93",X"93",X"98",X"98",X"9B",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9E",X"9B",X"9E",
-		X"9B",X"98",X"98",X"98",X"93",X"93",X"90",X"93",X"8B",X"88",X"75",X"52",X"37",X"1F",X"1C",X"24",
-		X"37",X"4D",X"68",X"88",X"AE",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"9B",X"65",
-		X"3F",X"37",X"52",X"80",X"B3",X"D9",X"EC",X"EC",X"C9",X"7D",X"37",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"27",X"88",X"D1",X"FC",X"FC",X"EC",X"D1",X"BE",X"A3",X"7D",X"62",X"3A",
-		X"2C",X"1F",X"1F",X"24",X"2C",X"32",X"2C",X"27",X"2F",X"27",X"27",X"27",X"2C",X"47",X"7D",X"C1",
-		X"F7",X"FC",X"FC",X"E9",X"E1",X"EC",X"FC",X"FC",X"FC",X"FC",X"FC",X"E4",X"AE",X"88",X"78",X"83",
-		X"8B",X"8B",X"93",X"A3",X"B9",X"BE",X"A6",X"90",X"75",X"65",X"52",X"52",X"52",X"4D",X"55",X"5D",
-		X"62",X"68",X"70",X"70",X"70",X"75",X"80",X"8B",X"90",X"90",X"8B",X"83",X"90",X"98",X"9B",X"9E",
-		X"9E",X"9B",X"93",X"93",X"8B",X"90",X"8B",X"8B",X"8B",X"88",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",
-		X"8B",X"8B",X"8B",X"8B",X"8B",X"88",X"8B",X"88",X"88",X"88",X"88",X"83",X"83",X"80",X"80",X"80",
-		X"80",X"7D",X"65",X"47",X"52",X"68",X"78",X"78",X"65",X"5A",X"5D",X"6D",X"75",X"78",X"70",X"68",
-		X"70",X"90",X"C9",X"EC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A6",X"68",X"42",X"3A",X"37",X"3A",X"5D",
-		X"7D",X"83",X"68",X"55",X"52",X"47",X"32",X"17",X"09",X"01",X"01",X"09",X"17",X"2C",X"52",X"9B",
-		X"E1",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"DC",X"A6",X"78",X"62",X"47",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"3F",X"7D",X"A3",X"9B",X"80",X"5D",X"4A",X"5A",X"7D",X"90",X"9B",X"AB",
-		X"A6",X"AB",X"AB",X"9E",X"A6",X"BE",X"D4",X"E4",X"D4",X"A6",X"88",X"7D",X"88",X"88",X"83",X"90",
-		X"A3",X"AB",X"A6",X"9E",X"98",X"8B",X"83",X"80",X"80",X"80",X"83",X"83",X"88",X"8B",X"8B",X"90",
-		X"90",X"90",X"93",X"98",X"98",X"9B",X"93",X"98",X"93",X"93",X"93",X"93",X"93",X"93",X"90",X"90",
-		X"90",X"8B",X"8B",X"83",X"80",X"7D",X"68",X"52",X"52",X"62",X"68",X"88",X"AB",X"C6",X"C9",X"C9",
-		X"B6",X"A6",X"9E",X"8B",X"83",X"8B",X"A3",X"B3",X"AE",X"98",X"80",X"6D",X"5D",X"52",X"47",X"42",
-		X"47",X"3F",X"47",X"42",X"42",X"4D",X"62",X"65",X"68",X"68",X"68",X"68",X"68",X"68",X"68",X"68",
-		X"65",X"68",X"68",X"68",X"6D",X"70",X"6D",X"6D",X"70",X"75",X"70",X"75",X"78",X"75",X"78",X"75",
-		X"78",X"78",X"78",X"78",X"78",X"78",X"78",X"7D",X"80",X"80",X"6D",X"65",X"70",X"80",X"80",X"68",
-		X"52",X"32",X"2C",X"37",X"68",X"9B",X"B6",X"B6",X"B6",X"C1",X"D4",X"D9",X"C6",X"A3",X"78",X"5A",
-		X"3F",X"32",X"32",X"3A",X"55",X"8B",X"CE",X"FC",X"FC",X"FC",X"FC",X"FC",X"E1",X"A3",X"62",X"2F",
-		X"1C",X"09",X"01",X"01",X"1C",X"47",X"5D",X"68",X"80",X"93",X"90",X"80",X"70",X"5A",X"4D",X"52",
-		X"68",X"78",X"7D",X"70",X"5D",X"4A",X"3A",X"32",X"32",X"2F",X"27",X"27",X"1C",X"11",X"09",X"0C",
-		X"14",X"2C",X"42",X"75",X"AB",X"DC",X"F7",X"FC",X"FC",X"F7",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"BE",X"88",X"4D",X"11",X"01",X"01",X"0C",X"3F",X"75",X"9E",X"B6",X"B3",
-		X"93",X"70",X"52",X"3A",X"1F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"3F",
-		X"52",X"62",X"68",X"7D",X"9E",X"C1",X"E4",X"FC",X"FC",X"F7",X"E1",X"BE",X"A3",X"90",X"80",X"88",
-		X"AB",X"E1",X"FC",X"FC",X"FC",X"FC",X"F7",X"BE",X"7D",X"3F",X"0C",X"01",X"01",X"01",X"01",X"27",
-		X"70",X"B6",X"E9",X"FC",X"FC",X"E9",X"AE",X"83",X"62",X"4D",X"2F",X"04",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"3F",X"98",X"CE",X"D1",X"BE",X"B6",X"C1",X"D4",X"E9",X"FC",X"E9",X"C9",X"AB",
-		X"9B",X"88",X"5D",X"37",X"27",X"27",X"1F",X"1C",X"1C",X"1F",X"37",X"70",X"B6",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"F4",X"F4",X"E4",X"C6",X"98",X"70",X"5A",X"3A",X"37",X"47",X"6D",X"AE",X"F7",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"93",X"55",X"17",X"01",X"01",X"01",X"1C",X"4A",X"80",X"AB",
-		X"B3",X"A6",X"A3",X"A3",X"A3",X"A6",X"9B",X"78",X"42",X"11",X"04",X"11",X"1C",X"1F",X"37",X"55",
-		X"7D",X"8B",X"80",X"5D",X"47",X"4D",X"65",X"6D",X"5D",X"4A",X"3F",X"4D",X"7D",X"B6",X"EC",X"FC",
-		X"FC",X"FC",X"E4",X"C6",X"9E",X"98",X"9B",X"90",X"75",X"5D",X"62",X"7D",X"9B",X"C6",X"E1",X"E9",
-		X"D9",X"B3",X"93",X"83",X"70",X"68",X"5D",X"5A",X"52",X"52",X"52",X"55",X"5D",X"65",X"65",X"68",
-		X"5A",X"37",X"2F",X"4A",X"65",X"6D",X"68",X"75",X"93",X"BE",X"E4",X"EC",X"D1",X"B3",X"9E",X"AB",
-		X"AB",X"9E",X"80",X"65",X"42",X"32",X"32",X"4A",X"75",X"90",X"A3",X"BE",X"E4",X"FC",X"FC",X"FC",
-		X"FC",X"D1",X"93",X"5A",X"3A",X"3A",X"47",X"5A",X"7D",X"A6",X"CE",X"CE",X"B9",X"A6",X"9B",X"80",
-		X"52",X"1C",X"01",X"01",X"01",X"11",X"47",X"78",X"9E",X"AB",X"9B",X"78",X"5A",X"2C",X"14",X"1C",
-		X"27",X"1F",X"11",X"01",X"01",X"01",X"1C",X"3F",X"75",X"AB",X"C9",X"D4",X"DC",X"CE",X"C9",X"D1",
-		X"E1",X"F4",X"FC",X"FC",X"FC",X"E4",X"BE",X"90",X"70",X"4A",X"11",X"01",X"01",X"01",X"01",X"09",
-		X"17",X"4A",X"90",X"D4",X"FC",X"FC",X"FC",X"F4",X"E9",X"E9",X"FC",X"FC",X"E4",X"B3",X"80",X"52",
-		X"2F",X"1C",X"1F",X"32",X"68",X"AE",X"F4",X"FC",X"FC",X"FC",X"E4",X"C9",X"AB",X"80",X"5D",X"47",
-		X"37",X"42",X"75",X"AB",X"DC",X"FC",X"FC",X"FC",X"D9",X"93",X"55",X"37",X"2F",X"3A",X"52",X"62",
-		X"68",X"68",X"55",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"1C",X"32",X"4D",X"68",
-		X"9B",X"CE",X"E4",X"F4",X"EC",X"E4",X"E4",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",
-		X"88",X"4A",X"17",X"04",X"11",X"42",X"75",X"88",X"9B",X"B6",X"BE",X"A6",X"7D",X"4D",X"1C",X"01",
-		X"01",X"17",X"27",X"32",X"4D",X"7D",X"A6",X"B3",X"B9",X"C6",X"D1",X"D9",X"D9",X"CE",X"BE",X"A6",
-		X"90",X"65",X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"14",X"68",X"93",X"98",X"83",X"75",X"7D",
-		X"9E",X"BE",X"C9",X"BE",X"A6",X"9E",X"B6",X"D9",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D9",X"C1",
-		X"B3",X"9B",X"75",X"5D",X"47",X"2F",X"2F",X"4A",X"68",X"7D",X"7D",X"78",X"83",X"90",X"9E",X"AE",
-		X"A3",X"83",X"75",X"52",X"3F",X"4A",X"5D",X"62",X"55",X"3F",X"2F",X"24",X"32",X"5A",X"7D",X"90",
-		X"AB",X"CE",X"E4",X"FC",X"FC",X"FC",X"E9",X"CE",X"B3",X"98",X"88",X"83",X"83",X"90",X"B3",X"EC",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"75",X"42",X"27",X"14",X"01",X"01",X"1C",X"3F",X"52",X"5A",
-		X"68",X"78",X"68",X"47",X"17",X"01",X"01",X"09",X"27",X"37",X"4A",X"65",X"75",X"6D",X"65",X"68",
-		X"68",X"5D",X"4D",X"42",X"27",X"0C",X"0C",X"14",X"1C",X"1F",X"3A",X"68",X"9E",X"CE",X"E1",X"DC",
-		X"DC",X"DC",X"DC",X"CE",X"A6",X"75",X"5A",X"4A",X"3A",X"4A",X"70",X"98",X"BE",X"E1",X"E9",X"E4",
-		X"B9",X"9E",X"90",X"8B",X"88",X"75",X"52",X"2F",X"2F",X"4A",X"5D",X"68",X"78",X"80",X"70",X"70",
-		X"7D",X"8B",X"9E",X"B6",X"BE",X"B6",X"AE",X"9B",X"98",X"AE",X"CE",X"E4",X"FC",X"FC",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"B9",X"9E",X"88",X"65",X"4D",X"47",X"3F",X"2F",X"11",X"01",X"04",
-		X"1F",X"2F",X"2F",X"1F",X"11",X"01",X"0C",X"2C",X"4D",X"62",X"78",X"98",X"AB",X"BE",X"DC",X"F4",
-		X"F7",X"E4",X"E1",X"DC",X"C1",X"9E",X"88",X"62",X"3A",X"14",X"01",X"11",X"17",X"27",X"32",X"55",
-		X"88",X"B6",X"E4",X"F7",X"E4",X"C6",X"A3",X"75",X"5A",X"52",X"5A",X"68",X"78",X"80",X"80",X"5A",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"3F",X"70",X"A3",X"C9",X"E1",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"DC",X"C6",X"B3",X"98",X"93",X"9B",X"AB",X"B9",X"AB",X"98",X"83",X"68",X"52",
-		X"4A",X"2F",X"17",X"04",X"01",X"0C",X"37",X"75",X"A3",X"B9",X"D1",X"CE",X"B3",X"A3",X"9B",X"93",
-		X"93",X"A6",X"BE",X"B9",X"9E",X"7D",X"55",X"37",X"27",X"27",X"4A",X"80",X"A6",X"B3",X"AE",X"AB",
-		X"B9",X"C6",X"B9",X"B3",X"A3",X"80",X"5D",X"4A",X"47",X"3A",X"32",X"3A",X"5A",X"7D",X"83",X"90",
-		X"8B",X"83",X"7D",X"70",X"65",X"6D",X"7D",X"78",X"65",X"47",X"1F",X"0C",X"01",X"01",X"09",X"2C",
-		X"68",X"AE",X"CE",X"D1",X"CE",X"D4",X"E4",X"E4",X"CE",X"A6",X"98",X"9B",X"AB",X"BE",X"CE",X"CE",
-		X"B9",X"90",X"52",X"14",X"01",X"01",X"01",X"01",X"09",X"3A",X"78",X"9E",X"AE",X"B9",X"CE",X"CE",
-		X"B9",X"A6",X"90",X"7D",X"7D",X"83",X"80",X"68",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",
-		X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",
-		X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",
-		X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",
-		X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",
-		X"01",X"01",X"01",X"01",X"01",X"24",X"47",X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",
-		X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",X"9B",X"98",X"98",X"90",X"83",X"88",X"A6",X"C9",X"DC",
-		X"D9",X"BE",X"AB",X"7D",X"52",X"2F",X"27",X"1F",X"11",X"17",X"27",X"2F",X"2F",X"3F",X"52",X"5D",
-		X"5A",X"65",X"70",X"75",X"80",X"88",X"8B",X"9B",X"AB",X"BE",X"C6",X"AE",X"83",X"55",X"27",X"09",
-		X"09",X"27",X"52",X"83",X"93",X"98",X"93",X"88",X"83",X"80",X"70",X"55",X"3F",X"2C",X"27",X"32",
-		X"47",X"65",X"8B",X"AE",X"D4",X"E9",X"D9",X"B3",X"98",X"90",X"93",X"88",X"68",X"4D",X"4A",X"5A",
-		X"68",X"6D",X"7D",X"8B",X"90",X"8B",X"88",X"8B",X"98",X"9E",X"9B",X"83",X"62",X"2F",X"09",X"04",
-		X"1F",X"47",X"6D",X"98",X"AE",X"B6",X"B3",X"AB",X"9B",X"9B",X"A3",X"B6",X"C6",X"B9",X"9B",X"83",
-		X"78",X"6D",X"65",X"5A",X"5A",X"68",X"88",X"A6",X"B6",X"A3",X"8B",X"75",X"68",X"6D",X"6D",X"65",
-		X"5D",X"5D",X"68",X"80",X"A3",X"CE",X"DC",X"D4",X"CE",X"CE",X"C9",X"C6",X"CE",X"BE",X"AB",X"90",
-		X"80",X"80",X"8B",X"98",X"9E",X"B6",X"DC",X"E4",X"E4",X"E1",X"CE",X"C6",X"B6",X"98",X"80",X"7D",
-		X"75",X"70",X"68",X"68",X"62",X"3F",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"11",X"47",X"68",X"90",X"B6",X"CE",X"D4",X"E1",X"E9",X"E9",X"E4",X"E4",X"E9",X"E4",X"D4",X"C6",
-		X"A6",X"78",X"42",X"14",X"01",X"01",X"01",X"01",X"14",X"42",X"78",X"AB",X"D1",X"E1",X"D9",X"C6",
-		X"9B",X"7D",X"75",X"78",X"88",X"93",X"8B",X"88",X"70",X"4D",X"2F",X"24",X"1C",X"24",X"27",X"24",
-		X"27",X"3A",X"62",X"88",X"B3",X"CE",X"DC",X"EC",X"EF",X"E1",X"CE",X"BE",X"A3",X"83",X"68",X"52",
-		X"4D",X"55",X"65",X"78",X"78",X"80",X"90",X"90",X"90",X"8B",X"75",X"5D",X"4D",X"52",X"62",X"80",
-		X"A3",X"B6",X"B6",X"B6",X"A6",X"90",X"83",X"88",X"93",X"9E",X"BE",X"D1",X"C9",X"AE",X"8B",X"62",
-		X"3F",X"27",X"1C",X"32",X"62",X"88",X"9B",X"A3",X"AB",X"C1",X"CE",X"C1",X"B6",X"A6",X"90",X"6D",
-		X"5D",X"55",X"3F",X"2F",X"2F",X"47",X"5D",X"65",X"6D",X"75",X"78",X"83",X"7D",X"75",X"7D",X"83",
-		X"80",X"68",X"4D",X"2F",X"14",X"04",X"04",X"17",X"37",X"70",X"A6",X"C1",X"C1",X"B9",X"BE",X"D1",
-		X"D4",X"C1",X"A3",X"98",X"9E",X"AE",X"C9",X"D4",X"D4",X"C6",X"98",X"5D",X"24",X"01",X"01",X"01",
-		X"01",X"17",X"4A",X"7D",X"A3",X"AE",X"B9",X"C9",X"C6",X"B6",X"A3",X"8B",X"7D",X"80",X"83",X"83",
-		X"6D",X"55",X"52",X"4A",X"42",X"37",X"32",X"47",X"75",X"A6",X"C1",X"D1",X"D9",X"CE",X"C9",X"B6",
-		X"9B",X"7D",X"62",X"4D",X"4D",X"6D",X"9E",X"D4",X"F4",X"EC",X"E4",X"CE",X"A3",X"78",X"65",X"5A",
-		X"4A",X"37",X"2C",X"37",X"5D",X"93",X"C6",X"E9",X"FC",X"FC",X"D4",X"A6",X"88",X"75",X"68",X"52",
-		X"27",X"01",X"01",X"01",X"01",X"01",X"11",X"5D",X"9B",X"C9",X"D1",X"C9",X"BE",X"B9",X"B9",X"B9",
-		X"B6",X"AE",X"A3",X"98",X"83",X"70",X"4D",X"17",X"01",X"01",X"01",X"01",X"01",X"01",X"24",X"47",
-		X"68",X"9B",X"DC",X"FC",X"FC",X"FC",X"FC",X"E9",X"F4",X"FC",X"FC",X"FC",X"E4",X"D4",X"C9",X"B3",
-		X"9B",X"98",X"98",X"8B",X"83",X"8B",X"A6",X"C9",X"E1",X"DC",X"C1",X"A6",X"7D",X"4D",X"2C",X"24",
-		X"17",X"0C",X"11",X"1F",X"2C",X"2C",X"3A",X"52",X"5D",X"5A",X"65",X"70",X"78",X"88",X"90",X"90",
-		X"9E",X"AB",X"C1",X"C6",X"A6",X"78",X"3F",X"11",X"01",X"01",X"14",X"47",X"80",X"93",X"98",X"93",
-		X"83",X"70",X"65",X"4D",X"2F",X"14",X"04",X"04",X"27",X"47",X"70",X"A3",X"D1",X"FC",X"FC",X"F7",
-		X"C9",X"A6",X"9B",X"9B",X"8B",X"70",X"5A",X"5D",X"75",X"7D",X"80",X"8B",X"9E",X"9B",X"93",X"8B",
-		X"98",X"A3",X"AE",X"AE",X"93",X"68",X"32",X"04",X"04",X"24",X"52",X"88",X"B6",X"C9",X"B9",X"AB",
-		X"98",X"80",X"80",X"90",X"A6",X"B9",X"BE",X"A6",X"93",X"8B",X"80",X"70",X"4D",X"37",X"3F",X"62",
-		X"88",X"9E",X"98",X"80",X"65",X"55",X"62",X"68",X"68",X"70",X"75",X"78",X"93",X"C6",X"FC",X"FC",
-		X"FC",X"FC",X"F7",X"E9",X"DC",X"D4",X"BE",X"A3",X"80",X"68",X"70",X"75",X"75",X"70",X"80",X"A3",
-		X"B3",X"B3",X"AE",X"98",X"83",X"75",X"5D",X"52",X"5A",X"68",X"78",X"83",X"83",X"78",X"4A",X"11",
-		X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"37",X"78",X"A6",X"D1",X"E9",X"E4",
-		X"E1",X"E1",X"DC",X"D9",X"E9",X"FC",X"FC",X"FC",X"FC",X"EF",X"B9",X"75",X"2F",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"27",X"5D",X"9B",X"D4",X"F4",X"EC",X"CE",X"A6",X"93",X"9E",X"B6",X"B6",X"A3",
-		X"93",X"8B",X"83",X"70",X"68",X"78",X"93",X"A6",X"9E",X"90",X"83",X"98",X"AE",X"C9",X"D4",X"DC",
-		X"CE",X"A6",X"7D",X"65",X"52",X"2C",X"04",X"01",X"01",X"01",X"01",X"01",X"01",X"11",X"4D",X"9E",
-		X"E4",X"FC",X"FC",X"FC",X"EC",X"EC",X"FC",X"FC",X"FC",X"FC",X"E9",X"AE",X"78",X"4A",X"2F",X"2F",
-		X"52",X"8B",X"C6",X"F4",X"FC",X"F7",X"DC",X"B3",X"80",X"4D",X"17",X"01",X"01",X"01",X"1C",X"3F",
-		X"70",X"A6",X"D1",X"E9",X"E1",X"CE",X"B9",X"B3",X"AE",X"A6",X"88",X"5A",X"1F",X"01",X"01",X"01",
-		X"01",X"01",X"14",X"52",X"8B",X"B9",X"C6",X"B6",X"A6",X"9E",X"90",X"75",X"68",X"52",X"4A",X"52",
-		X"68",X"88",X"93",X"83",X"62",X"3F",X"1F",X"17",X"2F",X"4D",X"68",X"75",X"83",X"9E",X"D1",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"D4",X"BE",X"B3",X"A3",X"A6",X"BE",X"D4",X"E1",X"CE",X"B3",X"A6",X"98",
-		X"75",X"4A",X"27",X"1C",X"2F",X"4D",X"68",X"7D",X"68",X"47",X"17",X"01",X"01",X"01",X"01",X"01",
-		X"04",X"0C",X"1F",X"32",X"4A",X"5D",X"80",X"B3",X"F7",X"FC",X"FC",X"FC",X"EC",X"D4",X"CE",X"BE",
-		X"C1",X"CE",X"D9",X"C9",X"A3",X"83",X"70",X"5A",X"3F",X"32",X"3F",X"5D",X"68",X"65",X"47",X"2C",
-		X"17",X"04",X"09",X"27",X"4A",X"68",X"90",X"9E",X"98",X"88",X"7D",X"83",X"9E",X"CE",X"E9",X"F7",
-		X"E4",X"BE",X"9E",X"68",X"37",X"09",X"01",X"01",X"01",X"04",X"14",X"37",X"55",X"65",X"70",X"88",
-		X"AE",X"DC",X"FC",X"F4",X"D1",X"AE",X"93",X"80",X"78",X"83",X"9B",X"B3",X"B3",X"98",X"70",X"47",
-		X"24",X"17",X"32",X"62",X"9B",X"C9",X"CE",X"B9",X"A3",X"9B",X"88",X"70",X"5D",X"55",X"68",X"93",
-		X"B6",X"BE",X"B3",X"AE",X"AE",X"A3",X"90",X"90",X"98",X"9B",X"AB",X"AB",X"AE",X"B3",X"AB",X"93",
-		X"78",X"65",X"68",X"78",X"75",X"70",X"68",X"78",X"8B",X"93",X"93",X"9E",X"B9",X"DC",X"FC",X"FC",
-		X"FC",X"D4",X"93",X"62",X"42",X"1C",X"01",X"01",X"04",X"0C",X"0C",X"1F",X"4A",X"78",X"AB",X"C9",
-		X"DC",X"E1",X"D9",X"C6",X"AB",X"90",X"70",X"47",X"09",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"1C",X"47",X"62",X"75",X"88",X"AB",X"D1",X"E9",X"EC",X"E9",X"E4",X"DC",X"F7",X"FC",X"FC",
-		X"FC",X"FC",X"FC",X"FC",X"E4",X"9E",X"80",X"75",X"7D",X"70",X"6D",X"75",X"80",X"8B",X"80",X"65",
-		X"4A",X"2C",X"04",X"01",X"01",X"01",X"04",X"2C",X"52",X"62",X"5A",X"4D",X"5A",X"78",X"9B",X"B3",
-		X"C1",X"AB",X"93",X"83",X"78",X"62",X"4D",X"4A",X"52",X"4A",X"3F",X"4D",X"5D",X"7D",X"90",X"9B",
-		X"9E",X"83",X"68",X"62",X"5D",X"68",X"78",X"88",X"88",X"8B",X"8B",X"80",X"62",X"47",X"3F",X"3A",
-		X"32",X"37",X"37",X"37",X"4D",X"70",X"88",X"8B",X"80",X"70",X"70",X"8B",X"B6",X"D4",X"D4",X"CE",
-		X"B9",X"B9",X"C9",X"C9",X"C6",X"B6",X"B9",X"D4",X"FC",X"FC",X"FC",X"FC",X"EC",X"B6",X"80",X"52",
-		X"37",X"2F",X"2C",X"37",X"62",X"98",X"D1",X"FC",X"FC",X"EC",X"D1",X"A3",X"68",X"4A",X"32",X"27",
-		X"27",X"3A",X"55",X"68",X"62",X"52",X"3F",X"1C",X"01",X"01",X"01",X"01",X"01",X"01",X"04",X"37",
-		X"5A",X"70",X"88",X"88",X"7D",X"65",X"52",X"47",X"52",X"68",X"83",X"9E",X"AE",X"B6",X"C1",X"B9",
-		X"B6",X"AE",X"98",X"78",X"5D",X"42",X"32",X"2C",X"2F",X"4D",X"7D",X"B9",X"F7",X"FC",X"FC",X"FC",
-		X"E1",X"AB",X"83",X"65",X"52",X"5A",X"68",X"65",X"52",X"3F",X"3F",X"3F",X"37",X"37",X"52",X"7D",
-		X"A6",X"C1",X"BE",X"9E",X"88",X"7D",X"68",X"5A",X"47",X"47",X"62",X"90",X"B3",X"C6",X"D9",X"EF",
-		X"FC",X"FC",X"E4",X"CE",X"B9",X"B3",X"B3",X"AE",X"AB",X"9B",X"75",X"55",X"37",X"11",X"01",X"01",
-		X"01",X"01",X"04",X"4D",X"88",X"AB",X"B3",X"AE",X"A3",X"9B",X"AE",X"C6",X"CE",X"C9",X"BE",X"B6",
-		X"B3",X"AB",X"AE",X"C6",X"EF",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"CE",X"88",X"4A",X"14",X"01",
-		X"09",X"2C",X"52",X"78",X"93",X"93",X"78",X"47",X"0C",X"01",X"01",X"01",X"01",X"09",X"09",X"11",
-		X"27",X"4D",X"62",X"68",X"7D",X"90",X"9E",X"AE",X"AB",X"8B",X"70",X"62",X"52",X"3A",X"1C",X"04",
-		X"11",X"2F",X"5A",X"83",X"9E",X"B3",X"B9",X"B9",X"AB",X"80",X"62",X"4D",X"4D",X"5A",X"65",X"75",
-		X"7D",X"83",X"83",X"70",X"4D",X"1F",X"0C",X"14",X"32",X"5D",X"70",X"68",X"65",X"68",X"83",X"9E",
-		X"9E",X"93",X"88",X"83",X"9B",X"BE",X"D9",X"E1",X"D1",X"B6",X"A3",X"93",X"88",X"88",X"8B",X"98",
-		X"A3",X"C6",X"FC",X"FC",X"FC",X"FC",X"FC",X"F4",X"D4",X"B3",X"88",X"65",X"4A",X"32",X"3A",X"5D",
-		X"88",X"B3",X"D4",X"E4",X"E1",X"B9",X"78",X"37",X"11",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
-		X"01",X"01",X"01",X"01",X"14",X"37",X"42",X"4A",X"5A",X"68",X"78",X"90",X"AE",X"C9",X"E1",X"E1",
-		X"C9",X"93",X"65",X"4D",X"32",X"1F",X"17",X"27",X"37",X"3F",X"42",X"4D",X"68",X"88",X"98",X"A3",
-		X"B6",X"C9",X"D4",X"E4",X"E4",X"D4",X"BE",X"A6",X"AE",X"C6",X"E4",X"FC",X"FC",X"FC",X"E4",X"AB",
-		X"6D",X"3F",X"27",X"2F",X"52",X"83",X"AB",X"AB",X"AE",X"AE",X"AE",X"98",X"70",X"5A",X"5A",X"65",
-		X"7D",X"88",X"80",X"5D",X"3A",X"24",X"11",X"11",X"2F",X"52",X"75",X"83",X"93",X"A3",X"C9",X"EF",
-		X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"FC",X"D4",X"98",X"5A",X"1F",X"01",X"01",X"01",X"11",X"2F",
-		X"5D",X"90",X"BE",X"E4",X"FC",X"FC",X"D9",X"A3",X"78",X"65",X"68",X"75",X"70",X"65",X"5A",X"4A",
-		X"2C",X"14",X"04",X"11",X"37",X"68",X"9B",X"A6",X"9B",X"88",X"83",X"90",X"93",X"90",X"8B",X"83",
-		X"7D",X"83",X"93",X"A6",X"B6",X"BE",X"B9",X"9E",X"68",X"42",X"2C",X"2F",X"47",X"5D",X"78",X"88",
-		X"90",X"93",X"90",X"70",X"52",X"37",X"17",X"11",X"17",X"2C",X"37",X"3F",X"4D",X"4A",X"3F",X"32",
-		X"2F",X"37",X"5A",X"7D",X"9B",X"9E",X"A6",X"AE",X"B6",X"D4",X"FC",X"FC",X"FC",X"FC",X"FC",X"EC",
-		X"E1",X"B9",X"93",X"6D",X"5A",X"5A",X"5D",X"68",X"75",X"78",X"83",X"83",X"83",X"83",X"70",X"5D",
-		X"4A",X"4D",X"62",X"7D",X"90",X"98",X"88",X"62",X"2F",X"01",X"01",X"01",X"01",X"1C",X"37",X"52",
-		X"65",X"68",X"5A",X"52",X"5D",X"75",X"7D",X"75",X"5D",X"4A",X"4D",X"65",X"88",X"AB",X"C6",X"D9",
-		X"D4",X"B6",X"93",X"83",X"70",X"5A",X"47",X"47",X"4A",X"3F",X"3A",X"3F",X"32",X"27",X"17",X"1F",
-		X"3F",X"68",X"93",X"9E",X"9B",X"93",X"98",X"A6",X"AB",X"AB",X"A3",X"A6",X"BE",X"E1",X"F7",X"FC",
-		X"FC",X"EC",X"D1",X"AE",X"93",X"8B",X"9B",X"B3",X"B6",X"B6",X"C6",X"C6",X"B6",X"A6",X"9E",X"93",
-		X"7D",X"5D",X"37",X"1C",X"1F",X"27",X"2C",X"37",X"52",X"75",X"93",X"98",X"8B",X"7D",X"65",X"5D",
-		X"65",X"75",X"88",X"9B",X"9E",X"9B",X"8B",X"80",X"83",X"8B",X"8B",X"83",X"93",X"AB",X"C9",X"DC",
-		X"CE",X"B9",X"A6",X"83",X"5D",X"32",X"17",X"01",X"01",X"04",X"1C",X"4A",X"80",X"B6",X"DC",X"E1",
-		X"D4",X"BE",X"A6",X"98",X"90",X"88",X"6D",X"4D",X"2C",X"11",X"04",X"04",X"1C",X"4D",X"83",X"B6",
-		X"DC",X"E4",X"D1",X"C1",X"B3",X"9B",X"80",X"68",X"68",X"68",X"75",X"7D",X"7D",X"70",X"52",X"2C",
-		X"04",X"01",X"01",X"01",X"11",X"2F",X"47",X"5D",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",
-		X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",
-		X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",
-		X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",
-		X"93",X"78",X"65",X"62",X"68",X"70",X"80",X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",
-		X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",
-		X"7D",X"62",X"47",X"2F",X"11",X"01",X"01",X"01",X"01",X"01",X"17",X"3F",X"65",X"78",X"93",X"9B",
-		X"9E",X"93",X"98",X"9B",X"98",X"A3",X"A6",X"AB",X"B3",X"C1",X"D1",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"75",X"65",X"52",X"4A",X"3F",X"3A",X"3F",X"52",X"68",X"80",X"93",X"AB",X"B6",X"C9",X"E1",X"E4",
-		X"D4",X"CE",X"CE",X"C9",X"BE",X"9E",X"7D",X"5A",X"37",X"27",X"1C",X"1F",X"37",X"5A",X"75",X"80",
-		X"8B",X"93",X"90",X"8B",X"88",X"88",X"80",X"80",X"83",X"80",X"88",X"A3",X"C6",X"E1",X"FC",X"FC",
-		X"F4",X"CE",X"A3",X"80",X"65",X"4A",X"37",X"37",X"3F",X"47",X"52",X"62",X"70",X"7D",X"70",X"62",
-		X"52",X"55",X"68",X"78",X"80",X"75",X"65",X"65",X"5D",X"55",X"5A",X"5A",X"65",X"80",X"98",X"A3",
-		X"9B",X"8B",X"7D",X"80",X"88",X"90",X"98",X"9B",X"93",X"93",X"9E",X"AE",X"B9",X"B6",X"AE",X"AE",
-		X"A6",X"93",X"78",X"65",X"52",X"4D",X"4A",X"52",X"68",X"78",X"88",X"93",X"90",X"83",X"80",X"6D",
-		X"5D",X"5D",X"62",X"68",X"6D",X"6D",X"5D",X"4A",X"37",X"2F",X"32",X"52",X"75",X"93",X"A6",X"AE",
-		X"AB",X"AE",X"B6",X"C6",X"BE",X"C1",X"B9",X"A6",X"98",X"8B",X"70",X"52",X"3A",X"2C",X"37",X"42",
-		X"5A",X"68",X"70",X"78",X"7D",X"88",X"93",X"98",X"90",X"7D",X"7D",X"88",X"90",X"98",X"93",X"7D",
-		X"52",X"2C",X"09",X"01",X"01",X"09",X"32",X"52",X"70",X"88",X"9B",X"93",X"90",X"93",X"98",X"90",
-		X"83",X"70",X"65",X"62",X"78",X"93",X"AE",X"BE",X"C6",X"B9",X"9E",X"83",X"70",X"65",X"5D",X"5A",
-		X"5A",X"5D",X"5A",X"55",X"55",X"47",X"37",X"27",X"1F",X"37",X"5A",X"78",X"88",X"8B",X"8B",X"93",
-		X"A3",X"A6",X"AB",X"A6",X"AB",X"BE",X"D4",X"E4",X"EC",X"EC",X"E1",X"C9",X"A6",X"90",X"83",X"90",
-		X"98",X"9B",X"9E",X"AE",X"AB",X"A6",X"9E",X"9B",X"9B",X"90",X"78",X"5A",X"3F",X"37",X"37",X"37",
-		X"3F",X"52",X"68",X"88",X"83",X"78",X"68",X"5A",X"55",X"65",X"78",X"8B",X"9E",X"A3",X"9B",X"90",
-		X"83",X"88",X"8B",X"88",X"80",X"8B",X"9E",X"B9",X"C9",X"B9",X"A6",X"93",X"75",X"52",X"32",X"1C",
-		X"11",X"0C",X"14",X"2C",X"5A",X"8B",X"BE",X"DC",X"E1",X"D9",X"C6",X"AE",X"9E",X"98",X"8B",X"75",
-		X"55",X"32",X"1C",X"11",X"11",X"24",X"52",X"88",X"B6",X"D9",X"E4",X"CE",X"BE",X"AE",X"98",X"7D",
-		X"68",X"65",X"68",X"75",X"78",X"7D",X"70",X"52",X"2F",X"09",X"01",X"01",X"01",X"11",X"2F",X"47",
-		X"5A",X"78",X"A3",X"D4",X"EC",X"FC",X"FC",X"F7",X"EC",X"EF",X"EC",X"D4",X"C9",X"C6",X"B9",X"9E",
-		X"80",X"65",X"68",X"70",X"78",X"7D",X"80",X"93",X"9E",X"AB",X"AE",X"AE",X"A3",X"8B",X"68",X"52",
-		X"42",X"32",X"27",X"1C",X"14",X"09",X"01",X"01",X"01",X"14",X"3F",X"78",X"A3",X"AE",X"AE",X"A3",
-		X"A6",X"BE",X"D4",X"D9",X"D9",X"D9",X"C6",X"B9",X"AB",X"93",X"78",X"65",X"62",X"68",X"70",X"80",
-		X"8B",X"88",X"7D",X"70",X"6D",X"78",X"7D",X"78",X"70",X"6D",X"83",X"9E",X"C1",X"CE",X"C1",X"B3",
-		X"98",X"75",X"52",X"3F",X"47",X"5A",X"68",X"7D",X"88",X"7D",X"62",X"47",X"2C",X"0C",X"01",X"01",
-		X"01",X"01",X"01",X"14",X"3A",X"65",X"7D",X"98",X"A3",X"A3",X"98",X"9B",X"9E",X"9E",X"A6",X"AB",
-		X"AB",X"B6",X"C6",X"D4",X"CE",X"BE",X"AB",X"90",X"78",X"68",X"5A",X"47",X"32",X"27",X"1F",X"24",
-		X"3A",X"62",X"80",X"9E",X"B9",X"CE",X"D4",X"E9",X"EC",X"E1",X"D1",X"D1",X"CE",X"C6",X"A6",X"80",
-		X"55",X"2F",X"17",X"04",X"11",X"2F",X"62",X"83",X"9B",X"A6",X"AB",X"9B",X"90",X"8B",X"88",X"78",
-		X"70",X"65",X"5A",X"65",X"88",X"A6",X"CE",X"EF",X"FC",X"FC",X"E1",X"B6",X"9E",X"88",X"68",X"52",
-		X"4A",X"47",X"3F",X"37",X"3A",X"47",X"47",X"3A",X"2F",X"2F",X"4A",X"68",X"80",X"83",X"75",X"65",
-		X"65",X"65",X"68",X"75",X"7D",X"88",X"9E",X"AB",X"AB",X"98",X"80",X"78",X"7D",X"80",X"8B",X"9E",
-		X"9E",X"9B",X"9E",X"AE",X"BE",X"C1",X"B3",X"A6",X"A3",X"A6",X"AB",X"9B",X"83",X"68",X"52",X"42",
-		X"3F",X"52",X"68",X"80",X"93",X"A3",X"A6",X"B3",X"A6",X"93",X"88",X"88",X"93",X"90",X"83",X"68",
-		X"4D",X"37",X"2C",X"2F",X"47",X"68",X"90",X"AB",X"AE",X"A6",X"A6",X"9B",X"88",X"75",X"68",X"62",
-		X"52",X"42",X"32",X"27",X"11",X"01",X"01",X"11",X"27",X"3F",X"5A",X"65",X"68",X"78",X"8B",X"A6",
-		X"C1",X"C6",X"B9",X"B3",X"B3",X"AB",X"A3",X"8B",X"68",X"42",X"24",X"11",X"11",X"11",X"27",X"4D",
-		X"70",X"98",X"B9",X"DC",X"E9",X"E9",X"E1",X"CE",X"AB",X"98",X"90",X"83",X"83",X"93",X"A3",X"B6",
-		X"AE",X"A3",X"90",X"78",X"5D",X"4A",X"4D",X"62",X"78",X"83",X"80",X"80",X"83",X"7D",X"68",X"52",
-		X"37",X"1F",X"1F",X"2F",X"47",X"55",X"65",X"7D",X"90",X"93",X"98",X"A3",X"AE",X"B3",X"B9",X"B6",
-		X"B6",X"C1",X"C6",X"B9",X"A6",X"8B",X"80",X"70",X"65",X"52",X"4A",X"52",X"62",X"65",X"68",X"7D",
-		X"90",X"AB",X"C6",X"D1",X"CE",X"AE",X"88",X"68",X"65",X"62",X"52",X"52",X"4D",X"3F",X"2F",X"27",
-		X"27",X"3A",X"62",X"83",X"9E",X"B3",X"A6",X"9E",X"93",X"90",X"8B",X"7D",X"68",X"62",X"65",X"65",
-		X"65",X"55",X"3F",X"27",X"14",X"11",X"14",X"1C",X"2F",X"4A",X"62",X"78",X"98",X"B6",X"D1",X"E4",
-		X"E4",X"E1",X"E4",X"F7",X"FC",X"F7",X"E4",X"D1",X"BE",X"AB",X"98",X"83",X"8B",X"98",X"93",X"90",
-		X"93",X"90",X"83",X"78",X"70",X"6D",X"62",X"4A",X"2C",X"17",X"14",X"1C",X"27",X"3F",X"4D",X"5D",
-		X"68",X"68",X"68",X"68",X"75",X"8B",X"9E",X"A6",X"9E",X"9B",X"98",X"98",X"93",X"80",X"70",X"62",
-		X"52",X"4A",X"42",X"3A",X"2F",X"27",X"2C",X"2F",X"3F",X"5D",X"80",X"90",X"9B",X"A3",X"AE",X"C9",
-		X"E1",X"E4",X"DC",X"CE",X"C9",X"CE",X"C6",X"B3",X"98",X"8B",X"83",X"75",X"68",X"6D",X"7D",X"90",
-		X"A3",X"B3",X"B9",X"AE",X"98",X"7D",X"70",X"62",X"4A",X"2F",X"17",X"11",X"17",X"24",X"37",X"52",
-		X"62",X"75",X"80",X"80",X"80",X"88",X"8B",X"8B",X"98",X"9B",X"9E",X"AB",X"B6",X"AE",X"A3",X"90",
-		X"83",X"80",X"7D",X"83",X"90",X"90",X"88",X"75",X"62",X"52",X"47",X"42",X"4A",X"5D",X"75",X"8B",
-		X"A3",X"AB",X"AB",X"A3",X"93",X"98",X"9E",X"AE",X"BE",X"BE",X"AB",X"88",X"68",X"52",X"3A",X"37",
-		X"47",X"62",X"83",X"98",X"A3",X"9B",X"98",X"98",X"88",X"68",X"52",X"4D",X"52",X"62",X"65",X"62",
-		X"62",X"5D",X"4A",X"37",X"27",X"2C",X"3F",X"5D",X"6D",X"75",X"75",X"80",X"90",X"A3",X"B3",X"BE",
-		X"C6",X"C1",X"B9",X"AB",X"9E",X"83",X"68",X"52",X"3F",X"27",X"11",X"0C",X"11",X"1C",X"3F",X"68",
-		X"9B",X"B6",X"BE",X"B6",X"B3",X"B6",X"BE",X"C9",X"C6",X"AE",X"9B",X"8B",X"80",X"7D",X"83",X"93",
-		X"A3",X"AE",X"A3",X"9E",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"7D",X"68",X"62",X"5D",X"62",X"5D",
-		X"52",X"4D",X"5A",X"52",X"52",X"52",X"52",X"52",X"5A",X"5A",X"5A",X"62",X"68",X"78",X"88",X"90",
-		X"98",X"A6",X"B6",X"B9",X"B6",X"B3",X"B6",X"B9",X"B9",X"B6",X"AE",X"AB",X"93",X"78",X"65",X"4D",
-		X"32",X"24",X"24",X"32",X"52",X"70",X"83",X"88",X"83",X"7D",X"70",X"65",X"68",X"6D",X"6D",X"6D",
-		X"68",X"65",X"68",X"68",X"65",X"5D",X"55",X"5D",X"70",X"8B",X"90",X"93",X"8B",X"80",X"7D",X"7D",
-		X"8B",X"9E",X"A6",X"A3",X"9E",X"9E",X"A3",X"A3",X"98",X"88",X"80",X"75",X"68",X"62",X"55",X"4D",
-		X"4A",X"4D",X"5D",X"75",X"93",X"AE",X"B6",X"AB",X"93",X"78",X"65",X"52",X"5A",X"5D",X"65",X"78",
-		X"88",X"88",X"80",X"75",X"70",X"68",X"5D",X"5A",X"5D",X"62",X"68",X"70",X"75",X"78",X"7D",X"7D",
-		X"80",X"78",X"70",X"65",X"5D",X"52",X"5A",X"70",X"8B",X"A3",X"AE",X"AE",X"A6",X"9B",X"90",X"83",
-		X"75",X"68",X"55",X"4D",X"4A",X"4A",X"4D",X"5A",X"78",X"93",X"B9",X"D4",X"E4",X"E1",X"CE",X"BE",
-		X"AE",X"9B",X"88",X"78",X"78",X"78",X"78",X"68",X"62",X"55",X"4D",X"3A",X"32",X"3A",X"4D",X"68",
-		X"7D",X"80",X"7D",X"78",X"75",X"7D",X"88",X"98",X"A3",X"AE",X"AE",X"AB",X"AE",X"B6",X"C6",X"D1",
-		X"D4",X"D4",X"C6",X"AB",X"98",X"83",X"78",X"65",X"4D",X"3F",X"3F",X"3F",X"4A",X"5A",X"68",X"70",
-		X"68",X"68",X"70",X"80",X"8B",X"93",X"8B",X"7D",X"70",X"6D",X"68",X"70",X"75",X"75",X"78",X"78",
-		X"75",X"68",X"65",X"62",X"6D",X"83",X"98",X"AE",X"B6",X"A6",X"98",X"90",X"80",X"75",X"68",X"5D",
-		X"62",X"68",X"80",X"93",X"9B",X"93",X"90",X"80",X"6D",X"5A",X"4A",X"42",X"47",X"52",X"5D",X"6D",
-		X"83",X"90",X"90",X"83",X"80",X"80",X"75",X"75",X"70",X"68",X"65",X"5A",X"52",X"4D",X"52",X"65",
-		X"7D",X"98",X"A6",X"AB",X"AB",X"A6",X"9E",X"9B",X"90",X"80",X"75",X"6D",X"65",X"52",X"52",X"52",
-		X"52",X"4D",X"42",X"3F",X"47",X"4A",X"55",X"5D",X"62",X"62",X"62",X"62",X"68",X"7D",X"88",X"93",
-		X"A3",X"9E",X"A3",X"98",X"90",X"90",X"98",X"A3",X"B6",X"C1",X"BE",X"B6",X"B3",X"AB",X"9B",X"88",
-		X"75",X"70",X"68",X"65",X"70",X"78",X"7D",X"70",X"68",X"68",X"68",X"68",X"65",X"62",X"5D",X"68",
-		X"7D",X"90",X"9B",X"9B",X"98",X"98",X"98",X"93",X"98",X"9E",X"9B",X"98",X"93",X"93",X"90",X"83",
-		X"80",X"80",X"78",X"68",X"62",X"62",X"65",X"75",X"83",X"88",X"8B",X"90",X"8B",X"7D",X"70",X"68",
-		X"65",X"5D",X"55",X"52",X"4D",X"4A",X"4D",X"5A",X"5D",X"65",X"70",X"80",X"8B",X"93",X"9E",X"9E",
-		X"9B",X"9E",X"A3",X"9B",X"98",X"90",X"88",X"83",X"83",X"88",X"90",X"A6",X"B9",X"BE",X"C1",X"C6",
-		X"C6",X"C6",X"B6",X"9B",X"83",X"65",X"52",X"4A",X"4D",X"5D",X"6D",X"80",X"8B",X"93",X"8B",X"80",
-		X"65",X"5A",X"52",X"52",X"52",X"47",X"3F",X"3A",X"47",X"52",X"5D",X"6D",X"83",X"93",X"9B",X"9E",
-		X"98",X"8B",X"88",X"80",X"80",X"78",X"6D",X"68",X"68",X"70",X"70",X"68",X"68",X"62",X"5A",X"5A",
-		X"5D",X"5A",X"5D",X"65",X"70",X"75",X"8B",X"98",X"9B",X"9B",X"9B",X"93",X"88",X"88",X"83",X"88",
-		X"88",X"93",X"9B",X"98",X"8B",X"80",X"78",X"70",X"68",X"68",X"70",X"80",X"88",X"90",X"93",X"9B",
-		X"9E",X"98",X"98",X"98",X"98",X"90",X"83",X"78",X"78",X"6D",X"6D",X"78",X"88",X"98",X"A3",X"AB",
-		X"AB",X"A6",X"98",X"83",X"70",X"52",X"47",X"37",X"32",X"27",X"27",X"37",X"47",X"4D",X"65",X"75",
-		X"88",X"90",X"98",X"90",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"68",X"62",X"5D",X"4D",X"42",
-		X"3A",X"3A",X"3F",X"47",X"52",X"5A",X"68",X"78",X"83",X"90",X"A3",X"AE",X"B6",X"B9",X"B6",X"AE",
-		X"B3",X"B6",X"C1",X"C6",X"BE",X"B9",X"B9",X"AE",X"9B",X"88",X"80",X"75",X"68",X"65",X"65",X"70",
-		X"78",X"83",X"8B",X"90",X"88",X"7D",X"65",X"5A",X"55",X"5A",X"52",X"4D",X"47",X"42",X"3F",X"47",
-		X"4A",X"52",X"65",X"7D",X"93",X"9B",X"98",X"93",X"90",X"93",X"9B",X"A6",X"AE",X"AE",X"A6",X"98",
-		X"8B",X"78",X"68",X"5A",X"52",X"52",X"5A",X"65",X"68",X"75",X"75",X"70",X"70",X"7D",X"80",X"83",
-		X"83",X"80",X"80",X"80",X"8B",X"98",X"A3",X"A3",X"A6",X"A3",X"9B",X"93",X"90",X"8B",X"88",X"80",
-		X"78",X"70",X"62",X"5A",X"5A",X"52",X"52",X"55",X"5A",X"62",X"68",X"75",X"70",X"6D",X"65",X"65",
-		X"68",X"6D",X"70",X"70",X"70",X"75",X"75",X"7D",X"83",X"88",X"93",X"9B",X"A3",X"A3",X"A6",X"A6",
-		X"A3",X"9E",X"93",X"88",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"7D",X"70",X"68",X"62",
-		X"62",X"68",X"70",X"78",X"7D",X"7D",X"78",X"75",X"68",X"68",X"62",X"62",X"68",X"78",X"78",X"7D",
-		X"75",X"68",X"6D",X"6D",X"70",X"75",X"7D",X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"80",X"83",
-		X"88",X"8B",X"88",X"83",X"80",X"80",X"83",X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",
-		X"75",X"6D",X"68",X"75",X"80",X"83",X"88",X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",
-		X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",
-		X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",
-		X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"7D",X"78",X"78",X"75",X"70",X"70",X"6D",X"68",X"6D",X"70",X"78",X"80",
-		X"80",X"80",X"83",X"88",X"90",X"8B",X"8B",X"8B",X"88",X"80",X"7D",X"78",X"70",X"68",X"68",X"68",
-		X"68",X"6D",X"6D",X"70",X"78",X"7D",X"83",X"8B",X"8B",X"90",X"8B",X"88",X"88",X"88",X"88",X"83",
-		X"80",X"80",X"83",X"80",X"80",X"7D",X"83",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"78",X"78",
-		X"75",X"70",X"70",X"70",X"75",X"78",X"78",X"78",X"75",X"75",X"70",X"70",X"75",X"78",X"75",X"75",
-		X"75",X"75",X"78",X"7D",X"80",X"7D",X"7D",X"7D",X"83",X"88",X"8B",X"88",X"88",X"88",X"88",X"88",
-		X"8B",X"90",X"90",X"88",X"83",X"7D",X"7D",X"78",X"75",X"75",X"75",X"7D",X"7D",X"80",X"7D",X"78",
-		X"75",X"70",X"70",X"78",X"80",X"88",X"88",X"88",X"88",X"83",X"7D",X"78",X"78",X"80",X"83",X"83",
-		X"83",X"80",X"78",X"75",X"75",X"75",X"78",X"80",X"80",X"83",X"83",X"80",X"7D",X"78",X"6D",X"68",
-		X"65",X"62",X"5D",X"5A",X"62",X"65",X"68",X"75",X"80",X"8B",X"90",X"93",X"90",X"88",X"83",X"80",
-		X"78",X"75",X"75",X"70",X"68",X"65",X"5D",X"5D",X"55",X"5A",X"5D",X"65",X"68",X"75",X"75",X"80",
-		X"83",X"8B",X"90",X"9B",X"A3",X"A6",X"A6",X"9E",X"9B",X"98",X"98",X"9E",X"9E",X"A3",X"A3",X"A6",
-		X"A3",X"9B",X"8B",X"88",X"7D",X"75",X"6D",X"68",X"6D",X"75",X"7D",X"7D",X"83",X"83",X"80",X"75",
-		X"6D",X"68",X"68",X"68",X"65",X"62",X"5D",X"5A",X"5A",X"5D",X"62",X"68",X"78",X"80",X"83",X"80",
-		X"7D",X"80",X"83",X"8B",X"98",X"9B",X"9B",X"98",X"90",X"8B",X"7D",X"70",X"68",X"62",X"65",X"68",
-		X"70",X"78",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"7D",X"7D",X"7D",X"83",X"90",X"98",
-		X"9B",X"9E",X"9B",X"98",X"90",X"8B",X"83",X"83",X"7D",X"75",X"70",X"65",X"5D",X"5D",X"5A",X"5D",
-		X"62",X"65",X"68",X"75",X"75",X"75",X"75",X"68",X"6D",X"6D",X"70",X"70",X"75",X"70",X"75",X"75",
-		X"78",X"7D",X"83",X"90",X"98",X"9B",X"9B",X"9E",X"9E",X"9E",X"9E",X"93",X"88",X"83",X"7D",X"7D",
-		X"7D",X"80",X"83",X"80",X"80",X"7D",X"75",X"68",X"65",X"65",X"68",X"75",X"78",X"7D",X"78",X"78",
-		X"78",X"6D",X"68",X"65",X"68",X"6D",X"78",X"7D",X"7D",X"75",X"6D",X"6D",X"70",X"75",X"78",X"80",
-		X"83",X"80",X"80",X"80",X"83",X"83",X"80",X"83",X"83",X"88",X"8B",X"88",X"83",X"80",X"80",X"83",
-		X"8B",X"98",X"9E",X"9E",X"9E",X"9B",X"90",X"83",X"7D",X"75",X"6D",X"68",X"75",X"80",X"83",X"88",
-		X"8B",X"90",X"8B",X"83",X"7D",X"75",X"75",X"78",X"7D",X"80",X"80",X"75",X"68",X"5D",X"52",X"4A",
-		X"4D",X"52",X"5D",X"68",X"6D",X"78",X"80",X"88",X"8B",X"98",X"9B",X"A3",X"A3",X"9B",X"93",X"8B",
-		X"88",X"7D",X"70",X"68",X"65",X"65",X"62",X"62",X"62",X"65",X"70",X"78",X"7D",X"80",X"88",X"8B",
-		X"93",X"93",X"90",X"8B",X"88",X"80",X"83",X"88",X"90",X"9E",X"9E",X"9B",X"9B",X"93",X"88",X"7D",
-		X"7D",X"7D",X"78",X"7D",X"78",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"78",X"78",X"75",
-		X"75",X"70",X"75",X"6D",X"68",X"6D",X"70",X"78",X"80",X"83",X"80",X"83",X"88",X"90",X"8B",X"8B",
-		X"88",X"83",X"7D",X"78",X"75",X"6D",X"68",X"68",X"68",X"65",X"68",X"68",X"68",X"70",X"75",X"7D",
-		X"88",X"83",X"88",X"88",X"80",X"83",X"83",X"88",X"8B",X"88",X"88",X"88",X"83",X"80",X"7D",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"7D",X"75",X"75",X"75",X"75",X"70",
-		X"70",X"68",X"68",X"68",X"68",X"70",X"70",X"75",X"75",X"75",X"75",X"78",X"83",X"83",X"83",X"88",
-		X"88",X"90",X"98",X"98",X"93",X"90",X"90",X"8B",X"88",X"88",X"8B",X"88",X"80",X"78",X"78",X"75",
-		X"70",X"68",X"68",X"65",X"68",X"70",X"78",X"78",X"78",X"75",X"75",X"70",X"78",X"80",X"83",X"83",
-		X"80",X"7D",X"70",X"68",X"65",X"68",X"70",X"7D",X"83",X"83",X"83",X"80",X"75",X"70",X"68",X"65",
-		X"65",X"65",X"68",X"6D",X"70",X"78",X"7D",X"7D",X"7D",X"83",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"80",X"83",X"8B",X"90",X"93",X"93",X"8B",X"83",X"7D",X"78",X"70",X"6D",X"68",X"65",X"65",X"62",
-		X"65",X"68",X"70",X"7D",X"88",X"88",X"93",X"90",X"90",X"90",X"90",X"93",X"93",X"93",X"98",X"90",
-		X"88",X"80",X"78",X"78",X"75",X"78",X"80",X"88",X"90",X"90",X"93",X"8B",X"8B",X"88",X"7D",X"78",
-		X"6D",X"65",X"65",X"68",X"6D",X"75",X"80",X"83",X"88",X"88",X"88",X"83",X"83",X"83",X"83",X"80",
-		X"7D",X"80",X"7D",X"75",X"6D",X"68",X"5D",X"55",X"52",X"52",X"62",X"68",X"70",X"75",X"75",X"75",
-		X"78",X"7D",X"83",X"80",X"83",X"83",X"83",X"83",X"88",X"8B",X"90",X"98",X"98",X"9B",X"9B",X"93",
-		X"8B",X"83",X"7D",X"78",X"78",X"70",X"75",X"7D",X"80",X"80",X"83",X"80",X"80",X"75",X"70",X"68",
-		X"68",X"68",X"65",X"68",X"68",X"65",X"68",X"70",X"78",X"7D",X"88",X"88",X"88",X"83",X"83",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"68",X"68",X"68",X"68",X"6D",X"6D",X"70",X"70",X"75",
-		X"75",X"7D",X"83",X"83",X"88",X"83",X"88",X"83",X"88",X"83",X"83",X"8B",X"88",X"8B",X"88",X"88",
-		X"80",X"7D",X"7D",X"75",X"6D",X"68",X"6D",X"70",X"7D",X"80",X"7D",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"80",X"7D",X"7D",X"80",X"80",
-		X"83",X"83",X"80",X"80",X"7D",X"78",X"75",X"70",X"68",X"6D",X"75",X"78",X"7D",X"80",X"80",X"80",
-		X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"88",X"88",X"8B",X"8B",X"8B",
-		X"8B",X"88",X"83",X"83",X"80",X"78",X"75",X"75",X"70",X"70",X"75",X"75",X"80",X"83",X"80",X"83",
-		X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",
-		X"75",X"75",X"78",X"7D",X"7D",X"80",X"80",X"83",X"83",X"83",X"83",X"88",X"83",X"83",X"83",X"88",
-		X"83",X"83",X"88",X"8B",X"88",X"88",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"7D",X"7D",X"75",X"75",X"75",X"75",X"75",X"70",X"75",X"75",X"75",X"78",X"83",
-		X"80",X"83",X"80",X"7D",X"80",X"78",X"78",X"80",X"80",X"80",X"7D",X"80",X"80",X"80",X"7D",X"75",
-		X"70",X"68",X"68",X"68",X"68",X"68",X"70",X"75",X"7D",X"83",X"8B",X"90",X"90",X"8B",X"83",X"80",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"75",X"75",X"75",X"70",X"70",X"75",X"75",
-		X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"7D",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"83",X"83",
-		X"8B",X"8B",X"8B",X"88",X"83",X"83",X"80",X"83",X"7D",X"7D",X"7D",X"7D",X"75",X"75",X"78",X"7D",
-		X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"7D",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"7D",X"80",X"78",X"80",X"80",X"78",X"78",X"78",X"78",X"7D",X"78",X"7D",
-		X"78",X"78",X"7D",X"78",X"78",X"78",X"75",X"78",X"78",X"7D",X"78",X"7D",X"80",X"78",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"78",X"78",X"7D",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",
-		X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"78",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"75",X"75",X"75",X"75",X"83",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"88",X"83",
-		X"80",X"80",X"7D",X"78",X"75",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"75",X"75",X"75",X"78",X"83",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"75",X"78",X"75",X"75",X"78",
-		X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"78",X"78",X"78",X"75",X"75",X"75",X"70",X"75",X"75",X"7D",X"7D",X"80",X"80",X"80",
-		X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"80",X"78",X"78",X"7D",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"78",X"78",X"78",
-		X"78",X"78",X"78",X"78",X"78",X"75",X"78",X"78",X"80",X"80",X"80",X"80",X"80",X"80",X"83",X"83",
-		X"83",X"83",X"88",X"83",X"83",X"83",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"7D",X"78",X"78",X"78",X"75",X"75",
-		X"75",X"78",X"7D",X"78",X"83",X"80",X"80",X"80",X"80",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"78",X"78",X"78",X"78",X"75",X"75",X"75",X"75",X"78",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",
-		X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"78",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"80",X"83",X"83",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"83",X"80",X"83",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"78",X"78",X"7D",X"78",X"7D",X"7D",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",X"78",X"78",X"7D",
-		X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"80",X"83",X"80",X"80",X"83",X"80",X"80",X"83",X"7D",X"7D",X"7D",
-		X"7D",X"78",X"78",X"78",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"7D",X"80",X"80",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"7D",X"7D",X"7D",X"78",X"7D",X"78",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"78",X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"7D",
-		X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",X"78",X"78",X"7D",X"78",X"78",X"7D",
-		X"7D",X"80",X"80",X"80",X"80",X"83",X"83",X"83",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"7D",
-		X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"78",
-		X"78",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",X"7D",X"7D",X"80",X"80",X"80",X"80",X"80",X"80",
-		X"80",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"80",X"7D",X"7D",X"7D",X"7D",X"7D",X"7D",X"78",
-		X"7D",X"78",X"7D",X"80",X"80",X"80",X"80",X"7D",X"80",X"83",X"80",X"80",X"80",X"80",X"80",X"80");
-begin
-process(clk)
-begin
-	if rising_edge(clk) then
-		data <= rom_data(to_integer(unsigned(addr)));
-	end if;
-end process;
-end architecture;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/build_roms_galaxian.bat b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/build_roms_galaxian.bat
deleted file mode 100644
index 8d35a90e..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/build_roms_galaxian.bat	
+++ /dev/null
@@ -1,20 +0,0 @@
-@echo off
-
-
-copy /b/y warofbug.1j + warofbug.1k gfx1.bin > NUL
-copy /b/y warofbug.u + warofbug.v + warofbug.w + warofbug.y + warofbug.z main.bin > NUL
-
-
-
-romgen warofbug.cla    GALAXIAN_6L  5 a r e     > GALAXIAN_6L.vhd
-
-
-romgen gfx1.bin        GFX1      12 a r e > GFX1.vhd
-romgen main.bin        ROM_PGM_0 14 a r e > ROM_PGM_0.vhd
-
-romgen warofbug.1j    GALAXIAN_1H 11 a r e > GALAXIAN_1H.vhd
-romgen warofbug.1k    GALAXIAN_1K 11 a r e > GALAXIAN_1K.vhd
-
-
-echo done
-pause
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/gfx1.bin b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/gfx1.bin
deleted file mode 100644
index 3593689f5904516a63d14c95e2bba482b4f13dd0..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 4096
zcmeHKU5FG{7C!xx?$)$+t;}qCu<WWx6MQhS$j?}llv9;q5FbQ*%frH?39f`iVkd!E
zS<0H5iI^eC*fe3;m7!-b1oE&Ck_TB5nJGnP4fKp5FA+37wGy2Wl9^@{sgTO8oLkk^
zKQ&577T@+j_r2$S_uTK+Ik)S(EgP36P8u@A<CKoX0bW`A^h|AWFPv(ueNsJ{gbbxu
zUX}B}&z?Pd_VzcBtyQaEnhIF<x!ROvLH4yXXFgdw0=oORYIUsy!{(LAE9Nj9q19@Y
zQW%||n3%`)Wdl3tPXxn2Dro43_FLm>wW_}^r5wkxb#d{D2>_SI<MC7yCgxvL@;Htj
zJ{bU|Wx0$UN_oFEaP|Z>pzKUePU84q-KqDP|Hi%ADduO#zN}X79RflqC8V`3b)o6-
zn|Y@R4z9yf2j*7{*;ttet63;CEr3fm*FLRHodjj%osT~H$A}{94w^0l2fN-Afs<c#
zz8b%#?+C}k_CYx2Cy^6ggp5L$Pa{9PDC80>X)ZmzOqEP3lPGGOsFgU7Ha^b5<j2K~
z_5_#c?=O-qrDTOo#VT%KEfL8<h-Z?lUjb2LEkGu7tH1wwL@VNfmp^;HzyDSy1MuOW
z4u}=P@Ywb~9~bvkp7Qa&?J<TwRoN#3aQk-hDLgk2Pd+lW^Y0>PECfH=Gp9-gOa8;g
z%}IuHeSQ3?9UVM2qP%0m2^}ZLAeDlHmEvd~h{pOj0vdt*Xt8n-QUMO2XaW!`z*Arm
z5HuNiJeavU10LGN*;(RE9s`dYBi<aD^RRNB@0egx((pb%fBth1*lhDH@8bFMS8>pw
zi<V9CK)1~FR+o<}JZ1om5Mto@w|elIumAj93&$yl-?UbG;(vHsmboBaL)>lNUhKwa
zmU`oR`J?+`{Fl1;@8jE-y7&=~`aS%J_xPCdk|Znb=a2G>Ql3{7!|<Occ;24<K$cfz
zS?|Vs_#u(rTu>COb6~&5kNLlKd`~C8QGV0I{68DkM}sIoi#J;JBO2lnevHTbZwu;+
zTk`AO#TV?d^Zl^#4pXZasYeu#<|B$n^RW((<fB#ZcKyaxwZP|cX$$P8jX$!eDf;Vg
zs={V4nsjy1b;?nk&*!(YH&p)k&kKzk9X!MDIljE=nc@79H+tTb;evqlF}sW}PTWB_
zKWsz(e0{M&*YWeitl(&gaeN_AS0-T`@ap*L@|~`8=>P5v?TLZ;q14d4s1eBmOM(pp
zt&kw}*YLf&gsW;!{oU~!9#giet4njlcItN<tKPAft{+nea>?($yKa6z?P!U#AiSXN
z9<=PHW85(QrS93iRS<INBkqk0EJ4K&_Iuv`4~h?J3o54ER157qL^|^S_5b1Of2j9i
z`=I;418`QZ7>s!UdE>4QjyLA3D>$IvHS!EiBx75)vyOx>H7owO$UzEVG?@ghgtCm%
z%ZU)PfJ69%CgM~SrxZaPJ6fRsBfEV4*G@DZ842`%45xPVpW&$gqL2IfKXyXw=zk)X
zVETWcuG@*kyZ;%-<7V4;>UOQA|A;gF-+!fp|M#YQk&;0F6R}5gsQ;I**`;&2M`H=5
z|L02fwaYF2Poy{HQ2(tZyCmf{r4dhoRI-;W)PE-Y|BIC!cXp<(ODuux`k}kE#^L9-
z`S&F@g!tTC3%AhM-Id$sa9ck}*{M&@-C*%}WAX7?<1a%)TUei2`NzenX;;U0OJJ?|
z?)7J97FzsZF}~SauRnL8#gE(b_tWdwXD;~sKo|q=C*m)hX8f(~A>QjV{TD?EGZ~o9
z^3mqUs!JS)`rdwTvV4U6enciONn*LJ1A2!)STLT<=4GjkxA|Lq>-bsz2MZfRILhzm
zudUaFK$PFFAK%I^;t~EJ|Alt`S-lU1_lc0St9{sb7gf-W)FX;V^AW|P`B;ZX^5LKV
z1-)G#eYYwI*-dExTPj&(UHFh`9(@M&A0+e6z52CwTsUz+C~QM{O63jL{r9;qO5u2h
zfA&zL=60VWcFz3sj_uRoJarF-qyFO`OzD35AM%$ZbEWJ4!TxceO%KNsf&Np9w}Ynb
z2IKh6D<*B!$3y@1;GDzWC;zxGxM}cmsQ<#?QSa)!rV*>u#Dgu~7e6eDK3>wa(Vcu<
z$tu0^hb1n+Epoqj@2!Cp!<#mNoS?j5{_wSj@?O8^dFs!NrK96RLi)3xexfVWjulG_
zxm|)fj4#xt>*^PTZK{wHaxuekT<6>7Kf~uK_GMKy+gB7TTC=HD#PB`<**;49vf;FK
F?Jorb`C0$~

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/main.bin b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/main.bin
deleted file mode 100644
index c5f466976785bad8cc9a084271117b628717ca4f..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 10240
zcmdT~dvF`adEYx64j>7V2a=+W5-A=CS-QxI1;I4KAQZgdLo{oNfcX%uBx6cxBB`B>
zMb~zzCxpaFooO<z?Q~q*lSygMG>x1;U^Q*wIvtr3Dw+^<DV0W|<jK{f9g_0Iw#c|j
zBw2UY-`;_G#F;kjG))T<cl-FhZ@=CB_IoYXllF9$xUw5d`V(>TmA>JibS)<y-xO=R
zH{M0Q+LrxWp@T@ooh@;1VTG@@c6E34Z6{em++BSS;4Q^A#j}4{mE9+1FS@gzb!CTq
zx&2GBN0)$R_HuFdK~KlfrF57Z@<zxW?};-r`iwCXAZ>nfKbIo!y{ug$THY7nX=6|u
zc57$c+D4-3#Tq5rSH*}#FXcN`w|3Ai`vNr4AXDvWk2X}YU`*@N)2EL`IZ$56vF~D;
zuunGX!o#S_9xKUKaM@li`vjLg!hzq?99fq27H78xveN;=OJYw)tbHp@Y>I8|=%MQ^
zKOvDSnjcg}JwRfzfM=_o^k!5!a4$Dllk|8z@qoMSp<wW!d3W<=bhXTS^kHv~D0EwD
zWONGH93g(101bCQipj2k)Oye~LM!%}eQM1f(<+lx@3Q#pH8Z4$L&1lFBB>N)y@}+2
z`YU)q8Bca*#w#Twn5+oO7t2V1Ytx#z2uEk<!yHWq$TpEo2FR|-s1+uA9Nvo=?*=%R
zy^Md9V);YL!+Nr4Lq@$rA1>09#b&w6wdljem-M9DTo&@`jqU&mCOa2idE*qXC&m0<
z>%(I96rT=DRO=$qQEe0PPw;cm6bkD}d%zVFFQ+F1u2%6f#%~i-lY!d$26wE%-3s`0
zcpc52BhHYYa)xBXfx-9Xa1|q|k=vqEjH=GhIeeG-XE6X93ElD?{ttM0-X4=RIUphf
zkzMGz4#+xQlMibZTu$(LJ7b$WXnadYkLC9H?9H{@WyOX4#RlJ030t;MGU*JEL{!2;
z;$yc3$o=WX(k@JI+hS!16`BSZW^J#y18!Ljqtup0KN04%uXyAjNJ3r%2`Yvrqu#Ke
zY7csB2u%8-JC_doDC9donSY(FFa(vXux0mu^C1$_+ZONXSWoe}r;FMZR<;Xa%MDSE
ziEgf>k>XiRT18h?sYrQIDrxKKXz%K?++HEk)6v^Y*Ds!-*8aY}csDxuM1Su+Xpi^M
z@UM3Igs$%1j-Eam>yG!`gOk@5@9MT(RmB^7Iy!7%i(es78td82*eQJ0f3kVKbqPx3
zj6SU=xyMBkhitbQMMe{Ws1akB(>L<b<xgf#&I!;LoI;8=9DhsDyE%~*aZ{EawEvRC
zwA7-rAsmEY_7?&a$wKZoBTL<eL)QS|h}$M?*p#=p^&Nu#pex^c@^kLwY`HN^g4r*+
zljZo>HKS<B@m{w*Rx&f*GMv+fe9_u)30))8h?{oi+Z1KC9{OjnCQ?E>56;$`uI7)u
z5?Xb@><v{mg&|Bi{W~H%uRvOm&m1&gYreol=y3>8&R<Oq&d%?yktZUA4njW+lz(sV
zy@AJGg2sC3v9O!wqN%WpMqD&AE?)`oOx{;a`gu}w!0c0go(}MB;=##WIzXv7GRbNO
z3Np{%k0R4E9z1v9Y0G^sLbgFSix6oq%|*N*8}ZPVu!pA60Jdi3%&4}H>G1r(D3kW6
z06x>;L3_6(r(JPt6{3HKZ!V{`Frdy^c`zc<IEZ`+q{>M~@uHqlc-a>ryJkntQT0GZ
z9onA(gyJ^2Q+IkyUMb$&vN|k+tcOO{(ab1NOitZp@;~0{!Bo;>)ug{!nDc*2n2X*X
z{&ufFEL_9_K{?BT@-|Uw3<jkS!4Qrto6yeVOK?b`-k=lGVPQx%F&YRyC%*vpMJhj^
zzh{&Uq{#j~f?VNm6~G*`QBfMMq;vAu=NMYf{~4!UxsZ>m??y+_C(jsA29Q+AXyT@f
zCU<FcRk$5XM}}ryV_di>7A|VdX>WNVZ8UtaExfla(vIaQry13?cU^pM_)yzfcX)rB
z1{-EC@3?JYikO8dYE5p)jCTg!O!%j)rfW6Qhq(YD4Q(`M1lp+f9dD$SnpYJOme{>(
zA)^W{;Z|Gw#Fa^{v?!8byBEW(x<PpmV-DndkN+jZ$|zO)GKw2(BYX0{ul|zFcBfJe
zj4@BRjYjUH>&}Xp1|yt<EW{`Z+N0j+WsH!!4%SZ1bD=e3UVFlj2-sI<m1F_WR-;ky
zXMD?yqr#}sBoL#q7}_z0wYKTW-<&yPB+0t`-R#d8=8YtGz2d?&{R%OXJSJ7MLB8TA
z2_xwmtnqUs^Inhfs9-$eP8!2v=JYgHn#OT@W}^dole<jw7wZ@;`&bc%siX2;@GG>Z
zirF%Z7gkLVY@wp(gucV2KM0!$OjByU->h!d^rSF*w<$N@3pHf#5tvfAbz{O)rW|V0
zy9s7~*89|$X!=5{wdcHS3+ia*`1@W)CKcE2Co|OvurQ6mYiV>I$07|bj`>BR*GS)3
z(@B%2q_}U#b9~^88B*^y*Q%c~FRP!}FzldQ0}9sVtam4q5oi3f^6s)SZDR>WJiQMd
z#${E|mK5hOPOeFkU)N{!z~eqB%2yQ+7}uwBIi?Tg_h3THh%qCVlyNf8O16My)O+)T
z$_}<g+Qp)LOeqb2mxez{2h-tZDwpCBKFlhgq;ezMfyY*3cS1|SN~Q%xF60A$Eg2Nq
zo*L5*(Q*G#-<<yy-^CmQWH?;tZTXBX4$sb<IbkH-`Y;DfeVB|%g`JKARv&hac^xU}
zbhdr(jZNQkW6OEt5!W$nw;rHveuxt@!CvgFQKQ!wK_e)AkYi5h%!x~EdxPmoXkRnb
zESM9`d^EN54g$myY@sM(C9zn>uwV?k_27XqX{YoqCXs)A;n+0uKyz{}KFSHvV}KO4
z4qRuHO3Wamlp2o^<5A9d$PLdlXVge<r;p(@GF}RRY6yU{rdg(}Hd|DcX=bH7%@zyO
zA9h15<TCSGNQ9~=!$E0smxIb!4shlL<=;@>AivK<8k;v;n;Fj!D7DzG+X8&+-u!k&
z@_!b~4E?H=`?Oa)xtw1SF8WvDyH>cE3-B?(yzB3|1%}P-7SA^VyYJGElICi6<Swco
z<(f;~ktP)QW<k3`u#VHgpudSGD{fydU1crs7#w2_-=Vrt^3*SuzQ=f#$5(Jnb?Hz5
z*d)@L3)A(Xkg|^6k^1<ywe)h)m7=Rf9~Ry02qid)_X`zbrC60%lGx^{_cc?&Q_tVi
z)kn9)HuZN{YX}WC5T?{Jr(j<MILA4-g_m!p@{uyzk1`85o%RYQj{mT<jO6b}#E~kM
z%h<V6?4nEiPU&8)tyJ4srhTq75=OfV1>+$BLQKr65TAd+e5;wyKL<HAM^HUt&Z2ra
zm*1+ojYb0Hxm|S`cai)b;MK_G9~w9A;%pl_pz`@?tOuVzpC88ao%|s@7np2|+}@ms
zxBxo$W~ki^idn080njCK49@5l7&kr)zhF*b_#=#)6sqso)x*s24XYLThg2_kVr+?E
z$>9oIaxyrC#0t3+@IE@zV_xanz`@xm=ghHZ{J^X$znc9W=}ezR_u1M(Nc9ev@gP4F
zgd&EzQj4@V%Elzq+w2b}Z%5r1EHr?T=lqn^Fdz@w%nPA%2c(#Rm>0nE3rypI#9L*i
z$z}k1X2aiTnZ__R!Qgc;Hr>Ol4K3pg&o_Z}*W|MO#xsPy_ZiP{@AW=O!%x%Pkz25p
za(l6EV6z4rdrJX(%PrU+k)Qtz|04+h#~QSbCEBx<>A(mTg-ItMnXQHOV`dM^Db5Vu
zNwUhUI{CyZv*M(0^<LZR6+vA}X7d}b`I#!Kk$$WlT9S+S;Qjevl5ER(vZl&h$sQ^m
zM$)qJR+ypCGN$xWuvZ^4HJ7}q2xF4WpOu*2v(Jtf6!NbzrHkr?=2BL*P=(d2q<d{t
za(uUcurQFi!d$5?GgY-ZQjKHTb)E1SBPj<W6*Tit>;3Ft$Uni`meqn3qFt65KiA?o
z8ndz^=trP@vrU!G$&jZoZZ(x_)9hJ|K?i4BOj&&gBhHwLdI4tnr~7A91NOAy`)3d3
z_bFbjwt`W~Y1I{%FpaZb%ymJ2_d3t@;CVSHEVX%Fd!1){8M1=^CZ^B*c#&zyH=Brk
za4{VQ<}5kmo!`yYBb8AC_P(VC*-qVg^79quCw}z#iu~r2F{$PIY+^CV1{k#gLJXi0
z4;x@Z0YDG5SFp@SQw1#B>^10r)x-P*=~7Nla>sIVsJ2mQTp3bBYeR&{57!PW!z&+F
zhu01h?4h$;(2LG4qTptmf2ya#T*)3Pdwk;5XDZA)@i3Cb=&fm%u_6!_6=G$(4RG18
zaK<pi5G%g8yljr3r4|EP1T<m;tVDPPq>c;M<LMClIJ!TE?%O~t5JB&-7(p*127vrN
z==bUh+2!m~30rIhVhPem-cMnT0E<oJ$Jnkp>&1{@32G~39hij~oxHaa<9INR3sC2E
z+qUbNEt8KM9I7yq#>{DWqiUV8gEJl^`W8-qfVrm%xW{3LM?;4(tl!IAzoX|t3>FFJ
zFdrXf28xNUbdLF=IBg;vH@2Qq^J@5^rMj~q&CAS|P_+*4L&f%zvjY5F^3<3YV9eV9
zS$KNzRIyBOQCWM4MUKeBIKCv0$SgVqhcdc>$;jU=HISz}j|X#4i`ck&jWe#?yab2X
z4}Fi5q(8vxTU=~r75dESz#;lxPv~FH>+p@TPcSi?O}(EQ3xT3M6{&>j8P8{MhFL}l
zWY<x|SctT4N@1~>MH~uL7t%-o^2U$}Vz`G8*eSjZEY?FZrHaZW8=T75Pyv9GpCX)-
zp8^uwjS%uvB&Ka&%{<uctJC4)Sh%<q6Ss3Nb|y=Uv&53akub!%I+Y+oe8k~NJ4MIU
z2JHZOf4CT8;$1}6J|NJX+7yxVIE9Ei*^Xt#p-GeRVDd}sn;EqOW$gi?4aiZE>Bhi5
z?51GK=gf5z*;PxKqQ#t<u4Qsv3xQSC05nP+B&ZI8RpaQ_sRNnugPBpLme-~ybE`Oc
z?ha0VyXlVe`VOK$$ie6T4DuhK5nf64q>1-!cth61t7u>)LJ38!1=%uo$bwB)P?M^M
z<u&#TRas$ec*{u<VOc}9ag>Z3LFsbTf`_ZDRM#?pSr2Rn!(U%2k_ZMlN{-*XG=fo%
za;&h5`GhDy_`(7EG&bPLhl7;)$&9tsU?e~@C(UZ4UK+oz4+~75>_$}F+7s3C3VQ~a
zc@fxjWA+^UON>0Nt@p#%jx-<=?jHa;1l<JcJ|LPpOp8;rB0&JOqW`u5Hg~7BSWlJ|
ziY5BY8C#Mu*lB(GJc|ORwN*>yzhVXdRm-ShwO8yKvumhjuT>k<EW3o59bX<_7ruxp
zn%pEO>_LoHnzr|4l1&se?F<tOGmK!isam#bWlNE*wY64lt)<jjYZc2{X<4dOt6GX`
ztzB#PtyR&&{#RN=!G2gP@xRux2>X|bwUStb*nNaBcXjq{NG#3{L^qC8!VTr`Q(R%!
zE+;m)65SB)XPF*zUbzx2Lm63@U6EpHsv%o||Cz~qD$LUe51GEIeOYEn3;PJ+*rdgE
zliDmx!D{b1d0*`v=e<Y*3D?(I4tKjP*(^B=CUAP}gOrt)pm1v(5!l$KCw+FN+;`C2
zHi61;5Fh#HfzjRrW_&yerMY(I)HCw*?efJf*mdm}1cwVr{-&#p+JNH55UyR(YZ$EQ
zLpC3$DCMLayo5@22$d4;7uEKe%SNUAY1`XX%JSPGl#1({GWQr9g8Y5Zfoh?~v6@>g
z$!DOW;P*1LU&<duUW6y}BIK7T+9m4e+39p45fybY1v+RPEpKi{%s5+ax|DSVhXVd5
z%h=V1d`;o#wJ@R4C7{W)#lXoZbRoA6*?G{vWH&9S0;});k~tr$fR&MFz-&f&Gg`%z
z<+;Ua$Uls{09Ib0=w-e`yub#W4TA8^^<|lR8gqiHt(liYxqPo8L@Q)IT8UtTXHJvb
z;f{IcwinGeT?G#}oKU9bHQzF(u@RdROxcIzN0P+Br75UiG?LP-8;K)o3g>XVU|HPJ
zG9>gnbu7tj`M@5tT=C`iDu^t&{682Ek$styJ<CmAT?#_IrdKUDM@}AEZjPRGEjOps
zSdPJMAGeo7DF?*>321-6JTgLG9iNEKpE$Ggj`=bPdhPVF%=mt!;M|aLu5SMrf^k7_
zMBoMd*f@*b6(@EdOCdK}9H_U+yhvYF8$!wgqvI{BVsxe#>2!gP@vu!~p+E-2814oe
z_XYau#3EgUQDdpyC(h)%RAChy)m8Il6(E*5eQZ46rFcLF*{j@sIGauhgs^9@2lr8P
zbYeHsKnTFZRZ<x*3k>&!jgBeVu_J(e)a30270*RDY&OS|!Lx@L*DEm)bj?aE`pwl`
zXY!R0FS~;e1h?eaA(}6|oC@mpwN*?{mVys5#A5A8cdhJ-#A~6qNA;#sPH!sX^u{88
zbM2geP3;_Z0jWU=#;6YW7-@(vB+g7JR~WzoI&xgS&>HXV@1?D=-VV!MPv}QJR^rhc
zlJ)<jq$r^frHMo;H8hk+Snb2ly)=>9Mo~{e<C2$ta7usa$&^K{(U(W?u4vq{=lOs9
z*M(rmPV0M`Mdp9<>a%~`7p`cu_B_wvvr=1h8Q0K}<1DG+F^fo&GXSz1iX>Siv27^z
z<Om}*WF>$wKQ%frH9s*rGGR^4qb~1y<k^vDAKBH^Y_&vDmr}||Xo`ZFp<UY)#cH^-
zW9Jw8=ckkq{?PyBul&i^{`4D9Jo)sWKlAMK-}<&Se_`s}#Q5kdFMoGrYJPs+3MGb8
zL)#KGq+oD-QmOg#yS{LC@_fUc?fpB3E!!1i`a3{|(xNhH+Y)w}M<)w8cj#RnK9~Ps
zy>s8@e|oX-Z4^>K^&ej>jMvZkk1SSZP`Ew(Y_9`z1zk1Doc}K6`n8?ov9%Q%^uVVT
z=In~_3y=UK&??Z2dXk3{vz;Kni@C9H88iMJ%A9SJX(5j;q3w^HHW6)}QKPA(0&RPp
zHn?3)r6Wd@zsjG&VBzpwkN<HLE{A{C<Nq@hBuoOv&f(|z0zdwj3k7x)akBO{EQiOF
zQAPiRGA9fEQS`FOFXAybvfx&-cPH#FvxxSUhvQ}2>3z7a#jWr{ncrygf_q~;-i|A<
zcDk{@8&_aG3CrazX7_0w-F>~5;1dU8Jv6?N;);y6_ILJLVx@O8Zq<6?@y&E|?9(`j
zWxjZiCHncz@$TNfj-EJ<=w@81_2UM#mv(j2n1w74uF*QWyJB=xUpuug(L8k|(G%~q
zVw*R2b$8OfcwcPOrmeWD>+0<4j%~6$EBOBISbyI=XzA@}r|tcTO<irVzAoJCdFqRR
zdrwzuS6@fF<#7qltzoQvORT%CgZ9N*H+5JvB_~p~+fubdDTR2XaERU+qKzSoD_Qc%
zPzWbu2~vI*san#+UNuYZ3bA)x<>swy7F#WsD8##Qk=sN22I7U=L##-#r*Ln`?hAV@
zx9nk1>~@!iLv0_a+p;U0O!R;KhhrZX&xtP1>*9Pao`Ffu3niZ8U7W!4UYD!bg`X6#
zkK_`Z0x$(Yl)I3Ab4gsG+v$T4;Qk9YGz$A2LF=zk$ZrOqkf#E_s*rPmIsXp=|A9gV
zz<)s@Yh>A)QF;KE5+2(zl0OzX4kL4%qBUu9<8VUYFjt{5KQNyE3v?vW6oe7Tt(j=R
z%btkh#l>G5*W)>u=Zw;#ZEAqs(gUX(z`nZNzC*Yad68Wrjnj1qHUtpKMJ*Y>k3cq^
zT^j0ez3$e7(l42HRB@w6aWClsm|V?hsuEgYsD!8j|AnGGau}^E^uU|;7+%M(mOs#U
z@CbNpBXyWYzDv!-Xd1T?fe~i7a@Z1{ce#X0_njgX9;ejtw9ZBAghZWtTb(#m=SkIh
zpR6kysVjQ9E-_kHK7z#<f!nj_T5-63Wqx0DfboNj=PdU(%#A__u7rgAv@AMVN;q_|
z>q7o1dFf5wXYtbiN$-=xDlGb-39xvx56XOmdeg0_jFC`t;8riR?nhDSW;YZ*A6(5;
zGuHw)(e^jr!}K!HVYa_Hr4<;L&;C~YO`M!9RN;Bzqrz_H&F>tCb`*!go}rv`Tz*$i
zmPFq@ZnLD6q{HR3z*Ur!f9}|WrrQd3@Apt(8b8}oFH{K|yLx*2sPh{Ls5Pc}gpK_@
z&QBTaUq<xW3h8$>vEOi99KBoRpSPvo{B_cgTZ)@ypU*#aljN@|NPg_U7k2^e=D5oa
zmOd)_JPW^UF&=c}Ur<)xD)`Gok|{Lb5`qB*3AJ@MLahZ`^nd1v{!bC(JBsm*--77J
Qq%`vCzhfEyk3`|$0q(`P`Tzg`

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/romgen.exe b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/romgen.exe
deleted file mode 100644
index ab2427f200e6fdee464c891048c2a26782e42724..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 578560
zcmeFaeS8!}@;|<tEU<)yi4p-7kEoFY1tcDNJOmAdB@qZlAc#Oj1R^RbhTRYzf{VKg
zOoqih#m7U16Fr|!y;BhpApy)1L=6EI1r;&sj>~BTgb+CLeOGtS&TLp7CO`lAy<VTZ
zV5g_Ms=B(my1Kf$XC`-i(2{7eSZw&;*l4k=#g+at+3%TuJScA0WnDYV+pRyobggy7
z$Cr+oe%GwjnML>CSv2|H)G3qiyYGHi>K)Tki`@66-gRH<kef!Q-h2PlX}#LEO-d7_
z^PCpT2&>)l(u=p>tkt&9A|<x5CR|{tYiY4m+btG{#d7<3C`~4aR`{RE(+Qk!D{_c`
z_Lth4-CQ}fHEWl}k}B|k%<!WZ4qs=tBq#A?vwo9XTRO!--1nQ^5+ue>^ViEYt;B`0
zzQ3T2#22+S+6azxyCv`TUQ;K#Cgb+R9h8T*PsQahU=4qnmfOpF6>-4Kc_^3(xcRt_
zBU$NxfXnPPZTh4_^p4|K<kz9R4%b~x;d+<%x?|QX!VI^;&pz})oIj5xv%J?`yj~_l
z$ddZXvLzNi(*k-~qs9;kE-UmA`i}K2Wr{xr=bFLlO{F}@mciAWN>8Bt-{t?K1oGt{
zya(*7-aMFNscPI;7!>y_4fmtH2l}i!@j|x6U+(H08j{9316Lb$VaUcta$~jkfCFjI
zd6|~*>Wx;5_kb;2y&w8B;3tbE;H(QdNzp9wkhJ7g7E88;@NN5Y7(On@cLbb=aj}PA
z{=jNkm4i%wxjQfXJnobWY(SBd!^>(d7H@4`xbjC({u`ALrhOGrLc+GnLJ3=1_y_PN
zZw?m&MDCmxz6cxz)(`{AB`eUh=NUa9C|St_K31!eh$vaTDQ|FWULNK3LY{h8V`HOy
zB(VO^M32d<6IxEfXuMzvh=;eHY-|h$-tHPxPPRalzZ6>z`KBmNyMo3H{F}v6K6}8x
z04_zt-zOXr6cIudB>3=K>ml5FtK@^RhJ+;lE4ZeYd$*)aDA;7P3|tOW*R2B|r_03y
zAH~J}UF4mCEszMfx>{V$ftOI;#|FAYKRkicb<ILAzlq8yGf-@4tX_-eHb$Nk?MdIG
z-i><$HW`TUB?9|qaOAs>0BmVg5ES_8MC4KZq8TE)FsNn;YOJli+VH1nxp!-$`sdg(
zR?}OetW9hglg$$-^Y3vdF_u-8#2kJfDiir7sQpFz%Q7?D5>7&YjzWW{QG41WhdTLx
z)RqHwWS>XbcBmA%w$x=q7)smvJ1`KcT<OT_P9#ErCK6W?>|X_mbx{(n0Y@l})m59<
z&gehL68UG4&9RaFe5{e~FkTh_2jX*GL4<}2LJ!0c;yhGsM!&4}4F;{B7>(Mx(Q8*&
ztd?+gI(}aHo-55%kO1x5Zv&HM^IBR0zO+mLQ48;xYO{Dt?KbJ*&mnfI&u0KG05Iik
zHRRnW@)`_z*NVIohP+GTz_k^5IS=Rz9h=MRm~P1XLF6ql<n0i7uNm?_5P7wRyq85@
z=OVq1$3)&uhP;I$&)AN8Mc#A++^r(-Nkg794sN>0t2V%0BJxfc@><8i{e2FXLFZXI
z&)<o>5r({vMP7*^?>&*X+K~4G^4`a&XjI2`fuVCcyyZ59^<)j8sNbJhi~jeeje#0?
z*RzYoJy-yCqAuTUAU77|<cVoELL4TlBeBta|7cZ_KUpl5zO)-alCIZ_>p;3P%E^i)
zu$-04W76zY$#KEWdEf?G*kZxu3^0WO5`m_G;ddEeO99x40a6W30XG5=Ogt=@SSGFk
zaUCtLOT|?Y*D`UH>B@MqD@+_G4dTcy(Zw+UX=;fkj;nBA#vAV|cikqE8AYx(T5^;-
z35-$2*2wi*<}|(B$;yclYvfNvx|2&+itV$tjxB}l1~#=_R76Qp5lc3$h-LDMSn`Y&
zO^H^N!YiU~&6vX2WXUY|rNmsOfw`-JBV=w>J41lrkHJpX(FSp}DF(FqVunUtWL1B_
zOrfFOp`#6Ucc<EX2DA!}Mm=iP1ggGhK%b$bk8t-Q^wkFRhvJ}v3@L&&a)-vky*iCt
zPUAxZjq5oLQkEzSQ5vl8zA!*11DX%Yii<54&w8c<7FP%2>~{lP*xk|+Nuk_ix8CzL
z$PM|@e5i}o2uONF5|o%)yOWS&itFl$6jNzeCxO#W$H_!8(njQykIwYm!G=;_(A0)f
zFVs#W-1Rn`D_<HF`O6n1i{t>#%Ys3~XdeTk-NC4`oG}VY%x2tujV)%7v;+v3#Jd-v
zdQKbuR*yaS|MkQ)JDV2QfwfF9Kvcp<-?Caz(n%SD|6|fR1G*CmI)9Dpm-ExEEJVST
zZ#xQ+-|fp8Y2Eg$NE-o$k-QQuosT5+k)&3F1bGNZx>z1d&O{O`4C)moH_7)QhoJ&;
zHUu~k5&U}V+qyEn_3d0q-g<{?y4n$CqAEe3suHy}sfv0-h2yFrkcTCBW1jRWytM^D
zP<>m+5MWe=KyFe6b*$>ePn6vxSH8DCX?~HnzKyFJcy>=eExXieA`o#3kW(4d1QWST
zfSk$^fzWz781SX_K^lD-K0X1e;7hw5xAcePL_L|KCx__Cae8uwNJcuKRdf>?;_E|n
z8u{(Q^(?pX28%^{w%k|l-VL}hfTOBkS`D-9OCxfTB0v%k1i65X)cFP#E-cdY(~d<d
zl$mfqi7@0bzCM^S8B?xyS|)D>xF8TioqhB=4Y}=*ixo|Zz{XG_T`je}X^kYj33D#_
z3ov&Z5Ul^Ul4`QSE%}bagNNXz0*C(8t^9tvcK;;qfn0)nZ+(K~dj(yC#Dh>&tE;nG
zgko>KP4Y?TRd2mr@|{FNoxrh(>N+AU?_5%`^Lu$WL`I!~3Q6GgRAD9vq5`T=-c+&Q
zzLpjsS8;%VEkQx2$eS)-&hP+7BpJ2ij2ek<$7)TcI+2s-OvK82F&>fs{Sib?{1HTs
z{}DtQ{s<z+{s<z}@#ogXqIb~o)YCA?Hmp6CV|axJzYdLjjp>mc#iUP1t1H4?NaJ7o
zAH3BsxMGpQ?AW)Cf|2pHkRn>@U!kR-qA5_TwGW<^#U1;a=wSud!-N<*3rx@vjg3pE
z^bev#t-b1uqf2ks>4pE{Yf<6bnhO6NtdG_4kSBWTY3ixz00t0sM8&>@brLv;-xDaX
zs4wHkAi<VvVO7t<F{sAx3gS)c(w1wlH$&+3ZLfM2ZRZk9fbk~9yMav*l79#+ZR8GN
z-MXN<$PfbuE!I-jRk6b7iVdiy`h5qgX<W+4qtu|@?$?5t8>m@=HcY+;chU+>Qj-6s
z1~9>;jdBt?%E@OD<y}zzKKQVxC5U~ak5*G3ZFvP&*_QSZrPuQGUP`~l(<dmslBc^A
zBfXrbX+{nQd3pfl&*$mkl%8pTnSr!e0%@c8E(82*N@oHF6Vp=gYH_isALU-jbJ=2w
z<*ugO6r#s{y&Pc`wo-l%<f9#y*+|#D%+l9Vx|XLiD7~Af8SlH0Zo=0f13ZIy6ENV5
z`Nfj25|#utOeCmfoYD$PKg83!DP7Fd`zU=kPuoh6zKznnGpPq6-9^u$1)2>LjY%W$
zNdOnlh)^_%dm>xGz;uFW%ZV?cw3Vlyr1bAEv8KOBX_cqnqx9E2&6@Qk(jd!RJ=ahp
zTYu8oB6C|!m^%R-%S$WH%T7QrdNR>AG_DDi!$c*ZQxSC-l^4-NL2Dr3H22wcIY5a^
z_)g@8z$p+yx?m1S_6KOBBS5H36!fHmONk#_+7L?r@K2VWMCmV)j<$Q0k>e|4+dY$@
z_i)TwN<W8mTp5HkzWoGkkU@4V#V}Ek0fTHBvN>oyjqC-a?E`2m4dK->f%es_6J%n9
zwHi1R=7OM|<4mRWi5FQz7f`wmX&{nZv@x<&gO3WJ6Cg;q8bmok{KzrM=hpHMQ~oEM
z`k&_^{m7}*hfw}2$UiOh5`tL5sk}<*5lBZnx*b}ym2$5`ZiHm=1KoAw@Coyg?#$Dy
z-N`)Nh4O7Y&E#f58m%&N-<x0rJcHT$0;`vWawOlye70gGn@|Gm5r(!;CF~mHgQM3d
z{WzudZdPAG*8zvR(z~w}ym8`vJ3+4C)To4cvfP2$K}8D<6&dxQ2kAk^sfCPaDiwCo
ziC)nP>r8+7oEACWt@WAS`d03XG)BU$#Ax`EYHJT1p}PVAby6e6v@j5}1__*C-(Ag`
z%Ea*&(&!)-`$7P~mUe(39y37vji<YmBEQs-KZj%L;RH@&3}{?Ius3s9W-y&Rok{uq
zkOqr=jU8ZsmnnS#hi4p~hqP{<f5mzkT|@I8{i&6>2Q|7E;&_q>*oXk1MH$!|e8Iw;
z1>Q$*6WG_!GhS#2vDMFOv8$g#V6oLtvbOp;M5~{hI5Dd8467ej@BgiSG|x>qT=CXn
z|F`-vdWYYUVh&jajpP=`t_3QfP{I#=h1Ne+=eYi1dia0qA2!fw$ev~W!^HpLb5Zfz
zFxioLe^AJN4K06iVSR+v`TzNnhc)-}XQR!HyX2W{m<*e@<YCp^k7{E5t1jHf{8tc@
z#*d`;ojJ&9S3iBRx&bVkRO+5F_!g&iB2^;$J3yN{kteBOFA6~K`~^s_<msy^y&UPN
zmvbg3atJ{`&M}{*^mwFW8z~&=s1un<(7JaK86_rc%wJ7b2`h<UKY#<`6n~QW5r<dk
zQ+XKaQ(S=P%F+E4+PRYmuH`siQ~EWYK1S)4NDHNw-r#;ETyh#RgQYjPZ$6B8q!>GB
zIUWSg3gATLL|#!k<&Nc4vnf4{rzcbTdY&$(^c|EoNTEHDd&5?RFGYdg4CdVm_epw=
z!n9uia0yYU`@5m;k;q+2xk;y^TLo~PF7t`w(|r<va5(silzi4_iS9$lWj^a$bm!tQ
zeBXrmwUm3C2J<!D<>3z42Pr*-r(1fE?#t8XQMw1xV2Xq+L=T<}tNBZhHa3D6;m4Li
zKDb*7Xp4(#y_9H#pB9|`h3>w>9ZJ{;`2^`GJoU~9f>_IQ^%eKMlv~5`mQecfrVwi=
z*TW&0gXZE8%;l4O6iAKM6Xh!pFic{b2zxNcW_(@8v3Wb9e5LYSov&{QFNxzFq4de8
zSlik!MEW454f@klj3VKNHyKIY2<2Cx=o&yq9m1w91#X2lKtOo}_XMwI0i_kB(KMYY
zCJHx)V4}E-r<W3R0n#k^V%Wv_@+O-Fx0$Gib{4kbR^GjE%L?32sM;)VHh{j4vPc5U
z(!l@DzzH$^zlLK&sW@E{zU5F0OVwt6GzB~2R`;a~OC59?(@l;%14)gvAZ?g^ZKfrh
z^HpP`1|EVFOpqueM>_m2mIqavgLE$Bma(IiQoFZd(Cl`NX^&+-l1=A%{8jG0>3ihe
z6K<Qt&XM3KOPw+^Wx&i%rQty5;)?GR62~PEm1m~-_qe{4+sngk@;ti$_cyw>2-x+J
z8g^C;b>O6zGS1-{Fxu57y+*Dc&nO22v#jz=N7-<zuS)WN3(nH3j%3=g?Jx~&ZXi}Y
z$6S&RqsG#|?fjM57Rl#l=_gtG36_4Fr5CbvHA_Fr(g#?&l%?&fvMugK>*%7)P4PEM
zzH5=M4C^H4)+sqD19Cb^fzHUe=Sv4#Hb~B)mPw(+4q!o^XH!b+sDa~p_>V|F6?saL
zLm8iJ9oM@bFqd5kao)4Tk(kFZYb4)AwEjw9*hMyZyj^XLj6$?G0qyl1o8-PEeb0b#
zsgn0s_!o_t-IUDEO3IVETyCxQ9B(Zx-bEs*39!4_y@B7kM%qvnnD|t6zptdlZvj`y
zbCf0daMEb7oJWLRY4TSbz8H8LJ;yJU7At^@Vpc`A6b7>*4+Yb!<gX&T{57r%$~t&|
z&hj)^rN=i(Yii`r)x|(aKcaewevwT9`{#p89O`PIoSYQ(cU;#|f2glh>UK)4rWEys
z`ZT4ehtwdYs2|itl%n2I=OZOJTa*g2Y7%7>(;2z3qvc9@Cs?}JJ77@ppOn!yxh`A_
z7_7mQlnHj6+WIk=UOwTrs?CK#C9yHhpYtfwS7lKOIuFO91_MXQ#6KL&a-SFJK)PJB
zAY~ZKa5=nvuX6nw`5?WV<-6Yo#+v}g<y929S4UPC21AQT5%A9vd7O_A?|~kQ+pgq0
zl!9a>%N7`tU{&VX`_&hxE5jWa8aI2l^kDkD5k9&_o{z(Ui5S9ier<Tx<Fqrb<kz}}
z$%#-QhT#5GNleVL$su{iq18&FwHh~-sB*MTBjj&%JFr46ew|S)4DR>|wY^Bcvkym}
zWz@r&kHI3+K8Pihg=H#TXmc4C2QjbS3Au6p<w_;FEXi~1KG)Uhje$Yc8Leku0}<Ff
zq)S5vRS%XslqCtJQ89cIj`D$D7#u7E5vL*{i%@!b<ol>R<jwNu>E-XCibna1gRdXm
zaig4D>zb)}Z2(3k=(+rTkqhOD%q3&m*kqQy<WV~cv-_3S7H5~GTt5)@$m0IG(wj*1
z6>l;w<Zm!rMLEuW5aN>jy^W7jgBrbLx^NhXj6_-f-pGsSLrq?sFD1v}={L!h#DKWz
zy4i|hQFgP{({P`wKlmC}?K#$Zc4lCvL&<ccR|Oohw4o+2Vpw&i+_Ee=FrJ28G0EWl
zz@SEKKQSs8cQ+?6Itg4BYtySDdo)>)T~l&w-M{R&WB!8yM|(NP0UKs>wea*ybItWO
zv|f<DF>iUc<vr>h`I|#8N>4ZsNsm<Y%{}Dq7?@=*8*cX;>*X3pgLky&Sek1jber4S
z-T_B(#disbIo#G(xh{oOx)|f5V~FHnk#DuhH{0c{6L@2bAsOwaFbE^&h<FNvo(0yC
z?$?!^-rkB1-FL`2y_LL_0ePKDcLp4zIB}Sc6sYkQPBb*gb}QHo4YFT=Dk85(+v%@C
zG%CkYcAl@sos?dFn~)6zNL6_orc1sjf#Gc^c7GQjnE(`Wmwc}itDk#+?(J!4J-Z_;
z7WArpS&~=njm{`O1VCv`x_r>nFv<N=06msp2VqNV=2+zhhOZF*$-qsl?=CtOKhFUa
zY0Wi^gyf$LrBw3k$RILJP)8vHeF&BqBp(Vr<WD#Qv$rbkWB7@@&SY119xP!tP@!jo
zIZtIt@+XlhQU;C11o@;og~LSUL?-zn&+$pF3p~f~b9dT+;zqe{QnZhb5NDD928Oft
z><g4Y5oKpxzy@916X=r_7>N<tvFxHi7Dj4uSaH^Qf4Le&J^d%S{}b87>sfeU1xaPI
zoWC6UkfJOhqlIbv0wsUBlHjc$RNOJ-)eKpX{11zTaS(*noc>t0C8)TUD`Rc)?(nPN
zFY>kGT(0EN?F!r~xyuzO*6#4bR93-<H5;&!@BL9Y@|$O^9Fl0eUw)Lvd!?5K_WcVR
zXhciC$pkPM0PSrv`N-!0GX(*=PGFjmz%-4(>v+aP5GXPdC=vt`#zr}qY$PyQBk)pw
zlz_`fz$FOWMCE5{!tZ0E1mbe=SzeSts*!_KNZ-4Oq}XmTOt2p_8<#6}NiWH_6RS9H
zeGkbu22B7|ZvvoxAXzIiP)1P>x^S@F+c#bE_odrWHgA96yb2uNMUw$3=nl3imW_$%
z&-d7tcqKD0L1tcpl7H1TWLc??M9cFhp}Wv?6Ecl*nZRpQ@`#NUh&ILG{CXS5DTu)-
zAijs%ynTB}{$~g!)8;L)TP1&x-+207FZq2)FMOZs=c=*xc8womqI(R%?&?@T!}gKx
zkq9GL4ADVx*8~Wy?^TljI-)$&Mn2e8NTxSN&Z9X16L)(UU|2AR{6*jvE1&$sa(<9x
zlxdTl%hQjr8EI+6Q5YOLz#WtVKcB#$d@B{4q3x*bMcns0S-M|g8m%ePQ|K?Di9L)0
z>mkHBn98{##p*%iDc%fk|H~!cGrcfp9f^_Y8>6F$-HZy<EjkP@07Ee-P93GY5v4n7
z^7gw<@(sHhaykj;`2gx;bf`N&J`NY_1b$*$)+0OGvb&8fyIZtu=g=sF@yFO40^p;(
z*hrvQ5J){6fl6nTK&p{IsvvMLm2=q^8QWW=bxwPoz%(O)X@bDIAyERej09$B1RS~y
z?l%&+Ul4dpZ-U!Mz^xIuRhL0rGhxvQOfeFeq7nEIhZuwq<2E4;XUyX2SJZg_atz&j
z3BqKW(fEtxPo&#CySINI$$u2(+-UUhLo2kgHQR?98o+jp7GCZ^`MTDyBv6`^Bft`6
zq(pT9SKkFGjJH@ldgP{P3+5SRI8Vs1AC>c7j4#7)M@9+UXC!c+Ah3waIf46(GQ3Zd
z;i23pfyqV!lLdjNshktI*GS-AjX<VOAZ{o8G$Kl1s*%7{jX;0^_)v(e$$fMJE+YY#
zM&PUAQ37*}O_(E^u#n1m6J{C-%+v^E^^X#W+k^xCq698C61bcj@l4I{z6{+TaITb{
zK?*@^kga%Th&lO6X^^~p`O}*u-v^gLcetZ3%&J_v8~~9&1>^YpL;JaxON$-`PFc!d
zS$o`Hp5EurT`D`$mOSQy+Y!(0X9bZJOxJBOOy{nYbA!MQw~o(r18H<TrY|`y&mo}v
zfjq}dEI-^3?XaoF9-k_Dd?}Ul9*^%MU8572Vk9s{5crZT3nwtc*yA%am3dG%J#l@c
zt~!A^Mgns*0^0{hn-JH{n?>bkYQlv&fw;qFQ%01)Y39h^4r`q%THU^T6eV_!R2!n8
z8?GcJpJ$6)Rv1@b7oN-pfaKc?jIs_~W4}19#>yFIRo7=?rtyPUMOlpRK0iqSXK<fy
z&<Vs>jUTRz5{Nr1Ev0haG4ZGNYjgr}RpU!t%JG}<AOY|u#N}W}w<rg(ZWEi<Xu|1u
z2-Dh7{3vgAf{!M@Gam*)cCQr1$+<-KQa<@^`Kv?Dm$2}FO`;%>?0k(J#4E6dfP1P~
zyy1?t*S|Og8S=r9b17gfa)Bq3Omi8z&m3ZQzB0^?1yqi=bZMfrIP1^A&s|#aolVa5
z1q#B}j{;e15wZFFJ&Ls)dO>k7k!P({oWVq=Pj)U*ay{}w;wUtj)<Tv>=ThZ-ESR5F
z3Ovz94L*qW_*qLh_s*B-(acH6Mx|EQUzF0NH_7!C`)o>nFyKnCMQq^lCZz)eau7=v
z?=Q*TMyvZ5MPV`t5G6<e3l4>)0k+YFiMkyK9!a!G{<dAv2<E2K6pvL!Uq51#zy79;
z8o0%X+~x)&si^0)c5ox$&&3Y1N#pFcn;GE^KO@9IgYeSRjKKsp1~WTj+W6zg;PaVL
z{hMyIZPPW|b|V3B1-{E@UGEZhrcO7{@m+$)b@Lq8z7Nz1#2>`p>*hJGTU4f-=hz{n
zHKDgoAg){Vg>IhXPY|WLd5$XsJYRNZGqR2BHy7e8qY!5aAwHnn_xMfds1qnO5-1b|
zHVlYz5Z?|>C4e*7p=YrJDJ)?u2T?!y;a^~fHsFVbQL$Zivo&Q2TZ8_SvW+gq@-vL1
zptNW<;Ll|o<t{%bABfc~B=Onh(T3b@ROq`kZJ0*@ToQ4$!L6%Pv5`QrM&RPJsM980
z8)8MN5ty#4Q<kwavqTfV&^b7bKAwdGJXNZ7X8h&eHl2gG`q)Q`5{Tb~{TD}t7*`*U
zQ#qel<LhI(P9W~QI7}xH%Ry8h8za!iUI#SA+wi$Cqo?&{Q~*f6WMKS}c67u0XRG%!
zR<8#;V1H1(@6((|8+UcsWRV*XCt}m}g~~9S(mL>f>OF}`eizF6ZIyhf5EGk!zfvoZ
zg~3}k))wQ2rDAFf<XD%CNwmod1*rJ$gj(}6Fk@Wxk9tOXJ?;v(h|168X?M~I#2tGZ
z^&nFG1!{77l!H5rL+1`Lbl%m?Sp3<jfB?=g`djJ*nt0k;ykN1~R4fslW_Ke~-33$2
zb((ROoc7Z!Ifu`SyW|{}f=)D=+NEO2*(JUY&(@q51L>UX?YXTvx!;l_77wTMTc$F<
zWl8%#R`2Cf=J^V*ak=a~#pjJ$h_8P_PmyDZ9a9$BTss`HbFSnLvwDz<86DYapy^&N
zyHBOb!qQ6#qx2<gNxml^go`;H^dhe#zF6ojNwP@(%^g9X>B+*mHp??)ZeBnZAV(2q
z%vicd_p4%;d>EmH-UW8xhS6(6h2{^2+UBsGhDm&o@{NQ^3y(Fz$CiAT5x~s=Xk!~>
zoV5mNlg`#bQN@qDO1_`U`Phvgpu3A|;3LOv)N;3A@q8-h1Y*aoD*s6RKzl0KpJ@eY
z451A8;6-*?pWID%Z;|0yc=CVLn8j~gNMZKB*m?vOB;eX2Rc3*6-sDt8Ndv4F)s+Jj
zAqoHX1BkF>KUOUH+k<RBh9~)3AuY2i)Dr|~bQtzr73DkrRJD)*c*Ena?z`y(;ybXP
z=!?j>bDjHatI&&e0&!QNo6fch{Z{vRVmaX2s?4>ONnUlb=h%g_|17%mID81&nMlnv
zc6KT`f0#e!+LTdtw&8{cXK^e+>?#B!r;j0d0d`I{h+<dgxONh}=IM**_%7QKEMY|#
z#&zJIp>nRf@dNC%1{MV3_Q20wqXgo|b|aTY3B;ZG9-;CxO`Uyp0<rc&$l%-5D1rEq
zRX+i6HJ)zl(&>Ug51l~#Ce)ChzzM`%hs~jK-h_LMCg>i`1a;8~#BD<5pP~ffH-WX0
za}aNr!oL?*_O#)t0FIg1(u|?hbuc4{>Z&gRjRgt%x8wHvMmr(_r0EN=l_vSBzSB&G
zQ1j)djqhS@^LId>lb)a3+D3Cbl0lZ3^tCx3Od1W?MFXN@>t&RCFE&;wgtTiPT;)X8
z3KlN$m%wC(*whCJQ0NF7t8)HQ3W@9hY{<Ei@&i1Q%tI`CZ0Ri)TXOqk_iNb84PV4!
zN;kv$BZMS7m(o7vQV@|h$+>R^oNw~kR?dGr<XlTsW%qh{hjPC6=Zm}z@KYUx_<&7z
zFQvI)G$A_61I}`R=H3!=ZY4A&-zVp9S8zUy<I#Mkj6}$0DRt4s46i!itQL5=yF$+0
z438Myt5^l2i+=l-+P8#4S4#d;+Kh%wBUlenGyMOcZ1+;^LVNq)Ao-4F;x^hw><Z!i
zJ4*on8i*k5HBxqa<T?bY5)truhGI~W_VR9kAZqp#NGiEYa2UuF7?&)6D_3gavRn^B
zX^9BY=OhDwrxhO6TgJL4&lbwGqb}h4aGazOF||=Pjg8`G<wMbqJ^l^&a4z-s1y5Bl
z*h>Bq>cel~b0IlQuBHH5E&^y)J0eVQ6y-0Jmhgvq#VAk#Fyoo}u_vHAKJ*WwZM582
z46-*d{9hs)Vkqpy3rfV$k3Vwf5C9*!akq6+bpr9Xbt>T!2m*1pb?&8dZhY=C4uZQh
z<I`Rz5Z8L`x;jdr&`6+ABQTc$&R~4D*O@Xtm07k_W`NYUfykw~;gPegC0Dbx<cP2T
zur+LqPrBfeXcObka#v6}7jpcKkdF|g6f%nIDiu*VClKFN>ZB8hJ5g`c!vgWQK&R<(
zg}8wUhfW~AxAz~c(?t{FPExm0Id4LIJ!!lkN+7PH(VG?pf!N4~rf8XMqXgnM;U`Cw
zK>Q{I2!Ly9thXm-`s;K8u^ezG9fSUP9GF&X@FVo{g|q49I;NMmQ&{hhiBZSsr3+J@
zXwX=r>oQg}=wd48eKN*4cE@NUtvD}AV2qK#7*4>S{9m;9h7-~D&N*9q|Hj&T0JF#+
z)L!F+?t`5b&57^MUP%DFgX50V9lAW?Z)?rg1sXSu@+X}@{0QVGJ&+U69Q!ZEp(GQY
zm~IRc>0lH0IC6sq7lkc5;QzRim23P*+)3WK_Lh?G5F#s3*TY}nS&{c?w<$yNRVQKc
zGm3M)ZrL-8+L6H)Kja_19mT(1^4-}K->KtYZ^XY|aR+6#C#U`s1Qg~MkrT6w?$~;l
zw%yqI>kHLqaVQOQ^Rg##<!7+rCLvAduzyk~5K4^B-$CbHcpt}&wY{yMhlxL9j@Jpq
zU2*i+tw8)W&%QQM4(>G$ntR2llM&hwYT6{M1%Gm|Ei?Y11lRPqVXax{Jl<>C0W}fU
zI^%v^7O>9A*ESK?60KX&I@-Dg#$I2bzJT5EBZ;Y!|Kpb68U2hs5O_!bZUJ4~bZS5;
z&aNzZ+q=Wpe@1Guk~^%5`z5H3|2E_?+WAx%qY!<rqs0mxB~2Y{WGIz3PP-B~4!>34
zY(Cos<#8>Xyx$!z8jp?8764!yHtb;Q=3TIN2k{d#P`1G36dhV>tf5p50hIQL*(d}_
zFQLY8_m)0s^)xC=Pa)3nRL)IweE-a%6No!)zO1WjPa|_ZwLnn#mz`+TCE(12;n9|W
zcKGh;<rts-9iT!>m?~UZ#7gpQK+@a)D#@4C3LV~3=9}xg!==cV*{D}vBxtC@Oq+s}
zpGW(hl)R5p7PCVEdITUCxhh!J!P79wl|Gco#5FL^HgmtD(xUN1wxRn$Z$sjPAD49)
z8mSJ9w92{5ae94{<O_iZ9KBwD+D2j{o*ouB%fX>VwCKZ@e~tr`!80wQzN^tVj)rs2
zaE|FMK%djtJEwS#P!ndW&lKmpgN!kca}G7C!BB0gx9e_tT<7NvoCp<)7=LceCjf4E
z;|5Ak($vQ_Id-k1uG*o=PqbzgKxtvsEz>w8y78bJKOFtrt(x5vI0FPu(-Xn_Anw!l
zdEk`T24>WvwXlvBbq(TfCJ?m|@sK$*)K|#sYhfDke!dR+@Aqe56sz3RL~qJ4Tu$3Q
zoLfOO(HQgrqdhpIBWZvpdiSNO>*$my8>;Gpu$C14@tLkKlZ*;CNmICay1tAycJpXK
z;4+;+e1+Re3Uvl=&Zci4#k%Wi@RVJJdv)#aZ)B#wV5Woa%k($4roZ|rT;S8qAic*x
zkIu)L*VD@RR0Y)Z=<!3Q&~&{WZyHhPk<~P!(A<CGun<LBijuu2t<pndF`T_8TS|+L
zBDm{4*$Qt#qXA9<IlIyyQ@+0sLCmF-{#R0}{#wa@DS-^Om02=+OTL@Xa~XJa!GX+m
zmtZ>#Q|Fc{%u=&I=JTo1O}$YJ{3Zc+wfJ{XGy;<E9Vc9)wgsT3l-qg`Oncje7*}CJ
zG;p+OdlRD9Bfw2Wn>^W|ehfg3Xrdt6GlpnS^^t0HF}7>qz-dpe$*wfpsXBoNDX*Z-
z9xpv?;4gnLInp6W6RUqBYQbA`?K#+0z)`UXximSHhhSDFu{sJ{N0Q%D583s`J$#X7
zsA6xNVr>T6d!L^b?bO-!J+i&&<z;LdR#zfCiQ{kjV@Rs|BP>}KB;-rJ1Z>`*U(}zD
zHa2c-2_?}VU-4&C85C|14yMyWW!6{>#AQ$(<uMB3%8ydKQ0)#{&1lyWtT{}eVPxLR
z4QH#vW)X|Hg@4`j$ehe;oUzwzjd$}J+nYudv*z@(cY2dqMOYunG@^^Q@f~>R=DK4t
zZ{tMMh@y=NrV*#{8ecZ&WJ7ai@;2UN8c|5~$WF7u8N+M5ZjWh1-o}qHADZiqvAo7v
z<`7wJ*o3;=^w_wM*Y^`<Epv?C#ap<{G-6L)V;|FqGkA^L%!vkia|f?+rfEbmHaeO{
z6r=Hj17@XK%-cBCG@|IoFwPa3>&HS~<HM#AQ@K>HHH|1(-Gxcq9IHa*=9xyE##z18
zG~!GyoUJ(SVUE=~yvF-XBf5Bv7c>{~GHlSAV^#FyR(KcY5bxov-ftRFD8L1#5#7AT
z_1HKy$Le(69e0>U6y4F<G@_8|8`xVl$EvV$V@)FpFXsfd^~}|HKNn7Ir71*)lwPC$
z*Yw;dX5+o4m-u3ZWj?5IAJ?1irfa;5i{{fa1r<(Rp<v1pK2EV|MB(FfHjOxkw{i1+
zQ@sdQ#awllIYd?)JdP}cI?SotJT6nexnnk9R491BG@`KLeas<hE$sEFsTOKz`#v;<
zMmoa<v)VM`y}awYn|5!7L_e)D%c?L^#ikKO=XW-ZC`|v!-DX)8>b=@DqF8PYH;pKa
z#&4!q#=`k~(lnyboXaZA3P+gYuFYL;Za2O76E5{E(}-fZd7)`UVT#L5uNs9ZE;NlO
zq}tXTqGmWM&Dk5>FqWA{oXQPHx@knQqWa<!QwpcGu&?R*x^vTbqIvZtZ8pUwBr3eO
zPd1rF6w2l{jVP4uV$+CX-rr<;><hy<-87;w{*r0LDZCfoDQ~7!Cz?i_%4<w8jW~;s
zj9%}XW|h~tYn@p{G2P5FjVN^WQqzdS6mP`~Da?6r#k`I8nMM>fUSJyWZeHX2Yt6Dc
zh4*9Fbd6%VS!NnhI4akgMik4iJ*L|zSoLl(D;zOTU1=IoEX1nK+g08jvrQw;;tFty
zX+)uNTTI(k;l<r;8c~?X^GqWOZ~R@;c2yh!zRfhE2*lV-BZ_J6RnvA=804GHBXZ5D
z-)L6JML#}k8gV+W(P<hni|guxrWHW+V^`CNLUXp8?nklWm}MGK8;_=06%*?g(>01V
z-fbFD8;_<Dg+cCT8c~GQQ)ox~bZ=ulHEP7v4H1>2ubV=Hw<;!pex?z{Fy8ksvo#8D
zb&+XAG3E3$jVNL`cfM_wRS}7AYZ_66e&2q}Y>mPp8*ds>EXS;-5ykrdpZ_t-s)!to
zG>s@m<Kcgstx>R=X?h7LVz_shu2D>KcGHN$lY8S$vuzYXu6)yoVjv%U#cYjYSUqJL
zQ7i&)FpVhusvloA#j0lG7Qfakv`d<YwzzqQI2mYkx)q0J@aj{X&&D~T=g?k$jtZw+
z>0M7tPxr7g9^xzl@VOjrWv3EPJ^jPn2)vtHdr2Q&Tg#4#<q!{}Y@YsjA#4WH#uvhd
zap0Wu7w^a@PF@eSt9IbfIqV|a#{2OE%6m9~ZozAA{q=~hM9)G0_##f56{8pjhQ>aR
z6H{Z%jabfnjXD|blQ`{`gyX^fq0lsM{dJP>0X&=t+6z#R_m>3kNt?9zMWh?k-kJG$
zwq;#1Kj^mSAE<g6@zR!OY@>`)WEfjLFs9WrVh+mAP;Y7iePax?I|kaVUP_g<=am&u
zWy#2B#x(vPbE_&${5#D##lQ%fj!ld8@SF{%+5{g%#BREnMjXW5=*kbw);Nisep6?d
zL)0wHI&)}fp_{wy3(O&+7aldYnE{NR<}kE2eS#C9CNxp+wMR@N3iIC2G@_WozBOlZ
z!Rk=1CyPuY3O(roL~msx9s#GvAL_89fd{l<+3==l+3BN`-*`vidH6yD-cq00FH}6G
z;zwJcPkNbMe5m0E_6>~|v+WGzuaP~0Tc7hBZy_x{f#<7O-Yt<33|0W=SJi)kJUv&P
zyDxyRD)2`+@@v(Xu^bX_L{!JVLDtmA-&d&KM7C9X@Z}&#tn126Ov5uUG5=bHQugS#
z`UH~Z`dCciUCikeBrf{6(sUn><|Ac>X~apqkK3C=#36%^&a}0OIjhO3ehje(uxg_(
zUa-DVyPI3Xp+?)8YCLuEh8q3mIzSuLYfLMAe=h#H<`BW5qj?-|H8=CKry(H0C#ui`
zqim|xTmS`pe!J4t7y!l`U|_goq*~N_FhwDa2c#|PB%WrEu#869=rpWBuI?)JjBx|R
z^I+-(9H*A?W>UO;lnv#6rAsC6a)=RQ8Q&L?{Ij=#Xz3F6`lQ8o<EAWs342PyJ?ONf
zn4b9T6Z33Uh@H$QW5vJ9!d*Vj9KBIZ@Wx-MhBr$LRWC$Ur>(%Ko=r)s-~0~$rXx2#
zrBA{5^o9j$9x3@qb1_SsjoI$G=GK{fl6}7iU(QOCH`9wS620|Zi`(K=8(Y#QRH?uJ
z9nUu6TOK}mpFxGa!cKcF)?f#otr^5#i<N489!7h!{(bad_?ezJYfAu}z$7DqN#cQ;
ze<eo=6dPa6RjhF^f&e&ycuz|E4oFb~Q;Y<rXap1j-~{46?0uC^;C>^4`!xdF+C>S(
zeIhQQZIpv<MgrYn0x)Yn@ifMa@%fWi@C2fG050~;(yTW&)A|IqV-or-2JI*bf<HGG
z`xuk<c*)ZQz@LMP%jb*K6`Vl)mq*;FKjk0yt(O1QIf#97PvanX77kMM$KvBZ#QLtz
zLEL8t8)3NOK0C-o7bCB$_2$NxSF!#Of85VbT%>aw|2+{O=-kdQ>h=tw+mm$;;y=0e
z5*C7IdU9<9m7nRM-(N|Uc$dfJ;0ayTV!K=o{*Rt#j(G&RmrgA1Sg*lqS#T5o4R>w=
z;M~M}y_D}lok0ATkJMv%DhR|=K))4Z;+*U?pG!19<73uV;}D#L7f%SYm1-Qasd#=$
z{h@)r9m8H|b$9fY7Q9RSJ21~SgM(*)M&nxN!F8h$Wmn^4gk6Om$MnldU94S=YSxv{
zw(pwfC$b3dJdLU2e7*1E4!kvb*To+T6*_^qFFTl~YhwJ@E!cGeaaH*>or73a){IXg
znPIMdB}Oroh|zenZaZS_K|GnCufMw??t66B;3XHL17ly-sB!Zfy`_e86Zh>AkLho*
zxznftcWMOs>IC9)uvc$R{K52vF3`9f%+q@${`)Kbq!Wnu&ME&J%^QvLfQGTa-#60D
z)zvU4@E$UKE^Rt6X)Yc9Xp>3tdR;4GpU2h2_#NIVA^IWi1HD&cgo}>6(%27Ia;+!~
znjc;2W%aPFXTg*64;!C<6OTJ8`G?gzkDGly6AN0gMd0AFJxkrjih(P(iQj;gM8BBB
zy^}9%M>hvoY@{5a9xz+4Xz!=Tnt>}eH;bBsD}sm}nu9Ag$KHc>m}{>#k6n8Xdex+F
zXYd7cJr;B3>Lk73eY>JLxZ38*IpH=L3#giliblh8ht58hnzXqqZ}SS%az@2sH|d(@
z^sk5$f7YCO#ddT?bLtg+{B3jU6?@Cx=HQB_nY*47Zj(MX*t;zUo1vTH5Jnxe!?a$D
zAW}=XdFFBXn0Tc*{Uo;IOU`LbG|_2sMDpHql64bYVP})i3Aaf<VMy?>HjTxOzny(7
zo{E1z>ubV)x2`$(+>{Xh*k<8RiPnGQ*XGpEx9zF^$C`y-9IgM_X5mj_=8Wp!^-FX3
z=bHqC?>YzkCb}a|NnC@-ndz}2{EE*GHv?DfrQ||lrt1}F$$mp?P2-AsZ)r}w;?&IX
z=F}_f*|W{T6?4bn=HQm_xw5u7Hdx5{z2?*_=E~m9!4-bVuKzZpf5pbn;^x#V=GiNo
zgDd=sPnyHCICK60aL?kLH!;43N%mEAaA8pUuJlB?Qr?Mg3EZo!W#4*kbWg!2Z)Zi?
zV!SAiv#c6-o-&+1VwR<h#=Dd8L3pe;Ey@OZcQw8|FE68nxBd#rcLPgwm3(CYpqD`V
zRv{tRh09dzAaI0>{d?Rmdbdmz-}zP+u{z4#2b6hsd<}xv5y<(`dn}>&x--<ZlU32x
zbs6fx``_xqT~AwwT)Kt6X4VEkzhfb*<ZqE5XFLloP_As~1l~i7=$HN|URxLb$wzEc
z-jSAgE%YKPSVUh}5OIWJ3IPpiY3qe$qx?7(R4yXn^is0${dPO{fa-5>C#g>p-UJ(N
z*&Du#56NGVOhEh;R)XLqFw9QuCSp4eV2yN6!?{IXWaL<3m1zsxaTHRb07C~`f0^;e
z+0fopWu<b89kxWdfzAHv7#uaxsQgaL<6(@-Jb9Vkn0Z?8`|kum(erk;sm5xwuS*W5
za$e0eV>Qt)aEB?>#`!EX641W9^)Qul0+WpdqF>;?Rwv*#641Vzu~%>C3?qT)=P4i3
zCFL>_&_3baT_=!gB#^2J=~FEf)4?{`NI?56Y_S&0X=y7m5{Q0YxU){+P9uRkg-U%0
z^${|-+(_VZC9BETZA!PxrElXyk>Pux8R_NTsz&;jDqfOa?wZN9G`%r^PqF8(k6bLi
zXVcEct6cIpX=!%9((+<w*_eUbdGv5^<)TDnL&ddMPlbl0*=SQwajvKLAm*=aeB1$u
z#zkrPWzz)?X63Jqybv=g^7U>kH8!DC6XJ2b7vk#cYP}a?^_2}Gbq%5fr)4!Tlzp1O
zz$Z3F$C<;>7TF(}L#rHW6YGhG%^_;_wW286>H6T*hM~SYStqC;A?9KZQ7j^gOe2aF
zL?_dT!bR9<PBdtvh#yQdjVO-1J4_>rGf@9Q^v#@9g-da(X+-fTQ6tu&=4uoU-;1UZ
z#Um&qOe4-?u7r9B%U%<#YAW8%bZ3Ymb-=VtOZoczQ658uzcUt_-l_6t`Ez+2T$~<w
z6CAyq_8+is^43T@@^^CByIUV4i-&jWxqnTsLZG<@yYw-E>HndenP_~`#~3G$P7)(v
z9Yvsdf^qv{g3<w=7WUf1%jP$s`JGO)z(}*eyCrqPZB?7)t;AoZ&D$5=6<Ocdz4@o9
zM!vBfcfW2RmGiy%*nMf%!a6MJV)uYPCwBOjMR#Khx~uigi}ZgAw6n#*jq6QKUm_;)
z_@q>$dI*m-u6?v|>O^zAYqXA>9qshqwrm<XCgzz<?a+Mn9#G!gTE)#i^;Hf>LRkQp
zS@OSwq+Ex6yc~SA(5rUz9!s9xsxd8)`b0KUWXZRmG={X>wI{t%Ox*M(L*SyP=|nPJ
z74|hm{Y~+ZAAOo_2O?{+>TwOJ6IYLJM)kn!cx#pOgpR*5r-_c=MOb_bJNB>xvnZ^p
zLR2L)F1%ZMuoc2aAaPfN$4-c8-*C9C^j^y>y5fD|-vg%1OFm6Ts^t5Lni8|6`JB%0
z>4yjBtjU)O<4a^CmQXP!;X_mzw`s!V@qco5H885brg~2UtuUD0s5X!uh$eP(*)y(`
z{O6(ZoC)<>Bw-)Y8{f31SE;)R_AJXoV`bV{n_`Yf4XqU_Z$@noqqcOsC>#v`*<8h%
zaC%ZZjbr0;d<v;QK5G!ZdNxkM3I!s&xwaD&AmpK6`cpi#mXe(@$5#0Xo!^TgRPDf|
z_zr^Wo|wM=85BfcH~9uaOa5lje}e``z1}s^fa;nj&|*J*5UcO8io1sD;sY&Kan<{&
z_hXcN)9GL%3n7DM^w7<yqB(lBpZdi_eOiBZFj=35mqd6`J@EGL;c6#3U+wCq@q@0#
zXI;s3&c#Q_TrMR@tK0NFfgC)#vQMsL>!TfmmtbMb*DFidDn6@UL2Yq%nXL;S#O~<&
z=yA3_8k1&^u8;Ef$th_|oO_MyBR)Q=%A9*6FBAqfbp)T<**kx^tH4{|(lySYBlt2D
zbz{7#8kYDLmp0_tip_OpT${tUtI_A$p}th0ndlEOup=*=1?TjW-VNvx)UWkP22L90
zIm!|;Mo7M`kbK4%$=3&Kyo_0ruN&PLx+Vs4sy)YAON+ij^E2*uCwb;t?~{C$xI?>d
z!gqjV=Pn4W8$Jtx$Wjl<cNGx5^*s@lVToRn?-`arQ5XrFcdzqq$zXE`Xw7s#8yK7*
zXF1A-CD4&o-&ibCJ;&~IeG!=F2n?!DKa$aU_Q&ZpN-MdbI*{@Rj=Bf>+#DENohi49
z9*+M>DX3Pm9G<?D+$#fPcVvQ`l9iHvWI$G@(!T}zWLEr`kT@$D*(v@bE>EZ>4kTFQ
zu{N~`;_z-tkViYvmIpf^vywc|3CL#TZj}5tA&tWG!4-vlep`nGwfx_ABfnDZjpD*!
z*<fo%k>vZBL^M<Ke~)n%B^$&|$d-m8i(Ij85XYXyu@9n*#=!92i3lyJ3G(pX$~7CO
z!aHE^N5)f6PdKZkM=JW}R!jbWbJT7KJAo4=ch@?+=bTvS%82PwMNDCLxZ*ODRjO1w
z##!zz<z^dwiq1z9B0jp{nlViBKR|re_i{s6Bs<BslKhq3;jgiVjQkyX5^cm=^fXi@
zipEoihlFr^JJFvAbU-Rd5a!?SVp6$?+QsTrMmZvji60p>83hj|=t+gylz>Q&t?R>)
zZzE(T<G=8XT%JKqy@uxu;Plr4RmtB)PrpI^szK~ZBIew#zgt>yS3`Wh1TePoPEDXJ
z({;hdyJIpWKe<gHQi^ZU%9UE<T$I@dg5JI^o!9=sbjBd@)0^kKN;#D()sESKX|a`Q
z@s}uv7E8XiRCF`c*wfHjT5P2|Xj}fS^qQvn46?EnDm|xKKJGc*x_Ez7sU?31t23e4
zjal6^-IfCXru<m_mV7Ia8ET1`AJg$=bmy$aorSf`>CUI|AyhKGYTcCtxI4V>PSzB%
z*|@um8qYdM=z9ef+tO4zri|0`G;#p;7S?cR|7XYyxN9RVp)-M*^b+r<Q9wg!A&BeR
zFRF4AEqtQSRj7=1c=|it9}UJ3RNS@dQV;_6YGTPa+Ojxv_fkEG=#F-X7I{jnPIoVF
zIT?^sTGS3m>JBs?uVnuVXL~=bIl*Wm=khQX*<j=9Q#jmNC^$?J9Dd3;bk?d1iC(!n
z7Z*KN5C2~&>7is|6y4}bLdZ{ZadNEka7S65)zjc~cWufhKB-HBzY}#u5sEFMWyIw`
zPs2FZXivk9uEBu28a)bTSLw_O0$nv`7a{0hb{^_-U61y88b-J`0PkIVaWqm%V=xz;
z7Fmxz8U(Iz|2skjynT{C8)ekS$O^4|UJu1tt1+gxbt2lD<0!+oCP!qnE4~zDhT;gV
zK5Xhqb70}MeFSMuIgYJ+Fyab>o;g;R<fAn#)F11YX{0^OcJM*xuB1f-J^6sr=SUZf
zN^m^`kNkt|o1m|5!)fNiAhm~44ABVY=E;fA+fYSpy5Y<O@lh2tv22i4t_<YX%AZCY
zg~33H4KgT8kSocAcZCJa7%Ta%q3dwTKN7r<SiD)iTdu=*`!r={E7*Tc1&6H=k9a@*
zNaRVfmlZJKB-y`!EoF4dfYF^wvjUD$72hQ!4o?Q16nHr)A<zV&LALo2N@$QB6E11H
zW<zfws+FiP5#y{DLcltsD)J52d!|d6ode*{(=b)?6(aE-`VPZJ&fOj!OG4Y^FNf8_
zsXffY*SorS>oZ*!p*VkQcr)x(`Vkc8Zv_NCMGA25F)Y+R08h%SlmW9kNr6|84%mt-
z_9Y}{B@dNnr9kT(A<GTKW{zFP$Ca32K*iKeFHIqK)z+XCqz{8xkWjKx2V|v5fd?r)
zy0hHpA()(0ww%B|%C2-`_K;i|^zCtt31n4gv@V_&$a*g0!s6RJ$Fp3wdX5iqjqx1M
zcirSUKEgH3b9^+PTRq2blzg9|TF-GfDnGCUx|x=jp5wXh*0kh)3c2_O)UFV&vAvJ}
z!LH3ycu>IK=o-kSO$|Y2?Hy=C2=%ybR>qP=a&-XAd&<z%0YlSD|E-MdEN3jtl!vC4
zU8LratV59+p%tyy;j5k&^#>UC!eBHHA7HeoJ6IkF0_%KWQ8~M5ftw&_pf0=}b*q@c
z*?O7Q&ERJ>%oKAp)bYr`-j6)eQ8o%zWRh#Jr{O-y{|&XRT>T45ahU-z%hl>My5PI1
zyX5O>?VW(?(G<yl47Q3mBLjN}nXj5bpw~FGn=&#by?nq(botLfy{E#FI5ZhW=x@nK
zYt@j2O(J<VbsO%u`9hB;&?H<zY9z^vP>I?WM5Cp*!y2(N-x0I|g8)^GMin7I-m}R8
zm15%nRlI{7-c6xQ+r2avGVSOci@E{@fsu~%ayfU4?0!4a@t*P|X+uq5NOHB}-lB9M
zfwY4>0>j8PE&fh%zpadPc>3Xir=P$mMv8h7B%|A`5wKaAj<RG=Ly_w$Ps3POS5L!m
z*QE@9SaDnEW4(9F2<DOor8QNE(5z?nii~g@=uH5hyn=_y@Fx&{A@JQ-&^*cv13tSN
zV;Gj-4hhjWXe%SnLtt3z@cHg>rL-1`^*25~N*B}E$lzmRE?|O!VC!}G>YOF=FZ~{$
zxwAx`0jXllSn!^lwL$7)Cy=zU_E$<r>7gR^&&VN)Ks!Xe8FfN01vO;;GD*;iycIPr
zKG@&?MmyX4^H5JiZ)x!!<Vb638q*#NKbdV2G|4{eG%w>cpVnxq6ZP8NF_5Voa%L3r
z8bFq1S_662@R5q8j7hFG-teG|3#G+t;ixma{!a~9IA{LhAc-c-!+9xgjf9(Wkp`&l
zC7z))wnqXs|8~47fV5f$L2j3&rN2PAR}orzBjUH#tlo`T4)qYJ9`i7;{3y$TGY22;
z1Rz7sT>wQa7uHHzJe)CxHOV(Yu_hUFbIgiF#X!v6MIRjV!%n7G2|=w(<Bgwnn-INv
zE!Y&&7q!hfrM6n+fE~0Q!uW>tk*|Z|)JbbG$wzZACcfR_;~1InVX^SQS8b`!8wyy(
z(2n(Jsp!ei0HyaN+y#QH=8$lC9?>CRje*3c&I$6xDCBfN8XAKYMQ^Z9GW7Q+i8acl
zwVwW1RowtUQeYqGX$o9S>8JvO?z4#R$8_#MR*`x=^ab-a_pLIm8K~wzsKy)aO<i*j
zx>Vj;$i_}tviIlSq*MpRWZWarXB1xyG9z@vb+Npu`!?4FA#evYd}@2FovnnzxJ7ht
zCwfN+=}lNOEOnW$5I}GOrs<Q&0P+>~qDJx+4&y3jfKz>ig%g2JKJUw9OvvHLC~{W_
za6XAdJ~hbhR>?O5^gPFgNxt#aq}}0O!~rc({SIV6YiZR6`%Y&Ch)MMda2tdNwT$Lq
zAlx{a5ag^L>Te`(6wJaE1-+@Df(oWmMuqSPKPKbCJg%<1XSYv4Mo6V+bAa_aigh&^
z#6e!>An&6L%MvWOrNDk@{5|!K#Cgf!Dh2kgZK&1dfDUEbwm*x&cQ(EkO5;skWI*~?
zQ>5Kdq}4!*RB6<GO#$DC0!}Bul^WoLrhtp0fI$GNh`mHvzPbr4!VoBp!p|r8A;^Ig
z%5k(vm%;!ph3ChUplIm*hx^oJ2|nCBj~nXZ4D`|yNUO_PDfxv`U?$bsKw=_Y#K;J>
z>IQ0MLXjUYhv!@<XWI*@$A<wJm0tyXIon1RWg{6F?%=8fBQ+fmYzWMj6l*3{lA7)x
zVj#Y9myNM9OIj`{C#fw!gQ>d*$TU?qGR}U1RlVn+10fUQjGVf?$O*OV5B6Y(;K7yI
zL(Xd4(b#q;N7WXYusoWPOaoB_Zc2B-PJU}JS=vJP)@oYj{wN>!mR4I_2}i#|NQP`2
zW66IPsuV+y&eU_g><;P>L!Vno-0D!|^WH9fz^HJN?@4HEwD;Ch?~$Vt$QV`eQ-TmU
znV*lqEeC^8)gvU)yaZYy<Rrk}Q&ZGA(9u&e2@=-f8Zj>LH548=+J+H|7O3yhNZlQ-
zI!J6{vZnre3P*~)eLG10;ow?TaEDO<A|9euqkh6K15h1zrP8bTN}pm_vy82C-5F{H
zb7zrnB0HkK3=Gtj4sO%glKTg$oQ>iuxU^c1BR15Jk&pTwB|&64!qpSN#>==Ntx%sq
zVYHd*A_hv-hl4r+z|CpBj(N3zCP*IZ7;II`xCkC4Q{9r+{~TH}z`e!Q!rS)>w@X3H
zo=2<x%(*GKg>f^7+IvKOh-#`)8$d>M_U#drS29xmUy!Zd4%)<UmkAIV#S7r((I_Lf
zV7erE7p$GS5;?FeYC7pe{ythq(gPsc<dQ_`;hp6axbawtz(*BvP_g$MavlbI*vNI1
zSuj)vWjI{}1Mb6-o<V)Ai|EC>Fb&L-ccy`LzOTmBnU>rgc}PM2ok9xkDhdLy4PwQ4
z7*_wFG83DF?g+lN>g|8I`+G$FymOOVyT3xB`{>?qfT{Y(N4n3NfpskTtf1dFFwQDZ
zB6q|Ghk}$gFfIWZOLF&n8j2;qAE;%{{d@vk^eFBso!=KnS_g4Ka=+#MKFCWi56WM4
z-z4v-P`g-n>^NqvkP&g(R<Yj}_|NVCfL(rse#?@U<kt4h{oZ{!9PGaN`z7C}!0n&E
z|G|qC=dR3tyWQ)kX*_;gmj8X<{MrRSDh0bDKfo{XG)$5FmxDh~>HcC^4bI6Fbw0#h
z)`s~~D)O`t2lu58ASW=}p=86mY2w?oj7E4>#3CTZlJqL&mXravz<d@{7urVADm5E+
z>K3+Y!CJJDoUU7O4Ox1Eva}(8Kb!zswdUAWT3?|KjRtw1r_kuaaPbZli#*e&wbWm;
zz$e#-kAg5J&g>p4^XcouPh($H*ARRK(*mf+Fe9_gzCe~$&UTayx1z<&nzROOsQcBp
zEXn^~oeIsR{^4Gr9+&SdVl2WX&I{x{=V`dGI4zL(fv3SLEn>0y5iVB-KCKr)ojl0V
znJr*o3*Mta2}i-Ddi(Zp*FxtML=y(vz2&Xstlp8G!N4r?B){dpYk6QyUiBa>sH}l;
z%p$AuaqJYoiiX&!x#U1lK!=kL;xq$%4NyQBB?I%$HZ)A@Q0Bo)i-qBD2dgi9)p&KV
zwUFe`ge=H4>5D6Pe~gUPCR9l_GYxr&X<=pOa><{o9dU~g4plq@yUD0H!zK9}$=Mn0
zK!lZ|OMZ%}2L`bng_{$wVwQZbV;-Vav+oNk8tzz9O^pxCtd<X90+JRFLHRv3SYd+8
zglfeam}!;Mu^@@;<!u!WwE|3QDBlxVoJcd=9;Kc91^m&JzY~Rtnk@NhMwJ_|^-e08
z0p^eH!OD1#v}7c){JF}`5GbR2K-z8Si|?-4-jf|%MHyLGsGwIfhDiR)07><y^T0>O
zHE0DD^_KjtP{cOjdDKaBd+N~nr-XzlqE9AqC$6EE2<BVl1?20hTabbMfx&k8V`bKe
zPe^VM=0C2n-2?;IxMpSi#WkJ2^tlW;aVn;G{wWoce@PXO$2HWlm0t01WMCv5#bqO;
zXi=|&d^S=jOzokiBG0m-$P-%k&XD}=fe;O|WzgKm+^!R}co6<@9nxYlxdqw;MOyMT
z6|;Dp6rhN3tan34-$E^~7t9T{Ym>$c3@aMGdJ?y%$cH@Z^gU`v>e1t{VdPHvX8>|A
zv4BotyHHYK0<!L@BcBTS%%{2$IiZ%BR4e&CJYseYG9yZQO{7BGqw9gtD&_&Z=U6uS
z573@t2!3rNv^qI|Z+Pm@sChGm^!B>uK$BV?8EUt><|80dX2ncah?(pT`75Qrw-E=W
zCt%DJIlRAK<ZVol7X1z)=`|TxVf-2S=q6^nu}Z58@5eMsBan<aITOd$F=wJK{2n&M
zDC5g@ENod9eu*+RQ$&`Z3t>k=19?AUx2gCLj)24dWZ4xsqZc7(cDo?F9_<e2t+VWr
zEzrM_y}cDF^2pv4Vj1I_>1oJzN$GoZqGU&~Do6Az&x#4LHjtBm5SFK56ylBGLwfiU
z{CXM&xwm0x*M-Z`8@g4-mK8<*8b=bN>L_RzCS7VR1&h@G;m1gO3AtZG9p0a_JPm)5
z7SlAtLm#g_l}+ylpx7Cxt-?uvrh4oI34(A$jM0VT)4x}-gT?n$3X-6G{TtIhnEy1x
z=U;!_`yZ?7Wo4k14_Z3A6aqtL9%uJ?0O9T$s?NDj8Oowiuw{qQF`6|R%wiIQA%egH
z2SC!RNL~(^!XG1sRntysa$r2S?Mi+vlqBism#|4oo+6%ya-9tzjSwfb?L#=U-l4r)
zz>mW2If4gx(4JWO02>I9AZ-B^2G<qy%<ZGOrsN`*2|o)XLT?QM;e`4SNBs<C>!$Op
zM+IVvhL{wCh&R3v;*A`ULV}EXfx!Ak%NT)-^gX1jC0bSmjjU+23%e6U$ifMY22jwe
zwt%uBa}S(N9kMlt{Cos!W_Lh()g%u1pBTU-4)`w)XaOK-JsbmqXXL5YG7dua2X`}K
zK=A4k0=bietm7az#(?0>J_Is^gFFF{sH$oP`XsNt;74Oiunj_Z4vseoc!*jekcDi-
zKqdc5qO<^`2{R;=sog2cbRKfxYqi3>b{aims~Z0;Amlw}m6nY}LIK5A>3eA9OQ%A!
zWoTnTE#fo&uW^e5@U=LV-o>{^@}&Ygy~cAq&D~!87np*+mf1SOTqR|sxmpe$kY79h
zSLL>p0k^@?BQNrv%@mu?l5b;P9vMHHR5szt1ITiTP0q8Ue(M*gv^#VhC+DhA>@BUe
zNXwo_O0I}_A(Cr<Fv_Vt6(IgUjP>|mX)#izeo4Z~OJvq2Q4=$5#Gs5q_hs4E4D3ie
z4P1&nDRfPf{3C#^j7=FZwo~a$3Um*JS2`B_y6y;B`T<7Tuty$e1CQQN0+{sPTbrQf
zgPe7&0}}`ZP;^cFE9Ywj=j%C|=CDE3m*-xGT<E($70AH+9Hri&jszqrI{a2Im2B2q
zSF@8y+InK)fu&^0H_MOF0ZchCAHQtn|1z>S=FxjrnOE@5p%>kklx5j7dP%<9P(%$J
zOV>2XM|)v~!I0kvTySF9fNC1$-{f!8%lQKi1#bszZDi-#kaIm7bOq%BTWi_5J>=X<
z@N({M5k(C-sZ(LU_VG(CU9d?OuvrnTr2wRNUtM_FI4H)Lw2Qs_>jH!RL^<;*X9#lk
zVd~q0oqz8K#EccsHGwzDTMx{D^X;%L48}Go&T?AJNq%ysNM9D>8uHT~GqD$P2Jwsa
z(Q+hLQZnRR%`b1#Me#FHIiFORwB+0sA?Hg}5MU(2Q}WQ?&S0gl1s$@$!%Hh<oIH~8
zWJbVGIq0#*{3o$kDt*a<m`h;VVdkHwM^iXAlGQq62o4P*BKiU_JoAz;R{o9@avq~7
z4b4SN-YT8S3u3!_yyPcK%X<Nhwx|?c$N1r*NR$>I$GvxR8@Zrd>l^u#qo0q&exJW;
zL8-h0y+L^XJ+7H>IcJ2(`?AR6ZE}%4y@pdskRIFQ-IM`Q3Y83R!u~KMT2P)|{vPZ0
zZ>h@zL)u_g5>mb#`RZe+9PLU(5Whou4GG^t*$X(2*vDK!Ya*azSu@7FzxHlU0H3Ib
z&6Z(1q9UT-)GVOrJ`nBSc>0cTwKZ(6bDw~sHT=xQNwmXrY`psliVR?~*d1Pb1YHDx
zB+oIY`$HDT5MBy9Bl9(E0mkQR-oBUP><h3JtZLe^W$Ht?TX!uZh#kfcknmNxybx$8
zl2jNZ3pWexqPS_9HN)xtMXvAu8=YgDmoi`;;xz%sgM807Tb@UIz8(0+&jh~pD?ebv
zUYz`ZU3Or01)o!g>U>K63rS*h?kI@OS1`2hI#jPxeYBDrmQ1S&;l&_ypwiAg`X91=
zGaA8x7$o2CkRTir3(AG3z&2$7tI0J(aoQEPgC<Y%1)&aYl!9ceP<#!z4LNt?7neAL
zHITb|U47q7OPB&jgim9O`xfI_Un&K=p<(kVcvyy_7`3@kaV8J2&*~>nOtWEkBAojz
z6tHtzxZoRHv4Kgav|20qDMB^jTJms15DrP?Met8s8u`1zJpr%a7?3krPL8m1_|DxJ
zb>Rz;kHDjojBn>*t{g@R!hp4m{97qa#?y=+vHg17uj1AH4(Jd~<OCB?a;ek4V|YA|
z*;EDt5VE=yL87yb-UD_LVm^fEwy!1Ns?CVOyACV4$zczf=6dUe<=%ZKk<IK4i8LQu
zn?Dq6mX8G1Q&f!l!+W5U;v^!MEBVP}M97$cGPUO!>`t&Vl~tP@mVm1(w)GQTyQ4YG
z#^dZ_igLkA2XpXDn8VvYu{hm3aOS=oOM)vY)Pf~Y4}0>n1x7!Zl6=o1hY?W<P7vi#
zi>*KBSjaYD)R(`IZ3!nsklq6bH$UGOq=Z(0w~tXsjD^3Za{KdZfk#I!!^mGnpj7w~
z3ZH)oB`gPEq$X=YU1>}35bzCPm{K*aYdMcpw~-_CERm&bh(r^|vKAN)6v+v-Aawc*
zwIGu8M>S7oY}rCBh!y%{G<g+tE86>hiseSj!sGNS`Dlk!Nrb{AG*){z+jzG7zeaB2
zRTp_Wh(Gk-=oKr*$(vv?QZ0GUtQhx9diBec#vTAFOfQ%IL9Ks6<3;+%kxHwpmACB(
zaA+;`*US;=grjh3JQl6UMz@wIq@CR+Xr;*u_oLLN-KHL?h(cz1en@rqB58Z1e+;Bc
z@g>w2-1%!tE@g<BuB3&G0ZW3#GNE8IzwrP#QYi|6fp8Jm^G<R>y>iJ4XqfCi5pX-u
zGj`gi)_TahITHh#9m9GNy7S~$5H$4Hg*mZv8fkR+-aQseI1l+u-*fy`a=~G^B<^}V
z`BQpA{?y%8DLAaS>lNG_DA*iuZlyXpqYgG8U?Cm`1@8e26IZd~-0Q8kxw_Nomb8Gg
z79b8pC<!A|U?|S5qz-p5q-1$MIB{WMflh=m#|SJX0*j*rhz=BO7u6{6FXQ;?B&Zx(
z$PO11Qy3+ksHNXPbpmhGmYKykp8KxKqmh6nqJgC+z;kT#)@DYsEj{VSTi+_wf`B1z
z%Yv`G^=;m#>;>JFfpmqr`jc|)5K0|!rzmZ6C{^W7dVd5GL9z!*dw-34BA#uA{m931
zn})Z)EvR`nI~E=%8nb*GES5~10L0VQ(wfnBYn}BsZ$q-u&o#x{kjkA|Z-d?C7BdB`
zj}7hfQ2S_w!Kp~z{*VEq6e!&XV(;0&v9(S~PHgYpjPDTalN-WaAPx>*^tGA<_`;y{
zZZdSd<o@p40vY|W)Ab${&JxJ44IcvO$hA0gfiQQ;plC74fr@ugafiZSVqe^K|CH4R
z^f2vRN1G-+)D@MeE2-LTG}(3EW^Iu3Ya?rMi+k<1jJgzU8bNKM6Pq-0`5(9AtLzs3
zSdOb>V>P=8V7|??$rn%oM5|V94y*xdq`$OpkgQy?y<(`vd%V%r6O&#0K%ZymzA)I>
z!TXEN8?m~NpuV~zm?mH81dg{PPq+<gjk$VHBthN`Pe@7e69#&(F7g2ijQV3&+TISG
zfSpXJ+8k;@X_8A-WFd{mJ>M5#LecqW{H!V=gmQPQz_fa*3bijmPIw6>a^;ejkR)rq
z$8{BZhCO^UvXLQIhHpX&cn(awh<?$e+*qwlu;YyYpJ_Bka9}|>j=t0U1;uj>E;<kM
zle<NjrbuQ#t2T$nBh9!2g!|`E3u2W1H0qxtstHyipE7+G?QnJEfYfY3h|6EYdP!jI
zj<nT8!LE=G&4-MPQh<ra4Zo4BzUV&<e<tu(X<{jNbySl3edV@ChS1g3MXpdX3HLV*
z{6=1#AVtrV+|1_Z7e3P)a)n^&D=NN#Xh-(4`9b3c1Y0mx$Zpd59@MFU;Ym0bDQ{j2
zK{cX__QH0GdgVk&R?f18D*(aRm04dRcm|Pa%)N#}ILDCTDyr`mQi#s-M;UpNPX&27
zcdxW&E1s(GekXa4Ig0J!&@K$JVhavCy@nAHRN7$LgR*s0-21#g&h(y4mVDcRXx-r}
zpOc`pCR>h^z0rLDg11LL2?~RO1Cf<-{%-jG?X#pc4LDG>@4=n>TH^$1MJtSLRjyO=
zcYBX@nJsyL!o;(Inz{4G)`$+~)<%|q4<nr~a9@^~C2#WXe{kpi*7=M`dC37pJSm*c
zmd(;eFp!{PE!+tE!qV4M+PgW?`~3;lnkFnG4wt`|MVBF;$`<R<H@3<a8~Eh|e%Z(`
zoA_ljzf|x`IlqK(aa6Y0$}d&?vW;Ip;+O6G@*ys$VGCWLdb;1;Ss8Zw(FzC`lJLx(
zX~F(JTs&nwbG@@E*-5#^Q!)buBPg&r7b#yhQskQ7Ksf^$_maOSZe;g9`7c2Qv4tX=
zr{rEBb!13L`T7f_YZwx1B)+5q^UILvRTxEfPsx42`5u{`xk&kX37oDBhsj6sZ_#la
zN|D1;azAk1U^qzmE)zHxF&rjE$sg2ll9i%lPYJbj9>YP(*FoU4V>nE@l7FI(lcE%*
zcuF1sPBz0q%9kW?5*QBa7|GvF$LXXLb@G%H0jE8~LCSX$DH7Zf${EPI7Ke2(=7bD7
zD@C0>C9{C@EiyfGk@6iBI6pHSrU#P0T*paOic&o#F5tY%aFFu-C~&@EIIPztKMT81
z2Pxyyl%h0Gi5obx84gmuuLMpF!(j>|`N!$?bW@7Dc}j|blf`h5@_iz3Dj7~CX_w?D
z8zS1%Ln-RvDVYr%iQypS+az$-F&t81;M9>_;Jo!#ih6rWN`M1r2Qom)w?^Qw{j-6j
z@4#8F<MdIA`gls_0Oy|!2Pxkx0_PvB9vU3LS)$|gRf_t0O6FSJvpsX?0-oTgZ=PoG
zG>UBQiGrsLr6|KwGSA{3?wLCeu+IwE#~CaQHJiJ)fX!5jGCd{pE$%L!x$^-_^oZ^w
z43@?tc0VqJ(uAwApG~XM?TGRb#1>rpeIxnS<0`FbOXEuZ_RwneH7W<(ZUI*<;I?u&
z8cGaqt$?c)aC-&ZE)GY-hrv-jM2~i-sNS%E+sEN($S^pnhu~;Oi{K6mxC0!Hh6#hC
zdI-)APln)V@k;He=WsMM7#!6@a47=LA>eGdqP;X67#!6@aH#^WlYmR+a5MxM9MwZ`
zJp^2ufa}cRNbMOM)kAQ71zc|d*NwxGsxvsMhv0??xC{Z;hr^M2GdQY;;PM1qj)2SL
zaHP@<j_M(}i2`nnfE&T#NR1gB)kAP}W|8D~yMP<V;Yf8E9MwZ`GX&gJ0Y~&9KT=r+
zNAwA9rhp^5)E`6_aHOsbj`4rQ)gE)a)bAS?yz#cAo>X=ub4sSWy^@0nkLyATbnz{B
zJU0Q$>G~-^1@529+L8`nvN$q$N~WtN%^&WOo?{qisi;b66Uhn&#wV-)K8Bm|Ii7*S
zuqL8VE~s7j9R_2j%T_sfriGq?7?!L)3`oSo$PlP=Foh!h<yAR3%HZkNtvV0fr&xG^
z-l0HoWIA;t2e#vvrddD5$NTM^mAe7On7gGl^;v<u|9KjIDQ+1qfFA)LpUw~OgR6mg
zcmRA2%!l5SH_ZM{UjGgu5AF91k(|95KIq4a@11?PS-6F2<L9yo#~%3@b3GCXkuB1O
z0a=j^SX->Ybxk3jJ#alfQsJ~Rx=6kpEKQ_ESK>DV(Y;M{T`u_^qid?<$8!*kN54?#
z;X=Mfduh$4lbi7DB8tiDn8_AJ1-O%zwZgBrAye{Yu>}077A%1+_{)H<e86OI%Q&?T
z=7pXK$0kSnEV-IHKq2n`{MXxfp7b!CO(<JTCPv|sOL_0eAar6I&-{Kg*?$ZQ8R$ql
zZm;xLzs4mfZKU?9J18CUSK|T!Biffvan@7okv|}i^cwhM?`%a%{+zYX=#y1)mVTBG
zDh!0Yvh&F+Ys+@^cm5<FJNjkoZC*wRTxWoc5+Jf=3mNac#TgIFA5aavDXbmmDGW!n
zrln}j2~tZx1MO@5LZx#H;E5hEm){|(a%HT~80D`{Vde4p+lnJ?>p}T6@>W-(Oj?r|
z7~9ydS_+ilF01<{W&LBMYpNHwO#iTRRe&_~hR%zt_walg$3u}EsosfS(k;n%9S0+|
zRLNEu`+^HXerF2`MZZXE4&u-Z^MQp5{LH&XVM2pD%%G`l7rd0|I*+YycJ7n^A9-&d
zA60ej|Id&CCJ;SQqoPuYHue%h4K2MAi8VY#s0JJ5L9PbNz1OC+(n@s(s6rl`8OUK6
zNL%cq*Q?*!UT<sbLzM?bOaK!=tU;(IJZMy^=P;m%Ed*5ZeSh{jlLQOxy|3Tz_50_?
zi_AG^Kd!yj+H0@9_S$<lfqH}M*aveA&#Xf(pNwbv8!Sf$h+lqAn&g=t@|j_~kMNzE
z@I<T=>QyU$Loc2ysmt(OP&_xE_}XI>GF63K<Ids{`=H33$<ulvD^;1*$Ng8{g#&pf
z+)%}FX&d?^SD0R_WtDM+{xrD39nF*d)W^YTHm_Wp=Xb~C(q|kn!y#)WdDh|sSd6_*
zVGsO<c}MJcA8T1VVW}Isk}FaokA1(`A~o%J>e^3}YmI2}S<NG#z1Ad4rVN8GH6-;K
zZ+od-IcsO=yHM}bx{_YH)V0SmMf!y;H5Ir@R?^RkAEj#c9we^i8y``7I?p3-x;OHW
zT{j1-iIphiOFaB)>iS@6#$K6}>gDXYLHjPgK;(#5i(g?8#eUr##Fs~Ncz>Wiysm#^
zWqN()bxL{_)14Bw=W2>Sw;Y<rwK=yWY$euVLxwEdcr=(kW4f4q#BM&J|NEWh08^yn
z9xj3{?gL~xzR615!_!)Mjk}a*;VW)}hut~i)gvDQ-+aYAe$<`AGy4_yTRc)F#qPiI
z-2R?>iyj}illACwbtut@SKKl^)W8*L;FbDn<m*2g>5_$+um9B71$+_nU=zD)>{r|z
z@ACow^HT<%i(WB)w|3{xjvOV!K7y=O*SK$+F)1_VXdY@OSZ{+h<n5kHut%=TPRJ#D
zO}-*qlFummqhBS<Hez^XgzHzka7Q3IDQT{!6q{;-le}N4%)n_zz+_6_En{-Yf=pJ~
z$sat#dki<bco{ixTH)M^U%Y7M$|>)z%O{ftisXF{kaEOf<o%#hd#5*7eNDo3*Zc#i
zydq}i#0OF-0qd;AqsC6KAP)nWmW-Lm9i8|hnzCXG4u$&8`+9Qxp%A+z57IIGIzope
z;7Hf2j@P^E7?n(^MAnh~TBcD;uSWK59{<JJG|W^Odh*)X@iU{#ymr>Ec}~z-i9f({
zUY5Fln@M3cbsL3mGwOE3mkb@MT_+)epm-n7^ondAKVo(;%QVXNO1BcjDI)y<W4wnW
z@-67wN;QvAW-@LF*8?Ex5y{<Y{3Lzchz41q4|}I6Q5yMbc9;3T!pT@x6}y2SA>a)c
z2sJ@F^pucdCA5m_>VOO*GzaqH3r!E?!(}a{(Sb%zexQLM&|P4MJ`I8mHoEappaOru
zk8t>dpVIo+F~sqcBwzA#BaWBeFUIh=^`hDZXX6Bae$wpb$f{pKdfTJzCUc5hL+!_)
z{%%#4oo-i|ra#n8oJq>sUL^BiN#59_`F({<*h9UFLd|Ss!kTIuR(8`yW@qe0CHB--
zoPv{6!!7q^7OO^c0zquCz<DXT#1L`v%%*)qvL=@oZ@c@hmNM~*@!uF!YOVa(K34a3
zBLOH(k&Eh%)$$sdT6auAY=z>t_Tww&&Uda~Z}P<6yM{xPtjE_qK@3vIUZ)C*%Ub82
zhuJQfG}T3SB&V4gr%~fwKh3P8lUH4@p;y1i^gZCW9)IdFifS2u%v(Jgc`W@XcG-gG
z!@t#-L%ox*;~x!?CXilcbcmiloatYuEPoQ^Kk1c!)RceZ4SVEKvnB=HOMbMPQmvIc
zkFSpmmR#_($qm?btmSv`i!@3+#1sF=?<;U+uED~O4Hojwuz##}m%4v}d9a*QqV@QX
zGI2jr9Bu*bYs4l`mNC{Ca@P=f>OOL+cDWmr?d0;z;Oj$!FZWhI*(q?}f)Jxw0dLd&
zsc19<{D0(?r`{%Ldzbe=pn>Rzgl0APsJlrWLmm!R{NGs~OitaJ{JA*Tp0RaJp`NdU
zVn&B(*#5D?-Jh5Y;p7kWWs)QphV9o#GGnXlWu3a!{T``=kQ3!^FFv!MQqMj$&g>`E
zlUwQ@;#V^xcZgqN@3wZAHzRESLFKi?y3>C^2R#+N;B)&amG5pQ6%?}TG$MJm2{WgF
zD|pcTsb4HQL=WHhf<v@HeP=oKqf@t^aw;gN#dGgrN}}=XB<0!BO(L(U%Ub!7eaIUs
zeG>2U^!s<2f0)VR_IK?MQG#DFz4%%6vg9Nd0=IY_xnzsGTly75ITh?44*fp;zpAh0
zzK5tzbg~{dHQUb`^nP14YF;N9_jllbPFc6VW49aljbs!2_BvBafnUlAaQ{O-KS7qM
zzt|&>x$P)Yz0m&u1m~xKnG*t9#=jOa6_&i_&XQVpN}NlUei)+P!7m^FU4F@@90XcR
zEKXu!t0h*;ul}{fmh$U`$zrIgTVleT7p9IHHeq6NFHD^!$Amr79rh4!xh71w_tHJe
zTb>Dfx;yL%-UgYlwcTN>c^hoPHg<<K@|MqEOKdB@UU{2%D==X@y2Dy|8*0LKcZap{
zHr#~m?GEeUt;mG!?+$Z#8)?G+(j9h?w^1hSlkTui-b(m$+tBk)O^>NN?7L>UPm@OD
za9QjaMhjVaVr=G4)JR3t;XKo2|M5MLw%`hd`wpbB%?RVpGntv{RH&v`)7v>$AUUlv
z{gQc3NpGmz-v}W1=beRrp8FH%n(;M^?Jw7%Je+Z}YmL&_uh+MI^qb_=)|Roe_zbj+
zt<b~Xmb|H4iun>mmAxs}IK`~FkD1xz3`vdeBmX&P7&~h0vQ6@xcp7m;8OgDg+CNw)
zdb2)1jFUGTL--iR8u2vTxCVs^x9s{hd8cJf+L{`JAJNv@d$PX)0;uNHyva62d({&Z
z`uF?!=`rL~_Oq&ng{jx^KC*ogwYB#9Vde~H`?Z`@uBr|(pna_QzBN3d!^Ya;d#t#0
za5nVL*f@@3##wia?pQLe3wPKNRSi0uE1&3+oBT7mpk<N1CtHb9Dr;UOJw7<jWQcA{
zF5IY{jrS3wL9h>7T0%lt4hI>vvZdz?xx~%bu_Pu|FCk?fDPtY|jcbt3z_ynEp3=d1
z;yj+K!z4>C+>{#MA19|Bwa-4wH>#W@^(px;HL{2*m;6jktYvY$*jl-(M-LhpQY8{Q
z(t{qMN~Y00oLKsf$B96DV}*<kS};n^*p$plan-EIRAQQP(7BeacCwOs2RAGU)-O_p
zW5&53qE9sFTW#d~E%SYbvGGL)_1O0wCc0*bpkUEf+SreItd<zd6v}vJOn(~{cB~?@
zOFbyA-s;q^@-T1`*_$dU0>#ZS;VRfww$c4O0NC5n^Xwmq{7e?zkI@4fYVR2^%Sy<`
zl!Q@d?66~NiB63<Ew+9j4zBJb#Vl-1-aKVYYT;fTDSq+Wl+?s#ID65fBpv7WRohr^
zx8gVQhDVH*U~_lZ>Re)t52dkJu$Mrcc#SEnGW{g&V)NzA%Ih&q;uWe|tr0)dbUX(`
z#G4$`%?`e*hSiWR;2t2U!AiMUN3vzKs+MedS2-rNB3s--UO8dsmpaAj`iaTO<+b-5
zhuzjw!jiEcmpE2@11wOIwBorGQ+rQW%rXwQwO3`cKt^T`hhy6K9o`H{YVYZDnU(l=
z6Ol#4znHfW66$N_tuJ9^yul$YiyxvEN)NOw{wcqLx@GZ-%-e(<6Ez`>?$Xt=SQHVL
zw@euCg_rUXC~7o&ldy$1yVa(_)FjiTdjns9+iE37lE3yU;2x%zdxD)-;v)0*F|E_7
zG|8ZLyEKS<P63v^z3?UbKLr}Q<5hjCUP7pFn{BmB&;<+xJmLj>ZBUB`d8%Fm8%e$v
zZkdqhr4chIB)4V4NH63eKcuK-LWvjhfFCldWrED=l&t=tToYR+6nG&*hC=d_CUT5D
zG34U~F<aPbPblp{7#yNSuG)J(nH7l`Jp8kvL~tWk0P~i$+S|bfZU~dzp!Obx$;g)+
zGs<*KkH6hxvW$t<E8P!xrO-*RlTdxt?d%^gI1eVR#CF~|Alm)43cG4Ubg}yr-r(nq
ztw@8V)+chIgq_OccTFupcwD~8AXFBz$CbB?n@LD%>X`zi(Mh`F7#t<?8VFCGCU;3~
zAlSy2x6&Sn&iVh^VZdLwiS&0a{DamNk_pqIvb~4Lv0@Nv9>@9(VqjcuOW8)z4ySv=
z=Vc;lz_jZ5{opDg6wv7IdGpmdcryi}|A~1jmpA8LXnqskX@g>ZOu{!@Io~4Y=CtFy
z{09A`ud=BkmjjEs$NIYc2H#v&f`hi55JHpFa_#%`O`6pGLsfa3^Nt+5%|<<3W$<_F
z3lH$J`h0$pCNU0YgK)0P!$U7Oc}|j(IOI%UUXbH^ZK>w2`&GW^^j|8atFPx>nJjAs
z{4bs~x14MSkeDW!5?bvRyzL@)#yZ2%Z*+sVf=xH_CtUlYtXKUa*I)#yxxhC7<-`oe
zvA1W<4n$AK1_Vu(JZWf>ZC_vRo@3g&TGg1Hz3h<~SI$Sk{RGxDTNv%mx{X4VF{)+s
zq#oRL1M-}4SeLZ}nOV3EBkK*hSXonf_ah?%wrRh$!ZV+8lz~to0r&SXkW3jaFE_q#
z9u9<oZwUim$F=aP?#h?#I}r<)oEi(~2n(Nc;>fB@TStk~n_x8ea)Xa#FnwsXpzhUj
z`Y2vW=p%BN#vE3Y=bOSpKhT;42DXnwku#mkD7K+?!5Omyk@s)C702mhKo5gA78{eL
z6A8<dH5G47wi)FL*t{k6vaHFz8?}<5`&bo?oa?;txM)?opbzEkvj^Wd-IQey@}87q
z$}IQFWY(D+D-|?3DaQ^b#}e$-I~DIz4nOPu7916R9=%t3@3H+uQ)T--@6qr?>9F7Y
zyws^ke+~jrStA-ZZ^+a+y;uGz-aCF<b^9x!Q*uU5$}CgbiAP`~Ux+22*T+Y{@g{$z
zfK+OiJ)L^yQ9|uQUIr)n7xj|J8QMWvw^4=pd>4COr<e7Ko|E3&P>W&vf|l{ITu2ls
zjdh+GIWIY-IaEI-tCBtD(T-$Zvppr2o8F6TO(sf2UG{OB?b=oLxarA6rO0fLy9MUc
zPFK$)KQ5F`8hrKgce<&fZok}Zm|SF9ln=PcNuku#urr>SL+XC555eC2uE_@;%r(y_
z%}2jVJu{RiFsOA(<^1F$={fZM4J1?#SjjVKRz_(w>}<-Kf+(p(l$@2kzFU+?7^nwy
z3j+@M_0IKGXSl1ohQxb7m(YTsBm$3qkr86AOMHp2)BtigaXlE22iMxZQ+NwRIR_#X
z`6uVQ>}b<IsgVlgpF4(^2Kt5xF^9GZr@{35M&auAdB)3gT#hm%?-!XQ1QJEOFzk-Y
zHE2mbFAQ~~#%pPt^E(Di`gHUeukAh;EN=&;8<Nim4Ea5Kg^43)P>9`bM?Qy#^Zw-2
zgWV9M%1;X=zZ0;xdOQy=igr>lQvab9bB|=m^W{tmQ_l<09=YDo!b^_qQDf;Qx%SxH
zlv(m)iMcH7Y}3>enZxE1-@SYD1~WkIZ#xx;I^p#nfY?3e3r0!z40G)jjy&dik8vmU
zA3bosnKY}Gf;P;_$N1gm**l%@z=DD=&-ue|DF$BK>3q(EIlAB8>ErX7Qv$0qUjG5G
z8JVAfmA=5i2Do$NY3)#IR4?2#oTMe6Q%ia<o@qx0&CuiyXrfm1a}N9l`PnTE7QcQf
zBx}X@e*(AmrbsN}49g`Mo@coFQCDj(nKhe`<iecKFiI5zT1Gkn<E{^=aXrQKr3Xjn
z<B~6TeEWV0wXUg@pER%0+hWK1Ms71a(y95N5jJ$j$4J*NGE$v!NOxxxXC5wlsWie6
z-Ip~#OWiQ+yvKrv`dPL;>1lkXTgs%{ddEI_d)Hg*HVSCZy`-1VY;$sch~4t@MkEKN
z@P($stfeS`o?^2LJ(Qe_n{;#(3gzo|`$xaQ(WBc>hYaI~=z1_`iI?Nz)Ra+KN8Y^X
zm_7CrlP|K#<a(qhmvfB=Cu0J5Zt2^~07iql5LQMQ@C-|iNO-9M8RcvTM8*aEmpe%B
zyrPfJuE>SI+|8$w?!9D;*$Z<K94*goBafYLk}l1elS~(=&+`$+CZ6QL$jJGeWHJ6h
zwh+)yOFvN~UMAVN;y33xb~Nla(p^JXH?D?fbmi!I83wW9zXHgNvMK!2)28D|?(H{9
zUM&EfH)%8e!c1si=Iv(f=PKLloB?z<YHr&M5Ems!6@P3k-cM=QdvHbnTf$@tEMNmC
z2UOpiua*icsc{zx;K8O?#)Nn$f%Yhgy@yqyBA+AjCKTQ16V6Ot)BkO^I-1bQ?mr>y
zeifX@uFjKgY{fqyJBSu7oLfmeP2&ttY%1a8E%J-U_rHzUakhEbw}idzR^&ZT#Pjoh
zO?8sDKIBm}Oc91W>OK#Pbb@RIso2%xz6ms`ylaZL&&^6r&QImYSt)=HYz|yyJH*-G
zUbw+f$APZ7g~v#u0#j2~hs2H_{l@IKa1Q+1tAskcx+~d1=E;+Vn^C<0{5_#Jy4pYi
z$b&Q;m`#X39Wcm<UYOyyTZqwg;3mXfOJ7B*72WNYmBnr0$H=;AlSO!xrWveJ<t4)`
z77ny?TS^U2+uMq#hwjc|J2YNf{foCmv+OxJx=jb~eWM%YD(A#-@pa+3{e92>^E|!D
z^pOq_r^Z44zuQNiV4k2pvX}I}9_R7=-}8%q90rDO@r&Q2wZi|O`NbRjaGrJT{Oo%o
z1ABJca!zu#zlqb|`J2r;Ms6v-{YNv;+Iu;9<m=$>GvP}n58$YdNO5e#0G+66p?j7`
zA1NKT<SYeWTzjk{dVu2`t(6!eYmfyaUUhDQkG%M3hkX1nOL@nOG?aRUKa&3M%$O>B
zvnHUL4#lJJBr{@l3x938rL58W+N1|JWy<FKM_!NYOf5JoRJ?FgWFCf5F%)*>`m)z?
zPQrd&yYTg{$QNQAb7GzO_?=U%wXBg`u}&<2k`J-Y3M)ZRldk7gn7lUEUSIciXMe)#
zj&=68;t1bBRg;4|WMgp|=Pl!V9H_k^H)Jp5Vk_|1tG?9rVa?|`D{bmVRBA_lq6UTn
zzB~hM<mT!xW8teADH*9zG`p*;ar8NN_p#5xI$DW!lnspD{$cjMXAF7JgQQ!X*Z+^<
zYavNKBeBlhXxbgioAyQQwN|Z9|IS)D_4TH=vo7h6Dv{k<Wz(L8oBa8H^4c&4c6SgN
z8j{@Q$9s<6m7<gvAI<3m^<~Bu(PipZ90y8sJuGw{Z;V{7y&)b}^TBHMIR>NIyn<2P
z5z`H4Vvr$bD@Y5Nrp4=c^Un}4gp7Ra@U^+2$XG}@<*d-?sXHQ9+N?Y@I_7A;mJ-%9
z8YAats{1Rst>sC6g{GHGS*CE-Dwqk6VCNi|$}@IzUIwz=+OBK}kLB>N9{ffZWe|&P
z@L2uSmoO`X43Q77iaf~I>a36jYvD^>kxjTGWsK`F>Z`fBhd_H7idLk5P3t3*#Y^!!
z!J;$bVaC_wH1^W9x{Uiiu3L>M0XuKVTE2^}k#6KY*NSVzaE?DD9@KZ@1-{L>ztB|l
zYIS9h^yt;<o^9UC_Ff`=B3<jtY3^Q=HaZy+?SoPAgJtWJ?*ki|QEg$^ji8TJM6#U~
z)P&AFeZ*mA$FU|_{1+V%bIAE68Z;Z82}+LhN!^&5deDnB$9$F@EH3-Y+)Irx_fN(H
z#=Ar5XW*CQ-Qo1_cw(!L{L;DHwCB9W^y?Wu8qOHaK6S<t`{1x^wc_K*AFqBr{R(gk
zGT?f9&8u?-^1T9ifb-UWf=^&xz#_v9VZ;ye#rX@$z1=o!oGGb)uafA$p1Ve5PR*s{
znkEmwaB4<}wDfi4;yA<Nvb}R}@!R3cB-MAN>T7krr}~mNhtoe$yKWApZLeLdV~D&r
z5e=>6Lnt$S`aext-L;{#KjKNd|0~mOBiH1RbBg|RJN?7&Ka+U%`p*XsX8L(zCV?5*
zq`l2GzDV@?&NqAao#LrmGkr&=TiT!PJ1@h%)^ge1#KA{+`UTU${l0?=m(<-B9n_S~
z0#IQS{yL}k>N)k^kxt%vjo){+*ppg6EBdA)ezeGe*t1eobp{b5LMef!PyN0}9!{>g
zOwj05Jw%w@ihm}utRsD&a8AGaC)2MuAgIe}{}1Rw|EYe>`6I9J9wx>~8{Mmk^!mz1
zcZ7K_Ll(BCpEiAPqq~tFm63O=^{##v*I?l+GUb?W*`S@d<~u{X5{_%)d@h=2zY=Q+
zC&wT%_il6S_17V7ta=&aQ{w{+Ic@A|i?$U<_f{_eY3ZwhJyr6Q{ZVS<5)Mw)ZsdN(
zoWz;KEY?ol+BJ2zRKTs@pOoyEwCvOE{;9|XLFF&8+f%m%N6*;1a2+KiLq9jURR$CN
z4u%#9<4Kz`1>ja;)&Chd?2pnvY>0iQtxwma9hNOIg#Bg4-s{;efZo1rHA%pEYWz=;
zC_oGDSmGHI=7@(RQ~Fl>`fzemn;qn=onZBX5u1${$N!=oU;S)5M*XkbF~5*D{J5cO
z(q5W@eNpHCET2Y0GDk;nj#0_a-T#J6dUAk$_t_$qHk-YtHZG~iJ-j{`Sr~g8-`g9r
zXffy3)^OJCresY>E2?LqjQfY)>RRe(YgTmQw)b_BLgiEJi}Z!bv&?s;MR=0Qim#xg
zj7(t%8f93^ze|{Okoi0%3F3G1;*9zQDcNzFYj0>ub9&20?=lJokksHrSX4p;eMyPR
z+F<(lcd@Oulxl`xV$L%$a7LuRA4&rbPsqim_{Stlemy5SP`f)*QTAvuvF>zkrbERx
zupb;N#QVvGZT7;o%mTS3VB_d{AuDkQIAS0C;nG|_Mo`3&(p+gaR^nDZ5F`tRjtL~A
zyY1*|t<vsMB{y@a@g_BG8DAqBpF4=&o%$LVe6`xg?8-&q)chdo*4$fDmG_0~K2~fr
zKYb1Gv<)k3ZR+fkBu&fsMQSYvGbo;EV3y(H@z0v0b+j{IeEf75VuxPv^!yEWXHU`d
zer3NtVi&s~8q;S=rj{>e4dEx@v8Bajo93RIEMKJC(p@k3!SFZ*&vR)z?MO~qYu`ve
zS*=5wt_@{P2o;xYv=X<&GWLg33Ceaj`Lff{r>CwK!%te99Lsc>lPDoY^7|opY&u(P
z;EmPE$b(@!+6q3)QuD~NHYFxm$exAtxq=HD!E>=RvmZEw%s5DKK2IxCJ+3DAx~rOL
z+E~L0%2Fdzq5kT2Q`g$%_tEt>YDWEaRa~|)y*TzZbY6(GPyS1e4g<gs0iJ@C_A5~O
zPuPQl&7!r=33%To_)r}S$wTnLXnJd)IDJCyC0!6Vdy_pOw|MHtNZ5Sx;nkFgqKzh_
zjjT}@b0}VaYFaW`9R@WDoT&Olg@BQhNKSH6BZq2TsbRz%3|MJQEaXj&%l&VUha4!J
z<VgE@A=WrvvlczWcPjM7ZBDXsF_tm04E8Y%eUn;?CpB8JF9=O#Thm$m6tA~D|Do3I
z^qkydM|Y6&t~Zr6x;1N(`T94`OG`hfwdr_VBP6TUi5~#5H?A-2kO|`54*`_nW~&))
zq{A`XY$MPN_Kntkh2+dC+gn`Lc-NWNLRP#sin)>Nz9VQ3-jL?E(6pYW-;RkIozPxy
z&O=Jxnq$w{<SD=h$&L<uk@kknF*A#)6mBh_%ddt_jV6hMl$#l;kuUdzINz=-@)J<O
z=4}QoUjt5`msQp=x~!4w2*^Fop0Q)}!X4J4Z>!_Z*b)4ATN($MWaOt|DL%e#3LCdN
ze?5p8^oElros+ZCd4~`t6%;o2xAvRqRq!ZBMK2Q3XRJ<+3kA7p%XIbR!qr0AAMlh&
zmbEcnC2!2JbL}xXwO`E*x;x1r?)uQ&zCaV|FCP<dU#B@HWyoDjZxXxR9CjDz6_&U@
zCpEPV)8Hm>=0?4iJC~8|A!Q@M-8s6Qm#v&8Z)18O`crerzp?iyIsb^v1$X;6nsAQN
zOloy?WQ7sn%(S+;s|b};a0fwo!`SlM8JlbF?UJ5ww)BLAj{0`vq_saXSJlwtIRF5D
zbLT4Xs4oOAKyJESgc$u<=M2cwF++!v^h@T_!Tjz0S<r#5pKDJJagdNbIc#%B)i|@<
zQpK~gf5vzQYr_4ps|S0wr|0>=<RTk~^Cozf$?Bfu*>m`Qct1ZJA8LP2FK9dWXA-{a
zC7d6}Bx1y;EMss*;9=Q5kR{GmQpm{kb)a(o@V-nqs!(Zs6He4Vv3zq%L4yiXOS%h6
znu3@qarqG883=AC_(oR?A%x`1l60{LQ`AZ?Cy06i&bdnDw=}XZy$C)-U-}0)Y#GOB
z0#3%6hMgLVi%8Us#TS&r$Kubhk_n3oPJzWAWfDF_!W$Ef^Y1$)78j91Se!vSo$nkt
zDHf|5{zrHmXNod-yuBA52NPUjPASdcapwvTd@G&G;PDlLdf_qd;n6#j1amI^#Xkdt
zH6_{gKz-*A5uh7dJiD2vH*nt$F&uN9(^Bg5rN;P&#cCpNipXw+Zs8+?r->d!Rw72A
zNuE60uqO8yc&ypTHH$v>uNSNoS1*m?l!(2IR6^{vLTujtlOeY5Gk7&ekr=!7-|*;r
zKT>H1x1v-AltzN5xmva(#PDdfLSPLmy@ViI6L9V(s26T^M{9;hXXLbay_zMiap($p
zS`uYdxVvLFkIU^-Rd@XfoqI8bc4M)Tj|?<@s7P$N@Dyx0B9ky%5W$u*cb~j-e*kg8
zp6Rj9Ypmm+q;u1b{}EsQ)|6#%_wT)M7bm#F)zz~Z+>Iqf@LTDn8Qfh-P%qrYPJ+7=
zd-FfUUZOYlIC-cWdmDe?)qd|k!rn_H#P0ofu=gY>y0Q0D_oUeS4DX#nHr{DUGPwIj
zFWgNexWd&uG=sZ-gm}1HmciY}4JY8vx1&imlEQT1FE2k;7ygH6Jf&=0NUeWQHg+>%
zoP>WLjo&6kHyUqrPKw6=p=|soQ`Fzc#sI-5%Eon|#KU8^Z2SX3y?D@<jooWqtle?5
zSZ0BWxokfM?)Q`CuspP^i@Uq3v_3Fz#^Ia2YOKV1I56pnxLuKRi|@|ixS;Pe@QmD<
z8kd*6HIJpC50h6rlAuf)-yr#FeWcG#-kekXMJ_#40beIs<owixJo`<iXu;?^#q)BQ
zmfW0&D)ljaCIe0MVrlui$YQr;AYLs&t2D^k-1MJxKZOBt?=mCF=D&POA+d!N&?o)d
zza7(8nJ9zr3w!Zx1Hl!>%nP0b9S59Cmw0+95PfWp;o&GmIhO*3k*AlF11>=(Tt*Op
z2b|9n)I*QVa#7-8G${8;ew?pRnsd>+z4;~Grgb1B_-411B<7v-r8q}i`jwISf}?;q
zyNpDirwC8hc<UEh)BIbCe%Onm2?jS9hr?kBOn%M~44RDo(p{&!djPwEdCsC8y!bS2
z$WR@hGvyeU_e(S4$$RigR<)C7n<CItk15l@;sJMOyC3jcJm9VYseAI0H{}8PAsea<
zf#IHH$Lg2OID41_^+^Wn-G-vgx|iJtJG70$?O9|GkJAKvElD^*!86Ye?y)H7gcoc1
zQz`&AX4S{c=4)6i&7R~OdG%wJqtLNoyEDT=n*Vb*7&@TmlP4Q-H#G6PdNIIq@M^|x
zGm4&S^!XmCU@UhOIbRSO{8n0VEeE=15Nvl2n_#T1KLaG@MPDLJR@3V=Ba2Vu%eit1
z{q3{L=7pwc!<aWyR)*P+V8p-KmAfwnl;}pcKLsQwhuxrghFoppW&-mwFN@*K6=Z=k
z<>qJ<?Vfeb`-r)bb<GFyH29lwlfxL8OPHBWL&J?JX6RQ3aydl*>^fJ^ST?te@HBz*
z(uGX~*d6xPBpzX*3V%J*)61~2bHLiJ$XM1qzhaJ>G;)Z8+6+JYt_BCd0vL~;k^Tbf
zN`4pWAn+!W<v{u+_<Z#_5ZYINx?XF^f(bCUq@SXnu<i=)&&YAsl1DB9XW9Mi89DS4
z>T%DaspQvdCGp+;N}cIBRia6ZJk+WhHoI35keTBYIK%nEod|7*wC5_VJU7bz;@rwR
ztM-2}L!wFVon`9TF--DOk{ER?(pQC3_8WFj*?BBKczPA&&!H(|gOmC^bdZbnT<Kmq
z%*~S#MlNtlA7BLpiWhF?6zpcfX!dh*X^dd~(uXm_W^_1ZTVsla$s&6)=_eZlze(=N
z6&C(i!(40vJ7_&Q;7BVTg2s=pS3UnmF;dem6Zn2J%pA<G<~mai^F&UAX5qqz#Rp1l
z@yqgYal)+UA7Q4s-p7om19~uL_|7><EK70VVi|8D@{rMYha=;A@L<IHlco^x5Iqwu
zO-yCq9roF*LAh&5;9;gm_g45U!l!kO!wI1$+-nbn3OnB;+HUgD_bTW+3nUF5eSJ7G
z&|vvrj6bHyu2*2s)P8+<M5BUwa04nQLVjA%-$z`FKP?1|w@|fd-26ZPEdfmXHWQDW
zI)MPfyFX?yyiCfq%XZUybd>YLJW#fiwT<(N+b!Ap1Duz@)iIfsXy7b<(^~up5!Ul9
zv4cY}_*?OZ`CKxoWBYsS@_8GEA0=zGA8vQDJF(mHuDA|X0_>gJ-^S%w?;K#f+azh-
zp0;-$iMH9>k9=b<enL&f+wYpKlTLROZaQzfays@-QofztYVXwNzFx3k*!0k8&UN5a
zY4bdI<U?~nG&a_qnZ#8M#c$pfD*kX@KkkG2<9Ww)xsSJyg_X8x*rdG|Ol?aqDK6V_
z*9Z1aJg1CLhOa-d4hN1FvQaF@{-ZfzIeK|<`@CtNsa>aUgDq^c{I+1BrE>2uqlV(P
zd4sIyJ7Y(NL`N03S@*?3)96Wi=hlEvj5LfCJ&9?pDF7o|uTa`@RCwFHS|~2;v=7xc
zZQqxiv^#r?P9QzX22yNQZxHxC1sny>GxqY4&fd<o!-tM=&e1k|!;x?7W_9XPHfX=e
zX`D;&%iU#8zv*3(*2R^-c>Ue&4XJx|?DK7ifQE*yODZ`ASI=4gbGHAy-G9zBPrx((
z5Xy3E*9o=d1v=gOLKygb%<-I&uJc>1RfEr|vIpnJ*7u3I!RWzTZ|gbRQwLhc_7BIE
zX()w^#HqD_f<`4P3yP9c3Q8!fIQD)JuRNU^okOxPNpvctYIY7?hz4@dUOz9lIdoQl
zOa&A&6nf);nclCInVj8y#?QH$oW0Wvj?BNwKoF+(Tx%64{?e8+utl9_H&xl^aW_wF
zUoiUDTYI;F<ROyhSgRO65ifl{+CYX2s*1zW)7Ad;S?p-%EAk$B;e+VG5se!@>M3FJ
zh+VP$6FK?6gf`~#9Hq8W>J&j;fU$}15Z@Ix;{3wP5jU*k_KzLwH!p`nr#``t=ea<j
zvFp)rq+i`j;H8$94{sk|Fg&(#B9IbUTa$hZM%d$>r&|evL2lg!>{WrLcg~fyye5#n
zJ^g$pz9jur1{<PJIY5o{ffJD3z>WG0aCMjU0`7AFH|R0W`j}EMN{7`RtbrQC`5MV{
zDA0!M$_s`I-aX?*wermQrF;>pagx~1uC$Il?iIr7{(6-Hx0R?QQ-0HzLb_xjPi^_2
zD|;KO4a3vF@Y>_osC0rLEi+=T@($LR%OtuReCqc0%4EPR5||m{h*;&q2SoZlfOiw=
zO7Jk!!$V0`-TJSTRsn_Bd!$~5HtoyR^HPDQm*IZE<zT3P6(}kS)b5(?A;`3+ikgbL
zYV^1~P^$-U>2ay|pzidBlLmWP8uh^SI{lz`-mLlbvcg;Xq69ts@+jS%gJkg28Lygd
zWbrc1FmN7SFW<v=Xip=}wQ+ldZ=DxwjPXA=wjmh%cwqFc*hVhRMg~}`LVGrnj_(sC
zLTrBt%w7rrvI~d}<fE-;j-FMNIvj=^%5yN!D|o8c4Cfhscs`<ulrV$IVJMa~G}%_G
z@iCtcdb$~`Sv=j~!An_$?z7fWSlWT#OH2X?QW`tf6}iqYT$QM@?n+JoOO=MHG#RL$
zQgDUAB69(F;a^R?gRE76XzFB;My){lXgiSlwK=?-+6JLNUyQuD5b<$7Bgq#yn!(7=
zkprvjkzrr>988i~89DJgwlRk`<eZr*2?t*y^-2Ih-bMx<ud*Z7@tAAG)%%~#(VKee
z-#Mz>022Wy%BAdFU<8iB;v<nuSjoG812g{nn?^K_dMWw^Bzk{qRZhRE;+LXdLbypL
zrqNhV1dOw?2sy7&z{WcI`0&P@Af)I2W+Dq&!Rgf!4=(y&VzcQ9(L6lOx&rfN*5~>z
zDdp(y?8;WZ9}LhH8QO#W61APDVH)D|csC3ql8HKs$H~CiRP8eYr$K9sc{TE1&d`PA
z4Z!dLL;CdnLVV`DYNH*L7}kPn6|fVW_wWKZEjbkOO-U9pPR)UM^ASnYx!iMe^z3wT
za6_=A_TH`l`>mS$6fY>4J{P>5W4DoJusxi69OzPs#+tSlcxolzX0G)08MIGD+C@Df
z`i^}NY!UqQmQ2DCy)u!6dQ+7Jm&3?;>AlpvAaq$El5gt$KLBt-)jwzENY(A>809wL
zQ1bK_RJPw<#$(DWvQ{CX;KuyqX=<vq>Q$W0*=T*5x>z#XnMxrshS~<Y#f9meJv=3k
z#ma(Gd&7vv#H(=CcxYS!S51TirbN#Gg{6dy=WC*benVojTu-_p?;2N-67RNZYh@qZ
zL-LTC4DPrV@>jgpE`ZFDvik7_S5s>VR5g8&>U5Pt4y&l5jiI*sqFqwpyuCow9)wz~
z{agXFY0I5YeR70E+A>f`l7y6Yok`0W4qpt1PD3MK()CY^u#a_%p%dz27hn2^RV}PW
zvt9J_6e_kssm=xbDm%+CtvitL&q69eM(rm+Iw}KcWPq3PRnUUI;3V(KFlTHN>vHb1
zgi}F%KZ7^-w@PMueoE^?0VY~QlV=<Dlqz+8@@!FzMh$qj6Z1u+4>wTac1`<6igY$!
zeT+x6D=evnV&q&!iLs4C(H+#DsUH8s6P3`c0@_VU&MugqXe4!R_$^8dfxukTKN5#c
z@5u9dhlnvKa;I6%{1!H#C`-KunEcO3o<r|gU%baYXKo=EMp5)2+bwJt?Rd`<J$UBY
zI74(gk71&KTVH|~2Z;UKOg|}3-+jox*xbKDg~R6!7Eq_UQyF?3i0rp#7Yt?x!0duS
zY9qs3YC*x}>9aif?*UUuw>)R=gQk9$^qxmXHxys+px{s=k=aAHcfW}yqS9K6z-S3T
zmU_rfY)*dBLw)l6X9o#Qee5klcDYf%M$$8kGMhpAi*hyCSio3lI@Gh>9cnU~#Qup?
zAZeG+a|%yYIGv{iP$lX?KJUZZ|NM(LJNC3$s~Qh)3`WjByfK8cipRSp@Myq#fec)w
zlSfSSR{slp7}0r2pw{Tbv+OJYkPbSSvTuh=bHy&`+%r9GZxF#ViOy3O<e9@$)rXz2
zr4mr+oQF4-Muw_j^+;3Cnhh_Yar{E`P`HFKN9r`Dm*M{`s1#^AMN{2dD5HTo_bU|U
zeiLLHe!ebr_{Dr|Ker4jzGZNAZtb6Qqvyif*A1!<4I~id!sgfTY;piF54PbQz;>$V
z(JGA=CnW0KU#8kG-aO5IZL<B6r}?Q(VcIktn7l!QQT#pmfR1A}Fh5+}Y%PBj_%USi
zni7Hw4<;H}Evp`IcwAp_&hkfq{xmo}LGAU?6t-5C1t>bCqJhp?L6KzJP<_dWE_9EQ
z;jxyWAax`#?6$&AnEt)ki+z{?B@WlDL2eFCb2Bjex6IVg*-I}422N+Al*wVzn!_Tv
z7-5`zYr8y7C4IA5*ka%X#9sLyIWd3qJy(`W*|>y{KTfu{OEVawHiwGW*UZA_ws^zB
zX@zZ6cWt<ut2q0HBGVZ5E;sOB%_c@#;OGLc;y0rQNbZ3)EnIz`eaM5kNOkr^2<9Bq
zom;LoFsGkj{<|T)Lco&DbhAv}zt97F<&D0Vj`fmHgONvL<g?v{{qb8N`uAzg@aAP;
zo7;0^f6lj74*p{7oj0@7^@FdBH3wtIv!eS`H)j>DH~98u@aFysavyn7t^<*?Rl+b8
zrBc$XeXimC$cu0%2Qx+<QIh=bB=>_~*<9>b3`cFySbAel@~dGR53nIeS}$siHJ)3%
zX<;8731e=3Tf}-Mr4P}qZy2*Dgt(C4G!(A-`+=aK#-0#j6C0Zt_hxU3OgHVdag;=B
zf;+<l0D@-@5AHzda8ASO9cwJA&q{I?0$t){$<TlXXro$_-HJohYtbiIyWs-pL0Mcv
zvXd8UL}PO(t0>kOEN+edHMjwfODjGIV3HFU8LMx>SIDrygmCo@$*+ZuG&K@uZ;A91
z%_f9dL}9G0{}~V+elZlioLn9o+#I&IR1XpV9rJjh0D;#lw&p!N?BcI}e`0giWx$?3
zjVng%W7fJX=VN?jif8P->-}D-VJW{D-M-i>qUJqsAz;P^T|yLY&Kjn|8e?ylMxJZV
z%Gbvq>`j*h`pK+~c;aYSc&1kY_7-bdl%VFUB0@=@0l(&edkf(WM|Q<t3mkdF+;6S^
zZSaSWAgoOuGPwT0ozWkS4NjB%;jzv;F<@IOHqf@%JIDCM&|@yc>qH$%m3-PCw8a{;
zWP_^4ti8kT^w_2|H9l)l^0shs8?4jjv(EL7VI9k`P6t~9wq!S1@z)@SwQ>@Mz7Cv(
z@EeQ0m0v$;7eRY3YO?>Bx}m6^`y{wjuDCiob;FedChe-f9{(Tfcdgs^9d62JFxL&z
z+p?RYTSrqwbcYqM74@rgm;o%4;WTSuN8y|LkfU@Dw{&{k(!sq9N{^R6j*lI<vn|t6
zF@@_<2C+CH4K9u?+<j-{4CDt!Qr#4ZB?`tnkIP!cI!(fXQk<<6RSl8Ttd(WEo5uy=
zYn{!zaBrfkI$P3**T@)voST<i*dcZ~BzD<~YaTYh4~(O1^*MAMUxJXrd7Q|^u9^cG
zCJ{e+vI$k#`GI1)Y7TH+2bAtg|I&<Co@nyJ(7(P;lmN66r}HKtt+>31JnA>Nokqxo
zdh^(DqG@H-h{mdhUcD=8#$LZzv$xHYFI;Y{lm4FT;io55V0BJiRj7-NvJlq&9w80B
z+HP#Tb~D3dNo;=Zr{3^W6|2q*M3C9J_BW6@M$}xuDrC2)*^w&i@UN)UcxSD;)>FIi
z9m^|lI`LOS%(qluh1P^e_qx#eNcRmv=gv+<N2de;{q-BI88m`Jlq&AOBKosoC4{B7
z`*k_D%|ZFXkcq)e5-gWoMr918%HGwe_<Q5;Rt-Q?->u?`QMT!rb0;8FcYk_O^3@xk
z(6X>QSj)86RRdI$wR9~-`ooF;NF1;dqfCMjijkF=!~3J99E_x}X<>NpESzF{(JMZS
z7;*Swp4Q5<Ru@qwS2Ops)~yE%paN#O9a_LF9UN^X#;wtS7>*3UL-N~(0q8H0i(HqS
zCo93ZM5Men#~&keYA_;uLt)`2hCX$KuZU@;<<NstT2U<IAP{1#WtVy3tcfnuFooRp
zBI0>OpkQ0cX<V%)vFzQa-jl%G12-*H`))t)erRu)%?z+V0`<KH*qZmiTYM93ApwTH
zfO8iK;Q!60c>-~nWT#h%aq0?o>W<|@23^j0Qlk*e|G;d`A#@mJKt^X65ylnK<9DnF
zNQF$U)BgsDE^GPsJs?B{=fGddy~G2-oSWOz0lo6vw3j+x)ghmq=aeIlKrenOR_L4U
zKTUh~n^jd+lZ`*WOwj1NHty~PrAPLmI1Xw$I;81XpTaHnw#c9tl#&s<Ie6rQo^Vv0
zarwo~2;^qeFir9g*8GdFd!Zr^UIPIFHfM4aIA4|OGA<v3y>3kpoo0qiHt2NZ$2OHY
z7XY7D#oJTk`<Zhnm<}<smR@A9Z#p)_{SB;Aco6L^{a@g3n(6D~Ig&<9avzm2R--sp
zFtgCqAeTl=r+;Z`Fw_`Ju!W+I77;dx?@@F!qK5OCnQ0YC1Q0foXO5X7JByG2nyS<t
z4b;K`8zPr+cc~P9b{J^_s%E`?J#}v!&y=O*+8hSdz-o<O##rbl{?NG%dMfS8?zEau
z+Gs}QehVHT51n|XKxKk?yJ^Dgf?3_*M!crj3xIjHX+~bA3Eo8UMDR7!aauUAychV*
zk?VYj0OdI}hICFwjs6ccw6_|q7KRP9<(_If&TE?*XxyCqlG>g7Ae>U~yiR!VQlmfj
zYG14~U@aYHdZP9K{=eBwO|6^`IdU(6N?nFZ&7M<Etn1SS-(t2>+*0#z%t*pkVhxD}
z>0iFBH6_HwxE!l~1A&I5M{$_|FWTqEU1J%<#D&7oBIbjy_B7QWe^f*C8kPQIN|!W%
z$;Bytu}jhO6#I0qtS#e=Y0k5A=v=kf9XY}DW~1K{XL!lrTbD(!2sSRq$QMul_4u&e
z$-?tL{i_CCBP0rSgm#d_M8fV+-ps_yzkk%&FBT-@1r2KO0|gHW8CaMJ!7nqAyd#IN
z@qGQ1uh^%j^EHt#@g=Y2)*{{eM2kx4WaFh7S@Fx57;3#|Vk%N_8;NotLMiHY5hjN5
zJO^=rJyIm!JD+7Ry-$XwQQS|0U5d97YbBr3%*qR{R6+Slo|C?v{!LB8?S08PId*5_
zaP{d_I$UdDo%UTh_CC2xy(BO{&bF4xcPh5w$^n%HSHkOq>RF!(Qp_OxPj-v-*axAe
z10nnU?BiBk3K#|KvyaOVVt*8S$FkdzWF(e7Lh$8(iT5utmS+DEXK^qHuND>4l6hy5
zqC`ueJclR0$N3NdMMQJI%aMp`Z0uNIUN(2%S&L?nQOyB%d!NrA)?=+fMDDhIN_L23
z^A03-ndVxFFRLP!IEsOKo<*s{J?*Eyn26YhBDcU4C<If_Xdzgr6tY3ImI5X+M9~!t
z6Cg1LTgxWtlkF7;hxt}a?&7TO6Wl~SqpTNR^^UBXQZUHK|GKv%i?Q;Zw>dRC+z;Fj
zBHf@P`+DSj<h<3A|FIW?M_k6Uo`~ps#bDD~ey@5qCKF%wW4EjqV;faNDuz^zG*3E~
z8Nr6hqYCGYokspocP=pBnp|B%U+NPXV){@xll&7Vbtm*gp<!;B{V6<Gl+K~QI_)GW
zK0cR=8H3ikezDHWqx<lIdI#}Te0<(MB!T^br)NygVdCV2@rWtcS3oA`pw9^=>xC`@
zR)rH+yexC=!F$7X*N4oYrSZr)AE^`DxWGt9?A7!N(v@PWXB~0g>DD9bgTY4cYwn>n
zr^9>e=q`amwjgqEwAjJ=)sb!cw!eGWOgD~<I2=59#xeSEz4+A2zQ!^+l>Wqt2^B%+
z@oogE;_J(@?tuQneTO&pgY_pP@8)Z?zX@eXU(2MAWu)5gace&To3t8=**7SMXK&c)
zX*+RJx)TYuUZA5Jwox_eVD2EV#9;vGR4Sd$bE=BLjzM!EQl_?2#f6BY79%Pk9ZWka
zaiIEqEC;t;PT<Vc_=2xD2Z~%>CWSCczkP%h5){$hM00HdWPY=k{);@T+b=D*?va94
z9y)Lrv9_DH<kJNmJTTVf|Bg)xM{n2Kn-zbHFl!yMxkx9WE`F6y-IW$V${8=frKTM8
z@!KJxjMcOB1kg%SsEXQ``w*&IqRcYj93vTL64^#1F%cdzXfGhoeAHc#RF1B!x_?4U
ztn-r8y}@YIFAYbt+eaM8RKwF$OV*j(-Ws$&Cilb<o6)z|O5fh6Nqg<FTjo~9I*YAk
zzoR@<h04{J@Z!9g2F{PImFK1#oU>@HIsE2Pj;g%~P~CI+(Rxv(vx;<H;T~8C?UDqu
zk-Ck-q+#WZyfSw=O$UEIKOCe%&kJ4N6|K$Y%z)a_vrSmEKhRY@pB0Fe7t9RVN}EYG
znkpb$>?rrvU&ni_^9pO(7+!Sz;!1|MC#AMcWC7~)dM3|ghKvrx_F2>@LP}D3KTM6U
zXjP=$#}th%@6T{k>_DH`r-<7pDMZKHSn)eFu9OrwXZ<_R^&q$s%lQ}CX~1qGKyvRS
zm)|}_`58%%;)vauR(u+Hljo$WLt1YHvGZxF&FbxOduhQVdS6lS5D(`|$SIYj17BmG
zs;%*hfmD#h*8oZE(?0C+`jpdJV=8e<L4?Yg+_4&Rmis=u(;J@*sonTIlLARodu)~!
z??;LD!RHZ|-O;*77gEh++O;YF(U9SjxUOtW_K7v;B(Do6ZwlF=f)wlu=Y+vw$eD-Q
zscPq)EU#{M{5yGXMQ$qZXn}0T;}fg?+27AziCUuUy5ml22*kn(>C<3_->pUF(BFW$
zNgfP|SoLv(;*|GrzK>B*MXaHS23!DU)`AW&E0iDaYcOra3wcQfD8Nh-sKEAeLoQLx
zia%v&65`HF@sk&-%IJj;k-(X3`ovl8WNLw0Gl6nT{^9j<nt>~Hbn>pDAh^A8*IJ`G
zndOB`0%fwCK_4srI1pH?mKwduex>fcKrP>i{gBpQiSQFES-g$kDjD~yw7TnM;>-{d
zSJk;)*JOeW6*Y<R)HUeJo76PO9^zFx8n0nqeFZJYIo~Jt5)^y(&w-~yTxl0Fcw&7a
zUc_s10GJXL;s!gE5&(#Ycv$go0~!p?C6{{XjB<jCx(jlHej;4jEZg{<;BxwuNOK`|
zdHl>*?XiD`9@J8M>`T-)o<_mLAh4T<uTb)*zd(po1^DSv{GN47-=01x_%_xY-bL?i
zVlJY>n;1%alHK^(WY40RE7{LUX4Z@S@^sen3FT>@rxJdTgc<h3n0x~3RlzpD2P}9`
z59a_@BIUW7JVxL4SOdO*w5kA>3-4J`P)p*!;fRN6xwY!Cf<;8yA9x(W$z@w=#Z!Bj
zW8C=_agSjLEt^6`l~aYL3WDQ$t^0FV|0?^jf_gsC1;R}oVK`b*09vcSRdG{()g@h4
zRpNl)S9MlGcgIqok`DBeMg~+tZ<Q4M#IH(J1sJU@`e}W}QYxRZmU^!_-SikCyC6dQ
zUY_cXG8|{*@l?XhDsgQluv`8UgZxm&Ye1&S2#;hk4pubsLGeQ}@${=q{3o)d5f39w
zWLfbM(yhP)C3ckE&^mva#qcX=^``>1d)R@>6A93wkM3kL(;zec?e(boO#)Tn?=vk4
z_f(iv1`l3yo<0pN%>X02pU=MnAfYpbpUiSgc=*(Hb>g&v*Xys4paDRv_@#uK&8Zpw
zHv^XR4+bncrSth);XaL6>lw4Y>jSzDn@8=v!7o~gr^t`p*FbVYpV~zd;7wf{O8zrU
zIx%tB{-RaCTcQaKq&b5M_Yb7=1Z9)vJie6ldbYb4%#+z0s;a!PN_Q$5dGWWx!Zphc
zRE93qGbZ1t4A+I|7|AnF95h`WU)f!Ly%`GML0r+akr*I}>~0#|+bu2v6evTZ==wZ7
z(;e|1c{#a9HECRaM5Oi_<epDU?1SFz^O1sC>hHuFTtrYHn%&=$cTZco&z`ntC!yV7
zj270NwLZqniLR<U(3Mpc`!v?w1DEP**Q&k&oYcI2=Kg_zXBk=oFI-D0ZUdk`dn0db
z!BBDE@r(PEQ54oK7aTB|`qoVMeiB=&JW<*kxn77{OB1XYd;*<>SlV^(v3*><Jkz5_
zY(7$n-KZI4brXG^s?X4slK>!mF6Vtqvi-Xm-%km|$5dji^MTNOC&Muwy4|Pf3NMUO
z(<Q&vJXE?ax1JBPW>2l5<aN2Jv3aTTC3(naZR@eTy{R1TQ`|J~z(*To^vw1AE95_r
z$Fx>Px%|}KLz<5F9X%&hbDiBDduK?~(Y~>dgR%CmR7GAYQlD3R$ex&c_xbj=mY`~l
zHHC`*IPaq)uLch_?c+Lx2KkT;Sd$NO3fs4T`;(Y)u0z&2uZ@NTSYa+K!9DO1Z{+g)
zMKbm0C-2T>n^&s*4|z!r8S08&+Cni5hz92U_|)467k-{Yb&byrHb)L_)s^XT-;1rM
zIhhaUI*O&zC#jU3KAhwy4oGo+PIHQrw0$K_DXy6gSZuZU$oaC;UYpB#2KWyxz>4xZ
zqFP4E9G*k5P?TV5D8&pgovHss!gYZ5;5`A2D(BIt<P{)(D4RGipA<Sl<{ogI@(;C^
zjYcNKKK(LhYaS1BW61G7M)!(bjc3I^)&mA0i^x2MDQNr#lCt{@YsK5a^k5^;FsmXm
z<0Dl_O%CZV<&8Bm&nsDHd^*lJ(+rFoR4NCF;pZJb@>=ZOTs}k2RTE74@Bud-s(gTA
zrMGzf!n^IJ!fnMb;~0Xi)=IU3B{ElzIPCAGZwXW=Na<-TQ5E(XHl7VQ>wtxj6QEvY
z$SyK=Y=Ls17*GzvPbJ{06dS>KY*NP4DkFa<gp1c#KTe^QkZHtWRo&9(m(=52G>zF@
z;9_3=`c-o}PC-*}ar@^HhmF(EAmWkhSHXWr+Q<+2)XFJWdyvv2ObSjcIF}?1+{JJ^
z&*ay*;MYogPOqd$-NOPCdqr5wyNJ6$3Jo^B6H}d^k2NLb8WIj75edQ|05Y(*tkXW)
z)Y&)o)(|Q(thoL5g1lsTEbk)R&nd<bq@~OhktgINUTx8U%~;vQuPWEP^jCVPdFzB>
z_dj~(M>x>Grf&D{kmQtP9y=1m3hwDj;MoU2@+M@UP52ND<Jo38n{$lUa{`F<JcmxR
zU7~n><Vw&shz*$o*iIMgFpL4jT0jk$?Gqwaz6a(|^&enybtixUDqldg@n!5QL)}k#
z_31~xbu)=}bTz3GgXlMi?p_Zx_JL27;=?JlF<`?mcndj4^tGZO7YLBOdr6>wyzcPc
zG@ytBK>)HE?MSQs?eFh-pkNcBW|eNXwK7<8nYCz%GBVXy#*!l5C|W%64r3KnD5JIR
zVC?u6$(wRB^O0pgKAR47yx3Zv;)TvzG2(y@uCO<y3sZxCk*d6nh035X;h7bzbww0l
zEmKQOwvY63EL{C+?3h)vBemdnfz<5k)`s+EYh^1w*86|Yj2(SRa0$sWhAuS?0%%M;
ziOFKUrKbHfPL1}_pusHD8b3?&F~eJl1Cd<XBdm~9+-9Famzs}{Unx4-rI2`ba&1Ar
zBAApQp^PKpx2_?*R|Uv-Zuw{PDU5fY7e8Y|Y^k9^IK47cw>hS@p$Bev8BEte!4)v=
zbZgzH;v?KK(wDlhnSnqlveU_I#(AEYWoUL+nH7HkWg^z~4J-a5UPf$IcJcfuy1}q=
zbOVq4!jkAf(?l_RePSJ1=B}Lfv&gS|SDxp^^i#P@#tR-Jhp|#j!57Q(K$`*%rpJ!w
zR`*?(ODtQ6j%V8s6g;7_R}?(W<ITs+7jp*jQS}wObN<@-!~{uDFXF^xZ#4M~m-hXC
z_O!_Z)T$ZCWA>M=W$)4?>aLIzV&Pv?<NE?B$5&1OQu*9lk+b*2O-;LV{#5$pgn(Zh
zUJ_Q~3xLQ)Zt;Q+An}ud-yA}A6CxUFJlXtZs#xJ!)RvmG!9(^Rhe2#`AjSb?rN<Or
zXw$nOyEAo6PaaHVWbkUi(Z(-nt-*3?<QXbRz9qQW;7j(*8DzXOWItW-C`D$-So}T$
zK4PVGE1~^*;RmrU+W1qz&+wIGCA{^<l}v8d8W?@p0Q?aOf=wfkYOMj(J0}ZsJsh+w
zsZQ#(1ECrr{a~oyQY!NC$TJU*Ln?T;2e|Sp#V09IEH0@;4)3xOm+8H{V2*@(HYAC4
z-C)JPOlE8O=lG3vebtv&R$?D)mwF&$D-3neQ6>C7V#F6$zC?8FF%vB#N$4Fve!Ge1
zbY@Q;1OZfR>N77@b|Z_^yXmlM1vs_KGH}J&li1x-4=WmiFAx^J&Ih;7&kb1rxjyz*
zXYkeREr-_^K`nJu?n;(&zNOUvcKUve`pnpv{<5`lOt54+&84K0`78(V?CG|WkwuXY
z;*B(B3NSJ7IGSa6D0d&$i~x>ChJ<xS*1w)+fHaaf?n$S$=ApLuqHyKcaM&4U#jl4~
zYL8xKtvgED5sC)RXRxrRCbY&nv#rGe%8GRrML$PnDp2yUS262G5gB<uHQ^QR1h5vr
zBS^f2u@8z+x+>@Z3n1!(-g&+sjCEa6eQm6(xMmD1<j4zL{=rHu<);T=Z$W4iHz<|I
zovt@C3}%2<ZCBLbm;~XJSfXYa6;OAL_KH>19UXE50-^63J(4s?+)x2fN7~)53j07r
z10Mpr)-qR3Bj6ls`34ct>*FA@0@vo8=NliNK+>zvB<b4L)%4#$VJi}%BIS`YxCvRA
z1Jxy}W1U|HB*`-C!A4&SAm4W99FV-QadKa3n29W5pXpL-jYt7MA-mI;D9%kxBmg;a
zF=84A@H+rm_Ck+{y~Y+FAw=w;PWK^AFjkfZjmj2p#G8Fq<ZDRL3ei;ja@DmcnP&|&
z7^?&?@}8dq!nCSCi-eJM_EmXBR$}h}+S1I?!g(X&uSWNy3(O)_B|vJxs0bdU|N9KI
zZj=>24L?DR8jKyi#*Nh1T4P7E36D^{JYxdZ;?+RNuqF<od{eU^06fx}kz@!Y2r|n=
zp|;}x1=dsF4+7<MCV?fVr*j$4gS%ji;!Z1Gr`U<uNW#?)CxF#BsoB2^1P`P;GWsZT
zE>krlf`lM7&7?KcsaeB|T9k{<n<Ih%LC9tz6GhL3`m;r3vYRoG<+&q!#KW=199sT>
zit+|6<ls;FqWoGOQpfyR^DKl9#Zhv|`QaCNZ)OH{x?Lh2JLD8Ga&wHpfoc;Xjr+Sw
z(}EDJOzf&21dx?JVL~>Zl@*HBxG3oikPj76+5Fs~y}??x1c^n%rnAJu5;stoiH|hr
zdss(;kCvT@B4RuS9%c2*ihosX4i=D=2E30D_3eEJGj#58-|TqMy6+}bfjw>VZkiM}
za<M_B@{fKplZ)za@j~N-P?V&l5l8LL9;|U0oWacXM1saS;7X$!EZ@O{#WUaXN+Y8K
zil-FJwwBibVk%y+pLlld%}hO3;PA>&mBYA6%fn9Ua=zD7l+u{iJVzc-ny2`XbJ++J
zFUme<`h(_HIxSLd<Zq(Q=9pPmn5NH3yb1y)GKBiWRhcGKCDF@RAssy?*IN37EZeYU
zaoq3?mugWEV@U^fYb-JROwG>g!>NFRU*Spb7NRt81))AQ%wi2j8}MWrSJtc*#^jvk
z;iGtc^fdQM3ikB>J#ExDCxbqTtS5*QweM0TB?Zp6Rfz~k#kVPp!ETxtwjepy4BJ1^
zCxVs*JHw?n<{I6xh3PT(Awf5xBWyFke-5_^z>?(P)CGmysv?{HuoNc}PRtd*d-zS|
zq)cw+*v{J%$wSuw(P~wTcTH5`i;!z3VWM^LMduR;0zX#(aYfU|Lyl}015<h}(O5q|
zPt-;0VTN`*OqnEG^;*6NI&g`4)G$~ni}HreE||@7c!VUC)dL8P1o!EkQY(|Q3o3)_
zgD-P3{=Vuywp-l9Z&PA36_K`ZQ{k4vm-P;;Q_!lv0%E4{E^#-}baxv4YxOLt*9zzR
zT{uMj77LSe>{8Rta_Yj)McuP-HL#Xn!u*J_ncpKjDav%n$LT}v`I<OQ%o79Lp;uU6
zu5P-+ns%Em;12*nk@Xi8FS7nf)kLVCu*G^`z<MX)_bMI|->tC6JXN|ZJlZSCO5KUg
zi~D0Ts`afJ$D~@1F)xVEwPIqA!fM%Y6?1~B!=Nvwm3{-iXar+$5ku%7x(`=54M>d{
z!mKzIT2$P8w`Ct{>BD5FE4DsV+&b?gdkZsFRyQ#4t;r`#;kNCwK5<{?Q~H5Hjo<GA
zQha%brTi`j{!8%Q7(I#JCfg#kk;)hUH9QZ{9TX=ykH$*|eR=0U&_OSvm$<dySAt^q
zX+@G-o-w}dk^(;3o7y`(LAK}s`S!H=u{(`$Tl5oA#<S*Ud&;OgnQ^wNq0n_}neN)S
z!2>D%&`hbFKY1N&BE8=*HqS>XHfYl?JZw3y4uwz%fh|0HA^f)z@^lk-6jfF=wD%Qs
zEEVnE+`jp|&9S#Q`8$`-^A5!R9NbgMI!522Y74Du->e2OWt51eS50})T6_TV>}mI<
zYDP*xuZ(PVe~2#VxBE#nhPKP{doa_!*>C;Nh;ctP?S&T}qj(vo-qg7487@ccLj_Zr
z+zFm7VIBD=U*oulKwbq>zFz&wx!ad|eS21<c&Rtp@DMBh;y4=$*A#1rwd^kgx)H?W
z5y79Fl}8O{xW5ztv+Mb=5<gLT7U!FSv13DO+}N>Tbs_dhENY|(!8euG+LyN<;AIL-
zQ#l&hVH063zs+lfs6*GA4bRIO>P?aupgRZ$mm%jJRzZEzxziy{kG?S5r(WTolu(`K
zb#<EZg4u;0^&yEV#v{CYooW;#H)V;Rt>??@L$MF#{v^=!ozgeU;Zv;C%OrNs?y<KV
zX%h>ngJ}5r?w6>D5BDmPnf0+fZS89d<hde_h^;lm3Tlx`VNd7CZoZng_Q%X)S7pI0
zUKO_so>QK-x0o8&6Ts<9jOcz5tnz4Ga?d`tbhSTt*M&@jNgp&WM8iDtssKtCrNx)M
zne4Kj^_t$jM5uZUNvakwt@1jGH+E{coJC0icPn{&m31;+S|gd}OM;*4eT9)nEn}r;
zsPqWA_VQZ6pHEs>8=j;eGlFZ60}rfabs-%t0*@+~?}WY)CsV9t<AKAykRJr?9Ln^R
z+rLp@fqRZ>b^G9-(4&8k*bHjg6n<QeOpsRc{zr0Ze5|((458mG47^FG+lALoQ)h@B
zww+e>jeGib&_Ovv_vwPIq>Z_`95Ad!(%QN|a;m{Kb#I%q4ZPT<eR;8?7LsfeNmFaj
z4Z^o=oBatx&02`qVIj&@kiEsrNtV>pCZR%1xm#2&*3T6tp|$LKTIQF@MYmbl$Q}(w
z`eWZ{1hQ?N(Tt7Gy;!bfo*Y)!Dts~aDYMV6EYn0$yBk^O!@lf`>S7x4ea0VTxSaXA
zXA7Dqru}*1qEE=L{!HfSl%YZlr>HQbUBImeVR(HA|2Y=py4U-xWgmJYs)ni~ZyKFg
z<699qZYC|+&2)#`QOF@uS?lHp-6DCHF|FHYEj=5`-N8(zGlNiXG6w=B5q-nk?kCKw
zO$!Ac+5t68*&&i>-1d>589=>})%h{k;A!qw#o@rr-5#d}zI@3TLV6h3$;O`N&Ha7B
z<L<_HLd{nle%Oimeo2J0jn!_TG*$~^I>74V-Xt1D3g!c?QR>!u1G}d<&=b@QAp>p4
zoD7f=apS=ocltpibu26Km`7`4&h<^PKK(L4UI~!&o%u|QnEwc6?lrhCsB+xNy@`=~
z86jZIH^#a@lv7B&O@ZrCn{-P-k3ntZi@gnMZ{v;fI0>7Mh2W%PR`o4=`sQl_y^S_!
zx=Lpqh^DK&B9^|y^b{|$$?4rwp6+*IPkEl6vM-lib57`v#)HB2nLfkLEe;YPZ_3NT
zRxTBfDn*CUY*+PK%gzU^OowTt!!!nU{yjbB#Q*?qI~G0QZl-6714$onzmK>_0clSf
z4b)2f4pD{W+f!FEL$b#0Hg~Rhkknr=x{vSl_Ea}#8e6bz4c@Tr^Q8DuUBxz9OW6G`
z6|QEM7Z^sLN>!Z0?5YBd73BM1`vn5AP!1I<kmEUsF2ngNJT1^?^1_zgIiD&StP=Js
zwDU5I@AjcCYuQ&lAt08^aMb_#JnudidV@iRr3)RxB`@4Vcr(FIVn}R62vsKi-dYp(
zMYweif0gcA@FF~b0U)=g{~ZSgFe8Y7%Q+yPf|OZbrh6|XX{_s8R(v0gjdgvOL)Pi#
zsUGv7>zn^}{1a+TqZNNl;@h)O`-6&lHqzKwEi-*^4BHHYTovRQ>uawXY9(B;zi*s>
z85Y;V5JD*IT#CY%X(`~TJ8|@zyGH3f4uYRB3t~t*o4CSO_bJ4KRKUhq2Xn16{7mk8
z{B?Q-n`yTnXD$B~k<ydQ27_L6)c8{6Vo0M8*YOHe8SZd$F9sCN95r3pU?VMWyTD*!
z*%x3lzxif5fOPk}c}C^w(VUd;*KhSGPZxNQ#IJw@DV<q$<VHU;i0z<>tS(b!g}tTe
zSYK9=^Tdt>R9dmV==`zyd0o*Vsfs}$aSFYg2>KLD&s(fTdnhwj+!Z<48#sufb5@}F
zY=-ig*3wy0z&st{@Yp=&JoSvjLe4a0H`a>y3(_OFTl2cS)Rg=3l0ix5w}|dp>E1HW
z?Ny6AUSoMBi!oTE=Yt-1l>!iMvZ{WQ0B^qTKBQoEv+|<jsqY0bM8U+<t>xF#FYeei
zV8r39%7Tb@9X+Zp3a_s<UW$3oz!v#ezuJpHm3tu*E89UUr1$wrh486`#65#hi5=~-
zmOjAVOh1ymLNP6oaou}JXb0SzNMyg}-Y*r$Q^?UkGn$i9SP5-g>M2K@dJ%szDOri}
z8Yt(3&BRr_QOzSnnSw9n8v)>4)L}~QAl#T`&3IF)Mauhf?JY-kGA;DhDhGJhYbEU6
z)VCQNH8x0lV!<_%7u(XsiDQHeJOd8_@6LGGK}NU;<DV+ew6UkvsqvRekC!-EZBlq$
zP7QIVL3HMdcF>g()%Z_L9r3DJ!F+&t+?v<wk!8QAo2LGZ-8y6svlf2~&A6)|QGxo?
zkct;9C5_0Tnfc3uNRL$jC?}?-guBp;OL-q}tQYf}I;Ct59nm_BU%U~!tU%pn4IVUe
z{AFK8vY?TdCK}r=xt+3ipEgUsedqAIi!pZhY4dq|qp4bEsQF$<tqEygP*81g#80&p
zehiT9vkMmNVr`aZH3NyJv~w>c!%%N9xxdl+IeN_i{xCcj5-ztKhP#fu;3jx(=s6Uk
z6AW(`!scB<19U{f?R*6GgkF}c7o7fdac<uj2Sf#FHEv14!d9z(l#Iu)Jb5aWNBL2I
z>w|<tuc1L?3~@6RM?as%oTHIfRuJ9?v;J3KYuO&H13qTrIRDTO$9C~erkvLDJ1ET$
z!zJtma#H4Ol}TUU$b&iSvUicC{%7pi>DG^%*oEARW@~7MFp}J<FE1#t=|fG3TkVYD
z&MTPy2^CbDLz6Hg(wZre!3(9>O+h3DVt)=tPFu~GrV(_CV&j{+-(@yxKBk<oR9et@
zI!yp9>B5pWBQ>u@+VCx9ww&BT&2%=148h2I0T`TK>|mU73PD`qi~LT9a|J3<Gufdr
zjpVas{}@8E@Ljly@N$}vpV4lQ4*{c|ovPfXNniOK-^NZ=;N0Y~rp{Z*$AE`_UExtH
z@n=d>3BGyGnavR_q`)R=(m`hI%q-ecng%iF0cyy^_}ItR`!Y?VNh3{@78J}{O)3D4
zSY$0tVk>2;CC7weG>M?f)cj9k?+r=e)Y*t`Xo$i7y6TGrtH7f-IrlO4_^@{OvEej$
zcov0#jKL~9liJQHaBj?G0BGWF*Np3TunKutrLmS}=a~1|8rG)+aPR|AI2da5pb+!S
zz@Adni$_8+PK2@&51}t%m7k8xFGorVX7vsLkUP+DiYXQJG98R!jFbVNZ_Y!YF(aL`
z^9UL)1t7%tD5vjve7|S}5=RKjy0RUnA*z5>&VQX_AT7`!B>Oe;xlsrOjK}opDSwHF
z^uEGO><{-r5I67*-;FG$a$}AJsNujno#jNJCu$Vh>Fv3^0+XiPMfnsfo*!91Nq8E{
zJ|k&OU^!#&0GS5Ka8oW|CFJyxAGw^foysHP43LAD0#6$fyiXT0G!qdqPQKCm8}ax@
zzMIQP<FB7-PnVL)p?a%YsO!zVS9>Uh7G)2t+bB_Nw`TVHcs-N5RYn=lmsnSRb#}0k
zNh$jckJt=5&#F!jD>!^jU@nbe@;;h0l#*9dR_ca4Sb3to#n_`*2oKo<WUC~_-3Nz3
zPqyBs#{W1s-Iw`1*2__W)OCzDUxeH-C&UJZbj!8i&~W@jJ)yI+_hM7))B2nOQsl27
z9^sH<esL`mEnh(qQQ{W30cBdVbicKD42hc{iJWW22s-m-64KrIHr(VPK`3A(ZQTGr
zn7oe}q_qUi_DeWV*(H?7`c-AU;v`vp%zKmj78Y~?34Kpl!(P@>W&H~+{7kLh{zreH
z+naA-R}+Co%`RjB2sVM)a`!Zp6rX?S`9IFJr{y-i-IxAfxSqNux-T)>X6Czb!`kEz
z&^hLh*zApK^}ql~+E}lrP5|uUSz(@WBi@z840I@A8t7o(`LgVIcz30;wl}Kpw>7o(
zeSq>b7T2+HFAylr5;b0@z3q&(4=K)!XM5h#%GTnYirC!V;f<Dyhatn$xlGX7(gXDC
zd9kWA*?UY6u<FmHI#tH^&_ts@N?Oa#rYM!2`gV}24r!q7B|QFS%+55WykI_voSzy~
zBy_ZGsqgcK+x|WVUjW1&XT@*N=|(?%TVcijg}!gU-rjcwjiF0bq|f&BPxwnTVjF+_
zixLlw7?yn$wKuhWbOHiDQ|n9hWdY>D8~dnv%bvHXdFO-C$M5-_hXeaqI;1x>7|Ilh
z9Ma?H((Y-!?4{n=pV%)o6CJ{Dy;6I+4m*IPWwMUS7`f~^-dQ2^jPO@0!n5-&ODUpJ
zUu~zUjZ_&CGl138e#-aXl9(bj?8dJ^ux3cm_Ysor9{KVpRG4105H!7M@y1(_-_xPG
zS&J?Sdl`B_i_P_Yd}jG?@`B0B8YsDkK#MI1@8cev7jMdlgVfXL{T`XpSHeFh$+{bW
zPnxwxSvR+D*}Zx9mi8_G2tY$T1LWMFL#XyW?S^3O;v<i<6a5$kttA0|L9CX+PoUxi
zSemfe!j7n%wbb-GC_D#3V`xJY$8;w4vX<S3@)|qpX;|t9?yt4L!~Qcf=qw#go1zyW
z^BPIbDG~B(lPuP_6~B;32K0%fozf>V<`hHNKTGRd$-o6Z;Y>jUcM9ly3d*ovx#oI|
z$0lWcA5v9lZ1BKD_zcI51=1je$;pcmFCj1xa2{shDE=5nZgU5*H!(gjMGYw!);^ol
z-r#&gF)cA)FL2*yV&VI1B9<lc^XRbdV08lEF7(WqvsC?&cJMgU?Zncd@yN{Vx^10q
z6Tv-d)@W&y7-Kj9gz=Y|Z4j)3?U{w0cm>c@c)k+CY|4<OUYn$7b$$?ylE3MU3=*kM
zLL-nyUKB`o9#hSeHMfC8*a2G1K4>3`5LZ+60o|U;-q%W8>vM^Ub^ip1dg2irl@g+U
zTCOL9gmiNIPtvCdEYb*?i8MGEZk+jPji+xItu^HA7IOk90^9x)EM?{zC!^jwOcp@F
z9Jpt;*EF#w#O$>d-~?*gXf(g~GZ|DUz0k4Mn|X6<c48>6K>mapFh+jmEcI)wvzDE%
zL_#V*)5V1&4FbBL7ur{eX=iCKQI8rXn?_Ok;*$aY1<iDP=HX~`-+$wv5!gkZ7#{tA
z>1j2Mz^Z-dI<2A{ct>WC2<BM7w&IJ`6V;Pg+tq7zZm?#c8=@?;-ufbEF?FTNx;TOf
zXEfLY2ZMdheMX2cMVEY<$6>E9<#4x)MlvxxmMJ=fav_<o;_<&B*klnY!41F+ch7`I
z_KWGTlBvGlwQT_$YU==HLxXnfni1q{?o(7B&J<+o_6yof-N0is0QXXiC{$W;dM}Kc
z$(+%k-K&TuMhs@CFu=39%mgBJK6L=+oijZ~Vk=6{|7Gu8z@w_ph5wmkfB{DLAW@^n
z8Z{~rtVFRgf*LLZ6p2P9UO}zZ)LPq8m?7F42u`BxYzJantL?FBD?L(cg?cQaA|?cr
zpojq?HxZ*!ongFyMDCLB_pY_~%;W-Idd~Mh-}C%=9x{9Fy)N&1*Sp@^TI*fn0@DPX
z!PYKPGIvC~z6$zf4k-$x@g%)~CQ;vGGf=3cLLpMIQ7$5fO`UU&m$LLs_NRdfP>RrZ
zs9k#I3{-qRL;@=ma1l`EW^p~yIZo16)ys;_5h;yCGwR4Q;@Q!ILM??9OxBk8-9YhR
zVRZ5TCT`|vWARo=O0}a)vc`A7cNkDl{4=DejLbV5sAdrJSgI+MJW1e2i%>;P5s_)W
zwb`d+WjflmpFxYTjjt(xL&CS=H6Z{^!JP#YN_`(NqC6H`;>b|p-a0D`JkS(g_Rc26
znv%^Mmu;v^DjUXqZv)wu_w_>eqsG1WLR{}4z%*94>ft}?PHw`5Ax3(uctr*$GR#*i
z%G(D+;Gr)VjgUi^zm!qdJAT2}IIGAL9m`TNQ%FOSF98j1!h9>_<s>{|g+{bq>vR+H
z376+|F8&NJH`Lm~{}?5a6*%F(zwBM{9z3Iu(1AUfWM+W)P+U&wXv8Ou(!a1tHAy5z
zcG=rDAij!m&VQqz*2cFCj5-QQhKZexI_S0XG00seINNIFNzZ!O13+f6{DhE)Cx$?>
zT2v+pS_!;`N2-h-I1aq<9>@V447N>H#e~>bay_&UTbVPDS{+LfV(CzmiK+KPDnlp<
zOBx)W!`}&s*)s7oyHm>#u?6B7YG7Cj^(6AdzJw*n1d^><b8m)n!+m!NFC{P@3Ei~_
zEz_cs7&RRS7@RqR|4O`$9BWZc(wpZ*i4v={F?t(uB-uqFCx1Ll;;5%efCoZv?4mp#
zlt9-29;rQ4xyU>}-bd>0o;iJ}KgLG@Wan{-PlG}v02=#ym~QIO%3vAE8Dl%+<1vPz
zBR)QX!#enw^Du=N(;<P-g&hob#nStzCMqum5(hc)a|A3YKo!Fo{y|37QM|(94lw@l
zj3i)t(2}H-fEE9{sM$;vry6I<jHReyWy7rE4+zJkOPpt}lIU-VWzKnz<ak{Pg-Z>&
zQss3d1WNMHy+J)^sUej1j7p0|7<F}q=H92WT$YSCtK<F3W~>myH^nOU7t{{B+;7bN
z5Gr75hN4s1Sd@vAtI%REszkDs<7=`QG&*|6gC1t^P_nUM^>>~~JtuG;<QiPYarX{&
zo@Y4u2-@-%a8Uhdb4x+HiUl!1AOrkC@~cLa4FS7P=gkoHhGRRH8wQ(ATiFa_PQN?y
zayULpQ#l+ZkoZ=g6?`&~{+~eLYJLasJ1AM9oAnAJnttFWrp-`t5195CJ(M0yp~4Bc
zAh<wTTniV=9xA#rZJ;{1C$87g3}#{C2*)2Y0PVRCeh7B01nQ=42bMxr6@4~?e)1~3
z@mg&O{Ucao_RgM1FKBHz;o_)K7TZHax!A?|o=nhFFVlv80520l&5dk&MwdZnF1^X6
zH+lKnkK4y3A{;EkV=fCYT;(wB71cPNRO!Rr_i&$gco^;$)rT`AHhK8uWFLBqz04WG
zF7Rt7`4sb7KecgMOz!-htj{Ov`0##f{DJ7m1M1-1+V?q0X%<U_WPfD2FaArW3>Dk)
z`P6j)*^6N-GQhc!z5S>Aa1Ti!O@H9E>1`$~?O{ro*#I0_o_&42jaa+9K99)wF)q1a
zOnHW%goKSneJfYY_L|E=M^PIo%nBZO*C)J#^Jy98G5R!Ol9bg0V$_o!k05pPhR#R-
z00~h2G^k?o!+5#U-p|R!{O0f}(cuq@5Q+YRb*TW+8isiyamL<b9Tzx0+&{2xYUhaj
z$JJUnd66bJurnY!O1~&#cK;v{QMWjX+DE!WXSiv4Q6J_!5Ar6wV`qI@{>aC2@Glpd
zl?zb(3L|#|s8C0-KRPZedUuWg#auymFY`;|<qeUYC*^O7?C)b9Gjr^Vuv1RF<ZlY>
zoz}}LJ7BKn-k8;9<J!-nmmF>GTidE`=D4_bgCf@<dGBy6o`z_|59nD!f`rDc=N{|5
zQ^!UUeM3W*N=pUp`C9^SOz&ltAK-x8XY37qi%V;Eu-j`R-t6rcbBj-`_j>3<jzcA$
zQtwnMD=+a#<P#4ySyvwjeU$h|X^jd7m;I*!gvjRXQRr8!93GcA-8PdTtJo_z#3LVj
z>>TdUR>?L|Q4Z5Zi4Af~`IrZ<x4Mffd?~Mn%Bvsf(j<!|c||Ju><Cxvv&jd!7EQ{E
zDi-xzAN9N{#Y_a)**dFgNKQpn{ZbfgGIL_Jwl5hU0RxH_ub%>=T$S`vNL|FH;8@K<
z0KIVFSf-PLTw<=J|D(Rhg$kk&(<7%o>M2YE>d&ci_O#*nu$M9Ovu}M!<X4{FGfyd~
zjXfz6g`32(s&13s^fz<VLu5IZPF>FsEcad?e;q%&_y>6IL~jMPOo40&K&Vc3CTGRO
zMHFf8J@XiA$jeeC^R1MC{T`J_6ubnNb8(%}2T{)-sn%5&%dBhVBKW-6WRfuchR`WC
zyygs#c>`d?`U^U3KkgWeb1IN?t3u&fw5<qF_|<tK0*`mo0Nb#(Jq##y`!b_h{#pBS
zfuYQddK#XP0*Qz0_97oofCUsYU&i4v8~{mQL$B0nVtP560TI|^J%C1xH;V+!U=W+J
zSRQPjX|7V6vRrka%H2jiWxn`DOB;YPGl&J2sm79b&5dh6t9qN-a*WD9QXYC3kjpOz
zw`fsxwgGEDqSBn+Z!%Tx%;HGtKDSw%ecT!@MIvlLu|G71&y%9RJ@*aKXG&Zzo=5Tg
zO`JCD<{+=J<TZP-b?r7OofW+{S25=Bi)>}Ak(oOQZ||(cIWS>!vWu;a1hPCf@n1Tg
z2Veq&4i64n((--+c)1D8-(pSn<15dvkL*WJ=mlzw`)}qiabSaLr{y~+*GiBNF)GjJ
z1DAlaE94qqG?>LrR*h%?vXx-Cb(J5C503r}uKBwxa|`d})}bNh>mXk)8_9_*%Q9EX
z_y%E6tR|e4Uw_=XfqXncJ~nzHuX^OhCE^TmTqA%|0RzbfvpHbKRkmUniZZu!5fz;i
z!JmV@>}jW%Z<_DaSlRHq{l|SOs|vddK8bwfHjmef3xmr(u&xs+h5$ScV1_GvXi08)
zSw(46kfV1fNJok+91^huJ4Umrlo%L&v?p3lr;hPB^tH`H6;>bad-`6Waq4ymN+66q
zhb5sA6*@{PO0AE}=k%(L$m7f|Gp1?$3+&?>(vE(o$44!1F|ea8&OjWrN<4%Kh)(M1
zX5&hr-dTUC*Xu7AI4%2)%KK>x1&x!6Cl;(x{cZHr2ms=f`#da&<6@f!vgGEogPeJe
zmJk7eqg<S&4&C}fE*atVI~d9w^9>m}^p)db^dFe<-uumL>jIJC%RFm8W5-BV*;a-l
zJJK#zU5+_4^0p|oehJKcjo-v}zXIA;Z**`|`@RM>-DUa5^io-1UD@Y}Ce2xOd;&)w
z6-|vjN7fB~>*xMJ!nprjsLza<@0i?}aH4D27|}-xjmK&+M>EGLS}mYKH3XxL%FpQv
zoh{^y=rX!UD23PP<ODX$H#hQ0uq3e=c1ABlpgxur9g`K<8x1{^MWy2)*CAw<BXYy1
z{aleUdZsl%NQ?)zMvtTFp^&j`NEyfOkW+<NQQnkN=jOQ|PdIF{`!V~__UK6tM3!wH
zM4#)YRk<N$4W>AOBpTxI>0S(up`OI=YCvWoi_>yGWdhinVEyudEP}O%<@8ZuqPGyA
zXn8%*N4bO5(MCnLMu$O@b+kE$|86I;S7TfP`)c|}e%U<Gjd_BvKw?hj+T;p%Q9>xC
zzv%H8PR+%1_8NLpY!&*=Es@5ox`VR2LY9apvPy>1!ub(o37RVjw(OlQc&2jEEAlMQ
zLxLn@L5%#lyKiBe<TiOhN;rr@57@|YZ|b+hTxIU$*jm<oXh|rxgQU8di_Fh^Zwj5J
z072CsR_ra8rFCh(*ql_8#lb_CVZ@eFGr2gje7MqTIYuKdkxl(D!k~}F&;^n+I?l)b
zBh#11R2TbH)q}DY;cyKCKK2_t%<3H_?-PFxJx|PmBNa=x5|7yZ)A-2&H?nd)n5Y=7
znc=d!{TT@8QtP~jw~6o!_l?h{kn#sM?5cN%2d&-@5pi8}__KxXSPVCd^<7yzG0CNj
zH1pHg`?#sd8)|_bMX`##rziTWp_@sWpT%~NVfFs-Vn)oqPRR09waLc7l*?RoWhjF$
z9XF~ZG(+M|)q;xe>;M=#N5A_SRmQI;Q$c%TzG@d&`j72)&7Pr{o;>ku$O0Mt0yQf3
zlok;UPe@-w4LV0+fvx1I`vQF++;6G-@r<RgXE(^n!ALZgx+8lEXP`P=H<N9fxq%I#
zchz-aeA8$+Qf^3DBpA2#X*LT%CRtP{q~qtX3eg*)lV+<REK?;2i$8joCvb4u+4-xv
zk?^k1>ORY0N37-ho$0F)F1RneGwP`c)K5Q3^GB&$afAA@oe)fC{fy=$9;w(1#eVbk
zy8S%@o9^y2<198vnVZ7js}YTSbd5h+?BNc^-ih2m-LxE;qlEtm?NoiB2i!fm-liAT
zJuCEZmbr6nV(kZko#9Q1m(uiqv4=*(B#WaWm?o*sE^0yJ16%^U6S*i`8#&aMi-O~i
zz0P|?_`p$Oiw+-%;H_(A0X~BavM>scW}NWO2H9#fIxml8Ze;oBEjyBEeP<(|@|k3O
z8X%wc%BQsX|6*Xy2SdR+QL_O@u5}VKdUW&>ui3PFo9ZFqc2@7pf30AJoC=Z60d;P!
z5ZTS#dYLsOSL|W&>ch{76=3rj@L4RH%tWL2j0>Yz_ZAMIhuK(~b+-1MsYN1Fj*ATD
zvo|&s_8$0j<`&B4m|sLE7VOSs8V3?H^5GThDJK_wFh4t&yMS`htnUWa&U`y!i=s3I
z+~IFjMYkrx5{8ZOm-mGBi_LWcX7q+EmLh;7wp!L2Kq3TDOn1bH%oAP+znL!1P`R71
zn2&kU3I7n0nhQdfWg(8KY!GQ3U*=rof${tWM4UnfenI@Rc4+(V3tgGWh`PAH?o+>e
zmARML!MN5*lh~0=l$ukxX=<p*F0m1*vTT9Sib%;2jsrYU(czB<_DmaMog>xnoW(uR
zRG)L4xiMJ@EkuVDm^-908Yoqkd7!auB`T4ySK+DyV6Ut<@F1OJUwAE;eL!tz)M6&D
zD|>xb2oVEbbisN#*{I_H5yx>^haf-~pjer(m2)INL4}BgB*;rVphiWHhhK>d6lwHL
z^e@!NJu>sw8qp{O6`lAX7YusLtUNj?6A|)=PW+=QI@JSCd@RY33BY~Uq(90=3r{ZT
ze7uos6VdTr<gIu5D9a;zhrG1o%WsYr?yrkwXfeUfb`$T#T$k+cqxWn=4q21#6(O=V
zG0c<4HMp|xdUO>R-<#Rt%ksIjBLnUl^oM&j23f&_n=JP$(Ie9c2b6dE+qAZOP1KiB
zP+P|>eRXat>t0*DHNlRki|b~zyku+>Pp8d4;dbJlh+du*oivNf6a$;4oe;T;>mK^D
z<p6!U4_+)o@BsT<TekiBdh7dH#*!7+yPK5j!=~?83-02I3$qjBz|2tM;b1FJvykf~
ztDolC1?W=aGosgJRO}rbJ{G5+fT4XA_|ldUlVEU&5M?VWUWmczakq+QX)HRw;1lz6
z!ndAlEE;I;0NvSw19RKZ)kamZGy|*V2)nO8f$>OEk+H~ktoc^uitx6mZ=kU#-`r*_
z`n+PPuC?+^9N=bbI7e05<!KeO+E{c<1vjjJ!JY9Hi|xigl#iOj(x$TN5;@#6&a<>H
zgSn-EU@`p@J#`JnqHPr~tHR+=haPKGuEB<9?e;B7<VuN9Uo_vhh(Qbu<(k_n<Tm$%
zysy|d#i;y(2hLeSr;?RlWtRvB8Tx+V9??<loXe!`f=@6jt3+Z!COIP0Zx^#E1T!Y2
z#;3FiK43FG@iA2Xm{r1v91p!rJ+L<4R}aiYD`4)2<k_`nRLz&JZZWqPtXaJ$)C&Z1
z2xu?V9}{OZ%}nBQtu;_%&}B~X&*;}UdUh7_S-k0ijo}^UrofgN#!I<?WNysgyLP{5
zO9I5pEUpO=TqCEH-46XNA8y7p^(wJzEV{}a{TUH?iAS*&=qvV}<zT_6e1#XrqBX{%
zYQZb~;}?;=$IZMWTEd9^)Xmu`W6|H$7tpYWPDH*u&Y1fd4-NtoJ$N;9!0tLA*%OlO
zp0dqfXe8<*zC;n^c4o4U@LKwcJ2sTDd!w5%ikFKWC4-^{BmOg`<Bn-BSd+gYvZvP!
zrEjd>LuI69qEF_<j+B!NYhX7y!j?xX&NHZ>wqmB+73!z;W9a<uW8G|k3%3P!8j%f}
zg7cz-dJ+C=h50U}2EcH#Ihu94_*3@gMz8hgcwv|##-a-8Fz0C2w)S2Y*gfr70=p5X
zdr{8|g0AqIOz6OTJ+OOf+<18z`?Khf?CG0mei~`;;0Rz?at6Xf>kej^Q~lO)=I*+W
zdgM29IrrRq(Y1{G^Y~k^i(+zuE_YbaYs`H^=!-g36kQA52S-l%^#l1E*l)}kDpbBJ
z`g4x?oJ?2rVUD;G+rl}wt!<_3APxdlc^(L5Mpk7|cTWC(v|U-dd0G5qvD+{dXl|mM
zNT*dCBc}=dI7Hl!CKM6N$+HN7;Vak4!y96bOp+c6jhT|l#gE;IzWA2?5`YnE3A>1~
zAuZFkXZ#t4v$Q7G*US3G<s!osJ(^#bTNv?NN(dFHc^|(N4b`S!SydiF(jbV+Yy_mb
zmxCyRIj+zsVd^<*!e<MWIn`WnDa&7dDWmW3pmNxi=SZVU7Ppy1#v;bImWUgCaj!BK
z9cg~<u)xZrrKifHYrkT??J(CFi;jvv4$RokGE|%gm)ZWP)F-q3A|7IYreiOQF`>_z
zr4S=1Ga=S~tkcBqmRwJClgsX}xytEA5*vjy3|e!{E%^tP4$nr>zd-o;s0b<29~76J
zQNk|=2r|&Qj724`xE!FDcf4{XwgJD4T9QYq0Gj#lqHqa)0OLF8MA(oQN3Rw}l%wd%
zTwMy8L0veB3B}l>YIHO!bRzfeh@s~xU7G2FvSLrDlHndpg~U{s?JD<SgRt_G8<)ji
zOu=nwTwb7xpDX0Z9v)ecT?CO}h{*d`0VjH-e<|0Cbc_zjo?{_IIsSVMT=M0c<-IVy
z*onOy{Kqo{ZIh^$112|8ZQ@A@ktO3cOOKo44{XO#DX3gL64Ghu&8?hXj^|S<I?Wxw
z0ss{z2C8l3M&)*ps^FO7H&G<-d<N$HrR-Y3gDBfvrIuk~|J~WdfDB#87S4Za7e9`D
z2`+~>K)Qt@LtdBEuud#SI)v9CS0c9L4jT_As0U#$pG=ncJ-Wf0L>9fk+xTDgHm#dv
z=kt7d@vywWE?1j+nRYOu_|L!q5^K(8!2~VxQYpTB*xrGg>Q!FvZjj+(3z;+k<LFz!
z>J$-e5jXKZcBAp$q|6-%ZTMsS_t?&Wu37XjFatBIdKF9&>5}g=W#hDPh(R1DmhLsW
z<!?MFIoKgUTMx@%Y*Y#E2WyVcCap#@gMA2?jHkbRij<gRLoFVtNgD8r0UR6qk8!!a
z*4*fDJ;n2Kkgipuf1kw(R;m9b+a}QZ(ga&of@w0r!Nn~=cpE|Sh!EN%(t1)f>j6e@
zI1F={EJ@xJoqB+oHl%Un0U!|{r?IHmO(4)C68%s_bb>qc_T|=0|E%Ip_h6&)4DiS)
zV?2f8M*=~5B~*k<y|L(WcXR~h;iOb&EPBcoqE&K&mRgMa{=x%3(Lu(X-;g76u-D9+
zhT(iJt(kVsi*O8=^5x}!Zk=2Aen$Rk=G|bfBVzp!0v`<IKIZRW^G%Uom<f9=c5$rz
zm$|Vw-pI9|;@lfx-hRM5r|f;Q55?je44gjdzs;;$DzzK;UMu=V!c$7@N)SX>fQ9-8
z(79Z02dQ<-!}Q&{uMbOxx>T>K&ZM-&u|Hb6bFh~&=O;X{ym=ez*O3CAX;0374}t&m
z7fs(UCeOxcpPR2~RaKJ9rtJi7oXm`{OpqbiM7J506;hl76|A!;{d<{F`BP~In_Qf}
zpW)$Mj0U1F0ieA_#Tn6Y85R4k3H7encc+dUSaD}2I1UTZ)Wv0k4jLp*gvdef%>GvY
zy7xVie;H<7@3+i>@nSLwX1F&-ql8smg%Krb6YHwjokg7defc_!vwA?i;P7*a8#Li1
z=&#;o3XG7-QXB{2Pt<y<<BRSB;&LXi262f@<$v;rff`=*HseX`H#!GR4pAhq7@*n*
z;$d7HJ2mKn_r+IffCm^6i>H@mIIaG#<nojMg}I^bUm5wIF_447Fm#b^Zdv;wM$kHQ
z)7ovrggB=hF#S`7E(XhZO}j6CIkm(}DX!&n{7uaTZfg|ji7AwZZM5JaR?qkZO30*<
zE6xx0GK<)W;^I}j6i^wtn?Qq^p)e5N%lkBAoyQjjQ|pW0eRiyCF?OV@X7((Z8yGHv
zO(Zea(8vGy!HZ`|hU3Z5?e`Hc<{s|*&a_42_R~V#r(9Fhep;pdTVem+Z~xA-e{*;0
ze808RK0EETe{1dc1MIZR{#|Up_t@#D?er~n`hcBovwyeSzs>gVX8U)g{p+{OZMD-a
z_U{J!cZvNw(a!g<oi4W1+4k=s`?tpao@1vc*uUfK-<bV<sGVMJr<?5G!S?&n_U|P7
z_cr@?xcz&R{hMX~=GnhP?B8qb-#vD{&)L5p+rO>qx1hG3u`0Cl4z|B--=W9GWv4y%
zZ?65@W`Cbxr^ng9h4$|O`+Lm(_1f=0w$nLwI?MhYV*hTnzYn$3gY4hY_OH+W9bo?!
z+rPu@-&VW)9{YEq{XWnB&9;C2>KAgC`)Fl_IOwyAyeMY5*3nI3nym?OGx&V{#8sm{
zv&g%m{eAdFLG6nA74g#tIQq3+{s<{$l?cZ){<K)i)rNd#358l$#BV#Jy?uo}M^ygo
zSk(wt);)Q5_b+tC%!>}{&wNwa(tf#|z2d@g?y;ELM>O_$d@=_KZXW9*7lq|@ENiPr
z+WMfehkO{Yj*|!Wm#hBek>^QuV_dP*X`(}M?lGp{*^NEsUp>|}UzeI7IS+8Cp|Qt2
z-rlC)-XU*4<n4-jUB)_MN~;*JVb6+s{0Fo!0XPPQbRWr6ap9e;FuTIN8hXfsyW+wM
zCoK=8v!z4wT^>jeaMJQXI_Bh;2hxk3v^<b*a?<iZ`e7$652U?LeeythkMms~NN;e`
z@<4jNla>d!GX@nG&UW6*1Nmy4v^<c`b=r{!(u19}Jdob*<d+B1wN6?dNH;rac_96`
zla>e4ey2WpAnkI}@<6)P$uAG27dmNqNcKZJquD6`rmWz<0@0f|^GdeHhF>CjDmSm1
z=T~P$$GeBOhsGI;w#$<8l*pc3qw;z38gu@{UzQz=%4YR|o2Onq;BlJEgGt<gqOGx0
zrLtvQD;s}+mo;XYr@G(ltFzF{4lWCoptP;1srDDjCbOAqKj^(BQrD|;&7Ge_hYU8$
zeAWKhS07z?*gSsii(XMLb8uIDJhHE*aje=Gk*MVzbAaoc{GoxdZD{J;ldYlpJsA~L
zQMO*v>+P|hBWBT3ZlnTS5-~epfs-$>u14mD!r5@M(d5S0qGoHdclX-NYq%<#OMs@k
zs{4<U&>u5#Sv1)FkVExL=y&ziSvcJeqC`C@s3GERugE@3B5}jc{5h&hIO_W+&m61B
zyv%1^?Tv<8#ksqYR~D|)V6)tFUDAT4mX+6D>{YS7d4npl)#{1bt8NC2GGzF0$tM;f
z<=cz>#Bi>hM5h+Iv5av@LB)}MnIZmoLOo({VO2zZ;+3Q2L}h7B)b~B&h~7zo(wc%5
z@t+GiYLg`u4pij*AXlK(M#{bJva_r!vfzuyM6byOY3*yw$zIt|wj%z;J08xN^VWH>
zl^52?9Pk}G8Ehx<nPa{_9O{V!gjuxNSk%O=+>!T;$X?%cZ|q!wa60GKqYuyG+`7dz
z%xpLe9Sc?>A5MuJ^c$5cDd=9!72p|GZ&vnA?of^_&(VFA{NBW>n#SN(=_H<~2D4;C
zX$@m#EZS%8(Zdzos>dtNUYe2(k-aCC8Ig|)Lw%Og{r0sV_6~1_fD^NUBfXyWGUl11
zWHe{8cdJBIQhVpe=5~%AK=36LHeLaM3{98D^XmB`Ue`qGGb0}yP`&8{GP-)n=J+5o
zX};QC;*EV5TVBw1^G1&=u_O7u{pg!6fyesoucOshHAYHyc^h5XZy^=pAHBs$sQ0vG
zzeMg(j~dI#-p0&vWMuea&)w-^^NT%#3zFrW`Xt+m_*^pS`keQ()%%&r{Hh)GvQs<r
z?RMtVzhpaOljWTHB-@I3L@?D6&X`?ZHl`=b_v%t!vaN`ZN|tx(z3p9jzrMwRU%{zf
zYB)RQTktjW-FKLL*?&@E5wVX*yiJDdw4Y(g_jp`HDM{ud<A92wtm>NkdK69?3)c$o
zvNEiUOf-y)M)gXlSLa1O1GeR|j#f3V37s#b5&5a|APuAyaRbJl2PX{m26g1nd)u}V
z;-~YpzQ{0>`@$_?U`74NkXKTT<1~5w*Lnvp;2{$94p<SdSes$%LLJhI59YxCta87Q
zP01G-uExw5szG$x0E}4CoUo78it7<?WvGR!9YtIRT^sJ5oSWva23x@_bJS?5;iY#o
zTn(eX&;Ri*YgD1hwTj&CJBp~UYAwjQ+F?|-Ai}AF$xPAKUAh4m-2j)JVSAzN(6GJQ
zqKlRs7PgbVJ#3?G*lroCV6*3&Kz&LQEX6K0{dI=@%bkaY{htht$cW!hI2>MoxaC{p
zbvA=44a^_YEna_c7}$Pl!}jGRhl8#0oo@}>$6!xj^J&=9@cP>44$9K-%J)2|wK22l
zZO!MJK}&Sh0HOYJXn+rJhUh3Ioc0vhJTMO__P1sacd!gV?3%&0*yZH4f^9l`q&|m%
zl-CWE;I-8Ds~}#mcWvI<vCT=THhU-AluCr(N?S9jCe_xzz+pFSU6*RhICNXvL9N}t
zKT=N$V5hDA9oo99`?fyi5;(hGPvF1N{YvtNTi)!*8|-vv8vgzfnY2G(eRsTJN3$Nr
zx4wTkI+?cnThqygBXN^MCtHyP-SCFL`wk7;Uv1a|hlOoD6Z~89t>HFo<1}n(G<-}F
ztTY<#jMp7~4-Nb885-$!`MAU3^@MK^dj*3k4ctGnTfCMW2DZy>*xtj~JG4BQ3G?}u
zc-;#21h(xXI`iD6eH@gf;Wfz{yqh&|r~xhZ-1z}C(3t6MP4b4#Tw<M^uX9(X&)4(F
ztLCd@Pw|GQC}Gc`8v&>jZ*bboNwxV2_|a{q^M)T%O^P?HAWt`KU6g8TXW=2+S_o?G
z{>|#Pt=)st+nU^cTWiQ<_v^l7TcVpdYRPc46yb=M<B-G*JIm2bPJH8Vn#mLBE$G!^
zY#&lD>XTXIGy8Pbi$p0Z%yo1mG!RLeLGOzAW%{HR_1SaGx-yq_t8wN?PgU)mSymq|
zpBQ2GF-Nf-2g^llN%(#2PFV<Z-f2Bl_HX$`?Fsv=QL+l?lbyvJ$rI&D9JNAsiz!E3
z09NfM_G~w=q*C^=09WIvJQUJ)Cn^22bvfYdT9v3!pzmgCQ$7|o{|DKPm-ww<c4Ma0
z*Eq_ff5ZnZ2Je;Q3_@issx1`2#1gc|<VsCL6<p!d?4(-f3vT$mS+cn?*eYeC;SDc{
z)7^Y`=U>Ez8YDK<GBq9rwTXW?{ByX#fB{&(AsY6pdmDHD#qwK4vXd$cM2JHft964_
zzM0h=FY2Jy1+fmV@E4mKqPMo$6{|589F$0fkv;99Gps9exfJmG=6I~UJCCsX%$AX%
zGvLoG!R5wq)@;MUJyLZk%p*(X$JOp`RycCTS6B8O##vdybpD6rOb&nyGIkbYyQe+8
zNjdjBd`q`EI?zf^l2*jPrdpo>poj+F0yHx^4s2KEGRxEJ(BhYY63jG?QUhgQXOL8E
zZ8cZvx3(hkw=<Y2nYST1g%(ET9umfHS^p*9tbQA+jRVq5#QPgPNna_ZrD#!++8i}Z
z{~({5!-t%g&&N91cQU6y>V3Q~P0c)q?s6>dPb&9weB|_kw^^4W0#&K$xo%Y8-Oxar
zri-Mc4C)7*R_I^aIEER=0gE($0A;Mv*BvZ1$K<8G7C3GBTF&J5vp3_rw9&I>RA37(
z-?1`3J+x;$@3~GOe24g~rG?@5QdN-qb3Nw&_B^ejax6e+o|+`h|LgPgibKy+K`^H?
zuE=FV8qc$3k2$&W!{nTNk4HR;9CKe(JI?0gsd=dipKMP|DGfHCr$nhD?j-+ZZmMxy
zrzU6m$Mkt+)63P;xSr~Ejkof~5%Ds%cKceae&cy~DkgPf=KSP5><G@kUw{3n->80j
z9$tQ0+C20u?=TOQ3S!U0eDZaGF-Awk0=?;$v<m9$(`<iaXQNB9t%wgJQzu^L!l@wT
zbJNR5x|Ek}E8_cq*rmKUC8T^SpOQYDQC-SQwiWT0lI8Whs<?173mPt?Y8kAwp@$^g
zv2}1EabovD1Y1))6&Ib!zC>ZQ!L1@1qrt5rUlC23^D>u(5sR$$aDt5(G$%g7%1@-e
zkR@A{ZLk!!MLK#*TNJ;|#t)#flCAhUFCd$8ZQMZhP7yXDq!&4D4n_V`iUhYJlP`-+
zMOj2fNXg-Ou{=s9mY3H2Nj0oQwQ87yis`kqNW(W#OKc#2&`ZX|2hbtvp^idcC7v7~
z8X<FN?5iGE?DGa`Bi2qpbn<qt`>c+24-g1FQpYN(peGervahE73NL;Y8xe96HVqM1
zNttG<cQ7!C^70IlRBVRPq+>q;jQDimbmnTF2>2onie!O`W2-&d-W5FyIc{YKUY|bP
zTvk2OKinPqbn2ktnPt1=y+1m6w*!aLtt1eFg0DKbJ0ccyeGT~%3-UKwSL7vL(eu1x
zTcws~oX(28KYUxex^Ju03hvT1bZSfV7H7@NXL+Mp{kYAwN%Rz3HyF--eQx2AS2F*Q
z;erNlpbxz9zu}!NXOM}Ll@`iM09(9m%4~bnEymTLNPFh=zT&}Gx*Yh*ly#jFzZv#1
z^{hh9DXA~*t)(@xL||u2@rx``Jw*6vW&ROWZzxC9-b_>&nNaXkw%xj<xF}XN(wsav
z<AMC2>~9Rl$is~MSpRGnEwM4!CMia`D2DRrv-<K^D1{$A)VMl7j<oh9gnNk7ul6_u
zV`iqbrYJz+)|TCZi)^brZ`kDA&{^VJ1aO(<AFdK?gbec}fqSfn6(S)hsnA&`2<AAM
zU(lIrRaS3elO8*NASjorBGaOyD>|*A$*?j8L<eI4MB5duR|W#75$kCS*?m!23*JLV
zq)@DA-^+xfNZ4;q7S+}onVlStG+ko2g-*ik0rX(2Rgz_Kh;1@nqs>+j`(~>(IZsg>
zhnZwmYC~)fTUn*O7OQAO=uGomtEAPuQq<|I+^g959^Ohnq!V~o1p|6j2zZ8tw}wU$
zY~LDcPR4V!)tsDbP2OzMR5;tDS*n3>7#tuSn`0MjZ>@>!Js4gDEeJ{ze`lTrH!EBw
z0s2uoK#wYLyopM|t4+h;kN$Cnwp==g%7u9*xS?IpGudf$WNs2YpxH(*i$$@Xb^|Qa
zw1$>17HUk9a<ZKX%FGa=U{&9*D2-VVvMXwedD#FYcxy7Mf+9$QSyrLf3^vdA8&&tq
zi|c&VK^FK3<Mw8>XoFb<|7MqCWfRR^(iq&p4-~yweynh_8E!@VsKniyvUWF$d@vpi
zt`GODD1Va!Ub6N?O|Jlo?7)18&vosxu-A(>nE~tK%yPdqdXpc{65armve!)PP6e<m
z)HbzWo~^;H6kdy*F@v>S6BxRh0bqaZ3|~e0dRMq-r1eWPxY;VovhMPsI~Q36!@?Vk
zsumhV&Ar_UXZ0TAk=>d@rIv7(MXDAHQtz9R`P?3#Cd|B|{1sQ|32VY8#$&5lRGWAR
zIrOF#UT)if(xx##BXrrWkzO`4z9*ZGgy1Krr8w?9EU)#3z7uKphK`frvx1`h(T~{J
z*EPX5g@*uU;|P!7DpiteI~G$Vu>|H&<wAGjX=rS`mj&4PkEIQ|OR?S~JZkGYVMY1Z
zrINJybT>0**C@ZAn5_^VH$idct0*^6lx<Z03-gz{g#9q-M9BW_HG$2jl4`*|3%avo
zk|~%w5XKl>(hz)!(6Il-{}<hyvWdLrHcOsk(}?v8$y<2~c`vno#WbJS7!;I4A?bu-
zTi#|ltGixn^ygV-T^*s;i<Zx4XRHKAvZ$>*JJYaw^U{1Xvz#eWYZWbF4YYrte2MYv
z;PUFC7l#%tH!9o6K0hOTM5Nqz(5O5fBu3u<Qh3Mc-F|Cmw5Ww{<!CcK+bYT-#R2A8
ze(1h*S=|(fkz>oR_N&Rfxi1IQisqS@V0pDh+It$6J?T-TowaM(vt3dC5~|o|bj#{*
zmMoX8mKV{ktU#C421)=bQzdKViwvuEr7yBKlfAJNiAdO~xd6@jcgC}Bi6a&!#Wn50
zT7F%nueiZ;Z9$W4_MUSJub`mJ8AzlSGt&xgV2w!N-zP(0Ug_Ia2Zg9!Q*UKIX^a)5
z;JirrJdaWJb10=c_)_9*Xs0OK>?;dbzhaP?62|N;)Qy~THwA*ZDJF08$Ga8z3ctqb
zQocNXm!dhlyH)*U(v-BI6+UG5ZEhZ~%+>UGP6NGQxM*VTxx8fIea4Y;r$&HL*)`Ui
z5n=(X#fAZ?<6^zffnZPc?pNHDH5RF-_)b~{1{*bChON5q>UWTzJ3bfY#rIQ-Y6ZV@
zd((ZrfzoEo)|FnfWFDw;#}gFW6`aQg`s-xh<9hzo(2}`YU7cK7!`xtae?%_Ti@6s_
zf68l7C1$|Kq~*{AD16rlIxtG`67<0^W=~c~TuvVdd?I*U7M=KOH?@9AO$=A>QJ(k|
z9&2PewMol2lcKyjFQ7s(#E+2g7L>~PY+!t#a%glOKgZ}68QI&(GduWFJWuk<!*AIt
zSyBF9E~D}UUR9L8$WuR_n3AseFZf6sGABY8ac9jSJ_yX^IhqG47iB|(n&g#ooeHCD
zUWu*|&ye~XgR*_Y6+fCUHYWM>5zv>`yeM);1B*1c!~+e+-{8xO;NF$^5Pm1~P(s6s
zT)WsTf7~jUkmpd5G%jkDvra0CgNVzg&7%2M`Qz<Z6Uqy2Zk0T370r+DPV2*1Q2;XZ
zEcRO^IZRfh*>a{Y`##jvmC5X5>qjo9$ycje-;#tNfGu>#2MCZdj(op~=QQ3pLHSs+
z1Lf?iP@7L~@X?JgLqCazw)o8Qmc(VHHJ4b&>{^x)8cF2+J>J=?nZ~n=K0<7j_%kzD
zmcHtM)yFDt(H&L#P^R{g+L|O<QTye&%;}l8M?Ur9r&*vklqcncG?fTSJ3Wym0og1L
z?Y7K!htIOc9I(WpNYCXI1PXOaCga7Xmqt`Qx+2>o?Ao8vwZD*fobj$G|Hu`3g!n>^
zI7-tFo0jX*_fuTy4)G~GDZO%Wt)-UeZGBkQ^H9SYGjC#%9=~HK#KDHpB^WiQ(!Tcy
zP%3crzF!--m)w%!5)To2Dqd7MBjV-wpvuxny<!6o=#WL7yYn7r=lRUe<LM@kxCy1H
zb#|WCAEq}&&9W?cnU%rhRLhcEF&ojh7BB9uKj17Dd5d{bvRhE8ls8}-T9#g?#>c`#
zl^@l${GRDu%MXnt@ws?X>KW1%e?4I~rygOAYm0iu5&8KctfYmg+9^G;+$SP=Knuf+
z-iyG@u!`GYy(7?8ISYTmcy!3X+UXhQ+USrI5)!xT5}iwLjKX^-yY`g<{;SKClg$_T
zln?{q4KFd`?J`!j0pzrqBU3lk&~Ox}p&eW41)WL;sM6~+Ae0VHk3B>iw$0(RF^KHe
zP-|>k$4(WphX}?O=-8ZB=7j>NYoDGh{;ED*sq6?;Yind1RC{vt8aT5*u%WDfA-ZgB
z$Um-hm~UkG3*{d-HzeZ9{iba>TUSS)KvCBnd~}T(2?`FedJVg#ZQ5Dj9lz{WA)`*n
z=%a!2kFt728ZyW{b$utKJNN+Sx()FboU1DyM8$f}cdqx@%T%Yktyd%3sdtc5uTSrr
zD+J-KU0`qR2>VtU$V(5?h9(%=P(DUN*<r~rKF3>EwgsA}_EiYf_He#Lkq3N<K<$Zo
zMoG<WmkRWujrkimVX4h$ZEt!N%aCV#jmW<kL2}Z-k!=XrVL|`Yj1~35!>D7=PnGY_
z86P!AJgYm;k@GYim0c)Pqvs)M=!Y7hL(L0wt@5+j_BP|xOV7ab?b<Jv+It9%A`gT`
zcOI_HL)3523F?12HD2A$3w!>R6-rZwo#PJ`DdZleFH2<HI?jn4XHHCKA7R1+4;fb)
zU{3VLCI5vp9g;RBG$n?su%!pyOrc!n!f=7FALU1>`KpP2+UcEUhm`zmf+FGdY5b?t
z)JV4H%ndc$E|3;{HOUz@Ex&u5&rPe}#&fd%F1$!h?hfooIx|d~@|V(<@Sel;<<zvc
zY+jmdE5%!{gzJdQgvySx#<vBUruIts3j<Bl`j!sM85z?2$3eC|2W$~Bthj9&fjNp-
z)Z=rUj--t}_Y+0`N`OF(>KkPwUFfZgos{&oNg7S{G31K<-IbPKukEt1D{HH0onCg6
zUfTw59G_oLNPr^{6NZeCTFf=qB5!s?JtH`N7djqikCvMFnob$71&LnsEwx;wX3u0X
zKt4rWx^6(W=egyw;d6W;J~2(ibF?{j(HrQF08(IG3cF@sXy_+_rm~;p*9G1zyES^F
zJ38csaR`m*$P74{xn9m{jp9nmjKIdJV+bB`WqYaBt28j?U^ph;0i|xXDgih|suy3;
z5XIT38DCL&nYkXXge?L~YXWah@9~O~i^-QsIvgYt8wZ6(l!h;KJHXuzaC@iT(hYFF
zZvY$4mCdn-6{}!FE@tRAgG~VQDIu4_Ug!>>yF;O_v>WJ-WbgCW$DM+2k76(12)=J6
zBbvt@N=C>a9A)~os7TV2RoEsZl}xA6ze8&>Hx5;n8Itr*+k76+rWW{re+}Yp)HCgx
zw!ph(XXft@>?}JkI^>#!`w~%sB%`QU%!Cb!6@+Z|`(Ba_XqJQTXlJ64d1$vG#x<tB
zY;09E52EI^W#>!HnaGn)b>IC}b+1jl>eQ|DE0-u&ced#UirWI~%g)Z<r_{yHZOBAX
z@Mj;Q4b8@YU$@aoetaXHN`VuJ`3^Z=oyJne41O8S8gGw!S|4GksH!?cpvkyT{IQVx
z#<Cx}>!La1qeDgpc7|>hr__3khy0zZ_s`ldDh1b<k&cc&;Yec5&e}(yM%VO-;@5nd
z*MxC2h@~Yj^P5-4qFI@<_DP}XJzkWb=;))4Oyncu%#Eo=!vFDNG4>IC<G`urCYV3q
zYZKavIK&@%l7+uU5roB_#zM6w7cKS)CmpOfspFE}8hdNB801@LwU4I4a7m{sX_s)C
zrRG>);vJqjxA7=kSvFcv5V_Fu0}l}x7mLZoCxRp9ohQ7v>Q+`;J$c!Z<z<#I8^<aL
z%#%tRJ=bBl|G|+B>GLK{PS|`J-3Mg%vZl1zZvF=vnH%+ioxqC)vR&9M`j3bBvgl|l
zzpq3*aT)UwAxWK4%N#}YQ`+?4UDsxA4D6(a9b(f<4O0I84&}9MNsT?QAWv}&7$UJI
z`^qK^oa_tKmyNJN+tmPQ4S_9yR+gUxti%`f9F?iSJIkqlL;iLLyc*P>wPt<dC6F~<
z5H|s2(WVWv_|Rn~LW%I}L{5%CPQG47NTk4)vNM!JLVHr9o{`dp6^f08J*H|ybpe{#
zn0Sk@L=>6+M&fg)rT5jMuhTykn^a?|mM&8*osXvj8U2ek^Idq*X~H42X04jLu0wN4
zp0hi#-h4g1;Pl4CHmBX&yS9ruq}rX@7T8|)6J7AGwm^Ay*$w$%v~2vqa#@WD>@ORl
zz&KMes`Bip@2)gp-WZ!c{I<?z?oO;R_e-hiuO&VQ7h9aVrazbX(1B^)&9Z=Q(`0w^
zU)cv*l^Qm(txVYkDn7y^l(fr<o->fb*m}*77MrEg<bzeX$4M(2Bc1M(&%V{IAR?36
z9asuE=x0Ayr^%Jnv$SX1^qGZiwn5K4?P$|aW)bQIrDeSP`7^s$f1kAlDJJ%?n15Kn
zXOClPEzp2I-k|jHOKoMwSn4@n@oIb(dCL`odlMwEb*ZW?MaL;R(gJ3%HAbo)j4eNC
zoQQz>={=xxEx)MrJ5s4F@K)B_^}Zc$?IggY?=~-hKBZC-F)7f8X#4#vyNRAOk%3*L
z6)~DQNx_bsysf)7(sbo&S^GPj&3=I|BfJYEUHEXfHv43v(JLHdtvE;yovmRlBR<cx
zQ#*lW_kPtf)%!l90z0R^lkC0?T3Y{^B;{G4bBI)_B<&Qb^)zT&RDzPNbocl)tWN*>
z^`=ZfWvT1>Tj9F8e(Dw@lQl)B2{EXSN!GumtXsHkJxnmm?AEsWv@>i2eW`7rt4PeR
z*9i&;Y6aW2_lBmK^fvu>wbk+1Ufi9nK7k9TQgm~8+W$IqKS+c3RdlZi$fo;_G%r2`
zB$Y$<g1rs3s>{7Gc)lskcdlC*9qF`wcXxFklGab?YKsqr*2NUx<yeP`H`?<sEVj7A
zPIlXr-s;Rrre~mjYTv}!%#%^WCU3<S$7<4@Pfo_Sv3RKdT`}2gxH=Pl+W0v-t3CUv
z-kTVt>lVs)uxd}IncuMPB<-s%bkjx(e#Nt7@J{$zZHWC{-L3t7K~6@<<|Ph>>2F6F
zBlb6f010*GJ?I5PCZ*&Ij9x^BJukl6{!Yt(^;NRB8li#phG1u=OOJ^zd_jIwU=Q|p
zEdlzL`{f8Ld}R-la)*1BIN=S<*1DbZlHaP2oZZJx0OC3U@qz0PVQ-@}I|O6%Mrl~w
zqvonhLz4pyWs~!_o57D!rY16q)vnpWonj}(Gt8n`qAzhv-GSi8Q-_*OkZN_&&Y=@B
z+KI<EB!k+<T1BzIik<&yJQV!M_;uaTqL0`W09m2>s6L3?Nz#^nndGSgmyHGGt6c#s
zb->ajuxyx`4hs@9#yuNcCGkH5OP0U_Eh@%7uFXLZk~s|~g`cesehvxK1u6V&O~cOz
z3O^rc{A6{9AN^AB^YwYRvE*y;Zl!hq_uA0o+St+2(T4V*!gQ3u(aUkYd#!A16sl3#
zfc)mb_US#%?dS;OqC+wRYak$VwIZIK3OPGN!uCE;lkz%+A%_pK3a*s@RBdNcTNC<H
zllEVJWqmhxs84Ko8SIZy8q+{L%dE>^EgEDKa5kmE`SBs)jBrbWI&!YY?cdO21Po#i
zeIq+L^NKb-tPY-J)0!Ab2>k-<1}qlizE*5Q<=wm5T_4T)j=KR9`C2iN#rDnLIcvYj
zapS&MNkvB;5xw$6+diHk_Hm`WeMwAXZ6)WgpVcn;@tVm`bnFp{)6KQXio;L7D9eU)
zMa*Jl17H@5&i1aDNB2C8QG917dpHNywsGgY3nz;Ci{9IzD12_5FYy8Ua}rB!yVoVm
zZu1q&?v>R@K0N^sjLYljRm$#N$uauat0g>Z%iGLu7@h5NCI0O2>@;28a&_R(%sh`w
z7Y0KMqwS8YT`#gWdM&}hhE3i+J<}@M9#~<n7wWAwe!Xl!v$3=m;_YDtF@LYONy6rJ
zy0#mjG+6|@y3Jf2*o29)QFBg;*9~aW#l>=LPSKO?H<B^+TIX0-wFOFiWtU*(Fr5mM
zb1ln;ER&s68*wO|5?Fz*YD1P*b+agV+AuR$CpMYO5=%hbK|$O^kd;P5$`)mtq0?$}
z*~t85f!E3gyBkysd0*WE@@sWsgZY{+F@04+?mtj%#U^%bE7eeuYUo@M3<2xLHj0C+
zvXi<)ReFCmCf+e$>sV;|>xr1tW+<)AK{5<Q>7AP<Zlz(gh9~JqXvifjy!rz;5+>xo
z&i(`1KiA#he$!k%jCZ+RL1ECh<~KXa6gE*p;%k|kl7#>z&e@)=c6HPLk$B&MY}1vU
zY~S=b-BBk=vwP=Jit!S{`r3A{OxUEYOS$B;7zoPhRXWY$$5ZRy(mq2ol7MJ9VYQ#8
z{c^urTTrmc4o2CoJV4vY9p2^XcS@E`Rt#5;kx4}I_A9bDdtpsJpo|LoK_1z65Do4Y
zT~)@XP!=-m?6F^8oxaLWejUR=beLSi3~5~~^-e+$rR!%_;gDosrCO_Su$}G}wj9oH
zb%YJ=pcDMrmv_jMYTK7=yZb)r{kmB5ORwtGCmBnDZBPeTs|)+3VC@D+c@B<#*15j!
z+t*uwY5$_m`E~o%g-4~@>)LNQ+m?o#4&(ieX`mwxyN5SP19M6`;VXsn{|OrCLZ4l6
zk=+>=(1_BjzcvlLII&Zo{!JRVy>ort<1|SF7j(}5^=P0YZvH(Q=!nDa;Z4#&^_89Q
z^-XDDXotC#;tRCfb$oNW&}Y{?*`0Cmb!i~mnYY{6mnRmJ-auvZ^mHDj$E4I!6Z4R~
za)49cA3E39Jx+6-{I_?`@6ce@VfjEu-28hq&=H5-!<(dmdoTaLN&{W!vl|-djEiqf
z10S+G@4u4<e%HCa?s1x=fzr<Tza9;A#Ep=P)~}Vr@d~f(U-w#9_*en!=9^!>Wp)2;
z9N)%I;4VpPe6cx>=ZPj)@QlC49LH^wlgx2h))hB#OB%JR`I2leTk6c|w$AF`Vk+>t
z`eFH{=ITe(18*Kz4?e4Uo_g?G)$`RumQ^h#k~uEhs$Qrba;)m-)I+XSy;wcuS=F+6
z)*Ls$`gN^56f5y<>-}7WA{!WaFRO9#6Ki~0mZ=<@0{<Or0lU#RahYQv1uP6Cu60L+
z+&NDTf>N2B!qpV!OgvK;14a2XG52I5qcKVGO{#J^mgAJThBw$vUfGAaxSA7$yTU!m
z%%*KeTeagOJ=uOxh2Q$k98pI*;dPLV$6z%cL)3T-RpT*SjYpvxkI~(YN3M)VUbo{h
z{uZh8HdW^xs?I5@&XB6}PN{SJ-3s*;pv@cy>cti{$AS9U>H*Z>uO2{sjXVhIp@(j0
z?f<94E_8VDQ-`C&f6P8C9cEDYaCCT`syv+zoBx`k!@*Pz9g0R>+Q`6lqQn!~OE1LS
z`+motnVjGMPtl>XhAwOMcM`oc_8eXmVovso=BO};1XZ*$@$hm`R6F6xcN^%4O}Y={
z2e&pBYR2JeCW?&h$Y?C|k;Bzc=;uwAJT?}}Hferx^iQt*G!*9X|1|#JBH^~x>iRKL
zGF@_LPp^X6OZLGRGhJ4u1At)t1CukhPt^bciFG6*<y&2$PgsMp<1%^@t!91f4q;UA
zlqqblV9urY^=|2F6FVxtqOZbaV^i+!*w@x?+}F}ZI_u)^>GZo|o^;>o@)_Z7x_kxU
zKRR}KJM<WPey;BF2PC@h@?Ee`>2f)nLo|QHSWB%BOUQ6elxdkH`v-EB<?M@2-j4Ci
zd1IFFY@Mt9a$m7Ed3$tP+pL4i>(yHV5$urwDv=8%;GHY{9czp?THJ14#b&;l?`gYO
zZP=+FnBht^i&T*n;OM9WGER$F_)M&`Ir%$8!j_jS=!w9&_|()Mbo6B%<Bp93GH%KA
zP@P8PaH*Z{gZ?&TMLg#)-(1OW>9|O(j|aW!&*^z0wchl02Cs-e$8H;7QZRJ>CV~B(
zZ#K>~e1lfR?>@}8o1AaLLjuK~P)~_s%=sw%JN}gan&HY4amylrY;Kla4WN)vE`cjO
zA$7LcUKb5yQpn!Ktl*J)bw8B2PJb2!TEm>)Z>!M8ugag)VW1`4Dw1EpqWldKWkfqn
zViVtol(7;31BYtb+EZE^|DEk^eXmP<dQS|13DY{;n&ycdY!CG%Vy@mT3Qmi?!-{>=
zPB9i`NNB@`<R^S#OQDnY<O|zrq(alQ=#x9iZ>nz{+8RY$rP5fRR3^Kv@0D5^D%yrY
zES2;oJ6GC$`-$Ya3l(>T#lmubVE;6^%e1Glw7+tAsR*;PGl{@bwoP`9YX2$YR2}pY
z$5kfz71_Hy<K5iwP@Bte$QaswTV&iJ>-2t&Iy0y<mR9GikLAuIoKXd}(SODu?V8!1
zo`u9lhGTqTWk!E>BCO9BEr}^+BU{YywH4<yjLLDpAenalXUIb$W7cx1r=yR0*2fd1
z?h>i{k6U%!naR2{qA#AvXR7zZdz280azIvgZ=r3<7OV$bDAQh?XQ_vVdrssamTuMD
zLc2%lH#9BHsHUxqXwgShp=#u%D;oV5b#zxLN1NQb;?VPHHQ2b8NL6atgVmcIxa8+0
z*JBtX`)rMqC;KpYn0bTbY#3ZXcG36(`=|DmNoTK-t2i)(A~v2E%8)G|Ndn<abNDTS
z;6fzntLo{rENAE0&v7jGNIb80UHt2D4%nHQQff<CB1PIlKkzo=d31USJM%L6<efby
zy43UF*R1EKc0IPN{<i%L9jc$eEE*k=sEx`m8O`ZultP(C<!YYG#_~RwyX1K0sZigh
zEvy*czzdI2`JxmV&a>C3oTIb(!tXQ&z0<@U9ba&gI@3s%8KHAZFJy;A9pCO!-+p6%
zlZEorsUai$7rsqY-^%ni(xoc>qh$J0mA*Qe9;wn}lj-3qeSR{1lS-eFOpjCPW0UFY
zRJvC(eTPc#{!WLphbo?I*vAb%#yx$QA#udHtdEsiFU{e}cs{a_AL07O^IW1%+}cOg
z`fks@FV*Pp&vyL&r2gKkwC_v5))}7bnBm@J1;5qb7j^tznyTP;I>X|Q8G^|Q9@gLG
z>}MK;r==?RgU+y|V+K#Mf=BfCr5(R-{iEulbm38*p|)d&dYu6rJg&bl>-hbNR0V(5
z8J2g<a8I&=dHTCtO_bJ!n^P71r_RvSF~f*t1@ray*E)VbIaR?^I>XA28C=N<p5_C_
zyWGvmA%?Jj`k+WHM;o#j`e!<pS^0?I#i(lik^o=rarvo%&p9F}P0k>cVS(lT(yISb
zR8+M>CQ#LXDUzv*>4YMWD!Dv{FNzkbzM~Ur+^gg=9loeRuBy=qHK0{b>Vz7-D!HtN
zY-*&c-qHy*ELC#nCtuVMR1MS#h3~30I-zh|C8yTOrVv>*KqnN^sxH<E!4R>JC__ZP
zJmHsVm}!(r@$7#n%v2uNE@zY_ih`EPDsO56sl4~9yx~nWsW4D^@E~}k&eTLw`EJnp
zo+Y0`PUQ!7zSMkD`M#&~Rmbb?@2UBuz8|Aut11Py_|tZt6hW&zpZ`IR>`2KYcS;F7
zDWX<+R@r&JBYB>+^Q5Mx%JY<+N4BfSi|jn9>8bMEYv)-fdA?`oNzG7|=Vm*PG!s9`
z&Xby@D$hlB9*Iv8_u6?<^GxMA-p(V(*W-QdJgJ$`E}OS@{a*Kd44*k>&SfBSR-OK*
z=A^1?m7VW9QrAkMee$HHrONY^oo64P)!jytCp9%yo_p;)>m<*kQje0QBIjk9Uv?mI
zKh$vo!=mF$tw(N9!pA&rBzF!4n#;DSu$EGWJMYMk7^y6lEVf>ubcPaJ&ttE6buepo
z@S}=f`ds02(I1Yd-qd-c>flGSdnz?y`nEB)8gTk?65g>r{9)of@}hk<ms*(!v6*Ej
zD!kNIkIp#4DfQeK`{VQvbrd+Wq&2oRTh+k+(2!?#&%|4*748E7W@SqN9lN?F`&Feq
z6=*qj47tDRqM?l0^|Q5gfo;UM>PfU|zev_&tNvbsO^G#B<3vFXAM>X{*!+c0$X_$l
z{;bY<dzi%H`jjs*|KHl%3(d^L7VTeDdWgi?)JM%_G%~Cy-2IJ5RHDVK;OZ@F2KU*c
zPT&a<qu%zCS`P^cg-^7u(q{)Gsz7Tjtlr8l*~)v!FD7yYt&7Qi{COM_KVtMh*_qPM
zalNYT9N$;UrmSm|tL<cRWk%Wk#R0pi?qR?1823IWEo((O)-puC^RdC>ztHL*9oeS#
ztQb|(1X2ZlA@<{;8~9B(4g4mpfoW+C3{wrfAnt)col%uX6Ms@2DE1t>fpfZPU}{<e
zN2N8Odys5^u=uGy9IlO3xm~ezkT59@mYz8`g{4lNz^~<W0xRPM7+bs9br^oyO#{)i
z28z-e=+ub|I&|VNZS?M@jpNeVh@W%FPHZEaJrc=X{argT|D>*1nvGm@urxcZfli(H
zBMl^}srWE$jP9n5th6@r(%R@W5=E&_9EM&$_)gbOtYt<!ov1HJVX0FmTpc=bm^Nm1
zX``%{^?iJ4Gx|BrOiF8}Q$PMrckRL8zUxC#)Ct|SahJEMJ=MmZ!H4XM+?tabkHa+c
z944=ri^Ijb#Y<z&ka$+=?$eFG)<W+``*ECe>A7$m&9z=pUxaH_jhByO^ahbE?qRjd
zoXcywZ&vwMz2RF$Leb_YjH?l9PHz~wVM+Ilxg#hWFOqr%rN-R%L<oMuAN%`HC4E;a
zeToR%@AAjaf3uXAyFTsoX7&)pWBjqp-zMphq;>tfC4Xk>dqmQ6`2#ohpDD5c=YhzC
zKM7+)16MIkNGmp72KB}zh>){wZ)#h^=)pdhzP(x9gK^VXy2^QyJ$NWO=elcO*OE=$
zygORpu{Q=fE!^78yJx$3mqFh;m%Xf;caL@R?&EIWT@3D#)3z)Wo7`vhwE72{jmqDH
z73)sF)eCpq-PRR;xxPI#4S^-DNwcImR#_uNWtB9CCtEX-lcAfVM57jW3~JVY>}hYm
zA{uN}lL(dBB3;adLQy%w)52M6B3DOmY#Vl2Tj=6~6|>4)lq0%y)_(PS-s~njf;IX;
z!HQJMl9<)uhid-ePQ6q6;eK0}criN48+omLc2RSz?(YIxby4%oMbY4gVrhwh?R9j9
zi+71X6A>y>>*RgV$vcC<-<u-|U%U(w7^y>k`q9E=rUX|?k8ch#OM@%va^l@+@FS^L
z0%dvfq|LuVJ-PzgP-G;gLj5mN>zV9j^PB#~uqL!O<(pAadAfO)<6ENlu*jv#SiwAr
zL)4+{;lFWAHG5#{C|X)w>FxjNZi&e{)QwYF$NwgudMCT{coq+dz+uw|I)?U5g>zVq
z;i$*{X;%*m=T1GcMs*}Hp(YT{oxU@w&R_Y=J^34CiYbzi)9@{^A0KV2iY=jYB6|*o
znoy&9l{OOOX`!1nXR{AlxVs)N*7F4rR<?P(Rg!0(<HS!C>%*1!$bn}9sNq<k>@{|C
zHXoyw<Fk9LBcxBp0(aDtIWU-u0XxT{SfC_p`j3cNIqk<nl);v0(T4<kOL#@+Ezh0K
zVT~4n)p%a+I`+s{pCa=62tH=kp&&Ep+G|8uy8I0s6v#E-B`%*Vledb?-fiy3grb?U
z1(=OeufmB0LhC2JINphhR3o5l7AV%4jfpH-3s4pGbJr`2JZt(Xux%jeDUb-=W&(q#
z=<CeSH42`pF+Zn~Cv@tO4*G0zjO+pW0d&F)zOG<bqE~56dr@}i@@~cl9T_CKWQ<<z
zpB$qzWQ<N>j56%uVWahs!3@u0aTh8%BlB}tD#h5Sy*TN+0_NQh3YQf~e7Xl~>-K%8
zH%B9#F&r+A1J**;8I>d8%d#z8;?w1SuBTUuJ>%gmSs6Q;ITmHzvSejsAFjP^0`j|T
zjn})kjjDSoYfgp~vIBTDD&OZjyU`^uo|i8KE*&^IOEZL2%^-Mbf4KUxXrY{s)_3i(
z1tOd!+rnq<6NY3|U8KrGIhzSO<K6@};CvjLgTpOm17i)FQ*@4jCbRwvL>Oo**BXI3
zbQzu0w_PXMbiqdM(2?!KCO3z_SMc_*aEtNV`b(mO^rYy)Lb?cX@VJx5q+G49QG3zj
zN5Py*YbX;sb<~)|eL`ol<vo70djFDomb+-#|6HH=+e?7$O3bUFHxwW5Q<t78iZCia
zAs6Fbb1$}$k6j`JdCGIr2To<NvEGK`Cjy7i;g*A9D|Z?in{;A#9i_&mV2z3x=?E!*
zgQveMew#Ek(hDpu^Z16*$0Ji0@JjJO?YEV=%u!}yh7w^-+|JXh?eC6k;(Sb&>K<zZ
z=JA0Bqw<GzPAKL_{K^TUmQIjq-W+Si;{(w|%3B!R)5y!jEow>9%p7?G&5UYuZy*vW
z;m%gSFHv4mfzG@QEHosFWR4P&#Wu~Za}T@L<7kP;3U{+d{akL!RvER8hNxgWX39*H
z%lC+ip*f9@a$XURsCLqn#2yR;TguKaq#wi#?JHWwy+4xsKSaR99^+9ijFf8!by+2R
z)V7=FDXSQ*s?ICb&4;3G;wz|C^mcdO_F?7CM%6jc3H5uW{?n<{9^?Bi0(MqkliFkT
zF|&((@eML?I;duRJ<qVy$_M0~O*btk3!TV_(C8@Y5ITAL?UZtK9V!$@AL5xbn<S{?
z$(VRey4Ch$*^8l}dAO8y@C8$nrzWJc{)W+hN>7p=lKoY(C*GFze}cOt{*j^|weQuR
z-21F(O1(?%#lBLMXig$;ns!t{ZC!0IV`(3E(@2gh?8KP>H{A<QO09j$I;;xV$-y6G
zq-$Q>euXb>*O}cu0hH7E-SYbm&F?12PVREW^41%b(}jTXFFY*-yl?fsPV@^-C3Ne`
z3U=q!MW;}zNwGb-lv`GSly)zImD?Pb$BqESL@6ZGti2M-!Khj%`Q&Cx%?%Gge>OMF
z;|tEBf#Iyx2Rrja=;AtQaar_EU*sTDM*O$J-}II*Z8$W=9?hUR+S;ev`kkt=mD7Y#
z&lsjrlv5@pD>+~u^^Aq0MWQKH5b|i!bW~L-_0rmsDqL_w#)#JV4|yCuc38MMJOaj8
zt{CI2@|C&`2{(_ljZR_Tf_^hZdWgw0K`rRPn<N;IIl`xI<ED7%3`A<AF(ZCA<oAk1
z%!ps7_~cUcEWte$pL|5~$p>o~^is=RYL4{9Pa&htDOYQXpEny$`Tlnlr#yujpweqd
zCkeagSrA7TH!^Q(I*q2oC%>Fw4=0>b{Gra4i;JzImDUKg>*8_=p)?n%Pgwnbi57s;
zDdfNOS8i8aoUM%`G%xK(JdLYZ#W_aak&hC<yb|SBvY+%Y+cN&?@ZEFBTSnfi(%R(y
zi{v&BW3ISgwQiucdK61*kEYek#q?5b6OOLLo2j`c)ZCGGzgF3icb5zARwx%vaZaGo
zsGP>g3F(*do4*GNS<Rp3PAEg?629_!IT)*F0z}H2p~pc&YTVW;s-@VskWfEYd;6^Y
znkJfrCZKwU5{Z);^;|4~Uw^X<RpL_UMDugb-Vq4#7w%zGJ!L&3zx29h9Isfi7UDS%
z5*t_XeU%UNjpG=aP46-(tZ)nD1q{h(<TyH|q4z;rpt0=S=$&q7^W#fDfYoX+BxVYm
zES+L9yjlkQjbf@-DUnh$ldjXjhwou%WMZ{|6RfkUVT`m>_l;C2^WvH|jf3zHJ8*I}
zCr0_=aOET~muKPSv*evk$=)2r%XQ}?3p6Dg>)_?K<c5MqPi5_0F>{A(rx5{Ib_!i7
zJB98`v$p!(1^Gx&>*VY>n>rJZ34*>P2uN)C?X*W?I|;h-nM|DD-UMI&7YyDaf=r^Z
zQQzYubihqBiquaQh;3503G)00A;?)`r=<A)*OdkMQ$!X#k1P=NeQnteTN)_({x<SJ
z=__|&m_$e2A#+z~nqJ<%0ZcSl*K;R8bL7_M@z65M(Cm?7yH_)7&VS~qF}PfAc!=s4
zoZfdd?o<H6{hQm{M-lJ05L0dFGNbB;Sdj&9Hv|{Bs;}}l1nb?6!IcyxM)pfoxZH14
z=29W+b<53Q6A`dQFRWZ+RPD!xib|CEg^Pt*6s*}DCdYHpF_#i(yJE&IE~D}Q6R4uR
z9s!b%*VmT*4Z&tt#SFhI)O+X+rx}&S<QaNHo>6(XOva)n5s}8yx3w~~MEbjHrlzp#
z$uKauB(let!Df=42=ze8bH+V8fz?=0vfQlOy*jX(6Ntv572cxeXch`!OFK5U1U%*n
zVzsBoh^(PABh6xOW6&>Pi>!#ht<a+)@y0fjNJr1(R4?eMN8M^ACKarv>OJ1UWAPuH
zCNZ_cC&?#?Z5lor`&xE_^1URtF@v^TiIZz8-wuCNQQizjJ_Tu3QC_24+Q$BCbV(M$
zQHb5lxe;#$;3_V-P|U{Qe6wU;>^yP$2j^QQoSMJGkx!t}9nYl}c#w1=54dO7$Nvmb
zGgd2QN;WXE#!?u*Vhjs~0sa~Xn?1g9Sr#m<sn~zEF;{lP6uh16VC6~Fn=BbzD5G!<
zC9RT$qAgfse5%SZN;bT7jK?KGq9sr@k&YYP(xdo00*4;^vj8J)?5oi|mJOa=vcy=r
zHd5Zy$GG<{>BXq#;k}J}AEj(`)MLYY828D&<&kYyNA|(nZz2bpcA)6FsXvDhjRke)
zYDT**IofWHI(9SI8$frb!9K7tZ7zI9B5klM`vbKgb3N}trbu|fb7KC`$xDnmo1{;X
zZG+>t@m@Gbu0UJVY8J_0#b%s<({DSjv6@I?M8$r(@K*{%ww)gzN`9%fLRC9-%y{Fs
z!39QT53oLT%q7ed>S6NDu1}kKm22z?Lb!cBL1Z0y=na<|mDlp1V!2ns26;6>auyj?
ze<EcSHOrEdtcR<~TlFwcY1MX`4Nvj46N26r_9AW#2}~V(gB12odm6)#dwXnFp__Pb
zzlejTW9UWvZJvq4y<D`4csYrR@&&F?=I+TYjGuTf`oxdKQ^=ZHa5=k(UGZzlLv6|K
zip8n;!FC=HXV{X*683-CNS}dw$>l0EN2br+vutPyUkZ7j)CJngGpJv1@8Ofear_}F
zmiCie&H<&B576vOu23I3)(3<N2*GC9M*%Njt;>NJmZAc)D;-DAz4_~<pOiaaw@^sA
zRQ)hijgAVbA5P+m&%>F^yj9On@T`idR5huz$x`rkyowGGGJXa>&Jk6$LY_>VBwla(
z@M`=t=`OKm)to)RT7Z&;s}8o?o1O>6U+D;3d>h5n{61af%|3}v+eO}R0N$22&+<eU
z)8x&=>ja3X4tQ&kNSk9-(`<S3H;0H)n6l*!_t<tLZ@8pX%bTYw%KyeCf^tDpg&AC!
z6g*d5YL?i7NA5Au%xCB!1<%zGlOnVT4_2^A^d(2|lq?ZyD!)q$o}0;#E_f6pGVa+2
z02a3<ELd$7EhKi|SIZvm@$Nj^eo7?nB&u#Ak&dc)w2+cLB4CWFe@Uyt-_vD}h$UoC
zNuIj61SVj!;lzM6+4H$VN)mN486`BmX4tj}D$0%YPKuzXl?a+=mOLJN_PZj2=2<0=
zJ0eKQpBxyQEq~?_=Np#!A420wHX4<y(&bN))D}DH_>}z7Hd810qdHl60`(^44{`Px
zj19*D0hP#tQ3v@m%&+CoN3@)jsPT;ghbDpZI?11+rbyl3*+t)2{sdbBLFA9IAh=ux
z{A-Ax_qvLo^0jKbHM^QZB5k}Y{Qxbz>KfjI%j>}c`~vy&<X6Zah1-L&=+t^R`QuXc
zYWefGuPc9Kom9;e?pD$A=LbA!`SZMb<;b7El2Yu_s63rVEgT-_DQ$*#l0R6vooB@L
zYd}I${uGhwB!7;g3=C6LGTp>#c%CDFUgtR}e||~=W`X{BznV2l0A<Ae!torY|9$dM
z+t-pmg|ysB{`_5-BhcyreT-B`Xe*DUei_qBK56M7@&{ks?hWyuGQerLaX=DRSqC}v
zdnr-Uj413z4n4(3dk*H(M!Fmt%BNKQNjY?<)UTw?{b_Q@>L7=vc9BDO(Gld(RDP1u
zCMbY8qUV@&Idq(K8#(l}=#HT?wH)%{ut~}x@inFa7k~e&<j~aDsj`b4I-K3(Zx$eI
zIh08vZL<CEw|fpw{U5e_cC1q9(Td(y66xr9yo2od|HSUOkUf=OY4;2Q?yt6c{(u+T
zCbn;A_uNFuZtb4>-v3Y8J)Sqx=EClk9R@pT_q@ydZ*2G6d*oNyJ+oD{|I6*34}`rW
z<<48AI&$)=|5bL+c{a3K?wrvD+N9m%<5NoR{P)^D3t#IfZ~nK~J)S%*Zyu>jlQ&;s
z_e|>IXUljMf@oBJwwB1PE%@15@UwB27tN+6>1S(Fc8~VfKE5K2q5g(MIzx5*Y|p!@
zuSR)kL>xE6V=)3>p~5EoY^;=G_uv96TG`pp7G%A6@#6M&m+SYt%bQB^utmq>XREE4
znewwWqUW52xl^#KfpxZunaag>BQCZQ)Rv();$oY{gDe1~Svp0vqL%;W4lQbKBEvwr
zmr%RdN(12~#yz_LveZ}*ZZe)<_kw_ct@E1k*fL|$8gEI9yP=(>&W=8|w>sK6QH`B@
zn$oZnCXtSvKicA^QMuU)3HfVOz0W)FfkQ)VomV>h+0>EiqydvSxzx6GTJW=pt%EC$
zEGQ@`8>dm+Y#nTz#mdH6$Yox!RkG(axR7hSBFiT!Hye0N`q=DFyiDA1IHW9Q$XYHs
znNj(wwsT}1f#`lxW9-Z$MBb?JRTsZ?@w2HOI)1kFlG}X(#bOyFYpnLOja7cOD>Dxx
zZ)EHX07H*`b<s*?;?yb^+sZ!E@3Gx$Pl8d~y;jSk<6iqQdZ>)`)L+`;+@QyKHIeBb
zll?qi5V5Z7IJb7RZ)_C(LE@L!+y0{{iL`O9%m#6GzNvfymDkX?@`bdx6ORp@%r2Xx
zpY2A`kJJ5Z3b)624<&ETmZ~(d9jz)KI#yh5&l{B)G6lxsYTHY<nSbJHOU}L;rToiG
zQNA{rDazM&Bfd77J3@Pg_O;z8w$6=7Ut5d#+KwlSn!vWNEm?1;S@9S0rTN-yK<^MP
z(_mxkMiOJvTy4E5Vsi`K!WPtO^cdx8+rYE%^CsnM6ZO2J{CQU>WA_%Jd~<Nzr|q03
zKYiAIwyU+BBV9efKq#gl`vp4r+0LigG&?8CrX*;3*>VM`_UinTL>i=(18CmP_Xj>H
z6vrQ?>NGq9sscrw$rPlDpA83a)n5dJuxwU1j~B4kdLV|}V2$qhB0fSNHo7jPa#eJw
zZej#q!GVKwn5ssH?Q3gv#UFQU9G)K&8%IVT{_Be0OG;0eL%7+l5V#!k=Gb)e<`lXs
z=FMU;ZyuEGvN?INvtCLQH?@>agDd_S#r0mLSsy<__qvFi-z*jMDsfXAxwRH?Q;WEH
z2ZqiQILTyh8$+MwW-F){AZ+s{k3`x;t6B^X7T?iaZ7VMTGfQX|aq|onu0-5~sTv-J
zJP0mMlQ)-9P_64=g3g8R2a;|KO0XGz1o8@s{2tlE6{5nWWE+W9@~~C(2yPnL)ESGu
z$5zMSZ_SeV(MvDIIj$Fjegm@*XRuLqo9c-gvZSkXW%`;>EA*#a4)8*U875tGY8~VK
zTeZMSkkhOiShO&*S438vMHIX=^No8%)Rh5ObD-q6#yzq|Y)x)47EG>H%Ln*W7`*1)
zx7M0fQ(ziw!+J2pulai2{*$cW!&b>7`Ax@dGJ}t^{-Q2lw5sHLAUJR8F~)sr$yOB%
z1Rpmda`j@3mpuyVm8EKOH}#`<vs#r{(uooL8N{bC0`U%%5*eJK)Y{y&B+`enj{4OK
zUD^_qFf{gJEg}5Ktrg|ZxWYHe>W##*<>C!lV4{rNt1CZAubA@1vv8Ih>63Kw)hGct
z+bpS!y@7Mi3eL7lDrYU1fmSk*y#*)JbCIo2R+O)VAg)5rXwvwUr=-)daila>k!&pS
z06vD5?sz*B!S+v7)GCgD6mOurC9*~prVyUKC0ce0FtJa2i0o9v8ec|MTXsG`m(tg$
zq~1;?pQEG|tWmPFgOBjo1DR@#>UGK_7v|zG3mlpx-=Zh>Y)vD{>fqu??cmvru`E?B
zW~mC3yxo?ieSyc8rLry&9sk$JUY4q^C5Kv?ga|i)5Qs3?90)>$ugOq+8zMwId9DKy
zJ~#D<vR`Rx3j`NVoAM24PtJyPqP=ZP(`fG<5^1zoSqa+`0)3VD2x}1*?9*J6xL?LL
z@#mqFA2;Td^0Fp6zB#_12UrCd;O7zk&Wtz1C~G>%a5ctPxRBwG$Tw%L>}1MD$FGQs
zTSyw5xKtX{Hsf5bhy}%JtxUFGDtji4pCz4l!VVPUcwaprzu7tfu|5OYzNub0zREgM
z+(#_(TQ+1Wj#wr8Y}2akG;LS&wG-+VybQ2xHqkDWKapYyK7Fn1Ov(T)tLykGVY*dO
z<yTv*1o(YCBfC~A`8|My%&JhI-7M>uw76u+jJ=_(ng#PrKjEd~7m9C}{7Q)K*{kfj
zWY=X6rs}##*G}^MN}x!S=YrlZmT1T|$N7j<N60H1s9!R!<de1^EveX9yN0!>@jXJr
zloTxvcq0CoThAyNzY-ZgOG*a`EG$0EmB_Q#nGWr8CHFJ#_^<hB^N2~br^?xDX}Nq#
zjR{grqw6NAUp6ho&jwJXKiba<SoP&-zI2_`$ohYRYh0Pn@RJnprwe?JtlvVfl8F+s
z{U7$;1wM-E>>p1;lpxWG8Wn5Q)CL=bDpadPQX3MMo2CXdikGNW8?D7kAuFh?26tC8
z8CTO+Vo_14Ql*u)h*6>-1c(rnYJjLHXrrdOW2{C+K~VGmexEZlJG0q@aB1JZpa1Xk
zQF3PX%(*_d^V|-3eGPg2pWyjVUO)0_7q6f19izG0#p^}$9Ph&M#ItBp@%r__U#<tQ
zUtgewRtm4@+I)x-BpDa4_bufhEM7kx4=yAP&jk@BgLqKE+S6F2MyxJ){bD7VhAy&r
zJu=eQxp@5;d?>trE(~Dc>GiOn**qQ2Jc7uOzxg-11SS<>hzldMw5?ZM{g1-cah-Gc
z=LxualbfrHOifP@1Tle3*RdmqtFNbxC;c+T)xQP2lB=)xaP@`S?ex>NxcWTpcFN|8
zpw@$%z%FBR^?Kb`NzdvKZk^X(TDkLhdf_&0Z${<qo8$uP5oMvNhiZ5J4U06wSE&Ub
zN1?nXt+)xq8q~XwukvtwZSn8MI70AnSN{F@bFw`Oo9@ShdwZTk<J_L7UHqGb0sOlW
z{QD=BfyGIFT<~J??}6R&@AhGgVKGaw9puMvR0f(r*zU8ruxwYM?3U}y`*auAlDWe2
zA)nPm--4^P;hSxg*34=oqzcOiUNt3~ebJnSlTFY(fcOt3&KYHmOs9SmAO|B(<j8!4
z`0hX)1TVjCCvSzPb4+z{V^w+vA`~J{v}rBcuprf>i9`9Kgt0PiKK}-O0iSPF5`wh4
z9spwa=62=tr)*Pv{xN(L<MXxBHt!q{|0w~VZ$c<fot&4S5I$e$<?~Q@*nB<-L&KRF
zzz>84ujfXHzzNW7LbVuZG6x7qxAwPU2Q*iTz$u{l5<pXg=#}~=L?CS6h!*v?wr>Qn
zLJvtJN&%eH;U!y{=UYFuuSLSDOPkY50iTtS&)m{wJam2l?22PkX-iztxeK(%1)ZTQ
zEe`)a-eZ%$#$s{*+ZUW!_JkIh%C&>f3q~jq;qdE=@B@5X`2JJY@$h)rrQhs;+unTg
zc=C~uG_UyigNgaML$e&F_6C+inA$5+06+gF3d9#JL`U10@5^8Cge9d&Nz_uO<@qSN
zNMRfrzl2}o7V00*V4)m-z5!2Ot{6TN-v~c{8vGnOyYQdD9M<~kgrC!s!#R(S!b4@?
zK`%cS;sW$WjL(Er^9sc~)uA{O_0h63^`7|oxfn$pKObm~Tv4E-x{N&Z9+)Bb;hQ=)
zKNmk7fSj-ja2ydWnEwd8d$DsqCjtRZmHm<D^FQH>PG2MVOS1VmezfSsJhUy}S-kr+
z{1jV%=WJfV_CXGl%*!z-;oVl*;@x=i;g@*c-2}Q|K8JMz?_P{Q4u?JzAnZK+h=a8m
z`9-Ma8iDyWfgQYjE_wOeP|}f?`{6F@m?al*%vMaL6>?zHs4p=lCx-1(BambGvVskh
zNti6x%vb*^h^ACf|MN5+)>vn{Fdkg`l5jG(<*=`+&&z;7qt?F}d(eV4avUrlMHSq0
z>Z9s6ayAaq4VAZ0+j~29zcK(VXLwy-K;wCkE?e;J%lLoA(CXrb+~O60BIGk0UIabQ
z`)Hj-@Lgm=W7ujM#R~m1ZTU(esW`}EEq-?a2J34i{`{Dvy{|iafE}Wu0+|6s_ih6L
z=4H~=#Vh(K!hTeYuD^w0iI-F}7@o)Z@_PK@LODxe^sB|PP)f0MDIQ!46}l1RETX)c
zN8%?;S6>77(@-vGubN``SQIM*FJnQ*i8R8cVFnh%zn(!oFJc{ItV+@$*b_QJ#m&@H
z_*n5pj8(0VXH_*AxV2Lzd&Zemc3=$JwwGV;$cHQC*4TQ(Z8J&#eE4~nLT7m1m0I{o
zXXE}LB|3!u9;MwZ_K6%A7aQ3cerdSYIZr0$S>QAAs_O!$J>^>9U5mU6TmfmuTHsdv
zG`#5Sid%*kjn_htV`%ys0;SCC?h|F+`FYwsStx1CJA$7K)%}gG(d+(Z<eI?Z{x&WA
z)vZW8CW>uRohv_g0H%?w7LtH#BAYP;@pBnp4!Y1X*wv(J&lN_G#*T<J)?&Bhq<`>9
zTP^XBm*kb%BK~wb!+-iW*TTGqhZyAf%PF@|p;B==fy;l8?09G~r7eHGgs~K*3kDU5
ze*Wop${zlHjsgU*FP^;0#83xE>FBTfQQWG7J=r!f)L2XZOBsn-5BfydA~3H+SwYzn
zl*nICCTw8=)&u>3@X6*;*a)GYEk82Xf^ea%zAeBH>f6&%;!LJ&gL?Jwm{XO&d{FSX
zM^s<X5re*y-J3QMWI_fp0Bj7gFD^i*)<*SSFC_x{Ur}<#akQ*xY&6Pf@}&TJkE8jX
zYcw8QSj27d5}R}k(2Waf%fCU8HmI^9HlN}lw&hyr+8D8E!B15yfekPqv{W1cjHt*E
z;zNWm9|T`1ufa1Y?E%Bj9$1k({Op{HA7Ik(OboWB1RDkuG`LyEV^;D_hkT>IA`chi
zp~j|vuCCU@Z5z8R2>1dD(xr<>&{ol3{|sGfp{IzTinJ3~hZp@^3qOQ{ay9<}N?qOG
z-@#k=q9|7N;X*8m<HhtQp5koZC*v~=g+q^VsL&N;(wJs81}eu$0je86f!udCd8JyP
zell1}PFN!?bTA4~B*w2(RdHQ(+h>3^y8J>Qk9qwjV^dtxjzV2lAI4GJTbYB0*jAze
zEldw`{T1`~J6z6$3epU8WS%Z?3tCfx0JCPGI%3~O>cuT1#*>6iObc(k^(e+nTKo9O
zzbr(6-W$<zYf{sOy3v7#CGm-@Qg~?XZRAOdXPHInJ(dtrRv40i!5oOk7~(PbjX#i!
zn<2cjsKU9<*A!f^)amGj%%ET!h82rE2AIv`s?(Xxk$sLP#@T{UHF|U&wo@vK%Ny}D
zHq5E;0yoxML5BN8f)5Wv%T`^Sc=YiI(@aZOOA+9pRWmT-dVVTP&{94&q)V@$a!a;j
zXer>)*!0elT<opc5o=kuGGEy2Sx0S%cp%Xr@H^oNOcC#Y{s0lrUW;~~NmPs`L^uX_
zLLxsW2l4;e_%pyL&cYwuJcbJr2B5?sSyW-jC!SIz+?FYIhX#4og>_c|;(PX`EriSN
zx3+TkV_QS^V_P}<v8~Mg*jD;}Y-_-NYzz4j_Zv)P?Z>vV-EB#X+Bue}gA^KPr-On9
z-+d;yE=@l>U1ip_5et};iSz+RU;v~iW)#X0+RBI`6)KqYIuJe3qTd2sYa>z~Z3pB^
z44vIq)>j4T$y%7PLSROaZ$K_vVTR0t$_IaVs{~}vOs4$+#l)KoHNLps4tkYLFI`8>
zsjn3oSG7ADz?z_KUz3#VD32_&^O`@Bs8~|Nb9iuRP{NGIfz;;&Z#jbwdJcz+=b?=?
z#-wcM&t|VO#twk-VRnPQma4%wlAlV}H&<=aSB17{VJ4bY9U~&Us(5{L47+Dgt3>eS
z;YsNwe2Dx*6d%<JO>p|qLg!&9o-YqZ-6~&mXp5==@$~0e!&48{X0Hsb)56q$>N^;{
zbtva>Yi6~td3fqk5P6_md?U%94lUyZR1AHNiiNg(H7RYxBt+wUhj&H#Bs&@>w65Z|
z5f@}@_paur71xZoV1RZnriTfIPQe~YKcRsvZ5q~q+6UxamR)hRR7P<?#jP+UB6VWE
zNCw{p8)&FRgn~%X_L4%*l;K{6X3TT&Pt6JpJjq-GURPf8baHzTja0>bRD+mMm~`2=
z>TLvi`^n1I<5%uD9<rKr)BbyEHE%|XQZc!`l{yU!RJ`!@O^cGvas1H^*)y-^(*PWu
z)fRQ02fnl(i)>PH<BF#_$M9#b^|di-a;+^Ym9>#4{rsN@jJ-4`3&?=De<n!p4b;y3
zl%PPUjsA2NQkz2u3k?C`TmtKJ2;^3F!Qzd5Y`2L6AH!E`E%^ER(az2>j+cqQPw)_H
z!7wUFfy_^|3Za{jePDpHR~}i=G3GzxJ^5<k0|-lZbRpf(@w&FXnd6*KoH<@p+4CH0
zV{<$K({ko`#O~+#&aT9BT!Z(V<7LoE_hycFyuUYdtoxTUNB?a-&+*&X9MAfLYmUS4
zu$z6{Df;)W`}iK-bB;H|MMvfs{5Y3(#!(=mzHI#21Bjdm&lAbRvkz_D3TMfEZDSSa
z`M$RC$!q)G#*th1y^ZDXTWtu>>*||2@j<|WG9bEqQ<>va`KG>t64aJrKvYM(DUaX_
z+r#84Jd~4#mD^F^ASKF1rPSLAqQJ+YNzlYDao|Vc%X$#QSOoY5GZ=`sd_D*>4*vad
zd{co~W1)j_yel>-)8Iknd6%82g)RmaM+wJ6CSC#=1=mL6Dt8$8bU5%*JxL1yqVYED
zu)S36Kydo0b`1pI6c-3SzzziO;9{*xK`3~+#DXif840vTeGj{qYB(OeOZ5QyA<veG
z@W_m9IE-Oj;a0rn`bb>(_Zf!cKgKv}H!<Oxus{ci>H=ZoTtr9kumbXwSb=;q#Tm0Y
zRRSp*ZFSf+Z50xAW}A}DWAQcmw*;114{;9Sfk!`8=<c=9Tj<DE0AZd~PTUSh3H#u*
zRd{H55CP$L4#gsi5zd)k=m%&&?(0$b8e&{rK;EA>TZ%9{0^SI;20u+VnahH@t<}(N
z{S-rSfdZ`0aI~RYv$n(v3a7gjJZ+Hb7h&N~a&3zq!2_bIm*c_qT%E)vQ-OImGceB^
z7QV?F7Vd2QKLL`Strz_=w|@Lw*?J{s{S*(Ltq&c5DOgAIY^kYa5UzjwgXMV$62F6z
z2xG*{FfxbXtHmyR8%OjF-{AN5kyvI-1ssM(G;=5?>+Ic&MDEq)d84O55PMo_Oz<=n
zK7iO3*hn0G(9$I8gDf0cgC7+REmNf#TIlB}sZhNI>RpA@zEKljRh-x907KbNMbh1a
zlB;ng@Hxvyt+i*_6lGzaaPVDadFqFUaxx`{vh2ckiOI|k*L!{!R>le!uR~dEP~rnK
z0Z)~%)2ev!Qswz#evTEBI%1sq5$Y&AnKf-%AJw$~8QYzcMuDZmta0-LGB&lJ*W<x6
zwonEdv-YzDKcZdWjPmVvEdvOtbS;vd#Mi-ZmGR+BijMON5>~=*mGR*_FjqT19OTNi
zr=Q)=sUbvsxax$FbM)oG2hf!)rN@RWfzJ05n@8_dz=V|PDJ0*?(_}okkOxMwX_yC$
zVw3U5(Q-`U;HdHdT;p0}(=n1+&j+HioqFXwV@z6PQm1~oqzih4t70X)WNz1mdhvp2
zCfqlSVkDthXx@h3k#+{;<3VWRDHfhugWN8$$%q3CfgfPq84>q&tCiQ!#h^+TqM`QM
zm~7QG=6vdGbkT*sHIZaX>;)sKz5K0a4hLmHVGs`<%njFq;E-r{pXH<sO_F}c=Q$aS
zFX1GZeDuayA7Qg9p~u&oV?pO0UWZsQi`SjsJ+He`VIp|l-6$pGbq4h2<aO7hLPB20
zvln??T;zGT%x)J~E+Mm<^n2I3os9?Yy8Qtid6*q7B3k%Eytep?-{y6F5tE)M|A`%g
zPF{DIy_hO|A7?F|@Dim#@vyveFnq=GT=`GH^N#e;&B%S6iV0W*y)eqw^F;R!I*j95
zcW;UDyw{{|0-h(+^u(cC9J2&pcjbA{Zb;1Y7|LMtypb4+3vKrs&x;F2?~dt3yJdQ%
zwE_Z)NRGvW2LwXjLf2{$$-z?7JR8d{Ja6u9dET#H2hV$9_dIU{5#Hu`$c@rZkc2#s
z{x_g~G4kT(dGz5>#Gkqwl)&>QqNI2pv*F>L!}I3iS?IMEIs!$-^X^5-)p#7w`y=ah
zL7eCb9Inmtj=+P5uY|2JQ$|#sJPwj+^SpT|$9UdP@kAeF|4cb=10T$7ST67e#dMCv
z@0fm!&5H}Jh{`5_%i5STAyARuRo^S)Qd=3ogJ)c!Bs6AyaRq)<tcWRt(D(Mu?UkT^
zuBEVtz<waN#qy%iM*?5Kmoow1LlA_E?|uD0UcNVyZN>U<_+FUrg}eR6#rJOT@V)c9
z@V#p>AMm|j;E%)i&gbA<e2?j7+|RqvN@BkE09VJw_ZH~I^P^cy$@h@?Vu5)xeph_&
zF*q8N?~MSvc1^}yfxhDTp0x7LSPY_c0UC1iy{_lFn<MC=3*YPMTsP-;9F)cP3_N&{
zH~im!u6yLE|J1qe`Wn|#U4aMhQgu1kDOT4C`a`*ZXQ<usIy=|bzwKQ2r+YXD`&_4Z
zT!M4mpIc%)uG@2+;&BPib(8URS01<VrNlh$|H8R$>fN&SiZ1>V51y@epX<g-%{@BT
zg%MiNn{(a2h}<@h`?sF!cqZBBbKO}SuFd0y;laa8!v8Dhx{0SNKKJNdGB&lJwRrH1
z&3&$$fgcs0+rx8Rcl^zJt~(md|DQhB<<})R*R7`79{lZ++r9jaferEeO-_g3jU<1I
zKi75TZx7tTeT$E&-^|mAoa;V8$$PG=NA_;V^7bSiJeV8)BZO+6Ppqi=1bWNs(PW}?
z-5K~2dP|9@Z-nZpJ~CzoGgq#d4}y=Q3bOfGXSr)}mSdbKRF({?hu-0Gs4ST)93>p%
z#D~vHAm&k7HX=6<k8wAms^=JoVC#DA_GGqz!1~5Sf%TghSZ^h-bTlxBVI*CpQE?G%
ziQcWpR?2#H3toBG>we5FcAi5zTBW?S&T}5!Wr}s4Q*rk8AuSeXPaby?7Ln1$5@&B$
z@u)6w4TwL(&V7$mtjMyge{QQTu`i;#Ji>jBv&O!niqkQv5V7=^|3YWZS&nY8lFxj_
z-(#%q@2HG6)p>3dmRIR8?P+??b508Zv;c7yR*$%l`_|R*E`6n~!H?2SI!G%$Ca)h-
zppoD>=jW_!6=nk#-cez`fd^ZKc@b(Uc!=Pw1rJ>V@Ha64KOP=FjX%?gM$THmTbVuF
zvRPZNevMZicnHyv#?pMtdPK*{SLPWQmFSh*?^0*H#h5eonh<1TdQE2uZ%3|V^RGO&
zIJ!*+d{MV~6j#B~ZJHzi;DKYP+eBc#I_HhC&v_RnIOh@BpnS5BjWK#aJDl^zqomGx
z^z+9%Ip<vt-R5jOTe{7IQB+4T1ErX(jt!^dtb<u|Sg-3j?@SKYb}{=A9?I!s=IA!J
zW5*;u-#+Kvha-Z0&Z|K=cFv>TGA=&9#eL2@7{8+_b<X3I)j5y!Mb3Fj*E;bOi~ogP
z<Eq7jXIvq=8d`>c8Tb+H0+V>o<9KYHBMGhOH9x}-p7Y%zyl~?2sn_hlJZ-(^YWx`6
z&!f@2#s8#}acnErhjYG*@V%Vx$~iVmuXzp1GC29=96Tvxf=aUt>w%-)1^D9}?S8>=
z$<a;#k6O)C=XB@1dKb;u2fXn}9U2+isgD=M<}5U3AMi2}!}k{eEpx;%B0y-#%h1r1
z?_G6^m+!sm=6i*7_oX*)zY!!&i`wVgas78;nYzUFKXDtkN?4vN*3Tp*mpDibF58H7
zaGB~}401@;k**#O9+V9~3nEGq{-9E;Q+LeZBT&+((PVRm7P=LU)A`!BEat2kW?Vl5
zQnb)8l-By@@td{2`S`aIc7A=s%C8Y8*8nF-+TQ5*X87hI=P)OWTfU-8{=oRZxlrUr
zXyB`J41Bz(Rq!x;jhc#TxP^ZZCG4^DK^p{2rJXMYUm3;A&`-?HS4S1bJqX?+(|i|I
z83b6j;cF)hkSU)LYc&NwS#i~KwcDvr?Iy0;4g*wS{hW;o>u(mX5yKbCTQ&7C?anrg
z)F`dY!^J#7#%$|5(nxBtES^X!1Ydb*#xwEU*fAsZL6UXspb88AYF7LXGFp~9xRe2b
zj)g6pf{7sCO%r1H%V-AiUnus&3Ejp63gX%E{2qnrNf;Uxrmm<y;2iGW{XXeByn3Eg
zvHZUQ{}P}Ge??9n7v1Y<W}&o@SpHoe+&>l*16|3&OX`A~Xk!cjw!ovAO*Pfhm>vhi
zlm(*Z^HNvwXOi4F8)GMaj{Cax#YAV((aRE_MVCwa3L4+UjN(Ix))VFsfKaZ(L3qi_
z!N4*E`&~~CW%FrX>gMq2Q}GZqFO<Ok38)1!k>>*dl7CylegHt;QM?ZTh&a?BTMz)8
zb_@2Ym+&_b6ZG&b2mXSjIX3*=hzAb^2~|2wKYEeWG&^M7hIO`wB(DEH@ccUMj?3^i
zXbv@*D+UAu3xGfK@$YTsOCX!Em_KFT3_u5K-j5#~8Q@rH;0)8&393Xg|Gbr>v+SFQ
z1w0z7tn8Z_N}}s^2%5{j`GHg;?bxbHkO6*!5>Z79@v;WDu9tFxm4|j1ib5E}e?!Sd
zE#vT+O?cK*@!ZonT>Bh62oIjKX80I<g)tMGRVTND{~%&rLIP)^OrF~;#=R^&b%_b|
z#`q6XGC{L2=8xfqjizI|-}kYeihRC_lEvZA`k|5u?hd%dISUV-afV(+W0q6;)%a1J
zi5YkgBaBKLY-R8;4^U%p_5j0|;ZVAUoB;bQ?4QlBf8NEf1M8LjlUEN=@7?KZVyLtE
z2uBFHPwn|<GdXp9YS}*rvaQ%wfQP9i`W4?}EtAY)953Yrlo{hM1D2<w@YEHtAu}+b
zA3f7c-H{oFaf~i?FzxT|=aHyvOAB5z=ra6bOA9oE&en@-q6fnuU=)Me%{J%accl)V
z{hAURhD@W_V6R)UIrm!(G|mhvt-ShU45D;48lpPb@uQpBMR>SwI{N4$JS-&R5#eDY
zN>~b)@KALNM`Z~Qx8T8p`eDXxll44d!)$E4mhdnVO=8`<$PXI6Oe`nFX9|eGtwF9X
zSQz>F3=mpJQmAw!g+aTO6fArOwr>N1C6p9?`Jj>%Hlac{k^*G|OHx2Smh;(C;tVXl
z8YT?D=EM>Pyt@4jcfx?#Q!}(Xp9O%A2-Il7zo3A80gw{ldy9MlHHYJ4D_=mooNyDj
z%YC+R==7GGWV4i<@CqKho3#j?c;p17k*1@Q;<x@`A}1hVj`_g5l@qMI0mY!)R^9;S
z@tI1FPuv%}-X(7U%suv%6duuHDd0faVrNRW0Krk@`RR*hi0_JMCd<sslYo7+#Wv9v
zTijJPNLe0}4U`YBk_~FGQ;uw)^wj;)ew=L3_(CGt;H0|5vcXF-79|@b$^!t|0Jn>X
z8&Ws2K`KV&$OcE@!6O@3!s)Bnofyci#M3^2T)*kJ0o<nD%-j^cg0*ksH3AN--9S=e
z%LG^A!2@fd*`QU{-ua}axkJ`#*gCIFP>#2h3FzBF+Lnz8T7q5xJlA~F&HwYH@)>gB
z8)3uZ|2J|Z7XN>u*ZhAY7F;nui#CA&({E7mf2c7%{GU1j;Z0iTSQHg&eh?)W!HeVn
zY{G-57XRmP9sZ984_^&Sjy^a4Uj@Ek^MCS?82@K9dS&2=o^k?&-28tK>i2^GA8+x0
z=$o8z&ccIdoS}3yX7hji7~}sOpUtz#OoZ3Ji=FfE`gwRE2^MJcjpy}9hU4P(2cUU3
zuO}3^`fzxCfbWH)-wuv0bOgK}!nTXoUyG-Ny#6Ch2fY4${Bd|aovPft{p&bhA3){A
zynZmC*3IkZ>BV!S-+zd_el9LOF#F?o#p@S9Sx6N@!LPl%eo+EmFRi?P5_$bRH00s+
z=X6OPaO(}|1G*-;_-o}fc4)EjIy`u=HM~>UIQGzSDA_2QRPLpdK;Q*blC%1HhXXS=
zMr8n++wdfCV0=%l_8Q*?w@(FgrwX2hk!TaOH=s6Elj=J;svw?t(l$g@FoIVCBrOVX
zDkuPn0t1!l+mlJ>v*@vSi$1K7Y)9ob1S9B*Zv3Ees%!E~@Zg<1s6J?FYvh(~xIq<3
zDe^c*#%EI_eJRBkoJYF2r5^s*IAt!s_i#4mT2!1(-2w>s=SrQ7*Y+}%*C_t91`|}Y
zC{<SL;n{dmad3Iw!}Czk!eyY2>g)5Qv=Jj?{0JB4m#9Hsd-2SRCM}`z*`rtZ0Xp<7
zj6=hp{H-jEGJ8FY2hYNUZsCSY<>)N_C_bZ4pgW<pp+8`#I#OS5N|s67F#-ePeDdJ$
zi=v&2$r;)&pXI)7Og3*r6BxN9j?k8@=Gh*kfXbTpey2pRA7e`f`_{uLyJ4udyg_Qj
z_8;wZ`dXx^9Y7Q0v=A77dx}klZX@%-{j-D7k!syuo_C+&7&gVjPHVSE-zqc;#8FFh
z3m&{n)X1LH5?v-W&B2OxDLDTlepdVTAWD|6(3$8g4$#MASQhG;15uMcUc{5no$sS4
zbw!24WI7v?<@VeffJ+?Qur1a9F;XJjh~uW6ivW@Hfc1F1TME|YfR?lFf5h83(Bg$y
z9?+7VAkLML`q%`g2oK(M%f^S+ww=fy30kvPRvbads?da)aGT6$KqzbQh%@Vf`0d1s
z5AknK#k-YXdjh^=#32cTlrNdumN3A3ea!8cJ!qL%zBqOf<O@Zq1%4j-4Tr3T(tvyw
z0_c}b(L!@k^3uj(ov}mo$$(XbyE&>fLkoWorOE(ToB2D&#H|`b4!W*d^jP!{!=Zio
z$02;Q;^rL-0W;<3ffhw+lg-P(fsi-AeWt$vsHcW=4oWKe&CVa7mMOY*ak9Pm6A*4e
z#QOu3Rt~eDjR!BYXSN?}yQbqubO=S=$HIrPrb96(tLa&2S`af0om*e{oG+}L5|{wC
z2&r_@Y8)br#P^`ZCT|jvZM;eq(C7x-5Q+zEqKaBC%`sBq1J@OUXoFtHJPCCjPCh%1
zlOGw!$zQ@q+?;-s{V_n9W`W}XKZ;-Pp#Bj2y5_3y9Ns_7<L=xK-@19f+<`l=mb{;L
z;F=~y5Ud&&sMB_4mOB05I)e(R*1qKb#gjvmzx$Z^{})fbXE_G`e-}@F0TL+;g&NG5
zmacaMTb~IwrRhcK5#Kh51$Jnn#F6hlzWct{K?8gr>!rBRJ>BqifK+Gb(~y&A8>KHR
zCOp_U^peY%#6j8cf*)TBxm?AU{}ohnU*gM;dlmh!)P0-v(ybIZkU_$?m4mRu&DVjg
zU?>bXw_PWgh-%F>q+NEbIUYQmID9p~a;0!~`BDTu@#ZIAg?4rqZ|-XZ&t=T{YnZK~
z|5e4!(L#0`V{NDM(aYMZi<`Aj8OEZdDSmV?YK6Ao2mir{GRM_;<$0+StVna_ve9?)
z-q_<gek6yIpD*-;nqS6HbEQLWv{|qfY~CMV1y`pa++0QLv1XWT%-1+#v=elG9a?qA
zoeu`dmR>`&dm(jYEb#oQSm1d8ys-Pgb9EI&jT$_SK;~Ka$BH{&1wJKl=apz97I$ua
zgA>yIs_j_Z`5AF>=X0nTyM?3UAXMDB3{(QoQ9|T7eJ&gjF|n;G@*Ha}Vdu?el$_lS
z!;CqXb6}hZ_15E}G26qK^Rb^{8FA1n-7J{2nLr#}Q3y%Iw>9G13e@yQpSMy%dG%f=
z`h45fE{OgR4{nH7@#k_7qcxOQPczQZpRSH#YANkg`$-1wh@R4^PvafY@2E?@Q^DSu
zi@vxadP9U<y8%$pzS3sd>S|}J!Ue~0p%FII(7s&B2b*!4q<k>tlJBhi{G<Wht=|Js
z|Kn)6hwGQtkzoC9Lp(@N>$fzves#oTn<6}chkw`lopRT1*6+yg#joES1RHYwhF;v8
z^}85qxjkRMrcV;A-_HtqUca@m^{cqjwSL#&;or4>pH}Z?{azmszkZVtU%>V2K)fD!
z&_2Y_zp`@Q<Ib;Z+V?id_x3do|M}PUy^Zp%``*TtZB`qUO9mKziXcW=j<&os)99bP
zk}@x-A2>Qw*?_+@As}zWNM&+`ysAD)gF5s+!Nvhz8Dlal(r}c4K>2FlfGXco<g4*=
z@6g47*|m{LCmQH#BJzDSLNJPq%K2fi74l3=@V)VH)(P$`&_dUdHSSE)YJD$5c7f~6
z-E>WbRVuhD6X|&+Az+A^vpM|Y^?IOgoZhj5CPPFqZm%A7cxqL0{omKGU%&kW{q>cf
z^zpYEfjWfG4MKA*gEmLTX436d3)A+c8vCtk49PXCd?;>5wsF|EwQv;~av;-~o|gB{
zt$C5r$6>6|J7;{?8JUT3f7n664QWc4MvLixkp0`Y6blArlH|4dOFv-r7y8$j@!CQ(
z$Pq8ox9c59t9T4^;isShdM2epOzJEdnzvdDpNRhT4t-};GejNO-#(B0a+{c?##N8`
zVO4UGIT_qCGU}LY4&|Ha7>ZiL$dr^w*3mMcbFhDM(^5K)h1@@F`Ivzm7WdG92gbB|
z&=>k=CgbxNYyUEY4leUOFmpm#gVd1cVxfW!nYs^op?PV`gB-fAabQvbc4mhtK02`S
zSpUfReKN87!B(w0HKi(f<tM5B4hdMS!FW&Pc$cA3r#XDF{T+R!ITkOu%22{+A*5bG
z`kyS680p9!E5;3L;Lqqzt8J(r)i<|lB#bmE)niVoN`};AUW1A%QBE^T97<`{IK4U8
z+P8XCA8h~1kNWsOHPi4LhJkO2%%7m_$i%&Y*Om+8;I*MEyfzBFK8!81;k7sm&Q4<m
zs$?r2s2#QuUYl6T%>*@HL;O-kF6BC60$9gB96#2v{b$bC3QTA7+kJz1>XcMtpK(v)
zVf#scZ()1Gfq<hugl#4|NC?{wd<^>vz;V35r48c)IHWy;@!tg<7|(EE+~f@l+kFiR
z=4c~UFh{E(x2EDpgt><9VeVB_R4_LjAKP&C9Nq%>%;WgCczstO1d2Lxn1VZqbD)z8
zfppB&1lO|C_0^>Vs!E^iLNiNBDJL`r8%_j;Wd6Q!ICa$pKQ4$=fc|{Yf&8?=cgN#K
zqTts6tp^B)Uz2Vwg)>ExcDM55Zw@x(G7ccH6d3jhL8z<=nS_nNvYK-tQ;HHCe?_N7
z$+H5!k<&410AKZ}l+>!e-Br2~gb*_4>-vU%EBzp_%LeTN#Ug>tg-BX?GifaI#;cxT
zdjbt--j1qYpt#*v=c2JV{7xZ_9j>pksO<OQdeS|WeNxC7&X(g-Eim+Ft{rWW*o83?
z+mMLFPD1zkXZnt+mHI0{#TbdL8HWoDsz(c%{T24O#)iS!$Qqv*1`Ej`)8Uk>=xm`w
zXAef8qD5!vZALn~ls+y=+C6j$nhB31+;wng8OmHA{}oJ4wJI0<GZ<Ke&E)wKnRUH%
zBCt%<b0EAekxLKEJl7!@eYJ%zrLHtn^`?H!{-`+xt&YPUR2K>feh7~>@aM<!Z{Hl;
zn6&*ZWUmaa%+=wp%KdxQ`~vDl?ugLi-=I1Gq(3f53|)yb2UKw}v7^qy4ldKE18t%_
z+9JxQqpm^_MkWEitihJG$Uqfo=1BXjH2dhU^n2a^p}7VftC0$o<~UsEK7}tJ?t(A=
zEZyG#c?H1S4ZdVgB)%Z^ir@<}^WB)P`xg;kY&oMj_`!JHUl;riOZ*YwAo!i&i&46)
ze`$jzwr}N7aXrD+r*MbID}cA&q`#@J3I^)%Z4OoncPqwiPvdSj2B%*)jx;G8ITBqd
z93f&b(O(=c9D)7p1umSG+#@cmPlOAnp~o0WUhl#M1GHsLF7jckq0zKpVEN0I8G**G
zbmO!fh#slYp8;#TryEwKvyd+z+1EDd&HXz3b>@cv7U*o8{!}mRbMVf_zswu<82=&x
z2mfg4SNLaUqPX3+NWr=I3i_Az_ctI*6Mo>%RtzPaFLL0#DFK}0U}(WPwIzVwrs_h0
z-jR3&K_RHD(%&>U0+_K_@RsQw{y!3cw{>+{Mj*rRBUM>8Wb*3LOk}t|NB?ZlO1-!P
zWLYG0h?(h@SgtMKNXeY(U2!wX+?jonjQ)dBbL|)Njl&0*W(_XwNN%RIo@M(r8K)+%
z*=<ATp`pP@-{*X2>tSYnEb#yo^%p6WeA}1(c3Hg${7+Ux#~Cm4*ZiFLSVxKf=2S#*
zR;?g`S<Wn2X%YW=vKnwTj(+D;$w>-N2g`Y&F*+32e<B&++rIj@DP=RcCX#HD7tx@`
ztR|3X83qK^%r{|fc5ufK?Vf(<VQp$ocG;Mu=-ZcJ1Hd&WOg6@+jwnpif}KR$)LC@L
z-^Pj-+heO&tWXIJKYo6U7^HUm18uHh%{NgqQY5m!F&Th(e$L?FdmVadJvKM_AJwC?
z@{^Ip3zd*}GGr1@4#d95fdDlyathvh>AcPoF#LI(JNi>D1(*dxFXlzx`;vBN{H%qT
zb7e5pn5U%}#dXyqbE*!+@kLH7AzmuW8vtNpByPx%cEE1~<V`JGJ#07C$@xFRJ#?s&
zKUig48P=e}B9bEcDSdD!k`KzrI&FEuKwN5wK8y+J1`^U+?dlzac3{s0Ot|Qr31S-H
z-Kl`Bk=u33&47`zI(@DF<`?q^mo+ADHp=ElvIaN;Wxl@CV&s!JzL^+b?6{<^gSAgg
z4llp;n-q$a0Zbxu?Z`N0ejEZ*6anLnw4Ni=DVS=EhAnc@ut-UAq~Lg-lr~<6QJjNO
zyxYNm5UhCf$%L=1aqz_rlKicW3cR)wydDyH(xffDyk-TwJd(^aq^$Ne`Zctu_|QxR
z{?}Be7=ik#zGuTngz9$ahfqC;UqH`-yHd2fi%2D~O(T<e^#Gmts>h{NevLAn{c+{O
z-Mk^R@@o|Sf`WNC{=v7yzB0FwSm<95#suB~3;trh`8T{Foy<C3PJZtFDxS?%A^_&+
zL~omcllu<yLNpcqq0uKvv1wXEqeF02pgZ1&>41tCzU|8p%ucWJK`c%49_61KZ=rRX
zh1LxUmt@NvyiOyaobcCpyq@%<MC;xKuVvwLZcm8U2VBAxOxruW&fb~;ub;m5--Oo(
zeZIGNoy{Trr}6s28@t2nG^GTI;dLd>;Jw4^$9Fh*owmR6dMDgBy?DI?A-rArMm$~%
z+jx<AN>_XE`gAv5e;@4YzZ<WgsEFb9xp#W-`g~+?vgL}IqMxf5rd?NEJfN!h=|t@M
z-O<GBWt2c?2)ia;$FXab74Pgn6Rk_I@~0?@8l5#rmVL|h*;{6M+4bolfL?Z8d@I*I
zxZ@|<JqM9;SnT>_Xk5JPIth+S7Q6mZkr+9pCSup)kfc$u>$gzTV%J-*7PLM^*mZ-O
zU6-R0*)`7qiP`l6Vb=>1vFioVQ$JB?y+8|Pq9vPMFSFS7GB3M^kCel%$8kubux!+N
zHaP71MpPlYX8aG?^+GI~V%H7Au9qoxJs)ucF?P*%6}w*6m0izwvFl2>#t(*6>Sosq
z6SM0-!L0;neTs)&)Bnw8*H4o%(yaR`Bq*|LOd`gv>#Vak*mb?lt{c4UnyENr?7BY2
zu5mY%!>>=^FdXQ@&CAhjMg{q{#sL^|5Ow9(|GI_nWzH8|R{Yw9*9)TKz`vOPs1Nv`
z@au*czh;W9B=dH~bA?|Qq8#Jb>+odr>laWazkUXPg<ms&qInqpQT$p?vmSo^*B<!w
zd>6ldb&BBi1!yWd9ny#5*9<6#&iuOzuOWm&Ayn-Hn|`_rn?9^ap>wItrdKK)N;`+J
zWsBd!rf-26mH2D}W@Gdz1mnqaXY`2A!lna|1{2`(WpEYsvgtj*=bKv4rikAzd`|zx
zzX_kO`e<+Q`6j3pon`w^;qxMdxhBTvE^PYE%X^E@ogEH7$Jq4#!sm$`h6kTZen0?g
z-EzGLz~b>)`1G-mUgPljCow*~AbJz{)_*rXcTSGs^AnIdT==|jo#3-|--@=pcmVEi
zDa#Uho|YV(j~Tk&^|}`8`VsJW&$rsMz4_R4KMQSv*&rWI=WrL0{*lNZo%b*XT*HyA
zOo5JVWk_5@xK_|<i;f08wuh@YhKRC4bPk?*^=eJ5t54$Bq*vcs*OTDey<ZPp<KkM6
zy>AC@a$VZ-11z#(VN5p;2g?(?BMc8H!UJponIIW6WH+8zPyH8g`BbM7YfkV(%Y>zO
zfcT;fd}c*w=fRAKfIk{+5%@Y2tz=-cs9>V3NJcM*VYv@(1x&}f4|<PnaGI(1ZL3n=
zXV!HV;&q08kl)?X6P4le4OoJos4k`R+x9hNtp0J@vs7AP7?dfx@9fcc+1XYd_n@$|
zR&=HYWt&55B1MxqKy^`NRq5>L5Awm8OJ~z1i>Vrnu~~ZY9HS%~9yWQav<Tk~LJEnw
z!3NQrG(e4KD^&yY5Y1BUd*X{fuPu^8?5qzMsu=t(TMI?m7S}$#x;P`W&Og}bV+7{X
z+G_;niE@YDI<u>aYiPms&4r?*y0}IQA1h)`RTDIwWsSPONiPGF&Vc3j`$ivG)#5p1
z__Vl`&c>(s4#Ny@LwBgEcXXLCWD27M25`)2fSS`?Ltvz^M(m6a$9rksKZoiy)w~*<
z^dMuaQk_&4$1SRRo<FeK3CxL~q}`7HQjAjO*P{D3JM;TqY=K0X!ZC1Z*7^r>VxOT`
zxq11iWOFM78vH?MM<?PYA$QR%C#Ck5r;^*}0iNKc0GJ;DNat-<Rw55>yn=KU@B)$(
z9sVgj8yvb3`v|I3=etV*atXd&_!YFj*5yRfXRh@*KD7KH_$M)5Y=1{O-sA6X0ElD2
zp6}EgN%48r4|b>fZWp}o%ojd3vFXZ?d-46851jAgd_k7b7bKEC7Nf8xpU4^H+FyaC
zb!^z-atCpEz+^dZTK*uo9;sXpJde3}wMdue0mb1Ef_pkLjRGi@;Sf>)<?0XRwAK=A
z9ghQ2a7Td_ng!Sh?obXPG_Y%T--<V4G=^o<atOJZuWaKua0TuHF0YVsW7K(R<+|4|
zWUK8LvSC+!CctmdX4ozw>4nNYWGUV#Q~B*|x-^TX%ZVsD?jbsAI2zA0Bco0i!g39y
zcAK!o`-d#?Js*R==sHs*u08S($;SX<rze+x2<BUEj5!H&EHdG@+8IfG=md<9%FowI
zF(TW9o*GHL2xB0O#k+|t8FL~>M>mn`YbbIJ`eMT_IEs7)G*x~gvikS%bi|cGJ{S6l
za1WH92!lg#)OW068?lve+EK0|vLSGANNz4SQj0K7I*WW{-h#&PlQAY&hR!2Yjrcvl
z7D^8j_={{X2jQ*bFQW4c@fW#GO7Iss&+RV~Y&Z<tJqFu7^1Gm!YK%d46!97<L3Jg0
zJ&%&|8sVtuH-ayU2q5$vX*WNBcqxP8r$y#bs17`pyGwcn+riW0U>nXO@vz+}u+1~P
z4cqj>@t-R&7tRxygUb__!FC?m!Iv)Qk+0wb5M0CcwWgsZci4*y50a1CeTY@Jw@AS<
zQbfhjgkQxxr}hFz7>lRcWek5;T)5=C-r~XwAM80UG@;LgxZuoL{7DW6HbA!!!-p3q
z?lC^xe6<T74nl*159T-khT~K6EglqHejz3Jl$`4JDd`q28&O@s<;iH-1$R&42M`|f
zJAh+sljC5ONo~5=%wbB3_c4K#Sgx1;xeFbB<5Y@Ta54cNyPZs~ut)|R`&>>Yu+w>+
zOrYQgafI(e2`|ZkD}xq7cw~~}WD@)|h59<W=i#sD?`$uVLqV5->VUgKpkB9rCWnBa
zI({aLU|k)w3j{kC4U%9tgJ6T^RL-Eg$qKx5jY00quA*+uaW@f~ZJXHh;cjA4?WaH-
zx~JNI7P<(f*O6@&nEEp9i$MMKH~BoYkuH4+{Y}_^Vt*5EHNpmrLPfUWNDlkXDi@?4
z!%-!q++N3%C4~;<ZvKS}Qab<};Ds^Y6F|P>domhjE|!0?vwzC>gc%>)z9(CP?{@@O
z<DNs?qr=~VT@~k(<jtTrqp^8z2bA~3(4=@Uozn{yX=h4w(xZ4kl#-Yq3iHxAekgzr
zM(FqV!4HLqCVnVayZumrQL=slKZ@8F+QgnTTOm~?+i}KTW{=%QBgZ3!zBBJjjvKWv
zhO|{={vCs|ZQ#L=75%q;QgCj978h<@rBIs#zkFTsYx+>)7o1WAzbxlhIHkDpi_Wig
z;!Jn|4rI!iaH;K-awOnKfI3`B#IkTLfm6y@eCu{farTXVDLwBPbDF?6r3+p)DZFA%
zD1}#4P*Y$N7Zn%&{I<AP`15*ekNA_&M`bj+jFEYdj|v@hN<h5S*o0@=J}Qamj^%)I
zKd`DNx?@$lZ-UEDWs$iBV8k<+-KX+X(bpmif(K`>IcJY?HtRAM&N5Wg!da8IBs=~p
z#2;jI>F<Nx;wF^EU*&YSzlz{PlSNPC@L>$TQ24Nj-;(k)*$~c<amW?6;|jIZFqXh^
z#R8gcP-Ptv!<LKkA?MR^#h(Lr4`k4~O5ZhT^@d%M^ht@&5!w>vy#fq^!s2^nSb<f8
zOS3lYG!7Z`CO%1%V<){M+M?%RCydgzL2varQa>`-nD6+r9MbJE#oPSSOP%Ip4cIu{
z)vpDDjB;(Ua2m$4$QYNpA^I3j-gImklL`lss=rf-;%l@mWu@zJ29vAObM8^r?+Q2`
ze9#dsI|QR}Tw0V(EF&V-9mf_P+AXh^6R#pvh*!%|=mBQ39D23%g`UH>&~a(`lt`~!
zTELqe9!s8E8Ryb6@CB{{U0T+mrtLto1hh3~LWR)=9wN{<MpBOh(@PU2LS_zCDW&zD
z6Nf-O<hZZ!pfG5YXwHl0Aa^nv9n=xY90}fG6y%iiCY(B<AE8EY6lPO=8K?~Qb{rmg
zFv(}vwvD^7`an9aAYw->VIll=99NQ8_Te=~_4Hd=QULG1c?LXA>D@P1I!nW5uzlvk
z(_bI-%7*VEslRnjIY{y;hxa;8$ned>AE*!N#r0-R^pT6PDk}#U*Khb5Zt<9&Q94I9
z5U^J~C))gTz+UkjIM??no3D)EBW<B!Cj8j#@mohd@FRSj&YrX-rGK^{LHEsxZrMW8
zXZYp-RMw73!xBIcw|!N=A9HV!22$}H3kt~Kw49&-mxl}JM9gOP2~Zr4!2~sEiK3tO
zC$!lPE;h6w%>~y&rYM`scsC&6b5{`9%-;j0nRBI4yj)J=laUNxlXCsQv+J?Hjz<gp
zX^<P4{wzaKsvezO<(p4`mbc_7rOH>&r}cQM49tg(jIMIDmGR^yWNp|+^KH@(*KriE
z1{I6iC8avDZax2I5(mfAs0qj9&gj+G+A8!9`1q^EeUdCXq;OgJuo!_f<;DVS1Ua)8
zg<EsoDEtcM#(lxIabpxx3Jza^Jj*=1SvY(@Za3_@s)=w|mi5ZZIr1(zTm%>Ly~E*O
zJckCm;P4m76twp^{7bmD!})CQaCip0{@=#oEf-)_y2s)4v%AOP`cbj*?-qxTLcWoI
zD-NH;(Zq0ga2lb_c7p5yhs93zCAnNY4iEY-!QtVh99#^C=ix-H<PpK)KO&ov2Zu$4
zSg%}Gs95kry7n*b!ikR_NHkt%apIR18rz&$h@D{Z19vI|cLh8fz==08dWFVE@m8_d
zHHO9XS#fdVxtDP4;;?cAdayZh;4}{w!{%ah;`dm~I_)On#1B4$1_g_msnq7gKZ2`4
z%t%U3OxKAnoOmA2nF%=YBQGl~o~MO!(Wu3Vm)V?nnU@nYR^P>m7sGcMSghPqEKXdF
zD)dRA`qS}Au{d!91X0C_7a*ohIPrYEG77+nmyr`w&y;`@&lm3FTSoq9_!i&~IB|n;
z;(5^{&cmtziyLB`nBJJF{JD5ubTs&zQ9MsL@xnMx{CPoa{0XsmvBQbyMJKc<ES~4)
z#I~gyoY?kUu{m*lj1wQiX*rzO<-FqZT`A{S6rj=3^cse!IF2hetl4~6+)Wjz3Bwq6
z5o)hC@AvTGA&GEUd8$kX15|wYWR!#tFC^!sX{CBJ_;3TCUcpmkU?KP~bxq{M49hcj
zp<VFdf8bA7KCJdg{A*Hi)}gRhF@b{<9OeNex)nl$!r>?%-~DqO4lDN*@L|P)7kfGI
zWyoO=L*4a&S&IXUe~KWZ;O;v?5AGh-$68Nu9I)3j5$?)@wqD3FcfsA2IF-9N@E+jq
zKb}H^U2yleXYC8_zQ1-KaQCa9#$ey~zlFOOor_iJ9(SwZ_1qoqp6(j|ZgID^`QM7W
zf6n*d?vwCX5<cO9wFI~;{MRomE)I7G|CiuyJ+5|f<8C%i+%DW5_=Lh;+vj4*KKP-?
zxBKFUVt2mJekiVn_Jbda-J1Bb^ytUZ)eoij-zM-wu|MwhdUWH5vd8Uo?}xIaSAHlT
zf~t4phq7dE{ZOX$-VcR&^WgIW%SUyw%L!$y_Ut+;rIe1Sdnc41?am3s<Ab7?&aHyJ
zpb8m9s*C4@))}R9weVXU0X<RX88gHaWvv$BJI2_|kBmwZi}6o}3-9<LT&WEoB_ya0
zL^*~C3aTKE{TWiT#yO_QX^nS#SUwx2$WZ9dh0g{;dQ=;jAzd%3O6MBIvpXliH)Vb`
zhjgfjFjdGe5a*b348EpYi`Q#I3%`zDY|jlaa){)%6OJ)9Q)VXqC~LL5PJ{u&8Yuly
zWK48-VXMXSVgnL)5E+c2+O8^vuY<c~=%ba-O=(6|>7AI`u`;y;<HJJu&(%AseRpy~
zZch{~48Oomc%$IX7v(r&yQ28!LtBO4l+#HzN{f>v=Met<22X2zcP6(#Df&VBpDgK(
z|H;fa{}bn<UihChb@e|{pJUvX3kLr{Il?uf(98+J>xG(|JKu5pk@Wt%!5;q;XSmX3
zFZ@UD^7^0b@%Ia3{wMV{#+W3_cL$R)3R0C{45#aQzc%R#<WX9;DwS~!!l%k8Si)Tr
z5s;Fs&+Dzov>f6TM+c;d=@WDWseQxGdCm-e%=N>!g=y<LTb2E^=XV)SJ@lPvu<tC{
z3M9LE0(trM&B4aZOYHWCHK;joTI{dOTuT01=W+?~z2~`DYaj7#C#~Yl3b1MRQb%vS
zTrEb9EJkdv;_4HkiICBs_pZLP*vG}!?|I+SoqZG7N~<o&al;y(2U^e0z5=GK!F5i|
z@WM^PI+-ON*h*Muz{L1EIe?+KHF4JP%**y{4bR%BHf=X+?yTV<@%8s?4WU%<tYNuP
za3Wr)y;ivKA6UagW2P_LQ2K$DWkXF<2_%cYege3_1&+Z)oRpNo<Y90hx0)ttnKuS_
z+hcu_aH-yH4t!@b(;^Z#LINCsLwhDIp>VzhX$IM}SeQUgj6Bcn&vR|M4z7uRL9fp~
z631Tq3cj=Oz#I4qwAl^AS0Qy=e;7?j<gGl8(VKAOj#fP=KH>@Hwi9RQy_?$r_uL5X
zdoi~Lcy)N@cEb^_xm}5e9_RK@3Ffx&0cUOn&b~?b_Ho|1MJep4eS14@-{NDp^B?8D
zX(47GS?lY-zeokyfjQ=4({ixm*+?wTozK#KD1Qg2D%(({H+z~!5lZ&dDD6PP_A`S0
zVYHLoy*|^m0$1Rnn-wUa+q~i17H*hv@Q)_<#nh1Ix-hf7KG<+|`xnvMah#6+?tagi
zjEpV^JWV`d!J!?t2ZST%O9xb<O1e=-&X-D47T~ROA`Sx}3l<-;`4Z41M=`*?YSWX)
zRs7<H*kOFv91oBz9b!y$Fzz`lm$h^B7II@;{LbAzj|c9p+`KAO4F+;kw9p_`O4UL|
zC?UTb^pRh!^|i^S1=7oF7~;I`Flv)ptvl*Iz*7*ZlVhkg*zmRG`Es?8WZn$qqBVk%
zQ9Lx*4?0MNb5`(y;mghQwN3jw+ntM+s(h{5v&}~F*6Prq^y>~aR9qS<X|CMaZ~C7i
zna{$RJyKE9taoUCTRp;;b6ail<~(0^;O_cs%FD~Qx3AopvU1n)gWl3Np&O8sql}WY
z5hdwba5nlc)JxLV`k1Duv(wjR{uqBC`xb9ClCex_C!q$SGFrKxc**lX>E_Oo?EI6A
z(#=>H)W+*7H7Zkb)-0u`m3UT{*8~G?DO&hw)CzubHN};oCT7!FvowmpO0yn1JNA{O
z5A)97$y$xfjGfW#=KvHB{5?R?($5D!p6MW}5Lo}Q9wKxTR><0JdW*QXJD$Ma`!Ke9
zEq8kyYo@Ba4FkRHar>?Ij*DwA9(;<>9$VvG-bj9Cl#E5_piy!T(=C<2L2Z#yay~q5
zjFL%A-%xTX-F8Z@K;k*0WC$|S86`t?ctw<)M%UAl;W|>ZmE`NCEk;QJ*4-!=1<+jU
zYenOrC#@hB%$Agm31$I-@rwHF0TEwYFUiOehdX2>&<dA{;W09DA|S$H5=Y~q8!|Fe
zTp{2aLB>=vpuHhF_H1m|g|*x+XTS38m3>*#h32|&^C_rZt;KyDMfYaKFYX6(?ai9b
zk4keQskOExf9fC{VK2=&9-d<Moh+Jb1{dPNH3N984so!~K1^D-7z{zxD&H2&2dMG}
z@m$s$M?0|e_DsNQE8IKv)2c@5#jT_B{5dz~7^zQJC!OirQt`fVlyzAHFt>AJ+Hkyk
zm35|Xr87&QHCej@>C?dzm=!;XN5gC*|Muqq=AFYDKL6|X4Uyk=K934X?J39&m3lAy
z@s0dhuHVPyeRgAt{#oIO($=YO$D#9deCR>vt$D>;wIFfZnp?>svL-6!Nf91mYl1)%
zpyRO4$Z1Or-hgSO-cEXxnufKoSj%Df05j4;voOF;EJJB4hNvHy7igW{B$K<7hgvCx
zA3$qy<Ez7GuJIZEt)q=&^s-h?GW~wNxNTU2%+v_9$x>X@nfK1rA$jj;Vfc2TF=Q`k
z)iX@G4Z`nWO#7WRuGU89y)&)F8tAVM#x(5<hAzd!7>5j3EHaAQs?&#66(iBEFwA`X
zKHRs}|9dssC5kvsoo^GN_J{3~iFj7Tzy1&4`>L^h>`gS&@m8wft}~>{M`|ncW(*Os
zsKg>MlG;nI)-Y#jOdk9M+h$?F`zX3GAf8;cfgvk$Ma_YYR5yCtdpOqKy>acuW7KT4
zM{+fVpMYG|kR#}&l}61RDTIs~s<8CZDx+qe6z(!==1ZZ*s97L|*+vbg$he>y1}#Ai
zWz=x1VS6%a>ZLH>s97e31x8JS6hIEI7IJv4ki*GB4yOn?tPpaD8*xDnXObM&RLUpo
zjhc`YnvI$&DYO_hcS&KhQCY)6choT*KSq3&dqy3%AIughI2-;}WI{SCMjg{|cbY>T
zcflPyhDR<DdR8MB#_<)iXk<qF^U<8qfT2@sTr_gl$60Deg`v%dR1UuAN-**greFcd
z3KV++k`-W;dKlg%@Tt&3gE0#mP>Q=WJ1y4iwQ<eH!^*YNEG*8_Yzt~T=$cD(9j8Ym
z988Ht!$34P>S4&Aki~L>t5Wsa9F*xVq|olgezJrrokKkyVoO*tWW+;kYFZ9(HN383
z5ZwBLX{q>Di3zhBxmK=q4R7>sZGWG?`*V}usXkJBcBc{HNUKA6N?g)Hf52Ac5A>H6
z8O6EPnMZ5Ser{J8W>-n!4k&7$@6$q$@r!d+^3h;)Wd88!ncA}ronQ-hj!BYxp->^I
zCRp5-T4Yl5h<iwmtg3}KyL~O#yJ;XTVZQLcsi@2Aw&-;yPGv6YRb>7XB%?+RNr_%;
z+{&;8u?sR6guX|NT28AfbSB5F?!4)KLQ4IZ3|JALqPWJiP$8PK8~m{}hyzn+x4q+T
z`7R&u22&$KSTjaiDj5417b$JSnbbKX?Eawo1+FAf_*P`T0i%@#D0BN_!mG4rJG$)G
zCQK{8AGQ{Q;4YYc6s)hxyZ!1Fesz!*`nCNPl-t;_Hi)>nN~0zRG)Nf4vMj(k{|>-<
z!z-(m+Q}Xd-Nlm6;F>S&xj;06J3{y^ObFT7$I2-yqsaUUleL)g(gSe`45WL3SYzaX
zuTo30wa`i)$^1FNHB`E~h4zAe9>`JBUM`|EFf<uCN6L|-o-=al3e0>QI@PX#Nl|0z
zndtGZ>JWZ{4fG-Gd9F(Td&}qcT#L-(F)bH73^3a{ZwEjWf2qBe@S<2u?PMtnm#Lj1
z<#`y0URxn$;Wf20q`W}h&y?~)mdU3S#{r*G90z<#aUAd|#c^tk$_7^U%~mS~?_jP}
zw!OEJFh@hqAd{vdqUTAg4L;$^*rZR|<(?x&ehByw`61v#<cEL{ksks+M1F8Ii2O}P
z!4(Ku>pC7K#Me2486d_0OP-yb+67FI_U%^m-L;`ZFk=GkJgA={IJQway?X@w`8In_
z7G!=OU4qRiaWNAQF&eFf(m3lt8?x$!zr}?=kmiuVE&Mr(77D)KhhHlKQ+YGfE1wRh
z&g#PP`e(ye;v-zj))jbdv^&b00sid43_4%~vGhR}LU)Dp5eZsGrp^HMY0NQ`VP*kl
zaW1VDvQ`MPrnFN^Poai9KtWN@tEwO+Yll6iA~Wf0LW*#vk&?CVMW7_p09}W_YNd>n
zNbyE&m^fsU(_kM{m*B7X0A-P@QdI_J&G|W5ifjRLsaNfJFr{hCnRCzf*kGn%VBOQb
zeAhCm-g<6dP4<RQV(lM}_C1qbgF`<j3&mfe$#RmM>{HHUO&mCS7@~V84G}NQ(jGr>
z({jOfs=IrhmRhzs|B6j3A4}N%vbo{5{Xw;*)rGRxNN*z3{~i7&*lSLk(_avqz9#&v
z4TE&kcYq2jdR2#_qUm`midz5uV|yylM?pXg7hpc%Oej_zi;=l>fkkG?SNP4r14!((
z!%2QiuGMSvr7&5qEs(+#y>^roD)id1QkbFFo+E{sdTj{{N{p{PU&<j&La&`9<tiy(
zD&@PRd<Dx&qz_+>vRZHG3km1hoIJNO66R>|rnjV9ZRRx&kti~602y~p5IPuSH-HXi
zuIOOqi4JDI=wP75DWDdII+#UW$D>I19A_{V=@wOtd-H7iW^-FA%VONtyr2BDdx@<^
zhD-WU6;cx0H{7A_Ke)Wh2g%&-Fq@z)U`6M5on}z@m%Kv8#D#oyDcQDD>wdl(kD);~
zY_{U3wZ4r5$DTQ`e68>G;w1B0e7~I7`y53M<AqE#j@*zF_?pn{eSIcgM}Ls#+-0*2
zVXJO7QITI=I96Ch=xvb8BJ*X)Qi_f+q2s|Ai;X=*7basB(m24J?@(7(Z2Qhzaj;Xd
z{SVHGehHV4m)Y}<yD8f+vWJlJ(a~F7YM-1Ahv;jRy7gAP_|ZC$G5iKYAxQFXmrSlF
zSKFudAU~qs>NQ($_56|XdaH%sa6PQssvg0Ei|K}cC`Xhw_B0H;(8>bORO$lG->Od)
zzrNc0X^3|`TlL1_rz+nYN;C~IW|i)>TiF;cvuHo4rqj2zU<4G<6C#<s6Dlc^ez-Br
z2xJ?lEkUM@J`jT;$^`00oH^|^eS38&l7ZF@&pe}IQfF}+8jYM*%a4rwQ}sORh|+(I
z01o{SG&uEd%y>XO_*N}+1_p%m88BZQ1ta)~LMWs!z^eki&{jx~F@FG1!u$$E5TZ62
zoZ8o#H(U$R5jJl|sunsxni&#2$Wo%msq@NqajwuY<!pFYhdM0u0*I=kz1PcNlh1BH
zQqGnb`)2*L+Y5AG+vpMgtvG%vy<Teqy<RKydZ;rMdcDnZO4ULXJmcm=EsASCs2E9&
z*jv8>$)Mq;dpyHs{H?<_atw(yetP<SQ1`V>eNTDIW$@e*XiL_@AEN}-MBZ6i7?Xsf
zNuDofdY{2Q5pgXup1m4y=H?Y2xh4-w(R!qSa^75yHFki>d<y6t4gJKO6KZemK9(by
z(gW|Ky~lEB+b?Y)X;jP})twDDW(y3_hI`lnSm2n>j=4E3?B@x@js59yHr%0iC>>jb
zpV)p1_91x>?6`Hb<Kp(a4kSRLgbh1e={5w^lX^wp-{B$}uj8SdRKvP7)uoaOHj3RZ
z`q-&ZKrKd!a?#P#t{XSs6CmyH-Fyp>3!923XTE!B+ij$6x4Zd%vE4P_5Ad*?`9A$)
z%y-qyg!7f4#vkLb;+pTa*#4Sv`&$_o)L0Ty^IgMw{{~xcCg_{)i|VBx<78v_K1L)N
z6p|fKNan>9lJ6r$io-Ns$3xHSk-+Zztg`!755q#;e~aRQ`-rpuIlHfH;SI^yLXX{7
z^5!UuJ#8ayEREmAYG!&?cHar8s_edBVoOm1lhN?58@undUt+a&-+R_E`650B1MkuD
zYvbP#VR<n9wm1zwj#47iFV3CH_Pd_8-*hxaTkN3}E5sJNqyZvkDiwkghgufkM-y0p
z?^YJzJG-#}XDT)1w2R%BFw^|Y`yIiDlns}LBin{c3Er{cj>Cgx!zB;u(T3apX!P_`
z08_r39J$JhceZ_GguX7OSQn$O4E?d_>uqs67f)ZCD{blOV%AJmLCRNp+dDJX-YIeI
z#X~|R+9Ul+=O>m47Y708b8rxVJ_iQ@=yPDdfIbK2T<CM4?YTm<Jvcr<+k@i+v^_B4
zLfZoqF3h<w;liAY<3qC?A6jg|Es+U#9*+=8$<UkQTy-X?!)DxwD%3$;hg#YSq3UNb
z>hL0xfIHNo9uM76hgpq0eu-iod+OM9pNm!?XL>X^o#fMzjcL;ryxR@|-YXmbB_<m`
z8Ydgaul8X~fvxavsx2HlM%{<{LqeJf3F*TQO9{5?Gt9)kxbYJ_crG67$*jAQU#@`|
z2!q1rVOuQk4Q9>=Y&HU0+Yg6uW?&(+XxD8k$}7vcaj=p4K)Hdd%{waIGc?UYy?nSp
zv~*4wP@cC2IUFjQSateqMqslDWp_MF@KS=g(O20~$)KkqtAY>^I0^5BBn|uS8Z>XD
z-icq)U~~d1<aMA$n0GshMwGQpeFs(FP|Du{w%OonwC=^();xc!76kXgAvvArp3TU)
z;w;h2cyKQfE|Z|7SlYVbJ%G%xjktVgXC!Me4AHQ`rp^MbDL3-r6iCY`M`iH)ytSO@
zuPNN)ztn2IPoBSRdXxT!%=peDNE$>S4WMmH`M2}_6nMV378yU&1CXn;jm+nnOA#ul
zYwzVo<gK21N_kD*7g`u0?8>&=2HP&807-vFw?9<lo@P<r7t=Ob^V{($zF%vdkJ|Cz
zzNo$8FPIyqaIsbSW&V!LfA^_%w2ixu*=N4?N1_Xn!aREKNwnv-0{WB8p_q^TyIG3?
z*)Tur<AwO$vE>Tg+PTw1w^9hhisNjLqcibzYXGDXWy{^jniews+1nm2gSXpzBCfr7
zOlkttCf#D*f|xDW(w*}lqSwyk%q)v8bm#N<vJ|@W`BH%HTvY6((4BLldMRwYO1};p
zZ=Jk>jaTW{VdGW$b=Y_t<R?%^Sad-hVbKM3oGjFFicm*bbfF8MA=D8T-3HsD+h|*K
zVdE7g5Xhuu(QURZy4?^<9=0Rl8JN(X(aVdq1oV>HFE_oc{TD&h0<kJQbW1O}PI2@y
zqy4$)s9eC*c}RNh(92mLuUES)P}2wr-D}^y2`YOFaDIa#_&sMR>V$Z}`3E?u9%kI7
zY&UCLz;k_<W>1JUdsJMr@$gf{X2lh17(epml58!#2P+Ytg1#(*3A?Tz2M=Y@y_U$q
zxXh~|29)dJ8}V$d+C;tyzQ8vwNvPta5f8DkX(vD;!kYh3S#}}w(EV*zBiG2W>z1{J
zxA@;tcHQFKNajU`Wa#3uXiE-)ik!ijdhONhqGV|PKtqZZKP)#6E7xn;Gl#aWofJTZ
zR&lMe)sDvp<uygI=3o-mmSkQ8jXIk|V-_jM_f;H`e{RL0%K8f%B(1+K`k17izHQ$?
z8IC5qTAONb!d`mFnTc>q=(M<p`))UV5GQs$d_GY@6sr1xMwp7#a(y%m(`BBX;AK|Z
z$~TZwYTKl6nqEuKAId7V*fbRK^;(d96bkg(Z7e|N83t%!Z`*)vqF%5pXrlHEvqhqz
zC^G4d+_U7OOa*mfidYY!2m|&ttI_g4nb^8e;an*rfx<Z?1t^@WqyUBUT~dI;xkd_5
zID>~`*ibmnVWFlHprY5#m9kPe&y%uJIM0{zT~cQO%a+1<A<A86N_32bIT~lCy|op-
z1SKQlj6wJ~(*`xu7okp7y|~rGspti`zn8jwla|;p_3%mwPe`CLo;@lhRrot9n3cBw
zJ7{Y?+WsH&x4x0u0c-#{WH6Al7Xj_~o4O2t1viF7BJ%q=j=%OE8~Q(jjS%)&=-Rm+
zbJTh~1GRAX#%Z@%rI(f)W$t)gZd$(!yo`O-sJ_Pa*cW#iQx=Q=9`$vd^c8})6#J@D
zeZ4IPQR0nzpCKm5K6^}95z^CM+G@Y+K-F-CY_)JfY&HL?POqgwHf|?hwsw*`y1#ZZ
z8ya`8A{oUL{)<uYuNuXB__g~j^%xl8Ji0rop^P^N%Dib4(#4H{J<@=$dYnQFKwk$!
z1%gSh3BjDdHSe%M@IIJPb9Zpwm&zz;tKum5SB>H${A$z+ao=a_@p4khFb!$SipHKw
zoSrH<4lubkkaD=5$_YiXV}Xy#WGAN4;CcWzLJZ<=6B@X@z<Dd31aN-rooCCp1oCjc
z42Y&b4v2p_bq?hs48<!7jNzLuqJS2n{n_%4xfaD>U~7^VzRa4@VX<a}Pb)hQnRBki
z&9(4&dJu@0Q6hg9H_2d*soufY<FxcD!<X1PIlbZ5^t!kDy3x4zOL?aBHAI$jsI`>*
ztDtDU*j{ZYf>%i`tTy0o=jgRbs6<^vEtIq<oUhlWNnw&+n=XY*_1X*;3a(HtcwIMN
zF>bc#u(RDWZiRxo#D3ZWhjc8CZ?hWhS7K<iM{D`{EaHGIKc6}&&m~;e)=PPwl$S|a
zP9U`nQkFwVZKISIN}VPt%Tc6uy_DrNQrj$LIgr%0NLkJ#wVPR1Za?9zD0iK{;^rKm
zGyUCjb2a^M#KoZziXBeBNlkw{OouL%=Tc@{!7_@;?}5Vz?VY>;5m)P=gL>7$edwU8
zxL~sp+nP+Y7nZeq-z_DCE%}IjEyP)keJxUborJ!K%6GTMQI%}&hB&s9sxTEft7+9K
z3DA&30onC<p~<;{k!lE9gRX{`M(}RO45K8~NWzl2ql%A}k<G`6k|SH7MplER=^o?V
zj9Z0A^el&}{j4)F+we@F3mnSWS0($B^NALIm9}TP?ZNqHWJZyxac?l^Y5(BTV18+s
zCXOQwGI}n}Q1}*xXIs^_Riz{qnQu`n!$)WJ@KHZ4d^tX9U)TNg>`nH%4D`aUYhx7s
zBL^Yk>M^}}YAJmf6wUdaK-}o;qjC1b2<N`z5N}0w#c1xKx}j>w7DeWP_}o#FoQRP}
zuf9rbhAKz7eIngrVx2s8b0)g84!WyR#1eAb__s^C$gi%$sFZH-UVh~<oX^_+ZCt>|
zKi-y8dms}a8r_Ho_o-bAGjY9jh_!6pwwkVZD^0^K&^uZ7@mkfAvZGhUw-jnbOOZf2
zyZJSKH2iJ6yR-?j7`Ab(Z!@O@gTNZGqi?3^cG~%obTNrXPV0~03fR%1_Vd;CfzwX$
ze8abOMDn!P$_?Kd8pn%U%JWjSii?!CEs{?&8WwB>whj>&r{x)e`T7|&2QLJO=J_^j
zp`TzlacaT~@ydPRggrm#Ye_M)0Of_|b@&$wyA)jX3)@0zYaYB|8Bv%wK2-~KqPrR+
zFeIn}2Y4#CEy$K)?<Npb9SXr5Y7kqs(4Rm<9dkO>skEqXZD*WJ8}+FYCqsLB>on+7
z7mGf12lT1^ZKUD-Bh8{uMXSvfO{_ZgHJa7MxiIu724wBaAHz^8dTi*od<iH}8e%=r
zifrov+^LXV1H--2tVVa<N&rM6rp0KtZR!WuddxJ*?2BP5r6ttiKyiH5n%7qg^8%2b
z4e7SG$fNi!dcze^^jvVH6AWVO5EtMayI*Y8|0itd*1ZHsvsIQYckZ+R|0RTW3*6dC
z>&H(vCZvuSi5rm91pjZR>grqUgd6{_h_kGIRSx`@E7)E^%@JieT4*))4)KUBK-c!$
zpu>UgT?_pcFRS}#&o))hK16)^k^b#FysO*^FaEzv0dD+_^69E!8x0M7Crj~t{sA*;
z!5c(RC&+O@b~gbz<yw&j7#5alUmNblVYd|{s{3otZm13&DP1;HjL07dr*eQ#_2HF)
zj3obCM4z#lBgPKUf}f)AszW;qGWn%{jiv7jHcqy6hX*>WWH~d#s0*8$#OWVtk}DQg
zsczaIRCBIaUfrk4w+U0`?Rz0L>xPQ4aPdd{nfX18qQ*Ef)@FmSC#01wZt9$fKmwz<
zsY0t#-&L(LkwUk#W>^C<v4P`L|85)z|K!-`zD?HmRj_6iukW0ICaO!D{ORa#ScCZ_
zKB5h<&T7&06N%E)O-oFk*E!*|0xi4-)z<hjlFb)Ti2elWpQ2fZJF(Z<2nOc;U)u7r
zY$HQk?q_JD#JTtC@+{mZmd%Lfn67?3)*MM-4BQeWCnn@@toCJBg)iV1`Eshl7ouRp
z>8bAnPGdQZe+786m=y9L^a!LAuC{@c*}u`A1n|87o~ON|W9`vz$qn@JAzsOBPt>q<
zJgB^te$y|YR6V+|%GXx;0!NKk_wkiXq00BqYME4(?}IhI55Wou)Cl%(!yh>TSE6p@
z896f}xii_;48(0%(L4Hf3EnZpM^k?TnQn$4(+v}sur7$RxO3_e9zmfQHKdTY(va8w
zVtq%|Dt$9Fx9CHFxyByMKiBv^ND{v-#79H6IR6bS3E@0-AnM{xXUPC_5E_jhc_=_(
z;3ZZ%u=a)a9tJ-?hpGDj50crQL`4jacf1=<RA$Kf3Q@T}Zhhm`+<&;z-mkMzQ-})k
zjX;D$OsB7<{q&l0L*Xxab@2CF)F{^v4X#Yl$7YrnYN7Y>BDgw5$j|RlmWf%iAa6$_
z0*g}GzerW9sOY9j)hcM2uYs2Ns$uJlzF7Dy6{q7I7%bw1Kq*MeMk#LM<DKZKvPG24
z;)#<rtnja}w2FfV8_%)mj5U_1do2AedQ$~1Tr#w}v{_sJ5@^B{e2zOtfUcQr$jJyL
z*sQOTJ9(m0F2c@TsM&T7`Vk2pBhS}<!{c+fw-z4DfzQI@*Fi-Dj{#T2V*!m{Q^bzp
z@g)Kmv&d{pb^{kWIJsgrgIO~*M+`N`c-v#>zC{<3;@XS1(&Vu{!Q(A9e8d1h7xH0i
z<qI4+aQR_Em$p32M|zU5%-Nyb1{d28(5H>ltzMiaxfVPHP7lG!n0S^3%ZI+oh;Xg+
zS8-t+@tNtTY<%VkT95EdO?;LEbsp;Th5roT^GbcQ{?e>QuDflEagFFbjHnF)6u~Qc
z>A~3lUtefr?kdE*)>p>mQp!+yStR#OX0SEcqS1K%svt8(tF`hJ$?sE~y7=t?=QqL?
zF2GBxyv3hX(Z9N=BG{NA#NL=T6Mj&ql1f$_UOoD!RYetRiu}pe&x-DB-DuODY^<}Q
zJMFJW|B$ZyQPj8qA+s?Mj9;E-sBzH$sTvrEJWZ2khPPClQF#kGIs}ZZdeq^^29+0~
zq&V9a^|PBk)ur2rzHrAydZq%Eq@uGmdKx-Y@xZ~4hZup3YMAPGI?a}9&wf@NI@OXR
z`rB7fk`E)DTAQ|f6?PrWQAq~OsMZQ87+kozv~~EZio>eZx32H>9WX+!K>l?lgQ_`t
z*4B>{SLNXO_MAQIE%o=qzG3~Ci>LCI8<Q&14Q?CqQ?2H_ie|z-cASy17VJQ_MLe*}
zb?)Dd*gw{bes>TjVDCw0;yr@@rnN-{Z1Yf1DzyRFw2`?;y%b#{&9EJeClwSF_bAE?
zS^sDQlxm$`oWYED*fxAsH1wiN_}y*JcYC^i^_f8@pP0zTGeJ*89)9^PK#3=?cO9%S
z7D-u-A{N9s568>HAAm(7B{QknE3BHDGlj0H)6phRWLZYx<j8516_WZ)NjDCGu!pPa
zLd^6ZTsa(f-0<d`vDtk0{(<PUv?+LVZjx5(draQ|oW25WRo=u)jNZnt6d!yGaGc?5
zdzT_Ou)@RS19-!stzbhQ^5vo#qwq9|ysihuz!96eIo$a3D2mN2T9=8h^-;-(AD&K%
zl%+@fne7L|&%CbFS6>-uNdhpG)@jQ}9kDgIBUQVD&JKW+HNKYQV4%Lwt*-|I3z0kF
zEsTt{wb1ubp)&9&O7C$l#ZAUINVhHGVuQ0ezNMUV1>_tU@>P)Wd3cEV(pU5wQMORK
zogrx~gkQthpy>(D*p__bg_y7~b549Hey}dYSosvQ<RVSRj!w0PptHVKd&`Wm+w|tV
zm*BtCM11A9oG^n%GjpO7aEF2nIQ%mX*w<#1Y=f6p5iU+_t_(b#RFR6(e0&H?-2$%i
z@WZ&u%;=FOYfP11Djel$mY<W>2cblMs06Z+#)6+~q505;!;Xr&d4)r?P%R#@5R}VV
zhpRD>9Kv><^5LP#NsEA{7-MZajmtiZ%4kkB?L>@24e8r~9MW8)bWX5QCH}xV!z4Z%
zK^`@Ok$wA!$$*yX%#<pmEI}%qvD+}o$j!+kZc3fr*BF-;UU%yeh_JKo7kT(#HrI+e
z)x|AU=^0Q(L<+b4^nA3Tg~wr)Ix!t@@aq`7b%jkcd)v&H3I61KQ&Ea#deB0b;i$<P
z7fTK9DOG1yf)3oM&Q<>CH{4P!d=}W5z5|Olyzo#h^bMd35Uw(o^X?OU=kSulv~W6#
zvf5#B^a(U0`Y{w?IGeAn+u2%+w<w*n<+fKBH_L3>VzbS_yexDv`%&H^R%LTwrRb92
zJu;V1i}?gJo{`O-|H)y_$YluTTPPA+fOpB}x^K`zan@HO4@UB$8`NCDjc}$L27e8#
z$k>;#W=vv|6a6WQ!9YtaQ4tU$uwJ{JbcBV_3^W$*L^4cY)>j2=@EW{OxS3>LjxrnE
zzRuo+f1%{sgz&j)VDO`@>jPbt`j($GI-fl6{Umgd)##&m51$L8xWSl!sOZ9ME%YfY
zx1iuaoMm>*$ZJ><SBypbV_b&z8ky%6Xn~72A#-@@nOgWKTv;zby@t(m0n`{13cb!6
zwZ}W@j8Hfv+;HnrNa_Jq9cWjwy-Qb7!^5r!!DF|Ps^Sj!PO}&z6k>Jfop=OMV>0@g
zC}IH+uRGV;Cp@KS;cQf{_WdJ2RSR8&DwTo9fXE+0!J6Mk3;zRuO=RT9*}A&;vEXOP
zRmCmlCwR%#y945yq=ag4BF68N{;)P$=xY|On3@Hcp=*6OWb+36&Q=Q0io%`KQF3it
zNXPV8<2cq>B><Q;JVOirmTNLH8#V*k28<g6vb#!2(A7_^0lx;97uD6vD7m|0a(Q<3
zG;64?a@bX-bd?+HigCGiS4<leH!A`CS77SI6qC$fVv1{gj}dp=%q{c-R3K^27Sh~C
z`vR!*;r)`6%tP>#Y(aQEAh0s96#%<RO7CFj>QR!#8$)ZV;x9=UGBmcsQ;&wup9|py
zu1;*W3%H8RYxybo0nTqQ(~y#{`a;OGc`3dY&K91II%XjovqN@H;JktK1-R?2#XK6n
z1LlG=zDb&Kh{ch=iIOa|Rt_JEYzX*We(Y~?t$*N0%sAsmm@)o>49Q=I!Qs(nQW^h}
zcGebPt{BAysw<GJ@#c{zL*f{P%F)-xLJ(QKwm|sX+N81XLqsT0?G=dhvZf#-X-&bQ
z`2R5clF1&{77S2-vech!^(ROD$yI-bs6S-6_~11DSyNDisbyJL_YzLDb5oL-hZnIk
zkme}$a3O1Nfo}M8-gEt#c`%ITj&b4y%*7g=e)G09qlTv^nU8T|wjy^C9`x0Q0)+1!
zkGz-YWbv|ZB|!3%@$jnLQjrEpJPU{I)aaj(50U-7h9BBL(^p4lB0U+usKgi1vy)tb
zRbQfKr<WbvM0-a^<AI!5vbH~QTyj!-Wi$s3Iu*|CI%u2l(7V7sOE_}nG@SPKTCTjC
zQ}W1_6=1>9<I(1SRIa=mp?v>0<jS<wSQ=Zd+_h?7<;q_@vG;Q2*H|>KTv>pejy=eg
zt$n%5iRH?I?^5<cuH3m2t6|HP|H4DB<jO_IU>r)W{3DAA<jTsulPgE}VRQQ`SLSe5
zB3FJ7B{##e<;oPPkyx($pR4~<a^)nXE!qdU@+J`<ZMjk%5BFNG>{x*{Q*z}$QQUXA
z@)0&Dn^23AYZJPcD<?ajT<QJ9kt@gJ{l3YSX=vd;Ay@K<_@9+4PhP%1<jN>aJZjtC
zLCLjkj$FBhHTH*G8F0Fq7T1+6S6&k9>OU@5E`=R(FXYMv@QT_ux$-)5f5?^d-|0cF
zyc0k6Qm(9juUB$q;4F_^Iq5$uS1vs}kzD!H-|iQ=auvdODJ5RKSjm<56~xJv6UHdH
zGJqdMuFNS^a%C>Qh<@=UMqx{jy_74@MVF8(*Z*vf<VxsBPousw13?k63}sthY|tX%
zX@K^uebvEkay}zo|1>A(^L}a*Hr`m9qF04|FdH}W+1l0XUj*93tUr5T#WhA_vDZMu
z5)vz}(uRh%XyKP|1c{Wj;jEFx6C2#ZarEeoTUoOBucb44B$PfgwjsUlbrcnNrlAhZ
z3a~jD=RZ0~9me3$!f%j``*7=*T-c4AU#N|3NnTq$S~3aELL0~i_**7wZKhd}$06m#
zpbU>$1hsQTfk+n~+W=UzS2MW>-d*M}oClRX<*w(x>ue9B{Pp1C79-G%tG&ON-+p(r
z<cpM~=;c4<I<of-xaNiWrC%YWBNj7CLmpL0%vx_B%LA~fOpOHEFbQN9XM%C~B@x=h
z9Rt(j1v#lOU-7~W9=*P!Kiz8m^=PCP7z;fk&QUnms&7##S2U$qGSpr3A*$r(L<>2b
z&HCr|<;~?ad(z`+@StnI3w@%c9Z=+Qf;G6M+I<ca`(r!K0^W1jebCff`h5dM9>56#
z1ci9h^ns(Wc)s<7!fya4fa)1Mhy5OHCO(HXQtNa8ss>l)i+;b+n2|%p;9sa>E^Q3n
zJcRoFC#c^SMZVJS4}|kC{GdFVeYu1;Qq~&nw?lop>MRE86*n3qha<jtt<SC8w~nGz
z<vYs#1)S9y-{Vv|w`<f3ch&807TrG6m?-_BN4I}7#;kPvC!s=R;BlzJ?&UmSV<><Y
zXg$9}E;wYqXwjPhf2lbfulWpC$3BW}#e>`HkGf1K`M-cJoCUc_2)<sT<S(<a5r37E
zA8ulq(&n4@%Xw^s==n>rTGaDzwYRQ2J-?(!=a9;=gfjl{m!gxWQ6Z_~EL+nLTLWGb
zMp2oN^z)r~M6!JBm{I6f^FM`@Vf3_p0QHrUzppe1C4XaHA#^=Epn*{<q5|ni1Jo2Y
z!r$5nVSEt}?q#tI2Pp<Z`2xVkt&vIFX6;gX_wQr6I6UFa^L&x_mKLtSF7VDtTj^h3
z1D*c@gi}!GzhQ^c`fJNmQ)EugDo+1eH2A<7*{3o=L>5n1V^i*xgW|@fg_tDC`Y4?>
zS97C8bFbWN5kf`Gu5bBPH1{*8)Gcl-&%5X_Ep$A-#o|=n{QpsRE$~qlS3fTy!on^P
zAYgc?Q3;@eP-O{dNLWNL7{DkZsI4`ht=b~lkbnk=Ng$W&YN}MLwbm+Dt5*H0B0h?N
zU=k4J6$KG73e{bgDvt;e(R}~^nS1Zv-E1J>qy7B-B)fO#&dfP;=Dg<&;#g%P@g>ha
zJ;_-<1fP^o_e?e@*vN!UoIFP`z_Zb|5^Jz>rk{n!sJJ2%QnAa*f64c-8!j2lZ*TD%
z=rSjj`Z>oz{dRmTKNlbAB*aFD4fGYio#8cS(kQ!|l7h_fT6ie&AMXtyLe6+W7E2){
z8DH#+g~+L=&h4pp-T_?_UDUaA>z!pQ>06pvj}wwk%Q62Hp5@Ue4F?xK8lBhu!$t|O
z;fuZVg5R>a^350E9p%^LoPKA2tt{d-)Q(jH_<xOGkP@bMu^m3?k9i`tg8Jtq-ejYt
z|LVAy;G>w7|NLXV^FP2nTfT^Q#OFF44-B7c6M}GDiOG->%$1$sEI&YZx42%dgYr*f
zal<oU>jQV8S)SqBXMtIL%n<SIg9JQJ+I{<%;77x^zeAtaSpI>t?5}v&=G#AyBNn_!
zGCB(%m2aPyLvXfs-~I>m?I)ng!r~`Dl3~96e`6T>_Mfo(_7z2R1CZFhiXz(Ki+$0Y
zWwY@n@w4Z7G=midF5N%R4WIc{0#+)0=EMi`#OO#iu6x)C;<V#LFgq6w3`%*Jy_u}^
zclZ)MXh&nv!qA{Ni-SS;V}<oGgF}NJ<^yBU<|u>8?ufy_B)-7?z)p?l32v{z<?zJ{
zrph;>kA=nC;DWD_Put;we;uD>(vP5-I%i|}(Mhp|J4|M%tqXibxFIMI;;VfQ1e3cS
zq%zN0ULSgX<yCPp7o(Ja;2$z5qRQnB>=(rk@bGCgq+}p5qj&P@FZRNitA_hk_Hlm{
z^$>@?3a|#Q#tUF4PX<oo5EL?S(05U{+jDx;Hj!uS5FfoC;}{Nni(QVu?-=mtZu*dn
zLA;tW$?(+Qj}D<PT#m{5FF*+&n|J=ks8&>7EnM?4_!rLk6LrnkW{kji@X$}eRO}x5
z0uOk73lIH)>y;(71|Ir}^w1;envsQN#3-Hdz!J;wO~fkud!Rs7>F8Mv<H4iL-@+(*
zR-!MbS(};&s=oU-vQD3pb8}(VB7-k59nb9DB$Hfg6#o5LaC)+3I{!i|-Lecu)x&;F
z6OyC@#tQTCzv%`B@xwk;jS^ez55w^QuRny>w3^^c#>@(`!)Em+0P%S~GiNo7v-;l%
z;0^&ek`?$_bE%)nvHosw6-xc^i09v24@LV4OLwNPUv$jHI6f7wV-ALNG<3{U@e%#B
zs$)J%(3Fn(4b{<v)Z3|J4nv<u(J^li(=lhIlJDJrR2}oqqv@EBGt30_^k_OJRmoQM
z%wy`9JOB|z$NW+hDdvx;Pt-9xh{AJJ9kU!6&K6@V!WTPZG;~Zi&>=eJA4NrLO~<tK
z>;hC)fS+FJn0wl)V_MuI?h8}LyjgVQ7CPpoRN6v1=I2O37afzbLg|=e#F)zdROy&q
z&|c}7&k+DvquFcRlc8fig0BWotb)2p-EZkJb-&v%oRz&{3FWUahFt&|a_7va1iebw
z^}-iBdXZBP31YN7@;9`s27O1-2cKN0^g-r1W9~{HY>#(AX-XeF4PTT#n2b+KAMDHq
zGdEJi|Ffk&_#&`u>VrI)DU6>wU-_kcj~bw;eJA5p{+5|anagn`Z@^j3+!0DFk$9Ba
zma_KDQS`y?1k;rMiTGkiNJt<2lx#7(&YcZ?uq*q{t}kC}(+7Fh-_Qrib_^V@cv3pY
zVF&P@r}4$!xwG7_lo&%Nlqv-h>!t`Rw!b<n^3}3?)FA#V@XOJ4!W+?2rExrN2K4i(
zuvNvO_$Lxfad<VTi=^jK0@!+^QvET~Yna}LTR0;1zB@pob`oobD5vgb>V01lPqz*!
zKZu-;7J6Scezf#HmD2%tcyr(tE2m=uzUnhyB)MFKk4o?BZY;9W`|gyS4$=Ek&_wBd
zQ}K{F9TV|4a1tKd^}gwNXe`bthy+?I-x*)R7N=|pCP-W~0;Dj#Po-tp^u9RsX{um<
ziol5=_FvFa*wx?A)zKI03!+SElfNSPhGO@J2n}0$tx*#svE*=$rZ$;{FX5oPZ4gUZ
z2o$AFzDU}zYm?Oa%t1eiGN|mW9smb3h>;3XrZ)L&s01ph;wJoT7|OZ*St?dkLr(K=
zkK4AxL-=B!rj-^K#ZdlII6#=8{45^X4P~Xt_Q3p=ChL$-)MVrENf0&?Q)G^wXsUfM
zyrrp5ZAsjpV{h7tTeR0{)P<zRzfBju3Cg5m+S)3)at%B)p+EQqK&B#dI(SE526YoU
zmGO|JVM~c<ny8}M?&Gg=@k(Gfh7i^EX?zH&ww5wlTtjB4RNGt8#87Q5SvM2EV**E4
zZ7tEJ!{=&KZCPW&RBdOR8K&A6{q(Bs&a7yvZ8A&=CZABXtv5?b6RS{Xz1)d5^)^=F
zP*mSez%kiy#efJ6Gz%pY?Jqg7@swY6?h()!G}tZ=sz5?EUJY(Q9!g`H(ovfp_%>|3
zYp|-^hjecF)A4q2g@4(H@YTL>mZf4BObt_HM_?EGJeGR>Yv|vBR6H})-jQLgDO+r6
z?<lt3g=Zu=(6FiI4n~Gs@GlV$d-CC{c1W*^KvxoaGIF>7KgA^q`a72wGcX}4d;K%m
z*jHHhQC>{hpCHFl<W%xe^!5Fyyr@-EtLTZB3^%UU1jkBwHMetdgSgF&&;)LIIqG?E
zb>e+o02CoLBY8j<r<^>hY$UvXIgR?PMjWZg!8$?b2dUxIh!Kz&l#N*<R1v3-KT^K7
zs1xbQIm~>9GYK7`Z#sO#&!elJDQ;ji&65WstGD!X+zCp@f5~C`6bmj_o_KXC$pk@e
zv^e&qwhDyL5CRB{0CD->-wsmtr-n$mFEk3@_-1VaEX4))nS_bCK2`_XFE<I$Cz;f&
zad__)<hu32jmp2D47Vj&<n#B1{QEN)5tEVyJiJ|yYP!=Ax^R{)HrOgcM1Wl4LlTo=
zVFMf<u^rdKPCtjS3uH*(Hb?wR+@pYo$A#L&;45&%N}&>m3U(NA3`r9E4(H}oZ^}8V
z+_eQ6+D2_%>6#hF`7UzzHccbzGvLq5&8ckcf`Q!9vzoPhV(lptYdo91M$4}9|4%K}
z8F{$5Yl1!#gUWn08cfP164#(jaHV2Y8xJW)b>r^^kB9-L0*g4}nS$8j%>I}s?~Ii)
z5Wo}yi%IwjbhWrX)+qgL##%<%d%;@h#RH@-o)*15RpLf0EphZd5lS4Tjw@RB^(dY-
zl=Z@Gwt4{$GN)8{K3iCv6jQ)kdy{Y^^)visFp4EC%maA-KS1c4y{UG4qcwX4hPm0y
z8uR8Qo}>y-^^)9_id=*kl8r1!Bdc@X{5Trua&Y7xYQNZH6B5!haf<pth=WjJ$C6kU
zf8?o==P4H?w7Cr}OZVj9n#^-?O{V{{c|vj@+|vI8gf!8GiyNL@6(R2me-ktC9pEBg
z9|!1D{XI6|h1$}li=20}N`N8~Ibn)#64dlb{J}rhPiny-ZP=O&X~GLu&kk}|l3RfI
z*Z4-I8?j6tjisA7mJs1U!x~b7={$m<YtBhoSX>=bFvEuqK`+olcpM5*3l>?4I1s6;
zswPN@Ls*0=mF8K23Y7k_U-5w)Ug@;}8_BZ*iP=_R1KvqjkIq7U<4SEFw#4>Cd3A^}
zd;@LB4LbY47K4w%x8Tc&MNv23#r;Yf_WBRJDAgzguZN0=*KMufRYxH>pjM%E8?o{R
z?vK!F1AnK8hhQK45Zpog@rC~GuhZVwi`Qs7ah=9NJn{#T?T%DCb);kx=!2Z9-92z-
z{i`1Zg@NeH8!^fEL+5C3)(dd>IT@s8(o-hY{*XlaE1e)pBK;8`k48_|L2b}H8!3_s
z*wi?Mw2ykUr(Pd-GgjC)O3Gct7diBPw3U>PB1IpuBx}To_Rg~Bp~mY|Q7C!6J~2hh
zUZH38*O1_RaicGxJvwpMI&o5!w6am3fSiN&2NO^_pzL|7*G(CWg)Dv*pVOK+AdOyU
z*;0Hr0?K&eOE{U!#zRa%@cE3SXF(9vr>#bq9p?L8AkY{<P*F=?$5hFgAB8!Yn*am*
z61t)b(7<jzqme6y-(W|Pj&{?l{I56IDO|;C^r?xcY`SD(*NW_ySu|Oq_??ZhfAJc@
z*bQ5gpn=9f+DNSsDmO?06#X)1OL=<bDl93w#BmacVu-M{*gU8_fS;1tlX{-LCT*48
z)xF8Ncw)QIVx_GknPQKaaPL%bBgS!ob7fW+j$zDd$A|2TYgkc03}g)^gz?22F}nm~
zycn|lNsP7<2f20eIgJbdh2tN4xKXo`V~I*b4k}zFP?E!<tbL!I*Prn`nF3(B0_dqP
zZE`uw&IST&Jg+nAww|Hj#i{5E{-goS^ITYrAIb+{9r1IuAOxMAhncbld0p%rl$Wd<
z&v|0|W|+TE7t@2eo(zjEs-}Hdyrw_uKH!tl5qL#?8pC`RuQJz?(@h~$@-%R#gB)k_
zbYMkx9nQ_B=%@)zo|7npL7AB{gtS-w3BXw5sjKj;XR(u9l(5{P&2&_t19bO3f&>PM
zyn~Om<G?RC09lDy@S)PV+;uQvaw6h|(5eH&@elnIgrDUx!r(_xgZANi=gK#MvcfZf
zu2Ddj*`A&(d;2)m-m`vHL*lBYWWI7HUdh2L;3sMf9)-5Q^A6|)W8fWm!MWH6R)d#*
zDdV8PgA3m)^{K;Uzv7r3_A3JN+^?lgv85k12Ru;HRVqrNP>|Xp6Y5|I+y>w(^_g{K
z15?qDp1s1kGS*zasTexY7mxEQ502yEqONR`Mb?gkm`P?c?;12i!5{KOfuZbkd@*1E
zJ=70UVO%c2GEhX|E!CFf&YgwFr@o2D;L@;P>&Uxs>o2B^xk%KSEo!%;1-Yy_7oO*7
zITwF5nr*;O)?ARE(aKzsIhV&&TLqs44qL#tlzsNJ_t~M<KGzTsUaN@lRbexMZwyg{
zkT_foprbOLU5bvMGQR(T@qP$Dv3!3G9>b$ZhROp#;rMw1`#L}$CTJzMj)8Azb`fn#
z*=D}9QSge-vjx1%R-@UKXci6w<a|uPi^pIXftx^6Zd4<<$MbsNEf|G1Xk;@B)Gu?^
z7ow%|q2TJ}bKvQzgisobUFRQ+$~?AE*pGft#W(I|p|=#|J*7a;FxUrFD9A;MqA$ne
zX}`c;*!^J1ZXt8e#zWiqmccc40|}sL{$%6EvsVGoTL7Ei4|TzRs3!nJf0rdkI1V~c
z4WP`!4-&fikfpsapO3Mi)DJ`=4&MXTjEC#xA&LJqJPCdbysch@aL{#I7<aFW4Ri<M
zts2&)ds^xdhyQe<dPFj38m33csgu8<!~aq};)~5#nIBq@_|wbm^q6`??-$Ul?Rtds
zl~(nLjsGBhiGI;WJ>tGC0(TTWVkx80*&D$xTGu01P`;js9<e|I=EtK)Yy<7KqDOp=
zgqx%35nT-};KcQa`j?2;A54$<9aL0<BP_zl@2f|Ajx~(bBlZAYt?3c3s`in3M9k6j
zh(*>r;d(^U_tYces=)h{9--t;OFg0^hHir%G5B>fYoi`90~8TOk9eP5h#sNjWJ^6_
z0oX(v^oU2G&$m^N*of2EZP6nxWuI--BW`D(E%k`6*+pCQh*5mMr5^DL-xobXtyN1s
z;#%x$Q;$%(SW7)3oo$Y-N6dH?&06XaKjR#ZOON<1SG9FLVmIpC*z|}W{a}Jkk2vF$
zXnMpG8OPKk9s&|t>JbB90idEsJn|;=i04qdiRwaoSA-t1nwk@S_yP??kN7=`bWvq^
zpv0y}?AfLCh%$LdJz_hag!G7HBuYl;5vCvT<sZZkX!i00`T+-vua|yX`T^<gg#!vs
zz_Xx@B{^R{*uuF7EG>f-W|rSMO0$<xa@%ZX`2c5#50Ld+aG4)0f6EEzY2X4B{92rV
z5=QVX4RZp%N=sZhZJxtNyVE8zwfyPsSUssm^=GuSIRPi+QBl|t#aVTys+%6^1nlw}
zUZ@c#;HOZrBb|T<7Z^^!vP*>iRImW<5b*$h)LT953H27Cf?+_WxWYg>%~J+1EUt|y
zxYl&Wz3f?oR`8*>?u;7@VAL&1^^(Fo7SRP~`6`*0U~dqTM;MW{`}(Ay8dlQi-tZ$v
z^Yxw73B>$o+9>q(Rr$t=udn@ILcYF^HxPZ%e0@Y8GnJ{viwjkJeOsuP)dXr_-TC{i
z#%E~cGSNG*%-mih!SwvS9HDT=8DX)uGhnsaB6H(U#cu9`XLM-bj~Q#L8jY|Tf`Z0U
zOuiCu+-K?WC3_wMhTsxZb@iTw)-U9B&OKqeeD{tPd3C_YqmkF8sN)D%5AEuHY-*fb
z`0#hs<*UReSQY6L9D(#RWW(qq^sG^ND7{)%NKX`<3|0EX{#y2vdKTQbufxdzcbVSB
zmvAv@2D?i<arCN4j&V|2(<b-<SK$44jO=O10S)*PV$c{CmAHJr7>SOvhQOMo|8EWb
ze@H+R|KAhn$MFC4$MAqroZyILSpL6;7XCl!G_4Oih2H+6`2U{QCnn{wnlF6xrUOtG
z_TN3x4iB@@<7JqXasZ;dH=T>w&(pmGQe4LA(#v-boSf`a#o`PHpdyjS*pqsm{bJfG
ztq!U8UELd<i~pC2eCQ4^#Q;J&0SUZ%>)mwD6N%2wyGrqUo}Pu<aXinfj<npRJk5~3
z40oQrn2z$li_TBrAe<fcu@o+P-mQjZyQT26@g6)}e3!i}PfHqKQoK~{xk+5jY#vCd
zXiuDG4M7(?(cnwCQaV#hadj$w8z<HdROO7uc+cyHJZoa;#46i>&8$yNiA6T{3LH<d
zuVe8J%9b-Zlk7DmAB$%(`$c_RB8aZ^YnQX^g?98TK2Nt+m3S7vLuYiAVHaZm>N8)b
z|EUBBz|r?S9j?S3bg&Yp6@a}8u%ki|(LMhZwQI$_@FEgi?M>ml%F|NDmmDV0-tM)T
zBt!IGrS;CM9XlN>KpW%r*g3u7+ckWZPco~Cs|yHboG$%|w{neh5s!x;X{bM{F5?r(
z;8`?;w{lJE-pYRn14Y$lcq^++Z{_RoR`#Q}l5XWNZ{-?i`Bb|0Jv)}<zFvU~XlBA;
zUZrJkqr)=WWn-E@lV+06Lg3uny#uZMTPAbb*w6wL7qyZD-b_JGV3>7MvWDzMqHCxq
zdp1}de2cFm*YOs?J!@k>s*uXd$Aqk~1j~f{uEsiowCKbpzJ^~QbH`FyO|^A-diJAv
znj@#AxJ;Izhwdpe3Vi6f%QP2OA_pr0I1Qg^F&&^F1lT`qokx85Jf1oKd(6XA74pT-
zr(4ya$?Vs072z#<F6a?kGFNayY?R3+TbhZDmOdF<@>=pm0LGXjaMItHi>;})DNoM@
zPPiXUoMe~Pj#1PJ<`N5>j3G`i7sEEog_{kNDN=ZuIzrg)0Aag>7272@FM-FYv^Fll
zQv%#ahz66rFiM~{^aO0^z(e#B=~EKHS?_)Wp93G@pM}NPj%DA`kEsY7e%dvI5RWtV
zLe*(_^CSE$KEMWZ$<LrjtHWdEKYW&+<t$dTg+G{XVZlLCe>A!mKjB@DQ*fiTOMO?x
zYBQ_Srvq{CKp@yQ^Jl}&MFi31=`)`VZDnWKICN%iXGrZhAS@FI3!EdqMFk5h$wY^x
zk&}*B^C90grg;^oxd*sVu*?TkEnyjty8Z#AdRwquM_6pDYY{?c!V@Bdo(4R&ra}mS
z%OV74*~#cRz!W|OgZPD`uE!9<VA*pP48P~}XwNAa{t6&l!cf*1jdTUStcSp0+qK-_
zEH7XB3$S|I2A?|2T$At(4j8Nr?kpRMo&ze4jx^Q!I^0Zzo9h4qHQ2}|PA{|$zm5t+
z6$E;Kb$1M!a+Z$;)QYaG$ytnwcg@=1(9dfN9Q(L8-oro8LIQ4VDL3?%dpyqvJje;N
zQC7&m{YPToftK{$tUy3LFbO9o=-<8^Jl20HPS@D%(x2q0hs`$ib)#)sB|<0U<L-E#
z*rxrF2j_e_>q6POo;8M#TPY=Lupm&!B6!J#5G8?~ginWHQ0(Ln+%vgL12}U;986Dy
z9KZW4(!)ruBADf5VLQ9!+tR=h{6#zK{YtJO-e*C6^_)W9c{dNt@cDE2OWd0M+zVXm
z*-Pd4kG=huM*H^o-G9S!nzgUT%Fz`|N+KX^my*uA{|+yID3iwj$L;{{0X*}&V{l<W
zLh5@JaJ7F$d&;x|o}8%c>EQ^QU=|h!f6?OLf%}10D0_BofAdge4BUW@X)lgO-~NR5
z(8uv*2)^KC%a>;Ls^GtnDEL+^eoRUAZ$Q$pN_iTJVFPnpnh|r^@p*Wza&KC*8xEGA
zsNImnd4|~yavJ4vbogIjH!MGg3;F}w4f|kVw8d_C33k+R*bUR+f@sBVxQRU-x83lk
za|QSlw;PJiR>M*}eQ&$r^kj5)qISa<gYok5*$sQJHL35MpxtmgN3@w3-`8$P71NK$
z<=nX^W;e`(>j^XZ@39+v*attF-Ed@}iGNFSpP=0k^S$f_@AsKUq}`D8{p<#Rn!-t>
zx_DxC!+`H;H+02@J~6wYq6gk=X*c{k36GCuH|*$!M#pP6JU753rXSpHc%3SNsjosc
zGVF#^2}?*{jczx%2+N7s4IiBqoe)mYZfN3UTiOjXIlW`q4VQLBqZ6?kPBCDxnHaLc
zPta}{P8iH}2-yt}aC)J2h;BDjbU~vNwHv0MY0_3WqY8)P`0a-4iT&2?h9uPLvDpnj
z$vGOE-SB`bn%%JFjAPmjcVa<W+70a>O8#Hi4QD@fB6h>|aIGr4A+}LsL1H)j^EsQ{
zFzX^^HypX)c<hD;&#>7IC!ufu`oriHc0&{BqlMjYFKUp{Znz(VD7)e73o)}OcEcEU
zY}gH@d*EzkV!eB#cdVX~uq1Ke*8{z$=~EIGjvVM6$S<dgYYW4^-9?IK@+J=CB^1RD
zEZD{yD)K5bf;%cR(X`;*VB_<+K?L>)e_#wP@^5Io)yEuf=5dS%AO?9H#vK|sCV)~@
zydgu~PZ9AQF;3olp~si{9izoZISdCF%Qw$I!*tW*uQ=yu$-!(CybhvooUg!{37e}~
z-GX7o2?w)Bls^BUpvy}7#<jg>C^4_H<QtgB{hW*MLRY@Ar*!s>ca?k{gKbebS=)&P
z#pPxG{$FDGYPDGjhOg8&%TfAGEOLsxxd>2M_xm6N{T$!7%_Yq;?+0sneFWy$FRwP?
z8bpz_%94+poiQ;h*?ZbMo4$zMSwbIQzryyuvFCRV-cz}f--7#b)pm{}xB_Nw@|`eq
zr#us<?(&ejZG-g!-0S3UA1LVZhQQJkf+g+1rf*Dm?l<Ad!O<asCtLf71UmH#0JB;v
zvVbWfFy5(z1TjTA32}3Zf2ofBkh|OP*FRu5_~@)pxE8=vfW`-xd_s8M5O}t3`ZD&T
zl4gOYr*G^<geOmLm#1Yqg0I3J7}^{xc|+j)!~|^a(*Vpon_|MX6J@wDb(Tp$ygkMa
z(zZyD=A6UO1XoVYWQELR<0ii^DZb<|2b*)!tNh~|+qH8rzEaz6Ea+wb=7It|EyqGb
zj-X+Lg@z<qdLPaW6AiMa1>?1iCbnM{<Xc}AtQR|i?-JI{!TW$82LQd4D_HhKT+Gl9
zR=|$HPk|zO3v9G89q4?*#K{fdbN?Bfr0;1fPUa#p<$L2~)?eF<lgWQmI9b7cMaBV|
z!QC}DvBE<~9#`7NO-;zA_PTHyj2F>lC$0^=TY=hnd3s!)rg+}5+CP4r?F){xy{AR{
zWRroBA7WpY!il=Jnx9?*b*>Fu3#Mbmoq6{Wc$mk<&~tHeo>u&+-c4IIXhI|In_?1m
zKlgiuKgafEeG0VWAF1!s1zyndg9V+mZ6@K;HqUh+MjIbr`dzHIAM*&DFXw)0N|Ku}
z(@<;hq7k8Qpwb!=^cx^(+uTw(w_=B0z%z(k5l(`U4$8c{;jqLEI<l7(b#QFcXYuLQ
z*y`>`6`xtGhE~n!Lrjt-Y;Suv#4o-dPro$KR-Qf`v-+WV`g~Bo(6PFoOIW(z4#B$g
zX^r`psM9MW4Bk5gv98voAB4`?jHmNuFlkCZU&6Ffb;}plYYx}zEg6pc#+0w!aDj?G
zo`+;EP-6DzqhK9t;bPYLnjvF#qzYszL96!T+Q14_j0}xY@(uTEK|9sPJT2MV9u3`%
zyT0V-KrvqBhLHJZ$%Z%|H6Vi9rSAdQBQni`lS-?gNtm6T)SQtR{5Ri2Od-aH3;n>g
zJ&pcdI18bB8iSjaj^Rm^w+O$ThoDmf7DG3Y@92n325s>>c8VG|ZY?ftQ1aZ2l8P=R
zGFj+93&%f;dMTit<?A`0d<QiRMa}v!eQJV|_s+#t_|^U1oRhH&-8K1fIAab4Af$O*
zKrZm~r{M&u$Cp<XjPVsZ3|d@f%8>RD$>ShH?yYq1&wo?t7)lb>K@tuhVkjABijwiT
zZ>j@*kX`nXUCPiXXz1}$@bviLV}=g01-vuMk*8hkkm8j=-NbnJ3@s}$a2iFJp`N_(
zm|8hm0kv|!gmM_5Y7@pIilMi-;``}WCYU<P>qNsAg@$UNp*mav8$vWJ`xnqqqfImA
zwB8<Q80ovlQSzOT*RO57!M#0yeI)!T$!fGhz<)~T;4{7}9eA1WpK8Gm>VEtVz~4Uj
zROM?*UqI6m;NW85V4Q)2yNpo1)(!~I0>aBp6g>Z^o$f(1#*n{g9k@BC<F|gTPPPvx
z%Q~I@WxD~t1-;r!p*enNPT_1!fi!F0BgsSK-Fy=o^;;9m4;Ecm^0nxs=i_|(AZ!<e
zXC?0?QjzA~`H22vdDYX1C<-^E<|>sdVpk^^V^H)W>#K`zdZUhG&j*XT>&d?S#?twT
zF-0j_FHNo(%&V-;k^!vW=I%C8Xf#puVe+JS=9Ng^PTN=?mhC)FmhTy?&&H2vJDH&3
z*z}Y}hRnz+2s<%*5T0S#!!{l~sPCq4%$M+&S9{AbUT%>ZdXn22W#d9TR>5H2vq-e$
zy3$r}I_w>&)eIW8={vJKiP%xU#<Xu^SMgR?vkZ2P^)qpSZjeRU4bygSEVPy^ZMAz{
zVK3>)kncm$6L$b_{j1d01$TiUn#l6EJz}Ft2L~M(kI)bWGvkd)=Rk4_vMS|WjBVH#
zl;tj5TNR-*#H(AnwD%6}EMXE}KldT$;>XZ|Z+Or2TN4V~mCj9!nSZL=<CvZ3OUiNQ
zI_6v}_5_B00!|_<le*L_A*ZxC)_Vcd(XdrawIg)_HekonfWsiwJB$dPHWc{;w}M~;
zw}29%6X0Sty=R{03cd&Zz(GtKqtH^jPzHi>iWxu^R3irO1X30gDeeCprnig|oyq~~
zn9a%!*Q+TOHEPB6v4^zc-RknSxryb?^ZVi42aqSL_dYyCRCjvX+UvzQIa@@fW*`+R
z6RJtbNwh&#(4A|gj?Y66lk622*33*d*=+?Y0iDP$Srau+ocG6;!&Kb`F6ZLE0P}+i
zT<)5}xtRK|Y*RVf)cbPk(v7T!fQr@jCCv)~aJC%)UvW49$sqtxTdF2lYQWGC4Tdcy
z-X}h6;vIVU+5jWVCcRzCH7H;)T_}ki*t@E20f6YCtd}gOHHY3W!HprHxp$n47jsW;
zLOxCGek?iie2{*|NcQ|bwl(@0-Cbc_NJ3o>S7<B&biUjy8Y&pUT*BB5l{PS3NpU?n
zCF+EN+HeRh3Rr<F@e}pp;ARuP=N>ZQyJD)+8uUcpRTgjT9pa72T8FD~*LH|En!km3
zqtV398)g6gx*6K>G54?NBB&EC%yfLCsd4NA(y%r22LpBovkojyi0!!t$b!LLUP;Vi
z1x)?hH)_1Q*ipD%pNB25;7t%t+Nw=oyWg497sb*>8tUmgrfc9lY}DD<sKM8X<a8q0
zw!g>X6pA1@SX;^8Pl@>b@`dK_PpCca%+nHsf2@RC2d#Ta>tg1xO5w+Y^S*5kOy)XZ
zQh9n8@Pj}mzG6ZCmm9tBAGshVjmiFr$7J;L+<UzPee)ajD?u<tgOn<T8xz6jeU~|W
zvw$yI{_+N*LTnbbTPyWRjrzq2I9^xsH3`wV_$<7Wo?Sl&{2p7st9um`m{q>9CwKPc
zzzT)qM4T=oAZfJh2LFdUAjVN{wm}<jX)@z*+fczpz6lP6NoV<k7*vm!JK!r(nl8UO
z(yif0RHGM;=0L&6z(X)?EqgaQp-MBG^kMD-lyJc5YK*;hE>JrTxxfv2?vCI+d6lma
z0xXkJz~p9RgR(&A70_Uvceeu?A@2C1{{uRk8?=rAmI*f383|qqV`QSZ2eVn}NSR7U
z63?aC?T}3E%EZ9qeA7@BD;@|b`9=v8j4}ylq%lhH4w5908dLg(sHA<{<9U1lB|Z&3
z(vs6KgJ+@)zC-VzPo{i49ddCy<YKPNmoNsEVYC8R71TijpGr=Pwq4|+P(~Hz0J;!9
zREJ+p8WH<i_>dUa@yM_>6z6MX%K)+VE%OQ-UoGuwq197Kt9FaJ7x2$*HCU`)^8IKw
z^-ZXTqV_y}6}eQf2E{Qy+p#vld$n!yKzwCV?L{v}>NI=-Jy3+Sx!<77Mt61Lb!nS6
zeGMUR9od&$F14a@oc0I6c7gq_<V_#Pccu^U6m2Fh^F@LxP?!xA%7g>ci@t^2&C}c_
z1Xxb-0=#lRW^Cdwg?>p?L~mD8)X2GbM?wWnt5)h1R~6V(_7l_(s#ApwtM~9FOb0e<
zSreOXTg7?I0j6O9^sjUx7j>9CB;kR^9rV%}UJgT*Vc&)-W6eqV6qED|eV1YLHiG{-
z7vGDyXsZuxH@qfWaAY4(+{Lc^v+XzoTQSh)e+Ney;Abq~j1fYfV<gqPJ+8vH^fA~q
z3)Y0aYiKn9@*cdacczc3skGrcUjm%Q4&SKBKF2A(q(t{tXX)eU)ZLVSm3Ek#OzB}1
zxLe6_E{6_5bpy^=wTTnvU=zy@PTS&hIFTEU6;pZHM21Wjvh2eGAP7dMMQdEw+oXk&
z1p8W83*_}Wd`U6!J=pGAwo~pK$*8YHQ@K+WG|S&FlYZ2+{Q3NG50)CVAq+S)Y@QAh
zZy#V8KIMaJAE@RohDw{K$L48q0Tic~_oN+aHIhZ_BI7>wK8e%F=c{l>1=mvI5-uHu
z;;F;iJzU1xv&5U>7c}f~(jpvDylDmMxXCBZ5<byK%S{qK;nE;b$SQ>D0xZA?oo0LR
zBXcrKF#(glg+I{8<)T+g%l%X*i*VN#{`SzelQ4ciXkxR-DJ(iy{x2=J!G9;xh{_Kl
zB`HFu4)cS_#xrpH8BXAZI0p7!&(Jq>a)(g2#oQ?8;<MrpcKffRZ*rqPTiJgq?Y>R+
zUk8w^ybAkIIh6FSzNE=EBhXkA;ZeZtC5<>UgD}P@cU@us+4Pi{Cn{EfEEOFm;oenr
zEWZgGNUIb2#`FDOarFSoLnMG--W%HUYJizsKXZ(+7-PU}!>1H|oW2-GaRTSdAAqA_
zB=ECb!_icR(af=$?lENn`7Ic#$7T7EvHx?Ss``*l2pT5Q8uz_J-Y4>lT|ZOtDhX7D
z{Arty;<W=SE99|{s4**p|3{tA*@fZrfxZb_9LBzK4d*7O?T0~xKieoeT-vrlu_8k#
z3~}Hp#IG%Rm&DBY&R+>%bwR&kS803k68JUkSJ1RrJ!j!<ldqVx*7mUjlwgXNCs@c%
z!#NyIvd$26S6{t0P=$tQr|8&R6^i>)^!!H5MT&^Yi<qDBCU*@8sT{8=M}>+J91m`&
z0djuF^G<g=Ox7yoCU5#A>Jm%?bf18?hxAfe1G`UukjH_ONy@Qr8a#zKwBbnGq^%P}
zSGb>8mn<;X;2#PTUa=OjofO;O^hta-YR!gk-#Bps4Bb5|g0GAW<0~T7cinCB63E?D
zV4iaKi~R<DK&?;$B0~Ivn1TCL>)tBi!<QOy0eCW$DYlVmcw3!|kwzP%y_fc#`<=pz
zwS8%u3|O<1or_VE5Qa)p{xDUEPU`uI){j|?m7^ueNJ1`O1>AG)mzp}2_D=96aXTax
zzRBWO%z<9;8ae^H_Bke?7LzaOBGg^-CAr+23Ul@BB-%18(Ige`!p7ObV<Yjf{(MQ}
z<2@Toi<2Q~p96%dt!3TM`i(-Tngs4eO1e-@VRm<nit}U$OyLY>+J07ist^7iXNm!u
zw+KJ72FzN(AO(1mxDD!ri8>eW!&BeoF`a!Aj6k$=Q4AjONQsv~uTw_BD-!G6v?<^-
zje<ERiC*u!{N&DojhHOuGET>U2bgH8^{i*qQtB@4jso{?_{Q)U#@%Qb5g}`+45u5-
za)-Fbn$xyh3|{<7jqa5VaWR4a!57rWLU2j2_9n3=$56pw*PB|(1-E?L9DJx!<exNq
zHiTSTJjjJ+fgb1(`iHiPzWwYq{(CWs6mSk%QoixfSJ$)Bm3KU96p?dbeL0wpLQ{<4
zuko+B8TwQ18pG5oYeKJvL4&G2S_d?QSu>v5Flsz>AZ#Du>$irk4c>v-8+PW$Xkd#?
z1)vA<yQd!Kw5*Wt?=(nfPaVLDc~#=RYXhU84ngube2{YU?-b!JpU?5hXNmRa;W<;<
zrPR#3h`4a`{XFa2$h`I5@Z|*-Vj@aE8bDRY(2p2=i@ry1fRb&>t&p!zY#tnE#VKl-
ztsqTPTN;?QIz4xHVP8lSQJ0dmVwYCnkdTe=nE(sS!q*n07g|8M9@7uAQ|L<+Po{Zd
zmTHsY0cAjqwlS><0)3daiVV&QWL`%-imPaD{E1)+u(q5bZdIw(1=qH!KRt0%IG@u!
zpF$xGy^Z+_uRF9Pv<y$^VRIj4$Tqj{%0@ji!Cj4-O(fF7M)v{d9S`ASD0d_sJHov!
zzoTz>41d({qtAOvXRV;Vv<4{KUGg0_>zoAlw%J9v^NrTEQtE5hW4Z0Yjf>$DfRRoE
zZJrh5aF&0{kz+#}vYg{<y-Zi4D0%buskxQrfzGr8fot)H`{qDk7Cu#$e9Bx66&Koz
zxR4nanRAjAO@MPFFq3V4)3M6CjWEe+vYjmNC;b9NzrtSP;o^qCbhgjK-CI_iBycev
znLdEAVT@t|elc7NzPH4+5V!!3uo^=Azv7-zMc>RAOMu=8sCl+C8=Sx?G0J7|l*m%Z
zDO4q=K!UDM1+FKQ3g^q)aZnRxEXD5qn6TL0U8Yk)LCzcWkC;?XMnVzCC`f`kHFoEq
znT|owIL9Zz)wt+spxN}GJ-|hV`|%s1em^rxkS0@Fg`|Uq(XzaQ+?(>x(pE*rbdr#N
zgN+K0Q8s$;U5fXzchg5hzO=)?W*ra#YOoSfAnhsO8ZZo^mgrsYN$c|u_>P%k%-86l
za&N;SD>7o7H13J46u%=lrLwdrF~)iKM4$}WCl`W)xwBo~^I>(xXFEg&g6SvmbJ7Gc
z9-kyAV)7~9HZ+8{$tK&QJ2gtRvwSTl60#>*A9BCD##u_BwAJDnf<_PzGcq9)vjZo>
zXOISX25rU#GJsqIDW1Dg|APT~%B6^vz&$y4Lus)i);mGj^CDac6(-|SZNDX-(`W9^
z(>vyA9b{sGUjWET$?XZ?k_U@~&RiTPa<4<4Hr^3fgJ1M)yw@vFOAau*%8cO-fv<8F
zg9?mfn#6h*co{1o=kO&BE@gPbP*D`(OxW@EI*7MB*@;PypNrag*S8R6TTGe~|0{T&
z;eYkr8k;^lVNRN<MgIv$*v#MZv{A-+=z=b$>!Y%CUSiCGP4HK#1Jau1RsB$CokULW
zkk+9#hO#`8pCif5S+;`f3c)cV0J0yR<wj1`Kk$e@y^X(VJ2!o2QuQ8um*BIRCWf3U
zq+UIW$C1v*q;^qrs`d*Z@AiLF3trYTrwVH5r2t-)s(=JXkjBkaODm^}1)^zND%Dlu
z&&`-|`6R52Bw2<3o~Oq%EFD~h{fs=TI}rS^gl@_m$SFE#=2`s`9hfol3n1KQGe&Om
zns3X%?aeiV9!`l#R2{&5Wd^ENN1*EC7N|OxsJg$6s7iou!Nk>un$~cY5rL~tzqI2j
zCma_o(L<e2;pc6IpS$e%IkM1>ABu%Y{QTL(&xfT7KNv7XXd!%o3WxZvX+$muk{(jb
zq=yfPq1%AUL~Vq*pgNrGNPLjQK<DDO(89e{Mf_{wFt25%U?}lnBxuS1k2irFTY@57
z*YJ~P`Q{mZa_^tby+Kd(#aPw50IU0O{_059J8FcHka&(HBtGh!=s+)&5NC*Xq0YFH
zB>(ygpcyW5C^HY{RjNG2w}4CLKp4L5V2Q~mR1QQpqR)_A&w=pB6~K^9@AY+ip}T$w
zZV{#rS)S{z`h-SzopUi?@eR*RTjhSg@H+SheJPpl1KwYdu--vu_VmYp5xdM#wYKVI
z+|dldw%Dps(jQYnfA5<k6g(V_cC7r!bJs+rPq6dB;sT^gK<(vQer~7F$>H=V`JdRU
zA1hjX)SeSL3l*5HoXFr}U~-7~|A<Kgt5=oab3~%#!!{Z;qX7TixZJh6t++h(x)a1@
zYH?ItzKiW{;<6Jzw~ou7n*Xs@b5vQ;g8yA>$I18Qf48-r|A9Qi<wLFu`QzOsf1Ff4
z#AI-wZ8M+gE^~)Q$sylSMUdN)L;m?SR=(kV_9bHudHD(Ekas3Hgr^mL4kK`;3pwT8
zC8s=$fdf7}7oxZe<3fc-Uimj~06-ht_C?PtA2m}gsB%dE-el!wUU}IMkXL>xwu5c$
z6l~Ce7;7P8U4_4PkQyREQhDX~;c;6St1Ykm(8{QE4ZfKX!8d<4<GAS>x%A+rmRz^x
zm#5CP?SC=%>~zEYa!anCgv&DiGr0NSpKZlWud9DR+$7>k0ZYyt9XA2o>Y(<>ap>6f
zAO3_o_WiF%#bFd3`(0dT`=jXCE9TgF=uvg-2SAoKTKkD*%uTEg(Iy%5w`q1<eNP$l
zhXOl(j;dqN1!*dJ`^k0eNw@^U&a8h59Xk`%M!$!SJ+TlPOt_AHWcUAL9s8{nQRy>^
zj(zeKcKSRH9ovy_<9#6=`=8jtre63J$Td<}{QuLj7rfk7T>kU&6U1fJtx<7#EAeO8
zD}VDI6_-CX|3jsnHuArzcAR`){x_@b{14<AE+4+9j$QN;L2iqVy$B#1=O}(K9s8--
z0Ou(D{0Gpn?|%^h9$UxWHd!s`kEmn+6WhVIc0ZwxeeVlV={kyzy(#Co>AH0tyXqF(
z{y(}N`4?<~{|s&l|It?5ymZ+Qh?`|Mw;4C(zg4)AoIaedim~cww(+3Y<^KyNYdYZ7
zE%2Q_g#&)OEg$DZ`aOc`u@U{g^si9AKVn|@J)0!A!hSB}+|5je3_F+cUy#Gx3n=<e
z<uIRw3#O?&9(N9N>T^GA4)Yq&dN`dhAh~20rWYlLdHQxdx92dcTvo&?<&3Nfc}aTJ
zsEr7xAyb2k4nK``o~VEcg$_EFCE<{MYYva^65<)Ui}9p9Z3y3$V^_9)fatq~p^ooN
z)y_|h5EXng@NvV8L})L^mRqY}kTVJIz0-nrUwA7z?IL7woabzAZNT8gZ8~T3=>*_8
zbb9Fc&)G;mc+)z2J~+4t26yog-SkFZer)KFQ*VjpA%2TG3F|+?BoX#B+99SlU7cWJ
zVyTL0MV@2|erk&eFkZ-mqR5}g9SG9Oa#Z?ph2*$dT;ZB=Ui@ExuSNV?JMMP*vuGjz
z;J?~M%%b3b`sm$TP}m}!VfpTUeoTt5%@Q&(Qkn5ftQ1mzZzOg^_dRSgHPM%q7?1dO
z_r3gz)K=>}*7Imp8-MdQ%q7dQRQ@C`#2+(Isnr@&<;<rJ0%sVN>VLUE$RS-v#zZHX
zgQJ@<2dy@^QFJ3CKi7i!=V?C*%;pxcfd1IsD$r(I#-3h9vo=FL6YE8&SM@sz)MmUw
z^5bCwAVoeaL2HL37=2=*=IBv7PVHr63nQP{m(Y&W7{=L7b>KvXZ=9^pR2TBNjI%F2
z_+vb}$UtN*NlR+S>b~R5H0EkV+q53~l!)%pX>UwZ*1$SPf$2n>i;0lXd>$JSWj<yz
zPWTQsh&Cr-Nv%$4abHe}x{|>caXR@gLYY~K1h12j<)!h7e-Y|t#<fXVCUu)s$lL|o
zfM^{kAN)5nkC=xYk!N6#d`=>9(?>d<;Y!rIOV2zXs`n9^O>xy`$dc4%$W}B`NM@mP
z&J&%flP8yeEg&~CQJ>(@#wQ{{S)Y#F)I@ww(B$hBoJPk1bLlHQFOsqx*pobH_=Qn#
z{xc$RG|uraEdDIUJFV8!Ae)-GQnB0hJIe44*=0BD$R8qC0x6`Z%b$6{123ROE`uDg
zaFJt^J+XiJoPe98hv=RL#8AV|Gx2PxFR5F{%p}MZNo2V70^ko~M4fo@zj|F<%mnXQ
zoZ0D5b9sdxAW)L@4A(1^NdEkvq4Lr4XX0Xl53|{kr`RlhTBC1jlAdL>xr}X|h1Q1p
zsXCf6G2!kMXjWfZI&v%cI2-wIKMp=1f7^hMpPwIwkEgD+@X<{GZHbTThXdBX0$B<l
zdq9IN@Np5_JWN%p+J76G5+4grX$wC3obqGg1Nnn(z{g~)q>VlvyvD*uya3t~A5(_`
z*86}gg^wLiM#0CqY;za1G~nYVG$lTM+q*6J=!Am)KMs8iZWBJnU?pw%STfVX$AKrJ
z@0TppclIv=vJ^hnOS6dm(vNNCKP&jS8cm6hYkRc?AK&6I{Evf=)HdN`C|1&jk9jjJ
zeC$H~k!bv5*igVa2UMZ(@wzmNz=xA<e)D(1$3!$GJ}ygc3qE*%$d7{$T>sLB{c<W+
z(uR*;Uv1%I%j41UarzLzng^;-_;^N|Mc||PT(r4{jI`RHj;6%NMLpYsj}KA)^T)vl
zQhwTik1kkA8$PB_xA0Mo63o%)qZ?tp0#u>!@sKo&z{i*8pv@#Q(rW)8G$lUH?a>x|
zyp0l~KMp=nd!h~ah{bB#@G;>k3m>eh5)B{mgmoOKLgC|1X%>NxkIqJ$3&}{U{imQQ
z@zJk)Tk!Eu6i@hZ@Zo9`KK21R8$L!(v+(iQqtWqkU@%}kA5@|6al15&z{du*Ip=SJ
zkB(?cd^nTZf{(wWSi+BkkCZmy<72F(4IcxqwD587U!vn<*C4=pCa6N;<7R0VfsZ%X
zrY{+3wf`F+jQD8o+7^8L31tF)9DMX|6FxR!C2jcVeT9XO(nq4>W6MCm+5<o;e9Vw$
z5%_qHZ90>YR{MiM81eCC7ZV?rA4Y5sZ~X1Zr<|~GeoBmY;F57?IagLed1me?{W3Oh
z4vJU9QWoO}`7<<;D^EendOO-oIG)HS%{j@zH~hJ|Hea#$_=;W5<poKG-ApZ>nzqeK
z=!v4avI<vgd!5Vo;*f!G3f&uDgk<~lagN!;13asQaZ8(;y|<-%>b*l?vQ)(3HWWv5
z7Vc9{)UQBI(fnI8U^co}JH?&gTn>vfA=7>M_O%(_aj(*98M=086-uA9LwSyxb}@Q>
z0*+v$nrx|KPLdo$gWB%~MTOP{<HA(=618aRU&VQ?m{;QP4`Q9jLivZ@P5>XEtuC!=
z&h*};rXm#)jh|8jb6~Yh@D8Ir@yx@~m-Wa1EZId^Olz8f%W3xDmAUdt#1gM(`$6P|
z)&4}h#wB*RWQl2mL|fxbS>w~JHMTEq8elON7de$!+ZTI9S=(Cw+^OMf>saD(Re0)=
zy<MBBEKGBCaWvbo0o^#HA*(x`CmLdD@Oop7g>{y81uZz2k8m!>m4G-)*5n;tsU6m{
zlG3x1ou&6;S{1J5EL28FY|acV^JH1(jrlj=O?Pp9!P^$rcs%dw1f;c{X$}@!XIoeL
zW?=4`24P;Mv96oVWy~lT6S>6CnCqz3lKL8gK0V&Ke6w+4u{mdWhO>MI*6Lzsc>(?e
z-!Mpk&n9?ha0!<`gkf>=GY-JVZnT@531?v)FUAU65Cq(KFKkF>*{|>@@IEqcvD&@S
zn5*5lGh8(2dpi53Ta<lov-kbvndrMcS!bQ$kHFc-#Hicw5PPb`$^M1Khhn_HR@-kZ
zwqH(SdXB?cT8f2mF7J@3<?wxR-Fh4qiPoe`Z%c^rW&)YH*d!w-c;~Udsy{}jbr<I~
z^-po!&tW|jtc<c1p9O}v6?qU-ccI_rDFd`sSP2~416m?i>t&8SPDYN{G7p@AVVlSf
ztNrf+X++}t4z*?4gdd)+5d2JUfggG^!ttZksVPrzmMy`LoYnIWM#o1CCzgd70Us-b
zOKsLCCg8~8X?nN#>5Uz;lsf~{eH55m0iY2{Av(yHHWv)EJ&8aNb9GjbW4$WO>TlY{
z;4_@bnKF|I{LD?oG+1K`_<0EkBz|7$cpUi2K}`U`Pwxo)<R>|o$Ehi|oNFqUvfvZ(
zDPY@|)~W09F!oD8i><lgx4G#7A~9m>D^JJNV=-s&;NX3PaBQ?@_p{kS6wCsITYv&W
zxV3{_F81e6DsZ*FM{b6wBaEu9Q-2mdLOmbyH0~A`k2)C6Y0RQ|N`EaY!Cm9sf+phj
z$^?MzOy^WR5KhXLUJUT={6lma*>M`C-VbvQE+%+4NV5nmtYDj-3cN<ZPw<*fwqyeQ
zk+T0y4lQ0f+4%S4sIx5GsTL^M%1H(>C1-fM53N$mS7}=iz>NvWn#Br87%mnd*_s$Y
zy?lR^HS56HW@DOMv%eFl%4p4Yor-3e<ayQpeg;sdE1*n2^vzf_pJ#=y!0`%qk5+r&
zaVawgSKz_Sq?5ex5t=u?;$FHUUvb_4CTKMW9`|{+=^b#@W$oD1WI8T=x2Goh3hJbj
z1CJZ3fbMy*IVTAjO50BN?8qp1(Y}%i=1O(|VFe$UfI?{iW9@y>m#`NhnSq51+>C9>
zmVcI(5v#brKblPjcLc!apfy+VyhN^|39p<%N9+kzKsv%n>vMEGI0j%kLSW+T?j?Y8
zn?4k}6u?U&csLFS@>GRvS#v}k712HQ%{i_sO!!`l3g1AiRqzo5zQFIJ!{_G2Z^s%2
z@(uXjkd_hfb!D?#$$zW;lhB&*O=;f(J_HHl(M>b9qWUAQWt|}cL=+BY0AQS*HP#hX
z9Kj3qj3Qs|HWpZOnK0w8i_!{z<$e4Ww=x$F%a289p5mJF3eN7wXdmGmE0*2Xr$N3=
zO961Z_*sp<E0Xkah7WjRKY(!;7ErW1uI8p_%~IK{l-#u1e;ryA+F!P7u_skni?a-=
z#<De!;M~5&Qxyv-!rmML!R*dS$VU|bREV{tBRUXl30#9S3jSrRCg_2jM{QGt6{cei
z%(o06yK(kW{NdO41pt4=LI(dpAotwMW)Vwz5!*aWh6?{Lni9wbCkc=y&5nY`jrtAF
zG6Hy1b+H2=MoRl#tlUPm(OI^L#A~XKGoU(VC8lRVDd~x>sN>_O$q6-{Eu;bWd-E@%
zmNrtyp)EwCnpi5OUfY|t5k|xOcu+geO3l9^c9k|UF?Kai1>_{SH#isl4P!W$$GYEJ
zu&M-lR`UYysSAs@#CSWP_u4T;>VgdKFKntK#^N~JEm#)5$_Zl{v4KJ~$M2bD_j9I=
z!Eo*kbH-r^HC?GB#NUC_43M9xk&2cWk4PHVONm0P*Hb{SZES?4QebSQ2465fnbyZ+
z02zP>mzpi)YMcq)K^$i2J?O+hV{DzC<0>7W6ua<~*n%Pc8m_7*G0+baXVZ3UYU!(?
zrruuum%)<!{~%wg_TP=yxYqZ^<C^M+@htecwce%0u4ZT1G_E#l5QiHFvil@Jlmgfh
z{V8vD-u0ff;Ok{E5LPs%pwEc27JZYk==f<i7JWmEcG$V{uvWY=uhL!Mn13S|<$9E{
z@?L|JZdiKU$DFniBcvU2*Urc3JQV75-o>hP2spt4+GwzFEw|3U=h<(Yc~-s7o1oRE
zZH+yQU~=qtT%=hE?%aCkqAz7$aTsU8A4-ZHBnt023yU|zc%6z2_+%yj!7Q9*e?;?i
z%w(2r={UW&IlVgd2AV8nbu19hhS<PJyqi}!&NgHfe#^u>(sS$c^Pxo%C9@OcmT$v0
z#}ghb<~>Fx5g8QR-sni}m;4JeQ0Le-6?PTZg48ZbiB4*ZOi~M+gGo;C-bgyxdAFTT
zl<nc~(;F1x{hgvH?i}+?Wg<JvM)28G+~CUfk>ko1x#Fr2+BoOqZ4%bVSY_kPi8jtl
zy)e!I@YLYjX1w+2_RaIeGwqucVRWLgiG7pb&1Tq`e9=^;GYV9J2Lvs{_GFJ!F!E-D
zd%k-Yz>UH^&)^(ytVGKviLYm+Sp@ftWt;2BHmm)k(UgFXiBTfLiYFp`gX^t#<5aI$
z+`EvUQG=ZmuNOi7r)%r<Ta)0*7_Hwr3*MZrwBWa+Mn~xPg~hvKyd#HJ>9g6cCnBfa
zq>ETHqXYa3N?u*U$$QPxQmP=vxmZp7c5rNZCzp4oeru6FDKUK#xUUb`bS^(xpLctC
zvv+>!*UjE5oy*tiS0*1!n9$#QCf>2UGTDZ?eipd3b9t4t$?RY75vE6xHnb{m14sh3
ze(~vQ5{L4sh-I+BXtaVBOki~A*8v&c-D-s3GXKY!z`ya9w#s-Va2<OM<!Br~4)0^F
zI}67rjKg5^{|6lYY0S}a7|o}2LVm+(tb*CnZ`cRpTl79^i6`k;j->{$Jf$Jb7om_{
zuVrsET_O4m*kgvG@Qz(kaIP$_M>XW&+)826JpAYOY;=}gfkuZmqxQEx(UG<fNiDI5
z-RmGR*0F-&T~%lXivawyUL*$Vovio2`lON=>me~#r|oAN!=?kvP=gO6$8IFM%}$J;
zoS;ok5QU|inul*fY<jlq_Jx!Mr^wjb(Yts;#P$#$K+shg;o5**T7D3&%bAXvc*x8|
z{aX0BoaOi6-H=$f`ML^v2n#la0_*!29#b@L9+QAMA|c1U(OFuKE;2A%_v$&2G1B*y
z34vVf9(XSvCgk8<`!#fjQQOnc)MW7bp-JFf6}sJh#n;5IR;sNFT+bay)-|5P0SWo(
z9LVze1kOSOlluoP8DmNcsaP!2l)Y>UlHl*mR{{elFfhBzIlBlinE&2xm|Z)v)N22(
zC5p3tcKC=rPXl!l65*V7M78)uLz#y=e#Lz`$zUsbCN=PL3=O=4Z(g&uZ{&n#?+D$6
ziZsL)&yv%!fCk>nddaSTZwJ~aXH+tsR+JdrX9$uzD*#6nL9(MOK<Nh<g0%$q25A-{
zNLH{-Pl!r@+X#G6kTiWQ;BsGa{~pu7aVKsz78yBGW}#n>U6kn<l$q%LS$Wm`(PCHY
zmv<}DJGl2^bL_=tu>8nLNXzLDhX*pS45tQYE)L2`b505hidKj0k#I@69?KM5XCOdd
z93254bOCUE0afr3BH)+OECK;9vrP}kSRmj4Fhm3#YBJYb!C#Q*yC#u8yc)|iJ(ZJ~
zg`C7J<RoUPoWv}ZlUTYCi^>0LOX=U^f3@wNVcy`l#47nCTCFWcG6^eSfQ~lIdc;V)
zf#9TgK;>!V%=0iID`%}gO3WJb8TdoZhejahN+ACUj6|J~H_n>SyN56#&<Dtad1Y{4
z>0OXFiTXj8BxsIgLw85X9WC2|#7fO0^@pxU&sLt>QQoWdh`}9taiF}Y#^b$cwedtL
zk~YmPn57U0RBZrCtn9aQ?%;rUkF_LO!b4tzKiaS@GSq9VaCtx8Q*$FcxhSe^q^}_-
z%xte}CP`n8wapEo`Ix(pI~cj6*ri7PvXRf%>hGcb6)Kn-^05uWP2IAwehvlg=RVIt
z?i_Lowa?%^BynhCuwG5Ey*8JAl2E!jjvuQ^8xj^4AH=OQ;5xmKtZw*xI!;#6Do3hc
zcL7hPBN4p!V8K4&u)!_HraHf@#ik;O_!o7?hFM#VO;yFwozg6{sie&>*k%>EXSM%f
zG$mO*`V}{oT8p)Trmd1=EcwPqwuL^&Y!7`-_#pH-aff`CyxCUr<W53KQ(?N-)p{B*
zQ}V>Hyg{$z4f=|A9B<wr+-5ttW7`(LAL>+?HS!1Njj-agyFiX6DcFN9!#V+7bAU({
zpM71Lg-{9&Aja=xo8OQ_SNkWTDN%Y^qsgZPkBv5bH7R^4{C;>$+^s#JaOW)JwF1%c
z=PY}QNM-Kj3E|MQV|2{I=H}wzx~Bm~gXU?#Hp{Dxi&<!TUOR@8F!umllBYsqUghZK
z1u-!Tdhrb{4jsT4S!@42qR-|9!KeH&7ZCH}U;R}{bj-if5m-G!e0v&#Pm`W6l9mz3
zzlY8CL3{xD@1Ql2zj?o%o}W}W7JNUmGeoz~e-w`UCAp3oP$%ljnS`LvqWRTFAD@Ki
z&CRgFDst=nld<MzgC)HEfj?e`HxUXg!ngGCh;&w9IV!p|XC&zbyW!+4YCJgh!cP6Y
zDgNsLcp0s=u@_S9=ooU!54Yp2bZvrBiIPLkb6_Qk8)7h=_gQo7U?pub)C04Oe#;*?
z0qsM*>ClK&coQseGQ*qyBU)N0gkind1uq6J!LJj%<B9RN7ers1uTBQiufuW#QqY*?
zARE|xHGF-<|CD`4X!dixf>M~QT>6Pvx#!u*1&h#Tiy^Pny_!b!1=vZou+xg-^>Zvf
z0VPW}cw_HYrku&q{=N{Sy~C*<m`}(eX4IE$9w$?*_TPb~gk{lQgO-H9{SdJU7ii-s
zv56_B?>>5L;x`=tf*G4QTc8jhdRW$TZXy7w0w%23M0_-O&tbEd$g!&Z_n<Z5z3)pq
zyeANwAb3ZMO<1v)=&^~rum)CaBD**`{S~yw#2WyT6`MF+T1KqrBsP1uRN(suS`)tI
zU$lVl`^P2-GxW4$$0l-)5u2ECI{=Q1O)PE)F!lpLD>m`7Xw9x;v(Lx^tNm-xn$Xt$
zo6y>QCK3>h<a6U^;Re4`^c)ubEiVHw8q|;*VUL^4Mt&-|#pH4=0;59^6^(8it;8Bc
zGQn%kYmEt>%iV0$*(+U_VCL`4MJHr{-j~b?$rU8Dfur(2G!J!T$eGyNqSI2^NkH3D
zAXF@5@`kPR*fN5a;@C_BN3*zHJ@Et_|8kFTyUFMxxI6fjX`A69OqM-IUXpf=(h7YE
z@w#BTheGFR#B!XJTf|`6HuV&5z>6n|S$UPj0kl@8xbR6}7S<Sgn)2PWssBe|?+P$&
z>ffdMH_kwbQvw*D1@SdZ#MiPR=E@C=5ML*o$F3@IeO?rqv>f=enh-~=j*)S~V@!!0
zL*YqCUI-_8RG-A#S8!xRzoAd^)<?nkcL}W5X)K5}?@O_`vWY~zPiu@lpiiAuzS)br
zBa={+vwRO}18)3O*x!)<(m?&P8NbLjdTk*-Ay85_0t&^#+X`Zw<@6irQ*TGelf}2E
z@cFzHM9f%cZ^?ww6%)NMYh#W6Do_}FYEk)SmeP!IF0Im?beGAcAW6=ZaGqVND$&ax
zqH!`RRnOkoJUO*&Gqx&^cg5}(!`+hp-2f_zm;zJOSJGv{UpU8H@briUzmB(QTq?!Q
zfgdQ1uv57m-iB=~d-X+Qq7vPJuCgS{3m2di->oEW`XAtl)OtOZ7H)q4f$e~l!-`b_
z7A|aUZ~q3}her0ljEu_(-fV8${)L#n5m2_P@Z)2#b6+UJ2JeS{{pEPW+QUe(Yv!aM
z@yj0ep_S5Dw#;E?5kcbbV$f4LSSvJ^5Kkp7EJ6B|XUowj;tK)@sJkADqzLknaEdtJ
zqKF;%O`mu>iom1dZdneW&m~1{#PcO%MptAhis%9JKK1||tdSJ4-nl$`3rL}Ll33q7
zIk8oeh>2@S5|03ZN`;LiiJ75=!Ft<h;uS1`(8LQSO*pX>q=~6sD7XO+zEzSNI`)Ak
zpj5|MG(mS$vQR{HUVja`4h`#nVxUD2u7c?FFrqm&#{U@BS7KHE0=!|-Lkzev>7f$W
zGC_<Mqm`nEYHt*J_~JYCQ~<dWMh`PU4<C9QAI_{h8a;e&&_f(dV*@D$@8H_DMi1La
z4;F_IdJqo55Ni|;QQLwZ>Ob_<eK<qNp*AXqsBfN}(keOZ1L`6<#P5K==;Uw>*JXxq
z2pcW@9eoHbEH`O^+uh_3wPJn<e~9_AHU7{YFSN!VCZYS#xc>VGSo9E+ADtcse2Z1Q
z7wa2175(~ez#A4l>}^u?uyD7~!!2l~=;4LgQRrdk5%hG!+z5JTtE_0+A4v&6uB`ar
z7RLv-AB8bMR`hR`5<UacA}L`pFc+N?T9XxjK`(8R6^(mZqlKf%icEBG;|=<m7A-W+
zicSkD-(Uq7V{MhJxC(Drw6Gg4Kk^3eCqfH9M=M1OPe^AGvSRaL^mG+OQW$S&D=qBV
z`_s}w8}tT8tF-U|kQPY`w*hm<M+?74FKwa)|K}${3+JPI8!aqIwP?Zro9MLQ`Wh>E
z8`f6QLN?y8XklBUqJ<j~w1k|<MJq)Mf0WK5XrZPFJ!L~2oe(WFeDPmL3$9jaVFQpB
zNejOP=8lgRH1yIYTG-(~5n33C?rpS?f0{)LJ8q6n3kip?g1^PuDq0wWH!NCM557&l
zFk`3C!X;>>XyI<@EP@tZJ&2yhKoo`10(Azsv5^C+;dYqZ^)+-vwqjc}8Ja`go=Cdb
z*+O&R1q{lz_>`K1rAc06X_B-#mR!=pwy4&#iZsuf@+!-`=*djX+&bQog9H809g<;X
zRGT`4p1lSiX#^-k18PK4t3>h?uo+1t6M)j_L~?CNoZIb;8_<c+$V;Xkagw1&P^YX8
zq~n|Dlq*ntDY~7}{wR7xJ9Hl!*ne4ni$+%bIy#LsG-72ZV$B2nsYmp|8y1Z`34Tr*
z8L>lX<P5Y@G;))47C|HTv8O(_{s1(x?DPL_8cA-IMizb5l19!1N{@?1#-Nin(a2KN
z={$ZK`2_1^qme;<EgD&RV{{sMeLq(AEUdYrk+1vMXrv5$o-~rQU1%g0trU%1ES*Kr
z$ZYoXHF=F;i-zLiVunBUN$iQl!}l10@b_^E7u+C*P477n8;Uz8*aG24c43uNAbjTg
zD()OHkJG;QJZK7nNr|tG__G4w_KD<&CQ`rc2=B~AyeAYcjvv#gPf1|;Al!URf7;r>
zt>}vWoT%-LFt;=ukA`Sx#EWa=i6UQC0^-|(2zVY20!AyaoqN5?ds6+@#z=GCouisF
zpk0IZ;y(yYkkwf*!K6f~ttIdNKyhsJwKg#J-=SC+b7Xj6(z64TZZI9H$}{;}@j-g0
z*?h0x;<~qm#XI1h3Stpho%{{_)e9QHc0+M3J;mIbk#VhAAx|vMBErUZeF~mr<iseK
z=kG9=SVY=J`*J^%tgMV8p**BLUJS8-fTB8-0|%-E!aIgec3z9w1%4}h{8h-bnBXq>
zgd3vxAJ0d_&`iwn)jQ9TPw$`)DJH1)VC8#9tU1a}K86$d^<QFNhv)N1RDJgs*o~Lv
zVPEeuGMMg>mJv?mf3n%wo4D!yr=oSRLivlaMmRAEy2MS&k7KC}x?CH0^2<=X@|k_c
z=j8X{T|g=VsE2bdLmOVQW6(0vfZ+r*E(a|`@K`-x8{oa7=I5Jj&u_M#GldxGB0Scp
zkBxJbHcTjO%JB9qZA$cZb-uCI?DSl`413-Avh}17o*3ifl2`>tcXVsPkp!=oIrd=q
zMDZE39|U;it}7;W02mj+;5(7uty~RU`!xD;Tq@)pCRdrxKLgA`5>oKjJP~3si`V*t
zPNUvmD!%8zrr+)}WLR{4^*VHmYpRUs1K=z94grvh3UBv~>*Twlk8xXirY7e&p1+oB
zs1=zvrTcPt90Ebpt=hgNp3e?ERq~BY^V!-gnU*%JX6!Hrk_gbRZzV6|Qg!>&ww5%@
zDD8X~cM3jU`3AoP4^*O$iY!O)6%_7WUxM5C_F{VhFNV)t9RIirq0<UZ+VrZY9Vq!m
z`YQHib@EL$XFN*#h*a|3HJGuzFl&Z`mtS3oYP9bkSXOdaru(9G*+I?N-k9z(+;x!Z
zdo9X*yK=ryR4(aUF#$InRSs<qKB(sYnK|Xrm@?NgY|cBq#pEEr!%j7)>s<USzS*Zd
z=L`&cOSEC<oFs#AY}{!eaGgoG!qx#$4Zu18Dj}7EOs;B*xS=YoRW`n3{^K3Nt(^Zq
zjJscA?f|~MNbyBYe&h?s;HUe|OSzJ3#wG(T&zdk^g{1MH0LILjKL(7IJ=+9h0W!u3
z;|fxU!Dp_-0W-=FWRa!qEB!haXYy(fEW75~wLHVRq(_B|A7$<TGwpC6x2ZLduYmlW
zs7$rCnxDP~!K@8Db{(J!`S3+1BG1>nqZl_XRpjn6?z!c?kK9=9_X;N=#VhRI$170*
z4D3VdmKkwNy<6;IGJ|f48SFanR7mbD@$9aM3w;G0%_F&W!I=Szj?B5>LP~Y<t5Li`
zs_P;DFnhQEV?cu&;E;G?yHi(>k8R>wIJp*~F)Fzpwy(BvjJU;#@W1IlG5-Utf}U(~
zPraQlr!jq6WBz#EEFLN>YzQLRtxE-H6p!}??)b7%JTw*&XNk6AF$QumGO+hCmL+r0
z^mvAV2A|0xSl84TA|9uurBp6)FZ$S!tL$SaVbR9&!e328qAOHl=se9xvm{AB>%;Mq
z?b7!E(7R%LC*f|!wbka0U?(+aBnJP@_oyZLaLN$3V<D6E>M|HUp2py2Qy-PLBKJEw
z1q<YehP;;V=!gsf<8qhhD#=_Bhnvzfl+bh4jCDCeJOda_q3$VHvh`9xJIi0-e6k!S
zi-uo+7&4BP@O3VJ0>8Rza2;C`&H~~(w)cEjbn;E=Q}Q)sQsHoku>v8GY_m*Rtarq|
z80pKvWo$wbkDEfRLrp?rOz=MU-u$|f8j)!q^TyG%cMM728+`}=UWr<#c$qt?3wM&<
zF}S>PrO4%vDwj-jK;YrgV<uwNRcmxMm_lJ}ceOx*Xth9J-GOT$dZG<*WynJbO2^wl
z{mW57J)5AquLP*!fc^}shg$Glo16oT8(N3)MS&423t;T7Z50?_Q!o+*zt0mmQIN7@
zaGAN5i8Uw-6MV=7@>-<4EB<Nj6OY4CKW4hC)p~8gdTsGd?c|$itk<0W_$j5N+J^hL
zjF<Yd9qP~k$jh$)kkic7R6FN2;vY?dJIx8~M3%YGtg<&jfT$JPjiqpJO)NiHbYaQY
zviRr2tQZ8cZ%s+$9=I1($JDEyMpVKjne)0wp5tGgAbeTfxeota7a#Jd^Ep6wJ=vGv
zSUNv3rYJ@0r5X7ewMyNyew(}7ye`&g5{@(Sh~wlfpQ0p~owr!|%#eB9rUs~}WIUyj
zwiLHK2usd<JcV~{wVOqa9Mso*1%IvM$~<v)J4b3)n*r1}H(OlN!a44?GhCKwt5Jiq
zX3#LRBMvKvCcp|Wkm;J8ARZ`)BF_lX4YUYJGj(q)w3aGuwR>G*FX;&Y&@J+B)c&Fv
z6Gn=%B)dQf&yZhNc2&A@=^oUTacEnIR=vU*?|=5trc2<HRM)jCEdYfPpe`ptISG^f
zAf9X&m<DoKOd0OtLeFc|zB{zDq(+4QKIdXyw(A@2hGRB8KcTR_5W@Vk-MNn0iM~-I
z-NlYM*CI%bN%Opj=4sHfclhr^Nh;mbfc2P%+Tc5&8er26*0w@>!oExNO>Q*URH?zH
zkSwL$+E_F8Jcr8O!@aVOB^@g|1UF-U;H|XxT8wd?IfifedAR>tjTBr81f>%}FSyLT
zD!k`X#jW-8^hu2nme-*$^z=q;W<9|zUK6`PE8d-c8^OCR5w(>D*hkyJO5$r!-ie!S
znC{sjVBsxP7LU(eL(qB&KMBEA(Amrqfv(*l_%9Pm+_!rbprn<tGo**9xk2%9=tD6*
z+z#wq%v;U|WxL#)3U9@9uWxm_S0|Q#5M{dETbXWw%b0P$$QdV@GlsunQ&5+Ae-vfj
z+e`#^76gm@g|B59a!O1-FZq+%>X2tGC`|N3l{8ZcmNUB%1s#a@rbF9K5-M9&c)hmQ
zps`t8gbdtYI={EM2vq+X{F#t_*fAui21QV3X<L_gY7abxJ~JDYh5UPibMvO)3BYtB
zFkP}FyB3S^zB%y+IxD^NhrT=D$`jv<U@9nt5$_w{2=7t}PIon5<XrqANWkrJ<PX8#
zVrk(JR|7(F8~mGyklY4lFW!ZwA#K+;d<2en7uJbTSg?u*$7|h(=cJT37Ys2Z#AdVj
zd6$~8U4Wz2I3Vav$GtQKa{5ndwg<Oh@A3KR<VY%5DtjDb7tewQ#lr5GK=5g`M?o@)
z>P6hu3Ks<4gf3z9C^wk19q6J<g)1-#%nA!~1Gj1-a_ddn5j!BBu8^+ojou+37M#^B
zUt2V+<U5KsXZfknFiLA2U`KNAx_bC8z)x!FW<vtT0<DZo083Kt2It~KXqH~wFb5`2
zgU=D;-T+y>!FO3F-^G1!E?KS%FFYUKI$i)?JqZHYGO>B!VgeXP!3EGfU?&aTtkjQ*
zxJAGVP%7QU4f$`D)KbWwA^KIV;o~?B{Rf|}^v!o@#SOT85sZc$V-S3aV1-i}p=T){
z!d6r1z^RViH3=>Vyg)B>4ZUQN0|q<WE-@9bQ8+b>3$am&oVQ`eq8WwPhHUua8sUpG
zn++VJO-c;BjVHjh_*5Q3@;Id<-e@jW_jKF<JuSF`52?JBelA6)N6f_n#|Q4gtCU-o
z4PxDt+d-e)2-$TyWY%`btXvoFu;r<1*4LLDLevn)+_mi@vt*rjU~H3L;B2_XFJ#TZ
z!HZqm;fmbP#MNkMr&CPRlhecO#2>y59txPBa;`~<F3?*yTA$GC3|CZ$5HN?PXy)fV
z9SmKHerNaqJ&r+f;)^^3XduiXofTCa;!BEfxTX0bZ#tz>4W&M@g}+Mc=W$8M>(O%9
z8ek+1(c^6jfbzUx5ybNCDMMRh4Cay4nOOEDP@z_%J6CX|L1P--)rFU1E2OPMox#v~
zEK1r@!T~lw!7Kj&TQGE~L3~d-xVq34r0qTMlqK861~<Q%^SB#n=Y~!oyvx->kKnxn
zL=8RDkf5}?Sc*%j6CoVIi7=D(?esWoN+emjw>lRypHJI#=>3va!sFj^E>6Z1l#R$g
zHw>KH(Q`IR?!yl);5f^dVFV0j8b_7BB$qqaRk&6MwQpXq8fS>pYFc!mCihR2@8Ut?
zE>H?$5Bn1Ox>x6WVM7hpHm2?64bz3d%qn;a-cMWQ8{Rv1HTNRq2)1HqKw|Jpw5y>z
z&Gvjry9ylj3C&Au0?06P(R?@=or~=QnX+g3a06EXPln)$$Wsk_Ii?~`!s)^bUBU}p
z_#I1fKY8I1WO19HpGh?K3v^tU9s|6JBml{UuZS0$)bde@y$L0kejOYwNv2>i_Uc)(
zSNmwWNwQa6IO8qbRfsci4tkOO`jI*QU^Tw%1KFeKv%nzJ3ePUtr|#OqYfUj;Q+OS>
ztF<SvvfLACC^v@f+9|Xp3Hx#Riv%@)QmBy~^lm#-hVwkIvV%H8t<+~LJ4hM9ZLx!N
zsK>gz3Oh*MtP+o-mLW?>^fcNT!XtpoOBzR$q6<g4>k9kNrsZ##A8D&Z^Tt-8MRy)L
zmfwUypoEX{{5@n;;dw%84%gcOK(LR*E|3A1fDweo7>h9m%x<R)fav3_L;vb`=gJSX
znJyL!f`|eHFd70kVl;ECN02EldzJ_jKPIXFWYdc&J~P9I2?7JW8i0$i-4KhAAVkpx
zO5qxU{O{I1Pgwmym|paFgu!>A^?F>~n#cm-@mx%OZJ^JMxPf9xY=ulf;U|F$AdSIm
z(q<+TPS+sRK66Y1oN!-->kuG&)CxNkVHfcXhhq>7CdJkU#mlN-n%lseO!j!J@vg#n
zPojNfyYLw;LJP}o>~EjEeu|#oh>74{id2UXMk3%~A_>UmGMR{!(~Ims67K1kNB=1E
zh-`N?+A)77vcJ%L*%M0_g=`YWiO6-p){B$1uPd^54FXB@&{hqa&}ee>!f9BKv`z5M
z5)fcAQGkFVaz2Cv>X&w4o`90j(9Ys}kSX>cQ(WSqgV_2J{6J*1^#Bwr+x&|-Lq<cl
zPStahTF56CIilez4rhw(MNFmA>IK}w!$#5OhJzV&6z3}vIhE^hE=Hn3jJ9RaOo#ie
z!b>3-HW~0`Cp#Bs;5T<ozT0q015S(gs***Q;`ARdgd+{*K2vOsGR_BRZv~&H?0T=T
zO1}(B?1ER&jnB~;BAt&n6=tT@=$>RC&LJHOS(?J|0Ms2d)8RwnJ&w}iWQkj$2SX;Q
zQKYYKGRo|8rMt9kzTrcHPmsrA#ZbE=mhTp<f$V`#T;!K}wbK2LcNzmz8K5C;UD|%r
z@VFk|eVLtn6ATZQbJ42+ji)o(@t0R^o~#W@%MFF70*rED>{?Gf!*nb)f{H)6ybnbI
zDQ7iIU7|CAoS6(#xd=+H+&L!-ec6i;MurmWEN>)YvqayWD*Eny_?437qfF?#n#e81
zupo?yr#wpIdO=n23COgq^i1S#^nZ!=A)OwV&)|rGp1YBj%30b5mOT-s<}71szNL<f
zKR0k59sw@Mam3EHF?RM8a%V(-kHJqc(jA~$iK7ih2JX<!W*n^)kE_V)PmK}LE}u84
z&!Uo_jL#Zk@p5SN=3Yw2O?df8Gx)t-Pygo}_*1_Hw4mqGJp(A-4V{4X5Tow`)SeR6
zz}f>LT^p3A=cd4x!M-vzgn?<R({pzh_SJHeMMX%`pp!$<=D{G@$ARY|`mmRSADU3L
z$Lz!WO0Z?2C&*4);z_RXP@ktpSXc-htO@dLxV8#RBNSemYU=n#tjCYUQ7R0!_zl*u
zE?5_#Ga%p`QYjcajuK<~I}R(DGo6Vfc^e+6ASH^=5=NrC)>&3UGMh@>^^OXB%&Rob
z#_jm#Zpv>@cl_4bbA4BK@?B;+cN5%Avu`5bzBj{8Tlz#Ai*rmjwX^(DcFw|eAtEn-
zgwLS2x=bd?Jxd*T{ugQ<rSm{p+EzL5iQlxX!BS;nmM9;7#O}MYQ-H;0Dt%YbL}hdy
z;=L=qZo9!VCN|3Tn51E4PvXI~Xb$uU8QuY^HECY_-hoT;t7%E5as!TUMhQR~oa68d
zHXywaS6_tWklcpAFm@G2u>AF8FU&}|2-cAYPc?+#OjpG=POT&K?x(H>hsK;Ldh>%_
z{(wuL=fl;4*TCVE1Xoz>`w%qX(u1HNjZbiA?{+R?-J_CXoKm2>WE!Z3PZxhow8A}r
z42JoAN}9>7=A7!@m*2;T4SXi{`FCcpr3c<aTVWA9{Od2oGKPW;xsLM9u>GCob?6jP
zA~+LRuZZ3`$dGA`W;`beoxrJ}#X&y`UdDASf*;X&_cg!@LhPdf0^EAupFvcCnWOk;
ze6}O@9mqqYvNGg~Xd*1hw8P);T4HU7&fd_MVoK!?atfxe)|YTHV070wOOv=3HGxj}
z!*Su^D{#c02kwA@;!)WEGIzSlcaT#iY;&HlzJ}6bN38ceZ3Cn@tdvxAAofW+88@h@
z*hruO9LJ=QYmiTlHspcgXOPc{fqiVE!e8{ls0dgf2OUNypUr45<g>${GMePGBk%^h
zh#;RG{&lwsB7*C<Z&l1=raE?ZNO{Y08hx{Q1K^xNU?O5|oI(agj<Y2DP=y0NcGEXl
z&_(I=sC9e^h4DM!VMfSqHavwxET1ez2|WT@huRp*FjEIM`~d|H%FNfX7=~`C9irFW
zH=}d2`+%xf!3K1jhq66LK4IA&gFr@QtVn*0jE|GBUMlC~yis-r!`+RQ9imK3<&0u}
z0-1@}bJck&?<3-wl3yDtU&G=w2PVpzLzX>k&jYy`+1jBzkWv#%Mjpt6CNWG#Lb=6H
zagQE+0It{r?wtxQ;()~?LpWekbr=rL!k~q1hd=#T@K1<<Rq|dUo|*7de%oO#Legvq
z=DQ<c{;LV|Ovom}j9x>;LEc8<98Ah#fDF#L@~WZ~(`CujLGWZ_CWbzI8-0_egyF>y
z?phT<+zO}UR=bQT97g#vY@{80C0|CG^2Pg@IbjvCTv`cvwKkfpC_D{a2cHd>5zxs^
z84-Lg&-6!{e#eQ8!3WKKjKJ@>#K5^A8xtcFkuuJW3kDcd8k8+~<d;xXI--qDFTm9*
zE-*o;t9n;`dZT-rb8!RS@C}bktA^e^Ew<X1(%XH&JH6%JS;Ka=<gPgr+qiem;NE%5
z=(*spEy=;!TknmqBiGnlDfYcJDJmW9q8_-?PDewKG#sL%$AG2XOlA8RTgt>(FMc*S
zkFlp7we6$-W;{K6!4HL}MC2Do!P6_)h9;i&A<_IOc>1yV&Fb@`z#7JHzYo7jL}qRX
z{#N<Tzd=qGZ9sQdLAB3dFm+w2?5jj=h^Z79Sp~P-H%norwv%4l#-9NiTfT^ImdKCs
z$n1nQ&fHDqGJDnt`DwjXm{M{#Ul5D$6VaRAGd%O{pfe$NQ{{-L+|5i|?&fezyfr>)
z$O`0gc8|IzO_5Pp90rMz(>aikSb-U1uV&cxs`t4Fs`)eaIriwWayntxy%8;^^H)aB
zye0o3=P2b$z?aCa9>8C7%Fe~hBe~W8vG*=;QC3_3_>7=VIysoAR8*wq5z~USlcd(j
zID{aEBIYSAD<kVzS<D!PC<YjhPgB&f)4gMMv-{1|>>`RWU>?Ow<tZyl%bCWLR;Fep
z|L<D+xy|ql;H~$4f1iJ!b9^42*_U<OYp=c5-fPpoPH!u-oVu@b%wQATj+x9Yz((vg
z$lM(eO-<%hUL7BNuN-td@qOmMZNgXDqt5C7EA74u&ufiF$I9;W>@w0Ts@?au-Oc6W
zINE&|rnZLv(dgmQkP+vodiXjFo&OoTZ)l1U{r^37UmgZmgxwc=#s4+C@5^(H#623j
zZ%EK6N1ELi#E??$nKSAA|EArybl|a~Q(VB5POC5sRXY9peT#HD-ge*G0VcQ}vpG0!
zrxE|C`sNpilQst*jotVA*}&#cwEKnu@Z)3moky7bnRef;5LJx_$JY*;(BA~NV<vNt
z?`V_E&4p<GN%$5dA5VN=#<AEo*tz$AC-CLiJ3;{#&7a%GLkUy*HQP&d@?<)cV2GI?
zNxQb@?XH@nxBEY_Z*eTrBa2Nx2A>YclC-^g1GT++=dPq6UfLl?MH0M1+Gf49{f>$N
zR!0#V^{{s<a-ZIBDAn3Ny$h9ndZ+%yC`#Hsy`h-Qd7qwu#qZ6*ZnoRulfqh%_Uf&Q
zx>xV{7WV4Bsrts$dEBs9?-cf>>U;I(sXnvty?Tep_l*#F@4kp#lH*)0Cid#BCqKA)
z{t<E<?h_BZbGgZ0y?e&;UcG;yDve*3XWFLD*QCKG$&m$wOYiv@T`QZ(QBLgXLqVhh
zRkpM7mL3#0ZZ!?uz(<#*pTvPGv6bD}&k^kB@4-zP&I%#GE%vwruD0x>J%6K#JdTEs
zjvS1w?(vSYX}WPcLI;zN`5tdR`&8aw-0$eN&Br|!*y<QZgC=XQ?+)wG*|hO_Cblol
z?#Y2r-b^1DO)&9J`mDY4C-1CG>}1$JuW$QPy*76sl5rs-89PZ1Xs<18E40bE_FC&%
zz7f`awKh-3+7Z^XeIwfKtBv)<)>?WyYc1#0I<5VEneECy_jIV7*v^+3BQ=~w9^JA7
zv7X_>EqL>sGWQ#c6JHK;Hut2m>PsrEBWkS{Bq5Ic#jX8PP*rO!P)c!ZPmxW3Oh4pW
zpb-AcHHIt#j^1i4nf3;ei=B$q2k%B9p?982d|Nw@smeK>ta6lp1f5aq?0OF3l(o*2
z2H=4)TJFO|2TpMe#u+dEN<cw;OcZ}5iNE@Yzxs*42GB$9PJKzaDQHT{9sJaE+Rl(?
zn{TVk8bZ%ZYh_j%zqG5&x{zODDzk?2OKfG<Fn(!YnKhhWI#gy|#4jByvo7WrwBzKL
z6DqSt(2KKEWqP_81_f2n0V4rKU|28AF-~lg0L+%m?Szhv{}5Q!I^zgy{Qo5Ug2N(&
znu?+LD@i>1h=&nFzcWRA988Z|r^|wCO@hlvjVR-r?xMntN+od?$Ai_l6~iBsspQB2
zd6liNq@k!jakGH*8DHy4;XRx(l1j8x8Rz{|xibQMQ`?OXYgau-)J$<XBAY!=Z}#&C
zso4m4?Pl$o0sJ=hM}z^qb(RM3Txwb9Qx)E}(&5U;X6Ne7_Gf^@+ifEqaKmIcwEgvF
zH!nCEI=q6YX&4<EiZwdiK`ra>Dl$N$&SO(@m2=qV2~^>oBDmH!IPwfk%R&Y!^rp^X
zAX{sTcAHQeqp3mB#t6NQ?{Q0<%5Tn{{{Qy)Kix3?C;rcm|H{K0|95C&blw9x-_-G>
z%RRMw7~@}W_VfE&lzT(FZ5#hZ8o+a@WnEUo^<c|%Xg>b+X8SY1;qA7O4$a5E-t6Y8
zqoG6d@qfEUhdZcc9bSJ7<8CtkQAHpBND`rrf4!-57|7Pz(#AhEsEmKTjqmRxL`54B
z<G;Y~Jn0+@{*50%^JLiUpD>SY0c0+qDKbg?rA~_CFP`?5Nl~5s2lMPd1pmt2$pR>F
ze9);t${dDgmK84-(MvnLIO!z@FX{9Wi<gn~(jG4v^wI$@ne@^TFIn_r!^>!TIRP(Y
z@G=f9=jI9v0Q3KNKpGf^L=@WmKh1Rf6V}+S#?$|iPX2!95F$*ia~#_MZ?$Lx)U~Js
zu8EwiE4-R0opZ0wyXHE8+Ks9MI!88pj^6C2z7}QQ(5{&dcq4LF-Qv*zE}@onc@5VA
zEz<!jweTsmL~ph)103G2t^*A4HebZyn%eMY`|8bZxaVl-@Is^wu&z*}gO^&?;q}Kb
z?#*?;BdDV304MTSDC2jo-c)}EvbDBU9gs;43LP+9Z{s_e5EX6wzpn#^^f2gvqW>K_
z!1kHQm1n*VXr=?^-l~aG|M@!an(F{+x9vKhzuxR-sYTg0wA&^f&@e*-_zr4Wm)CF|
z&@vsG>3}=*W_vNf;qB@=zyNO>bU-h?*^erZh7QeiK;11G9d4zTb$I<TjC*q(@F1#a
zI$#(wRw(1QL~p7u1KC<zsty=Q4GJBQrnm9U-Gr!U!=MAo;H<#hKmI;iD%-^)ZZiKB
zFCGa6{8yrQBwf#c^|_HB{lv!sH}PL79)1ii=EsmSehl;R!}(8sjC_J0na}ZK^o#t+
zeU%^M-{i-{rTmz*f*(^p;K$U}{Ft_uAJaGUW5$2@;rWUmMcer?D?pFZQcTbP<+pOY
z?d7*hydC1Vd+^qwipo{t&B1RA@Rq=D592M7-yX+X62C3PTOWRV25;PB>0-R~<8LqH
zZ2-T$j<*zkTY|U2{I(o#L->uh!4BiMYP>n|rugw-ztrJNU>0sl)a)1AH^dYhz7uc6
z1G}^7uXyn|GS`J-z4)EOL@Q457%3i^;xSr0a>av;D|9<iJSK_96!DlU9@E5Qx_HbG
z507{hiN`E{l$O#1|M^SH#S7jlwYPh;w<_&zf%f*W_V&2;worR}MtfVVy}hixy{^42
z(cYG8Z|`Yu)yi9K=^A<?FAwsT(m4`?FUH{8&~$s?#~U&9TyapDv0M{A9;okd1LWDi
zYbs()xiTh|^H#!pq-(WIUAqVVNlm*O$vI6&XW<fGm_j!Zdy{A*y$gOz&2in6yA-FE
z;J-KQyT*}#{W!r=vg1;mAEJG3JCNK#LR!m1Wlc?<!u?yz8e@<PB5l>}v*|98`+x)z
zc%*K+6c>*>r9;V|q~jRY&p0;VxddSe9JJ2gB7M4QcRT6es&Cp!`CC0_#^j(l`Qzwd
zlO;Xv;B9+j+*{A~Zk6-5rr~NjM@A~;D4_%U>1jWC_sb>Q=#Xp<9l7vslM3VbWJHy;
zDp-sF0nQYIgoT7U5I&;}2{+x_LgfVc1dJ5f6_@62^w`O@Lf?KuW`w{AINK=I2EIea
zm(Z$ko*DdH2Feb*p&8RY#)U{_M#tP9lu>fnK5|!>UJsw&h-1VFmo4z^v}VoDj%@Z3
zz1ehXmh^KQWMMuv4X*35u;831ve22kY?CZ(wf`TGh3g4*$U?Wd23g3$m7S5Y@Lgxf
z!XHSp1zGqExmVgI3n|w(V_H3~_Xv}P9Vny7g0ED_f*KowvyTLzFfOpOz>1TQ5Y2rM
zO~88@z`?56=mbPUGZNbCs7pw>kDfG#b2^AYC@-YnOW)DLnNj;Hj_50dd<o`#{fd%$
zAE#2wJi@vveY`&>8a_QE`nWr49}kB0v5fxWK3<_W;PE%5kMMYeVuy^R$<b*SkGKi^
zSG;&6Oyj>2#UtrP{;SUne)JO`2h8NZQp));_yK+lS;UWFOZnlf<HyKP_>mdl$LKx$
z$UVT1@s|4uh>13SOp4>jlmvcEP2$J26n;!k=f{jO{P0}PkD_b%F>5+KN=u;yXYyM)
z-pcun=DLUZjpn+={6=%#3Vx%xZXLhTT(^baXs+AFZwv9ZgWsOP8~4a|$S(dybKPEk
zqq**PextcA_5p&0<~lpS(OehLZ`F89#9M?NvKP4wG&>~W|F=UxC9+rkSKA>I^||MU
zYcSSYu|rO~R#RiO#VyZ0)Usb>tqXLaro-l*gnm)xp2M(1CLyoG|9U$lbhXf658Y{)
zd)8y5M9w`oB6CDwF5M$t8@LjRGWy(Or0kL@&6w8A4w(iJl)0xXpfId2!|f1*EKF|R
zY%@EgtKRI2JK8P_?WpN6S+MtwA`6FMhvdfoACQHwt`f2!7a3$>HKaIF7OuoygaI!M
zQ^>+N$V%H}VKFXWi5S4m?2t(SL6L>_fP!Q}w?kL}V250VhKzQ|hIY|xgD<E{*dgr+
zGtCZp3FXE7{a^YW^Y<gSN9*h7$>Dun8?~=nsV%LKf6!lSBS=ag=SS`1zKA}WaJ8Sg
zt#e{nALnX)oTc=!ac0=~@yAS4^e3!pT-`vX**JfM={InZM)C)!x=QmT1pbu<T(MfB
zHE&O%=dVuzJ3Oxjq{@+6bq~|&hO}gJHv8QBdFv5q{Oj{gO`+AajKm^HO+2>id~9a=
zq_sXB)K>-iY^kr$4So5jueA|<mFj&dYhIYPUx>AhPM`B?vHL2f6m$zSkUOGxMKGs(
z`JN5M))Qq3z?T<dT}=W&Np~)>MDAmuCb5qNg~VP3+LU9FoqFzn`dc~wuG*2viqkke
zv+Tgo+q=rK70x#=!JQDE4sthS+@VbwykCk}Ojw?Qw{Ir>(Imy7$o5(nQn76feSz^K
z_R+{tYDlV+aONM%nxFk;DC^Z4DlLw+c)R#x$ShFzhy{A0f}g%v<QVGWdUSyf{u4Na
zm$D(To`9&JLSxt)m`F(=u&npsU^`{_qMR$hms)w@ak}cI>_C%;^LUHX%7K@ZCjU*n
zi*M@Mk@wy*!HSTOCa#K-rSNg@VYr7FjZssblWRO(t+k=;Sc?a)Qrh|iuG3_#Ig)M8
z<AjsANH}Df?O0C2xPt!S90ap$bFsK=nsfV3=j<~m8yjV`LAEuOSp@v=kNw{C2pBc1
z26rRinyJE1L+=>$6rF-52HA-uyj2eHV9B&6@X;CJw3P8T7|;oqB)DQh^3aCBVtfKs
zy)~h2>Nw<lvuHDlEFkH#=LD@Qb+9=BBTK@!Bnjxf1DgLFJ`5#K6`nS7=g<%#<`Q0m
z(Kk_E+1^L}D`%R~dkN0%##L<cj!8wbIfaqP>f%j6UJix9)W+6FRbJGB7k+qTLXCmV
z$OA~C@?#8AHvLRphy&1|i?OZAacE2BE84n8Ypcd{wiRh|sI9xzwg67@XVPY5g>#hO
z2$t#1LOy~M@kQZ@6MD>t95ld`_BOKojX=|&d>k(A`0Omp9*bqTr4$?7n2t`QKdzCz
z0U{9`$r_2Y%D+GIdsA{Pr7q&4L?_;;Ms%#jKCOr`%wtRp)q*PH7*oFm-a0K@E@JRE
zkFiJbLej7y^j+AvQg?Q0dDb*GLJe7yv1K%7F|^If!SW@RcaXk_(&zsCoTux`ztRWF
z-p3y(@2?nU$cxP@`d2RF?WQ(DMRmSGbzg|jYEdz%_3JMt&M7m(bs=?2y3j_ytGaOL
zZ|dGXbx$7^s}F7mqz1frFEJFEdk4hXu-~k12To7lJ^>A4U!Tj)?f=e51_;SrWg3z@
z7|9>#gFq4=^bL{<j`e7Xcq?$+p^lgd)B!;(lH5Fo4g{)S55OCU;JpPysup2SMBfO-
zH>d)>PsVqW0c}npc$Eb8lc_JQ#vHW^+S$|>_hf26(LTAW@vAb!bfPAswRwWxCV|Us
z>7PW5q`ThM2RBEyH4Ri#n5)<X7p<f@uixhpb6&ScHHeDPiolWP4N;beFp}<xRr#Dp
z*&rBhmCw{<eeetv65q8s(}^Fbeyp*6w`TRJSbgv-T%x1Zr+A^6U32FLgu}#094>uC
z!(quy;W$uPf}s@6YdG9T*&V`gpknpGE7}6XzV``+8Idr2^soj)N(2m4mSFgu?pRgn
z*tr=DRIEPuDGF(H5PYaq>Zic3qSgOse<Ti6tUlNog~D-rJwV?d)5^0R<BuW_k2q(5
zjC;8$(&n=5ab@4wJh*6L_5eB8DdomWxi;V6PSOlJ4x=Y)0h~A*S;{UH)}?A$DHjDj
zpCT*LW;t^t(*Ml-NWzU)xpBVnotmWF1S%}x101DA<1OAZkZ4fK9gWS)*cIc;%~tx%
z9gU`Ho#U-)`8=h9=PWrlHZ9lYcyP62>82PeH(Jijl_xrpSRc?znN*E7EQ@|Hzs=pX
zjg+0&CTGN_WyCq|T7^GrD=xzXVlADWg*(T|Q6*<gq#efRVM0*$J0_G@J1XYlr_%SS
zti@C0E7{@mO~t$98;O5?8AGHBN`T`V(@*kIA|*6}%CnI4Z&n|>QWSaGWn}S1B})Dm
z+ox%qoeZOPp2^6EICHAn_^C)puUO8|IZe5PosI_?M$Dn}`DN}J!h_S!(YzX^crcj&
zLac)8SVEL{2~m%;A0&v8b!rf0Mf6oL7Bpcp+;q(1!Aukg+yn`f`891dc9DxlvK<xq
zT-$MP4xS3gjtWXg#Ob91on9q@g#KWAVl+lD#YbFB((}Ve>Ya(t3WbxT)sELb@ui<$
z*0?8dJ+_SaX7xF@Z08=IYl!4-pmLbkNq;B$;(G$_1duh}$4htIcW1Z$L<#4FqQg$|
z1~vd(6N$!SZPIEY@4&JHF^&qlYJ+STMJJZk^rI1Z7q0P2+v8YJ?YnNTxI+o~QIZe&
zT>T^%6S~QROG^V2P*%=gm*ribR_k3W=S`G5`H;=t1IS`KqTevcTx3)NE(&#k4h<+q
zSswuuvHdjeMQxvQ=fM)%hg)~~vNwcO6Xszy90-C2mb`4dpRcqy6Fc-}mlKu)2aewP
z854}l3FIubu1qW_C#k>ui+`C!zxZ8K#AB*>OrwV|OqBVD^bED_?I`CtVb;QCpqmIt
zZd@Y?I4@e0Tu$_14Q*F>JdAi;66Y)IM^oh5oBn7jul96G)rbjUwl4wa!7`QZRM3k1
z)adz$sIY-Lc2tlbnGti8Q-VdQIHlG#3P@$4-&hz0lFROQ#S`Rymry>g1o}&M4VEA)
zu3`KAWCVFTN?SPs=gZ%U#SDZ6P#}uJCLWsu1Qk_;70N8hjl;S6t-amboZdAg6F1|x
z)au{`5NyE1IoT8<%s_$&g$Th(_!)HIInYk)E?jQ616$Yl8{Jib%m31H<8JGiS}o|v
zu~k%R;_**IyV|j|I#aPD$^SuXafOz%rxPu`prx`Ht|G`%erv*4#{&0$zbl1MsCA9E
z2<nlJGBAG;Qakuv(V4H376`VHy2P->xTB90WC5@!E!hvI5f#WL=QO5O2Dv<w0dNW+
zGcCa>D42zupb(`Adm+}=eO61Yd%u;_Ez(yfzEU3}(MO;OW)rNia3sUzeid>#n9Ke1
z{7V~9&vQz7u~ME*%4<ci2&~E1kzE+bLfV=j=}k?~@fbknM3nj4Dl0B<b(F)PVpQH<
zOIVOD0e&yv$Q-pxg%dShQ(8RA;wa}Fb3#obn5E7<@lMaJ;`e#XT2`Z%=)cp<R8C3_
z%f6T74(Pur7vH@9V!4;IQ!v%A=%b2e2{#x0v5M$BDy{`qe%D0em<nKNG0luw_#t=&
z;Vk~X5U(VSi(u7ZynocH3<c@Z8M$~8t4z4O&c=Agn3P>pNk@`$@VSQJRVYZ-rmm@S
z@w8;WcX%qs;3Ua4)p|g3O>4C$O&0_o#89lFrm0<O0xWpL0XNj^sr!OA;K#rf&#U$m
z&sThR6D@(`6o&nV%*3E)7tpsSZVKrj6*{HjktFP5H3i*>dlq*4T_cIYVQV+6ap*J_
z88@Ce$YFIa0v0%&joU7yjq<qIv<64{r}*M`HxjkeRtr@C>m(*)w3IPg9+N9ia7q(m
zk%CJaW3SB^k9&CK87Z=JB<8c*)0b0+X*F{$;$*T)o>ea|?LJv$u~^-Wn0M6Wx6%nI
zB(;T^A7rN0%wA1dDo3zb$!JhFcsz^CzO#9r1~_CHc^^gJGclFQPJ8kmM|nER0t!b(
zN4(7MfhA^Tj}>^eSo0|ft#zyo{U_J>ZtVxh5MA=^Z47k=t*o_h+|0E4dF@Y*BC(C*
zZQKV6w~nKnj)G#bzE$!f@uDY}Tn6b*DLqz7w@K-Cf4b28bT<eHm(H5MHhmP9I2xw#
zdkBJZT^k4;d<u+4-)NJN9h)MLa7rU$r4cr1guU#WIB1lyBXQ7e=1J0scxgnOZ)9AP
zG=h|O=oFyu&k&tvh)y%OQ)y4FbClK4EzOa@lyc3l4(>;X^J(2(*&ze@RGUWFvP<uP
ziJJ=0h)8HUNLk!{x9Q{w2Jr!NzP$o-e%f<Tj@8dVxrqv#f-QW$<=pJ96iT-%v_>N}
zOdgM>anJysTlcwl#CiTs%ENn|oEI;<5|SHe=z2TL*=&%<_(n7hx4<PdyZv%{q}9$E
z2Je6JYFH#}wvv5F14j%6%J2Cx_=NnP)=$#*cm|}cF6oopP_|~6n*SL7KahY{HvB2L
z5}EKom(=ReXL4bRob8mdW06r*%C?t%7w1Wk3rFG-hnaCwcD$4w=Np}hbfXEO9#y9E
zJ1hWe$QO9|X|{tDUlk5-!nTCFip~x~yC5rNta$JgPwFWK<`l-S14Wdvfa|Vs23g6&
zO!gRS9@frl>1JH_R^;SVWXR{;`VRR>abv^J&$9ojcY3VT^QJy=LMu&!VrpF{xf97g
zNrwew07RQVCecCE5~vH@2~n*ube+!7c&QdMZYAYq1{D5wjAXjNHC^#;RG)CbQN9o*
zkfdsX`#oP?KPi7Xr4k&1{Cp6I+e%B`vv{YM7LUh_T~00K4VLoXllD9!ZFIc0L3UR=
zUaPgPlJ@N12^g%{8?}an$J2>&EIZ0OL2&)<t=zMFn|L&$6<*Rl@e@;dvd^v2OR5FM
z2-is@9(2bTRPM#7S5@nN&!XKA<BCmlVF^b@P>gG|<Qgq!=fe1;IT^-Yww-L7;5by%
zcm_b_{53pLKt5%GV;t^)m)vzQ(EaWPf(nrMymibxB)kXjw)W27mhLE@jHWd1<xP_E
zrb&5Il@41l0zjv{As7L{(@>wrI_&;-WXaQP>p6+1Gy5Y}cXikNHNlTDlFes1nu4$r
z2%G3)T$9drO;hU1dBebypnA5O<(y>0SF+saje7^9)WT#n6L-aE9CZz|n;GrtBj?4Y
zR;T3=i52?h<tif)^vz@Xf})apiR@l315Nj0DgWiDj9#*b8J*Y?qgC@lb}yFmUsf4K
zrqPXoHgU=G%#m<tiNYb(E>mr3sNsFClsHHEVi1pQsfs7@R(7b#v0xSS9dsk6;xe+o
z%Im#dq&>LxBQHK(B9%$XP*H-UO!~qq1-q}2^HPih9&-rHJ=B-;XdZFQ<NKMg_H&83
z#FbD*y_Nq1MaY%RW-|Nd+3D=V-STAipo0$ud9$jPL(H&ii%W`DXX1>rZlz12_3@ag
z@)Afl0`$k|%zl$AKJ);5>w7BQd&}!RkFnmIYpzp+WWg6yK|eo;xrOLO{&PVuo2LU!
z7M?B)iSN1t<gh{h-@NgV^)y#(;Xsid+OgEx1mrw35u}}6zR8Oz2IkHz6ao*eoJC+y
zsJhCR6Tk&IBm2bD?1^U_O@nyyMTB_T3141{+51%H?`X=6%az@M-tJvaNBN!j32V4S
z47NTn66WXc@cM$+;Umv23TSwj_5{b{E7l)aC61P{JI$5rb7hN_jW2Jskala3Ok8y?
z<$Diir|kEW67@{>Wnjg>gRI1ut9TS;%U9Zwqnlkqo}A>($^;vae6Q!1?Tq!LC<e@|
zodDl2oIW%ICrPWM1CQ+g)mo#+DmVwP{%4@^aeXeE4#Go9RjS7+{GYD+c!bs#YXF;^
zXNR?TH`Wzc?2$3(n0Ek6+f2#5PMJC`g`zOn0wr)*kR0RAQIa&pv~}*_bzDUix1-Be
zl=*j*g@IzB0gapK?dEzVI02M~-qyT4Ae-af8!({)9>;49$k8unPn8R&C9lU7acMs}
z?&}UvQaACmW9KgHj`HiMytiR!;S|SxrvXi*`o|1c@jbm}Pm*%hr0$clr%H9!J+wB+
z9wKEA!)*j$CtYE1?|o=d+IV*MB%j?jG#gFyLv!kwRtRwck}lAKb|>nv6^i5LSe7<e
zVrXuk1{F$a^RuU>t#aJ8fy$I@iE)&7C9=79zyd1S(#{hLhs!mD-UawfoOG1uQUP^&
z>5FX#*M-y&jks3FQutytek&Ld5TO?!+sQu#zr(CjRa(+uag^5r2%|QL)+j*=8~rt$
zA%kUEM3&`Ok6FnkL&H{WE-RiWUjPOuZY<fmj;>hrz>_r|KDNB6c<_w_SW05%8p672
z7_R5o(lidrGZro~CP>9@n)V7O$=TDAf0W(p(&}cmlj@MD6E?A&H_5sh6K(Jllp&;o
z&*KGf$gXL;YzR)o-;7*EZwL*M)KNYN1O(gxg8MH5ZX?#g*F_tC_c|1`1T8=lvy7C#
zB=B#T*)U=x_Zmpf80aTCe~F{K6s5!#@sb9lUv4M)k+Z$LAF;_@om!8gWk0l&ymdq$
z>=&24b;;{Tq;0tUr?ip=PllY+ko>EZvwT&sos?6z>TCS_o~Kt#32M@QaoTHc88I}c
z?zW#}-0z+3eNWDLFD+-er%ML?PPg)oNc)lYi*KRJLkJY%sObW2Lm=<_3W0<CC9=0#
z0uAB9bWPz)E!G4P1#QAB`w8JV7Ry+wvJ)87U%)bd33i<S@;lQMBzv7mwwJ;o+Sp5y
zbJqDrT45zMNNa=GxDQ@Ul}oB|s|B*b&j8WkfTU4?GrLWxn}Rs5L_#x+T6z&J1yVV(
zQO$|qHM^DKc!+F$Mf>Z>IKhL>Q9ojL{FhiXsUACCJNXI|$r$imgyl_49ikO}SCS~)
zhaSG-em+-{B4q*j8-O7^Kz`R?QEZ5K3=<Ehc#Om*40e91wnMEe8!e9(zvj||Y)Qqp
z(UMn;fLrhyIdSxOB7NJ16}RM?s4l7LQa1OFz@e`JAX9+K%(|GuKRkn^=80ILx>h+-
zI$bxsEp)n;!1(j&G#$?ANII=qW=5w^8jW-s59TX$I$>O7OjU_<?Sf6OXy`|@%05>j
zP0#VD&nry|iTbxer(wAxZu`CoWf5ByJSnS5gyBFT*Ka^ZCFJ_h*x#E%UnxFs5o07V
zBm=BS@AE9JPijOBzdnX$^uDa-ea+PSIy-t_cD=86zEX)}?CadHz8*vw6TCX<eXYz@
z@oGyfFY8#u^0E#!kL68NV|lq8%Ny^b&>Y7PbH{KjZ(>9&Z=%KX7h^1M<2Nz6xd;Nv
znd8Hwc@sIBCv3O2#_|veIr>=MBp6di7t4du!Lhsoc>Fn(23xv?SYET@!G6%tm`9E*
zmiN?Wke$Pi<z4iEX)KRPdLd1ln!Cw+8zv&<&#+kDW7ssJ#`0jB<up(^vshk!BiR{<
z%lYDG;EfK0VR7GpS7pZIpqU!SdmZYWCdBYK-irU2$MLfJ;pQivKk1G_L^$2+0{5b<
zF^)G0*QDTPv(ZuFcxS`I*mwvRtN<=}I2*|rqFI_2Zg2xkFbnA6a9Mnxz**>sjb_ZI
z9MGEtss^^h>JE$VH;d_g3+HfHY-5TV)BA{jnL<;V-!)Y{risUNdPIxqal9}rrnj+?
zl<B|Fo)XXseXYlCIi{h-^?pLuIjntKkLx9W%4S$#m8kGPAJ<cZ8(xm<-39_RkLw9S
z{PPoy5W&ka-t@g8YHW{g$ASJ4_s~a)?LjhW2{@RBx*FV5*4KvE-lANhXJl+Isd;Q~
zVpwcX6N1{0Nj#<i8*?F0%^;)2Y`RX+q9tU%tV7N~QkZRs?YS8MCjme)XJc&d&aIH}
zvp$Q6?M=m3>SG%E2=s=zYl!U$B*S8R-)@O2|NP4o>e*EOHPqF`SDRvcb4PJ(@8<us
z5Zl}MtcdMB3FSwqq{2+pVtWl^n4^g8O;ST=h?VKFJyx54*VSfZY>$7>)_*@nvAuB-
zu|1B7ssOee+k4;u`@7m4+na)Q9`2Uo*xtqi(2a3e-;u&JkM2#Ai>D*HcQHlxreL8>
z(Y@(ymsj?ZVy&jf_ok3G+xRoApjY8+z7AtGP%Nu@);zv<Y7R5)NaA~=;VDx?d@x~V
zQHXC6v5$gQwxQ{<j`BV9=eXR|rsY_iSgfnz5Eph0+!nIaiEtDJqQ+t-S%X+q?TCrE
zm{HD3k<&TEcOe!W9OC<{wpW%K0FI+xMr(fQK-rqnV!sMVh+fs2Gixcd_YniaQuTx?
zRZ>nPhlenOd0r~}+U9u<FqGbbsL&Jg2*k$h$*VUWbd--ndGcgd&^%ipBXv=icL<h^
zUt8D1kwQ>p+N_@@Z}#OP%CJM)7&@t-%IZ(9ag;AYG2dXUmg$yIv2Po9J#V1|o)qAt
zcp(COn-SeBrf8fY6z3ly0&OG2nsEd#7Hdb0!eyZvo)mzLm9uO(2o97fnwOjA-XZkt
z#>U{IV0jfx1`b<cfKtqAEVeUpPcSDMrH#QMq}YK0?Q>fNCbS$1%soV*z<de?BFLoX
zEf5fj%!|_M+H`n2H5d!zxB{t1SuOHv!bPwndnFN$Z%32r%BtDFxJtccje~uo=R;d=
zt_+h?o_i5WMR=<?1tt^e<n3rjCia8kO=F=Qu$jwqbJ@-~&kdwzyw}Rb9OXN(@jz>F
zJ|wt`OZIPUf=$F%s;WasS#JFRZdng;jL(l4A5b&K_;7Ej9^)JOq8{VRPSM<5(70t^
zQ;bi98sp$im-4Xp59@`z)?$2hck6yp_!nA_@rAIHsLe6H?>4|ZIlLGjbklV51G=28
z?2<XG7$5U=9r09H(MJ{I8=uM6nHJ-lXgTIFzKUZJ<J;I6<I06!Ud|pL9_5=ThKLfE
zg+H!&jBmht;@n}!_@+pC(-Gz~il(_8)I7#F$q?hi(887#`^E!mly5V1O|<!r=CkH;
zzA0zBriaJ*?jwDr#v%?g&UbYNv;5}LVoW}L4RJn=#)#F3n7b0`n@E1nwnqB?DMC@F
zw-o8q&zLli_03+_CT@8a>DF4?Ii<$>t|48n(vNi}_F(O&aG%G^I`NhQj`OXSvtf$F
zr>!cy88Ip(;7cj1hCe<&xsJ^gaglW*B2QZaT{y-!AE`bDVf&PE%tN7h=a`BP+Pqvk
z5b9W<#_fc<B>%S1e_`z?vAfZkhp^v)V|Sapr)nTcdqOJ<stT}YrhJnJn;)~RwEIuh
zzoI?IJTDMe+8K#<TnWJ<d@;rpckt2_F0J9rNJshAC_v32Ovc-|h;D6+`AvlED=|O7
zY%7qRhls8oZvmoyvw;127Q#DG4BSMX#1z8f@MC^3RZU`k1xnEG9^P_C@yaMMzg&*_
zjrY+$0@^;{%NxTnzll~37pig+9`n0ekNG)VJfbdDV}8)kp0UZBH~yw-Xhi)kpr{|N
zTV)sTypO;IME!KnNAsv(fw+6q5cdm|>hoLcaX-@J6i)_imAKy~7!+#U&yHx8i2Lz$
za&1`LPr2jREcQ3D4v^EHk_tE@&{``q8;#NBke?=A<#F6bkN>rxZ}?7O-801TKQG1e
zl=xpAf<<!SbS?gOB7o82f5owB#fbmiO6A>kLtRrH_a(!OR^osA=(TW)<VF0C%x5eg
z5CEJm0)U8hZ2TI|rc~^6cij6gv`R6+DI5btGbw0NwGtJRXAq9cl99C;q-H}EMhHNO
zp_w0z#=??Apb{7G-t`WZXhHxmhA4-9;_Eje`w&F{_woJe_qy?2L;x?R5-M%UuN7sF
zDGwUi82?K}2qyGqK^5YDKhPXej@#H9Sqj>~sY@LdOAH~uU309KH?6@`u&;{tUtTPg
z)ZzRBY(AXYZ14?B!&?IF6ZK_J!$ZXS;9FB-ePADK&Ps%)a_XAK#t|+2^YfPw2`cD%
za%MsuxOld=4q-op1Jm}*j6pn6iCKYntcobGza&s|4Xkn36b{y+m7pIjK%NkAdWi6p
zUDHK8a5Vk`(iL>CD5xu3xN0!)6ktSgWt|qmXGA+{EN~a1S8ORS39MRU)nb8lX0gCJ
z(^y~~#{wGwn}`KAXtBULiUro`vA~9?vA_l`7FhCLT1m^XKyvJ;vB2+Z5UT*eF<ZN)
zpfAL?K}<+_uzO@Ike0j@3;Z0{V#~!-q!Nw=9taWv0J|Cs43wZn-9xLz0_zY9#Myf=
zahh2ykivvuO$i=qEbvLR6gZ0$k(<T>ZH-3|3!K}FVqCUuEyn`q&~fb}ig6WiAkgp1
z#SnteXgob?vCFxoFreSX&Qx;qeD)8Ha&=Nef7oAxuY<9wmRyt6k4il7hYu-~LsXzL
z(|c=it}`!a77sikTIHYF7Fy*I82=NrdKD82`88Ft2wK^&*QGhFR<AMA$_XJ*Ce~lh
zkBAA9Xi$7^i5@en&?+l2K?~|@ak{svjd8lap)AMFh~j!oa6L$=#01OGV?<0)?bE6E
z*;VV)7^k}%&FC?~|JIoHb&cLv&**(^32HIVXVH!jBx7HvhV?bqysv#p8eT6AHsHm1
z0K%?YP;z*s!dQp?Ioa>F)6kG(VkYioQc`+@#xZD(zQBSmtBb`M7wxAH@skoq4R0Gq
zVR)kvrz+SCGYPGqYTEi;Xac(2y#4FK+gG67ETHYE#5s(0m3?#rQBV0*_2HMfZG-EB
z1JXDrf)<na6&BGjy?Pk=nv1G%MADxzgSA73$5NZ&#h*p=r$1vBKjxLv1ONHwm5UdP
zJiOl)2<K4wlD%^G0rVOlqi%)(I8+KhS+_z_2fiK+Qg%<FLV1{9Z87PnGnoF=b1tIT
z3KV;)4?fFI{60i!GiEgF$083uY*X;?72Bb90ylq&*^WY6KxH;{5yoRGk-L^zkc6#v
z0wSD_-|LIzG!K>>A{HNouED|g+`ZP%<aFjVQ8T_z;43t#7Lfc3ov5#GKsIVU<2<;|
z#de72IU>FT#ZZ}0pi!F@j}#q#$shV2WV&pxd?J&{-c2DBet1zkqe=Iw(*Y>vOFg2D
ze+FMh!R_7#zVt$|!{N&(+jPEsmu2LO7#~EtrLe>?IC`0JrU3n^gr_lL!W);NNEmN2
zh6>)in4<Bf^H-#qB6#!aNk_<=foXpZZ(bSICf>|LvBTlbg`exZ$wFO~&S6BfLjH(J
z*PW{ovGxlSBHqxo4MYrEe_~5_F#_8*sRNiQXWJ!v4}S&^O-&GJfOa6Q@lqxzkQXOS
zu=z4rWx$ylrY~?g5v;pd(iWG+OYt4BTebuJk(We&xccA(k?%@7jl_}I2teCxW%^xd
zel*n<=}&~>;H}7~!`KRwOGAzIsG-sea!Dvye+t(b1hZNMw;f46<Z<C>5@KD>0a<B#
z&W^w>7%C*2HL4!#5eG;C@%IB!rY027<I=o-KOFk~{gPJbmqi8IM88-B^CRhJr`j6*
zl#va{x4~Ed1$CWkpx`~Iqmjpqegv~tAR7JF576j$F2p&EexGy^^m~!Y93B16&S-^x
zov1*Y=(mP82Smu<IxLu5MRohx8mc72VW@_1`kX{%C6!@RHJ>2OC4QbbeZ@tXNsM!6
zAr5@ndE*zRvN>Ru4`+xWl>=6g>1?M>jb*jGRq?r=Cc5P*p2p#op*fo8@bNLWr`Q&t
z$+ej+Aj}KWCNG_@7^*zy25n2pd>qW%*LDP6eTT6N1AqodFTh}&Q}<!ZygC)5&CAdx
z5e4us?+=r2rE$Epkp{)ECKVd=0~BE(1Qzu;b~Gqak3a<%4mRTcCVWglBCKP=y)XJU
z;(icb0R!$=pb-W4_mU%VN3sWmkW3WfY`Z^0upi_rT@BPTnEe9*1pPwn_a_p+p6{-S
zcU}T()HrBVR<QBX_zu`sPima>tsTEAYFw3Q-vpJjTb2pzjBOKknP|SOCYFW;8C9nN
zIR%>^`T?5_m^YMMD&cmWVh!g&b3)CS+wRNB8Z@`9pTJM8+wQxeSJ1k-?S46$h-$kJ
z4{u+A_GbZY3$}ZE)HAi+XAF$A-DeTKo=qV;WY$96b}#V5c!%{4_eUG7_i1FL3hRBk
zVreT|nN?d^wceMJ3D<oF71FJD5B(W78&{#&Q&aJowLp>5X3RZow$EB3toMbw_5R)u
zP+yAmK0eG!WWN~%@J497u({Y^y?=rls;ot^5#KTtA@hc5MWpMMD$JXCeW5so{r(%G
z1tfiJzY`LqSkJiuN1KiII}@s9`<;1n!nuDIZ%$<^u~pveg;{bqyh*}=SCu!**-j$&
zC^kUQhA>(lfjjHAM$GdD?hG+lmZtW5PeXw)-pm8(sP*srXuP><w+U|^xc&%vbJM^-
zi#Kz~Kx%#5OhmE6;Z1o+=S`x)TnZ!O#pehzKHXa*V*<uoGZD`&XqAjdY`@QG&3?MF
z&Gu6jd{L41QxetI>`#_TjM=|_5}`8;*5@MBFz5_3`;%Z+i$t~G$MgbGh5cT$OAuAF
z-w#ejj0JG?r!q%pe_jj&vBmYz=~SRi_Gd2qYmxM8MCt~ee!Bg>cT2>$Hc)Vi(PlNH
zAHm!z{koi~(XR}`OhT#AZ^gBOe%~h@HT{}gt<djFD$pkS#RZzvZy{>8ifV5{Lx{@5
zkl`>?H(Vo7Z8}3mHNt+Usnb_H3p1B-_GJ5=owS(B9s{!!+jaV@Y`e0nSJ?00bvDr~
zPw`}-*zY`xll{)tfUw^qtN~@(gh~!2huQC$FB)ywA6{YXV8iMFkd=20U?3Y-ol`%%
znj#TmDn^?Rp-mzR?DqqwN7}Gtzqf$~4{g?HFbz<Ife`qn)3Kw0ZofD7GvfZ!%jUQj
zpl>7YUrq_b{V_D6;Qsq*k+`>Pzcc$mzQ;Fd_WMl$0`@yoU)b+EPte5sXzcfR1v_Kg
z#Mw$TZ?NC3Ku*Et9Kwd|clI~a{uEGw&&QDt^0{{syYo-OvGkIi7SBW_>4a)0+*J<O
zG0eW{@@+*jGHlT<+C*PTBOZJ-6K%1#9#8m6FoclIg4*YI%6x{y$&J`+*_rkphz%rF
zayR&4eDU2nr^oX|5#J~9pcB%pl?Y@_v0Ab`e<8@;f?xv}b`<+^<B?C5H-QG;!r`kx
z#>-Yq=t(Me4;Mpxz{f}CMVb4k%tddY>6*Z)C`wbo8HpgrZf$Hwp@%#1c+mr9TN~(6
zad8+uF1$*k$I~yE)8pyk!1b>$sq~n|#Uki2hsvDuI@6;wiV{5>r?!P2=bw7K=+UoD
z^zhPAJ6%5dU#ZdKAB)ZD@ehOr0(~JBLO!N*u?TwHLS;^;?ejH(-#{>;N7Kn|p~qRL
z94~qdXcIl?Jf?vjr%cx9QTDt!J<8yU5A*<%f*zB&SOh(;qB31xWqO1_FrvrqgtpM5
z`^m?P9(~$Gk9-OO>GIKOl17ih=gjF*2(Nme1CSK-7|q2Z=y55PIYf%1Ch$23M)dfq
zXItpe9{a|Rk3L17p*H9bHw9jFdK|o5qsO(+n$zQ2L{b9#Km|dMVO%VN9v4%YA4qZ3
z1U^DhqQ{0FZK206J&qSWD6wVh^UL`ZL(%E+{ogct<RQV8+5D0>1h{?&DhPTE;9?Q<
zIG4(N2^|A^yo;hlkColqLXU5|A1`_!Wmp^NaTYjfpvPwuHF~(7Hm8T{0^s@ys37Q(
z$i*V)aR!xHPl~iA@Dhp=Jzk4%3q3x@sf*(?UT~VT4fN;^P8#U3_A-qggBF?7W6)oL
zYb~fC=wat#5%h3SnGZ;j)&w3yQKHAcy0wKKA9g!l^hj(IJ=%kl270WRpwXlEQ|9#O
z4c~uYDX1Xm@%ut57D10D_{amVk|M1M$S6wmxbLL4(Bo~~Hhz5MBdJaF_yyP*=<#B{
zMvrccXmk6t8{zsKh$ZN;>t81H*p1{OfhS3k)&z=Cl;|<1t4a^m-_8rckukGig%6V1
z$=eAwIgH+>as3?2s$oJy2dW-H)$>9|xo}_y{unQO?8<%<tYu2#^)Rmu+e6uES5^Yq
zT?M5b<^RDC9HNycbtpo3VW`V~+oi!n_=-J!v>)10z8-%Rr1?Era*n+~vX-sFVIw=T
zMT*jnveopv9LM|IZ3W1D_HSyFn{t#b;U6vXm{{Lf>(KnTSuYhhJ#$u2{5kdW)M{j+
zL#|6&auoPGVhvL7y+REbcSaI#9LXlTe-g+{>8!-gku1;c^l{FUAhzNtF|HZroCkWJ
z1ct#!JtkJ`DYT%V3dCJ5eHMCRMF({MZae(Lr{#h(vGr5Q`_vCf6^H15_6erbw$Qq!
z;DvZnw>IuJX2xFMgm^haS*LWSK39-3tO+~>As`+<=4gS(1I&3$?p~F-odKT0+@w5x
zANMfO3X)JDxj(^SF@L%m$rmgJ!4wuxbEqtyhlc1_nw6pildKAt3opgqe>sIuEtEfv
zA_ZyQPdt<5OX7!Kl2CY&a!TM5SR%G29E4NYDN{j}*HQy``FBNV-cl21NwuLD<(`gZ
zwT#FxaX#6*ydcBl6wIgx+mZb1idf`#KT8G7T4&(*bdVGMYHLaGZI84zw3+$FS5GkC
zLd#XAanj^0&-uil>mNsD98turFng^HM#;Di@teSbC#)6?4z5R)&Z9~IiiV+etFclF
zRr-qbSWVzP)FswdpUAAG^`)BoP2Yzl7{ROV{nYeVClVv}TRb;#>+;B$BIKVRnrnBI
zEn;eRDqG!-vdGubaPt(RB^s^BHC`aKBXz{7*|NkIdunjrV}R9Uu}psaz{vm+`;`^B
z-<Mhsv+1vDX#<H*pn#0pIF+X%@c|79rY|VI7FWQ0A^j9ut(-~d7o4OFf%XhQgxa@J
z@5@NP)dUuRnnb6E?HZk+=Q#g~7VwHB({d;?Cet;|$n=B>nWigbD&xCnK^+N&h&t0A
zHK)!rxaR}E0dnZI<*a@-VS_mo&LFv4%;kGKa{_hVkMaXBL1Y%gp4+DKM4S~w9IoQ|
zH?FKnFci@!L?>UQhR`d__eThj2r7MpP)Oi@C?`<qW&lG}x~(%&NyJ`TrqKfE1g251
z2pSb$Tp+h&@rf5eYv+TIwWh|f=dqotT_|4G9D_cg6^cjZOf%^F5cJDHU?{}UKMBc$
z51SzQ#{d+2nbcrSKtgFk($`6df^p2?%xUytvl#Oq;fjllR57J}X;5J_fcX9=%ttsy
zKr;lT!9$+7TF+(_(Y6(KU}WKVN~F+?+KPgplOacY*qdk^?@j`KGq4ZcO$eTBhF~I<
z`3MsM5L}F+gy733G?R6B$avn>b;0Hn6b7EDp@NYXugFh=)6<=fU@^}O%rWrKs`76X
zSYarlAocf$OxSVr*?`sxFo|m{nj_7MT|&k7k%p@YYzEeZ)TcH^O7$z!86uw>`9bZR
zAC%LbDsH}g>GAD7@c*gD{j210xVob5jabUgij#eECn;x%AD0%8Qxa)fY?L#VhT+f8
zDzm)oUec5sf0>d)z`MlA$yk+><3Rb)BUzsQ#G8_Tnh*7o{=g&-C<Lb~8Y_=WMvTP?
zRII%~_#04!5dN;CG8Wm68ckCI0<igUa%XweUZ1`5z7asvuA>PXV-)b*DyQNY3ebxu
z^ki>5A9n`-ft!#~q_J~v5y>V+>i>65@w*L72rX3bd*VTJ{GLb#;3<Guo4yLUWCVUQ
zsn}VhifaPx6#P0g$Iol`$B?$eP!tb#8>^PpJ|_@%Xb2;_F7%=7EJD_ITxrf$4C4&k
z<4D-?<obBB%a|Ak_VXBxn;^2}euX0@V7n?SXj2j2mlpux4iUE1YyE&mIvB`i8u7it
ztXL%#yMR<`O&}hniJJ)>nvKb*^Uo0Ic-F0bG{zKRY$9EhEiE^;FwKVp<(akuIsFif
z9@a@TOvCp<h|vj!^Abo;3WtgaOHXx`j~ftLsbKp7&U&yKh|oYE`~{ed1xG`V5Vj9-
zu?XHiN@YfoZmkLQMNz`Ge|w|s4l66MBbo9UU`mU2qO&~;xN$MO<6g=dOY1K&nW~nV
zZZbN`V28r|V{3A3Y_0oK*w|_L_SsIJdM=cU?Q)?_`Zf8-jlZJF<c74m*+|TYw4t+a
z@YyqPo>R$75u3KbG4Fl!Rv=qZe@^w>5<6sXj;B{?$*0HzjjsJ8NE+vW)`bR3P+60B
zwrVJqQl{!sfMN~ah6)8$=_rmQU}^hj-cTTSKyn1B(1!dt<y9yrOx3~+4Ta!Es6!P%
z=Sy)^PqjGNevH9(S=ya0=1g$)V-Vc{jB4<PRMWR#=$~00H?_6>ew0*9Zfl*K8&{SY
zZ!P`C>g^RMB6cDxJ6)MW>xx2xK*>29d>UuV0=JR!MI%pABbp(rH{$6LxRi?21O}ij
z;(SUBaXyfSuUgDwG+jQVE)~`j1w3G0^d;dCppSf!_cjteSqMHMit%nUZE5Hz+pb8!
z7_i@OaV*PUFXh*zZJ0fqMWCo4&Ar}(3|+WytpU_VS}jWR0ZkztOkO)Qf6MF`Wb>qa
zANMXs>vS@b4xNcfT*|Kwbip3difTE(+EM;4b&nkGtCQEFg$7^j2pqJ<iq5)G8WW3U
zs-uinsbFQ=hB<f51r;Gb=arWDEgo#QW8uNhLP!v=VPB`BfXz{U7xjy^q)2CiH4quy
zbqx1vL7h@McL|a5TZ6sP0%UFkdQ5XSIOb96W^MUHOWg(dph#6AN!6IxASEXy9SP7I
zf*EK)-PMEhh%hNdzjJ?Oc!ARxWo=bBM=YRq*g$)2x3eaLW6uK1HSkrz3C&YiLRh{|
zMbji%x8RxOxr9V1?>>l<vR2jw$=f&ZeHAqq{4ZcuTL^xs|IsJdjU=*>Gz^-tb2HG-
zSooHWiMKAcLKbW2$C|)GY6-IVjD=<K6?`RGY}M|sCSud_=r61b_2p4vdV#Djjhvp7
z6pLTgt3+div8Pe!+&%zA)4c#29u!UIX59-yn5><$dO@Fl0rWx(3DMqMEJEk@r7|C5
z?g6%Mq9|dzwCOityDNSds1n?UG1)%f9ao9_65NfokdJQiov<>8A_vTj_=<hr;qr_b
zIKg`o?Tfn+t91SM(vlq(&xKeX-%90rV(He6o3N^`58w;~u`c$6J#;oIN88*wv^TG7
z_Kh5RVw@*co>7GBa))MMh%94)wa9nOq6D<h&|i>uZx75{S$nPj5zFW*X%#Ya&&T<>
z$=DV`bnWO^wwVSeX7Si0RKoVKrd%76vZacK3!Ta+z=a{?1n8=K9#kMF6qNne<b7YB
zyhH95dK7JbhS!30<cE)uGtnh7qMZi8RBn*z7h0vf^}*JiHF7tW-oUx(B(ES45^;k(
z1gglUW87<exU@cmh4?X`^@cP5-=cMmvn5&|EC1wV^rFp8lW1;o$HRxUHu{A0Jk+I_
zh&GZ96FCv}!g8E6?(A4hLbyU=9pu(`sTHdXnCod99X=L)R{kf`oR#KY>nO*X)Uy9m
z3Au=I4ko8TF1FzqbMmhnk!^X4oKx)^)^%tJ%~2&=%9=1oJxrosvIPnp)6_berevJ|
zhkm&JESjd2gZVf!;ZOb)DUML`R}@mN_T>YK7hz8&W;|c)NmjQ#2D`U$5^r{_G+Rty
zaB~q3MzHT0g~7pdQh@+@7hqt26|a`qa}m0n#;Cy=E0-)mlYosUsUShU8tsx_DUXex
z?f4|7DMy*GyNGbXbx`gRJ~gBntN0ua*~xIovPIy96~(LM4hHYhN2f#mVHTPsa)M#o
z9+Eo;Ei~bX`w56hUsjq<I(G!T^T|gwTk%oB9T<|>H~R{Fd=DtNu)neJuVPNr{dJQ`
zb*R=-n*K+>V0ZjMvtA#=$Izo%*)2HE9!Maq4ai0^WD)b&Z_xSB>{}(F*|+^lnmzC>
zzG`wyXFQOKO~Q3(;ci!bkIj#m*g1xgqE0h%ZV@iH8;nG4Y3Z?r9SVldIOIu}+c}mA
z!+>t~7yuQ@duN1$TlhJ!Dv)#I%hp<z^>JXrX@Cq9n<!KkXh&BS?FrQ=%ZXd=HlNyV
zITh1ZJ75)hf^g5|Vi8kYHkCQ(V*-2%;?UIg`2ivT;ja2PTlCi)I3Vt5^9*Ce<?-;+
zq}$I<w{1M&8B|d{dni;d4rYz-RwQ>y+k<t%9xM$te>bQwmRvaSM5=dDh)YirE2`&w
z==APHqnckwo9ag<0;_c@{_~>Xe+uCbq(X}re=Zh@Kb1LnkH8-UV*K}q<L|}EHXHr$
zq=mLK^VwaT_NV>-F6{qziPO6-aeB9`6eEuQ^Ou#27mL5cI@*w*VQb_E3y{IxzXl*E
zsG|&>F+g9GPI{*mc;Vs>;vGQJ_@Tkm<=DYP^F4t}Xby@7&;%WzW&3{9?~a86f*P>P
zU8Okr^1bpX<iAbuI|ZIOaflh=3^J~ZzXAunKZQ!xa?-X?&o54ii;9<{;*(ra*p=e0
zS|TdWH>)GkB}fNiy#}&q$H%+Or4CWAY!_q>cQ|piT;$nf`20>$EgzTJ-;R0$Ho^y)
z@j6L1IDc@xmlUs-hfh^)%U<8qsKcWUdT^@=+3PS`=~~M+{H~8N?fPx8bB|*PkNu(y
zuB%}<UhQ-5qp?G~@WfbyN0h|l>Jbp31J;u_m3<Qn-A}L8WsR|=CHpMi4)A51jGTsw
zAFK0N5nMyU#HIw$34khh#lZ0Vk@an8vof%Hlr<YzM6^JUo)|PQlw)93Q}4U)qGI~M
z;xa$=K$)jVrPc&yqbLd1U3(Rq8N8?uX5yTlpk;k<^j7^n_dojkc$`X6%S^;EA-uP=
z&+(?ciVmI<WuK#m_c{7XwjJ(1N4NsF(U@)9euHO0Afl|;5gEAr0xh0g194PE#pryl
z=?-#D0KG*#`Ef3$lN9EHCGamQGlrCOP2g-4C6b=|v#P6@rXvN71buM~N~PUsoG5OE
zcB#m4D6Fo#(V02@9OX#GXgP8ky0;Ctlr}Y$494Py(>yd%unV`Tmhv1CzG-v{BuFP>
zLDlf4ITp*DlSOz;g!Su<zelv$G$-_8pz(a7Jo}7Cm6}t2R6MA<jp*%e48271d<K_{
zAbu|@wh>bZi2o`|6Y<~t(J0Rc4D|k8(3|;S`AVm~Vn@`v8=;|gsDdD8&OpemCnkM_
zm!>0mcwjUbuKmiN^HB$JTtpD#hvp_I5k%=cjv&S(#F~#ZQLxvF_U;>b(TPc(#K4HZ
za*~v8^2m$Go!MCrHDnOg6kB3#tZHQZ2n0(@8ZDlsYR91}vPZPZSMzcDQIdYcg*EL|
zSDE(Xi}+D*UygGu+ehk()Z)0oQf+W7tTZe&k>nhd{t+%nBIFHweuKk;*|cc3Ih*c1
z3G_c7oC$WL7Erl}OGdEidMehxg4xs&r9%&fe$nO|&L5&il0cI_8cn<>n_~J!H-QYP
zaz!V$ivr&dUD5G_bI{{@0`Bt?LL&mWwN%DO%CIJIBZ?C0H}6(ti1pgBh_l3Dh_(=C
zQFAp%iL-nU0%~!V?u<qAP??nwSqw^OahA|56MR2IU?A`WX{wsQohVKC&i=uO?-9gV
z2)&l#ELtjd^EgW<!cUE}oX=1<$L~x6ybj1~ahA?z_#Jeh*!!6MfZwAiP53?e-)8t7
zeVm1GhJ^;G_!&LUlG{q0Wn?kf6d7k3L}+{l1hqKJX=cUjRBQvOzM8<xC{5VDzKgIm
z`etaI6lbd6PG$Wja>kO5n}%h+s%nJlyGhk?&4Rosi13;Z(F;M8NY$5-8cp?`tE;A}
zGF|um0@PUdy{!Tir0kdQm6__eS`^nCQWRJ44jKW?W$EJ+LAF^SXfR(<Tr0U`gl>41
ziros0r76cPU^dZsbm%u|%s?8N2<?D2!#qwlV;s3sCfjQ}Sfne3HAw45o=JKLa`qxB
zxBHE#jLxL3;wx&vs~9Kl+9MjkTBRK~^d-2f3-32NjP@5DJe>CL5$&_CLuNpmd=-H{
z1C!Pup0w^cSLNKGh)D}~N+c>ihs$D3=AHA<vQ~s>6t$0jN8HDH@F=VgK_?b@X1)0i
z1rpxVnFpNR%Bp6!Vv661HVdj0hG=k;pNt0)PwEr*T7Q=FX26+n3R<9ynsp=_2u$^X
z(*d(S7ZAU^ieGpby<3Vm^8J$5C@r38ag;B`7un^J^NMisYQ-iBpjjLXR?7}{f>F3S
zUhFuG!wLj@&DL=6ol>16h@G>gX>1?li#-|rY0(L7+JDOq>1T_EERdnh%#{OGW)6*D
z<|N&P1l*DD3#(5O^_$QNkHaMjQo-{vX2|E|qWzJ@BBGiEu-TsIS0K4OSc6;T9$0r;
ze-8FS=_q6NBs8t}8t^0Bp5@7*sXApQ=|th_GMeOxoiHM6ZpXl-U{K&e)X>J}5IB`s
z|Lx?l`2<RZc2Hy6z0_DlAbZmZXz4+y%+O{-4l3gDe7C*Q?Qe<GYYAC!`ojH@oPHg@
zFsJ2GDwDINqTW#s&7?5<ZG0qVXBSn}Yn(3GLa8|$97{|5SOFQi&7nAo%DJ}y4>_j+
zci}|k_J<%%B)2z$K1j+3doz;Tm+N#l@Om!VQ0z@1z`;R>#cN_p6khj5(|VtQ&yzJ?
zkMx-HI>iPKeG1+M&mvyGfEpUFM?-@Wuh)FbynX|v1h4lOn(+F&j%ewHJ56}~h1>qc
z<c5}by_)z4UXQ_|KYUbE%#?YpjcTB%Fq-7RbX0%gZunwS7?Z<?bko?xs2tu7f<$t7
zH>hIH;b`Oe3A7SEo`)V5kNZXEaXOkd@Ob}UG#*d6&78-hJAgAkgJ)tqe~20ykEcP8
z5|10VGmrm`Qi8|bxUq=w+>ToMu*ihREpfM6;qDA9w8OdkTr=(hIfc8V&rP}e`AzoE
z!-sGrcax%Ww>^Y3lDl2|MdPmd_+14egpc3hhsE3e(Ro{drVYG3wXeq8@)_p5oe>L;
z^aQWO_zhC5TwP?|1I<aijs1ps`{S)DZ!h4+B6!=ES_)!HXr`-M;;lL#FF<DZaNZu*
z`Pd$n!@b)#=kU3p<Kd0pFF=g&@q5hX<GawbfyWp0(RjS@W^*3j(+->&1fGfU+a5JE
z9xsN*BpxR<GLKJ0DKUQYxUmQxr&CMqNsmX)$8F*9>y#qp&$GGWqVo9SnC3jr22~D^
z$G?IY$BD;JqG<z<^LlAKes8)tj~83OnM=Vl!Q(SgL*wxp=uP7BurHa%$tWdwd<!=g
z!Q(5br87y7NAehMTm*{gj@tY!E%BSzUzm-nk)J1=-(*gqrd8Hv<3vqg(;RNl*M4_3
zKETSxZ6h$V*I{22ENS@M;$d(l7_IG`HDrQOK5p{xlfk{NX>5E{=BHbmGk*-oWzPI7
zbT%06?LR;y=Kb3Wg1kAc?e=z$=sJ86n$|lFT$ZHqzWPRU-oK1pU4cCCk|Vi+vrt3h
zeI4{F@!q+Oc|Q=P1n&#Eu?XH@LoJ;}dj4p6zlKt#gpKt-kM{{td7se)8H-qKjRUz3
zi}zMEa-4Yo9O!T0{S~Kcyk9fTocFK)4vt+0UJBkPqlU)&b<nrO`;nh9?^97q@cwpg
zEQ0q1)Kc;-I`2h%jbf&}#Qf|VxX_LyhHL+VVz{wMco>4W9si)cqZ~oQkA~oF{~h3w
z2;R#7QDdbMu#7nduowfkcLH})V4lD>5Cxb+TL~Bu7t+I=F(Ww48Apnd{XzA?foLph
zIVC&`$5DMS76s9svR}v_Lxl3VViA{Ra$r$>I=a^avL)AweHDm}a6Fca=f)x)%f%@W
z`vd60FzNtmaafM2a@}JTf8`iWIr4R>J|itgvkgEusxCd@S-XXOXr74%-{CvI(Ky;>
zaa4q$=qvU)%2(nkdmEuQ^k~dmm?6aQjEu(2&^?LRGY5}d?oQ|&#gQmncK6r1w^<SY
z9q!BDNt^Q!24auNVC+ZgZM9&xptf;@1Gt^_1C*x%I^GXjP_+VclqIwsYvx81|JhFm
z!6Pj$r1mfByhdYj8@V@}yTn*r{>g6|j6u2~NpXVin2PZo?gZs%aKizN%G(PtzPDrN
z5w)~}OGY?BU!Y>s|4xHHFbbtZmBQZ%9yyjG`s%jV2j2&)6uGPqK8{p^LYC`;9$X&A
z?+O3GN*fz<AU)Jm5y~KJugWs^Rpay!{zsCQh=8$Le=lrE^*z?`eVg{3_GDw51D!9F
zN4B$<HD;9^aC&-{9k6*$a;&UZ8}-9b!5r#XrhR!EUzGkG%M?5+(5!~XB&<=?zDHv%
zig$JYY)q!EaWJe1qc7p4DB~jr(2KNF<Q)shE|ksbA1mWq=o(7v#0|J&eKYpXJv4sO
zB^GZ_Ql}NDL(l(SrENbc8$P2k(_-<Sj!m7u+$JQ0#vYu_KKFiA+A2CA2lZ-FIbeBH
zS%9G_T7Z4OpD=w}=+i-cbw!_wf->#vb3<PzQ(tQ%`m*bNsrwV%ab<OM7o)nP2wOsk
zMyvnMnbl5FG?j3H)188J-N3CsK*8u9*;v&hOTXpQZ-V~HeFJ*?B5|A2!xYg&qG=Bf
zv_f_idEVLU8`j5<{|)OyY49o>T7s9eg}kNjpq|)RBK(LL7r1jEr9QZP>+d8p?DHo5
z<ty~iCgcBpPLrMI2=5$NLa8}L*3#ulhEZ+z8;xrH&Vie-SJ59con}avr<C+R_Q2zI
zPH3~g&W1Ka(lPSz0wNbm;t;b=Qu+Z=7IJ$zZe;v>6VJJMMUfCYSE8O8v}U^MacSW_
zM*YVOWhg--<4v7DxedB)7-AutptTq*?9~oT!A=Ck{FUnh7(-*a(UqZZS*9at`p9R0
z4oy$SbP|Q8-^>c5>F)0%Xez{1q3S!+n5t)*QS}D&p;9$0*00g@5<`hFnr1<?h^DVL
z7-?#sb2v05qs&8k!Hr}DNT|zlDr~b_Y_F?z;ckppch||oSxzsK>23@mr)qv=4P|84
z-9u9JA$G|6JFuK)2ss_2%IUquI!yu5V<@Ro26zkD2-I<4KjFP}1Mp_KC0UARDQ}c6
zlIiLRAxmnqeOx`!OqS?c-;7v^c2~#%L6bWTVm_TpAfE(4upyp?f;<7apJRO3x{Ut6
zyc6^2EM*@UB7ao&y8sCS4lXJBkg`T_`q;M%qRYT_229Omz-1^QPl%OxJEsw9>ifC%
zu+E2JHrf&BSi+>F#g|bhwH@cv2@eyTzrUk7&Ohypz*$e4yYjl|`s5aLq4GDHKFKze
ziHi5D|JLw!h+%o;c=sh-Oz{4xs5#yTzta(j3S3tmxZ8w$12`j3go5!EdsMw$i2al{
zHDUdF5YXpJA@&wuLFYtmhJ^LMEVo#m;-SZ~sSG{sS{g<BLQ<1H#fYJqm$w`ROD>~y
zjww+1BrCnqE~baDrs?}bXkG5k&9k^EV@kcwMOE%-eicruDY+1Pt;24FC2hy=2OOAE
z@O$j?Nc_6D2|qneWg6hn@ybSfW_Yc{;e@u~75rGkE9;|3yl5;%2#U%#kfeu>SIysa
zyhNtT;RFHe9?~c_{U#x8IB3k7hsp*dxIQuGAOgvzGN<t2(Y1iL9(-uUM%xEP0fWcf
zM!UKN8_nHT8*PE;!Q4h`f;AQ0M*G^-MtcZ~zGWNjg=jWf{Dw#yjqe{CwTbMBB3k?^
z_d*?BZuvF3l~&iXm39SNX)m*tR#Y8kr9EE7oK~&0)E2C?5zum=fT=z4iopUipG#yz
z39=^`Z?e%2f($gTU0G+eCmJ3gxKtaB@zdr?vw2my)9IInKZ~Xv*-A5|Y36-lH2tDQ
zD=mcS98~SC82|>`_cDVG7HzH?WGE9x*F_rzT|4-VbS=97aOg^QS`isPPi!DNO~~ru
z`_Sa!EUUs&6S5lBQhN<Hhra{UHABd%W~uG*>2w856$a~sEHxof_+c@GfF#OZYqZp6
zv!tt*nvke)OU*ccwB2So6vbvq2egrP+9oP%W~Y6Ni9Xuc8f(DQd~BU-C}FCeX(B(g
zMzdE6g@7Kpz0xTP&SUOrj`Nq%?X=yuN0<F83^rIa*}uS0CMw<?bi9l2WdS;JyibZ^
zr%jNX<NaM*?6ezdG^Tthq`R4&Mngf|FT|Rg?KCwpc{_-WV#jR8{%TkPoS9lACeL{d
zb{Y>nVW&k*5{d@KI4Syfn4R`<j?qplM!Uik(3>VxVE3yK<?h_Pu+zeIw5s6I{K;ru
zu@CNC9cj<_V_L$m7X(DX@8{e|{B8mSt>dTLY4@))+G$UtJu|#|wi&MxXivdw(W*$i
z%<VKaqj(n5&nbAFYQRg_X%D`FcH3sBeR*jZ5}KVhj+!uAuqp8VRIS))%3ewG8`)_x
ze!HILPx}$uBwKWwWNVmBLatYea;n$e)KOrf`!*`0Uw6|;e<BoNSC1wvLMeaDE;d~3
z@n4dc$!5Vr-HS;R9s^6TzkwZdr1rZ5ImNfbFc|HI235x=vagJBUR8ITaMq@D73s|g
zZ$v>_ElZmEWr_~973+7wF~a(cl`UYcug4R`=3yjZ#JNl5en7Y(w26=$3)<y<y$N32
zJEh+Z7$?QioJLS~pdZz%ulQm>R|0OXQduMC#VYsm8JkDFnI9PZ)XH9FQ&?1z=<xjG
zYZG|XVg%D|RKN@--t`<6r0wskaXMw);>)u?#j+`Ga5#|#b2M&nVEJZsdZLgmec3DI
zFuqS98S<nBy(%+#Up3mLsDv-muJAwCMn_{$<Ax{2+2roravXo;mJ{Q&gNmZ%92=d6
zT;~@tH#I;;;jzo(r9_*YWk<3i{u7&cZTLG@ImC#So_dH8r&+?!#E?VQm||3kGt3^(
z6SMjHY#^5PutQA!+g<6mi1nY^zUo6~=}8nln6J-1q7`*iANni!)zF6m@~Qa@atl6m
zFX}b-p$|a(Xq9n&MmFyZvUy)vgJGC4<A{8dPwgdD)<N1Mcc(YHiuc3=^ojFpkdK?h
z^<1p<{T&97Udx!_#KVU~0T|1_!E49E3{Z4tZ$Jc_sL*HQ7~x*3{3Gh94cz&tq^|05
zmcg)ZTl4Q;Zzw|6Gvi5U-}s?WDC<{frpdWC@H8WE5u;jQWAA~rSWW0VUBA%%nF{@G
zs5##B+r8PGe(%D4rPA*sl;OBTxEK-zABJfIqdUorf|=L^q*Bn7et$6(2%}$rhz+%V
z?>id(c3*!a^h;iSyy^EEc_2*WuNZD5m3}hHsDuc^Gac+DJfB;x;o0$U@Z`J-s+~h8
zSm2ThyXvkhdXDgQ@#y&C+UCagw^;1*!b;&XJ-F}^SV&<!HY~5F8c;**T08HkjS-iz
zK$tm2qxY3%8sc3rU}0K?J`3})YHLXL={LhKm0%9{<uS;AAgoT*SHtPlSNll(bZ7Ub
zF%f#efZ<)JrZO))Z=HtYRfZzrCL{G*zf{AqKL%AKj(iYFOx~<}=rXS`9_C;vu1&~v
zfu*A1PF8U=D6KP5Rs}YEswPM-)*)F4@f464^$rERNtODFXJDHTYtus7i=z6p4}wlU
z*8pnk`H{4ih&A}M&s>DH1nX?ER$^UESFH=R2r<vAhPdm_?AM*NNE)CxvnQZIKor&{
zEt1wg1@w6a5U~?QYr>hWwfh@3ji4%lHR)|w<?kL2PJMNpHoGEm%0cHX;G{2%iU5L+
z%X~CshRdOat>SX7j!V^&NL+-hsK%Kh3)niv`~iV4&jEijm_Ho}7yP2%k~)_<XM+{K
zYY16<2USvh6I3Q_Oc#I~D-sjjR5#2TRp`CzEx_2o^fvmd)ro>sh+<r1K(RrKnA<~d
zv|tZC*j9UJhX~Y}+e4S4mFV_RYIq+C$U6ndE!ac9Mze>eE|0W_I9B_}yEGqpcx`z2
zKES79KUOUwdSi>oMxVkgqBmfbAWq8`k*8F*h<;H5fMlTfP$q0fS9SeD5%x2k&+Uw?
zIQwoopNAssA;y!syZk*d&wcQQrV0m%c%R&zapK#@Ph?!8*+WdfzhMXI@uuIcuu9D6
z_qGy9B!qHMCX9aiTyiBeE9AVFnMJhLVDLn-DW5kKAzMMCVGoE7*$Q{QuF-He{N5Oc
zhe^ZkNYr?|X*iIr%H}e7E1XfPRdfQ%s2V5?(*a;IVOsT?hH3lOFjajL%KpQaY@++4
z*hC-0p%iH|Tt{We*&JyT6=Cv?W)tl&nmlGUQH`-cGn?p<S2eV|V90{Ohi4PL5yd9@
z#oHXeis&}cKarI^OpXmUQ9A<yQEZ~GTC|DYenrEvKZaE#j;-26|Bhl4byaaR*hEjY
zXcL{SL$VOUDIkfoA4rguI6u9yO{DsdSA$N9P4thUY(MBu-oS~Ez<yv2Cu}0taAXsS
zVGSX_cv+ZD^f<EJ=ypUp8U#eJiS#yUI$ruP#8PNZ;W!qW6E>07?#`toxoi_<z8q;s
zke$~OPCrc1a9Vj`Bu;7Qyak+en`kOP&~cfGhRksJ{-IWJIaSAH)=QDNM6-!hKXEU@
zMc70?r?E}Mv=n~go2c_vY@+v3ivZ6MOwb&}sZ`g@CffR<W)o??VN4c0#bWL_5%lxN
zEQTPhTruwwad8BeIX^$=>ALbg`q06GhUtS>Kez8ghG_U_AGsfOv0W1-z+G|a2|oA5
zXVqya)zSnt5}i<m(SSwOjpVO2z)=DCj}(rs=5Rb&6$!_C=!D={^8&-6*odNAg7b0u
zot6Z&d-Pv})f{5HM;-abh)T#UhC<q&O?d6p?^kKx&FK6-e)Y!$h|cRPBk0^fA6lSu
zDiATD^9T1u;<uOJ2Yx#iN2T-mM*+tR=+Fd?zczzox&p@}0f$CsLZ9e7ntoU5e8Hed
zI#aRw;9pQEoX+CAL;J4L8ToWe;w+8_tC4-sA5;15C6>U|_o54=l#A(yHAkzW-AR?#
zf+|I}-$#8DT(j_5Eh}Vuup-+tp2sA@(*7oO4K7@XFS_m~c{hRc9pBNx+1(t@MQAo0
z&U+M|)IF!d*-3$ODZZ#{Cce9bDX8pZew*L}%f6r|u?*?(gXPG|f{(Oc{X=|L_N(9A
zQad*p>sN_JseXlC|D2ZU4>Z=#)$6<U`ae9|GQAg*T#UL$p?4<9MQcN`xm-Mp`X+L5
z9zKWDdyPWxiGWJT#iP_U<RYUja6Tm;9h`rlz6qT3@i`pML<P>*pHbobiMj@yPvT3s
zTo45nxp;yKK`uU|rz#iIk&i`@i&yYnk&6i}wUckGUnCkOxwuKM-=n4a-Hr8!==BHc
z^*?!9!9&&K)4=-r;L3AUy~9eJKZ>&@&{tv{G(WF#&fY^!m@mkWVLY`Fvq8gl8hX>?
zC88`5YVmp)ysFM~X??3OQIqw-G87Uzk98ZbA8^JsPR>b0ur*%JNx%akwm94jhg@tn
ztPs?@#+t^(<r=T!Q0G~?HyHs~+;8IZ#woY8;M_}25?V?S$;GxBFL6mkF5CEV#+FzH
zM0g69GSIm)#Jck1rChsm7DxRJpZM5WZi2|InOZHL;&*GVO({<g@~f)f<CX7%7UE*9
z!uF1(?dakS988nb`yfH5aV`Kw(v!4r;1|H66iRYd{Lrj~LVM-OP3iHDr8R$}yE{7J
zg^q=w#E8KNxpA&fr7yITVr)m`l>@(!wA|_G2G110NJm6l#F^l;S<dHWI3+0IK<%L6
zEZfj5d*KO=rPdKr7VwnYQFqRMTHC-iEQctvExYV#s|&kQ<7o{u&qP0>4<+3(F0n%@
z<aE#Xl$hCN4}FgB;H0w;monnO7m*cqOb1&)NQGkDvnm55N2#0A^5bR?#N{5yo1Ofl
z_gwBr%HPqH+YcGGu>sx#F|$`%(?{U+6UxrnQYAI0OJc06+;Qq<AauF-s-K^+uC}^t
z)aX{J#2$J*Qf|F=(d7Ufn!z$b&Q3^P<xQ4j980^<#sSh3`HfAvgPl0V=INN8!CmS-
zhV{2Y?Ju56y{ngEInsHVV5GO-Laaj2RXo^Ct;a<*T<5Y0ly?gO+>(GkF3f5mpVO6B
ziE4u1xVP1&TqtArWi=s2>sXqOV`=IgF&O5QA#nhBq00wnQTD_Te{kk3QOF>Rk|O)c
zcrT%|PZ;06iHVdt7LEs6VNH=pz3c#M)%=T`IF{7P{iN~^C~N|9QVlsPdJ9Du`20yy
zeFTTGFP&a=@KXG)j#VB@Zrgkuj^j&nZtI4`k4yRZ8x6z($o$*X=)1gWNLG{gTWKQW
zPNOVJANh8_r4Fi%g4da`7$y|broc9aYMhiAhXE^P#`C`kWvdf$VzsO~k<X$|ujIJ6
zfK@c2#m||Qey5!l9)4$>c*KiG0zK45E<+;%KLzI_hiBW}#{eEb8WHelHZf7h=Srk-
z!A)SZHbo@$<9!B3{8g;nD5uI6tv{#<^|xf@H&x#p$viT_sQpzPazyjUWyY2aI{#?q
zk&WN*Oai!Q=nx%fK<3-&J7yC6t?*jt#rC*W?=a^P%oR1tOmd=fS!z~1CJtzI$Fk3*
z$vl-f2lG(S`9O10)VT!7;ZK4h2P`6?zfkop%_W_2uM%C;8abN?e8c7vk!L?iyVQoS
z^XRW!Y154^5#Z@comfI&M@%J{XF}T|>DHO^(PBoSIE9#n!{!vq`Iovc%}aC2Wj6T|
zTotwPfOnwW5&8#H3SWQFO=S4Zpr-QeC`)q+t{f2Q|1hUaj!XVItp<tYYoP6ncP^~O
zzC!Dl8@F4pvQZant&{DcXNcCyn$OU8ynIQ5+BYUJ$Fi=x*^HnVOgZ^8%G~yLt@f?@
zFXEB2OY1v6yl+LWz~?`Io>4C@)8`rJiYW68vh}wYd^>`<X7625=bE!B%;uV9<@k!3
z=$40%Xs&^oB*vR9Ei3l6?qNf00A`k^M%?d|HsX-?+p-{y1{#Nu1C#lTbUS&|4u7t(
z0B249MI(nl*M#P(y4^6>92q<_(9}`GbA<+vHrEg|%3NbDGt4zh&J3Gt*d?h<!~X$k
zbR8#Xqs}$&E5C)!HO>7Td%nZEd*dwhNB)>hz;Fcqn1Lmx>)91(R@EnBmAzvTI>PF;
z@j-Px+Y43c%X)lKY(G#W3Y^JD31<cBo2<J}Y6j;p1<oNFoOe>!fU~a(C!iGTP@<r+
z?mmkOVYKDYQ(brOJwsb}pO5d#y8Fuo3chCTd{JzuZxM~sy89P=SL#36QvD~4^{eR*
z;SYLSuYaXlU(wl-{;#;5kc)TjL{*ZDX(Shi?~mz@{!Hk-2+fAe#R7%ib^lQ1q7y+4
zdN0M7mgIur?0S@N-h}!la2~uP63$)N<Uvp+X>eXcUE@m^6;6$x1eqciCsHBE#rgD9
z<zm}unp~WQ?+RaQABdC-LpvV=Agz9Y{t$fq0<TK_c`eniFxFqJ*MCB<pP|;*Y}0VR
zXeO}oV_P`>1I1$LNtks5Vf-<bZBZYc)nzMemk6T!ygP`NcNGyjJJcx1vW4gapZ)l(
z))ngHm8Zoo_usFI&1RILvUBi7*q?`oM>hI8W_YZ)Jq(ZC{}Qk@;d3}1-zwr?U!~&F
zS;1o&zC^4^h{#0p*Qt`~v%2q8)nBHrNvK$TP(~q9Km2>4_B{%HD$V&k2lf0hb!|}x
zt@HWOnPK$lO$dQ^U*U5&eNKB;{PMzmDt$sILuDVrmlpXP1&?Jcug3_FP2Mm(u27Uj
z&t`b!KO><2`d$@}-U=QY@FjxJ1RU`>i7KgleqOuRN989Ks}KH$kr2*j@qN4Y9d<zK
zCJ~8QjTIh@g|AUj_*7f^4f;&n15^izAb4f~TMeF`&EY|@`d~H+MZm+~2Wj7%^_kfM
zJci#icx(XyPou{G&)v9dC%j)ORv&y9h0MM`t$l9>Ph|`67=F{>$yDIUHNvyMXCypS
ztUh?Q*00J(@x7b&y%{_UTY$&#n+DGm1)l0c1AVS<1`idh4?c!M;q(#T%e3!kH=5sl
z={EAaF9&>OM!&nfjD`i@tF=cC_q$VBlBJYo2EY49JtApE#p;8dQAohXx@r>qrM0f9
zR)1`tqRB8)Vi)2DK)MwRON*iDHb>dzG3YmTE?pl;R}N#25xyt{!=2Tby)bR<T7mxI
z)JcMEE!9%V?I`Ih*@4Yj<i(@)X&i3w*nv&{67Jd^hJA3j!WH)~<7z|t>jJ<kxtGW#
z)t8nvA^Cf$1@|6qEo+RyC5LIN9C!bt9deW*Pxv(ii+f4xCX_7O-42%_R@GW8P8pXX
zewv=P@%Eq6a;iNUxQ;g&H!N1K`W{R1HLJeCzso(nVscQgpvoVM2)f0RJ~V&LZ9m7j
zm!Dm-T+Ufe^}1X_zt_gbS<=%EdiOJQYkVb**ygMuk*lIFyVqbsg)e4_vH}luEBc*M
zi3Hx-1<Z1m;Pz;=P|@V+GT&NWJ=->H4q~>Un5xw3N>?1Nax%0UkIO%{F=-O0f!nA7
z97h5{&*)BcSuPhR09CrST?Zw8Tr*IXtDscgE<owWpe&cN<9$e>uGdY-MZR?IFo`;}
za)(LO;j8h~VYOVG#2q#mD~)Z|VYS*}Po=|UA;P^{%1%T@x((G<>FT4r+ACdWLCBIw
z$o};NgbbHG_f&=KAXuUZ*>1e5J>hAavNBxA-lZ&y?lmN34_Pr5SNmLjCHH&s`O}aj
z%s0Ew{Pe_OxJY~fn!yFI9yxyvg@E3JAKs1-l5i%|C5DM*HCfVR)SF86t~>=oH2)G*
z^^8Tefnn9iUqd3m)qL0Oy#iix@)b#|f(3tIG?6fXcsUOsrC2TbkdPG>Nu-A3?;v(t
zHobESp;z+W&(DNbz0*g14;JI6z}}CLJZ?Asp%$*dI4CPwV!^#fxFQp*Id~F%SWX|@
z%c(?=KUC9){Ax-+wG|%%yOF1lemxcS|3CJ=20p6d>N_915Oj4TM2!+Ot<i#@4=5^;
zs39RC0s#a9RE=V#DQ*2g*j20sf}3b=uB)k9OVwHstf**F5m6}yh}obBfkxy@37G0#
z7d1)*1U2vfKXdQw-Q9#l>+`&QpSSt_viIEiIOoinGc#vq&dd#cfs9(-GUMz|P#Jm4
z%)49zc`HFUE;JvP)GbE0#r|T+JxAIiqs6yW(87Z7qLmlpEHm~7?RbJX`_vZtGSm`!
zGqleb2?Y(UG6}va69&&?xdtKz^Ln%2b-`mnj*|`Ogz)(~@?x%P*I`vVkewn!QspB}
zKGON9%g(_6nfRZE5%#|cr|Rd)U)deg;-CV#xJb?;u4S8b0&c3~mn!7zH1Ud0J<8W2
zyi%M`-e?;dMk5fs9vyG*NW88{yx%4RuVtzf0C}hQ-bM}^pR2^H;`2E>zC$+%eC8N{
z?{?e`!zhl!z@2QN-~K6T80Z}y29l$OfzeUJz$vhvwRLQuw>U5i;1hIlVuOdxhr_@w
z|Lj&ASkWfA=C$!=KX=7qq(g^IeI7t2(VVTJU>>-#4+Zy{LqV<>3Rc;M0`%Qo9}AH2
z`-}y1Fj9#QIMLjyLP=uBf>l<3*nK9Xm$wb&e2oRnJnXJG6MVB98k3~Y;jrKq!$J=^
zEI3LyF61ZsiyE<B&CM{%Dh0A?v}Bb!uWh)H)vthP^InQ7-c3=}=yT-g&|qfeXqytt
zoa(GUxsJ>=0P(BDnEAE4;ubQ8p?FS;zi5MvgVf1--Uf?<bc=)Kii5ewlY?44KOLi#
zzqH=QL27uoDB{3`J1E6f(d^Zx3l8cj9>D>`6UXXAiZN-xk%kf^m1y}HChP)y7Bn-1
zntA;nqsETAp&?@I@XWQ38)Z@BhL7Kk6k7QyhK+?BE%aXgF?~5O_zN=d;QeFVtHp-q
zLJkUgFJIjZbo_`uH8MJK47d?vfH45dXZ#F5?1vwO68lP5iEeup1J1+ua(tz>Zu=)9
zpq44*V3CXf<7eoYtt%#P)JKTxEGMHEa^JrOH2irV2@WB_7hn3WE%+S50(rG4K0bU{
z!$;^Y(G@Q@&TVF&y*x5D2#47=bpKD9{ngX+aK%X8svvG*Y=h*)-m!T*=9R-Rl-*;o
zl3`<IuG^pYPm7I386Yz$HFyI#iNugf3=Jkb&t7R~C%7HAsfNC^un)0eci-<71#Pw{
z3<HJWbqF&tT_-UG9|npjihs=p#Z{q4jF+jE5c+XwAHgL^Xe>fVXr4tdx;P(N#2U|F
zanggQ#}?;uB5$xT;Ce|_H*<QTLDP;s9Lze>))xE?2>SCrws0oB2%P!21hz(78|;k)
zQCzoN2E?xh2P2n-{Y)En_x&HCcKmsJEqnvPV{l7sjV&RbP1YVE=ceH?x9NM2xg`M%
zx^ehD3*&FuV(OOM_l_CQe?;7BtR&8|*9FyxVR&DUh~e#h@v4Tmjd<lSd|HWZ7=9Ch
zT+{CqcXcH0d6Bqh61O!J|NWPk-E{?LRwT}IB5|H($NB3pPB|}}z5^YQbTl>(MLoWe
z^THO$#%G@w&UzZ%pPUzND~+5NGA$*txVvp$_)=2zypYM(2j?P@oEOH_anjyso2^|>
zgh004Y!ezpBd;&DCy+frJ_gFiVEGs#A6fE|Eg!?>qd-1J%f~qRm?$4p<l}1jm?|IB
z<YT&gz`h~b8S>$gkJ<8Zr+Ac=@qxcUS-AuNRVwIS1yw8PAqCA>&|?Z(prFMHTB4w(
z3R<S1<qBG<pj8U0F`>G$T0%A-fXMd!pZbx43Y7g@)Q{?GSTAgU_g-h~k<Q0AZX(x)
zm~4IUS4h-e_*fMl(=Jp0(=J8D|C`kNf9eOd5h(k&?Kf4sWV>OzY%R96%SZ8Pn#lIY
zWb1>Qkf^=zS5&yd+t<X~w9tk(HwG`0VGSLLB;F48j0(16)Kz<fNz`=Oj(n2&#1Ci=
z6aZJJE(V?N9bJQw6vzb;+g{;c-v6$R`$CT*I&u$b*d7`4ORu%}@)XiA?F5AUE9L4B
znm<~(?!Kzsas{x&PF~j`I<j29Zjv#6k5#TsNW-*uAVii+)i;IDsu;{nmUTFx&8k<m
z7a{7~jYN@p#O&*X2X|ZH9q2*j(e>a6@&^(te;hrSbY;8p`Xgvi1`i@SQeK((G6rLc
zXIb+43(_!T6he-w2c4Abj32XHbAH}#x!yn<BCoF_I<j2X?UgYVGp%w3kcMezAtXu<
zD17R{0A{lEVAQwKdcb7sgWZuRQV(SK=V(z!l~?`I^<Y2pV=tL{(3xvV=l#JL7})Lf
z2ltz;UPpAKye{~slvmL$mc0ImG?Z5^LjIL<_5Lx-b?fAI%k_%c>R&>1WVwp5kit@w
z&ale$2GTI(w+M;S0}7vd(3hDkJ;*&0tp`lDKA4C^k$ND*LugS)l~)pGhDR9}K1cpQ
zV$z2{iXP-oYFA#m+3J0Wj+ED+kEOf{Z?@!hKhjWMLlN??l<VXlvs^b7wOg*2%vS#_
zq9e=o^N(b?yf<0pdIf1%uImvJr3Vx~^&o?pEIk<db+jHZ+4^7`T27=M$ncL<xVc7O
znp8I;mkabWur_I2eOJ^1{dTUP%6;060MU9~rpb_0_Bu2Mrh~OlI~$*1l>4+d!<@kC
z{9rD)R*pD9ZPktFX@cq6hyi|lv`uava$#0&<c@H$jJ2DvzICljE3V<&O@|;9Y*-f8
zjPf06^USrc+^@y5F*kAFBcpjMv2tHr;|nEd#kE*9&DM)+`~Bmnd$_B(hl^}6>-MYq
zV;iq<mDt104e#OZz#c9ctM%i1ST_D+m&WDBDcB!-B{oj+{2WUy*cH~s;#2Rgik<E3
z;f_f57h8L{lnU4C#UAd6R3dnu2moRg@~VRr$twNYRKbe1hbuD0vLd$-fT8y1l9g$K
zl~vl<6o0X`hs(UF*fbV<xFga@@Df2VodiEQK!P>;wdsPOwTCM*#cmqQZ2@4IU=rN_
z4$EGnjZO0xZ?MTN4V%UrxM@71F9~j7GJqg>yC7JrU)xtJUgj^Zw`U6P0^}{j5+*jx
zYsDrBFzlToOL&(cSgVb-c8W8!5d(pPO4(N%G1%HP{>@xyJkGuKvNnymk#B1J-2m+x
zAH8XOH$NLCJQMDUN7D`r(Mp%=eQrQQ^51c6RW`SMhhW?HY}~FRcJ$>|F*jn!MOx%~
z|3z3Hu4dD}+JiOM4X++cKCoZ=0rq#_HO_b*;)hi3M^iAjZlOuo4nFrQ28d08;#Cx3
z9}yrn1+Y4dEG`isHU%K26x^lQicN){Fer_8o<jj6*ZLocd=KP_g`<!UsI|PMM*j_{
zpuDA#iNsgW%%I>T?&Q8^CjaJbkvuqzf$x)>jZoasJTv-z86AnuBpEyod4f0L2hBQ|
z!<}Qv!V;M&bYJM+;AKpMn<(0hlYrMafvsYlaVk1RBsNa_H9JwPsm9Eq3(!f%?ibf(
zpMd?~o`^{iom_URe5A=ox_o5FM_>6EARhzeV=y0e*|{C9YyS_?4bLS|&ayjl<2+fm
zedi-zLbJmA&illxTJU~fyk=P2&>Qh8WH}a3Yt(rYfe~xfELRMj2L&dzzg;d~6&<g5
zRdh=5s_?%srYrc*kHnu5iT}h%{N3#MuQ2gPkAWVJfm812`WUz%Y7F#zgHnhd;a?vE
zYwFQ<)EM}iFM#>~-7#>~1lcWz0w~nKG6p_F1ab_V+(MCj?=i4uykupnV5QSBFjEi|
zW8g>dBKiSi;8>I3=XET5r(<9}lgTmAD+qq?G4O*cWC`a8f}M|nC2%tPp=01(>}!AY
zF>uO_?Tmq^KLt`4LUc5Rh%xZ&&!Wb_Q$&Dm3``OMwlVPFrx-4d$6#u#|LgZ11Aq1=
zDyZvY;GtTP+%^Wj1;tfk;C31P{l>t>GE>wT*b{h-<Jc<J87Hy7!x(t#FFG0nr~F?U
z1OJEUsxgrCV#cO}p@=ci5U*-%+Adzz*z^`&g)9s3w8p?S2#gp5+of~Az@)~&GV!YD
z+#+5TonPQp;eT#KSMdK=B>wbB{3k@>Pq5=JH1Ufu@CMvbU6(&z`0H{EoCq5<!e94~
z;d$V_QS-o>s4;K`>`mzs<LL$=Q*zSrrl-yECdGu)wfuqf<qG>JCDU)!@(xnIT<bto
zD_TbLbt*m{q~$HqOP5Kv-gz*&v^58}`}QObEnMclr`enlUQFtFOX$nBOt|$fw|u#l
zn|{4WPQTt|^y^(F{CbxQzuu*s6Cz`HPMBG={5JUYF702sR4-hXS-3RDub18$%jryO
z^X0P5i<Zl2$`Z?$Yv^bQIMSEPPZ1X`p)Xgy3+7i>e7WFBrF^;4EKjNgAd<dZ7X&G)
zW%`^n!CZtdmu(JZGPlfP?zAj27vanG9hoa#rp-x>^5wz|RrzvdSR9;;1pvvxO9nYu
zuIF?15ar7io~ITqmA+id;SeP*e12>wIf(G(x*1a}dO(j!_rv)%tS@QMms(3-23Q>I
zRo-NS$U#8Im2r7XWj4R?3B&{}Tt9_Ng)0`WnD)y_Q*XgQjenf!&bHZIF$gHNIemeH
z3Z0?l4>rNRTK*8rkF57C5e;Y7ucQyzRQohC+K22ibk+2097!3U$mye=<g3dPK4MoM
zYn|)H$k%qo0Nb1qiWp46q|xZU0Ns89emFSZgx29JT_Rk-mT-c2+{X-9CcMU$F~v6@
zF+jKjV^)d=6+!@f2gRo}cLO#KU<eu17FuSx4h@cQ9lA}pA}QCQufF@XEqFb`Fz75~
z2ZKT9$*bT39O=1rO>d0oH5SHEHjHzADqNkG!PTh`W_g3)eYPA;8WYoHd<4(J^v>q`
zbetc<DP5nI!S!ihtn1TPr-IPap_LY?XumAwW|jrU^+{>L&9QDzFA#_F%lfsAS@-=|
z(6IZ=&AAtzQ+W&%TBYSJHhRJBO3zyyywT=;b+Mj<PhGU(_%;3RUPiU~@hLZmh!ybS
zw-DjNSog5A$%Y;&NUdnG(G%f%(c;kZj>@>l^6Q!c%=)AO!7pOV_|7RTqi}#*Y)n00
zu&iVsd;#2q-xlG`q~)$)e;Xl@W>kXTJPMeFyYs$5X&Mk_;&w>f!DoOZ^lV2gD|fjk
zkzJpZ5nL5pwWkV}h2vhNP>eXl1ZQwDU^u84J)rZ313%RFtMLr>MR2e`5|~U~|9WJB
zEoFNZf(qV_#27h(d%mXgQhVzM)7!P3;Mvww__tyCAn*eh4+7aksP%Q(<2zbI_#dRL
zY$(z!yJLLhI>JkPp$NID)=I%*@tSVE{z1I<wO;SWE4zlRm*Q#JP^Acru%X(eGfH4m
zbh5;&qH~UTRdi0ntHS?l5bGR&Xir2rc8OPo{~htF@UO<J!r#NhA8kY3NgFEpw-G~u
z+jkTjswv8b8n6#kgj?|sv!UAchqu{KX)MM66E;-XNXUz}p$=kEuwxtQ2l>OdV?%wh
zo1$vphKglQ*-$&qBXeD|q3r(f?buK^3l7@1p~6;Nj14tKaL_dy3i@(18|u>!AcOX8
zsIUlPY^e7JQ3T)LhI;Q;5e=tHHq;SVdH;$HweDez7_0Ha5#wyMjtCoS{rgci)JhRx
zv!R|sfMr8H3fOoNqfVD?s29Ep+fc>qz|c`%H$KLOI<+T;>>tC1TJJl$4fVnaAk-Bb
z>QHNkHq?#8(KQ?DVz3isLv1?yd)iPpfs^)ZsE?AtMmsjtMud0GhDs4-Y}ba;h}^QF
z(j?1atLa~`p%(0qw4rMHNpW=1hPn>fJFua)y2)~THq<J_*legbsl_$;VT(vb2M}XJ
zoz6oDd5cwnzo!i~`~RX1^*=~k*-)ezV?*7%J;L^wDqfZCafNtQwnq+L*)=?H0iKo(
zm5IOz8>d}5-32CPLmk>ivWiYnyec|7@T%~i31Xe&e@b9b_~%FB*CO%%&W`_0?3vl{
z>xr-!Q_L$&Q{)wDC4pQVBht2+x3DEcBiqLJ4H?2VSMsfdd?_6d5Gw9_gH)s+1e2`~
zjwRK|{Pkx3!S?(+-?P$Les@f^KIo3kpVTbrx1MjK|7c8pCWHSc5=GH3F!L|B=f5f@
zKa;Hw-mmft+mqjz(~Huoie3GRQZYL|lT&Bkp>%ioGXhBV^ci%3U$`txt=zW%8EtdF
zFA}{e`xjg8DCTZBE;BWLJ{29~tvBdn97FSgv)S#dkB72IACSKTv@c~u?T9n~Ei^5$
zA;7HV4<LQn?6f#{`4;d|RWK6Q?pAdlQtv%iFHEk)Rj-A~tC1v5+a!*WRg*<;ine+G
zVw2P0m6)@YRF}<3i}RFJjVTyX?|G9i?s6PZiK`k@IHcZP@e`!+9gcV3mkL0}zRlRX
z|A1do92-Amjk{u@`PN;~t{M?vIZRv-2p$p;1s>oeD)!)6j&~<Q4&6A<?9WK<*r!&m
z5&WZQ!C8VYXd=@-t<s)jPm5$OB;%Rx!6Mx}m2RLt9c4nC15Nfl=U3%>$#DVr30{s+
zGygD^f40icj4ZdA<TRCJN;ru(rD{w(5{8~JcKFe)2dPz<*9zUq(hHL)_dHxO+oTt#
z>fSWmI@oW&KFp>@2Z79YDA|(}$lC=Fi!;r9aB<50$`)(k@Jx7T_Q(A|xL!H0DKT#s
zE)DiOuElMnzS=AvZx0TJo1?i@rWI||3LA}2im_LPI~)od^~-P2hdDGjyyP_x9R}6g
z=JwqV<<JXv>8^QNVKd!)rX#?vfDvnHE(m#>(L!T2ubI~1Wk{{9(V4>`YQ}|H>{~(_
zg-y5~vScWrqHW%BC0ci1AOU5gBA{%@7Z*GoQf1xYnrI|9mnKQ!Cb}aQ<EG|qEIY1-
zcHCwwV>-&H7dGqhN_PZb?Gg6eqY?^*uo9BHOjOu5cLkQ0+I-(Zw_ziN(TeJiNIfip
z1^Jm-F0FfsJ}jX`8<F4(I8ZFC$Ff)~U64wp$O<J9QV}!-7I($TND^9ZJg-An{{F7i
zm6h2+bUgAdn#mJ*WpkdZsyKPjdS7V@&f%}oMmhosmFS$%e@`jj>CLXoam594l0g!W
z6h5?^RR5KI2GzU@znM5~_x@+<a?;}bkKm52xDtekkh}Vj$*XV`0`kX4<`1oo#VObd
zJt_NAldt5e;uP|g`tQOQ#wdCIj`FeYe}_Vr-QkM!xNU1FQ#V5}7{it!QjB5zSioc%
z$jjyCBiuZeH!L3;d-A+s4DMm=;dT%Wtp?&8O9Jv@vf*KzpXN!NlfW>)Lp*3_=)~&E
z;inzv&yCNWccct8<1QbJ3L=jyq35{w+Pk|h-xW7#XEnnz&;gWa<=5PYl*qt(_I_Lv
zxcffji5Ja~Eel<haS}GgOSHS6M+D-l@kkKy07U$OD@6P<8UFwt4iQgHX8x@*{zV!8
z5FSY)KFN$<A>(<f9QYr`1NT9o8=yWi|HCqVg^Zt%N4khlH{)-W@hfHgBY0$s_-r$N
zl8k>%#y^HfnTRhl<1du)t7QD+c;FfY&=;!D^2>ORJm7Bu;}b+YAo6!$oG5>djDLdh
z4iOIli1N#Lx<4ZSV#dqQ#z6p#Um@dbW&B?mpDgl20HXXdzD~w3VSKuXPnYqx%J_O2
z{|w`^MSQl5pCseolJQF!Unb(qWc-CPegh(K0r*wdtY25+t0{9=Y{J?q6ed3S766;w
z7kPtSJ=+P+sbcDJ!r4HWi`#@;LhG(UHfaZjb)R{8F1bd0y@Yv<Mg79LES*0CS>ekr
z%{;cIkw9&>ru{kGCXZ-Of`?pjQ^yy;rg9p+$dQHgwRdb$;{HdZHIY6pkcRmL3S0XR
z<5al9L9%H+9mX}@!sXkSs-HNcsUWUmizkH=U(%EphcPva*BCTRJJPnWFCcWnyeoZW
z>S%<1cQSZ%GMKLc=Wr9U?s}G~wsn|F$c1$Cl7P4WlFPikeTSU49uKMu%7Opv`=Nx@
zZ5b7fc&mQ82IHpp196uPFGXh);=r+zO^;7@0erG4^Ld&1WYfjFWtRw>w%Ap6Np}1Q
zbR#LCM#z}nD3*FERw6mZw1!_`zw8nrkT%ayBw~Ou^p{8YxwHOwCmG{CR#RNuHsP|I
z)c2ENqOmrbS4<Ue#TW-0XwAn7FrMQN=}ELTe8>nl-6V6H&mqMQ>jaX&kg9p9ByzSz
zWTqgJY7&`l5@|At9Kt|q+1m>Rzct=oR-ryep@Qc^aNKj2MMy_ohIZqQXS24wr?%xf
z25r$&gZPXbzH4w5Ss0pqgf<HGfMPWdb#Ffa6GRk5<VBWzWYN}H)cy`@oZa=em%)%(
z$Gsb%YCt9i8VtmH<Hqn^E?Ky%njS)V$uz50gA(Uy?((G|>L1sJ?-1Y$>ybl?n%s9i
z%}A4Fcg2lJfLv|a_`XDwKaB=?T;jD3{rrjpz=KFr67C94E%2Q`Vw>bBaF+*UPAyR%
zi`wuM;)3i!2SO>3#|T%zkxE2}$<N$4>pXwj%i=X96*cpzew+~QdUwU8M3LhV`)-Z`
zZymlVkpctI5n5&1qw9P%i8MY(!0g-x`&jJ$@8Xu+k@b+!I&5=6iB8aOgWRii*Tb6Y
z!JN#sGr!8rYrYlcUo+~8N)nfyx%ReJ@TI|dx=7@I9r+;=@N<%Wn`_W|t$3H7cAu73
zIV^MY%&+v~U71DAx1InqjP+ej9Q0Ce1x{^pl6I{_8{yK6w?X@GMbkFcMm`Z1Hc~Gi
zrvX>gNHzyD)Dm|2gNU#+0YdlHIGA%o>yftL97ORBsSAW`4tQ^0H~^hM_9FgjiIG+4
zy99}YI3UwjO>EGdHh&ILX+;gj!{0)+iW-8?AsTgoZ<+K8;`R*ct(7)kki8KJ3)~f%
zh%?=;9l-&3u^5CdlDLtFblF;Ba5gm*>^_I7n=u6~DTw`95%MTQ@);73{7j=Ege{Zm
zdQLrJheM%rJf|?O-z8`^`>`3Ff*eeciU3A9HiY$=cdzqX)G*??-q5!IpQ0X#nw^O6
zJ?oCU5HwQ5C*E*TeJKnkaoc*Z1zUrbti3%W<QICw)&{MD-SCYlSZEOf_OY8xtg`0(
zV%`NF_@N5@w2GbH^Fmit7qAI|hw1uclZR{QG{TE}(DAYaH-Q6Ror5_%KOy7Zw=HG&
zo)XE>izU_8?Y+?gZ#*LTy5HjKw^{^W_|^#<IxKuGA&|q~6H7%&T24{`20i{vn|w`E
z0(sg}hiD|t;kPN!POm^Cbyv6LIM_0WbDDq#m?hii1c#n-v6eCftzwVa?mh2X?D^J;
zz3|h%<n=L0dI6jEOv-i5o&@?a{MsUf4_}bbI1oBMf{shkafRuqp`kH~(92)g39T0W
zE_)Rt4urHiihM?LpqnUhzK}v7pCc4LwkpMt&+!azVrrx3ChJ2gaLJ&KJ_j=#HkvP=
z$E5XOQ8ODg+Uk-wffpwMAdzGppBhZo&%>TdVKde`ka@O)xeMFL4Pne+XG0v*h$CNo
zs|QHXsRGMPhaF84(RAwsO&@^<Q*6OYc9KAoWJiO`q}=6ipnTC~v2(MvmfW~3G%kV0
zWk-{YJ&`+)hT=hig33mzWG4$0$#xVeK#_Sg6ypSn6bnU)K#^jium)VJ>I4`7W=pE=
zgNk-zfI~mA4;={miIySao)gY}()r0Jn4kEvXA+(N1G%!Ua~*M$VL{}&vL}szWT-P0
z1o;P$k^IZ{9ZK`!GoQ&BhzmIR8+QddfP~XwC+Tq|i}(hE%*yE;prC;Y8myop7KFoB
zs8|m6QW4SNk{sG`I?-R>B6`;(zEIhDDIyDY(V>W5w+85p$!AJDd|}!GGwrcV>nw+v
zC@4A00P*s=fU^>ipys^SgzB8tgaXcoRMdP0J*J=qCRFEKOsLNJq<l2<5pX^>%Az$N
zPyw$rb}j%!%H+%}AtQ||@+H@NVI1!kWeJN83a%l3lWRcr_|zKGB$ctokamihwx3A*
zkV;z(r~uc)Gc94Jooc52_5ktjf{Y~IZGgnb5r;#67BxxPB{7t_#+kVSB3JoXD_0qy
z0?axfLqMhsO$ah1ROkG?d_2GhBx*(nobwg*n1U84Xt9EpC}^pImMLht3Dr5*5ehg5
zLb|d{0|1Fj0i1&YkylDWaEUUR(q|&$<3HmJDB}3S^76zWrT^Ynlu|QtN{mf_rik(y
zB!<6$bDs&-Ia>(TIlqvPFZl>KTg~Wz^N@nRQBd4C3yniTNeXf)C|N-%CRFD<gHXVk
z1)e2$LjZ|G;?8V9<h7mhGLdm`fh;dySYDnEVR=7pWqBK+gA!u{pnBZUOFV>`w%XK%
z*G1Z9m9`1cAu}yurk!u5y<eoQg=4P7TLUNwr+Nd<dOGV0Ic`u;gMu0rv`s;~6x5`k
zW(64v+NYov1+^;Zkb=HZP}~@c7l(q96y#D+vVu|+l&YXK1*Iz}LqUBNG(bTE6*O2u
zLll&yplk&VS5Se1Mk{EXf+i|xih{0I&{PFYQ_yq;-JqZu3i2puwu0_dP?-tUIm-!A
zX+(8H5m@2q%v+!r#%dVYjN=QHq|8*l-+W2sTaHkvB+CHt)^DaIEYg|^b*V^OtJ2m0
z;uY3ROPFaZ&9pt47ViQpZf!=i@xUdLKfW+-hMD%GFCx-rPe9t6J`-U{d|_JNs>sIj
zT4dS{=qrscF%BY45?`2hw3+rkrgb_X1zEN@K;kAiXOdDsmkHH5lL-Z!DJm*eL1_v~
zH=z;?!vX|wmH;pu@fmO~LFpvD#egcs0JIbksgpa=@EjS8G%|7}=X_xtZ#88p8#(kk
z?^T0JC7>j8P$A5;SDR^<h_sKXwDSQ~nrR6$?KCs(og%FPIY|zi0g11$t~&_>&^{@@
zB!)8AL^D^u$Tb{2pUjmFXu9Z-3(S5o;2dp2b<S~wAeQkW1i(ZA1e{aMBmw8u3Yw~*
zX$qRIpc@o4LqQ$|%{HMr=L3WS&H{9-lEdME#7z{=(SXP=$`d^ZF_H0$zsPpM7nXUp
z*)GO^&Kg*ZoD$;#Kw_8QxrD?-=eg8`>YU36p{Os45CF>s5OA(ElLVZr6jY<2S_RcB
zXoG?p6x67oZ6;Lb{E`ra3%(_X;{b_U7o1Z7k>7U8%tXe_CuEuV!ZOpnkXm;Q+njS3
zbWvj52B^tw--Ma=AyX&L6KVIUv<9GL?C6jtVWxe|OxsPQU5xI@lqDc>E0}YM*?9$=
zOBJ+CLCY1iQbDT}RHL9;1=TBPgMu0q)Tp3s3fiThCIvMs$WYKe1+^%sRY8Xo^o@ez
zl)d3lP?CaN3QAT`ih@!Vl%}9`1!X9xuYv|BXrO`yD`<#<vJ{l9py3KCP|#=vjZ@G>
z1x-=V)e4$wLUqn*gs2Fjx}gXQAQTKl4l3W@|0b1>FI19pQ~CCUsC=uGLahXpWGWwF
zk=9hGmqpqQDs4R=e!GA)2{Y}zW?GGD@h*6AWK<&B*gQn?#}~$V%(TTwtIxu6p!~|f
z<G8If;JBMJ2N^2vw5T*gQAimoPWjH1p-n231FUhi4CO#9)3Sp%@?|Io1d|%m4wRwn
ztjx3wJynLXIqO%EGs??wh)^Hp>Z?uXZb**jI?hS&I9qIpvt?uRKr3o7UOs`dRICKH
zgmxl3jn7as09xH5gwu`C7KF@)G(zhEu>TL$0N}6`dIbP`$I$a6aQv%W+`*c<nAc(n
zIF8HlIQuT<wb^oBn=R+H**|bzdp5BAH_mJIJwhX5=C#)bBQ!<KYv*EIq*g`GYtLue
zf7^NO?H5U|S)<f%YhGJw2(Fc>z`1Nk^V%y!+OExO&lG9fnb+QM{88q$pMNa4L5q>Y
zLK&d{4f9&}{j!IPp4Ya0#PT+)^0Ke^-!QK|{Q+6t=y|PMl(%d1+7JIJWCMMbx^T34
z?JFW}EqYIxmc8qL=CzhlI#3xPgB3JHL0JmQR?u(-6)0%5g2pLmqJpL<=xPN`RnRmA
zO;^wj3YwuHkAh|^=uQQdnNTP5+K;e%#SS`pUi-j@RH&}aYfD7hTBUqPo7Y~<v|)2%
zHZmEnoh!RrzA(<3*B&34R?KT3-YxRS%xm}Vjle7BwWng}X4#_WwJVtR-+Ep<da&d?
zdS3ethu$vEYa2w`uFY!~i?r>`YeU_SGOxW!<oe$^udS+<?IL<!`@1IA!2iy9?IYN*
zW_yXA*WS%G*Ts45l_G7|=C$XFw2RSE$$^OG_<!cL)<E?C*}V3j=IVa*ytc>tRKBjw
zYv13+v|XFmzQDBMfk@12zwRfy-ROC31=5-`P0l~-2DUe^U1o;DDwS!)y!H_p8a1yi
zm!VPf+M8r()Vy|z42_!C=E%^fdF=oZ+RnUo5k5+Sd8ln(`#$EKKjOUh!e`8Rt?5gF
z4clA?{5F26PoUS$BzOlL2mh1_49?HoI%}AowG2DSt;&NV6<$B|dzlQ+ply10oC~LC
z&_<gd3%r6bfqrra{7H7f4*|%97sje5QIK5T(9sSpmz|d7<#mdU)OJN`lj$?khCjcg
zl}TDVZM4P-TEgjS9;WSjGKzLA9RV(q5&AfX6>_E(!s3fGy{r(I6%ucSC_JApW?_=`
zaVb`s_hkr**HbvPOXrsWLcy2iQ$oQwmS7M4Z%@N5Cjlj3$d^wc<j)K#hoer8=NJb5
z=@j9Q1IULA(#LXT`U>Ss4!^>M1EJ+0=oCJK91+BNEgB2cL5&!1aH&G1ls<xVEtI~3
z^i|GF3NTOH8!M|u#J$QT4!HO1|Esq<oKN{(Js??y7-MdU#RKSeMCq?6kM&JBi58?t
z%c5zW1sVufzxBaa7Fjq28zRv3ljouf{1{!9n@+69=4nIWhH|2C+1%nTpN)a3?2;jL
zcyyN^i<dxNQ;prh@lq6o0mha1ED$~L@M%S{REH89U!s!0ZwF3}v!8=dE}`!y{IS-y
z#c3xJ#)YHeD}-21erdorZ9Grx7!PkHt}kDB>^F3x?1c+?c%cMHQ^dyDT6)gx@=s}<
zcVr?~x7-y8U;-yTthVJD!irB99C`*In}gXV3hp}cj@+>nYe?1jmZIhC^k;!H$-MAn
zExf<67$*Eb(ehbxI;dGK>{nLgQ_n*CaARAWRZ_i=@OazlO~Q2{_!y1!X#;L?u5sBr
zD9TB}FOb3XmEE$BU3#pqZ19&%12RJT<rhP#^&EG3xrykdli&<5yinu3XTn{IJqtP_
z-1X6neAe|Pkm(p4zX&!UjDiL`ZRWSJF5L=@o8%|6>t^GI-~GHG1Y*nti>!<*KtWp<
z3StS*6vRQaC&paF7^FM{ty}ppr&tA#Rk>&3=%V)#D!0?qhyG>2n2t3>1H)0=N<z}Z
zx}^H`R4gQF+l*CMXw^g(tq-*(v|h9aoD-r$O){GY+lOcuE;u*Qcg)gxZ?`tM^`c+R
z6W%N6RMrQFY>4o+2_%BBa!!op`0I<n@dbioxQ*hT;kbq5LQBl7bC=^QTvnU$Ot9R_
zF1BjwyiDN;T!MF@g&P+ht&L2CZVA+A9*O2kEpiIIYk7)#=lQdx<?f2Vf@v%ETy%S(
zc_OdnWa)X0b!@3x-rI1^mRwts@%$ONg+8^SN`Tvscfn;}!DUBn<$2I5sa`GWro~AA
z1a%{Xqg^2IpKsy!_HFAHyin-8NoNBDDGrq7c!pACzUjrzS&n&v(ZLzUV{ai%9CDdO
zGuNdxl-3--*D~wNPe9vH=jh>5pagoV)fWFt7yhKZ3Oqfe8gV?^>Df<J9S!#)bvASE
z<6=y)8Uo{o`~&>d30(@0>u{6oZpqX;tSwGIU+>2Dby5M&&UDujc`#IrQtPTK4tPH0
z>4s)F`S6(r5|K%4Wkn&Dt%qVMd3l~vyddw=E#T!b!HXzkaZ=<Ng(Nr_nP(Jk#6>YU
zqj2<d2~2MsYo){?oOQTRy;=0MJU8%n#F*y>N_v`i_JOWE+aqYnvk1RLI+fA5hxn}X
z1Lyu3`e?`b>oCrqN5gqS7^lJ&4w7dP`h;=Soe<`a-yM&XOF>vJMXc`5<ihmEepVP$
zO1Tt-<?<wOm~t6oqbubiXi2#g(sM1*%xK(fDH;zuo%9&xV#9ew80X>Sa9Lt-eobF7
znbDHVNp>=<H)j~v^EO<ua;Xf<<r1s3DbNDhhDbZ|91GJMJK;;F<boDLiVq^UDUmEt
zwAx^FJ=o~IV`1r(-fyjxtOt|c8DV-G+!j44D?vlbU(i4k{)!kZX+8Fc7^2Aa`v^C=
zz8hGqb`^uC!k&K#Uu3EO9L}GAwETJY{L{nvi^KW5+49HM(~@vK{Q;hBo$4>s8|Pao
zZE_1C%q;Ok$6IncD!nr;EJv#+L2n&=#iI4%jxfCpMNi6Clu6c;pn-ZSBrU6+TIZ{J
zx*&|@gX5y>$%f~Ba$x0;BQjY}Um@Hq_2Wm&|7Uyt8otQ<FNgDAW97&A68UYqddS?g
z$&VIi_S-mjh4jF0OtFYUz`?dZTK1A<&kMA{^O4AA&tPUD!+Wdn7@G9;>4+a&oZ^RJ
z<fneWDMa#fa|}NsYj6<~Me-xVbrl}NPr*_6vBfEV7)E}E*!kIw>u@6Jimbt2imoL$
z8GZyVWHNmWKb1$}#}=pfVHo*Y0+d3@D4(%0{D`bUpQ3B=Bg22I!WG_n6YoP8Lf@&p
z#Cs5@k|N8=WT+1$lHtM@!MTVe_X=;aKNr1l6HXj<ci&eD3vga35Bbk^m;Z$}Y>_KR
zE869Eyo(nx#drbOah0mJHo#daPEXLli}S5by4?45oA(oa)HHdt{k}&LtdE*LXbbEm
zeeh=e&dvBvK!bK?gCl2XQL}d+&OCTB3!6MQ<1_@0D;a}{7>9!}O;{Up(Z1frc{9#g
zX%nX7(7ZNk8tD2RZ&^O@#G9Lf>l`#({+^rc&DL7VYjCbEm#zRfI+kW71g_k4hJ`*s
z9!cO?uqF<kjr63@{9D^YEbz?tq4PUDMi%u;C~yRYbW-q~Wnu#b@_px@1mD45N)xk&
z7*+y<$wz1#eDbFt4eS4EP{H^n<eyd5=LQ)4Wu-}RUIz}CA6p5#Ph2aou9_1pFm*+D
zx)w7PJgu^)V6%L;SU<QLpfL`8RKQuoEp!>W3!rha2#pJ;O=H>&8TxZ<R5l3=X#kDm
zMQ9lkn4ym`?ICmvz#9(T#n8PB#fil$0hhdti*hb_?8|~U|D1F%#;~no>nVwg8l3bZ
z>2wCW|9~ZN6aM_TZ`#Uh+!ee^o~Xz|Z=eDOf+hymIcM<9#o%`yk{Ad-XJU90^DD&H
zFl_ts@7nzN**K~OrfqlxCz!7wox$J=iATV{H1V8BJV?V5Al>3?kxo0q3_~V_)kFA(
z*9;?mgiX5!Vb?{5IhePQVc_d3z*k^W42}TyeJ@5f22<?kb^*8}{12CuO>Z<RVi2;E
z7yw!rY_c(!;sp}};oqAWZo#|<7_y1=9ej2M(v9K)ckG(WAJduW28l$#qfI2Ws00dz
z>;qW_S7;mq%rH<xSiw|;we*)^B!RGIhV6<BE58n5^$4@3Jno9EDCENF5G-dsClc@-
zN^n<vgX3U8vVf9wpD1KAm6A@Ba2&%Arik!#GL(3dNZ&-F2Tv4m8Ht4e2mc0SX!p(;
z;EbvOXBj|r76J(&oU~WJYpZi=46Sok@v*QBzl(<Rr+`1B@dFP>{PHj09H*cuCKP;+
zt06eA>TH2jSUmx!gK@TMT)vWYdN8!kc?=&5<M6wv7C9Ex^JfDk>TJZXq|>0FZ6*}N
zU0fy|WR>M{V5!QYgFs`nq{C3q;bUPOeizk}SUrC>;0JW@Ytm8BHWLb#;f$gz4^-Wx
zLmtfXupuQsCd$K5(BWfY9DWzoB63kZe>UI;bnt7^QP4IM3f_(C5p-rCM9Qt4ac2Dh
zG?qLn>W87IA3heA;djw+{uJ<MG=5M&_?2|VDQJob1+fZc(gBO69*|{|4nQMY(qSm*
z@UgHAzl(<Rr+`1B@dG;eHR&j5iU|b=m~_x)Fbs$;j~&O5by$1ghthc}S#;?S^pGRL
z_(ZwLb>Hu?l$iM-R{6fggj6hsu{Sb~!DVEjx8*wuV;p_~@2`t@(aU|p_h;ohD$n@r
z9lSp(-<kgdzUwkS<2T}6oJo~y%&;KRc*hdfBCbirYQ`zpTYx={rE0Nyip>KYZtRVd
zoIz_Xg5%MiYA}260~km@%#oW1dV(y*Z77DcEiBu_kwI}A&-l^uC!}gP66ey!;iO-(
zHZCcUEsh*&xv6rAA(AJ-(B;-aN8ACE>k`Y4*rM>Brw`>gngXoY{m9UcSjjxw1E%c#
zx#FIMzpoKXP@Ad)`QmW3RSp|1>!5MPo83_9vO|iO9TFC=@cloz3IjcrgK)gwM+|zi
z(ru%$b2x@asTTzb8m*vl3Yw^(DHi0&5F`0o;ZDl&eL98;?SiR*0?ujp6}l82<DIn_
z;w7zm1#M7JgMu0rw9SGX8Nxo8BxuoU5VZO<0fJK)eo4!JM|Qv&2g1Una5?}<a!Cqu
zDJWS%DGExpAV-EUJU+%^p2R4~U6PJ?99_V#D4IFu{sfHzCm+y}^RLdCN~q3x3LgPy
zni(E&rYk5zL46g(fn(n`;^#mfw;d42c2YFyEIbAH%rX5r^g03O5DYMqW)`73=Ouig
zdd+ZLE}@_T1&vlv4O;n9L6e3;jeu$a@sHFgXp7<*lDe=S{!37AH1X6qw-KsyZs!B8
z0t$bVf|?a%D2T(OEHRN<C1(ABrl9jT=ssX!oxI+ixIL5&{_32w3Dr4o=Of^}(+m$d
z%M?_uph^XC7?w1NG>WF6Gn6!iWLYEgj+;T=(iz6`G7K7lK1~>%P6r_V1)NC=aw#ZT
zK`9DKwIJviK*J}zKZ$Y4du%@GfN%sN0}m=+8N?w;l>?HbDiw6Ef~pntkb>r0kRwCb
z#;Jl7F$z+B761aN#dwfZ4W5!zEg(s%UO^ia)S#e71#Pn+G*p1bbHY277zL?IngD@R
zGah1m5jL6Oq~IQcHN-ze&lg~w^ASFA7}bmkI2R~rv4WN;C>@aNeO3(7rW1nlQlwBG
zLFq8hIGI-8OhI*}+3-Mhl>qCUtNDZ&RFkY#P`!dSC@34yhFzpeW3ov=!>w4*FGE=^
zn!l6ug@ySgClJnwu=UJRPZ409^GZH(yvK|QIHxLTnu4Y)h?b))HPKq7rpQ56P;yAB
z!iK$5P;E7Hqtu54Sm!*<XTbT583W~3a&;&uNkOzxB~_x0qADoecN+0gzO0vd$F)!<
z=~kH;X6;S%Z*xvZZ)1&A;?4^0dw_q28!KOf{V@=R1#K-z)E-y<0^(Ao(cvWB1w6q3
z2Y-OZ2vji#+Gh_Rrcok#)M^>O7!BC?nHjH}@%5l)#uGHUoAJLj<JlRR@uFY)7{Vm}
zQD!_l4l`c#AptYKzZp**H2D+i_>>uctQk)QGUEvv_n7gauO<JiO*39p?61uDw-Ilx
zm87bDrqr0(iRUzHFF(S*oAN5}3`_9th1}S&8IzO3^OjK(W`}89CSlf{F{+1Xz|=nD
zG6{=$%lUw@NDVvd_Iq%1Q1A@RvZ=y*M_!kI&JCPkQ+QXxzY{lGa54vX595#YOExQ+
zn?=32SZwVjVZ%ALoGA;Nz>t3&j2;5GU<HeQ777%Jfre)#$|z#Q8n?Vpz?&4vcfe}G
zeG#<Yd5J^<>^*;RD;fI&4x-$L_0`=#M!svtD}o=#)7*qqwxV3m&EAGxd|Xff?#(NI
zwqjq|Cw5Pe6YK3fO7c9W*EmO#gXLIheI9oRwF`NDeK#b9brtKbgFvD{nCtM*Xr1>R
z_w>CdlYtw7fX{dD;?+gs+={iyeVU#xHn}HZlY8zz{CNk3RKfg>xT-j`mO`P$V(xBF
zeFb}ITW#_vPHKmyo3y_E>CtKJw9$$ut+%3RwXRUKto6Vqtmg%A$c2K>mhzVtbs(EY
zHv+{a9{=Ju8v@x`5?Qu<4401r`4}x9<K$zad`yv#tL0;=d`u&UetcnO+;m^f4Pw8%
zp{Y%+gK-`b=*A++sYn+3D%)HHYDhHJeB_@p(aF}XwYS7JJ@8y+8vA<wbpND`%mz;{
z81ll)X=@pkbUIP_^KYQiBvVPfSTmI#L2HnpTFx$30L1L#CCo0&DT3z_t5VF_#kDV^
zQtl&~cYK)T%&x!$?rP|VIW6*hB^7gOx&4lw$Z`(tN;yxmdirbZ#T?RMF+ZQHipj<o
zF5XY!Ym7Obm_2PpB9!kn?TF=G@I+Mc%9f*e53_imp{W>uLNUbprdhl{w94YmL)qEx
zFy~`C=6)aV&Xo7owV+0g&<+UM+6R>_*;uqw?Wl|fqR9N=d+$X4XWPkteK@}>CVv$D
z-?o$gjBx%9`#YiEzn%OaBFx+ox;G+!Adx(q_hI^(6Yc+HKCOMFtLKOgi2H|s4r9p&
zmdO1>8=gFS{^=4a^B0HncRN~sr#*k)aQ;5w{B>VO(vPgiWSk&3&e$GXk2?`&%Ap(>
zI;uyJ|HEyu`5z7EA0CrGT#q9EqIU9M70&O7$sg7uk^lO3^7jtsul>T#e;|>0%zAv2
zIZ=<F@@duMLwBlrd>7%S6y^X+WIfvOl-lzzkVsjNe+cKl^l14nvFD!}&R-PH|6Pko
zpW|RM8YH?=^nV_V5mWsfF~q7%9ma^d?2K~}S(kn00R4jL7#|1K(6_Y8)va=L!dbZQ
zC&SyKUoZ_318Y?HNQ9q?@La6lq+BNuraI7{2C~yi#9KOyK8&m4c1(2J>}-u^?qC8Y
zgDao7c_(7PA~Q!Dt-vUlJrn=acxz^G5c=2%+abzV1NBBb0xV*{CQ(-1Cs;i7*=z~p
zC-12`d+YPaI*Y{@$mRHDnJ2{eNHo69TNS?FwSzCLiv{4%#Aj#l@@Rx*VTApNFtTkW
zt3H<aV#|9N3yu-x9TY~l<FoHyUVfz^0^go@Re7u0!PjYde;$pnI*c%r2*c%ty9&!F
z6gf$kSLF-iw-{Medvx5c+GAcA)n}hZmbHCcR-1Maq1>~N594^ohJ(Hi(jEJjK#puu
z@(Q^+Tnk+i$jLaDzh@1I)BBihs>Hq8l~|&U&gpBmsXnqzsqh)HP2oc68`y+$WP{2{
zyH&iI4GNpObdp>GEi|s2ZEH_Wd)TUldfFQI(b`i<01XOUW}k(npR&bNY%~_QlJ*x3
zD=hcOc2L=_o_!Rpw(I|)^kU||NZH5Yi)~jAN8`IajPIxI;0x;+`D>?L<wYax8%DS}
z6rpFa{KdAb1JP=`eTypZT|{To+gN<D<^5|kJ}r#zyms()THc~)ghRpz_k0pj-aw+L
z)7W<9L>ASqmU>mY`gF4@>%&B4D{K3>tah~=8O?U}bQs5Y3rCD^MLp`WBi|ESoVCx8
z$T0TGqe+KE=>xIfW6hndIg`j5{23Bi^I%+wM_(9{3%XT!3_rXCq9cB6af%;?k)Kr!
zHh!*;;YVZ*{t<~H`H|ssRd@_P1xMk>7N_`O82K4s=jR`@qU9s92D>Y|mfU3c=bJ1(
zWB8eR6n<=RiXVoNpT~ew)mLr|KO$@JHbvLsM}}Xk!WG`xCf>?k&{<0lLNlYw$z<z;
z*CUZ7cisancBhi{f)wBE*>RXL)>kxmUF+BR*2ilFDO!D~1^sV1Jv%<YF1XNr$q(}N
zz*&=V$=-zZ>kL24LbeOU^*E+tjR?Cv9OgSFeo4FtoQA-tbXS<^r0s^SIb7BXDLs)B
z7YCn{e8PuEp=9}Y66~KRf`=1cM0b_D%h;9U?bpLa%xQ$T7c!<CF_u-94=UKcTNMzY
z0&Wh7yaHY=Wg_mLoIx+2ku#|JER(giQdQ(CyTcpjNv_KER8H`i%P5@7&bkxs%9-NR
zCcUciFR9D*#)lK&EX3f9%A!`Iumvv4;yWbiAc;VHhoq{gHPm3Z&$j9$yxvtRgi!G*
zRxoFYwWJ4ziQ@f+>q?)D1cKZ<3HFwyo=*5dmfBY)u^T_n6&Z3EvmT2Unve3R%k|*j
zi$P-s-tZ9XCfXgd2i4%F(1$RCO|ceL1G!RW^8+F$ljCv{fnUInMCp-UFdME-$7xb6
zjuGpIzPI8-pIIvOXk<CF<i)*Qm4M9(UF5WTF7(@9+RX2fm>aT2D|YV2bDeK8J37?v
zJ=rXoyBxQbi<;kgIi6BIT%yqK@_WswG8SB^NWRpm5+Yeaof68R=g-DuVTgZr8rK*7
z-X=&4UNuJRMt1y-u)VON2j1Goi#vSD$(iH?a(xrM1{k-UZIOB=KEGvCwa3D$CO$Z$
ztz+(cWNsGwPWDmYYH%}`Z9_rPMpCJcg)Tj3wl<QYJ;wa}2G=TccwQ*(Ku&VJM>Wx*
z{UY=zi&mT0mAM}`pd+!KKh1Y2$$kHJz{2&dQOj%4=cHmmB-vaJaaSBdWZMXr-9~>C
zOICXB^r3l;;YFo+H&Jys&k+@HA=X&5JMg`tX^>k*&72H<&h$YwTJZ+GxB+V~DFJ<S
z0G9%<(?+jzWCM|RpN_b^1}%3weR6WA@jJk|F04etCd1v~xc*<ypP}W>D4XNO`Kj(;
zs%nylt<PP)7BtbiOs(;Y>vXlEdfY3`UECY=qI&BiHf2yHzNTateE_oF3NMwKGZz^7
zz7YEhY)AmNWXq@`Gb*2LOg1LOy3E+VX6$ULoM;vlRe~vpM|Oi^ezJyhcoS0eQK&O_
z`3}TYtaVrHWg6w^rr&WVFXpXBVA<TXIPYm-p%SI&iw_~|-H9`u>3NnBokTsmlwdbl
zs`?y}uiDJ#xxQ-hC6$vrb@_<j1*30GQzF&Lc_T7IzH9X{)1Ww~465Nih=a1jb_kZl
z@t2*s#=B1{LJ*%V44<d+<NkBtD4vgP5`2G72(CI5%U9*vP&wMSHX$Y08>|@xX9Br7
zS}cQ^9qu-Sw@|p}2tET&&E6$g2G|@|%<<^haVfGZImYZtx??;-Kk|izd;*Zmz9+iB
z+|1j762*Rs?BBxO9i|V|S<$71SqbyV)^`$iInD0&j4aW6ithFfj5%g^yHqHUM|8It
z1qfE%?I*Zn5#yEUZs{EJ<9E06Oxa&~N(i0DF->7xl=Cz4zlFQBKdksM{wU}><QOFG
zF8X0e$<ta~Mq|o!)5T$#{tV-mDbp!ZazdsJ`F5E;EGt3Cw3~?ev4=1z)A3Ln%5=pC
zu`->*?dTs?{IE=wtwz<PRGLsz%2vDV*Ooq8wjPtM55A5>))*^ob{W3N7XH0#xKqy{
zA!&a}+s|ght*6BpWt+X+PS`>-EXrQX&lHs_>^0hM=779us0bGJ+9<Z8yUWlHDT3o<
zjIh_{Q5$|ldrhnXdSS2K3VTh@^^|C{V6e%r*TCQFPK@`b>&dE{6`vuj%e^(;md?06
zUCJZ6kNE<dkETM8A0i4T?6c>Gp$O6@+iBDD$t;=bBu<er!>Me3m@2Z9C<(wQgH?tu
zy6aZi!{M$gv^w0Oh33mTH1(oWo2>g!EZr03Y}Y0Wy@?V>+GJC)ha_yWbpa?cYI6i`
zKC|0of5}Gaq)oO#Xhzs38_t3&HRvYwM%ZM(quw0VCYuUYI<U!pPfj4$L3sXfn{0ob
z$jt%J0LY>(*zqseWKY47!ZudfY_f8g60n$rP4+I}4sEhlL`K<UgSd_xWs`k6jpLiL
z$(}%x|0bL4R+wQ2(Tepsu*vvRhnEuVj##7Yg>}%J2&0U;WEy3a0BL!-E|98o4a&*)
zX&7ToqwM#lRt+|zdJIF9GRoe@xen?a?L%f9N}Y=_%A8ySjxx$#1;aGT*5Da7%EZ1T
z`UZFTVuZKXKLk&r4VEv`l(mzlM9YUQc5A#A2=0YlQ&Mf(W8UjQ=X=;=U$<kAy>lPz
zv4dRbk~UWsZLY@NVVf(fPlU~Nh(?x>6&Q^RzHPI)7Jh%5Yj;|N9;b0`A?<@=%nt&I
z3ov4ty_dZ^>x$L2-~-j6#-AVVP>V76n;mME&=8L>#=2d`N~ZAH*y{(245CBLqTYz=
zw{y_tX>Nxds<aW#<s1hTAJ`geBV4)rUl4(5C5Ul3daQ~6R}i!B8veeL?URGTvW>^s
zYs&UqDM2CIXJCniWqX6H3?bVlR>psuY`378l<kG@#>)0Pl;8)emtD5X2BWG{Hdm9X
zwO;o6wU&NcHW-tw4_<^skv5nNKRqUVnMglN;lUUbh!cVG4iUUZoqc46&f^r{^%mc+
z+xSjY^en!a416O|B;PXpbQK=MPt#HOvBfEV7)Cj6c+JMotZSm>D6$5hLZV21Wcd9m
zJcb{BUZErT*y0pF3?n~Tc78rAj^;;X4W6v%T5^-&ZLeB<#_+>iwmag-7N_`O82MQW
zluFMg#PB1s2JcaHEq-M9%`xG9$wu&4g$H~F;zXd-CESP8cH%VLh}d@GR9=!8ER`n}
z`b@?8-51Ih;ldI>@0(JF&#QU{qCbD*7<8%_14n7~gSH$zST+14M`hy5cQ$O;aBz>d
zc}+0U`%lp7w~ZeFUZ<_~?H%bmob5U5%(!eUvmS~+rN-CP0yO^N-BLzrZ~6ARt5T9H
zd#wpNye*+RL;$a^se9G%Za_<HpNE#wR<-&($xdonDZUV0jL&*ikA;1nM4s?;;Xz??
zP0*Nd@GxwMl&awgj!LeTw3}!=UF6njTeXHB+q}!k_#tayQ}I41lJ`=qhNt+4C!~zk
zc9`s+>|VOxvF0;}_GOP9UL&-UpBpPe{5DY%(no^CHJ>GFEg<u8=#OFf%CC}{^1Tq>
zX13((3npkSlyHeYd_q!*7B6M|k+v0hynD!M{pLfFQtltYsjnsl_=x9A@EO0hL{FJe
zqMZOfy`O~MFr!+)A}HjN0uhJ!aorB&eLdyv`#hl|VeWxj7s?HEIY8H;%s)6_lld|s
z^UbkRzfhHBi*Ij>Z*2;NT9^Xz6stSFp+t8K0~Jg3l<eNn3sUrEDwa&JVi*61p?guj
zh17apTqD#U4c01iUoeEPkz*advgkv6F|Mk2W%0g1-Ug~xAg_TBv<S`H>|VVep9deS
zl^TP#4BCm0Ok)kRG_BvJ%!BUx`B^Z0K96ggdAo)drn$@ikbqWmd%RYP4-cmGdrK=a
z)_jtn744JXAas|{MZB-n=;8k3I&HVMu}7WnqeS;ZYqhOEIq1K|k=erV5B%dCnVa2z
zT-#%-c39hAzQbK!fNc2Gdr<?HN<lyC1ubh?{!s6}neYe|<V$z?vxey2UH-v?@U6nk
zBEwyti#*5y;#DVAo;(7{)4X5l-hG;vIkbcLB6xrAw*2^(_%Fb&wlU-wg~?RKPIq}L
z3SU+9VP&$vARb@y)=QhK+~w=%G*!M;^GQNw(f*pf_}%9&-;CmyeT}l@8G31BkAuFC
zS(fx7!#~H7S=xvaXz%&QIWxDiEbnQD%gNSb$TX-;Pg$)^Tp2$?J3ORl|7~BmSCsAp
z@%Tepp5f2BwDPU9i}qC(?Yg*dpQkt1j`vlibk~cG%9O<Hs^VRJ*Ol*_`>9^M?{fEw
z^~2%|8{;<yv)k~I_|koG?)!cVdlnFmZeItepEqr2kufU`?y|{Mj^xU`eW=#>t)gOE
zg6APcNp-F`Sjc+arX3DBs!^F0xVDS)fss{(A66#$r^NG9kEO{~u9G2%-IZ_Ggc2%?
z_t$)gUkKuLq?Cea)=PJpf>@Vc+$;pKOH{UhiZk;AKs|PAN6L$v-Q{;9(;$3g)4+El
zqr{;X8K6g@#2?Xs1rmAt?Bacu#fBvjR4OIXEG1%?5-GAIvI`Qq5E9|{0{hC&10QDJ
z7(5N-)i&ZQYQ@k2uDb`DFo&otG@uUruzPc8Q6<ip;|2QxMsOaI>!nn>;6|jg+Ri|>
z9ez?CABjt@>RDOT638=9nz%t*^ulDVu*to;v;~d$a-4zJ3)A{--~4sv*Y5kDM$Hc`
zMk8rpBN>$-nvwSP=HM`-+Z@yiTQ={}3U}cPqN0&ByP#P6wCz3C`1U}r)}$Bi^N(_5
z)+4mmU*O1m+x^EiNrkmlg|+2{r~{2nWIfu3u4PpY8(P>hvlYkX{aHQyt|40CHh<Po
zyk-_Qdj|Q(CV&<g>ko<~-hwZA7VX2A*4ess$Ji3hF_IX(U+M_P$K*?!{jSU6>*L?X
zcj86ew1m22Y#gcQ)lyNo`%<C}^cMhctzOzxb$a>EIeRO&Hv}sS_ciQ+c-`gP7AQNy
zB0)u3jxDVfjRl3`t1p1|Qj79voBRdcG7HfStm&~y`?|akdh(WNFdDu%2;@aAddh2P
zISHcW?7QtVenPOY*1aOn*xVGq27*k?Ye6w8x1Wtl-E?uW;YmjWLNP$72&GHG_v2II
z$NFj#&>pwU4WWdi+$(nahxbm1&#R5kYYCnu^roz|1#PJi3IGUgDHjlg(6129sd-kP
z98`3b>x4?ku{1gUJ*^aV{&mpJM7PGZL3JEdouX}_Zg@A_(`IPMNJ~zlHKm;lLG7^#
zs>xmcHd0AJp;LjNc3Fbrs}L00Q>>sMVjR9S8&u)0_5@{6xmM&gNkJJxP|Xxn69v_z
z1Z6;`od{|d1$8C_h4wYjYF|<_f}fzJpl{FH7JN`ZIx7T~w@WKDLXT;?#rrN)CMqj9
z6=G6jQWi#B2MWQB6F!XBJ+Rj5%+Dlh2l?sA#)CzTY@Jw=I%fh#pLP5sV&neB%*tC5
zt*m9p>c=O55scQ#<Tt@P6y7}V!^~?QnwRA1Q8pybGyMH+p@jFhAv{2emXjhn%Rn4i
zG4GLMlyMGFTHj~&kLPZ>c~8T3=Ky^~-1hbF@7dk-{`Ruwys~d#3T}4}6rnqUyPFu+
zn(ci-(1F<6;0)Q;_IX>Vr%5{;HdoOO-DNsj4+y}LKnYSOh5g85WOYA2Qs1$x;=yl+
zvYLpjk+M2Z%4&Pf&LO6>j-|B5Kw6HH>R5T1?q`a1yVwrQ42x~j6=AWJRJSX)bK8*{
ztS8iuk`cv+lQgj4Pqlc7ikpj}->Smk&4@H5x%W*e$&C{^5wiO87+L0m<&I_f^0=eO
zG6`8DWjP71o8W(Ygx+OE>7C-%F1b~=ge8{-qL#w7E4QCU%k7(N?~A6~=C*~7M?a)=
zZLUqp?lVObsFk9539U-n?F%_?61F1&X*(`##bF>3MnHzGT#Vzb0F^uk*xE50k+FXU
z<hk~Z*X}lNG1cmDiRn51yi_z#7iL{}U`t0FVFJfg^`F4u5=%`jzS;qzd#ScMf%m?A
z{@`Zb6~lhN$>=whb%72`M=uu8w#trxgwPQP+P8uB(I~wFmqM)$?fL;z^di?Va*XNf
zlk}<ya}h2h*RJdGn&4y9toPD$TD3L)!HJr8gFa`5R@w+Rf|>dpe&lt6Z<9lu)WV9+
zuJ<{bG{w0q&ckS^dz<xc`s~&N!!JE9-IH$2OyZK1_hfzerF6k?n{KYD+3xa_kvzOI
zTW$7#Uu^!iEs8cMdhY{U@%o%3uz|6OcIbV(Q3?7S*SwFH0r0h@yC2GX+g))123DOM
zBbU2;C!)$q-;VR1ppR?~3_lj!V4-v}+D<h}CK7oK;esIiBFw$_Asp7RXYVfm9N4PH
zUQ#(m?7vICHtF8R{@&z@19P6$4!c)ufw3Oy1s|ZVE01Z*P8oynOY}rNyHy{aI2)Js
z4jq>|^FuvZFKp08n@%Q!v%TA@k!D<L{0==wT=Rn-on8$0@4^6^s28*b$C5|*tsp06
zEFP#5)?#@$jyqWcGwZx>;E<M#FHJ@S-AELHftdl%DeV$Cmjq<hQZDX_uP{~xcjHG&
z;Umb$l)^<QyOctYqe;Pi-(Qf&l*ERRGpg*fCWi$x_d}~@vl6w^4Z(>VC#@i%Xu(qu
z1e+bIpO84NHBvY;cVY|<`&U4u8&ruQ(#P8^@FmC;N#X+x;OIBpE9Q8D7eUGvd?rW(
z<~Bn)?$wO;(WqP_eJI5KMf>qPfx%z{HBQIRNYB}9^p$9ALMDC(F567Ohm&80IOB|E
zINV_LMh6(I{|4nk%4<Z*#3`+QxR&Ia$uuTQE`o${&4##T_NvBjMJo=yfi}L**oMv`
z)ExTC>i0+6+VHXZ6|Gu>e{e6&+bG&_L;G!bDK<Q18}8Xo8-5;z>7WfCL{V5Jqh)_a
zhaVIq4|ntEk+dV*aD!;W4Q_dnR!kc{0a($<%r^WAq-D0@VQ9mN_BNc=OTR6p;sDz4
zT<%hBV8+`#V55H?ZsMM^(f!JIP&BwKg^p|EoVT%}ZO*F@iaxy8Y<+gh(AlYO-yUQt
z(Jt}@613SVT1!c`x6z-{EA%ty!cp2^2kq+@*fkZk9UKqU`u^?nr_3)!C)?*KKod;F
zPuU!n@HMv2Tf-%sAWB%v5~2@c8R?$ozV9xkyP_2Zfp3{r(p?CQEa}F`7RGOVL{wbR
zE8C;JGJ}~%X`{d39*R;3seW0#&}#?#BbT|aR!Qcf_U5g9HA%iMcq)oqt&b4<a8>Q5
zAK|GRacjJl9;Q<pd)eA>mms3zcLY;d6Op}zhzg#7Jcb9zM|ujWx9`Itti7hX{sW|&
z0YAgw9yC=W2RT%0{O4v|0F5!Vc$H|4Batf9Ok~vpSyXGDOH4Vi7eoI*d*!|6=77Gp
z0A_j|FSFwU-SU(3#hLbfZ(w~HxTYfq(yv?+wn=>Z`pVO_urXY=3BifoalRU63+<MU
z(gY*YC?2j6Jj})#J9((NSn{y4M)J^%u1fYXT&BxQ)>HKfts}8qFeY>BtqIyzILKxX
zT3=FK<!}#i^n#!1$YGgZ%sdl!)jQC6^s91RR8sA~qOI(3>1{m*Z5eW``|-6uX%O8;
zNi`DGhu$rzUKStPgoM>YTmpe-6Wp!d#)@{NtX7Pmtom-3d_Gn+T*zwN>ypnb$tTv>
zji19?R?o(#25@fEl8Ny3Rg&YiK=21`;nvg{J;eETb}t6LjLVq?mZB;CbJjwE@>;?t
zuEllqsr{vZT3?f!0PD~Zw|nGzi$CuG>5$0b(6?=&H8drml-7~!Pj8pUpjl4xH?Up)
zd{A+yi{S4ix=JbjPQW}qmcM(KO2MSAlKh>~75=VlkH12}AJ^vdnvFxyYnEg~ZxR)%
ze%-6s)H^Egf$m}657I|S@$PMx_i4{b-ZM<ze}$p3Q`tU_NqUTIe?ObDHF?i6c~1`W
z{^ZKect6(0`_Ks9pTps{Sh-JGZYre7`?Ju(PI=!OY=`%EZ?o}UMt@Yued4J~?!i}V
zyhAmTsk-xrQ@o}IQPIAFZ@;PH+1=1tQK`{k?aGc~egKa7@5DR^3k$hP3m4$33pnhu
zCzx**=xVb-JJ83qTcFi8ML&TBdM--Q9kM`lzHT;j*m_i;I&$*_`W}|<Bos-j3+)sA
zSI2GPHfLC$o}#mn(x>+eqKYNjYTC=PPNthhIJu)D*xTwDqn$b#cB`#U_OY7)*EOlC
zPKs98>ZILv{5n?Atacp2SQ6&_$#!{PVDj!UdA|y7?d^)+&iex&x5Imd*T(xmlXpj$
z_dmTXc^CV21B|M#F_s4`y~-A>`f=48RD$)|D)g#}<u?+;dUXhs34CB8+*$q%XQ-53
zX?F;fYBI}IW|rw5G|YC(1V#SH>N{6|gfhJtrBW|o{R-_nKsGW@1{>c|ohGn<L`Yz{
zrB3XhWVv7;^KQ7j<hr<c9C;i%!R7X?M9XonNC@OL1BeTqL)))AXI-YJdE2;w@wrLy
zdCi%1b4&C@kZ2p1;XBmk$pi*`(x=~6-*@qIH&m|CC#MXZoI2~A%7nHNDQ#FGgtz+y
zS7yVkVcBR^c&>G?z*cITHvrYQ)&cbH*zyo|3%$WHm8m0rGKk-BDoM64_BQLW^fOPQ
z4n1qJV=_;!7J;kaf6;;p&+P|9lsh+RXfDdl`7u8Si%jnFNAY4wU_f<r`TZ$z@e@oD
zTyN22M$ZU+lnVs4js3Q6{*H2}g;75Aw$xd_EYZ68>JqfuD2dFsW{oP*6MSnE@U@MS
zY)DS<Fl)I<-}|bqtnHQGVr?6WAG+J*pl@ioezN<O8lfYQ-uS^lUCT-t<qByQo5FkD
zvWb+vbJJzCBNjk6*~=xbkX^*RR7ni_t!N)d9n<#5h1>BNKoxGsU%^j5c3g-XlP3(7
zxWCKs_(2e8SLf~R_^l7yX~%!Z5}F#*rnCEls%PQ)P<E$aee(;Q^+6Zec>fihs#O0O
zJgz-kXZl>p`!bXF_t3sN<^A~fc#pU9zLb3mcrWXvct5dI-tTDpR`s9H(w#~1{$xgb
zyf-~8c^|M^%Ds12cptyF9l7UW{Y=TdWtil>wx{C#=gT^i`y1bddH<XaSBm%e^V;M6
z&|=B^IFt8lVSjWg_lNhi!@G8~jrYMO?@3|a|NJ+}yKPP~1`NW^-YeV3^rey&4_Sed
zHNwt_=u^4og*6V|gM-n*?`>wyKJX`uA$Xpeg2IYU+Vdz1D%Qt5SRczz8k+B#H3;n;
z{i1tCjXpW`fFmc}dmJZ`a+Q>QL4J}xiM{BMY%L$X=*%s8H(-^0u(uxQ)KXf4=m}Eb
z7q?!{L?se4ecx=)7KtqMDr67F{`m-!VZ`|J^R}^1`0%z{p0)F3d7kKHm1i*!M3?7g
z@LZxNm-r61dCzE<yNh`gIlPwD-Tlg27y!h$nvQN5i%eQkW81i-@*2IU(bM0O6OeL~
z52vUa(9b<7gJ(WuNdvcw>m@lJzYVjLQ{Pa7Ebal;2a5arb11H5vnO+CFsp<I9dpD%
z$DdZ^|IEEw_N>U!@EVq#@^A*3KK8+ptG>lL9R)ZA_eIG=kH?U4ap*A=F#3Ff(Fgir
z`btUk!xQP3KS0j?MRMVnZ}s1xQuR89a8lt(=Wkbi2mjX=u}4k4gj#`wuu!3Zmw_R<
zRv#Oe3p7?7zG3v(>)&#p8*{?-!6iUy_UoOM+nQQaU^sYZoivr@o{GDx+9~&$U{~21
zSyg#(PH5opf<-2=#V`>~LtdBr`Lo|*(e2|nZ@-l+7JPd26ZG+|@oycQ!@UEs9z0k2
zs#|*`K;%MFUQ(~eqq!kj_%;w1d}ZN0%oBwPTz<YfVK&A=VczTmb@z&k-7ByNUAO_;
z_F^3=kk?3L?$r!!2%QYSf;N}|n-G>+y1`wZgIpX*b6x!!R%7Agvi{!2%(^)VS{(*?
z_kAxRomiO0qMu}!hxELYc{i<IRPS+Ub^W$lHWUvbqfy?2ZWZHxd<%@BcyFVyLDrLp
z6+`BgHXZ>D_uaQ~VoXNfvKXN+w~*0m6jZ1W?#~yTSGVOgit^0>r#Uby2G!92vJuPL
zS0F@d@YOqli?PVFG6DHs<4>qb$j)ETiY~)HGk)kTj@!EHmnT)MpK~&2M&?e<?p6xY
z1woE$#rm}i+gvU^*`L#TiMVlXG6*ZnZlJX6+;?#?*|Ip`9?okg*muDcn+Q<w5IhOo
zSf-0_QyaEHxDa5Pa<7>?j@r!Dy5R#|aiRGmJ-=jMI~=D_s2{BJ_<FgDZ1}J$VeG)!
z3YI$P1R7H;q4gFQW`MBn=q!$HWpKlzfLJ*G3$jwP7d;Id8ANu&6W>yv_y&{6X(aM{
zSO}pfLT}S8;wEGcj>C^ticp#8N4nn5?XBuqREhN9HTL0aZq|5m1B~AiEw8TqhI8rD
z-^qqEpyP(KV*@y3KXQXuVnRK1)^;kV+uDu?ZAT1EZr@<2O^Kdb;yXeU8ERFMS&UDa
zy$Q|-wYgs@tV4?mom5gS6U<QwmLLHSz2XEeMz5lVerq=$#<lEir}z6B8~&M_=Om(s
zhq9t2J<X(rjT`{<q77oof%<r9^I^0kcll7D)F&lr>-zm;^AT+4i8%>(d(hxNMost~
zy%RAY<R``N##rk1eFSV^cpl88w$t5rPlIAe-o9f5nD->x8dL8<=*LG`g<S+%a)6;y
zVF#^(XINxI!bb*#KBHOm)QT4SK5=P9%k{#=`sJ-C5Ik<`hmK@p8jr79&N)xdt7orZ
zw)+vkgmBSm_0S3z`+_d5aJinhm>n3}kr>;ti3SPiMT>DtXym-o<-@PW#fCSH7@F5G
z>uNRVVQ8~By^HI^YS>#BJf5YjW?8~*J(z{SYKTrRZVavi_cAW{HU#5)yDhi_L6%*B
zk#nJ5xI8e7%WG%`_1Xy~f#Fx6w+*sC8q_ut=RQ#>uMK8ZSuIf?m+UJ@i7(q5?>*fZ
zi?b@CDZUB3p-ndCYCzB!JrsfjhS|hm_R;YTVGN#BqaTul9zxS}02P~N(q9j^g+4b<
zKsei8f8YrohaZdU(EXzARpC2*{5BO7UOc4@Hv=LxF2pUVq}Ed(=@^=mG;5IVn1><w
zY^yb}g_U9D6i>%KE@XnkD@jhSnWEkBLz-gj<h*G%aqh*<pq=5YiNe{fW1MBgd0!WB
z#;uCv^F<uB>wwR4;=H&EI9*XVujv?PIxm0y2segyR`#h_wYSUjn2vE~5a$D3z*!cB
za|Jr@4$59YoR@Y1=e<!lf6+0{(Zu-)Exk^3X?_&W<2%MVjyNCg0?x%zIA6nP*g@GR
z5@${qa4w6&S<*4iDa831t-VglzA6f5&yI0kO`MN(0cU*_&ea&CJ1F~9;>_;?&c-O5
zzv&p~G~)ac7lL+H_NFMDCv}W-25~;#1)Oo%d9t^owdfT)D7%L^M|J^cdKAu^I>tGh
zI1eoEyzJRgI8W^u=bgm)L>F+5j>1`o^Kl)Ny^J`=bOGnoD4a7p##v6BhhOTv>}63n
zPwN<GC2{_>3pf`<;d~1tW(Q@zmpI3F0q4>voVRw2vzj=+d$IGfH%H<8X~#GpBF<;J
zfU_kE=f?9pEc<-ooYV!J-$dd3UB@^dBhG{_;7nQ***4GW0H=9EX~gC5JcDU*M}Js2
zw*6dTqdb7y+U@<zInqWs3vFM_cJYj{QC6Hsxp;7Ii189mry6U|HhmwZ?c)*Se;4pB
zh_X|z3FEzrcz+X#SK2?zI_EdW{t4qvB;KBpc<&^?Rb9Z_6vglJgOnVe-3`32VVy$Q
zgi;Q|wmPp1c%yBrNnyMbi1!zfc!hnn<8PhIA=<wBZlL1#$OpiCOe9`mW8KvSywNt+
zU&DA85$}tABjh0Lth2j-H`>k`6UIA=c(07aD{QST&v!0|Xj|*Re<?Zae;;@gBJm1)
z>vvti8*Ohr9>)79@jmmj2ssFw>!)478*Ovthw<hT@Ayc(!tQ$Oxz6PfZFhZku98D&
z7w{fFD}rBPd(G?u-e}wF;V|9@iT8;}yu$uEwF`Ko?XOG2c!v`2$Vj}x23xzdb2&uY
zU>}{M<nSRp7L6~@jF5w{!+z5RywP^pePO&h@jeoXSJ+}byMQ+?Y7DtBjQ4!v&56V-
z?6KFL?OYD&QFwU=q1mtR+yT6wWJJh8*kr%x0^aN>ymyE3`iS>|NW8)>JEjYGqwTVD
z!+3e0x^ZzNUSXTP_)O<=m>R|JRt%J;9R9H#c=w(WAqQcfUD*Y^Wl?zNgz?@%yj78S
zg^iZb1-uKQ@SYXM%lp)g^CIyIJMEdLJC{SWowgC<q$!8D=?S~zrx9`xw%YhE;ElG`
zZVls|MZ9-K;uZGV;U%5(8*Q(h7RK9~c+ZZ+D{QtWx_~#@W~;+EY06>Ud%(NpClPWG
zcH77<;ElH1ZVKc5E%E-&!aErYx?+E%$ORX^vm;I_T+WqBu}q0Isv2Irhn=kCt8iwV
z>)p1^xOj78z<A|3TOwhfbQ%BDuHc{i!|}&;1^>aN(fq@=5_<xbc?W5oVvRIT`ubSs
zvYx@slIFUZOb5?pD;>9OtaNupr|SUUl~y{e@xhmMJUn~h(dz0k5;wUDd0OFI7#^LB
zkKM@iKyG3rVTIQ3N;<gZCs!b~8BQEBtz0vlKm<iD-{B<BIljZk;N0AL-{EAO&|I@8
z5d^Pnjb8^x7T?~Nd%UGhaN*YOSFtV*SJ&!Sv-#Ym_PoTm7rW_GTI2WgI!Bzm;6;d@
z3we~la}uvPtb*KfJv@LSKSGH8v@CqH<WaP?sCyA{bLzW|az73BEcamIxFItU+7}k#
zW$#eb;k`^R@0Z2Vm!EP4b!!$T9*{hb!Em>7D{tWhWpPnhHIAxa<M_)+C+NQ{w<l5M
z8o+N#60y5{DN1ZM2zV0l><$mb`W-zu#krw3)^78#&D4x*86j0yRT9YXI7m0)%=`c{
zyH~HriPAwkL#OeqgR9DQsx66U7QPGZ&$^O{l7&~0*d)bq`P`w!%`-Ovv)C!XX#fa;
zg^EX^kO%GbSbkC(`)un@1rzFoPrJoj`I0QA+#fe?#P#96(xy1i$vkw#&sOikxme?O
zK!g*YIP5vnGla!^wGRSV9>1fT{W!yuFQE4reL7U(o=_u}u!jL;1?1f?cbDdge2Ft!
z{gYB~SCc#gF@u@T$B-F%hjNx}3L8HiG?r7)RH^PvYw7#HV>^)d=7~M^8Ljaj&~qPm
z)aAM8<1V|(Yu2w5zVM!mXg_$~Eft;AXuxH(C^Ncbev1az8`!tg2kJ@g)mzM6qqZyh
zLVgFrosIN7Mn&vGGx3QpMHusdPRhHZHuX2vrj*ZIq{91e!IeEzF>A$Pak1SDbr9+Z
zN>988PXV4-GEXES=>A&l|CA={7wP%f^J&INHWqu4iE<lOoHQPKyV{671@40uu1UZ}
z66eWbrNLL)9Pdfz@!015i}hY=N46K`DpVO)pH|~;gyhg3>-;A4c_cPeldz$>U3!})
ze+~}OaF*OFzKvp*5#39w|NpS}E^tv*UH|yrbLJq9=%8R(X^p0jcn!RzrZouTEm2Z5
zD+@;$gyI$qf~5rk<v5U9npRd+mOf=qR+`qMg_pdPm8PYp7M4AMSXmFHnZ@tB_Bm(f
z%m8Xu@7w$T&-t*}Yp=c6zO23X+P8Ji<ksOr3a3qT=3tyEKd@yky%`F=d{PK5eq61U
zYTQ-_4RcHRXuP6SS3abjYxYrH1+E}FEK*STL<I)pL!Z#)SExIR4CgNf1K(8q3pbZM
zh#Xw|TnA7QQtDb=%%xip0Ft*t?z>ScV^RGXx*&hxGXxLXHlsN#@&@h8HQ;j$H?}Mv
z*P-ZV1_R*y5tOC*VkBK))Fg0yUFnXzvE}h0;`-WL(ic}++Ff(-R-=j4bOZ&q`$2OI
z;>}Xb<AYA+t|{6^NfsTcH#64lLnZ(GPROqIvH6e(UROk##XoarZ`VG&`G<;JUswBh
z%KW#fptbw7?4hvK1`w}TBcHJ$b4G?Ba?KscS2Jj8OU6Albj^sHrkzDN5jh2=gsv=p
z+poA*m@WS^8sA9EMjX5#IXjppj+k$h_n{8XC6gA9zNYt}&{j0r*p8}wwHfr5RqI;6
z;5{nyTcV|e5d}@+q_M7}zIwHL628K56e{&*(M@r~Ni)yHE$DcBH(t_&S&r_y^Ab{;
z^m-ropGCUhr)3c0OSUa%?XzR(e)@d+?3Ck5pRIFw`>e22!h3;`!Z-af(QVx(#Wy}C
zw~kQ8q<Do8h5T0^6cPjSVs}m*EPi0nNn^2~4sYu4lb+r@GZ^nnX}y{1b}y1q*u3%a
zR#myN045>Mo|?4>O%!!7<a4*cWpB~X;xhMQk5Lk8i~g13Zj<7oQL0|Kq9Hi0T%$uU
z8|+nvY2GxY${bbpw5zByhU&obd~K*MLdzBXM!A?v=?1%eY={dpAt|P8s$E(+-uRm7
zt=nCsYVPu{+q1(_H^J1x6QAl9GLy_*#H26kN0TnD-ovSWVYme^I<4eP*Xw?DbdRHP
zi%agJpV4ElFh6iHN_S1%-WmAD287mT&_)d3jpeb;Tb0L$qPrEH7DG55@}u{FM};B9
zP1LnUdWQ0dI{Z}hjpd`YY)jhESRNLP%$duOvdtKcE9>8o8=2L*c+G7Ho<AsVZ|;jl
zU(hgKM>%xcwYwTCLZwvs(Nut1H`;^*hlR}O5Pa;(IT`~6wi-f{iFcFnt%IuS4zO`_
zkHFFqBjAv@8wa1TYp7kP7K3<Dl34lynHu_mqWLK>gh+7>3t2~FtY%n)F@HTGVa&HH
z!<aW>G2<EY--%y;Tr(77zANG=-Qu>XO1C(6ziPuK^tb32c_F?dz%$sl#$vFq{fQb-
zOPu=i#TPaV3XodU!=Rgf7<>b}Lj5oZ*LM+h3><B24D3@XduO6j*<VYQF(7Q%uwo+H
zOM$o3;Y+Y4*XU&mE@U$XbrwAYvkIv{)dDS}RIxxam&BuC=m?$+$6%C@9bEd8`N3om
zHEYgWt4Lg1vd{)_$Iut5Z955l?oO;dRf7ok6kY&RCSldJ63j5^9E%SVsa8m??`!kW
zSA;QAn8<IZdvrVV>$`q3-eAFR9p;jye77I)X__9h_YT?zJF|Vo^{|d{qk{NYPWf<-
zNw1~(^+}u<oYRq3H+-lh#I^Ci%Um$%hjIEQ*nn}>ChT%i00Z8;M(>~Hf~D1yNGPfj
ztCFo;*l>`w-L}})ieM)0B@2sEM8WtPC1zitnm1dK>tgfkp`w%z)}Fw69mf4S`>&f+
z`>*1yU`Cbep`2h&=W5zG>7P$RW;DMmIlP7OaBs~+=--Ns*v&LPwi|0VYbI8z#sBlF
znb^aSy9?$u6Sq`%&8C#LyC-f@g*@7sNXj>?4cgOVrlQ(%jbDn@_CKLhqAF`bkcVa^
zRuiZ9j7B*;A(05dV%|xL2#s9;gH}p@b!&ZhQIr4g<48UQ-BD--wLD^iuU)Uq%j)`7
z>x{G~qg^u+{PI5Pi6@z}gSN88tMkFv#E0aDn_o8#bH$U<*qmS*JDsuj#J))EiCi1e
zoAAW}-I0T`3dIsA_6b<wd@$PCmC~1}z^Xy7e%CUA%KQj~RlAI$9fEFjOMdTcUPW;p
zqy^RH>N^mX1d(+g8Rq=m_aS2Jw^xjNm5m5~+$4-vM9Mxy*?waji8ub8eZ=n+w4>ET
zvAf}BoPL48pSOAdzVNGCb7@WMt7qh*b6dJDf|PY*0tsREpk78sn0}V7Xx-0tLIZm`
zIQj}k?}IO3$itA#S7(J{iAhbi<SUQP`aT_bsoGAM$*MZ*9icKJ-L{?Xk?mYRm|x%Y
zlQG(2E}e&hsQtP2qT=7`op<>~$-4{MN7%`#+G`uM*EXTOo(6CEkijrD9dvR=3-jy4
zpuM6k&YAOdwy}yW-yLgFrABRIBe7Z-G;vpc$?&|^LPgYusKr6skw#N2hdsJ1ZZG{T
z#R}w%jZA4d4QQ{n8IE!kn_mx7sx|`yycS={f|OO8*t@uHCv!2a7ik}d1<!jsXnmyG
z#D4E@6KgL075VA(qPh585LDghYa6>&*v8_6e6&rdq0do~q3&0|iiT1(TO69rPqW=Z
zLv&C}bP7+ytE#79F^1@et%PQywU4I1R4IumhYSE+TWhX>Q@gVE1q|jV!9YFZnR^ti
z_8EGd)-5~+upKDr`OtrwGA{mrtafjwT*SLwH60*AvCPtTRCi&sIWUCPd`DR=#(b>I
z!I-KVA0C<aDE6$d1x5$-mcTtS7~2js<%4ZO_wCh#Q<YwQDZbpG&cv79jv{HjT4%r-
z2WHrV!n_ivRG!Ir`ykui+1HR^Xx>oKr&6{xQzYv%E#4}=9oQX7U|P)3b))$yG0tsK
zm9?0AcDfDbwR`AP4)rry(CYMMju5<_f!7!E4yL%Spl+eO>2b5(nA4#WZ$R<z`2~Eo
zp(X{wgbk-rB+`gMyy0o;7M`gS4Ge~R#Rp6@qez%?KI=8UtbHD)p0!V-oz;$22g&($
ztVz_ds!U4t^)}YZDb;6Bq6^%K&VhNemfBr?_r$fiW;wj*NeKv~o-}zDriGWOGhc^d
zQL1w(RnNjoKlRL^RIkRoq;}F8Cs=A<r8%YPc`{}ebrsB$5&rXJbc)+V@7BfR2foBx
zd1j2&6c>GPQ%spY-<$DFlCM35V){+0wUz3m`9X7(y^%@t1I(<|_7<2lpP?!)7t#DC
z%@-)nO_)w0odJkS(iwa=O`5158t`v>hW)3X-G#rU*|irPA4B6CKb5Vn#<5S(mg2YH
z<!jS^kvQVNNcSp8F#3z@M9~&Xqk&C(6SL&%K~UN1VXZnx&I7w^(Ju5`UxiYWgyhjk
z^sNh5=}v@`Z<~X<JLX@UUaKoIb1^OLQ{0y-M&%ryZKZn=A43)v@wF{6Cn-VmX%LH~
z+@a>Rn`t}gQ4mTFw1^`ekyf;UQYZw2x#VrZMt;|(VXj4lq_~#as^E@L$}$CIQK#$=
z5m{9!_zdnaa|wOpL<`&~0^1GRK-D!rK)S^(ib_Q(FQpV|H-v#gXJ(Ig{Ix!+QWSk*
z<?bpsHNm#ni^TSTz9n@WsnL8omDuzRkuu*$088OV`h|$zAdjn&hY}fLBYn~dW!hFs
z<-^|<HL3WoO*HB+muhnvv<)5Gk>NVMSu)xwe(Ak?5UT5GVUIQX_0=1p&5?c#)md3B
zcSZ_$!5p^iwVP^Bqjg=S+u?OB+JgVphtd9SL2wH~Enc%V);KXIS3gAB4FmlxnexIB
zKF;rp$A;qv|C|?9=TYG1>hZ{qI?SYeVX>YFD%SkP>79+iHE&J+6>CHVH{thjH9QB~
zeht5Uj2FN3MlarGvKPM;#|&Eh6oI>`^@62naidl<N#x^8d#n-K*n6oAzVUJzp#?qJ
zFkYudXfI&P<e%PSqHex<44c$2ULR3c-*_L~+c4e_jnJ-rqG7z78=-Al(J<bFc!$Qn
z%)?%7NNe?4L)t@Y8`3^$gm(Gc4dZ>*2+f3U=wFt11x-84z*tewH86FQlG$HPhmOD0
z&sXn0#oeIz942;Y`1+0d@xOPS%DV1#Nxdt_yh^{LReCV5^=rJgWy*Z<;XkAoUcZYv
z??wx~yXLG>-bliM6fHxlN05eNO??*UeawDpemAT64cGD$cic!Oo{~vM;;zj|{_^UL
z7_{|P;~PZBcU(XJ?+Y{siwks=DZ6SU^o;WwFishR1F_4N(0f469$I<Uf@>RN`-K5!
zaKy1_VI;j*eR*Rj$}`{HHi6?^j$KhZYJ;PTf5vuWcQt;Vvre49?Wt<M>sbmfZ|~ap
zrLk!9)M#Ae3>Dcz&D};CNzFP~WNj`Pt<Z!xVAPK6+o{>7s@Yem*}nyKIm~HxL0w#*
z3svyn>N@)EX?P=b=TUS=T)cHEUBSd%p^D{->KCA2NGwymVmal#BX+kHCH%-aSSy`j
zu@FpmO)yVVDVr1w9e}yp#-rXvzcG|$Mo{%lDB64>B~!|LA*bX1a-#Sfk2EiTbSe<-
zHxx^5(8=iNBg$)9Lv=C=7bR&*Mvp;P4s)7FC|z?%MugEf&uHzZ*lh|)e*nGQ^f#dr
zkcw~oCq?|GzKhgZi9cyV^)RIF#-1{`_*kTSbfo*{enlJE$9vZo?OFfAE9;7XVfixd
zbY`@|ch&m3LZd42zVBw-Q;!ZW-BEB!`Ayt)b9g;I)%=N5cIAY+LfymgG3p(g|4lPm
zxA$s~R2#4+7iR*V@rL^$46l126|5&G7-f;$M<Tb=EWb5QoAX25F^5PFN4j8KSHF#m
zAHTaCN?{06D396YF0i;Kw{vHQxa0Af^nSNhjQzL4Nhw^6NYyzQgKkzHANi9t64z7i
z@%Uu=mU6u4dOE7I`T%qXzVhsjUxh?*{%+e<eY(>x_4wFS%j)OQ35zS^UA8TFWx9Rm
zs2y+82O%iRJ|)VvT6en&b7Rw=k643rFfR^<P^w`QFDA!9*-%L6^S^dR9TnYHy#`&;
zP2=4xN-Dcqado^KN=$w4iey;5j3R~NGAg3c_L^}qx;>uaO_8*a8F1%m-1O2ftD_n7
zk17opKFZml_~&|jlW;VC{*?l;PK(a_-hFeZt6l9eYTr;-u$n?03R=6qdJtYxSN9{N
zH;aBDO_4(`KAoD=%JYjC3ob)_8jjCt4~y|RMHAR>znpD+mY`P_)lv>`(hpL&_MiM>
z<FTN1=+pIccJHa|D3i)kN<K_k`y9)JIQRD=7DbhQbn^Q*Mf{C>Hgyy#P`z4o(pPMR
zG993lX{}bK+eMk08mTAHi)t58r^-QN>-#ihfZ_;QAp4v)#kEsC;<)e9U$BRDw-own
zhgV;Xe@Mt<f|mEUr_Ux2C-Qb3D5{}+Hr6y3f*>)FM$*I}UJm{;17c_@qEPG1`GKeY
zN*UhL%5b|VLzDGKzpGs$>W`xuQGeRISx+hUHj1t~if`ste}W#Pdrwf%HtA?!+iK;S
z2Bja0e!2o5v!kS2C{6N>R-}DDlUSN6(yb_xI^P~kSLXLm(1!Z9nJZySk?fKGG}?6Z
zJAi4@*m*mZbrMWcMDCt0n@HtYyTG@3#))z?HP6!Tx#9c0N=p=8!}4J5#F@GDIgG=t
zF`SF3RtZg+PvLzj+<8>1<@cwkmeu=|S-iSNnZ>uO(`Y_Y$M{rAsdXgL5f3Y+EY;Ha
zr%0zMX<dbMTwYQ4>j4!BJ-X_S(=^A6Stj+Y1^E`$5wca*Sk#8}*(7x?_G!l$rDUFV
zG@rF(bZ4u!V<(h`8lV;WqLvr!pkPQPmNri1!^dcNR(%gTOZC&RPSNyIHEmJc?XYfu
zK}Mu|LZtipenp$a1hZRAFh8>y7F9iNj-<*bQg(2^L;0#FAt`+K;55%ac=DETn6YW;
zLf@6gRBVf>plOYEi1DGg9LCSpy2UT=xZ>Nn#jlUJ;@fYtT3L@CG25)MF%!p**k&CW
z{7Ez`uC-7m|Cz32b{}O{gO}1Nef2yL_6d36m=H&v;s@N;GwM0eHrsyWh*Kfj$-=2p
zoTE5P!5mONdoPY;+vDn_9bJ9R>KqQU16Tr*p_n*c#L|+!%0S;OtRLTAd=1oTr7L9o
zTu)H(=^$q)e#`<ET^&y={=632H5B?=@z-*3z0ny8Ymt!Bp9<QP_lq3#U*~6{pDTA&
z#lQXL{9asrq6lPxNcqxsTI5L|V6qff1r?tP%6kua*FG!ciTV~DFQf9~vyl_S@e>i+
zx2k3bb7z}%&~&V53q=qI8_=C`?TTw6U2!XPD}}ALmw7Q(3(aY@V1y4pxe^kj9COo^
zMS=s8wynYry<{f3N_pIR*CyAg>TfPVm)|<qwrfbe^U~s~?BY`vb4fOGG|#&q(P%?&
zf)C4Z`~Zb|*^SgbOU4`uTchIrFy_O{>N^K*H5ZRU#JRTJ=GXWChFoYJj&-}5WNRd5
zo;Mx6g-Y-^!irCYnoG#qF9pBp8jkOE&%kGFUxtbpOY0!p3R=R%TU--Yxkuu*e>EN1
zPeUR?8b8@Wg3Tqpv4$9FE_oDf3bVsGkI-IUd|q6fqabDRvEt8@P;q<~fYcoL1?@f1
z+!I#|qcGGa0<~F(^&hKQg!vKg$>S4KRp=qE?_K+=$6@w%ZPe=JZ11g8Icj5`w;6mS
zrnT@9BQ4Xw)~-pmp9EW_$|imq25fs3wj-Dv@fG@mQ9B@yxfcz`w*{*1#g=4q@y2E)
z9~FE9+b_wsevoZ-t_h#<cAcofeM`M$I|PdPzHX==+M*^4wBl1%bIHrdr1(_4xuiQ}
zT6`+fT)F^3P;H>I>LQZNrkYTMVT@D!eOi2RltS_8=Va9QuDFuwv4X`NS5gxuQUp&6
zR7d1Nzr7;z=;h0EsfXtx#8^iMMm4>lm2eKE7R0C&<N@$`Xsf1)!sQZ8l<i@yY}w!y
z`Md*!y7n80S~CS6T|r+F>{L*?ihwM2VG})JW0f%KilzBTpynD7+!Nc;GVzu=!6(9Q
zp)edz2st6{_2jR{oUhpC8mRyW;q}eu8#`5j%Fv-f8CrYFz?Cqn$QdxyJglZ;TY?I+
zsDs;Vs|nd=s~|_ro9O<qxH*Z4#itDB5}Z}w)SHIRozwv)u5jIq>x>H5Xy~_9u3;8;
z+!EJlm|3rO4ePv)6krYBaKaFyFCmvCfJL%lc&{eY-NEo(@4B@Dw-$V2g*$IG3>`}F
z8P9t6trZmB3_~1Rt@sG8UgjVK(YM(aS}`qeQ_8#5_AqnJE_2%|NEWtbROYB1QT6lZ
z;+yub|CfHQ>)t(IG~Y+v`C!2@*X(63+tT8nugDK8{*Tq!>P>Vew&x4i?vn?a$1RJh
zkJ`~VA91uHj+W}4-L(-M9~RGE#>^#akcRoe?f5@;;x61${<g_nayd#$zk1fJ_%tN;
zfEa=f{Kvg$DSjTV{tcS!%`e9-J9$8g+g?6#FS-EC2C8qk7<(b*mgh~xaK|l#+43zU
z(K!4n&O)~V@x(=r6Iby2-Oz^n-4awy2vwv!Za?%t?8X-gO+#Nr48<<0y&D2TP}~yt
zt;>WyQ-6yI!sB$5O3M;y_EOjE3fHL`oE)J`F2wGpwc9oa*GwkS)+JXW62200a+hS=
z9`%!=FWOn@ciTw7pC|(U2JN@75_zsbp0)FpUa}nv3FysmbYirri@cZ)+!I$}J~$lq
zOT981T&Ah+W2ni!_hJi%sRez19HP^u>IzqM=NcG@)+=4=7FrJ4DiD{|z(NqX=(aV_
z11~-;nM)o+J&I2o&84)Cc|&M{GLVFwe9e8plxn$<0J>Cyw@cNmpd?ONo$*jJ&Jr>7
z-$iaTV&1w9BL+quFgGeIoc%Bwe<>O>>Y!pNvKJ!+B7$Z`gF%Mnw)NGKm}-ho@S1Am
zNGXh@6nZ0ts2w$DkP*?GM7xwywYB?+ac5U|Jod*++_oid>nfLRVa-LNg6aTO@=B$=
zFfVVkpj~01hXvb9-(gV`z6JlL&w~~dbNx1%K2n|fx%N96+vNRNbL;)|!x~<{*iVEM
zSB3hV<>9N%<?$$8uq&S4lz_LivLKwW(76VDCa!!m$N7cJRNI2$peWCW{DS=lYE=Jb
ze=BSMQ8b&iJDOSH2JeYx)xgUDC4i{_dMK{qa!Z$R#>VdpT^hr7w2@sg?AS0F_|L;I
z|GpZ7fAy>_Z!!H9+!r4;%lpi9=OLbYb_s9QQ;y=3(%$Cm1CFR#5Yp$(Z<B9l_YoCO
zJ?q8Wx0hn10r1;p+{2^*DdnaoIeV1i7#N=|V&c{uoui(0<Co=03%InB%ZE98h2ret
zrsJG_t&gt6jpCM6X+D=+6!b4Hf6m!!gnrCT-*Q%?XFwhbPcMGOWT}u#GZF7eE`P|`
zvlQ<gZu*R~19}z_AN5I;?_k9gfTy1I=Uw^&zs+)nOV9Fgj6G(Ms|@TZgZ!R>Z8Vr_
z4D6r*5xf;s@*Tt@`mBJQPH<_7L3+?2zhhvp8{|(7?B4?an3#Ssm`Wubt6Juvyyt*P
zjIHMK27|Ph%a0q_uT-EHi3horNvz61)cYjUqDJ|9Uz5PtH-;kqagg+!46aIf5#j$0
zlHX{?P6f%!nz6^4nKm_JtD7OzQ+TE9H}IINK;6itMUr%g%iAP&zo8>z?-|;GP$VI2
zz9a*EO_C2uSj<t3O@gwI0)LfE4;Vd({-tU5M|Rt}^r$3#$>sMXR&MBo4rFKtLMatx
zp(F!cE6G(7TQ5<Jt%7op0*j0$cO&Jz20@>4=_N_}5q(TTTU!|W($EfsM~Q8PBm;d<
zlItY4OQIN`3d(mBxX5UF>VGIrs{1xk_b)`<%M5rO<-<Q#_x}s+jxjn_PG=>aG5UXB
z=h)>8Xi2o^AJRF{8&?%Dwv)>b8WeR{VvwFSNKca9*l3V{FtDu#3ad7leld6kDDqUs
z=pWTPHr|i)&N0Jhe0`8qN_uC#TuAt*L2_|3_IZ%}Z4j#ol0o?`2%*cGnf}$R(Q;fR
zziN<5d8b+~?<2YVhs!{pH^{3EiW+=N(S@e3)OskhijS^&f=k~Rq;*_=N@8Dd=&zLq
zA{-#jYJ&{aEy=4T(q)M8m_(G9X$*fXnJ}m|rTCYoNn?09mwq%zo4CAOV#hhg@M;4Q
zj!-#I7-XOiOY(Y&Es-e3GZImt(HJ`{nZ9nMoTR^A=g@!BZZ5Bt*e~3|*cOOWlD?-j
z3ndxovy!}1B3*_UuL{aGO7k1Zbn<^FO{)7}(MF58^p!z+mCK7Ic8KJ;%s_<QRCmmq
zK#L`LrNrh)6yqU@D9fqt?@OkAjntiV;-6a1);u^|zKnN9y6Q>_>nOae$r$FBXJt0W
zxC(U8O#N^8h_laW0FW=@R-LbfUB<3sFaMd6K<MPtl8nXMDWkl*6+14=-?w5_LGl7K
zTVs-6!T%QWZZmr^ME>5)o^B~GXvJ2xLb5yQ-*Ng^X2!pj^lvBqJ5K+~Lh+B*g{G0w
zZq64{LDUixy^QlB-W{}!T>h~I`mVe*gq5MkwqXA<$SXtG2Lk`eAg>Q$PfBs1&oRn7
zL)Z!<#d+5#9|~c|1U^rekB6|eay016f}-b!@CTX^<-2ASXJ0UJz1^JBS#F|~=e3}`
zN<(0(tQDx9wdBSisg<^HRs2D%y?)3&2wUIgLE*kM?50D4F80#e^3b@xa}9hCzj~2@
z&o`K{b%Kyd&R7e#9oqLnRTdk0-#U&KfC!WbB&*PoeNS_~nO|LM;DrV(y7jz+`aaCL
zSP8$+`xY8_DRoMf7cHDR-~?CJdeq)NzR>u=6$YFfNW}*BIB`*o+XvKfR@A7kVSLts
zhxV4<<Q%GICzn3rurlRZ>9qQZIGZ_tkINr(>0lFa+FmQqGw?+QSoVEskiR!zC5sYq
zM!%y&G79;JbTz+D9xjb(B#(L?a*^DdbpwY@sR#T+*+Af9J$@UbW%neH-#`8UM#Cr0
z6Yk>=ZZG#|W0bJ)&hm?#Www8mv*)Ry-cm<X%l7aLke}deN}>?v--Xbsue_VH>*O`K
zNx4;&tW^&g1OICIRnG3TtNjptIYbWQmq5PgJ|uUc2N>ubuDylZ{pj^PI8wTvO;%*$
z#n~u6uwz%eQ7M<p(hFRESe73%ykOX4lzzYsHY=8;1+uh3mOq!-r?UL5%xY*>KOs;t
zLF(pRtjiqoolNY`#8~<J?d?+J95$CafGA%S??jzokTgT0ZR!FpZ{q9`3SP%eXag*y
z8tjdt_?1_JdaHE5vZq|escrsAF}HKm5sn#0$E2(sz(buqiT1g(fxImCy4c>GWv|<x
zckYVtluMuC(&H4flFQiSzC-9yZu*t8Q~HchA5UJyH&H6$QZA6Excok6C?#W?x#<vR
zVmalzwo&UeS-Ou)If(cKmp|a_8RFT(P1u(2*Jq{W(~0D8qf{W>2^Uh^!kH-Oo7}WV
zJtxqzQOnk!ckR6Z-Shyz`bC5Eo<YVUbQdX(YJ&uV*sv{^Ot1LQ!BM<p&&A;TmS4UA
zOEiOwP4{Zz``lnUWnlj$)RUE(7xw*BJ~x-~j@W$O8@pF7Wk~lKOxQO+qUTWR(~DnD
z@$aVSg}ghhqNSS}i|&=P1@VW=SZ&M#vWClFa`q+(>Hs(Wz}YtqWj2U+zZ~KD(7}?>
zMPLF7>Ef2=FvUN^O^Z-meeu-%RNi}~Q(Qv-VeG$L28x<&Q|E&X2Gb`7CRRBfVTih6
zTy~Q;K+}^c7R_O5zrO+fJ_{*fT1USZlTy?D-c$BhxrB2R#$MvkN761X|Hg3u1411)
zl^fWcrpum>HCcc+AS?9*P#JfBpkJY1PnUCPh^zhj?>FD1%1*43wenrqd}FzCJnlfa
zG!I8oTt3Jdb~cRd=B8tueMP8ev}<z!<_=nw--f}4Jv6ZOTt;N9(y;;JChQpMn&P9m
zBemWC$ed%j68fl^OLOR8Ro=_l3M$mQ+yp)PS)=8{`R|oD7sbr$<`SmdeVk5#v2Ww1
z|8RDsQJz7($5n{(Jiq7}gM=dlI>42HZZgP465B@F>ZHLmU&2cuKs8Znb6m%W)tGlm
z4Dx*vUOY#HjfOV=;nFFCX@SJb^c<S(G4IgAw4BRO<PY&)ur1=!9g^E%f_)oKjs5db
z=c!^Wy`Vg4;`xe8cFAQhJ!4=`G>nhA`v1<nW9lYj#gSG@OH<4{sB8O)jNK!l)t?q;
z@nRNi>MR~>(*YeJuv_K(CHXX$PDs-GB#>_nW}q7-`G`2pWo(}$J#Ca~sW}!KO)sg(
zufF#Te?ZT$0B>Nf{|nYO*awHngV^PA8cRmk#eN?CX!!4B=^p=C!&|jMyaahJXNyU*
zA%!L=y?gk_@uB#aqlr`+=H!!#;PRpPrpspXob`OvvG)8)Nq(V&^tyB_@a0DN=?>Bs
zqYQj$ki4XWv^t3JvS4{$2WeUGXF>2h6)LaqAgv80h83;l*E&e=w5CW;hsp1BklqL*
zd{JBZ$M(`oZSN<B6ST40-2wlwJ61FSod*TC>pPYwD0^c?Cw1T#b<h0Oz}<$vb0m(f
z#M2Uv2dzGQ-FT-iS&XgX@*X42qN|Opp7;Gi;<!cHXJp55A*mhW2tD^Vt0%fei;R^m
zUd0Jo2=x-2QJE7kJ@I6@!XQ0v81AiXJ?>-M$4PS~n08{8<2Wi_DoHpZT`oz_NH_;;
za9(r?Z{7a^`LN7!Ch()o>gjkusC(oyl=t1kr6QS&t?D`hP8axlM(H~vKWUU#%92Z#
z*UHjzS$;!iuM*>C8BL?lqMmi+m&Nv_{iXDs0o&}p&l~sy2Kj&ihxt>zLZ>QXLxiKT
zXK04-^HQC$HtZ^Y&86iuP<{}zGv;LFJl$_jZggDwjKlCq8F#zaU<0PyCL?Q+X`60X
z@AZ?nb4L5B&0gx=pnk&H3{Y_<FXH--b)<<?-)rPT16xW_e(`e80{1S?QbEPBoZt@Y
zCKq#%afwY?iHmI1x(%JF$H|$@F1tAvN=oF5?vh{OY!R1nScsE=chzGA#1B*A<C_5X
zDPM494+=6Eu$2SDE&~|s&l}j&s#sNq9blNMt+~$1(5jo9igNx-JtINfP+FS~lap|`
zH<LNl5<2DQIIWbAa<+uaZ*lg9R#7E3UQ(WP3oh^9)vDx_aRdT}^#(B9`iOxo&`PK<
zV81&lQ9FmA5;n<z653J13ibE`aj&4G$eZM4oa_L;63TTWr$sa^pOpf)zl&DXSj7Aj
zTW&5tC-(2?e!r>VY7$s#BMJN{*J6INR>n1IL6O7;2$sudL=rg2ILs$&J9uv?&XL4M
zkwl?Hr9eW5`4pHK2;%}IVZMsyhQaz4Z*h{#4;UD3(nLSfdxh@$|MfVTCBG(G8^)bj
zneODcURT7_)Hs<%;{<ar#>w+M@jS-KEO~)o*h>saFBsT!YD1joIGG_Y=j=f)W9&V~
z<x0-}t(CBeaWaF(2^cU=9^<!YeGq*ktch_lLoPB9LnSdJJ_a@5E#U=>lUXusd7kC+
ziw4;B$jc3Mn^lS<HZ{@n87H%3baEttPL3qd$v@{e>pJ<Lkc9s@5o@uF<OoJbf`gPU
zfIA9bfB#lDh&zVcJmHa8yD=7h-hSWo{L{Zk_D!#UtDA7#h$CSo{ZKNoD#v8F3>GTV
zK#XSCD)owy;hinNFR_&zwmBTfac(1DYask7i2_&CHt7V6b&T3Pjk|#XSa*(B()Gdn
z%T{)SO4sB4<m*_xO4s9mN;=pE^I6j`VQe11@~2?_p+Q>FoF6yHh0UesB<b^DUMb0s
z2lG!Q$sNp3O7g40(j!J`XLJ6FQQp>^Rv7Oz=ha4eO>^l1S*i=>&&cwgV7^|K)->Y>
zWcf(2^gT|i;VBB14>o7_2V-(&pEQ?2`Kmc;1)sWktp7WerJlDPC~xL46zPoVT-;;f
z_*JO!KQSP<H})i>)wb2+z2t#xluAD*&hF&NnOE*^#$Pi?bAmZe`42XeT-db-^JS9!
zZZLmKk~Rd>0{Yot>9i!h9n2RQ<;}tTWuvs98Q+O(;$Z2hvDg3)Zh~<Y-ApEWGx_Ic
ztT=cC&i;dm;B6`zvsgnxfzNLLw0bavI};(ErszI>UEg>0ecglO{<Lj8>{9sMWP7)Q
zG#D<p_u$M3GbfF|bA)4E>8CSrPuU$yK2gT=!Tohm_~r6K&TeaeAIDfhGFVI~^=*Rg
z&)@PQ#2?=t@5HE#4G2w@%0Hz)R1%Wi4SZy&;opXNp{&mMy0k2m{fhlxD644xjuD>v
zmhw+#e!7)>*v#jfQRvsqmmzeI8DF0H)*M_I%I1dRBhG6>iAQOUzb4Ik-o1n;ZZNW+
z_zsS}-yx|#JdYb`AGppa1Am|HO+OMS)vF7?>>6C<a&fuH#d+5Te)(b5zEv$M;!WgZ
zKIVr)mWHzxW*OhF``r97hv$>l^1d*>w~hQ(7(Yh4{lc)$AY;c1Q@^m_BVnvI3^F(!
z)&bNP!$DmWE&=t(;4exSefb&w8Gk}z4@>PupEJefZ{;*W3tvq8E9l(x71MKJ?4yuH
zD9+QZWZ(x|MdMP@Oz0`|Oq|!XCiMB%Fw1zYbrjJ0HrFurc9=vc3>-S%1KljH#?ImE
z+CG+ymmUpz%*^JQYLH%aD+&0It$^NVCiDd}c9%$|Jw<)g_@n$L3}Q?t@Xo+<=1}18
zYT=h4{Fq^<@!uhAPqQ5ee?BA>_<JEL|M`U17~VI&8Nxnk_70^V5(@lXJ^xRJUB*2j
z?8|1m5&l+4DB%<?O6Whj8u<P62*Q2W3g`C!fwc$DLwk=DhI3q=V`Oi0d6|(fHpq*O
ze6xXY7}3G3ZVN3mo-)e#J!7q#lk`JL-@U}2Hhd<r0}_5k4z%B=hY?@D=FsDM9j?bc
zIvl)uT+i#l6}zVCcr$YW?^@N8A2djdTJck`pKK{@kfev3^UoytKy!XdlD=t4(^gT4
z^tMrYB7|2N<r5+Nv{72!k}sC!!y(c}S$Zs(e<91eTk>CI>4Ro`Ns#=WNm>^)6ZjUI
z*>*IOfi8lHQ!x7^xD=FwEr|l5iB*VdXZ80f&;PM?h~v(#2b=SM8>G$6_<qdS&7>zJ
zX|D+@5P5D3z8{U)oc}1vUj$1}8KpB=T^i-R&H1NB>Ej@APSsp`OnwT+^ZY$BS=|*R
z1D)SYu4~4AYX&{es+$u<Yc0{An_6!)MgM*M|6J>gbA<=iA>Ngek7h;Nv0M50-5gWK
zk9@wg_+qv}b_XqJ$99Lv@VHyPK%Ni7<j*hWAB4-tFXl&S%6*{iWeDARk&Us3E~bdf
zF9!ANi!Zsa9V=@G)T{sg>h$aR<)u8a)QB72*Z3DkDB);$prdf_X_SFd9mSetJ?A)S
z+rc?5mC4TMavZ&VOQ=>@A&Zar*R8gMv%R6RE1dl&bRLJt-9~;qoR^2mRbl*DT8OL<
z3j_K4u;AyySy8wI{1Fn%%k*!(@b3x7BBi!1MbnZOYo6;r;@`Eb2xH%v<+?ETV(0|m
z3tP(v!}ud@<V|6GB`tY&w~;_TK<JV%Lf6rfXHQu0S7Gcs%Ku;CMAZ_;d=l~;-;VLk
zelWnM7XB7Dl=0UM46~E)cD)3PlSBN=;A5@WyQaf<sqllAqk%s|YlT-^^#yv8Ok#<%
z;~f4k@y^b9c-zy$;FPpSe%{Q!ZGHg4-rFh+_-nLcMPg#%G2i%$eA>+ZW%>r;E6icQ
z9}s4?2q*rZ42O-6w`4yx+lufVAz{E*v{d=eC;Uf4k-VxUdn_1hQTBDnMZhcd{KeQ-
zz1EV=4SpBlM?%7Yi*U3@Yi=3<QzTwyz(NG~Cd#AIA2sl&8l$f@@D09n+(P{W1)kRa
ze$F1I9)-%&-AhNQfZwC03~8A9W#d#Bs|O0lyxaljE9zMb@ZPY1)ad7f{|;VZBPmBn
z!<4dU_rzou)v*VCh2~$9{E3m_<tD~{mIlm|q@707S4M`}-Fs7@-S@+$?W#x6Z9bM-
zel1D&VGnC$4^YHMja@(xyMbdyQ=R`iL2-Nt9Twdv<Bh3DD5ouw^pjC4H_GoA*+Z1T
zvqmDUGD^P~r40iAkjTf4rUzsu3>B1;E4B)-<Gj2ZV|U6g%VbWm!zgbt9OFenQoT`r
zO=cx@y|PG_UJ=%uc)v+DJ%(2?WC<}Eq!rEkbVgeF@<}6JUVG56!-zg3KLg`WDnO}>
z9xkn<1b4`$kI5udLJW}#wY6qD(Wxh1qG0bCuliD=LOd<ArLw$AW-k&au6uy`@eJj?
zu7+Jc`$1~?piz2>GJDGy3Um)_#EtBPQ7*v^6Or$i3H7k6c|rzVQ0}|sM`dZ1;a$VK
zvb3Hu+bv7QLDE54E)8P8$@0P=Hjk$AM}i1_DM&&*Z&GSnjoawon1M~EB)=8J4jE5E
z;ZQe@8goR|oaE~=;Q*(%RYX{esd9-Cw@uWkC@y9je>-M>zmFX=;`{i;Zai8^TaSmd
zmwGZX-5IKc!QYQ{0&es8|JLE*-A0SomL4@gbhzz%(Qp;yMLNUMcLKl3tBnM$bKe{J
ztvXsgZ`lv^yg{=)hM+@d(%JY^Tt;K;RU1P@ny49MQKY-b?h$7uu&Me)AIT@ByPJsQ
zlhQ1*e#NlEdJxu}RQ3+sd?S#J9QM?bIONy5*dbvfPr5et1<qHIg}uM7UCH^Yest)W
zD2RuBYUolT;T#lc<K4qgB`6;GTZtVdLX9A3`6%NMW9q6^;QP+d@;8HoBVfkfkR+h6
zpTRB}e5WM#Un1lE5uh5kGLC6H2cG}?5)ki!TVY?k5tsdVyzhl;?}yjdw*#GisVEh$
zww9ugx_y9m@$ufQhh_zB^V{|HmDin}w&ci2#0)$E2?Qh%kU&5J0SN>o5RgDX0s#pG
zBoL55Kmq{?1SAlUKtKWk2?Qh%kU&5J0SN>o5RgDX0s#pGBoL55Kmq{?1SAlUKtKWk
z2?Qh%kU&5J0SN>o5RgDX0s#pGBoL55Kmq{?1SAlUKtKWk2?Qh%kU&5J0SN>o5RgDX
z0s#pGBoL55Kmq{?1SAlUKtKWk2?Qh%kU&5J0SN>o5RgDX0s#s9`4T8R7R@G?D&N-n
z^HUF`7?40f0s#pGBoL55Kmq{?1SAlUKtKWk2?Qh%kU&5J0SWv)BoI1p1nUVf0)Fq4
z{NM<d3P=as3CIJ?1k45$0ZIWbKsjImfWj65wC6G4&j4NktOl$HYys>9>;)VG90eQ)
z)Bz~$4B%Xk|98^Q6`#VjZ>OJ6+(4Xw1OgHWNFX4A^Ou08ll?h@LBLO11)fGEke)Ve
zdQwtiZentNpI%YDlhe~#Vq%VCdRng2k&~E`W6y9Tre&sNF%j|hUQueC(K8aqtFdCz
z?YX&*T<|438slU+SsBwEnU-lYEpcggI7VA$IC65+vNA1wdq+m%_u80gVy=C<W3WYy
zHzX}HJI`rJNlSNJYZ>Cmbf!6HS~5`(_%ib{ra5vfSt%BKa&nF%H`g*P&6#_xiCG#v
zLsGJGGVIQ4Eq7~$awN~T-0jG;PfK^qHZc<$o0V_LL&+(P#2JnxXI72{1$E@4CFNSc
zZAr??$hJGvrlqB$1o>&sRLkVF^t8+Z%f!sI327M?$Rx*}Gn48-(VeLdVne2uY&#@p
zhX^SH%U~*>-D2rw$#JGzGP05#=~P*ZJtxOL(?aYBPx1{<vV$?#i8L}G0ujk#nMQHc
zGE7U)O1i^>Z2DO&5#B0VvhtiHK6`q;eP(VqO59>eZ;UT$z&ZJnb$rR_5;<wp@|=!j
z%GGj9W|q^Eo0pxPl|!VN4(F{@%?uq&h9g5XBMPC(M^{j<j3TnKo#+tu^lqBCkWdaK
zq>HZBD*}x&EiKcI#!9oNTe2YZocy$0M>j=|T0TlM>)N5wJRFoqk`ScIAle^7PeyX6
zprfbKBLoFamWwuXsIs*T6rB$pBiW(0p#@Kdy}%OH$ESaa&g5;cT*RiBYTSNji5oQl
zk*Q9O0((Ywx<eZyDLIbh-VlR@kVNWB$TG>2V=}RvY1E%=<HwI1Zy9Wf$;wMlwop@L
zWn&C_hn9tPNn)eM4j+d|NjVO5^UUcMb+8S#c=%PRD-9&l@ie)pvzmgZU-z^$=(r7|
z`1O4?f)G$Y>RUba?QYUaDZ<fdn~b1!H#D7AeRVkcbX8A+4LTR3r%A-OlZhdP&@Rb(
z*`}qZJEo%#Qgw3E?m}N_Ts>Jb@^YP)X%753^Brh~D2qKa*(+nxbQWh;mL=VuGaX&2
zOJtwP7AEA_kMir)OV<g78bXewQD;DddekauXwpWOG>5~1pUS2_M#_i0y>p$(iRoF>
z(~=USq6YNqZBI`}j7G!rGIP_WXQFqBIJzjP8)?QwB&CFD`Ar-<YQm_vYt-ZvU++nz
zJF_y;p>mbjYS-$LYe_?wwpd7QSR#N}EHPuQCr3Pk(M1XI6j+qgVzG^lRwCekQ*okW
zW5;We8pKf*d_<RIOLA6zrZdYD+3gxCh{X~co#07)FzHXwJo#&US9{q6Q@3lFBQyCL
zX3t4VO><)M$b(`SpD>2zCQl_(@-mZ1v#G-tvdif+ZH6TRE^0ygG;?}4bapUfe)P^l
zX}L=KSu8W`P;;2D5Ggk=-3cyTG)kvyx+8PCGqroaUQyl>Qe#ZR^qeV*O8O&><Qj=y
zM!Bjy;7HHP$`)}j|0okqjz}~$ZF*|2v~FlC(T^<R$xlU}>)ItUYI0YFU>SO?TCRw+
z?)`f7)d~PlH_PCmmV!<cxf8^!=3%jjG=$R5r8JO0W*&7$@>rmMl0`WbKl!MDicgi2
zA_pQ-urd%-xl*UcJnK}aDa)v_qY~m1#c0xmO+{%Cr$H15L+ibk@zHU^q6Q>R=#osG
z#h2bsBV!urm7Qaso?*8*bL^S9>6kAPvr<yPVbPWp=<FU@`jkxHpndxH*Mu0UiZJpI
zKAo5%7b*(ntJU@|&z3T@STIh=X-qy!?^G3mM>etJD84cd{YRn2fA}(rixE679{+zI
zkD@IUJ#o%_L@uhL@?%lzhcb+!NPdCZva+dik5bA_I`2HoU>n;=Hd+}bOdtj5R|YL`
z{Dg$218=l7lB|WPLsA<JloU-5%A}V_YjEV|UvmG-S}e|)*-(z-;u53BkB`0yT18p<
zMhJz}CAk|Z%?7FHG_Dx7$U7-36H8(&hmjUC_NEABqs%3YbWWeiofvwYC9<GPWWUKY
zZqW;A+@D9;qkPn;rbM%~x@PBOC1KkULA?jRD2p`lKnp41Lr@G=xk0majqIxCtBd0!
z919pIB{30^K2wt?IU`ZbRcOl;=#)H%X9=LpS-x6M8PgDA8sr0>bo(@HF(BqnVllxw
zQG#liuR_xib=s`)@v7=GuSUzTXOmV#?Zl(gYN&ldr$4B;B0I63Oify+xoFN2%O6$i
zM^F{IdNf-%4~vF1t$Nf|h*}K~qtHOehSmkT=0ZR1sR*A6B~%U~(X!fGOrcbi5{e$-
z4H1hRguwL@h0Xx66N~Jmr$Q?TDrH2E81$fE737Vk5xYip^%8{!Kuq*KFHwwqf1()i
z3XzFS@J}df>WA7ki26;o*k26R`es9lHW(<Ce0!SHl7~Gzmc?ngSl%Q$lBYW&P-}G}
zKzELy#oSN}%H56j%$X(&DH=RtA%-D=aUJ2z!nuRfG2M|9p)E<3e7dO#Q8Cj}8Yy6e
zHXM}>&`5?NH!ZUU1C~l67DHM(v<f1kx_TiE(|2+wY9TERRq2Rf?1|@91X{F4v!Z%X
zc49qAD@amRY|baqEO=iuiv<wA4p86+mGBSLg-^5RiuF0IDhCfvoRBE?bq?lB*Zc5W
z><xHG#pdKCIW1!+ju|6%d^7CnX~}*u?M{C}HU@%!EG*WrFY=F>OKRAUm>7psr|fil
zk|WWcSKt?j5$?$G&(M(rq4`BrlklS^Wo6IwBjx5zLoNM?w7A3eo?#{$JlIi?<PfJ4
zig%hlInhgEIP999nU|PUPyj(EVp>Yd%gJ$MqV#l_km$(C$;xRuPF|)imevMoS-FD;
zC#5^=In@5}C8BK{NIoucdQMh;Vt!UmGHsr8O>&la*u7;XVN;L2M~WT$OWL@`u=sHk
zMonf)jZ*Sx%c2&w>9Xod+GL%5>eKyCOp7t9MLJ1gLSiNzt)-(sC8A=E=~>w7dJx*+
zr)1@!1LEm<#Kt-U+5^G?A%K1WPg<jJlp+MHb-5JuJFS1wZhTr^%HY8TxzioaOp9ns
zY;)|%bV4G|_z;8gQO1rZK5}>Dq@?3eF$pJpNi&>-2jeU#QQ4nG&|XT{bWQT6Wl}dx
zcQ_rEq*R<DCea}x9rP%fo`p{gQyd3?GuLrv9`!~qW0QPMRL?IyIw3ka4sM-^P|S`3
z6p9vs3QZj5DqWu0nSC0|VfG$$4rT8#jpeg^5a1=e2mYq9Y}zW%NXv2NA&Cr!Gc}7e
zAP!To#ZvOc*!1YIru324n|(PHt-#poCu7*kr7^4wZoj8uSQXqlz#-6P!9N*b0Zaug
z^obZY5N<eN8EAXqU->uy?i>IEJ^hgwmb@^A#lk%fSOQoHSO{9b#Yh9NAO3cL?Vz1l
z6vK7`rhr}sH~C=zTq|H5piA%WV^YwE<n$PpcSj6s0oZXn_|jt7OZFJn0r1+?7<MOM
zNh0EBT-7D{sxC8Gmyv_J#3}y=cbUKr_lRL<y2r4)0RsW;J9!}#{+GIW{S-FK&rh^L
zpdE;aVPgP#{<^M8y0ib`OV`Kggs^M7#IRm~cRR<hNdPUJ=o+rMN3M)vF9I~b-p%u)
zcYvSj<=etEuU%N5sC)x$02l%&Sc7(io4z)NMZAeNCU_mPhX2gE7*+u&0F;3ifp`Of
z??u>3z^T`e4*YXoieWtgMu7F7F>E#5elMa8;ch1YZ7Td*R>rVYfEAGN0>a@kz*2-c
z0hP;<4*Xi5$SaOv@7x!|MgxKYHx{AYX2!5J1u<+e;8cDL8v$slPrPl7VHwfj8y3Tk
z0k&V~h3PRdY!5(ByDrw(PhqP;8*D>;0s6RohAZhVg{!CQ@q&>t>>s00zR@x4e!vd^
zEu82YuDNB`$FP=T8qz6zm>+#2>PGc~1U>p(Xm2q^C<~s%B$|aWZHQYVozfi>lNgh5
zQ@o7<89On~HXelmnlLI(kYdJ-855l#(7179Z3)riZ=&Eh+k^?xBWx3pW8uAkdQJ1>
zW@Fl5*-%wZmXzttNoTkXapa&}`S@>7&rY?o<h1E&PG~%w1F{0eV^7CXDx02T&rVgR
zVp?2?30vpKlF*49#ae{IX$y^2n0i0Oa%bX#E(7-}Visq^a<cBg;T*P)8Mq5!!vz)h
z6f|wkqyxsBG{+1q0^*ejo{(HD5pq+~5Hd0Ij!c}3D$|`dx9RmT-4Xb&xAY^kF`lNz
zsh)4};QueLB^mAAS&BU!t>VPQn8#@8kb-$Ko#hG~UOY{%t$z3Vi!n^j8FWL26@-{o
z(f(MT=BCYXq>H=C2I2M;T4Xp=vCO13j-Bp_=$r)$2%IT&WnE1T)1-R{Ix0tGtWl6Q
zuBg-%Gi{RdQ|-=(ZiBJ2V{AlR0vkCYfkj`BfAN4gKn%bJhz5)$zb%1{A{yM$aM=hJ
z$KbG$Y=Us3+4U+Guex!n8>6~5)s0r&v7T_7NMV#Gp5h;^`g=u2_37KM|A4Cp4r0A}
z6ioJd?bDKy9VyYnVq$H0g|D$NZ(J=F^V7>TOS9-W7LVd$iD;k6;<AL3kmtxH?~RV+
zOa)6wMKcj;cupEQ6YN-`3nVX-xENR{IzvQ?LlM|$duAT4eb{ivv>buN(Uk;?hF(f%
zaY$u!UZw;8(r2>hyy>`!ViT~janL<F8;3h@a>r)PPzbS(Bn3gLlp+$yp`<7gN`sOh
ze&Qr91_suJWw5L8KUw^ri8kwkRvV1}apFH|PKW?L#^S~Q2^a^Nh;L^UJC0@Pd<kNV
z<a$DH#3)HdIQC^8S^`T&tQ;L>IDBcI@CiuSDPm}OC^>3*G4uyzBr2(spHgH@Nr$0l
zPzsEVhMS2HJJP4J4o5j?f$OEjiLfN_QysHKInsd>oj67#E|p%v(giIVwCR9ck;ept
zW&?9Tj??g;Hh|+;5-3?7|5)HNd}74Hm*hiH%Bq!7DFLOWlu9d!Rt}<5DX6ZLzm_Ls
zN?wd9IUwLHPhEd2JK+aJ(*qk|WdsyY!_VaszY#o*K~w1v52Z^yJ=Oe(M)9?Dv~p?X
z@h`jHuf@^xXyw*u<PxoHpq0(=g9`YGUZR43`1$x7OZQxS=fk6w>s)E+!_Sp2g(r>}
zGj3S)m_!y~&&<l4nUR%;T`z2R#9FBv8y!t1FYK0EnP&}8M-(%h;*OIpDw$a5z~V?*
zya^Ig>ZR=$ovC@5chEg1QV^G;xD8OR2E9Skp$L<`cc&te97hVwlW0zZ^24PQU6qS~
zv;vlt&TwkZpx<Esg!@Qs!lt>qOL{Wv-McrNo}M+$F1EbN`B+v?uH_ELOjwFgVbsuM
zM`MAEv3<8#S=JN<Ho#4CSlJ~hR(3Ps#84|cINi!7C0kial9hc12u_55s+D~J_;#9=
zJ#dqinZ{e$!{e;%p&P91`Y~3v31EQ#KF~F|Yoe8%3tqk6%Jw49pj5;ijXc29W|HDw
zeWR5TYyn(5%F5~y@0#nZEEBK>__HyJOL*UC1-8Kb68^VQj(NkaEM|n2Z5?T464Lz^
zG>RJ%Yh~$HE4y<s!U25%9RW`PIzMY=?x+7e=!x{EEW_A)4thX`7d&reD*$HzotInL
z9Kezl4f73tL7`QkOr5uQA$hZvX+ZRdcf6p*)50~E=$LYou?KJhp<@l0jbXWE$NJBi
z%qn(SSr5Q|)g@em$tteJ(dgu^0xbUc{NTI2R@M|O+pmPZi?qH6P`rWzR(AO(jq|ib
z809+>;nn+;IBk$d4*WylW~nrNeiUEt*W=s4cRoNo{_z@1=eH)(yY*nxWzeVNk6&_u
zd|Em+pIX@lz(N4g?tnW$#kDwkH%u4y;vwh=HUHyq=Y4HurT<YNU56LcSlL8?7S@#8
z2XUIK@v5rN9p68lM;hU|wGo;>Ut|8x;EP2arl>%;9%{d`G6FsA?}Agg6eB5dM9ZdS
zWu=RM4lJ7K(3a65EKAPHgW(QN12E)O9H+xru_q=9H>%G-rd@3*3DH4<hobk0M7%+i
zBvL^PpENv_+*BA>d7~@d8Cf_!$fx2ZI+a3+WIXwaataa-uhVeS-nS1^u>t)wjPgsh
zr>BT&!Yl>{A4sroA0UlC10Ns3S|CVsDON0KM!2KkHiJuWgG!sEx*)MzfCuT^VBph0
zqx3YFXqlkNI+tip&`dg)X!nBFQs)9?<)BGAmjhn_S_s@H;S!$#(Acva;ZzUJrF2$;
zMtNv1g}<q$qq!il&7if`xkURT&&NoQWT3f})<Mu(>0F{U_8dbzDyQZ)2mT#s`gS3{
zlb}(UR$t1GFCD?!=v->Ae=JgDs<|MsaKs~C%_Z99Dot~V76BTyo8}U&FKARg&80RO
z2%6rdc+o0NbBQL-&(zB>T*-Mc^<d3=W9oCvtnexGwSw!9tcFmh?`aW9C<7`7*WS5;
ze633N<fKq7*DA@75w*jfp-)pKoi$OgD+Tc3&r%c9>ZwFgspprTmV~GaE*+K9dCnb4
zJR0@<64YXo@bQpdn6+5x51K0i@XrpYdQ$15n)@C6)K8`Xeg;lsL~~m_rHsp5(Aohf
zJ<u8MaJX7n8t^;Rcm;5y;C}%wjma#)IyG#&8g^O@OGa35g%YnF+&=JM50}P|eJuOO
zP-dUN@XyZv@egKCX84!MBD%4p3>c{-WwCo$@+5ZEP?n4%UkBaZVT+UOVBJ}Ax=LWZ
zS@H~=kT}M%+lDen7Q2l(?qoxU;z*ZWi~mk`ElZ!kh71|XFl*5NTzFWzlMP`Rqgbz@
zEMpAoj{j+_7t2Uz85uAPW|=siaO5L1obhxV$}lfr4(Z4;^NGx|#<N*NSymRCHH)G5
z&tlnQSdXDBJDv4l+2FsnJIl^yJ>bcOhuxXSu46g4T^h=ACa`N!s+<g*;^gE4$BcKE
z1E+y3_b!Gx3>UG}Gs$be3leJj>HPEv))hcHl%PBCUI5aw<i84dA6<BV-~-igiZfW}
zr}#n8Ekkwjt-xc{_!MpfK2r4)|7hTG016|B2R;Enx`V=}08a!EPGAR~3?My5{^{tu
zcc|gSp8-5u=g$G22hh?l0DiYFd^YexU3f9@`*nU7@G=19MQKQ=-;9Oc^d3am0sze|
z6ut=f5`dQ9<G`QP`JV>944|d=Jn(<&!dC)+S?7Nh_!@u~e=TrL9+bzM@NWPRPH`%M
zZw3h65C0C}JJoQC^C568J&OMk{2v1dC)fx4QvlV6{GS0o0?_Jn6!_OV|1sd-04OfS
z`40FGy6_)?pVEb&2L3BRlNWyma|b{xe>31(d`k0nw694Gr#LNvhXN>!(r5#`tuDMB
z@XG*N`d0w&1klRY8F*KKR-a^~-yMFMODRqt;Cg?5_y+>C{uu4&2g_L>9Q04m&xndt
z-`o;j9OT28CIe@>i8!E0OvbA+SS@;jJhWBcTUi|OTXM)^D+6yY!Bhm7^WuG_Ny-KN
z4S5baC=oU!;=BY#iL|_h2`3K!)t9ikWK$t6crQx1M9R)}<Rxd}T!!x9gb@mErkq(x
zS?Qjazq%y%rg{EsJg`uP#pYcOiyF7?XDf4_#@-h|cxSjr;p(9$Xv=irQw`B<tO~1D
zcO~3qfTe&kDVk9nf`uxqG)A*zK&Tvz3;JkQ4SYL6P&7*iP<oWs5a9kmbbXi}*W!jZ
z!l#7=BaHno!xq%}e-k<*|Nl)Gf<8fQyhL@W4auLUx>|n<xZbh#XUpOQWPL|)G|K@T
zY8K7D1e^e9`J4h?ulk!IPAfoLKzjhixe{&^;5tAYU<zOu;_q)B&77ua77Hi=9s+j>
z;GU3Zc1_D@mI;^(SOItka0YN?E8IN-asjUcz6P{3N3%r0Jir>je*nEhquDcn@Yd1n
zX25fRi`qc9Anm^bZbRD7he0k#KcpLU8DKkr@F9RR5xx)$+In61$uZD1anZ~II01Z*
z>L>cEplu;Kz%VwNRlv;#5IuApY*9fQ2)7dMR{-)8-TzUH9TZy##YRFgf>6vK6iW%k
zf<m#8P;4p`I||ia!aqqL|J0S3TRCpj;Yx7R;aU(Q2QKXy3*cT1`aN)IPA-9aBm8sW
zhQdD|F3r7<zy+Btg<A+$d*a8B8k;aY(Kb0A79nF35@Sb=7?m&q`%`f%i2DN84N)WL
zC8lm{EOrW`GE<1xk{iw5yh8!5;wN&vG%aiuX!BKiHrxp+ezodq@h-%Tyi>{VWVYh&
zg1a10sQTkom(sp5y<yq3JPUPo(P&j!O~=>bv{mC|XGXJCfJngi85l2sM*u`CgiG;<
ztNGjDr?g?f<dNTIghc}Md1^S(&-S1-(lYS^Ic?W|y*rwXJO@<FLSOfTbMc&SIHh~O
zaUW9SR-wG-dT1?5>v39R(wd6Su4vy%d*?7fTR=O&rGWN;D*zn<R|5V4hyZj4^a5N3
zpgnUx03Iu2h1bCaRO0grpGRLb>FXz7mNpHcKzh*K75P%%k7TU*lhMrjgaU=YZ2<6I
zXOGEBTK>RC*S)rVsykxt*6V(m`BZ#Z?4Ik4r)NKLQLlwV`rJHXBKej4EMT%)8LI+R
z04V<^p2DiDXKs#;xj0i^vu54H!+-qwx*BQRz_>mgB7Yv4f8WhR-p;-E@VK^lO>ndI
zuKkN&{b=cszROp9eC1E01`S<a7yGOExjs)UF8eU}&0D&}WUWk&2-;3!J<D@KEnjD=
z66q$zwa!!AIhz&t_EW+wEa^=`VY}KS3Abe5V&OX8f1g}SVufKC-0B%4uO|1Ig_mZ)
zwSKiU@)@}EFW<8M6S)2U@#7sKF-)yLtJq(9W4{?Nq8mFsV<U_Thc1|Ubn=lHYuTED
z4llQjjsNb8PmW%Cee6RY#|3?OqA-^F%O!x>fU`ZSRf}Q>!@Slm8c+QFBQ#XF<8}Ut
zz;D#~Zw7v=&Tj{<=TCxP&z}Ono<9wKJ-<)J7vQ1%^$+E*e=_|1*?xYC%K-*}HU?=f
zp|d6$bDaQJ18xG$2h;#&f?*mM4uWAQ4jI~^XHCRJl!3vy34`z|8)M(&pvtla<F^ZE
zQJ-=)tlq$K4;a~+{mod!t0C<0+;Aoj?a02^)}MWCypiqLS;kiF{*ujnGMjhHPB1*v
z>K*C5doBseDF3Yaz>rhs=N|p!lEcq^(CxnKo{LHRDmUXu=SyBeQN;6qz5L(I9l?GA
za5v5k0pS1(;J5nvE2x6>O_($F^<sPyPP&oS1=MiVRv~B$YCkK05DOfV39Stbk|!#B
z3cZ1g$d#){coY<+SvUo2h+9XnIe-%2C2-3C^jP4I1at<BQEBmT6I6UM+^K*9z!X3-
zU>1O$Y`9Jp7X<v95C0NCHu7--76M-iC;&bSaIPnN%?LIhPy$E*R0384=pi}807zaW
zBMX4!Vx$1TDmYYM@=`cG8cu!+vjT|60-$sX0Tuwo)6%5~go}rmED8@LIvQSzD<W74
z@qMU0>9PD9_3aVMVgYq%X9A*~dT}^A3TW!l@*Rk{38Q0KX8`&O^_hC2Sym2bA%Lcy
z0xf{@H-aCK4caO2Gtg3z_Y}Y!_z8%%3;y+LnKXWV`L(#`Q+~>e9)0=eBOikEDgP{m
zoo!!_e$&&&k^v>)B_P@o)V<^^_1E~V8z3u(jcrf1i8FtyKhaj9p34AQnnWA;(s0%p
zK#z8BScSZLj<&Hgqin1UyaYt6MBXdUlE22Um!HOeKJwG#udlx*|MRK8*8lYUTK_vA
zey#uM>#y~{^Qr$IZGTOE`usKdolpKFKOVuX8%MAeaHqm;4<K5FN~<FOn@YH4lNX-~
zd<FUf@m1*XDjjawjQ)o{AkqfDOvNjJuUC1ifNxQ8%NBgku~Ln%!z)yr%2frN(yLQx
z)xbmE@t)UGpCR2vW5)npMB$+br-$^=7Njqsfr%d82%XYy2RfBwB=88}<PKEhiiC9k
zD4mgN80C8$vLZKGEeC~9Jx6%KIl||kC42?aUx9GSm+<vEd>3#{o>i0v<UA5_P5`I4
z#;qvZ+X~(ec%h2-1l~?<E2|Dq(BY{%d=_v@o6?*QT+6c(xYo{Wo41{<z!~I2@e6^I
zPN@c7Npw8aPP=sN#I`r2k3@Vc=#)kRTrJN+;M50*UJ0DW@Yx>9m+kQOABs=yM`MTj
z52a&8IQ1vO3xQLZNFR8aDzp8-m#Fv&;LB7z_+98w;3L6n0Zx4V;A(9#6*z@es9{wU
zrjCJAz%42s`X0)m;t{~dsJIpQR28oPUZ~=1C(=~$slZpNcqMSHt@Z-f`pt12ZhYU{
z{_TNlaR%z}1mK#?(}5SN@+kveq2eonSE~3<;8iMq9JrQd$Om4$rw$*Z;?<B%I&gaQ
z<7*1iB0q(fog=)mk?=^hor#})*f4#4xV4dRE&mnZA4B14drt;#QSnsZRuwM*uGM*t
z4zJMRRXW_V%Nu{H4zB=CavzC&R|2Q<uY>C^pHsT}Z9hvmm483NwX#*KxJXcyFWcQP
z{cy|+n*6P238(Z65w4|Qsl(Yv-acdjeoB?qR28Q>Rsg3oD&cBrusvSfs>2IaocJn%
zle-J<*`Bdck$C^Rpuj#YZAMg7f0%Y<<s{*gY<Zb@l?H1e-|(vum%f%L-sTeDRm67h
ztdB4MAd$WUSMT1J(a)ZO4}Tw&H8<^d6~UK3Dlu_J#_vjCY*Zi3Bs_6!VpN|f{cGo*
z7rC3RLj!*0#W&@(^$XzdqrO0Qz6p$l$kjLfqx!-~CM_#bec^jl(gbHzl+OHTRFcis
zpdx4C&-drgKL`InCI8%+nMvne2z~yI@t>;@I{rS9p7+Smb@8z>@yd6D8vAx<J%7KZ
zzLap5H1zxfeEIcX9cVIzu@jsFl$SyKi`PUcB4`7(?<-ubUU?IJLNWjbL=$lSg0_j&
zy>==5N%U%h_$q@Eo`LV%&Gh$+Ym8AzW2Qxl&OqsicpiFGWAywc;)CvqkHJTm^lCyV
zF!dijEnlT6ANo^X$fr2?BH489Ll5xxQ9n<hmRzLMN3GjTdRGG-nbP*9A#tK5XJy#a
zpnb##E=Xpe>4!A6KGBq~9{9$?>w@?wTB0b97EeE%Ra#$?yXR#>BA(?zUWiX-YG)gk
zO()Qhzp)W<Ui^yfT%&5?_wZk6{;Fl*s0-y+ZT~KSA8+^22Yi(emY}L6Q`Mrx+X0#o
z0pj*kEgMrVM1YO(|1JUO_%BERUjD2<Sbh)x?=HV*JgcKODNT&ketz_PFFjp+pm3UJ
zw2L-Fd>=Zg6KczTVz7JWT7?GVBJr)0b2Tvd`z!6Mv@X7^^1DVzWBk8IK*aCupWX^L
zMpyM`f4rVAlx(6-KosAfuEi&<oQQA5c;X}SAayvRzKP;>9~faZT5%HcSsu#QKYgly
zqv<y$nDb2^-;DMtzd9QJwDRlH7v*m({R=F==fgW{XM}jLRPeM`l07L^o6{Q7m3eJI
zTBi7XP9na*i|^dRh87Rf!Ghg0=VAn?2{joehK%5&IZXTdD;V)gp^~0=E#Q&1HuVd>
zM#GgQKojAfr9;!<UjBiw1Ef`p(!bRTX$3%in+W%;K^hD96rc%y-5RD3)+@?N!%pAd
z!iNLIB7_zkLOxA}D{`ec{?7zwpT4v##G5KJoQZy^lEOR3b2fgVFwe=~UsOn0GpV@f
zQ&+2n8kMBzU5{VY!|)4rt5kl1)8qH4Ea>RSq+NveXmr@0Z6l)NzaX`t@?-QW`8PIf
z&m({0zo21{r8*6zBs+b#z`JZGTvO{pfO<a(5PnSoXyG2eUciW_sn-h<u%7=y1g!C2
zsDSnS7b4&Z&Osz!@wQ51U0sB$Z-F#Ae>KLWqxtYt0eyDN*zxM(Him-#tXlzu3x#%}
zBgBXQ0vgc6e}N6?!+!w{2!7FjvBq+c{K!wcRPmb~@Tc#Geg5k>I|YQS#n~cYA!vmF
zdRD@%1RN*-fre*YV-Deb5<F#q3cyZ46~GCYN-n~u0-Acth<_dO23P=PfC_*UFcq*G
z;T31$--)m)K*(Y61JVII!B+(+1ilgw@&>{HmB5b!#sHrRC<9ag!aqa#2=MfTyA!l3
zfE9Q;AOv?G7C@mI#|nH4zN@(sFn?{+cfVSl>3-`B;_d}3*$~4j0Q0|zX8pc}{UqF_
zaL)jmdJ@3jb3g1x0gdH11>wmE8v^i8Km0q`vjP%MG@X7b_?LlqRwMlD!MEjyXjXNy
zX?`d8_kwplpzajn{S14&?!(xrZo}Aqz`346@Sg$iQNR}P?)shlW#I380Cuea<7wEL
z0)9{aOTZs_809|{%_eV%#rb+HTe3Npt$qi0_5Y4#p*vz(I?>?P7223(do0_sF_xX!
z8Y`-{4E$q`z;?I_ZF&H-gRyMZ=do<*kytinUo10z1sAmWaIFvEo0CUl*^0xl?9dkq
z|0?je{|{vM73`3aeteOQ6@H1j97P}d0)3>|#*FZvfPV}8%it!!KN&7P>%qUQ2JHt}
zcE61+MII4fgBK8sbf?U<u~~4-s)55D0=Eh-gG<kL@K=Mk63}xBS#&7RUeF_sAr2rG
zGS!|c&{ILP0^)UaIzO*#KAar_&{GG0yB@gT?>?MWo4x63>5!}4k2Bo2X!a3C(EaTr
zv^#T(r?-zFa}atg#IM?S5HA7I{%ZRU$~zwUES($6oB-n`4f}f`mF>Y;76~Z3bQn7W
zC_ub1aCZWh0%ifKK-<*_e+BVB1b)E$_DH`2;$Jq5#RK03r~niKj)Jxq;Qv&DzwnV*
z)(^1o@?p$)1>z%(1mJrC%K#;SYS8ur{GTfDmpm5B1_G8?hOyv|h>tWT1K$r=0hj|g
z4%#6=gJ(T#ot}wh?E&<Jz#sZzEL--1;-|advX!x{9iV4~m%lUU$uGsSA%H1o(IW#9
zFZ<P4HWE<Sa~K;5=n1In0r~VA##RIB0Q&)rJ+a`gcnxC|u&U26HYE~mgt$k0gCDRI
zFb9wTXg>gQ>JK{HNB}+Y;Geu2?E}!4e+uYJK+6V<)YU5$^!96@OZ?(HsT`me0QBh;
zf?fsMI)GjdWuS+?9?MRFzE_vNe;t<~Uij`<d`l$u!t@*XBffz?JdQr}JN27pKeGyH
z)SZOR{K;$oM6^QK{x|`eO%2gT!k(v}YSW|H53L7%wPa(f3|{*oqAdY$89=iiB3d?h
zr>OjzexQ4I&3;MK4@5hc{SxUSdgxAGvp@Ph_BVog1J)K}VYh_ONb1{<!ZiDu5X6}?
z$;MVp^x8KOts3>%tJX!N<@ZmMZ#%?|oQk<4(dLmQ(L!NIb>=Mmn*Jpl3C%uB)4xR1
z?6WleOEkTGmS$fx74-NF%rogWrrDPfZ7T8~quO%$6<v6>`llmq@(l3idFxNKIpB4k
zg`W~BK)jHdHg>eY#(G+zgRUFKLgAi(8w__O;0*Alo)Yjo@4|OI0TIy{|A@Z?kPVm*
z7%~j{4sKJ=eDDvMWn*=B+t_i$4YwhU5#IPq5uR`lzB3It1p2Pg!&qvZH=OL8jw5U@
zfYx^ezi0ij3jC?}+L#sK-@mBLWFs@D)W)U)wDm>heKuAFh{bw?))(8c=IB>~I>5gR
z{(%TfhD#6GPu00?Y$w38zHr&tNI)6Z8??S?KgY%@;L`eL2;3#`??N~|JHfxR9Cm|%
zRiXH1E?^x%d-fyz=sc`j0ROMO?~kjjD)(M<I2w8=QAtOmIw}?!6&fZLc@O98b3{cY
zB}GLCW?*ELnZX%G(a0z%G08jGR9N&z#Vu}8jW%6*yWD$8u}G()BAaeprJ^nt6}P4?
z71jIwt{>;Dz0W>Bz(3yi{dAennzPS7-{-rY^{i+8+|S;-_e4B<8L1!1{4L`5(g&d1
z`=IYhct$SLAby`jTDEWo@BLhXeDDBl|9-TMlkp5+q*-tXd{!dm`dfqi0myeE)t!px
z`Mwa({4K%reNV&ld|wh13;3Sxukc?nKm7n=7a<=xAJ3RR4|<;)6Ll9rt_IJ6er<O7
z638Ed{2<c!RVi#3=baD2_DJ2=q|R61`~uERAld#<jq}aJm`ft@&%yV_Pr@ch{A<AX
z)lt+Nl0E)3<9yE;`W7Vqb>MsPcw8)fR(<cr_YQoIAldUr3C4eY_`T`#aZ!o1k@?Rc
z<XaBHCy_QX{~4lw4?{nsjm&>WA>VZfb&s@>`OiVfFMb)mjl{o6d|&zs=J-hbo5A;r
zC*xxJ3H5!B`OU>eArk)<@O}UH;-Uk|^bh%dN&>{a%tCf-gYt|wDt-#}okL#c<?|n7
zlo}vkj+9MrA5nR#1@ay9=s%G*GQaDCe9;2h!!ziAHZZ?q4Bk+2LO4hp8DAK;cko2a
zNsu-&zA)CW>}0H~PD=QWFO2^?T!J|elHd3;iQmUxh~JUs`lDE<U_3;sM4CW~+=uZE
zss3Jk-h;7e00}trHv{>aQxc*Csp>JvejT_cAdAlkK4*}Mp2V7F25bJuqoVq2`0de@
z{2cXz>?qRMvr*Bxj5P<+JW}Z|A@d8&*Kr)dZ+?FZkZ(Q}c_UTgmZs$w#6%g^lg&uO
zNIm#Ijx-ZW^?^3eGUN|Ib`WXaT8A<otmah-(O9APa1i&__L_t!Me-Y`!uY-7T-+~E
zneZK_>^$w`2;?TK5~2%fBjXoiF-xiwV&($OlQCYccl>IB`~>9pBW+~->VtgU>k}f3
zw2|>^1oB59dl1PUzZf&x@dj`r+2hv)&QIao5K{TIsXAqBb*BRxBJqzgyepT%E=c@i
z++y|R&=biXhZb>u4CnfgB73p-cB|rCA^wU4?n_RH)%!4}zek;4!}%GU8$oKgALI3V
z)%iliBsMj`2ay^-5fh6aSLYeiK7w-tNM`@7ntOam2sZZo3vV+2yubK;ZxN9|wtr0`
z{hu5E7LocF7y13O8Lk$oe+fKGDW88v9wqvpzyGf-uvu%r>CT3Fv8lK4SnQmmwG{<}
z1DmSwTNr8T<cN6W4BmqEXhPJ!pzvLR=<|<piVF(&iQ`sIKW^>Jg1$43f2{U#2-WhL
zT$E`-y8Zl!D8Z*(V;i{!!W4#U|NDU9J;yH0Eh)?he)}>orCv;v!erCG1~OsFeXmw*
z+T_V2arZIr4&GA`_%byAYVFsg_R-Kj^#v+EE_ge$XhE9&Zml>kll-(L?}Vhx0m{LO
z&pr=%mRUBtSmn9Z5{bcJVc=(wh963ZAL27uW65Yevz3!J4kPhiDL#u&+7h2UUya0j
z*zEIVIM;x*f_|3whr4Wl$??g0B(4Xk;*Gg+Bf#<At+cvy?k?D>d_(HPa`JvIuRaSn
z&wKB3$rqv?ct4&kUjf-L&QI4l;vO6an=Jdq?+(7ZAh1Q6T$fCiANWb+7bYGl<=1x?
zT%+}s<p*v!2d)a@BfuTGz`?WBJ$y3%w<fc{DCE$^r1O>odjxX*=VI@Uavhf5u-l!G
zGL;eG?*Z(&zt$1I;_;A$)jqPz@~cEBaH;-EXQrD;->d^i*?HKfBgb?)$99V&3L&<E
zUdWUn-v!F7rpw%5$uJ|<$3e){U+jnh%9KBr>Niw<v`7(MINEOk_=B%=WP5Yfhs3`<
z36F&?OWKcen+xE}>y%@^&;Yq^)Yn$(hm@>;ZOc7YnWCW^?QQ|j<HLQokT2e#d<62d
zkYB8F#4V`*V6|l*(=UC>r9i;ZUs;*#WXVwi#n)Z~pC?C`568V0M=TVm^WkU$#}fSe
zL*y9u;n?Tq==X52u7{~dcS3BzvCEdS?siKFR`o^DI}FTWfJXNv#EZQ6Yh<&KKDPo)
z-TM;adM`%XXQxXoWskCBkpGs1n1*eG%RXhf%@T@+3MvBb!qA^Oz|sBp2|S!Jy)5?>
zu!X6i!U=8Rp&Tf}z>Yw!c|Yc}Ub!|^CSs<6smg&_0;WF;hB_7<i@IN@j+ApCH@8l?
z2;_Pp*A{WaacHB#is@8a)^$;E+$PJgaI|i>UCA*8j;^TY=-U`a5aVg}8yxX`>M`fT
zQEcnsgaTdZdeniV*Kx!d<S2hUy)0+i98ur041!}Mp*eat#xV<yx*A=USs#uQY&~kz
z^a#VIC50GE>mB)A7gxKxTKOF9UJXpsh1%|AUrjG>9(C6Xj*4o{(X)OI_7PLyI8YZC
z_u@Es*y2#*L947Os*TRA444(-FTu5V;*pa5GsZ=GeBOK<+G`FReLn)+N;TgQ<l&R~
zXC9w>AUAv-_P!}MZ|UtbK92%hbbefo&qZHLvvoe>^Ab2}UW+|@=2xB0;Ws{);u#_p
zRoL&ROlP``-}u}BnK0&S@1e}FC8O#?O;L4y(0+Zu&s>0O48$WP>qFu*kIxg3>sY58
z$JZ6e4Whobdh^S3e6GY;Q@%m@2=eTL{2J;~j?d$kebzBP9|A||xpDC}j;)J69QRq>
zCYpG&ySoz9V-*}z@NYRjm(8U4R3OLrTn>(!B8*KKZ|iXEsyp~FheTF$9QlOtdk3&n
zS;l6rCkBCOIFOKQJQttz1?6qZbvk5;I7pf~%M4^^wqmb{V|1HOc|2ouk<S=iga_=*
zU~X`=w>&a`l_&F$a*Y0JYK(RuH}L+1d}5nR?{=cq9HIl5@B;~P6YFf;N56k^)tOpX
zsCj@~`_kUy;248_uJGyydk1Q@!GVt8_ang0MdIQ|%x~Ezzn@z9VQBRXX_BK95Br*k
zYL3X)(|sfljuvo~zcDVJr5*=-IDT#E0bljgV-y_2PF(zf97{eNf3Y|)wEA%@fnzA4
zIclCrFH0UA6(?Y9e3Q1vejkn;_6Vb1y1>z2AJ00r9sp+b!npVW%e&~4&ofqeGuZ41
zIGopOU8|o=FK-TAv+WC%p&TsB{>@SO>GJtEyVv>b8_J#^O`pGBo5FD|*o8E-%Mqsr
zP-Yw_#{n}JJl&qRL_^eJ6scmn&)S&n;S$yV5O)}9<TA&<-6Rx_IvhoE-sXtYXm=cY
zb-2l8cD05r2ey81{xT8JHbbW6E=RmPLq381IwN*)PRL#|%JnumMj+eK{oFVf!7=dm
z=f+Wv`r5zmxp8!YBhu@L-=bW8b`QMQGJGs_xn-TCJ-9DWx97QW90f=DTj7J5>g6AD
z>rsvIr}EZ~bI=ca!7=&{#BF7;$Mu#P92_Xaac}(g{AD7LS%l2NzUOAMa#YyFZ5!vH
z?w#PMdAB1zlF9BI+ss}nYMf)?2pwg>!MhDSJ|oBKy~(|tGW^bcfvzS8?_%^|*-u=W
z>L-o@SJLRDkN?DBdx)bs^Df0&db*8oG4$}syaP=pb7Jd&oxH}u8x?)AR~szt&<*Tr
zC*t@r*}?P+R0Mm%<R62~?3*1m_ZYPL`D=9lda;^=gn^v{b{cl5z%k92?B6;RhPGM-
zCIY)&<HgVhm#1tM#=3j$gs5Coxwslr{W|lh18(dp#6f%cl&#((YnIu=k!gb-;147J
z4}0-ue!SQ61uZiUneKai@-Q-{$FTBQfXvc$>&vGEYwP~&9r0);-Q4?PvOL@uSiRN}
zzsw+GtHym%)<G|1hF}9eFV$sR=bnNNwM`^(qrgprI~$HRJq%o9vm-w1<<s`L+A=A1
z;5vy9*&A&4u_^q3lT&5N8*#)zsy1|`KF9gKTo*&W0`e{1Je#$DTz|Y0yheWlM}O&o
z+`%pfZ!-3jUHMBys>;lvD9bhm{QeuW^c`k{lQQ}`$~<KHZ*W9Wrgmm_xV67fuVSp9
zD_Rii>#Nr-Nwv5a$vWh|z>#~L^mz~Mr_3jD9l#Z$@5@$)<l7Hi19Z-Yqiz$x^+V5h
zdiB(G{Whtoa-vws)I6&q7P>_L#%~-~$XAH<a(}BM-j#tbaFIn=8@kG(h=wk<zJahA
z98KVJwmPCMlkKmw_%N66bWt?AzL{#GzUG<&_XXy*`SkU={I^>4X5V-jGGmZA$6Lnj
zbO2SK#jr;a^yWI%+a`DGHc5L`16Pi*;Uiw0>5I%}x$?)Rj0Mtt+W`2&uzzble2^&z
zZW1!x=ocEiGVnbvgPAq$MeGtjS1=~z8b^sODZ*R>yfH7YY@0o1D3g8@0d~2=5wn<6
z1xKuL$=G3sRS{T!stY$}!F#)9mS~9Wd_VYBZgIp7-n=!R+G$f2VfGxRAu|b?v^KLd
zRj*6Hj6+X8$kkh~w^{XCjP-N_#^z6Zai%<Pc9qAy<zhRkuA>(4b=-t|6uf-WmbWHt
zS%KdNxt7N|r_PHtWhdIwbrSf^DANNO@X0H9G(&CZTFcmuw-cxbM-kS}YnWr)mx(W7
zl|35D>eDPkGx!Fs^y%YudE7(1yGyx5m6c6i_5a{n0avEEvQb7gH#JwDrwrDE`N}xZ
zxftu|mg1<-JdRiUw;gXPAQrkt9#g?ss4jVoY8MgkG=XQbB$|2ccfVB|iS)G}+rlt7
zI!{GB9*$i;YkV<g)ram!W+AfxnT+!)&!U3)1dGw`PC-0-rhKkQ&!-wP0{L`ilJU&t
znNKHV+TP*_UW4~5k9VJ$ebESHYA~<9%bO49si_Hy^pV5Bc3$m>Z+NlBUhXkR%J3og
zr5`}d9%T;s^j~9E+4a1l3No`F(lU?cC({8L@xg@n2FpI{Bl7_(AFO>MfDc1vbH5{g
zP2G@^^LSGp_dL{0F_lXK9zj|FNBGX?#!-e~iSoOj8%GB?D(~1h2mNOp9G&lU#6RQM
z&mMk#zyf5td)6mYf}obM%N_B>4EdOzN_DHs&UKK9G&tfX8Ds+QwCXn+vPTLI(Xy@v
z!O?uh#yK{Fhkt&tSP`5LBOMMW#EFHl-$J?%wpl7Vp@L5ytH0Bs%)F}&91G<M@gP2f
zHHTCCjjeLNkBg>T^+aDSNLg<~NcE>B#M`kJ3pQFZ+K<ibl=fskXvXpnfswt1I5&Vc
z!?gy>$NQBzH!$H~n!;=atL|T}%+)|y4QvAv?{R)6T`oBvQG)I*IOaKs#CxOL(`9#A
z=8A^eQ-gCD*l8r*Z+*5Uhb{}6F(>~rat^>U^1g37KX!HOf+<-W!bS!@9|w;8Bga|Z
zBkthS*aUbMgz#tx`<{f8o8t)YC1;$4!D{<)x@d+r>5t?aMdE$vjAiiPZ+79;>RuV#
zVUDCyN`@i3jKq7}GueV==AWP6mg0OEsT=ad1s5&<!FT>1L27!Jjt4oK{(B34AB6l%
z@EHt#BjvOBPWe8hgNV&N1E0ao?%(}<(bUuM!wGRWWQ=WKcTQ+kHF2D!2{2}4<0yOz
z?}l=7@Y*Rk5^|144oq}ecGh+Ago=}~@|3@|;kSuL)HN;dZ}`dAwv{*^M(X@RLcA1h
zELdTcT|0(1PKIrw5vk%(Li`1v!8%I@2H+S@<u6iGePs*ckp_{PK9BnZm{*4-hq>@Q
z1zcMz7vg3w^O-~ne=#ABC%)gpBOeas%18mOFp~LX^QAKKAu%4Dz8FNZE6+4e;%IBe
zk>|p70T+H#B7N<lu6v;N)w*&BpB=S6II~ZpaZ~s#M!aNNY}1vg{Wj{igmeV)@2|tB
zs~i>|>$e!TTZtw_fHoYpY^duu@F=WjTE3n`I=~J?S1I#wZW-#sz095q6XNw=eXf^!
z%RYtri~x5CxQ7ECy|q3CAF{9i)P|}dGY6So#QCSia>+GRgDe0YAR1DWTQ(W`5M_&z
zkEltA9r$qBNy@5`hq8`Gmb%tMwh?t(hWvw5K6dzqWjkb81DQU^IM>AlUl`=dPnXX<
z#+qFUYV64M?-b;ZqO1*GdH6hc;Z!-fidIL|lh-pkQO1Y7GNz92w)8|Dvn`evz#rjf
z@9@e<y98YOwXEMJ;14By{MX~>eZb9M;)ApNl6+&p&7pne@^i*H4g;6V&sTx#tWStz
zSyyvDb@f%Z4QRItR8aAyTIR>OWvF)xWQyu?`}qKHb-+D<y1`+ppD}(uWc#_Q`$+(+
zu8-jk3Xcrxo?fo}bQ_N7FRE=Y&hcQ}Cssh#<2AC-l#7KZr-B){MwR712K@-?RQmUd
zPx(FmUC#1DW*R!4@1rAQi<DQYK5r1%Az)wO#cpx;35S3a&?D1)JMb>4x*8m`|1Lph
zGs>Nh{}zLufA)NmZIxpMpIdVhe8!BKrpdVXPXn!517&!~aSUui;`48gK^=SK3(hmu
zO9||6MlFI^$OJgjTDY)Zo0>6&!Fdpg&)PW~pN1DMV1_5ze&_HTpSyD!>|ij)wJHOa
zy)Xi?oc!~fU(pZ3NW9OD^W$Lfo2mJcF~%JhA2w4d!}9aKIF3WXavzy@S~3Y0lQ#ft
zIo2N+PzEWfI10B*xsHh7G|PV&_u}=jE!X>SPg>kgXsiB4OS9XT`W+?5OB3?lS;5Y9
z4toO2_D~Ew|7;)O_(9t(?M#T@;nQR1fZ4)PwP>rM+9qwZuqz>s^YJhDw!&pr5o$x(
z>Wh7M7>Um?p?)qq>iW7RHKI#jX#kGTI>`smHr|KC`(ZD^XK>K69qNe<f#v1iE3xB9
zy!ZAhVu#&WF3N1|5ny<at{lh5-Pj%vHVB*XnJZF<NjKK3LnW|$Hp`XN;jkNPCWl5}
z#$@n5Ux}U1jAj48b>}MV{AKbYB^^NDhZ9htVy0iZE7gkCe0K)&!;t6u+kE9OPE{0b
zxe9z6bbB-L%WmD6m9b?6zn7uU8F<(cj}g0SVNIKL@AKKa@H9o%KA{x9hmn?d<6cI5
zx^%~P{vJVE+n)LN7X03m<@Y}PK6;bCd>FrtAPsgT)Lu{Vw^DtQ9M_b7)4&98)|fN=
zF-yQS?9rI>{4u;fICP7~#QZVzvBpk~Y4pc50#n+hG41{s&XenQXv}T?m|<X!7@m9l
zF;l=CxK;BE`C}G=S%!^2N;@GX{nxT#A^fNq{oD75`A3UK`%xI@D}b4Tou4A+pDm2$
zp+7VLQ?%E=KC|^_WsnUcO?@sQUWU)$ti^vtYR!|4gKdW#OW@c=jwOo&eU@oE?B}!b
z(AUYsXPms2JV;5Kfrl4+*an>t8ZJj0{7f14^L(y}pG<0t+AT8x89oE$t@w21qwVgV
zf2e#Wf#q{l@|CFpeg%ooYT1(^pSPn-spTK;v`cN>$g<Jz`RtdS8RY%+Y=cbK-En;l
zZ#LC-b=i8YJUL)<OdEnsAD&O+WXMO~SV{9sJp0yZ;N|!LnPffbJl>irmMjPR)+Usr
z-pg;*Yi+1aRWLC0Df<0pl;bsC857g^X5|E7{N4oYA@p}=c(FG~m8A~64{jdMyph*7
zi}JGz<K1TPT%LUGvH*P1yYsh8G1g6^@ZAQl-mr@qJ8Nb90Lu{#(Jl^T`cRI1?9v77
zkt}w})*j7VhtD~b<2Ca3)^i}1s%YX_4nEf~AAA_tKBQ5^f}e#?S3BII>W!SENJkOV
z&V5rCM)rT|DkjnN<p?lyNNr=7Gomhno2_~_^M<(90I<>iPJ68Yk}%{q!(Ues1D;7Q
z)<X?2&K>@7`S!h^*=$?_9_GjAoSlSESw4L7d^HlEk7%DS!#U|ISbLp}W0yUA?)`1d
z^WI;+cQb8`Pao7RlKRXb@m-u=eHL(@@14vgUkH2gU6i)G^f8=2^a@AZ51wF~RbR4x
z16<asJ8m(6$npb!6#9mVM@sr6^tJCT;#fbI1IPSF$XDiwo4kB7f7YbRo|}mgU}k}D
zdXc`5x7*TJ_kH$-iA?wLmcTa$PSf}Cj-+#_LaV7QH}5KuFYo>BIbGk!JC`oQy<any
zn0}poo^y^P{+?wEemgZ5DBG$~Yc?L(mSr0U{@_`Ts6`oFw$)`z-sD0VCuB!s)Im+j
zu>y|HGdIq`akC2j)}hUg_%4ovC6?Z(<GWB!<c?+i#W<oO(GYj!c#d<7D#&z0zOGbX
z%d2zC%UCK^W^M!+F=^v*$W6ao*KMyQXUgv$u;o~|KwZln@mK14(2`L$=Ek~mAXEz5
zbTJG&cd8?vCVt6_SC`UMsr0sm){u6ohwRZ)9JN<a`khpL!Y))z6^nLJLcD%p3dlZd
z5b_7kaMXOW!7U#!=7bUHZxeKYlW`rEzR+)BjV=B~mMnSEfNg0RG9xEBdG*!IgE78k
zCpzLz<}vA$$CQ-^8X)s%fXrlZe(jZI?gRc%i6dUjJXWkcV6y<rpo}K>kH>+Xd!fdL
zzw5GZz-$6y%ZS%MXjdo1y#r-oS$@cuRN&d6$T!$v$tzz_-oyOh3lU&SaZT2Fm5yWY
zxA4Zs@3zVx4Vflxs#J2cfTQo#cy=huH|4|eki`)TQFSxRWH%u>M!`|DHzB@7z1Ms=
z+!y!R1Puq9oQiP+N5{t!s?8S7xoyW-8OzR$@jWt<5H~YFq+}ni%WVR?DB^_nxw4A@
z-U#`@=R4vAmN{bOW$b1&BtZtd4S}Qic+JtfF^+j~bcQs?#Kt(nh1hQ_(i}%O#?c0j
z(qlD8<@ZvyUxz&y<2(EU&C$6rj%9F+pP)I$HpWqj*xLHzG{@q`IJ&`6@jT5DeriMZ
zV2p1~q2_4b7{?koijL77L+j^YpAtD9bB=THY(5+Z=PVA@r>I>p-L}er=>opwRk`oI
z9s=$t=51l}A|>0PHIFLC=_%k2pB?wVud6oIt|P!Q#&`5Z`X1^<OIPiO`OJ-Y@9*4c
z`X1`y@2AzB-`uDTGSjE)d#Igs8PjpnOlEF01eums#>M-fcd*-%QFi6>D>?6E*=C3@
zi;ErXbMQTBFVn`{otE$1sHg}wKXc<8oC7p~L%=?AZq#q-o#)($F}?>%@hn`>1Sj0`
z0cx#`v;{}5afbK)&Xvc-pD4F%$(iz-EqK-Ex<id2Q-Q>Le`jA2S97JZBdNMoHs^FD
zX>-n%YJd-Kj;py+vlpLzuG9nB>Qm$5r_^`9CChQ2Yd}>_Gg)#?A~}bgfP4|^YKijG
z9(jhyQyvczvF*e;%?jk2PL7KQ=qIa|oUzldWGR!Ad$zGM#L5;!rjB_bC4CFJ+G|Pj
zHvrpvVqCnR{8c|l+0gL+z~aZ~O#XhzR6ynm9DDigdzxwUgTOAA#Kp_V-(m5qI#Ttj
zJVVZdOoh=mmmynnN?cvj9I|9-bIu`XGuQlySJf36{e$=ZR-x~b^QRe0Uge!Oe`*H4
z?bUI0FX5VnH@3)Q{xkxPk=Ml4{Hgli)9snZ{Am#!McoPY?1*k34z&tUb&m3zm^)Q+
zwPq<VM!eUj5@G>%2=-eXwB6;}cDN}%X)xd-NG*_S8BK`S1R!_Fk~21V0up9nh-;zm
z&|gj7tn*QD6k*S#3CAw~kakzSr>Z(N+!$HrzW~{_=f~AtO#Cq2etFEr$`B`e_;}4x
zvoQ|F_|AtkN6*GM#=)^%q&W_4jAI2HgU4!)m5p&!VUwij1kF(~zag9UfTOfnb98Ks
zV-g&b$7znyjd5_JYWR7YV_{<)4midOHAm@xY{(u1;OIR@b2P1=V>5i6e}32T*~f;F
z_@0_u@EJT{@uU6n{wlT~a~-rE7{1SDFR`O;EH@==Y!5Jee~sil<i>h=M}g&gZY1xt
z8*B4c0ym3Py<D4q4*~Q|4R3FQHf-(cSpd8)JPf^MEGOjcaq2BfZMjER0i5&0>^P1W
zyk;lBH;j+qoTabsyVUNR87fUjqIw_7AAtPWziauQtzVw8ZEes~=D)grdG6yCnf#A`
zI?XS$=}(_&g#57anNmyM<1?(UK43>P)E5KB=rgepZKUi|2AM;UnSej!s;_zATAs;{
zqrHRJ>na7Gv{!|tZ=UtVYZuc`YxxV;FW(ROKIkd)Z&<(lG~~-o{#(~4&-!BQ_=IVT
z-IlzkzOwZdoacm*_OHgpQ<yIW`z;<h-WF_m0cz3At5}Z>NCS9(Rx3V(!Dmu_7D#RS
zlb3x(+4B?PG5B?GvxQUhr;l2+a*uC}e8(rmKGc7(#=`6RET}aXN0fKb2J=Y0MTzu#
zhhc-{ToQ{cV!7wvgjg2p57VXki(7OI+7|k%S{qaWJMpZxNvEZYk4>`Km-Y%XFZ{J4
z1(z)@%U%)uR)^Gi0iKVJeVpK*Eu1O;_kz-7DxMxUP}(=mA+C!3_#jfxg;CK8{ewjd
zsk+e|f%j<&Wx_g(ur|a!MQbOm30$=AENmwGdmJbG*juH|oKQ^P;*pS_xW^#Zr?PPv
zRMpUN<T%6};@DLmEmThJ<23_Q4oq5{*kwBZt%@%Kjsajho`=|1mc2Z^>;=uX|I~%-
z+r+tX$bRiGWDore@4Z0V3^w_2%myq2*2*|t0e_wOG2VqizwJ(!34GTjBJ-&NcIc;Z
z@eXg<bv>ykU8=E$<1}^afJ`ZL`#=VnfC}q0^Li;W44IlA;awWE$%Kz?-*@Yl&6lf@
zZ<uLDUn|0K(jR2IP=Q9uwE`cM%&Z>lm9zadBk>)1=i$>;-|G26PUu=ym&|7XiSNE!
z@nZAHXBskmm)>i=vL>JFQa(d|zO#?{xpXq^#XJCrBDmqkZ7sFtVPC=b_Ob2xa;V)K
z(`?f?8X(sL4!$>#u>-yw_qcKn{7iqPTIdOGwZ6jIs*k2G^Id}1X5w_OM*}~xNU${f
znDtfet4F{a1{dFF$iCE9Pj~-ff*I)&$!l_L;NUwAp9{wrIQWjmN1%kC9_~v71<#t6
zPkYfoEXy)D_@2cl^W*q0KaNWD6FuM3&q7-8X<x>uv_Ngh+&xP*k~Zb_!G>>Yj$f~z
zgKcX99N{nHoohID*~2w|R{h8#uw4^)UP7iid|1~!b;bo>w#UsN<vT1H1LWdYWBG@q
z1WOeQwaa5wUfBmVQs5Cs?DEQ*7>KW1`Jr+mfHP*E@7H|XE2G<``zE!(ux3cwwFVrA
z!EyLe)Gv-*I%^Jl_>5yKA~pD7Y=TS?uAhyfzmnG+#g9^BsVuYdFlC~^NV5E}7yIfu
z$Tp%rGWobWBvXxby^!I%_imxS6;^(p`5fze4A?${t;vj~E_?<M->3IS^442e)5odW
zOAa<Az!l>98Q-mkCAYF2K6yUO>wAd1z}9;5JoBi=dA`%_37&8B$-^F-FrbmE6Eb|~
zo1F)_`f;A`w>v_vJAJt9fNjk+0U5sk&gP<>W^tbHGL&o3{T3H&>Rp4b0n2v|%6pwg
zEUdAU=@D7!I^Rmn)%gBFJ71QK&j8}P3cYq}!Fj&-?mH~ogijv!-ki?k0A%=HJUb8C
zX&mSI4!{L+eba}_zJ*nDEkK6v2=sET;ymAB`^F6IE%1+48^wH@`BxO84}Q!MFG4@+
z*S-StmJHf8Wm+Ip1f4%Zoqy`1bE_qT9+EN#AX9#2T>PFgfAWzTb<0G6n}JODs<`+K
zWnTE>RNFOmsb(i;F>fx(B>N9?6ybVV-xY`tr%ft+INas)<!As$Nu$<1;lnXx>F)Sn
zQ$GNXxdyGr4L%%CTO2;umubTz;Apu9@3f*lZujBvbV!sbg7bD>9#4;-K-*#e%Vv-W
zVW)*w1D-OxK6n^1+n5hha()Pz9xYSnk?Dp^CG7krADOGQ4DRQ1<ueAEm0R>Ppzrl5
z4+YIWv-YET$T&OV;%Cg~qdqcrT|g!R9G?MHadTY7xIE$`bDt|8Ums`$$Mp8NxR8GI
zO&^YLSR65bAK>-DB9!+h)P2c^<Gr~#=D`u{(0csUhvQooM{T+utlw}E)*!p$;uF;4
zw4bE6D{j_#?A{2OgYE0{qXEbi!)EL8qe;kgLuNgGv;vtR`ut~Eo>%&m#~vHCAC=*n
zTI4s5h_XH}_mTMzw+$lTZh}nzZ}H3}%IxxyvFAV;d|;T@0DtX>50K-1=^O=~=e&EJ
zk$NnEWBRDp<Dqnpz>_ZBy%e%d@cQ8BiX$GR9&_m&1t*%BGJA;h!qAU8z_GIG$mg^M
zkEU}3-saLn_ASGZ5x;WM@BKyJ!nvFpmfii)EM%G?lNPTF8AkF@<|0pj6vXwjNyy~u
zN3?4-WCniWh*#1k&s$7y7eBSi6Z2mO^n#=L=bGb`^>dU%k122*{hojPY-%4}_0`M3
z*34mjNSz^@?5oWf`FTrc%xfcngp08!^keX6k{PsQ@C1-c^j8iMm^R3IYy-#P@2qb<
zFa#OCPx|W_^5uABx*e=teb)o?;5hj7#@7R-xR%z3eFeE5D7We-kM%$kWGkL>)bk5`
zZ0#9-<$lQ^WcV)aTYwKXTKU0uz1LbMfIVQaZJDu^;93Nh@5h$wfo=<H>fP@1^t^F1
zCX9Snwmom;Jhu`j_+D)ct;&aZ4yg|3`Hto%cz)0)51;iwFJ$-*XFCsa9l!~`uUf7L
zKH<aVvmTg%4BuyMbFqCa-~``IF4qGS78h*lT@MtU41Wp4)p}sY!WujItOp{H;rqnx
zd}*g9oaej8y>{xtdA`T`JG9e+PaZz&fl<itJ=b;~w9_Qc^PS!c<odl2m(O}&1u}f+
zx0kCBN)P`C&&bQr-U6Ss8XSCt`PV?E_ZdgLG@yOKdy}ktzAR<BAam$Oy&ib}Pt*HN
zpY^~fWM;3Ai&d8MEFYOqS-R<Y+!4skH0$-in|x$GXvz4@p(Dtv^o6*dajl+*H~Mho
zn1_?21ssz%==H!Z9}asCnqfUK3XY!Z;^J!7&AWU!7Ob-PaImhHz){$$*8?B(;qY`w
zlqo$0ZK`Q~^SB1cbU|i4^SFM<%t0pK@t3+yKqiQGbT5vB5BZeGXFaeCnWjBDrs{DY
znGaib)P58`6?4D6dOh%rk4zrxfi`f=?bh?~-}`Xnn1@GD#xZb&yY+gY_-E<uCXe;N
zGB`?ZjjMU=%Y8V$ZIwTL8YkOt<!1EFx9jyltq+IKdY}z5Q&>az&B-{9`>iX7AQOho
z*5gNqA=3|;_4tuE4fEqocy|T;=qjJ`*khw!4^%-${KXLt+v9CMGS66c)PB?f8RxHh
z9{xcenLO45<KUS2qn?NV?{tn_^Kkmn3OM?O_QfBhbL6ugs5%{E{hHQeEuEv_WP3f3
zzOZEb?E%NZU|g*SO8+z6pMBN?<B*yB!}`_(3y|3ioB8=(ru9I{i=ZE5^7SLQo&58Q
z%_+k#VI;mE{cL=?=G~Zsm<M|hSBKP*2d)b^zOOkK-w<$ouW~Nj6mSh=x%FEDj_>Kt
z#aE1W!S{*h!pZBwSLDXEfRFEI&c?^N9<K-UUFa9$I9O@<6zt65O|2Kz-uoe7`95!n
zjbz5MUKW5|?8$DQ3gCD@{lF*mdjJ|NPIb*BDtiU31bM50Kl;Axyu`Htw|rtu_P;@V
zPp;cgE<AdWjPjcL0C1Ce;CNs0U>>+5z>SpRUGT^<TfU+I^Rql~eC||39=HbJdS8?~
z-yYzGPtT1T0q$@fxEbK;^T4eD*K=C#d^f{r)dzFeZv?o?&*#Q<05|x7+_?R~bsor$
zV|$qZj_<Qiuzp)Ce}!Lhxn{SQMPTPo(%7!-*y3a0*Kdt0-oEVE8enUBF&<He{cfzc
z&2|8L_`MoCk{x>h*nVJT*$%p~cG=31?-a1XVZ>ll2PC_F+3yZn0<QPV@$`FjVXwe-
z%3kCv#&xB>uVlxuzu+~r(og91{*<Mo>Mzt*imn8<!4BY;qfv1z+GTLo!t3>E!OQG%
zS3OgG7&7Bm#l)lN!(3(4*J2BHr_1mfT1h-AUc!79ee$`*mWhRU?UnD>4Bwa#KjJY`
z(uQX3%ouWO!^Xb&N?&v!f8@RTog}48srdkGYpx?;Dkb+xx`3S>)Y$Uu*kNGH!Fx6J
zs&Zp**FJ7|XIKXCN^B%M_9(D@;C%~u>)lv0r!~C1$F2vw65Es+OW&ynwg`RSS>#1Z
z+7WiRmcH;9#yFhr2Cfl(P%hjsa3$!|a^a?dTgkx}M!vkqE&?335#0J+A%`JBjC_wq
z7EC!XRk%KN<bAph+uSzs)^`iAv->r+D?4@&*mCg7I_!00z4gs|?84xc*n#ZWMPU2D
zE9>xp8|$s_Vr=^KfLCHiGGkefHNY0XICuTD0oRm=Ukn1b8Dng&`aT5Q(HwlNOL+|q
zxNP+;xX+sf!@jEwn2|$q@pCwJaNM$q>AU(0tPVmw6R`<0qyMaBs-I2u2^nM}$Y&5T
zO`nUad(5ZPWjqgkHmeM7SF^baa?IkOZ(MWy$HqAL9*veSXpY}+jH3x01DF?l4>|=;
z_<36SbCreuH4KiLTVv|EV)$<NCxN=um^BUDQdf3d1;m$u>wj-dwHcew^z+tp&6s~F
zublz!;22f!${)|^k(~zn1HNA~T&167S#FgT{T}bMBhd7xUBFhpR%5HOV|fj&57^6@
zf5eSt%%#mc1ML3uG`2oF_9(EkhPNp@HjHah3x>BXGnV$M2e$2`SkCs_4ctH;I9@{=
z&w*q6oCa?7gK^P@N(y#aI-0gt<!+x5$gD!90_&H@aU5Jsmy!3}nK9pcBRyouQG;tz
zZTmIH+WI+Yvp#Tiy(20v#<ADO0+E!Dj{&#*&fGY@N2CAl+_+WXM)Kg}HMHtH`09Y0
z%>&m3Txox9{df(nF%SKwfSb(2eoMd==D}Bt>rG{O@Kpm>`kztXeU@(BH?V$NfIAAD
zoM+;@-G|{VfU*xEZUDH-rR+HNH3xy~1TKzam%qq)_nn-lCi|s%U=QVqEyP8YX6TuV
zm;EU3u^R>Ua<2}iAJxx=r6Md_8}JK1%U!lX;HE#W=Sn5NNR1gj^XLg+CqAaJ;q2H&
zV2eleT&cp1_0Fq`F<A)yFO99vjIBhuYJlwkFXR4$j)gULF!w0X5IUxe*U*~5FJ;<t
z%h2AuhPM0(y*JZu$@uKeP_H@QOWzz55w3yoJ?V3%KRn;P2BKf_8d@{fT4{Bv@{ms}
zGxb>oY~<Wn&OWOdxTBT1as9xpost_j4qU^jxp8yA4d&2~WnKer{?!TDmj@46c7?yS
zddAoC7s5UUJCYsS2<))Ij%UaA0b6RY6PdAWN8`X27sq_w1%~(#Ru0xzEY}=xqh^0_
z+RbV2OGJPbr@#h-aq%e}2InlS@!^ZDsckH@U4KJnsX3<ujw-{kynYVqJOGZO`}O`v
zaM{)NZJpVV9s;%*dzu5(xx~V1oz2~jG)dH>GUbm#eh$}xr2N_Ilc%m#xE3{hlJ=X|
zS@J%9(*kUT!A3J<S-*q8_FWWBe<uTYZ?fw55O8f~ulRB|r){eUI2VAe$9|Tq-y1FL
zI_kF!7YRo1)Eu|1pMy5*07tLcE4$y~K-p}aX@>*A_TS_4p8G&u^1-UaO#)XnkQ=uM
z++rTMB3xe@y)QQ(uc0~b$&G6U?!djdas9v@ephZBuc3A4ftv%a?f%?+Yrq|PZ*E)}
zu0zeeJ2$Q#xL_W9-M}>t=H?p)?r07>bG(}dPCOVB@j~Q3V)>RC@7`n2|JB~&Dr6@1
zYnh|DW!P_2;M&?e)`NR-97OVtt8cfu%G%I2wP(nl5>V>d3HgTmV`4kU<+@*{`Z%L!
zpFJ+CeS{InbUYOoZ_F^3ztxqe?*AdPhIwBUdAjtJWBKjLIbsCA^P$-FFN>;Y+VrIB
zWNs;A_k+i8r0qGdTn;#@pNWbi1)ls&xjt^+hZvLhA@)F~@B2});FU3ZyPvjYRGp1O
zX63t4@v98BD7ekGUo;ekZVQkp{be-${h@cVM5<nbFUCIlY*f6;tBcY9!|A-$keOf3
z&f5%3-8ZA6CzHPS*}S##8MXT%6L~f&I-q-c-34wimB+G80y_#FF7RUarpmSe%+Qlj
z@r6t}Y;o&A-V)sO-kF8B0hnrF#-L||m)G1U#ZKL<pAqEvOKakQP|IfPtK7Sy9}R-D
z<%d3gWPIXdZl9p8Q;=ExMKt|B&0Q%QECN&flc<=@RKE|}ys=OjcsIWk?cJ|_F<#-B
z&XT+yxCn5ict^p_I8LvxYh*DAHt#ZKci`w-GkJ{Ho6=4^6cKRj2j4K}xIgz^^U%H+
z_^R8kfAScT>xDUREW9u#UgYIab9q%2R0@`--GgD|yFDh~eH<J~?*j_vZ2PEwsTwlX
z&01zPKbcPEgZ;cOP_KqxrT2g5*uJRR{0L+sdt)k|vL#){^^O$;?M4L351Ex$#ngS#
z`0nke3m&oasSOnzZ@#M<p-ncQfw{#?V&d!!{$22ABSS+fo76*Q;Ix?d9LwjIucy5;
zpFYS`zbGcwy!n{=R(I>U?vp+QndWdzydV2`u6#^8d6io?`ot1s%1dJM9(k9H@`<k{
z9Th%7{N^*k4Ii4vaV|W|Q3rhU?NRYHTx$sKO0TDasCga$?WO9r7cw0KQSoEu@uhT`
zz+;xLYhOJGnf`mU%wze<EJCLKUM=(O{A4ztg?x5L#rJWoEclEiV{H6cyG^LErk*nQ
zMbr0-0}&QlwzV!`hHk=mOWxyuooWMychu&sm1Ec_WFk3uXMmZ!E-H57`e*PQi`R@{
z#Wt@KVjZtRrUQF%X?>URJvrJa*9!w*QHD9wd$O0W0hsB_v>un_)`PtLkg3eUI|fWe
zE8g47^4;vidxBj)Ww&|AtmWWkU`|zIRJ@D4@A2V1E1kCrGTm8t8&IYuVCG=k&jrAX
z@7_KrVB&t+<wQdTm)lJ?7UK3kM^E)D#Ib~tf7#-+#`1{2ssl?o=95s*trx~MJD#fx
zzlZaPzZwEA@`mj3O{fMjg|zh9-1#m6S9NM`KE`R4<Pp!sIIYTt+<Yy-6<?7ZR}S46
zr**hQ$6k$F{^D8363aNPigPt~GBcL;Spc>kYwT?G!Zuq7e=7d0-U~czajJein(W6B
z=T6>g;OF0;otL;4;3`kfFHTG3fn%K3SU7i_(GlQ|<be|fXj6IM7^gM*lHB<=05_Kh
zj&WLzdEiEXo5i&%j)g&_WP68S*l})*)9Qa|Zv9q(>%+D6Tzrhvs>8MEY<|P~jQ|&U
zI5&=QTBW#_mWz*ZT5Ea6X)RXj*sFQVUtyPRa8?eCa8<c)$vCZkw5<efxSSo!IIZEo
z*D+FS*|Ch%S_Jk&@)oV6#$2B^%Q&sZyEL{mJN5vuMZijZE8JMSY-PxoaaseP)b9|(
zciTS#mn%CE$2hI&C$h(15m$`ys&Fnlj{ODWv_?Op<Fsll9aVqf8>iKMO-%M(sE(AL
zW`1&qJy5B6FXOakFNuoXXv@KRD-SdGaLK6k|14zYFN%uqP-ehKrpcX84OC&A7XN;P
z<kHQ|SMrF{n*V^lW;AT&2|w`0?J!Pj?tsRQWydm3s{*`NQ?EmAtoQm7<Fv}aE3s4A
zv5eE|2k%?Rd)STj#_h;wp@Uaqk7UNucNnKtf<EXhuN`3rZ=6<h9`QYl(<((DnTwBc
zTB|wu!qACvT6MtTGM2lZJ#ku9Suo|0Wt`T+gSrkE-8S*oH{-O93~B62b}ZwxD#0u3
zaLtYN);Hs{%E2qKh5zO1d%Rf2X$^o^)?tYo>#c9bY4w3uV#ArStZ&9?Z9XG+{V-0e
zB@e$~oK_fPajyDioYq<nzA*G-oK`(>+3K5dTGd%F948s4HTGy+oQZZ5tgvii`k`@q
zA6WHWjMG|vQp-%{mWd!A#%Xmtq+^@vf0L?H(+{a9J*$P26H41NB?sfQ_9MRfdpHiZ
zZ;XR+T3uh%9CvMugK=6zm={PrKD2%g`WNH0=I+fNe?=VQwEA-3Du830*5Jq27pGMR
zyhB?e*<-6WPOIkv9eZ`qDl7Uuzc{Ud*J<ozb}ZwxjsPpKozJ+jesNk$=WFa-b}Zwx
z%Av31UC54QoL05bVL3CF^}sl-G0fp}wO__*9nJ&CIIWc&IJQs5X{{kv{X3ZB1XnE`
zP5aCcr&WUW%j1v_cK$ZKtu<MDL|Njr>L1V?{p;tT%^0UO^>4Z3mKdj1^Of8<#%ayv
zfn%K3%2aMX#%T@Y!N)kQ@T0l;7^l^l2aa)Cqj~7ZIIW^QaE#Mx$^*wZt?oSPgK=7;
z$HnrB)9O7wmRFqCL=GJ19*omE3S69ii<In><h(mQPOB!AAC_@iizrVnUiPDm)2e_D
zmwR<E<CIUFRtLD{T-(+e{iBIhW7!y|RgX2rHRK((+LO;bnsHi@F*A?Oj%A$I5U^?<
z?Z$fNN{rJQ{FIqTXU0}SN5*NbfLF#`9k#H>4jJOK7QruNmUGL{-tt)oW^bnGXsWOB
z*_)wWjMM6ROH4fj7T=RTV*102?KMzLULRzfRvFf3X?3ddNQ=|zZ^#`l#W=0%JaCND
zI$D*Rk8xUc=jX;TPHQ$tzVtW7X^mFuc$-qouJE^3y@$Yyh{Q5ZtIS}_vtt>j)n>3&
z*|Ch%T6~SxA(9!(v4U}0^TqkaX?32f_Xq3UoOVo11e}c1I*RzHPvJ1wY+;QL=NYF}
zZ#cTw&q4b#POA(t&vGwi(BeQ{*gCThVVu_V9Xifx*urX^^NG`{G4h{VpFDMCoR(9f
z>+D}Gc^|)FoYvgQ8v8_MEbEtXTKjR0<6IoO`gZVo<Ftx!FR`@MQ*KV%RuS+pPOI&0
zx_*CVVb@W=jMJJ#jFt3}zpS5wHe;OD0ki*g%I{Krn5TYe2gYg5=NYFpm`D5-<Fsn>
zh?ioV)>@u%TEjWwhgc5AX)WiGFXOa&^N53DoK{&LIL2vB-k&=Tig8*+dEgkQRgp)1
zFixxay}9#coYr`raa#2`>VxB*jMI83CaST%3zl2HW%d?Z>}$m8dF71Lni<tH1G#0`
z?=Vhl5$nO-ICiy9-Im^JEg3S!X*GT#CT`{4<dT)AmM`eA$7LrJK|YMr8a)yhucQpV
zd&lyC9Y}=-_}Y&bO74GyqaX9YD8yYHa%@k<ZLysemtqeJ*ZW@Q#iE^>y=RVz5&T{Q
zZ1u~d;<v;W{XW&Eb$M*n5aZRa&BJStq>$Gj`oOWYDJC8(@aSgh&T~DS^?e93O@EAv
zCo{=BWM5lV`!P$9>HmFHoa&V^wtu&6dv)Et6fsW2C&aSGctwCI`)yR*n2GmO>Ac;L
zY0kkr1Wf-*RD3i;y%&7U=2bCXhaoeAdhTF-ASHc8&EZ@zUaQm_I$YqzS}|Uwh;JJE
zWmL>((!q6~w7NFl0GZ_%Wae!^e%-)S7R5xu%d6|$b&nJrXU*j}u2*&OaeC5^X24nY
zmuO}``bW1<gdw*EnI7nR9*$l1vSPf#h<O@6CMN#bTffFXKWX!-ck(n+2D}$~dC`VU
zj2G?D3)}!=ygI!&Szl@cLPfRQAT6L8PJQw?>WcSLZE_Zz2QWug&+7)U_xWS)XX+$F
zVN9dsdZQ$a{h8Os#LIE**ku>xM}LqCP%#}l;{e}#S4<S3GJ;j<{XoIzpQme339$|L
zKxT7yOl-p*ZSa7P%(J##)wP{*$dtb)Cg1lRT=tQ9xw}m;p9RRQ-WL;fEX!KDOyJ{|
zYC6uV<P79<Sxh|NTj!>)_?A1Lf&%khS&{iRfkV{9#OpKoc)>~O<r{=d-32l673vD{
zWZfBGbH$4)n@mBb==Cx28*e^Z*T5&O^6C0I3YnS<WAfdAzWJPO%ES6nF+JsHqFv+O
zmtR3GmyGfW^@c<36ZD}b;OEcF4^Mjy06+YQj*ANYciLD|@V{)GRGil&WU9Xw6%pF&
zb?GvJZ={!f1v0CTYnga{GG%AMUuU#TV}3GCkU98;sCbsw47R1q6dbhc-wB0bgF(m?
zJ()cY>L4&(pT_-xh2Xv0;x#_<fpp$Q$jm&Eowu+IbBzb1;%Qtz4Sv$%H9miu&8zkd
zY9KR#y}Uc2yN^%owquGrfQ{tPVGx*^`?L;^<<@~Vo1zY1&tA4gVERU)VufY<i4Sk7
zT{cx0o6pAhn?v6kV8$MZir<sBU^U%mE7EzpAhVW5-v*TF05DaLMa5SF9=n=0eMtK?
zyBjA|aE-fZtSiQgZI5=GZBB^O*pAB5%i(&?rS3x-A=7kSLh!wE!5SYK&-*iE8;4B)
z^$BqaWg2~C{>5sq=!@BpOd@q0mk{UUGl-Pz6XWj=-cxYn@g@|U6G|-e<X^T}wz`L%
ztT8ANFw`L(e8>?)_zZUX=;@9JNV|8f26BT)Yp;r`>!>(R>aFYWYOAQx(9Tp;9-x#z
zjI{XbjmZ~7mVcYXrrtvM2xH4Qx2JtpU!mgq&9neh5?)nQ9X*~?K$i*w=O7jTu~yEF
zEbL7>L|qWWdFJdNGGj31mUbw{b5D3|c$%0SzGtg1)_oYMt~@I4!)LJ1ss}mdsMr1I
zAxG-Vwj-d=H1Y4V@F=9YF7JeHL~&WlxX)26luakvFpP8rd$DqEH{#A?i#8;Ek=S~q
z<uBryi1-YSyRm#hjM1Ig9;Ct1xWZ0k$BqJf@Q~)6&W@c0w(3h7JDVN525kLhdJk^i
zjrEqT96q%=u6dW-SZ~?*j-55^{YX0;&5rE@wi|I`5-a|Y>QhmNHg7)l)Oe1*&RXQ=
zvCEQ;rwsN8BSqerknd^<;yCHVmnLr+l<SW={M3B5BW_}!U1sHH#?Q;_PC6E92EG@m
z^reotjWSI>GM;Bf23p}XCVICvwAJ;^{hNq@d!A`HA?_vrejok|Y@M*sV$(?ROO7z=
z!})kZloo(vA)Q0Mw>#Ad7hG*9*~Ii%(FTsj+wd-C>QV8>RGpgf>{6YtZV((Rh9Fb=
zvbcDJGF|C11y7iaC=`|U<h#E5UK$toQD)Rf<_uc~Zwxcff>yek=nD0XPGZ@DI#qyo
z@Q#EykG5D$=MSi*nTgNH+P@j!8agg2!r*rKmU>4UyAc^{OW*4GbFJ)CT)1o9KG+4^
zfgi`@J4{_T<AW7;`5k#b(kNu+kHo}P_;ksjy#+2w#Sd~ks`%HK|NF`l3P&3qMXLO5
zOq`FpaPes!+<QW5?asdB@PFnn6G0xle%5g`Ch9Zf6L`?7KUB5tVt9<dAjb%0pM7o|
zi{Lo)yXVGH4!>&n`E%pw1c&%dOuRIcJ>2s#GlQY8%RLm@gR#}aKYMN*N5L_(g8iRN
zdi<-^*6~6ctCm<Tf_hY=eYO2`;~ezEUT}n0W8#}Q_VYt`c!%=CgOHhA&R>SQ@;!3m
zzn`1U%Aw%!FE-A>@^*qF^5<B_cSE?ZiK+R?2xO}M>J!5t=U02!|FLtGeb8ZG!%v`Z
zL0&jajf3nbE=~0lNAcs}<G6p%4|j#aalTV}40Qf}#=T0s=tyNwY#p&*$6k?_Q|&!m
zZLqXMH?Rj6V&e0e{O{A2|DlH^{}^OS9*c=rkiYUzsqyI=-M?Ne%^<?~eGb@e*n#s?
zmmNA3rVQs-iGf|O^I~YLH>YeB#=5arM5TRQT#c!Io%z%OR|=c%^z!NQ%MvkrJ>K>J
zzlQw(!HYNJEhocf%+}A38Hdb4%(~h$$s{ZpozDVf4jf)zJ|)->srg1sd?Qmn?ssRZ
zxfNu_o{XvIkwY#y2h-*8gjq;?_CjVBHh85sAJoBCRRt0^3S2L^v*GAhhk@Jt&6xPM
zmrv_(mD@aW4JQiGzA(0SdS#$PY7WXtmzr{1i6d4cuiI2XCIb06w2>CCe6#kC>-Bqw
zuhE~tQP&>GEiJ~xR<E4a)%^~1B{L40-r4;759YG~nT~J8#7UXjTHG><UeA{x7P;;_
z80);cNngH23eW}@!3Jzg4)8^&$8s;8Hni%o6Sxxef7$Ahe0+~w4Rp?iqi&PHjX=-$
zdh^vb?6r#Kgj)4C)}s?LArq=r)jE*xk*ohM?yb$hhewduZSp$n+eM*^Ec)7ze1~u|
z_`2s};>k?5zs6#~)c)fZh2t4^1Ev9Kg;}?g;O~6Or@z<bSF3L|)n#3UA+rLR2xQLj
zmT`NkZ!7^e0=?6&xu8CG==!AnYk->q*FSo>bpD>XHZM(@*?QDl0W1$=s~2GZmP~xc
z#=0M+zfD1=0)0b+R|dM8xOq-mh+W3#2*!n4FIM{XZDxp)*v&<lHvn7bi+x)X%X}SR
zkNz+wZoxbw=vZTuu|u0x&v*cW8RuD*nD!1^c7f-pwmt;T1JA_74c`1Ur+popeNh;=
z!;oo#Oj>Np&Q#s<J#rJ!_4Qs}*sIH`+s)5MnZWhGy*N`Q_vV;cGO$R|&}Hrt(e@qS
ztNQoc*S9NxJpk<fANa&M>b!eWtx)z+)4-RYOdrprtGnaR>WB5<D0u<=A9IZdGx0gD
z`gE7w)3MNh+Q2stzP%av?AJm?U0Vit0b8og$Z_K!xEiKo>U~w<^NzD`u~g%tf$eG$
zGQC(AK9M1RuZ#oSX2c#ZVBV9avurEe<xz9L+K_T?Rq?6oo^<30cv`?SbWAk!JDfja
z`3hnq>@{FQ>pu#P?!u_JErb59{S6eFWj+F#Wym~`NyhHI(LqqAs2INYyr}5TB*Veq
z%*h}_UyVSf5c%Bfl~MD)Skh2hFUD5Se>En~*yNd;YTq_n8oG;<ebFdnmS$q&Zf_oF
zvjKXu23O+uSzraQOJ1yLx17pYWuQzD@ydsW5-LWd$*2Fa*QKZw$}qNi>LUs93(9Zz
zk@=jJk1l&BWX2v$h*Pls40ij-e8Q4JJ`r$_KxXxiKF>2T<@vlN6Ak&UnfV^M1HXQ5
z9OZ~lp8vyh<LCrO&#yMlLAxIWhkzbG#D{A=qV3_gW@c>l@GsXVv-xDq0sk!~zMml<
zZ=VqXt{yT~Ux|s6Gx)aW8kK44s_TF}Irf7iJhgF-Y<tBVhr&oh#kjtO&tSjhgJ?^f
zA+jl%m@JM32T#=41KF`Xz%~PWC3#2P*c~3;QD7YCAhCzCV`qU~J3-$UJ?+LCec9Kt
zY`iv50v!_g49;f8X0s9dv@p^*Vv~PF9;D<Lqxv*8_0W9|^KC$ytV&?C0Dj(`uUSJG
zn{q$B3s`CYWjB@sscru;V8!_f@iX%B*j$`qzjucQqwv&W4ymMC>#*kL_39wtpEDO|
z9g5acdkNsRb;xEX<{3tsy5A8uf-g<K?`i$e_Yq59ntD%uSo%`$19)#QK7*xh{k&zN
zFI567?OEZ*+GU{*^rc?tD|u_&ST8SqsS;SpTkpntdAT<{{Xs`;^|QnG-Sx!lOjFP|
zA8a46{U6r)HoJB3>N^f>HLz0OPB+%8?-5}8ps%z;uN&*-4F=Gs0V{b2-B_D9o3Dgn
zOQxzH)QXqm)8#AM=<(`z2fvm5xHkR%j=&`n#Qla2q?s=z#C0e`aM-O+z`R_zHq;EO
zvtNbxsWtitK3gES9iPENmYlVZRfgYYkjfrOsQJu{g=<RfcV#PU3FN~_v!8XptCQ!e
zkveexczjA5;FIUse^h@i9nZ2J^x&yuAJR-)_V?b9cMPe_hj$9+M}2sY5Fd2>_eJ&o
zDR~8KKj~Ax%{bre;jIL`66ZyMBkspXaNe@1nZwxYL-c2q;q|!9n;h{Q%KXwt=8LFd
zGmnD|`)yv2+mC$SN1083PW5Z5-{vr6Chanh8Q_Zoj=UZeJjucvy}snmgL<t&W^`Lz
zmE~nVGCpOgL>rpGJ3Nn4uM2!+Jo&IJZESa_V_B9<Etw2uIRO0lR{g%xW(#l1@`$@E
z*?c&R{F(ZGUMv0y<qdYF^A+QF{@L*x^l$QZP2f5zKFx4tR2Z~WP%#c>JES&iOatv6
zMyfwED*gqZ!Tss_1U_n!>oKtr*ctSRHQblLaZ(|Sa|QQrf&jY}6{pvSpXbV=;@|KY
z9P{D-SUUe9U>iP}o8Qk?Y)7=!;K79SMPn<TXL%<*=lwXsz)23=Z*>-q4F`&69%m)(
zR)gP~PRxuU2mkzHk~nUMkt$y7h!y(6l#gu=TeiXej(e+)v$Rw_ldlV@@5OQPSMsg;
z@XfmU+zjq-es*CVEK_w!t+)gG|Hdxb4-0mikT;GH*mr!hJG-MUg~7x2$iDc{>9t}P
zbT)h@oN+T<$?A*BfgM6BE3Fl8@WG$6DFr8X8mZ;Qwemg59`3+W3M%)SSAea4sk+W?
zus6z~DHe*cJougZvM=rd?yER9IIVBMEE4Jc93ZQKsRO<)Tr0k8>3eD4^WJ&v-N!J9
ztpH&Ogn#X;kHKK~JdV#tr;0WOrEEWBf@jvs{U?)`B@2H@ioQK1sq~zJ>=<M}W9ezj
zK4=M0Px@fvS?HJi@#?Arw8LXpEiG|v3V6mw6qVHqgr6sEay?bUch*Baey_mqem46j
zs~-G(E)044T=&_v(!Y%z0yoIQ;|dmH)sXmS_nFj-azo{{GG5Eb=|}X+x@5U)&aD+=
zR^1q1zSs6WR3_UxeRc7?S`qc}{k8&^cL$z!yROV{4D#i#uNAdce&|!wOo{c6=djY%
zxUWoKJA%~thFTHNgnuH1uL8CZxI=HO71vsLIjpIDQ`QJFQJOIy8jtxzfG>Vit$4j9
z2fYISAWaO#cBb+nz6-ee3)AtRHh5ghvCA<6{J`I(l_T)5!FQ(ctdm*bXCt-pJ_b{7
zx?ao<Fw251?s1pV%OG0>U)vw8m2sX%_A>1%_1Y&{hAQADfV&Z&250L2bi3|R8Gimn
zd(*$_<F)b{pW%@9R(pWV%{)DV=D_Hw#-Ij#PC%{_pGGcvcktZ>*UI8ht}Z0+qgM*E
zT>VH(kU7(mxmuPh7Lvm)&WDl4k%|(v;??*x+^9==73MLVBiAfa4KU|em@Sek>f&0(
z?;XJXorMF}?bM1~Y-6RUt1)13t7$U7tCZTZ?bqP<Dg1t!^*cC}>W{@jozhcOKhXhf
z`9-zjQaAQa<tDLELSw`D{Q$7tz<PKCajhKN>jW^<z`V`kQ`0=P(N1VIq&8n!K~CsO
z_C`FE*I-v6@6^@GHMV6-6N(s<*XEQUp0*~%WSKcH-4D6zt$b1DWIMl0m&4Dm8X-f!
zT82FLa!tP4H_=j(BO+!5@3Q>galMry7BVj$r(U(8Y<U%5QY&7No|k<&DH`gqa<0`z
zQ_m7bJ9J<Afck%ve+?^z$#T!H7K(-cDinvUbK(z$qWL$4V$nJm{9~c$#yP*guHP1l
zyO170`V7*eNV7;!BOOHw9xW7`k<LL%Al-=6jWmcff;53NgY-1gZ;%4ND->a*a-=Gx
z3z6!Pu0!fX>P310iGO4Gd>CmG>8nWJMB?8Od@doaA{G7~`6ImysTwJYRF8BuQVUWC
z(jKI{klusz0Manhr;rXJeHrOdq$iNRgY@r6KSugF(r=K~kdFQDLh%Bm(~-)N&O@p}
zN+2~LU5(U&bTiT(q&t!Nk@h2f7-<yg^GFj&k0KpLdJ5^sNWVf_MGBy<UVwBuQW?^#
zk=}shAT=Oehs3}CsgM7+>f=fg>)gG!y{>gvTW33>1!8;JTf5t@YTwz~)v<d|d#w=P
z5>9((dv|+m&yMaL+gdxXYTwqqWA`q+nIgWcyM2%Mv^aHByk|#u!=ByS+V}1iEt?X1
z+S}`QY~9nk=MM4Mri<FUWBc~(Y2Ve|*nzCtE^ZUzFFae{y0<&NXV30ELYx@D_se#-
z?d#NfL5o_RBWZ10+a3~&rvn%7f<~>KJMK)=?LYAwbnD!`?Uwd7r+wR=_MONPqrZJV
z-m|Tvb=OVp;urSWi+3f_e+pc@*NMiis)wG@JG$HBJwm*?0N-v)%TSzKP`|siO_vk;
zHWysBud{mx#Ts{Cv!ks&*3r60e5c?_*s^tR%D_Uzf>*gp-_7rD*#*^5BW+N!y^Hov
z?C3;^L|^c#&i3{$@%~_A=ib^*ln~=Mk7;J{0Up6nSGRWVYZo8nH;}1s{}Q}<$DZze
zt(~x9H|kJ`e=}#^yssUVBfb{ArgcYmV)ve_cI>*Tv;B&#Hxu?u(5T<IJ6R^oRkmzz
z+uhZ^ON4Q>x4RX5uN7N5_qMm+!mCAFSh<L}+j2YH20?Kbh%H-gYVY3Jx?@-Co}2dK
zxldcRbZ*<SZFgIHS1anE7T<Sn-Lh@po-I3DVdu;6y=%*s_FcE_*aK%n+_e0@eJ2D2
zA{n=A+1uW|rM0VTOZOdJIP-q7Wm`M^PGI%5rG3wyUAwtox@G&0&aL~l<0*Puws-F3
z(eazM?AX0kh_`RrvU`^l_{=6!Dc;iqTW;U6YiH}taKnoNty_2R=@yp<&>$r9RROra
zwD^|5_HAr7LTn9e-`=@zZ-)>!2ewOlbOyF}?d#qqcFNDaqARdn+TvDzLSkQFyEM}6
zf$iPxot@&2z;<n;w*_D!lo;Ca==N>mfxwQvw{KG={8#{4w|2H~+fBr1V5in)EU>eE
z=e7>Co6pFjF4W{_d9-u)ZS9Cj?%I93cqq`dXUDGY?LvGpK;`I*hj@f`^d){GuP+Cn
zrYzo600vQ+;T}31-$u(l8rZwzrd_R_LOdSWtLbI}d-rZ@-38t!1ADvoY}?s|NEdmu
z8zuXOJfc3|;t^_vt$UWo+q-w{ge|_!<4!n{_zxcSY~QmJZM1v$?VY=ChqH@kdAzTy
zi^o3?>_cOPVbNaY5p-S-+_v46?013Nx9#1=d{=p-bNB;~We&#{;7H~mICuEJkS>j1
zd3n74wdcLM4NBs#1Uh)r&b_y7+taNO<@o(?G1)eto&M+VZ_5G)|0^Q8kpAcIZ_fg!
Y6<;h$k;)h9a9!l$zdZx|jhFcU0F_vEg8%>k

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1j b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1j
deleted file mode 100644
index d8c1eddeb8aea2cce4eb2689cf644baa379b1253..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2048
zcmcIkO=ufO6n^@tybi|N6pPAutK9|>atMi_KiQ;f@5Y$mLkPb0P-sPIAqNxG7HYMu
z*Ar1(QH&#&P+C)Da0&F#L&?F1wAdRTgafGzxwH^h5h0Esw3bjy*n>LTH(ISFZ5l!g
zeIUJg^Sw9U%=czT*0*wtx(vY}rISH`cbYd=isf^#RB2u}7sJ3&x_wcOgRrr-w)XG=
z3>8iDj-h~6{l2(tSuk{IW#xKv7P74`OtYDW31d6IZA`!{HBFOJm@4IRC0t+Dae#5o
zod!}s!`QQbTURWa?R6>Td7iC{i|29xEgB34BVovuE-7)G#|TdbKxszK;DA!0?RCt~
zQ5`aNKA*?=Pg={Lv-pF@#U&OGy>-VlAHNHPP)bN=UD|?%Ees2G18iJJpf;5Dby?pp
zfz?PP8WzCT{pOA0@**gcm#<y>YEqH2Hd<B&9!`EH0WV*)e_r?{d(4~n{L^sMClnRW
z0;ka0737DrVl>1=Ytbt;s&El5l+<`hOY@LA^b!yGZ<CyMln=#XN%DL;Twtl##X;tY
zL}nn!h1s|OlEyp$$L+;pXAmt&7vBEiOf0s?aRA@Ec|j@=h6j#}v~g*=aH5Tm90@S|
zL}6M2;HQrZ5xh4L3_rJg{7VTmR)Rn6<)w7Ok`Esm4l|q|84;F_b@9NYa@l}SvzQ!!
zNCajI$*DLHjg4^zGy?IdWMKv(E)Jk*A`r{PBVZ8_H5qvvSlw9#2kqv@266Ip;E*}u
zY?4g}JLj|m0}M(k&aL(JTMn>n<0I$h`uYw|>a=WCDPHJ~8BV=6uL!6B8X-i-`)~E(
ztG~YYY6r&@#P3`Cef7V8EX%xGuOZ%QJS_L(tM~fr`}zI*Vf<S?{QnSFw|e*y_s4zw
zi1)=Pc{(L42j}<mOR2b^D7xN0k9*#}{lJi*$a1z9@8gHiz;HrQu+OeNiy!shn;-A$
z>*qHd)c+N)KN|S?S-sxrAJGu^@nb#e|DxMp+)}&WJ$&viyZ`?;-eu~HeEsm_em(rS
zUymnnpB|llAM|fQRTDxqI$%MyQN@qUZ%X$44^?p(^aib$TXx2e3-S0Ed!gd<fBjV1
z?c$s;K3}UlhL`X0`tO@Ekr0tSP|e`Oi97J}J@4_yZ<j0d34URMH5@IpfDZy~$;7Jz
zL0zcV{^+@f?e9+4j*ga2M^2X{jifBFQZP8$DRE1mg`Ybq?x<1qKi3bwpp2>Ydz++c
z-~O{wcjn%>JEx9D!;c=_HGccr)<OfK__})PHLKdN^<Ditb^O$rC`JcnTf09pfs$9x
VJI?v5$*1{*ijo^@;y?%A;BQrTW)}be

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1k b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.1k
deleted file mode 100644
index 92d611b2067ef43547349068eedcccb33b849b6f..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2048
zcmcIl!E4)Q6o0Z^+iRUjEADVXv9#dB4jmC&mnqD(g$X5xF!~o5F+wP#G~NzF4B=>A
z$igU@5oNFtlo9AX^fbDVXeD?#IN9iBIc$zv*0Rfta7)mr_IXdT<upn!W9%LDeeeC=
zd%y4deV-&zy<b~YMTkTQDMbK2=-gW|_OHUNR_Ct17=t7syVu1Guv_cv>rZ}%l%eYn
zs(CQ24P)6fA$4<Q<!<K&DDKy~-jShD-Cf$P7T^Zab)68HY}9HE>@TV~LBG}ugH}gF
zKd^sWXBfKQmk@?wyuR4HRs(QJBoc|opw_sV&tM!q+!+8N6|sU7LRf!PF}p@os5nbY
zOBnyuUH;PZKRz;Ud48(=K-Z6EK+_1(w0>XWg6*)wtYd?NeOTf^qpgZ+y8))1&Dtiw
z{YRa9#_}TMOP}4j^Gzu)UUz<(KTzHnjEaM%h`_+u7d$Y7c#s#uJ$)!BcL6f$GX<P(
z8C^67lxJ$jn?+;P`B85oBmvCG>pTN-fXP@47#RSMlwo+FOkfaRka$dG0OA_rIFSI7
z$;TH;V}K{ZOAD<tr3;Ufm|4cux`thW8cq8+KUL>_JUxmlC@=8!DIQx)U1H-=DhiR<
znfIHD6^(xW<9sm-mi4r08K(H^+2NRnGwC!ty?cy5eB}N>v;_tGQ&H+1eXX9`Ik4mn
z`W(90e?ztoc5?M=5Jx;QL<8i_LrWIup#<V_5M=An6al*b(JGF+wboPwZ>OM1c#n<N
z>^mc`_&z=m-`?)yCi;roeo`%rphCWB6{oqn{i|0mX<o#u|8QdBypQ6e^4I?Is;dZQ
zKhUp#vH#ZEUY{RKk8jI3>2GiL`EhyvdQSSywN0NNG>-z;6Y}@I^7#A9L;R$VdzN`#
zKqY&oczO)@0eFF7L{Y(W>Y1lU!0$(r8A0GHl>k?c`Fo*AER_+30Y2al3c~!J{^QxR
z0UYM{^}E9M^~X0e%<rEc+t(NI5Pwhq>_C6-yk;&3{Q}nG@&Cq;nfkMk9$`GJM;H(5
zaS9LV;otu~WpF;qyG4#m4J809K{mBh<rCHF+}qqRer>8xkD3RAx*+i)mmT5gL_DLq
z?spqM%RxNJUY=<g?u+-xyJ!A=$MLNouXqK^=>&y87{ReEGl&Ocz%L8c_P*-`{Qfr)
zV6{L+qY1PqA;iUcH>d+PUnQ;PeBgi7yXSEA&DZwEhsJk!NyB&46u9xZ?oSO#(oEUL
zi_O0jpXGTUmnCWP65GtD@+a$O1*V6a+RN&@pInT4xNT`bbNTnGfBx3BY^QnD?H2!T
z9nQ^9aEb4qKPT-~$D|S*J;oIa_(8Q@SJ~u7iX6?+l<GLH^N0Oyu%BEyRV=2`IleC0
Ywp8bHx2L<^>DxI-r3p!=g0xfPKhK_%L;wH)

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.cla b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.cla
deleted file mode 100644
index 298d9068868a581aba53d4f337d0d9fd5f37c0c6..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 32
kcmZSh&whY`{eV4#1(>#Au(x1mIAG7t@Pplg;ef?)0F<Z+MF0Q*

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.u b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.u
deleted file mode 100644
index 8f554dec3872585ed5282c4dbd3aae242af74d84..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2048
zcmcgtU5pb|6uvW^d;1GJvn*s533Rp*t0u5JlFd3U<85b4X@G6hmcM9R^Z_@<V2Kaq
zZ_64WJeU~co5mP?!Ke?_#H2h)VWRF(Cc(s|#$@6y2`vxcvYIuEFjLP=!5E%=@;1G5
z&OPUT=iGb0d+rb#tLn(7Zwv3vWzp$kImSOQ$mN|0ZAUhP&S?5KTnh0B>tVdd70x6x
z<C)^CNJj`~im$+zPwdR<Z}jQMh`xaJmwkFEVjN$sf4dqm_2rO$$e$`LRb{3WP|%UU
zce6LGoAyl!X#(2EOrtwrnGcZJh)68m5;M!#oW<rgWLhDUBJ&JUc)HX`$FVtu#fU_6
z10pp)@SCOZqCIcT&;NKyWdM26aQ}~F<ThRPL1*{rm%@54qZb(cJx2eUfqYjOXssRy
z>H8&pUP3HS@~Onwewy2v*q_SNp^ku%(nlK;abig*A#%_stxBL47o{D{M1RHa_h%)n
z9gfAOoEJxy!8F?PTjhX(qV&M@x%wQ;W)Ko+4luC9Cq$pbC#M{HaQ!i-81FygbXM~5
zz}jr<fioB-rP$#ZL8~~?8b$_8eQX{~nW>~}Gpl$zR_Tq23oDVtXy!1ZFtl}7W@uGH
z2MB6PXtJqxWOSsPd&te*hRnr)n?Fd2#>wd0RwcN#7T;u*gH|Qv^u(D_s~lRgD%e>&
z7_hcr3B@Yu#S6b&WvvQnd}fu2ewD4tJT)^&t(!ZMaE)!N(;y6?G0B%8%hjgjOOj=X
zuaW7dv~I%yP7L5A_*do4RR0-uL%z@r>4t*@e-q_C7t%yes&g)?#kRY7uM}Dkz>NfE
zag*=|E8g{Dx<g$T;<|`FF#Y4`8ZL^To4t&|MFQ!>t`yDgN##2@67deVgI9(go-Z8m
zzZALSk<w+SgmNkm8wt%DlhD5EBWV(rci@py0)<w=4OZ>#c-Ott8K_f_jRNA@=4rne
z14!Vjl%r&@sRm?$nuq+J2P}F48&x?%f!~d0;|F(#fv9M`$KC(4BM23=Y(6zap>5Al
zPjO{WkUJQtoFJG9Z=ukyK}q84TR|vG_^_5wjb(}*9N=>KRG~nJ9^Ikj?qV@J4hA;2
zyRaR`vw12%Zj5l5@j@zJq>1rtaXZ{REt?td`1(TI@~M>P++o*qlqT}K+;kqcq31`2
zI!jPQX03Uv!ki^23*6T1pgoL$YRE1#);3ms;{Do{HV5^BiK5`v%QrY{oFOR4%yq1o
z_p2bM6AxY=go_Z<|Ky;MEE@j}mSVe$YXh)?Jz(2I-h-`!oOQ_8NM3mjS6V%G8O8KB
zais^Er`f^PmkZd7RjJL4mJPEMQP;^~`iw{wOw$c58f|TW`ZLk5glT%JwZZX?Jbhts
z;|ZrQxN2AiG8xu+;@(%7v?$I_ITuH6xfD7J1Tus*XsUJht$y*Eg6IU)hrK;tPTbjh
z>I<k?U!0OLHPmU@M-?Bf&4~9T*5&*9rof{96HYPudsSjJGSxJy5~bu^)74Hq<UG3%
zM7PfPp`V1_<GrDv15ld@P&z;jB>=FBpN`6YT7>~ft0mUz<}tU1H}=+DwyPZES%n<T
z+hN1Jhs|Ch9E`LLbJTT8x5NpB&@6zw15iDv77c)2i?U)wL6fbzQ;(mh#Y@L);1R_R
zbM-mD!$w0#N1u`j!1}4Onbzts#bM%;4*S!7KP;t6`kKNB*A_nJ+Um3NCj~*~7GQ&*
zIEzw`M))nU7=IrUf-CDT==IC1;gUjmgPKs4xsvEWGywci{1nnBRQ#y1z3v8zioy|2
z>=lw6B<H?SDwS8!w)k$_on{Cxb;qN(8rk@5wGKA%rVYgan9AG3%$z-pSEw81G1xj(
zYWcor<X}P$CJpn3U(u*MrO8J%Wem2Xht}f0qnoow<&)ZVEFafQc*DHyo$+3np!>oE
yla;NtnY8q4PMGTqKj`Q08xleT8Z~T5qvrX5lBCXGQ35Y9o?NWOxluXkp3&a})|sOK

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.v
deleted file mode 100644
index ce7f3ea7655b3d8a4fcc81635c93ab71bffd1ee2..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2048
zcmd5+Piz!b7=JT6GrQaFZfBs>SuJ+fiFN`=$4R>`Bb3(`sRqNYpe-gQEt<4=0h>V9
zBCJg~c<~^b5b>g1hz*BLPeVLZi|MkHaSR+<)MOGCvI`_YC2B0#H}!kFE2ZJ!)tT&@
z@B8-m{dwQ-d(TNLSKMgW%wVf%_FzldZHjovY{G-i-V0xa%w8}xAGH+TM8k5>c~|?(
zL<gKvr3E|+L8A|wuj7t+!PtTG27kcrW{e&Tf_o&?y=e4e`yp%x_J7tl6heTsA%!!f
z2_%7fWDeF|(#c6y<ViBkeNU1cBApF(9s<c<R^!Q^m*+?hbvWDUOR_A<F%OkM0wGC3
zB*$7B7vCn|mr#b}0z+|$LDro;<OoL&^Er|gtji_aL^$o`_)7Pnm*iuv)Zjt3A5MfJ
z&3Y_%x$if+CmU!RiX_p8-LoMtF@S~OtTz(y4zg8GUrg=uTT-r<<0{*IIkn5nF=^<R
z1w|=LM}a%(%X-q=jbP{Vp_2u{kLd00=@0}n*JJC#-4G2kk#_f?a!UqEC_(a8-2Iyo
zfEKRDGm?P3xcJG2ew_0~h2IEkad6Jpwe9{U?InLvdvRN~=CTAX(3knp=t};1`A{t8
z?remNmycGK0M5DV8f?g8Cq?<9SN0MgN4y;RRtZAkUdgsS)l=m=W;2c<QkENIjLcFA
zII75&w#yk(Mkqz@LfGk1qQ*Da*n)@hMheSOSd2-kY{7CTW#B|Ru%kZ#t+2L&$mkKM
zZ>t3&<&>0aL5tFK<c4%UvS3pn^<nhu@?3Qsz9`Slk{s`48SwP7s36vvP6O7<1`46t
z6!h0<A73H;gB8kIayT#pbbAThC&4%+GFS)!vn1}tiAq%QciStIa(VVoO0Sx~V)EG6
zQ=ES(#dc4OZbsnP2owqebP}3HvK-0so_eexj*7SG^j^F-Qz9j3pWF(MGAjfLgaYcI
zYD-xQJFt`}IgH2=hK%tu-Hc7*;`RKDU8|)I)N}w=d_ShN`&%{548UP)%F|}S_Om>U
zg&gyjbb-LI!a+&$O%SDE1J1vx`~mtl`7Rx4Ag|JD6`et)73g|4!S;?j`xQ}o8`?Y)
zx#2cN-19-(mK1J5dJcY@xCJ}G_5kL#v}YBjelor4$%M7n?8HLAn?|V?-t5BOG?R+*
zW)cK8#kuzp^s%I>QWEFZY<x<5KrK9jaP?W{nU=Z~Z2MO_M{AXfPcv`<@H7pOgnDfQ
zzo6?%2i`pK{O~5c7``8V5dJ%i9(gj1$V%KAVXe@dS(h0Ownb8y3%0SZy!r+n=y~nU
zmzOsntUiM<Y{B~RcB9Q147Q!`<i$sVJT6i`V$0yuU+rM#!cWl{a`tJwI}w#*^js-b
zG2ot!j=OzPcW2CfCu$mC4}d_%I2dB&H|wl(#=n+gozpO<{@0*R`4vznZRahGC!Gi`
z&;43}bRp+G_;fPPSdnxwa3c*ngBt6UpdYOBi<5=*mh%y;_vma3%(yKeKpj|xIz&;_
zHC+b=1cu_sZjM$Hf%NzMtB`(*Rx<(Wt*SZ+(*h~hIAdA}YNBNcP*SZbsFIPPLYP?2
zo;_Y^>(3WL;?m&p%GKJLqigzDCE&Evcd9=>4}Z_M4#8B91js?QtinYM*OeA_e~lGH
zKa`Tx+(ytNYTW>ZoR%<(Q&13W{!P8925F!W|0a}thTeD(;#$o2=?<i;%T@e}r37i>
zs`?N{w>wE~U@20+$R+5zE5|-0rx5)fC8wA>dq2g-XV{)v<*hVTo3-Li4OQ=fy7#~;
Q@5ct{zx*F__@5d60Xyr}fdBvi

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.w b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.w
deleted file mode 100644
index cfe60857df7631f7b2d2304f41390cd6d56a7833..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2048
zcmYjSUu+ab7@xgA+oLUH?^>=?Twu3%l+~QDEVW!N^g1ONL)07+fd>+hgb<#9golHI
z+w;xDgv2)=dGW!g3nAuwD%EQ3^|&aClo}`L1$)#)h<`$&*qQY=dw}L<zWrwAoA2-M
zn`^$hvH4M7)xO5`*rM0V3I=PN^TIyD^e*AYOYNdG7Ra#dU${CfQwzP@FSW-d&99Sg
z-jMkpZzhvE5rf8^=G4Y|p_lE23gO3;%)(&5%qrr52tNq#ZIQ0K33}U=n(+S-Wli``
ztk|4EBX<o^Cc@X`H8%kbjhmtzQ_I!-dbJF&ENWgKyA)m}Uz|&xcxuSmBD2mW={V^^
zn$@fW&lS%pmDDbzSnbPQN#PSof5P{4RGf_@85#7YfqhDqKWn7|VQtzNSHJ6`9G@NS
z6R!{qx(vH%M$M|CX&61x-Yco|3oNck%UP8<=jY4q%F!^a(&hG4W70}A&6LtoZ>Cd^
z5yssFV*Q=|`rPNO@c9L37zlmNJ@+|G!)z@1Kd0~AdFFJ-VKG9~@QD)Zq+IzPIj8bb
zsabYdx5^1ssoe{wQgY9Cr&5hK7bc9oH&kE~Mkp{73b;yO1SAv~dn&-~{V5vb_Gs!W
zy{o;(r-{?WGdyEFu5(}eyiQ$n#2U%Ej+=7{p%=`uRnA^;%DFOuW1VW%6{D&MCa#Kq
z>rhH&6>${VbL&`2?gkNlH%<rh6d3_n9Kg!$MRcO9BXOb(7$W1((yL;GE~gvPI;101
z$$DFWI?dY(+EMm0j$g#_HYl?TI4$c1oGN7yXiPeB6oy7SRq9d6wg5}0zW%6!96=UE
zjLfO3b@HVyS#iiyj+;*-T6nz=cDi6E3aKS-A7pxhBU*)z|2%Z~N=vNVu01^DY!;_A
zahC8S8b403VZnPeL#gO~0<*~k;e*EX5|nlNuu+;3P^zG7+~a6UberC#ER0Jdzg?#D
z>v<<3`Au@Ko8~^LIVdl=8!LhTa4rF{1TH~sU6rncG|k1reRmZ$ynY6Bo2(e|3|3tB
zqO3TkF!JeuSm7&6AT6A)Q+D}a$1crpL=z{`L+B)aJi?DeRb(l?a@(F_4-dKDFY%UW
z&0bY7YgZms=3Ho`%Y{DHD9<-)=;5j|rg=M=r=8zL_E&B4j!qVBat4zO>F4eA)}i>s
zP<$VR5);h>MBSY#=*;RJ+wSSCn1J83XRNb$9}5T+XPR%2B+(ueD`0R*Rl}`9<wW!3
zcAM-2t$N)PUiUr(-uPPi5K5Lvp`Ud;ik(+SuUQ$J9ZVA9x7Va=X=dh%eB1itveylm
zB%WPv{z>q1HkS!)pbKj=*l(M)dAy{4DdWGVW^JYzc;sU9IB6cGMP0p(_9Utqlk}e4
z`R(lRfO=>VvwCY4u1x^ea%{XPn}MLs0M=mVeO<m%n}4@9qn_nlb+JCI(FZ#;dVh4s
z5<gA&S#86H<}ngN!OJr4%l5dp4PRj08)kNv`A};@?FQ9knb9EAG}2}IQux7=T51np
z>g&3&htgu2%!`ciS23tl)5<zIz5*=RC*kl113D?d$Taz4e4qd;)0$$2!9>6Se4ZV4
z;}B@X%P`U6E#+F}M8RgY1(}wCGjfBMV+v2<CKmDL)im7_Mu5oI!Ob|L*XkTF6s_j2
zByZIVL#*Z;K8ouAy2RB<T$CJtEgd!}WFW8)=i82|*gL!3-0ykH_VAS-LL|f3ZQfdf
zcIX}+pdTwH`6Lj7YV}#TQvYjM&90?ION`=O8`Ur)m{H6aW}MVx7o}mXuZDG5RDnV#
z-btPj;cs>{O#_n#77cP{V48tt201GTvO(YkrW06BkjsT<IR`sxWCLQM9zhl(7X(BN
zN`fp22no*!2^7@s1F`5GK(~Z0(atyCvZ7w}Od-nTs`Ynq%sb2!{~P!X;H&Dan@PtF
M0sKvfelNoQ1+Q3C6aWAK

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.y b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.y
deleted file mode 100644
index 03c2e3bff6bdec3c47f0ce5c703faf1c1f1fe5ec..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2048
zcmdT_|8G-O6u<BFwJW1^?~S2vY-G0^k{2;j9<!-0^Le|i8%tPUY4;_;M7Bg=KNu;B
zb~q^&j2dH<pfPhXr0|o$ABMkJoQ4z$(5}>!ACQswv@=<Y(Zo&z0`lJTymnhO{sq1!
zz2}^J&gXv4J@=j~(IkoQ=Z^BzA`_8QxgE$AB-6GnH*!Uk>qEI;QN@`1xjIU<L>Jt4
zsexp#hz%q+igLqz#Y3h50PG@5F0$)Phuwlrbs-<mz<;N!r%R1FI*K)F)NxoJ$%7JY
zgOC5+l?uP6E9qFVLw{`H>PP(iX8yOK1$7~J2jvP#ouBvIH_?W%6_&7!$q#^|=dbA%
zk<G9f{g!vF<bX_8=k7ct8zLIND6`pX5+d0sc4kMl7{Znhc<PuIMcJKNj1rbK%G9jF
z>TFVrTD1d=8TKdthjf~Bh^Glm6`$7E3D0RUrf5lGTDB+<yjwe8=k-cfQmoT0c#F2z
zqP;+K7&RU)w&=}nhewnjh=|DR08?Ut`mD@C*p@1-+ZEHIz?k~P>w4K;uSF?-0mvrt
zk8%S9@pH>*@ZU<OfXXQXv%7(XvP5GTGRlr(%Tb;>0XgY*Z%)7K&Sb-wk?VO{UYi{i
z=&WHTRbkg=(u?V=Kzr^(j%el6%$;_uSLe0)jOId+vLl%Wa0OWEjPSe`WB*-9HOA=7
zoEoduS+7-gs?pkB6}F^UH$1M_VMq25wrlNF_Dk&mdNny4YSL-pVE_v2cA-vB%pPgd
zQ?r&Py&(89rr&6~vK_b%5M9WX`=UuokePH|E?>I7@A0ye%{_yzT}Y-UbV{&hcVcS8
z#AQZ{GHN?hiT9<U4m$QSdfrQ4j^8$6S}HK7$&AqI#)~G7-PvH`%rE2g0gm=k1!Qpv
z2FRGPPgP=1k(vB5Zo$Oef9ZO*Phd8&JiV#xtOu~<wF~KNAFcry4Y*8PW|t%Yf|?~$
z(oUkM^82MA(c^C0Ce}&wj2U~W5)LWBaWmJ3bF0&p4Ykcl6cn2x=FvK0vfc;_X&z=H
zZ2CXdOmFO*o93-;&$bO^%u7^W8mbEDl}qPSV{3p1ia-UeQlOc)NJ_JM9;H;z8cOvz
zDYbnS=WQ-=k2aT}3b&`>?z+&1))bkB;|nKFkK=o$!y-&%s1~ME2@Hlwr!VX`tSyNA
z=QDyYuN<uZi-57)O-L{pk4GZGpwS)u_)I=NLO_ojki(g;uBvB_#|>hn&L&{2Zyy?;
z`uc~(Hvc~3vz&p--_K0GG9cEs8{<=^|3$V-UQf09GnB!$9y1WjRu^!)F=kl<1xF(B
z;|UWgVgw<eTu9{$<$NlUHwtCY`LTnOiOGXw9<R|MgU-fr!d)OhCNegHvC+ECzi-cA
zxq#j9gZZOxy!rM!@4k2Z#D^bEPJMFHDBmi~<<qHiXFp98%H^`*4o2dUksxtnSRB51
zynJ(P&v!R&wr=Yl+#5B_npfLCicH(^4d}5{#D%(S<c5UCiYYw>eU}z(gge|)syK2d
zmW7ib#GxB=-z*F1mJ;{*va$feW^poH^|=RAjkv@;fvYg^xK!b~mJF(E7uMkMu`y~4
zK~ICO0)0`9(a^*=8`2s%3sM`|pR@&TFD_~Gng_a-hbm|uD+{(4t2P_hYEqhKbv@V)
zRc#Kitx0Geu7QigVxm|Iac_ZeSNtW!y$=ElNv!ahTH?c<T@s`^l$>pT1h%85CMnps
zJTCDJmx5U{`Q^Brg3L~K1@_Y%d-1)>izqW-fR_@KRX%Z5r)(E%JH=WbJZ-#AGu9qO
z=_bBFH|ZG+kS-+@G%WVoV8|c#2L{3h<FF0;LPY5y1Ka(ibFepT*w)(n2gBP#iqcQ|
zeY@Z$Ivq;LuyJ(15(p3YLke8ceqTTt9P)?4q%S~x2I6hLP`^LW=Oa4?y2;ijy<3f%
K4Ja5=djAHQ+~A1-

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.z b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/Neuer/warofbug.z
deleted file mode 100644
index d1ed656c834ecf3c281008da81049a44381e6019..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 2048
zcmc&!&u<$=6rNvRJ3rcNnwV~Bw_Ya#mR_=KixpPZW;V&TF>-8UJB@Nmaw$Ev;edh!
zSO)$93J0!9PwmNwiw{W1YA&``mM8}*A+6d<C_zF<l&We$c$YV}D<x_{2nl5lJ2T&#
z_ulv3elwx7xR}XZ;N^VT$!1r0zL>d?$vN3DdYUZdoTc&tASHL6&o33SnK`GN$>+jo
zVxUmWFJxvjWp_S|QdXMF7hUemUvzSFE-yQ?SvTZWrBFS!Rz0;*)lgJ64Sv?(=Zp{!
z#osWD5Xte^#55jHiRncAbwkYR*y2j5>=su-DzSXd1wy>MoacqCv*H#@AsdWlawWG|
z=5u*igb^hwP6;zNjk#y`HZdix1n6%E7K0KjQ5>Uqm=bYP?oF^Fm{80JiBUR8X)lUQ
zS#JTJ3{H$tDq$+)zPV?!WWKA^o8GD>`AIaZF!(xt<w(6@p$%_Uk63q;3bpPf{clji
zPaVO2>L~Wl4UD#ud!t_`_rU*A&6If(sS^!eGZD8C531Vl;=ltiv~YsW=5tFWKI@d+
zFp@z0nGqJ=ZKD^@H24RBVnprGMDHoDTDN%Gyu|^n1h@%M5bEOqddp4k3oujwnuMIK
zGv7|Y)Gb7dCDG-YgzmJgEne5s?d*g#%>Cr;381f^^e6pE<&kxr*PB+8PX(IJAV|v&
zl_!1$LFJdFsK1H48GllKY;E(pJ`B}FVF*Sqh?u$z2=s;7nnG+2xOEfI(|+=9H%Cn5
zfGiLFOT@o|yFIzdts6WjG-~Dzp4<|BYQZldgi<yZIV*(-VNE4mrCenNHL|8k8)~$w
z#y(XCw$y<y)j~rZ*@9+l@lJ*1cWGTCHb!W*Q;F=_%Yx60H?xbs>TE_j6%=R&^X@BB
z@Y6K$wmTIZQ~|iA90y<wx>47L+JnctP2RC(@3!#Y)Q)=V;H%Nk75qsDTJRP)>ir!S
zyNEvI)kTJPm~eZnJcK@`&FjDkLl*>>nINtgfMSm!&4Xptityb;5Yco&#F$QYF44{v
zGOD2y9|Ep^XUi$m{u5+l$00aGe*dGOI*rr86XRHC6Dz*}y}Gt%kAqdY_msHuJ^Y=t
zxh=#7ZFt%gx(qdV>l*!7!Jk1DL2SAWfm&WkWA-ulUt`|7PP|Z*(d98Ih*SbuC#gRm
zH{6_yTq6Vxb9U7l=ib{*8=KOG8Qp00uFGM4EwtucZFVVXLp5`R_gUFk`OR*$vuHH+
z(q3=zCM>Fe?4%QHoSn}UOYjI4-T6!zo;C6Eu=7jB@`79JqowYHbXbM`%e-*)4(gwD
z)gL@h{lvS!U;D(nwomyl_m%JbH|2xd0p(9USNcRqzboUu{+ag5LE)b?<bX{N@7F%K
p>^Sli=>ONA^dEGk|8r0JKeqeKl^^~G={s^wVs{Q%<NqXuzW}i^6(0Zq

diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/gfx1.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/gfx1.vhd
deleted file mode 100644
index 1b3ce2c4..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/ROM/gfx1.vhd	
+++ /dev/null
@@ -1,547 +0,0 @@
--- generated with romgen v3.0 by MikeJ
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-library UNISIM;
-  use UNISIM.Vcomponents.all;
-
-entity GFX1 is
-  port (
-    CLK         : in    std_logic;
-    ENA         : in    std_logic;
-    ADDR        : in    std_logic_vector(11 downto 0);
-    DATA        : out   std_logic_vector(7 downto 0)
-    );
-end;
-
-architecture RTL of GFX1 is
-
-
-  type ROM_ARRAY is array(0 to 4095) of std_logic_vector(7 downto 0);
-  constant ROM : ROM_ARRAY := (
-    x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0000
-    x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0008
-    x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0010
-    x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0018
-    x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0020
-    x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0028
-    x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0030
-    x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0038
-    x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0040
-    x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0048
-    x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0050
-    x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0058
-    x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0060
-    x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0068
-    x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0070
-    x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0078
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0080
-    x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0088
-    x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0090
-    x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0098
-    x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x00A0
-    x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x00A8
-    x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x00B0
-    x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x00B8
-    x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x00C0
-    x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x00C8
-    x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x00D0
-    x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x00D8
-    x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x00E0
-    x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x00E8
-    x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x00F0
-    x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x00F8
-    x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0100
-    x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0108
-    x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0110
-    x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0118
-    x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0120
-    x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0128
-    x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0130
-    x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0138
-    x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0140
-    x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0148
-    x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0150
-    x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0158
-    x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0160
-    x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0168
-    x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0170
-    x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0178
-    x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0180
-    x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0188
-    x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0190
-    x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0198
-    x"00",x"00",x"00",x"03",x"0F",x"1F",x"41",x"00", -- 0x01A0
-    x"08",x"3C",x"FE",x"E7",x"8F",x"FE",x"FC",x"00", -- 0x01A8
-    x"00",x"41",x"1F",x"0F",x"03",x"00",x"00",x"00", -- 0x01B0
-    x"00",x"FC",x"FE",x"8F",x"E7",x"FE",x"3C",x"08", -- 0x01B8
-    x"06",x"08",x"03",x"24",x"40",x"10",x"20",x"40", -- 0x01C0
-    x"60",x"10",x"00",x"30",x"0A",x"21",x"10",x"00", -- 0x01C8
-    x"88",x"A8",x"24",x"08",x"40",x"26",x"10",x"03", -- 0x01D0
-    x"15",x"15",x"24",x"80",x"12",x"60",x"04",x"90", -- 0x01D8
-    x"00",x"00",x"00",x"00",x"04",x"00",x"08",x"09", -- 0x01E0
-    x"00",x"00",x"00",x"00",x"80",x"20",x"80",x"50", -- 0x01E8
-    x"00",x"02",x"08",x"04",x"00",x"00",x"00",x"00", -- 0x01F0
-    x"90",x"00",x"20",x"40",x"00",x"00",x"00",x"00", -- 0x01F8
-    x"00",x"00",x"08",x"08",x"E5",x"15",x"15",x"3A", -- 0x0200
-    x"00",x"00",x"80",x"90",x"20",x"4E",x"5F",x"BB", -- 0x0208
-    x"3A",x"15",x"15",x"E5",x"08",x"08",x"00",x"00", -- 0x0210
-    x"A3",x"5B",x"4E",x"20",x"90",x"80",x"00",x"00", -- 0x0218
-    x"00",x"00",x"01",x"22",x"14",x"15",x"15",x"3A", -- 0x0220
-    x"00",x"00",x"20",x"48",x"90",x"2E",x"5F",x"BB", -- 0x0228
-    x"3A",x"15",x"15",x"14",x"22",x"01",x"00",x"00", -- 0x0230
-    x"A3",x"5B",x"2E",x"90",x"48",x"20",x"00",x"00", -- 0x0238
-    x"10",x"48",x"2C",x"1C",x"06",x"02",x"00",x"00", -- 0x0240
-    x"00",x"02",x"04",x"05",x"8E",x"2C",x"98",x"20", -- 0x0248
-    x"00",x"40",x"00",x"00",x"00",x"01",x"00",x"00", -- 0x0250
-    x"00",x"40",x"33",x"8C",x"60",x"1E",x"C0",x"38", -- 0x0258
-    x"11",x"0A",x"0E",x"04",x"06",x"02",x"00",x"00", -- 0x0260
-    x"10",x"14",x"14",x"1C",x"8C",x"28",x"98",x"20", -- 0x0268
-    x"00",x"40",x"00",x"00",x"00",x"01",x"00",x"00", -- 0x0270
-    x"01",x"42",x"3C",x"81",x"7E",x"00",x"84",x"78", -- 0x0278
-    x"00",x"00",x"01",x"01",x"00",x"06",x"06",x"00", -- 0x0280
-    x"50",x"90",x"24",x"44",x"18",x"00",x"80",x"40", -- 0x0288
-    x"00",x"06",x"06",x"00",x"01",x"01",x"00",x"00", -- 0x0290
-    x"40",x"80",x"00",x"18",x"44",x"24",x"90",x"50", -- 0x0298
-    x"00",x"06",x"01",x"01",x"00",x"06",x"06",x"00", -- 0x02A0
-    x"00",x"00",x"3C",x"40",x"1F",x"00",x"80",x"C0", -- 0x02A8
-    x"00",x"06",x"06",x"00",x"01",x"01",x"06",x"00", -- 0x02B0
-    x"C0",x"80",x"00",x"1F",x"40",x"38",x"00",x"00", -- 0x02B8
-    x"00",x"FF",x"00",x"9F",x"CF",x"9F",x"00",x"FF", -- 0x02C0
-    x"FF",x"FF",x"FF",x"C1",x"BE",x"BE",x"80",x"FF", -- 0x02C8
-    x"88",x"77",x"00",x"FF",x"80",x"77",x"80",x"FF", -- 0x02D0
-    x"BF",x"80",x"BF",x"FF",x"FE",x"FE",x"80",x"FF", -- 0x02D8
-    x"FF",x"80",x"77",x"80",x"FF",x"7E",x"00",x"7E", -- 0x02E0
-    x"FE",x"80",x"DE",x"FF",x"C9",x"B6",x"B6",x"C9", -- 0x02E8
-    x"FF",x"00",x"CF",x"9F",x"00",x"FF",x"7E",x"76", -- 0x02F0
-    x"FF",x"C1",x"B6",x"B6",x"CF",x"FE",x"80",x"DE", -- 0x02F8
-    x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0300
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308
-    x"7E",x"FF",x"EF",x"E7",x"7D",x"3C",x"1C",x"08", -- 0x0310
-    x"00",x"00",x"00",x"00",x"00",x"80",x"80",x"80", -- 0x0318
-    x"7C",x"FE",x"FE",x"C8",x"C0",x"FE",x"7E",x"3C", -- 0x0320
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328
-    x"7E",x"FF",x"9F",x"DD",x"65",x"35",x"1C",x"08", -- 0x0330
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338
-    x"7C",x"FE",x"FE",x"E2",x"C0",x"EE",x"7E",x"3C", -- 0x0340
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348
-    x"7E",x"FF",x"EF",x"ED",x"79",x"38",x"38",x"10", -- 0x0350
-    x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x0358
-    x"7C",x"FE",x"FC",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x0360
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368
-    x"7E",x"FF",x"9F",x"DF",x"65",x"35",x"1C",x"08", -- 0x0370
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378
-    x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0380
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388
-    x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0390
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398
-    x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x03A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8
-    x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x03B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8
-    x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x03C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8
-    x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x03D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8
-    x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x03E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8
-    x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x03F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8
-    x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0400
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408
-    x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0410
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418
-    x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x0420
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428
-    x"7C",x"FE",x"FE",x"C8",x"C2",x"FE",x"7E",x"3C", -- 0x0430
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438
-    x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x0440
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448
-    x"7C",x"FE",x"FE",x"E0",x"C2",x"EE",x"7E",x"3C", -- 0x0450
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458
-    x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x0460
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468
-    x"7C",x"FE",x"FE",x"F0",x"E6",x"CE",x"7E",x"3C", -- 0x0470
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478
-    x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0480
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488
-    x"7E",x"FF",x"EF",x"E5",x"7D",x"3D",x"1C",x"08", -- 0x0490
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498
-    x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x04A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8
-    x"7E",x"FF",x"9F",x"DD",x"65",x"34",x"1C",x"08", -- 0x04B0
-    x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x04B8
-    x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x04C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8
-    x"7E",x"FF",x"EF",x"E5",x"7C",x"3C",x"1C",x"08", -- 0x04D0
-    x"00",x"00",x"00",x"00",x"80",x"40",x"40",x"00", -- 0x04D8
-    x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x04E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8
-    x"7E",x"FF",x"9F",x"DF",x"65",x"35",x"1D",x"08", -- 0x04F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8
-    x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0500
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518
-    x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0520
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538
-    x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0540
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558
-    x"7E",x"FF",x"EF",x"E7",x"7D",x"3D",x"1C",x"08", -- 0x0560
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588
-    x"00",x"80",x"40",x"60",x"30",x"38",x"3C",x"3C", -- 0x0590
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8
-    x"20",x"30",x"18",x"1C",x"3C",x"3C",x"7C",x"7C", -- 0x05B0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8
-    x"00",x"0C",x"1C",x"3C",x"38",x"38",x"78",x"7C", -- 0x05D0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8
-    x"00",x"03",x"07",x"0E",x"1E",x"3C",x"3C",x"78", -- 0x05F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8
-    x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x0600
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608
-    x"7F",x"3F",x"3F",x"1E",x"1C",x"0F",x"0F",x"07", -- 0x0610
-    x"C0",x"00",x"E0",x"F0",x"E0",x"C0",x"80",x"00", -- 0x0618
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628
-    x"3C",x"78",x"71",x"73",x"3F",x"1F",x"0E",x"00", -- 0x0630
-    x"7C",x"F0",x"FE",x"EF",x"CE",x"FC",x"F8",x"70", -- 0x0638
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648
-    x"1C",x"18",x"18",x"1B",x"1F",x"0F",x"03",x"00", -- 0x0650
-    x"18",x"7D",x"FD",x"CD",x"DE",x"DC",x"F8",x"70", -- 0x0658
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660
-    x"08",x"1C",x"3D",x"7D",x"E7",x"EF",x"FF",x"7E", -- 0x0668
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670
-    x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x0678
-    x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"3C", -- 0x0680
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688
-    x"3C",x"3E",x"1E",x"1F",x"0F",x"0F",x"07",x"01", -- 0x0690
-    x"E0",x"70",x"78",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0698
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8
-    x"3C",x"78",x"71",x"73",x"3F",x"1F",x"0E",x"00", -- 0x06B0
-    x"18",x"CC",x"CE",x"DE",x"FE",x"FC",x"F8",x"70", -- 0x06B8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"1C",x"3E", -- 0x06C8
-    x"00",x"00",x"03",x"07",x"07",x"07",x"07",x"03", -- 0x06D0
-    x"7F",x"FF",x"FF",x"FF",x"FE",x"FC",x"38",x"80", -- 0x06D8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0
-    x"00",x"1C",x"3F",x"7F",x"EF",x"E7",x"F3",x"78", -- 0x06E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0
-    x"7C",x"FE",x"CE",x"C0",x"E0",x"FE",x"7E",x"7C", -- 0x06F8
-    x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0700
-    x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0708
-    x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0710
-    x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0718
-    x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0720
-    x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0728
-    x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0730
-    x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0738
-    x"46",x"2F",x"1F",x"CF",x"3F",x"0F",x"3F",x"C6", -- 0x0740
-    x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0748
-    x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0750
-    x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0758
-    x"40",x"26",x"19",x"C6",x"39",x"06",x"39",x"C6", -- 0x0760
-    x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0768
-    x"00",x"09",x"19",x"00",x"00",x"00",x"00",x"00", -- 0x0770
-    x"00",x"00",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0778
-    x"09",x"17",x"3C",x"1B",x"3F",x"EF",x"DF",x"BF", -- 0x0780
-    x"80",x"E0",x"F8",x"CC",x"F4",x"DE",x"EF",x"FF", -- 0x0788
-    x"77",x"57",x"DB",x"77",x"3F",x"19",x"0F",x"04", -- 0x0790
-    x"EA",x"EA",x"DB",x"7E",x"EC",x"9C",x"F8",x"40", -- 0x0798
-    x"03",x"07",x"1F",x"1F",x"3B",x"3F",x"37",x"36", -- 0x07A0
-    x"C0",x"E0",x"F0",x"F8",x"7C",x"DC",x"7C",x"AC", -- 0x07A8
-    x"3F",x"3D",x"37",x"1B",x"1F",x"1F",x"0F",x"07", -- 0x07B0
-    x"6C",x"FC",x"DC",x"BC",x"F8",x"F8",x"F0",x"E0", -- 0x07B8
-    x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07C0
-    x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07C8
-    x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07D0
-    x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x07D8
-    x"1E",x"3F",x"7E",x"00",x"00",x"7E",x"3F",x"1E", -- 0x07E0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8
-    x"38",x"7C",x"C2",x"82",x"86",x"7C",x"38",x"00", -- 0x0800
-    x"02",x"02",x"FE",x"FE",x"42",x"02",x"00",x"00", -- 0x0808
-    x"62",x"F2",x"BA",x"9A",x"9E",x"CE",x"46",x"00", -- 0x0810
-    x"8C",x"DE",x"F2",x"B2",x"92",x"86",x"04",x"00", -- 0x0818
-    x"08",x"FE",x"FE",x"C8",x"68",x"38",x"18",x"00", -- 0x0820
-    x"1C",x"BE",x"A2",x"A2",x"A2",x"E6",x"E4",x"00", -- 0x0828
-    x"0C",x"9E",x"92",x"92",x"D2",x"7E",x"3C",x"00", -- 0x0830
-    x"C0",x"E0",x"B0",x"9E",x"8E",x"C0",x"C0",x"00", -- 0x0838
-    x"0C",x"6E",x"9A",x"9A",x"B2",x"F2",x"6C",x"00", -- 0x0840
-    x"78",x"FC",x"96",x"92",x"92",x"F2",x"60",x"00", -- 0x0848
-    x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0850
-    x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0858
-    x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0860
-    x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x0868
-    x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x0870
-    x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x0878
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880
-    x"3E",x"7E",x"C8",x"88",x"C8",x"7E",x"3E",x"00", -- 0x0888
-    x"6C",x"FE",x"92",x"92",x"92",x"FE",x"FE",x"00", -- 0x0890
-    x"44",x"C6",x"82",x"82",x"C6",x"7C",x"38",x"00", -- 0x0898
-    x"38",x"7C",x"C6",x"82",x"82",x"FE",x"FE",x"00", -- 0x08A0
-    x"82",x"92",x"92",x"92",x"FE",x"FE",x"00",x"00", -- 0x08A8
-    x"80",x"90",x"90",x"90",x"90",x"FE",x"FE",x"00", -- 0x08B0
-    x"9E",x"9E",x"92",x"82",x"C6",x"7C",x"38",x"00", -- 0x08B8
-    x"FE",x"FE",x"10",x"10",x"10",x"FE",x"FE",x"00", -- 0x08C0
-    x"82",x"82",x"FE",x"FE",x"82",x"82",x"00",x"00", -- 0x08C8
-    x"FC",x"FE",x"02",x"02",x"02",x"06",x"04",x"00", -- 0x08D0
-    x"82",x"C6",x"6E",x"3C",x"18",x"FE",x"FE",x"00", -- 0x08D8
-    x"02",x"02",x"02",x"02",x"FE",x"FE",x"00",x"00", -- 0x08E0
-    x"FE",x"FE",x"70",x"38",x"70",x"FE",x"FE",x"00", -- 0x08E8
-    x"FE",x"FE",x"1C",x"38",x"70",x"FE",x"FE",x"00", -- 0x08F0
-    x"7C",x"FE",x"82",x"82",x"82",x"FE",x"7C",x"00", -- 0x08F8
-    x"70",x"F8",x"88",x"88",x"88",x"FE",x"FE",x"00", -- 0x0900
-    x"7A",x"FC",x"8E",x"8A",x"82",x"FE",x"7C",x"00", -- 0x0908
-    x"72",x"F6",x"9E",x"8C",x"88",x"FE",x"FE",x"00", -- 0x0910
-    x"0C",x"5E",x"D2",x"92",x"92",x"F6",x"64",x"00", -- 0x0918
-    x"80",x"80",x"FE",x"FE",x"80",x"80",x"00",x"00", -- 0x0920
-    x"FC",x"FE",x"02",x"02",x"02",x"FE",x"FC",x"00", -- 0x0928
-    x"F0",x"F8",x"1C",x"0E",x"1C",x"F8",x"F0",x"00", -- 0x0930
-    x"F8",x"FE",x"1C",x"38",x"1C",x"FE",x"F8",x"00", -- 0x0938
-    x"C6",x"EE",x"7C",x"38",x"7C",x"EE",x"C6",x"00", -- 0x0940
-    x"C0",x"F0",x"1E",x"1E",x"F0",x"C0",x"00",x"00", -- 0x0948
-    x"C2",x"E2",x"F2",x"BA",x"9E",x"8E",x"86",x"00", -- 0x0950
-    x"3C",x"42",x"81",x"A5",x"A5",x"99",x"42",x"3C", -- 0x0958
-    x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0960
-    x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0968
-    x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0970
-    x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0978
-    x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0980
-    x"38",x"68",x"F8",x"D7",x"7F",x"D8",x"78",x"28", -- 0x0988
-    x"38",x"78",x"F8",x"F8",x"F8",x"F8",x"78",x"38", -- 0x0990
-    x"00",x"10",x"00",x"2F",x"87",x"20",x"00",x"10", -- 0x0998
-    x"00",x"00",x"00",x"00",x"01",x"00",x"5E",x"FF", -- 0x09A0
-    x"00",x"00",x"18",x"7C",x"F4",x"78",x"00",x"F8", -- 0x09A8
-    x"FF",x"5E",x"00",x"01",x"00",x"00",x"00",x"00", -- 0x09B0
-    x"F8",x"00",x"78",x"F4",x"7C",x"18",x"00",x"00", -- 0x09B8
-    x"00",x"00",x"03",x"04",x"01",x"12",x"22",x"00", -- 0x09C0
-    x"00",x"00",x"00",x"30",x"08",x"00",x"00",x"C0", -- 0x09C8
-    x"02",x"21",x"20",x"10",x"00",x"06",x"00",x"00", -- 0x09D0
-    x"44",x"04",x"04",x"00",x"10",x"60",x"00",x"00", -- 0x09D8
-    x"02",x"00",x"00",x"10",x"10",x"20",x"00",x"01", -- 0x09E0
-    x"C0",x"00",x"10",x"08",x"00",x"00",x"84",x"40", -- 0x09E8
-    x"20",x"22",x"00",x"00",x"10",x"00",x"00",x"06", -- 0x09F0
-    x"80",x"04",x"04",x"00",x"00",x"10",x"00",x"40", -- 0x09F8
-    x"00",x"00",x"08",x"08",x"E5",x"15",x"42",x"2F", -- 0x0A00
-    x"00",x"00",x"80",x"90",x"20",x"40",x"84",x"DE", -- 0x0A08
-    x"05",x"42",x"15",x"E5",x"08",x"08",x"00",x"00", -- 0x0A10
-    x"5E",x"84",x"40",x"20",x"90",x"80",x"00",x"00", -- 0x0A18
-    x"00",x"00",x"01",x"22",x"14",x"15",x"42",x"2F", -- 0x0A20
-    x"00",x"00",x"20",x"48",x"90",x"20",x"84",x"DE", -- 0x0A28
-    x"05",x"42",x"15",x"14",x"22",x"01",x"00",x"00", -- 0x0A30
-    x"5E",x"84",x"20",x"90",x"48",x"20",x"00",x"00", -- 0x0A38
-    x"10",x"48",x"2C",x"1C",x"06",x"03",x"01",x"03", -- 0x0A40
-    x"00",x"02",x"04",x"05",x"4E",x"CC",x"78",x"E0", -- 0x0A48
-    x"03",x"03",x"83",x"C7",x"7F",x"3F",x"1E",x"00", -- 0x0A50
-    x"E0",x"E0",x"F3",x"CC",x"E0",x"9E",x"C0",x"38", -- 0x0A58
-    x"11",x"0A",x"0E",x"04",x"06",x"03",x"01",x"03", -- 0x0A60
-    x"10",x"14",x"14",x"1C",x"4C",x"C8",x"78",x"E0", -- 0x0A68
-    x"03",x"03",x"83",x"C7",x"7F",x"3F",x"1E",x"00", -- 0x0A70
-    x"E1",x"E2",x"FC",x"C1",x"FE",x"80",x"84",x"78", -- 0x0A78
-    x"00",x"00",x"01",x"01",x"03",x"01",x"0B",x"0F", -- 0x0A80
-    x"50",x"90",x"24",x"C4",x"D8",x"E0",x"60",x"B0", -- 0x0A88
-    x"0F",x"0B",x"01",x"03",x"01",x"01",x"00",x"00", -- 0x0A90
-    x"B0",x"60",x"E0",x"D8",x"C4",x"24",x"90",x"50", -- 0x0A98
-    x"00",x"06",x"01",x"01",x"03",x"07",x"0D",x"0F", -- 0x0AA0
-    x"00",x"00",x"3C",x"C0",x"DF",x"E0",x"60",x"30", -- 0x0AA8
-    x"0F",x"0D",x"07",x"03",x"01",x"01",x"06",x"00", -- 0x0AB0
-    x"30",x"60",x"E0",x"DF",x"C0",x"38",x"00",x"00", -- 0x0AB8
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AC0
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AC8
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AD0
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AD8
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AE0
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AE8
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AF0
-    x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0AF8
-    x"70",x"F8",x"FC",x"BE",x"9F",x"CC",x"78",x"30", -- 0x0B00
-    x"00",x"00",x"00",x"00",x"00",x"80",x"40",x"00", -- 0x0B08
-    x"78",x"FC",x"9E",x"DE",x"66",x"35",x"1D",x"09", -- 0x0B10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18
-    x"70",x"F8",x"FC",x"BF",x"BF",x"CC",x"78",x"30", -- 0x0B20
-    x"00",x"00",x"00",x"00",x"C0",x"00",x"00",x"00", -- 0x0B28
-    x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1D",x"08", -- 0x0B30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"80", -- 0x0B38
-    x"70",x"F8",x"CC",x"9C",x"BF",x"DC",x"78",x"30", -- 0x0B40
-    x"00",x"00",x"40",x"80",x"00",x"00",x"00",x"00", -- 0x0B48
-    x"78",x"FC",x"9E",x"DE",x"6A",x"39",x"39",x"12", -- 0x0B50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58
-    x"70",x"F9",x"CE",x"8E",x"9C",x"FC",x"78",x"30", -- 0x0B60
-    x"C0",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68
-    x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1D",x"09", -- 0x0B70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78
-    x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"30", -- 0x0B80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"00", -- 0x0B88
-    x"70",x"F8",x"FC",x"BE",x"9E",x"CD",x"78",x"30", -- 0x0B90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"00", -- 0x0B98
-    x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x0BA0
-    x"00",x"00",x"00",x"00",x"80",x"40",x"00",x"00", -- 0x0BA8
-    x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x0BB0
-    x"00",x"00",x"00",x"00",x"80",x"40",x"00",x"00", -- 0x0BB8
-    x"70",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x0BC0
-    x"00",x"00",x"00",x"80",x"00",x"00",x"00",x"00", -- 0x0BC8
-    x"70",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x0BD0
-    x"00",x"00",x"00",x"80",x"00",x"00",x"00",x"00", -- 0x0BD8
-    x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x0BE0
-    x"00",x"40",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8
-    x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x0BF0
-    x"00",x"40",x"80",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8
-    x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0C00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08
-    x"78",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"30", -- 0x0C10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18
-    x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x0C20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28
-    x"70",x"F8",x"FC",x"BF",x"BC",x"CC",x"78",x"30", -- 0x0C30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38
-    x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x0C40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48
-    x"78",x"F8",x"CC",x"9F",x"BC",x"DC",x"78",x"30", -- 0x0C50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58
-    x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x0C60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68
-    x"70",x"F8",x"CD",x"8F",x"9C",x"FC",x"78",x"30", -- 0x0C70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78
-    x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0C80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88
-    x"78",x"FC",x"9E",x"DE",x"66",x"36",x"1E",x"0A", -- 0x0C90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98
-    x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x0CA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8
-    x"78",x"FC",x"EE",x"E6",x"7E",x"3D",x"1C",x"08", -- 0x0CB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x0CB8
-    x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x0CC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8
-    x"78",x"FC",x"9E",x"DE",x"66",x"35",x"1C",x"09", -- 0x0CD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"80", -- 0x0CD8
-    x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x0CE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8
-    x"78",x"FC",x"EE",x"E6",x"7E",x"3E",x"1E",x"09", -- 0x0CF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8
-    x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18
-    x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38
-    x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58
-    x"78",x"FC",x"9E",x"DE",x"64",x"34",x"1C",x"08", -- 0x0D60
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88
-    x"00",x"80",x"40",x"60",x"20",x"20",x"30",x"38", -- 0x0D90
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8
-    x"20",x"30",x"10",x"10",x"38",x"38",x"78",x"78", -- 0x0DB0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8
-    x"00",x"08",x"18",x"30",x"30",x"20",x"70",x"70", -- 0x0DD0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8
-    x"00",x"02",x"04",x"0C",x"18",x"38",x"30",x"70", -- 0x0DF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8
-    x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"70", -- 0x0E00
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08
-    x"78",x"37",x"3F",x"1F",x"1F",x"0C",x"0D",x"07", -- 0x0E10
-    x"00",x"00",x"E0",x"30",x"60",x"C0",x"80",x"00", -- 0x0E18
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28
-    x"39",x"7E",x"7E",x"6F",x"33",x"1F",x"0E",x"00", -- 0x0E30
-    x"00",x"30",x"7E",x"F3",x"F6",x"CC",x"D8",x"70", -- 0x0E38
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48
-    x"19",x"1F",x"1E",x"1D",x"1F",x"0F",x"07",x"06", -- 0x0E50
-    x"18",x"7C",x"FC",x"FC",x"B8",x"B0",x"D0",x"60", -- 0x0E58
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60
-    x"08",x"1C",x"34",x"64",x"DE",x"9E",x"FC",x"78", -- 0x0E68
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70
-    x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"00", -- 0x0E78
-    x"70",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"32", -- 0x0E80
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88
-    x"3F",x"3D",x"1D",x"1F",x"0F",x"0F",x"07",x"01", -- 0x0E90
-    x"00",x"C0",x"E0",x"30",x"F8",x"F0",x"E0",x"C0", -- 0x0E98
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8
-    x"39",x"7E",x"7E",x"6F",x"33",x"1F",x"0E",x"00", -- 0x0EB0
-    x"60",x"30",x"7E",x"EE",x"CE",x"FC",x"F8",x"70", -- 0x0EB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"01", -- 0x0EC0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"9C",x"3E", -- 0x0EC8
-    x"01",x"03",x"03",x"07",x"07",x"07",x"07",x"03", -- 0x0ED0
-    x"FE",x"FE",x"FE",x"FC",x"F8",x"F0",x"E0",x"FC", -- 0x0ED8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0
-    x"00",x"1C",x"3C",x"7E",x"FE",x"DE",x"CC",x"7F", -- 0x0EE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0
-    x"71",x"F8",x"FC",x"BE",x"9F",x"CD",x"78",x"00", -- 0x0EF8
-    x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0F00
-    x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F08
-    x"1F",x"36",x"6F",x"FF",x"CF",x"C6",x"40",x"40", -- 0x0F10
-    x"80",x"C0",x"60",x"F0",x"30",x"30",x"20",x"20", -- 0x0F18
-    x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0F20
-    x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F28
-    x"1F",x"36",x"6F",x"FF",x"CF",x"66",x"20",x"20", -- 0x0F30
-    x"80",x"C0",x"60",x"F0",x"30",x"60",x"40",x"40", -- 0x0F38
-    x"44",x"2C",x"1C",x"CC",x"3C",x"0C",x"3C",x"C4", -- 0x0F40
-    x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F48
-    x"1F",x"36",x"6F",x"FF",x"CF",x"66",x"30",x"10", -- 0x0F50
-    x"80",x"C0",x"60",x"F0",x"30",x"60",x"C0",x"80", -- 0x0F58
-    x"46",x"2D",x"16",x"CD",x"36",x"0D",x"36",x"C4", -- 0x0F60
-    x"20",x"40",x"80",x"30",x"C0",x"00",x"C0",x"30", -- 0x0F68
-    x"1F",x"36",x"6F",x"FF",x"FF",x"76",x"19",x"06", -- 0x0F70
-    x"80",x"C0",x"60",x"F0",x"F0",x"E0",x"80",x"00", -- 0x0F78
-    x"0F",x"1F",x"3C",x"3B",x"7E",x"ED",x"DD",x"FF", -- 0x0F80
-    x"E0",x"F0",x"F8",x"CC",x"F6",x"FF",x"FF",x"3F", -- 0x0F88
-    x"FD",x"DE",x"DF",x"6F",x"7F",x"39",x"1F",x"07", -- 0x0F90
-    x"BB",x"FB",x"FB",x"FE",x"EE",x"9C",x"F8",x"C0", -- 0x0F98
-    x"01",x"07",x"1F",x"0F",x"2F",x"1F",x"3F",x"3E", -- 0x0FA0
-    x"00",x"E0",x"E0",x"F0",x"FC",x"FC",x"78",x"BC", -- 0x0FA8
-    x"1F",x"1D",x"3F",x"1F",x"0F",x"1F",x"0F",x"01", -- 0x0FB0
-    x"7C",x"F8",x"F8",x"FC",x"F8",x"E8",x"F0",x"A0", -- 0x0FB8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0
-    x"24",x"14",x"0C",x"3F",x"3F",x"0C",x"14",x"24", -- 0x0FC8
-    x"20",x"90",x"40",x"F0",x"F0",x"40",x"90",x"20", -- 0x0FD0
-    x"24",x"94",x"4C",x"FF",x"FF",x"4C",x"94",x"24", -- 0x0FD8
-    x"00",x"0C",x"14",x"FE",x"FE",x"14",x"0C",x"00", -- 0x0FE0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0
-    x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00"  -- 0x0FF8
-  );
-
-begin
-
-  p_rom : process
-  begin
-    wait until rising_edge(CLK);
-    if (ENA = '1') then
-       DATA <= ROM(to_integer(unsigned(ADDR)));
-    end if;
-  end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/WarOfTheBugs.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/WarOfTheBugs.sv
deleted file mode 100644
index a9c1d6ef..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/WarOfTheBugs.sv	
+++ /dev/null
@@ -1,192 +0,0 @@
-//============================================================================
-//  Arcade: WarOfTheBugs
-//
-//  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
-//
-//  This program is free software; you can redistribute it and/or modify it
-//  under the terms of the GNU General Public License as published by the Free
-//  Software Foundation; either version 2 of the License, or (at your option)
-//  any later version.
-//
-//  This program is distributed in the hope that it will be useful, but WITHOUT
-//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-//  more details.
-//
-//  You should have received a copy of the GNU General Public License along
-//  with this program; if not, write to the Free Software Foundation, Inc.,
-//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-//============================================================================
-
-module WarOfTheBugs(
-	output        LED,
-	output  [5:0] VGA_R,
-	output  [5:0] VGA_G,
-	output  [5:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        AUDIO_L,
-	output        AUDIO_R,
-	input         SPI_SCK,
-	output        SPI_DO,
-	input         SPI_DI,
-	input         SPI_SS2,
-	input         SPI_SS3,
-	input         CONF_DATA0,
-	input         CLOCK_27
-);
-
-`include "rtl\build_id.v" 
-
-localparam CONF_STR = {
-	"WarOfTheBugs;;",
-	"O2,Rotate Controls,Off,On;",
-	"O34,Scanlines,Off,25%,50%,75%;",
-	"T6,Reset;",
-	"V,v1.20.",`BUILD_DATE
-};
-
-assign LED = 1;
-assign AUDIO_R = AUDIO_L;
-
-wire clk_24, clk_18, clk_12, clk_6;
-wire pll_locked;
-pll pll(
-	.inclk0(CLOCK_27),
-	.areset(0),
-	.c0(clk_24),
-	.c1(clk_18),
-	.c2(clk_12),
-	.c3(clk_6)
-	);
-	
-wire [31:0] status;
-wire  [1:0] buttons;
-wire  [1:0] switches;
-wire  [7:0] joystick_0;#
-wire  [7:0] joystick_1;
-wire        scandoublerD;
-wire        ypbpr;
-wire [10:0] ps2_key;
-wire  [7:0] audio_a, audio_b;
-wire [10:0] audio = {1'b0, audio_b, 2'b0} + {3'b0, audio_a};
-wire 			hs, vs;
-wire 			hb, vb;
-wire        blankn = ~(hb | vb);
-wire  [2:0] r,g,b;
-
-galaxian warofbugs(
-	.W_CLK_18M(clk_18),
-	.W_CLK_12M(clk_12),
-	.W_CLK_6M(clk_6),
-	.I_RESET(status[0] | status[6] | buttons[1]),
-	.P1_CSJUDLR({btn_coin,btn_one_player,m_fire,m_up,m_down,m_left,m_right}),
-	.P2_CSJUDLR({1'b0,btn_two_players,m_fire,m_up,m_down,m_left,m_right}),
-	.W_R(r),
-	.W_G(g),
-	.W_B(b),
-	.W_H_SYNC(hs),
-	.W_V_SYNC(vs),
-	.HBLANK(hb),
-	.VBLANK(vb),
-	.W_SDAT_A(audio_a),
-	.W_SDAT_B(audio_b)
-	);
-
-video_mixer video_mixer(
-	.clk_sys(clk_24),
-	.ce_pix(clk_6),
-	.ce_pix_actual(clk_6),
-	.SPI_SCK(SPI_SCK),
-	.SPI_SS3(SPI_SS3),
-	.SPI_DI(SPI_DI),
-	.R(blankn ? r : "000"),
-	.G(blankn ? g : "000"),
-	.B(blankn ? b : "000"),
-	.HSync(hs),
-	.VSync(vs),
-	.VGA_R(VGA_R),
-	.VGA_G(VGA_G),
-	.VGA_B(VGA_B),
-	.VGA_VS(VGA_VS),
-	.VGA_HS(VGA_HS),
-	.rotate({1'b1,status[2]}),
-	.scandoublerD(scandoublerD),
-	.scanlines(scandoublerD ? 2'b00 : status[4:3]),
-	.ypbpr(ypbpr),
-	.ypbpr_full(1),
-	.line_start(0),
-	.mono(0)
-	);
-
-mist_io #(
-	.STRLEN(($size(CONF_STR)>>3)))
-mist_io(
-	.clk_sys        (clk_24         ),
-	.conf_str       (CONF_STR       ),
-	.SPI_SCK        (SPI_SCK        ),
-	.CONF_DATA0     (CONF_DATA0     ),
-	.SPI_SS2			 (SPI_SS2        ),
-	.SPI_DO         (SPI_DO         ),
-	.SPI_DI         (SPI_DI         ),
-	.buttons        (buttons        ),
-	.switches   	 (switches       ),
-	.scandoublerD	 (scandoublerD	  ),
-	.ypbpr          (ypbpr          ),
-	.ps2_key			 (ps2_key        ),
-	.joystick_0   	 (joystick_0     ),
-	.joystick_1     (joystick_1     ),
-	.status         (status         )
-	);
-	
-dac #(
-	.msbi_g(15))
-dac(
-	.clk_i(clk_24),
-	.res_n_i(1),
-	.dac_i({audio,5'd0}),
-	.dac_o(AUDIO_L)
-	);
-	
-//											Rotated														Normal
-wire m_up     = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
-wire m_down   = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
-wire m_left   = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
-wire m_right  = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
-wire m_fire   = btn_fire1 | joystick_0[4] | joystick_1[4];
-wire m_bomb   = btn_fire2 | joystick_0[5] | joystick_1[5];
-
-reg btn_one_player = 0;
-reg btn_two_players = 0;
-reg btn_left = 0;
-reg btn_right = 0;
-reg btn_down = 0;
-reg btn_up = 0;
-reg btn_fire1 = 0;
-reg btn_fire2 = 0;
-reg btn_fire3 = 0;
-reg btn_coin  = 0;
-wire       pressed = ps2_key[9];
-wire [7:0] code    = ps2_key[7:0];	
-
-always @(posedge clk_24) begin
-	reg old_state;
-	old_state <= ps2_key[10];
-	if(old_state != ps2_key[10]) begin
-		case(code)
-			'h75: btn_up         	<= pressed; // up
-			'h72: btn_down        	<= pressed; // down
-			'h6B: btn_left      		<= pressed; // left
-			'h74: btn_right       	<= pressed; // right
-			'h76: btn_coin				<= pressed; // ESC
-			'h05: btn_one_player   	<= pressed; // F1
-			'h06: btn_two_players  	<= pressed; // F2
-			'h14: btn_fire3 			<= pressed; // ctrl
-			'h11: btn_fire2 			<= pressed; // alt
-			'h29: btn_fire1   		<= pressed; // Space
-		endcase
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/build_id.tcl b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/build_id.tcl
deleted file mode 100644
index 938515d8..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/build_id.tcl	
+++ /dev/null
@@ -1,35 +0,0 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
-
-proc generateBuildID_Verilog {} {
-
-	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
-	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
-	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
-
-	# Create a Verilog file for output
-	set outputFileName "rtl/build_id.v"
-	set outputFile [open $outputFileName "w"]
-
-	# Output the Verilog source
-	puts $outputFile "`define BUILD_DATE \"$buildDate\""
-	puts $outputFile "`define BUILD_TIME \"$buildTime\""
-	close $outputFile
-
-	# Send confirmation message to the Messages window
-	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
-	post_message "Date:             $buildDate"
-	post_message "Time:             $buildTime"
-}
-
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80.vhd
deleted file mode 100644
index c07d2629..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80.vhd	
+++ /dev/null
@@ -1,1093 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0210 : Fixed wait and halt
---
---      0211 : Fixed Refresh addition and IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
---      0235 : Added clock enable and IM 2 fix by Mike Johnson
---
---      0237 : Changed 8080 I/O address output, added IntE output
---
---      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
---      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
---      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
---      0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
-	generic(
-		Mode			: integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-end T80;
-
-architecture rtl of T80 is
-
-	constant aNone				: std_logic_vector(2 downto 0)  := "111";
-	constant aBC				: std_logic_vector(2 downto 0)  := "000";
-	constant aDE				: std_logic_vector(2 downto 0)  := "001";
-	constant aXY				: std_logic_vector(2 downto 0)  := "010";
-	constant aIOA				: std_logic_vector(2 downto 0)  := "100";
-	constant aSP				: std_logic_vector(2 downto 0)  := "101";
-	constant aZI                : std_logic_vector(2 downto 0) := "110";
-
-	-- Registers
-	signal ACC, F               : std_logic_vector(7 downto 0);
-	signal Ap, Fp               : std_logic_vector(7 downto 0);
-	signal I                    : std_logic_vector(7 downto 0);
-	signal R                    : unsigned(7 downto 0);
-	signal SP, PC               : unsigned(15 downto 0);
-
-	signal RegDIH               : std_logic_vector(7 downto 0);
-	signal RegDIL               : std_logic_vector(7 downto 0);
-	signal RegBusA              : std_logic_vector(15 downto 0);
-	signal RegBusB              : std_logic_vector(15 downto 0);
-	signal RegBusC              : std_logic_vector(15 downto 0);
-	signal RegAddrA_r           : std_logic_vector(2 downto 0);
-	signal RegAddrA             : std_logic_vector(2 downto 0);
-	signal RegAddrB_r           : std_logic_vector(2 downto 0);
-	signal RegAddrB             : std_logic_vector(2 downto 0);
-	signal RegAddrC             : std_logic_vector(2 downto 0);
-	signal RegWEH               : std_logic;
-	signal RegWEL               : std_logic;
-	signal Alternate            : std_logic;
-
-	-- Help Registers
-	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
-	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
-	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
-	signal RegBusA_r            : std_logic_vector(15 downto 0);
-
-	signal ID16                 : signed(15 downto 0);
-	signal Save_Mux             : std_logic_vector(7 downto 0);
-
-	signal TState               : unsigned(2 downto 0);
-	signal MCycle               : std_logic_vector(2 downto 0);
-	signal IntE_FF1             : std_logic;
-	signal IntE_FF2             : std_logic;
-	signal Halt_FF              : std_logic;
-	signal BusReq_s             : std_logic;
-	signal BusAck               : std_logic;
-	signal ClkEn                : std_logic;
-	signal NMI_s                : std_logic;
-	signal INT_s                : std_logic;
-	signal IStatus              : std_logic_vector(1 downto 0);
-
-	signal DI_Reg               : std_logic_vector(7 downto 0);
-	signal T_Res                : std_logic;
-	signal XY_State             : std_logic_vector(1 downto 0);
-	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
-	signal NextIs_XY_Fetch      : std_logic;
-	signal XY_Ind               : std_logic;
-	signal No_BTR               : std_logic;
-	signal BTR_r                : std_logic;
-	signal Auto_Wait            : std_logic;
-	signal Auto_Wait_t1         : std_logic;
-	signal Auto_Wait_t2         : std_logic;
-	signal IncDecZ              : std_logic;
-
-	-- ALU signals
-	signal BusB                 : std_logic_vector(7 downto 0);
-	signal BusA                 : std_logic_vector(7 downto 0);
-	signal ALU_Q                : std_logic_vector(7 downto 0);
-	signal F_Out                : std_logic_vector(7 downto 0);
-
-	-- Registered micro code outputs
-	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
-	signal Arith16_r            : std_logic;
-	signal Z16_r                : std_logic;
-	signal ALU_Op_r             : std_logic_vector(3 downto 0);
-	signal Save_ALU_r           : std_logic;
-	signal PreserveC_r          : std_logic;
-	signal MCycles              : std_logic_vector(2 downto 0);
-
-	-- Micro code outputs
-	signal MCycles_d            : std_logic_vector(2 downto 0);
-	signal TStates              : std_logic_vector(2 downto 0);
-	signal IntCycle             : std_logic;
-	signal NMICycle             : std_logic;
-	signal Inc_PC               : std_logic;
-	signal Inc_WZ               : std_logic;
-	signal IncDec_16            : std_logic_vector(3 downto 0);
-	signal Prefix               : std_logic_vector(1 downto 0);
-	signal Read_To_Acc          : std_logic;
-	signal Read_To_Reg          : std_logic;
-	signal Set_BusB_To          : std_logic_vector(3 downto 0);
-	signal Set_BusA_To          : std_logic_vector(3 downto 0);
-	signal ALU_Op               : std_logic_vector(3 downto 0);
-	signal Save_ALU             : std_logic;
-	signal PreserveC            : std_logic;
-	signal Arith16              : std_logic;
-	signal Set_Addr_To          : std_logic_vector(2 downto 0);
-	signal Jump                 : std_logic;
-	signal JumpE                : std_logic;
-	signal JumpXY               : std_logic;
-	signal Call                 : std_logic;
-	signal RstP                 : std_logic;
-	signal LDZ                  : std_logic;
-	signal LDW                  : std_logic;
-	signal LDSPHL               : std_logic;
-	signal IORQ_i               : std_logic;
-	signal Special_LD           : std_logic_vector(2 downto 0);
-	signal ExchangeDH           : std_logic;
-	signal ExchangeRp           : std_logic;
-	signal ExchangeAF           : std_logic;
-	signal ExchangeRS           : std_logic;
-	signal I_DJNZ               : std_logic;
-	signal I_CPL                : std_logic;
-	signal I_CCF                : std_logic;
-	signal I_SCF                : std_logic;
-	signal I_RETN               : std_logic;
-	signal I_BT                 : std_logic;
-	signal I_BC                 : std_logic;
-	signal I_BTR                : std_logic;
-	signal I_RLD                : std_logic;
-	signal I_RRD                : std_logic;
-	signal I_INRC               : std_logic;
-	signal SetDI                : std_logic;
-	signal SetEI                : std_logic;
-	signal IMode                : std_logic_vector(1 downto 0);
-	signal Halt                 : std_logic;
-	signal XYbit_undoc          : std_logic;
-
-begin
-
-	mcode : T80_MCode
-		generic map(
-			Mode   => Mode,
-			Flag_C => Flag_C,
-			Flag_N => Flag_N,
-			Flag_P => Flag_P,
-			Flag_X => Flag_X,
-			Flag_H => Flag_H,
-			Flag_Y => Flag_Y,
-			Flag_Z => Flag_Z,
-			Flag_S => Flag_S)
-		port map(
-			IR				=> IR,
-			ISet			=> ISet,
-			MCycle		=> MCycle,
-			F				=> F,
-			NMICycle		=> NMICycle,
-			IntCycle		=> IntCycle,
-			XY_State    => XY_State,
-			MCycles		=> MCycles_d,
-			TStates		=> TStates,
-			Prefix		=> Prefix,
-			Inc_PC		=> Inc_PC,
-			Inc_WZ		=> Inc_WZ,
-			IncDec_16	=> IncDec_16,
-			Read_To_Acc	=> Read_To_Acc,
-			Read_To_Reg	=> Read_To_Reg,
-			Set_BusB_To	=> Set_BusB_To,
-			Set_BusA_To	=> Set_BusA_To,
-			ALU_Op		=> ALU_Op,
-			Save_ALU		=> Save_ALU,
-			PreserveC	=> PreserveC,
-			Arith16		=> Arith16,
-			Set_Addr_To	=> Set_Addr_To,
-			IORQ			=> IORQ_i,
-			Jump			=> Jump,
-			JumpE			=> JumpE,
-			JumpXY		=> JumpXY,
-			Call			=> Call,
-			RstP			=> RstP,
-			LDZ			=> LDZ,
-			LDW			=> LDW,
-			LDSPHL		=> LDSPHL,
-			Special_LD	=> Special_LD,
-			ExchangeDH	=> ExchangeDH,
-			ExchangeRp	=> ExchangeRp,
-			ExchangeAF	=> ExchangeAF,
-			ExchangeRS	=> ExchangeRS,
-			I_DJNZ		=> I_DJNZ,
-			I_CPL			=> I_CPL,
-			I_CCF			=> I_CCF,
-			I_SCF			=> I_SCF,
-			I_RETN		=> I_RETN,
-			I_BT			=> I_BT,
-			I_BC			=> I_BC,
-			I_BTR			=> I_BTR,
-			I_RLD			=> I_RLD,
-			I_RRD			=> I_RRD,
-			I_INRC		=> I_INRC,
-			SetDI			=> SetDI,
-			SetEI			=> SetEI,
-			IMode			=> IMode,
-			Halt			=> Halt,
-			NoRead		=> NoRead,
-			Write       => Write,
-			XYbit_undoc => XYbit_undoc);
-
-	alu : T80_ALU
-		generic map(
-			Mode		=> Mode,
-			Flag_C	=> Flag_C,
-			Flag_N	=> Flag_N,
-			Flag_P	=> Flag_P,
-			Flag_X	=> Flag_X,
-			Flag_H	=> Flag_H,
-			Flag_Y	=> Flag_Y,
-			Flag_Z	=> Flag_Z,
-			Flag_S	=> Flag_S)
-		port map(
-			Arith16	=> Arith16_r,
-			Z16		=> Z16_r,
-			ALU_Op	=> ALU_Op_r,
-			IR			=> IR(5 downto 0),
-			ISet		=> ISet,
-			BusA		=> BusA,
-			BusB		=> BusB,
-			F_In		=> F,
-			Q			=> ALU_Q,
-			F_Out		=> F_Out);
-
-	ClkEn <= CEN and not BusAck;
-
-	T_Res <= '1' when TState = unsigned(TStates) else '0';
-
-	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
-							((Set_Addr_To = aXY) or
-							(MCycle = "001" and IR = "11001011") or
-							(MCycle = "001" and IR = "00110110")) else '0';
-
-	Save_Mux <= BusB when ExchangeRp = '1' else
-		DI_Reg when Save_ALU_r = '0' else
-		ALU_Q;
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			PC <= (others => '0');  -- Program Counter
-			A <= (others => '0');
-			TmpAddr <= (others => '0');
-			IR <= "00000000";
-			ISet <= "00";
-			XY_State <= "00";
-			IStatus <= "00";
-			MCycles <= "000";
-			DO <= "00000000";
-
-			ACC <= (others => '1');
-			F <= (others => '1');
-			Ap <= (others => '1');
-			Fp <= (others => '1');
-			I <= (others => '0');
-			R <= (others => '0');
-			SP <= (others => '1');
-			Alternate <= '0';
-
-			Read_To_Reg_r <= "00000";
-			F <= (others => '1');
-			Arith16_r <= '0';
-			BTR_r <= '0';
-			Z16_r <= '0';
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			PreserveC_r <= '0';
-			XY_Ind <= '0';
-
-		elsif CLK_n'event and CLK_n = '1' then
-
-			if ClkEn = '1' then
-
-			ALU_Op_r <= "0000";
-			Save_ALU_r <= '0';
-			Read_To_Reg_r <= "00000";
-
-			MCycles <= MCycles_d;
-
-			if IMode /= "11" then
-				IStatus <= IMode;
-			end if;
-
-			Arith16_r <= Arith16;
-			PreserveC_r <= PreserveC;
-			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
-				Z16_r <= '1';
-			else
-				Z16_r <= '0';
-			end if;
-
-			if MCycle  = "001" and TState(2) = '0' then
-			-- MCycle = 1 and TState = 1, 2, or 3
-
-				if TState = 2 and Wait_n = '1' then
-					if Mode < 2 then
-						A(7 downto 0) <= std_logic_vector(R);
-						A(15 downto 8) <= I;
-						R(6 downto 0) <= R(6 downto 0) + 1;
-					end if;
-
-					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
-						PC <= PC + 1;
-					end if;
-
-					if IntCycle = '1' and IStatus = "01" then
-						IR <= "11111111";
-					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
-						IR <= "00000000";
-					else
-						IR <= DInst;
-					end if;
-
-					ISet <= "00";
-					if Prefix /= "00" then
-						if Prefix = "11" then
-							if IR(5) = '1' then
-								XY_State <= "10";
-							else
-								XY_State <= "01";
-							end if;
-						else
-							if Prefix = "10" then
-								XY_State <= "00";
-								XY_Ind <= '0';
-							end if;
-							ISet <= Prefix;
-						end if;
-					else
-						XY_State <= "00";
-						XY_Ind <= '0';
-					end if;
-				end if;
-
-			else
-			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
-				if MCycle = "110" then
-					XY_Ind <= '1';
-					if Prefix = "01" then
-						ISet <= "01";
-					end if;
-				end if;
-
-				if T_Res = '1' then
-					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
-					if Jump = '1' then
-						A(15 downto 8) <= DI_Reg;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(DI_Reg);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					elsif JumpXY = '1' then
-						A <= RegBusC;
-						PC <= unsigned(RegBusC);
-					elsif Call = '1' or RstP = '1' then
-						A <= TmpAddr;
-						PC <= unsigned(TmpAddr);
-					elsif MCycle = MCycles and NMICycle = '1' then
-						A <= "0000000001100110";
-						PC <= "0000000001100110";
-					elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
-						A(15 downto 8) <= I;
-						A(7 downto 0) <= TmpAddr(7 downto 0);
-						PC(15 downto 8) <= unsigned(I);
-						PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
-					else
-						case Set_Addr_To is
-						when aXY =>
-							if XY_State = "00" then
-								A <= RegBusC;
-							else
-								if NextIs_XY_Fetch = '1' then
-									A <= std_logic_vector(PC);
-								else
-									A <= TmpAddr;
-								end if;
-							end if;
-						when aIOA =>
-							if Mode = 3 then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-							elsif Mode = 2 then
-								-- Duplicate I/O address on 8080
-								A(15 downto 8) <= DI_Reg;
-							else
-								A(15 downto 8) <= ACC;
-							end if;
-							A(7 downto 0) <= DI_Reg;
-						when aSP =>
-							A <= std_logic_vector(SP);
-						when aBC =>
-							if Mode = 3 and IORQ_i = '1' then
-								-- Memory map I/O on GBZ80
-								A(15 downto 8) <= (others => '1');
-								A(7 downto 0) <= RegBusC(7 downto 0);
-							else
-								A <= RegBusC;
-							end if;
-						when aDE =>
-							A <= RegBusC;
-						when aZI =>
-							if Inc_WZ = '1' then
-								A <= std_logic_vector(unsigned(TmpAddr) + 1);
-							else
-								A(15 downto 8) <= DI_Reg;
-								A(7 downto 0) <= TmpAddr(7 downto 0);
-							end if;
-						when others =>
-							A <= std_logic_vector(PC);
-						end case;
-					end if;
-
-					Save_ALU_r <= Save_ALU;
-					ALU_Op_r <= ALU_Op;
-
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-				end if;
-
-				if TState = 2 and Wait_n = '1' then
-					if ISet = "01" and MCycle = "111" then
-						IR <= DInst;
-					end if;
-					if JumpE = '1' then
-						PC <= unsigned(signed(PC) + signed(DI_Reg));
-					elsif Inc_PC = '1' then
-						PC <= PC + 1;
-					end if;
-					if BTR_r = '1' then
-						PC <= PC - 2;
-					end if;
-					if RstP = '1' then
-						TmpAddr <= (others =>'0');
-						TmpAddr(5 downto 3) <= IR(5 downto 3);
-					end if;
-				end if;
-				if TState = 3 and MCycle = "110" then
-					TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
-				end if;
-
-				if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
-					if IncDec_16(2 downto 0) = "111" then
-						if IncDec_16(3) = '1' then
-							SP <= SP - 1;
-						else
-							SP <= SP + 1;
-						end if;
-					end if;
-				end if;
-
-				if LDSPHL = '1' then
-					SP <= unsigned(RegBusC);
-				end if;
-				if ExchangeAF = '1' then
-					Ap <= ACC;
-					ACC <= Ap;
-					Fp <= F;
-					F <= Fp;
-				end if;
-				if ExchangeRS = '1' then
-					Alternate <= not Alternate;
-				end if;
-			end if;
-
-			if TState = 3 then
-				if LDZ = '1' then
-					TmpAddr(7 downto 0) <= DI_Reg;
-				end if;
-				if LDW = '1' then
-					TmpAddr(15 downto 8) <= DI_Reg;
-				end if;
-
-				if Special_LD(2) = '1' then
-					case Special_LD(1 downto 0) is
-					when "00" =>
-						ACC <= I;
-						F(Flag_P) <= IntE_FF2;
-					when "01" =>
-						ACC <= std_logic_vector(R);
-						F(Flag_P) <= IntE_FF2;
-					when "10" =>
-						I <= ACC;
-					when others =>
-						R <= unsigned(ACC);
-					end case;
-				end if;
-			end if;
-
-			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
-				if Mode = 3 then
-					F(6) <= F_Out(6);
-					F(5) <= F_Out(5);
-					F(7) <= F_Out(7);
-					if PreserveC_r = '0' then
-						F(4) <= F_Out(4);
-					end if;
-				else
-					F(7 downto 1) <= F_Out(7 downto 1);
-					if PreserveC_r = '0' then
-						F(Flag_C) <= F_Out(0);
-					end if;
-				end if;
-			end if;
-			if T_Res = '1' and I_INRC = '1' then
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-				if DI_Reg(7 downto 0) = "00000000" then
-					F(Flag_Z) <= '1';
-				else
-					F(Flag_Z) <= '0';
-				end if;
-				F(Flag_S) <= DI_Reg(7);
-				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
-					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
-			end if;
-
-			if TState = 1 then
-				DO <= BusB;
-				if I_RLD = '1' then
-					DO(3 downto 0) <= BusA(3 downto 0);
-					DO(7 downto 4) <= BusB(3 downto 0);
-				end if;
-				if I_RRD = '1' then
-					DO(3 downto 0) <= BusB(7 downto 4);
-					DO(7 downto 4) <= BusA(3 downto 0);
-				end if;
-			end if;
-
-			if T_Res = '1' then
-				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
-				Read_To_Reg_r(4) <= Read_To_Reg;
-				if Read_To_Acc = '1' then
-					Read_To_Reg_r(3 downto 0) <= "0111";
-					Read_To_Reg_r(4) <= '1';
-				end if;
-			end if;
-
-			if TState = 1 and I_BT = '1' then
-				F(Flag_X) <= ALU_Q(3);
-				F(Flag_Y) <= ALU_Q(1);
-				F(Flag_H) <= '0';
-				F(Flag_N) <= '0';
-			end if;
-			if I_BC = '1' or I_BT = '1' then
-				F(Flag_P) <= IncDecZ;
-			end if;
-
-			if (TState = 1 and Save_ALU_r = '0') or
-				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-				case Read_To_Reg_r is
-				when "10111" =>
-					ACC <= Save_Mux;
-				when "10110" =>
-					DO <= Save_Mux;
-				when "11000" =>
-					SP(7 downto 0) <= unsigned(Save_Mux);
-				when "11001" =>
-					SP(15 downto 8) <= unsigned(Save_Mux);
-				when "11011" =>
-					F <= Save_Mux;
-				when others =>
-				end case;
-				if XYbit_undoc='1' then
-					DO <= ALU_Q;
-				end if;
-			end if;
-
-		end if;
-
-		end if;
-
-	end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-				-- Bus A / Write
-				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
-					RegAddrA_r <= XY_State(1) & "11";
-				end if;
-
-				-- Bus B
-				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
-				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
-					RegAddrB_r <= XY_State(1) & "11";
-				end if;
-
-				-- Address from register
-				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-				-- Jump (HL), LD SP,HL
-				if (JumpXY = '1' or LDSPHL = '1') then
-					RegAddrC <= Alternate & "10";
-				end if;
-				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
-					RegAddrC <= XY_State(1) & "11";
-				end if;
-
-				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
-					IncDecZ <= F_Out(Flag_Z);
-				end if;
-				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
-					if ID16 = 0 then
-						IncDecZ <= '0';
-					else
-						IncDecZ <= '1';
-					end if;
-				end if;
-
-				RegBusA_r <= RegBusA;
-			end if;
-		end if;
-	end process;
-
-	RegAddrA <=
-			-- 16 bit increment/decrement
-			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
-			XY_State(1) & "11" when (TState = 2 or
-				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-			-- EX HL,DL
-			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
-			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-			-- Bus A / Write
-			RegAddrA_r;
-
-	RegAddrB <=
-			-- EX HL,DL
-			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-			-- Bus B
-			RegAddrB_r;
-
-	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
-			signed(RegBusA) + 1;
-
-	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegWEH <= '0';
-		RegWEL <= '0';
-		if (TState = 1 and Save_ALU_r = '0') or
-			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
-			case Read_To_Reg_r is
-			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
-				RegWEH <= not Read_To_Reg_r(0);
-				RegWEL <= Read_To_Reg_r(0);
-			when others =>
-			end case;
-		end if;
-
-		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
-			RegWEH <= '1';
-			RegWEL <= '1';
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			case IncDec_16(1 downto 0) is
-			when "00" | "01" | "10" =>
-				RegWEH <= '1';
-				RegWEL <= '1';
-			when others =>
-			end case;
-		end if;
-	end process;
-
-	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
-	begin
-		RegDIH <= Save_Mux;
-		RegDIL <= Save_Mux;
-
-		if ExchangeDH = '1' and TState = 3 then
-			RegDIH <= RegBusB(15 downto 8);
-			RegDIL <= RegBusB(7 downto 0);
-		end if;
-		if ExchangeDH = '1' and TState = 4 then
-			RegDIH <= RegBusA_r(15 downto 8);
-			RegDIL <= RegBusA_r(7 downto 0);
-		end if;
-
-		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
-			RegDIH <= std_logic_vector(ID16(15 downto 8));
-			RegDIL <= std_logic_vector(ID16(7 downto 0));
-		end if;
-	end process;
-
-	Regs : T80_Reg
-		port map(
-			Clk	=> CLK_n,
-			CEN	=> ClkEn,
-			WEH	=> RegWEH,
-			WEL	=> RegWEL,
-			AddrA	=> RegAddrA,
-			AddrB	=> RegAddrB,
-			AddrC	=> RegAddrC,
-			DIH	=> RegDIH,
-			DIL	=> RegDIL,
-			DOAH	=> RegBusA(15 downto 8),
-			DOAL	=> RegBusA(7 downto 0),
-			DOBH	=> RegBusB(15 downto 8),
-			DOBL	=> RegBusB(7 downto 0),
-			DOCH	=> RegBusC(15 downto 8),
-			DOCL	=> RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '1' then
-			if ClkEn = '1' then
-			case Set_BusB_To is
-			when "0111" =>
-				BusB <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusB_To(0) = '1' then
-					BusB <= RegBusB(7 downto 0);
-				else
-					BusB <= RegBusB(15 downto 8);
-				end if;
-			when "0110" =>
-				BusB <= DI_Reg;
-			when "1000" =>
-				BusB <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusB <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusB <= "00000001";
-			when "1011" =>
-				BusB <= F;
-			when "1100" =>
-				BusB <= std_logic_vector(PC(7 downto 0));
-			when "1101" =>
-				BusB <= std_logic_vector(PC(15 downto 8));
-			when "1110" =>
-				BusB <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-
-			case Set_BusA_To is
-			when "0111" =>
-				BusA <= ACC;
-			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
-				if Set_BusA_To(0) = '1' then
-					BusA <= RegBusA(7 downto 0);
-				else
-					BusA <= RegBusA(15 downto 8);
-				end if;
-			when "0110" =>
-				BusA <= DI_Reg;
-			when "1000" =>
-				BusA <= std_logic_vector(SP(7 downto 0));
-			when "1001" =>
-				BusA <= std_logic_vector(SP(15 downto 8));
-			when "1010" =>
-				BusA <= "00000000";
-			when others =>
-				BusB <= "--------";
-			end case;
-			if XYbit_undoc='1' then
-				BusA <= DI_Reg;
-				BusB <= DI_Reg;
-			end if;
-			end if;
-		end if;
-	end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
-	process (RESET_n,CLK_n)
-	begin
-		if RESET_n = '0' then
-			RFSH_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
-				RFSH_n <= '0';
-			else
-				RFSH_n <= '1';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	MC <= std_logic_vector(MCycle);
-	TS <= std_logic_vector(TState);
-	DI_Reg <= DI;
-	HALT_n <= not Halt_FF;
-	BUSAK_n <= not BusAck;
-	IntCycle_n <= not IntCycle;
-	IntE <= IntE_FF1;
-	IORQ <= IORQ_i;
-	Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-		variable OldNMI_n : std_logic;
-	begin
-		if RESET_n = '0' then
-			BusReq_s <= '0';
-			INT_s <= '0';
-			NMI_s <= '0';
-			OldNMI_n := '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			BusReq_s <= not BUSRQ_n;
-			INT_s <= not INT_n;
-			if NMICycle = '1' then
-				NMI_s <= '0';
-			elsif NMI_n = '0' and OldNMI_n = '1' then
-				NMI_s <= '1';
-			end if;
-			OldNMI_n := NMI_n;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			MCycle <= "001";
-			TState <= "000";
-			Pre_XY_F_M <= "000";
-			Halt_FF <= '0';
-			BusAck <= '0';
-			NMICycle <= '0';
-			IntCycle <= '0';
-			IntE_FF1 <= '0';
-			IntE_FF2 <= '0';
-			No_BTR <= '0';
-			Auto_Wait_t1 <= '0';
-			Auto_Wait_t2 <= '0';
-			M1_n <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			if CEN = '1' then
-			Auto_Wait_t1 <= Auto_Wait;
-			Auto_Wait_t2 <= Auto_Wait_t1;
-			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
-					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
-					(I_BTR and (not IR(4) or F(Flag_Z)));
-			if TState = 2 then
-				if SetEI = '1' then
-					IntE_FF1 <= '1';
-					IntE_FF2 <= '1';
-				end if;
-				if I_RETN = '1' then
-					IntE_FF1 <= IntE_FF2;
-				end if;
-			end if;
-			if TState = 3 then
-				if SetDI = '1' then
-					IntE_FF1 <= '0';
-					IntE_FF2 <= '0';
-				end if;
-			end if;
-			if IntCycle = '1' or NMICycle = '1' then
-				Halt_FF <= '0';
-			end if;
-			if MCycle = "001" and TState = 2 and Wait_n = '1' then
-				M1_n <= '1';
-			end if;
-			if BusReq_s = '1' and BusAck = '1' then
-			else
-				BusAck <= '0';
-				if TState = 2 and Wait_n = '0' then
-				elsif T_Res = '1' then
-					if Halt = '1' then
-						Halt_FF <= '1';
-					end if;
-					if BusReq_s = '1' then
-						BusAck <= '1';
-					else
-						TState <= "001";
-						if NextIs_XY_Fetch = '1' then
-							MCycle <= "110";
-							Pre_XY_F_M <= MCycle;
-							if IR = "00110110" and Mode = 0 then
-								Pre_XY_F_M <= "010";
-							end if;
-						elsif (MCycle = "111") or
-							(MCycle = "110" and Mode = 1 and ISet /= "01") then
-							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
-						elsif (MCycle = MCycles) or
-							No_BTR = '1' or
-							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
-							M1_n <= '0';
-							MCycle <= "001";
-							IntCycle <= '0';
-							NMICycle <= '0';
-							if NMI_s = '1' and Prefix = "00" then
-								NMICycle <= '1';
-								IntE_FF1 <= '0';
-							elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
-								IntCycle <= '1';
-								IntE_FF1 <= '0';
-								IntE_FF2 <= '0';
-							end if;
-						else
-							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
-						end if;
-					end if;
-				else
-					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
-						TState <= TState + 1;
-					end if;
-				end if;
-			end if;
-			if TState = 0 then
-				M1_n <= '0';
-			end if;
-			end if;
-		end if;
-	end process;
-
-	process (IntCycle, NMICycle, MCycle)
-	begin
-		Auto_Wait <= '0';
-		if IntCycle = '1' or NMICycle = '1' then
-			if MCycle = "001" then
-				Auto_Wait <= '1';
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd
deleted file mode 100644
index 6bd576cf..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_ALU.vhd	
+++ /dev/null
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0238 : Fixed zero flag for 16 bit SBC and ADC
---
---      0240 : Added GB operations
---
---      0242 : Cleanup
---
---      0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
-	procedure AddSub(A		: std_logic_vector;
-					 B				: std_logic_vector;
-					 Sub			: std_logic;
-					 Carry_In	: std_logic;
-			  signal Res		: out std_logic_vector;
-			  signal Carry		: out std_logic) is
-
-		variable B_i			: unsigned(A'length - 1 downto 0);
-		variable Res_i			: unsigned(A'length + 1 downto 0);
-	begin
-		if Sub = '1' then
-			B_i := not unsigned(B);
-		else
-			B_i :=     unsigned(B);
-		end if;
-
-		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
-		Carry <= Res_i(A'length + 1);
-		Res <= std_logic_vector(Res_i(A'length downto 1));
-	end;
-
-	-- AddSub variables (temporary signals)
-	signal UseCarry                : std_logic;
-	signal Carry7_v                : std_logic;
-	signal Overflow_v              : std_logic;
-	signal HalfCarry_v             : std_logic;
-	signal Carry_v                 : std_logic;
-	signal Q_v                     : std_logic_vector(7 downto 0);
-
-	signal BitMask                 : std_logic_vector(7 downto 0);
-
-begin
-
-	with IR(5 downto 3) select BitMask <= "00000001" when "000",
-										  "00000010" when "001",
-										  "00000100" when "010",
-										  "00001000" when "011",
-										  "00010000" when "100",
-										  "00100000" when "101",
-										  "01000000" when "110",
-										  "10000000" when others;
-
-	UseCarry <= not ALU_Op(2) and ALU_Op(0);
-	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
-	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
-	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
-	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
-	process (Carry_v, Carry7_v, Q_v)
-	begin
-		if(Mode=2) then
-			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
-					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
-			OverFlow_v <= Carry_v xor Carry7_v;
-		end if;
-	end process;
-
-	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
-		variable Q_t : std_logic_vector(7 downto 0);
-		variable DAA_Q : unsigned(8 downto 0);
-	begin
-		Q_t := "--------";
-		F_Out <= F_In;
-		DAA_Q := "---------";
-		case ALU_Op is
-		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_C) <= '0';
-			case ALU_OP(2 downto 0) is
-			when "000" | "001" => -- ADD, ADC
-				Q_t := Q_v;
-				F_Out(Flag_C) <= Carry_v;
-				F_Out(Flag_H) <= HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "010" | "011" | "111" => -- SUB, SBC, CP
-				Q_t := Q_v;
-				F_Out(Flag_N) <= '1';
-				F_Out(Flag_C) <= not Carry_v;
-				F_Out(Flag_H) <= not HalfCarry_v;
-				F_Out(Flag_P) <= OverFlow_v;
-			when "100" => -- AND
-				Q_t(7 downto 0) := BusA and BusB;
-				F_Out(Flag_H) <= '1';
-			when "101" => -- XOR
-				Q_t(7 downto 0) := BusA xor BusB;
-				F_Out(Flag_H) <= '0';
-			when others => -- OR "110"
-				Q_t(7 downto 0) := BusA or BusB;
-				F_Out(Flag_H) <= '0';
-			end case;
-			if ALU_Op(2 downto 0) = "111" then -- CP
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			else
-				F_Out(Flag_X) <= Q_t(3);
-				F_Out(Flag_Y) <= Q_t(5);
-			end if;
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				if Z16 = '1' then
-					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
-				end if;
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			case ALU_Op(2 downto 0) is
-			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
-			when others =>
-				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			end case;
-			if Arith16 = '1' then
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-				F_Out(Flag_P) <= F_In(Flag_P);
-			end if;
-		when "1100" =>
-			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
-				end if;
-			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
-					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
-				end if;
-			end if;
-			F_Out(Flag_X) <= DAA_Q(3);
-			F_Out(Flag_Y) <= DAA_Q(5);
-			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
-			Q_t := std_logic_vector(DAA_Q(7 downto 0));
-			if DAA_Q(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= DAA_Q(7);
-			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
-				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
-		when "1101" | "1110" =>
-			-- RLD, RRD
-			Q_t(7 downto 4) := BusA(7 downto 4);
-			if ALU_Op(0) = '1' then
-				Q_t(3 downto 0) := BusB(7 downto 4);
-			else
-				Q_t(3 downto 0) := BusB(3 downto 0);
-			end if;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_S) <= Q_t(7);
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-		when "1001" =>
-			-- BIT
-			Q_t(7 downto 0) := BusB and BitMask;
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-				F_Out(Flag_P) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-				F_Out(Flag_P) <= '0';
-			end if;
-			F_Out(Flag_H) <= '1';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= '0';
-			F_Out(Flag_Y) <= '0';
-			if IR(2 downto 0) /= "110" then
-				F_Out(Flag_X) <= BusB(3);
-				F_Out(Flag_Y) <= BusB(5);
-			end if;
-		when "1010" =>
-			-- SET
-			Q_t(7 downto 0) := BusB or BitMask;
-		when "1011" =>
-			-- RES
-			Q_t(7 downto 0) := BusB and not BitMask;
-		when "1000" =>
-			-- ROT
-			case IR(5 downto 3) is
-			when "000" => -- RLC
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := BusA(7);
-				F_Out(Flag_C) <= BusA(7);
-			when "010" => -- RL
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(7);
-			when "001" => -- RRC
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(0);
-				F_Out(Flag_C) <= BusA(0);
-			when "011" => -- RR
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := F_In(Flag_C);
-				F_Out(Flag_C) <= BusA(0);
-			when "100" => -- SLA
-				Q_t(7 downto 1) := BusA(6 downto 0);
-				Q_t(0) := '0';
-				F_Out(Flag_C) <= BusA(7);
-			when "110" => -- SLL (Undocumented) / SWAP
-				if Mode = 3 then
-					Q_t(7 downto 4) := BusA(3 downto 0);
-					Q_t(3 downto 0) := BusA(7 downto 4);
-					F_Out(Flag_C) <= '0';
-				else
-					Q_t(7 downto 1) := BusA(6 downto 0);
-					Q_t(0) := '1';
-					F_Out(Flag_C) <= BusA(7);
-				end if;
-			when "101" => -- SRA
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := BusA(7);
-				F_Out(Flag_C) <= BusA(0);
-			when others => -- SRL
-				Q_t(6 downto 0) := BusA(7 downto 1);
-				Q_t(7) := '0';
-				F_Out(Flag_C) <= BusA(0);
-			end case;
-			F_Out(Flag_H) <= '0';
-			F_Out(Flag_N) <= '0';
-			F_Out(Flag_X) <= Q_t(3);
-			F_Out(Flag_Y) <= Q_t(5);
-			F_Out(Flag_S) <= Q_t(7);
-			if Q_t(7 downto 0) = "00000000" then
-				F_Out(Flag_Z) <= '1';
-			else
-				F_Out(Flag_Z) <= '0';
-			end if;
-			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
-				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
-			if ISet = "00" then
-				F_Out(Flag_P) <= F_In(Flag_P);
-				F_Out(Flag_S) <= F_In(Flag_S);
-				F_Out(Flag_Z) <= F_In(Flag_Z);
-			end if;
-		when others =>
-			null;
-		end case;
-		Q <= Q_t;
-	end process;
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd
deleted file mode 100644
index ee217402..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_MCode.vhd	
+++ /dev/null
@@ -1,2026 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0208 : First complete release
---
---      0211 : Fixed IM 1
---
---      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
---      0235 : Added IM 2 fix by Mike Johnson
---
---      0238 : Added NoRead signal
---
---      0238b: Fixed instruction timing for POP and DJNZ
---
---      0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
---      0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
---      0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
-	generic(
-		Mode : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in std_logic_vector(7 downto 0);
-		ISet			: in std_logic_vector(1 downto 0);
-		MCycle		: in std_logic_vector(2 downto 0);
-		F				: in std_logic_vector(7 downto 0);
-		NMICycle		: in std_logic;
-		IntCycle		: in std_logic;
-		XY_State		: in std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
-	constant aNone	: std_logic_vector(2 downto 0) := "111";
-	constant aBC	: std_logic_vector(2 downto 0) := "000";
-	constant aDE	: std_logic_vector(2 downto 0) := "001";
-	constant aXY	: std_logic_vector(2 downto 0) := "010";
-	constant aIOA	: std_logic_vector(2 downto 0) := "100";
-	constant aSP	: std_logic_vector(2 downto 0) := "101";
-	constant aZI	: std_logic_vector(2 downto 0) := "110";
-
-	function is_cc_true(
-		F : std_logic_vector(7 downto 0);
-		cc : bit_vector(2 downto 0)
-		) return boolean is
-	begin
-		if Mode = 3 then
-			case cc is
-			when "000" => return F(7) = '0'; -- NZ
-			when "001" => return F(7) = '1'; -- Z
-			when "010" => return F(4) = '0'; -- NC
-			when "011" => return F(4) = '1'; -- C
-			when "100" => return false;
-			when "101" => return false;
-			when "110" => return false;
-			when "111" => return false;
-			end case;
-		else
-			case cc is
-			when "000" => return F(6) = '0'; -- NZ
-			when "001" => return F(6) = '1'; -- Z
-			when "010" => return F(0) = '0'; -- NC
-			when "011" => return F(0) = '1'; -- C
-			when "100" => return F(2) = '0'; -- PO
-			when "101" => return F(2) = '1'; -- PE
-			when "110" => return F(7) = '0'; -- P
-			when "111" => return F(7) = '1'; -- M
-			end case;
-		end if;
-	end;
-
-begin
-
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
-		variable DDD : std_logic_vector(2 downto 0);
-		variable SSS : std_logic_vector(2 downto 0);
-		variable DPair : std_logic_vector(1 downto 0);
-		variable IRB : bit_vector(7 downto 0);
-	begin
-		DDD := IR(5 downto 3);
-		SSS := IR(2 downto 0);
-		DPair := IR(5 downto 4);
-		IRB := to_bitvector(IR);
-
-		MCycles <= "001";
-		if MCycle = "001" then
-			TStates <= "100";
-		else
-			TStates <= "011";
-		end if;
-		Prefix <= "00";
-		Inc_PC <= '0';
-		Inc_WZ <= '0';
-		IncDec_16 <= "0000";
-		Read_To_Acc <= '0';
-		Read_To_Reg <= '0';
-		Set_BusB_To <= "0000";
-		Set_BusA_To <= "0000";
-		ALU_Op <= "0" & IR(5 downto 3);
-		Save_ALU <= '0';
-		PreserveC <= '0';
-		Arith16 <= '0';
-		IORQ <= '0';
-		Set_Addr_To <= aNone;
-		Jump <= '0';
-		JumpE <= '0';
-		JumpXY <= '0';
-		Call <= '0';
-		RstP <= '0';
-		LDZ <= '0';
-		LDW <= '0';
-		LDSPHL <= '0';
-		Special_LD <= "000";
-		ExchangeDH <= '0';
-		ExchangeRp <= '0';
-		ExchangeAF <= '0';
-		ExchangeRS <= '0';
-		I_DJNZ <= '0';
-		I_CPL <= '0';
-		I_CCF <= '0';
-		I_SCF <= '0';
-		I_RETN <= '0';
-		I_BT <= '0';
-		I_BC <= '0';
-		I_BTR <= '0';
-		I_RLD <= '0';
-		I_RRD <= '0';
-		I_INRC <= '0';
-		SetDI <= '0';
-		SetEI <= '0';
-		IMode <= "11";
-		Halt <= '0';
-		NoRead <= '0';
-		Write <= '0';
-		XYbit_undoc <= '0';
-
-		case ISet is
-		when "00" =>
-
-------------------------------------------------------------------------------
---
---      Unprefixed instructions
---
-------------------------------------------------------------------------------
-
-		case IRB is
--- 8 BIT LOAD GROUP
-		when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-			|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-			|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-			|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-			|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-			|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-			|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-			-- LD r,r'
-			Set_BusB_To(2 downto 0) <= SSS;
-			ExchangeRp <= '1';
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-		when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-			-- LD r,n
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-			-- LD r,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Set_BusA_To(2 downto 0) <= DDD;
-				Read_To_Reg <= '1';
-			when others => null;
-			end case;
-		when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-			-- LD (HL),r
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110110" =>
-			-- LD (HL),n
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Set_Addr_To <= aXY;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00001010" =>
-			-- LD A,(BC)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00011010" =>
-			-- LD A,(DE)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-			when 2 =>
-				Read_To_Acc <= '1';
-			when others => null;
-			end case;
-		when "00111010" =>
-			if Mode = 3 then
-				-- LDD A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD A,(nn)
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-				when 4 =>
-					Read_To_Acc <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00000010" =>
-			-- LD (BC),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aBC;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00010010" =>
-			-- LD (DE),A
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aDE;
-				Set_BusB_To <= "0111";
-			when 2 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00110010" =>
-			if Mode = 3 then
-				-- LDD (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "1110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),A
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					Set_BusB_To <= "0111";
-				when 4 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 16 BIT LOAD GROUP
-		when "00000001"|"00010001"|"00100001"|"00110001" =>
-			-- LD dd,nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1000";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1001";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-		when "00101010" =>
-			if Mode = 3 then
-				-- LDI A,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					Read_To_Acc <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD HL,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Set_BusA_To(2 downto 0) <= "101"; -- L
-					Read_To_Reg <= '1';
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Set_BusA_To(2 downto 0) <= "100"; -- H
-					Read_To_Reg <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "00100010" =>
-			if Mode = 3 then
-				-- LDI (HL),A
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "0111";
-				when 2 =>
-					Write <= '1';
-					IncDec_16 <= "0110";
-				when others => null;
-				end case;
-			else
-				-- LD (nn),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "0101"; -- L
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "0100"; -- H
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11111001" =>
-			-- LD SP,HL
-			TStates <= "110";
-			LDSPHL <= '1';
-		when "11000101"|"11010101"|"11100101"|"11110101" =>
-			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "11000001"|"11010001"|"11100001"|"11110001" =>
-			-- POP qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "1011";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '1';
-				end if;
-			when 3 =>
-				IncDec_16 <= "0111";
-				Read_To_Reg <= '1';
-				if DPAIR = "11" then
-					Set_BusA_To(3 downto 0) <= "0111";
-				else
-					Set_BusA_To(2 downto 1) <= DPAIR;
-					Set_BusA_To(0) <= '0';
-				end if;
-			when others => null;
-			end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
-		when "11101011" =>
-			if Mode /= 3 then
-				-- EX DE,HL
-				ExchangeDH <= '1';
-			end if;
-		when "00001000" =>
-			if Mode = 3 then
-				-- LD (nn),SP
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					Set_BusB_To <= "1000";
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					Set_BusB_To <= "1001";
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EX AF,AF'
-				ExchangeAF <= '1';
-			end if;
-		when "11011001" =>
-			if Mode = 3 then
-				-- RETI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-					SetEI <= '1';
-				when others => null;
-				end case;
-			elsif Mode < 2 then
-				-- EXX
-				ExchangeRS <= '1';
-			end if;
-		when "11100011" =>
-			if Mode /= 3 then
-				-- EX (SP),HL
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aSP;
-				when 2 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0101";
-					Set_BusB_To <= "0101";
-					Set_Addr_To <= aSP;
-				when 3 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					Set_BusA_To <= "0100";
-					Set_BusB_To <= "0100";
-					Set_Addr_To <= aSP;
-				when 5 =>
-					IncDec_16 <= "1111";
-					TStates <= "101";
-					Write <= '1';
-				when others => null;
-				end case;
-			end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
-		when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-			|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-			|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-			|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-			|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-			|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-			|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-			|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-			-- ADD A,r
-			-- ADC A,r
-			-- SUB A,r
-			-- SBC A,r
-			-- AND A,r
-			-- OR A,r
-			-- XOR A,r
-			-- CP A,r
-			Set_BusB_To(2 downto 0) <= SSS;
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-		when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-			-- ADD A,(HL)
-			-- ADC A,(HL)
-			-- SUB A,(HL)
-			-- SBC A,(HL)
-			-- AND A,(HL)
-			-- OR A,(HL)
-			-- XOR A,(HL)
-			-- CP A,(HL)
-			MCycles <= "010";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			when others => null;
-			end case;
-		when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-			-- ADD A,n
-			-- ADC A,n
-			-- SUB A,n
-			-- SBC A,n
-			-- AND A,n
-			-- OR A,n
-			-- XOR A,n
-			-- CP A,n
-			MCycles <= "010";
-			if MCycle = "010" then
-				Inc_PC <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusA_To(2 downto 0) <= "111";
-			end if;
-		when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-			-- INC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0000";
-		when "00110100" =>
-			-- INC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				ALU_Op <= "0000";
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-		when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-			-- DEC r
-			Set_BusB_To <= "1010";
-			Set_BusA_To(2 downto 0) <= DDD;
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-			PreserveC <= '1';
-			ALU_Op <= "0010";
-		when "00110101" =>
-			-- DEC (HL)
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_To <= aXY;
-			when 2 =>
-				TStates <= "100";
-				Set_Addr_To <= aXY;
-				ALU_Op <= "0010";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				PreserveC <= '1';
-				Set_BusB_To <= "1010";
-				Set_BusA_To(2 downto 0) <= DDD;
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
-		when "00100111" =>
-			-- DAA
-			Set_BusA_To(2 downto 0) <= "111";
-			Read_To_Reg <= '1';
-			ALU_Op <= "1100";
-			Save_ALU <= '1';
-		when "00101111" =>
-			-- CPL
-			I_CPL <= '1';
-		when "00111111" =>
-			-- CCF
-			I_CCF <= '1';
-		when "00110111" =>
-			-- SCF
-			I_SCF <= '1';
-		when "00000000" =>
-			if NMICycle = '1' then
-				-- NMI
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when others => null;
-				end case;
-			elsif IntCycle = '1' then
-				-- INT (IM 2)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					LDZ <= '1';
-					TStates <= "101";
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1101";
-				when 2 =>
-					TStates <= "100";
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 3 =>
-					TStates <= "100";
-					Write <= '1';
-				when 4 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 5 =>
-					Jump <= '1';
-				when others => null;
-				end case;
-			else
-				-- NOP
-			end if;
-		when "01110110" =>
-			-- HALT
-			Halt <= '1';
-		when "11110011" =>
-			-- DI
-			SetDI <= '1';
-		when "11111011" =>
-			-- EI
-			SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
-		when "00001001"|"00011001"|"00101001"|"00111001" =>
-			-- ADD HL,ss
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				NoRead <= '1';
-				ALU_Op <= "0000";
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				Set_BusA_To(2 downto 0) <= "101";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-				when others =>
-					Set_BusB_To <= "1000";
-				end case;
-				TStates <= "100";
-				Arith16 <= '1';
-			when 3 =>
-				NoRead <= '1';
-				Read_To_Reg <= '1';
-				Save_ALU <= '1';
-				ALU_Op <= "0001";
-				Set_BusA_To(2 downto 0) <= "100";
-				case to_integer(unsigned(IR(5 downto 4))) is
-				when 0|1|2 =>
-					Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-				when others =>
-					Set_BusB_To <= "1001";
-				end case;
-				Arith16 <= '1';
-			when others =>
-			end case;
-		when "00000011"|"00010011"|"00100011"|"00110011" =>
-			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
-		when "00001011"|"00011011"|"00101011"|"00111011" =>
-			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
-		when "00000111"
-			-- RLCA
-			|"00010111"
-			-- RLA
-			|"00001111"
-			-- RRCA
-			|"00011111" =>
-			-- RRA
-			Set_BusA_To(2 downto 0) <= "111";
-			ALU_Op <= "1000";
-			Read_To_Reg <= '1';
-			Save_ALU <= '1';
-
--- JUMP GROUP
-		when "11000011" =>
-			-- JP nn
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				Inc_PC <= '1';
-				Jump <= '1';
-			when others => null;
-			end case;
-		when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+C),A
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-						Set_BusB_To     <= "0111";
-					when 2 =>
-						Write <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "01" =>
-					-- LD (nn),A
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						Set_BusB_To <= "0111";
-					when 4 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "10" =>
-					-- LD A,($FF00+C)
-					MCycles <= "010";
-					case to_integer(unsigned(MCycle)) is
-					when 1 =>
-						Set_Addr_To <= aBC;
-					when 2 =>
-						Read_To_Acc <= '1';
-						IORQ <= '1';
-					when others =>
-					end case;
-				when "11" =>
-					-- LD A,(nn)
-					MCycles <= "100";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-					when 4 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- JP cc,nn
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Jump <= '1';
-					end if;
-				when others => null;
-				end case;
-			end if;
-		when "00011000" =>
-			if Mode /= 2 then
-				-- JR e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00111000" =>
-			if Mode /= 2 then
-				-- JR C,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00110000" =>
-			if Mode /= 2 then
-				-- JR NC,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_C) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00101000" =>
-			if Mode /= 2 then
-				-- JR Z,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '0' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "00100000" =>
-			if Mode /= 2 then
-				-- JR NZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					if F(Flag_Z) = '1' then
-						MCycles <= "010";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-		when "11101001" =>
-			-- JP (HL)
-			JumpXY <= '1';
-		when "00010000" =>
-			if Mode = 3 then
-				I_DJNZ <= '1';
-			elsif Mode < 2 then
-				-- DJNZ,e
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					I_DJNZ <= '1';
-					Set_BusB_To <= "1010";
-					Set_BusA_To(2 downto 0) <= "000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					I_DJNZ <= '1';
-					Inc_PC <= '1';
-				when 3 =>
-					NoRead <= '1';
-					JumpE <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end if;
-
--- CALL AND RETURN GROUP
-		when "11001101" =>
-			-- CALL nn
-			MCycles <= "101";
-			case to_integer(unsigned(MCycle)) is
-			when 2 =>
-				Inc_PC <= '1';
-				LDZ <= '1';
-			when 3 =>
-				IncDec_16 <= "1111";
-				Inc_PC <= '1';
-				TStates <= "100";
-				Set_Addr_To <= aSP;
-				LDW <= '1';
-				Set_BusB_To <= "1101";
-			when 4 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 5 =>
-				Write <= '1';
-				Call <= '1';
-			when others => null;
-			end case;
-		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
-			if IR(5) = '0' or Mode /= 3 then
-				-- CALL cc,nn
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Inc_PC <= '1';
-					LDW <= '1';
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						IncDec_16 <= "1111";
-						Set_Addr_TO <= aSP;
-						TStates <= "100";
-						Set_BusB_To <= "1101";
-					else
-						MCycles <= "011";
-					end if;
-				when 4 =>
-					Write <= '1';
-					IncDec_16 <= "1111";
-					Set_Addr_To <= aSP;
-					Set_BusB_To <= "1100";
-				when 5 =>
-					Write <= '1';
-					Call <= '1';
-				when others => null;
-				end case;
-			end if;
-		when "11001001" =>
-			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
-		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
-			if IR(5) = '1' and Mode = 3 then
-				case IRB(4 downto 3) is
-				when "00" =>
-					-- LD ($FF00+nn),A
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-						Set_BusB_To     <= "0111";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				when "01" =>
-					-- ADD SP,n
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
-					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
-					when others =>
-					end case;
-				when "10" =>
-					-- LD A,($FF00+nn)
-					MCycles <= "011";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						Set_Addr_To <= aIOA;
-					when 3 =>
-						Read_To_Acc <= '1';
-					when others => null;
-					end case;
-				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
-					case to_integer(unsigned(MCycle)) is
-					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
-					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
-					when others => null;
-					end case;
-				end case;
-			else
-				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
-			end if;
-		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-			-- RST p
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1101";
-			when 2 =>
-				Write <= '1';
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				Set_BusB_To <= "1100";
-			when 3 =>
-				Write <= '1';
-				RstP <= '1';
-			when others => null;
-			end case;
-
--- INPUT AND OUTPUT GROUP
-		when "11011011" =>
-			if Mode /= 3 then
-				-- IN A,(n)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-				when 3 =>
-					Read_To_Acc <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-		when "11010011" =>
-			if Mode /= 3 then
-				-- OUT (n),A
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					Set_Addr_To <= aIOA;
-					Set_BusB_To <= "0111";
-				when 3 =>
-					Write <= '1';
-					IORQ <= '1';
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-				when others => null;
-				end case;
-			end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-		when "11001011" =>
-			if Mode /= 2 then
-				Prefix <= "01";
-			end if;
-
-		when "11101101" =>
-			if Mode < 2 then
-				Prefix <= "10";
-			end if;
-
-		when "11011101"|"11111101" =>
-			if Mode < 2 then
-				Prefix <= "11";
-			end if;
-
-		end case;
-
-		when "01" =>
-
-------------------------------------------------------------------------------
---
---      CB prefixed instructions
---
-------------------------------------------------------------------------------
-
-			Set_BusA_To(2 downto 0) <= IR(2 downto 0);
-			Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-				-- RLC r
-				-- RL r
-				-- RRC r
-				-- RR r
-				-- SLA r
-				-- SRA r
-				-- SRL r
-				-- SLL r (Undocumented) / SWAP r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1000";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- R/S (IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1000";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-				-- RLC (HL)
-				-- RL (HL)
-				-- RRC (HL)
-				-- RR (HL)
-				-- SRA (HL)
-				-- SRL (HL)
-				-- SLA (HL)
-				-- SLL (HL) (Undocumented) / SWAP (HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
-				|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
-				|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
-				|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
-				|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
-				|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
-				|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
-				|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-				-- BIT b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-					  ALU_Op <= "1001";
-					end if;
-				else
-				-- BIT b,(IX+d), undocumented
-					MCycles <= "010";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1001";
-						TStates <= "100";
-					when others => null;
-					end case;
-				end if;
-			when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-				-- BIT b,(HL)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1001";
-					TStates <= "100";
-				when others => null;
-				end case;
-			when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-				-- SET b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1010";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- SET b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1010";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-			when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-				-- SET b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7=>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1010";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
-				|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
-				|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
-				|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
-				|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-				-- RES b,r
-				if XY_State="00" then
-					if MCycle = "001" then
-					  ALU_Op <= "1011";
-					  Read_To_Reg <= '1';
-					  Save_ALU <= '1';
-					end if;
-				else
-				-- RES b,(IX+d),Reg, undocumented
-					MCycles <= "011";
-					XYbit_undoc <= '1';
-					case to_integer(unsigned(MCycle)) is
-					when 1 | 7=>
-						Set_Addr_To <= aXY;
-					when 2 =>
-						ALU_Op <= "1011";
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_Addr_To <= aXY;
-						TStates <= "100";
-					when 3 =>
-						Write <= '1';
-					when others => null;
-					end case;
-				end if;
-				
-			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-				-- RES b,(HL)
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 | 7 =>
-					Set_Addr_To <= aXY;
-				when 2 =>
-					ALU_Op <= "1011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-				when 3 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			end case;
-
-		when others =>
-
-------------------------------------------------------------------------------
---
---      ED prefixed instructions
---
-------------------------------------------------------------------------------
-
-			case IRB is
-			when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
-				|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
-				|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
-				|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
-				|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
-				|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
-				|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
-				|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
-				|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
-				|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
-				|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
-				|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
-				|                                            "10100100"|"10100101"|"10100110"|"10100111"
-				|                                            "10101100"|"10101101"|"10101110"|"10101111"
-				|                                            "10110100"|"10110101"|"10110110"|"10110111"
-				|                                            "10111100"|"10111101"|"10111110"|"10111111"
-				|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
-				|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
-				|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
-				|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
-				|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
-				|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
-				|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
-				|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
-				null; -- NOP, undocumented
-			when "01111110"|"01111111" =>
-				-- NOP, undocumented
-				null;
--- 8 BIT LOAD GROUP
-			when "01010111" =>
-				-- LD A,I
-				Special_LD <= "100";
-				TStates <= "101";
-			when "01011111" =>
-				-- LD A,R
-				Special_LD <= "101";
-				TStates <= "101";
-			when "01000111" =>
-				-- LD I,A
-				Special_LD <= "110";
-				TStates <= "101";
-			when "01001111" =>
-				-- LD R,A
-				Special_LD <= "111";
-				TStates <= "101";
--- 16 BIT LOAD GROUP
-			when "01001011"|"01011011"|"01101011"|"01111011" =>
-				-- LD dd,(nn)
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-				when 4 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1000";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '1';
-					end if;
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-				when 5 =>
-					Read_To_Reg <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusA_To <= "1001";
-					else
-						Set_BusA_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusA_To(0) <= '0';
-					end if;
-				when others => null;
-				end case;
-			when "01000011"|"01010011"|"01100011"|"01110011" =>
-				-- LD (nn),dd
-				MCycles <= "101";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Inc_PC <= '1';
-					LDZ <= '1';
-				when 3 =>
-					Set_Addr_To <= aZI;
-					Inc_PC <= '1';
-					LDW <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1000";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 4 =>
-					Inc_WZ <= '1';
-					Set_Addr_To <= aZI;
-					Write <= '1';
-					if IR(5 downto 4) = "11" then
-						Set_BusB_To <= "1001";
-					else
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-						Set_BusB_To(3) <= '0';
-					end if;
-				when 5 =>
-					Write <= '1';
-				when others => null;
-				end case;
-			when "10100000" | "10101000" | "10110000" | "10111000" =>
-				-- LDI, LDD, LDIR, LDDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0000";
-					Set_Addr_To <= aDE;
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- IX
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					I_BT <= '1';
-					TStates <= "101";
-					Write <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0101"; -- DE
-					else
-						IncDec_16 <= "1101";
-					end if;
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100001" | "10101001" | "10110001" | "10111001" =>
-				-- CPI, CPD, CPIR, CPDR
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aXY;
-					IncDec_16 <= "1100"; -- BC
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "0111";
-					Save_ALU <= '1';
-					PreserveC <= '1';
-					if IR(3) = '0' then
-						IncDec_16 <= "0110";
-					else
-						IncDec_16 <= "1110";
-					end if;
-				when 3 =>
-					NoRead <= '1';
-					I_BC <= '1';
-					TStates <= "101";
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-				-- NEG
-				Alu_OP <= "0010";
-				Set_BusB_To <= "0111";
-				Set_BusA_To <= "1010";
-				Read_To_Acc <= '1';
-				Save_ALU <= '1';
-			when "01000110"|"01001110"|"01100110"|"01101110" =>
-				-- IM 0
-				IMode <= "00";
-			when "01010110"|"01110110" =>
-				-- IM 1
-				IMode <= "01";
-			when "01011110"|"01110111" =>
-				-- IM 2
-				IMode <= "10";
--- 16 bit arithmetic
-			when "01001010"|"01011010"|"01101010"|"01111010" =>
-				-- ADC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0001";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					Set_BusB_To(0) <= '1';
-						when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0001";
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '0';
-					when others =>
-						Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01000010"|"01010010"|"01100010"|"01110010" =>
-				-- SBC HL,ss
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "101";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-						Set_BusB_To(0) <= '1';
-					when others =>
-						Set_BusB_To <= "1000";
-					end case;
-					TStates <= "100";
-				when 3 =>
-					NoRead <= '1';
-					ALU_Op <= "0011";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					Set_BusA_To(2 downto 0) <= "100";
-					case to_integer(unsigned(IR(5 downto 4))) is
-					when 0|1|2 =>
-						Set_BusB_To(2 downto 1) <= IR(5 downto 4);
-					when others =>
-							Set_BusB_To <= "1001";
-					end case;
-				when others =>
-				end case;
-			when "01101111" =>
-				-- RLD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					NoRead <= '1';
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1101";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RLD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01100111" =>
-				-- RRD
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 2 =>
-					Set_Addr_To <= aXY;
-				when 3 =>
-					Read_To_Reg <= '1';
-					Set_BusB_To(2 downto 0) <= "110";
-					Set_BusA_To(2 downto 0) <= "111";
-					ALU_Op <= "1110";
-					TStates <= "100";
-					Set_Addr_To <= aXY;
-					Save_ALU <= '1';
-				when 4 =>
-					I_RRD <= '1';
-					Write <= '1';
-				when others =>
-				end case;
-			when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-				-- RETI, RETN
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_TO <= aSP;
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-					I_RETN <= '1';
-				when others => null;
-				end case;
-			when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-				-- IN r,(C)
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					if IR(5 downto 3) /= "110" then
-						Read_To_Reg <= '1';
-						Set_BusA_To(2 downto 0) <= IR(5 downto 3);
-					end if;
-					I_INRC <= '1';
-				when others =>
-				end case;
-			when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-				-- OUT (C),r
-				-- OUT (C),0
-				MCycles <= "010";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To(2 downto 0)     <= IR(5 downto 3);
-					if IR(5 downto 3) = "110" then
-						Set_BusB_To(3) <= '1';
-					end if;
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					Write <= '1';
-					IORQ <= '1';
-				when others =>
-				end case;
-			when "10100010" | "10101010" | "10110010" | "10111010" =>
-				-- INI, IND, INIR, INDR
-				-- note B is decremented AFTER being put on the bus
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					Set_Addr_To <= aBC;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aXY;
-				when 3 =>
-					if IR(3) = '0' then
-						--IncDec_16 <= "0010";
-						IncDec_16 <= "0110";
-					else
-						--IncDec_16 <= "1010";
-						IncDec_16 <= "1110";
-					end if;
-					TStates <= "100";
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			when "10100011" | "10101011" | "10110011" | "10111011" =>
-				-- OUTI, OUTD, OTIR, OTDR
-				-- note B is decremented BEFORE being put on the bus.
-				-- mikej fix for hl inc
-				MCycles <= "100";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					TStates <= "101";
-					Set_Addr_To <= aXY;
-					Set_BusB_To <= "1010";
-					Set_BusA_To <= "0000";
-					Read_To_Reg <= '1';
-					Save_ALU <= '1';
-					ALU_Op <= "0010";
-				when 2 =>
-					Set_BusB_To <= "0110";
-					Set_Addr_To <= aBC;
-				when 3 =>
-					if IR(3) = '0' then
-						IncDec_16 <= "0110"; -- mikej
-					else
-						IncDec_16 <= "1110"; -- mikej
-					end if;
-					TStates <= "100"; -- MIKEJ should be 4 for IO cycle
-					IORQ <= '1';
-					Write <= '1';
-					I_BTR <= '1';
-				when 4 =>
-					NoRead <= '1';
-					TStates <= "101";
-				when others => null;
-				end case;
-			end case;
-
-		end case;
-
-		if Mode = 1 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "011";
-			end if;
-		end if;
-
-		if Mode = 3 then
-			if MCycle = "001" then
---              TStates <= "100";
-			else
-				TStates <= "100";
-			end if;
-		end if;
-
-		if Mode < 2 then
-			if MCycle = "110" then
-				Inc_PC <= '1';
-				if Mode = 1 then
-					Set_Addr_To <= aXY;
-					TStates <= "100";
-					Set_BusB_To(2 downto 0) <= SSS;
-					Set_BusB_To(3) <= '0';
-				end if;
-				if IRB = "00110110" or IRB = "11001011" then
-					Set_Addr_To <= aNone;
-				end if;
-			end if;
-			if MCycle = "111" then
-				if Mode = 0 then
-					TStates <= "101";
-				end if;
-				if ISet /= "01" then
-					Set_Addr_To <= aXY;
-				end if;
-				Set_BusB_To(2 downto 0) <= SSS;
-				Set_BusB_To(3) <= '0';
-				if IRB = "00110110" or ISet = "01" then
-					-- LD (HL),n
-					Inc_PC <= '1';
-				else
-					NoRead <= '1';
-				end if;
-			end if;
-		end if;
-
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd
deleted file mode 100644
index 679730ab..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Pack.vhd	
+++ /dev/null
@@ -1,220 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
-	component T80
-	generic(
-		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
-		Flag_C		: integer := 0;
-		Flag_N		: integer := 1;
-		Flag_P		: integer := 2;
-		Flag_X		: integer := 3;
-		Flag_H		: integer := 4;
-		Flag_Y		: integer := 5;
-		Flag_Z		: integer := 6;
-		Flag_S		: integer := 7
-	);
-	port(
-		RESET_n		: in  std_logic;
-		CLK_n			: in  std_logic;
-		CEN			: in  std_logic;
-		WAIT_n		: in  std_logic;
-		INT_n			: in  std_logic;
-		NMI_n			: in  std_logic;
-		BUSRQ_n		: in  std_logic;
-		M1_n			: out std_logic;
-		IORQ			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A				: out std_logic_vector(15 downto 0);
-		DInst			: in  std_logic_vector(7 downto 0);
-		DI				: in  std_logic_vector(7 downto 0);
-		DO				: out std_logic_vector(7 downto 0);
-		MC				: out std_logic_vector(2 downto 0);
-		TS				: out std_logic_vector(2 downto 0);
-		IntCycle_n	: out std_logic;
-		IntE			: out std_logic;
-		Stop			: out std_logic
-	);
-	end component;
-
-	component T80_Reg
-	port(
-		Clk			: in  std_logic;
-		CEN			: in  std_logic;
-		WEH			: in  std_logic;
-		WEL			: in  std_logic;
-		AddrA			: in  std_logic_vector(2 downto 0);
-		AddrB			: in  std_logic_vector(2 downto 0);
-		AddrC			: in  std_logic_vector(2 downto 0);
-		DIH			: in  std_logic_vector(7 downto 0);
-		DIL			: in  std_logic_vector(7 downto 0);
-		DOAH			: out std_logic_vector(7 downto 0);
-		DOAL			: out std_logic_vector(7 downto 0);
-		DOBH			: out std_logic_vector(7 downto 0);
-		DOBL			: out std_logic_vector(7 downto 0);
-		DOCH			: out std_logic_vector(7 downto 0);
-		DOCL			: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-	component T80_MCode
-	generic(
-		Mode   : integer := 0;
-		Flag_C : integer := 0;
-		Flag_N : integer := 1;
-		Flag_P : integer := 2;
-		Flag_X : integer := 3;
-		Flag_H : integer := 4;
-		Flag_Y : integer := 5;
-		Flag_Z : integer := 6;
-		Flag_S : integer := 7
-	);
-	port(
-		IR				: in  std_logic_vector(7 downto 0);
-		ISet			: in  std_logic_vector(1 downto 0);
-		MCycle		: in  std_logic_vector(2 downto 0);
-		F				: in  std_logic_vector(7 downto 0);
-		NMICycle		: in  std_logic;
-		IntCycle		: in  std_logic;
-		XY_State		: in  std_logic_vector(1 downto 0);
-		MCycles		: out std_logic_vector(2 downto 0);
-		TStates		: out std_logic_vector(2 downto 0);
-		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
-		Inc_PC		: out std_logic;
-		Inc_WZ		: out std_logic;
-		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
-		Read_To_Reg	: out std_logic;
-		Read_To_Acc	: out std_logic;
-		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
-		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
-		ALU_Op		: out std_logic_vector(3 downto 0);
-			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
-		Save_ALU		: out std_logic;
-		PreserveC	: out std_logic;
-		Arith16		: out std_logic;
-		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
-		IORQ			: out std_logic;
-		Jump			: out std_logic;
-		JumpE			: out std_logic;
-		JumpXY		: out std_logic;
-		Call			: out std_logic;
-		RstP			: out std_logic;
-		LDZ			: out std_logic;
-		LDW			: out std_logic;
-		LDSPHL		: out std_logic;
-		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
-		ExchangeDH	: out std_logic;
-		ExchangeRp	: out std_logic;
-		ExchangeAF	: out std_logic;
-		ExchangeRS	: out std_logic;
-		I_DJNZ		: out std_logic;
-		I_CPL			: out std_logic;
-		I_CCF			: out std_logic;
-		I_SCF			: out std_logic;
-		I_RETN		: out std_logic;
-		I_BT			: out std_logic;
-		I_BC			: out std_logic;
-		I_BTR			: out std_logic;
-		I_RLD			: out std_logic;
-		I_RRD			: out std_logic;
-		I_INRC		: out std_logic;
-		SetDI			: out std_logic;
-		SetEI			: out std_logic;
-		IMode			: out std_logic_vector(1 downto 0);
-		Halt			: out std_logic;
-		NoRead		: out std_logic;
-		Write			: out std_logic;
-		XYbit_undoc	: out std_logic
-	);
-	end component;
-
-	component T80_ALU
-	generic(
-		Mode		: integer := 0;
-		Flag_C	: integer := 0;
-		Flag_N	: integer := 1;
-		Flag_P	: integer := 2;
-		Flag_X	: integer := 3;
-		Flag_H	: integer := 4;
-		Flag_Y	: integer := 5;
-		Flag_Z	: integer := 6;
-		Flag_S	: integer := 7
-	);
-	port(
-		Arith16	: in  std_logic;
-		Z16		: in  std_logic;
-		ALU_Op	: in  std_logic_vector(3 downto 0);
-		IR			: in  std_logic_vector(5 downto 0);
-		ISet		: in  std_logic_vector(1 downto 0);
-		BusA		: in  std_logic_vector(7 downto 0);
-		BusB		: in  std_logic_vector(7 downto 0);
-		F_In		: in  std_logic_vector(7 downto 0);
-		Q			: out std_logic_vector(7 downto 0);
-		F_Out		: out std_logic_vector(7 downto 0)
-	);
-	end component;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd
deleted file mode 100644
index 828485fb..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80_Reg.vhd	
+++ /dev/null
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
---	0242 : Initial release
---
---	0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
-	port(
-		Clk			: in std_logic;
-		CEN			: in std_logic;
-		WEH			: in std_logic;
-		WEL			: in std_logic;
-		AddrA		: in std_logic_vector(2 downto 0);
-		AddrB		: in std_logic_vector(2 downto 0);
-		AddrC		: in std_logic_vector(2 downto 0);
-		DIH			: in std_logic_vector(7 downto 0);
-		DIL			: in std_logic_vector(7 downto 0);
-		DOAH		: out std_logic_vector(7 downto 0);
-		DOAL		: out std_logic_vector(7 downto 0);
-		DOBH		: out std_logic_vector(7 downto 0);
-		DOBL		: out std_logic_vector(7 downto 0);
-		DOCH		: out std_logic_vector(7 downto 0);
-		DOCL		: out std_logic_vector(7 downto 0)
-	);
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
-	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
-	signal	RegsH	: Register_Image(0 to 7);
-	signal	RegsL	: Register_Image(0 to 7);
-
-begin
-
-	process (Clk)
-	begin
-		if Clk'event and Clk = '1' then
-			if CEN = '1' then
-				if WEH = '1' then
-					RegsH(to_integer(unsigned(AddrA))) <= DIH;
-				end if;
-				if WEL = '1' then
-					RegsL(to_integer(unsigned(AddrA))) <= DIL;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	DOAH <= RegsH(to_integer(unsigned(AddrA)));
-	DOAL <= RegsL(to_integer(unsigned(AddrA)));
-	DOBH <= RegsH(to_integer(unsigned(AddrB)));
-	DOBL <= RegsL(to_integer(unsigned(AddrB)));
-	DOCH <= RegsH(to_integer(unsigned(AddrC)));
-	DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80as.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80as.vhd
deleted file mode 100644
index fe477f50..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80as.vhd	
+++ /dev/null
@@ -1,283 +0,0 @@
-------------------------------------------------------------------------------
--- t80as.vhd : The non-tristate signal edition of t80a.vhd
---
--- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
---
--- 1.separate 'D' to 'DO' and 'DI'.
--- 2.added 'DOE' to 'DO' enable signal.(data direction)
--- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
---
--- There is a mark of "--AS" in all the change points. 
---
-------------------------------------------------------------------------------
-
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---	http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---	0208 : First complete release
---
---	0211 : Fixed interrupt cycle
---
---	0235 : Updated for T80 interface change
---
---	0238 : Updated for T80 interface change
---
---	0240 : Updated for T80 interface change
---
---	0242 : Updated for T80 interface change
---
---	0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80as is
-	generic(
-		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
-	);
-	port(
-		RESET_n		: in std_logic;
-		CLK_n		: in std_logic;
-		WAIT_n		: in std_logic;
-		INT_n		: in std_logic;
-		NMI_n		: in std_logic;
-		BUSRQ_n		: in std_logic;
-		M1_n		: out std_logic;
-		MREQ_n		: out std_logic;
-		IORQ_n		: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n		: out std_logic;
-		HALT_n		: out std_logic;
-		BUSAK_n		: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
---AS--	D			: inout std_logic_vector(7 downto 0)
---AS>>
-		DI			: in  std_logic_vector(7 downto 0); 
-		DO			: out std_logic_vector(7 downto 0);
-		DOE			: out std_logic
---<<AS
-	);
-end T80as;
-
-architecture RTL of T80as is
-
-	signal CEN			: std_logic;
-	signal Reset_s		: std_logic;
-	signal IntCycle_n	: std_logic;
-	signal IORQ			: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal MREQ			: std_logic;
-	signal MReq_Inhibit	: std_logic;
-	signal Req_Inhibit	: std_logic;
-	signal RD			: std_logic;
-	signal MREQ_n_i		: std_logic;
-	signal IORQ_n_i		: std_logic;
-	signal RD_n_i		: std_logic;
-	signal WR_n_i		: std_logic;
-	signal RFSH_n_i		: std_logic;
-	signal BUSAK_n_i	: std_logic;
-	signal A_i			: std_logic_vector(15 downto 0);
---AS--	signal DO			: std_logic_vector(7 downto 0);
-	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
-	signal Wait_s		: std_logic;
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	CEN <= '1';
-
-	BUSAK_n <= BUSAK_n_i;
-	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
-	RD_n_i <= not RD or Req_Inhibit;
-
---AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
---AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
---AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
---AS>>
-	MREQ_n <= MREQ_n_i;
-	IORQ_n <= IORQ_n_i;
-	RD_n <= RD_n_i;
-	WR_n <= WR_n_i;
-	RFSH_n <= RFSH_n_i;
-	A <= A_i;
-	DOE <= Write when BUSAK_n_i = '1' else '0';
---<<AS
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			Reset_s <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			Reset_s <= '1';
-		end if;
-	end process;
-
-	u0 : T80
-		generic map(
-			Mode => Mode,
-			IOWait => 1)
-		port map(
-			CEN => CEN,
-			M1_n => M1_n,
-			IORQ => IORQ,
-			NoRead => NoRead,
-			Write => Write,
-			RFSH_n => RFSH_n_i,
-			HALT_n => HALT_n,
-			WAIT_n => Wait_s,
-			INT_n => INT_n,
-			NMI_n => NMI_n,
-			RESET_n => Reset_s,
-			BUSRQ_n => BUSRQ_n,
-			BUSAK_n => BUSAK_n_i,
-			CLK_n => CLK_n,
-			A => A_i,
---			DInst => D,
-			DInst => DI,
-			DI => DI_Reg,
-			DO => DO,
-			MC => MCycle,
-			TS => TState,
-			IntCycle_n => IntCycle_n);
-
-	process (CLK_n)
-	begin
-		if CLK_n'event and CLK_n = '0' then
-			Wait_s <= WAIT_n;
-			if TState = "011" and BUSAK_n_i = '1' then
---AS--				DI_Reg <= to_x01(D);
---AS>>
-				DI_Reg <= to_x01(DI);
---<<AS
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			WR_n_i <= '1';
-		elsif CLK_n'event and CLK_n = '1' then
-			WR_n_i <= '1';
-			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
-				WR_n_i <= not Write;
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			Req_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '1' then
-			if MCycle = "001" and TState = "010" then
-				Req_Inhibit <= '1';
-			else
-				Req_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process (Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			MReq_Inhibit <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-			if MCycle = "001" and TState = "010" then
-				MReq_Inhibit <= '1';
-			else
-				MReq_Inhibit <= '0';
-			end if;
-		end if;
-	end process;
-
-	process(Reset_s,CLK_n)
-	begin
-		if Reset_s = '0' then
-			RD <= '0';
-			IORQ_n_i <= '1';
-			MREQ <= '0';
-		elsif CLK_n'event and CLK_n = '0' then
-
-			if MCycle = "001" then
-				if TState = "001" then
-					RD <= IntCycle_n;
-					MREQ <= IntCycle_n;
-					IORQ_n_i <= IntCycle_n;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '1';
-				end if;
-				if TState = "100" then
-					MREQ <= '0';
-				end if;
-			else
-				if TState = "001" and NoRead = '0' then
-					RD <= not Write;
-					IORQ_n_i <= not IORQ;
-					MREQ <= not IORQ;
-				end if;
-				if TState = "011" then
-					RD <= '0';
-					IORQ_n_i <= '1';
-					MREQ <= '0';
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80sed.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80sed.vhd
deleted file mode 100644
index 9db00b93..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/cpu/T80sed.vhd	
+++ /dev/null
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
---      http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
---      0235 : First release
---
---      0236 : Added T2Write generic
---
---      0237 : Fixed T2Write with wait state
---
---      0238 : Updated for T80 interface change
---
---      0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
-	port(
-		RESET_n	: in  std_logic;
-		CLK_n		: in  std_logic;
-		CLKEN		: in  std_logic;
-		WAIT_n	: in  std_logic;
-		INT_n		: in  std_logic;
-		NMI_n		: in  std_logic;
-		BUSRQ_n	: in  std_logic;
-		M1_n		: out std_logic;
-		MREQ_n	: out std_logic;
-		IORQ_n	: out std_logic;
-		RD_n		: out std_logic;
-		WR_n		: out std_logic;
-		RFSH_n	: out std_logic;
-		HALT_n	: out std_logic;
-		BUSAK_n	: out std_logic;
-		A			: out std_logic_vector(15 downto 0);
-		DI			: in  std_logic_vector(7 downto 0);
-		DO			: out std_logic_vector(7 downto 0)
-	);
-end T80sed;
-
-architecture rtl of T80sed is
-
-	signal IntCycle_n	: std_logic;
-	signal NoRead		: std_logic;
-	signal Write		: std_logic;
-	signal IORQ			: std_logic;
-	signal DI_Reg		: std_logic_vector(7 downto 0);
-	signal MCycle		: std_logic_vector(2 downto 0);
-	signal TState		: std_logic_vector(2 downto 0);
-
-begin
-
-	u0 : T80
-		generic map(
-			Mode			=> 0,
-			IOWait		=> 1)
-		port map(
-			CEN			=> CLKEN,
-			M1_n			=> M1_n,
-			IORQ			=> IORQ,
-			NoRead		=> NoRead,
-			Write			=> Write,
-			RFSH_n		=> RFSH_n,
-			HALT_n		=> HALT_n,
-			WAIT_n		=> Wait_n,
-			INT_n			=> INT_n,
-			NMI_n			=> NMI_n,
-			RESET_n		=> RESET_n,
-			BUSRQ_n		=> BUSRQ_n,
-			BUSAK_n		=> BUSAK_n,
-			CLK_n			=> CLK_n,
-			A				=> A,
-			DInst			=> DI,
-			DI				=> DI_Reg,
-			DO				=> DO,
-			MC				=> MCycle,
-			TS				=> TState,
-			IntCycle_n	=> IntCycle_n);
-
-	process (RESET_n, CLK_n)
-	begin
-		if RESET_n = '0' then
-			RD_n <= '1';
-			WR_n <= '1';
-			IORQ_n <= '1';
-			MREQ_n <= '1';
-			DI_Reg <= "00000000";
-		elsif CLK_n'event and CLK_n = '1' then
-			if CLKEN = '1' then
-				RD_n <= '1';
-				WR_n <= '1';
-				IORQ_n <= '1';
-				MREQ_n <= '1';
-				if MCycle = "001" then
-					if TState = "001" or (TState = "010" and Wait_n = '0') then
-						RD_n <= not IntCycle_n;
-						MREQ_n <= not IntCycle_n;
-						IORQ_n <= IntCycle_n;
-					end if;
-					if TState = "011" then
-						MREQ_n <= '0';
-					end if;
-				else
-					if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
-						RD_n <= '0';
-						IORQ_n <= not IORQ;
-						MREQ_n <= IORQ;
-					end if;
-						if ((TState = "001") or (TState = "010")) and Write = '1' then
-							WR_n <= '0';
-							IORQ_n <= not IORQ;
-							MREQ_n <= IORQ;
-						end if;
-				end if;
-				if TState = "010" and Wait_n = '1' then
-					DI_Reg <= DI;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dac.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dac.vhd
deleted file mode 100644
index b1ecdcb7..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dac.vhd	
+++ /dev/null
@@ -1,71 +0,0 @@
--------------------------------------------------------------------------------
---
--- Delta-Sigma DAC
---
--- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
---
--- Refer to Xilinx Application Note XAPP154.
---
--- This DAC requires an external RC low-pass filter:
---
---   dac_o 0---XXXXX---+---0 analog audio
---              3k3    |
---                    === 4n7
---                     |
---                    GND
---
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity dac is
-
-  generic (
-    msbi_g : integer := 11
-  );
-  port (
-    clk_i   : in  std_logic;
-    res_n_i : in  std_logic;
-    dac_i   : in  std_logic_vector(msbi_g downto 0);
-    dac_o   : out std_logic
-  );
-
-end dac;
-
-library ieee;
-use ieee.numeric_std.all;
-
-architecture rtl of dac is
-
-  signal DACout_q      : std_logic;
-  signal DeltaAdder_s,
-         SigmaAdder_s,
-         SigmaLatch_q,
-         DeltaB_s      : unsigned(msbi_g+2 downto 0);
-
-begin
-
-  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
-                                        SigmaLatch_q(msbi_g+2);
-  DeltaB_s(msbi_g   downto        0) <= (others => '0');
-
-  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
-
-  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
-
-  seq: process (clk_i, res_n_i)
-  begin
-    if res_n_i = '0' then
-      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
-      DACout_q     <= '0';
-
-    elsif clk_i'event and clk_i = '1' then
-      SigmaLatch_q <= SigmaAdder_s;
-      DACout_q     <= SigmaLatch_q(msbi_g+2);
-    end if;
-  end process seq;
-
-  dac_o <= DACout_q;
-
-end rtl;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dpram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dpram.vhd
deleted file mode 100644
index dafe8385..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/dpram.vhd	
+++ /dev/null
@@ -1,75 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-entity dpram is
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clock_a		: IN STD_LOGIC  := '1';
-		clock_b		: IN STD_LOGIC ;
-		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		enable_a		: IN STD_LOGIC  := '1';
-		enable_b		: IN STD_LOGIC  := '1';
-		wren_a		: IN STD_LOGIC  := '0';
-		wren_b		: IN STD_LOGIC  := '0';
-		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END dpram;
-
-
-ARCHITECTURE SYN OF dpram IS
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "NORMAL",
-		clock_enable_input_b => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		indata_reg_b => "CLOCK1",
-		intended_device_family => "Cyclone V",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		numwords_b => 2**addr_width_g,
-		operation_mode => "BIDIR_DUAL_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_aclr_b => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		outdata_reg_b => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		widthad_b => addr_width_g,
-		width_a => data_width_g,
-		width_b => data_width_g,
-		width_byteena_a => 1,
-		width_byteena_b => 1,
-		wrcontrol_wraddress_reg_b => "CLOCK1"
-	)
-	PORT MAP (
-		address_a => address_a,
-		address_b => address_b,
-		clock0 => clock_a,
-		clock1 => clock_b,
-		clocken0 => enable_a,
-		clocken1 => enable_b,
-		data_a => data_a,
-		data_b => data_b,
-		wren_a => wren_a,
-		wren_b => wren_b,
-		q_a => q_a,
-		q_b => q_b
-	);
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/galaxian.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/galaxian.vhd
deleted file mode 100644
index a2c66505..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/galaxian.vhd	
+++ /dev/null
@@ -1,450 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA GALAXIAN
---
--- Version  downto  2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important  not
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
--- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---use work.pkg_galaxian.all;
-
-entity galaxian is
-	port(
-		W_CLK_18M  : in  std_logic;
-		W_CLK_12M  : in  std_logic;
-		W_CLK_6M   : in  std_logic;
-
-		P1_CSJUDLR : in  std_logic_vector(6 downto 0);
-		P2_CSJUDLR : in  std_logic_vector(6 downto 0);
-		I_RESET    : in  std_logic;
-
-		W_R        : out std_logic_vector(2 downto 0);
-		W_G        : out std_logic_vector(2 downto 0);
-		W_B        : out std_logic_vector(2 downto 0);
-		HBLANK     : out std_logic;
-		VBLANK     : out std_logic;
-		W_H_SYNC   : out std_logic;
-		W_V_SYNC   : out std_logic;
-		W_SDAT_A   : out std_logic_vector( 7 downto 0);
-		W_SDAT_B   : out std_logic_vector( 7 downto 0);
-		O_CMPBL    : out std_logic
-	);
-end;
-
-architecture RTL of galaxian is
-	--    CPU ADDRESS BUS
-	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
-	--    CPU IF
-	signal W_CPU_CLK          : std_logic := '0';
-	signal W_CPU_MREQn        : std_logic := '0';
-	signal W_CPU_NMIn         : std_logic := '0';
-	signal W_CPU_RDn          : std_logic := '0';
-	signal W_CPU_RFSHn        : std_logic := '0';
-	signal W_CPU_WAITn        : std_logic := '0';
-	signal W_CPU_WRn          : std_logic := '0';
-	signal W_CPU_WR           : std_logic := '0';
-	signal W_RESETn           : std_logic := '0';
-	-------- H and V COUNTER -------------------------
-	signal W_C_BLn            : std_logic := '0';
-	signal W_C_BLnX           : std_logic := '0';
-	signal W_C_BLXn           : std_logic := '0';
-	signal W_H_BL             : std_logic := '0';
-	signal W_H_SYNC_int       : std_logic := '0';
-	signal W_V_BLn            : std_logic := '0';
-	signal W_V_BL2n           : std_logic := '0';
-	signal W_V_SYNC_int       : std_logic := '0';
-	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
-	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
-	-------- CPU RAM  ----------------------------
-	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
-	-------- ADDRESS DECDER ----------------------
-	signal W_BD_G             : std_logic := '0';
-	signal W_CPU_RAM_CS       : std_logic := '0';
-	signal W_CPU_RAM_RD       : std_logic := '0';
---	signal W_CPU_RAM_WR       : std_logic := '0';
-	signal W_CPU_ROM_CS       : std_logic := '0';
-	signal W_DIP_OE           : std_logic := '0';
-	signal W_H_FLIP           : std_logic := '0';
-	signal W_DRIVER_WE        : std_logic := '0';
-	signal W_OBJ_RAM_RD       : std_logic := '0';
-	signal W_OBJ_RAM_RQ       : std_logic := '0';
-	signal W_OBJ_RAM_WR       : std_logic := '0';
-	signal W_PITCH            : std_logic := '0';
-	signal W_SOUND_WE         : std_logic := '0';
-	signal W_STARS_ON         : std_logic := '0';
-	signal W_STARS_OFFn       : std_logic := '0';
-	signal W_SW0_OE           : std_logic := '0';
-	signal W_SW1_OE           : std_logic := '0';
-	signal W_V_FLIP           : std_logic := '0';
-	signal W_VID_RAM_RD       : std_logic := '0';
-	signal W_VID_RAM_WR       : std_logic := '0';
-	signal W_WDR_OE           : std_logic := '0';
-	--------- INPORT -----------------------------
-	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
-	--------- VIDEO  -----------------------------
-	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
-	-----  DATA I/F -------------------------------------
-	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_CPU_RAM_CLK      : std_logic := '0';
-	signal W_VOL1             : std_logic := '0';
-	signal W_VOL2             : std_logic := '0';
-	signal W_FIRE             : std_logic := '0';
-	signal W_HIT              : std_logic := '0';
-	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal blx_comb           : std_logic := '0';
-	signal W_1VF              : std_logic := '0';
-	signal W_256HnX           : std_logic := '0';
-	signal W_8HF              : std_logic := '0';
-	signal W_DAC_A            : std_logic := '0';
-	signal W_DAC_B            : std_logic := '0';
-	signal W_MISSILEn         : std_logic := '0';
-	signal W_SHELLn           : std_logic := '0';
-	signal W_MS_D             : std_logic := '0';
-	signal W_MS_R             : std_logic := '0';
-	signal W_MS_G             : std_logic := '0';
-	signal W_MS_B             : std_logic := '0';
-
-	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
-	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
-	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
-	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
-	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
-
-begin
-	mc_vid : entity work.MC_VIDEO
-	port map(
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT       => W_H_CNT,
-		I_V_CNT       => W_V_CNT,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_FLIP      => W_V_FLIP,
-		I_V_BLn       => W_V_BLn,
-		I_C_BLn       => W_C_BLn,
-		I_A           => W_A(9 downto 0),
-		I_OBJ_SUB_A   => "000",
-		I_BD          => W_BDI,
-		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		I_VID_RAM_RD  => W_VID_RAM_RD,
-		I_VID_RAM_WR  => W_VID_RAM_WR,
-		I_DRIVER_WR   => W_DRIVER_WE,
-		O_C_BLnX      => W_C_BLnX,
-		O_8HF         => W_8HF,
-		O_256HnX      => W_256HnX,
-		O_1VF         => W_1VF,
-		O_MISSILEn    => W_MISSILEn,
-		O_SHELLn      => W_SHELLn,
-		O_BD          => W_VID_DO,
-		O_VID         => W_VID,
-		O_COL         => W_COL
-	);
-
-	cpu : entity work.T80as
-	port map (
-		RESET_n       => W_RESETn,
-		CLK_n         => W_CPU_CLK,
-		WAIT_n        => W_CPU_WAITn,
-		INT_n         => '1',
-		NMI_n         => W_CPU_NMIn,
-		BUSRQ_n       => '1',
-		MREQ_n        => W_CPU_MREQn,
-		RD_n          => W_CPU_RDn,
-		WR_n          => W_CPU_WRn,
-		RFSH_n        => W_CPU_RFSHn,
-		A             => W_A,
-		DI            => W_BDO,
-		DO            => W_BDI,
-		M1_n          => open,
-		IORQ_n        => open,
-		HALT_n        => open,
-		BUSAK_n       => open,
-		DOE           => open
-	);
-
-	mc_cpu_ram : entity work.MC_CPU_RAM
-	port map (
-		I_CLK         => W_CPU_RAM_CLK,
-		I_ADDR        => W_A(9 downto 0),
-		I_D           => W_BDI,
-		I_WE          => W_CPU_WR,
-		I_OE          => W_CPU_RAM_RD,
-		O_D           => W_CPU_RAM_DO
-	);
-
-	mc_adec : entity work.MC_ADEC
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_CPU_CLK     => W_CPU_CLK,
-		I_RSTn        => W_RESETn,
-
-		I_CPU_A       => W_A,
-		I_CPU_D       => W_BDI(0),
-		I_MREQn       => W_CPU_MREQn,
-		I_RFSHn       => W_CPU_RFSHn,
-		I_RDn         => W_CPU_RDn,
-		I_WRn         => W_CPU_WRn,
-		I_H_BL        => W_H_BL,
-		I_V_BLn       => W_V_BLn,
-
-		O_WAITn       => W_CPU_WAITn,
-		O_NMIn        => W_CPU_NMIn,
-		O_CPU_ROM_CS  => W_CPU_ROM_CS,
-		O_CPU_RAM_RD  => W_CPU_RAM_RD,
---		O_CPU_RAM_WR  => W_CPU_RAM_WR,
-		O_CPU_RAM_CS  => W_CPU_RAM_CS,
-		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
-		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
-		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
-		O_VID_RAM_RD  => W_VID_RAM_RD,
-		O_VID_RAM_WR  => W_VID_RAM_WR,
-		O_SW0_OE      => W_SW0_OE,
-		O_SW1_OE      => W_SW1_OE,
-		O_DIP_OE      => W_DIP_OE,
-		O_WDR_OE      => W_WDR_OE,
-		O_DRIVER_WE   => W_DRIVER_WE,
-		O_SOUND_WE    => W_SOUND_WE,
-		O_PITCH       => W_PITCH,
-		O_H_FLIP      => W_H_FLIP,
-		O_V_FLIP      => W_V_FLIP,
-		O_BD_G        => W_BD_G,
-		O_STARS_ON    => W_STARS_ON
-	);
-
-	-- active high buttons
-	mc_inport : entity work.MC_INPORT
-	port map (
-		I_COIN1       => P1_CSJUDLR(6),
-		I_COIN2       => P2_CSJUDLR(6),
-		I_1P_START    => P1_CSJUDLR(5),
-		I_2P_START    => P2_CSJUDLR(5),
-		I_1P_SH       => P1_CSJUDLR(4),
-		I_2P_SH       => P2_CSJUDLR(4),
-		I_1P_UP		  => P1_CSJUDLR(3),
-		I_2P_UP		  => P2_CSJUDLR(3),
-		I_1P_DW       => P1_CSJUDLR(2),
-		I_2P_DW       => P2_CSJUDLR(2),
-		I_1P_LE       => P1_CSJUDLR(1),
-		I_2P_LE       => P2_CSJUDLR(1),
-		I_1P_RI       => P1_CSJUDLR(0),
-		I_2P_RI       => P2_CSJUDLR(0),
-		I_SW0_OE      => W_SW0_OE,
-		I_SW1_OE      => W_SW1_OE,
-		I_DIP_OE      => W_DIP_OE,
-		O_D           => W_SW_DO
-	);
-
-	mc_hv : entity work.MC_HV_COUNT
-	port map(
-		I_CLK         => W_CLK_6M,
-		I_RSTn        => W_RESETn,
-		O_H_CNT       => W_H_CNT,
-		O_H_SYNC      => W_H_SYNC_int,
-		O_H_BL        => W_H_BL,
-		O_V_CNT       => W_V_CNT,
-		O_V_SYNC      => W_V_SYNC_int,
-		O_V_BL2n      => W_V_BL2n,
-		O_V_BLn       => W_V_BLn,
-		O_C_BLn       => W_C_BLn
-	);
-
-	mc_col_pal : entity work.MC_COL_PAL
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_VID         => W_VID,
-		I_COL         => W_COL,
-		I_C_BLnX      => W_C_BLnX,
-		O_C_BLXn      => W_C_BLXn,
-		O_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_VIDEO_R,
-		O_G           => W_VIDEO_G,
-		O_B           => W_VIDEO_B
-	);
-
-	mc_stars : entity work.MC_STARS
-	port map (
-		I_CLK_18M     => W_CLK_18M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_FLIP      => W_H_FLIP,
-		I_V_SYNC      => W_V_SYNC_int,
-		I_8HF         => W_8HF,
-		I_256HnX      => W_256HnX,
-		I_1VF         => W_1VF,
-		I_2V          => W_V_CNT(1),
-		I_STARS_ON    => W_STARS_ON,
-		I_STARS_OFFn  => W_STARS_OFFn,
-		O_R           => W_STARS_R,
-		O_G           => W_STARS_G,
-		O_B           => W_STARS_B,
-		O_NOISE       => open
-	);
-
-	mc_sound_a : entity work.MC_SOUND_A
-	port map(
-		I_CLK_12M     => W_CLK_12M,
-		I_CLK_6M      => W_CLK_6M,
-		I_H_CNT1      => W_H_CNT(1),
-		I_BD          => W_BDI,
-		I_PITCH       => W_PITCH,
-		I_VOL1        => W_VOL1,
-		I_VOL2        => W_VOL2,
-		O_SDAT        => W_SDAT_A,
-		O_DO          => open
-	);
-
-	vmc_sound_b : entity work.MC_SOUND_B
-	port map(
-		I_CLK1        => W_CLK_6M,
-		I_RSTn        => rst_count(3),
-		I_SW          => new_sw,
-		I_DAC         => W_DAC,
-		I_FS          => W_FS,
-		O_SDAT        => W_SDAT_B
-	);
-
---------- ROM           -------------------------------------------------------
-	mc_roms : entity work.ROM_PGM_0
-	port map (
-		CLK  => W_CLK_12M,
-		ADDR => W_A(13 downto 0),
-		DATA => W_CPU_ROM_DO
-	);
-
--------- VIDEO  -----------------------------
-	blx_comb <= not ( W_C_BLXn and W_V_BL2n );
-	W_V_SYNC <= not W_V_SYNC_int;
-	W_H_SYNC <= not W_H_SYNC_int;
-	O_CMPBL  <= W_C_BLnX;
-	
-	-- MISSILE => Yellow ;
-	-- SHELL   => White  ;
-	W_MS_D <= not (W_MISSILEn and W_SHELLn);
-	W_MS_R <= not   blx_comb  and W_MS_D;
-	W_MS_G <= not   blx_comb  and W_MS_D;
-	W_MS_B <= not   blx_comb  and W_MS_D and not W_SHELLn ;
-
-	W_R <= W_VIDEO_R or (W_STARS_R & "0") or (W_MS_R & W_MS_R & "0");
-	W_G <= W_VIDEO_G or (W_STARS_G & "0") or (W_MS_G & W_MS_G & "0");
-	W_B <= W_VIDEO_B or (W_STARS_B & "0") or (W_MS_B & W_MS_B & "0");
-
-	process(W_CLK_6M)
-	begin
-		if rising_edge(W_CLK_6M) then
-			HBLANK   <= not W_C_BLXn;
-			VBLANK   <= not W_V_BL2n;
-		end if;
-	end process;
-
-
------  CPU I/F  -------------------------------------
-
-	W_CPU_CLK     <= W_H_CNT(0);
-	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
-
-	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
-
-	W_RESETn  <= not I_RESET;
-	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
-	W_CPU_WR  <= not W_CPU_WRn;
-
-	new_sw <= (W_FS(2) or W_FS(1) or W_FS(0)) & W_HIT & W_FIRE;
-
-	process(W_CPU_CLK, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			rst_count <= (others => '0');
-		elsif rising_edge( W_CPU_CLK) then
-			if ( rst_count /= x"f") then
-				rst_count <= rst_count + 1;
-			end if;
-		end if;
-	end process;
-
------  Parts 9L ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_FS   <= (others=>'0');
-			W_HIT  <= '0';
-			W_FIRE <= '0';
-			W_VOL1 <= '0';
-			W_VOL2 <= '0';
-		elsif rising_edge(W_CLK_12M) then
-			if (W_SOUND_WE = '1') then
-				case(W_A(2 downto 0)) is
-					when "000" => W_FS(0) <= W_BDI(0);
-					when "001" => W_FS(1) <= W_BDI(0);
-					when "010" => W_FS(2) <= W_BDI(0);
-					when "011" => W_HIT   <= W_BDI(0);
---					when "100" => UNUSED  <= W_BDI(0);
-					when "101" => W_FIRE  <= W_BDI(0);
-					when "110" => W_VOL1  <= W_BDI(0);
-					when "111" => W_VOL2  <= W_BDI(0);
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
------  Parts 9M ---------
-	process(W_CLK_12M, I_RESET)
-	begin
-		if (I_RESET = '1') then
-			W_DAC   <= (others=>'0');
-		elsif rising_edge(W_CLK_12M) then
-			if (W_DRIVER_WE = '1') then
-				case(W_A(2 downto 0)) is
-					-- next 4 outputs go off board via ULN2075 buffer
---					when "000" => 1P START  <= W_BDI(0);
---					when "001" => 2P START  <= W_BDI(0);
---					when "010" => COIN LOCK <= W_BDI(0);
---					when "011" => COIN CTR  <= W_BDI(0);
-					when "100" => W_DAC(0)  <= W_BDI(0); --   1M
-					when "101" => W_DAC(1)  <= W_BDI(0); -- 470K
-					when "110" => W_DAC(2)  <= W_BDI(0); -- 220K
-					when "111" => W_DAC(3)  <= W_BDI(0); -- 100K
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
--------------------------------------------------------------------------------
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/hq2x.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/hq2x.sv
deleted file mode 100644
index f17732b6..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/hq2x.sv	
+++ /dev/null
@@ -1,454 +0,0 @@
-//
-//
-// Copyright (c) 2012-2013 Ludvig Strigeus
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-module hq2x_in #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input            rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input            wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-	wire [DWIDTH:0] out[2];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-endmodule
-
-
-module hq2x_out #(parameter LENGTH, parameter DWIDTH)
-(
-	input            clk,
-
-	input [AWIDTH:0] rdaddr,
-	input      [1:0] rdbuf,
-	output[DWIDTH:0] q,
-
-	input [AWIDTH:0] wraddr,
-	input      [1:0] wrbuf,
-	input [DWIDTH:0] data,
-	input            wren
-);
-
-	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
-	wire  [DWIDTH:0] out[4];
-	assign q = out[rdbuf];
-
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
-	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
-endmodule
-
-
-module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
-(
-	input	            clock,
-	input	 [DWIDTH:0] data,
-	input	 [AWIDTH:0] rdaddress,
-	input	 [AWIDTH:0] wraddress,
-	input	            wren,
-	output [DWIDTH:0] q
-);
-
-	altsyncram	altsyncram_component (
-				.address_a (wraddress),
-				.clock0 (clock),
-				.data_a (data),
-				.wren_a (wren),
-				.address_b (rdaddress),
-				.q_b(q),
-				.aclr0 (1'b0),
-				.aclr1 (1'b0),
-				.addressstall_a (1'b0),
-				.addressstall_b (1'b0),
-				.byteena_a (1'b1),
-				.byteena_b (1'b1),
-				.clock1 (1'b1),
-				.clocken0 (1'b1),
-				.clocken1 (1'b1),
-				.clocken2 (1'b1),
-				.clocken3 (1'b1),
-				.data_b ({(DWIDTH+1){1'b1}}),
-				.eccstatus (),
-				.q_a (),
-				.rden_a (1'b1),
-				.rden_b (1'b1),
-				.wren_b (1'b0));
-	defparam
-		altsyncram_component.address_aclr_b = "NONE",
-		altsyncram_component.address_reg_b = "CLOCK0",
-		altsyncram_component.clock_enable_input_a = "BYPASS",
-		altsyncram_component.clock_enable_input_b = "BYPASS",
-		altsyncram_component.clock_enable_output_b = "BYPASS",
-		altsyncram_component.intended_device_family = "Cyclone III",
-		altsyncram_component.lpm_type = "altsyncram",
-		altsyncram_component.numwords_a = NUMWORDS,
-		altsyncram_component.numwords_b = NUMWORDS,
-		altsyncram_component.operation_mode = "DUAL_PORT",
-		altsyncram_component.outdata_aclr_b = "NONE",
-		altsyncram_component.outdata_reg_b = "UNREGISTERED",
-		altsyncram_component.power_up_uninitialized = "FALSE",
-		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
-		altsyncram_component.widthad_a = AWIDTH+1,
-		altsyncram_component.widthad_b = AWIDTH+1,
-		altsyncram_component.width_a = DWIDTH+1,
-		altsyncram_component.width_b = DWIDTH+1,
-		altsyncram_component.width_byteena_a = 1;
-
-endmodule
-
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module DiffCheck
-(
-	input [17:0] rgb1,
-	input [17:0] rgb2,
-	output result
-);
-
-	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
-	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
-	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
-	wire [6:0] t = $signed(r) + $signed(b);
-	wire [6:0] gx = {g[5], g};
-	wire [7:0] y = $signed(t) + $signed(gx);
-	wire [6:0] u = $signed(r) - $signed(b);
-	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
-
-	// if y is inside (-24..24)
-	wire y_inside = (y < 8'h18 || y >= 8'he8);
-
-	// if u is inside (-4, 4)
-	wire u_inside = (u < 7'h4 || u >= 7'h7c);
-
-	// if v is inside (-6, 6)
-	wire v_inside = (v < 8'h6 || v >= 8'hfA);
-	assign result = !(y_inside && u_inside && v_inside);
-endmodule
-
-module InnerBlend
-(
-	input  [8:0] Op,
-	input  [5:0] A,
-	input  [5:0] B,
-	input  [5:0] C,
-	output [5:0] O
-);
-
-	function  [8:0] mul6x3;
-		input  [5:0] op1;
-		input  [2:0] op2;
-	begin
-		mul6x3 = 9'd0;
-		if(op2[0]) mul6x3 = mul6x3 + op1;
-		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
-		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
-	end
-	endfunction
-
-	wire OpOnes = Op[4];
-	wire [8:0] Amul = mul6x3(A, Op[7:5]);
-	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
-	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
-	wire [8:0] At =  Amul;
-	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
-	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
-	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
-	assign O = Op[8] ? A : Res[9:4];
-endmodule
-
-module Blend
-(
-	input   [5:0] rule,
-	input         disable_hq2x,
-	input  [17:0] E,
-	input  [17:0] A,
-	input  [17:0] B,
-	input  [17:0] D,
-	input  [17:0] F,
-	input  [17:0] H,
-	output [17:0] Result
-);
-
-	reg [1:0] input_ctrl;
-	reg [8:0] op;
-	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
-	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
-	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
-	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
-	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
-	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
-	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
-	localparam AB = 2'b00;
-	localparam AD = 2'b01;
-	localparam DB = 2'b10;
-	localparam BD = 2'b11;
-	wire is_diff;
-	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
-
-	always @* begin
-		case({!is_diff, rule[5:2]})
-			1,17:  {op, input_ctrl} = {BLEND1, AB};
-			2,18:  {op, input_ctrl} = {BLEND1, DB};
-			3,19:  {op, input_ctrl} = {BLEND1, BD};
-			4,20:  {op, input_ctrl} = {BLEND2, DB};
-			5,21:  {op, input_ctrl} = {BLEND2, AB};
-			6,22:  {op, input_ctrl} = {BLEND2, AD};
-
-			8: {op, input_ctrl} = {BLEND0, 2'bxx};
-			9: {op, input_ctrl} = {BLEND0, 2'bxx};
-			10: {op, input_ctrl} = {BLEND0, 2'bxx};
-			11: {op, input_ctrl} = {BLEND1, AB};
-			12: {op, input_ctrl} = {BLEND1, AB};
-			13: {op, input_ctrl} = {BLEND1, AB};
-			14: {op, input_ctrl} = {BLEND1, DB};
-			15: {op, input_ctrl} = {BLEND1, BD};
-
-			24: {op, input_ctrl} = {BLEND2, DB};
-			25: {op, input_ctrl} = {BLEND5, DB};
-			26: {op, input_ctrl} = {BLEND6, DB};
-			27: {op, input_ctrl} = {BLEND2, DB};
-			28: {op, input_ctrl} = {BLEND4, DB};
-			29: {op, input_ctrl} = {BLEND5, DB};
-			30: {op, input_ctrl} = {BLEND3, BD};
-			31: {op, input_ctrl} = {BLEND3, DB};
-			default: {op, input_ctrl} = 11'bx;
-		endcase
-
-		// Setting op[8] effectively disables HQ2X because blend will always return E.
-		if (disable_hq2x) op[8] = 1;
-	end
-
-	// Generate inputs to the inner blender. Valid combinations.
-	// 00: E A B
-	// 01: E A D 
-	// 10: E D B
-	// 11: E B D
-	wire [17:0] Input1 = E;
-	wire [17:0] Input2 = !input_ctrl[1] ? A :
-                        !input_ctrl[0] ? D : B;
-
-	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
-	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
-	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
-	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
-endmodule
-
-
-////////////////////////////////////////////////////////////////////////////////////////////////////
-
-module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	input               clk,
-	input               ce_x4,
-	input    [DWIDTH:0] inputpixel,
-	input               mono,
-	input               disable_hq2x,
-	input               reset_frame,
-	input               reset_line,
-	input         [1:0] read_y,
-	input  [AWIDTH+1:0] read_x,
-	output   [DWIDTH:0] outpixel
-);
-
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-localparam DWIDTH = HALF_DEPTH ? 8 : 17;
-
-wire [5:0] hqTable[256] = '{
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
-	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
-};
-
-reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
-reg [17:0] A, B, D, F, G, H;
-reg  [7:0] pattern, nextpatt;
-reg  [1:0] i;
-reg  [7:0] y;
-
-wire curbuf = y[0];
-reg  prevbuf = 0;
-wire iobuf = !curbuf;
-
-wire diff0, diff1;
-DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
-DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
-
-wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
-
-wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
-wire [17:0] blend_result;
-Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
-
-reg             Curr2_addr1;
-reg  [AWIDTH:0] Curr2_addr2;
-wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
-wire [DWIDTH:0] Curr2tmp;
-
-reg  [AWIDTH:0] wrin_addr2;
-reg  [DWIDTH:0] wrpix;
-reg             wrin_en;
-
-function [17:0] h2rgb;
-	input  [8:0] v;
-begin
-	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
-end
-endfunction
-
-function  [8:0] rgb2h;
-	input [17:0] v;
-begin
-	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
-end
-endfunction
-
-hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
-(
-	.clk(clk),
-
-	.rdaddr(Curr2_addr2),
-	.rdbuf(Curr2_addr1),
-	.q(Curr2tmp),
-
-	.wraddr(wrin_addr2),
-	.wrbuf(iobuf),
-	.data(wrpix),
-	.wren(wrin_en)
-);
-
-reg         [1:0] wrout_addr1;
-reg  [AWIDTH+1:0] wrout_addr2;
-reg               wrout_en;
-reg    [DWIDTH:0] wrdata;
-
-hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
-(
-	.clk(clk),
-
-	.rdaddr(read_x),
-	.rdbuf(read_y),
-	.q(outpixel),
-
-	.wraddr(wrout_addr2),
-	.wrbuf(wrout_addr1),
-	.data(wrdata),
-	.wren(wrout_en)
-);
-
-always @(posedge clk) begin
-	reg [AWIDTH:0] offs;
-	reg old_reset_line;
-	reg old_reset_frame;
-
-	wrout_en <= 0;
-	wrin_en  <= 0;
-
-	if(ce_x4) begin
-
-		pattern <= new_pattern;
-
-		if(~&offs) begin
-			if (i == 0) begin
-				Curr2_addr1 <= prevbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 1) begin
-				Prev2 <= Curr2;
-				Curr2_addr1 <= curbuf;
-				Curr2_addr2 <= offs;
-			end
-			if (i == 2) begin
-				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
-				wrpix <= inputpixel;
-				wrin_addr2 <= offs;
-				wrin_en <= 1;
-			end
-			if (i == 3) begin
-				offs <= offs + 1'd1;
-			end
-
-			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
-			else           wrdata <= blend_result;
-
-			wrout_addr1 <= {curbuf, i[1]};
-			wrout_addr2 <= {offs, i[1]^i[0]};
-			wrout_en    <= 1;
-		end
-
-		if(i==3) begin
-			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
-			{A, G} <= {Prev0, Next0};
-			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
-			{Prev0, Prev1} <= {Prev1, Prev2};
-			{Curr0, Curr1} <= {Curr1, Curr2};
-			{Next0, Next1} <= {Next1, Next2};
-		end else begin
-			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
-			{B, F, H, D} <= {F, H, D, B};
-		end
-
-		i <= i + 1'b1;
-		if(old_reset_line && ~reset_line) begin
-			old_reset_frame <= reset_frame;
-			offs <= 0;
-			i <= 0;
-			y <= y + 1'd1;
-			prevbuf <= curbuf;
-			if(old_reset_frame & ~reset_frame) begin
-				y <= 0;
-				prevbuf <= 0;
-			end
-		end
-
-		old_reset_line  <= reset_line;
-	end
-end
-
-endmodule  // Hq2x
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_adec.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_adec.vhd
deleted file mode 100644
index 7245ce8c..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_adec.vhd	
+++ /dev/null
@@ -1,251 +0,0 @@
----------------------------------------------------------------------
--- FPGA GALAXIAN ADDRESS DECDER
---
--- Version : 2.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 4-30  galaxian modify by K.DEGAWA
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.
----------------------------------------------------------------------
---
---GALAXIAN Address Map
---
--- Address      Item(R..read-mode W..wight-mode)        Parts
---0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
---2000 - 3FFF   CPU-ROM..R                            ( 7L )
---4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
---5000 - 57FF   VID-RAM..RW
---5800 - 5FFF   OBJ-RAM..RW
---6000 -        SW0..R   LAMP......W
---6800 -        SW1..R   SOUND.....W
---7000 -        DIP..R
---7001                   NMI_ON....W
---7004                   STARS_ON..W
---7006                   H_FLIP....W
---7007                   V-FLIP....W
---7800          WDR..R   PITCH.....W
---
---W MODE
---6000                  1P START
---6001                  2P START
---6002                  COIN LOCKOUT
---6003                  COIN COUNTER
---6004 - 6007           SOUND CONTROL(OSC)
---
---6800                  SOUND CONTROL(FS1)
---6801                  SOUND CONTROL(FS2)
---6802                  SOUND CONTROL(FS3)
---6803                  SOUND CONTROL(HIT)
---6805                  SOUND CONTROL(SHOT)
---6806                  SOUND CONTROL(VOL1)
---6807                  SOUND CONTROL(VOL2)
---
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_ADEC is
-	port (
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_CPU_CLK     : in  std_logic;
-		I_RSTn        : in  std_logic;
-
-		I_CPU_A       : in  std_logic_vector(15 downto 0);
-		I_CPU_D       : in  std_logic;
-		I_MREQn       : in  std_logic;
-		I_RFSHn       : in  std_logic;
-		I_RDn         : in  std_logic;
-		I_WRn         : in  std_logic;
-		I_H_BL        : in  std_logic;
-		I_V_BLn       : in  std_logic;
-
-		O_WAITn       : out std_logic;
-		O_NMIn        : out std_logic;
-		O_CPU_ROM_CS  : out std_logic;
-		O_CPU_RAM_RD  : out std_logic;
-		O_CPU_RAM_WR  : out std_logic;
-		O_CPU_RAM_CS  : out std_logic;
-		O_OBJ_RAM_RD  : out std_logic;
-		O_OBJ_RAM_WR  : out std_logic;
-		O_OBJ_RAM_RQ  : out std_logic;
-		O_VID_RAM_RD  : out std_logic;
-		O_VID_RAM_WR  : out std_logic;
-		O_SW0_OE      : out std_logic;
-		O_SW1_OE      : out std_logic;
-		O_DIP_OE      : out std_logic;
-		O_WDR_OE      : out std_logic;
-		O_DRIVER_WE   : out std_logic;
-		O_SOUND_WE    : out std_logic;
-		O_PITCH       : out std_logic;
-		O_H_FLIP      : out std_logic;
-		O_V_FLIP      : out std_logic;
-		O_BD_G        : out std_logic;
-		O_STARS_ON    : out std_logic
-	);
-end;
-
-architecture RTL of MC_ADEC is
-	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_NMI_ONn : std_logic := '0';
-	--------  CPU WAITn  ----------------------------------------------
---	signal W_6S1_Q   : std_logic := '0';
-	signal W_6S1_Qn  : std_logic := '0';
---	signal W_6S2_Qn  : std_logic := '0';
-
-	signal W_V_BL    : std_logic := '0';
-
-begin
-		W_NMI_ONn <= W_9N_Q(1); --  galaxian
-
---		O_WAITn <= '1' ; -- No Wait
-		O_WAITn <= W_6S1_Qn;
-
-	process(I_CPU_CLK, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
---			W_6S1_Q  <= '0';
-			W_6S1_Qn <= '1';
-		elsif rising_edge(I_CPU_CLK) then
---			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
-			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
-		end if;
-	end process;
-
---	process(I_CPU_CLK)
---	begin
---		if falling_edge(I_CPU_CLK) then
---			W_6S2_Qn <= not W_6S1_Q;
---		end if;
---	end process;
-
---------  CPU NMIn  -----------------------------------------------
-	W_V_BL <= not I_V_BLn;
-	process(W_V_BL, W_NMI_ONn)
-	begin
-		if (W_NMI_ONn = '0') then
-			O_NMIn  <= '1';
-		elsif rising_edge(W_V_BL) then
-			O_NMIn  <= '0';
-		end if;
-	end process;
-
-	-------------------------------------------------------------------
-	u_8e1 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_MREQn,
-		I_Sel(1) => I_CPU_A(15),
-		I_Sel(0) => I_CPU_A(14),
-		O_Q      => W_8E1_Q
-	);
-
-	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
-	u_8e2 : entity work.LOGIC_74XX139
-	port map (
-		I_G      => I_RDn,
-		I_Sel(1) => W_8E1_Q(0),
-		I_Sel(0) => I_CPU_A(13),
-		O_Q      => W_8E2_Q
-	);
-
-	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
-	-------------------------------------------------------------------
-	--                  ADDRESS
-	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
-	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
-	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
-	--    W_8E1_Q[3] = C000 - FFFF
-
-	u_8p : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => I_RFSHn,
-		I_G2a => W_8E1_Q(1),   -- <= *1
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8P_Q
-	);
-
-	u_8n : entity work.LOGIC_74XX138
-	port map (
-		I_G1  => '1',
-		I_G2a => I_RDn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8N_Q
-	);
-
-	u_8m : entity work.LOGIC_74XX138
-	port map (
-	--	I_G1  => W_6S2_Qn,
-		I_G1  => '1', -- No Wait
-		I_G2a => I_WRn,
-		I_G2b => W_8E1_Q(1),   -- <= *1
-		I_Sel => I_CPU_A(13 downto 11),
-		O_Q   => W_8M_Q
-	);
-
-	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
-	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
-
-	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
-
-	O_WDR_OE      <= not W_8N_Q(7);
-	O_DIP_OE      <= not W_8N_Q(6);
-	O_SW1_OE      <= not W_8N_Q(5);
-	O_SW0_OE      <= not W_8N_Q(4);
-	O_OBJ_RAM_RD  <= not W_8N_Q(3);
-	O_VID_RAM_RD  <= not W_8N_Q(2);
---	UNUSED        <= not W_8N_Q(1);
-	O_CPU_RAM_RD  <= not W_8N_Q(0);
-
-	O_PITCH       <= not W_8M_Q(7);
---	STARS_ON_ENA  <= not W_8M_Q(6);
-	O_SOUND_WE    <= not W_8M_Q(5);
-	O_DRIVER_WE   <= not W_8M_Q(4);
-	O_OBJ_RAM_WR  <= not W_8M_Q(3);
-	O_VID_RAM_WR  <= not W_8M_Q(2);
---	UNUSED        <= not W_8M_Q(1);
-	O_CPU_RAM_WR  <= not W_8M_Q(0);
-
-	-----  Parts 9N ---------
-
-	process(I_CLK_12M, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			W_9N_Q <= (others => '0');
-		elsif rising_edge(I_CLK_12M) then
-			if (W_8M_Q(6) = '0') then
-				case I_CPU_A(2 downto 0) is
-					when "000"  => W_9N_Q(0) <= I_CPU_D;
-					when "001"  => W_9N_Q(1) <= I_CPU_D;
-					when "010"  => W_9N_Q(2) <= I_CPU_D;
-					when "011"  => W_9N_Q(3) <= I_CPU_D;
-					when "100"  => W_9N_Q(4) <= I_CPU_D;
-					when "101"  => W_9N_Q(5) <= I_CPU_D;
-					when "110"  => W_9N_Q(6) <= I_CPU_D;
-					when "111"  => W_9N_Q(7) <= I_CPU_D;
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	O_STARS_ON <= W_9N_Q(4);
-	O_H_FLIP   <= W_9N_Q(6);
-	O_V_FLIP   <= W_9N_Q(7);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_bram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_bram.vhd
deleted file mode 100644
index a6df1ce1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_bram.vhd	
+++ /dev/null
@@ -1,182 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA & GALAXIAN
---      FPGA BLOCK RAM I/F (XILINX SPARTAN)
---
--- Version : 2.50
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- mc_col_rom(6L) added by k.Degawa
---
--- 2004- 5- 6  first release.
--- 2004- 8-23  Improvement with T80-IP.    K.Degawa
--- 2004- 9-18  added Xilinx Device         K.Degawa
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_top.v use
-entity MC_CPU_RAM is
-	port (
-		I_CLK  : in  std_logic;
-		I_ADDR : in  std_logic_vector(9 downto 0);
-		I_D    : in  std_logic_vector(7 downto 0);
-		I_WE   : in  std_logic;
-		I_OE   : in  std_logic;
-		O_D    : out std_logic_vector(7 downto 0)
-	);
-end;
-architecture RTL of MC_CPU_RAM is
-
-	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
-begin
-	O_D <= W_D when I_OE ='1' else (others=>'0');
-
-	ram_inst : work.spram generic map(10,8)
-	port map
-	(
-		address  => I_ADDR,
-		clock    => I_CLK,
-		data     => I_D,
-		wren		=> I_WE,
-		q			=> W_D
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_OBJ_RAM is
-	port(
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(7 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(7 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-	end;
-
-architecture RTL of MC_OBJ_RAM is
-begin
-
-	ram_inst : work.dpram generic map(8,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_VID_RAM is
-	port (
-		I_CLKA  : in  std_logic := '0';
-		I_WEA   : in  std_logic := '0';
-		I_CEA   : in  std_logic := '0';
-		I_ADDRA : in  std_logic_vector(9 downto 0);
-		I_DA    : in  std_logic_vector(7 downto 0);
-		O_DA    : out std_logic_vector(7 downto 0);
-
-		I_CLKB  : in  std_logic := '0';
-		I_WEB   : in  std_logic := '0';
-		I_CEB   : in  std_logic := '0';
-		I_ADDRB : in  std_logic_vector(9 downto 0);
-		I_DB    : in  std_logic_vector(7 downto 0);
-		O_DB    : out std_logic_vector(7 downto 0)
-	);
-end;
-
-architecture RTL of MC_VID_RAM is
-begin
-	ram_inst : work.dpram generic map(10,8)
-	port map
-	(
-		clock_a		=> I_CLKA,
-		address_a	=> I_ADDRA,
-		data_a		=> I_DA,
-		q_a			=> O_DA,
-		enable_a    => I_CEA,
-		wren_a		=> I_WEA,
-
-		clock_b		=> I_CLKB,
-		address_b	=> I_ADDRB,
-		data_b		=> I_DB,
-		q_b			=> O_DB,
-		enable_b    => I_CEB,
-		wren_b		=> I_WEB
-	);
-end RTL;
-
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---  mc_video.v use
-entity MC_LRAM is
-	port (
-		I_CLK   : in  std_logic;
-		I_ADDR  : in  std_logic_vector(7 downto 0);
-		I_D     : in  std_logic_vector(4 downto 0);
-		I_WE    : in  std_logic;
-		O_Dn    : out std_logic_vector(4 downto 0)
-	);
-end;
-
-architecture RTL of MC_LRAM is
-	signal W_D  : std_logic_vector(4 downto 0) := (others => '0');
-begin
-
-	O_Dn <= not W_D;
-
-	ram_inst : work.dpram generic map(8,5)
-	port map
-	(
-		clock_a		=> I_CLK,
-		address_a	=> I_ADDR,
-		data_a		=> I_D,
-		wren_a		=> not I_WE,
-
-		clock_b		=> not I_CLK,
-		address_b	=> I_ADDR,
-		data_b		=> (others => '0'),
-		q_b			=> W_D,
-		enable_b    => '1',
-		wren_b		=> '0'
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_clocks.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_clocks.vhd
deleted file mode 100644
index 5a4d0094..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_clocks.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA CLOCK GEN
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity CLOCKGEN is
-port (
-	CLKIN_IN        : in  std_logic;
-	RST_IN          : in  std_logic;
-	--
-	O_CLK_24M       : out std_logic;
-	O_CLK_18M       : out std_logic;
-	O_CLK_12M       : out std_logic;
-	O_CLK_06M       : out std_logic
-);
-end;
-
-architecture RTL of CLOCKGEN is
-	signal state                    : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr1                     : std_logic_vector(1 downto 0) := (others => '0');
-	signal ctr2                     : std_logic_vector(2 downto 0) := (others => '0');
-	signal CLKFB_IN                 : std_logic := '0';
-	signal CLK0_BUF                 : std_logic := '0';
-	signal CLKFX_BUF                : std_logic := '0';
-	signal CLK_72M                  : std_logic := '0';
-	signal I_DCM_LOCKED             : std_logic := '0';
-
-begin
-	dcm_inst : DCM_SP
-	generic map (
-		CLKFX_MULTIPLY => 9,
-		CLKFX_DIVIDE   => 4,
-		CLKIN_PERIOD   => 31.25
-	)
-	port map (
-		CLKIN    => CLKIN_IN,
-		CLKFB    => CLKFB_IN,
-		RST      => RST_IN,
-		CLK0     => CLK0_BUF,
-		CLKFX    => CLKFX_BUF,
-		LOCKED   => I_DCM_LOCKED
-	);
-
-	BUFG0  : BUFG  port map (I=> CLK0_BUF,  O => CLKFB_IN);
-	BUFG1  : BUFG  port map (I=> CLKFX_BUF, O => CLK_72M);
-	O_CLK_06M <= ctr2(2);
-	O_CLK_12M <= ctr2(1);
-	O_CLK_24M <= ctr2(0);
-	O_CLK_18M <= ctr1(1);
-
-	-- generate all clocks, 36Mhz, 18Mhz, 24Mhz, 12Mhz and 6Mhz
-	process(CLK_72M)
-	begin
-		if rising_edge(CLK_72M) then
-			if (I_DCM_LOCKED = '0') then
-				state <= "00";
-				ctr1 <= (others=>'0');
-				ctr2 <= (others=>'0');
-			else
-				ctr1 <= ctr1 + 1;
-				case state is
-					when "00" => state <= "01"; ctr2 <= ctr2 + 1;
-					when "01" => state <= "10"; ctr2 <= ctr2 + 1;
-					when "10" => state <= "00";
-					when "11" => state <= "00";
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_col_pal.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_col_pal.vhd
deleted file mode 100644
index c4dc06ad..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_col_pal.vhd	
+++ /dev/null
@@ -1,78 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA COLOR-PALETTE
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-18 added Xilinx Device.  K.Degawa
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
---  use ieee.numeric_std.all;
-
---library UNISIM;
---  use UNISIM.Vcomponents.all;
-
-entity MC_COL_PAL is
-port (
-	I_CLK_12M    : in  std_logic;
-	I_CLK_6M     : in  std_logic;
-	I_VID        : in  std_logic_vector(1 downto 0);
-	I_COL        : in  std_logic_vector(2 downto 0);
-	I_C_BLnX     : in  std_logic;
-
-	O_C_BLXn     : out std_logic;
-	O_STARS_OFFn : out std_logic;
-	O_R          : out std_logic_vector(2 downto 0);
-	O_G          : out std_logic_vector(2 downto 0);
-	O_B          : out std_logic_vector(2 downto 0)
-);
-end;
-
-architecture RTL of MC_COL_PAL is
-	---    Parts 6M    --------------------------------------------------------
-	signal W_COL_ROM_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6M_DI      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_DO      : std_logic_vector(6 downto 0) := (others => '0');
-	signal W_6M_CLR     : std_logic := '0';
-
-begin
-	W_6M_DI      <= I_COL(2 downto 0) & I_VID(1 downto 0) & not (I_VID(0) or I_VID(1)) & I_C_BLnX;
-	W_6M_CLR     <= W_6M_DI(0) or W_6M_DO(0);
-	O_C_BLXn     <= W_6M_DI(0) or W_6M_DO(0);
-	O_STARS_OFFn <= W_6M_DO(1);
-
---always@(posedge I_CLK_6M or negedge W_6M_CLR)
-	process(I_CLK_6M, W_6M_CLR)
-	begin
-		if (W_6M_CLR = '0') then
-			W_6M_DO <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			W_6M_DO <= W_6M_DI;
-		end if;
-	end process;
-
-	---    COL ROM     --------------------------------------------------------
---wire   W_COL_ROM_OEn = W_6M_DO[1];
-
-	galaxian_6l : entity work.GALAXIAN_6L
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_6M_DO(6 downto 2),
-		DATA => W_COL_ROM_DO
-	);
-
-	---    VID OUT     --------------------------------------------------------
-	O_R <= W_COL_ROM_DO(2 downto 0);
-	O_G <= W_COL_ROM_DO(5 downto 3);
-	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_hv_count.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_hv_count.vhd
deleted file mode 100644
index f310321b..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_hv_count.vhd	
+++ /dev/null
@@ -1,145 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA   H & V COUNTER 
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use. 
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22  
------------------------------------------------------------------------
---  MoonCrest hv_count
---  H_CNT   0 - 255 , 384 - 511  Total 384 count
---  V_CNT   0 - 255 , 504 - 511  Total 264 count
--------------------------------------------------------------------------------------------
--- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
---    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
--------------------------------------------------------------------------------------------
--- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
---    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_HV_COUNT is
-	port(
-		I_CLK    : in  std_logic;
-		I_RSTn   : in  std_logic;
-		O_H_CNT  : out std_logic_vector(8 downto 0);
-		O_H_SYNC : out std_logic;
-		O_H_BL   : out std_logic;
-		O_V_BL2n : out std_logic;
-		O_V_CNT  : out std_logic_vector(7 downto 0);
-		O_V_SYNC : out std_logic;
-		O_V_BLn  : out std_logic;
-		O_C_BLn  : out std_logic
-	);
-end;
-
-architecture RTL of MC_HV_COUNT is
-	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
-	signal H_SYNC : std_logic := '0';
-	signal H_CLK  : std_logic := '0';
-	signal H_BL   : std_logic := '0';
-	signal V_BLn  : std_logic := '0';
-	signal V_BL2n : std_logic := '0';
-
-begin
----------   H_COUNT   ----------------------------------------   
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if (H_CNT = 255) then
-				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
-			else
-				H_CNT <= H_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_H_CNT  <= H_CNT;
-
----------   H_SYNC     ----------------------------------------
-	H_CLK <= H_CNT(4);
-	process(H_CLK, H_CNT(8))
-	begin
-		if (H_CNT(8) = '0') then
-			H_SYNC <= '0';
-		elsif rising_edge(H_CLK) then
-			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
-		end if;
-	end process;
-
-	O_H_SYNC <= H_SYNC;
-
----------   H_BL     ------------------------------------------
-
-	process(I_CLK)
-	begin
-		if rising_edge(I_CLK) then
-			if H_CNT = 387 then
-				H_BL <= '1';
-			elsif H_CNT = 503 then
-				H_BL <= '0';
-			end if;
-		end if;
-	end process;
-
-	O_H_BL <= H_BL;
-
----------   V_COUNT   ----------------------------------------   
-	process(H_SYNC, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			V_CNT <= (others => '0');
-		elsif rising_edge(H_SYNC) then
-			if (V_CNT = 255) then
-				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
-			else
-				V_CNT <= V_CNT + 1 ;
-			end if;
-		end if;
-	end process;
-
-	O_V_CNT  <= V_CNT(7 downto 0);
-	O_V_SYNC <= V_CNT(8);
-
----------   V_BLn    ------------------------------------------
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BLn <= '0';
-			elsif V_CNT(7 downto 0) = 15 then
-				V_BLn <= '1';
-			end if;
-		end if;
-	end process;
-
-	process(H_SYNC)
-	begin
-		if rising_edge(H_SYNC) then
-			if V_CNT(7 downto 0) = 239 then
-				V_BL2n <= '0';
-			elsif V_CNT(7 downto 0) = 16 then
-				V_BL2n <= '1';
-			end if;
-		end if;
-	end process;
-
-	O_V_BLn  <= V_BLn;
-	O_V_BL2n <= V_BL2n;
--------   C_BLn     ------------------------------------------
-	O_C_BLn  <= V_BLn and (not H_CNT(8));
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_inport.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_inport.vhd
deleted file mode 100644
index 25250c11..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_inport.vhd	
+++ /dev/null
@@ -1,85 +0,0 @@
------------------------------------------------------------------------
--- FPGA MOONCRESTA INPORT
---
--- Version : 1.01
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004-4-30  galaxian modify by K.DEGAWA
------------------------------------------------------------------------
-
---    DIP SW        0     1     2     3     4     5
------------------------------------------------------------------
---  COIN CHUTE
--- 1 COIN/1 PLAY   1'b0  1'b0
--- 2 COIN/1 PLAY   1'b1  1'b0
--- 1 COIN/2 PLAY   1'b0  1'b1
--- FREE PLAY       1'b1  1'b1
---   BOUNS
---                             1'b0  1'b0
---                             1'b1  1'b0
---                             1'b0  1'b1
---                             1'b1  1'b1
---   LIVES
---     2                                   1'b0
---     3                                   1'b1
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_INPORT is
-port (
-	I_COIN1    : in  std_logic;   --  active high
-	I_COIN2    : in  std_logic;   --  active high
-	I_1P_LE    : in  std_logic;   --  active high
-	I_1P_RI    : in  std_logic;   --  active high
-	I_1P_SH    : in  std_logic;   --  active high
-	I_1P_UP    : in  std_logic;   --  active high
-	I_1P_DW    : in  std_logic;   --  active high
-	
-	I_2P_LE    : in  std_logic;
-	I_2P_RI    : in  std_logic;
-	I_2P_SH    : in  std_logic;
-	I_2P_UP    : in  std_logic;   --  active high
-	I_2P_DW    : in  std_logic;   --  active high
-	I_1P_START : in  std_logic;   --  active high
-	I_2P_START : in  std_logic;   --  active high
-	I_SW0_OE   : in  std_logic;
-	I_SW1_OE   : in  std_logic;
-	I_DIP_OE   : in  std_logic;
-	O_D        : out std_logic_vector(7 downto 0)
-);
-
-end;
-
-architecture RTL of MC_INPORT is
-
-	constant W_TABLE   : std_logic := '0';  -- UP = 0;
-	constant W_TEST    : std_logic := '0';
-	constant W_SERVICE : std_logic := '0';
-
-	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-
-	W_SW0_DO <= x"00" when I_SW0_OE = '0' else I_1P_UP & I_1P_DW & W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_1P_UP & I_COIN1;
-	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "01"              & I_2P_DW &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
-	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
-	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-	
---	W_SW0_DO <= x"00" when I_SW0_OE = '0' else W_SERVICE & W_TEST &  W_TABLE &  I_1P_SH &  I_1P_RI & I_1P_LE & I_COIN2    & I_COIN1;
---	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "010"                         &  I_2P_SH &  I_2P_RI & I_2P_LE & I_2P_START & I_1P_START;
---	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00001010";
---	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
-
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_ld_pls.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_ld_pls.vhd
deleted file mode 100644
index 0945fe35..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_ld_pls.vhd	
+++ /dev/null
@@ -1,115 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
--------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_LD_PLS is
-	port (
-		I_CLK_6M     : in  std_logic;
-		I_H_CNT      : in  std_logic_vector(8 downto 0);
-		I_3D_DI      : in  std_logic;
-
-		O_LDn        : out std_logic;
-		O_CNTRLDn    : out std_logic;
-		O_CNTRCLRn   : out std_logic;
-		O_COLLn      : out std_logic;
-		O_VPLn       : out std_logic;
-		O_OBJDATALn  : out std_logic;
-		O_MLDn       : out std_logic;
-		O_SLDn       : out std_logic
-	);
-end;
-
-architecture RTL of MC_LD_PLS is
-	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4C1_Q3 : std_logic := '0';
-	signal W_4C2_B  : std_logic := '0';
-	signal W_4D1_G  : std_logic := '0';
-	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_5C_Q   : std_logic := '0';
-	signal W_HCNT   : std_logic := '0';
-begin
-	O_LDn       <= W_4D1_G;
-	O_CNTRLDn   <= W_4D1_Q(2);
-	O_CNTRCLRn  <= W_4D1_Q(0);
-	O_COLLn     <= W_4D2_Q(2);
-	O_VPLn      <= W_4D2_Q(0);
-	O_OBJDATALn <= W_4C1_Q(2);
-	O_MLDn      <= W_4C2_Q(0);
-	O_SLDn      <= W_4C2_Q(1);
-	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
-	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
-	--    Parts 4D
-	u_4d1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_G,
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      =>W_4D1_Q
-	);
-
-	u_4d2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_5C_Q,
-		I_Sel(1) => I_H_CNT(2),
-		I_Sel(0) => I_H_CNT(1),
-		O_Q      => W_4D2_Q
-	);
-
-	--    Parts 4C
-	u_4c1 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D2_Q(1),
-		I_Sel(1) => I_H_CNT(8),
-		I_Sel(0) => I_H_CNT(3),
-		O_Q      => W_4C1_Q
-	);
-
-	u_4c2 : entity work.LOGIC_74XX139
-	port map(
-		I_G      => W_4D1_Q(3),
-		I_Sel(1) => W_4C2_B,
-		I_Sel(0) => W_HCNT,
-		O_Q      => W_4C2_Q
-	);
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_5C_Q <= I_H_CNT(0);
-		end if;
-	end process;
-
-	-- 2004-9-22 added
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			W_4C1_Q3 <= W_4C1_Q(3);
-		end if;
-	end process;
-
-	process(W_4C1_Q3)
-	begin
-		if rising_edge(W_4C1_Q3) then
-			W_4C2_B <= I_3D_DI;
-		end if;
-	end process;
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_logic.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_logic.vhd
deleted file mode 100644
index 5dae8a87..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_logic.vhd	
+++ /dev/null
@@ -1,92 +0,0 @@
--------------------------------------------------------------------------------
--- FPGA MOONCRESTA    LOGIC IP MODULE
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
--------------------------------------------------------------------------------
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx138
--- 3-to-8 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX138 is
-	port (
-		I_G1  : in  std_logic;
-		I_G2a : in  std_logic;
-		I_G2b : in  std_logic;
-		I_Sel : in  std_logic_vector(2 downto 0);
-		O_Q   : out std_logic_vector(7 downto 0)
-	);
-end logic_74xx138;
-
-architecture RTL of LOGIC_74XX138 is
-	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
-
-begin
-	I_G <= I_G1 & I_G2a & I_G2b;
-
-	xx138 : process(I_G, I_Sel)
-	begin
-		if(I_G = "100" ) then
-			case I_Sel is
-				when "000" => O_Q <= "11111110";
-				when "001" => O_Q <= "11111101";
-				when "010" => O_Q <= "11111011";
-				when "011" => O_Q <= "11110111";
-				when "100" => O_Q <= "11101111";
-				when "101" => O_Q <= "11011111";
-				when "110" => O_Q <= "10111111";
-				when "111" => O_Q <= "01111111";
-				when others => null;
-			end case;
-		 else
-				O_Q <= (others => '1');
-		 end if;
-	end process;
-end RTL;
-
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
--------------------------------------------------------------------------------
--- 74xx139
--- 2-to-4 line decoder
--------------------------------------------------------------------------------
-entity LOGIC_74XX139 is
-	port (
-		I_G   : in  std_logic;
-		I_Sel : in  std_logic_vector(1 downto 0);
-		O_Q   : out std_logic_vector(3 downto 0)
-	);
-end;
-
-architecture RTL of LOGIC_74XX139 is
-begin
-	xx139 : process (I_G, I_Sel)
-	begin
-		if I_G = '0' then
-			case I_Sel is
-				when "00" => O_Q <= "1110";
-				when "01" => O_Q <= "1101";
-				when "10" => O_Q <= "1011";
-				when "11" => O_Q <= "0111";
-				when others => null;
-			end case;
-		else
-			O_Q <= "1111";
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_missile.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_missile.vhd
deleted file mode 100644
index c5aa6633..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_missile.vhd	
+++ /dev/null
@@ -1,107 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA VIDEO-MISSILE
-----
----- Version : 2.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 9-22 The problem which missile didn't sometimes come out from was improved.
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_MISSILE is
-	port(
-		I_CLK_6M    : in std_logic;
-		I_CLK_18M   : in std_logic;
-		I_C_BLn_X   : in std_logic;
-		I_MLDn      : in std_logic;
-		I_SLDn      : in std_logic;
-		I_HPOS      : in std_logic_vector (7 downto 0);
-
-		O_MISSILEn  : out std_logic;
-		O_SHELLn    : out std_logic
-	);
-end;
-
-architecture RTL of MC_MISSILE is
-	signal W_45R_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_45S_Q   : std_logic_vector (7 downto 0) := (others => '0');
-	signal W_5P1_Q   : std_logic := '0';
-	signal W_5P2_Q   : std_logic := '0';
-	signal W_5P1_CLK : std_logic := '0';
-	signal W_5P2_CLK : std_logic := '0';
-begin
-
-	O_MISSILEn <= W_5P1_CLK;
-	O_SHELLn   <= W_5P2_CLK;
-
-	-- missile counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if (I_MLDn = '0') then
-				W_45R_Q <= I_HPOS;
-			else
-				if (I_C_BLn_X = '1') then
-					W_45R_Q <= W_45R_Q + 1;
-					if (W_45R_Q(7 downto 2) = "111111") and W_5P1_Q = '1' then
-						W_5P1_CLK <= '0';
-					else
-						W_5P1_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- shell counter
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			if(I_SLDn = '0') then
-				W_45S_Q <= I_HPOS;
-			else
-				if(I_C_BLn_X = '1') then
-					W_45S_Q <= W_45S_Q + 1;
-					if (W_45S_Q(7 downto 2) = "111111") and W_5P2_Q = '1' then
-						W_5P2_CLK <= '0';
-					else
-						W_5P2_CLK <= '1';
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_MLDn) and clock active on rising edge (W_5P1_CLK)
-	process(W_5P1_CLK, I_MLDn)
-	begin
-		if (I_MLDn = '0') then
-			W_5P1_Q <= '1';
-		elsif rising_edge(W_5P1_CLK) then
-			W_5P1_Q <= '0';
-		end if;
-	end process;
-
-	-- Standard D-type flip-flop with D input tied low, async active
-	-- low preset (I_SLDn) and clock active on rising edge (W_5P2_CLK)
-	process(W_5P2_CLK, I_SLDn)
-	begin
-		if (I_SLDn = '0') then
-			W_5P2_Q <= '1';
-		elsif rising_edge(W_5P2_CLK) then
-			W_5P2_Q <= '0';
-		end if;
-	end process;
-
-end RTL;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_a.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_a.vhd
deleted file mode 100644
index ee0c66be..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_a.vhd	
+++ /dev/null
@@ -1,117 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA SOUND I/F
---
--- Version : 1.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-	use IEEE.std_logic_arith.all;
-
-entity MC_SOUND_A is
-port (
-	I_CLK_12M  : in   std_logic;
-	I_CLK_6M   : in   std_logic;
-	I_H_CNT1   : in   std_logic;
-	I_BD       : in   std_logic_vector(7 downto 0);
-	I_PITCH    : in   std_logic;
-	I_VOL1     : in   std_logic;
-	I_VOL2     : in   std_logic;
-
-	O_SDAT     : out  std_logic_vector(7 downto 0);
-	O_DO       : out  std_logic_vector(3 downto 0)
-);
-end;
-
-architecture RTL of MC_SOUND_A is
-	signal W_PITCH     : std_logic := '0';
-	signal W_89K_LDn   : std_logic := '0';
-	signal W_89K_Q     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_89K_LDATA : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_6T_Q      : std_logic_vector(3 downto 0) := (others => '0');
-	signal W_SDAT0     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT2     : std_logic_vector(7 downto 0) := (others => '0');
-	signal W_SDAT3     : std_logic_vector(7 downto 0) := (others => '0');
-
-begin
-	O_DO <= W_6T_Q;
-
-	process (I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M)  then
-			W_PITCH  <= I_PITCH;
-			if (W_89K_Q = x"ff") then
-				W_89K_LDn <= '0' ;
-			else
-				W_89K_LDn <= '1' ;
-			end if;
-		end if;
-	end process;
-
-	-- Parts 9J
-	process (W_PITCH)
-	begin
-		if falling_edge(W_PITCH) then
-			W_89K_LDATA <= I_BD;
-		end if;
-	end process;
-
-	process (I_H_CNT1)
-	begin
-		if rising_edge(I_H_CNT1) then
-			if (W_89K_LDn = '0') then
-				W_89K_Q <= W_89K_LDATA;
-			else
-				W_89K_Q <= W_89K_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	process (W_89K_LDn)
-	begin
-		if falling_edge(W_89K_LDn) then
-			W_6T_Q <= W_6T_Q + 1;
-		end if;
-	end process;
-
-	process (I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			O_SDAT <= (x"14" + W_SDAT3) + (W_SDAT0 + W_SDAT2);
-
-			if W_6T_Q(0)='1' then
-				W_SDAT0 <= x"2a";
-			else
-				W_SDAT0 <= (others => '0');
-			end if;
-
-			if W_6T_Q(2)='1' then
-				if I_VOL1 = '1' then
-					W_SDAT2 <= x"69";
-				else
-					W_SDAT2 <= x"39";
-				end if;
-			else
-				W_SDAT2 <= (others => '0');
-			end if;
-
-			if (W_6T_Q(3)='1') and (I_VOL2 = '1') then
-				W_SDAT3 <= x"48" ;
-			else
-				W_SDAT3 <= (others => '0');
-			end if;
-
-		end if;
-	end process;
-
-end;
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_b.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_b.vhd
deleted file mode 100644
index b74e4bb1..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_b.vhd	
+++ /dev/null
@@ -1,253 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA MOONCRESTA WAVE SOUND
-----
----- Version : 1.00
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does no guarantee this program.
----- You can use this at your own risk.
-----
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
---pragma translate_off
---	use ieee.std_logic_textio.all;
---	use std.textio.all;
---pragma translate_on
-
-entity MC_SOUND_B is
-	port(
-		I_CLK1    : in  std_logic;   --  6MHz
-		I_RSTn    : in  std_logic;
-		I_SW      : in  std_logic_vector( 2 downto 0);
-		I_DAC     : in  std_logic_vector( 3 downto 0);
-		I_FS      : in  std_logic_vector( 2 downto 0);
-		O_SDAT    : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_B is
-constant sample_time : integer := 557;    -- sample time : 557 = 11025Hz, 557/2 = 22050Hz
-constant fire_cnt    : std_logic_vector(15 downto 0) := x"2000";
-constant hit_cnt     : std_logic_vector(15 downto 0) := x"2000";
-
-signal sample     : std_logic_vector(10 downto 0) := (others => '0');
-signal sample_pls : std_logic := '0';
-signal s0_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s0_trg     : std_logic := '0';
-signal s1_trg_ff  : std_logic_vector( 1 downto 0) := (others => '0');
-signal s1_trg     : std_logic := '0';
-signal fire_addr  : std_logic_vector(15 downto 0) := (others => '0');
-signal hit_addr   : std_logic_vector(15 downto 0) := (others => '0');
-
-signal WAV_D0     : std_logic_vector( 7 downto 0) := (others => '0');
-signal WAV_D1     : std_logic_vector( 7 downto 0) := (others => '0');
-
-signal W_VCO1_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_STEP: std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO1_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO2_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal W_VCO3_OUT : std_logic_vector( 7 downto 0) := (others => '0');
-signal VCO_CTR    : std_logic_vector(24 downto 0) := (others => '0');
-
-signal SDAT      : std_logic_vector(10 downto 0) := (others => '0');
-
-begin
-	-- ideally we should divide by 5 because this is the sum of 5 channels
-	-- but in practice we divide by 4 and just clip sounds that are too loud.
-	O_SDAT <= SDAT(9 downto 2) when SDAT(10) = '0' else (others=>'1'); -- clip overrange sounds
-
-	process(I_CLK1)
-	begin
-		if rising_edge(I_CLK1) then
-			SDAT <=  ("000" & W_VCO3_OUT) + ( ( ("000" & W_VCO2_OUT) + ("000" & W_VCO1_OUT) ) + ( ("000" & WAV_D0) + ("000" & WAV_D1) ) );
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			sample     <= (others => '0');
-			sample_pls <= '0';
-		elsif rising_edge(I_CLK1) then
-			if (sample = sample_time - 1) then
-				sample     <= (others => '0');
-				sample_pls <= '1';
-			else
-				sample     <= sample + 1;
-				sample_pls <= '0';
-			end if;
-		end if;
-	end process;
-
--------------  FIRE SOUND ------------------------------------------
-	mc_roms_fire : entity work.GAL_FIR
-	port map (
-		CLK  => I_CLK1,
-		ADDR => fire_addr(12 downto 0),
-		DATA => WAV_D0
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s0_trg_ff    <= (others => '0');
-			s0_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s0_trg_ff(0) <= I_SW(0);
-			s0_trg_ff(1) <= s0_trg_ff(0);
-			s0_trg       <= not s0_trg_ff(1) and s0_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			fire_addr <= fire_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s0_trg = '1') then
-				fire_addr <= (others => '0');
-			else
-				if(sample_pls = '1') then
-					if(fire_addr <= fire_cnt) then
-						fire_addr <= fire_addr + 1;
-					else
-						fire_addr <= fire_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
--------------  HIT SOUND ------------------------------------------
-	mc_roms_hit : entity work.GAL_HIT
-	port map (
-		CLK  => I_CLK1,
-		ADDR => hit_addr(12 downto 0),
-		DATA => WAV_D1
-	);
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			s1_trg_ff    <= (others => '0');
-			s1_trg       <= '0';
-		elsif rising_edge(I_CLK1) then
-			s1_trg_ff(0) <= I_SW(1);
-			s1_trg_ff(1) <= s1_trg_ff(0);
-			s1_trg       <= not s1_trg_ff(1) and s1_trg_ff(0);
-		end if;
-	end process;
-
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-			hit_addr <= hit_cnt;
-		elsif rising_edge(I_CLK1) then
-			if (s1_trg = '1') then
-				hit_addr <= (others => '0');
-			else
-				if (sample_pls = '1') then
-					if (hit_addr <= hit_cnt) then
-						hit_addr <= hit_addr + 1 ;
-					else
-						hit_addr <= hit_addr ;
-					end if;
-				end if;
-			end if;
-		end if;
-	end process;
-
----------------  EFFECT SOUND ---------------------------------------
-
---	9R modulator voltage generator based on DAC value
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK1) then
-			VCO_CTR <= VCO_CTR + (not I_DAC);
-		end if;
-	end process;
-
-	-- modulator frequency lookup tables for the three VCOs
-	process(I_CLK1, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		elsif rising_edge(I_CLK1) then
-			case VCO_CTR(23 downto 19) is
-				when "00000" => W_VCO1_STEP <= x"2A"; W_VCO2_STEP <= x"3A"; W_VCO3_STEP <= x"54";
-				when "00001" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"39"; W_VCO3_STEP <= x"53"; 
-				when "00010" => W_VCO1_STEP <= x"29"; W_VCO2_STEP <= x"38"; W_VCO3_STEP <= x"52";
-				when "00011" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"50";
-				when "00100" => W_VCO1_STEP <= x"28"; W_VCO2_STEP <= x"37"; W_VCO3_STEP <= x"4F";
-				when "00101" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"36"; W_VCO3_STEP <= x"4E";
-				when "00110" => W_VCO1_STEP <= x"27"; W_VCO2_STEP <= x"35"; W_VCO3_STEP <= x"4D";
-				when "00111" => W_VCO1_STEP <= x"26"; W_VCO2_STEP <= x"34"; W_VCO3_STEP <= x"4C";
-				when "01000" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"4A";
-				when "01001" => W_VCO1_STEP <= x"25"; W_VCO2_STEP <= x"33"; W_VCO3_STEP <= x"49";
-				when "01010" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"32"; W_VCO3_STEP <= x"48";
-				when "01011" => W_VCO1_STEP <= x"24"; W_VCO2_STEP <= x"31"; W_VCO3_STEP <= x"47";
-				when "01100" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"30"; W_VCO3_STEP <= x"46";
-				when "01101" => W_VCO1_STEP <= x"23"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"44";
-				when "01110" => W_VCO1_STEP <= x"22"; W_VCO2_STEP <= x"2F"; W_VCO3_STEP <= x"43";
-				when "01111" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2E"; W_VCO3_STEP <= x"42";
-				when "10000" => W_VCO1_STEP <= x"21"; W_VCO2_STEP <= x"2D"; W_VCO3_STEP <= x"41";
-				when "10001" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2C"; W_VCO3_STEP <= x"40"; 
-				when "10010" => W_VCO1_STEP <= x"20"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3F";
-				when "10011" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2B"; W_VCO3_STEP <= x"3D";
-				when "10100" => W_VCO1_STEP <= x"1F"; W_VCO2_STEP <= x"2A"; W_VCO3_STEP <= x"3C";
-				when "10101" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"29"; W_VCO3_STEP <= x"3B";
-				when "10110" => W_VCO1_STEP <= x"1E"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"3A";
-				when "10111" => W_VCO1_STEP <= x"1D"; W_VCO2_STEP <= x"28"; W_VCO3_STEP <= x"39";
-				when "11000" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"27"; W_VCO3_STEP <= x"37";
-				when "11001" => W_VCO1_STEP <= x"1C"; W_VCO2_STEP <= x"26"; W_VCO3_STEP <= x"36";
-				when "11010" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"25"; W_VCO3_STEP <= x"35";
-				when "11011" => W_VCO1_STEP <= x"1B"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"34";
-				when "11100" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"24"; W_VCO3_STEP <= x"33";
-				when "11101" => W_VCO1_STEP <= x"1A"; W_VCO2_STEP <= x"23"; W_VCO3_STEP <= x"32";
-				when "11110" => W_VCO1_STEP <= x"19"; W_VCO2_STEP <= x"22"; W_VCO3_STEP <= x"30";
-				when "11111" => W_VCO1_STEP <= x"18"; W_VCO2_STEP <= x"21"; W_VCO3_STEP <= x"2F";
-				when others => null;
-			end case;
-		end if;     
-	end process;
-
---	8R VCO 240Hz - 140Hz (8)
-	mc_vco1 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(0),
-		I_STEP  => W_VCO1_STEP,
-		O_WAV   => W_VCO1_OUT
-	);
-
---	8S VCO 330Hz - 190Hz (11)
-	mc_vco2 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(1),
-		I_STEP  => W_VCO2_STEP,
-		O_WAV   => W_VCO2_OUT
-	);
-
---	8T VCO 480Hz - 270Hz (16)
-	mc_vco3 : entity work.MC_SOUND_VCO
-	port map (
-		I_CLK   => I_CLK1,
-		I_RSTn  => I_RSTn,
-		I_FS    => I_FS(2),
-		I_STEP  => W_VCO3_STEP,
-		O_WAV   => W_VCO3_OUT
-	);
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_vco.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_vco.vhd
deleted file mode 100644
index e2a63e85..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_sound_vco.vhd	
+++ /dev/null
@@ -1,49 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA VCO
---------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-use work.sine_package.all;
-
--- O_CLK = (I_CLK / 2^20) * I_STEP
-entity MC_SOUND_VCO is
-	port(
-		I_CLK     : in  std_logic;
-		I_RSTn    : in  std_logic;
-		I_FS      : in  std_logic;
-		I_STEP    : in  std_logic_vector( 7 downto 0);
-		O_WAV     : out std_logic_vector( 7 downto 0)
-	);
-end;
-
-architecture RTL of MC_SOUND_VCO is
-	signal VCO1_CTR   : std_logic_vector(19 downto 0) := (others => '0');
-	signal sine 		: std_logic_vector(14 downto 0) := (others => '0');
-
-begin
-	O_WAV <= sine(14 downto 7);
-	process(I_CLK, I_RSTn)
-	begin
-		if (I_RSTn = '0') then
-		  VCO1_CTR <= (others=>'0');
-		elsif rising_edge(I_CLK) then
-			if I_FS = '1' then
-				VCO1_CTR <= VCO1_CTR + I_STEP;
-				case VCO1_CTR(19 downto 18) is
-					when "00" => 
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "01" =>
-						sine <= "100000000000000" + std_logic_vector( to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when "10" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value(     VCO1_CTR(17 downto 11)), 15));
-					when "11" =>
-						sine <= "100000000000000" + std_logic_vector(-to_signed(get_table_value( not VCO1_CTR(17 downto 11)), 15));
-					when others => null;
-				end case;
-			end if;
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_stars.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_stars.vhd
deleted file mode 100644
index b91197b3..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_stars.vhd	
+++ /dev/null
@@ -1,90 +0,0 @@
-------------------------------------------------------------------------------
--- FPGA MOONCRESTA STARS
---
--- Version : 2.00
---
--- Copyright(c) 2004 Katsumi Degawa , All rights reserved
---
--- Important !
---
--- This program is freeware for non-commercial use.
--- The author does not guarantee this program.
--- You can use this at your own risk.
---
-------------------------------------------------------------------------------
-library ieee;
-	use ieee.std_logic_1164.all;
-	use ieee.numeric_std.all;
-
-entity MC_STARS is
-	port (
-		I_CLK_18M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_FLIP      : in  std_logic;
-		I_V_SYNC      : in  std_logic;
-		I_8HF         : in  std_logic;
-		I_256HnX      : in  std_logic;
-		I_1VF         : in  std_logic;
-		I_2V          : in  std_logic;
-		I_STARS_ON    : in  std_logic;
-		I_STARS_OFFn  : in  std_logic;
-
-		O_R           : out std_logic_vector(1 downto 0);
-		O_G           : out std_logic_vector(1 downto 0);
-		O_B           : out std_logic_vector(1 downto 0);
-		O_NOISE       : out std_logic
-	);
-end;
-
-architecture RTL of MC_STARS is
-	signal CLK_1C           : std_logic := '0';
-	signal W_2D_Qn          : std_logic := '0';
-	
-	signal W_3B             : std_logic := '0';
-	signal noise            : std_logic := '0';
-	signal W_2A             : std_logic := '0';
-	signal W_4P             : std_logic := '0';
-	signal CLK_1AB          : std_logic := '0';
-	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
-	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
-begin
-	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
-
-	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
-	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
-	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
-
-	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
-	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
-
-	O_NOISE   <= noise ;
-
-	process(I_2V)
-	begin
-		if rising_edge(I_2V) then
-			noise <= W_2D_Qn;
-		end if;
-	end process;
-
-	process(CLK_1C, I_V_SYNC)
-	begin
-		if(I_V_SYNC = '1') then
-			W_1C_Q <= (others => '0');
-		elsif rising_edge(CLK_1C) then
-			W_1C_Q <= W_1C_Q(0) & '1';
-		end if;
-	end process;
-
-	process(CLK_1AB, I_STARS_ON)
-	begin
-		if(I_STARS_ON = '0') then
-			W_1AB_Q <= (others => '0');
-			W_2D_Qn <= '1';
-		elsif rising_edge(CLK_1AB) then
-			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
-			W_2D_Qn <= not W_1AB_Q(15);
-		end if;
-	end process;
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_video.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_video.vhd
deleted file mode 100644
index 9642043d..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mc_video.vhd	
+++ /dev/null
@@ -1,436 +0,0 @@
---------------------------------------------------------------------------------
----- FPGA GALAXIAN  VIDEO
-----
----- Version : 2.50
-----
----- Copyright(c) 2004 Katsumi Degawa , All rights reserved
-----
----- Important !
-----
----- This program is freeware for non-commercial use. 
----- The author does not guarantee this program.
----- You can use this at your own risk.
-----
----- 2004- 4-30  galaxian modify by K.DEGAWA
----- 2004- 5- 6  first release.
----- 2004- 8-23  Improvement with T80-IP.
----- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
---------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------
--- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
---    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
--------------------------------------------------------------------------------------------
--- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
---    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
--------------------------------------------------------------------------------------------
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-entity MC_VIDEO is
-	port(
-		I_CLK_18M     : in  std_logic;
-		I_CLK_12M     : in  std_logic;
-		I_CLK_6M      : in  std_logic;
-		I_H_CNT       : in  std_logic_vector(8 downto 0);
-		I_V_CNT       : in  std_logic_vector(7 downto 0);
-		I_H_FLIP      : in  std_logic;
-		I_V_FLIP      : in  std_logic;
-		I_V_BLn       : in  std_logic;
-		I_C_BLn       : in  std_logic;
-
-		I_A           : in  std_logic_vector(9 downto 0);
-		I_BD          : in  std_logic_vector(7 downto 0);
-		I_OBJ_SUB_A   : in  std_logic_vector(2 downto 0);
-		I_OBJ_RAM_RQ  : in  std_logic;
-		I_OBJ_RAM_RD  : in  std_logic;
-		I_OBJ_RAM_WR  : in  std_logic;
-		I_VID_RAM_RD  : in  std_logic;
-		I_VID_RAM_WR  : in  std_logic;
-		I_DRIVER_WR   : in  std_logic;
-
-
-		O_C_BLnX      : out std_logic;
-		O_8HF         : out std_logic;
-		O_256HnX      : out std_logic;
-		O_1VF         : out std_logic;
-		O_MISSILEn    : out std_logic;
-		O_SHELLn      : out std_logic;
-
-		O_BD          : out std_logic_vector(7 downto 0);
-		O_VID         : out std_logic_vector(1 downto 0);
-		O_COL         : out std_logic_vector(2 downto 0)
-	);
-end;
-
-architecture RTL of MC_VIDEO is
-
-	signal WB_LDn       : std_logic := '0';
-	signal WB_CNTRLDn   : std_logic := '0';
-	signal WB_CNTRCLRn  : std_logic := '0';
-	signal WB_COLLn     : std_logic := '0';
-	signal WB_VPLn      : std_logic := '0';
-	signal WB_OBJDATALn : std_logic := '0';
-	signal WB_MLDn      : std_logic := '0';
-	signal WB_SLDn      : std_logic := '0';
-	signal W_3D         : std_logic := '0';
-	signal W_LDn        : std_logic := '0';
-	signal W_CNTRLDn    : std_logic := '0';
-	signal W_CNTRCLRn   : std_logic := '0';
-	signal W_COLLn      : std_logic := '0';
-	signal W_VPLn       : std_logic := '0';
-	signal W_OBJDATALn  : std_logic := '0';
-	signal W_MLDn       : std_logic := '0';
-	signal W_SLDn       : std_logic := '0';
-	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
-	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
-
-	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
-	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
-	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
-	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
-	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
-	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
-	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
---	signal W_OBJ_RAM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
-	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
-	signal W_256HnX       : std_logic := '0';
-	signal W_2N           : std_logic := '0';
-	signal W_45T_CLR      : std_logic := '0';
-	signal W_C_BLnX       : std_logic := '0';
-	signal W_H_FLIP1      : std_logic := '0';
-	signal W_H_FLIP2      : std_logic := '0';
-	signal W_H_FLIP1X     : std_logic := '0';
-	signal W_H_FLIP2X     : std_logic := '0';
-	signal W_LRAM_AND     : std_logic := '0';
-	signal W_RAW0         : std_logic := '0';
-	signal W_RAW1         : std_logic := '0';
-	signal W_RAW_OR       : std_logic := '0';
-	signal W_SRCLK        : std_logic := '0';
-	signal W_SRLD         : std_logic := '0';
-	signal W_VID_RAM_CS   : std_logic := '0';
-	signal W_CLK_6Mn      : std_logic := '0';
-
-begin
-
-	ld_pls : entity work.MC_LD_PLS
-	port map(
-		I_CLK_6M    => I_CLK_6M,
-		I_H_CNT     => I_H_CNT,
-		I_3D_DI     => W_3D,
-
-		O_LDn       => WB_LDn,
-		O_CNTRLDn   => WB_CNTRLDn,
-		O_CNTRCLRn  => WB_CNTRCLRn,
-		O_COLLn     => WB_COLLn,
-		O_VPLn      => WB_VPLn,
-		O_OBJDATALn => WB_OBJDATALn,
-		O_MLDn      => WB_MLDn,
-		O_SLDn      => WB_SLDn
-	);
-
-	obj_ram : entity work.MC_OBJ_RAM 
-	port map(
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(7 downto 0),
-		I_WEA   => I_OBJ_RAM_WR,
-		I_CEA   => I_OBJ_RAM_RQ,
-		I_DA    => I_BD,
-		O_DA    => W_OBJ_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_OBJ_RAM_AB,
-		I_WEB   => '0',
-		I_CEB   => '1',
-		I_DB    => x"00",
-		O_DB    => W_OBJ_RAM_DOB
-	);
-
-	lram : entity work.MC_LRAM
-	port map(
-		I_CLK  => I_CLK_18M,
-		I_ADDR => W_LRAM_A,
-		I_WE   => W_CLK_6Mn,
-		I_D    => W_LRAM_DI,
-		O_Dn   => W_LRAM_DO
-	);
-
-	missile : entity work.MC_MISSILE
-	port map(
-		I_CLK_18M  => I_CLK_18M,
-		I_CLK_6M   => I_CLK_6M,
-		I_C_BLn_X  => W_C_BLnX,
-		I_MLDn     => W_MLDn,
-		I_SLDn     => W_SLDn,
-		I_HPOS     => W_H_POSI,
-		O_MISSILEn => O_MISSILEn,
-		O_SHELLn   => O_SHELLn
-	);
-
-	vid_ram : entity work.MC_VID_RAM
-	port map (
-		I_CLKA  => I_CLK_12M,
-		I_ADDRA => I_A(9 downto 0),
-		I_DA    => W_VID_RAM_DI,
-		I_WEA   => I_VID_RAM_WR,
-		I_CEA   => W_VID_RAM_CS,
-		O_DA    => W_VID_RAM_DOA,
-
-		I_CLKB  => I_CLK_12M,
-		I_ADDRB => W_VID_RAM_A(9 downto 0),
-		I_DB    => x"00",
-		I_WEB   => '0',
-		I_CEB   => '1',
-		O_DB    => W_VID_RAM_DOB
-	);
-
-	-- 1H VID-Rom
-	k_rom : entity work.GALAXIAN_1H 
-	port map (
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1H_D
-	);
-
-	-- 1K VID-Rom
-	h_rom : entity work.GALAXIAN_1K
-	port map(
-		CLK  => I_CLK_12M,
-		ADDR => W_O_OBJ_ROM_A,
-		DATA => W_1K_D
-	);
-
-
------------------------------------------------------------------------------------
-
-	process(I_CLK_12M)
-	begin
-		if falling_edge(I_CLK_12M) then
-			W_LDn       <= WB_LDn;
-			W_CNTRLDn   <= WB_CNTRLDn;
-			W_CNTRCLRn  <= WB_CNTRCLRn;
-			W_COLLn     <= WB_COLLn;
-			W_VPLn      <= WB_VPLn;
-			W_OBJDATALn <= WB_OBJDATALn;
-			W_MLDn      <= WB_MLDn;
-			W_SLDn      <= WB_SLDn;
-		end if;
-	end process;
-
-	W_CLK_6Mn <= not I_CLK_6M;
-
-	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
-	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
-	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
-
-	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
-
-	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
-	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
-
-	O_8HF <= W_HF_CNT(3);
-	O_1VF <= W_VF_CNT(0);
-	W_H_FLIP2 <= W_6J_Q(3);
-
---   Parts  4F,5F
-	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
---	W_OBJ_RAM_A  <= W_OBJ_RAM_AB when I_OBJ_RAM_RQ = '0' else I_A(7 downto 0) ;
-
-	process(I_CLK_12M)
-	begin
-		if rising_edge(I_CLK_12M) then
-			W_H_POSI <= W_OBJ_RAM_DOB;
-		end if;
-	end process;
-
-	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
-
---   Parts  4L
-	process(W_OBJDATALn)
-	begin
-		if rising_edge(W_OBJDATALn) then
-			W_OBJ_D <= W_H_POSI; 
-		end if;
-	end process;
-
---   Parts  4,5N
-	W_45N_Q <= W_VF_CNT + W_H_POSI;
-	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
-
-	process(W_VPLn, I_V_BLn)
-	begin
-		if (I_V_BLn = '0') then
-			W_2M_Q <= (others => '0');
-		elsif rising_edge(W_VPLn) then
-			W_2M_Q <= W_45N_Q;
-		end if;
-	end process;
-	
-	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
-	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
-	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
-	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
-	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
-	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
-	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
-	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
-
-----  VIDEO DATA OUTPUT  --------------
-
-	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
-	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
-	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
-	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
-	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
-
------------------------------------------------------------------------------------
-
-	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
-	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
-	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
-	C_2HJ   <= W_3L_Y(1 downto 0);
-	C_2KL   <= W_3L_Y(1 downto 0);
-	W_RAW0  <= W_3L_Y(2);
-	W_RAW1  <= W_3L_Y(3);
-	W_SRCLK <= I_CLK_6M;
-
---------  PARTS 2KL  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2KL) is
-				when "00" => reg_2KL <= reg_2KL;
-				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
-				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
-				when "11" => reg_2KL <= W_1K_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
---------  PARTS 2HJ  ---------------------------------------------- 
-
-	process(W_SRCLK)
-	begin
-		if rising_edge(W_SRCLK) then
-			case(C_2HJ) is
-				when "00" => reg_2HJ <= reg_2HJ;
-				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
-				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
-				when "11" => reg_2HJ <= W_1H_D;
-				when others => null;
-			end case;
-		end if;
-	end process;
-
--------  SHT2 -----------------------------------------------------
-
---  Parts 6K
-	process(W_COLLn)
-	begin
-		if rising_edge(W_COLLn) then
-			W_6K_Q <= W_H_POSI(2 downto 0);
-		end if;
-	end process;
-
---  Parts 6P
-	process(I_CLK_6M)
-	begin
-		if rising_edge(I_CLK_6M) then
-			if (W_LDn = '0') then
-				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
-			else
-				W_6P_Q <= W_6P_Q;
-			end if;
-		end if;
-	end process;
-
-	W_H_FLIP2X <= W_6P_Q(6);
-	W_H_FLIP1X <= W_6P_Q(5);
-	W_C_BLnX   <= W_6P_Q(4);
-	W_256HnX   <= W_6P_Q(3);
-	W_CD       <= W_6P_Q(2 downto 0);
-	O_256HnX   <= W_256HnX;
-	O_C_BLnX   <= W_C_BLnX;
-	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
-
-	process(I_CLK_6M, W_45T_CLR)
-	begin
-		if (W_45T_CLR = '0') then
-			W_45T_Q <= (others => '0');
-		elsif rising_edge(I_CLK_6M) then
-			if (W_CNTRLDn = '0') then
-				W_45T_Q <= W_H_POSI;
-			else
-				W_45T_Q <= W_45T_Q + 1;
-			end if;
-		end if;
-	end process;
-
-	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
-
-	process(I_CLK_6M)
-	begin
-		if falling_edge(I_CLK_6M) then
-			W_RV <= W_LRAM_DO(1 downto 0);
-			W_RC <= W_LRAM_DO(4 downto 2);
-		end if;
-	end process;
-
-	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
-	W_RAW_OR   <= W_RAW0 or W_RAW1 ;
-
-	W_VID(0) <= not (not (W_RAW0   and W_RV(1)) and W_RV(0));
-	W_VID(1) <= not (not (W_RAW1   and W_RV(0)) and W_RV(1));
-	W_COL(0) <= not (not (W_RAW_OR and W_CD(0)  and W_RC(1) and W_RC(2)) and W_RC(0));
-	W_COL(1) <= not (not (W_RAW_OR and W_CD(1)  and W_RC(2) and W_RC(0)) and W_RC(1));
-	W_COL(2) <= not (not (W_RAW_OR and W_CD(2)  and W_RC(0) and W_RC(1)) and W_RC(2));
-
-	O_VID <= W_VID;
-	O_COL <= W_COL;
-
-	W_LRAM_DI(0) <= W_LRAM_AND and W_VID(0);
-	W_LRAM_DI(1) <= W_LRAM_AND and W_VID(1); 
-	W_LRAM_DI(2) <= W_LRAM_AND and W_COL(0);
-	W_LRAM_DI(3) <= W_LRAM_AND and W_COL(1);
-	W_LRAM_DI(4) <= W_LRAM_AND and W_COL(2);
-
-end RTL;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mist_io.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mist_io.v
deleted file mode 100644
index 2f41221f..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/mist_io.v	
+++ /dev/null
@@ -1,530 +0,0 @@
-//
-// mist_io.v
-//
-// mist_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-// Copyright (c) 2015-2017 Sorgelig
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-///////////////////////////////////////////////////////////////////////
-
-//
-// Use buffer to access SD card. It's time-critical part.
-// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
-//                                                           (Sorgelig)
-//
-// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
-// clk_ps2 = clk_sys/(PS2DIV*2)
-//
-
-module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
-(
-
-	// parameter STRLEN and the actual length of conf_str have to match
-	input [(8*STRLEN)-1:0] conf_str,
-
-	// Global clock. It should be around 100MHz (higher is better).
-	input             clk_sys,
-
-	// Global SPI clock from ARM. 24MHz
-	input             SPI_SCK,
-
-	input             CONF_DATA0,
-	input             SPI_SS2,
-	output            SPI_DO,
-	input             SPI_DI,
-
-	output reg [7:0] joystick_0,
-	output reg [7:0] joystick_1,
-//	output reg [31:0] joystick_2,
-//	output reg [31:0] joystick_3,
-//	output reg [31:0] joystick_4,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output      [1:0] buttons,
-	output      [1:0] switches,
-	output            scandoublerD,
-	output            ypbpr,
-
-	output reg [31:0] status,
-
-	// SD config
-	input             sd_conf,
-	input             sd_sdhc,
-	output      [1:0] img_mounted, // signaling that new image has been mounted
-	output reg [31:0] img_size,    // size of image in bytes
-
-	// SD block level access
-	input      [31:0] sd_lba,
-	input       [1:0] sd_rd,
-	input       [1:0] sd_wr,
-	output reg        sd_ack,
-	output reg        sd_ack_conf,
-
-	// SD byte level access. Signals for 2-PORT altsyncram.
-	output reg  [8:0] sd_buff_addr,
-	output reg  [7:0] sd_buff_dout,
-	input       [7:0] sd_buff_din,
-	output reg        sd_buff_wr,
-
-	// ps2 keyboard emulation
-	output            ps2_kbd_clk,
-	output reg        ps2_kbd_data,
-	output            ps2_mouse_clk,
-	output reg        ps2_mouse_data,
-
-	// ps2 alternative interface. 
-
-	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
-	output reg [10:0] ps2_key = 0,
-
-	// [24] - toggles with every event
-	output reg [24:0] ps2_mouse = 0,
-
-	// ARM -> FPGA download
-	input             ioctl_ce,
-	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
-	output reg        ioctl_wr = 0,
-	output reg [24:0] ioctl_addr,
-	output reg  [7:0] ioctl_dout
-);
-
-reg [7:0] but_sw;
-reg [2:0] stick_idx;
-
-reg [1:0] mount_strobe = 0;
-assign img_mounted  = mount_strobe;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign scandoublerD = but_sw[4];
-assign ypbpr = but_sw[5];
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire       drive_sel = sd_rd[1] | sd_wr[1];
-wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
-
-reg [7:0] cmd;
-reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0] byte_cnt;   // counts bytes
-
-reg spi_do;
-assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
-
-reg [7:0] spi_data_out;
-
-// SPI transmitter
-always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
-
-reg [7:0] spi_data_in;
-reg       spi_data_ready = 0;
-
-// SPI receiver
-always@(posedge SPI_SCK or posedge CONF_DATA0) begin
-	reg [6:0]  sbuf;
-	reg [31:0] sd_lba_r;
-	reg        drive_sel_r;
-
-	if(CONF_DATA0) begin
-	   bit_cnt <= 0;
-	   byte_cnt <= 0;
-		spi_data_out <= core_type;
-	end
-	else
-	begin
-		bit_cnt <= bit_cnt + 1'd1;
-		sbuf <= {sbuf[5:0], SPI_DI};
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
-
-			spi_data_in <= {sbuf, SPI_DI};
-			spi_data_ready <= ~spi_data_ready;
-			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
-			
-			spi_data_out <= 0;
-			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
-				// reading config string
-				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
-
-				// reading sd card status
-				8'h16: if(byte_cnt == 0) begin
-							spi_data_out <= sd_cmd;
-							sd_lba_r <= sd_lba;
-							drive_sel_r <= drive_sel;
-						end else if (byte_cnt == 1) begin
-							spi_data_out <= drive_sel_r;
-						end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
-
-				// reading sd card write data
-				8'h18: spi_data_out <= sd_buff_din;
-			endcase
-		end
-	end
-end
-
-reg [31:0] ps2_key_raw = 0;
-wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
-wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
-
-// transfer to clk_sys domain
-always@(posedge clk_sys) begin
-	reg old_ss1, old_ss2;
-	reg old_ready1, old_ready2;
-	reg [2:0] b_wr;
-	reg       got_ps2 = 0;
-
-	old_ss1 <= CONF_DATA0;
-	old_ss2 <= old_ss1;
-	old_ready1 <= spi_data_ready;
-	old_ready2 <= old_ready1;
-	
-	sd_buff_wr <= b_wr[0];
-	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
-	b_wr <= (b_wr<<1);
-
-	if(old_ss2) begin
-		got_ps2      <= 0;
-		sd_ack       <= 0;
-		sd_ack_conf  <= 0;
-		sd_buff_addr <= 0;
-		if(got_ps2) begin
-			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
-			if(cmd == 5) begin
-				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
-				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
-				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
-				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
-			end
-		end
-	end
-	else
-	if(old_ready2 ^ old_ready1) begin
-
-		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
-
-		if(byte_cnt < 2) begin
-
-			if (cmd == 8'h19) sd_ack_conf  <= 1;
-			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
-			mount_strobe <= 0;
-
-			if(cmd == 5) ps2_key_raw <= 0;
-		end else begin
-		
-			case(cmd)
-				// buttons and switches
-				8'h01: but_sw <= spi_data_in; 
-				8'h02: joystick_0 <= spi_data_in;
-				8'h03: joystick_1 <= spi_data_in;
-//				8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-//				8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
-				// store incoming ps2 mouse bytes 
-				8'h04: begin
-						got_ps2 <= 1;
-						case(byte_cnt)
-							2: ps2_mouse[7:0]   <= spi_data_in;
-							3: ps2_mouse[15:8]  <= spi_data_in;
-							4: ps2_mouse[23:16] <= spi_data_in;
-						endcase 
-						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
-						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
-					end
-
-				// store incoming ps2 keyboard bytes 
-				8'h05: begin
-						got_ps2 <= 1;
-						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
-						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
-						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
-					end
-			
-				8'h15: status[7:0] <= spi_data_in;
-			
-				// send SD config IO -> FPGA
-				// flag that download begins
-				// sd card knows data is config if sd_dout_strobe is asserted
-				// with sd_ack still being inactive (low)
-				8'h19,
-				// send sector IO -> FPGA
-				// flag that download begins
-				8'h17: begin
-						sd_buff_dout <= spi_data_in;
-						b_wr <= 1;
-					end
-
-				// joystick analog
-				8'h1a: begin
-						// first byte is joystick index
-						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
-						else if(byte_cnt == 3) begin
-							// second byte is x axis
-							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
-						end else if(byte_cnt == 4) begin
-							// third byte is y axis
-							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
-								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
-						end
-					end
-
-				// notify image selection
-				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
-
-				// send image info
-				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-
-				// status, 32bit version
-				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
-				default: ;
-			endcase
-		end
-	end
-end
-
-
-///////////////////////////////   PS2   ///////////////////////////////
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-reg clk_ps2;
-always @(negedge clk_sys) begin
-	integer cnt;
-	cnt <= cnt + 1'd1;
-	if(cnt == PS2DIV) begin
-		clk_ps2 <= ~clk_ps2;
-		cnt <= 0;
-	end
-end
-
-// keyboard
-reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_kbd_r_inc <= 0;
-
-		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_kbd_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-				// load tx register from fifo
-				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-				ps2_kbd_r_inc <= 1;
-
-				// reset parity
-				ps2_kbd_parity <= 1;
-
-				// start transmitter
-				ps2_kbd_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_kbd_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
-				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-				if(ps2_kbd_tx_byte[0]) 
-					ps2_kbd_parity <= !ps2_kbd_parity;
-			end
-
-			// transmission of parity
-			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
-
-			// transmission of stop bit
-			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
-
-			// advance state machine
-			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
-				else ps2_kbd_tx_state <= 0;
-		end
-	end
-end
-
-// mouse
-reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge clk_sys) begin
-	reg old_clk;
-	old_clk <= clk_ps2;
-	if(~old_clk & clk_ps2) begin
-		ps2_mouse_r_inc <= 0;
-
-		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
-
-		// transmitter is idle?
-		if(ps2_mouse_tx_state == 0) begin
-			// data in fifo present?
-			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-				// load tx register from fifo
-				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-				ps2_mouse_r_inc <= 1;
-
-				// reset parity
-				ps2_mouse_parity <= 1;
-
-				// start transmitter
-				ps2_mouse_tx_state <= 1;
-
-				// put start bit on data line
-				ps2_mouse_data <= 0;			// start bit is 0
-			end
-		end else begin
-
-			// transmission of 8 data bits
-			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-				if(ps2_mouse_tx_byte[0]) 
-					ps2_mouse_parity <= !ps2_mouse_parity;
-			end
-
-			// transmission of parity
-			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
-
-			// transmission of stop bit
-			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
-
-			// advance state machine
-			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
-				else ps2_mouse_tx_state <= 0;
-		end
-	end
-end
-
-
-///////////////////////////////   DOWNLOADING   ///////////////////////////////
-
-reg  [7:0] data_w;
-reg [24:0] addr_w;
-reg        rclk   = 0;
-
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-
-reg        rdownload = 0;
-
-// data_io has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS2) begin
-	reg  [6:0] sbuf;
-	reg  [7:0] cmd;
-	reg  [4:0] cnt;
-	reg [24:0] addr;
-
-	if(SPI_SS2) cnt <= 0;
-	else begin
-		// don't shift in last bit. It is evaluated directly
-		// when writing to ram
-		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
-
-		// count 0-7 8-15 8-15 ... 
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		// finished command byte
-      if(cnt == 7) cmd <= {sbuf, SPI_DI};
-
-		// prepare/end transmission
-		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
-			// prepare 
-			if(SPI_DI) begin
-				case(ioctl_index[4:0]) 
-							1: addr <= 25'h200000; // TRD buffer  at 2MB
-							2: addr <= 25'h400000; // tape buffer at 4MB 
-					default: addr <= 25'h150000; // boot rom
-				endcase
-				rdownload <= 1; 
-			end else begin
-				addr_w <= addr;
-				rdownload <= 0;
-			end
-		end
-
-		// command 0x54: UIO_FILE_TX
-		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
-			addr_w <= addr;
-			data_w <= {sbuf, SPI_DI};
-			addr <= addr + 1'd1;
-			rclk <= ~rclk;
-		end
-
-      // expose file (menu) index
-      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
-	end
-end
-
-// transfer to ioctl_clk domain.
-// ioctl_index is set before ioctl_download, so it's stable already
-always@(posedge clk_sys) begin
-	reg        rclkD, rclkD2;
-
-	if(ioctl_ce) begin
-		ioctl_download <= rdownload;
-
-		rclkD    <= rclk;
-		rclkD2   <= rclkD;
-		ioctl_wr <= 0;
-
-		if(rclkD != rclkD2) begin
-			ioctl_dout <= data_w;
-			ioctl_addr <= addr_w;
-			ioctl_wr   <= 1;
-		end
-	end
-end
-
-endmodule 
\ No newline at end of file
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/osd.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/osd.v
deleted file mode 100644
index b9181763..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/osd.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input        clk_sys,
-
-	// SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-
-	// VGA signals coming from core
-	input  [5:0] R_in,
-	input  [5:0] G_in,
-	input  [5:0] B_in,
-	input        HSync,
-	input        VSync,
-
-	// VGA signals going to video connector
-	output [5:0] R_out,
-	output [5:0] G_out,
-	output [5:0] B_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH   = 10'd256;
-localparam OSD_HEIGHT  = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg        osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge SPI_SCK, posedge SPI_SS3) begin
-	reg  [4:0] cnt;
-	reg [10:0] bcnt;
-	reg  [7:0] sbuf;
-	reg  [7:0] cmd;
-
-	if(SPI_SS3) begin
-		cnt  <= 0;
-		bcnt <= 0;
-	end else begin
-		sbuf <= {sbuf[6:0], SPI_DI};
-
-		// 0:7 is command, rest payload
-		if(cnt < 15) cnt <= cnt + 1'd1;
-			else cnt <= 8;
-
-		if(cnt == 7) begin
-			cmd <= {sbuf[6:0], SPI_DI};
-
-			// lower three command bits are line address
-			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
-
-			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
-		end
-
-		// command 0x20: OSDCMDWRITE
-		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
-			bcnt <= bcnt + 1'd1;
-		end
-	end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg  [9:0] h_cnt;
-reg  [9:0] hs_low, hs_high;
-wire       hs_pol = hs_high < hs_low;
-wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
-
-// vertical counter
-reg  [9:0] v_cnt;
-reg  [9:0] vs_low, vs_high;
-wire       vs_pol = vs_high < vs_low;
-wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
-
-wire doublescan = (dsp_height>350);
-
-reg ce_pix;
-always @(negedge clk_sys) begin
-	integer cnt = 0;
-	integer pixsz, pixcnt;
-	reg hs;
-
-	cnt <= cnt + 1;
-	hs <= HSync;
-
-	pixcnt <= pixcnt + 1;
-	if(pixcnt == pixsz) pixcnt <= 0;
-	ce_pix <= !pixcnt;
-
-	if(hs && ~HSync) begin
-		cnt    <= 0;
-		pixsz  <= (cnt >> 9) - 1;
-		pixcnt <= 0;
-		ce_pix <= 1;
-	end
-end
-
-always @(posedge clk_sys) begin
-	reg hsD, hsD2;
-	reg vsD, vsD2;
-
-	if(ce_pix) begin
-		// bring hsync into local clock domain
-		hsD <= HSync;
-		hsD2 <= hsD;
-
-		// falling edge of HSync
-		if(!hsD && hsD2) begin
-			h_cnt <= 0;
-			hs_high <= h_cnt;
-		end
-
-		// rising edge of HSync
-		else if(hsD && !hsD2) begin
-			h_cnt <= 0;
-			hs_low <= h_cnt;
-			v_cnt <= v_cnt + 1'd1;
-		end else begin
-			h_cnt <= h_cnt + 1'd1;
-		end
-
-		vsD <= VSync;
-		vsD2 <= vsD;
-
-		// falling edge of VSync
-		if(!vsD && vsD2) begin
-			v_cnt <= 0;
-			vs_high <= v_cnt;
-		end
-
-		// rising edge of VSync
-		else if(vsD && !vsD2) begin
-			v_cnt <= 0;
-			vs_low <= v_cnt;
-		end
-	end
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
-wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
-wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
-wire [9:0] osd_hcnt    = h_cnt - h_osd_start;
-wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
-wire [9:0] osd_hcnt_next  = osd_hcnt + 2'd1;  // one pixel offset for osd pixel
-wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2;  // two pixel offset for osd byte address register
-
-wire osd_de = osd_enable &&
-              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
-              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
-
-reg [10:0] osd_buffer_addr;
-wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
-reg        osd_pixel;
-
-always @(posedge clk_sys) begin
-    if(ce_pix) begin
-		osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
-		                                rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
-										            (doublescan ?  osd_vcnt[7:0]  : {osd_vcnt[6:0], 1'b0})} :
-		                               {doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
-
-		osd_pixel <= rotate[0]  ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
-		                          osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
-	end
-end
-
-assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
-assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
-assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/pll.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/pll.vhd
deleted file mode 100644
index 2822d752..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/pll.vhd	
+++ /dev/null
@@ -1,451 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll 
-
--- ============================================================
--- File Name: pll.vhd
--- Megafunction Name(s):
--- 			altpll
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.1.0 Build 162 10/23/2013 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY pll IS
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
-	);
-END pll;
-
-
-ARCHITECTURE SYN OF pll IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
-	SIGNAL sub_wire1	: STD_LOGIC ;
-	SIGNAL sub_wire2	: STD_LOGIC ;
-	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
-	COMPONENT altpll
-	GENERIC (
-		bandwidth_type		: STRING;
-		clk0_divide_by		: NATURAL;
-		clk0_duty_cycle		: NATURAL;
-		clk0_multiply_by		: NATURAL;
-		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
-		clk3_divide_by		: NATURAL;
-		clk3_duty_cycle		: NATURAL;
-		clk3_multiply_by		: NATURAL;
-		clk3_phase_shift		: STRING;
-		compensate_clock		: STRING;
-		inclk0_input_frequency		: NATURAL;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		operation_mode		: STRING;
-		pll_type		: STRING;
-		port_activeclock		: STRING;
-		port_areset		: STRING;
-		port_clkbad0		: STRING;
-		port_clkbad1		: STRING;
-		port_clkloss		: STRING;
-		port_clkswitch		: STRING;
-		port_configupdate		: STRING;
-		port_fbin		: STRING;
-		port_inclk0		: STRING;
-		port_inclk1		: STRING;
-		port_locked		: STRING;
-		port_pfdena		: STRING;
-		port_phasecounterselect		: STRING;
-		port_phasedone		: STRING;
-		port_phasestep		: STRING;
-		port_phaseupdown		: STRING;
-		port_pllena		: STRING;
-		port_scanaclr		: STRING;
-		port_scanclk		: STRING;
-		port_scanclkena		: STRING;
-		port_scandata		: STRING;
-		port_scandataout		: STRING;
-		port_scandone		: STRING;
-		port_scanread		: STRING;
-		port_scanwrite		: STRING;
-		port_clk0		: STRING;
-		port_clk1		: STRING;
-		port_clk2		: STRING;
-		port_clk3		: STRING;
-		port_clk4		: STRING;
-		port_clk5		: STRING;
-		port_clkena0		: STRING;
-		port_clkena1		: STRING;
-		port_clkena2		: STRING;
-		port_clkena3		: STRING;
-		port_clkena4		: STRING;
-		port_clkena5		: STRING;
-		port_extclk0		: STRING;
-		port_extclk1		: STRING;
-		port_extclk2		: STRING;
-		port_extclk3		: STRING;
-		width_clock		: NATURAL
-	);
-	PORT (
-			areset	: IN STD_LOGIC ;
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire2    <= sub_wire0(3);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
-	c3    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
-
-	altpll_component : altpll
-	GENERIC MAP (
-		bandwidth_type => "AUTO",
-		clk0_divide_by => 9,
-		clk0_duty_cycle => 50,
-		clk0_multiply_by => 8,
-		clk0_phase_shift => "0",
-		clk1_divide_by => 3,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 2,
-		clk1_phase_shift => "0",
-		clk2_divide_by => 9,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 4,
-		clk2_phase_shift => "0",
-		clk3_divide_by => 9,
-		clk3_duty_cycle => 50,
-		clk3_multiply_by => 2,
-		clk3_phase_shift => "0",
-		compensate_clock => "CLK0",
-		inclk0_input_frequency => 37037,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "CBX_MODULE_PREFIX=pll",
-		lpm_type => "altpll",
-		operation_mode => "NORMAL",
-		pll_type => "AUTO",
-		port_activeclock => "PORT_UNUSED",
-		port_areset => "PORT_USED",
-		port_clkbad0 => "PORT_UNUSED",
-		port_clkbad1 => "PORT_UNUSED",
-		port_clkloss => "PORT_UNUSED",
-		port_clkswitch => "PORT_UNUSED",
-		port_configupdate => "PORT_UNUSED",
-		port_fbin => "PORT_UNUSED",
-		port_inclk0 => "PORT_USED",
-		port_inclk1 => "PORT_UNUSED",
-		port_locked => "PORT_UNUSED",
-		port_pfdena => "PORT_UNUSED",
-		port_phasecounterselect => "PORT_UNUSED",
-		port_phasedone => "PORT_UNUSED",
-		port_phasestep => "PORT_UNUSED",
-		port_phaseupdown => "PORT_UNUSED",
-		port_pllena => "PORT_UNUSED",
-		port_scanaclr => "PORT_UNUSED",
-		port_scanclk => "PORT_UNUSED",
-		port_scanclkena => "PORT_UNUSED",
-		port_scandata => "PORT_UNUSED",
-		port_scandataout => "PORT_UNUSED",
-		port_scandone => "PORT_UNUSED",
-		port_scanread => "PORT_UNUSED",
-		port_scanwrite => "PORT_UNUSED",
-		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
-		port_clk3 => "PORT_USED",
-		port_clk4 => "PORT_UNUSED",
-		port_clk5 => "PORT_UNUSED",
-		port_clkena0 => "PORT_UNUSED",
-		port_clkena1 => "PORT_UNUSED",
-		port_clkena2 => "PORT_UNUSED",
-		port_clkena3 => "PORT_UNUSED",
-		port_clkena4 => "PORT_UNUSED",
-		port_clkena5 => "PORT_UNUSED",
-		port_extclk0 => "PORT_UNUSED",
-		port_extclk1 => "PORT_UNUSED",
-		port_extclk2 => "PORT_UNUSED",
-		port_extclk3 => "PORT_UNUSED",
-		width_clock => 5
-	)
-	PORT MAP (
-		areset => areset,
-		inclk => sub_wire6,
-		clk => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
--- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
--- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
--- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
--- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/scandoubler.v b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/scandoubler.v
deleted file mode 100644
index 36e71ed2..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/scandoubler.v	
+++ /dev/null
@@ -1,194 +0,0 @@
-//
-// scandoubler.v
-// 
-// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
-// Copyright (c) 2017 Sorgelig
-// 
-// This source file is free software: you can redistribute it and/or modify 
-// it under the terms of the GNU General Public License as published 
-// by the Free Software Foundation, either version 3 of the License, or 
-// (at your option) any later version. 
-// 
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-// 
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
-
-// TODO: Delay vsync one line
-
-module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
-(
-	// system interface
-	input             clk_sys,
-	input             ce_pix,
-	input             ce_pix_actual,
-
-	input             hq2x,
-
-	// shifter video interface
-	input             hs_in,
-	input             vs_in,
-	input             line_start,
-
-	input  [DWIDTH:0] r_in,
-	input  [DWIDTH:0] g_in,
-	input  [DWIDTH:0] b_in,
-	input             mono,
-
-	// output interface
-	output reg        hs_out,
-	output            vs_out,
-	output [DWIDTH:0] r_out,
-	output [DWIDTH:0] g_out,
-	output [DWIDTH:0] b_out
-);
-
-`define BITS_TO_FIT(N) ( \
-     N <=   2 ? 0 : \
-     N <=   4 ? 1 : \
-     N <=   8 ? 2 : \
-     N <=  16 ? 3 : \
-     N <=  32 ? 4 : \
-     N <=  64 ? 5 : \
-     N <= 128 ? 6 : \
-     N <= 256 ? 7 : \
-     N <= 512 ? 8 : \
-     N <=1024 ? 9 : 10 )
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-assign vs_out = vs_in;
-
-reg  [2:0] phase;
-reg  [2:0] ce_div;
-reg  [7:0] pix_len = 0;
-wire [7:0] pl = pix_len + 1'b1;
-
-reg ce_x1, ce_x4;
-reg req_line_reset;
-wire ls_in = hs_in | line_start;
-always @(negedge clk_sys) begin
-	reg old_ce;
-	reg [2:0] ce_cnt;
-
-	reg [7:0] pixsz2, pixsz4 = 0;
-
-	old_ce <= ce_pix;
-	if(~&pix_len) pix_len <= pix_len + 1'd1;
-
-	ce_x4 <= 0;
-	ce_x1 <= 0;
-
-	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
-	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
-		phase <= phase + 1'd1;
-		ce_x4 <= 1;
-	end
-
-	if(~old_ce & ce_pix) begin
-		pixsz2 <= {1'b0,  pl[7:1]};
-		pixsz4 <= {2'b00, pl[7:2]};
-		ce_x1 <= 1;
-		ce_x4 <= 1;
-		pix_len <= 0;
-		phase <= phase + 1'd1;
-
-		ce_cnt <= ce_cnt + 1'd1;
-		if(ce_pix_actual) begin
-			phase <= 0;
-			ce_div <= ce_cnt + 1'd1;
-			ce_cnt <= 0;
-			req_line_reset <= 0;
-		end
-
-		if(ls_in) req_line_reset <= 1;
-	end
-end
-
-reg ce_sd;
-always @(*) begin
-	case(ce_div)
-		2: ce_sd = !phase[0];
-		4: ce_sd = !phase[1:0];
-		default: ce_sd <= 1;
-	endcase
-end
-
-localparam AWIDTH = `BITS_TO_FIT(LENGTH);
-Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
-(
-	.clk(clk_sys),
-	.ce_x4(ce_x4 & ce_sd),
-	.inputpixel({b_in,g_in,r_in}),
-	.mono(mono),
-	.disable_hq2x(~hq2x),
-	.reset_frame(vs_in),
-	.reset_line(req_line_reset),
-	.read_y(sd_line),
-	.read_x(sd_h_actual),
-	.outpixel({b_out,g_out,r_out})
-);
-
-reg [10:0] sd_h_actual;
-always @(*) begin
-	case(ce_div)
-		2: sd_h_actual = sd_h[10:1];
-		4: sd_h_actual = sd_h[10:2];
-		default: sd_h_actual = sd_h;
-	endcase
-end
-
-reg [10:0] sd_h;
-reg  [1:0] sd_line;
-always @(posedge clk_sys) begin
-
-	reg [11:0] hs_max,hs_rise,hs_ls;
-	reg [10:0] hcnt;
-	reg [11:0] sd_hcnt;
-
-	reg hs, hs2, vs, ls;
-
-	if(ce_x1) begin
-		hs <= hs_in;
-		ls <= ls_in;
-
-		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
-
-		// falling edge of hsync indicates start of line
-		if(hs && !hs_in) begin
-			hs_max <= {hcnt,1'b1};
-			hcnt <= 0;
-			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
-		end else begin
-			hcnt <= hcnt + 1'd1;
-		end
-
-		// save position of rising edge
-		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
-
-		vs <= vs_in;
-		if(vs && ~vs_in) sd_line <= 0;
-	end
-
-	if(ce_x4) begin
-		hs2 <= hs_in;
-
-		// output counter synchronous to input and at twice the rate
-		sd_hcnt <= sd_hcnt + 1'd1;
-		sd_h    <= sd_h    + 1'd1;
-		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
-		if(sd_hcnt == hs_max) sd_hcnt <= 0;
-
-		// replicate horizontal sync at twice the speed
-		if(sd_hcnt == hs_max)  hs_out <= 0;
-		if(sd_hcnt == hs_rise) hs_out <= 1;
-
-		if(sd_hcnt == hs_ls)   sd_h    <= 0;
-		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
-	end
-end
-
-endmodule
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/sine_package.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/sine_package.vhd
deleted file mode 100644
index 473caa04..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/sine_package.vhd	
+++ /dev/null
@@ -1,152 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-package sine_package is
-
-	subtype table_value_type is integer range 0 to 16383;
-	subtype table_index_type is std_logic_vector( 6 downto 0 );
-
-	function get_table_value (table_index: table_index_type) return table_value_type;
-
-end;
-
-package body sine_package is
-
-	function get_table_value (table_index: table_index_type) return table_value_type is
-		variable table_value: table_value_type;
-	begin
-		case table_index is
-			when "0000000" =>	table_value := 101;
-			when "0000001" =>	table_value := 302;
-			when "0000010" =>	table_value := 503;
-			when "0000011" =>	table_value := 703;
-			when "0000100" =>	table_value := 904;
-			when "0000101" =>	table_value := 1105;
-			when "0000110" =>	table_value := 1305;
-			when "0000111" =>	table_value := 1506;
-			when "0001000" =>	table_value := 1706;
-			when "0001001" =>	table_value := 1906;
-			when "0001010" =>	table_value := 2105;
-			when "0001011" =>	table_value := 2304;
-			when "0001100" =>	table_value := 2503;
-			when "0001101" =>	table_value := 2702;
-			when "0001110" =>	table_value := 2900;
-			when "0001111" =>	table_value := 3098;
-			when "0010000" =>	table_value := 3295;
-			when "0010001" =>	table_value := 3491;
-			when "0010010" =>	table_value := 3688;
-			when "0010011" =>	table_value := 3883;
-			when "0010100" =>	table_value := 4078;
-			when "0010101" =>	table_value := 4273;
-			when "0010110" =>	table_value := 4466;
-			when "0010111" =>	table_value := 4659;
-			when "0011000" =>	table_value := 4852;
-			when "0011001" =>	table_value := 5044;
-			when "0011010" =>	table_value := 5234;
-			when "0011011" =>	table_value := 5425;
-			when "0011100" =>	table_value := 5614;
-			when "0011101" =>	table_value := 5802;
-			when "0011110" =>	table_value := 5990;
-			when "0011111" =>	table_value := 6177;
-			when "0100000" =>	table_value := 6362;
-			when "0100001" =>	table_value := 6547;
-			when "0100010" =>	table_value := 6731;
-			when "0100011" =>	table_value := 6914;
-			when "0100100" =>	table_value := 7095;
-			when "0100101" =>	table_value := 7276;
-			when "0100110" =>	table_value := 7456;
-			when "0100111" =>	table_value := 7634;
-			when "0101000" =>	table_value := 7811;
-			when "0101001" =>	table_value := 7988;
-			when "0101010" =>	table_value := 8162;
-			when "0101011" =>	table_value := 8336;
-			when "0101100" =>	table_value := 8509;
-			when "0101101" =>	table_value := 8680;
-			when "0101110" =>	table_value := 8850;
-			when "0101111" =>	table_value := 9018;
-			when "0110000" =>	table_value := 9185;
-			when "0110001" =>	table_value := 9351;
-			when "0110010" =>	table_value := 9515;
-			when "0110011" =>	table_value := 9678;
-			when "0110100" =>	table_value := 9840;
-			when "0110101" =>	table_value := 10000;
-			when "0110110" =>	table_value := 10158;
-			when "0110111" =>	table_value := 10315;
-			when "0111000" =>	table_value := 10471;
-			when "0111001" =>	table_value := 10625;
-			when "0111010" =>	table_value := 10777;
-			when "0111011" =>	table_value := 10927;
-			when "0111100" =>	table_value := 11076;
-			when "0111101" =>	table_value := 11224;
-			when "0111110" =>	table_value := 11369;
-			when "0111111" =>	table_value := 11513;
-			when "1000000" =>	table_value := 11655;
-			when "1000001" =>	table_value := 11796;
-			when "1000010" =>	table_value := 11934;
-			when "1000011" =>	table_value := 12071;
-			when "1000100" =>	table_value := 12206;
-			when "1000101" =>	table_value := 12339;
-			when "1000110" =>	table_value := 12471;
-			when "1000111" =>	table_value := 12600;
-			when "1001000" =>	table_value := 12728;
-			when "1001001" =>	table_value := 12853;
-			when "1001010" =>	table_value := 12977;
-			when "1001011" =>	table_value := 13099;
-			when "1001100" =>	table_value := 13219;
-			when "1001101" =>	table_value := 13336;
-			when "1001110" =>	table_value := 13452;
-			when "1001111" =>	table_value := 13566;
-			when "1010000" =>	table_value := 13678;
-			when "1010001" =>	table_value := 13787;
-			when "1010010" =>	table_value := 13895;
-			when "1010011" =>	table_value := 14000;
-			when "1010100" =>	table_value := 14104;
-			when "1010101" =>	table_value := 14205;
-			when "1010110" =>	table_value := 14304;
-			when "1010111" =>	table_value := 14401;
-			when "1011000" =>	table_value := 14496;
-			when "1011001" =>	table_value := 14588;
-			when "1011010" =>	table_value := 14679;
-			when "1011011" =>	table_value := 14767;
-			when "1011100" =>	table_value := 14853;
-			when "1011101" =>	table_value := 14936;
-			when "1011110" =>	table_value := 15018;
-			when "1011111" =>	table_value := 15097;
-			when "1100000" =>	table_value := 15174;
-			when "1100001" =>	table_value := 15249;
-			when "1100010" =>	table_value := 15321;
-			when "1100011" =>	table_value := 15391;
-			when "1100100" =>	table_value := 15459;
-			when "1100101" =>	table_value := 15524;
-			when "1100110" =>	table_value := 15587;
-			when "1100111" =>	table_value := 15648;
-			when "1101000" =>	table_value := 15706;
-			when "1101001" =>	table_value := 15762;
-			when "1101010" =>	table_value := 15816;
-			when "1101011" =>	table_value := 15867;
-			when "1101100" =>	table_value := 15916;
-			when "1101101" =>	table_value := 15963;
-			when "1101110" =>	table_value := 16007;
-			when "1101111" =>	table_value := 16048;
-			when "1110000" =>	table_value := 16088;
-			when "1110001" =>	table_value := 16124;
-			when "1110010" =>	table_value := 16159;
-			when "1110011" =>	table_value := 16191;
-			when "1110100" =>	table_value := 16220;
-			when "1110101" =>	table_value := 16247;
-			when "1110110" =>	table_value := 16272;
-			when "1110111" =>	table_value := 16294;
-			when "1111000" =>	table_value := 16314;
-			when "1111001" =>	table_value := 16331;
-			when "1111010" =>	table_value := 16346;
-			when "1111011" =>	table_value := 16358;
-			when "1111100" =>	table_value := 16368;
-			when "1111101" =>	table_value := 16375;
-			when "1111110" =>	table_value := 16380;
-			when "1111111" =>	table_value := 16383;
-			when others => null;
-		end case;
-		return table_value;
-	end;
-
-end;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/spram.vhd b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/spram.vhd
deleted file mode 100644
index ad6b58b5..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/spram.vhd	
+++ /dev/null
@@ -1,55 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY spram IS
-	generic (
-		 addr_width_g : integer := 8;
-		 data_width_g : integer := 8
-	); 
-	PORT
-	(
-		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
-		clken		: IN STD_LOGIC  := '1';
-		clock		: IN STD_LOGIC  := '1';
-		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-BEGIN
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "NORMAL",
-		clock_enable_output_a => "BYPASS",
-		intended_device_family => "Cyclone V",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 2**addr_width_g,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => "UNREGISTERED",
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => addr_width_g,
-		width_a => data_width_g,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => address,
-		clock0 => clock,
-		clocken0 => clken,
-		data_a => data,
-		wren_a => wren,
-		q_a => q
-	);
-
-
-
-END SYN;
diff --git a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/video_mixer.sv b/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/video_mixer.sv
deleted file mode 100644
index 79d8ca03..00000000
--- a/Arcade_MiST/Galaxian Hardware/Z80 Based/WarOfBugs_MiST/rtl/video_mixer.sv	
+++ /dev/null
@@ -1,243 +0,0 @@
-//
-//
-// Copyright (c) 2017 Sorgelig
-//
-// This program is GPL Licensed. See COPYING for the full license.
-//
-//
-////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1ns / 1ps
-
-//
-// LINE_LENGTH: Length of  display line in pixels
-//              Usually it's length from HSync to HSync.
-//              May be less if line_start is used.
-//
-// HALF_DEPTH:  If =1 then color dept is 3 bits per component
-//              For half depth 6 bits monochrome is available with
-//              mono signal enabled and color = {G, R}
-
-module video_mixer
-#(
-	parameter LINE_LENGTH  = 480,
-	parameter HALF_DEPTH   = 1,
-
-	parameter OSD_COLOR    = 3'd4,
-	parameter OSD_X_OFFSET = 10'd0,
-	parameter OSD_Y_OFFSET = 10'd0
-)
-(
-	// master clock
-	// it should be multiple by (ce_pix*4).
-	input        clk_sys,
-	
-	// Pixel clock or clock_enable (both are accepted).
-	input        ce_pix,
-
-	// Some systems have multiple resolutions.
-	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
-	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
-	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
-	input        ce_pix_actual,
-
-	// OSD SPI interface
-	input        SPI_SCK,
-	input        SPI_SS3,
-	input        SPI_DI,
-
-	// scanlines (00-none 01-25% 10-50% 11-75%)
-	input  [1:0] scanlines,
-
-	// 0 = HVSync 31KHz, 1 = CSync 15KHz
-	input        scandoublerD,
-
-	// High quality 2x scaling
-	input        hq2x,
-
-	// YPbPr always uses composite sync
-	input        ypbpr,
-
-	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
-	input        ypbpr_full,
-	input  [1:0] rotate, //[0] - rotate [1] - left or right
-	// color
-	input [DWIDTH:0] R,
-	input [DWIDTH:0] G,
-	input [DWIDTH:0] B,
-
-	// Monochrome mode (for HALF_DEPTH only)
-	input            mono,
-
-	// interlace sync. Positive pulses.
-	input        HSync,
-	input        VSync,
-
-	// Falling of this signal means start of informative part of line.
-	// It can be horizontal blank signal.
-	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
-	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
-	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
-	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
-	// before first informative pixel.
-	input        line_start,
-
-	// MiST video output signals
-	output [5:0] VGA_R,
-	output [5:0] VGA_G,
-	output [5:0] VGA_B,
-	output       VGA_VS,
-	output       VGA_HS
-);
-
-localparam DWIDTH = HALF_DEPTH ? 2 : 5;
-
-wire [DWIDTH:0] R_sd;
-wire [DWIDTH:0] G_sd;
-wire [DWIDTH:0] B_sd;
-wire hs_sd, vs_sd;
-
-scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
-(
-	.*,
-	.hs_in(HSync),
-	.vs_in(VSync),
-	.r_in(R),
-	.g_in(G),
-	.b_in(B),
-
-	.hs_out(hs_sd),
-	.vs_out(vs_sd),
-	.r_out(R_sd),
-	.g_out(G_sd),
-	.b_out(B_sd)
-);
-
-wire [DWIDTH:0] rt  = (scandoublerD ? R : R_sd);
-wire [DWIDTH:0] gt  = (scandoublerD ? G : G_sd);
-wire [DWIDTH:0] bt  = (scandoublerD ? B : B_sd);
-
-generate
-	if(HALF_DEPTH) begin
-		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
-		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
-		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
-	end else begin
-		wire [5:0] r  = rt;
-		wire [5:0] g  = gt;
-		wire [5:0] b  = bt;
-	end
-endgenerate
-
-wire       hs = (scandoublerD ? HSync : hs_sd);
-wire       vs = (scandoublerD ? VSync : vs_sd);
-
-reg scanline = 0;
-always @(posedge clk_sys) begin
-	reg old_hs, old_vs;
-	
-	old_hs <= hs;
-	old_vs <= vs;
-	
-	if(old_hs && ~hs) scanline <= ~scanline;
-	if(old_vs && ~vs) scanline <= 0;
-end
-
-wire [5:0] r_out, g_out, b_out;
-always @(*) begin
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
-			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
-			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
-		end
-
-		2: begin // reduce 50% = 1/2
-			r_out = {1'b0, r[5:1]};
-			g_out = {1'b0, g[5:1]};
-			b_out = {1'b0, b[5:1]};
-		end
-
-		3: begin // reduce 75% = 1/4
-			r_out = {2'b00, r[5:2]};
-			g_out = {2'b00, g[5:2]};
-			b_out = {2'b00, b[5:2]};
-		end
-
-		default: begin
-			r_out = r;
-			g_out = g;
-			b_out = b;
-		end
-	endcase
-end
-
-wire [5:0] red, green, blue;
-osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
-(
-	.*,
-
-	.R_in(r_out),
-	.G_in(g_out),
-	.B_in(b_out),
-	.HSync(hs),
-	.VSync(vs),
-	.rotate(rotate),
-
-	.R_out(red),
-	.G_out(green),
-	.B_out(blue)
-);
-
-wire [5:0] yuv_full[225] = '{
-  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
-  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
-  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
-  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
-  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
-  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
-  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
-  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
-  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
-  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
-  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
-  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
-  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
-  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
-  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
-  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
-  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
-  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
-  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
-  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
-  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
-  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
-  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
-  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
-  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
-  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
-  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
-  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
-  6'd63
-};
-
-// http://marsee101.blog19.fc2.com/blog-entry-2311.html
-// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
-// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
-// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
-
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
-
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
-
-assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
-assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
-assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
-assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
-assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
-
-endmodule